drivers/event/dpaa2/dpaa2_eventdev.h

   1 /*
   2  * SPDX-License-Identifier: BSD-3-Clause
   3  *
   4  *   Copyright 2017 NXP
   5  *
   6  */
   7
   8 #ifndef __DPAA2_EVENTDEV_H__
   9 #define __DPAA2_EVENTDEV_H__
  10
  11 #include <rte_eventdev_pmd.h>
  12 #include <rte_eventdev_pmd_vdev.h>
  13 #include <rte_atomic.h>
  14 #include <mc/fsl_dpcon.h>
  15 #include <mc/fsl_mc_sys.h>
  16
  17 #define EVENTDEV_NAME_DPAA2_PMD         event_dpaa2
  18
  19 #define DPAA2_EVENT_DEFAULT_DPCI_PRIO 0
  20
  21 #define DPAA2_EVENT_MAX_QUEUES                  16
  22 #define DPAA2_EVENT_MIN_DEQUEUE_TIMEOUT         1
  23 #define DPAA2_EVENT_MAX_DEQUEUE_TIMEOUT         (UINT32_MAX - 1)
  24 #define DPAA2_EVENT_PORT_DEQUEUE_TIMEOUT_NS     100UL
  25 #define DPAA2_EVENT_MAX_QUEUE_FLOWS             2048
  26 #define DPAA2_EVENT_MAX_QUEUE_PRIORITY_LEVELS   8
  27 #define DPAA2_EVENT_MAX_EVENT_PRIORITY_LEVELS   0
  28 #define DPAA2_EVENT_MAX_PORT_DEQUEUE_DEPTH      8
  29 #define DPAA2_EVENT_MAX_PORT_ENQUEUE_DEPTH      8
  30 #define DPAA2_EVENT_MAX_NUM_EVENTS              (INT32_MAX - 1)
  31
  32 #define DPAA2_EVENT_QUEUE_ATOMIC_FLOWS          2048
  33 #define DPAA2_EVENT_QUEUE_ORDER_SEQUENCES       2048
  34
  35 enum {
  36         DPAA2_EVENT_DPCI_PARALLEL_QUEUE,
  37         DPAA2_EVENT_DPCI_ATOMIC_QUEUE,
  38         DPAA2_EVENT_DPCI_MAX_QUEUES
  39 };
  40
  41 #define RTE_EVENT_ETH_RX_ADAPTER_DPAA2_CAP \
  42                 (RTE_EVENT_ETH_RX_ADAPTER_CAP_INTERNAL_PORT | \
  43                 RTE_EVENT_ETH_RX_ADAPTER_CAP_MULTI_EVENTQ | \
  44                 RTE_EVENT_ETH_RX_ADAPTER_CAP_OVERRIDE_FLOW_ID)
  45 /**< Ethernet Rx adapter cap to return If the packet transfers from
  46  * the ethdev to eventdev with DPAA2 devices.
  47  */
  48
  49 struct dpaa2_dpcon_dev {
  50         TAILQ_ENTRY(dpaa2_dpcon_dev) next;
  51         struct fsl_mc_io dpcon;
  52         uint16_t token;
  53         rte_atomic16_t in_use;
  54         uint32_t dpcon_id;
  55         uint16_t qbman_ch_id;
  56         uint8_t num_priorities;
  57         uint8_t channel_index;
  58 };
  59
  60 struct dpaa2_eventq {
  61         /* DPcon device */
  62         struct dpaa2_dpcon_dev *dpcon;
  63         /* Attached DPCI device */
  64         struct dpaa2_dpci_dev *dpci;
  65         /* Mapped event port */
  66         struct dpaa2_io_portal_t *event_port;
  67         /* Configuration provided by the user */
  68         uint32_t event_queue_cfg;
  69         uint32_t event_queue_id;
  70 };
  71
  72 struct dpaa2_port {
  73         struct dpaa2_eventq evq_info[DPAA2_EVENT_MAX_QUEUES];
  74         uint8_t num_linked_evq;
  75         uint8_t is_port_linked;
  76         uint64_t timeout_us;
  77 };
  78
  79 struct dpaa2_eventdev {
  80         struct dpaa2_eventq evq_info[DPAA2_EVENT_MAX_QUEUES];
  81         uint32_t dequeue_timeout_ns;
  82         uint8_t max_event_queues;
  83         uint8_t nb_event_queues;
  84         uint8_t nb_event_ports;
  85         uint8_t resvd_1;
  86         uint32_t nb_event_queue_flows;
  87         uint32_t nb_event_port_dequeue_depth;
  88         uint32_t nb_event_port_enqueue_depth;
  89         uint32_t event_dev_cfg;
  90 };
  91
  92 struct dpaa2_dpcon_dev *rte_dpaa2_alloc_dpcon_dev(void);
  93 void rte_dpaa2_free_dpcon_dev(struct dpaa2_dpcon_dev *dpcon);
  94
  95 #endif /* __DPAA2_EVENTDEV_H__ */