4 * Copyright (C) Cavium networks Ltd. 2017.
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
10 * * Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * * Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in
14 * the documentation and/or other materials provided with the
16 * * Neither the name of Cavium networks nor the names of its
17 * contributors may be used to endorse or promote products derived
18 * from this software without specific prior written permission.
20 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
21 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
22 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
23 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
24 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
25 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
26 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
27 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
28 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
30 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
35 #include <rte_common.h>
36 #include <rte_debug.h>
39 #include <rte_lcore.h>
41 #include <rte_malloc.h>
42 #include <rte_memory.h>
43 #include <rte_memzone.h>
46 #include "ssovf_evdev.h"
48 /* SSOPF Mailbox messages */
50 struct ssovf_mbox_dev_info {
51 uint64_t min_deq_timeout_ns;
52 uint64_t max_deq_timeout_ns;
53 uint32_t max_num_events;
57 ssovf_mbox_dev_info(struct ssovf_mbox_dev_info *info)
59 struct octeontx_mbox_hdr hdr = {0};
60 uint16_t len = sizeof(struct ssovf_mbox_dev_info);
62 hdr.coproc = SSO_COPROC;
63 hdr.msg = SSO_GET_DEV_INFO;
67 return octeontx_ssovf_mbox_send(&hdr, NULL, 0, info, len);
70 struct ssovf_mbox_getwork_wait {
75 ssovf_mbox_getwork_tmo_set(uint32_t timeout_ns)
77 struct octeontx_mbox_hdr hdr = {0};
78 struct ssovf_mbox_getwork_wait tmo_set;
79 uint16_t len = sizeof(struct ssovf_mbox_getwork_wait);
82 hdr.coproc = SSO_COPROC;
83 hdr.msg = SSO_SET_GETWORK_WAIT;
86 tmo_set.wait_ns = timeout_ns;
87 ret = octeontx_ssovf_mbox_send(&hdr, &tmo_set, len, NULL, 0);
89 ssovf_log_err("Failed to set getwork timeout(%d)", ret);
94 struct ssovf_mbox_grp_pri {
95 uint8_t wgt_left; /* Read only */
102 ssovf_mbox_priority_set(uint8_t queue, uint8_t prio)
104 struct octeontx_mbox_hdr hdr = {0};
105 struct ssovf_mbox_grp_pri grp;
106 uint16_t len = sizeof(struct ssovf_mbox_grp_pri);
109 hdr.coproc = SSO_COPROC;
110 hdr.msg = SSO_GRP_SET_PRIORITY;
115 grp.priority = prio / 32; /* Normalize to 0 to 7 */
117 ret = octeontx_ssovf_mbox_send(&hdr, &grp, len, NULL, 0);
119 ssovf_log_err("Failed to set grp=%d prio=%d", queue, prio);
124 struct ssovf_mbox_convert_ns_getworks_iter {
126 uint32_t getwork_iter;/* Get_work iterations for the given wait_ns */
130 ssovf_mbox_timeout_ticks(uint64_t ns, uint64_t *tmo_ticks)
132 struct octeontx_mbox_hdr hdr = {0};
133 struct ssovf_mbox_convert_ns_getworks_iter ns2iter;
134 uint16_t len = sizeof(ns2iter);
137 hdr.coproc = SSO_COPROC;
138 hdr.msg = SSO_CONVERT_NS_GETWORK_ITER;
141 memset(&ns2iter, 0, len);
142 ns2iter.wait_ns = ns;
143 ret = octeontx_ssovf_mbox_send(&hdr, &ns2iter, len, &ns2iter, len);
144 if (ret < 0 || (ret != len)) {
145 ssovf_log_err("Failed to get tmo ticks ns=%"PRId64"", ns);
149 *tmo_ticks = ns2iter.getwork_iter;
154 ssovf_fastpath_fns_set(struct rte_eventdev *dev)
156 struct ssovf_evdev *edev = ssovf_pmd_priv(dev);
158 dev->schedule = NULL;
159 dev->enqueue = ssows_enq;
160 dev->enqueue_burst = ssows_enq_burst;
161 dev->dequeue = ssows_deq;
162 dev->dequeue_burst = ssows_deq_burst;
164 if (edev->is_timeout_deq) {
165 dev->dequeue = ssows_deq_timeout;
166 dev->dequeue_burst = ssows_deq_timeout_burst;
171 ssovf_info_get(struct rte_eventdev *dev, struct rte_event_dev_info *dev_info)
173 struct ssovf_evdev *edev = ssovf_pmd_priv(dev);
175 dev_info->driver_name = RTE_STR(EVENTDEV_NAME_OCTEONTX_PMD);
176 dev_info->min_dequeue_timeout_ns = edev->min_deq_timeout_ns;
177 dev_info->max_dequeue_timeout_ns = edev->max_deq_timeout_ns;
178 dev_info->max_event_queues = edev->max_event_queues;
179 dev_info->max_event_queue_flows = (1ULL << 20);
180 dev_info->max_event_queue_priority_levels = 8;
181 dev_info->max_event_priority_levels = 1;
182 dev_info->max_event_ports = edev->max_event_ports;
183 dev_info->max_event_port_dequeue_depth = 1;
184 dev_info->max_event_port_enqueue_depth = 1;
185 dev_info->max_num_events = edev->max_num_events;
186 dev_info->event_dev_cap = RTE_EVENT_DEV_CAP_QUEUE_QOS |
187 RTE_EVENT_DEV_CAP_DISTRIBUTED_SCHED |
188 RTE_EVENT_DEV_CAP_QUEUE_ALL_TYPES;
192 ssovf_configure(const struct rte_eventdev *dev)
194 struct rte_event_dev_config *conf = &dev->data->dev_conf;
195 struct ssovf_evdev *edev = ssovf_pmd_priv(dev);
199 deq_tmo_ns = conf->dequeue_timeout_ns;
201 if (conf->event_dev_cfg & RTE_EVENT_DEV_CFG_PER_DEQUEUE_TIMEOUT) {
202 edev->is_timeout_deq = 1;
203 deq_tmo_ns = edev->min_deq_timeout_ns;
205 edev->nb_event_queues = conf->nb_event_queues;
206 edev->nb_event_ports = conf->nb_event_ports;
208 return ssovf_mbox_getwork_tmo_set(deq_tmo_ns);
212 ssovf_queue_def_conf(struct rte_eventdev *dev, uint8_t queue_id,
213 struct rte_event_queue_conf *queue_conf)
216 RTE_SET_USED(queue_id);
218 queue_conf->nb_atomic_flows = (1ULL << 20);
219 queue_conf->nb_atomic_order_sequences = (1ULL << 20);
220 queue_conf->event_queue_cfg = RTE_EVENT_QUEUE_CFG_ALL_TYPES;
221 queue_conf->priority = RTE_EVENT_DEV_PRIORITY_NORMAL;
225 ssovf_queue_release(struct rte_eventdev *dev, uint8_t queue_id)
228 RTE_SET_USED(queue_id);
232 ssovf_queue_setup(struct rte_eventdev *dev, uint8_t queue_id,
233 const struct rte_event_queue_conf *queue_conf)
236 ssovf_func_trace("queue=%d prio=%d", queue_id, queue_conf->priority);
238 return ssovf_mbox_priority_set(queue_id, queue_conf->priority);
242 ssovf_port_def_conf(struct rte_eventdev *dev, uint8_t port_id,
243 struct rte_event_port_conf *port_conf)
245 struct ssovf_evdev *edev = ssovf_pmd_priv(dev);
247 RTE_SET_USED(port_id);
248 port_conf->new_event_threshold = edev->max_num_events;
249 port_conf->dequeue_depth = 1;
250 port_conf->enqueue_depth = 1;
254 ssovf_port_release(void *port)
260 ssovf_port_setup(struct rte_eventdev *dev, uint8_t port_id,
261 const struct rte_event_port_conf *port_conf)
266 struct ssovf_evdev *edev = ssovf_pmd_priv(dev);
268 ssovf_func_trace("port=%d", port_id);
269 RTE_SET_USED(port_conf);
271 /* Free memory prior to re-allocation if needed */
272 if (dev->data->ports[port_id] != NULL) {
273 ssovf_port_release(dev->data->ports[port_id]);
274 dev->data->ports[port_id] = NULL;
277 /* Allocate event port memory */
278 ws = rte_zmalloc_socket("eventdev ssows",
279 sizeof(struct ssows), RTE_CACHE_LINE_SIZE,
280 dev->data->socket_id);
282 ssovf_log_err("Failed to alloc memory for port=%d", port_id);
286 ws->base = octeontx_ssovf_bar(OCTEONTX_SSO_HWS, port_id, 0);
287 if (ws->base == NULL) {
289 ssovf_log_err("Failed to get hws base addr port=%d", port_id);
293 reg_off = SSOW_VHWS_OP_GET_WORK0;
294 reg_off |= 1 << 4; /* Index_ggrp_mask (Use maskset zero) */
295 reg_off |= 1 << 16; /* Wait */
296 ws->getwork = ws->base + reg_off;
299 for (q = 0; q < edev->nb_event_queues; q++) {
300 ws->grps[q] = octeontx_ssovf_bar(OCTEONTX_SSO_GROUP, q, 2);
301 if (ws->grps[q] == NULL) {
303 ssovf_log_err("Failed to get grp%d base addr", q);
308 dev->data->ports[port_id] = ws;
309 ssovf_log_dbg("port=%d ws=%p", port_id, ws);
314 ssovf_port_link(struct rte_eventdev *dev, void *port, const uint8_t queues[],
315 const uint8_t priorities[], uint16_t nb_links)
319 struct ssows *ws = port;
321 ssovf_func_trace("port=%d nb_links=%d", ws->port, nb_links);
323 RTE_SET_USED(priorities);
325 for (link = 0; link < nb_links; link++) {
327 val |= (1ULL << 24); /* Set membership */
328 ssovf_write64(val, ws->base + SSOW_VHWS_GRPMSK_CHGX(0));
330 return (int)nb_links;
334 ssovf_port_unlink(struct rte_eventdev *dev, void *port, uint8_t queues[],
339 struct ssows *ws = port;
341 ssovf_func_trace("port=%d nb_links=%d", ws->port, nb_unlinks);
344 for (unlink = 0; unlink < nb_unlinks; unlink++) {
345 val = queues[unlink];
346 val &= ~(1ULL << 24); /* Clear membership */
347 ssovf_write64(val, ws->base + SSOW_VHWS_GRPMSK_CHGX(0));
349 return (int)nb_unlinks;
353 ssovf_timeout_ticks(struct rte_eventdev *dev, uint64_t ns, uint64_t *tmo_ticks)
357 return ssovf_mbox_timeout_ticks(ns, tmo_ticks);
361 ssows_dump(struct ssows *ws, FILE *f)
363 uint8_t *base = ws->base;
366 fprintf(f, "\t---------------port%d---------------\n", ws->port);
367 val = ssovf_read64(base + SSOW_VHWS_TAG);
368 fprintf(f, "\ttag=0x%x tt=%d head=%d tail=%d grp=%d index=%d tail=%d\n",
369 (uint32_t)(val & 0xffffffff), (int)(val >> 32) & 0x3,
370 (int)(val >> 34) & 0x1, (int)(val >> 35) & 0x1,
371 (int)(val >> 36) & 0x3ff, (int)(val >> 48) & 0x3ff,
372 (int)(val >> 63) & 0x1);
374 val = ssovf_read64(base + SSOW_VHWS_WQP);
375 fprintf(f, "\twqp=0x%"PRIx64"\n", val);
377 val = ssovf_read64(base + SSOW_VHWS_LINKS);
378 fprintf(f, "\tindex=%d valid=%d revlink=%d tail=%d head=%d grp=%d\n",
379 (int)(val & 0x3ff), (int)(val >> 10) & 0x1,
380 (int)(val >> 11) & 0x3ff, (int)(val >> 26) & 0x1,
381 (int)(val >> 27) & 0x1, (int)(val >> 28) & 0x3ff);
383 val = ssovf_read64(base + SSOW_VHWS_PENDTAG);
384 fprintf(f, "\tptag=0x%x ptt=%d pgwi=%d pdesc=%d pgw=%d pgww=%d ps=%d\n",
385 (uint32_t)(val & 0xffffffff), (int)(val >> 32) & 0x3,
386 (int)(val >> 56) & 0x1, (int)(val >> 58) & 0x1,
387 (int)(val >> 61) & 0x1, (int)(val >> 62) & 0x1,
388 (int)(val >> 63) & 0x1);
390 val = ssovf_read64(base + SSOW_VHWS_PENDWQP);
391 fprintf(f, "\tpwqp=0x%"PRIx64"\n", val);
395 ssovf_dump(struct rte_eventdev *dev, FILE *f)
397 struct ssovf_evdev *edev = ssovf_pmd_priv(dev);
400 /* Dump SSOWVF debug registers */
401 for (port = 0; port < edev->nb_event_ports; port++)
402 ssows_dump(dev->data->ports[port], f);
406 ssovf_start(struct rte_eventdev *dev)
408 struct ssovf_evdev *edev = ssovf_pmd_priv(dev);
414 for (i = 0; i < edev->nb_event_ports; i++) {
415 ws = dev->data->ports[i];
420 for (i = 0; i < edev->nb_event_queues; i++) {
421 /* Consume all the events through HWS0 */
422 ssows_flush_events(dev->data->ports[0], i);
424 base = octeontx_ssovf_bar(OCTEONTX_SSO_GROUP, i, 0);
425 base += SSO_VHGRP_QCTL;
426 ssovf_write64(1, base); /* Enable SSO group */
429 ssovf_fastpath_fns_set(dev);
434 ssovf_stop(struct rte_eventdev *dev)
436 struct ssovf_evdev *edev = ssovf_pmd_priv(dev);
442 for (i = 0; i < edev->nb_event_ports; i++) {
443 ws = dev->data->ports[i];
448 for (i = 0; i < edev->nb_event_queues; i++) {
449 /* Consume all the events through HWS0 */
450 ssows_flush_events(dev->data->ports[0], i);
452 base = octeontx_ssovf_bar(OCTEONTX_SSO_GROUP, i, 0);
453 base += SSO_VHGRP_QCTL;
454 ssovf_write64(0, base); /* Disable SSO group */
459 ssovf_close(struct rte_eventdev *dev)
461 struct ssovf_evdev *edev = ssovf_pmd_priv(dev);
462 uint8_t all_queues[RTE_EVENT_MAX_QUEUES_PER_DEV];
465 for (i = 0; i < edev->nb_event_queues; i++)
468 for (i = 0; i < edev->nb_event_ports; i++)
469 ssovf_port_unlink(dev, dev->data->ports[i], all_queues,
470 edev->nb_event_queues);
474 /* Initialize and register event driver with DPDK Application */
475 static const struct rte_eventdev_ops ssovf_ops = {
476 .dev_infos_get = ssovf_info_get,
477 .dev_configure = ssovf_configure,
478 .queue_def_conf = ssovf_queue_def_conf,
479 .queue_setup = ssovf_queue_setup,
480 .queue_release = ssovf_queue_release,
481 .port_def_conf = ssovf_port_def_conf,
482 .port_setup = ssovf_port_setup,
483 .port_release = ssovf_port_release,
484 .port_link = ssovf_port_link,
485 .port_unlink = ssovf_port_unlink,
486 .timeout_ticks = ssovf_timeout_ticks,
488 .dev_start = ssovf_start,
489 .dev_stop = ssovf_stop,
490 .dev_close = ssovf_close
494 ssovf_vdev_probe(struct rte_vdev_device *vdev)
496 struct octeontx_ssovf_info oinfo;
497 struct ssovf_mbox_dev_info info;
498 struct ssovf_evdev *edev;
499 struct rte_eventdev *eventdev;
500 static int ssovf_init_once;
504 name = rte_vdev_device_name(vdev);
505 /* More than one instance is not supported */
506 if (ssovf_init_once) {
507 ssovf_log_err("Request to create >1 %s instance", name);
511 eventdev = rte_event_pmd_vdev_init(name, sizeof(struct ssovf_evdev),
513 if (eventdev == NULL) {
514 ssovf_log_err("Failed to create eventdev vdev %s", name);
517 eventdev->dev_ops = &ssovf_ops;
519 /* For secondary processes, the primary has done all the work */
520 if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
521 ssovf_fastpath_fns_set(eventdev);
525 ret = octeontx_ssovf_info(&oinfo);
527 ssovf_log_err("Failed to probe and validate ssovfs %d", ret);
531 edev = ssovf_pmd_priv(eventdev);
532 edev->max_event_ports = oinfo.total_ssowvfs;
533 edev->max_event_queues = oinfo.total_ssovfs;
534 edev->is_timeout_deq = 0;
536 ret = ssovf_mbox_dev_info(&info);
537 if (ret < 0 || ret != sizeof(struct ssovf_mbox_dev_info)) {
538 ssovf_log_err("Failed to get mbox devinfo %d", ret);
542 edev->min_deq_timeout_ns = info.min_deq_timeout_ns;
543 edev->max_deq_timeout_ns = info.max_deq_timeout_ns;
544 edev->max_num_events = info.max_num_events;
545 ssovf_log_dbg("min_deq_tmo=%"PRId64" max_deq_tmo=%"PRId64" max_evts=%d",
546 info.min_deq_timeout_ns, info.max_deq_timeout_ns,
547 info.max_num_events);
549 if (!edev->max_event_ports || !edev->max_event_queues) {
550 ssovf_log_err("Not enough eventdev resource queues=%d ports=%d",
551 edev->max_event_queues, edev->max_event_ports);
556 ssovf_log_info("Initializing %s domain=%d max_queues=%d max_ports=%d",
557 name, oinfo.domain, edev->max_event_queues,
558 edev->max_event_ports);
564 rte_event_pmd_vdev_uninit(name);
569 ssovf_vdev_remove(struct rte_vdev_device *vdev)
573 name = rte_vdev_device_name(vdev);
574 ssovf_log_info("Closing %s", name);
575 return rte_event_pmd_vdev_uninit(name);
578 static struct rte_vdev_driver vdev_ssovf_pmd = {
579 .probe = ssovf_vdev_probe,
580 .remove = ssovf_vdev_remove
583 RTE_PMD_REGISTER_VDEV(EVENTDEV_NAME_OCTEONTX_PMD, vdev_ssovf_pmd);