drivers/event/octeontx/timvf_evdev.h

   1 /*
   2  * SPDX-License-Identifier: BSD-3-Clause
   3  * Copyright(c) 2017 Cavium, Inc
   4  */
   5
   6 #ifndef __TIMVF_EVDEV_H__
   7 #define __TIMVF_EVDEV_H__
   8
   9 #include <rte_common.h>
  10 #include <rte_cycles.h>
  11 #include <rte_debug.h>
  12 #include <rte_eal.h>
  13 #include <rte_eventdev.h>
  14 #include <rte_event_timer_adapter.h>
  15 #include <rte_event_timer_adapter_pmd.h>
  16 #include <rte_io.h>
  17 #include <rte_lcore.h>
  18 #include <rte_log.h>
  19 #include <rte_malloc.h>
  20 #include <rte_mbuf_pool_ops.h>
  21 #include <rte_mempool.h>
  22 #include <rte_memzone.h>
  23 #include <rte_pci.h>
  24 #include <rte_prefetch.h>
  25 #include <rte_reciprocal.h>
  26
  27 #include <octeontx_mbox.h>
  28
  29 #define timvf_log(level, fmt, args...) \
  30         rte_log(RTE_LOG_ ## level, otx_logtype_timvf, \
  31                         "[%s] %s() " fmt "\n", \
  32                         RTE_STR(event_timer_octeontx), __func__, ## args)
  33
  34 #define timvf_log_info(fmt, ...) timvf_log(INFO, fmt, ##__VA_ARGS__)
  35 #define timvf_log_dbg(fmt, ...) timvf_log(DEBUG, fmt, ##__VA_ARGS__)
  36 #define timvf_log_err(fmt, ...) timvf_log(ERR, fmt, ##__VA_ARGS__)
  37 #define timvf_func_trace timvf_log_dbg
  38
  39 #define TIM_COPROC                              (8)
  40 #define TIM_GET_DEV_INFO                        (1)
  41 #define TIM_GET_RING_INFO                       (2)
  42 #define TIM_SET_RING_INFO                       (3)
  43 #define TIM_RING_START_CYC_GET                  (4)
  44
  45 #define TIM_MAX_RINGS                           (64)
  46 #define TIM_DEV_PER_NODE                        (1)
  47 #define TIM_VF_PER_DEV                          (64)
  48 #define TIM_RING_PER_DEV                        (TIM_VF_PER_DEV)
  49 #define TIM_RING_NODE_SHIFT                     (6)
  50 #define TIM_RING_MASK                           ((TIM_RING_PER_DEV) - 1)
  51 #define TIM_RING_INVALID                        (-1)
  52
  53 #define TIM_MIN_INTERVAL                        (1E3)
  54 #define TIM_MAX_INTERVAL                        ((1ull << 32) - 1)
  55 #define TIM_MAX_BUCKETS                         (1ull << 20)
  56 #define TIM_CHUNK_SIZE                          (4096)
  57 #define TIM_MAX_CHUNKS_PER_BUCKET               (1ull << 32)
  58
  59 #define TIMVF_MAX_BURST                         (8)
  60
  61 /* TIM VF Control/Status registers (CSRs): */
  62 /* VF_BAR0: */
  63 #define TIM_VF_NRSPERR_INT                      (0x0)
  64 #define TIM_VF_NRSPERR_INT_W1S                  (0x8)
  65 #define TIM_VF_NRSPERR_ENA_W1C                  (0x10)
  66 #define TIM_VF_NRSPERR_ENA_W1S                  (0x18)
  67 #define TIM_VRING_FR_RN_CYCLES                  (0x20)
  68 #define TIM_VRING_FR_RN_GPIOS                   (0x28)
  69 #define TIM_VRING_FR_RN_GTI                     (0x30)
  70 #define TIM_VRING_FR_RN_PTP                     (0x38)
  71 #define TIM_VRING_CTL0                          (0x40)
  72 #define TIM_VRING_CTL1                          (0x50)
  73 #define TIM_VRING_CTL2                          (0x60)
  74 #define TIM_VRING_BASE                          (0x100)
  75 #define TIM_VRING_AURA                          (0x108)
  76 #define TIM_VRING_REL                           (0x110)
  77
  78 #define timvf_read64 rte_read64_relaxed
  79 #define timvf_write64 rte_write64_relaxed
  80
  81 extern int otx_logtype_timvf;
  82 static const uint16_t nb_chunk_slots = (TIM_CHUNK_SIZE / 16) - 1;
  83
  84 struct timvf_info {
  85         uint16_t domain; /* Domain id */
  86         uint8_t total_timvfs; /* Total timvf available in domain */
  87 };
  88
  89 enum timvf_clk_src {
  90         TIM_CLK_SRC_SCLK = RTE_EVENT_TIMER_ADAPTER_CPU_CLK,
  91         TIM_CLK_SRC_GPIO = RTE_EVENT_TIMER_ADAPTER_EXT_CLK0,
  92         TIM_CLK_SRC_GTI = RTE_EVENT_TIMER_ADAPTER_EXT_CLK1,
  93         TIM_CLK_SRC_PTP = RTE_EVENT_TIMER_ADAPTER_EXT_CLK2,
  94 };
  95
  96 /* TIM_MEM_BUCKET */
  97 struct tim_mem_bucket {
  98         uint64_t first_chunk;
  99         union {
 100                 uint64_t w1;
 101                 struct {
 102                         uint32_t nb_entry;
 103                         uint8_t sbt:1;
 104                         uint8_t hbt:1;
 105                         uint8_t bsk:1;
 106                         uint8_t rsvd:5;
 107                         uint8_t lock;
 108                         int16_t chunk_remainder;
 109                 };
 110         };
 111         uint64_t current_chunk;
 112         uint64_t pad;
 113 } __rte_packed;
 114
 115 struct tim_mem_entry {
 116         uint64_t w0;
 117         uint64_t wqe;
 118 } __rte_packed;
 119
 120 struct timvf_ctrl_reg {
 121         uint64_t rctrl0;
 122         uint64_t rctrl1;
 123         uint64_t rctrl2;
 124         uint8_t use_pmu;
 125 } __rte_packed;
 126
 127 struct timvf_ring;
 128
 129 typedef uint32_t (*bkt_id)(const uint32_t bkt_tcks, const uint32_t nb_bkts);
 130 typedef struct tim_mem_entry * (*refill_chunk)(
 131                 struct tim_mem_bucket * const bkt,
 132                 struct timvf_ring * const timr);
 133
 134 struct timvf_ring {
 135         bkt_id get_target_bkt;
 136         refill_chunk refill_chunk;
 137         struct rte_reciprocal_u64 fast_div;
 138         uint64_t ring_start_cyc;
 139         uint32_t nb_bkts;
 140         struct tim_mem_bucket *bkt;
 141         void *chunk_pool;
 142         uint64_t tck_int;
 143         uint64_t tck_nsec;
 144         void  *vbar0;
 145         void *bkt_pos;
 146         uint64_t max_tout;
 147         uint64_t nb_chunks;
 148         enum timvf_clk_src clk_src;
 149         uint16_t tim_ring_id;
 150 } __rte_cache_aligned;
 151
 152 static __rte_always_inline uint32_t
 153 bkt_mod(const uint32_t rel_bkt, const uint32_t nb_bkts)
 154 {
 155         return rel_bkt % nb_bkts;
 156 }
 157
 158 int timvf_info(struct timvf_info *tinfo);
 159 void *timvf_bar(uint8_t id, uint8_t bar);
 160 int timvf_timer_adapter_caps_get(const struct rte_eventdev *dev, uint64_t flags,
 161                 uint32_t *caps, const struct rte_event_timer_adapter_ops **ops,
 162                 uint8_t enable_stats);
 163
 164 #endif /* __TIMVF_EVDEV_H__ */