drivers/event/octeontx2/otx2_evdev.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(C) 2019 Marvell International Ltd.
   3  */
   4
   5 #include <inttypes.h>
   6
   7 #include <rte_bus_pci.h>
   8 #include <rte_common.h>
   9 #include <rte_eal.h>
  10 #include <rte_eventdev_pmd_pci.h>
  11 #include <rte_kvargs.h>
  12 #include <rte_mbuf_pool_ops.h>
  13 #include <rte_pci.h>
  14
  15 #include "otx2_evdev_stats.h"
  16 #include "otx2_evdev.h"
  17 #include "otx2_irq.h"
  18 #include "otx2_tim_evdev.h"
  19
  20 static inline int
  21 sso_get_msix_offsets(const struct rte_eventdev *event_dev)
  22 {
  23         struct otx2_sso_evdev *dev = sso_pmd_priv(event_dev);
  24         uint8_t nb_ports = dev->nb_event_ports * (dev->dual_ws ? 2 : 1);
  25         struct otx2_mbox *mbox = dev->mbox;
  26         struct msix_offset_rsp *msix_rsp;
  27         int i, rc;
  28
  29         /* Get SSO and SSOW MSIX vector offsets */
  30         otx2_mbox_alloc_msg_msix_offset(mbox);
  31         rc = otx2_mbox_process_msg(mbox, (void *)&msix_rsp);
  32
  33         for (i = 0; i < nb_ports; i++)
  34                 dev->ssow_msixoff[i] = msix_rsp->ssow_msixoff[i];
  35
  36         for (i = 0; i < dev->nb_event_queues; i++)
  37                 dev->sso_msixoff[i] = msix_rsp->sso_msixoff[i];
  38
  39         return rc;
  40 }
  41
  42 void
  43 sso_fastpath_fns_set(struct rte_eventdev *event_dev)
  44 {
  45         struct otx2_sso_evdev *dev = sso_pmd_priv(event_dev);
  46         /* Single WS modes */
  47         const event_dequeue_t ssogws_deq[2][2][2][2][2][2][2] = {
  48 #define R(name, f6, f5, f4, f3, f2, f1, f0, flags)                      \
  49                 [f6][f5][f4][f3][f2][f1][f0] = otx2_ssogws_deq_ ##name,
  50 SSO_RX_ADPTR_ENQ_FASTPATH_FUNC
  51 #undef R
  52         };
  53
  54         const event_dequeue_burst_t ssogws_deq_burst[2][2][2][2][2][2][2] = {
  55 #define R(name, f6, f5, f4, f3, f2, f1, f0, flags)                      \
  56                 [f6][f5][f4][f3][f2][f1][f0] = otx2_ssogws_deq_burst_ ##name,
  57 SSO_RX_ADPTR_ENQ_FASTPATH_FUNC
  58 #undef R
  59         };
  60
  61         const event_dequeue_t ssogws_deq_timeout[2][2][2][2][2][2][2] = {
  62 #define R(name, f6, f5, f4, f3, f2, f1, f0, flags)                      \
  63                 [f6][f5][f4][f3][f2][f1][f0] = otx2_ssogws_deq_timeout_ ##name,
  64 SSO_RX_ADPTR_ENQ_FASTPATH_FUNC
  65 #undef R
  66         };
  67
  68         const event_dequeue_burst_t
  69                 ssogws_deq_timeout_burst[2][2][2][2][2][2][2] = {
  70 #define R(name, f6, f5, f4, f3, f2, f1, f0, flags)                      \
  71                 [f6][f5][f4][f3][f2][f1][f0] =                          \
  72                         otx2_ssogws_deq_timeout_burst_ ##name,
  73 SSO_RX_ADPTR_ENQ_FASTPATH_FUNC
  74 #undef R
  75         };
  76
  77         const event_dequeue_t ssogws_deq_seg[2][2][2][2][2][2][2] = {
  78 #define R(name, f6, f5, f4, f3, f2, f1, f0, flags)                      \
  79                 [f6][f5][f4][f3][f2][f1][f0] = otx2_ssogws_deq_seg_ ##name,
  80 SSO_RX_ADPTR_ENQ_FASTPATH_FUNC
  81 #undef R
  82         };
  83
  84         const event_dequeue_burst_t
  85                 ssogws_deq_seg_burst[2][2][2][2][2][2][2] = {
  86 #define R(name, f6, f5, f4, f3, f2, f1, f0, flags)                      \
  87                 [f6][f5][f4][f3][f2][f1][f0] =                          \
  88                         otx2_ssogws_deq_seg_burst_ ##name,
  89 SSO_RX_ADPTR_ENQ_FASTPATH_FUNC
  90 #undef R
  91         };
  92
  93         const event_dequeue_t ssogws_deq_seg_timeout[2][2][2][2][2][2][2] = {
  94 #define R(name, f6, f5, f4, f3, f2, f1, f0, flags)                      \
  95                 [f6][f5][f4][f3][f2][f1][f0] =                          \
  96                         otx2_ssogws_deq_seg_timeout_ ##name,
  97 SSO_RX_ADPTR_ENQ_FASTPATH_FUNC
  98 #undef R
  99         };
 100
 101         const event_dequeue_burst_t
 102                 ssogws_deq_seg_timeout_burst[2][2][2][2][2][2][2] = {
 103 #define R(name, f6, f5, f4, f3, f2, f1, f0, flags)                      \
 104                 [f6][f5][f4][f3][f2][f1][f0] =                          \
 105                                 otx2_ssogws_deq_seg_timeout_burst_ ##name,
 106 SSO_RX_ADPTR_ENQ_FASTPATH_FUNC
 107 #undef R
 108         };
 109
 110
 111         /* Dual WS modes */
 112         const event_dequeue_t ssogws_dual_deq[2][2][2][2][2][2][2] = {
 113 #define R(name, f6, f5, f4, f3, f2, f1, f0, flags)                      \
 114                 [f6][f5][f4][f3][f2][f1][f0] = otx2_ssogws_dual_deq_ ##name,
 115 SSO_RX_ADPTR_ENQ_FASTPATH_FUNC
 116 #undef R
 117         };
 118
 119         const event_dequeue_burst_t
 120                 ssogws_dual_deq_burst[2][2][2][2][2][2][2] = {
 121 #define R(name, f6, f5, f4, f3, f2, f1, f0, flags)                      \
 122                 [f6][f5][f4][f3][f2][f1][f0] =                          \
 123                         otx2_ssogws_dual_deq_burst_ ##name,
 124 SSO_RX_ADPTR_ENQ_FASTPATH_FUNC
 125 #undef R
 126         };
 127
 128         const event_dequeue_t ssogws_dual_deq_timeout[2][2][2][2][2][2][2] = {
 129 #define R(name, f6, f5, f4, f3, f2, f1, f0, flags)                      \
 130                 [f6][f5][f4][f3][f2][f1][f0] =                          \
 131                         otx2_ssogws_dual_deq_timeout_ ##name,
 132 SSO_RX_ADPTR_ENQ_FASTPATH_FUNC
 133 #undef R
 134         };
 135
 136         const event_dequeue_burst_t
 137                 ssogws_dual_deq_timeout_burst[2][2][2][2][2][2][2] = {
 138 #define R(name, f6, f5, f4, f3, f2, f1, f0, flags)                      \
 139         [f6][f5][f4][f3][f2][f1][f0] =                                  \
 140                         otx2_ssogws_dual_deq_timeout_burst_ ##name,
 141 SSO_RX_ADPTR_ENQ_FASTPATH_FUNC
 142 #undef R
 143         };
 144
 145         const event_dequeue_t ssogws_dual_deq_seg[2][2][2][2][2][2][2] = {
 146 #define R(name, f6, f5, f4, f3, f2, f1, f0, flags)                      \
 147                 [f6][f5][f4][f3][f2][f1][f0] = otx2_ssogws_dual_deq_seg_ ##name,
 148 SSO_RX_ADPTR_ENQ_FASTPATH_FUNC
 149 #undef R
 150         };
 151
 152         const event_dequeue_burst_t
 153                 ssogws_dual_deq_seg_burst[2][2][2][2][2][2][2] = {
 154 #define R(name, f6, f5, f4, f3, f2, f1, f0, flags)                      \
 155                 [f6][f5][f4][f3][f2][f1][f0] =                          \
 156                         otx2_ssogws_dual_deq_seg_burst_ ##name,
 157 SSO_RX_ADPTR_ENQ_FASTPATH_FUNC
 158 #undef R
 159         };
 160
 161         const event_dequeue_t
 162                 ssogws_dual_deq_seg_timeout[2][2][2][2][2][2][2] = {
 163 #define R(name, f6, f5, f4, f3, f2, f1, f0, flags)                      \
 164                 [f6][f5][f4][f3][f2][f1][f0] =                          \
 165                         otx2_ssogws_dual_deq_seg_timeout_ ##name,
 166 SSO_RX_ADPTR_ENQ_FASTPATH_FUNC
 167 #undef R
 168         };
 169
 170         const event_dequeue_burst_t
 171                 ssogws_dual_deq_seg_timeout_burst[2][2][2][2][2][2][2] = {
 172 #define R(name, f6, f5, f4, f3, f2, f1, f0, flags)                      \
 173                 [f6][f5][f4][f3][f2][f1][f0] =                          \
 174                         otx2_ssogws_dual_deq_seg_timeout_burst_ ##name,
 175 SSO_RX_ADPTR_ENQ_FASTPATH_FUNC
 176 #undef R
 177         };
 178
 179         /* Tx modes */
 180         const event_tx_adapter_enqueue
 181                 ssogws_tx_adptr_enq[2][2][2][2][2][2][2] = {
 182 #define T(name, f6, f5, f4, f3, f2, f1, f0, sz, flags)                  \
 183                 [f6][f5][f4][f3][f2][f1][f0] =                          \
 184                         otx2_ssogws_tx_adptr_enq_ ## name,
 185 SSO_TX_ADPTR_ENQ_FASTPATH_FUNC
 186 #undef T
 187         };
 188
 189         const event_tx_adapter_enqueue
 190                 ssogws_tx_adptr_enq_seg[2][2][2][2][2][2][2] = {
 191 #define T(name, f6, f5, f4, f3, f2, f1, f0, sz, flags)                  \
 192                 [f6][f5][f4][f3][f2][f1][f0] =                          \
 193                         otx2_ssogws_tx_adptr_enq_seg_ ## name,
 194 SSO_TX_ADPTR_ENQ_FASTPATH_FUNC
 195 #undef T
 196         };
 197
 198         const event_tx_adapter_enqueue
 199                 ssogws_dual_tx_adptr_enq[2][2][2][2][2][2][2] = {
 200 #define T(name, f6, f5, f4, f3, f2, f1, f0, sz, flags)                  \
 201                 [f6][f5][f4][f3][f2][f1][f0] =                          \
 202                         otx2_ssogws_dual_tx_adptr_enq_ ## name,
 203 SSO_TX_ADPTR_ENQ_FASTPATH_FUNC
 204 #undef T
 205         };
 206
 207         const event_tx_adapter_enqueue
 208                 ssogws_dual_tx_adptr_enq_seg[2][2][2][2][2][2][2] = {
 209 #define T(name, f6, f5, f4, f3, f2, f1, f0, sz, flags)                  \
 210                 [f6][f5][f4][f3][f2][f1][f0] =                          \
 211                         otx2_ssogws_dual_tx_adptr_enq_seg_ ## name,
 212 SSO_TX_ADPTR_ENQ_FASTPATH_FUNC
 213 #undef T
 214         };
 215
 216         event_dev->enqueue                      = otx2_ssogws_enq;
 217         event_dev->enqueue_burst                = otx2_ssogws_enq_burst;
 218         event_dev->enqueue_new_burst            = otx2_ssogws_enq_new_burst;
 219         event_dev->enqueue_forward_burst        = otx2_ssogws_enq_fwd_burst;
 220         if (dev->rx_offloads & NIX_RX_MULTI_SEG_F) {
 221                 event_dev->dequeue              = ssogws_deq_seg
 222                         [!!(dev->rx_offloads & NIX_RX_OFFLOAD_SECURITY_F)]
 223                         [!!(dev->rx_offloads & NIX_RX_OFFLOAD_TSTAMP_F)]
 224                         [!!(dev->rx_offloads & NIX_RX_OFFLOAD_MARK_UPDATE_F)]
 225                         [!!(dev->rx_offloads & NIX_RX_OFFLOAD_VLAN_STRIP_F)]
 226                         [!!(dev->rx_offloads & NIX_RX_OFFLOAD_CHECKSUM_F)]
 227                         [!!(dev->rx_offloads & NIX_RX_OFFLOAD_PTYPE_F)]
 228                         [!!(dev->rx_offloads & NIX_RX_OFFLOAD_RSS_F)];
 229                 event_dev->dequeue_burst        = ssogws_deq_seg_burst
 230                         [!!(dev->rx_offloads & NIX_RX_OFFLOAD_SECURITY_F)]
 231                         [!!(dev->rx_offloads & NIX_RX_OFFLOAD_TSTAMP_F)]
 232                         [!!(dev->rx_offloads & NIX_RX_OFFLOAD_MARK_UPDATE_F)]
 233                         [!!(dev->rx_offloads & NIX_RX_OFFLOAD_VLAN_STRIP_F)]
 234                         [!!(dev->rx_offloads & NIX_RX_OFFLOAD_CHECKSUM_F)]
 235                         [!!(dev->rx_offloads & NIX_RX_OFFLOAD_PTYPE_F)]
 236                         [!!(dev->rx_offloads & NIX_RX_OFFLOAD_RSS_F)];
 237                 if (dev->is_timeout_deq) {
 238                         event_dev->dequeue      = ssogws_deq_seg_timeout
 239                         [!!(dev->rx_offloads & NIX_RX_OFFLOAD_SECURITY_F)]
 240                         [!!(dev->rx_offloads & NIX_RX_OFFLOAD_TSTAMP_F)]
 241                         [!!(dev->rx_offloads & NIX_RX_OFFLOAD_MARK_UPDATE_F)]
 242                         [!!(dev->rx_offloads & NIX_RX_OFFLOAD_VLAN_STRIP_F)]
 243                         [!!(dev->rx_offloads & NIX_RX_OFFLOAD_CHECKSUM_F)]
 244                         [!!(dev->rx_offloads & NIX_RX_OFFLOAD_PTYPE_F)]
 245                         [!!(dev->rx_offloads & NIX_RX_OFFLOAD_RSS_F)];
 246                         event_dev->dequeue_burst        =
 247                                 ssogws_deq_seg_timeout_burst
 248                         [!!(dev->rx_offloads & NIX_RX_OFFLOAD_SECURITY_F)]
 249                         [!!(dev->rx_offloads & NIX_RX_OFFLOAD_TSTAMP_F)]
 250                         [!!(dev->rx_offloads & NIX_RX_OFFLOAD_MARK_UPDATE_F)]
 251                         [!!(dev->rx_offloads & NIX_RX_OFFLOAD_VLAN_STRIP_F)]
 252                         [!!(dev->rx_offloads & NIX_RX_OFFLOAD_CHECKSUM_F)]
 253                         [!!(dev->rx_offloads & NIX_RX_OFFLOAD_PTYPE_F)]
 254                         [!!(dev->rx_offloads & NIX_RX_OFFLOAD_RSS_F)];
 255                 }
 256         } else {
 257                 event_dev->dequeue                      = ssogws_deq
 258                         [!!(dev->rx_offloads & NIX_RX_OFFLOAD_SECURITY_F)]
 259                         [!!(dev->rx_offloads & NIX_RX_OFFLOAD_TSTAMP_F)]
 260                         [!!(dev->rx_offloads & NIX_RX_OFFLOAD_MARK_UPDATE_F)]
 261                         [!!(dev->rx_offloads & NIX_RX_OFFLOAD_VLAN_STRIP_F)]
 262                         [!!(dev->rx_offloads & NIX_RX_OFFLOAD_CHECKSUM_F)]
 263                         [!!(dev->rx_offloads & NIX_RX_OFFLOAD_PTYPE_F)]
 264                         [!!(dev->rx_offloads & NIX_RX_OFFLOAD_RSS_F)];
 265                 event_dev->dequeue_burst                = ssogws_deq_burst
 266                         [!!(dev->rx_offloads & NIX_RX_OFFLOAD_SECURITY_F)]
 267                         [!!(dev->rx_offloads & NIX_RX_OFFLOAD_TSTAMP_F)]
 268                         [!!(dev->rx_offloads & NIX_RX_OFFLOAD_MARK_UPDATE_F)]
 269                         [!!(dev->rx_offloads & NIX_RX_OFFLOAD_VLAN_STRIP_F)]
 270                         [!!(dev->rx_offloads & NIX_RX_OFFLOAD_CHECKSUM_F)]
 271                         [!!(dev->rx_offloads & NIX_RX_OFFLOAD_PTYPE_F)]
 272                         [!!(dev->rx_offloads & NIX_RX_OFFLOAD_RSS_F)];
 273                 if (dev->is_timeout_deq) {
 274                         event_dev->dequeue              = ssogws_deq_timeout
 275                         [!!(dev->rx_offloads & NIX_RX_OFFLOAD_SECURITY_F)]
 276                         [!!(dev->rx_offloads & NIX_RX_OFFLOAD_TSTAMP_F)]
 277                         [!!(dev->rx_offloads & NIX_RX_OFFLOAD_MARK_UPDATE_F)]
 278                         [!!(dev->rx_offloads & NIX_RX_OFFLOAD_VLAN_STRIP_F)]
 279                         [!!(dev->rx_offloads & NIX_RX_OFFLOAD_CHECKSUM_F)]
 280                         [!!(dev->rx_offloads & NIX_RX_OFFLOAD_PTYPE_F)]
 281                         [!!(dev->rx_offloads & NIX_RX_OFFLOAD_RSS_F)];
 282                         event_dev->dequeue_burst        =
 283                                 ssogws_deq_timeout_burst
 284                         [!!(dev->rx_offloads & NIX_RX_OFFLOAD_SECURITY_F)]
 285                         [!!(dev->rx_offloads & NIX_RX_OFFLOAD_TSTAMP_F)]
 286                         [!!(dev->rx_offloads & NIX_RX_OFFLOAD_MARK_UPDATE_F)]
 287                         [!!(dev->rx_offloads & NIX_RX_OFFLOAD_VLAN_STRIP_F)]
 288                         [!!(dev->rx_offloads & NIX_RX_OFFLOAD_CHECKSUM_F)]
 289                         [!!(dev->rx_offloads & NIX_RX_OFFLOAD_PTYPE_F)]
 290                         [!!(dev->rx_offloads & NIX_RX_OFFLOAD_RSS_F)];
 291                 }
 292         }
 293
 294         if (dev->tx_offloads & NIX_TX_MULTI_SEG_F) {
 295                 /* [SEC] [TSMP] [MBUF_NOFF] [VLAN] [OL3_L4_CSUM] [L3_L4_CSUM] */
 296                 event_dev->txa_enqueue = ssogws_tx_adptr_enq_seg
 297                         [!!(dev->tx_offloads & NIX_TX_OFFLOAD_SECURITY_F)]
 298                         [!!(dev->tx_offloads & NIX_TX_OFFLOAD_TSO_F)]
 299                         [!!(dev->tx_offloads & NIX_TX_OFFLOAD_TSTAMP_F)]
 300                         [!!(dev->tx_offloads & NIX_TX_OFFLOAD_MBUF_NOFF_F)]
 301                         [!!(dev->tx_offloads & NIX_TX_OFFLOAD_VLAN_QINQ_F)]
 302                         [!!(dev->tx_offloads & NIX_TX_OFFLOAD_OL3_OL4_CSUM_F)]
 303                         [!!(dev->tx_offloads & NIX_TX_OFFLOAD_L3_L4_CSUM_F)];
 304         } else {
 305                 event_dev->txa_enqueue = ssogws_tx_adptr_enq
 306                         [!!(dev->tx_offloads & NIX_TX_OFFLOAD_SECURITY_F)]
 307                         [!!(dev->tx_offloads & NIX_TX_OFFLOAD_TSO_F)]
 308                         [!!(dev->tx_offloads & NIX_TX_OFFLOAD_TSTAMP_F)]
 309                         [!!(dev->tx_offloads & NIX_TX_OFFLOAD_MBUF_NOFF_F)]
 310                         [!!(dev->tx_offloads & NIX_TX_OFFLOAD_VLAN_QINQ_F)]
 311                         [!!(dev->tx_offloads & NIX_TX_OFFLOAD_OL3_OL4_CSUM_F)]
 312                         [!!(dev->tx_offloads & NIX_TX_OFFLOAD_L3_L4_CSUM_F)];
 313         }
 314
 315         if (dev->dual_ws) {
 316                 event_dev->enqueue              = otx2_ssogws_dual_enq;
 317                 event_dev->enqueue_burst        = otx2_ssogws_dual_enq_burst;
 318                 event_dev->enqueue_new_burst    =
 319                                         otx2_ssogws_dual_enq_new_burst;
 320                 event_dev->enqueue_forward_burst =
 321                                         otx2_ssogws_dual_enq_fwd_burst;
 322
 323                 if (dev->rx_offloads & NIX_RX_MULTI_SEG_F) {
 324                         event_dev->dequeue      = ssogws_dual_deq_seg
 325                                 [!!(dev->rx_offloads &
 326                                                 NIX_RX_OFFLOAD_SECURITY_F)]
 327                                 [!!(dev->rx_offloads &
 328                                                 NIX_RX_OFFLOAD_TSTAMP_F)]
 329                                 [!!(dev->rx_offloads &
 330                                                 NIX_RX_OFFLOAD_MARK_UPDATE_F)]
 331                                 [!!(dev->rx_offloads &
 332                                                 NIX_RX_OFFLOAD_VLAN_STRIP_F)]
 333                                 [!!(dev->rx_offloads &
 334                                                 NIX_RX_OFFLOAD_CHECKSUM_F)]
 335                                 [!!(dev->rx_offloads & NIX_RX_OFFLOAD_PTYPE_F)]
 336                                 [!!(dev->rx_offloads & NIX_RX_OFFLOAD_RSS_F)];
 337                         event_dev->dequeue_burst = ssogws_dual_deq_seg_burst
 338                                 [!!(dev->rx_offloads &
 339                                                 NIX_RX_OFFLOAD_SECURITY_F)]
 340                                 [!!(dev->rx_offloads & NIX_RX_OFFLOAD_TSTAMP_F)]
 341                                 [!!(dev->rx_offloads &
 342                                                 NIX_RX_OFFLOAD_MARK_UPDATE_F)]
 343                                 [!!(dev->rx_offloads &
 344                                                 NIX_RX_OFFLOAD_VLAN_STRIP_F)]
 345                                 [!!(dev->rx_offloads &
 346                                                 NIX_RX_OFFLOAD_CHECKSUM_F)]
 347                                 [!!(dev->rx_offloads & NIX_RX_OFFLOAD_PTYPE_F)]
 348                                 [!!(dev->rx_offloads & NIX_RX_OFFLOAD_RSS_F)];
 349                         if (dev->is_timeout_deq) {
 350                                 event_dev->dequeue      =
 351                                         ssogws_dual_deq_seg_timeout
 352                                         [!!(dev->rx_offloads &
 353                                                 NIX_RX_OFFLOAD_SECURITY_F)]
 354                                         [!!(dev->rx_offloads &
 355                                                 NIX_RX_OFFLOAD_TSTAMP_F)]
 356                                         [!!(dev->rx_offloads &
 357                                                 NIX_RX_OFFLOAD_MARK_UPDATE_F)]
 358                                         [!!(dev->rx_offloads &
 359                                                 NIX_RX_OFFLOAD_VLAN_STRIP_F)]
 360                                         [!!(dev->rx_offloads &
 361                                                 NIX_RX_OFFLOAD_CHECKSUM_F)]
 362                                         [!!(dev->rx_offloads &
 363                                                         NIX_RX_OFFLOAD_PTYPE_F)]
 364                                         [!!(dev->rx_offloads &
 365                                                         NIX_RX_OFFLOAD_RSS_F)];
 366                                 event_dev->dequeue_burst =
 367                                         ssogws_dual_deq_seg_timeout_burst
 368                                         [!!(dev->rx_offloads &
 369                                                 NIX_RX_OFFLOAD_SECURITY_F)]
 370                                         [!!(dev->rx_offloads &
 371                                                 NIX_RX_OFFLOAD_TSTAMP_F)]
 372                                         [!!(dev->rx_offloads &
 373                                                 NIX_RX_OFFLOAD_MARK_UPDATE_F)]
 374                                         [!!(dev->rx_offloads &
 375                                                 NIX_RX_OFFLOAD_VLAN_STRIP_F)]
 376                                         [!!(dev->rx_offloads &
 377                                                 NIX_RX_OFFLOAD_CHECKSUM_F)]
 378                                         [!!(dev->rx_offloads &
 379                                                         NIX_RX_OFFLOAD_PTYPE_F)]
 380                                         [!!(dev->rx_offloads &
 381                                                         NIX_RX_OFFLOAD_RSS_F)];
 382                         }
 383                 } else {
 384                         event_dev->dequeue              = ssogws_dual_deq
 385                                 [!!(dev->rx_offloads &
 386                                                 NIX_RX_OFFLOAD_SECURITY_F)]
 387                                 [!!(dev->rx_offloads &
 388                                                 NIX_RX_OFFLOAD_TSTAMP_F)]
 389                                 [!!(dev->rx_offloads &
 390                                                 NIX_RX_OFFLOAD_MARK_UPDATE_F)]
 391                                 [!!(dev->rx_offloads &
 392                                                 NIX_RX_OFFLOAD_VLAN_STRIP_F)]
 393                                 [!!(dev->rx_offloads &
 394                                                 NIX_RX_OFFLOAD_CHECKSUM_F)]
 395                                 [!!(dev->rx_offloads & NIX_RX_OFFLOAD_PTYPE_F)]
 396                                 [!!(dev->rx_offloads & NIX_RX_OFFLOAD_RSS_F)];
 397                         event_dev->dequeue_burst        = ssogws_dual_deq_burst
 398                                 [!!(dev->rx_offloads &
 399                                                 NIX_RX_OFFLOAD_SECURITY_F)]
 400                                 [!!(dev->rx_offloads &
 401                                                 NIX_RX_OFFLOAD_TSTAMP_F)]
 402                                 [!!(dev->rx_offloads &
 403                                                 NIX_RX_OFFLOAD_MARK_UPDATE_F)]
 404                                 [!!(dev->rx_offloads &
 405                                                 NIX_RX_OFFLOAD_VLAN_STRIP_F)]
 406                                 [!!(dev->rx_offloads &
 407                                                 NIX_RX_OFFLOAD_CHECKSUM_F)]
 408                                 [!!(dev->rx_offloads & NIX_RX_OFFLOAD_PTYPE_F)]
 409                                 [!!(dev->rx_offloads & NIX_RX_OFFLOAD_RSS_F)];
 410                         if (dev->is_timeout_deq) {
 411                                 event_dev->dequeue      =
 412                                         ssogws_dual_deq_timeout
 413                                         [!!(dev->rx_offloads &
 414                                                 NIX_RX_OFFLOAD_SECURITY_F)]
 415                                         [!!(dev->rx_offloads &
 416                                                 NIX_RX_OFFLOAD_TSTAMP_F)]
 417                                         [!!(dev->rx_offloads &
 418                                                 NIX_RX_OFFLOAD_MARK_UPDATE_F)]
 419                                         [!!(dev->rx_offloads &
 420                                                 NIX_RX_OFFLOAD_VLAN_STRIP_F)]
 421                                         [!!(dev->rx_offloads &
 422                                                 NIX_RX_OFFLOAD_CHECKSUM_F)]
 423                                         [!!(dev->rx_offloads &
 424                                                         NIX_RX_OFFLOAD_PTYPE_F)]
 425                                         [!!(dev->rx_offloads &
 426                                                         NIX_RX_OFFLOAD_RSS_F)];
 427                                 event_dev->dequeue_burst =
 428                                         ssogws_dual_deq_timeout_burst
 429                                         [!!(dev->rx_offloads &
 430                                                 NIX_RX_OFFLOAD_SECURITY_F)]
 431                                         [!!(dev->rx_offloads &
 432                                                 NIX_RX_OFFLOAD_TSTAMP_F)]
 433                                         [!!(dev->rx_offloads &
 434                                                 NIX_RX_OFFLOAD_MARK_UPDATE_F)]
 435                                         [!!(dev->rx_offloads &
 436                                                 NIX_RX_OFFLOAD_VLAN_STRIP_F)]
 437                                         [!!(dev->rx_offloads &
 438                                                 NIX_RX_OFFLOAD_CHECKSUM_F)]
 439                                         [!!(dev->rx_offloads &
 440                                                         NIX_RX_OFFLOAD_PTYPE_F)]
 441                                         [!!(dev->rx_offloads &
 442                                                         NIX_RX_OFFLOAD_RSS_F)];
 443                         }
 444                 }
 445
 446                 if (dev->tx_offloads & NIX_TX_MULTI_SEG_F) {
 447                 /* [SEC] [TSMP] [MBUF_NOFF] [VLAN] [OL3_L4_CSUM] [L3_L4_CSUM] */
 448                         event_dev->txa_enqueue = ssogws_dual_tx_adptr_enq_seg
 449                                 [!!(dev->tx_offloads &
 450                                                 NIX_TX_OFFLOAD_SECURITY_F)]
 451                                 [!!(dev->tx_offloads & NIX_TX_OFFLOAD_TSO_F)]
 452                                 [!!(dev->tx_offloads & NIX_TX_OFFLOAD_TSTAMP_F)]
 453                                 [!!(dev->tx_offloads &
 454                                                 NIX_TX_OFFLOAD_MBUF_NOFF_F)]
 455                                 [!!(dev->tx_offloads &
 456                                                 NIX_TX_OFFLOAD_VLAN_QINQ_F)]
 457                                 [!!(dev->tx_offloads &
 458                                                 NIX_TX_OFFLOAD_OL3_OL4_CSUM_F)]
 459                                 [!!(dev->tx_offloads &
 460                                                 NIX_TX_OFFLOAD_L3_L4_CSUM_F)];
 461                 } else {
 462                         event_dev->txa_enqueue = ssogws_dual_tx_adptr_enq
 463                                 [!!(dev->tx_offloads &
 464                                                 NIX_TX_OFFLOAD_SECURITY_F)]
 465                                 [!!(dev->tx_offloads & NIX_TX_OFFLOAD_TSO_F)]
 466                                 [!!(dev->tx_offloads & NIX_TX_OFFLOAD_TSTAMP_F)]
 467                                 [!!(dev->tx_offloads &
 468                                                 NIX_TX_OFFLOAD_MBUF_NOFF_F)]
 469                                 [!!(dev->tx_offloads &
 470                                                 NIX_TX_OFFLOAD_VLAN_QINQ_F)]
 471                                 [!!(dev->tx_offloads &
 472                                                 NIX_TX_OFFLOAD_OL3_OL4_CSUM_F)]
 473                                 [!!(dev->tx_offloads &
 474                                                 NIX_TX_OFFLOAD_L3_L4_CSUM_F)];
 475                 }
 476         }
 477
 478         event_dev->txa_enqueue_same_dest = event_dev->txa_enqueue;
 479         rte_mb();
 480 }
 481
 482 static void
 483 otx2_sso_info_get(struct rte_eventdev *event_dev,
 484                   struct rte_event_dev_info *dev_info)
 485 {
 486         struct otx2_sso_evdev *dev = sso_pmd_priv(event_dev);
 487
 488         dev_info->driver_name = RTE_STR(EVENTDEV_NAME_OCTEONTX2_PMD);
 489         dev_info->min_dequeue_timeout_ns = dev->min_dequeue_timeout_ns;
 490         dev_info->max_dequeue_timeout_ns = dev->max_dequeue_timeout_ns;
 491         dev_info->max_event_queues = dev->max_event_queues;
 492         dev_info->max_event_queue_flows = (1ULL << 20);
 493         dev_info->max_event_queue_priority_levels = 8;
 494         dev_info->max_event_priority_levels = 1;
 495         dev_info->max_event_ports = dev->max_event_ports;
 496         dev_info->max_event_port_dequeue_depth = 1;
 497         dev_info->max_event_port_enqueue_depth = 1;
 498         dev_info->max_num_events =  dev->max_num_events;
 499         dev_info->event_dev_cap = RTE_EVENT_DEV_CAP_QUEUE_QOS |
 500                                         RTE_EVENT_DEV_CAP_DISTRIBUTED_SCHED |
 501                                         RTE_EVENT_DEV_CAP_QUEUE_ALL_TYPES |
 502                                         RTE_EVENT_DEV_CAP_RUNTIME_PORT_LINK |
 503                                         RTE_EVENT_DEV_CAP_MULTIPLE_QUEUE_PORT |
 504                                         RTE_EVENT_DEV_CAP_NONSEQ_MODE;
 505 }
 506
 507 static void
 508 sso_port_link_modify(struct otx2_ssogws *ws, uint8_t queue, uint8_t enable)
 509 {
 510         uintptr_t base = OTX2_SSOW_GET_BASE_ADDR(ws->getwrk_op);
 511         uint64_t val;
 512
 513         val = queue;
 514         val |= 0ULL << 12; /* SET 0 */
 515         val |= 0x8000800080000000; /* Dont modify rest of the masks */
 516         val |= (uint64_t)enable << 14;   /* Enable/Disable Membership. */
 517
 518         otx2_write64(val, base + SSOW_LF_GWS_GRPMSK_CHG);
 519 }
 520
 521 static int
 522 otx2_sso_port_link(struct rte_eventdev *event_dev, void *port,
 523                    const uint8_t queues[], const uint8_t priorities[],
 524                    uint16_t nb_links)
 525 {
 526         struct otx2_sso_evdev *dev = sso_pmd_priv(event_dev);
 527         uint8_t port_id = 0;
 528         uint16_t link;
 529
 530         RTE_SET_USED(priorities);
 531         for (link = 0; link < nb_links; link++) {
 532                 if (dev->dual_ws) {
 533                         struct otx2_ssogws_dual *ws = port;
 534
 535                         port_id = ws->port;
 536                         sso_port_link_modify((struct otx2_ssogws *)
 537                                         &ws->ws_state[0], queues[link], true);
 538                         sso_port_link_modify((struct otx2_ssogws *)
 539                                         &ws->ws_state[1], queues[link], true);
 540                 } else {
 541                         struct otx2_ssogws *ws = port;
 542
 543                         port_id = ws->port;
 544                         sso_port_link_modify(ws, queues[link], true);
 545                 }
 546         }
 547         sso_func_trace("Port=%d nb_links=%d", port_id, nb_links);
 548
 549         return (int)nb_links;
 550 }
 551
 552 static int
 553 otx2_sso_port_unlink(struct rte_eventdev *event_dev, void *port,
 554                      uint8_t queues[], uint16_t nb_unlinks)
 555 {
 556         struct otx2_sso_evdev *dev = sso_pmd_priv(event_dev);
 557         uint8_t port_id = 0;
 558         uint16_t unlink;
 559
 560         for (unlink = 0; unlink < nb_unlinks; unlink++) {
 561                 if (dev->dual_ws) {
 562                         struct otx2_ssogws_dual *ws = port;
 563
 564                         port_id = ws->port;
 565                         sso_port_link_modify((struct otx2_ssogws *)
 566                                         &ws->ws_state[0], queues[unlink],
 567                                         false);
 568                         sso_port_link_modify((struct otx2_ssogws *)
 569                                         &ws->ws_state[1], queues[unlink],
 570                                         false);
 571                 } else {
 572                         struct otx2_ssogws *ws = port;
 573
 574                         port_id = ws->port;
 575                         sso_port_link_modify(ws, queues[unlink], false);
 576                 }
 577         }
 578         sso_func_trace("Port=%d nb_unlinks=%d", port_id, nb_unlinks);
 579
 580         return (int)nb_unlinks;
 581 }
 582
 583 static int
 584 sso_hw_lf_cfg(struct otx2_mbox *mbox, enum otx2_sso_lf_type type,
 585               uint16_t nb_lf, uint8_t attach)
 586 {
 587         if (attach) {
 588                 struct rsrc_attach_req *req;
 589
 590                 req = otx2_mbox_alloc_msg_attach_resources(mbox);
 591                 switch (type) {
 592                 case SSO_LF_GGRP:
 593                         req->sso = nb_lf;
 594                         break;
 595                 case SSO_LF_GWS:
 596                         req->ssow = nb_lf;
 597                         break;
 598                 default:
 599                         return -EINVAL;
 600                 }
 601                 req->modify = true;
 602                 if (otx2_mbox_process(mbox) < 0)
 603                         return -EIO;
 604         } else {
 605                 struct rsrc_detach_req *req;
 606
 607                 req = otx2_mbox_alloc_msg_detach_resources(mbox);
 608                 switch (type) {
 609                 case SSO_LF_GGRP:
 610                         req->sso = true;
 611                         break;
 612                 case SSO_LF_GWS:
 613                         req->ssow = true;
 614                         break;
 615                 default:
 616                         return -EINVAL;
 617                 }
 618                 req->partial = true;
 619                 if (otx2_mbox_process(mbox) < 0)
 620                         return -EIO;
 621         }
 622
 623         return 0;
 624 }
 625
 626 static int
 627 sso_lf_cfg(struct otx2_sso_evdev *dev, struct otx2_mbox *mbox,
 628            enum otx2_sso_lf_type type, uint16_t nb_lf, uint8_t alloc)
 629 {
 630         void *rsp;
 631         int rc;
 632
 633         if (alloc) {
 634                 switch (type) {
 635                 case SSO_LF_GGRP:
 636                         {
 637                         struct sso_lf_alloc_req *req_ggrp;
 638                         req_ggrp = otx2_mbox_alloc_msg_sso_lf_alloc(mbox);
 639                         req_ggrp->hwgrps = nb_lf;
 640                         }
 641                         break;
 642                 case SSO_LF_GWS:
 643                         {
 644                         struct ssow_lf_alloc_req *req_hws;
 645                         req_hws = otx2_mbox_alloc_msg_ssow_lf_alloc(mbox);
 646                         req_hws->hws = nb_lf;
 647                         }
 648                         break;
 649                 default:
 650                         return -EINVAL;
 651                 }
 652         } else {
 653                 switch (type) {
 654                 case SSO_LF_GGRP:
 655                         {
 656                         struct sso_lf_free_req *req_ggrp;
 657                         req_ggrp = otx2_mbox_alloc_msg_sso_lf_free(mbox);
 658                         req_ggrp->hwgrps = nb_lf;
 659                         }
 660                         break;
 661                 case SSO_LF_GWS:
 662                         {
 663                         struct ssow_lf_free_req *req_hws;
 664                         req_hws = otx2_mbox_alloc_msg_ssow_lf_free(mbox);
 665                         req_hws->hws = nb_lf;
 666                         }
 667                         break;
 668                 default:
 669                         return -EINVAL;
 670                 }
 671         }
 672
 673         rc = otx2_mbox_process_msg_tmo(mbox, (void **)&rsp, ~0);
 674         if (rc < 0)
 675                 return rc;
 676
 677         if (alloc && type == SSO_LF_GGRP) {
 678                 struct sso_lf_alloc_rsp *rsp_ggrp = rsp;
 679
 680                 dev->xaq_buf_size = rsp_ggrp->xaq_buf_size;
 681                 dev->xae_waes = rsp_ggrp->xaq_wq_entries;
 682                 dev->iue = rsp_ggrp->in_unit_entries;
 683         }
 684
 685         return 0;
 686 }
 687
 688 static void
 689 otx2_sso_port_release(void *port)
 690 {
 691         rte_free(port);
 692 }
 693
 694 static void
 695 otx2_sso_queue_release(struct rte_eventdev *event_dev, uint8_t queue_id)
 696 {
 697         RTE_SET_USED(event_dev);
 698         RTE_SET_USED(queue_id);
 699 }
 700
 701 static void
 702 sso_clr_links(const struct rte_eventdev *event_dev)
 703 {
 704         struct otx2_sso_evdev *dev = sso_pmd_priv(event_dev);
 705         int i, j;
 706
 707         for (i = 0; i < dev->nb_event_ports; i++) {
 708                 if (dev->dual_ws) {
 709                         struct otx2_ssogws_dual *ws;
 710
 711                         ws = event_dev->data->ports[i];
 712                         for (j = 0; j < dev->nb_event_queues; j++) {
 713                                 sso_port_link_modify((struct otx2_ssogws *)
 714                                                 &ws->ws_state[0], j, false);
 715                                 sso_port_link_modify((struct otx2_ssogws *)
 716                                                 &ws->ws_state[1], j, false);
 717                         }
 718                 } else {
 719                         struct otx2_ssogws *ws;
 720
 721                         ws = event_dev->data->ports[i];
 722                         for (j = 0; j < dev->nb_event_queues; j++)
 723                                 sso_port_link_modify(ws, j, false);
 724                 }
 725         }
 726 }
 727
 728 static void
 729 sso_restore_links(const struct rte_eventdev *event_dev)
 730 {
 731         struct otx2_sso_evdev *dev = sso_pmd_priv(event_dev);
 732         uint16_t *links_map;
 733         int i, j;
 734
 735         for (i = 0; i < dev->nb_event_ports; i++) {
 736                 links_map = event_dev->data->links_map;
 737                 /* Point links_map to this port specific area */
 738                 links_map += (i * RTE_EVENT_MAX_QUEUES_PER_DEV);
 739                 if (dev->dual_ws) {
 740                         struct otx2_ssogws_dual *ws;
 741
 742                         ws = event_dev->data->ports[i];
 743                         for (j = 0; j < dev->nb_event_queues; j++) {
 744                                 if (links_map[j] == 0xdead)
 745                                         continue;
 746                                 sso_port_link_modify((struct otx2_ssogws *)
 747                                                 &ws->ws_state[0], j, true);
 748                                 sso_port_link_modify((struct otx2_ssogws *)
 749                                                 &ws->ws_state[1], j, true);
 750                                 sso_func_trace("Restoring port %d queue %d "
 751                                                 "link", i, j);
 752                         }
 753                 } else {
 754                         struct otx2_ssogws *ws;
 755
 756                         ws = event_dev->data->ports[i];
 757                         for (j = 0; j < dev->nb_event_queues; j++) {
 758                                 if (links_map[j] == 0xdead)
 759                                         continue;
 760                                 sso_port_link_modify(ws, j, true);
 761                                 sso_func_trace("Restoring port %d queue %d "
 762                                                 "link", i, j);
 763                         }
 764                 }
 765         }
 766 }
 767
 768 static void
 769 sso_set_port_ops(struct otx2_ssogws *ws, uintptr_t base)
 770 {
 771         ws->tag_op              = base + SSOW_LF_GWS_TAG;
 772         ws->wqp_op              = base + SSOW_LF_GWS_WQP;
 773         ws->getwrk_op           = base + SSOW_LF_GWS_OP_GET_WORK;
 774         ws->swtp_op             = base + SSOW_LF_GWS_SWTP;
 775         ws->swtag_norm_op       = base + SSOW_LF_GWS_OP_SWTAG_NORM;
 776         ws->swtag_desched_op    = base + SSOW_LF_GWS_OP_SWTAG_DESCHED;
 777 }
 778
 779 static int
 780 sso_configure_dual_ports(const struct rte_eventdev *event_dev)
 781 {
 782         struct otx2_sso_evdev *dev = sso_pmd_priv(event_dev);
 783         struct otx2_mbox *mbox = dev->mbox;
 784         uint8_t vws = 0;
 785         uint8_t nb_lf;
 786         int i, rc;
 787
 788         otx2_sso_dbg("Configuring event ports %d", dev->nb_event_ports);
 789
 790         nb_lf = dev->nb_event_ports * 2;
 791         /* Ask AF to attach required LFs. */
 792         rc = sso_hw_lf_cfg(mbox, SSO_LF_GWS, nb_lf, true);
 793         if (rc < 0) {
 794                 otx2_err("Failed to attach SSO GWS LF");
 795                 return -ENODEV;
 796         }
 797
 798         if (sso_lf_cfg(dev, mbox, SSO_LF_GWS, nb_lf, true) < 0) {
 799                 sso_hw_lf_cfg(mbox, SSO_LF_GWS, nb_lf, false);
 800                 otx2_err("Failed to init SSO GWS LF");
 801                 return -ENODEV;
 802         }
 803
 804         for (i = 0; i < dev->nb_event_ports; i++) {
 805                 struct otx2_ssogws_dual *ws;
 806                 uintptr_t base;
 807
 808                 if (event_dev->data->ports[i] != NULL) {
 809                         ws = event_dev->data->ports[i];
 810                 } else {
 811                         /* Allocate event port memory */
 812                         ws = rte_zmalloc_socket("otx2_sso_ws",
 813                                         sizeof(struct otx2_ssogws_dual),
 814                                         RTE_CACHE_LINE_SIZE,
 815                                         event_dev->data->socket_id);
 816                 }
 817                 if (ws == NULL) {
 818                         otx2_err("Failed to alloc memory for port=%d", i);
 819                         rc = -ENOMEM;
 820                         break;
 821                 }
 822
 823                 ws->port = i;
 824                 base = dev->bar2 + (RVU_BLOCK_ADDR_SSOW << 20 | vws << 12);
 825                 sso_set_port_ops((struct otx2_ssogws *)&ws->ws_state[0], base);
 826                 vws++;
 827
 828                 base = dev->bar2 + (RVU_BLOCK_ADDR_SSOW << 20 | vws << 12);
 829                 sso_set_port_ops((struct otx2_ssogws *)&ws->ws_state[1], base);
 830                 vws++;
 831
 832                 event_dev->data->ports[i] = ws;
 833         }
 834
 835         if (rc < 0) {
 836                 sso_lf_cfg(dev, mbox, SSO_LF_GWS, nb_lf, false);
 837                 sso_hw_lf_cfg(mbox, SSO_LF_GWS, nb_lf, false);
 838         }
 839
 840         return rc;
 841 }
 842
 843 static int
 844 sso_configure_ports(const struct rte_eventdev *event_dev)
 845 {
 846         struct otx2_sso_evdev *dev = sso_pmd_priv(event_dev);
 847         struct otx2_mbox *mbox = dev->mbox;
 848         uint8_t nb_lf;
 849         int i, rc;
 850
 851         otx2_sso_dbg("Configuring event ports %d", dev->nb_event_ports);
 852
 853         nb_lf = dev->nb_event_ports;
 854         /* Ask AF to attach required LFs. */
 855         rc = sso_hw_lf_cfg(mbox, SSO_LF_GWS, nb_lf, true);
 856         if (rc < 0) {
 857                 otx2_err("Failed to attach SSO GWS LF");
 858                 return -ENODEV;
 859         }
 860
 861         if (sso_lf_cfg(dev, mbox, SSO_LF_GWS, nb_lf, true) < 0) {
 862                 sso_hw_lf_cfg(mbox, SSO_LF_GWS, nb_lf, false);
 863                 otx2_err("Failed to init SSO GWS LF");
 864                 return -ENODEV;
 865         }
 866
 867         for (i = 0; i < nb_lf; i++) {
 868                 struct otx2_ssogws *ws;
 869                 uintptr_t base;
 870
 871                 /* Free memory prior to re-allocation if needed */
 872                 if (event_dev->data->ports[i] != NULL) {
 873                         ws = event_dev->data->ports[i];
 874                         rte_free(ws);
 875                         ws = NULL;
 876                 }
 877
 878                 /* Allocate event port memory */
 879                 ws = rte_zmalloc_socket("otx2_sso_ws",
 880                                         sizeof(struct otx2_ssogws),
 881                                         RTE_CACHE_LINE_SIZE,
 882                                         event_dev->data->socket_id);
 883                 if (ws == NULL) {
 884                         otx2_err("Failed to alloc memory for port=%d", i);
 885                         rc = -ENOMEM;
 886                         break;
 887                 }
 888
 889                 ws->port = i;
 890                 base = dev->bar2 + (RVU_BLOCK_ADDR_SSOW << 20 | i << 12);
 891                 sso_set_port_ops(ws, base);
 892
 893                 event_dev->data->ports[i] = ws;
 894         }
 895
 896         if (rc < 0) {
 897                 sso_lf_cfg(dev, mbox, SSO_LF_GWS, nb_lf, false);
 898                 sso_hw_lf_cfg(mbox, SSO_LF_GWS, nb_lf, false);
 899         }
 900
 901         return rc;
 902 }
 903
 904 static int
 905 sso_configure_queues(const struct rte_eventdev *event_dev)
 906 {
 907         struct otx2_sso_evdev *dev = sso_pmd_priv(event_dev);
 908         struct otx2_mbox *mbox = dev->mbox;
 909         uint8_t nb_lf;
 910         int rc;
 911
 912         otx2_sso_dbg("Configuring event queues %d", dev->nb_event_queues);
 913
 914         nb_lf = dev->nb_event_queues;
 915         /* Ask AF to attach required LFs. */
 916         rc = sso_hw_lf_cfg(mbox, SSO_LF_GGRP, nb_lf, true);
 917         if (rc < 0) {
 918                 otx2_err("Failed to attach SSO GGRP LF");
 919                 return -ENODEV;
 920         }
 921
 922         if (sso_lf_cfg(dev, mbox, SSO_LF_GGRP, nb_lf, true) < 0) {
 923                 sso_hw_lf_cfg(mbox, SSO_LF_GGRP, nb_lf, false);
 924                 otx2_err("Failed to init SSO GGRP LF");
 925                 return -ENODEV;
 926         }
 927
 928         return rc;
 929 }
 930
 931 static int
 932 sso_xaq_allocate(struct otx2_sso_evdev *dev)
 933 {
 934         const struct rte_memzone *mz;
 935         struct npa_aura_s *aura;
 936         static int reconfig_cnt;
 937         char pool_name[RTE_MEMZONE_NAMESIZE];
 938         uint32_t xaq_cnt;
 939         int rc;
 940
 941         if (dev->xaq_pool)
 942                 rte_mempool_free(dev->xaq_pool);
 943
 944         /*
 945          * Allocate memory for Add work backpressure.
 946          */
 947         mz = rte_memzone_lookup(OTX2_SSO_FC_NAME);
 948         if (mz == NULL)
 949                 mz = rte_memzone_reserve_aligned(OTX2_SSO_FC_NAME,
 950                                                  OTX2_ALIGN +
 951                                                  sizeof(struct npa_aura_s),
 952                                                  rte_socket_id(),
 953                                                  RTE_MEMZONE_IOVA_CONTIG,
 954                                                  OTX2_ALIGN);
 955         if (mz == NULL) {
 956                 otx2_err("Failed to allocate mem for fcmem");
 957                 return -ENOMEM;
 958         }
 959
 960         dev->fc_iova = mz->iova;
 961         dev->fc_mem = mz->addr;
 962
 963         aura = (struct npa_aura_s *)((uintptr_t)dev->fc_mem + OTX2_ALIGN);
 964         memset(aura, 0, sizeof(struct npa_aura_s));
 965
 966         aura->fc_ena = 1;
 967         aura->fc_addr = dev->fc_iova;
 968         aura->fc_hyst_bits = 0; /* Store count on all updates */
 969
 970         /* Taken from HRM 14.3.3(4) */
 971         xaq_cnt = dev->nb_event_queues * OTX2_SSO_XAQ_CACHE_CNT;
 972         if (dev->xae_cnt)
 973                 xaq_cnt += dev->xae_cnt / dev->xae_waes;
 974         else if (dev->adptr_xae_cnt)
 975                 xaq_cnt += (dev->adptr_xae_cnt / dev->xae_waes) +
 976                         (OTX2_SSO_XAQ_SLACK * dev->nb_event_queues);
 977         else
 978                 xaq_cnt += (dev->iue / dev->xae_waes) +
 979                         (OTX2_SSO_XAQ_SLACK * dev->nb_event_queues);
 980
 981         otx2_sso_dbg("Configuring %d xaq buffers", xaq_cnt);
 982         /* Setup XAQ based on number of nb queues. */
 983         snprintf(pool_name, 30, "otx2_xaq_buf_pool_%d", reconfig_cnt);
 984         dev->xaq_pool = (void *)rte_mempool_create_empty(pool_name,
 985                         xaq_cnt, dev->xaq_buf_size, 0, 0,
 986                         rte_socket_id(), 0);
 987
 988         if (dev->xaq_pool == NULL) {
 989                 otx2_err("Unable to create empty mempool.");
 990                 rte_memzone_free(mz);
 991                 return -ENOMEM;
 992         }
 993
 994         rc = rte_mempool_set_ops_byname(dev->xaq_pool,
 995                                         rte_mbuf_platform_mempool_ops(), aura);
 996         if (rc != 0) {
 997                 otx2_err("Unable to set xaqpool ops.");
 998                 goto alloc_fail;
 999         }
1000
1001         rc = rte_mempool_populate_default(dev->xaq_pool);
1002         if (rc < 0) {
1003                 otx2_err("Unable to set populate xaqpool.");
1004                 goto alloc_fail;
1005         }
1006         reconfig_cnt++;
1007         /* When SW does addwork (enqueue) check if there is space in XAQ by
1008          * comparing fc_addr above against the xaq_lmt calculated below.
1009          * There should be a minimum headroom (OTX2_SSO_XAQ_SLACK / 2) for SSO
1010          * to request XAQ to cache them even before enqueue is called.
1011          */
1012         dev->xaq_lmt = xaq_cnt - (OTX2_SSO_XAQ_SLACK / 2 *
1013                                   dev->nb_event_queues);
1014         dev->nb_xaq_cfg = xaq_cnt;
1015
1016         return 0;
1017 alloc_fail:
1018         rte_mempool_free(dev->xaq_pool);
1019         rte_memzone_free(mz);
1020         return rc;
1021 }
1022
1023 static int
1024 sso_ggrp_alloc_xaq(struct otx2_sso_evdev *dev)
1025 {
1026         struct otx2_mbox *mbox = dev->mbox;
1027         struct sso_hw_setconfig *req;
1028
1029         otx2_sso_dbg("Configuring XAQ for GGRPs");
1030         req = otx2_mbox_alloc_msg_sso_hw_setconfig(mbox);
1031         req->npa_pf_func = otx2_npa_pf_func_get();
1032         req->npa_aura_id = npa_lf_aura_handle_to_aura(dev->xaq_pool->pool_id);
1033         req->hwgrps = dev->nb_event_queues;
1034
1035         return otx2_mbox_process(mbox);
1036 }
1037
1038 static void
1039 sso_lf_teardown(struct otx2_sso_evdev *dev,
1040                 enum otx2_sso_lf_type lf_type)
1041 {
1042         uint8_t nb_lf;
1043
1044         switch (lf_type) {
1045         case SSO_LF_GGRP:
1046                 nb_lf = dev->nb_event_queues;
1047                 break;
1048         case SSO_LF_GWS:
1049                 nb_lf = dev->nb_event_ports;
1050                 nb_lf *= dev->dual_ws ? 2 : 1;
1051                 break;
1052         default:
1053                 return;
1054         }
1055
1056         sso_lf_cfg(dev, dev->mbox, lf_type, nb_lf, false);
1057         sso_hw_lf_cfg(dev->mbox, lf_type, nb_lf, false);
1058 }
1059
1060 static int
1061 otx2_sso_configure(const struct rte_eventdev *event_dev)
1062 {
1063         struct rte_event_dev_config *conf = &event_dev->data->dev_conf;
1064         struct otx2_sso_evdev *dev = sso_pmd_priv(event_dev);
1065         uint32_t deq_tmo_ns;
1066         int rc;
1067
1068         sso_func_trace();
1069         deq_tmo_ns = conf->dequeue_timeout_ns;
1070
1071         if (deq_tmo_ns == 0)
1072                 deq_tmo_ns = dev->min_dequeue_timeout_ns;
1073
1074         if (deq_tmo_ns < dev->min_dequeue_timeout_ns ||
1075             deq_tmo_ns > dev->max_dequeue_timeout_ns) {
1076                 otx2_err("Unsupported dequeue timeout requested");
1077                 return -EINVAL;
1078         }
1079
1080         if (conf->event_dev_cfg & RTE_EVENT_DEV_CFG_PER_DEQUEUE_TIMEOUT)
1081                 dev->is_timeout_deq = 1;
1082
1083         dev->deq_tmo_ns = deq_tmo_ns;
1084
1085         if (conf->nb_event_ports > dev->max_event_ports ||
1086             conf->nb_event_queues > dev->max_event_queues) {
1087                 otx2_err("Unsupported event queues/ports requested");
1088                 return -EINVAL;
1089         }
1090
1091         if (conf->nb_event_port_dequeue_depth > 1) {
1092                 otx2_err("Unsupported event port deq depth requested");
1093                 return -EINVAL;
1094         }
1095
1096         if (conf->nb_event_port_enqueue_depth > 1) {
1097                 otx2_err("Unsupported event port enq depth requested");
1098                 return -EINVAL;
1099         }
1100
1101         if (dev->configured) {
1102                 sso_unregister_irqs(event_dev);
1103                 /* Clear any prior port-queue mapping. */
1104                 sso_clr_links(event_dev);
1105         }
1106
1107         if (dev->nb_event_queues) {
1108                 /* Finit any previous queues. */
1109                 sso_lf_teardown(dev, SSO_LF_GGRP);
1110         }
1111         if (dev->nb_event_ports) {
1112                 /* Finit any previous ports. */
1113                 sso_lf_teardown(dev, SSO_LF_GWS);
1114         }
1115
1116         dev->nb_event_queues = conf->nb_event_queues;
1117         dev->nb_event_ports = conf->nb_event_ports;
1118
1119         if (dev->dual_ws)
1120                 rc = sso_configure_dual_ports(event_dev);
1121         else
1122                 rc = sso_configure_ports(event_dev);
1123
1124         if (rc < 0) {
1125                 otx2_err("Failed to configure event ports");
1126                 return -ENODEV;
1127         }
1128
1129         if (sso_configure_queues(event_dev) < 0) {
1130                 otx2_err("Failed to configure event queues");
1131                 rc = -ENODEV;
1132                 goto teardown_hws;
1133         }
1134
1135         if (sso_xaq_allocate(dev) < 0) {
1136                 rc = -ENOMEM;
1137                 goto teardown_hwggrp;
1138         }
1139
1140         /* Restore any prior port-queue mapping. */
1141         sso_restore_links(event_dev);
1142         rc = sso_ggrp_alloc_xaq(dev);
1143         if (rc < 0) {
1144                 otx2_err("Failed to alloc xaq to ggrp %d", rc);
1145                 goto teardown_hwggrp;
1146         }
1147
1148         rc = sso_get_msix_offsets(event_dev);
1149         if (rc < 0) {
1150                 otx2_err("Failed to get msix offsets %d", rc);
1151                 goto teardown_hwggrp;
1152         }
1153
1154         rc = sso_register_irqs(event_dev);
1155         if (rc < 0) {
1156                 otx2_err("Failed to register irq %d", rc);
1157                 goto teardown_hwggrp;
1158         }
1159
1160         dev->configured = 1;
1161         rte_mb();
1162
1163         return 0;
1164 teardown_hwggrp:
1165         sso_lf_teardown(dev, SSO_LF_GGRP);
1166 teardown_hws:
1167         sso_lf_teardown(dev, SSO_LF_GWS);
1168         dev->nb_event_queues = 0;
1169         dev->nb_event_ports = 0;
1170         dev->configured = 0;
1171         return rc;
1172 }
1173
1174 static void
1175 otx2_sso_queue_def_conf(struct rte_eventdev *event_dev, uint8_t queue_id,
1176                         struct rte_event_queue_conf *queue_conf)
1177 {
1178         RTE_SET_USED(event_dev);
1179         RTE_SET_USED(queue_id);
1180
1181         queue_conf->nb_atomic_flows = (1ULL << 20);
1182         queue_conf->nb_atomic_order_sequences = (1ULL << 20);
1183         queue_conf->event_queue_cfg = RTE_EVENT_QUEUE_CFG_ALL_TYPES;
1184         queue_conf->priority = RTE_EVENT_DEV_PRIORITY_NORMAL;
1185 }
1186
1187 static int
1188 otx2_sso_queue_setup(struct rte_eventdev *event_dev, uint8_t queue_id,
1189                      const struct rte_event_queue_conf *queue_conf)
1190 {
1191         struct otx2_sso_evdev *dev = sso_pmd_priv(event_dev);
1192         struct otx2_mbox *mbox = dev->mbox;
1193         struct sso_grp_priority *req;
1194         int rc;
1195
1196         sso_func_trace("Queue=%d prio=%d", queue_id, queue_conf->priority);
1197
1198         req = otx2_mbox_alloc_msg_sso_grp_set_priority(dev->mbox);
1199         req->grp = queue_id;
1200         req->weight = 0xFF;
1201         req->affinity = 0xFF;
1202         /* Normalize <0-255> to <0-7> */
1203         req->priority = queue_conf->priority / 32;
1204
1205         rc = otx2_mbox_process(mbox);
1206         if (rc < 0) {
1207                 otx2_err("Failed to set priority queue=%d", queue_id);
1208                 return rc;
1209         }
1210
1211         return 0;
1212 }
1213
1214 static void
1215 otx2_sso_port_def_conf(struct rte_eventdev *event_dev, uint8_t port_id,
1216                        struct rte_event_port_conf *port_conf)
1217 {
1218         struct otx2_sso_evdev *dev = sso_pmd_priv(event_dev);
1219
1220         RTE_SET_USED(port_id);
1221         port_conf->new_event_threshold = dev->max_num_events;
1222         port_conf->dequeue_depth = 1;
1223         port_conf->enqueue_depth = 1;
1224 }
1225
1226 static int
1227 otx2_sso_port_setup(struct rte_eventdev *event_dev, uint8_t port_id,
1228                     const struct rte_event_port_conf *port_conf)
1229 {
1230         struct otx2_sso_evdev *dev = sso_pmd_priv(event_dev);
1231         uintptr_t grps_base[OTX2_SSO_MAX_VHGRP] = {0};
1232         uint64_t val;
1233         uint16_t q;
1234
1235         sso_func_trace("Port=%d", port_id);
1236         RTE_SET_USED(port_conf);
1237
1238         if (event_dev->data->ports[port_id] == NULL) {
1239                 otx2_err("Invalid port Id %d", port_id);
1240                 return -EINVAL;
1241         }
1242
1243         for (q = 0; q < dev->nb_event_queues; q++) {
1244                 grps_base[q] = dev->bar2 + (RVU_BLOCK_ADDR_SSO << 20 | q << 12);
1245                 if (grps_base[q] == 0) {
1246                         otx2_err("Failed to get grp[%d] base addr", q);
1247                         return -EINVAL;
1248                 }
1249         }
1250
1251         /* Set get_work timeout for HWS */
1252         val = NSEC2USEC(dev->deq_tmo_ns) - 1;
1253
1254         if (dev->dual_ws) {
1255                 struct otx2_ssogws_dual *ws = event_dev->data->ports[port_id];
1256
1257                 rte_memcpy(ws->grps_base, grps_base,
1258                            sizeof(uintptr_t) * OTX2_SSO_MAX_VHGRP);
1259                 ws->fc_mem = dev->fc_mem;
1260                 ws->xaq_lmt = dev->xaq_lmt;
1261                 ws->tstamp = dev->tstamp;
1262                 otx2_write64(val, OTX2_SSOW_GET_BASE_ADDR(
1263                              ws->ws_state[0].getwrk_op) + SSOW_LF_GWS_NW_TIM);
1264                 otx2_write64(val, OTX2_SSOW_GET_BASE_ADDR(
1265                              ws->ws_state[1].getwrk_op) + SSOW_LF_GWS_NW_TIM);
1266         } else {
1267                 struct otx2_ssogws *ws = event_dev->data->ports[port_id];
1268                 uintptr_t base = OTX2_SSOW_GET_BASE_ADDR(ws->getwrk_op);
1269
1270                 rte_memcpy(ws->grps_base, grps_base,
1271                            sizeof(uintptr_t) * OTX2_SSO_MAX_VHGRP);
1272                 ws->fc_mem = dev->fc_mem;
1273                 ws->xaq_lmt = dev->xaq_lmt;
1274                 ws->tstamp = dev->tstamp;
1275                 otx2_write64(val, base + SSOW_LF_GWS_NW_TIM);
1276         }
1277
1278         otx2_sso_dbg("Port=%d ws=%p", port_id, event_dev->data->ports[port_id]);
1279
1280         return 0;
1281 }
1282
1283 static int
1284 otx2_sso_timeout_ticks(struct rte_eventdev *event_dev, uint64_t ns,
1285                        uint64_t *tmo_ticks)
1286 {
1287         RTE_SET_USED(event_dev);
1288         *tmo_ticks = NSEC2TICK(ns, rte_get_timer_hz());
1289
1290         return 0;
1291 }
1292
1293 static void
1294 ssogws_dump(struct otx2_ssogws *ws, FILE *f)
1295 {
1296         uintptr_t base = OTX2_SSOW_GET_BASE_ADDR(ws->getwrk_op);
1297
1298         fprintf(f, "SSOW_LF_GWS Base addr   0x%" PRIx64 "\n", (uint64_t)base);
1299         fprintf(f, "SSOW_LF_GWS_LINKS       0x%" PRIx64 "\n",
1300                 otx2_read64(base + SSOW_LF_GWS_LINKS));
1301         fprintf(f, "SSOW_LF_GWS_PENDWQP     0x%" PRIx64 "\n",
1302                 otx2_read64(base + SSOW_LF_GWS_PENDWQP));
1303         fprintf(f, "SSOW_LF_GWS_PENDSTATE   0x%" PRIx64 "\n",
1304                 otx2_read64(base + SSOW_LF_GWS_PENDSTATE));
1305         fprintf(f, "SSOW_LF_GWS_NW_TIM      0x%" PRIx64 "\n",
1306                 otx2_read64(base + SSOW_LF_GWS_NW_TIM));
1307         fprintf(f, "SSOW_LF_GWS_TAG         0x%" PRIx64 "\n",
1308                 otx2_read64(base + SSOW_LF_GWS_TAG));
1309         fprintf(f, "SSOW_LF_GWS_WQP         0x%" PRIx64 "\n",
1310                 otx2_read64(base + SSOW_LF_GWS_TAG));
1311         fprintf(f, "SSOW_LF_GWS_SWTP        0x%" PRIx64 "\n",
1312                 otx2_read64(base + SSOW_LF_GWS_SWTP));
1313         fprintf(f, "SSOW_LF_GWS_PENDTAG     0x%" PRIx64 "\n",
1314                 otx2_read64(base + SSOW_LF_GWS_PENDTAG));
1315 }
1316
1317 static void
1318 ssoggrp_dump(uintptr_t base, FILE *f)
1319 {
1320         fprintf(f, "SSO_LF_GGRP Base addr   0x%" PRIx64 "\n", (uint64_t)base);
1321         fprintf(f, "SSO_LF_GGRP_QCTL        0x%" PRIx64 "\n",
1322                 otx2_read64(base + SSO_LF_GGRP_QCTL));
1323         fprintf(f, "SSO_LF_GGRP_XAQ_CNT     0x%" PRIx64 "\n",
1324                 otx2_read64(base + SSO_LF_GGRP_XAQ_CNT));
1325         fprintf(f, "SSO_LF_GGRP_INT_THR     0x%" PRIx64 "\n",
1326                 otx2_read64(base + SSO_LF_GGRP_INT_THR));
1327         fprintf(f, "SSO_LF_GGRP_INT_CNT     0x%" PRIX64 "\n",
1328                 otx2_read64(base + SSO_LF_GGRP_INT_CNT));
1329         fprintf(f, "SSO_LF_GGRP_AQ_CNT      0x%" PRIX64 "\n",
1330                 otx2_read64(base + SSO_LF_GGRP_AQ_CNT));
1331         fprintf(f, "SSO_LF_GGRP_AQ_THR      0x%" PRIX64 "\n",
1332                 otx2_read64(base + SSO_LF_GGRP_AQ_THR));
1333         fprintf(f, "SSO_LF_GGRP_MISC_CNT    0x%" PRIx64 "\n",
1334                 otx2_read64(base + SSO_LF_GGRP_MISC_CNT));
1335 }
1336
1337 static void
1338 otx2_sso_dump(struct rte_eventdev *event_dev, FILE *f)
1339 {
1340         struct otx2_sso_evdev *dev = sso_pmd_priv(event_dev);
1341         uint8_t queue;
1342         uint8_t port;
1343
1344         fprintf(f, "[%s] SSO running in [%s] mode\n", __func__, dev->dual_ws ?
1345                 "dual_ws" : "single_ws");
1346         /* Dump SSOW registers */
1347         for (port = 0; port < dev->nb_event_ports; port++) {
1348                 if (dev->dual_ws) {
1349                         struct otx2_ssogws_dual *ws =
1350                                 event_dev->data->ports[port];
1351
1352                         fprintf(f, "[%s] SSO dual workslot[%d] vws[%d] dump\n",
1353                                 __func__, port, 0);
1354                         ssogws_dump((struct otx2_ssogws *)&ws->ws_state[0], f);
1355                         fprintf(f, "[%s]SSO dual workslot[%d] vws[%d] dump\n",
1356                                 __func__, port, 1);
1357                         ssogws_dump((struct otx2_ssogws *)&ws->ws_state[1], f);
1358                 } else {
1359                         fprintf(f, "[%s]SSO single workslot[%d] dump\n",
1360                                 __func__, port);
1361                         ssogws_dump(event_dev->data->ports[port], f);
1362                 }
1363         }
1364
1365         /* Dump SSO registers */
1366         for (queue = 0; queue < dev->nb_event_queues; queue++) {
1367                 fprintf(f, "[%s]SSO group[%d] dump\n", __func__, queue);
1368                 if (dev->dual_ws) {
1369                         struct otx2_ssogws_dual *ws = event_dev->data->ports[0];
1370                         ssoggrp_dump(ws->grps_base[queue], f);
1371                 } else {
1372                         struct otx2_ssogws *ws = event_dev->data->ports[0];
1373                         ssoggrp_dump(ws->grps_base[queue], f);
1374                 }
1375         }
1376 }
1377
1378 static void
1379 otx2_handle_event(void *arg, struct rte_event event)
1380 {
1381         struct rte_eventdev *event_dev = arg;
1382
1383         if (event_dev->dev_ops->dev_stop_flush != NULL)
1384                 event_dev->dev_ops->dev_stop_flush(event_dev->data->dev_id,
1385                                 event, event_dev->data->dev_stop_flush_arg);
1386 }
1387
1388 static void
1389 sso_qos_cfg(struct rte_eventdev *event_dev)
1390 {
1391         struct otx2_sso_evdev *dev = sso_pmd_priv(event_dev);
1392         struct sso_grp_qos_cfg *req;
1393         uint16_t i;
1394
1395         for (i = 0; i < dev->qos_queue_cnt; i++) {
1396                 uint8_t xaq_prcnt = dev->qos_parse_data[i].xaq_prcnt;
1397                 uint8_t iaq_prcnt = dev->qos_parse_data[i].iaq_prcnt;
1398                 uint8_t taq_prcnt = dev->qos_parse_data[i].taq_prcnt;
1399
1400                 if (dev->qos_parse_data[i].queue >= dev->nb_event_queues)
1401                         continue;
1402
1403                 req = otx2_mbox_alloc_msg_sso_grp_qos_config(dev->mbox);
1404                 req->xaq_limit = (dev->nb_xaq_cfg *
1405                                   (xaq_prcnt ? xaq_prcnt : 100)) / 100;
1406                 req->taq_thr = (SSO_HWGRP_IAQ_MAX_THR_MASK *
1407                                 (iaq_prcnt ? iaq_prcnt : 100)) / 100;
1408                 req->iaq_thr = (SSO_HWGRP_TAQ_MAX_THR_MASK *
1409                                 (taq_prcnt ? taq_prcnt : 100)) / 100;
1410         }
1411
1412         if (dev->qos_queue_cnt)
1413                 otx2_mbox_process(dev->mbox);
1414 }
1415
1416 static void
1417 sso_cleanup(struct rte_eventdev *event_dev, uint8_t enable)
1418 {
1419         struct otx2_sso_evdev *dev = sso_pmd_priv(event_dev);
1420         uint16_t i;
1421
1422         for (i = 0; i < dev->nb_event_ports; i++) {
1423                 if (dev->dual_ws) {
1424                         struct otx2_ssogws_dual *ws;
1425
1426                         ws = event_dev->data->ports[i];
1427                         ssogws_reset((struct otx2_ssogws *)&ws->ws_state[0]);
1428                         ssogws_reset((struct otx2_ssogws *)&ws->ws_state[1]);
1429                         ws->swtag_req = 0;
1430                         ws->vws = 0;
1431                         ws->ws_state[0].cur_grp = 0;
1432                         ws->ws_state[0].cur_tt = SSO_SYNC_EMPTY;
1433                         ws->ws_state[1].cur_grp = 0;
1434                         ws->ws_state[1].cur_tt = SSO_SYNC_EMPTY;
1435                 } else {
1436                         struct otx2_ssogws *ws;
1437
1438                         ws = event_dev->data->ports[i];
1439                         ssogws_reset(ws);
1440                         ws->swtag_req = 0;
1441                         ws->cur_grp = 0;
1442                         ws->cur_tt = SSO_SYNC_EMPTY;
1443                 }
1444         }
1445
1446         rte_mb();
1447         if (dev->dual_ws) {
1448                 struct otx2_ssogws_dual *ws = event_dev->data->ports[0];
1449                 struct otx2_ssogws temp_ws;
1450
1451                 memcpy(&temp_ws, &ws->ws_state[0],
1452                        sizeof(struct otx2_ssogws_state));
1453                 for (i = 0; i < dev->nb_event_queues; i++) {
1454                         /* Consume all the events through HWS0 */
1455                         ssogws_flush_events(&temp_ws, i, ws->grps_base[i],
1456                                             otx2_handle_event, event_dev);
1457                         /* Enable/Disable SSO GGRP */
1458                         otx2_write64(enable, ws->grps_base[i] +
1459                                      SSO_LF_GGRP_QCTL);
1460                 }
1461                 ws->ws_state[0].cur_grp = 0;
1462                 ws->ws_state[0].cur_tt = SSO_SYNC_EMPTY;
1463         } else {
1464                 struct otx2_ssogws *ws = event_dev->data->ports[0];
1465
1466                 for (i = 0; i < dev->nb_event_queues; i++) {
1467                         /* Consume all the events through HWS0 */
1468                         ssogws_flush_events(ws, i, ws->grps_base[i],
1469                                             otx2_handle_event, event_dev);
1470                         /* Enable/Disable SSO GGRP */
1471                         otx2_write64(enable, ws->grps_base[i] +
1472                                      SSO_LF_GGRP_QCTL);
1473                 }
1474                 ws->cur_grp = 0;
1475                 ws->cur_tt = SSO_SYNC_EMPTY;
1476         }
1477
1478         /* reset SSO GWS cache */
1479         otx2_mbox_alloc_msg_sso_ws_cache_inv(dev->mbox);
1480         otx2_mbox_process(dev->mbox);
1481 }
1482
1483 int
1484 sso_xae_reconfigure(struct rte_eventdev *event_dev)
1485 {
1486         struct otx2_sso_evdev *dev = sso_pmd_priv(event_dev);
1487         struct rte_mempool *prev_xaq_pool;
1488         int rc = 0;
1489
1490         if (event_dev->data->dev_started)
1491                 sso_cleanup(event_dev, 0);
1492
1493         prev_xaq_pool = dev->xaq_pool;
1494         dev->xaq_pool = NULL;
1495         rc = sso_xaq_allocate(dev);
1496         if (rc < 0) {
1497                 otx2_err("Failed to alloc xaq pool %d", rc);
1498                 rte_mempool_free(prev_xaq_pool);
1499                 return rc;
1500         }
1501         rc = sso_ggrp_alloc_xaq(dev);
1502         if (rc < 0) {
1503                 otx2_err("Failed to alloc xaq to ggrp %d", rc);
1504                 rte_mempool_free(prev_xaq_pool);
1505                 return rc;
1506         }
1507
1508         rte_mempool_free(prev_xaq_pool);
1509         rte_mb();
1510         if (event_dev->data->dev_started)
1511                 sso_cleanup(event_dev, 1);
1512
1513         return 0;
1514 }
1515
1516 static int
1517 otx2_sso_start(struct rte_eventdev *event_dev)
1518 {
1519         sso_func_trace();
1520         sso_qos_cfg(event_dev);
1521         sso_cleanup(event_dev, 1);
1522         sso_fastpath_fns_set(event_dev);
1523
1524         return 0;
1525 }
1526
1527 static void
1528 otx2_sso_stop(struct rte_eventdev *event_dev)
1529 {
1530         sso_func_trace();
1531         sso_cleanup(event_dev, 0);
1532         rte_mb();
1533 }
1534
1535 static int
1536 otx2_sso_close(struct rte_eventdev *event_dev)
1537 {
1538         struct otx2_sso_evdev *dev = sso_pmd_priv(event_dev);
1539         uint8_t all_queues[RTE_EVENT_MAX_QUEUES_PER_DEV];
1540         uint16_t i;
1541
1542         if (!dev->configured)
1543                 return 0;
1544
1545         sso_unregister_irqs(event_dev);
1546
1547         for (i = 0; i < dev->nb_event_queues; i++)
1548                 all_queues[i] = i;
1549
1550         for (i = 0; i < dev->nb_event_ports; i++)
1551                 otx2_sso_port_unlink(event_dev, event_dev->data->ports[i],
1552                                      all_queues, dev->nb_event_queues);
1553
1554         sso_lf_teardown(dev, SSO_LF_GGRP);
1555         sso_lf_teardown(dev, SSO_LF_GWS);
1556         dev->nb_event_ports = 0;
1557         dev->nb_event_queues = 0;
1558         rte_mempool_free(dev->xaq_pool);
1559         rte_memzone_free(rte_memzone_lookup(OTX2_SSO_FC_NAME));
1560
1561         return 0;
1562 }
1563
1564 /* Initialize and register event driver with DPDK Application */
1565 static struct rte_eventdev_ops otx2_sso_ops = {
1566         .dev_infos_get    = otx2_sso_info_get,
1567         .dev_configure    = otx2_sso_configure,
1568         .queue_def_conf   = otx2_sso_queue_def_conf,
1569         .queue_setup      = otx2_sso_queue_setup,
1570         .queue_release    = otx2_sso_queue_release,
1571         .port_def_conf    = otx2_sso_port_def_conf,
1572         .port_setup       = otx2_sso_port_setup,
1573         .port_release     = otx2_sso_port_release,
1574         .port_link        = otx2_sso_port_link,
1575         .port_unlink      = otx2_sso_port_unlink,
1576         .timeout_ticks    = otx2_sso_timeout_ticks,
1577
1578         .eth_rx_adapter_caps_get  = otx2_sso_rx_adapter_caps_get,
1579         .eth_rx_adapter_queue_add = otx2_sso_rx_adapter_queue_add,
1580         .eth_rx_adapter_queue_del = otx2_sso_rx_adapter_queue_del,
1581         .eth_rx_adapter_start = otx2_sso_rx_adapter_start,
1582         .eth_rx_adapter_stop = otx2_sso_rx_adapter_stop,
1583
1584         .eth_tx_adapter_caps_get = otx2_sso_tx_adapter_caps_get,
1585         .eth_tx_adapter_queue_add = otx2_sso_tx_adapter_queue_add,
1586         .eth_tx_adapter_queue_del = otx2_sso_tx_adapter_queue_del,
1587
1588         .timer_adapter_caps_get = otx2_tim_caps_get,
1589
1590         .xstats_get       = otx2_sso_xstats_get,
1591         .xstats_reset     = otx2_sso_xstats_reset,
1592         .xstats_get_names = otx2_sso_xstats_get_names,
1593
1594         .dump             = otx2_sso_dump,
1595         .dev_start        = otx2_sso_start,
1596         .dev_stop         = otx2_sso_stop,
1597         .dev_close        = otx2_sso_close,
1598         .dev_selftest     = otx2_sso_selftest,
1599 };
1600
1601 #define OTX2_SSO_XAE_CNT        "xae_cnt"
1602 #define OTX2_SSO_SINGLE_WS      "single_ws"
1603 #define OTX2_SSO_GGRP_QOS       "qos"
1604 #define OTX2_SSO_SELFTEST       "selftest"
1605
1606 static void
1607 parse_queue_param(char *value, void *opaque)
1608 {
1609         struct otx2_sso_qos queue_qos = {0};
1610         uint8_t *val = (uint8_t *)&queue_qos;
1611         struct otx2_sso_evdev *dev = opaque;
1612         char *tok = strtok(value, "-");
1613         struct otx2_sso_qos *old_ptr;
1614
1615         if (!strlen(value))
1616                 return;
1617
1618         while (tok != NULL) {
1619                 *val = atoi(tok);
1620                 tok = strtok(NULL, "-");
1621                 val++;
1622         }
1623
1624         if (val != (&queue_qos.iaq_prcnt + 1)) {
1625                 otx2_err("Invalid QoS parameter expected [Qx-XAQ-TAQ-IAQ]");
1626                 return;
1627         }
1628
1629         dev->qos_queue_cnt++;
1630         old_ptr = dev->qos_parse_data;
1631         dev->qos_parse_data = rte_realloc(dev->qos_parse_data,
1632                                           sizeof(struct otx2_sso_qos) *
1633                                           dev->qos_queue_cnt, 0);
1634         if (dev->qos_parse_data == NULL) {
1635                 dev->qos_parse_data = old_ptr;
1636                 dev->qos_queue_cnt--;
1637                 return;
1638         }
1639         dev->qos_parse_data[dev->qos_queue_cnt - 1] = queue_qos;
1640 }
1641
1642 static void
1643 parse_qos_list(const char *value, void *opaque)
1644 {
1645         char *s = strdup(value);
1646         char *start = NULL;
1647         char *end = NULL;
1648         char *f = s;
1649
1650         while (*s) {
1651                 if (*s == '[')
1652                         start = s;
1653                 else if (*s == ']')
1654                         end = s;
1655
1656                 if (start && start < end) {
1657                         *end = 0;
1658                         parse_queue_param(start + 1, opaque);
1659                         s = end;
1660                         start = end;
1661                 }
1662                 s++;
1663         }
1664
1665         free(f);
1666 }
1667
1668 static int
1669 parse_sso_kvargs_dict(const char *key, const char *value, void *opaque)
1670 {
1671         RTE_SET_USED(key);
1672
1673         /* Dict format [Qx-XAQ-TAQ-IAQ][Qz-XAQ-TAQ-IAQ] use '-' cause ','
1674          * isn't allowed. Everything is expressed in percentages, 0 represents
1675          * default.
1676          */
1677         parse_qos_list(value, opaque);
1678
1679         return 0;
1680 }
1681
1682 static void
1683 sso_parse_devargs(struct otx2_sso_evdev *dev, struct rte_devargs *devargs)
1684 {
1685         struct rte_kvargs *kvlist;
1686         uint8_t single_ws = 0;
1687
1688         if (devargs == NULL)
1689                 return;
1690         kvlist = rte_kvargs_parse(devargs->args, NULL);
1691         if (kvlist == NULL)
1692                 return;
1693
1694         rte_kvargs_process(kvlist, OTX2_SSO_SELFTEST, &parse_kvargs_flag,
1695                            &dev->selftest);
1696         rte_kvargs_process(kvlist, OTX2_SSO_XAE_CNT, &parse_kvargs_value,
1697                            &dev->xae_cnt);
1698         rte_kvargs_process(kvlist, OTX2_SSO_SINGLE_WS, &parse_kvargs_flag,
1699                            &single_ws);
1700         rte_kvargs_process(kvlist, OTX2_SSO_GGRP_QOS, &parse_sso_kvargs_dict,
1701                            dev);
1702         otx2_parse_common_devargs(kvlist);
1703         dev->dual_ws = !single_ws;
1704         rte_kvargs_free(kvlist);
1705 }
1706
1707 static int
1708 otx2_sso_probe(struct rte_pci_driver *pci_drv, struct rte_pci_device *pci_dev)
1709 {
1710         return rte_event_pmd_pci_probe(pci_drv, pci_dev,
1711                                        sizeof(struct otx2_sso_evdev),
1712                                        otx2_sso_init);
1713 }
1714
1715 static int
1716 otx2_sso_remove(struct rte_pci_device *pci_dev)
1717 {
1718         return rte_event_pmd_pci_remove(pci_dev, otx2_sso_fini);
1719 }
1720
1721 static const struct rte_pci_id pci_sso_map[] = {
1722         {
1723                 RTE_PCI_DEVICE(PCI_VENDOR_ID_CAVIUM,
1724                                PCI_DEVID_OCTEONTX2_RVU_SSO_TIM_PF)
1725         },
1726         {
1727                 .vendor_id = 0,
1728         },
1729 };
1730
1731 static struct rte_pci_driver pci_sso = {
1732         .id_table = pci_sso_map,
1733         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_NEED_IOVA_AS_VA,
1734         .probe = otx2_sso_probe,
1735         .remove = otx2_sso_remove,
1736 };
1737
1738 int
1739 otx2_sso_init(struct rte_eventdev *event_dev)
1740 {
1741         struct free_rsrcs_rsp *rsrc_cnt;
1742         struct rte_pci_device *pci_dev;
1743         struct otx2_sso_evdev *dev;
1744         int rc;
1745
1746         event_dev->dev_ops = &otx2_sso_ops;
1747         /* For secondary processes, the primary has done all the work */
1748         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
1749                 sso_fastpath_fns_set(event_dev);
1750                 return 0;
1751         }
1752
1753         dev = sso_pmd_priv(event_dev);
1754
1755         pci_dev = container_of(event_dev->dev, struct rte_pci_device, device);
1756
1757         /* Initialize the base otx2_dev object */
1758         rc = otx2_dev_init(pci_dev, dev);
1759         if (rc < 0) {
1760                 otx2_err("Failed to initialize otx2_dev rc=%d", rc);
1761                 goto error;
1762         }
1763
1764         /* Get SSO and SSOW MSIX rsrc cnt */
1765         otx2_mbox_alloc_msg_free_rsrc_cnt(dev->mbox);
1766         rc = otx2_mbox_process_msg(dev->mbox, (void *)&rsrc_cnt);
1767         if (rc < 0) {
1768                 otx2_err("Unable to get free rsrc count");
1769                 goto otx2_dev_uninit;
1770         }
1771         otx2_sso_dbg("SSO %d SSOW %d NPA %d provisioned", rsrc_cnt->sso,
1772                      rsrc_cnt->ssow, rsrc_cnt->npa);
1773
1774         dev->max_event_ports = RTE_MIN(rsrc_cnt->ssow, OTX2_SSO_MAX_VHWS);
1775         dev->max_event_queues = RTE_MIN(rsrc_cnt->sso, OTX2_SSO_MAX_VHGRP);
1776         /* Grab the NPA LF if required */
1777         rc = otx2_npa_lf_init(pci_dev, dev);
1778         if (rc < 0) {
1779                 otx2_err("Unable to init NPA lf. It might not be provisioned");
1780                 goto otx2_dev_uninit;
1781         }
1782
1783         dev->drv_inited = true;
1784         dev->is_timeout_deq = 0;
1785         dev->min_dequeue_timeout_ns = USEC2NSEC(1);
1786         dev->max_dequeue_timeout_ns = USEC2NSEC(0x3FF);
1787         dev->max_num_events = -1;
1788         dev->nb_event_queues = 0;
1789         dev->nb_event_ports = 0;
1790
1791         if (!dev->max_event_ports || !dev->max_event_queues) {
1792                 otx2_err("Not enough eventdev resource queues=%d ports=%d",
1793                          dev->max_event_queues, dev->max_event_ports);
1794                 rc = -ENODEV;
1795                 goto otx2_npa_lf_uninit;
1796         }
1797
1798         dev->dual_ws = 1;
1799         sso_parse_devargs(dev, pci_dev->device.devargs);
1800         if (dev->dual_ws) {
1801                 otx2_sso_dbg("Using dual workslot mode");
1802                 dev->max_event_ports = dev->max_event_ports / 2;
1803         } else {
1804                 otx2_sso_dbg("Using single workslot mode");
1805         }
1806
1807         otx2_sso_pf_func_set(dev->pf_func);
1808         otx2_sso_dbg("Initializing %s max_queues=%d max_ports=%d",
1809                      event_dev->data->name, dev->max_event_queues,
1810                      dev->max_event_ports);
1811         if (dev->selftest) {
1812                 event_dev->dev->driver = &pci_sso.driver;
1813                 event_dev->dev_ops->dev_selftest();
1814         }
1815
1816         otx2_tim_init(pci_dev, (struct otx2_dev *)dev);
1817
1818         return 0;
1819
1820 otx2_npa_lf_uninit:
1821         otx2_npa_lf_fini();
1822 otx2_dev_uninit:
1823         otx2_dev_fini(pci_dev, dev);
1824 error:
1825         return rc;
1826 }
1827
1828 int
1829 otx2_sso_fini(struct rte_eventdev *event_dev)
1830 {
1831         struct otx2_sso_evdev *dev = sso_pmd_priv(event_dev);
1832         struct rte_pci_device *pci_dev;
1833
1834         /* For secondary processes, nothing to be done */
1835         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1836                 return 0;
1837
1838         pci_dev = container_of(event_dev->dev, struct rte_pci_device, device);
1839
1840         if (!dev->drv_inited)
1841                 goto dev_fini;
1842
1843         dev->drv_inited = false;
1844         otx2_npa_lf_fini();
1845
1846 dev_fini:
1847         if (otx2_npa_lf_active(dev)) {
1848                 otx2_info("Common resource in use by other devices");
1849                 return -EAGAIN;
1850         }
1851
1852         otx2_tim_fini();
1853         otx2_dev_fini(pci_dev, dev);
1854
1855         return 0;
1856 }
1857
1858 RTE_PMD_REGISTER_PCI(event_octeontx2, pci_sso);
1859 RTE_PMD_REGISTER_PCI_TABLE(event_octeontx2, pci_sso_map);
1860 RTE_PMD_REGISTER_KMOD_DEP(event_octeontx2, "vfio-pci");
1861 RTE_PMD_REGISTER_PARAM_STRING(event_octeontx2, OTX2_SSO_XAE_CNT "=<int>"
1862                               OTX2_SSO_SINGLE_WS "=1"
1863                               OTX2_SSO_GGRP_QOS "=<string>"
1864                               OTX2_SSO_SELFTEST "=1"
1865                               OTX2_NPA_LOCK_MASK "=<1-65535>");