drivers/event/octeontx2/otx2_evdev.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(C) 2019 Marvell International Ltd.
   3  */
   4
   5 #include <inttypes.h>
   6
   7 #include <rte_bus_pci.h>
   8 #include <rte_common.h>
   9 #include <rte_eal.h>
  10 #include <rte_eventdev_pmd_pci.h>
  11 #include <rte_kvargs.h>
  12 #include <rte_mbuf_pool_ops.h>
  13 #include <rte_pci.h>
  14
  15 #include "otx2_evdev_stats.h"
  16 #include "otx2_evdev.h"
  17 #include "otx2_irq.h"
  18 #include "otx2_tim_evdev.h"
  19
  20 static inline int
  21 sso_get_msix_offsets(const struct rte_eventdev *event_dev)
  22 {
  23         struct otx2_sso_evdev *dev = sso_pmd_priv(event_dev);
  24         uint8_t nb_ports = dev->nb_event_ports * (dev->dual_ws ? 2 : 1);
  25         struct otx2_mbox *mbox = dev->mbox;
  26         struct msix_offset_rsp *msix_rsp;
  27         int i, rc;
  28
  29         /* Get SSO and SSOW MSIX vector offsets */
  30         otx2_mbox_alloc_msg_msix_offset(mbox);
  31         rc = otx2_mbox_process_msg(mbox, (void *)&msix_rsp);
  32
  33         for (i = 0; i < nb_ports; i++)
  34                 dev->ssow_msixoff[i] = msix_rsp->ssow_msixoff[i];
  35
  36         for (i = 0; i < dev->nb_event_queues; i++)
  37                 dev->sso_msixoff[i] = msix_rsp->sso_msixoff[i];
  38
  39         return rc;
  40 }
  41
  42 void
  43 sso_fastpath_fns_set(struct rte_eventdev *event_dev)
  44 {
  45         struct otx2_sso_evdev *dev = sso_pmd_priv(event_dev);
  46         /* Single WS modes */
  47         const event_dequeue_t ssogws_deq[2][2][2][2][2][2][2] = {
  48 #define R(name, f6, f5, f4, f3, f2, f1, f0, flags)                      \
  49                 [f6][f5][f4][f3][f2][f1][f0] = otx2_ssogws_deq_ ##name,
  50 SSO_RX_ADPTR_ENQ_FASTPATH_FUNC
  51 #undef R
  52         };
  53
  54         const event_dequeue_burst_t ssogws_deq_burst[2][2][2][2][2][2][2] = {
  55 #define R(name, f6, f5, f4, f3, f2, f1, f0, flags)                      \
  56                 [f6][f5][f4][f3][f2][f1][f0] = otx2_ssogws_deq_burst_ ##name,
  57 SSO_RX_ADPTR_ENQ_FASTPATH_FUNC
  58 #undef R
  59         };
  60
  61         const event_dequeue_t ssogws_deq_timeout[2][2][2][2][2][2][2] = {
  62 #define R(name, f6, f5, f4, f3, f2, f1, f0, flags)                      \
  63                 [f6][f5][f4][f3][f2][f1][f0] = otx2_ssogws_deq_timeout_ ##name,
  64 SSO_RX_ADPTR_ENQ_FASTPATH_FUNC
  65 #undef R
  66         };
  67
  68         const event_dequeue_burst_t
  69                 ssogws_deq_timeout_burst[2][2][2][2][2][2][2] = {
  70 #define R(name, f6, f5, f4, f3, f2, f1, f0, flags)                      \
  71                 [f6][f5][f4][f3][f2][f1][f0] =                          \
  72                         otx2_ssogws_deq_timeout_burst_ ##name,
  73 SSO_RX_ADPTR_ENQ_FASTPATH_FUNC
  74 #undef R
  75         };
  76
  77         const event_dequeue_t ssogws_deq_seg[2][2][2][2][2][2][2] = {
  78 #define R(name, f6, f5, f4, f3, f2, f1, f0, flags)                      \
  79                 [f6][f5][f4][f3][f2][f1][f0] = otx2_ssogws_deq_seg_ ##name,
  80 SSO_RX_ADPTR_ENQ_FASTPATH_FUNC
  81 #undef R
  82         };
  83
  84         const event_dequeue_burst_t
  85                 ssogws_deq_seg_burst[2][2][2][2][2][2][2] = {
  86 #define R(name, f6, f5, f4, f3, f2, f1, f0, flags)                      \
  87                 [f6][f5][f4][f3][f2][f1][f0] =                          \
  88                         otx2_ssogws_deq_seg_burst_ ##name,
  89 SSO_RX_ADPTR_ENQ_FASTPATH_FUNC
  90 #undef R
  91         };
  92
  93         const event_dequeue_t ssogws_deq_seg_timeout[2][2][2][2][2][2][2] = {
  94 #define R(name, f6, f5, f4, f3, f2, f1, f0, flags)                      \
  95                 [f6][f5][f4][f3][f2][f1][f0] =                          \
  96                         otx2_ssogws_deq_seg_timeout_ ##name,
  97 SSO_RX_ADPTR_ENQ_FASTPATH_FUNC
  98 #undef R
  99         };
 100
 101         const event_dequeue_burst_t
 102                 ssogws_deq_seg_timeout_burst[2][2][2][2][2][2][2] = {
 103 #define R(name, f6, f5, f4, f3, f2, f1, f0, flags)                      \
 104                 [f6][f5][f4][f3][f2][f1][f0] =                          \
 105                                 otx2_ssogws_deq_seg_timeout_burst_ ##name,
 106 SSO_RX_ADPTR_ENQ_FASTPATH_FUNC
 107 #undef R
 108         };
 109
 110
 111         /* Dual WS modes */
 112         const event_dequeue_t ssogws_dual_deq[2][2][2][2][2][2][2] = {
 113 #define R(name, f6, f5, f4, f3, f2, f1, f0, flags)                      \
 114                 [f6][f5][f4][f3][f2][f1][f0] = otx2_ssogws_dual_deq_ ##name,
 115 SSO_RX_ADPTR_ENQ_FASTPATH_FUNC
 116 #undef R
 117         };
 118
 119         const event_dequeue_burst_t
 120                 ssogws_dual_deq_burst[2][2][2][2][2][2][2] = {
 121 #define R(name, f6, f5, f4, f3, f2, f1, f0, flags)                      \
 122                 [f6][f5][f4][f3][f2][f1][f0] =                          \
 123                         otx2_ssogws_dual_deq_burst_ ##name,
 124 SSO_RX_ADPTR_ENQ_FASTPATH_FUNC
 125 #undef R
 126         };
 127
 128         const event_dequeue_t ssogws_dual_deq_timeout[2][2][2][2][2][2][2] = {
 129 #define R(name, f6, f5, f4, f3, f2, f1, f0, flags)                      \
 130                 [f6][f5][f4][f3][f2][f1][f0] =                          \
 131                         otx2_ssogws_dual_deq_timeout_ ##name,
 132 SSO_RX_ADPTR_ENQ_FASTPATH_FUNC
 133 #undef R
 134         };
 135
 136         const event_dequeue_burst_t
 137                 ssogws_dual_deq_timeout_burst[2][2][2][2][2][2][2] = {
 138 #define R(name, f6, f5, f4, f3, f2, f1, f0, flags)                      \
 139         [f6][f5][f4][f3][f2][f1][f0] =                                  \
 140                         otx2_ssogws_dual_deq_timeout_burst_ ##name,
 141 SSO_RX_ADPTR_ENQ_FASTPATH_FUNC
 142 #undef R
 143         };
 144
 145         const event_dequeue_t ssogws_dual_deq_seg[2][2][2][2][2][2][2] = {
 146 #define R(name, f6, f5, f4, f3, f2, f1, f0, flags)                      \
 147                 [f6][f5][f4][f3][f2][f1][f0] = otx2_ssogws_dual_deq_seg_ ##name,
 148 SSO_RX_ADPTR_ENQ_FASTPATH_FUNC
 149 #undef R
 150         };
 151
 152         const event_dequeue_burst_t
 153                 ssogws_dual_deq_seg_burst[2][2][2][2][2][2][2] = {
 154 #define R(name, f6, f5, f4, f3, f2, f1, f0, flags)                      \
 155                 [f6][f5][f4][f3][f2][f1][f0] =                          \
 156                         otx2_ssogws_dual_deq_seg_burst_ ##name,
 157 SSO_RX_ADPTR_ENQ_FASTPATH_FUNC
 158 #undef R
 159         };
 160
 161         const event_dequeue_t
 162                 ssogws_dual_deq_seg_timeout[2][2][2][2][2][2][2] = {
 163 #define R(name, f6, f5, f4, f3, f2, f1, f0, flags)                      \
 164                 [f6][f5][f4][f3][f2][f1][f0] =                          \
 165                         otx2_ssogws_dual_deq_seg_timeout_ ##name,
 166 SSO_RX_ADPTR_ENQ_FASTPATH_FUNC
 167 #undef R
 168         };
 169
 170         const event_dequeue_burst_t
 171                 ssogws_dual_deq_seg_timeout_burst[2][2][2][2][2][2][2] = {
 172 #define R(name, f6, f5, f4, f3, f2, f1, f0, flags)                      \
 173                 [f6][f5][f4][f3][f2][f1][f0] =                          \
 174                         otx2_ssogws_dual_deq_seg_timeout_burst_ ##name,
 175 SSO_RX_ADPTR_ENQ_FASTPATH_FUNC
 176 #undef R
 177         };
 178
 179         /* Tx modes */
 180         const event_tx_adapter_enqueue
 181                 ssogws_tx_adptr_enq[2][2][2][2][2][2][2] = {
 182 #define T(name, f6, f5, f4, f3, f2, f1, f0, sz, flags)                  \
 183                 [f6][f5][f4][f3][f2][f1][f0] =                          \
 184                         otx2_ssogws_tx_adptr_enq_ ## name,
 185 SSO_TX_ADPTR_ENQ_FASTPATH_FUNC
 186 #undef T
 187         };
 188
 189         const event_tx_adapter_enqueue
 190                 ssogws_tx_adptr_enq_seg[2][2][2][2][2][2][2] = {
 191 #define T(name, f6, f5, f4, f3, f2, f1, f0, sz, flags)                  \
 192                 [f6][f5][f4][f3][f2][f1][f0] =                          \
 193                         otx2_ssogws_tx_adptr_enq_seg_ ## name,
 194 SSO_TX_ADPTR_ENQ_FASTPATH_FUNC
 195 #undef T
 196         };
 197
 198         const event_tx_adapter_enqueue
 199                 ssogws_dual_tx_adptr_enq[2][2][2][2][2][2][2] = {
 200 #define T(name, f6, f5, f4, f3, f2, f1, f0, sz, flags)                  \
 201                 [f6][f5][f4][f3][f2][f1][f0] =                          \
 202                         otx2_ssogws_dual_tx_adptr_enq_ ## name,
 203 SSO_TX_ADPTR_ENQ_FASTPATH_FUNC
 204 #undef T
 205         };
 206
 207         const event_tx_adapter_enqueue
 208                 ssogws_dual_tx_adptr_enq_seg[2][2][2][2][2][2][2] = {
 209 #define T(name, f6, f5, f4, f3, f2, f1, f0, sz, flags)                  \
 210                 [f6][f5][f4][f3][f2][f1][f0] =                          \
 211                         otx2_ssogws_dual_tx_adptr_enq_seg_ ## name,
 212 SSO_TX_ADPTR_ENQ_FASTPATH_FUNC
 213 #undef T
 214         };
 215
 216         event_dev->enqueue                      = otx2_ssogws_enq;
 217         event_dev->enqueue_burst                = otx2_ssogws_enq_burst;
 218         event_dev->enqueue_new_burst            = otx2_ssogws_enq_new_burst;
 219         event_dev->enqueue_forward_burst        = otx2_ssogws_enq_fwd_burst;
 220         if (dev->rx_offloads & NIX_RX_MULTI_SEG_F) {
 221                 event_dev->dequeue              = ssogws_deq_seg
 222                         [!!(dev->rx_offloads & NIX_RX_OFFLOAD_SECURITY_F)]
 223                         [!!(dev->rx_offloads & NIX_RX_OFFLOAD_TSTAMP_F)]
 224                         [!!(dev->rx_offloads & NIX_RX_OFFLOAD_MARK_UPDATE_F)]
 225                         [!!(dev->rx_offloads & NIX_RX_OFFLOAD_VLAN_STRIP_F)]
 226                         [!!(dev->rx_offloads & NIX_RX_OFFLOAD_CHECKSUM_F)]
 227                         [!!(dev->rx_offloads & NIX_RX_OFFLOAD_PTYPE_F)]
 228                         [!!(dev->rx_offloads & NIX_RX_OFFLOAD_RSS_F)];
 229                 event_dev->dequeue_burst        = ssogws_deq_seg_burst
 230                         [!!(dev->rx_offloads & NIX_RX_OFFLOAD_SECURITY_F)]
 231                         [!!(dev->rx_offloads & NIX_RX_OFFLOAD_TSTAMP_F)]
 232                         [!!(dev->rx_offloads & NIX_RX_OFFLOAD_MARK_UPDATE_F)]
 233                         [!!(dev->rx_offloads & NIX_RX_OFFLOAD_VLAN_STRIP_F)]
 234                         [!!(dev->rx_offloads & NIX_RX_OFFLOAD_CHECKSUM_F)]
 235                         [!!(dev->rx_offloads & NIX_RX_OFFLOAD_PTYPE_F)]
 236                         [!!(dev->rx_offloads & NIX_RX_OFFLOAD_RSS_F)];
 237                 if (dev->is_timeout_deq) {
 238                         event_dev->dequeue      = ssogws_deq_seg_timeout
 239                         [!!(dev->rx_offloads & NIX_RX_OFFLOAD_SECURITY_F)]
 240                         [!!(dev->rx_offloads & NIX_RX_OFFLOAD_TSTAMP_F)]
 241                         [!!(dev->rx_offloads & NIX_RX_OFFLOAD_MARK_UPDATE_F)]
 242                         [!!(dev->rx_offloads & NIX_RX_OFFLOAD_VLAN_STRIP_F)]
 243                         [!!(dev->rx_offloads & NIX_RX_OFFLOAD_CHECKSUM_F)]
 244                         [!!(dev->rx_offloads & NIX_RX_OFFLOAD_PTYPE_F)]
 245                         [!!(dev->rx_offloads & NIX_RX_OFFLOAD_RSS_F)];
 246                         event_dev->dequeue_burst        =
 247                                 ssogws_deq_seg_timeout_burst
 248                         [!!(dev->rx_offloads & NIX_RX_OFFLOAD_SECURITY_F)]
 249                         [!!(dev->rx_offloads & NIX_RX_OFFLOAD_TSTAMP_F)]
 250                         [!!(dev->rx_offloads & NIX_RX_OFFLOAD_MARK_UPDATE_F)]
 251                         [!!(dev->rx_offloads & NIX_RX_OFFLOAD_VLAN_STRIP_F)]
 252                         [!!(dev->rx_offloads & NIX_RX_OFFLOAD_CHECKSUM_F)]
 253                         [!!(dev->rx_offloads & NIX_RX_OFFLOAD_PTYPE_F)]
 254                         [!!(dev->rx_offloads & NIX_RX_OFFLOAD_RSS_F)];
 255                 }
 256         } else {
 257                 event_dev->dequeue                      = ssogws_deq
 258                         [!!(dev->rx_offloads & NIX_RX_OFFLOAD_SECURITY_F)]
 259                         [!!(dev->rx_offloads & NIX_RX_OFFLOAD_TSTAMP_F)]
 260                         [!!(dev->rx_offloads & NIX_RX_OFFLOAD_MARK_UPDATE_F)]
 261                         [!!(dev->rx_offloads & NIX_RX_OFFLOAD_VLAN_STRIP_F)]
 262                         [!!(dev->rx_offloads & NIX_RX_OFFLOAD_CHECKSUM_F)]
 263                         [!!(dev->rx_offloads & NIX_RX_OFFLOAD_PTYPE_F)]
 264                         [!!(dev->rx_offloads & NIX_RX_OFFLOAD_RSS_F)];
 265                 event_dev->dequeue_burst                = ssogws_deq_burst
 266                         [!!(dev->rx_offloads & NIX_RX_OFFLOAD_SECURITY_F)]
 267                         [!!(dev->rx_offloads & NIX_RX_OFFLOAD_TSTAMP_F)]
 268                         [!!(dev->rx_offloads & NIX_RX_OFFLOAD_MARK_UPDATE_F)]
 269                         [!!(dev->rx_offloads & NIX_RX_OFFLOAD_VLAN_STRIP_F)]
 270                         [!!(dev->rx_offloads & NIX_RX_OFFLOAD_CHECKSUM_F)]
 271                         [!!(dev->rx_offloads & NIX_RX_OFFLOAD_PTYPE_F)]
 272                         [!!(dev->rx_offloads & NIX_RX_OFFLOAD_RSS_F)];
 273                 if (dev->is_timeout_deq) {
 274                         event_dev->dequeue              = ssogws_deq_timeout
 275                         [!!(dev->rx_offloads & NIX_RX_OFFLOAD_SECURITY_F)]
 276                         [!!(dev->rx_offloads & NIX_RX_OFFLOAD_TSTAMP_F)]
 277                         [!!(dev->rx_offloads & NIX_RX_OFFLOAD_MARK_UPDATE_F)]
 278                         [!!(dev->rx_offloads & NIX_RX_OFFLOAD_VLAN_STRIP_F)]
 279                         [!!(dev->rx_offloads & NIX_RX_OFFLOAD_CHECKSUM_F)]
 280                         [!!(dev->rx_offloads & NIX_RX_OFFLOAD_PTYPE_F)]
 281                         [!!(dev->rx_offloads & NIX_RX_OFFLOAD_RSS_F)];
 282                         event_dev->dequeue_burst        =
 283                                 ssogws_deq_timeout_burst
 284                         [!!(dev->rx_offloads & NIX_RX_OFFLOAD_SECURITY_F)]
 285                         [!!(dev->rx_offloads & NIX_RX_OFFLOAD_TSTAMP_F)]
 286                         [!!(dev->rx_offloads & NIX_RX_OFFLOAD_MARK_UPDATE_F)]
 287                         [!!(dev->rx_offloads & NIX_RX_OFFLOAD_VLAN_STRIP_F)]
 288                         [!!(dev->rx_offloads & NIX_RX_OFFLOAD_CHECKSUM_F)]
 289                         [!!(dev->rx_offloads & NIX_RX_OFFLOAD_PTYPE_F)]
 290                         [!!(dev->rx_offloads & NIX_RX_OFFLOAD_RSS_F)];
 291                 }
 292         }
 293
 294         if (dev->tx_offloads & NIX_TX_MULTI_SEG_F) {
 295                 /* [SEC] [TSMP] [MBUF_NOFF] [VLAN] [OL3_L4_CSUM] [L3_L4_CSUM] */
 296                 event_dev->txa_enqueue = ssogws_tx_adptr_enq_seg
 297                         [!!(dev->tx_offloads & NIX_TX_OFFLOAD_SECURITY_F)]
 298                         [!!(dev->tx_offloads & NIX_TX_OFFLOAD_TSO_F)]
 299                         [!!(dev->tx_offloads & NIX_TX_OFFLOAD_TSTAMP_F)]
 300                         [!!(dev->tx_offloads & NIX_TX_OFFLOAD_MBUF_NOFF_F)]
 301                         [!!(dev->tx_offloads & NIX_TX_OFFLOAD_VLAN_QINQ_F)]
 302                         [!!(dev->tx_offloads & NIX_TX_OFFLOAD_OL3_OL4_CSUM_F)]
 303                         [!!(dev->tx_offloads & NIX_TX_OFFLOAD_L3_L4_CSUM_F)];
 304         } else {
 305                 event_dev->txa_enqueue = ssogws_tx_adptr_enq
 306                         [!!(dev->tx_offloads & NIX_TX_OFFLOAD_SECURITY_F)]
 307                         [!!(dev->tx_offloads & NIX_TX_OFFLOAD_TSO_F)]
 308                         [!!(dev->tx_offloads & NIX_TX_OFFLOAD_TSTAMP_F)]
 309                         [!!(dev->tx_offloads & NIX_TX_OFFLOAD_MBUF_NOFF_F)]
 310                         [!!(dev->tx_offloads & NIX_TX_OFFLOAD_VLAN_QINQ_F)]
 311                         [!!(dev->tx_offloads & NIX_TX_OFFLOAD_OL3_OL4_CSUM_F)]
 312                         [!!(dev->tx_offloads & NIX_TX_OFFLOAD_L3_L4_CSUM_F)];
 313         }
 314
 315         if (dev->dual_ws) {
 316                 event_dev->enqueue              = otx2_ssogws_dual_enq;
 317                 event_dev->enqueue_burst        = otx2_ssogws_dual_enq_burst;
 318                 event_dev->enqueue_new_burst    =
 319                                         otx2_ssogws_dual_enq_new_burst;
 320                 event_dev->enqueue_forward_burst =
 321                                         otx2_ssogws_dual_enq_fwd_burst;
 322
 323                 if (dev->rx_offloads & NIX_RX_MULTI_SEG_F) {
 324                         event_dev->dequeue      = ssogws_dual_deq_seg
 325                                 [!!(dev->rx_offloads &
 326                                                 NIX_RX_OFFLOAD_SECURITY_F)]
 327                                 [!!(dev->rx_offloads &
 328                                                 NIX_RX_OFFLOAD_TSTAMP_F)]
 329                                 [!!(dev->rx_offloads &
 330                                                 NIX_RX_OFFLOAD_MARK_UPDATE_F)]
 331                                 [!!(dev->rx_offloads &
 332                                                 NIX_RX_OFFLOAD_VLAN_STRIP_F)]
 333                                 [!!(dev->rx_offloads &
 334                                                 NIX_RX_OFFLOAD_CHECKSUM_F)]
 335                                 [!!(dev->rx_offloads & NIX_RX_OFFLOAD_PTYPE_F)]
 336                                 [!!(dev->rx_offloads & NIX_RX_OFFLOAD_RSS_F)];
 337                         event_dev->dequeue_burst = ssogws_dual_deq_seg_burst
 338                                 [!!(dev->rx_offloads &
 339                                                 NIX_RX_OFFLOAD_SECURITY_F)]
 340                                 [!!(dev->rx_offloads & NIX_RX_OFFLOAD_TSTAMP_F)]
 341                                 [!!(dev->rx_offloads &
 342                                                 NIX_RX_OFFLOAD_MARK_UPDATE_F)]
 343                                 [!!(dev->rx_offloads &
 344                                                 NIX_RX_OFFLOAD_VLAN_STRIP_F)]
 345                                 [!!(dev->rx_offloads &
 346                                                 NIX_RX_OFFLOAD_CHECKSUM_F)]
 347                                 [!!(dev->rx_offloads & NIX_RX_OFFLOAD_PTYPE_F)]
 348                                 [!!(dev->rx_offloads & NIX_RX_OFFLOAD_RSS_F)];
 349                         if (dev->is_timeout_deq) {
 350                                 event_dev->dequeue      =
 351                                         ssogws_dual_deq_seg_timeout
 352                                         [!!(dev->rx_offloads &
 353                                                 NIX_RX_OFFLOAD_SECURITY_F)]
 354                                         [!!(dev->rx_offloads &
 355                                                 NIX_RX_OFFLOAD_TSTAMP_F)]
 356                                         [!!(dev->rx_offloads &
 357                                                 NIX_RX_OFFLOAD_MARK_UPDATE_F)]
 358                                         [!!(dev->rx_offloads &
 359                                                 NIX_RX_OFFLOAD_VLAN_STRIP_F)]
 360                                         [!!(dev->rx_offloads &
 361                                                 NIX_RX_OFFLOAD_CHECKSUM_F)]
 362                                         [!!(dev->rx_offloads &
 363                                                         NIX_RX_OFFLOAD_PTYPE_F)]
 364                                         [!!(dev->rx_offloads &
 365                                                         NIX_RX_OFFLOAD_RSS_F)];
 366                                 event_dev->dequeue_burst =
 367                                         ssogws_dual_deq_seg_timeout_burst
 368                                         [!!(dev->rx_offloads &
 369                                                 NIX_RX_OFFLOAD_SECURITY_F)]
 370                                         [!!(dev->rx_offloads &
 371                                                 NIX_RX_OFFLOAD_TSTAMP_F)]
 372                                         [!!(dev->rx_offloads &
 373                                                 NIX_RX_OFFLOAD_MARK_UPDATE_F)]
 374                                         [!!(dev->rx_offloads &
 375                                                 NIX_RX_OFFLOAD_VLAN_STRIP_F)]
 376                                         [!!(dev->rx_offloads &
 377                                                 NIX_RX_OFFLOAD_CHECKSUM_F)]
 378                                         [!!(dev->rx_offloads &
 379                                                         NIX_RX_OFFLOAD_PTYPE_F)]
 380                                         [!!(dev->rx_offloads &
 381                                                         NIX_RX_OFFLOAD_RSS_F)];
 382                         }
 383                 } else {
 384                         event_dev->dequeue              = ssogws_dual_deq
 385                                 [!!(dev->rx_offloads &
 386                                                 NIX_RX_OFFLOAD_SECURITY_F)]
 387                                 [!!(dev->rx_offloads &
 388                                                 NIX_RX_OFFLOAD_TSTAMP_F)]
 389                                 [!!(dev->rx_offloads &
 390                                                 NIX_RX_OFFLOAD_MARK_UPDATE_F)]
 391                                 [!!(dev->rx_offloads &
 392                                                 NIX_RX_OFFLOAD_VLAN_STRIP_F)]
 393                                 [!!(dev->rx_offloads &
 394                                                 NIX_RX_OFFLOAD_CHECKSUM_F)]
 395                                 [!!(dev->rx_offloads & NIX_RX_OFFLOAD_PTYPE_F)]
 396                                 [!!(dev->rx_offloads & NIX_RX_OFFLOAD_RSS_F)];
 397                         event_dev->dequeue_burst        = ssogws_dual_deq_burst
 398                                 [!!(dev->rx_offloads &
 399                                                 NIX_RX_OFFLOAD_SECURITY_F)]
 400                                 [!!(dev->rx_offloads &
 401                                                 NIX_RX_OFFLOAD_TSTAMP_F)]
 402                                 [!!(dev->rx_offloads &
 403                                                 NIX_RX_OFFLOAD_MARK_UPDATE_F)]
 404                                 [!!(dev->rx_offloads &
 405                                                 NIX_RX_OFFLOAD_VLAN_STRIP_F)]
 406                                 [!!(dev->rx_offloads &
 407                                                 NIX_RX_OFFLOAD_CHECKSUM_F)]
 408                                 [!!(dev->rx_offloads & NIX_RX_OFFLOAD_PTYPE_F)]
 409                                 [!!(dev->rx_offloads & NIX_RX_OFFLOAD_RSS_F)];
 410                         if (dev->is_timeout_deq) {
 411                                 event_dev->dequeue      =
 412                                         ssogws_dual_deq_timeout
 413                                         [!!(dev->rx_offloads &
 414                                                 NIX_RX_OFFLOAD_SECURITY_F)]
 415                                         [!!(dev->rx_offloads &
 416                                                 NIX_RX_OFFLOAD_TSTAMP_F)]
 417                                         [!!(dev->rx_offloads &
 418                                                 NIX_RX_OFFLOAD_MARK_UPDATE_F)]
 419                                         [!!(dev->rx_offloads &
 420                                                 NIX_RX_OFFLOAD_VLAN_STRIP_F)]
 421                                         [!!(dev->rx_offloads &
 422                                                 NIX_RX_OFFLOAD_CHECKSUM_F)]
 423                                         [!!(dev->rx_offloads &
 424                                                         NIX_RX_OFFLOAD_PTYPE_F)]
 425                                         [!!(dev->rx_offloads &
 426                                                         NIX_RX_OFFLOAD_RSS_F)];
 427                                 event_dev->dequeue_burst =
 428                                         ssogws_dual_deq_timeout_burst
 429                                         [!!(dev->rx_offloads &
 430                                                 NIX_RX_OFFLOAD_SECURITY_F)]
 431                                         [!!(dev->rx_offloads &
 432                                                 NIX_RX_OFFLOAD_TSTAMP_F)]
 433                                         [!!(dev->rx_offloads &
 434                                                 NIX_RX_OFFLOAD_MARK_UPDATE_F)]
 435                                         [!!(dev->rx_offloads &
 436                                                 NIX_RX_OFFLOAD_VLAN_STRIP_F)]
 437                                         [!!(dev->rx_offloads &
 438                                                 NIX_RX_OFFLOAD_CHECKSUM_F)]
 439                                         [!!(dev->rx_offloads &
 440                                                         NIX_RX_OFFLOAD_PTYPE_F)]
 441                                         [!!(dev->rx_offloads &
 442                                                         NIX_RX_OFFLOAD_RSS_F)];
 443                         }
 444                 }
 445
 446                 if (dev->tx_offloads & NIX_TX_MULTI_SEG_F) {
 447                 /* [SEC] [TSMP] [MBUF_NOFF] [VLAN] [OL3_L4_CSUM] [L3_L4_CSUM] */
 448                         event_dev->txa_enqueue = ssogws_dual_tx_adptr_enq_seg
 449                                 [!!(dev->tx_offloads &
 450                                                 NIX_TX_OFFLOAD_SECURITY_F)]
 451                                 [!!(dev->tx_offloads & NIX_TX_OFFLOAD_TSO_F)]
 452                                 [!!(dev->tx_offloads & NIX_TX_OFFLOAD_TSTAMP_F)]
 453                                 [!!(dev->tx_offloads &
 454                                                 NIX_TX_OFFLOAD_MBUF_NOFF_F)]
 455                                 [!!(dev->tx_offloads &
 456                                                 NIX_TX_OFFLOAD_VLAN_QINQ_F)]
 457                                 [!!(dev->tx_offloads &
 458                                                 NIX_TX_OFFLOAD_OL3_OL4_CSUM_F)]
 459                                 [!!(dev->tx_offloads &
 460                                                 NIX_TX_OFFLOAD_L3_L4_CSUM_F)];
 461                 } else {
 462                         event_dev->txa_enqueue = ssogws_dual_tx_adptr_enq
 463                                 [!!(dev->tx_offloads &
 464                                                 NIX_TX_OFFLOAD_SECURITY_F)]
 465                                 [!!(dev->tx_offloads & NIX_TX_OFFLOAD_TSO_F)]
 466                                 [!!(dev->tx_offloads & NIX_TX_OFFLOAD_TSTAMP_F)]
 467                                 [!!(dev->tx_offloads &
 468                                                 NIX_TX_OFFLOAD_MBUF_NOFF_F)]
 469                                 [!!(dev->tx_offloads &
 470                                                 NIX_TX_OFFLOAD_VLAN_QINQ_F)]
 471                                 [!!(dev->tx_offloads &
 472                                                 NIX_TX_OFFLOAD_OL3_OL4_CSUM_F)]
 473                                 [!!(dev->tx_offloads &
 474                                                 NIX_TX_OFFLOAD_L3_L4_CSUM_F)];
 475                 }
 476         }
 477
 478         event_dev->txa_enqueue_same_dest = event_dev->txa_enqueue;
 479         rte_mb();
 480 }
 481
 482 static void
 483 otx2_sso_info_get(struct rte_eventdev *event_dev,
 484                   struct rte_event_dev_info *dev_info)
 485 {
 486         struct otx2_sso_evdev *dev = sso_pmd_priv(event_dev);
 487
 488         dev_info->driver_name = RTE_STR(EVENTDEV_NAME_OCTEONTX2_PMD);
 489         dev_info->min_dequeue_timeout_ns = dev->min_dequeue_timeout_ns;
 490         dev_info->max_dequeue_timeout_ns = dev->max_dequeue_timeout_ns;
 491         dev_info->max_event_queues = dev->max_event_queues;
 492         dev_info->max_event_queue_flows = (1ULL << 20);
 493         dev_info->max_event_queue_priority_levels = 8;
 494         dev_info->max_event_priority_levels = 1;
 495         dev_info->max_event_ports = dev->max_event_ports;
 496         dev_info->max_event_port_dequeue_depth = 1;
 497         dev_info->max_event_port_enqueue_depth = 1;
 498         dev_info->max_num_events =  dev->max_num_events;
 499         dev_info->event_dev_cap = RTE_EVENT_DEV_CAP_QUEUE_QOS |
 500                                         RTE_EVENT_DEV_CAP_DISTRIBUTED_SCHED |
 501                                         RTE_EVENT_DEV_CAP_QUEUE_ALL_TYPES |
 502                                         RTE_EVENT_DEV_CAP_RUNTIME_PORT_LINK |
 503                                         RTE_EVENT_DEV_CAP_MULTIPLE_QUEUE_PORT |
 504                                         RTE_EVENT_DEV_CAP_NONSEQ_MODE;
 505 }
 506
 507 static void
 508 sso_port_link_modify(struct otx2_ssogws *ws, uint8_t queue, uint8_t enable)
 509 {
 510         uintptr_t base = OTX2_SSOW_GET_BASE_ADDR(ws->getwrk_op);
 511         uint64_t val;
 512
 513         val = queue;
 514         val |= 0ULL << 12; /* SET 0 */
 515         val |= 0x8000800080000000; /* Dont modify rest of the masks */
 516         val |= (uint64_t)enable << 14;   /* Enable/Disable Membership. */
 517
 518         otx2_write64(val, base + SSOW_LF_GWS_GRPMSK_CHG);
 519 }
 520
 521 static int
 522 otx2_sso_port_link(struct rte_eventdev *event_dev, void *port,
 523                    const uint8_t queues[], const uint8_t priorities[],
 524                    uint16_t nb_links)
 525 {
 526         struct otx2_sso_evdev *dev = sso_pmd_priv(event_dev);
 527         uint8_t port_id = 0;
 528         uint16_t link;
 529
 530         RTE_SET_USED(priorities);
 531         for (link = 0; link < nb_links; link++) {
 532                 if (dev->dual_ws) {
 533                         struct otx2_ssogws_dual *ws = port;
 534
 535                         port_id = ws->port;
 536                         sso_port_link_modify((struct otx2_ssogws *)
 537                                         &ws->ws_state[0], queues[link], true);
 538                         sso_port_link_modify((struct otx2_ssogws *)
 539                                         &ws->ws_state[1], queues[link], true);
 540                 } else {
 541                         struct otx2_ssogws *ws = port;
 542
 543                         port_id = ws->port;
 544                         sso_port_link_modify(ws, queues[link], true);
 545                 }
 546         }
 547         sso_func_trace("Port=%d nb_links=%d", port_id, nb_links);
 548
 549         return (int)nb_links;
 550 }
 551
 552 static int
 553 otx2_sso_port_unlink(struct rte_eventdev *event_dev, void *port,
 554                      uint8_t queues[], uint16_t nb_unlinks)
 555 {
 556         struct otx2_sso_evdev *dev = sso_pmd_priv(event_dev);
 557         uint8_t port_id = 0;
 558         uint16_t unlink;
 559
 560         for (unlink = 0; unlink < nb_unlinks; unlink++) {
 561                 if (dev->dual_ws) {
 562                         struct otx2_ssogws_dual *ws = port;
 563
 564                         port_id = ws->port;
 565                         sso_port_link_modify((struct otx2_ssogws *)
 566                                         &ws->ws_state[0], queues[unlink],
 567                                         false);
 568                         sso_port_link_modify((struct otx2_ssogws *)
 569                                         &ws->ws_state[1], queues[unlink],
 570                                         false);
 571                 } else {
 572                         struct otx2_ssogws *ws = port;
 573
 574                         port_id = ws->port;
 575                         sso_port_link_modify(ws, queues[unlink], false);
 576                 }
 577         }
 578         sso_func_trace("Port=%d nb_unlinks=%d", port_id, nb_unlinks);
 579
 580         return (int)nb_unlinks;
 581 }
 582
 583 static int
 584 sso_hw_lf_cfg(struct otx2_mbox *mbox, enum otx2_sso_lf_type type,
 585               uint16_t nb_lf, uint8_t attach)
 586 {
 587         if (attach) {
 588                 struct rsrc_attach_req *req;
 589
 590                 req = otx2_mbox_alloc_msg_attach_resources(mbox);
 591                 switch (type) {
 592                 case SSO_LF_GGRP:
 593                         req->sso = nb_lf;
 594                         break;
 595                 case SSO_LF_GWS:
 596                         req->ssow = nb_lf;
 597                         break;
 598                 default:
 599                         return -EINVAL;
 600                 }
 601                 req->modify = true;
 602                 if (otx2_mbox_process(mbox) < 0)
 603                         return -EIO;
 604         } else {
 605                 struct rsrc_detach_req *req;
 606
 607                 req = otx2_mbox_alloc_msg_detach_resources(mbox);
 608                 switch (type) {
 609                 case SSO_LF_GGRP:
 610                         req->sso = true;
 611                         break;
 612                 case SSO_LF_GWS:
 613                         req->ssow = true;
 614                         break;
 615                 default:
 616                         return -EINVAL;
 617                 }
 618                 req->partial = true;
 619                 if (otx2_mbox_process(mbox) < 0)
 620                         return -EIO;
 621         }
 622
 623         return 0;
 624 }
 625
 626 static int
 627 sso_lf_cfg(struct otx2_sso_evdev *dev, struct otx2_mbox *mbox,
 628            enum otx2_sso_lf_type type, uint16_t nb_lf, uint8_t alloc)
 629 {
 630         void *rsp;
 631         int rc;
 632
 633         if (alloc) {
 634                 switch (type) {
 635                 case SSO_LF_GGRP:
 636                         {
 637                         struct sso_lf_alloc_req *req_ggrp;
 638                         req_ggrp = otx2_mbox_alloc_msg_sso_lf_alloc(mbox);
 639                         req_ggrp->hwgrps = nb_lf;
 640                         }
 641                         break;
 642                 case SSO_LF_GWS:
 643                         {
 644                         struct ssow_lf_alloc_req *req_hws;
 645                         req_hws = otx2_mbox_alloc_msg_ssow_lf_alloc(mbox);
 646                         req_hws->hws = nb_lf;
 647                         }
 648                         break;
 649                 default:
 650                         return -EINVAL;
 651                 }
 652         } else {
 653                 switch (type) {
 654                 case SSO_LF_GGRP:
 655                         {
 656                         struct sso_lf_free_req *req_ggrp;
 657                         req_ggrp = otx2_mbox_alloc_msg_sso_lf_free(mbox);
 658                         req_ggrp->hwgrps = nb_lf;
 659                         }
 660                         break;
 661                 case SSO_LF_GWS:
 662                         {
 663                         struct ssow_lf_free_req *req_hws;
 664                         req_hws = otx2_mbox_alloc_msg_ssow_lf_free(mbox);
 665                         req_hws->hws = nb_lf;
 666                         }
 667                         break;
 668                 default:
 669                         return -EINVAL;
 670                 }
 671         }
 672
 673         rc = otx2_mbox_process_msg_tmo(mbox, (void **)&rsp, ~0);
 674         if (rc < 0)
 675                 return rc;
 676
 677         if (alloc && type == SSO_LF_GGRP) {
 678                 struct sso_lf_alloc_rsp *rsp_ggrp = rsp;
 679
 680                 dev->xaq_buf_size = rsp_ggrp->xaq_buf_size;
 681                 dev->xae_waes = rsp_ggrp->xaq_wq_entries;
 682                 dev->iue = rsp_ggrp->in_unit_entries;
 683         }
 684
 685         return 0;
 686 }
 687
 688 static void
 689 otx2_sso_port_release(void *port)
 690 {
 691         rte_free(port);
 692 }
 693
 694 static void
 695 otx2_sso_queue_release(struct rte_eventdev *event_dev, uint8_t queue_id)
 696 {
 697         RTE_SET_USED(event_dev);
 698         RTE_SET_USED(queue_id);
 699 }
 700
 701 static void
 702 sso_clr_links(const struct rte_eventdev *event_dev)
 703 {
 704         struct otx2_sso_evdev *dev = sso_pmd_priv(event_dev);
 705         int i, j;
 706
 707         for (i = 0; i < dev->nb_event_ports; i++) {
 708                 if (dev->dual_ws) {
 709                         struct otx2_ssogws_dual *ws;
 710
 711                         ws = event_dev->data->ports[i];
 712                         for (j = 0; j < dev->nb_event_queues; j++) {
 713                                 sso_port_link_modify((struct otx2_ssogws *)
 714                                                 &ws->ws_state[0], j, false);
 715                                 sso_port_link_modify((struct otx2_ssogws *)
 716                                                 &ws->ws_state[1], j, false);
 717                         }
 718                 } else {
 719                         struct otx2_ssogws *ws;
 720
 721                         ws = event_dev->data->ports[i];
 722                         for (j = 0; j < dev->nb_event_queues; j++)
 723                                 sso_port_link_modify(ws, j, false);
 724                 }
 725         }
 726 }
 727
 728 static void
 729 sso_set_port_ops(struct otx2_ssogws *ws, uintptr_t base)
 730 {
 731         ws->tag_op              = base + SSOW_LF_GWS_TAG;
 732         ws->wqp_op              = base + SSOW_LF_GWS_WQP;
 733         ws->getwrk_op           = base + SSOW_LF_GWS_OP_GET_WORK;
 734         ws->swtp_op             = base + SSOW_LF_GWS_SWTP;
 735         ws->swtag_norm_op       = base + SSOW_LF_GWS_OP_SWTAG_NORM;
 736         ws->swtag_desched_op    = base + SSOW_LF_GWS_OP_SWTAG_DESCHED;
 737 }
 738
 739 static int
 740 sso_configure_dual_ports(const struct rte_eventdev *event_dev)
 741 {
 742         struct otx2_sso_evdev *dev = sso_pmd_priv(event_dev);
 743         struct otx2_mbox *mbox = dev->mbox;
 744         uint8_t vws = 0;
 745         uint8_t nb_lf;
 746         int i, rc;
 747
 748         otx2_sso_dbg("Configuring event ports %d", dev->nb_event_ports);
 749
 750         nb_lf = dev->nb_event_ports * 2;
 751         /* Ask AF to attach required LFs. */
 752         rc = sso_hw_lf_cfg(mbox, SSO_LF_GWS, nb_lf, true);
 753         if (rc < 0) {
 754                 otx2_err("Failed to attach SSO GWS LF");
 755                 return -ENODEV;
 756         }
 757
 758         if (sso_lf_cfg(dev, mbox, SSO_LF_GWS, nb_lf, true) < 0) {
 759                 sso_hw_lf_cfg(mbox, SSO_LF_GWS, nb_lf, false);
 760                 otx2_err("Failed to init SSO GWS LF");
 761                 return -ENODEV;
 762         }
 763
 764         for (i = 0; i < dev->nb_event_ports; i++) {
 765                 struct otx2_ssogws_dual *ws;
 766                 uintptr_t base;
 767
 768                 /* Free memory prior to re-allocation if needed */
 769                 if (event_dev->data->ports[i] != NULL) {
 770                         ws = event_dev->data->ports[i];
 771                         rte_free(ws);
 772                         ws = NULL;
 773                 }
 774
 775                 /* Allocate event port memory */
 776                 ws = rte_zmalloc_socket("otx2_sso_ws",
 777                                         sizeof(struct otx2_ssogws_dual),
 778                                         RTE_CACHE_LINE_SIZE,
 779                                         event_dev->data->socket_id);
 780                 if (ws == NULL) {
 781                         otx2_err("Failed to alloc memory for port=%d", i);
 782                         rc = -ENOMEM;
 783                         break;
 784                 }
 785
 786                 ws->port = i;
 787                 base = dev->bar2 + (RVU_BLOCK_ADDR_SSOW << 20 | vws << 12);
 788                 sso_set_port_ops((struct otx2_ssogws *)&ws->ws_state[0], base);
 789                 vws++;
 790
 791                 base = dev->bar2 + (RVU_BLOCK_ADDR_SSOW << 20 | vws << 12);
 792                 sso_set_port_ops((struct otx2_ssogws *)&ws->ws_state[1], base);
 793                 vws++;
 794
 795                 event_dev->data->ports[i] = ws;
 796         }
 797
 798         if (rc < 0) {
 799                 sso_lf_cfg(dev, mbox, SSO_LF_GWS, nb_lf, false);
 800                 sso_hw_lf_cfg(mbox, SSO_LF_GWS, nb_lf, false);
 801         }
 802
 803         return rc;
 804 }
 805
 806 static int
 807 sso_configure_ports(const struct rte_eventdev *event_dev)
 808 {
 809         struct otx2_sso_evdev *dev = sso_pmd_priv(event_dev);
 810         struct otx2_mbox *mbox = dev->mbox;
 811         uint8_t nb_lf;
 812         int i, rc;
 813
 814         otx2_sso_dbg("Configuring event ports %d", dev->nb_event_ports);
 815
 816         nb_lf = dev->nb_event_ports;
 817         /* Ask AF to attach required LFs. */
 818         rc = sso_hw_lf_cfg(mbox, SSO_LF_GWS, nb_lf, true);
 819         if (rc < 0) {
 820                 otx2_err("Failed to attach SSO GWS LF");
 821                 return -ENODEV;
 822         }
 823
 824         if (sso_lf_cfg(dev, mbox, SSO_LF_GWS, nb_lf, true) < 0) {
 825                 sso_hw_lf_cfg(mbox, SSO_LF_GWS, nb_lf, false);
 826                 otx2_err("Failed to init SSO GWS LF");
 827                 return -ENODEV;
 828         }
 829
 830         for (i = 0; i < nb_lf; i++) {
 831                 struct otx2_ssogws *ws;
 832                 uintptr_t base;
 833
 834                 /* Free memory prior to re-allocation if needed */
 835                 if (event_dev->data->ports[i] != NULL) {
 836                         ws = event_dev->data->ports[i];
 837                         rte_free(ws);
 838                         ws = NULL;
 839                 }
 840
 841                 /* Allocate event port memory */
 842                 ws = rte_zmalloc_socket("otx2_sso_ws",
 843                                         sizeof(struct otx2_ssogws),
 844                                         RTE_CACHE_LINE_SIZE,
 845                                         event_dev->data->socket_id);
 846                 if (ws == NULL) {
 847                         otx2_err("Failed to alloc memory for port=%d", i);
 848                         rc = -ENOMEM;
 849                         break;
 850                 }
 851
 852                 ws->port = i;
 853                 base = dev->bar2 + (RVU_BLOCK_ADDR_SSOW << 20 | i << 12);
 854                 sso_set_port_ops(ws, base);
 855
 856                 event_dev->data->ports[i] = ws;
 857         }
 858
 859         if (rc < 0) {
 860                 sso_lf_cfg(dev, mbox, SSO_LF_GWS, nb_lf, false);
 861                 sso_hw_lf_cfg(mbox, SSO_LF_GWS, nb_lf, false);
 862         }
 863
 864         return rc;
 865 }
 866
 867 static int
 868 sso_configure_queues(const struct rte_eventdev *event_dev)
 869 {
 870         struct otx2_sso_evdev *dev = sso_pmd_priv(event_dev);
 871         struct otx2_mbox *mbox = dev->mbox;
 872         uint8_t nb_lf;
 873         int rc;
 874
 875         otx2_sso_dbg("Configuring event queues %d", dev->nb_event_queues);
 876
 877         nb_lf = dev->nb_event_queues;
 878         /* Ask AF to attach required LFs. */
 879         rc = sso_hw_lf_cfg(mbox, SSO_LF_GGRP, nb_lf, true);
 880         if (rc < 0) {
 881                 otx2_err("Failed to attach SSO GGRP LF");
 882                 return -ENODEV;
 883         }
 884
 885         if (sso_lf_cfg(dev, mbox, SSO_LF_GGRP, nb_lf, true) < 0) {
 886                 sso_hw_lf_cfg(mbox, SSO_LF_GGRP, nb_lf, false);
 887                 otx2_err("Failed to init SSO GGRP LF");
 888                 return -ENODEV;
 889         }
 890
 891         return rc;
 892 }
 893
 894 static int
 895 sso_xaq_allocate(struct otx2_sso_evdev *dev)
 896 {
 897         const struct rte_memzone *mz;
 898         struct npa_aura_s *aura;
 899         static int reconfig_cnt;
 900         char pool_name[RTE_MEMZONE_NAMESIZE];
 901         uint32_t xaq_cnt;
 902         int rc;
 903
 904         if (dev->xaq_pool)
 905                 rte_mempool_free(dev->xaq_pool);
 906
 907         /*
 908          * Allocate memory for Add work backpressure.
 909          */
 910         mz = rte_memzone_lookup(OTX2_SSO_FC_NAME);
 911         if (mz == NULL)
 912                 mz = rte_memzone_reserve_aligned(OTX2_SSO_FC_NAME,
 913                                                  OTX2_ALIGN +
 914                                                  sizeof(struct npa_aura_s),
 915                                                  rte_socket_id(),
 916                                                  RTE_MEMZONE_IOVA_CONTIG,
 917                                                  OTX2_ALIGN);
 918         if (mz == NULL) {
 919                 otx2_err("Failed to allocate mem for fcmem");
 920                 return -ENOMEM;
 921         }
 922
 923         dev->fc_iova = mz->iova;
 924         dev->fc_mem = mz->addr;
 925
 926         aura = (struct npa_aura_s *)((uintptr_t)dev->fc_mem + OTX2_ALIGN);
 927         memset(aura, 0, sizeof(struct npa_aura_s));
 928
 929         aura->fc_ena = 1;
 930         aura->fc_addr = dev->fc_iova;
 931         aura->fc_hyst_bits = 0; /* Store count on all updates */
 932
 933         /* Taken from HRM 14.3.3(4) */
 934         xaq_cnt = dev->nb_event_queues * OTX2_SSO_XAQ_CACHE_CNT;
 935         if (dev->xae_cnt)
 936                 xaq_cnt += dev->xae_cnt / dev->xae_waes;
 937         else if (dev->adptr_xae_cnt)
 938                 xaq_cnt += (dev->adptr_xae_cnt / dev->xae_waes) +
 939                         (OTX2_SSO_XAQ_SLACK * dev->nb_event_queues);
 940         else
 941                 xaq_cnt += (dev->iue / dev->xae_waes) +
 942                         (OTX2_SSO_XAQ_SLACK * dev->nb_event_queues);
 943
 944         otx2_sso_dbg("Configuring %d xaq buffers", xaq_cnt);
 945         /* Setup XAQ based on number of nb queues. */
 946         snprintf(pool_name, 30, "otx2_xaq_buf_pool_%d", reconfig_cnt);
 947         dev->xaq_pool = (void *)rte_mempool_create_empty(pool_name,
 948                         xaq_cnt, dev->xaq_buf_size, 0, 0,
 949                         rte_socket_id(), 0);
 950
 951         if (dev->xaq_pool == NULL) {
 952                 otx2_err("Unable to create empty mempool.");
 953                 rte_memzone_free(mz);
 954                 return -ENOMEM;
 955         }
 956
 957         rc = rte_mempool_set_ops_byname(dev->xaq_pool,
 958                                         rte_mbuf_platform_mempool_ops(), aura);
 959         if (rc != 0) {
 960                 otx2_err("Unable to set xaqpool ops.");
 961                 goto alloc_fail;
 962         }
 963
 964         rc = rte_mempool_populate_default(dev->xaq_pool);
 965         if (rc < 0) {
 966                 otx2_err("Unable to set populate xaqpool.");
 967                 goto alloc_fail;
 968         }
 969         reconfig_cnt++;
 970         /* When SW does addwork (enqueue) check if there is space in XAQ by
 971          * comparing fc_addr above against the xaq_lmt calculated below.
 972          * There should be a minimum headroom (OTX2_SSO_XAQ_SLACK / 2) for SSO
 973          * to request XAQ to cache them even before enqueue is called.
 974          */
 975         dev->xaq_lmt = xaq_cnt - (OTX2_SSO_XAQ_SLACK / 2 *
 976                                   dev->nb_event_queues);
 977         dev->nb_xaq_cfg = xaq_cnt;
 978
 979         return 0;
 980 alloc_fail:
 981         rte_mempool_free(dev->xaq_pool);
 982         rte_memzone_free(mz);
 983         return rc;
 984 }
 985
 986 static int
 987 sso_ggrp_alloc_xaq(struct otx2_sso_evdev *dev)
 988 {
 989         struct otx2_mbox *mbox = dev->mbox;
 990         struct sso_hw_setconfig *req;
 991
 992         otx2_sso_dbg("Configuring XAQ for GGRPs");
 993         req = otx2_mbox_alloc_msg_sso_hw_setconfig(mbox);
 994         req->npa_pf_func = otx2_npa_pf_func_get();
 995         req->npa_aura_id = npa_lf_aura_handle_to_aura(dev->xaq_pool->pool_id);
 996         req->hwgrps = dev->nb_event_queues;
 997
 998         return otx2_mbox_process(mbox);
 999 }
1000
1001 static void
1002 sso_lf_teardown(struct otx2_sso_evdev *dev,
1003                 enum otx2_sso_lf_type lf_type)
1004 {
1005         uint8_t nb_lf;
1006
1007         switch (lf_type) {
1008         case SSO_LF_GGRP:
1009                 nb_lf = dev->nb_event_queues;
1010                 break;
1011         case SSO_LF_GWS:
1012                 nb_lf = dev->nb_event_ports;
1013                 nb_lf *= dev->dual_ws ? 2 : 1;
1014                 break;
1015         default:
1016                 return;
1017         }
1018
1019         sso_lf_cfg(dev, dev->mbox, lf_type, nb_lf, false);
1020         sso_hw_lf_cfg(dev->mbox, lf_type, nb_lf, false);
1021 }
1022
1023 static int
1024 otx2_sso_configure(const struct rte_eventdev *event_dev)
1025 {
1026         struct rte_event_dev_config *conf = &event_dev->data->dev_conf;
1027         struct otx2_sso_evdev *dev = sso_pmd_priv(event_dev);
1028         uint32_t deq_tmo_ns;
1029         int rc;
1030
1031         sso_func_trace();
1032         deq_tmo_ns = conf->dequeue_timeout_ns;
1033
1034         if (deq_tmo_ns == 0)
1035                 deq_tmo_ns = dev->min_dequeue_timeout_ns;
1036
1037         if (deq_tmo_ns < dev->min_dequeue_timeout_ns ||
1038             deq_tmo_ns > dev->max_dequeue_timeout_ns) {
1039                 otx2_err("Unsupported dequeue timeout requested");
1040                 return -EINVAL;
1041         }
1042
1043         if (conf->event_dev_cfg & RTE_EVENT_DEV_CFG_PER_DEQUEUE_TIMEOUT)
1044                 dev->is_timeout_deq = 1;
1045
1046         dev->deq_tmo_ns = deq_tmo_ns;
1047
1048         if (conf->nb_event_ports > dev->max_event_ports ||
1049             conf->nb_event_queues > dev->max_event_queues) {
1050                 otx2_err("Unsupported event queues/ports requested");
1051                 return -EINVAL;
1052         }
1053
1054         if (conf->nb_event_port_dequeue_depth > 1) {
1055                 otx2_err("Unsupported event port deq depth requested");
1056                 return -EINVAL;
1057         }
1058
1059         if (conf->nb_event_port_enqueue_depth > 1) {
1060                 otx2_err("Unsupported event port enq depth requested");
1061                 return -EINVAL;
1062         }
1063
1064         if (dev->configured)
1065                 sso_unregister_irqs(event_dev);
1066
1067         if (dev->nb_event_queues) {
1068                 /* Finit any previous queues. */
1069                 sso_lf_teardown(dev, SSO_LF_GGRP);
1070         }
1071         if (dev->nb_event_ports) {
1072                 /* Finit any previous ports. */
1073                 sso_lf_teardown(dev, SSO_LF_GWS);
1074         }
1075
1076         dev->nb_event_queues = conf->nb_event_queues;
1077         dev->nb_event_ports = conf->nb_event_ports;
1078
1079         if (dev->dual_ws)
1080                 rc = sso_configure_dual_ports(event_dev);
1081         else
1082                 rc = sso_configure_ports(event_dev);
1083
1084         if (rc < 0) {
1085                 otx2_err("Failed to configure event ports");
1086                 return -ENODEV;
1087         }
1088
1089         if (sso_configure_queues(event_dev) < 0) {
1090                 otx2_err("Failed to configure event queues");
1091                 rc = -ENODEV;
1092                 goto teardown_hws;
1093         }
1094
1095         if (sso_xaq_allocate(dev) < 0) {
1096                 rc = -ENOMEM;
1097                 goto teardown_hwggrp;
1098         }
1099
1100         /* Clear any prior port-queue mapping. */
1101         sso_clr_links(event_dev);
1102         rc = sso_ggrp_alloc_xaq(dev);
1103         if (rc < 0) {
1104                 otx2_err("Failed to alloc xaq to ggrp %d", rc);
1105                 goto teardown_hwggrp;
1106         }
1107
1108         rc = sso_get_msix_offsets(event_dev);
1109         if (rc < 0) {
1110                 otx2_err("Failed to get msix offsets %d", rc);
1111                 goto teardown_hwggrp;
1112         }
1113
1114         rc = sso_register_irqs(event_dev);
1115         if (rc < 0) {
1116                 otx2_err("Failed to register irq %d", rc);
1117                 goto teardown_hwggrp;
1118         }
1119
1120         dev->configured = 1;
1121         rte_mb();
1122
1123         return 0;
1124 teardown_hwggrp:
1125         sso_lf_teardown(dev, SSO_LF_GGRP);
1126 teardown_hws:
1127         sso_lf_teardown(dev, SSO_LF_GWS);
1128         dev->nb_event_queues = 0;
1129         dev->nb_event_ports = 0;
1130         dev->configured = 0;
1131         return rc;
1132 }
1133
1134 static void
1135 otx2_sso_queue_def_conf(struct rte_eventdev *event_dev, uint8_t queue_id,
1136                         struct rte_event_queue_conf *queue_conf)
1137 {
1138         RTE_SET_USED(event_dev);
1139         RTE_SET_USED(queue_id);
1140
1141         queue_conf->nb_atomic_flows = (1ULL << 20);
1142         queue_conf->nb_atomic_order_sequences = (1ULL << 20);
1143         queue_conf->event_queue_cfg = RTE_EVENT_QUEUE_CFG_ALL_TYPES;
1144         queue_conf->priority = RTE_EVENT_DEV_PRIORITY_NORMAL;
1145 }
1146
1147 static int
1148 otx2_sso_queue_setup(struct rte_eventdev *event_dev, uint8_t queue_id,
1149                      const struct rte_event_queue_conf *queue_conf)
1150 {
1151         struct otx2_sso_evdev *dev = sso_pmd_priv(event_dev);
1152         struct otx2_mbox *mbox = dev->mbox;
1153         struct sso_grp_priority *req;
1154         int rc;
1155
1156         sso_func_trace("Queue=%d prio=%d", queue_id, queue_conf->priority);
1157
1158         req = otx2_mbox_alloc_msg_sso_grp_set_priority(dev->mbox);
1159         req->grp = queue_id;
1160         req->weight = 0xFF;
1161         req->affinity = 0xFF;
1162         /* Normalize <0-255> to <0-7> */
1163         req->priority = queue_conf->priority / 32;
1164
1165         rc = otx2_mbox_process(mbox);
1166         if (rc < 0) {
1167                 otx2_err("Failed to set priority queue=%d", queue_id);
1168                 return rc;
1169         }
1170
1171         return 0;
1172 }
1173
1174 static void
1175 otx2_sso_port_def_conf(struct rte_eventdev *event_dev, uint8_t port_id,
1176                        struct rte_event_port_conf *port_conf)
1177 {
1178         struct otx2_sso_evdev *dev = sso_pmd_priv(event_dev);
1179
1180         RTE_SET_USED(port_id);
1181         port_conf->new_event_threshold = dev->max_num_events;
1182         port_conf->dequeue_depth = 1;
1183         port_conf->enqueue_depth = 1;
1184 }
1185
1186 static int
1187 otx2_sso_port_setup(struct rte_eventdev *event_dev, uint8_t port_id,
1188                     const struct rte_event_port_conf *port_conf)
1189 {
1190         struct otx2_sso_evdev *dev = sso_pmd_priv(event_dev);
1191         uintptr_t grps_base[OTX2_SSO_MAX_VHGRP] = {0};
1192         uint64_t val;
1193         uint16_t q;
1194
1195         sso_func_trace("Port=%d", port_id);
1196         RTE_SET_USED(port_conf);
1197
1198         if (event_dev->data->ports[port_id] == NULL) {
1199                 otx2_err("Invalid port Id %d", port_id);
1200                 return -EINVAL;
1201         }
1202
1203         for (q = 0; q < dev->nb_event_queues; q++) {
1204                 grps_base[q] = dev->bar2 + (RVU_BLOCK_ADDR_SSO << 20 | q << 12);
1205                 if (grps_base[q] == 0) {
1206                         otx2_err("Failed to get grp[%d] base addr", q);
1207                         return -EINVAL;
1208                 }
1209         }
1210
1211         /* Set get_work timeout for HWS */
1212         val = NSEC2USEC(dev->deq_tmo_ns) - 1;
1213
1214         if (dev->dual_ws) {
1215                 struct otx2_ssogws_dual *ws = event_dev->data->ports[port_id];
1216
1217                 rte_memcpy(ws->grps_base, grps_base,
1218                            sizeof(uintptr_t) * OTX2_SSO_MAX_VHGRP);
1219                 ws->fc_mem = dev->fc_mem;
1220                 ws->xaq_lmt = dev->xaq_lmt;
1221                 ws->tstamp = dev->tstamp;
1222                 otx2_write64(val, OTX2_SSOW_GET_BASE_ADDR(
1223                              ws->ws_state[0].getwrk_op) + SSOW_LF_GWS_NW_TIM);
1224                 otx2_write64(val, OTX2_SSOW_GET_BASE_ADDR(
1225                              ws->ws_state[1].getwrk_op) + SSOW_LF_GWS_NW_TIM);
1226         } else {
1227                 struct otx2_ssogws *ws = event_dev->data->ports[port_id];
1228                 uintptr_t base = OTX2_SSOW_GET_BASE_ADDR(ws->getwrk_op);
1229
1230                 rte_memcpy(ws->grps_base, grps_base,
1231                            sizeof(uintptr_t) * OTX2_SSO_MAX_VHGRP);
1232                 ws->fc_mem = dev->fc_mem;
1233                 ws->xaq_lmt = dev->xaq_lmt;
1234                 ws->tstamp = dev->tstamp;
1235                 otx2_write64(val, base + SSOW_LF_GWS_NW_TIM);
1236         }
1237
1238         otx2_sso_dbg("Port=%d ws=%p", port_id, event_dev->data->ports[port_id]);
1239
1240         return 0;
1241 }
1242
1243 static int
1244 otx2_sso_timeout_ticks(struct rte_eventdev *event_dev, uint64_t ns,
1245                        uint64_t *tmo_ticks)
1246 {
1247         RTE_SET_USED(event_dev);
1248         *tmo_ticks = NSEC2TICK(ns, rte_get_timer_hz());
1249
1250         return 0;
1251 }
1252
1253 static void
1254 ssogws_dump(struct otx2_ssogws *ws, FILE *f)
1255 {
1256         uintptr_t base = OTX2_SSOW_GET_BASE_ADDR(ws->getwrk_op);
1257
1258         fprintf(f, "SSOW_LF_GWS Base addr   0x%" PRIx64 "\n", (uint64_t)base);
1259         fprintf(f, "SSOW_LF_GWS_LINKS       0x%" PRIx64 "\n",
1260                 otx2_read64(base + SSOW_LF_GWS_LINKS));
1261         fprintf(f, "SSOW_LF_GWS_PENDWQP     0x%" PRIx64 "\n",
1262                 otx2_read64(base + SSOW_LF_GWS_PENDWQP));
1263         fprintf(f, "SSOW_LF_GWS_PENDSTATE   0x%" PRIx64 "\n",
1264                 otx2_read64(base + SSOW_LF_GWS_PENDSTATE));
1265         fprintf(f, "SSOW_LF_GWS_NW_TIM      0x%" PRIx64 "\n",
1266                 otx2_read64(base + SSOW_LF_GWS_NW_TIM));
1267         fprintf(f, "SSOW_LF_GWS_TAG         0x%" PRIx64 "\n",
1268                 otx2_read64(base + SSOW_LF_GWS_TAG));
1269         fprintf(f, "SSOW_LF_GWS_WQP         0x%" PRIx64 "\n",
1270                 otx2_read64(base + SSOW_LF_GWS_TAG));
1271         fprintf(f, "SSOW_LF_GWS_SWTP        0x%" PRIx64 "\n",
1272                 otx2_read64(base + SSOW_LF_GWS_SWTP));
1273         fprintf(f, "SSOW_LF_GWS_PENDTAG     0x%" PRIx64 "\n",
1274                 otx2_read64(base + SSOW_LF_GWS_PENDTAG));
1275 }
1276
1277 static void
1278 ssoggrp_dump(uintptr_t base, FILE *f)
1279 {
1280         fprintf(f, "SSO_LF_GGRP Base addr   0x%" PRIx64 "\n", (uint64_t)base);
1281         fprintf(f, "SSO_LF_GGRP_QCTL        0x%" PRIx64 "\n",
1282                 otx2_read64(base + SSO_LF_GGRP_QCTL));
1283         fprintf(f, "SSO_LF_GGRP_XAQ_CNT     0x%" PRIx64 "\n",
1284                 otx2_read64(base + SSO_LF_GGRP_XAQ_CNT));
1285         fprintf(f, "SSO_LF_GGRP_INT_THR     0x%" PRIx64 "\n",
1286                 otx2_read64(base + SSO_LF_GGRP_INT_THR));
1287         fprintf(f, "SSO_LF_GGRP_INT_CNT     0x%" PRIX64 "\n",
1288                 otx2_read64(base + SSO_LF_GGRP_INT_CNT));
1289         fprintf(f, "SSO_LF_GGRP_AQ_CNT      0x%" PRIX64 "\n",
1290                 otx2_read64(base + SSO_LF_GGRP_AQ_CNT));
1291         fprintf(f, "SSO_LF_GGRP_AQ_THR      0x%" PRIX64 "\n",
1292                 otx2_read64(base + SSO_LF_GGRP_AQ_THR));
1293         fprintf(f, "SSO_LF_GGRP_MISC_CNT    0x%" PRIx64 "\n",
1294                 otx2_read64(base + SSO_LF_GGRP_MISC_CNT));
1295 }
1296
1297 static void
1298 otx2_sso_dump(struct rte_eventdev *event_dev, FILE *f)
1299 {
1300         struct otx2_sso_evdev *dev = sso_pmd_priv(event_dev);
1301         uint8_t queue;
1302         uint8_t port;
1303
1304         fprintf(f, "[%s] SSO running in [%s] mode\n", __func__, dev->dual_ws ?
1305                 "dual_ws" : "single_ws");
1306         /* Dump SSOW registers */
1307         for (port = 0; port < dev->nb_event_ports; port++) {
1308                 if (dev->dual_ws) {
1309                         struct otx2_ssogws_dual *ws =
1310                                 event_dev->data->ports[port];
1311
1312                         fprintf(f, "[%s] SSO dual workslot[%d] vws[%d] dump\n",
1313                                 __func__, port, 0);
1314                         ssogws_dump((struct otx2_ssogws *)&ws->ws_state[0], f);
1315                         fprintf(f, "[%s]SSO dual workslot[%d] vws[%d] dump\n",
1316                                 __func__, port, 1);
1317                         ssogws_dump((struct otx2_ssogws *)&ws->ws_state[1], f);
1318                 } else {
1319                         fprintf(f, "[%s]SSO single workslot[%d] dump\n",
1320                                 __func__, port);
1321                         ssogws_dump(event_dev->data->ports[port], f);
1322                 }
1323         }
1324
1325         /* Dump SSO registers */
1326         for (queue = 0; queue < dev->nb_event_queues; queue++) {
1327                 fprintf(f, "[%s]SSO group[%d] dump\n", __func__, queue);
1328                 if (dev->dual_ws) {
1329                         struct otx2_ssogws_dual *ws = event_dev->data->ports[0];
1330                         ssoggrp_dump(ws->grps_base[queue], f);
1331                 } else {
1332                         struct otx2_ssogws *ws = event_dev->data->ports[0];
1333                         ssoggrp_dump(ws->grps_base[queue], f);
1334                 }
1335         }
1336 }
1337
1338 static void
1339 otx2_handle_event(void *arg, struct rte_event event)
1340 {
1341         struct rte_eventdev *event_dev = arg;
1342
1343         if (event_dev->dev_ops->dev_stop_flush != NULL)
1344                 event_dev->dev_ops->dev_stop_flush(event_dev->data->dev_id,
1345                                 event, event_dev->data->dev_stop_flush_arg);
1346 }
1347
1348 static void
1349 sso_qos_cfg(struct rte_eventdev *event_dev)
1350 {
1351         struct otx2_sso_evdev *dev = sso_pmd_priv(event_dev);
1352         struct sso_grp_qos_cfg *req;
1353         uint16_t i;
1354
1355         for (i = 0; i < dev->qos_queue_cnt; i++) {
1356                 uint8_t xaq_prcnt = dev->qos_parse_data[i].xaq_prcnt;
1357                 uint8_t iaq_prcnt = dev->qos_parse_data[i].iaq_prcnt;
1358                 uint8_t taq_prcnt = dev->qos_parse_data[i].taq_prcnt;
1359
1360                 if (dev->qos_parse_data[i].queue >= dev->nb_event_queues)
1361                         continue;
1362
1363                 req = otx2_mbox_alloc_msg_sso_grp_qos_config(dev->mbox);
1364                 req->xaq_limit = (dev->nb_xaq_cfg *
1365                                   (xaq_prcnt ? xaq_prcnt : 100)) / 100;
1366                 req->taq_thr = (SSO_HWGRP_IAQ_MAX_THR_MASK *
1367                                 (iaq_prcnt ? iaq_prcnt : 100)) / 100;
1368                 req->iaq_thr = (SSO_HWGRP_TAQ_MAX_THR_MASK *
1369                                 (taq_prcnt ? taq_prcnt : 100)) / 100;
1370         }
1371
1372         if (dev->qos_queue_cnt)
1373                 otx2_mbox_process(dev->mbox);
1374 }
1375
1376 static void
1377 sso_cleanup(struct rte_eventdev *event_dev, uint8_t enable)
1378 {
1379         struct otx2_sso_evdev *dev = sso_pmd_priv(event_dev);
1380         uint16_t i;
1381
1382         for (i = 0; i < dev->nb_event_ports; i++) {
1383                 if (dev->dual_ws) {
1384                         struct otx2_ssogws_dual *ws;
1385
1386                         ws = event_dev->data->ports[i];
1387                         ssogws_reset((struct otx2_ssogws *)&ws->ws_state[0]);
1388                         ssogws_reset((struct otx2_ssogws *)&ws->ws_state[1]);
1389                         ws->swtag_req = 0;
1390                         ws->vws = 0;
1391                         ws->ws_state[0].cur_grp = 0;
1392                         ws->ws_state[0].cur_tt = SSO_SYNC_EMPTY;
1393                         ws->ws_state[1].cur_grp = 0;
1394                         ws->ws_state[1].cur_tt = SSO_SYNC_EMPTY;
1395                 } else {
1396                         struct otx2_ssogws *ws;
1397
1398                         ws = event_dev->data->ports[i];
1399                         ssogws_reset(ws);
1400                         ws->swtag_req = 0;
1401                         ws->cur_grp = 0;
1402                         ws->cur_tt = SSO_SYNC_EMPTY;
1403                 }
1404         }
1405
1406         rte_mb();
1407         if (dev->dual_ws) {
1408                 struct otx2_ssogws_dual *ws = event_dev->data->ports[0];
1409                 struct otx2_ssogws temp_ws;
1410
1411                 memcpy(&temp_ws, &ws->ws_state[0],
1412                        sizeof(struct otx2_ssogws_state));
1413                 for (i = 0; i < dev->nb_event_queues; i++) {
1414                         /* Consume all the events through HWS0 */
1415                         ssogws_flush_events(&temp_ws, i, ws->grps_base[i],
1416                                             otx2_handle_event, event_dev);
1417                         /* Enable/Disable SSO GGRP */
1418                         otx2_write64(enable, ws->grps_base[i] +
1419                                      SSO_LF_GGRP_QCTL);
1420                 }
1421                 ws->ws_state[0].cur_grp = 0;
1422                 ws->ws_state[0].cur_tt = SSO_SYNC_EMPTY;
1423         } else {
1424                 struct otx2_ssogws *ws = event_dev->data->ports[0];
1425
1426                 for (i = 0; i < dev->nb_event_queues; i++) {
1427                         /* Consume all the events through HWS0 */
1428                         ssogws_flush_events(ws, i, ws->grps_base[i],
1429                                             otx2_handle_event, event_dev);
1430                         /* Enable/Disable SSO GGRP */
1431                         otx2_write64(enable, ws->grps_base[i] +
1432                                      SSO_LF_GGRP_QCTL);
1433                 }
1434                 ws->cur_grp = 0;
1435                 ws->cur_tt = SSO_SYNC_EMPTY;
1436         }
1437
1438         /* reset SSO GWS cache */
1439         otx2_mbox_alloc_msg_sso_ws_cache_inv(dev->mbox);
1440         otx2_mbox_process(dev->mbox);
1441 }
1442
1443 int
1444 sso_xae_reconfigure(struct rte_eventdev *event_dev)
1445 {
1446         struct otx2_sso_evdev *dev = sso_pmd_priv(event_dev);
1447         struct rte_mempool *prev_xaq_pool;
1448         int rc = 0;
1449
1450         if (event_dev->data->dev_started)
1451                 sso_cleanup(event_dev, 0);
1452
1453         prev_xaq_pool = dev->xaq_pool;
1454         dev->xaq_pool = NULL;
1455         rc = sso_xaq_allocate(dev);
1456         if (rc < 0) {
1457                 otx2_err("Failed to alloc xaq pool %d", rc);
1458                 rte_mempool_free(prev_xaq_pool);
1459                 return rc;
1460         }
1461         rc = sso_ggrp_alloc_xaq(dev);
1462         if (rc < 0) {
1463                 otx2_err("Failed to alloc xaq to ggrp %d", rc);
1464                 rte_mempool_free(prev_xaq_pool);
1465                 return rc;
1466         }
1467
1468         rte_mempool_free(prev_xaq_pool);
1469         rte_mb();
1470         if (event_dev->data->dev_started)
1471                 sso_cleanup(event_dev, 1);
1472
1473         return 0;
1474 }
1475
1476 static int
1477 otx2_sso_start(struct rte_eventdev *event_dev)
1478 {
1479         sso_func_trace();
1480         sso_qos_cfg(event_dev);
1481         sso_cleanup(event_dev, 1);
1482         sso_fastpath_fns_set(event_dev);
1483
1484         return 0;
1485 }
1486
1487 static void
1488 otx2_sso_stop(struct rte_eventdev *event_dev)
1489 {
1490         sso_func_trace();
1491         sso_cleanup(event_dev, 0);
1492         rte_mb();
1493 }
1494
1495 static int
1496 otx2_sso_close(struct rte_eventdev *event_dev)
1497 {
1498         struct otx2_sso_evdev *dev = sso_pmd_priv(event_dev);
1499         uint8_t all_queues[RTE_EVENT_MAX_QUEUES_PER_DEV];
1500         uint16_t i;
1501
1502         if (!dev->configured)
1503                 return 0;
1504
1505         sso_unregister_irqs(event_dev);
1506
1507         for (i = 0; i < dev->nb_event_queues; i++)
1508                 all_queues[i] = i;
1509
1510         for (i = 0; i < dev->nb_event_ports; i++)
1511                 otx2_sso_port_unlink(event_dev, event_dev->data->ports[i],
1512                                      all_queues, dev->nb_event_queues);
1513
1514         sso_lf_teardown(dev, SSO_LF_GGRP);
1515         sso_lf_teardown(dev, SSO_LF_GWS);
1516         dev->nb_event_ports = 0;
1517         dev->nb_event_queues = 0;
1518         rte_mempool_free(dev->xaq_pool);
1519         rte_memzone_free(rte_memzone_lookup(OTX2_SSO_FC_NAME));
1520
1521         return 0;
1522 }
1523
1524 /* Initialize and register event driver with DPDK Application */
1525 static struct rte_eventdev_ops otx2_sso_ops = {
1526         .dev_infos_get    = otx2_sso_info_get,
1527         .dev_configure    = otx2_sso_configure,
1528         .queue_def_conf   = otx2_sso_queue_def_conf,
1529         .queue_setup      = otx2_sso_queue_setup,
1530         .queue_release    = otx2_sso_queue_release,
1531         .port_def_conf    = otx2_sso_port_def_conf,
1532         .port_setup       = otx2_sso_port_setup,
1533         .port_release     = otx2_sso_port_release,
1534         .port_link        = otx2_sso_port_link,
1535         .port_unlink      = otx2_sso_port_unlink,
1536         .timeout_ticks    = otx2_sso_timeout_ticks,
1537
1538         .eth_rx_adapter_caps_get  = otx2_sso_rx_adapter_caps_get,
1539         .eth_rx_adapter_queue_add = otx2_sso_rx_adapter_queue_add,
1540         .eth_rx_adapter_queue_del = otx2_sso_rx_adapter_queue_del,
1541         .eth_rx_adapter_start = otx2_sso_rx_adapter_start,
1542         .eth_rx_adapter_stop = otx2_sso_rx_adapter_stop,
1543
1544         .eth_tx_adapter_caps_get = otx2_sso_tx_adapter_caps_get,
1545         .eth_tx_adapter_queue_add = otx2_sso_tx_adapter_queue_add,
1546         .eth_tx_adapter_queue_del = otx2_sso_tx_adapter_queue_del,
1547
1548         .timer_adapter_caps_get = otx2_tim_caps_get,
1549
1550         .xstats_get       = otx2_sso_xstats_get,
1551         .xstats_reset     = otx2_sso_xstats_reset,
1552         .xstats_get_names = otx2_sso_xstats_get_names,
1553
1554         .dump             = otx2_sso_dump,
1555         .dev_start        = otx2_sso_start,
1556         .dev_stop         = otx2_sso_stop,
1557         .dev_close        = otx2_sso_close,
1558         .dev_selftest     = otx2_sso_selftest,
1559 };
1560
1561 #define OTX2_SSO_XAE_CNT        "xae_cnt"
1562 #define OTX2_SSO_SINGLE_WS      "single_ws"
1563 #define OTX2_SSO_GGRP_QOS       "qos"
1564 #define OTX2_SSO_SELFTEST       "selftest"
1565
1566 static void
1567 parse_queue_param(char *value, void *opaque)
1568 {
1569         struct otx2_sso_qos queue_qos = {0};
1570         uint8_t *val = (uint8_t *)&queue_qos;
1571         struct otx2_sso_evdev *dev = opaque;
1572         char *tok = strtok(value, "-");
1573         struct otx2_sso_qos *old_ptr;
1574
1575         if (!strlen(value))
1576                 return;
1577
1578         while (tok != NULL) {
1579                 *val = atoi(tok);
1580                 tok = strtok(NULL, "-");
1581                 val++;
1582         }
1583
1584         if (val != (&queue_qos.iaq_prcnt + 1)) {
1585                 otx2_err("Invalid QoS parameter expected [Qx-XAQ-TAQ-IAQ]");
1586                 return;
1587         }
1588
1589         dev->qos_queue_cnt++;
1590         old_ptr = dev->qos_parse_data;
1591         dev->qos_parse_data = rte_realloc(dev->qos_parse_data,
1592                                           sizeof(struct otx2_sso_qos) *
1593                                           dev->qos_queue_cnt, 0);
1594         if (dev->qos_parse_data == NULL) {
1595                 dev->qos_parse_data = old_ptr;
1596                 dev->qos_queue_cnt--;
1597                 return;
1598         }
1599         dev->qos_parse_data[dev->qos_queue_cnt - 1] = queue_qos;
1600 }
1601
1602 static void
1603 parse_qos_list(const char *value, void *opaque)
1604 {
1605         char *s = strdup(value);
1606         char *start = NULL;
1607         char *end = NULL;
1608         char *f = s;
1609
1610         while (*s) {
1611                 if (*s == '[')
1612                         start = s;
1613                 else if (*s == ']')
1614                         end = s;
1615
1616                 if (start && start < end) {
1617                         *end = 0;
1618                         parse_queue_param(start + 1, opaque);
1619                         s = end;
1620                         start = end;
1621                 }
1622                 s++;
1623         }
1624
1625         free(f);
1626 }
1627
1628 static int
1629 parse_sso_kvargs_dict(const char *key, const char *value, void *opaque)
1630 {
1631         RTE_SET_USED(key);
1632
1633         /* Dict format [Qx-XAQ-TAQ-IAQ][Qz-XAQ-TAQ-IAQ] use '-' cause ','
1634          * isn't allowed. Everything is expressed in percentages, 0 represents
1635          * default.
1636          */
1637         parse_qos_list(value, opaque);
1638
1639         return 0;
1640 }
1641
1642 static void
1643 sso_parse_devargs(struct otx2_sso_evdev *dev, struct rte_devargs *devargs)
1644 {
1645         struct rte_kvargs *kvlist;
1646         uint8_t single_ws = 0;
1647
1648         if (devargs == NULL)
1649                 return;
1650         kvlist = rte_kvargs_parse(devargs->args, NULL);
1651         if (kvlist == NULL)
1652                 return;
1653
1654         rte_kvargs_process(kvlist, OTX2_SSO_SELFTEST, &parse_kvargs_flag,
1655                            &dev->selftest);
1656         rte_kvargs_process(kvlist, OTX2_SSO_XAE_CNT, &parse_kvargs_value,
1657                            &dev->xae_cnt);
1658         rte_kvargs_process(kvlist, OTX2_SSO_SINGLE_WS, &parse_kvargs_flag,
1659                            &single_ws);
1660         rte_kvargs_process(kvlist, OTX2_SSO_GGRP_QOS, &parse_sso_kvargs_dict,
1661                            dev);
1662
1663         dev->dual_ws = !single_ws;
1664         rte_kvargs_free(kvlist);
1665 }
1666
1667 static int
1668 otx2_sso_probe(struct rte_pci_driver *pci_drv, struct rte_pci_device *pci_dev)
1669 {
1670         return rte_event_pmd_pci_probe(pci_drv, pci_dev,
1671                                        sizeof(struct otx2_sso_evdev),
1672                                        otx2_sso_init);
1673 }
1674
1675 static int
1676 otx2_sso_remove(struct rte_pci_device *pci_dev)
1677 {
1678         return rte_event_pmd_pci_remove(pci_dev, otx2_sso_fini);
1679 }
1680
1681 static const struct rte_pci_id pci_sso_map[] = {
1682         {
1683                 RTE_PCI_DEVICE(PCI_VENDOR_ID_CAVIUM,
1684                                PCI_DEVID_OCTEONTX2_RVU_SSO_TIM_PF)
1685         },
1686         {
1687                 .vendor_id = 0,
1688         },
1689 };
1690
1691 static struct rte_pci_driver pci_sso = {
1692         .id_table = pci_sso_map,
1693         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_NEED_IOVA_AS_VA,
1694         .probe = otx2_sso_probe,
1695         .remove = otx2_sso_remove,
1696 };
1697
1698 int
1699 otx2_sso_init(struct rte_eventdev *event_dev)
1700 {
1701         struct free_rsrcs_rsp *rsrc_cnt;
1702         struct rte_pci_device *pci_dev;
1703         struct otx2_sso_evdev *dev;
1704         int rc;
1705
1706         event_dev->dev_ops = &otx2_sso_ops;
1707         /* For secondary processes, the primary has done all the work */
1708         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
1709                 sso_fastpath_fns_set(event_dev);
1710                 return 0;
1711         }
1712
1713         dev = sso_pmd_priv(event_dev);
1714
1715         pci_dev = container_of(event_dev->dev, struct rte_pci_device, device);
1716
1717         /* Initialize the base otx2_dev object */
1718         rc = otx2_dev_init(pci_dev, dev);
1719         if (rc < 0) {
1720                 otx2_err("Failed to initialize otx2_dev rc=%d", rc);
1721                 goto error;
1722         }
1723
1724         /* Get SSO and SSOW MSIX rsrc cnt */
1725         otx2_mbox_alloc_msg_free_rsrc_cnt(dev->mbox);
1726         rc = otx2_mbox_process_msg(dev->mbox, (void *)&rsrc_cnt);
1727         if (rc < 0) {
1728                 otx2_err("Unable to get free rsrc count");
1729                 goto otx2_dev_uninit;
1730         }
1731         otx2_sso_dbg("SSO %d SSOW %d NPA %d provisioned", rsrc_cnt->sso,
1732                      rsrc_cnt->ssow, rsrc_cnt->npa);
1733
1734         dev->max_event_ports = RTE_MIN(rsrc_cnt->ssow, OTX2_SSO_MAX_VHWS);
1735         dev->max_event_queues = RTE_MIN(rsrc_cnt->sso, OTX2_SSO_MAX_VHGRP);
1736         /* Grab the NPA LF if required */
1737         rc = otx2_npa_lf_init(pci_dev, dev);
1738         if (rc < 0) {
1739                 otx2_err("Unable to init NPA lf. It might not be provisioned");
1740                 goto otx2_dev_uninit;
1741         }
1742
1743         dev->drv_inited = true;
1744         dev->is_timeout_deq = 0;
1745         dev->min_dequeue_timeout_ns = USEC2NSEC(1);
1746         dev->max_dequeue_timeout_ns = USEC2NSEC(0x3FF);
1747         dev->max_num_events = -1;
1748         dev->nb_event_queues = 0;
1749         dev->nb_event_ports = 0;
1750
1751         if (!dev->max_event_ports || !dev->max_event_queues) {
1752                 otx2_err("Not enough eventdev resource queues=%d ports=%d",
1753                          dev->max_event_queues, dev->max_event_ports);
1754                 rc = -ENODEV;
1755                 goto otx2_npa_lf_uninit;
1756         }
1757
1758         dev->dual_ws = 1;
1759         sso_parse_devargs(dev, pci_dev->device.devargs);
1760         if (dev->dual_ws) {
1761                 otx2_sso_dbg("Using dual workslot mode");
1762                 dev->max_event_ports = dev->max_event_ports / 2;
1763         } else {
1764                 otx2_sso_dbg("Using single workslot mode");
1765         }
1766
1767         otx2_sso_pf_func_set(dev->pf_func);
1768         otx2_sso_dbg("Initializing %s max_queues=%d max_ports=%d",
1769                      event_dev->data->name, dev->max_event_queues,
1770                      dev->max_event_ports);
1771         if (dev->selftest) {
1772                 event_dev->dev->driver = &pci_sso.driver;
1773                 event_dev->dev_ops->dev_selftest();
1774         }
1775
1776         otx2_tim_init(pci_dev, (struct otx2_dev *)dev);
1777
1778         return 0;
1779
1780 otx2_npa_lf_uninit:
1781         otx2_npa_lf_fini();
1782 otx2_dev_uninit:
1783         otx2_dev_fini(pci_dev, dev);
1784 error:
1785         return rc;
1786 }
1787
1788 int
1789 otx2_sso_fini(struct rte_eventdev *event_dev)
1790 {
1791         struct otx2_sso_evdev *dev = sso_pmd_priv(event_dev);
1792         struct rte_pci_device *pci_dev;
1793
1794         /* For secondary processes, nothing to be done */
1795         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1796                 return 0;
1797
1798         pci_dev = container_of(event_dev->dev, struct rte_pci_device, device);
1799
1800         if (!dev->drv_inited)
1801                 goto dev_fini;
1802
1803         dev->drv_inited = false;
1804         otx2_npa_lf_fini();
1805
1806 dev_fini:
1807         if (otx2_npa_lf_active(dev)) {
1808                 otx2_info("Common resource in use by other devices");
1809                 return -EAGAIN;
1810         }
1811
1812         otx2_tim_fini();
1813         otx2_dev_fini(pci_dev, dev);
1814
1815         return 0;
1816 }
1817
1818 RTE_PMD_REGISTER_PCI(event_octeontx2, pci_sso);
1819 RTE_PMD_REGISTER_PCI_TABLE(event_octeontx2, pci_sso_map);
1820 RTE_PMD_REGISTER_KMOD_DEP(event_octeontx2, "vfio-pci");
1821 RTE_PMD_REGISTER_PARAM_STRING(event_octeontx2, OTX2_SSO_XAE_CNT "=<int>"
1822                               OTX2_SSO_SINGLE_WS "=1"
1823                               OTX2_SSO_GGRP_QOS "=<string>"
1824                               OTX2_SSO_SELFTEST "=1");