1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(C) 2019 Marvell International Ltd.
5 #ifndef __OTX2_EVDEV_H__
6 #define __OTX2_EVDEV_H__
8 #include <rte_eventdev.h>
9 #include <rte_eventdev_pmd.h>
10 #include <rte_event_eth_rx_adapter.h>
12 #include "otx2_common.h"
14 #include "otx2_ethdev.h"
15 #include "otx2_mempool.h"
17 #define EVENTDEV_NAME_OCTEONTX2_PMD otx2_eventdev
19 #define sso_func_trace otx2_sso_dbg
21 #define OTX2_SSO_MAX_VHGRP RTE_EVENT_MAX_QUEUES_PER_DEV
22 #define OTX2_SSO_MAX_VHWS (UINT8_MAX)
23 #define OTX2_SSO_FC_NAME "otx2_evdev_xaq_fc"
24 #define OTX2_SSO_XAQ_SLACK (8)
25 #define OTX2_SSO_XAQ_CACHE_CNT (0x7)
27 /* SSO LF register offsets (BAR2) */
28 #define SSO_LF_GGRP_OP_ADD_WORK0 (0x0ull)
29 #define SSO_LF_GGRP_OP_ADD_WORK1 (0x8ull)
31 #define SSO_LF_GGRP_QCTL (0x20ull)
32 #define SSO_LF_GGRP_EXE_DIS (0x80ull)
33 #define SSO_LF_GGRP_INT (0x100ull)
34 #define SSO_LF_GGRP_INT_W1S (0x108ull)
35 #define SSO_LF_GGRP_INT_ENA_W1S (0x110ull)
36 #define SSO_LF_GGRP_INT_ENA_W1C (0x118ull)
37 #define SSO_LF_GGRP_INT_THR (0x140ull)
38 #define SSO_LF_GGRP_INT_CNT (0x180ull)
39 #define SSO_LF_GGRP_XAQ_CNT (0x1b0ull)
40 #define SSO_LF_GGRP_AQ_CNT (0x1c0ull)
41 #define SSO_LF_GGRP_AQ_THR (0x1e0ull)
42 #define SSO_LF_GGRP_MISC_CNT (0x200ull)
44 /* SSOW LF register offsets (BAR2) */
45 #define SSOW_LF_GWS_LINKS (0x10ull)
46 #define SSOW_LF_GWS_PENDWQP (0x40ull)
47 #define SSOW_LF_GWS_PENDSTATE (0x50ull)
48 #define SSOW_LF_GWS_NW_TIM (0x70ull)
49 #define SSOW_LF_GWS_GRPMSK_CHG (0x80ull)
50 #define SSOW_LF_GWS_INT (0x100ull)
51 #define SSOW_LF_GWS_INT_W1S (0x108ull)
52 #define SSOW_LF_GWS_INT_ENA_W1S (0x110ull)
53 #define SSOW_LF_GWS_INT_ENA_W1C (0x118ull)
54 #define SSOW_LF_GWS_TAG (0x200ull)
55 #define SSOW_LF_GWS_WQP (0x210ull)
56 #define SSOW_LF_GWS_SWTP (0x220ull)
57 #define SSOW_LF_GWS_PENDTAG (0x230ull)
58 #define SSOW_LF_GWS_OP_ALLOC_WE (0x400ull)
59 #define SSOW_LF_GWS_OP_GET_WORK (0x600ull)
60 #define SSOW_LF_GWS_OP_SWTAG_FLUSH (0x800ull)
61 #define SSOW_LF_GWS_OP_SWTAG_UNTAG (0x810ull)
62 #define SSOW_LF_GWS_OP_SWTP_CLR (0x820ull)
63 #define SSOW_LF_GWS_OP_UPD_WQP_GRP0 (0x830ull)
64 #define SSOW_LF_GWS_OP_UPD_WQP_GRP1 (0x838ull)
65 #define SSOW_LF_GWS_OP_DESCHED (0x880ull)
66 #define SSOW_LF_GWS_OP_DESCHED_NOSCH (0x8c0ull)
67 #define SSOW_LF_GWS_OP_SWTAG_DESCHED (0x980ull)
68 #define SSOW_LF_GWS_OP_SWTAG_NOSCHED (0x9c0ull)
69 #define SSOW_LF_GWS_OP_CLR_NSCHED0 (0xa00ull)
70 #define SSOW_LF_GWS_OP_CLR_NSCHED1 (0xa08ull)
71 #define SSOW_LF_GWS_OP_SWTP_SET (0xc00ull)
72 #define SSOW_LF_GWS_OP_SWTAG_NORM (0xc10ull)
73 #define SSOW_LF_GWS_OP_SWTAG_FULL0 (0xc20ull)
74 #define SSOW_LF_GWS_OP_SWTAG_FULL1 (0xc28ull)
75 #define SSOW_LF_GWS_OP_GWC_INVAL (0xe00ull)
77 #define OTX2_SSOW_GET_BASE_ADDR(_GW) ((_GW) - SSOW_LF_GWS_OP_GET_WORK)
79 #define NSEC2USEC(__ns) ((__ns) / 1E3)
80 #define USEC2NSEC(__us) ((__us) * 1E3)
81 #define NSEC2TICK(__ns, __freq) (((__ns) * (__freq)) / 1E9)
82 #define TICK2NSEC(__tck, __freq) (((__tck) * 1E9) / (__freq))
84 enum otx2_sso_lf_type {
89 union otx2_sso_event {
93 uint32_t sub_event_type:8;
94 uint32_t event_type:4;
111 struct otx2_sso_qos {
118 struct otx2_sso_evdev {
119 OTX2_DEV; /* Base class */
120 uint8_t max_event_queues;
121 uint8_t max_event_ports;
122 uint8_t is_timeout_deq;
123 uint8_t nb_event_queues;
124 uint8_t nb_event_ports;
127 uint32_t min_dequeue_timeout_ns;
128 uint32_t max_dequeue_timeout_ns;
129 int32_t max_num_events;
134 struct rte_mempool *xaq_pool;
135 uint64_t rx_offloads;
136 uint16_t rx_adptr_pool_cnt;
137 uint32_t adptr_xae_cnt;
138 uint64_t *rx_adptr_pools;
143 uint8_t qos_queue_cnt;
144 struct otx2_sso_qos *qos_parse_data;
147 uint32_t xaq_buf_size;
150 uint16_t sso_msixoff[OTX2_SSO_MAX_VHGRP];
151 uint16_t ssow_msixoff[OTX2_SSO_MAX_VHWS];
153 struct otx2_timesync_info *tstamp;
154 } __rte_cache_aligned;
156 #define OTX2_SSOGWS_OPS \
158 uintptr_t getwrk_op; \
162 uintptr_t swtag_norm_op; \
163 uintptr_t swtag_desched_op; \
167 /* Event port aka GWS */
169 /* Get Work Fastpath data */
174 /* Add Work Fastpath data */
175 uint64_t xaq_lmt __rte_cache_aligned;
177 uintptr_t grps_base[OTX2_SSO_MAX_VHGRP];
179 struct otx2_timesync_info *tstamp;
180 } __rte_cache_aligned;
182 struct otx2_ssogws_state {
186 struct otx2_ssogws_dual {
187 /* Get Work Fastpath data */
188 struct otx2_ssogws_state ws_state[2]; /* Ping and Pong */
190 uint8_t vws; /* Ping pong bit */
193 /* Add Work Fastpath data */
194 uint64_t xaq_lmt __rte_cache_aligned;
196 uintptr_t grps_base[OTX2_SSO_MAX_VHGRP];
198 struct otx2_timesync_info *tstamp;
199 } __rte_cache_aligned;
201 static inline struct otx2_sso_evdev *
202 sso_pmd_priv(const struct rte_eventdev *event_dev)
204 return event_dev->data->dev_private;
207 static const union mbuf_initializer mbuf_init = {
209 .data_off = RTE_PKTMBUF_HEADROOM,
216 static __rte_always_inline void
217 otx2_wqe_to_mbuf(uint64_t get_work1, const uint64_t mbuf, uint8_t port_id,
218 const uint32_t tag, const uint32_t flags,
219 const void * const lookup_mem)
221 struct nix_wqe_hdr_s *wqe = (struct nix_wqe_hdr_s *)get_work1;
223 otx2_nix_cqe_to_mbuf((struct nix_cqe_hdr_s *)wqe, tag,
224 (struct rte_mbuf *)mbuf, lookup_mem,
225 mbuf_init.value | (uint64_t)port_id << 48, flags);
230 parse_kvargs_flag(const char *key, const char *value, void *opaque)
234 *(uint8_t *)opaque = !!atoi(value);
239 parse_kvargs_value(const char *key, const char *value, void *opaque)
243 *(uint32_t *)opaque = (uint32_t)atoi(value);
247 #define SSO_RX_ADPTR_ENQ_FASTPATH_FUNC NIX_RX_FASTPATH_MODES
248 #define SSO_TX_ADPTR_ENQ_FASTPATH_FUNC NIX_TX_FASTPATH_MODES
250 /* Single WS API's */
251 uint16_t otx2_ssogws_enq(void *port, const struct rte_event *ev);
252 uint16_t otx2_ssogws_enq_burst(void *port, const struct rte_event ev[],
254 uint16_t otx2_ssogws_enq_new_burst(void *port, const struct rte_event ev[],
256 uint16_t otx2_ssogws_enq_fwd_burst(void *port, const struct rte_event ev[],
260 uint16_t otx2_ssogws_dual_enq(void *port, const struct rte_event *ev);
261 uint16_t otx2_ssogws_dual_enq_burst(void *port, const struct rte_event ev[],
263 uint16_t otx2_ssogws_dual_enq_new_burst(void *port, const struct rte_event ev[],
265 uint16_t otx2_ssogws_dual_enq_fwd_burst(void *port, const struct rte_event ev[],
268 /* Auto generated API's */
269 #define R(name, f5, f4, f3, f2, f1, f0, flags) \
270 uint16_t otx2_ssogws_deq_ ##name(void *port, struct rte_event *ev, \
271 uint64_t timeout_ticks); \
272 uint16_t otx2_ssogws_deq_burst_ ##name(void *port, struct rte_event ev[], \
273 uint16_t nb_events, \
274 uint64_t timeout_ticks); \
275 uint16_t otx2_ssogws_deq_timeout_ ##name(void *port, \
276 struct rte_event *ev, \
277 uint64_t timeout_ticks); \
278 uint16_t otx2_ssogws_deq_timeout_burst_ ##name(void *port, \
279 struct rte_event ev[], \
280 uint16_t nb_events, \
281 uint64_t timeout_ticks); \
282 uint16_t otx2_ssogws_deq_seg_ ##name(void *port, struct rte_event *ev, \
283 uint64_t timeout_ticks); \
284 uint16_t otx2_ssogws_deq_seg_burst_ ##name(void *port, \
285 struct rte_event ev[], \
286 uint16_t nb_events, \
287 uint64_t timeout_ticks); \
288 uint16_t otx2_ssogws_deq_seg_timeout_ ##name(void *port, \
289 struct rte_event *ev, \
290 uint64_t timeout_ticks); \
291 uint16_t otx2_ssogws_deq_seg_timeout_burst_ ##name(void *port, \
292 struct rte_event ev[], \
293 uint16_t nb_events, \
294 uint64_t timeout_ticks); \
296 uint16_t otx2_ssogws_dual_deq_ ##name(void *port, struct rte_event *ev, \
297 uint64_t timeout_ticks); \
298 uint16_t otx2_ssogws_dual_deq_burst_ ##name(void *port, \
299 struct rte_event ev[], \
300 uint16_t nb_events, \
301 uint64_t timeout_ticks); \
302 uint16_t otx2_ssogws_dual_deq_timeout_ ##name(void *port, \
303 struct rte_event *ev, \
304 uint64_t timeout_ticks); \
305 uint16_t otx2_ssogws_dual_deq_timeout_burst_ ##name(void *port, \
306 struct rte_event ev[], \
307 uint16_t nb_events, \
308 uint64_t timeout_ticks); \
309 uint16_t otx2_ssogws_dual_deq_seg_ ##name(void *port, struct rte_event *ev, \
310 uint64_t timeout_ticks); \
311 uint16_t otx2_ssogws_dual_deq_seg_burst_ ##name(void *port, \
312 struct rte_event ev[], \
313 uint16_t nb_events, \
314 uint64_t timeout_ticks); \
315 uint16_t otx2_ssogws_dual_deq_seg_timeout_ ##name(void *port, \
316 struct rte_event *ev, \
317 uint64_t timeout_ticks); \
318 uint16_t otx2_ssogws_dual_deq_seg_timeout_burst_ ##name(void *port, \
319 struct rte_event ev[], \
320 uint16_t nb_events, \
321 uint64_t timeout_ticks);\
323 SSO_RX_ADPTR_ENQ_FASTPATH_FUNC
326 void sso_updt_xae_cnt(struct otx2_sso_evdev *dev, void *data,
327 uint32_t event_type);
328 int sso_xae_reconfigure(struct rte_eventdev *event_dev);
329 void sso_fastpath_fns_set(struct rte_eventdev *event_dev);
331 int otx2_sso_rx_adapter_caps_get(const struct rte_eventdev *event_dev,
332 const struct rte_eth_dev *eth_dev,
334 int otx2_sso_rx_adapter_queue_add(const struct rte_eventdev *event_dev,
335 const struct rte_eth_dev *eth_dev,
337 const struct rte_event_eth_rx_adapter_queue_conf *queue_conf);
338 int otx2_sso_rx_adapter_queue_del(const struct rte_eventdev *event_dev,
339 const struct rte_eth_dev *eth_dev,
340 int32_t rx_queue_id);
341 int otx2_sso_rx_adapter_start(const struct rte_eventdev *event_dev,
342 const struct rte_eth_dev *eth_dev);
343 int otx2_sso_rx_adapter_stop(const struct rte_eventdev *event_dev,
344 const struct rte_eth_dev *eth_dev);
346 typedef void (*otx2_handle_event_t)(void *arg, struct rte_event ev);
347 void ssogws_flush_events(struct otx2_ssogws *ws, uint8_t queue_id,
348 uintptr_t base, otx2_handle_event_t fn, void *arg);
349 void ssogws_reset(struct otx2_ssogws *ws);
351 int otx2_sso_selftest(void);
352 /* Init and Fini API's */
353 int otx2_sso_init(struct rte_eventdev *event_dev);
354 int otx2_sso_fini(struct rte_eventdev *event_dev);
356 int sso_register_irqs(const struct rte_eventdev *event_dev);
357 void sso_unregister_irqs(const struct rte_eventdev *event_dev);
359 #endif /* __OTX2_EVDEV_H__ */