drivers/event/octeontx2/otx2_tim_evdev.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(C) 2019 Marvell International Ltd.
   3  */
   4
   5 #include <rte_kvargs.h>
   6 #include <rte_malloc.h>
   7 #include <rte_mbuf_pool_ops.h>
   8
   9 #include "otx2_evdev.h"
  10 #include "otx2_tim_evdev.h"
  11
  12 static struct rte_event_timer_adapter_ops otx2_tim_ops;
  13
  14 static void
  15 tim_optimze_bkt_param(struct otx2_tim_ring *tim_ring)
  16 {
  17         uint64_t tck_nsec;
  18         uint32_t hbkts;
  19         uint32_t lbkts;
  20
  21         hbkts = rte_align32pow2(tim_ring->nb_bkts);
  22         tck_nsec = RTE_ALIGN_MUL_CEIL(tim_ring->max_tout / (hbkts - 1), 10);
  23
  24         if ((tck_nsec < TICK2NSEC(OTX2_TIM_MIN_TMO_TKS,
  25                                   tim_ring->tenns_clk_freq) ||
  26             hbkts > OTX2_TIM_MAX_BUCKETS))
  27                 hbkts = 0;
  28
  29         lbkts = rte_align32prevpow2(tim_ring->nb_bkts);
  30         tck_nsec = RTE_ALIGN_MUL_CEIL((tim_ring->max_tout / (lbkts - 1)), 10);
  31
  32         if ((tck_nsec < TICK2NSEC(OTX2_TIM_MIN_TMO_TKS,
  33                                   tim_ring->tenns_clk_freq) ||
  34             lbkts > OTX2_TIM_MAX_BUCKETS))
  35                 lbkts = 0;
  36
  37         if (!hbkts && !lbkts)
  38                 return;
  39
  40         if (!hbkts) {
  41                 tim_ring->nb_bkts = lbkts;
  42                 goto end;
  43         } else if (!lbkts) {
  44                 tim_ring->nb_bkts = hbkts;
  45                 goto end;
  46         }
  47
  48         tim_ring->nb_bkts = (hbkts - tim_ring->nb_bkts) <
  49                 (tim_ring->nb_bkts - lbkts) ? hbkts : lbkts;
  50 end:
  51         tim_ring->optimized = true;
  52         tim_ring->tck_nsec = RTE_ALIGN_MUL_CEIL((tim_ring->max_tout /
  53                                                 (tim_ring->nb_bkts - 1)), 10);
  54         otx2_tim_dbg("Optimized configured values");
  55         otx2_tim_dbg("Nb_bkts  : %" PRIu32 "", tim_ring->nb_bkts);
  56         otx2_tim_dbg("Tck_nsec : %" PRIu64 "", tim_ring->tck_nsec);
  57 }
  58
  59 static int
  60 tim_chnk_pool_create(struct otx2_tim_ring *tim_ring,
  61                      struct rte_event_timer_adapter_conf *rcfg)
  62 {
  63         unsigned int cache_sz = (tim_ring->nb_chunks / 1.5);
  64         unsigned int mp_flags = 0;
  65         char pool_name[25];
  66         int rc;
  67
  68         /* Create chunk pool. */
  69         if (rcfg->flags & RTE_EVENT_TIMER_ADAPTER_F_SP_PUT) {
  70                 mp_flags = MEMPOOL_F_SP_PUT | MEMPOOL_F_SC_GET;
  71                 otx2_tim_dbg("Using single producer mode");
  72                 tim_ring->prod_type_sp = true;
  73         }
  74
  75         snprintf(pool_name, sizeof(pool_name), "otx2_tim_chunk_pool%d",
  76                  tim_ring->ring_id);
  77
  78         if (cache_sz > RTE_MEMPOOL_CACHE_MAX_SIZE)
  79                 cache_sz = RTE_MEMPOOL_CACHE_MAX_SIZE;
  80
  81         if (!tim_ring->disable_npa) {
  82                 /* NPA need not have cache as free is not visible to SW */
  83                 tim_ring->chunk_pool = rte_mempool_create_empty(pool_name,
  84                                 tim_ring->nb_chunks, tim_ring->chunk_sz,
  85                                 0, 0, rte_socket_id(), mp_flags);
  86
  87                 if (tim_ring->chunk_pool == NULL) {
  88                         otx2_err("Unable to create chunkpool.");
  89                         return -ENOMEM;
  90                 }
  91
  92                 rc = rte_mempool_set_ops_byname(tim_ring->chunk_pool,
  93                                                 rte_mbuf_platform_mempool_ops(),
  94                                                 NULL);
  95                 if (rc < 0) {
  96                         otx2_err("Unable to set chunkpool ops");
  97                         goto free;
  98                 }
  99
 100                 rc = rte_mempool_populate_default(tim_ring->chunk_pool);
 101                 if (rc < 0) {
 102                         otx2_err("Unable to set populate chunkpool.");
 103                         goto free;
 104                 }
 105                 tim_ring->aura = npa_lf_aura_handle_to_aura(
 106                                 tim_ring->chunk_pool->pool_id);
 107                 tim_ring->ena_dfb = 0;
 108         } else {
 109                 tim_ring->chunk_pool = rte_mempool_create(pool_name,
 110                                 tim_ring->nb_chunks, tim_ring->chunk_sz,
 111                                 cache_sz, 0, NULL, NULL, NULL, NULL,
 112                                 rte_socket_id(),
 113                                 mp_flags);
 114                 if (tim_ring->chunk_pool == NULL) {
 115                         otx2_err("Unable to create chunkpool.");
 116                         return -ENOMEM;
 117                 }
 118                 tim_ring->ena_dfb = 1;
 119         }
 120
 121         return 0;
 122
 123 free:
 124         rte_mempool_free(tim_ring->chunk_pool);
 125         return rc;
 126 }
 127
 128 static void
 129 tim_err_desc(int rc)
 130 {
 131         switch (rc) {
 132         case TIM_AF_NO_RINGS_LEFT:
 133                 otx2_err("Unable to allocat new TIM ring.");
 134                 break;
 135         case TIM_AF_INVALID_NPA_PF_FUNC:
 136                 otx2_err("Invalid NPA pf func.");
 137                 break;
 138         case TIM_AF_INVALID_SSO_PF_FUNC:
 139                 otx2_err("Invalid SSO pf func.");
 140                 break;
 141         case TIM_AF_RING_STILL_RUNNING:
 142                 otx2_tim_dbg("Ring busy.");
 143                 break;
 144         case TIM_AF_LF_INVALID:
 145                 otx2_err("Invalid Ring id.");
 146                 break;
 147         case TIM_AF_CSIZE_NOT_ALIGNED:
 148                 otx2_err("Chunk size specified needs to be multiple of 16.");
 149                 break;
 150         case TIM_AF_CSIZE_TOO_SMALL:
 151                 otx2_err("Chunk size too small.");
 152                 break;
 153         case TIM_AF_CSIZE_TOO_BIG:
 154                 otx2_err("Chunk size too big.");
 155                 break;
 156         case TIM_AF_INTERVAL_TOO_SMALL:
 157                 otx2_err("Bucket traversal interval too small.");
 158                 break;
 159         case TIM_AF_INVALID_BIG_ENDIAN_VALUE:
 160                 otx2_err("Invalid Big endian value.");
 161                 break;
 162         case TIM_AF_INVALID_CLOCK_SOURCE:
 163                 otx2_err("Invalid Clock source specified.");
 164                 break;
 165         case TIM_AF_GPIO_CLK_SRC_NOT_ENABLED:
 166                 otx2_err("GPIO clock source not enabled.");
 167                 break;
 168         case TIM_AF_INVALID_BSIZE:
 169                 otx2_err("Invalid bucket size.");
 170                 break;
 171         case TIM_AF_INVALID_ENABLE_PERIODIC:
 172                 otx2_err("Invalid bucket size.");
 173                 break;
 174         case TIM_AF_INVALID_ENABLE_DONTFREE:
 175                 otx2_err("Invalid Don't free value.");
 176                 break;
 177         case TIM_AF_ENA_DONTFRE_NSET_PERIODIC:
 178                 otx2_err("Don't free bit not set when periodic is enabled.");
 179                 break;
 180         case TIM_AF_RING_ALREADY_DISABLED:
 181                 otx2_err("Ring already stopped");
 182                 break;
 183         default:
 184                 otx2_err("Unknown Error.");
 185         }
 186 }
 187
 188 static int
 189 otx2_tim_ring_create(struct rte_event_timer_adapter *adptr)
 190 {
 191         struct rte_event_timer_adapter_conf *rcfg = &adptr->data->conf;
 192         struct otx2_tim_evdev *dev = tim_priv_get();
 193         struct otx2_tim_ring *tim_ring;
 194         struct tim_config_req *cfg_req;
 195         struct tim_ring_req *free_req;
 196         struct tim_lf_alloc_req *req;
 197         struct tim_lf_alloc_rsp *rsp;
 198         uint64_t nb_timers;
 199         int rc;
 200
 201         if (dev == NULL)
 202                 return -ENODEV;
 203
 204         if (adptr->data->id >= dev->nb_rings)
 205                 return -ENODEV;
 206
 207         req = otx2_mbox_alloc_msg_tim_lf_alloc(dev->mbox);
 208         req->npa_pf_func = otx2_npa_pf_func_get();
 209         req->sso_pf_func = otx2_sso_pf_func_get();
 210         req->ring = adptr->data->id;
 211
 212         rc = otx2_mbox_process_msg(dev->mbox, (void **)&rsp);
 213         if (rc < 0) {
 214                 tim_err_desc(rc);
 215                 return -ENODEV;
 216         }
 217
 218         if (NSEC2TICK(RTE_ALIGN_MUL_CEIL(rcfg->timer_tick_ns, 10),
 219                       rsp->tenns_clk) < OTX2_TIM_MIN_TMO_TKS) {
 220                 if (rcfg->flags & RTE_EVENT_TIMER_ADAPTER_F_ADJUST_RES)
 221                         rcfg->timer_tick_ns = TICK2NSEC(OTX2_TIM_MIN_TMO_TKS,
 222                                         rsp->tenns_clk);
 223                 else {
 224                         rc = -ERANGE;
 225                         goto rng_mem_err;
 226                 }
 227         }
 228
 229         tim_ring = rte_zmalloc("otx2_tim_prv", sizeof(struct otx2_tim_ring), 0);
 230         if (tim_ring == NULL) {
 231                 rc =  -ENOMEM;
 232                 goto rng_mem_err;
 233         }
 234
 235         adptr->data->adapter_priv = tim_ring;
 236
 237         tim_ring->tenns_clk_freq = rsp->tenns_clk;
 238         tim_ring->clk_src = (int)rcfg->clk_src;
 239         tim_ring->ring_id = adptr->data->id;
 240         tim_ring->tck_nsec = RTE_ALIGN_MUL_CEIL(rcfg->timer_tick_ns, 10);
 241         tim_ring->max_tout = rcfg->max_tmo_ns;
 242         tim_ring->nb_bkts = (tim_ring->max_tout / tim_ring->tck_nsec);
 243         tim_ring->chunk_sz = dev->chunk_sz;
 244         nb_timers = rcfg->nb_timers;
 245         tim_ring->disable_npa = dev->disable_npa;
 246
 247         tim_ring->nb_chunks = nb_timers / OTX2_TIM_NB_CHUNK_SLOTS(
 248                                                         tim_ring->chunk_sz);
 249         tim_ring->nb_chunk_slots = OTX2_TIM_NB_CHUNK_SLOTS(tim_ring->chunk_sz);
 250
 251         /* Try to optimize the bucket parameters. */
 252         if ((rcfg->flags & RTE_EVENT_TIMER_ADAPTER_F_ADJUST_RES)) {
 253                 if (rte_is_power_of_2(tim_ring->nb_bkts))
 254                         tim_ring->optimized = true;
 255                 else
 256                         tim_optimze_bkt_param(tim_ring);
 257         }
 258
 259         tim_ring->nb_chunks = tim_ring->nb_chunks * tim_ring->nb_bkts;
 260         /* Create buckets. */
 261         tim_ring->bkt = rte_zmalloc("otx2_tim_bucket", (tim_ring->nb_bkts) *
 262                                     sizeof(struct otx2_tim_bkt),
 263                                     RTE_CACHE_LINE_SIZE);
 264         if (tim_ring->bkt == NULL)
 265                 goto bkt_mem_err;
 266
 267         rc = tim_chnk_pool_create(tim_ring, rcfg);
 268         if (rc < 0)
 269                 goto chnk_mem_err;
 270
 271         cfg_req = otx2_mbox_alloc_msg_tim_config_ring(dev->mbox);
 272
 273         cfg_req->ring = tim_ring->ring_id;
 274         cfg_req->bigendian = false;
 275         cfg_req->clocksource = tim_ring->clk_src;
 276         cfg_req->enableperiodic = false;
 277         cfg_req->enabledontfreebuffer = tim_ring->ena_dfb;
 278         cfg_req->bucketsize = tim_ring->nb_bkts;
 279         cfg_req->chunksize = tim_ring->chunk_sz;
 280         cfg_req->interval = NSEC2TICK(tim_ring->tck_nsec,
 281                                       tim_ring->tenns_clk_freq);
 282
 283         rc = otx2_mbox_process(dev->mbox);
 284         if (rc < 0) {
 285                 tim_err_desc(rc);
 286                 goto chnk_mem_err;
 287         }
 288
 289         tim_ring->base = dev->bar2 +
 290                 (RVU_BLOCK_ADDR_TIM << 20 | tim_ring->ring_id << 12);
 291
 292         otx2_write64((uint64_t)tim_ring->bkt,
 293                      tim_ring->base + TIM_LF_RING_BASE);
 294         otx2_write64(tim_ring->aura, tim_ring->base + TIM_LF_RING_AURA);
 295
 296         return rc;
 297
 298 chnk_mem_err:
 299         rte_free(tim_ring->bkt);
 300 bkt_mem_err:
 301         rte_free(tim_ring);
 302 rng_mem_err:
 303         free_req = otx2_mbox_alloc_msg_tim_lf_free(dev->mbox);
 304         free_req->ring = adptr->data->id;
 305         otx2_mbox_process(dev->mbox);
 306         return rc;
 307 }
 308
 309 static int
 310 otx2_tim_ring_free(struct rte_event_timer_adapter *adptr)
 311 {
 312         struct otx2_tim_ring *tim_ring = adptr->data->adapter_priv;
 313         struct otx2_tim_evdev *dev = tim_priv_get();
 314         struct tim_ring_req *req;
 315         int rc;
 316
 317         if (dev == NULL)
 318                 return -ENODEV;
 319
 320         req = otx2_mbox_alloc_msg_tim_lf_free(dev->mbox);
 321         req->ring = tim_ring->ring_id;
 322
 323         rc = otx2_mbox_process(dev->mbox);
 324         if (rc < 0) {
 325                 tim_err_desc(rc);
 326                 return -EBUSY;
 327         }
 328
 329         rte_free(tim_ring->bkt);
 330         rte_mempool_free(tim_ring->chunk_pool);
 331         rte_free(adptr->data->adapter_priv);
 332
 333         return 0;
 334 }
 335
 336 int
 337 otx2_tim_caps_get(const struct rte_eventdev *evdev, uint64_t flags,
 338                   uint32_t *caps,
 339                   const struct rte_event_timer_adapter_ops **ops)
 340 {
 341         struct otx2_tim_evdev *dev = tim_priv_get();
 342
 343         RTE_SET_USED(flags);
 344         if (dev == NULL)
 345                 return -ENODEV;
 346
 347         otx2_tim_ops.init = otx2_tim_ring_create;
 348         otx2_tim_ops.uninit = otx2_tim_ring_free;
 349
 350         /* Store evdev pointer for later use. */
 351         dev->event_dev = (struct rte_eventdev *)(uintptr_t)evdev;
 352         *caps = RTE_EVENT_TIMER_ADAPTER_CAP_INTERNAL_PORT;
 353         *ops = &otx2_tim_ops;
 354
 355         return 0;
 356 }
 357
 358 #define OTX2_TIM_DISABLE_NPA    "tim_disable_npa"
 359 #define OTX2_TIM_CHNK_SLOTS     "tim_chnk_slots"
 360
 361 static void
 362 tim_parse_devargs(struct rte_devargs *devargs, struct otx2_tim_evdev *dev)
 363 {
 364         struct rte_kvargs *kvlist;
 365
 366         if (devargs == NULL)
 367                 return;
 368
 369         kvlist = rte_kvargs_parse(devargs->args, NULL);
 370         if (kvlist == NULL)
 371                 return;
 372
 373         rte_kvargs_process(kvlist, OTX2_TIM_DISABLE_NPA,
 374                            &parse_kvargs_flag, &dev->disable_npa);
 375         rte_kvargs_process(kvlist, OTX2_TIM_CHNK_SLOTS,
 376                            &parse_kvargs_value, &dev->chunk_slots);
 377 }
 378
 379 void
 380 otx2_tim_init(struct rte_pci_device *pci_dev, struct otx2_dev *cmn_dev)
 381 {
 382         struct rsrc_attach_req *atch_req;
 383         struct free_rsrcs_rsp *rsrc_cnt;
 384         const struct rte_memzone *mz;
 385         struct otx2_tim_evdev *dev;
 386         int rc;
 387
 388         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
 389                 return;
 390
 391         mz = rte_memzone_reserve(RTE_STR(OTX2_TIM_EVDEV_NAME),
 392                                  sizeof(struct otx2_tim_evdev),
 393                                  rte_socket_id(), 0);
 394         if (mz == NULL) {
 395                 otx2_tim_dbg("Unable to allocate memory for TIM Event device");
 396                 return;
 397         }
 398
 399         dev = mz->addr;
 400         dev->pci_dev = pci_dev;
 401         dev->mbox = cmn_dev->mbox;
 402         dev->bar2 = cmn_dev->bar2;
 403
 404         tim_parse_devargs(pci_dev->device.devargs, dev);
 405
 406         otx2_mbox_alloc_msg_free_rsrc_cnt(dev->mbox);
 407         rc = otx2_mbox_process_msg(dev->mbox, (void *)&rsrc_cnt);
 408         if (rc < 0) {
 409                 otx2_err("Unable to get free rsrc count.");
 410                 goto mz_free;
 411         }
 412
 413         dev->nb_rings = rsrc_cnt->tim;
 414
 415         if (!dev->nb_rings) {
 416                 otx2_tim_dbg("No TIM Logical functions provisioned.");
 417                 goto mz_free;
 418         }
 419
 420         atch_req = otx2_mbox_alloc_msg_attach_resources(dev->mbox);
 421         atch_req->modify = true;
 422         atch_req->timlfs = dev->nb_rings;
 423
 424         rc = otx2_mbox_process(dev->mbox);
 425         if (rc < 0) {
 426                 otx2_err("Unable to attach TIM rings.");
 427                 goto mz_free;
 428         }
 429
 430         if (dev->chunk_slots &&
 431             dev->chunk_slots <= OTX2_TIM_MAX_CHUNK_SLOTS &&
 432             dev->chunk_slots >= OTX2_TIM_MIN_CHUNK_SLOTS) {
 433                 dev->chunk_sz = (dev->chunk_slots + 1) *
 434                         OTX2_TIM_CHUNK_ALIGNMENT;
 435         } else {
 436                 dev->chunk_sz = OTX2_TIM_RING_DEF_CHUNK_SZ;
 437         }
 438
 439         return;
 440
 441 mz_free:
 442         rte_memzone_free(mz);
 443 }
 444
 445 void
 446 otx2_tim_fini(void)
 447 {
 448         struct otx2_tim_evdev *dev = tim_priv_get();
 449         struct rsrc_detach_req *dtch_req;
 450
 451         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
 452                 return;
 453
 454         dtch_req = otx2_mbox_alloc_msg_detach_resources(dev->mbox);
 455         dtch_req->partial = true;
 456         dtch_req->timlfs = true;
 457
 458         otx2_mbox_process(dev->mbox);
 459         rte_memzone_free(rte_memzone_lookup(RTE_STR(OTX2_TIM_EVDEV_NAME)));
 460 }