drivers/mempool/octeontx2/otx2_mempool_debug.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(C) 2019 Marvell International Ltd.
   3  */
   4
   5 #include "otx2_mempool.h"
   6
   7 #define npa_dump(fmt, ...) fprintf(stderr, fmt "\n", ##__VA_ARGS__)
   8
   9 static inline void
  10 npa_lf_pool_dump(struct npa_pool_s *pool)
  11 {
  12         npa_dump("W0: Stack base\t\t0x%"PRIx64"", pool->stack_base);
  13         npa_dump("W1: ena \t\t%d\nW1: nat_align \t\t%d\nW1: stack_caching \t%d",
  14                 pool->ena, pool->nat_align, pool->stack_caching);
  15         npa_dump("W1: stack_way_mask\t%d\nW1: buf_offset\t\t%d",
  16                 pool->stack_way_mask, pool->buf_offset);
  17         npa_dump("W1: buf_size \t\t%d", pool->buf_size);
  18
  19         npa_dump("W2: stack_max_pages \t%d\nW2: stack_pages\t\t%d",
  20                 pool->stack_max_pages, pool->stack_pages);
  21
  22         npa_dump("W3: op_pc \t\t0x%"PRIx64"", (uint64_t)pool->op_pc);
  23
  24         npa_dump("W4: stack_offset\t%d\nW4: shift\t\t%d\nW4: avg_level\t\t%d",
  25                 pool->stack_offset, pool->shift, pool->avg_level);
  26         npa_dump("W4: avg_con \t\t%d\nW4: fc_ena\t\t%d\nW4: fc_stype\t\t%d",
  27                 pool->avg_con, pool->fc_ena, pool->fc_stype);
  28         npa_dump("W4: fc_hyst_bits\t%d\nW4: fc_up_crossing\t%d",
  29                 pool->fc_hyst_bits, pool->fc_up_crossing);
  30         npa_dump("W4: update_time\t\t%d\n", pool->update_time);
  31
  32         npa_dump("W5: fc_addr\t\t0x%"PRIx64"\n", pool->fc_addr);
  33
  34         npa_dump("W6: ptr_start\t\t0x%"PRIx64"\n", pool->ptr_start);
  35
  36         npa_dump("W7: ptr_end\t\t0x%"PRIx64"\n", pool->ptr_end);
  37         npa_dump("W8: err_int\t\t%d\nW8: err_int_ena\t\t%d",
  38                 pool->err_int, pool->err_int_ena);
  39         npa_dump("W8: thresh_int\t\t%d", pool->thresh_int);
  40
  41         npa_dump("W8: thresh_int_ena\t%d\nW8: thresh_up\t\t%d",
  42                 pool->thresh_int_ena, pool->thresh_up);
  43         npa_dump("W8: thresh_qint_idx\t%d\nW8: err_qint_idx\t%d",
  44                 pool->thresh_qint_idx, pool->err_qint_idx);
  45 }
  46
  47 static inline void
  48 npa_lf_aura_dump(struct npa_aura_s *aura)
  49 {
  50         npa_dump("W0: Pool addr\t\t0x%"PRIx64"\n", aura->pool_addr);
  51
  52         npa_dump("W1: ena\t\t\t%d\nW1: pool caching\t%d\nW1: pool way mask\t%d",
  53                 aura->ena, aura->pool_caching, aura->pool_way_mask);
  54         npa_dump("W1: avg con\t\t%d\nW1: pool drop ena\t%d",
  55                 aura->avg_con, aura->pool_drop_ena);
  56         npa_dump("W1: aura drop ena\t%d", aura->aura_drop_ena);
  57         npa_dump("W1: bp_ena\t\t%d\nW1: aura drop\t\t%d\nW1: aura shift\t\t%d",
  58                 aura->bp_ena, aura->aura_drop, aura->shift);
  59         npa_dump("W1: avg_level\t\t%d\n", aura->avg_level);
  60
  61         npa_dump("W2: count\t\t%"PRIx64"\nW2: nix0_bpid\t\t%d",
  62                 (uint64_t)aura->count, aura->nix0_bpid);
  63         npa_dump("W2: nix1_bpid\t\t%d", aura->nix1_bpid);
  64
  65         npa_dump("W3: limit\t\t%"PRIx64"\nW3: bp\t\t\t%d\nW3: fc_ena\t\t%d\n",
  66                 (uint64_t)aura->limit, aura->bp, aura->fc_ena);
  67         npa_dump("W3: fc_up_crossing\t%d\nW3: fc_stype\t\t%d",
  68                 aura->fc_up_crossing, aura->fc_stype);
  69
  70         npa_dump("W3: fc_hyst_bits\t%d", aura->fc_hyst_bits);
  71
  72         npa_dump("W4: fc_addr\t\t0x%"PRIx64"\n", aura->fc_addr);
  73
  74         npa_dump("W5: pool_drop\t\t%d\nW5: update_time\t\t%d",
  75                 aura->pool_drop, aura->update_time);
  76         npa_dump("W5: err_int\t\t%d",  aura->err_int);
  77         npa_dump("W5: err_int_ena\t\t%d\nW5: thresh_int\t\t%d",
  78                 aura->err_int_ena, aura->thresh_int);
  79         npa_dump("W5: thresh_int_ena\t%d", aura->thresh_int_ena);
  80
  81         npa_dump("W5: thresh_up\t\t%d\nW5: thresh_qint_idx\t%d",
  82                 aura->thresh_up, aura->thresh_qint_idx);
  83         npa_dump("W5: err_qint_idx\t%d", aura->err_qint_idx);
  84
  85         npa_dump("W6: thresh\t\t%"PRIx64"\n", (uint64_t)aura->thresh);
  86 }
  87
  88 int
  89 otx2_mempool_ctx_dump(struct otx2_npa_lf *lf)
  90 {
  91         struct npa_aq_enq_req *aq;
  92         struct npa_aq_enq_rsp *rsp;
  93         uint32_t q;
  94         int rc;
  95
  96         for (q = 0; q < lf->nr_pools; q++) {
  97                 /* Skip disabled POOL */
  98                 if (rte_bitmap_get(lf->npa_bmp, q))
  99                         continue;
 100
 101                 aq = otx2_mbox_alloc_msg_npa_aq_enq(lf->mbox);
 102                 aq->aura_id = q;
 103                 aq->ctype = NPA_AQ_CTYPE_POOL;
 104                 aq->op = NPA_AQ_INSTOP_READ;
 105
 106                 rc = otx2_mbox_process_msg(lf->mbox, (void *)&rsp);
 107                 if (rc) {
 108                         otx2_err("Failed to get pool(%d) context", q);
 109                         return rc;
 110                 }
 111                 npa_dump("============== pool=%d ===============\n", q);
 112                 npa_lf_pool_dump(&rsp->pool);
 113         }
 114
 115         for (q = 0; q < lf->nr_pools; q++) {
 116                 /* Skip disabled AURA */
 117                 if (rte_bitmap_get(lf->npa_bmp, q))
 118                         continue;
 119
 120                 aq = otx2_mbox_alloc_msg_npa_aq_enq(lf->mbox);
 121                 aq->aura_id = q;
 122                 aq->ctype = NPA_AQ_CTYPE_AURA;
 123                 aq->op = NPA_AQ_INSTOP_READ;
 124
 125                 rc = otx2_mbox_process_msg(lf->mbox, (void *)&rsp);
 126                 if (rc) {
 127                         otx2_err("Failed to get aura(%d) context", q);
 128                         return rc;
 129                 }
 130                 npa_dump("============== aura=%d ===============\n", q);
 131                 npa_lf_aura_dump(&rsp->aura);
 132         }
 133
 134         return rc;
 135 }