1 // SPDX-License-Identifier: (BSD-3-Clause OR GPL-2.0)
2 /* Copyright (C) 2014-2017 aQuantia Corporation. */
4 /* File hw_atl_utils_fw2x.c: Definition of firmware 2.x functions for
5 * Atlantic hardware abstraction layer.
9 #include "../atl_hw_regs.h"
11 #include "../atl_types.h"
12 #include "hw_atl_utils.h"
13 #include "hw_atl_llh.h"
15 #define HW_ATL_FW2X_MPI_EFUSE_ADDR 0x364
16 #define HW_ATL_FW2X_MPI_MBOX_ADDR 0x360
17 #define HW_ATL_FW2X_MPI_RPC_ADDR 0x334
19 #define HW_ATL_FW2X_MPI_CONTROL_ADDR 0x368
20 #define HW_ATL_FW2X_MPI_CONTROL2_ADDR 0x36C
21 #define HW_ATL_FW2X_MPI_LED_ADDR 0x31c
23 #define HW_ATL_FW2X_MPI_STATE_ADDR 0x370
24 #define HW_ATL_FW2X_MPI_STATE2_ADDR 0x374
26 #define HW_ATL_FW2X_CAP_SLEEP_PROXY BIT(CAPS_HI_SLEEP_PROXY)
27 #define HW_ATL_FW2X_CAP_WOL BIT(CAPS_HI_WOL)
29 #define HW_ATL_FW2X_CAP_EEE_1G_MASK BIT(CAPS_HI_1000BASET_FD_EEE)
30 #define HW_ATL_FW2X_CAP_EEE_2G5_MASK BIT(CAPS_HI_2P5GBASET_FD_EEE)
31 #define HW_ATL_FW2X_CAP_EEE_5G_MASK BIT(CAPS_HI_5GBASET_FD_EEE)
32 #define HW_ATL_FW2X_CAP_EEE_10G_MASK BIT(CAPS_HI_10GBASET_FD_EEE)
34 #define HAL_ATLANTIC_WOL_FILTERS_COUNT 8
35 #define HAL_ATLANTIC_UTILS_FW2X_MSG_WOL 0x0E
37 #define HW_ATL_FW_FEATURE_EEPROM 0x03010025
38 #define HW_ATL_FW_FEATURE_LED 0x03010026
40 struct fw2x_msg_wol_pattern {
43 } __attribute__((__packed__));
48 u8 magic_packet_enabled;
50 struct fw2x_msg_wol_pattern filter[HAL_ATLANTIC_WOL_FILTERS_COUNT];
55 u32 link_down_timeout;
56 } __attribute__((__packed__));
58 static int aq_fw2x_set_link_speed(struct aq_hw_s *self, u32 speed);
59 static int aq_fw2x_set_state(struct aq_hw_s *self,
60 enum hal_atl_utils_fw_state_e state);
62 static int aq_fw2x_init(struct aq_hw_s *self)
65 struct hw_aq_atl_utils_mbox mbox;
67 /* check 10 times by 1ms */
68 AQ_HW_WAIT_FOR(0U != (self->mbox_addr =
69 aq_hw_read_reg(self, HW_ATL_FW2X_MPI_MBOX_ADDR)),
71 AQ_HW_WAIT_FOR(0U != (self->rpc_addr =
72 aq_hw_read_reg(self, HW_ATL_FW2X_MPI_RPC_ADDR)),
76 hw_atl_utils_mpi_read_stats(self, &mbox);
78 self->caps_lo = mbox.info.caps_lo;
83 static int aq_fw2x_deinit(struct aq_hw_s *self)
85 int err = aq_fw2x_set_link_speed(self, 0);
88 err = aq_fw2x_set_state(self, MPI_DEINIT);
93 static enum hw_atl_fw2x_rate link_speed_mask_2fw2x_ratemask(u32 speed)
95 enum hw_atl_fw2x_rate rate = 0;
97 if (speed & AQ_NIC_RATE_10G)
98 rate |= FW2X_RATE_10G;
100 if (speed & AQ_NIC_RATE_5G)
101 rate |= FW2X_RATE_5G;
103 if (speed & AQ_NIC_RATE_5G5R)
104 rate |= FW2X_RATE_5G;
106 if (speed & AQ_NIC_RATE_2G5)
107 rate |= FW2X_RATE_2G5;
109 if (speed & AQ_NIC_RATE_1G)
110 rate |= FW2X_RATE_1G;
112 if (speed & AQ_NIC_RATE_100M)
113 rate |= FW2X_RATE_100M;
118 static u32 fw2x_to_eee_mask(u32 speed)
122 if (speed & HW_ATL_FW2X_CAP_EEE_10G_MASK)
123 rate |= AQ_NIC_RATE_EEE_10G;
125 if (speed & HW_ATL_FW2X_CAP_EEE_5G_MASK)
126 rate |= AQ_NIC_RATE_EEE_5G;
128 if (speed & HW_ATL_FW2X_CAP_EEE_2G5_MASK)
129 rate |= AQ_NIC_RATE_EEE_2G5;
131 if (speed & HW_ATL_FW2X_CAP_EEE_1G_MASK)
132 rate |= AQ_NIC_RATE_EEE_1G;
137 static int aq_fw2x_set_link_speed(struct aq_hw_s *self, u32 speed)
139 u32 rate_mask = link_speed_mask_2fw2x_ratemask(speed);
140 u32 reg_val = aq_hw_read_reg(self, HW_ATL_FW2X_MPI_CONTROL_ADDR);
141 u32 val = rate_mask | ((BIT(CAPS_LO_SMBUS_READ) |
142 BIT(CAPS_LO_SMBUS_WRITE) |
143 BIT(CAPS_LO_MACSEC)) & reg_val);
145 aq_hw_write_reg(self, HW_ATL_FW2X_MPI_CONTROL_ADDR, val);
150 static void aq_fw2x_set_mpi_flow_control(struct aq_hw_s *self, u32 *mpi_state)
152 if (self->aq_nic_cfg->flow_control & AQ_NIC_FC_RX)
153 *mpi_state |= BIT(CAPS_HI_PAUSE);
155 *mpi_state &= ~BIT(CAPS_HI_PAUSE);
157 if (self->aq_nic_cfg->flow_control & AQ_NIC_FC_TX)
158 *mpi_state |= BIT(CAPS_HI_ASYMMETRIC_PAUSE);
160 *mpi_state &= ~BIT(CAPS_HI_ASYMMETRIC_PAUSE);
163 static int aq_fw2x_set_state(struct aq_hw_s *self,
164 enum hal_atl_utils_fw_state_e state)
166 u32 mpi_state = aq_hw_read_reg(self, HW_ATL_FW2X_MPI_CONTROL2_ADDR);
170 mpi_state &= ~BIT(CAPS_HI_LINK_DROP);
171 aq_fw2x_set_mpi_flow_control(self, &mpi_state);
174 mpi_state |= BIT(CAPS_HI_LINK_DROP);
181 aq_hw_write_reg(self, HW_ATL_FW2X_MPI_CONTROL2_ADDR, mpi_state);
185 static int aq_fw2x_update_link_status(struct aq_hw_s *self)
187 u32 mpi_state = aq_hw_read_reg(self, HW_ATL_FW2X_MPI_STATE_ADDR);
188 u32 speed = mpi_state & (FW2X_RATE_100M | FW2X_RATE_1G |
189 FW2X_RATE_2G5 | FW2X_RATE_5G | FW2X_RATE_10G);
190 struct aq_hw_link_status_s *link_status = &self->aq_link_status;
193 if (speed & FW2X_RATE_10G)
194 link_status->mbps = 10000;
195 else if (speed & FW2X_RATE_5G)
196 link_status->mbps = 5000;
197 else if (speed & FW2X_RATE_2G5)
198 link_status->mbps = 2500;
199 else if (speed & FW2X_RATE_1G)
200 link_status->mbps = 1000;
201 else if (speed & FW2X_RATE_100M)
202 link_status->mbps = 100;
204 link_status->mbps = 10000;
206 link_status->mbps = 0;
213 int aq_fw2x_get_mac_permanent(struct aq_hw_s *self, u8 *mac)
218 u32 mac_addr[2] = { 0 };
219 u32 efuse_addr = aq_hw_read_reg(self, HW_ATL_FW2X_MPI_EFUSE_ADDR);
221 if (efuse_addr != 0) {
222 err = hw_atl_utils_fw_downld_dwords(self,
223 efuse_addr + (40U * 4U),
225 ARRAY_SIZE(mac_addr));
228 mac_addr[0] = rte_constant_bswap32(mac_addr[0]);
229 mac_addr[1] = rte_constant_bswap32(mac_addr[1]);
232 ether_addr_copy((struct ether_addr *)mac_addr,
233 (struct ether_addr *)mac);
235 if ((mac[0] & 0x01U) || ((mac[0] | mac[1] | mac[2]) == 0x00U)) {
236 unsigned int rnd = (uint32_t)rte_rand();
238 //get_random_bytes(&rnd, sizeof(unsigned int));
245 mac[5] = (u8)(0xFFU & l);
247 mac[4] = (u8)(0xFFU & l);
249 mac[3] = (u8)(0xFFU & l);
251 mac[2] = (u8)(0xFFU & l);
252 mac[1] = (u8)(0xFFU & h);
254 mac[0] = (u8)(0xFFU & h);
259 static int aq_fw2x_update_stats(struct aq_hw_s *self)
262 u32 mpi_opts = aq_hw_read_reg(self, HW_ATL_FW2X_MPI_CONTROL2_ADDR);
263 u32 orig_stats_val = mpi_opts & BIT(CAPS_HI_STATISTICS);
265 /* Toggle statistics bit for FW to update */
266 mpi_opts = mpi_opts ^ BIT(CAPS_HI_STATISTICS);
267 aq_hw_write_reg(self, HW_ATL_FW2X_MPI_CONTROL2_ADDR, mpi_opts);
269 /* Wait FW to report back */
270 AQ_HW_WAIT_FOR(orig_stats_val !=
271 (aq_hw_read_reg(self, HW_ATL_FW2X_MPI_STATE2_ADDR) &
272 BIT(CAPS_HI_STATISTICS)),
277 return hw_atl_utils_update_stats(self);
280 static int aq_fw2x_get_temp(struct aq_hw_s *self, int *temp)
283 u32 mpi_opts = aq_hw_read_reg(self, HW_ATL_FW2X_MPI_CONTROL2_ADDR);
284 u32 temp_val = mpi_opts & BIT(CAPS_HI_TEMPERATURE);
287 /* Toggle statistics bit for FW to 0x36C.18 (CAPS_HI_TEMPERATURE) */
288 mpi_opts = mpi_opts ^ BIT(CAPS_HI_TEMPERATURE);
289 aq_hw_write_reg(self, HW_ATL_FW2X_MPI_CONTROL2_ADDR, mpi_opts);
291 /* Wait FW to report back */
292 AQ_HW_WAIT_FOR(temp_val !=
293 (aq_hw_read_reg(self, HW_ATL_FW2X_MPI_STATE2_ADDR) &
294 BIT(CAPS_HI_TEMPERATURE)), 1U, 10000U);
295 err = hw_atl_utils_fw_downld_dwords(self,
297 offsetof(struct hw_aq_atl_utils_mbox, info) +
298 offsetof(struct hw_aq_info, phy_temperature),
300 sizeof(temp_res) / sizeof(u32));
305 *temp = temp_res * 100 / 256;
309 static int aq_fw2x_get_cable_len(struct aq_hw_s *self, int *cable_len)
314 err = hw_atl_utils_fw_downld_dwords(self,
316 offsetof(struct hw_aq_atl_utils_mbox, info) +
317 offsetof(struct hw_aq_info, phy_temperature),
319 sizeof(cable_len_res) / sizeof(u32));
324 *cable_len = (cable_len_res >> 16) & 0xFF;
332 static int aq_fw2x_set_sleep_proxy(struct aq_hw_s *self, u8 *mac)
335 struct hw_aq_atl_utils_fw_rpc *rpc = NULL;
336 struct offload_info *cfg = NULL;
337 unsigned int rpc_size = 0U;
340 rpc_size = sizeof(rpc->msg_id) + sizeof(*cfg);
342 err = hw_atl_utils_fw_rpc_wait(self, &rpc);
346 memset(rpc, 0, rpc_size);
347 cfg = (struct offload_info *)(&rpc->msg_id + 1);
349 memcpy(cfg->mac_addr, mac, ETH_ALEN);
350 cfg->len = sizeof(*cfg);
352 /* Clear bit 0x36C.23 */
353 mpi_opts = aq_hw_read_reg(self, HW_ATL_FW2X_MPI_CONTROL2_ADDR);
354 mpi_opts &= ~HW_ATL_FW2X_CAP_SLEEP_PROXY;
356 aq_hw_write_reg(self, HW_ATL_FW2X_MPI_CONTROL2_ADDR, mpi_opts);
358 err = hw_atl_utils_fw_rpc_call(self, rpc_size);
362 /* Set bit 0x36C.23 */
363 mpi_opts |= HW_ATL_FW2X_CAP_SLEEP_PROXY;
364 aq_hw_write_reg(self, HW_ATL_FW2X_MPI_CONTROL2_ADDR, mpi_opts);
366 AQ_HW_WAIT_FOR((aq_hw_read_reg(self, HW_ATL_FW2X_MPI_STATE2_ADDR) &
367 HW_ATL_FW2X_CAP_SLEEP_PROXY), 1U, 10000U);
372 static int aq_fw2x_set_wol_params(struct aq_hw_s *self, u8 *mac)
375 struct fw2x_msg_wol *msg = NULL;
378 struct hw_aq_atl_utils_fw_rpc *rpc = NULL;
380 err = hw_atl_utils_fw_rpc_wait(self, &rpc);
384 msg = (struct fw2x_msg_wol *)rpc;
386 msg->msg_id = HAL_ATLANTIC_UTILS_FW2X_MSG_WOL;
387 msg->magic_packet_enabled = true;
388 memcpy(msg->hw_addr, mac, ETH_ALEN);
390 mpi_opts = aq_hw_read_reg(self, HW_ATL_FW2X_MPI_CONTROL2_ADDR);
391 mpi_opts &= ~(HW_ATL_FW2X_CAP_SLEEP_PROXY | HW_ATL_FW2X_CAP_WOL);
393 aq_hw_write_reg(self, HW_ATL_FW2X_MPI_CONTROL2_ADDR, mpi_opts);
395 err = hw_atl_utils_fw_rpc_call(self, sizeof(*msg));
399 /* Set bit 0x36C.24 */
400 mpi_opts |= HW_ATL_FW2X_CAP_WOL;
401 aq_hw_write_reg(self, HW_ATL_FW2X_MPI_CONTROL2_ADDR, mpi_opts);
403 AQ_HW_WAIT_FOR((aq_hw_read_reg(self, HW_ATL_FW2X_MPI_STATE2_ADDR) &
404 HW_ATL_FW2X_CAP_WOL), 1U, 10000U);
409 static int aq_fw2x_set_power(struct aq_hw_s *self,
410 unsigned int power_state __rte_unused,
415 if (self->aq_nic_cfg->wol & AQ_NIC_WOL_ENABLED) {
416 err = aq_fw2x_set_sleep_proxy(self, mac);
419 err = aq_fw2x_set_wol_params(self, mac);
427 static int aq_fw2x_set_eee_rate(struct aq_hw_s *self, u32 speed)
429 u32 mpi_opts = aq_hw_read_reg(self, HW_ATL_FW2X_MPI_CONTROL2_ADDR);
430 mpi_opts &= ~(HW_ATL_FW2X_CAP_EEE_1G_MASK |
431 HW_ATL_FW2X_CAP_EEE_2G5_MASK | HW_ATL_FW2X_CAP_EEE_5G_MASK |
432 HW_ATL_FW2X_CAP_EEE_10G_MASK);
434 if (speed & AQ_NIC_RATE_EEE_10G)
435 mpi_opts |= HW_ATL_FW2X_CAP_EEE_10G_MASK;
437 if (speed & AQ_NIC_RATE_EEE_5G)
438 mpi_opts |= HW_ATL_FW2X_CAP_EEE_5G_MASK;
440 if (speed & AQ_NIC_RATE_EEE_2G5)
441 mpi_opts |= HW_ATL_FW2X_CAP_EEE_2G5_MASK;
443 if (speed & AQ_NIC_RATE_EEE_1G)
444 mpi_opts |= HW_ATL_FW2X_CAP_EEE_1G_MASK;
446 aq_hw_write_reg(self, HW_ATL_FW2X_MPI_CONTROL2_ADDR, mpi_opts);
451 static int aq_fw2x_get_eee_rate(struct aq_hw_s *self, u32 *rate,
452 u32 *supported_rates)
458 err = hw_atl_utils_fw_downld_dwords(self,
460 offsetof(struct hw_aq_atl_utils_mbox, info) +
461 offsetof(struct hw_aq_info, caps_hi),
463 sizeof(caps_hi) / sizeof(u32));
468 *supported_rates = fw2x_to_eee_mask(caps_hi);
470 mpi_state = aq_hw_read_reg(self, HW_ATL_FW2X_MPI_STATE2_ADDR);
471 *rate = fw2x_to_eee_mask(mpi_state);
476 static int aq_fw2x_get_flow_control(struct aq_hw_s *self, u32 *fc)
478 u32 mpi_state = aq_hw_read_reg(self, HW_ATL_FW2X_MPI_CONTROL2_ADDR);
480 *fc = ((mpi_state & BIT(CAPS_HI_PAUSE)) ? AQ_NIC_FC_RX : 0) |
481 ((mpi_state & BIT(CAPS_HI_ASYMMETRIC_PAUSE)) ? AQ_NIC_FC_TX : 0);
486 static int aq_fw2x_set_flow_control(struct aq_hw_s *self)
488 u32 mpi_state = aq_hw_read_reg(self, HW_ATL_FW2X_MPI_CONTROL2_ADDR);
490 aq_fw2x_set_mpi_flow_control(self, &mpi_state);
492 aq_hw_write_reg(self, HW_ATL_FW2X_MPI_CONTROL2_ADDR, mpi_state);
497 static int aq_fw2x_led_control(struct aq_hw_s *self, u32 mode)
499 if (self->fw_ver_actual < HW_ATL_FW_FEATURE_LED)
502 aq_hw_write_reg(self, HW_ATL_FW2X_MPI_LED_ADDR, mode);
506 static int aq_fw2x_get_eeprom(struct aq_hw_s *self, int dev_addr,
507 u32 *data, u32 len, u32 offset)
509 u32 bytes_remains = len % sizeof(u32);
510 u32 num_dwords = len / sizeof(u32);
511 struct smbus_request request;
516 if (self->fw_ver_actual < HW_ATL_FW_FEATURE_EEPROM)
520 request.device_id = dev_addr;
521 request.address = offset;
522 request.length = len;
524 /* Write SMBUS request to cfg memory */
525 err = hw_atl_utils_fw_upload_dwords(self, self->rpc_addr,
526 (u32 *)(void *)&request,
527 sizeof(request) / sizeof(u32));
532 /* Toggle 0x368.CAPS_LO_SMBUS_READ bit */
533 mpi_opts = aq_hw_read_reg(self, HW_ATL_FW2X_MPI_CONTROL_ADDR);
534 mpi_opts ^= BIT(CAPS_LO_SMBUS_READ);
536 aq_hw_write_reg(self, HW_ATL_FW2X_MPI_CONTROL_ADDR, mpi_opts);
538 /* Wait until REQUEST_BIT matched in 0x370 */
540 AQ_HW_WAIT_FOR((aq_hw_read_reg(self, HW_ATL_FW2X_MPI_STATE_ADDR) &
541 BIT(CAPS_LO_SMBUS_READ)) == (mpi_opts & BIT(CAPS_LO_SMBUS_READ)),
547 err = hw_atl_utils_fw_downld_dwords(self, self->rpc_addr + sizeof(u32),
549 sizeof(result) / sizeof(u32));
558 err = hw_atl_utils_fw_downld_dwords(self,
559 self->rpc_addr + sizeof(u32) * 2,
570 err = hw_atl_utils_fw_downld_dwords(self,
571 self->rpc_addr + (sizeof(u32) * 2) +
572 (num_dwords * sizeof(u32)),
579 rte_memcpy((u8 *)data + len - bytes_remains,
580 &val, bytes_remains);
587 static int aq_fw2x_set_eeprom(struct aq_hw_s *self, int dev_addr,
588 u32 *data, u32 len, u32 offset)
590 struct smbus_request request;
591 u32 mpi_opts, result = 0;
594 if (self->fw_ver_actual < HW_ATL_FW_FEATURE_EEPROM)
598 request.device_id = dev_addr;
599 request.address = offset;
600 request.length = len;
602 /* Write SMBUS request to cfg memory */
603 err = hw_atl_utils_fw_upload_dwords(self, self->rpc_addr,
604 (u32 *)(void *)&request,
605 sizeof(request) / sizeof(u32));
610 /* Write SMBUS data to cfg memory */
611 u32 num_dwords = len / sizeof(u32);
612 u32 bytes_remains = len % sizeof(u32);
615 err = hw_atl_utils_fw_upload_dwords(self,
616 self->rpc_addr + sizeof(request),
627 rte_memcpy(&val, (u8 *)data + (sizeof(u32) * num_dwords),
630 err = hw_atl_utils_fw_upload_dwords(self,
631 self->rpc_addr + sizeof(request) +
632 (num_dwords * sizeof(u32)),
640 /* Toggle 0x368.CAPS_LO_SMBUS_WRITE bit */
641 mpi_opts = aq_hw_read_reg(self, HW_ATL_FW2X_MPI_CONTROL_ADDR);
642 mpi_opts ^= BIT(CAPS_LO_SMBUS_WRITE);
644 aq_hw_write_reg(self, HW_ATL_FW2X_MPI_CONTROL_ADDR, mpi_opts);
646 /* Wait until REQUEST_BIT matched in 0x370 */
647 AQ_HW_WAIT_FOR((aq_hw_read_reg(self, HW_ATL_FW2X_MPI_STATE_ADDR) &
648 BIT(CAPS_LO_SMBUS_WRITE)) == (mpi_opts & BIT(CAPS_LO_SMBUS_WRITE)),
654 /* Read status of write operation */
655 err = hw_atl_utils_fw_downld_dwords(self, self->rpc_addr + sizeof(u32),
657 sizeof(result) / sizeof(u32));
668 static int aq_fw2x_send_macsec_request(struct aq_hw_s *self,
669 struct macsec_msg_fw_request *req,
670 struct macsec_msg_fw_response *response)
675 if (!response || !response)
678 if ((self->caps_lo & BIT(CAPS_LO_MACSEC)) == 0)
681 /* Write macsec request to cfg memory */
682 err = hw_atl_utils_fw_upload_dwords(self, self->rpc_addr,
684 RTE_ALIGN(sizeof(*req) / sizeof(u32), sizeof(u32)));
689 /* Toggle 0x368.CAPS_LO_MACSEC bit */
690 mpi_opts = aq_hw_read_reg(self, HW_ATL_FW2X_MPI_CONTROL_ADDR);
691 mpi_opts ^= BIT(CAPS_LO_MACSEC);
693 aq_hw_write_reg(self, HW_ATL_FW2X_MPI_CONTROL_ADDR, mpi_opts);
695 /* Wait until REQUEST_BIT matched in 0x370 */
696 AQ_HW_WAIT_FOR((aq_hw_read_reg(self, HW_ATL_FW2X_MPI_STATE_ADDR) &
697 BIT(CAPS_LO_MACSEC)) == (mpi_opts & BIT(CAPS_LO_MACSEC)),
703 /* Read status of write operation */
704 err = hw_atl_utils_fw_downld_dwords(self, self->rpc_addr + sizeof(u32),
705 (u32 *)(void *)response,
706 RTE_ALIGN(sizeof(*response) / sizeof(u32), sizeof(u32)));
711 const struct aq_fw_ops aq_fw_2x_ops = {
712 .init = aq_fw2x_init,
713 .deinit = aq_fw2x_deinit,
715 .get_mac_permanent = aq_fw2x_get_mac_permanent,
716 .set_link_speed = aq_fw2x_set_link_speed,
717 .set_state = aq_fw2x_set_state,
718 .update_link_status = aq_fw2x_update_link_status,
719 .update_stats = aq_fw2x_update_stats,
720 .set_power = aq_fw2x_set_power,
721 .get_temp = aq_fw2x_get_temp,
722 .get_cable_len = aq_fw2x_get_cable_len,
723 .set_eee_rate = aq_fw2x_set_eee_rate,
724 .get_eee_rate = aq_fw2x_get_eee_rate,
725 .get_flow_control = aq_fw2x_get_flow_control,
726 .set_flow_control = aq_fw2x_set_flow_control,
727 .led_control = aq_fw2x_led_control,
728 .get_eeprom = aq_fw2x_get_eeprom,
729 .set_eeprom = aq_fw2x_set_eeprom,
730 .send_macsec_req = aq_fw2x_send_macsec_request,