drivers/net/axgbe/axgbe_ethdev.c

   1 /*   SPDX-License-Identifier: BSD-3-Clause
   2  *   Copyright(c) 2018 Advanced Micro Devices, Inc. All rights reserved.
   3  *   Copyright(c) 2018 Synopsys, Inc. All rights reserved.
   4  */
   5
   6 #include "axgbe_rxtx.h"
   7 #include "axgbe_ethdev.h"
   8 #include "axgbe_common.h"
   9 #include "axgbe_phy.h"
  10 #include "axgbe_regs.h"
  11 #include "rte_time.h"
  12
  13 static int eth_axgbe_dev_init(struct rte_eth_dev *eth_dev);
  14 static int eth_axgbe_dev_uninit(struct rte_eth_dev *eth_dev);
  15 static int  axgbe_dev_configure(struct rte_eth_dev *dev);
  16 static int  axgbe_dev_start(struct rte_eth_dev *dev);
  17 static void axgbe_dev_stop(struct rte_eth_dev *dev);
  18 static void axgbe_dev_interrupt_handler(void *param);
  19 static int axgbe_dev_close(struct rte_eth_dev *dev);
  20 static int axgbe_dev_promiscuous_enable(struct rte_eth_dev *dev);
  21 static int axgbe_dev_promiscuous_disable(struct rte_eth_dev *dev);
  22 static int axgbe_dev_allmulticast_enable(struct rte_eth_dev *dev);
  23 static int axgbe_dev_allmulticast_disable(struct rte_eth_dev *dev);
  24 static int axgbe_dev_mac_addr_set(struct rte_eth_dev *dev,
  25                                   struct rte_ether_addr *mac_addr);
  26 static int axgbe_dev_mac_addr_add(struct rte_eth_dev *dev,
  27                                   struct rte_ether_addr *mac_addr,
  28                                   uint32_t index,
  29                                   uint32_t vmdq);
  30 static void axgbe_dev_mac_addr_remove(struct rte_eth_dev *dev, uint32_t index);
  31 static int axgbe_dev_set_mc_addr_list(struct rte_eth_dev *dev,
  32                                       struct rte_ether_addr *mc_addr_set,
  33                                       uint32_t nb_mc_addr);
  34 static int axgbe_dev_uc_hash_table_set(struct rte_eth_dev *dev,
  35                                        struct rte_ether_addr *mac_addr,
  36                                        uint8_t add);
  37 static int axgbe_dev_uc_all_hash_table_set(struct rte_eth_dev *dev,
  38                                            uint8_t add);
  39 static int axgbe_dev_link_update(struct rte_eth_dev *dev,
  40                                  int wait_to_complete);
  41 static int axgbe_dev_get_regs(struct rte_eth_dev *dev,
  42                               struct rte_dev_reg_info *regs);
  43 static int axgbe_dev_stats_get(struct rte_eth_dev *dev,
  44                                 struct rte_eth_stats *stats);
  45 static int axgbe_dev_stats_reset(struct rte_eth_dev *dev);
  46 static int axgbe_dev_xstats_get(struct rte_eth_dev *dev,
  47                                 struct rte_eth_xstat *stats,
  48                                 unsigned int n);
  49 static int
  50 axgbe_dev_xstats_get_names(struct rte_eth_dev *dev,
  51                            struct rte_eth_xstat_name *xstats_names,
  52                            unsigned int size);
  53 static int
  54 axgbe_dev_xstats_get_by_id(struct rte_eth_dev *dev,
  55                            const uint64_t *ids,
  56                            uint64_t *values,
  57                            unsigned int n);
  58 static int
  59 axgbe_dev_xstats_get_names_by_id(struct rte_eth_dev *dev,
  60                                  struct rte_eth_xstat_name *xstats_names,
  61                                  const uint64_t *ids,
  62                                  unsigned int size);
  63 static int axgbe_dev_xstats_reset(struct rte_eth_dev *dev);
  64 static int axgbe_dev_rss_reta_update(struct rte_eth_dev *dev,
  65                           struct rte_eth_rss_reta_entry64 *reta_conf,
  66                           uint16_t reta_size);
  67 static int axgbe_dev_rss_reta_query(struct rte_eth_dev *dev,
  68                          struct rte_eth_rss_reta_entry64 *reta_conf,
  69                          uint16_t reta_size);
  70 static int axgbe_dev_rss_hash_update(struct rte_eth_dev *dev,
  71                                      struct rte_eth_rss_conf *rss_conf);
  72 static int axgbe_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
  73                                        struct rte_eth_rss_conf *rss_conf);
  74 static int  axgbe_dev_info_get(struct rte_eth_dev *dev,
  75                                struct rte_eth_dev_info *dev_info);
  76 static int axgbe_flow_ctrl_get(struct rte_eth_dev *dev,
  77                                 struct rte_eth_fc_conf *fc_conf);
  78 static int axgbe_flow_ctrl_set(struct rte_eth_dev *dev,
  79                                 struct rte_eth_fc_conf *fc_conf);
  80 static int axgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev,
  81                                 struct rte_eth_pfc_conf *pfc_conf);
  82 static void axgbe_rxq_info_get(struct rte_eth_dev *dev, uint16_t queue_id,
  83         struct rte_eth_rxq_info *qinfo);
  84 static void axgbe_txq_info_get(struct rte_eth_dev *dev, uint16_t queue_id,
  85         struct rte_eth_txq_info *qinfo);
  86 const uint32_t *axgbe_dev_supported_ptypes_get(struct rte_eth_dev *dev);
  87 static int axgb_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
  88
  89 static int
  90 axgbe_timesync_enable(struct rte_eth_dev *dev);
  91 static int
  92 axgbe_timesync_disable(struct rte_eth_dev *dev);
  93 static int
  94 axgbe_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
  95                         struct timespec *timestamp, uint32_t flags);
  96 static int
  97 axgbe_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
  98                         struct timespec *timestamp);
  99 static int
 100 axgbe_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta);
 101 static int
 102 axgbe_timesync_read_time(struct rte_eth_dev *dev,
 103                         struct timespec *timestamp);
 104 static int
 105 axgbe_timesync_write_time(struct rte_eth_dev *dev,
 106                         const struct timespec *timestamp);
 107 static void
 108 axgbe_set_tstamp_time(struct axgbe_port *pdata, unsigned int sec,
 109                         unsigned int nsec);
 110 static void
 111 axgbe_update_tstamp_addend(struct axgbe_port *pdata,
 112                         unsigned int addend);
 113
 114 struct axgbe_xstats {
 115         char name[RTE_ETH_XSTATS_NAME_SIZE];
 116         int offset;
 117 };
 118
 119 #define AXGMAC_MMC_STAT(_string, _var)                           \
 120         { _string,                                              \
 121           offsetof(struct axgbe_mmc_stats, _var),       \
 122         }
 123
 124 static const struct axgbe_xstats axgbe_xstats_strings[] = {
 125         AXGMAC_MMC_STAT("tx_bytes", txoctetcount_gb),
 126         AXGMAC_MMC_STAT("tx_packets", txframecount_gb),
 127         AXGMAC_MMC_STAT("tx_unicast_packets", txunicastframes_gb),
 128         AXGMAC_MMC_STAT("tx_broadcast_packets", txbroadcastframes_gb),
 129         AXGMAC_MMC_STAT("tx_multicast_packets", txmulticastframes_gb),
 130         AXGMAC_MMC_STAT("tx_vlan_packets", txvlanframes_g),
 131         AXGMAC_MMC_STAT("tx_64_byte_packets", tx64octets_gb),
 132         AXGMAC_MMC_STAT("tx_65_to_127_byte_packets", tx65to127octets_gb),
 133         AXGMAC_MMC_STAT("tx_128_to_255_byte_packets", tx128to255octets_gb),
 134         AXGMAC_MMC_STAT("tx_256_to_511_byte_packets", tx256to511octets_gb),
 135         AXGMAC_MMC_STAT("tx_512_to_1023_byte_packets", tx512to1023octets_gb),
 136         AXGMAC_MMC_STAT("tx_1024_to_max_byte_packets", tx1024tomaxoctets_gb),
 137         AXGMAC_MMC_STAT("tx_underflow_errors", txunderflowerror),
 138         AXGMAC_MMC_STAT("tx_pause_frames", txpauseframes),
 139
 140         AXGMAC_MMC_STAT("rx_bytes", rxoctetcount_gb),
 141         AXGMAC_MMC_STAT("rx_packets", rxframecount_gb),
 142         AXGMAC_MMC_STAT("rx_unicast_packets", rxunicastframes_g),
 143         AXGMAC_MMC_STAT("rx_broadcast_packets", rxbroadcastframes_g),
 144         AXGMAC_MMC_STAT("rx_multicast_packets", rxmulticastframes_g),
 145         AXGMAC_MMC_STAT("rx_vlan_packets", rxvlanframes_gb),
 146         AXGMAC_MMC_STAT("rx_64_byte_packets", rx64octets_gb),
 147         AXGMAC_MMC_STAT("rx_65_to_127_byte_packets", rx65to127octets_gb),
 148         AXGMAC_MMC_STAT("rx_128_to_255_byte_packets", rx128to255octets_gb),
 149         AXGMAC_MMC_STAT("rx_256_to_511_byte_packets", rx256to511octets_gb),
 150         AXGMAC_MMC_STAT("rx_512_to_1023_byte_packets", rx512to1023octets_gb),
 151         AXGMAC_MMC_STAT("rx_1024_to_max_byte_packets", rx1024tomaxoctets_gb),
 152         AXGMAC_MMC_STAT("rx_undersize_packets", rxundersize_g),
 153         AXGMAC_MMC_STAT("rx_oversize_packets", rxoversize_g),
 154         AXGMAC_MMC_STAT("rx_crc_errors", rxcrcerror),
 155         AXGMAC_MMC_STAT("rx_crc_errors_small_packets", rxrunterror),
 156         AXGMAC_MMC_STAT("rx_crc_errors_giant_packets", rxjabbererror),
 157         AXGMAC_MMC_STAT("rx_length_errors", rxlengtherror),
 158         AXGMAC_MMC_STAT("rx_out_of_range_errors", rxoutofrangetype),
 159         AXGMAC_MMC_STAT("rx_fifo_overflow_errors", rxfifooverflow),
 160         AXGMAC_MMC_STAT("rx_watchdog_errors", rxwatchdogerror),
 161         AXGMAC_MMC_STAT("rx_pause_frames", rxpauseframes),
 162 };
 163
 164 #define AXGBE_XSTATS_COUNT        ARRAY_SIZE(axgbe_xstats_strings)
 165
 166 /* The set of PCI devices this driver supports */
 167 #define AMD_PCI_VENDOR_ID       0x1022
 168 #define AMD_PCI_RV_ROOT_COMPLEX_ID      0x15d0
 169 #define AMD_PCI_AXGBE_DEVICE_V2A 0x1458
 170 #define AMD_PCI_AXGBE_DEVICE_V2B 0x1459
 171
 172 static const struct rte_pci_id pci_id_axgbe_map[] = {
 173         {RTE_PCI_DEVICE(AMD_PCI_VENDOR_ID, AMD_PCI_AXGBE_DEVICE_V2A)},
 174         {RTE_PCI_DEVICE(AMD_PCI_VENDOR_ID, AMD_PCI_AXGBE_DEVICE_V2B)},
 175         { .vendor_id = 0, },
 176 };
 177
 178 static struct axgbe_version_data axgbe_v2a = {
 179         .init_function_ptrs_phy_impl    = axgbe_init_function_ptrs_phy_v2,
 180         .xpcs_access                    = AXGBE_XPCS_ACCESS_V2,
 181         .mmc_64bit                      = 1,
 182         .tx_max_fifo_size               = 229376,
 183         .rx_max_fifo_size               = 229376,
 184         .tx_tstamp_workaround           = 1,
 185         .ecc_support                    = 1,
 186         .i2c_support                    = 1,
 187         .an_cdr_workaround              = 1,
 188 };
 189
 190 static struct axgbe_version_data axgbe_v2b = {
 191         .init_function_ptrs_phy_impl    = axgbe_init_function_ptrs_phy_v2,
 192         .xpcs_access                    = AXGBE_XPCS_ACCESS_V2,
 193         .mmc_64bit                      = 1,
 194         .tx_max_fifo_size               = 65536,
 195         .rx_max_fifo_size               = 65536,
 196         .tx_tstamp_workaround           = 1,
 197         .ecc_support                    = 1,
 198         .i2c_support                    = 1,
 199         .an_cdr_workaround              = 1,
 200 };
 201
 202 static const struct rte_eth_desc_lim rx_desc_lim = {
 203         .nb_max = AXGBE_MAX_RING_DESC,
 204         .nb_min = AXGBE_MIN_RING_DESC,
 205         .nb_align = 8,
 206 };
 207
 208 static const struct rte_eth_desc_lim tx_desc_lim = {
 209         .nb_max = AXGBE_MAX_RING_DESC,
 210         .nb_min = AXGBE_MIN_RING_DESC,
 211         .nb_align = 8,
 212 };
 213
 214 static const struct eth_dev_ops axgbe_eth_dev_ops = {
 215         .dev_configure        = axgbe_dev_configure,
 216         .dev_start            = axgbe_dev_start,
 217         .dev_stop             = axgbe_dev_stop,
 218         .dev_close            = axgbe_dev_close,
 219         .promiscuous_enable   = axgbe_dev_promiscuous_enable,
 220         .promiscuous_disable  = axgbe_dev_promiscuous_disable,
 221         .allmulticast_enable  = axgbe_dev_allmulticast_enable,
 222         .allmulticast_disable = axgbe_dev_allmulticast_disable,
 223         .mac_addr_set         = axgbe_dev_mac_addr_set,
 224         .mac_addr_add         = axgbe_dev_mac_addr_add,
 225         .mac_addr_remove      = axgbe_dev_mac_addr_remove,
 226         .set_mc_addr_list     = axgbe_dev_set_mc_addr_list,
 227         .uc_hash_table_set    = axgbe_dev_uc_hash_table_set,
 228         .uc_all_hash_table_set = axgbe_dev_uc_all_hash_table_set,
 229         .link_update          = axgbe_dev_link_update,
 230         .get_reg              = axgbe_dev_get_regs,
 231         .stats_get            = axgbe_dev_stats_get,
 232         .stats_reset          = axgbe_dev_stats_reset,
 233         .xstats_get           = axgbe_dev_xstats_get,
 234         .xstats_reset         = axgbe_dev_xstats_reset,
 235         .xstats_get_names     = axgbe_dev_xstats_get_names,
 236         .xstats_get_names_by_id = axgbe_dev_xstats_get_names_by_id,
 237         .xstats_get_by_id     = axgbe_dev_xstats_get_by_id,
 238         .reta_update          = axgbe_dev_rss_reta_update,
 239         .reta_query           = axgbe_dev_rss_reta_query,
 240         .rss_hash_update      = axgbe_dev_rss_hash_update,
 241         .rss_hash_conf_get    = axgbe_dev_rss_hash_conf_get,
 242         .dev_infos_get        = axgbe_dev_info_get,
 243         .rx_queue_setup       = axgbe_dev_rx_queue_setup,
 244         .rx_queue_release     = axgbe_dev_rx_queue_release,
 245         .tx_queue_setup       = axgbe_dev_tx_queue_setup,
 246         .tx_queue_release     = axgbe_dev_tx_queue_release,
 247         .flow_ctrl_get        = axgbe_flow_ctrl_get,
 248         .flow_ctrl_set        = axgbe_flow_ctrl_set,
 249         .priority_flow_ctrl_set = axgbe_priority_flow_ctrl_set,
 250         .rxq_info_get                 = axgbe_rxq_info_get,
 251         .txq_info_get                 = axgbe_txq_info_get,
 252         .dev_supported_ptypes_get     = axgbe_dev_supported_ptypes_get,
 253         .mtu_set                = axgb_mtu_set,
 254         .timesync_enable              = axgbe_timesync_enable,
 255         .timesync_disable             = axgbe_timesync_disable,
 256         .timesync_read_rx_timestamp   = axgbe_timesync_read_rx_timestamp,
 257         .timesync_read_tx_timestamp   = axgbe_timesync_read_tx_timestamp,
 258         .timesync_adjust_time         = axgbe_timesync_adjust_time,
 259         .timesync_read_time           = axgbe_timesync_read_time,
 260         .timesync_write_time          = axgbe_timesync_write_time,
 261 };
 262
 263 static int axgbe_phy_reset(struct axgbe_port *pdata)
 264 {
 265         pdata->phy_link = -1;
 266         pdata->phy_speed = SPEED_UNKNOWN;
 267         return pdata->phy_if.phy_reset(pdata);
 268 }
 269
 270 /*
 271  * Interrupt handler triggered by NIC  for handling
 272  * specific interrupt.
 273  *
 274  * @param handle
 275  *  Pointer to interrupt handle.
 276  * @param param
 277  *  The address of parameter (struct rte_eth_dev *) regsitered before.
 278  *
 279  * @return
 280  *  void
 281  */
 282 static void
 283 axgbe_dev_interrupt_handler(void *param)
 284 {
 285         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
 286         struct axgbe_port *pdata = dev->data->dev_private;
 287         unsigned int dma_isr, dma_ch_isr;
 288
 289         pdata->phy_if.an_isr(pdata);
 290         /*DMA related interrupts*/
 291         dma_isr = AXGMAC_IOREAD(pdata, DMA_ISR);
 292         PMD_DRV_LOG(DEBUG, "DMA_ISR=%#010x\n", dma_isr);
 293         if (dma_isr) {
 294                 if (dma_isr & 1) {
 295                         dma_ch_isr =
 296                                 AXGMAC_DMA_IOREAD((struct axgbe_rx_queue *)
 297                                                   pdata->rx_queues[0],
 298                                                   DMA_CH_SR);
 299                         PMD_DRV_LOG(DEBUG, "DMA_CH0_ISR=%#010x\n", dma_ch_isr);
 300                         AXGMAC_DMA_IOWRITE((struct axgbe_rx_queue *)
 301                                            pdata->rx_queues[0],
 302                                            DMA_CH_SR, dma_ch_isr);
 303                 }
 304         }
 305         /* Unmask interrupts since disabled after generation */
 306         rte_intr_ack(&pdata->pci_dev->intr_handle);
 307 }
 308
 309 /*
 310  * Configure device link speed and setup link.
 311  * It returns 0 on success.
 312  */
 313 static int
 314 axgbe_dev_configure(struct rte_eth_dev *dev)
 315 {
 316         struct axgbe_port *pdata =  dev->data->dev_private;
 317         /* Checksum offload to hardware */
 318         pdata->rx_csum_enable = dev->data->dev_conf.rxmode.offloads &
 319                                 DEV_RX_OFFLOAD_CHECKSUM;
 320         return 0;
 321 }
 322
 323 static int
 324 axgbe_dev_rx_mq_config(struct rte_eth_dev *dev)
 325 {
 326         struct axgbe_port *pdata = dev->data->dev_private;
 327
 328         if (dev->data->dev_conf.rxmode.mq_mode == ETH_MQ_RX_RSS)
 329                 pdata->rss_enable = 1;
 330         else if (dev->data->dev_conf.rxmode.mq_mode == ETH_MQ_RX_NONE)
 331                 pdata->rss_enable = 0;
 332         else
 333                 return  -1;
 334         return 0;
 335 }
 336
 337 static int
 338 axgbe_dev_start(struct rte_eth_dev *dev)
 339 {
 340         struct axgbe_port *pdata = dev->data->dev_private;
 341         int ret;
 342         struct rte_eth_dev_data *dev_data = dev->data;
 343         uint16_t max_pkt_len = dev_data->dev_conf.rxmode.max_rx_pkt_len;
 344
 345         dev->dev_ops = &axgbe_eth_dev_ops;
 346
 347         PMD_INIT_FUNC_TRACE();
 348
 349         /* Multiqueue RSS */
 350         ret = axgbe_dev_rx_mq_config(dev);
 351         if (ret) {
 352                 PMD_DRV_LOG(ERR, "Unable to config RX MQ\n");
 353                 return ret;
 354         }
 355         ret = axgbe_phy_reset(pdata);
 356         if (ret) {
 357                 PMD_DRV_LOG(ERR, "phy reset failed\n");
 358                 return ret;
 359         }
 360         ret = pdata->hw_if.init(pdata);
 361         if (ret) {
 362                 PMD_DRV_LOG(ERR, "dev_init failed\n");
 363                 return ret;
 364         }
 365
 366         /* enable uio/vfio intr/eventfd mapping */
 367         rte_intr_enable(&pdata->pci_dev->intr_handle);
 368
 369         /* phy start*/
 370         pdata->phy_if.phy_start(pdata);
 371         axgbe_dev_enable_tx(dev);
 372         axgbe_dev_enable_rx(dev);
 373
 374         rte_bit_relaxed_clear32(AXGBE_STOPPED, &pdata->dev_state);
 375         rte_bit_relaxed_clear32(AXGBE_DOWN, &pdata->dev_state);
 376         if ((dev_data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_SCATTER) ||
 377                                 max_pkt_len > pdata->rx_buf_size)
 378                 dev_data->scattered_rx = 1;
 379
 380         /*  Scatter Rx handling */
 381         if (dev_data->scattered_rx)
 382                 dev->rx_pkt_burst = &eth_axgbe_recv_scattered_pkts;
 383         else
 384                 dev->rx_pkt_burst = &axgbe_recv_pkts;
 385
 386         return 0;
 387 }
 388
 389 /* Stop device: disable rx and tx functions to allow for reconfiguring. */
 390 static void
 391 axgbe_dev_stop(struct rte_eth_dev *dev)
 392 {
 393         struct axgbe_port *pdata = dev->data->dev_private;
 394
 395         PMD_INIT_FUNC_TRACE();
 396
 397         rte_intr_disable(&pdata->pci_dev->intr_handle);
 398
 399         if (rte_bit_relaxed_get32(AXGBE_STOPPED, &pdata->dev_state))
 400                 return;
 401
 402         rte_bit_relaxed_set32(AXGBE_STOPPED, &pdata->dev_state);
 403         axgbe_dev_disable_tx(dev);
 404         axgbe_dev_disable_rx(dev);
 405
 406         pdata->phy_if.phy_stop(pdata);
 407         pdata->hw_if.exit(pdata);
 408         memset(&dev->data->dev_link, 0, sizeof(struct rte_eth_link));
 409         rte_bit_relaxed_set32(AXGBE_DOWN, &pdata->dev_state);
 410 }
 411
 412 /* Clear all resources like TX/RX queues. */
 413 static int
 414 axgbe_dev_close(struct rte_eth_dev *dev)
 415 {
 416         axgbe_dev_clear_queues(dev);
 417         return 0;
 418 }
 419
 420 static int
 421 axgbe_dev_promiscuous_enable(struct rte_eth_dev *dev)
 422 {
 423         struct axgbe_port *pdata = dev->data->dev_private;
 424
 425         PMD_INIT_FUNC_TRACE();
 426
 427         AXGMAC_IOWRITE_BITS(pdata, MAC_PFR, PR, 1);
 428
 429         return 0;
 430 }
 431
 432 static int
 433 axgbe_dev_promiscuous_disable(struct rte_eth_dev *dev)
 434 {
 435         struct axgbe_port *pdata = dev->data->dev_private;
 436
 437         PMD_INIT_FUNC_TRACE();
 438
 439         AXGMAC_IOWRITE_BITS(pdata, MAC_PFR, PR, 0);
 440
 441         return 0;
 442 }
 443
 444 static int
 445 axgbe_dev_allmulticast_enable(struct rte_eth_dev *dev)
 446 {
 447         struct axgbe_port *pdata = dev->data->dev_private;
 448
 449         PMD_INIT_FUNC_TRACE();
 450
 451         if (AXGMAC_IOREAD_BITS(pdata, MAC_PFR, PM))
 452                 return 0;
 453         AXGMAC_IOWRITE_BITS(pdata, MAC_PFR, PM, 1);
 454
 455         return 0;
 456 }
 457
 458 static int
 459 axgbe_dev_allmulticast_disable(struct rte_eth_dev *dev)
 460 {
 461         struct axgbe_port *pdata = dev->data->dev_private;
 462
 463         PMD_INIT_FUNC_TRACE();
 464
 465         if (!AXGMAC_IOREAD_BITS(pdata, MAC_PFR, PM))
 466                 return 0;
 467         AXGMAC_IOWRITE_BITS(pdata, MAC_PFR, PM, 0);
 468
 469         return 0;
 470 }
 471
 472 static int
 473 axgbe_dev_mac_addr_set(struct rte_eth_dev *dev, struct rte_ether_addr *mac_addr)
 474 {
 475         struct axgbe_port *pdata = dev->data->dev_private;
 476
 477         /* Set Default MAC Addr */
 478         axgbe_set_mac_addn_addr(pdata, (u8 *)mac_addr, 0);
 479
 480         return 0;
 481 }
 482
 483 static int
 484 axgbe_dev_mac_addr_add(struct rte_eth_dev *dev, struct rte_ether_addr *mac_addr,
 485                               uint32_t index, uint32_t pool __rte_unused)
 486 {
 487         struct axgbe_port *pdata = dev->data->dev_private;
 488         struct axgbe_hw_features *hw_feat = &pdata->hw_feat;
 489
 490         if (index > hw_feat->addn_mac) {
 491                 PMD_DRV_LOG(ERR, "Invalid Index %d\n", index);
 492                 return -EINVAL;
 493         }
 494         axgbe_set_mac_addn_addr(pdata, (u8 *)mac_addr, index);
 495         return 0;
 496 }
 497
 498 static int
 499 axgbe_dev_rss_reta_update(struct rte_eth_dev *dev,
 500                           struct rte_eth_rss_reta_entry64 *reta_conf,
 501                           uint16_t reta_size)
 502 {
 503         struct axgbe_port *pdata = dev->data->dev_private;
 504         unsigned int i, idx, shift;
 505         int ret;
 506
 507         if (!pdata->rss_enable) {
 508                 PMD_DRV_LOG(ERR, "RSS not enabled\n");
 509                 return -ENOTSUP;
 510         }
 511
 512         if (reta_size == 0 || reta_size > AXGBE_RSS_MAX_TABLE_SIZE) {
 513                 PMD_DRV_LOG(ERR, "reta_size %d is not supported\n", reta_size);
 514                 return -EINVAL;
 515         }
 516
 517         for (i = 0; i < reta_size; i++) {
 518                 idx = i / RTE_RETA_GROUP_SIZE;
 519                 shift = i % RTE_RETA_GROUP_SIZE;
 520                 if ((reta_conf[idx].mask & (1ULL << shift)) == 0)
 521                         continue;
 522                 pdata->rss_table[i] = reta_conf[idx].reta[shift];
 523         }
 524
 525         /* Program the lookup table */
 526         ret = axgbe_write_rss_lookup_table(pdata);
 527         return ret;
 528 }
 529
 530 static int
 531 axgbe_dev_rss_reta_query(struct rte_eth_dev *dev,
 532                          struct rte_eth_rss_reta_entry64 *reta_conf,
 533                          uint16_t reta_size)
 534 {
 535         struct axgbe_port *pdata = dev->data->dev_private;
 536         unsigned int i, idx, shift;
 537
 538         if (!pdata->rss_enable) {
 539                 PMD_DRV_LOG(ERR, "RSS not enabled\n");
 540                 return -ENOTSUP;
 541         }
 542
 543         if (reta_size == 0 || reta_size > AXGBE_RSS_MAX_TABLE_SIZE) {
 544                 PMD_DRV_LOG(ERR, "reta_size %d is not supported\n", reta_size);
 545                 return -EINVAL;
 546         }
 547
 548         for (i = 0; i < reta_size; i++) {
 549                 idx = i / RTE_RETA_GROUP_SIZE;
 550                 shift = i % RTE_RETA_GROUP_SIZE;
 551                 if ((reta_conf[idx].mask & (1ULL << shift)) == 0)
 552                         continue;
 553                 reta_conf[idx].reta[shift] = pdata->rss_table[i];
 554         }
 555         return 0;
 556 }
 557
 558 static int
 559 axgbe_dev_rss_hash_update(struct rte_eth_dev *dev,
 560                           struct rte_eth_rss_conf *rss_conf)
 561 {
 562         struct axgbe_port *pdata = dev->data->dev_private;
 563         int ret;
 564
 565         if (!pdata->rss_enable) {
 566                 PMD_DRV_LOG(ERR, "RSS not enabled\n");
 567                 return -ENOTSUP;
 568         }
 569
 570         if (rss_conf == NULL) {
 571                 PMD_DRV_LOG(ERR, "rss_conf value isn't valid\n");
 572                 return -EINVAL;
 573         }
 574
 575         if (rss_conf->rss_key != NULL &&
 576             rss_conf->rss_key_len == AXGBE_RSS_HASH_KEY_SIZE) {
 577                 rte_memcpy(pdata->rss_key, rss_conf->rss_key,
 578                        AXGBE_RSS_HASH_KEY_SIZE);
 579                 /* Program the hash key */
 580                 ret = axgbe_write_rss_hash_key(pdata);
 581                 if (ret != 0)
 582                         return ret;
 583         }
 584
 585         pdata->rss_hf = rss_conf->rss_hf & AXGBE_RSS_OFFLOAD;
 586
 587         if (pdata->rss_hf & (ETH_RSS_IPV4 | ETH_RSS_IPV6))
 588                 AXGMAC_SET_BITS(pdata->rss_options, MAC_RSSCR, IP2TE, 1);
 589         if (pdata->rss_hf &
 590             (ETH_RSS_NONFRAG_IPV4_TCP | ETH_RSS_NONFRAG_IPV6_TCP))
 591                 AXGMAC_SET_BITS(pdata->rss_options, MAC_RSSCR, TCP4TE, 1);
 592         if (pdata->rss_hf &
 593             (ETH_RSS_NONFRAG_IPV4_UDP | ETH_RSS_NONFRAG_IPV6_UDP))
 594                 AXGMAC_SET_BITS(pdata->rss_options, MAC_RSSCR, UDP4TE, 1);
 595
 596         /* Set the RSS options */
 597         AXGMAC_IOWRITE(pdata, MAC_RSSCR, pdata->rss_options);
 598
 599         return 0;
 600 }
 601
 602 static int
 603 axgbe_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
 604                             struct rte_eth_rss_conf *rss_conf)
 605 {
 606         struct axgbe_port *pdata = dev->data->dev_private;
 607
 608         if (!pdata->rss_enable) {
 609                 PMD_DRV_LOG(ERR, "RSS not enabled\n");
 610                 return -ENOTSUP;
 611         }
 612
 613         if (rss_conf == NULL) {
 614                 PMD_DRV_LOG(ERR, "rss_conf value isn't valid\n");
 615                 return -EINVAL;
 616         }
 617
 618         if (rss_conf->rss_key != NULL &&
 619             rss_conf->rss_key_len >= AXGBE_RSS_HASH_KEY_SIZE) {
 620                 rte_memcpy(rss_conf->rss_key, pdata->rss_key,
 621                        AXGBE_RSS_HASH_KEY_SIZE);
 622         }
 623         rss_conf->rss_key_len = AXGBE_RSS_HASH_KEY_SIZE;
 624         rss_conf->rss_hf = pdata->rss_hf;
 625         return 0;
 626 }
 627
 628 static void
 629 axgbe_dev_mac_addr_remove(struct rte_eth_dev *dev, uint32_t index)
 630 {
 631         struct axgbe_port *pdata = dev->data->dev_private;
 632         struct axgbe_hw_features *hw_feat = &pdata->hw_feat;
 633
 634         if (index > hw_feat->addn_mac) {
 635                 PMD_DRV_LOG(ERR, "Invalid Index %d\n", index);
 636                 return;
 637         }
 638         axgbe_set_mac_addn_addr(pdata, NULL, index);
 639 }
 640
 641 static int
 642 axgbe_dev_set_mc_addr_list(struct rte_eth_dev *dev,
 643                                       struct rte_ether_addr *mc_addr_set,
 644                                       uint32_t nb_mc_addr)
 645 {
 646         struct axgbe_port *pdata = dev->data->dev_private;
 647         struct axgbe_hw_features *hw_feat = &pdata->hw_feat;
 648         uint32_t index = 1; /* 0 is always default mac */
 649         uint32_t i;
 650
 651         if (nb_mc_addr > hw_feat->addn_mac) {
 652                 PMD_DRV_LOG(ERR, "Invalid Index %d\n", nb_mc_addr);
 653                 return -EINVAL;
 654         }
 655
 656         /* clear unicast addresses */
 657         for (i = 1; i < hw_feat->addn_mac; i++) {
 658                 if (rte_is_zero_ether_addr(&dev->data->mac_addrs[i]))
 659                         continue;
 660                 memset(&dev->data->mac_addrs[i], 0,
 661                        sizeof(struct rte_ether_addr));
 662         }
 663
 664         while (nb_mc_addr--)
 665                 axgbe_set_mac_addn_addr(pdata, (u8 *)mc_addr_set++, index++);
 666
 667         return 0;
 668 }
 669
 670 static int
 671 axgbe_dev_uc_hash_table_set(struct rte_eth_dev *dev,
 672                             struct rte_ether_addr *mac_addr, uint8_t add)
 673 {
 674         struct axgbe_port *pdata = dev->data->dev_private;
 675         struct axgbe_hw_features *hw_feat = &pdata->hw_feat;
 676
 677         if (!hw_feat->hash_table_size) {
 678                 PMD_DRV_LOG(ERR, "MAC Hash Table not supported\n");
 679                 return -ENOTSUP;
 680         }
 681
 682         axgbe_set_mac_hash_table(pdata, (u8 *)mac_addr, add);
 683
 684         if (pdata->uc_hash_mac_addr > 0) {
 685                 AXGMAC_IOWRITE_BITS(pdata, MAC_PFR, HPF, 1);
 686                 AXGMAC_IOWRITE_BITS(pdata, MAC_PFR, HUC, 1);
 687         } else {
 688                 AXGMAC_IOWRITE_BITS(pdata, MAC_PFR, HPF, 0);
 689                 AXGMAC_IOWRITE_BITS(pdata, MAC_PFR, HUC, 0);
 690         }
 691         return 0;
 692 }
 693
 694 static int
 695 axgbe_dev_uc_all_hash_table_set(struct rte_eth_dev *dev, uint8_t add)
 696 {
 697         struct axgbe_port *pdata = dev->data->dev_private;
 698         struct axgbe_hw_features *hw_feat = &pdata->hw_feat;
 699         uint32_t index;
 700
 701         if (!hw_feat->hash_table_size) {
 702                 PMD_DRV_LOG(ERR, "MAC Hash Table not supported\n");
 703                 return -ENOTSUP;
 704         }
 705
 706         for (index = 0; index < pdata->hash_table_count; index++) {
 707                 if (add)
 708                         pdata->uc_hash_table[index] = ~0;
 709                 else
 710                         pdata->uc_hash_table[index] = 0;
 711
 712                 PMD_DRV_LOG(DEBUG, "%s MAC hash table at Index %#x\n",
 713                             add ? "set" : "clear", index);
 714
 715                 AXGMAC_IOWRITE(pdata, MAC_HTR(index),
 716                                pdata->uc_hash_table[index]);
 717         }
 718
 719         if (add) {
 720                 AXGMAC_IOWRITE_BITS(pdata, MAC_PFR, HPF, 1);
 721                 AXGMAC_IOWRITE_BITS(pdata, MAC_PFR, HUC, 1);
 722         } else {
 723                 AXGMAC_IOWRITE_BITS(pdata, MAC_PFR, HPF, 0);
 724                 AXGMAC_IOWRITE_BITS(pdata, MAC_PFR, HUC, 0);
 725         }
 726         return 0;
 727 }
 728
 729 /* return 0 means link status changed, -1 means not changed */
 730 static int
 731 axgbe_dev_link_update(struct rte_eth_dev *dev,
 732                       int wait_to_complete __rte_unused)
 733 {
 734         struct axgbe_port *pdata = dev->data->dev_private;
 735         struct rte_eth_link link;
 736         int ret = 0;
 737
 738         PMD_INIT_FUNC_TRACE();
 739         rte_delay_ms(800);
 740
 741         pdata->phy_if.phy_status(pdata);
 742
 743         memset(&link, 0, sizeof(struct rte_eth_link));
 744         link.link_duplex = pdata->phy.duplex;
 745         link.link_status = pdata->phy_link;
 746         link.link_speed = pdata->phy_speed;
 747         link.link_autoneg = !(dev->data->dev_conf.link_speeds &
 748                               ETH_LINK_SPEED_FIXED);
 749         ret = rte_eth_linkstatus_set(dev, &link);
 750         if (ret == -1)
 751                 PMD_DRV_LOG(ERR, "No change in link status\n");
 752
 753         return ret;
 754 }
 755
 756 static int
 757 axgbe_dev_get_regs(struct rte_eth_dev *dev, struct rte_dev_reg_info *regs)
 758 {
 759         struct axgbe_port *pdata = dev->data->dev_private;
 760
 761         if (regs->data == NULL) {
 762                 regs->length = axgbe_regs_get_count(pdata);
 763                 regs->width = sizeof(uint32_t);
 764                 return 0;
 765         }
 766
 767         /* Only full register dump is supported */
 768         if (regs->length &&
 769             regs->length != (uint32_t)axgbe_regs_get_count(pdata))
 770                 return -ENOTSUP;
 771
 772         regs->version = pdata->pci_dev->id.vendor_id << 16 |
 773                         pdata->pci_dev->id.device_id;
 774         axgbe_regs_dump(pdata, regs->data);
 775         return 0;
 776 }
 777 static void axgbe_read_mmc_stats(struct axgbe_port *pdata)
 778 {
 779         struct axgbe_mmc_stats *stats = &pdata->mmc_stats;
 780
 781         /* Freeze counters */
 782         AXGMAC_IOWRITE_BITS(pdata, MMC_CR, MCF, 1);
 783
 784         /* Tx counters */
 785         stats->txoctetcount_gb +=
 786                 AXGMAC_IOREAD(pdata, MMC_TXOCTETCOUNT_GB_LO);
 787         stats->txoctetcount_gb +=
 788         ((uint64_t)AXGMAC_IOREAD(pdata, MMC_TXOCTETCOUNT_GB_HI) << 32);
 789
 790         stats->txframecount_gb +=
 791                 AXGMAC_IOREAD(pdata, MMC_TXFRAMECOUNT_GB_LO);
 792         stats->txframecount_gb +=
 793         ((uint64_t)AXGMAC_IOREAD(pdata, MMC_TXFRAMECOUNT_GB_HI) << 32);
 794
 795         stats->txbroadcastframes_g +=
 796                 AXGMAC_IOREAD(pdata, MMC_TXBROADCASTFRAMES_G_LO);
 797         stats->txbroadcastframes_g +=
 798         ((uint64_t)AXGMAC_IOREAD(pdata, MMC_TXBROADCASTFRAMES_G_HI) << 32);
 799
 800         stats->txmulticastframes_g +=
 801                 AXGMAC_IOREAD(pdata, MMC_TXMULTICASTFRAMES_G_LO);
 802         stats->txmulticastframes_g +=
 803         ((uint64_t)AXGMAC_IOREAD(pdata, MMC_TXMULTICASTFRAMES_G_HI) << 32);
 804
 805         stats->tx64octets_gb +=
 806                 AXGMAC_IOREAD(pdata, MMC_TX64OCTETS_GB_LO);
 807         stats->tx64octets_gb +=
 808         ((uint64_t)AXGMAC_IOREAD(pdata, MMC_TX64OCTETS_GB_HI) << 32);
 809
 810         stats->tx65to127octets_gb +=
 811                 AXGMAC_IOREAD(pdata, MMC_TX65TO127OCTETS_GB_LO);
 812         stats->tx65to127octets_gb +=
 813         ((uint64_t)AXGMAC_IOREAD(pdata, MMC_TX65TO127OCTETS_GB_HI) << 32);
 814
 815         stats->tx128to255octets_gb +=
 816                 AXGMAC_IOREAD(pdata, MMC_TX128TO255OCTETS_GB_LO);
 817         stats->tx128to255octets_gb +=
 818         ((uint64_t)AXGMAC_IOREAD(pdata, MMC_TX128TO255OCTETS_GB_HI) << 32);
 819
 820         stats->tx256to511octets_gb +=
 821                 AXGMAC_IOREAD(pdata, MMC_TX256TO511OCTETS_GB_LO);
 822         stats->tx256to511octets_gb +=
 823         ((uint64_t)AXGMAC_IOREAD(pdata, MMC_TX256TO511OCTETS_GB_HI) << 32);
 824
 825         stats->tx512to1023octets_gb +=
 826                 AXGMAC_IOREAD(pdata, MMC_TX512TO1023OCTETS_GB_LO);
 827         stats->tx512to1023octets_gb +=
 828         ((uint64_t)AXGMAC_IOREAD(pdata, MMC_TX512TO1023OCTETS_GB_HI) << 32);
 829
 830         stats->tx1024tomaxoctets_gb +=
 831                 AXGMAC_IOREAD(pdata, MMC_TX1024TOMAXOCTETS_GB_LO);
 832         stats->tx1024tomaxoctets_gb +=
 833         ((uint64_t)AXGMAC_IOREAD(pdata, MMC_TX1024TOMAXOCTETS_GB_HI) << 32);
 834
 835         stats->txunicastframes_gb +=
 836                 AXGMAC_IOREAD(pdata, MMC_TXUNICASTFRAMES_GB_LO);
 837         stats->txunicastframes_gb +=
 838         ((uint64_t)AXGMAC_IOREAD(pdata, MMC_TXUNICASTFRAMES_GB_HI) << 32);
 839
 840         stats->txmulticastframes_gb +=
 841                 AXGMAC_IOREAD(pdata, MMC_TXMULTICASTFRAMES_GB_LO);
 842         stats->txmulticastframes_gb +=
 843         ((uint64_t)AXGMAC_IOREAD(pdata, MMC_TXMULTICASTFRAMES_GB_HI) << 32);
 844
 845         stats->txbroadcastframes_g +=
 846                 AXGMAC_IOREAD(pdata, MMC_TXBROADCASTFRAMES_GB_LO);
 847         stats->txbroadcastframes_g +=
 848         ((uint64_t)AXGMAC_IOREAD(pdata, MMC_TXBROADCASTFRAMES_GB_HI) << 32);
 849
 850         stats->txunderflowerror +=
 851                 AXGMAC_IOREAD(pdata, MMC_TXUNDERFLOWERROR_LO);
 852         stats->txunderflowerror +=
 853         ((uint64_t)AXGMAC_IOREAD(pdata, MMC_TXUNDERFLOWERROR_HI) << 32);
 854
 855         stats->txoctetcount_g +=
 856                 AXGMAC_IOREAD(pdata, MMC_TXOCTETCOUNT_G_LO);
 857         stats->txoctetcount_g +=
 858         ((uint64_t)AXGMAC_IOREAD(pdata, MMC_TXOCTETCOUNT_G_HI) << 32);
 859
 860         stats->txframecount_g +=
 861                 AXGMAC_IOREAD(pdata, MMC_TXFRAMECOUNT_G_LO);
 862         stats->txframecount_g +=
 863         ((uint64_t)AXGMAC_IOREAD(pdata, MMC_TXFRAMECOUNT_G_HI) << 32);
 864
 865         stats->txpauseframes +=
 866                 AXGMAC_IOREAD(pdata, MMC_TXPAUSEFRAMES_LO);
 867         stats->txpauseframes +=
 868         ((uint64_t)AXGMAC_IOREAD(pdata, MMC_TXPAUSEFRAMES_HI) << 32);
 869
 870         stats->txvlanframes_g +=
 871                 AXGMAC_IOREAD(pdata, MMC_TXVLANFRAMES_G_LO);
 872         stats->txvlanframes_g +=
 873         ((uint64_t)AXGMAC_IOREAD(pdata, MMC_TXVLANFRAMES_G_HI) << 32);
 874
 875         /* Rx counters */
 876         stats->rxframecount_gb +=
 877                 AXGMAC_IOREAD(pdata, MMC_RXFRAMECOUNT_GB_LO);
 878         stats->rxframecount_gb +=
 879         ((uint64_t)AXGMAC_IOREAD(pdata, MMC_RXFRAMECOUNT_GB_HI) << 32);
 880
 881         stats->rxoctetcount_gb +=
 882                 AXGMAC_IOREAD(pdata, MMC_RXOCTETCOUNT_GB_LO);
 883         stats->rxoctetcount_gb +=
 884         ((uint64_t)AXGMAC_IOREAD(pdata, MMC_RXOCTETCOUNT_GB_HI) << 32);
 885
 886         stats->rxoctetcount_g +=
 887                 AXGMAC_IOREAD(pdata, MMC_RXOCTETCOUNT_G_LO);
 888         stats->rxoctetcount_g +=
 889         ((uint64_t)AXGMAC_IOREAD(pdata, MMC_RXOCTETCOUNT_G_HI) << 32);
 890
 891         stats->rxbroadcastframes_g +=
 892                 AXGMAC_IOREAD(pdata, MMC_RXBROADCASTFRAMES_G_LO);
 893         stats->rxbroadcastframes_g +=
 894         ((uint64_t)AXGMAC_IOREAD(pdata, MMC_RXBROADCASTFRAMES_G_HI) << 32);
 895
 896         stats->rxmulticastframes_g +=
 897                 AXGMAC_IOREAD(pdata, MMC_RXMULTICASTFRAMES_G_LO);
 898         stats->rxmulticastframes_g +=
 899         ((uint64_t)AXGMAC_IOREAD(pdata, MMC_RXMULTICASTFRAMES_G_HI) << 32);
 900
 901         stats->rxcrcerror +=
 902                 AXGMAC_IOREAD(pdata, MMC_RXCRCERROR_LO);
 903         stats->rxcrcerror +=
 904         ((uint64_t)AXGMAC_IOREAD(pdata, MMC_RXCRCERROR_HI) << 32);
 905
 906         stats->rxrunterror +=
 907                 AXGMAC_IOREAD(pdata, MMC_RXRUNTERROR);
 908
 909         stats->rxjabbererror +=
 910                 AXGMAC_IOREAD(pdata, MMC_RXJABBERERROR);
 911
 912         stats->rxundersize_g +=
 913                 AXGMAC_IOREAD(pdata, MMC_RXUNDERSIZE_G);
 914
 915         stats->rxoversize_g +=
 916                 AXGMAC_IOREAD(pdata, MMC_RXOVERSIZE_G);
 917
 918         stats->rx64octets_gb +=
 919                 AXGMAC_IOREAD(pdata, MMC_RX64OCTETS_GB_LO);
 920         stats->rx64octets_gb +=
 921         ((uint64_t)AXGMAC_IOREAD(pdata, MMC_RX64OCTETS_GB_HI) << 32);
 922
 923         stats->rx65to127octets_gb +=
 924                 AXGMAC_IOREAD(pdata, MMC_RX65TO127OCTETS_GB_LO);
 925         stats->rx65to127octets_gb +=
 926         ((uint64_t)AXGMAC_IOREAD(pdata, MMC_RX65TO127OCTETS_GB_HI) << 32);
 927
 928         stats->rx128to255octets_gb +=
 929                 AXGMAC_IOREAD(pdata, MMC_RX128TO255OCTETS_GB_LO);
 930         stats->rx128to255octets_gb +=
 931         ((uint64_t)AXGMAC_IOREAD(pdata, MMC_RX128TO255OCTETS_GB_HI) << 32);
 932
 933         stats->rx256to511octets_gb +=
 934                 AXGMAC_IOREAD(pdata, MMC_RX256TO511OCTETS_GB_LO);
 935         stats->rx256to511octets_gb +=
 936         ((uint64_t)AXGMAC_IOREAD(pdata, MMC_RX256TO511OCTETS_GB_HI) << 32);
 937
 938         stats->rx512to1023octets_gb +=
 939                 AXGMAC_IOREAD(pdata, MMC_RX512TO1023OCTETS_GB_LO);
 940         stats->rx512to1023octets_gb +=
 941         ((uint64_t)AXGMAC_IOREAD(pdata, MMC_RX512TO1023OCTETS_GB_HI) << 32);
 942
 943         stats->rx1024tomaxoctets_gb +=
 944                 AXGMAC_IOREAD(pdata, MMC_RX1024TOMAXOCTETS_GB_LO);
 945         stats->rx1024tomaxoctets_gb +=
 946         ((uint64_t)AXGMAC_IOREAD(pdata, MMC_RX1024TOMAXOCTETS_GB_HI) << 32);
 947
 948         stats->rxunicastframes_g +=
 949                 AXGMAC_IOREAD(pdata, MMC_RXUNICASTFRAMES_G_LO);
 950         stats->rxunicastframes_g +=
 951         ((uint64_t)AXGMAC_IOREAD(pdata, MMC_RXUNICASTFRAMES_G_HI) << 32);
 952
 953         stats->rxlengtherror +=
 954                 AXGMAC_IOREAD(pdata, MMC_RXLENGTHERROR_LO);
 955         stats->rxlengtherror +=
 956         ((uint64_t)AXGMAC_IOREAD(pdata, MMC_RXLENGTHERROR_HI) << 32);
 957
 958         stats->rxoutofrangetype +=
 959                 AXGMAC_IOREAD(pdata, MMC_RXOUTOFRANGETYPE_LO);
 960         stats->rxoutofrangetype +=
 961         ((uint64_t)AXGMAC_IOREAD(pdata, MMC_RXOUTOFRANGETYPE_HI) << 32);
 962
 963         stats->rxpauseframes +=
 964                 AXGMAC_IOREAD(pdata, MMC_RXPAUSEFRAMES_LO);
 965         stats->rxpauseframes +=
 966         ((uint64_t)AXGMAC_IOREAD(pdata, MMC_RXPAUSEFRAMES_HI) << 32);
 967
 968         stats->rxfifooverflow +=
 969                 AXGMAC_IOREAD(pdata, MMC_RXFIFOOVERFLOW_LO);
 970         stats->rxfifooverflow +=
 971         ((uint64_t)AXGMAC_IOREAD(pdata, MMC_RXFIFOOVERFLOW_HI) << 32);
 972
 973         stats->rxvlanframes_gb +=
 974                 AXGMAC_IOREAD(pdata, MMC_RXVLANFRAMES_GB_LO);
 975         stats->rxvlanframes_gb +=
 976         ((uint64_t)AXGMAC_IOREAD(pdata, MMC_RXVLANFRAMES_GB_HI) << 32);
 977
 978         stats->rxwatchdogerror +=
 979                 AXGMAC_IOREAD(pdata, MMC_RXWATCHDOGERROR);
 980
 981         /* Un-freeze counters */
 982         AXGMAC_IOWRITE_BITS(pdata, MMC_CR, MCF, 0);
 983 }
 984
 985 static int
 986 axgbe_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *stats,
 987                      unsigned int n)
 988 {
 989         struct axgbe_port *pdata = dev->data->dev_private;
 990         unsigned int i;
 991
 992         if (!stats)
 993                 return 0;
 994
 995         axgbe_read_mmc_stats(pdata);
 996
 997         for (i = 0; i < n && i < AXGBE_XSTATS_COUNT; i++) {
 998                 stats[i].id = i;
 999                 stats[i].value = *(u64 *)((uint8_t *)&pdata->mmc_stats +
1000                                 axgbe_xstats_strings[i].offset);
1001         }
1002
1003         return i;
1004 }
1005
1006 static int
1007 axgbe_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
1008                            struct rte_eth_xstat_name *xstats_names,
1009                            unsigned int n)
1010 {
1011         unsigned int i;
1012
1013         if (n >= AXGBE_XSTATS_COUNT && xstats_names) {
1014                 for (i = 0; i < AXGBE_XSTATS_COUNT; ++i) {
1015                         snprintf(xstats_names[i].name,
1016                                  RTE_ETH_XSTATS_NAME_SIZE, "%s",
1017                                  axgbe_xstats_strings[i].name);
1018                 }
1019         }
1020
1021         return AXGBE_XSTATS_COUNT;
1022 }
1023
1024 static int
1025 axgbe_dev_xstats_get_by_id(struct rte_eth_dev *dev, const uint64_t *ids,
1026                            uint64_t *values, unsigned int n)
1027 {
1028         unsigned int i;
1029         uint64_t values_copy[AXGBE_XSTATS_COUNT];
1030
1031         if (!ids) {
1032                 struct axgbe_port *pdata = dev->data->dev_private;
1033
1034                 if (n < AXGBE_XSTATS_COUNT)
1035                         return AXGBE_XSTATS_COUNT;
1036
1037                 axgbe_read_mmc_stats(pdata);
1038
1039                 for (i = 0; i < AXGBE_XSTATS_COUNT; i++) {
1040                         values[i] = *(u64 *)((uint8_t *)&pdata->mmc_stats +
1041                                         axgbe_xstats_strings[i].offset);
1042                 }
1043
1044                 return i;
1045         }
1046
1047         axgbe_dev_xstats_get_by_id(dev, NULL, values_copy, AXGBE_XSTATS_COUNT);
1048
1049         for (i = 0; i < n; i++) {
1050                 if (ids[i] >= AXGBE_XSTATS_COUNT) {
1051                         PMD_DRV_LOG(ERR, "id value isn't valid\n");
1052                         return -1;
1053                 }
1054                 values[i] = values_copy[ids[i]];
1055         }
1056         return n;
1057 }
1058
1059 static int
1060 axgbe_dev_xstats_get_names_by_id(struct rte_eth_dev *dev,
1061                                  struct rte_eth_xstat_name *xstats_names,
1062                                  const uint64_t *ids,
1063                                  unsigned int size)
1064 {
1065         struct rte_eth_xstat_name xstats_names_copy[AXGBE_XSTATS_COUNT];
1066         unsigned int i;
1067
1068         if (!ids)
1069                 return axgbe_dev_xstats_get_names(dev, xstats_names, size);
1070
1071         axgbe_dev_xstats_get_names(dev, xstats_names_copy, size);
1072
1073         for (i = 0; i < size; i++) {
1074                 if (ids[i] >= AXGBE_XSTATS_COUNT) {
1075                         PMD_DRV_LOG(ERR, "id value isn't valid\n");
1076                         return -1;
1077                 }
1078                 strcpy(xstats_names[i].name, xstats_names_copy[ids[i]].name);
1079         }
1080         return size;
1081 }
1082
1083 static int
1084 axgbe_dev_xstats_reset(struct rte_eth_dev *dev)
1085 {
1086         struct axgbe_port *pdata = dev->data->dev_private;
1087         struct axgbe_mmc_stats *stats = &pdata->mmc_stats;
1088
1089         /* MMC registers are configured for reset on read */
1090         axgbe_read_mmc_stats(pdata);
1091
1092         /* Reset stats */
1093         memset(stats, 0, sizeof(*stats));
1094
1095         return 0;
1096 }
1097
1098 static int
1099 axgbe_dev_stats_get(struct rte_eth_dev *dev,
1100                     struct rte_eth_stats *stats)
1101 {
1102         struct axgbe_rx_queue *rxq;
1103         struct axgbe_tx_queue *txq;
1104         struct axgbe_port *pdata = dev->data->dev_private;
1105         struct axgbe_mmc_stats *mmc_stats = &pdata->mmc_stats;
1106         unsigned int i;
1107
1108         axgbe_read_mmc_stats(pdata);
1109
1110         stats->imissed = mmc_stats->rxfifooverflow;
1111
1112         for (i = 0; i < dev->data->nb_rx_queues; i++) {
1113                 rxq = dev->data->rx_queues[i];
1114                 stats->q_ipackets[i] = rxq->pkts;
1115                 stats->ipackets += rxq->pkts;
1116                 stats->q_ibytes[i] = rxq->bytes;
1117                 stats->ibytes += rxq->bytes;
1118                 stats->rx_nombuf += rxq->rx_mbuf_alloc_failed;
1119                 stats->q_errors[i] = rxq->errors + rxq->rx_mbuf_alloc_failed;
1120                 stats->ierrors += rxq->errors;
1121         }
1122
1123         for (i = 0; i < dev->data->nb_tx_queues; i++) {
1124                 txq = dev->data->tx_queues[i];
1125                 stats->q_opackets[i] = txq->pkts;
1126                 stats->opackets += txq->pkts;
1127                 stats->q_obytes[i] = txq->bytes;
1128                 stats->obytes += txq->bytes;
1129                 stats->oerrors += txq->errors;
1130         }
1131
1132         return 0;
1133 }
1134
1135 static int
1136 axgbe_dev_stats_reset(struct rte_eth_dev *dev)
1137 {
1138         struct axgbe_rx_queue *rxq;
1139         struct axgbe_tx_queue *txq;
1140         unsigned int i;
1141
1142         for (i = 0; i < dev->data->nb_rx_queues; i++) {
1143                 rxq = dev->data->rx_queues[i];
1144                 rxq->pkts = 0;
1145                 rxq->bytes = 0;
1146                 rxq->errors = 0;
1147                 rxq->rx_mbuf_alloc_failed = 0;
1148         }
1149         for (i = 0; i < dev->data->nb_tx_queues; i++) {
1150                 txq = dev->data->tx_queues[i];
1151                 txq->pkts = 0;
1152                 txq->bytes = 0;
1153                 txq->errors = 0;
1154         }
1155
1156         return 0;
1157 }
1158
1159 static int
1160 axgbe_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
1161 {
1162         struct axgbe_port *pdata = dev->data->dev_private;
1163
1164         dev_info->max_rx_queues = pdata->rx_ring_count;
1165         dev_info->max_tx_queues = pdata->tx_ring_count;
1166         dev_info->min_rx_bufsize = AXGBE_RX_MIN_BUF_SIZE;
1167         dev_info->max_rx_pktlen = AXGBE_RX_MAX_BUF_SIZE;
1168         dev_info->max_mac_addrs = pdata->hw_feat.addn_mac + 1;
1169         dev_info->max_hash_mac_addrs = pdata->hw_feat.hash_table_size;
1170         dev_info->speed_capa =  ETH_LINK_SPEED_10G;
1171
1172         dev_info->rx_offload_capa =
1173                 DEV_RX_OFFLOAD_IPV4_CKSUM |
1174                 DEV_RX_OFFLOAD_UDP_CKSUM  |
1175                 DEV_RX_OFFLOAD_TCP_CKSUM  |
1176                 DEV_RX_OFFLOAD_JUMBO_FRAME      |
1177                 DEV_RX_OFFLOAD_SCATTER    |
1178                 DEV_RX_OFFLOAD_KEEP_CRC;
1179
1180         dev_info->tx_offload_capa =
1181                 DEV_TX_OFFLOAD_IPV4_CKSUM  |
1182                 DEV_TX_OFFLOAD_UDP_CKSUM   |
1183                 DEV_TX_OFFLOAD_TCP_CKSUM;
1184
1185         if (pdata->hw_feat.rss) {
1186                 dev_info->flow_type_rss_offloads = AXGBE_RSS_OFFLOAD;
1187                 dev_info->reta_size = pdata->hw_feat.hash_table_size;
1188                 dev_info->hash_key_size =  AXGBE_RSS_HASH_KEY_SIZE;
1189         }
1190
1191         dev_info->rx_desc_lim = rx_desc_lim;
1192         dev_info->tx_desc_lim = tx_desc_lim;
1193
1194         dev_info->default_rxconf = (struct rte_eth_rxconf) {
1195                 .rx_free_thresh = AXGBE_RX_FREE_THRESH,
1196         };
1197
1198         dev_info->default_txconf = (struct rte_eth_txconf) {
1199                 .tx_free_thresh = AXGBE_TX_FREE_THRESH,
1200         };
1201
1202         return 0;
1203 }
1204
1205 static int
1206 axgbe_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
1207 {
1208         struct axgbe_port *pdata = dev->data->dev_private;
1209         struct xgbe_fc_info fc = pdata->fc;
1210         unsigned int reg, reg_val = 0;
1211
1212         reg = MAC_Q0TFCR;
1213         reg_val = AXGMAC_IOREAD(pdata, reg);
1214         fc.low_water[0] =  AXGMAC_MTL_IOREAD_BITS(pdata, 0, MTL_Q_RQFCR, RFA);
1215         fc.high_water[0] =  AXGMAC_MTL_IOREAD_BITS(pdata, 0, MTL_Q_RQFCR, RFD);
1216         fc.pause_time[0] = AXGMAC_GET_BITS(reg_val, MAC_Q0TFCR, PT);
1217         fc.autoneg = pdata->pause_autoneg;
1218
1219         if (pdata->rx_pause && pdata->tx_pause)
1220                 fc.mode = RTE_FC_FULL;
1221         else if (pdata->rx_pause)
1222                 fc.mode = RTE_FC_RX_PAUSE;
1223         else if (pdata->tx_pause)
1224                 fc.mode = RTE_FC_TX_PAUSE;
1225         else
1226                 fc.mode = RTE_FC_NONE;
1227
1228         fc_conf->high_water =  (1024 + (fc.low_water[0] << 9)) / 1024;
1229         fc_conf->low_water =  (1024 + (fc.high_water[0] << 9)) / 1024;
1230         fc_conf->pause_time = fc.pause_time[0];
1231         fc_conf->send_xon = fc.send_xon;
1232         fc_conf->mode = fc.mode;
1233
1234         return 0;
1235 }
1236
1237 static int
1238 axgbe_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
1239 {
1240         struct axgbe_port *pdata = dev->data->dev_private;
1241         struct xgbe_fc_info fc = pdata->fc;
1242         unsigned int reg, reg_val = 0;
1243         reg = MAC_Q0TFCR;
1244
1245         pdata->pause_autoneg = fc_conf->autoneg;
1246         pdata->phy.pause_autoneg = pdata->pause_autoneg;
1247         fc.send_xon = fc_conf->send_xon;
1248         AXGMAC_MTL_IOWRITE_BITS(pdata, 0, MTL_Q_RQFCR, RFA,
1249                         AXGMAC_FLOW_CONTROL_VALUE(1024 * fc_conf->high_water));
1250         AXGMAC_MTL_IOWRITE_BITS(pdata, 0, MTL_Q_RQFCR, RFD,
1251                         AXGMAC_FLOW_CONTROL_VALUE(1024 * fc_conf->low_water));
1252         AXGMAC_SET_BITS(reg_val, MAC_Q0TFCR, PT, fc_conf->pause_time);
1253         AXGMAC_IOWRITE(pdata, reg, reg_val);
1254         fc.mode = fc_conf->mode;
1255
1256         if (fc.mode == RTE_FC_FULL) {
1257                 pdata->tx_pause = 1;
1258                 pdata->rx_pause = 1;
1259         } else if (fc.mode == RTE_FC_RX_PAUSE) {
1260                 pdata->tx_pause = 0;
1261                 pdata->rx_pause = 1;
1262         } else if (fc.mode == RTE_FC_TX_PAUSE) {
1263                 pdata->tx_pause = 1;
1264                 pdata->rx_pause = 0;
1265         } else {
1266                 pdata->tx_pause = 0;
1267                 pdata->rx_pause = 0;
1268         }
1269
1270         if (pdata->tx_pause != (unsigned int)pdata->phy.tx_pause)
1271                 pdata->hw_if.config_tx_flow_control(pdata);
1272
1273         if (pdata->rx_pause != (unsigned int)pdata->phy.rx_pause)
1274                 pdata->hw_if.config_rx_flow_control(pdata);
1275
1276         pdata->hw_if.config_flow_control(pdata);
1277         pdata->phy.tx_pause = pdata->tx_pause;
1278         pdata->phy.rx_pause = pdata->rx_pause;
1279
1280         return 0;
1281 }
1282
1283 static int
1284 axgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev,
1285                 struct rte_eth_pfc_conf *pfc_conf)
1286 {
1287         struct axgbe_port *pdata = dev->data->dev_private;
1288         struct xgbe_fc_info fc = pdata->fc;
1289         uint8_t tc_num;
1290
1291         tc_num = pdata->pfc_map[pfc_conf->priority];
1292
1293         if (pfc_conf->priority >= pdata->hw_feat.tc_cnt) {
1294                 PMD_INIT_LOG(ERR, "Max supported  traffic class: %d\n",
1295                                 pdata->hw_feat.tc_cnt);
1296         return -EINVAL;
1297         }
1298
1299         pdata->pause_autoneg = pfc_conf->fc.autoneg;
1300         pdata->phy.pause_autoneg = pdata->pause_autoneg;
1301         fc.send_xon = pfc_conf->fc.send_xon;
1302         AXGMAC_MTL_IOWRITE_BITS(pdata, tc_num, MTL_Q_RQFCR, RFA,
1303                 AXGMAC_FLOW_CONTROL_VALUE(1024 * pfc_conf->fc.high_water));
1304         AXGMAC_MTL_IOWRITE_BITS(pdata, tc_num, MTL_Q_RQFCR, RFD,
1305                 AXGMAC_FLOW_CONTROL_VALUE(1024 * pfc_conf->fc.low_water));
1306
1307         switch (tc_num) {
1308         case 0:
1309                 AXGMAC_IOWRITE_BITS(pdata, MTL_TCPM0R,
1310                                 PSTC0, pfc_conf->fc.pause_time);
1311                 break;
1312         case 1:
1313                 AXGMAC_IOWRITE_BITS(pdata, MTL_TCPM0R,
1314                                 PSTC1, pfc_conf->fc.pause_time);
1315                 break;
1316         case 2:
1317                 AXGMAC_IOWRITE_BITS(pdata, MTL_TCPM0R,
1318                                 PSTC2, pfc_conf->fc.pause_time);
1319                 break;
1320         case 3:
1321                 AXGMAC_IOWRITE_BITS(pdata, MTL_TCPM0R,
1322                                 PSTC3, pfc_conf->fc.pause_time);
1323                 break;
1324         case 4:
1325                 AXGMAC_IOWRITE_BITS(pdata, MTL_TCPM1R,
1326                                 PSTC4, pfc_conf->fc.pause_time);
1327                 break;
1328         case 5:
1329                 AXGMAC_IOWRITE_BITS(pdata, MTL_TCPM1R,
1330                                 PSTC5, pfc_conf->fc.pause_time);
1331                 break;
1332         case 7:
1333                 AXGMAC_IOWRITE_BITS(pdata, MTL_TCPM1R,
1334                                 PSTC6, pfc_conf->fc.pause_time);
1335                 break;
1336         case 6:
1337                 AXGMAC_IOWRITE_BITS(pdata, MTL_TCPM1R,
1338                                 PSTC7, pfc_conf->fc.pause_time);
1339                 break;
1340         }
1341
1342         fc.mode = pfc_conf->fc.mode;
1343
1344         if (fc.mode == RTE_FC_FULL) {
1345                 pdata->tx_pause = 1;
1346                 pdata->rx_pause = 1;
1347                 AXGMAC_IOWRITE_BITS(pdata, MAC_RFCR, PFCE, 1);
1348         } else if (fc.mode == RTE_FC_RX_PAUSE) {
1349                 pdata->tx_pause = 0;
1350                 pdata->rx_pause = 1;
1351                 AXGMAC_IOWRITE_BITS(pdata, MAC_RFCR, PFCE, 1);
1352         } else if (fc.mode == RTE_FC_TX_PAUSE) {
1353                 pdata->tx_pause = 1;
1354                 pdata->rx_pause = 0;
1355                 AXGMAC_IOWRITE_BITS(pdata, MAC_RFCR, PFCE, 0);
1356         } else {
1357                 pdata->tx_pause = 0;
1358                 pdata->rx_pause = 0;
1359                 AXGMAC_IOWRITE_BITS(pdata, MAC_RFCR, PFCE, 0);
1360         }
1361
1362         if (pdata->tx_pause != (unsigned int)pdata->phy.tx_pause)
1363                 pdata->hw_if.config_tx_flow_control(pdata);
1364
1365         if (pdata->rx_pause != (unsigned int)pdata->phy.rx_pause)
1366                 pdata->hw_if.config_rx_flow_control(pdata);
1367         pdata->hw_if.config_flow_control(pdata);
1368         pdata->phy.tx_pause = pdata->tx_pause;
1369         pdata->phy.rx_pause = pdata->rx_pause;
1370
1371         return 0;
1372 }
1373
1374 void
1375 axgbe_rxq_info_get(struct rte_eth_dev *dev, uint16_t queue_id,
1376         struct rte_eth_rxq_info *qinfo)
1377 {
1378         struct   axgbe_rx_queue *rxq;
1379
1380         rxq = dev->data->rx_queues[queue_id];
1381         qinfo->mp = rxq->mb_pool;
1382         qinfo->scattered_rx = dev->data->scattered_rx;
1383         qinfo->nb_desc = rxq->nb_desc;
1384         qinfo->conf.rx_free_thresh = rxq->free_thresh;
1385 }
1386
1387 void
1388 axgbe_txq_info_get(struct rte_eth_dev *dev, uint16_t queue_id,
1389         struct rte_eth_txq_info *qinfo)
1390 {
1391         struct  axgbe_tx_queue *txq;
1392
1393         txq = dev->data->tx_queues[queue_id];
1394         qinfo->nb_desc = txq->nb_desc;
1395         qinfo->conf.tx_free_thresh = txq->free_thresh;
1396 }
1397 const uint32_t *
1398 axgbe_dev_supported_ptypes_get(struct rte_eth_dev *dev)
1399 {
1400         static const uint32_t ptypes[] = {
1401                 RTE_PTYPE_L2_ETHER,
1402                 RTE_PTYPE_L2_ETHER_TIMESYNC,
1403                 RTE_PTYPE_L2_ETHER_LLDP,
1404                 RTE_PTYPE_L2_ETHER_ARP,
1405                 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN,
1406                 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN,
1407                 RTE_PTYPE_L4_FRAG,
1408                 RTE_PTYPE_L4_ICMP,
1409                 RTE_PTYPE_L4_NONFRAG,
1410                 RTE_PTYPE_L4_SCTP,
1411                 RTE_PTYPE_L4_TCP,
1412                 RTE_PTYPE_L4_UDP,
1413                 RTE_PTYPE_TUNNEL_GRENAT,
1414                 RTE_PTYPE_TUNNEL_IP,
1415                 RTE_PTYPE_INNER_L2_ETHER,
1416                 RTE_PTYPE_INNER_L2_ETHER_VLAN,
1417                 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN,
1418                 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN,
1419                 RTE_PTYPE_INNER_L4_FRAG,
1420                 RTE_PTYPE_INNER_L4_ICMP,
1421                 RTE_PTYPE_INNER_L4_NONFRAG,
1422                 RTE_PTYPE_INNER_L4_SCTP,
1423                 RTE_PTYPE_INNER_L4_TCP,
1424                 RTE_PTYPE_INNER_L4_UDP,
1425                 RTE_PTYPE_UNKNOWN
1426         };
1427
1428         if (dev->rx_pkt_burst == axgbe_recv_pkts)
1429                 return ptypes;
1430         return NULL;
1431 }
1432
1433 static int axgb_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
1434 {
1435         struct rte_eth_dev_info dev_info;
1436         struct axgbe_port *pdata = dev->data->dev_private;
1437         uint32_t frame_size = mtu + RTE_ETHER_HDR_LEN + RTE_ETHER_CRC_LEN;
1438         unsigned int val = 0;
1439         axgbe_dev_info_get(dev, &dev_info);
1440         /* check that mtu is within the allowed range */
1441         if (mtu < RTE_ETHER_MIN_MTU || frame_size > dev_info.max_rx_pktlen)
1442                 return -EINVAL;
1443         /* mtu setting is forbidden if port is start */
1444         if (dev->data->dev_started) {
1445                 PMD_DRV_LOG(ERR, "port %d must be stopped before configuration",
1446                                 dev->data->port_id);
1447                 return -EBUSY;
1448         }
1449         if (frame_size > RTE_ETHER_MAX_LEN) {
1450                 dev->data->dev_conf.rxmode.offloads |=
1451                         DEV_RX_OFFLOAD_JUMBO_FRAME;
1452                 val = 1;
1453         } else {
1454                 dev->data->dev_conf.rxmode.offloads &=
1455                         ~DEV_RX_OFFLOAD_JUMBO_FRAME;
1456                 val = 0;
1457         }
1458         AXGMAC_IOWRITE_BITS(pdata, MAC_RCR, JE, val);
1459         dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
1460         return 0;
1461 }
1462
1463 static void
1464 axgbe_update_tstamp_time(struct axgbe_port *pdata,
1465                 unsigned int sec, unsigned int nsec, int addsub)
1466 {
1467         unsigned int count = 100;
1468         uint32_t sub_val = 0;
1469         uint32_t sub_val_sec = 0xFFFFFFFF;
1470         uint32_t sub_val_nsec = 0x3B9ACA00;
1471
1472         if (addsub) {
1473                 if (sec)
1474                         sub_val = sub_val_sec - (sec - 1);
1475                 else
1476                         sub_val = sec;
1477
1478                 AXGMAC_IOWRITE(pdata, MAC_STSUR, sub_val);
1479                 sub_val = sub_val_nsec - nsec;
1480                 AXGMAC_IOWRITE(pdata, MAC_STNUR, sub_val);
1481                 AXGMAC_IOWRITE_BITS(pdata, MAC_STNUR, ADDSUB, 1);
1482         } else {
1483                 AXGMAC_IOWRITE(pdata, MAC_STSUR, sec);
1484                 AXGMAC_IOWRITE_BITS(pdata, MAC_STNUR, ADDSUB, 0);
1485                 AXGMAC_IOWRITE(pdata, MAC_STNUR, nsec);
1486         }
1487         AXGMAC_IOWRITE_BITS(pdata, MAC_TSCR, TSUPDT, 1);
1488         /* Wait for time update to complete */
1489         while (--count && AXGMAC_IOREAD_BITS(pdata, MAC_TSCR, TSUPDT))
1490                 rte_delay_ms(1);
1491 }
1492
1493 static inline uint64_t
1494 div_u64_rem(uint64_t dividend, uint32_t divisor, uint32_t *remainder)
1495 {
1496         *remainder = dividend % divisor;
1497         return dividend / divisor;
1498 }
1499
1500 static inline uint64_t
1501 div_u64(uint64_t dividend, uint32_t divisor)
1502 {
1503         uint32_t remainder;
1504         return div_u64_rem(dividend, divisor, &remainder);
1505 }
1506
1507 static int
1508 axgbe_adjfreq(struct axgbe_port *pdata, int64_t delta)
1509 {
1510         uint64_t adjust;
1511         uint32_t addend, diff;
1512         unsigned int neg_adjust = 0;
1513
1514         if (delta < 0) {
1515                 neg_adjust = 1;
1516                 delta = -delta;
1517         }
1518         adjust = (uint64_t)pdata->tstamp_addend;
1519         adjust *= delta;
1520         diff = (uint32_t)div_u64(adjust, 1000000000UL);
1521         addend = (neg_adjust) ? pdata->tstamp_addend - diff :
1522                                 pdata->tstamp_addend + diff;
1523         pdata->tstamp_addend = addend;
1524         axgbe_update_tstamp_addend(pdata, addend);
1525         return 0;
1526 }
1527
1528 static int
1529 axgbe_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
1530 {
1531         struct axgbe_port *pdata = dev->data->dev_private;
1532         struct timespec timestamp_delta;
1533
1534         axgbe_adjfreq(pdata, delta);
1535         pdata->systime_tc.nsec += delta;
1536
1537         if (delta < 0) {
1538                 delta = -delta;
1539                 timestamp_delta = rte_ns_to_timespec(delta);
1540                 axgbe_update_tstamp_time(pdata, timestamp_delta.tv_sec,
1541                                 timestamp_delta.tv_nsec, 1);
1542         } else {
1543                 timestamp_delta = rte_ns_to_timespec(delta);
1544                 axgbe_update_tstamp_time(pdata, timestamp_delta.tv_sec,
1545                                 timestamp_delta.tv_nsec, 0);
1546         }
1547         return 0;
1548 }
1549
1550 static int
1551 axgbe_timesync_read_time(struct rte_eth_dev *dev,
1552                 struct timespec *timestamp)
1553 {
1554         uint64_t nsec;
1555         struct axgbe_port *pdata = dev->data->dev_private;
1556
1557         nsec = AXGMAC_IOREAD(pdata, MAC_STSR);
1558         nsec *= NSEC_PER_SEC;
1559         nsec += AXGMAC_IOREAD(pdata, MAC_STNR);
1560         *timestamp = rte_ns_to_timespec(nsec);
1561         return 0;
1562 }
1563 static int
1564 axgbe_timesync_write_time(struct rte_eth_dev *dev,
1565                                     const struct timespec *timestamp)
1566 {
1567         unsigned int count = 100;
1568         struct axgbe_port *pdata = dev->data->dev_private;
1569
1570         AXGMAC_IOWRITE(pdata, MAC_STSUR, timestamp->tv_sec);
1571         AXGMAC_IOWRITE(pdata, MAC_STNUR, timestamp->tv_nsec);
1572         AXGMAC_IOWRITE_BITS(pdata, MAC_TSCR, TSUPDT, 1);
1573         /* Wait for time update to complete */
1574         while (--count && AXGMAC_IOREAD_BITS(pdata, MAC_TSCR, TSUPDT))
1575                 rte_delay_ms(1);
1576         if (!count)
1577                 PMD_DRV_LOG(ERR, "Timed out update timestamp\n");
1578         return 0;
1579 }
1580
1581 static void
1582 axgbe_update_tstamp_addend(struct axgbe_port *pdata,
1583                 uint32_t addend)
1584 {
1585         unsigned int count = 100;
1586
1587         AXGMAC_IOWRITE(pdata, MAC_TSAR, addend);
1588         AXGMAC_IOWRITE_BITS(pdata, MAC_TSCR, TSADDREG, 1);
1589
1590         /* Wait for addend update to complete */
1591         while (--count && AXGMAC_IOREAD_BITS(pdata, MAC_TSCR, TSADDREG))
1592                 rte_delay_ms(1);
1593         if (!count)
1594                 PMD_DRV_LOG(ERR, "Timed out updating timestamp addend register\n");
1595 }
1596
1597 static void
1598 axgbe_set_tstamp_time(struct axgbe_port *pdata, unsigned int sec,
1599                 unsigned int nsec)
1600 {
1601         unsigned int count = 100;
1602
1603         /*System Time Sec Update*/
1604         AXGMAC_IOWRITE(pdata, MAC_STSUR, sec);
1605         /*System Time nanoSec Update*/
1606         AXGMAC_IOWRITE(pdata, MAC_STNUR, nsec);
1607         /*Initialize Timestamp*/
1608         AXGMAC_IOWRITE_BITS(pdata, MAC_TSCR, TSINIT, 1);
1609
1610         /* Wait for time update to complete */
1611         while (--count && AXGMAC_IOREAD_BITS(pdata, MAC_TSCR, TSINIT))
1612                 rte_delay_ms(1);
1613         if (!count)
1614                 PMD_DRV_LOG(ERR, "Timed out initializing timestamp\n");
1615 }
1616
1617 static int
1618 axgbe_timesync_enable(struct rte_eth_dev *dev)
1619 {
1620         struct axgbe_port *pdata = dev->data->dev_private;
1621         unsigned int mac_tscr = 0;
1622         uint64_t dividend;
1623         struct timespec timestamp;
1624         uint64_t nsec;
1625
1626         /* Set one nano-second accuracy */
1627         AXGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSCTRLSSR, 1);
1628
1629         /* Set fine timestamp update */
1630         AXGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSCFUPDT, 1);
1631
1632         /* Overwrite earlier timestamps */
1633         AXGMAC_SET_BITS(mac_tscr, MAC_TSCR, TXTSSTSM, 1);
1634
1635         AXGMAC_IOWRITE(pdata, MAC_TSCR, mac_tscr);
1636
1637         /* Enabling processing of ptp over eth pkt */
1638         AXGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSIPENA, 1);
1639         AXGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSVER2ENA, 1);
1640         /* Enable timestamp for all pkts*/
1641         AXGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSENALL, 1);
1642
1643         /* enabling timestamp */
1644         AXGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSENA, 1);
1645         AXGMAC_IOWRITE(pdata, MAC_TSCR, mac_tscr);
1646
1647         /* Exit if timestamping is not enabled */
1648         if (!AXGMAC_GET_BITS(mac_tscr, MAC_TSCR, TSENA)) {
1649                 PMD_DRV_LOG(ERR, "Exiting as timestamp is not enabled\n");
1650                 return 0;
1651         }
1652
1653         /* Sub-second Increment Value*/
1654         AXGMAC_IOWRITE_BITS(pdata, MAC_SSIR, SSINC, AXGBE_TSTAMP_SSINC);
1655         /* Sub-nanosecond Increment Value */
1656         AXGMAC_IOWRITE_BITS(pdata, MAC_SSIR, SNSINC, AXGBE_TSTAMP_SNSINC);
1657
1658         pdata->ptpclk_rate = AXGBE_V2_PTP_CLOCK_FREQ;
1659         dividend = 50000000;
1660         dividend <<= 32;
1661         pdata->tstamp_addend = div_u64(dividend, pdata->ptpclk_rate);
1662
1663         axgbe_update_tstamp_addend(pdata, pdata->tstamp_addend);
1664         axgbe_set_tstamp_time(pdata, 0, 0);
1665
1666         /* Initialize the timecounter */
1667         memset(&pdata->systime_tc, 0, sizeof(struct rte_timecounter));
1668
1669         pdata->systime_tc.cc_mask = AXGBE_CYCLECOUNTER_MASK;
1670         pdata->systime_tc.cc_shift = 0;
1671         pdata->systime_tc.nsec_mask = 0;
1672
1673         PMD_DRV_LOG(DEBUG, "Initializing system time counter with realtime\n");
1674
1675         /* Updating the counter once with clock real time */
1676         clock_gettime(CLOCK_REALTIME, &timestamp);
1677         nsec = rte_timespec_to_ns(&timestamp);
1678         nsec = rte_timecounter_update(&pdata->systime_tc, nsec);
1679         axgbe_set_tstamp_time(pdata, timestamp.tv_sec, timestamp.tv_nsec);
1680         return 0;
1681 }
1682
1683 static int
1684 axgbe_timesync_disable(struct rte_eth_dev *dev)
1685 {
1686         struct axgbe_port *pdata = dev->data->dev_private;
1687         unsigned int mac_tscr = 0;
1688
1689         /*disable timestamp for all pkts*/
1690         AXGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSENALL, 0);
1691         /*disable the addened register*/
1692         AXGMAC_IOWRITE_BITS(pdata, MAC_TSCR, TSADDREG, 0);
1693         /* disable timestamp update */
1694         AXGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSCFUPDT, 0);
1695         /*disable time stamp*/
1696         AXGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSENA, 0);
1697         return 0;
1698 }
1699
1700 static int
1701 axgbe_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
1702                                 struct timespec *timestamp, uint32_t flags)
1703 {
1704         uint64_t nsec = 0;
1705         volatile union axgbe_rx_desc *desc;
1706         uint16_t idx, pmt;
1707         struct axgbe_rx_queue *rxq = *dev->data->rx_queues;
1708
1709         idx = AXGBE_GET_DESC_IDX(rxq, rxq->cur);
1710         desc = &rxq->desc[idx];
1711
1712         while (AXGMAC_GET_BITS_LE(desc->write.desc3, RX_NORMAL_DESC3, OWN))
1713                 rte_delay_ms(1);
1714         if (AXGMAC_GET_BITS_LE(desc->write.desc3, RX_NORMAL_DESC3, CTXT)) {
1715                 if (AXGMAC_GET_BITS_LE(desc->write.desc3, RX_CONTEXT_DESC3, TSA) &&
1716                                 !AXGMAC_GET_BITS_LE(desc->write.desc3,
1717                                         RX_CONTEXT_DESC3, TSD)) {
1718                         pmt = AXGMAC_GET_BITS_LE(desc->write.desc3,
1719                                         RX_CONTEXT_DESC3, PMT);
1720                         nsec = rte_le_to_cpu_32(desc->write.desc1);
1721                         nsec *= NSEC_PER_SEC;
1722                         nsec += rte_le_to_cpu_32(desc->write.desc0);
1723                         if (nsec != 0xffffffffffffffffULL) {
1724                                 if (pmt == 0x01)
1725                                         *timestamp = rte_ns_to_timespec(nsec);
1726                                 PMD_DRV_LOG(DEBUG,
1727                                         "flags = 0x%x nsec = %"PRIu64"\n",
1728                                         flags, nsec);
1729                         }
1730                 }
1731         }
1732
1733         return 0;
1734 }
1735
1736 static int
1737 axgbe_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
1738                                 struct timespec *timestamp)
1739 {
1740         uint64_t nsec;
1741         struct axgbe_port *pdata = dev->data->dev_private;
1742         unsigned int tx_snr, tx_ssr;
1743
1744         rte_delay_us(5);
1745         if (pdata->vdata->tx_tstamp_workaround) {
1746                 tx_snr = AXGMAC_IOREAD(pdata, MAC_TXSNR);
1747                 tx_ssr = AXGMAC_IOREAD(pdata, MAC_TXSSR);
1748
1749         } else {
1750                 tx_ssr = AXGMAC_IOREAD(pdata, MAC_TXSSR);
1751                 tx_snr = AXGMAC_IOREAD(pdata, MAC_TXSNR);
1752         }
1753         if (AXGMAC_GET_BITS(tx_snr, MAC_TXSNR, TXTSSTSMIS)) {
1754                 PMD_DRV_LOG(DEBUG, "Waiting for TXTSSTSMIS\n");
1755                 return 0;
1756         }
1757         nsec = tx_ssr;
1758         nsec *= NSEC_PER_SEC;
1759         nsec += tx_snr;
1760         PMD_DRV_LOG(DEBUG, "nsec = %"PRIu64" tx_ssr = %d tx_snr = %d\n",
1761                         nsec, tx_ssr, tx_snr);
1762         *timestamp = rte_ns_to_timespec(nsec);
1763         return 0;
1764 }
1765
1766 static void axgbe_get_all_hw_features(struct axgbe_port *pdata)
1767 {
1768         unsigned int mac_hfr0, mac_hfr1, mac_hfr2;
1769         struct axgbe_hw_features *hw_feat = &pdata->hw_feat;
1770
1771         mac_hfr0 = AXGMAC_IOREAD(pdata, MAC_HWF0R);
1772         mac_hfr1 = AXGMAC_IOREAD(pdata, MAC_HWF1R);
1773         mac_hfr2 = AXGMAC_IOREAD(pdata, MAC_HWF2R);
1774
1775         memset(hw_feat, 0, sizeof(*hw_feat));
1776
1777         hw_feat->version = AXGMAC_IOREAD(pdata, MAC_VR);
1778
1779         /* Hardware feature register 0 */
1780         hw_feat->gmii        = AXGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, GMIISEL);
1781         hw_feat->vlhash      = AXGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, VLHASH);
1782         hw_feat->sma         = AXGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, SMASEL);
1783         hw_feat->rwk         = AXGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, RWKSEL);
1784         hw_feat->mgk         = AXGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, MGKSEL);
1785         hw_feat->mmc         = AXGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, MMCSEL);
1786         hw_feat->aoe         = AXGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, ARPOFFSEL);
1787         hw_feat->ts          = AXGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, TSSEL);
1788         hw_feat->eee         = AXGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, EEESEL);
1789         hw_feat->tx_coe      = AXGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, TXCOESEL);
1790         hw_feat->rx_coe      = AXGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, RXCOESEL);
1791         hw_feat->addn_mac    = AXGMAC_GET_BITS(mac_hfr0, MAC_HWF0R,
1792                                               ADDMACADRSEL);
1793         hw_feat->ts_src      = AXGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, TSSTSSEL);
1794         hw_feat->sa_vlan_ins = AXGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, SAVLANINS);
1795
1796         /* Hardware feature register 1 */
1797         hw_feat->rx_fifo_size  = AXGMAC_GET_BITS(mac_hfr1, MAC_HWF1R,
1798                                                 RXFIFOSIZE);
1799         hw_feat->tx_fifo_size  = AXGMAC_GET_BITS(mac_hfr1, MAC_HWF1R,
1800                                                 TXFIFOSIZE);
1801         hw_feat->adv_ts_hi     = AXGMAC_GET_BITS(mac_hfr1,
1802                                                  MAC_HWF1R, ADVTHWORD);
1803         hw_feat->dma_width     = AXGMAC_GET_BITS(mac_hfr1, MAC_HWF1R, ADDR64);
1804         hw_feat->dcb           = AXGMAC_GET_BITS(mac_hfr1, MAC_HWF1R, DCBEN);
1805         hw_feat->sph           = AXGMAC_GET_BITS(mac_hfr1, MAC_HWF1R, SPHEN);
1806         hw_feat->tso           = AXGMAC_GET_BITS(mac_hfr1, MAC_HWF1R, TSOEN);
1807         hw_feat->dma_debug     = AXGMAC_GET_BITS(mac_hfr1, MAC_HWF1R, DBGMEMA);
1808         hw_feat->rss           = AXGMAC_GET_BITS(mac_hfr1, MAC_HWF1R, RSSEN);
1809         hw_feat->tc_cnt        = AXGMAC_GET_BITS(mac_hfr1, MAC_HWF1R, NUMTC);
1810         hw_feat->hash_table_size = AXGMAC_GET_BITS(mac_hfr1, MAC_HWF1R,
1811                                                   HASHTBLSZ);
1812         hw_feat->l3l4_filter_num = AXGMAC_GET_BITS(mac_hfr1, MAC_HWF1R,
1813                                                   L3L4FNUM);
1814
1815         /* Hardware feature register 2 */
1816         hw_feat->rx_q_cnt     = AXGMAC_GET_BITS(mac_hfr2, MAC_HWF2R, RXQCNT);
1817         hw_feat->tx_q_cnt     = AXGMAC_GET_BITS(mac_hfr2, MAC_HWF2R, TXQCNT);
1818         hw_feat->rx_ch_cnt    = AXGMAC_GET_BITS(mac_hfr2, MAC_HWF2R, RXCHCNT);
1819         hw_feat->tx_ch_cnt    = AXGMAC_GET_BITS(mac_hfr2, MAC_HWF2R, TXCHCNT);
1820         hw_feat->pps_out_num  = AXGMAC_GET_BITS(mac_hfr2, MAC_HWF2R, PPSOUTNUM);
1821         hw_feat->aux_snap_num = AXGMAC_GET_BITS(mac_hfr2, MAC_HWF2R,
1822                                                 AUXSNAPNUM);
1823
1824         /* Translate the Hash Table size into actual number */
1825         switch (hw_feat->hash_table_size) {
1826         case 0:
1827                 break;
1828         case 1:
1829                 hw_feat->hash_table_size = 64;
1830                 break;
1831         case 2:
1832                 hw_feat->hash_table_size = 128;
1833                 break;
1834         case 3:
1835                 hw_feat->hash_table_size = 256;
1836                 break;
1837         }
1838
1839         /* Translate the address width setting into actual number */
1840         switch (hw_feat->dma_width) {
1841         case 0:
1842                 hw_feat->dma_width = 32;
1843                 break;
1844         case 1:
1845                 hw_feat->dma_width = 40;
1846                 break;
1847         case 2:
1848                 hw_feat->dma_width = 48;
1849                 break;
1850         default:
1851                 hw_feat->dma_width = 32;
1852         }
1853
1854         /* The Queue, Channel and TC counts are zero based so increment them
1855          * to get the actual number
1856          */
1857         hw_feat->rx_q_cnt++;
1858         hw_feat->tx_q_cnt++;
1859         hw_feat->rx_ch_cnt++;
1860         hw_feat->tx_ch_cnt++;
1861         hw_feat->tc_cnt++;
1862
1863         /* Translate the fifo sizes into actual numbers */
1864         hw_feat->rx_fifo_size = 1 << (hw_feat->rx_fifo_size + 7);
1865         hw_feat->tx_fifo_size = 1 << (hw_feat->tx_fifo_size + 7);
1866 }
1867
1868 static void axgbe_init_all_fptrs(struct axgbe_port *pdata)
1869 {
1870         axgbe_init_function_ptrs_dev(&pdata->hw_if);
1871         axgbe_init_function_ptrs_phy(&pdata->phy_if);
1872         axgbe_init_function_ptrs_i2c(&pdata->i2c_if);
1873         pdata->vdata->init_function_ptrs_phy_impl(&pdata->phy_if);
1874 }
1875
1876 static void axgbe_set_counts(struct axgbe_port *pdata)
1877 {
1878         /* Set all the function pointers */
1879         axgbe_init_all_fptrs(pdata);
1880
1881         /* Populate the hardware features */
1882         axgbe_get_all_hw_features(pdata);
1883
1884         /* Set default max values if not provided */
1885         if (!pdata->tx_max_channel_count)
1886                 pdata->tx_max_channel_count = pdata->hw_feat.tx_ch_cnt;
1887         if (!pdata->rx_max_channel_count)
1888                 pdata->rx_max_channel_count = pdata->hw_feat.rx_ch_cnt;
1889
1890         if (!pdata->tx_max_q_count)
1891                 pdata->tx_max_q_count = pdata->hw_feat.tx_q_cnt;
1892         if (!pdata->rx_max_q_count)
1893                 pdata->rx_max_q_count = pdata->hw_feat.rx_q_cnt;
1894
1895         /* Calculate the number of Tx and Rx rings to be created
1896          *  -Tx (DMA) Channels map 1-to-1 to Tx Queues so set
1897          *   the number of Tx queues to the number of Tx channels
1898          *   enabled
1899          *  -Rx (DMA) Channels do not map 1-to-1 so use the actual
1900          *   number of Rx queues or maximum allowed
1901          */
1902         pdata->tx_ring_count = RTE_MIN(pdata->hw_feat.tx_ch_cnt,
1903                                      pdata->tx_max_channel_count);
1904         pdata->tx_ring_count = RTE_MIN(pdata->tx_ring_count,
1905                                      pdata->tx_max_q_count);
1906
1907         pdata->tx_q_count = pdata->tx_ring_count;
1908
1909         pdata->rx_ring_count = RTE_MIN(pdata->hw_feat.rx_ch_cnt,
1910                                      pdata->rx_max_channel_count);
1911
1912         pdata->rx_q_count = RTE_MIN(pdata->hw_feat.rx_q_cnt,
1913                                   pdata->rx_max_q_count);
1914 }
1915
1916 static void axgbe_default_config(struct axgbe_port *pdata)
1917 {
1918         pdata->pblx8 = DMA_PBL_X8_ENABLE;
1919         pdata->tx_sf_mode = MTL_TSF_ENABLE;
1920         pdata->tx_threshold = MTL_TX_THRESHOLD_64;
1921         pdata->tx_pbl = DMA_PBL_32;
1922         pdata->tx_osp_mode = DMA_OSP_ENABLE;
1923         pdata->rx_sf_mode = MTL_RSF_ENABLE;
1924         pdata->rx_threshold = MTL_RX_THRESHOLD_64;
1925         pdata->rx_pbl = DMA_PBL_32;
1926         pdata->pause_autoneg = 1;
1927         pdata->tx_pause = 0;
1928         pdata->rx_pause = 0;
1929         pdata->phy_speed = SPEED_UNKNOWN;
1930         pdata->power_down = 0;
1931 }
1932
1933 static int
1934 pci_device_cmp(const struct rte_device *dev, const void *_pci_id)
1935 {
1936         const struct rte_pci_device *pdev = RTE_DEV_TO_PCI_CONST(dev);
1937         const struct rte_pci_id *pcid = _pci_id;
1938
1939         if (pdev->id.vendor_id == AMD_PCI_VENDOR_ID &&
1940                         pdev->id.device_id == pcid->device_id)
1941                 return 0;
1942         return 1;
1943 }
1944
1945 static bool
1946 pci_search_device(int device_id)
1947 {
1948         struct rte_bus *pci_bus;
1949         struct rte_pci_id dev_id;
1950
1951         dev_id.device_id = device_id;
1952         pci_bus = rte_bus_find_by_name("pci");
1953         return (pci_bus != NULL) &&
1954                 (pci_bus->find_device(NULL, pci_device_cmp, &dev_id) != NULL);
1955 }
1956
1957 /*
1958  * It returns 0 on success.
1959  */
1960 static int
1961 eth_axgbe_dev_init(struct rte_eth_dev *eth_dev)
1962 {
1963         PMD_INIT_FUNC_TRACE();
1964         struct axgbe_port *pdata;
1965         struct rte_pci_device *pci_dev;
1966         uint32_t reg, mac_lo, mac_hi;
1967         uint32_t len;
1968         int ret;
1969
1970         eth_dev->dev_ops = &axgbe_eth_dev_ops;
1971
1972         eth_dev->rx_descriptor_status = axgbe_dev_rx_descriptor_status;
1973         eth_dev->tx_descriptor_status = axgbe_dev_tx_descriptor_status;
1974
1975         /*
1976          * For secondary processes, we don't initialise any further as primary
1977          * has already done this work.
1978          */
1979         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1980                 return 0;
1981
1982         pdata = eth_dev->data->dev_private;
1983         /* initial state */
1984         rte_bit_relaxed_set32(AXGBE_DOWN, &pdata->dev_state);
1985         rte_bit_relaxed_set32(AXGBE_STOPPED, &pdata->dev_state);
1986         pdata->eth_dev = eth_dev;
1987
1988         pci_dev = RTE_DEV_TO_PCI(eth_dev->device);
1989         pdata->pci_dev = pci_dev;
1990
1991         /*
1992          * Use root complex device ID to differentiate RV AXGBE vs SNOWY AXGBE
1993          */
1994         if (pci_search_device(AMD_PCI_RV_ROOT_COMPLEX_ID)) {
1995                 pdata->xpcs_window_def_reg = PCS_V2_RV_WINDOW_DEF;
1996                 pdata->xpcs_window_sel_reg = PCS_V2_RV_WINDOW_SELECT;
1997         } else {
1998                 pdata->xpcs_window_def_reg = PCS_V2_WINDOW_DEF;
1999                 pdata->xpcs_window_sel_reg = PCS_V2_WINDOW_SELECT;
2000         }
2001
2002         pdata->xgmac_regs =
2003                 (void *)pci_dev->mem_resource[AXGBE_AXGMAC_BAR].addr;
2004         pdata->xprop_regs = (void *)((uint8_t *)pdata->xgmac_regs
2005                                      + AXGBE_MAC_PROP_OFFSET);
2006         pdata->xi2c_regs = (void *)((uint8_t *)pdata->xgmac_regs
2007                                     + AXGBE_I2C_CTRL_OFFSET);
2008         pdata->xpcs_regs = (void *)pci_dev->mem_resource[AXGBE_XPCS_BAR].addr;
2009
2010         /* version specific driver data*/
2011         if (pci_dev->id.device_id == AMD_PCI_AXGBE_DEVICE_V2A)
2012                 pdata->vdata = &axgbe_v2a;
2013         else
2014                 pdata->vdata = &axgbe_v2b;
2015
2016         /* Configure the PCS indirect addressing support */
2017         reg = XPCS32_IOREAD(pdata, pdata->xpcs_window_def_reg);
2018         pdata->xpcs_window = XPCS_GET_BITS(reg, PCS_V2_WINDOW_DEF, OFFSET);
2019         pdata->xpcs_window <<= 6;
2020         pdata->xpcs_window_size = XPCS_GET_BITS(reg, PCS_V2_WINDOW_DEF, SIZE);
2021         pdata->xpcs_window_size = 1 << (pdata->xpcs_window_size + 7);
2022         pdata->xpcs_window_mask = pdata->xpcs_window_size - 1;
2023
2024         PMD_INIT_LOG(DEBUG,
2025                      "xpcs window :%x, size :%x, mask :%x ", pdata->xpcs_window,
2026                      pdata->xpcs_window_size, pdata->xpcs_window_mask);
2027         XP_IOWRITE(pdata, XP_INT_EN, 0x1fffff);
2028
2029         /* Retrieve the MAC address */
2030         mac_lo = XP_IOREAD(pdata, XP_MAC_ADDR_LO);
2031         mac_hi = XP_IOREAD(pdata, XP_MAC_ADDR_HI);
2032         pdata->mac_addr.addr_bytes[0] = mac_lo & 0xff;
2033         pdata->mac_addr.addr_bytes[1] = (mac_lo >> 8) & 0xff;
2034         pdata->mac_addr.addr_bytes[2] = (mac_lo >> 16) & 0xff;
2035         pdata->mac_addr.addr_bytes[3] = (mac_lo >> 24) & 0xff;
2036         pdata->mac_addr.addr_bytes[4] = mac_hi & 0xff;
2037         pdata->mac_addr.addr_bytes[5] = (mac_hi >> 8)  &  0xff;
2038
2039         len = RTE_ETHER_ADDR_LEN * AXGBE_MAX_MAC_ADDRS;
2040         eth_dev->data->mac_addrs = rte_zmalloc("axgbe_mac_addr", len, 0);
2041
2042         if (!eth_dev->data->mac_addrs) {
2043                 PMD_INIT_LOG(ERR,
2044                              "Failed to alloc %u bytes needed to "
2045                              "store MAC addresses", len);
2046                 return -ENOMEM;
2047         }
2048
2049         /* Allocate memory for storing hash filter MAC addresses */
2050         len = RTE_ETHER_ADDR_LEN * AXGBE_MAX_HASH_MAC_ADDRS;
2051         eth_dev->data->hash_mac_addrs = rte_zmalloc("axgbe_hash_mac_addr",
2052                                                     len, 0);
2053
2054         if (eth_dev->data->hash_mac_addrs == NULL) {
2055                 PMD_INIT_LOG(ERR,
2056                              "Failed to allocate %d bytes needed to "
2057                              "store MAC addresses", len);
2058                 return -ENOMEM;
2059         }
2060
2061         if (!rte_is_valid_assigned_ether_addr(&pdata->mac_addr))
2062                 rte_eth_random_addr(pdata->mac_addr.addr_bytes);
2063
2064         /* Copy the permanent MAC address */
2065         rte_ether_addr_copy(&pdata->mac_addr, &eth_dev->data->mac_addrs[0]);
2066
2067         /* Clock settings */
2068         pdata->sysclk_rate = AXGBE_V2_DMA_CLOCK_FREQ;
2069         pdata->ptpclk_rate = AXGBE_V2_PTP_CLOCK_FREQ;
2070
2071         /* Set the DMA coherency values */
2072         pdata->coherent = 1;
2073         pdata->axdomain = AXGBE_DMA_OS_AXDOMAIN;
2074         pdata->arcache = AXGBE_DMA_OS_ARCACHE;
2075         pdata->awcache = AXGBE_DMA_OS_AWCACHE;
2076
2077         /* Set the maximum channels and queues */
2078         reg = XP_IOREAD(pdata, XP_PROP_1);
2079         pdata->tx_max_channel_count = XP_GET_BITS(reg, XP_PROP_1, MAX_TX_DMA);
2080         pdata->rx_max_channel_count = XP_GET_BITS(reg, XP_PROP_1, MAX_RX_DMA);
2081         pdata->tx_max_q_count = XP_GET_BITS(reg, XP_PROP_1, MAX_TX_QUEUES);
2082         pdata->rx_max_q_count = XP_GET_BITS(reg, XP_PROP_1, MAX_RX_QUEUES);
2083
2084         /* Set the hardware channel and queue counts */
2085         axgbe_set_counts(pdata);
2086
2087         /* Set the maximum fifo amounts */
2088         reg = XP_IOREAD(pdata, XP_PROP_2);
2089         pdata->tx_max_fifo_size = XP_GET_BITS(reg, XP_PROP_2, TX_FIFO_SIZE);
2090         pdata->tx_max_fifo_size *= 16384;
2091         pdata->tx_max_fifo_size = RTE_MIN(pdata->tx_max_fifo_size,
2092                                           pdata->vdata->tx_max_fifo_size);
2093         pdata->rx_max_fifo_size = XP_GET_BITS(reg, XP_PROP_2, RX_FIFO_SIZE);
2094         pdata->rx_max_fifo_size *= 16384;
2095         pdata->rx_max_fifo_size = RTE_MIN(pdata->rx_max_fifo_size,
2096                                           pdata->vdata->rx_max_fifo_size);
2097         /* Issue software reset to DMA */
2098         ret = pdata->hw_if.exit(pdata);
2099         if (ret)
2100                 PMD_DRV_LOG(ERR, "hw_if->exit EBUSY error\n");
2101
2102         /* Set default configuration data */
2103         axgbe_default_config(pdata);
2104
2105         /* Set default max values if not provided */
2106         if (!pdata->tx_max_fifo_size)
2107                 pdata->tx_max_fifo_size = pdata->hw_feat.tx_fifo_size;
2108         if (!pdata->rx_max_fifo_size)
2109                 pdata->rx_max_fifo_size = pdata->hw_feat.rx_fifo_size;
2110
2111         pdata->tx_desc_count = AXGBE_MAX_RING_DESC;
2112         pdata->rx_desc_count = AXGBE_MAX_RING_DESC;
2113         pthread_mutex_init(&pdata->xpcs_mutex, NULL);
2114         pthread_mutex_init(&pdata->i2c_mutex, NULL);
2115         pthread_mutex_init(&pdata->an_mutex, NULL);
2116         pthread_mutex_init(&pdata->phy_mutex, NULL);
2117
2118         ret = pdata->phy_if.phy_init(pdata);
2119         if (ret) {
2120                 rte_free(eth_dev->data->mac_addrs);
2121                 eth_dev->data->mac_addrs = NULL;
2122                 return ret;
2123         }
2124
2125         rte_intr_callback_register(&pci_dev->intr_handle,
2126                                    axgbe_dev_interrupt_handler,
2127                                    (void *)eth_dev);
2128         PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x",
2129                      eth_dev->data->port_id, pci_dev->id.vendor_id,
2130                      pci_dev->id.device_id);
2131
2132         return 0;
2133 }
2134
2135 static int
2136 eth_axgbe_dev_uninit(struct rte_eth_dev *eth_dev)
2137 {
2138         struct rte_pci_device *pci_dev;
2139
2140         PMD_INIT_FUNC_TRACE();
2141
2142         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
2143                 return 0;
2144
2145         pci_dev = RTE_DEV_TO_PCI(eth_dev->device);
2146         eth_dev->dev_ops = NULL;
2147         eth_dev->rx_pkt_burst = NULL;
2148         eth_dev->tx_pkt_burst = NULL;
2149         axgbe_dev_clear_queues(eth_dev);
2150
2151         /* disable uio intr before callback unregister */
2152         rte_intr_disable(&pci_dev->intr_handle);
2153         rte_intr_callback_unregister(&pci_dev->intr_handle,
2154                                      axgbe_dev_interrupt_handler,
2155                                      (void *)eth_dev);
2156
2157         return 0;
2158 }
2159
2160 static int eth_axgbe_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
2161         struct rte_pci_device *pci_dev)
2162 {
2163         return rte_eth_dev_pci_generic_probe(pci_dev,
2164                 sizeof(struct axgbe_port), eth_axgbe_dev_init);
2165 }
2166
2167 static int eth_axgbe_pci_remove(struct rte_pci_device *pci_dev)
2168 {
2169         return rte_eth_dev_pci_generic_remove(pci_dev, eth_axgbe_dev_uninit);
2170 }
2171
2172 static struct rte_pci_driver rte_axgbe_pmd = {
2173         .id_table = pci_id_axgbe_map,
2174         .drv_flags = RTE_PCI_DRV_NEED_MAPPING,
2175         .probe = eth_axgbe_pci_probe,
2176         .remove = eth_axgbe_pci_remove,
2177 };
2178
2179 RTE_PMD_REGISTER_PCI(net_axgbe, rte_axgbe_pmd);
2180 RTE_PMD_REGISTER_PCI_TABLE(net_axgbe, pci_id_axgbe_map);
2181 RTE_PMD_REGISTER_KMOD_DEP(net_axgbe, "* igb_uio | uio_pci_generic | vfio-pci");
2182 RTE_LOG_REGISTER(axgbe_logtype_init, pmd.net.axgbe.init, NOTICE);
2183 RTE_LOG_REGISTER(axgbe_logtype_driver, pmd.net.axgbe.driver, NOTICE);