1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2018 Advanced Micro Devices, Inc. All rights reserved.
3 * Copyright(c) 2018 Synopsys, Inc. All rights reserved.
6 #include "axgbe_rxtx.h"
7 #include "axgbe_ethdev.h"
8 #include "axgbe_common.h"
10 #include "axgbe_regs.h"
12 static int eth_axgbe_dev_init(struct rte_eth_dev *eth_dev);
13 static int eth_axgbe_dev_uninit(struct rte_eth_dev *eth_dev);
14 static int axgbe_dev_configure(struct rte_eth_dev *dev);
15 static int axgbe_dev_start(struct rte_eth_dev *dev);
16 static void axgbe_dev_stop(struct rte_eth_dev *dev);
17 static void axgbe_dev_interrupt_handler(void *param);
18 static void axgbe_dev_close(struct rte_eth_dev *dev);
19 static int axgbe_dev_promiscuous_enable(struct rte_eth_dev *dev);
20 static int axgbe_dev_promiscuous_disable(struct rte_eth_dev *dev);
21 static int axgbe_dev_allmulticast_enable(struct rte_eth_dev *dev);
22 static int axgbe_dev_allmulticast_disable(struct rte_eth_dev *dev);
23 static int axgbe_dev_link_update(struct rte_eth_dev *dev,
24 int wait_to_complete);
25 static int axgbe_dev_get_regs(struct rte_eth_dev *dev,
26 struct rte_dev_reg_info *regs);
27 static int axgbe_dev_stats_get(struct rte_eth_dev *dev,
28 struct rte_eth_stats *stats);
29 static int axgbe_dev_stats_reset(struct rte_eth_dev *dev);
30 static int axgbe_dev_xstats_get(struct rte_eth_dev *dev,
31 struct rte_eth_xstat *stats,
34 axgbe_dev_xstats_get_names(struct rte_eth_dev *dev,
35 struct rte_eth_xstat_name *xstats_names,
38 axgbe_dev_xstats_get_by_id(struct rte_eth_dev *dev,
43 axgbe_dev_xstats_get_names_by_id(struct rte_eth_dev *dev,
44 struct rte_eth_xstat_name *xstats_names,
47 static int axgbe_dev_xstats_reset(struct rte_eth_dev *dev);
48 static int axgbe_dev_info_get(struct rte_eth_dev *dev,
49 struct rte_eth_dev_info *dev_info);
52 char name[RTE_ETH_XSTATS_NAME_SIZE];
56 #define AXGMAC_MMC_STAT(_string, _var) \
58 offsetof(struct axgbe_mmc_stats, _var), \
61 static const struct axgbe_xstats axgbe_xstats_strings[] = {
62 AXGMAC_MMC_STAT("tx_bytes", txoctetcount_gb),
63 AXGMAC_MMC_STAT("tx_packets", txframecount_gb),
64 AXGMAC_MMC_STAT("tx_unicast_packets", txunicastframes_gb),
65 AXGMAC_MMC_STAT("tx_broadcast_packets", txbroadcastframes_gb),
66 AXGMAC_MMC_STAT("tx_multicast_packets", txmulticastframes_gb),
67 AXGMAC_MMC_STAT("tx_vlan_packets", txvlanframes_g),
68 AXGMAC_MMC_STAT("tx_64_byte_packets", tx64octets_gb),
69 AXGMAC_MMC_STAT("tx_65_to_127_byte_packets", tx65to127octets_gb),
70 AXGMAC_MMC_STAT("tx_128_to_255_byte_packets", tx128to255octets_gb),
71 AXGMAC_MMC_STAT("tx_256_to_511_byte_packets", tx256to511octets_gb),
72 AXGMAC_MMC_STAT("tx_512_to_1023_byte_packets", tx512to1023octets_gb),
73 AXGMAC_MMC_STAT("tx_1024_to_max_byte_packets", tx1024tomaxoctets_gb),
74 AXGMAC_MMC_STAT("tx_underflow_errors", txunderflowerror),
75 AXGMAC_MMC_STAT("tx_pause_frames", txpauseframes),
77 AXGMAC_MMC_STAT("rx_bytes", rxoctetcount_gb),
78 AXGMAC_MMC_STAT("rx_packets", rxframecount_gb),
79 AXGMAC_MMC_STAT("rx_unicast_packets", rxunicastframes_g),
80 AXGMAC_MMC_STAT("rx_broadcast_packets", rxbroadcastframes_g),
81 AXGMAC_MMC_STAT("rx_multicast_packets", rxmulticastframes_g),
82 AXGMAC_MMC_STAT("rx_vlan_packets", rxvlanframes_gb),
83 AXGMAC_MMC_STAT("rx_64_byte_packets", rx64octets_gb),
84 AXGMAC_MMC_STAT("rx_65_to_127_byte_packets", rx65to127octets_gb),
85 AXGMAC_MMC_STAT("rx_128_to_255_byte_packets", rx128to255octets_gb),
86 AXGMAC_MMC_STAT("rx_256_to_511_byte_packets", rx256to511octets_gb),
87 AXGMAC_MMC_STAT("rx_512_to_1023_byte_packets", rx512to1023octets_gb),
88 AXGMAC_MMC_STAT("rx_1024_to_max_byte_packets", rx1024tomaxoctets_gb),
89 AXGMAC_MMC_STAT("rx_undersize_packets", rxundersize_g),
90 AXGMAC_MMC_STAT("rx_oversize_packets", rxoversize_g),
91 AXGMAC_MMC_STAT("rx_crc_errors", rxcrcerror),
92 AXGMAC_MMC_STAT("rx_crc_errors_small_packets", rxrunterror),
93 AXGMAC_MMC_STAT("rx_crc_errors_giant_packets", rxjabbererror),
94 AXGMAC_MMC_STAT("rx_length_errors", rxlengtherror),
95 AXGMAC_MMC_STAT("rx_out_of_range_errors", rxoutofrangetype),
96 AXGMAC_MMC_STAT("rx_fifo_overflow_errors", rxfifooverflow),
97 AXGMAC_MMC_STAT("rx_watchdog_errors", rxwatchdogerror),
98 AXGMAC_MMC_STAT("rx_pause_frames", rxpauseframes),
101 #define AXGBE_XSTATS_COUNT ARRAY_SIZE(axgbe_xstats_strings)
103 /* The set of PCI devices this driver supports */
104 #define AMD_PCI_VENDOR_ID 0x1022
105 #define AMD_PCI_RV_ROOT_COMPLEX_ID 0x15d0
106 #define AMD_PCI_AXGBE_DEVICE_V2A 0x1458
107 #define AMD_PCI_AXGBE_DEVICE_V2B 0x1459
109 int axgbe_logtype_init;
110 int axgbe_logtype_driver;
112 static const struct rte_pci_id pci_id_axgbe_map[] = {
113 {RTE_PCI_DEVICE(AMD_PCI_VENDOR_ID, AMD_PCI_AXGBE_DEVICE_V2A)},
114 {RTE_PCI_DEVICE(AMD_PCI_VENDOR_ID, AMD_PCI_AXGBE_DEVICE_V2B)},
118 static struct axgbe_version_data axgbe_v2a = {
119 .init_function_ptrs_phy_impl = axgbe_init_function_ptrs_phy_v2,
120 .xpcs_access = AXGBE_XPCS_ACCESS_V2,
122 .tx_max_fifo_size = 229376,
123 .rx_max_fifo_size = 229376,
124 .tx_tstamp_workaround = 1,
127 .an_cdr_workaround = 1,
130 static struct axgbe_version_data axgbe_v2b = {
131 .init_function_ptrs_phy_impl = axgbe_init_function_ptrs_phy_v2,
132 .xpcs_access = AXGBE_XPCS_ACCESS_V2,
134 .tx_max_fifo_size = 65536,
135 .rx_max_fifo_size = 65536,
136 .tx_tstamp_workaround = 1,
139 .an_cdr_workaround = 1,
142 static const struct rte_eth_desc_lim rx_desc_lim = {
143 .nb_max = AXGBE_MAX_RING_DESC,
144 .nb_min = AXGBE_MIN_RING_DESC,
148 static const struct rte_eth_desc_lim tx_desc_lim = {
149 .nb_max = AXGBE_MAX_RING_DESC,
150 .nb_min = AXGBE_MIN_RING_DESC,
154 static const struct eth_dev_ops axgbe_eth_dev_ops = {
155 .dev_configure = axgbe_dev_configure,
156 .dev_start = axgbe_dev_start,
157 .dev_stop = axgbe_dev_stop,
158 .dev_close = axgbe_dev_close,
159 .promiscuous_enable = axgbe_dev_promiscuous_enable,
160 .promiscuous_disable = axgbe_dev_promiscuous_disable,
161 .allmulticast_enable = axgbe_dev_allmulticast_enable,
162 .allmulticast_disable = axgbe_dev_allmulticast_disable,
163 .link_update = axgbe_dev_link_update,
164 .get_reg = axgbe_dev_get_regs,
165 .stats_get = axgbe_dev_stats_get,
166 .stats_reset = axgbe_dev_stats_reset,
167 .xstats_get = axgbe_dev_xstats_get,
168 .xstats_reset = axgbe_dev_xstats_reset,
169 .xstats_get_names = axgbe_dev_xstats_get_names,
170 .xstats_get_names_by_id = axgbe_dev_xstats_get_names_by_id,
171 .xstats_get_by_id = axgbe_dev_xstats_get_by_id,
172 .dev_infos_get = axgbe_dev_info_get,
173 .rx_queue_setup = axgbe_dev_rx_queue_setup,
174 .rx_queue_release = axgbe_dev_rx_queue_release,
175 .tx_queue_setup = axgbe_dev_tx_queue_setup,
176 .tx_queue_release = axgbe_dev_tx_queue_release,
179 static int axgbe_phy_reset(struct axgbe_port *pdata)
181 pdata->phy_link = -1;
182 pdata->phy_speed = SPEED_UNKNOWN;
183 return pdata->phy_if.phy_reset(pdata);
187 * Interrupt handler triggered by NIC for handling
188 * specific interrupt.
191 * Pointer to interrupt handle.
193 * The address of parameter (struct rte_eth_dev *) regsitered before.
199 axgbe_dev_interrupt_handler(void *param)
201 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
202 struct axgbe_port *pdata = dev->data->dev_private;
203 unsigned int dma_isr, dma_ch_isr;
205 pdata->phy_if.an_isr(pdata);
206 /*DMA related interrupts*/
207 dma_isr = AXGMAC_IOREAD(pdata, DMA_ISR);
208 PMD_DRV_LOG(DEBUG, "DMA_ISR=%#010x\n", dma_isr);
212 AXGMAC_DMA_IOREAD((struct axgbe_rx_queue *)
215 PMD_DRV_LOG(DEBUG, "DMA_CH0_ISR=%#010x\n", dma_ch_isr);
216 AXGMAC_DMA_IOWRITE((struct axgbe_rx_queue *)
218 DMA_CH_SR, dma_ch_isr);
221 /* Unmask interrupts since disabled after generation */
222 rte_intr_ack(&pdata->pci_dev->intr_handle);
226 * Configure device link speed and setup link.
227 * It returns 0 on success.
230 axgbe_dev_configure(struct rte_eth_dev *dev)
232 struct axgbe_port *pdata = dev->data->dev_private;
233 /* Checksum offload to hardware */
234 pdata->rx_csum_enable = dev->data->dev_conf.rxmode.offloads &
235 DEV_RX_OFFLOAD_CHECKSUM;
240 axgbe_dev_rx_mq_config(struct rte_eth_dev *dev)
242 struct axgbe_port *pdata = dev->data->dev_private;
244 if (dev->data->dev_conf.rxmode.mq_mode == ETH_MQ_RX_RSS)
245 pdata->rss_enable = 1;
246 else if (dev->data->dev_conf.rxmode.mq_mode == ETH_MQ_RX_NONE)
247 pdata->rss_enable = 0;
254 axgbe_dev_start(struct rte_eth_dev *dev)
256 struct axgbe_port *pdata = dev->data->dev_private;
258 struct rte_eth_dev_data *dev_data = dev->data;
259 uint16_t max_pkt_len = dev_data->dev_conf.rxmode.max_rx_pkt_len;
261 dev->dev_ops = &axgbe_eth_dev_ops;
263 PMD_INIT_FUNC_TRACE();
266 ret = axgbe_dev_rx_mq_config(dev);
268 PMD_DRV_LOG(ERR, "Unable to config RX MQ\n");
271 ret = axgbe_phy_reset(pdata);
273 PMD_DRV_LOG(ERR, "phy reset failed\n");
276 ret = pdata->hw_if.init(pdata);
278 PMD_DRV_LOG(ERR, "dev_init failed\n");
282 /* enable uio/vfio intr/eventfd mapping */
283 rte_intr_enable(&pdata->pci_dev->intr_handle);
286 pdata->phy_if.phy_start(pdata);
287 axgbe_dev_enable_tx(dev);
288 axgbe_dev_enable_rx(dev);
290 axgbe_clear_bit(AXGBE_STOPPED, &pdata->dev_state);
291 axgbe_clear_bit(AXGBE_DOWN, &pdata->dev_state);
292 if ((dev_data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_SCATTER) ||
293 max_pkt_len > pdata->rx_buf_size)
294 dev_data->scattered_rx = 1;
296 /* Scatter Rx handling */
297 if (dev_data->scattered_rx)
298 dev->rx_pkt_burst = ð_axgbe_recv_scattered_pkts;
300 dev->rx_pkt_burst = &axgbe_recv_pkts;
305 /* Stop device: disable rx and tx functions to allow for reconfiguring. */
307 axgbe_dev_stop(struct rte_eth_dev *dev)
309 struct axgbe_port *pdata = dev->data->dev_private;
311 PMD_INIT_FUNC_TRACE();
313 rte_intr_disable(&pdata->pci_dev->intr_handle);
315 if (axgbe_test_bit(AXGBE_STOPPED, &pdata->dev_state))
318 axgbe_set_bit(AXGBE_STOPPED, &pdata->dev_state);
319 axgbe_dev_disable_tx(dev);
320 axgbe_dev_disable_rx(dev);
322 pdata->phy_if.phy_stop(pdata);
323 pdata->hw_if.exit(pdata);
324 memset(&dev->data->dev_link, 0, sizeof(struct rte_eth_link));
325 axgbe_set_bit(AXGBE_DOWN, &pdata->dev_state);
328 /* Clear all resources like TX/RX queues. */
330 axgbe_dev_close(struct rte_eth_dev *dev)
332 axgbe_dev_clear_queues(dev);
336 axgbe_dev_promiscuous_enable(struct rte_eth_dev *dev)
338 struct axgbe_port *pdata = dev->data->dev_private;
340 PMD_INIT_FUNC_TRACE();
342 AXGMAC_IOWRITE_BITS(pdata, MAC_PFR, PR, 1);
348 axgbe_dev_promiscuous_disable(struct rte_eth_dev *dev)
350 struct axgbe_port *pdata = dev->data->dev_private;
352 PMD_INIT_FUNC_TRACE();
354 AXGMAC_IOWRITE_BITS(pdata, MAC_PFR, PR, 0);
360 axgbe_dev_allmulticast_enable(struct rte_eth_dev *dev)
362 struct axgbe_port *pdata = dev->data->dev_private;
364 PMD_INIT_FUNC_TRACE();
366 if (AXGMAC_IOREAD_BITS(pdata, MAC_PFR, PM))
368 AXGMAC_IOWRITE_BITS(pdata, MAC_PFR, PM, 1);
374 axgbe_dev_allmulticast_disable(struct rte_eth_dev *dev)
376 struct axgbe_port *pdata = dev->data->dev_private;
378 PMD_INIT_FUNC_TRACE();
380 if (!AXGMAC_IOREAD_BITS(pdata, MAC_PFR, PM))
382 AXGMAC_IOWRITE_BITS(pdata, MAC_PFR, PM, 0);
387 /* return 0 means link status changed, -1 means not changed */
389 axgbe_dev_link_update(struct rte_eth_dev *dev,
390 int wait_to_complete __rte_unused)
392 struct axgbe_port *pdata = dev->data->dev_private;
393 struct rte_eth_link link;
396 PMD_INIT_FUNC_TRACE();
399 pdata->phy_if.phy_status(pdata);
401 memset(&link, 0, sizeof(struct rte_eth_link));
402 link.link_duplex = pdata->phy.duplex;
403 link.link_status = pdata->phy_link;
404 link.link_speed = pdata->phy_speed;
405 link.link_autoneg = !(dev->data->dev_conf.link_speeds &
406 ETH_LINK_SPEED_FIXED);
407 ret = rte_eth_linkstatus_set(dev, &link);
409 PMD_DRV_LOG(ERR, "No change in link status\n");
415 axgbe_dev_get_regs(struct rte_eth_dev *dev, struct rte_dev_reg_info *regs)
417 struct axgbe_port *pdata = dev->data->dev_private;
419 if (regs->data == NULL) {
420 regs->length = axgbe_regs_get_count(pdata);
421 regs->width = sizeof(uint32_t);
425 /* Only full register dump is supported */
427 regs->length != (uint32_t)axgbe_regs_get_count(pdata))
430 regs->version = pdata->pci_dev->id.vendor_id << 16 |
431 pdata->pci_dev->id.device_id;
432 axgbe_regs_dump(pdata, regs->data);
435 static void axgbe_read_mmc_stats(struct axgbe_port *pdata)
437 struct axgbe_mmc_stats *stats = &pdata->mmc_stats;
439 /* Freeze counters */
440 AXGMAC_IOWRITE_BITS(pdata, MMC_CR, MCF, 1);
443 stats->txoctetcount_gb +=
444 AXGMAC_IOREAD(pdata, MMC_TXOCTETCOUNT_GB_LO);
445 stats->txoctetcount_gb +=
446 ((uint64_t)AXGMAC_IOREAD(pdata, MMC_TXOCTETCOUNT_GB_HI) << 32);
448 stats->txframecount_gb +=
449 AXGMAC_IOREAD(pdata, MMC_TXFRAMECOUNT_GB_LO);
450 stats->txframecount_gb +=
451 ((uint64_t)AXGMAC_IOREAD(pdata, MMC_TXFRAMECOUNT_GB_HI) << 32);
453 stats->txbroadcastframes_g +=
454 AXGMAC_IOREAD(pdata, MMC_TXBROADCASTFRAMES_G_LO);
455 stats->txbroadcastframes_g +=
456 ((uint64_t)AXGMAC_IOREAD(pdata, MMC_TXBROADCASTFRAMES_G_HI) << 32);
458 stats->txmulticastframes_g +=
459 AXGMAC_IOREAD(pdata, MMC_TXMULTICASTFRAMES_G_LO);
460 stats->txmulticastframes_g +=
461 ((uint64_t)AXGMAC_IOREAD(pdata, MMC_TXMULTICASTFRAMES_G_HI) << 32);
463 stats->tx64octets_gb +=
464 AXGMAC_IOREAD(pdata, MMC_TX64OCTETS_GB_LO);
465 stats->tx64octets_gb +=
466 ((uint64_t)AXGMAC_IOREAD(pdata, MMC_TX64OCTETS_GB_HI) << 32);
468 stats->tx65to127octets_gb +=
469 AXGMAC_IOREAD(pdata, MMC_TX65TO127OCTETS_GB_LO);
470 stats->tx65to127octets_gb +=
471 ((uint64_t)AXGMAC_IOREAD(pdata, MMC_TX65TO127OCTETS_GB_HI) << 32);
473 stats->tx128to255octets_gb +=
474 AXGMAC_IOREAD(pdata, MMC_TX128TO255OCTETS_GB_LO);
475 stats->tx128to255octets_gb +=
476 ((uint64_t)AXGMAC_IOREAD(pdata, MMC_TX128TO255OCTETS_GB_HI) << 32);
478 stats->tx256to511octets_gb +=
479 AXGMAC_IOREAD(pdata, MMC_TX256TO511OCTETS_GB_LO);
480 stats->tx256to511octets_gb +=
481 ((uint64_t)AXGMAC_IOREAD(pdata, MMC_TX256TO511OCTETS_GB_HI) << 32);
483 stats->tx512to1023octets_gb +=
484 AXGMAC_IOREAD(pdata, MMC_TX512TO1023OCTETS_GB_LO);
485 stats->tx512to1023octets_gb +=
486 ((uint64_t)AXGMAC_IOREAD(pdata, MMC_TX512TO1023OCTETS_GB_HI) << 32);
488 stats->tx1024tomaxoctets_gb +=
489 AXGMAC_IOREAD(pdata, MMC_TX1024TOMAXOCTETS_GB_LO);
490 stats->tx1024tomaxoctets_gb +=
491 ((uint64_t)AXGMAC_IOREAD(pdata, MMC_TX1024TOMAXOCTETS_GB_HI) << 32);
493 stats->txunicastframes_gb +=
494 AXGMAC_IOREAD(pdata, MMC_TXUNICASTFRAMES_GB_LO);
495 stats->txunicastframes_gb +=
496 ((uint64_t)AXGMAC_IOREAD(pdata, MMC_TXUNICASTFRAMES_GB_HI) << 32);
498 stats->txmulticastframes_gb +=
499 AXGMAC_IOREAD(pdata, MMC_TXMULTICASTFRAMES_GB_LO);
500 stats->txmulticastframes_gb +=
501 ((uint64_t)AXGMAC_IOREAD(pdata, MMC_TXMULTICASTFRAMES_GB_HI) << 32);
503 stats->txbroadcastframes_g +=
504 AXGMAC_IOREAD(pdata, MMC_TXBROADCASTFRAMES_GB_LO);
505 stats->txbroadcastframes_g +=
506 ((uint64_t)AXGMAC_IOREAD(pdata, MMC_TXBROADCASTFRAMES_GB_HI) << 32);
508 stats->txunderflowerror +=
509 AXGMAC_IOREAD(pdata, MMC_TXUNDERFLOWERROR_LO);
510 stats->txunderflowerror +=
511 ((uint64_t)AXGMAC_IOREAD(pdata, MMC_TXUNDERFLOWERROR_HI) << 32);
513 stats->txoctetcount_g +=
514 AXGMAC_IOREAD(pdata, MMC_TXOCTETCOUNT_G_LO);
515 stats->txoctetcount_g +=
516 ((uint64_t)AXGMAC_IOREAD(pdata, MMC_TXOCTETCOUNT_G_HI) << 32);
518 stats->txframecount_g +=
519 AXGMAC_IOREAD(pdata, MMC_TXFRAMECOUNT_G_LO);
520 stats->txframecount_g +=
521 ((uint64_t)AXGMAC_IOREAD(pdata, MMC_TXFRAMECOUNT_G_HI) << 32);
523 stats->txpauseframes +=
524 AXGMAC_IOREAD(pdata, MMC_TXPAUSEFRAMES_LO);
525 stats->txpauseframes +=
526 ((uint64_t)AXGMAC_IOREAD(pdata, MMC_TXPAUSEFRAMES_HI) << 32);
528 stats->txvlanframes_g +=
529 AXGMAC_IOREAD(pdata, MMC_TXVLANFRAMES_G_LO);
530 stats->txvlanframes_g +=
531 ((uint64_t)AXGMAC_IOREAD(pdata, MMC_TXVLANFRAMES_G_HI) << 32);
534 stats->rxframecount_gb +=
535 AXGMAC_IOREAD(pdata, MMC_RXFRAMECOUNT_GB_LO);
536 stats->rxframecount_gb +=
537 ((uint64_t)AXGMAC_IOREAD(pdata, MMC_RXFRAMECOUNT_GB_HI) << 32);
539 stats->rxoctetcount_gb +=
540 AXGMAC_IOREAD(pdata, MMC_RXOCTETCOUNT_GB_LO);
541 stats->rxoctetcount_gb +=
542 ((uint64_t)AXGMAC_IOREAD(pdata, MMC_RXOCTETCOUNT_GB_HI) << 32);
544 stats->rxoctetcount_g +=
545 AXGMAC_IOREAD(pdata, MMC_RXOCTETCOUNT_G_LO);
546 stats->rxoctetcount_g +=
547 ((uint64_t)AXGMAC_IOREAD(pdata, MMC_RXOCTETCOUNT_G_HI) << 32);
549 stats->rxbroadcastframes_g +=
550 AXGMAC_IOREAD(pdata, MMC_RXBROADCASTFRAMES_G_LO);
551 stats->rxbroadcastframes_g +=
552 ((uint64_t)AXGMAC_IOREAD(pdata, MMC_RXBROADCASTFRAMES_G_HI) << 32);
554 stats->rxmulticastframes_g +=
555 AXGMAC_IOREAD(pdata, MMC_RXMULTICASTFRAMES_G_LO);
556 stats->rxmulticastframes_g +=
557 ((uint64_t)AXGMAC_IOREAD(pdata, MMC_RXMULTICASTFRAMES_G_HI) << 32);
560 AXGMAC_IOREAD(pdata, MMC_RXCRCERROR_LO);
562 ((uint64_t)AXGMAC_IOREAD(pdata, MMC_RXCRCERROR_HI) << 32);
564 stats->rxrunterror +=
565 AXGMAC_IOREAD(pdata, MMC_RXRUNTERROR);
567 stats->rxjabbererror +=
568 AXGMAC_IOREAD(pdata, MMC_RXJABBERERROR);
570 stats->rxundersize_g +=
571 AXGMAC_IOREAD(pdata, MMC_RXUNDERSIZE_G);
573 stats->rxoversize_g +=
574 AXGMAC_IOREAD(pdata, MMC_RXOVERSIZE_G);
576 stats->rx64octets_gb +=
577 AXGMAC_IOREAD(pdata, MMC_RX64OCTETS_GB_LO);
578 stats->rx64octets_gb +=
579 ((uint64_t)AXGMAC_IOREAD(pdata, MMC_RX64OCTETS_GB_HI) << 32);
581 stats->rx65to127octets_gb +=
582 AXGMAC_IOREAD(pdata, MMC_RX65TO127OCTETS_GB_LO);
583 stats->rx65to127octets_gb +=
584 ((uint64_t)AXGMAC_IOREAD(pdata, MMC_RX65TO127OCTETS_GB_HI) << 32);
586 stats->rx128to255octets_gb +=
587 AXGMAC_IOREAD(pdata, MMC_RX128TO255OCTETS_GB_LO);
588 stats->rx128to255octets_gb +=
589 ((uint64_t)AXGMAC_IOREAD(pdata, MMC_RX128TO255OCTETS_GB_HI) << 32);
591 stats->rx256to511octets_gb +=
592 AXGMAC_IOREAD(pdata, MMC_RX256TO511OCTETS_GB_LO);
593 stats->rx256to511octets_gb +=
594 ((uint64_t)AXGMAC_IOREAD(pdata, MMC_RX256TO511OCTETS_GB_HI) << 32);
596 stats->rx512to1023octets_gb +=
597 AXGMAC_IOREAD(pdata, MMC_RX512TO1023OCTETS_GB_LO);
598 stats->rx512to1023octets_gb +=
599 ((uint64_t)AXGMAC_IOREAD(pdata, MMC_RX512TO1023OCTETS_GB_HI) << 32);
601 stats->rx1024tomaxoctets_gb +=
602 AXGMAC_IOREAD(pdata, MMC_RX1024TOMAXOCTETS_GB_LO);
603 stats->rx1024tomaxoctets_gb +=
604 ((uint64_t)AXGMAC_IOREAD(pdata, MMC_RX1024TOMAXOCTETS_GB_HI) << 32);
606 stats->rxunicastframes_g +=
607 AXGMAC_IOREAD(pdata, MMC_RXUNICASTFRAMES_G_LO);
608 stats->rxunicastframes_g +=
609 ((uint64_t)AXGMAC_IOREAD(pdata, MMC_RXUNICASTFRAMES_G_HI) << 32);
611 stats->rxlengtherror +=
612 AXGMAC_IOREAD(pdata, MMC_RXLENGTHERROR_LO);
613 stats->rxlengtherror +=
614 ((uint64_t)AXGMAC_IOREAD(pdata, MMC_RXLENGTHERROR_HI) << 32);
616 stats->rxoutofrangetype +=
617 AXGMAC_IOREAD(pdata, MMC_RXOUTOFRANGETYPE_LO);
618 stats->rxoutofrangetype +=
619 ((uint64_t)AXGMAC_IOREAD(pdata, MMC_RXOUTOFRANGETYPE_HI) << 32);
621 stats->rxpauseframes +=
622 AXGMAC_IOREAD(pdata, MMC_RXPAUSEFRAMES_LO);
623 stats->rxpauseframes +=
624 ((uint64_t)AXGMAC_IOREAD(pdata, MMC_RXPAUSEFRAMES_HI) << 32);
626 stats->rxfifooverflow +=
627 AXGMAC_IOREAD(pdata, MMC_RXFIFOOVERFLOW_LO);
628 stats->rxfifooverflow +=
629 ((uint64_t)AXGMAC_IOREAD(pdata, MMC_RXFIFOOVERFLOW_HI) << 32);
631 stats->rxvlanframes_gb +=
632 AXGMAC_IOREAD(pdata, MMC_RXVLANFRAMES_GB_LO);
633 stats->rxvlanframes_gb +=
634 ((uint64_t)AXGMAC_IOREAD(pdata, MMC_RXVLANFRAMES_GB_HI) << 32);
636 stats->rxwatchdogerror +=
637 AXGMAC_IOREAD(pdata, MMC_RXWATCHDOGERROR);
639 /* Un-freeze counters */
640 AXGMAC_IOWRITE_BITS(pdata, MMC_CR, MCF, 0);
644 axgbe_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *stats,
647 struct axgbe_port *pdata = dev->data->dev_private;
653 axgbe_read_mmc_stats(pdata);
655 for (i = 0; i < n && i < AXGBE_XSTATS_COUNT; i++) {
657 stats[i].value = *(u64 *)((uint8_t *)&pdata->mmc_stats +
658 axgbe_xstats_strings[i].offset);
665 axgbe_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
666 struct rte_eth_xstat_name *xstats_names,
671 if (n >= AXGBE_XSTATS_COUNT && xstats_names) {
672 for (i = 0; i < AXGBE_XSTATS_COUNT; ++i) {
673 snprintf(xstats_names[i].name,
674 RTE_ETH_XSTATS_NAME_SIZE, "%s",
675 axgbe_xstats_strings[i].name);
679 return AXGBE_XSTATS_COUNT;
683 axgbe_dev_xstats_get_by_id(struct rte_eth_dev *dev, const uint64_t *ids,
684 uint64_t *values, unsigned int n)
687 uint64_t values_copy[AXGBE_XSTATS_COUNT];
690 struct axgbe_port *pdata = dev->data->dev_private;
692 if (n < AXGBE_XSTATS_COUNT)
693 return AXGBE_XSTATS_COUNT;
695 axgbe_read_mmc_stats(pdata);
697 for (i = 0; i < AXGBE_XSTATS_COUNT; i++) {
698 values[i] = *(u64 *)((uint8_t *)&pdata->mmc_stats +
699 axgbe_xstats_strings[i].offset);
705 axgbe_dev_xstats_get_by_id(dev, NULL, values_copy, AXGBE_XSTATS_COUNT);
707 for (i = 0; i < n; i++) {
708 if (ids[i] >= AXGBE_XSTATS_COUNT) {
709 PMD_DRV_LOG(ERR, "id value isn't valid\n");
712 values[i] = values_copy[ids[i]];
718 axgbe_dev_xstats_get_names_by_id(struct rte_eth_dev *dev,
719 struct rte_eth_xstat_name *xstats_names,
723 struct rte_eth_xstat_name xstats_names_copy[AXGBE_XSTATS_COUNT];
727 return axgbe_dev_xstats_get_names(dev, xstats_names, size);
729 axgbe_dev_xstats_get_names(dev, xstats_names_copy, size);
731 for (i = 0; i < size; i++) {
732 if (ids[i] >= AXGBE_XSTATS_COUNT) {
733 PMD_DRV_LOG(ERR, "id value isn't valid\n");
736 strcpy(xstats_names[i].name, xstats_names_copy[ids[i]].name);
742 axgbe_dev_xstats_reset(struct rte_eth_dev *dev)
744 struct axgbe_port *pdata = dev->data->dev_private;
745 struct axgbe_mmc_stats *stats = &pdata->mmc_stats;
747 /* MMC registers are configured for reset on read */
748 axgbe_read_mmc_stats(pdata);
751 memset(stats, 0, sizeof(*stats));
757 axgbe_dev_stats_get(struct rte_eth_dev *dev,
758 struct rte_eth_stats *stats)
760 struct axgbe_rx_queue *rxq;
761 struct axgbe_tx_queue *txq;
762 struct axgbe_port *pdata = dev->data->dev_private;
763 struct axgbe_mmc_stats *mmc_stats = &pdata->mmc_stats;
766 axgbe_read_mmc_stats(pdata);
768 stats->imissed = mmc_stats->rxfifooverflow;
770 for (i = 0; i < dev->data->nb_rx_queues; i++) {
771 rxq = dev->data->rx_queues[i];
772 stats->q_ipackets[i] = rxq->pkts;
773 stats->ipackets += rxq->pkts;
774 stats->q_ibytes[i] = rxq->bytes;
775 stats->ibytes += rxq->bytes;
776 stats->rx_nombuf += rxq->rx_mbuf_alloc_failed;
777 stats->q_errors[i] = rxq->errors + rxq->rx_mbuf_alloc_failed;
778 stats->ierrors += rxq->errors;
781 for (i = 0; i < dev->data->nb_tx_queues; i++) {
782 txq = dev->data->tx_queues[i];
783 stats->q_opackets[i] = txq->pkts;
784 stats->opackets += txq->pkts;
785 stats->q_obytes[i] = txq->bytes;
786 stats->obytes += txq->bytes;
787 stats->oerrors += txq->errors;
794 axgbe_dev_stats_reset(struct rte_eth_dev *dev)
796 struct axgbe_rx_queue *rxq;
797 struct axgbe_tx_queue *txq;
800 for (i = 0; i < dev->data->nb_rx_queues; i++) {
801 rxq = dev->data->rx_queues[i];
805 rxq->rx_mbuf_alloc_failed = 0;
807 for (i = 0; i < dev->data->nb_tx_queues; i++) {
808 txq = dev->data->tx_queues[i];
818 axgbe_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
820 struct axgbe_port *pdata = dev->data->dev_private;
822 dev_info->max_rx_queues = pdata->rx_ring_count;
823 dev_info->max_tx_queues = pdata->tx_ring_count;
824 dev_info->min_rx_bufsize = AXGBE_RX_MIN_BUF_SIZE;
825 dev_info->max_rx_pktlen = AXGBE_RX_MAX_BUF_SIZE;
826 dev_info->max_mac_addrs = AXGBE_MAX_MAC_ADDRS;
827 dev_info->speed_capa = ETH_LINK_SPEED_10G;
829 dev_info->rx_offload_capa =
830 DEV_RX_OFFLOAD_IPV4_CKSUM |
831 DEV_RX_OFFLOAD_UDP_CKSUM |
832 DEV_RX_OFFLOAD_TCP_CKSUM |
833 DEV_RX_OFFLOAD_JUMBO_FRAME |
834 DEV_RX_OFFLOAD_SCATTER |
835 DEV_RX_OFFLOAD_KEEP_CRC;
837 dev_info->tx_offload_capa =
838 DEV_TX_OFFLOAD_IPV4_CKSUM |
839 DEV_TX_OFFLOAD_UDP_CKSUM |
840 DEV_TX_OFFLOAD_TCP_CKSUM;
842 if (pdata->hw_feat.rss) {
843 dev_info->flow_type_rss_offloads = AXGBE_RSS_OFFLOAD;
844 dev_info->reta_size = pdata->hw_feat.hash_table_size;
845 dev_info->hash_key_size = AXGBE_RSS_HASH_KEY_SIZE;
848 dev_info->rx_desc_lim = rx_desc_lim;
849 dev_info->tx_desc_lim = tx_desc_lim;
851 dev_info->default_rxconf = (struct rte_eth_rxconf) {
852 .rx_free_thresh = AXGBE_RX_FREE_THRESH,
855 dev_info->default_txconf = (struct rte_eth_txconf) {
856 .tx_free_thresh = AXGBE_TX_FREE_THRESH,
862 static void axgbe_get_all_hw_features(struct axgbe_port *pdata)
864 unsigned int mac_hfr0, mac_hfr1, mac_hfr2;
865 struct axgbe_hw_features *hw_feat = &pdata->hw_feat;
867 mac_hfr0 = AXGMAC_IOREAD(pdata, MAC_HWF0R);
868 mac_hfr1 = AXGMAC_IOREAD(pdata, MAC_HWF1R);
869 mac_hfr2 = AXGMAC_IOREAD(pdata, MAC_HWF2R);
871 memset(hw_feat, 0, sizeof(*hw_feat));
873 hw_feat->version = AXGMAC_IOREAD(pdata, MAC_VR);
875 /* Hardware feature register 0 */
876 hw_feat->gmii = AXGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, GMIISEL);
877 hw_feat->vlhash = AXGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, VLHASH);
878 hw_feat->sma = AXGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, SMASEL);
879 hw_feat->rwk = AXGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, RWKSEL);
880 hw_feat->mgk = AXGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, MGKSEL);
881 hw_feat->mmc = AXGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, MMCSEL);
882 hw_feat->aoe = AXGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, ARPOFFSEL);
883 hw_feat->ts = AXGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, TSSEL);
884 hw_feat->eee = AXGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, EEESEL);
885 hw_feat->tx_coe = AXGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, TXCOESEL);
886 hw_feat->rx_coe = AXGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, RXCOESEL);
887 hw_feat->addn_mac = AXGMAC_GET_BITS(mac_hfr0, MAC_HWF0R,
889 hw_feat->ts_src = AXGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, TSSTSSEL);
890 hw_feat->sa_vlan_ins = AXGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, SAVLANINS);
892 /* Hardware feature register 1 */
893 hw_feat->rx_fifo_size = AXGMAC_GET_BITS(mac_hfr1, MAC_HWF1R,
895 hw_feat->tx_fifo_size = AXGMAC_GET_BITS(mac_hfr1, MAC_HWF1R,
897 hw_feat->adv_ts_hi = AXGMAC_GET_BITS(mac_hfr1,
898 MAC_HWF1R, ADVTHWORD);
899 hw_feat->dma_width = AXGMAC_GET_BITS(mac_hfr1, MAC_HWF1R, ADDR64);
900 hw_feat->dcb = AXGMAC_GET_BITS(mac_hfr1, MAC_HWF1R, DCBEN);
901 hw_feat->sph = AXGMAC_GET_BITS(mac_hfr1, MAC_HWF1R, SPHEN);
902 hw_feat->tso = AXGMAC_GET_BITS(mac_hfr1, MAC_HWF1R, TSOEN);
903 hw_feat->dma_debug = AXGMAC_GET_BITS(mac_hfr1, MAC_HWF1R, DBGMEMA);
904 hw_feat->rss = AXGMAC_GET_BITS(mac_hfr1, MAC_HWF1R, RSSEN);
905 hw_feat->tc_cnt = AXGMAC_GET_BITS(mac_hfr1, MAC_HWF1R, NUMTC);
906 hw_feat->hash_table_size = AXGMAC_GET_BITS(mac_hfr1, MAC_HWF1R,
908 hw_feat->l3l4_filter_num = AXGMAC_GET_BITS(mac_hfr1, MAC_HWF1R,
911 /* Hardware feature register 2 */
912 hw_feat->rx_q_cnt = AXGMAC_GET_BITS(mac_hfr2, MAC_HWF2R, RXQCNT);
913 hw_feat->tx_q_cnt = AXGMAC_GET_BITS(mac_hfr2, MAC_HWF2R, TXQCNT);
914 hw_feat->rx_ch_cnt = AXGMAC_GET_BITS(mac_hfr2, MAC_HWF2R, RXCHCNT);
915 hw_feat->tx_ch_cnt = AXGMAC_GET_BITS(mac_hfr2, MAC_HWF2R, TXCHCNT);
916 hw_feat->pps_out_num = AXGMAC_GET_BITS(mac_hfr2, MAC_HWF2R, PPSOUTNUM);
917 hw_feat->aux_snap_num = AXGMAC_GET_BITS(mac_hfr2, MAC_HWF2R,
920 /* Translate the Hash Table size into actual number */
921 switch (hw_feat->hash_table_size) {
925 hw_feat->hash_table_size = 64;
928 hw_feat->hash_table_size = 128;
931 hw_feat->hash_table_size = 256;
935 /* Translate the address width setting into actual number */
936 switch (hw_feat->dma_width) {
938 hw_feat->dma_width = 32;
941 hw_feat->dma_width = 40;
944 hw_feat->dma_width = 48;
947 hw_feat->dma_width = 32;
950 /* The Queue, Channel and TC counts are zero based so increment them
951 * to get the actual number
955 hw_feat->rx_ch_cnt++;
956 hw_feat->tx_ch_cnt++;
959 /* Translate the fifo sizes into actual numbers */
960 hw_feat->rx_fifo_size = 1 << (hw_feat->rx_fifo_size + 7);
961 hw_feat->tx_fifo_size = 1 << (hw_feat->tx_fifo_size + 7);
964 static void axgbe_init_all_fptrs(struct axgbe_port *pdata)
966 axgbe_init_function_ptrs_dev(&pdata->hw_if);
967 axgbe_init_function_ptrs_phy(&pdata->phy_if);
968 axgbe_init_function_ptrs_i2c(&pdata->i2c_if);
969 pdata->vdata->init_function_ptrs_phy_impl(&pdata->phy_if);
972 static void axgbe_set_counts(struct axgbe_port *pdata)
974 /* Set all the function pointers */
975 axgbe_init_all_fptrs(pdata);
977 /* Populate the hardware features */
978 axgbe_get_all_hw_features(pdata);
980 /* Set default max values if not provided */
981 if (!pdata->tx_max_channel_count)
982 pdata->tx_max_channel_count = pdata->hw_feat.tx_ch_cnt;
983 if (!pdata->rx_max_channel_count)
984 pdata->rx_max_channel_count = pdata->hw_feat.rx_ch_cnt;
986 if (!pdata->tx_max_q_count)
987 pdata->tx_max_q_count = pdata->hw_feat.tx_q_cnt;
988 if (!pdata->rx_max_q_count)
989 pdata->rx_max_q_count = pdata->hw_feat.rx_q_cnt;
991 /* Calculate the number of Tx and Rx rings to be created
992 * -Tx (DMA) Channels map 1-to-1 to Tx Queues so set
993 * the number of Tx queues to the number of Tx channels
995 * -Rx (DMA) Channels do not map 1-to-1 so use the actual
996 * number of Rx queues or maximum allowed
998 pdata->tx_ring_count = RTE_MIN(pdata->hw_feat.tx_ch_cnt,
999 pdata->tx_max_channel_count);
1000 pdata->tx_ring_count = RTE_MIN(pdata->tx_ring_count,
1001 pdata->tx_max_q_count);
1003 pdata->tx_q_count = pdata->tx_ring_count;
1005 pdata->rx_ring_count = RTE_MIN(pdata->hw_feat.rx_ch_cnt,
1006 pdata->rx_max_channel_count);
1008 pdata->rx_q_count = RTE_MIN(pdata->hw_feat.rx_q_cnt,
1009 pdata->rx_max_q_count);
1012 static void axgbe_default_config(struct axgbe_port *pdata)
1014 pdata->pblx8 = DMA_PBL_X8_ENABLE;
1015 pdata->tx_sf_mode = MTL_TSF_ENABLE;
1016 pdata->tx_threshold = MTL_TX_THRESHOLD_64;
1017 pdata->tx_pbl = DMA_PBL_32;
1018 pdata->tx_osp_mode = DMA_OSP_ENABLE;
1019 pdata->rx_sf_mode = MTL_RSF_ENABLE;
1020 pdata->rx_threshold = MTL_RX_THRESHOLD_64;
1021 pdata->rx_pbl = DMA_PBL_32;
1022 pdata->pause_autoneg = 1;
1023 pdata->tx_pause = 0;
1024 pdata->rx_pause = 0;
1025 pdata->phy_speed = SPEED_UNKNOWN;
1026 pdata->power_down = 0;
1030 pci_device_cmp(const struct rte_device *dev, const void *_pci_id)
1032 const struct rte_pci_device *pdev = RTE_DEV_TO_PCI_CONST(dev);
1033 const struct rte_pci_id *pcid = _pci_id;
1035 if (pdev->id.vendor_id == AMD_PCI_VENDOR_ID &&
1036 pdev->id.device_id == pcid->device_id)
1042 pci_search_device(int device_id)
1044 struct rte_bus *pci_bus;
1045 struct rte_pci_id dev_id;
1047 dev_id.device_id = device_id;
1048 pci_bus = rte_bus_find_by_name("pci");
1049 return (pci_bus != NULL) &&
1050 (pci_bus->find_device(NULL, pci_device_cmp, &dev_id) != NULL);
1054 * It returns 0 on success.
1057 eth_axgbe_dev_init(struct rte_eth_dev *eth_dev)
1059 PMD_INIT_FUNC_TRACE();
1060 struct axgbe_port *pdata;
1061 struct rte_pci_device *pci_dev;
1062 uint32_t reg, mac_lo, mac_hi;
1065 eth_dev->dev_ops = &axgbe_eth_dev_ops;
1068 * For secondary processes, we don't initialise any further as primary
1069 * has already done this work.
1071 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1074 pdata = eth_dev->data->dev_private;
1076 axgbe_set_bit(AXGBE_DOWN, &pdata->dev_state);
1077 axgbe_set_bit(AXGBE_STOPPED, &pdata->dev_state);
1078 pdata->eth_dev = eth_dev;
1080 pci_dev = RTE_DEV_TO_PCI(eth_dev->device);
1081 pdata->pci_dev = pci_dev;
1084 * Use root complex device ID to differentiate RV AXGBE vs SNOWY AXGBE
1086 if (pci_search_device(AMD_PCI_RV_ROOT_COMPLEX_ID)) {
1087 pdata->xpcs_window_def_reg = PCS_V2_RV_WINDOW_DEF;
1088 pdata->xpcs_window_sel_reg = PCS_V2_RV_WINDOW_SELECT;
1090 pdata->xpcs_window_def_reg = PCS_V2_WINDOW_DEF;
1091 pdata->xpcs_window_sel_reg = PCS_V2_WINDOW_SELECT;
1095 (void *)pci_dev->mem_resource[AXGBE_AXGMAC_BAR].addr;
1096 pdata->xprop_regs = (void *)((uint8_t *)pdata->xgmac_regs
1097 + AXGBE_MAC_PROP_OFFSET);
1098 pdata->xi2c_regs = (void *)((uint8_t *)pdata->xgmac_regs
1099 + AXGBE_I2C_CTRL_OFFSET);
1100 pdata->xpcs_regs = (void *)pci_dev->mem_resource[AXGBE_XPCS_BAR].addr;
1102 /* version specific driver data*/
1103 if (pci_dev->id.device_id == AMD_PCI_AXGBE_DEVICE_V2A)
1104 pdata->vdata = &axgbe_v2a;
1106 pdata->vdata = &axgbe_v2b;
1108 /* Configure the PCS indirect addressing support */
1109 reg = XPCS32_IOREAD(pdata, pdata->xpcs_window_def_reg);
1110 pdata->xpcs_window = XPCS_GET_BITS(reg, PCS_V2_WINDOW_DEF, OFFSET);
1111 pdata->xpcs_window <<= 6;
1112 pdata->xpcs_window_size = XPCS_GET_BITS(reg, PCS_V2_WINDOW_DEF, SIZE);
1113 pdata->xpcs_window_size = 1 << (pdata->xpcs_window_size + 7);
1114 pdata->xpcs_window_mask = pdata->xpcs_window_size - 1;
1117 "xpcs window :%x, size :%x, mask :%x ", pdata->xpcs_window,
1118 pdata->xpcs_window_size, pdata->xpcs_window_mask);
1119 XP_IOWRITE(pdata, XP_INT_EN, 0x1fffff);
1121 /* Retrieve the MAC address */
1122 mac_lo = XP_IOREAD(pdata, XP_MAC_ADDR_LO);
1123 mac_hi = XP_IOREAD(pdata, XP_MAC_ADDR_HI);
1124 pdata->mac_addr.addr_bytes[0] = mac_lo & 0xff;
1125 pdata->mac_addr.addr_bytes[1] = (mac_lo >> 8) & 0xff;
1126 pdata->mac_addr.addr_bytes[2] = (mac_lo >> 16) & 0xff;
1127 pdata->mac_addr.addr_bytes[3] = (mac_lo >> 24) & 0xff;
1128 pdata->mac_addr.addr_bytes[4] = mac_hi & 0xff;
1129 pdata->mac_addr.addr_bytes[5] = (mac_hi >> 8) & 0xff;
1131 eth_dev->data->mac_addrs = rte_zmalloc("axgbe_mac_addr",
1132 RTE_ETHER_ADDR_LEN, 0);
1133 if (!eth_dev->data->mac_addrs) {
1135 "Failed to alloc %u bytes needed to store MAC addr tbl",
1136 RTE_ETHER_ADDR_LEN);
1140 if (!rte_is_valid_assigned_ether_addr(&pdata->mac_addr))
1141 rte_eth_random_addr(pdata->mac_addr.addr_bytes);
1143 /* Copy the permanent MAC address */
1144 rte_ether_addr_copy(&pdata->mac_addr, ð_dev->data->mac_addrs[0]);
1146 /* Clock settings */
1147 pdata->sysclk_rate = AXGBE_V2_DMA_CLOCK_FREQ;
1148 pdata->ptpclk_rate = AXGBE_V2_PTP_CLOCK_FREQ;
1150 /* Set the DMA coherency values */
1151 pdata->coherent = 1;
1152 pdata->axdomain = AXGBE_DMA_OS_AXDOMAIN;
1153 pdata->arcache = AXGBE_DMA_OS_ARCACHE;
1154 pdata->awcache = AXGBE_DMA_OS_AWCACHE;
1156 /* Set the maximum channels and queues */
1157 reg = XP_IOREAD(pdata, XP_PROP_1);
1158 pdata->tx_max_channel_count = XP_GET_BITS(reg, XP_PROP_1, MAX_TX_DMA);
1159 pdata->rx_max_channel_count = XP_GET_BITS(reg, XP_PROP_1, MAX_RX_DMA);
1160 pdata->tx_max_q_count = XP_GET_BITS(reg, XP_PROP_1, MAX_TX_QUEUES);
1161 pdata->rx_max_q_count = XP_GET_BITS(reg, XP_PROP_1, MAX_RX_QUEUES);
1163 /* Set the hardware channel and queue counts */
1164 axgbe_set_counts(pdata);
1166 /* Set the maximum fifo amounts */
1167 reg = XP_IOREAD(pdata, XP_PROP_2);
1168 pdata->tx_max_fifo_size = XP_GET_BITS(reg, XP_PROP_2, TX_FIFO_SIZE);
1169 pdata->tx_max_fifo_size *= 16384;
1170 pdata->tx_max_fifo_size = RTE_MIN(pdata->tx_max_fifo_size,
1171 pdata->vdata->tx_max_fifo_size);
1172 pdata->rx_max_fifo_size = XP_GET_BITS(reg, XP_PROP_2, RX_FIFO_SIZE);
1173 pdata->rx_max_fifo_size *= 16384;
1174 pdata->rx_max_fifo_size = RTE_MIN(pdata->rx_max_fifo_size,
1175 pdata->vdata->rx_max_fifo_size);
1176 /* Issue software reset to DMA */
1177 ret = pdata->hw_if.exit(pdata);
1179 PMD_DRV_LOG(ERR, "hw_if->exit EBUSY error\n");
1181 /* Set default configuration data */
1182 axgbe_default_config(pdata);
1184 /* Set default max values if not provided */
1185 if (!pdata->tx_max_fifo_size)
1186 pdata->tx_max_fifo_size = pdata->hw_feat.tx_fifo_size;
1187 if (!pdata->rx_max_fifo_size)
1188 pdata->rx_max_fifo_size = pdata->hw_feat.rx_fifo_size;
1190 pdata->tx_desc_count = AXGBE_MAX_RING_DESC;
1191 pdata->rx_desc_count = AXGBE_MAX_RING_DESC;
1192 pthread_mutex_init(&pdata->xpcs_mutex, NULL);
1193 pthread_mutex_init(&pdata->i2c_mutex, NULL);
1194 pthread_mutex_init(&pdata->an_mutex, NULL);
1195 pthread_mutex_init(&pdata->phy_mutex, NULL);
1197 ret = pdata->phy_if.phy_init(pdata);
1199 rte_free(eth_dev->data->mac_addrs);
1200 eth_dev->data->mac_addrs = NULL;
1204 rte_intr_callback_register(&pci_dev->intr_handle,
1205 axgbe_dev_interrupt_handler,
1207 PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x",
1208 eth_dev->data->port_id, pci_dev->id.vendor_id,
1209 pci_dev->id.device_id);
1215 eth_axgbe_dev_uninit(struct rte_eth_dev *eth_dev)
1217 struct rte_pci_device *pci_dev;
1219 PMD_INIT_FUNC_TRACE();
1221 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1224 pci_dev = RTE_DEV_TO_PCI(eth_dev->device);
1225 eth_dev->dev_ops = NULL;
1226 eth_dev->rx_pkt_burst = NULL;
1227 eth_dev->tx_pkt_burst = NULL;
1228 axgbe_dev_clear_queues(eth_dev);
1230 /* disable uio intr before callback unregister */
1231 rte_intr_disable(&pci_dev->intr_handle);
1232 rte_intr_callback_unregister(&pci_dev->intr_handle,
1233 axgbe_dev_interrupt_handler,
1239 static int eth_axgbe_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
1240 struct rte_pci_device *pci_dev)
1242 return rte_eth_dev_pci_generic_probe(pci_dev,
1243 sizeof(struct axgbe_port), eth_axgbe_dev_init);
1246 static int eth_axgbe_pci_remove(struct rte_pci_device *pci_dev)
1248 return rte_eth_dev_pci_generic_remove(pci_dev, eth_axgbe_dev_uninit);
1251 static struct rte_pci_driver rte_axgbe_pmd = {
1252 .id_table = pci_id_axgbe_map,
1253 .drv_flags = RTE_PCI_DRV_NEED_MAPPING,
1254 .probe = eth_axgbe_pci_probe,
1255 .remove = eth_axgbe_pci_remove,
1258 RTE_PMD_REGISTER_PCI(net_axgbe, rte_axgbe_pmd);
1259 RTE_PMD_REGISTER_PCI_TABLE(net_axgbe, pci_id_axgbe_map);
1260 RTE_PMD_REGISTER_KMOD_DEP(net_axgbe, "* igb_uio | uio_pci_generic | vfio-pci");
1262 RTE_INIT(axgbe_init_log)
1264 axgbe_logtype_init = rte_log_register("pmd.net.axgbe.init");
1265 if (axgbe_logtype_init >= 0)
1266 rte_log_set_level(axgbe_logtype_init, RTE_LOG_NOTICE);
1267 axgbe_logtype_driver = rte_log_register("pmd.net.axgbe.driver");
1268 if (axgbe_logtype_driver >= 0)
1269 rte_log_set_level(axgbe_logtype_driver, RTE_LOG_NOTICE);