drivers/net/bnx2x/bnx2x.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright (c) 2007-2013 Broadcom Corporation.
   3  *
   4  * Eric Davis        <edavis@broadcom.com>
   5  * David Christensen <davidch@broadcom.com>
   6  * Gary Zambrano     <zambrano@broadcom.com>
   7  *
   8  * Copyright (c) 2013-2015 Brocade Communications Systems, Inc.
   9  * Copyright (c) 2015-2018 Cavium Inc.
  10  * All rights reserved.
  11  * www.cavium.com
  12  */
  13
  14 #define BNX2X_DRIVER_VERSION "1.78.18"
  15
  16 #include "bnx2x.h"
  17 #include "bnx2x_vfpf.h"
  18 #include "ecore_sp.h"
  19 #include "ecore_init.h"
  20 #include "ecore_init_ops.h"
  21
  22 #include "rte_version.h"
  23
  24 #include <sys/types.h>
  25 #include <sys/stat.h>
  26 #include <fcntl.h>
  27 #include <zlib.h>
  28 #include <rte_string_fns.h>
  29
  30 #define BNX2X_PMD_VER_PREFIX "BNX2X PMD"
  31 #define BNX2X_PMD_VERSION_MAJOR 1
  32 #define BNX2X_PMD_VERSION_MINOR 0
  33 #define BNX2X_PMD_VERSION_REVISION 7
  34 #define BNX2X_PMD_VERSION_PATCH 1
  35
  36 static inline const char *
  37 bnx2x_pmd_version(void)
  38 {
  39         static char version[32];
  40
  41         snprintf(version, sizeof(version), "%s %s_%d.%d.%d.%d",
  42                         BNX2X_PMD_VER_PREFIX,
  43                         BNX2X_DRIVER_VERSION,
  44                         BNX2X_PMD_VERSION_MAJOR,
  45                         BNX2X_PMD_VERSION_MINOR,
  46                         BNX2X_PMD_VERSION_REVISION,
  47                         BNX2X_PMD_VERSION_PATCH);
  48
  49         return version;
  50 }
  51
  52 static z_stream zlib_stream;
  53
  54 #define EVL_VLID_MASK 0x0FFF
  55
  56 #define BNX2X_DEF_SB_ATT_IDX 0x0001
  57 #define BNX2X_DEF_SB_IDX     0x0002
  58
  59 /*
  60  * FLR Support - bnx2x_pf_flr_clnup() is called during nic_load in the per
  61  * function HW initialization.
  62  */
  63 #define FLR_WAIT_USEC     10000 /* 10 msecs */
  64 #define FLR_WAIT_INTERVAL 50    /* usecs */
  65 #define FLR_POLL_CNT      (FLR_WAIT_USEC / FLR_WAIT_INTERVAL)   /* 200 */
  66
  67 struct pbf_pN_buf_regs {
  68         int pN;
  69         uint32_t init_crd;
  70         uint32_t crd;
  71         uint32_t crd_freed;
  72 };
  73
  74 struct pbf_pN_cmd_regs {
  75         int pN;
  76         uint32_t lines_occup;
  77         uint32_t lines_freed;
  78 };
  79
  80 /* resources needed for unloading a previously loaded device */
  81
  82 #define BNX2X_PREV_WAIT_NEEDED 1
  83 rte_spinlock_t bnx2x_prev_mtx;
  84 struct bnx2x_prev_list_node {
  85         LIST_ENTRY(bnx2x_prev_list_node) node;
  86         uint8_t bus;
  87         uint8_t slot;
  88         uint8_t path;
  89         uint8_t aer;
  90         uint8_t undi;
  91 };
  92
  93 static LIST_HEAD(, bnx2x_prev_list_node) bnx2x_prev_list
  94         = LIST_HEAD_INITIALIZER(bnx2x_prev_list);
  95
  96 static int load_count[2][3] = { { 0 } };
  97         /* per-path: 0-common, 1-port0, 2-port1 */
  98
  99 static void bnx2x_cmng_fns_init(struct bnx2x_softc *sc, uint8_t read_cfg,
 100                                 uint8_t cmng_type);
 101 static int bnx2x_get_cmng_fns_mode(struct bnx2x_softc *sc);
 102 static void storm_memset_cmng(struct bnx2x_softc *sc, struct cmng_init *cmng,
 103                               uint8_t port);
 104 static void bnx2x_set_reset_global(struct bnx2x_softc *sc);
 105 static void bnx2x_set_reset_in_progress(struct bnx2x_softc *sc);
 106 static uint8_t bnx2x_reset_is_done(struct bnx2x_softc *sc, int engine);
 107 static uint8_t bnx2x_clear_pf_load(struct bnx2x_softc *sc);
 108 static uint8_t bnx2x_chk_parity_attn(struct bnx2x_softc *sc, uint8_t * global,
 109                                      uint8_t print);
 110 static void bnx2x_int_disable(struct bnx2x_softc *sc);
 111 static int bnx2x_release_leader_lock(struct bnx2x_softc *sc);
 112 static void bnx2x_pf_disable(struct bnx2x_softc *sc);
 113 static void bnx2x_update_rx_prod(struct bnx2x_softc *sc,
 114                                  struct bnx2x_fastpath *fp,
 115                                  uint16_t rx_bd_prod, uint16_t rx_cq_prod);
 116 static void bnx2x_link_report_locked(struct bnx2x_softc *sc);
 117 static void bnx2x_link_report(struct bnx2x_softc *sc);
 118 void bnx2x_link_status_update(struct bnx2x_softc *sc);
 119 static int bnx2x_alloc_mem(struct bnx2x_softc *sc);
 120 static void bnx2x_free_mem(struct bnx2x_softc *sc);
 121 static int bnx2x_alloc_fw_stats_mem(struct bnx2x_softc *sc);
 122 static void bnx2x_free_fw_stats_mem(struct bnx2x_softc *sc);
 123 static __rte_noinline
 124 int bnx2x_nic_load(struct bnx2x_softc *sc);
 125
 126 static int bnx2x_handle_sp_tq(struct bnx2x_softc *sc);
 127 static void bnx2x_handle_fp_tq(struct bnx2x_fastpath *fp, int scan_fp);
 128 static void bnx2x_ack_sb(struct bnx2x_softc *sc, uint8_t igu_sb_id,
 129                          uint8_t storm, uint16_t index, uint8_t op,
 130                          uint8_t update);
 131
 132 int bnx2x_test_bit(int nr, volatile unsigned long *addr)
 133 {
 134         int res;
 135
 136         mb();
 137         res = ((*addr) & (1UL << nr)) != 0;
 138         mb();
 139         return res;
 140 }
 141
 142 void bnx2x_set_bit(unsigned int nr, volatile unsigned long *addr)
 143 {
 144         __sync_fetch_and_or(addr, (1UL << nr));
 145 }
 146
 147 void bnx2x_clear_bit(int nr, volatile unsigned long *addr)
 148 {
 149         __sync_fetch_and_and(addr, ~(1UL << nr));
 150 }
 151
 152 int bnx2x_test_and_clear_bit(int nr, volatile unsigned long *addr)
 153 {
 154         unsigned long mask = (1UL << nr);
 155         return __sync_fetch_and_and(addr, ~mask) & mask;
 156 }
 157
 158 int bnx2x_cmpxchg(volatile int *addr, int old, int new)
 159 {
 160         return __sync_val_compare_and_swap(addr, old, new);
 161 }
 162
 163 int
 164 bnx2x_dma_alloc(struct bnx2x_softc *sc, size_t size, struct bnx2x_dma *dma,
 165               const char *msg, uint32_t align)
 166 {
 167         char mz_name[RTE_MEMZONE_NAMESIZE];
 168         const struct rte_memzone *z;
 169
 170         dma->sc = sc;
 171         if (IS_PF(sc))
 172                 snprintf(mz_name, sizeof(mz_name), "bnx2x%d_%s_%" PRIx64, SC_ABS_FUNC(sc), msg,
 173                         rte_get_timer_cycles());
 174         else
 175                 snprintf(mz_name, sizeof(mz_name), "bnx2x%d_%s_%" PRIx64, sc->pcie_device, msg,
 176                         rte_get_timer_cycles());
 177
 178         /* Caller must take care that strlen(mz_name) < RTE_MEMZONE_NAMESIZE */
 179         z = rte_memzone_reserve_aligned(mz_name, (uint64_t)size,
 180                                         SOCKET_ID_ANY,
 181                                         RTE_MEMZONE_IOVA_CONTIG, align);
 182         if (z == NULL) {
 183                 PMD_DRV_LOG(ERR, sc, "DMA alloc failed for %s", msg);
 184                 return -ENOMEM;
 185         }
 186         dma->paddr = (uint64_t) z->iova;
 187         dma->vaddr = z->addr;
 188         dma->mzone = (const void *)z;
 189
 190         PMD_DRV_LOG(DEBUG, sc,
 191                     "%s: virt=%p phys=%" PRIx64, msg, dma->vaddr, dma->paddr);
 192
 193         return 0;
 194 }
 195
 196 void bnx2x_dma_free(struct bnx2x_dma *dma)
 197 {
 198         if (dma->mzone == NULL)
 199                 return;
 200
 201         rte_memzone_free((const struct rte_memzone *)dma->mzone);
 202         dma->sc = NULL;
 203         dma->paddr = 0;
 204         dma->vaddr = NULL;
 205         dma->nseg = 0;
 206         dma->mzone = NULL;
 207 }
 208
 209 static int bnx2x_acquire_hw_lock(struct bnx2x_softc *sc, uint32_t resource)
 210 {
 211         uint32_t lock_status;
 212         uint32_t resource_bit = (1 << resource);
 213         int func = SC_FUNC(sc);
 214         uint32_t hw_lock_control_reg;
 215         int cnt;
 216
 217 #ifndef RTE_LIBRTE_BNX2X_DEBUG_PERIODIC
 218         if (resource)
 219                 PMD_INIT_FUNC_TRACE(sc);
 220 #else
 221         PMD_INIT_FUNC_TRACE(sc);
 222 #endif
 223
 224         /* validate the resource is within range */
 225         if (resource > HW_LOCK_MAX_RESOURCE_VALUE) {
 226                 PMD_DRV_LOG(NOTICE, sc,
 227                             "resource 0x%x > HW_LOCK_MAX_RESOURCE_VALUE",
 228                             resource);
 229                 return -1;
 230         }
 231
 232         if (func <= 5) {
 233                 hw_lock_control_reg = (MISC_REG_DRIVER_CONTROL_1 + (func * 8));
 234         } else {
 235                 hw_lock_control_reg =
 236                     (MISC_REG_DRIVER_CONTROL_7 + ((func - 6) * 8));
 237         }
 238
 239         /* validate the resource is not already taken */
 240         lock_status = REG_RD(sc, hw_lock_control_reg);
 241         if (lock_status & resource_bit) {
 242                 PMD_DRV_LOG(NOTICE, sc,
 243                             "resource in use (status 0x%x bit 0x%x)",
 244                             lock_status, resource_bit);
 245                 return -1;
 246         }
 247
 248         /* try every 5ms for 5 seconds */
 249         for (cnt = 0; cnt < 1000; cnt++) {
 250                 REG_WR(sc, (hw_lock_control_reg + 4), resource_bit);
 251                 lock_status = REG_RD(sc, hw_lock_control_reg);
 252                 if (lock_status & resource_bit) {
 253                         return 0;
 254                 }
 255                 DELAY(5000);
 256         }
 257
 258         PMD_DRV_LOG(NOTICE, sc, "Resource 0x%x resource_bit 0x%x lock timeout!",
 259                     resource, resource_bit);
 260         return -1;
 261 }
 262
 263 static int bnx2x_release_hw_lock(struct bnx2x_softc *sc, uint32_t resource)
 264 {
 265         uint32_t lock_status;
 266         uint32_t resource_bit = (1 << resource);
 267         int func = SC_FUNC(sc);
 268         uint32_t hw_lock_control_reg;
 269
 270 #ifndef RTE_LIBRTE_BNX2X_DEBUG_PERIODIC
 271         if (resource)
 272                 PMD_INIT_FUNC_TRACE(sc);
 273 #else
 274         PMD_INIT_FUNC_TRACE(sc);
 275 #endif
 276
 277         /* validate the resource is within range */
 278         if (resource > HW_LOCK_MAX_RESOURCE_VALUE) {
 279                 PMD_DRV_LOG(NOTICE, sc,
 280                             "(resource 0x%x > HW_LOCK_MAX_RESOURCE_VALUE)"
 281                             " resource_bit 0x%x", resource, resource_bit);
 282                 return -1;
 283         }
 284
 285         if (func <= 5) {
 286                 hw_lock_control_reg = (MISC_REG_DRIVER_CONTROL_1 + (func * 8));
 287         } else {
 288                 hw_lock_control_reg =
 289                     (MISC_REG_DRIVER_CONTROL_7 + ((func - 6) * 8));
 290         }
 291
 292         /* validate the resource is currently taken */
 293         lock_status = REG_RD(sc, hw_lock_control_reg);
 294         if (!(lock_status & resource_bit)) {
 295                 PMD_DRV_LOG(NOTICE, sc,
 296                             "resource not in use (status 0x%x bit 0x%x)",
 297                             lock_status, resource_bit);
 298                 return -1;
 299         }
 300
 301         REG_WR(sc, hw_lock_control_reg, resource_bit);
 302         return 0;
 303 }
 304
 305 static void bnx2x_acquire_phy_lock(struct bnx2x_softc *sc)
 306 {
 307         BNX2X_PHY_LOCK(sc);
 308         bnx2x_acquire_hw_lock(sc, HW_LOCK_RESOURCE_MDIO);
 309 }
 310
 311 static void bnx2x_release_phy_lock(struct bnx2x_softc *sc)
 312 {
 313         bnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_MDIO);
 314         BNX2X_PHY_UNLOCK(sc);
 315 }
 316
 317 /* copy command into DMAE command memory and set DMAE command Go */
 318 void bnx2x_post_dmae(struct bnx2x_softc *sc, struct dmae_command *dmae, int idx)
 319 {
 320         uint32_t cmd_offset;
 321         uint32_t i;
 322
 323         cmd_offset = (DMAE_REG_CMD_MEM + (sizeof(struct dmae_command) * idx));
 324         for (i = 0; i < ((sizeof(struct dmae_command) / 4)); i++) {
 325                 REG_WR(sc, (cmd_offset + (i * 4)), *(((uint32_t *) dmae) + i));
 326         }
 327
 328         REG_WR(sc, dmae_reg_go_c[idx], 1);
 329 }
 330
 331 uint32_t bnx2x_dmae_opcode_add_comp(uint32_t opcode, uint8_t comp_type)
 332 {
 333         return opcode | ((comp_type << DMAE_COMMAND_C_DST_SHIFT) |
 334                           DMAE_COMMAND_C_TYPE_ENABLE);
 335 }
 336
 337 uint32_t bnx2x_dmae_opcode_clr_src_reset(uint32_t opcode)
 338 {
 339         return opcode & ~DMAE_COMMAND_SRC_RESET;
 340 }
 341
 342 uint32_t
 343 bnx2x_dmae_opcode(struct bnx2x_softc * sc, uint8_t src_type, uint8_t dst_type,
 344                 uint8_t with_comp, uint8_t comp_type)
 345 {
 346         uint32_t opcode = 0;
 347
 348         opcode |= ((src_type << DMAE_COMMAND_SRC_SHIFT) |
 349                    (dst_type << DMAE_COMMAND_DST_SHIFT));
 350
 351         opcode |= (DMAE_COMMAND_SRC_RESET | DMAE_COMMAND_DST_RESET);
 352
 353         opcode |= (SC_PORT(sc) ? DMAE_CMD_PORT_1 : DMAE_CMD_PORT_0);
 354
 355         opcode |= ((SC_VN(sc) << DMAE_COMMAND_E1HVN_SHIFT) |
 356                    (SC_VN(sc) << DMAE_COMMAND_DST_VN_SHIFT));
 357
 358         opcode |= (DMAE_COM_SET_ERR << DMAE_COMMAND_ERR_POLICY_SHIFT);
 359
 360 #ifdef __BIG_ENDIAN
 361         opcode |= DMAE_CMD_ENDIANITY_B_DW_SWAP;
 362 #else
 363         opcode |= DMAE_CMD_ENDIANITY_DW_SWAP;
 364 #endif
 365
 366         if (with_comp) {
 367                 opcode = bnx2x_dmae_opcode_add_comp(opcode, comp_type);
 368         }
 369
 370         return opcode;
 371 }
 372
 373 static void
 374 bnx2x_prep_dmae_with_comp(struct bnx2x_softc *sc, struct dmae_command *dmae,
 375                         uint8_t src_type, uint8_t dst_type)
 376 {
 377         memset(dmae, 0, sizeof(struct dmae_command));
 378
 379         /* set the opcode */
 380         dmae->opcode = bnx2x_dmae_opcode(sc, src_type, dst_type,
 381                                        TRUE, DMAE_COMP_PCI);
 382
 383         /* fill in the completion parameters */
 384         dmae->comp_addr_lo = U64_LO(BNX2X_SP_MAPPING(sc, wb_comp));
 385         dmae->comp_addr_hi = U64_HI(BNX2X_SP_MAPPING(sc, wb_comp));
 386         dmae->comp_val = DMAE_COMP_VAL;
 387 }
 388
 389 /* issue a DMAE command over the init channel and wait for completion */
 390 static int
 391 bnx2x_issue_dmae_with_comp(struct bnx2x_softc *sc, struct dmae_command *dmae)
 392 {
 393         uint32_t *wb_comp = BNX2X_SP(sc, wb_comp);
 394         int timeout = CHIP_REV_IS_SLOW(sc) ? 400000 : 4000;
 395
 396         /* reset completion */
 397         *wb_comp = 0;
 398
 399         /* post the command on the channel used for initializations */
 400         bnx2x_post_dmae(sc, dmae, INIT_DMAE_C(sc));
 401
 402         /* wait for completion */
 403         DELAY(500);
 404
 405         while ((*wb_comp & ~DMAE_PCI_ERR_FLAG) != DMAE_COMP_VAL) {
 406                 if (!timeout ||
 407                     (sc->recovery_state != BNX2X_RECOVERY_DONE &&
 408                      sc->recovery_state != BNX2X_RECOVERY_NIC_LOADING)) {
 409                         PMD_DRV_LOG(INFO, sc, "DMAE timeout!");
 410                         return DMAE_TIMEOUT;
 411                 }
 412
 413                 timeout--;
 414                 DELAY(50);
 415         }
 416
 417         if (*wb_comp & DMAE_PCI_ERR_FLAG) {
 418                 PMD_DRV_LOG(INFO, sc, "DMAE PCI error!");
 419                 return DMAE_PCI_ERROR;
 420         }
 421
 422         return 0;
 423 }
 424
 425 void bnx2x_read_dmae(struct bnx2x_softc *sc, uint32_t src_addr, uint32_t len32)
 426 {
 427         struct dmae_command dmae;
 428         uint32_t *data;
 429         uint32_t i;
 430         int rc;
 431
 432         if (!sc->dmae_ready) {
 433                 data = BNX2X_SP(sc, wb_data[0]);
 434
 435                 for (i = 0; i < len32; i++) {
 436                         data[i] = REG_RD(sc, (src_addr + (i * 4)));
 437                 }
 438
 439                 return;
 440         }
 441
 442         /* set opcode and fixed command fields */
 443         bnx2x_prep_dmae_with_comp(sc, &dmae, DMAE_SRC_GRC, DMAE_DST_PCI);
 444
 445         /* fill in addresses and len */
 446         dmae.src_addr_lo = (src_addr >> 2);     /* GRC addr has dword resolution */
 447         dmae.src_addr_hi = 0;
 448         dmae.dst_addr_lo = U64_LO(BNX2X_SP_MAPPING(sc, wb_data));
 449         dmae.dst_addr_hi = U64_HI(BNX2X_SP_MAPPING(sc, wb_data));
 450         dmae.len = len32;
 451
 452         /* issue the command and wait for completion */
 453         if ((rc = bnx2x_issue_dmae_with_comp(sc, &dmae)) != 0) {
 454                 rte_panic("DMAE failed (%d)", rc);
 455         };
 456 }
 457
 458 void
 459 bnx2x_write_dmae(struct bnx2x_softc *sc, rte_iova_t dma_addr, uint32_t dst_addr,
 460                uint32_t len32)
 461 {
 462         struct dmae_command dmae;
 463         int rc;
 464
 465         if (!sc->dmae_ready) {
 466                 ecore_init_str_wr(sc, dst_addr, BNX2X_SP(sc, wb_data[0]), len32);
 467                 return;
 468         }
 469
 470         /* set opcode and fixed command fields */
 471         bnx2x_prep_dmae_with_comp(sc, &dmae, DMAE_SRC_PCI, DMAE_DST_GRC);
 472
 473         /* fill in addresses and len */
 474         dmae.src_addr_lo = U64_LO(dma_addr);
 475         dmae.src_addr_hi = U64_HI(dma_addr);
 476         dmae.dst_addr_lo = (dst_addr >> 2);     /* GRC addr has dword resolution */
 477         dmae.dst_addr_hi = 0;
 478         dmae.len = len32;
 479
 480         /* issue the command and wait for completion */
 481         if ((rc = bnx2x_issue_dmae_with_comp(sc, &dmae)) != 0) {
 482                 rte_panic("DMAE failed (%d)", rc);
 483         }
 484 }
 485
 486 static void
 487 bnx2x_write_dmae_phys_len(struct bnx2x_softc *sc, rte_iova_t phys_addr,
 488                         uint32_t addr, uint32_t len)
 489 {
 490         uint32_t dmae_wr_max = DMAE_LEN32_WR_MAX(sc);
 491         uint32_t offset = 0;
 492
 493         while (len > dmae_wr_max) {
 494                 bnx2x_write_dmae(sc, (phys_addr + offset),      /* src DMA address */
 495                                (addr + offset), /* dst GRC address */
 496                                dmae_wr_max);
 497                 offset += (dmae_wr_max * 4);
 498                 len -= dmae_wr_max;
 499         }
 500
 501         bnx2x_write_dmae(sc, (phys_addr + offset),      /* src DMA address */
 502                        (addr + offset), /* dst GRC address */
 503                        len);
 504 }
 505
 506 void
 507 bnx2x_set_ctx_validation(struct bnx2x_softc *sc, struct eth_context *cxt,
 508                        uint32_t cid)
 509 {
 510         /* ustorm cxt validation */
 511         cxt->ustorm_ag_context.cdu_usage =
 512             CDU_RSRVD_VALUE_TYPE_A(HW_CID(sc, cid),
 513                                    CDU_REGION_NUMBER_UCM_AG,
 514                                    ETH_CONNECTION_TYPE);
 515         /* xcontext validation */
 516         cxt->xstorm_ag_context.cdu_reserved =
 517             CDU_RSRVD_VALUE_TYPE_A(HW_CID(sc, cid),
 518                                    CDU_REGION_NUMBER_XCM_AG,
 519                                    ETH_CONNECTION_TYPE);
 520 }
 521
 522 static void
 523 bnx2x_storm_memset_hc_timeout(struct bnx2x_softc *sc, uint8_t fw_sb_id,
 524                             uint8_t sb_index, uint8_t ticks)
 525 {
 526         uint32_t addr =
 527             (BAR_CSTRORM_INTMEM +
 528              CSTORM_STATUS_BLOCK_DATA_TIMEOUT_OFFSET(fw_sb_id, sb_index));
 529
 530         REG_WR8(sc, addr, ticks);
 531 }
 532
 533 static void
 534 bnx2x_storm_memset_hc_disable(struct bnx2x_softc *sc, uint16_t fw_sb_id,
 535                             uint8_t sb_index, uint8_t disable)
 536 {
 537         uint32_t enable_flag =
 538             (disable) ? 0 : (1 << HC_INDEX_DATA_HC_ENABLED_SHIFT);
 539         uint32_t addr =
 540             (BAR_CSTRORM_INTMEM +
 541              CSTORM_STATUS_BLOCK_DATA_FLAGS_OFFSET(fw_sb_id, sb_index));
 542         uint8_t flags;
 543
 544         /* clear and set */
 545         flags = REG_RD8(sc, addr);
 546         flags &= ~HC_INDEX_DATA_HC_ENABLED;
 547         flags |= enable_flag;
 548         REG_WR8(sc, addr, flags);
 549 }
 550
 551 void
 552 bnx2x_update_coalesce_sb_index(struct bnx2x_softc *sc, uint8_t fw_sb_id,
 553                              uint8_t sb_index, uint8_t disable, uint16_t usec)
 554 {
 555         uint8_t ticks = (usec / 4);
 556
 557         bnx2x_storm_memset_hc_timeout(sc, fw_sb_id, sb_index, ticks);
 558
 559         disable = (disable) ? 1 : ((usec) ? 0 : 1);
 560         bnx2x_storm_memset_hc_disable(sc, fw_sb_id, sb_index, disable);
 561 }
 562
 563 uint32_t elink_cb_reg_read(struct bnx2x_softc *sc, uint32_t reg_addr)
 564 {
 565         return REG_RD(sc, reg_addr);
 566 }
 567
 568 void elink_cb_reg_write(struct bnx2x_softc *sc, uint32_t reg_addr, uint32_t val)
 569 {
 570         REG_WR(sc, reg_addr, val);
 571 }
 572
 573 void
 574 elink_cb_event_log(__rte_unused struct bnx2x_softc *sc,
 575                    __rte_unused const elink_log_id_t elink_log_id, ...)
 576 {
 577         PMD_DRV_LOG(DEBUG, sc, "ELINK EVENT LOG (%d)", elink_log_id);
 578 }
 579
 580 static int bnx2x_set_spio(struct bnx2x_softc *sc, int spio, uint32_t mode)
 581 {
 582         uint32_t spio_reg;
 583
 584         /* Only 2 SPIOs are configurable */
 585         if ((spio != MISC_SPIO_SPIO4) && (spio != MISC_SPIO_SPIO5)) {
 586                 PMD_DRV_LOG(NOTICE, sc, "Invalid SPIO 0x%x", spio);
 587                 return -1;
 588         }
 589
 590         bnx2x_acquire_hw_lock(sc, HW_LOCK_RESOURCE_SPIO);
 591
 592         /* read SPIO and mask except the float bits */
 593         spio_reg = (REG_RD(sc, MISC_REG_SPIO) & MISC_SPIO_FLOAT);
 594
 595         switch (mode) {
 596         case MISC_SPIO_OUTPUT_LOW:
 597                 /* clear FLOAT and set CLR */
 598                 spio_reg &= ~(spio << MISC_SPIO_FLOAT_POS);
 599                 spio_reg |= (spio << MISC_SPIO_CLR_POS);
 600                 break;
 601
 602         case MISC_SPIO_OUTPUT_HIGH:
 603                 /* clear FLOAT and set SET */
 604                 spio_reg &= ~(spio << MISC_SPIO_FLOAT_POS);
 605                 spio_reg |= (spio << MISC_SPIO_SET_POS);
 606                 break;
 607
 608         case MISC_SPIO_INPUT_HI_Z:
 609                 /* set FLOAT */
 610                 spio_reg |= (spio << MISC_SPIO_FLOAT_POS);
 611                 break;
 612
 613         default:
 614                 break;
 615         }
 616
 617         REG_WR(sc, MISC_REG_SPIO, spio_reg);
 618         bnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_SPIO);
 619
 620         return 0;
 621 }
 622
 623 static int bnx2x_gpio_read(struct bnx2x_softc *sc, int gpio_num, uint8_t port)
 624 {
 625         /* The GPIO should be swapped if swap register is set and active */
 626         int gpio_port = ((REG_RD(sc, NIG_REG_PORT_SWAP) &&
 627                           REG_RD(sc, NIG_REG_STRAP_OVERRIDE)) ^ port);
 628         int gpio_shift = gpio_num;
 629         if (gpio_port)
 630                 gpio_shift += MISC_REGISTERS_GPIO_PORT_SHIFT;
 631
 632         uint32_t gpio_mask = (1 << gpio_shift);
 633         uint32_t gpio_reg;
 634
 635         if (gpio_num > MISC_REGISTERS_GPIO_3) {
 636                 PMD_DRV_LOG(NOTICE, sc, "Invalid GPIO %d", gpio_num);
 637                 return -1;
 638         }
 639
 640         /* read GPIO value */
 641         gpio_reg = REG_RD(sc, MISC_REG_GPIO);
 642
 643         /* get the requested pin value */
 644         return ((gpio_reg & gpio_mask) == gpio_mask) ? 1 : 0;
 645 }
 646
 647 static int
 648 bnx2x_gpio_write(struct bnx2x_softc *sc, int gpio_num, uint32_t mode, uint8_t port)
 649 {
 650         /* The GPIO should be swapped if swap register is set and active */
 651         int gpio_port = ((REG_RD(sc, NIG_REG_PORT_SWAP) &&
 652                           REG_RD(sc, NIG_REG_STRAP_OVERRIDE)) ^ port);
 653         int gpio_shift = gpio_num;
 654         if (gpio_port)
 655                 gpio_shift += MISC_REGISTERS_GPIO_PORT_SHIFT;
 656
 657         uint32_t gpio_mask = (1 << gpio_shift);
 658         uint32_t gpio_reg;
 659
 660         if (gpio_num > MISC_REGISTERS_GPIO_3) {
 661                 PMD_DRV_LOG(NOTICE, sc, "Invalid GPIO %d", gpio_num);
 662                 return -1;
 663         }
 664
 665         bnx2x_acquire_hw_lock(sc, HW_LOCK_RESOURCE_GPIO);
 666
 667         /* read GPIO and mask except the float bits */
 668         gpio_reg = (REG_RD(sc, MISC_REG_GPIO) & MISC_REGISTERS_GPIO_FLOAT);
 669
 670         switch (mode) {
 671         case MISC_REGISTERS_GPIO_OUTPUT_LOW:
 672                 /* clear FLOAT and set CLR */
 673                 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS);
 674                 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_CLR_POS);
 675                 break;
 676
 677         case MISC_REGISTERS_GPIO_OUTPUT_HIGH:
 678                 /* clear FLOAT and set SET */
 679                 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS);
 680                 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_SET_POS);
 681                 break;
 682
 683         case MISC_REGISTERS_GPIO_INPUT_HI_Z:
 684                 /* set FLOAT */
 685                 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS);
 686                 break;
 687
 688         default:
 689                 break;
 690         }
 691
 692         REG_WR(sc, MISC_REG_GPIO, gpio_reg);
 693         bnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_GPIO);
 694
 695         return 0;
 696 }
 697
 698 static int
 699 bnx2x_gpio_mult_write(struct bnx2x_softc *sc, uint8_t pins, uint32_t mode)
 700 {
 701         uint32_t gpio_reg;
 702
 703         /* any port swapping should be handled by caller */
 704
 705         bnx2x_acquire_hw_lock(sc, HW_LOCK_RESOURCE_GPIO);
 706
 707         /* read GPIO and mask except the float bits */
 708         gpio_reg = REG_RD(sc, MISC_REG_GPIO);
 709         gpio_reg &= ~(pins << MISC_REGISTERS_GPIO_FLOAT_POS);
 710         gpio_reg &= ~(pins << MISC_REGISTERS_GPIO_CLR_POS);
 711         gpio_reg &= ~(pins << MISC_REGISTERS_GPIO_SET_POS);
 712
 713         switch (mode) {
 714         case MISC_REGISTERS_GPIO_OUTPUT_LOW:
 715                 /* set CLR */
 716                 gpio_reg |= (pins << MISC_REGISTERS_GPIO_CLR_POS);
 717                 break;
 718
 719         case MISC_REGISTERS_GPIO_OUTPUT_HIGH:
 720                 /* set SET */
 721                 gpio_reg |= (pins << MISC_REGISTERS_GPIO_SET_POS);
 722                 break;
 723
 724         case MISC_REGISTERS_GPIO_INPUT_HI_Z:
 725                 /* set FLOAT */
 726                 gpio_reg |= (pins << MISC_REGISTERS_GPIO_FLOAT_POS);
 727                 break;
 728
 729         default:
 730                 PMD_DRV_LOG(NOTICE, sc,
 731                             "Invalid GPIO mode assignment %d", mode);
 732                 bnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_GPIO);
 733                 return -1;
 734         }
 735
 736         REG_WR(sc, MISC_REG_GPIO, gpio_reg);
 737         bnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_GPIO);
 738
 739         return 0;
 740 }
 741
 742 static int
 743 bnx2x_gpio_int_write(struct bnx2x_softc *sc, int gpio_num, uint32_t mode,
 744                    uint8_t port)
 745 {
 746         /* The GPIO should be swapped if swap register is set and active */
 747         int gpio_port = ((REG_RD(sc, NIG_REG_PORT_SWAP) &&
 748                           REG_RD(sc, NIG_REG_STRAP_OVERRIDE)) ^ port);
 749         int gpio_shift = gpio_num;
 750         if (gpio_port)
 751                 gpio_shift += MISC_REGISTERS_GPIO_PORT_SHIFT;
 752
 753         uint32_t gpio_mask = (1 << gpio_shift);
 754         uint32_t gpio_reg;
 755
 756         if (gpio_num > MISC_REGISTERS_GPIO_3) {
 757                 PMD_DRV_LOG(NOTICE, sc, "Invalid GPIO %d", gpio_num);
 758                 return -1;
 759         }
 760
 761         bnx2x_acquire_hw_lock(sc, HW_LOCK_RESOURCE_GPIO);
 762
 763         /* read GPIO int */
 764         gpio_reg = REG_RD(sc, MISC_REG_GPIO_INT);
 765
 766         switch (mode) {
 767         case MISC_REGISTERS_GPIO_INT_OUTPUT_CLR:
 768                 /* clear SET and set CLR */
 769                 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_INT_SET_POS);
 770                 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_INT_CLR_POS);
 771                 break;
 772
 773         case MISC_REGISTERS_GPIO_INT_OUTPUT_SET:
 774                 /* clear CLR and set SET */
 775                 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_INT_CLR_POS);
 776                 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_INT_SET_POS);
 777                 break;
 778
 779         default:
 780                 break;
 781         }
 782
 783         REG_WR(sc, MISC_REG_GPIO_INT, gpio_reg);
 784         bnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_GPIO);
 785
 786         return 0;
 787 }
 788
 789 uint32_t
 790 elink_cb_gpio_read(struct bnx2x_softc * sc, uint16_t gpio_num, uint8_t port)
 791 {
 792         return bnx2x_gpio_read(sc, gpio_num, port);
 793 }
 794
 795 uint8_t elink_cb_gpio_write(struct bnx2x_softc * sc, uint16_t gpio_num, uint8_t mode,   /* 0=low 1=high */
 796                             uint8_t port)
 797 {
 798         return bnx2x_gpio_write(sc, gpio_num, mode, port);
 799 }
 800
 801 uint8_t
 802 elink_cb_gpio_mult_write(struct bnx2x_softc * sc, uint8_t pins,
 803                          uint8_t mode /* 0=low 1=high */ )
 804 {
 805         return bnx2x_gpio_mult_write(sc, pins, mode);
 806 }
 807
 808 uint8_t elink_cb_gpio_int_write(struct bnx2x_softc * sc, uint16_t gpio_num, uint8_t mode,       /* 0=low 1=high */
 809                                 uint8_t port)
 810 {
 811         return bnx2x_gpio_int_write(sc, gpio_num, mode, port);
 812 }
 813
 814 void elink_cb_notify_link_changed(struct bnx2x_softc *sc)
 815 {
 816         REG_WR(sc, (MISC_REG_AEU_GENERAL_ATTN_12 +
 817                     (SC_FUNC(sc) * sizeof(uint32_t))), 1);
 818 }
 819
 820 /* send the MCP a request, block until there is a reply */
 821 uint32_t
 822 elink_cb_fw_command(struct bnx2x_softc *sc, uint32_t command, uint32_t param)
 823 {
 824         int mb_idx = SC_FW_MB_IDX(sc);
 825         uint32_t seq;
 826         uint32_t rc = 0;
 827         uint32_t cnt = 1;
 828         uint8_t delay = CHIP_REV_IS_SLOW(sc) ? 100 : 10;
 829
 830         seq = ++sc->fw_seq;
 831         SHMEM_WR(sc, func_mb[mb_idx].drv_mb_param, param);
 832         SHMEM_WR(sc, func_mb[mb_idx].drv_mb_header, (command | seq));
 833
 834         PMD_DRV_LOG(DEBUG, sc,
 835                     "wrote command 0x%08x to FW MB param 0x%08x",
 836                     (command | seq), param);
 837
 838         /* Let the FW do it's magic. GIve it up to 5 seconds... */
 839         do {
 840                 DELAY(delay * 1000);
 841                 rc = SHMEM_RD(sc, func_mb[mb_idx].fw_mb_header);
 842         } while ((seq != (rc & FW_MSG_SEQ_NUMBER_MASK)) && (cnt++ < 500));
 843
 844         /* is this a reply to our command? */
 845         if (seq == (rc & FW_MSG_SEQ_NUMBER_MASK)) {
 846                 rc &= FW_MSG_CODE_MASK;
 847         } else {
 848                 /* Ruh-roh! */
 849                 PMD_DRV_LOG(NOTICE, sc, "FW failed to respond!");
 850                 rc = 0;
 851         }
 852
 853         return rc;
 854 }
 855
 856 static uint32_t
 857 bnx2x_fw_command(struct bnx2x_softc *sc, uint32_t command, uint32_t param)
 858 {
 859         return elink_cb_fw_command(sc, command, param);
 860 }
 861
 862 static void
 863 __storm_memset_dma_mapping(struct bnx2x_softc *sc, uint32_t addr,
 864                            rte_iova_t mapping)
 865 {
 866         REG_WR(sc, addr, U64_LO(mapping));
 867         REG_WR(sc, (addr + 4), U64_HI(mapping));
 868 }
 869
 870 static void
 871 storm_memset_spq_addr(struct bnx2x_softc *sc, rte_iova_t mapping,
 872                       uint16_t abs_fid)
 873 {
 874         uint32_t addr = (XSEM_REG_FAST_MEMORY +
 875                          XSTORM_SPQ_PAGE_BASE_OFFSET(abs_fid));
 876         __storm_memset_dma_mapping(sc, addr, mapping);
 877 }
 878
 879 static void
 880 storm_memset_vf_to_pf(struct bnx2x_softc *sc, uint16_t abs_fid, uint16_t pf_id)
 881 {
 882         REG_WR8(sc, (BAR_XSTRORM_INTMEM + XSTORM_VF_TO_PF_OFFSET(abs_fid)),
 883                 pf_id);
 884         REG_WR8(sc, (BAR_CSTRORM_INTMEM + CSTORM_VF_TO_PF_OFFSET(abs_fid)),
 885                 pf_id);
 886         REG_WR8(sc, (BAR_TSTRORM_INTMEM + TSTORM_VF_TO_PF_OFFSET(abs_fid)),
 887                 pf_id);
 888         REG_WR8(sc, (BAR_USTRORM_INTMEM + USTORM_VF_TO_PF_OFFSET(abs_fid)),
 889                 pf_id);
 890 }
 891
 892 static void
 893 storm_memset_func_en(struct bnx2x_softc *sc, uint16_t abs_fid, uint8_t enable)
 894 {
 895         REG_WR8(sc, (BAR_XSTRORM_INTMEM + XSTORM_FUNC_EN_OFFSET(abs_fid)),
 896                 enable);
 897         REG_WR8(sc, (BAR_CSTRORM_INTMEM + CSTORM_FUNC_EN_OFFSET(abs_fid)),
 898                 enable);
 899         REG_WR8(sc, (BAR_TSTRORM_INTMEM + TSTORM_FUNC_EN_OFFSET(abs_fid)),
 900                 enable);
 901         REG_WR8(sc, (BAR_USTRORM_INTMEM + USTORM_FUNC_EN_OFFSET(abs_fid)),
 902                 enable);
 903 }
 904
 905 static void
 906 storm_memset_eq_data(struct bnx2x_softc *sc, struct event_ring_data *eq_data,
 907                      uint16_t pfid)
 908 {
 909         uint32_t addr;
 910         size_t size;
 911
 912         addr = (BAR_CSTRORM_INTMEM + CSTORM_EVENT_RING_DATA_OFFSET(pfid));
 913         size = sizeof(struct event_ring_data);
 914         ecore_storm_memset_struct(sc, addr, size, (uint32_t *) eq_data);
 915 }
 916
 917 static void
 918 storm_memset_eq_prod(struct bnx2x_softc *sc, uint16_t eq_prod, uint16_t pfid)
 919 {
 920         uint32_t addr = (BAR_CSTRORM_INTMEM +
 921                          CSTORM_EVENT_RING_PROD_OFFSET(pfid));
 922         REG_WR16(sc, addr, eq_prod);
 923 }
 924
 925 /*
 926  * Post a slowpath command.
 927  *
 928  * A slowpath command is used to propagate a configuration change through
 929  * the controller in a controlled manner, allowing each STORM processor and
 930  * other H/W blocks to phase in the change.  The commands sent on the
 931  * slowpath are referred to as ramrods.  Depending on the ramrod used the
 932  * completion of the ramrod will occur in different ways.  Here's a
 933  * breakdown of ramrods and how they complete:
 934  *
 935  * RAMROD_CMD_ID_ETH_PORT_SETUP
 936  *   Used to setup the leading connection on a port.  Completes on the
 937  *   Receive Completion Queue (RCQ) of that port (typically fp[0]).
 938  *
 939  * RAMROD_CMD_ID_ETH_CLIENT_SETUP
 940  *   Used to setup an additional connection on a port.  Completes on the
 941  *   RCQ of the multi-queue/RSS connection being initialized.
 942  *
 943  * RAMROD_CMD_ID_ETH_STAT_QUERY
 944  *   Used to force the storm processors to update the statistics database
 945  *   in host memory.  This ramrod is send on the leading connection CID and
 946  *   completes as an index increment of the CSTORM on the default status
 947  *   block.
 948  *
 949  * RAMROD_CMD_ID_ETH_UPDATE
 950  *   Used to update the state of the leading connection, usually to udpate
 951  *   the RSS indirection table.  Completes on the RCQ of the leading
 952  *   connection. (Not currently used under FreeBSD until OS support becomes
 953  *   available.)
 954  *
 955  * RAMROD_CMD_ID_ETH_HALT
 956  *   Used when tearing down a connection prior to driver unload.  Completes
 957  *   on the RCQ of the multi-queue/RSS connection being torn down.  Don't
 958  *   use this on the leading connection.
 959  *
 960  * RAMROD_CMD_ID_ETH_SET_MAC
 961  *   Sets the Unicast/Broadcast/Multicast used by the port.  Completes on
 962  *   the RCQ of the leading connection.
 963  *
 964  * RAMROD_CMD_ID_ETH_CFC_DEL
 965  *   Used when tearing down a conneciton prior to driver unload.  Completes
 966  *   on the RCQ of the leading connection (since the current connection
 967  *   has been completely removed from controller memory).
 968  *
 969  * RAMROD_CMD_ID_ETH_PORT_DEL
 970  *   Used to tear down the leading connection prior to driver unload,
 971  *   typically fp[0].  Completes as an index increment of the CSTORM on the
 972  *   default status block.
 973  *
 974  * RAMROD_CMD_ID_ETH_FORWARD_SETUP
 975  *   Used for connection offload.  Completes on the RCQ of the multi-queue
 976  *   RSS connection that is being offloaded.  (Not currently used under
 977  *   FreeBSD.)
 978  *
 979  * There can only be one command pending per function.
 980  *
 981  * Returns:
 982  *   0 = Success, !0 = Failure.
 983  */
 984
 985 /* must be called under the spq lock */
 986 static inline struct eth_spe *bnx2x_sp_get_next(struct bnx2x_softc *sc)
 987 {
 988         struct eth_spe *next_spe = sc->spq_prod_bd;
 989
 990         if (sc->spq_prod_bd == sc->spq_last_bd) {
 991                 /* wrap back to the first eth_spq */
 992                 sc->spq_prod_bd = sc->spq;
 993                 sc->spq_prod_idx = 0;
 994         } else {
 995                 sc->spq_prod_bd++;
 996                 sc->spq_prod_idx++;
 997         }
 998
 999         return next_spe;
1000 }
1001
1002 /* must be called under the spq lock */
1003 static void bnx2x_sp_prod_update(struct bnx2x_softc *sc)
1004 {
1005         int func = SC_FUNC(sc);
1006
1007         /*
1008          * Make sure that BD data is updated before writing the producer.
1009          * BD data is written to the memory, the producer is read from the
1010          * memory, thus we need a full memory barrier to ensure the ordering.
1011          */
1012         mb();
1013
1014         REG_WR16(sc, (BAR_XSTRORM_INTMEM + XSTORM_SPQ_PROD_OFFSET(func)),
1015                  sc->spq_prod_idx);
1016
1017         mb();
1018 }
1019
1020 /**
1021  * bnx2x_is_contextless_ramrod - check if the current command ends on EQ
1022  *
1023  * @cmd:      command to check
1024  * @cmd_type: command type
1025  */
1026 static int bnx2x_is_contextless_ramrod(int cmd, int cmd_type)
1027 {
1028         if ((cmd_type == NONE_CONNECTION_TYPE) ||
1029             (cmd == RAMROD_CMD_ID_ETH_FORWARD_SETUP) ||
1030             (cmd == RAMROD_CMD_ID_ETH_CLASSIFICATION_RULES) ||
1031             (cmd == RAMROD_CMD_ID_ETH_FILTER_RULES) ||
1032             (cmd == RAMROD_CMD_ID_ETH_MULTICAST_RULES) ||
1033             (cmd == RAMROD_CMD_ID_ETH_SET_MAC) ||
1034             (cmd == RAMROD_CMD_ID_ETH_RSS_UPDATE)) {
1035                 return TRUE;
1036         } else {
1037                 return FALSE;
1038         }
1039 }
1040
1041 /**
1042  * bnx2x_sp_post - place a single command on an SP ring
1043  *
1044  * @sc:         driver handle
1045  * @command:    command to place (e.g. SETUP, FILTER_RULES, etc.)
1046  * @cid:        SW CID the command is related to
1047  * @data_hi:    command private data address (high 32 bits)
1048  * @data_lo:    command private data address (low 32 bits)
1049  * @cmd_type:   command type (e.g. NONE, ETH)
1050  *
1051  * SP data is handled as if it's always an address pair, thus data fields are
1052  * not swapped to little endian in upper functions. Instead this function swaps
1053  * data as if it's two uint32 fields.
1054  */
1055 int
1056 bnx2x_sp_post(struct bnx2x_softc *sc, int command, int cid, uint32_t data_hi,
1057             uint32_t data_lo, int cmd_type)
1058 {
1059         struct eth_spe *spe;
1060         uint16_t type;
1061         int common;
1062
1063         common = bnx2x_is_contextless_ramrod(command, cmd_type);
1064
1065         if (common) {
1066                 if (!atomic_load_acq_long(&sc->eq_spq_left)) {
1067                         PMD_DRV_LOG(INFO, sc, "EQ ring is full!");
1068                         return -1;
1069                 }
1070         } else {
1071                 if (!atomic_load_acq_long(&sc->cq_spq_left)) {
1072                         PMD_DRV_LOG(INFO, sc, "SPQ ring is full!");
1073                         return -1;
1074                 }
1075         }
1076
1077         spe = bnx2x_sp_get_next(sc);
1078
1079         /* CID needs port number to be encoded int it */
1080         spe->hdr.conn_and_cmd_data =
1081             htole32((command << SPE_HDR_CMD_ID_SHIFT) | HW_CID(sc, cid));
1082
1083         type = (cmd_type << SPE_HDR_CONN_TYPE_SHIFT) & SPE_HDR_CONN_TYPE;
1084
1085         /* TBD: Check if it works for VFs */
1086         type |= ((SC_FUNC(sc) << SPE_HDR_FUNCTION_ID_SHIFT) &
1087                  SPE_HDR_FUNCTION_ID);
1088
1089         spe->hdr.type = htole16(type);
1090
1091         spe->data.update_data_addr.hi = htole32(data_hi);
1092         spe->data.update_data_addr.lo = htole32(data_lo);
1093
1094         /*
1095          * It's ok if the actual decrement is issued towards the memory
1096          * somewhere between the lock and unlock. Thus no more explict
1097          * memory barrier is needed.
1098          */
1099         if (common) {
1100                 atomic_subtract_acq_long(&sc->eq_spq_left, 1);
1101         } else {
1102                 atomic_subtract_acq_long(&sc->cq_spq_left, 1);
1103         }
1104
1105         PMD_DRV_LOG(DEBUG, sc,
1106                     "SPQE[%x] (%x:%x) (cmd, common?) (%d,%d) hw_cid %x"
1107                     "data (%x:%x) type(0x%x) left (CQ, EQ) (%lx,%lx)",
1108                     sc->spq_prod_idx,
1109                     (uint32_t) U64_HI(sc->spq_dma.paddr),
1110                     (uint32_t) (U64_LO(sc->spq_dma.paddr) +
1111                                 (uint8_t *) sc->spq_prod_bd -
1112                                 (uint8_t *) sc->spq), command, common,
1113                     HW_CID(sc, cid), data_hi, data_lo, type,
1114                     atomic_load_acq_long(&sc->cq_spq_left),
1115                     atomic_load_acq_long(&sc->eq_spq_left));
1116
1117         bnx2x_sp_prod_update(sc);
1118
1119         return 0;
1120 }
1121
1122 static void bnx2x_drv_pulse(struct bnx2x_softc *sc)
1123 {
1124         SHMEM_WR(sc, func_mb[SC_FW_MB_IDX(sc)].drv_pulse_mb,
1125                  sc->fw_drv_pulse_wr_seq);
1126 }
1127
1128 static int bnx2x_tx_queue_has_work(const struct bnx2x_fastpath *fp)
1129 {
1130         uint16_t hw_cons;
1131         struct bnx2x_tx_queue *txq = fp->sc->tx_queues[fp->index];
1132
1133         if (unlikely(!txq)) {
1134                 PMD_TX_LOG(ERR, "ERROR: TX queue is NULL");
1135                 return 0;
1136         }
1137
1138         mb();                   /* status block fields can change */
1139         hw_cons = le16toh(*fp->tx_cons_sb);
1140         return hw_cons != txq->tx_pkt_head;
1141 }
1142
1143 static uint8_t bnx2x_has_tx_work(struct bnx2x_fastpath *fp)
1144 {
1145         /* expand this for multi-cos if ever supported */
1146         return bnx2x_tx_queue_has_work(fp);
1147 }
1148
1149 static int bnx2x_has_rx_work(struct bnx2x_fastpath *fp)
1150 {
1151         uint16_t rx_cq_cons_sb;
1152         struct bnx2x_rx_queue *rxq;
1153         rxq = fp->sc->rx_queues[fp->index];
1154         if (unlikely(!rxq)) {
1155                 PMD_RX_LOG(ERR, "ERROR: RX queue is NULL");
1156                 return 0;
1157         }
1158
1159         mb();                   /* status block fields can change */
1160         rx_cq_cons_sb = le16toh(*fp->rx_cq_cons_sb);
1161         if (unlikely((rx_cq_cons_sb & MAX_RCQ_ENTRIES(rxq)) ==
1162                      MAX_RCQ_ENTRIES(rxq)))
1163                 rx_cq_cons_sb++;
1164         return rxq->rx_cq_head != rx_cq_cons_sb;
1165 }
1166
1167 static void
1168 bnx2x_sp_event(struct bnx2x_softc *sc, struct bnx2x_fastpath *fp,
1169              union eth_rx_cqe *rr_cqe)
1170 {
1171         int cid = SW_CID(rr_cqe->ramrod_cqe.conn_and_cmd_data);
1172         int command = CQE_CMD(rr_cqe->ramrod_cqe.conn_and_cmd_data);
1173         enum ecore_queue_cmd drv_cmd = ECORE_Q_CMD_MAX;
1174         struct ecore_queue_sp_obj *q_obj = &BNX2X_SP_OBJ(sc, fp).q_obj;
1175
1176         PMD_DRV_LOG(DEBUG, sc,
1177                     "fp=%d cid=%d got ramrod #%d state is %x type is %d",
1178                     fp->index, cid, command, sc->state,
1179                     rr_cqe->ramrod_cqe.ramrod_type);
1180
1181         switch (command) {
1182         case (RAMROD_CMD_ID_ETH_CLIENT_UPDATE):
1183                 PMD_DRV_LOG(DEBUG, sc, "got UPDATE ramrod. CID %d", cid);
1184                 drv_cmd = ECORE_Q_CMD_UPDATE;
1185                 break;
1186
1187         case (RAMROD_CMD_ID_ETH_CLIENT_SETUP):
1188                 PMD_DRV_LOG(DEBUG, sc, "got MULTI[%d] setup ramrod", cid);
1189                 drv_cmd = ECORE_Q_CMD_SETUP;
1190                 break;
1191
1192         case (RAMROD_CMD_ID_ETH_TX_QUEUE_SETUP):
1193                 PMD_DRV_LOG(DEBUG, sc,
1194                             "got MULTI[%d] tx-only setup ramrod", cid);
1195                 drv_cmd = ECORE_Q_CMD_SETUP_TX_ONLY;
1196                 break;
1197
1198         case (RAMROD_CMD_ID_ETH_HALT):
1199                 PMD_DRV_LOG(DEBUG, sc, "got MULTI[%d] halt ramrod", cid);
1200                 drv_cmd = ECORE_Q_CMD_HALT;
1201                 break;
1202
1203         case (RAMROD_CMD_ID_ETH_TERMINATE):
1204                 PMD_DRV_LOG(DEBUG, sc, "got MULTI[%d] teminate ramrod", cid);
1205                 drv_cmd = ECORE_Q_CMD_TERMINATE;
1206                 break;
1207
1208         case (RAMROD_CMD_ID_ETH_EMPTY):
1209                 PMD_DRV_LOG(DEBUG, sc, "got MULTI[%d] empty ramrod", cid);
1210                 drv_cmd = ECORE_Q_CMD_EMPTY;
1211                 break;
1212
1213         default:
1214                 PMD_DRV_LOG(DEBUG, sc,
1215                             "ERROR: unexpected MC reply (%d)"
1216                             "on fp[%d]", command, fp->index);
1217                 return;
1218         }
1219
1220         if ((drv_cmd != ECORE_Q_CMD_MAX) &&
1221             q_obj->complete_cmd(sc, q_obj, drv_cmd)) {
1222                 /*
1223                  * q_obj->complete_cmd() failure means that this was
1224                  * an unexpected completion.
1225                  *
1226                  * In this case we don't want to increase the sc->spq_left
1227                  * because apparently we haven't sent this command the first
1228                  * place.
1229                  */
1230                 // rte_panic("Unexpected SP completion");
1231                 return;
1232         }
1233
1234         atomic_add_acq_long(&sc->cq_spq_left, 1);
1235
1236         PMD_DRV_LOG(DEBUG, sc, "sc->cq_spq_left 0x%lx",
1237                     atomic_load_acq_long(&sc->cq_spq_left));
1238 }
1239
1240 static uint8_t bnx2x_rxeof(struct bnx2x_softc *sc, struct bnx2x_fastpath *fp)
1241 {
1242         struct bnx2x_rx_queue *rxq;
1243         uint16_t bd_cons, bd_prod, bd_prod_fw, comp_ring_cons;
1244         uint16_t hw_cq_cons, sw_cq_cons, sw_cq_prod;
1245
1246         rxq = sc->rx_queues[fp->index];
1247         if (!rxq) {
1248                 PMD_RX_LOG(ERR, "RX queue %d is NULL", fp->index);
1249                 return 0;
1250         }
1251
1252         /* CQ "next element" is of the size of the regular element */
1253         hw_cq_cons = le16toh(*fp->rx_cq_cons_sb);
1254         if (unlikely((hw_cq_cons & USABLE_RCQ_ENTRIES_PER_PAGE) ==
1255                      USABLE_RCQ_ENTRIES_PER_PAGE)) {
1256                 hw_cq_cons++;
1257         }
1258
1259         bd_cons = rxq->rx_bd_head;
1260         bd_prod = rxq->rx_bd_tail;
1261         bd_prod_fw = bd_prod;
1262         sw_cq_cons = rxq->rx_cq_head;
1263         sw_cq_prod = rxq->rx_cq_tail;
1264
1265         /*
1266          * Memory barrier necessary as speculative reads of the rx
1267          * buffer can be ahead of the index in the status block
1268          */
1269         rmb();
1270
1271         while (sw_cq_cons != hw_cq_cons) {
1272                 union eth_rx_cqe *cqe;
1273                 struct eth_fast_path_rx_cqe *cqe_fp;
1274                 uint8_t cqe_fp_flags;
1275                 enum eth_rx_cqe_type cqe_fp_type;
1276
1277                 comp_ring_cons = RCQ_ENTRY(sw_cq_cons, rxq);
1278                 bd_prod = RX_BD(bd_prod, rxq);
1279                 bd_cons = RX_BD(bd_cons, rxq);
1280
1281                 cqe = &rxq->cq_ring[comp_ring_cons];
1282                 cqe_fp = &cqe->fast_path_cqe;
1283                 cqe_fp_flags = cqe_fp->type_error_flags;
1284                 cqe_fp_type = cqe_fp_flags & ETH_FAST_PATH_RX_CQE_TYPE;
1285
1286                 /* is this a slowpath msg? */
1287                 if (CQE_TYPE_SLOW(cqe_fp_type)) {
1288                         bnx2x_sp_event(sc, fp, cqe);
1289                         goto next_cqe;
1290                 }
1291
1292                 /* is this an error packet? */
1293                 if (unlikely(cqe_fp_flags &
1294                              ETH_FAST_PATH_RX_CQE_PHY_DECODE_ERR_FLG)) {
1295                         PMD_RX_LOG(DEBUG, "flags 0x%x rx packet %u",
1296                                    cqe_fp_flags, sw_cq_cons);
1297                         goto next_rx;
1298                 }
1299
1300                 PMD_RX_LOG(DEBUG, "Dropping fastpath called from attn poller!");
1301
1302 next_rx:
1303                 bd_cons = NEXT_RX_BD(bd_cons);
1304                 bd_prod = NEXT_RX_BD(bd_prod);
1305                 bd_prod_fw = NEXT_RX_BD(bd_prod_fw);
1306
1307 next_cqe:
1308                 sw_cq_prod = NEXT_RCQ_IDX(sw_cq_prod);
1309                 sw_cq_cons = NEXT_RCQ_IDX(sw_cq_cons);
1310
1311         }                       /* while work to do */
1312
1313         rxq->rx_bd_head = bd_cons;
1314         rxq->rx_bd_tail = bd_prod_fw;
1315         rxq->rx_cq_head = sw_cq_cons;
1316         rxq->rx_cq_tail = sw_cq_prod;
1317
1318         /* Update producers */
1319         bnx2x_update_rx_prod(sc, fp, bd_prod_fw, sw_cq_prod);
1320
1321         return sw_cq_cons != hw_cq_cons;
1322 }
1323
1324 static uint16_t
1325 bnx2x_free_tx_pkt(__rte_unused struct bnx2x_fastpath *fp, struct bnx2x_tx_queue *txq,
1326                 uint16_t pkt_idx, uint16_t bd_idx)
1327 {
1328         struct eth_tx_start_bd *tx_start_bd =
1329             &txq->tx_ring[TX_BD(bd_idx, txq)].start_bd;
1330         uint16_t nbd = rte_le_to_cpu_16(tx_start_bd->nbd);
1331         struct rte_mbuf *tx_mbuf = txq->sw_ring[TX_BD(pkt_idx, txq)];
1332
1333         if (likely(tx_mbuf != NULL)) {
1334                 rte_pktmbuf_free_seg(tx_mbuf);
1335         } else {
1336                 PMD_RX_LOG(ERR, "fp[%02d] lost mbuf %lu",
1337                            fp->index, (unsigned long)TX_BD(pkt_idx, txq));
1338         }
1339
1340         txq->sw_ring[TX_BD(pkt_idx, txq)] = NULL;
1341         txq->nb_tx_avail += nbd;
1342
1343         while (nbd--)
1344                 bd_idx = NEXT_TX_BD(bd_idx);
1345
1346         return bd_idx;
1347 }
1348
1349 /* processes transmit completions */
1350 uint8_t bnx2x_txeof(__rte_unused struct bnx2x_softc * sc, struct bnx2x_fastpath * fp)
1351 {
1352         uint16_t bd_cons, hw_cons, sw_cons;
1353         __rte_unused uint16_t tx_bd_avail;
1354
1355         struct bnx2x_tx_queue *txq = fp->sc->tx_queues[fp->index];
1356
1357         if (unlikely(!txq)) {
1358                 PMD_TX_LOG(ERR, "ERROR: TX queue is NULL");
1359                 return 0;
1360         }
1361
1362         bd_cons = txq->tx_bd_head;
1363         hw_cons = rte_le_to_cpu_16(*fp->tx_cons_sb);
1364         sw_cons = txq->tx_pkt_head;
1365
1366         while (sw_cons != hw_cons) {
1367                 bd_cons = bnx2x_free_tx_pkt(fp, txq, sw_cons, bd_cons);
1368                 sw_cons++;
1369         }
1370
1371         txq->tx_pkt_head = sw_cons;
1372         txq->tx_bd_head = bd_cons;
1373
1374         tx_bd_avail = txq->nb_tx_avail;
1375
1376         PMD_TX_LOG(DEBUG, "fp[%02d] avail=%u cons_sb=%u, "
1377                    "pkt_head=%u pkt_tail=%u bd_head=%u bd_tail=%u",
1378                    fp->index, tx_bd_avail, hw_cons,
1379                    txq->tx_pkt_head, txq->tx_pkt_tail,
1380                    txq->tx_bd_head, txq->tx_bd_tail);
1381         return TRUE;
1382 }
1383
1384 static void bnx2x_drain_tx_queues(struct bnx2x_softc *sc)
1385 {
1386         struct bnx2x_fastpath *fp;
1387         int i, count;
1388
1389         /* wait until all TX fastpath tasks have completed */
1390         for (i = 0; i < sc->num_queues; i++) {
1391                 fp = &sc->fp[i];
1392
1393                 count = 1000;
1394
1395                 while (bnx2x_has_tx_work(fp)) {
1396                         bnx2x_txeof(sc, fp);
1397
1398                         if (count == 0) {
1399                                 PMD_TX_LOG(ERR,
1400                                            "Timeout waiting for fp[%d] "
1401                                            "transmits to complete!", i);
1402                                 rte_panic("tx drain failure");
1403                                 return;
1404                         }
1405
1406                         count--;
1407                         DELAY(1000);
1408                         rmb();
1409                 }
1410         }
1411
1412         return;
1413 }
1414
1415 static int
1416 bnx2x_del_all_macs(struct bnx2x_softc *sc, struct ecore_vlan_mac_obj *mac_obj,
1417                  int mac_type, uint8_t wait_for_comp)
1418 {
1419         unsigned long ramrod_flags = 0, vlan_mac_flags = 0;
1420         int rc;
1421
1422         /* wait for completion of requested */
1423         if (wait_for_comp) {
1424                 bnx2x_set_bit(RAMROD_COMP_WAIT, &ramrod_flags);
1425         }
1426
1427         /* Set the mac type of addresses we want to clear */
1428         bnx2x_set_bit(mac_type, &vlan_mac_flags);
1429
1430         rc = mac_obj->delete_all(sc, mac_obj, &vlan_mac_flags, &ramrod_flags);
1431         if (rc < 0)
1432                 PMD_DRV_LOG(ERR, sc, "Failed to delete MACs (%d)", rc);
1433
1434         return rc;
1435 }
1436
1437 static int
1438 bnx2x_fill_accept_flags(struct bnx2x_softc *sc, uint32_t rx_mode,
1439                         unsigned long *rx_accept_flags,
1440                         unsigned long *tx_accept_flags)
1441 {
1442         /* Clear the flags first */
1443         *rx_accept_flags = 0;
1444         *tx_accept_flags = 0;
1445
1446         switch (rx_mode) {
1447         case BNX2X_RX_MODE_NONE:
1448                 /*
1449                  * 'drop all' supersedes any accept flags that may have been
1450                  * passed to the function.
1451                  */
1452                 break;
1453
1454         case BNX2X_RX_MODE_NORMAL:
1455                 bnx2x_set_bit(ECORE_ACCEPT_UNICAST, rx_accept_flags);
1456                 bnx2x_set_bit(ECORE_ACCEPT_MULTICAST, rx_accept_flags);
1457                 bnx2x_set_bit(ECORE_ACCEPT_BROADCAST, rx_accept_flags);
1458
1459                 /* internal switching mode */
1460                 bnx2x_set_bit(ECORE_ACCEPT_UNICAST, tx_accept_flags);
1461                 bnx2x_set_bit(ECORE_ACCEPT_MULTICAST, tx_accept_flags);
1462                 bnx2x_set_bit(ECORE_ACCEPT_BROADCAST, tx_accept_flags);
1463
1464                 break;
1465
1466         case BNX2X_RX_MODE_ALLMULTI:
1467                 bnx2x_set_bit(ECORE_ACCEPT_UNICAST, rx_accept_flags);
1468                 bnx2x_set_bit(ECORE_ACCEPT_ALL_MULTICAST, rx_accept_flags);
1469                 bnx2x_set_bit(ECORE_ACCEPT_BROADCAST, rx_accept_flags);
1470
1471                 /* internal switching mode */
1472                 bnx2x_set_bit(ECORE_ACCEPT_UNICAST, tx_accept_flags);
1473                 bnx2x_set_bit(ECORE_ACCEPT_ALL_MULTICAST, tx_accept_flags);
1474                 bnx2x_set_bit(ECORE_ACCEPT_BROADCAST, tx_accept_flags);
1475
1476                 break;
1477
1478         case BNX2X_RX_MODE_ALLMULTI_PROMISC:
1479         case BNX2X_RX_MODE_PROMISC:
1480                 /*
1481                  * According to deffinition of SI mode, iface in promisc mode
1482                  * should receive matched and unmatched (in resolution of port)
1483                  * unicast packets.
1484                  */
1485                 bnx2x_set_bit(ECORE_ACCEPT_UNMATCHED, rx_accept_flags);
1486                 bnx2x_set_bit(ECORE_ACCEPT_UNICAST, rx_accept_flags);
1487                 bnx2x_set_bit(ECORE_ACCEPT_ALL_MULTICAST, rx_accept_flags);
1488                 bnx2x_set_bit(ECORE_ACCEPT_BROADCAST, rx_accept_flags);
1489
1490                 /* internal switching mode */
1491                 bnx2x_set_bit(ECORE_ACCEPT_ALL_MULTICAST, tx_accept_flags);
1492                 bnx2x_set_bit(ECORE_ACCEPT_BROADCAST, tx_accept_flags);
1493
1494                 if (IS_MF_SI(sc)) {
1495                         bnx2x_set_bit(ECORE_ACCEPT_ALL_UNICAST, tx_accept_flags);
1496                 } else {
1497                         bnx2x_set_bit(ECORE_ACCEPT_UNICAST, tx_accept_flags);
1498                 }
1499
1500                 break;
1501
1502         default:
1503                 PMD_RX_LOG(ERR, "Unknown rx_mode (%d)", rx_mode);
1504                 return -1;
1505         }
1506
1507         /* Set ACCEPT_ANY_VLAN as we do not enable filtering by VLAN */
1508         if (rx_mode != BNX2X_RX_MODE_NONE) {
1509                 bnx2x_set_bit(ECORE_ACCEPT_ANY_VLAN, rx_accept_flags);
1510                 bnx2x_set_bit(ECORE_ACCEPT_ANY_VLAN, tx_accept_flags);
1511         }
1512
1513         return 0;
1514 }
1515
1516 static int
1517 bnx2x_set_q_rx_mode(struct bnx2x_softc *sc, uint8_t cl_id,
1518                   unsigned long rx_mode_flags,
1519                   unsigned long rx_accept_flags,
1520                   unsigned long tx_accept_flags, unsigned long ramrod_flags)
1521 {
1522         struct ecore_rx_mode_ramrod_params ramrod_param;
1523         int rc;
1524
1525         memset(&ramrod_param, 0, sizeof(ramrod_param));
1526
1527         /* Prepare ramrod parameters */
1528         ramrod_param.cid = 0;
1529         ramrod_param.cl_id = cl_id;
1530         ramrod_param.rx_mode_obj = &sc->rx_mode_obj;
1531         ramrod_param.func_id = SC_FUNC(sc);
1532
1533         ramrod_param.pstate = &sc->sp_state;
1534         ramrod_param.state = ECORE_FILTER_RX_MODE_PENDING;
1535
1536         ramrod_param.rdata = BNX2X_SP(sc, rx_mode_rdata);
1537         ramrod_param.rdata_mapping =
1538             (rte_iova_t)BNX2X_SP_MAPPING(sc, rx_mode_rdata),
1539             bnx2x_set_bit(ECORE_FILTER_RX_MODE_PENDING, &sc->sp_state);
1540
1541         ramrod_param.ramrod_flags = ramrod_flags;
1542         ramrod_param.rx_mode_flags = rx_mode_flags;
1543
1544         ramrod_param.rx_accept_flags = rx_accept_flags;
1545         ramrod_param.tx_accept_flags = tx_accept_flags;
1546
1547         rc = ecore_config_rx_mode(sc, &ramrod_param);
1548         if (rc < 0) {
1549                 PMD_RX_LOG(ERR, "Set rx_mode %d failed", sc->rx_mode);
1550                 return rc;
1551         }
1552
1553         return 0;
1554 }
1555
1556 int bnx2x_set_storm_rx_mode(struct bnx2x_softc *sc)
1557 {
1558         unsigned long rx_mode_flags = 0, ramrod_flags = 0;
1559         unsigned long rx_accept_flags = 0, tx_accept_flags = 0;
1560         int rc;
1561
1562         rc = bnx2x_fill_accept_flags(sc, sc->rx_mode, &rx_accept_flags,
1563                                    &tx_accept_flags);
1564         if (rc) {
1565                 return rc;
1566         }
1567
1568         bnx2x_set_bit(RAMROD_RX, &ramrod_flags);
1569         bnx2x_set_bit(RAMROD_TX, &ramrod_flags);
1570         bnx2x_set_bit(RAMROD_COMP_WAIT, &ramrod_flags);
1571
1572         return bnx2x_set_q_rx_mode(sc, sc->fp[0].cl_id, rx_mode_flags,
1573                                  rx_accept_flags, tx_accept_flags,
1574                                  ramrod_flags);
1575 }
1576
1577 /* returns the "mcp load_code" according to global load_count array */
1578 static int bnx2x_nic_load_no_mcp(struct bnx2x_softc *sc)
1579 {
1580         int path = SC_PATH(sc);
1581         int port = SC_PORT(sc);
1582
1583         PMD_DRV_LOG(INFO, sc, "NO MCP - load counts[%d]      %d, %d, %d",
1584                     path, load_count[path][0], load_count[path][1],
1585                     load_count[path][2]);
1586
1587         load_count[path][0]++;
1588         load_count[path][1 + port]++;
1589         PMD_DRV_LOG(INFO, sc, "NO MCP - new load counts[%d]  %d, %d, %d",
1590                     path, load_count[path][0], load_count[path][1],
1591                     load_count[path][2]);
1592         if (load_count[path][0] == 1)
1593                 return FW_MSG_CODE_DRV_LOAD_COMMON;
1594         else if (load_count[path][1 + port] == 1)
1595                 return FW_MSG_CODE_DRV_LOAD_PORT;
1596         else
1597                 return FW_MSG_CODE_DRV_LOAD_FUNCTION;
1598 }
1599
1600 /* returns the "mcp load_code" according to global load_count array */
1601 static int bnx2x_nic_unload_no_mcp(struct bnx2x_softc *sc)
1602 {
1603         int port = SC_PORT(sc);
1604         int path = SC_PATH(sc);
1605
1606         PMD_DRV_LOG(INFO, sc, "NO MCP - load counts[%d]      %d, %d, %d",
1607                     path, load_count[path][0], load_count[path][1],
1608                     load_count[path][2]);
1609         load_count[path][0]--;
1610         load_count[path][1 + port]--;
1611         PMD_DRV_LOG(INFO, sc, "NO MCP - new load counts[%d]  %d, %d, %d",
1612                     path, load_count[path][0], load_count[path][1],
1613                     load_count[path][2]);
1614         if (load_count[path][0] == 0) {
1615                 return FW_MSG_CODE_DRV_UNLOAD_COMMON;
1616         } else if (load_count[path][1 + port] == 0) {
1617                 return FW_MSG_CODE_DRV_UNLOAD_PORT;
1618         } else {
1619                 return FW_MSG_CODE_DRV_UNLOAD_FUNCTION;
1620         }
1621 }
1622
1623 /* request unload mode from the MCP: COMMON, PORT or FUNCTION */
1624 static uint32_t bnx2x_send_unload_req(struct bnx2x_softc *sc, int unload_mode)
1625 {
1626         uint32_t reset_code = 0;
1627
1628         /* Select the UNLOAD request mode */
1629         if (unload_mode == UNLOAD_NORMAL) {
1630                 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS;
1631         } else {
1632                 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS;
1633         }
1634
1635         /* Send the request to the MCP */
1636         if (!BNX2X_NOMCP(sc)) {
1637                 reset_code = bnx2x_fw_command(sc, reset_code, 0);
1638         } else {
1639                 reset_code = bnx2x_nic_unload_no_mcp(sc);
1640         }
1641
1642         return reset_code;
1643 }
1644
1645 /* send UNLOAD_DONE command to the MCP */
1646 static void bnx2x_send_unload_done(struct bnx2x_softc *sc, uint8_t keep_link)
1647 {
1648         uint32_t reset_param =
1649             keep_link ? DRV_MSG_CODE_UNLOAD_SKIP_LINK_RESET : 0;
1650
1651         /* Report UNLOAD_DONE to MCP */
1652         if (!BNX2X_NOMCP(sc)) {
1653                 bnx2x_fw_command(sc, DRV_MSG_CODE_UNLOAD_DONE, reset_param);
1654         }
1655 }
1656
1657 static int bnx2x_func_wait_started(struct bnx2x_softc *sc)
1658 {
1659         int tout = 50;
1660
1661         if (!sc->port.pmf) {
1662                 return 0;
1663         }
1664
1665         /*
1666          * (assumption: No Attention from MCP at this stage)
1667          * PMF probably in the middle of TX disable/enable transaction
1668          * 1. Sync IRS for default SB
1669          * 2. Sync SP queue - this guarantees us that attention handling started
1670          * 3. Wait, that TX disable/enable transaction completes
1671          *
1672          * 1+2 guarantee that if DCBX attention was scheduled it already changed
1673          * pending bit of transaction from STARTED-->TX_STOPPED, if we already
1674          * received completion for the transaction the state is TX_STOPPED.
1675          * State will return to STARTED after completion of TX_STOPPED-->STARTED
1676          * transaction.
1677          */
1678
1679         while (ecore_func_get_state(sc, &sc->func_obj) !=
1680                ECORE_F_STATE_STARTED && tout--) {
1681                 DELAY(20000);
1682         }
1683
1684         if (ecore_func_get_state(sc, &sc->func_obj) != ECORE_F_STATE_STARTED) {
1685                 /*
1686                  * Failed to complete the transaction in a "good way"
1687                  * Force both transactions with CLR bit.
1688                  */
1689                 struct ecore_func_state_params func_params = { NULL };
1690
1691                 PMD_DRV_LOG(NOTICE, sc, "Unexpected function state! "
1692                             "Forcing STARTED-->TX_STOPPED-->STARTED");
1693
1694                 func_params.f_obj = &sc->func_obj;
1695                 bnx2x_set_bit(RAMROD_DRV_CLR_ONLY, &func_params.ramrod_flags);
1696
1697                 /* STARTED-->TX_STOPPED */
1698                 func_params.cmd = ECORE_F_CMD_TX_STOP;
1699                 ecore_func_state_change(sc, &func_params);
1700
1701                 /* TX_STOPPED-->STARTED */
1702                 func_params.cmd = ECORE_F_CMD_TX_START;
1703                 return ecore_func_state_change(sc, &func_params);
1704         }
1705
1706         return 0;
1707 }
1708
1709 static int bnx2x_stop_queue(struct bnx2x_softc *sc, int index)
1710 {
1711         struct bnx2x_fastpath *fp = &sc->fp[index];
1712         struct ecore_queue_state_params q_params = { NULL };
1713         int rc;
1714
1715         PMD_DRV_LOG(DEBUG, sc, "stopping queue %d cid %d", index, fp->index);
1716
1717         q_params.q_obj = &sc->sp_objs[fp->index].q_obj;
1718         /* We want to wait for completion in this context */
1719         bnx2x_set_bit(RAMROD_COMP_WAIT, &q_params.ramrod_flags);
1720
1721         /* Stop the primary connection: */
1722
1723         /* ...halt the connection */
1724         q_params.cmd = ECORE_Q_CMD_HALT;
1725         rc = ecore_queue_state_change(sc, &q_params);
1726         if (rc) {
1727                 return rc;
1728         }
1729
1730         /* ...terminate the connection */
1731         q_params.cmd = ECORE_Q_CMD_TERMINATE;
1732         memset(&q_params.params.terminate, 0,
1733                sizeof(q_params.params.terminate));
1734         q_params.params.terminate.cid_index = FIRST_TX_COS_INDEX;
1735         rc = ecore_queue_state_change(sc, &q_params);
1736         if (rc) {
1737                 return rc;
1738         }
1739
1740         /* ...delete cfc entry */
1741         q_params.cmd = ECORE_Q_CMD_CFC_DEL;
1742         memset(&q_params.params.cfc_del, 0, sizeof(q_params.params.cfc_del));
1743         q_params.params.cfc_del.cid_index = FIRST_TX_COS_INDEX;
1744         return ecore_queue_state_change(sc, &q_params);
1745 }
1746
1747 /* wait for the outstanding SP commands */
1748 static uint8_t bnx2x_wait_sp_comp(struct bnx2x_softc *sc, unsigned long mask)
1749 {
1750         unsigned long tmp;
1751         int tout = 5000;        /* wait for 5 secs tops */
1752
1753         while (tout--) {
1754                 mb();
1755                 if (!(atomic_load_acq_long(&sc->sp_state) & mask)) {
1756                         return TRUE;
1757                 }
1758
1759                 DELAY(1000);
1760         }
1761
1762         mb();
1763
1764         tmp = atomic_load_acq_long(&sc->sp_state);
1765         if (tmp & mask) {
1766                 PMD_DRV_LOG(INFO, sc, "Filtering completion timed out: "
1767                             "sp_state 0x%lx, mask 0x%lx", tmp, mask);
1768                 return FALSE;
1769         }
1770
1771         return FALSE;
1772 }
1773
1774 static int bnx2x_func_stop(struct bnx2x_softc *sc)
1775 {
1776         struct ecore_func_state_params func_params = { NULL };
1777         int rc;
1778
1779         /* prepare parameters for function state transitions */
1780         bnx2x_set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags);
1781         func_params.f_obj = &sc->func_obj;
1782         func_params.cmd = ECORE_F_CMD_STOP;
1783
1784         /*
1785          * Try to stop the function the 'good way'. If it fails (in case
1786          * of a parity error during bnx2x_chip_cleanup()) and we are
1787          * not in a debug mode, perform a state transaction in order to
1788          * enable further HW_RESET transaction.
1789          */
1790         rc = ecore_func_state_change(sc, &func_params);
1791         if (rc) {
1792                 PMD_DRV_LOG(NOTICE, sc, "FUNC_STOP ramrod failed. "
1793                             "Running a dry transaction");
1794                 bnx2x_set_bit(RAMROD_DRV_CLR_ONLY, &func_params.ramrod_flags);
1795                 return ecore_func_state_change(sc, &func_params);
1796         }
1797
1798         return 0;
1799 }
1800
1801 static int bnx2x_reset_hw(struct bnx2x_softc *sc, uint32_t load_code)
1802 {
1803         struct ecore_func_state_params func_params = { NULL };
1804
1805         /* Prepare parameters for function state transitions */
1806         bnx2x_set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags);
1807
1808         func_params.f_obj = &sc->func_obj;
1809         func_params.cmd = ECORE_F_CMD_HW_RESET;
1810
1811         func_params.params.hw_init.load_phase = load_code;
1812
1813         return ecore_func_state_change(sc, &func_params);
1814 }
1815
1816 static void bnx2x_int_disable_sync(struct bnx2x_softc *sc, int disable_hw)
1817 {
1818         if (disable_hw) {
1819                 /* prevent the HW from sending interrupts */
1820                 bnx2x_int_disable(sc);
1821         }
1822 }
1823
1824 static void
1825 bnx2x_chip_cleanup(struct bnx2x_softc *sc, uint32_t unload_mode, uint8_t keep_link)
1826 {
1827         int port = SC_PORT(sc);
1828         struct ecore_mcast_ramrod_params rparam = { NULL };
1829         uint32_t reset_code;
1830         int i, rc = 0;
1831
1832         bnx2x_drain_tx_queues(sc);
1833
1834         /* give HW time to discard old tx messages */
1835         DELAY(1000);
1836
1837         /* Clean all ETH MACs */
1838         rc = bnx2x_del_all_macs(sc, &sc->sp_objs[0].mac_obj, ECORE_ETH_MAC,
1839                               FALSE);
1840         if (rc < 0) {
1841                 PMD_DRV_LOG(NOTICE, sc,
1842                             "Failed to delete all ETH MACs (%d)", rc);
1843         }
1844
1845         /* Clean up UC list  */
1846         rc = bnx2x_del_all_macs(sc, &sc->sp_objs[0].mac_obj, ECORE_UC_LIST_MAC,
1847                               TRUE);
1848         if (rc < 0) {
1849                 PMD_DRV_LOG(NOTICE, sc,
1850                             "Failed to delete UC MACs list (%d)", rc);
1851         }
1852
1853         /* Disable LLH */
1854         REG_WR(sc, NIG_REG_LLH0_FUNC_EN + port * 8, 0);
1855
1856         /* Set "drop all" to stop Rx */
1857
1858         /*
1859          * We need to take the if_maddr_lock() here in order to prevent
1860          * a race between the completion code and this code.
1861          */
1862
1863         if (bnx2x_test_bit(ECORE_FILTER_RX_MODE_PENDING, &sc->sp_state)) {
1864                 bnx2x_set_bit(ECORE_FILTER_RX_MODE_SCHED, &sc->sp_state);
1865         } else {
1866                 bnx2x_set_storm_rx_mode(sc);
1867         }
1868
1869         /* Clean up multicast configuration */
1870         rparam.mcast_obj = &sc->mcast_obj;
1871         rc = ecore_config_mcast(sc, &rparam, ECORE_MCAST_CMD_DEL);
1872         if (rc < 0) {
1873                 PMD_DRV_LOG(NOTICE, sc,
1874                             "Failed to send DEL MCAST command (%d)", rc);
1875         }
1876
1877         /*
1878          * Send the UNLOAD_REQUEST to the MCP. This will return if
1879          * this function should perform FUNCTION, PORT, or COMMON HW
1880          * reset.
1881          */
1882         reset_code = bnx2x_send_unload_req(sc, unload_mode);
1883
1884         /*
1885          * (assumption: No Attention from MCP at this stage)
1886          * PMF probably in the middle of TX disable/enable transaction
1887          */
1888         rc = bnx2x_func_wait_started(sc);
1889         if (rc) {
1890                 PMD_DRV_LOG(NOTICE, sc, "bnx2x_func_wait_started failed");
1891         }
1892
1893         /*
1894          * Close multi and leading connections
1895          * Completions for ramrods are collected in a synchronous way
1896          */
1897         for (i = 0; i < sc->num_queues; i++) {
1898                 if (bnx2x_stop_queue(sc, i)) {
1899                         goto unload_error;
1900                 }
1901         }
1902
1903         /*
1904          * If SP settings didn't get completed so far - something
1905          * very wrong has happen.
1906          */
1907         if (!bnx2x_wait_sp_comp(sc, ~0x0UL)) {
1908                 PMD_DRV_LOG(NOTICE, sc, "Common slow path ramrods got stuck!");
1909         }
1910
1911 unload_error:
1912
1913         rc = bnx2x_func_stop(sc);
1914         if (rc) {
1915                 PMD_DRV_LOG(NOTICE, sc, "Function stop failed!");
1916         }
1917
1918         /* disable HW interrupts */
1919         bnx2x_int_disable_sync(sc, TRUE);
1920
1921         /* Reset the chip */
1922         rc = bnx2x_reset_hw(sc, reset_code);
1923         if (rc) {
1924                 PMD_DRV_LOG(NOTICE, sc, "Hardware reset failed");
1925         }
1926
1927         /* Report UNLOAD_DONE to MCP */
1928         bnx2x_send_unload_done(sc, keep_link);
1929 }
1930
1931 static void bnx2x_disable_close_the_gate(struct bnx2x_softc *sc)
1932 {
1933         uint32_t val;
1934
1935         PMD_DRV_LOG(DEBUG, sc, "Disabling 'close the gates'");
1936
1937         val = REG_RD(sc, MISC_REG_AEU_GENERAL_MASK);
1938         val &= ~(MISC_AEU_GENERAL_MASK_REG_AEU_PXP_CLOSE_MASK |
1939                  MISC_AEU_GENERAL_MASK_REG_AEU_NIG_CLOSE_MASK);
1940         REG_WR(sc, MISC_REG_AEU_GENERAL_MASK, val);
1941 }
1942
1943 /*
1944  * Cleans the object that have internal lists without sending
1945  * ramrods. Should be run when interrutps are disabled.
1946  */
1947 static void bnx2x_squeeze_objects(struct bnx2x_softc *sc)
1948 {
1949         unsigned long ramrod_flags = 0, vlan_mac_flags = 0;
1950         struct ecore_mcast_ramrod_params rparam = { NULL };
1951         struct ecore_vlan_mac_obj *mac_obj = &sc->sp_objs->mac_obj;
1952         int rc;
1953
1954         /* Cleanup MACs' object first... */
1955
1956         /* Wait for completion of requested */
1957         bnx2x_set_bit(RAMROD_COMP_WAIT, &ramrod_flags);
1958         /* Perform a dry cleanup */
1959         bnx2x_set_bit(RAMROD_DRV_CLR_ONLY, &ramrod_flags);
1960
1961         /* Clean ETH primary MAC */
1962         bnx2x_set_bit(ECORE_ETH_MAC, &vlan_mac_flags);
1963         rc = mac_obj->delete_all(sc, &sc->sp_objs->mac_obj, &vlan_mac_flags,
1964                                  &ramrod_flags);
1965         if (rc != 0) {
1966                 PMD_DRV_LOG(NOTICE, sc, "Failed to clean ETH MACs (%d)", rc);
1967         }
1968
1969         /* Cleanup UC list */
1970         vlan_mac_flags = 0;
1971         bnx2x_set_bit(ECORE_UC_LIST_MAC, &vlan_mac_flags);
1972         rc = mac_obj->delete_all(sc, mac_obj, &vlan_mac_flags, &ramrod_flags);
1973         if (rc != 0) {
1974                 PMD_DRV_LOG(NOTICE, sc,
1975                             "Failed to clean UC list MACs (%d)", rc);
1976         }
1977
1978         /* Now clean mcast object... */
1979
1980         rparam.mcast_obj = &sc->mcast_obj;
1981         bnx2x_set_bit(RAMROD_DRV_CLR_ONLY, &rparam.ramrod_flags);
1982
1983         /* Add a DEL command... */
1984         rc = ecore_config_mcast(sc, &rparam, ECORE_MCAST_CMD_DEL);
1985         if (rc < 0) {
1986                 PMD_DRV_LOG(NOTICE, sc,
1987                             "Failed to send DEL MCAST command (%d)", rc);
1988         }
1989
1990         /* now wait until all pending commands are cleared */
1991
1992         rc = ecore_config_mcast(sc, &rparam, ECORE_MCAST_CMD_CONT);
1993         while (rc != 0) {
1994                 if (rc < 0) {
1995                         PMD_DRV_LOG(NOTICE, sc,
1996                                     "Failed to clean MCAST object (%d)", rc);
1997                         return;
1998                 }
1999
2000                 rc = ecore_config_mcast(sc, &rparam, ECORE_MCAST_CMD_CONT);
2001         }
2002 }
2003
2004 /* stop the controller */
2005 __rte_noinline
2006 int
2007 bnx2x_nic_unload(struct bnx2x_softc *sc, uint32_t unload_mode, uint8_t keep_link)
2008 {
2009         uint8_t global = FALSE;
2010         uint32_t val;
2011
2012         PMD_DRV_LOG(DEBUG, sc, "Starting NIC unload...");
2013
2014         /* mark driver as unloaded in shmem2 */
2015         if (IS_PF(sc) && SHMEM2_HAS(sc, drv_capabilities_flag)) {
2016                 val = SHMEM2_RD(sc, drv_capabilities_flag[SC_FW_MB_IDX(sc)]);
2017                 SHMEM2_WR(sc, drv_capabilities_flag[SC_FW_MB_IDX(sc)],
2018                           val & ~DRV_FLAGS_CAPABILITIES_LOADED_L2);
2019         }
2020
2021         if (IS_PF(sc) && sc->recovery_state != BNX2X_RECOVERY_DONE &&
2022             (sc->state == BNX2X_STATE_CLOSED || sc->state == BNX2X_STATE_ERROR)) {
2023                 /*
2024                  * We can get here if the driver has been unloaded
2025                  * during parity error recovery and is either waiting for a
2026                  * leader to complete or for other functions to unload and
2027                  * then ifconfig down has been issued. In this case we want to
2028                  * unload and let other functions to complete a recovery
2029                  * process.
2030                  */
2031                 sc->recovery_state = BNX2X_RECOVERY_DONE;
2032                 sc->is_leader = 0;
2033                 bnx2x_release_leader_lock(sc);
2034                 mb();
2035
2036                 PMD_DRV_LOG(NOTICE, sc, "Can't unload in closed or error state");
2037                 return -1;
2038         }
2039
2040         /*
2041          * Nothing to do during unload if previous bnx2x_nic_load()
2042          * did not completed successfully - all resourses are released.
2043          */
2044         if ((sc->state == BNX2X_STATE_CLOSED) || (sc->state == BNX2X_STATE_ERROR)) {
2045                 return 0;
2046         }
2047
2048         sc->state = BNX2X_STATE_CLOSING_WAITING_HALT;
2049         mb();
2050
2051         sc->rx_mode = BNX2X_RX_MODE_NONE;
2052         bnx2x_set_rx_mode(sc);
2053         mb();
2054
2055         if (IS_PF(sc)) {
2056                 /* set ALWAYS_ALIVE bit in shmem */
2057                 sc->fw_drv_pulse_wr_seq |= DRV_PULSE_ALWAYS_ALIVE;
2058
2059                 bnx2x_drv_pulse(sc);
2060
2061                 bnx2x_stats_handle(sc, STATS_EVENT_STOP);
2062                 bnx2x_save_statistics(sc);
2063         }
2064
2065         /* wait till consumers catch up with producers in all queues */
2066         bnx2x_drain_tx_queues(sc);
2067
2068         /* if VF indicate to PF this function is going down (PF will delete sp
2069          * elements and clear initializations
2070          */
2071         if (IS_VF(sc)) {
2072                 bnx2x_vf_unload(sc);
2073         } else if (unload_mode != UNLOAD_RECOVERY) {
2074                 /* if this is a normal/close unload need to clean up chip */
2075                 bnx2x_chip_cleanup(sc, unload_mode, keep_link);
2076         } else {
2077                 /* Send the UNLOAD_REQUEST to the MCP */
2078                 bnx2x_send_unload_req(sc, unload_mode);
2079
2080                 /*
2081                  * Prevent transactions to host from the functions on the
2082                  * engine that doesn't reset global blocks in case of global
2083                  * attention once gloabl blocks are reset and gates are opened
2084                  * (the engine which leader will perform the recovery
2085                  * last).
2086                  */
2087                 if (!CHIP_IS_E1x(sc)) {
2088                         bnx2x_pf_disable(sc);
2089                 }
2090
2091                 /* disable HW interrupts */
2092                 bnx2x_int_disable_sync(sc, TRUE);
2093
2094                 /* Report UNLOAD_DONE to MCP */
2095                 bnx2x_send_unload_done(sc, FALSE);
2096         }
2097
2098         /*
2099          * At this stage no more interrupts will arrive so we may safely clean
2100          * the queue'able objects here in case they failed to get cleaned so far.
2101          */
2102         if (IS_PF(sc)) {
2103                 bnx2x_squeeze_objects(sc);
2104         }
2105
2106         /* There should be no more pending SP commands at this stage */
2107         sc->sp_state = 0;
2108
2109         sc->port.pmf = 0;
2110
2111         if (IS_PF(sc)) {
2112                 bnx2x_free_mem(sc);
2113         }
2114
2115         bnx2x_free_fw_stats_mem(sc);
2116
2117         sc->state = BNX2X_STATE_CLOSED;
2118
2119         /*
2120          * Check if there are pending parity attentions. If there are - set
2121          * RECOVERY_IN_PROGRESS.
2122          */
2123         if (IS_PF(sc) && bnx2x_chk_parity_attn(sc, &global, FALSE)) {
2124                 bnx2x_set_reset_in_progress(sc);
2125
2126                 /* Set RESET_IS_GLOBAL if needed */
2127                 if (global) {
2128                         bnx2x_set_reset_global(sc);
2129                 }
2130         }
2131
2132         /*
2133          * The last driver must disable a "close the gate" if there is no
2134          * parity attention or "process kill" pending.
2135          */
2136         if (IS_PF(sc) && !bnx2x_clear_pf_load(sc) &&
2137             bnx2x_reset_is_done(sc, SC_PATH(sc))) {
2138                 bnx2x_disable_close_the_gate(sc);
2139         }
2140
2141         PMD_DRV_LOG(DEBUG, sc, "Ended NIC unload");
2142
2143         return 0;
2144 }
2145
2146 /*
2147  * Encapsulte an mbuf cluster into the tx bd chain and makes the memory
2148  * visible to the controller.
2149  *
2150  * If an mbuf is submitted to this routine and cannot be given to the
2151  * controller (e.g. it has too many fragments) then the function may free
2152  * the mbuf and return to the caller.
2153  *
2154  * Returns:
2155  *     int: Number of TX BDs used for the mbuf
2156  *
2157  *   Note the side effect that an mbuf may be freed if it causes a problem.
2158  */
2159 int bnx2x_tx_encap(struct bnx2x_tx_queue *txq, struct rte_mbuf *m0)
2160 {
2161         struct eth_tx_start_bd *tx_start_bd;
2162         uint16_t bd_prod, pkt_prod;
2163         struct bnx2x_softc *sc;
2164         uint32_t nbds = 0;
2165
2166         sc = txq->sc;
2167         bd_prod = txq->tx_bd_tail;
2168         pkt_prod = txq->tx_pkt_tail;
2169
2170         txq->sw_ring[TX_BD(pkt_prod, txq)] = m0;
2171
2172         tx_start_bd = &txq->tx_ring[TX_BD(bd_prod, txq)].start_bd;
2173
2174         tx_start_bd->addr =
2175             rte_cpu_to_le_64(rte_mbuf_data_iova(m0));
2176         tx_start_bd->nbytes = rte_cpu_to_le_16(m0->data_len);
2177         tx_start_bd->bd_flags.as_bitfield = ETH_TX_BD_FLAGS_START_BD;
2178         tx_start_bd->general_data =
2179             (1 << ETH_TX_START_BD_HDR_NBDS_SHIFT);
2180
2181         tx_start_bd->nbd = rte_cpu_to_le_16(2);
2182
2183         if (m0->ol_flags & PKT_TX_VLAN_PKT) {
2184                 tx_start_bd->vlan_or_ethertype =
2185                     rte_cpu_to_le_16(m0->vlan_tci);
2186                 tx_start_bd->bd_flags.as_bitfield |=
2187                     (X_ETH_OUTBAND_VLAN <<
2188                      ETH_TX_BD_FLAGS_VLAN_MODE_SHIFT);
2189         } else {
2190                 if (IS_PF(sc))
2191                         tx_start_bd->vlan_or_ethertype =
2192                             rte_cpu_to_le_16(pkt_prod);
2193                 else {
2194                         struct ether_hdr *eh =
2195                             rte_pktmbuf_mtod(m0, struct ether_hdr *);
2196
2197                         tx_start_bd->vlan_or_ethertype =
2198                             rte_cpu_to_le_16(rte_be_to_cpu_16(eh->ether_type));
2199                 }
2200         }
2201
2202         bd_prod = NEXT_TX_BD(bd_prod);
2203         if (IS_VF(sc)) {
2204                 struct eth_tx_parse_bd_e2 *tx_parse_bd;
2205                 const struct ether_hdr *eh =
2206                     rte_pktmbuf_mtod(m0, struct ether_hdr *);
2207                 uint8_t mac_type = UNICAST_ADDRESS;
2208
2209                 tx_parse_bd =
2210                     &txq->tx_ring[TX_BD(bd_prod, txq)].parse_bd_e2;
2211                 if (is_multicast_ether_addr(&eh->d_addr)) {
2212                         if (is_broadcast_ether_addr(&eh->d_addr))
2213                                 mac_type = BROADCAST_ADDRESS;
2214                         else
2215                                 mac_type = MULTICAST_ADDRESS;
2216                 }
2217                 tx_parse_bd->parsing_data =
2218                     (mac_type << ETH_TX_PARSE_BD_E2_ETH_ADDR_TYPE_SHIFT);
2219
2220                 rte_memcpy(&tx_parse_bd->data.mac_addr.dst_hi,
2221                            &eh->d_addr.addr_bytes[0], 2);
2222                 rte_memcpy(&tx_parse_bd->data.mac_addr.dst_mid,
2223                            &eh->d_addr.addr_bytes[2], 2);
2224                 rte_memcpy(&tx_parse_bd->data.mac_addr.dst_lo,
2225                            &eh->d_addr.addr_bytes[4], 2);
2226                 rte_memcpy(&tx_parse_bd->data.mac_addr.src_hi,
2227                            &eh->s_addr.addr_bytes[0], 2);
2228                 rte_memcpy(&tx_parse_bd->data.mac_addr.src_mid,
2229                            &eh->s_addr.addr_bytes[2], 2);
2230                 rte_memcpy(&tx_parse_bd->data.mac_addr.src_lo,
2231                            &eh->s_addr.addr_bytes[4], 2);
2232
2233                 tx_parse_bd->data.mac_addr.dst_hi =
2234                     rte_cpu_to_be_16(tx_parse_bd->data.mac_addr.dst_hi);
2235                 tx_parse_bd->data.mac_addr.dst_mid =
2236                     rte_cpu_to_be_16(tx_parse_bd->data.
2237                                      mac_addr.dst_mid);
2238                 tx_parse_bd->data.mac_addr.dst_lo =
2239                     rte_cpu_to_be_16(tx_parse_bd->data.mac_addr.dst_lo);
2240                 tx_parse_bd->data.mac_addr.src_hi =
2241                     rte_cpu_to_be_16(tx_parse_bd->data.mac_addr.src_hi);
2242                 tx_parse_bd->data.mac_addr.src_mid =
2243                     rte_cpu_to_be_16(tx_parse_bd->data.
2244                                      mac_addr.src_mid);
2245                 tx_parse_bd->data.mac_addr.src_lo =
2246                     rte_cpu_to_be_16(tx_parse_bd->data.mac_addr.src_lo);
2247
2248                 PMD_TX_LOG(DEBUG,
2249                            "PBD dst %x %x %x src %x %x %x p_data %x",
2250                            tx_parse_bd->data.mac_addr.dst_hi,
2251                            tx_parse_bd->data.mac_addr.dst_mid,
2252                            tx_parse_bd->data.mac_addr.dst_lo,
2253                            tx_parse_bd->data.mac_addr.src_hi,
2254                            tx_parse_bd->data.mac_addr.src_mid,
2255                            tx_parse_bd->data.mac_addr.src_lo,
2256                            tx_parse_bd->parsing_data);
2257         }
2258
2259         PMD_TX_LOG(DEBUG,
2260                    "start bd: nbytes %d flags %x vlan %x",
2261                    tx_start_bd->nbytes,
2262                    tx_start_bd->bd_flags.as_bitfield,
2263                    tx_start_bd->vlan_or_ethertype);
2264
2265         bd_prod = NEXT_TX_BD(bd_prod);
2266         pkt_prod++;
2267
2268         if (TX_IDX(bd_prod) < 2)
2269                 nbds++;
2270
2271         txq->nb_tx_avail -= 2;
2272         txq->tx_bd_tail = bd_prod;
2273         txq->tx_pkt_tail = pkt_prod;
2274
2275         return nbds + 2;
2276 }
2277
2278 static uint16_t bnx2x_cid_ilt_lines(struct bnx2x_softc *sc)
2279 {
2280         return L2_ILT_LINES(sc);
2281 }
2282
2283 static void bnx2x_ilt_set_info(struct bnx2x_softc *sc)
2284 {
2285         struct ilt_client_info *ilt_client;
2286         struct ecore_ilt *ilt = sc->ilt;
2287         uint16_t line = 0;
2288
2289         PMD_INIT_FUNC_TRACE(sc);
2290
2291         ilt->start_line = FUNC_ILT_BASE(SC_FUNC(sc));
2292
2293         /* CDU */
2294         ilt_client = &ilt->clients[ILT_CLIENT_CDU];
2295         ilt_client->client_num = ILT_CLIENT_CDU;
2296         ilt_client->page_size = CDU_ILT_PAGE_SZ;
2297         ilt_client->flags = ILT_CLIENT_SKIP_MEM;
2298         ilt_client->start = line;
2299         line += bnx2x_cid_ilt_lines(sc);
2300
2301         if (CNIC_SUPPORT(sc)) {
2302                 line += CNIC_ILT_LINES;
2303         }
2304
2305         ilt_client->end = (line - 1);
2306
2307         /* QM */
2308         if (QM_INIT(sc->qm_cid_count)) {
2309                 ilt_client = &ilt->clients[ILT_CLIENT_QM];
2310                 ilt_client->client_num = ILT_CLIENT_QM;
2311                 ilt_client->page_size = QM_ILT_PAGE_SZ;
2312                 ilt_client->flags = 0;
2313                 ilt_client->start = line;
2314
2315                 /* 4 bytes for each cid */
2316                 line += DIV_ROUND_UP(sc->qm_cid_count * QM_QUEUES_PER_FUNC * 4,
2317                                      QM_ILT_PAGE_SZ);
2318
2319                 ilt_client->end = (line - 1);
2320         }
2321
2322         if (CNIC_SUPPORT(sc)) {
2323                 /* SRC */
2324                 ilt_client = &ilt->clients[ILT_CLIENT_SRC];
2325                 ilt_client->client_num = ILT_CLIENT_SRC;
2326                 ilt_client->page_size = SRC_ILT_PAGE_SZ;
2327                 ilt_client->flags = 0;
2328                 ilt_client->start = line;
2329                 line += SRC_ILT_LINES;
2330                 ilt_client->end = (line - 1);
2331
2332                 /* TM */
2333                 ilt_client = &ilt->clients[ILT_CLIENT_TM];
2334                 ilt_client->client_num = ILT_CLIENT_TM;
2335                 ilt_client->page_size = TM_ILT_PAGE_SZ;
2336                 ilt_client->flags = 0;
2337                 ilt_client->start = line;
2338                 line += TM_ILT_LINES;
2339                 ilt_client->end = (line - 1);
2340         }
2341
2342         assert((line <= ILT_MAX_LINES));
2343 }
2344
2345 static void bnx2x_set_fp_rx_buf_size(struct bnx2x_softc *sc)
2346 {
2347         int i;
2348
2349         for (i = 0; i < sc->num_queues; i++) {
2350                 /* get the Rx buffer size for RX frames */
2351                 sc->fp[i].rx_buf_size =
2352                     (IP_HEADER_ALIGNMENT_PADDING + ETH_OVERHEAD + sc->mtu);
2353         }
2354 }
2355
2356 int bnx2x_alloc_ilt_mem(struct bnx2x_softc *sc)
2357 {
2358
2359         sc->ilt = rte_malloc("", sizeof(struct ecore_ilt), RTE_CACHE_LINE_SIZE);
2360
2361         return sc->ilt == NULL;
2362 }
2363
2364 static int bnx2x_alloc_ilt_lines_mem(struct bnx2x_softc *sc)
2365 {
2366         sc->ilt->lines = rte_calloc("",
2367                                     sizeof(struct ilt_line), ILT_MAX_LINES,
2368                                     RTE_CACHE_LINE_SIZE);
2369         return sc->ilt->lines == NULL;
2370 }
2371
2372 void bnx2x_free_ilt_mem(struct bnx2x_softc *sc)
2373 {
2374         rte_free(sc->ilt);
2375         sc->ilt = NULL;
2376 }
2377
2378 static void bnx2x_free_ilt_lines_mem(struct bnx2x_softc *sc)
2379 {
2380         if (sc->ilt->lines != NULL) {
2381                 rte_free(sc->ilt->lines);
2382                 sc->ilt->lines = NULL;
2383         }
2384 }
2385
2386 static void bnx2x_free_mem(struct bnx2x_softc *sc)
2387 {
2388         uint32_t i;
2389
2390         for (i = 0; i < L2_ILT_LINES(sc); i++) {
2391                 sc->context[i].vcxt = NULL;
2392                 sc->context[i].size = 0;
2393         }
2394
2395         ecore_ilt_mem_op(sc, ILT_MEMOP_FREE);
2396
2397         bnx2x_free_ilt_lines_mem(sc);
2398 }
2399
2400 static int bnx2x_alloc_mem(struct bnx2x_softc *sc)
2401 {
2402         int context_size;
2403         int allocated;
2404         int i;
2405         char cdu_name[RTE_MEMZONE_NAMESIZE];
2406
2407         /*
2408          * Allocate memory for CDU context:
2409          * This memory is allocated separately and not in the generic ILT
2410          * functions because CDU differs in few aspects:
2411          * 1. There can be multiple entities allocating memory for context -
2412          * regular L2, CNIC, and SRIOV drivers. Each separately controls
2413          * its own ILT lines.
2414          * 2. Since CDU page-size is not a single 4KB page (which is the case
2415          * for the other ILT clients), to be efficient we want to support
2416          * allocation of sub-page-size in the last entry.
2417          * 3. Context pointers are used by the driver to pass to FW / update
2418          * the context (for the other ILT clients the pointers are used just to
2419          * free the memory during unload).
2420          */
2421         context_size = (sizeof(union cdu_context) * BNX2X_L2_CID_COUNT(sc));
2422         for (i = 0, allocated = 0; allocated < context_size; i++) {
2423                 sc->context[i].size = min(CDU_ILT_PAGE_SZ,
2424                                           (context_size - allocated));
2425
2426                 snprintf(cdu_name, sizeof(cdu_name), "cdu_%d", i);
2427                 if (bnx2x_dma_alloc(sc, sc->context[i].size,
2428                                   &sc->context[i].vcxt_dma,
2429                                   cdu_name, BNX2X_PAGE_SIZE) != 0) {
2430                         bnx2x_free_mem(sc);
2431                         return -1;
2432                 }
2433
2434                 sc->context[i].vcxt =
2435                     (union cdu_context *)sc->context[i].vcxt_dma.vaddr;
2436
2437                 allocated += sc->context[i].size;
2438         }
2439
2440         bnx2x_alloc_ilt_lines_mem(sc);
2441
2442         if (ecore_ilt_mem_op(sc, ILT_MEMOP_ALLOC)) {
2443                 PMD_DRV_LOG(NOTICE, sc, "ecore_ilt_mem_op ILT_MEMOP_ALLOC failed");
2444                 bnx2x_free_mem(sc);
2445                 return -1;
2446         }
2447
2448         return 0;
2449 }
2450
2451 static void bnx2x_free_fw_stats_mem(struct bnx2x_softc *sc)
2452 {
2453         bnx2x_dma_free(&sc->fw_stats_dma);
2454         sc->fw_stats_num = 0;
2455
2456         sc->fw_stats_req_size = 0;
2457         sc->fw_stats_req = NULL;
2458         sc->fw_stats_req_mapping = 0;
2459
2460         sc->fw_stats_data_size = 0;
2461         sc->fw_stats_data = NULL;
2462         sc->fw_stats_data_mapping = 0;
2463 }
2464
2465 static int bnx2x_alloc_fw_stats_mem(struct bnx2x_softc *sc)
2466 {
2467         uint8_t num_queue_stats;
2468         int num_groups, vf_headroom = 0;
2469
2470         /* number of queues for statistics is number of eth queues */
2471         num_queue_stats = BNX2X_NUM_ETH_QUEUES(sc);
2472
2473         /*
2474          * Total number of FW statistics requests =
2475          *   1 for port stats + 1 for PF stats + num of queues
2476          */
2477         sc->fw_stats_num = (2 + num_queue_stats);
2478
2479         /*
2480          * Request is built from stats_query_header and an array of
2481          * stats_query_cmd_group each of which contains STATS_QUERY_CMD_COUNT
2482          * rules. The real number or requests is configured in the
2483          * stats_query_header.
2484          */
2485         num_groups = (sc->fw_stats_num + vf_headroom) / STATS_QUERY_CMD_COUNT;
2486         if ((sc->fw_stats_num + vf_headroom) % STATS_QUERY_CMD_COUNT)
2487                 num_groups++;
2488
2489         sc->fw_stats_req_size =
2490             (sizeof(struct stats_query_header) +
2491              (num_groups * sizeof(struct stats_query_cmd_group)));
2492
2493         /*
2494          * Data for statistics requests + stats_counter.
2495          * stats_counter holds per-STORM counters that are incremented when
2496          * STORM has finished with the current request. Memory for FCoE
2497          * offloaded statistics are counted anyway, even if they will not be sent.
2498          * VF stats are not accounted for here as the data of VF stats is stored
2499          * in memory allocated by the VF, not here.
2500          */
2501         sc->fw_stats_data_size =
2502             (sizeof(struct stats_counter) +
2503              sizeof(struct per_port_stats) + sizeof(struct per_pf_stats) +
2504              /* sizeof(struct fcoe_statistics_params) + */
2505              (sizeof(struct per_queue_stats) * num_queue_stats));
2506
2507         if (bnx2x_dma_alloc(sc, (sc->fw_stats_req_size + sc->fw_stats_data_size),
2508                           &sc->fw_stats_dma, "fw_stats",
2509                           RTE_CACHE_LINE_SIZE) != 0) {
2510                 bnx2x_free_fw_stats_mem(sc);
2511                 return -1;
2512         }
2513
2514         /* set up the shortcuts */
2515
2516         sc->fw_stats_req = (struct bnx2x_fw_stats_req *)sc->fw_stats_dma.vaddr;
2517         sc->fw_stats_req_mapping = sc->fw_stats_dma.paddr;
2518
2519         sc->fw_stats_data =
2520             (struct bnx2x_fw_stats_data *)((uint8_t *) sc->fw_stats_dma.vaddr +
2521                                          sc->fw_stats_req_size);
2522         sc->fw_stats_data_mapping = (sc->fw_stats_dma.paddr +
2523                                      sc->fw_stats_req_size);
2524
2525         return 0;
2526 }
2527
2528 /*
2529  * Bits map:
2530  * 0-7  - Engine0 load counter.
2531  * 8-15 - Engine1 load counter.
2532  * 16   - Engine0 RESET_IN_PROGRESS bit.
2533  * 17   - Engine1 RESET_IN_PROGRESS bit.
2534  * 18   - Engine0 ONE_IS_LOADED. Set when there is at least one active
2535  *        function on the engine
2536  * 19   - Engine1 ONE_IS_LOADED.
2537  * 20   - Chip reset flow bit. When set none-leader must wait for both engines
2538  *        leader to complete (check for both RESET_IN_PROGRESS bits and not
2539  *        for just the one belonging to its engine).
2540  */
2541 #define BNX2X_RECOVERY_GLOB_REG     MISC_REG_GENERIC_POR_1
2542 #define BNX2X_PATH0_LOAD_CNT_MASK   0x000000ff
2543 #define BNX2X_PATH0_LOAD_CNT_SHIFT  0
2544 #define BNX2X_PATH1_LOAD_CNT_MASK   0x0000ff00
2545 #define BNX2X_PATH1_LOAD_CNT_SHIFT  8
2546 #define BNX2X_PATH0_RST_IN_PROG_BIT 0x00010000
2547 #define BNX2X_PATH1_RST_IN_PROG_BIT 0x00020000
2548 #define BNX2X_GLOBAL_RESET_BIT      0x00040000
2549
2550 /* set the GLOBAL_RESET bit, should be run under rtnl lock */
2551 static void bnx2x_set_reset_global(struct bnx2x_softc *sc)
2552 {
2553         uint32_t val;
2554         bnx2x_acquire_hw_lock(sc, HW_LOCK_RESOURCE_RECOVERY_REG);
2555         val = REG_RD(sc, BNX2X_RECOVERY_GLOB_REG);
2556         REG_WR(sc, BNX2X_RECOVERY_GLOB_REG, val | BNX2X_GLOBAL_RESET_BIT);
2557         bnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_RECOVERY_REG);
2558 }
2559
2560 /* clear the GLOBAL_RESET bit, should be run under rtnl lock */
2561 static void bnx2x_clear_reset_global(struct bnx2x_softc *sc)
2562 {
2563         uint32_t val;
2564         bnx2x_acquire_hw_lock(sc, HW_LOCK_RESOURCE_RECOVERY_REG);
2565         val = REG_RD(sc, BNX2X_RECOVERY_GLOB_REG);
2566         REG_WR(sc, BNX2X_RECOVERY_GLOB_REG, val & (~BNX2X_GLOBAL_RESET_BIT));
2567         bnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_RECOVERY_REG);
2568 }
2569
2570 /* checks the GLOBAL_RESET bit, should be run under rtnl lock */
2571 static uint8_t bnx2x_reset_is_global(struct bnx2x_softc *sc)
2572 {
2573         return REG_RD(sc, BNX2X_RECOVERY_GLOB_REG) & BNX2X_GLOBAL_RESET_BIT;
2574 }
2575
2576 /* clear RESET_IN_PROGRESS bit for the engine, should be run under rtnl lock */
2577 static void bnx2x_set_reset_done(struct bnx2x_softc *sc)
2578 {
2579         uint32_t val;
2580         uint32_t bit = SC_PATH(sc) ? BNX2X_PATH1_RST_IN_PROG_BIT :
2581             BNX2X_PATH0_RST_IN_PROG_BIT;
2582
2583         bnx2x_acquire_hw_lock(sc, HW_LOCK_RESOURCE_RECOVERY_REG);
2584
2585         val = REG_RD(sc, BNX2X_RECOVERY_GLOB_REG);
2586         /* Clear the bit */
2587         val &= ~bit;
2588         REG_WR(sc, BNX2X_RECOVERY_GLOB_REG, val);
2589
2590         bnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_RECOVERY_REG);
2591 }
2592
2593 /* set RESET_IN_PROGRESS for the engine, should be run under rtnl lock */
2594 static void bnx2x_set_reset_in_progress(struct bnx2x_softc *sc)
2595 {
2596         uint32_t val;
2597         uint32_t bit = SC_PATH(sc) ? BNX2X_PATH1_RST_IN_PROG_BIT :
2598             BNX2X_PATH0_RST_IN_PROG_BIT;
2599
2600         bnx2x_acquire_hw_lock(sc, HW_LOCK_RESOURCE_RECOVERY_REG);
2601
2602         val = REG_RD(sc, BNX2X_RECOVERY_GLOB_REG);
2603         /* Set the bit */
2604         val |= bit;
2605         REG_WR(sc, BNX2X_RECOVERY_GLOB_REG, val);
2606
2607         bnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_RECOVERY_REG);
2608 }
2609
2610 /* check RESET_IN_PROGRESS bit for an engine, should be run under rtnl lock */
2611 static uint8_t bnx2x_reset_is_done(struct bnx2x_softc *sc, int engine)
2612 {
2613         uint32_t val = REG_RD(sc, BNX2X_RECOVERY_GLOB_REG);
2614         uint32_t bit = engine ? BNX2X_PATH1_RST_IN_PROG_BIT :
2615             BNX2X_PATH0_RST_IN_PROG_BIT;
2616
2617         /* return false if bit is set */
2618         return (val & bit) ? FALSE : TRUE;
2619 }
2620
2621 /* get the load status for an engine, should be run under rtnl lock */
2622 static uint8_t bnx2x_get_load_status(struct bnx2x_softc *sc, int engine)
2623 {
2624         uint32_t mask = engine ? BNX2X_PATH1_LOAD_CNT_MASK :
2625             BNX2X_PATH0_LOAD_CNT_MASK;
2626         uint32_t shift = engine ? BNX2X_PATH1_LOAD_CNT_SHIFT :
2627             BNX2X_PATH0_LOAD_CNT_SHIFT;
2628         uint32_t val = REG_RD(sc, BNX2X_RECOVERY_GLOB_REG);
2629
2630         val = ((val & mask) >> shift);
2631
2632         return val != 0;
2633 }
2634
2635 /* set pf load mark */
2636 static void bnx2x_set_pf_load(struct bnx2x_softc *sc)
2637 {
2638         uint32_t val;
2639         uint32_t val1;
2640         uint32_t mask = SC_PATH(sc) ? BNX2X_PATH1_LOAD_CNT_MASK :
2641             BNX2X_PATH0_LOAD_CNT_MASK;
2642         uint32_t shift = SC_PATH(sc) ? BNX2X_PATH1_LOAD_CNT_SHIFT :
2643             BNX2X_PATH0_LOAD_CNT_SHIFT;
2644
2645         bnx2x_acquire_hw_lock(sc, HW_LOCK_RESOURCE_RECOVERY_REG);
2646
2647         PMD_INIT_FUNC_TRACE(sc);
2648
2649         val = REG_RD(sc, BNX2X_RECOVERY_GLOB_REG);
2650
2651         /* get the current counter value */
2652         val1 = ((val & mask) >> shift);
2653
2654         /* set bit of this PF */
2655         val1 |= (1 << SC_ABS_FUNC(sc));
2656
2657         /* clear the old value */
2658         val &= ~mask;
2659
2660         /* set the new one */
2661         val |= ((val1 << shift) & mask);
2662
2663         REG_WR(sc, BNX2X_RECOVERY_GLOB_REG, val);
2664
2665         bnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_RECOVERY_REG);
2666 }
2667
2668 /* clear pf load mark */
2669 static uint8_t bnx2x_clear_pf_load(struct bnx2x_softc *sc)
2670 {
2671         uint32_t val1, val;
2672         uint32_t mask = SC_PATH(sc) ? BNX2X_PATH1_LOAD_CNT_MASK :
2673             BNX2X_PATH0_LOAD_CNT_MASK;
2674         uint32_t shift = SC_PATH(sc) ? BNX2X_PATH1_LOAD_CNT_SHIFT :
2675             BNX2X_PATH0_LOAD_CNT_SHIFT;
2676
2677         bnx2x_acquire_hw_lock(sc, HW_LOCK_RESOURCE_RECOVERY_REG);
2678         val = REG_RD(sc, BNX2X_RECOVERY_GLOB_REG);
2679
2680         /* get the current counter value */
2681         val1 = (val & mask) >> shift;
2682
2683         /* clear bit of that PF */
2684         val1 &= ~(1 << SC_ABS_FUNC(sc));
2685
2686         /* clear the old value */
2687         val &= ~mask;
2688
2689         /* set the new one */
2690         val |= ((val1 << shift) & mask);
2691
2692         REG_WR(sc, BNX2X_RECOVERY_GLOB_REG, val);
2693         bnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_RECOVERY_REG);
2694         return val1 != 0;
2695 }
2696
2697 /* send load requrest to mcp and analyze response */
2698 static int bnx2x_nic_load_request(struct bnx2x_softc *sc, uint32_t * load_code)
2699 {
2700         PMD_INIT_FUNC_TRACE(sc);
2701
2702         /* init fw_seq */
2703         sc->fw_seq =
2704             (SHMEM_RD(sc, func_mb[SC_FW_MB_IDX(sc)].drv_mb_header) &
2705              DRV_MSG_SEQ_NUMBER_MASK);
2706
2707         PMD_DRV_LOG(DEBUG, sc, "initial fw_seq 0x%04x", sc->fw_seq);
2708
2709 #ifdef BNX2X_PULSE
2710         /* get the current FW pulse sequence */
2711         sc->fw_drv_pulse_wr_seq =
2712             (SHMEM_RD(sc, func_mb[SC_FW_MB_IDX(sc)].drv_pulse_mb) &
2713              DRV_PULSE_SEQ_MASK);
2714 #else
2715         /* set ALWAYS_ALIVE bit in shmem */
2716         sc->fw_drv_pulse_wr_seq |= DRV_PULSE_ALWAYS_ALIVE;
2717         bnx2x_drv_pulse(sc);
2718 #endif
2719
2720         /* load request */
2721         (*load_code) = bnx2x_fw_command(sc, DRV_MSG_CODE_LOAD_REQ,
2722                                       DRV_MSG_CODE_LOAD_REQ_WITH_LFA);
2723
2724         /* if the MCP fails to respond we must abort */
2725         if (!(*load_code)) {
2726                 PMD_DRV_LOG(NOTICE, sc, "MCP response failure!");
2727                 return -1;
2728         }
2729
2730         /* if MCP refused then must abort */
2731         if ((*load_code) == FW_MSG_CODE_DRV_LOAD_REFUSED) {
2732                 PMD_DRV_LOG(NOTICE, sc, "MCP refused load request");
2733                 return -1;
2734         }
2735
2736         return 0;
2737 }
2738
2739 /*
2740  * Check whether another PF has already loaded FW to chip. In virtualized
2741  * environments a pf from anoth VM may have already initialized the device
2742  * including loading FW.
2743  */
2744 static int bnx2x_nic_load_analyze_req(struct bnx2x_softc *sc, uint32_t load_code)
2745 {
2746         uint32_t my_fw, loaded_fw;
2747
2748         /* is another pf loaded on this engine? */
2749         if ((load_code != FW_MSG_CODE_DRV_LOAD_COMMON_CHIP) &&
2750             (load_code != FW_MSG_CODE_DRV_LOAD_COMMON)) {
2751                 /* build my FW version dword */
2752                 my_fw = (BNX2X_5710_FW_MAJOR_VERSION +
2753                          (BNX2X_5710_FW_MINOR_VERSION << 8) +
2754                          (BNX2X_5710_FW_REVISION_VERSION << 16) +
2755                          (BNX2X_5710_FW_ENGINEERING_VERSION << 24));
2756
2757                 /* read loaded FW from chip */
2758                 loaded_fw = REG_RD(sc, XSEM_REG_PRAM);
2759                 PMD_DRV_LOG(DEBUG, sc, "loaded FW 0x%08x / my FW 0x%08x",
2760                             loaded_fw, my_fw);
2761
2762                 /* abort nic load if version mismatch */
2763                 if (my_fw != loaded_fw) {
2764                         PMD_DRV_LOG(NOTICE, sc,
2765                                     "FW 0x%08x already loaded (mine is 0x%08x)",
2766                                     loaded_fw, my_fw);
2767                         return -1;
2768                 }
2769         }
2770
2771         return 0;
2772 }
2773
2774 /* mark PMF if applicable */
2775 static void bnx2x_nic_load_pmf(struct bnx2x_softc *sc, uint32_t load_code)
2776 {
2777         uint32_t ncsi_oem_data_addr;
2778
2779         PMD_INIT_FUNC_TRACE(sc);
2780
2781         if ((load_code == FW_MSG_CODE_DRV_LOAD_COMMON) ||
2782             (load_code == FW_MSG_CODE_DRV_LOAD_COMMON_CHIP) ||
2783             (load_code == FW_MSG_CODE_DRV_LOAD_PORT)) {
2784                 /*
2785                  * Barrier here for ordering between the writing to sc->port.pmf here
2786                  * and reading it from the periodic task.
2787                  */
2788                 sc->port.pmf = 1;
2789                 mb();
2790         } else {
2791                 sc->port.pmf = 0;
2792         }
2793
2794         PMD_DRV_LOG(DEBUG, sc, "pmf %d", sc->port.pmf);
2795
2796         if (load_code == FW_MSG_CODE_DRV_LOAD_COMMON_CHIP) {
2797                 if (SHMEM2_HAS(sc, ncsi_oem_data_addr)) {
2798                         ncsi_oem_data_addr = SHMEM2_RD(sc, ncsi_oem_data_addr);
2799                         if (ncsi_oem_data_addr) {
2800                                 REG_WR(sc,
2801                                        (ncsi_oem_data_addr +
2802                                         offsetof(struct glob_ncsi_oem_data,
2803                                                  driver_version)), 0);
2804                         }
2805                 }
2806         }
2807 }
2808
2809 static void bnx2x_read_mf_cfg(struct bnx2x_softc *sc)
2810 {
2811         int n = (CHIP_IS_MODE_4_PORT(sc) ? 2 : 1);
2812         int abs_func;
2813         int vn;
2814
2815         if (BNX2X_NOMCP(sc)) {
2816                 return;         /* what should be the default bvalue in this case */
2817         }
2818
2819         /*
2820          * The formula for computing the absolute function number is...
2821          * For 2 port configuration (4 functions per port):
2822          *   abs_func = 2 * vn + SC_PORT + SC_PATH
2823          * For 4 port configuration (2 functions per port):
2824          *   abs_func = 4 * vn + 2 * SC_PORT + SC_PATH
2825          */
2826         for (vn = VN_0; vn < SC_MAX_VN_NUM(sc); vn++) {
2827                 abs_func = (n * (2 * vn + SC_PORT(sc)) + SC_PATH(sc));
2828                 if (abs_func >= E1H_FUNC_MAX) {
2829                         break;
2830                 }
2831                 sc->devinfo.mf_info.mf_config[vn] =
2832                     MFCFG_RD(sc, func_mf_config[abs_func].config);
2833         }
2834
2835         if (sc->devinfo.mf_info.mf_config[SC_VN(sc)] &
2836             FUNC_MF_CFG_FUNC_DISABLED) {
2837                 PMD_DRV_LOG(DEBUG, sc, "mf_cfg function disabled");
2838                 sc->flags |= BNX2X_MF_FUNC_DIS;
2839         } else {
2840                 PMD_DRV_LOG(DEBUG, sc, "mf_cfg function enabled");
2841                 sc->flags &= ~BNX2X_MF_FUNC_DIS;
2842         }
2843 }
2844
2845 /* acquire split MCP access lock register */
2846 static int bnx2x_acquire_alr(struct bnx2x_softc *sc)
2847 {
2848         uint32_t j, val;
2849
2850         for (j = 0; j < 1000; j++) {
2851                 val = (1UL << 31);
2852                 REG_WR(sc, GRCBASE_MCP + 0x9c, val);
2853                 val = REG_RD(sc, GRCBASE_MCP + 0x9c);
2854                 if (val & (1L << 31))
2855                         break;
2856
2857                 DELAY(5000);
2858         }
2859
2860         if (!(val & (1L << 31))) {
2861                 PMD_DRV_LOG(NOTICE, sc, "Cannot acquire MCP access lock register");
2862                 return -1;
2863         }
2864
2865         return 0;
2866 }
2867
2868 /* release split MCP access lock register */
2869 static void bnx2x_release_alr(struct bnx2x_softc *sc)
2870 {
2871         REG_WR(sc, GRCBASE_MCP + 0x9c, 0);
2872 }
2873
2874 static void bnx2x_fan_failure(struct bnx2x_softc *sc)
2875 {
2876         int port = SC_PORT(sc);
2877         uint32_t ext_phy_config;
2878
2879         /* mark the failure */
2880         ext_phy_config =
2881             SHMEM_RD(sc, dev_info.port_hw_config[port].external_phy_config);
2882
2883         ext_phy_config &= ~PORT_HW_CFG_XGXS_EXT_PHY_TYPE_MASK;
2884         ext_phy_config |= PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE;
2885         SHMEM_WR(sc, dev_info.port_hw_config[port].external_phy_config,
2886                  ext_phy_config);
2887
2888         /* log the failure */
2889         PMD_DRV_LOG(INFO, sc,
2890                     "Fan Failure has caused the driver to shutdown "
2891                     "the card to prevent permanent damage. "
2892                     "Please contact OEM Support for assistance");
2893
2894         rte_panic("Schedule task to handle fan failure");
2895 }
2896
2897 /* this function is called upon a link interrupt */
2898 static void bnx2x_link_attn(struct bnx2x_softc *sc)
2899 {
2900         uint32_t pause_enabled = 0;
2901         struct host_port_stats *pstats;
2902         int cmng_fns;
2903
2904         /* Make sure that we are synced with the current statistics */
2905         bnx2x_stats_handle(sc, STATS_EVENT_STOP);
2906
2907         elink_link_update(&sc->link_params, &sc->link_vars);
2908
2909         if (sc->link_vars.link_up) {
2910
2911                 /* dropless flow control */
2912                 if (sc->dropless_fc) {
2913                         pause_enabled = 0;
2914
2915                         if (sc->link_vars.flow_ctrl & ELINK_FLOW_CTRL_TX) {
2916                                 pause_enabled = 1;
2917                         }
2918
2919                         REG_WR(sc,
2920                                (BAR_USTRORM_INTMEM +
2921                                 USTORM_ETH_PAUSE_ENABLED_OFFSET(SC_PORT(sc))),
2922                                pause_enabled);
2923                 }
2924
2925                 if (sc->link_vars.mac_type != ELINK_MAC_TYPE_EMAC) {
2926                         pstats = BNX2X_SP(sc, port_stats);
2927                         /* reset old mac stats */
2928                         memset(&(pstats->mac_stx[0]), 0,
2929                                sizeof(struct mac_stx));
2930                 }
2931
2932                 if (sc->state == BNX2X_STATE_OPEN) {
2933                         bnx2x_stats_handle(sc, STATS_EVENT_LINK_UP);
2934                 }
2935         }
2936
2937         if (sc->link_vars.link_up && sc->link_vars.line_speed) {
2938                 cmng_fns = bnx2x_get_cmng_fns_mode(sc);
2939
2940                 if (cmng_fns != CMNG_FNS_NONE) {
2941                         bnx2x_cmng_fns_init(sc, FALSE, cmng_fns);
2942                         storm_memset_cmng(sc, &sc->cmng, SC_PORT(sc));
2943                 }
2944         }
2945
2946         bnx2x_link_report_locked(sc);
2947
2948         if (IS_MF(sc)) {
2949                 bnx2x_link_sync_notify(sc);
2950         }
2951 }
2952
2953 static void bnx2x_attn_int_asserted(struct bnx2x_softc *sc, uint32_t asserted)
2954 {
2955         int port = SC_PORT(sc);
2956         uint32_t aeu_addr = port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 :
2957             MISC_REG_AEU_MASK_ATTN_FUNC_0;
2958         uint32_t nig_int_mask_addr = port ? NIG_REG_MASK_INTERRUPT_PORT1 :
2959             NIG_REG_MASK_INTERRUPT_PORT0;
2960         uint32_t aeu_mask;
2961         uint32_t nig_mask = 0;
2962         uint32_t reg_addr;
2963         uint32_t igu_acked;
2964         uint32_t cnt;
2965
2966         if (sc->attn_state & asserted) {
2967                 PMD_DRV_LOG(ERR, sc, "IGU ERROR attn=0x%08x", asserted);
2968         }
2969
2970         bnx2x_acquire_hw_lock(sc, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
2971
2972         aeu_mask = REG_RD(sc, aeu_addr);
2973
2974         aeu_mask &= ~(asserted & 0x3ff);
2975
2976         REG_WR(sc, aeu_addr, aeu_mask);
2977
2978         bnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
2979
2980         sc->attn_state |= asserted;
2981
2982         if (asserted & ATTN_HARD_WIRED_MASK) {
2983                 if (asserted & ATTN_NIG_FOR_FUNC) {
2984
2985                         bnx2x_acquire_phy_lock(sc);
2986                         /* save nig interrupt mask */
2987                         nig_mask = REG_RD(sc, nig_int_mask_addr);
2988
2989                         /* If nig_mask is not set, no need to call the update function */
2990                         if (nig_mask) {
2991                                 REG_WR(sc, nig_int_mask_addr, 0);
2992
2993                                 bnx2x_link_attn(sc);
2994                         }
2995
2996                         /* handle unicore attn? */
2997                 }
2998
2999                 if (asserted & ATTN_SW_TIMER_4_FUNC) {
3000                         PMD_DRV_LOG(DEBUG, sc, "ATTN_SW_TIMER_4_FUNC!");
3001                 }
3002
3003                 if (asserted & GPIO_2_FUNC) {
3004                         PMD_DRV_LOG(DEBUG, sc, "GPIO_2_FUNC!");
3005                 }
3006
3007                 if (asserted & GPIO_3_FUNC) {
3008                         PMD_DRV_LOG(DEBUG, sc, "GPIO_3_FUNC!");
3009                 }
3010
3011                 if (asserted & GPIO_4_FUNC) {
3012                         PMD_DRV_LOG(DEBUG, sc, "GPIO_4_FUNC!");
3013                 }
3014
3015                 if (port == 0) {
3016                         if (asserted & ATTN_GENERAL_ATTN_1) {
3017                                 PMD_DRV_LOG(DEBUG, sc, "ATTN_GENERAL_ATTN_1!");
3018                                 REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_1, 0x0);
3019                         }
3020                         if (asserted & ATTN_GENERAL_ATTN_2) {
3021                                 PMD_DRV_LOG(DEBUG, sc, "ATTN_GENERAL_ATTN_2!");
3022                                 REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_2, 0x0);
3023                         }
3024                         if (asserted & ATTN_GENERAL_ATTN_3) {
3025                                 PMD_DRV_LOG(DEBUG, sc, "ATTN_GENERAL_ATTN_3!");
3026                                 REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_3, 0x0);
3027                         }
3028                 } else {
3029                         if (asserted & ATTN_GENERAL_ATTN_4) {
3030                                 PMD_DRV_LOG(DEBUG, sc, "ATTN_GENERAL_ATTN_4!");
3031                                 REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_4, 0x0);
3032                         }
3033                         if (asserted & ATTN_GENERAL_ATTN_5) {
3034                                 PMD_DRV_LOG(DEBUG, sc, "ATTN_GENERAL_ATTN_5!");
3035                                 REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_5, 0x0);
3036                         }
3037                         if (asserted & ATTN_GENERAL_ATTN_6) {
3038                                 PMD_DRV_LOG(DEBUG, sc, "ATTN_GENERAL_ATTN_6!");
3039                                 REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_6, 0x0);
3040                         }
3041                 }
3042         }
3043         /* hardwired */
3044         if (sc->devinfo.int_block == INT_BLOCK_HC) {
3045                 reg_addr =
3046                     (HC_REG_COMMAND_REG + port * 32 +
3047                      COMMAND_REG_ATTN_BITS_SET);
3048         } else {
3049                 reg_addr = (BAR_IGU_INTMEM + IGU_CMD_ATTN_BIT_SET_UPPER * 8);
3050         }
3051
3052         PMD_DRV_LOG(DEBUG, sc, "about to mask 0x%08x at %s addr 0x%08x",
3053                     asserted,
3054                     (sc->devinfo.int_block == INT_BLOCK_HC) ? "HC" : "IGU",
3055                     reg_addr);
3056         REG_WR(sc, reg_addr, asserted);
3057
3058         /* now set back the mask */
3059         if (asserted & ATTN_NIG_FOR_FUNC) {
3060                 /*
3061                  * Verify that IGU ack through BAR was written before restoring
3062                  * NIG mask. This loop should exit after 2-3 iterations max.
3063                  */
3064                 if (sc->devinfo.int_block != INT_BLOCK_HC) {
3065                         cnt = 0;
3066
3067                         do {
3068                                 igu_acked =
3069                                     REG_RD(sc, IGU_REG_ATTENTION_ACK_BITS);
3070                         } while (((igu_acked & ATTN_NIG_FOR_FUNC) == 0)
3071                                  && (++cnt < MAX_IGU_ATTN_ACK_TO));
3072
3073                         if (!igu_acked) {
3074                                 PMD_DRV_LOG(ERR, sc,
3075                                             "Failed to verify IGU ack on time");
3076                         }
3077
3078                         mb();
3079                 }
3080
3081                 REG_WR(sc, nig_int_mask_addr, nig_mask);
3082
3083                 bnx2x_release_phy_lock(sc);
3084         }
3085 }
3086
3087 static void
3088 bnx2x_print_next_block(__rte_unused struct bnx2x_softc *sc, __rte_unused int idx,
3089                      __rte_unused const char *blk)
3090 {
3091         PMD_DRV_LOG(INFO, sc, "%s%s", idx ? ", " : "", blk);
3092 }
3093
3094 static int
3095 bnx2x_check_blocks_with_parity0(struct bnx2x_softc *sc, uint32_t sig, int par_num,
3096                               uint8_t print)
3097 {
3098         uint32_t cur_bit = 0;
3099         int i = 0;
3100
3101         for (i = 0; sig; i++) {
3102                 cur_bit = ((uint32_t) 0x1 << i);
3103                 if (sig & cur_bit) {
3104                         switch (cur_bit) {
3105                         case AEU_INPUTS_ATTN_BITS_BRB_PARITY_ERROR:
3106                                 if (print)
3107                                         bnx2x_print_next_block(sc, par_num++,
3108                                                              "BRB");
3109                                 break;
3110                         case AEU_INPUTS_ATTN_BITS_PARSER_PARITY_ERROR:
3111                                 if (print)
3112                                         bnx2x_print_next_block(sc, par_num++,
3113                                                              "PARSER");
3114                                 break;
3115                         case AEU_INPUTS_ATTN_BITS_TSDM_PARITY_ERROR:
3116                                 if (print)
3117                                         bnx2x_print_next_block(sc, par_num++,
3118                                                              "TSDM");
3119                                 break;
3120                         case AEU_INPUTS_ATTN_BITS_SEARCHER_PARITY_ERROR:
3121                                 if (print)
3122                                         bnx2x_print_next_block(sc, par_num++,
3123                                                              "SEARCHER");
3124                                 break;
3125                         case AEU_INPUTS_ATTN_BITS_TCM_PARITY_ERROR:
3126                                 if (print)
3127                                         bnx2x_print_next_block(sc, par_num++,
3128                                                              "TCM");
3129                                 break;
3130                         case AEU_INPUTS_ATTN_BITS_TSEMI_PARITY_ERROR:
3131                                 if (print)
3132                                         bnx2x_print_next_block(sc, par_num++,
3133                                                              "TSEMI");
3134                                 break;
3135                         case AEU_INPUTS_ATTN_BITS_PBCLIENT_PARITY_ERROR:
3136                                 if (print)
3137                                         bnx2x_print_next_block(sc, par_num++,
3138                                                              "XPB");
3139                                 break;
3140                         }
3141
3142                         /* Clear the bit */
3143                         sig &= ~cur_bit;
3144                 }
3145         }
3146
3147         return par_num;
3148 }
3149
3150 static int
3151 bnx2x_check_blocks_with_parity1(struct bnx2x_softc *sc, uint32_t sig, int par_num,
3152                               uint8_t * global, uint8_t print)
3153 {
3154         int i = 0;
3155         uint32_t cur_bit = 0;
3156         for (i = 0; sig; i++) {
3157                 cur_bit = ((uint32_t) 0x1 << i);
3158                 if (sig & cur_bit) {
3159                         switch (cur_bit) {
3160                         case AEU_INPUTS_ATTN_BITS_PBF_PARITY_ERROR:
3161                                 if (print)
3162                                         bnx2x_print_next_block(sc, par_num++,
3163                                                              "PBF");
3164                                 break;
3165                         case AEU_INPUTS_ATTN_BITS_QM_PARITY_ERROR:
3166                                 if (print)
3167                                         bnx2x_print_next_block(sc, par_num++,
3168                                                              "QM");
3169                                 break;
3170                         case AEU_INPUTS_ATTN_BITS_TIMERS_PARITY_ERROR:
3171                                 if (print)
3172                                         bnx2x_print_next_block(sc, par_num++,
3173                                                              "TM");
3174                                 break;
3175                         case AEU_INPUTS_ATTN_BITS_XSDM_PARITY_ERROR:
3176                                 if (print)
3177                                         bnx2x_print_next_block(sc, par_num++,
3178                                                              "XSDM");
3179                                 break;
3180                         case AEU_INPUTS_ATTN_BITS_XCM_PARITY_ERROR:
3181                                 if (print)
3182                                         bnx2x_print_next_block(sc, par_num++,
3183                                                              "XCM");
3184                                 break;
3185                         case AEU_INPUTS_ATTN_BITS_XSEMI_PARITY_ERROR:
3186                                 if (print)
3187                                         bnx2x_print_next_block(sc, par_num++,
3188                                                              "XSEMI");
3189                                 break;
3190                         case AEU_INPUTS_ATTN_BITS_DOORBELLQ_PARITY_ERROR:
3191                                 if (print)
3192                                         bnx2x_print_next_block(sc, par_num++,
3193                                                              "DOORBELLQ");
3194                                 break;
3195                         case AEU_INPUTS_ATTN_BITS_NIG_PARITY_ERROR:
3196                                 if (print)
3197                                         bnx2x_print_next_block(sc, par_num++,
3198                                                              "NIG");
3199                                 break;
3200                         case AEU_INPUTS_ATTN_BITS_VAUX_PCI_CORE_PARITY_ERROR:
3201                                 if (print)
3202                                         bnx2x_print_next_block(sc, par_num++,
3203                                                              "VAUX PCI CORE");
3204                                 *global = TRUE;
3205                                 break;
3206                         case AEU_INPUTS_ATTN_BITS_DEBUG_PARITY_ERROR:
3207                                 if (print)
3208                                         bnx2x_print_next_block(sc, par_num++,
3209                                                              "DEBUG");
3210                                 break;
3211                         case AEU_INPUTS_ATTN_BITS_USDM_PARITY_ERROR:
3212                                 if (print)
3213                                         bnx2x_print_next_block(sc, par_num++,
3214                                                              "USDM");
3215                                 break;
3216                         case AEU_INPUTS_ATTN_BITS_UCM_PARITY_ERROR:
3217                                 if (print)
3218                                         bnx2x_print_next_block(sc, par_num++,
3219                                                              "UCM");
3220                                 break;
3221                         case AEU_INPUTS_ATTN_BITS_USEMI_PARITY_ERROR:
3222                                 if (print)
3223                                         bnx2x_print_next_block(sc, par_num++,
3224                                                              "USEMI");
3225                                 break;
3226                         case AEU_INPUTS_ATTN_BITS_UPB_PARITY_ERROR:
3227                                 if (print)
3228                                         bnx2x_print_next_block(sc, par_num++,
3229                                                              "UPB");
3230                                 break;
3231                         case AEU_INPUTS_ATTN_BITS_CSDM_PARITY_ERROR:
3232                                 if (print)
3233                                         bnx2x_print_next_block(sc, par_num++,
3234                                                              "CSDM");
3235                                 break;
3236                         case AEU_INPUTS_ATTN_BITS_CCM_PARITY_ERROR:
3237                                 if (print)
3238                                         bnx2x_print_next_block(sc, par_num++,
3239                                                              "CCM");
3240                                 break;
3241                         }
3242
3243                         /* Clear the bit */
3244                         sig &= ~cur_bit;
3245                 }
3246         }
3247
3248         return par_num;
3249 }
3250
3251 static int
3252 bnx2x_check_blocks_with_parity2(struct bnx2x_softc *sc, uint32_t sig, int par_num,
3253                               uint8_t print)
3254 {
3255         uint32_t cur_bit = 0;
3256         int i = 0;
3257
3258         for (i = 0; sig; i++) {
3259                 cur_bit = ((uint32_t) 0x1 << i);
3260                 if (sig & cur_bit) {
3261                         switch (cur_bit) {
3262                         case AEU_INPUTS_ATTN_BITS_CSEMI_PARITY_ERROR:
3263                                 if (print)
3264                                         bnx2x_print_next_block(sc, par_num++,
3265                                                              "CSEMI");
3266                                 break;
3267                         case AEU_INPUTS_ATTN_BITS_PXP_PARITY_ERROR:
3268                                 if (print)
3269                                         bnx2x_print_next_block(sc, par_num++,
3270                                                              "PXP");
3271                                 break;
3272                         case AEU_IN_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR:
3273                                 if (print)
3274                                         bnx2x_print_next_block(sc, par_num++,
3275                                                              "PXPPCICLOCKCLIENT");
3276                                 break;
3277                         case AEU_INPUTS_ATTN_BITS_CFC_PARITY_ERROR:
3278                                 if (print)
3279                                         bnx2x_print_next_block(sc, par_num++,
3280                                                              "CFC");
3281                                 break;
3282                         case AEU_INPUTS_ATTN_BITS_CDU_PARITY_ERROR:
3283                                 if (print)
3284                                         bnx2x_print_next_block(sc, par_num++,
3285                                                              "CDU");
3286                                 break;
3287                         case AEU_INPUTS_ATTN_BITS_DMAE_PARITY_ERROR:
3288                                 if (print)
3289                                         bnx2x_print_next_block(sc, par_num++,
3290                                                              "DMAE");
3291                                 break;
3292                         case AEU_INPUTS_ATTN_BITS_IGU_PARITY_ERROR:
3293                                 if (print)
3294                                         bnx2x_print_next_block(sc, par_num++,
3295                                                              "IGU");
3296                                 break;
3297                         case AEU_INPUTS_ATTN_BITS_MISC_PARITY_ERROR:
3298                                 if (print)
3299                                         bnx2x_print_next_block(sc, par_num++,
3300                                                              "MISC");
3301                                 break;
3302                         }
3303
3304                         /* Clear the bit */
3305                         sig &= ~cur_bit;
3306                 }
3307         }
3308
3309         return par_num;
3310 }
3311
3312 static int
3313 bnx2x_check_blocks_with_parity3(struct bnx2x_softc *sc, uint32_t sig, int par_num,
3314                               uint8_t * global, uint8_t print)
3315 {
3316         uint32_t cur_bit = 0;
3317         int i = 0;
3318
3319         for (i = 0; sig; i++) {
3320                 cur_bit = ((uint32_t) 0x1 << i);
3321                 if (sig & cur_bit) {
3322                         switch (cur_bit) {
3323                         case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_ROM_PARITY:
3324                                 if (print)
3325                                         bnx2x_print_next_block(sc, par_num++,
3326                                                              "MCP ROM");
3327                                 *global = TRUE;
3328                                 break;
3329                         case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_RX_PARITY:
3330                                 if (print)
3331                                         bnx2x_print_next_block(sc, par_num++,
3332                                                              "MCP UMP RX");
3333                                 *global = TRUE;
3334                                 break;
3335                         case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_TX_PARITY:
3336                                 if (print)
3337                                         bnx2x_print_next_block(sc, par_num++,
3338                                                              "MCP UMP TX");
3339                                 *global = TRUE;
3340                                 break;
3341                         case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_SCPAD_PARITY:
3342                                 if (print)
3343                                         bnx2x_print_next_block(sc, par_num++,
3344                                                              "MCP SCPAD");
3345                                 *global = TRUE;
3346                                 break;
3347                         }
3348
3349                         /* Clear the bit */
3350                         sig &= ~cur_bit;
3351                 }
3352         }
3353
3354         return par_num;
3355 }
3356
3357 static int
3358 bnx2x_check_blocks_with_parity4(struct bnx2x_softc *sc, uint32_t sig, int par_num,
3359                               uint8_t print)
3360 {
3361         uint32_t cur_bit = 0;
3362         int i = 0;
3363
3364         for (i = 0; sig; i++) {
3365                 cur_bit = ((uint32_t) 0x1 << i);
3366                 if (sig & cur_bit) {
3367                         switch (cur_bit) {
3368                         case AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR:
3369                                 if (print)
3370                                         bnx2x_print_next_block(sc, par_num++,
3371                                                              "PGLUE_B");
3372                                 break;
3373                         case AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR:
3374                                 if (print)
3375                                         bnx2x_print_next_block(sc, par_num++,
3376                                                              "ATC");
3377                                 break;
3378                         }
3379
3380                         /* Clear the bit */
3381                         sig &= ~cur_bit;
3382                 }
3383         }
3384
3385         return par_num;
3386 }
3387
3388 static uint8_t
3389 bnx2x_parity_attn(struct bnx2x_softc *sc, uint8_t * global, uint8_t print,
3390                 uint32_t * sig)
3391 {
3392         int par_num = 0;
3393
3394         if ((sig[0] & HW_PRTY_ASSERT_SET_0) ||
3395             (sig[1] & HW_PRTY_ASSERT_SET_1) ||
3396             (sig[2] & HW_PRTY_ASSERT_SET_2) ||
3397             (sig[3] & HW_PRTY_ASSERT_SET_3) ||
3398             (sig[4] & HW_PRTY_ASSERT_SET_4)) {
3399                 PMD_DRV_LOG(ERR, sc,
3400                             "Parity error: HW block parity attention:"
3401                             "[0]:0x%08x [1]:0x%08x [2]:0x%08x [3]:0x%08x [4]:0x%08x",
3402                             (uint32_t) (sig[0] & HW_PRTY_ASSERT_SET_0),
3403                             (uint32_t) (sig[1] & HW_PRTY_ASSERT_SET_1),
3404                             (uint32_t) (sig[2] & HW_PRTY_ASSERT_SET_2),
3405                             (uint32_t) (sig[3] & HW_PRTY_ASSERT_SET_3),
3406                             (uint32_t) (sig[4] & HW_PRTY_ASSERT_SET_4));
3407
3408                 if (print)
3409                         PMD_DRV_LOG(INFO, sc, "Parity errors detected in blocks: ");
3410
3411                 par_num =
3412                     bnx2x_check_blocks_with_parity0(sc, sig[0] &
3413                                                   HW_PRTY_ASSERT_SET_0,
3414                                                   par_num, print);
3415                 par_num =
3416                     bnx2x_check_blocks_with_parity1(sc, sig[1] &
3417                                                   HW_PRTY_ASSERT_SET_1,
3418                                                   par_num, global, print);
3419                 par_num =
3420                     bnx2x_check_blocks_with_parity2(sc, sig[2] &
3421                                                   HW_PRTY_ASSERT_SET_2,
3422                                                   par_num, print);
3423                 par_num =
3424                     bnx2x_check_blocks_with_parity3(sc, sig[3] &
3425                                                   HW_PRTY_ASSERT_SET_3,
3426                                                   par_num, global, print);
3427                 par_num =
3428                     bnx2x_check_blocks_with_parity4(sc, sig[4] &
3429                                                   HW_PRTY_ASSERT_SET_4,
3430                                                   par_num, print);
3431
3432                 if (print)
3433                         PMD_DRV_LOG(INFO, sc, "");
3434
3435                 return TRUE;
3436         }
3437
3438         return FALSE;
3439 }
3440
3441 static uint8_t
3442 bnx2x_chk_parity_attn(struct bnx2x_softc *sc, uint8_t * global, uint8_t print)
3443 {
3444         struct attn_route attn = { {0} };
3445         int port = SC_PORT(sc);
3446
3447         attn.sig[0] = REG_RD(sc, MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 + port * 4);
3448         attn.sig[1] = REG_RD(sc, MISC_REG_AEU_AFTER_INVERT_2_FUNC_0 + port * 4);
3449         attn.sig[2] = REG_RD(sc, MISC_REG_AEU_AFTER_INVERT_3_FUNC_0 + port * 4);
3450         attn.sig[3] = REG_RD(sc, MISC_REG_AEU_AFTER_INVERT_4_FUNC_0 + port * 4);
3451
3452         if (!CHIP_IS_E1x(sc))
3453                 attn.sig[4] =
3454                     REG_RD(sc, MISC_REG_AEU_AFTER_INVERT_5_FUNC_0 + port * 4);
3455
3456         return bnx2x_parity_attn(sc, global, print, attn.sig);
3457 }
3458
3459 static void bnx2x_attn_int_deasserted4(struct bnx2x_softc *sc, uint32_t attn)
3460 {
3461         uint32_t val;
3462
3463         if (attn & AEU_INPUTS_ATTN_BITS_PGLUE_HW_INTERRUPT) {
3464                 val = REG_RD(sc, PGLUE_B_REG_PGLUE_B_INT_STS_CLR);
3465                 PMD_DRV_LOG(INFO, sc, "ERROR: PGLUE hw attention 0x%08x", val);
3466                 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_ADDRESS_ERROR)
3467                         PMD_DRV_LOG(INFO, sc,
3468                                     "ERROR: PGLUE_B_PGLUE_B_INT_STS_REG_ADDRESS_ERROR");
3469                 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_INCORRECT_RCV_BEHAVIOR)
3470                         PMD_DRV_LOG(INFO, sc,
3471                                     "ERROR: PGLUE_B_PGLUE_B_INT_STS_REG_INCORRECT_RCV_BEHAVIOR");
3472                 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_WAS_ERROR_ATTN)
3473                         PMD_DRV_LOG(INFO, sc,
3474                                     "ERROR: PGLUE_B_PGLUE_B_INT_STS_REG_WAS_ERROR_ATTN");
3475                 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_VF_LENGTH_VIOLATION_ATTN)
3476                         PMD_DRV_LOG(INFO, sc,
3477                                     "ERROR: PGLUE_B_PGLUE_B_INT_STS_REG_VF_LENGTH_VIOLATION_ATTN");
3478                 if (val &
3479                     PGLUE_B_PGLUE_B_INT_STS_REG_VF_GRC_SPACE_VIOLATION_ATTN)
3480                         PMD_DRV_LOG(INFO, sc,
3481                                     "ERROR: PGLUE_B_PGLUE_B_INT_STS_REG_VF_GRC_SPACE_VIOLATION_ATTN");
3482                 if (val &
3483                     PGLUE_B_PGLUE_B_INT_STS_REG_VF_MSIX_BAR_VIOLATION_ATTN)
3484                         PMD_DRV_LOG(INFO, sc,
3485                                     "ERROR: PGLUE_B_PGLUE_B_INT_STS_REG_VF_MSIX_BAR_VIOLATION_ATTN");
3486                 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_ERROR_ATTN)
3487                         PMD_DRV_LOG(INFO, sc,
3488                                     "ERROR: PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_ERROR_ATTN");
3489                 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_IN_TWO_RCBS_ATTN)
3490                         PMD_DRV_LOG(INFO, sc,
3491                                     "ERROR: PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_IN_TWO_RCBS_ATTN");
3492                 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_CSSNOOP_FIFO_OVERFLOW)
3493                         PMD_DRV_LOG(INFO, sc,
3494                                     "ERROR: PGLUE_B_PGLUE_B_INT_STS_REG_CSSNOOP_FIFO_OVERFLOW");
3495         }
3496
3497         if (attn & AEU_INPUTS_ATTN_BITS_ATC_HW_INTERRUPT) {
3498                 val = REG_RD(sc, ATC_REG_ATC_INT_STS_CLR);
3499                 PMD_DRV_LOG(INFO, sc, "ERROR: ATC hw attention 0x%08x", val);
3500                 if (val & ATC_ATC_INT_STS_REG_ADDRESS_ERROR)
3501                         PMD_DRV_LOG(INFO, sc,
3502                                     "ERROR: ATC_ATC_INT_STS_REG_ADDRESS_ERROR");
3503                 if (val & ATC_ATC_INT_STS_REG_ATC_TCPL_TO_NOT_PEND)
3504                         PMD_DRV_LOG(INFO, sc,
3505                                     "ERROR: ATC_ATC_INT_STS_REG_ATC_TCPL_TO_NOT_PEND");
3506                 if (val & ATC_ATC_INT_STS_REG_ATC_GPA_MULTIPLE_HITS)
3507                         PMD_DRV_LOG(INFO, sc,
3508                                     "ERROR: ATC_ATC_INT_STS_REG_ATC_GPA_MULTIPLE_HITS");
3509                 if (val & ATC_ATC_INT_STS_REG_ATC_RCPL_TO_EMPTY_CNT)
3510                         PMD_DRV_LOG(INFO, sc,
3511                                     "ERROR: ATC_ATC_INT_STS_REG_ATC_RCPL_TO_EMPTY_CNT");
3512                 if (val & ATC_ATC_INT_STS_REG_ATC_TCPL_ERROR)
3513                         PMD_DRV_LOG(INFO, sc,
3514                                     "ERROR: ATC_ATC_INT_STS_REG_ATC_TCPL_ERROR");
3515                 if (val & ATC_ATC_INT_STS_REG_ATC_IREQ_LESS_THAN_STU)
3516                         PMD_DRV_LOG(INFO, sc,
3517                                     "ERROR: ATC_ATC_INT_STS_REG_ATC_IREQ_LESS_THAN_STU");
3518         }
3519
3520         if (attn & (AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR |
3521                     AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR)) {
3522                 PMD_DRV_LOG(INFO, sc,
3523                             "ERROR: FATAL parity attention set4 0x%08x",
3524                             (uint32_t) (attn &
3525                                         (AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR
3526                                          |
3527                                          AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR)));
3528         }
3529 }
3530
3531 static void bnx2x_e1h_disable(struct bnx2x_softc *sc)
3532 {
3533         int port = SC_PORT(sc);
3534
3535         REG_WR(sc, NIG_REG_LLH0_FUNC_EN + port * 8, 0);
3536 }
3537
3538 static void bnx2x_e1h_enable(struct bnx2x_softc *sc)
3539 {
3540         int port = SC_PORT(sc);
3541
3542         REG_WR(sc, NIG_REG_LLH0_FUNC_EN + port * 8, 1);
3543 }
3544
3545 /*
3546  * called due to MCP event (on pmf):
3547  *   reread new bandwidth configuration
3548  *   configure FW
3549  *   notify others function about the change
3550  */
3551 static void bnx2x_config_mf_bw(struct bnx2x_softc *sc)
3552 {
3553         if (sc->link_vars.link_up) {
3554                 bnx2x_cmng_fns_init(sc, TRUE, CMNG_FNS_MINMAX);
3555                 bnx2x_link_sync_notify(sc);
3556         }
3557
3558         storm_memset_cmng(sc, &sc->cmng, SC_PORT(sc));
3559 }
3560
3561 static void bnx2x_set_mf_bw(struct bnx2x_softc *sc)
3562 {
3563         bnx2x_config_mf_bw(sc);
3564         bnx2x_fw_command(sc, DRV_MSG_CODE_SET_MF_BW_ACK, 0);
3565 }
3566
3567 static void bnx2x_handle_eee_event(struct bnx2x_softc *sc)
3568 {
3569         bnx2x_fw_command(sc, DRV_MSG_CODE_EEE_RESULTS_ACK, 0);
3570 }
3571
3572 #define DRV_INFO_ETH_STAT_NUM_MACS_REQUIRED 3
3573
3574 static void bnx2x_drv_info_ether_stat(struct bnx2x_softc *sc)
3575 {
3576         struct eth_stats_info *ether_stat = &sc->sp->drv_info_to_mcp.ether_stat;
3577
3578         strncpy(ether_stat->version, BNX2X_DRIVER_VERSION,
3579                 ETH_STAT_INFO_VERSION_LEN);
3580
3581         sc->sp_objs[0].mac_obj.get_n_elements(sc, &sc->sp_objs[0].mac_obj,
3582                                               DRV_INFO_ETH_STAT_NUM_MACS_REQUIRED,
3583                                               ether_stat->mac_local + MAC_PAD,
3584                                               MAC_PAD, ETH_ALEN);
3585
3586         ether_stat->mtu_size = sc->mtu;
3587
3588         ether_stat->feature_flags |= FEATURE_ETH_CHKSUM_OFFLOAD_MASK;
3589         ether_stat->promiscuous_mode = 0;       // (flags & PROMISC) ? 1 : 0;
3590
3591         ether_stat->txq_size = sc->tx_ring_size;
3592         ether_stat->rxq_size = sc->rx_ring_size;
3593 }
3594
3595 static void bnx2x_handle_drv_info_req(struct bnx2x_softc *sc)
3596 {
3597         enum drv_info_opcode op_code;
3598         uint32_t drv_info_ctl = SHMEM2_RD(sc, drv_info_control);
3599
3600         /* if drv_info version supported by MFW doesn't match - send NACK */
3601         if ((drv_info_ctl & DRV_INFO_CONTROL_VER_MASK) != DRV_INFO_CUR_VER) {
3602                 bnx2x_fw_command(sc, DRV_MSG_CODE_DRV_INFO_NACK, 0);
3603                 return;
3604         }
3605
3606         op_code = ((drv_info_ctl & DRV_INFO_CONTROL_OP_CODE_MASK) >>
3607                    DRV_INFO_CONTROL_OP_CODE_SHIFT);
3608
3609         memset(&sc->sp->drv_info_to_mcp, 0, sizeof(union drv_info_to_mcp));
3610
3611         switch (op_code) {
3612         case ETH_STATS_OPCODE:
3613                 bnx2x_drv_info_ether_stat(sc);
3614                 break;
3615         case FCOE_STATS_OPCODE:
3616         case ISCSI_STATS_OPCODE:
3617         default:
3618                 /* if op code isn't supported - send NACK */
3619                 bnx2x_fw_command(sc, DRV_MSG_CODE_DRV_INFO_NACK, 0);
3620                 return;
3621         }
3622
3623         /*
3624          * If we got drv_info attn from MFW then these fields are defined in
3625          * shmem2 for sure
3626          */
3627         SHMEM2_WR(sc, drv_info_host_addr_lo,
3628                   U64_LO(BNX2X_SP_MAPPING(sc, drv_info_to_mcp)));
3629         SHMEM2_WR(sc, drv_info_host_addr_hi,
3630                   U64_HI(BNX2X_SP_MAPPING(sc, drv_info_to_mcp)));
3631
3632         bnx2x_fw_command(sc, DRV_MSG_CODE_DRV_INFO_ACK, 0);
3633 }
3634
3635 static void bnx2x_dcc_event(struct bnx2x_softc *sc, uint32_t dcc_event)
3636 {
3637         if (dcc_event & DRV_STATUS_DCC_DISABLE_ENABLE_PF) {
3638 /*
3639  * This is the only place besides the function initialization
3640  * where the sc->flags can change so it is done without any
3641  * locks
3642  */
3643                 if (sc->devinfo.
3644                     mf_info.mf_config[SC_VN(sc)] & FUNC_MF_CFG_FUNC_DISABLED) {
3645                         PMD_DRV_LOG(DEBUG, sc, "mf_cfg function disabled");
3646                         sc->flags |= BNX2X_MF_FUNC_DIS;
3647                         bnx2x_e1h_disable(sc);
3648                 } else {
3649                         PMD_DRV_LOG(DEBUG, sc, "mf_cfg function enabled");
3650                         sc->flags &= ~BNX2X_MF_FUNC_DIS;
3651                         bnx2x_e1h_enable(sc);
3652                 }
3653                 dcc_event &= ~DRV_STATUS_DCC_DISABLE_ENABLE_PF;
3654         }
3655
3656         if (dcc_event & DRV_STATUS_DCC_BANDWIDTH_ALLOCATION) {
3657                 bnx2x_config_mf_bw(sc);
3658                 dcc_event &= ~DRV_STATUS_DCC_BANDWIDTH_ALLOCATION;
3659         }
3660
3661         /* Report results to MCP */
3662         if (dcc_event)
3663                 bnx2x_fw_command(sc, DRV_MSG_CODE_DCC_FAILURE, 0);
3664         else
3665                 bnx2x_fw_command(sc, DRV_MSG_CODE_DCC_OK, 0);
3666 }
3667
3668 static void bnx2x_pmf_update(struct bnx2x_softc *sc)
3669 {
3670         int port = SC_PORT(sc);
3671         uint32_t val;
3672
3673         sc->port.pmf = 1;
3674
3675         /*
3676          * We need the mb() to ensure the ordering between the writing to
3677          * sc->port.pmf here and reading it from the bnx2x_periodic_task().
3678          */
3679         mb();
3680
3681         /* enable nig attention */
3682         val = (0xff0f | (1 << (SC_VN(sc) + 4)));
3683         if (sc->devinfo.int_block == INT_BLOCK_HC) {
3684                 REG_WR(sc, HC_REG_TRAILING_EDGE_0 + port * 8, val);
3685                 REG_WR(sc, HC_REG_LEADING_EDGE_0 + port * 8, val);
3686         } else if (!CHIP_IS_E1x(sc)) {
3687                 REG_WR(sc, IGU_REG_TRAILING_EDGE_LATCH, val);
3688                 REG_WR(sc, IGU_REG_LEADING_EDGE_LATCH, val);
3689         }
3690
3691         bnx2x_stats_handle(sc, STATS_EVENT_PMF);
3692 }
3693
3694 static int bnx2x_mc_assert(struct bnx2x_softc *sc)
3695 {
3696         char last_idx;
3697         int i, rc = 0;
3698         __rte_unused uint32_t row0, row1, row2, row3;
3699
3700         /* XSTORM */
3701         last_idx =
3702             REG_RD8(sc, BAR_XSTRORM_INTMEM + XSTORM_ASSERT_LIST_INDEX_OFFSET);
3703         if (last_idx)
3704                 PMD_DRV_LOG(ERR, sc, "XSTORM_ASSERT_LIST_INDEX 0x%x", last_idx);
3705
3706         /* print the asserts */
3707         for (i = 0; i < STORM_ASSERT_ARRAY_SIZE; i++) {
3708
3709                 row0 =
3710                     REG_RD(sc,
3711                            BAR_XSTRORM_INTMEM + XSTORM_ASSERT_LIST_OFFSET(i));
3712                 row1 =
3713                     REG_RD(sc,
3714                            BAR_XSTRORM_INTMEM + XSTORM_ASSERT_LIST_OFFSET(i) +
3715                            4);
3716                 row2 =
3717                     REG_RD(sc,
3718                            BAR_XSTRORM_INTMEM + XSTORM_ASSERT_LIST_OFFSET(i) +
3719                            8);
3720                 row3 =
3721                     REG_RD(sc,
3722                            BAR_XSTRORM_INTMEM + XSTORM_ASSERT_LIST_OFFSET(i) +
3723                            12);
3724
3725                 if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) {
3726                         PMD_DRV_LOG(ERR, sc,
3727                                     "XSTORM_ASSERT_INDEX 0x%x = 0x%08x 0x%08x 0x%08x 0x%08x",
3728                                     i, row3, row2, row1, row0);
3729                         rc++;
3730                 } else {
3731                         break;
3732                 }
3733         }
3734
3735         /* TSTORM */
3736         last_idx =
3737             REG_RD8(sc, BAR_TSTRORM_INTMEM + TSTORM_ASSERT_LIST_INDEX_OFFSET);
3738         if (last_idx) {
3739                 PMD_DRV_LOG(ERR, sc, "TSTORM_ASSERT_LIST_INDEX 0x%x", last_idx);
3740         }
3741
3742         /* print the asserts */
3743         for (i = 0; i < STORM_ASSERT_ARRAY_SIZE; i++) {
3744
3745                 row0 =
3746                     REG_RD(sc,
3747                            BAR_TSTRORM_INTMEM + TSTORM_ASSERT_LIST_OFFSET(i));
3748                 row1 =
3749                     REG_RD(sc,
3750                            BAR_TSTRORM_INTMEM + TSTORM_ASSERT_LIST_OFFSET(i) +
3751                            4);
3752                 row2 =
3753                     REG_RD(sc,
3754                            BAR_TSTRORM_INTMEM + TSTORM_ASSERT_LIST_OFFSET(i) +
3755                            8);
3756                 row3 =
3757                     REG_RD(sc,
3758                            BAR_TSTRORM_INTMEM + TSTORM_ASSERT_LIST_OFFSET(i) +
3759                            12);
3760
3761                 if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) {
3762                         PMD_DRV_LOG(ERR, sc,
3763                                     "TSTORM_ASSERT_INDEX 0x%x = 0x%08x 0x%08x 0x%08x 0x%08x",
3764                                     i, row3, row2, row1, row0);
3765                         rc++;
3766                 } else {
3767                         break;
3768                 }
3769         }
3770
3771         /* CSTORM */
3772         last_idx =
3773             REG_RD8(sc, BAR_CSTRORM_INTMEM + CSTORM_ASSERT_LIST_INDEX_OFFSET);
3774         if (last_idx) {
3775                 PMD_DRV_LOG(ERR, sc, "CSTORM_ASSERT_LIST_INDEX 0x%x", last_idx);
3776         }
3777
3778         /* print the asserts */
3779         for (i = 0; i < STORM_ASSERT_ARRAY_SIZE; i++) {
3780
3781                 row0 =
3782                     REG_RD(sc,
3783                            BAR_CSTRORM_INTMEM + CSTORM_ASSERT_LIST_OFFSET(i));
3784                 row1 =
3785                     REG_RD(sc,
3786                            BAR_CSTRORM_INTMEM + CSTORM_ASSERT_LIST_OFFSET(i) +
3787                            4);
3788                 row2 =
3789                     REG_RD(sc,
3790                            BAR_CSTRORM_INTMEM + CSTORM_ASSERT_LIST_OFFSET(i) +
3791                            8);
3792                 row3 =
3793                     REG_RD(sc,
3794                            BAR_CSTRORM_INTMEM + CSTORM_ASSERT_LIST_OFFSET(i) +
3795                            12);
3796
3797                 if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) {
3798                         PMD_DRV_LOG(ERR, sc,
3799                                     "CSTORM_ASSERT_INDEX 0x%x = 0x%08x 0x%08x 0x%08x 0x%08x",
3800                                     i, row3, row2, row1, row0);
3801                         rc++;
3802                 } else {
3803                         break;
3804                 }
3805         }
3806
3807         /* USTORM */
3808         last_idx =
3809             REG_RD8(sc, BAR_USTRORM_INTMEM + USTORM_ASSERT_LIST_INDEX_OFFSET);
3810         if (last_idx) {
3811                 PMD_DRV_LOG(ERR, sc, "USTORM_ASSERT_LIST_INDEX 0x%x", last_idx);
3812         }
3813
3814         /* print the asserts */
3815         for (i = 0; i < STORM_ASSERT_ARRAY_SIZE; i++) {
3816
3817                 row0 =
3818                     REG_RD(sc,
3819                            BAR_USTRORM_INTMEM + USTORM_ASSERT_LIST_OFFSET(i));
3820                 row1 =
3821                     REG_RD(sc,
3822                            BAR_USTRORM_INTMEM + USTORM_ASSERT_LIST_OFFSET(i) +
3823                            4);
3824                 row2 =
3825                     REG_RD(sc,
3826                            BAR_USTRORM_INTMEM + USTORM_ASSERT_LIST_OFFSET(i) +
3827                            8);
3828                 row3 =
3829                     REG_RD(sc,
3830                            BAR_USTRORM_INTMEM + USTORM_ASSERT_LIST_OFFSET(i) +
3831                            12);
3832
3833                 if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) {
3834                         PMD_DRV_LOG(ERR, sc,
3835                                     "USTORM_ASSERT_INDEX 0x%x = 0x%08x 0x%08x 0x%08x 0x%08x",
3836                                     i, row3, row2, row1, row0);
3837                         rc++;
3838                 } else {
3839                         break;
3840                 }
3841         }
3842
3843         return rc;
3844 }
3845
3846 static void bnx2x_attn_int_deasserted3(struct bnx2x_softc *sc, uint32_t attn)
3847 {
3848         int func = SC_FUNC(sc);
3849         uint32_t val;
3850
3851         if (attn & EVEREST_GEN_ATTN_IN_USE_MASK) {
3852
3853                 if (attn & BNX2X_PMF_LINK_ASSERT(sc)) {
3854
3855                         REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_12 + func * 4, 0);
3856                         bnx2x_read_mf_cfg(sc);
3857                         sc->devinfo.mf_info.mf_config[SC_VN(sc)] =
3858                             MFCFG_RD(sc,
3859                                      func_mf_config[SC_ABS_FUNC(sc)].config);
3860                         val =
3861                             SHMEM_RD(sc, func_mb[SC_FW_MB_IDX(sc)].drv_status);
3862
3863                         if (val & DRV_STATUS_DCC_EVENT_MASK)
3864                                 bnx2x_dcc_event(sc,
3865                                               (val &
3866                                                DRV_STATUS_DCC_EVENT_MASK));
3867
3868                         if (val & DRV_STATUS_SET_MF_BW)
3869                                 bnx2x_set_mf_bw(sc);
3870
3871                         if (val & DRV_STATUS_DRV_INFO_REQ)
3872                                 bnx2x_handle_drv_info_req(sc);
3873
3874                         if ((sc->port.pmf == 0) && (val & DRV_STATUS_PMF))
3875                                 bnx2x_pmf_update(sc);
3876
3877                         if (val & DRV_STATUS_EEE_NEGOTIATION_RESULTS)
3878                                 bnx2x_handle_eee_event(sc);
3879
3880                         if (sc->link_vars.periodic_flags &
3881                             ELINK_PERIODIC_FLAGS_LINK_EVENT) {
3882                                 /* sync with link */
3883                                 bnx2x_acquire_phy_lock(sc);
3884                                 sc->link_vars.periodic_flags &=
3885                                     ~ELINK_PERIODIC_FLAGS_LINK_EVENT;
3886                                 bnx2x_release_phy_lock(sc);
3887                                 if (IS_MF(sc)) {
3888                                         bnx2x_link_sync_notify(sc);
3889                                 }
3890                                 bnx2x_link_report(sc);
3891                         }
3892
3893                         /*
3894                          * Always call it here: bnx2x_link_report() will
3895                          * prevent the link indication duplication.
3896                          */
3897                         bnx2x_link_status_update(sc);
3898
3899                 } else if (attn & BNX2X_MC_ASSERT_BITS) {
3900
3901                         PMD_DRV_LOG(ERR, sc, "MC assert!");
3902                         bnx2x_mc_assert(sc);
3903                         REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_10, 0);
3904                         REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_9, 0);
3905                         REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_8, 0);
3906                         REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_7, 0);
3907                         rte_panic("MC assert!");
3908
3909                 } else if (attn & BNX2X_MCP_ASSERT) {
3910
3911                         PMD_DRV_LOG(ERR, sc, "MCP assert!");
3912                         REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_11, 0);
3913
3914                 } else {
3915                         PMD_DRV_LOG(ERR, sc,
3916                                     "Unknown HW assert! (attn 0x%08x)", attn);
3917                 }
3918         }
3919
3920         if (attn & EVEREST_LATCHED_ATTN_IN_USE_MASK) {
3921                 PMD_DRV_LOG(ERR, sc, "LATCHED attention 0x%08x (masked)", attn);
3922                 if (attn & BNX2X_GRC_TIMEOUT) {
3923                         val = REG_RD(sc, MISC_REG_GRC_TIMEOUT_ATTN);
3924                         PMD_DRV_LOG(ERR, sc, "GRC time-out 0x%08x", val);
3925                 }
3926                 if (attn & BNX2X_GRC_RSV) {
3927                         val = REG_RD(sc, MISC_REG_GRC_RSV_ATTN);
3928                         PMD_DRV_LOG(ERR, sc, "GRC reserved 0x%08x", val);
3929                 }
3930                 REG_WR(sc, MISC_REG_AEU_CLR_LATCH_SIGNAL, 0x7ff);
3931         }
3932 }
3933
3934 static void bnx2x_attn_int_deasserted2(struct bnx2x_softc *sc, uint32_t attn)
3935 {
3936         int port = SC_PORT(sc);
3937         int reg_offset;
3938         uint32_t val0, mask0, val1, mask1;
3939         uint32_t val;
3940
3941         if (attn & AEU_INPUTS_ATTN_BITS_CFC_HW_INTERRUPT) {
3942                 val = REG_RD(sc, CFC_REG_CFC_INT_STS_CLR);
3943                 PMD_DRV_LOG(ERR, sc, "CFC hw attention 0x%08x", val);
3944 /* CFC error attention */
3945                 if (val & 0x2) {
3946                         PMD_DRV_LOG(ERR, sc, "FATAL error from CFC");
3947                 }
3948         }
3949
3950         if (attn & AEU_INPUTS_ATTN_BITS_PXP_HW_INTERRUPT) {
3951                 val = REG_RD(sc, PXP_REG_PXP_INT_STS_CLR_0);
3952                 PMD_DRV_LOG(ERR, sc, "PXP hw attention-0 0x%08x", val);
3953 /* RQ_USDMDP_FIFO_OVERFLOW */
3954                 if (val & 0x18000) {
3955                         PMD_DRV_LOG(ERR, sc, "FATAL error from PXP");
3956                 }
3957
3958                 if (!CHIP_IS_E1x(sc)) {
3959                         val = REG_RD(sc, PXP_REG_PXP_INT_STS_CLR_1);
3960                         PMD_DRV_LOG(ERR, sc, "PXP hw attention-1 0x%08x", val);
3961                 }
3962         }
3963 #define PXP2_EOP_ERROR_BIT  PXP2_PXP2_INT_STS_CLR_0_REG_WR_PGLUE_EOP_ERROR
3964 #define AEU_PXP2_HW_INT_BIT AEU_INPUTS_ATTN_BITS_PXPPCICLOCKCLIENT_HW_INTERRUPT
3965
3966         if (attn & AEU_PXP2_HW_INT_BIT) {
3967 /*  CQ47854 workaround do not panic on
3968  *  PXP2_PXP2_INT_STS_0_REG_WR_PGLUE_EOP_ERROR
3969  */
3970                 if (!CHIP_IS_E1x(sc)) {
3971                         mask0 = REG_RD(sc, PXP2_REG_PXP2_INT_MASK_0);
3972                         val1 = REG_RD(sc, PXP2_REG_PXP2_INT_STS_1);
3973                         mask1 = REG_RD(sc, PXP2_REG_PXP2_INT_MASK_1);
3974                         val0 = REG_RD(sc, PXP2_REG_PXP2_INT_STS_0);
3975                         /*
3976                          * If the only PXP2_EOP_ERROR_BIT is set in
3977                          * STS0 and STS1 - clear it
3978                          *
3979                          * probably we lose additional attentions between
3980                          * STS0 and STS_CLR0, in this case user will not
3981                          * be notified about them
3982                          */
3983                         if (val0 & mask0 & PXP2_EOP_ERROR_BIT &&
3984                             !(val1 & mask1))
3985                                 val0 = REG_RD(sc, PXP2_REG_PXP2_INT_STS_CLR_0);
3986
3987                         /* print the register, since no one can restore it */
3988                         PMD_DRV_LOG(ERR, sc,
3989                                     "PXP2_REG_PXP2_INT_STS_CLR_0 0x%08x", val0);
3990
3991                         /*
3992                          * if PXP2_PXP2_INT_STS_0_REG_WR_PGLUE_EOP_ERROR
3993                          * then notify
3994                          */
3995                         if (val0 & PXP2_EOP_ERROR_BIT) {
3996                                 PMD_DRV_LOG(ERR, sc, "PXP2_WR_PGLUE_EOP_ERROR");
3997
3998                                 /*
3999                                  * if only PXP2_PXP2_INT_STS_0_REG_WR_PGLUE_EOP_ERROR is
4000                                  * set then clear attention from PXP2 block without panic
4001                                  */
4002                                 if (((val0 & mask0) == PXP2_EOP_ERROR_BIT) &&
4003                                     ((val1 & mask1) == 0))
4004                                         attn &= ~AEU_PXP2_HW_INT_BIT;
4005                         }
4006                 }
4007         }
4008
4009         if (attn & HW_INTERRUT_ASSERT_SET_2) {
4010                 reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_2 :
4011                               MISC_REG_AEU_ENABLE1_FUNC_0_OUT_2);
4012
4013                 val = REG_RD(sc, reg_offset);
4014                 val &= ~(attn & HW_INTERRUT_ASSERT_SET_2);
4015                 REG_WR(sc, reg_offset, val);
4016
4017                 PMD_DRV_LOG(ERR, sc,
4018                             "FATAL HW block attention set2 0x%x",
4019                             (uint32_t) (attn & HW_INTERRUT_ASSERT_SET_2));
4020                 rte_panic("HW block attention set2");
4021         }
4022 }
4023
4024 static void bnx2x_attn_int_deasserted1(struct bnx2x_softc *sc, uint32_t attn)
4025 {
4026         int port = SC_PORT(sc);
4027         int reg_offset;
4028         uint32_t val;
4029
4030         if (attn & AEU_INPUTS_ATTN_BITS_DOORBELLQ_HW_INTERRUPT) {
4031                 val = REG_RD(sc, DORQ_REG_DORQ_INT_STS_CLR);
4032                 PMD_DRV_LOG(ERR, sc, "DB hw attention 0x%08x", val);
4033 /* DORQ discard attention */
4034                 if (val & 0x2) {
4035                         PMD_DRV_LOG(ERR, sc, "FATAL error from DORQ");
4036                 }
4037         }
4038
4039         if (attn & HW_INTERRUT_ASSERT_SET_1) {
4040                 reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_1 :
4041                               MISC_REG_AEU_ENABLE1_FUNC_0_OUT_1);
4042
4043                 val = REG_RD(sc, reg_offset);
4044                 val &= ~(attn & HW_INTERRUT_ASSERT_SET_1);
4045                 REG_WR(sc, reg_offset, val);
4046
4047                 PMD_DRV_LOG(ERR, sc,
4048                             "FATAL HW block attention set1 0x%08x",
4049                             (uint32_t) (attn & HW_INTERRUT_ASSERT_SET_1));
4050                 rte_panic("HW block attention set1");
4051         }
4052 }
4053
4054 static void bnx2x_attn_int_deasserted0(struct bnx2x_softc *sc, uint32_t attn)
4055 {
4056         int port = SC_PORT(sc);
4057         int reg_offset;
4058         uint32_t val;
4059
4060         reg_offset = (port) ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 :
4061             MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0;
4062
4063         if (attn & AEU_INPUTS_ATTN_BITS_SPIO5) {
4064                 val = REG_RD(sc, reg_offset);
4065                 val &= ~AEU_INPUTS_ATTN_BITS_SPIO5;
4066                 REG_WR(sc, reg_offset, val);
4067
4068                 PMD_DRV_LOG(WARNING, sc, "SPIO5 hw attention");
4069
4070 /* Fan failure attention */
4071                 elink_hw_reset_phy(&sc->link_params);
4072                 bnx2x_fan_failure(sc);
4073         }
4074
4075         if ((attn & sc->link_vars.aeu_int_mask) && sc->port.pmf) {
4076                 bnx2x_acquire_phy_lock(sc);
4077                 elink_handle_module_detect_int(&sc->link_params);
4078                 bnx2x_release_phy_lock(sc);
4079         }
4080
4081         if (attn & HW_INTERRUT_ASSERT_SET_0) {
4082                 val = REG_RD(sc, reg_offset);
4083                 val &= ~(attn & HW_INTERRUT_ASSERT_SET_0);
4084                 REG_WR(sc, reg_offset, val);
4085
4086                 rte_panic("FATAL HW block attention set0 0x%lx",
4087                           (attn & HW_INTERRUT_ASSERT_SET_0));
4088         }
4089 }
4090
4091 static void bnx2x_attn_int_deasserted(struct bnx2x_softc *sc, uint32_t deasserted)
4092 {
4093         struct attn_route attn;
4094         struct attn_route *group_mask;
4095         int port = SC_PORT(sc);
4096         int index;
4097         uint32_t reg_addr;
4098         uint32_t val;
4099         uint32_t aeu_mask;
4100         uint8_t global = FALSE;
4101
4102         /*
4103          * Need to take HW lock because MCP or other port might also
4104          * try to handle this event.
4105          */
4106         bnx2x_acquire_alr(sc);
4107
4108         if (bnx2x_chk_parity_attn(sc, &global, TRUE)) {
4109                 sc->recovery_state = BNX2X_RECOVERY_INIT;
4110
4111 /* disable HW interrupts */
4112                 bnx2x_int_disable(sc);
4113                 bnx2x_release_alr(sc);
4114                 return;
4115         }
4116
4117         attn.sig[0] = REG_RD(sc, MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 + port * 4);
4118         attn.sig[1] = REG_RD(sc, MISC_REG_AEU_AFTER_INVERT_2_FUNC_0 + port * 4);
4119         attn.sig[2] = REG_RD(sc, MISC_REG_AEU_AFTER_INVERT_3_FUNC_0 + port * 4);
4120         attn.sig[3] = REG_RD(sc, MISC_REG_AEU_AFTER_INVERT_4_FUNC_0 + port * 4);
4121         if (!CHIP_IS_E1x(sc)) {
4122                 attn.sig[4] =
4123                     REG_RD(sc, MISC_REG_AEU_AFTER_INVERT_5_FUNC_0 + port * 4);
4124         } else {
4125                 attn.sig[4] = 0;
4126         }
4127
4128         for (index = 0; index < MAX_DYNAMIC_ATTN_GRPS; index++) {
4129                 if (deasserted & (1 << index)) {
4130                         group_mask = &sc->attn_group[index];
4131
4132                         bnx2x_attn_int_deasserted4(sc,
4133                                                  attn.
4134                                                  sig[4] & group_mask->sig[4]);
4135                         bnx2x_attn_int_deasserted3(sc,
4136                                                  attn.
4137                                                  sig[3] & group_mask->sig[3]);
4138                         bnx2x_attn_int_deasserted1(sc,
4139                                                  attn.
4140                                                  sig[1] & group_mask->sig[1]);
4141                         bnx2x_attn_int_deasserted2(sc,
4142                                                  attn.
4143                                                  sig[2] & group_mask->sig[2]);
4144                         bnx2x_attn_int_deasserted0(sc,
4145                                                  attn.
4146                                                  sig[0] & group_mask->sig[0]);
4147                 }
4148         }
4149
4150         bnx2x_release_alr(sc);
4151
4152         if (sc->devinfo.int_block == INT_BLOCK_HC) {
4153                 reg_addr = (HC_REG_COMMAND_REG + port * 32 +
4154                             COMMAND_REG_ATTN_BITS_CLR);
4155         } else {
4156                 reg_addr = (BAR_IGU_INTMEM + IGU_CMD_ATTN_BIT_CLR_UPPER * 8);
4157         }
4158
4159         val = ~deasserted;
4160         PMD_DRV_LOG(DEBUG, sc,
4161                     "about to mask 0x%08x at %s addr 0x%08x", val,
4162                     (sc->devinfo.int_block == INT_BLOCK_HC) ? "HC" : "IGU",
4163                     reg_addr);
4164         REG_WR(sc, reg_addr, val);
4165
4166         if (~sc->attn_state & deasserted) {
4167                 PMD_DRV_LOG(ERR, sc, "IGU error");
4168         }
4169
4170         reg_addr = port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 :
4171             MISC_REG_AEU_MASK_ATTN_FUNC_0;
4172
4173         bnx2x_acquire_hw_lock(sc, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
4174
4175         aeu_mask = REG_RD(sc, reg_addr);
4176
4177         aeu_mask |= (deasserted & 0x3ff);
4178
4179         REG_WR(sc, reg_addr, aeu_mask);
4180         bnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
4181
4182         sc->attn_state &= ~deasserted;
4183 }
4184
4185 static void bnx2x_attn_int(struct bnx2x_softc *sc)
4186 {
4187         /* read local copy of bits */
4188         uint32_t attn_bits = le32toh(sc->def_sb->atten_status_block.attn_bits);
4189         uint32_t attn_ack =
4190             le32toh(sc->def_sb->atten_status_block.attn_bits_ack);
4191         uint32_t attn_state = sc->attn_state;
4192
4193         /* look for changed bits */
4194         uint32_t asserted = attn_bits & ~attn_ack & ~attn_state;
4195         uint32_t deasserted = ~attn_bits & attn_ack & attn_state;
4196
4197         PMD_DRV_LOG(DEBUG, sc,
4198                     "attn_bits 0x%08x attn_ack 0x%08x asserted 0x%08x deasserted 0x%08x",
4199                     attn_bits, attn_ack, asserted, deasserted);
4200
4201         if (~(attn_bits ^ attn_ack) & (attn_bits ^ attn_state)) {
4202                 PMD_DRV_LOG(ERR, sc, "BAD attention state");
4203         }
4204
4205         /* handle bits that were raised */
4206         if (asserted) {
4207                 bnx2x_attn_int_asserted(sc, asserted);
4208         }
4209
4210         if (deasserted) {
4211                 bnx2x_attn_int_deasserted(sc, deasserted);
4212         }
4213 }
4214
4215 static uint16_t bnx2x_update_dsb_idx(struct bnx2x_softc *sc)
4216 {
4217         struct host_sp_status_block *def_sb = sc->def_sb;
4218         uint16_t rc = 0;
4219
4220         if (!def_sb)
4221                 return 0;
4222
4223         mb();                   /* status block is written to by the chip */
4224
4225         if (sc->def_att_idx != def_sb->atten_status_block.attn_bits_index) {
4226                 sc->def_att_idx = def_sb->atten_status_block.attn_bits_index;
4227                 rc |= BNX2X_DEF_SB_ATT_IDX;
4228         }
4229
4230         if (sc->def_idx != def_sb->sp_sb.running_index) {
4231                 sc->def_idx = def_sb->sp_sb.running_index;
4232                 rc |= BNX2X_DEF_SB_IDX;
4233         }
4234
4235         mb();
4236
4237         return rc;
4238 }
4239
4240 static struct ecore_queue_sp_obj *bnx2x_cid_to_q_obj(struct bnx2x_softc *sc,
4241                                                           uint32_t cid)
4242 {
4243         return &sc->sp_objs[CID_TO_FP(cid, sc)].q_obj;
4244 }
4245
4246 static void bnx2x_handle_mcast_eqe(struct bnx2x_softc *sc)
4247 {
4248         struct ecore_mcast_ramrod_params rparam;
4249         int rc;
4250
4251         memset(&rparam, 0, sizeof(rparam));
4252
4253         rparam.mcast_obj = &sc->mcast_obj;
4254
4255         /* clear pending state for the last command */
4256         sc->mcast_obj.raw.clear_pending(&sc->mcast_obj.raw);
4257
4258         /* if there are pending mcast commands - send them */
4259         if (sc->mcast_obj.check_pending(&sc->mcast_obj)) {
4260                 rc = ecore_config_mcast(sc, &rparam, ECORE_MCAST_CMD_CONT);
4261                 if (rc < 0) {
4262                         PMD_DRV_LOG(INFO, sc,
4263                                     "Failed to send pending mcast commands (%d)",
4264                                     rc);
4265                 }
4266         }
4267 }
4268
4269 static void
4270 bnx2x_handle_classification_eqe(struct bnx2x_softc *sc, union event_ring_elem *elem)
4271 {
4272         unsigned long ramrod_flags = 0;
4273         int rc = 0;
4274         uint32_t cid = elem->message.data.eth_event.echo & BNX2X_SWCID_MASK;
4275         struct ecore_vlan_mac_obj *vlan_mac_obj;
4276
4277         /* always push next commands out, don't wait here */
4278         bnx2x_set_bit(RAMROD_CONT, &ramrod_flags);
4279
4280         switch (le32toh(elem->message.data.eth_event.echo) >> BNX2X_SWCID_SHIFT) {
4281         case ECORE_FILTER_MAC_PENDING:
4282                 PMD_DRV_LOG(DEBUG, sc, "Got SETUP_MAC completions");
4283                 vlan_mac_obj = &sc->sp_objs[cid].mac_obj;
4284                 break;
4285
4286         case ECORE_FILTER_MCAST_PENDING:
4287                 PMD_DRV_LOG(DEBUG, sc, "Got SETUP_MCAST completions");
4288                 bnx2x_handle_mcast_eqe(sc);
4289                 return;
4290
4291         default:
4292                 PMD_DRV_LOG(NOTICE, sc, "Unsupported classification command: %d",
4293                             elem->message.data.eth_event.echo);
4294                 return;
4295         }
4296
4297         rc = vlan_mac_obj->complete(sc, vlan_mac_obj, elem, &ramrod_flags);
4298
4299         if (rc < 0) {
4300                 PMD_DRV_LOG(NOTICE, sc,
4301                             "Failed to schedule new commands (%d)", rc);
4302         } else if (rc > 0) {
4303                 PMD_DRV_LOG(DEBUG, sc, "Scheduled next pending commands...");
4304         }
4305 }
4306
4307 static void bnx2x_handle_rx_mode_eqe(struct bnx2x_softc *sc)
4308 {
4309         bnx2x_clear_bit(ECORE_FILTER_RX_MODE_PENDING, &sc->sp_state);
4310
4311         /* send rx_mode command again if was requested */
4312         if (bnx2x_test_and_clear_bit(ECORE_FILTER_RX_MODE_SCHED, &sc->sp_state)) {
4313                 bnx2x_set_storm_rx_mode(sc);
4314         }
4315 }
4316
4317 static void bnx2x_update_eq_prod(struct bnx2x_softc *sc, uint16_t prod)
4318 {
4319         storm_memset_eq_prod(sc, prod, SC_FUNC(sc));
4320         wmb();                  /* keep prod updates ordered */
4321 }
4322
4323 static void bnx2x_eq_int(struct bnx2x_softc *sc)
4324 {
4325         uint16_t hw_cons, sw_cons, sw_prod;
4326         union event_ring_elem *elem;
4327         uint8_t echo;
4328         uint32_t cid;
4329         uint8_t opcode;
4330         int spqe_cnt = 0;
4331         struct ecore_queue_sp_obj *q_obj;
4332         struct ecore_func_sp_obj *f_obj = &sc->func_obj;
4333         struct ecore_raw_obj *rss_raw = &sc->rss_conf_obj.raw;
4334
4335         hw_cons = le16toh(*sc->eq_cons_sb);
4336
4337         /*
4338          * The hw_cons range is 1-255, 257 - the sw_cons range is 0-254, 256.
4339          * when we get to the next-page we need to adjust so the loop
4340          * condition below will be met. The next element is the size of a
4341          * regular element and hence incrementing by 1
4342          */
4343         if ((hw_cons & EQ_DESC_MAX_PAGE) == EQ_DESC_MAX_PAGE) {
4344                 hw_cons++;
4345         }
4346
4347         /*
4348          * This function may never run in parallel with itself for a
4349          * specific sc and no need for a read memory barrier here.
4350          */
4351         sw_cons = sc->eq_cons;
4352         sw_prod = sc->eq_prod;
4353
4354         for (;
4355              sw_cons != hw_cons;
4356              sw_prod = NEXT_EQ_IDX(sw_prod), sw_cons = NEXT_EQ_IDX(sw_cons)) {
4357
4358                 elem = &sc->eq[EQ_DESC(sw_cons)];
4359
4360 /* elem CID originates from FW, actually LE */
4361                 cid = SW_CID(elem->message.data.cfc_del_event.cid);
4362                 opcode = elem->message.opcode;
4363
4364 /* handle eq element */
4365                 switch (opcode) {
4366                 case EVENT_RING_OPCODE_STAT_QUERY:
4367                         PMD_DEBUG_PERIODIC_LOG(DEBUG, sc, "got statistics completion event %d",
4368                                     sc->stats_comp++);
4369                         /* nothing to do with stats comp */
4370                         goto next_spqe;
4371
4372                 case EVENT_RING_OPCODE_CFC_DEL:
4373                         /* handle according to cid range */
4374                         /* we may want to verify here that the sc state is HALTING */
4375                         PMD_DRV_LOG(DEBUG, sc, "got delete ramrod for MULTI[%d]",
4376                                     cid);
4377                         q_obj = bnx2x_cid_to_q_obj(sc, cid);
4378                         if (q_obj->complete_cmd(sc, q_obj, ECORE_Q_CMD_CFC_DEL)) {
4379                                 break;
4380                         }
4381                         goto next_spqe;
4382
4383                 case EVENT_RING_OPCODE_STOP_TRAFFIC:
4384                         PMD_DRV_LOG(DEBUG, sc, "got STOP TRAFFIC");
4385                         if (f_obj->complete_cmd(sc, f_obj, ECORE_F_CMD_TX_STOP)) {
4386                                 break;
4387                         }
4388                         goto next_spqe;
4389
4390                 case EVENT_RING_OPCODE_START_TRAFFIC:
4391                         PMD_DRV_LOG(DEBUG, sc, "got START TRAFFIC");
4392                         if (f_obj->complete_cmd
4393                             (sc, f_obj, ECORE_F_CMD_TX_START)) {
4394                                 break;
4395                         }
4396                         goto next_spqe;
4397
4398                 case EVENT_RING_OPCODE_FUNCTION_UPDATE:
4399                         echo = elem->message.data.function_update_event.echo;
4400                         if (echo == SWITCH_UPDATE) {
4401                                 PMD_DRV_LOG(DEBUG, sc,
4402                                             "got FUNC_SWITCH_UPDATE ramrod");
4403                                 if (f_obj->complete_cmd(sc, f_obj,
4404                                                         ECORE_F_CMD_SWITCH_UPDATE))
4405                                 {
4406                                         break;
4407                                 }
4408                         } else {
4409                                 PMD_DRV_LOG(DEBUG, sc,
4410                                             "AFEX: ramrod completed FUNCTION_UPDATE");
4411                                 f_obj->complete_cmd(sc, f_obj,
4412                                                     ECORE_F_CMD_AFEX_UPDATE);
4413                         }
4414                         goto next_spqe;
4415
4416                 case EVENT_RING_OPCODE_FORWARD_SETUP:
4417                         q_obj = &bnx2x_fwd_sp_obj(sc, q_obj);
4418                         if (q_obj->complete_cmd(sc, q_obj,
4419                                                 ECORE_Q_CMD_SETUP_TX_ONLY)) {
4420                                 break;
4421                         }
4422                         goto next_spqe;
4423
4424                 case EVENT_RING_OPCODE_FUNCTION_START:
4425                         PMD_DRV_LOG(DEBUG, sc, "got FUNC_START ramrod");
4426                         if (f_obj->complete_cmd(sc, f_obj, ECORE_F_CMD_START)) {
4427                                 break;
4428                         }
4429                         goto next_spqe;
4430
4431                 case EVENT_RING_OPCODE_FUNCTION_STOP:
4432                         PMD_DRV_LOG(DEBUG, sc, "got FUNC_STOP ramrod");
4433                         if (f_obj->complete_cmd(sc, f_obj, ECORE_F_CMD_STOP)) {
4434                                 break;
4435                         }
4436                         goto next_spqe;
4437                 }
4438
4439                 switch (opcode | sc->state) {
4440                 case (EVENT_RING_OPCODE_RSS_UPDATE_RULES | BNX2X_STATE_OPEN):
4441                 case (EVENT_RING_OPCODE_RSS_UPDATE_RULES | BNX2X_STATE_OPENING_WAITING_PORT):
4442                         cid =
4443                             elem->message.data.eth_event.echo & BNX2X_SWCID_MASK;
4444                         PMD_DRV_LOG(DEBUG, sc, "got RSS_UPDATE ramrod. CID %d",
4445                                     cid);
4446                         rss_raw->clear_pending(rss_raw);
4447                         break;
4448
4449                 case (EVENT_RING_OPCODE_SET_MAC | BNX2X_STATE_OPEN):
4450                 case (EVENT_RING_OPCODE_SET_MAC | BNX2X_STATE_DIAG):
4451                 case (EVENT_RING_OPCODE_SET_MAC | BNX2X_STATE_CLOSING_WAITING_HALT):
4452                 case (EVENT_RING_OPCODE_CLASSIFICATION_RULES | BNX2X_STATE_OPEN):
4453                 case (EVENT_RING_OPCODE_CLASSIFICATION_RULES | BNX2X_STATE_DIAG):
4454                 case (EVENT_RING_OPCODE_CLASSIFICATION_RULES | BNX2X_STATE_CLOSING_WAITING_HALT):
4455                         PMD_DRV_LOG(DEBUG, sc,
4456                                     "got (un)set mac ramrod");
4457                         bnx2x_handle_classification_eqe(sc, elem);
4458                         break;
4459
4460                 case (EVENT_RING_OPCODE_MULTICAST_RULES | BNX2X_STATE_OPEN):
4461                 case (EVENT_RING_OPCODE_MULTICAST_RULES | BNX2X_STATE_DIAG):
4462                 case (EVENT_RING_OPCODE_MULTICAST_RULES | BNX2X_STATE_CLOSING_WAITING_HALT):
4463                         PMD_DRV_LOG(DEBUG, sc,
4464                                     "got mcast ramrod");
4465                         bnx2x_handle_mcast_eqe(sc);
4466                         break;
4467
4468                 case (EVENT_RING_OPCODE_FILTERS_RULES | BNX2X_STATE_OPEN):
4469                 case (EVENT_RING_OPCODE_FILTERS_RULES | BNX2X_STATE_DIAG):
4470                 case (EVENT_RING_OPCODE_FILTERS_RULES | BNX2X_STATE_CLOSING_WAITING_HALT):
4471                         PMD_DRV_LOG(DEBUG, sc,
4472                                     "got rx_mode ramrod");
4473                         bnx2x_handle_rx_mode_eqe(sc);
4474                         break;
4475
4476                 default:
4477                         /* unknown event log error and continue */
4478                         PMD_DRV_LOG(INFO, sc, "Unknown EQ event %d, sc->state 0x%x",
4479                                     elem->message.opcode, sc->state);
4480                 }
4481
4482 next_spqe:
4483                 spqe_cnt++;
4484         }                       /* for */
4485
4486         mb();
4487         atomic_add_acq_long(&sc->eq_spq_left, spqe_cnt);
4488
4489         sc->eq_cons = sw_cons;
4490         sc->eq_prod = sw_prod;
4491
4492         /* make sure that above mem writes were issued towards the memory */
4493         wmb();
4494
4495         /* update producer */
4496         bnx2x_update_eq_prod(sc, sc->eq_prod);
4497 }
4498
4499 static int bnx2x_handle_sp_tq(struct bnx2x_softc *sc)
4500 {
4501         uint16_t status;
4502         int rc = 0;
4503
4504         PMD_DRV_LOG(DEBUG, sc, "---> SP TASK <---");
4505
4506         /* what work needs to be performed? */
4507         status = bnx2x_update_dsb_idx(sc);
4508
4509         PMD_DRV_LOG(DEBUG, sc, "dsb status 0x%04x", status);
4510
4511         /* HW attentions */
4512         if (status & BNX2X_DEF_SB_ATT_IDX) {
4513                 PMD_DRV_LOG(DEBUG, sc, "---> ATTN INTR <---");
4514                 bnx2x_attn_int(sc);
4515                 status &= ~BNX2X_DEF_SB_ATT_IDX;
4516                 rc = 1;
4517         }
4518
4519         /* SP events: STAT_QUERY and others */
4520         if (status & BNX2X_DEF_SB_IDX) {
4521 /* handle EQ completions */
4522                 PMD_DRV_LOG(DEBUG, sc, "---> EQ INTR <---");
4523                 bnx2x_eq_int(sc);
4524                 bnx2x_ack_sb(sc, sc->igu_dsb_id, USTORM_ID,
4525                            le16toh(sc->def_idx), IGU_INT_NOP, 1);
4526                 status &= ~BNX2X_DEF_SB_IDX;
4527         }
4528
4529         /* if status is non zero then something went wrong */
4530         if (unlikely(status)) {
4531                 PMD_DRV_LOG(INFO, sc,
4532                             "Got an unknown SP interrupt! (0x%04x)", status);
4533         }
4534
4535         /* ack status block only if something was actually handled */
4536         bnx2x_ack_sb(sc, sc->igu_dsb_id, ATTENTION_ID,
4537                    le16toh(sc->def_att_idx), IGU_INT_ENABLE, 1);
4538
4539         return rc;
4540 }
4541
4542 static void bnx2x_handle_fp_tq(struct bnx2x_fastpath *fp, int scan_fp)
4543 {
4544         struct bnx2x_softc *sc = fp->sc;
4545         uint8_t more_rx = FALSE;
4546
4547         /* Make sure FP is initialized */
4548         if (!fp->sb_running_index)
4549                 return;
4550
4551         PMD_DEBUG_PERIODIC_LOG(DEBUG, sc,
4552                                "---> FP TASK QUEUE (%d) <--", fp->index);
4553
4554         /* update the fastpath index */
4555         bnx2x_update_fp_sb_idx(fp);
4556
4557         if (scan_fp) {
4558                 if (bnx2x_has_rx_work(fp)) {
4559                         more_rx = bnx2x_rxeof(sc, fp);
4560                 }
4561
4562                 if (more_rx) {
4563                         /* still more work to do */
4564                         bnx2x_handle_fp_tq(fp, scan_fp);
4565                         return;
4566                 }
4567         }
4568
4569         bnx2x_ack_sb(sc, fp->igu_sb_id, USTORM_ID,
4570                    le16toh(fp->fp_hc_idx), IGU_INT_ENABLE, 1);
4571 }
4572
4573 /*
4574  * Legacy interrupt entry point.
4575  *
4576  * Verifies that the controller generated the interrupt and
4577  * then calls a separate routine to handle the various
4578  * interrupt causes: link, RX, and TX.
4579  */
4580 int bnx2x_intr_legacy(struct bnx2x_softc *sc, int scan_fp)
4581 {
4582         struct bnx2x_fastpath *fp;
4583         uint32_t status, mask;
4584         int i, rc = 0;
4585
4586         /*
4587          * 0 for ustorm, 1 for cstorm
4588          * the bits returned from ack_int() are 0-15
4589          * bit 0 = attention status block
4590          * bit 1 = fast path status block
4591          * a mask of 0x2 or more = tx/rx event
4592          * a mask of 1 = slow path event
4593          */
4594
4595         status = bnx2x_ack_int(sc);
4596
4597         /* the interrupt is not for us */
4598         if (unlikely(status == 0)) {
4599                 return 0;
4600         }
4601
4602         PMD_DEBUG_PERIODIC_LOG(DEBUG, sc, "Interrupt status 0x%04x", status);
4603         //bnx2x_dump_status_block(sc);
4604
4605         FOR_EACH_ETH_QUEUE(sc, i) {
4606                 fp = &sc->fp[i];
4607                 mask = (0x2 << (fp->index + CNIC_SUPPORT(sc)));
4608                 if (status & mask) {
4609                 /* acknowledge and disable further fastpath interrupts */
4610                         bnx2x_ack_sb(sc, fp->igu_sb_id, USTORM_ID,
4611                                      0, IGU_INT_DISABLE, 0);
4612                         bnx2x_handle_fp_tq(fp, scan_fp);
4613                         status &= ~mask;
4614                 }
4615         }
4616
4617         if (unlikely(status & 0x1)) {
4618                 /* acknowledge and disable further slowpath interrupts */
4619                 bnx2x_ack_sb(sc, sc->igu_dsb_id, USTORM_ID,
4620                              0, IGU_INT_DISABLE, 0);
4621                 rc = bnx2x_handle_sp_tq(sc);
4622                 status &= ~0x1;
4623         }
4624
4625         if (unlikely(status)) {
4626                 PMD_DRV_LOG(WARNING, sc,
4627                             "Unexpected fastpath status (0x%08x)!", status);
4628         }
4629
4630         return rc;
4631 }
4632
4633 static int bnx2x_init_hw_common_chip(struct bnx2x_softc *sc);
4634 static int bnx2x_init_hw_common(struct bnx2x_softc *sc);
4635 static int bnx2x_init_hw_port(struct bnx2x_softc *sc);
4636 static int bnx2x_init_hw_func(struct bnx2x_softc *sc);
4637 static void bnx2x_reset_common(struct bnx2x_softc *sc);
4638 static void bnx2x_reset_port(struct bnx2x_softc *sc);
4639 static void bnx2x_reset_func(struct bnx2x_softc *sc);
4640 static int bnx2x_init_firmware(struct bnx2x_softc *sc);
4641 static void bnx2x_release_firmware(struct bnx2x_softc *sc);
4642
4643 static struct
4644 ecore_func_sp_drv_ops bnx2x_func_sp_drv = {
4645         .init_hw_cmn_chip = bnx2x_init_hw_common_chip,
4646         .init_hw_cmn = bnx2x_init_hw_common,
4647         .init_hw_port = bnx2x_init_hw_port,
4648         .init_hw_func = bnx2x_init_hw_func,
4649
4650         .reset_hw_cmn = bnx2x_reset_common,
4651         .reset_hw_port = bnx2x_reset_port,
4652         .reset_hw_func = bnx2x_reset_func,
4653
4654         .init_fw = bnx2x_init_firmware,
4655         .release_fw = bnx2x_release_firmware,
4656 };
4657
4658 static void bnx2x_init_func_obj(struct bnx2x_softc *sc)
4659 {
4660         sc->dmae_ready = 0;
4661
4662         PMD_INIT_FUNC_TRACE(sc);
4663
4664         ecore_init_func_obj(sc,
4665                             &sc->func_obj,
4666                             BNX2X_SP(sc, func_rdata),
4667                             (rte_iova_t)BNX2X_SP_MAPPING(sc, func_rdata),
4668                             BNX2X_SP(sc, func_afex_rdata),
4669                             (rte_iova_t)BNX2X_SP_MAPPING(sc, func_afex_rdata),
4670                             &bnx2x_func_sp_drv);
4671 }
4672
4673 static int bnx2x_init_hw(struct bnx2x_softc *sc, uint32_t load_code)
4674 {
4675         struct ecore_func_state_params func_params = { NULL };
4676         int rc;
4677
4678         PMD_INIT_FUNC_TRACE(sc);
4679
4680         /* prepare the parameters for function state transitions */
4681         bnx2x_set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags);
4682
4683         func_params.f_obj = &sc->func_obj;
4684         func_params.cmd = ECORE_F_CMD_HW_INIT;
4685
4686         func_params.params.hw_init.load_phase = load_code;
4687
4688         /*
4689          * Via a plethora of function pointers, we will eventually reach
4690          * bnx2x_init_hw_common(), bnx2x_init_hw_port(), or bnx2x_init_hw_func().
4691          */
4692         rc = ecore_func_state_change(sc, &func_params);
4693
4694         return rc;
4695 }
4696
4697 static void
4698 bnx2x_fill(struct bnx2x_softc *sc, uint32_t addr, int fill, uint32_t len)
4699 {
4700         uint32_t i;
4701
4702         if (!(len % 4) && !(addr % 4)) {
4703                 for (i = 0; i < len; i += 4) {
4704                         REG_WR(sc, (addr + i), fill);
4705                 }
4706         } else {
4707                 for (i = 0; i < len; i++) {
4708                         REG_WR8(sc, (addr + i), fill);
4709                 }
4710         }
4711 }
4712
4713 /* writes FP SP data to FW - data_size in dwords */
4714 static void
4715 bnx2x_wr_fp_sb_data(struct bnx2x_softc *sc, int fw_sb_id, uint32_t * sb_data_p,
4716                   uint32_t data_size)
4717 {
4718         uint32_t index;
4719
4720         for (index = 0; index < data_size; index++) {
4721                 REG_WR(sc,
4722                        (BAR_CSTRORM_INTMEM +
4723                         CSTORM_STATUS_BLOCK_DATA_OFFSET(fw_sb_id) +
4724                         (sizeof(uint32_t) * index)), *(sb_data_p + index));
4725         }
4726 }
4727
4728 static void bnx2x_zero_fp_sb(struct bnx2x_softc *sc, int fw_sb_id)
4729 {
4730         struct hc_status_block_data_e2 sb_data_e2;
4731         struct hc_status_block_data_e1x sb_data_e1x;
4732         uint32_t *sb_data_p;
4733         uint32_t data_size = 0;
4734
4735         if (!CHIP_IS_E1x(sc)) {
4736                 memset(&sb_data_e2, 0, sizeof(struct hc_status_block_data_e2));
4737                 sb_data_e2.common.state = SB_DISABLED;
4738                 sb_data_e2.common.p_func.vf_valid = FALSE;
4739                 sb_data_p = (uint32_t *) & sb_data_e2;
4740                 data_size = (sizeof(struct hc_status_block_data_e2) /
4741                              sizeof(uint32_t));
4742         } else {
4743                 memset(&sb_data_e1x, 0,
4744                        sizeof(struct hc_status_block_data_e1x));
4745                 sb_data_e1x.common.state = SB_DISABLED;
4746                 sb_data_e1x.common.p_func.vf_valid = FALSE;
4747                 sb_data_p = (uint32_t *) & sb_data_e1x;
4748                 data_size = (sizeof(struct hc_status_block_data_e1x) /
4749                              sizeof(uint32_t));
4750         }
4751
4752         bnx2x_wr_fp_sb_data(sc, fw_sb_id, sb_data_p, data_size);
4753
4754         bnx2x_fill(sc,
4755                  (BAR_CSTRORM_INTMEM + CSTORM_STATUS_BLOCK_OFFSET(fw_sb_id)), 0,
4756                  CSTORM_STATUS_BLOCK_SIZE);
4757         bnx2x_fill(sc, (BAR_CSTRORM_INTMEM + CSTORM_SYNC_BLOCK_OFFSET(fw_sb_id)),
4758                  0, CSTORM_SYNC_BLOCK_SIZE);
4759 }
4760
4761 static void
4762 bnx2x_wr_sp_sb_data(struct bnx2x_softc *sc,
4763                   struct hc_sp_status_block_data *sp_sb_data)
4764 {
4765         uint32_t i;
4766
4767         for (i = 0;
4768              i < (sizeof(struct hc_sp_status_block_data) / sizeof(uint32_t));
4769              i++) {
4770                 REG_WR(sc,
4771                        (BAR_CSTRORM_INTMEM +
4772                         CSTORM_SP_STATUS_BLOCK_DATA_OFFSET(SC_FUNC(sc)) +
4773                         (i * sizeof(uint32_t))),
4774                        *((uint32_t *) sp_sb_data + i));
4775         }
4776 }
4777
4778 static void bnx2x_zero_sp_sb(struct bnx2x_softc *sc)
4779 {
4780         struct hc_sp_status_block_data sp_sb_data;
4781
4782         memset(&sp_sb_data, 0, sizeof(struct hc_sp_status_block_data));
4783
4784         sp_sb_data.state = SB_DISABLED;
4785         sp_sb_data.p_func.vf_valid = FALSE;
4786
4787         bnx2x_wr_sp_sb_data(sc, &sp_sb_data);
4788
4789         bnx2x_fill(sc,
4790                  (BAR_CSTRORM_INTMEM +
4791                   CSTORM_SP_STATUS_BLOCK_OFFSET(SC_FUNC(sc))),
4792                  0, CSTORM_SP_STATUS_BLOCK_SIZE);
4793         bnx2x_fill(sc,
4794                  (BAR_CSTRORM_INTMEM +
4795                   CSTORM_SP_SYNC_BLOCK_OFFSET(SC_FUNC(sc))),
4796                  0, CSTORM_SP_SYNC_BLOCK_SIZE);
4797 }
4798
4799 static void
4800 bnx2x_setup_ndsb_state_machine(struct hc_status_block_sm *hc_sm, int igu_sb_id,
4801                              int igu_seg_id)
4802 {
4803         hc_sm->igu_sb_id = igu_sb_id;
4804         hc_sm->igu_seg_id = igu_seg_id;
4805         hc_sm->timer_value = 0xFF;
4806         hc_sm->time_to_expire = 0xFFFFFFFF;
4807 }
4808
4809 static void bnx2x_map_sb_state_machines(struct hc_index_data *index_data)
4810 {
4811         /* zero out state machine indices */
4812
4813         /* rx indices */
4814         index_data[HC_INDEX_ETH_RX_CQ_CONS].flags &= ~HC_INDEX_DATA_SM_ID;
4815
4816         /* tx indices */
4817         index_data[HC_INDEX_OOO_TX_CQ_CONS].flags &= ~HC_INDEX_DATA_SM_ID;
4818         index_data[HC_INDEX_ETH_TX_CQ_CONS_COS0].flags &= ~HC_INDEX_DATA_SM_ID;
4819         index_data[HC_INDEX_ETH_TX_CQ_CONS_COS1].flags &= ~HC_INDEX_DATA_SM_ID;
4820         index_data[HC_INDEX_ETH_TX_CQ_CONS_COS2].flags &= ~HC_INDEX_DATA_SM_ID;
4821
4822         /* map indices */
4823
4824         /* rx indices */
4825         index_data[HC_INDEX_ETH_RX_CQ_CONS].flags |=
4826             (SM_RX_ID << HC_INDEX_DATA_SM_ID_SHIFT);
4827
4828         /* tx indices */
4829         index_data[HC_INDEX_OOO_TX_CQ_CONS].flags |=
4830             (SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT);
4831         index_data[HC_INDEX_ETH_TX_CQ_CONS_COS0].flags |=
4832             (SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT);
4833         index_data[HC_INDEX_ETH_TX_CQ_CONS_COS1].flags |=
4834             (SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT);
4835         index_data[HC_INDEX_ETH_TX_CQ_CONS_COS2].flags |=
4836             (SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT);
4837 }
4838
4839 static void
4840 bnx2x_init_sb(struct bnx2x_softc *sc, rte_iova_t busaddr, int vfid,
4841             uint8_t vf_valid, int fw_sb_id, int igu_sb_id)
4842 {
4843         struct hc_status_block_data_e2 sb_data_e2;
4844         struct hc_status_block_data_e1x sb_data_e1x;
4845         struct hc_status_block_sm *hc_sm_p;
4846         uint32_t *sb_data_p;
4847         int igu_seg_id;
4848         int data_size;
4849
4850         if (CHIP_INT_MODE_IS_BC(sc)) {
4851                 igu_seg_id = HC_SEG_ACCESS_NORM;
4852         } else {
4853                 igu_seg_id = IGU_SEG_ACCESS_NORM;
4854         }
4855
4856         bnx2x_zero_fp_sb(sc, fw_sb_id);
4857
4858         if (!CHIP_IS_E1x(sc)) {
4859                 memset(&sb_data_e2, 0, sizeof(struct hc_status_block_data_e2));
4860                 sb_data_e2.common.state = SB_ENABLED;
4861                 sb_data_e2.common.p_func.pf_id = SC_FUNC(sc);
4862                 sb_data_e2.common.p_func.vf_id = vfid;
4863                 sb_data_e2.common.p_func.vf_valid = vf_valid;
4864                 sb_data_e2.common.p_func.vnic_id = SC_VN(sc);
4865                 sb_data_e2.common.same_igu_sb_1b = TRUE;
4866                 sb_data_e2.common.host_sb_addr.hi = U64_HI(busaddr);
4867                 sb_data_e2.common.host_sb_addr.lo = U64_LO(busaddr);
4868                 hc_sm_p = sb_data_e2.common.state_machine;
4869                 sb_data_p = (uint32_t *) & sb_data_e2;
4870                 data_size = (sizeof(struct hc_status_block_data_e2) /
4871                              sizeof(uint32_t));
4872                 bnx2x_map_sb_state_machines(sb_data_e2.index_data);
4873         } else {
4874                 memset(&sb_data_e1x, 0,
4875                        sizeof(struct hc_status_block_data_e1x));
4876                 sb_data_e1x.common.state = SB_ENABLED;
4877                 sb_data_e1x.common.p_func.pf_id = SC_FUNC(sc);
4878                 sb_data_e1x.common.p_func.vf_id = 0xff;
4879                 sb_data_e1x.common.p_func.vf_valid = FALSE;
4880                 sb_data_e1x.common.p_func.vnic_id = SC_VN(sc);
4881                 sb_data_e1x.common.same_igu_sb_1b = TRUE;
4882                 sb_data_e1x.common.host_sb_addr.hi = U64_HI(busaddr);
4883                 sb_data_e1x.common.host_sb_addr.lo = U64_LO(busaddr);
4884                 hc_sm_p = sb_data_e1x.common.state_machine;
4885                 sb_data_p = (uint32_t *) & sb_data_e1x;
4886                 data_size = (sizeof(struct hc_status_block_data_e1x) /
4887                              sizeof(uint32_t));
4888                 bnx2x_map_sb_state_machines(sb_data_e1x.index_data);
4889         }
4890
4891         bnx2x_setup_ndsb_state_machine(&hc_sm_p[SM_RX_ID], igu_sb_id, igu_seg_id);
4892         bnx2x_setup_ndsb_state_machine(&hc_sm_p[SM_TX_ID], igu_sb_id, igu_seg_id);
4893
4894         /* write indices to HW - PCI guarantees endianity of regpairs */
4895         bnx2x_wr_fp_sb_data(sc, fw_sb_id, sb_data_p, data_size);
4896 }
4897
4898 static uint8_t bnx2x_fp_qzone_id(struct bnx2x_fastpath *fp)
4899 {
4900         if (CHIP_IS_E1x(fp->sc)) {
4901                 return fp->cl_id + SC_PORT(fp->sc) * ETH_MAX_RX_CLIENTS_E1H;
4902         } else {
4903                 return fp->cl_id;
4904         }
4905 }
4906
4907 static uint32_t
4908 bnx2x_rx_ustorm_prods_offset(struct bnx2x_softc *sc, struct bnx2x_fastpath *fp)
4909 {
4910         uint32_t offset = BAR_USTRORM_INTMEM;
4911
4912         if (IS_VF(sc)) {
4913                 return PXP_VF_ADDR_USDM_QUEUES_START +
4914                         (sc->acquire_resp.resc.hw_qid[fp->index] *
4915                          sizeof(struct ustorm_queue_zone_data));
4916         } else if (!CHIP_IS_E1x(sc)) {
4917                 offset += USTORM_RX_PRODS_E2_OFFSET(fp->cl_qzone_id);
4918         } else {
4919                 offset += USTORM_RX_PRODS_E1X_OFFSET(SC_PORT(sc), fp->cl_id);
4920         }
4921
4922         return offset;
4923 }
4924
4925 static void bnx2x_init_eth_fp(struct bnx2x_softc *sc, int idx)
4926 {
4927         struct bnx2x_fastpath *fp = &sc->fp[idx];
4928         uint32_t cids[ECORE_MULTI_TX_COS] = { 0 };
4929         unsigned long q_type = 0;
4930         int cos;
4931
4932         fp->sc = sc;
4933         fp->index = idx;
4934
4935         fp->igu_sb_id = (sc->igu_base_sb + idx + CNIC_SUPPORT(sc));
4936         fp->fw_sb_id = (sc->base_fw_ndsb + idx + CNIC_SUPPORT(sc));
4937
4938         if (CHIP_IS_E1x(sc))
4939                 fp->cl_id = SC_L_ID(sc) + idx;
4940         else
4941 /* want client ID same as IGU SB ID for non-E1 */
4942                 fp->cl_id = fp->igu_sb_id;
4943         fp->cl_qzone_id = bnx2x_fp_qzone_id(fp);
4944
4945         /* setup sb indices */
4946         if (!CHIP_IS_E1x(sc)) {
4947                 fp->sb_index_values = fp->status_block.e2_sb->sb.index_values;
4948                 fp->sb_running_index = fp->status_block.e2_sb->sb.running_index;
4949         } else {
4950                 fp->sb_index_values = fp->status_block.e1x_sb->sb.index_values;
4951                 fp->sb_running_index =
4952                     fp->status_block.e1x_sb->sb.running_index;
4953         }
4954
4955         /* init shortcut */
4956         fp->ustorm_rx_prods_offset = bnx2x_rx_ustorm_prods_offset(sc, fp);
4957
4958         fp->rx_cq_cons_sb = &fp->sb_index_values[HC_INDEX_ETH_RX_CQ_CONS];
4959
4960         for (cos = 0; cos < sc->max_cos; cos++) {
4961                 cids[cos] = idx;
4962         }
4963         fp->tx_cons_sb = &fp->sb_index_values[HC_INDEX_ETH_TX_CQ_CONS_COS0];
4964
4965         /* nothing more for a VF to do */
4966         if (IS_VF(sc)) {
4967                 return;
4968         }
4969
4970         bnx2x_init_sb(sc, fp->sb_dma.paddr, BNX2X_VF_ID_INVALID, FALSE,
4971                     fp->fw_sb_id, fp->igu_sb_id);
4972
4973         bnx2x_update_fp_sb_idx(fp);
4974
4975         /* Configure Queue State object */
4976         bnx2x_set_bit(ECORE_Q_TYPE_HAS_RX, &q_type);
4977         bnx2x_set_bit(ECORE_Q_TYPE_HAS_TX, &q_type);
4978
4979         ecore_init_queue_obj(sc,
4980                              &sc->sp_objs[idx].q_obj,
4981                              fp->cl_id,
4982                              cids,
4983                              sc->max_cos,
4984                              SC_FUNC(sc),
4985                              BNX2X_SP(sc, q_rdata),
4986                              (rte_iova_t)BNX2X_SP_MAPPING(sc, q_rdata),
4987                              q_type);
4988
4989         /* configure classification DBs */
4990         ecore_init_mac_obj(sc,
4991                            &sc->sp_objs[idx].mac_obj,
4992                            fp->cl_id,
4993                            idx,
4994                            SC_FUNC(sc),
4995                            BNX2X_SP(sc, mac_rdata),
4996                            (rte_iova_t)BNX2X_SP_MAPPING(sc, mac_rdata),
4997                            ECORE_FILTER_MAC_PENDING, &sc->sp_state,
4998                            ECORE_OBJ_TYPE_RX_TX, &sc->macs_pool);
4999 }
5000
5001 static void
5002 bnx2x_update_rx_prod(struct bnx2x_softc *sc, struct bnx2x_fastpath *fp,
5003                    uint16_t rx_bd_prod, uint16_t rx_cq_prod)
5004 {
5005         union ustorm_eth_rx_producers rx_prods;
5006         uint32_t i;
5007
5008         /* update producers */
5009         rx_prods.prod.bd_prod = rx_bd_prod;
5010         rx_prods.prod.cqe_prod = rx_cq_prod;
5011         rx_prods.prod.reserved = 0;
5012
5013         /*
5014          * Make sure that the BD and SGE data is updated before updating the
5015          * producers since FW might read the BD/SGE right after the producer
5016          * is updated.
5017          * This is only applicable for weak-ordered memory model archs such
5018          * as IA-64. The following barrier is also mandatory since FW will
5019          * assumes BDs must have buffers.
5020          */
5021         wmb();
5022
5023         for (i = 0; i < (sizeof(rx_prods) / 4); i++) {
5024                 REG_WR(sc,
5025                        (fp->ustorm_rx_prods_offset + (i * 4)),
5026                        rx_prods.raw_data[i]);
5027         }
5028
5029         wmb();                  /* keep prod updates ordered */
5030 }
5031
5032 static void bnx2x_init_rx_rings(struct bnx2x_softc *sc)
5033 {
5034         struct bnx2x_fastpath *fp;
5035         int i;
5036         struct bnx2x_rx_queue *rxq;
5037
5038         for (i = 0; i < sc->num_queues; i++) {
5039                 fp = &sc->fp[i];
5040                 rxq = sc->rx_queues[fp->index];
5041                 if (!rxq) {
5042                         PMD_RX_LOG(ERR, "RX queue is NULL");
5043                         return;
5044                 }
5045
5046                 rxq->rx_bd_head = 0;
5047                 rxq->rx_bd_tail = rxq->nb_rx_desc;
5048                 rxq->rx_cq_head = 0;
5049                 rxq->rx_cq_tail = TOTAL_RCQ_ENTRIES(rxq);
5050                 *fp->rx_cq_cons_sb = 0;
5051
5052                 /*
5053                  * Activate the BD ring...
5054                  * Warning, this will generate an interrupt (to the TSTORM)
5055                  * so this can only be done after the chip is initialized
5056                  */
5057                 bnx2x_update_rx_prod(sc, fp, rxq->rx_bd_tail, rxq->rx_cq_tail);
5058
5059                 if (i != 0) {
5060                         continue;
5061                 }
5062         }
5063 }
5064
5065 static void bnx2x_init_tx_ring_one(struct bnx2x_fastpath *fp)
5066 {
5067         struct bnx2x_tx_queue *txq = fp->sc->tx_queues[fp->index];
5068
5069         fp->tx_db.data.header.header = 1 << DOORBELL_HDR_DB_TYPE_SHIFT;
5070         fp->tx_db.data.zero_fill1 = 0;
5071         fp->tx_db.data.prod = 0;
5072
5073         if (!txq) {
5074                 PMD_TX_LOG(ERR, "ERROR: TX queue is NULL");
5075                 return;
5076         }
5077
5078         txq->tx_pkt_tail = 0;
5079         txq->tx_pkt_head = 0;
5080         txq->tx_bd_tail = 0;
5081         txq->tx_bd_head = 0;
5082 }
5083
5084 static void bnx2x_init_tx_rings(struct bnx2x_softc *sc)
5085 {
5086         int i;
5087
5088         for (i = 0; i < sc->num_queues; i++) {
5089                 bnx2x_init_tx_ring_one(&sc->fp[i]);
5090         }
5091 }
5092
5093 static void bnx2x_init_def_sb(struct bnx2x_softc *sc)
5094 {
5095         struct host_sp_status_block *def_sb = sc->def_sb;
5096         rte_iova_t mapping = sc->def_sb_dma.paddr;
5097         int igu_sp_sb_index;
5098         int igu_seg_id;
5099         int port = SC_PORT(sc);
5100         int func = SC_FUNC(sc);
5101         int reg_offset, reg_offset_en5;
5102         uint64_t section;
5103         int index, sindex;
5104         struct hc_sp_status_block_data sp_sb_data;
5105
5106         memset(&sp_sb_data, 0, sizeof(struct hc_sp_status_block_data));
5107
5108         if (CHIP_INT_MODE_IS_BC(sc)) {
5109                 igu_sp_sb_index = DEF_SB_IGU_ID;
5110                 igu_seg_id = HC_SEG_ACCESS_DEF;
5111         } else {
5112                 igu_sp_sb_index = sc->igu_dsb_id;
5113                 igu_seg_id = IGU_SEG_ACCESS_DEF;
5114         }
5115
5116         /* attentions */
5117         section = ((uint64_t) mapping +
5118                    offsetof(struct host_sp_status_block, atten_status_block));
5119         def_sb->atten_status_block.status_block_id = igu_sp_sb_index;
5120         sc->attn_state = 0;
5121
5122         reg_offset = (port) ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 :
5123             MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0;
5124
5125         reg_offset_en5 = (port) ? MISC_REG_AEU_ENABLE5_FUNC_1_OUT_0 :
5126             MISC_REG_AEU_ENABLE5_FUNC_0_OUT_0;
5127
5128         for (index = 0; index < MAX_DYNAMIC_ATTN_GRPS; index++) {
5129 /* take care of sig[0]..sig[4] */
5130                 for (sindex = 0; sindex < 4; sindex++) {
5131                         sc->attn_group[index].sig[sindex] =
5132                             REG_RD(sc,
5133                                    (reg_offset + (sindex * 0x4) +
5134                                     (0x10 * index)));
5135                 }
5136
5137                 if (!CHIP_IS_E1x(sc)) {
5138                         /*
5139                          * enable5 is separate from the rest of the registers,
5140                          * and the address skip is 4 and not 16 between the
5141                          * different groups
5142                          */
5143                         sc->attn_group[index].sig[4] =
5144                             REG_RD(sc, (reg_offset_en5 + (0x4 * index)));
5145                 } else {
5146                         sc->attn_group[index].sig[4] = 0;
5147                 }
5148         }
5149
5150         if (sc->devinfo.int_block == INT_BLOCK_HC) {
5151                 reg_offset =
5152                     port ? HC_REG_ATTN_MSG1_ADDR_L : HC_REG_ATTN_MSG0_ADDR_L;
5153                 REG_WR(sc, reg_offset, U64_LO(section));
5154                 REG_WR(sc, (reg_offset + 4), U64_HI(section));
5155         } else if (!CHIP_IS_E1x(sc)) {
5156                 REG_WR(sc, IGU_REG_ATTN_MSG_ADDR_L, U64_LO(section));
5157                 REG_WR(sc, IGU_REG_ATTN_MSG_ADDR_H, U64_HI(section));
5158         }
5159
5160         section = ((uint64_t) mapping +
5161                    offsetof(struct host_sp_status_block, sp_sb));
5162
5163         bnx2x_zero_sp_sb(sc);
5164
5165         /* PCI guarantees endianity of regpair */
5166         sp_sb_data.state = SB_ENABLED;
5167         sp_sb_data.host_sb_addr.lo = U64_LO(section);
5168         sp_sb_data.host_sb_addr.hi = U64_HI(section);
5169         sp_sb_data.igu_sb_id = igu_sp_sb_index;
5170         sp_sb_data.igu_seg_id = igu_seg_id;
5171         sp_sb_data.p_func.pf_id = func;
5172         sp_sb_data.p_func.vnic_id = SC_VN(sc);
5173         sp_sb_data.p_func.vf_id = 0xff;
5174
5175         bnx2x_wr_sp_sb_data(sc, &sp_sb_data);
5176
5177         bnx2x_ack_sb(sc, sc->igu_dsb_id, USTORM_ID, 0, IGU_INT_ENABLE, 0);
5178 }
5179
5180 static void bnx2x_init_sp_ring(struct bnx2x_softc *sc)
5181 {
5182         atomic_store_rel_long(&sc->cq_spq_left, MAX_SPQ_PENDING);
5183         sc->spq_prod_idx = 0;
5184         sc->dsb_sp_prod =
5185             &sc->def_sb->sp_sb.index_values[HC_SP_INDEX_ETH_DEF_CONS];
5186         sc->spq_prod_bd = sc->spq;
5187         sc->spq_last_bd = (sc->spq_prod_bd + MAX_SP_DESC_CNT);
5188 }
5189
5190 static void bnx2x_init_eq_ring(struct bnx2x_softc *sc)
5191 {
5192         union event_ring_elem *elem;
5193         int i;
5194
5195         for (i = 1; i <= NUM_EQ_PAGES; i++) {
5196                 elem = &sc->eq[EQ_DESC_CNT_PAGE * i - 1];
5197
5198                 elem->next_page.addr.hi = htole32(U64_HI(sc->eq_dma.paddr +
5199                                                          BNX2X_PAGE_SIZE *
5200                                                          (i % NUM_EQ_PAGES)));
5201                 elem->next_page.addr.lo = htole32(U64_LO(sc->eq_dma.paddr +
5202                                                          BNX2X_PAGE_SIZE *
5203                                                          (i % NUM_EQ_PAGES)));
5204         }
5205
5206         sc->eq_cons = 0;
5207         sc->eq_prod = NUM_EQ_DESC;
5208         sc->eq_cons_sb = &sc->def_sb->sp_sb.index_values[HC_SP_INDEX_EQ_CONS];
5209
5210         atomic_store_rel_long(&sc->eq_spq_left,
5211                               (min((MAX_SP_DESC_CNT - MAX_SPQ_PENDING),
5212                                    NUM_EQ_DESC) - 1));
5213 }
5214
5215 static void bnx2x_init_internal_common(struct bnx2x_softc *sc)
5216 {
5217         int i;
5218
5219         if (IS_MF_SI(sc)) {
5220 /*
5221  * In switch independent mode, the TSTORM needs to accept
5222  * packets that failed classification, since approximate match
5223  * mac addresses aren't written to NIG LLH.
5224  */
5225                 REG_WR8(sc,
5226                         (BAR_TSTRORM_INTMEM +
5227                          TSTORM_ACCEPT_CLASSIFY_FAILED_OFFSET), 2);
5228         } else
5229                 REG_WR8(sc,
5230                         (BAR_TSTRORM_INTMEM +
5231                          TSTORM_ACCEPT_CLASSIFY_FAILED_OFFSET), 0);
5232
5233         /*
5234          * Zero this manually as its initialization is currently missing
5235          * in the initTool.
5236          */
5237         for (i = 0; i < (USTORM_AGG_DATA_SIZE >> 2); i++) {
5238                 REG_WR(sc,
5239                        (BAR_USTRORM_INTMEM + USTORM_AGG_DATA_OFFSET + (i * 4)),
5240                        0);
5241         }
5242
5243         if (!CHIP_IS_E1x(sc)) {
5244                 REG_WR8(sc, (BAR_CSTRORM_INTMEM + CSTORM_IGU_MODE_OFFSET),
5245                         CHIP_INT_MODE_IS_BC(sc) ? HC_IGU_BC_MODE :
5246                         HC_IGU_NBC_MODE);
5247         }
5248 }
5249
5250 static void bnx2x_init_internal(struct bnx2x_softc *sc, uint32_t load_code)
5251 {
5252         switch (load_code) {
5253         case FW_MSG_CODE_DRV_LOAD_COMMON:
5254         case FW_MSG_CODE_DRV_LOAD_COMMON_CHIP:
5255                 bnx2x_init_internal_common(sc);
5256                 /* no break */
5257
5258         case FW_MSG_CODE_DRV_LOAD_PORT:
5259                 /* nothing to do */
5260                 /* no break */
5261
5262         case FW_MSG_CODE_DRV_LOAD_FUNCTION:
5263                 /* internal memory per function is initialized inside bnx2x_pf_init */
5264                 break;
5265
5266         default:
5267                 PMD_DRV_LOG(NOTICE, sc, "Unknown load_code (0x%x) from MCP",
5268                             load_code);
5269                 break;
5270         }
5271 }
5272
5273 static void
5274 storm_memset_func_cfg(struct bnx2x_softc *sc,
5275                       struct tstorm_eth_function_common_config *tcfg,
5276                       uint16_t abs_fid)
5277 {
5278         uint32_t addr;
5279         size_t size;
5280
5281         addr = (BAR_TSTRORM_INTMEM +
5282                 TSTORM_FUNCTION_COMMON_CONFIG_OFFSET(abs_fid));
5283         size = sizeof(struct tstorm_eth_function_common_config);
5284         ecore_storm_memset_struct(sc, addr, size, (uint32_t *) tcfg);
5285 }
5286
5287 static void bnx2x_func_init(struct bnx2x_softc *sc, struct bnx2x_func_init_params *p)
5288 {
5289         struct tstorm_eth_function_common_config tcfg = { 0 };
5290
5291         if (CHIP_IS_E1x(sc)) {
5292                 storm_memset_func_cfg(sc, &tcfg, p->func_id);
5293         }
5294
5295         /* Enable the function in the FW */
5296         storm_memset_vf_to_pf(sc, p->func_id, p->pf_id);
5297         storm_memset_func_en(sc, p->func_id, 1);
5298
5299         /* spq */
5300         if (p->func_flgs & FUNC_FLG_SPQ) {
5301                 storm_memset_spq_addr(sc, p->spq_map, p->func_id);
5302                 REG_WR(sc,
5303                        (XSEM_REG_FAST_MEMORY +
5304                         XSTORM_SPQ_PROD_OFFSET(p->func_id)), p->spq_prod);
5305         }
5306 }
5307
5308 /*
5309  * Calculates the sum of vn_min_rates.
5310  * It's needed for further normalizing of the min_rates.
5311  * Returns:
5312  *   sum of vn_min_rates.
5313  *     or
5314  *   0 - if all the min_rates are 0.
5315  * In the later case fainess algorithm should be deactivated.
5316  * If all min rates are not zero then those that are zeroes will be set to 1.
5317  */
5318 static void bnx2x_calc_vn_min(struct bnx2x_softc *sc, struct cmng_init_input *input)
5319 {
5320         uint32_t vn_cfg;
5321         uint32_t vn_min_rate;
5322         int all_zero = 1;
5323         int vn;
5324
5325         for (vn = VN_0; vn < SC_MAX_VN_NUM(sc); vn++) {
5326                 vn_cfg = sc->devinfo.mf_info.mf_config[vn];
5327                 vn_min_rate = (((vn_cfg & FUNC_MF_CFG_MIN_BW_MASK) >>
5328                                 FUNC_MF_CFG_MIN_BW_SHIFT) * 100);
5329
5330                 if (vn_cfg & FUNC_MF_CFG_FUNC_HIDE) {
5331                         /* skip hidden VNs */
5332                         vn_min_rate = 0;
5333                 } else if (!vn_min_rate) {
5334                         /* If min rate is zero - set it to 100 */
5335                         vn_min_rate = DEF_MIN_RATE;
5336                 } else {
5337                         all_zero = 0;
5338                 }
5339
5340                 input->vnic_min_rate[vn] = vn_min_rate;
5341         }
5342
5343         /* if ETS or all min rates are zeros - disable fairness */
5344         if (all_zero) {
5345                 input->flags.cmng_enables &= ~CMNG_FLAGS_PER_PORT_FAIRNESS_VN;
5346         } else {
5347                 input->flags.cmng_enables |= CMNG_FLAGS_PER_PORT_FAIRNESS_VN;
5348         }
5349 }
5350
5351 static uint16_t
5352 bnx2x_extract_max_cfg(__rte_unused struct bnx2x_softc *sc, uint32_t mf_cfg)
5353 {
5354         uint16_t max_cfg = ((mf_cfg & FUNC_MF_CFG_MAX_BW_MASK) >>
5355                             FUNC_MF_CFG_MAX_BW_SHIFT);
5356
5357         if (!max_cfg) {
5358                 PMD_DRV_LOG(DEBUG, sc,
5359                             "Max BW configured to 0 - using 100 instead");
5360                 max_cfg = 100;
5361         }
5362
5363         return max_cfg;
5364 }
5365
5366 static void
5367 bnx2x_calc_vn_max(struct bnx2x_softc *sc, int vn, struct cmng_init_input *input)
5368 {
5369         uint16_t vn_max_rate;
5370         uint32_t vn_cfg = sc->devinfo.mf_info.mf_config[vn];
5371         uint32_t max_cfg;
5372
5373         if (vn_cfg & FUNC_MF_CFG_FUNC_HIDE) {
5374                 vn_max_rate = 0;
5375         } else {
5376                 max_cfg = bnx2x_extract_max_cfg(sc, vn_cfg);
5377
5378                 if (IS_MF_SI(sc)) {
5379                         /* max_cfg in percents of linkspeed */
5380                         vn_max_rate =
5381                             ((sc->link_vars.line_speed * max_cfg) / 100);
5382                 } else {        /* SD modes */
5383                         /* max_cfg is absolute in 100Mb units */
5384                         vn_max_rate = (max_cfg * 100);
5385                 }
5386         }
5387
5388         input->vnic_max_rate[vn] = vn_max_rate;
5389 }
5390
5391 static void
5392 bnx2x_cmng_fns_init(struct bnx2x_softc *sc, uint8_t read_cfg, uint8_t cmng_type)
5393 {
5394         struct cmng_init_input input;
5395         int vn;
5396
5397         memset(&input, 0, sizeof(struct cmng_init_input));
5398
5399         input.port_rate = sc->link_vars.line_speed;
5400
5401         if (cmng_type == CMNG_FNS_MINMAX) {
5402 /* read mf conf from shmem */
5403                 if (read_cfg) {
5404                         bnx2x_read_mf_cfg(sc);
5405                 }
5406
5407 /* get VN min rate and enable fairness if not 0 */
5408                 bnx2x_calc_vn_min(sc, &input);
5409
5410 /* get VN max rate */
5411                 if (sc->port.pmf) {
5412                         for (vn = VN_0; vn < SC_MAX_VN_NUM(sc); vn++) {
5413                                 bnx2x_calc_vn_max(sc, vn, &input);
5414                         }
5415                 }
5416
5417 /* always enable rate shaping and fairness */
5418                 input.flags.cmng_enables |= CMNG_FLAGS_PER_PORT_RATE_SHAPING_VN;
5419
5420                 ecore_init_cmng(&input, &sc->cmng);
5421                 return;
5422         }
5423 }
5424
5425 static int bnx2x_get_cmng_fns_mode(struct bnx2x_softc *sc)
5426 {
5427         if (CHIP_REV_IS_SLOW(sc)) {
5428                 return CMNG_FNS_NONE;
5429         }
5430
5431         if (IS_MF(sc)) {
5432                 return CMNG_FNS_MINMAX;
5433         }
5434
5435         return CMNG_FNS_NONE;
5436 }
5437
5438 static void
5439 storm_memset_cmng(struct bnx2x_softc *sc, struct cmng_init *cmng, uint8_t port)
5440 {
5441         int vn;
5442         int func;
5443         uint32_t addr;
5444         size_t size;
5445
5446         addr = (BAR_XSTRORM_INTMEM + XSTORM_CMNG_PER_PORT_VARS_OFFSET(port));
5447         size = sizeof(struct cmng_struct_per_port);
5448         ecore_storm_memset_struct(sc, addr, size, (uint32_t *) & cmng->port);
5449
5450         for (vn = VN_0; vn < SC_MAX_VN_NUM(sc); vn++) {
5451                 func = func_by_vn(sc, vn);
5452
5453                 addr = (BAR_XSTRORM_INTMEM +
5454                         XSTORM_RATE_SHAPING_PER_VN_VARS_OFFSET(func));
5455                 size = sizeof(struct rate_shaping_vars_per_vn);
5456                 ecore_storm_memset_struct(sc, addr, size,
5457                                           (uint32_t *) & cmng->
5458                                           vnic.vnic_max_rate[vn]);
5459
5460                 addr = (BAR_XSTRORM_INTMEM +
5461                         XSTORM_FAIRNESS_PER_VN_VARS_OFFSET(func));
5462                 size = sizeof(struct fairness_vars_per_vn);
5463                 ecore_storm_memset_struct(sc, addr, size,
5464                                           (uint32_t *) & cmng->
5465                                           vnic.vnic_min_rate[vn]);
5466         }
5467 }
5468
5469 static void bnx2x_pf_init(struct bnx2x_softc *sc)
5470 {
5471         struct bnx2x_func_init_params func_init;
5472         struct event_ring_data eq_data;
5473         uint16_t flags;
5474
5475         memset(&eq_data, 0, sizeof(struct event_ring_data));
5476         memset(&func_init, 0, sizeof(struct bnx2x_func_init_params));
5477
5478         if (!CHIP_IS_E1x(sc)) {
5479 /* reset IGU PF statistics: MSIX + ATTN */
5480 /* PF */
5481                 REG_WR(sc,
5482                        (IGU_REG_STATISTIC_NUM_MESSAGE_SENT +
5483                         (BNX2X_IGU_STAS_MSG_VF_CNT * 4) +
5484                         ((CHIP_IS_MODE_4_PORT(sc) ? SC_FUNC(sc) : SC_VN(sc)) *
5485                          4)), 0);
5486 /* ATTN */
5487                 REG_WR(sc,
5488                        (IGU_REG_STATISTIC_NUM_MESSAGE_SENT +
5489                         (BNX2X_IGU_STAS_MSG_VF_CNT * 4) +
5490                         (BNX2X_IGU_STAS_MSG_PF_CNT * 4) +
5491                         ((CHIP_IS_MODE_4_PORT(sc) ? SC_FUNC(sc) : SC_VN(sc)) *
5492                          4)), 0);
5493         }
5494
5495         /* function setup flags */
5496         flags = (FUNC_FLG_STATS | FUNC_FLG_LEADING | FUNC_FLG_SPQ);
5497
5498         func_init.func_flgs = flags;
5499         func_init.pf_id = SC_FUNC(sc);
5500         func_init.func_id = SC_FUNC(sc);
5501         func_init.spq_map = sc->spq_dma.paddr;
5502         func_init.spq_prod = sc->spq_prod_idx;
5503
5504         bnx2x_func_init(sc, &func_init);
5505
5506         memset(&sc->cmng, 0, sizeof(struct cmng_struct_per_port));
5507
5508         /*
5509          * Congestion management values depend on the link rate.
5510          * There is no active link so initial link rate is set to 10Gbps.
5511          * When the link comes up the congestion management values are
5512          * re-calculated according to the actual link rate.
5513          */
5514         sc->link_vars.line_speed = SPEED_10000;
5515         bnx2x_cmng_fns_init(sc, TRUE, bnx2x_get_cmng_fns_mode(sc));
5516
5517         /* Only the PMF sets the HW */
5518         if (sc->port.pmf) {
5519                 storm_memset_cmng(sc, &sc->cmng, SC_PORT(sc));
5520         }
5521
5522         /* init Event Queue - PCI bus guarantees correct endainity */
5523         eq_data.base_addr.hi = U64_HI(sc->eq_dma.paddr);
5524         eq_data.base_addr.lo = U64_LO(sc->eq_dma.paddr);
5525         eq_data.producer = sc->eq_prod;
5526         eq_data.index_id = HC_SP_INDEX_EQ_CONS;
5527         eq_data.sb_id = DEF_SB_ID;
5528         storm_memset_eq_data(sc, &eq_data, SC_FUNC(sc));
5529 }
5530
5531 static void bnx2x_hc_int_enable(struct bnx2x_softc *sc)
5532 {
5533         int port = SC_PORT(sc);
5534         uint32_t addr = (port) ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0;
5535         uint32_t val = REG_RD(sc, addr);
5536         uint8_t msix = (sc->interrupt_mode == INTR_MODE_MSIX)
5537             || (sc->interrupt_mode == INTR_MODE_SINGLE_MSIX);
5538         uint8_t single_msix = (sc->interrupt_mode == INTR_MODE_SINGLE_MSIX);
5539         uint8_t msi = (sc->interrupt_mode == INTR_MODE_MSI);
5540
5541         if (msix) {
5542                 val &= ~(HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
5543                          HC_CONFIG_0_REG_INT_LINE_EN_0);
5544                 val |= (HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
5545                         HC_CONFIG_0_REG_ATTN_BIT_EN_0);
5546                 if (single_msix) {
5547                         val |= HC_CONFIG_0_REG_SINGLE_ISR_EN_0;
5548                 }
5549         } else if (msi) {
5550                 val &= ~HC_CONFIG_0_REG_INT_LINE_EN_0;
5551                 val |= (HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
5552                         HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
5553                         HC_CONFIG_0_REG_ATTN_BIT_EN_0);
5554         } else {
5555                 val |= (HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
5556                         HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
5557                         HC_CONFIG_0_REG_INT_LINE_EN_0 |
5558                         HC_CONFIG_0_REG_ATTN_BIT_EN_0);
5559
5560                 REG_WR(sc, addr, val);
5561
5562                 val &= ~HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0;
5563         }
5564
5565         REG_WR(sc, addr, val);
5566
5567         /* ensure that HC_CONFIG is written before leading/trailing edge config */
5568         mb();
5569
5570         /* init leading/trailing edge */
5571         if (IS_MF(sc)) {
5572                 val = (0xee0f | (1 << (SC_VN(sc) + 4)));
5573                 if (sc->port.pmf) {
5574                         /* enable nig and gpio3 attention */
5575                         val |= 0x1100;
5576                 }
5577         } else {
5578                 val = 0xffff;
5579         }
5580
5581         REG_WR(sc, (HC_REG_TRAILING_EDGE_0 + port * 8), val);
5582         REG_WR(sc, (HC_REG_LEADING_EDGE_0 + port * 8), val);
5583
5584         /* make sure that interrupts are indeed enabled from here on */
5585         mb();
5586 }
5587
5588 static void bnx2x_igu_int_enable(struct bnx2x_softc *sc)
5589 {
5590         uint32_t val;
5591         uint8_t msix = (sc->interrupt_mode == INTR_MODE_MSIX)
5592             || (sc->interrupt_mode == INTR_MODE_SINGLE_MSIX);
5593         uint8_t single_msix = (sc->interrupt_mode == INTR_MODE_SINGLE_MSIX);
5594         uint8_t msi = (sc->interrupt_mode == INTR_MODE_MSI);
5595
5596         val = REG_RD(sc, IGU_REG_PF_CONFIGURATION);
5597
5598         if (msix) {
5599                 val &= ~(IGU_PF_CONF_INT_LINE_EN | IGU_PF_CONF_SINGLE_ISR_EN);
5600                 val |= (IGU_PF_CONF_MSI_MSIX_EN | IGU_PF_CONF_ATTN_BIT_EN);
5601                 if (single_msix) {
5602                         val |= IGU_PF_CONF_SINGLE_ISR_EN;
5603                 }
5604         } else if (msi) {
5605                 val &= ~IGU_PF_CONF_INT_LINE_EN;
5606                 val |= (IGU_PF_CONF_MSI_MSIX_EN |
5607                         IGU_PF_CONF_ATTN_BIT_EN | IGU_PF_CONF_SINGLE_ISR_EN);
5608         } else {
5609                 val &= ~IGU_PF_CONF_MSI_MSIX_EN;
5610                 val |= (IGU_PF_CONF_INT_LINE_EN |
5611                         IGU_PF_CONF_ATTN_BIT_EN | IGU_PF_CONF_SINGLE_ISR_EN);
5612         }
5613
5614         /* clean previous status - need to configure igu prior to ack */
5615         if ((!msix) || single_msix) {
5616                 REG_WR(sc, IGU_REG_PF_CONFIGURATION, val);
5617                 bnx2x_ack_int(sc);
5618         }
5619
5620         val |= IGU_PF_CONF_FUNC_EN;
5621
5622         PMD_DRV_LOG(DEBUG, sc, "write 0x%x to IGU mode %s",
5623                     val, ((msix) ? "MSI-X" : ((msi) ? "MSI" : "INTx")));
5624
5625         REG_WR(sc, IGU_REG_PF_CONFIGURATION, val);
5626
5627         mb();
5628
5629         /* init leading/trailing edge */
5630         if (IS_MF(sc)) {
5631                 val = (0xee0f | (1 << (SC_VN(sc) + 4)));
5632                 if (sc->port.pmf) {
5633                         /* enable nig and gpio3 attention */
5634                         val |= 0x1100;
5635                 }
5636         } else {
5637                 val = 0xffff;
5638         }
5639
5640         REG_WR(sc, IGU_REG_TRAILING_EDGE_LATCH, val);
5641         REG_WR(sc, IGU_REG_LEADING_EDGE_LATCH, val);
5642
5643         /* make sure that interrupts are indeed enabled from here on */
5644         mb();
5645 }
5646
5647 static void bnx2x_int_enable(struct bnx2x_softc *sc)
5648 {
5649         if (sc->devinfo.int_block == INT_BLOCK_HC) {
5650                 bnx2x_hc_int_enable(sc);
5651         } else {
5652                 bnx2x_igu_int_enable(sc);
5653         }
5654 }
5655
5656 static void bnx2x_hc_int_disable(struct bnx2x_softc *sc)
5657 {
5658         int port = SC_PORT(sc);
5659         uint32_t addr = (port) ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0;
5660         uint32_t val = REG_RD(sc, addr);
5661
5662         val &= ~(HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
5663                  HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
5664                  HC_CONFIG_0_REG_INT_LINE_EN_0 | HC_CONFIG_0_REG_ATTN_BIT_EN_0);
5665         /* flush all outstanding writes */
5666         mb();
5667
5668         REG_WR(sc, addr, val);
5669         if (REG_RD(sc, addr) != val) {
5670                 PMD_DRV_LOG(ERR, sc, "proper val not read from HC IGU!");
5671         }
5672 }
5673
5674 static void bnx2x_igu_int_disable(struct bnx2x_softc *sc)
5675 {
5676         uint32_t val = REG_RD(sc, IGU_REG_PF_CONFIGURATION);
5677
5678         val &= ~(IGU_PF_CONF_MSI_MSIX_EN |
5679                  IGU_PF_CONF_INT_LINE_EN | IGU_PF_CONF_ATTN_BIT_EN);
5680
5681         PMD_DRV_LOG(DEBUG, sc, "write %x to IGU", val);
5682
5683         /* flush all outstanding writes */
5684         mb();
5685
5686         REG_WR(sc, IGU_REG_PF_CONFIGURATION, val);
5687         if (REG_RD(sc, IGU_REG_PF_CONFIGURATION) != val) {
5688                 PMD_DRV_LOG(ERR, sc, "proper val not read from IGU!");
5689         }
5690 }
5691
5692 static void bnx2x_int_disable(struct bnx2x_softc *sc)
5693 {
5694         if (sc->devinfo.int_block == INT_BLOCK_HC) {
5695                 bnx2x_hc_int_disable(sc);
5696         } else {
5697                 bnx2x_igu_int_disable(sc);
5698         }
5699 }
5700
5701 static void bnx2x_nic_init(struct bnx2x_softc *sc, int load_code)
5702 {
5703         int i;
5704
5705         PMD_INIT_FUNC_TRACE(sc);
5706
5707         for (i = 0; i < sc->num_queues; i++) {
5708                 bnx2x_init_eth_fp(sc, i);
5709         }
5710
5711         rmb();                  /* ensure status block indices were read */
5712
5713         bnx2x_init_rx_rings(sc);
5714         bnx2x_init_tx_rings(sc);
5715
5716         if (IS_VF(sc)) {
5717                 bnx2x_memset_stats(sc);
5718                 return;
5719         }
5720
5721         /* initialize MOD_ABS interrupts */
5722         elink_init_mod_abs_int(sc, &sc->link_vars,
5723                                sc->devinfo.chip_id,
5724                                sc->devinfo.shmem_base,
5725                                sc->devinfo.shmem2_base, SC_PORT(sc));
5726
5727         bnx2x_init_def_sb(sc);
5728         bnx2x_update_dsb_idx(sc);
5729         bnx2x_init_sp_ring(sc);
5730         bnx2x_init_eq_ring(sc);
5731         bnx2x_init_internal(sc, load_code);
5732         bnx2x_pf_init(sc);
5733         bnx2x_stats_init(sc);
5734
5735         /* flush all before enabling interrupts */
5736         mb();
5737
5738         bnx2x_int_enable(sc);
5739
5740         /* check for SPIO5 */
5741         bnx2x_attn_int_deasserted0(sc,
5742                                  REG_RD(sc,
5743                                         (MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 +
5744                                          SC_PORT(sc) * 4)) &
5745                                  AEU_INPUTS_ATTN_BITS_SPIO5);
5746 }
5747
5748 static void bnx2x_init_objs(struct bnx2x_softc *sc)
5749 {
5750         /* mcast rules must be added to tx if tx switching is enabled */
5751         ecore_obj_type o_type;
5752         if (sc->flags & BNX2X_TX_SWITCHING)
5753                 o_type = ECORE_OBJ_TYPE_RX_TX;
5754         else
5755                 o_type = ECORE_OBJ_TYPE_RX;
5756
5757         /* RX_MODE controlling object */
5758         ecore_init_rx_mode_obj(sc, &sc->rx_mode_obj);
5759
5760         /* multicast configuration controlling object */
5761         ecore_init_mcast_obj(sc,
5762                              &sc->mcast_obj,
5763                              sc->fp[0].cl_id,
5764                              sc->fp[0].index,
5765                              SC_FUNC(sc),
5766                              SC_FUNC(sc),
5767                              BNX2X_SP(sc, mcast_rdata),
5768                              (rte_iova_t)BNX2X_SP_MAPPING(sc, mcast_rdata),
5769                              ECORE_FILTER_MCAST_PENDING,
5770                              &sc->sp_state, o_type);
5771
5772         /* Setup CAM credit pools */
5773         ecore_init_mac_credit_pool(sc,
5774                                    &sc->macs_pool,
5775                                    SC_FUNC(sc),
5776                                    CHIP_IS_E1x(sc) ? VNICS_PER_PORT(sc) :
5777                                    VNICS_PER_PATH(sc));
5778
5779         ecore_init_vlan_credit_pool(sc,
5780                                     &sc->vlans_pool,
5781                                     SC_ABS_FUNC(sc) >> 1,
5782                                     CHIP_IS_E1x(sc) ? VNICS_PER_PORT(sc) :
5783                                     VNICS_PER_PATH(sc));
5784
5785         /* RSS configuration object */
5786         ecore_init_rss_config_obj(&sc->rss_conf_obj,
5787                                   sc->fp[0].cl_id,
5788                                   sc->fp[0].index,
5789                                   SC_FUNC(sc),
5790                                   SC_FUNC(sc),
5791                                   BNX2X_SP(sc, rss_rdata),
5792                                   (rte_iova_t)BNX2X_SP_MAPPING(sc, rss_rdata),
5793                                   ECORE_FILTER_RSS_CONF_PENDING,
5794                                   &sc->sp_state, ECORE_OBJ_TYPE_RX);
5795 }
5796
5797 /*
5798  * Initialize the function. This must be called before sending CLIENT_SETUP
5799  * for the first client.
5800  */
5801 static int bnx2x_func_start(struct bnx2x_softc *sc)
5802 {
5803         struct ecore_func_state_params func_params = { NULL };
5804         struct ecore_func_start_params *start_params =
5805             &func_params.params.start;
5806
5807         /* Prepare parameters for function state transitions */
5808         bnx2x_set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags);
5809
5810         func_params.f_obj = &sc->func_obj;
5811         func_params.cmd = ECORE_F_CMD_START;
5812
5813         /* Function parameters */
5814         start_params->mf_mode = sc->devinfo.mf_info.mf_mode;
5815         start_params->sd_vlan_tag = OVLAN(sc);
5816
5817         if (CHIP_IS_E2(sc) || CHIP_IS_E3(sc)) {
5818                 start_params->network_cos_mode = STATIC_COS;
5819         } else {                /* CHIP_IS_E1X */
5820                 start_params->network_cos_mode = FW_WRR;
5821         }
5822
5823         start_params->gre_tunnel_mode = 0;
5824         start_params->gre_tunnel_rss = 0;
5825
5826         return ecore_func_state_change(sc, &func_params);
5827 }
5828
5829 static int bnx2x_set_power_state(struct bnx2x_softc *sc, uint8_t state)
5830 {
5831         uint16_t pmcsr;
5832
5833         /* If there is no power capability, silently succeed */
5834         if (!(sc->devinfo.pcie_cap_flags & BNX2X_PM_CAPABLE_FLAG)) {
5835                 PMD_DRV_LOG(INFO, sc, "No power capability");
5836                 return 0;
5837         }
5838
5839         pci_read(sc, (sc->devinfo.pcie_pm_cap_reg + PCIR_POWER_STATUS), &pmcsr,
5840                  2);
5841
5842         switch (state) {
5843         case PCI_PM_D0:
5844                 pci_write_word(sc,
5845                                (sc->devinfo.pcie_pm_cap_reg +
5846                                 PCIR_POWER_STATUS),
5847                                ((pmcsr & ~PCIM_PSTAT_DMASK) | PCIM_PSTAT_PME));
5848
5849                 if (pmcsr & PCIM_PSTAT_DMASK) {
5850                         /* delay required during transition out of D3hot */
5851                         DELAY(20000);
5852                 }
5853
5854                 break;
5855
5856         case PCI_PM_D3hot:
5857                 /* don't shut down the power for emulation and FPGA */
5858                 if (CHIP_REV_IS_SLOW(sc)) {
5859                         return 0;
5860                 }
5861
5862                 pmcsr &= ~PCIM_PSTAT_DMASK;
5863                 pmcsr |= PCIM_PSTAT_D3;
5864
5865                 if (sc->wol) {
5866                         pmcsr |= PCIM_PSTAT_PMEENABLE;
5867                 }
5868
5869                 pci_write_long(sc,
5870                                (sc->devinfo.pcie_pm_cap_reg +
5871                                 PCIR_POWER_STATUS), pmcsr);
5872
5873                 /*
5874                  * No more memory access after this point until device is brought back
5875                  * to D0 state.
5876                  */
5877                 break;
5878
5879         default:
5880                 PMD_DRV_LOG(NOTICE, sc, "Can't support PCI power state = %d",
5881                             state);
5882                 return -1;
5883         }
5884
5885         return 0;
5886 }
5887
5888 /* return true if succeeded to acquire the lock */
5889 static uint8_t bnx2x_trylock_hw_lock(struct bnx2x_softc *sc, uint32_t resource)
5890 {
5891         uint32_t lock_status;
5892         uint32_t resource_bit = (1 << resource);
5893         int func = SC_FUNC(sc);
5894         uint32_t hw_lock_control_reg;
5895
5896         /* Validating that the resource is within range */
5897         if (resource > HW_LOCK_MAX_RESOURCE_VALUE) {
5898                 PMD_DRV_LOG(INFO, sc,
5899                             "resource(0x%x) > HW_LOCK_MAX_RESOURCE_VALUE(0x%x)",
5900                             resource, HW_LOCK_MAX_RESOURCE_VALUE);
5901                 return FALSE;
5902         }
5903
5904         if (func <= 5) {
5905                 hw_lock_control_reg = (MISC_REG_DRIVER_CONTROL_1 + func * 8);
5906         } else {
5907                 hw_lock_control_reg =
5908                     (MISC_REG_DRIVER_CONTROL_7 + (func - 6) * 8);
5909         }
5910
5911         /* try to acquire the lock */
5912         REG_WR(sc, hw_lock_control_reg + 4, resource_bit);
5913         lock_status = REG_RD(sc, hw_lock_control_reg);
5914         if (lock_status & resource_bit) {
5915                 return TRUE;
5916         }
5917
5918         PMD_DRV_LOG(NOTICE, sc, "Failed to get a resource lock 0x%x", resource);
5919
5920         return FALSE;
5921 }
5922
5923 /*
5924  * Get the recovery leader resource id according to the engine this function
5925  * belongs to. Currently only only 2 engines is supported.
5926  */
5927 static int bnx2x_get_leader_lock_resource(struct bnx2x_softc *sc)
5928 {
5929         if (SC_PATH(sc)) {
5930                 return HW_LOCK_RESOURCE_RECOVERY_LEADER_1;
5931         } else {
5932                 return HW_LOCK_RESOURCE_RECOVERY_LEADER_0;
5933         }
5934 }
5935
5936 /* try to acquire a leader lock for current engine */
5937 static uint8_t bnx2x_trylock_leader_lock(struct bnx2x_softc *sc)
5938 {
5939         return bnx2x_trylock_hw_lock(sc, bnx2x_get_leader_lock_resource(sc));
5940 }
5941
5942 static int bnx2x_release_leader_lock(struct bnx2x_softc *sc)
5943 {
5944         return bnx2x_release_hw_lock(sc, bnx2x_get_leader_lock_resource(sc));
5945 }
5946
5947 /* close gates #2, #3 and #4 */
5948 static void bnx2x_set_234_gates(struct bnx2x_softc *sc, uint8_t close)
5949 {
5950         uint32_t val;
5951
5952         /* gates #2 and #4a are closed/opened */
5953         /* #4 */
5954         REG_WR(sc, PXP_REG_HST_DISCARD_DOORBELLS, ! !close);
5955         /* #2 */
5956         REG_WR(sc, PXP_REG_HST_DISCARD_INTERNAL_WRITES, ! !close);
5957
5958         /* #3 */
5959         if (CHIP_IS_E1x(sc)) {
5960 /* prevent interrupts from HC on both ports */
5961                 val = REG_RD(sc, HC_REG_CONFIG_1);
5962                 if (close)
5963                         REG_WR(sc, HC_REG_CONFIG_1, (val & ~(uint32_t)
5964                                                      HC_CONFIG_1_REG_BLOCK_DISABLE_1));
5965                 else
5966                         REG_WR(sc, HC_REG_CONFIG_1,
5967                                (val | HC_CONFIG_1_REG_BLOCK_DISABLE_1));
5968
5969                 val = REG_RD(sc, HC_REG_CONFIG_0);
5970                 if (close)
5971                         REG_WR(sc, HC_REG_CONFIG_0, (val & ~(uint32_t)
5972                                                      HC_CONFIG_0_REG_BLOCK_DISABLE_0));
5973                 else
5974                         REG_WR(sc, HC_REG_CONFIG_0,
5975                                (val | HC_CONFIG_0_REG_BLOCK_DISABLE_0));
5976
5977         } else {
5978 /* Prevent incoming interrupts in IGU */
5979                 val = REG_RD(sc, IGU_REG_BLOCK_CONFIGURATION);
5980
5981                 if (close)
5982                         REG_WR(sc, IGU_REG_BLOCK_CONFIGURATION,
5983                                (val & ~(uint32_t)
5984                                 IGU_BLOCK_CONFIGURATION_REG_BLOCK_ENABLE));
5985                 else
5986                         REG_WR(sc, IGU_REG_BLOCK_CONFIGURATION,
5987                                (val |
5988                                 IGU_BLOCK_CONFIGURATION_REG_BLOCK_ENABLE));
5989         }
5990
5991         wmb();
5992 }
5993
5994 /* poll for pending writes bit, it should get cleared in no more than 1s */
5995 static int bnx2x_er_poll_igu_vq(struct bnx2x_softc *sc)
5996 {
5997         uint32_t cnt = 1000;
5998         uint32_t pend_bits = 0;
5999
6000         do {
6001                 pend_bits = REG_RD(sc, IGU_REG_PENDING_BITS_STATUS);
6002
6003                 if (pend_bits == 0) {
6004                         break;
6005                 }
6006
6007                 DELAY(1000);
6008         } while (cnt-- > 0);
6009
6010         if (cnt <= 0) {
6011                 PMD_DRV_LOG(NOTICE, sc, "Still pending IGU requests bits=0x%08x!",
6012                             pend_bits);
6013                 return -1;
6014         }
6015
6016         return 0;
6017 }
6018
6019 #define SHARED_MF_CLP_MAGIC  0x80000000 /* 'magic' bit */
6020
6021 static void bnx2x_clp_reset_prep(struct bnx2x_softc *sc, uint32_t * magic_val)
6022 {
6023         /* Do some magic... */
6024         uint32_t val = MFCFG_RD(sc, shared_mf_config.clp_mb);
6025         *magic_val = val & SHARED_MF_CLP_MAGIC;
6026         MFCFG_WR(sc, shared_mf_config.clp_mb, val | SHARED_MF_CLP_MAGIC);
6027 }
6028
6029 /* restore the value of the 'magic' bit */
6030 static void bnx2x_clp_reset_done(struct bnx2x_softc *sc, uint32_t magic_val)
6031 {
6032         /* Restore the 'magic' bit value... */
6033         uint32_t val = MFCFG_RD(sc, shared_mf_config.clp_mb);
6034         MFCFG_WR(sc, shared_mf_config.clp_mb,
6035                  (val & (~SHARED_MF_CLP_MAGIC)) | magic_val);
6036 }
6037
6038 /* prepare for MCP reset, takes care of CLP configurations */
6039 static void bnx2x_reset_mcp_prep(struct bnx2x_softc *sc, uint32_t * magic_val)
6040 {
6041         uint32_t shmem;
6042         uint32_t validity_offset;
6043
6044         /* set `magic' bit in order to save MF config */
6045         bnx2x_clp_reset_prep(sc, magic_val);
6046
6047         /* get shmem offset */
6048         shmem = REG_RD(sc, MISC_REG_SHARED_MEM_ADDR);
6049         validity_offset =
6050             offsetof(struct shmem_region, validity_map[SC_PORT(sc)]);
6051
6052         /* Clear validity map flags */
6053         if (shmem > 0) {
6054                 REG_WR(sc, shmem + validity_offset, 0);
6055         }
6056 }
6057
6058 #define MCP_TIMEOUT      5000   /* 5 seconds (in ms) */
6059 #define MCP_ONE_TIMEOUT  100    /* 100 ms */
6060
6061 static void bnx2x_mcp_wait_one(struct bnx2x_softc *sc)
6062 {
6063         /* special handling for emulation and FPGA (10 times longer) */
6064         if (CHIP_REV_IS_SLOW(sc)) {
6065                 DELAY((MCP_ONE_TIMEOUT * 10) * 1000);
6066         } else {
6067                 DELAY((MCP_ONE_TIMEOUT) * 1000);
6068         }
6069 }
6070
6071 /* initialize shmem_base and waits for validity signature to appear */
6072 static int bnx2x_init_shmem(struct bnx2x_softc *sc)
6073 {
6074         int cnt = 0;
6075         uint32_t val = 0;
6076
6077         do {
6078                 sc->devinfo.shmem_base =
6079                     sc->link_params.shmem_base =
6080                     REG_RD(sc, MISC_REG_SHARED_MEM_ADDR);
6081
6082                 if (sc->devinfo.shmem_base) {
6083                         val = SHMEM_RD(sc, validity_map[SC_PORT(sc)]);
6084                         if (val & SHR_MEM_VALIDITY_MB)
6085                                 return 0;
6086                 }
6087
6088                 bnx2x_mcp_wait_one(sc);
6089
6090         } while (cnt++ < (MCP_TIMEOUT / MCP_ONE_TIMEOUT));
6091
6092         PMD_DRV_LOG(NOTICE, sc, "BAD MCP validity signature");
6093
6094         return -1;
6095 }
6096
6097 static int bnx2x_reset_mcp_comp(struct bnx2x_softc *sc, uint32_t magic_val)
6098 {
6099         int rc = bnx2x_init_shmem(sc);
6100
6101         /* Restore the `magic' bit value */
6102         bnx2x_clp_reset_done(sc, magic_val);
6103
6104         return rc;
6105 }
6106
6107 static void bnx2x_pxp_prep(struct bnx2x_softc *sc)
6108 {
6109         REG_WR(sc, PXP2_REG_RD_START_INIT, 0);
6110         REG_WR(sc, PXP2_REG_RQ_RBC_DONE, 0);
6111         wmb();
6112 }
6113
6114 /*
6115  * Reset the whole chip except for:
6116  *      - PCIE core
6117  *      - PCI Glue, PSWHST, PXP/PXP2 RF (all controlled by one reset bit)
6118  *      - IGU
6119  *      - MISC (including AEU)
6120  *      - GRC
6121  *      - RBCN, RBCP
6122  */
6123 static void bnx2x_process_kill_chip_reset(struct bnx2x_softc *sc, uint8_t global)
6124 {
6125         uint32_t not_reset_mask1, reset_mask1, not_reset_mask2, reset_mask2;
6126         uint32_t global_bits2, stay_reset2;
6127
6128         /*
6129          * Bits that have to be set in reset_mask2 if we want to reset 'global'
6130          * (per chip) blocks.
6131          */
6132         global_bits2 =
6133             MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_CMN_CPU |
6134             MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_CMN_CORE;
6135
6136         /*
6137          * Don't reset the following blocks.
6138          * Important: per port blocks (such as EMAC, BMAC, UMAC) can't be
6139          *            reset, as in 4 port device they might still be owned
6140          *            by the MCP (there is only one leader per path).
6141          */
6142         not_reset_mask1 =
6143             MISC_REGISTERS_RESET_REG_1_RST_HC |
6144             MISC_REGISTERS_RESET_REG_1_RST_PXPV |
6145             MISC_REGISTERS_RESET_REG_1_RST_PXP;
6146
6147         not_reset_mask2 =
6148             MISC_REGISTERS_RESET_REG_2_RST_PCI_MDIO |
6149             MISC_REGISTERS_RESET_REG_2_RST_EMAC0_HARD_CORE |
6150             MISC_REGISTERS_RESET_REG_2_RST_EMAC1_HARD_CORE |
6151             MISC_REGISTERS_RESET_REG_2_RST_MISC_CORE |
6152             MISC_REGISTERS_RESET_REG_2_RST_RBCN |
6153             MISC_REGISTERS_RESET_REG_2_RST_GRC |
6154             MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_REG_HARD_CORE |
6155             MISC_REGISTERS_RESET_REG_2_RST_MCP_N_HARD_CORE_RST_B |
6156             MISC_REGISTERS_RESET_REG_2_RST_ATC |
6157             MISC_REGISTERS_RESET_REG_2_PGLC |
6158             MISC_REGISTERS_RESET_REG_2_RST_BMAC0 |
6159             MISC_REGISTERS_RESET_REG_2_RST_BMAC1 |
6160             MISC_REGISTERS_RESET_REG_2_RST_EMAC0 |
6161             MISC_REGISTERS_RESET_REG_2_RST_EMAC1 |
6162             MISC_REGISTERS_RESET_REG_2_UMAC0 | MISC_REGISTERS_RESET_REG_2_UMAC1;
6163
6164         /*
6165          * Keep the following blocks in reset:
6166          *  - all xxMACs are handled by the elink code.
6167          */
6168         stay_reset2 =
6169             MISC_REGISTERS_RESET_REG_2_XMAC |
6170             MISC_REGISTERS_RESET_REG_2_XMAC_SOFT;
6171
6172         /* Full reset masks according to the chip */
6173         reset_mask1 = 0xffffffff;
6174
6175         if (CHIP_IS_E1H(sc))
6176                 reset_mask2 = 0x1ffff;
6177         else if (CHIP_IS_E2(sc))
6178                 reset_mask2 = 0xfffff;
6179         else                    /* CHIP_IS_E3 */
6180                 reset_mask2 = 0x3ffffff;
6181
6182         /* Don't reset global blocks unless we need to */
6183         if (!global)
6184                 reset_mask2 &= ~global_bits2;
6185
6186         /*
6187          * In case of attention in the QM, we need to reset PXP
6188          * (MISC_REGISTERS_RESET_REG_2_RST_PXP_RQ_RD_WR) before QM
6189          * because otherwise QM reset would release 'close the gates' shortly
6190          * before resetting the PXP, then the PSWRQ would send a write
6191          * request to PGLUE. Then when PXP is reset, PGLUE would try to
6192          * read the payload data from PSWWR, but PSWWR would not
6193          * respond. The write queue in PGLUE would stuck, dmae commands
6194          * would not return. Therefore it's important to reset the second
6195          * reset register (containing the
6196          * MISC_REGISTERS_RESET_REG_2_RST_PXP_RQ_RD_WR bit) before the
6197          * first one (containing the MISC_REGISTERS_RESET_REG_1_RST_QM
6198          * bit).
6199          */
6200         REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
6201                reset_mask2 & (~not_reset_mask2));
6202
6203         REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR,
6204                reset_mask1 & (~not_reset_mask1));
6205
6206         mb();
6207         wmb();
6208
6209         REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET,
6210                reset_mask2 & (~stay_reset2));
6211
6212         mb();
6213         wmb();
6214
6215         REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, reset_mask1);
6216         wmb();
6217 }
6218
6219 static int bnx2x_process_kill(struct bnx2x_softc *sc, uint8_t global)
6220 {
6221         int cnt = 1000;
6222         uint32_t val = 0;
6223         uint32_t sr_cnt, blk_cnt, port_is_idle_0, port_is_idle_1, pgl_exp_rom2;
6224         uint32_t tags_63_32 = 0;
6225
6226         /* Empty the Tetris buffer, wait for 1s */
6227         do {
6228                 sr_cnt = REG_RD(sc, PXP2_REG_RD_SR_CNT);
6229                 blk_cnt = REG_RD(sc, PXP2_REG_RD_BLK_CNT);
6230                 port_is_idle_0 = REG_RD(sc, PXP2_REG_RD_PORT_IS_IDLE_0);
6231                 port_is_idle_1 = REG_RD(sc, PXP2_REG_RD_PORT_IS_IDLE_1);
6232                 pgl_exp_rom2 = REG_RD(sc, PXP2_REG_PGL_EXP_ROM2);
6233                 if (CHIP_IS_E3(sc)) {
6234                         tags_63_32 = REG_RD(sc, PGLUE_B_REG_TAGS_63_32);
6235                 }
6236
6237                 if ((sr_cnt == 0x7e) && (blk_cnt == 0xa0) &&
6238                     ((port_is_idle_0 & 0x1) == 0x1) &&
6239                     ((port_is_idle_1 & 0x1) == 0x1) &&
6240                     (pgl_exp_rom2 == 0xffffffff) &&
6241                     (!CHIP_IS_E3(sc) || (tags_63_32 == 0xffffffff)))
6242                         break;
6243                 DELAY(1000);
6244         } while (cnt-- > 0);
6245
6246         if (cnt <= 0) {
6247                 PMD_DRV_LOG(NOTICE, sc,
6248                             "ERROR: Tetris buffer didn't get empty or there "
6249                             "are still outstanding read requests after 1s! "
6250                             "sr_cnt=0x%08x, blk_cnt=0x%08x, port_is_idle_0=0x%08x, "
6251                             "port_is_idle_1=0x%08x, pgl_exp_rom2=0x%08x",
6252                             sr_cnt, blk_cnt, port_is_idle_0, port_is_idle_1,
6253                             pgl_exp_rom2);
6254                 return -1;
6255         }
6256
6257         mb();
6258
6259         /* Close gates #2, #3 and #4 */
6260         bnx2x_set_234_gates(sc, TRUE);
6261
6262         /* Poll for IGU VQs for 57712 and newer chips */
6263         if (!CHIP_IS_E1x(sc) && bnx2x_er_poll_igu_vq(sc)) {
6264                 return -1;
6265         }
6266
6267         /* clear "unprepared" bit */
6268         REG_WR(sc, MISC_REG_UNPREPARED, 0);
6269         mb();
6270
6271         /* Make sure all is written to the chip before the reset */
6272         wmb();
6273
6274         /*
6275          * Wait for 1ms to empty GLUE and PCI-E core queues,
6276          * PSWHST, GRC and PSWRD Tetris buffer.
6277          */
6278         DELAY(1000);
6279
6280         /* Prepare to chip reset: */
6281         /* MCP */
6282         if (global) {
6283                 bnx2x_reset_mcp_prep(sc, &val);
6284         }
6285
6286         /* PXP */
6287         bnx2x_pxp_prep(sc);
6288         mb();
6289
6290         /* reset the chip */
6291         bnx2x_process_kill_chip_reset(sc, global);
6292         mb();
6293
6294         /* Recover after reset: */
6295         /* MCP */
6296         if (global && bnx2x_reset_mcp_comp(sc, val)) {
6297                 return -1;
6298         }
6299
6300         /* Open the gates #2, #3 and #4 */
6301         bnx2x_set_234_gates(sc, FALSE);
6302
6303         return 0;
6304 }
6305
6306 static int bnx2x_leader_reset(struct bnx2x_softc *sc)
6307 {
6308         int rc = 0;
6309         uint8_t global = bnx2x_reset_is_global(sc);
6310         uint32_t load_code;
6311
6312         /*
6313          * If not going to reset MCP, load "fake" driver to reset HW while
6314          * driver is owner of the HW.
6315          */
6316         if (!global && !BNX2X_NOMCP(sc)) {
6317                 load_code = bnx2x_fw_command(sc, DRV_MSG_CODE_LOAD_REQ,
6318                                            DRV_MSG_CODE_LOAD_REQ_WITH_LFA);
6319                 if (!load_code) {
6320                         PMD_DRV_LOG(NOTICE, sc, "MCP response failure, aborting");
6321                         rc = -1;
6322                         goto exit_leader_reset;
6323                 }
6324
6325                 if ((load_code != FW_MSG_CODE_DRV_LOAD_COMMON_CHIP) &&
6326                     (load_code != FW_MSG_CODE_DRV_LOAD_COMMON)) {
6327                         PMD_DRV_LOG(NOTICE, sc,
6328                                     "MCP unexpected response, aborting");
6329                         rc = -1;
6330                         goto exit_leader_reset2;
6331                 }
6332
6333                 load_code = bnx2x_fw_command(sc, DRV_MSG_CODE_LOAD_DONE, 0);
6334                 if (!load_code) {
6335                         PMD_DRV_LOG(NOTICE, sc, "MCP response failure, aborting");
6336                         rc = -1;
6337                         goto exit_leader_reset2;
6338                 }
6339         }
6340
6341         /* try to recover after the failure */
6342         if (bnx2x_process_kill(sc, global)) {
6343                 PMD_DRV_LOG(NOTICE, sc, "Something bad occurred on engine %d!",
6344                             SC_PATH(sc));
6345                 rc = -1;
6346                 goto exit_leader_reset2;
6347         }
6348
6349         /*
6350          * Clear the RESET_IN_PROGRESS and RESET_GLOBAL bits and update the driver
6351          * state.
6352          */
6353         bnx2x_set_reset_done(sc);
6354         if (global) {
6355                 bnx2x_clear_reset_global(sc);
6356         }
6357
6358 exit_leader_reset2:
6359
6360         /* unload "fake driver" if it was loaded */
6361         if (!global &&!BNX2X_NOMCP(sc)) {
6362                 bnx2x_fw_command(sc, DRV_MSG_CODE_UNLOAD_REQ_WOL_MCP, 0);
6363                 bnx2x_fw_command(sc, DRV_MSG_CODE_UNLOAD_DONE, 0);
6364         }
6365
6366 exit_leader_reset:
6367
6368         sc->is_leader = 0;
6369         bnx2x_release_leader_lock(sc);
6370
6371         mb();
6372         return rc;
6373 }
6374
6375 /*
6376  * prepare INIT transition, parameters configured:
6377  *   - HC configuration
6378  *   - Queue's CDU context
6379  */
6380 static void
6381 bnx2x_pf_q_prep_init(struct bnx2x_softc *sc, struct bnx2x_fastpath *fp,
6382                    struct ecore_queue_init_params *init_params)
6383 {
6384         uint8_t cos;
6385         int cxt_index, cxt_offset;
6386
6387         bnx2x_set_bit(ECORE_Q_FLG_HC, &init_params->rx.flags);
6388         bnx2x_set_bit(ECORE_Q_FLG_HC, &init_params->tx.flags);
6389
6390         bnx2x_set_bit(ECORE_Q_FLG_HC_EN, &init_params->rx.flags);
6391         bnx2x_set_bit(ECORE_Q_FLG_HC_EN, &init_params->tx.flags);
6392
6393         /* HC rate */
6394         init_params->rx.hc_rate =
6395             sc->hc_rx_ticks ? (1000000 / sc->hc_rx_ticks) : 0;
6396         init_params->tx.hc_rate =
6397             sc->hc_tx_ticks ? (1000000 / sc->hc_tx_ticks) : 0;
6398
6399         /* FW SB ID */
6400         init_params->rx.fw_sb_id = init_params->tx.fw_sb_id = fp->fw_sb_id;
6401
6402         /* CQ index among the SB indices */
6403         init_params->rx.sb_cq_index = HC_INDEX_ETH_RX_CQ_CONS;
6404         init_params->tx.sb_cq_index = HC_INDEX_ETH_FIRST_TX_CQ_CONS;
6405
6406         /* set maximum number of COSs supported by this queue */
6407         init_params->max_cos = sc->max_cos;
6408
6409         /* set the context pointers queue object */
6410         for (cos = FIRST_TX_COS_INDEX; cos < init_params->max_cos; cos++) {
6411                 cxt_index = fp->index / ILT_PAGE_CIDS;
6412                 cxt_offset = fp->index - (cxt_index * ILT_PAGE_CIDS);
6413                 init_params->cxts[cos] =
6414                     &sc->context[cxt_index].vcxt[cxt_offset].eth;
6415         }
6416 }
6417
6418 /* set flags that are common for the Tx-only and not normal connections */
6419 static unsigned long
6420 bnx2x_get_common_flags(struct bnx2x_softc *sc, uint8_t zero_stats)
6421 {
6422         unsigned long flags = 0;
6423
6424         /* PF driver will always initialize the Queue to an ACTIVE state */
6425         bnx2x_set_bit(ECORE_Q_FLG_ACTIVE, &flags);
6426
6427         /*
6428          * tx only connections collect statistics (on the same index as the
6429          * parent connection). The statistics are zeroed when the parent
6430          * connection is initialized.
6431          */
6432
6433         bnx2x_set_bit(ECORE_Q_FLG_STATS, &flags);
6434         if (zero_stats) {
6435                 bnx2x_set_bit(ECORE_Q_FLG_ZERO_STATS, &flags);
6436         }
6437
6438         /*
6439          * tx only connections can support tx-switching, though their
6440          * CoS-ness doesn't survive the loopback
6441          */
6442         if (sc->flags & BNX2X_TX_SWITCHING) {
6443                 bnx2x_set_bit(ECORE_Q_FLG_TX_SWITCH, &flags);
6444         }
6445
6446         bnx2x_set_bit(ECORE_Q_FLG_PCSUM_ON_PKT, &flags);
6447
6448         return flags;
6449 }
6450
6451 static unsigned long bnx2x_get_q_flags(struct bnx2x_softc *sc, uint8_t leading)
6452 {
6453         unsigned long flags = 0;
6454
6455         if (IS_MF_SD(sc)) {
6456                 bnx2x_set_bit(ECORE_Q_FLG_OV, &flags);
6457         }
6458
6459         if (leading) {
6460                 bnx2x_set_bit(ECORE_Q_FLG_LEADING_RSS, &flags);
6461                 bnx2x_set_bit(ECORE_Q_FLG_MCAST, &flags);
6462         }
6463
6464         bnx2x_set_bit(ECORE_Q_FLG_VLAN, &flags);
6465
6466         /* merge with common flags */
6467         return flags | bnx2x_get_common_flags(sc, TRUE);
6468 }
6469
6470 static void
6471 bnx2x_pf_q_prep_general(struct bnx2x_softc *sc, struct bnx2x_fastpath *fp,
6472                       struct ecore_general_setup_params *gen_init, uint8_t cos)
6473 {
6474         gen_init->stat_id = bnx2x_stats_id(fp);
6475         gen_init->spcl_id = fp->cl_id;
6476         gen_init->mtu = sc->mtu;
6477         gen_init->cos = cos;
6478 }
6479
6480 static void
6481 bnx2x_pf_rx_q_prep(struct bnx2x_softc *sc, struct bnx2x_fastpath *fp,
6482                  struct rxq_pause_params *pause,
6483                  struct ecore_rxq_setup_params *rxq_init)
6484 {
6485         struct bnx2x_rx_queue *rxq;
6486
6487         rxq = sc->rx_queues[fp->index];
6488         if (!rxq) {
6489                 PMD_RX_LOG(ERR, "RX queue is NULL");
6490                 return;
6491         }
6492         /* pause */
6493         pause->bd_th_lo = BD_TH_LO(sc);
6494         pause->bd_th_hi = BD_TH_HI(sc);
6495
6496         pause->rcq_th_lo = RCQ_TH_LO(sc);
6497         pause->rcq_th_hi = RCQ_TH_HI(sc);
6498
6499         /* validate rings have enough entries to cross high thresholds */
6500         if (sc->dropless_fc &&
6501             pause->bd_th_hi + FW_PREFETCH_CNT > sc->rx_ring_size) {
6502                 PMD_DRV_LOG(WARNING, sc, "rx bd ring threshold limit");
6503         }
6504
6505         if (sc->dropless_fc &&
6506             pause->rcq_th_hi + FW_PREFETCH_CNT > USABLE_RCQ_ENTRIES(rxq)) {
6507                 PMD_DRV_LOG(WARNING, sc, "rcq ring threshold limit");
6508         }
6509
6510         pause->pri_map = 1;
6511
6512         /* rxq setup */
6513         rxq_init->dscr_map = (rte_iova_t)rxq->rx_ring_phys_addr;
6514         rxq_init->rcq_map = (rte_iova_t)rxq->cq_ring_phys_addr;
6515         rxq_init->rcq_np_map = (rte_iova_t)(rxq->cq_ring_phys_addr +
6516                                               BNX2X_PAGE_SIZE);
6517
6518         /*
6519          * This should be a maximum number of data bytes that may be
6520          * placed on the BD (not including paddings).
6521          */
6522         rxq_init->buf_sz = (fp->rx_buf_size - IP_HEADER_ALIGNMENT_PADDING);
6523
6524         rxq_init->cl_qzone_id = fp->cl_qzone_id;
6525         rxq_init->rss_engine_id = SC_FUNC(sc);
6526         rxq_init->mcast_engine_id = SC_FUNC(sc);
6527
6528         rxq_init->cache_line_log = BNX2X_RX_ALIGN_SHIFT;
6529         rxq_init->fw_sb_id = fp->fw_sb_id;
6530
6531         rxq_init->sb_cq_index = HC_INDEX_ETH_RX_CQ_CONS;
6532
6533         /*
6534          * configure silent vlan removal
6535          * if multi function mode is afex, then mask default vlan
6536          */
6537         if (IS_MF_AFEX(sc)) {
6538                 rxq_init->silent_removal_value =
6539                     sc->devinfo.mf_info.afex_def_vlan_tag;
6540                 rxq_init->silent_removal_mask = EVL_VLID_MASK;
6541         }
6542 }
6543
6544 static void
6545 bnx2x_pf_tx_q_prep(struct bnx2x_softc *sc, struct bnx2x_fastpath *fp,
6546                  struct ecore_txq_setup_params *txq_init, uint8_t cos)
6547 {
6548         struct bnx2x_tx_queue *txq = fp->sc->tx_queues[fp->index];
6549
6550         if (!txq) {
6551                 PMD_TX_LOG(ERR, "ERROR: TX queue is NULL");
6552                 return;
6553         }
6554         txq_init->dscr_map = (rte_iova_t)txq->tx_ring_phys_addr;
6555         txq_init->sb_cq_index = HC_INDEX_ETH_FIRST_TX_CQ_CONS + cos;
6556         txq_init->traffic_type = LLFC_TRAFFIC_TYPE_NW;
6557         txq_init->fw_sb_id = fp->fw_sb_id;
6558
6559         /*
6560          * set the TSS leading client id for TX classfication to the
6561          * leading RSS client id
6562          */
6563         txq_init->tss_leading_cl_id = BNX2X_FP(sc, 0, cl_id);
6564 }
6565
6566 /*
6567  * This function performs 2 steps in a queue state machine:
6568  *   1) RESET->INIT
6569  *   2) INIT->SETUP
6570  */
6571 static int
6572 bnx2x_setup_queue(struct bnx2x_softc *sc, struct bnx2x_fastpath *fp, uint8_t leading)
6573 {
6574         struct ecore_queue_state_params q_params = { NULL };
6575         struct ecore_queue_setup_params *setup_params = &q_params.params.setup;
6576         int rc;
6577
6578         PMD_DRV_LOG(DEBUG, sc, "setting up queue %d", fp->index);
6579
6580         bnx2x_ack_sb(sc, fp->igu_sb_id, USTORM_ID, 0, IGU_INT_ENABLE, 0);
6581
6582         q_params.q_obj = &BNX2X_SP_OBJ(sc, fp).q_obj;
6583
6584         /* we want to wait for completion in this context */
6585         bnx2x_set_bit(RAMROD_COMP_WAIT, &q_params.ramrod_flags);
6586
6587         /* prepare the INIT parameters */
6588         bnx2x_pf_q_prep_init(sc, fp, &q_params.params.init);
6589
6590         /* Set the command */
6591         q_params.cmd = ECORE_Q_CMD_INIT;
6592
6593         /* Change the state to INIT */
6594         rc = ecore_queue_state_change(sc, &q_params);
6595         if (rc) {
6596                 PMD_DRV_LOG(NOTICE, sc, "Queue(%d) INIT failed", fp->index);
6597                 return rc;
6598         }
6599
6600         PMD_DRV_LOG(DEBUG, sc, "init complete");
6601
6602         /* now move the Queue to the SETUP state */
6603         memset(setup_params, 0, sizeof(*setup_params));
6604
6605         /* set Queue flags */
6606         setup_params->flags = bnx2x_get_q_flags(sc, leading);
6607
6608         /* set general SETUP parameters */
6609         bnx2x_pf_q_prep_general(sc, fp, &setup_params->gen_params,
6610                               FIRST_TX_COS_INDEX);
6611
6612         bnx2x_pf_rx_q_prep(sc, fp,
6613                          &setup_params->pause_params,
6614                          &setup_params->rxq_params);
6615
6616         bnx2x_pf_tx_q_prep(sc, fp, &setup_params->txq_params, FIRST_TX_COS_INDEX);
6617
6618         /* Set the command */
6619         q_params.cmd = ECORE_Q_CMD_SETUP;
6620
6621         /* change the state to SETUP */
6622         rc = ecore_queue_state_change(sc, &q_params);
6623         if (rc) {
6624                 PMD_DRV_LOG(NOTICE, sc, "Queue(%d) SETUP failed", fp->index);
6625                 return rc;
6626         }
6627
6628         return rc;
6629 }
6630
6631 static int bnx2x_setup_leading(struct bnx2x_softc *sc)
6632 {
6633         if (IS_PF(sc))
6634                 return bnx2x_setup_queue(sc, &sc->fp[0], TRUE);
6635         else                    /* VF */
6636                 return bnx2x_vf_setup_queue(sc, &sc->fp[0], TRUE);
6637 }
6638
6639 static int
6640 bnx2x_config_rss_pf(struct bnx2x_softc *sc, struct ecore_rss_config_obj *rss_obj,
6641                   uint8_t config_hash)
6642 {
6643         struct ecore_config_rss_params params = { NULL };
6644         uint32_t i;
6645
6646         /*
6647          * Although RSS is meaningless when there is a single HW queue we
6648          * still need it enabled in order to have HW Rx hash generated.
6649          */
6650
6651         params.rss_obj = rss_obj;
6652
6653         bnx2x_set_bit(RAMROD_COMP_WAIT, &params.ramrod_flags);
6654
6655         bnx2x_set_bit(ECORE_RSS_MODE_REGULAR, &params.rss_flags);
6656
6657         /* RSS configuration */
6658         bnx2x_set_bit(ECORE_RSS_IPV4, &params.rss_flags);
6659         bnx2x_set_bit(ECORE_RSS_IPV4_TCP, &params.rss_flags);
6660         bnx2x_set_bit(ECORE_RSS_IPV6, &params.rss_flags);
6661         bnx2x_set_bit(ECORE_RSS_IPV6_TCP, &params.rss_flags);
6662         if (rss_obj->udp_rss_v4) {
6663                 bnx2x_set_bit(ECORE_RSS_IPV4_UDP, &params.rss_flags);
6664         }
6665         if (rss_obj->udp_rss_v6) {
6666                 bnx2x_set_bit(ECORE_RSS_IPV6_UDP, &params.rss_flags);
6667         }
6668
6669         /* Hash bits */
6670         params.rss_result_mask = MULTI_MASK;
6671
6672         rte_memcpy(params.ind_table, rss_obj->ind_table,
6673                          sizeof(params.ind_table));
6674
6675         if (config_hash) {
6676 /* RSS keys */
6677                 for (i = 0; i < sizeof(params.rss_key) / 4; i++) {
6678                         params.rss_key[i] = (uint32_t) rte_rand();
6679                 }
6680
6681                 bnx2x_set_bit(ECORE_RSS_SET_SRCH, &params.rss_flags);
6682         }
6683
6684         if (IS_PF(sc))
6685                 return ecore_config_rss(sc, &params);
6686         else
6687                 return bnx2x_vf_config_rss(sc, &params);
6688 }
6689
6690 static int bnx2x_config_rss_eth(struct bnx2x_softc *sc, uint8_t config_hash)
6691 {
6692         return bnx2x_config_rss_pf(sc, &sc->rss_conf_obj, config_hash);
6693 }
6694
6695 static int bnx2x_init_rss_pf(struct bnx2x_softc *sc)
6696 {
6697         uint8_t num_eth_queues = BNX2X_NUM_ETH_QUEUES(sc);
6698         uint32_t i;
6699
6700         /*
6701          * Prepare the initial contents of the indirection table if
6702          * RSS is enabled
6703          */
6704         for (i = 0; i < sizeof(sc->rss_conf_obj.ind_table); i++) {
6705                 sc->rss_conf_obj.ind_table[i] =
6706                     (sc->fp->cl_id + (i % num_eth_queues));
6707         }
6708
6709         if (sc->udp_rss) {
6710                 sc->rss_conf_obj.udp_rss_v4 = sc->rss_conf_obj.udp_rss_v6 = 1;
6711         }
6712
6713         /*
6714          * For 57711 SEARCHER configuration (rss_keys) is
6715          * per-port, so if explicit configuration is needed, do it only
6716          * for a PMF.
6717          *
6718          * For 57712 and newer it's a per-function configuration.
6719          */
6720         return bnx2x_config_rss_eth(sc, sc->port.pmf || !CHIP_IS_E1x(sc));
6721 }
6722
6723 static int
6724 bnx2x_set_mac_one(struct bnx2x_softc *sc, uint8_t * mac,
6725                 struct ecore_vlan_mac_obj *obj, uint8_t set, int mac_type,
6726                 unsigned long *ramrod_flags)
6727 {
6728         struct ecore_vlan_mac_ramrod_params ramrod_param;
6729         int rc;
6730
6731         memset(&ramrod_param, 0, sizeof(ramrod_param));
6732
6733         /* fill in general parameters */
6734         ramrod_param.vlan_mac_obj = obj;
6735         ramrod_param.ramrod_flags = *ramrod_flags;
6736
6737         /* fill a user request section if needed */
6738         if (!bnx2x_test_bit(RAMROD_CONT, ramrod_flags)) {
6739                 rte_memcpy(ramrod_param.user_req.u.mac.mac, mac,
6740                                  ETH_ALEN);
6741
6742                 bnx2x_set_bit(mac_type, &ramrod_param.user_req.vlan_mac_flags);
6743
6744 /* Set the command: ADD or DEL */
6745                 ramrod_param.user_req.cmd = (set) ? ECORE_VLAN_MAC_ADD :
6746                     ECORE_VLAN_MAC_DEL;
6747         }
6748
6749         rc = ecore_config_vlan_mac(sc, &ramrod_param);
6750
6751         if (rc == ECORE_EXISTS) {
6752                 PMD_DRV_LOG(INFO, sc, "Failed to schedule ADD operations (EEXIST)");
6753 /* do not treat adding same MAC as error */
6754                 rc = 0;
6755         } else if (rc < 0) {
6756                 PMD_DRV_LOG(ERR, sc,
6757                             "%s MAC failed (%d)", (set ? "Set" : "Delete"), rc);
6758         }
6759
6760         return rc;
6761 }
6762
6763 static int bnx2x_set_eth_mac(struct bnx2x_softc *sc, uint8_t set)
6764 {
6765         unsigned long ramrod_flags = 0;
6766
6767         PMD_DRV_LOG(DEBUG, sc, "Adding Ethernet MAC");
6768
6769         bnx2x_set_bit(RAMROD_COMP_WAIT, &ramrod_flags);
6770
6771         /* Eth MAC is set on RSS leading client (fp[0]) */
6772         return bnx2x_set_mac_one(sc, sc->link_params.mac_addr,
6773                                &sc->sp_objs->mac_obj,
6774                                set, ECORE_ETH_MAC, &ramrod_flags);
6775 }
6776
6777 static int bnx2x_get_cur_phy_idx(struct bnx2x_softc *sc)
6778 {
6779         uint32_t sel_phy_idx = 0;
6780
6781         if (sc->link_params.num_phys <= 1) {
6782                 return ELINK_INT_PHY;
6783         }
6784
6785         if (sc->link_vars.link_up) {
6786                 sel_phy_idx = ELINK_EXT_PHY1;
6787 /* In case link is SERDES, check if the ELINK_EXT_PHY2 is the one */
6788                 if ((sc->link_vars.link_status & LINK_STATUS_SERDES_LINK) &&
6789                     (sc->link_params.phy[ELINK_EXT_PHY2].supported &
6790                      ELINK_SUPPORTED_FIBRE))
6791                         sel_phy_idx = ELINK_EXT_PHY2;
6792         } else {
6793                 switch (elink_phy_selection(&sc->link_params)) {
6794                 case PORT_HW_CFG_PHY_SELECTION_HARDWARE_DEFAULT:
6795                 case PORT_HW_CFG_PHY_SELECTION_FIRST_PHY:
6796                 case PORT_HW_CFG_PHY_SELECTION_FIRST_PHY_PRIORITY:
6797                         sel_phy_idx = ELINK_EXT_PHY1;
6798                         break;
6799                 case PORT_HW_CFG_PHY_SELECTION_SECOND_PHY:
6800                 case PORT_HW_CFG_PHY_SELECTION_SECOND_PHY_PRIORITY:
6801                         sel_phy_idx = ELINK_EXT_PHY2;
6802                         break;
6803                 }
6804         }
6805
6806         return sel_phy_idx;
6807 }
6808
6809 static int bnx2x_get_link_cfg_idx(struct bnx2x_softc *sc)
6810 {
6811         uint32_t sel_phy_idx = bnx2x_get_cur_phy_idx(sc);
6812
6813         /*
6814          * The selected activated PHY is always after swapping (in case PHY
6815          * swapping is enabled). So when swapping is enabled, we need to reverse
6816          * the configuration
6817          */
6818
6819         if (sc->link_params.multi_phy_config & PORT_HW_CFG_PHY_SWAPPED_ENABLED) {
6820                 if (sel_phy_idx == ELINK_EXT_PHY1)
6821                         sel_phy_idx = ELINK_EXT_PHY2;
6822                 else if (sel_phy_idx == ELINK_EXT_PHY2)
6823                         sel_phy_idx = ELINK_EXT_PHY1;
6824         }
6825
6826         return ELINK_LINK_CONFIG_IDX(sel_phy_idx);
6827 }
6828
6829 static void bnx2x_set_requested_fc(struct bnx2x_softc *sc)
6830 {
6831         /*
6832          * Initialize link parameters structure variables
6833          * It is recommended to turn off RX FC for jumbo frames
6834          * for better performance
6835          */
6836         if (CHIP_IS_E1x(sc) && (sc->mtu > 5000)) {
6837                 sc->link_params.req_fc_auto_adv = ELINK_FLOW_CTRL_TX;
6838         } else {
6839                 sc->link_params.req_fc_auto_adv = ELINK_FLOW_CTRL_BOTH;
6840         }
6841 }
6842
6843 static void bnx2x_calc_fc_adv(struct bnx2x_softc *sc)
6844 {
6845         uint8_t cfg_idx = bnx2x_get_link_cfg_idx(sc);
6846         switch (sc->link_vars.ieee_fc &
6847                 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_MASK) {
6848         case MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_NONE:
6849         default:
6850                 sc->port.advertising[cfg_idx] &= ~(ADVERTISED_Asym_Pause |
6851                                                    ADVERTISED_Pause);
6852                 break;
6853
6854         case MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH:
6855                 sc->port.advertising[cfg_idx] |= (ADVERTISED_Asym_Pause |
6856                                                   ADVERTISED_Pause);
6857                 break;
6858
6859         case MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC:
6860                 sc->port.advertising[cfg_idx] |= ADVERTISED_Asym_Pause;
6861                 break;
6862         }
6863 }
6864
6865 static uint16_t bnx2x_get_mf_speed(struct bnx2x_softc *sc)
6866 {
6867         uint16_t line_speed = sc->link_vars.line_speed;
6868         if (IS_MF(sc)) {
6869                 uint16_t maxCfg = bnx2x_extract_max_cfg(sc,
6870                                                       sc->devinfo.
6871                                                       mf_info.mf_config[SC_VN
6872                                                                         (sc)]);
6873
6874 /* calculate the current MAX line speed limit for the MF devices */
6875                 if (IS_MF_SI(sc)) {
6876                         line_speed = (line_speed * maxCfg) / 100;
6877                 } else {        /* SD mode */
6878                         uint16_t vn_max_rate = maxCfg * 100;
6879
6880                         if (vn_max_rate < line_speed) {
6881                                 line_speed = vn_max_rate;
6882                         }
6883                 }
6884         }
6885
6886         return line_speed;
6887 }
6888
6889 static void
6890 bnx2x_fill_report_data(struct bnx2x_softc *sc, struct bnx2x_link_report_data *data)
6891 {
6892         uint16_t line_speed = bnx2x_get_mf_speed(sc);
6893
6894         memset(data, 0, sizeof(*data));
6895
6896         /* fill the report data with the effective line speed */
6897         data->line_speed = line_speed;
6898
6899         /* Link is down */
6900         if (!sc->link_vars.link_up || (sc->flags & BNX2X_MF_FUNC_DIS)) {
6901                 bnx2x_set_bit(BNX2X_LINK_REPORT_LINK_DOWN,
6902                             &data->link_report_flags);
6903         }
6904
6905         /* Full DUPLEX */
6906         if (sc->link_vars.duplex == DUPLEX_FULL) {
6907                 bnx2x_set_bit(BNX2X_LINK_REPORT_FULL_DUPLEX,
6908                             &data->link_report_flags);
6909         }
6910
6911         /* Rx Flow Control is ON */
6912         if (sc->link_vars.flow_ctrl & ELINK_FLOW_CTRL_RX) {
6913                 bnx2x_set_bit(BNX2X_LINK_REPORT_RX_FC_ON, &data->link_report_flags);
6914         }
6915
6916         /* Tx Flow Control is ON */
6917         if (sc->link_vars.flow_ctrl & ELINK_FLOW_CTRL_TX) {
6918                 bnx2x_set_bit(BNX2X_LINK_REPORT_TX_FC_ON, &data->link_report_flags);
6919         }
6920 }
6921
6922 /* report link status to OS, should be called under phy_lock */
6923 static void bnx2x_link_report_locked(struct bnx2x_softc *sc)
6924 {
6925         struct bnx2x_link_report_data cur_data;
6926
6927         /* reread mf_cfg */
6928         if (IS_PF(sc)) {
6929                 bnx2x_read_mf_cfg(sc);
6930         }
6931
6932         /* Read the current link report info */
6933         bnx2x_fill_report_data(sc, &cur_data);
6934
6935         /* Don't report link down or exactly the same link status twice */
6936         if (!memcmp(&cur_data, &sc->last_reported_link, sizeof(cur_data)) ||
6937             (bnx2x_test_bit(BNX2X_LINK_REPORT_LINK_DOWN,
6938                           &sc->last_reported_link.link_report_flags) &&
6939              bnx2x_test_bit(BNX2X_LINK_REPORT_LINK_DOWN,
6940                           &cur_data.link_report_flags))) {
6941                 return;
6942         }
6943
6944         ELINK_DEBUG_P2(sc, "Change in link status : cur_data = %lx, last_reported_link = %lx",
6945                        cur_data.link_report_flags,
6946                        sc->last_reported_link.link_report_flags);
6947
6948         sc->link_cnt++;
6949
6950         ELINK_DEBUG_P1(sc, "link status change count = %x", sc->link_cnt);
6951         /* report new link params and remember the state for the next time */
6952         rte_memcpy(&sc->last_reported_link, &cur_data, sizeof(cur_data));
6953
6954         if (bnx2x_test_bit(BNX2X_LINK_REPORT_LINK_DOWN,
6955                          &cur_data.link_report_flags)) {
6956                 ELINK_DEBUG_P0(sc, "NIC Link is Down");
6957         } else {
6958                 __rte_unused const char *duplex;
6959                 __rte_unused const char *flow;
6960
6961                 if (bnx2x_test_and_clear_bit(BNX2X_LINK_REPORT_FULL_DUPLEX,
6962                                            &cur_data.link_report_flags)) {
6963                         duplex = "full";
6964                                 ELINK_DEBUG_P0(sc, "link set to full duplex");
6965                 } else {
6966                         duplex = "half";
6967                                 ELINK_DEBUG_P0(sc, "link set to half duplex");
6968                 }
6969
6970 /*
6971  * Handle the FC at the end so that only these flags would be
6972  * possibly set. This way we may easily check if there is no FC
6973  * enabled.
6974  */
6975                 if (cur_data.link_report_flags) {
6976                         if (bnx2x_test_bit(BNX2X_LINK_REPORT_RX_FC_ON,
6977                                          &cur_data.link_report_flags) &&
6978                             bnx2x_test_bit(BNX2X_LINK_REPORT_TX_FC_ON,
6979                                          &cur_data.link_report_flags)) {
6980                                 flow = "ON - receive & transmit";
6981                         } else if (bnx2x_test_bit(BNX2X_LINK_REPORT_RX_FC_ON,
6982                                                 &cur_data.link_report_flags) &&
6983                                    !bnx2x_test_bit(BNX2X_LINK_REPORT_TX_FC_ON,
6984                                                  &cur_data.link_report_flags)) {
6985                                 flow = "ON - receive";
6986                         } else if (!bnx2x_test_bit(BNX2X_LINK_REPORT_RX_FC_ON,
6987                                                  &cur_data.link_report_flags) &&
6988                                    bnx2x_test_bit(BNX2X_LINK_REPORT_TX_FC_ON,
6989                                                 &cur_data.link_report_flags)) {
6990                                 flow = "ON - transmit";
6991                         } else {
6992                                 flow = "none";  /* possible? */
6993                         }
6994                 } else {
6995                         flow = "none";
6996                 }
6997
6998                 PMD_DRV_LOG(INFO, sc,
6999                             "NIC Link is Up, %d Mbps %s duplex, Flow control: %s",
7000                             cur_data.line_speed, duplex, flow);
7001         }
7002 }
7003
7004 static void
7005 bnx2x_link_report(struct bnx2x_softc *sc)
7006 {
7007         bnx2x_acquire_phy_lock(sc);
7008         bnx2x_link_report_locked(sc);
7009         bnx2x_release_phy_lock(sc);
7010 }
7011
7012 void bnx2x_link_status_update(struct bnx2x_softc *sc)
7013 {
7014         if (sc->state != BNX2X_STATE_OPEN) {
7015                 return;
7016         }
7017
7018         if (IS_PF(sc) && !CHIP_REV_IS_SLOW(sc)) {
7019                 elink_link_status_update(&sc->link_params, &sc->link_vars);
7020         } else {
7021                 sc->port.supported[0] |= (ELINK_SUPPORTED_10baseT_Half |
7022                                           ELINK_SUPPORTED_10baseT_Full |
7023                                           ELINK_SUPPORTED_100baseT_Half |
7024                                           ELINK_SUPPORTED_100baseT_Full |
7025                                           ELINK_SUPPORTED_1000baseT_Full |
7026                                           ELINK_SUPPORTED_2500baseX_Full |
7027                                           ELINK_SUPPORTED_10000baseT_Full |
7028                                           ELINK_SUPPORTED_TP |
7029                                           ELINK_SUPPORTED_FIBRE |
7030                                           ELINK_SUPPORTED_Autoneg |
7031                                           ELINK_SUPPORTED_Pause |
7032                                           ELINK_SUPPORTED_Asym_Pause);
7033                 sc->port.advertising[0] = sc->port.supported[0];
7034
7035                 sc->link_params.sc = sc;
7036                 sc->link_params.port = SC_PORT(sc);
7037                 sc->link_params.req_duplex[0] = DUPLEX_FULL;
7038                 sc->link_params.req_flow_ctrl[0] = ELINK_FLOW_CTRL_NONE;
7039                 sc->link_params.req_line_speed[0] = SPEED_10000;
7040                 sc->link_params.speed_cap_mask[0] = 0x7f0000;
7041                 sc->link_params.switch_cfg = ELINK_SWITCH_CFG_10G;
7042
7043                 if (CHIP_REV_IS_FPGA(sc)) {
7044                         sc->link_vars.mac_type = ELINK_MAC_TYPE_EMAC;
7045                         sc->link_vars.line_speed = ELINK_SPEED_1000;
7046                         sc->link_vars.link_status = (LINK_STATUS_LINK_UP |
7047                                                      LINK_STATUS_SPEED_AND_DUPLEX_1000TFD);
7048                 } else {
7049                         sc->link_vars.mac_type = ELINK_MAC_TYPE_BMAC;
7050                         sc->link_vars.line_speed = ELINK_SPEED_10000;
7051                         sc->link_vars.link_status = (LINK_STATUS_LINK_UP |
7052                                                      LINK_STATUS_SPEED_AND_DUPLEX_10GTFD);
7053                 }
7054
7055                 sc->link_vars.link_up = 1;
7056
7057                 sc->link_vars.duplex = DUPLEX_FULL;
7058                 sc->link_vars.flow_ctrl = ELINK_FLOW_CTRL_NONE;
7059
7060                 if (IS_PF(sc)) {
7061                         REG_WR(sc,
7062                                NIG_REG_EGRESS_DRAIN0_MODE +
7063                                sc->link_params.port * 4, 0);
7064                         bnx2x_stats_handle(sc, STATS_EVENT_LINK_UP);
7065                         bnx2x_link_report(sc);
7066                 }
7067         }
7068
7069         if (IS_PF(sc)) {
7070                 if (sc->link_vars.link_up) {
7071                         bnx2x_stats_handle(sc, STATS_EVENT_LINK_UP);
7072                 } else {
7073                         bnx2x_stats_handle(sc, STATS_EVENT_STOP);
7074                 }
7075                 bnx2x_link_report(sc);
7076         } else {
7077                 bnx2x_link_report_locked(sc);
7078                 bnx2x_stats_handle(sc, STATS_EVENT_LINK_UP);
7079         }
7080 }
7081
7082 static int bnx2x_initial_phy_init(struct bnx2x_softc *sc, int load_mode)
7083 {
7084         int rc, cfg_idx = bnx2x_get_link_cfg_idx(sc);
7085         uint16_t req_line_speed = sc->link_params.req_line_speed[cfg_idx];
7086         struct elink_params *lp = &sc->link_params;
7087
7088         bnx2x_set_requested_fc(sc);
7089
7090         bnx2x_acquire_phy_lock(sc);
7091
7092         if (load_mode == LOAD_DIAG) {
7093                 lp->loopback_mode = ELINK_LOOPBACK_XGXS;
7094 /* Prefer doing PHY loopback at 10G speed, if possible */
7095                 if (lp->req_line_speed[cfg_idx] < ELINK_SPEED_10000) {
7096                         if (lp->speed_cap_mask[cfg_idx] &
7097                             PORT_HW_CFG_SPEED_CAPABILITY_D0_10G) {
7098                                 lp->req_line_speed[cfg_idx] = ELINK_SPEED_10000;
7099                         } else {
7100                                 lp->req_line_speed[cfg_idx] = ELINK_SPEED_1000;
7101                         }
7102                 }
7103         }
7104
7105         if (load_mode == LOAD_LOOPBACK_EXT) {
7106                 lp->loopback_mode = ELINK_LOOPBACK_EXT;
7107         }
7108
7109         rc = elink_phy_init(&sc->link_params, &sc->link_vars);
7110
7111         bnx2x_release_phy_lock(sc);
7112
7113         bnx2x_calc_fc_adv(sc);
7114
7115         if (sc->link_vars.link_up) {
7116                 bnx2x_stats_handle(sc, STATS_EVENT_LINK_UP);
7117                 bnx2x_link_report(sc);
7118         }
7119
7120         sc->link_params.req_line_speed[cfg_idx] = req_line_speed;
7121         return rc;
7122 }
7123
7124 /* update flags in shmem */
7125 static void
7126 bnx2x_update_drv_flags(struct bnx2x_softc *sc, uint32_t flags, uint32_t set)
7127 {
7128         uint32_t drv_flags;
7129
7130         if (SHMEM2_HAS(sc, drv_flags)) {
7131                 bnx2x_acquire_hw_lock(sc, HW_LOCK_RESOURCE_DRV_FLAGS);
7132                 drv_flags = SHMEM2_RD(sc, drv_flags);
7133
7134                 if (set) {
7135                         drv_flags |= flags;
7136                 } else {
7137                         drv_flags &= ~flags;
7138                 }
7139
7140                 SHMEM2_WR(sc, drv_flags, drv_flags);
7141
7142                 bnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_DRV_FLAGS);
7143         }
7144 }
7145
7146 /* periodic timer callout routine, only runs when the interface is up */
7147 void bnx2x_periodic_callout(struct bnx2x_softc *sc)
7148 {
7149         if ((sc->state != BNX2X_STATE_OPEN) ||
7150             (atomic_load_acq_long(&sc->periodic_flags) == PERIODIC_STOP)) {
7151                 PMD_DRV_LOG(DEBUG, sc, "periodic callout exit (state=0x%x)",
7152                             sc->state);
7153                 return;
7154         }
7155         if (!CHIP_REV_IS_SLOW(sc)) {
7156 /*
7157  * This barrier is needed to ensure the ordering between the writing
7158  * to the sc->port.pmf in the bnx2x_nic_load() or bnx2x_pmf_update() and
7159  * the reading here.
7160  */
7161                 mb();
7162                 if (sc->port.pmf) {
7163                         bnx2x_acquire_phy_lock(sc);
7164                         elink_period_func(&sc->link_params, &sc->link_vars);
7165                         bnx2x_release_phy_lock(sc);
7166                 }
7167         }
7168 #ifdef BNX2X_PULSE
7169         if (IS_PF(sc) && !BNX2X_NOMCP(sc)) {
7170                 int mb_idx = SC_FW_MB_IDX(sc);
7171                 uint32_t drv_pulse;
7172                 uint32_t mcp_pulse;
7173
7174                 ++sc->fw_drv_pulse_wr_seq;
7175                 sc->fw_drv_pulse_wr_seq &= DRV_PULSE_SEQ_MASK;
7176
7177                 drv_pulse = sc->fw_drv_pulse_wr_seq;
7178                 bnx2x_drv_pulse(sc);
7179
7180                 mcp_pulse = (SHMEM_RD(sc, func_mb[mb_idx].mcp_pulse_mb) &
7181                              MCP_PULSE_SEQ_MASK);
7182
7183 /*
7184  * The delta between driver pulse and mcp response should
7185  * be 1 (before mcp response) or 0 (after mcp response).
7186  */
7187                 if ((drv_pulse != mcp_pulse) &&
7188                     (drv_pulse != ((mcp_pulse + 1) & MCP_PULSE_SEQ_MASK))) {
7189                         /* someone lost a heartbeat... */
7190                         PMD_DRV_LOG(ERR, sc,
7191                                     "drv_pulse (0x%x) != mcp_pulse (0x%x)",
7192                                     drv_pulse, mcp_pulse);
7193                 }
7194         }
7195 #endif
7196 }
7197
7198 /* start the controller */
7199 static __rte_noinline
7200 int bnx2x_nic_load(struct bnx2x_softc *sc)
7201 {
7202         uint32_t val;
7203         uint32_t load_code = 0;
7204         int i, rc = 0;
7205
7206         PMD_INIT_FUNC_TRACE(sc);
7207
7208         sc->state = BNX2X_STATE_OPENING_WAITING_LOAD;
7209
7210         if (IS_PF(sc)) {
7211 /* must be called before memory allocation and HW init */
7212                 bnx2x_ilt_set_info(sc);
7213         }
7214
7215         bnx2x_set_fp_rx_buf_size(sc);
7216
7217         if (IS_PF(sc)) {
7218                 if (bnx2x_alloc_mem(sc) != 0) {
7219                         sc->state = BNX2X_STATE_CLOSED;
7220                         rc = -ENOMEM;
7221                         goto bnx2x_nic_load_error0;
7222                 }
7223         }
7224
7225         if (bnx2x_alloc_fw_stats_mem(sc) != 0) {
7226                 sc->state = BNX2X_STATE_CLOSED;
7227                 rc = -ENOMEM;
7228                 goto bnx2x_nic_load_error0;
7229         }
7230
7231         if (IS_VF(sc)) {
7232                 rc = bnx2x_vf_init(sc);
7233                 if (rc) {
7234                         sc->state = BNX2X_STATE_ERROR;
7235                         goto bnx2x_nic_load_error0;
7236                 }
7237         }
7238
7239         if (IS_PF(sc)) {
7240 /* set pf load just before approaching the MCP */
7241                 bnx2x_set_pf_load(sc);
7242
7243 /* if MCP exists send load request and analyze response */
7244                 if (!BNX2X_NOMCP(sc)) {
7245                         /* attempt to load pf */
7246                         if (bnx2x_nic_load_request(sc, &load_code) != 0) {
7247                                 sc->state = BNX2X_STATE_CLOSED;
7248                                 rc = -ENXIO;
7249                                 goto bnx2x_nic_load_error1;
7250                         }
7251
7252                         /* what did the MCP say? */
7253                         if (bnx2x_nic_load_analyze_req(sc, load_code) != 0) {
7254                                 bnx2x_fw_command(sc, DRV_MSG_CODE_LOAD_DONE, 0);
7255                                 sc->state = BNX2X_STATE_CLOSED;
7256                                 rc = -ENXIO;
7257                                 goto bnx2x_nic_load_error2;
7258                         }
7259                 } else {
7260                         PMD_DRV_LOG(INFO, sc, "Device has no MCP!");
7261                         load_code = bnx2x_nic_load_no_mcp(sc);
7262                 }
7263
7264 /* mark PMF if applicable */
7265                 bnx2x_nic_load_pmf(sc, load_code);
7266
7267 /* Init Function state controlling object */
7268                 bnx2x_init_func_obj(sc);
7269
7270 /* Initialize HW */
7271                 if (bnx2x_init_hw(sc, load_code) != 0) {
7272                         PMD_DRV_LOG(NOTICE, sc, "HW init failed");
7273                         bnx2x_fw_command(sc, DRV_MSG_CODE_LOAD_DONE, 0);
7274                         sc->state = BNX2X_STATE_CLOSED;
7275                         rc = -ENXIO;
7276                         goto bnx2x_nic_load_error2;
7277                 }
7278         }
7279
7280         bnx2x_nic_init(sc, load_code);
7281
7282         /* Init per-function objects */
7283         if (IS_PF(sc)) {
7284                 bnx2x_init_objs(sc);
7285
7286 /* set AFEX default VLAN tag to an invalid value */
7287                 sc->devinfo.mf_info.afex_def_vlan_tag = -1;
7288
7289                 sc->state = BNX2X_STATE_OPENING_WAITING_PORT;
7290                 rc = bnx2x_func_start(sc);
7291                 if (rc) {
7292                         PMD_DRV_LOG(NOTICE, sc, "Function start failed!");
7293                         bnx2x_fw_command(sc, DRV_MSG_CODE_LOAD_DONE, 0);
7294                         sc->state = BNX2X_STATE_ERROR;
7295                         goto bnx2x_nic_load_error3;
7296                 }
7297
7298 /* send LOAD_DONE command to MCP */
7299                 if (!BNX2X_NOMCP(sc)) {
7300                         load_code =
7301                             bnx2x_fw_command(sc, DRV_MSG_CODE_LOAD_DONE, 0);
7302                         if (!load_code) {
7303                                 PMD_DRV_LOG(NOTICE, sc,
7304                                             "MCP response failure, aborting");
7305                                 sc->state = BNX2X_STATE_ERROR;
7306                                 rc = -ENXIO;
7307                                 goto bnx2x_nic_load_error3;
7308                         }
7309                 }
7310         }
7311
7312         rc = bnx2x_setup_leading(sc);
7313         if (rc) {
7314                 PMD_DRV_LOG(NOTICE, sc, "Setup leading failed!");
7315                 sc->state = BNX2X_STATE_ERROR;
7316                 goto bnx2x_nic_load_error3;
7317         }
7318
7319         FOR_EACH_NONDEFAULT_ETH_QUEUE(sc, i) {
7320                 if (IS_PF(sc))
7321                         rc = bnx2x_setup_queue(sc, &sc->fp[i], FALSE);
7322                 else            /* IS_VF(sc) */
7323                         rc = bnx2x_vf_setup_queue(sc, &sc->fp[i], FALSE);
7324
7325                 if (rc) {
7326                         PMD_DRV_LOG(NOTICE, sc, "Queue(%d) setup failed", i);
7327                         sc->state = BNX2X_STATE_ERROR;
7328                         goto bnx2x_nic_load_error3;
7329                 }
7330         }
7331
7332         rc = bnx2x_init_rss_pf(sc);
7333         if (rc) {
7334                 PMD_DRV_LOG(NOTICE, sc, "PF RSS init failed");
7335                 sc->state = BNX2X_STATE_ERROR;
7336                 goto bnx2x_nic_load_error3;
7337         }
7338
7339         /* now when Clients are configured we are ready to work */
7340         sc->state = BNX2X_STATE_OPEN;
7341
7342         /* Configure a ucast MAC */
7343         if (IS_PF(sc)) {
7344                 rc = bnx2x_set_eth_mac(sc, TRUE);
7345         } else {                /* IS_VF(sc) */
7346                 rc = bnx2x_vf_set_mac(sc, TRUE);
7347         }
7348
7349         if (rc) {
7350                 PMD_DRV_LOG(NOTICE, sc, "Setting Ethernet MAC failed");
7351                 sc->state = BNX2X_STATE_ERROR;
7352                 goto bnx2x_nic_load_error3;
7353         }
7354
7355         if (sc->port.pmf) {
7356                 rc = bnx2x_initial_phy_init(sc, LOAD_OPEN);
7357                 if (rc) {
7358                         sc->state = BNX2X_STATE_ERROR;
7359                         goto bnx2x_nic_load_error3;
7360                 }
7361         }
7362
7363         sc->link_params.feature_config_flags &=
7364             ~ELINK_FEATURE_CONFIG_BOOT_FROM_SAN;
7365
7366         /* start the Tx */
7367         switch (LOAD_OPEN) {
7368         case LOAD_NORMAL:
7369         case LOAD_OPEN:
7370                 break;
7371
7372         case LOAD_DIAG:
7373         case LOAD_LOOPBACK_EXT:
7374                 sc->state = BNX2X_STATE_DIAG;
7375                 break;
7376
7377         default:
7378                 break;
7379         }
7380
7381         if (sc->port.pmf) {
7382                 bnx2x_update_drv_flags(sc, 1 << DRV_FLAGS_PORT_MASK, 0);
7383         } else {
7384                 bnx2x_link_status_update(sc);
7385         }
7386
7387         if (IS_PF(sc) && SHMEM2_HAS(sc, drv_capabilities_flag)) {
7388 /* mark driver is loaded in shmem2 */
7389                 val = SHMEM2_RD(sc, drv_capabilities_flag[SC_FW_MB_IDX(sc)]);
7390                 SHMEM2_WR(sc, drv_capabilities_flag[SC_FW_MB_IDX(sc)],
7391                           (val |
7392                            DRV_FLAGS_CAPABILITIES_LOADED_SUPPORTED |
7393                            DRV_FLAGS_CAPABILITIES_LOADED_L2));
7394         }
7395
7396         /* start fast path */
7397         /* Initialize Rx filter */
7398         bnx2x_set_rx_mode(sc);
7399
7400         /* wait for all pending SP commands to complete */
7401         if (IS_PF(sc) && !bnx2x_wait_sp_comp(sc, ~0x0UL)) {
7402                 PMD_DRV_LOG(NOTICE, sc, "Timeout waiting for all SPs to complete!");
7403                 bnx2x_periodic_stop(sc);
7404                 bnx2x_nic_unload(sc, UNLOAD_CLOSE, FALSE);
7405                 return -ENXIO;
7406         }
7407
7408         PMD_DRV_LOG(DEBUG, sc, "NIC successfully loaded");
7409
7410         return 0;
7411
7412 bnx2x_nic_load_error3:
7413
7414         if (IS_PF(sc)) {
7415                 bnx2x_int_disable_sync(sc, 1);
7416
7417 /* clean out queued objects */
7418                 bnx2x_squeeze_objects(sc);
7419         }
7420
7421 bnx2x_nic_load_error2:
7422
7423         if (IS_PF(sc) && !BNX2X_NOMCP(sc)) {
7424                 bnx2x_fw_command(sc, DRV_MSG_CODE_UNLOAD_REQ_WOL_MCP, 0);
7425                 bnx2x_fw_command(sc, DRV_MSG_CODE_UNLOAD_DONE, 0);
7426         }
7427
7428         sc->port.pmf = 0;
7429
7430 bnx2x_nic_load_error1:
7431
7432         /* clear pf_load status, as it was already set */
7433         if (IS_PF(sc)) {
7434                 bnx2x_clear_pf_load(sc);
7435         }
7436
7437 bnx2x_nic_load_error0:
7438
7439         bnx2x_free_fw_stats_mem(sc);
7440         bnx2x_free_mem(sc);
7441
7442         return rc;
7443 }
7444
7445 /*
7446 * Handles controller initialization.
7447 */
7448 int bnx2x_init(struct bnx2x_softc *sc)
7449 {
7450         int other_engine = SC_PATH(sc) ? 0 : 1;
7451         uint8_t other_load_status, load_status;
7452         uint8_t global = FALSE;
7453         int rc;
7454
7455         /* Check if the driver is still running and bail out if it is. */
7456         if (sc->state != BNX2X_STATE_CLOSED) {
7457                 PMD_DRV_LOG(DEBUG, sc, "Init called while driver is running!");
7458                 rc = 0;
7459                 goto bnx2x_init_done;
7460         }
7461
7462         bnx2x_set_power_state(sc, PCI_PM_D0);
7463
7464         /*
7465          * If parity occurred during the unload, then attentions and/or
7466          * RECOVERY_IN_PROGRESS may still be set. If so we want the first function
7467          * loaded on the current engine to complete the recovery. Parity recovery
7468          * is only relevant for PF driver.
7469          */
7470         if (IS_PF(sc)) {
7471                 other_load_status = bnx2x_get_load_status(sc, other_engine);
7472                 load_status = bnx2x_get_load_status(sc, SC_PATH(sc));
7473
7474                 if (!bnx2x_reset_is_done(sc, SC_PATH(sc)) ||
7475                     bnx2x_chk_parity_attn(sc, &global, TRUE)) {
7476                         do {
7477                                 /*
7478                                  * If there are attentions and they are in global blocks, set
7479                                  * the GLOBAL_RESET bit regardless whether it will be this
7480                                  * function that will complete the recovery or not.
7481                                  */
7482                                 if (global) {
7483                                         bnx2x_set_reset_global(sc);
7484                                 }
7485
7486                                 /*
7487                                  * Only the first function on the current engine should try
7488                                  * to recover in open. In case of attentions in global blocks
7489                                  * only the first in the chip should try to recover.
7490                                  */
7491                                 if ((!load_status
7492                                      && (!global ||!other_load_status))
7493                                     && bnx2x_trylock_leader_lock(sc)
7494                                     && !bnx2x_leader_reset(sc)) {
7495                                         PMD_DRV_LOG(INFO, sc,
7496                                                     "Recovered during init");
7497                                         break;
7498                                 }
7499
7500                                 /* recovery has failed... */
7501                                 bnx2x_set_power_state(sc, PCI_PM_D3hot);
7502
7503                                 sc->recovery_state = BNX2X_RECOVERY_FAILED;
7504
7505                                 PMD_DRV_LOG(NOTICE, sc,
7506                                             "Recovery flow hasn't properly "
7507                                             "completed yet, try again later. "
7508                                             "If you still see this message after a "
7509                                             "few retries then power cycle is required.");
7510
7511                                 rc = -ENXIO;
7512                                 goto bnx2x_init_done;
7513                         } while (0);
7514                 }
7515         }
7516
7517         sc->recovery_state = BNX2X_RECOVERY_DONE;
7518
7519         rc = bnx2x_nic_load(sc);
7520
7521 bnx2x_init_done:
7522
7523         if (rc) {
7524                 PMD_DRV_LOG(NOTICE, sc, "Initialization failed, "
7525                             "stack notified driver is NOT running!");
7526         }
7527
7528         return rc;
7529 }
7530
7531 static void bnx2x_get_function_num(struct bnx2x_softc *sc)
7532 {
7533         uint32_t val = 0;
7534
7535         /*
7536          * Read the ME register to get the function number. The ME register
7537          * holds the relative-function number and absolute-function number. The
7538          * absolute-function number appears only in E2 and above. Before that
7539          * these bits always contained zero, therefore we cannot blindly use them.
7540          */
7541
7542         val = REG_RD(sc, BAR_ME_REGISTER);
7543
7544         sc->pfunc_rel =
7545             (uint8_t) ((val & ME_REG_PF_NUM) >> ME_REG_PF_NUM_SHIFT);
7546         sc->path_id =
7547             (uint8_t) ((val & ME_REG_ABS_PF_NUM) >> ME_REG_ABS_PF_NUM_SHIFT) &
7548             1;
7549
7550         if (CHIP_PORT_MODE(sc) == CHIP_4_PORT_MODE) {
7551                 sc->pfunc_abs = ((sc->pfunc_rel << 1) | sc->path_id);
7552         } else {
7553                 sc->pfunc_abs = (sc->pfunc_rel | sc->path_id);
7554         }
7555
7556         PMD_DRV_LOG(DEBUG, sc,
7557                     "Relative function %d, Absolute function %d, Path %d",
7558                     sc->pfunc_rel, sc->pfunc_abs, sc->path_id);
7559 }
7560
7561 static uint32_t bnx2x_get_shmem_mf_cfg_base(struct bnx2x_softc *sc)
7562 {
7563         uint32_t shmem2_size;
7564         uint32_t offset;
7565         uint32_t mf_cfg_offset_value;
7566
7567         /* Non 57712 */
7568         offset = (SHMEM_ADDR(sc, func_mb) +
7569                   (MAX_FUNC_NUM * sizeof(struct drv_func_mb)));
7570
7571         /* 57712 plus */
7572         if (sc->devinfo.shmem2_base != 0) {
7573                 shmem2_size = SHMEM2_RD(sc, size);
7574                 if (shmem2_size > offsetof(struct shmem2_region, mf_cfg_addr)) {
7575                         mf_cfg_offset_value = SHMEM2_RD(sc, mf_cfg_addr);
7576                         if (SHMEM_MF_CFG_ADDR_NONE != mf_cfg_offset_value) {
7577                                 offset = mf_cfg_offset_value;
7578                         }
7579                 }
7580         }
7581
7582         return offset;
7583 }
7584
7585 static uint32_t bnx2x_pcie_capability_read(struct bnx2x_softc *sc, int reg)
7586 {
7587         uint32_t ret;
7588         struct bnx2x_pci_cap *caps;
7589
7590         /* ensure PCIe capability is enabled */
7591         caps = pci_find_cap(sc, PCIY_EXPRESS, BNX2X_PCI_CAP);
7592         if (NULL != caps) {
7593                 PMD_DRV_LOG(DEBUG, sc, "Found PCIe capability: "
7594                             "id=0x%04X type=0x%04X addr=0x%08X",
7595                             caps->id, caps->type, caps->addr);
7596                 pci_read(sc, (caps->addr + reg), &ret, 2);
7597                 return ret;
7598         }
7599
7600         PMD_DRV_LOG(WARNING, sc, "PCIe capability NOT FOUND!!!");
7601
7602         return 0;
7603 }
7604
7605 static uint8_t bnx2x_is_pcie_pending(struct bnx2x_softc *sc)
7606 {
7607         return bnx2x_pcie_capability_read(sc, PCIR_EXPRESS_DEVICE_STA) &
7608                 PCIM_EXP_STA_TRANSACTION_PND;
7609 }
7610
7611 /*
7612 * Walk the PCI capabiites list for the device to find what features are
7613 * supported. These capabilites may be enabled/disabled by firmware so it's
7614 * best to walk the list rather than make assumptions.
7615 */
7616 static void bnx2x_probe_pci_caps(struct bnx2x_softc *sc)
7617 {
7618         PMD_INIT_FUNC_TRACE(sc);
7619
7620         struct bnx2x_pci_cap *caps;
7621         uint16_t link_status;
7622         int reg = 0;
7623
7624         /* check if PCI Power Management is enabled */
7625         caps = pci_find_cap(sc, PCIY_PMG, BNX2X_PCI_CAP);
7626         if (NULL != caps) {
7627                 PMD_DRV_LOG(DEBUG, sc, "Found PM capability: "
7628                             "id=0x%04X type=0x%04X addr=0x%08X",
7629                             caps->id, caps->type, caps->addr);
7630
7631                 sc->devinfo.pcie_cap_flags |= BNX2X_PM_CAPABLE_FLAG;
7632                 sc->devinfo.pcie_pm_cap_reg = caps->addr;
7633         }
7634
7635         link_status = bnx2x_pcie_capability_read(sc, PCIR_EXPRESS_LINK_STA);
7636
7637         sc->devinfo.pcie_link_speed = (link_status & PCIM_LINK_STA_SPEED);
7638         sc->devinfo.pcie_link_width =
7639             ((link_status & PCIM_LINK_STA_WIDTH) >> 4);
7640
7641         PMD_DRV_LOG(DEBUG, sc, "PCIe link speed=%d width=%d",
7642                     sc->devinfo.pcie_link_speed, sc->devinfo.pcie_link_width);
7643
7644         sc->devinfo.pcie_cap_flags |= BNX2X_PCIE_CAPABLE_FLAG;
7645
7646         /* check if MSI capability is enabled */
7647         caps = pci_find_cap(sc, PCIY_MSI, BNX2X_PCI_CAP);
7648         if (NULL != caps) {
7649                 PMD_DRV_LOG(DEBUG, sc, "Found MSI capability at 0x%04x", reg);
7650
7651                 sc->devinfo.pcie_cap_flags |= BNX2X_MSI_CAPABLE_FLAG;
7652                 sc->devinfo.pcie_msi_cap_reg = caps->addr;
7653         }
7654
7655         /* check if MSI-X capability is enabled */
7656         caps = pci_find_cap(sc, PCIY_MSIX, BNX2X_PCI_CAP);
7657         if (NULL != caps) {
7658                 PMD_DRV_LOG(DEBUG, sc, "Found MSI-X capability at 0x%04x", reg);
7659
7660                 sc->devinfo.pcie_cap_flags |= BNX2X_MSIX_CAPABLE_FLAG;
7661                 sc->devinfo.pcie_msix_cap_reg = caps->addr;
7662         }
7663 }
7664
7665 static int bnx2x_get_shmem_mf_cfg_info_sd(struct bnx2x_softc *sc)
7666 {
7667         struct bnx2x_mf_info *mf_info = &sc->devinfo.mf_info;
7668         uint32_t val;
7669
7670         /* get the outer vlan if we're in switch-dependent mode */
7671
7672         val = MFCFG_RD(sc, func_mf_config[SC_ABS_FUNC(sc)].e1hov_tag);
7673         mf_info->ext_id = (uint16_t) val;
7674
7675         mf_info->multi_vnics_mode = 1;
7676
7677         if (!VALID_OVLAN(mf_info->ext_id)) {
7678                 PMD_DRV_LOG(NOTICE, sc, "Invalid VLAN (%d)", mf_info->ext_id);
7679                 return 1;
7680         }
7681
7682         /* get the capabilities */
7683         if ((mf_info->mf_config[SC_VN(sc)] & FUNC_MF_CFG_PROTOCOL_MASK) ==
7684             FUNC_MF_CFG_PROTOCOL_ISCSI) {
7685                 mf_info->mf_protos_supported |= MF_PROTO_SUPPORT_ISCSI;
7686         } else if ((mf_info->mf_config[SC_VN(sc)] & FUNC_MF_CFG_PROTOCOL_MASK)
7687                    == FUNC_MF_CFG_PROTOCOL_FCOE) {
7688                 mf_info->mf_protos_supported |= MF_PROTO_SUPPORT_FCOE;
7689         } else {
7690                 mf_info->mf_protos_supported |= MF_PROTO_SUPPORT_ETHERNET;
7691         }
7692
7693         mf_info->vnics_per_port =
7694             (CHIP_PORT_MODE(sc) == CHIP_4_PORT_MODE) ? 2 : 4;
7695
7696         return 0;
7697 }
7698
7699 static uint32_t bnx2x_get_shmem_ext_proto_support_flags(struct bnx2x_softc *sc)
7700 {
7701         uint32_t retval = 0;
7702         uint32_t val;
7703
7704         val = MFCFG_RD(sc, func_ext_config[SC_ABS_FUNC(sc)].func_cfg);
7705
7706         if (val & MACP_FUNC_CFG_FLAGS_ENABLED) {
7707                 if (val & MACP_FUNC_CFG_FLAGS_ETHERNET) {
7708                         retval |= MF_PROTO_SUPPORT_ETHERNET;
7709                 }
7710                 if (val & MACP_FUNC_CFG_FLAGS_ISCSI_OFFLOAD) {
7711                         retval |= MF_PROTO_SUPPORT_ISCSI;
7712                 }
7713                 if (val & MACP_FUNC_CFG_FLAGS_FCOE_OFFLOAD) {
7714                         retval |= MF_PROTO_SUPPORT_FCOE;
7715                 }
7716         }
7717
7718         return retval;
7719 }
7720
7721 static int bnx2x_get_shmem_mf_cfg_info_si(struct bnx2x_softc *sc)
7722 {
7723         struct bnx2x_mf_info *mf_info = &sc->devinfo.mf_info;
7724         uint32_t val;
7725
7726         /*
7727          * There is no outer vlan if we're in switch-independent mode.
7728          * If the mac is valid then assume multi-function.
7729          */
7730
7731         val = MFCFG_RD(sc, func_ext_config[SC_ABS_FUNC(sc)].func_cfg);
7732
7733         mf_info->multi_vnics_mode = ((val & MACP_FUNC_CFG_FLAGS_MASK) != 0);
7734
7735         mf_info->mf_protos_supported =
7736             bnx2x_get_shmem_ext_proto_support_flags(sc);
7737
7738         mf_info->vnics_per_port =
7739             (CHIP_PORT_MODE(sc) == CHIP_4_PORT_MODE) ? 2 : 4;
7740
7741         return 0;
7742 }
7743
7744 static int bnx2x_get_shmem_mf_cfg_info_niv(struct bnx2x_softc *sc)
7745 {
7746         struct bnx2x_mf_info *mf_info = &sc->devinfo.mf_info;
7747         uint32_t e1hov_tag;
7748         uint32_t func_config;
7749         uint32_t niv_config;
7750
7751         mf_info->multi_vnics_mode = 1;
7752
7753         e1hov_tag = MFCFG_RD(sc, func_mf_config[SC_ABS_FUNC(sc)].e1hov_tag);
7754         func_config = MFCFG_RD(sc, func_mf_config[SC_ABS_FUNC(sc)].config);
7755         niv_config = MFCFG_RD(sc, func_mf_config[SC_ABS_FUNC(sc)].afex_config);
7756
7757         mf_info->ext_id =
7758             (uint16_t) ((e1hov_tag & FUNC_MF_CFG_E1HOV_TAG_MASK) >>
7759                         FUNC_MF_CFG_E1HOV_TAG_SHIFT);
7760
7761         mf_info->default_vlan =
7762             (uint16_t) ((e1hov_tag & FUNC_MF_CFG_AFEX_VLAN_MASK) >>
7763                         FUNC_MF_CFG_AFEX_VLAN_SHIFT);
7764
7765         mf_info->niv_allowed_priorities =
7766             (uint8_t) ((niv_config & FUNC_MF_CFG_AFEX_COS_FILTER_MASK) >>
7767                        FUNC_MF_CFG_AFEX_COS_FILTER_SHIFT);
7768
7769         mf_info->niv_default_cos =
7770             (uint8_t) ((func_config & FUNC_MF_CFG_TRANSMIT_PRIORITY_MASK) >>
7771                        FUNC_MF_CFG_TRANSMIT_PRIORITY_SHIFT);
7772
7773         mf_info->afex_vlan_mode =
7774             ((niv_config & FUNC_MF_CFG_AFEX_VLAN_MODE_MASK) >>
7775              FUNC_MF_CFG_AFEX_VLAN_MODE_SHIFT);
7776
7777         mf_info->niv_mba_enabled =
7778             ((niv_config & FUNC_MF_CFG_AFEX_MBA_ENABLED_MASK) >>
7779              FUNC_MF_CFG_AFEX_MBA_ENABLED_SHIFT);
7780
7781         mf_info->mf_protos_supported =
7782             bnx2x_get_shmem_ext_proto_support_flags(sc);
7783
7784         mf_info->vnics_per_port =
7785             (CHIP_PORT_MODE(sc) == CHIP_4_PORT_MODE) ? 2 : 4;
7786
7787         return 0;
7788 }
7789
7790 static int bnx2x_check_valid_mf_cfg(struct bnx2x_softc *sc)
7791 {
7792         struct bnx2x_mf_info *mf_info = &sc->devinfo.mf_info;
7793         uint32_t mf_cfg1;
7794         uint32_t mf_cfg2;
7795         uint32_t ovlan1;
7796         uint32_t ovlan2;
7797         uint8_t i, j;
7798
7799         /* various MF mode sanity checks... */
7800
7801         if (mf_info->mf_config[SC_VN(sc)] & FUNC_MF_CFG_FUNC_HIDE) {
7802                 PMD_DRV_LOG(NOTICE, sc,
7803                             "Enumerated function %d is marked as hidden",
7804                             SC_PORT(sc));
7805                 return 1;
7806         }
7807
7808         if ((mf_info->vnics_per_port > 1) && !mf_info->multi_vnics_mode) {
7809                 PMD_DRV_LOG(NOTICE, sc, "vnics_per_port=%d multi_vnics_mode=%d",
7810                             mf_info->vnics_per_port, mf_info->multi_vnics_mode);
7811                 return 1;
7812         }
7813
7814         if (mf_info->mf_mode == MULTI_FUNCTION_SD) {
7815 /* vnic id > 0 must have valid ovlan in switch-dependent mode */
7816                 if ((SC_VN(sc) > 0) && !VALID_OVLAN(OVLAN(sc))) {
7817                         PMD_DRV_LOG(NOTICE, sc, "mf_mode=SD vnic_id=%d ovlan=%d",
7818                                     SC_VN(sc), OVLAN(sc));
7819                         return 1;
7820                 }
7821
7822                 if (!VALID_OVLAN(OVLAN(sc)) && mf_info->multi_vnics_mode) {
7823                         PMD_DRV_LOG(NOTICE, sc,
7824                                     "mf_mode=SD multi_vnics_mode=%d ovlan=%d",
7825                                     mf_info->multi_vnics_mode, OVLAN(sc));
7826                         return 1;
7827                 }
7828
7829 /*
7830  * Verify all functions are either MF or SF mode. If MF, make sure
7831  * sure that all non-hidden functions have a valid ovlan. If SF,
7832  * make sure that all non-hidden functions have an invalid ovlan.
7833  */
7834                 FOREACH_ABS_FUNC_IN_PORT(sc, i) {
7835                         mf_cfg1 = MFCFG_RD(sc, func_mf_config[i].config);
7836                         ovlan1 = MFCFG_RD(sc, func_mf_config[i].e1hov_tag);
7837                         if (!(mf_cfg1 & FUNC_MF_CFG_FUNC_HIDE) &&
7838                             (((mf_info->multi_vnics_mode)
7839                               && !VALID_OVLAN(ovlan1))
7840                              || ((!mf_info->multi_vnics_mode)
7841                                  && VALID_OVLAN(ovlan1)))) {
7842                                 PMD_DRV_LOG(NOTICE, sc,
7843                                             "mf_mode=SD function %d MF config "
7844                                             "mismatch, multi_vnics_mode=%d ovlan=%d",
7845                                             i, mf_info->multi_vnics_mode,
7846                                             ovlan1);
7847                                 return 1;
7848                         }
7849                 }
7850
7851 /* Verify all funcs on the same port each have a different ovlan. */
7852                 FOREACH_ABS_FUNC_IN_PORT(sc, i) {
7853                         mf_cfg1 = MFCFG_RD(sc, func_mf_config[i].config);
7854                         ovlan1 = MFCFG_RD(sc, func_mf_config[i].e1hov_tag);
7855                         /* iterate from the next function on the port to the max func */
7856                         for (j = i + 2; j < MAX_FUNC_NUM; j += 2) {
7857                                 mf_cfg2 =
7858                                     MFCFG_RD(sc, func_mf_config[j].config);
7859                                 ovlan2 =
7860                                     MFCFG_RD(sc, func_mf_config[j].e1hov_tag);
7861                                 if (!(mf_cfg1 & FUNC_MF_CFG_FUNC_HIDE)
7862                                     && VALID_OVLAN(ovlan1)
7863                                     && !(mf_cfg2 & FUNC_MF_CFG_FUNC_HIDE)
7864                                     && VALID_OVLAN(ovlan2)
7865                                     && (ovlan1 == ovlan2)) {
7866                                         PMD_DRV_LOG(NOTICE, sc,
7867                                                     "mf_mode=SD functions %d and %d "
7868                                                     "have the same ovlan (%d)",
7869                                                     i, j, ovlan1);
7870                                         return 1;
7871                                 }
7872                         }
7873                 }
7874         }
7875         /* MULTI_FUNCTION_SD */
7876         return 0;
7877 }
7878
7879 static int bnx2x_get_mf_cfg_info(struct bnx2x_softc *sc)
7880 {
7881         struct bnx2x_mf_info *mf_info = &sc->devinfo.mf_info;
7882         uint32_t val, mac_upper;
7883         uint8_t i, vnic;
7884
7885         /* initialize mf_info defaults */
7886         mf_info->vnics_per_port = 1;
7887         mf_info->multi_vnics_mode = FALSE;
7888         mf_info->path_has_ovlan = FALSE;
7889         mf_info->mf_mode = SINGLE_FUNCTION;
7890
7891         if (!CHIP_IS_MF_CAP(sc)) {
7892                 return 0;
7893         }
7894
7895         if (sc->devinfo.mf_cfg_base == SHMEM_MF_CFG_ADDR_NONE) {
7896                 PMD_DRV_LOG(NOTICE, sc, "Invalid mf_cfg_base!");
7897                 return 1;
7898         }
7899
7900         /* get the MF mode (switch dependent / independent / single-function) */
7901
7902         val = SHMEM_RD(sc, dev_info.shared_feature_config.config);
7903
7904         switch (val & SHARED_FEAT_CFG_FORCE_SF_MODE_MASK) {
7905         case SHARED_FEAT_CFG_FORCE_SF_MODE_SWITCH_INDEPT:
7906
7907                 mac_upper =
7908                     MFCFG_RD(sc, func_mf_config[SC_ABS_FUNC(sc)].mac_upper);
7909
7910                 /* check for legal upper mac bytes */
7911                 if (mac_upper != FUNC_MF_CFG_UPPERMAC_DEFAULT) {
7912                         mf_info->mf_mode = MULTI_FUNCTION_SI;
7913                 } else {
7914                         PMD_DRV_LOG(NOTICE, sc,
7915                                     "Invalid config for Switch Independent mode");
7916                 }
7917
7918                 break;
7919
7920         case SHARED_FEAT_CFG_FORCE_SF_MODE_MF_ALLOWED:
7921         case SHARED_FEAT_CFG_FORCE_SF_MODE_SPIO4:
7922
7923                 /* get outer vlan configuration */
7924                 val = MFCFG_RD(sc, func_mf_config[SC_ABS_FUNC(sc)].e1hov_tag);
7925
7926                 if ((val & FUNC_MF_CFG_E1HOV_TAG_MASK) !=
7927                     FUNC_MF_CFG_E1HOV_TAG_DEFAULT) {
7928                         mf_info->mf_mode = MULTI_FUNCTION_SD;
7929                 } else {
7930                         PMD_DRV_LOG(NOTICE, sc,
7931                                     "Invalid config for Switch Dependent mode");
7932                 }
7933
7934                 break;
7935
7936         case SHARED_FEAT_CFG_FORCE_SF_MODE_FORCED_SF:
7937
7938                 /* not in MF mode, vnics_per_port=1 and multi_vnics_mode=FALSE */
7939                 return 0;
7940
7941         case SHARED_FEAT_CFG_FORCE_SF_MODE_AFEX_MODE:
7942
7943                 /*
7944                  * Mark MF mode as NIV if MCP version includes NPAR-SD support
7945                  * and the MAC address is valid.
7946                  */
7947                 mac_upper =
7948                     MFCFG_RD(sc, func_mf_config[SC_ABS_FUNC(sc)].mac_upper);
7949
7950                 if ((SHMEM2_HAS(sc, afex_driver_support)) &&
7951                     (mac_upper != FUNC_MF_CFG_UPPERMAC_DEFAULT)) {
7952                         mf_info->mf_mode = MULTI_FUNCTION_AFEX;
7953                 } else {
7954                         PMD_DRV_LOG(NOTICE, sc, "Invalid config for AFEX mode");
7955                 }
7956
7957                 break;
7958
7959         default:
7960
7961                 PMD_DRV_LOG(NOTICE, sc, "Unknown MF mode (0x%08x)",
7962                             (val & SHARED_FEAT_CFG_FORCE_SF_MODE_MASK));
7963
7964                 return 1;
7965         }
7966
7967         /* set path mf_mode (which could be different than function mf_mode) */
7968         if (mf_info->mf_mode == MULTI_FUNCTION_SD) {
7969                 mf_info->path_has_ovlan = TRUE;
7970         } else if (mf_info->mf_mode == SINGLE_FUNCTION) {
7971 /*
7972  * Decide on path multi vnics mode. If we're not in MF mode and in
7973  * 4-port mode, this is good enough to check vnic-0 of the other port
7974  * on the same path
7975  */
7976                 if (CHIP_PORT_MODE(sc) == CHIP_4_PORT_MODE) {
7977                         uint8_t other_port = !(PORT_ID(sc) & 1);
7978                         uint8_t abs_func_other_port =
7979                             (SC_PATH(sc) + (2 * other_port));
7980
7981                         val =
7982                             MFCFG_RD(sc,
7983                                      func_mf_config
7984                                      [abs_func_other_port].e1hov_tag);
7985
7986                         mf_info->path_has_ovlan = VALID_OVLAN((uint16_t) val);
7987                 }
7988         }
7989
7990         if (mf_info->mf_mode == SINGLE_FUNCTION) {
7991 /* invalid MF config */
7992                 if (SC_VN(sc) >= 1) {
7993                         PMD_DRV_LOG(NOTICE, sc, "VNIC ID >= 1 in SF mode");
7994                         return 1;
7995                 }
7996
7997                 return 0;
7998         }
7999
8000         /* get the MF configuration */
8001         mf_info->mf_config[SC_VN(sc)] =
8002             MFCFG_RD(sc, func_mf_config[SC_ABS_FUNC(sc)].config);
8003
8004         switch (mf_info->mf_mode) {
8005         case MULTI_FUNCTION_SD:
8006
8007                 bnx2x_get_shmem_mf_cfg_info_sd(sc);
8008                 break;
8009
8010         case MULTI_FUNCTION_SI:
8011
8012                 bnx2x_get_shmem_mf_cfg_info_si(sc);
8013                 break;
8014
8015         case MULTI_FUNCTION_AFEX:
8016
8017                 bnx2x_get_shmem_mf_cfg_info_niv(sc);
8018                 break;
8019
8020         default:
8021
8022                 PMD_DRV_LOG(NOTICE, sc, "Get MF config failed (mf_mode=0x%08x)",
8023                             mf_info->mf_mode);
8024                 return 1;
8025         }
8026
8027         /* get the congestion management parameters */
8028
8029         vnic = 0;
8030         FOREACH_ABS_FUNC_IN_PORT(sc, i) {
8031 /* get min/max bw */
8032                 val = MFCFG_RD(sc, func_mf_config[i].config);
8033                 mf_info->min_bw[vnic] =
8034                     ((val & FUNC_MF_CFG_MIN_BW_MASK) >>
8035                      FUNC_MF_CFG_MIN_BW_SHIFT);
8036                 mf_info->max_bw[vnic] =
8037                     ((val & FUNC_MF_CFG_MAX_BW_MASK) >>
8038                      FUNC_MF_CFG_MAX_BW_SHIFT);
8039                 vnic++;
8040         }
8041
8042         return bnx2x_check_valid_mf_cfg(sc);
8043 }
8044
8045 static int bnx2x_get_shmem_info(struct bnx2x_softc *sc)
8046 {
8047         int port;
8048         uint32_t mac_hi, mac_lo, val;
8049
8050         PMD_INIT_FUNC_TRACE(sc);
8051
8052         port = SC_PORT(sc);
8053         mac_hi = mac_lo = 0;
8054
8055         sc->link_params.sc = sc;
8056         sc->link_params.port = port;
8057
8058         /* get the hardware config info */
8059         sc->devinfo.hw_config = SHMEM_RD(sc, dev_info.shared_hw_config.config);
8060         sc->devinfo.hw_config2 =
8061             SHMEM_RD(sc, dev_info.shared_hw_config.config2);
8062
8063         sc->link_params.hw_led_mode =
8064             ((sc->devinfo.hw_config & SHARED_HW_CFG_LED_MODE_MASK) >>
8065              SHARED_HW_CFG_LED_MODE_SHIFT);
8066
8067         /* get the port feature config */
8068         sc->port.config =
8069             SHMEM_RD(sc, dev_info.port_feature_config[port].config);
8070
8071         /* get the link params */
8072         sc->link_params.speed_cap_mask[ELINK_INT_PHY] =
8073             SHMEM_RD(sc, dev_info.port_hw_config[port].speed_capability_mask)
8074             & PORT_HW_CFG_SPEED_CAPABILITY_D0_MASK;
8075         sc->link_params.speed_cap_mask[ELINK_EXT_PHY1] =
8076             SHMEM_RD(sc, dev_info.port_hw_config[port].speed_capability_mask2)
8077             & PORT_HW_CFG_SPEED_CAPABILITY_D0_MASK;
8078
8079         /* get the lane config */
8080         sc->link_params.lane_config =
8081             SHMEM_RD(sc, dev_info.port_hw_config[port].lane_config);
8082
8083         /* get the link config */
8084         val = SHMEM_RD(sc, dev_info.port_feature_config[port].link_config);
8085         sc->port.link_config[ELINK_INT_PHY] = val;
8086         sc->link_params.switch_cfg = (val & PORT_FEATURE_CONNECTED_SWITCH_MASK);
8087         sc->port.link_config[ELINK_EXT_PHY1] =
8088             SHMEM_RD(sc, dev_info.port_feature_config[port].link_config2);
8089
8090         /* get the override preemphasis flag and enable it or turn it off */
8091         val = SHMEM_RD(sc, dev_info.shared_feature_config.config);
8092         if (val & SHARED_FEAT_CFG_OVERRIDE_PREEMPHASIS_CFG_ENABLED) {
8093                 sc->link_params.feature_config_flags |=
8094                     ELINK_FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED;
8095         } else {
8096                 sc->link_params.feature_config_flags &=
8097                     ~ELINK_FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED;
8098         }
8099
8100         /* get the initial value of the link params */
8101         sc->link_params.multi_phy_config =
8102             SHMEM_RD(sc, dev_info.port_hw_config[port].multi_phy_config);
8103
8104         /* get external phy info */
8105         sc->port.ext_phy_config =
8106             SHMEM_RD(sc, dev_info.port_hw_config[port].external_phy_config);
8107
8108         /* get the multifunction configuration */
8109         bnx2x_get_mf_cfg_info(sc);
8110
8111         /* get the mac address */
8112         if (IS_MF(sc)) {
8113                 mac_hi =
8114                     MFCFG_RD(sc, func_mf_config[SC_ABS_FUNC(sc)].mac_upper);
8115                 mac_lo =
8116                     MFCFG_RD(sc, func_mf_config[SC_ABS_FUNC(sc)].mac_lower);
8117         } else {
8118                 mac_hi = SHMEM_RD(sc, dev_info.port_hw_config[port].mac_upper);
8119                 mac_lo = SHMEM_RD(sc, dev_info.port_hw_config[port].mac_lower);
8120         }
8121
8122         if ((mac_lo == 0) && (mac_hi == 0)) {
8123                 *sc->mac_addr_str = 0;
8124                 PMD_DRV_LOG(NOTICE, sc, "No Ethernet address programmed!");
8125         } else {
8126                 sc->link_params.mac_addr[0] = (uint8_t) (mac_hi >> 8);
8127                 sc->link_params.mac_addr[1] = (uint8_t) (mac_hi);
8128                 sc->link_params.mac_addr[2] = (uint8_t) (mac_lo >> 24);
8129                 sc->link_params.mac_addr[3] = (uint8_t) (mac_lo >> 16);
8130                 sc->link_params.mac_addr[4] = (uint8_t) (mac_lo >> 8);
8131                 sc->link_params.mac_addr[5] = (uint8_t) (mac_lo);
8132                 snprintf(sc->mac_addr_str, sizeof(sc->mac_addr_str),
8133                          "%02x:%02x:%02x:%02x:%02x:%02x",
8134                          sc->link_params.mac_addr[0],
8135                          sc->link_params.mac_addr[1],
8136                          sc->link_params.mac_addr[2],
8137                          sc->link_params.mac_addr[3],
8138                          sc->link_params.mac_addr[4],
8139                          sc->link_params.mac_addr[5]);
8140                 PMD_DRV_LOG(DEBUG, sc,
8141                             "Ethernet address: %s", sc->mac_addr_str);
8142         }
8143
8144         return 0;
8145 }
8146
8147 static void bnx2x_media_detect(struct bnx2x_softc *sc)
8148 {
8149         uint32_t phy_idx = bnx2x_get_cur_phy_idx(sc);
8150         switch (sc->link_params.phy[phy_idx].media_type) {
8151         case ELINK_ETH_PHY_SFPP_10G_FIBER:
8152         case ELINK_ETH_PHY_SFP_1G_FIBER:
8153         case ELINK_ETH_PHY_XFP_FIBER:
8154         case ELINK_ETH_PHY_KR:
8155         case ELINK_ETH_PHY_CX4:
8156                 PMD_DRV_LOG(INFO, sc, "Found 10GBase-CX4 media.");
8157                 sc->media = IFM_10G_CX4;
8158                 break;
8159         case ELINK_ETH_PHY_DA_TWINAX:
8160                 PMD_DRV_LOG(INFO, sc, "Found 10Gb Twinax media.");
8161                 sc->media = IFM_10G_TWINAX;
8162                 break;
8163         case ELINK_ETH_PHY_BASE_T:
8164                 PMD_DRV_LOG(INFO, sc, "Found 10GBase-T media.");
8165                 sc->media = IFM_10G_T;
8166                 break;
8167         case ELINK_ETH_PHY_NOT_PRESENT:
8168                 PMD_DRV_LOG(INFO, sc, "Media not present.");
8169                 sc->media = 0;
8170                 break;
8171         case ELINK_ETH_PHY_UNSPECIFIED:
8172         default:
8173                 PMD_DRV_LOG(INFO, sc, "Unknown media!");
8174                 sc->media = 0;
8175                 break;
8176         }
8177 }
8178
8179 #define GET_FIELD(value, fname)                     \
8180 (((value) & (fname##_MASK)) >> (fname##_SHIFT))
8181 #define IGU_FID(val) GET_FIELD((val), IGU_REG_MAPPING_MEMORY_FID)
8182 #define IGU_VEC(val) GET_FIELD((val), IGU_REG_MAPPING_MEMORY_VECTOR)
8183
8184 static int bnx2x_get_igu_cam_info(struct bnx2x_softc *sc)
8185 {
8186         int pfid = SC_FUNC(sc);
8187         int igu_sb_id;
8188         uint32_t val;
8189         uint8_t fid, igu_sb_cnt = 0;
8190
8191         sc->igu_base_sb = 0xff;
8192
8193         if (CHIP_INT_MODE_IS_BC(sc)) {
8194                 int vn = SC_VN(sc);
8195                 igu_sb_cnt = sc->igu_sb_cnt;
8196                 sc->igu_base_sb = ((CHIP_IS_MODE_4_PORT(sc) ? pfid : vn) *
8197                                    FP_SB_MAX_E1x);
8198                 sc->igu_dsb_id = (E1HVN_MAX * FP_SB_MAX_E1x +
8199                                   (CHIP_IS_MODE_4_PORT(sc) ? pfid : vn));
8200                 return 0;
8201         }
8202
8203         /* IGU in normal mode - read CAM */
8204         for (igu_sb_id = 0;
8205              igu_sb_id < IGU_REG_MAPPING_MEMORY_SIZE; igu_sb_id++) {
8206                 val = REG_RD(sc, IGU_REG_MAPPING_MEMORY + igu_sb_id * 4);
8207                 if (!(val & IGU_REG_MAPPING_MEMORY_VALID)) {
8208                         continue;
8209                 }
8210                 fid = IGU_FID(val);
8211                 if (fid & IGU_FID_ENCODE_IS_PF) {
8212                         if ((fid & IGU_FID_PF_NUM_MASK) != pfid) {
8213                                 continue;
8214                         }
8215                         if (IGU_VEC(val) == 0) {
8216                                 /* default status block */
8217                                 sc->igu_dsb_id = igu_sb_id;
8218                         } else {
8219                                 if (sc->igu_base_sb == 0xff) {
8220                                         sc->igu_base_sb = igu_sb_id;
8221                                 }
8222                                 igu_sb_cnt++;
8223                         }
8224                 }
8225         }
8226
8227         /*
8228          * Due to new PF resource allocation by MFW T7.4 and above, it's optional
8229          * that number of CAM entries will not be equal to the value advertised in
8230          * PCI. Driver should use the minimal value of both as the actual status
8231          * block count
8232          */
8233         sc->igu_sb_cnt = min(sc->igu_sb_cnt, igu_sb_cnt);
8234
8235         if (igu_sb_cnt == 0) {
8236                 PMD_DRV_LOG(ERR, sc, "CAM configuration error");
8237                 return -1;
8238         }
8239
8240         return 0;
8241 }
8242
8243 /*
8244 * Gather various information from the device config space, the device itself,
8245 * shmem, and the user input.
8246 */
8247 static int bnx2x_get_device_info(struct bnx2x_softc *sc)
8248 {
8249         uint32_t val;
8250         int rc;
8251
8252         /* get the chip revision (chip metal comes from pci config space) */
8253         sc->devinfo.chip_id = sc->link_params.chip_id =
8254             (((REG_RD(sc, MISC_REG_CHIP_NUM) & 0xffff) << 16) |
8255              ((REG_RD(sc, MISC_REG_CHIP_REV) & 0xf) << 12) |
8256              (((REG_RD(sc, PCICFG_OFFSET + PCI_ID_VAL3) >> 24) & 0xf) << 4) |
8257              ((REG_RD(sc, MISC_REG_BOND_ID) & 0xf) << 0));
8258
8259         /* force 57811 according to MISC register */
8260         if (REG_RD(sc, MISC_REG_CHIP_TYPE) & MISC_REG_CHIP_TYPE_57811_MASK) {
8261                 if (CHIP_IS_57810(sc)) {
8262                         sc->devinfo.chip_id = ((CHIP_NUM_57811 << 16) |
8263                                                (sc->
8264                                                 devinfo.chip_id & 0x0000ffff));
8265                 } else if (CHIP_IS_57810_MF(sc)) {
8266                         sc->devinfo.chip_id = ((CHIP_NUM_57811_MF << 16) |
8267                                                (sc->
8268                                                 devinfo.chip_id & 0x0000ffff));
8269                 }
8270                 sc->devinfo.chip_id |= 0x1;
8271         }
8272
8273         PMD_DRV_LOG(DEBUG, sc,
8274                     "chip_id=0x%08x (num=0x%04x rev=0x%01x metal=0x%02x bond=0x%01x)",
8275                     sc->devinfo.chip_id,
8276                     ((sc->devinfo.chip_id >> 16) & 0xffff),
8277                     ((sc->devinfo.chip_id >> 12) & 0xf),
8278                     ((sc->devinfo.chip_id >> 4) & 0xff),
8279                     ((sc->devinfo.chip_id >> 0) & 0xf));
8280
8281         val = (REG_RD(sc, 0x2874) & 0x55);
8282         if ((sc->devinfo.chip_id & 0x1) || (CHIP_IS_E1H(sc) && (val == 0x55))) {
8283                 sc->flags |= BNX2X_ONE_PORT_FLAG;
8284                 PMD_DRV_LOG(DEBUG, sc, "single port device");
8285         }
8286
8287         /* set the doorbell size */
8288         sc->doorbell_size = (1 << BNX2X_DB_SHIFT);
8289
8290         /* determine whether the device is in 2 port or 4 port mode */
8291         sc->devinfo.chip_port_mode = CHIP_PORT_MODE_NONE;       /* E1h */
8292         if (CHIP_IS_E2E3(sc)) {
8293 /*
8294  * Read port4mode_en_ovwr[0]:
8295  *   If 1, four port mode is in port4mode_en_ovwr[1].
8296  *   If 0, four port mode is in port4mode_en[0].
8297  */
8298                 val = REG_RD(sc, MISC_REG_PORT4MODE_EN_OVWR);
8299                 if (val & 1) {
8300                         val = ((val >> 1) & 1);
8301                 } else {
8302                         val = REG_RD(sc, MISC_REG_PORT4MODE_EN);
8303                 }
8304
8305                 sc->devinfo.chip_port_mode =
8306                     (val) ? CHIP_4_PORT_MODE : CHIP_2_PORT_MODE;
8307
8308                 PMD_DRV_LOG(DEBUG, sc, "Port mode = %s", (val) ? "4" : "2");
8309         }
8310
8311         /* get the function and path info for the device */
8312         bnx2x_get_function_num(sc);
8313
8314         /* get the shared memory base address */
8315         sc->devinfo.shmem_base =
8316             sc->link_params.shmem_base = REG_RD(sc, MISC_REG_SHARED_MEM_ADDR);
8317         sc->devinfo.shmem2_base =
8318             REG_RD(sc, (SC_PATH(sc) ? MISC_REG_GENERIC_CR_1 :
8319                         MISC_REG_GENERIC_CR_0));
8320
8321         if (!sc->devinfo.shmem_base) {
8322 /* this should ONLY prevent upcoming shmem reads */
8323                 PMD_DRV_LOG(INFO, sc, "MCP not active");
8324                 sc->flags |= BNX2X_NO_MCP_FLAG;
8325                 return 0;
8326         }
8327
8328         /* make sure the shared memory contents are valid */
8329         val = SHMEM_RD(sc, validity_map[SC_PORT(sc)]);
8330         if ((val & (SHR_MEM_VALIDITY_DEV_INFO | SHR_MEM_VALIDITY_MB)) !=
8331             (SHR_MEM_VALIDITY_DEV_INFO | SHR_MEM_VALIDITY_MB)) {
8332                 PMD_DRV_LOG(NOTICE, sc, "Invalid SHMEM validity signature: 0x%08x",
8333                             val);
8334                 return 0;
8335         }
8336
8337         /* get the bootcode version */
8338         sc->devinfo.bc_ver = SHMEM_RD(sc, dev_info.bc_rev);
8339         snprintf(sc->devinfo.bc_ver_str,
8340                  sizeof(sc->devinfo.bc_ver_str),
8341                  "%d.%d.%d",
8342                  ((sc->devinfo.bc_ver >> 24) & 0xff),
8343                  ((sc->devinfo.bc_ver >> 16) & 0xff),
8344                  ((sc->devinfo.bc_ver >> 8) & 0xff));
8345         PMD_DRV_LOG(DEBUG, sc, "Bootcode version: %s", sc->devinfo.bc_ver_str);
8346
8347         /* get the bootcode shmem address */
8348         sc->devinfo.mf_cfg_base = bnx2x_get_shmem_mf_cfg_base(sc);
8349
8350         /* clean indirect addresses as they're not used */
8351         pci_write_long(sc, PCICFG_GRC_ADDRESS, 0);
8352         if (IS_PF(sc)) {
8353                 REG_WR(sc, PXP2_REG_PGL_ADDR_88_F0, 0);
8354                 REG_WR(sc, PXP2_REG_PGL_ADDR_8C_F0, 0);
8355                 REG_WR(sc, PXP2_REG_PGL_ADDR_90_F0, 0);
8356                 REG_WR(sc, PXP2_REG_PGL_ADDR_94_F0, 0);
8357                 if (CHIP_IS_E1x(sc)) {
8358                         REG_WR(sc, PXP2_REG_PGL_ADDR_88_F1, 0);
8359                         REG_WR(sc, PXP2_REG_PGL_ADDR_8C_F1, 0);
8360                         REG_WR(sc, PXP2_REG_PGL_ADDR_90_F1, 0);
8361                         REG_WR(sc, PXP2_REG_PGL_ADDR_94_F1, 0);
8362                 }
8363         }
8364
8365         /* get the nvram size */
8366         val = REG_RD(sc, MCP_REG_MCPR_NVM_CFG4);
8367         sc->devinfo.flash_size =
8368             (NVRAM_1MB_SIZE << (val & MCPR_NVM_CFG4_FLASH_SIZE));
8369
8370         bnx2x_set_power_state(sc, PCI_PM_D0);
8371         /* get various configuration parameters from shmem */
8372         bnx2x_get_shmem_info(sc);
8373
8374         /* initialize IGU parameters */
8375         if (CHIP_IS_E1x(sc)) {
8376                 sc->devinfo.int_block = INT_BLOCK_HC;
8377                 sc->igu_dsb_id = DEF_SB_IGU_ID;
8378                 sc->igu_base_sb = 0;
8379         } else {
8380                 sc->devinfo.int_block = INT_BLOCK_IGU;
8381
8382 /* do not allow device reset during IGU info preocessing */
8383                 bnx2x_acquire_hw_lock(sc, HW_LOCK_RESOURCE_RESET);
8384
8385                 val = REG_RD(sc, IGU_REG_BLOCK_CONFIGURATION);
8386
8387                 if (val & IGU_BLOCK_CONFIGURATION_REG_BACKWARD_COMP_EN) {
8388                         int tout = 5000;
8389
8390                         val &= ~(IGU_BLOCK_CONFIGURATION_REG_BACKWARD_COMP_EN);
8391                         REG_WR(sc, IGU_REG_BLOCK_CONFIGURATION, val);
8392                         REG_WR(sc, IGU_REG_RESET_MEMORIES, 0x7f);
8393
8394                         while (tout && REG_RD(sc, IGU_REG_RESET_MEMORIES)) {
8395                                 tout--;
8396                                 DELAY(1000);
8397                         }
8398
8399                         if (REG_RD(sc, IGU_REG_RESET_MEMORIES)) {
8400                                 PMD_DRV_LOG(NOTICE, sc,
8401                                             "FORCING IGU Normal Mode failed!!!");
8402                                 bnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_RESET);
8403                                 return -1;
8404                         }
8405                 }
8406
8407                 if (val & IGU_BLOCK_CONFIGURATION_REG_BACKWARD_COMP_EN) {
8408                         PMD_DRV_LOG(DEBUG, sc, "IGU Backward Compatible Mode");
8409                         sc->devinfo.int_block |= INT_BLOCK_MODE_BW_COMP;
8410                 } else {
8411                         PMD_DRV_LOG(DEBUG, sc, "IGU Normal Mode");
8412                 }
8413
8414                 rc = bnx2x_get_igu_cam_info(sc);
8415
8416                 bnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_RESET);
8417
8418                 if (rc) {
8419                         return rc;
8420                 }
8421         }
8422
8423         /*
8424          * Get base FW non-default (fast path) status block ID. This value is
8425          * used to initialize the fw_sb_id saved on the fp/queue structure to
8426          * determine the id used by the FW.
8427          */
8428         if (CHIP_IS_E1x(sc)) {
8429                 sc->base_fw_ndsb =
8430                     ((SC_PORT(sc) * FP_SB_MAX_E1x) + SC_L_ID(sc));
8431         } else {
8432 /*
8433  * 57712+ - We currently use one FW SB per IGU SB (Rx and Tx of
8434  * the same queue are indicated on the same IGU SB). So we prefer
8435  * FW and IGU SBs to be the same value.
8436  */
8437                 sc->base_fw_ndsb = sc->igu_base_sb;
8438         }
8439
8440         elink_phy_probe(&sc->link_params);
8441
8442         return 0;
8443 }
8444
8445 static void
8446 bnx2x_link_settings_supported(struct bnx2x_softc *sc, uint32_t switch_cfg)
8447 {
8448         uint32_t cfg_size = 0;
8449         uint32_t idx;
8450         uint8_t port = SC_PORT(sc);
8451
8452         /* aggregation of supported attributes of all external phys */
8453         sc->port.supported[0] = 0;
8454         sc->port.supported[1] = 0;
8455
8456         switch (sc->link_params.num_phys) {
8457         case 1:
8458                 sc->port.supported[0] =
8459                     sc->link_params.phy[ELINK_INT_PHY].supported;
8460                 cfg_size = 1;
8461                 break;
8462         case 2:
8463                 sc->port.supported[0] =
8464                     sc->link_params.phy[ELINK_EXT_PHY1].supported;
8465                 cfg_size = 1;
8466                 break;
8467         case 3:
8468                 if (sc->link_params.multi_phy_config &
8469                     PORT_HW_CFG_PHY_SWAPPED_ENABLED) {
8470                         sc->port.supported[1] =
8471                             sc->link_params.phy[ELINK_EXT_PHY1].supported;
8472                         sc->port.supported[0] =
8473                             sc->link_params.phy[ELINK_EXT_PHY2].supported;
8474                 } else {
8475                         sc->port.supported[0] =
8476                             sc->link_params.phy[ELINK_EXT_PHY1].supported;
8477                         sc->port.supported[1] =
8478                             sc->link_params.phy[ELINK_EXT_PHY2].supported;
8479                 }
8480                 cfg_size = 2;
8481                 break;
8482         }
8483
8484         if (!(sc->port.supported[0] || sc->port.supported[1])) {
8485                 PMD_DRV_LOG(ERR, sc,
8486                             "Invalid phy config in NVRAM (PHY1=0x%08x PHY2=0x%08x)",
8487                             SHMEM_RD(sc,
8488                                      dev_info.port_hw_config
8489                                      [port].external_phy_config),
8490                             SHMEM_RD(sc,
8491                                      dev_info.port_hw_config
8492                                      [port].external_phy_config2));
8493                 return;
8494         }
8495
8496         if (CHIP_IS_E3(sc))
8497                 sc->port.phy_addr = REG_RD(sc, MISC_REG_WC0_CTRL_PHY_ADDR);
8498         else {
8499                 switch (switch_cfg) {
8500                 case ELINK_SWITCH_CFG_1G:
8501                         sc->port.phy_addr =
8502                             REG_RD(sc,
8503                                    NIG_REG_SERDES0_CTRL_PHY_ADDR + port * 0x10);
8504                         break;
8505                 case ELINK_SWITCH_CFG_10G:
8506                         sc->port.phy_addr =
8507                             REG_RD(sc,
8508                                    NIG_REG_XGXS0_CTRL_PHY_ADDR + port * 0x18);
8509                         break;
8510                 default:
8511                         PMD_DRV_LOG(ERR, sc,
8512                                     "Invalid switch config in"
8513                                     "link_config=0x%08x",
8514                                     sc->port.link_config[0]);
8515                         return;
8516                 }
8517         }
8518
8519         PMD_DRV_LOG(INFO, sc, "PHY addr 0x%08x", sc->port.phy_addr);
8520
8521         /* mask what we support according to speed_cap_mask per configuration */
8522         for (idx = 0; idx < cfg_size; idx++) {
8523                 if (!(sc->link_params.speed_cap_mask[idx] &
8524                       PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_HALF)) {
8525                         sc->port.supported[idx] &=
8526                             ~ELINK_SUPPORTED_10baseT_Half;
8527                 }
8528
8529                 if (!(sc->link_params.speed_cap_mask[idx] &
8530                       PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL)) {
8531                         sc->port.supported[idx] &=
8532                             ~ELINK_SUPPORTED_10baseT_Full;
8533                 }
8534
8535                 if (!(sc->link_params.speed_cap_mask[idx] &
8536                       PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_HALF)) {
8537                         sc->port.supported[idx] &=
8538                             ~ELINK_SUPPORTED_100baseT_Half;
8539                 }
8540
8541                 if (!(sc->link_params.speed_cap_mask[idx] &
8542                       PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_FULL)) {
8543                         sc->port.supported[idx] &=
8544                             ~ELINK_SUPPORTED_100baseT_Full;
8545                 }
8546
8547                 if (!(sc->link_params.speed_cap_mask[idx] &
8548                       PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)) {
8549                         sc->port.supported[idx] &=
8550                             ~ELINK_SUPPORTED_1000baseT_Full;
8551                 }
8552
8553                 if (!(sc->link_params.speed_cap_mask[idx] &
8554                       PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G)) {
8555                         sc->port.supported[idx] &=
8556                             ~ELINK_SUPPORTED_2500baseX_Full;
8557                 }
8558
8559                 if (!(sc->link_params.speed_cap_mask[idx] &
8560                       PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)) {
8561                         sc->port.supported[idx] &=
8562                             ~ELINK_SUPPORTED_10000baseT_Full;
8563                 }
8564
8565                 if (!(sc->link_params.speed_cap_mask[idx] &
8566                       PORT_HW_CFG_SPEED_CAPABILITY_D0_20G)) {
8567                         sc->port.supported[idx] &=
8568                             ~ELINK_SUPPORTED_20000baseKR2_Full;
8569                 }
8570         }
8571
8572         PMD_DRV_LOG(INFO, sc, "PHY supported 0=0x%08x 1=0x%08x",
8573                     sc->port.supported[0], sc->port.supported[1]);
8574 }
8575
8576 static void bnx2x_link_settings_requested(struct bnx2x_softc *sc)
8577 {
8578         uint32_t link_config;
8579         uint32_t idx;
8580         uint32_t cfg_size = 0;
8581
8582         sc->port.advertising[0] = 0;
8583         sc->port.advertising[1] = 0;
8584
8585         switch (sc->link_params.num_phys) {
8586         case 1:
8587         case 2:
8588                 cfg_size = 1;
8589                 break;
8590         case 3:
8591                 cfg_size = 2;
8592                 break;
8593         }
8594
8595         for (idx = 0; idx < cfg_size; idx++) {
8596                 sc->link_params.req_duplex[idx] = DUPLEX_FULL;
8597                 link_config = sc->port.link_config[idx];
8598
8599                 switch (link_config & PORT_FEATURE_LINK_SPEED_MASK) {
8600                 case PORT_FEATURE_LINK_SPEED_AUTO:
8601                         if (sc->port.supported[idx] & ELINK_SUPPORTED_Autoneg) {
8602                                 sc->link_params.req_line_speed[idx] =
8603                                     ELINK_SPEED_AUTO_NEG;
8604                                 sc->port.advertising[idx] |=
8605                                     sc->port.supported[idx];
8606                                 if (sc->link_params.phy[ELINK_EXT_PHY1].type ==
8607                                     PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X84833)
8608                                         sc->port.advertising[idx] |=
8609                                             (ELINK_SUPPORTED_100baseT_Half |
8610                                              ELINK_SUPPORTED_100baseT_Full);
8611                         } else {
8612                                 /* force 10G, no AN */
8613                                 sc->link_params.req_line_speed[idx] =
8614                                     ELINK_SPEED_10000;
8615                                 sc->port.advertising[idx] |=
8616                                     (ADVERTISED_10000baseT_Full |
8617                                      ADVERTISED_FIBRE);
8618                                 continue;
8619                         }
8620                         break;
8621
8622                 case PORT_FEATURE_LINK_SPEED_10M_FULL:
8623                         if (sc->
8624                             port.supported[idx] & ELINK_SUPPORTED_10baseT_Full)
8625                         {
8626                                 sc->link_params.req_line_speed[idx] =
8627                                     ELINK_SPEED_10;
8628                                 sc->port.advertising[idx] |=
8629                                     (ADVERTISED_10baseT_Full | ADVERTISED_TP);
8630                         } else {
8631                                 PMD_DRV_LOG(ERR, sc,
8632                                             "Invalid NVRAM config link_config=0x%08x "
8633                                             "speed_cap_mask=0x%08x",
8634                                             link_config,
8635                                             sc->
8636                                             link_params.speed_cap_mask[idx]);
8637                                 return;
8638                         }
8639                         break;
8640
8641                 case PORT_FEATURE_LINK_SPEED_10M_HALF:
8642                         if (sc->
8643                             port.supported[idx] & ELINK_SUPPORTED_10baseT_Half)
8644                         {
8645                                 sc->link_params.req_line_speed[idx] =
8646                                     ELINK_SPEED_10;
8647                                 sc->link_params.req_duplex[idx] = DUPLEX_HALF;
8648                                 sc->port.advertising[idx] |=
8649                                     (ADVERTISED_10baseT_Half | ADVERTISED_TP);
8650                         } else {
8651                                 PMD_DRV_LOG(ERR, sc,
8652                                             "Invalid NVRAM config link_config=0x%08x "
8653                                             "speed_cap_mask=0x%08x",
8654                                             link_config,
8655                                             sc->
8656                                             link_params.speed_cap_mask[idx]);
8657                                 return;
8658                         }
8659                         break;
8660
8661                 case PORT_FEATURE_LINK_SPEED_100M_FULL:
8662                         if (sc->
8663                             port.supported[idx] & ELINK_SUPPORTED_100baseT_Full)
8664                         {
8665                                 sc->link_params.req_line_speed[idx] =
8666                                     ELINK_SPEED_100;
8667                                 sc->port.advertising[idx] |=
8668                                     (ADVERTISED_100baseT_Full | ADVERTISED_TP);
8669                         } else {
8670                                 PMD_DRV_LOG(ERR, sc,
8671                                             "Invalid NVRAM config link_config=0x%08x "
8672                                             "speed_cap_mask=0x%08x",
8673                                             link_config,
8674                                             sc->
8675                                             link_params.speed_cap_mask[idx]);
8676                                 return;
8677                         }
8678                         break;
8679
8680                 case PORT_FEATURE_LINK_SPEED_100M_HALF:
8681                         if (sc->
8682                             port.supported[idx] & ELINK_SUPPORTED_100baseT_Half)
8683                         {
8684                                 sc->link_params.req_line_speed[idx] =
8685                                     ELINK_SPEED_100;
8686                                 sc->link_params.req_duplex[idx] = DUPLEX_HALF;
8687                                 sc->port.advertising[idx] |=
8688                                     (ADVERTISED_100baseT_Half | ADVERTISED_TP);
8689                         } else {
8690                                 PMD_DRV_LOG(ERR, sc,
8691                                             "Invalid NVRAM config link_config=0x%08x "
8692                                             "speed_cap_mask=0x%08x",
8693                                             link_config,
8694                                             sc->
8695                                             link_params.speed_cap_mask[idx]);
8696                                 return;
8697                         }
8698                         break;
8699
8700                 case PORT_FEATURE_LINK_SPEED_1G:
8701                         if (sc->port.supported[idx] &
8702                             ELINK_SUPPORTED_1000baseT_Full) {
8703                                 sc->link_params.req_line_speed[idx] =
8704                                     ELINK_SPEED_1000;
8705                                 sc->port.advertising[idx] |=
8706                                     (ADVERTISED_1000baseT_Full | ADVERTISED_TP);
8707                         } else {
8708                                 PMD_DRV_LOG(ERR, sc,
8709                                             "Invalid NVRAM config link_config=0x%08x "
8710                                             "speed_cap_mask=0x%08x",
8711                                             link_config,
8712                                             sc->
8713                                             link_params.speed_cap_mask[idx]);
8714                                 return;
8715                         }
8716                         break;
8717
8718                 case PORT_FEATURE_LINK_SPEED_2_5G:
8719                         if (sc->port.supported[idx] &
8720                             ELINK_SUPPORTED_2500baseX_Full) {
8721                                 sc->link_params.req_line_speed[idx] =
8722                                     ELINK_SPEED_2500;
8723                                 sc->port.advertising[idx] |=
8724                                     (ADVERTISED_2500baseX_Full | ADVERTISED_TP);
8725                         } else {
8726                                 PMD_DRV_LOG(ERR, sc,
8727                                             "Invalid NVRAM config link_config=0x%08x "
8728                                             "speed_cap_mask=0x%08x",
8729                                             link_config,
8730                                             sc->
8731                                             link_params.speed_cap_mask[idx]);
8732                                 return;
8733                         }
8734                         break;
8735
8736                 case PORT_FEATURE_LINK_SPEED_10G_CX4:
8737                         if (sc->port.supported[idx] &
8738                             ELINK_SUPPORTED_10000baseT_Full) {
8739                                 sc->link_params.req_line_speed[idx] =
8740                                     ELINK_SPEED_10000;
8741                                 sc->port.advertising[idx] |=
8742                                     (ADVERTISED_10000baseT_Full |
8743                                      ADVERTISED_FIBRE);
8744                         } else {
8745                                 PMD_DRV_LOG(ERR, sc,
8746                                             "Invalid NVRAM config link_config=0x%08x "
8747                                             "speed_cap_mask=0x%08x",
8748                                             link_config,
8749                                             sc->
8750                                             link_params.speed_cap_mask[idx]);
8751                                 return;
8752                         }
8753                         break;
8754
8755                 case PORT_FEATURE_LINK_SPEED_20G:
8756                         sc->link_params.req_line_speed[idx] = ELINK_SPEED_20000;
8757                         break;
8758
8759                 default:
8760                         PMD_DRV_LOG(ERR, sc,
8761                                     "Invalid NVRAM config link_config=0x%08x "
8762                                     "speed_cap_mask=0x%08x", link_config,
8763                                     sc->link_params.speed_cap_mask[idx]);
8764                         sc->link_params.req_line_speed[idx] =
8765                             ELINK_SPEED_AUTO_NEG;
8766                         sc->port.advertising[idx] = sc->port.supported[idx];
8767                         break;
8768                 }
8769
8770                 sc->link_params.req_flow_ctrl[idx] =
8771                     (link_config & PORT_FEATURE_FLOW_CONTROL_MASK);
8772
8773                 if (sc->link_params.req_flow_ctrl[idx] == ELINK_FLOW_CTRL_AUTO) {
8774                         if (!
8775                             (sc->
8776                              port.supported[idx] & ELINK_SUPPORTED_Autoneg)) {
8777                                 sc->link_params.req_flow_ctrl[idx] =
8778                                     ELINK_FLOW_CTRL_NONE;
8779                         } else {
8780                                 bnx2x_set_requested_fc(sc);
8781                         }
8782                 }
8783         }
8784 }
8785
8786 static void bnx2x_get_phy_info(struct bnx2x_softc *sc)
8787 {
8788         uint8_t port = SC_PORT(sc);
8789         uint32_t eee_mode;
8790
8791         PMD_INIT_FUNC_TRACE(sc);
8792
8793         /* shmem data already read in bnx2x_get_shmem_info() */
8794
8795         bnx2x_link_settings_supported(sc, sc->link_params.switch_cfg);
8796         bnx2x_link_settings_requested(sc);
8797
8798         /* configure link feature according to nvram value */
8799         eee_mode =
8800             (((SHMEM_RD(sc, dev_info.port_feature_config[port].eee_power_mode))
8801               & PORT_FEAT_CFG_EEE_POWER_MODE_MASK) >>
8802              PORT_FEAT_CFG_EEE_POWER_MODE_SHIFT);
8803         if (eee_mode != PORT_FEAT_CFG_EEE_POWER_MODE_DISABLED) {
8804                 sc->link_params.eee_mode = (ELINK_EEE_MODE_ADV_LPI |
8805                                             ELINK_EEE_MODE_ENABLE_LPI |
8806                                             ELINK_EEE_MODE_OUTPUT_TIME);
8807         } else {
8808                 sc->link_params.eee_mode = 0;
8809         }
8810
8811         /* get the media type */
8812         bnx2x_media_detect(sc);
8813 }
8814
8815 static void bnx2x_set_modes_bitmap(struct bnx2x_softc *sc)
8816 {
8817         uint32_t flags = MODE_ASIC | MODE_PORT2;
8818
8819         if (CHIP_IS_E2(sc)) {
8820                 flags |= MODE_E2;
8821         } else if (CHIP_IS_E3(sc)) {
8822                 flags |= MODE_E3;
8823                 if (CHIP_REV(sc) == CHIP_REV_Ax) {
8824                         flags |= MODE_E3_A0;
8825                 } else {        /*if (CHIP_REV(sc) == CHIP_REV_Bx) */
8826
8827                         flags |= MODE_E3_B0 | MODE_COS3;
8828                 }
8829         }
8830
8831         if (IS_MF(sc)) {
8832                 flags |= MODE_MF;
8833                 switch (sc->devinfo.mf_info.mf_mode) {
8834                 case MULTI_FUNCTION_SD:
8835                         flags |= MODE_MF_SD;
8836                         break;
8837                 case MULTI_FUNCTION_SI:
8838                         flags |= MODE_MF_SI;
8839                         break;
8840                 case MULTI_FUNCTION_AFEX:
8841                         flags |= MODE_MF_AFEX;
8842                         break;
8843                 }
8844         } else {
8845                 flags |= MODE_SF;
8846         }
8847
8848 #if defined(__LITTLE_ENDIAN)
8849         flags |= MODE_LITTLE_ENDIAN;
8850 #else /* __BIG_ENDIAN */
8851         flags |= MODE_BIG_ENDIAN;
8852 #endif
8853
8854         INIT_MODE_FLAGS(sc) = flags;
8855 }
8856
8857 int bnx2x_alloc_hsi_mem(struct bnx2x_softc *sc)
8858 {
8859         struct bnx2x_fastpath *fp;
8860         char buf[32];
8861         uint32_t i;
8862
8863         if (IS_PF(sc)) {
8864 /************************/
8865 /* DEFAULT STATUS BLOCK */
8866 /************************/
8867
8868                 if (bnx2x_dma_alloc(sc, sizeof(struct host_sp_status_block),
8869                                   &sc->def_sb_dma, "def_sb",
8870                                   RTE_CACHE_LINE_SIZE) != 0) {
8871                         return -1;
8872                 }
8873
8874                 sc->def_sb =
8875                     (struct host_sp_status_block *)sc->def_sb_dma.vaddr;
8876 /***************/
8877 /* EVENT QUEUE */
8878 /***************/
8879
8880                 if (bnx2x_dma_alloc(sc, BNX2X_PAGE_SIZE,
8881                                   &sc->eq_dma, "ev_queue",
8882                                   RTE_CACHE_LINE_SIZE) != 0) {
8883                         sc->def_sb = NULL;
8884                         return -1;
8885                 }
8886
8887                 sc->eq = (union event_ring_elem *)sc->eq_dma.vaddr;
8888
8889 /*************/
8890 /* SLOW PATH */
8891 /*************/
8892
8893                 if (bnx2x_dma_alloc(sc, sizeof(struct bnx2x_slowpath),
8894                                   &sc->sp_dma, "sp",
8895                                   RTE_CACHE_LINE_SIZE) != 0) {
8896                         sc->eq = NULL;
8897                         sc->def_sb = NULL;
8898                         return -1;
8899                 }
8900
8901                 sc->sp = (struct bnx2x_slowpath *)sc->sp_dma.vaddr;
8902
8903 /*******************/
8904 /* SLOW PATH QUEUE */
8905 /*******************/
8906
8907                 if (bnx2x_dma_alloc(sc, BNX2X_PAGE_SIZE,
8908                                   &sc->spq_dma, "sp_queue",
8909                                   RTE_CACHE_LINE_SIZE) != 0) {
8910                         sc->sp = NULL;
8911                         sc->eq = NULL;
8912                         sc->def_sb = NULL;
8913                         return -1;
8914                 }
8915
8916                 sc->spq = (struct eth_spe *)sc->spq_dma.vaddr;
8917
8918 /***************************/
8919 /* FW DECOMPRESSION BUFFER */
8920 /***************************/
8921
8922                 if (bnx2x_dma_alloc(sc, FW_BUF_SIZE, &sc->gz_buf_dma,
8923                                   "fw_buf", RTE_CACHE_LINE_SIZE) != 0) {
8924                         sc->spq = NULL;
8925                         sc->sp = NULL;
8926                         sc->eq = NULL;
8927                         sc->def_sb = NULL;
8928                         return -1;
8929                 }
8930
8931                 sc->gz_buf = (void *)sc->gz_buf_dma.vaddr;
8932         }
8933
8934         /*************/
8935         /* FASTPATHS */
8936         /*************/
8937
8938         /* allocate DMA memory for each fastpath structure */
8939         for (i = 0; i < sc->num_queues; i++) {
8940                 fp = &sc->fp[i];
8941                 fp->sc = sc;
8942                 fp->index = i;
8943
8944 /*******************/
8945 /* FP STATUS BLOCK */
8946 /*******************/
8947
8948                 snprintf(buf, sizeof(buf), "fp_%d_sb", i);
8949                 if (bnx2x_dma_alloc(sc, sizeof(union bnx2x_host_hc_status_block),
8950                                   &fp->sb_dma, buf, RTE_CACHE_LINE_SIZE) != 0) {
8951                         PMD_DRV_LOG(NOTICE, sc, "Failed to alloc %s", buf);
8952                         return -1;
8953                 } else {
8954                         if (CHIP_IS_E2E3(sc)) {
8955                                 fp->status_block.e2_sb =
8956                                     (struct host_hc_status_block_e2 *)
8957                                     fp->sb_dma.vaddr;
8958                         } else {
8959                                 fp->status_block.e1x_sb =
8960                                     (struct host_hc_status_block_e1x *)
8961                                     fp->sb_dma.vaddr;
8962                         }
8963                 }
8964         }
8965
8966         return 0;
8967 }
8968
8969 void bnx2x_free_hsi_mem(struct bnx2x_softc *sc)
8970 {
8971         struct bnx2x_fastpath *fp;
8972         int i;
8973
8974         for (i = 0; i < sc->num_queues; i++) {
8975                 fp = &sc->fp[i];
8976
8977 /*******************/
8978 /* FP STATUS BLOCK */
8979 /*******************/
8980
8981                 memset(&fp->status_block, 0, sizeof(fp->status_block));
8982         }
8983
8984         /***************************/
8985         /* FW DECOMPRESSION BUFFER */
8986         /***************************/
8987
8988         sc->gz_buf = NULL;
8989
8990         /*******************/
8991         /* SLOW PATH QUEUE */
8992         /*******************/
8993
8994         sc->spq = NULL;
8995
8996         /*************/
8997         /* SLOW PATH */
8998         /*************/
8999
9000         sc->sp = NULL;
9001
9002         /***************/
9003         /* EVENT QUEUE */
9004         /***************/
9005
9006         sc->eq = NULL;
9007
9008         /************************/
9009         /* DEFAULT STATUS BLOCK */
9010         /************************/
9011
9012         sc->def_sb = NULL;
9013
9014 }
9015
9016 /*
9017 * Previous driver DMAE transaction may have occurred when pre-boot stage
9018 * ended and boot began. This would invalidate the addresses of the
9019 * transaction, resulting in was-error bit set in the PCI causing all
9020 * hw-to-host PCIe transactions to timeout. If this happened we want to clear
9021 * the interrupt which detected this from the pglueb and the was-done bit
9022 */
9023 static void bnx2x_prev_interrupted_dmae(struct bnx2x_softc *sc)
9024 {
9025         uint32_t val;
9026
9027         if (!CHIP_IS_E1x(sc)) {
9028                 val = REG_RD(sc, PGLUE_B_REG_PGLUE_B_INT_STS);
9029                 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_WAS_ERROR_ATTN) {
9030                         REG_WR(sc, PGLUE_B_REG_WAS_ERROR_PF_7_0_CLR,
9031                                1 << SC_FUNC(sc));
9032                 }
9033         }
9034 }
9035
9036 static int bnx2x_prev_mcp_done(struct bnx2x_softc *sc)
9037 {
9038         uint32_t rc = bnx2x_fw_command(sc, DRV_MSG_CODE_UNLOAD_DONE,
9039                                      DRV_MSG_CODE_UNLOAD_SKIP_LINK_RESET);
9040         if (!rc) {
9041                 PMD_DRV_LOG(NOTICE, sc, "MCP response failure, aborting");
9042                 return -1;
9043         }
9044
9045         return 0;
9046 }
9047
9048 static struct bnx2x_prev_list_node *bnx2x_prev_path_get_entry(struct bnx2x_softc *sc)
9049 {
9050         struct bnx2x_prev_list_node *tmp;
9051
9052         LIST_FOREACH(tmp, &bnx2x_prev_list, node) {
9053                 if ((sc->pcie_bus == tmp->bus) &&
9054                     (sc->pcie_device == tmp->slot) &&
9055                     (SC_PATH(sc) == tmp->path)) {
9056                         return tmp;
9057                 }
9058         }
9059
9060         return NULL;
9061 }
9062
9063 static uint8_t bnx2x_prev_is_path_marked(struct bnx2x_softc *sc)
9064 {
9065         struct bnx2x_prev_list_node *tmp;
9066         int rc = FALSE;
9067
9068         rte_spinlock_lock(&bnx2x_prev_mtx);
9069
9070         tmp = bnx2x_prev_path_get_entry(sc);
9071         if (tmp) {
9072                 if (tmp->aer) {
9073                         PMD_DRV_LOG(DEBUG, sc,
9074                                     "Path %d/%d/%d was marked by AER",
9075                                     sc->pcie_bus, sc->pcie_device, SC_PATH(sc));
9076                 } else {
9077                         rc = TRUE;
9078                         PMD_DRV_LOG(DEBUG, sc,
9079                                     "Path %d/%d/%d was already cleaned from previous drivers",
9080                                     sc->pcie_bus, sc->pcie_device, SC_PATH(sc));
9081                 }
9082         }
9083
9084         rte_spinlock_unlock(&bnx2x_prev_mtx);
9085
9086         return rc;
9087 }
9088
9089 static int bnx2x_prev_mark_path(struct bnx2x_softc *sc, uint8_t after_undi)
9090 {
9091         struct bnx2x_prev_list_node *tmp;
9092
9093         rte_spinlock_lock(&bnx2x_prev_mtx);
9094
9095         /* Check whether the entry for this path already exists */
9096         tmp = bnx2x_prev_path_get_entry(sc);
9097         if (tmp) {
9098                 if (!tmp->aer) {
9099                         PMD_DRV_LOG(DEBUG, sc,
9100                                     "Re-marking AER in path %d/%d/%d",
9101                                     sc->pcie_bus, sc->pcie_device, SC_PATH(sc));
9102                 } else {
9103                         PMD_DRV_LOG(DEBUG, sc,
9104                                     "Removing AER indication from path %d/%d/%d",
9105                                     sc->pcie_bus, sc->pcie_device, SC_PATH(sc));
9106                         tmp->aer = 0;
9107                 }
9108
9109                 rte_spinlock_unlock(&bnx2x_prev_mtx);
9110                 return 0;
9111         }
9112
9113         rte_spinlock_unlock(&bnx2x_prev_mtx);
9114
9115         /* Create an entry for this path and add it */
9116         tmp = rte_malloc("", sizeof(struct bnx2x_prev_list_node),
9117                          RTE_CACHE_LINE_SIZE);
9118         if (!tmp) {
9119                 PMD_DRV_LOG(NOTICE, sc, "Failed to allocate 'bnx2x_prev_list_node'");
9120                 return -1;
9121         }
9122
9123         tmp->bus = sc->pcie_bus;
9124         tmp->slot = sc->pcie_device;
9125         tmp->path = SC_PATH(sc);
9126         tmp->aer = 0;
9127         tmp->undi = after_undi ? (1 << SC_PORT(sc)) : 0;
9128
9129         rte_spinlock_lock(&bnx2x_prev_mtx);
9130
9131         LIST_INSERT_HEAD(&bnx2x_prev_list, tmp, node);
9132
9133         rte_spinlock_unlock(&bnx2x_prev_mtx);
9134
9135         return 0;
9136 }
9137
9138 static int bnx2x_do_flr(struct bnx2x_softc *sc)
9139 {
9140         int i;
9141
9142         /* only E2 and onwards support FLR */
9143         if (CHIP_IS_E1x(sc)) {
9144                 PMD_DRV_LOG(WARNING, sc, "FLR not supported in E1H");
9145                 return -1;
9146         }
9147
9148         /* only bootcode REQ_BC_VER_4_INITIATE_FLR and onwards support flr */
9149         if (sc->devinfo.bc_ver < REQ_BC_VER_4_INITIATE_FLR) {
9150                 PMD_DRV_LOG(WARNING, sc,
9151                             "FLR not supported by BC_VER: 0x%08x",
9152                             sc->devinfo.bc_ver);
9153                 return -1;
9154         }
9155
9156         /* Wait for Transaction Pending bit clean */
9157         for (i = 0; i < 4; i++) {
9158                 if (i) {
9159                         DELAY(((1 << (i - 1)) * 100) * 1000);
9160                 }
9161
9162                 if (!bnx2x_is_pcie_pending(sc)) {
9163                         goto clear;
9164                 }
9165         }
9166
9167         PMD_DRV_LOG(NOTICE, sc, "PCIE transaction is not cleared, "
9168                     "proceeding with reset anyway");
9169
9170 clear:
9171         bnx2x_fw_command(sc, DRV_MSG_CODE_INITIATE_FLR, 0);
9172
9173         return 0;
9174 }
9175
9176 struct bnx2x_mac_vals {
9177         uint32_t xmac_addr;
9178         uint32_t xmac_val;
9179         uint32_t emac_addr;
9180         uint32_t emac_val;
9181         uint32_t umac_addr;
9182         uint32_t umac_val;
9183         uint32_t bmac_addr;
9184         uint32_t bmac_val[2];
9185 };
9186
9187 static void
9188 bnx2x_prev_unload_close_mac(struct bnx2x_softc *sc, struct bnx2x_mac_vals *vals)
9189 {
9190         uint32_t val, base_addr, offset, mask, reset_reg;
9191         uint8_t mac_stopped = FALSE;
9192         uint8_t port = SC_PORT(sc);
9193         uint32_t wb_data[2];
9194
9195         /* reset addresses as they also mark which values were changed */
9196         vals->bmac_addr = 0;
9197         vals->umac_addr = 0;
9198         vals->xmac_addr = 0;
9199         vals->emac_addr = 0;
9200
9201         reset_reg = REG_RD(sc, MISC_REG_RESET_REG_2);
9202
9203         if (!CHIP_IS_E3(sc)) {
9204                 val = REG_RD(sc, NIG_REG_BMAC0_REGS_OUT_EN + port * 4);
9205                 mask = MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port;
9206                 if ((mask & reset_reg) && val) {
9207                         base_addr = SC_PORT(sc) ? NIG_REG_INGRESS_BMAC1_MEM
9208                             : NIG_REG_INGRESS_BMAC0_MEM;
9209                         offset = CHIP_IS_E2(sc) ? BIGMAC2_REGISTER_BMAC_CONTROL
9210                             : BIGMAC_REGISTER_BMAC_CONTROL;
9211
9212                         /*
9213                          * use rd/wr since we cannot use dmae. This is safe
9214                          * since MCP won't access the bus due to the request
9215                          * to unload, and no function on the path can be
9216                          * loaded at this time.
9217                          */
9218                         wb_data[0] = REG_RD(sc, base_addr + offset);
9219                         wb_data[1] = REG_RD(sc, base_addr + offset + 0x4);
9220                         vals->bmac_addr = base_addr + offset;
9221                         vals->bmac_val[0] = wb_data[0];
9222                         vals->bmac_val[1] = wb_data[1];
9223                         wb_data[0] &= ~ELINK_BMAC_CONTROL_RX_ENABLE;
9224                         REG_WR(sc, vals->bmac_addr, wb_data[0]);
9225                         REG_WR(sc, vals->bmac_addr + 0x4, wb_data[1]);
9226                 }
9227
9228                 vals->emac_addr = NIG_REG_NIG_EMAC0_EN + SC_PORT(sc) * 4;
9229                 vals->emac_val = REG_RD(sc, vals->emac_addr);
9230                 REG_WR(sc, vals->emac_addr, 0);
9231                 mac_stopped = TRUE;
9232         } else {
9233                 if (reset_reg & MISC_REGISTERS_RESET_REG_2_XMAC) {
9234                         base_addr = SC_PORT(sc) ? GRCBASE_XMAC1 : GRCBASE_XMAC0;
9235                         val = REG_RD(sc, base_addr + XMAC_REG_PFC_CTRL_HI);
9236                         REG_WR(sc, base_addr + XMAC_REG_PFC_CTRL_HI,
9237                                val & ~(1 << 1));
9238                         REG_WR(sc, base_addr + XMAC_REG_PFC_CTRL_HI,
9239                                val | (1 << 1));
9240                         vals->xmac_addr = base_addr + XMAC_REG_CTRL;
9241                         vals->xmac_val = REG_RD(sc, vals->xmac_addr);
9242                         REG_WR(sc, vals->xmac_addr, 0);
9243                         mac_stopped = TRUE;
9244                 }
9245
9246                 mask = MISC_REGISTERS_RESET_REG_2_UMAC0 << port;
9247                 if (mask & reset_reg) {
9248                         base_addr = SC_PORT(sc) ? GRCBASE_UMAC1 : GRCBASE_UMAC0;
9249                         vals->umac_addr = base_addr + UMAC_REG_COMMAND_CONFIG;
9250                         vals->umac_val = REG_RD(sc, vals->umac_addr);
9251                         REG_WR(sc, vals->umac_addr, 0);
9252                         mac_stopped = TRUE;
9253                 }
9254         }
9255
9256         if (mac_stopped) {
9257                 DELAY(20000);
9258         }
9259 }
9260
9261 #define BNX2X_PREV_UNDI_PROD_ADDR(p)  (BAR_TSTRORM_INTMEM + 0x1508 + ((p) << 4))
9262 #define BNX2X_PREV_UNDI_RCQ(val)      ((val) & 0xffff)
9263 #define BNX2X_PREV_UNDI_BD(val)       ((val) >> 16 & 0xffff)
9264 #define BNX2X_PREV_UNDI_PROD(rcq, bd) ((bd) << 16 | (rcq))
9265
9266 static void
9267 bnx2x_prev_unload_undi_inc(struct bnx2x_softc *sc, uint8_t port, uint8_t inc)
9268 {
9269         uint16_t rcq, bd;
9270         uint32_t tmp_reg = REG_RD(sc, BNX2X_PREV_UNDI_PROD_ADDR(port));
9271
9272         rcq = BNX2X_PREV_UNDI_RCQ(tmp_reg) + inc;
9273         bd = BNX2X_PREV_UNDI_BD(tmp_reg) + inc;
9274
9275         tmp_reg = BNX2X_PREV_UNDI_PROD(rcq, bd);
9276         REG_WR(sc, BNX2X_PREV_UNDI_PROD_ADDR(port), tmp_reg);
9277 }
9278
9279 static int bnx2x_prev_unload_common(struct bnx2x_softc *sc)
9280 {
9281         uint32_t reset_reg, tmp_reg = 0, rc;
9282         uint8_t prev_undi = FALSE;
9283         struct bnx2x_mac_vals mac_vals;
9284         uint32_t timer_count = 1000;
9285         uint32_t prev_brb;
9286
9287         /*
9288          * It is possible a previous function received 'common' answer,
9289          * but hasn't loaded yet, therefore creating a scenario of
9290          * multiple functions receiving 'common' on the same path.
9291          */
9292         memset(&mac_vals, 0, sizeof(mac_vals));
9293
9294         if (bnx2x_prev_is_path_marked(sc)) {
9295                 return bnx2x_prev_mcp_done(sc);
9296         }
9297
9298         reset_reg = REG_RD(sc, MISC_REG_RESET_REG_1);
9299
9300         /* Reset should be performed after BRB is emptied */
9301         if (reset_reg & MISC_REGISTERS_RESET_REG_1_RST_BRB1) {
9302                 /* Close the MAC Rx to prevent BRB from filling up */
9303                 bnx2x_prev_unload_close_mac(sc, &mac_vals);
9304
9305                 /* close LLH filters towards the BRB */
9306                 elink_set_rx_filter(&sc->link_params, 0);
9307
9308                 /*
9309                  * Check if the UNDI driver was previously loaded.
9310                  * UNDI driver initializes CID offset for normal bell to 0x7
9311                  */
9312                 if (reset_reg & MISC_REGISTERS_RESET_REG_1_RST_DORQ) {
9313                         tmp_reg = REG_RD(sc, DORQ_REG_NORM_CID_OFST);
9314                         if (tmp_reg == 0x7) {
9315                                 PMD_DRV_LOG(DEBUG, sc, "UNDI previously loaded");
9316                                 prev_undi = TRUE;
9317                                 /* clear the UNDI indication */
9318                                 REG_WR(sc, DORQ_REG_NORM_CID_OFST, 0);
9319                                 /* clear possible idle check errors */
9320                                 REG_RD(sc, NIG_REG_NIG_INT_STS_CLR_0);
9321                         }
9322                 }
9323
9324                 /* wait until BRB is empty */
9325                 tmp_reg = REG_RD(sc, BRB1_REG_NUM_OF_FULL_BLOCKS);
9326                 while (timer_count) {
9327                         prev_brb = tmp_reg;
9328
9329                         tmp_reg = REG_RD(sc, BRB1_REG_NUM_OF_FULL_BLOCKS);
9330                         if (!tmp_reg) {
9331                                 break;
9332                         }
9333
9334                         PMD_DRV_LOG(DEBUG, sc, "BRB still has 0x%08x", tmp_reg);
9335
9336                         /* reset timer as long as BRB actually gets emptied */
9337                         if (prev_brb > tmp_reg) {
9338                                 timer_count = 1000;
9339                         } else {
9340                                 timer_count--;
9341                         }
9342
9343                         /* If UNDI resides in memory, manually increment it */
9344                         if (prev_undi) {
9345                                 bnx2x_prev_unload_undi_inc(sc, SC_PORT(sc), 1);
9346                         }
9347
9348                         DELAY(10);
9349                 }
9350
9351                 if (!timer_count) {
9352                         PMD_DRV_LOG(NOTICE, sc, "Failed to empty BRB");
9353                 }
9354         }
9355
9356         /* No packets are in the pipeline, path is ready for reset */
9357         bnx2x_reset_common(sc);
9358
9359         if (mac_vals.xmac_addr) {
9360                 REG_WR(sc, mac_vals.xmac_addr, mac_vals.xmac_val);
9361         }
9362         if (mac_vals.umac_addr) {
9363                 REG_WR(sc, mac_vals.umac_addr, mac_vals.umac_val);
9364         }
9365         if (mac_vals.emac_addr) {
9366                 REG_WR(sc, mac_vals.emac_addr, mac_vals.emac_val);
9367         }
9368         if (mac_vals.bmac_addr) {
9369                 REG_WR(sc, mac_vals.bmac_addr, mac_vals.bmac_val[0]);
9370                 REG_WR(sc, mac_vals.bmac_addr + 4, mac_vals.bmac_val[1]);
9371         }
9372
9373         rc = bnx2x_prev_mark_path(sc, prev_undi);
9374         if (rc) {
9375                 bnx2x_prev_mcp_done(sc);
9376                 return rc;
9377         }
9378
9379         return bnx2x_prev_mcp_done(sc);
9380 }
9381
9382 static int bnx2x_prev_unload_uncommon(struct bnx2x_softc *sc)
9383 {
9384         int rc;
9385
9386         /* Test if previous unload process was already finished for this path */
9387         if (bnx2x_prev_is_path_marked(sc)) {
9388                 return bnx2x_prev_mcp_done(sc);
9389         }
9390
9391         /*
9392          * If function has FLR capabilities, and existing FW version matches
9393          * the one required, then FLR will be sufficient to clean any residue
9394          * left by previous driver
9395          */
9396         rc = bnx2x_nic_load_analyze_req(sc, FW_MSG_CODE_DRV_LOAD_FUNCTION);
9397         if (!rc) {
9398                 /* fw version is good */
9399                 rc = bnx2x_do_flr(sc);
9400         }
9401
9402         if (!rc) {
9403                 /* FLR was performed */
9404                 return 0;
9405         }
9406
9407         PMD_DRV_LOG(INFO, sc, "Could not FLR");
9408
9409         /* Close the MCP request, return failure */
9410         rc = bnx2x_prev_mcp_done(sc);
9411         if (!rc) {
9412                 rc = BNX2X_PREV_WAIT_NEEDED;
9413         }
9414
9415         return rc;
9416 }
9417
9418 static int bnx2x_prev_unload(struct bnx2x_softc *sc)
9419 {
9420         int time_counter = 10;
9421         uint32_t fw, hw_lock_reg, hw_lock_val;
9422         uint32_t rc = 0;
9423
9424         PMD_INIT_FUNC_TRACE(sc);
9425
9426         /*
9427          * Clear HW from errors which may have resulted from an interrupted
9428          * DMAE transaction.
9429          */
9430         bnx2x_prev_interrupted_dmae(sc);
9431
9432         /* Release previously held locks */
9433         hw_lock_reg = (SC_FUNC(sc) <= 5) ?
9434                         (MISC_REG_DRIVER_CONTROL_1 + SC_FUNC(sc) * 8) :
9435                         (MISC_REG_DRIVER_CONTROL_7 + (SC_FUNC(sc) - 6) * 8);
9436
9437         hw_lock_val = (REG_RD(sc, hw_lock_reg));
9438         if (hw_lock_val) {
9439                 if (hw_lock_val & HW_LOCK_RESOURCE_NVRAM) {
9440                         PMD_DRV_LOG(DEBUG, sc, "Releasing previously held NVRAM lock\n");
9441                         REG_WR(sc, MCP_REG_MCPR_NVM_SW_ARB,
9442                                (MCPR_NVM_SW_ARB_ARB_REQ_CLR1 << SC_PORT(sc)));
9443                 }
9444                 PMD_DRV_LOG(DEBUG, sc, "Releasing previously held HW lock\n");
9445                 REG_WR(sc, hw_lock_reg, 0xffffffff);
9446         }
9447
9448         if (MCPR_ACCESS_LOCK_LOCK & REG_RD(sc, MCP_REG_MCPR_ACCESS_LOCK)) {
9449                 PMD_DRV_LOG(DEBUG, sc, "Releasing previously held ALR\n");
9450                 REG_WR(sc, MCP_REG_MCPR_ACCESS_LOCK, 0);
9451         }
9452
9453         do {
9454                 /* Lock MCP using an unload request */
9455                 fw = bnx2x_fw_command(sc, DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS, 0);
9456                 if (!fw) {
9457                         PMD_DRV_LOG(NOTICE, sc, "MCP response failure, aborting");
9458                         rc = -1;
9459                         break;
9460                 }
9461
9462                 if (fw == FW_MSG_CODE_DRV_UNLOAD_COMMON) {
9463                         rc = bnx2x_prev_unload_common(sc);
9464                         break;
9465                 }
9466
9467                 /* non-common reply from MCP might require looping */
9468                 rc = bnx2x_prev_unload_uncommon(sc);
9469                 if (rc != BNX2X_PREV_WAIT_NEEDED) {
9470                         break;
9471                 }
9472
9473                 DELAY(20000);
9474         } while (--time_counter);
9475
9476         if (!time_counter || rc) {
9477                 PMD_DRV_LOG(NOTICE, sc, "Failed to unload previous driver!");
9478                 rc = -1;
9479         }
9480
9481         return rc;
9482 }
9483
9484 static void
9485 bnx2x_dcbx_set_state(struct bnx2x_softc *sc, uint8_t dcb_on, uint32_t dcbx_enabled)
9486 {
9487         if (!CHIP_IS_E1x(sc)) {
9488                 sc->dcb_state = dcb_on;
9489                 sc->dcbx_enabled = dcbx_enabled;
9490         } else {
9491                 sc->dcb_state = FALSE;
9492                 sc->dcbx_enabled = BNX2X_DCBX_ENABLED_INVALID;
9493         }
9494         PMD_DRV_LOG(DEBUG, sc,
9495                     "DCB state [%s:%s]",
9496                     dcb_on ? "ON" : "OFF",
9497                     (dcbx_enabled == BNX2X_DCBX_ENABLED_OFF) ? "user-mode" :
9498                     (dcbx_enabled ==
9499                      BNX2X_DCBX_ENABLED_ON_NEG_OFF) ? "on-chip static"
9500                     : (dcbx_enabled ==
9501                        BNX2X_DCBX_ENABLED_ON_NEG_ON) ?
9502                     "on-chip with negotiation" : "invalid");
9503 }
9504
9505 static int bnx2x_set_qm_cid_count(struct bnx2x_softc *sc)
9506 {
9507         int cid_count = BNX2X_L2_MAX_CID(sc);
9508
9509         if (CNIC_SUPPORT(sc)) {
9510                 cid_count += CNIC_CID_MAX;
9511         }
9512
9513         return roundup(cid_count, QM_CID_ROUND);
9514 }
9515
9516 static void bnx2x_init_multi_cos(struct bnx2x_softc *sc)
9517 {
9518         int pri, cos;
9519
9520         uint32_t pri_map = 0;
9521
9522         for (pri = 0; pri < BNX2X_MAX_PRIORITY; pri++) {
9523                 cos = ((pri_map & (0xf << (pri * 4))) >> (pri * 4));
9524                 if (cos < sc->max_cos) {
9525                         sc->prio_to_cos[pri] = cos;
9526                 } else {
9527                         PMD_DRV_LOG(WARNING, sc,
9528                                     "Invalid COS %d for priority %d "
9529                                     "(max COS is %d), setting to 0", cos, pri,
9530                                     (sc->max_cos - 1));
9531                         sc->prio_to_cos[pri] = 0;
9532                 }
9533         }
9534 }
9535
9536 static int bnx2x_pci_get_caps(struct bnx2x_softc *sc)
9537 {
9538         struct {
9539                 uint8_t id;
9540                 uint8_t next;
9541         } pci_cap;
9542         uint16_t status;
9543         struct bnx2x_pci_cap *cap;
9544
9545         cap = sc->pci_caps = rte_zmalloc("caps", sizeof(struct bnx2x_pci_cap),
9546                                          RTE_CACHE_LINE_SIZE);
9547         if (!cap) {
9548                 PMD_DRV_LOG(NOTICE, sc, "Failed to allocate memory");
9549                 return -ENOMEM;
9550         }
9551
9552 #ifndef __FreeBSD__
9553         pci_read(sc, PCI_STATUS, &status, 2);
9554         if (!(status & PCI_STATUS_CAP_LIST)) {
9555 #else
9556         pci_read(sc, PCIR_STATUS, &status, 2);
9557         if (!(status & PCIM_STATUS_CAPPRESENT)) {
9558 #endif
9559                 PMD_DRV_LOG(NOTICE, sc, "PCIe capability reading failed");
9560                 return -1;
9561         }
9562
9563 #ifndef __FreeBSD__
9564         pci_read(sc, PCI_CAPABILITY_LIST, &pci_cap.next, 1);
9565 #else
9566         pci_read(sc, PCIR_CAP_PTR, &pci_cap.next, 1);
9567 #endif
9568         while (pci_cap.next) {
9569                 cap->addr = pci_cap.next & ~3;
9570                 pci_read(sc, pci_cap.next & ~3, &pci_cap, 2);
9571                 if (pci_cap.id == 0xff)
9572                         break;
9573                 cap->id = pci_cap.id;
9574                 cap->type = BNX2X_PCI_CAP;
9575                 cap->next = rte_zmalloc("pci_cap",
9576                                         sizeof(struct bnx2x_pci_cap),
9577                                         RTE_CACHE_LINE_SIZE);
9578                 if (!cap->next) {
9579                         PMD_DRV_LOG(NOTICE, sc, "Failed to allocate memory");
9580                         return -ENOMEM;
9581                 }
9582                 cap = cap->next;
9583         }
9584
9585         return 0;
9586 }
9587
9588 static void bnx2x_init_rte(struct bnx2x_softc *sc)
9589 {
9590         if (IS_VF(sc)) {
9591                 sc->max_tx_queues = min(BNX2X_VF_MAX_QUEUES_PER_VF,
9592                                         sc->igu_sb_cnt);
9593                 sc->max_rx_queues = min(BNX2X_VF_MAX_QUEUES_PER_VF,
9594                                         sc->igu_sb_cnt);
9595         } else {
9596                 sc->max_rx_queues = BNX2X_MAX_RSS_COUNT(sc);
9597                 sc->max_tx_queues = sc->max_rx_queues;
9598         }
9599 }
9600
9601 #define FW_HEADER_LEN 104
9602 #define FW_NAME_57711 "/lib/firmware/bnx2x/bnx2x-e1h-7.2.51.0.fw"
9603 #define FW_NAME_57810 "/lib/firmware/bnx2x/bnx2x-e2-7.2.51.0.fw"
9604
9605 void bnx2x_load_firmware(struct bnx2x_softc *sc)
9606 {
9607         const char *fwname;
9608         int f;
9609         struct stat st;
9610
9611         fwname = sc->devinfo.device_id == CHIP_NUM_57711
9612                 ? FW_NAME_57711 : FW_NAME_57810;
9613         f = open(fwname, O_RDONLY);
9614         if (f < 0) {
9615                 PMD_DRV_LOG(NOTICE, sc, "Can't open firmware file");
9616                 return;
9617         }
9618
9619         if (fstat(f, &st) < 0) {
9620                 PMD_DRV_LOG(NOTICE, sc, "Can't stat firmware file");
9621                 close(f);
9622                 return;
9623         }
9624
9625         sc->firmware = rte_zmalloc("bnx2x_fw", st.st_size, RTE_CACHE_LINE_SIZE);
9626         if (!sc->firmware) {
9627                 PMD_DRV_LOG(NOTICE, sc, "Can't allocate memory for firmware");
9628                 close(f);
9629                 return;
9630         }
9631
9632         if (read(f, sc->firmware, st.st_size) != st.st_size) {
9633                 PMD_DRV_LOG(NOTICE, sc, "Can't read firmware data");
9634                 close(f);
9635                 return;
9636         }
9637         close(f);
9638
9639         sc->fw_len = st.st_size;
9640         if (sc->fw_len < FW_HEADER_LEN) {
9641                 PMD_DRV_LOG(NOTICE, sc,
9642                             "Invalid fw size: %" PRIu64, sc->fw_len);
9643                 return;
9644         }
9645         PMD_DRV_LOG(DEBUG, sc, "fw_len = %" PRIu64, sc->fw_len);
9646 }
9647
9648 static void
9649 bnx2x_data_to_init_ops(uint8_t * data, struct raw_op *dst, uint32_t len)
9650 {
9651         uint32_t *src = (uint32_t *) data;
9652         uint32_t i, j, tmp;
9653
9654         for (i = 0, j = 0; i < len / 8; ++i, j += 2) {
9655                 tmp = rte_be_to_cpu_32(src[j]);
9656                 dst[i].op = (tmp >> 24) & 0xFF;
9657                 dst[i].offset = tmp & 0xFFFFFF;
9658                 dst[i].raw_data = rte_be_to_cpu_32(src[j + 1]);
9659         }
9660 }
9661
9662 static void
9663 bnx2x_data_to_init_offsets(uint8_t * data, uint16_t * dst, uint32_t len)
9664 {
9665         uint16_t *src = (uint16_t *) data;
9666         uint32_t i;
9667
9668         for (i = 0; i < len / 2; ++i)
9669                 dst[i] = rte_be_to_cpu_16(src[i]);
9670 }
9671
9672 static void bnx2x_data_to_init_data(uint8_t * data, uint32_t * dst, uint32_t len)
9673 {
9674         uint32_t *src = (uint32_t *) data;
9675         uint32_t i;
9676
9677         for (i = 0; i < len / 4; ++i)
9678                 dst[i] = rte_be_to_cpu_32(src[i]);
9679 }
9680
9681 static void bnx2x_data_to_iro_array(uint8_t * data, struct iro *dst, uint32_t len)
9682 {
9683         uint32_t *src = (uint32_t *) data;
9684         uint32_t i, j, tmp;
9685
9686         for (i = 0, j = 0; i < len / sizeof(struct iro); ++i, ++j) {
9687                 dst[i].base = rte_be_to_cpu_32(src[j++]);
9688                 tmp = rte_be_to_cpu_32(src[j]);
9689                 dst[i].m1 = (tmp >> 16) & 0xFFFF;
9690                 dst[i].m2 = tmp & 0xFFFF;
9691                 ++j;
9692                 tmp = rte_be_to_cpu_32(src[j]);
9693                 dst[i].m3 = (tmp >> 16) & 0xFFFF;
9694                 dst[i].size = tmp & 0xFFFF;
9695         }
9696 }
9697
9698 /*
9699 * Device attach function.
9700 *
9701 * Allocates device resources, performs secondary chip identification, and
9702 * initializes driver instance variables. This function is called from driver
9703 * load after a successful probe.
9704 *
9705 * Returns:
9706 *   0 = Success, >0 = Failure
9707 */
9708 int bnx2x_attach(struct bnx2x_softc *sc)
9709 {
9710         int rc;
9711
9712         PMD_DRV_LOG(DEBUG, sc, "Starting attach...");
9713
9714         rc = bnx2x_pci_get_caps(sc);
9715         if (rc) {
9716                 PMD_DRV_LOG(NOTICE, sc, "PCIe caps reading was failed");
9717                 return rc;
9718         }
9719
9720         sc->state = BNX2X_STATE_CLOSED;
9721
9722         pci_write_long(sc, PCICFG_GRC_ADDRESS, PCICFG_VENDOR_ID_OFFSET);
9723
9724         sc->igu_base_addr = IS_VF(sc) ? PXP_VF_ADDR_IGU_START : BAR_IGU_INTMEM;
9725
9726         /* get PCI capabilites */
9727         bnx2x_probe_pci_caps(sc);
9728
9729         if (sc->devinfo.pcie_msix_cap_reg != 0) {
9730                 uint32_t val;
9731                 pci_read(sc,
9732                          (sc->devinfo.pcie_msix_cap_reg + PCIR_MSIX_CTRL), &val,
9733                          2);
9734                 sc->igu_sb_cnt = (val & PCIM_MSIXCTRL_TABLE_SIZE) + 1;
9735         } else {
9736                 sc->igu_sb_cnt = 1;
9737         }
9738
9739         /* Init RTE stuff */
9740         bnx2x_init_rte(sc);
9741
9742         if (IS_PF(sc)) {
9743                 /* Enable internal target-read (in case we are probed after PF
9744                  * FLR). Must be done prior to any BAR read access. Only for
9745                  * 57712 and up
9746                  */
9747                 if (!CHIP_IS_E1x(sc)) {
9748                         REG_WR(sc, PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_READ,
9749                                1);
9750                         DELAY(200000);
9751                 }
9752
9753                 /* get device info and set params */
9754                 if (bnx2x_get_device_info(sc) != 0) {
9755                         PMD_DRV_LOG(NOTICE, sc, "getting device info");
9756                         return -ENXIO;
9757                 }
9758
9759 /* get phy settings from shmem and 'and' against admin settings */
9760                 bnx2x_get_phy_info(sc);
9761         } else {
9762                 /* Left mac of VF unfilled, PF should set it for VF */
9763                 memset(sc->link_params.mac_addr, 0, ETHER_ADDR_LEN);
9764         }
9765
9766         sc->wol = 0;
9767
9768         /* set the default MTU (changed via ifconfig) */
9769         sc->mtu = ETHER_MTU;
9770
9771         bnx2x_set_modes_bitmap(sc);
9772
9773         /* need to reset chip if UNDI was active */
9774         if (IS_PF(sc) && !BNX2X_NOMCP(sc)) {
9775 /* init fw_seq */
9776                 sc->fw_seq =
9777                     (SHMEM_RD(sc, func_mb[SC_FW_MB_IDX(sc)].drv_mb_header) &
9778                      DRV_MSG_SEQ_NUMBER_MASK);
9779                 PMD_DRV_LOG(DEBUG, sc, "prev unload fw_seq 0x%04x",
9780                             sc->fw_seq);
9781                 bnx2x_prev_unload(sc);
9782         }
9783
9784         bnx2x_dcbx_set_state(sc, FALSE, BNX2X_DCBX_ENABLED_OFF);
9785
9786         /* calculate qm_cid_count */
9787         sc->qm_cid_count = bnx2x_set_qm_cid_count(sc);
9788
9789         sc->max_cos = 1;
9790         bnx2x_init_multi_cos(sc);
9791
9792         return 0;
9793 }
9794
9795 static void
9796 bnx2x_igu_ack_sb(struct bnx2x_softc *sc, uint8_t igu_sb_id, uint8_t segment,
9797                uint16_t index, uint8_t op, uint8_t update)
9798 {
9799         uint32_t igu_addr = sc->igu_base_addr;
9800         igu_addr += (IGU_CMD_INT_ACK_BASE + igu_sb_id) * 8;
9801         bnx2x_igu_ack_sb_gen(sc, segment, index, op, update, igu_addr);
9802 }
9803
9804 static void
9805 bnx2x_ack_sb(struct bnx2x_softc *sc, uint8_t igu_sb_id, uint8_t storm,
9806            uint16_t index, uint8_t op, uint8_t update)
9807 {
9808         if (unlikely(sc->devinfo.int_block == INT_BLOCK_HC))
9809                 bnx2x_hc_ack_sb(sc, igu_sb_id, storm, index, op, update);
9810         else {
9811                 uint8_t segment;
9812                 if (CHIP_INT_MODE_IS_BC(sc)) {
9813                         segment = storm;
9814                 } else if (igu_sb_id != sc->igu_dsb_id) {
9815                         segment = IGU_SEG_ACCESS_DEF;
9816                 } else if (storm == ATTENTION_ID) {
9817                         segment = IGU_SEG_ACCESS_ATTN;
9818                 } else {
9819                         segment = IGU_SEG_ACCESS_DEF;
9820                 }
9821                 bnx2x_igu_ack_sb(sc, igu_sb_id, segment, index, op, update);
9822         }
9823 }
9824
9825 static void
9826 bnx2x_igu_clear_sb_gen(struct bnx2x_softc *sc, uint8_t func, uint8_t idu_sb_id,
9827                      uint8_t is_pf)
9828 {
9829         uint32_t data, ctl, cnt = 100;
9830         uint32_t igu_addr_data = IGU_REG_COMMAND_REG_32LSB_DATA;
9831         uint32_t igu_addr_ctl = IGU_REG_COMMAND_REG_CTRL;
9832         uint32_t igu_addr_ack = IGU_REG_CSTORM_TYPE_0_SB_CLEANUP +
9833             (idu_sb_id / 32) * 4;
9834         uint32_t sb_bit = 1 << (idu_sb_id % 32);
9835         uint32_t func_encode = func |
9836             (is_pf ? 1 : 0) << IGU_FID_ENCODE_IS_PF_SHIFT;
9837         uint32_t addr_encode = IGU_CMD_E2_PROD_UPD_BASE + idu_sb_id;
9838
9839         /* Not supported in BC mode */
9840         if (CHIP_INT_MODE_IS_BC(sc)) {
9841                 return;
9842         }
9843
9844         data = ((IGU_USE_REGISTER_cstorm_type_0_sb_cleanup <<
9845                  IGU_REGULAR_CLEANUP_TYPE_SHIFT) |
9846                 IGU_REGULAR_CLEANUP_SET | IGU_REGULAR_BCLEANUP);
9847
9848         ctl = ((addr_encode << IGU_CTRL_REG_ADDRESS_SHIFT) |
9849                (func_encode << IGU_CTRL_REG_FID_SHIFT) |
9850                (IGU_CTRL_CMD_TYPE_WR << IGU_CTRL_REG_TYPE_SHIFT));
9851
9852         REG_WR(sc, igu_addr_data, data);
9853
9854         mb();
9855
9856         PMD_DRV_LOG(DEBUG, sc, "write 0x%08x to IGU(via GRC) addr 0x%x",
9857                     ctl, igu_addr_ctl);
9858         REG_WR(sc, igu_addr_ctl, ctl);
9859
9860         mb();
9861
9862         /* wait for clean up to finish */
9863         while (!(REG_RD(sc, igu_addr_ack) & sb_bit) && --cnt) {
9864                 DELAY(20000);
9865         }
9866
9867         if (!(REG_RD(sc, igu_addr_ack) & sb_bit)) {
9868                 PMD_DRV_LOG(DEBUG, sc,
9869                             "Unable to finish IGU cleanup: "
9870                             "idu_sb_id %d offset %d bit %d (cnt %d)",
9871                             idu_sb_id, idu_sb_id / 32, idu_sb_id % 32, cnt);
9872         }
9873 }
9874
9875 static void bnx2x_igu_clear_sb(struct bnx2x_softc *sc, uint8_t idu_sb_id)
9876 {
9877         bnx2x_igu_clear_sb_gen(sc, SC_FUNC(sc), idu_sb_id, TRUE /*PF*/);
9878 }
9879
9880 /*******************/
9881 /* ECORE CALLBACKS */
9882 /*******************/
9883
9884 static void bnx2x_reset_common(struct bnx2x_softc *sc)
9885 {
9886         uint32_t val = 0x1400;
9887
9888         PMD_INIT_FUNC_TRACE(sc);
9889
9890         /* reset_common */
9891         REG_WR(sc, (GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR),
9892                0xd3ffff7f);
9893
9894         if (CHIP_IS_E3(sc)) {
9895                 val |= MISC_REGISTERS_RESET_REG_2_MSTAT0;
9896                 val |= MISC_REGISTERS_RESET_REG_2_MSTAT1;
9897         }
9898
9899         REG_WR(sc, (GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR), val);
9900 }
9901
9902 static void bnx2x_common_init_phy(struct bnx2x_softc *sc)
9903 {
9904         uint32_t shmem_base[2];
9905         uint32_t shmem2_base[2];
9906
9907         /* Avoid common init in case MFW supports LFA */
9908         if (SHMEM2_RD(sc, size) >
9909             (uint32_t) offsetof(struct shmem2_region,
9910                                 lfa_host_addr[SC_PORT(sc)])) {
9911                 return;
9912         }
9913
9914         shmem_base[0] = sc->devinfo.shmem_base;
9915         shmem2_base[0] = sc->devinfo.shmem2_base;
9916
9917         if (!CHIP_IS_E1x(sc)) {
9918                 shmem_base[1] = SHMEM2_RD(sc, other_shmem_base_addr);
9919                 shmem2_base[1] = SHMEM2_RD(sc, other_shmem2_base_addr);
9920         }
9921
9922         bnx2x_acquire_phy_lock(sc);
9923         elink_common_init_phy(sc, shmem_base, shmem2_base,
9924                               sc->devinfo.chip_id, 0);
9925         bnx2x_release_phy_lock(sc);
9926 }
9927
9928 static void bnx2x_pf_disable(struct bnx2x_softc *sc)
9929 {
9930         uint32_t val = REG_RD(sc, IGU_REG_PF_CONFIGURATION);
9931
9932         val &= ~IGU_PF_CONF_FUNC_EN;
9933
9934         REG_WR(sc, IGU_REG_PF_CONFIGURATION, val);
9935         REG_WR(sc, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 0);
9936         REG_WR(sc, CFC_REG_WEAK_ENABLE_PF, 0);
9937 }
9938
9939 static void bnx2x_init_pxp(struct bnx2x_softc *sc)
9940 {
9941         uint16_t devctl;
9942         int r_order, w_order;
9943
9944         devctl = bnx2x_pcie_capability_read(sc, PCIR_EXPRESS_DEVICE_CTL);
9945
9946         w_order = ((devctl & PCIM_EXP_CTL_MAX_PAYLOAD) >> 5);
9947         r_order = ((devctl & PCIM_EXP_CTL_MAX_READ_REQUEST) >> 12);
9948
9949         ecore_init_pxp_arb(sc, r_order, w_order);
9950 }
9951
9952 static uint32_t bnx2x_get_pretend_reg(struct bnx2x_softc *sc)
9953 {
9954         uint32_t base = PXP2_REG_PGL_PRETEND_FUNC_F0;
9955         uint32_t stride = (PXP2_REG_PGL_PRETEND_FUNC_F1 - base);
9956         return base + (SC_ABS_FUNC(sc)) * stride;
9957 }
9958
9959 /*
9960  * Called only on E1H or E2.
9961  * When pretending to be PF, the pretend value is the function number 0..7.
9962  * When pretending to be VF, the pretend val is the PF-num:VF-valid:ABS-VFID
9963  * combination.
9964  */
9965 static int bnx2x_pretend_func(struct bnx2x_softc *sc, uint16_t pretend_func_val)
9966 {
9967         uint32_t pretend_reg;
9968
9969         if (CHIP_IS_E1H(sc) && (pretend_func_val > E1H_FUNC_MAX))
9970                 return -1;
9971
9972         /* get my own pretend register */
9973         pretend_reg = bnx2x_get_pretend_reg(sc);
9974         REG_WR(sc, pretend_reg, pretend_func_val);
9975         REG_RD(sc, pretend_reg);
9976         return 0;
9977 }
9978
9979 static void bnx2x_setup_fan_failure_detection(struct bnx2x_softc *sc)
9980 {
9981         int is_required;
9982         uint32_t val;
9983         int port;
9984
9985         is_required = 0;
9986         val = (SHMEM_RD(sc, dev_info.shared_hw_config.config2) &
9987                SHARED_HW_CFG_FAN_FAILURE_MASK);
9988
9989         if (val == SHARED_HW_CFG_FAN_FAILURE_ENABLED) {
9990                 is_required = 1;
9991         }
9992         /*
9993          * The fan failure mechanism is usually related to the PHY type since
9994          * the power consumption of the board is affected by the PHY. Currently,
9995          * fan is required for most designs with SFX7101, BNX2X8727 and BNX2X8481.
9996          */
9997         else if (val == SHARED_HW_CFG_FAN_FAILURE_PHY_TYPE) {
9998                 for (port = PORT_0; port < PORT_MAX; port++) {
9999                         is_required |= elink_fan_failure_det_req(sc,
10000                                                                  sc->
10001                                                                  devinfo.shmem_base,
10002                                                                  sc->
10003                                                                  devinfo.shmem2_base,
10004                                                                  port);
10005                 }
10006         }
10007
10008         if (is_required == 0) {
10009                 return;
10010         }
10011
10012         /* Fan failure is indicated by SPIO 5 */
10013         bnx2x_set_spio(sc, MISC_SPIO_SPIO5, MISC_SPIO_INPUT_HI_Z);
10014
10015         /* set to active low mode */
10016         val = REG_RD(sc, MISC_REG_SPIO_INT);
10017         val |= (MISC_SPIO_SPIO5 << MISC_SPIO_INT_OLD_SET_POS);
10018         REG_WR(sc, MISC_REG_SPIO_INT, val);
10019
10020         /* enable interrupt to signal the IGU */
10021         val = REG_RD(sc, MISC_REG_SPIO_EVENT_EN);
10022         val |= MISC_SPIO_SPIO5;
10023         REG_WR(sc, MISC_REG_SPIO_EVENT_EN, val);
10024 }
10025
10026 static void bnx2x_enable_blocks_attention(struct bnx2x_softc *sc)
10027 {
10028         uint32_t val;
10029
10030         REG_WR(sc, PXP_REG_PXP_INT_MASK_0, 0);
10031         if (!CHIP_IS_E1x(sc)) {
10032                 REG_WR(sc, PXP_REG_PXP_INT_MASK_1, 0x40);
10033         } else {
10034                 REG_WR(sc, PXP_REG_PXP_INT_MASK_1, 0);
10035         }
10036         REG_WR(sc, DORQ_REG_DORQ_INT_MASK, 0);
10037         REG_WR(sc, CFC_REG_CFC_INT_MASK, 0);
10038         /*
10039          * mask read length error interrupts in brb for parser
10040          * (parsing unit and 'checksum and crc' unit)
10041          * these errors are legal (PU reads fixed length and CAC can cause
10042          * read length error on truncated packets)
10043          */
10044         REG_WR(sc, BRB1_REG_BRB1_INT_MASK, 0xFC00);
10045         REG_WR(sc, QM_REG_QM_INT_MASK, 0);
10046         REG_WR(sc, TM_REG_TM_INT_MASK, 0);
10047         REG_WR(sc, XSDM_REG_XSDM_INT_MASK_0, 0);
10048         REG_WR(sc, XSDM_REG_XSDM_INT_MASK_1, 0);
10049         REG_WR(sc, XCM_REG_XCM_INT_MASK, 0);
10050         /*      REG_WR(sc, XSEM_REG_XSEM_INT_MASK_0, 0); */
10051         /*      REG_WR(sc, XSEM_REG_XSEM_INT_MASK_1, 0); */
10052         REG_WR(sc, USDM_REG_USDM_INT_MASK_0, 0);
10053         REG_WR(sc, USDM_REG_USDM_INT_MASK_1, 0);
10054         REG_WR(sc, UCM_REG_UCM_INT_MASK, 0);
10055         /*      REG_WR(sc, USEM_REG_USEM_INT_MASK_0, 0); */
10056         /*      REG_WR(sc, USEM_REG_USEM_INT_MASK_1, 0); */
10057         REG_WR(sc, GRCBASE_UPB + PB_REG_PB_INT_MASK, 0);
10058         REG_WR(sc, CSDM_REG_CSDM_INT_MASK_0, 0);
10059         REG_WR(sc, CSDM_REG_CSDM_INT_MASK_1, 0);
10060         REG_WR(sc, CCM_REG_CCM_INT_MASK, 0);
10061         /*      REG_WR(sc, CSEM_REG_CSEM_INT_MASK_0, 0); */
10062         /*      REG_WR(sc, CSEM_REG_CSEM_INT_MASK_1, 0); */
10063
10064         val = (PXP2_PXP2_INT_MASK_0_REG_PGL_CPL_AFT |
10065                PXP2_PXP2_INT_MASK_0_REG_PGL_CPL_OF |
10066                PXP2_PXP2_INT_MASK_0_REG_PGL_PCIE_ATTN);
10067         if (!CHIP_IS_E1x(sc)) {
10068                 val |= (PXP2_PXP2_INT_MASK_0_REG_PGL_READ_BLOCKED |
10069                         PXP2_PXP2_INT_MASK_0_REG_PGL_WRITE_BLOCKED);
10070         }
10071         REG_WR(sc, PXP2_REG_PXP2_INT_MASK_0, val);
10072
10073         REG_WR(sc, TSDM_REG_TSDM_INT_MASK_0, 0);
10074         REG_WR(sc, TSDM_REG_TSDM_INT_MASK_1, 0);
10075         REG_WR(sc, TCM_REG_TCM_INT_MASK, 0);
10076         /*      REG_WR(sc, TSEM_REG_TSEM_INT_MASK_0, 0); */
10077
10078         if (!CHIP_IS_E1x(sc)) {
10079 /* enable VFC attentions: bits 11 and 12, bits 31:13 reserved */
10080                 REG_WR(sc, TSEM_REG_TSEM_INT_MASK_1, 0x07ff);
10081         }
10082
10083         REG_WR(sc, CDU_REG_CDU_INT_MASK, 0);
10084         REG_WR(sc, DMAE_REG_DMAE_INT_MASK, 0);
10085         /*      REG_WR(sc, MISC_REG_MISC_INT_MASK, 0); */
10086         REG_WR(sc, PBF_REG_PBF_INT_MASK, 0x18); /* bit 3,4 masked */
10087 }
10088
10089 /**
10090  * bnx2x_init_hw_common - initialize the HW at the COMMON phase.
10091  *
10092  * @sc:     driver handle
10093  */
10094 static int bnx2x_init_hw_common(struct bnx2x_softc *sc)
10095 {
10096         uint8_t abs_func_id;
10097         uint32_t val;
10098
10099         PMD_DRV_LOG(DEBUG, sc,
10100                     "starting common init for func %d", SC_ABS_FUNC(sc));
10101
10102         /*
10103          * take the RESET lock to protect undi_unload flow from accessing
10104          * registers while we are resetting the chip
10105          */
10106         bnx2x_acquire_hw_lock(sc, HW_LOCK_RESOURCE_RESET);
10107
10108         bnx2x_reset_common(sc);
10109
10110         REG_WR(sc, (GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET), 0xffffffff);
10111
10112         val = 0xfffc;
10113         if (CHIP_IS_E3(sc)) {
10114                 val |= MISC_REGISTERS_RESET_REG_2_MSTAT0;
10115                 val |= MISC_REGISTERS_RESET_REG_2_MSTAT1;
10116         }
10117
10118         REG_WR(sc, (GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET), val);
10119
10120         bnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_RESET);
10121
10122         ecore_init_block(sc, BLOCK_MISC, PHASE_COMMON);
10123
10124         if (!CHIP_IS_E1x(sc)) {
10125 /*
10126  * 4-port mode or 2-port mode we need to turn off master-enable for
10127  * everyone. After that we turn it back on for self. So, we disregard
10128  * multi-function, and always disable all functions on the given path,
10129  * this means 0,2,4,6 for path 0 and 1,3,5,7 for path 1
10130  */
10131                 for (abs_func_id = SC_PATH(sc);
10132                      abs_func_id < (E2_FUNC_MAX * 2); abs_func_id += 2) {
10133                         if (abs_func_id == SC_ABS_FUNC(sc)) {
10134                                 REG_WR(sc,
10135                                        PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER,
10136                                        1);
10137                                 continue;
10138                         }
10139
10140                         bnx2x_pretend_func(sc, abs_func_id);
10141
10142                         /* clear pf enable */
10143                         bnx2x_pf_disable(sc);
10144
10145                         bnx2x_pretend_func(sc, SC_ABS_FUNC(sc));
10146                 }
10147         }
10148
10149         ecore_init_block(sc, BLOCK_PXP, PHASE_COMMON);
10150
10151         ecore_init_block(sc, BLOCK_PXP2, PHASE_COMMON);
10152         bnx2x_init_pxp(sc);
10153
10154 #ifdef __BIG_ENDIAN
10155         REG_WR(sc, PXP2_REG_RQ_QM_ENDIAN_M, 1);
10156         REG_WR(sc, PXP2_REG_RQ_TM_ENDIAN_M, 1);
10157         REG_WR(sc, PXP2_REG_RQ_SRC_ENDIAN_M, 1);
10158         REG_WR(sc, PXP2_REG_RQ_CDU_ENDIAN_M, 1);
10159         REG_WR(sc, PXP2_REG_RQ_DBG_ENDIAN_M, 1);
10160         /* make sure this value is 0 */
10161         REG_WR(sc, PXP2_REG_RQ_HC_ENDIAN_M, 0);
10162
10163         //REG_WR(sc, PXP2_REG_RD_PBF_SWAP_MODE, 1);
10164         REG_WR(sc, PXP2_REG_RD_QM_SWAP_MODE, 1);
10165         REG_WR(sc, PXP2_REG_RD_TM_SWAP_MODE, 1);
10166         REG_WR(sc, PXP2_REG_RD_SRC_SWAP_MODE, 1);
10167         REG_WR(sc, PXP2_REG_RD_CDURD_SWAP_MODE, 1);
10168 #endif
10169
10170         ecore_ilt_init_page_size(sc, INITOP_SET);
10171
10172         if (CHIP_REV_IS_FPGA(sc) && CHIP_IS_E1H(sc)) {
10173                 REG_WR(sc, PXP2_REG_PGL_TAGS_LIMIT, 0x1);
10174         }
10175
10176         /* let the HW do it's magic... */
10177         DELAY(100000);
10178
10179         /* finish PXP init */
10180
10181         val = REG_RD(sc, PXP2_REG_RQ_CFG_DONE);
10182         if (val != 1) {
10183                 PMD_DRV_LOG(NOTICE, sc, "PXP2 CFG failed");
10184                 return -1;
10185         }
10186         val = REG_RD(sc, PXP2_REG_RD_INIT_DONE);
10187         if (val != 1) {
10188                 PMD_DRV_LOG(NOTICE, sc, "PXP2 RD_INIT failed");
10189                 return -1;
10190         }
10191
10192         /*
10193          * Timer bug workaround for E2 only. We need to set the entire ILT to have
10194          * entries with value "0" and valid bit on. This needs to be done by the
10195          * first PF that is loaded in a path (i.e. common phase)
10196          */
10197         if (!CHIP_IS_E1x(sc)) {
10198 /*
10199  * In E2 there is a bug in the timers block that can cause function 6 / 7
10200  * (i.e. vnic3) to start even if it is marked as "scan-off".
10201  * This occurs when a different function (func2,3) is being marked
10202  * as "scan-off". Real-life scenario for example: if a driver is being
10203  * load-unloaded while func6,7 are down. This will cause the timer to access
10204  * the ilt, translate to a logical address and send a request to read/write.
10205  * Since the ilt for the function that is down is not valid, this will cause
10206  * a translation error which is unrecoverable.
10207  * The Workaround is intended to make sure that when this happens nothing
10208  * fatal will occur. The workaround:
10209  *  1.  First PF driver which loads on a path will:
10210  *      a.  After taking the chip out of reset, by using pretend,
10211  *          it will write "0" to the following registers of
10212  *          the other vnics.
10213  *          REG_WR(pdev, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 0);
10214  *          REG_WR(pdev, CFC_REG_WEAK_ENABLE_PF,0);
10215  *          REG_WR(pdev, CFC_REG_STRONG_ENABLE_PF,0);
10216  *          And for itself it will write '1' to
10217  *          PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER to enable
10218  *          dmae-operations (writing to pram for example.)
10219  *          note: can be done for only function 6,7 but cleaner this
10220  *            way.
10221  *      b.  Write zero+valid to the entire ILT.
10222  *      c.  Init the first_timers_ilt_entry, last_timers_ilt_entry of
10223  *          VNIC3 (of that port). The range allocated will be the
10224  *          entire ILT. This is needed to prevent  ILT range error.
10225  *  2.  Any PF driver load flow:
10226  *      a.  ILT update with the physical addresses of the allocated
10227  *          logical pages.
10228  *      b.  Wait 20msec. - note that this timeout is needed to make
10229  *          sure there are no requests in one of the PXP internal
10230  *          queues with "old" ILT addresses.
10231  *      c.  PF enable in the PGLC.
10232  *      d.  Clear the was_error of the PF in the PGLC. (could have
10233  *          occurred while driver was down)
10234  *      e.  PF enable in the CFC (WEAK + STRONG)
10235  *      f.  Timers scan enable
10236  *  3.  PF driver unload flow:
10237  *      a.  Clear the Timers scan_en.
10238  *      b.  Polling for scan_on=0 for that PF.
10239  *      c.  Clear the PF enable bit in the PXP.
10240  *      d.  Clear the PF enable in the CFC (WEAK + STRONG)
10241  *      e.  Write zero+valid to all ILT entries (The valid bit must
10242  *          stay set)
10243  *      f.  If this is VNIC 3 of a port then also init
10244  *          first_timers_ilt_entry to zero and last_timers_ilt_entry
10245  *          to the last enrty in the ILT.
10246  *
10247  *      Notes:
10248  *      Currently the PF error in the PGLC is non recoverable.
10249  *      In the future the there will be a recovery routine for this error.
10250  *      Currently attention is masked.
10251  *      Having an MCP lock on the load/unload process does not guarantee that
10252  *      there is no Timer disable during Func6/7 enable. This is because the
10253  *      Timers scan is currently being cleared by the MCP on FLR.
10254  *      Step 2.d can be done only for PF6/7 and the driver can also check if
10255  *      there is error before clearing it. But the flow above is simpler and
10256  *      more general.
10257  *      All ILT entries are written by zero+valid and not just PF6/7
10258  *      ILT entries since in the future the ILT entries allocation for
10259  *      PF-s might be dynamic.
10260  */
10261                 struct ilt_client_info ilt_cli;
10262                 struct ecore_ilt ilt;
10263
10264                 memset(&ilt_cli, 0, sizeof(struct ilt_client_info));
10265                 memset(&ilt, 0, sizeof(struct ecore_ilt));
10266
10267 /* initialize dummy TM client */
10268                 ilt_cli.start = 0;
10269                 ilt_cli.end = ILT_NUM_PAGE_ENTRIES - 1;
10270                 ilt_cli.client_num = ILT_CLIENT_TM;
10271
10272 /*
10273  * Step 1: set zeroes to all ilt page entries with valid bit on
10274  * Step 2: set the timers first/last ilt entry to point
10275  * to the entire range to prevent ILT range error for 3rd/4th
10276  * vnic (this code assumes existence of the vnic)
10277  *
10278  * both steps performed by call to ecore_ilt_client_init_op()
10279  * with dummy TM client
10280  *
10281  * we must use pretend since PXP2_REG_RQ_##blk##_FIRST_ILT
10282  * and his brother are split registers
10283  */
10284
10285                 bnx2x_pretend_func(sc, (SC_PATH(sc) + 6));
10286                 ecore_ilt_client_init_op_ilt(sc, &ilt, &ilt_cli, INITOP_CLEAR);
10287                 bnx2x_pretend_func(sc, SC_ABS_FUNC(sc));
10288
10289                 REG_WR(sc, PXP2_REG_RQ_DRAM_ALIGN, BNX2X_PXP_DRAM_ALIGN);
10290                 REG_WR(sc, PXP2_REG_RQ_DRAM_ALIGN_RD, BNX2X_PXP_DRAM_ALIGN);
10291                 REG_WR(sc, PXP2_REG_RQ_DRAM_ALIGN_SEL, 1);
10292         }
10293
10294         REG_WR(sc, PXP2_REG_RQ_DISABLE_INPUTS, 0);
10295         REG_WR(sc, PXP2_REG_RD_DISABLE_INPUTS, 0);
10296
10297         if (!CHIP_IS_E1x(sc)) {
10298                 int factor = 0;
10299
10300                 ecore_init_block(sc, BLOCK_PGLUE_B, PHASE_COMMON);
10301                 ecore_init_block(sc, BLOCK_ATC, PHASE_COMMON);
10302
10303 /* let the HW do it's magic... */
10304                 do {
10305                         DELAY(200000);
10306                         val = REG_RD(sc, ATC_REG_ATC_INIT_DONE);
10307                 } while (factor-- && (val != 1));
10308
10309                 if (val != 1) {
10310                         PMD_DRV_LOG(NOTICE, sc, "ATC_INIT failed");
10311                         return -1;
10312                 }
10313         }
10314
10315         ecore_init_block(sc, BLOCK_DMAE, PHASE_COMMON);
10316
10317         /* clean the DMAE memory */
10318         sc->dmae_ready = 1;
10319         ecore_init_fill(sc, TSEM_REG_PRAM, 0, 8);
10320
10321         ecore_init_block(sc, BLOCK_TCM, PHASE_COMMON);
10322
10323         ecore_init_block(sc, BLOCK_UCM, PHASE_COMMON);
10324
10325         ecore_init_block(sc, BLOCK_CCM, PHASE_COMMON);
10326
10327         ecore_init_block(sc, BLOCK_XCM, PHASE_COMMON);
10328
10329         bnx2x_read_dmae(sc, XSEM_REG_PASSIVE_BUFFER, 3);
10330         bnx2x_read_dmae(sc, CSEM_REG_PASSIVE_BUFFER, 3);
10331         bnx2x_read_dmae(sc, TSEM_REG_PASSIVE_BUFFER, 3);
10332         bnx2x_read_dmae(sc, USEM_REG_PASSIVE_BUFFER, 3);
10333
10334         ecore_init_block(sc, BLOCK_QM, PHASE_COMMON);
10335
10336         /* QM queues pointers table */
10337         ecore_qm_init_ptr_table(sc, sc->qm_cid_count, INITOP_SET);
10338
10339         /* soft reset pulse */
10340         REG_WR(sc, QM_REG_SOFT_RESET, 1);
10341         REG_WR(sc, QM_REG_SOFT_RESET, 0);
10342
10343         if (CNIC_SUPPORT(sc))
10344                 ecore_init_block(sc, BLOCK_TM, PHASE_COMMON);
10345
10346         ecore_init_block(sc, BLOCK_DORQ, PHASE_COMMON);
10347         REG_WR(sc, DORQ_REG_DPM_CID_OFST, BNX2X_DB_SHIFT);
10348
10349         if (!CHIP_REV_IS_SLOW(sc)) {
10350 /* enable hw interrupt from doorbell Q */
10351                 REG_WR(sc, DORQ_REG_DORQ_INT_MASK, 0);
10352         }
10353
10354         ecore_init_block(sc, BLOCK_BRB1, PHASE_COMMON);
10355
10356         ecore_init_block(sc, BLOCK_PRS, PHASE_COMMON);
10357         REG_WR(sc, PRS_REG_A_PRSU_20, 0xf);
10358         REG_WR(sc, PRS_REG_E1HOV_MODE, sc->devinfo.mf_info.path_has_ovlan);
10359
10360         if (!CHIP_IS_E1x(sc) && !CHIP_IS_E3B0(sc)) {
10361                 if (IS_MF_AFEX(sc)) {
10362                         /*
10363                          * configure that AFEX and VLAN headers must be
10364                          * received in AFEX mode
10365                          */
10366                         REG_WR(sc, PRS_REG_HDRS_AFTER_BASIC, 0xE);
10367                         REG_WR(sc, PRS_REG_MUST_HAVE_HDRS, 0xA);
10368                         REG_WR(sc, PRS_REG_HDRS_AFTER_TAG_0, 0x6);
10369                         REG_WR(sc, PRS_REG_TAG_ETHERTYPE_0, 0x8926);
10370                         REG_WR(sc, PRS_REG_TAG_LEN_0, 0x4);
10371                 } else {
10372                         /*
10373                          * Bit-map indicating which L2 hdrs may appear
10374                          * after the basic Ethernet header
10375                          */
10376                         REG_WR(sc, PRS_REG_HDRS_AFTER_BASIC,
10377                                sc->devinfo.mf_info.path_has_ovlan ? 7 : 6);
10378                 }
10379         }
10380
10381         ecore_init_block(sc, BLOCK_TSDM, PHASE_COMMON);
10382         ecore_init_block(sc, BLOCK_CSDM, PHASE_COMMON);
10383         ecore_init_block(sc, BLOCK_USDM, PHASE_COMMON);
10384         ecore_init_block(sc, BLOCK_XSDM, PHASE_COMMON);
10385
10386         if (!CHIP_IS_E1x(sc)) {
10387 /* reset VFC memories */
10388                 REG_WR(sc, TSEM_REG_FAST_MEMORY + VFC_REG_MEMORIES_RST,
10389                        VFC_MEMORIES_RST_REG_CAM_RST |
10390                        VFC_MEMORIES_RST_REG_RAM_RST);
10391                 REG_WR(sc, XSEM_REG_FAST_MEMORY + VFC_REG_MEMORIES_RST,
10392                        VFC_MEMORIES_RST_REG_CAM_RST |
10393                        VFC_MEMORIES_RST_REG_RAM_RST);
10394
10395                 DELAY(20000);
10396         }
10397
10398         ecore_init_block(sc, BLOCK_TSEM, PHASE_COMMON);
10399         ecore_init_block(sc, BLOCK_USEM, PHASE_COMMON);
10400         ecore_init_block(sc, BLOCK_CSEM, PHASE_COMMON);
10401         ecore_init_block(sc, BLOCK_XSEM, PHASE_COMMON);
10402
10403         /* sync semi rtc */
10404         REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR, 0x80000000);
10405         REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, 0x80000000);
10406
10407         ecore_init_block(sc, BLOCK_UPB, PHASE_COMMON);
10408         ecore_init_block(sc, BLOCK_XPB, PHASE_COMMON);
10409         ecore_init_block(sc, BLOCK_PBF, PHASE_COMMON);
10410
10411         if (!CHIP_IS_E1x(sc)) {
10412                 if (IS_MF_AFEX(sc)) {
10413                         /*
10414                          * configure that AFEX and VLAN headers must be
10415                          * sent in AFEX mode
10416                          */
10417                         REG_WR(sc, PBF_REG_HDRS_AFTER_BASIC, 0xE);
10418                         REG_WR(sc, PBF_REG_MUST_HAVE_HDRS, 0xA);
10419                         REG_WR(sc, PBF_REG_HDRS_AFTER_TAG_0, 0x6);
10420                         REG_WR(sc, PBF_REG_TAG_ETHERTYPE_0, 0x8926);
10421                         REG_WR(sc, PBF_REG_TAG_LEN_0, 0x4);
10422                 } else {
10423                         REG_WR(sc, PBF_REG_HDRS_AFTER_BASIC,
10424                                sc->devinfo.mf_info.path_has_ovlan ? 7 : 6);
10425                 }
10426         }
10427
10428         REG_WR(sc, SRC_REG_SOFT_RST, 1);
10429
10430         ecore_init_block(sc, BLOCK_SRC, PHASE_COMMON);
10431
10432         if (CNIC_SUPPORT(sc)) {
10433                 REG_WR(sc, SRC_REG_KEYSEARCH_0, 0x63285672);
10434                 REG_WR(sc, SRC_REG_KEYSEARCH_1, 0x24b8f2cc);
10435                 REG_WR(sc, SRC_REG_KEYSEARCH_2, 0x223aef9b);
10436                 REG_WR(sc, SRC_REG_KEYSEARCH_3, 0x26001e3a);
10437                 REG_WR(sc, SRC_REG_KEYSEARCH_4, 0x7ae91116);
10438                 REG_WR(sc, SRC_REG_KEYSEARCH_5, 0x5ce5230b);
10439                 REG_WR(sc, SRC_REG_KEYSEARCH_6, 0x298d8adf);
10440                 REG_WR(sc, SRC_REG_KEYSEARCH_7, 0x6eb0ff09);
10441                 REG_WR(sc, SRC_REG_KEYSEARCH_8, 0x1830f82f);
10442                 REG_WR(sc, SRC_REG_KEYSEARCH_9, 0x01e46be7);
10443         }
10444         REG_WR(sc, SRC_REG_SOFT_RST, 0);
10445
10446         if (sizeof(union cdu_context) != 1024) {
10447 /* we currently assume that a context is 1024 bytes */
10448                 PMD_DRV_LOG(NOTICE, sc,
10449                             "please adjust the size of cdu_context(%ld)",
10450                             (long)sizeof(union cdu_context));
10451         }
10452
10453         ecore_init_block(sc, BLOCK_CDU, PHASE_COMMON);
10454         val = (4 << 24) + (0 << 12) + 1024;
10455         REG_WR(sc, CDU_REG_CDU_GLOBAL_PARAMS, val);
10456
10457         ecore_init_block(sc, BLOCK_CFC, PHASE_COMMON);
10458
10459         REG_WR(sc, CFC_REG_INIT_REG, 0x7FF);
10460         /* enable context validation interrupt from CFC */
10461         REG_WR(sc, CFC_REG_CFC_INT_MASK, 0);
10462
10463         /* set the thresholds to prevent CFC/CDU race */
10464         REG_WR(sc, CFC_REG_DEBUG0, 0x20020000);
10465         ecore_init_block(sc, BLOCK_HC, PHASE_COMMON);
10466
10467         if (!CHIP_IS_E1x(sc) && BNX2X_NOMCP(sc)) {
10468                 REG_WR(sc, IGU_REG_RESET_MEMORIES, 0x36);
10469         }
10470
10471         ecore_init_block(sc, BLOCK_IGU, PHASE_COMMON);
10472         ecore_init_block(sc, BLOCK_MISC_AEU, PHASE_COMMON);
10473
10474         /* Reset PCIE errors for debug */
10475         REG_WR(sc, 0x2814, 0xffffffff);
10476         REG_WR(sc, 0x3820, 0xffffffff);
10477
10478         if (!CHIP_IS_E1x(sc)) {
10479                 REG_WR(sc, PCICFG_OFFSET + PXPCS_TL_CONTROL_5,
10480                        (PXPCS_TL_CONTROL_5_ERR_UNSPPORT1 |
10481                         PXPCS_TL_CONTROL_5_ERR_UNSPPORT));
10482                 REG_WR(sc, PCICFG_OFFSET + PXPCS_TL_FUNC345_STAT,
10483                        (PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT4 |
10484                         PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT3 |
10485                         PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT2));
10486                 REG_WR(sc, PCICFG_OFFSET + PXPCS_TL_FUNC678_STAT,
10487                        (PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT7 |
10488                         PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT6 |
10489                         PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT5));
10490         }
10491
10492         ecore_init_block(sc, BLOCK_NIG, PHASE_COMMON);
10493
10494         /* in E3 this done in per-port section */
10495         if (!CHIP_IS_E3(sc))
10496                 REG_WR(sc, NIG_REG_LLH_MF_MODE, IS_MF(sc));
10497
10498         if (CHIP_IS_E1H(sc)) {
10499 /* not applicable for E2 (and above ...) */
10500                 REG_WR(sc, NIG_REG_LLH_E1HOV_MODE, IS_MF_SD(sc));
10501         }
10502
10503         if (CHIP_REV_IS_SLOW(sc)) {
10504                 DELAY(200000);
10505         }
10506
10507         /* finish CFC init */
10508         val = reg_poll(sc, CFC_REG_LL_INIT_DONE, 1, 100, 10);
10509         if (val != 1) {
10510                 PMD_DRV_LOG(NOTICE, sc, "CFC LL_INIT failed");
10511                 return -1;
10512         }
10513         val = reg_poll(sc, CFC_REG_AC_INIT_DONE, 1, 100, 10);
10514         if (val != 1) {
10515                 PMD_DRV_LOG(NOTICE, sc, "CFC AC_INIT failed");
10516                 return -1;
10517         }
10518         val = reg_poll(sc, CFC_REG_CAM_INIT_DONE, 1, 100, 10);
10519         if (val != 1) {
10520                 PMD_DRV_LOG(NOTICE, sc, "CFC CAM_INIT failed");
10521                 return -1;
10522         }
10523         REG_WR(sc, CFC_REG_DEBUG0, 0);
10524
10525         bnx2x_setup_fan_failure_detection(sc);
10526
10527         /* clear PXP2 attentions */
10528         REG_RD(sc, PXP2_REG_PXP2_INT_STS_CLR_0);
10529
10530         bnx2x_enable_blocks_attention(sc);
10531
10532         if (!CHIP_REV_IS_SLOW(sc)) {
10533                 ecore_enable_blocks_parity(sc);
10534         }
10535
10536         if (!BNX2X_NOMCP(sc)) {
10537                 if (CHIP_IS_E1x(sc)) {
10538                         bnx2x_common_init_phy(sc);
10539                 }
10540         }
10541
10542         return 0;
10543 }
10544
10545 /**
10546  * bnx2x_init_hw_common_chip - init HW at the COMMON_CHIP phase.
10547  *
10548  * @sc:     driver handle
10549  */
10550 static int bnx2x_init_hw_common_chip(struct bnx2x_softc *sc)
10551 {
10552         int rc = bnx2x_init_hw_common(sc);
10553
10554         if (rc) {
10555                 return rc;
10556         }
10557
10558         /* In E2 2-PORT mode, same ext phy is used for the two paths */
10559         if (!BNX2X_NOMCP(sc)) {
10560                 bnx2x_common_init_phy(sc);
10561         }
10562
10563         return 0;
10564 }
10565
10566 static int bnx2x_init_hw_port(struct bnx2x_softc *sc)
10567 {
10568         int port = SC_PORT(sc);
10569         int init_phase = port ? PHASE_PORT1 : PHASE_PORT0;
10570         uint32_t low, high;
10571         uint32_t val;
10572
10573         PMD_DRV_LOG(DEBUG, sc, "starting port init for port %d", port);
10574
10575         REG_WR(sc, NIG_REG_MASK_INTERRUPT_PORT0 + port * 4, 0);
10576
10577         ecore_init_block(sc, BLOCK_MISC, init_phase);
10578         ecore_init_block(sc, BLOCK_PXP, init_phase);
10579         ecore_init_block(sc, BLOCK_PXP2, init_phase);
10580
10581         /*
10582          * Timers bug workaround: disables the pf_master bit in pglue at
10583          * common phase, we need to enable it here before any dmae access are
10584          * attempted. Therefore we manually added the enable-master to the
10585          * port phase (it also happens in the function phase)
10586          */
10587         if (!CHIP_IS_E1x(sc)) {
10588                 REG_WR(sc, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 1);
10589         }
10590
10591         ecore_init_block(sc, BLOCK_ATC, init_phase);
10592         ecore_init_block(sc, BLOCK_DMAE, init_phase);
10593         ecore_init_block(sc, BLOCK_PGLUE_B, init_phase);
10594         ecore_init_block(sc, BLOCK_QM, init_phase);
10595
10596         ecore_init_block(sc, BLOCK_TCM, init_phase);
10597         ecore_init_block(sc, BLOCK_UCM, init_phase);
10598         ecore_init_block(sc, BLOCK_CCM, init_phase);
10599         ecore_init_block(sc, BLOCK_XCM, init_phase);
10600
10601         /* QM cid (connection) count */
10602         ecore_qm_init_cid_count(sc, sc->qm_cid_count, INITOP_SET);
10603
10604         if (CNIC_SUPPORT(sc)) {
10605                 ecore_init_block(sc, BLOCK_TM, init_phase);
10606                 REG_WR(sc, TM_REG_LIN0_SCAN_TIME + port * 4, 20);
10607                 REG_WR(sc, TM_REG_LIN0_MAX_ACTIVE_CID + port * 4, 31);
10608         }
10609
10610         ecore_init_block(sc, BLOCK_DORQ, init_phase);
10611
10612         ecore_init_block(sc, BLOCK_BRB1, init_phase);
10613
10614         if (CHIP_IS_E1H(sc)) {
10615                 if (IS_MF(sc)) {
10616                         low = (BNX2X_ONE_PORT(sc) ? 160 : 246);
10617                 } else if (sc->mtu > 4096) {
10618                         if (BNX2X_ONE_PORT(sc)) {
10619                                 low = 160;
10620                         } else {
10621                                 val = sc->mtu;
10622                                 /* (24*1024 + val*4)/256 */
10623                                 low = (96 + (val / 64) + ((val % 64) ? 1 : 0));
10624                         }
10625                 } else {
10626                         low = (BNX2X_ONE_PORT(sc) ? 80 : 160);
10627                 }
10628                 high = (low + 56);      /* 14*1024/256 */
10629                 REG_WR(sc, BRB1_REG_PAUSE_LOW_THRESHOLD_0 + port * 4, low);
10630                 REG_WR(sc, BRB1_REG_PAUSE_HIGH_THRESHOLD_0 + port * 4, high);
10631         }
10632
10633         if (CHIP_IS_MODE_4_PORT(sc)) {
10634                 REG_WR(sc, SC_PORT(sc) ?
10635                        BRB1_REG_MAC_GUARANTIED_1 :
10636                        BRB1_REG_MAC_GUARANTIED_0, 40);
10637         }
10638
10639         ecore_init_block(sc, BLOCK_PRS, init_phase);
10640         if (CHIP_IS_E3B0(sc)) {
10641                 if (IS_MF_AFEX(sc)) {
10642                         /* configure headers for AFEX mode */
10643                         if (SC_PORT(sc)) {
10644                                 REG_WR(sc, PRS_REG_HDRS_AFTER_BASIC_PORT_1,
10645                                        0xE);
10646                                 REG_WR(sc, PRS_REG_HDRS_AFTER_TAG_0_PORT_1,
10647                                        0x6);
10648                                 REG_WR(sc, PRS_REG_MUST_HAVE_HDRS_PORT_1, 0xA);
10649                         } else {
10650                                 REG_WR(sc, PRS_REG_HDRS_AFTER_BASIC_PORT_0,
10651                                        0xE);
10652                                 REG_WR(sc, PRS_REG_HDRS_AFTER_TAG_0_PORT_0,
10653                                        0x6);
10654                                 REG_WR(sc, PRS_REG_MUST_HAVE_HDRS_PORT_0, 0xA);
10655                         }
10656                 } else {
10657                         /* Ovlan exists only if we are in multi-function +
10658                          * switch-dependent mode, in switch-independent there
10659                          * is no ovlan headers
10660                          */
10661                         REG_WR(sc, SC_PORT(sc) ?
10662                                PRS_REG_HDRS_AFTER_BASIC_PORT_1 :
10663                                PRS_REG_HDRS_AFTER_BASIC_PORT_0,
10664                                (sc->devinfo.mf_info.path_has_ovlan ? 7 : 6));
10665                 }
10666         }
10667
10668         ecore_init_block(sc, BLOCK_TSDM, init_phase);
10669         ecore_init_block(sc, BLOCK_CSDM, init_phase);
10670         ecore_init_block(sc, BLOCK_USDM, init_phase);
10671         ecore_init_block(sc, BLOCK_XSDM, init_phase);
10672
10673         ecore_init_block(sc, BLOCK_TSEM, init_phase);
10674         ecore_init_block(sc, BLOCK_USEM, init_phase);
10675         ecore_init_block(sc, BLOCK_CSEM, init_phase);
10676         ecore_init_block(sc, BLOCK_XSEM, init_phase);
10677
10678         ecore_init_block(sc, BLOCK_UPB, init_phase);
10679         ecore_init_block(sc, BLOCK_XPB, init_phase);
10680
10681         ecore_init_block(sc, BLOCK_PBF, init_phase);
10682
10683         if (CHIP_IS_E1x(sc)) {
10684 /* configure PBF to work without PAUSE mtu 9000 */
10685                 REG_WR(sc, PBF_REG_P0_PAUSE_ENABLE + port * 4, 0);
10686
10687 /* update threshold */
10688                 REG_WR(sc, PBF_REG_P0_ARB_THRSH + port * 4, (9040 / 16));
10689 /* update init credit */
10690                 REG_WR(sc, PBF_REG_P0_INIT_CRD + port * 4,
10691                        (9040 / 16) + 553 - 22);
10692
10693 /* probe changes */
10694                 REG_WR(sc, PBF_REG_INIT_P0 + port * 4, 1);
10695                 DELAY(50);
10696                 REG_WR(sc, PBF_REG_INIT_P0 + port * 4, 0);
10697         }
10698
10699         if (CNIC_SUPPORT(sc)) {
10700                 ecore_init_block(sc, BLOCK_SRC, init_phase);
10701         }
10702
10703         ecore_init_block(sc, BLOCK_CDU, init_phase);
10704         ecore_init_block(sc, BLOCK_CFC, init_phase);
10705         ecore_init_block(sc, BLOCK_HC, init_phase);
10706         ecore_init_block(sc, BLOCK_IGU, init_phase);
10707         ecore_init_block(sc, BLOCK_MISC_AEU, init_phase);
10708         /* init aeu_mask_attn_func_0/1:
10709          *  - SF mode: bits 3-7 are masked. only bits 0-2 are in use
10710          *  - MF mode: bit 3 is masked. bits 0-2 are in use as in SF
10711          *             bits 4-7 are used for "per vn group attention" */
10712         val = IS_MF(sc) ? 0xF7 : 0x7;
10713         val |= 0x10;
10714         REG_WR(sc, MISC_REG_AEU_MASK_ATTN_FUNC_0 + port * 4, val);
10715
10716         ecore_init_block(sc, BLOCK_NIG, init_phase);
10717
10718         if (!CHIP_IS_E1x(sc)) {
10719 /* Bit-map indicating which L2 hdrs may appear after the
10720  * basic Ethernet header
10721  */
10722                 if (IS_MF_AFEX(sc)) {
10723                         REG_WR(sc, SC_PORT(sc) ?
10724                                NIG_REG_P1_HDRS_AFTER_BASIC :
10725                                NIG_REG_P0_HDRS_AFTER_BASIC, 0xE);
10726                 } else {
10727                         REG_WR(sc, SC_PORT(sc) ?
10728                                NIG_REG_P1_HDRS_AFTER_BASIC :
10729                                NIG_REG_P0_HDRS_AFTER_BASIC,
10730                                IS_MF_SD(sc) ? 7 : 6);
10731                 }
10732
10733                 if (CHIP_IS_E3(sc)) {
10734                         REG_WR(sc, SC_PORT(sc) ?
10735                                NIG_REG_LLH1_MF_MODE :
10736                                NIG_REG_LLH_MF_MODE, IS_MF(sc));
10737                 }
10738         }
10739         if (!CHIP_IS_E3(sc)) {
10740                 REG_WR(sc, NIG_REG_XGXS_SERDES0_MODE_SEL + port * 4, 1);
10741         }
10742
10743         /* 0x2 disable mf_ov, 0x1 enable */
10744         REG_WR(sc, NIG_REG_LLH0_BRB1_DRV_MASK_MF + port * 4,
10745                (IS_MF_SD(sc) ? 0x1 : 0x2));
10746
10747         if (!CHIP_IS_E1x(sc)) {
10748                 val = 0;
10749                 switch (sc->devinfo.mf_info.mf_mode) {
10750                 case MULTI_FUNCTION_SD:
10751                         val = 1;
10752                         break;
10753                 case MULTI_FUNCTION_SI:
10754                 case MULTI_FUNCTION_AFEX:
10755                         val = 2;
10756                         break;
10757                 }
10758
10759                 REG_WR(sc, (SC_PORT(sc) ? NIG_REG_LLH1_CLS_TYPE :
10760                             NIG_REG_LLH0_CLS_TYPE), val);
10761         }
10762         REG_WR(sc, NIG_REG_LLFC_ENABLE_0 + port * 4, 0);
10763         REG_WR(sc, NIG_REG_LLFC_OUT_EN_0 + port * 4, 0);
10764         REG_WR(sc, NIG_REG_PAUSE_ENABLE_0 + port * 4, 1);
10765
10766         /* If SPIO5 is set to generate interrupts, enable it for this port */
10767         val = REG_RD(sc, MISC_REG_SPIO_EVENT_EN);
10768         if (val & MISC_SPIO_SPIO5) {
10769                 uint32_t reg_addr = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 :
10770                                      MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0);
10771                 val = REG_RD(sc, reg_addr);
10772                 val |= AEU_INPUTS_ATTN_BITS_SPIO5;
10773                 REG_WR(sc, reg_addr, val);
10774         }
10775
10776         return 0;
10777 }
10778
10779 static uint32_t
10780 bnx2x_flr_clnup_reg_poll(struct bnx2x_softc *sc, uint32_t reg,
10781                        uint32_t expected, uint32_t poll_count)
10782 {
10783         uint32_t cur_cnt = poll_count;
10784         uint32_t val;
10785
10786         while ((val = REG_RD(sc, reg)) != expected && cur_cnt--) {
10787                 DELAY(FLR_WAIT_INTERVAL);
10788         }
10789
10790         return val;
10791 }
10792
10793 static int
10794 bnx2x_flr_clnup_poll_hw_counter(struct bnx2x_softc *sc, uint32_t reg,
10795                               __rte_unused const char *msg, uint32_t poll_cnt)
10796 {
10797         uint32_t val = bnx2x_flr_clnup_reg_poll(sc, reg, 0, poll_cnt);
10798
10799         if (val != 0) {
10800                 PMD_DRV_LOG(NOTICE, sc, "%s usage count=%d", msg, val);
10801                 return -1;
10802         }
10803
10804         return 0;
10805 }
10806
10807 /* Common routines with VF FLR cleanup */
10808 static uint32_t bnx2x_flr_clnup_poll_count(struct bnx2x_softc *sc)
10809 {
10810         /* adjust polling timeout */
10811         if (CHIP_REV_IS_EMUL(sc)) {
10812                 return FLR_POLL_CNT * 2000;
10813         }
10814
10815         if (CHIP_REV_IS_FPGA(sc)) {
10816                 return FLR_POLL_CNT * 120;
10817         }
10818
10819         return FLR_POLL_CNT;
10820 }
10821
10822 static int bnx2x_poll_hw_usage_counters(struct bnx2x_softc *sc, uint32_t poll_cnt)
10823 {
10824         /* wait for CFC PF usage-counter to zero (includes all the VFs) */
10825         if (bnx2x_flr_clnup_poll_hw_counter(sc,
10826                                           CFC_REG_NUM_LCIDS_INSIDE_PF,
10827                                           "CFC PF usage counter timed out",
10828                                           poll_cnt)) {
10829                 return -1;
10830         }
10831
10832         /* Wait for DQ PF usage-counter to zero (until DQ cleanup) */
10833         if (bnx2x_flr_clnup_poll_hw_counter(sc,
10834                                           DORQ_REG_PF_USAGE_CNT,
10835                                           "DQ PF usage counter timed out",
10836                                           poll_cnt)) {
10837                 return -1;
10838         }
10839
10840         /* Wait for QM PF usage-counter to zero (until DQ cleanup) */
10841         if (bnx2x_flr_clnup_poll_hw_counter(sc,
10842                                           QM_REG_PF_USG_CNT_0 + 4 * SC_FUNC(sc),
10843                                           "QM PF usage counter timed out",
10844                                           poll_cnt)) {
10845                 return -1;
10846         }
10847
10848         /* Wait for Timer PF usage-counters to zero (until DQ cleanup) */
10849         if (bnx2x_flr_clnup_poll_hw_counter(sc,
10850                                           TM_REG_LIN0_VNIC_UC + 4 * SC_PORT(sc),
10851                                           "Timers VNIC usage counter timed out",
10852                                           poll_cnt)) {
10853                 return -1;
10854         }
10855
10856         if (bnx2x_flr_clnup_poll_hw_counter(sc,
10857                                           TM_REG_LIN0_NUM_SCANS +
10858                                           4 * SC_PORT(sc),
10859                                           "Timers NUM_SCANS usage counter timed out",
10860                                           poll_cnt)) {
10861                 return -1;
10862         }
10863
10864         /* Wait DMAE PF usage counter to zero */
10865         if (bnx2x_flr_clnup_poll_hw_counter(sc,
10866                                           dmae_reg_go_c[INIT_DMAE_C(sc)],
10867                                           "DMAE dommand register timed out",
10868                                           poll_cnt)) {
10869                 return -1;
10870         }
10871
10872         return 0;
10873 }
10874
10875 #define OP_GEN_PARAM(param)                                            \
10876         (((param) << SDM_OP_GEN_COMP_PARAM_SHIFT) & SDM_OP_GEN_COMP_PARAM)
10877 #define OP_GEN_TYPE(type)                                           \
10878         (((type) << SDM_OP_GEN_COMP_TYPE_SHIFT) & SDM_OP_GEN_COMP_TYPE)
10879 #define OP_GEN_AGG_VECT(index)                                             \
10880         (((index) << SDM_OP_GEN_AGG_VECT_IDX_SHIFT) & SDM_OP_GEN_AGG_VECT_IDX)
10881
10882 static int
10883 bnx2x_send_final_clnup(struct bnx2x_softc *sc, uint8_t clnup_func,
10884                      uint32_t poll_cnt)
10885 {
10886         uint32_t op_gen_command = 0;
10887         uint32_t comp_addr = (BAR_CSTRORM_INTMEM +
10888                               CSTORM_FINAL_CLEANUP_COMPLETE_OFFSET(clnup_func));
10889         int ret = 0;
10890
10891         if (REG_RD(sc, comp_addr)) {
10892                 PMD_DRV_LOG(NOTICE, sc,
10893                             "Cleanup complete was not 0 before sending");
10894                 return -1;
10895         }
10896
10897         op_gen_command |= OP_GEN_PARAM(XSTORM_AGG_INT_FINAL_CLEANUP_INDEX);
10898         op_gen_command |= OP_GEN_TYPE(XSTORM_AGG_INT_FINAL_CLEANUP_COMP_TYPE);
10899         op_gen_command |= OP_GEN_AGG_VECT(clnup_func);
10900         op_gen_command |= 1 << SDM_OP_GEN_AGG_VECT_IDX_VALID_SHIFT;
10901
10902         REG_WR(sc, XSDM_REG_OPERATION_GEN, op_gen_command);
10903
10904         if (bnx2x_flr_clnup_reg_poll(sc, comp_addr, 1, poll_cnt) != 1) {
10905                 PMD_DRV_LOG(NOTICE, sc, "FW final cleanup did not succeed");
10906                 PMD_DRV_LOG(DEBUG, sc, "At timeout completion address contained %x",
10907                             (REG_RD(sc, comp_addr)));
10908                 rte_panic("FLR cleanup failed");
10909                 return -1;
10910         }
10911
10912         /* Zero completion for nxt FLR */
10913         REG_WR(sc, comp_addr, 0);
10914
10915         return ret;
10916 }
10917
10918 static void
10919 bnx2x_pbf_pN_buf_flushed(struct bnx2x_softc *sc, struct pbf_pN_buf_regs *regs,
10920                        uint32_t poll_count)
10921 {
10922         uint32_t init_crd, crd, crd_start, crd_freed, crd_freed_start;
10923         uint32_t cur_cnt = poll_count;
10924
10925         crd_freed = crd_freed_start = REG_RD(sc, regs->crd_freed);
10926         crd = crd_start = REG_RD(sc, regs->crd);
10927         init_crd = REG_RD(sc, regs->init_crd);
10928
10929         while ((crd != init_crd) &&
10930                ((uint32_t) ((int32_t) crd_freed - (int32_t) crd_freed_start) <
10931                 (init_crd - crd_start))) {
10932                 if (cur_cnt--) {
10933                         DELAY(FLR_WAIT_INTERVAL);
10934                         crd = REG_RD(sc, regs->crd);
10935                         crd_freed = REG_RD(sc, regs->crd_freed);
10936                 } else {
10937                         break;
10938                 }
10939         }
10940 }
10941
10942 static void
10943 bnx2x_pbf_pN_cmd_flushed(struct bnx2x_softc *sc, struct pbf_pN_cmd_regs *regs,
10944                        uint32_t poll_count)
10945 {
10946         uint32_t occup, to_free, freed, freed_start;
10947         uint32_t cur_cnt = poll_count;
10948
10949         occup = to_free = REG_RD(sc, regs->lines_occup);
10950         freed = freed_start = REG_RD(sc, regs->lines_freed);
10951
10952         while (occup &&
10953                ((uint32_t) ((int32_t) freed - (int32_t) freed_start) <
10954                 to_free)) {
10955                 if (cur_cnt--) {
10956                         DELAY(FLR_WAIT_INTERVAL);
10957                         occup = REG_RD(sc, regs->lines_occup);
10958                         freed = REG_RD(sc, regs->lines_freed);
10959                 } else {
10960                         break;
10961                 }
10962         }
10963 }
10964
10965 static void bnx2x_tx_hw_flushed(struct bnx2x_softc *sc, uint32_t poll_count)
10966 {
10967         struct pbf_pN_cmd_regs cmd_regs[] = {
10968                 {0, (CHIP_IS_E3B0(sc)) ?
10969                  PBF_REG_TQ_OCCUPANCY_Q0 : PBF_REG_P0_TQ_OCCUPANCY,
10970                  (CHIP_IS_E3B0(sc)) ?
10971                  PBF_REG_TQ_LINES_FREED_CNT_Q0 : PBF_REG_P0_TQ_LINES_FREED_CNT},
10972                 {1, (CHIP_IS_E3B0(sc)) ?
10973                  PBF_REG_TQ_OCCUPANCY_Q1 : PBF_REG_P1_TQ_OCCUPANCY,
10974                  (CHIP_IS_E3B0(sc)) ?
10975                  PBF_REG_TQ_LINES_FREED_CNT_Q1 : PBF_REG_P1_TQ_LINES_FREED_CNT},
10976                 {4, (CHIP_IS_E3B0(sc)) ?
10977                  PBF_REG_TQ_OCCUPANCY_LB_Q : PBF_REG_P4_TQ_OCCUPANCY,
10978                  (CHIP_IS_E3B0(sc)) ?
10979                  PBF_REG_TQ_LINES_FREED_CNT_LB_Q :
10980                  PBF_REG_P4_TQ_LINES_FREED_CNT}
10981         };
10982
10983         struct pbf_pN_buf_regs buf_regs[] = {
10984                 {0, (CHIP_IS_E3B0(sc)) ?
10985                  PBF_REG_INIT_CRD_Q0 : PBF_REG_P0_INIT_CRD,
10986                  (CHIP_IS_E3B0(sc)) ? PBF_REG_CREDIT_Q0 : PBF_REG_P0_CREDIT,
10987                  (CHIP_IS_E3B0(sc)) ?
10988                  PBF_REG_INTERNAL_CRD_FREED_CNT_Q0 :
10989                  PBF_REG_P0_INTERNAL_CRD_FREED_CNT},
10990                 {1, (CHIP_IS_E3B0(sc)) ?
10991                  PBF_REG_INIT_CRD_Q1 : PBF_REG_P1_INIT_CRD,
10992                  (CHIP_IS_E3B0(sc)) ? PBF_REG_CREDIT_Q1 : PBF_REG_P1_CREDIT,
10993                  (CHIP_IS_E3B0(sc)) ?
10994                  PBF_REG_INTERNAL_CRD_FREED_CNT_Q1 :
10995                  PBF_REG_P1_INTERNAL_CRD_FREED_CNT},
10996                 {4, (CHIP_IS_E3B0(sc)) ?
10997                  PBF_REG_INIT_CRD_LB_Q : PBF_REG_P4_INIT_CRD,
10998                  (CHIP_IS_E3B0(sc)) ? PBF_REG_CREDIT_LB_Q : PBF_REG_P4_CREDIT,
10999                  (CHIP_IS_E3B0(sc)) ?
11000                  PBF_REG_INTERNAL_CRD_FREED_CNT_LB_Q :
11001                  PBF_REG_P4_INTERNAL_CRD_FREED_CNT},
11002         };
11003
11004         uint32_t i;
11005
11006         /* Verify the command queues are flushed P0, P1, P4 */
11007         for (i = 0; i < ARRAY_SIZE(cmd_regs); i++) {
11008                 bnx2x_pbf_pN_cmd_flushed(sc, &cmd_regs[i], poll_count);
11009         }
11010
11011         /* Verify the transmission buffers are flushed P0, P1, P4 */
11012         for (i = 0; i < ARRAY_SIZE(buf_regs); i++) {
11013                 bnx2x_pbf_pN_buf_flushed(sc, &buf_regs[i], poll_count);
11014         }
11015 }
11016
11017 static void bnx2x_hw_enable_status(struct bnx2x_softc *sc)
11018 {
11019         __rte_unused uint32_t val;
11020
11021         val = REG_RD(sc, CFC_REG_WEAK_ENABLE_PF);
11022         PMD_DRV_LOG(DEBUG, sc, "CFC_REG_WEAK_ENABLE_PF is 0x%x", val);
11023
11024         val = REG_RD(sc, PBF_REG_DISABLE_PF);
11025         PMD_DRV_LOG(DEBUG, sc, "PBF_REG_DISABLE_PF is 0x%x", val);
11026
11027         val = REG_RD(sc, IGU_REG_PCI_PF_MSI_EN);
11028         PMD_DRV_LOG(DEBUG, sc, "IGU_REG_PCI_PF_MSI_EN is 0x%x", val);
11029
11030         val = REG_RD(sc, IGU_REG_PCI_PF_MSIX_EN);
11031         PMD_DRV_LOG(DEBUG, sc, "IGU_REG_PCI_PF_MSIX_EN is 0x%x", val);
11032
11033         val = REG_RD(sc, IGU_REG_PCI_PF_MSIX_FUNC_MASK);
11034         PMD_DRV_LOG(DEBUG, sc, "IGU_REG_PCI_PF_MSIX_FUNC_MASK is 0x%x", val);
11035
11036         val = REG_RD(sc, PGLUE_B_REG_SHADOW_BME_PF_7_0_CLR);
11037         PMD_DRV_LOG(DEBUG, sc,
11038                     "PGLUE_B_REG_SHADOW_BME_PF_7_0_CLR is 0x%x", val);
11039
11040         val = REG_RD(sc, PGLUE_B_REG_FLR_REQUEST_PF_7_0_CLR);
11041         PMD_DRV_LOG(DEBUG, sc,
11042                     "PGLUE_B_REG_FLR_REQUEST_PF_7_0_CLR is 0x%x", val);
11043
11044         val = REG_RD(sc, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER);
11045         PMD_DRV_LOG(DEBUG, sc, "PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER is 0x%x",
11046                     val);
11047 }
11048
11049 /**
11050  *      bnx2x_pf_flr_clnup
11051  *      a. re-enable target read on the PF
11052  *      b. poll cfc per function usgae counter
11053  *      c. poll the qm perfunction usage counter
11054  *      d. poll the tm per function usage counter
11055  *      e. poll the tm per function scan-done indication
11056  *      f. clear the dmae channel associated wit hthe PF
11057  *      g. zero the igu 'trailing edge' and 'leading edge' regs (attentions)
11058  *      h. call the common flr cleanup code with -1 (pf indication)
11059  */
11060 static int bnx2x_pf_flr_clnup(struct bnx2x_softc *sc)
11061 {
11062         uint32_t poll_cnt = bnx2x_flr_clnup_poll_count(sc);
11063
11064         /* Re-enable PF target read access */
11065         REG_WR(sc, PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_READ, 1);
11066
11067         /* Poll HW usage counters */
11068         if (bnx2x_poll_hw_usage_counters(sc, poll_cnt)) {
11069                 return -1;
11070         }
11071
11072         /* Zero the igu 'trailing edge' and 'leading edge' */
11073
11074         /* Send the FW cleanup command */
11075         if (bnx2x_send_final_clnup(sc, (uint8_t) SC_FUNC(sc), poll_cnt)) {
11076                 return -1;
11077         }
11078
11079         /* ATC cleanup */
11080
11081         /* Verify TX hw is flushed */
11082         bnx2x_tx_hw_flushed(sc, poll_cnt);
11083
11084         /* Wait 100ms (not adjusted according to platform) */
11085         DELAY(100000);
11086
11087         /* Verify no pending pci transactions */
11088         if (bnx2x_is_pcie_pending(sc)) {
11089                 PMD_DRV_LOG(NOTICE, sc, "PCIE Transactions still pending");
11090         }
11091
11092         /* Debug */
11093         bnx2x_hw_enable_status(sc);
11094
11095         /*
11096          * Master enable - Due to WB DMAE writes performed before this
11097          * register is re-initialized as part of the regular function init
11098          */
11099         REG_WR(sc, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 1);
11100
11101         return 0;
11102 }
11103
11104 static int bnx2x_init_hw_func(struct bnx2x_softc *sc)
11105 {
11106         int port = SC_PORT(sc);
11107         int func = SC_FUNC(sc);
11108         int init_phase = PHASE_PF0 + func;
11109         struct ecore_ilt *ilt = sc->ilt;
11110         uint16_t cdu_ilt_start;
11111         uint32_t addr, val;
11112         uint32_t main_mem_base, main_mem_size, main_mem_prty_clr;
11113         int main_mem_width, rc;
11114         uint32_t i;
11115
11116         PMD_DRV_LOG(DEBUG, sc, "starting func init for func %d", func);
11117
11118         /* FLR cleanup */
11119         if (!CHIP_IS_E1x(sc)) {
11120                 rc = bnx2x_pf_flr_clnup(sc);
11121                 if (rc) {
11122                         PMD_DRV_LOG(NOTICE, sc, "FLR cleanup failed!");
11123                         return rc;
11124                 }
11125         }
11126
11127         /* set MSI reconfigure capability */
11128         if (sc->devinfo.int_block == INT_BLOCK_HC) {
11129                 addr = (port ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0);
11130                 val = REG_RD(sc, addr);
11131                 val |= HC_CONFIG_0_REG_MSI_ATTN_EN_0;
11132                 REG_WR(sc, addr, val);
11133         }
11134
11135         ecore_init_block(sc, BLOCK_PXP, init_phase);
11136         ecore_init_block(sc, BLOCK_PXP2, init_phase);
11137
11138         ilt = sc->ilt;
11139         cdu_ilt_start = ilt->clients[ILT_CLIENT_CDU].start;
11140
11141         for (i = 0; i < L2_ILT_LINES(sc); i++) {
11142                 ilt->lines[cdu_ilt_start + i].page = sc->context[i].vcxt;
11143                 ilt->lines[cdu_ilt_start + i].page_mapping =
11144                     (rte_iova_t)sc->context[i].vcxt_dma.paddr;
11145                 ilt->lines[cdu_ilt_start + i].size = sc->context[i].size;
11146         }
11147         ecore_ilt_init_op(sc, INITOP_SET);
11148
11149         REG_WR(sc, PRS_REG_NIC_MODE, 1);
11150
11151         if (!CHIP_IS_E1x(sc)) {
11152                 uint32_t pf_conf = IGU_PF_CONF_FUNC_EN;
11153
11154 /* Turn on a single ISR mode in IGU if driver is going to use
11155  * INT#x or MSI
11156  */
11157                 if ((sc->interrupt_mode != INTR_MODE_MSIX)
11158                     || (sc->interrupt_mode != INTR_MODE_SINGLE_MSIX)) {
11159                         pf_conf |= IGU_PF_CONF_SINGLE_ISR_EN;
11160                 }
11161
11162 /*
11163  * Timers workaround bug: function init part.
11164  * Need to wait 20msec after initializing ILT,
11165  * needed to make sure there are no requests in
11166  * one of the PXP internal queues with "old" ILT addresses
11167  */
11168                 DELAY(20000);
11169
11170 /*
11171  * Master enable - Due to WB DMAE writes performed before this
11172  * register is re-initialized as part of the regular function
11173  * init
11174  */
11175                 REG_WR(sc, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 1);
11176 /* Enable the function in IGU */
11177                 REG_WR(sc, IGU_REG_PF_CONFIGURATION, pf_conf);
11178         }
11179
11180         sc->dmae_ready = 1;
11181
11182         ecore_init_block(sc, BLOCK_PGLUE_B, init_phase);
11183
11184         if (!CHIP_IS_E1x(sc))
11185                 REG_WR(sc, PGLUE_B_REG_WAS_ERROR_PF_7_0_CLR, func);
11186
11187         ecore_init_block(sc, BLOCK_ATC, init_phase);
11188         ecore_init_block(sc, BLOCK_DMAE, init_phase);
11189         ecore_init_block(sc, BLOCK_NIG, init_phase);
11190         ecore_init_block(sc, BLOCK_SRC, init_phase);
11191         ecore_init_block(sc, BLOCK_MISC, init_phase);
11192         ecore_init_block(sc, BLOCK_TCM, init_phase);
11193         ecore_init_block(sc, BLOCK_UCM, init_phase);
11194         ecore_init_block(sc, BLOCK_CCM, init_phase);
11195         ecore_init_block(sc, BLOCK_XCM, init_phase);
11196         ecore_init_block(sc, BLOCK_TSEM, init_phase);
11197         ecore_init_block(sc, BLOCK_USEM, init_phase);
11198         ecore_init_block(sc, BLOCK_CSEM, init_phase);
11199         ecore_init_block(sc, BLOCK_XSEM, init_phase);
11200
11201         if (!CHIP_IS_E1x(sc))
11202                 REG_WR(sc, QM_REG_PF_EN, 1);
11203
11204         if (!CHIP_IS_E1x(sc)) {
11205                 REG_WR(sc, TSEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func);
11206                 REG_WR(sc, USEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func);
11207                 REG_WR(sc, CSEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func);
11208                 REG_WR(sc, XSEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func);
11209         }
11210         ecore_init_block(sc, BLOCK_QM, init_phase);
11211
11212         ecore_init_block(sc, BLOCK_TM, init_phase);
11213         ecore_init_block(sc, BLOCK_DORQ, init_phase);
11214
11215         ecore_init_block(sc, BLOCK_BRB1, init_phase);
11216         ecore_init_block(sc, BLOCK_PRS, init_phase);
11217         ecore_init_block(sc, BLOCK_TSDM, init_phase);
11218         ecore_init_block(sc, BLOCK_CSDM, init_phase);
11219         ecore_init_block(sc, BLOCK_USDM, init_phase);
11220         ecore_init_block(sc, BLOCK_XSDM, init_phase);
11221         ecore_init_block(sc, BLOCK_UPB, init_phase);
11222         ecore_init_block(sc, BLOCK_XPB, init_phase);
11223         ecore_init_block(sc, BLOCK_PBF, init_phase);
11224         if (!CHIP_IS_E1x(sc))
11225                 REG_WR(sc, PBF_REG_DISABLE_PF, 0);
11226
11227         ecore_init_block(sc, BLOCK_CDU, init_phase);
11228
11229         ecore_init_block(sc, BLOCK_CFC, init_phase);
11230
11231         if (!CHIP_IS_E1x(sc))
11232                 REG_WR(sc, CFC_REG_WEAK_ENABLE_PF, 1);
11233
11234         if (IS_MF(sc)) {
11235                 REG_WR(sc, NIG_REG_LLH0_FUNC_EN + port * 8, 1);
11236                 REG_WR(sc, NIG_REG_LLH0_FUNC_VLAN_ID + port * 8, OVLAN(sc));
11237         }
11238
11239         ecore_init_block(sc, BLOCK_MISC_AEU, init_phase);
11240
11241         /* HC init per function */
11242         if (sc->devinfo.int_block == INT_BLOCK_HC) {
11243                 if (CHIP_IS_E1H(sc)) {
11244                         REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_12 + func * 4, 0);
11245
11246                         REG_WR(sc, HC_REG_LEADING_EDGE_0 + port * 8, 0);
11247                         REG_WR(sc, HC_REG_TRAILING_EDGE_0 + port * 8, 0);
11248                 }
11249                 ecore_init_block(sc, BLOCK_HC, init_phase);
11250
11251         } else {
11252                 uint32_t num_segs, sb_idx, prod_offset;
11253
11254                 REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_12 + func * 4, 0);
11255
11256                 if (!CHIP_IS_E1x(sc)) {
11257                         REG_WR(sc, IGU_REG_LEADING_EDGE_LATCH, 0);
11258                         REG_WR(sc, IGU_REG_TRAILING_EDGE_LATCH, 0);
11259                 }
11260
11261                 ecore_init_block(sc, BLOCK_IGU, init_phase);
11262
11263                 if (!CHIP_IS_E1x(sc)) {
11264                         int dsb_idx = 0;
11265         /**
11266          * Producer memory:
11267          * E2 mode: address 0-135 match to the mapping memory;
11268          * 136 - PF0 default prod; 137 - PF1 default prod;
11269          * 138 - PF2 default prod; 139 - PF3 default prod;
11270          * 140 - PF0 attn prod;    141 - PF1 attn prod;
11271          * 142 - PF2 attn prod;    143 - PF3 attn prod;
11272          * 144-147 reserved.
11273          *
11274          * E1.5 mode - In backward compatible mode;
11275          * for non default SB; each even line in the memory
11276          * holds the U producer and each odd line hold
11277          * the C producer. The first 128 producers are for
11278          * NDSB (PF0 - 0-31; PF1 - 32-63 and so on). The last 20
11279          * producers are for the DSB for each PF.
11280          * Each PF has five segments: (the order inside each
11281          * segment is PF0; PF1; PF2; PF3) - 128-131 U prods;
11282          * 132-135 C prods; 136-139 X prods; 140-143 T prods;
11283          * 144-147 attn prods;
11284          */
11285                         /* non-default-status-blocks */
11286                         num_segs = CHIP_INT_MODE_IS_BC(sc) ?
11287                             IGU_BC_NDSB_NUM_SEGS : IGU_NORM_NDSB_NUM_SEGS;
11288                         for (sb_idx = 0; sb_idx < sc->igu_sb_cnt; sb_idx++) {
11289                                 prod_offset = (sc->igu_base_sb + sb_idx) *
11290                                     num_segs;
11291
11292                                 for (i = 0; i < num_segs; i++) {
11293                                         addr = IGU_REG_PROD_CONS_MEMORY +
11294                                             (prod_offset + i) * 4;
11295                                         REG_WR(sc, addr, 0);
11296                                 }
11297                                 /* send consumer update with value 0 */
11298                                 bnx2x_ack_sb(sc, sc->igu_base_sb + sb_idx,
11299                                            USTORM_ID, 0, IGU_INT_NOP, 1);
11300                                 bnx2x_igu_clear_sb(sc, sc->igu_base_sb + sb_idx);
11301                         }
11302
11303                         /* default-status-blocks */
11304                         num_segs = CHIP_INT_MODE_IS_BC(sc) ?
11305                             IGU_BC_DSB_NUM_SEGS : IGU_NORM_DSB_NUM_SEGS;
11306
11307                         if (CHIP_IS_MODE_4_PORT(sc))
11308                                 dsb_idx = SC_FUNC(sc);
11309                         else
11310                                 dsb_idx = SC_VN(sc);
11311
11312                         prod_offset = (CHIP_INT_MODE_IS_BC(sc) ?
11313                                        IGU_BC_BASE_DSB_PROD + dsb_idx :
11314                                        IGU_NORM_BASE_DSB_PROD + dsb_idx);
11315
11316                         /*
11317                          * igu prods come in chunks of E1HVN_MAX (4) -
11318                          * does not matters what is the current chip mode
11319                          */
11320                         for (i = 0; i < (num_segs * E1HVN_MAX); i += E1HVN_MAX) {
11321                                 addr = IGU_REG_PROD_CONS_MEMORY +
11322                                     (prod_offset + i) * 4;
11323                                 REG_WR(sc, addr, 0);
11324                         }
11325                         /* send consumer update with 0 */
11326                         if (CHIP_INT_MODE_IS_BC(sc)) {
11327                                 bnx2x_ack_sb(sc, sc->igu_dsb_id,
11328                                            USTORM_ID, 0, IGU_INT_NOP, 1);
11329                                 bnx2x_ack_sb(sc, sc->igu_dsb_id,
11330                                            CSTORM_ID, 0, IGU_INT_NOP, 1);
11331                                 bnx2x_ack_sb(sc, sc->igu_dsb_id,
11332                                            XSTORM_ID, 0, IGU_INT_NOP, 1);
11333                                 bnx2x_ack_sb(sc, sc->igu_dsb_id,
11334                                            TSTORM_ID, 0, IGU_INT_NOP, 1);
11335                                 bnx2x_ack_sb(sc, sc->igu_dsb_id,
11336                                            ATTENTION_ID, 0, IGU_INT_NOP, 1);
11337                         } else {
11338                                 bnx2x_ack_sb(sc, sc->igu_dsb_id,
11339                                            USTORM_ID, 0, IGU_INT_NOP, 1);
11340                                 bnx2x_ack_sb(sc, sc->igu_dsb_id,
11341                                            ATTENTION_ID, 0, IGU_INT_NOP, 1);
11342                         }
11343                         bnx2x_igu_clear_sb(sc, sc->igu_dsb_id);
11344
11345                         /* !!! these should become driver const once
11346                            rf-tool supports split-68 const */
11347                         REG_WR(sc, IGU_REG_SB_INT_BEFORE_MASK_LSB, 0);
11348                         REG_WR(sc, IGU_REG_SB_INT_BEFORE_MASK_MSB, 0);
11349                         REG_WR(sc, IGU_REG_SB_MASK_LSB, 0);
11350                         REG_WR(sc, IGU_REG_SB_MASK_MSB, 0);
11351                         REG_WR(sc, IGU_REG_PBA_STATUS_LSB, 0);
11352                         REG_WR(sc, IGU_REG_PBA_STATUS_MSB, 0);
11353                 }
11354         }
11355
11356         /* Reset PCIE errors for debug */
11357         REG_WR(sc, 0x2114, 0xffffffff);
11358         REG_WR(sc, 0x2120, 0xffffffff);
11359
11360         if (CHIP_IS_E1x(sc)) {
11361                 main_mem_size = HC_REG_MAIN_MEMORY_SIZE / 2;    /*dwords */
11362                 main_mem_base = HC_REG_MAIN_MEMORY +
11363                     SC_PORT(sc) * (main_mem_size * 4);
11364                 main_mem_prty_clr = HC_REG_HC_PRTY_STS_CLR;
11365                 main_mem_width = 8;
11366
11367                 val = REG_RD(sc, main_mem_prty_clr);
11368                 if (val) {
11369                         PMD_DRV_LOG(DEBUG, sc,
11370                                     "Parity errors in HC block during function init (0x%x)!",
11371                                     val);
11372                 }
11373
11374 /* Clear "false" parity errors in MSI-X table */
11375                 for (i = main_mem_base;
11376                      i < main_mem_base + main_mem_size * 4;
11377                      i += main_mem_width) {
11378                         bnx2x_read_dmae(sc, i, main_mem_width / 4);
11379                         bnx2x_write_dmae(sc, BNX2X_SP_MAPPING(sc, wb_data),
11380                                        i, main_mem_width / 4);
11381                 }
11382 /* Clear HC parity attention */
11383                 REG_RD(sc, main_mem_prty_clr);
11384         }
11385
11386         /* Enable STORMs SP logging */
11387         REG_WR8(sc, BAR_USTRORM_INTMEM +
11388                 USTORM_RECORD_SLOW_PATH_OFFSET(SC_FUNC(sc)), 1);
11389         REG_WR8(sc, BAR_TSTRORM_INTMEM +
11390                 TSTORM_RECORD_SLOW_PATH_OFFSET(SC_FUNC(sc)), 1);
11391         REG_WR8(sc, BAR_CSTRORM_INTMEM +
11392                 CSTORM_RECORD_SLOW_PATH_OFFSET(SC_FUNC(sc)), 1);
11393         REG_WR8(sc, BAR_XSTRORM_INTMEM +
11394                 XSTORM_RECORD_SLOW_PATH_OFFSET(SC_FUNC(sc)), 1);
11395
11396         elink_phy_probe(&sc->link_params);
11397
11398         return 0;
11399 }
11400
11401 static void bnx2x_link_reset(struct bnx2x_softc *sc)
11402 {
11403         if (!BNX2X_NOMCP(sc)) {
11404                 bnx2x_acquire_phy_lock(sc);
11405                 elink_lfa_reset(&sc->link_params, &sc->link_vars);
11406                 bnx2x_release_phy_lock(sc);
11407         } else {
11408                 if (!CHIP_REV_IS_SLOW(sc)) {
11409                         PMD_DRV_LOG(WARNING, sc,
11410                                     "Bootcode is missing - cannot reset link");
11411                 }
11412         }
11413 }
11414
11415 static void bnx2x_reset_port(struct bnx2x_softc *sc)
11416 {
11417         int port = SC_PORT(sc);
11418         uint32_t val;
11419
11420         /* reset physical Link */
11421         bnx2x_link_reset(sc);
11422
11423         REG_WR(sc, NIG_REG_MASK_INTERRUPT_PORT0 + port * 4, 0);
11424
11425         /* Do not rcv packets to BRB */
11426         REG_WR(sc, NIG_REG_LLH0_BRB1_DRV_MASK + port * 4, 0x0);
11427         /* Do not direct rcv packets that are not for MCP to the BRB */
11428         REG_WR(sc, (port ? NIG_REG_LLH1_BRB1_NOT_MCP :
11429                     NIG_REG_LLH0_BRB1_NOT_MCP), 0x0);
11430
11431         /* Configure AEU */
11432         REG_WR(sc, MISC_REG_AEU_MASK_ATTN_FUNC_0 + port * 4, 0);
11433
11434         DELAY(100000);
11435
11436         /* Check for BRB port occupancy */
11437         val = REG_RD(sc, BRB1_REG_PORT_NUM_OCC_BLOCKS_0 + port * 4);
11438         if (val) {
11439                 PMD_DRV_LOG(DEBUG, sc,
11440                             "BRB1 is not empty, %d blocks are occupied", val);
11441         }
11442 }
11443
11444 static void bnx2x_ilt_wr(struct bnx2x_softc *sc, uint32_t index, rte_iova_t addr)
11445 {
11446         int reg;
11447         uint32_t wb_write[2];
11448
11449         reg = PXP2_REG_RQ_ONCHIP_AT_B0 + index * 8;
11450
11451         wb_write[0] = ONCHIP_ADDR1(addr);
11452         wb_write[1] = ONCHIP_ADDR2(addr);
11453         REG_WR_DMAE(sc, reg, wb_write, 2);
11454 }
11455
11456 static void bnx2x_clear_func_ilt(struct bnx2x_softc *sc, uint32_t func)
11457 {
11458         uint32_t i, base = FUNC_ILT_BASE(func);
11459         for (i = base; i < base + ILT_PER_FUNC; i++) {
11460                 bnx2x_ilt_wr(sc, i, 0);
11461         }
11462 }
11463
11464 static void bnx2x_reset_func(struct bnx2x_softc *sc)
11465 {
11466         struct bnx2x_fastpath *fp;
11467         int port = SC_PORT(sc);
11468         int func = SC_FUNC(sc);
11469         int i;
11470
11471         /* Disable the function in the FW */
11472         REG_WR8(sc, BAR_XSTRORM_INTMEM + XSTORM_FUNC_EN_OFFSET(func), 0);
11473         REG_WR8(sc, BAR_CSTRORM_INTMEM + CSTORM_FUNC_EN_OFFSET(func), 0);
11474         REG_WR8(sc, BAR_TSTRORM_INTMEM + TSTORM_FUNC_EN_OFFSET(func), 0);
11475         REG_WR8(sc, BAR_USTRORM_INTMEM + USTORM_FUNC_EN_OFFSET(func), 0);
11476
11477         /* FP SBs */
11478         FOR_EACH_ETH_QUEUE(sc, i) {
11479                 fp = &sc->fp[i];
11480                 REG_WR8(sc, BAR_CSTRORM_INTMEM +
11481                         CSTORM_STATUS_BLOCK_DATA_STATE_OFFSET(fp->fw_sb_id),
11482                         SB_DISABLED);
11483         }
11484
11485         /* SP SB */
11486         REG_WR8(sc, BAR_CSTRORM_INTMEM +
11487                 CSTORM_SP_STATUS_BLOCK_DATA_STATE_OFFSET(func), SB_DISABLED);
11488
11489         for (i = 0; i < XSTORM_SPQ_DATA_SIZE / 4; i++) {
11490                 REG_WR(sc, BAR_XSTRORM_INTMEM + XSTORM_SPQ_DATA_OFFSET(func),
11491                        0);
11492         }
11493
11494         /* Configure IGU */
11495         if (sc->devinfo.int_block == INT_BLOCK_HC) {
11496                 REG_WR(sc, HC_REG_LEADING_EDGE_0 + port * 8, 0);
11497                 REG_WR(sc, HC_REG_TRAILING_EDGE_0 + port * 8, 0);
11498         } else {
11499                 REG_WR(sc, IGU_REG_LEADING_EDGE_LATCH, 0);
11500                 REG_WR(sc, IGU_REG_TRAILING_EDGE_LATCH, 0);
11501         }
11502
11503         if (CNIC_LOADED(sc)) {
11504 /* Disable Timer scan */
11505                 REG_WR(sc, TM_REG_EN_LINEAR0_TIMER + port * 4, 0);
11506 /*
11507  * Wait for at least 10ms and up to 2 second for the timers
11508  * scan to complete
11509  */
11510                 for (i = 0; i < 200; i++) {
11511                         DELAY(10000);
11512                         if (!REG_RD(sc, TM_REG_LIN0_SCAN_ON + port * 4))
11513                                 break;
11514                 }
11515         }
11516
11517         /* Clear ILT */
11518         bnx2x_clear_func_ilt(sc, func);
11519
11520         /*
11521          * Timers workaround bug for E2: if this is vnic-3,
11522          * we need to set the entire ilt range for this timers.
11523          */
11524         if (!CHIP_IS_E1x(sc) && SC_VN(sc) == 3) {
11525                 struct ilt_client_info ilt_cli;
11526 /* use dummy TM client */
11527                 memset(&ilt_cli, 0, sizeof(struct ilt_client_info));
11528                 ilt_cli.start = 0;
11529                 ilt_cli.end = ILT_NUM_PAGE_ENTRIES - 1;
11530                 ilt_cli.client_num = ILT_CLIENT_TM;
11531
11532                 ecore_ilt_boundry_init_op(sc, &ilt_cli, 0);
11533         }
11534
11535         /* this assumes that reset_port() called before reset_func() */
11536         if (!CHIP_IS_E1x(sc)) {
11537                 bnx2x_pf_disable(sc);
11538         }
11539
11540         sc->dmae_ready = 0;
11541 }
11542
11543 static void bnx2x_release_firmware(struct bnx2x_softc *sc)
11544 {
11545         rte_free(sc->init_ops);
11546         rte_free(sc->init_ops_offsets);
11547         rte_free(sc->init_data);
11548         rte_free(sc->iro_array);
11549 }
11550
11551 static int bnx2x_init_firmware(struct bnx2x_softc *sc)
11552 {
11553         uint32_t len, i;
11554         uint8_t *p = sc->firmware;
11555         uint32_t off[24];
11556
11557         for (i = 0; i < 24; ++i)
11558                 off[i] = rte_be_to_cpu_32(*((uint32_t *) sc->firmware + i));
11559
11560         len = off[0];
11561         sc->init_ops = rte_zmalloc("", len, RTE_CACHE_LINE_SIZE);
11562         if (!sc->init_ops)
11563                 goto alloc_failed;
11564         bnx2x_data_to_init_ops(p + off[1], sc->init_ops, len);
11565
11566         len = off[2];
11567         sc->init_ops_offsets = rte_zmalloc("", len, RTE_CACHE_LINE_SIZE);
11568         if (!sc->init_ops_offsets)
11569                 goto alloc_failed;
11570         bnx2x_data_to_init_offsets(p + off[3], sc->init_ops_offsets, len);
11571
11572         len = off[4];
11573         sc->init_data = rte_zmalloc("", len, RTE_CACHE_LINE_SIZE);
11574         if (!sc->init_data)
11575                 goto alloc_failed;
11576         bnx2x_data_to_init_data(p + off[5], sc->init_data, len);
11577
11578         sc->tsem_int_table_data = p + off[7];
11579         sc->tsem_pram_data = p + off[9];
11580         sc->usem_int_table_data = p + off[11];
11581         sc->usem_pram_data = p + off[13];
11582         sc->csem_int_table_data = p + off[15];
11583         sc->csem_pram_data = p + off[17];
11584         sc->xsem_int_table_data = p + off[19];
11585         sc->xsem_pram_data = p + off[21];
11586
11587         len = off[22];
11588         sc->iro_array = rte_zmalloc("", len, RTE_CACHE_LINE_SIZE);
11589         if (!sc->iro_array)
11590                 goto alloc_failed;
11591         bnx2x_data_to_iro_array(p + off[23], sc->iro_array, len);
11592
11593         return 0;
11594
11595 alloc_failed:
11596         bnx2x_release_firmware(sc);
11597         return -1;
11598 }
11599
11600 static int cut_gzip_prefix(const uint8_t * zbuf, int len)
11601 {
11602 #define MIN_PREFIX_SIZE (10)
11603
11604         int n = MIN_PREFIX_SIZE;
11605         uint16_t xlen;
11606
11607         if (!(zbuf[0] == 0x1f && zbuf[1] == 0x8b && zbuf[2] == Z_DEFLATED) ||
11608             len <= MIN_PREFIX_SIZE) {
11609                 return -1;
11610         }
11611
11612         /* optional extra fields are present */
11613         if (zbuf[3] & 0x4) {
11614                 xlen = zbuf[13];
11615                 xlen <<= 8;
11616                 xlen += zbuf[12];
11617
11618                 n += xlen;
11619         }
11620         /* file name is present */
11621         if (zbuf[3] & 0x8) {
11622                 while ((zbuf[n++] != 0) && (n < len)) ;
11623         }
11624
11625         return n;
11626 }
11627
11628 static int ecore_gunzip(struct bnx2x_softc *sc, const uint8_t * zbuf, int len)
11629 {
11630         int ret;
11631         int data_begin = cut_gzip_prefix(zbuf, len);
11632
11633         PMD_DRV_LOG(DEBUG, sc, "ecore_gunzip %d", len);
11634
11635         if (data_begin <= 0) {
11636                 PMD_DRV_LOG(NOTICE, sc, "bad gzip prefix");
11637                 return -1;
11638         }
11639
11640         memset(&zlib_stream, 0, sizeof(zlib_stream));
11641         zlib_stream.next_in = zbuf + data_begin;
11642         zlib_stream.avail_in = len - data_begin;
11643         zlib_stream.next_out = sc->gz_buf;
11644         zlib_stream.avail_out = FW_BUF_SIZE;
11645
11646         ret = inflateInit2(&zlib_stream, -MAX_WBITS);
11647         if (ret != Z_OK) {
11648                 PMD_DRV_LOG(NOTICE, sc, "zlib inflateInit2 error");
11649                 return ret;
11650         }
11651
11652         ret = inflate(&zlib_stream, Z_FINISH);
11653         if ((ret != Z_STREAM_END) && (ret != Z_OK)) {
11654                 PMD_DRV_LOG(NOTICE, sc, "zlib inflate error: %d %s", ret,
11655                             zlib_stream.msg);
11656         }
11657
11658         sc->gz_outlen = zlib_stream.total_out;
11659         if (sc->gz_outlen & 0x3) {
11660                 PMD_DRV_LOG(NOTICE, sc, "firmware is not aligned. gz_outlen == %d",
11661                             sc->gz_outlen);
11662         }
11663         sc->gz_outlen >>= 2;
11664
11665         inflateEnd(&zlib_stream);
11666
11667         if (ret == Z_STREAM_END)
11668                 return 0;
11669
11670         return ret;
11671 }
11672
11673 static void
11674 ecore_write_dmae_phys_len(struct bnx2x_softc *sc, rte_iova_t phys_addr,
11675                           uint32_t addr, uint32_t len)
11676 {
11677         bnx2x_write_dmae_phys_len(sc, phys_addr, addr, len);
11678 }
11679
11680 void
11681 ecore_storm_memset_struct(struct bnx2x_softc *sc, uint32_t addr, size_t size,
11682                           uint32_t * data)
11683 {
11684         uint8_t i;
11685         for (i = 0; i < size / 4; i++) {
11686                 REG_WR(sc, addr + (i * 4), data[i]);
11687         }
11688 }
11689
11690 static const char *get_ext_phy_type(uint32_t ext_phy_type)
11691 {
11692         uint32_t phy_type_idx = ext_phy_type >> 8;
11693         static const char *types[] =
11694             { "DIRECT", "BNX2X-8071", "BNX2X-8072", "BNX2X-8073",
11695                 "BNX2X-8705", "BNX2X-8706", "BNX2X-8726", "BNX2X-8481", "SFX-7101",
11696                 "BNX2X-8727",
11697                 "BNX2X-8727-NOC", "BNX2X-84823", "NOT_CONN", "FAILURE"
11698         };
11699
11700         if (phy_type_idx < 12)
11701                 return types[phy_type_idx];
11702         else if (PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN == ext_phy_type)
11703                 return types[12];
11704         else
11705                 return types[13];
11706 }
11707
11708 static const char *get_state(uint32_t state)
11709 {
11710         uint32_t state_idx = state >> 12;
11711         static const char *states[] = { "CLOSED", "OPENING_WAIT4_LOAD",
11712                 "OPENING_WAIT4_PORT", "OPEN", "CLOSING_WAIT4_HALT",
11713                 "CLOSING_WAIT4_DELETE", "CLOSING_WAIT4_UNLOAD",
11714                 "UNKNOWN", "UNKNOWN", "UNKNOWN", "UNKNOWN", "UNKNOWN",
11715                 "UNKNOWN", "DISABLED", "DIAG", "ERROR", "UNDEFINED"
11716         };
11717
11718         if (state_idx <= 0xF)
11719                 return states[state_idx];
11720         else
11721                 return states[0x10];
11722 }
11723
11724 static const char *get_recovery_state(uint32_t state)
11725 {
11726         static const char *states[] = { "NONE", "DONE", "INIT",
11727                 "WAIT", "FAILED", "NIC_LOADING"
11728         };
11729         return states[state];
11730 }
11731
11732 static const char *get_rx_mode(uint32_t mode)
11733 {
11734         static const char *modes[] = { "NONE", "NORMAL", "ALLMULTI",
11735                 "PROMISC", "MAX_MULTICAST", "ERROR"
11736         };
11737
11738         if (mode < 0x4)
11739                 return modes[mode];
11740         else if (BNX2X_MAX_MULTICAST == mode)
11741                 return modes[4];
11742         else
11743                 return modes[5];
11744 }
11745
11746 #define BNX2X_INFO_STR_MAX 256
11747 static const char *get_bnx2x_flags(uint32_t flags)
11748 {
11749         int i;
11750         static const char *flag[] = { "ONE_PORT ", "NO_ISCSI ",
11751                 "NO_FCOE ", "NO_WOL ", "USING_DAC ", "USING_MSIX ",
11752                 "USING_MSI ", "DISABLE_MSI ", "UNKNOWN ", "NO_MCP ",
11753                 "SAFC_TX_FLAG ", "MF_FUNC_DIS ", "TX_SWITCHING "
11754         };
11755         static char flag_str[BNX2X_INFO_STR_MAX];
11756         memset(flag_str, 0, BNX2X_INFO_STR_MAX);
11757
11758         for (i = 0; i < 5; i++)
11759                 if (flags & (1 << i)) {
11760                         strlcat(flag_str, flag[i], sizeof(flag_str));
11761                         flags ^= (1 << i);
11762                 }
11763         if (flags) {
11764                 static char unknown[BNX2X_INFO_STR_MAX];
11765                 snprintf(unknown, 32, "Unknown flag mask %x", flags);
11766                 strlcat(flag_str, unknown, sizeof(flag_str));
11767         }
11768         return flag_str;
11769 }
11770
11771 /* Prints useful adapter info. */
11772 void bnx2x_print_adapter_info(struct bnx2x_softc *sc)
11773 {
11774         int i = 0;
11775
11776         PMD_DRV_LOG(INFO, sc, "========================================");
11777         /* DPDK and Driver versions */
11778         PMD_DRV_LOG(INFO, sc, "%12s : %s", "DPDK",
11779                         rte_version());
11780         PMD_DRV_LOG(INFO, sc, "%12s : %s", "Driver",
11781                         bnx2x_pmd_version());
11782         /* Firmware versions. */
11783         PMD_DRV_LOG(INFO, sc, "%12s : %d.%d.%d",
11784                      "Firmware",
11785                      BNX2X_5710_FW_MAJOR_VERSION,
11786                      BNX2X_5710_FW_MINOR_VERSION,
11787                      BNX2X_5710_FW_REVISION_VERSION);
11788         PMD_DRV_LOG(INFO, sc, "%12s : %s",
11789                      "Bootcode", sc->devinfo.bc_ver_str);
11790         /* Hardware chip info. */
11791         PMD_DRV_LOG(INFO, sc, "%12s : %#08x", "ASIC", sc->devinfo.chip_id);
11792         PMD_DRV_LOG(INFO, sc, "%12s : %c%d", "Rev", (CHIP_REV(sc) >> 12) + 'A',
11793                      (CHIP_METAL(sc) >> 4));
11794         /* Bus PCIe info. */
11795         PMD_DRV_LOG(INFO, sc, "%12s : 0x%x", "Vendor Id",
11796                     sc->devinfo.vendor_id);
11797         PMD_DRV_LOG(INFO, sc, "%12s : 0x%x", "Device Id",
11798                     sc->devinfo.device_id);
11799         PMD_DRV_LOG(INFO, sc, "%12s : width x%d, ", "Bus PCIe",
11800                     sc->devinfo.pcie_link_width);
11801         switch (sc->devinfo.pcie_link_speed) {
11802         case 1:
11803                 PMD_DRV_LOG(INFO, sc, "%23s", "2.5 Gbps");
11804                 break;
11805         case 2:
11806                 PMD_DRV_LOG(INFO, sc, "%21s", "5 Gbps");
11807                 break;
11808         case 4:
11809                 PMD_DRV_LOG(INFO, sc, "%21s", "8 Gbps");
11810                 break;
11811         default:
11812                 PMD_DRV_LOG(INFO, sc, "%33s", "Unknown link speed");
11813         }
11814         /* Device features. */
11815         PMD_DRV_LOG(INFO, sc, "%12s : ", "Flags");
11816         /* Miscellaneous flags. */
11817         if (sc->devinfo.pcie_cap_flags & BNX2X_MSI_CAPABLE_FLAG) {
11818                 PMD_DRV_LOG(INFO, sc, "%18s", "MSI");
11819                 i++;
11820         }
11821         if (sc->devinfo.pcie_cap_flags & BNX2X_MSIX_CAPABLE_FLAG) {
11822                 if (i > 0)
11823                         PMD_DRV_LOG(INFO, sc, "|");
11824                 PMD_DRV_LOG(INFO, sc, "%20s", "MSI-X");
11825                 i++;
11826         }
11827         PMD_DRV_LOG(INFO, sc, "%12s : %s", "OVLAN", (OVLAN(sc) ? "YES" : "NO"));
11828         PMD_DRV_LOG(INFO, sc, "%12s : %s", "MF", (IS_MF(sc) ? "YES" : "NO"));
11829         PMD_DRV_LOG(INFO, sc, "========================================");
11830 }
11831
11832 /* Prints useful device info. */
11833 void bnx2x_print_device_info(struct bnx2x_softc *sc)
11834 {
11835         __rte_unused uint32_t ext_phy_type;
11836         uint32_t offset, reg_val;
11837
11838         PMD_INIT_FUNC_TRACE(sc);
11839         offset = offsetof(struct shmem_region,
11840                           dev_info.port_hw_config[0].external_phy_config);
11841         reg_val = REG_RD(sc, sc->devinfo.shmem_base + offset);
11842         if (sc->link_vars.phy_flags & PHY_XGXS_FLAG)
11843                 ext_phy_type = ELINK_XGXS_EXT_PHY_TYPE(reg_val);
11844         else
11845                 ext_phy_type = ELINK_SERDES_EXT_PHY_TYPE(reg_val);
11846
11847         /* Device features. */
11848         PMD_DRV_LOG(INFO, sc, "%12s : %u", "Bnx2x Func", sc->pcie_func);
11849         PMD_DRV_LOG(INFO, sc,
11850                     "%12s : %s", "Bnx2x Flags", get_bnx2x_flags(sc->flags));
11851         PMD_DRV_LOG(INFO, sc, "%12s : %s", "DMAE Is",
11852                      (sc->dmae_ready ? "Ready" : "Not Ready"));
11853         PMD_DRV_LOG(INFO, sc, "%12s : %u", "MTU", sc->mtu);
11854         PMD_DRV_LOG(INFO, sc,
11855                     "%12s : %s", "PHY Type", get_ext_phy_type(ext_phy_type));
11856         PMD_DRV_LOG(INFO, sc, "%12s : %x:%x:%x:%x:%x:%x", "MAC Addr",
11857                         sc->link_params.mac_addr[0],
11858                         sc->link_params.mac_addr[1],
11859                         sc->link_params.mac_addr[2],
11860                         sc->link_params.mac_addr[3],
11861                         sc->link_params.mac_addr[4],
11862                         sc->link_params.mac_addr[5]);
11863         PMD_DRV_LOG(INFO, sc, "%12s : %s", "RX Mode", get_rx_mode(sc->rx_mode));
11864         PMD_DRV_LOG(INFO, sc, "%12s : %s", "State", get_state(sc->state));
11865         if (sc->recovery_state)
11866                 PMD_DRV_LOG(INFO, sc, "%12s : %s", "Recovery",
11867                              get_recovery_state(sc->recovery_state));
11868         /* Queue info. */
11869         if (IS_PF(sc)) {
11870                 switch (sc->sp->rss_rdata.rss_mode) {
11871                 case ETH_RSS_MODE_DISABLED:
11872                         PMD_DRV_LOG(INFO, sc, "%12s : %s", "Queues", "RSS mode - None");
11873                         break;
11874                 case ETH_RSS_MODE_REGULAR:
11875                         PMD_DRV_LOG(INFO, sc, "%12s : %s,", "Queues", "RSS mode - Regular");
11876                         PMD_DRV_LOG(INFO, sc, "%16d", sc->num_queues);
11877                         break;
11878                 default:
11879                         PMD_DRV_LOG(INFO, sc, "%12s : %s", "Queues", "RSS mode - Unknown");
11880                         break;
11881                 }
11882         }
11883         PMD_DRV_LOG(INFO, sc, "%12s : CQ = %lx,  EQ = %lx", "SPQ Left",
11884                      sc->cq_spq_left, sc->eq_spq_left);
11885
11886         PMD_DRV_LOG(INFO, sc,
11887                     "%12s : %x", "Switch", sc->link_params.switch_cfg);
11888         PMD_DRV_LOG(INFO, sc, "pcie_bus=%d, pcie_device=%d",
11889                         sc->pcie_bus, sc->pcie_device);
11890         PMD_DRV_LOG(INFO, sc, "bar0.addr=%p, bar1.addr=%p",
11891                         sc->bar[BAR0].base_addr, sc->bar[BAR1].base_addr);
11892         PMD_DRV_LOG(INFO, sc, "port=%d, path=%d, vnic=%d, func=%d",
11893                         PORT_ID(sc), PATH_ID(sc), VNIC_ID(sc), FUNC_ID(sc));
11894 }