2 * Copyright (c) 2007-2013 Broadcom Corporation.
4 * Eric Davis <edavis@broadcom.com>
5 * David Christensen <davidch@broadcom.com>
6 * Gary Zambrano <zambrano@broadcom.com>
8 * Copyright (c) 2013-2015 Brocade Communications Systems, Inc.
9 * Copyright (c) 2015 QLogic Corporation.
10 * All rights reserved.
13 * See LICENSE.bnx2x_pmd for copyright and licensing details.
16 #define BNX2X_DRIVER_VERSION "1.78.18"
19 #include "bnx2x_vfpf.h"
21 #include "ecore_init.h"
22 #include "ecore_init_ops.h"
24 #include "rte_version.h"
25 #include "rte_pci_dev_ids.h"
27 #include <sys/types.h>
32 #define BNX2X_PMD_VER_PREFIX "BNX2X PMD"
33 #define BNX2X_PMD_VERSION_MAJOR 1
34 #define BNX2X_PMD_VERSION_MINOR 0
35 #define BNX2X_PMD_VERSION_PATCH 0
37 static inline const char *
38 bnx2x_pmd_version(void)
40 static char version[32];
42 snprintf(version, sizeof(version), "%s %s_%d.%d.%d",
45 BNX2X_PMD_VERSION_MAJOR,
46 BNX2X_PMD_VERSION_MINOR,
47 BNX2X_PMD_VERSION_PATCH);
52 static z_stream zlib_stream;
54 #define EVL_VLID_MASK 0x0FFF
56 #define BNX2X_DEF_SB_ATT_IDX 0x0001
57 #define BNX2X_DEF_SB_IDX 0x0002
60 * FLR Support - bnx2x_pf_flr_clnup() is called during nic_load in the per
61 * function HW initialization.
63 #define FLR_WAIT_USEC 10000 /* 10 msecs */
64 #define FLR_WAIT_INTERVAL 50 /* usecs */
65 #define FLR_POLL_CNT (FLR_WAIT_USEC / FLR_WAIT_INTERVAL) /* 200 */
67 struct pbf_pN_buf_regs {
74 struct pbf_pN_cmd_regs {
80 /* resources needed for unloading a previously loaded device */
82 #define BNX2X_PREV_WAIT_NEEDED 1
83 rte_spinlock_t bnx2x_prev_mtx;
84 struct bnx2x_prev_list_node {
85 LIST_ENTRY(bnx2x_prev_list_node) node;
93 static LIST_HEAD(, bnx2x_prev_list_node) bnx2x_prev_list
94 = LIST_HEAD_INITIALIZER(bnx2x_prev_list);
96 static int load_count[2][3] = { { 0 } };
97 /* per-path: 0-common, 1-port0, 2-port1 */
99 static void bnx2x_cmng_fns_init(struct bnx2x_softc *sc, uint8_t read_cfg,
101 static int bnx2x_get_cmng_fns_mode(struct bnx2x_softc *sc);
102 static void storm_memset_cmng(struct bnx2x_softc *sc, struct cmng_init *cmng,
104 static void bnx2x_set_reset_global(struct bnx2x_softc *sc);
105 static void bnx2x_set_reset_in_progress(struct bnx2x_softc *sc);
106 static uint8_t bnx2x_reset_is_done(struct bnx2x_softc *sc, int engine);
107 static uint8_t bnx2x_clear_pf_load(struct bnx2x_softc *sc);
108 static uint8_t bnx2x_chk_parity_attn(struct bnx2x_softc *sc, uint8_t * global,
110 static void bnx2x_int_disable(struct bnx2x_softc *sc);
111 static int bnx2x_release_leader_lock(struct bnx2x_softc *sc);
112 static void bnx2x_pf_disable(struct bnx2x_softc *sc);
113 static void bnx2x_update_rx_prod(struct bnx2x_softc *sc,
114 struct bnx2x_fastpath *fp,
115 uint16_t rx_bd_prod, uint16_t rx_cq_prod);
116 static void bnx2x_link_report(struct bnx2x_softc *sc);
117 void bnx2x_link_status_update(struct bnx2x_softc *sc);
118 static int bnx2x_alloc_mem(struct bnx2x_softc *sc);
119 static void bnx2x_free_mem(struct bnx2x_softc *sc);
120 static int bnx2x_alloc_fw_stats_mem(struct bnx2x_softc *sc);
121 static void bnx2x_free_fw_stats_mem(struct bnx2x_softc *sc);
122 static __attribute__ ((noinline))
123 int bnx2x_nic_load(struct bnx2x_softc *sc);
125 static int bnx2x_handle_sp_tq(struct bnx2x_softc *sc);
126 static void bnx2x_handle_fp_tq(struct bnx2x_fastpath *fp, int scan_fp);
127 static void bnx2x_periodic_stop(struct bnx2x_softc *sc);
128 static void bnx2x_ack_sb(struct bnx2x_softc *sc, uint8_t igu_sb_id,
129 uint8_t storm, uint16_t index, uint8_t op,
132 int bnx2x_test_bit(int nr, volatile unsigned long *addr)
137 res = ((*addr) & (1UL << nr)) != 0;
142 void bnx2x_set_bit(unsigned int nr, volatile unsigned long *addr)
144 __sync_fetch_and_or(addr, (1UL << nr));
147 void bnx2x_clear_bit(int nr, volatile unsigned long *addr)
149 __sync_fetch_and_and(addr, ~(1UL << nr));
152 int bnx2x_test_and_clear_bit(int nr, volatile unsigned long *addr)
154 unsigned long mask = (1UL << nr);
155 return __sync_fetch_and_and(addr, ~mask) & mask;
158 int bnx2x_cmpxchg(volatile int *addr, int old, int new)
160 return __sync_val_compare_and_swap(addr, old, new);
164 bnx2x_dma_alloc(struct bnx2x_softc *sc, size_t size, struct bnx2x_dma *dma,
165 const char *msg, uint32_t align)
167 char mz_name[RTE_MEMZONE_NAMESIZE];
168 const struct rte_memzone *z;
172 sprintf(mz_name, "bnx2x%d_%s_%" PRIx64, SC_ABS_FUNC(sc), msg,
173 rte_get_timer_cycles());
175 sprintf(mz_name, "bnx2x%d_%s_%" PRIx64, sc->pcie_device, msg,
176 rte_get_timer_cycles());
178 /* Caller must take care that strlen(mz_name) < RTE_MEMZONE_NAMESIZE */
179 z = rte_memzone_reserve_aligned(mz_name, (uint64_t) (size),
180 rte_lcore_to_socket_id(rte_lcore_id()),
183 PMD_DRV_LOG(ERR, "DMA alloc failed for %s", msg);
186 dma->paddr = (uint64_t) z->phys_addr;
187 dma->vaddr = z->addr;
189 PMD_DRV_LOG(DEBUG, "%s: virt=%p phys=%" PRIx64, msg, dma->vaddr, dma->paddr);
194 static int bnx2x_acquire_hw_lock(struct bnx2x_softc *sc, uint32_t resource)
196 uint32_t lock_status;
197 uint32_t resource_bit = (1 << resource);
198 int func = SC_FUNC(sc);
199 uint32_t hw_lock_control_reg;
202 PMD_INIT_FUNC_TRACE();
204 /* validate the resource is within range */
205 if (resource > HW_LOCK_MAX_RESOURCE_VALUE) {
207 "resource 0x%x > HW_LOCK_MAX_RESOURCE_VALUE",
213 hw_lock_control_reg = (MISC_REG_DRIVER_CONTROL_1 + (func * 8));
215 hw_lock_control_reg =
216 (MISC_REG_DRIVER_CONTROL_7 + ((func - 6) * 8));
219 /* validate the resource is not already taken */
220 lock_status = REG_RD(sc, hw_lock_control_reg);
221 if (lock_status & resource_bit) {
223 "resource in use (status 0x%x bit 0x%x)",
224 lock_status, resource_bit);
228 /* try every 5ms for 5 seconds */
229 for (cnt = 0; cnt < 1000; cnt++) {
230 REG_WR(sc, (hw_lock_control_reg + 4), resource_bit);
231 lock_status = REG_RD(sc, hw_lock_control_reg);
232 if (lock_status & resource_bit) {
238 PMD_DRV_LOG(NOTICE, "Resource lock timeout!");
242 static int bnx2x_release_hw_lock(struct bnx2x_softc *sc, uint32_t resource)
244 uint32_t lock_status;
245 uint32_t resource_bit = (1 << resource);
246 int func = SC_FUNC(sc);
247 uint32_t hw_lock_control_reg;
249 PMD_INIT_FUNC_TRACE();
251 /* validate the resource is within range */
252 if (resource > HW_LOCK_MAX_RESOURCE_VALUE) {
254 "resource 0x%x > HW_LOCK_MAX_RESOURCE_VALUE",
260 hw_lock_control_reg = (MISC_REG_DRIVER_CONTROL_1 + (func * 8));
262 hw_lock_control_reg =
263 (MISC_REG_DRIVER_CONTROL_7 + ((func - 6) * 8));
266 /* validate the resource is currently taken */
267 lock_status = REG_RD(sc, hw_lock_control_reg);
268 if (!(lock_status & resource_bit)) {
270 "resource not in use (status 0x%x bit 0x%x)",
271 lock_status, resource_bit);
275 REG_WR(sc, hw_lock_control_reg, resource_bit);
279 /* copy command into DMAE command memory and set DMAE command Go */
280 void bnx2x_post_dmae(struct bnx2x_softc *sc, struct dmae_command *dmae, int idx)
285 cmd_offset = (DMAE_REG_CMD_MEM + (sizeof(struct dmae_command) * idx));
286 for (i = 0; i < ((sizeof(struct dmae_command) / 4)); i++) {
287 REG_WR(sc, (cmd_offset + (i * 4)), *(((uint32_t *) dmae) + i));
290 REG_WR(sc, dmae_reg_go_c[idx], 1);
293 uint32_t bnx2x_dmae_opcode_add_comp(uint32_t opcode, uint8_t comp_type)
295 return (opcode | ((comp_type << DMAE_COMMAND_C_DST_SHIFT) |
296 DMAE_COMMAND_C_TYPE_ENABLE));
299 uint32_t bnx2x_dmae_opcode_clr_src_reset(uint32_t opcode)
301 return (opcode & ~DMAE_COMMAND_SRC_RESET);
305 bnx2x_dmae_opcode(struct bnx2x_softc * sc, uint8_t src_type, uint8_t dst_type,
306 uint8_t with_comp, uint8_t comp_type)
310 opcode |= ((src_type << DMAE_COMMAND_SRC_SHIFT) |
311 (dst_type << DMAE_COMMAND_DST_SHIFT));
313 opcode |= (DMAE_COMMAND_SRC_RESET | DMAE_COMMAND_DST_RESET);
315 opcode |= (SC_PORT(sc) ? DMAE_CMD_PORT_1 : DMAE_CMD_PORT_0);
317 opcode |= ((SC_VN(sc) << DMAE_COMMAND_E1HVN_SHIFT) |
318 (SC_VN(sc) << DMAE_COMMAND_DST_VN_SHIFT));
320 opcode |= (DMAE_COM_SET_ERR << DMAE_COMMAND_ERR_POLICY_SHIFT);
323 opcode |= DMAE_CMD_ENDIANITY_B_DW_SWAP;
325 opcode |= DMAE_CMD_ENDIANITY_DW_SWAP;
329 opcode = bnx2x_dmae_opcode_add_comp(opcode, comp_type);
336 bnx2x_prep_dmae_with_comp(struct bnx2x_softc *sc, struct dmae_command *dmae,
337 uint8_t src_type, uint8_t dst_type)
339 memset(dmae, 0, sizeof(struct dmae_command));
342 dmae->opcode = bnx2x_dmae_opcode(sc, src_type, dst_type,
343 TRUE, DMAE_COMP_PCI);
345 /* fill in the completion parameters */
346 dmae->comp_addr_lo = U64_LO(BNX2X_SP_MAPPING(sc, wb_comp));
347 dmae->comp_addr_hi = U64_HI(BNX2X_SP_MAPPING(sc, wb_comp));
348 dmae->comp_val = DMAE_COMP_VAL;
351 /* issue a DMAE command over the init channel and wait for completion */
353 bnx2x_issue_dmae_with_comp(struct bnx2x_softc *sc, struct dmae_command *dmae)
355 uint32_t *wb_comp = BNX2X_SP(sc, wb_comp);
356 int timeout = CHIP_REV_IS_SLOW(sc) ? 400000 : 4000;
358 /* reset completion */
361 /* post the command on the channel used for initializations */
362 bnx2x_post_dmae(sc, dmae, INIT_DMAE_C(sc));
364 /* wait for completion */
367 while ((*wb_comp & ~DMAE_PCI_ERR_FLAG) != DMAE_COMP_VAL) {
369 (sc->recovery_state != BNX2X_RECOVERY_DONE &&
370 sc->recovery_state != BNX2X_RECOVERY_NIC_LOADING)) {
371 PMD_DRV_LOG(INFO, "DMAE timeout!");
379 if (*wb_comp & DMAE_PCI_ERR_FLAG) {
380 PMD_DRV_LOG(INFO, "DMAE PCI error!");
381 return DMAE_PCI_ERROR;
387 void bnx2x_read_dmae(struct bnx2x_softc *sc, uint32_t src_addr, uint32_t len32)
389 struct dmae_command dmae;
394 if (!sc->dmae_ready) {
395 data = BNX2X_SP(sc, wb_data[0]);
397 for (i = 0; i < len32; i++) {
398 data[i] = REG_RD(sc, (src_addr + (i * 4)));
404 /* set opcode and fixed command fields */
405 bnx2x_prep_dmae_with_comp(sc, &dmae, DMAE_SRC_GRC, DMAE_DST_PCI);
407 /* fill in addresses and len */
408 dmae.src_addr_lo = (src_addr >> 2); /* GRC addr has dword resolution */
409 dmae.src_addr_hi = 0;
410 dmae.dst_addr_lo = U64_LO(BNX2X_SP_MAPPING(sc, wb_data));
411 dmae.dst_addr_hi = U64_HI(BNX2X_SP_MAPPING(sc, wb_data));
414 /* issue the command and wait for completion */
415 if ((rc = bnx2x_issue_dmae_with_comp(sc, &dmae)) != 0) {
416 rte_panic("DMAE failed (%d)", rc);
421 bnx2x_write_dmae(struct bnx2x_softc *sc, phys_addr_t dma_addr, uint32_t dst_addr,
424 struct dmae_command dmae;
427 if (!sc->dmae_ready) {
428 ecore_init_str_wr(sc, dst_addr, BNX2X_SP(sc, wb_data[0]), len32);
432 /* set opcode and fixed command fields */
433 bnx2x_prep_dmae_with_comp(sc, &dmae, DMAE_SRC_PCI, DMAE_DST_GRC);
435 /* fill in addresses and len */
436 dmae.src_addr_lo = U64_LO(dma_addr);
437 dmae.src_addr_hi = U64_HI(dma_addr);
438 dmae.dst_addr_lo = (dst_addr >> 2); /* GRC addr has dword resolution */
439 dmae.dst_addr_hi = 0;
442 /* issue the command and wait for completion */
443 if ((rc = bnx2x_issue_dmae_with_comp(sc, &dmae)) != 0) {
444 rte_panic("DMAE failed (%d)", rc);
449 bnx2x_write_dmae_phys_len(struct bnx2x_softc *sc, phys_addr_t phys_addr,
450 uint32_t addr, uint32_t len)
452 uint32_t dmae_wr_max = DMAE_LEN32_WR_MAX(sc);
455 while (len > dmae_wr_max) {
456 bnx2x_write_dmae(sc, (phys_addr + offset), /* src DMA address */
457 (addr + offset), /* dst GRC address */
459 offset += (dmae_wr_max * 4);
463 bnx2x_write_dmae(sc, (phys_addr + offset), /* src DMA address */
464 (addr + offset), /* dst GRC address */
469 bnx2x_set_ctx_validation(struct bnx2x_softc *sc, struct eth_context *cxt,
472 /* ustorm cxt validation */
473 cxt->ustorm_ag_context.cdu_usage =
474 CDU_RSRVD_VALUE_TYPE_A(HW_CID(sc, cid),
475 CDU_REGION_NUMBER_UCM_AG,
476 ETH_CONNECTION_TYPE);
477 /* xcontext validation */
478 cxt->xstorm_ag_context.cdu_reserved =
479 CDU_RSRVD_VALUE_TYPE_A(HW_CID(sc, cid),
480 CDU_REGION_NUMBER_XCM_AG,
481 ETH_CONNECTION_TYPE);
485 bnx2x_storm_memset_hc_timeout(struct bnx2x_softc *sc, uint8_t fw_sb_id,
486 uint8_t sb_index, uint8_t ticks)
489 (BAR_CSTRORM_INTMEM +
490 CSTORM_STATUS_BLOCK_DATA_TIMEOUT_OFFSET(fw_sb_id, sb_index));
492 REG_WR8(sc, addr, ticks);
496 bnx2x_storm_memset_hc_disable(struct bnx2x_softc *sc, uint16_t fw_sb_id,
497 uint8_t sb_index, uint8_t disable)
499 uint32_t enable_flag =
500 (disable) ? 0 : (1 << HC_INDEX_DATA_HC_ENABLED_SHIFT);
502 (BAR_CSTRORM_INTMEM +
503 CSTORM_STATUS_BLOCK_DATA_FLAGS_OFFSET(fw_sb_id, sb_index));
507 flags = REG_RD8(sc, addr);
508 flags &= ~HC_INDEX_DATA_HC_ENABLED;
509 flags |= enable_flag;
510 REG_WR8(sc, addr, flags);
514 bnx2x_update_coalesce_sb_index(struct bnx2x_softc *sc, uint8_t fw_sb_id,
515 uint8_t sb_index, uint8_t disable, uint16_t usec)
517 uint8_t ticks = (usec / 4);
519 bnx2x_storm_memset_hc_timeout(sc, fw_sb_id, sb_index, ticks);
521 disable = (disable) ? 1 : ((usec) ? 0 : 1);
522 bnx2x_storm_memset_hc_disable(sc, fw_sb_id, sb_index, disable);
525 uint32_t elink_cb_reg_read(struct bnx2x_softc *sc, uint32_t reg_addr)
527 return REG_RD(sc, reg_addr);
530 void elink_cb_reg_write(struct bnx2x_softc *sc, uint32_t reg_addr, uint32_t val)
532 REG_WR(sc, reg_addr, val);
536 elink_cb_event_log(__rte_unused struct bnx2x_softc *sc,
537 __rte_unused const elink_log_id_t elink_log_id, ...)
539 PMD_DRV_LOG(DEBUG, "ELINK EVENT LOG (%d)", elink_log_id);
542 static int bnx2x_set_spio(struct bnx2x_softc *sc, int spio, uint32_t mode)
546 /* Only 2 SPIOs are configurable */
547 if ((spio != MISC_SPIO_SPIO4) && (spio != MISC_SPIO_SPIO5)) {
548 PMD_DRV_LOG(NOTICE, "Invalid SPIO 0x%x", spio);
552 bnx2x_acquire_hw_lock(sc, HW_LOCK_RESOURCE_SPIO);
554 /* read SPIO and mask except the float bits */
555 spio_reg = (REG_RD(sc, MISC_REG_SPIO) & MISC_SPIO_FLOAT);
558 case MISC_SPIO_OUTPUT_LOW:
559 /* clear FLOAT and set CLR */
560 spio_reg &= ~(spio << MISC_SPIO_FLOAT_POS);
561 spio_reg |= (spio << MISC_SPIO_CLR_POS);
564 case MISC_SPIO_OUTPUT_HIGH:
565 /* clear FLOAT and set SET */
566 spio_reg &= ~(spio << MISC_SPIO_FLOAT_POS);
567 spio_reg |= (spio << MISC_SPIO_SET_POS);
570 case MISC_SPIO_INPUT_HI_Z:
572 spio_reg |= (spio << MISC_SPIO_FLOAT_POS);
579 REG_WR(sc, MISC_REG_SPIO, spio_reg);
580 bnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_SPIO);
585 static int bnx2x_gpio_read(struct bnx2x_softc *sc, int gpio_num, uint8_t port)
587 /* The GPIO should be swapped if swap register is set and active */
588 int gpio_port = ((REG_RD(sc, NIG_REG_PORT_SWAP) &&
589 REG_RD(sc, NIG_REG_STRAP_OVERRIDE)) ^ port);
590 int gpio_shift = gpio_num;
592 gpio_shift += MISC_REGISTERS_GPIO_PORT_SHIFT;
594 uint32_t gpio_mask = (1 << gpio_shift);
597 if (gpio_num > MISC_REGISTERS_GPIO_3) {
598 PMD_DRV_LOG(NOTICE, "Invalid GPIO %d", gpio_num);
602 /* read GPIO value */
603 gpio_reg = REG_RD(sc, MISC_REG_GPIO);
605 /* get the requested pin value */
606 return ((gpio_reg & gpio_mask) == gpio_mask) ? 1 : 0;
610 bnx2x_gpio_write(struct bnx2x_softc *sc, int gpio_num, uint32_t mode, uint8_t port)
612 /* The GPIO should be swapped if swap register is set and active */
613 int gpio_port = ((REG_RD(sc, NIG_REG_PORT_SWAP) &&
614 REG_RD(sc, NIG_REG_STRAP_OVERRIDE)) ^ port);
615 int gpio_shift = gpio_num;
617 gpio_shift += MISC_REGISTERS_GPIO_PORT_SHIFT;
619 uint32_t gpio_mask = (1 << gpio_shift);
622 if (gpio_num > MISC_REGISTERS_GPIO_3) {
623 PMD_DRV_LOG(NOTICE, "Invalid GPIO %d", gpio_num);
627 bnx2x_acquire_hw_lock(sc, HW_LOCK_RESOURCE_GPIO);
629 /* read GPIO and mask except the float bits */
630 gpio_reg = (REG_RD(sc, MISC_REG_GPIO) & MISC_REGISTERS_GPIO_FLOAT);
633 case MISC_REGISTERS_GPIO_OUTPUT_LOW:
634 /* clear FLOAT and set CLR */
635 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS);
636 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_CLR_POS);
639 case MISC_REGISTERS_GPIO_OUTPUT_HIGH:
640 /* clear FLOAT and set SET */
641 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS);
642 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_SET_POS);
645 case MISC_REGISTERS_GPIO_INPUT_HI_Z:
647 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS);
654 REG_WR(sc, MISC_REG_GPIO, gpio_reg);
655 bnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_GPIO);
661 bnx2x_gpio_mult_write(struct bnx2x_softc *sc, uint8_t pins, uint32_t mode)
665 /* any port swapping should be handled by caller */
667 bnx2x_acquire_hw_lock(sc, HW_LOCK_RESOURCE_GPIO);
669 /* read GPIO and mask except the float bits */
670 gpio_reg = REG_RD(sc, MISC_REG_GPIO);
671 gpio_reg &= ~(pins << MISC_REGISTERS_GPIO_FLOAT_POS);
672 gpio_reg &= ~(pins << MISC_REGISTERS_GPIO_CLR_POS);
673 gpio_reg &= ~(pins << MISC_REGISTERS_GPIO_SET_POS);
676 case MISC_REGISTERS_GPIO_OUTPUT_LOW:
678 gpio_reg |= (pins << MISC_REGISTERS_GPIO_CLR_POS);
681 case MISC_REGISTERS_GPIO_OUTPUT_HIGH:
683 gpio_reg |= (pins << MISC_REGISTERS_GPIO_SET_POS);
686 case MISC_REGISTERS_GPIO_INPUT_HI_Z:
688 gpio_reg |= (pins << MISC_REGISTERS_GPIO_FLOAT_POS);
692 PMD_DRV_LOG(NOTICE, "Invalid GPIO mode assignment %d", mode);
693 bnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_GPIO);
697 REG_WR(sc, MISC_REG_GPIO, gpio_reg);
698 bnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_GPIO);
704 bnx2x_gpio_int_write(struct bnx2x_softc *sc, int gpio_num, uint32_t mode,
707 /* The GPIO should be swapped if swap register is set and active */
708 int gpio_port = ((REG_RD(sc, NIG_REG_PORT_SWAP) &&
709 REG_RD(sc, NIG_REG_STRAP_OVERRIDE)) ^ port);
710 int gpio_shift = gpio_num;
712 gpio_shift += MISC_REGISTERS_GPIO_PORT_SHIFT;
714 uint32_t gpio_mask = (1 << gpio_shift);
717 if (gpio_num > MISC_REGISTERS_GPIO_3) {
718 PMD_DRV_LOG(NOTICE, "Invalid GPIO %d", gpio_num);
722 bnx2x_acquire_hw_lock(sc, HW_LOCK_RESOURCE_GPIO);
725 gpio_reg = REG_RD(sc, MISC_REG_GPIO_INT);
728 case MISC_REGISTERS_GPIO_INT_OUTPUT_CLR:
729 /* clear SET and set CLR */
730 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_INT_SET_POS);
731 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_INT_CLR_POS);
734 case MISC_REGISTERS_GPIO_INT_OUTPUT_SET:
735 /* clear CLR and set SET */
736 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_INT_CLR_POS);
737 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_INT_SET_POS);
744 REG_WR(sc, MISC_REG_GPIO_INT, gpio_reg);
745 bnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_GPIO);
751 elink_cb_gpio_read(struct bnx2x_softc * sc, uint16_t gpio_num, uint8_t port)
753 return bnx2x_gpio_read(sc, gpio_num, port);
756 uint8_t elink_cb_gpio_write(struct bnx2x_softc * sc, uint16_t gpio_num, uint8_t mode, /* 0=low 1=high */
759 return bnx2x_gpio_write(sc, gpio_num, mode, port);
763 elink_cb_gpio_mult_write(struct bnx2x_softc * sc, uint8_t pins,
764 uint8_t mode /* 0=low 1=high */ )
766 return bnx2x_gpio_mult_write(sc, pins, mode);
769 uint8_t elink_cb_gpio_int_write(struct bnx2x_softc * sc, uint16_t gpio_num, uint8_t mode, /* 0=low 1=high */
772 return bnx2x_gpio_int_write(sc, gpio_num, mode, port);
775 void elink_cb_notify_link_changed(struct bnx2x_softc *sc)
777 REG_WR(sc, (MISC_REG_AEU_GENERAL_ATTN_12 +
778 (SC_FUNC(sc) * sizeof(uint32_t))), 1);
781 /* send the MCP a request, block until there is a reply */
783 elink_cb_fw_command(struct bnx2x_softc *sc, uint32_t command, uint32_t param)
785 int mb_idx = SC_FW_MB_IDX(sc);
789 uint8_t delay = CHIP_REV_IS_SLOW(sc) ? 100 : 10;
792 SHMEM_WR(sc, func_mb[mb_idx].drv_mb_param, param);
793 SHMEM_WR(sc, func_mb[mb_idx].drv_mb_header, (command | seq));
796 "wrote command 0x%08x to FW MB param 0x%08x",
797 (command | seq), param);
799 /* Let the FW do it's magic. GIve it up to 5 seconds... */
802 rc = SHMEM_RD(sc, func_mb[mb_idx].fw_mb_header);
803 } while ((seq != (rc & FW_MSG_SEQ_NUMBER_MASK)) && (cnt++ < 500));
805 /* is this a reply to our command? */
806 if (seq == (rc & FW_MSG_SEQ_NUMBER_MASK)) {
807 rc &= FW_MSG_CODE_MASK;
810 PMD_DRV_LOG(NOTICE, "FW failed to respond!");
818 bnx2x_fw_command(struct bnx2x_softc *sc, uint32_t command, uint32_t param)
820 return elink_cb_fw_command(sc, command, param);
824 __storm_memset_dma_mapping(struct bnx2x_softc *sc, uint32_t addr,
827 REG_WR(sc, addr, U64_LO(mapping));
828 REG_WR(sc, (addr + 4), U64_HI(mapping));
832 storm_memset_spq_addr(struct bnx2x_softc *sc, phys_addr_t mapping,
835 uint32_t addr = (XSEM_REG_FAST_MEMORY +
836 XSTORM_SPQ_PAGE_BASE_OFFSET(abs_fid));
837 __storm_memset_dma_mapping(sc, addr, mapping);
841 storm_memset_vf_to_pf(struct bnx2x_softc *sc, uint16_t abs_fid, uint16_t pf_id)
843 REG_WR8(sc, (BAR_XSTRORM_INTMEM + XSTORM_VF_TO_PF_OFFSET(abs_fid)),
845 REG_WR8(sc, (BAR_CSTRORM_INTMEM + CSTORM_VF_TO_PF_OFFSET(abs_fid)),
847 REG_WR8(sc, (BAR_TSTRORM_INTMEM + TSTORM_VF_TO_PF_OFFSET(abs_fid)),
849 REG_WR8(sc, (BAR_USTRORM_INTMEM + USTORM_VF_TO_PF_OFFSET(abs_fid)),
854 storm_memset_func_en(struct bnx2x_softc *sc, uint16_t abs_fid, uint8_t enable)
856 REG_WR8(sc, (BAR_XSTRORM_INTMEM + XSTORM_FUNC_EN_OFFSET(abs_fid)),
858 REG_WR8(sc, (BAR_CSTRORM_INTMEM + CSTORM_FUNC_EN_OFFSET(abs_fid)),
860 REG_WR8(sc, (BAR_TSTRORM_INTMEM + TSTORM_FUNC_EN_OFFSET(abs_fid)),
862 REG_WR8(sc, (BAR_USTRORM_INTMEM + USTORM_FUNC_EN_OFFSET(abs_fid)),
867 storm_memset_eq_data(struct bnx2x_softc *sc, struct event_ring_data *eq_data,
873 addr = (BAR_CSTRORM_INTMEM + CSTORM_EVENT_RING_DATA_OFFSET(pfid));
874 size = sizeof(struct event_ring_data);
875 ecore_storm_memset_struct(sc, addr, size, (uint32_t *) eq_data);
879 storm_memset_eq_prod(struct bnx2x_softc *sc, uint16_t eq_prod, uint16_t pfid)
881 uint32_t addr = (BAR_CSTRORM_INTMEM +
882 CSTORM_EVENT_RING_PROD_OFFSET(pfid));
883 REG_WR16(sc, addr, eq_prod);
887 * Post a slowpath command.
889 * A slowpath command is used to propogate a configuration change through
890 * the controller in a controlled manner, allowing each STORM processor and
891 * other H/W blocks to phase in the change. The commands sent on the
892 * slowpath are referred to as ramrods. Depending on the ramrod used the
893 * completion of the ramrod will occur in different ways. Here's a
894 * breakdown of ramrods and how they complete:
896 * RAMROD_CMD_ID_ETH_PORT_SETUP
897 * Used to setup the leading connection on a port. Completes on the
898 * Receive Completion Queue (RCQ) of that port (typically fp[0]).
900 * RAMROD_CMD_ID_ETH_CLIENT_SETUP
901 * Used to setup an additional connection on a port. Completes on the
902 * RCQ of the multi-queue/RSS connection being initialized.
904 * RAMROD_CMD_ID_ETH_STAT_QUERY
905 * Used to force the storm processors to update the statistics database
906 * in host memory. This ramrod is send on the leading connection CID and
907 * completes as an index increment of the CSTORM on the default status
910 * RAMROD_CMD_ID_ETH_UPDATE
911 * Used to update the state of the leading connection, usually to udpate
912 * the RSS indirection table. Completes on the RCQ of the leading
913 * connection. (Not currently used under FreeBSD until OS support becomes
916 * RAMROD_CMD_ID_ETH_HALT
917 * Used when tearing down a connection prior to driver unload. Completes
918 * on the RCQ of the multi-queue/RSS connection being torn down. Don't
919 * use this on the leading connection.
921 * RAMROD_CMD_ID_ETH_SET_MAC
922 * Sets the Unicast/Broadcast/Multicast used by the port. Completes on
923 * the RCQ of the leading connection.
925 * RAMROD_CMD_ID_ETH_CFC_DEL
926 * Used when tearing down a conneciton prior to driver unload. Completes
927 * on the RCQ of the leading connection (since the current connection
928 * has been completely removed from controller memory).
930 * RAMROD_CMD_ID_ETH_PORT_DEL
931 * Used to tear down the leading connection prior to driver unload,
932 * typically fp[0]. Completes as an index increment of the CSTORM on the
933 * default status block.
935 * RAMROD_CMD_ID_ETH_FORWARD_SETUP
936 * Used for connection offload. Completes on the RCQ of the multi-queue
937 * RSS connection that is being offloaded. (Not currently used under
940 * There can only be one command pending per function.
943 * 0 = Success, !0 = Failure.
946 /* must be called under the spq lock */
947 static inline struct eth_spe *bnx2x_sp_get_next(struct bnx2x_softc *sc)
949 struct eth_spe *next_spe = sc->spq_prod_bd;
951 if (sc->spq_prod_bd == sc->spq_last_bd) {
952 /* wrap back to the first eth_spq */
953 sc->spq_prod_bd = sc->spq;
954 sc->spq_prod_idx = 0;
963 /* must be called under the spq lock */
964 static void bnx2x_sp_prod_update(struct bnx2x_softc *sc)
966 int func = SC_FUNC(sc);
969 * Make sure that BD data is updated before writing the producer.
970 * BD data is written to the memory, the producer is read from the
971 * memory, thus we need a full memory barrier to ensure the ordering.
975 REG_WR16(sc, (BAR_XSTRORM_INTMEM + XSTORM_SPQ_PROD_OFFSET(func)),
982 * bnx2x_is_contextless_ramrod - check if the current command ends on EQ
984 * @cmd: command to check
985 * @cmd_type: command type
987 static int bnx2x_is_contextless_ramrod(int cmd, int cmd_type)
989 if ((cmd_type == NONE_CONNECTION_TYPE) ||
990 (cmd == RAMROD_CMD_ID_ETH_FORWARD_SETUP) ||
991 (cmd == RAMROD_CMD_ID_ETH_CLASSIFICATION_RULES) ||
992 (cmd == RAMROD_CMD_ID_ETH_FILTER_RULES) ||
993 (cmd == RAMROD_CMD_ID_ETH_MULTICAST_RULES) ||
994 (cmd == RAMROD_CMD_ID_ETH_SET_MAC) ||
995 (cmd == RAMROD_CMD_ID_ETH_RSS_UPDATE)) {
1003 * bnx2x_sp_post - place a single command on an SP ring
1005 * @sc: driver handle
1006 * @command: command to place (e.g. SETUP, FILTER_RULES, etc.)
1007 * @cid: SW CID the command is related to
1008 * @data_hi: command private data address (high 32 bits)
1009 * @data_lo: command private data address (low 32 bits)
1010 * @cmd_type: command type (e.g. NONE, ETH)
1012 * SP data is handled as if it's always an address pair, thus data fields are
1013 * not swapped to little endian in upper functions. Instead this function swaps
1014 * data as if it's two uint32 fields.
1017 bnx2x_sp_post(struct bnx2x_softc *sc, int command, int cid, uint32_t data_hi,
1018 uint32_t data_lo, int cmd_type)
1020 struct eth_spe *spe;
1024 common = bnx2x_is_contextless_ramrod(command, cmd_type);
1027 if (!atomic_load_acq_long(&sc->eq_spq_left)) {
1028 PMD_DRV_LOG(INFO, "EQ ring is full!");
1032 if (!atomic_load_acq_long(&sc->cq_spq_left)) {
1033 PMD_DRV_LOG(INFO, "SPQ ring is full!");
1038 spe = bnx2x_sp_get_next(sc);
1040 /* CID needs port number to be encoded int it */
1041 spe->hdr.conn_and_cmd_data =
1042 htole32((command << SPE_HDR_CMD_ID_SHIFT) | HW_CID(sc, cid));
1044 type = (cmd_type << SPE_HDR_CONN_TYPE_SHIFT) & SPE_HDR_CONN_TYPE;
1046 /* TBD: Check if it works for VFs */
1047 type |= ((SC_FUNC(sc) << SPE_HDR_FUNCTION_ID_SHIFT) &
1048 SPE_HDR_FUNCTION_ID);
1050 spe->hdr.type = htole16(type);
1052 spe->data.update_data_addr.hi = htole32(data_hi);
1053 spe->data.update_data_addr.lo = htole32(data_lo);
1056 * It's ok if the actual decrement is issued towards the memory
1057 * somewhere between the lock and unlock. Thus no more explict
1058 * memory barrier is needed.
1061 atomic_subtract_acq_long(&sc->eq_spq_left, 1);
1063 atomic_subtract_acq_long(&sc->cq_spq_left, 1);
1067 "SPQE[%x] (%x:%x) (cmd, common?) (%d,%d) hw_cid %x"
1068 "data (%x:%x) type(0x%x) left (CQ, EQ) (%lx,%lx)",
1070 (uint32_t) U64_HI(sc->spq_dma.paddr),
1071 (uint32_t) (U64_LO(sc->spq_dma.paddr) +
1072 (uint8_t *) sc->spq_prod_bd -
1073 (uint8_t *) sc->spq), command, common,
1074 HW_CID(sc, cid), data_hi, data_lo, type,
1075 atomic_load_acq_long(&sc->cq_spq_left),
1076 atomic_load_acq_long(&sc->eq_spq_left));
1078 bnx2x_sp_prod_update(sc);
1083 static void bnx2x_drv_pulse(struct bnx2x_softc *sc)
1085 SHMEM_WR(sc, func_mb[SC_FW_MB_IDX(sc)].drv_pulse_mb,
1086 sc->fw_drv_pulse_wr_seq);
1089 static int bnx2x_tx_queue_has_work(const struct bnx2x_fastpath *fp)
1092 struct bnx2x_tx_queue *txq = fp->sc->tx_queues[fp->index];
1094 if (unlikely(!txq)) {
1095 PMD_TX_LOG(ERR, "ERROR: TX queue is NULL");
1099 mb(); /* status block fields can change */
1100 hw_cons = le16toh(*fp->tx_cons_sb);
1101 return (hw_cons != txq->tx_pkt_head);
1104 static uint8_t bnx2x_has_tx_work(struct bnx2x_fastpath *fp)
1106 /* expand this for multi-cos if ever supported */
1107 return bnx2x_tx_queue_has_work(fp);
1110 static int bnx2x_has_rx_work(struct bnx2x_fastpath *fp)
1112 uint16_t rx_cq_cons_sb;
1113 struct bnx2x_rx_queue *rxq;
1114 rxq = fp->sc->rx_queues[fp->index];
1115 if (unlikely(!rxq)) {
1116 PMD_RX_LOG(ERR, "ERROR: RX queue is NULL");
1120 mb(); /* status block fields can change */
1121 rx_cq_cons_sb = le16toh(*fp->rx_cq_cons_sb);
1122 if (unlikely((rx_cq_cons_sb & MAX_RCQ_ENTRIES(rxq)) ==
1123 MAX_RCQ_ENTRIES(rxq)))
1125 return (rxq->rx_cq_head != rx_cq_cons_sb);
1129 bnx2x_sp_event(struct bnx2x_softc *sc, struct bnx2x_fastpath *fp,
1130 union eth_rx_cqe *rr_cqe)
1132 #ifdef RTE_LIBRTE_BNX2X_DEBUG
1133 int cid = SW_CID(rr_cqe->ramrod_cqe.conn_and_cmd_data);
1135 int command = CQE_CMD(rr_cqe->ramrod_cqe.conn_and_cmd_data);
1136 enum ecore_queue_cmd drv_cmd = ECORE_Q_CMD_MAX;
1137 struct ecore_queue_sp_obj *q_obj = &BNX2X_SP_OBJ(sc, fp).q_obj;
1140 "fp=%d cid=%d got ramrod #%d state is %x type is %d",
1141 fp->index, cid, command, sc->state,
1142 rr_cqe->ramrod_cqe.ramrod_type);
1145 case (RAMROD_CMD_ID_ETH_CLIENT_UPDATE):
1146 PMD_DRV_LOG(DEBUG, "got UPDATE ramrod. CID %d", cid);
1147 drv_cmd = ECORE_Q_CMD_UPDATE;
1150 case (RAMROD_CMD_ID_ETH_CLIENT_SETUP):
1151 PMD_DRV_LOG(DEBUG, "got MULTI[%d] setup ramrod", cid);
1152 drv_cmd = ECORE_Q_CMD_SETUP;
1155 case (RAMROD_CMD_ID_ETH_TX_QUEUE_SETUP):
1156 PMD_DRV_LOG(DEBUG, "got MULTI[%d] tx-only setup ramrod", cid);
1157 drv_cmd = ECORE_Q_CMD_SETUP_TX_ONLY;
1160 case (RAMROD_CMD_ID_ETH_HALT):
1161 PMD_DRV_LOG(DEBUG, "got MULTI[%d] halt ramrod", cid);
1162 drv_cmd = ECORE_Q_CMD_HALT;
1165 case (RAMROD_CMD_ID_ETH_TERMINATE):
1166 PMD_DRV_LOG(DEBUG, "got MULTI[%d] teminate ramrod", cid);
1167 drv_cmd = ECORE_Q_CMD_TERMINATE;
1170 case (RAMROD_CMD_ID_ETH_EMPTY):
1171 PMD_DRV_LOG(DEBUG, "got MULTI[%d] empty ramrod", cid);
1172 drv_cmd = ECORE_Q_CMD_EMPTY;
1177 "ERROR: unexpected MC reply (%d)"
1178 "on fp[%d]", command, fp->index);
1182 if ((drv_cmd != ECORE_Q_CMD_MAX) &&
1183 q_obj->complete_cmd(sc, q_obj, drv_cmd)) {
1185 * q_obj->complete_cmd() failure means that this was
1186 * an unexpected completion.
1188 * In this case we don't want to increase the sc->spq_left
1189 * because apparently we haven't sent this command the first
1192 // rte_panic("Unexpected SP completion");
1196 atomic_add_acq_long(&sc->cq_spq_left, 1);
1198 PMD_DRV_LOG(DEBUG, "sc->cq_spq_left 0x%lx",
1199 atomic_load_acq_long(&sc->cq_spq_left));
1202 static uint8_t bnx2x_rxeof(struct bnx2x_softc *sc, struct bnx2x_fastpath *fp)
1204 struct bnx2x_rx_queue *rxq;
1205 uint16_t bd_cons, bd_prod, bd_prod_fw, comp_ring_cons;
1206 uint16_t hw_cq_cons, sw_cq_cons, sw_cq_prod;
1208 rxq = sc->rx_queues[fp->index];
1210 PMD_RX_LOG(ERR, "RX queue %d is NULL", fp->index);
1214 /* CQ "next element" is of the size of the regular element */
1215 hw_cq_cons = le16toh(*fp->rx_cq_cons_sb);
1216 if (unlikely((hw_cq_cons & USABLE_RCQ_ENTRIES_PER_PAGE) ==
1217 USABLE_RCQ_ENTRIES_PER_PAGE)) {
1221 bd_cons = rxq->rx_bd_head;
1222 bd_prod = rxq->rx_bd_tail;
1223 bd_prod_fw = bd_prod;
1224 sw_cq_cons = rxq->rx_cq_head;
1225 sw_cq_prod = rxq->rx_cq_tail;
1228 * Memory barrier necessary as speculative reads of the rx
1229 * buffer can be ahead of the index in the status block
1233 while (sw_cq_cons != hw_cq_cons) {
1234 union eth_rx_cqe *cqe;
1235 struct eth_fast_path_rx_cqe *cqe_fp;
1236 uint8_t cqe_fp_flags;
1237 enum eth_rx_cqe_type cqe_fp_type;
1239 comp_ring_cons = RCQ_ENTRY(sw_cq_cons, rxq);
1240 bd_prod = RX_BD(bd_prod, rxq);
1241 bd_cons = RX_BD(bd_cons, rxq);
1243 cqe = &rxq->cq_ring[comp_ring_cons];
1244 cqe_fp = &cqe->fast_path_cqe;
1245 cqe_fp_flags = cqe_fp->type_error_flags;
1246 cqe_fp_type = cqe_fp_flags & ETH_FAST_PATH_RX_CQE_TYPE;
1248 /* is this a slowpath msg? */
1249 if (CQE_TYPE_SLOW(cqe_fp_type)) {
1250 bnx2x_sp_event(sc, fp, cqe);
1254 /* is this an error packet? */
1255 if (unlikely(cqe_fp_flags &
1256 ETH_FAST_PATH_RX_CQE_PHY_DECODE_ERR_FLG)) {
1257 PMD_RX_LOG(DEBUG, "flags 0x%x rx packet %u",
1258 cqe_fp_flags, sw_cq_cons);
1262 PMD_RX_LOG(DEBUG, "Dropping fastpath called from attn poller!");
1265 bd_cons = NEXT_RX_BD(bd_cons);
1266 bd_prod = NEXT_RX_BD(bd_prod);
1267 bd_prod_fw = NEXT_RX_BD(bd_prod_fw);
1270 sw_cq_prod = NEXT_RCQ_IDX(sw_cq_prod);
1271 sw_cq_cons = NEXT_RCQ_IDX(sw_cq_cons);
1273 } /* while work to do */
1275 rxq->rx_bd_head = bd_cons;
1276 rxq->rx_bd_tail = bd_prod_fw;
1277 rxq->rx_cq_head = sw_cq_cons;
1278 rxq->rx_cq_tail = sw_cq_prod;
1280 /* Update producers */
1281 bnx2x_update_rx_prod(sc, fp, bd_prod_fw, sw_cq_prod);
1283 return (sw_cq_cons != hw_cq_cons);
1287 bnx2x_free_tx_pkt(__rte_unused struct bnx2x_fastpath *fp, struct bnx2x_tx_queue *txq,
1288 uint16_t pkt_idx, uint16_t bd_idx)
1290 struct eth_tx_start_bd *tx_start_bd =
1291 &txq->tx_ring[TX_BD(bd_idx, txq)].start_bd;
1292 uint16_t nbd = rte_le_to_cpu_16(tx_start_bd->nbd);
1293 struct rte_mbuf *tx_mbuf = txq->sw_ring[TX_BD(pkt_idx, txq)];
1295 if (likely(tx_mbuf != NULL)) {
1296 rte_pktmbuf_free(tx_mbuf);
1298 PMD_RX_LOG(ERR, "fp[%02d] lost mbuf %lu",
1299 fp->index, (unsigned long)TX_BD(pkt_idx, txq));
1302 txq->sw_ring[TX_BD(pkt_idx, txq)] = NULL;
1303 txq->nb_tx_avail += nbd;
1306 bd_idx = NEXT_TX_BD(bd_idx);
1311 /* processes transmit completions */
1312 uint8_t bnx2x_txeof(__rte_unused struct bnx2x_softc * sc, struct bnx2x_fastpath * fp)
1314 uint16_t bd_cons, hw_cons, sw_cons;
1315 __rte_unused uint16_t tx_bd_avail;
1317 struct bnx2x_tx_queue *txq = fp->sc->tx_queues[fp->index];
1319 if (unlikely(!txq)) {
1320 PMD_TX_LOG(ERR, "ERROR: TX queue is NULL");
1324 bd_cons = txq->tx_bd_head;
1325 hw_cons = rte_le_to_cpu_16(*fp->tx_cons_sb);
1326 sw_cons = txq->tx_pkt_head;
1328 while (sw_cons != hw_cons) {
1329 bd_cons = bnx2x_free_tx_pkt(fp, txq, sw_cons, bd_cons);
1333 txq->tx_pkt_head = sw_cons;
1334 txq->tx_bd_head = bd_cons;
1336 tx_bd_avail = txq->nb_tx_avail;
1338 PMD_TX_LOG(DEBUG, "fp[%02d] avail=%u cons_sb=%u, "
1339 "pkt_head=%u pkt_tail=%u bd_head=%u bd_tail=%u",
1340 fp->index, tx_bd_avail, hw_cons,
1341 txq->tx_pkt_head, txq->tx_pkt_tail,
1342 txq->tx_bd_head, txq->tx_bd_tail);
1346 static void bnx2x_drain_tx_queues(struct bnx2x_softc *sc)
1348 struct bnx2x_fastpath *fp;
1351 /* wait until all TX fastpath tasks have completed */
1352 for (i = 0; i < sc->num_queues; i++) {
1357 while (bnx2x_has_tx_work(fp)) {
1358 bnx2x_txeof(sc, fp);
1362 "Timeout waiting for fp[%d] "
1363 "transmits to complete!", i);
1364 rte_panic("tx drain failure");
1378 bnx2x_del_all_macs(struct bnx2x_softc *sc, struct ecore_vlan_mac_obj *mac_obj,
1379 int mac_type, uint8_t wait_for_comp)
1381 unsigned long ramrod_flags = 0, vlan_mac_flags = 0;
1384 /* wait for completion of requested */
1385 if (wait_for_comp) {
1386 bnx2x_set_bit(RAMROD_COMP_WAIT, &ramrod_flags);
1389 /* Set the mac type of addresses we want to clear */
1390 bnx2x_set_bit(mac_type, &vlan_mac_flags);
1392 rc = mac_obj->delete_all(sc, mac_obj, &vlan_mac_flags, &ramrod_flags);
1394 PMD_DRV_LOG(ERR, "Failed to delete MACs (%d)", rc);
1400 bnx2x_fill_accept_flags(struct bnx2x_softc *sc, uint32_t rx_mode,
1401 unsigned long *rx_accept_flags,
1402 unsigned long *tx_accept_flags)
1404 /* Clear the flags first */
1405 *rx_accept_flags = 0;
1406 *tx_accept_flags = 0;
1409 case BNX2X_RX_MODE_NONE:
1411 * 'drop all' supersedes any accept flags that may have been
1412 * passed to the function.
1416 case BNX2X_RX_MODE_NORMAL:
1417 bnx2x_set_bit(ECORE_ACCEPT_UNICAST, rx_accept_flags);
1418 bnx2x_set_bit(ECORE_ACCEPT_MULTICAST, rx_accept_flags);
1419 bnx2x_set_bit(ECORE_ACCEPT_BROADCAST, rx_accept_flags);
1421 /* internal switching mode */
1422 bnx2x_set_bit(ECORE_ACCEPT_UNICAST, tx_accept_flags);
1423 bnx2x_set_bit(ECORE_ACCEPT_MULTICAST, tx_accept_flags);
1424 bnx2x_set_bit(ECORE_ACCEPT_BROADCAST, tx_accept_flags);
1428 case BNX2X_RX_MODE_ALLMULTI:
1429 bnx2x_set_bit(ECORE_ACCEPT_UNICAST, rx_accept_flags);
1430 bnx2x_set_bit(ECORE_ACCEPT_ALL_MULTICAST, rx_accept_flags);
1431 bnx2x_set_bit(ECORE_ACCEPT_BROADCAST, rx_accept_flags);
1433 /* internal switching mode */
1434 bnx2x_set_bit(ECORE_ACCEPT_UNICAST, tx_accept_flags);
1435 bnx2x_set_bit(ECORE_ACCEPT_ALL_MULTICAST, tx_accept_flags);
1436 bnx2x_set_bit(ECORE_ACCEPT_BROADCAST, tx_accept_flags);
1440 case BNX2X_RX_MODE_PROMISC:
1442 * According to deffinition of SI mode, iface in promisc mode
1443 * should receive matched and unmatched (in resolution of port)
1446 bnx2x_set_bit(ECORE_ACCEPT_UNMATCHED, rx_accept_flags);
1447 bnx2x_set_bit(ECORE_ACCEPT_UNICAST, rx_accept_flags);
1448 bnx2x_set_bit(ECORE_ACCEPT_ALL_MULTICAST, rx_accept_flags);
1449 bnx2x_set_bit(ECORE_ACCEPT_BROADCAST, rx_accept_flags);
1451 /* internal switching mode */
1452 bnx2x_set_bit(ECORE_ACCEPT_ALL_MULTICAST, tx_accept_flags);
1453 bnx2x_set_bit(ECORE_ACCEPT_BROADCAST, tx_accept_flags);
1456 bnx2x_set_bit(ECORE_ACCEPT_ALL_UNICAST, tx_accept_flags);
1458 bnx2x_set_bit(ECORE_ACCEPT_UNICAST, tx_accept_flags);
1464 PMD_RX_LOG(ERR, "Unknown rx_mode (%d)", rx_mode);
1468 /* Set ACCEPT_ANY_VLAN as we do not enable filtering by VLAN */
1469 if (rx_mode != BNX2X_RX_MODE_NONE) {
1470 bnx2x_set_bit(ECORE_ACCEPT_ANY_VLAN, rx_accept_flags);
1471 bnx2x_set_bit(ECORE_ACCEPT_ANY_VLAN, tx_accept_flags);
1478 bnx2x_set_q_rx_mode(struct bnx2x_softc *sc, uint8_t cl_id,
1479 unsigned long rx_mode_flags,
1480 unsigned long rx_accept_flags,
1481 unsigned long tx_accept_flags, unsigned long ramrod_flags)
1483 struct ecore_rx_mode_ramrod_params ramrod_param;
1486 memset(&ramrod_param, 0, sizeof(ramrod_param));
1488 /* Prepare ramrod parameters */
1489 ramrod_param.cid = 0;
1490 ramrod_param.cl_id = cl_id;
1491 ramrod_param.rx_mode_obj = &sc->rx_mode_obj;
1492 ramrod_param.func_id = SC_FUNC(sc);
1494 ramrod_param.pstate = &sc->sp_state;
1495 ramrod_param.state = ECORE_FILTER_RX_MODE_PENDING;
1497 ramrod_param.rdata = BNX2X_SP(sc, rx_mode_rdata);
1498 ramrod_param.rdata_mapping =
1499 (phys_addr_t)BNX2X_SP_MAPPING(sc, rx_mode_rdata),
1500 bnx2x_set_bit(ECORE_FILTER_RX_MODE_PENDING, &sc->sp_state);
1502 ramrod_param.ramrod_flags = ramrod_flags;
1503 ramrod_param.rx_mode_flags = rx_mode_flags;
1505 ramrod_param.rx_accept_flags = rx_accept_flags;
1506 ramrod_param.tx_accept_flags = tx_accept_flags;
1508 rc = ecore_config_rx_mode(sc, &ramrod_param);
1510 PMD_RX_LOG(ERR, "Set rx_mode %d failed", sc->rx_mode);
1517 int bnx2x_set_storm_rx_mode(struct bnx2x_softc *sc)
1519 unsigned long rx_mode_flags = 0, ramrod_flags = 0;
1520 unsigned long rx_accept_flags = 0, tx_accept_flags = 0;
1523 rc = bnx2x_fill_accept_flags(sc, sc->rx_mode, &rx_accept_flags,
1529 bnx2x_set_bit(RAMROD_RX, &ramrod_flags);
1530 bnx2x_set_bit(RAMROD_TX, &ramrod_flags);
1531 bnx2x_set_bit(RAMROD_COMP_WAIT, &ramrod_flags);
1533 return bnx2x_set_q_rx_mode(sc, sc->fp[0].cl_id, rx_mode_flags,
1534 rx_accept_flags, tx_accept_flags,
1538 /* returns the "mcp load_code" according to global load_count array */
1539 static int bnx2x_nic_load_no_mcp(struct bnx2x_softc *sc)
1541 int path = SC_PATH(sc);
1542 int port = SC_PORT(sc);
1544 PMD_DRV_LOG(INFO, "NO MCP - load counts[%d] %d, %d, %d",
1545 path, load_count[path][0], load_count[path][1],
1546 load_count[path][2]);
1548 load_count[path][0]++;
1549 load_count[path][1 + port]++;
1550 PMD_DRV_LOG(INFO, "NO MCP - new load counts[%d] %d, %d, %d",
1551 path, load_count[path][0], load_count[path][1],
1552 load_count[path][2]);
1553 if (load_count[path][0] == 1)
1554 return FW_MSG_CODE_DRV_LOAD_COMMON;
1555 else if (load_count[path][1 + port] == 1)
1556 return FW_MSG_CODE_DRV_LOAD_PORT;
1558 return FW_MSG_CODE_DRV_LOAD_FUNCTION;
1561 /* returns the "mcp load_code" according to global load_count array */
1562 static int bnx2x_nic_unload_no_mcp(struct bnx2x_softc *sc)
1564 int port = SC_PORT(sc);
1565 int path = SC_PATH(sc);
1567 PMD_DRV_LOG(INFO, "NO MCP - load counts[%d] %d, %d, %d",
1568 path, load_count[path][0], load_count[path][1],
1569 load_count[path][2]);
1570 load_count[path][0]--;
1571 load_count[path][1 + port]--;
1572 PMD_DRV_LOG(INFO, "NO MCP - new load counts[%d] %d, %d, %d",
1573 path, load_count[path][0], load_count[path][1],
1574 load_count[path][2]);
1575 if (load_count[path][0] == 0) {
1576 return FW_MSG_CODE_DRV_UNLOAD_COMMON;
1577 } else if (load_count[path][1 + port] == 0) {
1578 return FW_MSG_CODE_DRV_UNLOAD_PORT;
1580 return FW_MSG_CODE_DRV_UNLOAD_FUNCTION;
1584 /* request unload mode from the MCP: COMMON, PORT or FUNCTION */
1585 static uint32_t bnx2x_send_unload_req(struct bnx2x_softc *sc, int unload_mode)
1587 uint32_t reset_code = 0;
1589 /* Select the UNLOAD request mode */
1590 if (unload_mode == UNLOAD_NORMAL) {
1591 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS;
1593 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS;
1596 /* Send the request to the MCP */
1597 if (!BNX2X_NOMCP(sc)) {
1598 reset_code = bnx2x_fw_command(sc, reset_code, 0);
1600 reset_code = bnx2x_nic_unload_no_mcp(sc);
1606 /* send UNLOAD_DONE command to the MCP */
1607 static void bnx2x_send_unload_done(struct bnx2x_softc *sc, uint8_t keep_link)
1609 uint32_t reset_param =
1610 keep_link ? DRV_MSG_CODE_UNLOAD_SKIP_LINK_RESET : 0;
1612 /* Report UNLOAD_DONE to MCP */
1613 if (!BNX2X_NOMCP(sc)) {
1614 bnx2x_fw_command(sc, DRV_MSG_CODE_UNLOAD_DONE, reset_param);
1618 static int bnx2x_func_wait_started(struct bnx2x_softc *sc)
1622 if (!sc->port.pmf) {
1627 * (assumption: No Attention from MCP at this stage)
1628 * PMF probably in the middle of TX disable/enable transaction
1629 * 1. Sync IRS for default SB
1630 * 2. Sync SP queue - this guarantees us that attention handling started
1631 * 3. Wait, that TX disable/enable transaction completes
1633 * 1+2 guarantee that if DCBX attention was scheduled it already changed
1634 * pending bit of transaction from STARTED-->TX_STOPPED, if we already
1635 * received completion for the transaction the state is TX_STOPPED.
1636 * State will return to STARTED after completion of TX_STOPPED-->STARTED
1640 while (ecore_func_get_state(sc, &sc->func_obj) !=
1641 ECORE_F_STATE_STARTED && tout--) {
1645 if (ecore_func_get_state(sc, &sc->func_obj) != ECORE_F_STATE_STARTED) {
1647 * Failed to complete the transaction in a "good way"
1648 * Force both transactions with CLR bit.
1650 struct ecore_func_state_params func_params = { NULL };
1652 PMD_DRV_LOG(NOTICE, "Unexpected function state! "
1653 "Forcing STARTED-->TX_STOPPED-->STARTED");
1655 func_params.f_obj = &sc->func_obj;
1656 bnx2x_set_bit(RAMROD_DRV_CLR_ONLY, &func_params.ramrod_flags);
1658 /* STARTED-->TX_STOPPED */
1659 func_params.cmd = ECORE_F_CMD_TX_STOP;
1660 ecore_func_state_change(sc, &func_params);
1662 /* TX_STOPPED-->STARTED */
1663 func_params.cmd = ECORE_F_CMD_TX_START;
1664 return ecore_func_state_change(sc, &func_params);
1670 static int bnx2x_stop_queue(struct bnx2x_softc *sc, int index)
1672 struct bnx2x_fastpath *fp = &sc->fp[index];
1673 struct ecore_queue_state_params q_params = { NULL };
1676 PMD_DRV_LOG(DEBUG, "stopping queue %d cid %d", index, fp->index);
1678 q_params.q_obj = &sc->sp_objs[fp->index].q_obj;
1679 /* We want to wait for completion in this context */
1680 bnx2x_set_bit(RAMROD_COMP_WAIT, &q_params.ramrod_flags);
1682 /* Stop the primary connection: */
1684 /* ...halt the connection */
1685 q_params.cmd = ECORE_Q_CMD_HALT;
1686 rc = ecore_queue_state_change(sc, &q_params);
1691 /* ...terminate the connection */
1692 q_params.cmd = ECORE_Q_CMD_TERMINATE;
1693 memset(&q_params.params.terminate, 0,
1694 sizeof(q_params.params.terminate));
1695 q_params.params.terminate.cid_index = FIRST_TX_COS_INDEX;
1696 rc = ecore_queue_state_change(sc, &q_params);
1701 /* ...delete cfc entry */
1702 q_params.cmd = ECORE_Q_CMD_CFC_DEL;
1703 memset(&q_params.params.cfc_del, 0, sizeof(q_params.params.cfc_del));
1704 q_params.params.cfc_del.cid_index = FIRST_TX_COS_INDEX;
1705 return ecore_queue_state_change(sc, &q_params);
1708 /* wait for the outstanding SP commands */
1709 static uint8_t bnx2x_wait_sp_comp(struct bnx2x_softc *sc, unsigned long mask)
1712 int tout = 5000; /* wait for 5 secs tops */
1716 if (!(atomic_load_acq_long(&sc->sp_state) & mask)) {
1725 tmp = atomic_load_acq_long(&sc->sp_state);
1727 PMD_DRV_LOG(INFO, "Filtering completion timed out: "
1728 "sp_state 0x%lx, mask 0x%lx", tmp, mask);
1735 static int bnx2x_func_stop(struct bnx2x_softc *sc)
1737 struct ecore_func_state_params func_params = { NULL };
1740 /* prepare parameters for function state transitions */
1741 bnx2x_set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags);
1742 func_params.f_obj = &sc->func_obj;
1743 func_params.cmd = ECORE_F_CMD_STOP;
1746 * Try to stop the function the 'good way'. If it fails (in case
1747 * of a parity error during bnx2x_chip_cleanup()) and we are
1748 * not in a debug mode, perform a state transaction in order to
1749 * enable further HW_RESET transaction.
1751 rc = ecore_func_state_change(sc, &func_params);
1753 PMD_DRV_LOG(NOTICE, "FUNC_STOP ramrod failed. "
1754 "Running a dry transaction");
1755 bnx2x_set_bit(RAMROD_DRV_CLR_ONLY, &func_params.ramrod_flags);
1756 return ecore_func_state_change(sc, &func_params);
1762 static int bnx2x_reset_hw(struct bnx2x_softc *sc, uint32_t load_code)
1764 struct ecore_func_state_params func_params = { NULL };
1766 /* Prepare parameters for function state transitions */
1767 bnx2x_set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags);
1769 func_params.f_obj = &sc->func_obj;
1770 func_params.cmd = ECORE_F_CMD_HW_RESET;
1772 func_params.params.hw_init.load_phase = load_code;
1774 return ecore_func_state_change(sc, &func_params);
1777 static void bnx2x_int_disable_sync(struct bnx2x_softc *sc, int disable_hw)
1780 /* prevent the HW from sending interrupts */
1781 bnx2x_int_disable(sc);
1786 bnx2x_chip_cleanup(struct bnx2x_softc *sc, uint32_t unload_mode, uint8_t keep_link)
1788 int port = SC_PORT(sc);
1789 struct ecore_mcast_ramrod_params rparam = { NULL };
1790 uint32_t reset_code;
1793 bnx2x_drain_tx_queues(sc);
1795 /* give HW time to discard old tx messages */
1798 /* Clean all ETH MACs */
1799 rc = bnx2x_del_all_macs(sc, &sc->sp_objs[0].mac_obj, ECORE_ETH_MAC,
1802 PMD_DRV_LOG(NOTICE, "Failed to delete all ETH MACs (%d)", rc);
1805 /* Clean up UC list */
1806 rc = bnx2x_del_all_macs(sc, &sc->sp_objs[0].mac_obj, ECORE_UC_LIST_MAC,
1809 PMD_DRV_LOG(NOTICE, "Failed to delete UC MACs list (%d)", rc);
1813 REG_WR(sc, NIG_REG_LLH0_FUNC_EN + port * 8, 0);
1815 /* Set "drop all" to stop Rx */
1818 * We need to take the if_maddr_lock() here in order to prevent
1819 * a race between the completion code and this code.
1822 if (bnx2x_test_bit(ECORE_FILTER_RX_MODE_PENDING, &sc->sp_state)) {
1823 bnx2x_set_bit(ECORE_FILTER_RX_MODE_SCHED, &sc->sp_state);
1825 bnx2x_set_storm_rx_mode(sc);
1828 /* Clean up multicast configuration */
1829 rparam.mcast_obj = &sc->mcast_obj;
1830 rc = ecore_config_mcast(sc, &rparam, ECORE_MCAST_CMD_DEL);
1833 "Failed to send DEL MCAST command (%d)", rc);
1837 * Send the UNLOAD_REQUEST to the MCP. This will return if
1838 * this function should perform FUNCTION, PORT, or COMMON HW
1841 reset_code = bnx2x_send_unload_req(sc, unload_mode);
1844 * (assumption: No Attention from MCP at this stage)
1845 * PMF probably in the middle of TX disable/enable transaction
1847 rc = bnx2x_func_wait_started(sc);
1849 PMD_DRV_LOG(NOTICE, "bnx2x_func_wait_started failed");
1853 * Close multi and leading connections
1854 * Completions for ramrods are collected in a synchronous way
1856 for (i = 0; i < sc->num_queues; i++) {
1857 if (bnx2x_stop_queue(sc, i)) {
1863 * If SP settings didn't get completed so far - something
1864 * very wrong has happen.
1866 if (!bnx2x_wait_sp_comp(sc, ~0x0UL)) {
1867 PMD_DRV_LOG(NOTICE, "Common slow path ramrods got stuck!");
1872 rc = bnx2x_func_stop(sc);
1874 PMD_DRV_LOG(NOTICE, "Function stop failed!");
1877 /* disable HW interrupts */
1878 bnx2x_int_disable_sync(sc, TRUE);
1880 /* Reset the chip */
1881 rc = bnx2x_reset_hw(sc, reset_code);
1883 PMD_DRV_LOG(NOTICE, "Hardware reset failed");
1886 /* Report UNLOAD_DONE to MCP */
1887 bnx2x_send_unload_done(sc, keep_link);
1890 static void bnx2x_disable_close_the_gate(struct bnx2x_softc *sc)
1894 PMD_DRV_LOG(DEBUG, "Disabling 'close the gates'");
1896 val = REG_RD(sc, MISC_REG_AEU_GENERAL_MASK);
1897 val &= ~(MISC_AEU_GENERAL_MASK_REG_AEU_PXP_CLOSE_MASK |
1898 MISC_AEU_GENERAL_MASK_REG_AEU_NIG_CLOSE_MASK);
1899 REG_WR(sc, MISC_REG_AEU_GENERAL_MASK, val);
1903 * Cleans the object that have internal lists without sending
1904 * ramrods. Should be run when interrutps are disabled.
1906 static void bnx2x_squeeze_objects(struct bnx2x_softc *sc)
1908 unsigned long ramrod_flags = 0, vlan_mac_flags = 0;
1909 struct ecore_mcast_ramrod_params rparam = { NULL };
1910 struct ecore_vlan_mac_obj *mac_obj = &sc->sp_objs->mac_obj;
1913 /* Cleanup MACs' object first... */
1915 /* Wait for completion of requested */
1916 bnx2x_set_bit(RAMROD_COMP_WAIT, &ramrod_flags);
1917 /* Perform a dry cleanup */
1918 bnx2x_set_bit(RAMROD_DRV_CLR_ONLY, &ramrod_flags);
1920 /* Clean ETH primary MAC */
1921 bnx2x_set_bit(ECORE_ETH_MAC, &vlan_mac_flags);
1922 rc = mac_obj->delete_all(sc, &sc->sp_objs->mac_obj, &vlan_mac_flags,
1925 PMD_DRV_LOG(NOTICE, "Failed to clean ETH MACs (%d)", rc);
1928 /* Cleanup UC list */
1930 bnx2x_set_bit(ECORE_UC_LIST_MAC, &vlan_mac_flags);
1931 rc = mac_obj->delete_all(sc, mac_obj, &vlan_mac_flags, &ramrod_flags);
1933 PMD_DRV_LOG(NOTICE, "Failed to clean UC list MACs (%d)", rc);
1936 /* Now clean mcast object... */
1938 rparam.mcast_obj = &sc->mcast_obj;
1939 bnx2x_set_bit(RAMROD_DRV_CLR_ONLY, &rparam.ramrod_flags);
1941 /* Add a DEL command... */
1942 rc = ecore_config_mcast(sc, &rparam, ECORE_MCAST_CMD_DEL);
1945 "Failed to send DEL MCAST command (%d)", rc);
1948 /* now wait until all pending commands are cleared */
1950 rc = ecore_config_mcast(sc, &rparam, ECORE_MCAST_CMD_CONT);
1954 "Failed to clean MCAST object (%d)", rc);
1958 rc = ecore_config_mcast(sc, &rparam, ECORE_MCAST_CMD_CONT);
1962 /* stop the controller */
1963 __attribute__ ((noinline))
1965 bnx2x_nic_unload(struct bnx2x_softc *sc, uint32_t unload_mode, uint8_t keep_link)
1967 uint8_t global = FALSE;
1970 PMD_DRV_LOG(DEBUG, "Starting NIC unload...");
1972 /* stop the periodic callout */
1973 bnx2x_periodic_stop(sc);
1975 /* mark driver as unloaded in shmem2 */
1976 if (IS_PF(sc) && SHMEM2_HAS(sc, drv_capabilities_flag)) {
1977 val = SHMEM2_RD(sc, drv_capabilities_flag[SC_FW_MB_IDX(sc)]);
1978 SHMEM2_WR(sc, drv_capabilities_flag[SC_FW_MB_IDX(sc)],
1979 val & ~DRV_FLAGS_CAPABILITIES_LOADED_L2);
1982 if (IS_PF(sc) && sc->recovery_state != BNX2X_RECOVERY_DONE &&
1983 (sc->state == BNX2X_STATE_CLOSED || sc->state == BNX2X_STATE_ERROR)) {
1985 * We can get here if the driver has been unloaded
1986 * during parity error recovery and is either waiting for a
1987 * leader to complete or for other functions to unload and
1988 * then ifconfig down has been issued. In this case we want to
1989 * unload and let other functions to complete a recovery
1992 sc->recovery_state = BNX2X_RECOVERY_DONE;
1994 bnx2x_release_leader_lock(sc);
1997 PMD_DRV_LOG(NOTICE, "Can't unload in closed or error state");
2002 * Nothing to do during unload if previous bnx2x_nic_load()
2003 * did not completed succesfully - all resourses are released.
2005 if ((sc->state == BNX2X_STATE_CLOSED) || (sc->state == BNX2X_STATE_ERROR)) {
2009 sc->state = BNX2X_STATE_CLOSING_WAITING_HALT;
2012 sc->rx_mode = BNX2X_RX_MODE_NONE;
2013 bnx2x_set_rx_mode(sc);
2017 /* set ALWAYS_ALIVE bit in shmem */
2018 sc->fw_drv_pulse_wr_seq |= DRV_PULSE_ALWAYS_ALIVE;
2020 bnx2x_drv_pulse(sc);
2022 bnx2x_stats_handle(sc, STATS_EVENT_STOP);
2023 bnx2x_save_statistics(sc);
2026 /* wait till consumers catch up with producers in all queues */
2027 bnx2x_drain_tx_queues(sc);
2029 /* if VF indicate to PF this function is going down (PF will delete sp
2030 * elements and clear initializations
2033 bnx2x_vf_unload(sc);
2034 } else if (unload_mode != UNLOAD_RECOVERY) {
2035 /* if this is a normal/close unload need to clean up chip */
2036 bnx2x_chip_cleanup(sc, unload_mode, keep_link);
2038 /* Send the UNLOAD_REQUEST to the MCP */
2039 bnx2x_send_unload_req(sc, unload_mode);
2042 * Prevent transactions to host from the functions on the
2043 * engine that doesn't reset global blocks in case of global
2044 * attention once gloabl blocks are reset and gates are opened
2045 * (the engine which leader will perform the recovery
2048 if (!CHIP_IS_E1x(sc)) {
2049 bnx2x_pf_disable(sc);
2052 /* disable HW interrupts */
2053 bnx2x_int_disable_sync(sc, TRUE);
2055 /* Report UNLOAD_DONE to MCP */
2056 bnx2x_send_unload_done(sc, FALSE);
2060 * At this stage no more interrupts will arrive so we may safely clean
2061 * the queue'able objects here in case they failed to get cleaned so far.
2064 bnx2x_squeeze_objects(sc);
2067 /* There should be no more pending SP commands at this stage */
2076 bnx2x_free_fw_stats_mem(sc);
2078 sc->state = BNX2X_STATE_CLOSED;
2081 * Check if there are pending parity attentions. If there are - set
2082 * RECOVERY_IN_PROGRESS.
2084 if (IS_PF(sc) && bnx2x_chk_parity_attn(sc, &global, FALSE)) {
2085 bnx2x_set_reset_in_progress(sc);
2087 /* Set RESET_IS_GLOBAL if needed */
2089 bnx2x_set_reset_global(sc);
2094 * The last driver must disable a "close the gate" if there is no
2095 * parity attention or "process kill" pending.
2097 if (IS_PF(sc) && !bnx2x_clear_pf_load(sc) &&
2098 bnx2x_reset_is_done(sc, SC_PATH(sc))) {
2099 bnx2x_disable_close_the_gate(sc);
2102 PMD_DRV_LOG(DEBUG, "Ended NIC unload");
2108 * Encapsulte an mbuf cluster into the tx bd chain and makes the memory
2109 * visible to the controller.
2111 * If an mbuf is submitted to this routine and cannot be given to the
2112 * controller (e.g. it has too many fragments) then the function may free
2113 * the mbuf and return to the caller.
2116 * 0 = Success, !0 = Failure
2117 * Note the side effect that an mbuf may be freed if it causes a problem.
2119 int bnx2x_tx_encap(struct bnx2x_tx_queue *txq, struct rte_mbuf **m_head, int m_pkts)
2121 struct rte_mbuf *m0;
2122 struct eth_tx_start_bd *tx_start_bd;
2123 uint16_t bd_prod, pkt_prod;
2125 struct bnx2x_softc *sc;
2127 struct bnx2x_fastpath *fp;
2130 fp = &sc->fp[txq->queue_id];
2132 bd_prod = txq->tx_bd_tail;
2133 pkt_prod = txq->tx_pkt_tail;
2135 for (m_tx = 0; m_tx < m_pkts; m_tx++) {
2139 if (unlikely(txq->nb_tx_avail < 3)) {
2140 PMD_TX_LOG(ERR, "no enough bds %d/%d",
2141 bd_prod, txq->nb_tx_avail);
2145 txq->sw_ring[TX_BD(pkt_prod, txq)] = m0;
2147 tx_start_bd = &txq->tx_ring[TX_BD(bd_prod, txq)].start_bd;
2150 rte_cpu_to_le_64(RTE_MBUF_DATA_DMA_ADDR(m0));
2151 tx_start_bd->nbytes = rte_cpu_to_le_16(m0->data_len);
2152 tx_start_bd->bd_flags.as_bitfield = ETH_TX_BD_FLAGS_START_BD;
2153 tx_start_bd->general_data =
2154 (1 << ETH_TX_START_BD_HDR_NBDS_SHIFT);
2156 tx_start_bd->nbd = rte_cpu_to_le_16(2);
2158 if (m0->ol_flags & PKT_TX_VLAN_PKT) {
2159 tx_start_bd->vlan_or_ethertype =
2160 rte_cpu_to_le_16(m0->vlan_tci);
2161 tx_start_bd->bd_flags.as_bitfield |=
2162 (X_ETH_OUTBAND_VLAN <<
2163 ETH_TX_BD_FLAGS_VLAN_MODE_SHIFT);
2166 tx_start_bd->vlan_or_ethertype =
2167 rte_cpu_to_le_16(pkt_prod);
2169 struct ether_hdr *eh
2170 = rte_pktmbuf_mtod(m0, struct ether_hdr *);
2172 tx_start_bd->vlan_or_ethertype
2173 = rte_cpu_to_le_16(rte_be_to_cpu_16(eh->ether_type));
2177 bd_prod = NEXT_TX_BD(bd_prod);
2179 struct eth_tx_parse_bd_e2 *tx_parse_bd;
2180 const struct ether_hdr *eh = rte_pktmbuf_mtod(m0, struct ether_hdr *);
2181 uint8_t mac_type = UNICAST_ADDRESS;
2184 &txq->tx_ring[TX_BD(bd_prod, txq)].parse_bd_e2;
2185 if (is_multicast_ether_addr(&eh->d_addr)) {
2186 if (is_broadcast_ether_addr(&eh->d_addr))
2187 mac_type = BROADCAST_ADDRESS;
2189 mac_type = MULTICAST_ADDRESS;
2191 tx_parse_bd->parsing_data =
2192 (mac_type << ETH_TX_PARSE_BD_E2_ETH_ADDR_TYPE_SHIFT);
2194 rte_memcpy(&tx_parse_bd->data.mac_addr.dst_hi,
2195 &eh->d_addr.addr_bytes[0], 2);
2196 rte_memcpy(&tx_parse_bd->data.mac_addr.dst_mid,
2197 &eh->d_addr.addr_bytes[2], 2);
2198 rte_memcpy(&tx_parse_bd->data.mac_addr.dst_lo,
2199 &eh->d_addr.addr_bytes[4], 2);
2200 rte_memcpy(&tx_parse_bd->data.mac_addr.src_hi,
2201 &eh->s_addr.addr_bytes[0], 2);
2202 rte_memcpy(&tx_parse_bd->data.mac_addr.src_mid,
2203 &eh->s_addr.addr_bytes[2], 2);
2204 rte_memcpy(&tx_parse_bd->data.mac_addr.src_lo,
2205 &eh->s_addr.addr_bytes[4], 2);
2207 tx_parse_bd->data.mac_addr.dst_hi =
2208 rte_cpu_to_be_16(tx_parse_bd->data.mac_addr.dst_hi);
2209 tx_parse_bd->data.mac_addr.dst_mid =
2210 rte_cpu_to_be_16(tx_parse_bd->data.
2212 tx_parse_bd->data.mac_addr.dst_lo =
2213 rte_cpu_to_be_16(tx_parse_bd->data.mac_addr.dst_lo);
2214 tx_parse_bd->data.mac_addr.src_hi =
2215 rte_cpu_to_be_16(tx_parse_bd->data.mac_addr.src_hi);
2216 tx_parse_bd->data.mac_addr.src_mid =
2217 rte_cpu_to_be_16(tx_parse_bd->data.
2219 tx_parse_bd->data.mac_addr.src_lo =
2220 rte_cpu_to_be_16(tx_parse_bd->data.mac_addr.src_lo);
2223 "PBD dst %x %x %x src %x %x %x p_data %x",
2224 tx_parse_bd->data.mac_addr.dst_hi,
2225 tx_parse_bd->data.mac_addr.dst_mid,
2226 tx_parse_bd->data.mac_addr.dst_lo,
2227 tx_parse_bd->data.mac_addr.src_hi,
2228 tx_parse_bd->data.mac_addr.src_mid,
2229 tx_parse_bd->data.mac_addr.src_lo,
2230 tx_parse_bd->parsing_data);
2234 "start bd: nbytes %d flags %x vlan %x\n",
2235 tx_start_bd->nbytes,
2236 tx_start_bd->bd_flags.as_bitfield,
2237 tx_start_bd->vlan_or_ethertype);
2239 bd_prod = NEXT_TX_BD(bd_prod);
2242 if (TX_IDX(bd_prod) < 2) {
2247 txq->nb_tx_avail -= m_pkts << 1;
2248 txq->tx_bd_tail = bd_prod;
2249 txq->tx_pkt_tail = pkt_prod;
2252 fp->tx_db.data.prod += (m_pkts << 1) + nbds;
2253 DOORBELL(sc, txq->queue_id, fp->tx_db.raw);
2259 static uint16_t bnx2x_cid_ilt_lines(struct bnx2x_softc *sc)
2261 return L2_ILT_LINES(sc);
2264 static void bnx2x_ilt_set_info(struct bnx2x_softc *sc)
2266 struct ilt_client_info *ilt_client;
2267 struct ecore_ilt *ilt = sc->ilt;
2270 PMD_INIT_FUNC_TRACE();
2272 ilt->start_line = FUNC_ILT_BASE(SC_FUNC(sc));
2275 ilt_client = &ilt->clients[ILT_CLIENT_CDU];
2276 ilt_client->client_num = ILT_CLIENT_CDU;
2277 ilt_client->page_size = CDU_ILT_PAGE_SZ;
2278 ilt_client->flags = ILT_CLIENT_SKIP_MEM;
2279 ilt_client->start = line;
2280 line += bnx2x_cid_ilt_lines(sc);
2282 if (CNIC_SUPPORT(sc)) {
2283 line += CNIC_ILT_LINES;
2286 ilt_client->end = (line - 1);
2289 if (QM_INIT(sc->qm_cid_count)) {
2290 ilt_client = &ilt->clients[ILT_CLIENT_QM];
2291 ilt_client->client_num = ILT_CLIENT_QM;
2292 ilt_client->page_size = QM_ILT_PAGE_SZ;
2293 ilt_client->flags = 0;
2294 ilt_client->start = line;
2296 /* 4 bytes for each cid */
2297 line += DIV_ROUND_UP(sc->qm_cid_count * QM_QUEUES_PER_FUNC * 4,
2300 ilt_client->end = (line - 1);
2303 if (CNIC_SUPPORT(sc)) {
2305 ilt_client = &ilt->clients[ILT_CLIENT_SRC];
2306 ilt_client->client_num = ILT_CLIENT_SRC;
2307 ilt_client->page_size = SRC_ILT_PAGE_SZ;
2308 ilt_client->flags = 0;
2309 ilt_client->start = line;
2310 line += SRC_ILT_LINES;
2311 ilt_client->end = (line - 1);
2314 ilt_client = &ilt->clients[ILT_CLIENT_TM];
2315 ilt_client->client_num = ILT_CLIENT_TM;
2316 ilt_client->page_size = TM_ILT_PAGE_SZ;
2317 ilt_client->flags = 0;
2318 ilt_client->start = line;
2319 line += TM_ILT_LINES;
2320 ilt_client->end = (line - 1);
2323 assert((line <= ILT_MAX_LINES));
2326 static void bnx2x_set_fp_rx_buf_size(struct bnx2x_softc *sc)
2330 for (i = 0; i < sc->num_queues; i++) {
2331 /* get the Rx buffer size for RX frames */
2332 sc->fp[i].rx_buf_size =
2333 (IP_HEADER_ALIGNMENT_PADDING + ETH_OVERHEAD + sc->mtu);
2335 /* get the mbuf allocation size for RX frames */
2336 if (sc->fp[i].rx_buf_size <= MCLBYTES) {
2337 sc->fp[i].mbuf_alloc_size = MCLBYTES;
2338 } else if (sc->fp[i].rx_buf_size <= BNX2X_PAGE_SIZE) {
2339 sc->fp[i].mbuf_alloc_size = PAGE_SIZE;
2341 sc->fp[i].mbuf_alloc_size = MJUM9BYTES;
2346 int bnx2x_alloc_ilt_mem(struct bnx2x_softc *sc)
2349 sc->ilt = rte_malloc("", sizeof(struct ecore_ilt), RTE_CACHE_LINE_SIZE);
2351 return sc->ilt == NULL;
2354 static int bnx2x_alloc_ilt_lines_mem(struct bnx2x_softc *sc)
2356 sc->ilt->lines = rte_calloc("",
2357 sizeof(struct ilt_line), ILT_MAX_LINES,
2358 RTE_CACHE_LINE_SIZE);
2359 return sc->ilt->lines == NULL;
2362 void bnx2x_free_ilt_mem(struct bnx2x_softc *sc)
2368 static void bnx2x_free_ilt_lines_mem(struct bnx2x_softc *sc)
2370 if (sc->ilt->lines != NULL) {
2371 rte_free(sc->ilt->lines);
2372 sc->ilt->lines = NULL;
2376 static void bnx2x_free_mem(struct bnx2x_softc *sc)
2380 for (i = 0; i < L2_ILT_LINES(sc); i++) {
2381 sc->context[i].vcxt = NULL;
2382 sc->context[i].size = 0;
2385 ecore_ilt_mem_op(sc, ILT_MEMOP_FREE);
2387 bnx2x_free_ilt_lines_mem(sc);
2390 static int bnx2x_alloc_mem(struct bnx2x_softc *sc)
2395 char cdu_name[RTE_MEMZONE_NAMESIZE];
2398 * Allocate memory for CDU context:
2399 * This memory is allocated separately and not in the generic ILT
2400 * functions because CDU differs in few aspects:
2401 * 1. There can be multiple entities allocating memory for context -
2402 * regular L2, CNIC, and SRIOV drivers. Each separately controls
2403 * its own ILT lines.
2404 * 2. Since CDU page-size is not a single 4KB page (which is the case
2405 * for the other ILT clients), to be efficient we want to support
2406 * allocation of sub-page-size in the last entry.
2407 * 3. Context pointers are used by the driver to pass to FW / update
2408 * the context (for the other ILT clients the pointers are used just to
2409 * free the memory during unload).
2411 context_size = (sizeof(union cdu_context) * BNX2X_L2_CID_COUNT(sc));
2412 for (i = 0, allocated = 0; allocated < context_size; i++) {
2413 sc->context[i].size = min(CDU_ILT_PAGE_SZ,
2414 (context_size - allocated));
2416 snprintf(cdu_name, sizeof(cdu_name), "cdu_%d", i);
2417 if (bnx2x_dma_alloc(sc, sc->context[i].size,
2418 &sc->context[i].vcxt_dma,
2419 cdu_name, BNX2X_PAGE_SIZE) != 0) {
2424 sc->context[i].vcxt =
2425 (union cdu_context *)sc->context[i].vcxt_dma.vaddr;
2427 allocated += sc->context[i].size;
2430 bnx2x_alloc_ilt_lines_mem(sc);
2432 if (ecore_ilt_mem_op(sc, ILT_MEMOP_ALLOC)) {
2433 PMD_DRV_LOG(NOTICE, "ecore_ilt_mem_op ILT_MEMOP_ALLOC failed");
2441 static void bnx2x_free_fw_stats_mem(struct bnx2x_softc *sc)
2443 sc->fw_stats_num = 0;
2445 sc->fw_stats_req_size = 0;
2446 sc->fw_stats_req = NULL;
2447 sc->fw_stats_req_mapping = 0;
2449 sc->fw_stats_data_size = 0;
2450 sc->fw_stats_data = NULL;
2451 sc->fw_stats_data_mapping = 0;
2454 static int bnx2x_alloc_fw_stats_mem(struct bnx2x_softc *sc)
2456 uint8_t num_queue_stats;
2457 int num_groups, vf_headroom = 0;
2459 /* number of queues for statistics is number of eth queues */
2460 num_queue_stats = BNX2X_NUM_ETH_QUEUES(sc);
2463 * Total number of FW statistics requests =
2464 * 1 for port stats + 1 for PF stats + num of queues
2466 sc->fw_stats_num = (2 + num_queue_stats);
2469 * Request is built from stats_query_header and an array of
2470 * stats_query_cmd_group each of which contains STATS_QUERY_CMD_COUNT
2471 * rules. The real number or requests is configured in the
2472 * stats_query_header.
2474 num_groups = (sc->fw_stats_num + vf_headroom) / STATS_QUERY_CMD_COUNT;
2475 if ((sc->fw_stats_num + vf_headroom) % STATS_QUERY_CMD_COUNT)
2478 sc->fw_stats_req_size =
2479 (sizeof(struct stats_query_header) +
2480 (num_groups * sizeof(struct stats_query_cmd_group)));
2483 * Data for statistics requests + stats_counter.
2484 * stats_counter holds per-STORM counters that are incremented when
2485 * STORM has finished with the current request. Memory for FCoE
2486 * offloaded statistics are counted anyway, even if they will not be sent.
2487 * VF stats are not accounted for here as the data of VF stats is stored
2488 * in memory allocated by the VF, not here.
2490 sc->fw_stats_data_size =
2491 (sizeof(struct stats_counter) +
2492 sizeof(struct per_port_stats) + sizeof(struct per_pf_stats) +
2493 /* sizeof(struct fcoe_statistics_params) + */
2494 (sizeof(struct per_queue_stats) * num_queue_stats));
2496 if (bnx2x_dma_alloc(sc, (sc->fw_stats_req_size + sc->fw_stats_data_size),
2497 &sc->fw_stats_dma, "fw_stats",
2498 RTE_CACHE_LINE_SIZE) != 0) {
2499 bnx2x_free_fw_stats_mem(sc);
2503 /* set up the shortcuts */
2505 sc->fw_stats_req = (struct bnx2x_fw_stats_req *)sc->fw_stats_dma.vaddr;
2506 sc->fw_stats_req_mapping = sc->fw_stats_dma.paddr;
2509 (struct bnx2x_fw_stats_data *)((uint8_t *) sc->fw_stats_dma.vaddr +
2510 sc->fw_stats_req_size);
2511 sc->fw_stats_data_mapping = (sc->fw_stats_dma.paddr +
2512 sc->fw_stats_req_size);
2519 * 0-7 - Engine0 load counter.
2520 * 8-15 - Engine1 load counter.
2521 * 16 - Engine0 RESET_IN_PROGRESS bit.
2522 * 17 - Engine1 RESET_IN_PROGRESS bit.
2523 * 18 - Engine0 ONE_IS_LOADED. Set when there is at least one active
2524 * function on the engine
2525 * 19 - Engine1 ONE_IS_LOADED.
2526 * 20 - Chip reset flow bit. When set none-leader must wait for both engines
2527 * leader to complete (check for both RESET_IN_PROGRESS bits and not
2528 * for just the one belonging to its engine).
2530 #define BNX2X_RECOVERY_GLOB_REG MISC_REG_GENERIC_POR_1
2531 #define BNX2X_PATH0_LOAD_CNT_MASK 0x000000ff
2532 #define BNX2X_PATH0_LOAD_CNT_SHIFT 0
2533 #define BNX2X_PATH1_LOAD_CNT_MASK 0x0000ff00
2534 #define BNX2X_PATH1_LOAD_CNT_SHIFT 8
2535 #define BNX2X_PATH0_RST_IN_PROG_BIT 0x00010000
2536 #define BNX2X_PATH1_RST_IN_PROG_BIT 0x00020000
2537 #define BNX2X_GLOBAL_RESET_BIT 0x00040000
2539 /* set the GLOBAL_RESET bit, should be run under rtnl lock */
2540 static void bnx2x_set_reset_global(struct bnx2x_softc *sc)
2543 bnx2x_acquire_hw_lock(sc, HW_LOCK_RESOURCE_RECOVERY_REG);
2544 val = REG_RD(sc, BNX2X_RECOVERY_GLOB_REG);
2545 REG_WR(sc, BNX2X_RECOVERY_GLOB_REG, val | BNX2X_GLOBAL_RESET_BIT);
2546 bnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_RECOVERY_REG);
2549 /* clear the GLOBAL_RESET bit, should be run under rtnl lock */
2550 static void bnx2x_clear_reset_global(struct bnx2x_softc *sc)
2553 bnx2x_acquire_hw_lock(sc, HW_LOCK_RESOURCE_RECOVERY_REG);
2554 val = REG_RD(sc, BNX2X_RECOVERY_GLOB_REG);
2555 REG_WR(sc, BNX2X_RECOVERY_GLOB_REG, val & (~BNX2X_GLOBAL_RESET_BIT));
2556 bnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_RECOVERY_REG);
2559 /* checks the GLOBAL_RESET bit, should be run under rtnl lock */
2560 static uint8_t bnx2x_reset_is_global(struct bnx2x_softc *sc)
2562 return (REG_RD(sc, BNX2X_RECOVERY_GLOB_REG) & BNX2X_GLOBAL_RESET_BIT);
2565 /* clear RESET_IN_PROGRESS bit for the engine, should be run under rtnl lock */
2566 static void bnx2x_set_reset_done(struct bnx2x_softc *sc)
2569 uint32_t bit = SC_PATH(sc) ? BNX2X_PATH1_RST_IN_PROG_BIT :
2570 BNX2X_PATH0_RST_IN_PROG_BIT;
2572 bnx2x_acquire_hw_lock(sc, HW_LOCK_RESOURCE_RECOVERY_REG);
2574 val = REG_RD(sc, BNX2X_RECOVERY_GLOB_REG);
2577 REG_WR(sc, BNX2X_RECOVERY_GLOB_REG, val);
2579 bnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_RECOVERY_REG);
2582 /* set RESET_IN_PROGRESS for the engine, should be run under rtnl lock */
2583 static void bnx2x_set_reset_in_progress(struct bnx2x_softc *sc)
2586 uint32_t bit = SC_PATH(sc) ? BNX2X_PATH1_RST_IN_PROG_BIT :
2587 BNX2X_PATH0_RST_IN_PROG_BIT;
2589 bnx2x_acquire_hw_lock(sc, HW_LOCK_RESOURCE_RECOVERY_REG);
2591 val = REG_RD(sc, BNX2X_RECOVERY_GLOB_REG);
2594 REG_WR(sc, BNX2X_RECOVERY_GLOB_REG, val);
2596 bnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_RECOVERY_REG);
2599 /* check RESET_IN_PROGRESS bit for an engine, should be run under rtnl lock */
2600 static uint8_t bnx2x_reset_is_done(struct bnx2x_softc *sc, int engine)
2602 uint32_t val = REG_RD(sc, BNX2X_RECOVERY_GLOB_REG);
2603 uint32_t bit = engine ? BNX2X_PATH1_RST_IN_PROG_BIT :
2604 BNX2X_PATH0_RST_IN_PROG_BIT;
2606 /* return false if bit is set */
2607 return (val & bit) ? FALSE : TRUE;
2610 /* get the load status for an engine, should be run under rtnl lock */
2611 static uint8_t bnx2x_get_load_status(struct bnx2x_softc *sc, int engine)
2613 uint32_t mask = engine ? BNX2X_PATH1_LOAD_CNT_MASK :
2614 BNX2X_PATH0_LOAD_CNT_MASK;
2615 uint32_t shift = engine ? BNX2X_PATH1_LOAD_CNT_SHIFT :
2616 BNX2X_PATH0_LOAD_CNT_SHIFT;
2617 uint32_t val = REG_RD(sc, BNX2X_RECOVERY_GLOB_REG);
2619 val = ((val & mask) >> shift);
2624 /* set pf load mark */
2625 static void bnx2x_set_pf_load(struct bnx2x_softc *sc)
2629 uint32_t mask = SC_PATH(sc) ? BNX2X_PATH1_LOAD_CNT_MASK :
2630 BNX2X_PATH0_LOAD_CNT_MASK;
2631 uint32_t shift = SC_PATH(sc) ? BNX2X_PATH1_LOAD_CNT_SHIFT :
2632 BNX2X_PATH0_LOAD_CNT_SHIFT;
2634 bnx2x_acquire_hw_lock(sc, HW_LOCK_RESOURCE_RECOVERY_REG);
2636 PMD_INIT_FUNC_TRACE();
2638 val = REG_RD(sc, BNX2X_RECOVERY_GLOB_REG);
2640 /* get the current counter value */
2641 val1 = ((val & mask) >> shift);
2643 /* set bit of this PF */
2644 val1 |= (1 << SC_ABS_FUNC(sc));
2646 /* clear the old value */
2649 /* set the new one */
2650 val |= ((val1 << shift) & mask);
2652 REG_WR(sc, BNX2X_RECOVERY_GLOB_REG, val);
2654 bnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_RECOVERY_REG);
2657 /* clear pf load mark */
2658 static uint8_t bnx2x_clear_pf_load(struct bnx2x_softc *sc)
2661 uint32_t mask = SC_PATH(sc) ? BNX2X_PATH1_LOAD_CNT_MASK :
2662 BNX2X_PATH0_LOAD_CNT_MASK;
2663 uint32_t shift = SC_PATH(sc) ? BNX2X_PATH1_LOAD_CNT_SHIFT :
2664 BNX2X_PATH0_LOAD_CNT_SHIFT;
2666 bnx2x_acquire_hw_lock(sc, HW_LOCK_RESOURCE_RECOVERY_REG);
2667 val = REG_RD(sc, BNX2X_RECOVERY_GLOB_REG);
2669 /* get the current counter value */
2670 val1 = (val & mask) >> shift;
2672 /* clear bit of that PF */
2673 val1 &= ~(1 << SC_ABS_FUNC(sc));
2675 /* clear the old value */
2678 /* set the new one */
2679 val |= ((val1 << shift) & mask);
2681 REG_WR(sc, BNX2X_RECOVERY_GLOB_REG, val);
2682 bnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_RECOVERY_REG);
2686 /* send load requrest to mcp and analyze response */
2687 static int bnx2x_nic_load_request(struct bnx2x_softc *sc, uint32_t * load_code)
2689 PMD_INIT_FUNC_TRACE();
2693 (SHMEM_RD(sc, func_mb[SC_FW_MB_IDX(sc)].drv_mb_header) &
2694 DRV_MSG_SEQ_NUMBER_MASK);
2696 PMD_DRV_LOG(DEBUG, "initial fw_seq 0x%04x", sc->fw_seq);
2699 /* get the current FW pulse sequence */
2700 sc->fw_drv_pulse_wr_seq =
2701 (SHMEM_RD(sc, func_mb[SC_FW_MB_IDX(sc)].drv_pulse_mb) &
2702 DRV_PULSE_SEQ_MASK);
2704 /* set ALWAYS_ALIVE bit in shmem */
2705 sc->fw_drv_pulse_wr_seq |= DRV_PULSE_ALWAYS_ALIVE;
2706 bnx2x_drv_pulse(sc);
2710 (*load_code) = bnx2x_fw_command(sc, DRV_MSG_CODE_LOAD_REQ,
2711 DRV_MSG_CODE_LOAD_REQ_WITH_LFA);
2713 /* if the MCP fails to respond we must abort */
2714 if (!(*load_code)) {
2715 PMD_DRV_LOG(NOTICE, "MCP response failure!");
2719 /* if MCP refused then must abort */
2720 if ((*load_code) == FW_MSG_CODE_DRV_LOAD_REFUSED) {
2721 PMD_DRV_LOG(NOTICE, "MCP refused load request");
2729 * Check whether another PF has already loaded FW to chip. In virtualized
2730 * environments a pf from anoth VM may have already initialized the device
2731 * including loading FW.
2733 static int bnx2x_nic_load_analyze_req(struct bnx2x_softc *sc, uint32_t load_code)
2735 uint32_t my_fw, loaded_fw;
2737 /* is another pf loaded on this engine? */
2738 if ((load_code != FW_MSG_CODE_DRV_LOAD_COMMON_CHIP) &&
2739 (load_code != FW_MSG_CODE_DRV_LOAD_COMMON)) {
2740 /* build my FW version dword */
2741 my_fw = (BNX2X_5710_FW_MAJOR_VERSION +
2742 (BNX2X_5710_FW_MINOR_VERSION << 8) +
2743 (BNX2X_5710_FW_REVISION_VERSION << 16) +
2744 (BNX2X_5710_FW_ENGINEERING_VERSION << 24));
2746 /* read loaded FW from chip */
2747 loaded_fw = REG_RD(sc, XSEM_REG_PRAM);
2748 PMD_DRV_LOG(DEBUG, "loaded FW 0x%08x / my FW 0x%08x",
2751 /* abort nic load if version mismatch */
2752 if (my_fw != loaded_fw) {
2754 "FW 0x%08x already loaded (mine is 0x%08x)",
2763 /* mark PMF if applicable */
2764 static void bnx2x_nic_load_pmf(struct bnx2x_softc *sc, uint32_t load_code)
2766 uint32_t ncsi_oem_data_addr;
2768 PMD_INIT_FUNC_TRACE();
2770 if ((load_code == FW_MSG_CODE_DRV_LOAD_COMMON) ||
2771 (load_code == FW_MSG_CODE_DRV_LOAD_COMMON_CHIP) ||
2772 (load_code == FW_MSG_CODE_DRV_LOAD_PORT)) {
2774 * Barrier here for ordering between the writing to sc->port.pmf here
2775 * and reading it from the periodic task.
2783 PMD_DRV_LOG(DEBUG, "pmf %d", sc->port.pmf);
2785 if (load_code == FW_MSG_CODE_DRV_LOAD_COMMON_CHIP) {
2786 if (SHMEM2_HAS(sc, ncsi_oem_data_addr)) {
2787 ncsi_oem_data_addr = SHMEM2_RD(sc, ncsi_oem_data_addr);
2788 if (ncsi_oem_data_addr) {
2790 (ncsi_oem_data_addr +
2791 offsetof(struct glob_ncsi_oem_data,
2792 driver_version)), 0);
2798 static void bnx2x_read_mf_cfg(struct bnx2x_softc *sc)
2800 int n = (CHIP_IS_MODE_4_PORT(sc) ? 2 : 1);
2804 if (BNX2X_NOMCP(sc)) {
2805 return; /* what should be the default bvalue in this case */
2809 * The formula for computing the absolute function number is...
2810 * For 2 port configuration (4 functions per port):
2811 * abs_func = 2 * vn + SC_PORT + SC_PATH
2812 * For 4 port configuration (2 functions per port):
2813 * abs_func = 4 * vn + 2 * SC_PORT + SC_PATH
2815 for (vn = VN_0; vn < SC_MAX_VN_NUM(sc); vn++) {
2816 abs_func = (n * (2 * vn + SC_PORT(sc)) + SC_PATH(sc));
2817 if (abs_func >= E1H_FUNC_MAX) {
2820 sc->devinfo.mf_info.mf_config[vn] =
2821 MFCFG_RD(sc, func_mf_config[abs_func].config);
2824 if (sc->devinfo.mf_info.mf_config[SC_VN(sc)] &
2825 FUNC_MF_CFG_FUNC_DISABLED) {
2826 PMD_DRV_LOG(DEBUG, "mf_cfg function disabled");
2827 sc->flags |= BNX2X_MF_FUNC_DIS;
2829 PMD_DRV_LOG(DEBUG, "mf_cfg function enabled");
2830 sc->flags &= ~BNX2X_MF_FUNC_DIS;
2834 /* acquire split MCP access lock register */
2835 static int bnx2x_acquire_alr(struct bnx2x_softc *sc)
2839 for (j = 0; j < 1000; j++) {
2841 REG_WR(sc, GRCBASE_MCP + 0x9c, val);
2842 val = REG_RD(sc, GRCBASE_MCP + 0x9c);
2843 if (val & (1L << 31))
2849 if (!(val & (1L << 31))) {
2850 PMD_DRV_LOG(NOTICE, "Cannot acquire MCP access lock register");
2857 /* release split MCP access lock register */
2858 static void bnx2x_release_alr(struct bnx2x_softc *sc)
2860 REG_WR(sc, GRCBASE_MCP + 0x9c, 0);
2863 static void bnx2x_fan_failure(struct bnx2x_softc *sc)
2865 int port = SC_PORT(sc);
2866 uint32_t ext_phy_config;
2868 /* mark the failure */
2870 SHMEM_RD(sc, dev_info.port_hw_config[port].external_phy_config);
2872 ext_phy_config &= ~PORT_HW_CFG_XGXS_EXT_PHY_TYPE_MASK;
2873 ext_phy_config |= PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE;
2874 SHMEM_WR(sc, dev_info.port_hw_config[port].external_phy_config,
2877 /* log the failure */
2879 "Fan Failure has caused the driver to shutdown "
2880 "the card to prevent permanent damage. "
2881 "Please contact OEM Support for assistance");
2883 rte_panic("Schedule task to handle fan failure");
2886 /* this function is called upon a link interrupt */
2887 static void bnx2x_link_attn(struct bnx2x_softc *sc)
2889 uint32_t pause_enabled = 0;
2890 struct host_port_stats *pstats;
2893 /* Make sure that we are synced with the current statistics */
2894 bnx2x_stats_handle(sc, STATS_EVENT_STOP);
2896 elink_link_update(&sc->link_params, &sc->link_vars);
2898 if (sc->link_vars.link_up) {
2900 /* dropless flow control */
2901 if (sc->dropless_fc) {
2904 if (sc->link_vars.flow_ctrl & ELINK_FLOW_CTRL_TX) {
2909 (BAR_USTRORM_INTMEM +
2910 USTORM_ETH_PAUSE_ENABLED_OFFSET(SC_PORT(sc))),
2914 if (sc->link_vars.mac_type != ELINK_MAC_TYPE_EMAC) {
2915 pstats = BNX2X_SP(sc, port_stats);
2916 /* reset old mac stats */
2917 memset(&(pstats->mac_stx[0]), 0,
2918 sizeof(struct mac_stx));
2921 if (sc->state == BNX2X_STATE_OPEN) {
2922 bnx2x_stats_handle(sc, STATS_EVENT_LINK_UP);
2926 if (sc->link_vars.link_up && sc->link_vars.line_speed) {
2927 cmng_fns = bnx2x_get_cmng_fns_mode(sc);
2929 if (cmng_fns != CMNG_FNS_NONE) {
2930 bnx2x_cmng_fns_init(sc, FALSE, cmng_fns);
2931 storm_memset_cmng(sc, &sc->cmng, SC_PORT(sc));
2935 bnx2x_link_report(sc);
2938 bnx2x_link_sync_notify(sc);
2942 static void bnx2x_attn_int_asserted(struct bnx2x_softc *sc, uint32_t asserted)
2944 int port = SC_PORT(sc);
2945 uint32_t aeu_addr = port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 :
2946 MISC_REG_AEU_MASK_ATTN_FUNC_0;
2947 uint32_t nig_int_mask_addr = port ? NIG_REG_MASK_INTERRUPT_PORT1 :
2948 NIG_REG_MASK_INTERRUPT_PORT0;
2950 uint32_t nig_mask = 0;
2955 if (sc->attn_state & asserted) {
2956 PMD_DRV_LOG(ERR, "IGU ERROR attn=0x%08x", asserted);
2959 bnx2x_acquire_hw_lock(sc, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
2961 aeu_mask = REG_RD(sc, aeu_addr);
2963 aeu_mask &= ~(asserted & 0x3ff);
2965 REG_WR(sc, aeu_addr, aeu_mask);
2967 bnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
2969 sc->attn_state |= asserted;
2971 if (asserted & ATTN_HARD_WIRED_MASK) {
2972 if (asserted & ATTN_NIG_FOR_FUNC) {
2974 /* save nig interrupt mask */
2975 nig_mask = REG_RD(sc, nig_int_mask_addr);
2977 /* If nig_mask is not set, no need to call the update function */
2979 REG_WR(sc, nig_int_mask_addr, 0);
2981 bnx2x_link_attn(sc);
2984 /* handle unicore attn? */
2987 if (asserted & ATTN_SW_TIMER_4_FUNC) {
2988 PMD_DRV_LOG(DEBUG, "ATTN_SW_TIMER_4_FUNC!");
2991 if (asserted & GPIO_2_FUNC) {
2992 PMD_DRV_LOG(DEBUG, "GPIO_2_FUNC!");
2995 if (asserted & GPIO_3_FUNC) {
2996 PMD_DRV_LOG(DEBUG, "GPIO_3_FUNC!");
2999 if (asserted & GPIO_4_FUNC) {
3000 PMD_DRV_LOG(DEBUG, "GPIO_4_FUNC!");
3004 if (asserted & ATTN_GENERAL_ATTN_1) {
3005 PMD_DRV_LOG(DEBUG, "ATTN_GENERAL_ATTN_1!");
3006 REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_1, 0x0);
3008 if (asserted & ATTN_GENERAL_ATTN_2) {
3009 PMD_DRV_LOG(DEBUG, "ATTN_GENERAL_ATTN_2!");
3010 REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_2, 0x0);
3012 if (asserted & ATTN_GENERAL_ATTN_3) {
3013 PMD_DRV_LOG(DEBUG, "ATTN_GENERAL_ATTN_3!");
3014 REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_3, 0x0);
3017 if (asserted & ATTN_GENERAL_ATTN_4) {
3018 PMD_DRV_LOG(DEBUG, "ATTN_GENERAL_ATTN_4!");
3019 REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_4, 0x0);
3021 if (asserted & ATTN_GENERAL_ATTN_5) {
3022 PMD_DRV_LOG(DEBUG, "ATTN_GENERAL_ATTN_5!");
3023 REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_5, 0x0);
3025 if (asserted & ATTN_GENERAL_ATTN_6) {
3026 PMD_DRV_LOG(DEBUG, "ATTN_GENERAL_ATTN_6!");
3027 REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_6, 0x0);
3032 if (sc->devinfo.int_block == INT_BLOCK_HC) {
3034 (HC_REG_COMMAND_REG + port * 32 +
3035 COMMAND_REG_ATTN_BITS_SET);
3037 reg_addr = (BAR_IGU_INTMEM + IGU_CMD_ATTN_BIT_SET_UPPER * 8);
3040 PMD_DRV_LOG(DEBUG, "about to mask 0x%08x at %s addr 0x%08x",
3042 (sc->devinfo.int_block == INT_BLOCK_HC) ? "HC" : "IGU",
3044 REG_WR(sc, reg_addr, asserted);
3046 /* now set back the mask */
3047 if (asserted & ATTN_NIG_FOR_FUNC) {
3049 * Verify that IGU ack through BAR was written before restoring
3050 * NIG mask. This loop should exit after 2-3 iterations max.
3052 if (sc->devinfo.int_block != INT_BLOCK_HC) {
3057 REG_RD(sc, IGU_REG_ATTENTION_ACK_BITS);
3058 } while (((igu_acked & ATTN_NIG_FOR_FUNC) == 0)
3059 && (++cnt < MAX_IGU_ATTN_ACK_TO));
3063 "Failed to verify IGU ack on time");
3069 REG_WR(sc, nig_int_mask_addr, nig_mask);
3075 bnx2x_print_next_block(__rte_unused struct bnx2x_softc *sc, __rte_unused int idx,
3076 __rte_unused const char *blk)
3078 PMD_DRV_LOG(INFO, "%s%s", idx ? ", " : "", blk);
3082 bnx2x_check_blocks_with_parity0(struct bnx2x_softc *sc, uint32_t sig, int par_num,
3085 uint32_t cur_bit = 0;
3088 for (i = 0; sig; i++) {
3089 cur_bit = ((uint32_t) 0x1 << i);
3090 if (sig & cur_bit) {
3092 case AEU_INPUTS_ATTN_BITS_BRB_PARITY_ERROR:
3094 bnx2x_print_next_block(sc, par_num++,
3097 case AEU_INPUTS_ATTN_BITS_PARSER_PARITY_ERROR:
3099 bnx2x_print_next_block(sc, par_num++,
3102 case AEU_INPUTS_ATTN_BITS_TSDM_PARITY_ERROR:
3104 bnx2x_print_next_block(sc, par_num++,
3107 case AEU_INPUTS_ATTN_BITS_SEARCHER_PARITY_ERROR:
3109 bnx2x_print_next_block(sc, par_num++,
3112 case AEU_INPUTS_ATTN_BITS_TCM_PARITY_ERROR:
3114 bnx2x_print_next_block(sc, par_num++,
3117 case AEU_INPUTS_ATTN_BITS_TSEMI_PARITY_ERROR:
3119 bnx2x_print_next_block(sc, par_num++,
3122 case AEU_INPUTS_ATTN_BITS_PBCLIENT_PARITY_ERROR:
3124 bnx2x_print_next_block(sc, par_num++,
3138 bnx2x_check_blocks_with_parity1(struct bnx2x_softc *sc, uint32_t sig, int par_num,
3139 uint8_t * global, uint8_t print)
3142 uint32_t cur_bit = 0;
3143 for (i = 0; sig; i++) {
3144 cur_bit = ((uint32_t) 0x1 << i);
3145 if (sig & cur_bit) {
3147 case AEU_INPUTS_ATTN_BITS_PBF_PARITY_ERROR:
3149 bnx2x_print_next_block(sc, par_num++,
3152 case AEU_INPUTS_ATTN_BITS_QM_PARITY_ERROR:
3154 bnx2x_print_next_block(sc, par_num++,
3157 case AEU_INPUTS_ATTN_BITS_TIMERS_PARITY_ERROR:
3159 bnx2x_print_next_block(sc, par_num++,
3162 case AEU_INPUTS_ATTN_BITS_XSDM_PARITY_ERROR:
3164 bnx2x_print_next_block(sc, par_num++,
3167 case AEU_INPUTS_ATTN_BITS_XCM_PARITY_ERROR:
3169 bnx2x_print_next_block(sc, par_num++,
3172 case AEU_INPUTS_ATTN_BITS_XSEMI_PARITY_ERROR:
3174 bnx2x_print_next_block(sc, par_num++,
3177 case AEU_INPUTS_ATTN_BITS_DOORBELLQ_PARITY_ERROR:
3179 bnx2x_print_next_block(sc, par_num++,
3182 case AEU_INPUTS_ATTN_BITS_NIG_PARITY_ERROR:
3184 bnx2x_print_next_block(sc, par_num++,
3187 case AEU_INPUTS_ATTN_BITS_VAUX_PCI_CORE_PARITY_ERROR:
3189 bnx2x_print_next_block(sc, par_num++,
3193 case AEU_INPUTS_ATTN_BITS_DEBUG_PARITY_ERROR:
3195 bnx2x_print_next_block(sc, par_num++,
3198 case AEU_INPUTS_ATTN_BITS_USDM_PARITY_ERROR:
3200 bnx2x_print_next_block(sc, par_num++,
3203 case AEU_INPUTS_ATTN_BITS_UCM_PARITY_ERROR:
3205 bnx2x_print_next_block(sc, par_num++,
3208 case AEU_INPUTS_ATTN_BITS_USEMI_PARITY_ERROR:
3210 bnx2x_print_next_block(sc, par_num++,
3213 case AEU_INPUTS_ATTN_BITS_UPB_PARITY_ERROR:
3215 bnx2x_print_next_block(sc, par_num++,
3218 case AEU_INPUTS_ATTN_BITS_CSDM_PARITY_ERROR:
3220 bnx2x_print_next_block(sc, par_num++,
3223 case AEU_INPUTS_ATTN_BITS_CCM_PARITY_ERROR:
3225 bnx2x_print_next_block(sc, par_num++,
3239 bnx2x_check_blocks_with_parity2(struct bnx2x_softc *sc, uint32_t sig, int par_num,
3242 uint32_t cur_bit = 0;
3245 for (i = 0; sig; i++) {
3246 cur_bit = ((uint32_t) 0x1 << i);
3247 if (sig & cur_bit) {
3249 case AEU_INPUTS_ATTN_BITS_CSEMI_PARITY_ERROR:
3251 bnx2x_print_next_block(sc, par_num++,
3254 case AEU_INPUTS_ATTN_BITS_PXP_PARITY_ERROR:
3256 bnx2x_print_next_block(sc, par_num++,
3259 case AEU_IN_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR:
3261 bnx2x_print_next_block(sc, par_num++,
3262 "PXPPCICLOCKCLIENT");
3264 case AEU_INPUTS_ATTN_BITS_CFC_PARITY_ERROR:
3266 bnx2x_print_next_block(sc, par_num++,
3269 case AEU_INPUTS_ATTN_BITS_CDU_PARITY_ERROR:
3271 bnx2x_print_next_block(sc, par_num++,
3274 case AEU_INPUTS_ATTN_BITS_DMAE_PARITY_ERROR:
3276 bnx2x_print_next_block(sc, par_num++,
3279 case AEU_INPUTS_ATTN_BITS_IGU_PARITY_ERROR:
3281 bnx2x_print_next_block(sc, par_num++,
3284 case AEU_INPUTS_ATTN_BITS_MISC_PARITY_ERROR:
3286 bnx2x_print_next_block(sc, par_num++,
3300 bnx2x_check_blocks_with_parity3(struct bnx2x_softc *sc, uint32_t sig, int par_num,
3301 uint8_t * global, uint8_t print)
3303 uint32_t cur_bit = 0;
3306 for (i = 0; sig; i++) {
3307 cur_bit = ((uint32_t) 0x1 << i);
3308 if (sig & cur_bit) {
3310 case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_ROM_PARITY:
3312 bnx2x_print_next_block(sc, par_num++,
3316 case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_RX_PARITY:
3318 bnx2x_print_next_block(sc, par_num++,
3322 case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_TX_PARITY:
3324 bnx2x_print_next_block(sc, par_num++,
3328 case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_SCPAD_PARITY:
3330 bnx2x_print_next_block(sc, par_num++,
3345 bnx2x_check_blocks_with_parity4(struct bnx2x_softc *sc, uint32_t sig, int par_num,
3348 uint32_t cur_bit = 0;
3351 for (i = 0; sig; i++) {
3352 cur_bit = ((uint32_t) 0x1 << i);
3353 if (sig & cur_bit) {
3355 case AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR:
3357 bnx2x_print_next_block(sc, par_num++,
3360 case AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR:
3362 bnx2x_print_next_block(sc, par_num++,
3376 bnx2x_parity_attn(struct bnx2x_softc *sc, uint8_t * global, uint8_t print,
3381 if ((sig[0] & HW_PRTY_ASSERT_SET_0) ||
3382 (sig[1] & HW_PRTY_ASSERT_SET_1) ||
3383 (sig[2] & HW_PRTY_ASSERT_SET_2) ||
3384 (sig[3] & HW_PRTY_ASSERT_SET_3) ||
3385 (sig[4] & HW_PRTY_ASSERT_SET_4)) {
3387 "Parity error: HW block parity attention:"
3388 "[0]:0x%08x [1]:0x%08x [2]:0x%08x [3]:0x%08x [4]:0x%08x",
3389 (uint32_t) (sig[0] & HW_PRTY_ASSERT_SET_0),
3390 (uint32_t) (sig[1] & HW_PRTY_ASSERT_SET_1),
3391 (uint32_t) (sig[2] & HW_PRTY_ASSERT_SET_2),
3392 (uint32_t) (sig[3] & HW_PRTY_ASSERT_SET_3),
3393 (uint32_t) (sig[4] & HW_PRTY_ASSERT_SET_4));
3396 PMD_DRV_LOG(INFO, "Parity errors detected in blocks: ");
3399 bnx2x_check_blocks_with_parity0(sc, sig[0] &
3400 HW_PRTY_ASSERT_SET_0,
3403 bnx2x_check_blocks_with_parity1(sc, sig[1] &
3404 HW_PRTY_ASSERT_SET_1,
3405 par_num, global, print);
3407 bnx2x_check_blocks_with_parity2(sc, sig[2] &
3408 HW_PRTY_ASSERT_SET_2,
3411 bnx2x_check_blocks_with_parity3(sc, sig[3] &
3412 HW_PRTY_ASSERT_SET_3,
3413 par_num, global, print);
3415 bnx2x_check_blocks_with_parity4(sc, sig[4] &
3416 HW_PRTY_ASSERT_SET_4,
3420 PMD_DRV_LOG(INFO, "");
3429 bnx2x_chk_parity_attn(struct bnx2x_softc *sc, uint8_t * global, uint8_t print)
3431 struct attn_route attn = { {0} };
3432 int port = SC_PORT(sc);
3434 attn.sig[0] = REG_RD(sc, MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 + port * 4);
3435 attn.sig[1] = REG_RD(sc, MISC_REG_AEU_AFTER_INVERT_2_FUNC_0 + port * 4);
3436 attn.sig[2] = REG_RD(sc, MISC_REG_AEU_AFTER_INVERT_3_FUNC_0 + port * 4);
3437 attn.sig[3] = REG_RD(sc, MISC_REG_AEU_AFTER_INVERT_4_FUNC_0 + port * 4);
3439 if (!CHIP_IS_E1x(sc))
3441 REG_RD(sc, MISC_REG_AEU_AFTER_INVERT_5_FUNC_0 + port * 4);
3443 return bnx2x_parity_attn(sc, global, print, attn.sig);
3446 static void bnx2x_attn_int_deasserted4(struct bnx2x_softc *sc, uint32_t attn)
3450 if (attn & AEU_INPUTS_ATTN_BITS_PGLUE_HW_INTERRUPT) {
3451 val = REG_RD(sc, PGLUE_B_REG_PGLUE_B_INT_STS_CLR);
3452 PMD_DRV_LOG(INFO, "ERROR: PGLUE hw attention 0x%08x", val);
3453 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_ADDRESS_ERROR)
3455 "ERROR: PGLUE_B_PGLUE_B_INT_STS_REG_ADDRESS_ERROR");
3456 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_INCORRECT_RCV_BEHAVIOR)
3458 "ERROR: PGLUE_B_PGLUE_B_INT_STS_REG_INCORRECT_RCV_BEHAVIOR");
3459 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_WAS_ERROR_ATTN)
3461 "ERROR: PGLUE_B_PGLUE_B_INT_STS_REG_WAS_ERROR_ATTN");
3462 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_VF_LENGTH_VIOLATION_ATTN)
3464 "ERROR: PGLUE_B_PGLUE_B_INT_STS_REG_VF_LENGTH_VIOLATION_ATTN");
3466 PGLUE_B_PGLUE_B_INT_STS_REG_VF_GRC_SPACE_VIOLATION_ATTN)
3468 "ERROR: PGLUE_B_PGLUE_B_INT_STS_REG_VF_GRC_SPACE_VIOLATION_ATTN");
3470 PGLUE_B_PGLUE_B_INT_STS_REG_VF_MSIX_BAR_VIOLATION_ATTN)
3472 "ERROR: PGLUE_B_PGLUE_B_INT_STS_REG_VF_MSIX_BAR_VIOLATION_ATTN");
3473 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_ERROR_ATTN)
3475 "ERROR: PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_ERROR_ATTN");
3476 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_IN_TWO_RCBS_ATTN)
3478 "ERROR: PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_IN_TWO_RCBS_ATTN");
3479 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_CSSNOOP_FIFO_OVERFLOW)
3481 "ERROR: PGLUE_B_PGLUE_B_INT_STS_REG_CSSNOOP_FIFO_OVERFLOW");
3484 if (attn & AEU_INPUTS_ATTN_BITS_ATC_HW_INTERRUPT) {
3485 val = REG_RD(sc, ATC_REG_ATC_INT_STS_CLR);
3486 PMD_DRV_LOG(INFO, "ERROR: ATC hw attention 0x%08x", val);
3487 if (val & ATC_ATC_INT_STS_REG_ADDRESS_ERROR)
3489 "ERROR: ATC_ATC_INT_STS_REG_ADDRESS_ERROR");
3490 if (val & ATC_ATC_INT_STS_REG_ATC_TCPL_TO_NOT_PEND)
3492 "ERROR: ATC_ATC_INT_STS_REG_ATC_TCPL_TO_NOT_PEND");
3493 if (val & ATC_ATC_INT_STS_REG_ATC_GPA_MULTIPLE_HITS)
3495 "ERROR: ATC_ATC_INT_STS_REG_ATC_GPA_MULTIPLE_HITS");
3496 if (val & ATC_ATC_INT_STS_REG_ATC_RCPL_TO_EMPTY_CNT)
3498 "ERROR: ATC_ATC_INT_STS_REG_ATC_RCPL_TO_EMPTY_CNT");
3499 if (val & ATC_ATC_INT_STS_REG_ATC_TCPL_ERROR)
3501 "ERROR: ATC_ATC_INT_STS_REG_ATC_TCPL_ERROR");
3502 if (val & ATC_ATC_INT_STS_REG_ATC_IREQ_LESS_THAN_STU)
3504 "ERROR: ATC_ATC_INT_STS_REG_ATC_IREQ_LESS_THAN_STU");
3507 if (attn & (AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR |
3508 AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR)) {
3510 "ERROR: FATAL parity attention set4 0x%08x",
3512 (AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR
3514 AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR)));
3518 static void bnx2x_e1h_disable(struct bnx2x_softc *sc)
3520 int port = SC_PORT(sc);
3522 REG_WR(sc, NIG_REG_LLH0_FUNC_EN + port * 8, 0);
3525 static void bnx2x_e1h_enable(struct bnx2x_softc *sc)
3527 int port = SC_PORT(sc);
3529 REG_WR(sc, NIG_REG_LLH0_FUNC_EN + port * 8, 1);
3533 * called due to MCP event (on pmf):
3534 * reread new bandwidth configuration
3536 * notify others function about the change
3538 static void bnx2x_config_mf_bw(struct bnx2x_softc *sc)
3540 if (sc->link_vars.link_up) {
3541 bnx2x_cmng_fns_init(sc, TRUE, CMNG_FNS_MINMAX);
3542 bnx2x_link_sync_notify(sc);
3545 storm_memset_cmng(sc, &sc->cmng, SC_PORT(sc));
3548 static void bnx2x_set_mf_bw(struct bnx2x_softc *sc)
3550 bnx2x_config_mf_bw(sc);
3551 bnx2x_fw_command(sc, DRV_MSG_CODE_SET_MF_BW_ACK, 0);
3554 static void bnx2x_handle_eee_event(struct bnx2x_softc *sc)
3556 bnx2x_fw_command(sc, DRV_MSG_CODE_EEE_RESULTS_ACK, 0);
3559 #define DRV_INFO_ETH_STAT_NUM_MACS_REQUIRED 3
3561 static void bnx2x_drv_info_ether_stat(struct bnx2x_softc *sc)
3563 struct eth_stats_info *ether_stat = &sc->sp->drv_info_to_mcp.ether_stat;
3565 strncpy(ether_stat->version, BNX2X_DRIVER_VERSION,
3566 ETH_STAT_INFO_VERSION_LEN);
3568 sc->sp_objs[0].mac_obj.get_n_elements(sc, &sc->sp_objs[0].mac_obj,
3569 DRV_INFO_ETH_STAT_NUM_MACS_REQUIRED,
3570 ether_stat->mac_local + MAC_PAD,
3573 ether_stat->mtu_size = sc->mtu;
3575 ether_stat->feature_flags |= FEATURE_ETH_CHKSUM_OFFLOAD_MASK;
3576 ether_stat->promiscuous_mode = 0; // (flags & PROMISC) ? 1 : 0;
3578 ether_stat->txq_size = sc->tx_ring_size;
3579 ether_stat->rxq_size = sc->rx_ring_size;
3582 static void bnx2x_handle_drv_info_req(struct bnx2x_softc *sc)
3584 enum drv_info_opcode op_code;
3585 uint32_t drv_info_ctl = SHMEM2_RD(sc, drv_info_control);
3587 /* if drv_info version supported by MFW doesn't match - send NACK */
3588 if ((drv_info_ctl & DRV_INFO_CONTROL_VER_MASK) != DRV_INFO_CUR_VER) {
3589 bnx2x_fw_command(sc, DRV_MSG_CODE_DRV_INFO_NACK, 0);
3593 op_code = ((drv_info_ctl & DRV_INFO_CONTROL_OP_CODE_MASK) >>
3594 DRV_INFO_CONTROL_OP_CODE_SHIFT);
3596 memset(&sc->sp->drv_info_to_mcp, 0, sizeof(union drv_info_to_mcp));
3599 case ETH_STATS_OPCODE:
3600 bnx2x_drv_info_ether_stat(sc);
3602 case FCOE_STATS_OPCODE:
3603 case ISCSI_STATS_OPCODE:
3605 /* if op code isn't supported - send NACK */
3606 bnx2x_fw_command(sc, DRV_MSG_CODE_DRV_INFO_NACK, 0);
3611 * If we got drv_info attn from MFW then these fields are defined in
3614 SHMEM2_WR(sc, drv_info_host_addr_lo,
3615 U64_LO(BNX2X_SP_MAPPING(sc, drv_info_to_mcp)));
3616 SHMEM2_WR(sc, drv_info_host_addr_hi,
3617 U64_HI(BNX2X_SP_MAPPING(sc, drv_info_to_mcp)));
3619 bnx2x_fw_command(sc, DRV_MSG_CODE_DRV_INFO_ACK, 0);
3622 static void bnx2x_dcc_event(struct bnx2x_softc *sc, uint32_t dcc_event)
3624 if (dcc_event & DRV_STATUS_DCC_DISABLE_ENABLE_PF) {
3626 * This is the only place besides the function initialization
3627 * where the sc->flags can change so it is done without any
3631 mf_info.mf_config[SC_VN(sc)] & FUNC_MF_CFG_FUNC_DISABLED) {
3632 PMD_DRV_LOG(DEBUG, "mf_cfg function disabled");
3633 sc->flags |= BNX2X_MF_FUNC_DIS;
3634 bnx2x_e1h_disable(sc);
3636 PMD_DRV_LOG(DEBUG, "mf_cfg function enabled");
3637 sc->flags &= ~BNX2X_MF_FUNC_DIS;
3638 bnx2x_e1h_enable(sc);
3640 dcc_event &= ~DRV_STATUS_DCC_DISABLE_ENABLE_PF;
3643 if (dcc_event & DRV_STATUS_DCC_BANDWIDTH_ALLOCATION) {
3644 bnx2x_config_mf_bw(sc);
3645 dcc_event &= ~DRV_STATUS_DCC_BANDWIDTH_ALLOCATION;
3648 /* Report results to MCP */
3650 bnx2x_fw_command(sc, DRV_MSG_CODE_DCC_FAILURE, 0);
3652 bnx2x_fw_command(sc, DRV_MSG_CODE_DCC_OK, 0);
3655 static void bnx2x_pmf_update(struct bnx2x_softc *sc)
3657 int port = SC_PORT(sc);
3663 * We need the mb() to ensure the ordering between the writing to
3664 * sc->port.pmf here and reading it from the bnx2x_periodic_task().
3668 /* enable nig attention */
3669 val = (0xff0f | (1 << (SC_VN(sc) + 4)));
3670 if (sc->devinfo.int_block == INT_BLOCK_HC) {
3671 REG_WR(sc, HC_REG_TRAILING_EDGE_0 + port * 8, val);
3672 REG_WR(sc, HC_REG_LEADING_EDGE_0 + port * 8, val);
3673 } else if (!CHIP_IS_E1x(sc)) {
3674 REG_WR(sc, IGU_REG_TRAILING_EDGE_LATCH, val);
3675 REG_WR(sc, IGU_REG_LEADING_EDGE_LATCH, val);
3678 bnx2x_stats_handle(sc, STATS_EVENT_PMF);
3681 static int bnx2x_mc_assert(struct bnx2x_softc *sc)
3685 __rte_unused uint32_t row0, row1, row2, row3;
3689 REG_RD8(sc, BAR_XSTRORM_INTMEM + XSTORM_ASSERT_LIST_INDEX_OFFSET);
3691 PMD_DRV_LOG(ERR, "XSTORM_ASSERT_LIST_INDEX 0x%x", last_idx);
3693 /* print the asserts */
3694 for (i = 0; i < STORM_ASSERT_ARRAY_SIZE; i++) {
3698 BAR_XSTRORM_INTMEM + XSTORM_ASSERT_LIST_OFFSET(i));
3701 BAR_XSTRORM_INTMEM + XSTORM_ASSERT_LIST_OFFSET(i) +
3705 BAR_XSTRORM_INTMEM + XSTORM_ASSERT_LIST_OFFSET(i) +
3709 BAR_XSTRORM_INTMEM + XSTORM_ASSERT_LIST_OFFSET(i) +
3712 if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) {
3714 "XSTORM_ASSERT_INDEX 0x%x = 0x%08x 0x%08x 0x%08x 0x%08x",
3715 i, row3, row2, row1, row0);
3724 REG_RD8(sc, BAR_TSTRORM_INTMEM + TSTORM_ASSERT_LIST_INDEX_OFFSET);
3726 PMD_DRV_LOG(ERR, "TSTORM_ASSERT_LIST_INDEX 0x%x", last_idx);
3729 /* print the asserts */
3730 for (i = 0; i < STORM_ASSERT_ARRAY_SIZE; i++) {
3734 BAR_TSTRORM_INTMEM + TSTORM_ASSERT_LIST_OFFSET(i));
3737 BAR_TSTRORM_INTMEM + TSTORM_ASSERT_LIST_OFFSET(i) +
3741 BAR_TSTRORM_INTMEM + TSTORM_ASSERT_LIST_OFFSET(i) +
3745 BAR_TSTRORM_INTMEM + TSTORM_ASSERT_LIST_OFFSET(i) +
3748 if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) {
3750 "TSTORM_ASSERT_INDEX 0x%x = 0x%08x 0x%08x 0x%08x 0x%08x",
3751 i, row3, row2, row1, row0);
3760 REG_RD8(sc, BAR_CSTRORM_INTMEM + CSTORM_ASSERT_LIST_INDEX_OFFSET);
3762 PMD_DRV_LOG(ERR, "CSTORM_ASSERT_LIST_INDEX 0x%x", last_idx);
3765 /* print the asserts */
3766 for (i = 0; i < STORM_ASSERT_ARRAY_SIZE; i++) {
3770 BAR_CSTRORM_INTMEM + CSTORM_ASSERT_LIST_OFFSET(i));
3773 BAR_CSTRORM_INTMEM + CSTORM_ASSERT_LIST_OFFSET(i) +
3777 BAR_CSTRORM_INTMEM + CSTORM_ASSERT_LIST_OFFSET(i) +
3781 BAR_CSTRORM_INTMEM + CSTORM_ASSERT_LIST_OFFSET(i) +
3784 if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) {
3786 "CSTORM_ASSERT_INDEX 0x%x = 0x%08x 0x%08x 0x%08x 0x%08x",
3787 i, row3, row2, row1, row0);
3796 REG_RD8(sc, BAR_USTRORM_INTMEM + USTORM_ASSERT_LIST_INDEX_OFFSET);
3798 PMD_DRV_LOG(ERR, "USTORM_ASSERT_LIST_INDEX 0x%x", last_idx);
3801 /* print the asserts */
3802 for (i = 0; i < STORM_ASSERT_ARRAY_SIZE; i++) {
3806 BAR_USTRORM_INTMEM + USTORM_ASSERT_LIST_OFFSET(i));
3809 BAR_USTRORM_INTMEM + USTORM_ASSERT_LIST_OFFSET(i) +
3813 BAR_USTRORM_INTMEM + USTORM_ASSERT_LIST_OFFSET(i) +
3817 BAR_USTRORM_INTMEM + USTORM_ASSERT_LIST_OFFSET(i) +
3820 if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) {
3822 "USTORM_ASSERT_INDEX 0x%x = 0x%08x 0x%08x 0x%08x 0x%08x",
3823 i, row3, row2, row1, row0);
3833 static void bnx2x_attn_int_deasserted3(struct bnx2x_softc *sc, uint32_t attn)
3835 int func = SC_FUNC(sc);
3838 if (attn & EVEREST_GEN_ATTN_IN_USE_MASK) {
3840 if (attn & BNX2X_PMF_LINK_ASSERT(sc)) {
3842 REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_12 + func * 4, 0);
3843 bnx2x_read_mf_cfg(sc);
3844 sc->devinfo.mf_info.mf_config[SC_VN(sc)] =
3846 func_mf_config[SC_ABS_FUNC(sc)].config);
3848 SHMEM_RD(sc, func_mb[SC_FW_MB_IDX(sc)].drv_status);
3850 if (val & DRV_STATUS_DCC_EVENT_MASK)
3853 DRV_STATUS_DCC_EVENT_MASK));
3855 if (val & DRV_STATUS_SET_MF_BW)
3856 bnx2x_set_mf_bw(sc);
3858 if (val & DRV_STATUS_DRV_INFO_REQ)
3859 bnx2x_handle_drv_info_req(sc);
3861 if ((sc->port.pmf == 0) && (val & DRV_STATUS_PMF))
3862 bnx2x_pmf_update(sc);
3864 if (val & DRV_STATUS_EEE_NEGOTIATION_RESULTS)
3865 bnx2x_handle_eee_event(sc);
3867 if (sc->link_vars.periodic_flags &
3868 ELINK_PERIODIC_FLAGS_LINK_EVENT) {
3869 /* sync with link */
3870 sc->link_vars.periodic_flags &=
3871 ~ELINK_PERIODIC_FLAGS_LINK_EVENT;
3873 bnx2x_link_sync_notify(sc);
3875 bnx2x_link_report(sc);
3879 * Always call it here: bnx2x_link_report() will
3880 * prevent the link indication duplication.
3882 bnx2x_link_status_update(sc);
3884 } else if (attn & BNX2X_MC_ASSERT_BITS) {
3886 PMD_DRV_LOG(ERR, "MC assert!");
3887 bnx2x_mc_assert(sc);
3888 REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_10, 0);
3889 REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_9, 0);
3890 REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_8, 0);
3891 REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_7, 0);
3892 rte_panic("MC assert!");
3894 } else if (attn & BNX2X_MCP_ASSERT) {
3896 PMD_DRV_LOG(ERR, "MCP assert!");
3897 REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_11, 0);
3901 "Unknown HW assert! (attn 0x%08x)", attn);
3905 if (attn & EVEREST_LATCHED_ATTN_IN_USE_MASK) {
3906 PMD_DRV_LOG(ERR, "LATCHED attention 0x%08x (masked)", attn);
3907 if (attn & BNX2X_GRC_TIMEOUT) {
3908 val = REG_RD(sc, MISC_REG_GRC_TIMEOUT_ATTN);
3909 PMD_DRV_LOG(ERR, "GRC time-out 0x%08x", val);
3911 if (attn & BNX2X_GRC_RSV) {
3912 val = REG_RD(sc, MISC_REG_GRC_RSV_ATTN);
3913 PMD_DRV_LOG(ERR, "GRC reserved 0x%08x", val);
3915 REG_WR(sc, MISC_REG_AEU_CLR_LATCH_SIGNAL, 0x7ff);
3919 static void bnx2x_attn_int_deasserted2(struct bnx2x_softc *sc, uint32_t attn)
3921 int port = SC_PORT(sc);
3923 uint32_t val0, mask0, val1, mask1;
3926 if (attn & AEU_INPUTS_ATTN_BITS_CFC_HW_INTERRUPT) {
3927 val = REG_RD(sc, CFC_REG_CFC_INT_STS_CLR);
3928 PMD_DRV_LOG(ERR, "CFC hw attention 0x%08x", val);
3929 /* CFC error attention */
3931 PMD_DRV_LOG(ERR, "FATAL error from CFC");
3935 if (attn & AEU_INPUTS_ATTN_BITS_PXP_HW_INTERRUPT) {
3936 val = REG_RD(sc, PXP_REG_PXP_INT_STS_CLR_0);
3937 PMD_DRV_LOG(ERR, "PXP hw attention-0 0x%08x", val);
3938 /* RQ_USDMDP_FIFO_OVERFLOW */
3939 if (val & 0x18000) {
3940 PMD_DRV_LOG(ERR, "FATAL error from PXP");
3943 if (!CHIP_IS_E1x(sc)) {
3944 val = REG_RD(sc, PXP_REG_PXP_INT_STS_CLR_1);
3945 PMD_DRV_LOG(ERR, "PXP hw attention-1 0x%08x", val);
3948 #define PXP2_EOP_ERROR_BIT PXP2_PXP2_INT_STS_CLR_0_REG_WR_PGLUE_EOP_ERROR
3949 #define AEU_PXP2_HW_INT_BIT AEU_INPUTS_ATTN_BITS_PXPPCICLOCKCLIENT_HW_INTERRUPT
3951 if (attn & AEU_PXP2_HW_INT_BIT) {
3952 /* CQ47854 workaround do not panic on
3953 * PXP2_PXP2_INT_STS_0_REG_WR_PGLUE_EOP_ERROR
3955 if (!CHIP_IS_E1x(sc)) {
3956 mask0 = REG_RD(sc, PXP2_REG_PXP2_INT_MASK_0);
3957 val1 = REG_RD(sc, PXP2_REG_PXP2_INT_STS_1);
3958 mask1 = REG_RD(sc, PXP2_REG_PXP2_INT_MASK_1);
3959 val0 = REG_RD(sc, PXP2_REG_PXP2_INT_STS_0);
3961 * If the olny PXP2_EOP_ERROR_BIT is set in
3962 * STS0 and STS1 - clear it
3964 * probably we lose additional attentions between
3965 * STS0 and STS_CLR0, in this case user will not
3966 * be notified about them
3968 if (val0 & mask0 & PXP2_EOP_ERROR_BIT &&
3970 val0 = REG_RD(sc, PXP2_REG_PXP2_INT_STS_CLR_0);
3972 /* print the register, since no one can restore it */
3974 "PXP2_REG_PXP2_INT_STS_CLR_0 0x%08x", val0);
3977 * if PXP2_PXP2_INT_STS_0_REG_WR_PGLUE_EOP_ERROR
3980 if (val0 & PXP2_EOP_ERROR_BIT) {
3981 PMD_DRV_LOG(ERR, "PXP2_WR_PGLUE_EOP_ERROR");
3984 * if only PXP2_PXP2_INT_STS_0_REG_WR_PGLUE_EOP_ERROR is
3985 * set then clear attention from PXP2 block without panic
3987 if (((val0 & mask0) == PXP2_EOP_ERROR_BIT) &&
3988 ((val1 & mask1) == 0))
3989 attn &= ~AEU_PXP2_HW_INT_BIT;
3994 if (attn & HW_INTERRUT_ASSERT_SET_2) {
3995 reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_2 :
3996 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_2);
3998 val = REG_RD(sc, reg_offset);
3999 val &= ~(attn & HW_INTERRUT_ASSERT_SET_2);
4000 REG_WR(sc, reg_offset, val);
4003 "FATAL HW block attention set2 0x%x",
4004 (uint32_t) (attn & HW_INTERRUT_ASSERT_SET_2));
4005 rte_panic("HW block attention set2");
4009 static void bnx2x_attn_int_deasserted1(struct bnx2x_softc *sc, uint32_t attn)
4011 int port = SC_PORT(sc);
4015 if (attn & AEU_INPUTS_ATTN_BITS_DOORBELLQ_HW_INTERRUPT) {
4016 val = REG_RD(sc, DORQ_REG_DORQ_INT_STS_CLR);
4017 PMD_DRV_LOG(ERR, "DB hw attention 0x%08x", val);
4018 /* DORQ discard attention */
4020 PMD_DRV_LOG(ERR, "FATAL error from DORQ");
4024 if (attn & HW_INTERRUT_ASSERT_SET_1) {
4025 reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_1 :
4026 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_1);
4028 val = REG_RD(sc, reg_offset);
4029 val &= ~(attn & HW_INTERRUT_ASSERT_SET_1);
4030 REG_WR(sc, reg_offset, val);
4033 "FATAL HW block attention set1 0x%08x",
4034 (uint32_t) (attn & HW_INTERRUT_ASSERT_SET_1));
4035 rte_panic("HW block attention set1");
4039 static void bnx2x_attn_int_deasserted0(struct bnx2x_softc *sc, uint32_t attn)
4041 int port = SC_PORT(sc);
4045 reg_offset = (port) ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 :
4046 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0;
4048 if (attn & AEU_INPUTS_ATTN_BITS_SPIO5) {
4049 val = REG_RD(sc, reg_offset);
4050 val &= ~AEU_INPUTS_ATTN_BITS_SPIO5;
4051 REG_WR(sc, reg_offset, val);
4053 PMD_DRV_LOG(WARNING, "SPIO5 hw attention");
4055 /* Fan failure attention */
4056 elink_hw_reset_phy(&sc->link_params);
4057 bnx2x_fan_failure(sc);
4060 if ((attn & sc->link_vars.aeu_int_mask) && sc->port.pmf) {
4061 elink_handle_module_detect_int(&sc->link_params);
4064 if (attn & HW_INTERRUT_ASSERT_SET_0) {
4065 val = REG_RD(sc, reg_offset);
4066 val &= ~(attn & HW_INTERRUT_ASSERT_SET_0);
4067 REG_WR(sc, reg_offset, val);
4069 rte_panic("FATAL HW block attention set0 0x%lx",
4070 (attn & HW_INTERRUT_ASSERT_SET_0));
4074 static void bnx2x_attn_int_deasserted(struct bnx2x_softc *sc, uint32_t deasserted)
4076 struct attn_route attn;
4077 struct attn_route *group_mask;
4078 int port = SC_PORT(sc);
4083 uint8_t global = FALSE;
4086 * Need to take HW lock because MCP or other port might also
4087 * try to handle this event.
4089 bnx2x_acquire_alr(sc);
4091 if (bnx2x_chk_parity_attn(sc, &global, TRUE)) {
4092 sc->recovery_state = BNX2X_RECOVERY_INIT;
4094 /* disable HW interrupts */
4095 bnx2x_int_disable(sc);
4096 bnx2x_release_alr(sc);
4100 attn.sig[0] = REG_RD(sc, MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 + port * 4);
4101 attn.sig[1] = REG_RD(sc, MISC_REG_AEU_AFTER_INVERT_2_FUNC_0 + port * 4);
4102 attn.sig[2] = REG_RD(sc, MISC_REG_AEU_AFTER_INVERT_3_FUNC_0 + port * 4);
4103 attn.sig[3] = REG_RD(sc, MISC_REG_AEU_AFTER_INVERT_4_FUNC_0 + port * 4);
4104 if (!CHIP_IS_E1x(sc)) {
4106 REG_RD(sc, MISC_REG_AEU_AFTER_INVERT_5_FUNC_0 + port * 4);
4111 for (index = 0; index < MAX_DYNAMIC_ATTN_GRPS; index++) {
4112 if (deasserted & (1 << index)) {
4113 group_mask = &sc->attn_group[index];
4115 bnx2x_attn_int_deasserted4(sc,
4117 sig[4] & group_mask->sig[4]);
4118 bnx2x_attn_int_deasserted3(sc,
4120 sig[3] & group_mask->sig[3]);
4121 bnx2x_attn_int_deasserted1(sc,
4123 sig[1] & group_mask->sig[1]);
4124 bnx2x_attn_int_deasserted2(sc,
4126 sig[2] & group_mask->sig[2]);
4127 bnx2x_attn_int_deasserted0(sc,
4129 sig[0] & group_mask->sig[0]);
4133 bnx2x_release_alr(sc);
4135 if (sc->devinfo.int_block == INT_BLOCK_HC) {
4136 reg_addr = (HC_REG_COMMAND_REG + port * 32 +
4137 COMMAND_REG_ATTN_BITS_CLR);
4139 reg_addr = (BAR_IGU_INTMEM + IGU_CMD_ATTN_BIT_CLR_UPPER * 8);
4144 "about to mask 0x%08x at %s addr 0x%08x", val,
4145 (sc->devinfo.int_block == INT_BLOCK_HC) ? "HC" : "IGU",
4147 REG_WR(sc, reg_addr, val);
4149 if (~sc->attn_state & deasserted) {
4150 PMD_DRV_LOG(ERR, "IGU error");
4153 reg_addr = port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 :
4154 MISC_REG_AEU_MASK_ATTN_FUNC_0;
4156 bnx2x_acquire_hw_lock(sc, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
4158 aeu_mask = REG_RD(sc, reg_addr);
4160 aeu_mask |= (deasserted & 0x3ff);
4162 REG_WR(sc, reg_addr, aeu_mask);
4163 bnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
4165 sc->attn_state &= ~deasserted;
4168 static void bnx2x_attn_int(struct bnx2x_softc *sc)
4170 /* read local copy of bits */
4171 uint32_t attn_bits = le32toh(sc->def_sb->atten_status_block.attn_bits);
4173 le32toh(sc->def_sb->atten_status_block.attn_bits_ack);
4174 uint32_t attn_state = sc->attn_state;
4176 /* look for changed bits */
4177 uint32_t asserted = attn_bits & ~attn_ack & ~attn_state;
4178 uint32_t deasserted = ~attn_bits & attn_ack & attn_state;
4181 "attn_bits 0x%08x attn_ack 0x%08x asserted 0x%08x deasserted 0x%08x",
4182 attn_bits, attn_ack, asserted, deasserted);
4184 if (~(attn_bits ^ attn_ack) & (attn_bits ^ attn_state)) {
4185 PMD_DRV_LOG(ERR, "BAD attention state");
4188 /* handle bits that were raised */
4190 bnx2x_attn_int_asserted(sc, asserted);
4194 bnx2x_attn_int_deasserted(sc, deasserted);
4198 static uint16_t bnx2x_update_dsb_idx(struct bnx2x_softc *sc)
4200 struct host_sp_status_block *def_sb = sc->def_sb;
4203 mb(); /* status block is written to by the chip */
4205 if (sc->def_att_idx != def_sb->atten_status_block.attn_bits_index) {
4206 sc->def_att_idx = def_sb->atten_status_block.attn_bits_index;
4207 rc |= BNX2X_DEF_SB_ATT_IDX;
4210 if (sc->def_idx != def_sb->sp_sb.running_index) {
4211 sc->def_idx = def_sb->sp_sb.running_index;
4212 rc |= BNX2X_DEF_SB_IDX;
4220 static struct ecore_queue_sp_obj *bnx2x_cid_to_q_obj(struct bnx2x_softc *sc,
4223 return &sc->sp_objs[CID_TO_FP(cid, sc)].q_obj;
4226 static void bnx2x_handle_mcast_eqe(struct bnx2x_softc *sc)
4228 struct ecore_mcast_ramrod_params rparam;
4231 memset(&rparam, 0, sizeof(rparam));
4233 rparam.mcast_obj = &sc->mcast_obj;
4235 /* clear pending state for the last command */
4236 sc->mcast_obj.raw.clear_pending(&sc->mcast_obj.raw);
4238 /* if there are pending mcast commands - send them */
4239 if (sc->mcast_obj.check_pending(&sc->mcast_obj)) {
4240 rc = ecore_config_mcast(sc, &rparam, ECORE_MCAST_CMD_CONT);
4243 "Failed to send pending mcast commands (%d)",
4250 bnx2x_handle_classification_eqe(struct bnx2x_softc *sc, union event_ring_elem *elem)
4252 unsigned long ramrod_flags = 0;
4254 uint32_t cid = elem->message.data.eth_event.echo & BNX2X_SWCID_MASK;
4255 struct ecore_vlan_mac_obj *vlan_mac_obj;
4257 /* always push next commands out, don't wait here */
4258 bnx2x_set_bit(RAMROD_CONT, &ramrod_flags);
4260 switch (le32toh(elem->message.data.eth_event.echo) >> BNX2X_SWCID_SHIFT) {
4261 case ECORE_FILTER_MAC_PENDING:
4262 PMD_DRV_LOG(DEBUG, "Got SETUP_MAC completions");
4263 vlan_mac_obj = &sc->sp_objs[cid].mac_obj;
4266 case ECORE_FILTER_MCAST_PENDING:
4267 PMD_DRV_LOG(DEBUG, "Got SETUP_MCAST completions");
4268 bnx2x_handle_mcast_eqe(sc);
4272 PMD_DRV_LOG(NOTICE, "Unsupported classification command: %d",
4273 elem->message.data.eth_event.echo);
4277 rc = vlan_mac_obj->complete(sc, vlan_mac_obj, elem, &ramrod_flags);
4280 PMD_DRV_LOG(NOTICE, "Failed to schedule new commands (%d)", rc);
4281 } else if (rc > 0) {
4282 PMD_DRV_LOG(DEBUG, "Scheduled next pending commands...");
4286 static void bnx2x_handle_rx_mode_eqe(struct bnx2x_softc *sc)
4288 bnx2x_clear_bit(ECORE_FILTER_RX_MODE_PENDING, &sc->sp_state);
4290 /* send rx_mode command again if was requested */
4291 if (bnx2x_test_and_clear_bit(ECORE_FILTER_RX_MODE_SCHED, &sc->sp_state)) {
4292 bnx2x_set_storm_rx_mode(sc);
4296 static void bnx2x_update_eq_prod(struct bnx2x_softc *sc, uint16_t prod)
4298 storm_memset_eq_prod(sc, prod, SC_FUNC(sc));
4299 wmb(); /* keep prod updates ordered */
4302 static void bnx2x_eq_int(struct bnx2x_softc *sc)
4304 uint16_t hw_cons, sw_cons, sw_prod;
4305 union event_ring_elem *elem;
4310 struct ecore_queue_sp_obj *q_obj;
4311 struct ecore_func_sp_obj *f_obj = &sc->func_obj;
4312 struct ecore_raw_obj *rss_raw = &sc->rss_conf_obj.raw;
4314 hw_cons = le16toh(*sc->eq_cons_sb);
4317 * The hw_cons range is 1-255, 257 - the sw_cons range is 0-254, 256.
4318 * when we get to the next-page we need to adjust so the loop
4319 * condition below will be met. The next element is the size of a
4320 * regular element and hence incrementing by 1
4322 if ((hw_cons & EQ_DESC_MAX_PAGE) == EQ_DESC_MAX_PAGE) {
4327 * This function may never run in parallel with itself for a
4328 * specific sc and no need for a read memory barrier here.
4330 sw_cons = sc->eq_cons;
4331 sw_prod = sc->eq_prod;
4335 sw_prod = NEXT_EQ_IDX(sw_prod), sw_cons = NEXT_EQ_IDX(sw_cons)) {
4337 elem = &sc->eq[EQ_DESC(sw_cons)];
4339 /* elem CID originates from FW, actually LE */
4340 cid = SW_CID(elem->message.data.cfc_del_event.cid);
4341 opcode = elem->message.opcode;
4343 /* handle eq element */
4345 case EVENT_RING_OPCODE_STAT_QUERY:
4346 PMD_DEBUG_PERIODIC_LOG(DEBUG, "got statistics completion event %d",
4348 /* nothing to do with stats comp */
4351 case EVENT_RING_OPCODE_CFC_DEL:
4352 /* handle according to cid range */
4353 /* we may want to verify here that the sc state is HALTING */
4354 PMD_DRV_LOG(DEBUG, "got delete ramrod for MULTI[%d]",
4356 q_obj = bnx2x_cid_to_q_obj(sc, cid);
4357 if (q_obj->complete_cmd(sc, q_obj, ECORE_Q_CMD_CFC_DEL)) {
4362 case EVENT_RING_OPCODE_STOP_TRAFFIC:
4363 PMD_DRV_LOG(DEBUG, "got STOP TRAFFIC");
4364 if (f_obj->complete_cmd(sc, f_obj, ECORE_F_CMD_TX_STOP)) {
4369 case EVENT_RING_OPCODE_START_TRAFFIC:
4370 PMD_DRV_LOG(DEBUG, "got START TRAFFIC");
4371 if (f_obj->complete_cmd
4372 (sc, f_obj, ECORE_F_CMD_TX_START)) {
4377 case EVENT_RING_OPCODE_FUNCTION_UPDATE:
4378 echo = elem->message.data.function_update_event.echo;
4379 if (echo == SWITCH_UPDATE) {
4381 "got FUNC_SWITCH_UPDATE ramrod");
4382 if (f_obj->complete_cmd(sc, f_obj,
4383 ECORE_F_CMD_SWITCH_UPDATE))
4389 "AFEX: ramrod completed FUNCTION_UPDATE");
4390 f_obj->complete_cmd(sc, f_obj,
4391 ECORE_F_CMD_AFEX_UPDATE);
4395 case EVENT_RING_OPCODE_FORWARD_SETUP:
4396 q_obj = &bnx2x_fwd_sp_obj(sc, q_obj);
4397 if (q_obj->complete_cmd(sc, q_obj,
4398 ECORE_Q_CMD_SETUP_TX_ONLY)) {
4403 case EVENT_RING_OPCODE_FUNCTION_START:
4404 PMD_DRV_LOG(DEBUG, "got FUNC_START ramrod");
4405 if (f_obj->complete_cmd(sc, f_obj, ECORE_F_CMD_START)) {
4410 case EVENT_RING_OPCODE_FUNCTION_STOP:
4411 PMD_DRV_LOG(DEBUG, "got FUNC_STOP ramrod");
4412 if (f_obj->complete_cmd(sc, f_obj, ECORE_F_CMD_STOP)) {
4418 switch (opcode | sc->state) {
4419 case (EVENT_RING_OPCODE_RSS_UPDATE_RULES | BNX2X_STATE_OPEN):
4420 case (EVENT_RING_OPCODE_RSS_UPDATE_RULES | BNX2X_STATE_OPENING_WAITING_PORT):
4422 elem->message.data.eth_event.echo & BNX2X_SWCID_MASK;
4423 PMD_DRV_LOG(DEBUG, "got RSS_UPDATE ramrod. CID %d",
4425 rss_raw->clear_pending(rss_raw);
4428 case (EVENT_RING_OPCODE_SET_MAC | BNX2X_STATE_OPEN):
4429 case (EVENT_RING_OPCODE_SET_MAC | BNX2X_STATE_DIAG):
4430 case (EVENT_RING_OPCODE_SET_MAC | BNX2X_STATE_CLOSING_WAITING_HALT):
4431 case (EVENT_RING_OPCODE_CLASSIFICATION_RULES | BNX2X_STATE_OPEN):
4432 case (EVENT_RING_OPCODE_CLASSIFICATION_RULES | BNX2X_STATE_DIAG):
4433 case (EVENT_RING_OPCODE_CLASSIFICATION_RULES | BNX2X_STATE_CLOSING_WAITING_HALT):
4435 "got (un)set mac ramrod");
4436 bnx2x_handle_classification_eqe(sc, elem);
4439 case (EVENT_RING_OPCODE_MULTICAST_RULES | BNX2X_STATE_OPEN):
4440 case (EVENT_RING_OPCODE_MULTICAST_RULES | BNX2X_STATE_DIAG):
4441 case (EVENT_RING_OPCODE_MULTICAST_RULES | BNX2X_STATE_CLOSING_WAITING_HALT):
4443 "got mcast ramrod");
4444 bnx2x_handle_mcast_eqe(sc);
4447 case (EVENT_RING_OPCODE_FILTERS_RULES | BNX2X_STATE_OPEN):
4448 case (EVENT_RING_OPCODE_FILTERS_RULES | BNX2X_STATE_DIAG):
4449 case (EVENT_RING_OPCODE_FILTERS_RULES | BNX2X_STATE_CLOSING_WAITING_HALT):
4451 "got rx_mode ramrod");
4452 bnx2x_handle_rx_mode_eqe(sc);
4456 /* unknown event log error and continue */
4457 PMD_DRV_LOG(INFO, "Unknown EQ event %d, sc->state 0x%x",
4458 elem->message.opcode, sc->state);
4466 atomic_add_acq_long(&sc->eq_spq_left, spqe_cnt);
4468 sc->eq_cons = sw_cons;
4469 sc->eq_prod = sw_prod;
4471 /* make sure that above mem writes were issued towards the memory */
4474 /* update producer */
4475 bnx2x_update_eq_prod(sc, sc->eq_prod);
4478 static int bnx2x_handle_sp_tq(struct bnx2x_softc *sc)
4483 /* what work needs to be performed? */
4484 status = bnx2x_update_dsb_idx(sc);
4487 if (status & BNX2X_DEF_SB_ATT_IDX) {
4488 PMD_DRV_LOG(DEBUG, "---> ATTN INTR <---");
4490 status &= ~BNX2X_DEF_SB_ATT_IDX;
4494 /* SP events: STAT_QUERY and others */
4495 if (status & BNX2X_DEF_SB_IDX) {
4496 /* handle EQ completions */
4497 PMD_DEBUG_PERIODIC_LOG(DEBUG, "---> EQ INTR <---");
4499 bnx2x_ack_sb(sc, sc->igu_dsb_id, USTORM_ID,
4500 le16toh(sc->def_idx), IGU_INT_NOP, 1);
4501 status &= ~BNX2X_DEF_SB_IDX;
4504 /* if status is non zero then something went wrong */
4505 if (unlikely(status)) {
4507 "Got an unknown SP interrupt! (0x%04x)", status);
4510 /* ack status block only if something was actually handled */
4511 bnx2x_ack_sb(sc, sc->igu_dsb_id, ATTENTION_ID,
4512 le16toh(sc->def_att_idx), IGU_INT_ENABLE, 1);
4517 static void bnx2x_handle_fp_tq(struct bnx2x_fastpath *fp, int scan_fp)
4519 struct bnx2x_softc *sc = fp->sc;
4520 uint8_t more_rx = FALSE;
4522 /* update the fastpath index */
4523 bnx2x_update_fp_sb_idx(fp);
4526 if (bnx2x_has_rx_work(fp)) {
4527 more_rx = bnx2x_rxeof(sc, fp);
4531 /* still more work to do */
4532 bnx2x_handle_fp_tq(fp, scan_fp);
4537 bnx2x_ack_sb(sc, fp->igu_sb_id, USTORM_ID,
4538 le16toh(fp->fp_hc_idx), IGU_INT_ENABLE, 1);
4542 * Legacy interrupt entry point.
4544 * Verifies that the controller generated the interrupt and
4545 * then calls a separate routine to handle the various
4546 * interrupt causes: link, RX, and TX.
4548 int bnx2x_intr_legacy(struct bnx2x_softc *sc, int scan_fp)
4550 struct bnx2x_fastpath *fp;
4551 uint32_t status, mask;
4555 * 0 for ustorm, 1 for cstorm
4556 * the bits returned from ack_int() are 0-15
4557 * bit 0 = attention status block
4558 * bit 1 = fast path status block
4559 * a mask of 0x2 or more = tx/rx event
4560 * a mask of 1 = slow path event
4563 status = bnx2x_ack_int(sc);
4565 /* the interrupt is not for us */
4566 if (unlikely(status == 0)) {
4570 PMD_DEBUG_PERIODIC_LOG(DEBUG, "Interrupt status 0x%04x", status);
4571 //bnx2x_dump_status_block(sc);
4573 FOR_EACH_ETH_QUEUE(sc, i) {
4575 mask = (0x2 << (fp->index + CNIC_SUPPORT(sc)));
4576 if (status & mask) {
4577 bnx2x_handle_fp_tq(fp, scan_fp);
4582 if (unlikely(status & 0x1)) {
4583 rc = bnx2x_handle_sp_tq(sc);
4587 if (unlikely(status)) {
4588 PMD_DRV_LOG(WARNING,
4589 "Unexpected fastpath status (0x%08x)!", status);
4595 static int bnx2x_init_hw_common_chip(struct bnx2x_softc *sc);
4596 static int bnx2x_init_hw_common(struct bnx2x_softc *sc);
4597 static int bnx2x_init_hw_port(struct bnx2x_softc *sc);
4598 static int bnx2x_init_hw_func(struct bnx2x_softc *sc);
4599 static void bnx2x_reset_common(struct bnx2x_softc *sc);
4600 static void bnx2x_reset_port(struct bnx2x_softc *sc);
4601 static void bnx2x_reset_func(struct bnx2x_softc *sc);
4602 static int bnx2x_init_firmware(struct bnx2x_softc *sc);
4603 static void bnx2x_release_firmware(struct bnx2x_softc *sc);
4606 ecore_func_sp_drv_ops bnx2x_func_sp_drv = {
4607 .init_hw_cmn_chip = bnx2x_init_hw_common_chip,
4608 .init_hw_cmn = bnx2x_init_hw_common,
4609 .init_hw_port = bnx2x_init_hw_port,
4610 .init_hw_func = bnx2x_init_hw_func,
4612 .reset_hw_cmn = bnx2x_reset_common,
4613 .reset_hw_port = bnx2x_reset_port,
4614 .reset_hw_func = bnx2x_reset_func,
4616 .init_fw = bnx2x_init_firmware,
4617 .release_fw = bnx2x_release_firmware,
4620 static void bnx2x_init_func_obj(struct bnx2x_softc *sc)
4624 PMD_INIT_FUNC_TRACE();
4626 ecore_init_func_obj(sc,
4628 BNX2X_SP(sc, func_rdata),
4629 (phys_addr_t)BNX2X_SP_MAPPING(sc, func_rdata),
4630 BNX2X_SP(sc, func_afex_rdata),
4631 (phys_addr_t)BNX2X_SP_MAPPING(sc, func_afex_rdata),
4632 &bnx2x_func_sp_drv);
4635 static int bnx2x_init_hw(struct bnx2x_softc *sc, uint32_t load_code)
4637 struct ecore_func_state_params func_params = { NULL };
4640 PMD_INIT_FUNC_TRACE();
4642 /* prepare the parameters for function state transitions */
4643 bnx2x_set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags);
4645 func_params.f_obj = &sc->func_obj;
4646 func_params.cmd = ECORE_F_CMD_HW_INIT;
4648 func_params.params.hw_init.load_phase = load_code;
4651 * Via a plethora of function pointers, we will eventually reach
4652 * bnx2x_init_hw_common(), bnx2x_init_hw_port(), or bnx2x_init_hw_func().
4654 rc = ecore_func_state_change(sc, &func_params);
4660 bnx2x_fill(struct bnx2x_softc *sc, uint32_t addr, int fill, uint32_t len)
4664 if (!(len % 4) && !(addr % 4)) {
4665 for (i = 0; i < len; i += 4) {
4666 REG_WR(sc, (addr + i), fill);
4669 for (i = 0; i < len; i++) {
4670 REG_WR8(sc, (addr + i), fill);
4675 /* writes FP SP data to FW - data_size in dwords */
4677 bnx2x_wr_fp_sb_data(struct bnx2x_softc *sc, int fw_sb_id, uint32_t * sb_data_p,
4682 for (index = 0; index < data_size; index++) {
4684 (BAR_CSTRORM_INTMEM +
4685 CSTORM_STATUS_BLOCK_DATA_OFFSET(fw_sb_id) +
4686 (sizeof(uint32_t) * index)), *(sb_data_p + index));
4690 static void bnx2x_zero_fp_sb(struct bnx2x_softc *sc, int fw_sb_id)
4692 struct hc_status_block_data_e2 sb_data_e2;
4693 struct hc_status_block_data_e1x sb_data_e1x;
4694 uint32_t *sb_data_p;
4695 uint32_t data_size = 0;
4697 if (!CHIP_IS_E1x(sc)) {
4698 memset(&sb_data_e2, 0, sizeof(struct hc_status_block_data_e2));
4699 sb_data_e2.common.state = SB_DISABLED;
4700 sb_data_e2.common.p_func.vf_valid = FALSE;
4701 sb_data_p = (uint32_t *) & sb_data_e2;
4702 data_size = (sizeof(struct hc_status_block_data_e2) /
4705 memset(&sb_data_e1x, 0,
4706 sizeof(struct hc_status_block_data_e1x));
4707 sb_data_e1x.common.state = SB_DISABLED;
4708 sb_data_e1x.common.p_func.vf_valid = FALSE;
4709 sb_data_p = (uint32_t *) & sb_data_e1x;
4710 data_size = (sizeof(struct hc_status_block_data_e1x) /
4714 bnx2x_wr_fp_sb_data(sc, fw_sb_id, sb_data_p, data_size);
4717 (BAR_CSTRORM_INTMEM + CSTORM_STATUS_BLOCK_OFFSET(fw_sb_id)), 0,
4718 CSTORM_STATUS_BLOCK_SIZE);
4719 bnx2x_fill(sc, (BAR_CSTRORM_INTMEM + CSTORM_SYNC_BLOCK_OFFSET(fw_sb_id)),
4720 0, CSTORM_SYNC_BLOCK_SIZE);
4724 bnx2x_wr_sp_sb_data(struct bnx2x_softc *sc,
4725 struct hc_sp_status_block_data *sp_sb_data)
4730 i < (sizeof(struct hc_sp_status_block_data) / sizeof(uint32_t));
4733 (BAR_CSTRORM_INTMEM +
4734 CSTORM_SP_STATUS_BLOCK_DATA_OFFSET(SC_FUNC(sc)) +
4735 (i * sizeof(uint32_t))),
4736 *((uint32_t *) sp_sb_data + i));
4740 static void bnx2x_zero_sp_sb(struct bnx2x_softc *sc)
4742 struct hc_sp_status_block_data sp_sb_data;
4744 memset(&sp_sb_data, 0, sizeof(struct hc_sp_status_block_data));
4746 sp_sb_data.state = SB_DISABLED;
4747 sp_sb_data.p_func.vf_valid = FALSE;
4749 bnx2x_wr_sp_sb_data(sc, &sp_sb_data);
4752 (BAR_CSTRORM_INTMEM +
4753 CSTORM_SP_STATUS_BLOCK_OFFSET(SC_FUNC(sc))),
4754 0, CSTORM_SP_STATUS_BLOCK_SIZE);
4756 (BAR_CSTRORM_INTMEM +
4757 CSTORM_SP_SYNC_BLOCK_OFFSET(SC_FUNC(sc))),
4758 0, CSTORM_SP_SYNC_BLOCK_SIZE);
4762 bnx2x_setup_ndsb_state_machine(struct hc_status_block_sm *hc_sm, int igu_sb_id,
4765 hc_sm->igu_sb_id = igu_sb_id;
4766 hc_sm->igu_seg_id = igu_seg_id;
4767 hc_sm->timer_value = 0xFF;
4768 hc_sm->time_to_expire = 0xFFFFFFFF;
4771 static void bnx2x_map_sb_state_machines(struct hc_index_data *index_data)
4773 /* zero out state machine indices */
4776 index_data[HC_INDEX_ETH_RX_CQ_CONS].flags &= ~HC_INDEX_DATA_SM_ID;
4779 index_data[HC_INDEX_OOO_TX_CQ_CONS].flags &= ~HC_INDEX_DATA_SM_ID;
4780 index_data[HC_INDEX_ETH_TX_CQ_CONS_COS0].flags &= ~HC_INDEX_DATA_SM_ID;
4781 index_data[HC_INDEX_ETH_TX_CQ_CONS_COS1].flags &= ~HC_INDEX_DATA_SM_ID;
4782 index_data[HC_INDEX_ETH_TX_CQ_CONS_COS2].flags &= ~HC_INDEX_DATA_SM_ID;
4787 index_data[HC_INDEX_ETH_RX_CQ_CONS].flags |=
4788 (SM_RX_ID << HC_INDEX_DATA_SM_ID_SHIFT);
4791 index_data[HC_INDEX_OOO_TX_CQ_CONS].flags |=
4792 (SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT);
4793 index_data[HC_INDEX_ETH_TX_CQ_CONS_COS0].flags |=
4794 (SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT);
4795 index_data[HC_INDEX_ETH_TX_CQ_CONS_COS1].flags |=
4796 (SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT);
4797 index_data[HC_INDEX_ETH_TX_CQ_CONS_COS2].flags |=
4798 (SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT);
4802 bnx2x_init_sb(struct bnx2x_softc *sc, phys_addr_t busaddr, int vfid,
4803 uint8_t vf_valid, int fw_sb_id, int igu_sb_id)
4805 struct hc_status_block_data_e2 sb_data_e2;
4806 struct hc_status_block_data_e1x sb_data_e1x;
4807 struct hc_status_block_sm *hc_sm_p;
4808 uint32_t *sb_data_p;
4812 if (CHIP_INT_MODE_IS_BC(sc)) {
4813 igu_seg_id = HC_SEG_ACCESS_NORM;
4815 igu_seg_id = IGU_SEG_ACCESS_NORM;
4818 bnx2x_zero_fp_sb(sc, fw_sb_id);
4820 if (!CHIP_IS_E1x(sc)) {
4821 memset(&sb_data_e2, 0, sizeof(struct hc_status_block_data_e2));
4822 sb_data_e2.common.state = SB_ENABLED;
4823 sb_data_e2.common.p_func.pf_id = SC_FUNC(sc);
4824 sb_data_e2.common.p_func.vf_id = vfid;
4825 sb_data_e2.common.p_func.vf_valid = vf_valid;
4826 sb_data_e2.common.p_func.vnic_id = SC_VN(sc);
4827 sb_data_e2.common.same_igu_sb_1b = TRUE;
4828 sb_data_e2.common.host_sb_addr.hi = U64_HI(busaddr);
4829 sb_data_e2.common.host_sb_addr.lo = U64_LO(busaddr);
4830 hc_sm_p = sb_data_e2.common.state_machine;
4831 sb_data_p = (uint32_t *) & sb_data_e2;
4832 data_size = (sizeof(struct hc_status_block_data_e2) /
4834 bnx2x_map_sb_state_machines(sb_data_e2.index_data);
4836 memset(&sb_data_e1x, 0,
4837 sizeof(struct hc_status_block_data_e1x));
4838 sb_data_e1x.common.state = SB_ENABLED;
4839 sb_data_e1x.common.p_func.pf_id = SC_FUNC(sc);
4840 sb_data_e1x.common.p_func.vf_id = 0xff;
4841 sb_data_e1x.common.p_func.vf_valid = FALSE;
4842 sb_data_e1x.common.p_func.vnic_id = SC_VN(sc);
4843 sb_data_e1x.common.same_igu_sb_1b = TRUE;
4844 sb_data_e1x.common.host_sb_addr.hi = U64_HI(busaddr);
4845 sb_data_e1x.common.host_sb_addr.lo = U64_LO(busaddr);
4846 hc_sm_p = sb_data_e1x.common.state_machine;
4847 sb_data_p = (uint32_t *) & sb_data_e1x;
4848 data_size = (sizeof(struct hc_status_block_data_e1x) /
4850 bnx2x_map_sb_state_machines(sb_data_e1x.index_data);
4853 bnx2x_setup_ndsb_state_machine(&hc_sm_p[SM_RX_ID], igu_sb_id, igu_seg_id);
4854 bnx2x_setup_ndsb_state_machine(&hc_sm_p[SM_TX_ID], igu_sb_id, igu_seg_id);
4856 /* write indices to HW - PCI guarantees endianity of regpairs */
4857 bnx2x_wr_fp_sb_data(sc, fw_sb_id, sb_data_p, data_size);
4860 static uint8_t bnx2x_fp_qzone_id(struct bnx2x_fastpath *fp)
4862 if (CHIP_IS_E1x(fp->sc)) {
4863 return (fp->cl_id + SC_PORT(fp->sc) * ETH_MAX_RX_CLIENTS_E1H);
4870 bnx2x_rx_ustorm_prods_offset(struct bnx2x_softc *sc, struct bnx2x_fastpath *fp)
4872 uint32_t offset = BAR_USTRORM_INTMEM;
4875 return (PXP_VF_ADDR_USDM_QUEUES_START +
4876 (sc->acquire_resp.resc.hw_qid[fp->index] *
4877 sizeof(struct ustorm_queue_zone_data)));
4878 } else if (!CHIP_IS_E1x(sc)) {
4879 offset += USTORM_RX_PRODS_E2_OFFSET(fp->cl_qzone_id);
4881 offset += USTORM_RX_PRODS_E1X_OFFSET(SC_PORT(sc), fp->cl_id);
4887 static void bnx2x_init_eth_fp(struct bnx2x_softc *sc, int idx)
4889 struct bnx2x_fastpath *fp = &sc->fp[idx];
4890 uint32_t cids[ECORE_MULTI_TX_COS] = { 0 };
4891 unsigned long q_type = 0;
4897 fp->igu_sb_id = (sc->igu_base_sb + idx + CNIC_SUPPORT(sc));
4898 fp->fw_sb_id = (sc->base_fw_ndsb + idx + CNIC_SUPPORT(sc));
4900 if (CHIP_IS_E1x(sc))
4901 fp->cl_id = SC_L_ID(sc) + idx;
4903 /* want client ID same as IGU SB ID for non-E1 */
4904 fp->cl_id = fp->igu_sb_id;
4905 fp->cl_qzone_id = bnx2x_fp_qzone_id(fp);
4907 /* setup sb indices */
4908 if (!CHIP_IS_E1x(sc)) {
4909 fp->sb_index_values = fp->status_block.e2_sb->sb.index_values;
4910 fp->sb_running_index = fp->status_block.e2_sb->sb.running_index;
4912 fp->sb_index_values = fp->status_block.e1x_sb->sb.index_values;
4913 fp->sb_running_index =
4914 fp->status_block.e1x_sb->sb.running_index;
4918 fp->ustorm_rx_prods_offset = bnx2x_rx_ustorm_prods_offset(sc, fp);
4920 fp->rx_cq_cons_sb = &fp->sb_index_values[HC_INDEX_ETH_RX_CQ_CONS];
4922 for (cos = 0; cos < sc->max_cos; cos++) {
4925 fp->tx_cons_sb = &fp->sb_index_values[HC_INDEX_ETH_TX_CQ_CONS_COS0];
4927 /* nothing more for a VF to do */
4932 bnx2x_init_sb(sc, fp->sb_dma.paddr, BNX2X_VF_ID_INVALID, FALSE,
4933 fp->fw_sb_id, fp->igu_sb_id);
4935 bnx2x_update_fp_sb_idx(fp);
4937 /* Configure Queue State object */
4938 bnx2x_set_bit(ECORE_Q_TYPE_HAS_RX, &q_type);
4939 bnx2x_set_bit(ECORE_Q_TYPE_HAS_TX, &q_type);
4941 ecore_init_queue_obj(sc,
4942 &sc->sp_objs[idx].q_obj,
4947 BNX2X_SP(sc, q_rdata),
4948 (phys_addr_t)BNX2X_SP_MAPPING(sc, q_rdata),
4951 /* configure classification DBs */
4952 ecore_init_mac_obj(sc,
4953 &sc->sp_objs[idx].mac_obj,
4957 BNX2X_SP(sc, mac_rdata),
4958 (phys_addr_t)BNX2X_SP_MAPPING(sc, mac_rdata),
4959 ECORE_FILTER_MAC_PENDING, &sc->sp_state,
4960 ECORE_OBJ_TYPE_RX_TX, &sc->macs_pool);
4964 bnx2x_update_rx_prod(struct bnx2x_softc *sc, struct bnx2x_fastpath *fp,
4965 uint16_t rx_bd_prod, uint16_t rx_cq_prod)
4967 union ustorm_eth_rx_producers rx_prods;
4970 /* update producers */
4971 rx_prods.prod.bd_prod = rx_bd_prod;
4972 rx_prods.prod.cqe_prod = rx_cq_prod;
4973 rx_prods.prod.reserved = 0;
4976 * Make sure that the BD and SGE data is updated before updating the
4977 * producers since FW might read the BD/SGE right after the producer
4979 * This is only applicable for weak-ordered memory model archs such
4980 * as IA-64. The following barrier is also mandatory since FW will
4981 * assumes BDs must have buffers.
4985 for (i = 0; i < (sizeof(rx_prods) / 4); i++) {
4987 (fp->ustorm_rx_prods_offset + (i * 4)),
4988 rx_prods.raw_data[i]);
4991 wmb(); /* keep prod updates ordered */
4994 static void bnx2x_init_rx_rings(struct bnx2x_softc *sc)
4996 struct bnx2x_fastpath *fp;
4998 struct bnx2x_rx_queue *rxq;
5000 for (i = 0; i < sc->num_queues; i++) {
5002 rxq = sc->rx_queues[fp->index];
5004 PMD_RX_LOG(ERR, "RX queue is NULL");
5008 rxq->rx_bd_head = 0;
5009 rxq->rx_bd_tail = rxq->nb_rx_desc;
5010 rxq->rx_cq_head = 0;
5011 rxq->rx_cq_tail = TOTAL_RCQ_ENTRIES(rxq);
5012 *fp->rx_cq_cons_sb = 0;
5015 * Activate the BD ring...
5016 * Warning, this will generate an interrupt (to the TSTORM)
5017 * so this can only be done after the chip is initialized
5019 bnx2x_update_rx_prod(sc, fp, rxq->rx_bd_tail, rxq->rx_cq_tail);
5027 static void bnx2x_init_tx_ring_one(struct bnx2x_fastpath *fp)
5029 struct bnx2x_tx_queue *txq = fp->sc->tx_queues[fp->index];
5031 fp->tx_db.data.header.header = 1 << DOORBELL_HDR_DB_TYPE_SHIFT;
5032 fp->tx_db.data.zero_fill1 = 0;
5033 fp->tx_db.data.prod = 0;
5036 PMD_TX_LOG(ERR, "ERROR: TX queue is NULL");
5040 txq->tx_pkt_tail = 0;
5041 txq->tx_pkt_head = 0;
5042 txq->tx_bd_tail = 0;
5043 txq->tx_bd_head = 0;
5046 static void bnx2x_init_tx_rings(struct bnx2x_softc *sc)
5050 for (i = 0; i < sc->num_queues; i++) {
5051 bnx2x_init_tx_ring_one(&sc->fp[i]);
5055 static void bnx2x_init_def_sb(struct bnx2x_softc *sc)
5057 struct host_sp_status_block *def_sb = sc->def_sb;
5058 phys_addr_t mapping = sc->def_sb_dma.paddr;
5059 int igu_sp_sb_index;
5061 int port = SC_PORT(sc);
5062 int func = SC_FUNC(sc);
5063 int reg_offset, reg_offset_en5;
5066 struct hc_sp_status_block_data sp_sb_data;
5068 memset(&sp_sb_data, 0, sizeof(struct hc_sp_status_block_data));
5070 if (CHIP_INT_MODE_IS_BC(sc)) {
5071 igu_sp_sb_index = DEF_SB_IGU_ID;
5072 igu_seg_id = HC_SEG_ACCESS_DEF;
5074 igu_sp_sb_index = sc->igu_dsb_id;
5075 igu_seg_id = IGU_SEG_ACCESS_DEF;
5079 section = ((uint64_t) mapping +
5080 offsetof(struct host_sp_status_block, atten_status_block));
5081 def_sb->atten_status_block.status_block_id = igu_sp_sb_index;
5084 reg_offset = (port) ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 :
5085 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0;
5087 reg_offset_en5 = (port) ? MISC_REG_AEU_ENABLE5_FUNC_1_OUT_0 :
5088 MISC_REG_AEU_ENABLE5_FUNC_0_OUT_0;
5090 for (index = 0; index < MAX_DYNAMIC_ATTN_GRPS; index++) {
5091 /* take care of sig[0]..sig[4] */
5092 for (sindex = 0; sindex < 4; sindex++) {
5093 sc->attn_group[index].sig[sindex] =
5095 (reg_offset + (sindex * 0x4) +
5099 if (!CHIP_IS_E1x(sc)) {
5101 * enable5 is separate from the rest of the registers,
5102 * and the address skip is 4 and not 16 between the
5105 sc->attn_group[index].sig[4] =
5106 REG_RD(sc, (reg_offset_en5 + (0x4 * index)));
5108 sc->attn_group[index].sig[4] = 0;
5112 if (sc->devinfo.int_block == INT_BLOCK_HC) {
5114 port ? HC_REG_ATTN_MSG1_ADDR_L : HC_REG_ATTN_MSG0_ADDR_L;
5115 REG_WR(sc, reg_offset, U64_LO(section));
5116 REG_WR(sc, (reg_offset + 4), U64_HI(section));
5117 } else if (!CHIP_IS_E1x(sc)) {
5118 REG_WR(sc, IGU_REG_ATTN_MSG_ADDR_L, U64_LO(section));
5119 REG_WR(sc, IGU_REG_ATTN_MSG_ADDR_H, U64_HI(section));
5122 section = ((uint64_t) mapping +
5123 offsetof(struct host_sp_status_block, sp_sb));
5125 bnx2x_zero_sp_sb(sc);
5127 /* PCI guarantees endianity of regpair */
5128 sp_sb_data.state = SB_ENABLED;
5129 sp_sb_data.host_sb_addr.lo = U64_LO(section);
5130 sp_sb_data.host_sb_addr.hi = U64_HI(section);
5131 sp_sb_data.igu_sb_id = igu_sp_sb_index;
5132 sp_sb_data.igu_seg_id = igu_seg_id;
5133 sp_sb_data.p_func.pf_id = func;
5134 sp_sb_data.p_func.vnic_id = SC_VN(sc);
5135 sp_sb_data.p_func.vf_id = 0xff;
5137 bnx2x_wr_sp_sb_data(sc, &sp_sb_data);
5139 bnx2x_ack_sb(sc, sc->igu_dsb_id, USTORM_ID, 0, IGU_INT_ENABLE, 0);
5142 static void bnx2x_init_sp_ring(struct bnx2x_softc *sc)
5144 atomic_store_rel_long(&sc->cq_spq_left, MAX_SPQ_PENDING);
5145 sc->spq_prod_idx = 0;
5147 &sc->def_sb->sp_sb.index_values[HC_SP_INDEX_ETH_DEF_CONS];
5148 sc->spq_prod_bd = sc->spq;
5149 sc->spq_last_bd = (sc->spq_prod_bd + MAX_SP_DESC_CNT);
5152 static void bnx2x_init_eq_ring(struct bnx2x_softc *sc)
5154 union event_ring_elem *elem;
5157 for (i = 1; i <= NUM_EQ_PAGES; i++) {
5158 elem = &sc->eq[EQ_DESC_CNT_PAGE * i - 1];
5160 elem->next_page.addr.hi = htole32(U64_HI(sc->eq_dma.paddr +
5162 (i % NUM_EQ_PAGES)));
5163 elem->next_page.addr.lo = htole32(U64_LO(sc->eq_dma.paddr +
5165 (i % NUM_EQ_PAGES)));
5169 sc->eq_prod = NUM_EQ_DESC;
5170 sc->eq_cons_sb = &sc->def_sb->sp_sb.index_values[HC_SP_INDEX_EQ_CONS];
5172 atomic_store_rel_long(&sc->eq_spq_left,
5173 (min((MAX_SP_DESC_CNT - MAX_SPQ_PENDING),
5177 static void bnx2x_init_internal_common(struct bnx2x_softc *sc)
5183 * In switch independent mode, the TSTORM needs to accept
5184 * packets that failed classification, since approximate match
5185 * mac addresses aren't written to NIG LLH.
5188 (BAR_TSTRORM_INTMEM +
5189 TSTORM_ACCEPT_CLASSIFY_FAILED_OFFSET), 2);
5192 (BAR_TSTRORM_INTMEM +
5193 TSTORM_ACCEPT_CLASSIFY_FAILED_OFFSET), 0);
5196 * Zero this manually as its initialization is currently missing
5199 for (i = 0; i < (USTORM_AGG_DATA_SIZE >> 2); i++) {
5201 (BAR_USTRORM_INTMEM + USTORM_AGG_DATA_OFFSET + (i * 4)),
5205 if (!CHIP_IS_E1x(sc)) {
5206 REG_WR8(sc, (BAR_CSTRORM_INTMEM + CSTORM_IGU_MODE_OFFSET),
5207 CHIP_INT_MODE_IS_BC(sc) ? HC_IGU_BC_MODE :
5212 static void bnx2x_init_internal(struct bnx2x_softc *sc, uint32_t load_code)
5214 switch (load_code) {
5215 case FW_MSG_CODE_DRV_LOAD_COMMON:
5216 case FW_MSG_CODE_DRV_LOAD_COMMON_CHIP:
5217 bnx2x_init_internal_common(sc);
5220 case FW_MSG_CODE_DRV_LOAD_PORT:
5224 case FW_MSG_CODE_DRV_LOAD_FUNCTION:
5225 /* internal memory per function is initialized inside bnx2x_pf_init */
5229 PMD_DRV_LOG(NOTICE, "Unknown load_code (0x%x) from MCP",
5236 storm_memset_func_cfg(struct bnx2x_softc *sc,
5237 struct tstorm_eth_function_common_config *tcfg,
5243 addr = (BAR_TSTRORM_INTMEM +
5244 TSTORM_FUNCTION_COMMON_CONFIG_OFFSET(abs_fid));
5245 size = sizeof(struct tstorm_eth_function_common_config);
5246 ecore_storm_memset_struct(sc, addr, size, (uint32_t *) tcfg);
5249 static void bnx2x_func_init(struct bnx2x_softc *sc, struct bnx2x_func_init_params *p)
5251 struct tstorm_eth_function_common_config tcfg = { 0 };
5253 if (CHIP_IS_E1x(sc)) {
5254 storm_memset_func_cfg(sc, &tcfg, p->func_id);
5257 /* Enable the function in the FW */
5258 storm_memset_vf_to_pf(sc, p->func_id, p->pf_id);
5259 storm_memset_func_en(sc, p->func_id, 1);
5262 if (p->func_flgs & FUNC_FLG_SPQ) {
5263 storm_memset_spq_addr(sc, p->spq_map, p->func_id);
5265 (XSEM_REG_FAST_MEMORY +
5266 XSTORM_SPQ_PROD_OFFSET(p->func_id)), p->spq_prod);
5271 * Calculates the sum of vn_min_rates.
5272 * It's needed for further normalizing of the min_rates.
5274 * sum of vn_min_rates.
5276 * 0 - if all the min_rates are 0.
5277 * In the later case fainess algorithm should be deactivated.
5278 * If all min rates are not zero then those that are zeroes will be set to 1.
5280 static void bnx2x_calc_vn_min(struct bnx2x_softc *sc, struct cmng_init_input *input)
5283 uint32_t vn_min_rate;
5287 for (vn = VN_0; vn < SC_MAX_VN_NUM(sc); vn++) {
5288 vn_cfg = sc->devinfo.mf_info.mf_config[vn];
5289 vn_min_rate = (((vn_cfg & FUNC_MF_CFG_MIN_BW_MASK) >>
5290 FUNC_MF_CFG_MIN_BW_SHIFT) * 100);
5292 if (vn_cfg & FUNC_MF_CFG_FUNC_HIDE) {
5293 /* skip hidden VNs */
5295 } else if (!vn_min_rate) {
5296 /* If min rate is zero - set it to 100 */
5297 vn_min_rate = DEF_MIN_RATE;
5302 input->vnic_min_rate[vn] = vn_min_rate;
5305 /* if ETS or all min rates are zeros - disable fairness */
5307 input->flags.cmng_enables &= ~CMNG_FLAGS_PER_PORT_FAIRNESS_VN;
5309 input->flags.cmng_enables |= CMNG_FLAGS_PER_PORT_FAIRNESS_VN;
5314 bnx2x_extract_max_cfg(__rte_unused struct bnx2x_softc *sc, uint32_t mf_cfg)
5316 uint16_t max_cfg = ((mf_cfg & FUNC_MF_CFG_MAX_BW_MASK) >>
5317 FUNC_MF_CFG_MAX_BW_SHIFT);
5321 "Max BW configured to 0 - using 100 instead");
5329 bnx2x_calc_vn_max(struct bnx2x_softc *sc, int vn, struct cmng_init_input *input)
5331 uint16_t vn_max_rate;
5332 uint32_t vn_cfg = sc->devinfo.mf_info.mf_config[vn];
5335 if (vn_cfg & FUNC_MF_CFG_FUNC_HIDE) {
5338 max_cfg = bnx2x_extract_max_cfg(sc, vn_cfg);
5341 /* max_cfg in percents of linkspeed */
5343 ((sc->link_vars.line_speed * max_cfg) / 100);
5344 } else { /* SD modes */
5345 /* max_cfg is absolute in 100Mb units */
5346 vn_max_rate = (max_cfg * 100);
5350 input->vnic_max_rate[vn] = vn_max_rate;
5354 bnx2x_cmng_fns_init(struct bnx2x_softc *sc, uint8_t read_cfg, uint8_t cmng_type)
5356 struct cmng_init_input input;
5359 memset(&input, 0, sizeof(struct cmng_init_input));
5361 input.port_rate = sc->link_vars.line_speed;
5363 if (cmng_type == CMNG_FNS_MINMAX) {
5364 /* read mf conf from shmem */
5366 bnx2x_read_mf_cfg(sc);
5369 /* get VN min rate and enable fairness if not 0 */
5370 bnx2x_calc_vn_min(sc, &input);
5372 /* get VN max rate */
5374 for (vn = VN_0; vn < SC_MAX_VN_NUM(sc); vn++) {
5375 bnx2x_calc_vn_max(sc, vn, &input);
5379 /* always enable rate shaping and fairness */
5380 input.flags.cmng_enables |= CMNG_FLAGS_PER_PORT_RATE_SHAPING_VN;
5382 ecore_init_cmng(&input, &sc->cmng);
5387 static int bnx2x_get_cmng_fns_mode(struct bnx2x_softc *sc)
5389 if (CHIP_REV_IS_SLOW(sc)) {
5390 return CMNG_FNS_NONE;
5394 return CMNG_FNS_MINMAX;
5397 return CMNG_FNS_NONE;
5401 storm_memset_cmng(struct bnx2x_softc *sc, struct cmng_init *cmng, uint8_t port)
5408 addr = (BAR_XSTRORM_INTMEM + XSTORM_CMNG_PER_PORT_VARS_OFFSET(port));
5409 size = sizeof(struct cmng_struct_per_port);
5410 ecore_storm_memset_struct(sc, addr, size, (uint32_t *) & cmng->port);
5412 for (vn = VN_0; vn < SC_MAX_VN_NUM(sc); vn++) {
5413 func = func_by_vn(sc, vn);
5415 addr = (BAR_XSTRORM_INTMEM +
5416 XSTORM_RATE_SHAPING_PER_VN_VARS_OFFSET(func));
5417 size = sizeof(struct rate_shaping_vars_per_vn);
5418 ecore_storm_memset_struct(sc, addr, size,
5419 (uint32_t *) & cmng->
5420 vnic.vnic_max_rate[vn]);
5422 addr = (BAR_XSTRORM_INTMEM +
5423 XSTORM_FAIRNESS_PER_VN_VARS_OFFSET(func));
5424 size = sizeof(struct fairness_vars_per_vn);
5425 ecore_storm_memset_struct(sc, addr, size,
5426 (uint32_t *) & cmng->
5427 vnic.vnic_min_rate[vn]);
5431 static void bnx2x_pf_init(struct bnx2x_softc *sc)
5433 struct bnx2x_func_init_params func_init;
5434 struct event_ring_data eq_data;
5437 memset(&eq_data, 0, sizeof(struct event_ring_data));
5438 memset(&func_init, 0, sizeof(struct bnx2x_func_init_params));
5440 if (!CHIP_IS_E1x(sc)) {
5441 /* reset IGU PF statistics: MSIX + ATTN */
5444 (IGU_REG_STATISTIC_NUM_MESSAGE_SENT +
5445 (BNX2X_IGU_STAS_MSG_VF_CNT * 4) +
5446 ((CHIP_IS_MODE_4_PORT(sc) ? SC_FUNC(sc) : SC_VN(sc)) *
5450 (IGU_REG_STATISTIC_NUM_MESSAGE_SENT +
5451 (BNX2X_IGU_STAS_MSG_VF_CNT * 4) +
5452 (BNX2X_IGU_STAS_MSG_PF_CNT * 4) +
5453 ((CHIP_IS_MODE_4_PORT(sc) ? SC_FUNC(sc) : SC_VN(sc)) *
5457 /* function setup flags */
5458 flags = (FUNC_FLG_STATS | FUNC_FLG_LEADING | FUNC_FLG_SPQ);
5460 func_init.func_flgs = flags;
5461 func_init.pf_id = SC_FUNC(sc);
5462 func_init.func_id = SC_FUNC(sc);
5463 func_init.spq_map = sc->spq_dma.paddr;
5464 func_init.spq_prod = sc->spq_prod_idx;
5466 bnx2x_func_init(sc, &func_init);
5468 memset(&sc->cmng, 0, sizeof(struct cmng_struct_per_port));
5471 * Congestion management values depend on the link rate.
5472 * There is no active link so initial link rate is set to 10Gbps.
5473 * When the link comes up the congestion management values are
5474 * re-calculated according to the actual link rate.
5476 sc->link_vars.line_speed = SPEED_10000;
5477 bnx2x_cmng_fns_init(sc, TRUE, bnx2x_get_cmng_fns_mode(sc));
5479 /* Only the PMF sets the HW */
5481 storm_memset_cmng(sc, &sc->cmng, SC_PORT(sc));
5484 /* init Event Queue - PCI bus guarantees correct endainity */
5485 eq_data.base_addr.hi = U64_HI(sc->eq_dma.paddr);
5486 eq_data.base_addr.lo = U64_LO(sc->eq_dma.paddr);
5487 eq_data.producer = sc->eq_prod;
5488 eq_data.index_id = HC_SP_INDEX_EQ_CONS;
5489 eq_data.sb_id = DEF_SB_ID;
5490 storm_memset_eq_data(sc, &eq_data, SC_FUNC(sc));
5493 static void bnx2x_hc_int_enable(struct bnx2x_softc *sc)
5495 int port = SC_PORT(sc);
5496 uint32_t addr = (port) ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0;
5497 uint32_t val = REG_RD(sc, addr);
5498 uint8_t msix = (sc->interrupt_mode == INTR_MODE_MSIX)
5499 || (sc->interrupt_mode == INTR_MODE_SINGLE_MSIX);
5500 uint8_t single_msix = (sc->interrupt_mode == INTR_MODE_SINGLE_MSIX);
5501 uint8_t msi = (sc->interrupt_mode == INTR_MODE_MSI);
5504 val &= ~(HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
5505 HC_CONFIG_0_REG_INT_LINE_EN_0);
5506 val |= (HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
5507 HC_CONFIG_0_REG_ATTN_BIT_EN_0);
5509 val |= HC_CONFIG_0_REG_SINGLE_ISR_EN_0;
5512 val &= ~HC_CONFIG_0_REG_INT_LINE_EN_0;
5513 val |= (HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
5514 HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
5515 HC_CONFIG_0_REG_ATTN_BIT_EN_0);
5517 val |= (HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
5518 HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
5519 HC_CONFIG_0_REG_INT_LINE_EN_0 |
5520 HC_CONFIG_0_REG_ATTN_BIT_EN_0);
5522 REG_WR(sc, addr, val);
5524 val &= ~HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0;
5527 REG_WR(sc, addr, val);
5529 /* ensure that HC_CONFIG is written before leading/trailing edge config */
5532 /* init leading/trailing edge */
5534 val = (0xee0f | (1 << (SC_VN(sc) + 4)));
5536 /* enable nig and gpio3 attention */
5543 REG_WR(sc, (HC_REG_TRAILING_EDGE_0 + port * 8), val);
5544 REG_WR(sc, (HC_REG_LEADING_EDGE_0 + port * 8), val);
5546 /* make sure that interrupts are indeed enabled from here on */
5550 static void bnx2x_igu_int_enable(struct bnx2x_softc *sc)
5553 uint8_t msix = (sc->interrupt_mode == INTR_MODE_MSIX)
5554 || (sc->interrupt_mode == INTR_MODE_SINGLE_MSIX);
5555 uint8_t single_msix = (sc->interrupt_mode == INTR_MODE_SINGLE_MSIX);
5556 uint8_t msi = (sc->interrupt_mode == INTR_MODE_MSI);
5558 val = REG_RD(sc, IGU_REG_PF_CONFIGURATION);
5561 val &= ~(IGU_PF_CONF_INT_LINE_EN | IGU_PF_CONF_SINGLE_ISR_EN);
5562 val |= (IGU_PF_CONF_MSI_MSIX_EN | IGU_PF_CONF_ATTN_BIT_EN);
5564 val |= IGU_PF_CONF_SINGLE_ISR_EN;
5567 val &= ~IGU_PF_CONF_INT_LINE_EN;
5568 val |= (IGU_PF_CONF_MSI_MSIX_EN |
5569 IGU_PF_CONF_ATTN_BIT_EN | IGU_PF_CONF_SINGLE_ISR_EN);
5571 val &= ~IGU_PF_CONF_MSI_MSIX_EN;
5572 val |= (IGU_PF_CONF_INT_LINE_EN |
5573 IGU_PF_CONF_ATTN_BIT_EN | IGU_PF_CONF_SINGLE_ISR_EN);
5576 /* clean previous status - need to configure igu prior to ack */
5577 if ((!msix) || single_msix) {
5578 REG_WR(sc, IGU_REG_PF_CONFIGURATION, val);
5582 val |= IGU_PF_CONF_FUNC_EN;
5584 PMD_DRV_LOG(DEBUG, "write 0x%x to IGU mode %s",
5585 val, ((msix) ? "MSI-X" : ((msi) ? "MSI" : "INTx")));
5587 REG_WR(sc, IGU_REG_PF_CONFIGURATION, val);
5591 /* init leading/trailing edge */
5593 val = (0xee0f | (1 << (SC_VN(sc) + 4)));
5595 /* enable nig and gpio3 attention */
5602 REG_WR(sc, IGU_REG_TRAILING_EDGE_LATCH, val);
5603 REG_WR(sc, IGU_REG_LEADING_EDGE_LATCH, val);
5605 /* make sure that interrupts are indeed enabled from here on */
5609 static void bnx2x_int_enable(struct bnx2x_softc *sc)
5611 if (sc->devinfo.int_block == INT_BLOCK_HC) {
5612 bnx2x_hc_int_enable(sc);
5614 bnx2x_igu_int_enable(sc);
5618 static void bnx2x_hc_int_disable(struct bnx2x_softc *sc)
5620 int port = SC_PORT(sc);
5621 uint32_t addr = (port) ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0;
5622 uint32_t val = REG_RD(sc, addr);
5624 val &= ~(HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
5625 HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
5626 HC_CONFIG_0_REG_INT_LINE_EN_0 | HC_CONFIG_0_REG_ATTN_BIT_EN_0);
5627 /* flush all outstanding writes */
5630 REG_WR(sc, addr, val);
5631 if (REG_RD(sc, addr) != val) {
5632 PMD_DRV_LOG(ERR, "proper val not read from HC IGU!");
5636 static void bnx2x_igu_int_disable(struct bnx2x_softc *sc)
5638 uint32_t val = REG_RD(sc, IGU_REG_PF_CONFIGURATION);
5640 val &= ~(IGU_PF_CONF_MSI_MSIX_EN |
5641 IGU_PF_CONF_INT_LINE_EN | IGU_PF_CONF_ATTN_BIT_EN);
5643 PMD_DRV_LOG(DEBUG, "write %x to IGU", val);
5645 /* flush all outstanding writes */
5648 REG_WR(sc, IGU_REG_PF_CONFIGURATION, val);
5649 if (REG_RD(sc, IGU_REG_PF_CONFIGURATION) != val) {
5650 PMD_DRV_LOG(ERR, "proper val not read from IGU!");
5654 static void bnx2x_int_disable(struct bnx2x_softc *sc)
5656 if (sc->devinfo.int_block == INT_BLOCK_HC) {
5657 bnx2x_hc_int_disable(sc);
5659 bnx2x_igu_int_disable(sc);
5663 static void bnx2x_nic_init(struct bnx2x_softc *sc, int load_code)
5667 PMD_INIT_FUNC_TRACE();
5669 for (i = 0; i < sc->num_queues; i++) {
5670 bnx2x_init_eth_fp(sc, i);
5673 rmb(); /* ensure status block indices were read */
5675 bnx2x_init_rx_rings(sc);
5676 bnx2x_init_tx_rings(sc);
5679 bnx2x_memset_stats(sc);
5683 /* initialize MOD_ABS interrupts */
5684 elink_init_mod_abs_int(sc, &sc->link_vars,
5685 sc->devinfo.chip_id,
5686 sc->devinfo.shmem_base,
5687 sc->devinfo.shmem2_base, SC_PORT(sc));
5689 bnx2x_init_def_sb(sc);
5690 bnx2x_update_dsb_idx(sc);
5691 bnx2x_init_sp_ring(sc);
5692 bnx2x_init_eq_ring(sc);
5693 bnx2x_init_internal(sc, load_code);
5695 bnx2x_stats_init(sc);
5697 /* flush all before enabling interrupts */
5700 bnx2x_int_enable(sc);
5702 /* check for SPIO5 */
5703 bnx2x_attn_int_deasserted0(sc,
5705 (MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 +
5707 AEU_INPUTS_ATTN_BITS_SPIO5);
5710 static void bnx2x_init_objs(struct bnx2x_softc *sc)
5712 /* mcast rules must be added to tx if tx switching is enabled */
5713 ecore_obj_type o_type;
5714 if (sc->flags & BNX2X_TX_SWITCHING)
5715 o_type = ECORE_OBJ_TYPE_RX_TX;
5717 o_type = ECORE_OBJ_TYPE_RX;
5719 /* RX_MODE controlling object */
5720 ecore_init_rx_mode_obj(sc, &sc->rx_mode_obj);
5722 /* multicast configuration controlling object */
5723 ecore_init_mcast_obj(sc,
5729 BNX2X_SP(sc, mcast_rdata),
5730 (phys_addr_t)BNX2X_SP_MAPPING(sc, mcast_rdata),
5731 ECORE_FILTER_MCAST_PENDING,
5732 &sc->sp_state, o_type);
5734 /* Setup CAM credit pools */
5735 ecore_init_mac_credit_pool(sc,
5738 CHIP_IS_E1x(sc) ? VNICS_PER_PORT(sc) :
5739 VNICS_PER_PATH(sc));
5741 ecore_init_vlan_credit_pool(sc,
5743 SC_ABS_FUNC(sc) >> 1,
5744 CHIP_IS_E1x(sc) ? VNICS_PER_PORT(sc) :
5745 VNICS_PER_PATH(sc));
5747 /* RSS configuration object */
5748 ecore_init_rss_config_obj(&sc->rss_conf_obj,
5753 BNX2X_SP(sc, rss_rdata),
5754 (phys_addr_t)BNX2X_SP_MAPPING(sc, rss_rdata),
5755 ECORE_FILTER_RSS_CONF_PENDING,
5756 &sc->sp_state, ECORE_OBJ_TYPE_RX);
5760 * Initialize the function. This must be called before sending CLIENT_SETUP
5761 * for the first client.
5763 static int bnx2x_func_start(struct bnx2x_softc *sc)
5765 struct ecore_func_state_params func_params = { NULL };
5766 struct ecore_func_start_params *start_params =
5767 &func_params.params.start;
5769 /* Prepare parameters for function state transitions */
5770 bnx2x_set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags);
5772 func_params.f_obj = &sc->func_obj;
5773 func_params.cmd = ECORE_F_CMD_START;
5775 /* Function parameters */
5776 start_params->mf_mode = sc->devinfo.mf_info.mf_mode;
5777 start_params->sd_vlan_tag = OVLAN(sc);
5779 if (CHIP_IS_E2(sc) || CHIP_IS_E3(sc)) {
5780 start_params->network_cos_mode = STATIC_COS;
5781 } else { /* CHIP_IS_E1X */
5782 start_params->network_cos_mode = FW_WRR;
5785 start_params->gre_tunnel_mode = 0;
5786 start_params->gre_tunnel_rss = 0;
5788 return ecore_func_state_change(sc, &func_params);
5791 static int bnx2x_set_power_state(struct bnx2x_softc *sc, uint8_t state)
5795 /* If there is no power capability, silently succeed */
5796 if (!(sc->devinfo.pcie_cap_flags & BNX2X_PM_CAPABLE_FLAG)) {
5797 PMD_DRV_LOG(WARNING, "No power capability");
5801 pci_read(sc, (sc->devinfo.pcie_pm_cap_reg + PCIR_POWER_STATUS), &pmcsr,
5807 (sc->devinfo.pcie_pm_cap_reg +
5809 ((pmcsr & ~PCIM_PSTAT_DMASK) | PCIM_PSTAT_PME));
5811 if (pmcsr & PCIM_PSTAT_DMASK) {
5812 /* delay required during transition out of D3hot */
5819 /* don't shut down the power for emulation and FPGA */
5820 if (CHIP_REV_IS_SLOW(sc)) {
5824 pmcsr &= ~PCIM_PSTAT_DMASK;
5825 pmcsr |= PCIM_PSTAT_D3;
5828 pmcsr |= PCIM_PSTAT_PMEENABLE;
5832 (sc->devinfo.pcie_pm_cap_reg +
5833 PCIR_POWER_STATUS), pmcsr);
5836 * No more memory access after this point until device is brought back
5842 PMD_DRV_LOG(NOTICE, "Can't support PCI power state = %d",
5850 /* return true if succeeded to acquire the lock */
5851 static uint8_t bnx2x_trylock_hw_lock(struct bnx2x_softc *sc, uint32_t resource)
5853 uint32_t lock_status;
5854 uint32_t resource_bit = (1 << resource);
5855 int func = SC_FUNC(sc);
5856 uint32_t hw_lock_control_reg;
5858 /* Validating that the resource is within range */
5859 if (resource > HW_LOCK_MAX_RESOURCE_VALUE) {
5861 "resource(0x%x) > HW_LOCK_MAX_RESOURCE_VALUE(0x%x)",
5862 resource, HW_LOCK_MAX_RESOURCE_VALUE);
5867 hw_lock_control_reg = (MISC_REG_DRIVER_CONTROL_1 + func * 8);
5869 hw_lock_control_reg =
5870 (MISC_REG_DRIVER_CONTROL_7 + (func - 6) * 8);
5873 /* try to acquire the lock */
5874 REG_WR(sc, hw_lock_control_reg + 4, resource_bit);
5875 lock_status = REG_RD(sc, hw_lock_control_reg);
5876 if (lock_status & resource_bit) {
5880 PMD_DRV_LOG(NOTICE, "Failed to get a resource lock 0x%x", resource);
5886 * Get the recovery leader resource id according to the engine this function
5887 * belongs to. Currently only only 2 engines is supported.
5889 static int bnx2x_get_leader_lock_resource(struct bnx2x_softc *sc)
5892 return HW_LOCK_RESOURCE_RECOVERY_LEADER_1;
5894 return HW_LOCK_RESOURCE_RECOVERY_LEADER_0;
5898 /* try to acquire a leader lock for current engine */
5899 static uint8_t bnx2x_trylock_leader_lock(struct bnx2x_softc *sc)
5901 return bnx2x_trylock_hw_lock(sc, bnx2x_get_leader_lock_resource(sc));
5904 static int bnx2x_release_leader_lock(struct bnx2x_softc *sc)
5906 return bnx2x_release_hw_lock(sc, bnx2x_get_leader_lock_resource(sc));
5909 /* close gates #2, #3 and #4 */
5910 static void bnx2x_set_234_gates(struct bnx2x_softc *sc, uint8_t close)
5914 /* gates #2 and #4a are closed/opened */
5916 REG_WR(sc, PXP_REG_HST_DISCARD_DOORBELLS, ! !close);
5918 REG_WR(sc, PXP_REG_HST_DISCARD_INTERNAL_WRITES, ! !close);
5921 if (CHIP_IS_E1x(sc)) {
5922 /* prevent interrupts from HC on both ports */
5923 val = REG_RD(sc, HC_REG_CONFIG_1);
5925 REG_WR(sc, HC_REG_CONFIG_1, (val & ~(uint32_t)
5926 HC_CONFIG_1_REG_BLOCK_DISABLE_1));
5928 REG_WR(sc, HC_REG_CONFIG_1,
5929 (val | HC_CONFIG_1_REG_BLOCK_DISABLE_1));
5931 val = REG_RD(sc, HC_REG_CONFIG_0);
5933 REG_WR(sc, HC_REG_CONFIG_0, (val & ~(uint32_t)
5934 HC_CONFIG_0_REG_BLOCK_DISABLE_0));
5936 REG_WR(sc, HC_REG_CONFIG_0,
5937 (val | HC_CONFIG_0_REG_BLOCK_DISABLE_0));
5940 /* Prevent incomming interrupts in IGU */
5941 val = REG_RD(sc, IGU_REG_BLOCK_CONFIGURATION);
5944 REG_WR(sc, IGU_REG_BLOCK_CONFIGURATION,
5946 IGU_BLOCK_CONFIGURATION_REG_BLOCK_ENABLE));
5948 REG_WR(sc, IGU_REG_BLOCK_CONFIGURATION,
5950 IGU_BLOCK_CONFIGURATION_REG_BLOCK_ENABLE));
5956 /* poll for pending writes bit, it should get cleared in no more than 1s */
5957 static int bnx2x_er_poll_igu_vq(struct bnx2x_softc *sc)
5959 uint32_t cnt = 1000;
5960 uint32_t pend_bits = 0;
5963 pend_bits = REG_RD(sc, IGU_REG_PENDING_BITS_STATUS);
5965 if (pend_bits == 0) {
5970 } while (cnt-- > 0);
5973 PMD_DRV_LOG(NOTICE, "Still pending IGU requests bits=0x%08x!",
5981 #define SHARED_MF_CLP_MAGIC 0x80000000 /* 'magic' bit */
5983 static void bnx2x_clp_reset_prep(struct bnx2x_softc *sc, uint32_t * magic_val)
5985 /* Do some magic... */
5986 uint32_t val = MFCFG_RD(sc, shared_mf_config.clp_mb);
5987 *magic_val = val & SHARED_MF_CLP_MAGIC;
5988 MFCFG_WR(sc, shared_mf_config.clp_mb, val | SHARED_MF_CLP_MAGIC);
5991 /* restore the value of the 'magic' bit */
5992 static void bnx2x_clp_reset_done(struct bnx2x_softc *sc, uint32_t magic_val)
5994 /* Restore the 'magic' bit value... */
5995 uint32_t val = MFCFG_RD(sc, shared_mf_config.clp_mb);
5996 MFCFG_WR(sc, shared_mf_config.clp_mb,
5997 (val & (~SHARED_MF_CLP_MAGIC)) | magic_val);
6000 /* prepare for MCP reset, takes care of CLP configurations */
6001 static void bnx2x_reset_mcp_prep(struct bnx2x_softc *sc, uint32_t * magic_val)
6004 uint32_t validity_offset;
6006 /* set `magic' bit in order to save MF config */
6007 bnx2x_clp_reset_prep(sc, magic_val);
6009 /* get shmem offset */
6010 shmem = REG_RD(sc, MISC_REG_SHARED_MEM_ADDR);
6012 offsetof(struct shmem_region, validity_map[SC_PORT(sc)]);
6014 /* Clear validity map flags */
6016 REG_WR(sc, shmem + validity_offset, 0);
6020 #define MCP_TIMEOUT 5000 /* 5 seconds (in ms) */
6021 #define MCP_ONE_TIMEOUT 100 /* 100 ms */
6023 static void bnx2x_mcp_wait_one(struct bnx2x_softc *sc)
6025 /* special handling for emulation and FPGA (10 times longer) */
6026 if (CHIP_REV_IS_SLOW(sc)) {
6027 DELAY((MCP_ONE_TIMEOUT * 10) * 1000);
6029 DELAY((MCP_ONE_TIMEOUT) * 1000);
6033 /* initialize shmem_base and waits for validity signature to appear */
6034 static int bnx2x_init_shmem(struct bnx2x_softc *sc)
6040 sc->devinfo.shmem_base =
6041 sc->link_params.shmem_base =
6042 REG_RD(sc, MISC_REG_SHARED_MEM_ADDR);
6044 if (sc->devinfo.shmem_base) {
6045 val = SHMEM_RD(sc, validity_map[SC_PORT(sc)]);
6046 if (val & SHR_MEM_VALIDITY_MB)
6050 bnx2x_mcp_wait_one(sc);
6052 } while (cnt++ < (MCP_TIMEOUT / MCP_ONE_TIMEOUT));
6054 PMD_DRV_LOG(NOTICE, "BAD MCP validity signature");
6059 static int bnx2x_reset_mcp_comp(struct bnx2x_softc *sc, uint32_t magic_val)
6061 int rc = bnx2x_init_shmem(sc);
6063 /* Restore the `magic' bit value */
6064 bnx2x_clp_reset_done(sc, magic_val);
6069 static void bnx2x_pxp_prep(struct bnx2x_softc *sc)
6071 REG_WR(sc, PXP2_REG_RD_START_INIT, 0);
6072 REG_WR(sc, PXP2_REG_RQ_RBC_DONE, 0);
6077 * Reset the whole chip except for:
6079 * - PCI Glue, PSWHST, PXP/PXP2 RF (all controlled by one reset bit)
6081 * - MISC (including AEU)
6085 static void bnx2x_process_kill_chip_reset(struct bnx2x_softc *sc, uint8_t global)
6087 uint32_t not_reset_mask1, reset_mask1, not_reset_mask2, reset_mask2;
6088 uint32_t global_bits2, stay_reset2;
6091 * Bits that have to be set in reset_mask2 if we want to reset 'global'
6092 * (per chip) blocks.
6095 MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_CMN_CPU |
6096 MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_CMN_CORE;
6099 * Don't reset the following blocks.
6100 * Important: per port blocks (such as EMAC, BMAC, UMAC) can't be
6101 * reset, as in 4 port device they might still be owned
6102 * by the MCP (there is only one leader per path).
6105 MISC_REGISTERS_RESET_REG_1_RST_HC |
6106 MISC_REGISTERS_RESET_REG_1_RST_PXPV |
6107 MISC_REGISTERS_RESET_REG_1_RST_PXP;
6110 MISC_REGISTERS_RESET_REG_2_RST_PCI_MDIO |
6111 MISC_REGISTERS_RESET_REG_2_RST_EMAC0_HARD_CORE |
6112 MISC_REGISTERS_RESET_REG_2_RST_EMAC1_HARD_CORE |
6113 MISC_REGISTERS_RESET_REG_2_RST_MISC_CORE |
6114 MISC_REGISTERS_RESET_REG_2_RST_RBCN |
6115 MISC_REGISTERS_RESET_REG_2_RST_GRC |
6116 MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_REG_HARD_CORE |
6117 MISC_REGISTERS_RESET_REG_2_RST_MCP_N_HARD_CORE_RST_B |
6118 MISC_REGISTERS_RESET_REG_2_RST_ATC |
6119 MISC_REGISTERS_RESET_REG_2_PGLC |
6120 MISC_REGISTERS_RESET_REG_2_RST_BMAC0 |
6121 MISC_REGISTERS_RESET_REG_2_RST_BMAC1 |
6122 MISC_REGISTERS_RESET_REG_2_RST_EMAC0 |
6123 MISC_REGISTERS_RESET_REG_2_RST_EMAC1 |
6124 MISC_REGISTERS_RESET_REG_2_UMAC0 | MISC_REGISTERS_RESET_REG_2_UMAC1;
6127 * Keep the following blocks in reset:
6128 * - all xxMACs are handled by the elink code.
6131 MISC_REGISTERS_RESET_REG_2_XMAC |
6132 MISC_REGISTERS_RESET_REG_2_XMAC_SOFT;
6134 /* Full reset masks according to the chip */
6135 reset_mask1 = 0xffffffff;
6137 if (CHIP_IS_E1H(sc))
6138 reset_mask2 = 0x1ffff;
6139 else if (CHIP_IS_E2(sc))
6140 reset_mask2 = 0xfffff;
6141 else /* CHIP_IS_E3 */
6142 reset_mask2 = 0x3ffffff;
6144 /* Don't reset global blocks unless we need to */
6146 reset_mask2 &= ~global_bits2;
6149 * In case of attention in the QM, we need to reset PXP
6150 * (MISC_REGISTERS_RESET_REG_2_RST_PXP_RQ_RD_WR) before QM
6151 * because otherwise QM reset would release 'close the gates' shortly
6152 * before resetting the PXP, then the PSWRQ would send a write
6153 * request to PGLUE. Then when PXP is reset, PGLUE would try to
6154 * read the payload data from PSWWR, but PSWWR would not
6155 * respond. The write queue in PGLUE would stuck, dmae commands
6156 * would not return. Therefore it's important to reset the second
6157 * reset register (containing the
6158 * MISC_REGISTERS_RESET_REG_2_RST_PXP_RQ_RD_WR bit) before the
6159 * first one (containing the MISC_REGISTERS_RESET_REG_1_RST_QM
6162 REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
6163 reset_mask2 & (~not_reset_mask2));
6165 REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR,
6166 reset_mask1 & (~not_reset_mask1));
6171 REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET,
6172 reset_mask2 & (~stay_reset2));
6177 REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, reset_mask1);
6181 static int bnx2x_process_kill(struct bnx2x_softc *sc, uint8_t global)
6185 uint32_t sr_cnt, blk_cnt, port_is_idle_0, port_is_idle_1, pgl_exp_rom2;
6186 uint32_t tags_63_32 = 0;
6188 /* Empty the Tetris buffer, wait for 1s */
6190 sr_cnt = REG_RD(sc, PXP2_REG_RD_SR_CNT);
6191 blk_cnt = REG_RD(sc, PXP2_REG_RD_BLK_CNT);
6192 port_is_idle_0 = REG_RD(sc, PXP2_REG_RD_PORT_IS_IDLE_0);
6193 port_is_idle_1 = REG_RD(sc, PXP2_REG_RD_PORT_IS_IDLE_1);
6194 pgl_exp_rom2 = REG_RD(sc, PXP2_REG_PGL_EXP_ROM2);
6195 if (CHIP_IS_E3(sc)) {
6196 tags_63_32 = REG_RD(sc, PGLUE_B_REG_TAGS_63_32);
6199 if ((sr_cnt == 0x7e) && (blk_cnt == 0xa0) &&
6200 ((port_is_idle_0 & 0x1) == 0x1) &&
6201 ((port_is_idle_1 & 0x1) == 0x1) &&
6202 (pgl_exp_rom2 == 0xffffffff) &&
6203 (!CHIP_IS_E3(sc) || (tags_63_32 == 0xffffffff)))
6206 } while (cnt-- > 0);
6210 "ERROR: Tetris buffer didn't get empty or there "
6211 "are still outstanding read requests after 1s! "
6212 "sr_cnt=0x%08x, blk_cnt=0x%08x, port_is_idle_0=0x%08x, "
6213 "port_is_idle_1=0x%08x, pgl_exp_rom2=0x%08x",
6214 sr_cnt, blk_cnt, port_is_idle_0, port_is_idle_1,
6221 /* Close gates #2, #3 and #4 */
6222 bnx2x_set_234_gates(sc, TRUE);
6224 /* Poll for IGU VQs for 57712 and newer chips */
6225 if (!CHIP_IS_E1x(sc) && bnx2x_er_poll_igu_vq(sc)) {
6229 /* clear "unprepared" bit */
6230 REG_WR(sc, MISC_REG_UNPREPARED, 0);
6233 /* Make sure all is written to the chip before the reset */
6237 * Wait for 1ms to empty GLUE and PCI-E core queues,
6238 * PSWHST, GRC and PSWRD Tetris buffer.
6242 /* Prepare to chip reset: */
6245 bnx2x_reset_mcp_prep(sc, &val);
6252 /* reset the chip */
6253 bnx2x_process_kill_chip_reset(sc, global);
6256 /* Recover after reset: */
6258 if (global && bnx2x_reset_mcp_comp(sc, val)) {
6262 /* Open the gates #2, #3 and #4 */
6263 bnx2x_set_234_gates(sc, FALSE);
6268 static int bnx2x_leader_reset(struct bnx2x_softc *sc)
6271 uint8_t global = bnx2x_reset_is_global(sc);
6275 * If not going to reset MCP, load "fake" driver to reset HW while
6276 * driver is owner of the HW.
6278 if (!global && !BNX2X_NOMCP(sc)) {
6279 load_code = bnx2x_fw_command(sc, DRV_MSG_CODE_LOAD_REQ,
6280 DRV_MSG_CODE_LOAD_REQ_WITH_LFA);
6282 PMD_DRV_LOG(NOTICE, "MCP response failure, aborting");
6284 goto exit_leader_reset;
6287 if ((load_code != FW_MSG_CODE_DRV_LOAD_COMMON_CHIP) &&
6288 (load_code != FW_MSG_CODE_DRV_LOAD_COMMON)) {
6290 "MCP unexpected response, aborting");
6292 goto exit_leader_reset2;
6295 load_code = bnx2x_fw_command(sc, DRV_MSG_CODE_LOAD_DONE, 0);
6297 PMD_DRV_LOG(NOTICE, "MCP response failure, aborting");
6299 goto exit_leader_reset2;
6303 /* try to recover after the failure */
6304 if (bnx2x_process_kill(sc, global)) {
6305 PMD_DRV_LOG(NOTICE, "Something bad occurred on engine %d!",
6308 goto exit_leader_reset2;
6312 * Clear the RESET_IN_PROGRESS and RESET_GLOBAL bits and update the driver
6315 bnx2x_set_reset_done(sc);
6317 bnx2x_clear_reset_global(sc);
6322 /* unload "fake driver" if it was loaded */
6323 if (!global &&!BNX2X_NOMCP(sc)) {
6324 bnx2x_fw_command(sc, DRV_MSG_CODE_UNLOAD_REQ_WOL_MCP, 0);
6325 bnx2x_fw_command(sc, DRV_MSG_CODE_UNLOAD_DONE, 0);
6331 bnx2x_release_leader_lock(sc);
6338 * prepare INIT transition, parameters configured:
6339 * - HC configuration
6340 * - Queue's CDU context
6343 bnx2x_pf_q_prep_init(struct bnx2x_softc *sc, struct bnx2x_fastpath *fp,
6344 struct ecore_queue_init_params *init_params)
6347 int cxt_index, cxt_offset;
6349 bnx2x_set_bit(ECORE_Q_FLG_HC, &init_params->rx.flags);
6350 bnx2x_set_bit(ECORE_Q_FLG_HC, &init_params->tx.flags);
6352 bnx2x_set_bit(ECORE_Q_FLG_HC_EN, &init_params->rx.flags);
6353 bnx2x_set_bit(ECORE_Q_FLG_HC_EN, &init_params->tx.flags);
6356 init_params->rx.hc_rate =
6357 sc->hc_rx_ticks ? (1000000 / sc->hc_rx_ticks) : 0;
6358 init_params->tx.hc_rate =
6359 sc->hc_tx_ticks ? (1000000 / sc->hc_tx_ticks) : 0;
6362 init_params->rx.fw_sb_id = init_params->tx.fw_sb_id = fp->fw_sb_id;
6364 /* CQ index among the SB indices */
6365 init_params->rx.sb_cq_index = HC_INDEX_ETH_RX_CQ_CONS;
6366 init_params->tx.sb_cq_index = HC_INDEX_ETH_FIRST_TX_CQ_CONS;
6368 /* set maximum number of COSs supported by this queue */
6369 init_params->max_cos = sc->max_cos;
6371 /* set the context pointers queue object */
6372 for (cos = FIRST_TX_COS_INDEX; cos < init_params->max_cos; cos++) {
6373 cxt_index = fp->index / ILT_PAGE_CIDS;
6374 cxt_offset = fp->index - (cxt_index * ILT_PAGE_CIDS);
6375 init_params->cxts[cos] =
6376 &sc->context[cxt_index].vcxt[cxt_offset].eth;
6380 /* set flags that are common for the Tx-only and not normal connections */
6381 static unsigned long
6382 bnx2x_get_common_flags(struct bnx2x_softc *sc, uint8_t zero_stats)
6384 unsigned long flags = 0;
6386 /* PF driver will always initialize the Queue to an ACTIVE state */
6387 bnx2x_set_bit(ECORE_Q_FLG_ACTIVE, &flags);
6390 * tx only connections collect statistics (on the same index as the
6391 * parent connection). The statistics are zeroed when the parent
6392 * connection is initialized.
6395 bnx2x_set_bit(ECORE_Q_FLG_STATS, &flags);
6397 bnx2x_set_bit(ECORE_Q_FLG_ZERO_STATS, &flags);
6401 * tx only connections can support tx-switching, though their
6402 * CoS-ness doesn't survive the loopback
6404 if (sc->flags & BNX2X_TX_SWITCHING) {
6405 bnx2x_set_bit(ECORE_Q_FLG_TX_SWITCH, &flags);
6408 bnx2x_set_bit(ECORE_Q_FLG_PCSUM_ON_PKT, &flags);
6413 static unsigned long bnx2x_get_q_flags(struct bnx2x_softc *sc, uint8_t leading)
6415 unsigned long flags = 0;
6418 bnx2x_set_bit(ECORE_Q_FLG_OV, &flags);
6422 bnx2x_set_bit(ECORE_Q_FLG_LEADING_RSS, &flags);
6423 bnx2x_set_bit(ECORE_Q_FLG_MCAST, &flags);
6426 bnx2x_set_bit(ECORE_Q_FLG_VLAN, &flags);
6428 /* merge with common flags */
6429 return flags | bnx2x_get_common_flags(sc, TRUE);
6433 bnx2x_pf_q_prep_general(struct bnx2x_softc *sc, struct bnx2x_fastpath *fp,
6434 struct ecore_general_setup_params *gen_init, uint8_t cos)
6436 gen_init->stat_id = bnx2x_stats_id(fp);
6437 gen_init->spcl_id = fp->cl_id;
6438 gen_init->mtu = sc->mtu;
6439 gen_init->cos = cos;
6443 bnx2x_pf_rx_q_prep(struct bnx2x_softc *sc, struct bnx2x_fastpath *fp,
6444 struct rxq_pause_params *pause,
6445 struct ecore_rxq_setup_params *rxq_init)
6447 struct bnx2x_rx_queue *rxq;
6449 rxq = sc->rx_queues[fp->index];
6451 PMD_RX_LOG(ERR, "RX queue is NULL");
6455 pause->bd_th_lo = BD_TH_LO(sc);
6456 pause->bd_th_hi = BD_TH_HI(sc);
6458 pause->rcq_th_lo = RCQ_TH_LO(sc);
6459 pause->rcq_th_hi = RCQ_TH_HI(sc);
6461 /* validate rings have enough entries to cross high thresholds */
6462 if (sc->dropless_fc &&
6463 pause->bd_th_hi + FW_PREFETCH_CNT > sc->rx_ring_size) {
6464 PMD_DRV_LOG(WARNING, "rx bd ring threshold limit");
6467 if (sc->dropless_fc &&
6468 pause->rcq_th_hi + FW_PREFETCH_CNT > USABLE_RCQ_ENTRIES(rxq)) {
6469 PMD_DRV_LOG(WARNING, "rcq ring threshold limit");
6475 rxq_init->dscr_map = (phys_addr_t)rxq->rx_ring_phys_addr;
6476 rxq_init->rcq_map = (phys_addr_t)rxq->cq_ring_phys_addr;
6477 rxq_init->rcq_np_map = (phys_addr_t)(rxq->cq_ring_phys_addr +
6481 * This should be a maximum number of data bytes that may be
6482 * placed on the BD (not including paddings).
6484 rxq_init->buf_sz = (fp->rx_buf_size - IP_HEADER_ALIGNMENT_PADDING);
6486 rxq_init->cl_qzone_id = fp->cl_qzone_id;
6487 rxq_init->rss_engine_id = SC_FUNC(sc);
6488 rxq_init->mcast_engine_id = SC_FUNC(sc);
6490 rxq_init->cache_line_log = BNX2X_RX_ALIGN_SHIFT;
6491 rxq_init->fw_sb_id = fp->fw_sb_id;
6493 rxq_init->sb_cq_index = HC_INDEX_ETH_RX_CQ_CONS;
6496 * configure silent vlan removal
6497 * if multi function mode is afex, then mask default vlan
6499 if (IS_MF_AFEX(sc)) {
6500 rxq_init->silent_removal_value =
6501 sc->devinfo.mf_info.afex_def_vlan_tag;
6502 rxq_init->silent_removal_mask = EVL_VLID_MASK;
6507 bnx2x_pf_tx_q_prep(struct bnx2x_softc *sc, struct bnx2x_fastpath *fp,
6508 struct ecore_txq_setup_params *txq_init, uint8_t cos)
6510 struct bnx2x_tx_queue *txq = fp->sc->tx_queues[fp->index];
6513 PMD_TX_LOG(ERR, "ERROR: TX queue is NULL");
6516 txq_init->dscr_map = (phys_addr_t)txq->tx_ring_phys_addr;
6517 txq_init->sb_cq_index = HC_INDEX_ETH_FIRST_TX_CQ_CONS + cos;
6518 txq_init->traffic_type = LLFC_TRAFFIC_TYPE_NW;
6519 txq_init->fw_sb_id = fp->fw_sb_id;
6522 * set the TSS leading client id for TX classfication to the
6523 * leading RSS client id
6525 txq_init->tss_leading_cl_id = BNX2X_FP(sc, 0, cl_id);
6529 * This function performs 2 steps in a queue state machine:
6534 bnx2x_setup_queue(struct bnx2x_softc *sc, struct bnx2x_fastpath *fp, uint8_t leading)
6536 struct ecore_queue_state_params q_params = { NULL };
6537 struct ecore_queue_setup_params *setup_params = &q_params.params.setup;
6540 PMD_DRV_LOG(DEBUG, "setting up queue %d", fp->index);
6542 bnx2x_ack_sb(sc, fp->igu_sb_id, USTORM_ID, 0, IGU_INT_ENABLE, 0);
6544 q_params.q_obj = &BNX2X_SP_OBJ(sc, fp).q_obj;
6546 /* we want to wait for completion in this context */
6547 bnx2x_set_bit(RAMROD_COMP_WAIT, &q_params.ramrod_flags);
6549 /* prepare the INIT parameters */
6550 bnx2x_pf_q_prep_init(sc, fp, &q_params.params.init);
6552 /* Set the command */
6553 q_params.cmd = ECORE_Q_CMD_INIT;
6555 /* Change the state to INIT */
6556 rc = ecore_queue_state_change(sc, &q_params);
6558 PMD_DRV_LOG(NOTICE, "Queue(%d) INIT failed", fp->index);
6562 PMD_DRV_LOG(DEBUG, "init complete");
6564 /* now move the Queue to the SETUP state */
6565 memset(setup_params, 0, sizeof(*setup_params));
6567 /* set Queue flags */
6568 setup_params->flags = bnx2x_get_q_flags(sc, leading);
6570 /* set general SETUP parameters */
6571 bnx2x_pf_q_prep_general(sc, fp, &setup_params->gen_params,
6572 FIRST_TX_COS_INDEX);
6574 bnx2x_pf_rx_q_prep(sc, fp,
6575 &setup_params->pause_params,
6576 &setup_params->rxq_params);
6578 bnx2x_pf_tx_q_prep(sc, fp, &setup_params->txq_params, FIRST_TX_COS_INDEX);
6580 /* Set the command */
6581 q_params.cmd = ECORE_Q_CMD_SETUP;
6583 /* change the state to SETUP */
6584 rc = ecore_queue_state_change(sc, &q_params);
6586 PMD_DRV_LOG(NOTICE, "Queue(%d) SETUP failed", fp->index);
6593 static int bnx2x_setup_leading(struct bnx2x_softc *sc)
6596 return bnx2x_setup_queue(sc, &sc->fp[0], TRUE);
6598 return bnx2x_vf_setup_queue(sc, &sc->fp[0], TRUE);
6602 bnx2x_config_rss_pf(struct bnx2x_softc *sc, struct ecore_rss_config_obj *rss_obj,
6603 uint8_t config_hash)
6605 struct ecore_config_rss_params params = { NULL };
6609 * Although RSS is meaningless when there is a single HW queue we
6610 * still need it enabled in order to have HW Rx hash generated.
6613 params.rss_obj = rss_obj;
6615 bnx2x_set_bit(RAMROD_COMP_WAIT, ¶ms.ramrod_flags);
6617 bnx2x_set_bit(ECORE_RSS_MODE_REGULAR, ¶ms.rss_flags);
6619 /* RSS configuration */
6620 bnx2x_set_bit(ECORE_RSS_IPV4, ¶ms.rss_flags);
6621 bnx2x_set_bit(ECORE_RSS_IPV4_TCP, ¶ms.rss_flags);
6622 bnx2x_set_bit(ECORE_RSS_IPV6, ¶ms.rss_flags);
6623 bnx2x_set_bit(ECORE_RSS_IPV6_TCP, ¶ms.rss_flags);
6624 if (rss_obj->udp_rss_v4) {
6625 bnx2x_set_bit(ECORE_RSS_IPV4_UDP, ¶ms.rss_flags);
6627 if (rss_obj->udp_rss_v6) {
6628 bnx2x_set_bit(ECORE_RSS_IPV6_UDP, ¶ms.rss_flags);
6632 params.rss_result_mask = MULTI_MASK;
6634 (void)rte_memcpy(params.ind_table, rss_obj->ind_table,
6635 sizeof(params.ind_table));
6639 for (i = 0; i < sizeof(params.rss_key) / 4; i++) {
6640 params.rss_key[i] = (uint32_t) rte_rand();
6643 bnx2x_set_bit(ECORE_RSS_SET_SRCH, ¶ms.rss_flags);
6647 return ecore_config_rss(sc, ¶ms);
6649 return bnx2x_vf_config_rss(sc, ¶ms);
6652 static int bnx2x_config_rss_eth(struct bnx2x_softc *sc, uint8_t config_hash)
6654 return bnx2x_config_rss_pf(sc, &sc->rss_conf_obj, config_hash);
6657 static int bnx2x_init_rss_pf(struct bnx2x_softc *sc)
6659 uint8_t num_eth_queues = BNX2X_NUM_ETH_QUEUES(sc);
6663 * Prepare the initial contents of the indirection table if
6666 for (i = 0; i < sizeof(sc->rss_conf_obj.ind_table); i++) {
6667 sc->rss_conf_obj.ind_table[i] =
6668 (sc->fp->cl_id + (i % num_eth_queues));
6672 sc->rss_conf_obj.udp_rss_v4 = sc->rss_conf_obj.udp_rss_v6 = 1;
6676 * For 57711 SEARCHER configuration (rss_keys) is
6677 * per-port, so if explicit configuration is needed, do it only
6680 * For 57712 and newer it's a per-function configuration.
6682 return bnx2x_config_rss_eth(sc, sc->port.pmf || !CHIP_IS_E1x(sc));
6686 bnx2x_set_mac_one(struct bnx2x_softc *sc, uint8_t * mac,
6687 struct ecore_vlan_mac_obj *obj, uint8_t set, int mac_type,
6688 unsigned long *ramrod_flags)
6690 struct ecore_vlan_mac_ramrod_params ramrod_param;
6693 memset(&ramrod_param, 0, sizeof(ramrod_param));
6695 /* fill in general parameters */
6696 ramrod_param.vlan_mac_obj = obj;
6697 ramrod_param.ramrod_flags = *ramrod_flags;
6699 /* fill a user request section if needed */
6700 if (!bnx2x_test_bit(RAMROD_CONT, ramrod_flags)) {
6701 (void)rte_memcpy(ramrod_param.user_req.u.mac.mac, mac,
6704 bnx2x_set_bit(mac_type, &ramrod_param.user_req.vlan_mac_flags);
6706 /* Set the command: ADD or DEL */
6707 ramrod_param.user_req.cmd = (set) ? ECORE_VLAN_MAC_ADD :
6711 rc = ecore_config_vlan_mac(sc, &ramrod_param);
6713 if (rc == ECORE_EXISTS) {
6714 PMD_DRV_LOG(INFO, "Failed to schedule ADD operations (EEXIST)");
6715 /* do not treat adding same MAC as error */
6717 } else if (rc < 0) {
6719 "%s MAC failed (%d)", (set ? "Set" : "Delete"), rc);
6725 static int bnx2x_set_eth_mac(struct bnx2x_softc *sc, uint8_t set)
6727 unsigned long ramrod_flags = 0;
6729 PMD_DRV_LOG(DEBUG, "Adding Ethernet MAC");
6731 bnx2x_set_bit(RAMROD_COMP_WAIT, &ramrod_flags);
6733 /* Eth MAC is set on RSS leading client (fp[0]) */
6734 return bnx2x_set_mac_one(sc, sc->link_params.mac_addr,
6735 &sc->sp_objs->mac_obj,
6736 set, ECORE_ETH_MAC, &ramrod_flags);
6739 static int bnx2x_get_cur_phy_idx(struct bnx2x_softc *sc)
6741 uint32_t sel_phy_idx = 0;
6743 if (sc->link_params.num_phys <= 1) {
6744 return ELINK_INT_PHY;
6747 if (sc->link_vars.link_up) {
6748 sel_phy_idx = ELINK_EXT_PHY1;
6749 /* In case link is SERDES, check if the ELINK_EXT_PHY2 is the one */
6750 if ((sc->link_vars.link_status & LINK_STATUS_SERDES_LINK) &&
6751 (sc->link_params.phy[ELINK_EXT_PHY2].supported &
6752 ELINK_SUPPORTED_FIBRE))
6753 sel_phy_idx = ELINK_EXT_PHY2;
6755 switch (elink_phy_selection(&sc->link_params)) {
6756 case PORT_HW_CFG_PHY_SELECTION_HARDWARE_DEFAULT:
6757 case PORT_HW_CFG_PHY_SELECTION_FIRST_PHY:
6758 case PORT_HW_CFG_PHY_SELECTION_FIRST_PHY_PRIORITY:
6759 sel_phy_idx = ELINK_EXT_PHY1;
6761 case PORT_HW_CFG_PHY_SELECTION_SECOND_PHY:
6762 case PORT_HW_CFG_PHY_SELECTION_SECOND_PHY_PRIORITY:
6763 sel_phy_idx = ELINK_EXT_PHY2;
6771 static int bnx2x_get_link_cfg_idx(struct bnx2x_softc *sc)
6773 uint32_t sel_phy_idx = bnx2x_get_cur_phy_idx(sc);
6776 * The selected activated PHY is always after swapping (in case PHY
6777 * swapping is enabled). So when swapping is enabled, we need to reverse
6781 if (sc->link_params.multi_phy_config & PORT_HW_CFG_PHY_SWAPPED_ENABLED) {
6782 if (sel_phy_idx == ELINK_EXT_PHY1)
6783 sel_phy_idx = ELINK_EXT_PHY2;
6784 else if (sel_phy_idx == ELINK_EXT_PHY2)
6785 sel_phy_idx = ELINK_EXT_PHY1;
6788 return ELINK_LINK_CONFIG_IDX(sel_phy_idx);
6791 static void bnx2x_set_requested_fc(struct bnx2x_softc *sc)
6794 * Initialize link parameters structure variables
6795 * It is recommended to turn off RX FC for jumbo frames
6796 * for better performance
6798 if (CHIP_IS_E1x(sc) && (sc->mtu > 5000)) {
6799 sc->link_params.req_fc_auto_adv = ELINK_FLOW_CTRL_TX;
6801 sc->link_params.req_fc_auto_adv = ELINK_FLOW_CTRL_BOTH;
6805 static void bnx2x_calc_fc_adv(struct bnx2x_softc *sc)
6807 uint8_t cfg_idx = bnx2x_get_link_cfg_idx(sc);
6808 switch (sc->link_vars.ieee_fc &
6809 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_MASK) {
6810 case MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_NONE:
6812 sc->port.advertising[cfg_idx] &= ~(ADVERTISED_Asym_Pause |
6816 case MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH:
6817 sc->port.advertising[cfg_idx] |= (ADVERTISED_Asym_Pause |
6821 case MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC:
6822 sc->port.advertising[cfg_idx] |= ADVERTISED_Asym_Pause;
6827 static uint16_t bnx2x_get_mf_speed(struct bnx2x_softc *sc)
6829 uint16_t line_speed = sc->link_vars.line_speed;
6831 uint16_t maxCfg = bnx2x_extract_max_cfg(sc,
6833 mf_info.mf_config[SC_VN
6836 /* calculate the current MAX line speed limit for the MF devices */
6838 line_speed = (line_speed * maxCfg) / 100;
6839 } else { /* SD mode */
6840 uint16_t vn_max_rate = maxCfg * 100;
6842 if (vn_max_rate < line_speed) {
6843 line_speed = vn_max_rate;
6852 bnx2x_fill_report_data(struct bnx2x_softc *sc, struct bnx2x_link_report_data *data)
6854 uint16_t line_speed = bnx2x_get_mf_speed(sc);
6856 memset(data, 0, sizeof(*data));
6858 /* fill the report data with the effective line speed */
6859 data->line_speed = line_speed;
6862 if (!sc->link_vars.link_up || (sc->flags & BNX2X_MF_FUNC_DIS)) {
6863 bnx2x_set_bit(BNX2X_LINK_REPORT_LINK_DOWN,
6864 &data->link_report_flags);
6868 if (sc->link_vars.duplex == DUPLEX_FULL) {
6869 bnx2x_set_bit(BNX2X_LINK_REPORT_FULL_DUPLEX,
6870 &data->link_report_flags);
6873 /* Rx Flow Control is ON */
6874 if (sc->link_vars.flow_ctrl & ELINK_FLOW_CTRL_RX) {
6875 bnx2x_set_bit(BNX2X_LINK_REPORT_RX_FC_ON, &data->link_report_flags);
6878 /* Tx Flow Control is ON */
6879 if (sc->link_vars.flow_ctrl & ELINK_FLOW_CTRL_TX) {
6880 bnx2x_set_bit(BNX2X_LINK_REPORT_TX_FC_ON, &data->link_report_flags);
6884 /* report link status to OS, should be called under phy_lock */
6885 static void bnx2x_link_report(struct bnx2x_softc *sc)
6887 struct bnx2x_link_report_data cur_data;
6891 bnx2x_read_mf_cfg(sc);
6894 /* Read the current link report info */
6895 bnx2x_fill_report_data(sc, &cur_data);
6897 /* Don't report link down or exactly the same link status twice */
6898 if (!memcmp(&cur_data, &sc->last_reported_link, sizeof(cur_data)) ||
6899 (bnx2x_test_bit(BNX2X_LINK_REPORT_LINK_DOWN,
6900 &sc->last_reported_link.link_report_flags) &&
6901 bnx2x_test_bit(BNX2X_LINK_REPORT_LINK_DOWN,
6902 &cur_data.link_report_flags))) {
6908 /* report new link params and remember the state for the next time */
6909 (void)rte_memcpy(&sc->last_reported_link, &cur_data, sizeof(cur_data));
6911 if (bnx2x_test_bit(BNX2X_LINK_REPORT_LINK_DOWN,
6912 &cur_data.link_report_flags)) {
6913 PMD_DRV_LOG(INFO, "NIC Link is Down");
6915 __rte_unused const char *duplex;
6916 __rte_unused const char *flow;
6918 if (bnx2x_test_and_clear_bit(BNX2X_LINK_REPORT_FULL_DUPLEX,
6919 &cur_data.link_report_flags)) {
6926 * Handle the FC at the end so that only these flags would be
6927 * possibly set. This way we may easily check if there is no FC
6930 if (cur_data.link_report_flags) {
6931 if (bnx2x_test_bit(BNX2X_LINK_REPORT_RX_FC_ON,
6932 &cur_data.link_report_flags) &&
6933 bnx2x_test_bit(BNX2X_LINK_REPORT_TX_FC_ON,
6934 &cur_data.link_report_flags)) {
6935 flow = "ON - receive & transmit";
6936 } else if (bnx2x_test_bit(BNX2X_LINK_REPORT_RX_FC_ON,
6937 &cur_data.link_report_flags) &&
6938 !bnx2x_test_bit(BNX2X_LINK_REPORT_TX_FC_ON,
6939 &cur_data.link_report_flags)) {
6940 flow = "ON - receive";
6941 } else if (!bnx2x_test_bit(BNX2X_LINK_REPORT_RX_FC_ON,
6942 &cur_data.link_report_flags) &&
6943 bnx2x_test_bit(BNX2X_LINK_REPORT_TX_FC_ON,
6944 &cur_data.link_report_flags)) {
6945 flow = "ON - transmit";
6947 flow = "none"; /* possible? */
6954 "NIC Link is Up, %d Mbps %s duplex, Flow control: %s",
6955 cur_data.line_speed, duplex, flow);
6959 void bnx2x_link_status_update(struct bnx2x_softc *sc)
6961 if (sc->state != BNX2X_STATE_OPEN) {
6965 if (IS_PF(sc) && !CHIP_REV_IS_SLOW(sc)) {
6966 elink_link_status_update(&sc->link_params, &sc->link_vars);
6968 sc->port.supported[0] |= (ELINK_SUPPORTED_10baseT_Half |
6969 ELINK_SUPPORTED_10baseT_Full |
6970 ELINK_SUPPORTED_100baseT_Half |
6971 ELINK_SUPPORTED_100baseT_Full |
6972 ELINK_SUPPORTED_1000baseT_Full |
6973 ELINK_SUPPORTED_2500baseX_Full |
6974 ELINK_SUPPORTED_10000baseT_Full |
6975 ELINK_SUPPORTED_TP |
6976 ELINK_SUPPORTED_FIBRE |
6977 ELINK_SUPPORTED_Autoneg |
6978 ELINK_SUPPORTED_Pause |
6979 ELINK_SUPPORTED_Asym_Pause);
6980 sc->port.advertising[0] = sc->port.supported[0];
6982 sc->link_params.sc = sc;
6983 sc->link_params.port = SC_PORT(sc);
6984 sc->link_params.req_duplex[0] = DUPLEX_FULL;
6985 sc->link_params.req_flow_ctrl[0] = ELINK_FLOW_CTRL_NONE;
6986 sc->link_params.req_line_speed[0] = SPEED_10000;
6987 sc->link_params.speed_cap_mask[0] = 0x7f0000;
6988 sc->link_params.switch_cfg = ELINK_SWITCH_CFG_10G;
6990 if (CHIP_REV_IS_FPGA(sc)) {
6991 sc->link_vars.mac_type = ELINK_MAC_TYPE_EMAC;
6992 sc->link_vars.line_speed = ELINK_SPEED_1000;
6993 sc->link_vars.link_status = (LINK_STATUS_LINK_UP |
6994 LINK_STATUS_SPEED_AND_DUPLEX_1000TFD);
6996 sc->link_vars.mac_type = ELINK_MAC_TYPE_BMAC;
6997 sc->link_vars.line_speed = ELINK_SPEED_10000;
6998 sc->link_vars.link_status = (LINK_STATUS_LINK_UP |
6999 LINK_STATUS_SPEED_AND_DUPLEX_10GTFD);
7002 sc->link_vars.link_up = 1;
7004 sc->link_vars.duplex = DUPLEX_FULL;
7005 sc->link_vars.flow_ctrl = ELINK_FLOW_CTRL_NONE;
7009 NIG_REG_EGRESS_DRAIN0_MODE +
7010 sc->link_params.port * 4, 0);
7011 bnx2x_stats_handle(sc, STATS_EVENT_LINK_UP);
7012 bnx2x_link_report(sc);
7017 if (sc->link_vars.link_up) {
7018 bnx2x_stats_handle(sc, STATS_EVENT_LINK_UP);
7020 bnx2x_stats_handle(sc, STATS_EVENT_STOP);
7022 bnx2x_link_report(sc);
7024 bnx2x_link_report(sc);
7025 bnx2x_stats_handle(sc, STATS_EVENT_LINK_UP);
7029 static void bnx2x_periodic_start(struct bnx2x_softc *sc)
7031 atomic_store_rel_long(&sc->periodic_flags, PERIODIC_GO);
7034 static void bnx2x_periodic_stop(struct bnx2x_softc *sc)
7036 atomic_store_rel_long(&sc->periodic_flags, PERIODIC_STOP);
7039 static int bnx2x_initial_phy_init(struct bnx2x_softc *sc, int load_mode)
7041 int rc, cfg_idx = bnx2x_get_link_cfg_idx(sc);
7042 uint16_t req_line_speed = sc->link_params.req_line_speed[cfg_idx];
7043 struct elink_params *lp = &sc->link_params;
7045 bnx2x_set_requested_fc(sc);
7047 if (CHIP_REV_IS_SLOW(sc)) {
7048 uint32_t bond = CHIP_BOND_ID(sc);
7051 if (CHIP_IS_E2(sc) && CHIP_IS_MODE_4_PORT(sc)) {
7052 feat |= ELINK_FEATURE_CONFIG_EMUL_DISABLE_BMAC;
7053 } else if (bond & 0x4) {
7054 if (CHIP_IS_E3(sc)) {
7055 feat |= ELINK_FEATURE_CONFIG_EMUL_DISABLE_XMAC;
7057 feat |= ELINK_FEATURE_CONFIG_EMUL_DISABLE_BMAC;
7059 } else if (bond & 0x8) {
7060 if (CHIP_IS_E3(sc)) {
7061 feat |= ELINK_FEATURE_CONFIG_EMUL_DISABLE_UMAC;
7063 feat |= ELINK_FEATURE_CONFIG_EMUL_DISABLE_EMAC;
7067 /* disable EMAC for E3 and above */
7069 feat |= ELINK_FEATURE_CONFIG_EMUL_DISABLE_EMAC;
7072 sc->link_params.feature_config_flags |= feat;
7075 if (load_mode == LOAD_DIAG) {
7076 lp->loopback_mode = ELINK_LOOPBACK_XGXS;
7077 /* Prefer doing PHY loopback at 10G speed, if possible */
7078 if (lp->req_line_speed[cfg_idx] < ELINK_SPEED_10000) {
7079 if (lp->speed_cap_mask[cfg_idx] &
7080 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G) {
7081 lp->req_line_speed[cfg_idx] = ELINK_SPEED_10000;
7083 lp->req_line_speed[cfg_idx] = ELINK_SPEED_1000;
7088 if (load_mode == LOAD_LOOPBACK_EXT) {
7089 lp->loopback_mode = ELINK_LOOPBACK_EXT;
7092 rc = elink_phy_init(&sc->link_params, &sc->link_vars);
7094 bnx2x_calc_fc_adv(sc);
7096 if (sc->link_vars.link_up) {
7097 bnx2x_stats_handle(sc, STATS_EVENT_LINK_UP);
7098 bnx2x_link_report(sc);
7101 if (!CHIP_REV_IS_SLOW(sc)) {
7102 bnx2x_periodic_start(sc);
7105 sc->link_params.req_line_speed[cfg_idx] = req_line_speed;
7109 /* update flags in shmem */
7111 bnx2x_update_drv_flags(struct bnx2x_softc *sc, uint32_t flags, uint32_t set)
7115 if (SHMEM2_HAS(sc, drv_flags)) {
7116 bnx2x_acquire_hw_lock(sc, HW_LOCK_RESOURCE_DRV_FLAGS);
7117 drv_flags = SHMEM2_RD(sc, drv_flags);
7122 drv_flags &= ~flags;
7125 SHMEM2_WR(sc, drv_flags, drv_flags);
7127 bnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_DRV_FLAGS);
7131 /* periodic timer callout routine, only runs when the interface is up */
7132 void bnx2x_periodic_callout(struct bnx2x_softc *sc)
7134 if ((sc->state != BNX2X_STATE_OPEN) ||
7135 (atomic_load_acq_long(&sc->periodic_flags) == PERIODIC_STOP)) {
7136 PMD_DRV_LOG(WARNING, "periodic callout exit (state=0x%x)",
7140 if (!CHIP_REV_IS_SLOW(sc)) {
7142 * This barrier is needed to ensure the ordering between the writing
7143 * to the sc->port.pmf in the bnx2x_nic_load() or bnx2x_pmf_update() and
7148 elink_period_func(&sc->link_params, &sc->link_vars);
7152 if (IS_PF(sc) && !BNX2X_NOMCP(sc)) {
7153 int mb_idx = SC_FW_MB_IDX(sc);
7157 ++sc->fw_drv_pulse_wr_seq;
7158 sc->fw_drv_pulse_wr_seq &= DRV_PULSE_SEQ_MASK;
7160 drv_pulse = sc->fw_drv_pulse_wr_seq;
7161 bnx2x_drv_pulse(sc);
7163 mcp_pulse = (SHMEM_RD(sc, func_mb[mb_idx].mcp_pulse_mb) &
7164 MCP_PULSE_SEQ_MASK);
7167 * The delta between driver pulse and mcp response should
7168 * be 1 (before mcp response) or 0 (after mcp response).
7170 if ((drv_pulse != mcp_pulse) &&
7171 (drv_pulse != ((mcp_pulse + 1) & MCP_PULSE_SEQ_MASK))) {
7172 /* someone lost a heartbeat... */
7174 "drv_pulse (0x%x) != mcp_pulse (0x%x)",
7175 drv_pulse, mcp_pulse);
7181 /* start the controller */
7182 static __attribute__ ((noinline))
7183 int bnx2x_nic_load(struct bnx2x_softc *sc)
7186 uint32_t load_code = 0;
7189 PMD_INIT_FUNC_TRACE();
7191 sc->state = BNX2X_STATE_OPENING_WAITING_LOAD;
7194 /* must be called before memory allocation and HW init */
7195 bnx2x_ilt_set_info(sc);
7198 bnx2x_set_fp_rx_buf_size(sc);
7201 if (bnx2x_alloc_mem(sc) != 0) {
7202 sc->state = BNX2X_STATE_CLOSED;
7204 goto bnx2x_nic_load_error0;
7208 if (bnx2x_alloc_fw_stats_mem(sc) != 0) {
7209 sc->state = BNX2X_STATE_CLOSED;
7211 goto bnx2x_nic_load_error0;
7215 rc = bnx2x_vf_init(sc);
7217 sc->state = BNX2X_STATE_ERROR;
7218 goto bnx2x_nic_load_error0;
7223 /* set pf load just before approaching the MCP */
7224 bnx2x_set_pf_load(sc);
7226 /* if MCP exists send load request and analyze response */
7227 if (!BNX2X_NOMCP(sc)) {
7228 /* attempt to load pf */
7229 if (bnx2x_nic_load_request(sc, &load_code) != 0) {
7230 sc->state = BNX2X_STATE_CLOSED;
7232 goto bnx2x_nic_load_error1;
7235 /* what did the MCP say? */
7236 if (bnx2x_nic_load_analyze_req(sc, load_code) != 0) {
7237 bnx2x_fw_command(sc, DRV_MSG_CODE_LOAD_DONE, 0);
7238 sc->state = BNX2X_STATE_CLOSED;
7240 goto bnx2x_nic_load_error2;
7243 PMD_DRV_LOG(INFO, "Device has no MCP!");
7244 load_code = bnx2x_nic_load_no_mcp(sc);
7247 /* mark PMF if applicable */
7248 bnx2x_nic_load_pmf(sc, load_code);
7250 /* Init Function state controlling object */
7251 bnx2x_init_func_obj(sc);
7254 if (bnx2x_init_hw(sc, load_code) != 0) {
7255 PMD_DRV_LOG(NOTICE, "HW init failed");
7256 bnx2x_fw_command(sc, DRV_MSG_CODE_LOAD_DONE, 0);
7257 sc->state = BNX2X_STATE_CLOSED;
7259 goto bnx2x_nic_load_error2;
7263 bnx2x_nic_init(sc, load_code);
7265 /* Init per-function objects */
7267 bnx2x_init_objs(sc);
7269 /* set AFEX default VLAN tag to an invalid value */
7270 sc->devinfo.mf_info.afex_def_vlan_tag = -1;
7272 sc->state = BNX2X_STATE_OPENING_WAITING_PORT;
7273 rc = bnx2x_func_start(sc);
7275 PMD_DRV_LOG(NOTICE, "Function start failed!");
7276 bnx2x_fw_command(sc, DRV_MSG_CODE_LOAD_DONE, 0);
7277 sc->state = BNX2X_STATE_ERROR;
7278 goto bnx2x_nic_load_error3;
7281 /* send LOAD_DONE command to MCP */
7282 if (!BNX2X_NOMCP(sc)) {
7284 bnx2x_fw_command(sc, DRV_MSG_CODE_LOAD_DONE, 0);
7287 "MCP response failure, aborting");
7288 sc->state = BNX2X_STATE_ERROR;
7290 goto bnx2x_nic_load_error3;
7295 rc = bnx2x_setup_leading(sc);
7297 PMD_DRV_LOG(NOTICE, "Setup leading failed!");
7298 sc->state = BNX2X_STATE_ERROR;
7299 goto bnx2x_nic_load_error3;
7302 FOR_EACH_NONDEFAULT_ETH_QUEUE(sc, i) {
7304 rc = bnx2x_setup_queue(sc, &sc->fp[i], FALSE);
7305 else /* IS_VF(sc) */
7306 rc = bnx2x_vf_setup_queue(sc, &sc->fp[i], FALSE);
7309 PMD_DRV_LOG(NOTICE, "Queue(%d) setup failed", i);
7310 sc->state = BNX2X_STATE_ERROR;
7311 goto bnx2x_nic_load_error3;
7315 rc = bnx2x_init_rss_pf(sc);
7317 PMD_DRV_LOG(NOTICE, "PF RSS init failed");
7318 sc->state = BNX2X_STATE_ERROR;
7319 goto bnx2x_nic_load_error3;
7322 /* now when Clients are configured we are ready to work */
7323 sc->state = BNX2X_STATE_OPEN;
7325 /* Configure a ucast MAC */
7327 rc = bnx2x_set_eth_mac(sc, TRUE);
7328 } else { /* IS_VF(sc) */
7329 rc = bnx2x_vf_set_mac(sc, TRUE);
7333 PMD_DRV_LOG(NOTICE, "Setting Ethernet MAC failed");
7334 sc->state = BNX2X_STATE_ERROR;
7335 goto bnx2x_nic_load_error3;
7339 rc = bnx2x_initial_phy_init(sc, LOAD_OPEN);
7341 sc->state = BNX2X_STATE_ERROR;
7342 goto bnx2x_nic_load_error3;
7346 sc->link_params.feature_config_flags &=
7347 ~ELINK_FEATURE_CONFIG_BOOT_FROM_SAN;
7350 switch (LOAD_OPEN) {
7356 case LOAD_LOOPBACK_EXT:
7357 sc->state = BNX2X_STATE_DIAG;
7365 bnx2x_update_drv_flags(sc, 1 << DRV_FLAGS_PORT_MASK, 0);
7367 bnx2x_link_status_update(sc);
7370 if (IS_PF(sc) && SHMEM2_HAS(sc, drv_capabilities_flag)) {
7371 /* mark driver is loaded in shmem2 */
7372 val = SHMEM2_RD(sc, drv_capabilities_flag[SC_FW_MB_IDX(sc)]);
7373 SHMEM2_WR(sc, drv_capabilities_flag[SC_FW_MB_IDX(sc)],
7375 DRV_FLAGS_CAPABILITIES_LOADED_SUPPORTED |
7376 DRV_FLAGS_CAPABILITIES_LOADED_L2));
7379 /* start fast path */
7380 /* Initialize Rx filter */
7381 bnx2x_set_rx_mode(sc);
7383 /* wait for all pending SP commands to complete */
7384 if (IS_PF(sc) && !bnx2x_wait_sp_comp(sc, ~0x0UL)) {
7385 PMD_DRV_LOG(NOTICE, "Timeout waiting for all SPs to complete!");
7386 bnx2x_periodic_stop(sc);
7387 bnx2x_nic_unload(sc, UNLOAD_CLOSE, FALSE);
7391 PMD_DRV_LOG(DEBUG, "NIC successfully loaded");
7395 bnx2x_nic_load_error3:
7398 bnx2x_int_disable_sync(sc, 1);
7400 /* clean out queued objects */
7401 bnx2x_squeeze_objects(sc);
7404 bnx2x_nic_load_error2:
7406 if (IS_PF(sc) && !BNX2X_NOMCP(sc)) {
7407 bnx2x_fw_command(sc, DRV_MSG_CODE_UNLOAD_REQ_WOL_MCP, 0);
7408 bnx2x_fw_command(sc, DRV_MSG_CODE_UNLOAD_DONE, 0);
7413 bnx2x_nic_load_error1:
7415 /* clear pf_load status, as it was already set */
7417 bnx2x_clear_pf_load(sc);
7420 bnx2x_nic_load_error0:
7422 bnx2x_free_fw_stats_mem(sc);
7429 * Handles controller initialization.
7431 int bnx2x_init(struct bnx2x_softc *sc)
7433 int other_engine = SC_PATH(sc) ? 0 : 1;
7434 uint8_t other_load_status, load_status;
7435 uint8_t global = FALSE;
7438 /* Check if the driver is still running and bail out if it is. */
7439 if (sc->state != BNX2X_STATE_CLOSED) {
7440 PMD_DRV_LOG(DEBUG, "Init called while driver is running!");
7442 goto bnx2x_init_done;
7445 bnx2x_set_power_state(sc, PCI_PM_D0);
7448 * If parity occurred during the unload, then attentions and/or
7449 * RECOVERY_IN_PROGRESS may still be set. If so we want the first function
7450 * loaded on the current engine to complete the recovery. Parity recovery
7451 * is only relevant for PF driver.
7454 other_load_status = bnx2x_get_load_status(sc, other_engine);
7455 load_status = bnx2x_get_load_status(sc, SC_PATH(sc));
7457 if (!bnx2x_reset_is_done(sc, SC_PATH(sc)) ||
7458 bnx2x_chk_parity_attn(sc, &global, TRUE)) {
7461 * If there are attentions and they are in global blocks, set
7462 * the GLOBAL_RESET bit regardless whether it will be this
7463 * function that will complete the recovery or not.
7466 bnx2x_set_reset_global(sc);
7470 * Only the first function on the current engine should try
7471 * to recover in open. In case of attentions in global blocks
7472 * only the first in the chip should try to recover.
7475 && (!global ||!other_load_status))
7476 && bnx2x_trylock_leader_lock(sc)
7477 && !bnx2x_leader_reset(sc)) {
7479 "Recovered during init");
7483 /* recovery has failed... */
7484 bnx2x_set_power_state(sc, PCI_PM_D3hot);
7486 sc->recovery_state = BNX2X_RECOVERY_FAILED;
7489 "Recovery flow hasn't properly "
7490 "completed yet, try again later. "
7491 "If you still see this message after a "
7492 "few retries then power cycle is required.");
7495 goto bnx2x_init_done;
7500 sc->recovery_state = BNX2X_RECOVERY_DONE;
7502 rc = bnx2x_nic_load(sc);
7507 PMD_DRV_LOG(NOTICE, "Initialization failed, "
7508 "stack notified driver is NOT running!");
7514 static void bnx2x_get_function_num(struct bnx2x_softc *sc)
7519 * Read the ME register to get the function number. The ME register
7520 * holds the relative-function number and absolute-function number. The
7521 * absolute-function number appears only in E2 and above. Before that
7522 * these bits always contained zero, therefore we cannot blindly use them.
7525 val = REG_RD(sc, BAR_ME_REGISTER);
7528 (uint8_t) ((val & ME_REG_PF_NUM) >> ME_REG_PF_NUM_SHIFT);
7530 (uint8_t) ((val & ME_REG_ABS_PF_NUM) >> ME_REG_ABS_PF_NUM_SHIFT) &
7533 if (CHIP_PORT_MODE(sc) == CHIP_4_PORT_MODE) {
7534 sc->pfunc_abs = ((sc->pfunc_rel << 1) | sc->path_id);
7536 sc->pfunc_abs = (sc->pfunc_rel | sc->path_id);
7540 "Relative function %d, Absolute function %d, Path %d",
7541 sc->pfunc_rel, sc->pfunc_abs, sc->path_id);
7544 static uint32_t bnx2x_get_shmem_mf_cfg_base(struct bnx2x_softc *sc)
7546 uint32_t shmem2_size;
7548 uint32_t mf_cfg_offset_value;
7551 offset = (SHMEM_ADDR(sc, func_mb) +
7552 (MAX_FUNC_NUM * sizeof(struct drv_func_mb)));
7555 if (sc->devinfo.shmem2_base != 0) {
7556 shmem2_size = SHMEM2_RD(sc, size);
7557 if (shmem2_size > offsetof(struct shmem2_region, mf_cfg_addr)) {
7558 mf_cfg_offset_value = SHMEM2_RD(sc, mf_cfg_addr);
7559 if (SHMEM_MF_CFG_ADDR_NONE != mf_cfg_offset_value) {
7560 offset = mf_cfg_offset_value;
7568 static uint32_t bnx2x_pcie_capability_read(struct bnx2x_softc *sc, int reg)
7571 struct bnx2x_pci_cap *caps;
7573 /* ensure PCIe capability is enabled */
7574 caps = pci_find_cap(sc, PCIY_EXPRESS, BNX2X_PCI_CAP);
7576 PMD_DRV_LOG(DEBUG, "Found PCIe capability: "
7577 "id=0x%04X type=0x%04X addr=0x%08X",
7578 caps->id, caps->type, caps->addr);
7579 pci_read(sc, (caps->addr + reg), &ret, 2);
7583 PMD_DRV_LOG(WARNING, "PCIe capability NOT FOUND!!!");
7588 static uint8_t bnx2x_is_pcie_pending(struct bnx2x_softc *sc)
7590 return (bnx2x_pcie_capability_read(sc, PCIR_EXPRESS_DEVICE_STA) &
7591 PCIM_EXP_STA_TRANSACTION_PND);
7595 * Walk the PCI capabiites list for the device to find what features are
7596 * supported. These capabilites may be enabled/disabled by firmware so it's
7597 * best to walk the list rather than make assumptions.
7599 static void bnx2x_probe_pci_caps(struct bnx2x_softc *sc)
7601 PMD_INIT_FUNC_TRACE();
7603 struct bnx2x_pci_cap *caps;
7604 uint16_t link_status;
7605 #ifdef RTE_LIBRTE_BNX2X_DEBUG
7609 /* check if PCI Power Management is enabled */
7610 caps = pci_find_cap(sc, PCIY_PMG, BNX2X_PCI_CAP);
7612 PMD_DRV_LOG(DEBUG, "Found PM capability: "
7613 "id=0x%04X type=0x%04X addr=0x%08X",
7614 caps->id, caps->type, caps->addr);
7616 sc->devinfo.pcie_cap_flags |= BNX2X_PM_CAPABLE_FLAG;
7617 sc->devinfo.pcie_pm_cap_reg = caps->addr;
7620 link_status = bnx2x_pcie_capability_read(sc, PCIR_EXPRESS_LINK_STA);
7622 sc->devinfo.pcie_link_speed = (link_status & PCIM_LINK_STA_SPEED);
7623 sc->devinfo.pcie_link_width =
7624 ((link_status & PCIM_LINK_STA_WIDTH) >> 4);
7626 PMD_DRV_LOG(DEBUG, "PCIe link speed=%d width=%d",
7627 sc->devinfo.pcie_link_speed, sc->devinfo.pcie_link_width);
7629 sc->devinfo.pcie_cap_flags |= BNX2X_PCIE_CAPABLE_FLAG;
7631 /* check if MSI capability is enabled */
7632 caps = pci_find_cap(sc, PCIY_MSI, BNX2X_PCI_CAP);
7634 PMD_DRV_LOG(DEBUG, "Found MSI capability at 0x%04x", reg);
7636 sc->devinfo.pcie_cap_flags |= BNX2X_MSI_CAPABLE_FLAG;
7637 sc->devinfo.pcie_msi_cap_reg = caps->addr;
7640 /* check if MSI-X capability is enabled */
7641 caps = pci_find_cap(sc, PCIY_MSIX, BNX2X_PCI_CAP);
7643 PMD_DRV_LOG(DEBUG, "Found MSI-X capability at 0x%04x", reg);
7645 sc->devinfo.pcie_cap_flags |= BNX2X_MSIX_CAPABLE_FLAG;
7646 sc->devinfo.pcie_msix_cap_reg = caps->addr;
7650 static int bnx2x_get_shmem_mf_cfg_info_sd(struct bnx2x_softc *sc)
7652 struct bnx2x_mf_info *mf_info = &sc->devinfo.mf_info;
7655 /* get the outer vlan if we're in switch-dependent mode */
7657 val = MFCFG_RD(sc, func_mf_config[SC_ABS_FUNC(sc)].e1hov_tag);
7658 mf_info->ext_id = (uint16_t) val;
7660 mf_info->multi_vnics_mode = 1;
7662 if (!VALID_OVLAN(mf_info->ext_id)) {
7663 PMD_DRV_LOG(NOTICE, "Invalid VLAN (%d)", mf_info->ext_id);
7667 /* get the capabilities */
7668 if ((mf_info->mf_config[SC_VN(sc)] & FUNC_MF_CFG_PROTOCOL_MASK) ==
7669 FUNC_MF_CFG_PROTOCOL_ISCSI) {
7670 mf_info->mf_protos_supported |= MF_PROTO_SUPPORT_ISCSI;
7671 } else if ((mf_info->mf_config[SC_VN(sc)] & FUNC_MF_CFG_PROTOCOL_MASK)
7672 == FUNC_MF_CFG_PROTOCOL_FCOE) {
7673 mf_info->mf_protos_supported |= MF_PROTO_SUPPORT_FCOE;
7675 mf_info->mf_protos_supported |= MF_PROTO_SUPPORT_ETHERNET;
7678 mf_info->vnics_per_port =
7679 (CHIP_PORT_MODE(sc) == CHIP_4_PORT_MODE) ? 2 : 4;
7684 static uint32_t bnx2x_get_shmem_ext_proto_support_flags(struct bnx2x_softc *sc)
7686 uint32_t retval = 0;
7689 val = MFCFG_RD(sc, func_ext_config[SC_ABS_FUNC(sc)].func_cfg);
7691 if (val & MACP_FUNC_CFG_FLAGS_ENABLED) {
7692 if (val & MACP_FUNC_CFG_FLAGS_ETHERNET) {
7693 retval |= MF_PROTO_SUPPORT_ETHERNET;
7695 if (val & MACP_FUNC_CFG_FLAGS_ISCSI_OFFLOAD) {
7696 retval |= MF_PROTO_SUPPORT_ISCSI;
7698 if (val & MACP_FUNC_CFG_FLAGS_FCOE_OFFLOAD) {
7699 retval |= MF_PROTO_SUPPORT_FCOE;
7706 static int bnx2x_get_shmem_mf_cfg_info_si(struct bnx2x_softc *sc)
7708 struct bnx2x_mf_info *mf_info = &sc->devinfo.mf_info;
7712 * There is no outer vlan if we're in switch-independent mode.
7713 * If the mac is valid then assume multi-function.
7716 val = MFCFG_RD(sc, func_ext_config[SC_ABS_FUNC(sc)].func_cfg);
7718 mf_info->multi_vnics_mode = ((val & MACP_FUNC_CFG_FLAGS_MASK) != 0);
7720 mf_info->mf_protos_supported =
7721 bnx2x_get_shmem_ext_proto_support_flags(sc);
7723 mf_info->vnics_per_port =
7724 (CHIP_PORT_MODE(sc) == CHIP_4_PORT_MODE) ? 2 : 4;
7729 static int bnx2x_get_shmem_mf_cfg_info_niv(struct bnx2x_softc *sc)
7731 struct bnx2x_mf_info *mf_info = &sc->devinfo.mf_info;
7733 uint32_t func_config;
7734 uint32_t niv_config;
7736 mf_info->multi_vnics_mode = 1;
7738 e1hov_tag = MFCFG_RD(sc, func_mf_config[SC_ABS_FUNC(sc)].e1hov_tag);
7739 func_config = MFCFG_RD(sc, func_mf_config[SC_ABS_FUNC(sc)].config);
7740 niv_config = MFCFG_RD(sc, func_mf_config[SC_ABS_FUNC(sc)].afex_config);
7743 (uint16_t) ((e1hov_tag & FUNC_MF_CFG_E1HOV_TAG_MASK) >>
7744 FUNC_MF_CFG_E1HOV_TAG_SHIFT);
7746 mf_info->default_vlan =
7747 (uint16_t) ((e1hov_tag & FUNC_MF_CFG_AFEX_VLAN_MASK) >>
7748 FUNC_MF_CFG_AFEX_VLAN_SHIFT);
7750 mf_info->niv_allowed_priorities =
7751 (uint8_t) ((niv_config & FUNC_MF_CFG_AFEX_COS_FILTER_MASK) >>
7752 FUNC_MF_CFG_AFEX_COS_FILTER_SHIFT);
7754 mf_info->niv_default_cos =
7755 (uint8_t) ((func_config & FUNC_MF_CFG_TRANSMIT_PRIORITY_MASK) >>
7756 FUNC_MF_CFG_TRANSMIT_PRIORITY_SHIFT);
7758 mf_info->afex_vlan_mode =
7759 ((niv_config & FUNC_MF_CFG_AFEX_VLAN_MODE_MASK) >>
7760 FUNC_MF_CFG_AFEX_VLAN_MODE_SHIFT);
7762 mf_info->niv_mba_enabled =
7763 ((niv_config & FUNC_MF_CFG_AFEX_MBA_ENABLED_MASK) >>
7764 FUNC_MF_CFG_AFEX_MBA_ENABLED_SHIFT);
7766 mf_info->mf_protos_supported =
7767 bnx2x_get_shmem_ext_proto_support_flags(sc);
7769 mf_info->vnics_per_port =
7770 (CHIP_PORT_MODE(sc) == CHIP_4_PORT_MODE) ? 2 : 4;
7775 static int bnx2x_check_valid_mf_cfg(struct bnx2x_softc *sc)
7777 struct bnx2x_mf_info *mf_info = &sc->devinfo.mf_info;
7784 /* various MF mode sanity checks... */
7786 if (mf_info->mf_config[SC_VN(sc)] & FUNC_MF_CFG_FUNC_HIDE) {
7788 "Enumerated function %d is marked as hidden",
7793 if ((mf_info->vnics_per_port > 1) && !mf_info->multi_vnics_mode) {
7794 PMD_DRV_LOG(NOTICE, "vnics_per_port=%d multi_vnics_mode=%d",
7795 mf_info->vnics_per_port, mf_info->multi_vnics_mode);
7799 if (mf_info->mf_mode == MULTI_FUNCTION_SD) {
7800 /* vnic id > 0 must have valid ovlan in switch-dependent mode */
7801 if ((SC_VN(sc) > 0) && !VALID_OVLAN(OVLAN(sc))) {
7802 PMD_DRV_LOG(NOTICE, "mf_mode=SD vnic_id=%d ovlan=%d",
7803 SC_VN(sc), OVLAN(sc));
7807 if (!VALID_OVLAN(OVLAN(sc)) && mf_info->multi_vnics_mode) {
7809 "mf_mode=SD multi_vnics_mode=%d ovlan=%d",
7810 mf_info->multi_vnics_mode, OVLAN(sc));
7815 * Verify all functions are either MF or SF mode. If MF, make sure
7816 * sure that all non-hidden functions have a valid ovlan. If SF,
7817 * make sure that all non-hidden functions have an invalid ovlan.
7819 FOREACH_ABS_FUNC_IN_PORT(sc, i) {
7820 mf_cfg1 = MFCFG_RD(sc, func_mf_config[i].config);
7821 ovlan1 = MFCFG_RD(sc, func_mf_config[i].e1hov_tag);
7822 if (!(mf_cfg1 & FUNC_MF_CFG_FUNC_HIDE) &&
7823 (((mf_info->multi_vnics_mode)
7824 && !VALID_OVLAN(ovlan1))
7825 || ((!mf_info->multi_vnics_mode)
7826 && VALID_OVLAN(ovlan1)))) {
7828 "mf_mode=SD function %d MF config "
7829 "mismatch, multi_vnics_mode=%d ovlan=%d",
7830 i, mf_info->multi_vnics_mode,
7836 /* Verify all funcs on the same port each have a different ovlan. */
7837 FOREACH_ABS_FUNC_IN_PORT(sc, i) {
7838 mf_cfg1 = MFCFG_RD(sc, func_mf_config[i].config);
7839 ovlan1 = MFCFG_RD(sc, func_mf_config[i].e1hov_tag);
7840 /* iterate from the next function on the port to the max func */
7841 for (j = i + 2; j < MAX_FUNC_NUM; j += 2) {
7843 MFCFG_RD(sc, func_mf_config[j].config);
7845 MFCFG_RD(sc, func_mf_config[j].e1hov_tag);
7846 if (!(mf_cfg1 & FUNC_MF_CFG_FUNC_HIDE)
7847 && VALID_OVLAN(ovlan1)
7848 && !(mf_cfg2 & FUNC_MF_CFG_FUNC_HIDE)
7849 && VALID_OVLAN(ovlan2)
7850 && (ovlan1 == ovlan2)) {
7852 "mf_mode=SD functions %d and %d "
7853 "have the same ovlan (%d)",
7860 /* MULTI_FUNCTION_SD */
7864 static int bnx2x_get_mf_cfg_info(struct bnx2x_softc *sc)
7866 struct bnx2x_mf_info *mf_info = &sc->devinfo.mf_info;
7867 uint32_t val, mac_upper;
7870 /* initialize mf_info defaults */
7871 mf_info->vnics_per_port = 1;
7872 mf_info->multi_vnics_mode = FALSE;
7873 mf_info->path_has_ovlan = FALSE;
7874 mf_info->mf_mode = SINGLE_FUNCTION;
7876 if (!CHIP_IS_MF_CAP(sc)) {
7880 if (sc->devinfo.mf_cfg_base == SHMEM_MF_CFG_ADDR_NONE) {
7881 PMD_DRV_LOG(NOTICE, "Invalid mf_cfg_base!");
7885 /* get the MF mode (switch dependent / independent / single-function) */
7887 val = SHMEM_RD(sc, dev_info.shared_feature_config.config);
7889 switch (val & SHARED_FEAT_CFG_FORCE_SF_MODE_MASK) {
7890 case SHARED_FEAT_CFG_FORCE_SF_MODE_SWITCH_INDEPT:
7893 MFCFG_RD(sc, func_mf_config[SC_ABS_FUNC(sc)].mac_upper);
7895 /* check for legal upper mac bytes */
7896 if (mac_upper != FUNC_MF_CFG_UPPERMAC_DEFAULT) {
7897 mf_info->mf_mode = MULTI_FUNCTION_SI;
7900 "Invalid config for Switch Independent mode");
7905 case SHARED_FEAT_CFG_FORCE_SF_MODE_MF_ALLOWED:
7906 case SHARED_FEAT_CFG_FORCE_SF_MODE_SPIO4:
7908 /* get outer vlan configuration */
7909 val = MFCFG_RD(sc, func_mf_config[SC_ABS_FUNC(sc)].e1hov_tag);
7911 if ((val & FUNC_MF_CFG_E1HOV_TAG_MASK) !=
7912 FUNC_MF_CFG_E1HOV_TAG_DEFAULT) {
7913 mf_info->mf_mode = MULTI_FUNCTION_SD;
7916 "Invalid config for Switch Dependent mode");
7921 case SHARED_FEAT_CFG_FORCE_SF_MODE_FORCED_SF:
7923 /* not in MF mode, vnics_per_port=1 and multi_vnics_mode=FALSE */
7926 case SHARED_FEAT_CFG_FORCE_SF_MODE_AFEX_MODE:
7929 * Mark MF mode as NIV if MCP version includes NPAR-SD support
7930 * and the MAC address is valid.
7933 MFCFG_RD(sc, func_mf_config[SC_ABS_FUNC(sc)].mac_upper);
7935 if ((SHMEM2_HAS(sc, afex_driver_support)) &&
7936 (mac_upper != FUNC_MF_CFG_UPPERMAC_DEFAULT)) {
7937 mf_info->mf_mode = MULTI_FUNCTION_AFEX;
7939 PMD_DRV_LOG(NOTICE, "Invalid config for AFEX mode");
7946 PMD_DRV_LOG(NOTICE, "Unknown MF mode (0x%08x)",
7947 (val & SHARED_FEAT_CFG_FORCE_SF_MODE_MASK));
7952 /* set path mf_mode (which could be different than function mf_mode) */
7953 if (mf_info->mf_mode == MULTI_FUNCTION_SD) {
7954 mf_info->path_has_ovlan = TRUE;
7955 } else if (mf_info->mf_mode == SINGLE_FUNCTION) {
7957 * Decide on path multi vnics mode. If we're not in MF mode and in
7958 * 4-port mode, this is good enough to check vnic-0 of the other port
7961 if (CHIP_PORT_MODE(sc) == CHIP_4_PORT_MODE) {
7962 uint8_t other_port = !(PORT_ID(sc) & 1);
7963 uint8_t abs_func_other_port =
7964 (SC_PATH(sc) + (2 * other_port));
7969 [abs_func_other_port].e1hov_tag);
7971 mf_info->path_has_ovlan = VALID_OVLAN((uint16_t) val);
7975 if (mf_info->mf_mode == SINGLE_FUNCTION) {
7976 /* invalid MF config */
7977 if (SC_VN(sc) >= 1) {
7978 PMD_DRV_LOG(NOTICE, "VNIC ID >= 1 in SF mode");
7985 /* get the MF configuration */
7986 mf_info->mf_config[SC_VN(sc)] =
7987 MFCFG_RD(sc, func_mf_config[SC_ABS_FUNC(sc)].config);
7989 switch (mf_info->mf_mode) {
7990 case MULTI_FUNCTION_SD:
7992 bnx2x_get_shmem_mf_cfg_info_sd(sc);
7995 case MULTI_FUNCTION_SI:
7997 bnx2x_get_shmem_mf_cfg_info_si(sc);
8000 case MULTI_FUNCTION_AFEX:
8002 bnx2x_get_shmem_mf_cfg_info_niv(sc);
8007 PMD_DRV_LOG(NOTICE, "Get MF config failed (mf_mode=0x%08x)",
8012 /* get the congestion management parameters */
8015 FOREACH_ABS_FUNC_IN_PORT(sc, i) {
8016 /* get min/max bw */
8017 val = MFCFG_RD(sc, func_mf_config[i].config);
8018 mf_info->min_bw[vnic] =
8019 ((val & FUNC_MF_CFG_MIN_BW_MASK) >>
8020 FUNC_MF_CFG_MIN_BW_SHIFT);
8021 mf_info->max_bw[vnic] =
8022 ((val & FUNC_MF_CFG_MAX_BW_MASK) >>
8023 FUNC_MF_CFG_MAX_BW_SHIFT);
8027 return bnx2x_check_valid_mf_cfg(sc);
8030 static int bnx2x_get_shmem_info(struct bnx2x_softc *sc)
8033 uint32_t mac_hi, mac_lo, val;
8035 PMD_INIT_FUNC_TRACE();
8038 mac_hi = mac_lo = 0;
8040 sc->link_params.sc = sc;
8041 sc->link_params.port = port;
8043 /* get the hardware config info */
8044 sc->devinfo.hw_config = SHMEM_RD(sc, dev_info.shared_hw_config.config);
8045 sc->devinfo.hw_config2 =
8046 SHMEM_RD(sc, dev_info.shared_hw_config.config2);
8048 sc->link_params.hw_led_mode =
8049 ((sc->devinfo.hw_config & SHARED_HW_CFG_LED_MODE_MASK) >>
8050 SHARED_HW_CFG_LED_MODE_SHIFT);
8052 /* get the port feature config */
8054 SHMEM_RD(sc, dev_info.port_feature_config[port].config);
8056 /* get the link params */
8057 sc->link_params.speed_cap_mask[ELINK_INT_PHY] =
8058 SHMEM_RD(sc, dev_info.port_hw_config[port].speed_capability_mask)
8059 & PORT_HW_CFG_SPEED_CAPABILITY_D0_MASK;
8060 sc->link_params.speed_cap_mask[ELINK_EXT_PHY1] =
8061 SHMEM_RD(sc, dev_info.port_hw_config[port].speed_capability_mask2)
8062 & PORT_HW_CFG_SPEED_CAPABILITY_D0_MASK;
8064 /* get the lane config */
8065 sc->link_params.lane_config =
8066 SHMEM_RD(sc, dev_info.port_hw_config[port].lane_config);
8068 /* get the link config */
8069 val = SHMEM_RD(sc, dev_info.port_feature_config[port].link_config);
8070 sc->port.link_config[ELINK_INT_PHY] = val;
8071 sc->link_params.switch_cfg = (val & PORT_FEATURE_CONNECTED_SWITCH_MASK);
8072 sc->port.link_config[ELINK_EXT_PHY1] =
8073 SHMEM_RD(sc, dev_info.port_feature_config[port].link_config2);
8075 /* get the override preemphasis flag and enable it or turn it off */
8076 val = SHMEM_RD(sc, dev_info.shared_feature_config.config);
8077 if (val & SHARED_FEAT_CFG_OVERRIDE_PREEMPHASIS_CFG_ENABLED) {
8078 sc->link_params.feature_config_flags |=
8079 ELINK_FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED;
8081 sc->link_params.feature_config_flags &=
8082 ~ELINK_FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED;
8085 /* get the initial value of the link params */
8086 sc->link_params.multi_phy_config =
8087 SHMEM_RD(sc, dev_info.port_hw_config[port].multi_phy_config);
8089 /* get external phy info */
8090 sc->port.ext_phy_config =
8091 SHMEM_RD(sc, dev_info.port_hw_config[port].external_phy_config);
8093 /* get the multifunction configuration */
8094 bnx2x_get_mf_cfg_info(sc);
8096 /* get the mac address */
8099 MFCFG_RD(sc, func_mf_config[SC_ABS_FUNC(sc)].mac_upper);
8101 MFCFG_RD(sc, func_mf_config[SC_ABS_FUNC(sc)].mac_lower);
8103 mac_hi = SHMEM_RD(sc, dev_info.port_hw_config[port].mac_upper);
8104 mac_lo = SHMEM_RD(sc, dev_info.port_hw_config[port].mac_lower);
8107 if ((mac_lo == 0) && (mac_hi == 0)) {
8108 *sc->mac_addr_str = 0;
8109 PMD_DRV_LOG(NOTICE, "No Ethernet address programmed!");
8111 sc->link_params.mac_addr[0] = (uint8_t) (mac_hi >> 8);
8112 sc->link_params.mac_addr[1] = (uint8_t) (mac_hi);
8113 sc->link_params.mac_addr[2] = (uint8_t) (mac_lo >> 24);
8114 sc->link_params.mac_addr[3] = (uint8_t) (mac_lo >> 16);
8115 sc->link_params.mac_addr[4] = (uint8_t) (mac_lo >> 8);
8116 sc->link_params.mac_addr[5] = (uint8_t) (mac_lo);
8117 snprintf(sc->mac_addr_str, sizeof(sc->mac_addr_str),
8118 "%02x:%02x:%02x:%02x:%02x:%02x",
8119 sc->link_params.mac_addr[0],
8120 sc->link_params.mac_addr[1],
8121 sc->link_params.mac_addr[2],
8122 sc->link_params.mac_addr[3],
8123 sc->link_params.mac_addr[4],
8124 sc->link_params.mac_addr[5]);
8125 PMD_DRV_LOG(DEBUG, "Ethernet address: %s", sc->mac_addr_str);
8131 static void bnx2x_media_detect(struct bnx2x_softc *sc)
8133 uint32_t phy_idx = bnx2x_get_cur_phy_idx(sc);
8134 switch (sc->link_params.phy[phy_idx].media_type) {
8135 case ELINK_ETH_PHY_SFPP_10G_FIBER:
8136 case ELINK_ETH_PHY_SFP_1G_FIBER:
8137 case ELINK_ETH_PHY_XFP_FIBER:
8138 case ELINK_ETH_PHY_KR:
8139 case ELINK_ETH_PHY_CX4:
8140 PMD_DRV_LOG(INFO, "Found 10GBase-CX4 media.");
8141 sc->media = IFM_10G_CX4;
8143 case ELINK_ETH_PHY_DA_TWINAX:
8144 PMD_DRV_LOG(INFO, "Found 10Gb Twinax media.");
8145 sc->media = IFM_10G_TWINAX;
8147 case ELINK_ETH_PHY_BASE_T:
8148 PMD_DRV_LOG(INFO, "Found 10GBase-T media.");
8149 sc->media = IFM_10G_T;
8151 case ELINK_ETH_PHY_NOT_PRESENT:
8152 PMD_DRV_LOG(INFO, "Media not present.");
8155 case ELINK_ETH_PHY_UNSPECIFIED:
8157 PMD_DRV_LOG(INFO, "Unknown media!");
8163 #define GET_FIELD(value, fname) \
8164 (((value) & (fname##_MASK)) >> (fname##_SHIFT))
8165 #define IGU_FID(val) GET_FIELD((val), IGU_REG_MAPPING_MEMORY_FID)
8166 #define IGU_VEC(val) GET_FIELD((val), IGU_REG_MAPPING_MEMORY_VECTOR)
8168 static int bnx2x_get_igu_cam_info(struct bnx2x_softc *sc)
8170 int pfid = SC_FUNC(sc);
8173 uint8_t fid, igu_sb_cnt = 0;
8175 sc->igu_base_sb = 0xff;
8177 if (CHIP_INT_MODE_IS_BC(sc)) {
8179 igu_sb_cnt = sc->igu_sb_cnt;
8180 sc->igu_base_sb = ((CHIP_IS_MODE_4_PORT(sc) ? pfid : vn) *
8182 sc->igu_dsb_id = (E1HVN_MAX * FP_SB_MAX_E1x +
8183 (CHIP_IS_MODE_4_PORT(sc) ? pfid : vn));
8187 /* IGU in normal mode - read CAM */
8189 igu_sb_id < IGU_REG_MAPPING_MEMORY_SIZE; igu_sb_id++) {
8190 val = REG_RD(sc, IGU_REG_MAPPING_MEMORY + igu_sb_id * 4);
8191 if (!(val & IGU_REG_MAPPING_MEMORY_VALID)) {
8195 if ((fid & IGU_FID_ENCODE_IS_PF)) {
8196 if ((fid & IGU_FID_PF_NUM_MASK) != pfid) {
8199 if (IGU_VEC(val) == 0) {
8200 /* default status block */
8201 sc->igu_dsb_id = igu_sb_id;
8203 if (sc->igu_base_sb == 0xff) {
8204 sc->igu_base_sb = igu_sb_id;
8212 * Due to new PF resource allocation by MFW T7.4 and above, it's optional
8213 * that number of CAM entries will not be equal to the value advertised in
8214 * PCI. Driver should use the minimal value of both as the actual status
8217 sc->igu_sb_cnt = min(sc->igu_sb_cnt, igu_sb_cnt);
8219 if (igu_sb_cnt == 0) {
8220 PMD_DRV_LOG(ERR, "CAM configuration error");
8228 * Gather various information from the device config space, the device itself,
8229 * shmem, and the user input.
8231 static int bnx2x_get_device_info(struct bnx2x_softc *sc)
8236 /* get the chip revision (chip metal comes from pci config space) */
8237 sc->devinfo.chip_id = sc->link_params.chip_id =
8238 (((REG_RD(sc, MISC_REG_CHIP_NUM) & 0xffff) << 16) |
8239 ((REG_RD(sc, MISC_REG_CHIP_REV) & 0xf) << 12) |
8240 (((REG_RD(sc, PCICFG_OFFSET + PCI_ID_VAL3) >> 24) & 0xf) << 4) |
8241 ((REG_RD(sc, MISC_REG_BOND_ID) & 0xf) << 0));
8243 /* force 57811 according to MISC register */
8244 if (REG_RD(sc, MISC_REG_CHIP_TYPE) & MISC_REG_CHIP_TYPE_57811_MASK) {
8245 if (CHIP_IS_57810(sc)) {
8246 sc->devinfo.chip_id = ((CHIP_NUM_57811 << 16) |
8248 devinfo.chip_id & 0x0000ffff));
8249 } else if (CHIP_IS_57810_MF(sc)) {
8250 sc->devinfo.chip_id = ((CHIP_NUM_57811_MF << 16) |
8252 devinfo.chip_id & 0x0000ffff));
8254 sc->devinfo.chip_id |= 0x1;
8258 "chip_id=0x%08x (num=0x%04x rev=0x%01x metal=0x%02x bond=0x%01x)",
8259 sc->devinfo.chip_id,
8260 ((sc->devinfo.chip_id >> 16) & 0xffff),
8261 ((sc->devinfo.chip_id >> 12) & 0xf),
8262 ((sc->devinfo.chip_id >> 4) & 0xff),
8263 ((sc->devinfo.chip_id >> 0) & 0xf));
8265 val = (REG_RD(sc, 0x2874) & 0x55);
8266 if ((sc->devinfo.chip_id & 0x1) || (CHIP_IS_E1H(sc) && (val == 0x55))) {
8267 sc->flags |= BNX2X_ONE_PORT_FLAG;
8268 PMD_DRV_LOG(DEBUG, "single port device");
8271 /* set the doorbell size */
8272 sc->doorbell_size = (1 << BNX2X_DB_SHIFT);
8274 /* determine whether the device is in 2 port or 4 port mode */
8275 sc->devinfo.chip_port_mode = CHIP_PORT_MODE_NONE; /* E1h */
8276 if (CHIP_IS_E2E3(sc)) {
8278 * Read port4mode_en_ovwr[0]:
8279 * If 1, four port mode is in port4mode_en_ovwr[1].
8280 * If 0, four port mode is in port4mode_en[0].
8282 val = REG_RD(sc, MISC_REG_PORT4MODE_EN_OVWR);
8284 val = ((val >> 1) & 1);
8286 val = REG_RD(sc, MISC_REG_PORT4MODE_EN);
8289 sc->devinfo.chip_port_mode =
8290 (val) ? CHIP_4_PORT_MODE : CHIP_2_PORT_MODE;
8292 PMD_DRV_LOG(DEBUG, "Port mode = %s", (val) ? "4" : "2");
8295 /* get the function and path info for the device */
8296 bnx2x_get_function_num(sc);
8298 /* get the shared memory base address */
8299 sc->devinfo.shmem_base =
8300 sc->link_params.shmem_base = REG_RD(sc, MISC_REG_SHARED_MEM_ADDR);
8301 sc->devinfo.shmem2_base =
8302 REG_RD(sc, (SC_PATH(sc) ? MISC_REG_GENERIC_CR_1 :
8303 MISC_REG_GENERIC_CR_0));
8305 if (!sc->devinfo.shmem_base) {
8306 /* this should ONLY prevent upcoming shmem reads */
8307 PMD_DRV_LOG(INFO, "MCP not active");
8308 sc->flags |= BNX2X_NO_MCP_FLAG;
8312 /* make sure the shared memory contents are valid */
8313 val = SHMEM_RD(sc, validity_map[SC_PORT(sc)]);
8314 if ((val & (SHR_MEM_VALIDITY_DEV_INFO | SHR_MEM_VALIDITY_MB)) !=
8315 (SHR_MEM_VALIDITY_DEV_INFO | SHR_MEM_VALIDITY_MB)) {
8316 PMD_DRV_LOG(NOTICE, "Invalid SHMEM validity signature: 0x%08x",
8321 /* get the bootcode version */
8322 sc->devinfo.bc_ver = SHMEM_RD(sc, dev_info.bc_rev);
8323 snprintf(sc->devinfo.bc_ver_str,
8324 sizeof(sc->devinfo.bc_ver_str),
8326 ((sc->devinfo.bc_ver >> 24) & 0xff),
8327 ((sc->devinfo.bc_ver >> 16) & 0xff),
8328 ((sc->devinfo.bc_ver >> 8) & 0xff));
8329 PMD_DRV_LOG(INFO, "Bootcode version: %s", sc->devinfo.bc_ver_str);
8331 /* get the bootcode shmem address */
8332 sc->devinfo.mf_cfg_base = bnx2x_get_shmem_mf_cfg_base(sc);
8334 /* clean indirect addresses as they're not used */
8335 pci_write_long(sc, PCICFG_GRC_ADDRESS, 0);
8337 REG_WR(sc, PXP2_REG_PGL_ADDR_88_F0, 0);
8338 REG_WR(sc, PXP2_REG_PGL_ADDR_8C_F0, 0);
8339 REG_WR(sc, PXP2_REG_PGL_ADDR_90_F0, 0);
8340 REG_WR(sc, PXP2_REG_PGL_ADDR_94_F0, 0);
8341 if (CHIP_IS_E1x(sc)) {
8342 REG_WR(sc, PXP2_REG_PGL_ADDR_88_F1, 0);
8343 REG_WR(sc, PXP2_REG_PGL_ADDR_8C_F1, 0);
8344 REG_WR(sc, PXP2_REG_PGL_ADDR_90_F1, 0);
8345 REG_WR(sc, PXP2_REG_PGL_ADDR_94_F1, 0);
8349 * Enable internal target-read (in case we are probed after PF
8350 * FLR). Must be done prior to any BAR read access. Only for
8353 if (!CHIP_IS_E1x(sc)) {
8354 REG_WR(sc, PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_READ,
8359 /* get the nvram size */
8360 val = REG_RD(sc, MCP_REG_MCPR_NVM_CFG4);
8361 sc->devinfo.flash_size =
8362 (NVRAM_1MB_SIZE << (val & MCPR_NVM_CFG4_FLASH_SIZE));
8364 bnx2x_set_power_state(sc, PCI_PM_D0);
8365 /* get various configuration parameters from shmem */
8366 bnx2x_get_shmem_info(sc);
8368 /* initialize IGU parameters */
8369 if (CHIP_IS_E1x(sc)) {
8370 sc->devinfo.int_block = INT_BLOCK_HC;
8371 sc->igu_dsb_id = DEF_SB_IGU_ID;
8372 sc->igu_base_sb = 0;
8374 sc->devinfo.int_block = INT_BLOCK_IGU;
8376 /* do not allow device reset during IGU info preocessing */
8377 bnx2x_acquire_hw_lock(sc, HW_LOCK_RESOURCE_RESET);
8379 val = REG_RD(sc, IGU_REG_BLOCK_CONFIGURATION);
8381 if (val & IGU_BLOCK_CONFIGURATION_REG_BACKWARD_COMP_EN) {
8384 val &= ~(IGU_BLOCK_CONFIGURATION_REG_BACKWARD_COMP_EN);
8385 REG_WR(sc, IGU_REG_BLOCK_CONFIGURATION, val);
8386 REG_WR(sc, IGU_REG_RESET_MEMORIES, 0x7f);
8388 while (tout && REG_RD(sc, IGU_REG_RESET_MEMORIES)) {
8393 if (REG_RD(sc, IGU_REG_RESET_MEMORIES)) {
8395 "FORCING IGU Normal Mode failed!!!");
8396 bnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_RESET);
8401 if (val & IGU_BLOCK_CONFIGURATION_REG_BACKWARD_COMP_EN) {
8402 PMD_DRV_LOG(DEBUG, "IGU Backward Compatible Mode");
8403 sc->devinfo.int_block |= INT_BLOCK_MODE_BW_COMP;
8405 PMD_DRV_LOG(DEBUG, "IGU Normal Mode");
8408 rc = bnx2x_get_igu_cam_info(sc);
8410 bnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_RESET);
8418 * Get base FW non-default (fast path) status block ID. This value is
8419 * used to initialize the fw_sb_id saved on the fp/queue structure to
8420 * determine the id used by the FW.
8422 if (CHIP_IS_E1x(sc)) {
8424 ((SC_PORT(sc) * FP_SB_MAX_E1x) + SC_L_ID(sc));
8427 * 57712+ - We currently use one FW SB per IGU SB (Rx and Tx of
8428 * the same queue are indicated on the same IGU SB). So we prefer
8429 * FW and IGU SBs to be the same value.
8431 sc->base_fw_ndsb = sc->igu_base_sb;
8434 elink_phy_probe(&sc->link_params);
8440 bnx2x_link_settings_supported(struct bnx2x_softc *sc, uint32_t switch_cfg)
8442 uint32_t cfg_size = 0;
8444 uint8_t port = SC_PORT(sc);
8446 /* aggregation of supported attributes of all external phys */
8447 sc->port.supported[0] = 0;
8448 sc->port.supported[1] = 0;
8450 switch (sc->link_params.num_phys) {
8452 sc->port.supported[0] =
8453 sc->link_params.phy[ELINK_INT_PHY].supported;
8457 sc->port.supported[0] =
8458 sc->link_params.phy[ELINK_EXT_PHY1].supported;
8462 if (sc->link_params.multi_phy_config &
8463 PORT_HW_CFG_PHY_SWAPPED_ENABLED) {
8464 sc->port.supported[1] =
8465 sc->link_params.phy[ELINK_EXT_PHY1].supported;
8466 sc->port.supported[0] =
8467 sc->link_params.phy[ELINK_EXT_PHY2].supported;
8469 sc->port.supported[0] =
8470 sc->link_params.phy[ELINK_EXT_PHY1].supported;
8471 sc->port.supported[1] =
8472 sc->link_params.phy[ELINK_EXT_PHY2].supported;
8478 if (!(sc->port.supported[0] || sc->port.supported[1])) {
8480 "Invalid phy config in NVRAM (PHY1=0x%08x PHY2=0x%08x)",
8482 dev_info.port_hw_config
8483 [port].external_phy_config),
8485 dev_info.port_hw_config
8486 [port].external_phy_config2));
8491 sc->port.phy_addr = REG_RD(sc, MISC_REG_WC0_CTRL_PHY_ADDR);
8493 switch (switch_cfg) {
8494 case ELINK_SWITCH_CFG_1G:
8497 NIG_REG_SERDES0_CTRL_PHY_ADDR + port * 0x10);
8499 case ELINK_SWITCH_CFG_10G:
8502 NIG_REG_XGXS0_CTRL_PHY_ADDR + port * 0x18);
8506 "Invalid switch config in"
8507 "link_config=0x%08x",
8508 sc->port.link_config[0]);
8513 PMD_DRV_LOG(INFO, "PHY addr 0x%08x", sc->port.phy_addr);
8515 /* mask what we support according to speed_cap_mask per configuration */
8516 for (idx = 0; idx < cfg_size; idx++) {
8517 if (!(sc->link_params.speed_cap_mask[idx] &
8518 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_HALF)) {
8519 sc->port.supported[idx] &=
8520 ~ELINK_SUPPORTED_10baseT_Half;
8523 if (!(sc->link_params.speed_cap_mask[idx] &
8524 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL)) {
8525 sc->port.supported[idx] &=
8526 ~ELINK_SUPPORTED_10baseT_Full;
8529 if (!(sc->link_params.speed_cap_mask[idx] &
8530 PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_HALF)) {
8531 sc->port.supported[idx] &=
8532 ~ELINK_SUPPORTED_100baseT_Half;
8535 if (!(sc->link_params.speed_cap_mask[idx] &
8536 PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_FULL)) {
8537 sc->port.supported[idx] &=
8538 ~ELINK_SUPPORTED_100baseT_Full;
8541 if (!(sc->link_params.speed_cap_mask[idx] &
8542 PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)) {
8543 sc->port.supported[idx] &=
8544 ~ELINK_SUPPORTED_1000baseT_Full;
8547 if (!(sc->link_params.speed_cap_mask[idx] &
8548 PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G)) {
8549 sc->port.supported[idx] &=
8550 ~ELINK_SUPPORTED_2500baseX_Full;
8553 if (!(sc->link_params.speed_cap_mask[idx] &
8554 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)) {
8555 sc->port.supported[idx] &=
8556 ~ELINK_SUPPORTED_10000baseT_Full;
8559 if (!(sc->link_params.speed_cap_mask[idx] &
8560 PORT_HW_CFG_SPEED_CAPABILITY_D0_20G)) {
8561 sc->port.supported[idx] &=
8562 ~ELINK_SUPPORTED_20000baseKR2_Full;
8566 PMD_DRV_LOG(INFO, "PHY supported 0=0x%08x 1=0x%08x",
8567 sc->port.supported[0], sc->port.supported[1]);
8570 static void bnx2x_link_settings_requested(struct bnx2x_softc *sc)
8572 uint32_t link_config;
8574 uint32_t cfg_size = 0;
8576 sc->port.advertising[0] = 0;
8577 sc->port.advertising[1] = 0;
8579 switch (sc->link_params.num_phys) {
8589 for (idx = 0; idx < cfg_size; idx++) {
8590 sc->link_params.req_duplex[idx] = DUPLEX_FULL;
8591 link_config = sc->port.link_config[idx];
8593 switch (link_config & PORT_FEATURE_LINK_SPEED_MASK) {
8594 case PORT_FEATURE_LINK_SPEED_AUTO:
8595 if (sc->port.supported[idx] & ELINK_SUPPORTED_Autoneg) {
8596 sc->link_params.req_line_speed[idx] =
8597 ELINK_SPEED_AUTO_NEG;
8598 sc->port.advertising[idx] |=
8599 sc->port.supported[idx];
8600 if (sc->link_params.phy[ELINK_EXT_PHY1].type ==
8601 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X84833)
8602 sc->port.advertising[idx] |=
8603 (ELINK_SUPPORTED_100baseT_Half |
8604 ELINK_SUPPORTED_100baseT_Full);
8606 /* force 10G, no AN */
8607 sc->link_params.req_line_speed[idx] =
8609 sc->port.advertising[idx] |=
8610 (ADVERTISED_10000baseT_Full |
8616 case PORT_FEATURE_LINK_SPEED_10M_FULL:
8618 port.supported[idx] & ELINK_SUPPORTED_10baseT_Full)
8620 sc->link_params.req_line_speed[idx] =
8622 sc->port.advertising[idx] |=
8623 (ADVERTISED_10baseT_Full | ADVERTISED_TP);
8626 "Invalid NVRAM config link_config=0x%08x "
8627 "speed_cap_mask=0x%08x",
8630 link_params.speed_cap_mask[idx]);
8635 case PORT_FEATURE_LINK_SPEED_10M_HALF:
8637 port.supported[idx] & ELINK_SUPPORTED_10baseT_Half)
8639 sc->link_params.req_line_speed[idx] =
8641 sc->link_params.req_duplex[idx] = DUPLEX_HALF;
8642 sc->port.advertising[idx] |=
8643 (ADVERTISED_10baseT_Half | ADVERTISED_TP);
8646 "Invalid NVRAM config link_config=0x%08x "
8647 "speed_cap_mask=0x%08x",
8650 link_params.speed_cap_mask[idx]);
8655 case PORT_FEATURE_LINK_SPEED_100M_FULL:
8657 port.supported[idx] & ELINK_SUPPORTED_100baseT_Full)
8659 sc->link_params.req_line_speed[idx] =
8661 sc->port.advertising[idx] |=
8662 (ADVERTISED_100baseT_Full | ADVERTISED_TP);
8665 "Invalid NVRAM config link_config=0x%08x "
8666 "speed_cap_mask=0x%08x",
8669 link_params.speed_cap_mask[idx]);
8674 case PORT_FEATURE_LINK_SPEED_100M_HALF:
8676 port.supported[idx] & ELINK_SUPPORTED_100baseT_Half)
8678 sc->link_params.req_line_speed[idx] =
8680 sc->link_params.req_duplex[idx] = DUPLEX_HALF;
8681 sc->port.advertising[idx] |=
8682 (ADVERTISED_100baseT_Half | ADVERTISED_TP);
8685 "Invalid NVRAM config link_config=0x%08x "
8686 "speed_cap_mask=0x%08x",
8689 link_params.speed_cap_mask[idx]);
8694 case PORT_FEATURE_LINK_SPEED_1G:
8695 if (sc->port.supported[idx] &
8696 ELINK_SUPPORTED_1000baseT_Full) {
8697 sc->link_params.req_line_speed[idx] =
8699 sc->port.advertising[idx] |=
8700 (ADVERTISED_1000baseT_Full | ADVERTISED_TP);
8703 "Invalid NVRAM config link_config=0x%08x "
8704 "speed_cap_mask=0x%08x",
8707 link_params.speed_cap_mask[idx]);
8712 case PORT_FEATURE_LINK_SPEED_2_5G:
8713 if (sc->port.supported[idx] &
8714 ELINK_SUPPORTED_2500baseX_Full) {
8715 sc->link_params.req_line_speed[idx] =
8717 sc->port.advertising[idx] |=
8718 (ADVERTISED_2500baseX_Full | ADVERTISED_TP);
8721 "Invalid NVRAM config link_config=0x%08x "
8722 "speed_cap_mask=0x%08x",
8725 link_params.speed_cap_mask[idx]);
8730 case PORT_FEATURE_LINK_SPEED_10G_CX4:
8731 if (sc->port.supported[idx] &
8732 ELINK_SUPPORTED_10000baseT_Full) {
8733 sc->link_params.req_line_speed[idx] =
8735 sc->port.advertising[idx] |=
8736 (ADVERTISED_10000baseT_Full |
8740 "Invalid NVRAM config link_config=0x%08x "
8741 "speed_cap_mask=0x%08x",
8744 link_params.speed_cap_mask[idx]);
8749 case PORT_FEATURE_LINK_SPEED_20G:
8750 sc->link_params.req_line_speed[idx] = ELINK_SPEED_20000;
8755 "Invalid NVRAM config link_config=0x%08x "
8756 "speed_cap_mask=0x%08x", link_config,
8757 sc->link_params.speed_cap_mask[idx]);
8758 sc->link_params.req_line_speed[idx] =
8759 ELINK_SPEED_AUTO_NEG;
8760 sc->port.advertising[idx] = sc->port.supported[idx];
8764 sc->link_params.req_flow_ctrl[idx] =
8765 (link_config & PORT_FEATURE_FLOW_CONTROL_MASK);
8767 if (sc->link_params.req_flow_ctrl[idx] == ELINK_FLOW_CTRL_AUTO) {
8770 port.supported[idx] & ELINK_SUPPORTED_Autoneg)) {
8771 sc->link_params.req_flow_ctrl[idx] =
8772 ELINK_FLOW_CTRL_NONE;
8774 bnx2x_set_requested_fc(sc);
8780 static void bnx2x_get_phy_info(struct bnx2x_softc *sc)
8782 uint8_t port = SC_PORT(sc);
8785 PMD_INIT_FUNC_TRACE();
8787 /* shmem data already read in bnx2x_get_shmem_info() */
8789 bnx2x_link_settings_supported(sc, sc->link_params.switch_cfg);
8790 bnx2x_link_settings_requested(sc);
8792 /* configure link feature according to nvram value */
8794 (((SHMEM_RD(sc, dev_info.port_feature_config[port].eee_power_mode))
8795 & PORT_FEAT_CFG_EEE_POWER_MODE_MASK) >>
8796 PORT_FEAT_CFG_EEE_POWER_MODE_SHIFT);
8797 if (eee_mode != PORT_FEAT_CFG_EEE_POWER_MODE_DISABLED) {
8798 sc->link_params.eee_mode = (ELINK_EEE_MODE_ADV_LPI |
8799 ELINK_EEE_MODE_ENABLE_LPI |
8800 ELINK_EEE_MODE_OUTPUT_TIME);
8802 sc->link_params.eee_mode = 0;
8805 /* get the media type */
8806 bnx2x_media_detect(sc);
8809 static void bnx2x_set_modes_bitmap(struct bnx2x_softc *sc)
8811 uint32_t flags = MODE_ASIC | MODE_PORT2;
8813 if (CHIP_IS_E2(sc)) {
8815 } else if (CHIP_IS_E3(sc)) {
8817 if (CHIP_REV(sc) == CHIP_REV_Ax) {
8818 flags |= MODE_E3_A0;
8819 } else { /*if (CHIP_REV(sc) == CHIP_REV_Bx) */
8821 flags |= MODE_E3_B0 | MODE_COS3;
8827 switch (sc->devinfo.mf_info.mf_mode) {
8828 case MULTI_FUNCTION_SD:
8829 flags |= MODE_MF_SD;
8831 case MULTI_FUNCTION_SI:
8832 flags |= MODE_MF_SI;
8834 case MULTI_FUNCTION_AFEX:
8835 flags |= MODE_MF_AFEX;
8842 #if defined(__LITTLE_ENDIAN)
8843 flags |= MODE_LITTLE_ENDIAN;
8844 #else /* __BIG_ENDIAN */
8845 flags |= MODE_BIG_ENDIAN;
8848 INIT_MODE_FLAGS(sc) = flags;
8851 int bnx2x_alloc_hsi_mem(struct bnx2x_softc *sc)
8853 struct bnx2x_fastpath *fp;
8858 /************************/
8859 /* DEFAULT STATUS BLOCK */
8860 /************************/
8862 if (bnx2x_dma_alloc(sc, sizeof(struct host_sp_status_block),
8863 &sc->def_sb_dma, "def_sb",
8864 RTE_CACHE_LINE_SIZE) != 0) {
8869 (struct host_sp_status_block *)sc->def_sb_dma.vaddr;
8874 if (bnx2x_dma_alloc(sc, BNX2X_PAGE_SIZE,
8875 &sc->eq_dma, "ev_queue",
8876 RTE_CACHE_LINE_SIZE) != 0) {
8881 sc->eq = (union event_ring_elem *)sc->eq_dma.vaddr;
8887 if (bnx2x_dma_alloc(sc, sizeof(struct bnx2x_slowpath),
8889 RTE_CACHE_LINE_SIZE) != 0) {
8895 sc->sp = (struct bnx2x_slowpath *)sc->sp_dma.vaddr;
8897 /*******************/
8898 /* SLOW PATH QUEUE */
8899 /*******************/
8901 if (bnx2x_dma_alloc(sc, BNX2X_PAGE_SIZE,
8902 &sc->spq_dma, "sp_queue",
8903 RTE_CACHE_LINE_SIZE) != 0) {
8910 sc->spq = (struct eth_spe *)sc->spq_dma.vaddr;
8912 /***************************/
8913 /* FW DECOMPRESSION BUFFER */
8914 /***************************/
8916 if (bnx2x_dma_alloc(sc, FW_BUF_SIZE, &sc->gz_buf_dma,
8917 "fw_dec_buf", RTE_CACHE_LINE_SIZE) != 0) {
8925 sc->gz_buf = (void *)sc->gz_buf_dma.vaddr;
8932 /* allocate DMA memory for each fastpath structure */
8933 for (i = 0; i < sc->num_queues; i++) {
8938 /*******************/
8939 /* FP STATUS BLOCK */
8940 /*******************/
8942 snprintf(buf, sizeof(buf), "fp_%d_sb", i);
8943 if (bnx2x_dma_alloc(sc, sizeof(union bnx2x_host_hc_status_block),
8944 &fp->sb_dma, buf, RTE_CACHE_LINE_SIZE) != 0) {
8945 PMD_DRV_LOG(NOTICE, "Failed to alloc %s", buf);
8948 if (CHIP_IS_E2E3(sc)) {
8949 fp->status_block.e2_sb =
8950 (struct host_hc_status_block_e2 *)
8953 fp->status_block.e1x_sb =
8954 (struct host_hc_status_block_e1x *)
8963 void bnx2x_free_hsi_mem(struct bnx2x_softc *sc)
8965 struct bnx2x_fastpath *fp;
8968 for (i = 0; i < sc->num_queues; i++) {
8971 /*******************/
8972 /* FP STATUS BLOCK */
8973 /*******************/
8975 memset(&fp->status_block, 0, sizeof(fp->status_block));
8978 /***************************/
8979 /* FW DECOMPRESSION BUFFER */
8980 /***************************/
8984 /*******************/
8985 /* SLOW PATH QUEUE */
8986 /*******************/
9002 /************************/
9003 /* DEFAULT STATUS BLOCK */
9004 /************************/
9011 * Previous driver DMAE transaction may have occurred when pre-boot stage
9012 * ended and boot began. This would invalidate the addresses of the
9013 * transaction, resulting in was-error bit set in the PCI causing all
9014 * hw-to-host PCIe transactions to timeout. If this happened we want to clear
9015 * the interrupt which detected this from the pglueb and the was-done bit
9017 static void bnx2x_prev_interrupted_dmae(struct bnx2x_softc *sc)
9021 if (!CHIP_IS_E1x(sc)) {
9022 val = REG_RD(sc, PGLUE_B_REG_PGLUE_B_INT_STS);
9023 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_WAS_ERROR_ATTN) {
9024 REG_WR(sc, PGLUE_B_REG_WAS_ERROR_PF_7_0_CLR,
9030 static int bnx2x_prev_mcp_done(struct bnx2x_softc *sc)
9032 uint32_t rc = bnx2x_fw_command(sc, DRV_MSG_CODE_UNLOAD_DONE,
9033 DRV_MSG_CODE_UNLOAD_SKIP_LINK_RESET);
9035 PMD_DRV_LOG(NOTICE, "MCP response failure, aborting");
9042 static struct bnx2x_prev_list_node *bnx2x_prev_path_get_entry(struct bnx2x_softc *sc)
9044 struct bnx2x_prev_list_node *tmp;
9046 LIST_FOREACH(tmp, &bnx2x_prev_list, node) {
9047 if ((sc->pcie_bus == tmp->bus) &&
9048 (sc->pcie_device == tmp->slot) &&
9049 (SC_PATH(sc) == tmp->path)) {
9057 static uint8_t bnx2x_prev_is_path_marked(struct bnx2x_softc *sc)
9059 struct bnx2x_prev_list_node *tmp;
9062 rte_spinlock_lock(&bnx2x_prev_mtx);
9064 tmp = bnx2x_prev_path_get_entry(sc);
9068 "Path %d/%d/%d was marked by AER",
9069 sc->pcie_bus, sc->pcie_device, SC_PATH(sc));
9073 "Path %d/%d/%d was already cleaned from previous drivers",
9074 sc->pcie_bus, sc->pcie_device, SC_PATH(sc));
9078 rte_spinlock_unlock(&bnx2x_prev_mtx);
9083 static int bnx2x_prev_mark_path(struct bnx2x_softc *sc, uint8_t after_undi)
9085 struct bnx2x_prev_list_node *tmp;
9087 rte_spinlock_lock(&bnx2x_prev_mtx);
9089 /* Check whether the entry for this path already exists */
9090 tmp = bnx2x_prev_path_get_entry(sc);
9094 "Re-marking AER in path %d/%d/%d",
9095 sc->pcie_bus, sc->pcie_device, SC_PATH(sc));
9098 "Removing AER indication from path %d/%d/%d",
9099 sc->pcie_bus, sc->pcie_device, SC_PATH(sc));
9103 rte_spinlock_unlock(&bnx2x_prev_mtx);
9107 rte_spinlock_unlock(&bnx2x_prev_mtx);
9109 /* Create an entry for this path and add it */
9110 tmp = rte_malloc("", sizeof(struct bnx2x_prev_list_node),
9111 RTE_CACHE_LINE_SIZE);
9113 PMD_DRV_LOG(NOTICE, "Failed to allocate 'bnx2x_prev_list_node'");
9117 tmp->bus = sc->pcie_bus;
9118 tmp->slot = sc->pcie_device;
9119 tmp->path = SC_PATH(sc);
9121 tmp->undi = after_undi ? (1 << SC_PORT(sc)) : 0;
9123 rte_spinlock_lock(&bnx2x_prev_mtx);
9125 LIST_INSERT_HEAD(&bnx2x_prev_list, tmp, node);
9127 rte_spinlock_unlock(&bnx2x_prev_mtx);
9132 static int bnx2x_do_flr(struct bnx2x_softc *sc)
9136 /* only E2 and onwards support FLR */
9137 if (CHIP_IS_E1x(sc)) {
9138 PMD_DRV_LOG(WARNING, "FLR not supported in E1H");
9142 /* only bootcode REQ_BC_VER_4_INITIATE_FLR and onwards support flr */
9143 if (sc->devinfo.bc_ver < REQ_BC_VER_4_INITIATE_FLR) {
9144 PMD_DRV_LOG(WARNING,
9145 "FLR not supported by BC_VER: 0x%08x",
9146 sc->devinfo.bc_ver);
9150 /* Wait for Transaction Pending bit clean */
9151 for (i = 0; i < 4; i++) {
9153 DELAY(((1 << (i - 1)) * 100) * 1000);
9156 if (!bnx2x_is_pcie_pending(sc)) {
9161 PMD_DRV_LOG(NOTICE, "PCIE transaction is not cleared, "
9162 "proceeding with reset anyway");
9165 bnx2x_fw_command(sc, DRV_MSG_CODE_INITIATE_FLR, 0);
9170 struct bnx2x_mac_vals {
9178 uint32_t bmac_val[2];
9182 bnx2x_prev_unload_close_mac(struct bnx2x_softc *sc, struct bnx2x_mac_vals *vals)
9184 uint32_t val, base_addr, offset, mask, reset_reg;
9185 uint8_t mac_stopped = FALSE;
9186 uint8_t port = SC_PORT(sc);
9187 uint32_t wb_data[2];
9189 /* reset addresses as they also mark which values were changed */
9190 vals->bmac_addr = 0;
9191 vals->umac_addr = 0;
9192 vals->xmac_addr = 0;
9193 vals->emac_addr = 0;
9195 reset_reg = REG_RD(sc, MISC_REG_RESET_REG_2);
9197 if (!CHIP_IS_E3(sc)) {
9198 val = REG_RD(sc, NIG_REG_BMAC0_REGS_OUT_EN + port * 4);
9199 mask = MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port;
9200 if ((mask & reset_reg) && val) {
9201 base_addr = SC_PORT(sc) ? NIG_REG_INGRESS_BMAC1_MEM
9202 : NIG_REG_INGRESS_BMAC0_MEM;
9203 offset = CHIP_IS_E2(sc) ? BIGMAC2_REGISTER_BMAC_CONTROL
9204 : BIGMAC_REGISTER_BMAC_CONTROL;
9207 * use rd/wr since we cannot use dmae. This is safe
9208 * since MCP won't access the bus due to the request
9209 * to unload, and no function on the path can be
9210 * loaded at this time.
9212 wb_data[0] = REG_RD(sc, base_addr + offset);
9213 wb_data[1] = REG_RD(sc, base_addr + offset + 0x4);
9214 vals->bmac_addr = base_addr + offset;
9215 vals->bmac_val[0] = wb_data[0];
9216 vals->bmac_val[1] = wb_data[1];
9217 wb_data[0] &= ~ELINK_BMAC_CONTROL_RX_ENABLE;
9218 REG_WR(sc, vals->bmac_addr, wb_data[0]);
9219 REG_WR(sc, vals->bmac_addr + 0x4, wb_data[1]);
9222 vals->emac_addr = NIG_REG_NIG_EMAC0_EN + SC_PORT(sc) * 4;
9223 vals->emac_val = REG_RD(sc, vals->emac_addr);
9224 REG_WR(sc, vals->emac_addr, 0);
9227 if (reset_reg & MISC_REGISTERS_RESET_REG_2_XMAC) {
9228 base_addr = SC_PORT(sc) ? GRCBASE_XMAC1 : GRCBASE_XMAC0;
9229 val = REG_RD(sc, base_addr + XMAC_REG_PFC_CTRL_HI);
9230 REG_WR(sc, base_addr + XMAC_REG_PFC_CTRL_HI,
9232 REG_WR(sc, base_addr + XMAC_REG_PFC_CTRL_HI,
9234 vals->xmac_addr = base_addr + XMAC_REG_CTRL;
9235 vals->xmac_val = REG_RD(sc, vals->xmac_addr);
9236 REG_WR(sc, vals->xmac_addr, 0);
9240 mask = MISC_REGISTERS_RESET_REG_2_UMAC0 << port;
9241 if (mask & reset_reg) {
9242 base_addr = SC_PORT(sc) ? GRCBASE_UMAC1 : GRCBASE_UMAC0;
9243 vals->umac_addr = base_addr + UMAC_REG_COMMAND_CONFIG;
9244 vals->umac_val = REG_RD(sc, vals->umac_addr);
9245 REG_WR(sc, vals->umac_addr, 0);
9255 #define BNX2X_PREV_UNDI_PROD_ADDR(p) (BAR_TSTRORM_INTMEM + 0x1508 + ((p) << 4))
9256 #define BNX2X_PREV_UNDI_RCQ(val) ((val) & 0xffff)
9257 #define BNX2X_PREV_UNDI_BD(val) ((val) >> 16 & 0xffff)
9258 #define BNX2X_PREV_UNDI_PROD(rcq, bd) ((bd) << 16 | (rcq))
9261 bnx2x_prev_unload_undi_inc(struct bnx2x_softc *sc, uint8_t port, uint8_t inc)
9264 uint32_t tmp_reg = REG_RD(sc, BNX2X_PREV_UNDI_PROD_ADDR(port));
9266 rcq = BNX2X_PREV_UNDI_RCQ(tmp_reg) + inc;
9267 bd = BNX2X_PREV_UNDI_BD(tmp_reg) + inc;
9269 tmp_reg = BNX2X_PREV_UNDI_PROD(rcq, bd);
9270 REG_WR(sc, BNX2X_PREV_UNDI_PROD_ADDR(port), tmp_reg);
9273 static int bnx2x_prev_unload_common(struct bnx2x_softc *sc)
9275 uint32_t reset_reg, tmp_reg = 0, rc;
9276 uint8_t prev_undi = FALSE;
9277 struct bnx2x_mac_vals mac_vals;
9278 uint32_t timer_count = 1000;
9282 * It is possible a previous function received 'common' answer,
9283 * but hasn't loaded yet, therefore creating a scenario of
9284 * multiple functions receiving 'common' on the same path.
9286 memset(&mac_vals, 0, sizeof(mac_vals));
9288 if (bnx2x_prev_is_path_marked(sc)) {
9289 return bnx2x_prev_mcp_done(sc);
9292 reset_reg = REG_RD(sc, MISC_REG_RESET_REG_1);
9294 /* Reset should be performed after BRB is emptied */
9295 if (reset_reg & MISC_REGISTERS_RESET_REG_1_RST_BRB1) {
9296 /* Close the MAC Rx to prevent BRB from filling up */
9297 bnx2x_prev_unload_close_mac(sc, &mac_vals);
9299 /* close LLH filters towards the BRB */
9300 elink_set_rx_filter(&sc->link_params, 0);
9303 * Check if the UNDI driver was previously loaded.
9304 * UNDI driver initializes CID offset for normal bell to 0x7
9306 if (reset_reg & MISC_REGISTERS_RESET_REG_1_RST_DORQ) {
9307 tmp_reg = REG_RD(sc, DORQ_REG_NORM_CID_OFST);
9308 if (tmp_reg == 0x7) {
9309 PMD_DRV_LOG(DEBUG, "UNDI previously loaded");
9311 /* clear the UNDI indication */
9312 REG_WR(sc, DORQ_REG_NORM_CID_OFST, 0);
9313 /* clear possible idle check errors */
9314 REG_RD(sc, NIG_REG_NIG_INT_STS_CLR_0);
9318 /* wait until BRB is empty */
9319 tmp_reg = REG_RD(sc, BRB1_REG_NUM_OF_FULL_BLOCKS);
9320 while (timer_count) {
9323 tmp_reg = REG_RD(sc, BRB1_REG_NUM_OF_FULL_BLOCKS);
9328 PMD_DRV_LOG(DEBUG, "BRB still has 0x%08x", tmp_reg);
9330 /* reset timer as long as BRB actually gets emptied */
9331 if (prev_brb > tmp_reg) {
9337 /* If UNDI resides in memory, manually increment it */
9339 bnx2x_prev_unload_undi_inc(sc, SC_PORT(sc), 1);
9346 PMD_DRV_LOG(NOTICE, "Failed to empty BRB");
9350 /* No packets are in the pipeline, path is ready for reset */
9351 bnx2x_reset_common(sc);
9353 if (mac_vals.xmac_addr) {
9354 REG_WR(sc, mac_vals.xmac_addr, mac_vals.xmac_val);
9356 if (mac_vals.umac_addr) {
9357 REG_WR(sc, mac_vals.umac_addr, mac_vals.umac_val);
9359 if (mac_vals.emac_addr) {
9360 REG_WR(sc, mac_vals.emac_addr, mac_vals.emac_val);
9362 if (mac_vals.bmac_addr) {
9363 REG_WR(sc, mac_vals.bmac_addr, mac_vals.bmac_val[0]);
9364 REG_WR(sc, mac_vals.bmac_addr + 4, mac_vals.bmac_val[1]);
9367 rc = bnx2x_prev_mark_path(sc, prev_undi);
9369 bnx2x_prev_mcp_done(sc);
9373 return bnx2x_prev_mcp_done(sc);
9376 static int bnx2x_prev_unload_uncommon(struct bnx2x_softc *sc)
9380 /* Test if previous unload process was already finished for this path */
9381 if (bnx2x_prev_is_path_marked(sc)) {
9382 return bnx2x_prev_mcp_done(sc);
9386 * If function has FLR capabilities, and existing FW version matches
9387 * the one required, then FLR will be sufficient to clean any residue
9388 * left by previous driver
9390 rc = bnx2x_nic_load_analyze_req(sc, FW_MSG_CODE_DRV_LOAD_FUNCTION);
9392 /* fw version is good */
9393 rc = bnx2x_do_flr(sc);
9397 /* FLR was performed */
9401 PMD_DRV_LOG(INFO, "Could not FLR");
9403 /* Close the MCP request, return failure */
9404 rc = bnx2x_prev_mcp_done(sc);
9406 rc = BNX2X_PREV_WAIT_NEEDED;
9412 static int bnx2x_prev_unload(struct bnx2x_softc *sc)
9414 int time_counter = 10;
9415 uint32_t fw, hw_lock_reg, hw_lock_val;
9419 * Clear HW from errors which may have resulted from an interrupted
9422 bnx2x_prev_interrupted_dmae(sc);
9424 /* Release previously held locks */
9425 if (SC_FUNC(sc) <= 5)
9426 hw_lock_reg = (MISC_REG_DRIVER_CONTROL_1 + SC_FUNC(sc) * 8);
9429 (MISC_REG_DRIVER_CONTROL_7 + (SC_FUNC(sc) - 6) * 8);
9431 hw_lock_val = (REG_RD(sc, hw_lock_reg));
9433 if (hw_lock_val & HW_LOCK_RESOURCE_NVRAM) {
9434 REG_WR(sc, MCP_REG_MCPR_NVM_SW_ARB,
9435 (MCPR_NVM_SW_ARB_ARB_REQ_CLR1 << SC_PORT(sc)));
9437 REG_WR(sc, hw_lock_reg, 0xffffffff);
9440 if (MCPR_ACCESS_LOCK_LOCK & REG_RD(sc, MCP_REG_MCPR_ACCESS_LOCK)) {
9441 REG_WR(sc, MCP_REG_MCPR_ACCESS_LOCK, 0);
9445 /* Lock MCP using an unload request */
9446 fw = bnx2x_fw_command(sc, DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS, 0);
9448 PMD_DRV_LOG(NOTICE, "MCP response failure, aborting");
9453 if (fw == FW_MSG_CODE_DRV_UNLOAD_COMMON) {
9454 rc = bnx2x_prev_unload_common(sc);
9458 /* non-common reply from MCP might require looping */
9459 rc = bnx2x_prev_unload_uncommon(sc);
9460 if (rc != BNX2X_PREV_WAIT_NEEDED) {
9465 } while (--time_counter);
9467 if (!time_counter || rc) {
9468 PMD_DRV_LOG(NOTICE, "Failed to unload previous driver!");
9476 bnx2x_dcbx_set_state(struct bnx2x_softc *sc, uint8_t dcb_on, uint32_t dcbx_enabled)
9478 if (!CHIP_IS_E1x(sc)) {
9479 sc->dcb_state = dcb_on;
9480 sc->dcbx_enabled = dcbx_enabled;
9482 sc->dcb_state = FALSE;
9483 sc->dcbx_enabled = BNX2X_DCBX_ENABLED_INVALID;
9486 "DCB state [%s:%s]",
9487 dcb_on ? "ON" : "OFF",
9488 (dcbx_enabled == BNX2X_DCBX_ENABLED_OFF) ? "user-mode" :
9490 BNX2X_DCBX_ENABLED_ON_NEG_OFF) ? "on-chip static"
9492 BNX2X_DCBX_ENABLED_ON_NEG_ON) ?
9493 "on-chip with negotiation" : "invalid");
9496 static int bnx2x_set_qm_cid_count(struct bnx2x_softc *sc)
9498 int cid_count = BNX2X_L2_MAX_CID(sc);
9500 if (CNIC_SUPPORT(sc)) {
9501 cid_count += CNIC_CID_MAX;
9504 return roundup(cid_count, QM_CID_ROUND);
9507 static void bnx2x_init_multi_cos(struct bnx2x_softc *sc)
9511 uint32_t pri_map = 0;
9513 for (pri = 0; pri < BNX2X_MAX_PRIORITY; pri++) {
9514 cos = ((pri_map & (0xf << (pri * 4))) >> (pri * 4));
9515 if (cos < sc->max_cos) {
9516 sc->prio_to_cos[pri] = cos;
9518 PMD_DRV_LOG(WARNING,
9519 "Invalid COS %d for priority %d "
9520 "(max COS is %d), setting to 0", cos, pri,
9522 sc->prio_to_cos[pri] = 0;
9527 static int bnx2x_pci_get_caps(struct bnx2x_softc *sc)
9534 struct bnx2x_pci_cap *cap;
9536 cap = sc->pci_caps = rte_zmalloc("caps", sizeof(struct bnx2x_pci_cap),
9537 RTE_CACHE_LINE_SIZE);
9539 PMD_DRV_LOG(NOTICE, "Failed to allocate memory");
9544 pci_read(sc, PCI_STATUS, &status, 2);
9545 if (!(status & PCI_STATUS_CAP_LIST)) {
9547 pci_read(sc, PCIR_STATUS, &status, 2);
9548 if (!(status & PCIM_STATUS_CAPPRESENT)) {
9550 PMD_DRV_LOG(NOTICE, "PCIe capability reading failed");
9555 pci_read(sc, PCI_CAPABILITY_LIST, &pci_cap.next, 1);
9557 pci_read(sc, PCIR_CAP_PTR, &pci_cap.next, 1);
9559 while (pci_cap.next) {
9560 cap->addr = pci_cap.next & ~3;
9561 pci_read(sc, pci_cap.next & ~3, &pci_cap, 2);
9562 if (pci_cap.id == 0xff)
9564 cap->id = pci_cap.id;
9565 cap->type = BNX2X_PCI_CAP;
9566 cap->next = rte_zmalloc("pci_cap",
9567 sizeof(struct bnx2x_pci_cap),
9568 RTE_CACHE_LINE_SIZE);
9570 PMD_DRV_LOG(NOTICE, "Failed to allocate memory");
9579 static void bnx2x_init_rte(struct bnx2x_softc *sc)
9581 sc->max_tx_queues = 128;
9582 sc->max_rx_queues = 128;
9585 #define FW_HEADER_LEN 104
9586 #define FW_NAME_57711 "/lib/firmware/bnx2x/bnx2x-e1h-7.2.51.0.fw"
9587 #define FW_NAME_57810 "/lib/firmware/bnx2x/bnx2x-e2-7.2.51.0.fw"
9589 void bnx2x_load_firmware(struct bnx2x_softc *sc)
9595 fwname = sc->devinfo.device_id == BNX2X_DEV_ID_57711
9596 ? FW_NAME_57711 : FW_NAME_57810;
9597 f = open(fwname, O_RDONLY);
9599 PMD_DRV_LOG(NOTICE, "Can't open firmware file");
9603 if (fstat(f, &st) < 0) {
9604 PMD_DRV_LOG(NOTICE, "Can't stat firmware file");
9609 sc->firmware = rte_zmalloc("bnx2x_fw", st.st_size, RTE_CACHE_LINE_SIZE);
9610 if (!sc->firmware) {
9611 PMD_DRV_LOG(NOTICE, "Can't allocate memory for firmware");
9616 if (read(f, sc->firmware, st.st_size) != st.st_size) {
9617 PMD_DRV_LOG(NOTICE, "Can't read firmware data");
9623 sc->fw_len = st.st_size;
9624 if (sc->fw_len < FW_HEADER_LEN) {
9625 PMD_DRV_LOG(NOTICE, "Invalid fw size: %" PRIu64, sc->fw_len);
9628 PMD_DRV_LOG(DEBUG, "fw_len = %" PRIu64, sc->fw_len);
9632 bnx2x_data_to_init_ops(uint8_t * data, struct raw_op *dst, uint32_t len)
9634 uint32_t *src = (uint32_t *) data;
9637 for (i = 0, j = 0; i < len / 8; ++i, j += 2) {
9638 tmp = rte_be_to_cpu_32(src[j]);
9639 dst[i].op = (tmp >> 24) & 0xFF;
9640 dst[i].offset = tmp & 0xFFFFFF;
9641 dst[i].raw_data = rte_be_to_cpu_32(src[j + 1]);
9646 bnx2x_data_to_init_offsets(uint8_t * data, uint16_t * dst, uint32_t len)
9648 uint16_t *src = (uint16_t *) data;
9651 for (i = 0; i < len / 2; ++i)
9652 dst[i] = rte_be_to_cpu_16(src[i]);
9655 static void bnx2x_data_to_init_data(uint8_t * data, uint32_t * dst, uint32_t len)
9657 uint32_t *src = (uint32_t *) data;
9660 for (i = 0; i < len / 4; ++i)
9661 dst[i] = rte_be_to_cpu_32(src[i]);
9664 static void bnx2x_data_to_iro_array(uint8_t * data, struct iro *dst, uint32_t len)
9666 uint32_t *src = (uint32_t *) data;
9669 for (i = 0, j = 0; i < len / sizeof(struct iro); ++i, ++j) {
9670 dst[i].base = rte_be_to_cpu_32(src[j++]);
9671 tmp = rte_be_to_cpu_32(src[j]);
9672 dst[i].m1 = (tmp >> 16) & 0xFFFF;
9673 dst[i].m2 = tmp & 0xFFFF;
9675 tmp = rte_be_to_cpu_32(src[j]);
9676 dst[i].m3 = (tmp >> 16) & 0xFFFF;
9677 dst[i].size = tmp & 0xFFFF;
9682 * Device attach function.
9684 * Allocates device resources, performs secondary chip identification, and
9685 * initializes driver instance variables. This function is called from driver
9686 * load after a successful probe.
9689 * 0 = Success, >0 = Failure
9691 int bnx2x_attach(struct bnx2x_softc *sc)
9695 PMD_DRV_LOG(DEBUG, "Starting attach...");
9697 rc = bnx2x_pci_get_caps(sc);
9699 PMD_DRV_LOG(NOTICE, "PCIe caps reading was failed");
9703 sc->state = BNX2X_STATE_CLOSED;
9705 /* Init RTE stuff */
9708 pci_write_long(sc, PCICFG_GRC_ADDRESS, PCICFG_VENDOR_ID_OFFSET);
9710 sc->igu_base_addr = IS_VF(sc) ? PXP_VF_ADDR_IGU_START : BAR_IGU_INTMEM;
9712 /* get PCI capabilites */
9713 bnx2x_probe_pci_caps(sc);
9715 if (sc->devinfo.pcie_msix_cap_reg != 0) {
9718 (sc->devinfo.pcie_msix_cap_reg + PCIR_MSIX_CTRL), &val,
9720 sc->igu_sb_cnt = (val & PCIM_MSIXCTRL_TABLE_SIZE);
9726 /* get device info and set params */
9727 if (bnx2x_get_device_info(sc) != 0) {
9728 PMD_DRV_LOG(NOTICE, "getting device info");
9732 /* get phy settings from shmem and 'and' against admin settings */
9733 bnx2x_get_phy_info(sc);
9735 /* Left mac of VF unfilled, PF should set it for VF */
9736 memset(sc->link_params.mac_addr, 0, ETHER_ADDR_LEN);
9741 /* set the default MTU (changed via ifconfig) */
9742 sc->mtu = ETHER_MTU;
9744 bnx2x_set_modes_bitmap(sc);
9746 /* need to reset chip if UNDI was active */
9747 if (IS_PF(sc) && !BNX2X_NOMCP(sc)) {
9750 (SHMEM_RD(sc, func_mb[SC_FW_MB_IDX(sc)].drv_mb_header) &
9751 DRV_MSG_SEQ_NUMBER_MASK);
9752 bnx2x_prev_unload(sc);
9755 bnx2x_dcbx_set_state(sc, FALSE, BNX2X_DCBX_ENABLED_OFF);
9757 /* calculate qm_cid_count */
9758 sc->qm_cid_count = bnx2x_set_qm_cid_count(sc);
9761 bnx2x_init_multi_cos(sc);
9767 bnx2x_igu_ack_sb(struct bnx2x_softc *sc, uint8_t igu_sb_id, uint8_t segment,
9768 uint16_t index, uint8_t op, uint8_t update)
9770 uint32_t igu_addr = sc->igu_base_addr;
9771 igu_addr += (IGU_CMD_INT_ACK_BASE + igu_sb_id) * 8;
9772 bnx2x_igu_ack_sb_gen(sc, segment, index, op, update, igu_addr);
9776 bnx2x_ack_sb(struct bnx2x_softc *sc, uint8_t igu_sb_id, uint8_t storm,
9777 uint16_t index, uint8_t op, uint8_t update)
9779 if (unlikely(sc->devinfo.int_block == INT_BLOCK_HC))
9780 bnx2x_hc_ack_sb(sc, igu_sb_id, storm, index, op, update);
9783 if (CHIP_INT_MODE_IS_BC(sc)) {
9785 } else if (igu_sb_id != sc->igu_dsb_id) {
9786 segment = IGU_SEG_ACCESS_DEF;
9787 } else if (storm == ATTENTION_ID) {
9788 segment = IGU_SEG_ACCESS_ATTN;
9790 segment = IGU_SEG_ACCESS_DEF;
9792 bnx2x_igu_ack_sb(sc, igu_sb_id, segment, index, op, update);
9797 bnx2x_igu_clear_sb_gen(struct bnx2x_softc *sc, uint8_t func, uint8_t idu_sb_id,
9800 uint32_t data, ctl, cnt = 100;
9801 uint32_t igu_addr_data = IGU_REG_COMMAND_REG_32LSB_DATA;
9802 uint32_t igu_addr_ctl = IGU_REG_COMMAND_REG_CTRL;
9803 uint32_t igu_addr_ack = IGU_REG_CSTORM_TYPE_0_SB_CLEANUP +
9804 (idu_sb_id / 32) * 4;
9805 uint32_t sb_bit = 1 << (idu_sb_id % 32);
9806 uint32_t func_encode = func |
9807 (is_pf ? 1 : 0) << IGU_FID_ENCODE_IS_PF_SHIFT;
9808 uint32_t addr_encode = IGU_CMD_E2_PROD_UPD_BASE + idu_sb_id;
9810 /* Not supported in BC mode */
9811 if (CHIP_INT_MODE_IS_BC(sc)) {
9815 data = ((IGU_USE_REGISTER_cstorm_type_0_sb_cleanup <<
9816 IGU_REGULAR_CLEANUP_TYPE_SHIFT) |
9817 IGU_REGULAR_CLEANUP_SET | IGU_REGULAR_BCLEANUP);
9819 ctl = ((addr_encode << IGU_CTRL_REG_ADDRESS_SHIFT) |
9820 (func_encode << IGU_CTRL_REG_FID_SHIFT) |
9821 (IGU_CTRL_CMD_TYPE_WR << IGU_CTRL_REG_TYPE_SHIFT));
9823 REG_WR(sc, igu_addr_data, data);
9827 PMD_DRV_LOG(DEBUG, "write 0x%08x to IGU(via GRC) addr 0x%x",
9829 REG_WR(sc, igu_addr_ctl, ctl);
9833 /* wait for clean up to finish */
9834 while (!(REG_RD(sc, igu_addr_ack) & sb_bit) && --cnt) {
9838 if (!(REG_RD(sc, igu_addr_ack) & sb_bit)) {
9840 "Unable to finish IGU cleanup: "
9841 "idu_sb_id %d offset %d bit %d (cnt %d)",
9842 idu_sb_id, idu_sb_id / 32, idu_sb_id % 32, cnt);
9846 static void bnx2x_igu_clear_sb(struct bnx2x_softc *sc, uint8_t idu_sb_id)
9848 bnx2x_igu_clear_sb_gen(sc, SC_FUNC(sc), idu_sb_id, TRUE /*PF*/);
9851 /*******************/
9852 /* ECORE CALLBACKS */
9853 /*******************/
9855 static void bnx2x_reset_common(struct bnx2x_softc *sc)
9857 uint32_t val = 0x1400;
9859 PMD_INIT_FUNC_TRACE();
9862 REG_WR(sc, (GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR),
9865 if (CHIP_IS_E3(sc)) {
9866 val |= MISC_REGISTERS_RESET_REG_2_MSTAT0;
9867 val |= MISC_REGISTERS_RESET_REG_2_MSTAT1;
9870 REG_WR(sc, (GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR), val);
9873 static void bnx2x_common_init_phy(struct bnx2x_softc *sc)
9875 uint32_t shmem_base[2];
9876 uint32_t shmem2_base[2];
9878 /* Avoid common init in case MFW supports LFA */
9879 if (SHMEM2_RD(sc, size) >
9880 (uint32_t) offsetof(struct shmem2_region,
9881 lfa_host_addr[SC_PORT(sc)])) {
9885 shmem_base[0] = sc->devinfo.shmem_base;
9886 shmem2_base[0] = sc->devinfo.shmem2_base;
9888 if (!CHIP_IS_E1x(sc)) {
9889 shmem_base[1] = SHMEM2_RD(sc, other_shmem_base_addr);
9890 shmem2_base[1] = SHMEM2_RD(sc, other_shmem2_base_addr);
9893 elink_common_init_phy(sc, shmem_base, shmem2_base,
9894 sc->devinfo.chip_id, 0);
9897 static void bnx2x_pf_disable(struct bnx2x_softc *sc)
9899 uint32_t val = REG_RD(sc, IGU_REG_PF_CONFIGURATION);
9901 val &= ~IGU_PF_CONF_FUNC_EN;
9903 REG_WR(sc, IGU_REG_PF_CONFIGURATION, val);
9904 REG_WR(sc, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 0);
9905 REG_WR(sc, CFC_REG_WEAK_ENABLE_PF, 0);
9908 static void bnx2x_init_pxp(struct bnx2x_softc *sc)
9911 int r_order, w_order;
9913 devctl = bnx2x_pcie_capability_read(sc, PCIR_EXPRESS_DEVICE_CTL);
9915 w_order = ((devctl & PCIM_EXP_CTL_MAX_PAYLOAD) >> 5);
9916 r_order = ((devctl & PCIM_EXP_CTL_MAX_READ_REQUEST) >> 12);
9918 ecore_init_pxp_arb(sc, r_order, w_order);
9921 static uint32_t bnx2x_get_pretend_reg(struct bnx2x_softc *sc)
9923 uint32_t base = PXP2_REG_PGL_PRETEND_FUNC_F0;
9924 uint32_t stride = (PXP2_REG_PGL_PRETEND_FUNC_F1 - base);
9925 return (base + (SC_ABS_FUNC(sc)) * stride);
9929 * Called only on E1H or E2.
9930 * When pretending to be PF, the pretend value is the function number 0..7.
9931 * When pretending to be VF, the pretend val is the PF-num:VF-valid:ABS-VFID
9934 static int bnx2x_pretend_func(struct bnx2x_softc *sc, uint16_t pretend_func_val)
9936 uint32_t pretend_reg;
9938 if (CHIP_IS_E1H(sc) && (pretend_func_val > E1H_FUNC_MAX))
9941 /* get my own pretend register */
9942 pretend_reg = bnx2x_get_pretend_reg(sc);
9943 REG_WR(sc, pretend_reg, pretend_func_val);
9944 REG_RD(sc, pretend_reg);
9948 static void bnx2x_setup_fan_failure_detection(struct bnx2x_softc *sc)
9955 val = (SHMEM_RD(sc, dev_info.shared_hw_config.config2) &
9956 SHARED_HW_CFG_FAN_FAILURE_MASK);
9958 if (val == SHARED_HW_CFG_FAN_FAILURE_ENABLED) {
9962 * The fan failure mechanism is usually related to the PHY type since
9963 * the power consumption of the board is affected by the PHY. Currently,
9964 * fan is required for most designs with SFX7101, BNX2X8727 and BNX2X8481.
9966 else if (val == SHARED_HW_CFG_FAN_FAILURE_PHY_TYPE) {
9967 for (port = PORT_0; port < PORT_MAX; port++) {
9968 is_required |= elink_fan_failure_det_req(sc,
9972 devinfo.shmem2_base,
9977 if (is_required == 0) {
9981 /* Fan failure is indicated by SPIO 5 */
9982 bnx2x_set_spio(sc, MISC_SPIO_SPIO5, MISC_SPIO_INPUT_HI_Z);
9984 /* set to active low mode */
9985 val = REG_RD(sc, MISC_REG_SPIO_INT);
9986 val |= (MISC_SPIO_SPIO5 << MISC_SPIO_INT_OLD_SET_POS);
9987 REG_WR(sc, MISC_REG_SPIO_INT, val);
9989 /* enable interrupt to signal the IGU */
9990 val = REG_RD(sc, MISC_REG_SPIO_EVENT_EN);
9991 val |= MISC_SPIO_SPIO5;
9992 REG_WR(sc, MISC_REG_SPIO_EVENT_EN, val);
9995 static void bnx2x_enable_blocks_attention(struct bnx2x_softc *sc)
9999 REG_WR(sc, PXP_REG_PXP_INT_MASK_0, 0);
10000 if (!CHIP_IS_E1x(sc)) {
10001 REG_WR(sc, PXP_REG_PXP_INT_MASK_1, 0x40);
10003 REG_WR(sc, PXP_REG_PXP_INT_MASK_1, 0);
10005 REG_WR(sc, DORQ_REG_DORQ_INT_MASK, 0);
10006 REG_WR(sc, CFC_REG_CFC_INT_MASK, 0);
10008 * mask read length error interrupts in brb for parser
10009 * (parsing unit and 'checksum and crc' unit)
10010 * these errors are legal (PU reads fixed length and CAC can cause
10011 * read length error on truncated packets)
10013 REG_WR(sc, BRB1_REG_BRB1_INT_MASK, 0xFC00);
10014 REG_WR(sc, QM_REG_QM_INT_MASK, 0);
10015 REG_WR(sc, TM_REG_TM_INT_MASK, 0);
10016 REG_WR(sc, XSDM_REG_XSDM_INT_MASK_0, 0);
10017 REG_WR(sc, XSDM_REG_XSDM_INT_MASK_1, 0);
10018 REG_WR(sc, XCM_REG_XCM_INT_MASK, 0);
10019 /* REG_WR(sc, XSEM_REG_XSEM_INT_MASK_0, 0); */
10020 /* REG_WR(sc, XSEM_REG_XSEM_INT_MASK_1, 0); */
10021 REG_WR(sc, USDM_REG_USDM_INT_MASK_0, 0);
10022 REG_WR(sc, USDM_REG_USDM_INT_MASK_1, 0);
10023 REG_WR(sc, UCM_REG_UCM_INT_MASK, 0);
10024 /* REG_WR(sc, USEM_REG_USEM_INT_MASK_0, 0); */
10025 /* REG_WR(sc, USEM_REG_USEM_INT_MASK_1, 0); */
10026 REG_WR(sc, GRCBASE_UPB + PB_REG_PB_INT_MASK, 0);
10027 REG_WR(sc, CSDM_REG_CSDM_INT_MASK_0, 0);
10028 REG_WR(sc, CSDM_REG_CSDM_INT_MASK_1, 0);
10029 REG_WR(sc, CCM_REG_CCM_INT_MASK, 0);
10030 /* REG_WR(sc, CSEM_REG_CSEM_INT_MASK_0, 0); */
10031 /* REG_WR(sc, CSEM_REG_CSEM_INT_MASK_1, 0); */
10033 val = (PXP2_PXP2_INT_MASK_0_REG_PGL_CPL_AFT |
10034 PXP2_PXP2_INT_MASK_0_REG_PGL_CPL_OF |
10035 PXP2_PXP2_INT_MASK_0_REG_PGL_PCIE_ATTN);
10036 if (!CHIP_IS_E1x(sc)) {
10037 val |= (PXP2_PXP2_INT_MASK_0_REG_PGL_READ_BLOCKED |
10038 PXP2_PXP2_INT_MASK_0_REG_PGL_WRITE_BLOCKED);
10040 REG_WR(sc, PXP2_REG_PXP2_INT_MASK_0, val);
10042 REG_WR(sc, TSDM_REG_TSDM_INT_MASK_0, 0);
10043 REG_WR(sc, TSDM_REG_TSDM_INT_MASK_1, 0);
10044 REG_WR(sc, TCM_REG_TCM_INT_MASK, 0);
10045 /* REG_WR(sc, TSEM_REG_TSEM_INT_MASK_0, 0); */
10047 if (!CHIP_IS_E1x(sc)) {
10048 /* enable VFC attentions: bits 11 and 12, bits 31:13 reserved */
10049 REG_WR(sc, TSEM_REG_TSEM_INT_MASK_1, 0x07ff);
10052 REG_WR(sc, CDU_REG_CDU_INT_MASK, 0);
10053 REG_WR(sc, DMAE_REG_DMAE_INT_MASK, 0);
10054 /* REG_WR(sc, MISC_REG_MISC_INT_MASK, 0); */
10055 REG_WR(sc, PBF_REG_PBF_INT_MASK, 0x18); /* bit 3,4 masked */
10059 * bnx2x_init_hw_common - initialize the HW at the COMMON phase.
10061 * @sc: driver handle
10063 static int bnx2x_init_hw_common(struct bnx2x_softc *sc)
10065 uint8_t abs_func_id;
10068 PMD_DRV_LOG(DEBUG, "starting common init for func %d", SC_ABS_FUNC(sc));
10071 * take the RESET lock to protect undi_unload flow from accessing
10072 * registers while we are resetting the chip
10074 bnx2x_acquire_hw_lock(sc, HW_LOCK_RESOURCE_RESET);
10076 bnx2x_reset_common(sc);
10078 REG_WR(sc, (GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET), 0xffffffff);
10081 if (CHIP_IS_E3(sc)) {
10082 val |= MISC_REGISTERS_RESET_REG_2_MSTAT0;
10083 val |= MISC_REGISTERS_RESET_REG_2_MSTAT1;
10086 REG_WR(sc, (GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET), val);
10088 bnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_RESET);
10090 ecore_init_block(sc, BLOCK_MISC, PHASE_COMMON);
10092 if (!CHIP_IS_E1x(sc)) {
10094 * 4-port mode or 2-port mode we need to turn off master-enable for
10095 * everyone. After that we turn it back on for self. So, we disregard
10096 * multi-function, and always disable all functions on the given path,
10097 * this means 0,2,4,6 for path 0 and 1,3,5,7 for path 1
10099 for (abs_func_id = SC_PATH(sc);
10100 abs_func_id < (E2_FUNC_MAX * 2); abs_func_id += 2) {
10101 if (abs_func_id == SC_ABS_FUNC(sc)) {
10103 PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER,
10108 bnx2x_pretend_func(sc, abs_func_id);
10110 /* clear pf enable */
10111 bnx2x_pf_disable(sc);
10113 bnx2x_pretend_func(sc, SC_ABS_FUNC(sc));
10117 ecore_init_block(sc, BLOCK_PXP, PHASE_COMMON);
10119 ecore_init_block(sc, BLOCK_PXP2, PHASE_COMMON);
10120 bnx2x_init_pxp(sc);
10122 #ifdef __BIG_ENDIAN
10123 REG_WR(sc, PXP2_REG_RQ_QM_ENDIAN_M, 1);
10124 REG_WR(sc, PXP2_REG_RQ_TM_ENDIAN_M, 1);
10125 REG_WR(sc, PXP2_REG_RQ_SRC_ENDIAN_M, 1);
10126 REG_WR(sc, PXP2_REG_RQ_CDU_ENDIAN_M, 1);
10127 REG_WR(sc, PXP2_REG_RQ_DBG_ENDIAN_M, 1);
10128 /* make sure this value is 0 */
10129 REG_WR(sc, PXP2_REG_RQ_HC_ENDIAN_M, 0);
10131 //REG_WR(sc, PXP2_REG_RD_PBF_SWAP_MODE, 1);
10132 REG_WR(sc, PXP2_REG_RD_QM_SWAP_MODE, 1);
10133 REG_WR(sc, PXP2_REG_RD_TM_SWAP_MODE, 1);
10134 REG_WR(sc, PXP2_REG_RD_SRC_SWAP_MODE, 1);
10135 REG_WR(sc, PXP2_REG_RD_CDURD_SWAP_MODE, 1);
10138 ecore_ilt_init_page_size(sc, INITOP_SET);
10140 if (CHIP_REV_IS_FPGA(sc) && CHIP_IS_E1H(sc)) {
10141 REG_WR(sc, PXP2_REG_PGL_TAGS_LIMIT, 0x1);
10144 /* let the HW do it's magic... */
10147 /* finish PXP init */
10149 val = REG_RD(sc, PXP2_REG_RQ_CFG_DONE);
10151 PMD_DRV_LOG(NOTICE, "PXP2 CFG failed");
10154 val = REG_RD(sc, PXP2_REG_RD_INIT_DONE);
10156 PMD_DRV_LOG(NOTICE, "PXP2 RD_INIT failed");
10161 * Timer bug workaround for E2 only. We need to set the entire ILT to have
10162 * entries with value "0" and valid bit on. This needs to be done by the
10163 * first PF that is loaded in a path (i.e. common phase)
10165 if (!CHIP_IS_E1x(sc)) {
10167 * In E2 there is a bug in the timers block that can cause function 6 / 7
10168 * (i.e. vnic3) to start even if it is marked as "scan-off".
10169 * This occurs when a different function (func2,3) is being marked
10170 * as "scan-off". Real-life scenario for example: if a driver is being
10171 * load-unloaded while func6,7 are down. This will cause the timer to access
10172 * the ilt, translate to a logical address and send a request to read/write.
10173 * Since the ilt for the function that is down is not valid, this will cause
10174 * a translation error which is unrecoverable.
10175 * The Workaround is intended to make sure that when this happens nothing
10176 * fatal will occur. The workaround:
10177 * 1. First PF driver which loads on a path will:
10178 * a. After taking the chip out of reset, by using pretend,
10179 * it will write "0" to the following registers of
10181 * REG_WR(pdev, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 0);
10182 * REG_WR(pdev, CFC_REG_WEAK_ENABLE_PF,0);
10183 * REG_WR(pdev, CFC_REG_STRONG_ENABLE_PF,0);
10184 * And for itself it will write '1' to
10185 * PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER to enable
10186 * dmae-operations (writing to pram for example.)
10187 * note: can be done for only function 6,7 but cleaner this
10189 * b. Write zero+valid to the entire ILT.
10190 * c. Init the first_timers_ilt_entry, last_timers_ilt_entry of
10191 * VNIC3 (of that port). The range allocated will be the
10192 * entire ILT. This is needed to prevent ILT range error.
10193 * 2. Any PF driver load flow:
10194 * a. ILT update with the physical addresses of the allocated
10196 * b. Wait 20msec. - note that this timeout is needed to make
10197 * sure there are no requests in one of the PXP internal
10198 * queues with "old" ILT addresses.
10199 * c. PF enable in the PGLC.
10200 * d. Clear the was_error of the PF in the PGLC. (could have
10201 * occurred while driver was down)
10202 * e. PF enable in the CFC (WEAK + STRONG)
10203 * f. Timers scan enable
10204 * 3. PF driver unload flow:
10205 * a. Clear the Timers scan_en.
10206 * b. Polling for scan_on=0 for that PF.
10207 * c. Clear the PF enable bit in the PXP.
10208 * d. Clear the PF enable in the CFC (WEAK + STRONG)
10209 * e. Write zero+valid to all ILT entries (The valid bit must
10211 * f. If this is VNIC 3 of a port then also init
10212 * first_timers_ilt_entry to zero and last_timers_ilt_entry
10213 * to the last enrty in the ILT.
10216 * Currently the PF error in the PGLC is non recoverable.
10217 * In the future the there will be a recovery routine for this error.
10218 * Currently attention is masked.
10219 * Having an MCP lock on the load/unload process does not guarantee that
10220 * there is no Timer disable during Func6/7 enable. This is because the
10221 * Timers scan is currently being cleared by the MCP on FLR.
10222 * Step 2.d can be done only for PF6/7 and the driver can also check if
10223 * there is error before clearing it. But the flow above is simpler and
10225 * All ILT entries are written by zero+valid and not just PF6/7
10226 * ILT entries since in the future the ILT entries allocation for
10227 * PF-s might be dynamic.
10229 struct ilt_client_info ilt_cli;
10230 struct ecore_ilt ilt;
10232 memset(&ilt_cli, 0, sizeof(struct ilt_client_info));
10233 memset(&ilt, 0, sizeof(struct ecore_ilt));
10235 /* initialize dummy TM client */
10237 ilt_cli.end = ILT_NUM_PAGE_ENTRIES - 1;
10238 ilt_cli.client_num = ILT_CLIENT_TM;
10241 * Step 1: set zeroes to all ilt page entries with valid bit on
10242 * Step 2: set the timers first/last ilt entry to point
10243 * to the entire range to prevent ILT range error for 3rd/4th
10244 * vnic (this code assumes existence of the vnic)
10246 * both steps performed by call to ecore_ilt_client_init_op()
10247 * with dummy TM client
10249 * we must use pretend since PXP2_REG_RQ_##blk##_FIRST_ILT
10250 * and his brother are split registers
10253 bnx2x_pretend_func(sc, (SC_PATH(sc) + 6));
10254 ecore_ilt_client_init_op_ilt(sc, &ilt, &ilt_cli, INITOP_CLEAR);
10255 bnx2x_pretend_func(sc, SC_ABS_FUNC(sc));
10257 REG_WR(sc, PXP2_REG_RQ_DRAM_ALIGN, BNX2X_PXP_DRAM_ALIGN);
10258 REG_WR(sc, PXP2_REG_RQ_DRAM_ALIGN_RD, BNX2X_PXP_DRAM_ALIGN);
10259 REG_WR(sc, PXP2_REG_RQ_DRAM_ALIGN_SEL, 1);
10262 REG_WR(sc, PXP2_REG_RQ_DISABLE_INPUTS, 0);
10263 REG_WR(sc, PXP2_REG_RD_DISABLE_INPUTS, 0);
10265 if (!CHIP_IS_E1x(sc)) {
10268 ecore_init_block(sc, BLOCK_PGLUE_B, PHASE_COMMON);
10269 ecore_init_block(sc, BLOCK_ATC, PHASE_COMMON);
10271 /* let the HW do it's magic... */
10274 val = REG_RD(sc, ATC_REG_ATC_INIT_DONE);
10275 } while (factor-- && (val != 1));
10278 PMD_DRV_LOG(NOTICE, "ATC_INIT failed");
10283 ecore_init_block(sc, BLOCK_DMAE, PHASE_COMMON);
10285 /* clean the DMAE memory */
10286 sc->dmae_ready = 1;
10287 ecore_init_fill(sc, TSEM_REG_PRAM, 0, 8);
10289 ecore_init_block(sc, BLOCK_TCM, PHASE_COMMON);
10291 ecore_init_block(sc, BLOCK_UCM, PHASE_COMMON);
10293 ecore_init_block(sc, BLOCK_CCM, PHASE_COMMON);
10295 ecore_init_block(sc, BLOCK_XCM, PHASE_COMMON);
10297 bnx2x_read_dmae(sc, XSEM_REG_PASSIVE_BUFFER, 3);
10298 bnx2x_read_dmae(sc, CSEM_REG_PASSIVE_BUFFER, 3);
10299 bnx2x_read_dmae(sc, TSEM_REG_PASSIVE_BUFFER, 3);
10300 bnx2x_read_dmae(sc, USEM_REG_PASSIVE_BUFFER, 3);
10302 ecore_init_block(sc, BLOCK_QM, PHASE_COMMON);
10304 /* QM queues pointers table */
10305 ecore_qm_init_ptr_table(sc, sc->qm_cid_count, INITOP_SET);
10307 /* soft reset pulse */
10308 REG_WR(sc, QM_REG_SOFT_RESET, 1);
10309 REG_WR(sc, QM_REG_SOFT_RESET, 0);
10311 if (CNIC_SUPPORT(sc))
10312 ecore_init_block(sc, BLOCK_TM, PHASE_COMMON);
10314 ecore_init_block(sc, BLOCK_DORQ, PHASE_COMMON);
10315 REG_WR(sc, DORQ_REG_DPM_CID_OFST, BNX2X_DB_SHIFT);
10317 if (!CHIP_REV_IS_SLOW(sc)) {
10318 /* enable hw interrupt from doorbell Q */
10319 REG_WR(sc, DORQ_REG_DORQ_INT_MASK, 0);
10322 ecore_init_block(sc, BLOCK_BRB1, PHASE_COMMON);
10324 ecore_init_block(sc, BLOCK_PRS, PHASE_COMMON);
10325 REG_WR(sc, PRS_REG_A_PRSU_20, 0xf);
10326 REG_WR(sc, PRS_REG_E1HOV_MODE, sc->devinfo.mf_info.path_has_ovlan);
10328 if (!CHIP_IS_E1x(sc) && !CHIP_IS_E3B0(sc)) {
10329 if (IS_MF_AFEX(sc)) {
10331 * configure that AFEX and VLAN headers must be
10332 * received in AFEX mode
10334 REG_WR(sc, PRS_REG_HDRS_AFTER_BASIC, 0xE);
10335 REG_WR(sc, PRS_REG_MUST_HAVE_HDRS, 0xA);
10336 REG_WR(sc, PRS_REG_HDRS_AFTER_TAG_0, 0x6);
10337 REG_WR(sc, PRS_REG_TAG_ETHERTYPE_0, 0x8926);
10338 REG_WR(sc, PRS_REG_TAG_LEN_0, 0x4);
10341 * Bit-map indicating which L2 hdrs may appear
10342 * after the basic Ethernet header
10344 REG_WR(sc, PRS_REG_HDRS_AFTER_BASIC,
10345 sc->devinfo.mf_info.path_has_ovlan ? 7 : 6);
10349 ecore_init_block(sc, BLOCK_TSDM, PHASE_COMMON);
10350 ecore_init_block(sc, BLOCK_CSDM, PHASE_COMMON);
10351 ecore_init_block(sc, BLOCK_USDM, PHASE_COMMON);
10352 ecore_init_block(sc, BLOCK_XSDM, PHASE_COMMON);
10354 if (!CHIP_IS_E1x(sc)) {
10355 /* reset VFC memories */
10356 REG_WR(sc, TSEM_REG_FAST_MEMORY + VFC_REG_MEMORIES_RST,
10357 VFC_MEMORIES_RST_REG_CAM_RST |
10358 VFC_MEMORIES_RST_REG_RAM_RST);
10359 REG_WR(sc, XSEM_REG_FAST_MEMORY + VFC_REG_MEMORIES_RST,
10360 VFC_MEMORIES_RST_REG_CAM_RST |
10361 VFC_MEMORIES_RST_REG_RAM_RST);
10366 ecore_init_block(sc, BLOCK_TSEM, PHASE_COMMON);
10367 ecore_init_block(sc, BLOCK_USEM, PHASE_COMMON);
10368 ecore_init_block(sc, BLOCK_CSEM, PHASE_COMMON);
10369 ecore_init_block(sc, BLOCK_XSEM, PHASE_COMMON);
10371 /* sync semi rtc */
10372 REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR, 0x80000000);
10373 REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, 0x80000000);
10375 ecore_init_block(sc, BLOCK_UPB, PHASE_COMMON);
10376 ecore_init_block(sc, BLOCK_XPB, PHASE_COMMON);
10377 ecore_init_block(sc, BLOCK_PBF, PHASE_COMMON);
10379 if (!CHIP_IS_E1x(sc)) {
10380 if (IS_MF_AFEX(sc)) {
10382 * configure that AFEX and VLAN headers must be
10383 * sent in AFEX mode
10385 REG_WR(sc, PBF_REG_HDRS_AFTER_BASIC, 0xE);
10386 REG_WR(sc, PBF_REG_MUST_HAVE_HDRS, 0xA);
10387 REG_WR(sc, PBF_REG_HDRS_AFTER_TAG_0, 0x6);
10388 REG_WR(sc, PBF_REG_TAG_ETHERTYPE_0, 0x8926);
10389 REG_WR(sc, PBF_REG_TAG_LEN_0, 0x4);
10391 REG_WR(sc, PBF_REG_HDRS_AFTER_BASIC,
10392 sc->devinfo.mf_info.path_has_ovlan ? 7 : 6);
10396 REG_WR(sc, SRC_REG_SOFT_RST, 1);
10398 ecore_init_block(sc, BLOCK_SRC, PHASE_COMMON);
10400 if (CNIC_SUPPORT(sc)) {
10401 REG_WR(sc, SRC_REG_KEYSEARCH_0, 0x63285672);
10402 REG_WR(sc, SRC_REG_KEYSEARCH_1, 0x24b8f2cc);
10403 REG_WR(sc, SRC_REG_KEYSEARCH_2, 0x223aef9b);
10404 REG_WR(sc, SRC_REG_KEYSEARCH_3, 0x26001e3a);
10405 REG_WR(sc, SRC_REG_KEYSEARCH_4, 0x7ae91116);
10406 REG_WR(sc, SRC_REG_KEYSEARCH_5, 0x5ce5230b);
10407 REG_WR(sc, SRC_REG_KEYSEARCH_6, 0x298d8adf);
10408 REG_WR(sc, SRC_REG_KEYSEARCH_7, 0x6eb0ff09);
10409 REG_WR(sc, SRC_REG_KEYSEARCH_8, 0x1830f82f);
10410 REG_WR(sc, SRC_REG_KEYSEARCH_9, 0x01e46be7);
10412 REG_WR(sc, SRC_REG_SOFT_RST, 0);
10414 if (sizeof(union cdu_context) != 1024) {
10415 /* we currently assume that a context is 1024 bytes */
10416 PMD_DRV_LOG(NOTICE,
10417 "please adjust the size of cdu_context(%ld)",
10418 (long)sizeof(union cdu_context));
10421 ecore_init_block(sc, BLOCK_CDU, PHASE_COMMON);
10422 val = (4 << 24) + (0 << 12) + 1024;
10423 REG_WR(sc, CDU_REG_CDU_GLOBAL_PARAMS, val);
10425 ecore_init_block(sc, BLOCK_CFC, PHASE_COMMON);
10427 REG_WR(sc, CFC_REG_INIT_REG, 0x7FF);
10428 /* enable context validation interrupt from CFC */
10429 REG_WR(sc, CFC_REG_CFC_INT_MASK, 0);
10431 /* set the thresholds to prevent CFC/CDU race */
10432 REG_WR(sc, CFC_REG_DEBUG0, 0x20020000);
10433 ecore_init_block(sc, BLOCK_HC, PHASE_COMMON);
10435 if (!CHIP_IS_E1x(sc) && BNX2X_NOMCP(sc)) {
10436 REG_WR(sc, IGU_REG_RESET_MEMORIES, 0x36);
10439 ecore_init_block(sc, BLOCK_IGU, PHASE_COMMON);
10440 ecore_init_block(sc, BLOCK_MISC_AEU, PHASE_COMMON);
10442 /* Reset PCIE errors for debug */
10443 REG_WR(sc, 0x2814, 0xffffffff);
10444 REG_WR(sc, 0x3820, 0xffffffff);
10446 if (!CHIP_IS_E1x(sc)) {
10447 REG_WR(sc, PCICFG_OFFSET + PXPCS_TL_CONTROL_5,
10448 (PXPCS_TL_CONTROL_5_ERR_UNSPPORT1 |
10449 PXPCS_TL_CONTROL_5_ERR_UNSPPORT));
10450 REG_WR(sc, PCICFG_OFFSET + PXPCS_TL_FUNC345_STAT,
10451 (PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT4 |
10452 PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT3 |
10453 PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT2));
10454 REG_WR(sc, PCICFG_OFFSET + PXPCS_TL_FUNC678_STAT,
10455 (PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT7 |
10456 PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT6 |
10457 PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT5));
10460 ecore_init_block(sc, BLOCK_NIG, PHASE_COMMON);
10462 /* in E3 this done in per-port section */
10463 if (!CHIP_IS_E3(sc))
10464 REG_WR(sc, NIG_REG_LLH_MF_MODE, IS_MF(sc));
10466 if (CHIP_IS_E1H(sc)) {
10467 /* not applicable for E2 (and above ...) */
10468 REG_WR(sc, NIG_REG_LLH_E1HOV_MODE, IS_MF_SD(sc));
10471 if (CHIP_REV_IS_SLOW(sc)) {
10475 /* finish CFC init */
10476 val = reg_poll(sc, CFC_REG_LL_INIT_DONE, 1, 100, 10);
10478 PMD_DRV_LOG(NOTICE, "CFC LL_INIT failed");
10481 val = reg_poll(sc, CFC_REG_AC_INIT_DONE, 1, 100, 10);
10483 PMD_DRV_LOG(NOTICE, "CFC AC_INIT failed");
10486 val = reg_poll(sc, CFC_REG_CAM_INIT_DONE, 1, 100, 10);
10488 PMD_DRV_LOG(NOTICE, "CFC CAM_INIT failed");
10491 REG_WR(sc, CFC_REG_DEBUG0, 0);
10493 bnx2x_setup_fan_failure_detection(sc);
10495 /* clear PXP2 attentions */
10496 REG_RD(sc, PXP2_REG_PXP2_INT_STS_CLR_0);
10498 bnx2x_enable_blocks_attention(sc);
10500 if (!CHIP_REV_IS_SLOW(sc)) {
10501 ecore_enable_blocks_parity(sc);
10504 if (!BNX2X_NOMCP(sc)) {
10505 if (CHIP_IS_E1x(sc)) {
10506 bnx2x_common_init_phy(sc);
10514 * bnx2x_init_hw_common_chip - init HW at the COMMON_CHIP phase.
10516 * @sc: driver handle
10518 static int bnx2x_init_hw_common_chip(struct bnx2x_softc *sc)
10520 int rc = bnx2x_init_hw_common(sc);
10526 /* In E2 2-PORT mode, same ext phy is used for the two paths */
10527 if (!BNX2X_NOMCP(sc)) {
10528 bnx2x_common_init_phy(sc);
10534 static int bnx2x_init_hw_port(struct bnx2x_softc *sc)
10536 int port = SC_PORT(sc);
10537 int init_phase = port ? PHASE_PORT1 : PHASE_PORT0;
10538 uint32_t low, high;
10541 PMD_DRV_LOG(DEBUG, "starting port init for port %d", port);
10543 REG_WR(sc, NIG_REG_MASK_INTERRUPT_PORT0 + port * 4, 0);
10545 ecore_init_block(sc, BLOCK_MISC, init_phase);
10546 ecore_init_block(sc, BLOCK_PXP, init_phase);
10547 ecore_init_block(sc, BLOCK_PXP2, init_phase);
10550 * Timers bug workaround: disables the pf_master bit in pglue at
10551 * common phase, we need to enable it here before any dmae access are
10552 * attempted. Therefore we manually added the enable-master to the
10553 * port phase (it also happens in the function phase)
10555 if (!CHIP_IS_E1x(sc)) {
10556 REG_WR(sc, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 1);
10559 ecore_init_block(sc, BLOCK_ATC, init_phase);
10560 ecore_init_block(sc, BLOCK_DMAE, init_phase);
10561 ecore_init_block(sc, BLOCK_PGLUE_B, init_phase);
10562 ecore_init_block(sc, BLOCK_QM, init_phase);
10564 ecore_init_block(sc, BLOCK_TCM, init_phase);
10565 ecore_init_block(sc, BLOCK_UCM, init_phase);
10566 ecore_init_block(sc, BLOCK_CCM, init_phase);
10567 ecore_init_block(sc, BLOCK_XCM, init_phase);
10569 /* QM cid (connection) count */
10570 ecore_qm_init_cid_count(sc, sc->qm_cid_count, INITOP_SET);
10572 if (CNIC_SUPPORT(sc)) {
10573 ecore_init_block(sc, BLOCK_TM, init_phase);
10574 REG_WR(sc, TM_REG_LIN0_SCAN_TIME + port * 4, 20);
10575 REG_WR(sc, TM_REG_LIN0_MAX_ACTIVE_CID + port * 4, 31);
10578 ecore_init_block(sc, BLOCK_DORQ, init_phase);
10580 ecore_init_block(sc, BLOCK_BRB1, init_phase);
10582 if (CHIP_IS_E1H(sc)) {
10584 low = (BNX2X_ONE_PORT(sc) ? 160 : 246);
10585 } else if (sc->mtu > 4096) {
10586 if (BNX2X_ONE_PORT(sc)) {
10590 /* (24*1024 + val*4)/256 */
10591 low = (96 + (val / 64) + ((val % 64) ? 1 : 0));
10594 low = (BNX2X_ONE_PORT(sc) ? 80 : 160);
10596 high = (low + 56); /* 14*1024/256 */
10597 REG_WR(sc, BRB1_REG_PAUSE_LOW_THRESHOLD_0 + port * 4, low);
10598 REG_WR(sc, BRB1_REG_PAUSE_HIGH_THRESHOLD_0 + port * 4, high);
10601 if (CHIP_IS_MODE_4_PORT(sc)) {
10602 REG_WR(sc, SC_PORT(sc) ?
10603 BRB1_REG_MAC_GUARANTIED_1 :
10604 BRB1_REG_MAC_GUARANTIED_0, 40);
10607 ecore_init_block(sc, BLOCK_PRS, init_phase);
10608 if (CHIP_IS_E3B0(sc)) {
10609 if (IS_MF_AFEX(sc)) {
10610 /* configure headers for AFEX mode */
10612 REG_WR(sc, PRS_REG_HDRS_AFTER_BASIC_PORT_1,
10614 REG_WR(sc, PRS_REG_HDRS_AFTER_TAG_0_PORT_1,
10616 REG_WR(sc, PRS_REG_MUST_HAVE_HDRS_PORT_1, 0xA);
10618 REG_WR(sc, PRS_REG_HDRS_AFTER_BASIC_PORT_0,
10620 REG_WR(sc, PRS_REG_HDRS_AFTER_TAG_0_PORT_0,
10622 REG_WR(sc, PRS_REG_MUST_HAVE_HDRS_PORT_0, 0xA);
10625 /* Ovlan exists only if we are in multi-function +
10626 * switch-dependent mode, in switch-independent there
10627 * is no ovlan headers
10629 REG_WR(sc, SC_PORT(sc) ?
10630 PRS_REG_HDRS_AFTER_BASIC_PORT_1 :
10631 PRS_REG_HDRS_AFTER_BASIC_PORT_0,
10632 (sc->devinfo.mf_info.path_has_ovlan ? 7 : 6));
10636 ecore_init_block(sc, BLOCK_TSDM, init_phase);
10637 ecore_init_block(sc, BLOCK_CSDM, init_phase);
10638 ecore_init_block(sc, BLOCK_USDM, init_phase);
10639 ecore_init_block(sc, BLOCK_XSDM, init_phase);
10641 ecore_init_block(sc, BLOCK_TSEM, init_phase);
10642 ecore_init_block(sc, BLOCK_USEM, init_phase);
10643 ecore_init_block(sc, BLOCK_CSEM, init_phase);
10644 ecore_init_block(sc, BLOCK_XSEM, init_phase);
10646 ecore_init_block(sc, BLOCK_UPB, init_phase);
10647 ecore_init_block(sc, BLOCK_XPB, init_phase);
10649 ecore_init_block(sc, BLOCK_PBF, init_phase);
10651 if (CHIP_IS_E1x(sc)) {
10652 /* configure PBF to work without PAUSE mtu 9000 */
10653 REG_WR(sc, PBF_REG_P0_PAUSE_ENABLE + port * 4, 0);
10655 /* update threshold */
10656 REG_WR(sc, PBF_REG_P0_ARB_THRSH + port * 4, (9040 / 16));
10657 /* update init credit */
10658 REG_WR(sc, PBF_REG_P0_INIT_CRD + port * 4,
10659 (9040 / 16) + 553 - 22);
10661 /* probe changes */
10662 REG_WR(sc, PBF_REG_INIT_P0 + port * 4, 1);
10664 REG_WR(sc, PBF_REG_INIT_P0 + port * 4, 0);
10667 if (CNIC_SUPPORT(sc)) {
10668 ecore_init_block(sc, BLOCK_SRC, init_phase);
10671 ecore_init_block(sc, BLOCK_CDU, init_phase);
10672 ecore_init_block(sc, BLOCK_CFC, init_phase);
10673 ecore_init_block(sc, BLOCK_HC, init_phase);
10674 ecore_init_block(sc, BLOCK_IGU, init_phase);
10675 ecore_init_block(sc, BLOCK_MISC_AEU, init_phase);
10676 /* init aeu_mask_attn_func_0/1:
10677 * - SF mode: bits 3-7 are masked. only bits 0-2 are in use
10678 * - MF mode: bit 3 is masked. bits 0-2 are in use as in SF
10679 * bits 4-7 are used for "per vn group attention" */
10680 val = IS_MF(sc) ? 0xF7 : 0x7;
10682 REG_WR(sc, MISC_REG_AEU_MASK_ATTN_FUNC_0 + port * 4, val);
10684 ecore_init_block(sc, BLOCK_NIG, init_phase);
10686 if (!CHIP_IS_E1x(sc)) {
10687 /* Bit-map indicating which L2 hdrs may appear after the
10688 * basic Ethernet header
10690 if (IS_MF_AFEX(sc)) {
10691 REG_WR(sc, SC_PORT(sc) ?
10692 NIG_REG_P1_HDRS_AFTER_BASIC :
10693 NIG_REG_P0_HDRS_AFTER_BASIC, 0xE);
10695 REG_WR(sc, SC_PORT(sc) ?
10696 NIG_REG_P1_HDRS_AFTER_BASIC :
10697 NIG_REG_P0_HDRS_AFTER_BASIC,
10698 IS_MF_SD(sc) ? 7 : 6);
10701 if (CHIP_IS_E3(sc)) {
10702 REG_WR(sc, SC_PORT(sc) ?
10703 NIG_REG_LLH1_MF_MODE :
10704 NIG_REG_LLH_MF_MODE, IS_MF(sc));
10707 if (!CHIP_IS_E3(sc)) {
10708 REG_WR(sc, NIG_REG_XGXS_SERDES0_MODE_SEL + port * 4, 1);
10711 /* 0x2 disable mf_ov, 0x1 enable */
10712 REG_WR(sc, NIG_REG_LLH0_BRB1_DRV_MASK_MF + port * 4,
10713 (IS_MF_SD(sc) ? 0x1 : 0x2));
10715 if (!CHIP_IS_E1x(sc)) {
10717 switch (sc->devinfo.mf_info.mf_mode) {
10718 case MULTI_FUNCTION_SD:
10721 case MULTI_FUNCTION_SI:
10722 case MULTI_FUNCTION_AFEX:
10727 REG_WR(sc, (SC_PORT(sc) ? NIG_REG_LLH1_CLS_TYPE :
10728 NIG_REG_LLH0_CLS_TYPE), val);
10730 REG_WR(sc, NIG_REG_LLFC_ENABLE_0 + port * 4, 0);
10731 REG_WR(sc, NIG_REG_LLFC_OUT_EN_0 + port * 4, 0);
10732 REG_WR(sc, NIG_REG_PAUSE_ENABLE_0 + port * 4, 1);
10734 /* If SPIO5 is set to generate interrupts, enable it for this port */
10735 val = REG_RD(sc, MISC_REG_SPIO_EVENT_EN);
10736 if (val & MISC_SPIO_SPIO5) {
10737 uint32_t reg_addr = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 :
10738 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0);
10739 val = REG_RD(sc, reg_addr);
10740 val |= AEU_INPUTS_ATTN_BITS_SPIO5;
10741 REG_WR(sc, reg_addr, val);
10748 bnx2x_flr_clnup_reg_poll(struct bnx2x_softc *sc, uint32_t reg,
10749 uint32_t expected, uint32_t poll_count)
10751 uint32_t cur_cnt = poll_count;
10754 while ((val = REG_RD(sc, reg)) != expected && cur_cnt--) {
10755 DELAY(FLR_WAIT_INTERVAL);
10762 bnx2x_flr_clnup_poll_hw_counter(struct bnx2x_softc *sc, uint32_t reg,
10763 __rte_unused const char *msg, uint32_t poll_cnt)
10765 uint32_t val = bnx2x_flr_clnup_reg_poll(sc, reg, 0, poll_cnt);
10768 PMD_DRV_LOG(NOTICE, "%s usage count=%d", msg, val);
10775 /* Common routines with VF FLR cleanup */
10776 static uint32_t bnx2x_flr_clnup_poll_count(struct bnx2x_softc *sc)
10778 /* adjust polling timeout */
10779 if (CHIP_REV_IS_EMUL(sc)) {
10780 return (FLR_POLL_CNT * 2000);
10783 if (CHIP_REV_IS_FPGA(sc)) {
10784 return (FLR_POLL_CNT * 120);
10787 return FLR_POLL_CNT;
10790 static int bnx2x_poll_hw_usage_counters(struct bnx2x_softc *sc, uint32_t poll_cnt)
10792 /* wait for CFC PF usage-counter to zero (includes all the VFs) */
10793 if (bnx2x_flr_clnup_poll_hw_counter(sc,
10794 CFC_REG_NUM_LCIDS_INSIDE_PF,
10795 "CFC PF usage counter timed out",
10800 /* Wait for DQ PF usage-counter to zero (until DQ cleanup) */
10801 if (bnx2x_flr_clnup_poll_hw_counter(sc,
10802 DORQ_REG_PF_USAGE_CNT,
10803 "DQ PF usage counter timed out",
10808 /* Wait for QM PF usage-counter to zero (until DQ cleanup) */
10809 if (bnx2x_flr_clnup_poll_hw_counter(sc,
10810 QM_REG_PF_USG_CNT_0 + 4 * SC_FUNC(sc),
10811 "QM PF usage counter timed out",
10816 /* Wait for Timer PF usage-counters to zero (until DQ cleanup) */
10817 if (bnx2x_flr_clnup_poll_hw_counter(sc,
10818 TM_REG_LIN0_VNIC_UC + 4 * SC_PORT(sc),
10819 "Timers VNIC usage counter timed out",
10824 if (bnx2x_flr_clnup_poll_hw_counter(sc,
10825 TM_REG_LIN0_NUM_SCANS +
10827 "Timers NUM_SCANS usage counter timed out",
10832 /* Wait DMAE PF usage counter to zero */
10833 if (bnx2x_flr_clnup_poll_hw_counter(sc,
10834 dmae_reg_go_c[INIT_DMAE_C(sc)],
10835 "DMAE dommand register timed out",
10843 #define OP_GEN_PARAM(param) \
10844 (((param) << SDM_OP_GEN_COMP_PARAM_SHIFT) & SDM_OP_GEN_COMP_PARAM)
10845 #define OP_GEN_TYPE(type) \
10846 (((type) << SDM_OP_GEN_COMP_TYPE_SHIFT) & SDM_OP_GEN_COMP_TYPE)
10847 #define OP_GEN_AGG_VECT(index) \
10848 (((index) << SDM_OP_GEN_AGG_VECT_IDX_SHIFT) & SDM_OP_GEN_AGG_VECT_IDX)
10851 bnx2x_send_final_clnup(struct bnx2x_softc *sc, uint8_t clnup_func,
10854 uint32_t op_gen_command = 0;
10855 uint32_t comp_addr = (BAR_CSTRORM_INTMEM +
10856 CSTORM_FINAL_CLEANUP_COMPLETE_OFFSET(clnup_func));
10859 if (REG_RD(sc, comp_addr)) {
10860 PMD_DRV_LOG(NOTICE,
10861 "Cleanup complete was not 0 before sending");
10865 op_gen_command |= OP_GEN_PARAM(XSTORM_AGG_INT_FINAL_CLEANUP_INDEX);
10866 op_gen_command |= OP_GEN_TYPE(XSTORM_AGG_INT_FINAL_CLEANUP_COMP_TYPE);
10867 op_gen_command |= OP_GEN_AGG_VECT(clnup_func);
10868 op_gen_command |= 1 << SDM_OP_GEN_AGG_VECT_IDX_VALID_SHIFT;
10870 REG_WR(sc, XSDM_REG_OPERATION_GEN, op_gen_command);
10872 if (bnx2x_flr_clnup_reg_poll(sc, comp_addr, 1, poll_cnt) != 1) {
10873 PMD_DRV_LOG(NOTICE, "FW final cleanup did not succeed");
10874 PMD_DRV_LOG(DEBUG, "At timeout completion address contained %x",
10875 (REG_RD(sc, comp_addr)));
10876 rte_panic("FLR cleanup failed");
10880 /* Zero completion for nxt FLR */
10881 REG_WR(sc, comp_addr, 0);
10887 bnx2x_pbf_pN_buf_flushed(struct bnx2x_softc *sc, struct pbf_pN_buf_regs *regs,
10888 uint32_t poll_count)
10890 uint32_t init_crd, crd, crd_start, crd_freed, crd_freed_start;
10891 uint32_t cur_cnt = poll_count;
10893 crd_freed = crd_freed_start = REG_RD(sc, regs->crd_freed);
10894 crd = crd_start = REG_RD(sc, regs->crd);
10895 init_crd = REG_RD(sc, regs->init_crd);
10897 while ((crd != init_crd) &&
10898 ((uint32_t) ((int32_t) crd_freed - (int32_t) crd_freed_start) <
10899 (init_crd - crd_start))) {
10901 DELAY(FLR_WAIT_INTERVAL);
10902 crd = REG_RD(sc, regs->crd);
10903 crd_freed = REG_RD(sc, regs->crd_freed);
10911 bnx2x_pbf_pN_cmd_flushed(struct bnx2x_softc *sc, struct pbf_pN_cmd_regs *regs,
10912 uint32_t poll_count)
10914 uint32_t occup, to_free, freed, freed_start;
10915 uint32_t cur_cnt = poll_count;
10917 occup = to_free = REG_RD(sc, regs->lines_occup);
10918 freed = freed_start = REG_RD(sc, regs->lines_freed);
10921 ((uint32_t) ((int32_t) freed - (int32_t) freed_start) <
10924 DELAY(FLR_WAIT_INTERVAL);
10925 occup = REG_RD(sc, regs->lines_occup);
10926 freed = REG_RD(sc, regs->lines_freed);
10933 static void bnx2x_tx_hw_flushed(struct bnx2x_softc *sc, uint32_t poll_count)
10935 struct pbf_pN_cmd_regs cmd_regs[] = {
10936 {0, (CHIP_IS_E3B0(sc)) ?
10937 PBF_REG_TQ_OCCUPANCY_Q0 : PBF_REG_P0_TQ_OCCUPANCY,
10938 (CHIP_IS_E3B0(sc)) ?
10939 PBF_REG_TQ_LINES_FREED_CNT_Q0 : PBF_REG_P0_TQ_LINES_FREED_CNT},
10940 {1, (CHIP_IS_E3B0(sc)) ?
10941 PBF_REG_TQ_OCCUPANCY_Q1 : PBF_REG_P1_TQ_OCCUPANCY,
10942 (CHIP_IS_E3B0(sc)) ?
10943 PBF_REG_TQ_LINES_FREED_CNT_Q1 : PBF_REG_P1_TQ_LINES_FREED_CNT},
10944 {4, (CHIP_IS_E3B0(sc)) ?
10945 PBF_REG_TQ_OCCUPANCY_LB_Q : PBF_REG_P4_TQ_OCCUPANCY,
10946 (CHIP_IS_E3B0(sc)) ?
10947 PBF_REG_TQ_LINES_FREED_CNT_LB_Q :
10948 PBF_REG_P4_TQ_LINES_FREED_CNT}
10951 struct pbf_pN_buf_regs buf_regs[] = {
10952 {0, (CHIP_IS_E3B0(sc)) ?
10953 PBF_REG_INIT_CRD_Q0 : PBF_REG_P0_INIT_CRD,
10954 (CHIP_IS_E3B0(sc)) ? PBF_REG_CREDIT_Q0 : PBF_REG_P0_CREDIT,
10955 (CHIP_IS_E3B0(sc)) ?
10956 PBF_REG_INTERNAL_CRD_FREED_CNT_Q0 :
10957 PBF_REG_P0_INTERNAL_CRD_FREED_CNT},
10958 {1, (CHIP_IS_E3B0(sc)) ?
10959 PBF_REG_INIT_CRD_Q1 : PBF_REG_P1_INIT_CRD,
10960 (CHIP_IS_E3B0(sc)) ? PBF_REG_CREDIT_Q1 : PBF_REG_P1_CREDIT,
10961 (CHIP_IS_E3B0(sc)) ?
10962 PBF_REG_INTERNAL_CRD_FREED_CNT_Q1 :
10963 PBF_REG_P1_INTERNAL_CRD_FREED_CNT},
10964 {4, (CHIP_IS_E3B0(sc)) ?
10965 PBF_REG_INIT_CRD_LB_Q : PBF_REG_P4_INIT_CRD,
10966 (CHIP_IS_E3B0(sc)) ? PBF_REG_CREDIT_LB_Q : PBF_REG_P4_CREDIT,
10967 (CHIP_IS_E3B0(sc)) ?
10968 PBF_REG_INTERNAL_CRD_FREED_CNT_LB_Q :
10969 PBF_REG_P4_INTERNAL_CRD_FREED_CNT},
10974 /* Verify the command queues are flushed P0, P1, P4 */
10975 for (i = 0; i < ARRAY_SIZE(cmd_regs); i++) {
10976 bnx2x_pbf_pN_cmd_flushed(sc, &cmd_regs[i], poll_count);
10979 /* Verify the transmission buffers are flushed P0, P1, P4 */
10980 for (i = 0; i < ARRAY_SIZE(buf_regs); i++) {
10981 bnx2x_pbf_pN_buf_flushed(sc, &buf_regs[i], poll_count);
10985 static void bnx2x_hw_enable_status(struct bnx2x_softc *sc)
10987 __rte_unused uint32_t val;
10989 val = REG_RD(sc, CFC_REG_WEAK_ENABLE_PF);
10990 PMD_DRV_LOG(DEBUG, "CFC_REG_WEAK_ENABLE_PF is 0x%x", val);
10992 val = REG_RD(sc, PBF_REG_DISABLE_PF);
10993 PMD_DRV_LOG(DEBUG, "PBF_REG_DISABLE_PF is 0x%x", val);
10995 val = REG_RD(sc, IGU_REG_PCI_PF_MSI_EN);
10996 PMD_DRV_LOG(DEBUG, "IGU_REG_PCI_PF_MSI_EN is 0x%x", val);
10998 val = REG_RD(sc, IGU_REG_PCI_PF_MSIX_EN);
10999 PMD_DRV_LOG(DEBUG, "IGU_REG_PCI_PF_MSIX_EN is 0x%x", val);
11001 val = REG_RD(sc, IGU_REG_PCI_PF_MSIX_FUNC_MASK);
11002 PMD_DRV_LOG(DEBUG, "IGU_REG_PCI_PF_MSIX_FUNC_MASK is 0x%x", val);
11004 val = REG_RD(sc, PGLUE_B_REG_SHADOW_BME_PF_7_0_CLR);
11005 PMD_DRV_LOG(DEBUG, "PGLUE_B_REG_SHADOW_BME_PF_7_0_CLR is 0x%x", val);
11007 val = REG_RD(sc, PGLUE_B_REG_FLR_REQUEST_PF_7_0_CLR);
11008 PMD_DRV_LOG(DEBUG, "PGLUE_B_REG_FLR_REQUEST_PF_7_0_CLR is 0x%x", val);
11010 val = REG_RD(sc, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER);
11011 PMD_DRV_LOG(DEBUG, "PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER is 0x%x",
11016 * bnx2x_pf_flr_clnup
11017 * a. re-enable target read on the PF
11018 * b. poll cfc per function usgae counter
11019 * c. poll the qm perfunction usage counter
11020 * d. poll the tm per function usage counter
11021 * e. poll the tm per function scan-done indication
11022 * f. clear the dmae channel associated wit hthe PF
11023 * g. zero the igu 'trailing edge' and 'leading edge' regs (attentions)
11024 * h. call the common flr cleanup code with -1 (pf indication)
11026 static int bnx2x_pf_flr_clnup(struct bnx2x_softc *sc)
11028 uint32_t poll_cnt = bnx2x_flr_clnup_poll_count(sc);
11030 /* Re-enable PF target read access */
11031 REG_WR(sc, PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_READ, 1);
11033 /* Poll HW usage counters */
11034 if (bnx2x_poll_hw_usage_counters(sc, poll_cnt)) {
11038 /* Zero the igu 'trailing edge' and 'leading edge' */
11040 /* Send the FW cleanup command */
11041 if (bnx2x_send_final_clnup(sc, (uint8_t) SC_FUNC(sc), poll_cnt)) {
11047 /* Verify TX hw is flushed */
11048 bnx2x_tx_hw_flushed(sc, poll_cnt);
11050 /* Wait 100ms (not adjusted according to platform) */
11053 /* Verify no pending pci transactions */
11054 if (bnx2x_is_pcie_pending(sc)) {
11055 PMD_DRV_LOG(NOTICE, "PCIE Transactions still pending");
11059 bnx2x_hw_enable_status(sc);
11062 * Master enable - Due to WB DMAE writes performed before this
11063 * register is re-initialized as part of the regular function init
11065 REG_WR(sc, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 1);
11070 static int bnx2x_init_hw_func(struct bnx2x_softc *sc)
11072 int port = SC_PORT(sc);
11073 int func = SC_FUNC(sc);
11074 int init_phase = PHASE_PF0 + func;
11075 struct ecore_ilt *ilt = sc->ilt;
11076 uint16_t cdu_ilt_start;
11077 uint32_t addr, val;
11078 uint32_t main_mem_base, main_mem_size, main_mem_prty_clr;
11079 int main_mem_width, rc;
11082 PMD_DRV_LOG(DEBUG, "starting func init for func %d", func);
11085 if (!CHIP_IS_E1x(sc)) {
11086 rc = bnx2x_pf_flr_clnup(sc);
11088 PMD_DRV_LOG(NOTICE, "FLR cleanup failed!");
11093 /* set MSI reconfigure capability */
11094 if (sc->devinfo.int_block == INT_BLOCK_HC) {
11095 addr = (port ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0);
11096 val = REG_RD(sc, addr);
11097 val |= HC_CONFIG_0_REG_MSI_ATTN_EN_0;
11098 REG_WR(sc, addr, val);
11101 ecore_init_block(sc, BLOCK_PXP, init_phase);
11102 ecore_init_block(sc, BLOCK_PXP2, init_phase);
11105 cdu_ilt_start = ilt->clients[ILT_CLIENT_CDU].start;
11107 for (i = 0; i < L2_ILT_LINES(sc); i++) {
11108 ilt->lines[cdu_ilt_start + i].page = sc->context[i].vcxt;
11109 ilt->lines[cdu_ilt_start + i].page_mapping =
11110 (phys_addr_t)sc->context[i].vcxt_dma.paddr;
11111 ilt->lines[cdu_ilt_start + i].size = sc->context[i].size;
11113 ecore_ilt_init_op(sc, INITOP_SET);
11115 REG_WR(sc, PRS_REG_NIC_MODE, 1);
11117 if (!CHIP_IS_E1x(sc)) {
11118 uint32_t pf_conf = IGU_PF_CONF_FUNC_EN;
11120 /* Turn on a single ISR mode in IGU if driver is going to use
11123 if ((sc->interrupt_mode != INTR_MODE_MSIX)
11124 || (sc->interrupt_mode != INTR_MODE_SINGLE_MSIX)) {
11125 pf_conf |= IGU_PF_CONF_SINGLE_ISR_EN;
11129 * Timers workaround bug: function init part.
11130 * Need to wait 20msec after initializing ILT,
11131 * needed to make sure there are no requests in
11132 * one of the PXP internal queues with "old" ILT addresses
11137 * Master enable - Due to WB DMAE writes performed before this
11138 * register is re-initialized as part of the regular function
11141 REG_WR(sc, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 1);
11142 /* Enable the function in IGU */
11143 REG_WR(sc, IGU_REG_PF_CONFIGURATION, pf_conf);
11146 sc->dmae_ready = 1;
11148 ecore_init_block(sc, BLOCK_PGLUE_B, init_phase);
11150 if (!CHIP_IS_E1x(sc))
11151 REG_WR(sc, PGLUE_B_REG_WAS_ERROR_PF_7_0_CLR, func);
11153 ecore_init_block(sc, BLOCK_ATC, init_phase);
11154 ecore_init_block(sc, BLOCK_DMAE, init_phase);
11155 ecore_init_block(sc, BLOCK_NIG, init_phase);
11156 ecore_init_block(sc, BLOCK_SRC, init_phase);
11157 ecore_init_block(sc, BLOCK_MISC, init_phase);
11158 ecore_init_block(sc, BLOCK_TCM, init_phase);
11159 ecore_init_block(sc, BLOCK_UCM, init_phase);
11160 ecore_init_block(sc, BLOCK_CCM, init_phase);
11161 ecore_init_block(sc, BLOCK_XCM, init_phase);
11162 ecore_init_block(sc, BLOCK_TSEM, init_phase);
11163 ecore_init_block(sc, BLOCK_USEM, init_phase);
11164 ecore_init_block(sc, BLOCK_CSEM, init_phase);
11165 ecore_init_block(sc, BLOCK_XSEM, init_phase);
11167 if (!CHIP_IS_E1x(sc))
11168 REG_WR(sc, QM_REG_PF_EN, 1);
11170 if (!CHIP_IS_E1x(sc)) {
11171 REG_WR(sc, TSEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func);
11172 REG_WR(sc, USEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func);
11173 REG_WR(sc, CSEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func);
11174 REG_WR(sc, XSEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func);
11176 ecore_init_block(sc, BLOCK_QM, init_phase);
11178 ecore_init_block(sc, BLOCK_TM, init_phase);
11179 ecore_init_block(sc, BLOCK_DORQ, init_phase);
11181 ecore_init_block(sc, BLOCK_BRB1, init_phase);
11182 ecore_init_block(sc, BLOCK_PRS, init_phase);
11183 ecore_init_block(sc, BLOCK_TSDM, init_phase);
11184 ecore_init_block(sc, BLOCK_CSDM, init_phase);
11185 ecore_init_block(sc, BLOCK_USDM, init_phase);
11186 ecore_init_block(sc, BLOCK_XSDM, init_phase);
11187 ecore_init_block(sc, BLOCK_UPB, init_phase);
11188 ecore_init_block(sc, BLOCK_XPB, init_phase);
11189 ecore_init_block(sc, BLOCK_PBF, init_phase);
11190 if (!CHIP_IS_E1x(sc))
11191 REG_WR(sc, PBF_REG_DISABLE_PF, 0);
11193 ecore_init_block(sc, BLOCK_CDU, init_phase);
11195 ecore_init_block(sc, BLOCK_CFC, init_phase);
11197 if (!CHIP_IS_E1x(sc))
11198 REG_WR(sc, CFC_REG_WEAK_ENABLE_PF, 1);
11201 REG_WR(sc, NIG_REG_LLH0_FUNC_EN + port * 8, 1);
11202 REG_WR(sc, NIG_REG_LLH0_FUNC_VLAN_ID + port * 8, OVLAN(sc));
11205 ecore_init_block(sc, BLOCK_MISC_AEU, init_phase);
11207 /* HC init per function */
11208 if (sc->devinfo.int_block == INT_BLOCK_HC) {
11209 if (CHIP_IS_E1H(sc)) {
11210 REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_12 + func * 4, 0);
11212 REG_WR(sc, HC_REG_LEADING_EDGE_0 + port * 8, 0);
11213 REG_WR(sc, HC_REG_TRAILING_EDGE_0 + port * 8, 0);
11215 ecore_init_block(sc, BLOCK_HC, init_phase);
11218 uint32_t num_segs, sb_idx, prod_offset;
11220 REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_12 + func * 4, 0);
11222 if (!CHIP_IS_E1x(sc)) {
11223 REG_WR(sc, IGU_REG_LEADING_EDGE_LATCH, 0);
11224 REG_WR(sc, IGU_REG_TRAILING_EDGE_LATCH, 0);
11227 ecore_init_block(sc, BLOCK_IGU, init_phase);
11229 if (!CHIP_IS_E1x(sc)) {
11233 * E2 mode: address 0-135 match to the mapping memory;
11234 * 136 - PF0 default prod; 137 - PF1 default prod;
11235 * 138 - PF2 default prod; 139 - PF3 default prod;
11236 * 140 - PF0 attn prod; 141 - PF1 attn prod;
11237 * 142 - PF2 attn prod; 143 - PF3 attn prod;
11238 * 144-147 reserved.
11240 * E1.5 mode - In backward compatible mode;
11241 * for non default SB; each even line in the memory
11242 * holds the U producer and each odd line hold
11243 * the C producer. The first 128 producers are for
11244 * NDSB (PF0 - 0-31; PF1 - 32-63 and so on). The last 20
11245 * producers are for the DSB for each PF.
11246 * Each PF has five segments: (the order inside each
11247 * segment is PF0; PF1; PF2; PF3) - 128-131 U prods;
11248 * 132-135 C prods; 136-139 X prods; 140-143 T prods;
11249 * 144-147 attn prods;
11251 /* non-default-status-blocks */
11252 num_segs = CHIP_INT_MODE_IS_BC(sc) ?
11253 IGU_BC_NDSB_NUM_SEGS : IGU_NORM_NDSB_NUM_SEGS;
11254 for (sb_idx = 0; sb_idx < sc->igu_sb_cnt; sb_idx++) {
11255 prod_offset = (sc->igu_base_sb + sb_idx) *
11258 for (i = 0; i < num_segs; i++) {
11259 addr = IGU_REG_PROD_CONS_MEMORY +
11260 (prod_offset + i) * 4;
11261 REG_WR(sc, addr, 0);
11263 /* send consumer update with value 0 */
11264 bnx2x_ack_sb(sc, sc->igu_base_sb + sb_idx,
11265 USTORM_ID, 0, IGU_INT_NOP, 1);
11266 bnx2x_igu_clear_sb(sc, sc->igu_base_sb + sb_idx);
11269 /* default-status-blocks */
11270 num_segs = CHIP_INT_MODE_IS_BC(sc) ?
11271 IGU_BC_DSB_NUM_SEGS : IGU_NORM_DSB_NUM_SEGS;
11273 if (CHIP_IS_MODE_4_PORT(sc))
11274 dsb_idx = SC_FUNC(sc);
11276 dsb_idx = SC_VN(sc);
11278 prod_offset = (CHIP_INT_MODE_IS_BC(sc) ?
11279 IGU_BC_BASE_DSB_PROD + dsb_idx :
11280 IGU_NORM_BASE_DSB_PROD + dsb_idx);
11283 * igu prods come in chunks of E1HVN_MAX (4) -
11284 * does not matters what is the current chip mode
11286 for (i = 0; i < (num_segs * E1HVN_MAX); i += E1HVN_MAX) {
11287 addr = IGU_REG_PROD_CONS_MEMORY +
11288 (prod_offset + i) * 4;
11289 REG_WR(sc, addr, 0);
11291 /* send consumer update with 0 */
11292 if (CHIP_INT_MODE_IS_BC(sc)) {
11293 bnx2x_ack_sb(sc, sc->igu_dsb_id,
11294 USTORM_ID, 0, IGU_INT_NOP, 1);
11295 bnx2x_ack_sb(sc, sc->igu_dsb_id,
11296 CSTORM_ID, 0, IGU_INT_NOP, 1);
11297 bnx2x_ack_sb(sc, sc->igu_dsb_id,
11298 XSTORM_ID, 0, IGU_INT_NOP, 1);
11299 bnx2x_ack_sb(sc, sc->igu_dsb_id,
11300 TSTORM_ID, 0, IGU_INT_NOP, 1);
11301 bnx2x_ack_sb(sc, sc->igu_dsb_id,
11302 ATTENTION_ID, 0, IGU_INT_NOP, 1);
11304 bnx2x_ack_sb(sc, sc->igu_dsb_id,
11305 USTORM_ID, 0, IGU_INT_NOP, 1);
11306 bnx2x_ack_sb(sc, sc->igu_dsb_id,
11307 ATTENTION_ID, 0, IGU_INT_NOP, 1);
11309 bnx2x_igu_clear_sb(sc, sc->igu_dsb_id);
11311 /* !!! these should become driver const once
11312 rf-tool supports split-68 const */
11313 REG_WR(sc, IGU_REG_SB_INT_BEFORE_MASK_LSB, 0);
11314 REG_WR(sc, IGU_REG_SB_INT_BEFORE_MASK_MSB, 0);
11315 REG_WR(sc, IGU_REG_SB_MASK_LSB, 0);
11316 REG_WR(sc, IGU_REG_SB_MASK_MSB, 0);
11317 REG_WR(sc, IGU_REG_PBA_STATUS_LSB, 0);
11318 REG_WR(sc, IGU_REG_PBA_STATUS_MSB, 0);
11322 /* Reset PCIE errors for debug */
11323 REG_WR(sc, 0x2114, 0xffffffff);
11324 REG_WR(sc, 0x2120, 0xffffffff);
11326 if (CHIP_IS_E1x(sc)) {
11327 main_mem_size = HC_REG_MAIN_MEMORY_SIZE / 2; /*dwords */
11328 main_mem_base = HC_REG_MAIN_MEMORY +
11329 SC_PORT(sc) * (main_mem_size * 4);
11330 main_mem_prty_clr = HC_REG_HC_PRTY_STS_CLR;
11331 main_mem_width = 8;
11333 val = REG_RD(sc, main_mem_prty_clr);
11336 "Parity errors in HC block during function init (0x%x)!",
11340 /* Clear "false" parity errors in MSI-X table */
11341 for (i = main_mem_base;
11342 i < main_mem_base + main_mem_size * 4;
11343 i += main_mem_width) {
11344 bnx2x_read_dmae(sc, i, main_mem_width / 4);
11345 bnx2x_write_dmae(sc, BNX2X_SP_MAPPING(sc, wb_data),
11346 i, main_mem_width / 4);
11348 /* Clear HC parity attention */
11349 REG_RD(sc, main_mem_prty_clr);
11352 /* Enable STORMs SP logging */
11353 REG_WR8(sc, BAR_USTRORM_INTMEM +
11354 USTORM_RECORD_SLOW_PATH_OFFSET(SC_FUNC(sc)), 1);
11355 REG_WR8(sc, BAR_TSTRORM_INTMEM +
11356 TSTORM_RECORD_SLOW_PATH_OFFSET(SC_FUNC(sc)), 1);
11357 REG_WR8(sc, BAR_CSTRORM_INTMEM +
11358 CSTORM_RECORD_SLOW_PATH_OFFSET(SC_FUNC(sc)), 1);
11359 REG_WR8(sc, BAR_XSTRORM_INTMEM +
11360 XSTORM_RECORD_SLOW_PATH_OFFSET(SC_FUNC(sc)), 1);
11362 elink_phy_probe(&sc->link_params);
11367 static void bnx2x_link_reset(struct bnx2x_softc *sc)
11369 if (!BNX2X_NOMCP(sc)) {
11370 elink_lfa_reset(&sc->link_params, &sc->link_vars);
11372 if (!CHIP_REV_IS_SLOW(sc)) {
11373 PMD_DRV_LOG(WARNING,
11374 "Bootcode is missing - cannot reset link");
11379 static void bnx2x_reset_port(struct bnx2x_softc *sc)
11381 int port = SC_PORT(sc);
11384 /* reset physical Link */
11385 bnx2x_link_reset(sc);
11387 REG_WR(sc, NIG_REG_MASK_INTERRUPT_PORT0 + port * 4, 0);
11389 /* Do not rcv packets to BRB */
11390 REG_WR(sc, NIG_REG_LLH0_BRB1_DRV_MASK + port * 4, 0x0);
11391 /* Do not direct rcv packets that are not for MCP to the BRB */
11392 REG_WR(sc, (port ? NIG_REG_LLH1_BRB1_NOT_MCP :
11393 NIG_REG_LLH0_BRB1_NOT_MCP), 0x0);
11395 /* Configure AEU */
11396 REG_WR(sc, MISC_REG_AEU_MASK_ATTN_FUNC_0 + port * 4, 0);
11400 /* Check for BRB port occupancy */
11401 val = REG_RD(sc, BRB1_REG_PORT_NUM_OCC_BLOCKS_0 + port * 4);
11404 "BRB1 is not empty, %d blocks are occupied", val);
11408 static void bnx2x_ilt_wr(struct bnx2x_softc *sc, uint32_t index, phys_addr_t addr)
11411 uint32_t wb_write[2];
11413 reg = PXP2_REG_RQ_ONCHIP_AT_B0 + index * 8;
11415 wb_write[0] = ONCHIP_ADDR1(addr);
11416 wb_write[1] = ONCHIP_ADDR2(addr);
11417 REG_WR_DMAE(sc, reg, wb_write, 2);
11420 static void bnx2x_clear_func_ilt(struct bnx2x_softc *sc, uint32_t func)
11422 uint32_t i, base = FUNC_ILT_BASE(func);
11423 for (i = base; i < base + ILT_PER_FUNC; i++) {
11424 bnx2x_ilt_wr(sc, i, 0);
11428 static void bnx2x_reset_func(struct bnx2x_softc *sc)
11430 struct bnx2x_fastpath *fp;
11431 int port = SC_PORT(sc);
11432 int func = SC_FUNC(sc);
11435 /* Disable the function in the FW */
11436 REG_WR8(sc, BAR_XSTRORM_INTMEM + XSTORM_FUNC_EN_OFFSET(func), 0);
11437 REG_WR8(sc, BAR_CSTRORM_INTMEM + CSTORM_FUNC_EN_OFFSET(func), 0);
11438 REG_WR8(sc, BAR_TSTRORM_INTMEM + TSTORM_FUNC_EN_OFFSET(func), 0);
11439 REG_WR8(sc, BAR_USTRORM_INTMEM + USTORM_FUNC_EN_OFFSET(func), 0);
11442 FOR_EACH_ETH_QUEUE(sc, i) {
11444 REG_WR8(sc, BAR_CSTRORM_INTMEM +
11445 CSTORM_STATUS_BLOCK_DATA_STATE_OFFSET(fp->fw_sb_id),
11450 REG_WR8(sc, BAR_CSTRORM_INTMEM +
11451 CSTORM_SP_STATUS_BLOCK_DATA_STATE_OFFSET(func), SB_DISABLED);
11453 for (i = 0; i < XSTORM_SPQ_DATA_SIZE / 4; i++) {
11454 REG_WR(sc, BAR_XSTRORM_INTMEM + XSTORM_SPQ_DATA_OFFSET(func),
11458 /* Configure IGU */
11459 if (sc->devinfo.int_block == INT_BLOCK_HC) {
11460 REG_WR(sc, HC_REG_LEADING_EDGE_0 + port * 8, 0);
11461 REG_WR(sc, HC_REG_TRAILING_EDGE_0 + port * 8, 0);
11463 REG_WR(sc, IGU_REG_LEADING_EDGE_LATCH, 0);
11464 REG_WR(sc, IGU_REG_TRAILING_EDGE_LATCH, 0);
11467 if (CNIC_LOADED(sc)) {
11468 /* Disable Timer scan */
11469 REG_WR(sc, TM_REG_EN_LINEAR0_TIMER + port * 4, 0);
11471 * Wait for at least 10ms and up to 2 second for the timers
11474 for (i = 0; i < 200; i++) {
11476 if (!REG_RD(sc, TM_REG_LIN0_SCAN_ON + port * 4))
11482 bnx2x_clear_func_ilt(sc, func);
11485 * Timers workaround bug for E2: if this is vnic-3,
11486 * we need to set the entire ilt range for this timers.
11488 if (!CHIP_IS_E1x(sc) && SC_VN(sc) == 3) {
11489 struct ilt_client_info ilt_cli;
11490 /* use dummy TM client */
11491 memset(&ilt_cli, 0, sizeof(struct ilt_client_info));
11493 ilt_cli.end = ILT_NUM_PAGE_ENTRIES - 1;
11494 ilt_cli.client_num = ILT_CLIENT_TM;
11496 ecore_ilt_boundry_init_op(sc, &ilt_cli, 0);
11499 /* this assumes that reset_port() called before reset_func() */
11500 if (!CHIP_IS_E1x(sc)) {
11501 bnx2x_pf_disable(sc);
11504 sc->dmae_ready = 0;
11507 static void bnx2x_release_firmware(struct bnx2x_softc *sc)
11509 rte_free(sc->init_ops);
11510 rte_free(sc->init_ops_offsets);
11511 rte_free(sc->init_data);
11512 rte_free(sc->iro_array);
11515 static int bnx2x_init_firmware(struct bnx2x_softc *sc)
11518 uint8_t *p = sc->firmware;
11521 for (i = 0; i < 24; ++i)
11522 off[i] = rte_be_to_cpu_32(*((uint32_t *) sc->firmware + i));
11525 sc->init_ops = rte_zmalloc("", len, RTE_CACHE_LINE_SIZE);
11528 bnx2x_data_to_init_ops(p + off[1], sc->init_ops, len);
11531 sc->init_ops_offsets = rte_zmalloc("", len, RTE_CACHE_LINE_SIZE);
11532 if (!sc->init_ops_offsets)
11534 bnx2x_data_to_init_offsets(p + off[3], sc->init_ops_offsets, len);
11537 sc->init_data = rte_zmalloc("", len, RTE_CACHE_LINE_SIZE);
11538 if (!sc->init_data)
11540 bnx2x_data_to_init_data(p + off[5], sc->init_data, len);
11542 sc->tsem_int_table_data = p + off[7];
11543 sc->tsem_pram_data = p + off[9];
11544 sc->usem_int_table_data = p + off[11];
11545 sc->usem_pram_data = p + off[13];
11546 sc->csem_int_table_data = p + off[15];
11547 sc->csem_pram_data = p + off[17];
11548 sc->xsem_int_table_data = p + off[19];
11549 sc->xsem_pram_data = p + off[21];
11552 sc->iro_array = rte_zmalloc("", len, RTE_CACHE_LINE_SIZE);
11553 if (!sc->iro_array)
11555 bnx2x_data_to_iro_array(p + off[23], sc->iro_array, len);
11560 bnx2x_release_firmware(sc);
11564 static int cut_gzip_prefix(const uint8_t * zbuf, int len)
11566 #define MIN_PREFIX_SIZE (10)
11568 int n = MIN_PREFIX_SIZE;
11571 if (!(zbuf[0] == 0x1f && zbuf[1] == 0x8b && zbuf[2] == Z_DEFLATED) ||
11572 len <= MIN_PREFIX_SIZE) {
11576 /* optional extra fields are present */
11577 if (zbuf[3] & 0x4) {
11584 /* file name is present */
11585 if (zbuf[3] & 0x8) {
11586 while ((zbuf[n++] != 0) && (n < len)) ;
11592 static int ecore_gunzip(struct bnx2x_softc *sc, const uint8_t * zbuf, int len)
11595 int data_begin = cut_gzip_prefix(zbuf, len);
11597 PMD_DRV_LOG(DEBUG, "ecore_gunzip %d", len);
11599 if (data_begin <= 0) {
11600 PMD_DRV_LOG(NOTICE, "bad gzip prefix");
11604 memset(&zlib_stream, 0, sizeof(zlib_stream));
11605 zlib_stream.next_in = zbuf + data_begin;
11606 zlib_stream.avail_in = len - data_begin;
11607 zlib_stream.next_out = sc->gz_buf;
11608 zlib_stream.avail_out = FW_BUF_SIZE;
11610 ret = inflateInit2(&zlib_stream, -MAX_WBITS);
11612 PMD_DRV_LOG(NOTICE, "zlib inflateInit2 error");
11616 ret = inflate(&zlib_stream, Z_FINISH);
11617 if ((ret != Z_STREAM_END) && (ret != Z_OK)) {
11618 PMD_DRV_LOG(NOTICE, "zlib inflate error: %d %s", ret,
11622 sc->gz_outlen = zlib_stream.total_out;
11623 if (sc->gz_outlen & 0x3) {
11624 PMD_DRV_LOG(NOTICE, "firmware is not aligned. gz_outlen == %d",
11627 sc->gz_outlen >>= 2;
11629 inflateEnd(&zlib_stream);
11631 if (ret == Z_STREAM_END)
11638 ecore_write_dmae_phys_len(struct bnx2x_softc *sc, phys_addr_t phys_addr,
11639 uint32_t addr, uint32_t len)
11641 bnx2x_write_dmae_phys_len(sc, phys_addr, addr, len);
11645 ecore_storm_memset_struct(struct bnx2x_softc *sc, uint32_t addr, size_t size,
11649 for (i = 0; i < size / 4; i++) {
11650 REG_WR(sc, addr + (i * 4), data[i]);
11654 static const char *get_ext_phy_type(uint32_t ext_phy_type)
11656 uint32_t phy_type_idx = ext_phy_type >> 8;
11657 static const char *types[] =
11658 { "DIRECT", "BNX2X-8071", "BNX2X-8072", "BNX2X-8073",
11659 "BNX2X-8705", "BNX2X-8706", "BNX2X-8726", "BNX2X-8481", "SFX-7101",
11661 "BNX2X-8727-NOC", "BNX2X-84823", "NOT_CONN", "FAILURE"
11664 if (phy_type_idx < 12)
11665 return types[phy_type_idx];
11666 else if (PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN == ext_phy_type)
11672 static const char *get_state(uint32_t state)
11674 uint32_t state_idx = state >> 12;
11675 static const char *states[] = { "CLOSED", "OPENING_WAIT4_LOAD",
11676 "OPENING_WAIT4_PORT", "OPEN", "CLOSING_WAIT4_HALT",
11677 "CLOSING_WAIT4_DELETE", "CLOSING_WAIT4_UNLOAD",
11678 "UNKNOWN", "UNKNOWN", "UNKNOWN", "UNKNOWN", "UNKNOWN",
11679 "UNKNOWN", "DISABLED", "DIAG", "ERROR", "UNDEFINED"
11682 if (state_idx <= 0xF)
11683 return states[state_idx];
11685 return states[0x10];
11688 static const char *get_recovery_state(uint32_t state)
11690 static const char *states[] = { "NONE", "DONE", "INIT",
11691 "WAIT", "FAILED", "NIC_LOADING"
11693 return states[state];
11696 static const char *get_rx_mode(uint32_t mode)
11698 static const char *modes[] = { "NONE", "NORMAL", "ALLMULTI",
11699 "PROMISC", "MAX_MULTICAST", "ERROR"
11703 return modes[mode];
11704 else if (BNX2X_MAX_MULTICAST == mode)
11710 #define BNX2X_INFO_STR_MAX 256
11711 static const char *get_bnx2x_flags(uint32_t flags)
11714 static const char *flag[] = { "ONE_PORT ", "NO_ISCSI ",
11715 "NO_FCOE ", "NO_WOL ", "USING_DAC ", "USING_MSIX ",
11716 "USING_MSI ", "DISABLE_MSI ", "UNKNOWN ", "NO_MCP ",
11717 "SAFC_TX_FLAG ", "MF_FUNC_DIS ", "TX_SWITCHING "
11719 static char flag_str[BNX2X_INFO_STR_MAX];
11720 memset(flag_str, 0, BNX2X_INFO_STR_MAX);
11722 for (i = 0; i < 5; i++)
11723 if (flags & (1 << i)) {
11724 strcat(flag_str, flag[i]);
11728 static char unknown[BNX2X_INFO_STR_MAX];
11729 snprintf(unknown, 32, "Unknown flag mask %x", flags);
11730 strcat(flag_str, unknown);
11736 * Prints useful adapter info.
11738 void bnx2x_print_adapter_info(struct bnx2x_softc *sc)
11741 __rte_unused uint32_t ext_phy_type;
11743 PMD_INIT_FUNC_TRACE();
11744 if (sc->link_vars.phy_flags & PHY_XGXS_FLAG)
11745 ext_phy_type = ELINK_XGXS_EXT_PHY_TYPE(REG_RD(sc,
11750 dev_info.port_hw_config
11751 [0].external_phy_config)));
11753 ext_phy_type = ELINK_SERDES_EXT_PHY_TYPE(REG_RD(sc,
11759 dev_info.port_hw_config
11760 [0].external_phy_config)));
11762 PMD_INIT_LOG(DEBUG, "\n\n===================================\n");
11763 /* Hardware chip info. */
11764 PMD_INIT_LOG(DEBUG, "%12s : %#08x", "ASIC", sc->devinfo.chip_id);
11765 PMD_INIT_LOG(DEBUG, "%12s : %c%d", "Rev", (CHIP_REV(sc) >> 12) + 'A',
11766 (CHIP_METAL(sc) >> 4));
11769 PMD_INIT_LOG(DEBUG, "%12s : %d, ", "Bus PCIe", sc->devinfo.pcie_link_width);
11770 switch (sc->devinfo.pcie_link_speed) {
11772 PMD_INIT_LOG(DEBUG, "%23s", "2.5 Gbps");
11775 PMD_INIT_LOG(DEBUG, "%21s", "5 Gbps");
11778 PMD_INIT_LOG(DEBUG, "%21s", "8 Gbps");
11781 PMD_INIT_LOG(DEBUG, "%33s", "Unknown link speed");
11784 /* Device features. */
11785 PMD_INIT_LOG(DEBUG, "%12s : ", "Flags");
11787 /* Miscellaneous flags. */
11788 if (sc->devinfo.pcie_cap_flags & BNX2X_MSI_CAPABLE_FLAG) {
11789 PMD_INIT_LOG(DEBUG, "%18s", "MSI");
11793 if (sc->devinfo.pcie_cap_flags & BNX2X_MSIX_CAPABLE_FLAG) {
11795 PMD_INIT_LOG(DEBUG, "|");
11796 PMD_INIT_LOG(DEBUG, "%20s", "MSI-X");
11801 PMD_INIT_LOG(DEBUG, "%12s : ", "Queues");
11802 switch (sc->sp->rss_rdata.rss_mode) {
11803 case ETH_RSS_MODE_DISABLED:
11804 PMD_INIT_LOG(DEBUG, "%19s", "None");
11806 case ETH_RSS_MODE_REGULAR:
11807 PMD_INIT_LOG(DEBUG, "%18s : %d", "RSS", sc->num_queues);
11810 PMD_INIT_LOG(DEBUG, "%22s", "Unknown");
11815 /* RTE and Driver versions */
11816 PMD_INIT_LOG(DEBUG, "%12s : %s", "DPDK",
11818 PMD_INIT_LOG(DEBUG, "%12s : %s", "Driver",
11819 bnx2x_pmd_version());
11821 /* Firmware versions and device features. */
11822 PMD_INIT_LOG(DEBUG, "%12s : %d.%d.%d",
11824 BNX2X_5710_FW_MAJOR_VERSION,
11825 BNX2X_5710_FW_MINOR_VERSION,
11826 BNX2X_5710_FW_REVISION_VERSION);
11827 PMD_INIT_LOG(DEBUG, "%12s : %s",
11828 "Bootcode", sc->devinfo.bc_ver_str);
11830 PMD_INIT_LOG(DEBUG, "\n\n===================================\n");
11831 PMD_INIT_LOG(DEBUG, "%12s : %u", "Bnx2x Func", sc->pcie_func);
11832 PMD_INIT_LOG(DEBUG, "%12s : %s", "Bnx2x Flags", get_bnx2x_flags(sc->flags));
11833 PMD_INIT_LOG(DEBUG, "%12s : %s", "DMAE Is",
11834 (sc->dmae_ready ? "Ready" : "Not Ready"));
11835 PMD_INIT_LOG(DEBUG, "%12s : %s", "OVLAN", (OVLAN(sc) ? "YES" : "NO"));
11836 PMD_INIT_LOG(DEBUG, "%12s : %s", "MF", (IS_MF(sc) ? "YES" : "NO"));
11837 PMD_INIT_LOG(DEBUG, "%12s : %u", "MTU", sc->mtu);
11838 PMD_INIT_LOG(DEBUG, "%12s : %s", "PHY Type", get_ext_phy_type(ext_phy_type));
11839 PMD_INIT_LOG(DEBUG, "%12s : %x:%x:%x:%x:%x:%x", "MAC Addr",
11840 sc->link_params.mac_addr[0],
11841 sc->link_params.mac_addr[1],
11842 sc->link_params.mac_addr[2],
11843 sc->link_params.mac_addr[3],
11844 sc->link_params.mac_addr[4],
11845 sc->link_params.mac_addr[5]);
11846 PMD_INIT_LOG(DEBUG, "%12s : %s", "RX Mode", get_rx_mode(sc->rx_mode));
11847 PMD_INIT_LOG(DEBUG, "%12s : %s", "State", get_state(sc->state));
11848 if (sc->recovery_state)
11849 PMD_INIT_LOG(DEBUG, "%12s : %s", "Recovery",
11850 get_recovery_state(sc->recovery_state));
11851 PMD_INIT_LOG(DEBUG, "%12s : CQ = %lx, EQ = %lx", "SPQ Left",
11852 sc->cq_spq_left, sc->eq_spq_left);
11853 PMD_INIT_LOG(DEBUG, "%12s : %x", "Switch", sc->link_params.switch_cfg);
11854 PMD_INIT_LOG(DEBUG, "\n\n===================================\n");