drivers/net/bnx2x/bnx2x.c

   1 /*-
   2  * Copyright (c) 2007-2013 Broadcom Corporation.
   3  *
   4  * Eric Davis        <edavis@broadcom.com>
   5  * David Christensen <davidch@broadcom.com>
   6  * Gary Zambrano     <zambrano@broadcom.com>
   7  *
   8  * Copyright (c) 2013-2015 Brocade Communications Systems, Inc.
   9  * Copyright (c) 2015-2018 Cavium Inc.
  10  * All rights reserved.
  11  * www.cavium.com
  12  *
  13  * See LICENSE.bnx2x_pmd for copyright and licensing details.
  14  */
  15
  16 #define BNX2X_DRIVER_VERSION "1.78.18"
  17
  18 #include "bnx2x.h"
  19 #include "bnx2x_vfpf.h"
  20 #include "ecore_sp.h"
  21 #include "ecore_init.h"
  22 #include "ecore_init_ops.h"
  23
  24 #include "rte_version.h"
  25
  26 #include <sys/types.h>
  27 #include <sys/stat.h>
  28 #include <fcntl.h>
  29 #include <zlib.h>
  30
  31 #define BNX2X_PMD_VER_PREFIX "BNX2X PMD"
  32 #define BNX2X_PMD_VERSION_MAJOR 1
  33 #define BNX2X_PMD_VERSION_MINOR 0
  34 #define BNX2X_PMD_VERSION_REVISION 5
  35 #define BNX2X_PMD_VERSION_PATCH 1
  36
  37 static inline const char *
  38 bnx2x_pmd_version(void)
  39 {
  40         static char version[32];
  41
  42         snprintf(version, sizeof(version), "%s %s_%d.%d.%d.%d",
  43                         BNX2X_PMD_VER_PREFIX,
  44                         BNX2X_DRIVER_VERSION,
  45                         BNX2X_PMD_VERSION_MAJOR,
  46                         BNX2X_PMD_VERSION_MINOR,
  47                         BNX2X_PMD_VERSION_REVISION,
  48                         BNX2X_PMD_VERSION_PATCH);
  49
  50         return version;
  51 }
  52
  53 static z_stream zlib_stream;
  54
  55 #define EVL_VLID_MASK 0x0FFF
  56
  57 #define BNX2X_DEF_SB_ATT_IDX 0x0001
  58 #define BNX2X_DEF_SB_IDX     0x0002
  59
  60 /*
  61  * FLR Support - bnx2x_pf_flr_clnup() is called during nic_load in the per
  62  * function HW initialization.
  63  */
  64 #define FLR_WAIT_USEC     10000 /* 10 msecs */
  65 #define FLR_WAIT_INTERVAL 50    /* usecs */
  66 #define FLR_POLL_CNT      (FLR_WAIT_USEC / FLR_WAIT_INTERVAL)   /* 200 */
  67
  68 struct pbf_pN_buf_regs {
  69         int pN;
  70         uint32_t init_crd;
  71         uint32_t crd;
  72         uint32_t crd_freed;
  73 };
  74
  75 struct pbf_pN_cmd_regs {
  76         int pN;
  77         uint32_t lines_occup;
  78         uint32_t lines_freed;
  79 };
  80
  81 /* resources needed for unloading a previously loaded device */
  82
  83 #define BNX2X_PREV_WAIT_NEEDED 1
  84 rte_spinlock_t bnx2x_prev_mtx;
  85 struct bnx2x_prev_list_node {
  86         LIST_ENTRY(bnx2x_prev_list_node) node;
  87         uint8_t bus;
  88         uint8_t slot;
  89         uint8_t path;
  90         uint8_t aer;
  91         uint8_t undi;
  92 };
  93
  94 static LIST_HEAD(, bnx2x_prev_list_node) bnx2x_prev_list
  95         = LIST_HEAD_INITIALIZER(bnx2x_prev_list);
  96
  97 static int load_count[2][3] = { { 0 } };
  98         /* per-path: 0-common, 1-port0, 2-port1 */
  99
 100 static void bnx2x_cmng_fns_init(struct bnx2x_softc *sc, uint8_t read_cfg,
 101                                 uint8_t cmng_type);
 102 static int bnx2x_get_cmng_fns_mode(struct bnx2x_softc *sc);
 103 static void storm_memset_cmng(struct bnx2x_softc *sc, struct cmng_init *cmng,
 104                               uint8_t port);
 105 static void bnx2x_set_reset_global(struct bnx2x_softc *sc);
 106 static void bnx2x_set_reset_in_progress(struct bnx2x_softc *sc);
 107 static uint8_t bnx2x_reset_is_done(struct bnx2x_softc *sc, int engine);
 108 static uint8_t bnx2x_clear_pf_load(struct bnx2x_softc *sc);
 109 static uint8_t bnx2x_chk_parity_attn(struct bnx2x_softc *sc, uint8_t * global,
 110                                      uint8_t print);
 111 static void bnx2x_int_disable(struct bnx2x_softc *sc);
 112 static int bnx2x_release_leader_lock(struct bnx2x_softc *sc);
 113 static void bnx2x_pf_disable(struct bnx2x_softc *sc);
 114 static void bnx2x_update_rx_prod(struct bnx2x_softc *sc,
 115                                  struct bnx2x_fastpath *fp,
 116                                  uint16_t rx_bd_prod, uint16_t rx_cq_prod);
 117 static void bnx2x_link_report(struct bnx2x_softc *sc);
 118 void bnx2x_link_status_update(struct bnx2x_softc *sc);
 119 static int bnx2x_alloc_mem(struct bnx2x_softc *sc);
 120 static void bnx2x_free_mem(struct bnx2x_softc *sc);
 121 static int bnx2x_alloc_fw_stats_mem(struct bnx2x_softc *sc);
 122 static void bnx2x_free_fw_stats_mem(struct bnx2x_softc *sc);
 123 static __rte_noinline
 124 int bnx2x_nic_load(struct bnx2x_softc *sc);
 125
 126 static int bnx2x_handle_sp_tq(struct bnx2x_softc *sc);
 127 static void bnx2x_handle_fp_tq(struct bnx2x_fastpath *fp, int scan_fp);
 128 static void bnx2x_periodic_stop(struct bnx2x_softc *sc);
 129 static void bnx2x_ack_sb(struct bnx2x_softc *sc, uint8_t igu_sb_id,
 130                          uint8_t storm, uint16_t index, uint8_t op,
 131                          uint8_t update);
 132
 133 int bnx2x_test_bit(int nr, volatile unsigned long *addr)
 134 {
 135         int res;
 136
 137         mb();
 138         res = ((*addr) & (1UL << nr)) != 0;
 139         mb();
 140         return res;
 141 }
 142
 143 void bnx2x_set_bit(unsigned int nr, volatile unsigned long *addr)
 144 {
 145         __sync_fetch_and_or(addr, (1UL << nr));
 146 }
 147
 148 void bnx2x_clear_bit(int nr, volatile unsigned long *addr)
 149 {
 150         __sync_fetch_and_and(addr, ~(1UL << nr));
 151 }
 152
 153 int bnx2x_test_and_clear_bit(int nr, volatile unsigned long *addr)
 154 {
 155         unsigned long mask = (1UL << nr);
 156         return __sync_fetch_and_and(addr, ~mask) & mask;
 157 }
 158
 159 int bnx2x_cmpxchg(volatile int *addr, int old, int new)
 160 {
 161         return __sync_val_compare_and_swap(addr, old, new);
 162 }
 163
 164 int
 165 bnx2x_dma_alloc(struct bnx2x_softc *sc, size_t size, struct bnx2x_dma *dma,
 166               const char *msg, uint32_t align)
 167 {
 168         char mz_name[RTE_MEMZONE_NAMESIZE];
 169         const struct rte_memzone *z;
 170
 171         dma->sc = sc;
 172         if (IS_PF(sc))
 173                 snprintf(mz_name, sizeof(mz_name), "bnx2x%d_%s_%" PRIx64, SC_ABS_FUNC(sc), msg,
 174                         rte_get_timer_cycles());
 175         else
 176                 snprintf(mz_name, sizeof(mz_name), "bnx2x%d_%s_%" PRIx64, sc->pcie_device, msg,
 177                         rte_get_timer_cycles());
 178
 179         /* Caller must take care that strlen(mz_name) < RTE_MEMZONE_NAMESIZE */
 180         z = rte_memzone_reserve_aligned(mz_name, (uint64_t)size,
 181                                         SOCKET_ID_ANY,
 182                                         RTE_MEMZONE_IOVA_CONTIG, align);
 183         if (z == NULL) {
 184                 PMD_DRV_LOG(ERR, "DMA alloc failed for %s", msg);
 185                 return -ENOMEM;
 186         }
 187         dma->paddr = (uint64_t) z->iova;
 188         dma->vaddr = z->addr;
 189
 190         PMD_DRV_LOG(DEBUG, "%s: virt=%p phys=%" PRIx64, msg, dma->vaddr, dma->paddr);
 191
 192         return 0;
 193 }
 194
 195 static int bnx2x_acquire_hw_lock(struct bnx2x_softc *sc, uint32_t resource)
 196 {
 197         uint32_t lock_status;
 198         uint32_t resource_bit = (1 << resource);
 199         int func = SC_FUNC(sc);
 200         uint32_t hw_lock_control_reg;
 201         int cnt;
 202
 203         PMD_INIT_FUNC_TRACE();
 204
 205         /* validate the resource is within range */
 206         if (resource > HW_LOCK_MAX_RESOURCE_VALUE) {
 207                 PMD_DRV_LOG(NOTICE,
 208                             "resource 0x%x > HW_LOCK_MAX_RESOURCE_VALUE",
 209                             resource);
 210                 return -1;
 211         }
 212
 213         if (func <= 5) {
 214                 hw_lock_control_reg = (MISC_REG_DRIVER_CONTROL_1 + (func * 8));
 215         } else {
 216                 hw_lock_control_reg =
 217                     (MISC_REG_DRIVER_CONTROL_7 + ((func - 6) * 8));
 218         }
 219
 220         /* validate the resource is not already taken */
 221         lock_status = REG_RD(sc, hw_lock_control_reg);
 222         if (lock_status & resource_bit) {
 223                 PMD_DRV_LOG(NOTICE,
 224                             "resource in use (status 0x%x bit 0x%x)",
 225                             lock_status, resource_bit);
 226                 return -1;
 227         }
 228
 229         /* try every 5ms for 5 seconds */
 230         for (cnt = 0; cnt < 1000; cnt++) {
 231                 REG_WR(sc, (hw_lock_control_reg + 4), resource_bit);
 232                 lock_status = REG_RD(sc, hw_lock_control_reg);
 233                 if (lock_status & resource_bit) {
 234                         return 0;
 235                 }
 236                 DELAY(5000);
 237         }
 238
 239         PMD_DRV_LOG(NOTICE, "Resource lock timeout!");
 240         return -1;
 241 }
 242
 243 static int bnx2x_release_hw_lock(struct bnx2x_softc *sc, uint32_t resource)
 244 {
 245         uint32_t lock_status;
 246         uint32_t resource_bit = (1 << resource);
 247         int func = SC_FUNC(sc);
 248         uint32_t hw_lock_control_reg;
 249
 250         PMD_INIT_FUNC_TRACE();
 251
 252         /* validate the resource is within range */
 253         if (resource > HW_LOCK_MAX_RESOURCE_VALUE) {
 254                 PMD_DRV_LOG(NOTICE,
 255                             "resource 0x%x > HW_LOCK_MAX_RESOURCE_VALUE",
 256                             resource);
 257                 return -1;
 258         }
 259
 260         if (func <= 5) {
 261                 hw_lock_control_reg = (MISC_REG_DRIVER_CONTROL_1 + (func * 8));
 262         } else {
 263                 hw_lock_control_reg =
 264                     (MISC_REG_DRIVER_CONTROL_7 + ((func - 6) * 8));
 265         }
 266
 267         /* validate the resource is currently taken */
 268         lock_status = REG_RD(sc, hw_lock_control_reg);
 269         if (!(lock_status & resource_bit)) {
 270                 PMD_DRV_LOG(NOTICE,
 271                             "resource not in use (status 0x%x bit 0x%x)",
 272                             lock_status, resource_bit);
 273                 return -1;
 274         }
 275
 276         REG_WR(sc, hw_lock_control_reg, resource_bit);
 277         return 0;
 278 }
 279
 280 /* copy command into DMAE command memory and set DMAE command Go */
 281 void bnx2x_post_dmae(struct bnx2x_softc *sc, struct dmae_command *dmae, int idx)
 282 {
 283         uint32_t cmd_offset;
 284         uint32_t i;
 285
 286         cmd_offset = (DMAE_REG_CMD_MEM + (sizeof(struct dmae_command) * idx));
 287         for (i = 0; i < ((sizeof(struct dmae_command) / 4)); i++) {
 288                 REG_WR(sc, (cmd_offset + (i * 4)), *(((uint32_t *) dmae) + i));
 289         }
 290
 291         REG_WR(sc, dmae_reg_go_c[idx], 1);
 292 }
 293
 294 uint32_t bnx2x_dmae_opcode_add_comp(uint32_t opcode, uint8_t comp_type)
 295 {
 296         return opcode | ((comp_type << DMAE_COMMAND_C_DST_SHIFT) |
 297                           DMAE_COMMAND_C_TYPE_ENABLE);
 298 }
 299
 300 uint32_t bnx2x_dmae_opcode_clr_src_reset(uint32_t opcode)
 301 {
 302         return opcode & ~DMAE_COMMAND_SRC_RESET;
 303 }
 304
 305 uint32_t
 306 bnx2x_dmae_opcode(struct bnx2x_softc * sc, uint8_t src_type, uint8_t dst_type,
 307                 uint8_t with_comp, uint8_t comp_type)
 308 {
 309         uint32_t opcode = 0;
 310
 311         opcode |= ((src_type << DMAE_COMMAND_SRC_SHIFT) |
 312                    (dst_type << DMAE_COMMAND_DST_SHIFT));
 313
 314         opcode |= (DMAE_COMMAND_SRC_RESET | DMAE_COMMAND_DST_RESET);
 315
 316         opcode |= (SC_PORT(sc) ? DMAE_CMD_PORT_1 : DMAE_CMD_PORT_0);
 317
 318         opcode |= ((SC_VN(sc) << DMAE_COMMAND_E1HVN_SHIFT) |
 319                    (SC_VN(sc) << DMAE_COMMAND_DST_VN_SHIFT));
 320
 321         opcode |= (DMAE_COM_SET_ERR << DMAE_COMMAND_ERR_POLICY_SHIFT);
 322
 323 #ifdef __BIG_ENDIAN
 324         opcode |= DMAE_CMD_ENDIANITY_B_DW_SWAP;
 325 #else
 326         opcode |= DMAE_CMD_ENDIANITY_DW_SWAP;
 327 #endif
 328
 329         if (with_comp) {
 330                 opcode = bnx2x_dmae_opcode_add_comp(opcode, comp_type);
 331         }
 332
 333         return opcode;
 334 }
 335
 336 static void
 337 bnx2x_prep_dmae_with_comp(struct bnx2x_softc *sc, struct dmae_command *dmae,
 338                         uint8_t src_type, uint8_t dst_type)
 339 {
 340         memset(dmae, 0, sizeof(struct dmae_command));
 341
 342         /* set the opcode */
 343         dmae->opcode = bnx2x_dmae_opcode(sc, src_type, dst_type,
 344                                        TRUE, DMAE_COMP_PCI);
 345
 346         /* fill in the completion parameters */
 347         dmae->comp_addr_lo = U64_LO(BNX2X_SP_MAPPING(sc, wb_comp));
 348         dmae->comp_addr_hi = U64_HI(BNX2X_SP_MAPPING(sc, wb_comp));
 349         dmae->comp_val = DMAE_COMP_VAL;
 350 }
 351
 352 /* issue a DMAE command over the init channel and wait for completion */
 353 static int
 354 bnx2x_issue_dmae_with_comp(struct bnx2x_softc *sc, struct dmae_command *dmae)
 355 {
 356         uint32_t *wb_comp = BNX2X_SP(sc, wb_comp);
 357         int timeout = CHIP_REV_IS_SLOW(sc) ? 400000 : 4000;
 358
 359         /* reset completion */
 360         *wb_comp = 0;
 361
 362         /* post the command on the channel used for initializations */
 363         bnx2x_post_dmae(sc, dmae, INIT_DMAE_C(sc));
 364
 365         /* wait for completion */
 366         DELAY(500);
 367
 368         while ((*wb_comp & ~DMAE_PCI_ERR_FLAG) != DMAE_COMP_VAL) {
 369                 if (!timeout ||
 370                     (sc->recovery_state != BNX2X_RECOVERY_DONE &&
 371                      sc->recovery_state != BNX2X_RECOVERY_NIC_LOADING)) {
 372                         PMD_DRV_LOG(INFO, "DMAE timeout!");
 373                         return DMAE_TIMEOUT;
 374                 }
 375
 376                 timeout--;
 377                 DELAY(50);
 378         }
 379
 380         if (*wb_comp & DMAE_PCI_ERR_FLAG) {
 381                 PMD_DRV_LOG(INFO, "DMAE PCI error!");
 382                 return DMAE_PCI_ERROR;
 383         }
 384
 385         return 0;
 386 }
 387
 388 void bnx2x_read_dmae(struct bnx2x_softc *sc, uint32_t src_addr, uint32_t len32)
 389 {
 390         struct dmae_command dmae;
 391         uint32_t *data;
 392         uint32_t i;
 393         int rc;
 394
 395         if (!sc->dmae_ready) {
 396                 data = BNX2X_SP(sc, wb_data[0]);
 397
 398                 for (i = 0; i < len32; i++) {
 399                         data[i] = REG_RD(sc, (src_addr + (i * 4)));
 400                 }
 401
 402                 return;
 403         }
 404
 405         /* set opcode and fixed command fields */
 406         bnx2x_prep_dmae_with_comp(sc, &dmae, DMAE_SRC_GRC, DMAE_DST_PCI);
 407
 408         /* fill in addresses and len */
 409         dmae.src_addr_lo = (src_addr >> 2);     /* GRC addr has dword resolution */
 410         dmae.src_addr_hi = 0;
 411         dmae.dst_addr_lo = U64_LO(BNX2X_SP_MAPPING(sc, wb_data));
 412         dmae.dst_addr_hi = U64_HI(BNX2X_SP_MAPPING(sc, wb_data));
 413         dmae.len = len32;
 414
 415         /* issue the command and wait for completion */
 416         if ((rc = bnx2x_issue_dmae_with_comp(sc, &dmae)) != 0) {
 417                 rte_panic("DMAE failed (%d)", rc);
 418         };
 419 }
 420
 421 void
 422 bnx2x_write_dmae(struct bnx2x_softc *sc, rte_iova_t dma_addr, uint32_t dst_addr,
 423                uint32_t len32)
 424 {
 425         struct dmae_command dmae;
 426         int rc;
 427
 428         if (!sc->dmae_ready) {
 429                 ecore_init_str_wr(sc, dst_addr, BNX2X_SP(sc, wb_data[0]), len32);
 430                 return;
 431         }
 432
 433         /* set opcode and fixed command fields */
 434         bnx2x_prep_dmae_with_comp(sc, &dmae, DMAE_SRC_PCI, DMAE_DST_GRC);
 435
 436         /* fill in addresses and len */
 437         dmae.src_addr_lo = U64_LO(dma_addr);
 438         dmae.src_addr_hi = U64_HI(dma_addr);
 439         dmae.dst_addr_lo = (dst_addr >> 2);     /* GRC addr has dword resolution */
 440         dmae.dst_addr_hi = 0;
 441         dmae.len = len32;
 442
 443         /* issue the command and wait for completion */
 444         if ((rc = bnx2x_issue_dmae_with_comp(sc, &dmae)) != 0) {
 445                 rte_panic("DMAE failed (%d)", rc);
 446         }
 447 }
 448
 449 static void
 450 bnx2x_write_dmae_phys_len(struct bnx2x_softc *sc, rte_iova_t phys_addr,
 451                         uint32_t addr, uint32_t len)
 452 {
 453         uint32_t dmae_wr_max = DMAE_LEN32_WR_MAX(sc);
 454         uint32_t offset = 0;
 455
 456         while (len > dmae_wr_max) {
 457                 bnx2x_write_dmae(sc, (phys_addr + offset),      /* src DMA address */
 458                                (addr + offset), /* dst GRC address */
 459                                dmae_wr_max);
 460                 offset += (dmae_wr_max * 4);
 461                 len -= dmae_wr_max;
 462         }
 463
 464         bnx2x_write_dmae(sc, (phys_addr + offset),      /* src DMA address */
 465                        (addr + offset), /* dst GRC address */
 466                        len);
 467 }
 468
 469 void
 470 bnx2x_set_ctx_validation(struct bnx2x_softc *sc, struct eth_context *cxt,
 471                        uint32_t cid)
 472 {
 473         /* ustorm cxt validation */
 474         cxt->ustorm_ag_context.cdu_usage =
 475             CDU_RSRVD_VALUE_TYPE_A(HW_CID(sc, cid),
 476                                    CDU_REGION_NUMBER_UCM_AG,
 477                                    ETH_CONNECTION_TYPE);
 478         /* xcontext validation */
 479         cxt->xstorm_ag_context.cdu_reserved =
 480             CDU_RSRVD_VALUE_TYPE_A(HW_CID(sc, cid),
 481                                    CDU_REGION_NUMBER_XCM_AG,
 482                                    ETH_CONNECTION_TYPE);
 483 }
 484
 485 static void
 486 bnx2x_storm_memset_hc_timeout(struct bnx2x_softc *sc, uint8_t fw_sb_id,
 487                             uint8_t sb_index, uint8_t ticks)
 488 {
 489         uint32_t addr =
 490             (BAR_CSTRORM_INTMEM +
 491              CSTORM_STATUS_BLOCK_DATA_TIMEOUT_OFFSET(fw_sb_id, sb_index));
 492
 493         REG_WR8(sc, addr, ticks);
 494 }
 495
 496 static void
 497 bnx2x_storm_memset_hc_disable(struct bnx2x_softc *sc, uint16_t fw_sb_id,
 498                             uint8_t sb_index, uint8_t disable)
 499 {
 500         uint32_t enable_flag =
 501             (disable) ? 0 : (1 << HC_INDEX_DATA_HC_ENABLED_SHIFT);
 502         uint32_t addr =
 503             (BAR_CSTRORM_INTMEM +
 504              CSTORM_STATUS_BLOCK_DATA_FLAGS_OFFSET(fw_sb_id, sb_index));
 505         uint8_t flags;
 506
 507         /* clear and set */
 508         flags = REG_RD8(sc, addr);
 509         flags &= ~HC_INDEX_DATA_HC_ENABLED;
 510         flags |= enable_flag;
 511         REG_WR8(sc, addr, flags);
 512 }
 513
 514 void
 515 bnx2x_update_coalesce_sb_index(struct bnx2x_softc *sc, uint8_t fw_sb_id,
 516                              uint8_t sb_index, uint8_t disable, uint16_t usec)
 517 {
 518         uint8_t ticks = (usec / 4);
 519
 520         bnx2x_storm_memset_hc_timeout(sc, fw_sb_id, sb_index, ticks);
 521
 522         disable = (disable) ? 1 : ((usec) ? 0 : 1);
 523         bnx2x_storm_memset_hc_disable(sc, fw_sb_id, sb_index, disable);
 524 }
 525
 526 uint32_t elink_cb_reg_read(struct bnx2x_softc *sc, uint32_t reg_addr)
 527 {
 528         return REG_RD(sc, reg_addr);
 529 }
 530
 531 void elink_cb_reg_write(struct bnx2x_softc *sc, uint32_t reg_addr, uint32_t val)
 532 {
 533         REG_WR(sc, reg_addr, val);
 534 }
 535
 536 void
 537 elink_cb_event_log(__rte_unused struct bnx2x_softc *sc,
 538                    __rte_unused const elink_log_id_t elink_log_id, ...)
 539 {
 540         PMD_DRV_LOG(DEBUG, "ELINK EVENT LOG (%d)", elink_log_id);
 541 }
 542
 543 static int bnx2x_set_spio(struct bnx2x_softc *sc, int spio, uint32_t mode)
 544 {
 545         uint32_t spio_reg;
 546
 547         /* Only 2 SPIOs are configurable */
 548         if ((spio != MISC_SPIO_SPIO4) && (spio != MISC_SPIO_SPIO5)) {
 549                 PMD_DRV_LOG(NOTICE, "Invalid SPIO 0x%x", spio);
 550                 return -1;
 551         }
 552
 553         bnx2x_acquire_hw_lock(sc, HW_LOCK_RESOURCE_SPIO);
 554
 555         /* read SPIO and mask except the float bits */
 556         spio_reg = (REG_RD(sc, MISC_REG_SPIO) & MISC_SPIO_FLOAT);
 557
 558         switch (mode) {
 559         case MISC_SPIO_OUTPUT_LOW:
 560                 /* clear FLOAT and set CLR */
 561                 spio_reg &= ~(spio << MISC_SPIO_FLOAT_POS);
 562                 spio_reg |= (spio << MISC_SPIO_CLR_POS);
 563                 break;
 564
 565         case MISC_SPIO_OUTPUT_HIGH:
 566                 /* clear FLOAT and set SET */
 567                 spio_reg &= ~(spio << MISC_SPIO_FLOAT_POS);
 568                 spio_reg |= (spio << MISC_SPIO_SET_POS);
 569                 break;
 570
 571         case MISC_SPIO_INPUT_HI_Z:
 572                 /* set FLOAT */
 573                 spio_reg |= (spio << MISC_SPIO_FLOAT_POS);
 574                 break;
 575
 576         default:
 577                 break;
 578         }
 579
 580         REG_WR(sc, MISC_REG_SPIO, spio_reg);
 581         bnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_SPIO);
 582
 583         return 0;
 584 }
 585
 586 static int bnx2x_gpio_read(struct bnx2x_softc *sc, int gpio_num, uint8_t port)
 587 {
 588         /* The GPIO should be swapped if swap register is set and active */
 589         int gpio_port = ((REG_RD(sc, NIG_REG_PORT_SWAP) &&
 590                           REG_RD(sc, NIG_REG_STRAP_OVERRIDE)) ^ port);
 591         int gpio_shift = gpio_num;
 592         if (gpio_port)
 593                 gpio_shift += MISC_REGISTERS_GPIO_PORT_SHIFT;
 594
 595         uint32_t gpio_mask = (1 << gpio_shift);
 596         uint32_t gpio_reg;
 597
 598         if (gpio_num > MISC_REGISTERS_GPIO_3) {
 599                 PMD_DRV_LOG(NOTICE, "Invalid GPIO %d", gpio_num);
 600                 return -1;
 601         }
 602
 603         /* read GPIO value */
 604         gpio_reg = REG_RD(sc, MISC_REG_GPIO);
 605
 606         /* get the requested pin value */
 607         return ((gpio_reg & gpio_mask) == gpio_mask) ? 1 : 0;
 608 }
 609
 610 static int
 611 bnx2x_gpio_write(struct bnx2x_softc *sc, int gpio_num, uint32_t mode, uint8_t port)
 612 {
 613         /* The GPIO should be swapped if swap register is set and active */
 614         int gpio_port = ((REG_RD(sc, NIG_REG_PORT_SWAP) &&
 615                           REG_RD(sc, NIG_REG_STRAP_OVERRIDE)) ^ port);
 616         int gpio_shift = gpio_num;
 617         if (gpio_port)
 618                 gpio_shift += MISC_REGISTERS_GPIO_PORT_SHIFT;
 619
 620         uint32_t gpio_mask = (1 << gpio_shift);
 621         uint32_t gpio_reg;
 622
 623         if (gpio_num > MISC_REGISTERS_GPIO_3) {
 624                 PMD_DRV_LOG(NOTICE, "Invalid GPIO %d", gpio_num);
 625                 return -1;
 626         }
 627
 628         bnx2x_acquire_hw_lock(sc, HW_LOCK_RESOURCE_GPIO);
 629
 630         /* read GPIO and mask except the float bits */
 631         gpio_reg = (REG_RD(sc, MISC_REG_GPIO) & MISC_REGISTERS_GPIO_FLOAT);
 632
 633         switch (mode) {
 634         case MISC_REGISTERS_GPIO_OUTPUT_LOW:
 635                 /* clear FLOAT and set CLR */
 636                 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS);
 637                 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_CLR_POS);
 638                 break;
 639
 640         case MISC_REGISTERS_GPIO_OUTPUT_HIGH:
 641                 /* clear FLOAT and set SET */
 642                 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS);
 643                 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_SET_POS);
 644                 break;
 645
 646         case MISC_REGISTERS_GPIO_INPUT_HI_Z:
 647                 /* set FLOAT */
 648                 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS);
 649                 break;
 650
 651         default:
 652                 break;
 653         }
 654
 655         REG_WR(sc, MISC_REG_GPIO, gpio_reg);
 656         bnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_GPIO);
 657
 658         return 0;
 659 }
 660
 661 static int
 662 bnx2x_gpio_mult_write(struct bnx2x_softc *sc, uint8_t pins, uint32_t mode)
 663 {
 664         uint32_t gpio_reg;
 665
 666         /* any port swapping should be handled by caller */
 667
 668         bnx2x_acquire_hw_lock(sc, HW_LOCK_RESOURCE_GPIO);
 669
 670         /* read GPIO and mask except the float bits */
 671         gpio_reg = REG_RD(sc, MISC_REG_GPIO);
 672         gpio_reg &= ~(pins << MISC_REGISTERS_GPIO_FLOAT_POS);
 673         gpio_reg &= ~(pins << MISC_REGISTERS_GPIO_CLR_POS);
 674         gpio_reg &= ~(pins << MISC_REGISTERS_GPIO_SET_POS);
 675
 676         switch (mode) {
 677         case MISC_REGISTERS_GPIO_OUTPUT_LOW:
 678                 /* set CLR */
 679                 gpio_reg |= (pins << MISC_REGISTERS_GPIO_CLR_POS);
 680                 break;
 681
 682         case MISC_REGISTERS_GPIO_OUTPUT_HIGH:
 683                 /* set SET */
 684                 gpio_reg |= (pins << MISC_REGISTERS_GPIO_SET_POS);
 685                 break;
 686
 687         case MISC_REGISTERS_GPIO_INPUT_HI_Z:
 688                 /* set FLOAT */
 689                 gpio_reg |= (pins << MISC_REGISTERS_GPIO_FLOAT_POS);
 690                 break;
 691
 692         default:
 693                 PMD_DRV_LOG(NOTICE, "Invalid GPIO mode assignment %d", mode);
 694                 bnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_GPIO);
 695                 return -1;
 696         }
 697
 698         REG_WR(sc, MISC_REG_GPIO, gpio_reg);
 699         bnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_GPIO);
 700
 701         return 0;
 702 }
 703
 704 static int
 705 bnx2x_gpio_int_write(struct bnx2x_softc *sc, int gpio_num, uint32_t mode,
 706                    uint8_t port)
 707 {
 708         /* The GPIO should be swapped if swap register is set and active */
 709         int gpio_port = ((REG_RD(sc, NIG_REG_PORT_SWAP) &&
 710                           REG_RD(sc, NIG_REG_STRAP_OVERRIDE)) ^ port);
 711         int gpio_shift = gpio_num;
 712         if (gpio_port)
 713                 gpio_shift += MISC_REGISTERS_GPIO_PORT_SHIFT;
 714
 715         uint32_t gpio_mask = (1 << gpio_shift);
 716         uint32_t gpio_reg;
 717
 718         if (gpio_num > MISC_REGISTERS_GPIO_3) {
 719                 PMD_DRV_LOG(NOTICE, "Invalid GPIO %d", gpio_num);
 720                 return -1;
 721         }
 722
 723         bnx2x_acquire_hw_lock(sc, HW_LOCK_RESOURCE_GPIO);
 724
 725         /* read GPIO int */
 726         gpio_reg = REG_RD(sc, MISC_REG_GPIO_INT);
 727
 728         switch (mode) {
 729         case MISC_REGISTERS_GPIO_INT_OUTPUT_CLR:
 730                 /* clear SET and set CLR */
 731                 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_INT_SET_POS);
 732                 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_INT_CLR_POS);
 733                 break;
 734
 735         case MISC_REGISTERS_GPIO_INT_OUTPUT_SET:
 736                 /* clear CLR and set SET */
 737                 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_INT_CLR_POS);
 738                 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_INT_SET_POS);
 739                 break;
 740
 741         default:
 742                 break;
 743         }
 744
 745         REG_WR(sc, MISC_REG_GPIO_INT, gpio_reg);
 746         bnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_GPIO);
 747
 748         return 0;
 749 }
 750
 751 uint32_t
 752 elink_cb_gpio_read(struct bnx2x_softc * sc, uint16_t gpio_num, uint8_t port)
 753 {
 754         return bnx2x_gpio_read(sc, gpio_num, port);
 755 }
 756
 757 uint8_t elink_cb_gpio_write(struct bnx2x_softc * sc, uint16_t gpio_num, uint8_t mode,   /* 0=low 1=high */
 758                             uint8_t port)
 759 {
 760         return bnx2x_gpio_write(sc, gpio_num, mode, port);
 761 }
 762
 763 uint8_t
 764 elink_cb_gpio_mult_write(struct bnx2x_softc * sc, uint8_t pins,
 765                          uint8_t mode /* 0=low 1=high */ )
 766 {
 767         return bnx2x_gpio_mult_write(sc, pins, mode);
 768 }
 769
 770 uint8_t elink_cb_gpio_int_write(struct bnx2x_softc * sc, uint16_t gpio_num, uint8_t mode,       /* 0=low 1=high */
 771                                 uint8_t port)
 772 {
 773         return bnx2x_gpio_int_write(sc, gpio_num, mode, port);
 774 }
 775
 776 void elink_cb_notify_link_changed(struct bnx2x_softc *sc)
 777 {
 778         REG_WR(sc, (MISC_REG_AEU_GENERAL_ATTN_12 +
 779                     (SC_FUNC(sc) * sizeof(uint32_t))), 1);
 780 }
 781
 782 /* send the MCP a request, block until there is a reply */
 783 uint32_t
 784 elink_cb_fw_command(struct bnx2x_softc *sc, uint32_t command, uint32_t param)
 785 {
 786         int mb_idx = SC_FW_MB_IDX(sc);
 787         uint32_t seq;
 788         uint32_t rc = 0;
 789         uint32_t cnt = 1;
 790         uint8_t delay = CHIP_REV_IS_SLOW(sc) ? 100 : 10;
 791
 792         seq = ++sc->fw_seq;
 793         SHMEM_WR(sc, func_mb[mb_idx].drv_mb_param, param);
 794         SHMEM_WR(sc, func_mb[mb_idx].drv_mb_header, (command | seq));
 795
 796         PMD_DRV_LOG(DEBUG,
 797                     "wrote command 0x%08x to FW MB param 0x%08x",
 798                     (command | seq), param);
 799
 800         /* Let the FW do it's magic. GIve it up to 5 seconds... */
 801         do {
 802                 DELAY(delay * 1000);
 803                 rc = SHMEM_RD(sc, func_mb[mb_idx].fw_mb_header);
 804         } while ((seq != (rc & FW_MSG_SEQ_NUMBER_MASK)) && (cnt++ < 500));
 805
 806         /* is this a reply to our command? */
 807         if (seq == (rc & FW_MSG_SEQ_NUMBER_MASK)) {
 808                 rc &= FW_MSG_CODE_MASK;
 809         } else {
 810                 /* Ruh-roh! */
 811                 PMD_DRV_LOG(NOTICE, "FW failed to respond!");
 812                 rc = 0;
 813         }
 814
 815         return rc;
 816 }
 817
 818 static uint32_t
 819 bnx2x_fw_command(struct bnx2x_softc *sc, uint32_t command, uint32_t param)
 820 {
 821         return elink_cb_fw_command(sc, command, param);
 822 }
 823
 824 static void
 825 __storm_memset_dma_mapping(struct bnx2x_softc *sc, uint32_t addr,
 826                            rte_iova_t mapping)
 827 {
 828         REG_WR(sc, addr, U64_LO(mapping));
 829         REG_WR(sc, (addr + 4), U64_HI(mapping));
 830 }
 831
 832 static void
 833 storm_memset_spq_addr(struct bnx2x_softc *sc, rte_iova_t mapping,
 834                       uint16_t abs_fid)
 835 {
 836         uint32_t addr = (XSEM_REG_FAST_MEMORY +
 837                          XSTORM_SPQ_PAGE_BASE_OFFSET(abs_fid));
 838         __storm_memset_dma_mapping(sc, addr, mapping);
 839 }
 840
 841 static void
 842 storm_memset_vf_to_pf(struct bnx2x_softc *sc, uint16_t abs_fid, uint16_t pf_id)
 843 {
 844         REG_WR8(sc, (BAR_XSTRORM_INTMEM + XSTORM_VF_TO_PF_OFFSET(abs_fid)),
 845                 pf_id);
 846         REG_WR8(sc, (BAR_CSTRORM_INTMEM + CSTORM_VF_TO_PF_OFFSET(abs_fid)),
 847                 pf_id);
 848         REG_WR8(sc, (BAR_TSTRORM_INTMEM + TSTORM_VF_TO_PF_OFFSET(abs_fid)),
 849                 pf_id);
 850         REG_WR8(sc, (BAR_USTRORM_INTMEM + USTORM_VF_TO_PF_OFFSET(abs_fid)),
 851                 pf_id);
 852 }
 853
 854 static void
 855 storm_memset_func_en(struct bnx2x_softc *sc, uint16_t abs_fid, uint8_t enable)
 856 {
 857         REG_WR8(sc, (BAR_XSTRORM_INTMEM + XSTORM_FUNC_EN_OFFSET(abs_fid)),
 858                 enable);
 859         REG_WR8(sc, (BAR_CSTRORM_INTMEM + CSTORM_FUNC_EN_OFFSET(abs_fid)),
 860                 enable);
 861         REG_WR8(sc, (BAR_TSTRORM_INTMEM + TSTORM_FUNC_EN_OFFSET(abs_fid)),
 862                 enable);
 863         REG_WR8(sc, (BAR_USTRORM_INTMEM + USTORM_FUNC_EN_OFFSET(abs_fid)),
 864                 enable);
 865 }
 866
 867 static void
 868 storm_memset_eq_data(struct bnx2x_softc *sc, struct event_ring_data *eq_data,
 869                      uint16_t pfid)
 870 {
 871         uint32_t addr;
 872         size_t size;
 873
 874         addr = (BAR_CSTRORM_INTMEM + CSTORM_EVENT_RING_DATA_OFFSET(pfid));
 875         size = sizeof(struct event_ring_data);
 876         ecore_storm_memset_struct(sc, addr, size, (uint32_t *) eq_data);
 877 }
 878
 879 static void
 880 storm_memset_eq_prod(struct bnx2x_softc *sc, uint16_t eq_prod, uint16_t pfid)
 881 {
 882         uint32_t addr = (BAR_CSTRORM_INTMEM +
 883                          CSTORM_EVENT_RING_PROD_OFFSET(pfid));
 884         REG_WR16(sc, addr, eq_prod);
 885 }
 886
 887 /*
 888  * Post a slowpath command.
 889  *
 890  * A slowpath command is used to propagate a configuration change through
 891  * the controller in a controlled manner, allowing each STORM processor and
 892  * other H/W blocks to phase in the change.  The commands sent on the
 893  * slowpath are referred to as ramrods.  Depending on the ramrod used the
 894  * completion of the ramrod will occur in different ways.  Here's a
 895  * breakdown of ramrods and how they complete:
 896  *
 897  * RAMROD_CMD_ID_ETH_PORT_SETUP
 898  *   Used to setup the leading connection on a port.  Completes on the
 899  *   Receive Completion Queue (RCQ) of that port (typically fp[0]).
 900  *
 901  * RAMROD_CMD_ID_ETH_CLIENT_SETUP
 902  *   Used to setup an additional connection on a port.  Completes on the
 903  *   RCQ of the multi-queue/RSS connection being initialized.
 904  *
 905  * RAMROD_CMD_ID_ETH_STAT_QUERY
 906  *   Used to force the storm processors to update the statistics database
 907  *   in host memory.  This ramrod is send on the leading connection CID and
 908  *   completes as an index increment of the CSTORM on the default status
 909  *   block.
 910  *
 911  * RAMROD_CMD_ID_ETH_UPDATE
 912  *   Used to update the state of the leading connection, usually to udpate
 913  *   the RSS indirection table.  Completes on the RCQ of the leading
 914  *   connection. (Not currently used under FreeBSD until OS support becomes
 915  *   available.)
 916  *
 917  * RAMROD_CMD_ID_ETH_HALT
 918  *   Used when tearing down a connection prior to driver unload.  Completes
 919  *   on the RCQ of the multi-queue/RSS connection being torn down.  Don't
 920  *   use this on the leading connection.
 921  *
 922  * RAMROD_CMD_ID_ETH_SET_MAC
 923  *   Sets the Unicast/Broadcast/Multicast used by the port.  Completes on
 924  *   the RCQ of the leading connection.
 925  *
 926  * RAMROD_CMD_ID_ETH_CFC_DEL
 927  *   Used when tearing down a conneciton prior to driver unload.  Completes
 928  *   on the RCQ of the leading connection (since the current connection
 929  *   has been completely removed from controller memory).
 930  *
 931  * RAMROD_CMD_ID_ETH_PORT_DEL
 932  *   Used to tear down the leading connection prior to driver unload,
 933  *   typically fp[0].  Completes as an index increment of the CSTORM on the
 934  *   default status block.
 935  *
 936  * RAMROD_CMD_ID_ETH_FORWARD_SETUP
 937  *   Used for connection offload.  Completes on the RCQ of the multi-queue
 938  *   RSS connection that is being offloaded.  (Not currently used under
 939  *   FreeBSD.)
 940  *
 941  * There can only be one command pending per function.
 942  *
 943  * Returns:
 944  *   0 = Success, !0 = Failure.
 945  */
 946
 947 /* must be called under the spq lock */
 948 static inline struct eth_spe *bnx2x_sp_get_next(struct bnx2x_softc *sc)
 949 {
 950         struct eth_spe *next_spe = sc->spq_prod_bd;
 951
 952         if (sc->spq_prod_bd == sc->spq_last_bd) {
 953                 /* wrap back to the first eth_spq */
 954                 sc->spq_prod_bd = sc->spq;
 955                 sc->spq_prod_idx = 0;
 956         } else {
 957                 sc->spq_prod_bd++;
 958                 sc->spq_prod_idx++;
 959         }
 960
 961         return next_spe;
 962 }
 963
 964 /* must be called under the spq lock */
 965 static void bnx2x_sp_prod_update(struct bnx2x_softc *sc)
 966 {
 967         int func = SC_FUNC(sc);
 968
 969         /*
 970          * Make sure that BD data is updated before writing the producer.
 971          * BD data is written to the memory, the producer is read from the
 972          * memory, thus we need a full memory barrier to ensure the ordering.
 973          */
 974         mb();
 975
 976         REG_WR16(sc, (BAR_XSTRORM_INTMEM + XSTORM_SPQ_PROD_OFFSET(func)),
 977                  sc->spq_prod_idx);
 978
 979         mb();
 980 }
 981
 982 /**
 983  * bnx2x_is_contextless_ramrod - check if the current command ends on EQ
 984  *
 985  * @cmd:      command to check
 986  * @cmd_type: command type
 987  */
 988 static int bnx2x_is_contextless_ramrod(int cmd, int cmd_type)
 989 {
 990         if ((cmd_type == NONE_CONNECTION_TYPE) ||
 991             (cmd == RAMROD_CMD_ID_ETH_FORWARD_SETUP) ||
 992             (cmd == RAMROD_CMD_ID_ETH_CLASSIFICATION_RULES) ||
 993             (cmd == RAMROD_CMD_ID_ETH_FILTER_RULES) ||
 994             (cmd == RAMROD_CMD_ID_ETH_MULTICAST_RULES) ||
 995             (cmd == RAMROD_CMD_ID_ETH_SET_MAC) ||
 996             (cmd == RAMROD_CMD_ID_ETH_RSS_UPDATE)) {
 997                 return TRUE;
 998         } else {
 999                 return FALSE;
1000         }
1001 }
1002
1003 /**
1004  * bnx2x_sp_post - place a single command on an SP ring
1005  *
1006  * @sc:         driver handle
1007  * @command:    command to place (e.g. SETUP, FILTER_RULES, etc.)
1008  * @cid:        SW CID the command is related to
1009  * @data_hi:    command private data address (high 32 bits)
1010  * @data_lo:    command private data address (low 32 bits)
1011  * @cmd_type:   command type (e.g. NONE, ETH)
1012  *
1013  * SP data is handled as if it's always an address pair, thus data fields are
1014  * not swapped to little endian in upper functions. Instead this function swaps
1015  * data as if it's two uint32 fields.
1016  */
1017 int
1018 bnx2x_sp_post(struct bnx2x_softc *sc, int command, int cid, uint32_t data_hi,
1019             uint32_t data_lo, int cmd_type)
1020 {
1021         struct eth_spe *spe;
1022         uint16_t type;
1023         int common;
1024
1025         common = bnx2x_is_contextless_ramrod(command, cmd_type);
1026
1027         if (common) {
1028                 if (!atomic_load_acq_long(&sc->eq_spq_left)) {
1029                         PMD_DRV_LOG(INFO, "EQ ring is full!");
1030                         return -1;
1031                 }
1032         } else {
1033                 if (!atomic_load_acq_long(&sc->cq_spq_left)) {
1034                         PMD_DRV_LOG(INFO, "SPQ ring is full!");
1035                         return -1;
1036                 }
1037         }
1038
1039         spe = bnx2x_sp_get_next(sc);
1040
1041         /* CID needs port number to be encoded int it */
1042         spe->hdr.conn_and_cmd_data =
1043             htole32((command << SPE_HDR_CMD_ID_SHIFT) | HW_CID(sc, cid));
1044
1045         type = (cmd_type << SPE_HDR_CONN_TYPE_SHIFT) & SPE_HDR_CONN_TYPE;
1046
1047         /* TBD: Check if it works for VFs */
1048         type |= ((SC_FUNC(sc) << SPE_HDR_FUNCTION_ID_SHIFT) &
1049                  SPE_HDR_FUNCTION_ID);
1050
1051         spe->hdr.type = htole16(type);
1052
1053         spe->data.update_data_addr.hi = htole32(data_hi);
1054         spe->data.update_data_addr.lo = htole32(data_lo);
1055
1056         /*
1057          * It's ok if the actual decrement is issued towards the memory
1058          * somewhere between the lock and unlock. Thus no more explict
1059          * memory barrier is needed.
1060          */
1061         if (common) {
1062                 atomic_subtract_acq_long(&sc->eq_spq_left, 1);
1063         } else {
1064                 atomic_subtract_acq_long(&sc->cq_spq_left, 1);
1065         }
1066
1067         PMD_DRV_LOG(DEBUG,
1068                     "SPQE[%x] (%x:%x) (cmd, common?) (%d,%d) hw_cid %x"
1069                     "data (%x:%x) type(0x%x) left (CQ, EQ) (%lx,%lx)",
1070                     sc->spq_prod_idx,
1071                     (uint32_t) U64_HI(sc->spq_dma.paddr),
1072                     (uint32_t) (U64_LO(sc->spq_dma.paddr) +
1073                                 (uint8_t *) sc->spq_prod_bd -
1074                                 (uint8_t *) sc->spq), command, common,
1075                     HW_CID(sc, cid), data_hi, data_lo, type,
1076                     atomic_load_acq_long(&sc->cq_spq_left),
1077                     atomic_load_acq_long(&sc->eq_spq_left));
1078
1079         bnx2x_sp_prod_update(sc);
1080
1081         return 0;
1082 }
1083
1084 static void bnx2x_drv_pulse(struct bnx2x_softc *sc)
1085 {
1086         SHMEM_WR(sc, func_mb[SC_FW_MB_IDX(sc)].drv_pulse_mb,
1087                  sc->fw_drv_pulse_wr_seq);
1088 }
1089
1090 static int bnx2x_tx_queue_has_work(const struct bnx2x_fastpath *fp)
1091 {
1092         uint16_t hw_cons;
1093         struct bnx2x_tx_queue *txq = fp->sc->tx_queues[fp->index];
1094
1095         if (unlikely(!txq)) {
1096                 PMD_TX_LOG(ERR, "ERROR: TX queue is NULL");
1097                 return 0;
1098         }
1099
1100         mb();                   /* status block fields can change */
1101         hw_cons = le16toh(*fp->tx_cons_sb);
1102         return hw_cons != txq->tx_pkt_head;
1103 }
1104
1105 static uint8_t bnx2x_has_tx_work(struct bnx2x_fastpath *fp)
1106 {
1107         /* expand this for multi-cos if ever supported */
1108         return bnx2x_tx_queue_has_work(fp);
1109 }
1110
1111 static int bnx2x_has_rx_work(struct bnx2x_fastpath *fp)
1112 {
1113         uint16_t rx_cq_cons_sb;
1114         struct bnx2x_rx_queue *rxq;
1115         rxq = fp->sc->rx_queues[fp->index];
1116         if (unlikely(!rxq)) {
1117                 PMD_RX_LOG(ERR, "ERROR: RX queue is NULL");
1118                 return 0;
1119         }
1120
1121         mb();                   /* status block fields can change */
1122         rx_cq_cons_sb = le16toh(*fp->rx_cq_cons_sb);
1123         if (unlikely((rx_cq_cons_sb & MAX_RCQ_ENTRIES(rxq)) ==
1124                      MAX_RCQ_ENTRIES(rxq)))
1125                 rx_cq_cons_sb++;
1126         return rxq->rx_cq_head != rx_cq_cons_sb;
1127 }
1128
1129 static void
1130 bnx2x_sp_event(struct bnx2x_softc *sc, struct bnx2x_fastpath *fp,
1131              union eth_rx_cqe *rr_cqe)
1132 {
1133         int cid = SW_CID(rr_cqe->ramrod_cqe.conn_and_cmd_data);
1134         int command = CQE_CMD(rr_cqe->ramrod_cqe.conn_and_cmd_data);
1135         enum ecore_queue_cmd drv_cmd = ECORE_Q_CMD_MAX;
1136         struct ecore_queue_sp_obj *q_obj = &BNX2X_SP_OBJ(sc, fp).q_obj;
1137
1138         PMD_DRV_LOG(DEBUG,
1139                     "fp=%d cid=%d got ramrod #%d state is %x type is %d",
1140                     fp->index, cid, command, sc->state,
1141                     rr_cqe->ramrod_cqe.ramrod_type);
1142
1143         switch (command) {
1144         case (RAMROD_CMD_ID_ETH_CLIENT_UPDATE):
1145                 PMD_DRV_LOG(DEBUG, "got UPDATE ramrod. CID %d", cid);
1146                 drv_cmd = ECORE_Q_CMD_UPDATE;
1147                 break;
1148
1149         case (RAMROD_CMD_ID_ETH_CLIENT_SETUP):
1150                 PMD_DRV_LOG(DEBUG, "got MULTI[%d] setup ramrod", cid);
1151                 drv_cmd = ECORE_Q_CMD_SETUP;
1152                 break;
1153
1154         case (RAMROD_CMD_ID_ETH_TX_QUEUE_SETUP):
1155                 PMD_DRV_LOG(DEBUG, "got MULTI[%d] tx-only setup ramrod", cid);
1156                 drv_cmd = ECORE_Q_CMD_SETUP_TX_ONLY;
1157                 break;
1158
1159         case (RAMROD_CMD_ID_ETH_HALT):
1160                 PMD_DRV_LOG(DEBUG, "got MULTI[%d] halt ramrod", cid);
1161                 drv_cmd = ECORE_Q_CMD_HALT;
1162                 break;
1163
1164         case (RAMROD_CMD_ID_ETH_TERMINATE):
1165                 PMD_DRV_LOG(DEBUG, "got MULTI[%d] teminate ramrod", cid);
1166                 drv_cmd = ECORE_Q_CMD_TERMINATE;
1167                 break;
1168
1169         case (RAMROD_CMD_ID_ETH_EMPTY):
1170                 PMD_DRV_LOG(DEBUG, "got MULTI[%d] empty ramrod", cid);
1171                 drv_cmd = ECORE_Q_CMD_EMPTY;
1172                 break;
1173
1174         default:
1175                 PMD_DRV_LOG(DEBUG,
1176                             "ERROR: unexpected MC reply (%d)"
1177                             "on fp[%d]", command, fp->index);
1178                 return;
1179         }
1180
1181         if ((drv_cmd != ECORE_Q_CMD_MAX) &&
1182             q_obj->complete_cmd(sc, q_obj, drv_cmd)) {
1183                 /*
1184                  * q_obj->complete_cmd() failure means that this was
1185                  * an unexpected completion.
1186                  *
1187                  * In this case we don't want to increase the sc->spq_left
1188                  * because apparently we haven't sent this command the first
1189                  * place.
1190                  */
1191                 // rte_panic("Unexpected SP completion");
1192                 return;
1193         }
1194
1195         atomic_add_acq_long(&sc->cq_spq_left, 1);
1196
1197         PMD_DRV_LOG(DEBUG, "sc->cq_spq_left 0x%lx",
1198                     atomic_load_acq_long(&sc->cq_spq_left));
1199 }
1200
1201 static uint8_t bnx2x_rxeof(struct bnx2x_softc *sc, struct bnx2x_fastpath *fp)
1202 {
1203         struct bnx2x_rx_queue *rxq;
1204         uint16_t bd_cons, bd_prod, bd_prod_fw, comp_ring_cons;
1205         uint16_t hw_cq_cons, sw_cq_cons, sw_cq_prod;
1206
1207         rxq = sc->rx_queues[fp->index];
1208         if (!rxq) {
1209                 PMD_RX_LOG(ERR, "RX queue %d is NULL", fp->index);
1210                 return 0;
1211         }
1212
1213         /* CQ "next element" is of the size of the regular element */
1214         hw_cq_cons = le16toh(*fp->rx_cq_cons_sb);
1215         if (unlikely((hw_cq_cons & USABLE_RCQ_ENTRIES_PER_PAGE) ==
1216                      USABLE_RCQ_ENTRIES_PER_PAGE)) {
1217                 hw_cq_cons++;
1218         }
1219
1220         bd_cons = rxq->rx_bd_head;
1221         bd_prod = rxq->rx_bd_tail;
1222         bd_prod_fw = bd_prod;
1223         sw_cq_cons = rxq->rx_cq_head;
1224         sw_cq_prod = rxq->rx_cq_tail;
1225
1226         /*
1227          * Memory barrier necessary as speculative reads of the rx
1228          * buffer can be ahead of the index in the status block
1229          */
1230         rmb();
1231
1232         while (sw_cq_cons != hw_cq_cons) {
1233                 union eth_rx_cqe *cqe;
1234                 struct eth_fast_path_rx_cqe *cqe_fp;
1235                 uint8_t cqe_fp_flags;
1236                 enum eth_rx_cqe_type cqe_fp_type;
1237
1238                 comp_ring_cons = RCQ_ENTRY(sw_cq_cons, rxq);
1239                 bd_prod = RX_BD(bd_prod, rxq);
1240                 bd_cons = RX_BD(bd_cons, rxq);
1241
1242                 cqe = &rxq->cq_ring[comp_ring_cons];
1243                 cqe_fp = &cqe->fast_path_cqe;
1244                 cqe_fp_flags = cqe_fp->type_error_flags;
1245                 cqe_fp_type = cqe_fp_flags & ETH_FAST_PATH_RX_CQE_TYPE;
1246
1247                 /* is this a slowpath msg? */
1248                 if (CQE_TYPE_SLOW(cqe_fp_type)) {
1249                         bnx2x_sp_event(sc, fp, cqe);
1250                         goto next_cqe;
1251                 }
1252
1253                 /* is this an error packet? */
1254                 if (unlikely(cqe_fp_flags &
1255                              ETH_FAST_PATH_RX_CQE_PHY_DECODE_ERR_FLG)) {
1256                         PMD_RX_LOG(DEBUG, "flags 0x%x rx packet %u",
1257                                    cqe_fp_flags, sw_cq_cons);
1258                         goto next_rx;
1259                 }
1260
1261                 PMD_RX_LOG(DEBUG, "Dropping fastpath called from attn poller!");
1262
1263 next_rx:
1264                 bd_cons = NEXT_RX_BD(bd_cons);
1265                 bd_prod = NEXT_RX_BD(bd_prod);
1266                 bd_prod_fw = NEXT_RX_BD(bd_prod_fw);
1267
1268 next_cqe:
1269                 sw_cq_prod = NEXT_RCQ_IDX(sw_cq_prod);
1270                 sw_cq_cons = NEXT_RCQ_IDX(sw_cq_cons);
1271
1272         }                       /* while work to do */
1273
1274         rxq->rx_bd_head = bd_cons;
1275         rxq->rx_bd_tail = bd_prod_fw;
1276         rxq->rx_cq_head = sw_cq_cons;
1277         rxq->rx_cq_tail = sw_cq_prod;
1278
1279         /* Update producers */
1280         bnx2x_update_rx_prod(sc, fp, bd_prod_fw, sw_cq_prod);
1281
1282         return sw_cq_cons != hw_cq_cons;
1283 }
1284
1285 static uint16_t
1286 bnx2x_free_tx_pkt(__rte_unused struct bnx2x_fastpath *fp, struct bnx2x_tx_queue *txq,
1287                 uint16_t pkt_idx, uint16_t bd_idx)
1288 {
1289         struct eth_tx_start_bd *tx_start_bd =
1290             &txq->tx_ring[TX_BD(bd_idx, txq)].start_bd;
1291         uint16_t nbd = rte_le_to_cpu_16(tx_start_bd->nbd);
1292         struct rte_mbuf *tx_mbuf = txq->sw_ring[TX_BD(pkt_idx, txq)];
1293
1294         if (likely(tx_mbuf != NULL)) {
1295                 rte_pktmbuf_free_seg(tx_mbuf);
1296         } else {
1297                 PMD_RX_LOG(ERR, "fp[%02d] lost mbuf %lu",
1298                            fp->index, (unsigned long)TX_BD(pkt_idx, txq));
1299         }
1300
1301         txq->sw_ring[TX_BD(pkt_idx, txq)] = NULL;
1302         txq->nb_tx_avail += nbd;
1303
1304         while (nbd--)
1305                 bd_idx = NEXT_TX_BD(bd_idx);
1306
1307         return bd_idx;
1308 }
1309
1310 /* processes transmit completions */
1311 uint8_t bnx2x_txeof(__rte_unused struct bnx2x_softc * sc, struct bnx2x_fastpath * fp)
1312 {
1313         uint16_t bd_cons, hw_cons, sw_cons;
1314         __rte_unused uint16_t tx_bd_avail;
1315
1316         struct bnx2x_tx_queue *txq = fp->sc->tx_queues[fp->index];
1317
1318         if (unlikely(!txq)) {
1319                 PMD_TX_LOG(ERR, "ERROR: TX queue is NULL");
1320                 return 0;
1321         }
1322
1323         bd_cons = txq->tx_bd_head;
1324         hw_cons = rte_le_to_cpu_16(*fp->tx_cons_sb);
1325         sw_cons = txq->tx_pkt_head;
1326
1327         while (sw_cons != hw_cons) {
1328                 bd_cons = bnx2x_free_tx_pkt(fp, txq, sw_cons, bd_cons);
1329                 sw_cons++;
1330         }
1331
1332         txq->tx_pkt_head = sw_cons;
1333         txq->tx_bd_head = bd_cons;
1334
1335         tx_bd_avail = txq->nb_tx_avail;
1336
1337         PMD_TX_LOG(DEBUG, "fp[%02d] avail=%u cons_sb=%u, "
1338                    "pkt_head=%u pkt_tail=%u bd_head=%u bd_tail=%u",
1339                    fp->index, tx_bd_avail, hw_cons,
1340                    txq->tx_pkt_head, txq->tx_pkt_tail,
1341                    txq->tx_bd_head, txq->tx_bd_tail);
1342         return TRUE;
1343 }
1344
1345 static void bnx2x_drain_tx_queues(struct bnx2x_softc *sc)
1346 {
1347         struct bnx2x_fastpath *fp;
1348         int i, count;
1349
1350         /* wait until all TX fastpath tasks have completed */
1351         for (i = 0; i < sc->num_queues; i++) {
1352                 fp = &sc->fp[i];
1353
1354                 count = 1000;
1355
1356                 while (bnx2x_has_tx_work(fp)) {
1357                         bnx2x_txeof(sc, fp);
1358
1359                         if (count == 0) {
1360                                 PMD_TX_LOG(ERR,
1361                                            "Timeout waiting for fp[%d] "
1362                                            "transmits to complete!", i);
1363                                 rte_panic("tx drain failure");
1364                                 return;
1365                         }
1366
1367                         count--;
1368                         DELAY(1000);
1369                         rmb();
1370                 }
1371         }
1372
1373         return;
1374 }
1375
1376 static int
1377 bnx2x_del_all_macs(struct bnx2x_softc *sc, struct ecore_vlan_mac_obj *mac_obj,
1378                  int mac_type, uint8_t wait_for_comp)
1379 {
1380         unsigned long ramrod_flags = 0, vlan_mac_flags = 0;
1381         int rc;
1382
1383         /* wait for completion of requested */
1384         if (wait_for_comp) {
1385                 bnx2x_set_bit(RAMROD_COMP_WAIT, &ramrod_flags);
1386         }
1387
1388         /* Set the mac type of addresses we want to clear */
1389         bnx2x_set_bit(mac_type, &vlan_mac_flags);
1390
1391         rc = mac_obj->delete_all(sc, mac_obj, &vlan_mac_flags, &ramrod_flags);
1392         if (rc < 0)
1393                 PMD_DRV_LOG(ERR, "Failed to delete MACs (%d)", rc);
1394
1395         return rc;
1396 }
1397
1398 static int
1399 bnx2x_fill_accept_flags(struct bnx2x_softc *sc, uint32_t rx_mode,
1400                         unsigned long *rx_accept_flags,
1401                         unsigned long *tx_accept_flags)
1402 {
1403         /* Clear the flags first */
1404         *rx_accept_flags = 0;
1405         *tx_accept_flags = 0;
1406
1407         switch (rx_mode) {
1408         case BNX2X_RX_MODE_NONE:
1409                 /*
1410                  * 'drop all' supersedes any accept flags that may have been
1411                  * passed to the function.
1412                  */
1413                 break;
1414
1415         case BNX2X_RX_MODE_NORMAL:
1416                 bnx2x_set_bit(ECORE_ACCEPT_UNICAST, rx_accept_flags);
1417                 bnx2x_set_bit(ECORE_ACCEPT_MULTICAST, rx_accept_flags);
1418                 bnx2x_set_bit(ECORE_ACCEPT_BROADCAST, rx_accept_flags);
1419
1420                 /* internal switching mode */
1421                 bnx2x_set_bit(ECORE_ACCEPT_UNICAST, tx_accept_flags);
1422                 bnx2x_set_bit(ECORE_ACCEPT_MULTICAST, tx_accept_flags);
1423                 bnx2x_set_bit(ECORE_ACCEPT_BROADCAST, tx_accept_flags);
1424
1425                 break;
1426
1427         case BNX2X_RX_MODE_ALLMULTI:
1428                 bnx2x_set_bit(ECORE_ACCEPT_UNICAST, rx_accept_flags);
1429                 bnx2x_set_bit(ECORE_ACCEPT_ALL_MULTICAST, rx_accept_flags);
1430                 bnx2x_set_bit(ECORE_ACCEPT_BROADCAST, rx_accept_flags);
1431
1432                 /* internal switching mode */
1433                 bnx2x_set_bit(ECORE_ACCEPT_UNICAST, tx_accept_flags);
1434                 bnx2x_set_bit(ECORE_ACCEPT_ALL_MULTICAST, tx_accept_flags);
1435                 bnx2x_set_bit(ECORE_ACCEPT_BROADCAST, tx_accept_flags);
1436
1437                 break;
1438
1439         case BNX2X_RX_MODE_ALLMULTI_PROMISC:
1440         case BNX2X_RX_MODE_PROMISC:
1441                 /*
1442                  * According to deffinition of SI mode, iface in promisc mode
1443                  * should receive matched and unmatched (in resolution of port)
1444                  * unicast packets.
1445                  */
1446                 bnx2x_set_bit(ECORE_ACCEPT_UNMATCHED, rx_accept_flags);
1447                 bnx2x_set_bit(ECORE_ACCEPT_UNICAST, rx_accept_flags);
1448                 bnx2x_set_bit(ECORE_ACCEPT_ALL_MULTICAST, rx_accept_flags);
1449                 bnx2x_set_bit(ECORE_ACCEPT_BROADCAST, rx_accept_flags);
1450
1451                 /* internal switching mode */
1452                 bnx2x_set_bit(ECORE_ACCEPT_ALL_MULTICAST, tx_accept_flags);
1453                 bnx2x_set_bit(ECORE_ACCEPT_BROADCAST, tx_accept_flags);
1454
1455                 if (IS_MF_SI(sc)) {
1456                         bnx2x_set_bit(ECORE_ACCEPT_ALL_UNICAST, tx_accept_flags);
1457                 } else {
1458                         bnx2x_set_bit(ECORE_ACCEPT_UNICAST, tx_accept_flags);
1459                 }
1460
1461                 break;
1462
1463         default:
1464                 PMD_RX_LOG(ERR, "Unknown rx_mode (%d)", rx_mode);
1465                 return -1;
1466         }
1467
1468         /* Set ACCEPT_ANY_VLAN as we do not enable filtering by VLAN */
1469         if (rx_mode != BNX2X_RX_MODE_NONE) {
1470                 bnx2x_set_bit(ECORE_ACCEPT_ANY_VLAN, rx_accept_flags);
1471                 bnx2x_set_bit(ECORE_ACCEPT_ANY_VLAN, tx_accept_flags);
1472         }
1473
1474         return 0;
1475 }
1476
1477 static int
1478 bnx2x_set_q_rx_mode(struct bnx2x_softc *sc, uint8_t cl_id,
1479                   unsigned long rx_mode_flags,
1480                   unsigned long rx_accept_flags,
1481                   unsigned long tx_accept_flags, unsigned long ramrod_flags)
1482 {
1483         struct ecore_rx_mode_ramrod_params ramrod_param;
1484         int rc;
1485
1486         memset(&ramrod_param, 0, sizeof(ramrod_param));
1487
1488         /* Prepare ramrod parameters */
1489         ramrod_param.cid = 0;
1490         ramrod_param.cl_id = cl_id;
1491         ramrod_param.rx_mode_obj = &sc->rx_mode_obj;
1492         ramrod_param.func_id = SC_FUNC(sc);
1493
1494         ramrod_param.pstate = &sc->sp_state;
1495         ramrod_param.state = ECORE_FILTER_RX_MODE_PENDING;
1496
1497         ramrod_param.rdata = BNX2X_SP(sc, rx_mode_rdata);
1498         ramrod_param.rdata_mapping =
1499             (rte_iova_t)BNX2X_SP_MAPPING(sc, rx_mode_rdata),
1500             bnx2x_set_bit(ECORE_FILTER_RX_MODE_PENDING, &sc->sp_state);
1501
1502         ramrod_param.ramrod_flags = ramrod_flags;
1503         ramrod_param.rx_mode_flags = rx_mode_flags;
1504
1505         ramrod_param.rx_accept_flags = rx_accept_flags;
1506         ramrod_param.tx_accept_flags = tx_accept_flags;
1507
1508         rc = ecore_config_rx_mode(sc, &ramrod_param);
1509         if (rc < 0) {
1510                 PMD_RX_LOG(ERR, "Set rx_mode %d failed", sc->rx_mode);
1511                 return rc;
1512         }
1513
1514         return 0;
1515 }
1516
1517 int bnx2x_set_storm_rx_mode(struct bnx2x_softc *sc)
1518 {
1519         unsigned long rx_mode_flags = 0, ramrod_flags = 0;
1520         unsigned long rx_accept_flags = 0, tx_accept_flags = 0;
1521         int rc;
1522
1523         rc = bnx2x_fill_accept_flags(sc, sc->rx_mode, &rx_accept_flags,
1524                                    &tx_accept_flags);
1525         if (rc) {
1526                 return rc;
1527         }
1528
1529         bnx2x_set_bit(RAMROD_RX, &ramrod_flags);
1530         bnx2x_set_bit(RAMROD_TX, &ramrod_flags);
1531         bnx2x_set_bit(RAMROD_COMP_WAIT, &ramrod_flags);
1532
1533         return bnx2x_set_q_rx_mode(sc, sc->fp[0].cl_id, rx_mode_flags,
1534                                  rx_accept_flags, tx_accept_flags,
1535                                  ramrod_flags);
1536 }
1537
1538 /* returns the "mcp load_code" according to global load_count array */
1539 static int bnx2x_nic_load_no_mcp(struct bnx2x_softc *sc)
1540 {
1541         int path = SC_PATH(sc);
1542         int port = SC_PORT(sc);
1543
1544         PMD_DRV_LOG(INFO, "NO MCP - load counts[%d]      %d, %d, %d",
1545                     path, load_count[path][0], load_count[path][1],
1546                     load_count[path][2]);
1547
1548         load_count[path][0]++;
1549         load_count[path][1 + port]++;
1550         PMD_DRV_LOG(INFO, "NO MCP - new load counts[%d]  %d, %d, %d",
1551                     path, load_count[path][0], load_count[path][1],
1552                     load_count[path][2]);
1553         if (load_count[path][0] == 1)
1554                 return FW_MSG_CODE_DRV_LOAD_COMMON;
1555         else if (load_count[path][1 + port] == 1)
1556                 return FW_MSG_CODE_DRV_LOAD_PORT;
1557         else
1558                 return FW_MSG_CODE_DRV_LOAD_FUNCTION;
1559 }
1560
1561 /* returns the "mcp load_code" according to global load_count array */
1562 static int bnx2x_nic_unload_no_mcp(struct bnx2x_softc *sc)
1563 {
1564         int port = SC_PORT(sc);
1565         int path = SC_PATH(sc);
1566
1567         PMD_DRV_LOG(INFO, "NO MCP - load counts[%d]      %d, %d, %d",
1568                     path, load_count[path][0], load_count[path][1],
1569                     load_count[path][2]);
1570         load_count[path][0]--;
1571         load_count[path][1 + port]--;
1572         PMD_DRV_LOG(INFO, "NO MCP - new load counts[%d]  %d, %d, %d",
1573                     path, load_count[path][0], load_count[path][1],
1574                     load_count[path][2]);
1575         if (load_count[path][0] == 0) {
1576                 return FW_MSG_CODE_DRV_UNLOAD_COMMON;
1577         } else if (load_count[path][1 + port] == 0) {
1578                 return FW_MSG_CODE_DRV_UNLOAD_PORT;
1579         } else {
1580                 return FW_MSG_CODE_DRV_UNLOAD_FUNCTION;
1581         }
1582 }
1583
1584 /* request unload mode from the MCP: COMMON, PORT or FUNCTION */
1585 static uint32_t bnx2x_send_unload_req(struct bnx2x_softc *sc, int unload_mode)
1586 {
1587         uint32_t reset_code = 0;
1588
1589         /* Select the UNLOAD request mode */
1590         if (unload_mode == UNLOAD_NORMAL) {
1591                 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS;
1592         } else {
1593                 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS;
1594         }
1595
1596         /* Send the request to the MCP */
1597         if (!BNX2X_NOMCP(sc)) {
1598                 reset_code = bnx2x_fw_command(sc, reset_code, 0);
1599         } else {
1600                 reset_code = bnx2x_nic_unload_no_mcp(sc);
1601         }
1602
1603         return reset_code;
1604 }
1605
1606 /* send UNLOAD_DONE command to the MCP */
1607 static void bnx2x_send_unload_done(struct bnx2x_softc *sc, uint8_t keep_link)
1608 {
1609         uint32_t reset_param =
1610             keep_link ? DRV_MSG_CODE_UNLOAD_SKIP_LINK_RESET : 0;
1611
1612         /* Report UNLOAD_DONE to MCP */
1613         if (!BNX2X_NOMCP(sc)) {
1614                 bnx2x_fw_command(sc, DRV_MSG_CODE_UNLOAD_DONE, reset_param);
1615         }
1616 }
1617
1618 static int bnx2x_func_wait_started(struct bnx2x_softc *sc)
1619 {
1620         int tout = 50;
1621
1622         if (!sc->port.pmf) {
1623                 return 0;
1624         }
1625
1626         /*
1627          * (assumption: No Attention from MCP at this stage)
1628          * PMF probably in the middle of TX disable/enable transaction
1629          * 1. Sync IRS for default SB
1630          * 2. Sync SP queue - this guarantees us that attention handling started
1631          * 3. Wait, that TX disable/enable transaction completes
1632          *
1633          * 1+2 guarantee that if DCBX attention was scheduled it already changed
1634          * pending bit of transaction from STARTED-->TX_STOPPED, if we already
1635          * received completion for the transaction the state is TX_STOPPED.
1636          * State will return to STARTED after completion of TX_STOPPED-->STARTED
1637          * transaction.
1638          */
1639
1640         while (ecore_func_get_state(sc, &sc->func_obj) !=
1641                ECORE_F_STATE_STARTED && tout--) {
1642                 DELAY(20000);
1643         }
1644
1645         if (ecore_func_get_state(sc, &sc->func_obj) != ECORE_F_STATE_STARTED) {
1646                 /*
1647                  * Failed to complete the transaction in a "good way"
1648                  * Force both transactions with CLR bit.
1649                  */
1650                 struct ecore_func_state_params func_params = { NULL };
1651
1652                 PMD_DRV_LOG(NOTICE, "Unexpected function state! "
1653                             "Forcing STARTED-->TX_STOPPED-->STARTED");
1654
1655                 func_params.f_obj = &sc->func_obj;
1656                 bnx2x_set_bit(RAMROD_DRV_CLR_ONLY, &func_params.ramrod_flags);
1657
1658                 /* STARTED-->TX_STOPPED */
1659                 func_params.cmd = ECORE_F_CMD_TX_STOP;
1660                 ecore_func_state_change(sc, &func_params);
1661
1662                 /* TX_STOPPED-->STARTED */
1663                 func_params.cmd = ECORE_F_CMD_TX_START;
1664                 return ecore_func_state_change(sc, &func_params);
1665         }
1666
1667         return 0;
1668 }
1669
1670 static int bnx2x_stop_queue(struct bnx2x_softc *sc, int index)
1671 {
1672         struct bnx2x_fastpath *fp = &sc->fp[index];
1673         struct ecore_queue_state_params q_params = { NULL };
1674         int rc;
1675
1676         PMD_DRV_LOG(DEBUG, "stopping queue %d cid %d", index, fp->index);
1677
1678         q_params.q_obj = &sc->sp_objs[fp->index].q_obj;
1679         /* We want to wait for completion in this context */
1680         bnx2x_set_bit(RAMROD_COMP_WAIT, &q_params.ramrod_flags);
1681
1682         /* Stop the primary connection: */
1683
1684         /* ...halt the connection */
1685         q_params.cmd = ECORE_Q_CMD_HALT;
1686         rc = ecore_queue_state_change(sc, &q_params);
1687         if (rc) {
1688                 return rc;
1689         }
1690
1691         /* ...terminate the connection */
1692         q_params.cmd = ECORE_Q_CMD_TERMINATE;
1693         memset(&q_params.params.terminate, 0,
1694                sizeof(q_params.params.terminate));
1695         q_params.params.terminate.cid_index = FIRST_TX_COS_INDEX;
1696         rc = ecore_queue_state_change(sc, &q_params);
1697         if (rc) {
1698                 return rc;
1699         }
1700
1701         /* ...delete cfc entry */
1702         q_params.cmd = ECORE_Q_CMD_CFC_DEL;
1703         memset(&q_params.params.cfc_del, 0, sizeof(q_params.params.cfc_del));
1704         q_params.params.cfc_del.cid_index = FIRST_TX_COS_INDEX;
1705         return ecore_queue_state_change(sc, &q_params);
1706 }
1707
1708 /* wait for the outstanding SP commands */
1709 static uint8_t bnx2x_wait_sp_comp(struct bnx2x_softc *sc, unsigned long mask)
1710 {
1711         unsigned long tmp;
1712         int tout = 5000;        /* wait for 5 secs tops */
1713
1714         while (tout--) {
1715                 mb();
1716                 if (!(atomic_load_acq_long(&sc->sp_state) & mask)) {
1717                         return TRUE;
1718                 }
1719
1720                 DELAY(1000);
1721         }
1722
1723         mb();
1724
1725         tmp = atomic_load_acq_long(&sc->sp_state);
1726         if (tmp & mask) {
1727                 PMD_DRV_LOG(INFO, "Filtering completion timed out: "
1728                             "sp_state 0x%lx, mask 0x%lx", tmp, mask);
1729                 return FALSE;
1730         }
1731
1732         return FALSE;
1733 }
1734
1735 static int bnx2x_func_stop(struct bnx2x_softc *sc)
1736 {
1737         struct ecore_func_state_params func_params = { NULL };
1738         int rc;
1739
1740         /* prepare parameters for function state transitions */
1741         bnx2x_set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags);
1742         func_params.f_obj = &sc->func_obj;
1743         func_params.cmd = ECORE_F_CMD_STOP;
1744
1745         /*
1746          * Try to stop the function the 'good way'. If it fails (in case
1747          * of a parity error during bnx2x_chip_cleanup()) and we are
1748          * not in a debug mode, perform a state transaction in order to
1749          * enable further HW_RESET transaction.
1750          */
1751         rc = ecore_func_state_change(sc, &func_params);
1752         if (rc) {
1753                 PMD_DRV_LOG(NOTICE, "FUNC_STOP ramrod failed. "
1754                             "Running a dry transaction");
1755                 bnx2x_set_bit(RAMROD_DRV_CLR_ONLY, &func_params.ramrod_flags);
1756                 return ecore_func_state_change(sc, &func_params);
1757         }
1758
1759         return 0;
1760 }
1761
1762 static int bnx2x_reset_hw(struct bnx2x_softc *sc, uint32_t load_code)
1763 {
1764         struct ecore_func_state_params func_params = { NULL };
1765
1766         /* Prepare parameters for function state transitions */
1767         bnx2x_set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags);
1768
1769         func_params.f_obj = &sc->func_obj;
1770         func_params.cmd = ECORE_F_CMD_HW_RESET;
1771
1772         func_params.params.hw_init.load_phase = load_code;
1773
1774         return ecore_func_state_change(sc, &func_params);
1775 }
1776
1777 static void bnx2x_int_disable_sync(struct bnx2x_softc *sc, int disable_hw)
1778 {
1779         if (disable_hw) {
1780                 /* prevent the HW from sending interrupts */
1781                 bnx2x_int_disable(sc);
1782         }
1783 }
1784
1785 static void
1786 bnx2x_chip_cleanup(struct bnx2x_softc *sc, uint32_t unload_mode, uint8_t keep_link)
1787 {
1788         int port = SC_PORT(sc);
1789         struct ecore_mcast_ramrod_params rparam = { NULL };
1790         uint32_t reset_code;
1791         int i, rc = 0;
1792
1793         bnx2x_drain_tx_queues(sc);
1794
1795         /* give HW time to discard old tx messages */
1796         DELAY(1000);
1797
1798         /* Clean all ETH MACs */
1799         rc = bnx2x_del_all_macs(sc, &sc->sp_objs[0].mac_obj, ECORE_ETH_MAC,
1800                               FALSE);
1801         if (rc < 0) {
1802                 PMD_DRV_LOG(NOTICE, "Failed to delete all ETH MACs (%d)", rc);
1803         }
1804
1805         /* Clean up UC list  */
1806         rc = bnx2x_del_all_macs(sc, &sc->sp_objs[0].mac_obj, ECORE_UC_LIST_MAC,
1807                               TRUE);
1808         if (rc < 0) {
1809                 PMD_DRV_LOG(NOTICE, "Failed to delete UC MACs list (%d)", rc);
1810         }
1811
1812         /* Disable LLH */
1813         REG_WR(sc, NIG_REG_LLH0_FUNC_EN + port * 8, 0);
1814
1815         /* Set "drop all" to stop Rx */
1816
1817         /*
1818          * We need to take the if_maddr_lock() here in order to prevent
1819          * a race between the completion code and this code.
1820          */
1821
1822         if (bnx2x_test_bit(ECORE_FILTER_RX_MODE_PENDING, &sc->sp_state)) {
1823                 bnx2x_set_bit(ECORE_FILTER_RX_MODE_SCHED, &sc->sp_state);
1824         } else {
1825                 bnx2x_set_storm_rx_mode(sc);
1826         }
1827
1828         /* Clean up multicast configuration */
1829         rparam.mcast_obj = &sc->mcast_obj;
1830         rc = ecore_config_mcast(sc, &rparam, ECORE_MCAST_CMD_DEL);
1831         if (rc < 0) {
1832                 PMD_DRV_LOG(NOTICE,
1833                             "Failed to send DEL MCAST command (%d)", rc);
1834         }
1835
1836         /*
1837          * Send the UNLOAD_REQUEST to the MCP. This will return if
1838          * this function should perform FUNCTION, PORT, or COMMON HW
1839          * reset.
1840          */
1841         reset_code = bnx2x_send_unload_req(sc, unload_mode);
1842
1843         /*
1844          * (assumption: No Attention from MCP at this stage)
1845          * PMF probably in the middle of TX disable/enable transaction
1846          */
1847         rc = bnx2x_func_wait_started(sc);
1848         if (rc) {
1849                 PMD_DRV_LOG(NOTICE, "bnx2x_func_wait_started failed");
1850         }
1851
1852         /*
1853          * Close multi and leading connections
1854          * Completions for ramrods are collected in a synchronous way
1855          */
1856         for (i = 0; i < sc->num_queues; i++) {
1857                 if (bnx2x_stop_queue(sc, i)) {
1858                         goto unload_error;
1859                 }
1860         }
1861
1862         /*
1863          * If SP settings didn't get completed so far - something
1864          * very wrong has happen.
1865          */
1866         if (!bnx2x_wait_sp_comp(sc, ~0x0UL)) {
1867                 PMD_DRV_LOG(NOTICE, "Common slow path ramrods got stuck!");
1868         }
1869
1870 unload_error:
1871
1872         rc = bnx2x_func_stop(sc);
1873         if (rc) {
1874                 PMD_DRV_LOG(NOTICE, "Function stop failed!");
1875         }
1876
1877         /* disable HW interrupts */
1878         bnx2x_int_disable_sync(sc, TRUE);
1879
1880         /* Reset the chip */
1881         rc = bnx2x_reset_hw(sc, reset_code);
1882         if (rc) {
1883                 PMD_DRV_LOG(NOTICE, "Hardware reset failed");
1884         }
1885
1886         /* Report UNLOAD_DONE to MCP */
1887         bnx2x_send_unload_done(sc, keep_link);
1888 }
1889
1890 static void bnx2x_disable_close_the_gate(struct bnx2x_softc *sc)
1891 {
1892         uint32_t val;
1893
1894         PMD_DRV_LOG(DEBUG, "Disabling 'close the gates'");
1895
1896         val = REG_RD(sc, MISC_REG_AEU_GENERAL_MASK);
1897         val &= ~(MISC_AEU_GENERAL_MASK_REG_AEU_PXP_CLOSE_MASK |
1898                  MISC_AEU_GENERAL_MASK_REG_AEU_NIG_CLOSE_MASK);
1899         REG_WR(sc, MISC_REG_AEU_GENERAL_MASK, val);
1900 }
1901
1902 /*
1903  * Cleans the object that have internal lists without sending
1904  * ramrods. Should be run when interrutps are disabled.
1905  */
1906 static void bnx2x_squeeze_objects(struct bnx2x_softc *sc)
1907 {
1908         unsigned long ramrod_flags = 0, vlan_mac_flags = 0;
1909         struct ecore_mcast_ramrod_params rparam = { NULL };
1910         struct ecore_vlan_mac_obj *mac_obj = &sc->sp_objs->mac_obj;
1911         int rc;
1912
1913         /* Cleanup MACs' object first... */
1914
1915         /* Wait for completion of requested */
1916         bnx2x_set_bit(RAMROD_COMP_WAIT, &ramrod_flags);
1917         /* Perform a dry cleanup */
1918         bnx2x_set_bit(RAMROD_DRV_CLR_ONLY, &ramrod_flags);
1919
1920         /* Clean ETH primary MAC */
1921         bnx2x_set_bit(ECORE_ETH_MAC, &vlan_mac_flags);
1922         rc = mac_obj->delete_all(sc, &sc->sp_objs->mac_obj, &vlan_mac_flags,
1923                                  &ramrod_flags);
1924         if (rc != 0) {
1925                 PMD_DRV_LOG(NOTICE, "Failed to clean ETH MACs (%d)", rc);
1926         }
1927
1928         /* Cleanup UC list */
1929         vlan_mac_flags = 0;
1930         bnx2x_set_bit(ECORE_UC_LIST_MAC, &vlan_mac_flags);
1931         rc = mac_obj->delete_all(sc, mac_obj, &vlan_mac_flags, &ramrod_flags);
1932         if (rc != 0) {
1933                 PMD_DRV_LOG(NOTICE, "Failed to clean UC list MACs (%d)", rc);
1934         }
1935
1936         /* Now clean mcast object... */
1937
1938         rparam.mcast_obj = &sc->mcast_obj;
1939         bnx2x_set_bit(RAMROD_DRV_CLR_ONLY, &rparam.ramrod_flags);
1940
1941         /* Add a DEL command... */
1942         rc = ecore_config_mcast(sc, &rparam, ECORE_MCAST_CMD_DEL);
1943         if (rc < 0) {
1944                 PMD_DRV_LOG(NOTICE,
1945                             "Failed to send DEL MCAST command (%d)", rc);
1946         }
1947
1948         /* now wait until all pending commands are cleared */
1949
1950         rc = ecore_config_mcast(sc, &rparam, ECORE_MCAST_CMD_CONT);
1951         while (rc != 0) {
1952                 if (rc < 0) {
1953                         PMD_DRV_LOG(NOTICE,
1954                                     "Failed to clean MCAST object (%d)", rc);
1955                         return;
1956                 }
1957
1958                 rc = ecore_config_mcast(sc, &rparam, ECORE_MCAST_CMD_CONT);
1959         }
1960 }
1961
1962 /* stop the controller */
1963 __rte_noinline
1964 int
1965 bnx2x_nic_unload(struct bnx2x_softc *sc, uint32_t unload_mode, uint8_t keep_link)
1966 {
1967         uint8_t global = FALSE;
1968         uint32_t val;
1969
1970         PMD_DRV_LOG(DEBUG, "Starting NIC unload...");
1971
1972         /* stop the periodic callout */
1973         bnx2x_periodic_stop(sc);
1974
1975         /* mark driver as unloaded in shmem2 */
1976         if (IS_PF(sc) && SHMEM2_HAS(sc, drv_capabilities_flag)) {
1977                 val = SHMEM2_RD(sc, drv_capabilities_flag[SC_FW_MB_IDX(sc)]);
1978                 SHMEM2_WR(sc, drv_capabilities_flag[SC_FW_MB_IDX(sc)],
1979                           val & ~DRV_FLAGS_CAPABILITIES_LOADED_L2);
1980         }
1981
1982         if (IS_PF(sc) && sc->recovery_state != BNX2X_RECOVERY_DONE &&
1983             (sc->state == BNX2X_STATE_CLOSED || sc->state == BNX2X_STATE_ERROR)) {
1984                 /*
1985                  * We can get here if the driver has been unloaded
1986                  * during parity error recovery and is either waiting for a
1987                  * leader to complete or for other functions to unload and
1988                  * then ifconfig down has been issued. In this case we want to
1989                  * unload and let other functions to complete a recovery
1990                  * process.
1991                  */
1992                 sc->recovery_state = BNX2X_RECOVERY_DONE;
1993                 sc->is_leader = 0;
1994                 bnx2x_release_leader_lock(sc);
1995                 mb();
1996
1997                 PMD_DRV_LOG(NOTICE, "Can't unload in closed or error state");
1998                 return -1;
1999         }
2000
2001         /*
2002          * Nothing to do during unload if previous bnx2x_nic_load()
2003          * did not completed successfully - all resourses are released.
2004          */
2005         if ((sc->state == BNX2X_STATE_CLOSED) || (sc->state == BNX2X_STATE_ERROR)) {
2006                 return 0;
2007         }
2008
2009         sc->state = BNX2X_STATE_CLOSING_WAITING_HALT;
2010         mb();
2011
2012         sc->rx_mode = BNX2X_RX_MODE_NONE;
2013         bnx2x_set_rx_mode(sc);
2014         mb();
2015
2016         if (IS_PF(sc)) {
2017                 /* set ALWAYS_ALIVE bit in shmem */
2018                 sc->fw_drv_pulse_wr_seq |= DRV_PULSE_ALWAYS_ALIVE;
2019
2020                 bnx2x_drv_pulse(sc);
2021
2022                 bnx2x_stats_handle(sc, STATS_EVENT_STOP);
2023                 bnx2x_save_statistics(sc);
2024         }
2025
2026         /* wait till consumers catch up with producers in all queues */
2027         bnx2x_drain_tx_queues(sc);
2028
2029         /* if VF indicate to PF this function is going down (PF will delete sp
2030          * elements and clear initializations
2031          */
2032         if (IS_VF(sc)) {
2033                 bnx2x_vf_unload(sc);
2034         } else if (unload_mode != UNLOAD_RECOVERY) {
2035                 /* if this is a normal/close unload need to clean up chip */
2036                 bnx2x_chip_cleanup(sc, unload_mode, keep_link);
2037         } else {
2038                 /* Send the UNLOAD_REQUEST to the MCP */
2039                 bnx2x_send_unload_req(sc, unload_mode);
2040
2041                 /*
2042                  * Prevent transactions to host from the functions on the
2043                  * engine that doesn't reset global blocks in case of global
2044                  * attention once gloabl blocks are reset and gates are opened
2045                  * (the engine which leader will perform the recovery
2046                  * last).
2047                  */
2048                 if (!CHIP_IS_E1x(sc)) {
2049                         bnx2x_pf_disable(sc);
2050                 }
2051
2052                 /* disable HW interrupts */
2053                 bnx2x_int_disable_sync(sc, TRUE);
2054
2055                 /* Report UNLOAD_DONE to MCP */
2056                 bnx2x_send_unload_done(sc, FALSE);
2057         }
2058
2059         /*
2060          * At this stage no more interrupts will arrive so we may safely clean
2061          * the queue'able objects here in case they failed to get cleaned so far.
2062          */
2063         if (IS_PF(sc)) {
2064                 bnx2x_squeeze_objects(sc);
2065         }
2066
2067         /* There should be no more pending SP commands at this stage */
2068         sc->sp_state = 0;
2069
2070         sc->port.pmf = 0;
2071
2072         if (IS_PF(sc)) {
2073                 bnx2x_free_mem(sc);
2074         }
2075
2076         bnx2x_free_fw_stats_mem(sc);
2077
2078         sc->state = BNX2X_STATE_CLOSED;
2079
2080         /*
2081          * Check if there are pending parity attentions. If there are - set
2082          * RECOVERY_IN_PROGRESS.
2083          */
2084         if (IS_PF(sc) && bnx2x_chk_parity_attn(sc, &global, FALSE)) {
2085                 bnx2x_set_reset_in_progress(sc);
2086
2087                 /* Set RESET_IS_GLOBAL if needed */
2088                 if (global) {
2089                         bnx2x_set_reset_global(sc);
2090                 }
2091         }
2092
2093         /*
2094          * The last driver must disable a "close the gate" if there is no
2095          * parity attention or "process kill" pending.
2096          */
2097         if (IS_PF(sc) && !bnx2x_clear_pf_load(sc) &&
2098             bnx2x_reset_is_done(sc, SC_PATH(sc))) {
2099                 bnx2x_disable_close_the_gate(sc);
2100         }
2101
2102         PMD_DRV_LOG(DEBUG, "Ended NIC unload");
2103
2104         return 0;
2105 }
2106
2107 /*
2108  * Encapsulte an mbuf cluster into the tx bd chain and makes the memory
2109  * visible to the controller.
2110  *
2111  * If an mbuf is submitted to this routine and cannot be given to the
2112  * controller (e.g. it has too many fragments) then the function may free
2113  * the mbuf and return to the caller.
2114  *
2115  * Returns:
2116  *     int: Number of TX BDs used for the mbuf
2117  *
2118  *   Note the side effect that an mbuf may be freed if it causes a problem.
2119  */
2120 int bnx2x_tx_encap(struct bnx2x_tx_queue *txq, struct rte_mbuf *m0)
2121 {
2122         struct eth_tx_start_bd *tx_start_bd;
2123         uint16_t bd_prod, pkt_prod;
2124         struct bnx2x_softc *sc;
2125         uint32_t nbds = 0;
2126
2127         sc = txq->sc;
2128         bd_prod = txq->tx_bd_tail;
2129         pkt_prod = txq->tx_pkt_tail;
2130
2131         txq->sw_ring[TX_BD(pkt_prod, txq)] = m0;
2132
2133         tx_start_bd = &txq->tx_ring[TX_BD(bd_prod, txq)].start_bd;
2134
2135         tx_start_bd->addr =
2136             rte_cpu_to_le_64(rte_mbuf_data_iova(m0));
2137         tx_start_bd->nbytes = rte_cpu_to_le_16(m0->data_len);
2138         tx_start_bd->bd_flags.as_bitfield = ETH_TX_BD_FLAGS_START_BD;
2139         tx_start_bd->general_data =
2140             (1 << ETH_TX_START_BD_HDR_NBDS_SHIFT);
2141
2142         tx_start_bd->nbd = rte_cpu_to_le_16(2);
2143
2144         if (m0->ol_flags & PKT_TX_VLAN_PKT) {
2145                 tx_start_bd->vlan_or_ethertype =
2146                     rte_cpu_to_le_16(m0->vlan_tci);
2147                 tx_start_bd->bd_flags.as_bitfield |=
2148                     (X_ETH_OUTBAND_VLAN <<
2149                      ETH_TX_BD_FLAGS_VLAN_MODE_SHIFT);
2150         } else {
2151                 if (IS_PF(sc))
2152                         tx_start_bd->vlan_or_ethertype =
2153                             rte_cpu_to_le_16(pkt_prod);
2154                 else {
2155                         struct ether_hdr *eh =
2156                             rte_pktmbuf_mtod(m0, struct ether_hdr *);
2157
2158                         tx_start_bd->vlan_or_ethertype =
2159                             rte_cpu_to_le_16(rte_be_to_cpu_16(eh->ether_type));
2160                 }
2161         }
2162
2163         bd_prod = NEXT_TX_BD(bd_prod);
2164         if (IS_VF(sc)) {
2165                 struct eth_tx_parse_bd_e2 *tx_parse_bd;
2166                 const struct ether_hdr *eh =
2167                     rte_pktmbuf_mtod(m0, struct ether_hdr *);
2168                 uint8_t mac_type = UNICAST_ADDRESS;
2169
2170                 tx_parse_bd =
2171                     &txq->tx_ring[TX_BD(bd_prod, txq)].parse_bd_e2;
2172                 if (is_multicast_ether_addr(&eh->d_addr)) {
2173                         if (is_broadcast_ether_addr(&eh->d_addr))
2174                                 mac_type = BROADCAST_ADDRESS;
2175                         else
2176                                 mac_type = MULTICAST_ADDRESS;
2177                 }
2178                 tx_parse_bd->parsing_data =
2179                     (mac_type << ETH_TX_PARSE_BD_E2_ETH_ADDR_TYPE_SHIFT);
2180
2181                 rte_memcpy(&tx_parse_bd->data.mac_addr.dst_hi,
2182                            &eh->d_addr.addr_bytes[0], 2);
2183                 rte_memcpy(&tx_parse_bd->data.mac_addr.dst_mid,
2184                            &eh->d_addr.addr_bytes[2], 2);
2185                 rte_memcpy(&tx_parse_bd->data.mac_addr.dst_lo,
2186                            &eh->d_addr.addr_bytes[4], 2);
2187                 rte_memcpy(&tx_parse_bd->data.mac_addr.src_hi,
2188                            &eh->s_addr.addr_bytes[0], 2);
2189                 rte_memcpy(&tx_parse_bd->data.mac_addr.src_mid,
2190                            &eh->s_addr.addr_bytes[2], 2);
2191                 rte_memcpy(&tx_parse_bd->data.mac_addr.src_lo,
2192                            &eh->s_addr.addr_bytes[4], 2);
2193
2194                 tx_parse_bd->data.mac_addr.dst_hi =
2195                     rte_cpu_to_be_16(tx_parse_bd->data.mac_addr.dst_hi);
2196                 tx_parse_bd->data.mac_addr.dst_mid =
2197                     rte_cpu_to_be_16(tx_parse_bd->data.
2198                                      mac_addr.dst_mid);
2199                 tx_parse_bd->data.mac_addr.dst_lo =
2200                     rte_cpu_to_be_16(tx_parse_bd->data.mac_addr.dst_lo);
2201                 tx_parse_bd->data.mac_addr.src_hi =
2202                     rte_cpu_to_be_16(tx_parse_bd->data.mac_addr.src_hi);
2203                 tx_parse_bd->data.mac_addr.src_mid =
2204                     rte_cpu_to_be_16(tx_parse_bd->data.
2205                                      mac_addr.src_mid);
2206                 tx_parse_bd->data.mac_addr.src_lo =
2207                     rte_cpu_to_be_16(tx_parse_bd->data.mac_addr.src_lo);
2208
2209                 PMD_TX_LOG(DEBUG,
2210                            "PBD dst %x %x %x src %x %x %x p_data %x",
2211                            tx_parse_bd->data.mac_addr.dst_hi,
2212                            tx_parse_bd->data.mac_addr.dst_mid,
2213                            tx_parse_bd->data.mac_addr.dst_lo,
2214                            tx_parse_bd->data.mac_addr.src_hi,
2215                            tx_parse_bd->data.mac_addr.src_mid,
2216                            tx_parse_bd->data.mac_addr.src_lo,
2217                            tx_parse_bd->parsing_data);
2218         }
2219
2220         PMD_TX_LOG(DEBUG,
2221                    "start bd: nbytes %d flags %x vlan %x",
2222                    tx_start_bd->nbytes,
2223                    tx_start_bd->bd_flags.as_bitfield,
2224                    tx_start_bd->vlan_or_ethertype);
2225
2226         bd_prod = NEXT_TX_BD(bd_prod);
2227         pkt_prod++;
2228
2229         if (TX_IDX(bd_prod) < 2)
2230                 nbds++;
2231
2232         txq->nb_tx_avail -= 2;
2233         txq->tx_bd_tail = bd_prod;
2234         txq->tx_pkt_tail = pkt_prod;
2235
2236         return nbds + 2;
2237 }
2238
2239 static uint16_t bnx2x_cid_ilt_lines(struct bnx2x_softc *sc)
2240 {
2241         return L2_ILT_LINES(sc);
2242 }
2243
2244 static void bnx2x_ilt_set_info(struct bnx2x_softc *sc)
2245 {
2246         struct ilt_client_info *ilt_client;
2247         struct ecore_ilt *ilt = sc->ilt;
2248         uint16_t line = 0;
2249
2250         PMD_INIT_FUNC_TRACE();
2251
2252         ilt->start_line = FUNC_ILT_BASE(SC_FUNC(sc));
2253
2254         /* CDU */
2255         ilt_client = &ilt->clients[ILT_CLIENT_CDU];
2256         ilt_client->client_num = ILT_CLIENT_CDU;
2257         ilt_client->page_size = CDU_ILT_PAGE_SZ;
2258         ilt_client->flags = ILT_CLIENT_SKIP_MEM;
2259         ilt_client->start = line;
2260         line += bnx2x_cid_ilt_lines(sc);
2261
2262         if (CNIC_SUPPORT(sc)) {
2263                 line += CNIC_ILT_LINES;
2264         }
2265
2266         ilt_client->end = (line - 1);
2267
2268         /* QM */
2269         if (QM_INIT(sc->qm_cid_count)) {
2270                 ilt_client = &ilt->clients[ILT_CLIENT_QM];
2271                 ilt_client->client_num = ILT_CLIENT_QM;
2272                 ilt_client->page_size = QM_ILT_PAGE_SZ;
2273                 ilt_client->flags = 0;
2274                 ilt_client->start = line;
2275
2276                 /* 4 bytes for each cid */
2277                 line += DIV_ROUND_UP(sc->qm_cid_count * QM_QUEUES_PER_FUNC * 4,
2278                                      QM_ILT_PAGE_SZ);
2279
2280                 ilt_client->end = (line - 1);
2281         }
2282
2283         if (CNIC_SUPPORT(sc)) {
2284                 /* SRC */
2285                 ilt_client = &ilt->clients[ILT_CLIENT_SRC];
2286                 ilt_client->client_num = ILT_CLIENT_SRC;
2287                 ilt_client->page_size = SRC_ILT_PAGE_SZ;
2288                 ilt_client->flags = 0;
2289                 ilt_client->start = line;
2290                 line += SRC_ILT_LINES;
2291                 ilt_client->end = (line - 1);
2292
2293                 /* TM */
2294                 ilt_client = &ilt->clients[ILT_CLIENT_TM];
2295                 ilt_client->client_num = ILT_CLIENT_TM;
2296                 ilt_client->page_size = TM_ILT_PAGE_SZ;
2297                 ilt_client->flags = 0;
2298                 ilt_client->start = line;
2299                 line += TM_ILT_LINES;
2300                 ilt_client->end = (line - 1);
2301         }
2302
2303         assert((line <= ILT_MAX_LINES));
2304 }
2305
2306 static void bnx2x_set_fp_rx_buf_size(struct bnx2x_softc *sc)
2307 {
2308         int i;
2309
2310         for (i = 0; i < sc->num_queues; i++) {
2311                 /* get the Rx buffer size for RX frames */
2312                 sc->fp[i].rx_buf_size =
2313                     (IP_HEADER_ALIGNMENT_PADDING + ETH_OVERHEAD + sc->mtu);
2314         }
2315 }
2316
2317 int bnx2x_alloc_ilt_mem(struct bnx2x_softc *sc)
2318 {
2319
2320         sc->ilt = rte_malloc("", sizeof(struct ecore_ilt), RTE_CACHE_LINE_SIZE);
2321
2322         return sc->ilt == NULL;
2323 }
2324
2325 static int bnx2x_alloc_ilt_lines_mem(struct bnx2x_softc *sc)
2326 {
2327         sc->ilt->lines = rte_calloc("",
2328                                     sizeof(struct ilt_line), ILT_MAX_LINES,
2329                                     RTE_CACHE_LINE_SIZE);
2330         return sc->ilt->lines == NULL;
2331 }
2332
2333 void bnx2x_free_ilt_mem(struct bnx2x_softc *sc)
2334 {
2335         rte_free(sc->ilt);
2336         sc->ilt = NULL;
2337 }
2338
2339 static void bnx2x_free_ilt_lines_mem(struct bnx2x_softc *sc)
2340 {
2341         if (sc->ilt->lines != NULL) {
2342                 rte_free(sc->ilt->lines);
2343                 sc->ilt->lines = NULL;
2344         }
2345 }
2346
2347 static void bnx2x_free_mem(struct bnx2x_softc *sc)
2348 {
2349         uint32_t i;
2350
2351         for (i = 0; i < L2_ILT_LINES(sc); i++) {
2352                 sc->context[i].vcxt = NULL;
2353                 sc->context[i].size = 0;
2354         }
2355
2356         ecore_ilt_mem_op(sc, ILT_MEMOP_FREE);
2357
2358         bnx2x_free_ilt_lines_mem(sc);
2359 }
2360
2361 static int bnx2x_alloc_mem(struct bnx2x_softc *sc)
2362 {
2363         int context_size;
2364         int allocated;
2365         int i;
2366         char cdu_name[RTE_MEMZONE_NAMESIZE];
2367
2368         /*
2369          * Allocate memory for CDU context:
2370          * This memory is allocated separately and not in the generic ILT
2371          * functions because CDU differs in few aspects:
2372          * 1. There can be multiple entities allocating memory for context -
2373          * regular L2, CNIC, and SRIOV drivers. Each separately controls
2374          * its own ILT lines.
2375          * 2. Since CDU page-size is not a single 4KB page (which is the case
2376          * for the other ILT clients), to be efficient we want to support
2377          * allocation of sub-page-size in the last entry.
2378          * 3. Context pointers are used by the driver to pass to FW / update
2379          * the context (for the other ILT clients the pointers are used just to
2380          * free the memory during unload).
2381          */
2382         context_size = (sizeof(union cdu_context) * BNX2X_L2_CID_COUNT(sc));
2383         for (i = 0, allocated = 0; allocated < context_size; i++) {
2384                 sc->context[i].size = min(CDU_ILT_PAGE_SZ,
2385                                           (context_size - allocated));
2386
2387                 snprintf(cdu_name, sizeof(cdu_name), "cdu_%d", i);
2388                 if (bnx2x_dma_alloc(sc, sc->context[i].size,
2389                                   &sc->context[i].vcxt_dma,
2390                                   cdu_name, BNX2X_PAGE_SIZE) != 0) {
2391                         bnx2x_free_mem(sc);
2392                         return -1;
2393                 }
2394
2395                 sc->context[i].vcxt =
2396                     (union cdu_context *)sc->context[i].vcxt_dma.vaddr;
2397
2398                 allocated += sc->context[i].size;
2399         }
2400
2401         bnx2x_alloc_ilt_lines_mem(sc);
2402
2403         if (ecore_ilt_mem_op(sc, ILT_MEMOP_ALLOC)) {
2404                 PMD_DRV_LOG(NOTICE, "ecore_ilt_mem_op ILT_MEMOP_ALLOC failed");
2405                 bnx2x_free_mem(sc);
2406                 return -1;
2407         }
2408
2409         return 0;
2410 }
2411
2412 static void bnx2x_free_fw_stats_mem(struct bnx2x_softc *sc)
2413 {
2414         sc->fw_stats_num = 0;
2415
2416         sc->fw_stats_req_size = 0;
2417         sc->fw_stats_req = NULL;
2418         sc->fw_stats_req_mapping = 0;
2419
2420         sc->fw_stats_data_size = 0;
2421         sc->fw_stats_data = NULL;
2422         sc->fw_stats_data_mapping = 0;
2423 }
2424
2425 static int bnx2x_alloc_fw_stats_mem(struct bnx2x_softc *sc)
2426 {
2427         uint8_t num_queue_stats;
2428         int num_groups, vf_headroom = 0;
2429
2430         /* number of queues for statistics is number of eth queues */
2431         num_queue_stats = BNX2X_NUM_ETH_QUEUES(sc);
2432
2433         /*
2434          * Total number of FW statistics requests =
2435          *   1 for port stats + 1 for PF stats + num of queues
2436          */
2437         sc->fw_stats_num = (2 + num_queue_stats);
2438
2439         /*
2440          * Request is built from stats_query_header and an array of
2441          * stats_query_cmd_group each of which contains STATS_QUERY_CMD_COUNT
2442          * rules. The real number or requests is configured in the
2443          * stats_query_header.
2444          */
2445         num_groups = (sc->fw_stats_num + vf_headroom) / STATS_QUERY_CMD_COUNT;
2446         if ((sc->fw_stats_num + vf_headroom) % STATS_QUERY_CMD_COUNT)
2447                 num_groups++;
2448
2449         sc->fw_stats_req_size =
2450             (sizeof(struct stats_query_header) +
2451              (num_groups * sizeof(struct stats_query_cmd_group)));
2452
2453         /*
2454          * Data for statistics requests + stats_counter.
2455          * stats_counter holds per-STORM counters that are incremented when
2456          * STORM has finished with the current request. Memory for FCoE
2457          * offloaded statistics are counted anyway, even if they will not be sent.
2458          * VF stats are not accounted for here as the data of VF stats is stored
2459          * in memory allocated by the VF, not here.
2460          */
2461         sc->fw_stats_data_size =
2462             (sizeof(struct stats_counter) +
2463              sizeof(struct per_port_stats) + sizeof(struct per_pf_stats) +
2464              /* sizeof(struct fcoe_statistics_params) + */
2465              (sizeof(struct per_queue_stats) * num_queue_stats));
2466
2467         if (bnx2x_dma_alloc(sc, (sc->fw_stats_req_size + sc->fw_stats_data_size),
2468                           &sc->fw_stats_dma, "fw_stats",
2469                           RTE_CACHE_LINE_SIZE) != 0) {
2470                 bnx2x_free_fw_stats_mem(sc);
2471                 return -1;
2472         }
2473
2474         /* set up the shortcuts */
2475
2476         sc->fw_stats_req = (struct bnx2x_fw_stats_req *)sc->fw_stats_dma.vaddr;
2477         sc->fw_stats_req_mapping = sc->fw_stats_dma.paddr;
2478
2479         sc->fw_stats_data =
2480             (struct bnx2x_fw_stats_data *)((uint8_t *) sc->fw_stats_dma.vaddr +
2481                                          sc->fw_stats_req_size);
2482         sc->fw_stats_data_mapping = (sc->fw_stats_dma.paddr +
2483                                      sc->fw_stats_req_size);
2484
2485         return 0;
2486 }
2487
2488 /*
2489  * Bits map:
2490  * 0-7  - Engine0 load counter.
2491  * 8-15 - Engine1 load counter.
2492  * 16   - Engine0 RESET_IN_PROGRESS bit.
2493  * 17   - Engine1 RESET_IN_PROGRESS bit.
2494  * 18   - Engine0 ONE_IS_LOADED. Set when there is at least one active
2495  *        function on the engine
2496  * 19   - Engine1 ONE_IS_LOADED.
2497  * 20   - Chip reset flow bit. When set none-leader must wait for both engines
2498  *        leader to complete (check for both RESET_IN_PROGRESS bits and not
2499  *        for just the one belonging to its engine).
2500  */
2501 #define BNX2X_RECOVERY_GLOB_REG     MISC_REG_GENERIC_POR_1
2502 #define BNX2X_PATH0_LOAD_CNT_MASK   0x000000ff
2503 #define BNX2X_PATH0_LOAD_CNT_SHIFT  0
2504 #define BNX2X_PATH1_LOAD_CNT_MASK   0x0000ff00
2505 #define BNX2X_PATH1_LOAD_CNT_SHIFT  8
2506 #define BNX2X_PATH0_RST_IN_PROG_BIT 0x00010000
2507 #define BNX2X_PATH1_RST_IN_PROG_BIT 0x00020000
2508 #define BNX2X_GLOBAL_RESET_BIT      0x00040000
2509
2510 /* set the GLOBAL_RESET bit, should be run under rtnl lock */
2511 static void bnx2x_set_reset_global(struct bnx2x_softc *sc)
2512 {
2513         uint32_t val;
2514         bnx2x_acquire_hw_lock(sc, HW_LOCK_RESOURCE_RECOVERY_REG);
2515         val = REG_RD(sc, BNX2X_RECOVERY_GLOB_REG);
2516         REG_WR(sc, BNX2X_RECOVERY_GLOB_REG, val | BNX2X_GLOBAL_RESET_BIT);
2517         bnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_RECOVERY_REG);
2518 }
2519
2520 /* clear the GLOBAL_RESET bit, should be run under rtnl lock */
2521 static void bnx2x_clear_reset_global(struct bnx2x_softc *sc)
2522 {
2523         uint32_t val;
2524         bnx2x_acquire_hw_lock(sc, HW_LOCK_RESOURCE_RECOVERY_REG);
2525         val = REG_RD(sc, BNX2X_RECOVERY_GLOB_REG);
2526         REG_WR(sc, BNX2X_RECOVERY_GLOB_REG, val & (~BNX2X_GLOBAL_RESET_BIT));
2527         bnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_RECOVERY_REG);
2528 }
2529
2530 /* checks the GLOBAL_RESET bit, should be run under rtnl lock */
2531 static uint8_t bnx2x_reset_is_global(struct bnx2x_softc *sc)
2532 {
2533         return REG_RD(sc, BNX2X_RECOVERY_GLOB_REG) & BNX2X_GLOBAL_RESET_BIT;
2534 }
2535
2536 /* clear RESET_IN_PROGRESS bit for the engine, should be run under rtnl lock */
2537 static void bnx2x_set_reset_done(struct bnx2x_softc *sc)
2538 {
2539         uint32_t val;
2540         uint32_t bit = SC_PATH(sc) ? BNX2X_PATH1_RST_IN_PROG_BIT :
2541             BNX2X_PATH0_RST_IN_PROG_BIT;
2542
2543         bnx2x_acquire_hw_lock(sc, HW_LOCK_RESOURCE_RECOVERY_REG);
2544
2545         val = REG_RD(sc, BNX2X_RECOVERY_GLOB_REG);
2546         /* Clear the bit */
2547         val &= ~bit;
2548         REG_WR(sc, BNX2X_RECOVERY_GLOB_REG, val);
2549
2550         bnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_RECOVERY_REG);
2551 }
2552
2553 /* set RESET_IN_PROGRESS for the engine, should be run under rtnl lock */
2554 static void bnx2x_set_reset_in_progress(struct bnx2x_softc *sc)
2555 {
2556         uint32_t val;
2557         uint32_t bit = SC_PATH(sc) ? BNX2X_PATH1_RST_IN_PROG_BIT :
2558             BNX2X_PATH0_RST_IN_PROG_BIT;
2559
2560         bnx2x_acquire_hw_lock(sc, HW_LOCK_RESOURCE_RECOVERY_REG);
2561
2562         val = REG_RD(sc, BNX2X_RECOVERY_GLOB_REG);
2563         /* Set the bit */
2564         val |= bit;
2565         REG_WR(sc, BNX2X_RECOVERY_GLOB_REG, val);
2566
2567         bnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_RECOVERY_REG);
2568 }
2569
2570 /* check RESET_IN_PROGRESS bit for an engine, should be run under rtnl lock */
2571 static uint8_t bnx2x_reset_is_done(struct bnx2x_softc *sc, int engine)
2572 {
2573         uint32_t val = REG_RD(sc, BNX2X_RECOVERY_GLOB_REG);
2574         uint32_t bit = engine ? BNX2X_PATH1_RST_IN_PROG_BIT :
2575             BNX2X_PATH0_RST_IN_PROG_BIT;
2576
2577         /* return false if bit is set */
2578         return (val & bit) ? FALSE : TRUE;
2579 }
2580
2581 /* get the load status for an engine, should be run under rtnl lock */
2582 static uint8_t bnx2x_get_load_status(struct bnx2x_softc *sc, int engine)
2583 {
2584         uint32_t mask = engine ? BNX2X_PATH1_LOAD_CNT_MASK :
2585             BNX2X_PATH0_LOAD_CNT_MASK;
2586         uint32_t shift = engine ? BNX2X_PATH1_LOAD_CNT_SHIFT :
2587             BNX2X_PATH0_LOAD_CNT_SHIFT;
2588         uint32_t val = REG_RD(sc, BNX2X_RECOVERY_GLOB_REG);
2589
2590         val = ((val & mask) >> shift);
2591
2592         return val != 0;
2593 }
2594
2595 /* set pf load mark */
2596 static void bnx2x_set_pf_load(struct bnx2x_softc *sc)
2597 {
2598         uint32_t val;
2599         uint32_t val1;
2600         uint32_t mask = SC_PATH(sc) ? BNX2X_PATH1_LOAD_CNT_MASK :
2601             BNX2X_PATH0_LOAD_CNT_MASK;
2602         uint32_t shift = SC_PATH(sc) ? BNX2X_PATH1_LOAD_CNT_SHIFT :
2603             BNX2X_PATH0_LOAD_CNT_SHIFT;
2604
2605         bnx2x_acquire_hw_lock(sc, HW_LOCK_RESOURCE_RECOVERY_REG);
2606
2607         PMD_INIT_FUNC_TRACE();
2608
2609         val = REG_RD(sc, BNX2X_RECOVERY_GLOB_REG);
2610
2611         /* get the current counter value */
2612         val1 = ((val & mask) >> shift);
2613
2614         /* set bit of this PF */
2615         val1 |= (1 << SC_ABS_FUNC(sc));
2616
2617         /* clear the old value */
2618         val &= ~mask;
2619
2620         /* set the new one */
2621         val |= ((val1 << shift) & mask);
2622
2623         REG_WR(sc, BNX2X_RECOVERY_GLOB_REG, val);
2624
2625         bnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_RECOVERY_REG);
2626 }
2627
2628 /* clear pf load mark */
2629 static uint8_t bnx2x_clear_pf_load(struct bnx2x_softc *sc)
2630 {
2631         uint32_t val1, val;
2632         uint32_t mask = SC_PATH(sc) ? BNX2X_PATH1_LOAD_CNT_MASK :
2633             BNX2X_PATH0_LOAD_CNT_MASK;
2634         uint32_t shift = SC_PATH(sc) ? BNX2X_PATH1_LOAD_CNT_SHIFT :
2635             BNX2X_PATH0_LOAD_CNT_SHIFT;
2636
2637         bnx2x_acquire_hw_lock(sc, HW_LOCK_RESOURCE_RECOVERY_REG);
2638         val = REG_RD(sc, BNX2X_RECOVERY_GLOB_REG);
2639
2640         /* get the current counter value */
2641         val1 = (val & mask) >> shift;
2642
2643         /* clear bit of that PF */
2644         val1 &= ~(1 << SC_ABS_FUNC(sc));
2645
2646         /* clear the old value */
2647         val &= ~mask;
2648
2649         /* set the new one */
2650         val |= ((val1 << shift) & mask);
2651
2652         REG_WR(sc, BNX2X_RECOVERY_GLOB_REG, val);
2653         bnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_RECOVERY_REG);
2654         return val1 != 0;
2655 }
2656
2657 /* send load requrest to mcp and analyze response */
2658 static int bnx2x_nic_load_request(struct bnx2x_softc *sc, uint32_t * load_code)
2659 {
2660         PMD_INIT_FUNC_TRACE();
2661
2662         /* init fw_seq */
2663         sc->fw_seq =
2664             (SHMEM_RD(sc, func_mb[SC_FW_MB_IDX(sc)].drv_mb_header) &
2665              DRV_MSG_SEQ_NUMBER_MASK);
2666
2667         PMD_DRV_LOG(DEBUG, "initial fw_seq 0x%04x", sc->fw_seq);
2668
2669 #ifdef BNX2X_PULSE
2670         /* get the current FW pulse sequence */
2671         sc->fw_drv_pulse_wr_seq =
2672             (SHMEM_RD(sc, func_mb[SC_FW_MB_IDX(sc)].drv_pulse_mb) &
2673              DRV_PULSE_SEQ_MASK);
2674 #else
2675         /* set ALWAYS_ALIVE bit in shmem */
2676         sc->fw_drv_pulse_wr_seq |= DRV_PULSE_ALWAYS_ALIVE;
2677         bnx2x_drv_pulse(sc);
2678 #endif
2679
2680         /* load request */
2681         (*load_code) = bnx2x_fw_command(sc, DRV_MSG_CODE_LOAD_REQ,
2682                                       DRV_MSG_CODE_LOAD_REQ_WITH_LFA);
2683
2684         /* if the MCP fails to respond we must abort */
2685         if (!(*load_code)) {
2686                 PMD_DRV_LOG(NOTICE, "MCP response failure!");
2687                 return -1;
2688         }
2689
2690         /* if MCP refused then must abort */
2691         if ((*load_code) == FW_MSG_CODE_DRV_LOAD_REFUSED) {
2692                 PMD_DRV_LOG(NOTICE, "MCP refused load request");
2693                 return -1;
2694         }
2695
2696         return 0;
2697 }
2698
2699 /*
2700  * Check whether another PF has already loaded FW to chip. In virtualized
2701  * environments a pf from anoth VM may have already initialized the device
2702  * including loading FW.
2703  */
2704 static int bnx2x_nic_load_analyze_req(struct bnx2x_softc *sc, uint32_t load_code)
2705 {
2706         uint32_t my_fw, loaded_fw;
2707
2708         /* is another pf loaded on this engine? */
2709         if ((load_code != FW_MSG_CODE_DRV_LOAD_COMMON_CHIP) &&
2710             (load_code != FW_MSG_CODE_DRV_LOAD_COMMON)) {
2711                 /* build my FW version dword */
2712                 my_fw = (BNX2X_5710_FW_MAJOR_VERSION +
2713                          (BNX2X_5710_FW_MINOR_VERSION << 8) +
2714                          (BNX2X_5710_FW_REVISION_VERSION << 16) +
2715                          (BNX2X_5710_FW_ENGINEERING_VERSION << 24));
2716
2717                 /* read loaded FW from chip */
2718                 loaded_fw = REG_RD(sc, XSEM_REG_PRAM);
2719                 PMD_DRV_LOG(DEBUG, "loaded FW 0x%08x / my FW 0x%08x",
2720                             loaded_fw, my_fw);
2721
2722                 /* abort nic load if version mismatch */
2723                 if (my_fw != loaded_fw) {
2724                         PMD_DRV_LOG(NOTICE,
2725                                     "FW 0x%08x already loaded (mine is 0x%08x)",
2726                                     loaded_fw, my_fw);
2727                         return -1;
2728                 }
2729         }
2730
2731         return 0;
2732 }
2733
2734 /* mark PMF if applicable */
2735 static void bnx2x_nic_load_pmf(struct bnx2x_softc *sc, uint32_t load_code)
2736 {
2737         uint32_t ncsi_oem_data_addr;
2738
2739         PMD_INIT_FUNC_TRACE();
2740
2741         if ((load_code == FW_MSG_CODE_DRV_LOAD_COMMON) ||
2742             (load_code == FW_MSG_CODE_DRV_LOAD_COMMON_CHIP) ||
2743             (load_code == FW_MSG_CODE_DRV_LOAD_PORT)) {
2744                 /*
2745                  * Barrier here for ordering between the writing to sc->port.pmf here
2746                  * and reading it from the periodic task.
2747                  */
2748                 sc->port.pmf = 1;
2749                 mb();
2750         } else {
2751                 sc->port.pmf = 0;
2752         }
2753
2754         PMD_DRV_LOG(DEBUG, "pmf %d", sc->port.pmf);
2755
2756         if (load_code == FW_MSG_CODE_DRV_LOAD_COMMON_CHIP) {
2757                 if (SHMEM2_HAS(sc, ncsi_oem_data_addr)) {
2758                         ncsi_oem_data_addr = SHMEM2_RD(sc, ncsi_oem_data_addr);
2759                         if (ncsi_oem_data_addr) {
2760                                 REG_WR(sc,
2761                                        (ncsi_oem_data_addr +
2762                                         offsetof(struct glob_ncsi_oem_data,
2763                                                  driver_version)), 0);
2764                         }
2765                 }
2766         }
2767 }
2768
2769 static void bnx2x_read_mf_cfg(struct bnx2x_softc *sc)
2770 {
2771         int n = (CHIP_IS_MODE_4_PORT(sc) ? 2 : 1);
2772         int abs_func;
2773         int vn;
2774
2775         if (BNX2X_NOMCP(sc)) {
2776                 return;         /* what should be the default bvalue in this case */
2777         }
2778
2779         /*
2780          * The formula for computing the absolute function number is...
2781          * For 2 port configuration (4 functions per port):
2782          *   abs_func = 2 * vn + SC_PORT + SC_PATH
2783          * For 4 port configuration (2 functions per port):
2784          *   abs_func = 4 * vn + 2 * SC_PORT + SC_PATH
2785          */
2786         for (vn = VN_0; vn < SC_MAX_VN_NUM(sc); vn++) {
2787                 abs_func = (n * (2 * vn + SC_PORT(sc)) + SC_PATH(sc));
2788                 if (abs_func >= E1H_FUNC_MAX) {
2789                         break;
2790                 }
2791                 sc->devinfo.mf_info.mf_config[vn] =
2792                     MFCFG_RD(sc, func_mf_config[abs_func].config);
2793         }
2794
2795         if (sc->devinfo.mf_info.mf_config[SC_VN(sc)] &
2796             FUNC_MF_CFG_FUNC_DISABLED) {
2797                 PMD_DRV_LOG(DEBUG, "mf_cfg function disabled");
2798                 sc->flags |= BNX2X_MF_FUNC_DIS;
2799         } else {
2800                 PMD_DRV_LOG(DEBUG, "mf_cfg function enabled");
2801                 sc->flags &= ~BNX2X_MF_FUNC_DIS;
2802         }
2803 }
2804
2805 /* acquire split MCP access lock register */
2806 static int bnx2x_acquire_alr(struct bnx2x_softc *sc)
2807 {
2808         uint32_t j, val;
2809
2810         for (j = 0; j < 1000; j++) {
2811                 val = (1UL << 31);
2812                 REG_WR(sc, GRCBASE_MCP + 0x9c, val);
2813                 val = REG_RD(sc, GRCBASE_MCP + 0x9c);
2814                 if (val & (1L << 31))
2815                         break;
2816
2817                 DELAY(5000);
2818         }
2819
2820         if (!(val & (1L << 31))) {
2821                 PMD_DRV_LOG(NOTICE, "Cannot acquire MCP access lock register");
2822                 return -1;
2823         }
2824
2825         return 0;
2826 }
2827
2828 /* release split MCP access lock register */
2829 static void bnx2x_release_alr(struct bnx2x_softc *sc)
2830 {
2831         REG_WR(sc, GRCBASE_MCP + 0x9c, 0);
2832 }
2833
2834 static void bnx2x_fan_failure(struct bnx2x_softc *sc)
2835 {
2836         int port = SC_PORT(sc);
2837         uint32_t ext_phy_config;
2838
2839         /* mark the failure */
2840         ext_phy_config =
2841             SHMEM_RD(sc, dev_info.port_hw_config[port].external_phy_config);
2842
2843         ext_phy_config &= ~PORT_HW_CFG_XGXS_EXT_PHY_TYPE_MASK;
2844         ext_phy_config |= PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE;
2845         SHMEM_WR(sc, dev_info.port_hw_config[port].external_phy_config,
2846                  ext_phy_config);
2847
2848         /* log the failure */
2849         PMD_DRV_LOG(INFO,
2850                     "Fan Failure has caused the driver to shutdown "
2851                     "the card to prevent permanent damage. "
2852                     "Please contact OEM Support for assistance");
2853
2854         rte_panic("Schedule task to handle fan failure");
2855 }
2856
2857 /* this function is called upon a link interrupt */
2858 static void bnx2x_link_attn(struct bnx2x_softc *sc)
2859 {
2860         uint32_t pause_enabled = 0;
2861         struct host_port_stats *pstats;
2862         int cmng_fns;
2863
2864         /* Make sure that we are synced with the current statistics */
2865         bnx2x_stats_handle(sc, STATS_EVENT_STOP);
2866
2867         elink_link_update(&sc->link_params, &sc->link_vars);
2868
2869         if (sc->link_vars.link_up) {
2870
2871                 /* dropless flow control */
2872                 if (sc->dropless_fc) {
2873                         pause_enabled = 0;
2874
2875                         if (sc->link_vars.flow_ctrl & ELINK_FLOW_CTRL_TX) {
2876                                 pause_enabled = 1;
2877                         }
2878
2879                         REG_WR(sc,
2880                                (BAR_USTRORM_INTMEM +
2881                                 USTORM_ETH_PAUSE_ENABLED_OFFSET(SC_PORT(sc))),
2882                                pause_enabled);
2883                 }
2884
2885                 if (sc->link_vars.mac_type != ELINK_MAC_TYPE_EMAC) {
2886                         pstats = BNX2X_SP(sc, port_stats);
2887                         /* reset old mac stats */
2888                         memset(&(pstats->mac_stx[0]), 0,
2889                                sizeof(struct mac_stx));
2890                 }
2891
2892                 if (sc->state == BNX2X_STATE_OPEN) {
2893                         bnx2x_stats_handle(sc, STATS_EVENT_LINK_UP);
2894                 }
2895         }
2896
2897         if (sc->link_vars.link_up && sc->link_vars.line_speed) {
2898                 cmng_fns = bnx2x_get_cmng_fns_mode(sc);
2899
2900                 if (cmng_fns != CMNG_FNS_NONE) {
2901                         bnx2x_cmng_fns_init(sc, FALSE, cmng_fns);
2902                         storm_memset_cmng(sc, &sc->cmng, SC_PORT(sc));
2903                 }
2904         }
2905
2906         bnx2x_link_report(sc);
2907
2908         if (IS_MF(sc)) {
2909                 bnx2x_link_sync_notify(sc);
2910         }
2911 }
2912
2913 static void bnx2x_attn_int_asserted(struct bnx2x_softc *sc, uint32_t asserted)
2914 {
2915         int port = SC_PORT(sc);
2916         uint32_t aeu_addr = port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 :
2917             MISC_REG_AEU_MASK_ATTN_FUNC_0;
2918         uint32_t nig_int_mask_addr = port ? NIG_REG_MASK_INTERRUPT_PORT1 :
2919             NIG_REG_MASK_INTERRUPT_PORT0;
2920         uint32_t aeu_mask;
2921         uint32_t nig_mask = 0;
2922         uint32_t reg_addr;
2923         uint32_t igu_acked;
2924         uint32_t cnt;
2925
2926         if (sc->attn_state & asserted) {
2927                 PMD_DRV_LOG(ERR, "IGU ERROR attn=0x%08x", asserted);
2928         }
2929
2930         bnx2x_acquire_hw_lock(sc, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
2931
2932         aeu_mask = REG_RD(sc, aeu_addr);
2933
2934         aeu_mask &= ~(asserted & 0x3ff);
2935
2936         REG_WR(sc, aeu_addr, aeu_mask);
2937
2938         bnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
2939
2940         sc->attn_state |= asserted;
2941
2942         if (asserted & ATTN_HARD_WIRED_MASK) {
2943                 if (asserted & ATTN_NIG_FOR_FUNC) {
2944
2945                         /* save nig interrupt mask */
2946                         nig_mask = REG_RD(sc, nig_int_mask_addr);
2947
2948                         /* If nig_mask is not set, no need to call the update function */
2949                         if (nig_mask) {
2950                                 REG_WR(sc, nig_int_mask_addr, 0);
2951
2952                                 bnx2x_link_attn(sc);
2953                         }
2954
2955                         /* handle unicore attn? */
2956                 }
2957
2958                 if (asserted & ATTN_SW_TIMER_4_FUNC) {
2959                         PMD_DRV_LOG(DEBUG, "ATTN_SW_TIMER_4_FUNC!");
2960                 }
2961
2962                 if (asserted & GPIO_2_FUNC) {
2963                         PMD_DRV_LOG(DEBUG, "GPIO_2_FUNC!");
2964                 }
2965
2966                 if (asserted & GPIO_3_FUNC) {
2967                         PMD_DRV_LOG(DEBUG, "GPIO_3_FUNC!");
2968                 }
2969
2970                 if (asserted & GPIO_4_FUNC) {
2971                         PMD_DRV_LOG(DEBUG, "GPIO_4_FUNC!");
2972                 }
2973
2974                 if (port == 0) {
2975                         if (asserted & ATTN_GENERAL_ATTN_1) {
2976                                 PMD_DRV_LOG(DEBUG, "ATTN_GENERAL_ATTN_1!");
2977                                 REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_1, 0x0);
2978                         }
2979                         if (asserted & ATTN_GENERAL_ATTN_2) {
2980                                 PMD_DRV_LOG(DEBUG, "ATTN_GENERAL_ATTN_2!");
2981                                 REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_2, 0x0);
2982                         }
2983                         if (asserted & ATTN_GENERAL_ATTN_3) {
2984                                 PMD_DRV_LOG(DEBUG, "ATTN_GENERAL_ATTN_3!");
2985                                 REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_3, 0x0);
2986                         }
2987                 } else {
2988                         if (asserted & ATTN_GENERAL_ATTN_4) {
2989                                 PMD_DRV_LOG(DEBUG, "ATTN_GENERAL_ATTN_4!");
2990                                 REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_4, 0x0);
2991                         }
2992                         if (asserted & ATTN_GENERAL_ATTN_5) {
2993                                 PMD_DRV_LOG(DEBUG, "ATTN_GENERAL_ATTN_5!");
2994                                 REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_5, 0x0);
2995                         }
2996                         if (asserted & ATTN_GENERAL_ATTN_6) {
2997                                 PMD_DRV_LOG(DEBUG, "ATTN_GENERAL_ATTN_6!");
2998                                 REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_6, 0x0);
2999                         }
3000                 }
3001         }
3002         /* hardwired */
3003         if (sc->devinfo.int_block == INT_BLOCK_HC) {
3004                 reg_addr =
3005                     (HC_REG_COMMAND_REG + port * 32 +
3006                      COMMAND_REG_ATTN_BITS_SET);
3007         } else {
3008                 reg_addr = (BAR_IGU_INTMEM + IGU_CMD_ATTN_BIT_SET_UPPER * 8);
3009         }
3010
3011         PMD_DRV_LOG(DEBUG, "about to mask 0x%08x at %s addr 0x%08x",
3012                     asserted,
3013                     (sc->devinfo.int_block == INT_BLOCK_HC) ? "HC" : "IGU",
3014                     reg_addr);
3015         REG_WR(sc, reg_addr, asserted);
3016
3017         /* now set back the mask */
3018         if (asserted & ATTN_NIG_FOR_FUNC) {
3019                 /*
3020                  * Verify that IGU ack through BAR was written before restoring
3021                  * NIG mask. This loop should exit after 2-3 iterations max.
3022                  */
3023                 if (sc->devinfo.int_block != INT_BLOCK_HC) {
3024                         cnt = 0;
3025
3026                         do {
3027                                 igu_acked =
3028                                     REG_RD(sc, IGU_REG_ATTENTION_ACK_BITS);
3029                         } while (((igu_acked & ATTN_NIG_FOR_FUNC) == 0)
3030                                  && (++cnt < MAX_IGU_ATTN_ACK_TO));
3031
3032                         if (!igu_acked) {
3033                                 PMD_DRV_LOG(ERR,
3034                                             "Failed to verify IGU ack on time");
3035                         }
3036
3037                         mb();
3038                 }
3039
3040                 REG_WR(sc, nig_int_mask_addr, nig_mask);
3041
3042         }
3043 }
3044
3045 static void
3046 bnx2x_print_next_block(__rte_unused struct bnx2x_softc *sc, __rte_unused int idx,
3047                      __rte_unused const char *blk)
3048 {
3049         PMD_DRV_LOG(INFO, "%s%s", idx ? ", " : "", blk);
3050 }
3051
3052 static int
3053 bnx2x_check_blocks_with_parity0(struct bnx2x_softc *sc, uint32_t sig, int par_num,
3054                               uint8_t print)
3055 {
3056         uint32_t cur_bit = 0;
3057         int i = 0;
3058
3059         for (i = 0; sig; i++) {
3060                 cur_bit = ((uint32_t) 0x1 << i);
3061                 if (sig & cur_bit) {
3062                         switch (cur_bit) {
3063                         case AEU_INPUTS_ATTN_BITS_BRB_PARITY_ERROR:
3064                                 if (print)
3065                                         bnx2x_print_next_block(sc, par_num++,
3066                                                              "BRB");
3067                                 break;
3068                         case AEU_INPUTS_ATTN_BITS_PARSER_PARITY_ERROR:
3069                                 if (print)
3070                                         bnx2x_print_next_block(sc, par_num++,
3071                                                              "PARSER");
3072                                 break;
3073                         case AEU_INPUTS_ATTN_BITS_TSDM_PARITY_ERROR:
3074                                 if (print)
3075                                         bnx2x_print_next_block(sc, par_num++,
3076                                                              "TSDM");
3077                                 break;
3078                         case AEU_INPUTS_ATTN_BITS_SEARCHER_PARITY_ERROR:
3079                                 if (print)
3080                                         bnx2x_print_next_block(sc, par_num++,
3081                                                              "SEARCHER");
3082                                 break;
3083                         case AEU_INPUTS_ATTN_BITS_TCM_PARITY_ERROR:
3084                                 if (print)
3085                                         bnx2x_print_next_block(sc, par_num++,
3086                                                              "TCM");
3087                                 break;
3088                         case AEU_INPUTS_ATTN_BITS_TSEMI_PARITY_ERROR:
3089                                 if (print)
3090                                         bnx2x_print_next_block(sc, par_num++,
3091                                                              "TSEMI");
3092                                 break;
3093                         case AEU_INPUTS_ATTN_BITS_PBCLIENT_PARITY_ERROR:
3094                                 if (print)
3095                                         bnx2x_print_next_block(sc, par_num++,
3096                                                              "XPB");
3097                                 break;
3098                         }
3099
3100                         /* Clear the bit */
3101                         sig &= ~cur_bit;
3102                 }
3103         }
3104
3105         return par_num;
3106 }
3107
3108 static int
3109 bnx2x_check_blocks_with_parity1(struct bnx2x_softc *sc, uint32_t sig, int par_num,
3110                               uint8_t * global, uint8_t print)
3111 {
3112         int i = 0;
3113         uint32_t cur_bit = 0;
3114         for (i = 0; sig; i++) {
3115                 cur_bit = ((uint32_t) 0x1 << i);
3116                 if (sig & cur_bit) {
3117                         switch (cur_bit) {
3118                         case AEU_INPUTS_ATTN_BITS_PBF_PARITY_ERROR:
3119                                 if (print)
3120                                         bnx2x_print_next_block(sc, par_num++,
3121                                                              "PBF");
3122                                 break;
3123                         case AEU_INPUTS_ATTN_BITS_QM_PARITY_ERROR:
3124                                 if (print)
3125                                         bnx2x_print_next_block(sc, par_num++,
3126                                                              "QM");
3127                                 break;
3128                         case AEU_INPUTS_ATTN_BITS_TIMERS_PARITY_ERROR:
3129                                 if (print)
3130                                         bnx2x_print_next_block(sc, par_num++,
3131                                                              "TM");
3132                                 break;
3133                         case AEU_INPUTS_ATTN_BITS_XSDM_PARITY_ERROR:
3134                                 if (print)
3135                                         bnx2x_print_next_block(sc, par_num++,
3136                                                              "XSDM");
3137                                 break;
3138                         case AEU_INPUTS_ATTN_BITS_XCM_PARITY_ERROR:
3139                                 if (print)
3140                                         bnx2x_print_next_block(sc, par_num++,
3141                                                              "XCM");
3142                                 break;
3143                         case AEU_INPUTS_ATTN_BITS_XSEMI_PARITY_ERROR:
3144                                 if (print)
3145                                         bnx2x_print_next_block(sc, par_num++,
3146                                                              "XSEMI");
3147                                 break;
3148                         case AEU_INPUTS_ATTN_BITS_DOORBELLQ_PARITY_ERROR:
3149                                 if (print)
3150                                         bnx2x_print_next_block(sc, par_num++,
3151                                                              "DOORBELLQ");
3152                                 break;
3153                         case AEU_INPUTS_ATTN_BITS_NIG_PARITY_ERROR:
3154                                 if (print)
3155                                         bnx2x_print_next_block(sc, par_num++,
3156                                                              "NIG");
3157                                 break;
3158                         case AEU_INPUTS_ATTN_BITS_VAUX_PCI_CORE_PARITY_ERROR:
3159                                 if (print)
3160                                         bnx2x_print_next_block(sc, par_num++,
3161                                                              "VAUX PCI CORE");
3162                                 *global = TRUE;
3163                                 break;
3164                         case AEU_INPUTS_ATTN_BITS_DEBUG_PARITY_ERROR:
3165                                 if (print)
3166                                         bnx2x_print_next_block(sc, par_num++,
3167                                                              "DEBUG");
3168                                 break;
3169                         case AEU_INPUTS_ATTN_BITS_USDM_PARITY_ERROR:
3170                                 if (print)
3171                                         bnx2x_print_next_block(sc, par_num++,
3172                                                              "USDM");
3173                                 break;
3174                         case AEU_INPUTS_ATTN_BITS_UCM_PARITY_ERROR:
3175                                 if (print)
3176                                         bnx2x_print_next_block(sc, par_num++,
3177                                                              "UCM");
3178                                 break;
3179                         case AEU_INPUTS_ATTN_BITS_USEMI_PARITY_ERROR:
3180                                 if (print)
3181                                         bnx2x_print_next_block(sc, par_num++,
3182                                                              "USEMI");
3183                                 break;
3184                         case AEU_INPUTS_ATTN_BITS_UPB_PARITY_ERROR:
3185                                 if (print)
3186                                         bnx2x_print_next_block(sc, par_num++,
3187                                                              "UPB");
3188                                 break;
3189                         case AEU_INPUTS_ATTN_BITS_CSDM_PARITY_ERROR:
3190                                 if (print)
3191                                         bnx2x_print_next_block(sc, par_num++,
3192                                                              "CSDM");
3193                                 break;
3194                         case AEU_INPUTS_ATTN_BITS_CCM_PARITY_ERROR:
3195                                 if (print)
3196                                         bnx2x_print_next_block(sc, par_num++,
3197                                                              "CCM");
3198                                 break;
3199                         }
3200
3201                         /* Clear the bit */
3202                         sig &= ~cur_bit;
3203                 }
3204         }
3205
3206         return par_num;
3207 }
3208
3209 static int
3210 bnx2x_check_blocks_with_parity2(struct bnx2x_softc *sc, uint32_t sig, int par_num,
3211                               uint8_t print)
3212 {
3213         uint32_t cur_bit = 0;
3214         int i = 0;
3215
3216         for (i = 0; sig; i++) {
3217                 cur_bit = ((uint32_t) 0x1 << i);
3218                 if (sig & cur_bit) {
3219                         switch (cur_bit) {
3220                         case AEU_INPUTS_ATTN_BITS_CSEMI_PARITY_ERROR:
3221                                 if (print)
3222                                         bnx2x_print_next_block(sc, par_num++,
3223                                                              "CSEMI");
3224                                 break;
3225                         case AEU_INPUTS_ATTN_BITS_PXP_PARITY_ERROR:
3226                                 if (print)
3227                                         bnx2x_print_next_block(sc, par_num++,
3228                                                              "PXP");
3229                                 break;
3230                         case AEU_IN_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR:
3231                                 if (print)
3232                                         bnx2x_print_next_block(sc, par_num++,
3233                                                              "PXPPCICLOCKCLIENT");
3234                                 break;
3235                         case AEU_INPUTS_ATTN_BITS_CFC_PARITY_ERROR:
3236                                 if (print)
3237                                         bnx2x_print_next_block(sc, par_num++,
3238                                                              "CFC");
3239                                 break;
3240                         case AEU_INPUTS_ATTN_BITS_CDU_PARITY_ERROR:
3241                                 if (print)
3242                                         bnx2x_print_next_block(sc, par_num++,
3243                                                              "CDU");
3244                                 break;
3245                         case AEU_INPUTS_ATTN_BITS_DMAE_PARITY_ERROR:
3246                                 if (print)
3247                                         bnx2x_print_next_block(sc, par_num++,
3248                                                              "DMAE");
3249                                 break;
3250                         case AEU_INPUTS_ATTN_BITS_IGU_PARITY_ERROR:
3251                                 if (print)
3252                                         bnx2x_print_next_block(sc, par_num++,
3253                                                              "IGU");
3254                                 break;
3255                         case AEU_INPUTS_ATTN_BITS_MISC_PARITY_ERROR:
3256                                 if (print)
3257                                         bnx2x_print_next_block(sc, par_num++,
3258                                                              "MISC");
3259                                 break;
3260                         }
3261
3262                         /* Clear the bit */
3263                         sig &= ~cur_bit;
3264                 }
3265         }
3266
3267         return par_num;
3268 }
3269
3270 static int
3271 bnx2x_check_blocks_with_parity3(struct bnx2x_softc *sc, uint32_t sig, int par_num,
3272                               uint8_t * global, uint8_t print)
3273 {
3274         uint32_t cur_bit = 0;
3275         int i = 0;
3276
3277         for (i = 0; sig; i++) {
3278                 cur_bit = ((uint32_t) 0x1 << i);
3279                 if (sig & cur_bit) {
3280                         switch (cur_bit) {
3281                         case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_ROM_PARITY:
3282                                 if (print)
3283                                         bnx2x_print_next_block(sc, par_num++,
3284                                                              "MCP ROM");
3285                                 *global = TRUE;
3286                                 break;
3287                         case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_RX_PARITY:
3288                                 if (print)
3289                                         bnx2x_print_next_block(sc, par_num++,
3290                                                              "MCP UMP RX");
3291                                 *global = TRUE;
3292                                 break;
3293                         case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_TX_PARITY:
3294                                 if (print)
3295                                         bnx2x_print_next_block(sc, par_num++,
3296                                                              "MCP UMP TX");
3297                                 *global = TRUE;
3298                                 break;
3299                         case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_SCPAD_PARITY:
3300                                 if (print)
3301                                         bnx2x_print_next_block(sc, par_num++,
3302                                                              "MCP SCPAD");
3303                                 *global = TRUE;
3304                                 break;
3305                         }
3306
3307                         /* Clear the bit */
3308                         sig &= ~cur_bit;
3309                 }
3310         }
3311
3312         return par_num;
3313 }
3314
3315 static int
3316 bnx2x_check_blocks_with_parity4(struct bnx2x_softc *sc, uint32_t sig, int par_num,
3317                               uint8_t print)
3318 {
3319         uint32_t cur_bit = 0;
3320         int i = 0;
3321
3322         for (i = 0; sig; i++) {
3323                 cur_bit = ((uint32_t) 0x1 << i);
3324                 if (sig & cur_bit) {
3325                         switch (cur_bit) {
3326                         case AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR:
3327                                 if (print)
3328                                         bnx2x_print_next_block(sc, par_num++,
3329                                                              "PGLUE_B");
3330                                 break;
3331                         case AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR:
3332                                 if (print)
3333                                         bnx2x_print_next_block(sc, par_num++,
3334                                                              "ATC");
3335                                 break;
3336                         }
3337
3338                         /* Clear the bit */
3339                         sig &= ~cur_bit;
3340                 }
3341         }
3342
3343         return par_num;
3344 }
3345
3346 static uint8_t
3347 bnx2x_parity_attn(struct bnx2x_softc *sc, uint8_t * global, uint8_t print,
3348                 uint32_t * sig)
3349 {
3350         int par_num = 0;
3351
3352         if ((sig[0] & HW_PRTY_ASSERT_SET_0) ||
3353             (sig[1] & HW_PRTY_ASSERT_SET_1) ||
3354             (sig[2] & HW_PRTY_ASSERT_SET_2) ||
3355             (sig[3] & HW_PRTY_ASSERT_SET_3) ||
3356             (sig[4] & HW_PRTY_ASSERT_SET_4)) {
3357                 PMD_DRV_LOG(ERR,
3358                             "Parity error: HW block parity attention:"
3359                             "[0]:0x%08x [1]:0x%08x [2]:0x%08x [3]:0x%08x [4]:0x%08x",
3360                             (uint32_t) (sig[0] & HW_PRTY_ASSERT_SET_0),
3361                             (uint32_t) (sig[1] & HW_PRTY_ASSERT_SET_1),
3362                             (uint32_t) (sig[2] & HW_PRTY_ASSERT_SET_2),
3363                             (uint32_t) (sig[3] & HW_PRTY_ASSERT_SET_3),
3364                             (uint32_t) (sig[4] & HW_PRTY_ASSERT_SET_4));
3365
3366                 if (print)
3367                         PMD_DRV_LOG(INFO, "Parity errors detected in blocks: ");
3368
3369                 par_num =
3370                     bnx2x_check_blocks_with_parity0(sc, sig[0] &
3371                                                   HW_PRTY_ASSERT_SET_0,
3372                                                   par_num, print);
3373                 par_num =
3374                     bnx2x_check_blocks_with_parity1(sc, sig[1] &
3375                                                   HW_PRTY_ASSERT_SET_1,
3376                                                   par_num, global, print);
3377                 par_num =
3378                     bnx2x_check_blocks_with_parity2(sc, sig[2] &
3379                                                   HW_PRTY_ASSERT_SET_2,
3380                                                   par_num, print);
3381                 par_num =
3382                     bnx2x_check_blocks_with_parity3(sc, sig[3] &
3383                                                   HW_PRTY_ASSERT_SET_3,
3384                                                   par_num, global, print);
3385                 par_num =
3386                     bnx2x_check_blocks_with_parity4(sc, sig[4] &
3387                                                   HW_PRTY_ASSERT_SET_4,
3388                                                   par_num, print);
3389
3390                 if (print)
3391                         PMD_DRV_LOG(INFO, "");
3392
3393                 return TRUE;
3394         }
3395
3396         return FALSE;
3397 }
3398
3399 static uint8_t
3400 bnx2x_chk_parity_attn(struct bnx2x_softc *sc, uint8_t * global, uint8_t print)
3401 {
3402         struct attn_route attn = { {0} };
3403         int port = SC_PORT(sc);
3404
3405         attn.sig[0] = REG_RD(sc, MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 + port * 4);
3406         attn.sig[1] = REG_RD(sc, MISC_REG_AEU_AFTER_INVERT_2_FUNC_0 + port * 4);
3407         attn.sig[2] = REG_RD(sc, MISC_REG_AEU_AFTER_INVERT_3_FUNC_0 + port * 4);
3408         attn.sig[3] = REG_RD(sc, MISC_REG_AEU_AFTER_INVERT_4_FUNC_0 + port * 4);
3409
3410         if (!CHIP_IS_E1x(sc))
3411                 attn.sig[4] =
3412                     REG_RD(sc, MISC_REG_AEU_AFTER_INVERT_5_FUNC_0 + port * 4);
3413
3414         return bnx2x_parity_attn(sc, global, print, attn.sig);
3415 }
3416
3417 static void bnx2x_attn_int_deasserted4(struct bnx2x_softc *sc, uint32_t attn)
3418 {
3419         uint32_t val;
3420
3421         if (attn & AEU_INPUTS_ATTN_BITS_PGLUE_HW_INTERRUPT) {
3422                 val = REG_RD(sc, PGLUE_B_REG_PGLUE_B_INT_STS_CLR);
3423                 PMD_DRV_LOG(INFO, "ERROR: PGLUE hw attention 0x%08x", val);
3424                 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_ADDRESS_ERROR)
3425                         PMD_DRV_LOG(INFO,
3426                                     "ERROR: PGLUE_B_PGLUE_B_INT_STS_REG_ADDRESS_ERROR");
3427                 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_INCORRECT_RCV_BEHAVIOR)
3428                         PMD_DRV_LOG(INFO,
3429                                     "ERROR: PGLUE_B_PGLUE_B_INT_STS_REG_INCORRECT_RCV_BEHAVIOR");
3430                 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_WAS_ERROR_ATTN)
3431                         PMD_DRV_LOG(INFO,
3432                                     "ERROR: PGLUE_B_PGLUE_B_INT_STS_REG_WAS_ERROR_ATTN");
3433                 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_VF_LENGTH_VIOLATION_ATTN)
3434                         PMD_DRV_LOG(INFO,
3435                                     "ERROR: PGLUE_B_PGLUE_B_INT_STS_REG_VF_LENGTH_VIOLATION_ATTN");
3436                 if (val &
3437                     PGLUE_B_PGLUE_B_INT_STS_REG_VF_GRC_SPACE_VIOLATION_ATTN)
3438                         PMD_DRV_LOG(INFO,
3439                                     "ERROR: PGLUE_B_PGLUE_B_INT_STS_REG_VF_GRC_SPACE_VIOLATION_ATTN");
3440                 if (val &
3441                     PGLUE_B_PGLUE_B_INT_STS_REG_VF_MSIX_BAR_VIOLATION_ATTN)
3442                         PMD_DRV_LOG(INFO,
3443                                     "ERROR: PGLUE_B_PGLUE_B_INT_STS_REG_VF_MSIX_BAR_VIOLATION_ATTN");
3444                 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_ERROR_ATTN)
3445                         PMD_DRV_LOG(INFO,
3446                                     "ERROR: PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_ERROR_ATTN");
3447                 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_IN_TWO_RCBS_ATTN)
3448                         PMD_DRV_LOG(INFO,
3449                                     "ERROR: PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_IN_TWO_RCBS_ATTN");
3450                 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_CSSNOOP_FIFO_OVERFLOW)
3451                         PMD_DRV_LOG(INFO,
3452                                     "ERROR: PGLUE_B_PGLUE_B_INT_STS_REG_CSSNOOP_FIFO_OVERFLOW");
3453         }
3454
3455         if (attn & AEU_INPUTS_ATTN_BITS_ATC_HW_INTERRUPT) {
3456                 val = REG_RD(sc, ATC_REG_ATC_INT_STS_CLR);
3457                 PMD_DRV_LOG(INFO, "ERROR: ATC hw attention 0x%08x", val);
3458                 if (val & ATC_ATC_INT_STS_REG_ADDRESS_ERROR)
3459                         PMD_DRV_LOG(INFO,
3460                                     "ERROR: ATC_ATC_INT_STS_REG_ADDRESS_ERROR");
3461                 if (val & ATC_ATC_INT_STS_REG_ATC_TCPL_TO_NOT_PEND)
3462                         PMD_DRV_LOG(INFO,
3463                                     "ERROR: ATC_ATC_INT_STS_REG_ATC_TCPL_TO_NOT_PEND");
3464                 if (val & ATC_ATC_INT_STS_REG_ATC_GPA_MULTIPLE_HITS)
3465                         PMD_DRV_LOG(INFO,
3466                                     "ERROR: ATC_ATC_INT_STS_REG_ATC_GPA_MULTIPLE_HITS");
3467                 if (val & ATC_ATC_INT_STS_REG_ATC_RCPL_TO_EMPTY_CNT)
3468                         PMD_DRV_LOG(INFO,
3469                                     "ERROR: ATC_ATC_INT_STS_REG_ATC_RCPL_TO_EMPTY_CNT");
3470                 if (val & ATC_ATC_INT_STS_REG_ATC_TCPL_ERROR)
3471                         PMD_DRV_LOG(INFO,
3472                                     "ERROR: ATC_ATC_INT_STS_REG_ATC_TCPL_ERROR");
3473                 if (val & ATC_ATC_INT_STS_REG_ATC_IREQ_LESS_THAN_STU)
3474                         PMD_DRV_LOG(INFO,
3475                                     "ERROR: ATC_ATC_INT_STS_REG_ATC_IREQ_LESS_THAN_STU");
3476         }
3477
3478         if (attn & (AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR |
3479                     AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR)) {
3480                 PMD_DRV_LOG(INFO,
3481                             "ERROR: FATAL parity attention set4 0x%08x",
3482                             (uint32_t) (attn &
3483                                         (AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR
3484                                          |
3485                                          AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR)));
3486         }
3487 }
3488
3489 static void bnx2x_e1h_disable(struct bnx2x_softc *sc)
3490 {
3491         int port = SC_PORT(sc);
3492
3493         REG_WR(sc, NIG_REG_LLH0_FUNC_EN + port * 8, 0);
3494 }
3495
3496 static void bnx2x_e1h_enable(struct bnx2x_softc *sc)
3497 {
3498         int port = SC_PORT(sc);
3499
3500         REG_WR(sc, NIG_REG_LLH0_FUNC_EN + port * 8, 1);
3501 }
3502
3503 /*
3504  * called due to MCP event (on pmf):
3505  *   reread new bandwidth configuration
3506  *   configure FW
3507  *   notify others function about the change
3508  */
3509 static void bnx2x_config_mf_bw(struct bnx2x_softc *sc)
3510 {
3511         if (sc->link_vars.link_up) {
3512                 bnx2x_cmng_fns_init(sc, TRUE, CMNG_FNS_MINMAX);
3513                 bnx2x_link_sync_notify(sc);
3514         }
3515
3516         storm_memset_cmng(sc, &sc->cmng, SC_PORT(sc));
3517 }
3518
3519 static void bnx2x_set_mf_bw(struct bnx2x_softc *sc)
3520 {
3521         bnx2x_config_mf_bw(sc);
3522         bnx2x_fw_command(sc, DRV_MSG_CODE_SET_MF_BW_ACK, 0);
3523 }
3524
3525 static void bnx2x_handle_eee_event(struct bnx2x_softc *sc)
3526 {
3527         bnx2x_fw_command(sc, DRV_MSG_CODE_EEE_RESULTS_ACK, 0);
3528 }
3529
3530 #define DRV_INFO_ETH_STAT_NUM_MACS_REQUIRED 3
3531
3532 static void bnx2x_drv_info_ether_stat(struct bnx2x_softc *sc)
3533 {
3534         struct eth_stats_info *ether_stat = &sc->sp->drv_info_to_mcp.ether_stat;
3535
3536         strncpy(ether_stat->version, BNX2X_DRIVER_VERSION,
3537                 ETH_STAT_INFO_VERSION_LEN);
3538
3539         sc->sp_objs[0].mac_obj.get_n_elements(sc, &sc->sp_objs[0].mac_obj,
3540                                               DRV_INFO_ETH_STAT_NUM_MACS_REQUIRED,
3541                                               ether_stat->mac_local + MAC_PAD,
3542                                               MAC_PAD, ETH_ALEN);
3543
3544         ether_stat->mtu_size = sc->mtu;
3545
3546         ether_stat->feature_flags |= FEATURE_ETH_CHKSUM_OFFLOAD_MASK;
3547         ether_stat->promiscuous_mode = 0;       // (flags & PROMISC) ? 1 : 0;
3548
3549         ether_stat->txq_size = sc->tx_ring_size;
3550         ether_stat->rxq_size = sc->rx_ring_size;
3551 }
3552
3553 static void bnx2x_handle_drv_info_req(struct bnx2x_softc *sc)
3554 {
3555         enum drv_info_opcode op_code;
3556         uint32_t drv_info_ctl = SHMEM2_RD(sc, drv_info_control);
3557
3558         /* if drv_info version supported by MFW doesn't match - send NACK */
3559         if ((drv_info_ctl & DRV_INFO_CONTROL_VER_MASK) != DRV_INFO_CUR_VER) {
3560                 bnx2x_fw_command(sc, DRV_MSG_CODE_DRV_INFO_NACK, 0);
3561                 return;
3562         }
3563
3564         op_code = ((drv_info_ctl & DRV_INFO_CONTROL_OP_CODE_MASK) >>
3565                    DRV_INFO_CONTROL_OP_CODE_SHIFT);
3566
3567         memset(&sc->sp->drv_info_to_mcp, 0, sizeof(union drv_info_to_mcp));
3568
3569         switch (op_code) {
3570         case ETH_STATS_OPCODE:
3571                 bnx2x_drv_info_ether_stat(sc);
3572                 break;
3573         case FCOE_STATS_OPCODE:
3574         case ISCSI_STATS_OPCODE:
3575         default:
3576                 /* if op code isn't supported - send NACK */
3577                 bnx2x_fw_command(sc, DRV_MSG_CODE_DRV_INFO_NACK, 0);
3578                 return;
3579         }
3580
3581         /*
3582          * If we got drv_info attn from MFW then these fields are defined in
3583          * shmem2 for sure
3584          */
3585         SHMEM2_WR(sc, drv_info_host_addr_lo,
3586                   U64_LO(BNX2X_SP_MAPPING(sc, drv_info_to_mcp)));
3587         SHMEM2_WR(sc, drv_info_host_addr_hi,
3588                   U64_HI(BNX2X_SP_MAPPING(sc, drv_info_to_mcp)));
3589
3590         bnx2x_fw_command(sc, DRV_MSG_CODE_DRV_INFO_ACK, 0);
3591 }
3592
3593 static void bnx2x_dcc_event(struct bnx2x_softc *sc, uint32_t dcc_event)
3594 {
3595         if (dcc_event & DRV_STATUS_DCC_DISABLE_ENABLE_PF) {
3596 /*
3597  * This is the only place besides the function initialization
3598  * where the sc->flags can change so it is done without any
3599  * locks
3600  */
3601                 if (sc->devinfo.
3602                     mf_info.mf_config[SC_VN(sc)] & FUNC_MF_CFG_FUNC_DISABLED) {
3603                         PMD_DRV_LOG(DEBUG, "mf_cfg function disabled");
3604                         sc->flags |= BNX2X_MF_FUNC_DIS;
3605                         bnx2x_e1h_disable(sc);
3606                 } else {
3607                         PMD_DRV_LOG(DEBUG, "mf_cfg function enabled");
3608                         sc->flags &= ~BNX2X_MF_FUNC_DIS;
3609                         bnx2x_e1h_enable(sc);
3610                 }
3611                 dcc_event &= ~DRV_STATUS_DCC_DISABLE_ENABLE_PF;
3612         }
3613
3614         if (dcc_event & DRV_STATUS_DCC_BANDWIDTH_ALLOCATION) {
3615                 bnx2x_config_mf_bw(sc);
3616                 dcc_event &= ~DRV_STATUS_DCC_BANDWIDTH_ALLOCATION;
3617         }
3618
3619         /* Report results to MCP */
3620         if (dcc_event)
3621                 bnx2x_fw_command(sc, DRV_MSG_CODE_DCC_FAILURE, 0);
3622         else
3623                 bnx2x_fw_command(sc, DRV_MSG_CODE_DCC_OK, 0);
3624 }
3625
3626 static void bnx2x_pmf_update(struct bnx2x_softc *sc)
3627 {
3628         int port = SC_PORT(sc);
3629         uint32_t val;
3630
3631         sc->port.pmf = 1;
3632
3633         /*
3634          * We need the mb() to ensure the ordering between the writing to
3635          * sc->port.pmf here and reading it from the bnx2x_periodic_task().
3636          */
3637         mb();
3638
3639         /* enable nig attention */
3640         val = (0xff0f | (1 << (SC_VN(sc) + 4)));
3641         if (sc->devinfo.int_block == INT_BLOCK_HC) {
3642                 REG_WR(sc, HC_REG_TRAILING_EDGE_0 + port * 8, val);
3643                 REG_WR(sc, HC_REG_LEADING_EDGE_0 + port * 8, val);
3644         } else if (!CHIP_IS_E1x(sc)) {
3645                 REG_WR(sc, IGU_REG_TRAILING_EDGE_LATCH, val);
3646                 REG_WR(sc, IGU_REG_LEADING_EDGE_LATCH, val);
3647         }
3648
3649         bnx2x_stats_handle(sc, STATS_EVENT_PMF);
3650 }
3651
3652 static int bnx2x_mc_assert(struct bnx2x_softc *sc)
3653 {
3654         char last_idx;
3655         int i, rc = 0;
3656         __rte_unused uint32_t row0, row1, row2, row3;
3657
3658         /* XSTORM */
3659         last_idx =
3660             REG_RD8(sc, BAR_XSTRORM_INTMEM + XSTORM_ASSERT_LIST_INDEX_OFFSET);
3661         if (last_idx)
3662                 PMD_DRV_LOG(ERR, "XSTORM_ASSERT_LIST_INDEX 0x%x", last_idx);
3663
3664         /* print the asserts */
3665         for (i = 0; i < STORM_ASSERT_ARRAY_SIZE; i++) {
3666
3667                 row0 =
3668                     REG_RD(sc,
3669                            BAR_XSTRORM_INTMEM + XSTORM_ASSERT_LIST_OFFSET(i));
3670                 row1 =
3671                     REG_RD(sc,
3672                            BAR_XSTRORM_INTMEM + XSTORM_ASSERT_LIST_OFFSET(i) +
3673                            4);
3674                 row2 =
3675                     REG_RD(sc,
3676                            BAR_XSTRORM_INTMEM + XSTORM_ASSERT_LIST_OFFSET(i) +
3677                            8);
3678                 row3 =
3679                     REG_RD(sc,
3680                            BAR_XSTRORM_INTMEM + XSTORM_ASSERT_LIST_OFFSET(i) +
3681                            12);
3682
3683                 if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) {
3684                         PMD_DRV_LOG(ERR,
3685                                     "XSTORM_ASSERT_INDEX 0x%x = 0x%08x 0x%08x 0x%08x 0x%08x",
3686                                     i, row3, row2, row1, row0);
3687                         rc++;
3688                 } else {
3689                         break;
3690                 }
3691         }
3692
3693         /* TSTORM */
3694         last_idx =
3695             REG_RD8(sc, BAR_TSTRORM_INTMEM + TSTORM_ASSERT_LIST_INDEX_OFFSET);
3696         if (last_idx) {
3697                 PMD_DRV_LOG(ERR, "TSTORM_ASSERT_LIST_INDEX 0x%x", last_idx);
3698         }
3699
3700         /* print the asserts */
3701         for (i = 0; i < STORM_ASSERT_ARRAY_SIZE; i++) {
3702
3703                 row0 =
3704                     REG_RD(sc,
3705                            BAR_TSTRORM_INTMEM + TSTORM_ASSERT_LIST_OFFSET(i));
3706                 row1 =
3707                     REG_RD(sc,
3708                            BAR_TSTRORM_INTMEM + TSTORM_ASSERT_LIST_OFFSET(i) +
3709                            4);
3710                 row2 =
3711                     REG_RD(sc,
3712                            BAR_TSTRORM_INTMEM + TSTORM_ASSERT_LIST_OFFSET(i) +
3713                            8);
3714                 row3 =
3715                     REG_RD(sc,
3716                            BAR_TSTRORM_INTMEM + TSTORM_ASSERT_LIST_OFFSET(i) +
3717                            12);
3718
3719                 if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) {
3720                         PMD_DRV_LOG(ERR,
3721                                     "TSTORM_ASSERT_INDEX 0x%x = 0x%08x 0x%08x 0x%08x 0x%08x",
3722                                     i, row3, row2, row1, row0);
3723                         rc++;
3724                 } else {
3725                         break;
3726                 }
3727         }
3728
3729         /* CSTORM */
3730         last_idx =
3731             REG_RD8(sc, BAR_CSTRORM_INTMEM + CSTORM_ASSERT_LIST_INDEX_OFFSET);
3732         if (last_idx) {
3733                 PMD_DRV_LOG(ERR, "CSTORM_ASSERT_LIST_INDEX 0x%x", last_idx);
3734         }
3735
3736         /* print the asserts */
3737         for (i = 0; i < STORM_ASSERT_ARRAY_SIZE; i++) {
3738
3739                 row0 =
3740                     REG_RD(sc,
3741                            BAR_CSTRORM_INTMEM + CSTORM_ASSERT_LIST_OFFSET(i));
3742                 row1 =
3743                     REG_RD(sc,
3744                            BAR_CSTRORM_INTMEM + CSTORM_ASSERT_LIST_OFFSET(i) +
3745                            4);
3746                 row2 =
3747                     REG_RD(sc,
3748                            BAR_CSTRORM_INTMEM + CSTORM_ASSERT_LIST_OFFSET(i) +
3749                            8);
3750                 row3 =
3751                     REG_RD(sc,
3752                            BAR_CSTRORM_INTMEM + CSTORM_ASSERT_LIST_OFFSET(i) +
3753                            12);
3754
3755                 if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) {
3756                         PMD_DRV_LOG(ERR,
3757                                     "CSTORM_ASSERT_INDEX 0x%x = 0x%08x 0x%08x 0x%08x 0x%08x",
3758                                     i, row3, row2, row1, row0);
3759                         rc++;
3760                 } else {
3761                         break;
3762                 }
3763         }
3764
3765         /* USTORM */
3766         last_idx =
3767             REG_RD8(sc, BAR_USTRORM_INTMEM + USTORM_ASSERT_LIST_INDEX_OFFSET);
3768         if (last_idx) {
3769                 PMD_DRV_LOG(ERR, "USTORM_ASSERT_LIST_INDEX 0x%x", last_idx);
3770         }
3771
3772         /* print the asserts */
3773         for (i = 0; i < STORM_ASSERT_ARRAY_SIZE; i++) {
3774
3775                 row0 =
3776                     REG_RD(sc,
3777                            BAR_USTRORM_INTMEM + USTORM_ASSERT_LIST_OFFSET(i));
3778                 row1 =
3779                     REG_RD(sc,
3780                            BAR_USTRORM_INTMEM + USTORM_ASSERT_LIST_OFFSET(i) +
3781                            4);
3782                 row2 =
3783                     REG_RD(sc,
3784                            BAR_USTRORM_INTMEM + USTORM_ASSERT_LIST_OFFSET(i) +
3785                            8);
3786                 row3 =
3787                     REG_RD(sc,
3788                            BAR_USTRORM_INTMEM + USTORM_ASSERT_LIST_OFFSET(i) +
3789                            12);
3790
3791                 if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) {
3792                         PMD_DRV_LOG(ERR,
3793                                     "USTORM_ASSERT_INDEX 0x%x = 0x%08x 0x%08x 0x%08x 0x%08x",
3794                                     i, row3, row2, row1, row0);
3795                         rc++;
3796                 } else {
3797                         break;
3798                 }
3799         }
3800
3801         return rc;
3802 }
3803
3804 static void bnx2x_attn_int_deasserted3(struct bnx2x_softc *sc, uint32_t attn)
3805 {
3806         int func = SC_FUNC(sc);
3807         uint32_t val;
3808
3809         if (attn & EVEREST_GEN_ATTN_IN_USE_MASK) {
3810
3811                 if (attn & BNX2X_PMF_LINK_ASSERT(sc)) {
3812
3813                         REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_12 + func * 4, 0);
3814                         bnx2x_read_mf_cfg(sc);
3815                         sc->devinfo.mf_info.mf_config[SC_VN(sc)] =
3816                             MFCFG_RD(sc,
3817                                      func_mf_config[SC_ABS_FUNC(sc)].config);
3818                         val =
3819                             SHMEM_RD(sc, func_mb[SC_FW_MB_IDX(sc)].drv_status);
3820
3821                         if (val & DRV_STATUS_DCC_EVENT_MASK)
3822                                 bnx2x_dcc_event(sc,
3823                                               (val &
3824                                                DRV_STATUS_DCC_EVENT_MASK));
3825
3826                         if (val & DRV_STATUS_SET_MF_BW)
3827                                 bnx2x_set_mf_bw(sc);
3828
3829                         if (val & DRV_STATUS_DRV_INFO_REQ)
3830                                 bnx2x_handle_drv_info_req(sc);
3831
3832                         if ((sc->port.pmf == 0) && (val & DRV_STATUS_PMF))
3833                                 bnx2x_pmf_update(sc);
3834
3835                         if (val & DRV_STATUS_EEE_NEGOTIATION_RESULTS)
3836                                 bnx2x_handle_eee_event(sc);
3837
3838                         if (sc->link_vars.periodic_flags &
3839                             ELINK_PERIODIC_FLAGS_LINK_EVENT) {
3840                                 /* sync with link */
3841                                 sc->link_vars.periodic_flags &=
3842                                     ~ELINK_PERIODIC_FLAGS_LINK_EVENT;
3843                                 if (IS_MF(sc)) {
3844                                         bnx2x_link_sync_notify(sc);
3845                                 }
3846                                 bnx2x_link_report(sc);
3847                         }
3848
3849                         /*
3850                          * Always call it here: bnx2x_link_report() will
3851                          * prevent the link indication duplication.
3852                          */
3853                         bnx2x_link_status_update(sc);
3854
3855                 } else if (attn & BNX2X_MC_ASSERT_BITS) {
3856
3857                         PMD_DRV_LOG(ERR, "MC assert!");
3858                         bnx2x_mc_assert(sc);
3859                         REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_10, 0);
3860                         REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_9, 0);
3861                         REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_8, 0);
3862                         REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_7, 0);
3863                         rte_panic("MC assert!");
3864
3865                 } else if (attn & BNX2X_MCP_ASSERT) {
3866
3867                         PMD_DRV_LOG(ERR, "MCP assert!");
3868                         REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_11, 0);
3869
3870                 } else {
3871                         PMD_DRV_LOG(ERR,
3872                                     "Unknown HW assert! (attn 0x%08x)", attn);
3873                 }
3874         }
3875
3876         if (attn & EVEREST_LATCHED_ATTN_IN_USE_MASK) {
3877                 PMD_DRV_LOG(ERR, "LATCHED attention 0x%08x (masked)", attn);
3878                 if (attn & BNX2X_GRC_TIMEOUT) {
3879                         val = REG_RD(sc, MISC_REG_GRC_TIMEOUT_ATTN);
3880                         PMD_DRV_LOG(ERR, "GRC time-out 0x%08x", val);
3881                 }
3882                 if (attn & BNX2X_GRC_RSV) {
3883                         val = REG_RD(sc, MISC_REG_GRC_RSV_ATTN);
3884                         PMD_DRV_LOG(ERR, "GRC reserved 0x%08x", val);
3885                 }
3886                 REG_WR(sc, MISC_REG_AEU_CLR_LATCH_SIGNAL, 0x7ff);
3887         }
3888 }
3889
3890 static void bnx2x_attn_int_deasserted2(struct bnx2x_softc *sc, uint32_t attn)
3891 {
3892         int port = SC_PORT(sc);
3893         int reg_offset;
3894         uint32_t val0, mask0, val1, mask1;
3895         uint32_t val;
3896
3897         if (attn & AEU_INPUTS_ATTN_BITS_CFC_HW_INTERRUPT) {
3898                 val = REG_RD(sc, CFC_REG_CFC_INT_STS_CLR);
3899                 PMD_DRV_LOG(ERR, "CFC hw attention 0x%08x", val);
3900 /* CFC error attention */
3901                 if (val & 0x2) {
3902                         PMD_DRV_LOG(ERR, "FATAL error from CFC");
3903                 }
3904         }
3905
3906         if (attn & AEU_INPUTS_ATTN_BITS_PXP_HW_INTERRUPT) {
3907                 val = REG_RD(sc, PXP_REG_PXP_INT_STS_CLR_0);
3908                 PMD_DRV_LOG(ERR, "PXP hw attention-0 0x%08x", val);
3909 /* RQ_USDMDP_FIFO_OVERFLOW */
3910                 if (val & 0x18000) {
3911                         PMD_DRV_LOG(ERR, "FATAL error from PXP");
3912                 }
3913
3914                 if (!CHIP_IS_E1x(sc)) {
3915                         val = REG_RD(sc, PXP_REG_PXP_INT_STS_CLR_1);
3916                         PMD_DRV_LOG(ERR, "PXP hw attention-1 0x%08x", val);
3917                 }
3918         }
3919 #define PXP2_EOP_ERROR_BIT  PXP2_PXP2_INT_STS_CLR_0_REG_WR_PGLUE_EOP_ERROR
3920 #define AEU_PXP2_HW_INT_BIT AEU_INPUTS_ATTN_BITS_PXPPCICLOCKCLIENT_HW_INTERRUPT
3921
3922         if (attn & AEU_PXP2_HW_INT_BIT) {
3923 /*  CQ47854 workaround do not panic on
3924  *  PXP2_PXP2_INT_STS_0_REG_WR_PGLUE_EOP_ERROR
3925  */
3926                 if (!CHIP_IS_E1x(sc)) {
3927                         mask0 = REG_RD(sc, PXP2_REG_PXP2_INT_MASK_0);
3928                         val1 = REG_RD(sc, PXP2_REG_PXP2_INT_STS_1);
3929                         mask1 = REG_RD(sc, PXP2_REG_PXP2_INT_MASK_1);
3930                         val0 = REG_RD(sc, PXP2_REG_PXP2_INT_STS_0);
3931                         /*
3932                          * If the only PXP2_EOP_ERROR_BIT is set in
3933                          * STS0 and STS1 - clear it
3934                          *
3935                          * probably we lose additional attentions between
3936                          * STS0 and STS_CLR0, in this case user will not
3937                          * be notified about them
3938                          */
3939                         if (val0 & mask0 & PXP2_EOP_ERROR_BIT &&
3940                             !(val1 & mask1))
3941                                 val0 = REG_RD(sc, PXP2_REG_PXP2_INT_STS_CLR_0);
3942
3943                         /* print the register, since no one can restore it */
3944                         PMD_DRV_LOG(ERR,
3945                                     "PXP2_REG_PXP2_INT_STS_CLR_0 0x%08x", val0);
3946
3947                         /*
3948                          * if PXP2_PXP2_INT_STS_0_REG_WR_PGLUE_EOP_ERROR
3949                          * then notify
3950                          */
3951                         if (val0 & PXP2_EOP_ERROR_BIT) {
3952                                 PMD_DRV_LOG(ERR, "PXP2_WR_PGLUE_EOP_ERROR");
3953
3954                                 /*
3955                                  * if only PXP2_PXP2_INT_STS_0_REG_WR_PGLUE_EOP_ERROR is
3956                                  * set then clear attention from PXP2 block without panic
3957                                  */
3958                                 if (((val0 & mask0) == PXP2_EOP_ERROR_BIT) &&
3959                                     ((val1 & mask1) == 0))
3960                                         attn &= ~AEU_PXP2_HW_INT_BIT;
3961                         }
3962                 }
3963         }
3964
3965         if (attn & HW_INTERRUT_ASSERT_SET_2) {
3966                 reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_2 :
3967                               MISC_REG_AEU_ENABLE1_FUNC_0_OUT_2);
3968
3969                 val = REG_RD(sc, reg_offset);
3970                 val &= ~(attn & HW_INTERRUT_ASSERT_SET_2);
3971                 REG_WR(sc, reg_offset, val);
3972
3973                 PMD_DRV_LOG(ERR,
3974                             "FATAL HW block attention set2 0x%x",
3975                             (uint32_t) (attn & HW_INTERRUT_ASSERT_SET_2));
3976                 rte_panic("HW block attention set2");
3977         }
3978 }
3979
3980 static void bnx2x_attn_int_deasserted1(struct bnx2x_softc *sc, uint32_t attn)
3981 {
3982         int port = SC_PORT(sc);
3983         int reg_offset;
3984         uint32_t val;
3985
3986         if (attn & AEU_INPUTS_ATTN_BITS_DOORBELLQ_HW_INTERRUPT) {
3987                 val = REG_RD(sc, DORQ_REG_DORQ_INT_STS_CLR);
3988                 PMD_DRV_LOG(ERR, "DB hw attention 0x%08x", val);
3989 /* DORQ discard attention */
3990                 if (val & 0x2) {
3991                         PMD_DRV_LOG(ERR, "FATAL error from DORQ");
3992                 }
3993         }
3994
3995         if (attn & HW_INTERRUT_ASSERT_SET_1) {
3996                 reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_1 :
3997                               MISC_REG_AEU_ENABLE1_FUNC_0_OUT_1);
3998
3999                 val = REG_RD(sc, reg_offset);
4000                 val &= ~(attn & HW_INTERRUT_ASSERT_SET_1);
4001                 REG_WR(sc, reg_offset, val);
4002
4003                 PMD_DRV_LOG(ERR,
4004                             "FATAL HW block attention set1 0x%08x",
4005                             (uint32_t) (attn & HW_INTERRUT_ASSERT_SET_1));
4006                 rte_panic("HW block attention set1");
4007         }
4008 }
4009
4010 static void bnx2x_attn_int_deasserted0(struct bnx2x_softc *sc, uint32_t attn)
4011 {
4012         int port = SC_PORT(sc);
4013         int reg_offset;
4014         uint32_t val;
4015
4016         reg_offset = (port) ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 :
4017             MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0;
4018
4019         if (attn & AEU_INPUTS_ATTN_BITS_SPIO5) {
4020                 val = REG_RD(sc, reg_offset);
4021                 val &= ~AEU_INPUTS_ATTN_BITS_SPIO5;
4022                 REG_WR(sc, reg_offset, val);
4023
4024                 PMD_DRV_LOG(WARNING, "SPIO5 hw attention");
4025
4026 /* Fan failure attention */
4027                 elink_hw_reset_phy(&sc->link_params);
4028                 bnx2x_fan_failure(sc);
4029         }
4030
4031         if ((attn & sc->link_vars.aeu_int_mask) && sc->port.pmf) {
4032                 elink_handle_module_detect_int(&sc->link_params);
4033         }
4034
4035         if (attn & HW_INTERRUT_ASSERT_SET_0) {
4036                 val = REG_RD(sc, reg_offset);
4037                 val &= ~(attn & HW_INTERRUT_ASSERT_SET_0);
4038                 REG_WR(sc, reg_offset, val);
4039
4040                 rte_panic("FATAL HW block attention set0 0x%lx",
4041                           (attn & HW_INTERRUT_ASSERT_SET_0));
4042         }
4043 }
4044
4045 static void bnx2x_attn_int_deasserted(struct bnx2x_softc *sc, uint32_t deasserted)
4046 {
4047         struct attn_route attn;
4048         struct attn_route *group_mask;
4049         int port = SC_PORT(sc);
4050         int index;
4051         uint32_t reg_addr;
4052         uint32_t val;
4053         uint32_t aeu_mask;
4054         uint8_t global = FALSE;
4055
4056         /*
4057          * Need to take HW lock because MCP or other port might also
4058          * try to handle this event.
4059          */
4060         bnx2x_acquire_alr(sc);
4061
4062         if (bnx2x_chk_parity_attn(sc, &global, TRUE)) {
4063                 sc->recovery_state = BNX2X_RECOVERY_INIT;
4064
4065 /* disable HW interrupts */
4066                 bnx2x_int_disable(sc);
4067                 bnx2x_release_alr(sc);
4068                 return;
4069         }
4070
4071         attn.sig[0] = REG_RD(sc, MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 + port * 4);
4072         attn.sig[1] = REG_RD(sc, MISC_REG_AEU_AFTER_INVERT_2_FUNC_0 + port * 4);
4073         attn.sig[2] = REG_RD(sc, MISC_REG_AEU_AFTER_INVERT_3_FUNC_0 + port * 4);
4074         attn.sig[3] = REG_RD(sc, MISC_REG_AEU_AFTER_INVERT_4_FUNC_0 + port * 4);
4075         if (!CHIP_IS_E1x(sc)) {
4076                 attn.sig[4] =
4077                     REG_RD(sc, MISC_REG_AEU_AFTER_INVERT_5_FUNC_0 + port * 4);
4078         } else {
4079                 attn.sig[4] = 0;
4080         }
4081
4082         for (index = 0; index < MAX_DYNAMIC_ATTN_GRPS; index++) {
4083                 if (deasserted & (1 << index)) {
4084                         group_mask = &sc->attn_group[index];
4085
4086                         bnx2x_attn_int_deasserted4(sc,
4087                                                  attn.
4088                                                  sig[4] & group_mask->sig[4]);
4089                         bnx2x_attn_int_deasserted3(sc,
4090                                                  attn.
4091                                                  sig[3] & group_mask->sig[3]);
4092                         bnx2x_attn_int_deasserted1(sc,
4093                                                  attn.
4094                                                  sig[1] & group_mask->sig[1]);
4095                         bnx2x_attn_int_deasserted2(sc,
4096                                                  attn.
4097                                                  sig[2] & group_mask->sig[2]);
4098                         bnx2x_attn_int_deasserted0(sc,
4099                                                  attn.
4100                                                  sig[0] & group_mask->sig[0]);
4101                 }
4102         }
4103
4104         bnx2x_release_alr(sc);
4105
4106         if (sc->devinfo.int_block == INT_BLOCK_HC) {
4107                 reg_addr = (HC_REG_COMMAND_REG + port * 32 +
4108                             COMMAND_REG_ATTN_BITS_CLR);
4109         } else {
4110                 reg_addr = (BAR_IGU_INTMEM + IGU_CMD_ATTN_BIT_CLR_UPPER * 8);
4111         }
4112
4113         val = ~deasserted;
4114         PMD_DRV_LOG(DEBUG,
4115                     "about to mask 0x%08x at %s addr 0x%08x", val,
4116                     (sc->devinfo.int_block == INT_BLOCK_HC) ? "HC" : "IGU",
4117                     reg_addr);
4118         REG_WR(sc, reg_addr, val);
4119
4120         if (~sc->attn_state & deasserted) {
4121                 PMD_DRV_LOG(ERR, "IGU error");
4122         }
4123
4124         reg_addr = port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 :
4125             MISC_REG_AEU_MASK_ATTN_FUNC_0;
4126
4127         bnx2x_acquire_hw_lock(sc, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
4128
4129         aeu_mask = REG_RD(sc, reg_addr);
4130
4131         aeu_mask |= (deasserted & 0x3ff);
4132
4133         REG_WR(sc, reg_addr, aeu_mask);
4134         bnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
4135
4136         sc->attn_state &= ~deasserted;
4137 }
4138
4139 static void bnx2x_attn_int(struct bnx2x_softc *sc)
4140 {
4141         /* read local copy of bits */
4142         uint32_t attn_bits = le32toh(sc->def_sb->atten_status_block.attn_bits);
4143         uint32_t attn_ack =
4144             le32toh(sc->def_sb->atten_status_block.attn_bits_ack);
4145         uint32_t attn_state = sc->attn_state;
4146
4147         /* look for changed bits */
4148         uint32_t asserted = attn_bits & ~attn_ack & ~attn_state;
4149         uint32_t deasserted = ~attn_bits & attn_ack & attn_state;
4150
4151         PMD_DRV_LOG(DEBUG,
4152                     "attn_bits 0x%08x attn_ack 0x%08x asserted 0x%08x deasserted 0x%08x",
4153                     attn_bits, attn_ack, asserted, deasserted);
4154
4155         if (~(attn_bits ^ attn_ack) & (attn_bits ^ attn_state)) {
4156                 PMD_DRV_LOG(ERR, "BAD attention state");
4157         }
4158
4159         /* handle bits that were raised */
4160         if (asserted) {
4161                 bnx2x_attn_int_asserted(sc, asserted);
4162         }
4163
4164         if (deasserted) {
4165                 bnx2x_attn_int_deasserted(sc, deasserted);
4166         }
4167 }
4168
4169 static uint16_t bnx2x_update_dsb_idx(struct bnx2x_softc *sc)
4170 {
4171         struct host_sp_status_block *def_sb = sc->def_sb;
4172         uint16_t rc = 0;
4173
4174         mb();                   /* status block is written to by the chip */
4175
4176         if (sc->def_att_idx != def_sb->atten_status_block.attn_bits_index) {
4177                 sc->def_att_idx = def_sb->atten_status_block.attn_bits_index;
4178                 rc |= BNX2X_DEF_SB_ATT_IDX;
4179         }
4180
4181         if (sc->def_idx != def_sb->sp_sb.running_index) {
4182                 sc->def_idx = def_sb->sp_sb.running_index;
4183                 rc |= BNX2X_DEF_SB_IDX;
4184         }
4185
4186         mb();
4187
4188         return rc;
4189 }
4190
4191 static struct ecore_queue_sp_obj *bnx2x_cid_to_q_obj(struct bnx2x_softc *sc,
4192                                                           uint32_t cid)
4193 {
4194         return &sc->sp_objs[CID_TO_FP(cid, sc)].q_obj;
4195 }
4196
4197 static void bnx2x_handle_mcast_eqe(struct bnx2x_softc *sc)
4198 {
4199         struct ecore_mcast_ramrod_params rparam;
4200         int rc;
4201
4202         memset(&rparam, 0, sizeof(rparam));
4203
4204         rparam.mcast_obj = &sc->mcast_obj;
4205
4206         /* clear pending state for the last command */
4207         sc->mcast_obj.raw.clear_pending(&sc->mcast_obj.raw);
4208
4209         /* if there are pending mcast commands - send them */
4210         if (sc->mcast_obj.check_pending(&sc->mcast_obj)) {
4211                 rc = ecore_config_mcast(sc, &rparam, ECORE_MCAST_CMD_CONT);
4212                 if (rc < 0) {
4213                         PMD_DRV_LOG(INFO,
4214                                     "Failed to send pending mcast commands (%d)",
4215                                     rc);
4216                 }
4217         }
4218 }
4219
4220 static void
4221 bnx2x_handle_classification_eqe(struct bnx2x_softc *sc, union event_ring_elem *elem)
4222 {
4223         unsigned long ramrod_flags = 0;
4224         int rc = 0;
4225         uint32_t cid = elem->message.data.eth_event.echo & BNX2X_SWCID_MASK;
4226         struct ecore_vlan_mac_obj *vlan_mac_obj;
4227
4228         /* always push next commands out, don't wait here */
4229         bnx2x_set_bit(RAMROD_CONT, &ramrod_flags);
4230
4231         switch (le32toh(elem->message.data.eth_event.echo) >> BNX2X_SWCID_SHIFT) {
4232         case ECORE_FILTER_MAC_PENDING:
4233                 PMD_DRV_LOG(DEBUG, "Got SETUP_MAC completions");
4234                 vlan_mac_obj = &sc->sp_objs[cid].mac_obj;
4235                 break;
4236
4237         case ECORE_FILTER_MCAST_PENDING:
4238                 PMD_DRV_LOG(DEBUG, "Got SETUP_MCAST completions");
4239                 bnx2x_handle_mcast_eqe(sc);
4240                 return;
4241
4242         default:
4243                 PMD_DRV_LOG(NOTICE, "Unsupported classification command: %d",
4244                             elem->message.data.eth_event.echo);
4245                 return;
4246         }
4247
4248         rc = vlan_mac_obj->complete(sc, vlan_mac_obj, elem, &ramrod_flags);
4249
4250         if (rc < 0) {
4251                 PMD_DRV_LOG(NOTICE, "Failed to schedule new commands (%d)", rc);
4252         } else if (rc > 0) {
4253                 PMD_DRV_LOG(DEBUG, "Scheduled next pending commands...");
4254         }
4255 }
4256
4257 static void bnx2x_handle_rx_mode_eqe(struct bnx2x_softc *sc)
4258 {
4259         bnx2x_clear_bit(ECORE_FILTER_RX_MODE_PENDING, &sc->sp_state);
4260
4261         /* send rx_mode command again if was requested */
4262         if (bnx2x_test_and_clear_bit(ECORE_FILTER_RX_MODE_SCHED, &sc->sp_state)) {
4263                 bnx2x_set_storm_rx_mode(sc);
4264         }
4265 }
4266
4267 static void bnx2x_update_eq_prod(struct bnx2x_softc *sc, uint16_t prod)
4268 {
4269         storm_memset_eq_prod(sc, prod, SC_FUNC(sc));
4270         wmb();                  /* keep prod updates ordered */
4271 }
4272
4273 static void bnx2x_eq_int(struct bnx2x_softc *sc)
4274 {
4275         uint16_t hw_cons, sw_cons, sw_prod;
4276         union event_ring_elem *elem;
4277         uint8_t echo;
4278         uint32_t cid;
4279         uint8_t opcode;
4280         int spqe_cnt = 0;
4281         struct ecore_queue_sp_obj *q_obj;
4282         struct ecore_func_sp_obj *f_obj = &sc->func_obj;
4283         struct ecore_raw_obj *rss_raw = &sc->rss_conf_obj.raw;
4284
4285         hw_cons = le16toh(*sc->eq_cons_sb);
4286
4287         /*
4288          * The hw_cons range is 1-255, 257 - the sw_cons range is 0-254, 256.
4289          * when we get to the next-page we need to adjust so the loop
4290          * condition below will be met. The next element is the size of a
4291          * regular element and hence incrementing by 1
4292          */
4293         if ((hw_cons & EQ_DESC_MAX_PAGE) == EQ_DESC_MAX_PAGE) {
4294                 hw_cons++;
4295         }
4296
4297         /*
4298          * This function may never run in parallel with itself for a
4299          * specific sc and no need for a read memory barrier here.
4300          */
4301         sw_cons = sc->eq_cons;
4302         sw_prod = sc->eq_prod;
4303
4304         for (;
4305              sw_cons != hw_cons;
4306              sw_prod = NEXT_EQ_IDX(sw_prod), sw_cons = NEXT_EQ_IDX(sw_cons)) {
4307
4308                 elem = &sc->eq[EQ_DESC(sw_cons)];
4309
4310 /* elem CID originates from FW, actually LE */
4311                 cid = SW_CID(elem->message.data.cfc_del_event.cid);
4312                 opcode = elem->message.opcode;
4313
4314 /* handle eq element */
4315                 switch (opcode) {
4316                 case EVENT_RING_OPCODE_STAT_QUERY:
4317                         PMD_DEBUG_PERIODIC_LOG(DEBUG, "got statistics completion event %d",
4318                                     sc->stats_comp++);
4319                         /* nothing to do with stats comp */
4320                         goto next_spqe;
4321
4322                 case EVENT_RING_OPCODE_CFC_DEL:
4323                         /* handle according to cid range */
4324                         /* we may want to verify here that the sc state is HALTING */
4325                         PMD_DRV_LOG(DEBUG, "got delete ramrod for MULTI[%d]",
4326                                     cid);
4327                         q_obj = bnx2x_cid_to_q_obj(sc, cid);
4328                         if (q_obj->complete_cmd(sc, q_obj, ECORE_Q_CMD_CFC_DEL)) {
4329                                 break;
4330                         }
4331                         goto next_spqe;
4332
4333                 case EVENT_RING_OPCODE_STOP_TRAFFIC:
4334                         PMD_DRV_LOG(DEBUG, "got STOP TRAFFIC");
4335                         if (f_obj->complete_cmd(sc, f_obj, ECORE_F_CMD_TX_STOP)) {
4336                                 break;
4337                         }
4338                         goto next_spqe;
4339
4340                 case EVENT_RING_OPCODE_START_TRAFFIC:
4341                         PMD_DRV_LOG(DEBUG, "got START TRAFFIC");
4342                         if (f_obj->complete_cmd
4343                             (sc, f_obj, ECORE_F_CMD_TX_START)) {
4344                                 break;
4345                         }
4346                         goto next_spqe;
4347
4348                 case EVENT_RING_OPCODE_FUNCTION_UPDATE:
4349                         echo = elem->message.data.function_update_event.echo;
4350                         if (echo == SWITCH_UPDATE) {
4351                                 PMD_DRV_LOG(DEBUG,
4352                                             "got FUNC_SWITCH_UPDATE ramrod");
4353                                 if (f_obj->complete_cmd(sc, f_obj,
4354                                                         ECORE_F_CMD_SWITCH_UPDATE))
4355                                 {
4356                                         break;
4357                                 }
4358                         } else {
4359                                 PMD_DRV_LOG(DEBUG,
4360                                             "AFEX: ramrod completed FUNCTION_UPDATE");
4361                                 f_obj->complete_cmd(sc, f_obj,
4362                                                     ECORE_F_CMD_AFEX_UPDATE);
4363                         }
4364                         goto next_spqe;
4365
4366                 case EVENT_RING_OPCODE_FORWARD_SETUP:
4367                         q_obj = &bnx2x_fwd_sp_obj(sc, q_obj);
4368                         if (q_obj->complete_cmd(sc, q_obj,
4369                                                 ECORE_Q_CMD_SETUP_TX_ONLY)) {
4370                                 break;
4371                         }
4372                         goto next_spqe;
4373
4374                 case EVENT_RING_OPCODE_FUNCTION_START:
4375                         PMD_DRV_LOG(DEBUG, "got FUNC_START ramrod");
4376                         if (f_obj->complete_cmd(sc, f_obj, ECORE_F_CMD_START)) {
4377                                 break;
4378                         }
4379                         goto next_spqe;
4380
4381                 case EVENT_RING_OPCODE_FUNCTION_STOP:
4382                         PMD_DRV_LOG(DEBUG, "got FUNC_STOP ramrod");
4383                         if (f_obj->complete_cmd(sc, f_obj, ECORE_F_CMD_STOP)) {
4384                                 break;
4385                         }
4386                         goto next_spqe;
4387                 }
4388
4389                 switch (opcode | sc->state) {
4390                 case (EVENT_RING_OPCODE_RSS_UPDATE_RULES | BNX2X_STATE_OPEN):
4391                 case (EVENT_RING_OPCODE_RSS_UPDATE_RULES | BNX2X_STATE_OPENING_WAITING_PORT):
4392                         cid =
4393                             elem->message.data.eth_event.echo & BNX2X_SWCID_MASK;
4394                         PMD_DRV_LOG(DEBUG, "got RSS_UPDATE ramrod. CID %d",
4395                                     cid);
4396                         rss_raw->clear_pending(rss_raw);
4397                         break;
4398
4399                 case (EVENT_RING_OPCODE_SET_MAC | BNX2X_STATE_OPEN):
4400                 case (EVENT_RING_OPCODE_SET_MAC | BNX2X_STATE_DIAG):
4401                 case (EVENT_RING_OPCODE_SET_MAC | BNX2X_STATE_CLOSING_WAITING_HALT):
4402                 case (EVENT_RING_OPCODE_CLASSIFICATION_RULES | BNX2X_STATE_OPEN):
4403                 case (EVENT_RING_OPCODE_CLASSIFICATION_RULES | BNX2X_STATE_DIAG):
4404                 case (EVENT_RING_OPCODE_CLASSIFICATION_RULES | BNX2X_STATE_CLOSING_WAITING_HALT):
4405                         PMD_DRV_LOG(DEBUG,
4406                                     "got (un)set mac ramrod");
4407                         bnx2x_handle_classification_eqe(sc, elem);
4408                         break;
4409
4410                 case (EVENT_RING_OPCODE_MULTICAST_RULES | BNX2X_STATE_OPEN):
4411                 case (EVENT_RING_OPCODE_MULTICAST_RULES | BNX2X_STATE_DIAG):
4412                 case (EVENT_RING_OPCODE_MULTICAST_RULES | BNX2X_STATE_CLOSING_WAITING_HALT):
4413                         PMD_DRV_LOG(DEBUG,
4414                                     "got mcast ramrod");
4415                         bnx2x_handle_mcast_eqe(sc);
4416                         break;
4417
4418                 case (EVENT_RING_OPCODE_FILTERS_RULES | BNX2X_STATE_OPEN):
4419                 case (EVENT_RING_OPCODE_FILTERS_RULES | BNX2X_STATE_DIAG):
4420                 case (EVENT_RING_OPCODE_FILTERS_RULES | BNX2X_STATE_CLOSING_WAITING_HALT):
4421                         PMD_DRV_LOG(DEBUG,
4422                                     "got rx_mode ramrod");
4423                         bnx2x_handle_rx_mode_eqe(sc);
4424                         break;
4425
4426                 default:
4427                         /* unknown event log error and continue */
4428                         PMD_DRV_LOG(INFO, "Unknown EQ event %d, sc->state 0x%x",
4429                                     elem->message.opcode, sc->state);
4430                 }
4431
4432 next_spqe:
4433                 spqe_cnt++;
4434         }                       /* for */
4435
4436         mb();
4437         atomic_add_acq_long(&sc->eq_spq_left, spqe_cnt);
4438
4439         sc->eq_cons = sw_cons;
4440         sc->eq_prod = sw_prod;
4441
4442         /* make sure that above mem writes were issued towards the memory */
4443         wmb();
4444
4445         /* update producer */
4446         bnx2x_update_eq_prod(sc, sc->eq_prod);
4447 }
4448
4449 static int bnx2x_handle_sp_tq(struct bnx2x_softc *sc)
4450 {
4451         uint16_t status;
4452         int rc = 0;
4453
4454         /* what work needs to be performed? */
4455         status = bnx2x_update_dsb_idx(sc);
4456
4457         /* HW attentions */
4458         if (status & BNX2X_DEF_SB_ATT_IDX) {
4459                 PMD_DRV_LOG(DEBUG, "---> ATTN INTR <---");
4460                 bnx2x_attn_int(sc);
4461                 status &= ~BNX2X_DEF_SB_ATT_IDX;
4462                 rc = 1;
4463         }
4464
4465         /* SP events: STAT_QUERY and others */
4466         if (status & BNX2X_DEF_SB_IDX) {
4467 /* handle EQ completions */
4468                 PMD_DEBUG_PERIODIC_LOG(DEBUG, "---> EQ INTR <---");
4469                 bnx2x_eq_int(sc);
4470                 bnx2x_ack_sb(sc, sc->igu_dsb_id, USTORM_ID,
4471                            le16toh(sc->def_idx), IGU_INT_NOP, 1);
4472                 status &= ~BNX2X_DEF_SB_IDX;
4473         }
4474
4475         /* if status is non zero then something went wrong */
4476         if (unlikely(status)) {
4477                 PMD_DRV_LOG(INFO,
4478                             "Got an unknown SP interrupt! (0x%04x)", status);
4479         }
4480
4481         /* ack status block only if something was actually handled */
4482         bnx2x_ack_sb(sc, sc->igu_dsb_id, ATTENTION_ID,
4483                    le16toh(sc->def_att_idx), IGU_INT_ENABLE, 1);
4484
4485         return rc;
4486 }
4487
4488 static void bnx2x_handle_fp_tq(struct bnx2x_fastpath *fp, int scan_fp)
4489 {
4490         struct bnx2x_softc *sc = fp->sc;
4491         uint8_t more_rx = FALSE;
4492
4493         /* update the fastpath index */
4494         bnx2x_update_fp_sb_idx(fp);
4495
4496         if (scan_fp) {
4497                 if (bnx2x_has_rx_work(fp)) {
4498                         more_rx = bnx2x_rxeof(sc, fp);
4499                 }
4500
4501                 if (more_rx) {
4502                         /* still more work to do */
4503                         bnx2x_handle_fp_tq(fp, scan_fp);
4504                         return;
4505                 }
4506         }
4507
4508         bnx2x_ack_sb(sc, fp->igu_sb_id, USTORM_ID,
4509                    le16toh(fp->fp_hc_idx), IGU_INT_DISABLE, 1);
4510 }
4511
4512 /*
4513  * Legacy interrupt entry point.
4514  *
4515  * Verifies that the controller generated the interrupt and
4516  * then calls a separate routine to handle the various
4517  * interrupt causes: link, RX, and TX.
4518  */
4519 int bnx2x_intr_legacy(struct bnx2x_softc *sc, int scan_fp)
4520 {
4521         struct bnx2x_fastpath *fp;
4522         uint32_t status, mask;
4523         int i, rc = 0;
4524
4525         /*
4526          * 0 for ustorm, 1 for cstorm
4527          * the bits returned from ack_int() are 0-15
4528          * bit 0 = attention status block
4529          * bit 1 = fast path status block
4530          * a mask of 0x2 or more = tx/rx event
4531          * a mask of 1 = slow path event
4532          */
4533
4534         status = bnx2x_ack_int(sc);
4535
4536         /* the interrupt is not for us */
4537         if (unlikely(status == 0)) {
4538                 return 0;
4539         }
4540
4541         PMD_DEBUG_PERIODIC_LOG(DEBUG, "Interrupt status 0x%04x", status);
4542         //bnx2x_dump_status_block(sc);
4543
4544         FOR_EACH_ETH_QUEUE(sc, i) {
4545                 fp = &sc->fp[i];
4546                 mask = (0x2 << (fp->index + CNIC_SUPPORT(sc)));
4547                 if (status & mask) {
4548                         bnx2x_handle_fp_tq(fp, scan_fp);
4549                         status &= ~mask;
4550                 }
4551         }
4552
4553         if (unlikely(status & 0x1)) {
4554                 rc = bnx2x_handle_sp_tq(sc);
4555                 status &= ~0x1;
4556         }
4557
4558         if (unlikely(status)) {
4559                 PMD_DRV_LOG(WARNING,
4560                             "Unexpected fastpath status (0x%08x)!", status);
4561         }
4562
4563         return rc;
4564 }
4565
4566 static int bnx2x_init_hw_common_chip(struct bnx2x_softc *sc);
4567 static int bnx2x_init_hw_common(struct bnx2x_softc *sc);
4568 static int bnx2x_init_hw_port(struct bnx2x_softc *sc);
4569 static int bnx2x_init_hw_func(struct bnx2x_softc *sc);
4570 static void bnx2x_reset_common(struct bnx2x_softc *sc);
4571 static void bnx2x_reset_port(struct bnx2x_softc *sc);
4572 static void bnx2x_reset_func(struct bnx2x_softc *sc);
4573 static int bnx2x_init_firmware(struct bnx2x_softc *sc);
4574 static void bnx2x_release_firmware(struct bnx2x_softc *sc);
4575
4576 static struct
4577 ecore_func_sp_drv_ops bnx2x_func_sp_drv = {
4578         .init_hw_cmn_chip = bnx2x_init_hw_common_chip,
4579         .init_hw_cmn = bnx2x_init_hw_common,
4580         .init_hw_port = bnx2x_init_hw_port,
4581         .init_hw_func = bnx2x_init_hw_func,
4582
4583         .reset_hw_cmn = bnx2x_reset_common,
4584         .reset_hw_port = bnx2x_reset_port,
4585         .reset_hw_func = bnx2x_reset_func,
4586
4587         .init_fw = bnx2x_init_firmware,
4588         .release_fw = bnx2x_release_firmware,
4589 };
4590
4591 static void bnx2x_init_func_obj(struct bnx2x_softc *sc)
4592 {
4593         sc->dmae_ready = 0;
4594
4595         PMD_INIT_FUNC_TRACE();
4596
4597         ecore_init_func_obj(sc,
4598                             &sc->func_obj,
4599                             BNX2X_SP(sc, func_rdata),
4600                             (rte_iova_t)BNX2X_SP_MAPPING(sc, func_rdata),
4601                             BNX2X_SP(sc, func_afex_rdata),
4602                             (rte_iova_t)BNX2X_SP_MAPPING(sc, func_afex_rdata),
4603                             &bnx2x_func_sp_drv);
4604 }
4605
4606 static int bnx2x_init_hw(struct bnx2x_softc *sc, uint32_t load_code)
4607 {
4608         struct ecore_func_state_params func_params = { NULL };
4609         int rc;
4610
4611         PMD_INIT_FUNC_TRACE();
4612
4613         /* prepare the parameters for function state transitions */
4614         bnx2x_set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags);
4615
4616         func_params.f_obj = &sc->func_obj;
4617         func_params.cmd = ECORE_F_CMD_HW_INIT;
4618
4619         func_params.params.hw_init.load_phase = load_code;
4620
4621         /*
4622          * Via a plethora of function pointers, we will eventually reach
4623          * bnx2x_init_hw_common(), bnx2x_init_hw_port(), or bnx2x_init_hw_func().
4624          */
4625         rc = ecore_func_state_change(sc, &func_params);
4626
4627         return rc;
4628 }
4629
4630 static void
4631 bnx2x_fill(struct bnx2x_softc *sc, uint32_t addr, int fill, uint32_t len)
4632 {
4633         uint32_t i;
4634
4635         if (!(len % 4) && !(addr % 4)) {
4636                 for (i = 0; i < len; i += 4) {
4637                         REG_WR(sc, (addr + i), fill);
4638                 }
4639         } else {
4640                 for (i = 0; i < len; i++) {
4641                         REG_WR8(sc, (addr + i), fill);
4642                 }
4643         }
4644 }
4645
4646 /* writes FP SP data to FW - data_size in dwords */
4647 static void
4648 bnx2x_wr_fp_sb_data(struct bnx2x_softc *sc, int fw_sb_id, uint32_t * sb_data_p,
4649                   uint32_t data_size)
4650 {
4651         uint32_t index;
4652
4653         for (index = 0; index < data_size; index++) {
4654                 REG_WR(sc,
4655                        (BAR_CSTRORM_INTMEM +
4656                         CSTORM_STATUS_BLOCK_DATA_OFFSET(fw_sb_id) +
4657                         (sizeof(uint32_t) * index)), *(sb_data_p + index));
4658         }
4659 }
4660
4661 static void bnx2x_zero_fp_sb(struct bnx2x_softc *sc, int fw_sb_id)
4662 {
4663         struct hc_status_block_data_e2 sb_data_e2;
4664         struct hc_status_block_data_e1x sb_data_e1x;
4665         uint32_t *sb_data_p;
4666         uint32_t data_size = 0;
4667
4668         if (!CHIP_IS_E1x(sc)) {
4669                 memset(&sb_data_e2, 0, sizeof(struct hc_status_block_data_e2));
4670                 sb_data_e2.common.state = SB_DISABLED;
4671                 sb_data_e2.common.p_func.vf_valid = FALSE;
4672                 sb_data_p = (uint32_t *) & sb_data_e2;
4673                 data_size = (sizeof(struct hc_status_block_data_e2) /
4674                              sizeof(uint32_t));
4675         } else {
4676                 memset(&sb_data_e1x, 0,
4677                        sizeof(struct hc_status_block_data_e1x));
4678                 sb_data_e1x.common.state = SB_DISABLED;
4679                 sb_data_e1x.common.p_func.vf_valid = FALSE;
4680                 sb_data_p = (uint32_t *) & sb_data_e1x;
4681                 data_size = (sizeof(struct hc_status_block_data_e1x) /
4682                              sizeof(uint32_t));
4683         }
4684
4685         bnx2x_wr_fp_sb_data(sc, fw_sb_id, sb_data_p, data_size);
4686
4687         bnx2x_fill(sc,
4688                  (BAR_CSTRORM_INTMEM + CSTORM_STATUS_BLOCK_OFFSET(fw_sb_id)), 0,
4689                  CSTORM_STATUS_BLOCK_SIZE);
4690         bnx2x_fill(sc, (BAR_CSTRORM_INTMEM + CSTORM_SYNC_BLOCK_OFFSET(fw_sb_id)),
4691                  0, CSTORM_SYNC_BLOCK_SIZE);
4692 }
4693
4694 static void
4695 bnx2x_wr_sp_sb_data(struct bnx2x_softc *sc,
4696                   struct hc_sp_status_block_data *sp_sb_data)
4697 {
4698         uint32_t i;
4699
4700         for (i = 0;
4701              i < (sizeof(struct hc_sp_status_block_data) / sizeof(uint32_t));
4702              i++) {
4703                 REG_WR(sc,
4704                        (BAR_CSTRORM_INTMEM +
4705                         CSTORM_SP_STATUS_BLOCK_DATA_OFFSET(SC_FUNC(sc)) +
4706                         (i * sizeof(uint32_t))),
4707                        *((uint32_t *) sp_sb_data + i));
4708         }
4709 }
4710
4711 static void bnx2x_zero_sp_sb(struct bnx2x_softc *sc)
4712 {
4713         struct hc_sp_status_block_data sp_sb_data;
4714
4715         memset(&sp_sb_data, 0, sizeof(struct hc_sp_status_block_data));
4716
4717         sp_sb_data.state = SB_DISABLED;
4718         sp_sb_data.p_func.vf_valid = FALSE;
4719
4720         bnx2x_wr_sp_sb_data(sc, &sp_sb_data);
4721
4722         bnx2x_fill(sc,
4723                  (BAR_CSTRORM_INTMEM +
4724                   CSTORM_SP_STATUS_BLOCK_OFFSET(SC_FUNC(sc))),
4725                  0, CSTORM_SP_STATUS_BLOCK_SIZE);
4726         bnx2x_fill(sc,
4727                  (BAR_CSTRORM_INTMEM +
4728                   CSTORM_SP_SYNC_BLOCK_OFFSET(SC_FUNC(sc))),
4729                  0, CSTORM_SP_SYNC_BLOCK_SIZE);
4730 }
4731
4732 static void
4733 bnx2x_setup_ndsb_state_machine(struct hc_status_block_sm *hc_sm, int igu_sb_id,
4734                              int igu_seg_id)
4735 {
4736         hc_sm->igu_sb_id = igu_sb_id;
4737         hc_sm->igu_seg_id = igu_seg_id;
4738         hc_sm->timer_value = 0xFF;
4739         hc_sm->time_to_expire = 0xFFFFFFFF;
4740 }
4741
4742 static void bnx2x_map_sb_state_machines(struct hc_index_data *index_data)
4743 {
4744         /* zero out state machine indices */
4745
4746         /* rx indices */
4747         index_data[HC_INDEX_ETH_RX_CQ_CONS].flags &= ~HC_INDEX_DATA_SM_ID;
4748
4749         /* tx indices */
4750         index_data[HC_INDEX_OOO_TX_CQ_CONS].flags &= ~HC_INDEX_DATA_SM_ID;
4751         index_data[HC_INDEX_ETH_TX_CQ_CONS_COS0].flags &= ~HC_INDEX_DATA_SM_ID;
4752         index_data[HC_INDEX_ETH_TX_CQ_CONS_COS1].flags &= ~HC_INDEX_DATA_SM_ID;
4753         index_data[HC_INDEX_ETH_TX_CQ_CONS_COS2].flags &= ~HC_INDEX_DATA_SM_ID;
4754
4755         /* map indices */
4756
4757         /* rx indices */
4758         index_data[HC_INDEX_ETH_RX_CQ_CONS].flags |=
4759             (SM_RX_ID << HC_INDEX_DATA_SM_ID_SHIFT);
4760
4761         /* tx indices */
4762         index_data[HC_INDEX_OOO_TX_CQ_CONS].flags |=
4763             (SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT);
4764         index_data[HC_INDEX_ETH_TX_CQ_CONS_COS0].flags |=
4765             (SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT);
4766         index_data[HC_INDEX_ETH_TX_CQ_CONS_COS1].flags |=
4767             (SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT);
4768         index_data[HC_INDEX_ETH_TX_CQ_CONS_COS2].flags |=
4769             (SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT);
4770 }
4771
4772 static void
4773 bnx2x_init_sb(struct bnx2x_softc *sc, rte_iova_t busaddr, int vfid,
4774             uint8_t vf_valid, int fw_sb_id, int igu_sb_id)
4775 {
4776         struct hc_status_block_data_e2 sb_data_e2;
4777         struct hc_status_block_data_e1x sb_data_e1x;
4778         struct hc_status_block_sm *hc_sm_p;
4779         uint32_t *sb_data_p;
4780         int igu_seg_id;
4781         int data_size;
4782
4783         if (CHIP_INT_MODE_IS_BC(sc)) {
4784                 igu_seg_id = HC_SEG_ACCESS_NORM;
4785         } else {
4786                 igu_seg_id = IGU_SEG_ACCESS_NORM;
4787         }
4788
4789         bnx2x_zero_fp_sb(sc, fw_sb_id);
4790
4791         if (!CHIP_IS_E1x(sc)) {
4792                 memset(&sb_data_e2, 0, sizeof(struct hc_status_block_data_e2));
4793                 sb_data_e2.common.state = SB_ENABLED;
4794                 sb_data_e2.common.p_func.pf_id = SC_FUNC(sc);
4795                 sb_data_e2.common.p_func.vf_id = vfid;
4796                 sb_data_e2.common.p_func.vf_valid = vf_valid;
4797                 sb_data_e2.common.p_func.vnic_id = SC_VN(sc);
4798                 sb_data_e2.common.same_igu_sb_1b = TRUE;
4799                 sb_data_e2.common.host_sb_addr.hi = U64_HI(busaddr);
4800                 sb_data_e2.common.host_sb_addr.lo = U64_LO(busaddr);
4801                 hc_sm_p = sb_data_e2.common.state_machine;
4802                 sb_data_p = (uint32_t *) & sb_data_e2;
4803                 data_size = (sizeof(struct hc_status_block_data_e2) /
4804                              sizeof(uint32_t));
4805                 bnx2x_map_sb_state_machines(sb_data_e2.index_data);
4806         } else {
4807                 memset(&sb_data_e1x, 0,
4808                        sizeof(struct hc_status_block_data_e1x));
4809                 sb_data_e1x.common.state = SB_ENABLED;
4810                 sb_data_e1x.common.p_func.pf_id = SC_FUNC(sc);
4811                 sb_data_e1x.common.p_func.vf_id = 0xff;
4812                 sb_data_e1x.common.p_func.vf_valid = FALSE;
4813                 sb_data_e1x.common.p_func.vnic_id = SC_VN(sc);
4814                 sb_data_e1x.common.same_igu_sb_1b = TRUE;
4815                 sb_data_e1x.common.host_sb_addr.hi = U64_HI(busaddr);
4816                 sb_data_e1x.common.host_sb_addr.lo = U64_LO(busaddr);
4817                 hc_sm_p = sb_data_e1x.common.state_machine;
4818                 sb_data_p = (uint32_t *) & sb_data_e1x;
4819                 data_size = (sizeof(struct hc_status_block_data_e1x) /
4820                              sizeof(uint32_t));
4821                 bnx2x_map_sb_state_machines(sb_data_e1x.index_data);
4822         }
4823
4824         bnx2x_setup_ndsb_state_machine(&hc_sm_p[SM_RX_ID], igu_sb_id, igu_seg_id);
4825         bnx2x_setup_ndsb_state_machine(&hc_sm_p[SM_TX_ID], igu_sb_id, igu_seg_id);
4826
4827         /* write indices to HW - PCI guarantees endianity of regpairs */
4828         bnx2x_wr_fp_sb_data(sc, fw_sb_id, sb_data_p, data_size);
4829 }
4830
4831 static uint8_t bnx2x_fp_qzone_id(struct bnx2x_fastpath *fp)
4832 {
4833         if (CHIP_IS_E1x(fp->sc)) {
4834                 return fp->cl_id + SC_PORT(fp->sc) * ETH_MAX_RX_CLIENTS_E1H;
4835         } else {
4836                 return fp->cl_id;
4837         }
4838 }
4839
4840 static uint32_t
4841 bnx2x_rx_ustorm_prods_offset(struct bnx2x_softc *sc, struct bnx2x_fastpath *fp)
4842 {
4843         uint32_t offset = BAR_USTRORM_INTMEM;
4844
4845         if (IS_VF(sc)) {
4846                 return PXP_VF_ADDR_USDM_QUEUES_START +
4847                         (sc->acquire_resp.resc.hw_qid[fp->index] *
4848                          sizeof(struct ustorm_queue_zone_data));
4849         } else if (!CHIP_IS_E1x(sc)) {
4850                 offset += USTORM_RX_PRODS_E2_OFFSET(fp->cl_qzone_id);
4851         } else {
4852                 offset += USTORM_RX_PRODS_E1X_OFFSET(SC_PORT(sc), fp->cl_id);
4853         }
4854
4855         return offset;
4856 }
4857
4858 static void bnx2x_init_eth_fp(struct bnx2x_softc *sc, int idx)
4859 {
4860         struct bnx2x_fastpath *fp = &sc->fp[idx];
4861         uint32_t cids[ECORE_MULTI_TX_COS] = { 0 };
4862         unsigned long q_type = 0;
4863         int cos;
4864
4865         fp->sc = sc;
4866         fp->index = idx;
4867
4868         fp->igu_sb_id = (sc->igu_base_sb + idx + CNIC_SUPPORT(sc));
4869         fp->fw_sb_id = (sc->base_fw_ndsb + idx + CNIC_SUPPORT(sc));
4870
4871         if (CHIP_IS_E1x(sc))
4872                 fp->cl_id = SC_L_ID(sc) + idx;
4873         else
4874 /* want client ID same as IGU SB ID for non-E1 */
4875                 fp->cl_id = fp->igu_sb_id;
4876         fp->cl_qzone_id = bnx2x_fp_qzone_id(fp);
4877
4878         /* setup sb indices */
4879         if (!CHIP_IS_E1x(sc)) {
4880                 fp->sb_index_values = fp->status_block.e2_sb->sb.index_values;
4881                 fp->sb_running_index = fp->status_block.e2_sb->sb.running_index;
4882         } else {
4883                 fp->sb_index_values = fp->status_block.e1x_sb->sb.index_values;
4884                 fp->sb_running_index =
4885                     fp->status_block.e1x_sb->sb.running_index;
4886         }
4887
4888         /* init shortcut */
4889         fp->ustorm_rx_prods_offset = bnx2x_rx_ustorm_prods_offset(sc, fp);
4890
4891         fp->rx_cq_cons_sb = &fp->sb_index_values[HC_INDEX_ETH_RX_CQ_CONS];
4892
4893         for (cos = 0; cos < sc->max_cos; cos++) {
4894                 cids[cos] = idx;
4895         }
4896         fp->tx_cons_sb = &fp->sb_index_values[HC_INDEX_ETH_TX_CQ_CONS_COS0];
4897
4898         /* nothing more for a VF to do */
4899         if (IS_VF(sc)) {
4900                 return;
4901         }
4902
4903         bnx2x_init_sb(sc, fp->sb_dma.paddr, BNX2X_VF_ID_INVALID, FALSE,
4904                     fp->fw_sb_id, fp->igu_sb_id);
4905
4906         bnx2x_update_fp_sb_idx(fp);
4907
4908         /* Configure Queue State object */
4909         bnx2x_set_bit(ECORE_Q_TYPE_HAS_RX, &q_type);
4910         bnx2x_set_bit(ECORE_Q_TYPE_HAS_TX, &q_type);
4911
4912         ecore_init_queue_obj(sc,
4913                              &sc->sp_objs[idx].q_obj,
4914                              fp->cl_id,
4915                              cids,
4916                              sc->max_cos,
4917                              SC_FUNC(sc),
4918                              BNX2X_SP(sc, q_rdata),
4919                              (rte_iova_t)BNX2X_SP_MAPPING(sc, q_rdata),
4920                              q_type);
4921
4922         /* configure classification DBs */
4923         ecore_init_mac_obj(sc,
4924                            &sc->sp_objs[idx].mac_obj,
4925                            fp->cl_id,
4926                            idx,
4927                            SC_FUNC(sc),
4928                            BNX2X_SP(sc, mac_rdata),
4929                            (rte_iova_t)BNX2X_SP_MAPPING(sc, mac_rdata),
4930                            ECORE_FILTER_MAC_PENDING, &sc->sp_state,
4931                            ECORE_OBJ_TYPE_RX_TX, &sc->macs_pool);
4932 }
4933
4934 static void
4935 bnx2x_update_rx_prod(struct bnx2x_softc *sc, struct bnx2x_fastpath *fp,
4936                    uint16_t rx_bd_prod, uint16_t rx_cq_prod)
4937 {
4938         union ustorm_eth_rx_producers rx_prods;
4939         uint32_t i;
4940
4941         /* update producers */
4942         rx_prods.prod.bd_prod = rx_bd_prod;
4943         rx_prods.prod.cqe_prod = rx_cq_prod;
4944         rx_prods.prod.reserved = 0;
4945
4946         /*
4947          * Make sure that the BD and SGE data is updated before updating the
4948          * producers since FW might read the BD/SGE right after the producer
4949          * is updated.
4950          * This is only applicable for weak-ordered memory model archs such
4951          * as IA-64. The following barrier is also mandatory since FW will
4952          * assumes BDs must have buffers.
4953          */
4954         wmb();
4955
4956         for (i = 0; i < (sizeof(rx_prods) / 4); i++) {
4957                 REG_WR(sc,
4958                        (fp->ustorm_rx_prods_offset + (i * 4)),
4959                        rx_prods.raw_data[i]);
4960         }
4961
4962         wmb();                  /* keep prod updates ordered */
4963 }
4964
4965 static void bnx2x_init_rx_rings(struct bnx2x_softc *sc)
4966 {
4967         struct bnx2x_fastpath *fp;
4968         int i;
4969         struct bnx2x_rx_queue *rxq;
4970
4971         for (i = 0; i < sc->num_queues; i++) {
4972                 fp = &sc->fp[i];
4973                 rxq = sc->rx_queues[fp->index];
4974                 if (!rxq) {
4975                         PMD_RX_LOG(ERR, "RX queue is NULL");
4976                         return;
4977                 }
4978
4979                 rxq->rx_bd_head = 0;
4980                 rxq->rx_bd_tail = rxq->nb_rx_desc;
4981                 rxq->rx_cq_head = 0;
4982                 rxq->rx_cq_tail = TOTAL_RCQ_ENTRIES(rxq);
4983                 *fp->rx_cq_cons_sb = 0;
4984
4985                 /*
4986                  * Activate the BD ring...
4987                  * Warning, this will generate an interrupt (to the TSTORM)
4988                  * so this can only be done after the chip is initialized
4989                  */
4990                 bnx2x_update_rx_prod(sc, fp, rxq->rx_bd_tail, rxq->rx_cq_tail);
4991
4992                 if (i != 0) {
4993                         continue;
4994                 }
4995         }
4996 }
4997
4998 static void bnx2x_init_tx_ring_one(struct bnx2x_fastpath *fp)
4999 {
5000         struct bnx2x_tx_queue *txq = fp->sc->tx_queues[fp->index];
5001
5002         fp->tx_db.data.header.header = 1 << DOORBELL_HDR_DB_TYPE_SHIFT;
5003         fp->tx_db.data.zero_fill1 = 0;
5004         fp->tx_db.data.prod = 0;
5005
5006         if (!txq) {
5007                 PMD_TX_LOG(ERR, "ERROR: TX queue is NULL");
5008                 return;
5009         }
5010
5011         txq->tx_pkt_tail = 0;
5012         txq->tx_pkt_head = 0;
5013         txq->tx_bd_tail = 0;
5014         txq->tx_bd_head = 0;
5015 }
5016
5017 static void bnx2x_init_tx_rings(struct bnx2x_softc *sc)
5018 {
5019         int i;
5020
5021         for (i = 0; i < sc->num_queues; i++) {
5022                 bnx2x_init_tx_ring_one(&sc->fp[i]);
5023         }
5024 }
5025
5026 static void bnx2x_init_def_sb(struct bnx2x_softc *sc)
5027 {
5028         struct host_sp_status_block *def_sb = sc->def_sb;
5029         rte_iova_t mapping = sc->def_sb_dma.paddr;
5030         int igu_sp_sb_index;
5031         int igu_seg_id;
5032         int port = SC_PORT(sc);
5033         int func = SC_FUNC(sc);
5034         int reg_offset, reg_offset_en5;
5035         uint64_t section;
5036         int index, sindex;
5037         struct hc_sp_status_block_data sp_sb_data;
5038
5039         memset(&sp_sb_data, 0, sizeof(struct hc_sp_status_block_data));
5040
5041         if (CHIP_INT_MODE_IS_BC(sc)) {
5042                 igu_sp_sb_index = DEF_SB_IGU_ID;
5043                 igu_seg_id = HC_SEG_ACCESS_DEF;
5044         } else {
5045                 igu_sp_sb_index = sc->igu_dsb_id;
5046                 igu_seg_id = IGU_SEG_ACCESS_DEF;
5047         }
5048
5049         /* attentions */
5050         section = ((uint64_t) mapping +
5051                    offsetof(struct host_sp_status_block, atten_status_block));
5052         def_sb->atten_status_block.status_block_id = igu_sp_sb_index;
5053         sc->attn_state = 0;
5054
5055         reg_offset = (port) ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 :
5056             MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0;
5057
5058         reg_offset_en5 = (port) ? MISC_REG_AEU_ENABLE5_FUNC_1_OUT_0 :
5059             MISC_REG_AEU_ENABLE5_FUNC_0_OUT_0;
5060
5061         for (index = 0; index < MAX_DYNAMIC_ATTN_GRPS; index++) {
5062 /* take care of sig[0]..sig[4] */
5063                 for (sindex = 0; sindex < 4; sindex++) {
5064                         sc->attn_group[index].sig[sindex] =
5065                             REG_RD(sc,
5066                                    (reg_offset + (sindex * 0x4) +
5067                                     (0x10 * index)));
5068                 }
5069
5070                 if (!CHIP_IS_E1x(sc)) {
5071                         /*
5072                          * enable5 is separate from the rest of the registers,
5073                          * and the address skip is 4 and not 16 between the
5074                          * different groups
5075                          */
5076                         sc->attn_group[index].sig[4] =
5077                             REG_RD(sc, (reg_offset_en5 + (0x4 * index)));
5078                 } else {
5079                         sc->attn_group[index].sig[4] = 0;
5080                 }
5081         }
5082
5083         if (sc->devinfo.int_block == INT_BLOCK_HC) {
5084                 reg_offset =
5085                     port ? HC_REG_ATTN_MSG1_ADDR_L : HC_REG_ATTN_MSG0_ADDR_L;
5086                 REG_WR(sc, reg_offset, U64_LO(section));
5087                 REG_WR(sc, (reg_offset + 4), U64_HI(section));
5088         } else if (!CHIP_IS_E1x(sc)) {
5089                 REG_WR(sc, IGU_REG_ATTN_MSG_ADDR_L, U64_LO(section));
5090                 REG_WR(sc, IGU_REG_ATTN_MSG_ADDR_H, U64_HI(section));
5091         }
5092
5093         section = ((uint64_t) mapping +
5094                    offsetof(struct host_sp_status_block, sp_sb));
5095
5096         bnx2x_zero_sp_sb(sc);
5097
5098         /* PCI guarantees endianity of regpair */
5099         sp_sb_data.state = SB_ENABLED;
5100         sp_sb_data.host_sb_addr.lo = U64_LO(section);
5101         sp_sb_data.host_sb_addr.hi = U64_HI(section);
5102         sp_sb_data.igu_sb_id = igu_sp_sb_index;
5103         sp_sb_data.igu_seg_id = igu_seg_id;
5104         sp_sb_data.p_func.pf_id = func;
5105         sp_sb_data.p_func.vnic_id = SC_VN(sc);
5106         sp_sb_data.p_func.vf_id = 0xff;
5107
5108         bnx2x_wr_sp_sb_data(sc, &sp_sb_data);
5109
5110         bnx2x_ack_sb(sc, sc->igu_dsb_id, USTORM_ID, 0, IGU_INT_ENABLE, 0);
5111 }
5112
5113 static void bnx2x_init_sp_ring(struct bnx2x_softc *sc)
5114 {
5115         atomic_store_rel_long(&sc->cq_spq_left, MAX_SPQ_PENDING);
5116         sc->spq_prod_idx = 0;
5117         sc->dsb_sp_prod =
5118             &sc->def_sb->sp_sb.index_values[HC_SP_INDEX_ETH_DEF_CONS];
5119         sc->spq_prod_bd = sc->spq;
5120         sc->spq_last_bd = (sc->spq_prod_bd + MAX_SP_DESC_CNT);
5121 }
5122
5123 static void bnx2x_init_eq_ring(struct bnx2x_softc *sc)
5124 {
5125         union event_ring_elem *elem;
5126         int i;
5127
5128         for (i = 1; i <= NUM_EQ_PAGES; i++) {
5129                 elem = &sc->eq[EQ_DESC_CNT_PAGE * i - 1];
5130
5131                 elem->next_page.addr.hi = htole32(U64_HI(sc->eq_dma.paddr +
5132                                                          BNX2X_PAGE_SIZE *
5133                                                          (i % NUM_EQ_PAGES)));
5134                 elem->next_page.addr.lo = htole32(U64_LO(sc->eq_dma.paddr +
5135                                                          BNX2X_PAGE_SIZE *
5136                                                          (i % NUM_EQ_PAGES)));
5137         }
5138
5139         sc->eq_cons = 0;
5140         sc->eq_prod = NUM_EQ_DESC;
5141         sc->eq_cons_sb = &sc->def_sb->sp_sb.index_values[HC_SP_INDEX_EQ_CONS];
5142
5143         atomic_store_rel_long(&sc->eq_spq_left,
5144                               (min((MAX_SP_DESC_CNT - MAX_SPQ_PENDING),
5145                                    NUM_EQ_DESC) - 1));
5146 }
5147
5148 static void bnx2x_init_internal_common(struct bnx2x_softc *sc)
5149 {
5150         int i;
5151
5152         if (IS_MF_SI(sc)) {
5153 /*
5154  * In switch independent mode, the TSTORM needs to accept
5155  * packets that failed classification, since approximate match
5156  * mac addresses aren't written to NIG LLH.
5157  */
5158                 REG_WR8(sc,
5159                         (BAR_TSTRORM_INTMEM +
5160                          TSTORM_ACCEPT_CLASSIFY_FAILED_OFFSET), 2);
5161         } else
5162                 REG_WR8(sc,
5163                         (BAR_TSTRORM_INTMEM +
5164                          TSTORM_ACCEPT_CLASSIFY_FAILED_OFFSET), 0);
5165
5166         /*
5167          * Zero this manually as its initialization is currently missing
5168          * in the initTool.
5169          */
5170         for (i = 0; i < (USTORM_AGG_DATA_SIZE >> 2); i++) {
5171                 REG_WR(sc,
5172                        (BAR_USTRORM_INTMEM + USTORM_AGG_DATA_OFFSET + (i * 4)),
5173                        0);
5174         }
5175
5176         if (!CHIP_IS_E1x(sc)) {
5177                 REG_WR8(sc, (BAR_CSTRORM_INTMEM + CSTORM_IGU_MODE_OFFSET),
5178                         CHIP_INT_MODE_IS_BC(sc) ? HC_IGU_BC_MODE :
5179                         HC_IGU_NBC_MODE);
5180         }
5181 }
5182
5183 static void bnx2x_init_internal(struct bnx2x_softc *sc, uint32_t load_code)
5184 {
5185         switch (load_code) {
5186         case FW_MSG_CODE_DRV_LOAD_COMMON:
5187         case FW_MSG_CODE_DRV_LOAD_COMMON_CHIP:
5188                 bnx2x_init_internal_common(sc);
5189                 /* no break */
5190
5191         case FW_MSG_CODE_DRV_LOAD_PORT:
5192                 /* nothing to do */
5193                 /* no break */
5194
5195         case FW_MSG_CODE_DRV_LOAD_FUNCTION:
5196                 /* internal memory per function is initialized inside bnx2x_pf_init */
5197                 break;
5198
5199         default:
5200                 PMD_DRV_LOG(NOTICE, "Unknown load_code (0x%x) from MCP",
5201                             load_code);
5202                 break;
5203         }
5204 }
5205
5206 static void
5207 storm_memset_func_cfg(struct bnx2x_softc *sc,
5208                       struct tstorm_eth_function_common_config *tcfg,
5209                       uint16_t abs_fid)
5210 {
5211         uint32_t addr;
5212         size_t size;
5213
5214         addr = (BAR_TSTRORM_INTMEM +
5215                 TSTORM_FUNCTION_COMMON_CONFIG_OFFSET(abs_fid));
5216         size = sizeof(struct tstorm_eth_function_common_config);
5217         ecore_storm_memset_struct(sc, addr, size, (uint32_t *) tcfg);
5218 }
5219
5220 static void bnx2x_func_init(struct bnx2x_softc *sc, struct bnx2x_func_init_params *p)
5221 {
5222         struct tstorm_eth_function_common_config tcfg = { 0 };
5223
5224         if (CHIP_IS_E1x(sc)) {
5225                 storm_memset_func_cfg(sc, &tcfg, p->func_id);
5226         }
5227
5228         /* Enable the function in the FW */
5229         storm_memset_vf_to_pf(sc, p->func_id, p->pf_id);
5230         storm_memset_func_en(sc, p->func_id, 1);
5231
5232         /* spq */
5233         if (p->func_flgs & FUNC_FLG_SPQ) {
5234                 storm_memset_spq_addr(sc, p->spq_map, p->func_id);
5235                 REG_WR(sc,
5236                        (XSEM_REG_FAST_MEMORY +
5237                         XSTORM_SPQ_PROD_OFFSET(p->func_id)), p->spq_prod);
5238         }
5239 }
5240
5241 /*
5242  * Calculates the sum of vn_min_rates.
5243  * It's needed for further normalizing of the min_rates.
5244  * Returns:
5245  *   sum of vn_min_rates.
5246  *     or
5247  *   0 - if all the min_rates are 0.
5248  * In the later case fainess algorithm should be deactivated.
5249  * If all min rates are not zero then those that are zeroes will be set to 1.
5250  */
5251 static void bnx2x_calc_vn_min(struct bnx2x_softc *sc, struct cmng_init_input *input)
5252 {
5253         uint32_t vn_cfg;
5254         uint32_t vn_min_rate;
5255         int all_zero = 1;
5256         int vn;
5257
5258         for (vn = VN_0; vn < SC_MAX_VN_NUM(sc); vn++) {
5259                 vn_cfg = sc->devinfo.mf_info.mf_config[vn];
5260                 vn_min_rate = (((vn_cfg & FUNC_MF_CFG_MIN_BW_MASK) >>
5261                                 FUNC_MF_CFG_MIN_BW_SHIFT) * 100);
5262
5263                 if (vn_cfg & FUNC_MF_CFG_FUNC_HIDE) {
5264                         /* skip hidden VNs */
5265                         vn_min_rate = 0;
5266                 } else if (!vn_min_rate) {
5267                         /* If min rate is zero - set it to 100 */
5268                         vn_min_rate = DEF_MIN_RATE;
5269                 } else {
5270                         all_zero = 0;
5271                 }
5272
5273                 input->vnic_min_rate[vn] = vn_min_rate;
5274         }
5275
5276         /* if ETS or all min rates are zeros - disable fairness */
5277         if (all_zero) {
5278                 input->flags.cmng_enables &= ~CMNG_FLAGS_PER_PORT_FAIRNESS_VN;
5279         } else {
5280                 input->flags.cmng_enables |= CMNG_FLAGS_PER_PORT_FAIRNESS_VN;
5281         }
5282 }
5283
5284 static uint16_t
5285 bnx2x_extract_max_cfg(__rte_unused struct bnx2x_softc *sc, uint32_t mf_cfg)
5286 {
5287         uint16_t max_cfg = ((mf_cfg & FUNC_MF_CFG_MAX_BW_MASK) >>
5288                             FUNC_MF_CFG_MAX_BW_SHIFT);
5289
5290         if (!max_cfg) {
5291                 PMD_DRV_LOG(DEBUG,
5292                             "Max BW configured to 0 - using 100 instead");
5293                 max_cfg = 100;
5294         }
5295
5296         return max_cfg;
5297 }
5298
5299 static void
5300 bnx2x_calc_vn_max(struct bnx2x_softc *sc, int vn, struct cmng_init_input *input)
5301 {
5302         uint16_t vn_max_rate;
5303         uint32_t vn_cfg = sc->devinfo.mf_info.mf_config[vn];
5304         uint32_t max_cfg;
5305
5306         if (vn_cfg & FUNC_MF_CFG_FUNC_HIDE) {
5307                 vn_max_rate = 0;
5308         } else {
5309                 max_cfg = bnx2x_extract_max_cfg(sc, vn_cfg);
5310
5311                 if (IS_MF_SI(sc)) {
5312                         /* max_cfg in percents of linkspeed */
5313                         vn_max_rate =
5314                             ((sc->link_vars.line_speed * max_cfg) / 100);
5315                 } else {        /* SD modes */
5316                         /* max_cfg is absolute in 100Mb units */
5317                         vn_max_rate = (max_cfg * 100);
5318                 }
5319         }
5320
5321         input->vnic_max_rate[vn] = vn_max_rate;
5322 }
5323
5324 static void
5325 bnx2x_cmng_fns_init(struct bnx2x_softc *sc, uint8_t read_cfg, uint8_t cmng_type)
5326 {
5327         struct cmng_init_input input;
5328         int vn;
5329
5330         memset(&input, 0, sizeof(struct cmng_init_input));
5331
5332         input.port_rate = sc->link_vars.line_speed;
5333
5334         if (cmng_type == CMNG_FNS_MINMAX) {
5335 /* read mf conf from shmem */
5336                 if (read_cfg) {
5337                         bnx2x_read_mf_cfg(sc);
5338                 }
5339
5340 /* get VN min rate and enable fairness if not 0 */
5341                 bnx2x_calc_vn_min(sc, &input);
5342
5343 /* get VN max rate */
5344                 if (sc->port.pmf) {
5345                         for (vn = VN_0; vn < SC_MAX_VN_NUM(sc); vn++) {
5346                                 bnx2x_calc_vn_max(sc, vn, &input);
5347                         }
5348                 }
5349
5350 /* always enable rate shaping and fairness */
5351                 input.flags.cmng_enables |= CMNG_FLAGS_PER_PORT_RATE_SHAPING_VN;
5352
5353                 ecore_init_cmng(&input, &sc->cmng);
5354                 return;
5355         }
5356 }
5357
5358 static int bnx2x_get_cmng_fns_mode(struct bnx2x_softc *sc)
5359 {
5360         if (CHIP_REV_IS_SLOW(sc)) {
5361                 return CMNG_FNS_NONE;
5362         }
5363
5364         if (IS_MF(sc)) {
5365                 return CMNG_FNS_MINMAX;
5366         }
5367
5368         return CMNG_FNS_NONE;
5369 }
5370
5371 static void
5372 storm_memset_cmng(struct bnx2x_softc *sc, struct cmng_init *cmng, uint8_t port)
5373 {
5374         int vn;
5375         int func;
5376         uint32_t addr;
5377         size_t size;
5378
5379         addr = (BAR_XSTRORM_INTMEM + XSTORM_CMNG_PER_PORT_VARS_OFFSET(port));
5380         size = sizeof(struct cmng_struct_per_port);
5381         ecore_storm_memset_struct(sc, addr, size, (uint32_t *) & cmng->port);
5382
5383         for (vn = VN_0; vn < SC_MAX_VN_NUM(sc); vn++) {
5384                 func = func_by_vn(sc, vn);
5385
5386                 addr = (BAR_XSTRORM_INTMEM +
5387                         XSTORM_RATE_SHAPING_PER_VN_VARS_OFFSET(func));
5388                 size = sizeof(struct rate_shaping_vars_per_vn);
5389                 ecore_storm_memset_struct(sc, addr, size,
5390                                           (uint32_t *) & cmng->
5391                                           vnic.vnic_max_rate[vn]);
5392
5393                 addr = (BAR_XSTRORM_INTMEM +
5394                         XSTORM_FAIRNESS_PER_VN_VARS_OFFSET(func));
5395                 size = sizeof(struct fairness_vars_per_vn);
5396                 ecore_storm_memset_struct(sc, addr, size,
5397                                           (uint32_t *) & cmng->
5398                                           vnic.vnic_min_rate[vn]);
5399         }
5400 }
5401
5402 static void bnx2x_pf_init(struct bnx2x_softc *sc)
5403 {
5404         struct bnx2x_func_init_params func_init;
5405         struct event_ring_data eq_data;
5406         uint16_t flags;
5407
5408         memset(&eq_data, 0, sizeof(struct event_ring_data));
5409         memset(&func_init, 0, sizeof(struct bnx2x_func_init_params));
5410
5411         if (!CHIP_IS_E1x(sc)) {
5412 /* reset IGU PF statistics: MSIX + ATTN */
5413 /* PF */
5414                 REG_WR(sc,
5415                        (IGU_REG_STATISTIC_NUM_MESSAGE_SENT +
5416                         (BNX2X_IGU_STAS_MSG_VF_CNT * 4) +
5417                         ((CHIP_IS_MODE_4_PORT(sc) ? SC_FUNC(sc) : SC_VN(sc)) *
5418                          4)), 0);
5419 /* ATTN */
5420                 REG_WR(sc,
5421                        (IGU_REG_STATISTIC_NUM_MESSAGE_SENT +
5422                         (BNX2X_IGU_STAS_MSG_VF_CNT * 4) +
5423                         (BNX2X_IGU_STAS_MSG_PF_CNT * 4) +
5424                         ((CHIP_IS_MODE_4_PORT(sc) ? SC_FUNC(sc) : SC_VN(sc)) *
5425                          4)), 0);
5426         }
5427
5428         /* function setup flags */
5429         flags = (FUNC_FLG_STATS | FUNC_FLG_LEADING | FUNC_FLG_SPQ);
5430
5431         func_init.func_flgs = flags;
5432         func_init.pf_id = SC_FUNC(sc);
5433         func_init.func_id = SC_FUNC(sc);
5434         func_init.spq_map = sc->spq_dma.paddr;
5435         func_init.spq_prod = sc->spq_prod_idx;
5436
5437         bnx2x_func_init(sc, &func_init);
5438
5439         memset(&sc->cmng, 0, sizeof(struct cmng_struct_per_port));
5440
5441         /*
5442          * Congestion management values depend on the link rate.
5443          * There is no active link so initial link rate is set to 10Gbps.
5444          * When the link comes up the congestion management values are
5445          * re-calculated according to the actual link rate.
5446          */
5447         sc->link_vars.line_speed = SPEED_10000;
5448         bnx2x_cmng_fns_init(sc, TRUE, bnx2x_get_cmng_fns_mode(sc));
5449
5450         /* Only the PMF sets the HW */
5451         if (sc->port.pmf) {
5452                 storm_memset_cmng(sc, &sc->cmng, SC_PORT(sc));
5453         }
5454
5455         /* init Event Queue - PCI bus guarantees correct endainity */
5456         eq_data.base_addr.hi = U64_HI(sc->eq_dma.paddr);
5457         eq_data.base_addr.lo = U64_LO(sc->eq_dma.paddr);
5458         eq_data.producer = sc->eq_prod;
5459         eq_data.index_id = HC_SP_INDEX_EQ_CONS;
5460         eq_data.sb_id = DEF_SB_ID;
5461         storm_memset_eq_data(sc, &eq_data, SC_FUNC(sc));
5462 }
5463
5464 static void bnx2x_hc_int_enable(struct bnx2x_softc *sc)
5465 {
5466         int port = SC_PORT(sc);
5467         uint32_t addr = (port) ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0;
5468         uint32_t val = REG_RD(sc, addr);
5469         uint8_t msix = (sc->interrupt_mode == INTR_MODE_MSIX)
5470             || (sc->interrupt_mode == INTR_MODE_SINGLE_MSIX);
5471         uint8_t single_msix = (sc->interrupt_mode == INTR_MODE_SINGLE_MSIX);
5472         uint8_t msi = (sc->interrupt_mode == INTR_MODE_MSI);
5473
5474         if (msix) {
5475                 val &= ~(HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
5476                          HC_CONFIG_0_REG_INT_LINE_EN_0);
5477                 val |= (HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
5478                         HC_CONFIG_0_REG_ATTN_BIT_EN_0);
5479                 if (single_msix) {
5480                         val |= HC_CONFIG_0_REG_SINGLE_ISR_EN_0;
5481                 }
5482         } else if (msi) {
5483                 val &= ~HC_CONFIG_0_REG_INT_LINE_EN_0;
5484                 val |= (HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
5485                         HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
5486                         HC_CONFIG_0_REG_ATTN_BIT_EN_0);
5487         } else {
5488                 val |= (HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
5489                         HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
5490                         HC_CONFIG_0_REG_INT_LINE_EN_0 |
5491                         HC_CONFIG_0_REG_ATTN_BIT_EN_0);
5492
5493                 REG_WR(sc, addr, val);
5494
5495                 val &= ~HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0;
5496         }
5497
5498         REG_WR(sc, addr, val);
5499
5500         /* ensure that HC_CONFIG is written before leading/trailing edge config */
5501         mb();
5502
5503         /* init leading/trailing edge */
5504         if (IS_MF(sc)) {
5505                 val = (0xee0f | (1 << (SC_VN(sc) + 4)));
5506                 if (sc->port.pmf) {
5507                         /* enable nig and gpio3 attention */
5508                         val |= 0x1100;
5509                 }
5510         } else {
5511                 val = 0xffff;
5512         }
5513
5514         REG_WR(sc, (HC_REG_TRAILING_EDGE_0 + port * 8), val);
5515         REG_WR(sc, (HC_REG_LEADING_EDGE_0 + port * 8), val);
5516
5517         /* make sure that interrupts are indeed enabled from here on */
5518         mb();
5519 }
5520
5521 static void bnx2x_igu_int_enable(struct bnx2x_softc *sc)
5522 {
5523         uint32_t val;
5524         uint8_t msix = (sc->interrupt_mode == INTR_MODE_MSIX)
5525             || (sc->interrupt_mode == INTR_MODE_SINGLE_MSIX);
5526         uint8_t single_msix = (sc->interrupt_mode == INTR_MODE_SINGLE_MSIX);
5527         uint8_t msi = (sc->interrupt_mode == INTR_MODE_MSI);
5528
5529         val = REG_RD(sc, IGU_REG_PF_CONFIGURATION);
5530
5531         if (msix) {
5532                 val &= ~(IGU_PF_CONF_INT_LINE_EN | IGU_PF_CONF_SINGLE_ISR_EN);
5533                 val |= (IGU_PF_CONF_MSI_MSIX_EN | IGU_PF_CONF_ATTN_BIT_EN);
5534                 if (single_msix) {
5535                         val |= IGU_PF_CONF_SINGLE_ISR_EN;
5536                 }
5537         } else if (msi) {
5538                 val &= ~IGU_PF_CONF_INT_LINE_EN;
5539                 val |= (IGU_PF_CONF_MSI_MSIX_EN |
5540                         IGU_PF_CONF_ATTN_BIT_EN | IGU_PF_CONF_SINGLE_ISR_EN);
5541         } else {
5542                 val &= ~IGU_PF_CONF_MSI_MSIX_EN;
5543                 val |= (IGU_PF_CONF_INT_LINE_EN |
5544                         IGU_PF_CONF_ATTN_BIT_EN | IGU_PF_CONF_SINGLE_ISR_EN);
5545         }
5546
5547         /* clean previous status - need to configure igu prior to ack */
5548         if ((!msix) || single_msix) {
5549                 REG_WR(sc, IGU_REG_PF_CONFIGURATION, val);
5550                 bnx2x_ack_int(sc);
5551         }
5552
5553         val |= IGU_PF_CONF_FUNC_EN;
5554
5555         PMD_DRV_LOG(DEBUG, "write 0x%x to IGU mode %s",
5556                     val, ((msix) ? "MSI-X" : ((msi) ? "MSI" : "INTx")));
5557
5558         REG_WR(sc, IGU_REG_PF_CONFIGURATION, val);
5559
5560         mb();
5561
5562         /* init leading/trailing edge */
5563         if (IS_MF(sc)) {
5564                 val = (0xee0f | (1 << (SC_VN(sc) + 4)));
5565                 if (sc->port.pmf) {
5566                         /* enable nig and gpio3 attention */
5567                         val |= 0x1100;
5568                 }
5569         } else {
5570                 val = 0xffff;
5571         }
5572
5573         REG_WR(sc, IGU_REG_TRAILING_EDGE_LATCH, val);
5574         REG_WR(sc, IGU_REG_LEADING_EDGE_LATCH, val);
5575
5576         /* make sure that interrupts are indeed enabled from here on */
5577         mb();
5578 }
5579
5580 static void bnx2x_int_enable(struct bnx2x_softc *sc)
5581 {
5582         if (sc->devinfo.int_block == INT_BLOCK_HC) {
5583                 bnx2x_hc_int_enable(sc);
5584         } else {
5585                 bnx2x_igu_int_enable(sc);
5586         }
5587 }
5588
5589 static void bnx2x_hc_int_disable(struct bnx2x_softc *sc)
5590 {
5591         int port = SC_PORT(sc);
5592         uint32_t addr = (port) ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0;
5593         uint32_t val = REG_RD(sc, addr);
5594
5595         val &= ~(HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
5596                  HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
5597                  HC_CONFIG_0_REG_INT_LINE_EN_0 | HC_CONFIG_0_REG_ATTN_BIT_EN_0);
5598         /* flush all outstanding writes */
5599         mb();
5600
5601         REG_WR(sc, addr, val);
5602         if (REG_RD(sc, addr) != val) {
5603                 PMD_DRV_LOG(ERR, "proper val not read from HC IGU!");
5604         }
5605 }
5606
5607 static void bnx2x_igu_int_disable(struct bnx2x_softc *sc)
5608 {
5609         uint32_t val = REG_RD(sc, IGU_REG_PF_CONFIGURATION);
5610
5611         val &= ~(IGU_PF_CONF_MSI_MSIX_EN |
5612                  IGU_PF_CONF_INT_LINE_EN | IGU_PF_CONF_ATTN_BIT_EN);
5613
5614         PMD_DRV_LOG(DEBUG, "write %x to IGU", val);
5615
5616         /* flush all outstanding writes */
5617         mb();
5618
5619         REG_WR(sc, IGU_REG_PF_CONFIGURATION, val);
5620         if (REG_RD(sc, IGU_REG_PF_CONFIGURATION) != val) {
5621                 PMD_DRV_LOG(ERR, "proper val not read from IGU!");
5622         }
5623 }
5624
5625 static void bnx2x_int_disable(struct bnx2x_softc *sc)
5626 {
5627         if (sc->devinfo.int_block == INT_BLOCK_HC) {
5628                 bnx2x_hc_int_disable(sc);
5629         } else {
5630                 bnx2x_igu_int_disable(sc);
5631         }
5632 }
5633
5634 static void bnx2x_nic_init(struct bnx2x_softc *sc, int load_code)
5635 {
5636         int i;
5637
5638         PMD_INIT_FUNC_TRACE();
5639
5640         for (i = 0; i < sc->num_queues; i++) {
5641                 bnx2x_init_eth_fp(sc, i);
5642         }
5643
5644         rmb();                  /* ensure status block indices were read */
5645
5646         bnx2x_init_rx_rings(sc);
5647         bnx2x_init_tx_rings(sc);
5648
5649         if (IS_VF(sc)) {
5650                 bnx2x_memset_stats(sc);
5651                 return;
5652         }
5653
5654         /* initialize MOD_ABS interrupts */
5655         elink_init_mod_abs_int(sc, &sc->link_vars,
5656                                sc->devinfo.chip_id,
5657                                sc->devinfo.shmem_base,
5658                                sc->devinfo.shmem2_base, SC_PORT(sc));
5659
5660         bnx2x_init_def_sb(sc);
5661         bnx2x_update_dsb_idx(sc);
5662         bnx2x_init_sp_ring(sc);
5663         bnx2x_init_eq_ring(sc);
5664         bnx2x_init_internal(sc, load_code);
5665         bnx2x_pf_init(sc);
5666         bnx2x_stats_init(sc);
5667
5668         /* flush all before enabling interrupts */
5669         mb();
5670
5671         bnx2x_int_enable(sc);
5672
5673         /* check for SPIO5 */
5674         bnx2x_attn_int_deasserted0(sc,
5675                                  REG_RD(sc,
5676                                         (MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 +
5677                                          SC_PORT(sc) * 4)) &
5678                                  AEU_INPUTS_ATTN_BITS_SPIO5);
5679 }
5680
5681 static void bnx2x_init_objs(struct bnx2x_softc *sc)
5682 {
5683         /* mcast rules must be added to tx if tx switching is enabled */
5684         ecore_obj_type o_type;
5685         if (sc->flags & BNX2X_TX_SWITCHING)
5686                 o_type = ECORE_OBJ_TYPE_RX_TX;
5687         else
5688                 o_type = ECORE_OBJ_TYPE_RX;
5689
5690         /* RX_MODE controlling object */
5691         ecore_init_rx_mode_obj(sc, &sc->rx_mode_obj);
5692
5693         /* multicast configuration controlling object */
5694         ecore_init_mcast_obj(sc,
5695                              &sc->mcast_obj,
5696                              sc->fp[0].cl_id,
5697                              sc->fp[0].index,
5698                              SC_FUNC(sc),
5699                              SC_FUNC(sc),
5700                              BNX2X_SP(sc, mcast_rdata),
5701                              (rte_iova_t)BNX2X_SP_MAPPING(sc, mcast_rdata),
5702                              ECORE_FILTER_MCAST_PENDING,
5703                              &sc->sp_state, o_type);
5704
5705         /* Setup CAM credit pools */
5706         ecore_init_mac_credit_pool(sc,
5707                                    &sc->macs_pool,
5708                                    SC_FUNC(sc),
5709                                    CHIP_IS_E1x(sc) ? VNICS_PER_PORT(sc) :
5710                                    VNICS_PER_PATH(sc));
5711
5712         ecore_init_vlan_credit_pool(sc,
5713                                     &sc->vlans_pool,
5714                                     SC_ABS_FUNC(sc) >> 1,
5715                                     CHIP_IS_E1x(sc) ? VNICS_PER_PORT(sc) :
5716                                     VNICS_PER_PATH(sc));
5717
5718         /* RSS configuration object */
5719         ecore_init_rss_config_obj(&sc->rss_conf_obj,
5720                                   sc->fp[0].cl_id,
5721                                   sc->fp[0].index,
5722                                   SC_FUNC(sc),
5723                                   SC_FUNC(sc),
5724                                   BNX2X_SP(sc, rss_rdata),
5725                                   (rte_iova_t)BNX2X_SP_MAPPING(sc, rss_rdata),
5726                                   ECORE_FILTER_RSS_CONF_PENDING,
5727                                   &sc->sp_state, ECORE_OBJ_TYPE_RX);
5728 }
5729
5730 /*
5731  * Initialize the function. This must be called before sending CLIENT_SETUP
5732  * for the first client.
5733  */
5734 static int bnx2x_func_start(struct bnx2x_softc *sc)
5735 {
5736         struct ecore_func_state_params func_params = { NULL };
5737         struct ecore_func_start_params *start_params =
5738             &func_params.params.start;
5739
5740         /* Prepare parameters for function state transitions */
5741         bnx2x_set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags);
5742
5743         func_params.f_obj = &sc->func_obj;
5744         func_params.cmd = ECORE_F_CMD_START;
5745
5746         /* Function parameters */
5747         start_params->mf_mode = sc->devinfo.mf_info.mf_mode;
5748         start_params->sd_vlan_tag = OVLAN(sc);
5749
5750         if (CHIP_IS_E2(sc) || CHIP_IS_E3(sc)) {
5751                 start_params->network_cos_mode = STATIC_COS;
5752         } else {                /* CHIP_IS_E1X */
5753                 start_params->network_cos_mode = FW_WRR;
5754         }
5755
5756         start_params->gre_tunnel_mode = 0;
5757         start_params->gre_tunnel_rss = 0;
5758
5759         return ecore_func_state_change(sc, &func_params);
5760 }
5761
5762 static int bnx2x_set_power_state(struct bnx2x_softc *sc, uint8_t state)
5763 {
5764         uint16_t pmcsr;
5765
5766         /* If there is no power capability, silently succeed */
5767         if (!(sc->devinfo.pcie_cap_flags & BNX2X_PM_CAPABLE_FLAG)) {
5768                 PMD_DRV_LOG(WARNING, "No power capability");
5769                 return 0;
5770         }
5771
5772         pci_read(sc, (sc->devinfo.pcie_pm_cap_reg + PCIR_POWER_STATUS), &pmcsr,
5773                  2);
5774
5775         switch (state) {
5776         case PCI_PM_D0:
5777                 pci_write_word(sc,
5778                                (sc->devinfo.pcie_pm_cap_reg +
5779                                 PCIR_POWER_STATUS),
5780                                ((pmcsr & ~PCIM_PSTAT_DMASK) | PCIM_PSTAT_PME));
5781
5782                 if (pmcsr & PCIM_PSTAT_DMASK) {
5783                         /* delay required during transition out of D3hot */
5784                         DELAY(20000);
5785                 }
5786
5787                 break;
5788
5789         case PCI_PM_D3hot:
5790                 /* don't shut down the power for emulation and FPGA */
5791                 if (CHIP_REV_IS_SLOW(sc)) {
5792                         return 0;
5793                 }
5794
5795                 pmcsr &= ~PCIM_PSTAT_DMASK;
5796                 pmcsr |= PCIM_PSTAT_D3;
5797
5798                 if (sc->wol) {
5799                         pmcsr |= PCIM_PSTAT_PMEENABLE;
5800                 }
5801
5802                 pci_write_long(sc,
5803                                (sc->devinfo.pcie_pm_cap_reg +
5804                                 PCIR_POWER_STATUS), pmcsr);
5805
5806                 /*
5807                  * No more memory access after this point until device is brought back
5808                  * to D0 state.
5809                  */
5810                 break;
5811
5812         default:
5813                 PMD_DRV_LOG(NOTICE, "Can't support PCI power state = %d",
5814                             state);
5815                 return -1;
5816         }
5817
5818         return 0;
5819 }
5820
5821 /* return true if succeeded to acquire the lock */
5822 static uint8_t bnx2x_trylock_hw_lock(struct bnx2x_softc *sc, uint32_t resource)
5823 {
5824         uint32_t lock_status;
5825         uint32_t resource_bit = (1 << resource);
5826         int func = SC_FUNC(sc);
5827         uint32_t hw_lock_control_reg;
5828
5829         /* Validating that the resource is within range */
5830         if (resource > HW_LOCK_MAX_RESOURCE_VALUE) {
5831                 PMD_DRV_LOG(INFO,
5832                             "resource(0x%x) > HW_LOCK_MAX_RESOURCE_VALUE(0x%x)",
5833                             resource, HW_LOCK_MAX_RESOURCE_VALUE);
5834                 return FALSE;
5835         }
5836
5837         if (func <= 5) {
5838                 hw_lock_control_reg = (MISC_REG_DRIVER_CONTROL_1 + func * 8);
5839         } else {
5840                 hw_lock_control_reg =
5841                     (MISC_REG_DRIVER_CONTROL_7 + (func - 6) * 8);
5842         }
5843
5844         /* try to acquire the lock */
5845         REG_WR(sc, hw_lock_control_reg + 4, resource_bit);
5846         lock_status = REG_RD(sc, hw_lock_control_reg);
5847         if (lock_status & resource_bit) {
5848                 return TRUE;
5849         }
5850
5851         PMD_DRV_LOG(NOTICE, "Failed to get a resource lock 0x%x", resource);
5852
5853         return FALSE;
5854 }
5855
5856 /*
5857  * Get the recovery leader resource id according to the engine this function
5858  * belongs to. Currently only only 2 engines is supported.
5859  */
5860 static int bnx2x_get_leader_lock_resource(struct bnx2x_softc *sc)
5861 {
5862         if (SC_PATH(sc)) {
5863                 return HW_LOCK_RESOURCE_RECOVERY_LEADER_1;
5864         } else {
5865                 return HW_LOCK_RESOURCE_RECOVERY_LEADER_0;
5866         }
5867 }
5868
5869 /* try to acquire a leader lock for current engine */
5870 static uint8_t bnx2x_trylock_leader_lock(struct bnx2x_softc *sc)
5871 {
5872         return bnx2x_trylock_hw_lock(sc, bnx2x_get_leader_lock_resource(sc));
5873 }
5874
5875 static int bnx2x_release_leader_lock(struct bnx2x_softc *sc)
5876 {
5877         return bnx2x_release_hw_lock(sc, bnx2x_get_leader_lock_resource(sc));
5878 }
5879
5880 /* close gates #2, #3 and #4 */
5881 static void bnx2x_set_234_gates(struct bnx2x_softc *sc, uint8_t close)
5882 {
5883         uint32_t val;
5884
5885         /* gates #2 and #4a are closed/opened */
5886         /* #4 */
5887         REG_WR(sc, PXP_REG_HST_DISCARD_DOORBELLS, ! !close);
5888         /* #2 */
5889         REG_WR(sc, PXP_REG_HST_DISCARD_INTERNAL_WRITES, ! !close);
5890
5891         /* #3 */
5892         if (CHIP_IS_E1x(sc)) {
5893 /* prevent interrupts from HC on both ports */
5894                 val = REG_RD(sc, HC_REG_CONFIG_1);
5895                 if (close)
5896                         REG_WR(sc, HC_REG_CONFIG_1, (val & ~(uint32_t)
5897                                                      HC_CONFIG_1_REG_BLOCK_DISABLE_1));
5898                 else
5899                         REG_WR(sc, HC_REG_CONFIG_1,
5900                                (val | HC_CONFIG_1_REG_BLOCK_DISABLE_1));
5901
5902                 val = REG_RD(sc, HC_REG_CONFIG_0);
5903                 if (close)
5904                         REG_WR(sc, HC_REG_CONFIG_0, (val & ~(uint32_t)
5905                                                      HC_CONFIG_0_REG_BLOCK_DISABLE_0));
5906                 else
5907                         REG_WR(sc, HC_REG_CONFIG_0,
5908                                (val | HC_CONFIG_0_REG_BLOCK_DISABLE_0));
5909
5910         } else {
5911 /* Prevent incoming interrupts in IGU */
5912                 val = REG_RD(sc, IGU_REG_BLOCK_CONFIGURATION);
5913
5914                 if (close)
5915                         REG_WR(sc, IGU_REG_BLOCK_CONFIGURATION,
5916                                (val & ~(uint32_t)
5917                                 IGU_BLOCK_CONFIGURATION_REG_BLOCK_ENABLE));
5918                 else
5919                         REG_WR(sc, IGU_REG_BLOCK_CONFIGURATION,
5920                                (val |
5921                                 IGU_BLOCK_CONFIGURATION_REG_BLOCK_ENABLE));
5922         }
5923
5924         wmb();
5925 }
5926
5927 /* poll for pending writes bit, it should get cleared in no more than 1s */
5928 static int bnx2x_er_poll_igu_vq(struct bnx2x_softc *sc)
5929 {
5930         uint32_t cnt = 1000;
5931         uint32_t pend_bits = 0;
5932
5933         do {
5934                 pend_bits = REG_RD(sc, IGU_REG_PENDING_BITS_STATUS);
5935
5936                 if (pend_bits == 0) {
5937                         break;
5938                 }
5939
5940                 DELAY(1000);
5941         } while (cnt-- > 0);
5942
5943         if (cnt <= 0) {
5944                 PMD_DRV_LOG(NOTICE, "Still pending IGU requests bits=0x%08x!",
5945                             pend_bits);
5946                 return -1;
5947         }
5948
5949         return 0;
5950 }
5951
5952 #define SHARED_MF_CLP_MAGIC  0x80000000 /* 'magic' bit */
5953
5954 static void bnx2x_clp_reset_prep(struct bnx2x_softc *sc, uint32_t * magic_val)
5955 {
5956         /* Do some magic... */
5957         uint32_t val = MFCFG_RD(sc, shared_mf_config.clp_mb);
5958         *magic_val = val & SHARED_MF_CLP_MAGIC;
5959         MFCFG_WR(sc, shared_mf_config.clp_mb, val | SHARED_MF_CLP_MAGIC);
5960 }
5961
5962 /* restore the value of the 'magic' bit */
5963 static void bnx2x_clp_reset_done(struct bnx2x_softc *sc, uint32_t magic_val)
5964 {
5965         /* Restore the 'magic' bit value... */
5966         uint32_t val = MFCFG_RD(sc, shared_mf_config.clp_mb);
5967         MFCFG_WR(sc, shared_mf_config.clp_mb,
5968                  (val & (~SHARED_MF_CLP_MAGIC)) | magic_val);
5969 }
5970
5971 /* prepare for MCP reset, takes care of CLP configurations */
5972 static void bnx2x_reset_mcp_prep(struct bnx2x_softc *sc, uint32_t * magic_val)
5973 {
5974         uint32_t shmem;
5975         uint32_t validity_offset;
5976
5977         /* set `magic' bit in order to save MF config */
5978         bnx2x_clp_reset_prep(sc, magic_val);
5979
5980         /* get shmem offset */
5981         shmem = REG_RD(sc, MISC_REG_SHARED_MEM_ADDR);
5982         validity_offset =
5983             offsetof(struct shmem_region, validity_map[SC_PORT(sc)]);
5984
5985         /* Clear validity map flags */
5986         if (shmem > 0) {
5987                 REG_WR(sc, shmem + validity_offset, 0);
5988         }
5989 }
5990
5991 #define MCP_TIMEOUT      5000   /* 5 seconds (in ms) */
5992 #define MCP_ONE_TIMEOUT  100    /* 100 ms */
5993
5994 static void bnx2x_mcp_wait_one(struct bnx2x_softc *sc)
5995 {
5996         /* special handling for emulation and FPGA (10 times longer) */
5997         if (CHIP_REV_IS_SLOW(sc)) {
5998                 DELAY((MCP_ONE_TIMEOUT * 10) * 1000);
5999         } else {
6000                 DELAY((MCP_ONE_TIMEOUT) * 1000);
6001         }
6002 }
6003
6004 /* initialize shmem_base and waits for validity signature to appear */
6005 static int bnx2x_init_shmem(struct bnx2x_softc *sc)
6006 {
6007         int cnt = 0;
6008         uint32_t val = 0;
6009
6010         do {
6011                 sc->devinfo.shmem_base =
6012                     sc->link_params.shmem_base =
6013                     REG_RD(sc, MISC_REG_SHARED_MEM_ADDR);
6014
6015                 if (sc->devinfo.shmem_base) {
6016                         val = SHMEM_RD(sc, validity_map[SC_PORT(sc)]);
6017                         if (val & SHR_MEM_VALIDITY_MB)
6018                                 return 0;
6019                 }
6020
6021                 bnx2x_mcp_wait_one(sc);
6022
6023         } while (cnt++ < (MCP_TIMEOUT / MCP_ONE_TIMEOUT));
6024
6025         PMD_DRV_LOG(NOTICE, "BAD MCP validity signature");
6026
6027         return -1;
6028 }
6029
6030 static int bnx2x_reset_mcp_comp(struct bnx2x_softc *sc, uint32_t magic_val)
6031 {
6032         int rc = bnx2x_init_shmem(sc);
6033
6034         /* Restore the `magic' bit value */
6035         bnx2x_clp_reset_done(sc, magic_val);
6036
6037         return rc;
6038 }
6039
6040 static void bnx2x_pxp_prep(struct bnx2x_softc *sc)
6041 {
6042         REG_WR(sc, PXP2_REG_RD_START_INIT, 0);
6043         REG_WR(sc, PXP2_REG_RQ_RBC_DONE, 0);
6044         wmb();
6045 }
6046
6047 /*
6048  * Reset the whole chip except for:
6049  *      - PCIE core
6050  *      - PCI Glue, PSWHST, PXP/PXP2 RF (all controlled by one reset bit)
6051  *      - IGU
6052  *      - MISC (including AEU)
6053  *      - GRC
6054  *      - RBCN, RBCP
6055  */
6056 static void bnx2x_process_kill_chip_reset(struct bnx2x_softc *sc, uint8_t global)
6057 {
6058         uint32_t not_reset_mask1, reset_mask1, not_reset_mask2, reset_mask2;
6059         uint32_t global_bits2, stay_reset2;
6060
6061         /*
6062          * Bits that have to be set in reset_mask2 if we want to reset 'global'
6063          * (per chip) blocks.
6064          */
6065         global_bits2 =
6066             MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_CMN_CPU |
6067             MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_CMN_CORE;
6068
6069         /*
6070          * Don't reset the following blocks.
6071          * Important: per port blocks (such as EMAC, BMAC, UMAC) can't be
6072          *            reset, as in 4 port device they might still be owned
6073          *            by the MCP (there is only one leader per path).
6074          */
6075         not_reset_mask1 =
6076             MISC_REGISTERS_RESET_REG_1_RST_HC |
6077             MISC_REGISTERS_RESET_REG_1_RST_PXPV |
6078             MISC_REGISTERS_RESET_REG_1_RST_PXP;
6079
6080         not_reset_mask2 =
6081             MISC_REGISTERS_RESET_REG_2_RST_PCI_MDIO |
6082             MISC_REGISTERS_RESET_REG_2_RST_EMAC0_HARD_CORE |
6083             MISC_REGISTERS_RESET_REG_2_RST_EMAC1_HARD_CORE |
6084             MISC_REGISTERS_RESET_REG_2_RST_MISC_CORE |
6085             MISC_REGISTERS_RESET_REG_2_RST_RBCN |
6086             MISC_REGISTERS_RESET_REG_2_RST_GRC |
6087             MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_REG_HARD_CORE |
6088             MISC_REGISTERS_RESET_REG_2_RST_MCP_N_HARD_CORE_RST_B |
6089             MISC_REGISTERS_RESET_REG_2_RST_ATC |
6090             MISC_REGISTERS_RESET_REG_2_PGLC |
6091             MISC_REGISTERS_RESET_REG_2_RST_BMAC0 |
6092             MISC_REGISTERS_RESET_REG_2_RST_BMAC1 |
6093             MISC_REGISTERS_RESET_REG_2_RST_EMAC0 |
6094             MISC_REGISTERS_RESET_REG_2_RST_EMAC1 |
6095             MISC_REGISTERS_RESET_REG_2_UMAC0 | MISC_REGISTERS_RESET_REG_2_UMAC1;
6096
6097         /*
6098          * Keep the following blocks in reset:
6099          *  - all xxMACs are handled by the elink code.
6100          */
6101         stay_reset2 =
6102             MISC_REGISTERS_RESET_REG_2_XMAC |
6103             MISC_REGISTERS_RESET_REG_2_XMAC_SOFT;
6104
6105         /* Full reset masks according to the chip */
6106         reset_mask1 = 0xffffffff;
6107
6108         if (CHIP_IS_E1H(sc))
6109                 reset_mask2 = 0x1ffff;
6110         else if (CHIP_IS_E2(sc))
6111                 reset_mask2 = 0xfffff;
6112         else                    /* CHIP_IS_E3 */
6113                 reset_mask2 = 0x3ffffff;
6114
6115         /* Don't reset global blocks unless we need to */
6116         if (!global)
6117                 reset_mask2 &= ~global_bits2;
6118
6119         /*
6120          * In case of attention in the QM, we need to reset PXP
6121          * (MISC_REGISTERS_RESET_REG_2_RST_PXP_RQ_RD_WR) before QM
6122          * because otherwise QM reset would release 'close the gates' shortly
6123          * before resetting the PXP, then the PSWRQ would send a write
6124          * request to PGLUE. Then when PXP is reset, PGLUE would try to
6125          * read the payload data from PSWWR, but PSWWR would not
6126          * respond. The write queue in PGLUE would stuck, dmae commands
6127          * would not return. Therefore it's important to reset the second
6128          * reset register (containing the
6129          * MISC_REGISTERS_RESET_REG_2_RST_PXP_RQ_RD_WR bit) before the
6130          * first one (containing the MISC_REGISTERS_RESET_REG_1_RST_QM
6131          * bit).
6132          */
6133         REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
6134                reset_mask2 & (~not_reset_mask2));
6135
6136         REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR,
6137                reset_mask1 & (~not_reset_mask1));
6138
6139         mb();
6140         wmb();
6141
6142         REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET,
6143                reset_mask2 & (~stay_reset2));
6144
6145         mb();
6146         wmb();
6147
6148         REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, reset_mask1);
6149         wmb();
6150 }
6151
6152 static int bnx2x_process_kill(struct bnx2x_softc *sc, uint8_t global)
6153 {
6154         int cnt = 1000;
6155         uint32_t val = 0;
6156         uint32_t sr_cnt, blk_cnt, port_is_idle_0, port_is_idle_1, pgl_exp_rom2;
6157         uint32_t tags_63_32 = 0;
6158
6159         /* Empty the Tetris buffer, wait for 1s */
6160         do {
6161                 sr_cnt = REG_RD(sc, PXP2_REG_RD_SR_CNT);
6162                 blk_cnt = REG_RD(sc, PXP2_REG_RD_BLK_CNT);
6163                 port_is_idle_0 = REG_RD(sc, PXP2_REG_RD_PORT_IS_IDLE_0);
6164                 port_is_idle_1 = REG_RD(sc, PXP2_REG_RD_PORT_IS_IDLE_1);
6165                 pgl_exp_rom2 = REG_RD(sc, PXP2_REG_PGL_EXP_ROM2);
6166                 if (CHIP_IS_E3(sc)) {
6167                         tags_63_32 = REG_RD(sc, PGLUE_B_REG_TAGS_63_32);
6168                 }
6169
6170                 if ((sr_cnt == 0x7e) && (blk_cnt == 0xa0) &&
6171                     ((port_is_idle_0 & 0x1) == 0x1) &&
6172                     ((port_is_idle_1 & 0x1) == 0x1) &&
6173                     (pgl_exp_rom2 == 0xffffffff) &&
6174                     (!CHIP_IS_E3(sc) || (tags_63_32 == 0xffffffff)))
6175                         break;
6176                 DELAY(1000);
6177         } while (cnt-- > 0);
6178
6179         if (cnt <= 0) {
6180                 PMD_DRV_LOG(NOTICE,
6181                             "ERROR: Tetris buffer didn't get empty or there "
6182                             "are still outstanding read requests after 1s! "
6183                             "sr_cnt=0x%08x, blk_cnt=0x%08x, port_is_idle_0=0x%08x, "
6184                             "port_is_idle_1=0x%08x, pgl_exp_rom2=0x%08x",
6185                             sr_cnt, blk_cnt, port_is_idle_0, port_is_idle_1,
6186                             pgl_exp_rom2);
6187                 return -1;
6188         }
6189
6190         mb();
6191
6192         /* Close gates #2, #3 and #4 */
6193         bnx2x_set_234_gates(sc, TRUE);
6194
6195         /* Poll for IGU VQs for 57712 and newer chips */
6196         if (!CHIP_IS_E1x(sc) && bnx2x_er_poll_igu_vq(sc)) {
6197                 return -1;
6198         }
6199
6200         /* clear "unprepared" bit */
6201         REG_WR(sc, MISC_REG_UNPREPARED, 0);
6202         mb();
6203
6204         /* Make sure all is written to the chip before the reset */
6205         wmb();
6206
6207         /*
6208          * Wait for 1ms to empty GLUE and PCI-E core queues,
6209          * PSWHST, GRC and PSWRD Tetris buffer.
6210          */
6211         DELAY(1000);
6212
6213         /* Prepare to chip reset: */
6214         /* MCP */
6215         if (global) {
6216                 bnx2x_reset_mcp_prep(sc, &val);
6217         }
6218
6219         /* PXP */
6220         bnx2x_pxp_prep(sc);
6221         mb();
6222
6223         /* reset the chip */
6224         bnx2x_process_kill_chip_reset(sc, global);
6225         mb();
6226
6227         /* Recover after reset: */
6228         /* MCP */
6229         if (global && bnx2x_reset_mcp_comp(sc, val)) {
6230                 return -1;
6231         }
6232
6233         /* Open the gates #2, #3 and #4 */
6234         bnx2x_set_234_gates(sc, FALSE);
6235
6236         return 0;
6237 }
6238
6239 static int bnx2x_leader_reset(struct bnx2x_softc *sc)
6240 {
6241         int rc = 0;
6242         uint8_t global = bnx2x_reset_is_global(sc);
6243         uint32_t load_code;
6244
6245         /*
6246          * If not going to reset MCP, load "fake" driver to reset HW while
6247          * driver is owner of the HW.
6248          */
6249         if (!global && !BNX2X_NOMCP(sc)) {
6250                 load_code = bnx2x_fw_command(sc, DRV_MSG_CODE_LOAD_REQ,
6251                                            DRV_MSG_CODE_LOAD_REQ_WITH_LFA);
6252                 if (!load_code) {
6253                         PMD_DRV_LOG(NOTICE, "MCP response failure, aborting");
6254                         rc = -1;
6255                         goto exit_leader_reset;
6256                 }
6257
6258                 if ((load_code != FW_MSG_CODE_DRV_LOAD_COMMON_CHIP) &&
6259                     (load_code != FW_MSG_CODE_DRV_LOAD_COMMON)) {
6260                         PMD_DRV_LOG(NOTICE,
6261                                     "MCP unexpected response, aborting");
6262                         rc = -1;
6263                         goto exit_leader_reset2;
6264                 }
6265
6266                 load_code = bnx2x_fw_command(sc, DRV_MSG_CODE_LOAD_DONE, 0);
6267                 if (!load_code) {
6268                         PMD_DRV_LOG(NOTICE, "MCP response failure, aborting");
6269                         rc = -1;
6270                         goto exit_leader_reset2;
6271                 }
6272         }
6273
6274         /* try to recover after the failure */
6275         if (bnx2x_process_kill(sc, global)) {
6276                 PMD_DRV_LOG(NOTICE, "Something bad occurred on engine %d!",
6277                             SC_PATH(sc));
6278                 rc = -1;
6279                 goto exit_leader_reset2;
6280         }
6281
6282         /*
6283          * Clear the RESET_IN_PROGRESS and RESET_GLOBAL bits and update the driver
6284          * state.
6285          */
6286         bnx2x_set_reset_done(sc);
6287         if (global) {
6288                 bnx2x_clear_reset_global(sc);
6289         }
6290
6291 exit_leader_reset2:
6292
6293         /* unload "fake driver" if it was loaded */
6294         if (!global &&!BNX2X_NOMCP(sc)) {
6295                 bnx2x_fw_command(sc, DRV_MSG_CODE_UNLOAD_REQ_WOL_MCP, 0);
6296                 bnx2x_fw_command(sc, DRV_MSG_CODE_UNLOAD_DONE, 0);
6297         }
6298
6299 exit_leader_reset:
6300
6301         sc->is_leader = 0;
6302         bnx2x_release_leader_lock(sc);
6303
6304         mb();
6305         return rc;
6306 }
6307
6308 /*
6309  * prepare INIT transition, parameters configured:
6310  *   - HC configuration
6311  *   - Queue's CDU context
6312  */
6313 static void
6314 bnx2x_pf_q_prep_init(struct bnx2x_softc *sc, struct bnx2x_fastpath *fp,
6315                    struct ecore_queue_init_params *init_params)
6316 {
6317         uint8_t cos;
6318         int cxt_index, cxt_offset;
6319
6320         bnx2x_set_bit(ECORE_Q_FLG_HC, &init_params->rx.flags);
6321         bnx2x_set_bit(ECORE_Q_FLG_HC, &init_params->tx.flags);
6322
6323         bnx2x_set_bit(ECORE_Q_FLG_HC_EN, &init_params->rx.flags);
6324         bnx2x_set_bit(ECORE_Q_FLG_HC_EN, &init_params->tx.flags);
6325
6326         /* HC rate */
6327         init_params->rx.hc_rate =
6328             sc->hc_rx_ticks ? (1000000 / sc->hc_rx_ticks) : 0;
6329         init_params->tx.hc_rate =
6330             sc->hc_tx_ticks ? (1000000 / sc->hc_tx_ticks) : 0;
6331
6332         /* FW SB ID */
6333         init_params->rx.fw_sb_id = init_params->tx.fw_sb_id = fp->fw_sb_id;
6334
6335         /* CQ index among the SB indices */
6336         init_params->rx.sb_cq_index = HC_INDEX_ETH_RX_CQ_CONS;
6337         init_params->tx.sb_cq_index = HC_INDEX_ETH_FIRST_TX_CQ_CONS;
6338
6339         /* set maximum number of COSs supported by this queue */
6340         init_params->max_cos = sc->max_cos;
6341
6342         /* set the context pointers queue object */
6343         for (cos = FIRST_TX_COS_INDEX; cos < init_params->max_cos; cos++) {
6344                 cxt_index = fp->index / ILT_PAGE_CIDS;
6345                 cxt_offset = fp->index - (cxt_index * ILT_PAGE_CIDS);
6346                 init_params->cxts[cos] =
6347                     &sc->context[cxt_index].vcxt[cxt_offset].eth;
6348         }
6349 }
6350
6351 /* set flags that are common for the Tx-only and not normal connections */
6352 static unsigned long
6353 bnx2x_get_common_flags(struct bnx2x_softc *sc, uint8_t zero_stats)
6354 {
6355         unsigned long flags = 0;
6356
6357         /* PF driver will always initialize the Queue to an ACTIVE state */
6358         bnx2x_set_bit(ECORE_Q_FLG_ACTIVE, &flags);
6359
6360         /*
6361          * tx only connections collect statistics (on the same index as the
6362          * parent connection). The statistics are zeroed when the parent
6363          * connection is initialized.
6364          */
6365
6366         bnx2x_set_bit(ECORE_Q_FLG_STATS, &flags);
6367         if (zero_stats) {
6368                 bnx2x_set_bit(ECORE_Q_FLG_ZERO_STATS, &flags);
6369         }
6370
6371         /*
6372          * tx only connections can support tx-switching, though their
6373          * CoS-ness doesn't survive the loopback
6374          */
6375         if (sc->flags & BNX2X_TX_SWITCHING) {
6376                 bnx2x_set_bit(ECORE_Q_FLG_TX_SWITCH, &flags);
6377         }
6378
6379         bnx2x_set_bit(ECORE_Q_FLG_PCSUM_ON_PKT, &flags);
6380
6381         return flags;
6382 }
6383
6384 static unsigned long bnx2x_get_q_flags(struct bnx2x_softc *sc, uint8_t leading)
6385 {
6386         unsigned long flags = 0;
6387
6388         if (IS_MF_SD(sc)) {
6389                 bnx2x_set_bit(ECORE_Q_FLG_OV, &flags);
6390         }
6391
6392         if (leading) {
6393                 bnx2x_set_bit(ECORE_Q_FLG_LEADING_RSS, &flags);
6394                 bnx2x_set_bit(ECORE_Q_FLG_MCAST, &flags);
6395         }
6396
6397         bnx2x_set_bit(ECORE_Q_FLG_VLAN, &flags);
6398
6399         /* merge with common flags */
6400         return flags | bnx2x_get_common_flags(sc, TRUE);
6401 }
6402
6403 static void
6404 bnx2x_pf_q_prep_general(struct bnx2x_softc *sc, struct bnx2x_fastpath *fp,
6405                       struct ecore_general_setup_params *gen_init, uint8_t cos)
6406 {
6407         gen_init->stat_id = bnx2x_stats_id(fp);
6408         gen_init->spcl_id = fp->cl_id;
6409         gen_init->mtu = sc->mtu;
6410         gen_init->cos = cos;
6411 }
6412
6413 static void
6414 bnx2x_pf_rx_q_prep(struct bnx2x_softc *sc, struct bnx2x_fastpath *fp,
6415                  struct rxq_pause_params *pause,
6416                  struct ecore_rxq_setup_params *rxq_init)
6417 {
6418         struct bnx2x_rx_queue *rxq;
6419
6420         rxq = sc->rx_queues[fp->index];
6421         if (!rxq) {
6422                 PMD_RX_LOG(ERR, "RX queue is NULL");
6423                 return;
6424         }
6425         /* pause */
6426         pause->bd_th_lo = BD_TH_LO(sc);
6427         pause->bd_th_hi = BD_TH_HI(sc);
6428
6429         pause->rcq_th_lo = RCQ_TH_LO(sc);
6430         pause->rcq_th_hi = RCQ_TH_HI(sc);
6431
6432         /* validate rings have enough entries to cross high thresholds */
6433         if (sc->dropless_fc &&
6434             pause->bd_th_hi + FW_PREFETCH_CNT > sc->rx_ring_size) {
6435                 PMD_DRV_LOG(WARNING, "rx bd ring threshold limit");
6436         }
6437
6438         if (sc->dropless_fc &&
6439             pause->rcq_th_hi + FW_PREFETCH_CNT > USABLE_RCQ_ENTRIES(rxq)) {
6440                 PMD_DRV_LOG(WARNING, "rcq ring threshold limit");
6441         }
6442
6443         pause->pri_map = 1;
6444
6445         /* rxq setup */
6446         rxq_init->dscr_map = (rte_iova_t)rxq->rx_ring_phys_addr;
6447         rxq_init->rcq_map = (rte_iova_t)rxq->cq_ring_phys_addr;
6448         rxq_init->rcq_np_map = (rte_iova_t)(rxq->cq_ring_phys_addr +
6449                                               BNX2X_PAGE_SIZE);
6450
6451         /*
6452          * This should be a maximum number of data bytes that may be
6453          * placed on the BD (not including paddings).
6454          */
6455         rxq_init->buf_sz = (fp->rx_buf_size - IP_HEADER_ALIGNMENT_PADDING);
6456
6457         rxq_init->cl_qzone_id = fp->cl_qzone_id;
6458         rxq_init->rss_engine_id = SC_FUNC(sc);
6459         rxq_init->mcast_engine_id = SC_FUNC(sc);
6460
6461         rxq_init->cache_line_log = BNX2X_RX_ALIGN_SHIFT;
6462         rxq_init->fw_sb_id = fp->fw_sb_id;
6463
6464         rxq_init->sb_cq_index = HC_INDEX_ETH_RX_CQ_CONS;
6465
6466         /*
6467          * configure silent vlan removal
6468          * if multi function mode is afex, then mask default vlan
6469          */
6470         if (IS_MF_AFEX(sc)) {
6471                 rxq_init->silent_removal_value =
6472                     sc->devinfo.mf_info.afex_def_vlan_tag;
6473                 rxq_init->silent_removal_mask = EVL_VLID_MASK;
6474         }
6475 }
6476
6477 static void
6478 bnx2x_pf_tx_q_prep(struct bnx2x_softc *sc, struct bnx2x_fastpath *fp,
6479                  struct ecore_txq_setup_params *txq_init, uint8_t cos)
6480 {
6481         struct bnx2x_tx_queue *txq = fp->sc->tx_queues[fp->index];
6482
6483         if (!txq) {
6484                 PMD_TX_LOG(ERR, "ERROR: TX queue is NULL");
6485                 return;
6486         }
6487         txq_init->dscr_map = (rte_iova_t)txq->tx_ring_phys_addr;
6488         txq_init->sb_cq_index = HC_INDEX_ETH_FIRST_TX_CQ_CONS + cos;
6489         txq_init->traffic_type = LLFC_TRAFFIC_TYPE_NW;
6490         txq_init->fw_sb_id = fp->fw_sb_id;
6491
6492         /*
6493          * set the TSS leading client id for TX classfication to the
6494          * leading RSS client id
6495          */
6496         txq_init->tss_leading_cl_id = BNX2X_FP(sc, 0, cl_id);
6497 }
6498
6499 /*
6500  * This function performs 2 steps in a queue state machine:
6501  *   1) RESET->INIT
6502  *   2) INIT->SETUP
6503  */
6504 static int
6505 bnx2x_setup_queue(struct bnx2x_softc *sc, struct bnx2x_fastpath *fp, uint8_t leading)
6506 {
6507         struct ecore_queue_state_params q_params = { NULL };
6508         struct ecore_queue_setup_params *setup_params = &q_params.params.setup;
6509         int rc;
6510
6511         PMD_DRV_LOG(DEBUG, "setting up queue %d", fp->index);
6512
6513         bnx2x_ack_sb(sc, fp->igu_sb_id, USTORM_ID, 0, IGU_INT_ENABLE, 0);
6514
6515         q_params.q_obj = &BNX2X_SP_OBJ(sc, fp).q_obj;
6516
6517         /* we want to wait for completion in this context */
6518         bnx2x_set_bit(RAMROD_COMP_WAIT, &q_params.ramrod_flags);
6519
6520         /* prepare the INIT parameters */
6521         bnx2x_pf_q_prep_init(sc, fp, &q_params.params.init);
6522
6523         /* Set the command */
6524         q_params.cmd = ECORE_Q_CMD_INIT;
6525
6526         /* Change the state to INIT */
6527         rc = ecore_queue_state_change(sc, &q_params);
6528         if (rc) {
6529                 PMD_DRV_LOG(NOTICE, "Queue(%d) INIT failed", fp->index);
6530                 return rc;
6531         }
6532
6533         PMD_DRV_LOG(DEBUG, "init complete");
6534
6535         /* now move the Queue to the SETUP state */
6536         memset(setup_params, 0, sizeof(*setup_params));
6537
6538         /* set Queue flags */
6539         setup_params->flags = bnx2x_get_q_flags(sc, leading);
6540
6541         /* set general SETUP parameters */
6542         bnx2x_pf_q_prep_general(sc, fp, &setup_params->gen_params,
6543                               FIRST_TX_COS_INDEX);
6544
6545         bnx2x_pf_rx_q_prep(sc, fp,
6546                          &setup_params->pause_params,
6547                          &setup_params->rxq_params);
6548
6549         bnx2x_pf_tx_q_prep(sc, fp, &setup_params->txq_params, FIRST_TX_COS_INDEX);
6550
6551         /* Set the command */
6552         q_params.cmd = ECORE_Q_CMD_SETUP;
6553
6554         /* change the state to SETUP */
6555         rc = ecore_queue_state_change(sc, &q_params);
6556         if (rc) {
6557                 PMD_DRV_LOG(NOTICE, "Queue(%d) SETUP failed", fp->index);
6558                 return rc;
6559         }
6560
6561         return rc;
6562 }
6563
6564 static int bnx2x_setup_leading(struct bnx2x_softc *sc)
6565 {
6566         if (IS_PF(sc))
6567                 return bnx2x_setup_queue(sc, &sc->fp[0], TRUE);
6568         else                    /* VF */
6569                 return bnx2x_vf_setup_queue(sc, &sc->fp[0], TRUE);
6570 }
6571
6572 static int
6573 bnx2x_config_rss_pf(struct bnx2x_softc *sc, struct ecore_rss_config_obj *rss_obj,
6574                   uint8_t config_hash)
6575 {
6576         struct ecore_config_rss_params params = { NULL };
6577         uint32_t i;
6578
6579         /*
6580          * Although RSS is meaningless when there is a single HW queue we
6581          * still need it enabled in order to have HW Rx hash generated.
6582          */
6583
6584         params.rss_obj = rss_obj;
6585
6586         bnx2x_set_bit(RAMROD_COMP_WAIT, &params.ramrod_flags);
6587
6588         bnx2x_set_bit(ECORE_RSS_MODE_REGULAR, &params.rss_flags);
6589
6590         /* RSS configuration */
6591         bnx2x_set_bit(ECORE_RSS_IPV4, &params.rss_flags);
6592         bnx2x_set_bit(ECORE_RSS_IPV4_TCP, &params.rss_flags);
6593         bnx2x_set_bit(ECORE_RSS_IPV6, &params.rss_flags);
6594         bnx2x_set_bit(ECORE_RSS_IPV6_TCP, &params.rss_flags);
6595         if (rss_obj->udp_rss_v4) {
6596                 bnx2x_set_bit(ECORE_RSS_IPV4_UDP, &params.rss_flags);
6597         }
6598         if (rss_obj->udp_rss_v6) {
6599                 bnx2x_set_bit(ECORE_RSS_IPV6_UDP, &params.rss_flags);
6600         }
6601
6602         /* Hash bits */
6603         params.rss_result_mask = MULTI_MASK;
6604
6605         rte_memcpy(params.ind_table, rss_obj->ind_table,
6606                          sizeof(params.ind_table));
6607
6608         if (config_hash) {
6609 /* RSS keys */
6610                 for (i = 0; i < sizeof(params.rss_key) / 4; i++) {
6611                         params.rss_key[i] = (uint32_t) rte_rand();
6612                 }
6613
6614                 bnx2x_set_bit(ECORE_RSS_SET_SRCH, &params.rss_flags);
6615         }
6616
6617         if (IS_PF(sc))
6618                 return ecore_config_rss(sc, &params);
6619         else
6620                 return bnx2x_vf_config_rss(sc, &params);
6621 }
6622
6623 static int bnx2x_config_rss_eth(struct bnx2x_softc *sc, uint8_t config_hash)
6624 {
6625         return bnx2x_config_rss_pf(sc, &sc->rss_conf_obj, config_hash);
6626 }
6627
6628 static int bnx2x_init_rss_pf(struct bnx2x_softc *sc)
6629 {
6630         uint8_t num_eth_queues = BNX2X_NUM_ETH_QUEUES(sc);
6631         uint32_t i;
6632
6633         /*
6634          * Prepare the initial contents of the indirection table if
6635          * RSS is enabled
6636          */
6637         for (i = 0; i < sizeof(sc->rss_conf_obj.ind_table); i++) {
6638                 sc->rss_conf_obj.ind_table[i] =
6639                     (sc->fp->cl_id + (i % num_eth_queues));
6640         }
6641
6642         if (sc->udp_rss) {
6643                 sc->rss_conf_obj.udp_rss_v4 = sc->rss_conf_obj.udp_rss_v6 = 1;
6644         }
6645
6646         /*
6647          * For 57711 SEARCHER configuration (rss_keys) is
6648          * per-port, so if explicit configuration is needed, do it only
6649          * for a PMF.
6650          *
6651          * For 57712 and newer it's a per-function configuration.
6652          */
6653         return bnx2x_config_rss_eth(sc, sc->port.pmf || !CHIP_IS_E1x(sc));
6654 }
6655
6656 static int
6657 bnx2x_set_mac_one(struct bnx2x_softc *sc, uint8_t * mac,
6658                 struct ecore_vlan_mac_obj *obj, uint8_t set, int mac_type,
6659                 unsigned long *ramrod_flags)
6660 {
6661         struct ecore_vlan_mac_ramrod_params ramrod_param;
6662         int rc;
6663
6664         memset(&ramrod_param, 0, sizeof(ramrod_param));
6665
6666         /* fill in general parameters */
6667         ramrod_param.vlan_mac_obj = obj;
6668         ramrod_param.ramrod_flags = *ramrod_flags;
6669
6670         /* fill a user request section if needed */
6671         if (!bnx2x_test_bit(RAMROD_CONT, ramrod_flags)) {
6672                 rte_memcpy(ramrod_param.user_req.u.mac.mac, mac,
6673                                  ETH_ALEN);
6674
6675                 bnx2x_set_bit(mac_type, &ramrod_param.user_req.vlan_mac_flags);
6676
6677 /* Set the command: ADD or DEL */
6678                 ramrod_param.user_req.cmd = (set) ? ECORE_VLAN_MAC_ADD :
6679                     ECORE_VLAN_MAC_DEL;
6680         }
6681
6682         rc = ecore_config_vlan_mac(sc, &ramrod_param);
6683
6684         if (rc == ECORE_EXISTS) {
6685                 PMD_DRV_LOG(INFO, "Failed to schedule ADD operations (EEXIST)");
6686 /* do not treat adding same MAC as error */
6687                 rc = 0;
6688         } else if (rc < 0) {
6689                 PMD_DRV_LOG(ERR,
6690                             "%s MAC failed (%d)", (set ? "Set" : "Delete"), rc);
6691         }
6692
6693         return rc;
6694 }
6695
6696 static int bnx2x_set_eth_mac(struct bnx2x_softc *sc, uint8_t set)
6697 {
6698         unsigned long ramrod_flags = 0;
6699
6700         PMD_DRV_LOG(DEBUG, "Adding Ethernet MAC");
6701
6702         bnx2x_set_bit(RAMROD_COMP_WAIT, &ramrod_flags);
6703
6704         /* Eth MAC is set on RSS leading client (fp[0]) */
6705         return bnx2x_set_mac_one(sc, sc->link_params.mac_addr,
6706                                &sc->sp_objs->mac_obj,
6707                                set, ECORE_ETH_MAC, &ramrod_flags);
6708 }
6709
6710 static int bnx2x_get_cur_phy_idx(struct bnx2x_softc *sc)
6711 {
6712         uint32_t sel_phy_idx = 0;
6713
6714         if (sc->link_params.num_phys <= 1) {
6715                 return ELINK_INT_PHY;
6716         }
6717
6718         if (sc->link_vars.link_up) {
6719                 sel_phy_idx = ELINK_EXT_PHY1;
6720 /* In case link is SERDES, check if the ELINK_EXT_PHY2 is the one */
6721                 if ((sc->link_vars.link_status & LINK_STATUS_SERDES_LINK) &&
6722                     (sc->link_params.phy[ELINK_EXT_PHY2].supported &
6723                      ELINK_SUPPORTED_FIBRE))
6724                         sel_phy_idx = ELINK_EXT_PHY2;
6725         } else {
6726                 switch (elink_phy_selection(&sc->link_params)) {
6727                 case PORT_HW_CFG_PHY_SELECTION_HARDWARE_DEFAULT:
6728                 case PORT_HW_CFG_PHY_SELECTION_FIRST_PHY:
6729                 case PORT_HW_CFG_PHY_SELECTION_FIRST_PHY_PRIORITY:
6730                         sel_phy_idx = ELINK_EXT_PHY1;
6731                         break;
6732                 case PORT_HW_CFG_PHY_SELECTION_SECOND_PHY:
6733                 case PORT_HW_CFG_PHY_SELECTION_SECOND_PHY_PRIORITY:
6734                         sel_phy_idx = ELINK_EXT_PHY2;
6735                         break;
6736                 }
6737         }
6738
6739         return sel_phy_idx;
6740 }
6741
6742 static int bnx2x_get_link_cfg_idx(struct bnx2x_softc *sc)
6743 {
6744         uint32_t sel_phy_idx = bnx2x_get_cur_phy_idx(sc);
6745
6746         /*
6747          * The selected activated PHY is always after swapping (in case PHY
6748          * swapping is enabled). So when swapping is enabled, we need to reverse
6749          * the configuration
6750          */
6751
6752         if (sc->link_params.multi_phy_config & PORT_HW_CFG_PHY_SWAPPED_ENABLED) {
6753                 if (sel_phy_idx == ELINK_EXT_PHY1)
6754                         sel_phy_idx = ELINK_EXT_PHY2;
6755                 else if (sel_phy_idx == ELINK_EXT_PHY2)
6756                         sel_phy_idx = ELINK_EXT_PHY1;
6757         }
6758
6759         return ELINK_LINK_CONFIG_IDX(sel_phy_idx);
6760 }
6761
6762 static void bnx2x_set_requested_fc(struct bnx2x_softc *sc)
6763 {
6764         /*
6765          * Initialize link parameters structure variables
6766          * It is recommended to turn off RX FC for jumbo frames
6767          * for better performance
6768          */
6769         if (CHIP_IS_E1x(sc) && (sc->mtu > 5000)) {
6770                 sc->link_params.req_fc_auto_adv = ELINK_FLOW_CTRL_TX;
6771         } else {
6772                 sc->link_params.req_fc_auto_adv = ELINK_FLOW_CTRL_BOTH;
6773         }
6774 }
6775
6776 static void bnx2x_calc_fc_adv(struct bnx2x_softc *sc)
6777 {
6778         uint8_t cfg_idx = bnx2x_get_link_cfg_idx(sc);
6779         switch (sc->link_vars.ieee_fc &
6780                 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_MASK) {
6781         case MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_NONE:
6782         default:
6783                 sc->port.advertising[cfg_idx] &= ~(ADVERTISED_Asym_Pause |
6784                                                    ADVERTISED_Pause);
6785                 break;
6786
6787         case MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH:
6788                 sc->port.advertising[cfg_idx] |= (ADVERTISED_Asym_Pause |
6789                                                   ADVERTISED_Pause);
6790                 break;
6791
6792         case MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC:
6793                 sc->port.advertising[cfg_idx] |= ADVERTISED_Asym_Pause;
6794                 break;
6795         }
6796 }
6797
6798 static uint16_t bnx2x_get_mf_speed(struct bnx2x_softc *sc)
6799 {
6800         uint16_t line_speed = sc->link_vars.line_speed;
6801         if (IS_MF(sc)) {
6802                 uint16_t maxCfg = bnx2x_extract_max_cfg(sc,
6803                                                       sc->devinfo.
6804                                                       mf_info.mf_config[SC_VN
6805                                                                         (sc)]);
6806
6807 /* calculate the current MAX line speed limit for the MF devices */
6808                 if (IS_MF_SI(sc)) {
6809                         line_speed = (line_speed * maxCfg) / 100;
6810                 } else {        /* SD mode */
6811                         uint16_t vn_max_rate = maxCfg * 100;
6812
6813                         if (vn_max_rate < line_speed) {
6814                                 line_speed = vn_max_rate;
6815                         }
6816                 }
6817         }
6818
6819         return line_speed;
6820 }
6821
6822 static void
6823 bnx2x_fill_report_data(struct bnx2x_softc *sc, struct bnx2x_link_report_data *data)
6824 {
6825         uint16_t line_speed = bnx2x_get_mf_speed(sc);
6826
6827         memset(data, 0, sizeof(*data));
6828
6829         /* fill the report data with the effective line speed */
6830         data->line_speed = line_speed;
6831
6832         /* Link is down */
6833         if (!sc->link_vars.link_up || (sc->flags & BNX2X_MF_FUNC_DIS)) {
6834                 bnx2x_set_bit(BNX2X_LINK_REPORT_LINK_DOWN,
6835                             &data->link_report_flags);
6836         }
6837
6838         /* Full DUPLEX */
6839         if (sc->link_vars.duplex == DUPLEX_FULL) {
6840                 bnx2x_set_bit(BNX2X_LINK_REPORT_FULL_DUPLEX,
6841                             &data->link_report_flags);
6842         }
6843
6844         /* Rx Flow Control is ON */
6845         if (sc->link_vars.flow_ctrl & ELINK_FLOW_CTRL_RX) {
6846                 bnx2x_set_bit(BNX2X_LINK_REPORT_RX_FC_ON, &data->link_report_flags);
6847         }
6848
6849         /* Tx Flow Control is ON */
6850         if (sc->link_vars.flow_ctrl & ELINK_FLOW_CTRL_TX) {
6851                 bnx2x_set_bit(BNX2X_LINK_REPORT_TX_FC_ON, &data->link_report_flags);
6852         }
6853 }
6854
6855 /* report link status to OS, should be called under phy_lock */
6856 static void bnx2x_link_report(struct bnx2x_softc *sc)
6857 {
6858         struct bnx2x_link_report_data cur_data;
6859
6860         /* reread mf_cfg */
6861         if (IS_PF(sc)) {
6862                 bnx2x_read_mf_cfg(sc);
6863         }
6864
6865         /* Read the current link report info */
6866         bnx2x_fill_report_data(sc, &cur_data);
6867
6868         /* Don't report link down or exactly the same link status twice */
6869         if (!memcmp(&cur_data, &sc->last_reported_link, sizeof(cur_data)) ||
6870             (bnx2x_test_bit(BNX2X_LINK_REPORT_LINK_DOWN,
6871                           &sc->last_reported_link.link_report_flags) &&
6872              bnx2x_test_bit(BNX2X_LINK_REPORT_LINK_DOWN,
6873                           &cur_data.link_report_flags))) {
6874                 return;
6875         }
6876
6877         sc->link_cnt++;
6878
6879         /* report new link params and remember the state for the next time */
6880         rte_memcpy(&sc->last_reported_link, &cur_data, sizeof(cur_data));
6881
6882         if (bnx2x_test_bit(BNX2X_LINK_REPORT_LINK_DOWN,
6883                          &cur_data.link_report_flags)) {
6884                 PMD_DRV_LOG(INFO, "NIC Link is Down");
6885         } else {
6886                 __rte_unused const char *duplex;
6887                 __rte_unused const char *flow;
6888
6889                 if (bnx2x_test_and_clear_bit(BNX2X_LINK_REPORT_FULL_DUPLEX,
6890                                            &cur_data.link_report_flags)) {
6891                         duplex = "full";
6892                 } else {
6893                         duplex = "half";
6894                 }
6895
6896 /*
6897  * Handle the FC at the end so that only these flags would be
6898  * possibly set. This way we may easily check if there is no FC
6899  * enabled.
6900  */
6901                 if (cur_data.link_report_flags) {
6902                         if (bnx2x_test_bit(BNX2X_LINK_REPORT_RX_FC_ON,
6903                                          &cur_data.link_report_flags) &&
6904                             bnx2x_test_bit(BNX2X_LINK_REPORT_TX_FC_ON,
6905                                          &cur_data.link_report_flags)) {
6906                                 flow = "ON - receive & transmit";
6907                         } else if (bnx2x_test_bit(BNX2X_LINK_REPORT_RX_FC_ON,
6908                                                 &cur_data.link_report_flags) &&
6909                                    !bnx2x_test_bit(BNX2X_LINK_REPORT_TX_FC_ON,
6910                                                  &cur_data.link_report_flags)) {
6911                                 flow = "ON - receive";
6912                         } else if (!bnx2x_test_bit(BNX2X_LINK_REPORT_RX_FC_ON,
6913                                                  &cur_data.link_report_flags) &&
6914                                    bnx2x_test_bit(BNX2X_LINK_REPORT_TX_FC_ON,
6915                                                 &cur_data.link_report_flags)) {
6916                                 flow = "ON - transmit";
6917                         } else {
6918                                 flow = "none";  /* possible? */
6919                         }
6920                 } else {
6921                         flow = "none";
6922                 }
6923
6924                 PMD_DRV_LOG(INFO,
6925                             "NIC Link is Up, %d Mbps %s duplex, Flow control: %s",
6926                             cur_data.line_speed, duplex, flow);
6927         }
6928 }
6929
6930 void bnx2x_link_status_update(struct bnx2x_softc *sc)
6931 {
6932         if (sc->state != BNX2X_STATE_OPEN) {
6933                 return;
6934         }
6935
6936         if (IS_PF(sc) && !CHIP_REV_IS_SLOW(sc)) {
6937                 elink_link_status_update(&sc->link_params, &sc->link_vars);
6938         } else {
6939                 sc->port.supported[0] |= (ELINK_SUPPORTED_10baseT_Half |
6940                                           ELINK_SUPPORTED_10baseT_Full |
6941                                           ELINK_SUPPORTED_100baseT_Half |
6942                                           ELINK_SUPPORTED_100baseT_Full |
6943                                           ELINK_SUPPORTED_1000baseT_Full |
6944                                           ELINK_SUPPORTED_2500baseX_Full |
6945                                           ELINK_SUPPORTED_10000baseT_Full |
6946                                           ELINK_SUPPORTED_TP |
6947                                           ELINK_SUPPORTED_FIBRE |
6948                                           ELINK_SUPPORTED_Autoneg |
6949                                           ELINK_SUPPORTED_Pause |
6950                                           ELINK_SUPPORTED_Asym_Pause);
6951                 sc->port.advertising[0] = sc->port.supported[0];
6952
6953                 sc->link_params.sc = sc;
6954                 sc->link_params.port = SC_PORT(sc);
6955                 sc->link_params.req_duplex[0] = DUPLEX_FULL;
6956                 sc->link_params.req_flow_ctrl[0] = ELINK_FLOW_CTRL_NONE;
6957                 sc->link_params.req_line_speed[0] = SPEED_10000;
6958                 sc->link_params.speed_cap_mask[0] = 0x7f0000;
6959                 sc->link_params.switch_cfg = ELINK_SWITCH_CFG_10G;
6960
6961                 if (CHIP_REV_IS_FPGA(sc)) {
6962                         sc->link_vars.mac_type = ELINK_MAC_TYPE_EMAC;
6963                         sc->link_vars.line_speed = ELINK_SPEED_1000;
6964                         sc->link_vars.link_status = (LINK_STATUS_LINK_UP |
6965                                                      LINK_STATUS_SPEED_AND_DUPLEX_1000TFD);
6966                 } else {
6967                         sc->link_vars.mac_type = ELINK_MAC_TYPE_BMAC;
6968                         sc->link_vars.line_speed = ELINK_SPEED_10000;
6969                         sc->link_vars.link_status = (LINK_STATUS_LINK_UP |
6970                                                      LINK_STATUS_SPEED_AND_DUPLEX_10GTFD);
6971                 }
6972
6973                 sc->link_vars.link_up = 1;
6974
6975                 sc->link_vars.duplex = DUPLEX_FULL;
6976                 sc->link_vars.flow_ctrl = ELINK_FLOW_CTRL_NONE;
6977
6978                 if (IS_PF(sc)) {
6979                         REG_WR(sc,
6980                                NIG_REG_EGRESS_DRAIN0_MODE +
6981                                sc->link_params.port * 4, 0);
6982                         bnx2x_stats_handle(sc, STATS_EVENT_LINK_UP);
6983                         bnx2x_link_report(sc);
6984                 }
6985         }
6986
6987         if (IS_PF(sc)) {
6988                 if (sc->link_vars.link_up) {
6989                         bnx2x_stats_handle(sc, STATS_EVENT_LINK_UP);
6990                 } else {
6991                         bnx2x_stats_handle(sc, STATS_EVENT_STOP);
6992                 }
6993                 bnx2x_link_report(sc);
6994         } else {
6995                 bnx2x_link_report(sc);
6996                 bnx2x_stats_handle(sc, STATS_EVENT_LINK_UP);
6997         }
6998 }
6999
7000 static void bnx2x_periodic_start(struct bnx2x_softc *sc)
7001 {
7002         atomic_store_rel_long(&sc->periodic_flags, PERIODIC_GO);
7003 }
7004
7005 static void bnx2x_periodic_stop(struct bnx2x_softc *sc)
7006 {
7007         atomic_store_rel_long(&sc->periodic_flags, PERIODIC_STOP);
7008 }
7009
7010 static int bnx2x_initial_phy_init(struct bnx2x_softc *sc, int load_mode)
7011 {
7012         int rc, cfg_idx = bnx2x_get_link_cfg_idx(sc);
7013         uint16_t req_line_speed = sc->link_params.req_line_speed[cfg_idx];
7014         struct elink_params *lp = &sc->link_params;
7015
7016         bnx2x_set_requested_fc(sc);
7017
7018         if (load_mode == LOAD_DIAG) {
7019                 lp->loopback_mode = ELINK_LOOPBACK_XGXS;
7020 /* Prefer doing PHY loopback at 10G speed, if possible */
7021                 if (lp->req_line_speed[cfg_idx] < ELINK_SPEED_10000) {
7022                         if (lp->speed_cap_mask[cfg_idx] &
7023                             PORT_HW_CFG_SPEED_CAPABILITY_D0_10G) {
7024                                 lp->req_line_speed[cfg_idx] = ELINK_SPEED_10000;
7025                         } else {
7026                                 lp->req_line_speed[cfg_idx] = ELINK_SPEED_1000;
7027                         }
7028                 }
7029         }
7030
7031         if (load_mode == LOAD_LOOPBACK_EXT) {
7032                 lp->loopback_mode = ELINK_LOOPBACK_EXT;
7033         }
7034
7035         rc = elink_phy_init(&sc->link_params, &sc->link_vars);
7036
7037         bnx2x_calc_fc_adv(sc);
7038
7039         if (sc->link_vars.link_up) {
7040                 bnx2x_stats_handle(sc, STATS_EVENT_LINK_UP);
7041                 bnx2x_link_report(sc);
7042         }
7043
7044         if (!CHIP_REV_IS_SLOW(sc)) {
7045                 bnx2x_periodic_start(sc);
7046         }
7047
7048         sc->link_params.req_line_speed[cfg_idx] = req_line_speed;
7049         return rc;
7050 }
7051
7052 /* update flags in shmem */
7053 static void
7054 bnx2x_update_drv_flags(struct bnx2x_softc *sc, uint32_t flags, uint32_t set)
7055 {
7056         uint32_t drv_flags;
7057
7058         if (SHMEM2_HAS(sc, drv_flags)) {
7059                 bnx2x_acquire_hw_lock(sc, HW_LOCK_RESOURCE_DRV_FLAGS);
7060                 drv_flags = SHMEM2_RD(sc, drv_flags);
7061
7062                 if (set) {
7063                         drv_flags |= flags;
7064                 } else {
7065                         drv_flags &= ~flags;
7066                 }
7067
7068                 SHMEM2_WR(sc, drv_flags, drv_flags);
7069
7070                 bnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_DRV_FLAGS);
7071         }
7072 }
7073
7074 /* periodic timer callout routine, only runs when the interface is up */
7075 void bnx2x_periodic_callout(struct bnx2x_softc *sc)
7076 {
7077         if ((sc->state != BNX2X_STATE_OPEN) ||
7078             (atomic_load_acq_long(&sc->periodic_flags) == PERIODIC_STOP)) {
7079                 PMD_DRV_LOG(WARNING, "periodic callout exit (state=0x%x)",
7080                             sc->state);
7081                 return;
7082         }
7083         if (!CHIP_REV_IS_SLOW(sc)) {
7084 /*
7085  * This barrier is needed to ensure the ordering between the writing
7086  * to the sc->port.pmf in the bnx2x_nic_load() or bnx2x_pmf_update() and
7087  * the reading here.
7088  */
7089                 mb();
7090                 if (sc->port.pmf) {
7091                         elink_period_func(&sc->link_params, &sc->link_vars);
7092                 }
7093         }
7094 #ifdef BNX2X_PULSE
7095         if (IS_PF(sc) && !BNX2X_NOMCP(sc)) {
7096                 int mb_idx = SC_FW_MB_IDX(sc);
7097                 uint32_t drv_pulse;
7098                 uint32_t mcp_pulse;
7099
7100                 ++sc->fw_drv_pulse_wr_seq;
7101                 sc->fw_drv_pulse_wr_seq &= DRV_PULSE_SEQ_MASK;
7102
7103                 drv_pulse = sc->fw_drv_pulse_wr_seq;
7104                 bnx2x_drv_pulse(sc);
7105
7106                 mcp_pulse = (SHMEM_RD(sc, func_mb[mb_idx].mcp_pulse_mb) &
7107                              MCP_PULSE_SEQ_MASK);
7108
7109 /*
7110  * The delta between driver pulse and mcp response should
7111  * be 1 (before mcp response) or 0 (after mcp response).
7112  */
7113                 if ((drv_pulse != mcp_pulse) &&
7114                     (drv_pulse != ((mcp_pulse + 1) & MCP_PULSE_SEQ_MASK))) {
7115                         /* someone lost a heartbeat... */
7116                         PMD_DRV_LOG(ERR,
7117                                     "drv_pulse (0x%x) != mcp_pulse (0x%x)",
7118                                     drv_pulse, mcp_pulse);
7119                 }
7120         }
7121 #endif
7122 }
7123
7124 /* start the controller */
7125 static __rte_noinline
7126 int bnx2x_nic_load(struct bnx2x_softc *sc)
7127 {
7128         uint32_t val;
7129         uint32_t load_code = 0;
7130         int i, rc = 0;
7131
7132         PMD_INIT_FUNC_TRACE();
7133
7134         sc->state = BNX2X_STATE_OPENING_WAITING_LOAD;
7135
7136         if (IS_PF(sc)) {
7137 /* must be called before memory allocation and HW init */
7138                 bnx2x_ilt_set_info(sc);
7139         }
7140
7141         bnx2x_set_fp_rx_buf_size(sc);
7142
7143         if (IS_PF(sc)) {
7144                 if (bnx2x_alloc_mem(sc) != 0) {
7145                         sc->state = BNX2X_STATE_CLOSED;
7146                         rc = -ENOMEM;
7147                         goto bnx2x_nic_load_error0;
7148                 }
7149         }
7150
7151         if (bnx2x_alloc_fw_stats_mem(sc) != 0) {
7152                 sc->state = BNX2X_STATE_CLOSED;
7153                 rc = -ENOMEM;
7154                 goto bnx2x_nic_load_error0;
7155         }
7156
7157         if (IS_VF(sc)) {
7158                 rc = bnx2x_vf_init(sc);
7159                 if (rc) {
7160                         sc->state = BNX2X_STATE_ERROR;
7161                         goto bnx2x_nic_load_error0;
7162                 }
7163         }
7164
7165         if (IS_PF(sc)) {
7166 /* set pf load just before approaching the MCP */
7167                 bnx2x_set_pf_load(sc);
7168
7169 /* if MCP exists send load request and analyze response */
7170                 if (!BNX2X_NOMCP(sc)) {
7171                         /* attempt to load pf */
7172                         if (bnx2x_nic_load_request(sc, &load_code) != 0) {
7173                                 sc->state = BNX2X_STATE_CLOSED;
7174                                 rc = -ENXIO;
7175                                 goto bnx2x_nic_load_error1;
7176                         }
7177
7178                         /* what did the MCP say? */
7179                         if (bnx2x_nic_load_analyze_req(sc, load_code) != 0) {
7180                                 bnx2x_fw_command(sc, DRV_MSG_CODE_LOAD_DONE, 0);
7181                                 sc->state = BNX2X_STATE_CLOSED;
7182                                 rc = -ENXIO;
7183                                 goto bnx2x_nic_load_error2;
7184                         }
7185                 } else {
7186                         PMD_DRV_LOG(INFO, "Device has no MCP!");
7187                         load_code = bnx2x_nic_load_no_mcp(sc);
7188                 }
7189
7190 /* mark PMF if applicable */
7191                 bnx2x_nic_load_pmf(sc, load_code);
7192
7193 /* Init Function state controlling object */
7194                 bnx2x_init_func_obj(sc);
7195
7196 /* Initialize HW */
7197                 if (bnx2x_init_hw(sc, load_code) != 0) {
7198                         PMD_DRV_LOG(NOTICE, "HW init failed");
7199                         bnx2x_fw_command(sc, DRV_MSG_CODE_LOAD_DONE, 0);
7200                         sc->state = BNX2X_STATE_CLOSED;
7201                         rc = -ENXIO;
7202                         goto bnx2x_nic_load_error2;
7203                 }
7204         }
7205
7206         bnx2x_nic_init(sc, load_code);
7207
7208         /* Init per-function objects */
7209         if (IS_PF(sc)) {
7210                 bnx2x_init_objs(sc);
7211
7212 /* set AFEX default VLAN tag to an invalid value */
7213                 sc->devinfo.mf_info.afex_def_vlan_tag = -1;
7214
7215                 sc->state = BNX2X_STATE_OPENING_WAITING_PORT;
7216                 rc = bnx2x_func_start(sc);
7217                 if (rc) {
7218                         PMD_DRV_LOG(NOTICE, "Function start failed!");
7219                         bnx2x_fw_command(sc, DRV_MSG_CODE_LOAD_DONE, 0);
7220                         sc->state = BNX2X_STATE_ERROR;
7221                         goto bnx2x_nic_load_error3;
7222                 }
7223
7224 /* send LOAD_DONE command to MCP */
7225                 if (!BNX2X_NOMCP(sc)) {
7226                         load_code =
7227                             bnx2x_fw_command(sc, DRV_MSG_CODE_LOAD_DONE, 0);
7228                         if (!load_code) {
7229                                 PMD_DRV_LOG(NOTICE,
7230                                             "MCP response failure, aborting");
7231                                 sc->state = BNX2X_STATE_ERROR;
7232                                 rc = -ENXIO;
7233                                 goto bnx2x_nic_load_error3;
7234                         }
7235                 }
7236         }
7237
7238         rc = bnx2x_setup_leading(sc);
7239         if (rc) {
7240                 PMD_DRV_LOG(NOTICE, "Setup leading failed!");
7241                 sc->state = BNX2X_STATE_ERROR;
7242                 goto bnx2x_nic_load_error3;
7243         }
7244
7245         FOR_EACH_NONDEFAULT_ETH_QUEUE(sc, i) {
7246                 if (IS_PF(sc))
7247                         rc = bnx2x_setup_queue(sc, &sc->fp[i], FALSE);
7248                 else            /* IS_VF(sc) */
7249                         rc = bnx2x_vf_setup_queue(sc, &sc->fp[i], FALSE);
7250
7251                 if (rc) {
7252                         PMD_DRV_LOG(NOTICE, "Queue(%d) setup failed", i);
7253                         sc->state = BNX2X_STATE_ERROR;
7254                         goto bnx2x_nic_load_error3;
7255                 }
7256         }
7257
7258         rc = bnx2x_init_rss_pf(sc);
7259         if (rc) {
7260                 PMD_DRV_LOG(NOTICE, "PF RSS init failed");
7261                 sc->state = BNX2X_STATE_ERROR;
7262                 goto bnx2x_nic_load_error3;
7263         }
7264
7265         /* now when Clients are configured we are ready to work */
7266         sc->state = BNX2X_STATE_OPEN;
7267
7268         /* Configure a ucast MAC */
7269         if (IS_PF(sc)) {
7270                 rc = bnx2x_set_eth_mac(sc, TRUE);
7271         } else {                /* IS_VF(sc) */
7272                 rc = bnx2x_vf_set_mac(sc, TRUE);
7273         }
7274
7275         if (rc) {
7276                 PMD_DRV_LOG(NOTICE, "Setting Ethernet MAC failed");
7277                 sc->state = BNX2X_STATE_ERROR;
7278                 goto bnx2x_nic_load_error3;
7279         }
7280
7281         if (sc->port.pmf) {
7282                 rc = bnx2x_initial_phy_init(sc, LOAD_OPEN);
7283                 if (rc) {
7284                         sc->state = BNX2X_STATE_ERROR;
7285                         goto bnx2x_nic_load_error3;
7286                 }
7287         }
7288
7289         sc->link_params.feature_config_flags &=
7290             ~ELINK_FEATURE_CONFIG_BOOT_FROM_SAN;
7291
7292         /* start the Tx */
7293         switch (LOAD_OPEN) {
7294         case LOAD_NORMAL:
7295         case LOAD_OPEN:
7296                 break;
7297
7298         case LOAD_DIAG:
7299         case LOAD_LOOPBACK_EXT:
7300                 sc->state = BNX2X_STATE_DIAG;
7301                 break;
7302
7303         default:
7304                 break;
7305         }
7306
7307         if (sc->port.pmf) {
7308                 bnx2x_update_drv_flags(sc, 1 << DRV_FLAGS_PORT_MASK, 0);
7309         } else {
7310                 bnx2x_link_status_update(sc);
7311         }
7312
7313         if (IS_PF(sc) && SHMEM2_HAS(sc, drv_capabilities_flag)) {
7314 /* mark driver is loaded in shmem2 */
7315                 val = SHMEM2_RD(sc, drv_capabilities_flag[SC_FW_MB_IDX(sc)]);
7316                 SHMEM2_WR(sc, drv_capabilities_flag[SC_FW_MB_IDX(sc)],
7317                           (val |
7318                            DRV_FLAGS_CAPABILITIES_LOADED_SUPPORTED |
7319                            DRV_FLAGS_CAPABILITIES_LOADED_L2));
7320         }
7321
7322         /* start fast path */
7323         /* Initialize Rx filter */
7324         bnx2x_set_rx_mode(sc);
7325
7326         /* wait for all pending SP commands to complete */
7327         if (IS_PF(sc) && !bnx2x_wait_sp_comp(sc, ~0x0UL)) {
7328                 PMD_DRV_LOG(NOTICE, "Timeout waiting for all SPs to complete!");
7329                 bnx2x_periodic_stop(sc);
7330                 bnx2x_nic_unload(sc, UNLOAD_CLOSE, FALSE);
7331                 return -ENXIO;
7332         }
7333
7334         PMD_DRV_LOG(DEBUG, "NIC successfully loaded");
7335
7336         return 0;
7337
7338 bnx2x_nic_load_error3:
7339
7340         if (IS_PF(sc)) {
7341                 bnx2x_int_disable_sync(sc, 1);
7342
7343 /* clean out queued objects */
7344                 bnx2x_squeeze_objects(sc);
7345         }
7346
7347 bnx2x_nic_load_error2:
7348
7349         if (IS_PF(sc) && !BNX2X_NOMCP(sc)) {
7350                 bnx2x_fw_command(sc, DRV_MSG_CODE_UNLOAD_REQ_WOL_MCP, 0);
7351                 bnx2x_fw_command(sc, DRV_MSG_CODE_UNLOAD_DONE, 0);
7352         }
7353
7354         sc->port.pmf = 0;
7355
7356 bnx2x_nic_load_error1:
7357
7358         /* clear pf_load status, as it was already set */
7359         if (IS_PF(sc)) {
7360                 bnx2x_clear_pf_load(sc);
7361         }
7362
7363 bnx2x_nic_load_error0:
7364
7365         bnx2x_free_fw_stats_mem(sc);
7366         bnx2x_free_mem(sc);
7367
7368         return rc;
7369 }
7370
7371 /*
7372 * Handles controller initialization.
7373 */
7374 int bnx2x_init(struct bnx2x_softc *sc)
7375 {
7376         int other_engine = SC_PATH(sc) ? 0 : 1;
7377         uint8_t other_load_status, load_status;
7378         uint8_t global = FALSE;
7379         int rc;
7380
7381         /* Check if the driver is still running and bail out if it is. */
7382         if (sc->state != BNX2X_STATE_CLOSED) {
7383                 PMD_DRV_LOG(DEBUG, "Init called while driver is running!");
7384                 rc = 0;
7385                 goto bnx2x_init_done;
7386         }
7387
7388         bnx2x_set_power_state(sc, PCI_PM_D0);
7389
7390         /*
7391          * If parity occurred during the unload, then attentions and/or
7392          * RECOVERY_IN_PROGRESS may still be set. If so we want the first function
7393          * loaded on the current engine to complete the recovery. Parity recovery
7394          * is only relevant for PF driver.
7395          */
7396         if (IS_PF(sc)) {
7397                 other_load_status = bnx2x_get_load_status(sc, other_engine);
7398                 load_status = bnx2x_get_load_status(sc, SC_PATH(sc));
7399
7400                 if (!bnx2x_reset_is_done(sc, SC_PATH(sc)) ||
7401                     bnx2x_chk_parity_attn(sc, &global, TRUE)) {
7402                         do {
7403                                 /*
7404                                  * If there are attentions and they are in global blocks, set
7405                                  * the GLOBAL_RESET bit regardless whether it will be this
7406                                  * function that will complete the recovery or not.
7407                                  */
7408                                 if (global) {
7409                                         bnx2x_set_reset_global(sc);
7410                                 }
7411
7412                                 /*
7413                                  * Only the first function on the current engine should try
7414                                  * to recover in open. In case of attentions in global blocks
7415                                  * only the first in the chip should try to recover.
7416                                  */
7417                                 if ((!load_status
7418                                      && (!global ||!other_load_status))
7419                                     && bnx2x_trylock_leader_lock(sc)
7420                                     && !bnx2x_leader_reset(sc)) {
7421                                         PMD_DRV_LOG(INFO,
7422                                                     "Recovered during init");
7423                                         break;
7424                                 }
7425
7426                                 /* recovery has failed... */
7427                                 bnx2x_set_power_state(sc, PCI_PM_D3hot);
7428
7429                                 sc->recovery_state = BNX2X_RECOVERY_FAILED;
7430
7431                                 PMD_DRV_LOG(NOTICE,
7432                                             "Recovery flow hasn't properly "
7433                                             "completed yet, try again later. "
7434                                             "If you still see this message after a "
7435                                             "few retries then power cycle is required.");
7436
7437                                 rc = -ENXIO;
7438                                 goto bnx2x_init_done;
7439                         } while (0);
7440                 }
7441         }
7442
7443         sc->recovery_state = BNX2X_RECOVERY_DONE;
7444
7445         rc = bnx2x_nic_load(sc);
7446
7447 bnx2x_init_done:
7448
7449         if (rc) {
7450                 PMD_DRV_LOG(NOTICE, "Initialization failed, "
7451                             "stack notified driver is NOT running!");
7452         }
7453
7454         return rc;
7455 }
7456
7457 static void bnx2x_get_function_num(struct bnx2x_softc *sc)
7458 {
7459         uint32_t val = 0;
7460
7461         /*
7462          * Read the ME register to get the function number. The ME register
7463          * holds the relative-function number and absolute-function number. The
7464          * absolute-function number appears only in E2 and above. Before that
7465          * these bits always contained zero, therefore we cannot blindly use them.
7466          */
7467
7468         val = REG_RD(sc, BAR_ME_REGISTER);
7469
7470         sc->pfunc_rel =
7471             (uint8_t) ((val & ME_REG_PF_NUM) >> ME_REG_PF_NUM_SHIFT);
7472         sc->path_id =
7473             (uint8_t) ((val & ME_REG_ABS_PF_NUM) >> ME_REG_ABS_PF_NUM_SHIFT) &
7474             1;
7475
7476         if (CHIP_PORT_MODE(sc) == CHIP_4_PORT_MODE) {
7477                 sc->pfunc_abs = ((sc->pfunc_rel << 1) | sc->path_id);
7478         } else {
7479                 sc->pfunc_abs = (sc->pfunc_rel | sc->path_id);
7480         }
7481
7482         PMD_DRV_LOG(DEBUG,
7483                     "Relative function %d, Absolute function %d, Path %d",
7484                     sc->pfunc_rel, sc->pfunc_abs, sc->path_id);
7485 }
7486
7487 static uint32_t bnx2x_get_shmem_mf_cfg_base(struct bnx2x_softc *sc)
7488 {
7489         uint32_t shmem2_size;
7490         uint32_t offset;
7491         uint32_t mf_cfg_offset_value;
7492
7493         /* Non 57712 */
7494         offset = (SHMEM_ADDR(sc, func_mb) +
7495                   (MAX_FUNC_NUM * sizeof(struct drv_func_mb)));
7496
7497         /* 57712 plus */
7498         if (sc->devinfo.shmem2_base != 0) {
7499                 shmem2_size = SHMEM2_RD(sc, size);
7500                 if (shmem2_size > offsetof(struct shmem2_region, mf_cfg_addr)) {
7501                         mf_cfg_offset_value = SHMEM2_RD(sc, mf_cfg_addr);
7502                         if (SHMEM_MF_CFG_ADDR_NONE != mf_cfg_offset_value) {
7503                                 offset = mf_cfg_offset_value;
7504                         }
7505                 }
7506         }
7507
7508         return offset;
7509 }
7510
7511 static uint32_t bnx2x_pcie_capability_read(struct bnx2x_softc *sc, int reg)
7512 {
7513         uint32_t ret;
7514         struct bnx2x_pci_cap *caps;
7515
7516         /* ensure PCIe capability is enabled */
7517         caps = pci_find_cap(sc, PCIY_EXPRESS, BNX2X_PCI_CAP);
7518         if (NULL != caps) {
7519                 PMD_DRV_LOG(DEBUG, "Found PCIe capability: "
7520                             "id=0x%04X type=0x%04X addr=0x%08X",
7521                             caps->id, caps->type, caps->addr);
7522                 pci_read(sc, (caps->addr + reg), &ret, 2);
7523                 return ret;
7524         }
7525
7526         PMD_DRV_LOG(WARNING, "PCIe capability NOT FOUND!!!");
7527
7528         return 0;
7529 }
7530
7531 static uint8_t bnx2x_is_pcie_pending(struct bnx2x_softc *sc)
7532 {
7533         return bnx2x_pcie_capability_read(sc, PCIR_EXPRESS_DEVICE_STA) &
7534                 PCIM_EXP_STA_TRANSACTION_PND;
7535 }
7536
7537 /*
7538 * Walk the PCI capabiites list for the device to find what features are
7539 * supported. These capabilites may be enabled/disabled by firmware so it's
7540 * best to walk the list rather than make assumptions.
7541 */
7542 static void bnx2x_probe_pci_caps(struct bnx2x_softc *sc)
7543 {
7544         PMD_INIT_FUNC_TRACE();
7545
7546         struct bnx2x_pci_cap *caps;
7547         uint16_t link_status;
7548         int reg = 0;
7549
7550         /* check if PCI Power Management is enabled */
7551         caps = pci_find_cap(sc, PCIY_PMG, BNX2X_PCI_CAP);
7552         if (NULL != caps) {
7553                 PMD_DRV_LOG(DEBUG, "Found PM capability: "
7554                             "id=0x%04X type=0x%04X addr=0x%08X",
7555                             caps->id, caps->type, caps->addr);
7556
7557                 sc->devinfo.pcie_cap_flags |= BNX2X_PM_CAPABLE_FLAG;
7558                 sc->devinfo.pcie_pm_cap_reg = caps->addr;
7559         }
7560
7561         link_status = bnx2x_pcie_capability_read(sc, PCIR_EXPRESS_LINK_STA);
7562
7563         sc->devinfo.pcie_link_speed = (link_status & PCIM_LINK_STA_SPEED);
7564         sc->devinfo.pcie_link_width =
7565             ((link_status & PCIM_LINK_STA_WIDTH) >> 4);
7566
7567         PMD_DRV_LOG(DEBUG, "PCIe link speed=%d width=%d",
7568                     sc->devinfo.pcie_link_speed, sc->devinfo.pcie_link_width);
7569
7570         sc->devinfo.pcie_cap_flags |= BNX2X_PCIE_CAPABLE_FLAG;
7571
7572         /* check if MSI capability is enabled */
7573         caps = pci_find_cap(sc, PCIY_MSI, BNX2X_PCI_CAP);
7574         if (NULL != caps) {
7575                 PMD_DRV_LOG(DEBUG, "Found MSI capability at 0x%04x", reg);
7576
7577                 sc->devinfo.pcie_cap_flags |= BNX2X_MSI_CAPABLE_FLAG;
7578                 sc->devinfo.pcie_msi_cap_reg = caps->addr;
7579         }
7580
7581         /* check if MSI-X capability is enabled */
7582         caps = pci_find_cap(sc, PCIY_MSIX, BNX2X_PCI_CAP);
7583         if (NULL != caps) {
7584                 PMD_DRV_LOG(DEBUG, "Found MSI-X capability at 0x%04x", reg);
7585
7586                 sc->devinfo.pcie_cap_flags |= BNX2X_MSIX_CAPABLE_FLAG;
7587                 sc->devinfo.pcie_msix_cap_reg = caps->addr;
7588         }
7589 }
7590
7591 static int bnx2x_get_shmem_mf_cfg_info_sd(struct bnx2x_softc *sc)
7592 {
7593         struct bnx2x_mf_info *mf_info = &sc->devinfo.mf_info;
7594         uint32_t val;
7595
7596         /* get the outer vlan if we're in switch-dependent mode */
7597
7598         val = MFCFG_RD(sc, func_mf_config[SC_ABS_FUNC(sc)].e1hov_tag);
7599         mf_info->ext_id = (uint16_t) val;
7600
7601         mf_info->multi_vnics_mode = 1;
7602
7603         if (!VALID_OVLAN(mf_info->ext_id)) {
7604                 PMD_DRV_LOG(NOTICE, "Invalid VLAN (%d)", mf_info->ext_id);
7605                 return 1;
7606         }
7607
7608         /* get the capabilities */
7609         if ((mf_info->mf_config[SC_VN(sc)] & FUNC_MF_CFG_PROTOCOL_MASK) ==
7610             FUNC_MF_CFG_PROTOCOL_ISCSI) {
7611                 mf_info->mf_protos_supported |= MF_PROTO_SUPPORT_ISCSI;
7612         } else if ((mf_info->mf_config[SC_VN(sc)] & FUNC_MF_CFG_PROTOCOL_MASK)
7613                    == FUNC_MF_CFG_PROTOCOL_FCOE) {
7614                 mf_info->mf_protos_supported |= MF_PROTO_SUPPORT_FCOE;
7615         } else {
7616                 mf_info->mf_protos_supported |= MF_PROTO_SUPPORT_ETHERNET;
7617         }
7618
7619         mf_info->vnics_per_port =
7620             (CHIP_PORT_MODE(sc) == CHIP_4_PORT_MODE) ? 2 : 4;
7621
7622         return 0;
7623 }
7624
7625 static uint32_t bnx2x_get_shmem_ext_proto_support_flags(struct bnx2x_softc *sc)
7626 {
7627         uint32_t retval = 0;
7628         uint32_t val;
7629
7630         val = MFCFG_RD(sc, func_ext_config[SC_ABS_FUNC(sc)].func_cfg);
7631
7632         if (val & MACP_FUNC_CFG_FLAGS_ENABLED) {
7633                 if (val & MACP_FUNC_CFG_FLAGS_ETHERNET) {
7634                         retval |= MF_PROTO_SUPPORT_ETHERNET;
7635                 }
7636                 if (val & MACP_FUNC_CFG_FLAGS_ISCSI_OFFLOAD) {
7637                         retval |= MF_PROTO_SUPPORT_ISCSI;
7638                 }
7639                 if (val & MACP_FUNC_CFG_FLAGS_FCOE_OFFLOAD) {
7640                         retval |= MF_PROTO_SUPPORT_FCOE;
7641                 }
7642         }
7643
7644         return retval;
7645 }
7646
7647 static int bnx2x_get_shmem_mf_cfg_info_si(struct bnx2x_softc *sc)
7648 {
7649         struct bnx2x_mf_info *mf_info = &sc->devinfo.mf_info;
7650         uint32_t val;
7651
7652         /*
7653          * There is no outer vlan if we're in switch-independent mode.
7654          * If the mac is valid then assume multi-function.
7655          */
7656
7657         val = MFCFG_RD(sc, func_ext_config[SC_ABS_FUNC(sc)].func_cfg);
7658
7659         mf_info->multi_vnics_mode = ((val & MACP_FUNC_CFG_FLAGS_MASK) != 0);
7660
7661         mf_info->mf_protos_supported =
7662             bnx2x_get_shmem_ext_proto_support_flags(sc);
7663
7664         mf_info->vnics_per_port =
7665             (CHIP_PORT_MODE(sc) == CHIP_4_PORT_MODE) ? 2 : 4;
7666
7667         return 0;
7668 }
7669
7670 static int bnx2x_get_shmem_mf_cfg_info_niv(struct bnx2x_softc *sc)
7671 {
7672         struct bnx2x_mf_info *mf_info = &sc->devinfo.mf_info;
7673         uint32_t e1hov_tag;
7674         uint32_t func_config;
7675         uint32_t niv_config;
7676
7677         mf_info->multi_vnics_mode = 1;
7678
7679         e1hov_tag = MFCFG_RD(sc, func_mf_config[SC_ABS_FUNC(sc)].e1hov_tag);
7680         func_config = MFCFG_RD(sc, func_mf_config[SC_ABS_FUNC(sc)].config);
7681         niv_config = MFCFG_RD(sc, func_mf_config[SC_ABS_FUNC(sc)].afex_config);
7682
7683         mf_info->ext_id =
7684             (uint16_t) ((e1hov_tag & FUNC_MF_CFG_E1HOV_TAG_MASK) >>
7685                         FUNC_MF_CFG_E1HOV_TAG_SHIFT);
7686
7687         mf_info->default_vlan =
7688             (uint16_t) ((e1hov_tag & FUNC_MF_CFG_AFEX_VLAN_MASK) >>
7689                         FUNC_MF_CFG_AFEX_VLAN_SHIFT);
7690
7691         mf_info->niv_allowed_priorities =
7692             (uint8_t) ((niv_config & FUNC_MF_CFG_AFEX_COS_FILTER_MASK) >>
7693                        FUNC_MF_CFG_AFEX_COS_FILTER_SHIFT);
7694
7695         mf_info->niv_default_cos =
7696             (uint8_t) ((func_config & FUNC_MF_CFG_TRANSMIT_PRIORITY_MASK) >>
7697                        FUNC_MF_CFG_TRANSMIT_PRIORITY_SHIFT);
7698
7699         mf_info->afex_vlan_mode =
7700             ((niv_config & FUNC_MF_CFG_AFEX_VLAN_MODE_MASK) >>
7701              FUNC_MF_CFG_AFEX_VLAN_MODE_SHIFT);
7702
7703         mf_info->niv_mba_enabled =
7704             ((niv_config & FUNC_MF_CFG_AFEX_MBA_ENABLED_MASK) >>
7705              FUNC_MF_CFG_AFEX_MBA_ENABLED_SHIFT);
7706
7707         mf_info->mf_protos_supported =
7708             bnx2x_get_shmem_ext_proto_support_flags(sc);
7709
7710         mf_info->vnics_per_port =
7711             (CHIP_PORT_MODE(sc) == CHIP_4_PORT_MODE) ? 2 : 4;
7712
7713         return 0;
7714 }
7715
7716 static int bnx2x_check_valid_mf_cfg(struct bnx2x_softc *sc)
7717 {
7718         struct bnx2x_mf_info *mf_info = &sc->devinfo.mf_info;
7719         uint32_t mf_cfg1;
7720         uint32_t mf_cfg2;
7721         uint32_t ovlan1;
7722         uint32_t ovlan2;
7723         uint8_t i, j;
7724
7725         /* various MF mode sanity checks... */
7726
7727         if (mf_info->mf_config[SC_VN(sc)] & FUNC_MF_CFG_FUNC_HIDE) {
7728                 PMD_DRV_LOG(NOTICE,
7729                             "Enumerated function %d is marked as hidden",
7730                             SC_PORT(sc));
7731                 return 1;
7732         }
7733
7734         if ((mf_info->vnics_per_port > 1) && !mf_info->multi_vnics_mode) {
7735                 PMD_DRV_LOG(NOTICE, "vnics_per_port=%d multi_vnics_mode=%d",
7736                             mf_info->vnics_per_port, mf_info->multi_vnics_mode);
7737                 return 1;
7738         }
7739
7740         if (mf_info->mf_mode == MULTI_FUNCTION_SD) {
7741 /* vnic id > 0 must have valid ovlan in switch-dependent mode */
7742                 if ((SC_VN(sc) > 0) && !VALID_OVLAN(OVLAN(sc))) {
7743                         PMD_DRV_LOG(NOTICE, "mf_mode=SD vnic_id=%d ovlan=%d",
7744                                     SC_VN(sc), OVLAN(sc));
7745                         return 1;
7746                 }
7747
7748                 if (!VALID_OVLAN(OVLAN(sc)) && mf_info->multi_vnics_mode) {
7749                         PMD_DRV_LOG(NOTICE,
7750                                     "mf_mode=SD multi_vnics_mode=%d ovlan=%d",
7751                                     mf_info->multi_vnics_mode, OVLAN(sc));
7752                         return 1;
7753                 }
7754
7755 /*
7756  * Verify all functions are either MF or SF mode. If MF, make sure
7757  * sure that all non-hidden functions have a valid ovlan. If SF,
7758  * make sure that all non-hidden functions have an invalid ovlan.
7759  */
7760                 FOREACH_ABS_FUNC_IN_PORT(sc, i) {
7761                         mf_cfg1 = MFCFG_RD(sc, func_mf_config[i].config);
7762                         ovlan1 = MFCFG_RD(sc, func_mf_config[i].e1hov_tag);
7763                         if (!(mf_cfg1 & FUNC_MF_CFG_FUNC_HIDE) &&
7764                             (((mf_info->multi_vnics_mode)
7765                               && !VALID_OVLAN(ovlan1))
7766                              || ((!mf_info->multi_vnics_mode)
7767                                  && VALID_OVLAN(ovlan1)))) {
7768                                 PMD_DRV_LOG(NOTICE,
7769                                             "mf_mode=SD function %d MF config "
7770                                             "mismatch, multi_vnics_mode=%d ovlan=%d",
7771                                             i, mf_info->multi_vnics_mode,
7772                                             ovlan1);
7773                                 return 1;
7774                         }
7775                 }
7776
7777 /* Verify all funcs on the same port each have a different ovlan. */
7778                 FOREACH_ABS_FUNC_IN_PORT(sc, i) {
7779                         mf_cfg1 = MFCFG_RD(sc, func_mf_config[i].config);
7780                         ovlan1 = MFCFG_RD(sc, func_mf_config[i].e1hov_tag);
7781                         /* iterate from the next function on the port to the max func */
7782                         for (j = i + 2; j < MAX_FUNC_NUM; j += 2) {
7783                                 mf_cfg2 =
7784                                     MFCFG_RD(sc, func_mf_config[j].config);
7785                                 ovlan2 =
7786                                     MFCFG_RD(sc, func_mf_config[j].e1hov_tag);
7787                                 if (!(mf_cfg1 & FUNC_MF_CFG_FUNC_HIDE)
7788                                     && VALID_OVLAN(ovlan1)
7789                                     && !(mf_cfg2 & FUNC_MF_CFG_FUNC_HIDE)
7790                                     && VALID_OVLAN(ovlan2)
7791                                     && (ovlan1 == ovlan2)) {
7792                                         PMD_DRV_LOG(NOTICE,
7793                                                     "mf_mode=SD functions %d and %d "
7794                                                     "have the same ovlan (%d)",
7795                                                     i, j, ovlan1);
7796                                         return 1;
7797                                 }
7798                         }
7799                 }
7800         }
7801         /* MULTI_FUNCTION_SD */
7802         return 0;
7803 }
7804
7805 static int bnx2x_get_mf_cfg_info(struct bnx2x_softc *sc)
7806 {
7807         struct bnx2x_mf_info *mf_info = &sc->devinfo.mf_info;
7808         uint32_t val, mac_upper;
7809         uint8_t i, vnic;
7810
7811         /* initialize mf_info defaults */
7812         mf_info->vnics_per_port = 1;
7813         mf_info->multi_vnics_mode = FALSE;
7814         mf_info->path_has_ovlan = FALSE;
7815         mf_info->mf_mode = SINGLE_FUNCTION;
7816
7817         if (!CHIP_IS_MF_CAP(sc)) {
7818                 return 0;
7819         }
7820
7821         if (sc->devinfo.mf_cfg_base == SHMEM_MF_CFG_ADDR_NONE) {
7822                 PMD_DRV_LOG(NOTICE, "Invalid mf_cfg_base!");
7823                 return 1;
7824         }
7825
7826         /* get the MF mode (switch dependent / independent / single-function) */
7827
7828         val = SHMEM_RD(sc, dev_info.shared_feature_config.config);
7829
7830         switch (val & SHARED_FEAT_CFG_FORCE_SF_MODE_MASK) {
7831         case SHARED_FEAT_CFG_FORCE_SF_MODE_SWITCH_INDEPT:
7832
7833                 mac_upper =
7834                     MFCFG_RD(sc, func_mf_config[SC_ABS_FUNC(sc)].mac_upper);
7835
7836                 /* check for legal upper mac bytes */
7837                 if (mac_upper != FUNC_MF_CFG_UPPERMAC_DEFAULT) {
7838                         mf_info->mf_mode = MULTI_FUNCTION_SI;
7839                 } else {
7840                         PMD_DRV_LOG(NOTICE,
7841                                     "Invalid config for Switch Independent mode");
7842                 }
7843
7844                 break;
7845
7846         case SHARED_FEAT_CFG_FORCE_SF_MODE_MF_ALLOWED:
7847         case SHARED_FEAT_CFG_FORCE_SF_MODE_SPIO4:
7848
7849                 /* get outer vlan configuration */
7850                 val = MFCFG_RD(sc, func_mf_config[SC_ABS_FUNC(sc)].e1hov_tag);
7851
7852                 if ((val & FUNC_MF_CFG_E1HOV_TAG_MASK) !=
7853                     FUNC_MF_CFG_E1HOV_TAG_DEFAULT) {
7854                         mf_info->mf_mode = MULTI_FUNCTION_SD;
7855                 } else {
7856                         PMD_DRV_LOG(NOTICE,
7857                                     "Invalid config for Switch Dependent mode");
7858                 }
7859
7860                 break;
7861
7862         case SHARED_FEAT_CFG_FORCE_SF_MODE_FORCED_SF:
7863
7864                 /* not in MF mode, vnics_per_port=1 and multi_vnics_mode=FALSE */
7865                 return 0;
7866
7867         case SHARED_FEAT_CFG_FORCE_SF_MODE_AFEX_MODE:
7868
7869                 /*
7870                  * Mark MF mode as NIV if MCP version includes NPAR-SD support
7871                  * and the MAC address is valid.
7872                  */
7873                 mac_upper =
7874                     MFCFG_RD(sc, func_mf_config[SC_ABS_FUNC(sc)].mac_upper);
7875
7876                 if ((SHMEM2_HAS(sc, afex_driver_support)) &&
7877                     (mac_upper != FUNC_MF_CFG_UPPERMAC_DEFAULT)) {
7878                         mf_info->mf_mode = MULTI_FUNCTION_AFEX;
7879                 } else {
7880                         PMD_DRV_LOG(NOTICE, "Invalid config for AFEX mode");
7881                 }
7882
7883                 break;
7884
7885         default:
7886
7887                 PMD_DRV_LOG(NOTICE, "Unknown MF mode (0x%08x)",
7888                             (val & SHARED_FEAT_CFG_FORCE_SF_MODE_MASK));
7889
7890                 return 1;
7891         }
7892
7893         /* set path mf_mode (which could be different than function mf_mode) */
7894         if (mf_info->mf_mode == MULTI_FUNCTION_SD) {
7895                 mf_info->path_has_ovlan = TRUE;
7896         } else if (mf_info->mf_mode == SINGLE_FUNCTION) {
7897 /*
7898  * Decide on path multi vnics mode. If we're not in MF mode and in
7899  * 4-port mode, this is good enough to check vnic-0 of the other port
7900  * on the same path
7901  */
7902                 if (CHIP_PORT_MODE(sc) == CHIP_4_PORT_MODE) {
7903                         uint8_t other_port = !(PORT_ID(sc) & 1);
7904                         uint8_t abs_func_other_port =
7905                             (SC_PATH(sc) + (2 * other_port));
7906
7907                         val =
7908                             MFCFG_RD(sc,
7909                                      func_mf_config
7910                                      [abs_func_other_port].e1hov_tag);
7911
7912                         mf_info->path_has_ovlan = VALID_OVLAN((uint16_t) val);
7913                 }
7914         }
7915
7916         if (mf_info->mf_mode == SINGLE_FUNCTION) {
7917 /* invalid MF config */
7918                 if (SC_VN(sc) >= 1) {
7919                         PMD_DRV_LOG(NOTICE, "VNIC ID >= 1 in SF mode");
7920                         return 1;
7921                 }
7922
7923                 return 0;
7924         }
7925
7926         /* get the MF configuration */
7927         mf_info->mf_config[SC_VN(sc)] =
7928             MFCFG_RD(sc, func_mf_config[SC_ABS_FUNC(sc)].config);
7929
7930         switch (mf_info->mf_mode) {
7931         case MULTI_FUNCTION_SD:
7932
7933                 bnx2x_get_shmem_mf_cfg_info_sd(sc);
7934                 break;
7935
7936         case MULTI_FUNCTION_SI:
7937
7938                 bnx2x_get_shmem_mf_cfg_info_si(sc);
7939                 break;
7940
7941         case MULTI_FUNCTION_AFEX:
7942
7943                 bnx2x_get_shmem_mf_cfg_info_niv(sc);
7944                 break;
7945
7946         default:
7947
7948                 PMD_DRV_LOG(NOTICE, "Get MF config failed (mf_mode=0x%08x)",
7949                             mf_info->mf_mode);
7950                 return 1;
7951         }
7952
7953         /* get the congestion management parameters */
7954
7955         vnic = 0;
7956         FOREACH_ABS_FUNC_IN_PORT(sc, i) {
7957 /* get min/max bw */
7958                 val = MFCFG_RD(sc, func_mf_config[i].config);
7959                 mf_info->min_bw[vnic] =
7960                     ((val & FUNC_MF_CFG_MIN_BW_MASK) >>
7961                      FUNC_MF_CFG_MIN_BW_SHIFT);
7962                 mf_info->max_bw[vnic] =
7963                     ((val & FUNC_MF_CFG_MAX_BW_MASK) >>
7964                      FUNC_MF_CFG_MAX_BW_SHIFT);
7965                 vnic++;
7966         }
7967
7968         return bnx2x_check_valid_mf_cfg(sc);
7969 }
7970
7971 static int bnx2x_get_shmem_info(struct bnx2x_softc *sc)
7972 {
7973         int port;
7974         uint32_t mac_hi, mac_lo, val;
7975
7976         PMD_INIT_FUNC_TRACE();
7977
7978         port = SC_PORT(sc);
7979         mac_hi = mac_lo = 0;
7980
7981         sc->link_params.sc = sc;
7982         sc->link_params.port = port;
7983
7984         /* get the hardware config info */
7985         sc->devinfo.hw_config = SHMEM_RD(sc, dev_info.shared_hw_config.config);
7986         sc->devinfo.hw_config2 =
7987             SHMEM_RD(sc, dev_info.shared_hw_config.config2);
7988
7989         sc->link_params.hw_led_mode =
7990             ((sc->devinfo.hw_config & SHARED_HW_CFG_LED_MODE_MASK) >>
7991              SHARED_HW_CFG_LED_MODE_SHIFT);
7992
7993         /* get the port feature config */
7994         sc->port.config =
7995             SHMEM_RD(sc, dev_info.port_feature_config[port].config);
7996
7997         /* get the link params */
7998         sc->link_params.speed_cap_mask[ELINK_INT_PHY] =
7999             SHMEM_RD(sc, dev_info.port_hw_config[port].speed_capability_mask)
8000             & PORT_HW_CFG_SPEED_CAPABILITY_D0_MASK;
8001         sc->link_params.speed_cap_mask[ELINK_EXT_PHY1] =
8002             SHMEM_RD(sc, dev_info.port_hw_config[port].speed_capability_mask2)
8003             & PORT_HW_CFG_SPEED_CAPABILITY_D0_MASK;
8004
8005         /* get the lane config */
8006         sc->link_params.lane_config =
8007             SHMEM_RD(sc, dev_info.port_hw_config[port].lane_config);
8008
8009         /* get the link config */
8010         val = SHMEM_RD(sc, dev_info.port_feature_config[port].link_config);
8011         sc->port.link_config[ELINK_INT_PHY] = val;
8012         sc->link_params.switch_cfg = (val & PORT_FEATURE_CONNECTED_SWITCH_MASK);
8013         sc->port.link_config[ELINK_EXT_PHY1] =
8014             SHMEM_RD(sc, dev_info.port_feature_config[port].link_config2);
8015
8016         /* get the override preemphasis flag and enable it or turn it off */
8017         val = SHMEM_RD(sc, dev_info.shared_feature_config.config);
8018         if (val & SHARED_FEAT_CFG_OVERRIDE_PREEMPHASIS_CFG_ENABLED) {
8019                 sc->link_params.feature_config_flags |=
8020                     ELINK_FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED;
8021         } else {
8022                 sc->link_params.feature_config_flags &=
8023                     ~ELINK_FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED;
8024         }
8025
8026         /* get the initial value of the link params */
8027         sc->link_params.multi_phy_config =
8028             SHMEM_RD(sc, dev_info.port_hw_config[port].multi_phy_config);
8029
8030         /* get external phy info */
8031         sc->port.ext_phy_config =
8032             SHMEM_RD(sc, dev_info.port_hw_config[port].external_phy_config);
8033
8034         /* get the multifunction configuration */
8035         bnx2x_get_mf_cfg_info(sc);
8036
8037         /* get the mac address */
8038         if (IS_MF(sc)) {
8039                 mac_hi =
8040                     MFCFG_RD(sc, func_mf_config[SC_ABS_FUNC(sc)].mac_upper);
8041                 mac_lo =
8042                     MFCFG_RD(sc, func_mf_config[SC_ABS_FUNC(sc)].mac_lower);
8043         } else {
8044                 mac_hi = SHMEM_RD(sc, dev_info.port_hw_config[port].mac_upper);
8045                 mac_lo = SHMEM_RD(sc, dev_info.port_hw_config[port].mac_lower);
8046         }
8047
8048         if ((mac_lo == 0) && (mac_hi == 0)) {
8049                 *sc->mac_addr_str = 0;
8050                 PMD_DRV_LOG(NOTICE, "No Ethernet address programmed!");
8051         } else {
8052                 sc->link_params.mac_addr[0] = (uint8_t) (mac_hi >> 8);
8053                 sc->link_params.mac_addr[1] = (uint8_t) (mac_hi);
8054                 sc->link_params.mac_addr[2] = (uint8_t) (mac_lo >> 24);
8055                 sc->link_params.mac_addr[3] = (uint8_t) (mac_lo >> 16);
8056                 sc->link_params.mac_addr[4] = (uint8_t) (mac_lo >> 8);
8057                 sc->link_params.mac_addr[5] = (uint8_t) (mac_lo);
8058                 snprintf(sc->mac_addr_str, sizeof(sc->mac_addr_str),
8059                          "%02x:%02x:%02x:%02x:%02x:%02x",
8060                          sc->link_params.mac_addr[0],
8061                          sc->link_params.mac_addr[1],
8062                          sc->link_params.mac_addr[2],
8063                          sc->link_params.mac_addr[3],
8064                          sc->link_params.mac_addr[4],
8065                          sc->link_params.mac_addr[5]);
8066                 PMD_DRV_LOG(DEBUG, "Ethernet address: %s", sc->mac_addr_str);
8067         }
8068
8069         return 0;
8070 }
8071
8072 static void bnx2x_media_detect(struct bnx2x_softc *sc)
8073 {
8074         uint32_t phy_idx = bnx2x_get_cur_phy_idx(sc);
8075         switch (sc->link_params.phy[phy_idx].media_type) {
8076         case ELINK_ETH_PHY_SFPP_10G_FIBER:
8077         case ELINK_ETH_PHY_SFP_1G_FIBER:
8078         case ELINK_ETH_PHY_XFP_FIBER:
8079         case ELINK_ETH_PHY_KR:
8080         case ELINK_ETH_PHY_CX4:
8081                 PMD_DRV_LOG(INFO, "Found 10GBase-CX4 media.");
8082                 sc->media = IFM_10G_CX4;
8083                 break;
8084         case ELINK_ETH_PHY_DA_TWINAX:
8085                 PMD_DRV_LOG(INFO, "Found 10Gb Twinax media.");
8086                 sc->media = IFM_10G_TWINAX;
8087                 break;
8088         case ELINK_ETH_PHY_BASE_T:
8089                 PMD_DRV_LOG(INFO, "Found 10GBase-T media.");
8090                 sc->media = IFM_10G_T;
8091                 break;
8092         case ELINK_ETH_PHY_NOT_PRESENT:
8093                 PMD_DRV_LOG(INFO, "Media not present.");
8094                 sc->media = 0;
8095                 break;
8096         case ELINK_ETH_PHY_UNSPECIFIED:
8097         default:
8098                 PMD_DRV_LOG(INFO, "Unknown media!");
8099                 sc->media = 0;
8100                 break;
8101         }
8102 }
8103
8104 #define GET_FIELD(value, fname)                     \
8105 (((value) & (fname##_MASK)) >> (fname##_SHIFT))
8106 #define IGU_FID(val) GET_FIELD((val), IGU_REG_MAPPING_MEMORY_FID)
8107 #define IGU_VEC(val) GET_FIELD((val), IGU_REG_MAPPING_MEMORY_VECTOR)
8108
8109 static int bnx2x_get_igu_cam_info(struct bnx2x_softc *sc)
8110 {
8111         int pfid = SC_FUNC(sc);
8112         int igu_sb_id;
8113         uint32_t val;
8114         uint8_t fid, igu_sb_cnt = 0;
8115
8116         sc->igu_base_sb = 0xff;
8117
8118         if (CHIP_INT_MODE_IS_BC(sc)) {
8119                 int vn = SC_VN(sc);
8120                 igu_sb_cnt = sc->igu_sb_cnt;
8121                 sc->igu_base_sb = ((CHIP_IS_MODE_4_PORT(sc) ? pfid : vn) *
8122                                    FP_SB_MAX_E1x);
8123                 sc->igu_dsb_id = (E1HVN_MAX * FP_SB_MAX_E1x +
8124                                   (CHIP_IS_MODE_4_PORT(sc) ? pfid : vn));
8125                 return 0;
8126         }
8127
8128         /* IGU in normal mode - read CAM */
8129         for (igu_sb_id = 0;
8130              igu_sb_id < IGU_REG_MAPPING_MEMORY_SIZE; igu_sb_id++) {
8131                 val = REG_RD(sc, IGU_REG_MAPPING_MEMORY + igu_sb_id * 4);
8132                 if (!(val & IGU_REG_MAPPING_MEMORY_VALID)) {
8133                         continue;
8134                 }
8135                 fid = IGU_FID(val);
8136                 if (fid & IGU_FID_ENCODE_IS_PF) {
8137                         if ((fid & IGU_FID_PF_NUM_MASK) != pfid) {
8138                                 continue;
8139                         }
8140                         if (IGU_VEC(val) == 0) {
8141                                 /* default status block */
8142                                 sc->igu_dsb_id = igu_sb_id;
8143                         } else {
8144                                 if (sc->igu_base_sb == 0xff) {
8145                                         sc->igu_base_sb = igu_sb_id;
8146                                 }
8147                                 igu_sb_cnt++;
8148                         }
8149                 }
8150         }
8151
8152         /*
8153          * Due to new PF resource allocation by MFW T7.4 and above, it's optional
8154          * that number of CAM entries will not be equal to the value advertised in
8155          * PCI. Driver should use the minimal value of both as the actual status
8156          * block count
8157          */
8158         sc->igu_sb_cnt = min(sc->igu_sb_cnt, igu_sb_cnt);
8159
8160         if (igu_sb_cnt == 0) {
8161                 PMD_DRV_LOG(ERR, "CAM configuration error");
8162                 return -1;
8163         }
8164
8165         return 0;
8166 }
8167
8168 /*
8169 * Gather various information from the device config space, the device itself,
8170 * shmem, and the user input.
8171 */
8172 static int bnx2x_get_device_info(struct bnx2x_softc *sc)
8173 {
8174         uint32_t val;
8175         int rc;
8176
8177         /* get the chip revision (chip metal comes from pci config space) */
8178         sc->devinfo.chip_id = sc->link_params.chip_id =
8179             (((REG_RD(sc, MISC_REG_CHIP_NUM) & 0xffff) << 16) |
8180              ((REG_RD(sc, MISC_REG_CHIP_REV) & 0xf) << 12) |
8181              (((REG_RD(sc, PCICFG_OFFSET + PCI_ID_VAL3) >> 24) & 0xf) << 4) |
8182              ((REG_RD(sc, MISC_REG_BOND_ID) & 0xf) << 0));
8183
8184         /* force 57811 according to MISC register */
8185         if (REG_RD(sc, MISC_REG_CHIP_TYPE) & MISC_REG_CHIP_TYPE_57811_MASK) {
8186                 if (CHIP_IS_57810(sc)) {
8187                         sc->devinfo.chip_id = ((CHIP_NUM_57811 << 16) |
8188                                                (sc->
8189                                                 devinfo.chip_id & 0x0000ffff));
8190                 } else if (CHIP_IS_57810_MF(sc)) {
8191                         sc->devinfo.chip_id = ((CHIP_NUM_57811_MF << 16) |
8192                                                (sc->
8193                                                 devinfo.chip_id & 0x0000ffff));
8194                 }
8195                 sc->devinfo.chip_id |= 0x1;
8196         }
8197
8198         PMD_DRV_LOG(DEBUG,
8199                     "chip_id=0x%08x (num=0x%04x rev=0x%01x metal=0x%02x bond=0x%01x)",
8200                     sc->devinfo.chip_id,
8201                     ((sc->devinfo.chip_id >> 16) & 0xffff),
8202                     ((sc->devinfo.chip_id >> 12) & 0xf),
8203                     ((sc->devinfo.chip_id >> 4) & 0xff),
8204                     ((sc->devinfo.chip_id >> 0) & 0xf));
8205
8206         val = (REG_RD(sc, 0x2874) & 0x55);
8207         if ((sc->devinfo.chip_id & 0x1) || (CHIP_IS_E1H(sc) && (val == 0x55))) {
8208                 sc->flags |= BNX2X_ONE_PORT_FLAG;
8209                 PMD_DRV_LOG(DEBUG, "single port device");
8210         }
8211
8212         /* set the doorbell size */
8213         sc->doorbell_size = (1 << BNX2X_DB_SHIFT);
8214
8215         /* determine whether the device is in 2 port or 4 port mode */
8216         sc->devinfo.chip_port_mode = CHIP_PORT_MODE_NONE;       /* E1h */
8217         if (CHIP_IS_E2E3(sc)) {
8218 /*
8219  * Read port4mode_en_ovwr[0]:
8220  *   If 1, four port mode is in port4mode_en_ovwr[1].
8221  *   If 0, four port mode is in port4mode_en[0].
8222  */
8223                 val = REG_RD(sc, MISC_REG_PORT4MODE_EN_OVWR);
8224                 if (val & 1) {
8225                         val = ((val >> 1) & 1);
8226                 } else {
8227                         val = REG_RD(sc, MISC_REG_PORT4MODE_EN);
8228                 }
8229
8230                 sc->devinfo.chip_port_mode =
8231                     (val) ? CHIP_4_PORT_MODE : CHIP_2_PORT_MODE;
8232
8233                 PMD_DRV_LOG(DEBUG, "Port mode = %s", (val) ? "4" : "2");
8234         }
8235
8236         /* get the function and path info for the device */
8237         bnx2x_get_function_num(sc);
8238
8239         /* get the shared memory base address */
8240         sc->devinfo.shmem_base =
8241             sc->link_params.shmem_base = REG_RD(sc, MISC_REG_SHARED_MEM_ADDR);
8242         sc->devinfo.shmem2_base =
8243             REG_RD(sc, (SC_PATH(sc) ? MISC_REG_GENERIC_CR_1 :
8244                         MISC_REG_GENERIC_CR_0));
8245
8246         if (!sc->devinfo.shmem_base) {
8247 /* this should ONLY prevent upcoming shmem reads */
8248                 PMD_DRV_LOG(INFO, "MCP not active");
8249                 sc->flags |= BNX2X_NO_MCP_FLAG;
8250                 return 0;
8251         }
8252
8253         /* make sure the shared memory contents are valid */
8254         val = SHMEM_RD(sc, validity_map[SC_PORT(sc)]);
8255         if ((val & (SHR_MEM_VALIDITY_DEV_INFO | SHR_MEM_VALIDITY_MB)) !=
8256             (SHR_MEM_VALIDITY_DEV_INFO | SHR_MEM_VALIDITY_MB)) {
8257                 PMD_DRV_LOG(NOTICE, "Invalid SHMEM validity signature: 0x%08x",
8258                             val);
8259                 return 0;
8260         }
8261
8262         /* get the bootcode version */
8263         sc->devinfo.bc_ver = SHMEM_RD(sc, dev_info.bc_rev);
8264         snprintf(sc->devinfo.bc_ver_str,
8265                  sizeof(sc->devinfo.bc_ver_str),
8266                  "%d.%d.%d",
8267                  ((sc->devinfo.bc_ver >> 24) & 0xff),
8268                  ((sc->devinfo.bc_ver >> 16) & 0xff),
8269                  ((sc->devinfo.bc_ver >> 8) & 0xff));
8270         PMD_DRV_LOG(INFO, "Bootcode version: %s", sc->devinfo.bc_ver_str);
8271
8272         /* get the bootcode shmem address */
8273         sc->devinfo.mf_cfg_base = bnx2x_get_shmem_mf_cfg_base(sc);
8274
8275         /* clean indirect addresses as they're not used */
8276         pci_write_long(sc, PCICFG_GRC_ADDRESS, 0);
8277         if (IS_PF(sc)) {
8278                 REG_WR(sc, PXP2_REG_PGL_ADDR_88_F0, 0);
8279                 REG_WR(sc, PXP2_REG_PGL_ADDR_8C_F0, 0);
8280                 REG_WR(sc, PXP2_REG_PGL_ADDR_90_F0, 0);
8281                 REG_WR(sc, PXP2_REG_PGL_ADDR_94_F0, 0);
8282                 if (CHIP_IS_E1x(sc)) {
8283                         REG_WR(sc, PXP2_REG_PGL_ADDR_88_F1, 0);
8284                         REG_WR(sc, PXP2_REG_PGL_ADDR_8C_F1, 0);
8285                         REG_WR(sc, PXP2_REG_PGL_ADDR_90_F1, 0);
8286                         REG_WR(sc, PXP2_REG_PGL_ADDR_94_F1, 0);
8287                 }
8288         }
8289
8290         /* get the nvram size */
8291         val = REG_RD(sc, MCP_REG_MCPR_NVM_CFG4);
8292         sc->devinfo.flash_size =
8293             (NVRAM_1MB_SIZE << (val & MCPR_NVM_CFG4_FLASH_SIZE));
8294
8295         bnx2x_set_power_state(sc, PCI_PM_D0);
8296         /* get various configuration parameters from shmem */
8297         bnx2x_get_shmem_info(sc);
8298
8299         /* initialize IGU parameters */
8300         if (CHIP_IS_E1x(sc)) {
8301                 sc->devinfo.int_block = INT_BLOCK_HC;
8302                 sc->igu_dsb_id = DEF_SB_IGU_ID;
8303                 sc->igu_base_sb = 0;
8304         } else {
8305                 sc->devinfo.int_block = INT_BLOCK_IGU;
8306
8307 /* do not allow device reset during IGU info preocessing */
8308                 bnx2x_acquire_hw_lock(sc, HW_LOCK_RESOURCE_RESET);
8309
8310                 val = REG_RD(sc, IGU_REG_BLOCK_CONFIGURATION);
8311
8312                 if (val & IGU_BLOCK_CONFIGURATION_REG_BACKWARD_COMP_EN) {
8313                         int tout = 5000;
8314
8315                         val &= ~(IGU_BLOCK_CONFIGURATION_REG_BACKWARD_COMP_EN);
8316                         REG_WR(sc, IGU_REG_BLOCK_CONFIGURATION, val);
8317                         REG_WR(sc, IGU_REG_RESET_MEMORIES, 0x7f);
8318
8319                         while (tout && REG_RD(sc, IGU_REG_RESET_MEMORIES)) {
8320                                 tout--;
8321                                 DELAY(1000);
8322                         }
8323
8324                         if (REG_RD(sc, IGU_REG_RESET_MEMORIES)) {
8325                                 PMD_DRV_LOG(NOTICE,
8326                                             "FORCING IGU Normal Mode failed!!!");
8327                                 bnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_RESET);
8328                                 return -1;
8329                         }
8330                 }
8331
8332                 if (val & IGU_BLOCK_CONFIGURATION_REG_BACKWARD_COMP_EN) {
8333                         PMD_DRV_LOG(DEBUG, "IGU Backward Compatible Mode");
8334                         sc->devinfo.int_block |= INT_BLOCK_MODE_BW_COMP;
8335                 } else {
8336                         PMD_DRV_LOG(DEBUG, "IGU Normal Mode");
8337                 }
8338
8339                 rc = bnx2x_get_igu_cam_info(sc);
8340
8341                 bnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_RESET);
8342
8343                 if (rc) {
8344                         return rc;
8345                 }
8346         }
8347
8348         /*
8349          * Get base FW non-default (fast path) status block ID. This value is
8350          * used to initialize the fw_sb_id saved on the fp/queue structure to
8351          * determine the id used by the FW.
8352          */
8353         if (CHIP_IS_E1x(sc)) {
8354                 sc->base_fw_ndsb =
8355                     ((SC_PORT(sc) * FP_SB_MAX_E1x) + SC_L_ID(sc));
8356         } else {
8357 /*
8358  * 57712+ - We currently use one FW SB per IGU SB (Rx and Tx of
8359  * the same queue are indicated on the same IGU SB). So we prefer
8360  * FW and IGU SBs to be the same value.
8361  */
8362                 sc->base_fw_ndsb = sc->igu_base_sb;
8363         }
8364
8365         elink_phy_probe(&sc->link_params);
8366
8367         return 0;
8368 }
8369
8370 static void
8371 bnx2x_link_settings_supported(struct bnx2x_softc *sc, uint32_t switch_cfg)
8372 {
8373         uint32_t cfg_size = 0;
8374         uint32_t idx;
8375         uint8_t port = SC_PORT(sc);
8376
8377         /* aggregation of supported attributes of all external phys */
8378         sc->port.supported[0] = 0;
8379         sc->port.supported[1] = 0;
8380
8381         switch (sc->link_params.num_phys) {
8382         case 1:
8383                 sc->port.supported[0] =
8384                     sc->link_params.phy[ELINK_INT_PHY].supported;
8385                 cfg_size = 1;
8386                 break;
8387         case 2:
8388                 sc->port.supported[0] =
8389                     sc->link_params.phy[ELINK_EXT_PHY1].supported;
8390                 cfg_size = 1;
8391                 break;
8392         case 3:
8393                 if (sc->link_params.multi_phy_config &
8394                     PORT_HW_CFG_PHY_SWAPPED_ENABLED) {
8395                         sc->port.supported[1] =
8396                             sc->link_params.phy[ELINK_EXT_PHY1].supported;
8397                         sc->port.supported[0] =
8398                             sc->link_params.phy[ELINK_EXT_PHY2].supported;
8399                 } else {
8400                         sc->port.supported[0] =
8401                             sc->link_params.phy[ELINK_EXT_PHY1].supported;
8402                         sc->port.supported[1] =
8403                             sc->link_params.phy[ELINK_EXT_PHY2].supported;
8404                 }
8405                 cfg_size = 2;
8406                 break;
8407         }
8408
8409         if (!(sc->port.supported[0] || sc->port.supported[1])) {
8410                 PMD_DRV_LOG(ERR,
8411                             "Invalid phy config in NVRAM (PHY1=0x%08x PHY2=0x%08x)",
8412                             SHMEM_RD(sc,
8413                                      dev_info.port_hw_config
8414                                      [port].external_phy_config),
8415                             SHMEM_RD(sc,
8416                                      dev_info.port_hw_config
8417                                      [port].external_phy_config2));
8418                 return;
8419         }
8420
8421         if (CHIP_IS_E3(sc))
8422                 sc->port.phy_addr = REG_RD(sc, MISC_REG_WC0_CTRL_PHY_ADDR);
8423         else {
8424                 switch (switch_cfg) {
8425                 case ELINK_SWITCH_CFG_1G:
8426                         sc->port.phy_addr =
8427                             REG_RD(sc,
8428                                    NIG_REG_SERDES0_CTRL_PHY_ADDR + port * 0x10);
8429                         break;
8430                 case ELINK_SWITCH_CFG_10G:
8431                         sc->port.phy_addr =
8432                             REG_RD(sc,
8433                                    NIG_REG_XGXS0_CTRL_PHY_ADDR + port * 0x18);
8434                         break;
8435                 default:
8436                         PMD_DRV_LOG(ERR,
8437                                     "Invalid switch config in"
8438                                     "link_config=0x%08x",
8439                                     sc->port.link_config[0]);
8440                         return;
8441                 }
8442         }
8443
8444         PMD_DRV_LOG(INFO, "PHY addr 0x%08x", sc->port.phy_addr);
8445
8446         /* mask what we support according to speed_cap_mask per configuration */
8447         for (idx = 0; idx < cfg_size; idx++) {
8448                 if (!(sc->link_params.speed_cap_mask[idx] &
8449                       PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_HALF)) {
8450                         sc->port.supported[idx] &=
8451                             ~ELINK_SUPPORTED_10baseT_Half;
8452                 }
8453
8454                 if (!(sc->link_params.speed_cap_mask[idx] &
8455                       PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL)) {
8456                         sc->port.supported[idx] &=
8457                             ~ELINK_SUPPORTED_10baseT_Full;
8458                 }
8459
8460                 if (!(sc->link_params.speed_cap_mask[idx] &
8461                       PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_HALF)) {
8462                         sc->port.supported[idx] &=
8463                             ~ELINK_SUPPORTED_100baseT_Half;
8464                 }
8465
8466                 if (!(sc->link_params.speed_cap_mask[idx] &
8467                       PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_FULL)) {
8468                         sc->port.supported[idx] &=
8469                             ~ELINK_SUPPORTED_100baseT_Full;
8470                 }
8471
8472                 if (!(sc->link_params.speed_cap_mask[idx] &
8473                       PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)) {
8474                         sc->port.supported[idx] &=
8475                             ~ELINK_SUPPORTED_1000baseT_Full;
8476                 }
8477
8478                 if (!(sc->link_params.speed_cap_mask[idx] &
8479                       PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G)) {
8480                         sc->port.supported[idx] &=
8481                             ~ELINK_SUPPORTED_2500baseX_Full;
8482                 }
8483
8484                 if (!(sc->link_params.speed_cap_mask[idx] &
8485                       PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)) {
8486                         sc->port.supported[idx] &=
8487                             ~ELINK_SUPPORTED_10000baseT_Full;
8488                 }
8489
8490                 if (!(sc->link_params.speed_cap_mask[idx] &
8491                       PORT_HW_CFG_SPEED_CAPABILITY_D0_20G)) {
8492                         sc->port.supported[idx] &=
8493                             ~ELINK_SUPPORTED_20000baseKR2_Full;
8494                 }
8495         }
8496
8497         PMD_DRV_LOG(INFO, "PHY supported 0=0x%08x 1=0x%08x",
8498                     sc->port.supported[0], sc->port.supported[1]);
8499 }
8500
8501 static void bnx2x_link_settings_requested(struct bnx2x_softc *sc)
8502 {
8503         uint32_t link_config;
8504         uint32_t idx;
8505         uint32_t cfg_size = 0;
8506
8507         sc->port.advertising[0] = 0;
8508         sc->port.advertising[1] = 0;
8509
8510         switch (sc->link_params.num_phys) {
8511         case 1:
8512         case 2:
8513                 cfg_size = 1;
8514                 break;
8515         case 3:
8516                 cfg_size = 2;
8517                 break;
8518         }
8519
8520         for (idx = 0; idx < cfg_size; idx++) {
8521                 sc->link_params.req_duplex[idx] = DUPLEX_FULL;
8522                 link_config = sc->port.link_config[idx];
8523
8524                 switch (link_config & PORT_FEATURE_LINK_SPEED_MASK) {
8525                 case PORT_FEATURE_LINK_SPEED_AUTO:
8526                         if (sc->port.supported[idx] & ELINK_SUPPORTED_Autoneg) {
8527                                 sc->link_params.req_line_speed[idx] =
8528                                     ELINK_SPEED_AUTO_NEG;
8529                                 sc->port.advertising[idx] |=
8530                                     sc->port.supported[idx];
8531                                 if (sc->link_params.phy[ELINK_EXT_PHY1].type ==
8532                                     PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X84833)
8533                                         sc->port.advertising[idx] |=
8534                                             (ELINK_SUPPORTED_100baseT_Half |
8535                                              ELINK_SUPPORTED_100baseT_Full);
8536                         } else {
8537                                 /* force 10G, no AN */
8538                                 sc->link_params.req_line_speed[idx] =
8539                                     ELINK_SPEED_10000;
8540                                 sc->port.advertising[idx] |=
8541                                     (ADVERTISED_10000baseT_Full |
8542                                      ADVERTISED_FIBRE);
8543                                 continue;
8544                         }
8545                         break;
8546
8547                 case PORT_FEATURE_LINK_SPEED_10M_FULL:
8548                         if (sc->
8549                             port.supported[idx] & ELINK_SUPPORTED_10baseT_Full)
8550                         {
8551                                 sc->link_params.req_line_speed[idx] =
8552                                     ELINK_SPEED_10;
8553                                 sc->port.advertising[idx] |=
8554                                     (ADVERTISED_10baseT_Full | ADVERTISED_TP);
8555                         } else {
8556                                 PMD_DRV_LOG(ERR,
8557                                             "Invalid NVRAM config link_config=0x%08x "
8558                                             "speed_cap_mask=0x%08x",
8559                                             link_config,
8560                                             sc->
8561                                             link_params.speed_cap_mask[idx]);
8562                                 return;
8563                         }
8564                         break;
8565
8566                 case PORT_FEATURE_LINK_SPEED_10M_HALF:
8567                         if (sc->
8568                             port.supported[idx] & ELINK_SUPPORTED_10baseT_Half)
8569                         {
8570                                 sc->link_params.req_line_speed[idx] =
8571                                     ELINK_SPEED_10;
8572                                 sc->link_params.req_duplex[idx] = DUPLEX_HALF;
8573                                 sc->port.advertising[idx] |=
8574                                     (ADVERTISED_10baseT_Half | ADVERTISED_TP);
8575                         } else {
8576                                 PMD_DRV_LOG(ERR,
8577                                             "Invalid NVRAM config link_config=0x%08x "
8578                                             "speed_cap_mask=0x%08x",
8579                                             link_config,
8580                                             sc->
8581                                             link_params.speed_cap_mask[idx]);
8582                                 return;
8583                         }
8584                         break;
8585
8586                 case PORT_FEATURE_LINK_SPEED_100M_FULL:
8587                         if (sc->
8588                             port.supported[idx] & ELINK_SUPPORTED_100baseT_Full)
8589                         {
8590                                 sc->link_params.req_line_speed[idx] =
8591                                     ELINK_SPEED_100;
8592                                 sc->port.advertising[idx] |=
8593                                     (ADVERTISED_100baseT_Full | ADVERTISED_TP);
8594                         } else {
8595                                 PMD_DRV_LOG(ERR,
8596                                             "Invalid NVRAM config link_config=0x%08x "
8597                                             "speed_cap_mask=0x%08x",
8598                                             link_config,
8599                                             sc->
8600                                             link_params.speed_cap_mask[idx]);
8601                                 return;
8602                         }
8603                         break;
8604
8605                 case PORT_FEATURE_LINK_SPEED_100M_HALF:
8606                         if (sc->
8607                             port.supported[idx] & ELINK_SUPPORTED_100baseT_Half)
8608                         {
8609                                 sc->link_params.req_line_speed[idx] =
8610                                     ELINK_SPEED_100;
8611                                 sc->link_params.req_duplex[idx] = DUPLEX_HALF;
8612                                 sc->port.advertising[idx] |=
8613                                     (ADVERTISED_100baseT_Half | ADVERTISED_TP);
8614                         } else {
8615                                 PMD_DRV_LOG(ERR,
8616                                             "Invalid NVRAM config link_config=0x%08x "
8617                                             "speed_cap_mask=0x%08x",
8618                                             link_config,
8619                                             sc->
8620                                             link_params.speed_cap_mask[idx]);
8621                                 return;
8622                         }
8623                         break;
8624
8625                 case PORT_FEATURE_LINK_SPEED_1G:
8626                         if (sc->port.supported[idx] &
8627                             ELINK_SUPPORTED_1000baseT_Full) {
8628                                 sc->link_params.req_line_speed[idx] =
8629                                     ELINK_SPEED_1000;
8630                                 sc->port.advertising[idx] |=
8631                                     (ADVERTISED_1000baseT_Full | ADVERTISED_TP);
8632                         } else {
8633                                 PMD_DRV_LOG(ERR,
8634                                             "Invalid NVRAM config link_config=0x%08x "
8635                                             "speed_cap_mask=0x%08x",
8636                                             link_config,
8637                                             sc->
8638                                             link_params.speed_cap_mask[idx]);
8639                                 return;
8640                         }
8641                         break;
8642
8643                 case PORT_FEATURE_LINK_SPEED_2_5G:
8644                         if (sc->port.supported[idx] &
8645                             ELINK_SUPPORTED_2500baseX_Full) {
8646                                 sc->link_params.req_line_speed[idx] =
8647                                     ELINK_SPEED_2500;
8648                                 sc->port.advertising[idx] |=
8649                                     (ADVERTISED_2500baseX_Full | ADVERTISED_TP);
8650                         } else {
8651                                 PMD_DRV_LOG(ERR,
8652                                             "Invalid NVRAM config link_config=0x%08x "
8653                                             "speed_cap_mask=0x%08x",
8654                                             link_config,
8655                                             sc->
8656                                             link_params.speed_cap_mask[idx]);
8657                                 return;
8658                         }
8659                         break;
8660
8661                 case PORT_FEATURE_LINK_SPEED_10G_CX4:
8662                         if (sc->port.supported[idx] &
8663                             ELINK_SUPPORTED_10000baseT_Full) {
8664                                 sc->link_params.req_line_speed[idx] =
8665                                     ELINK_SPEED_10000;
8666                                 sc->port.advertising[idx] |=
8667                                     (ADVERTISED_10000baseT_Full |
8668                                      ADVERTISED_FIBRE);
8669                         } else {
8670                                 PMD_DRV_LOG(ERR,
8671                                             "Invalid NVRAM config link_config=0x%08x "
8672                                             "speed_cap_mask=0x%08x",
8673                                             link_config,
8674                                             sc->
8675                                             link_params.speed_cap_mask[idx]);
8676                                 return;
8677                         }
8678                         break;
8679
8680                 case PORT_FEATURE_LINK_SPEED_20G:
8681                         sc->link_params.req_line_speed[idx] = ELINK_SPEED_20000;
8682                         break;
8683
8684                 default:
8685                         PMD_DRV_LOG(ERR,
8686                                     "Invalid NVRAM config link_config=0x%08x "
8687                                     "speed_cap_mask=0x%08x", link_config,
8688                                     sc->link_params.speed_cap_mask[idx]);
8689                         sc->link_params.req_line_speed[idx] =
8690                             ELINK_SPEED_AUTO_NEG;
8691                         sc->port.advertising[idx] = sc->port.supported[idx];
8692                         break;
8693                 }
8694
8695                 sc->link_params.req_flow_ctrl[idx] =
8696                     (link_config & PORT_FEATURE_FLOW_CONTROL_MASK);
8697
8698                 if (sc->link_params.req_flow_ctrl[idx] == ELINK_FLOW_CTRL_AUTO) {
8699                         if (!
8700                             (sc->
8701                              port.supported[idx] & ELINK_SUPPORTED_Autoneg)) {
8702                                 sc->link_params.req_flow_ctrl[idx] =
8703                                     ELINK_FLOW_CTRL_NONE;
8704                         } else {
8705                                 bnx2x_set_requested_fc(sc);
8706                         }
8707                 }
8708         }
8709 }
8710
8711 static void bnx2x_get_phy_info(struct bnx2x_softc *sc)
8712 {
8713         uint8_t port = SC_PORT(sc);
8714         uint32_t eee_mode;
8715
8716         PMD_INIT_FUNC_TRACE();
8717
8718         /* shmem data already read in bnx2x_get_shmem_info() */
8719
8720         bnx2x_link_settings_supported(sc, sc->link_params.switch_cfg);
8721         bnx2x_link_settings_requested(sc);
8722
8723         /* configure link feature according to nvram value */
8724         eee_mode =
8725             (((SHMEM_RD(sc, dev_info.port_feature_config[port].eee_power_mode))
8726               & PORT_FEAT_CFG_EEE_POWER_MODE_MASK) >>
8727              PORT_FEAT_CFG_EEE_POWER_MODE_SHIFT);
8728         if (eee_mode != PORT_FEAT_CFG_EEE_POWER_MODE_DISABLED) {
8729                 sc->link_params.eee_mode = (ELINK_EEE_MODE_ADV_LPI |
8730                                             ELINK_EEE_MODE_ENABLE_LPI |
8731                                             ELINK_EEE_MODE_OUTPUT_TIME);
8732         } else {
8733                 sc->link_params.eee_mode = 0;
8734         }
8735
8736         /* get the media type */
8737         bnx2x_media_detect(sc);
8738 }
8739
8740 static void bnx2x_set_modes_bitmap(struct bnx2x_softc *sc)
8741 {
8742         uint32_t flags = MODE_ASIC | MODE_PORT2;
8743
8744         if (CHIP_IS_E2(sc)) {
8745                 flags |= MODE_E2;
8746         } else if (CHIP_IS_E3(sc)) {
8747                 flags |= MODE_E3;
8748                 if (CHIP_REV(sc) == CHIP_REV_Ax) {
8749                         flags |= MODE_E3_A0;
8750                 } else {        /*if (CHIP_REV(sc) == CHIP_REV_Bx) */
8751
8752                         flags |= MODE_E3_B0 | MODE_COS3;
8753                 }
8754         }
8755
8756         if (IS_MF(sc)) {
8757                 flags |= MODE_MF;
8758                 switch (sc->devinfo.mf_info.mf_mode) {
8759                 case MULTI_FUNCTION_SD:
8760                         flags |= MODE_MF_SD;
8761                         break;
8762                 case MULTI_FUNCTION_SI:
8763                         flags |= MODE_MF_SI;
8764                         break;
8765                 case MULTI_FUNCTION_AFEX:
8766                         flags |= MODE_MF_AFEX;
8767                         break;
8768                 }
8769         } else {
8770                 flags |= MODE_SF;
8771         }
8772
8773 #if defined(__LITTLE_ENDIAN)
8774         flags |= MODE_LITTLE_ENDIAN;
8775 #else /* __BIG_ENDIAN */
8776         flags |= MODE_BIG_ENDIAN;
8777 #endif
8778
8779         INIT_MODE_FLAGS(sc) = flags;
8780 }
8781
8782 int bnx2x_alloc_hsi_mem(struct bnx2x_softc *sc)
8783 {
8784         struct bnx2x_fastpath *fp;
8785         char buf[32];
8786         uint32_t i;
8787
8788         if (IS_PF(sc)) {
8789 /************************/
8790 /* DEFAULT STATUS BLOCK */
8791 /************************/
8792
8793                 if (bnx2x_dma_alloc(sc, sizeof(struct host_sp_status_block),
8794                                   &sc->def_sb_dma, "def_sb",
8795                                   RTE_CACHE_LINE_SIZE) != 0) {
8796                         return -1;
8797                 }
8798
8799                 sc->def_sb =
8800                     (struct host_sp_status_block *)sc->def_sb_dma.vaddr;
8801 /***************/
8802 /* EVENT QUEUE */
8803 /***************/
8804
8805                 if (bnx2x_dma_alloc(sc, BNX2X_PAGE_SIZE,
8806                                   &sc->eq_dma, "ev_queue",
8807                                   RTE_CACHE_LINE_SIZE) != 0) {
8808                         sc->def_sb = NULL;
8809                         return -1;
8810                 }
8811
8812                 sc->eq = (union event_ring_elem *)sc->eq_dma.vaddr;
8813
8814 /*************/
8815 /* SLOW PATH */
8816 /*************/
8817
8818                 if (bnx2x_dma_alloc(sc, sizeof(struct bnx2x_slowpath),
8819                                   &sc->sp_dma, "sp",
8820                                   RTE_CACHE_LINE_SIZE) != 0) {
8821                         sc->eq = NULL;
8822                         sc->def_sb = NULL;
8823                         return -1;
8824                 }
8825
8826                 sc->sp = (struct bnx2x_slowpath *)sc->sp_dma.vaddr;
8827
8828 /*******************/
8829 /* SLOW PATH QUEUE */
8830 /*******************/
8831
8832                 if (bnx2x_dma_alloc(sc, BNX2X_PAGE_SIZE,
8833                                   &sc->spq_dma, "sp_queue",
8834                                   RTE_CACHE_LINE_SIZE) != 0) {
8835                         sc->sp = NULL;
8836                         sc->eq = NULL;
8837                         sc->def_sb = NULL;
8838                         return -1;
8839                 }
8840
8841                 sc->spq = (struct eth_spe *)sc->spq_dma.vaddr;
8842
8843 /***************************/
8844 /* FW DECOMPRESSION BUFFER */
8845 /***************************/
8846
8847                 if (bnx2x_dma_alloc(sc, FW_BUF_SIZE, &sc->gz_buf_dma,
8848                                   "fw_buf", RTE_CACHE_LINE_SIZE) != 0) {
8849                         sc->spq = NULL;
8850                         sc->sp = NULL;
8851                         sc->eq = NULL;
8852                         sc->def_sb = NULL;
8853                         return -1;
8854                 }
8855
8856                 sc->gz_buf = (void *)sc->gz_buf_dma.vaddr;
8857         }
8858
8859         /*************/
8860         /* FASTPATHS */
8861         /*************/
8862
8863         /* allocate DMA memory for each fastpath structure */
8864         for (i = 0; i < sc->num_queues; i++) {
8865                 fp = &sc->fp[i];
8866                 fp->sc = sc;
8867                 fp->index = i;
8868
8869 /*******************/
8870 /* FP STATUS BLOCK */
8871 /*******************/
8872
8873                 snprintf(buf, sizeof(buf), "fp_%d_sb", i);
8874                 if (bnx2x_dma_alloc(sc, sizeof(union bnx2x_host_hc_status_block),
8875                                   &fp->sb_dma, buf, RTE_CACHE_LINE_SIZE) != 0) {
8876                         PMD_DRV_LOG(NOTICE, "Failed to alloc %s", buf);
8877                         return -1;
8878                 } else {
8879                         if (CHIP_IS_E2E3(sc)) {
8880                                 fp->status_block.e2_sb =
8881                                     (struct host_hc_status_block_e2 *)
8882                                     fp->sb_dma.vaddr;
8883                         } else {
8884                                 fp->status_block.e1x_sb =
8885                                     (struct host_hc_status_block_e1x *)
8886                                     fp->sb_dma.vaddr;
8887                         }
8888                 }
8889         }
8890
8891         return 0;
8892 }
8893
8894 void bnx2x_free_hsi_mem(struct bnx2x_softc *sc)
8895 {
8896         struct bnx2x_fastpath *fp;
8897         int i;
8898
8899         for (i = 0; i < sc->num_queues; i++) {
8900                 fp = &sc->fp[i];
8901
8902 /*******************/
8903 /* FP STATUS BLOCK */
8904 /*******************/
8905
8906                 memset(&fp->status_block, 0, sizeof(fp->status_block));
8907         }
8908
8909         /***************************/
8910         /* FW DECOMPRESSION BUFFER */
8911         /***************************/
8912
8913         sc->gz_buf = NULL;
8914
8915         /*******************/
8916         /* SLOW PATH QUEUE */
8917         /*******************/
8918
8919         sc->spq = NULL;
8920
8921         /*************/
8922         /* SLOW PATH */
8923         /*************/
8924
8925         sc->sp = NULL;
8926
8927         /***************/
8928         /* EVENT QUEUE */
8929         /***************/
8930
8931         sc->eq = NULL;
8932
8933         /************************/
8934         /* DEFAULT STATUS BLOCK */
8935         /************************/
8936
8937         sc->def_sb = NULL;
8938
8939 }
8940
8941 /*
8942 * Previous driver DMAE transaction may have occurred when pre-boot stage
8943 * ended and boot began. This would invalidate the addresses of the
8944 * transaction, resulting in was-error bit set in the PCI causing all
8945 * hw-to-host PCIe transactions to timeout. If this happened we want to clear
8946 * the interrupt which detected this from the pglueb and the was-done bit
8947 */
8948 static void bnx2x_prev_interrupted_dmae(struct bnx2x_softc *sc)
8949 {
8950         uint32_t val;
8951
8952         if (!CHIP_IS_E1x(sc)) {
8953                 val = REG_RD(sc, PGLUE_B_REG_PGLUE_B_INT_STS);
8954                 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_WAS_ERROR_ATTN) {
8955                         REG_WR(sc, PGLUE_B_REG_WAS_ERROR_PF_7_0_CLR,
8956                                1 << SC_FUNC(sc));
8957                 }
8958         }
8959 }
8960
8961 static int bnx2x_prev_mcp_done(struct bnx2x_softc *sc)
8962 {
8963         uint32_t rc = bnx2x_fw_command(sc, DRV_MSG_CODE_UNLOAD_DONE,
8964                                      DRV_MSG_CODE_UNLOAD_SKIP_LINK_RESET);
8965         if (!rc) {
8966                 PMD_DRV_LOG(NOTICE, "MCP response failure, aborting");
8967                 return -1;
8968         }
8969
8970         return 0;
8971 }
8972
8973 static struct bnx2x_prev_list_node *bnx2x_prev_path_get_entry(struct bnx2x_softc *sc)
8974 {
8975         struct bnx2x_prev_list_node *tmp;
8976
8977         LIST_FOREACH(tmp, &bnx2x_prev_list, node) {
8978                 if ((sc->pcie_bus == tmp->bus) &&
8979                     (sc->pcie_device == tmp->slot) &&
8980                     (SC_PATH(sc) == tmp->path)) {
8981                         return tmp;
8982                 }
8983         }
8984
8985         return NULL;
8986 }
8987
8988 static uint8_t bnx2x_prev_is_path_marked(struct bnx2x_softc *sc)
8989 {
8990         struct bnx2x_prev_list_node *tmp;
8991         int rc = FALSE;
8992
8993         rte_spinlock_lock(&bnx2x_prev_mtx);
8994
8995         tmp = bnx2x_prev_path_get_entry(sc);
8996         if (tmp) {
8997                 if (tmp->aer) {
8998                         PMD_DRV_LOG(DEBUG,
8999                                     "Path %d/%d/%d was marked by AER",
9000                                     sc->pcie_bus, sc->pcie_device, SC_PATH(sc));
9001                 } else {
9002                         rc = TRUE;
9003                         PMD_DRV_LOG(DEBUG,
9004                                     "Path %d/%d/%d was already cleaned from previous drivers",
9005                                     sc->pcie_bus, sc->pcie_device, SC_PATH(sc));
9006                 }
9007         }
9008
9009         rte_spinlock_unlock(&bnx2x_prev_mtx);
9010
9011         return rc;
9012 }
9013
9014 static int bnx2x_prev_mark_path(struct bnx2x_softc *sc, uint8_t after_undi)
9015 {
9016         struct bnx2x_prev_list_node *tmp;
9017
9018         rte_spinlock_lock(&bnx2x_prev_mtx);
9019
9020         /* Check whether the entry for this path already exists */
9021         tmp = bnx2x_prev_path_get_entry(sc);
9022         if (tmp) {
9023                 if (!tmp->aer) {
9024                         PMD_DRV_LOG(DEBUG,
9025                                     "Re-marking AER in path %d/%d/%d",
9026                                     sc->pcie_bus, sc->pcie_device, SC_PATH(sc));
9027                 } else {
9028                         PMD_DRV_LOG(DEBUG,
9029                                     "Removing AER indication from path %d/%d/%d",
9030                                     sc->pcie_bus, sc->pcie_device, SC_PATH(sc));
9031                         tmp->aer = 0;
9032                 }
9033
9034                 rte_spinlock_unlock(&bnx2x_prev_mtx);
9035                 return 0;
9036         }
9037
9038         rte_spinlock_unlock(&bnx2x_prev_mtx);
9039
9040         /* Create an entry for this path and add it */
9041         tmp = rte_malloc("", sizeof(struct bnx2x_prev_list_node),
9042                          RTE_CACHE_LINE_SIZE);
9043         if (!tmp) {
9044                 PMD_DRV_LOG(NOTICE, "Failed to allocate 'bnx2x_prev_list_node'");
9045                 return -1;
9046         }
9047
9048         tmp->bus = sc->pcie_bus;
9049         tmp->slot = sc->pcie_device;
9050         tmp->path = SC_PATH(sc);
9051         tmp->aer = 0;
9052         tmp->undi = after_undi ? (1 << SC_PORT(sc)) : 0;
9053
9054         rte_spinlock_lock(&bnx2x_prev_mtx);
9055
9056         LIST_INSERT_HEAD(&bnx2x_prev_list, tmp, node);
9057
9058         rte_spinlock_unlock(&bnx2x_prev_mtx);
9059
9060         return 0;
9061 }
9062
9063 static int bnx2x_do_flr(struct bnx2x_softc *sc)
9064 {
9065         int i;
9066
9067         /* only E2 and onwards support FLR */
9068         if (CHIP_IS_E1x(sc)) {
9069                 PMD_DRV_LOG(WARNING, "FLR not supported in E1H");
9070                 return -1;
9071         }
9072
9073         /* only bootcode REQ_BC_VER_4_INITIATE_FLR and onwards support flr */
9074         if (sc->devinfo.bc_ver < REQ_BC_VER_4_INITIATE_FLR) {
9075                 PMD_DRV_LOG(WARNING,
9076                             "FLR not supported by BC_VER: 0x%08x",
9077                             sc->devinfo.bc_ver);
9078                 return -1;
9079         }
9080
9081         /* Wait for Transaction Pending bit clean */
9082         for (i = 0; i < 4; i++) {
9083                 if (i) {
9084                         DELAY(((1 << (i - 1)) * 100) * 1000);
9085                 }
9086
9087                 if (!bnx2x_is_pcie_pending(sc)) {
9088                         goto clear;
9089                 }
9090         }
9091
9092         PMD_DRV_LOG(NOTICE, "PCIE transaction is not cleared, "
9093                     "proceeding with reset anyway");
9094
9095 clear:
9096         bnx2x_fw_command(sc, DRV_MSG_CODE_INITIATE_FLR, 0);
9097
9098         return 0;
9099 }
9100
9101 struct bnx2x_mac_vals {
9102         uint32_t xmac_addr;
9103         uint32_t xmac_val;
9104         uint32_t emac_addr;
9105         uint32_t emac_val;
9106         uint32_t umac_addr;
9107         uint32_t umac_val;
9108         uint32_t bmac_addr;
9109         uint32_t bmac_val[2];
9110 };
9111
9112 static void
9113 bnx2x_prev_unload_close_mac(struct bnx2x_softc *sc, struct bnx2x_mac_vals *vals)
9114 {
9115         uint32_t val, base_addr, offset, mask, reset_reg;
9116         uint8_t mac_stopped = FALSE;
9117         uint8_t port = SC_PORT(sc);
9118         uint32_t wb_data[2];
9119
9120         /* reset addresses as they also mark which values were changed */
9121         vals->bmac_addr = 0;
9122         vals->umac_addr = 0;
9123         vals->xmac_addr = 0;
9124         vals->emac_addr = 0;
9125
9126         reset_reg = REG_RD(sc, MISC_REG_RESET_REG_2);
9127
9128         if (!CHIP_IS_E3(sc)) {
9129                 val = REG_RD(sc, NIG_REG_BMAC0_REGS_OUT_EN + port * 4);
9130                 mask = MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port;
9131                 if ((mask & reset_reg) && val) {
9132                         base_addr = SC_PORT(sc) ? NIG_REG_INGRESS_BMAC1_MEM
9133                             : NIG_REG_INGRESS_BMAC0_MEM;
9134                         offset = CHIP_IS_E2(sc) ? BIGMAC2_REGISTER_BMAC_CONTROL
9135                             : BIGMAC_REGISTER_BMAC_CONTROL;
9136
9137                         /*
9138                          * use rd/wr since we cannot use dmae. This is safe
9139                          * since MCP won't access the bus due to the request
9140                          * to unload, and no function on the path can be
9141                          * loaded at this time.
9142                          */
9143                         wb_data[0] = REG_RD(sc, base_addr + offset);
9144                         wb_data[1] = REG_RD(sc, base_addr + offset + 0x4);
9145                         vals->bmac_addr = base_addr + offset;
9146                         vals->bmac_val[0] = wb_data[0];
9147                         vals->bmac_val[1] = wb_data[1];
9148                         wb_data[0] &= ~ELINK_BMAC_CONTROL_RX_ENABLE;
9149                         REG_WR(sc, vals->bmac_addr, wb_data[0]);
9150                         REG_WR(sc, vals->bmac_addr + 0x4, wb_data[1]);
9151                 }
9152
9153                 vals->emac_addr = NIG_REG_NIG_EMAC0_EN + SC_PORT(sc) * 4;
9154                 vals->emac_val = REG_RD(sc, vals->emac_addr);
9155                 REG_WR(sc, vals->emac_addr, 0);
9156                 mac_stopped = TRUE;
9157         } else {
9158                 if (reset_reg & MISC_REGISTERS_RESET_REG_2_XMAC) {
9159                         base_addr = SC_PORT(sc) ? GRCBASE_XMAC1 : GRCBASE_XMAC0;
9160                         val = REG_RD(sc, base_addr + XMAC_REG_PFC_CTRL_HI);
9161                         REG_WR(sc, base_addr + XMAC_REG_PFC_CTRL_HI,
9162                                val & ~(1 << 1));
9163                         REG_WR(sc, base_addr + XMAC_REG_PFC_CTRL_HI,
9164                                val | (1 << 1));
9165                         vals->xmac_addr = base_addr + XMAC_REG_CTRL;
9166                         vals->xmac_val = REG_RD(sc, vals->xmac_addr);
9167                         REG_WR(sc, vals->xmac_addr, 0);
9168                         mac_stopped = TRUE;
9169                 }
9170
9171                 mask = MISC_REGISTERS_RESET_REG_2_UMAC0 << port;
9172                 if (mask & reset_reg) {
9173                         base_addr = SC_PORT(sc) ? GRCBASE_UMAC1 : GRCBASE_UMAC0;
9174                         vals->umac_addr = base_addr + UMAC_REG_COMMAND_CONFIG;
9175                         vals->umac_val = REG_RD(sc, vals->umac_addr);
9176                         REG_WR(sc, vals->umac_addr, 0);
9177                         mac_stopped = TRUE;
9178                 }
9179         }
9180
9181         if (mac_stopped) {
9182                 DELAY(20000);
9183         }
9184 }
9185
9186 #define BNX2X_PREV_UNDI_PROD_ADDR(p)  (BAR_TSTRORM_INTMEM + 0x1508 + ((p) << 4))
9187 #define BNX2X_PREV_UNDI_RCQ(val)      ((val) & 0xffff)
9188 #define BNX2X_PREV_UNDI_BD(val)       ((val) >> 16 & 0xffff)
9189 #define BNX2X_PREV_UNDI_PROD(rcq, bd) ((bd) << 16 | (rcq))
9190
9191 static void
9192 bnx2x_prev_unload_undi_inc(struct bnx2x_softc *sc, uint8_t port, uint8_t inc)
9193 {
9194         uint16_t rcq, bd;
9195         uint32_t tmp_reg = REG_RD(sc, BNX2X_PREV_UNDI_PROD_ADDR(port));
9196
9197         rcq = BNX2X_PREV_UNDI_RCQ(tmp_reg) + inc;
9198         bd = BNX2X_PREV_UNDI_BD(tmp_reg) + inc;
9199
9200         tmp_reg = BNX2X_PREV_UNDI_PROD(rcq, bd);
9201         REG_WR(sc, BNX2X_PREV_UNDI_PROD_ADDR(port), tmp_reg);
9202 }
9203
9204 static int bnx2x_prev_unload_common(struct bnx2x_softc *sc)
9205 {
9206         uint32_t reset_reg, tmp_reg = 0, rc;
9207         uint8_t prev_undi = FALSE;
9208         struct bnx2x_mac_vals mac_vals;
9209         uint32_t timer_count = 1000;
9210         uint32_t prev_brb;
9211
9212         /*
9213          * It is possible a previous function received 'common' answer,
9214          * but hasn't loaded yet, therefore creating a scenario of
9215          * multiple functions receiving 'common' on the same path.
9216          */
9217         memset(&mac_vals, 0, sizeof(mac_vals));
9218
9219         if (bnx2x_prev_is_path_marked(sc)) {
9220                 return bnx2x_prev_mcp_done(sc);
9221         }
9222
9223         reset_reg = REG_RD(sc, MISC_REG_RESET_REG_1);
9224
9225         /* Reset should be performed after BRB is emptied */
9226         if (reset_reg & MISC_REGISTERS_RESET_REG_1_RST_BRB1) {
9227                 /* Close the MAC Rx to prevent BRB from filling up */
9228                 bnx2x_prev_unload_close_mac(sc, &mac_vals);
9229
9230                 /* close LLH filters towards the BRB */
9231                 elink_set_rx_filter(&sc->link_params, 0);
9232
9233                 /*
9234                  * Check if the UNDI driver was previously loaded.
9235                  * UNDI driver initializes CID offset for normal bell to 0x7
9236                  */
9237                 if (reset_reg & MISC_REGISTERS_RESET_REG_1_RST_DORQ) {
9238                         tmp_reg = REG_RD(sc, DORQ_REG_NORM_CID_OFST);
9239                         if (tmp_reg == 0x7) {
9240                                 PMD_DRV_LOG(DEBUG, "UNDI previously loaded");
9241                                 prev_undi = TRUE;
9242                                 /* clear the UNDI indication */
9243                                 REG_WR(sc, DORQ_REG_NORM_CID_OFST, 0);
9244                                 /* clear possible idle check errors */
9245                                 REG_RD(sc, NIG_REG_NIG_INT_STS_CLR_0);
9246                         }
9247                 }
9248
9249                 /* wait until BRB is empty */
9250                 tmp_reg = REG_RD(sc, BRB1_REG_NUM_OF_FULL_BLOCKS);
9251                 while (timer_count) {
9252                         prev_brb = tmp_reg;
9253
9254                         tmp_reg = REG_RD(sc, BRB1_REG_NUM_OF_FULL_BLOCKS);
9255                         if (!tmp_reg) {
9256                                 break;
9257                         }
9258
9259                         PMD_DRV_LOG(DEBUG, "BRB still has 0x%08x", tmp_reg);
9260
9261                         /* reset timer as long as BRB actually gets emptied */
9262                         if (prev_brb > tmp_reg) {
9263                                 timer_count = 1000;
9264                         } else {
9265                                 timer_count--;
9266                         }
9267
9268                         /* If UNDI resides in memory, manually increment it */
9269                         if (prev_undi) {
9270                                 bnx2x_prev_unload_undi_inc(sc, SC_PORT(sc), 1);
9271                         }
9272
9273                         DELAY(10);
9274                 }
9275
9276                 if (!timer_count) {
9277                         PMD_DRV_LOG(NOTICE, "Failed to empty BRB");
9278                 }
9279         }
9280
9281         /* No packets are in the pipeline, path is ready for reset */
9282         bnx2x_reset_common(sc);
9283
9284         if (mac_vals.xmac_addr) {
9285                 REG_WR(sc, mac_vals.xmac_addr, mac_vals.xmac_val);
9286         }
9287         if (mac_vals.umac_addr) {
9288                 REG_WR(sc, mac_vals.umac_addr, mac_vals.umac_val);
9289         }
9290         if (mac_vals.emac_addr) {
9291                 REG_WR(sc, mac_vals.emac_addr, mac_vals.emac_val);
9292         }
9293         if (mac_vals.bmac_addr) {
9294                 REG_WR(sc, mac_vals.bmac_addr, mac_vals.bmac_val[0]);
9295                 REG_WR(sc, mac_vals.bmac_addr + 4, mac_vals.bmac_val[1]);
9296         }
9297
9298         rc = bnx2x_prev_mark_path(sc, prev_undi);
9299         if (rc) {
9300                 bnx2x_prev_mcp_done(sc);
9301                 return rc;
9302         }
9303
9304         return bnx2x_prev_mcp_done(sc);
9305 }
9306
9307 static int bnx2x_prev_unload_uncommon(struct bnx2x_softc *sc)
9308 {
9309         int rc;
9310
9311         /* Test if previous unload process was already finished for this path */
9312         if (bnx2x_prev_is_path_marked(sc)) {
9313                 return bnx2x_prev_mcp_done(sc);
9314         }
9315
9316         /*
9317          * If function has FLR capabilities, and existing FW version matches
9318          * the one required, then FLR will be sufficient to clean any residue
9319          * left by previous driver
9320          */
9321         rc = bnx2x_nic_load_analyze_req(sc, FW_MSG_CODE_DRV_LOAD_FUNCTION);
9322         if (!rc) {
9323                 /* fw version is good */
9324                 rc = bnx2x_do_flr(sc);
9325         }
9326
9327         if (!rc) {
9328                 /* FLR was performed */
9329                 return 0;
9330         }
9331
9332         PMD_DRV_LOG(INFO, "Could not FLR");
9333
9334         /* Close the MCP request, return failure */
9335         rc = bnx2x_prev_mcp_done(sc);
9336         if (!rc) {
9337                 rc = BNX2X_PREV_WAIT_NEEDED;
9338         }
9339
9340         return rc;
9341 }
9342
9343 static int bnx2x_prev_unload(struct bnx2x_softc *sc)
9344 {
9345         int time_counter = 10;
9346         uint32_t fw, hw_lock_reg, hw_lock_val;
9347         uint32_t rc = 0;
9348
9349         /*
9350          * Clear HW from errors which may have resulted from an interrupted
9351          * DMAE transaction.
9352          */
9353         bnx2x_prev_interrupted_dmae(sc);
9354
9355         /* Release previously held locks */
9356         if (SC_FUNC(sc) <= 5)
9357                 hw_lock_reg = (MISC_REG_DRIVER_CONTROL_1 + SC_FUNC(sc) * 8);
9358         else
9359                 hw_lock_reg =
9360                     (MISC_REG_DRIVER_CONTROL_7 + (SC_FUNC(sc) - 6) * 8);
9361
9362         hw_lock_val = (REG_RD(sc, hw_lock_reg));
9363         if (hw_lock_val) {
9364                 if (hw_lock_val & HW_LOCK_RESOURCE_NVRAM) {
9365                         REG_WR(sc, MCP_REG_MCPR_NVM_SW_ARB,
9366                                (MCPR_NVM_SW_ARB_ARB_REQ_CLR1 << SC_PORT(sc)));
9367                 }
9368                 REG_WR(sc, hw_lock_reg, 0xffffffff);
9369         }
9370
9371         if (MCPR_ACCESS_LOCK_LOCK & REG_RD(sc, MCP_REG_MCPR_ACCESS_LOCK)) {
9372                 REG_WR(sc, MCP_REG_MCPR_ACCESS_LOCK, 0);
9373         }
9374
9375         do {
9376                 /* Lock MCP using an unload request */
9377                 fw = bnx2x_fw_command(sc, DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS, 0);
9378                 if (!fw) {
9379                         PMD_DRV_LOG(NOTICE, "MCP response failure, aborting");
9380                         rc = -1;
9381                         break;
9382                 }
9383
9384                 if (fw == FW_MSG_CODE_DRV_UNLOAD_COMMON) {
9385                         rc = bnx2x_prev_unload_common(sc);
9386                         break;
9387                 }
9388
9389                 /* non-common reply from MCP might require looping */
9390                 rc = bnx2x_prev_unload_uncommon(sc);
9391                 if (rc != BNX2X_PREV_WAIT_NEEDED) {
9392                         break;
9393                 }
9394
9395                 DELAY(20000);
9396         } while (--time_counter);
9397
9398         if (!time_counter || rc) {
9399                 PMD_DRV_LOG(NOTICE, "Failed to unload previous driver!");
9400                 rc = -1;
9401         }
9402
9403         return rc;
9404 }
9405
9406 static void
9407 bnx2x_dcbx_set_state(struct bnx2x_softc *sc, uint8_t dcb_on, uint32_t dcbx_enabled)
9408 {
9409         if (!CHIP_IS_E1x(sc)) {
9410                 sc->dcb_state = dcb_on;
9411                 sc->dcbx_enabled = dcbx_enabled;
9412         } else {
9413                 sc->dcb_state = FALSE;
9414                 sc->dcbx_enabled = BNX2X_DCBX_ENABLED_INVALID;
9415         }
9416         PMD_DRV_LOG(DEBUG,
9417                     "DCB state [%s:%s]",
9418                     dcb_on ? "ON" : "OFF",
9419                     (dcbx_enabled == BNX2X_DCBX_ENABLED_OFF) ? "user-mode" :
9420                     (dcbx_enabled ==
9421                      BNX2X_DCBX_ENABLED_ON_NEG_OFF) ? "on-chip static"
9422                     : (dcbx_enabled ==
9423                        BNX2X_DCBX_ENABLED_ON_NEG_ON) ?
9424                     "on-chip with negotiation" : "invalid");
9425 }
9426
9427 static int bnx2x_set_qm_cid_count(struct bnx2x_softc *sc)
9428 {
9429         int cid_count = BNX2X_L2_MAX_CID(sc);
9430
9431         if (CNIC_SUPPORT(sc)) {
9432                 cid_count += CNIC_CID_MAX;
9433         }
9434
9435         return roundup(cid_count, QM_CID_ROUND);
9436 }
9437
9438 static void bnx2x_init_multi_cos(struct bnx2x_softc *sc)
9439 {
9440         int pri, cos;
9441
9442         uint32_t pri_map = 0;
9443
9444         for (pri = 0; pri < BNX2X_MAX_PRIORITY; pri++) {
9445                 cos = ((pri_map & (0xf << (pri * 4))) >> (pri * 4));
9446                 if (cos < sc->max_cos) {
9447                         sc->prio_to_cos[pri] = cos;
9448                 } else {
9449                         PMD_DRV_LOG(WARNING,
9450                                     "Invalid COS %d for priority %d "
9451                                     "(max COS is %d), setting to 0", cos, pri,
9452                                     (sc->max_cos - 1));
9453                         sc->prio_to_cos[pri] = 0;
9454                 }
9455         }
9456 }
9457
9458 static int bnx2x_pci_get_caps(struct bnx2x_softc *sc)
9459 {
9460         struct {
9461                 uint8_t id;
9462                 uint8_t next;
9463         } pci_cap;
9464         uint16_t status;
9465         struct bnx2x_pci_cap *cap;
9466
9467         cap = sc->pci_caps = rte_zmalloc("caps", sizeof(struct bnx2x_pci_cap),
9468                                          RTE_CACHE_LINE_SIZE);
9469         if (!cap) {
9470                 PMD_DRV_LOG(NOTICE, "Failed to allocate memory");
9471                 return -ENOMEM;
9472         }
9473
9474 #ifndef __FreeBSD__
9475         pci_read(sc, PCI_STATUS, &status, 2);
9476         if (!(status & PCI_STATUS_CAP_LIST)) {
9477 #else
9478         pci_read(sc, PCIR_STATUS, &status, 2);
9479         if (!(status & PCIM_STATUS_CAPPRESENT)) {
9480 #endif
9481                 PMD_DRV_LOG(NOTICE, "PCIe capability reading failed");
9482                 return -1;
9483         }
9484
9485 #ifndef __FreeBSD__
9486         pci_read(sc, PCI_CAPABILITY_LIST, &pci_cap.next, 1);
9487 #else
9488         pci_read(sc, PCIR_CAP_PTR, &pci_cap.next, 1);
9489 #endif
9490         while (pci_cap.next) {
9491                 cap->addr = pci_cap.next & ~3;
9492                 pci_read(sc, pci_cap.next & ~3, &pci_cap, 2);
9493                 if (pci_cap.id == 0xff)
9494                         break;
9495                 cap->id = pci_cap.id;
9496                 cap->type = BNX2X_PCI_CAP;
9497                 cap->next = rte_zmalloc("pci_cap",
9498                                         sizeof(struct bnx2x_pci_cap),
9499                                         RTE_CACHE_LINE_SIZE);
9500                 if (!cap->next) {
9501                         PMD_DRV_LOG(NOTICE, "Failed to allocate memory");
9502                         return -ENOMEM;
9503                 }
9504                 cap = cap->next;
9505         }
9506
9507         return 0;
9508 }
9509
9510 static void bnx2x_init_rte(struct bnx2x_softc *sc)
9511 {
9512         if (IS_VF(sc)) {
9513                 sc->max_tx_queues = min(BNX2X_VF_MAX_QUEUES_PER_VF,
9514                                         sc->igu_sb_cnt);
9515                 sc->max_rx_queues = min(BNX2X_VF_MAX_QUEUES_PER_VF,
9516                                         sc->igu_sb_cnt);
9517         } else {
9518                 sc->max_rx_queues = BNX2X_MAX_RSS_COUNT(sc);
9519                 sc->max_tx_queues = sc->max_rx_queues;
9520         }
9521 }
9522
9523 #define FW_HEADER_LEN 104
9524 #define FW_NAME_57711 "/lib/firmware/bnx2x/bnx2x-e1h-7.2.51.0.fw"
9525 #define FW_NAME_57810 "/lib/firmware/bnx2x/bnx2x-e2-7.2.51.0.fw"
9526
9527 void bnx2x_load_firmware(struct bnx2x_softc *sc)
9528 {
9529         const char *fwname;
9530         int f;
9531         struct stat st;
9532
9533         fwname = sc->devinfo.device_id == CHIP_NUM_57711
9534                 ? FW_NAME_57711 : FW_NAME_57810;
9535         f = open(fwname, O_RDONLY);
9536         if (f < 0) {
9537                 PMD_DRV_LOG(NOTICE, "Can't open firmware file");
9538                 return;
9539         }
9540
9541         if (fstat(f, &st) < 0) {
9542                 PMD_DRV_LOG(NOTICE, "Can't stat firmware file");
9543                 close(f);
9544                 return;
9545         }
9546
9547         sc->firmware = rte_zmalloc("bnx2x_fw", st.st_size, RTE_CACHE_LINE_SIZE);
9548         if (!sc->firmware) {
9549                 PMD_DRV_LOG(NOTICE, "Can't allocate memory for firmware");
9550                 close(f);
9551                 return;
9552         }
9553
9554         if (read(f, sc->firmware, st.st_size) != st.st_size) {
9555                 PMD_DRV_LOG(NOTICE, "Can't read firmware data");
9556                 close(f);
9557                 return;
9558         }
9559         close(f);
9560
9561         sc->fw_len = st.st_size;
9562         if (sc->fw_len < FW_HEADER_LEN) {
9563                 PMD_DRV_LOG(NOTICE, "Invalid fw size: %" PRIu64, sc->fw_len);
9564                 return;
9565         }
9566         PMD_DRV_LOG(DEBUG, "fw_len = %" PRIu64, sc->fw_len);
9567 }
9568
9569 static void
9570 bnx2x_data_to_init_ops(uint8_t * data, struct raw_op *dst, uint32_t len)
9571 {
9572         uint32_t *src = (uint32_t *) data;
9573         uint32_t i, j, tmp;
9574
9575         for (i = 0, j = 0; i < len / 8; ++i, j += 2) {
9576                 tmp = rte_be_to_cpu_32(src[j]);
9577                 dst[i].op = (tmp >> 24) & 0xFF;
9578                 dst[i].offset = tmp & 0xFFFFFF;
9579                 dst[i].raw_data = rte_be_to_cpu_32(src[j + 1]);
9580         }
9581 }
9582
9583 static void
9584 bnx2x_data_to_init_offsets(uint8_t * data, uint16_t * dst, uint32_t len)
9585 {
9586         uint16_t *src = (uint16_t *) data;
9587         uint32_t i;
9588
9589         for (i = 0; i < len / 2; ++i)
9590                 dst[i] = rte_be_to_cpu_16(src[i]);
9591 }
9592
9593 static void bnx2x_data_to_init_data(uint8_t * data, uint32_t * dst, uint32_t len)
9594 {
9595         uint32_t *src = (uint32_t *) data;
9596         uint32_t i;
9597
9598         for (i = 0; i < len / 4; ++i)
9599                 dst[i] = rte_be_to_cpu_32(src[i]);
9600 }
9601
9602 static void bnx2x_data_to_iro_array(uint8_t * data, struct iro *dst, uint32_t len)
9603 {
9604         uint32_t *src = (uint32_t *) data;
9605         uint32_t i, j, tmp;
9606
9607         for (i = 0, j = 0; i < len / sizeof(struct iro); ++i, ++j) {
9608                 dst[i].base = rte_be_to_cpu_32(src[j++]);
9609                 tmp = rte_be_to_cpu_32(src[j]);
9610                 dst[i].m1 = (tmp >> 16) & 0xFFFF;
9611                 dst[i].m2 = tmp & 0xFFFF;
9612                 ++j;
9613                 tmp = rte_be_to_cpu_32(src[j]);
9614                 dst[i].m3 = (tmp >> 16) & 0xFFFF;
9615                 dst[i].size = tmp & 0xFFFF;
9616         }
9617 }
9618
9619 /*
9620 * Device attach function.
9621 *
9622 * Allocates device resources, performs secondary chip identification, and
9623 * initializes driver instance variables. This function is called from driver
9624 * load after a successful probe.
9625 *
9626 * Returns:
9627 *   0 = Success, >0 = Failure
9628 */
9629 int bnx2x_attach(struct bnx2x_softc *sc)
9630 {
9631         int rc;
9632
9633         PMD_DRV_LOG(DEBUG, "Starting attach...");
9634
9635         rc = bnx2x_pci_get_caps(sc);
9636         if (rc) {
9637                 PMD_DRV_LOG(NOTICE, "PCIe caps reading was failed");
9638                 return rc;
9639         }
9640
9641         sc->state = BNX2X_STATE_CLOSED;
9642
9643         pci_write_long(sc, PCICFG_GRC_ADDRESS, PCICFG_VENDOR_ID_OFFSET);
9644
9645         sc->igu_base_addr = IS_VF(sc) ? PXP_VF_ADDR_IGU_START : BAR_IGU_INTMEM;
9646
9647         /* get PCI capabilites */
9648         bnx2x_probe_pci_caps(sc);
9649
9650         if (sc->devinfo.pcie_msix_cap_reg != 0) {
9651                 uint32_t val;
9652                 pci_read(sc,
9653                          (sc->devinfo.pcie_msix_cap_reg + PCIR_MSIX_CTRL), &val,
9654                          2);
9655                 sc->igu_sb_cnt = (val & PCIM_MSIXCTRL_TABLE_SIZE) + 1;
9656         } else {
9657                 sc->igu_sb_cnt = 1;
9658         }
9659
9660         /* Init RTE stuff */
9661         bnx2x_init_rte(sc);
9662
9663         if (IS_PF(sc)) {
9664                 /* Enable internal target-read (in case we are probed after PF
9665                  * FLR). Must be done prior to any BAR read access. Only for
9666                  * 57712 and up
9667                  */
9668                 if (!CHIP_IS_E1x(sc)) {
9669                         REG_WR(sc, PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_READ,
9670                                1);
9671                         DELAY(200000);
9672                 }
9673
9674                 /* get device info and set params */
9675                 if (bnx2x_get_device_info(sc) != 0) {
9676                         PMD_DRV_LOG(NOTICE, "getting device info");
9677                         return -ENXIO;
9678                 }
9679
9680 /* get phy settings from shmem and 'and' against admin settings */
9681                 bnx2x_get_phy_info(sc);
9682         } else {
9683                 /* Left mac of VF unfilled, PF should set it for VF */
9684                 memset(sc->link_params.mac_addr, 0, ETHER_ADDR_LEN);
9685         }
9686
9687         sc->wol = 0;
9688
9689         /* set the default MTU (changed via ifconfig) */
9690         sc->mtu = ETHER_MTU;
9691
9692         bnx2x_set_modes_bitmap(sc);
9693
9694         /* need to reset chip if UNDI was active */
9695         if (IS_PF(sc) && !BNX2X_NOMCP(sc)) {
9696 /* init fw_seq */
9697                 sc->fw_seq =
9698                     (SHMEM_RD(sc, func_mb[SC_FW_MB_IDX(sc)].drv_mb_header) &
9699                      DRV_MSG_SEQ_NUMBER_MASK);
9700                 bnx2x_prev_unload(sc);
9701         }
9702
9703         bnx2x_dcbx_set_state(sc, FALSE, BNX2X_DCBX_ENABLED_OFF);
9704
9705         /* calculate qm_cid_count */
9706         sc->qm_cid_count = bnx2x_set_qm_cid_count(sc);
9707
9708         sc->max_cos = 1;
9709         bnx2x_init_multi_cos(sc);
9710
9711         return 0;
9712 }
9713
9714 static void
9715 bnx2x_igu_ack_sb(struct bnx2x_softc *sc, uint8_t igu_sb_id, uint8_t segment,
9716                uint16_t index, uint8_t op, uint8_t update)
9717 {
9718         uint32_t igu_addr = sc->igu_base_addr;
9719         igu_addr += (IGU_CMD_INT_ACK_BASE + igu_sb_id) * 8;
9720         bnx2x_igu_ack_sb_gen(sc, segment, index, op, update, igu_addr);
9721 }
9722
9723 static void
9724 bnx2x_ack_sb(struct bnx2x_softc *sc, uint8_t igu_sb_id, uint8_t storm,
9725            uint16_t index, uint8_t op, uint8_t update)
9726 {
9727         if (unlikely(sc->devinfo.int_block == INT_BLOCK_HC))
9728                 bnx2x_hc_ack_sb(sc, igu_sb_id, storm, index, op, update);
9729         else {
9730                 uint8_t segment;
9731                 if (CHIP_INT_MODE_IS_BC(sc)) {
9732                         segment = storm;
9733                 } else if (igu_sb_id != sc->igu_dsb_id) {
9734                         segment = IGU_SEG_ACCESS_DEF;
9735                 } else if (storm == ATTENTION_ID) {
9736                         segment = IGU_SEG_ACCESS_ATTN;
9737                 } else {
9738                         segment = IGU_SEG_ACCESS_DEF;
9739                 }
9740                 bnx2x_igu_ack_sb(sc, igu_sb_id, segment, index, op, update);
9741         }
9742 }
9743
9744 static void
9745 bnx2x_igu_clear_sb_gen(struct bnx2x_softc *sc, uint8_t func, uint8_t idu_sb_id,
9746                      uint8_t is_pf)
9747 {
9748         uint32_t data, ctl, cnt = 100;
9749         uint32_t igu_addr_data = IGU_REG_COMMAND_REG_32LSB_DATA;
9750         uint32_t igu_addr_ctl = IGU_REG_COMMAND_REG_CTRL;
9751         uint32_t igu_addr_ack = IGU_REG_CSTORM_TYPE_0_SB_CLEANUP +
9752             (idu_sb_id / 32) * 4;
9753         uint32_t sb_bit = 1 << (idu_sb_id % 32);
9754         uint32_t func_encode = func |
9755             (is_pf ? 1 : 0) << IGU_FID_ENCODE_IS_PF_SHIFT;
9756         uint32_t addr_encode = IGU_CMD_E2_PROD_UPD_BASE + idu_sb_id;
9757
9758         /* Not supported in BC mode */
9759         if (CHIP_INT_MODE_IS_BC(sc)) {
9760                 return;
9761         }
9762
9763         data = ((IGU_USE_REGISTER_cstorm_type_0_sb_cleanup <<
9764                  IGU_REGULAR_CLEANUP_TYPE_SHIFT) |
9765                 IGU_REGULAR_CLEANUP_SET | IGU_REGULAR_BCLEANUP);
9766
9767         ctl = ((addr_encode << IGU_CTRL_REG_ADDRESS_SHIFT) |
9768                (func_encode << IGU_CTRL_REG_FID_SHIFT) |
9769                (IGU_CTRL_CMD_TYPE_WR << IGU_CTRL_REG_TYPE_SHIFT));
9770
9771         REG_WR(sc, igu_addr_data, data);
9772
9773         mb();
9774
9775         PMD_DRV_LOG(DEBUG, "write 0x%08x to IGU(via GRC) addr 0x%x",
9776                     ctl, igu_addr_ctl);
9777         REG_WR(sc, igu_addr_ctl, ctl);
9778
9779         mb();
9780
9781         /* wait for clean up to finish */
9782         while (!(REG_RD(sc, igu_addr_ack) & sb_bit) && --cnt) {
9783                 DELAY(20000);
9784         }
9785
9786         if (!(REG_RD(sc, igu_addr_ack) & sb_bit)) {
9787                 PMD_DRV_LOG(DEBUG,
9788                             "Unable to finish IGU cleanup: "
9789                             "idu_sb_id %d offset %d bit %d (cnt %d)",
9790                             idu_sb_id, idu_sb_id / 32, idu_sb_id % 32, cnt);
9791         }
9792 }
9793
9794 static void bnx2x_igu_clear_sb(struct bnx2x_softc *sc, uint8_t idu_sb_id)
9795 {
9796         bnx2x_igu_clear_sb_gen(sc, SC_FUNC(sc), idu_sb_id, TRUE /*PF*/);
9797 }
9798
9799 /*******************/
9800 /* ECORE CALLBACKS */
9801 /*******************/
9802
9803 static void bnx2x_reset_common(struct bnx2x_softc *sc)
9804 {
9805         uint32_t val = 0x1400;
9806
9807         PMD_INIT_FUNC_TRACE();
9808
9809         /* reset_common */
9810         REG_WR(sc, (GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR),
9811                0xd3ffff7f);
9812
9813         if (CHIP_IS_E3(sc)) {
9814                 val |= MISC_REGISTERS_RESET_REG_2_MSTAT0;
9815                 val |= MISC_REGISTERS_RESET_REG_2_MSTAT1;
9816         }
9817
9818         REG_WR(sc, (GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR), val);
9819 }
9820
9821 static void bnx2x_common_init_phy(struct bnx2x_softc *sc)
9822 {
9823         uint32_t shmem_base[2];
9824         uint32_t shmem2_base[2];
9825
9826         /* Avoid common init in case MFW supports LFA */
9827         if (SHMEM2_RD(sc, size) >
9828             (uint32_t) offsetof(struct shmem2_region,
9829                                 lfa_host_addr[SC_PORT(sc)])) {
9830                 return;
9831         }
9832
9833         shmem_base[0] = sc->devinfo.shmem_base;
9834         shmem2_base[0] = sc->devinfo.shmem2_base;
9835
9836         if (!CHIP_IS_E1x(sc)) {
9837                 shmem_base[1] = SHMEM2_RD(sc, other_shmem_base_addr);
9838                 shmem2_base[1] = SHMEM2_RD(sc, other_shmem2_base_addr);
9839         }
9840
9841         elink_common_init_phy(sc, shmem_base, shmem2_base,
9842                               sc->devinfo.chip_id, 0);
9843 }
9844
9845 static void bnx2x_pf_disable(struct bnx2x_softc *sc)
9846 {
9847         uint32_t val = REG_RD(sc, IGU_REG_PF_CONFIGURATION);
9848
9849         val &= ~IGU_PF_CONF_FUNC_EN;
9850
9851         REG_WR(sc, IGU_REG_PF_CONFIGURATION, val);
9852         REG_WR(sc, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 0);
9853         REG_WR(sc, CFC_REG_WEAK_ENABLE_PF, 0);
9854 }
9855
9856 static void bnx2x_init_pxp(struct bnx2x_softc *sc)
9857 {
9858         uint16_t devctl;
9859         int r_order, w_order;
9860
9861         devctl = bnx2x_pcie_capability_read(sc, PCIR_EXPRESS_DEVICE_CTL);
9862
9863         w_order = ((devctl & PCIM_EXP_CTL_MAX_PAYLOAD) >> 5);
9864         r_order = ((devctl & PCIM_EXP_CTL_MAX_READ_REQUEST) >> 12);
9865
9866         ecore_init_pxp_arb(sc, r_order, w_order);
9867 }
9868
9869 static uint32_t bnx2x_get_pretend_reg(struct bnx2x_softc *sc)
9870 {
9871         uint32_t base = PXP2_REG_PGL_PRETEND_FUNC_F0;
9872         uint32_t stride = (PXP2_REG_PGL_PRETEND_FUNC_F1 - base);
9873         return base + (SC_ABS_FUNC(sc)) * stride;
9874 }
9875
9876 /*
9877  * Called only on E1H or E2.
9878  * When pretending to be PF, the pretend value is the function number 0..7.
9879  * When pretending to be VF, the pretend val is the PF-num:VF-valid:ABS-VFID
9880  * combination.
9881  */
9882 static int bnx2x_pretend_func(struct bnx2x_softc *sc, uint16_t pretend_func_val)
9883 {
9884         uint32_t pretend_reg;
9885
9886         if (CHIP_IS_E1H(sc) && (pretend_func_val > E1H_FUNC_MAX))
9887                 return -1;
9888
9889         /* get my own pretend register */
9890         pretend_reg = bnx2x_get_pretend_reg(sc);
9891         REG_WR(sc, pretend_reg, pretend_func_val);
9892         REG_RD(sc, pretend_reg);
9893         return 0;
9894 }
9895
9896 static void bnx2x_setup_fan_failure_detection(struct bnx2x_softc *sc)
9897 {
9898         int is_required;
9899         uint32_t val;
9900         int port;
9901
9902         is_required = 0;
9903         val = (SHMEM_RD(sc, dev_info.shared_hw_config.config2) &
9904                SHARED_HW_CFG_FAN_FAILURE_MASK);
9905
9906         if (val == SHARED_HW_CFG_FAN_FAILURE_ENABLED) {
9907                 is_required = 1;
9908         }
9909         /*
9910          * The fan failure mechanism is usually related to the PHY type since
9911          * the power consumption of the board is affected by the PHY. Currently,
9912          * fan is required for most designs with SFX7101, BNX2X8727 and BNX2X8481.
9913          */
9914         else if (val == SHARED_HW_CFG_FAN_FAILURE_PHY_TYPE) {
9915                 for (port = PORT_0; port < PORT_MAX; port++) {
9916                         is_required |= elink_fan_failure_det_req(sc,
9917                                                                  sc->
9918                                                                  devinfo.shmem_base,
9919                                                                  sc->
9920                                                                  devinfo.shmem2_base,
9921                                                                  port);
9922                 }
9923         }
9924
9925         if (is_required == 0) {
9926                 return;
9927         }
9928
9929         /* Fan failure is indicated by SPIO 5 */
9930         bnx2x_set_spio(sc, MISC_SPIO_SPIO5, MISC_SPIO_INPUT_HI_Z);
9931
9932         /* set to active low mode */
9933         val = REG_RD(sc, MISC_REG_SPIO_INT);
9934         val |= (MISC_SPIO_SPIO5 << MISC_SPIO_INT_OLD_SET_POS);
9935         REG_WR(sc, MISC_REG_SPIO_INT, val);
9936
9937         /* enable interrupt to signal the IGU */
9938         val = REG_RD(sc, MISC_REG_SPIO_EVENT_EN);
9939         val |= MISC_SPIO_SPIO5;
9940         REG_WR(sc, MISC_REG_SPIO_EVENT_EN, val);
9941 }
9942
9943 static void bnx2x_enable_blocks_attention(struct bnx2x_softc *sc)
9944 {
9945         uint32_t val;
9946
9947         REG_WR(sc, PXP_REG_PXP_INT_MASK_0, 0);
9948         if (!CHIP_IS_E1x(sc)) {
9949                 REG_WR(sc, PXP_REG_PXP_INT_MASK_1, 0x40);
9950         } else {
9951                 REG_WR(sc, PXP_REG_PXP_INT_MASK_1, 0);
9952         }
9953         REG_WR(sc, DORQ_REG_DORQ_INT_MASK, 0);
9954         REG_WR(sc, CFC_REG_CFC_INT_MASK, 0);
9955         /*
9956          * mask read length error interrupts in brb for parser
9957          * (parsing unit and 'checksum and crc' unit)
9958          * these errors are legal (PU reads fixed length and CAC can cause
9959          * read length error on truncated packets)
9960          */
9961         REG_WR(sc, BRB1_REG_BRB1_INT_MASK, 0xFC00);
9962         REG_WR(sc, QM_REG_QM_INT_MASK, 0);
9963         REG_WR(sc, TM_REG_TM_INT_MASK, 0);
9964         REG_WR(sc, XSDM_REG_XSDM_INT_MASK_0, 0);
9965         REG_WR(sc, XSDM_REG_XSDM_INT_MASK_1, 0);
9966         REG_WR(sc, XCM_REG_XCM_INT_MASK, 0);
9967         /*      REG_WR(sc, XSEM_REG_XSEM_INT_MASK_0, 0); */
9968         /*      REG_WR(sc, XSEM_REG_XSEM_INT_MASK_1, 0); */
9969         REG_WR(sc, USDM_REG_USDM_INT_MASK_0, 0);
9970         REG_WR(sc, USDM_REG_USDM_INT_MASK_1, 0);
9971         REG_WR(sc, UCM_REG_UCM_INT_MASK, 0);
9972         /*      REG_WR(sc, USEM_REG_USEM_INT_MASK_0, 0); */
9973         /*      REG_WR(sc, USEM_REG_USEM_INT_MASK_1, 0); */
9974         REG_WR(sc, GRCBASE_UPB + PB_REG_PB_INT_MASK, 0);
9975         REG_WR(sc, CSDM_REG_CSDM_INT_MASK_0, 0);
9976         REG_WR(sc, CSDM_REG_CSDM_INT_MASK_1, 0);
9977         REG_WR(sc, CCM_REG_CCM_INT_MASK, 0);
9978         /*      REG_WR(sc, CSEM_REG_CSEM_INT_MASK_0, 0); */
9979         /*      REG_WR(sc, CSEM_REG_CSEM_INT_MASK_1, 0); */
9980
9981         val = (PXP2_PXP2_INT_MASK_0_REG_PGL_CPL_AFT |
9982                PXP2_PXP2_INT_MASK_0_REG_PGL_CPL_OF |
9983                PXP2_PXP2_INT_MASK_0_REG_PGL_PCIE_ATTN);
9984         if (!CHIP_IS_E1x(sc)) {
9985                 val |= (PXP2_PXP2_INT_MASK_0_REG_PGL_READ_BLOCKED |
9986                         PXP2_PXP2_INT_MASK_0_REG_PGL_WRITE_BLOCKED);
9987         }
9988         REG_WR(sc, PXP2_REG_PXP2_INT_MASK_0, val);
9989
9990         REG_WR(sc, TSDM_REG_TSDM_INT_MASK_0, 0);
9991         REG_WR(sc, TSDM_REG_TSDM_INT_MASK_1, 0);
9992         REG_WR(sc, TCM_REG_TCM_INT_MASK, 0);
9993         /*      REG_WR(sc, TSEM_REG_TSEM_INT_MASK_0, 0); */
9994
9995         if (!CHIP_IS_E1x(sc)) {
9996 /* enable VFC attentions: bits 11 and 12, bits 31:13 reserved */
9997                 REG_WR(sc, TSEM_REG_TSEM_INT_MASK_1, 0x07ff);
9998         }
9999
10000         REG_WR(sc, CDU_REG_CDU_INT_MASK, 0);
10001         REG_WR(sc, DMAE_REG_DMAE_INT_MASK, 0);
10002         /*      REG_WR(sc, MISC_REG_MISC_INT_MASK, 0); */
10003         REG_WR(sc, PBF_REG_PBF_INT_MASK, 0x18); /* bit 3,4 masked */
10004 }
10005
10006 /**
10007  * bnx2x_init_hw_common - initialize the HW at the COMMON phase.
10008  *
10009  * @sc:     driver handle
10010  */
10011 static int bnx2x_init_hw_common(struct bnx2x_softc *sc)
10012 {
10013         uint8_t abs_func_id;
10014         uint32_t val;
10015
10016         PMD_DRV_LOG(DEBUG, "starting common init for func %d", SC_ABS_FUNC(sc));
10017
10018         /*
10019          * take the RESET lock to protect undi_unload flow from accessing
10020          * registers while we are resetting the chip
10021          */
10022         bnx2x_acquire_hw_lock(sc, HW_LOCK_RESOURCE_RESET);
10023
10024         bnx2x_reset_common(sc);
10025
10026         REG_WR(sc, (GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET), 0xffffffff);
10027
10028         val = 0xfffc;
10029         if (CHIP_IS_E3(sc)) {
10030                 val |= MISC_REGISTERS_RESET_REG_2_MSTAT0;
10031                 val |= MISC_REGISTERS_RESET_REG_2_MSTAT1;
10032         }
10033
10034         REG_WR(sc, (GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET), val);
10035
10036         bnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_RESET);
10037
10038         ecore_init_block(sc, BLOCK_MISC, PHASE_COMMON);
10039
10040         if (!CHIP_IS_E1x(sc)) {
10041 /*
10042  * 4-port mode or 2-port mode we need to turn off master-enable for
10043  * everyone. After that we turn it back on for self. So, we disregard
10044  * multi-function, and always disable all functions on the given path,
10045  * this means 0,2,4,6 for path 0 and 1,3,5,7 for path 1
10046  */
10047                 for (abs_func_id = SC_PATH(sc);
10048                      abs_func_id < (E2_FUNC_MAX * 2); abs_func_id += 2) {
10049                         if (abs_func_id == SC_ABS_FUNC(sc)) {
10050                                 REG_WR(sc,
10051                                        PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER,
10052                                        1);
10053                                 continue;
10054                         }
10055
10056                         bnx2x_pretend_func(sc, abs_func_id);
10057
10058                         /* clear pf enable */
10059                         bnx2x_pf_disable(sc);
10060
10061                         bnx2x_pretend_func(sc, SC_ABS_FUNC(sc));
10062                 }
10063         }
10064
10065         ecore_init_block(sc, BLOCK_PXP, PHASE_COMMON);
10066
10067         ecore_init_block(sc, BLOCK_PXP2, PHASE_COMMON);
10068         bnx2x_init_pxp(sc);
10069
10070 #ifdef __BIG_ENDIAN
10071         REG_WR(sc, PXP2_REG_RQ_QM_ENDIAN_M, 1);
10072         REG_WR(sc, PXP2_REG_RQ_TM_ENDIAN_M, 1);
10073         REG_WR(sc, PXP2_REG_RQ_SRC_ENDIAN_M, 1);
10074         REG_WR(sc, PXP2_REG_RQ_CDU_ENDIAN_M, 1);
10075         REG_WR(sc, PXP2_REG_RQ_DBG_ENDIAN_M, 1);
10076         /* make sure this value is 0 */
10077         REG_WR(sc, PXP2_REG_RQ_HC_ENDIAN_M, 0);
10078
10079         //REG_WR(sc, PXP2_REG_RD_PBF_SWAP_MODE, 1);
10080         REG_WR(sc, PXP2_REG_RD_QM_SWAP_MODE, 1);
10081         REG_WR(sc, PXP2_REG_RD_TM_SWAP_MODE, 1);
10082         REG_WR(sc, PXP2_REG_RD_SRC_SWAP_MODE, 1);
10083         REG_WR(sc, PXP2_REG_RD_CDURD_SWAP_MODE, 1);
10084 #endif
10085
10086         ecore_ilt_init_page_size(sc, INITOP_SET);
10087
10088         if (CHIP_REV_IS_FPGA(sc) && CHIP_IS_E1H(sc)) {
10089                 REG_WR(sc, PXP2_REG_PGL_TAGS_LIMIT, 0x1);
10090         }
10091
10092         /* let the HW do it's magic... */
10093         DELAY(100000);
10094
10095         /* finish PXP init */
10096
10097         val = REG_RD(sc, PXP2_REG_RQ_CFG_DONE);
10098         if (val != 1) {
10099                 PMD_DRV_LOG(NOTICE, "PXP2 CFG failed");
10100                 return -1;
10101         }
10102         val = REG_RD(sc, PXP2_REG_RD_INIT_DONE);
10103         if (val != 1) {
10104                 PMD_DRV_LOG(NOTICE, "PXP2 RD_INIT failed");
10105                 return -1;
10106         }
10107
10108         /*
10109          * Timer bug workaround for E2 only. We need to set the entire ILT to have
10110          * entries with value "0" and valid bit on. This needs to be done by the
10111          * first PF that is loaded in a path (i.e. common phase)
10112          */
10113         if (!CHIP_IS_E1x(sc)) {
10114 /*
10115  * In E2 there is a bug in the timers block that can cause function 6 / 7
10116  * (i.e. vnic3) to start even if it is marked as "scan-off".
10117  * This occurs when a different function (func2,3) is being marked
10118  * as "scan-off". Real-life scenario for example: if a driver is being
10119  * load-unloaded while func6,7 are down. This will cause the timer to access
10120  * the ilt, translate to a logical address and send a request to read/write.
10121  * Since the ilt for the function that is down is not valid, this will cause
10122  * a translation error which is unrecoverable.
10123  * The Workaround is intended to make sure that when this happens nothing
10124  * fatal will occur. The workaround:
10125  *  1.  First PF driver which loads on a path will:
10126  *      a.  After taking the chip out of reset, by using pretend,
10127  *          it will write "0" to the following registers of
10128  *          the other vnics.
10129  *          REG_WR(pdev, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 0);
10130  *          REG_WR(pdev, CFC_REG_WEAK_ENABLE_PF,0);
10131  *          REG_WR(pdev, CFC_REG_STRONG_ENABLE_PF,0);
10132  *          And for itself it will write '1' to
10133  *          PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER to enable
10134  *          dmae-operations (writing to pram for example.)
10135  *          note: can be done for only function 6,7 but cleaner this
10136  *            way.
10137  *      b.  Write zero+valid to the entire ILT.
10138  *      c.  Init the first_timers_ilt_entry, last_timers_ilt_entry of
10139  *          VNIC3 (of that port). The range allocated will be the
10140  *          entire ILT. This is needed to prevent  ILT range error.
10141  *  2.  Any PF driver load flow:
10142  *      a.  ILT update with the physical addresses of the allocated
10143  *          logical pages.
10144  *      b.  Wait 20msec. - note that this timeout is needed to make
10145  *          sure there are no requests in one of the PXP internal
10146  *          queues with "old" ILT addresses.
10147  *      c.  PF enable in the PGLC.
10148  *      d.  Clear the was_error of the PF in the PGLC. (could have
10149  *          occurred while driver was down)
10150  *      e.  PF enable in the CFC (WEAK + STRONG)
10151  *      f.  Timers scan enable
10152  *  3.  PF driver unload flow:
10153  *      a.  Clear the Timers scan_en.
10154  *      b.  Polling for scan_on=0 for that PF.
10155  *      c.  Clear the PF enable bit in the PXP.
10156  *      d.  Clear the PF enable in the CFC (WEAK + STRONG)
10157  *      e.  Write zero+valid to all ILT entries (The valid bit must
10158  *          stay set)
10159  *      f.  If this is VNIC 3 of a port then also init
10160  *          first_timers_ilt_entry to zero and last_timers_ilt_entry
10161  *          to the last enrty in the ILT.
10162  *
10163  *      Notes:
10164  *      Currently the PF error in the PGLC is non recoverable.
10165  *      In the future the there will be a recovery routine for this error.
10166  *      Currently attention is masked.
10167  *      Having an MCP lock on the load/unload process does not guarantee that
10168  *      there is no Timer disable during Func6/7 enable. This is because the
10169  *      Timers scan is currently being cleared by the MCP on FLR.
10170  *      Step 2.d can be done only for PF6/7 and the driver can also check if
10171  *      there is error before clearing it. But the flow above is simpler and
10172  *      more general.
10173  *      All ILT entries are written by zero+valid and not just PF6/7
10174  *      ILT entries since in the future the ILT entries allocation for
10175  *      PF-s might be dynamic.
10176  */
10177                 struct ilt_client_info ilt_cli;
10178                 struct ecore_ilt ilt;
10179
10180                 memset(&ilt_cli, 0, sizeof(struct ilt_client_info));
10181                 memset(&ilt, 0, sizeof(struct ecore_ilt));
10182
10183 /* initialize dummy TM client */
10184                 ilt_cli.start = 0;
10185                 ilt_cli.end = ILT_NUM_PAGE_ENTRIES - 1;
10186                 ilt_cli.client_num = ILT_CLIENT_TM;
10187
10188 /*
10189  * Step 1: set zeroes to all ilt page entries with valid bit on
10190  * Step 2: set the timers first/last ilt entry to point
10191  * to the entire range to prevent ILT range error for 3rd/4th
10192  * vnic (this code assumes existence of the vnic)
10193  *
10194  * both steps performed by call to ecore_ilt_client_init_op()
10195  * with dummy TM client
10196  *
10197  * we must use pretend since PXP2_REG_RQ_##blk##_FIRST_ILT
10198  * and his brother are split registers
10199  */
10200
10201                 bnx2x_pretend_func(sc, (SC_PATH(sc) + 6));
10202                 ecore_ilt_client_init_op_ilt(sc, &ilt, &ilt_cli, INITOP_CLEAR);
10203                 bnx2x_pretend_func(sc, SC_ABS_FUNC(sc));
10204
10205                 REG_WR(sc, PXP2_REG_RQ_DRAM_ALIGN, BNX2X_PXP_DRAM_ALIGN);
10206                 REG_WR(sc, PXP2_REG_RQ_DRAM_ALIGN_RD, BNX2X_PXP_DRAM_ALIGN);
10207                 REG_WR(sc, PXP2_REG_RQ_DRAM_ALIGN_SEL, 1);
10208         }
10209
10210         REG_WR(sc, PXP2_REG_RQ_DISABLE_INPUTS, 0);
10211         REG_WR(sc, PXP2_REG_RD_DISABLE_INPUTS, 0);
10212
10213         if (!CHIP_IS_E1x(sc)) {
10214                 int factor = 0;
10215
10216                 ecore_init_block(sc, BLOCK_PGLUE_B, PHASE_COMMON);
10217                 ecore_init_block(sc, BLOCK_ATC, PHASE_COMMON);
10218
10219 /* let the HW do it's magic... */
10220                 do {
10221                         DELAY(200000);
10222                         val = REG_RD(sc, ATC_REG_ATC_INIT_DONE);
10223                 } while (factor-- && (val != 1));
10224
10225                 if (val != 1) {
10226                         PMD_DRV_LOG(NOTICE, "ATC_INIT failed");
10227                         return -1;
10228                 }
10229         }
10230
10231         ecore_init_block(sc, BLOCK_DMAE, PHASE_COMMON);
10232
10233         /* clean the DMAE memory */
10234         sc->dmae_ready = 1;
10235         ecore_init_fill(sc, TSEM_REG_PRAM, 0, 8);
10236
10237         ecore_init_block(sc, BLOCK_TCM, PHASE_COMMON);
10238
10239         ecore_init_block(sc, BLOCK_UCM, PHASE_COMMON);
10240
10241         ecore_init_block(sc, BLOCK_CCM, PHASE_COMMON);
10242
10243         ecore_init_block(sc, BLOCK_XCM, PHASE_COMMON);
10244
10245         bnx2x_read_dmae(sc, XSEM_REG_PASSIVE_BUFFER, 3);
10246         bnx2x_read_dmae(sc, CSEM_REG_PASSIVE_BUFFER, 3);
10247         bnx2x_read_dmae(sc, TSEM_REG_PASSIVE_BUFFER, 3);
10248         bnx2x_read_dmae(sc, USEM_REG_PASSIVE_BUFFER, 3);
10249
10250         ecore_init_block(sc, BLOCK_QM, PHASE_COMMON);
10251
10252         /* QM queues pointers table */
10253         ecore_qm_init_ptr_table(sc, sc->qm_cid_count, INITOP_SET);
10254
10255         /* soft reset pulse */
10256         REG_WR(sc, QM_REG_SOFT_RESET, 1);
10257         REG_WR(sc, QM_REG_SOFT_RESET, 0);
10258
10259         if (CNIC_SUPPORT(sc))
10260                 ecore_init_block(sc, BLOCK_TM, PHASE_COMMON);
10261
10262         ecore_init_block(sc, BLOCK_DORQ, PHASE_COMMON);
10263         REG_WR(sc, DORQ_REG_DPM_CID_OFST, BNX2X_DB_SHIFT);
10264
10265         if (!CHIP_REV_IS_SLOW(sc)) {
10266 /* enable hw interrupt from doorbell Q */
10267                 REG_WR(sc, DORQ_REG_DORQ_INT_MASK, 0);
10268         }
10269
10270         ecore_init_block(sc, BLOCK_BRB1, PHASE_COMMON);
10271
10272         ecore_init_block(sc, BLOCK_PRS, PHASE_COMMON);
10273         REG_WR(sc, PRS_REG_A_PRSU_20, 0xf);
10274         REG_WR(sc, PRS_REG_E1HOV_MODE, sc->devinfo.mf_info.path_has_ovlan);
10275
10276         if (!CHIP_IS_E1x(sc) && !CHIP_IS_E3B0(sc)) {
10277                 if (IS_MF_AFEX(sc)) {
10278                         /*
10279                          * configure that AFEX and VLAN headers must be
10280                          * received in AFEX mode
10281                          */
10282                         REG_WR(sc, PRS_REG_HDRS_AFTER_BASIC, 0xE);
10283                         REG_WR(sc, PRS_REG_MUST_HAVE_HDRS, 0xA);
10284                         REG_WR(sc, PRS_REG_HDRS_AFTER_TAG_0, 0x6);
10285                         REG_WR(sc, PRS_REG_TAG_ETHERTYPE_0, 0x8926);
10286                         REG_WR(sc, PRS_REG_TAG_LEN_0, 0x4);
10287                 } else {
10288                         /*
10289                          * Bit-map indicating which L2 hdrs may appear
10290                          * after the basic Ethernet header
10291                          */
10292                         REG_WR(sc, PRS_REG_HDRS_AFTER_BASIC,
10293                                sc->devinfo.mf_info.path_has_ovlan ? 7 : 6);
10294                 }
10295         }
10296
10297         ecore_init_block(sc, BLOCK_TSDM, PHASE_COMMON);
10298         ecore_init_block(sc, BLOCK_CSDM, PHASE_COMMON);
10299         ecore_init_block(sc, BLOCK_USDM, PHASE_COMMON);
10300         ecore_init_block(sc, BLOCK_XSDM, PHASE_COMMON);
10301
10302         if (!CHIP_IS_E1x(sc)) {
10303 /* reset VFC memories */
10304                 REG_WR(sc, TSEM_REG_FAST_MEMORY + VFC_REG_MEMORIES_RST,
10305                        VFC_MEMORIES_RST_REG_CAM_RST |
10306                        VFC_MEMORIES_RST_REG_RAM_RST);
10307                 REG_WR(sc, XSEM_REG_FAST_MEMORY + VFC_REG_MEMORIES_RST,
10308                        VFC_MEMORIES_RST_REG_CAM_RST |
10309                        VFC_MEMORIES_RST_REG_RAM_RST);
10310
10311                 DELAY(20000);
10312         }
10313
10314         ecore_init_block(sc, BLOCK_TSEM, PHASE_COMMON);
10315         ecore_init_block(sc, BLOCK_USEM, PHASE_COMMON);
10316         ecore_init_block(sc, BLOCK_CSEM, PHASE_COMMON);
10317         ecore_init_block(sc, BLOCK_XSEM, PHASE_COMMON);
10318
10319         /* sync semi rtc */
10320         REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR, 0x80000000);
10321         REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, 0x80000000);
10322
10323         ecore_init_block(sc, BLOCK_UPB, PHASE_COMMON);
10324         ecore_init_block(sc, BLOCK_XPB, PHASE_COMMON);
10325         ecore_init_block(sc, BLOCK_PBF, PHASE_COMMON);
10326
10327         if (!CHIP_IS_E1x(sc)) {
10328                 if (IS_MF_AFEX(sc)) {
10329                         /*
10330                          * configure that AFEX and VLAN headers must be
10331                          * sent in AFEX mode
10332                          */
10333                         REG_WR(sc, PBF_REG_HDRS_AFTER_BASIC, 0xE);
10334                         REG_WR(sc, PBF_REG_MUST_HAVE_HDRS, 0xA);
10335                         REG_WR(sc, PBF_REG_HDRS_AFTER_TAG_0, 0x6);
10336                         REG_WR(sc, PBF_REG_TAG_ETHERTYPE_0, 0x8926);
10337                         REG_WR(sc, PBF_REG_TAG_LEN_0, 0x4);
10338                 } else {
10339                         REG_WR(sc, PBF_REG_HDRS_AFTER_BASIC,
10340                                sc->devinfo.mf_info.path_has_ovlan ? 7 : 6);
10341                 }
10342         }
10343
10344         REG_WR(sc, SRC_REG_SOFT_RST, 1);
10345
10346         ecore_init_block(sc, BLOCK_SRC, PHASE_COMMON);
10347
10348         if (CNIC_SUPPORT(sc)) {
10349                 REG_WR(sc, SRC_REG_KEYSEARCH_0, 0x63285672);
10350                 REG_WR(sc, SRC_REG_KEYSEARCH_1, 0x24b8f2cc);
10351                 REG_WR(sc, SRC_REG_KEYSEARCH_2, 0x223aef9b);
10352                 REG_WR(sc, SRC_REG_KEYSEARCH_3, 0x26001e3a);
10353                 REG_WR(sc, SRC_REG_KEYSEARCH_4, 0x7ae91116);
10354                 REG_WR(sc, SRC_REG_KEYSEARCH_5, 0x5ce5230b);
10355                 REG_WR(sc, SRC_REG_KEYSEARCH_6, 0x298d8adf);
10356                 REG_WR(sc, SRC_REG_KEYSEARCH_7, 0x6eb0ff09);
10357                 REG_WR(sc, SRC_REG_KEYSEARCH_8, 0x1830f82f);
10358                 REG_WR(sc, SRC_REG_KEYSEARCH_9, 0x01e46be7);
10359         }
10360         REG_WR(sc, SRC_REG_SOFT_RST, 0);
10361
10362         if (sizeof(union cdu_context) != 1024) {
10363 /* we currently assume that a context is 1024 bytes */
10364                 PMD_DRV_LOG(NOTICE,
10365                             "please adjust the size of cdu_context(%ld)",
10366                             (long)sizeof(union cdu_context));
10367         }
10368
10369         ecore_init_block(sc, BLOCK_CDU, PHASE_COMMON);
10370         val = (4 << 24) + (0 << 12) + 1024;
10371         REG_WR(sc, CDU_REG_CDU_GLOBAL_PARAMS, val);
10372
10373         ecore_init_block(sc, BLOCK_CFC, PHASE_COMMON);
10374
10375         REG_WR(sc, CFC_REG_INIT_REG, 0x7FF);
10376         /* enable context validation interrupt from CFC */
10377         REG_WR(sc, CFC_REG_CFC_INT_MASK, 0);
10378
10379         /* set the thresholds to prevent CFC/CDU race */
10380         REG_WR(sc, CFC_REG_DEBUG0, 0x20020000);
10381         ecore_init_block(sc, BLOCK_HC, PHASE_COMMON);
10382
10383         if (!CHIP_IS_E1x(sc) && BNX2X_NOMCP(sc)) {
10384                 REG_WR(sc, IGU_REG_RESET_MEMORIES, 0x36);
10385         }
10386
10387         ecore_init_block(sc, BLOCK_IGU, PHASE_COMMON);
10388         ecore_init_block(sc, BLOCK_MISC_AEU, PHASE_COMMON);
10389
10390         /* Reset PCIE errors for debug */
10391         REG_WR(sc, 0x2814, 0xffffffff);
10392         REG_WR(sc, 0x3820, 0xffffffff);
10393
10394         if (!CHIP_IS_E1x(sc)) {
10395                 REG_WR(sc, PCICFG_OFFSET + PXPCS_TL_CONTROL_5,
10396                        (PXPCS_TL_CONTROL_5_ERR_UNSPPORT1 |
10397                         PXPCS_TL_CONTROL_5_ERR_UNSPPORT));
10398                 REG_WR(sc, PCICFG_OFFSET + PXPCS_TL_FUNC345_STAT,
10399                        (PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT4 |
10400                         PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT3 |
10401                         PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT2));
10402                 REG_WR(sc, PCICFG_OFFSET + PXPCS_TL_FUNC678_STAT,
10403                        (PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT7 |
10404                         PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT6 |
10405                         PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT5));
10406         }
10407
10408         ecore_init_block(sc, BLOCK_NIG, PHASE_COMMON);
10409
10410         /* in E3 this done in per-port section */
10411         if (!CHIP_IS_E3(sc))
10412                 REG_WR(sc, NIG_REG_LLH_MF_MODE, IS_MF(sc));
10413
10414         if (CHIP_IS_E1H(sc)) {
10415 /* not applicable for E2 (and above ...) */
10416                 REG_WR(sc, NIG_REG_LLH_E1HOV_MODE, IS_MF_SD(sc));
10417         }
10418
10419         if (CHIP_REV_IS_SLOW(sc)) {
10420                 DELAY(200000);
10421         }
10422
10423         /* finish CFC init */
10424         val = reg_poll(sc, CFC_REG_LL_INIT_DONE, 1, 100, 10);
10425         if (val != 1) {
10426                 PMD_DRV_LOG(NOTICE, "CFC LL_INIT failed");
10427                 return -1;
10428         }
10429         val = reg_poll(sc, CFC_REG_AC_INIT_DONE, 1, 100, 10);
10430         if (val != 1) {
10431                 PMD_DRV_LOG(NOTICE, "CFC AC_INIT failed");
10432                 return -1;
10433         }
10434         val = reg_poll(sc, CFC_REG_CAM_INIT_DONE, 1, 100, 10);
10435         if (val != 1) {
10436                 PMD_DRV_LOG(NOTICE, "CFC CAM_INIT failed");
10437                 return -1;
10438         }
10439         REG_WR(sc, CFC_REG_DEBUG0, 0);
10440
10441         bnx2x_setup_fan_failure_detection(sc);
10442
10443         /* clear PXP2 attentions */
10444         REG_RD(sc, PXP2_REG_PXP2_INT_STS_CLR_0);
10445
10446         bnx2x_enable_blocks_attention(sc);
10447
10448         if (!CHIP_REV_IS_SLOW(sc)) {
10449                 ecore_enable_blocks_parity(sc);
10450         }
10451
10452         if (!BNX2X_NOMCP(sc)) {
10453                 if (CHIP_IS_E1x(sc)) {
10454                         bnx2x_common_init_phy(sc);
10455                 }
10456         }
10457
10458         return 0;
10459 }
10460
10461 /**
10462  * bnx2x_init_hw_common_chip - init HW at the COMMON_CHIP phase.
10463  *
10464  * @sc:     driver handle
10465  */
10466 static int bnx2x_init_hw_common_chip(struct bnx2x_softc *sc)
10467 {
10468         int rc = bnx2x_init_hw_common(sc);
10469
10470         if (rc) {
10471                 return rc;
10472         }
10473
10474         /* In E2 2-PORT mode, same ext phy is used for the two paths */
10475         if (!BNX2X_NOMCP(sc)) {
10476                 bnx2x_common_init_phy(sc);
10477         }
10478
10479         return 0;
10480 }
10481
10482 static int bnx2x_init_hw_port(struct bnx2x_softc *sc)
10483 {
10484         int port = SC_PORT(sc);
10485         int init_phase = port ? PHASE_PORT1 : PHASE_PORT0;
10486         uint32_t low, high;
10487         uint32_t val;
10488
10489         PMD_DRV_LOG(DEBUG, "starting port init for port %d", port);
10490
10491         REG_WR(sc, NIG_REG_MASK_INTERRUPT_PORT0 + port * 4, 0);
10492
10493         ecore_init_block(sc, BLOCK_MISC, init_phase);
10494         ecore_init_block(sc, BLOCK_PXP, init_phase);
10495         ecore_init_block(sc, BLOCK_PXP2, init_phase);
10496
10497         /*
10498          * Timers bug workaround: disables the pf_master bit in pglue at
10499          * common phase, we need to enable it here before any dmae access are
10500          * attempted. Therefore we manually added the enable-master to the
10501          * port phase (it also happens in the function phase)
10502          */
10503         if (!CHIP_IS_E1x(sc)) {
10504                 REG_WR(sc, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 1);
10505         }
10506
10507         ecore_init_block(sc, BLOCK_ATC, init_phase);
10508         ecore_init_block(sc, BLOCK_DMAE, init_phase);
10509         ecore_init_block(sc, BLOCK_PGLUE_B, init_phase);
10510         ecore_init_block(sc, BLOCK_QM, init_phase);
10511
10512         ecore_init_block(sc, BLOCK_TCM, init_phase);
10513         ecore_init_block(sc, BLOCK_UCM, init_phase);
10514         ecore_init_block(sc, BLOCK_CCM, init_phase);
10515         ecore_init_block(sc, BLOCK_XCM, init_phase);
10516
10517         /* QM cid (connection) count */
10518         ecore_qm_init_cid_count(sc, sc->qm_cid_count, INITOP_SET);
10519
10520         if (CNIC_SUPPORT(sc)) {
10521                 ecore_init_block(sc, BLOCK_TM, init_phase);
10522                 REG_WR(sc, TM_REG_LIN0_SCAN_TIME + port * 4, 20);
10523                 REG_WR(sc, TM_REG_LIN0_MAX_ACTIVE_CID + port * 4, 31);
10524         }
10525
10526         ecore_init_block(sc, BLOCK_DORQ, init_phase);
10527
10528         ecore_init_block(sc, BLOCK_BRB1, init_phase);
10529
10530         if (CHIP_IS_E1H(sc)) {
10531                 if (IS_MF(sc)) {
10532                         low = (BNX2X_ONE_PORT(sc) ? 160 : 246);
10533                 } else if (sc->mtu > 4096) {
10534                         if (BNX2X_ONE_PORT(sc)) {
10535                                 low = 160;
10536                         } else {
10537                                 val = sc->mtu;
10538                                 /* (24*1024 + val*4)/256 */
10539                                 low = (96 + (val / 64) + ((val % 64) ? 1 : 0));
10540                         }
10541                 } else {
10542                         low = (BNX2X_ONE_PORT(sc) ? 80 : 160);
10543                 }
10544                 high = (low + 56);      /* 14*1024/256 */
10545                 REG_WR(sc, BRB1_REG_PAUSE_LOW_THRESHOLD_0 + port * 4, low);
10546                 REG_WR(sc, BRB1_REG_PAUSE_HIGH_THRESHOLD_0 + port * 4, high);
10547         }
10548
10549         if (CHIP_IS_MODE_4_PORT(sc)) {
10550                 REG_WR(sc, SC_PORT(sc) ?
10551                        BRB1_REG_MAC_GUARANTIED_1 :
10552                        BRB1_REG_MAC_GUARANTIED_0, 40);
10553         }
10554
10555         ecore_init_block(sc, BLOCK_PRS, init_phase);
10556         if (CHIP_IS_E3B0(sc)) {
10557                 if (IS_MF_AFEX(sc)) {
10558                         /* configure headers for AFEX mode */
10559                         if (SC_PORT(sc)) {
10560                                 REG_WR(sc, PRS_REG_HDRS_AFTER_BASIC_PORT_1,
10561                                        0xE);
10562                                 REG_WR(sc, PRS_REG_HDRS_AFTER_TAG_0_PORT_1,
10563                                        0x6);
10564                                 REG_WR(sc, PRS_REG_MUST_HAVE_HDRS_PORT_1, 0xA);
10565                         } else {
10566                                 REG_WR(sc, PRS_REG_HDRS_AFTER_BASIC_PORT_0,
10567                                        0xE);
10568                                 REG_WR(sc, PRS_REG_HDRS_AFTER_TAG_0_PORT_0,
10569                                        0x6);
10570                                 REG_WR(sc, PRS_REG_MUST_HAVE_HDRS_PORT_0, 0xA);
10571                         }
10572                 } else {
10573                         /* Ovlan exists only if we are in multi-function +
10574                          * switch-dependent mode, in switch-independent there
10575                          * is no ovlan headers
10576                          */
10577                         REG_WR(sc, SC_PORT(sc) ?
10578                                PRS_REG_HDRS_AFTER_BASIC_PORT_1 :
10579                                PRS_REG_HDRS_AFTER_BASIC_PORT_0,
10580                                (sc->devinfo.mf_info.path_has_ovlan ? 7 : 6));
10581                 }
10582         }
10583
10584         ecore_init_block(sc, BLOCK_TSDM, init_phase);
10585         ecore_init_block(sc, BLOCK_CSDM, init_phase);
10586         ecore_init_block(sc, BLOCK_USDM, init_phase);
10587         ecore_init_block(sc, BLOCK_XSDM, init_phase);
10588
10589         ecore_init_block(sc, BLOCK_TSEM, init_phase);
10590         ecore_init_block(sc, BLOCK_USEM, init_phase);
10591         ecore_init_block(sc, BLOCK_CSEM, init_phase);
10592         ecore_init_block(sc, BLOCK_XSEM, init_phase);
10593
10594         ecore_init_block(sc, BLOCK_UPB, init_phase);
10595         ecore_init_block(sc, BLOCK_XPB, init_phase);
10596
10597         ecore_init_block(sc, BLOCK_PBF, init_phase);
10598
10599         if (CHIP_IS_E1x(sc)) {
10600 /* configure PBF to work without PAUSE mtu 9000 */
10601                 REG_WR(sc, PBF_REG_P0_PAUSE_ENABLE + port * 4, 0);
10602
10603 /* update threshold */
10604                 REG_WR(sc, PBF_REG_P0_ARB_THRSH + port * 4, (9040 / 16));
10605 /* update init credit */
10606                 REG_WR(sc, PBF_REG_P0_INIT_CRD + port * 4,
10607                        (9040 / 16) + 553 - 22);
10608
10609 /* probe changes */
10610                 REG_WR(sc, PBF_REG_INIT_P0 + port * 4, 1);
10611                 DELAY(50);
10612                 REG_WR(sc, PBF_REG_INIT_P0 + port * 4, 0);
10613         }
10614
10615         if (CNIC_SUPPORT(sc)) {
10616                 ecore_init_block(sc, BLOCK_SRC, init_phase);
10617         }
10618
10619         ecore_init_block(sc, BLOCK_CDU, init_phase);
10620         ecore_init_block(sc, BLOCK_CFC, init_phase);
10621         ecore_init_block(sc, BLOCK_HC, init_phase);
10622         ecore_init_block(sc, BLOCK_IGU, init_phase);
10623         ecore_init_block(sc, BLOCK_MISC_AEU, init_phase);
10624         /* init aeu_mask_attn_func_0/1:
10625          *  - SF mode: bits 3-7 are masked. only bits 0-2 are in use
10626          *  - MF mode: bit 3 is masked. bits 0-2 are in use as in SF
10627          *             bits 4-7 are used for "per vn group attention" */
10628         val = IS_MF(sc) ? 0xF7 : 0x7;
10629         val |= 0x10;
10630         REG_WR(sc, MISC_REG_AEU_MASK_ATTN_FUNC_0 + port * 4, val);
10631
10632         ecore_init_block(sc, BLOCK_NIG, init_phase);
10633
10634         if (!CHIP_IS_E1x(sc)) {
10635 /* Bit-map indicating which L2 hdrs may appear after the
10636  * basic Ethernet header
10637  */
10638                 if (IS_MF_AFEX(sc)) {
10639                         REG_WR(sc, SC_PORT(sc) ?
10640                                NIG_REG_P1_HDRS_AFTER_BASIC :
10641                                NIG_REG_P0_HDRS_AFTER_BASIC, 0xE);
10642                 } else {
10643                         REG_WR(sc, SC_PORT(sc) ?
10644                                NIG_REG_P1_HDRS_AFTER_BASIC :
10645                                NIG_REG_P0_HDRS_AFTER_BASIC,
10646                                IS_MF_SD(sc) ? 7 : 6);
10647                 }
10648
10649                 if (CHIP_IS_E3(sc)) {
10650                         REG_WR(sc, SC_PORT(sc) ?
10651                                NIG_REG_LLH1_MF_MODE :
10652                                NIG_REG_LLH_MF_MODE, IS_MF(sc));
10653                 }
10654         }
10655         if (!CHIP_IS_E3(sc)) {
10656                 REG_WR(sc, NIG_REG_XGXS_SERDES0_MODE_SEL + port * 4, 1);
10657         }
10658
10659         /* 0x2 disable mf_ov, 0x1 enable */
10660         REG_WR(sc, NIG_REG_LLH0_BRB1_DRV_MASK_MF + port * 4,
10661                (IS_MF_SD(sc) ? 0x1 : 0x2));
10662
10663         if (!CHIP_IS_E1x(sc)) {
10664                 val = 0;
10665                 switch (sc->devinfo.mf_info.mf_mode) {
10666                 case MULTI_FUNCTION_SD:
10667                         val = 1;
10668                         break;
10669                 case MULTI_FUNCTION_SI:
10670                 case MULTI_FUNCTION_AFEX:
10671                         val = 2;
10672                         break;
10673                 }
10674
10675                 REG_WR(sc, (SC_PORT(sc) ? NIG_REG_LLH1_CLS_TYPE :
10676                             NIG_REG_LLH0_CLS_TYPE), val);
10677         }
10678         REG_WR(sc, NIG_REG_LLFC_ENABLE_0 + port * 4, 0);
10679         REG_WR(sc, NIG_REG_LLFC_OUT_EN_0 + port * 4, 0);
10680         REG_WR(sc, NIG_REG_PAUSE_ENABLE_0 + port * 4, 1);
10681
10682         /* If SPIO5 is set to generate interrupts, enable it for this port */
10683         val = REG_RD(sc, MISC_REG_SPIO_EVENT_EN);
10684         if (val & MISC_SPIO_SPIO5) {
10685                 uint32_t reg_addr = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 :
10686                                      MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0);
10687                 val = REG_RD(sc, reg_addr);
10688                 val |= AEU_INPUTS_ATTN_BITS_SPIO5;
10689                 REG_WR(sc, reg_addr, val);
10690         }
10691
10692         return 0;
10693 }
10694
10695 static uint32_t
10696 bnx2x_flr_clnup_reg_poll(struct bnx2x_softc *sc, uint32_t reg,
10697                        uint32_t expected, uint32_t poll_count)
10698 {
10699         uint32_t cur_cnt = poll_count;
10700         uint32_t val;
10701
10702         while ((val = REG_RD(sc, reg)) != expected && cur_cnt--) {
10703                 DELAY(FLR_WAIT_INTERVAL);
10704         }
10705
10706         return val;
10707 }
10708
10709 static int
10710 bnx2x_flr_clnup_poll_hw_counter(struct bnx2x_softc *sc, uint32_t reg,
10711                               __rte_unused const char *msg, uint32_t poll_cnt)
10712 {
10713         uint32_t val = bnx2x_flr_clnup_reg_poll(sc, reg, 0, poll_cnt);
10714
10715         if (val != 0) {
10716                 PMD_DRV_LOG(NOTICE, "%s usage count=%d", msg, val);
10717                 return -1;
10718         }
10719
10720         return 0;
10721 }
10722
10723 /* Common routines with VF FLR cleanup */
10724 static uint32_t bnx2x_flr_clnup_poll_count(struct bnx2x_softc *sc)
10725 {
10726         /* adjust polling timeout */
10727         if (CHIP_REV_IS_EMUL(sc)) {
10728                 return FLR_POLL_CNT * 2000;
10729         }
10730
10731         if (CHIP_REV_IS_FPGA(sc)) {
10732                 return FLR_POLL_CNT * 120;
10733         }
10734
10735         return FLR_POLL_CNT;
10736 }
10737
10738 static int bnx2x_poll_hw_usage_counters(struct bnx2x_softc *sc, uint32_t poll_cnt)
10739 {
10740         /* wait for CFC PF usage-counter to zero (includes all the VFs) */
10741         if (bnx2x_flr_clnup_poll_hw_counter(sc,
10742                                           CFC_REG_NUM_LCIDS_INSIDE_PF,
10743                                           "CFC PF usage counter timed out",
10744                                           poll_cnt)) {
10745                 return -1;
10746         }
10747
10748         /* Wait for DQ PF usage-counter to zero (until DQ cleanup) */
10749         if (bnx2x_flr_clnup_poll_hw_counter(sc,
10750                                           DORQ_REG_PF_USAGE_CNT,
10751                                           "DQ PF usage counter timed out",
10752                                           poll_cnt)) {
10753                 return -1;
10754         }
10755
10756         /* Wait for QM PF usage-counter to zero (until DQ cleanup) */
10757         if (bnx2x_flr_clnup_poll_hw_counter(sc,
10758                                           QM_REG_PF_USG_CNT_0 + 4 * SC_FUNC(sc),
10759                                           "QM PF usage counter timed out",
10760                                           poll_cnt)) {
10761                 return -1;
10762         }
10763
10764         /* Wait for Timer PF usage-counters to zero (until DQ cleanup) */
10765         if (bnx2x_flr_clnup_poll_hw_counter(sc,
10766                                           TM_REG_LIN0_VNIC_UC + 4 * SC_PORT(sc),
10767                                           "Timers VNIC usage counter timed out",
10768                                           poll_cnt)) {
10769                 return -1;
10770         }
10771
10772         if (bnx2x_flr_clnup_poll_hw_counter(sc,
10773                                           TM_REG_LIN0_NUM_SCANS +
10774                                           4 * SC_PORT(sc),
10775                                           "Timers NUM_SCANS usage counter timed out",
10776                                           poll_cnt)) {
10777                 return -1;
10778         }
10779
10780         /* Wait DMAE PF usage counter to zero */
10781         if (bnx2x_flr_clnup_poll_hw_counter(sc,
10782                                           dmae_reg_go_c[INIT_DMAE_C(sc)],
10783                                           "DMAE dommand register timed out",
10784                                           poll_cnt)) {
10785                 return -1;
10786         }
10787
10788         return 0;
10789 }
10790
10791 #define OP_GEN_PARAM(param)                                            \
10792         (((param) << SDM_OP_GEN_COMP_PARAM_SHIFT) & SDM_OP_GEN_COMP_PARAM)
10793 #define OP_GEN_TYPE(type)                                           \
10794         (((type) << SDM_OP_GEN_COMP_TYPE_SHIFT) & SDM_OP_GEN_COMP_TYPE)
10795 #define OP_GEN_AGG_VECT(index)                                             \
10796         (((index) << SDM_OP_GEN_AGG_VECT_IDX_SHIFT) & SDM_OP_GEN_AGG_VECT_IDX)
10797
10798 static int
10799 bnx2x_send_final_clnup(struct bnx2x_softc *sc, uint8_t clnup_func,
10800                      uint32_t poll_cnt)
10801 {
10802         uint32_t op_gen_command = 0;
10803         uint32_t comp_addr = (BAR_CSTRORM_INTMEM +
10804                               CSTORM_FINAL_CLEANUP_COMPLETE_OFFSET(clnup_func));
10805         int ret = 0;
10806
10807         if (REG_RD(sc, comp_addr)) {
10808                 PMD_DRV_LOG(NOTICE,
10809                             "Cleanup complete was not 0 before sending");
10810                 return -1;
10811         }
10812
10813         op_gen_command |= OP_GEN_PARAM(XSTORM_AGG_INT_FINAL_CLEANUP_INDEX);
10814         op_gen_command |= OP_GEN_TYPE(XSTORM_AGG_INT_FINAL_CLEANUP_COMP_TYPE);
10815         op_gen_command |= OP_GEN_AGG_VECT(clnup_func);
10816         op_gen_command |= 1 << SDM_OP_GEN_AGG_VECT_IDX_VALID_SHIFT;
10817
10818         REG_WR(sc, XSDM_REG_OPERATION_GEN, op_gen_command);
10819
10820         if (bnx2x_flr_clnup_reg_poll(sc, comp_addr, 1, poll_cnt) != 1) {
10821                 PMD_DRV_LOG(NOTICE, "FW final cleanup did not succeed");
10822                 PMD_DRV_LOG(DEBUG, "At timeout completion address contained %x",
10823                             (REG_RD(sc, comp_addr)));
10824                 rte_panic("FLR cleanup failed");
10825                 return -1;
10826         }
10827
10828         /* Zero completion for nxt FLR */
10829         REG_WR(sc, comp_addr, 0);
10830
10831         return ret;
10832 }
10833
10834 static void
10835 bnx2x_pbf_pN_buf_flushed(struct bnx2x_softc *sc, struct pbf_pN_buf_regs *regs,
10836                        uint32_t poll_count)
10837 {
10838         uint32_t init_crd, crd, crd_start, crd_freed, crd_freed_start;
10839         uint32_t cur_cnt = poll_count;
10840
10841         crd_freed = crd_freed_start = REG_RD(sc, regs->crd_freed);
10842         crd = crd_start = REG_RD(sc, regs->crd);
10843         init_crd = REG_RD(sc, regs->init_crd);
10844
10845         while ((crd != init_crd) &&
10846                ((uint32_t) ((int32_t) crd_freed - (int32_t) crd_freed_start) <
10847                 (init_crd - crd_start))) {
10848                 if (cur_cnt--) {
10849                         DELAY(FLR_WAIT_INTERVAL);
10850                         crd = REG_RD(sc, regs->crd);
10851                         crd_freed = REG_RD(sc, regs->crd_freed);
10852                 } else {
10853                         break;
10854                 }
10855         }
10856 }
10857
10858 static void
10859 bnx2x_pbf_pN_cmd_flushed(struct bnx2x_softc *sc, struct pbf_pN_cmd_regs *regs,
10860                        uint32_t poll_count)
10861 {
10862         uint32_t occup, to_free, freed, freed_start;
10863         uint32_t cur_cnt = poll_count;
10864
10865         occup = to_free = REG_RD(sc, regs->lines_occup);
10866         freed = freed_start = REG_RD(sc, regs->lines_freed);
10867
10868         while (occup &&
10869                ((uint32_t) ((int32_t) freed - (int32_t) freed_start) <
10870                 to_free)) {
10871                 if (cur_cnt--) {
10872                         DELAY(FLR_WAIT_INTERVAL);
10873                         occup = REG_RD(sc, regs->lines_occup);
10874                         freed = REG_RD(sc, regs->lines_freed);
10875                 } else {
10876                         break;
10877                 }
10878         }
10879 }
10880
10881 static void bnx2x_tx_hw_flushed(struct bnx2x_softc *sc, uint32_t poll_count)
10882 {
10883         struct pbf_pN_cmd_regs cmd_regs[] = {
10884                 {0, (CHIP_IS_E3B0(sc)) ?
10885                  PBF_REG_TQ_OCCUPANCY_Q0 : PBF_REG_P0_TQ_OCCUPANCY,
10886                  (CHIP_IS_E3B0(sc)) ?
10887                  PBF_REG_TQ_LINES_FREED_CNT_Q0 : PBF_REG_P0_TQ_LINES_FREED_CNT},
10888                 {1, (CHIP_IS_E3B0(sc)) ?
10889                  PBF_REG_TQ_OCCUPANCY_Q1 : PBF_REG_P1_TQ_OCCUPANCY,
10890                  (CHIP_IS_E3B0(sc)) ?
10891                  PBF_REG_TQ_LINES_FREED_CNT_Q1 : PBF_REG_P1_TQ_LINES_FREED_CNT},
10892                 {4, (CHIP_IS_E3B0(sc)) ?
10893                  PBF_REG_TQ_OCCUPANCY_LB_Q : PBF_REG_P4_TQ_OCCUPANCY,
10894                  (CHIP_IS_E3B0(sc)) ?
10895                  PBF_REG_TQ_LINES_FREED_CNT_LB_Q :
10896                  PBF_REG_P4_TQ_LINES_FREED_CNT}
10897         };
10898
10899         struct pbf_pN_buf_regs buf_regs[] = {
10900                 {0, (CHIP_IS_E3B0(sc)) ?
10901                  PBF_REG_INIT_CRD_Q0 : PBF_REG_P0_INIT_CRD,
10902                  (CHIP_IS_E3B0(sc)) ? PBF_REG_CREDIT_Q0 : PBF_REG_P0_CREDIT,
10903                  (CHIP_IS_E3B0(sc)) ?
10904                  PBF_REG_INTERNAL_CRD_FREED_CNT_Q0 :
10905                  PBF_REG_P0_INTERNAL_CRD_FREED_CNT},
10906                 {1, (CHIP_IS_E3B0(sc)) ?
10907                  PBF_REG_INIT_CRD_Q1 : PBF_REG_P1_INIT_CRD,
10908                  (CHIP_IS_E3B0(sc)) ? PBF_REG_CREDIT_Q1 : PBF_REG_P1_CREDIT,
10909                  (CHIP_IS_E3B0(sc)) ?
10910                  PBF_REG_INTERNAL_CRD_FREED_CNT_Q1 :
10911                  PBF_REG_P1_INTERNAL_CRD_FREED_CNT},
10912                 {4, (CHIP_IS_E3B0(sc)) ?
10913                  PBF_REG_INIT_CRD_LB_Q : PBF_REG_P4_INIT_CRD,
10914                  (CHIP_IS_E3B0(sc)) ? PBF_REG_CREDIT_LB_Q : PBF_REG_P4_CREDIT,
10915                  (CHIP_IS_E3B0(sc)) ?
10916                  PBF_REG_INTERNAL_CRD_FREED_CNT_LB_Q :
10917                  PBF_REG_P4_INTERNAL_CRD_FREED_CNT},
10918         };
10919
10920         uint32_t i;
10921
10922         /* Verify the command queues are flushed P0, P1, P4 */
10923         for (i = 0; i < ARRAY_SIZE(cmd_regs); i++) {
10924                 bnx2x_pbf_pN_cmd_flushed(sc, &cmd_regs[i], poll_count);
10925         }
10926
10927         /* Verify the transmission buffers are flushed P0, P1, P4 */
10928         for (i = 0; i < ARRAY_SIZE(buf_regs); i++) {
10929                 bnx2x_pbf_pN_buf_flushed(sc, &buf_regs[i], poll_count);
10930         }
10931 }
10932
10933 static void bnx2x_hw_enable_status(struct bnx2x_softc *sc)
10934 {
10935         __rte_unused uint32_t val;
10936
10937         val = REG_RD(sc, CFC_REG_WEAK_ENABLE_PF);
10938         PMD_DRV_LOG(DEBUG, "CFC_REG_WEAK_ENABLE_PF is 0x%x", val);
10939
10940         val = REG_RD(sc, PBF_REG_DISABLE_PF);
10941         PMD_DRV_LOG(DEBUG, "PBF_REG_DISABLE_PF is 0x%x", val);
10942
10943         val = REG_RD(sc, IGU_REG_PCI_PF_MSI_EN);
10944         PMD_DRV_LOG(DEBUG, "IGU_REG_PCI_PF_MSI_EN is 0x%x", val);
10945
10946         val = REG_RD(sc, IGU_REG_PCI_PF_MSIX_EN);
10947         PMD_DRV_LOG(DEBUG, "IGU_REG_PCI_PF_MSIX_EN is 0x%x", val);
10948
10949         val = REG_RD(sc, IGU_REG_PCI_PF_MSIX_FUNC_MASK);
10950         PMD_DRV_LOG(DEBUG, "IGU_REG_PCI_PF_MSIX_FUNC_MASK is 0x%x", val);
10951
10952         val = REG_RD(sc, PGLUE_B_REG_SHADOW_BME_PF_7_0_CLR);
10953         PMD_DRV_LOG(DEBUG, "PGLUE_B_REG_SHADOW_BME_PF_7_0_CLR is 0x%x", val);
10954
10955         val = REG_RD(sc, PGLUE_B_REG_FLR_REQUEST_PF_7_0_CLR);
10956         PMD_DRV_LOG(DEBUG, "PGLUE_B_REG_FLR_REQUEST_PF_7_0_CLR is 0x%x", val);
10957
10958         val = REG_RD(sc, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER);
10959         PMD_DRV_LOG(DEBUG, "PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER is 0x%x",
10960                     val);
10961 }
10962
10963 /**
10964  *      bnx2x_pf_flr_clnup
10965  *      a. re-enable target read on the PF
10966  *      b. poll cfc per function usgae counter
10967  *      c. poll the qm perfunction usage counter
10968  *      d. poll the tm per function usage counter
10969  *      e. poll the tm per function scan-done indication
10970  *      f. clear the dmae channel associated wit hthe PF
10971  *      g. zero the igu 'trailing edge' and 'leading edge' regs (attentions)
10972  *      h. call the common flr cleanup code with -1 (pf indication)
10973  */
10974 static int bnx2x_pf_flr_clnup(struct bnx2x_softc *sc)
10975 {
10976         uint32_t poll_cnt = bnx2x_flr_clnup_poll_count(sc);
10977
10978         /* Re-enable PF target read access */
10979         REG_WR(sc, PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_READ, 1);
10980
10981         /* Poll HW usage counters */
10982         if (bnx2x_poll_hw_usage_counters(sc, poll_cnt)) {
10983                 return -1;
10984         }
10985
10986         /* Zero the igu 'trailing edge' and 'leading edge' */
10987
10988         /* Send the FW cleanup command */
10989         if (bnx2x_send_final_clnup(sc, (uint8_t) SC_FUNC(sc), poll_cnt)) {
10990                 return -1;
10991         }
10992
10993         /* ATC cleanup */
10994
10995         /* Verify TX hw is flushed */
10996         bnx2x_tx_hw_flushed(sc, poll_cnt);
10997
10998         /* Wait 100ms (not adjusted according to platform) */
10999         DELAY(100000);
11000
11001         /* Verify no pending pci transactions */
11002         if (bnx2x_is_pcie_pending(sc)) {
11003                 PMD_DRV_LOG(NOTICE, "PCIE Transactions still pending");
11004         }
11005
11006         /* Debug */
11007         bnx2x_hw_enable_status(sc);
11008
11009         /*
11010          * Master enable - Due to WB DMAE writes performed before this
11011          * register is re-initialized as part of the regular function init
11012          */
11013         REG_WR(sc, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 1);
11014
11015         return 0;
11016 }
11017
11018 static int bnx2x_init_hw_func(struct bnx2x_softc *sc)
11019 {
11020         int port = SC_PORT(sc);
11021         int func = SC_FUNC(sc);
11022         int init_phase = PHASE_PF0 + func;
11023         struct ecore_ilt *ilt = sc->ilt;
11024         uint16_t cdu_ilt_start;
11025         uint32_t addr, val;
11026         uint32_t main_mem_base, main_mem_size, main_mem_prty_clr;
11027         int main_mem_width, rc;
11028         uint32_t i;
11029
11030         PMD_DRV_LOG(DEBUG, "starting func init for func %d", func);
11031
11032         /* FLR cleanup */
11033         if (!CHIP_IS_E1x(sc)) {
11034                 rc = bnx2x_pf_flr_clnup(sc);
11035                 if (rc) {
11036                         PMD_DRV_LOG(NOTICE, "FLR cleanup failed!");
11037                         return rc;
11038                 }
11039         }
11040
11041         /* set MSI reconfigure capability */
11042         if (sc->devinfo.int_block == INT_BLOCK_HC) {
11043                 addr = (port ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0);
11044                 val = REG_RD(sc, addr);
11045                 val |= HC_CONFIG_0_REG_MSI_ATTN_EN_0;
11046                 REG_WR(sc, addr, val);
11047         }
11048
11049         ecore_init_block(sc, BLOCK_PXP, init_phase);
11050         ecore_init_block(sc, BLOCK_PXP2, init_phase);
11051
11052         ilt = sc->ilt;
11053         cdu_ilt_start = ilt->clients[ILT_CLIENT_CDU].start;
11054
11055         for (i = 0; i < L2_ILT_LINES(sc); i++) {
11056                 ilt->lines[cdu_ilt_start + i].page = sc->context[i].vcxt;
11057                 ilt->lines[cdu_ilt_start + i].page_mapping =
11058                     (rte_iova_t)sc->context[i].vcxt_dma.paddr;
11059                 ilt->lines[cdu_ilt_start + i].size = sc->context[i].size;
11060         }
11061         ecore_ilt_init_op(sc, INITOP_SET);
11062
11063         REG_WR(sc, PRS_REG_NIC_MODE, 1);
11064
11065         if (!CHIP_IS_E1x(sc)) {
11066                 uint32_t pf_conf = IGU_PF_CONF_FUNC_EN;
11067
11068 /* Turn on a single ISR mode in IGU if driver is going to use
11069  * INT#x or MSI
11070  */
11071                 if ((sc->interrupt_mode != INTR_MODE_MSIX)
11072                     || (sc->interrupt_mode != INTR_MODE_SINGLE_MSIX)) {
11073                         pf_conf |= IGU_PF_CONF_SINGLE_ISR_EN;
11074                 }
11075
11076 /*
11077  * Timers workaround bug: function init part.
11078  * Need to wait 20msec after initializing ILT,
11079  * needed to make sure there are no requests in
11080  * one of the PXP internal queues with "old" ILT addresses
11081  */
11082                 DELAY(20000);
11083
11084 /*
11085  * Master enable - Due to WB DMAE writes performed before this
11086  * register is re-initialized as part of the regular function
11087  * init
11088  */
11089                 REG_WR(sc, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 1);
11090 /* Enable the function in IGU */
11091                 REG_WR(sc, IGU_REG_PF_CONFIGURATION, pf_conf);
11092         }
11093
11094         sc->dmae_ready = 1;
11095
11096         ecore_init_block(sc, BLOCK_PGLUE_B, init_phase);
11097
11098         if (!CHIP_IS_E1x(sc))
11099                 REG_WR(sc, PGLUE_B_REG_WAS_ERROR_PF_7_0_CLR, func);
11100
11101         ecore_init_block(sc, BLOCK_ATC, init_phase);
11102         ecore_init_block(sc, BLOCK_DMAE, init_phase);
11103         ecore_init_block(sc, BLOCK_NIG, init_phase);
11104         ecore_init_block(sc, BLOCK_SRC, init_phase);
11105         ecore_init_block(sc, BLOCK_MISC, init_phase);
11106         ecore_init_block(sc, BLOCK_TCM, init_phase);
11107         ecore_init_block(sc, BLOCK_UCM, init_phase);
11108         ecore_init_block(sc, BLOCK_CCM, init_phase);
11109         ecore_init_block(sc, BLOCK_XCM, init_phase);
11110         ecore_init_block(sc, BLOCK_TSEM, init_phase);
11111         ecore_init_block(sc, BLOCK_USEM, init_phase);
11112         ecore_init_block(sc, BLOCK_CSEM, init_phase);
11113         ecore_init_block(sc, BLOCK_XSEM, init_phase);
11114
11115         if (!CHIP_IS_E1x(sc))
11116                 REG_WR(sc, QM_REG_PF_EN, 1);
11117
11118         if (!CHIP_IS_E1x(sc)) {
11119                 REG_WR(sc, TSEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func);
11120                 REG_WR(sc, USEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func);
11121                 REG_WR(sc, CSEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func);
11122                 REG_WR(sc, XSEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func);
11123         }
11124         ecore_init_block(sc, BLOCK_QM, init_phase);
11125
11126         ecore_init_block(sc, BLOCK_TM, init_phase);
11127         ecore_init_block(sc, BLOCK_DORQ, init_phase);
11128
11129         ecore_init_block(sc, BLOCK_BRB1, init_phase);
11130         ecore_init_block(sc, BLOCK_PRS, init_phase);
11131         ecore_init_block(sc, BLOCK_TSDM, init_phase);
11132         ecore_init_block(sc, BLOCK_CSDM, init_phase);
11133         ecore_init_block(sc, BLOCK_USDM, init_phase);
11134         ecore_init_block(sc, BLOCK_XSDM, init_phase);
11135         ecore_init_block(sc, BLOCK_UPB, init_phase);
11136         ecore_init_block(sc, BLOCK_XPB, init_phase);
11137         ecore_init_block(sc, BLOCK_PBF, init_phase);
11138         if (!CHIP_IS_E1x(sc))
11139                 REG_WR(sc, PBF_REG_DISABLE_PF, 0);
11140
11141         ecore_init_block(sc, BLOCK_CDU, init_phase);
11142
11143         ecore_init_block(sc, BLOCK_CFC, init_phase);
11144
11145         if (!CHIP_IS_E1x(sc))
11146                 REG_WR(sc, CFC_REG_WEAK_ENABLE_PF, 1);
11147
11148         if (IS_MF(sc)) {
11149                 REG_WR(sc, NIG_REG_LLH0_FUNC_EN + port * 8, 1);
11150                 REG_WR(sc, NIG_REG_LLH0_FUNC_VLAN_ID + port * 8, OVLAN(sc));
11151         }
11152
11153         ecore_init_block(sc, BLOCK_MISC_AEU, init_phase);
11154
11155         /* HC init per function */
11156         if (sc->devinfo.int_block == INT_BLOCK_HC) {
11157                 if (CHIP_IS_E1H(sc)) {
11158                         REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_12 + func * 4, 0);
11159
11160                         REG_WR(sc, HC_REG_LEADING_EDGE_0 + port * 8, 0);
11161                         REG_WR(sc, HC_REG_TRAILING_EDGE_0 + port * 8, 0);
11162                 }
11163                 ecore_init_block(sc, BLOCK_HC, init_phase);
11164
11165         } else {
11166                 uint32_t num_segs, sb_idx, prod_offset;
11167
11168                 REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_12 + func * 4, 0);
11169
11170                 if (!CHIP_IS_E1x(sc)) {
11171                         REG_WR(sc, IGU_REG_LEADING_EDGE_LATCH, 0);
11172                         REG_WR(sc, IGU_REG_TRAILING_EDGE_LATCH, 0);
11173                 }
11174
11175                 ecore_init_block(sc, BLOCK_IGU, init_phase);
11176
11177                 if (!CHIP_IS_E1x(sc)) {
11178                         int dsb_idx = 0;
11179         /**
11180          * Producer memory:
11181          * E2 mode: address 0-135 match to the mapping memory;
11182          * 136 - PF0 default prod; 137 - PF1 default prod;
11183          * 138 - PF2 default prod; 139 - PF3 default prod;
11184          * 140 - PF0 attn prod;    141 - PF1 attn prod;
11185          * 142 - PF2 attn prod;    143 - PF3 attn prod;
11186          * 144-147 reserved.
11187          *
11188          * E1.5 mode - In backward compatible mode;
11189          * for non default SB; each even line in the memory
11190          * holds the U producer and each odd line hold
11191          * the C producer. The first 128 producers are for
11192          * NDSB (PF0 - 0-31; PF1 - 32-63 and so on). The last 20
11193          * producers are for the DSB for each PF.
11194          * Each PF has five segments: (the order inside each
11195          * segment is PF0; PF1; PF2; PF3) - 128-131 U prods;
11196          * 132-135 C prods; 136-139 X prods; 140-143 T prods;
11197          * 144-147 attn prods;
11198          */
11199                         /* non-default-status-blocks */
11200                         num_segs = CHIP_INT_MODE_IS_BC(sc) ?
11201                             IGU_BC_NDSB_NUM_SEGS : IGU_NORM_NDSB_NUM_SEGS;
11202                         for (sb_idx = 0; sb_idx < sc->igu_sb_cnt; sb_idx++) {
11203                                 prod_offset = (sc->igu_base_sb + sb_idx) *
11204                                     num_segs;
11205
11206                                 for (i = 0; i < num_segs; i++) {
11207                                         addr = IGU_REG_PROD_CONS_MEMORY +
11208                                             (prod_offset + i) * 4;
11209                                         REG_WR(sc, addr, 0);
11210                                 }
11211                                 /* send consumer update with value 0 */
11212                                 bnx2x_ack_sb(sc, sc->igu_base_sb + sb_idx,
11213                                            USTORM_ID, 0, IGU_INT_NOP, 1);
11214                                 bnx2x_igu_clear_sb(sc, sc->igu_base_sb + sb_idx);
11215                         }
11216
11217                         /* default-status-blocks */
11218                         num_segs = CHIP_INT_MODE_IS_BC(sc) ?
11219                             IGU_BC_DSB_NUM_SEGS : IGU_NORM_DSB_NUM_SEGS;
11220
11221                         if (CHIP_IS_MODE_4_PORT(sc))
11222                                 dsb_idx = SC_FUNC(sc);
11223                         else
11224                                 dsb_idx = SC_VN(sc);
11225
11226                         prod_offset = (CHIP_INT_MODE_IS_BC(sc) ?
11227                                        IGU_BC_BASE_DSB_PROD + dsb_idx :
11228                                        IGU_NORM_BASE_DSB_PROD + dsb_idx);
11229
11230                         /*
11231                          * igu prods come in chunks of E1HVN_MAX (4) -
11232                          * does not matters what is the current chip mode
11233                          */
11234                         for (i = 0; i < (num_segs * E1HVN_MAX); i += E1HVN_MAX) {
11235                                 addr = IGU_REG_PROD_CONS_MEMORY +
11236                                     (prod_offset + i) * 4;
11237                                 REG_WR(sc, addr, 0);
11238                         }
11239                         /* send consumer update with 0 */
11240                         if (CHIP_INT_MODE_IS_BC(sc)) {
11241                                 bnx2x_ack_sb(sc, sc->igu_dsb_id,
11242                                            USTORM_ID, 0, IGU_INT_NOP, 1);
11243                                 bnx2x_ack_sb(sc, sc->igu_dsb_id,
11244                                            CSTORM_ID, 0, IGU_INT_NOP, 1);
11245                                 bnx2x_ack_sb(sc, sc->igu_dsb_id,
11246                                            XSTORM_ID, 0, IGU_INT_NOP, 1);
11247                                 bnx2x_ack_sb(sc, sc->igu_dsb_id,
11248                                            TSTORM_ID, 0, IGU_INT_NOP, 1);
11249                                 bnx2x_ack_sb(sc, sc->igu_dsb_id,
11250                                            ATTENTION_ID, 0, IGU_INT_NOP, 1);
11251                         } else {
11252                                 bnx2x_ack_sb(sc, sc->igu_dsb_id,
11253                                            USTORM_ID, 0, IGU_INT_NOP, 1);
11254                                 bnx2x_ack_sb(sc, sc->igu_dsb_id,
11255                                            ATTENTION_ID, 0, IGU_INT_NOP, 1);
11256                         }
11257                         bnx2x_igu_clear_sb(sc, sc->igu_dsb_id);
11258
11259                         /* !!! these should become driver const once
11260                            rf-tool supports split-68 const */
11261                         REG_WR(sc, IGU_REG_SB_INT_BEFORE_MASK_LSB, 0);
11262                         REG_WR(sc, IGU_REG_SB_INT_BEFORE_MASK_MSB, 0);
11263                         REG_WR(sc, IGU_REG_SB_MASK_LSB, 0);
11264                         REG_WR(sc, IGU_REG_SB_MASK_MSB, 0);
11265                         REG_WR(sc, IGU_REG_PBA_STATUS_LSB, 0);
11266                         REG_WR(sc, IGU_REG_PBA_STATUS_MSB, 0);
11267                 }
11268         }
11269
11270         /* Reset PCIE errors for debug */
11271         REG_WR(sc, 0x2114, 0xffffffff);
11272         REG_WR(sc, 0x2120, 0xffffffff);
11273
11274         if (CHIP_IS_E1x(sc)) {
11275                 main_mem_size = HC_REG_MAIN_MEMORY_SIZE / 2;    /*dwords */
11276                 main_mem_base = HC_REG_MAIN_MEMORY +
11277                     SC_PORT(sc) * (main_mem_size * 4);
11278                 main_mem_prty_clr = HC_REG_HC_PRTY_STS_CLR;
11279                 main_mem_width = 8;
11280
11281                 val = REG_RD(sc, main_mem_prty_clr);
11282                 if (val) {
11283                         PMD_DRV_LOG(DEBUG,
11284                                     "Parity errors in HC block during function init (0x%x)!",
11285                                     val);
11286                 }
11287
11288 /* Clear "false" parity errors in MSI-X table */
11289                 for (i = main_mem_base;
11290                      i < main_mem_base + main_mem_size * 4;
11291                      i += main_mem_width) {
11292                         bnx2x_read_dmae(sc, i, main_mem_width / 4);
11293                         bnx2x_write_dmae(sc, BNX2X_SP_MAPPING(sc, wb_data),
11294                                        i, main_mem_width / 4);
11295                 }
11296 /* Clear HC parity attention */
11297                 REG_RD(sc, main_mem_prty_clr);
11298         }
11299
11300         /* Enable STORMs SP logging */
11301         REG_WR8(sc, BAR_USTRORM_INTMEM +
11302                 USTORM_RECORD_SLOW_PATH_OFFSET(SC_FUNC(sc)), 1);
11303         REG_WR8(sc, BAR_TSTRORM_INTMEM +
11304                 TSTORM_RECORD_SLOW_PATH_OFFSET(SC_FUNC(sc)), 1);
11305         REG_WR8(sc, BAR_CSTRORM_INTMEM +
11306                 CSTORM_RECORD_SLOW_PATH_OFFSET(SC_FUNC(sc)), 1);
11307         REG_WR8(sc, BAR_XSTRORM_INTMEM +
11308                 XSTORM_RECORD_SLOW_PATH_OFFSET(SC_FUNC(sc)), 1);
11309
11310         elink_phy_probe(&sc->link_params);
11311
11312         return 0;
11313 }
11314
11315 static void bnx2x_link_reset(struct bnx2x_softc *sc)
11316 {
11317         if (!BNX2X_NOMCP(sc)) {
11318                 elink_lfa_reset(&sc->link_params, &sc->link_vars);
11319         } else {
11320                 if (!CHIP_REV_IS_SLOW(sc)) {
11321                         PMD_DRV_LOG(WARNING,
11322                                     "Bootcode is missing - cannot reset link");
11323                 }
11324         }
11325 }
11326
11327 static void bnx2x_reset_port(struct bnx2x_softc *sc)
11328 {
11329         int port = SC_PORT(sc);
11330         uint32_t val;
11331
11332         /* reset physical Link */
11333         bnx2x_link_reset(sc);
11334
11335         REG_WR(sc, NIG_REG_MASK_INTERRUPT_PORT0 + port * 4, 0);
11336
11337         /* Do not rcv packets to BRB */
11338         REG_WR(sc, NIG_REG_LLH0_BRB1_DRV_MASK + port * 4, 0x0);
11339         /* Do not direct rcv packets that are not for MCP to the BRB */
11340         REG_WR(sc, (port ? NIG_REG_LLH1_BRB1_NOT_MCP :
11341                     NIG_REG_LLH0_BRB1_NOT_MCP), 0x0);
11342
11343         /* Configure AEU */
11344         REG_WR(sc, MISC_REG_AEU_MASK_ATTN_FUNC_0 + port * 4, 0);
11345
11346         DELAY(100000);
11347
11348         /* Check for BRB port occupancy */
11349         val = REG_RD(sc, BRB1_REG_PORT_NUM_OCC_BLOCKS_0 + port * 4);
11350         if (val) {
11351                 PMD_DRV_LOG(DEBUG,
11352                             "BRB1 is not empty, %d blocks are occupied", val);
11353         }
11354 }
11355
11356 static void bnx2x_ilt_wr(struct bnx2x_softc *sc, uint32_t index, rte_iova_t addr)
11357 {
11358         int reg;
11359         uint32_t wb_write[2];
11360
11361         reg = PXP2_REG_RQ_ONCHIP_AT_B0 + index * 8;
11362
11363         wb_write[0] = ONCHIP_ADDR1(addr);
11364         wb_write[1] = ONCHIP_ADDR2(addr);
11365         REG_WR_DMAE(sc, reg, wb_write, 2);
11366 }
11367
11368 static void bnx2x_clear_func_ilt(struct bnx2x_softc *sc, uint32_t func)
11369 {
11370         uint32_t i, base = FUNC_ILT_BASE(func);
11371         for (i = base; i < base + ILT_PER_FUNC; i++) {
11372                 bnx2x_ilt_wr(sc, i, 0);
11373         }
11374 }
11375
11376 static void bnx2x_reset_func(struct bnx2x_softc *sc)
11377 {
11378         struct bnx2x_fastpath *fp;
11379         int port = SC_PORT(sc);
11380         int func = SC_FUNC(sc);
11381         int i;
11382
11383         /* Disable the function in the FW */
11384         REG_WR8(sc, BAR_XSTRORM_INTMEM + XSTORM_FUNC_EN_OFFSET(func), 0);
11385         REG_WR8(sc, BAR_CSTRORM_INTMEM + CSTORM_FUNC_EN_OFFSET(func), 0);
11386         REG_WR8(sc, BAR_TSTRORM_INTMEM + TSTORM_FUNC_EN_OFFSET(func), 0);
11387         REG_WR8(sc, BAR_USTRORM_INTMEM + USTORM_FUNC_EN_OFFSET(func), 0);
11388
11389         /* FP SBs */
11390         FOR_EACH_ETH_QUEUE(sc, i) {
11391                 fp = &sc->fp[i];
11392                 REG_WR8(sc, BAR_CSTRORM_INTMEM +
11393                         CSTORM_STATUS_BLOCK_DATA_STATE_OFFSET(fp->fw_sb_id),
11394                         SB_DISABLED);
11395         }
11396
11397         /* SP SB */
11398         REG_WR8(sc, BAR_CSTRORM_INTMEM +
11399                 CSTORM_SP_STATUS_BLOCK_DATA_STATE_OFFSET(func), SB_DISABLED);
11400
11401         for (i = 0; i < XSTORM_SPQ_DATA_SIZE / 4; i++) {
11402                 REG_WR(sc, BAR_XSTRORM_INTMEM + XSTORM_SPQ_DATA_OFFSET(func),
11403                        0);
11404         }
11405
11406         /* Configure IGU */
11407         if (sc->devinfo.int_block == INT_BLOCK_HC) {
11408                 REG_WR(sc, HC_REG_LEADING_EDGE_0 + port * 8, 0);
11409                 REG_WR(sc, HC_REG_TRAILING_EDGE_0 + port * 8, 0);
11410         } else {
11411                 REG_WR(sc, IGU_REG_LEADING_EDGE_LATCH, 0);
11412                 REG_WR(sc, IGU_REG_TRAILING_EDGE_LATCH, 0);
11413         }
11414
11415         if (CNIC_LOADED(sc)) {
11416 /* Disable Timer scan */
11417                 REG_WR(sc, TM_REG_EN_LINEAR0_TIMER + port * 4, 0);
11418 /*
11419  * Wait for at least 10ms and up to 2 second for the timers
11420  * scan to complete
11421  */
11422                 for (i = 0; i < 200; i++) {
11423                         DELAY(10000);
11424                         if (!REG_RD(sc, TM_REG_LIN0_SCAN_ON + port * 4))
11425                                 break;
11426                 }
11427         }
11428
11429         /* Clear ILT */
11430         bnx2x_clear_func_ilt(sc, func);
11431
11432         /*
11433          * Timers workaround bug for E2: if this is vnic-3,
11434          * we need to set the entire ilt range for this timers.
11435          */
11436         if (!CHIP_IS_E1x(sc) && SC_VN(sc) == 3) {
11437                 struct ilt_client_info ilt_cli;
11438 /* use dummy TM client */
11439                 memset(&ilt_cli, 0, sizeof(struct ilt_client_info));
11440                 ilt_cli.start = 0;
11441                 ilt_cli.end = ILT_NUM_PAGE_ENTRIES - 1;
11442                 ilt_cli.client_num = ILT_CLIENT_TM;
11443
11444                 ecore_ilt_boundry_init_op(sc, &ilt_cli, 0);
11445         }
11446
11447         /* this assumes that reset_port() called before reset_func() */
11448         if (!CHIP_IS_E1x(sc)) {
11449                 bnx2x_pf_disable(sc);
11450         }
11451
11452         sc->dmae_ready = 0;
11453 }
11454
11455 static void bnx2x_release_firmware(struct bnx2x_softc *sc)
11456 {
11457         rte_free(sc->init_ops);
11458         rte_free(sc->init_ops_offsets);
11459         rte_free(sc->init_data);
11460         rte_free(sc->iro_array);
11461 }
11462
11463 static int bnx2x_init_firmware(struct bnx2x_softc *sc)
11464 {
11465         uint32_t len, i;
11466         uint8_t *p = sc->firmware;
11467         uint32_t off[24];
11468
11469         for (i = 0; i < 24; ++i)
11470                 off[i] = rte_be_to_cpu_32(*((uint32_t *) sc->firmware + i));
11471
11472         len = off[0];
11473         sc->init_ops = rte_zmalloc("", len, RTE_CACHE_LINE_SIZE);
11474         if (!sc->init_ops)
11475                 goto alloc_failed;
11476         bnx2x_data_to_init_ops(p + off[1], sc->init_ops, len);
11477
11478         len = off[2];
11479         sc->init_ops_offsets = rte_zmalloc("", len, RTE_CACHE_LINE_SIZE);
11480         if (!sc->init_ops_offsets)
11481                 goto alloc_failed;
11482         bnx2x_data_to_init_offsets(p + off[3], sc->init_ops_offsets, len);
11483
11484         len = off[4];
11485         sc->init_data = rte_zmalloc("", len, RTE_CACHE_LINE_SIZE);
11486         if (!sc->init_data)
11487                 goto alloc_failed;
11488         bnx2x_data_to_init_data(p + off[5], sc->init_data, len);
11489
11490         sc->tsem_int_table_data = p + off[7];
11491         sc->tsem_pram_data = p + off[9];
11492         sc->usem_int_table_data = p + off[11];
11493         sc->usem_pram_data = p + off[13];
11494         sc->csem_int_table_data = p + off[15];
11495         sc->csem_pram_data = p + off[17];
11496         sc->xsem_int_table_data = p + off[19];
11497         sc->xsem_pram_data = p + off[21];
11498
11499         len = off[22];
11500         sc->iro_array = rte_zmalloc("", len, RTE_CACHE_LINE_SIZE);
11501         if (!sc->iro_array)
11502                 goto alloc_failed;
11503         bnx2x_data_to_iro_array(p + off[23], sc->iro_array, len);
11504
11505         return 0;
11506
11507 alloc_failed:
11508         bnx2x_release_firmware(sc);
11509         return -1;
11510 }
11511
11512 static int cut_gzip_prefix(const uint8_t * zbuf, int len)
11513 {
11514 #define MIN_PREFIX_SIZE (10)
11515
11516         int n = MIN_PREFIX_SIZE;
11517         uint16_t xlen;
11518
11519         if (!(zbuf[0] == 0x1f && zbuf[1] == 0x8b && zbuf[2] == Z_DEFLATED) ||
11520             len <= MIN_PREFIX_SIZE) {
11521                 return -1;
11522         }
11523
11524         /* optional extra fields are present */
11525         if (zbuf[3] & 0x4) {
11526                 xlen = zbuf[13];
11527                 xlen <<= 8;
11528                 xlen += zbuf[12];
11529
11530                 n += xlen;
11531         }
11532         /* file name is present */
11533         if (zbuf[3] & 0x8) {
11534                 while ((zbuf[n++] != 0) && (n < len)) ;
11535         }
11536
11537         return n;
11538 }
11539
11540 static int ecore_gunzip(struct bnx2x_softc *sc, const uint8_t * zbuf, int len)
11541 {
11542         int ret;
11543         int data_begin = cut_gzip_prefix(zbuf, len);
11544
11545         PMD_DRV_LOG(DEBUG, "ecore_gunzip %d", len);
11546
11547         if (data_begin <= 0) {
11548                 PMD_DRV_LOG(NOTICE, "bad gzip prefix");
11549                 return -1;
11550         }
11551
11552         memset(&zlib_stream, 0, sizeof(zlib_stream));
11553         zlib_stream.next_in = zbuf + data_begin;
11554         zlib_stream.avail_in = len - data_begin;
11555         zlib_stream.next_out = sc->gz_buf;
11556         zlib_stream.avail_out = FW_BUF_SIZE;
11557
11558         ret = inflateInit2(&zlib_stream, -MAX_WBITS);
11559         if (ret != Z_OK) {
11560                 PMD_DRV_LOG(NOTICE, "zlib inflateInit2 error");
11561                 return ret;
11562         }
11563
11564         ret = inflate(&zlib_stream, Z_FINISH);
11565         if ((ret != Z_STREAM_END) && (ret != Z_OK)) {
11566                 PMD_DRV_LOG(NOTICE, "zlib inflate error: %d %s", ret,
11567                             zlib_stream.msg);
11568         }
11569
11570         sc->gz_outlen = zlib_stream.total_out;
11571         if (sc->gz_outlen & 0x3) {
11572                 PMD_DRV_LOG(NOTICE, "firmware is not aligned. gz_outlen == %d",
11573                             sc->gz_outlen);
11574         }
11575         sc->gz_outlen >>= 2;
11576
11577         inflateEnd(&zlib_stream);
11578
11579         if (ret == Z_STREAM_END)
11580                 return 0;
11581
11582         return ret;
11583 }
11584
11585 static void
11586 ecore_write_dmae_phys_len(struct bnx2x_softc *sc, rte_iova_t phys_addr,
11587                           uint32_t addr, uint32_t len)
11588 {
11589         bnx2x_write_dmae_phys_len(sc, phys_addr, addr, len);
11590 }
11591
11592 void
11593 ecore_storm_memset_struct(struct bnx2x_softc *sc, uint32_t addr, size_t size,
11594                           uint32_t * data)
11595 {
11596         uint8_t i;
11597         for (i = 0; i < size / 4; i++) {
11598                 REG_WR(sc, addr + (i * 4), data[i]);
11599         }
11600 }
11601
11602 static const char *get_ext_phy_type(uint32_t ext_phy_type)
11603 {
11604         uint32_t phy_type_idx = ext_phy_type >> 8;
11605         static const char *types[] =
11606             { "DIRECT", "BNX2X-8071", "BNX2X-8072", "BNX2X-8073",
11607                 "BNX2X-8705", "BNX2X-8706", "BNX2X-8726", "BNX2X-8481", "SFX-7101",
11608                 "BNX2X-8727",
11609                 "BNX2X-8727-NOC", "BNX2X-84823", "NOT_CONN", "FAILURE"
11610         };
11611
11612         if (phy_type_idx < 12)
11613                 return types[phy_type_idx];
11614         else if (PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN == ext_phy_type)
11615                 return types[12];
11616         else
11617                 return types[13];
11618 }
11619
11620 static const char *get_state(uint32_t state)
11621 {
11622         uint32_t state_idx = state >> 12;
11623         static const char *states[] = { "CLOSED", "OPENING_WAIT4_LOAD",
11624                 "OPENING_WAIT4_PORT", "OPEN", "CLOSING_WAIT4_HALT",
11625                 "CLOSING_WAIT4_DELETE", "CLOSING_WAIT4_UNLOAD",
11626                 "UNKNOWN", "UNKNOWN", "UNKNOWN", "UNKNOWN", "UNKNOWN",
11627                 "UNKNOWN", "DISABLED", "DIAG", "ERROR", "UNDEFINED"
11628         };
11629
11630         if (state_idx <= 0xF)
11631                 return states[state_idx];
11632         else
11633                 return states[0x10];
11634 }
11635
11636 static const char *get_recovery_state(uint32_t state)
11637 {
11638         static const char *states[] = { "NONE", "DONE", "INIT",
11639                 "WAIT", "FAILED", "NIC_LOADING"
11640         };
11641         return states[state];
11642 }
11643
11644 static const char *get_rx_mode(uint32_t mode)
11645 {
11646         static const char *modes[] = { "NONE", "NORMAL", "ALLMULTI",
11647                 "PROMISC", "MAX_MULTICAST", "ERROR"
11648         };
11649
11650         if (mode < 0x4)
11651                 return modes[mode];
11652         else if (BNX2X_MAX_MULTICAST == mode)
11653                 return modes[4];
11654         else
11655                 return modes[5];
11656 }
11657
11658 #define BNX2X_INFO_STR_MAX 256
11659 static const char *get_bnx2x_flags(uint32_t flags)
11660 {
11661         int i;
11662         static const char *flag[] = { "ONE_PORT ", "NO_ISCSI ",
11663                 "NO_FCOE ", "NO_WOL ", "USING_DAC ", "USING_MSIX ",
11664                 "USING_MSI ", "DISABLE_MSI ", "UNKNOWN ", "NO_MCP ",
11665                 "SAFC_TX_FLAG ", "MF_FUNC_DIS ", "TX_SWITCHING "
11666         };
11667         static char flag_str[BNX2X_INFO_STR_MAX];
11668         memset(flag_str, 0, BNX2X_INFO_STR_MAX);
11669
11670         for (i = 0; i < 5; i++)
11671                 if (flags & (1 << i)) {
11672                         strcat(flag_str, flag[i]);
11673                         flags ^= (1 << i);
11674                 }
11675         if (flags) {
11676                 static char unknown[BNX2X_INFO_STR_MAX];
11677                 snprintf(unknown, 32, "Unknown flag mask %x", flags);
11678                 strcat(flag_str, unknown);
11679         }
11680         return flag_str;
11681 }
11682
11683 /*
11684  * Prints useful adapter info.
11685  */
11686 void bnx2x_print_adapter_info(struct bnx2x_softc *sc)
11687 {
11688         int i = 0;
11689         __rte_unused uint32_t ext_phy_type;
11690
11691         PMD_INIT_FUNC_TRACE();
11692         if (sc->link_vars.phy_flags & PHY_XGXS_FLAG)
11693                 ext_phy_type = ELINK_XGXS_EXT_PHY_TYPE(REG_RD(sc,
11694                                                               sc->
11695                                                               devinfo.shmem_base
11696                                                               + offsetof(struct
11697                                                                          shmem_region,
11698                                                                          dev_info.port_hw_config
11699                                                                          [0].external_phy_config)));
11700         else
11701                 ext_phy_type = ELINK_SERDES_EXT_PHY_TYPE(REG_RD(sc,
11702                                                                 sc->
11703                                                                 devinfo.shmem_base
11704                                                                 +
11705                                                                 offsetof(struct
11706                                                                          shmem_region,
11707                                                                          dev_info.port_hw_config
11708                                                                          [0].external_phy_config)));
11709
11710         PMD_INIT_LOG(DEBUG, "\n\n===================================\n");
11711         /* Hardware chip info. */
11712         PMD_INIT_LOG(DEBUG, "%12s : %#08x", "ASIC", sc->devinfo.chip_id);
11713         PMD_INIT_LOG(DEBUG, "%12s : %c%d", "Rev", (CHIP_REV(sc) >> 12) + 'A',
11714                      (CHIP_METAL(sc) >> 4));
11715
11716         /* Bus info. */
11717         PMD_INIT_LOG(DEBUG, "%12s : %d, ", "Bus PCIe", sc->devinfo.pcie_link_width);
11718         switch (sc->devinfo.pcie_link_speed) {
11719         case 1:
11720                 PMD_INIT_LOG(DEBUG, "%23s", "2.5 Gbps");
11721                 break;
11722         case 2:
11723                 PMD_INIT_LOG(DEBUG, "%21s", "5 Gbps");
11724                 break;
11725         case 4:
11726                 PMD_INIT_LOG(DEBUG, "%21s", "8 Gbps");
11727                 break;
11728         default:
11729                 PMD_INIT_LOG(DEBUG, "%33s", "Unknown link speed");
11730         }
11731
11732         /* Device features. */
11733         PMD_INIT_LOG(DEBUG, "%12s : ", "Flags");
11734
11735         /* Miscellaneous flags. */
11736         if (sc->devinfo.pcie_cap_flags & BNX2X_MSI_CAPABLE_FLAG) {
11737                 PMD_INIT_LOG(DEBUG, "%18s", "MSI");
11738                 i++;
11739         }
11740
11741         if (sc->devinfo.pcie_cap_flags & BNX2X_MSIX_CAPABLE_FLAG) {
11742                 if (i > 0)
11743                         PMD_INIT_LOG(DEBUG, "|");
11744                 PMD_INIT_LOG(DEBUG, "%20s", "MSI-X");
11745                 i++;
11746         }
11747
11748         if (IS_PF(sc)) {
11749                 PMD_INIT_LOG(DEBUG, "%12s : ", "Queues");
11750                 switch (sc->sp->rss_rdata.rss_mode) {
11751                 case ETH_RSS_MODE_DISABLED:
11752                         PMD_INIT_LOG(DEBUG, "%19s", "None");
11753                         break;
11754                 case ETH_RSS_MODE_REGULAR:
11755                         PMD_INIT_LOG(DEBUG, "%18s : %d", "RSS", sc->num_queues);
11756                         break;
11757                 default:
11758                         PMD_INIT_LOG(DEBUG, "%22s", "Unknown");
11759                         break;
11760                 }
11761         }
11762
11763         /* RTE and Driver versions */
11764         PMD_INIT_LOG(DEBUG, "%12s : %s", "DPDK",
11765                      rte_version());
11766         PMD_INIT_LOG(DEBUG, "%12s : %s", "Driver",
11767                      bnx2x_pmd_version());
11768
11769         /* Firmware versions and device features. */
11770         PMD_INIT_LOG(DEBUG, "%12s : %d.%d.%d",
11771                      "Firmware",
11772                      BNX2X_5710_FW_MAJOR_VERSION,
11773                      BNX2X_5710_FW_MINOR_VERSION,
11774                      BNX2X_5710_FW_REVISION_VERSION);
11775         PMD_INIT_LOG(DEBUG, "%12s : %s",
11776                      "Bootcode", sc->devinfo.bc_ver_str);
11777
11778         PMD_INIT_LOG(DEBUG, "\n\n===================================\n");
11779         PMD_INIT_LOG(DEBUG, "%12s : %u", "Bnx2x Func", sc->pcie_func);
11780         PMD_INIT_LOG(DEBUG, "%12s : %s", "Bnx2x Flags", get_bnx2x_flags(sc->flags));
11781         PMD_INIT_LOG(DEBUG, "%12s : %s", "DMAE Is",
11782                      (sc->dmae_ready ? "Ready" : "Not Ready"));
11783         PMD_INIT_LOG(DEBUG, "%12s : %s", "OVLAN", (OVLAN(sc) ? "YES" : "NO"));
11784         PMD_INIT_LOG(DEBUG, "%12s : %s", "MF", (IS_MF(sc) ? "YES" : "NO"));
11785         PMD_INIT_LOG(DEBUG, "%12s : %u", "MTU", sc->mtu);
11786         PMD_INIT_LOG(DEBUG, "%12s : %s", "PHY Type", get_ext_phy_type(ext_phy_type));
11787         PMD_INIT_LOG(DEBUG, "%12s : %x:%x:%x:%x:%x:%x", "MAC Addr",
11788                         sc->link_params.mac_addr[0],
11789                         sc->link_params.mac_addr[1],
11790                         sc->link_params.mac_addr[2],
11791                         sc->link_params.mac_addr[3],
11792                         sc->link_params.mac_addr[4],
11793                         sc->link_params.mac_addr[5]);
11794         PMD_INIT_LOG(DEBUG, "%12s : %s", "RX Mode", get_rx_mode(sc->rx_mode));
11795         PMD_INIT_LOG(DEBUG, "%12s : %s", "State", get_state(sc->state));
11796         if (sc->recovery_state)
11797                 PMD_INIT_LOG(DEBUG, "%12s : %s", "Recovery",
11798                              get_recovery_state(sc->recovery_state));
11799         PMD_INIT_LOG(DEBUG, "%12s : CQ = %lx,  EQ = %lx", "SPQ Left",
11800                      sc->cq_spq_left, sc->eq_spq_left);
11801         PMD_INIT_LOG(DEBUG, "%12s : %x", "Switch", sc->link_params.switch_cfg);
11802         PMD_INIT_LOG(DEBUG, "\n\n===================================\n");
11803 }