2 * Copyright (c) 2007-2013 Broadcom Corporation.
4 * Eric Davis <edavis@broadcom.com>
5 * David Christensen <davidch@broadcom.com>
6 * Gary Zambrano <zambrano@broadcom.com>
8 * Copyright (c) 2013-2015 Brocade Communications Systems, Inc.
9 * Copyright (c) 2015 QLogic Corporation.
10 * All rights reserved.
13 * See LICENSE.bnx2x_pmd for copyright and licensing details.
16 #define BNX2X_DRIVER_VERSION "1.78.18"
19 #include "bnx2x_vfpf.h"
21 #include "ecore_init.h"
22 #include "ecore_init_ops.h"
24 #include "rte_version.h"
26 #include <sys/types.h>
31 #define BNX2X_PMD_VER_PREFIX "BNX2X PMD"
32 #define BNX2X_PMD_VERSION_MAJOR 1
33 #define BNX2X_PMD_VERSION_MINOR 0
34 #define BNX2X_PMD_VERSION_REVISION 5
35 #define BNX2X_PMD_VERSION_PATCH 1
37 static inline const char *
38 bnx2x_pmd_version(void)
40 static char version[32];
42 snprintf(version, sizeof(version), "%s %s_%d.%d.%d.%d",
45 BNX2X_PMD_VERSION_MAJOR,
46 BNX2X_PMD_VERSION_MINOR,
47 BNX2X_PMD_VERSION_REVISION,
48 BNX2X_PMD_VERSION_PATCH);
53 static z_stream zlib_stream;
55 #define EVL_VLID_MASK 0x0FFF
57 #define BNX2X_DEF_SB_ATT_IDX 0x0001
58 #define BNX2X_DEF_SB_IDX 0x0002
61 * FLR Support - bnx2x_pf_flr_clnup() is called during nic_load in the per
62 * function HW initialization.
64 #define FLR_WAIT_USEC 10000 /* 10 msecs */
65 #define FLR_WAIT_INTERVAL 50 /* usecs */
66 #define FLR_POLL_CNT (FLR_WAIT_USEC / FLR_WAIT_INTERVAL) /* 200 */
68 struct pbf_pN_buf_regs {
75 struct pbf_pN_cmd_regs {
81 /* resources needed for unloading a previously loaded device */
83 #define BNX2X_PREV_WAIT_NEEDED 1
84 rte_spinlock_t bnx2x_prev_mtx;
85 struct bnx2x_prev_list_node {
86 LIST_ENTRY(bnx2x_prev_list_node) node;
94 static LIST_HEAD(, bnx2x_prev_list_node) bnx2x_prev_list
95 = LIST_HEAD_INITIALIZER(bnx2x_prev_list);
97 static int load_count[2][3] = { { 0 } };
98 /* per-path: 0-common, 1-port0, 2-port1 */
100 static void bnx2x_cmng_fns_init(struct bnx2x_softc *sc, uint8_t read_cfg,
102 static int bnx2x_get_cmng_fns_mode(struct bnx2x_softc *sc);
103 static void storm_memset_cmng(struct bnx2x_softc *sc, struct cmng_init *cmng,
105 static void bnx2x_set_reset_global(struct bnx2x_softc *sc);
106 static void bnx2x_set_reset_in_progress(struct bnx2x_softc *sc);
107 static uint8_t bnx2x_reset_is_done(struct bnx2x_softc *sc, int engine);
108 static uint8_t bnx2x_clear_pf_load(struct bnx2x_softc *sc);
109 static uint8_t bnx2x_chk_parity_attn(struct bnx2x_softc *sc, uint8_t * global,
111 static void bnx2x_int_disable(struct bnx2x_softc *sc);
112 static int bnx2x_release_leader_lock(struct bnx2x_softc *sc);
113 static void bnx2x_pf_disable(struct bnx2x_softc *sc);
114 static void bnx2x_update_rx_prod(struct bnx2x_softc *sc,
115 struct bnx2x_fastpath *fp,
116 uint16_t rx_bd_prod, uint16_t rx_cq_prod);
117 static void bnx2x_link_report(struct bnx2x_softc *sc);
118 void bnx2x_link_status_update(struct bnx2x_softc *sc);
119 static int bnx2x_alloc_mem(struct bnx2x_softc *sc);
120 static void bnx2x_free_mem(struct bnx2x_softc *sc);
121 static int bnx2x_alloc_fw_stats_mem(struct bnx2x_softc *sc);
122 static void bnx2x_free_fw_stats_mem(struct bnx2x_softc *sc);
123 static __rte_noinline
124 int bnx2x_nic_load(struct bnx2x_softc *sc);
126 static int bnx2x_handle_sp_tq(struct bnx2x_softc *sc);
127 static void bnx2x_handle_fp_tq(struct bnx2x_fastpath *fp, int scan_fp);
128 static void bnx2x_periodic_stop(struct bnx2x_softc *sc);
129 static void bnx2x_ack_sb(struct bnx2x_softc *sc, uint8_t igu_sb_id,
130 uint8_t storm, uint16_t index, uint8_t op,
133 int bnx2x_test_bit(int nr, volatile unsigned long *addr)
138 res = ((*addr) & (1UL << nr)) != 0;
143 void bnx2x_set_bit(unsigned int nr, volatile unsigned long *addr)
145 __sync_fetch_and_or(addr, (1UL << nr));
148 void bnx2x_clear_bit(int nr, volatile unsigned long *addr)
150 __sync_fetch_and_and(addr, ~(1UL << nr));
153 int bnx2x_test_and_clear_bit(int nr, volatile unsigned long *addr)
155 unsigned long mask = (1UL << nr);
156 return __sync_fetch_and_and(addr, ~mask) & mask;
159 int bnx2x_cmpxchg(volatile int *addr, int old, int new)
161 return __sync_val_compare_and_swap(addr, old, new);
165 bnx2x_dma_alloc(struct bnx2x_softc *sc, size_t size, struct bnx2x_dma *dma,
166 const char *msg, uint32_t align)
168 char mz_name[RTE_MEMZONE_NAMESIZE];
169 const struct rte_memzone *z;
173 sprintf(mz_name, "bnx2x%d_%s_%" PRIx64, SC_ABS_FUNC(sc), msg,
174 rte_get_timer_cycles());
176 sprintf(mz_name, "bnx2x%d_%s_%" PRIx64, sc->pcie_device, msg,
177 rte_get_timer_cycles());
179 /* Caller must take care that strlen(mz_name) < RTE_MEMZONE_NAMESIZE */
180 z = rte_memzone_reserve_aligned(mz_name, (uint64_t) (size),
184 PMD_DRV_LOG(ERR, "DMA alloc failed for %s", msg);
187 dma->paddr = (uint64_t) z->iova;
188 dma->vaddr = z->addr;
190 PMD_DRV_LOG(DEBUG, "%s: virt=%p phys=%" PRIx64, msg, dma->vaddr, dma->paddr);
195 static int bnx2x_acquire_hw_lock(struct bnx2x_softc *sc, uint32_t resource)
197 uint32_t lock_status;
198 uint32_t resource_bit = (1 << resource);
199 int func = SC_FUNC(sc);
200 uint32_t hw_lock_control_reg;
203 PMD_INIT_FUNC_TRACE();
205 /* validate the resource is within range */
206 if (resource > HW_LOCK_MAX_RESOURCE_VALUE) {
208 "resource 0x%x > HW_LOCK_MAX_RESOURCE_VALUE",
214 hw_lock_control_reg = (MISC_REG_DRIVER_CONTROL_1 + (func * 8));
216 hw_lock_control_reg =
217 (MISC_REG_DRIVER_CONTROL_7 + ((func - 6) * 8));
220 /* validate the resource is not already taken */
221 lock_status = REG_RD(sc, hw_lock_control_reg);
222 if (lock_status & resource_bit) {
224 "resource in use (status 0x%x bit 0x%x)",
225 lock_status, resource_bit);
229 /* try every 5ms for 5 seconds */
230 for (cnt = 0; cnt < 1000; cnt++) {
231 REG_WR(sc, (hw_lock_control_reg + 4), resource_bit);
232 lock_status = REG_RD(sc, hw_lock_control_reg);
233 if (lock_status & resource_bit) {
239 PMD_DRV_LOG(NOTICE, "Resource lock timeout!");
243 static int bnx2x_release_hw_lock(struct bnx2x_softc *sc, uint32_t resource)
245 uint32_t lock_status;
246 uint32_t resource_bit = (1 << resource);
247 int func = SC_FUNC(sc);
248 uint32_t hw_lock_control_reg;
250 PMD_INIT_FUNC_TRACE();
252 /* validate the resource is within range */
253 if (resource > HW_LOCK_MAX_RESOURCE_VALUE) {
255 "resource 0x%x > HW_LOCK_MAX_RESOURCE_VALUE",
261 hw_lock_control_reg = (MISC_REG_DRIVER_CONTROL_1 + (func * 8));
263 hw_lock_control_reg =
264 (MISC_REG_DRIVER_CONTROL_7 + ((func - 6) * 8));
267 /* validate the resource is currently taken */
268 lock_status = REG_RD(sc, hw_lock_control_reg);
269 if (!(lock_status & resource_bit)) {
271 "resource not in use (status 0x%x bit 0x%x)",
272 lock_status, resource_bit);
276 REG_WR(sc, hw_lock_control_reg, resource_bit);
280 /* copy command into DMAE command memory and set DMAE command Go */
281 void bnx2x_post_dmae(struct bnx2x_softc *sc, struct dmae_command *dmae, int idx)
286 cmd_offset = (DMAE_REG_CMD_MEM + (sizeof(struct dmae_command) * idx));
287 for (i = 0; i < ((sizeof(struct dmae_command) / 4)); i++) {
288 REG_WR(sc, (cmd_offset + (i * 4)), *(((uint32_t *) dmae) + i));
291 REG_WR(sc, dmae_reg_go_c[idx], 1);
294 uint32_t bnx2x_dmae_opcode_add_comp(uint32_t opcode, uint8_t comp_type)
296 return opcode | ((comp_type << DMAE_COMMAND_C_DST_SHIFT) |
297 DMAE_COMMAND_C_TYPE_ENABLE);
300 uint32_t bnx2x_dmae_opcode_clr_src_reset(uint32_t opcode)
302 return opcode & ~DMAE_COMMAND_SRC_RESET;
306 bnx2x_dmae_opcode(struct bnx2x_softc * sc, uint8_t src_type, uint8_t dst_type,
307 uint8_t with_comp, uint8_t comp_type)
311 opcode |= ((src_type << DMAE_COMMAND_SRC_SHIFT) |
312 (dst_type << DMAE_COMMAND_DST_SHIFT));
314 opcode |= (DMAE_COMMAND_SRC_RESET | DMAE_COMMAND_DST_RESET);
316 opcode |= (SC_PORT(sc) ? DMAE_CMD_PORT_1 : DMAE_CMD_PORT_0);
318 opcode |= ((SC_VN(sc) << DMAE_COMMAND_E1HVN_SHIFT) |
319 (SC_VN(sc) << DMAE_COMMAND_DST_VN_SHIFT));
321 opcode |= (DMAE_COM_SET_ERR << DMAE_COMMAND_ERR_POLICY_SHIFT);
324 opcode |= DMAE_CMD_ENDIANITY_B_DW_SWAP;
326 opcode |= DMAE_CMD_ENDIANITY_DW_SWAP;
330 opcode = bnx2x_dmae_opcode_add_comp(opcode, comp_type);
337 bnx2x_prep_dmae_with_comp(struct bnx2x_softc *sc, struct dmae_command *dmae,
338 uint8_t src_type, uint8_t dst_type)
340 memset(dmae, 0, sizeof(struct dmae_command));
343 dmae->opcode = bnx2x_dmae_opcode(sc, src_type, dst_type,
344 TRUE, DMAE_COMP_PCI);
346 /* fill in the completion parameters */
347 dmae->comp_addr_lo = U64_LO(BNX2X_SP_MAPPING(sc, wb_comp));
348 dmae->comp_addr_hi = U64_HI(BNX2X_SP_MAPPING(sc, wb_comp));
349 dmae->comp_val = DMAE_COMP_VAL;
352 /* issue a DMAE command over the init channel and wait for completion */
354 bnx2x_issue_dmae_with_comp(struct bnx2x_softc *sc, struct dmae_command *dmae)
356 uint32_t *wb_comp = BNX2X_SP(sc, wb_comp);
357 int timeout = CHIP_REV_IS_SLOW(sc) ? 400000 : 4000;
359 /* reset completion */
362 /* post the command on the channel used for initializations */
363 bnx2x_post_dmae(sc, dmae, INIT_DMAE_C(sc));
365 /* wait for completion */
368 while ((*wb_comp & ~DMAE_PCI_ERR_FLAG) != DMAE_COMP_VAL) {
370 (sc->recovery_state != BNX2X_RECOVERY_DONE &&
371 sc->recovery_state != BNX2X_RECOVERY_NIC_LOADING)) {
372 PMD_DRV_LOG(INFO, "DMAE timeout!");
380 if (*wb_comp & DMAE_PCI_ERR_FLAG) {
381 PMD_DRV_LOG(INFO, "DMAE PCI error!");
382 return DMAE_PCI_ERROR;
388 void bnx2x_read_dmae(struct bnx2x_softc *sc, uint32_t src_addr, uint32_t len32)
390 struct dmae_command dmae;
395 if (!sc->dmae_ready) {
396 data = BNX2X_SP(sc, wb_data[0]);
398 for (i = 0; i < len32; i++) {
399 data[i] = REG_RD(sc, (src_addr + (i * 4)));
405 /* set opcode and fixed command fields */
406 bnx2x_prep_dmae_with_comp(sc, &dmae, DMAE_SRC_GRC, DMAE_DST_PCI);
408 /* fill in addresses and len */
409 dmae.src_addr_lo = (src_addr >> 2); /* GRC addr has dword resolution */
410 dmae.src_addr_hi = 0;
411 dmae.dst_addr_lo = U64_LO(BNX2X_SP_MAPPING(sc, wb_data));
412 dmae.dst_addr_hi = U64_HI(BNX2X_SP_MAPPING(sc, wb_data));
415 /* issue the command and wait for completion */
416 if ((rc = bnx2x_issue_dmae_with_comp(sc, &dmae)) != 0) {
417 rte_panic("DMAE failed (%d)", rc);
422 bnx2x_write_dmae(struct bnx2x_softc *sc, phys_addr_t dma_addr, uint32_t dst_addr,
425 struct dmae_command dmae;
428 if (!sc->dmae_ready) {
429 ecore_init_str_wr(sc, dst_addr, BNX2X_SP(sc, wb_data[0]), len32);
433 /* set opcode and fixed command fields */
434 bnx2x_prep_dmae_with_comp(sc, &dmae, DMAE_SRC_PCI, DMAE_DST_GRC);
436 /* fill in addresses and len */
437 dmae.src_addr_lo = U64_LO(dma_addr);
438 dmae.src_addr_hi = U64_HI(dma_addr);
439 dmae.dst_addr_lo = (dst_addr >> 2); /* GRC addr has dword resolution */
440 dmae.dst_addr_hi = 0;
443 /* issue the command and wait for completion */
444 if ((rc = bnx2x_issue_dmae_with_comp(sc, &dmae)) != 0) {
445 rte_panic("DMAE failed (%d)", rc);
450 bnx2x_write_dmae_phys_len(struct bnx2x_softc *sc, phys_addr_t phys_addr,
451 uint32_t addr, uint32_t len)
453 uint32_t dmae_wr_max = DMAE_LEN32_WR_MAX(sc);
456 while (len > dmae_wr_max) {
457 bnx2x_write_dmae(sc, (phys_addr + offset), /* src DMA address */
458 (addr + offset), /* dst GRC address */
460 offset += (dmae_wr_max * 4);
464 bnx2x_write_dmae(sc, (phys_addr + offset), /* src DMA address */
465 (addr + offset), /* dst GRC address */
470 bnx2x_set_ctx_validation(struct bnx2x_softc *sc, struct eth_context *cxt,
473 /* ustorm cxt validation */
474 cxt->ustorm_ag_context.cdu_usage =
475 CDU_RSRVD_VALUE_TYPE_A(HW_CID(sc, cid),
476 CDU_REGION_NUMBER_UCM_AG,
477 ETH_CONNECTION_TYPE);
478 /* xcontext validation */
479 cxt->xstorm_ag_context.cdu_reserved =
480 CDU_RSRVD_VALUE_TYPE_A(HW_CID(sc, cid),
481 CDU_REGION_NUMBER_XCM_AG,
482 ETH_CONNECTION_TYPE);
486 bnx2x_storm_memset_hc_timeout(struct bnx2x_softc *sc, uint8_t fw_sb_id,
487 uint8_t sb_index, uint8_t ticks)
490 (BAR_CSTRORM_INTMEM +
491 CSTORM_STATUS_BLOCK_DATA_TIMEOUT_OFFSET(fw_sb_id, sb_index));
493 REG_WR8(sc, addr, ticks);
497 bnx2x_storm_memset_hc_disable(struct bnx2x_softc *sc, uint16_t fw_sb_id,
498 uint8_t sb_index, uint8_t disable)
500 uint32_t enable_flag =
501 (disable) ? 0 : (1 << HC_INDEX_DATA_HC_ENABLED_SHIFT);
503 (BAR_CSTRORM_INTMEM +
504 CSTORM_STATUS_BLOCK_DATA_FLAGS_OFFSET(fw_sb_id, sb_index));
508 flags = REG_RD8(sc, addr);
509 flags &= ~HC_INDEX_DATA_HC_ENABLED;
510 flags |= enable_flag;
511 REG_WR8(sc, addr, flags);
515 bnx2x_update_coalesce_sb_index(struct bnx2x_softc *sc, uint8_t fw_sb_id,
516 uint8_t sb_index, uint8_t disable, uint16_t usec)
518 uint8_t ticks = (usec / 4);
520 bnx2x_storm_memset_hc_timeout(sc, fw_sb_id, sb_index, ticks);
522 disable = (disable) ? 1 : ((usec) ? 0 : 1);
523 bnx2x_storm_memset_hc_disable(sc, fw_sb_id, sb_index, disable);
526 uint32_t elink_cb_reg_read(struct bnx2x_softc *sc, uint32_t reg_addr)
528 return REG_RD(sc, reg_addr);
531 void elink_cb_reg_write(struct bnx2x_softc *sc, uint32_t reg_addr, uint32_t val)
533 REG_WR(sc, reg_addr, val);
537 elink_cb_event_log(__rte_unused struct bnx2x_softc *sc,
538 __rte_unused const elink_log_id_t elink_log_id, ...)
540 PMD_DRV_LOG(DEBUG, "ELINK EVENT LOG (%d)", elink_log_id);
543 static int bnx2x_set_spio(struct bnx2x_softc *sc, int spio, uint32_t mode)
547 /* Only 2 SPIOs are configurable */
548 if ((spio != MISC_SPIO_SPIO4) && (spio != MISC_SPIO_SPIO5)) {
549 PMD_DRV_LOG(NOTICE, "Invalid SPIO 0x%x", spio);
553 bnx2x_acquire_hw_lock(sc, HW_LOCK_RESOURCE_SPIO);
555 /* read SPIO and mask except the float bits */
556 spio_reg = (REG_RD(sc, MISC_REG_SPIO) & MISC_SPIO_FLOAT);
559 case MISC_SPIO_OUTPUT_LOW:
560 /* clear FLOAT and set CLR */
561 spio_reg &= ~(spio << MISC_SPIO_FLOAT_POS);
562 spio_reg |= (spio << MISC_SPIO_CLR_POS);
565 case MISC_SPIO_OUTPUT_HIGH:
566 /* clear FLOAT and set SET */
567 spio_reg &= ~(spio << MISC_SPIO_FLOAT_POS);
568 spio_reg |= (spio << MISC_SPIO_SET_POS);
571 case MISC_SPIO_INPUT_HI_Z:
573 spio_reg |= (spio << MISC_SPIO_FLOAT_POS);
580 REG_WR(sc, MISC_REG_SPIO, spio_reg);
581 bnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_SPIO);
586 static int bnx2x_gpio_read(struct bnx2x_softc *sc, int gpio_num, uint8_t port)
588 /* The GPIO should be swapped if swap register is set and active */
589 int gpio_port = ((REG_RD(sc, NIG_REG_PORT_SWAP) &&
590 REG_RD(sc, NIG_REG_STRAP_OVERRIDE)) ^ port);
591 int gpio_shift = gpio_num;
593 gpio_shift += MISC_REGISTERS_GPIO_PORT_SHIFT;
595 uint32_t gpio_mask = (1 << gpio_shift);
598 if (gpio_num > MISC_REGISTERS_GPIO_3) {
599 PMD_DRV_LOG(NOTICE, "Invalid GPIO %d", gpio_num);
603 /* read GPIO value */
604 gpio_reg = REG_RD(sc, MISC_REG_GPIO);
606 /* get the requested pin value */
607 return ((gpio_reg & gpio_mask) == gpio_mask) ? 1 : 0;
611 bnx2x_gpio_write(struct bnx2x_softc *sc, int gpio_num, uint32_t mode, uint8_t port)
613 /* The GPIO should be swapped if swap register is set and active */
614 int gpio_port = ((REG_RD(sc, NIG_REG_PORT_SWAP) &&
615 REG_RD(sc, NIG_REG_STRAP_OVERRIDE)) ^ port);
616 int gpio_shift = gpio_num;
618 gpio_shift += MISC_REGISTERS_GPIO_PORT_SHIFT;
620 uint32_t gpio_mask = (1 << gpio_shift);
623 if (gpio_num > MISC_REGISTERS_GPIO_3) {
624 PMD_DRV_LOG(NOTICE, "Invalid GPIO %d", gpio_num);
628 bnx2x_acquire_hw_lock(sc, HW_LOCK_RESOURCE_GPIO);
630 /* read GPIO and mask except the float bits */
631 gpio_reg = (REG_RD(sc, MISC_REG_GPIO) & MISC_REGISTERS_GPIO_FLOAT);
634 case MISC_REGISTERS_GPIO_OUTPUT_LOW:
635 /* clear FLOAT and set CLR */
636 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS);
637 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_CLR_POS);
640 case MISC_REGISTERS_GPIO_OUTPUT_HIGH:
641 /* clear FLOAT and set SET */
642 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS);
643 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_SET_POS);
646 case MISC_REGISTERS_GPIO_INPUT_HI_Z:
648 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS);
655 REG_WR(sc, MISC_REG_GPIO, gpio_reg);
656 bnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_GPIO);
662 bnx2x_gpio_mult_write(struct bnx2x_softc *sc, uint8_t pins, uint32_t mode)
666 /* any port swapping should be handled by caller */
668 bnx2x_acquire_hw_lock(sc, HW_LOCK_RESOURCE_GPIO);
670 /* read GPIO and mask except the float bits */
671 gpio_reg = REG_RD(sc, MISC_REG_GPIO);
672 gpio_reg &= ~(pins << MISC_REGISTERS_GPIO_FLOAT_POS);
673 gpio_reg &= ~(pins << MISC_REGISTERS_GPIO_CLR_POS);
674 gpio_reg &= ~(pins << MISC_REGISTERS_GPIO_SET_POS);
677 case MISC_REGISTERS_GPIO_OUTPUT_LOW:
679 gpio_reg |= (pins << MISC_REGISTERS_GPIO_CLR_POS);
682 case MISC_REGISTERS_GPIO_OUTPUT_HIGH:
684 gpio_reg |= (pins << MISC_REGISTERS_GPIO_SET_POS);
687 case MISC_REGISTERS_GPIO_INPUT_HI_Z:
689 gpio_reg |= (pins << MISC_REGISTERS_GPIO_FLOAT_POS);
693 PMD_DRV_LOG(NOTICE, "Invalid GPIO mode assignment %d", mode);
694 bnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_GPIO);
698 REG_WR(sc, MISC_REG_GPIO, gpio_reg);
699 bnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_GPIO);
705 bnx2x_gpio_int_write(struct bnx2x_softc *sc, int gpio_num, uint32_t mode,
708 /* The GPIO should be swapped if swap register is set and active */
709 int gpio_port = ((REG_RD(sc, NIG_REG_PORT_SWAP) &&
710 REG_RD(sc, NIG_REG_STRAP_OVERRIDE)) ^ port);
711 int gpio_shift = gpio_num;
713 gpio_shift += MISC_REGISTERS_GPIO_PORT_SHIFT;
715 uint32_t gpio_mask = (1 << gpio_shift);
718 if (gpio_num > MISC_REGISTERS_GPIO_3) {
719 PMD_DRV_LOG(NOTICE, "Invalid GPIO %d", gpio_num);
723 bnx2x_acquire_hw_lock(sc, HW_LOCK_RESOURCE_GPIO);
726 gpio_reg = REG_RD(sc, MISC_REG_GPIO_INT);
729 case MISC_REGISTERS_GPIO_INT_OUTPUT_CLR:
730 /* clear SET and set CLR */
731 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_INT_SET_POS);
732 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_INT_CLR_POS);
735 case MISC_REGISTERS_GPIO_INT_OUTPUT_SET:
736 /* clear CLR and set SET */
737 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_INT_CLR_POS);
738 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_INT_SET_POS);
745 REG_WR(sc, MISC_REG_GPIO_INT, gpio_reg);
746 bnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_GPIO);
752 elink_cb_gpio_read(struct bnx2x_softc * sc, uint16_t gpio_num, uint8_t port)
754 return bnx2x_gpio_read(sc, gpio_num, port);
757 uint8_t elink_cb_gpio_write(struct bnx2x_softc * sc, uint16_t gpio_num, uint8_t mode, /* 0=low 1=high */
760 return bnx2x_gpio_write(sc, gpio_num, mode, port);
764 elink_cb_gpio_mult_write(struct bnx2x_softc * sc, uint8_t pins,
765 uint8_t mode /* 0=low 1=high */ )
767 return bnx2x_gpio_mult_write(sc, pins, mode);
770 uint8_t elink_cb_gpio_int_write(struct bnx2x_softc * sc, uint16_t gpio_num, uint8_t mode, /* 0=low 1=high */
773 return bnx2x_gpio_int_write(sc, gpio_num, mode, port);
776 void elink_cb_notify_link_changed(struct bnx2x_softc *sc)
778 REG_WR(sc, (MISC_REG_AEU_GENERAL_ATTN_12 +
779 (SC_FUNC(sc) * sizeof(uint32_t))), 1);
782 /* send the MCP a request, block until there is a reply */
784 elink_cb_fw_command(struct bnx2x_softc *sc, uint32_t command, uint32_t param)
786 int mb_idx = SC_FW_MB_IDX(sc);
790 uint8_t delay = CHIP_REV_IS_SLOW(sc) ? 100 : 10;
793 SHMEM_WR(sc, func_mb[mb_idx].drv_mb_param, param);
794 SHMEM_WR(sc, func_mb[mb_idx].drv_mb_header, (command | seq));
797 "wrote command 0x%08x to FW MB param 0x%08x",
798 (command | seq), param);
800 /* Let the FW do it's magic. GIve it up to 5 seconds... */
803 rc = SHMEM_RD(sc, func_mb[mb_idx].fw_mb_header);
804 } while ((seq != (rc & FW_MSG_SEQ_NUMBER_MASK)) && (cnt++ < 500));
806 /* is this a reply to our command? */
807 if (seq == (rc & FW_MSG_SEQ_NUMBER_MASK)) {
808 rc &= FW_MSG_CODE_MASK;
811 PMD_DRV_LOG(NOTICE, "FW failed to respond!");
819 bnx2x_fw_command(struct bnx2x_softc *sc, uint32_t command, uint32_t param)
821 return elink_cb_fw_command(sc, command, param);
825 __storm_memset_dma_mapping(struct bnx2x_softc *sc, uint32_t addr,
828 REG_WR(sc, addr, U64_LO(mapping));
829 REG_WR(sc, (addr + 4), U64_HI(mapping));
833 storm_memset_spq_addr(struct bnx2x_softc *sc, phys_addr_t mapping,
836 uint32_t addr = (XSEM_REG_FAST_MEMORY +
837 XSTORM_SPQ_PAGE_BASE_OFFSET(abs_fid));
838 __storm_memset_dma_mapping(sc, addr, mapping);
842 storm_memset_vf_to_pf(struct bnx2x_softc *sc, uint16_t abs_fid, uint16_t pf_id)
844 REG_WR8(sc, (BAR_XSTRORM_INTMEM + XSTORM_VF_TO_PF_OFFSET(abs_fid)),
846 REG_WR8(sc, (BAR_CSTRORM_INTMEM + CSTORM_VF_TO_PF_OFFSET(abs_fid)),
848 REG_WR8(sc, (BAR_TSTRORM_INTMEM + TSTORM_VF_TO_PF_OFFSET(abs_fid)),
850 REG_WR8(sc, (BAR_USTRORM_INTMEM + USTORM_VF_TO_PF_OFFSET(abs_fid)),
855 storm_memset_func_en(struct bnx2x_softc *sc, uint16_t abs_fid, uint8_t enable)
857 REG_WR8(sc, (BAR_XSTRORM_INTMEM + XSTORM_FUNC_EN_OFFSET(abs_fid)),
859 REG_WR8(sc, (BAR_CSTRORM_INTMEM + CSTORM_FUNC_EN_OFFSET(abs_fid)),
861 REG_WR8(sc, (BAR_TSTRORM_INTMEM + TSTORM_FUNC_EN_OFFSET(abs_fid)),
863 REG_WR8(sc, (BAR_USTRORM_INTMEM + USTORM_FUNC_EN_OFFSET(abs_fid)),
868 storm_memset_eq_data(struct bnx2x_softc *sc, struct event_ring_data *eq_data,
874 addr = (BAR_CSTRORM_INTMEM + CSTORM_EVENT_RING_DATA_OFFSET(pfid));
875 size = sizeof(struct event_ring_data);
876 ecore_storm_memset_struct(sc, addr, size, (uint32_t *) eq_data);
880 storm_memset_eq_prod(struct bnx2x_softc *sc, uint16_t eq_prod, uint16_t pfid)
882 uint32_t addr = (BAR_CSTRORM_INTMEM +
883 CSTORM_EVENT_RING_PROD_OFFSET(pfid));
884 REG_WR16(sc, addr, eq_prod);
888 * Post a slowpath command.
890 * A slowpath command is used to propagate a configuration change through
891 * the controller in a controlled manner, allowing each STORM processor and
892 * other H/W blocks to phase in the change. The commands sent on the
893 * slowpath are referred to as ramrods. Depending on the ramrod used the
894 * completion of the ramrod will occur in different ways. Here's a
895 * breakdown of ramrods and how they complete:
897 * RAMROD_CMD_ID_ETH_PORT_SETUP
898 * Used to setup the leading connection on a port. Completes on the
899 * Receive Completion Queue (RCQ) of that port (typically fp[0]).
901 * RAMROD_CMD_ID_ETH_CLIENT_SETUP
902 * Used to setup an additional connection on a port. Completes on the
903 * RCQ of the multi-queue/RSS connection being initialized.
905 * RAMROD_CMD_ID_ETH_STAT_QUERY
906 * Used to force the storm processors to update the statistics database
907 * in host memory. This ramrod is send on the leading connection CID and
908 * completes as an index increment of the CSTORM on the default status
911 * RAMROD_CMD_ID_ETH_UPDATE
912 * Used to update the state of the leading connection, usually to udpate
913 * the RSS indirection table. Completes on the RCQ of the leading
914 * connection. (Not currently used under FreeBSD until OS support becomes
917 * RAMROD_CMD_ID_ETH_HALT
918 * Used when tearing down a connection prior to driver unload. Completes
919 * on the RCQ of the multi-queue/RSS connection being torn down. Don't
920 * use this on the leading connection.
922 * RAMROD_CMD_ID_ETH_SET_MAC
923 * Sets the Unicast/Broadcast/Multicast used by the port. Completes on
924 * the RCQ of the leading connection.
926 * RAMROD_CMD_ID_ETH_CFC_DEL
927 * Used when tearing down a conneciton prior to driver unload. Completes
928 * on the RCQ of the leading connection (since the current connection
929 * has been completely removed from controller memory).
931 * RAMROD_CMD_ID_ETH_PORT_DEL
932 * Used to tear down the leading connection prior to driver unload,
933 * typically fp[0]. Completes as an index increment of the CSTORM on the
934 * default status block.
936 * RAMROD_CMD_ID_ETH_FORWARD_SETUP
937 * Used for connection offload. Completes on the RCQ of the multi-queue
938 * RSS connection that is being offloaded. (Not currently used under
941 * There can only be one command pending per function.
944 * 0 = Success, !0 = Failure.
947 /* must be called under the spq lock */
948 static inline struct eth_spe *bnx2x_sp_get_next(struct bnx2x_softc *sc)
950 struct eth_spe *next_spe = sc->spq_prod_bd;
952 if (sc->spq_prod_bd == sc->spq_last_bd) {
953 /* wrap back to the first eth_spq */
954 sc->spq_prod_bd = sc->spq;
955 sc->spq_prod_idx = 0;
964 /* must be called under the spq lock */
965 static void bnx2x_sp_prod_update(struct bnx2x_softc *sc)
967 int func = SC_FUNC(sc);
970 * Make sure that BD data is updated before writing the producer.
971 * BD data is written to the memory, the producer is read from the
972 * memory, thus we need a full memory barrier to ensure the ordering.
976 REG_WR16(sc, (BAR_XSTRORM_INTMEM + XSTORM_SPQ_PROD_OFFSET(func)),
983 * bnx2x_is_contextless_ramrod - check if the current command ends on EQ
985 * @cmd: command to check
986 * @cmd_type: command type
988 static int bnx2x_is_contextless_ramrod(int cmd, int cmd_type)
990 if ((cmd_type == NONE_CONNECTION_TYPE) ||
991 (cmd == RAMROD_CMD_ID_ETH_FORWARD_SETUP) ||
992 (cmd == RAMROD_CMD_ID_ETH_CLASSIFICATION_RULES) ||
993 (cmd == RAMROD_CMD_ID_ETH_FILTER_RULES) ||
994 (cmd == RAMROD_CMD_ID_ETH_MULTICAST_RULES) ||
995 (cmd == RAMROD_CMD_ID_ETH_SET_MAC) ||
996 (cmd == RAMROD_CMD_ID_ETH_RSS_UPDATE)) {
1004 * bnx2x_sp_post - place a single command on an SP ring
1006 * @sc: driver handle
1007 * @command: command to place (e.g. SETUP, FILTER_RULES, etc.)
1008 * @cid: SW CID the command is related to
1009 * @data_hi: command private data address (high 32 bits)
1010 * @data_lo: command private data address (low 32 bits)
1011 * @cmd_type: command type (e.g. NONE, ETH)
1013 * SP data is handled as if it's always an address pair, thus data fields are
1014 * not swapped to little endian in upper functions. Instead this function swaps
1015 * data as if it's two uint32 fields.
1018 bnx2x_sp_post(struct bnx2x_softc *sc, int command, int cid, uint32_t data_hi,
1019 uint32_t data_lo, int cmd_type)
1021 struct eth_spe *spe;
1025 common = bnx2x_is_contextless_ramrod(command, cmd_type);
1028 if (!atomic_load_acq_long(&sc->eq_spq_left)) {
1029 PMD_DRV_LOG(INFO, "EQ ring is full!");
1033 if (!atomic_load_acq_long(&sc->cq_spq_left)) {
1034 PMD_DRV_LOG(INFO, "SPQ ring is full!");
1039 spe = bnx2x_sp_get_next(sc);
1041 /* CID needs port number to be encoded int it */
1042 spe->hdr.conn_and_cmd_data =
1043 htole32((command << SPE_HDR_CMD_ID_SHIFT) | HW_CID(sc, cid));
1045 type = (cmd_type << SPE_HDR_CONN_TYPE_SHIFT) & SPE_HDR_CONN_TYPE;
1047 /* TBD: Check if it works for VFs */
1048 type |= ((SC_FUNC(sc) << SPE_HDR_FUNCTION_ID_SHIFT) &
1049 SPE_HDR_FUNCTION_ID);
1051 spe->hdr.type = htole16(type);
1053 spe->data.update_data_addr.hi = htole32(data_hi);
1054 spe->data.update_data_addr.lo = htole32(data_lo);
1057 * It's ok if the actual decrement is issued towards the memory
1058 * somewhere between the lock and unlock. Thus no more explict
1059 * memory barrier is needed.
1062 atomic_subtract_acq_long(&sc->eq_spq_left, 1);
1064 atomic_subtract_acq_long(&sc->cq_spq_left, 1);
1068 "SPQE[%x] (%x:%x) (cmd, common?) (%d,%d) hw_cid %x"
1069 "data (%x:%x) type(0x%x) left (CQ, EQ) (%lx,%lx)",
1071 (uint32_t) U64_HI(sc->spq_dma.paddr),
1072 (uint32_t) (U64_LO(sc->spq_dma.paddr) +
1073 (uint8_t *) sc->spq_prod_bd -
1074 (uint8_t *) sc->spq), command, common,
1075 HW_CID(sc, cid), data_hi, data_lo, type,
1076 atomic_load_acq_long(&sc->cq_spq_left),
1077 atomic_load_acq_long(&sc->eq_spq_left));
1079 bnx2x_sp_prod_update(sc);
1084 static void bnx2x_drv_pulse(struct bnx2x_softc *sc)
1086 SHMEM_WR(sc, func_mb[SC_FW_MB_IDX(sc)].drv_pulse_mb,
1087 sc->fw_drv_pulse_wr_seq);
1090 static int bnx2x_tx_queue_has_work(const struct bnx2x_fastpath *fp)
1093 struct bnx2x_tx_queue *txq = fp->sc->tx_queues[fp->index];
1095 if (unlikely(!txq)) {
1096 PMD_TX_LOG(ERR, "ERROR: TX queue is NULL");
1100 mb(); /* status block fields can change */
1101 hw_cons = le16toh(*fp->tx_cons_sb);
1102 return hw_cons != txq->tx_pkt_head;
1105 static uint8_t bnx2x_has_tx_work(struct bnx2x_fastpath *fp)
1107 /* expand this for multi-cos if ever supported */
1108 return bnx2x_tx_queue_has_work(fp);
1111 static int bnx2x_has_rx_work(struct bnx2x_fastpath *fp)
1113 uint16_t rx_cq_cons_sb;
1114 struct bnx2x_rx_queue *rxq;
1115 rxq = fp->sc->rx_queues[fp->index];
1116 if (unlikely(!rxq)) {
1117 PMD_RX_LOG(ERR, "ERROR: RX queue is NULL");
1121 mb(); /* status block fields can change */
1122 rx_cq_cons_sb = le16toh(*fp->rx_cq_cons_sb);
1123 if (unlikely((rx_cq_cons_sb & MAX_RCQ_ENTRIES(rxq)) ==
1124 MAX_RCQ_ENTRIES(rxq)))
1126 return rxq->rx_cq_head != rx_cq_cons_sb;
1130 bnx2x_sp_event(struct bnx2x_softc *sc, struct bnx2x_fastpath *fp,
1131 union eth_rx_cqe *rr_cqe)
1133 #ifdef RTE_LIBRTE_BNX2X_DEBUG
1134 int cid = SW_CID(rr_cqe->ramrod_cqe.conn_and_cmd_data);
1136 int command = CQE_CMD(rr_cqe->ramrod_cqe.conn_and_cmd_data);
1137 enum ecore_queue_cmd drv_cmd = ECORE_Q_CMD_MAX;
1138 struct ecore_queue_sp_obj *q_obj = &BNX2X_SP_OBJ(sc, fp).q_obj;
1141 "fp=%d cid=%d got ramrod #%d state is %x type is %d",
1142 fp->index, cid, command, sc->state,
1143 rr_cqe->ramrod_cqe.ramrod_type);
1146 case (RAMROD_CMD_ID_ETH_CLIENT_UPDATE):
1147 PMD_DRV_LOG(DEBUG, "got UPDATE ramrod. CID %d", cid);
1148 drv_cmd = ECORE_Q_CMD_UPDATE;
1151 case (RAMROD_CMD_ID_ETH_CLIENT_SETUP):
1152 PMD_DRV_LOG(DEBUG, "got MULTI[%d] setup ramrod", cid);
1153 drv_cmd = ECORE_Q_CMD_SETUP;
1156 case (RAMROD_CMD_ID_ETH_TX_QUEUE_SETUP):
1157 PMD_DRV_LOG(DEBUG, "got MULTI[%d] tx-only setup ramrod", cid);
1158 drv_cmd = ECORE_Q_CMD_SETUP_TX_ONLY;
1161 case (RAMROD_CMD_ID_ETH_HALT):
1162 PMD_DRV_LOG(DEBUG, "got MULTI[%d] halt ramrod", cid);
1163 drv_cmd = ECORE_Q_CMD_HALT;
1166 case (RAMROD_CMD_ID_ETH_TERMINATE):
1167 PMD_DRV_LOG(DEBUG, "got MULTI[%d] teminate ramrod", cid);
1168 drv_cmd = ECORE_Q_CMD_TERMINATE;
1171 case (RAMROD_CMD_ID_ETH_EMPTY):
1172 PMD_DRV_LOG(DEBUG, "got MULTI[%d] empty ramrod", cid);
1173 drv_cmd = ECORE_Q_CMD_EMPTY;
1178 "ERROR: unexpected MC reply (%d)"
1179 "on fp[%d]", command, fp->index);
1183 if ((drv_cmd != ECORE_Q_CMD_MAX) &&
1184 q_obj->complete_cmd(sc, q_obj, drv_cmd)) {
1186 * q_obj->complete_cmd() failure means that this was
1187 * an unexpected completion.
1189 * In this case we don't want to increase the sc->spq_left
1190 * because apparently we haven't sent this command the first
1193 // rte_panic("Unexpected SP completion");
1197 atomic_add_acq_long(&sc->cq_spq_left, 1);
1199 PMD_DRV_LOG(DEBUG, "sc->cq_spq_left 0x%lx",
1200 atomic_load_acq_long(&sc->cq_spq_left));
1203 static uint8_t bnx2x_rxeof(struct bnx2x_softc *sc, struct bnx2x_fastpath *fp)
1205 struct bnx2x_rx_queue *rxq;
1206 uint16_t bd_cons, bd_prod, bd_prod_fw, comp_ring_cons;
1207 uint16_t hw_cq_cons, sw_cq_cons, sw_cq_prod;
1209 rxq = sc->rx_queues[fp->index];
1211 PMD_RX_LOG(ERR, "RX queue %d is NULL", fp->index);
1215 /* CQ "next element" is of the size of the regular element */
1216 hw_cq_cons = le16toh(*fp->rx_cq_cons_sb);
1217 if (unlikely((hw_cq_cons & USABLE_RCQ_ENTRIES_PER_PAGE) ==
1218 USABLE_RCQ_ENTRIES_PER_PAGE)) {
1222 bd_cons = rxq->rx_bd_head;
1223 bd_prod = rxq->rx_bd_tail;
1224 bd_prod_fw = bd_prod;
1225 sw_cq_cons = rxq->rx_cq_head;
1226 sw_cq_prod = rxq->rx_cq_tail;
1229 * Memory barrier necessary as speculative reads of the rx
1230 * buffer can be ahead of the index in the status block
1234 while (sw_cq_cons != hw_cq_cons) {
1235 union eth_rx_cqe *cqe;
1236 struct eth_fast_path_rx_cqe *cqe_fp;
1237 uint8_t cqe_fp_flags;
1238 enum eth_rx_cqe_type cqe_fp_type;
1240 comp_ring_cons = RCQ_ENTRY(sw_cq_cons, rxq);
1241 bd_prod = RX_BD(bd_prod, rxq);
1242 bd_cons = RX_BD(bd_cons, rxq);
1244 cqe = &rxq->cq_ring[comp_ring_cons];
1245 cqe_fp = &cqe->fast_path_cqe;
1246 cqe_fp_flags = cqe_fp->type_error_flags;
1247 cqe_fp_type = cqe_fp_flags & ETH_FAST_PATH_RX_CQE_TYPE;
1249 /* is this a slowpath msg? */
1250 if (CQE_TYPE_SLOW(cqe_fp_type)) {
1251 bnx2x_sp_event(sc, fp, cqe);
1255 /* is this an error packet? */
1256 if (unlikely(cqe_fp_flags &
1257 ETH_FAST_PATH_RX_CQE_PHY_DECODE_ERR_FLG)) {
1258 PMD_RX_LOG(DEBUG, "flags 0x%x rx packet %u",
1259 cqe_fp_flags, sw_cq_cons);
1263 PMD_RX_LOG(DEBUG, "Dropping fastpath called from attn poller!");
1266 bd_cons = NEXT_RX_BD(bd_cons);
1267 bd_prod = NEXT_RX_BD(bd_prod);
1268 bd_prod_fw = NEXT_RX_BD(bd_prod_fw);
1271 sw_cq_prod = NEXT_RCQ_IDX(sw_cq_prod);
1272 sw_cq_cons = NEXT_RCQ_IDX(sw_cq_cons);
1274 } /* while work to do */
1276 rxq->rx_bd_head = bd_cons;
1277 rxq->rx_bd_tail = bd_prod_fw;
1278 rxq->rx_cq_head = sw_cq_cons;
1279 rxq->rx_cq_tail = sw_cq_prod;
1281 /* Update producers */
1282 bnx2x_update_rx_prod(sc, fp, bd_prod_fw, sw_cq_prod);
1284 return sw_cq_cons != hw_cq_cons;
1288 bnx2x_free_tx_pkt(__rte_unused struct bnx2x_fastpath *fp, struct bnx2x_tx_queue *txq,
1289 uint16_t pkt_idx, uint16_t bd_idx)
1291 struct eth_tx_start_bd *tx_start_bd =
1292 &txq->tx_ring[TX_BD(bd_idx, txq)].start_bd;
1293 uint16_t nbd = rte_le_to_cpu_16(tx_start_bd->nbd);
1294 struct rte_mbuf *tx_mbuf = txq->sw_ring[TX_BD(pkt_idx, txq)];
1296 if (likely(tx_mbuf != NULL)) {
1297 rte_pktmbuf_free_seg(tx_mbuf);
1299 PMD_RX_LOG(ERR, "fp[%02d] lost mbuf %lu",
1300 fp->index, (unsigned long)TX_BD(pkt_idx, txq));
1303 txq->sw_ring[TX_BD(pkt_idx, txq)] = NULL;
1304 txq->nb_tx_avail += nbd;
1307 bd_idx = NEXT_TX_BD(bd_idx);
1312 /* processes transmit completions */
1313 uint8_t bnx2x_txeof(__rte_unused struct bnx2x_softc * sc, struct bnx2x_fastpath * fp)
1315 uint16_t bd_cons, hw_cons, sw_cons;
1316 __rte_unused uint16_t tx_bd_avail;
1318 struct bnx2x_tx_queue *txq = fp->sc->tx_queues[fp->index];
1320 if (unlikely(!txq)) {
1321 PMD_TX_LOG(ERR, "ERROR: TX queue is NULL");
1325 bd_cons = txq->tx_bd_head;
1326 hw_cons = rte_le_to_cpu_16(*fp->tx_cons_sb);
1327 sw_cons = txq->tx_pkt_head;
1329 while (sw_cons != hw_cons) {
1330 bd_cons = bnx2x_free_tx_pkt(fp, txq, sw_cons, bd_cons);
1334 txq->tx_pkt_head = sw_cons;
1335 txq->tx_bd_head = bd_cons;
1337 tx_bd_avail = txq->nb_tx_avail;
1339 PMD_TX_LOG(DEBUG, "fp[%02d] avail=%u cons_sb=%u, "
1340 "pkt_head=%u pkt_tail=%u bd_head=%u bd_tail=%u",
1341 fp->index, tx_bd_avail, hw_cons,
1342 txq->tx_pkt_head, txq->tx_pkt_tail,
1343 txq->tx_bd_head, txq->tx_bd_tail);
1347 static void bnx2x_drain_tx_queues(struct bnx2x_softc *sc)
1349 struct bnx2x_fastpath *fp;
1352 /* wait until all TX fastpath tasks have completed */
1353 for (i = 0; i < sc->num_queues; i++) {
1358 while (bnx2x_has_tx_work(fp)) {
1359 bnx2x_txeof(sc, fp);
1363 "Timeout waiting for fp[%d] "
1364 "transmits to complete!", i);
1365 rte_panic("tx drain failure");
1379 bnx2x_del_all_macs(struct bnx2x_softc *sc, struct ecore_vlan_mac_obj *mac_obj,
1380 int mac_type, uint8_t wait_for_comp)
1382 unsigned long ramrod_flags = 0, vlan_mac_flags = 0;
1385 /* wait for completion of requested */
1386 if (wait_for_comp) {
1387 bnx2x_set_bit(RAMROD_COMP_WAIT, &ramrod_flags);
1390 /* Set the mac type of addresses we want to clear */
1391 bnx2x_set_bit(mac_type, &vlan_mac_flags);
1393 rc = mac_obj->delete_all(sc, mac_obj, &vlan_mac_flags, &ramrod_flags);
1395 PMD_DRV_LOG(ERR, "Failed to delete MACs (%d)", rc);
1401 bnx2x_fill_accept_flags(struct bnx2x_softc *sc, uint32_t rx_mode,
1402 unsigned long *rx_accept_flags,
1403 unsigned long *tx_accept_flags)
1405 /* Clear the flags first */
1406 *rx_accept_flags = 0;
1407 *tx_accept_flags = 0;
1410 case BNX2X_RX_MODE_NONE:
1412 * 'drop all' supersedes any accept flags that may have been
1413 * passed to the function.
1417 case BNX2X_RX_MODE_NORMAL:
1418 bnx2x_set_bit(ECORE_ACCEPT_UNICAST, rx_accept_flags);
1419 bnx2x_set_bit(ECORE_ACCEPT_MULTICAST, rx_accept_flags);
1420 bnx2x_set_bit(ECORE_ACCEPT_BROADCAST, rx_accept_flags);
1422 /* internal switching mode */
1423 bnx2x_set_bit(ECORE_ACCEPT_UNICAST, tx_accept_flags);
1424 bnx2x_set_bit(ECORE_ACCEPT_MULTICAST, tx_accept_flags);
1425 bnx2x_set_bit(ECORE_ACCEPT_BROADCAST, tx_accept_flags);
1429 case BNX2X_RX_MODE_ALLMULTI:
1430 bnx2x_set_bit(ECORE_ACCEPT_UNICAST, rx_accept_flags);
1431 bnx2x_set_bit(ECORE_ACCEPT_ALL_MULTICAST, rx_accept_flags);
1432 bnx2x_set_bit(ECORE_ACCEPT_BROADCAST, rx_accept_flags);
1434 /* internal switching mode */
1435 bnx2x_set_bit(ECORE_ACCEPT_UNICAST, tx_accept_flags);
1436 bnx2x_set_bit(ECORE_ACCEPT_ALL_MULTICAST, tx_accept_flags);
1437 bnx2x_set_bit(ECORE_ACCEPT_BROADCAST, tx_accept_flags);
1441 case BNX2X_RX_MODE_ALLMULTI_PROMISC:
1442 case BNX2X_RX_MODE_PROMISC:
1444 * According to deffinition of SI mode, iface in promisc mode
1445 * should receive matched and unmatched (in resolution of port)
1448 bnx2x_set_bit(ECORE_ACCEPT_UNMATCHED, rx_accept_flags);
1449 bnx2x_set_bit(ECORE_ACCEPT_UNICAST, rx_accept_flags);
1450 bnx2x_set_bit(ECORE_ACCEPT_ALL_MULTICAST, rx_accept_flags);
1451 bnx2x_set_bit(ECORE_ACCEPT_BROADCAST, rx_accept_flags);
1453 /* internal switching mode */
1454 bnx2x_set_bit(ECORE_ACCEPT_ALL_MULTICAST, tx_accept_flags);
1455 bnx2x_set_bit(ECORE_ACCEPT_BROADCAST, tx_accept_flags);
1458 bnx2x_set_bit(ECORE_ACCEPT_ALL_UNICAST, tx_accept_flags);
1460 bnx2x_set_bit(ECORE_ACCEPT_UNICAST, tx_accept_flags);
1466 PMD_RX_LOG(ERR, "Unknown rx_mode (%d)", rx_mode);
1470 /* Set ACCEPT_ANY_VLAN as we do not enable filtering by VLAN */
1471 if (rx_mode != BNX2X_RX_MODE_NONE) {
1472 bnx2x_set_bit(ECORE_ACCEPT_ANY_VLAN, rx_accept_flags);
1473 bnx2x_set_bit(ECORE_ACCEPT_ANY_VLAN, tx_accept_flags);
1480 bnx2x_set_q_rx_mode(struct bnx2x_softc *sc, uint8_t cl_id,
1481 unsigned long rx_mode_flags,
1482 unsigned long rx_accept_flags,
1483 unsigned long tx_accept_flags, unsigned long ramrod_flags)
1485 struct ecore_rx_mode_ramrod_params ramrod_param;
1488 memset(&ramrod_param, 0, sizeof(ramrod_param));
1490 /* Prepare ramrod parameters */
1491 ramrod_param.cid = 0;
1492 ramrod_param.cl_id = cl_id;
1493 ramrod_param.rx_mode_obj = &sc->rx_mode_obj;
1494 ramrod_param.func_id = SC_FUNC(sc);
1496 ramrod_param.pstate = &sc->sp_state;
1497 ramrod_param.state = ECORE_FILTER_RX_MODE_PENDING;
1499 ramrod_param.rdata = BNX2X_SP(sc, rx_mode_rdata);
1500 ramrod_param.rdata_mapping =
1501 (phys_addr_t)BNX2X_SP_MAPPING(sc, rx_mode_rdata),
1502 bnx2x_set_bit(ECORE_FILTER_RX_MODE_PENDING, &sc->sp_state);
1504 ramrod_param.ramrod_flags = ramrod_flags;
1505 ramrod_param.rx_mode_flags = rx_mode_flags;
1507 ramrod_param.rx_accept_flags = rx_accept_flags;
1508 ramrod_param.tx_accept_flags = tx_accept_flags;
1510 rc = ecore_config_rx_mode(sc, &ramrod_param);
1512 PMD_RX_LOG(ERR, "Set rx_mode %d failed", sc->rx_mode);
1519 int bnx2x_set_storm_rx_mode(struct bnx2x_softc *sc)
1521 unsigned long rx_mode_flags = 0, ramrod_flags = 0;
1522 unsigned long rx_accept_flags = 0, tx_accept_flags = 0;
1525 rc = bnx2x_fill_accept_flags(sc, sc->rx_mode, &rx_accept_flags,
1531 bnx2x_set_bit(RAMROD_RX, &ramrod_flags);
1532 bnx2x_set_bit(RAMROD_TX, &ramrod_flags);
1533 bnx2x_set_bit(RAMROD_COMP_WAIT, &ramrod_flags);
1535 return bnx2x_set_q_rx_mode(sc, sc->fp[0].cl_id, rx_mode_flags,
1536 rx_accept_flags, tx_accept_flags,
1540 /* returns the "mcp load_code" according to global load_count array */
1541 static int bnx2x_nic_load_no_mcp(struct bnx2x_softc *sc)
1543 int path = SC_PATH(sc);
1544 int port = SC_PORT(sc);
1546 PMD_DRV_LOG(INFO, "NO MCP - load counts[%d] %d, %d, %d",
1547 path, load_count[path][0], load_count[path][1],
1548 load_count[path][2]);
1550 load_count[path][0]++;
1551 load_count[path][1 + port]++;
1552 PMD_DRV_LOG(INFO, "NO MCP - new load counts[%d] %d, %d, %d",
1553 path, load_count[path][0], load_count[path][1],
1554 load_count[path][2]);
1555 if (load_count[path][0] == 1)
1556 return FW_MSG_CODE_DRV_LOAD_COMMON;
1557 else if (load_count[path][1 + port] == 1)
1558 return FW_MSG_CODE_DRV_LOAD_PORT;
1560 return FW_MSG_CODE_DRV_LOAD_FUNCTION;
1563 /* returns the "mcp load_code" according to global load_count array */
1564 static int bnx2x_nic_unload_no_mcp(struct bnx2x_softc *sc)
1566 int port = SC_PORT(sc);
1567 int path = SC_PATH(sc);
1569 PMD_DRV_LOG(INFO, "NO MCP - load counts[%d] %d, %d, %d",
1570 path, load_count[path][0], load_count[path][1],
1571 load_count[path][2]);
1572 load_count[path][0]--;
1573 load_count[path][1 + port]--;
1574 PMD_DRV_LOG(INFO, "NO MCP - new load counts[%d] %d, %d, %d",
1575 path, load_count[path][0], load_count[path][1],
1576 load_count[path][2]);
1577 if (load_count[path][0] == 0) {
1578 return FW_MSG_CODE_DRV_UNLOAD_COMMON;
1579 } else if (load_count[path][1 + port] == 0) {
1580 return FW_MSG_CODE_DRV_UNLOAD_PORT;
1582 return FW_MSG_CODE_DRV_UNLOAD_FUNCTION;
1586 /* request unload mode from the MCP: COMMON, PORT or FUNCTION */
1587 static uint32_t bnx2x_send_unload_req(struct bnx2x_softc *sc, int unload_mode)
1589 uint32_t reset_code = 0;
1591 /* Select the UNLOAD request mode */
1592 if (unload_mode == UNLOAD_NORMAL) {
1593 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS;
1595 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS;
1598 /* Send the request to the MCP */
1599 if (!BNX2X_NOMCP(sc)) {
1600 reset_code = bnx2x_fw_command(sc, reset_code, 0);
1602 reset_code = bnx2x_nic_unload_no_mcp(sc);
1608 /* send UNLOAD_DONE command to the MCP */
1609 static void bnx2x_send_unload_done(struct bnx2x_softc *sc, uint8_t keep_link)
1611 uint32_t reset_param =
1612 keep_link ? DRV_MSG_CODE_UNLOAD_SKIP_LINK_RESET : 0;
1614 /* Report UNLOAD_DONE to MCP */
1615 if (!BNX2X_NOMCP(sc)) {
1616 bnx2x_fw_command(sc, DRV_MSG_CODE_UNLOAD_DONE, reset_param);
1620 static int bnx2x_func_wait_started(struct bnx2x_softc *sc)
1624 if (!sc->port.pmf) {
1629 * (assumption: No Attention from MCP at this stage)
1630 * PMF probably in the middle of TX disable/enable transaction
1631 * 1. Sync IRS for default SB
1632 * 2. Sync SP queue - this guarantees us that attention handling started
1633 * 3. Wait, that TX disable/enable transaction completes
1635 * 1+2 guarantee that if DCBX attention was scheduled it already changed
1636 * pending bit of transaction from STARTED-->TX_STOPPED, if we already
1637 * received completion for the transaction the state is TX_STOPPED.
1638 * State will return to STARTED after completion of TX_STOPPED-->STARTED
1642 while (ecore_func_get_state(sc, &sc->func_obj) !=
1643 ECORE_F_STATE_STARTED && tout--) {
1647 if (ecore_func_get_state(sc, &sc->func_obj) != ECORE_F_STATE_STARTED) {
1649 * Failed to complete the transaction in a "good way"
1650 * Force both transactions with CLR bit.
1652 struct ecore_func_state_params func_params = { NULL };
1654 PMD_DRV_LOG(NOTICE, "Unexpected function state! "
1655 "Forcing STARTED-->TX_STOPPED-->STARTED");
1657 func_params.f_obj = &sc->func_obj;
1658 bnx2x_set_bit(RAMROD_DRV_CLR_ONLY, &func_params.ramrod_flags);
1660 /* STARTED-->TX_STOPPED */
1661 func_params.cmd = ECORE_F_CMD_TX_STOP;
1662 ecore_func_state_change(sc, &func_params);
1664 /* TX_STOPPED-->STARTED */
1665 func_params.cmd = ECORE_F_CMD_TX_START;
1666 return ecore_func_state_change(sc, &func_params);
1672 static int bnx2x_stop_queue(struct bnx2x_softc *sc, int index)
1674 struct bnx2x_fastpath *fp = &sc->fp[index];
1675 struct ecore_queue_state_params q_params = { NULL };
1678 PMD_DRV_LOG(DEBUG, "stopping queue %d cid %d", index, fp->index);
1680 q_params.q_obj = &sc->sp_objs[fp->index].q_obj;
1681 /* We want to wait for completion in this context */
1682 bnx2x_set_bit(RAMROD_COMP_WAIT, &q_params.ramrod_flags);
1684 /* Stop the primary connection: */
1686 /* ...halt the connection */
1687 q_params.cmd = ECORE_Q_CMD_HALT;
1688 rc = ecore_queue_state_change(sc, &q_params);
1693 /* ...terminate the connection */
1694 q_params.cmd = ECORE_Q_CMD_TERMINATE;
1695 memset(&q_params.params.terminate, 0,
1696 sizeof(q_params.params.terminate));
1697 q_params.params.terminate.cid_index = FIRST_TX_COS_INDEX;
1698 rc = ecore_queue_state_change(sc, &q_params);
1703 /* ...delete cfc entry */
1704 q_params.cmd = ECORE_Q_CMD_CFC_DEL;
1705 memset(&q_params.params.cfc_del, 0, sizeof(q_params.params.cfc_del));
1706 q_params.params.cfc_del.cid_index = FIRST_TX_COS_INDEX;
1707 return ecore_queue_state_change(sc, &q_params);
1710 /* wait for the outstanding SP commands */
1711 static uint8_t bnx2x_wait_sp_comp(struct bnx2x_softc *sc, unsigned long mask)
1714 int tout = 5000; /* wait for 5 secs tops */
1718 if (!(atomic_load_acq_long(&sc->sp_state) & mask)) {
1727 tmp = atomic_load_acq_long(&sc->sp_state);
1729 PMD_DRV_LOG(INFO, "Filtering completion timed out: "
1730 "sp_state 0x%lx, mask 0x%lx", tmp, mask);
1737 static int bnx2x_func_stop(struct bnx2x_softc *sc)
1739 struct ecore_func_state_params func_params = { NULL };
1742 /* prepare parameters for function state transitions */
1743 bnx2x_set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags);
1744 func_params.f_obj = &sc->func_obj;
1745 func_params.cmd = ECORE_F_CMD_STOP;
1748 * Try to stop the function the 'good way'. If it fails (in case
1749 * of a parity error during bnx2x_chip_cleanup()) and we are
1750 * not in a debug mode, perform a state transaction in order to
1751 * enable further HW_RESET transaction.
1753 rc = ecore_func_state_change(sc, &func_params);
1755 PMD_DRV_LOG(NOTICE, "FUNC_STOP ramrod failed. "
1756 "Running a dry transaction");
1757 bnx2x_set_bit(RAMROD_DRV_CLR_ONLY, &func_params.ramrod_flags);
1758 return ecore_func_state_change(sc, &func_params);
1764 static int bnx2x_reset_hw(struct bnx2x_softc *sc, uint32_t load_code)
1766 struct ecore_func_state_params func_params = { NULL };
1768 /* Prepare parameters for function state transitions */
1769 bnx2x_set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags);
1771 func_params.f_obj = &sc->func_obj;
1772 func_params.cmd = ECORE_F_CMD_HW_RESET;
1774 func_params.params.hw_init.load_phase = load_code;
1776 return ecore_func_state_change(sc, &func_params);
1779 static void bnx2x_int_disable_sync(struct bnx2x_softc *sc, int disable_hw)
1782 /* prevent the HW from sending interrupts */
1783 bnx2x_int_disable(sc);
1788 bnx2x_chip_cleanup(struct bnx2x_softc *sc, uint32_t unload_mode, uint8_t keep_link)
1790 int port = SC_PORT(sc);
1791 struct ecore_mcast_ramrod_params rparam = { NULL };
1792 uint32_t reset_code;
1795 bnx2x_drain_tx_queues(sc);
1797 /* give HW time to discard old tx messages */
1800 /* Clean all ETH MACs */
1801 rc = bnx2x_del_all_macs(sc, &sc->sp_objs[0].mac_obj, ECORE_ETH_MAC,
1804 PMD_DRV_LOG(NOTICE, "Failed to delete all ETH MACs (%d)", rc);
1807 /* Clean up UC list */
1808 rc = bnx2x_del_all_macs(sc, &sc->sp_objs[0].mac_obj, ECORE_UC_LIST_MAC,
1811 PMD_DRV_LOG(NOTICE, "Failed to delete UC MACs list (%d)", rc);
1815 REG_WR(sc, NIG_REG_LLH0_FUNC_EN + port * 8, 0);
1817 /* Set "drop all" to stop Rx */
1820 * We need to take the if_maddr_lock() here in order to prevent
1821 * a race between the completion code and this code.
1824 if (bnx2x_test_bit(ECORE_FILTER_RX_MODE_PENDING, &sc->sp_state)) {
1825 bnx2x_set_bit(ECORE_FILTER_RX_MODE_SCHED, &sc->sp_state);
1827 bnx2x_set_storm_rx_mode(sc);
1830 /* Clean up multicast configuration */
1831 rparam.mcast_obj = &sc->mcast_obj;
1832 rc = ecore_config_mcast(sc, &rparam, ECORE_MCAST_CMD_DEL);
1835 "Failed to send DEL MCAST command (%d)", rc);
1839 * Send the UNLOAD_REQUEST to the MCP. This will return if
1840 * this function should perform FUNCTION, PORT, or COMMON HW
1843 reset_code = bnx2x_send_unload_req(sc, unload_mode);
1846 * (assumption: No Attention from MCP at this stage)
1847 * PMF probably in the middle of TX disable/enable transaction
1849 rc = bnx2x_func_wait_started(sc);
1851 PMD_DRV_LOG(NOTICE, "bnx2x_func_wait_started failed");
1855 * Close multi and leading connections
1856 * Completions for ramrods are collected in a synchronous way
1858 for (i = 0; i < sc->num_queues; i++) {
1859 if (bnx2x_stop_queue(sc, i)) {
1865 * If SP settings didn't get completed so far - something
1866 * very wrong has happen.
1868 if (!bnx2x_wait_sp_comp(sc, ~0x0UL)) {
1869 PMD_DRV_LOG(NOTICE, "Common slow path ramrods got stuck!");
1874 rc = bnx2x_func_stop(sc);
1876 PMD_DRV_LOG(NOTICE, "Function stop failed!");
1879 /* disable HW interrupts */
1880 bnx2x_int_disable_sync(sc, TRUE);
1882 /* Reset the chip */
1883 rc = bnx2x_reset_hw(sc, reset_code);
1885 PMD_DRV_LOG(NOTICE, "Hardware reset failed");
1888 /* Report UNLOAD_DONE to MCP */
1889 bnx2x_send_unload_done(sc, keep_link);
1892 static void bnx2x_disable_close_the_gate(struct bnx2x_softc *sc)
1896 PMD_DRV_LOG(DEBUG, "Disabling 'close the gates'");
1898 val = REG_RD(sc, MISC_REG_AEU_GENERAL_MASK);
1899 val &= ~(MISC_AEU_GENERAL_MASK_REG_AEU_PXP_CLOSE_MASK |
1900 MISC_AEU_GENERAL_MASK_REG_AEU_NIG_CLOSE_MASK);
1901 REG_WR(sc, MISC_REG_AEU_GENERAL_MASK, val);
1905 * Cleans the object that have internal lists without sending
1906 * ramrods. Should be run when interrutps are disabled.
1908 static void bnx2x_squeeze_objects(struct bnx2x_softc *sc)
1910 unsigned long ramrod_flags = 0, vlan_mac_flags = 0;
1911 struct ecore_mcast_ramrod_params rparam = { NULL };
1912 struct ecore_vlan_mac_obj *mac_obj = &sc->sp_objs->mac_obj;
1915 /* Cleanup MACs' object first... */
1917 /* Wait for completion of requested */
1918 bnx2x_set_bit(RAMROD_COMP_WAIT, &ramrod_flags);
1919 /* Perform a dry cleanup */
1920 bnx2x_set_bit(RAMROD_DRV_CLR_ONLY, &ramrod_flags);
1922 /* Clean ETH primary MAC */
1923 bnx2x_set_bit(ECORE_ETH_MAC, &vlan_mac_flags);
1924 rc = mac_obj->delete_all(sc, &sc->sp_objs->mac_obj, &vlan_mac_flags,
1927 PMD_DRV_LOG(NOTICE, "Failed to clean ETH MACs (%d)", rc);
1930 /* Cleanup UC list */
1932 bnx2x_set_bit(ECORE_UC_LIST_MAC, &vlan_mac_flags);
1933 rc = mac_obj->delete_all(sc, mac_obj, &vlan_mac_flags, &ramrod_flags);
1935 PMD_DRV_LOG(NOTICE, "Failed to clean UC list MACs (%d)", rc);
1938 /* Now clean mcast object... */
1940 rparam.mcast_obj = &sc->mcast_obj;
1941 bnx2x_set_bit(RAMROD_DRV_CLR_ONLY, &rparam.ramrod_flags);
1943 /* Add a DEL command... */
1944 rc = ecore_config_mcast(sc, &rparam, ECORE_MCAST_CMD_DEL);
1947 "Failed to send DEL MCAST command (%d)", rc);
1950 /* now wait until all pending commands are cleared */
1952 rc = ecore_config_mcast(sc, &rparam, ECORE_MCAST_CMD_CONT);
1956 "Failed to clean MCAST object (%d)", rc);
1960 rc = ecore_config_mcast(sc, &rparam, ECORE_MCAST_CMD_CONT);
1964 /* stop the controller */
1967 bnx2x_nic_unload(struct bnx2x_softc *sc, uint32_t unload_mode, uint8_t keep_link)
1969 uint8_t global = FALSE;
1972 PMD_DRV_LOG(DEBUG, "Starting NIC unload...");
1974 /* stop the periodic callout */
1975 bnx2x_periodic_stop(sc);
1977 /* mark driver as unloaded in shmem2 */
1978 if (IS_PF(sc) && SHMEM2_HAS(sc, drv_capabilities_flag)) {
1979 val = SHMEM2_RD(sc, drv_capabilities_flag[SC_FW_MB_IDX(sc)]);
1980 SHMEM2_WR(sc, drv_capabilities_flag[SC_FW_MB_IDX(sc)],
1981 val & ~DRV_FLAGS_CAPABILITIES_LOADED_L2);
1984 if (IS_PF(sc) && sc->recovery_state != BNX2X_RECOVERY_DONE &&
1985 (sc->state == BNX2X_STATE_CLOSED || sc->state == BNX2X_STATE_ERROR)) {
1987 * We can get here if the driver has been unloaded
1988 * during parity error recovery and is either waiting for a
1989 * leader to complete or for other functions to unload and
1990 * then ifconfig down has been issued. In this case we want to
1991 * unload and let other functions to complete a recovery
1994 sc->recovery_state = BNX2X_RECOVERY_DONE;
1996 bnx2x_release_leader_lock(sc);
1999 PMD_DRV_LOG(NOTICE, "Can't unload in closed or error state");
2004 * Nothing to do during unload if previous bnx2x_nic_load()
2005 * did not completed successfully - all resourses are released.
2007 if ((sc->state == BNX2X_STATE_CLOSED) || (sc->state == BNX2X_STATE_ERROR)) {
2011 sc->state = BNX2X_STATE_CLOSING_WAITING_HALT;
2014 sc->rx_mode = BNX2X_RX_MODE_NONE;
2015 bnx2x_set_rx_mode(sc);
2019 /* set ALWAYS_ALIVE bit in shmem */
2020 sc->fw_drv_pulse_wr_seq |= DRV_PULSE_ALWAYS_ALIVE;
2022 bnx2x_drv_pulse(sc);
2024 bnx2x_stats_handle(sc, STATS_EVENT_STOP);
2025 bnx2x_save_statistics(sc);
2028 /* wait till consumers catch up with producers in all queues */
2029 bnx2x_drain_tx_queues(sc);
2031 /* if VF indicate to PF this function is going down (PF will delete sp
2032 * elements and clear initializations
2035 bnx2x_vf_unload(sc);
2036 } else if (unload_mode != UNLOAD_RECOVERY) {
2037 /* if this is a normal/close unload need to clean up chip */
2038 bnx2x_chip_cleanup(sc, unload_mode, keep_link);
2040 /* Send the UNLOAD_REQUEST to the MCP */
2041 bnx2x_send_unload_req(sc, unload_mode);
2044 * Prevent transactions to host from the functions on the
2045 * engine that doesn't reset global blocks in case of global
2046 * attention once gloabl blocks are reset and gates are opened
2047 * (the engine which leader will perform the recovery
2050 if (!CHIP_IS_E1x(sc)) {
2051 bnx2x_pf_disable(sc);
2054 /* disable HW interrupts */
2055 bnx2x_int_disable_sync(sc, TRUE);
2057 /* Report UNLOAD_DONE to MCP */
2058 bnx2x_send_unload_done(sc, FALSE);
2062 * At this stage no more interrupts will arrive so we may safely clean
2063 * the queue'able objects here in case they failed to get cleaned so far.
2066 bnx2x_squeeze_objects(sc);
2069 /* There should be no more pending SP commands at this stage */
2078 bnx2x_free_fw_stats_mem(sc);
2080 sc->state = BNX2X_STATE_CLOSED;
2083 * Check if there are pending parity attentions. If there are - set
2084 * RECOVERY_IN_PROGRESS.
2086 if (IS_PF(sc) && bnx2x_chk_parity_attn(sc, &global, FALSE)) {
2087 bnx2x_set_reset_in_progress(sc);
2089 /* Set RESET_IS_GLOBAL if needed */
2091 bnx2x_set_reset_global(sc);
2096 * The last driver must disable a "close the gate" if there is no
2097 * parity attention or "process kill" pending.
2099 if (IS_PF(sc) && !bnx2x_clear_pf_load(sc) &&
2100 bnx2x_reset_is_done(sc, SC_PATH(sc))) {
2101 bnx2x_disable_close_the_gate(sc);
2104 PMD_DRV_LOG(DEBUG, "Ended NIC unload");
2110 * Encapsulte an mbuf cluster into the tx bd chain and makes the memory
2111 * visible to the controller.
2113 * If an mbuf is submitted to this routine and cannot be given to the
2114 * controller (e.g. it has too many fragments) then the function may free
2115 * the mbuf and return to the caller.
2118 * int: Number of TX BDs used for the mbuf
2120 * Note the side effect that an mbuf may be freed if it causes a problem.
2122 int bnx2x_tx_encap(struct bnx2x_tx_queue *txq, struct rte_mbuf *m0)
2124 struct eth_tx_start_bd *tx_start_bd;
2125 uint16_t bd_prod, pkt_prod;
2126 struct bnx2x_softc *sc;
2130 bd_prod = txq->tx_bd_tail;
2131 pkt_prod = txq->tx_pkt_tail;
2133 txq->sw_ring[TX_BD(pkt_prod, txq)] = m0;
2135 tx_start_bd = &txq->tx_ring[TX_BD(bd_prod, txq)].start_bd;
2138 rte_cpu_to_le_64(rte_mbuf_data_iova(m0));
2139 tx_start_bd->nbytes = rte_cpu_to_le_16(m0->data_len);
2140 tx_start_bd->bd_flags.as_bitfield = ETH_TX_BD_FLAGS_START_BD;
2141 tx_start_bd->general_data =
2142 (1 << ETH_TX_START_BD_HDR_NBDS_SHIFT);
2144 tx_start_bd->nbd = rte_cpu_to_le_16(2);
2146 if (m0->ol_flags & PKT_TX_VLAN_PKT) {
2147 tx_start_bd->vlan_or_ethertype =
2148 rte_cpu_to_le_16(m0->vlan_tci);
2149 tx_start_bd->bd_flags.as_bitfield |=
2150 (X_ETH_OUTBAND_VLAN <<
2151 ETH_TX_BD_FLAGS_VLAN_MODE_SHIFT);
2154 tx_start_bd->vlan_or_ethertype =
2155 rte_cpu_to_le_16(pkt_prod);
2157 struct ether_hdr *eh =
2158 rte_pktmbuf_mtod(m0, struct ether_hdr *);
2160 tx_start_bd->vlan_or_ethertype =
2161 rte_cpu_to_le_16(rte_be_to_cpu_16(eh->ether_type));
2165 bd_prod = NEXT_TX_BD(bd_prod);
2167 struct eth_tx_parse_bd_e2 *tx_parse_bd;
2168 const struct ether_hdr *eh =
2169 rte_pktmbuf_mtod(m0, struct ether_hdr *);
2170 uint8_t mac_type = UNICAST_ADDRESS;
2173 &txq->tx_ring[TX_BD(bd_prod, txq)].parse_bd_e2;
2174 if (is_multicast_ether_addr(&eh->d_addr)) {
2175 if (is_broadcast_ether_addr(&eh->d_addr))
2176 mac_type = BROADCAST_ADDRESS;
2178 mac_type = MULTICAST_ADDRESS;
2180 tx_parse_bd->parsing_data =
2181 (mac_type << ETH_TX_PARSE_BD_E2_ETH_ADDR_TYPE_SHIFT);
2183 rte_memcpy(&tx_parse_bd->data.mac_addr.dst_hi,
2184 &eh->d_addr.addr_bytes[0], 2);
2185 rte_memcpy(&tx_parse_bd->data.mac_addr.dst_mid,
2186 &eh->d_addr.addr_bytes[2], 2);
2187 rte_memcpy(&tx_parse_bd->data.mac_addr.dst_lo,
2188 &eh->d_addr.addr_bytes[4], 2);
2189 rte_memcpy(&tx_parse_bd->data.mac_addr.src_hi,
2190 &eh->s_addr.addr_bytes[0], 2);
2191 rte_memcpy(&tx_parse_bd->data.mac_addr.src_mid,
2192 &eh->s_addr.addr_bytes[2], 2);
2193 rte_memcpy(&tx_parse_bd->data.mac_addr.src_lo,
2194 &eh->s_addr.addr_bytes[4], 2);
2196 tx_parse_bd->data.mac_addr.dst_hi =
2197 rte_cpu_to_be_16(tx_parse_bd->data.mac_addr.dst_hi);
2198 tx_parse_bd->data.mac_addr.dst_mid =
2199 rte_cpu_to_be_16(tx_parse_bd->data.
2201 tx_parse_bd->data.mac_addr.dst_lo =
2202 rte_cpu_to_be_16(tx_parse_bd->data.mac_addr.dst_lo);
2203 tx_parse_bd->data.mac_addr.src_hi =
2204 rte_cpu_to_be_16(tx_parse_bd->data.mac_addr.src_hi);
2205 tx_parse_bd->data.mac_addr.src_mid =
2206 rte_cpu_to_be_16(tx_parse_bd->data.
2208 tx_parse_bd->data.mac_addr.src_lo =
2209 rte_cpu_to_be_16(tx_parse_bd->data.mac_addr.src_lo);
2212 "PBD dst %x %x %x src %x %x %x p_data %x",
2213 tx_parse_bd->data.mac_addr.dst_hi,
2214 tx_parse_bd->data.mac_addr.dst_mid,
2215 tx_parse_bd->data.mac_addr.dst_lo,
2216 tx_parse_bd->data.mac_addr.src_hi,
2217 tx_parse_bd->data.mac_addr.src_mid,
2218 tx_parse_bd->data.mac_addr.src_lo,
2219 tx_parse_bd->parsing_data);
2223 "start bd: nbytes %d flags %x vlan %x",
2224 tx_start_bd->nbytes,
2225 tx_start_bd->bd_flags.as_bitfield,
2226 tx_start_bd->vlan_or_ethertype);
2228 bd_prod = NEXT_TX_BD(bd_prod);
2231 if (TX_IDX(bd_prod) < 2)
2234 txq->nb_tx_avail -= 2;
2235 txq->tx_bd_tail = bd_prod;
2236 txq->tx_pkt_tail = pkt_prod;
2241 static uint16_t bnx2x_cid_ilt_lines(struct bnx2x_softc *sc)
2243 return L2_ILT_LINES(sc);
2246 static void bnx2x_ilt_set_info(struct bnx2x_softc *sc)
2248 struct ilt_client_info *ilt_client;
2249 struct ecore_ilt *ilt = sc->ilt;
2252 PMD_INIT_FUNC_TRACE();
2254 ilt->start_line = FUNC_ILT_BASE(SC_FUNC(sc));
2257 ilt_client = &ilt->clients[ILT_CLIENT_CDU];
2258 ilt_client->client_num = ILT_CLIENT_CDU;
2259 ilt_client->page_size = CDU_ILT_PAGE_SZ;
2260 ilt_client->flags = ILT_CLIENT_SKIP_MEM;
2261 ilt_client->start = line;
2262 line += bnx2x_cid_ilt_lines(sc);
2264 if (CNIC_SUPPORT(sc)) {
2265 line += CNIC_ILT_LINES;
2268 ilt_client->end = (line - 1);
2271 if (QM_INIT(sc->qm_cid_count)) {
2272 ilt_client = &ilt->clients[ILT_CLIENT_QM];
2273 ilt_client->client_num = ILT_CLIENT_QM;
2274 ilt_client->page_size = QM_ILT_PAGE_SZ;
2275 ilt_client->flags = 0;
2276 ilt_client->start = line;
2278 /* 4 bytes for each cid */
2279 line += DIV_ROUND_UP(sc->qm_cid_count * QM_QUEUES_PER_FUNC * 4,
2282 ilt_client->end = (line - 1);
2285 if (CNIC_SUPPORT(sc)) {
2287 ilt_client = &ilt->clients[ILT_CLIENT_SRC];
2288 ilt_client->client_num = ILT_CLIENT_SRC;
2289 ilt_client->page_size = SRC_ILT_PAGE_SZ;
2290 ilt_client->flags = 0;
2291 ilt_client->start = line;
2292 line += SRC_ILT_LINES;
2293 ilt_client->end = (line - 1);
2296 ilt_client = &ilt->clients[ILT_CLIENT_TM];
2297 ilt_client->client_num = ILT_CLIENT_TM;
2298 ilt_client->page_size = TM_ILT_PAGE_SZ;
2299 ilt_client->flags = 0;
2300 ilt_client->start = line;
2301 line += TM_ILT_LINES;
2302 ilt_client->end = (line - 1);
2305 assert((line <= ILT_MAX_LINES));
2308 static void bnx2x_set_fp_rx_buf_size(struct bnx2x_softc *sc)
2312 for (i = 0; i < sc->num_queues; i++) {
2313 /* get the Rx buffer size for RX frames */
2314 sc->fp[i].rx_buf_size =
2315 (IP_HEADER_ALIGNMENT_PADDING + ETH_OVERHEAD + sc->mtu);
2319 int bnx2x_alloc_ilt_mem(struct bnx2x_softc *sc)
2322 sc->ilt = rte_malloc("", sizeof(struct ecore_ilt), RTE_CACHE_LINE_SIZE);
2324 return sc->ilt == NULL;
2327 static int bnx2x_alloc_ilt_lines_mem(struct bnx2x_softc *sc)
2329 sc->ilt->lines = rte_calloc("",
2330 sizeof(struct ilt_line), ILT_MAX_LINES,
2331 RTE_CACHE_LINE_SIZE);
2332 return sc->ilt->lines == NULL;
2335 void bnx2x_free_ilt_mem(struct bnx2x_softc *sc)
2341 static void bnx2x_free_ilt_lines_mem(struct bnx2x_softc *sc)
2343 if (sc->ilt->lines != NULL) {
2344 rte_free(sc->ilt->lines);
2345 sc->ilt->lines = NULL;
2349 static void bnx2x_free_mem(struct bnx2x_softc *sc)
2353 for (i = 0; i < L2_ILT_LINES(sc); i++) {
2354 sc->context[i].vcxt = NULL;
2355 sc->context[i].size = 0;
2358 ecore_ilt_mem_op(sc, ILT_MEMOP_FREE);
2360 bnx2x_free_ilt_lines_mem(sc);
2363 static int bnx2x_alloc_mem(struct bnx2x_softc *sc)
2368 char cdu_name[RTE_MEMZONE_NAMESIZE];
2371 * Allocate memory for CDU context:
2372 * This memory is allocated separately and not in the generic ILT
2373 * functions because CDU differs in few aspects:
2374 * 1. There can be multiple entities allocating memory for context -
2375 * regular L2, CNIC, and SRIOV drivers. Each separately controls
2376 * its own ILT lines.
2377 * 2. Since CDU page-size is not a single 4KB page (which is the case
2378 * for the other ILT clients), to be efficient we want to support
2379 * allocation of sub-page-size in the last entry.
2380 * 3. Context pointers are used by the driver to pass to FW / update
2381 * the context (for the other ILT clients the pointers are used just to
2382 * free the memory during unload).
2384 context_size = (sizeof(union cdu_context) * BNX2X_L2_CID_COUNT(sc));
2385 for (i = 0, allocated = 0; allocated < context_size; i++) {
2386 sc->context[i].size = min(CDU_ILT_PAGE_SZ,
2387 (context_size - allocated));
2389 snprintf(cdu_name, sizeof(cdu_name), "cdu_%d", i);
2390 if (bnx2x_dma_alloc(sc, sc->context[i].size,
2391 &sc->context[i].vcxt_dma,
2392 cdu_name, BNX2X_PAGE_SIZE) != 0) {
2397 sc->context[i].vcxt =
2398 (union cdu_context *)sc->context[i].vcxt_dma.vaddr;
2400 allocated += sc->context[i].size;
2403 bnx2x_alloc_ilt_lines_mem(sc);
2405 if (ecore_ilt_mem_op(sc, ILT_MEMOP_ALLOC)) {
2406 PMD_DRV_LOG(NOTICE, "ecore_ilt_mem_op ILT_MEMOP_ALLOC failed");
2414 static void bnx2x_free_fw_stats_mem(struct bnx2x_softc *sc)
2416 sc->fw_stats_num = 0;
2418 sc->fw_stats_req_size = 0;
2419 sc->fw_stats_req = NULL;
2420 sc->fw_stats_req_mapping = 0;
2422 sc->fw_stats_data_size = 0;
2423 sc->fw_stats_data = NULL;
2424 sc->fw_stats_data_mapping = 0;
2427 static int bnx2x_alloc_fw_stats_mem(struct bnx2x_softc *sc)
2429 uint8_t num_queue_stats;
2430 int num_groups, vf_headroom = 0;
2432 /* number of queues for statistics is number of eth queues */
2433 num_queue_stats = BNX2X_NUM_ETH_QUEUES(sc);
2436 * Total number of FW statistics requests =
2437 * 1 for port stats + 1 for PF stats + num of queues
2439 sc->fw_stats_num = (2 + num_queue_stats);
2442 * Request is built from stats_query_header and an array of
2443 * stats_query_cmd_group each of which contains STATS_QUERY_CMD_COUNT
2444 * rules. The real number or requests is configured in the
2445 * stats_query_header.
2447 num_groups = (sc->fw_stats_num + vf_headroom) / STATS_QUERY_CMD_COUNT;
2448 if ((sc->fw_stats_num + vf_headroom) % STATS_QUERY_CMD_COUNT)
2451 sc->fw_stats_req_size =
2452 (sizeof(struct stats_query_header) +
2453 (num_groups * sizeof(struct stats_query_cmd_group)));
2456 * Data for statistics requests + stats_counter.
2457 * stats_counter holds per-STORM counters that are incremented when
2458 * STORM has finished with the current request. Memory for FCoE
2459 * offloaded statistics are counted anyway, even if they will not be sent.
2460 * VF stats are not accounted for here as the data of VF stats is stored
2461 * in memory allocated by the VF, not here.
2463 sc->fw_stats_data_size =
2464 (sizeof(struct stats_counter) +
2465 sizeof(struct per_port_stats) + sizeof(struct per_pf_stats) +
2466 /* sizeof(struct fcoe_statistics_params) + */
2467 (sizeof(struct per_queue_stats) * num_queue_stats));
2469 if (bnx2x_dma_alloc(sc, (sc->fw_stats_req_size + sc->fw_stats_data_size),
2470 &sc->fw_stats_dma, "fw_stats",
2471 RTE_CACHE_LINE_SIZE) != 0) {
2472 bnx2x_free_fw_stats_mem(sc);
2476 /* set up the shortcuts */
2478 sc->fw_stats_req = (struct bnx2x_fw_stats_req *)sc->fw_stats_dma.vaddr;
2479 sc->fw_stats_req_mapping = sc->fw_stats_dma.paddr;
2482 (struct bnx2x_fw_stats_data *)((uint8_t *) sc->fw_stats_dma.vaddr +
2483 sc->fw_stats_req_size);
2484 sc->fw_stats_data_mapping = (sc->fw_stats_dma.paddr +
2485 sc->fw_stats_req_size);
2492 * 0-7 - Engine0 load counter.
2493 * 8-15 - Engine1 load counter.
2494 * 16 - Engine0 RESET_IN_PROGRESS bit.
2495 * 17 - Engine1 RESET_IN_PROGRESS bit.
2496 * 18 - Engine0 ONE_IS_LOADED. Set when there is at least one active
2497 * function on the engine
2498 * 19 - Engine1 ONE_IS_LOADED.
2499 * 20 - Chip reset flow bit. When set none-leader must wait for both engines
2500 * leader to complete (check for both RESET_IN_PROGRESS bits and not
2501 * for just the one belonging to its engine).
2503 #define BNX2X_RECOVERY_GLOB_REG MISC_REG_GENERIC_POR_1
2504 #define BNX2X_PATH0_LOAD_CNT_MASK 0x000000ff
2505 #define BNX2X_PATH0_LOAD_CNT_SHIFT 0
2506 #define BNX2X_PATH1_LOAD_CNT_MASK 0x0000ff00
2507 #define BNX2X_PATH1_LOAD_CNT_SHIFT 8
2508 #define BNX2X_PATH0_RST_IN_PROG_BIT 0x00010000
2509 #define BNX2X_PATH1_RST_IN_PROG_BIT 0x00020000
2510 #define BNX2X_GLOBAL_RESET_BIT 0x00040000
2512 /* set the GLOBAL_RESET bit, should be run under rtnl lock */
2513 static void bnx2x_set_reset_global(struct bnx2x_softc *sc)
2516 bnx2x_acquire_hw_lock(sc, HW_LOCK_RESOURCE_RECOVERY_REG);
2517 val = REG_RD(sc, BNX2X_RECOVERY_GLOB_REG);
2518 REG_WR(sc, BNX2X_RECOVERY_GLOB_REG, val | BNX2X_GLOBAL_RESET_BIT);
2519 bnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_RECOVERY_REG);
2522 /* clear the GLOBAL_RESET bit, should be run under rtnl lock */
2523 static void bnx2x_clear_reset_global(struct bnx2x_softc *sc)
2526 bnx2x_acquire_hw_lock(sc, HW_LOCK_RESOURCE_RECOVERY_REG);
2527 val = REG_RD(sc, BNX2X_RECOVERY_GLOB_REG);
2528 REG_WR(sc, BNX2X_RECOVERY_GLOB_REG, val & (~BNX2X_GLOBAL_RESET_BIT));
2529 bnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_RECOVERY_REG);
2532 /* checks the GLOBAL_RESET bit, should be run under rtnl lock */
2533 static uint8_t bnx2x_reset_is_global(struct bnx2x_softc *sc)
2535 return REG_RD(sc, BNX2X_RECOVERY_GLOB_REG) & BNX2X_GLOBAL_RESET_BIT;
2538 /* clear RESET_IN_PROGRESS bit for the engine, should be run under rtnl lock */
2539 static void bnx2x_set_reset_done(struct bnx2x_softc *sc)
2542 uint32_t bit = SC_PATH(sc) ? BNX2X_PATH1_RST_IN_PROG_BIT :
2543 BNX2X_PATH0_RST_IN_PROG_BIT;
2545 bnx2x_acquire_hw_lock(sc, HW_LOCK_RESOURCE_RECOVERY_REG);
2547 val = REG_RD(sc, BNX2X_RECOVERY_GLOB_REG);
2550 REG_WR(sc, BNX2X_RECOVERY_GLOB_REG, val);
2552 bnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_RECOVERY_REG);
2555 /* set RESET_IN_PROGRESS for the engine, should be run under rtnl lock */
2556 static void bnx2x_set_reset_in_progress(struct bnx2x_softc *sc)
2559 uint32_t bit = SC_PATH(sc) ? BNX2X_PATH1_RST_IN_PROG_BIT :
2560 BNX2X_PATH0_RST_IN_PROG_BIT;
2562 bnx2x_acquire_hw_lock(sc, HW_LOCK_RESOURCE_RECOVERY_REG);
2564 val = REG_RD(sc, BNX2X_RECOVERY_GLOB_REG);
2567 REG_WR(sc, BNX2X_RECOVERY_GLOB_REG, val);
2569 bnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_RECOVERY_REG);
2572 /* check RESET_IN_PROGRESS bit for an engine, should be run under rtnl lock */
2573 static uint8_t bnx2x_reset_is_done(struct bnx2x_softc *sc, int engine)
2575 uint32_t val = REG_RD(sc, BNX2X_RECOVERY_GLOB_REG);
2576 uint32_t bit = engine ? BNX2X_PATH1_RST_IN_PROG_BIT :
2577 BNX2X_PATH0_RST_IN_PROG_BIT;
2579 /* return false if bit is set */
2580 return (val & bit) ? FALSE : TRUE;
2583 /* get the load status for an engine, should be run under rtnl lock */
2584 static uint8_t bnx2x_get_load_status(struct bnx2x_softc *sc, int engine)
2586 uint32_t mask = engine ? BNX2X_PATH1_LOAD_CNT_MASK :
2587 BNX2X_PATH0_LOAD_CNT_MASK;
2588 uint32_t shift = engine ? BNX2X_PATH1_LOAD_CNT_SHIFT :
2589 BNX2X_PATH0_LOAD_CNT_SHIFT;
2590 uint32_t val = REG_RD(sc, BNX2X_RECOVERY_GLOB_REG);
2592 val = ((val & mask) >> shift);
2597 /* set pf load mark */
2598 static void bnx2x_set_pf_load(struct bnx2x_softc *sc)
2602 uint32_t mask = SC_PATH(sc) ? BNX2X_PATH1_LOAD_CNT_MASK :
2603 BNX2X_PATH0_LOAD_CNT_MASK;
2604 uint32_t shift = SC_PATH(sc) ? BNX2X_PATH1_LOAD_CNT_SHIFT :
2605 BNX2X_PATH0_LOAD_CNT_SHIFT;
2607 bnx2x_acquire_hw_lock(sc, HW_LOCK_RESOURCE_RECOVERY_REG);
2609 PMD_INIT_FUNC_TRACE();
2611 val = REG_RD(sc, BNX2X_RECOVERY_GLOB_REG);
2613 /* get the current counter value */
2614 val1 = ((val & mask) >> shift);
2616 /* set bit of this PF */
2617 val1 |= (1 << SC_ABS_FUNC(sc));
2619 /* clear the old value */
2622 /* set the new one */
2623 val |= ((val1 << shift) & mask);
2625 REG_WR(sc, BNX2X_RECOVERY_GLOB_REG, val);
2627 bnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_RECOVERY_REG);
2630 /* clear pf load mark */
2631 static uint8_t bnx2x_clear_pf_load(struct bnx2x_softc *sc)
2634 uint32_t mask = SC_PATH(sc) ? BNX2X_PATH1_LOAD_CNT_MASK :
2635 BNX2X_PATH0_LOAD_CNT_MASK;
2636 uint32_t shift = SC_PATH(sc) ? BNX2X_PATH1_LOAD_CNT_SHIFT :
2637 BNX2X_PATH0_LOAD_CNT_SHIFT;
2639 bnx2x_acquire_hw_lock(sc, HW_LOCK_RESOURCE_RECOVERY_REG);
2640 val = REG_RD(sc, BNX2X_RECOVERY_GLOB_REG);
2642 /* get the current counter value */
2643 val1 = (val & mask) >> shift;
2645 /* clear bit of that PF */
2646 val1 &= ~(1 << SC_ABS_FUNC(sc));
2648 /* clear the old value */
2651 /* set the new one */
2652 val |= ((val1 << shift) & mask);
2654 REG_WR(sc, BNX2X_RECOVERY_GLOB_REG, val);
2655 bnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_RECOVERY_REG);
2659 /* send load requrest to mcp and analyze response */
2660 static int bnx2x_nic_load_request(struct bnx2x_softc *sc, uint32_t * load_code)
2662 PMD_INIT_FUNC_TRACE();
2666 (SHMEM_RD(sc, func_mb[SC_FW_MB_IDX(sc)].drv_mb_header) &
2667 DRV_MSG_SEQ_NUMBER_MASK);
2669 PMD_DRV_LOG(DEBUG, "initial fw_seq 0x%04x", sc->fw_seq);
2672 /* get the current FW pulse sequence */
2673 sc->fw_drv_pulse_wr_seq =
2674 (SHMEM_RD(sc, func_mb[SC_FW_MB_IDX(sc)].drv_pulse_mb) &
2675 DRV_PULSE_SEQ_MASK);
2677 /* set ALWAYS_ALIVE bit in shmem */
2678 sc->fw_drv_pulse_wr_seq |= DRV_PULSE_ALWAYS_ALIVE;
2679 bnx2x_drv_pulse(sc);
2683 (*load_code) = bnx2x_fw_command(sc, DRV_MSG_CODE_LOAD_REQ,
2684 DRV_MSG_CODE_LOAD_REQ_WITH_LFA);
2686 /* if the MCP fails to respond we must abort */
2687 if (!(*load_code)) {
2688 PMD_DRV_LOG(NOTICE, "MCP response failure!");
2692 /* if MCP refused then must abort */
2693 if ((*load_code) == FW_MSG_CODE_DRV_LOAD_REFUSED) {
2694 PMD_DRV_LOG(NOTICE, "MCP refused load request");
2702 * Check whether another PF has already loaded FW to chip. In virtualized
2703 * environments a pf from anoth VM may have already initialized the device
2704 * including loading FW.
2706 static int bnx2x_nic_load_analyze_req(struct bnx2x_softc *sc, uint32_t load_code)
2708 uint32_t my_fw, loaded_fw;
2710 /* is another pf loaded on this engine? */
2711 if ((load_code != FW_MSG_CODE_DRV_LOAD_COMMON_CHIP) &&
2712 (load_code != FW_MSG_CODE_DRV_LOAD_COMMON)) {
2713 /* build my FW version dword */
2714 my_fw = (BNX2X_5710_FW_MAJOR_VERSION +
2715 (BNX2X_5710_FW_MINOR_VERSION << 8) +
2716 (BNX2X_5710_FW_REVISION_VERSION << 16) +
2717 (BNX2X_5710_FW_ENGINEERING_VERSION << 24));
2719 /* read loaded FW from chip */
2720 loaded_fw = REG_RD(sc, XSEM_REG_PRAM);
2721 PMD_DRV_LOG(DEBUG, "loaded FW 0x%08x / my FW 0x%08x",
2724 /* abort nic load if version mismatch */
2725 if (my_fw != loaded_fw) {
2727 "FW 0x%08x already loaded (mine is 0x%08x)",
2736 /* mark PMF if applicable */
2737 static void bnx2x_nic_load_pmf(struct bnx2x_softc *sc, uint32_t load_code)
2739 uint32_t ncsi_oem_data_addr;
2741 PMD_INIT_FUNC_TRACE();
2743 if ((load_code == FW_MSG_CODE_DRV_LOAD_COMMON) ||
2744 (load_code == FW_MSG_CODE_DRV_LOAD_COMMON_CHIP) ||
2745 (load_code == FW_MSG_CODE_DRV_LOAD_PORT)) {
2747 * Barrier here for ordering between the writing to sc->port.pmf here
2748 * and reading it from the periodic task.
2756 PMD_DRV_LOG(DEBUG, "pmf %d", sc->port.pmf);
2758 if (load_code == FW_MSG_CODE_DRV_LOAD_COMMON_CHIP) {
2759 if (SHMEM2_HAS(sc, ncsi_oem_data_addr)) {
2760 ncsi_oem_data_addr = SHMEM2_RD(sc, ncsi_oem_data_addr);
2761 if (ncsi_oem_data_addr) {
2763 (ncsi_oem_data_addr +
2764 offsetof(struct glob_ncsi_oem_data,
2765 driver_version)), 0);
2771 static void bnx2x_read_mf_cfg(struct bnx2x_softc *sc)
2773 int n = (CHIP_IS_MODE_4_PORT(sc) ? 2 : 1);
2777 if (BNX2X_NOMCP(sc)) {
2778 return; /* what should be the default bvalue in this case */
2782 * The formula for computing the absolute function number is...
2783 * For 2 port configuration (4 functions per port):
2784 * abs_func = 2 * vn + SC_PORT + SC_PATH
2785 * For 4 port configuration (2 functions per port):
2786 * abs_func = 4 * vn + 2 * SC_PORT + SC_PATH
2788 for (vn = VN_0; vn < SC_MAX_VN_NUM(sc); vn++) {
2789 abs_func = (n * (2 * vn + SC_PORT(sc)) + SC_PATH(sc));
2790 if (abs_func >= E1H_FUNC_MAX) {
2793 sc->devinfo.mf_info.mf_config[vn] =
2794 MFCFG_RD(sc, func_mf_config[abs_func].config);
2797 if (sc->devinfo.mf_info.mf_config[SC_VN(sc)] &
2798 FUNC_MF_CFG_FUNC_DISABLED) {
2799 PMD_DRV_LOG(DEBUG, "mf_cfg function disabled");
2800 sc->flags |= BNX2X_MF_FUNC_DIS;
2802 PMD_DRV_LOG(DEBUG, "mf_cfg function enabled");
2803 sc->flags &= ~BNX2X_MF_FUNC_DIS;
2807 /* acquire split MCP access lock register */
2808 static int bnx2x_acquire_alr(struct bnx2x_softc *sc)
2812 for (j = 0; j < 1000; j++) {
2814 REG_WR(sc, GRCBASE_MCP + 0x9c, val);
2815 val = REG_RD(sc, GRCBASE_MCP + 0x9c);
2816 if (val & (1L << 31))
2822 if (!(val & (1L << 31))) {
2823 PMD_DRV_LOG(NOTICE, "Cannot acquire MCP access lock register");
2830 /* release split MCP access lock register */
2831 static void bnx2x_release_alr(struct bnx2x_softc *sc)
2833 REG_WR(sc, GRCBASE_MCP + 0x9c, 0);
2836 static void bnx2x_fan_failure(struct bnx2x_softc *sc)
2838 int port = SC_PORT(sc);
2839 uint32_t ext_phy_config;
2841 /* mark the failure */
2843 SHMEM_RD(sc, dev_info.port_hw_config[port].external_phy_config);
2845 ext_phy_config &= ~PORT_HW_CFG_XGXS_EXT_PHY_TYPE_MASK;
2846 ext_phy_config |= PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE;
2847 SHMEM_WR(sc, dev_info.port_hw_config[port].external_phy_config,
2850 /* log the failure */
2852 "Fan Failure has caused the driver to shutdown "
2853 "the card to prevent permanent damage. "
2854 "Please contact OEM Support for assistance");
2856 rte_panic("Schedule task to handle fan failure");
2859 /* this function is called upon a link interrupt */
2860 static void bnx2x_link_attn(struct bnx2x_softc *sc)
2862 uint32_t pause_enabled = 0;
2863 struct host_port_stats *pstats;
2866 /* Make sure that we are synced with the current statistics */
2867 bnx2x_stats_handle(sc, STATS_EVENT_STOP);
2869 elink_link_update(&sc->link_params, &sc->link_vars);
2871 if (sc->link_vars.link_up) {
2873 /* dropless flow control */
2874 if (sc->dropless_fc) {
2877 if (sc->link_vars.flow_ctrl & ELINK_FLOW_CTRL_TX) {
2882 (BAR_USTRORM_INTMEM +
2883 USTORM_ETH_PAUSE_ENABLED_OFFSET(SC_PORT(sc))),
2887 if (sc->link_vars.mac_type != ELINK_MAC_TYPE_EMAC) {
2888 pstats = BNX2X_SP(sc, port_stats);
2889 /* reset old mac stats */
2890 memset(&(pstats->mac_stx[0]), 0,
2891 sizeof(struct mac_stx));
2894 if (sc->state == BNX2X_STATE_OPEN) {
2895 bnx2x_stats_handle(sc, STATS_EVENT_LINK_UP);
2899 if (sc->link_vars.link_up && sc->link_vars.line_speed) {
2900 cmng_fns = bnx2x_get_cmng_fns_mode(sc);
2902 if (cmng_fns != CMNG_FNS_NONE) {
2903 bnx2x_cmng_fns_init(sc, FALSE, cmng_fns);
2904 storm_memset_cmng(sc, &sc->cmng, SC_PORT(sc));
2908 bnx2x_link_report(sc);
2911 bnx2x_link_sync_notify(sc);
2915 static void bnx2x_attn_int_asserted(struct bnx2x_softc *sc, uint32_t asserted)
2917 int port = SC_PORT(sc);
2918 uint32_t aeu_addr = port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 :
2919 MISC_REG_AEU_MASK_ATTN_FUNC_0;
2920 uint32_t nig_int_mask_addr = port ? NIG_REG_MASK_INTERRUPT_PORT1 :
2921 NIG_REG_MASK_INTERRUPT_PORT0;
2923 uint32_t nig_mask = 0;
2928 if (sc->attn_state & asserted) {
2929 PMD_DRV_LOG(ERR, "IGU ERROR attn=0x%08x", asserted);
2932 bnx2x_acquire_hw_lock(sc, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
2934 aeu_mask = REG_RD(sc, aeu_addr);
2936 aeu_mask &= ~(asserted & 0x3ff);
2938 REG_WR(sc, aeu_addr, aeu_mask);
2940 bnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
2942 sc->attn_state |= asserted;
2944 if (asserted & ATTN_HARD_WIRED_MASK) {
2945 if (asserted & ATTN_NIG_FOR_FUNC) {
2947 /* save nig interrupt mask */
2948 nig_mask = REG_RD(sc, nig_int_mask_addr);
2950 /* If nig_mask is not set, no need to call the update function */
2952 REG_WR(sc, nig_int_mask_addr, 0);
2954 bnx2x_link_attn(sc);
2957 /* handle unicore attn? */
2960 if (asserted & ATTN_SW_TIMER_4_FUNC) {
2961 PMD_DRV_LOG(DEBUG, "ATTN_SW_TIMER_4_FUNC!");
2964 if (asserted & GPIO_2_FUNC) {
2965 PMD_DRV_LOG(DEBUG, "GPIO_2_FUNC!");
2968 if (asserted & GPIO_3_FUNC) {
2969 PMD_DRV_LOG(DEBUG, "GPIO_3_FUNC!");
2972 if (asserted & GPIO_4_FUNC) {
2973 PMD_DRV_LOG(DEBUG, "GPIO_4_FUNC!");
2977 if (asserted & ATTN_GENERAL_ATTN_1) {
2978 PMD_DRV_LOG(DEBUG, "ATTN_GENERAL_ATTN_1!");
2979 REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_1, 0x0);
2981 if (asserted & ATTN_GENERAL_ATTN_2) {
2982 PMD_DRV_LOG(DEBUG, "ATTN_GENERAL_ATTN_2!");
2983 REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_2, 0x0);
2985 if (asserted & ATTN_GENERAL_ATTN_3) {
2986 PMD_DRV_LOG(DEBUG, "ATTN_GENERAL_ATTN_3!");
2987 REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_3, 0x0);
2990 if (asserted & ATTN_GENERAL_ATTN_4) {
2991 PMD_DRV_LOG(DEBUG, "ATTN_GENERAL_ATTN_4!");
2992 REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_4, 0x0);
2994 if (asserted & ATTN_GENERAL_ATTN_5) {
2995 PMD_DRV_LOG(DEBUG, "ATTN_GENERAL_ATTN_5!");
2996 REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_5, 0x0);
2998 if (asserted & ATTN_GENERAL_ATTN_6) {
2999 PMD_DRV_LOG(DEBUG, "ATTN_GENERAL_ATTN_6!");
3000 REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_6, 0x0);
3005 if (sc->devinfo.int_block == INT_BLOCK_HC) {
3007 (HC_REG_COMMAND_REG + port * 32 +
3008 COMMAND_REG_ATTN_BITS_SET);
3010 reg_addr = (BAR_IGU_INTMEM + IGU_CMD_ATTN_BIT_SET_UPPER * 8);
3013 PMD_DRV_LOG(DEBUG, "about to mask 0x%08x at %s addr 0x%08x",
3015 (sc->devinfo.int_block == INT_BLOCK_HC) ? "HC" : "IGU",
3017 REG_WR(sc, reg_addr, asserted);
3019 /* now set back the mask */
3020 if (asserted & ATTN_NIG_FOR_FUNC) {
3022 * Verify that IGU ack through BAR was written before restoring
3023 * NIG mask. This loop should exit after 2-3 iterations max.
3025 if (sc->devinfo.int_block != INT_BLOCK_HC) {
3030 REG_RD(sc, IGU_REG_ATTENTION_ACK_BITS);
3031 } while (((igu_acked & ATTN_NIG_FOR_FUNC) == 0)
3032 && (++cnt < MAX_IGU_ATTN_ACK_TO));
3036 "Failed to verify IGU ack on time");
3042 REG_WR(sc, nig_int_mask_addr, nig_mask);
3048 bnx2x_print_next_block(__rte_unused struct bnx2x_softc *sc, __rte_unused int idx,
3049 __rte_unused const char *blk)
3051 PMD_DRV_LOG(INFO, "%s%s", idx ? ", " : "", blk);
3055 bnx2x_check_blocks_with_parity0(struct bnx2x_softc *sc, uint32_t sig, int par_num,
3058 uint32_t cur_bit = 0;
3061 for (i = 0; sig; i++) {
3062 cur_bit = ((uint32_t) 0x1 << i);
3063 if (sig & cur_bit) {
3065 case AEU_INPUTS_ATTN_BITS_BRB_PARITY_ERROR:
3067 bnx2x_print_next_block(sc, par_num++,
3070 case AEU_INPUTS_ATTN_BITS_PARSER_PARITY_ERROR:
3072 bnx2x_print_next_block(sc, par_num++,
3075 case AEU_INPUTS_ATTN_BITS_TSDM_PARITY_ERROR:
3077 bnx2x_print_next_block(sc, par_num++,
3080 case AEU_INPUTS_ATTN_BITS_SEARCHER_PARITY_ERROR:
3082 bnx2x_print_next_block(sc, par_num++,
3085 case AEU_INPUTS_ATTN_BITS_TCM_PARITY_ERROR:
3087 bnx2x_print_next_block(sc, par_num++,
3090 case AEU_INPUTS_ATTN_BITS_TSEMI_PARITY_ERROR:
3092 bnx2x_print_next_block(sc, par_num++,
3095 case AEU_INPUTS_ATTN_BITS_PBCLIENT_PARITY_ERROR:
3097 bnx2x_print_next_block(sc, par_num++,
3111 bnx2x_check_blocks_with_parity1(struct bnx2x_softc *sc, uint32_t sig, int par_num,
3112 uint8_t * global, uint8_t print)
3115 uint32_t cur_bit = 0;
3116 for (i = 0; sig; i++) {
3117 cur_bit = ((uint32_t) 0x1 << i);
3118 if (sig & cur_bit) {
3120 case AEU_INPUTS_ATTN_BITS_PBF_PARITY_ERROR:
3122 bnx2x_print_next_block(sc, par_num++,
3125 case AEU_INPUTS_ATTN_BITS_QM_PARITY_ERROR:
3127 bnx2x_print_next_block(sc, par_num++,
3130 case AEU_INPUTS_ATTN_BITS_TIMERS_PARITY_ERROR:
3132 bnx2x_print_next_block(sc, par_num++,
3135 case AEU_INPUTS_ATTN_BITS_XSDM_PARITY_ERROR:
3137 bnx2x_print_next_block(sc, par_num++,
3140 case AEU_INPUTS_ATTN_BITS_XCM_PARITY_ERROR:
3142 bnx2x_print_next_block(sc, par_num++,
3145 case AEU_INPUTS_ATTN_BITS_XSEMI_PARITY_ERROR:
3147 bnx2x_print_next_block(sc, par_num++,
3150 case AEU_INPUTS_ATTN_BITS_DOORBELLQ_PARITY_ERROR:
3152 bnx2x_print_next_block(sc, par_num++,
3155 case AEU_INPUTS_ATTN_BITS_NIG_PARITY_ERROR:
3157 bnx2x_print_next_block(sc, par_num++,
3160 case AEU_INPUTS_ATTN_BITS_VAUX_PCI_CORE_PARITY_ERROR:
3162 bnx2x_print_next_block(sc, par_num++,
3166 case AEU_INPUTS_ATTN_BITS_DEBUG_PARITY_ERROR:
3168 bnx2x_print_next_block(sc, par_num++,
3171 case AEU_INPUTS_ATTN_BITS_USDM_PARITY_ERROR:
3173 bnx2x_print_next_block(sc, par_num++,
3176 case AEU_INPUTS_ATTN_BITS_UCM_PARITY_ERROR:
3178 bnx2x_print_next_block(sc, par_num++,
3181 case AEU_INPUTS_ATTN_BITS_USEMI_PARITY_ERROR:
3183 bnx2x_print_next_block(sc, par_num++,
3186 case AEU_INPUTS_ATTN_BITS_UPB_PARITY_ERROR:
3188 bnx2x_print_next_block(sc, par_num++,
3191 case AEU_INPUTS_ATTN_BITS_CSDM_PARITY_ERROR:
3193 bnx2x_print_next_block(sc, par_num++,
3196 case AEU_INPUTS_ATTN_BITS_CCM_PARITY_ERROR:
3198 bnx2x_print_next_block(sc, par_num++,
3212 bnx2x_check_blocks_with_parity2(struct bnx2x_softc *sc, uint32_t sig, int par_num,
3215 uint32_t cur_bit = 0;
3218 for (i = 0; sig; i++) {
3219 cur_bit = ((uint32_t) 0x1 << i);
3220 if (sig & cur_bit) {
3222 case AEU_INPUTS_ATTN_BITS_CSEMI_PARITY_ERROR:
3224 bnx2x_print_next_block(sc, par_num++,
3227 case AEU_INPUTS_ATTN_BITS_PXP_PARITY_ERROR:
3229 bnx2x_print_next_block(sc, par_num++,
3232 case AEU_IN_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR:
3234 bnx2x_print_next_block(sc, par_num++,
3235 "PXPPCICLOCKCLIENT");
3237 case AEU_INPUTS_ATTN_BITS_CFC_PARITY_ERROR:
3239 bnx2x_print_next_block(sc, par_num++,
3242 case AEU_INPUTS_ATTN_BITS_CDU_PARITY_ERROR:
3244 bnx2x_print_next_block(sc, par_num++,
3247 case AEU_INPUTS_ATTN_BITS_DMAE_PARITY_ERROR:
3249 bnx2x_print_next_block(sc, par_num++,
3252 case AEU_INPUTS_ATTN_BITS_IGU_PARITY_ERROR:
3254 bnx2x_print_next_block(sc, par_num++,
3257 case AEU_INPUTS_ATTN_BITS_MISC_PARITY_ERROR:
3259 bnx2x_print_next_block(sc, par_num++,
3273 bnx2x_check_blocks_with_parity3(struct bnx2x_softc *sc, uint32_t sig, int par_num,
3274 uint8_t * global, uint8_t print)
3276 uint32_t cur_bit = 0;
3279 for (i = 0; sig; i++) {
3280 cur_bit = ((uint32_t) 0x1 << i);
3281 if (sig & cur_bit) {
3283 case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_ROM_PARITY:
3285 bnx2x_print_next_block(sc, par_num++,
3289 case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_RX_PARITY:
3291 bnx2x_print_next_block(sc, par_num++,
3295 case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_TX_PARITY:
3297 bnx2x_print_next_block(sc, par_num++,
3301 case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_SCPAD_PARITY:
3303 bnx2x_print_next_block(sc, par_num++,
3318 bnx2x_check_blocks_with_parity4(struct bnx2x_softc *sc, uint32_t sig, int par_num,
3321 uint32_t cur_bit = 0;
3324 for (i = 0; sig; i++) {
3325 cur_bit = ((uint32_t) 0x1 << i);
3326 if (sig & cur_bit) {
3328 case AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR:
3330 bnx2x_print_next_block(sc, par_num++,
3333 case AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR:
3335 bnx2x_print_next_block(sc, par_num++,
3349 bnx2x_parity_attn(struct bnx2x_softc *sc, uint8_t * global, uint8_t print,
3354 if ((sig[0] & HW_PRTY_ASSERT_SET_0) ||
3355 (sig[1] & HW_PRTY_ASSERT_SET_1) ||
3356 (sig[2] & HW_PRTY_ASSERT_SET_2) ||
3357 (sig[3] & HW_PRTY_ASSERT_SET_3) ||
3358 (sig[4] & HW_PRTY_ASSERT_SET_4)) {
3360 "Parity error: HW block parity attention:"
3361 "[0]:0x%08x [1]:0x%08x [2]:0x%08x [3]:0x%08x [4]:0x%08x",
3362 (uint32_t) (sig[0] & HW_PRTY_ASSERT_SET_0),
3363 (uint32_t) (sig[1] & HW_PRTY_ASSERT_SET_1),
3364 (uint32_t) (sig[2] & HW_PRTY_ASSERT_SET_2),
3365 (uint32_t) (sig[3] & HW_PRTY_ASSERT_SET_3),
3366 (uint32_t) (sig[4] & HW_PRTY_ASSERT_SET_4));
3369 PMD_DRV_LOG(INFO, "Parity errors detected in blocks: ");
3372 bnx2x_check_blocks_with_parity0(sc, sig[0] &
3373 HW_PRTY_ASSERT_SET_0,
3376 bnx2x_check_blocks_with_parity1(sc, sig[1] &
3377 HW_PRTY_ASSERT_SET_1,
3378 par_num, global, print);
3380 bnx2x_check_blocks_with_parity2(sc, sig[2] &
3381 HW_PRTY_ASSERT_SET_2,
3384 bnx2x_check_blocks_with_parity3(sc, sig[3] &
3385 HW_PRTY_ASSERT_SET_3,
3386 par_num, global, print);
3388 bnx2x_check_blocks_with_parity4(sc, sig[4] &
3389 HW_PRTY_ASSERT_SET_4,
3393 PMD_DRV_LOG(INFO, "");
3402 bnx2x_chk_parity_attn(struct bnx2x_softc *sc, uint8_t * global, uint8_t print)
3404 struct attn_route attn = { {0} };
3405 int port = SC_PORT(sc);
3407 attn.sig[0] = REG_RD(sc, MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 + port * 4);
3408 attn.sig[1] = REG_RD(sc, MISC_REG_AEU_AFTER_INVERT_2_FUNC_0 + port * 4);
3409 attn.sig[2] = REG_RD(sc, MISC_REG_AEU_AFTER_INVERT_3_FUNC_0 + port * 4);
3410 attn.sig[3] = REG_RD(sc, MISC_REG_AEU_AFTER_INVERT_4_FUNC_0 + port * 4);
3412 if (!CHIP_IS_E1x(sc))
3414 REG_RD(sc, MISC_REG_AEU_AFTER_INVERT_5_FUNC_0 + port * 4);
3416 return bnx2x_parity_attn(sc, global, print, attn.sig);
3419 static void bnx2x_attn_int_deasserted4(struct bnx2x_softc *sc, uint32_t attn)
3423 if (attn & AEU_INPUTS_ATTN_BITS_PGLUE_HW_INTERRUPT) {
3424 val = REG_RD(sc, PGLUE_B_REG_PGLUE_B_INT_STS_CLR);
3425 PMD_DRV_LOG(INFO, "ERROR: PGLUE hw attention 0x%08x", val);
3426 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_ADDRESS_ERROR)
3428 "ERROR: PGLUE_B_PGLUE_B_INT_STS_REG_ADDRESS_ERROR");
3429 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_INCORRECT_RCV_BEHAVIOR)
3431 "ERROR: PGLUE_B_PGLUE_B_INT_STS_REG_INCORRECT_RCV_BEHAVIOR");
3432 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_WAS_ERROR_ATTN)
3434 "ERROR: PGLUE_B_PGLUE_B_INT_STS_REG_WAS_ERROR_ATTN");
3435 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_VF_LENGTH_VIOLATION_ATTN)
3437 "ERROR: PGLUE_B_PGLUE_B_INT_STS_REG_VF_LENGTH_VIOLATION_ATTN");
3439 PGLUE_B_PGLUE_B_INT_STS_REG_VF_GRC_SPACE_VIOLATION_ATTN)
3441 "ERROR: PGLUE_B_PGLUE_B_INT_STS_REG_VF_GRC_SPACE_VIOLATION_ATTN");
3443 PGLUE_B_PGLUE_B_INT_STS_REG_VF_MSIX_BAR_VIOLATION_ATTN)
3445 "ERROR: PGLUE_B_PGLUE_B_INT_STS_REG_VF_MSIX_BAR_VIOLATION_ATTN");
3446 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_ERROR_ATTN)
3448 "ERROR: PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_ERROR_ATTN");
3449 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_IN_TWO_RCBS_ATTN)
3451 "ERROR: PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_IN_TWO_RCBS_ATTN");
3452 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_CSSNOOP_FIFO_OVERFLOW)
3454 "ERROR: PGLUE_B_PGLUE_B_INT_STS_REG_CSSNOOP_FIFO_OVERFLOW");
3457 if (attn & AEU_INPUTS_ATTN_BITS_ATC_HW_INTERRUPT) {
3458 val = REG_RD(sc, ATC_REG_ATC_INT_STS_CLR);
3459 PMD_DRV_LOG(INFO, "ERROR: ATC hw attention 0x%08x", val);
3460 if (val & ATC_ATC_INT_STS_REG_ADDRESS_ERROR)
3462 "ERROR: ATC_ATC_INT_STS_REG_ADDRESS_ERROR");
3463 if (val & ATC_ATC_INT_STS_REG_ATC_TCPL_TO_NOT_PEND)
3465 "ERROR: ATC_ATC_INT_STS_REG_ATC_TCPL_TO_NOT_PEND");
3466 if (val & ATC_ATC_INT_STS_REG_ATC_GPA_MULTIPLE_HITS)
3468 "ERROR: ATC_ATC_INT_STS_REG_ATC_GPA_MULTIPLE_HITS");
3469 if (val & ATC_ATC_INT_STS_REG_ATC_RCPL_TO_EMPTY_CNT)
3471 "ERROR: ATC_ATC_INT_STS_REG_ATC_RCPL_TO_EMPTY_CNT");
3472 if (val & ATC_ATC_INT_STS_REG_ATC_TCPL_ERROR)
3474 "ERROR: ATC_ATC_INT_STS_REG_ATC_TCPL_ERROR");
3475 if (val & ATC_ATC_INT_STS_REG_ATC_IREQ_LESS_THAN_STU)
3477 "ERROR: ATC_ATC_INT_STS_REG_ATC_IREQ_LESS_THAN_STU");
3480 if (attn & (AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR |
3481 AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR)) {
3483 "ERROR: FATAL parity attention set4 0x%08x",
3485 (AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR
3487 AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR)));
3491 static void bnx2x_e1h_disable(struct bnx2x_softc *sc)
3493 int port = SC_PORT(sc);
3495 REG_WR(sc, NIG_REG_LLH0_FUNC_EN + port * 8, 0);
3498 static void bnx2x_e1h_enable(struct bnx2x_softc *sc)
3500 int port = SC_PORT(sc);
3502 REG_WR(sc, NIG_REG_LLH0_FUNC_EN + port * 8, 1);
3506 * called due to MCP event (on pmf):
3507 * reread new bandwidth configuration
3509 * notify others function about the change
3511 static void bnx2x_config_mf_bw(struct bnx2x_softc *sc)
3513 if (sc->link_vars.link_up) {
3514 bnx2x_cmng_fns_init(sc, TRUE, CMNG_FNS_MINMAX);
3515 bnx2x_link_sync_notify(sc);
3518 storm_memset_cmng(sc, &sc->cmng, SC_PORT(sc));
3521 static void bnx2x_set_mf_bw(struct bnx2x_softc *sc)
3523 bnx2x_config_mf_bw(sc);
3524 bnx2x_fw_command(sc, DRV_MSG_CODE_SET_MF_BW_ACK, 0);
3527 static void bnx2x_handle_eee_event(struct bnx2x_softc *sc)
3529 bnx2x_fw_command(sc, DRV_MSG_CODE_EEE_RESULTS_ACK, 0);
3532 #define DRV_INFO_ETH_STAT_NUM_MACS_REQUIRED 3
3534 static void bnx2x_drv_info_ether_stat(struct bnx2x_softc *sc)
3536 struct eth_stats_info *ether_stat = &sc->sp->drv_info_to_mcp.ether_stat;
3538 strncpy(ether_stat->version, BNX2X_DRIVER_VERSION,
3539 ETH_STAT_INFO_VERSION_LEN);
3541 sc->sp_objs[0].mac_obj.get_n_elements(sc, &sc->sp_objs[0].mac_obj,
3542 DRV_INFO_ETH_STAT_NUM_MACS_REQUIRED,
3543 ether_stat->mac_local + MAC_PAD,
3546 ether_stat->mtu_size = sc->mtu;
3548 ether_stat->feature_flags |= FEATURE_ETH_CHKSUM_OFFLOAD_MASK;
3549 ether_stat->promiscuous_mode = 0; // (flags & PROMISC) ? 1 : 0;
3551 ether_stat->txq_size = sc->tx_ring_size;
3552 ether_stat->rxq_size = sc->rx_ring_size;
3555 static void bnx2x_handle_drv_info_req(struct bnx2x_softc *sc)
3557 enum drv_info_opcode op_code;
3558 uint32_t drv_info_ctl = SHMEM2_RD(sc, drv_info_control);
3560 /* if drv_info version supported by MFW doesn't match - send NACK */
3561 if ((drv_info_ctl & DRV_INFO_CONTROL_VER_MASK) != DRV_INFO_CUR_VER) {
3562 bnx2x_fw_command(sc, DRV_MSG_CODE_DRV_INFO_NACK, 0);
3566 op_code = ((drv_info_ctl & DRV_INFO_CONTROL_OP_CODE_MASK) >>
3567 DRV_INFO_CONTROL_OP_CODE_SHIFT);
3569 memset(&sc->sp->drv_info_to_mcp, 0, sizeof(union drv_info_to_mcp));
3572 case ETH_STATS_OPCODE:
3573 bnx2x_drv_info_ether_stat(sc);
3575 case FCOE_STATS_OPCODE:
3576 case ISCSI_STATS_OPCODE:
3578 /* if op code isn't supported - send NACK */
3579 bnx2x_fw_command(sc, DRV_MSG_CODE_DRV_INFO_NACK, 0);
3584 * If we got drv_info attn from MFW then these fields are defined in
3587 SHMEM2_WR(sc, drv_info_host_addr_lo,
3588 U64_LO(BNX2X_SP_MAPPING(sc, drv_info_to_mcp)));
3589 SHMEM2_WR(sc, drv_info_host_addr_hi,
3590 U64_HI(BNX2X_SP_MAPPING(sc, drv_info_to_mcp)));
3592 bnx2x_fw_command(sc, DRV_MSG_CODE_DRV_INFO_ACK, 0);
3595 static void bnx2x_dcc_event(struct bnx2x_softc *sc, uint32_t dcc_event)
3597 if (dcc_event & DRV_STATUS_DCC_DISABLE_ENABLE_PF) {
3599 * This is the only place besides the function initialization
3600 * where the sc->flags can change so it is done without any
3604 mf_info.mf_config[SC_VN(sc)] & FUNC_MF_CFG_FUNC_DISABLED) {
3605 PMD_DRV_LOG(DEBUG, "mf_cfg function disabled");
3606 sc->flags |= BNX2X_MF_FUNC_DIS;
3607 bnx2x_e1h_disable(sc);
3609 PMD_DRV_LOG(DEBUG, "mf_cfg function enabled");
3610 sc->flags &= ~BNX2X_MF_FUNC_DIS;
3611 bnx2x_e1h_enable(sc);
3613 dcc_event &= ~DRV_STATUS_DCC_DISABLE_ENABLE_PF;
3616 if (dcc_event & DRV_STATUS_DCC_BANDWIDTH_ALLOCATION) {
3617 bnx2x_config_mf_bw(sc);
3618 dcc_event &= ~DRV_STATUS_DCC_BANDWIDTH_ALLOCATION;
3621 /* Report results to MCP */
3623 bnx2x_fw_command(sc, DRV_MSG_CODE_DCC_FAILURE, 0);
3625 bnx2x_fw_command(sc, DRV_MSG_CODE_DCC_OK, 0);
3628 static void bnx2x_pmf_update(struct bnx2x_softc *sc)
3630 int port = SC_PORT(sc);
3636 * We need the mb() to ensure the ordering between the writing to
3637 * sc->port.pmf here and reading it from the bnx2x_periodic_task().
3641 /* enable nig attention */
3642 val = (0xff0f | (1 << (SC_VN(sc) + 4)));
3643 if (sc->devinfo.int_block == INT_BLOCK_HC) {
3644 REG_WR(sc, HC_REG_TRAILING_EDGE_0 + port * 8, val);
3645 REG_WR(sc, HC_REG_LEADING_EDGE_0 + port * 8, val);
3646 } else if (!CHIP_IS_E1x(sc)) {
3647 REG_WR(sc, IGU_REG_TRAILING_EDGE_LATCH, val);
3648 REG_WR(sc, IGU_REG_LEADING_EDGE_LATCH, val);
3651 bnx2x_stats_handle(sc, STATS_EVENT_PMF);
3654 static int bnx2x_mc_assert(struct bnx2x_softc *sc)
3658 __rte_unused uint32_t row0, row1, row2, row3;
3662 REG_RD8(sc, BAR_XSTRORM_INTMEM + XSTORM_ASSERT_LIST_INDEX_OFFSET);
3664 PMD_DRV_LOG(ERR, "XSTORM_ASSERT_LIST_INDEX 0x%x", last_idx);
3666 /* print the asserts */
3667 for (i = 0; i < STORM_ASSERT_ARRAY_SIZE; i++) {
3671 BAR_XSTRORM_INTMEM + XSTORM_ASSERT_LIST_OFFSET(i));
3674 BAR_XSTRORM_INTMEM + XSTORM_ASSERT_LIST_OFFSET(i) +
3678 BAR_XSTRORM_INTMEM + XSTORM_ASSERT_LIST_OFFSET(i) +
3682 BAR_XSTRORM_INTMEM + XSTORM_ASSERT_LIST_OFFSET(i) +
3685 if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) {
3687 "XSTORM_ASSERT_INDEX 0x%x = 0x%08x 0x%08x 0x%08x 0x%08x",
3688 i, row3, row2, row1, row0);
3697 REG_RD8(sc, BAR_TSTRORM_INTMEM + TSTORM_ASSERT_LIST_INDEX_OFFSET);
3699 PMD_DRV_LOG(ERR, "TSTORM_ASSERT_LIST_INDEX 0x%x", last_idx);
3702 /* print the asserts */
3703 for (i = 0; i < STORM_ASSERT_ARRAY_SIZE; i++) {
3707 BAR_TSTRORM_INTMEM + TSTORM_ASSERT_LIST_OFFSET(i));
3710 BAR_TSTRORM_INTMEM + TSTORM_ASSERT_LIST_OFFSET(i) +
3714 BAR_TSTRORM_INTMEM + TSTORM_ASSERT_LIST_OFFSET(i) +
3718 BAR_TSTRORM_INTMEM + TSTORM_ASSERT_LIST_OFFSET(i) +
3721 if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) {
3723 "TSTORM_ASSERT_INDEX 0x%x = 0x%08x 0x%08x 0x%08x 0x%08x",
3724 i, row3, row2, row1, row0);
3733 REG_RD8(sc, BAR_CSTRORM_INTMEM + CSTORM_ASSERT_LIST_INDEX_OFFSET);
3735 PMD_DRV_LOG(ERR, "CSTORM_ASSERT_LIST_INDEX 0x%x", last_idx);
3738 /* print the asserts */
3739 for (i = 0; i < STORM_ASSERT_ARRAY_SIZE; i++) {
3743 BAR_CSTRORM_INTMEM + CSTORM_ASSERT_LIST_OFFSET(i));
3746 BAR_CSTRORM_INTMEM + CSTORM_ASSERT_LIST_OFFSET(i) +
3750 BAR_CSTRORM_INTMEM + CSTORM_ASSERT_LIST_OFFSET(i) +
3754 BAR_CSTRORM_INTMEM + CSTORM_ASSERT_LIST_OFFSET(i) +
3757 if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) {
3759 "CSTORM_ASSERT_INDEX 0x%x = 0x%08x 0x%08x 0x%08x 0x%08x",
3760 i, row3, row2, row1, row0);
3769 REG_RD8(sc, BAR_USTRORM_INTMEM + USTORM_ASSERT_LIST_INDEX_OFFSET);
3771 PMD_DRV_LOG(ERR, "USTORM_ASSERT_LIST_INDEX 0x%x", last_idx);
3774 /* print the asserts */
3775 for (i = 0; i < STORM_ASSERT_ARRAY_SIZE; i++) {
3779 BAR_USTRORM_INTMEM + USTORM_ASSERT_LIST_OFFSET(i));
3782 BAR_USTRORM_INTMEM + USTORM_ASSERT_LIST_OFFSET(i) +
3786 BAR_USTRORM_INTMEM + USTORM_ASSERT_LIST_OFFSET(i) +
3790 BAR_USTRORM_INTMEM + USTORM_ASSERT_LIST_OFFSET(i) +
3793 if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) {
3795 "USTORM_ASSERT_INDEX 0x%x = 0x%08x 0x%08x 0x%08x 0x%08x",
3796 i, row3, row2, row1, row0);
3806 static void bnx2x_attn_int_deasserted3(struct bnx2x_softc *sc, uint32_t attn)
3808 int func = SC_FUNC(sc);
3811 if (attn & EVEREST_GEN_ATTN_IN_USE_MASK) {
3813 if (attn & BNX2X_PMF_LINK_ASSERT(sc)) {
3815 REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_12 + func * 4, 0);
3816 bnx2x_read_mf_cfg(sc);
3817 sc->devinfo.mf_info.mf_config[SC_VN(sc)] =
3819 func_mf_config[SC_ABS_FUNC(sc)].config);
3821 SHMEM_RD(sc, func_mb[SC_FW_MB_IDX(sc)].drv_status);
3823 if (val & DRV_STATUS_DCC_EVENT_MASK)
3826 DRV_STATUS_DCC_EVENT_MASK));
3828 if (val & DRV_STATUS_SET_MF_BW)
3829 bnx2x_set_mf_bw(sc);
3831 if (val & DRV_STATUS_DRV_INFO_REQ)
3832 bnx2x_handle_drv_info_req(sc);
3834 if ((sc->port.pmf == 0) && (val & DRV_STATUS_PMF))
3835 bnx2x_pmf_update(sc);
3837 if (val & DRV_STATUS_EEE_NEGOTIATION_RESULTS)
3838 bnx2x_handle_eee_event(sc);
3840 if (sc->link_vars.periodic_flags &
3841 ELINK_PERIODIC_FLAGS_LINK_EVENT) {
3842 /* sync with link */
3843 sc->link_vars.periodic_flags &=
3844 ~ELINK_PERIODIC_FLAGS_LINK_EVENT;
3846 bnx2x_link_sync_notify(sc);
3848 bnx2x_link_report(sc);
3852 * Always call it here: bnx2x_link_report() will
3853 * prevent the link indication duplication.
3855 bnx2x_link_status_update(sc);
3857 } else if (attn & BNX2X_MC_ASSERT_BITS) {
3859 PMD_DRV_LOG(ERR, "MC assert!");
3860 bnx2x_mc_assert(sc);
3861 REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_10, 0);
3862 REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_9, 0);
3863 REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_8, 0);
3864 REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_7, 0);
3865 rte_panic("MC assert!");
3867 } else if (attn & BNX2X_MCP_ASSERT) {
3869 PMD_DRV_LOG(ERR, "MCP assert!");
3870 REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_11, 0);
3874 "Unknown HW assert! (attn 0x%08x)", attn);
3878 if (attn & EVEREST_LATCHED_ATTN_IN_USE_MASK) {
3879 PMD_DRV_LOG(ERR, "LATCHED attention 0x%08x (masked)", attn);
3880 if (attn & BNX2X_GRC_TIMEOUT) {
3881 val = REG_RD(sc, MISC_REG_GRC_TIMEOUT_ATTN);
3882 PMD_DRV_LOG(ERR, "GRC time-out 0x%08x", val);
3884 if (attn & BNX2X_GRC_RSV) {
3885 val = REG_RD(sc, MISC_REG_GRC_RSV_ATTN);
3886 PMD_DRV_LOG(ERR, "GRC reserved 0x%08x", val);
3888 REG_WR(sc, MISC_REG_AEU_CLR_LATCH_SIGNAL, 0x7ff);
3892 static void bnx2x_attn_int_deasserted2(struct bnx2x_softc *sc, uint32_t attn)
3894 int port = SC_PORT(sc);
3896 uint32_t val0, mask0, val1, mask1;
3899 if (attn & AEU_INPUTS_ATTN_BITS_CFC_HW_INTERRUPT) {
3900 val = REG_RD(sc, CFC_REG_CFC_INT_STS_CLR);
3901 PMD_DRV_LOG(ERR, "CFC hw attention 0x%08x", val);
3902 /* CFC error attention */
3904 PMD_DRV_LOG(ERR, "FATAL error from CFC");
3908 if (attn & AEU_INPUTS_ATTN_BITS_PXP_HW_INTERRUPT) {
3909 val = REG_RD(sc, PXP_REG_PXP_INT_STS_CLR_0);
3910 PMD_DRV_LOG(ERR, "PXP hw attention-0 0x%08x", val);
3911 /* RQ_USDMDP_FIFO_OVERFLOW */
3912 if (val & 0x18000) {
3913 PMD_DRV_LOG(ERR, "FATAL error from PXP");
3916 if (!CHIP_IS_E1x(sc)) {
3917 val = REG_RD(sc, PXP_REG_PXP_INT_STS_CLR_1);
3918 PMD_DRV_LOG(ERR, "PXP hw attention-1 0x%08x", val);
3921 #define PXP2_EOP_ERROR_BIT PXP2_PXP2_INT_STS_CLR_0_REG_WR_PGLUE_EOP_ERROR
3922 #define AEU_PXP2_HW_INT_BIT AEU_INPUTS_ATTN_BITS_PXPPCICLOCKCLIENT_HW_INTERRUPT
3924 if (attn & AEU_PXP2_HW_INT_BIT) {
3925 /* CQ47854 workaround do not panic on
3926 * PXP2_PXP2_INT_STS_0_REG_WR_PGLUE_EOP_ERROR
3928 if (!CHIP_IS_E1x(sc)) {
3929 mask0 = REG_RD(sc, PXP2_REG_PXP2_INT_MASK_0);
3930 val1 = REG_RD(sc, PXP2_REG_PXP2_INT_STS_1);
3931 mask1 = REG_RD(sc, PXP2_REG_PXP2_INT_MASK_1);
3932 val0 = REG_RD(sc, PXP2_REG_PXP2_INT_STS_0);
3934 * If the only PXP2_EOP_ERROR_BIT is set in
3935 * STS0 and STS1 - clear it
3937 * probably we lose additional attentions between
3938 * STS0 and STS_CLR0, in this case user will not
3939 * be notified about them
3941 if (val0 & mask0 & PXP2_EOP_ERROR_BIT &&
3943 val0 = REG_RD(sc, PXP2_REG_PXP2_INT_STS_CLR_0);
3945 /* print the register, since no one can restore it */
3947 "PXP2_REG_PXP2_INT_STS_CLR_0 0x%08x", val0);
3950 * if PXP2_PXP2_INT_STS_0_REG_WR_PGLUE_EOP_ERROR
3953 if (val0 & PXP2_EOP_ERROR_BIT) {
3954 PMD_DRV_LOG(ERR, "PXP2_WR_PGLUE_EOP_ERROR");
3957 * if only PXP2_PXP2_INT_STS_0_REG_WR_PGLUE_EOP_ERROR is
3958 * set then clear attention from PXP2 block without panic
3960 if (((val0 & mask0) == PXP2_EOP_ERROR_BIT) &&
3961 ((val1 & mask1) == 0))
3962 attn &= ~AEU_PXP2_HW_INT_BIT;
3967 if (attn & HW_INTERRUT_ASSERT_SET_2) {
3968 reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_2 :
3969 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_2);
3971 val = REG_RD(sc, reg_offset);
3972 val &= ~(attn & HW_INTERRUT_ASSERT_SET_2);
3973 REG_WR(sc, reg_offset, val);
3976 "FATAL HW block attention set2 0x%x",
3977 (uint32_t) (attn & HW_INTERRUT_ASSERT_SET_2));
3978 rte_panic("HW block attention set2");
3982 static void bnx2x_attn_int_deasserted1(struct bnx2x_softc *sc, uint32_t attn)
3984 int port = SC_PORT(sc);
3988 if (attn & AEU_INPUTS_ATTN_BITS_DOORBELLQ_HW_INTERRUPT) {
3989 val = REG_RD(sc, DORQ_REG_DORQ_INT_STS_CLR);
3990 PMD_DRV_LOG(ERR, "DB hw attention 0x%08x", val);
3991 /* DORQ discard attention */
3993 PMD_DRV_LOG(ERR, "FATAL error from DORQ");
3997 if (attn & HW_INTERRUT_ASSERT_SET_1) {
3998 reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_1 :
3999 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_1);
4001 val = REG_RD(sc, reg_offset);
4002 val &= ~(attn & HW_INTERRUT_ASSERT_SET_1);
4003 REG_WR(sc, reg_offset, val);
4006 "FATAL HW block attention set1 0x%08x",
4007 (uint32_t) (attn & HW_INTERRUT_ASSERT_SET_1));
4008 rte_panic("HW block attention set1");
4012 static void bnx2x_attn_int_deasserted0(struct bnx2x_softc *sc, uint32_t attn)
4014 int port = SC_PORT(sc);
4018 reg_offset = (port) ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 :
4019 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0;
4021 if (attn & AEU_INPUTS_ATTN_BITS_SPIO5) {
4022 val = REG_RD(sc, reg_offset);
4023 val &= ~AEU_INPUTS_ATTN_BITS_SPIO5;
4024 REG_WR(sc, reg_offset, val);
4026 PMD_DRV_LOG(WARNING, "SPIO5 hw attention");
4028 /* Fan failure attention */
4029 elink_hw_reset_phy(&sc->link_params);
4030 bnx2x_fan_failure(sc);
4033 if ((attn & sc->link_vars.aeu_int_mask) && sc->port.pmf) {
4034 elink_handle_module_detect_int(&sc->link_params);
4037 if (attn & HW_INTERRUT_ASSERT_SET_0) {
4038 val = REG_RD(sc, reg_offset);
4039 val &= ~(attn & HW_INTERRUT_ASSERT_SET_0);
4040 REG_WR(sc, reg_offset, val);
4042 rte_panic("FATAL HW block attention set0 0x%lx",
4043 (attn & HW_INTERRUT_ASSERT_SET_0));
4047 static void bnx2x_attn_int_deasserted(struct bnx2x_softc *sc, uint32_t deasserted)
4049 struct attn_route attn;
4050 struct attn_route *group_mask;
4051 int port = SC_PORT(sc);
4056 uint8_t global = FALSE;
4059 * Need to take HW lock because MCP or other port might also
4060 * try to handle this event.
4062 bnx2x_acquire_alr(sc);
4064 if (bnx2x_chk_parity_attn(sc, &global, TRUE)) {
4065 sc->recovery_state = BNX2X_RECOVERY_INIT;
4067 /* disable HW interrupts */
4068 bnx2x_int_disable(sc);
4069 bnx2x_release_alr(sc);
4073 attn.sig[0] = REG_RD(sc, MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 + port * 4);
4074 attn.sig[1] = REG_RD(sc, MISC_REG_AEU_AFTER_INVERT_2_FUNC_0 + port * 4);
4075 attn.sig[2] = REG_RD(sc, MISC_REG_AEU_AFTER_INVERT_3_FUNC_0 + port * 4);
4076 attn.sig[3] = REG_RD(sc, MISC_REG_AEU_AFTER_INVERT_4_FUNC_0 + port * 4);
4077 if (!CHIP_IS_E1x(sc)) {
4079 REG_RD(sc, MISC_REG_AEU_AFTER_INVERT_5_FUNC_0 + port * 4);
4084 for (index = 0; index < MAX_DYNAMIC_ATTN_GRPS; index++) {
4085 if (deasserted & (1 << index)) {
4086 group_mask = &sc->attn_group[index];
4088 bnx2x_attn_int_deasserted4(sc,
4090 sig[4] & group_mask->sig[4]);
4091 bnx2x_attn_int_deasserted3(sc,
4093 sig[3] & group_mask->sig[3]);
4094 bnx2x_attn_int_deasserted1(sc,
4096 sig[1] & group_mask->sig[1]);
4097 bnx2x_attn_int_deasserted2(sc,
4099 sig[2] & group_mask->sig[2]);
4100 bnx2x_attn_int_deasserted0(sc,
4102 sig[0] & group_mask->sig[0]);
4106 bnx2x_release_alr(sc);
4108 if (sc->devinfo.int_block == INT_BLOCK_HC) {
4109 reg_addr = (HC_REG_COMMAND_REG + port * 32 +
4110 COMMAND_REG_ATTN_BITS_CLR);
4112 reg_addr = (BAR_IGU_INTMEM + IGU_CMD_ATTN_BIT_CLR_UPPER * 8);
4117 "about to mask 0x%08x at %s addr 0x%08x", val,
4118 (sc->devinfo.int_block == INT_BLOCK_HC) ? "HC" : "IGU",
4120 REG_WR(sc, reg_addr, val);
4122 if (~sc->attn_state & deasserted) {
4123 PMD_DRV_LOG(ERR, "IGU error");
4126 reg_addr = port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 :
4127 MISC_REG_AEU_MASK_ATTN_FUNC_0;
4129 bnx2x_acquire_hw_lock(sc, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
4131 aeu_mask = REG_RD(sc, reg_addr);
4133 aeu_mask |= (deasserted & 0x3ff);
4135 REG_WR(sc, reg_addr, aeu_mask);
4136 bnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
4138 sc->attn_state &= ~deasserted;
4141 static void bnx2x_attn_int(struct bnx2x_softc *sc)
4143 /* read local copy of bits */
4144 uint32_t attn_bits = le32toh(sc->def_sb->atten_status_block.attn_bits);
4146 le32toh(sc->def_sb->atten_status_block.attn_bits_ack);
4147 uint32_t attn_state = sc->attn_state;
4149 /* look for changed bits */
4150 uint32_t asserted = attn_bits & ~attn_ack & ~attn_state;
4151 uint32_t deasserted = ~attn_bits & attn_ack & attn_state;
4154 "attn_bits 0x%08x attn_ack 0x%08x asserted 0x%08x deasserted 0x%08x",
4155 attn_bits, attn_ack, asserted, deasserted);
4157 if (~(attn_bits ^ attn_ack) & (attn_bits ^ attn_state)) {
4158 PMD_DRV_LOG(ERR, "BAD attention state");
4161 /* handle bits that were raised */
4163 bnx2x_attn_int_asserted(sc, asserted);
4167 bnx2x_attn_int_deasserted(sc, deasserted);
4171 static uint16_t bnx2x_update_dsb_idx(struct bnx2x_softc *sc)
4173 struct host_sp_status_block *def_sb = sc->def_sb;
4176 mb(); /* status block is written to by the chip */
4178 if (sc->def_att_idx != def_sb->atten_status_block.attn_bits_index) {
4179 sc->def_att_idx = def_sb->atten_status_block.attn_bits_index;
4180 rc |= BNX2X_DEF_SB_ATT_IDX;
4183 if (sc->def_idx != def_sb->sp_sb.running_index) {
4184 sc->def_idx = def_sb->sp_sb.running_index;
4185 rc |= BNX2X_DEF_SB_IDX;
4193 static struct ecore_queue_sp_obj *bnx2x_cid_to_q_obj(struct bnx2x_softc *sc,
4196 return &sc->sp_objs[CID_TO_FP(cid, sc)].q_obj;
4199 static void bnx2x_handle_mcast_eqe(struct bnx2x_softc *sc)
4201 struct ecore_mcast_ramrod_params rparam;
4204 memset(&rparam, 0, sizeof(rparam));
4206 rparam.mcast_obj = &sc->mcast_obj;
4208 /* clear pending state for the last command */
4209 sc->mcast_obj.raw.clear_pending(&sc->mcast_obj.raw);
4211 /* if there are pending mcast commands - send them */
4212 if (sc->mcast_obj.check_pending(&sc->mcast_obj)) {
4213 rc = ecore_config_mcast(sc, &rparam, ECORE_MCAST_CMD_CONT);
4216 "Failed to send pending mcast commands (%d)",
4223 bnx2x_handle_classification_eqe(struct bnx2x_softc *sc, union event_ring_elem *elem)
4225 unsigned long ramrod_flags = 0;
4227 uint32_t cid = elem->message.data.eth_event.echo & BNX2X_SWCID_MASK;
4228 struct ecore_vlan_mac_obj *vlan_mac_obj;
4230 /* always push next commands out, don't wait here */
4231 bnx2x_set_bit(RAMROD_CONT, &ramrod_flags);
4233 switch (le32toh(elem->message.data.eth_event.echo) >> BNX2X_SWCID_SHIFT) {
4234 case ECORE_FILTER_MAC_PENDING:
4235 PMD_DRV_LOG(DEBUG, "Got SETUP_MAC completions");
4236 vlan_mac_obj = &sc->sp_objs[cid].mac_obj;
4239 case ECORE_FILTER_MCAST_PENDING:
4240 PMD_DRV_LOG(DEBUG, "Got SETUP_MCAST completions");
4241 bnx2x_handle_mcast_eqe(sc);
4245 PMD_DRV_LOG(NOTICE, "Unsupported classification command: %d",
4246 elem->message.data.eth_event.echo);
4250 rc = vlan_mac_obj->complete(sc, vlan_mac_obj, elem, &ramrod_flags);
4253 PMD_DRV_LOG(NOTICE, "Failed to schedule new commands (%d)", rc);
4254 } else if (rc > 0) {
4255 PMD_DRV_LOG(DEBUG, "Scheduled next pending commands...");
4259 static void bnx2x_handle_rx_mode_eqe(struct bnx2x_softc *sc)
4261 bnx2x_clear_bit(ECORE_FILTER_RX_MODE_PENDING, &sc->sp_state);
4263 /* send rx_mode command again if was requested */
4264 if (bnx2x_test_and_clear_bit(ECORE_FILTER_RX_MODE_SCHED, &sc->sp_state)) {
4265 bnx2x_set_storm_rx_mode(sc);
4269 static void bnx2x_update_eq_prod(struct bnx2x_softc *sc, uint16_t prod)
4271 storm_memset_eq_prod(sc, prod, SC_FUNC(sc));
4272 wmb(); /* keep prod updates ordered */
4275 static void bnx2x_eq_int(struct bnx2x_softc *sc)
4277 uint16_t hw_cons, sw_cons, sw_prod;
4278 union event_ring_elem *elem;
4283 struct ecore_queue_sp_obj *q_obj;
4284 struct ecore_func_sp_obj *f_obj = &sc->func_obj;
4285 struct ecore_raw_obj *rss_raw = &sc->rss_conf_obj.raw;
4287 hw_cons = le16toh(*sc->eq_cons_sb);
4290 * The hw_cons range is 1-255, 257 - the sw_cons range is 0-254, 256.
4291 * when we get to the next-page we need to adjust so the loop
4292 * condition below will be met. The next element is the size of a
4293 * regular element and hence incrementing by 1
4295 if ((hw_cons & EQ_DESC_MAX_PAGE) == EQ_DESC_MAX_PAGE) {
4300 * This function may never run in parallel with itself for a
4301 * specific sc and no need for a read memory barrier here.
4303 sw_cons = sc->eq_cons;
4304 sw_prod = sc->eq_prod;
4308 sw_prod = NEXT_EQ_IDX(sw_prod), sw_cons = NEXT_EQ_IDX(sw_cons)) {
4310 elem = &sc->eq[EQ_DESC(sw_cons)];
4312 /* elem CID originates from FW, actually LE */
4313 cid = SW_CID(elem->message.data.cfc_del_event.cid);
4314 opcode = elem->message.opcode;
4316 /* handle eq element */
4318 case EVENT_RING_OPCODE_STAT_QUERY:
4319 PMD_DEBUG_PERIODIC_LOG(DEBUG, "got statistics completion event %d",
4321 /* nothing to do with stats comp */
4324 case EVENT_RING_OPCODE_CFC_DEL:
4325 /* handle according to cid range */
4326 /* we may want to verify here that the sc state is HALTING */
4327 PMD_DRV_LOG(DEBUG, "got delete ramrod for MULTI[%d]",
4329 q_obj = bnx2x_cid_to_q_obj(sc, cid);
4330 if (q_obj->complete_cmd(sc, q_obj, ECORE_Q_CMD_CFC_DEL)) {
4335 case EVENT_RING_OPCODE_STOP_TRAFFIC:
4336 PMD_DRV_LOG(DEBUG, "got STOP TRAFFIC");
4337 if (f_obj->complete_cmd(sc, f_obj, ECORE_F_CMD_TX_STOP)) {
4342 case EVENT_RING_OPCODE_START_TRAFFIC:
4343 PMD_DRV_LOG(DEBUG, "got START TRAFFIC");
4344 if (f_obj->complete_cmd
4345 (sc, f_obj, ECORE_F_CMD_TX_START)) {
4350 case EVENT_RING_OPCODE_FUNCTION_UPDATE:
4351 echo = elem->message.data.function_update_event.echo;
4352 if (echo == SWITCH_UPDATE) {
4354 "got FUNC_SWITCH_UPDATE ramrod");
4355 if (f_obj->complete_cmd(sc, f_obj,
4356 ECORE_F_CMD_SWITCH_UPDATE))
4362 "AFEX: ramrod completed FUNCTION_UPDATE");
4363 f_obj->complete_cmd(sc, f_obj,
4364 ECORE_F_CMD_AFEX_UPDATE);
4368 case EVENT_RING_OPCODE_FORWARD_SETUP:
4369 q_obj = &bnx2x_fwd_sp_obj(sc, q_obj);
4370 if (q_obj->complete_cmd(sc, q_obj,
4371 ECORE_Q_CMD_SETUP_TX_ONLY)) {
4376 case EVENT_RING_OPCODE_FUNCTION_START:
4377 PMD_DRV_LOG(DEBUG, "got FUNC_START ramrod");
4378 if (f_obj->complete_cmd(sc, f_obj, ECORE_F_CMD_START)) {
4383 case EVENT_RING_OPCODE_FUNCTION_STOP:
4384 PMD_DRV_LOG(DEBUG, "got FUNC_STOP ramrod");
4385 if (f_obj->complete_cmd(sc, f_obj, ECORE_F_CMD_STOP)) {
4391 switch (opcode | sc->state) {
4392 case (EVENT_RING_OPCODE_RSS_UPDATE_RULES | BNX2X_STATE_OPEN):
4393 case (EVENT_RING_OPCODE_RSS_UPDATE_RULES | BNX2X_STATE_OPENING_WAITING_PORT):
4395 elem->message.data.eth_event.echo & BNX2X_SWCID_MASK;
4396 PMD_DRV_LOG(DEBUG, "got RSS_UPDATE ramrod. CID %d",
4398 rss_raw->clear_pending(rss_raw);
4401 case (EVENT_RING_OPCODE_SET_MAC | BNX2X_STATE_OPEN):
4402 case (EVENT_RING_OPCODE_SET_MAC | BNX2X_STATE_DIAG):
4403 case (EVENT_RING_OPCODE_SET_MAC | BNX2X_STATE_CLOSING_WAITING_HALT):
4404 case (EVENT_RING_OPCODE_CLASSIFICATION_RULES | BNX2X_STATE_OPEN):
4405 case (EVENT_RING_OPCODE_CLASSIFICATION_RULES | BNX2X_STATE_DIAG):
4406 case (EVENT_RING_OPCODE_CLASSIFICATION_RULES | BNX2X_STATE_CLOSING_WAITING_HALT):
4408 "got (un)set mac ramrod");
4409 bnx2x_handle_classification_eqe(sc, elem);
4412 case (EVENT_RING_OPCODE_MULTICAST_RULES | BNX2X_STATE_OPEN):
4413 case (EVENT_RING_OPCODE_MULTICAST_RULES | BNX2X_STATE_DIAG):
4414 case (EVENT_RING_OPCODE_MULTICAST_RULES | BNX2X_STATE_CLOSING_WAITING_HALT):
4416 "got mcast ramrod");
4417 bnx2x_handle_mcast_eqe(sc);
4420 case (EVENT_RING_OPCODE_FILTERS_RULES | BNX2X_STATE_OPEN):
4421 case (EVENT_RING_OPCODE_FILTERS_RULES | BNX2X_STATE_DIAG):
4422 case (EVENT_RING_OPCODE_FILTERS_RULES | BNX2X_STATE_CLOSING_WAITING_HALT):
4424 "got rx_mode ramrod");
4425 bnx2x_handle_rx_mode_eqe(sc);
4429 /* unknown event log error and continue */
4430 PMD_DRV_LOG(INFO, "Unknown EQ event %d, sc->state 0x%x",
4431 elem->message.opcode, sc->state);
4439 atomic_add_acq_long(&sc->eq_spq_left, spqe_cnt);
4441 sc->eq_cons = sw_cons;
4442 sc->eq_prod = sw_prod;
4444 /* make sure that above mem writes were issued towards the memory */
4447 /* update producer */
4448 bnx2x_update_eq_prod(sc, sc->eq_prod);
4451 static int bnx2x_handle_sp_tq(struct bnx2x_softc *sc)
4456 /* what work needs to be performed? */
4457 status = bnx2x_update_dsb_idx(sc);
4460 if (status & BNX2X_DEF_SB_ATT_IDX) {
4461 PMD_DRV_LOG(DEBUG, "---> ATTN INTR <---");
4463 status &= ~BNX2X_DEF_SB_ATT_IDX;
4467 /* SP events: STAT_QUERY and others */
4468 if (status & BNX2X_DEF_SB_IDX) {
4469 /* handle EQ completions */
4470 PMD_DEBUG_PERIODIC_LOG(DEBUG, "---> EQ INTR <---");
4472 bnx2x_ack_sb(sc, sc->igu_dsb_id, USTORM_ID,
4473 le16toh(sc->def_idx), IGU_INT_NOP, 1);
4474 status &= ~BNX2X_DEF_SB_IDX;
4477 /* if status is non zero then something went wrong */
4478 if (unlikely(status)) {
4480 "Got an unknown SP interrupt! (0x%04x)", status);
4483 /* ack status block only if something was actually handled */
4484 bnx2x_ack_sb(sc, sc->igu_dsb_id, ATTENTION_ID,
4485 le16toh(sc->def_att_idx), IGU_INT_ENABLE, 1);
4490 static void bnx2x_handle_fp_tq(struct bnx2x_fastpath *fp, int scan_fp)
4492 struct bnx2x_softc *sc = fp->sc;
4493 uint8_t more_rx = FALSE;
4495 /* update the fastpath index */
4496 bnx2x_update_fp_sb_idx(fp);
4499 if (bnx2x_has_rx_work(fp)) {
4500 more_rx = bnx2x_rxeof(sc, fp);
4504 /* still more work to do */
4505 bnx2x_handle_fp_tq(fp, scan_fp);
4510 bnx2x_ack_sb(sc, fp->igu_sb_id, USTORM_ID,
4511 le16toh(fp->fp_hc_idx), IGU_INT_DISABLE, 1);
4515 * Legacy interrupt entry point.
4517 * Verifies that the controller generated the interrupt and
4518 * then calls a separate routine to handle the various
4519 * interrupt causes: link, RX, and TX.
4521 int bnx2x_intr_legacy(struct bnx2x_softc *sc, int scan_fp)
4523 struct bnx2x_fastpath *fp;
4524 uint32_t status, mask;
4528 * 0 for ustorm, 1 for cstorm
4529 * the bits returned from ack_int() are 0-15
4530 * bit 0 = attention status block
4531 * bit 1 = fast path status block
4532 * a mask of 0x2 or more = tx/rx event
4533 * a mask of 1 = slow path event
4536 status = bnx2x_ack_int(sc);
4538 /* the interrupt is not for us */
4539 if (unlikely(status == 0)) {
4543 PMD_DEBUG_PERIODIC_LOG(DEBUG, "Interrupt status 0x%04x", status);
4544 //bnx2x_dump_status_block(sc);
4546 FOR_EACH_ETH_QUEUE(sc, i) {
4548 mask = (0x2 << (fp->index + CNIC_SUPPORT(sc)));
4549 if (status & mask) {
4550 bnx2x_handle_fp_tq(fp, scan_fp);
4555 if (unlikely(status & 0x1)) {
4556 rc = bnx2x_handle_sp_tq(sc);
4560 if (unlikely(status)) {
4561 PMD_DRV_LOG(WARNING,
4562 "Unexpected fastpath status (0x%08x)!", status);
4568 static int bnx2x_init_hw_common_chip(struct bnx2x_softc *sc);
4569 static int bnx2x_init_hw_common(struct bnx2x_softc *sc);
4570 static int bnx2x_init_hw_port(struct bnx2x_softc *sc);
4571 static int bnx2x_init_hw_func(struct bnx2x_softc *sc);
4572 static void bnx2x_reset_common(struct bnx2x_softc *sc);
4573 static void bnx2x_reset_port(struct bnx2x_softc *sc);
4574 static void bnx2x_reset_func(struct bnx2x_softc *sc);
4575 static int bnx2x_init_firmware(struct bnx2x_softc *sc);
4576 static void bnx2x_release_firmware(struct bnx2x_softc *sc);
4579 ecore_func_sp_drv_ops bnx2x_func_sp_drv = {
4580 .init_hw_cmn_chip = bnx2x_init_hw_common_chip,
4581 .init_hw_cmn = bnx2x_init_hw_common,
4582 .init_hw_port = bnx2x_init_hw_port,
4583 .init_hw_func = bnx2x_init_hw_func,
4585 .reset_hw_cmn = bnx2x_reset_common,
4586 .reset_hw_port = bnx2x_reset_port,
4587 .reset_hw_func = bnx2x_reset_func,
4589 .init_fw = bnx2x_init_firmware,
4590 .release_fw = bnx2x_release_firmware,
4593 static void bnx2x_init_func_obj(struct bnx2x_softc *sc)
4597 PMD_INIT_FUNC_TRACE();
4599 ecore_init_func_obj(sc,
4601 BNX2X_SP(sc, func_rdata),
4602 (phys_addr_t)BNX2X_SP_MAPPING(sc, func_rdata),
4603 BNX2X_SP(sc, func_afex_rdata),
4604 (phys_addr_t)BNX2X_SP_MAPPING(sc, func_afex_rdata),
4605 &bnx2x_func_sp_drv);
4608 static int bnx2x_init_hw(struct bnx2x_softc *sc, uint32_t load_code)
4610 struct ecore_func_state_params func_params = { NULL };
4613 PMD_INIT_FUNC_TRACE();
4615 /* prepare the parameters for function state transitions */
4616 bnx2x_set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags);
4618 func_params.f_obj = &sc->func_obj;
4619 func_params.cmd = ECORE_F_CMD_HW_INIT;
4621 func_params.params.hw_init.load_phase = load_code;
4624 * Via a plethora of function pointers, we will eventually reach
4625 * bnx2x_init_hw_common(), bnx2x_init_hw_port(), or bnx2x_init_hw_func().
4627 rc = ecore_func_state_change(sc, &func_params);
4633 bnx2x_fill(struct bnx2x_softc *sc, uint32_t addr, int fill, uint32_t len)
4637 if (!(len % 4) && !(addr % 4)) {
4638 for (i = 0; i < len; i += 4) {
4639 REG_WR(sc, (addr + i), fill);
4642 for (i = 0; i < len; i++) {
4643 REG_WR8(sc, (addr + i), fill);
4648 /* writes FP SP data to FW - data_size in dwords */
4650 bnx2x_wr_fp_sb_data(struct bnx2x_softc *sc, int fw_sb_id, uint32_t * sb_data_p,
4655 for (index = 0; index < data_size; index++) {
4657 (BAR_CSTRORM_INTMEM +
4658 CSTORM_STATUS_BLOCK_DATA_OFFSET(fw_sb_id) +
4659 (sizeof(uint32_t) * index)), *(sb_data_p + index));
4663 static void bnx2x_zero_fp_sb(struct bnx2x_softc *sc, int fw_sb_id)
4665 struct hc_status_block_data_e2 sb_data_e2;
4666 struct hc_status_block_data_e1x sb_data_e1x;
4667 uint32_t *sb_data_p;
4668 uint32_t data_size = 0;
4670 if (!CHIP_IS_E1x(sc)) {
4671 memset(&sb_data_e2, 0, sizeof(struct hc_status_block_data_e2));
4672 sb_data_e2.common.state = SB_DISABLED;
4673 sb_data_e2.common.p_func.vf_valid = FALSE;
4674 sb_data_p = (uint32_t *) & sb_data_e2;
4675 data_size = (sizeof(struct hc_status_block_data_e2) /
4678 memset(&sb_data_e1x, 0,
4679 sizeof(struct hc_status_block_data_e1x));
4680 sb_data_e1x.common.state = SB_DISABLED;
4681 sb_data_e1x.common.p_func.vf_valid = FALSE;
4682 sb_data_p = (uint32_t *) & sb_data_e1x;
4683 data_size = (sizeof(struct hc_status_block_data_e1x) /
4687 bnx2x_wr_fp_sb_data(sc, fw_sb_id, sb_data_p, data_size);
4690 (BAR_CSTRORM_INTMEM + CSTORM_STATUS_BLOCK_OFFSET(fw_sb_id)), 0,
4691 CSTORM_STATUS_BLOCK_SIZE);
4692 bnx2x_fill(sc, (BAR_CSTRORM_INTMEM + CSTORM_SYNC_BLOCK_OFFSET(fw_sb_id)),
4693 0, CSTORM_SYNC_BLOCK_SIZE);
4697 bnx2x_wr_sp_sb_data(struct bnx2x_softc *sc,
4698 struct hc_sp_status_block_data *sp_sb_data)
4703 i < (sizeof(struct hc_sp_status_block_data) / sizeof(uint32_t));
4706 (BAR_CSTRORM_INTMEM +
4707 CSTORM_SP_STATUS_BLOCK_DATA_OFFSET(SC_FUNC(sc)) +
4708 (i * sizeof(uint32_t))),
4709 *((uint32_t *) sp_sb_data + i));
4713 static void bnx2x_zero_sp_sb(struct bnx2x_softc *sc)
4715 struct hc_sp_status_block_data sp_sb_data;
4717 memset(&sp_sb_data, 0, sizeof(struct hc_sp_status_block_data));
4719 sp_sb_data.state = SB_DISABLED;
4720 sp_sb_data.p_func.vf_valid = FALSE;
4722 bnx2x_wr_sp_sb_data(sc, &sp_sb_data);
4725 (BAR_CSTRORM_INTMEM +
4726 CSTORM_SP_STATUS_BLOCK_OFFSET(SC_FUNC(sc))),
4727 0, CSTORM_SP_STATUS_BLOCK_SIZE);
4729 (BAR_CSTRORM_INTMEM +
4730 CSTORM_SP_SYNC_BLOCK_OFFSET(SC_FUNC(sc))),
4731 0, CSTORM_SP_SYNC_BLOCK_SIZE);
4735 bnx2x_setup_ndsb_state_machine(struct hc_status_block_sm *hc_sm, int igu_sb_id,
4738 hc_sm->igu_sb_id = igu_sb_id;
4739 hc_sm->igu_seg_id = igu_seg_id;
4740 hc_sm->timer_value = 0xFF;
4741 hc_sm->time_to_expire = 0xFFFFFFFF;
4744 static void bnx2x_map_sb_state_machines(struct hc_index_data *index_data)
4746 /* zero out state machine indices */
4749 index_data[HC_INDEX_ETH_RX_CQ_CONS].flags &= ~HC_INDEX_DATA_SM_ID;
4752 index_data[HC_INDEX_OOO_TX_CQ_CONS].flags &= ~HC_INDEX_DATA_SM_ID;
4753 index_data[HC_INDEX_ETH_TX_CQ_CONS_COS0].flags &= ~HC_INDEX_DATA_SM_ID;
4754 index_data[HC_INDEX_ETH_TX_CQ_CONS_COS1].flags &= ~HC_INDEX_DATA_SM_ID;
4755 index_data[HC_INDEX_ETH_TX_CQ_CONS_COS2].flags &= ~HC_INDEX_DATA_SM_ID;
4760 index_data[HC_INDEX_ETH_RX_CQ_CONS].flags |=
4761 (SM_RX_ID << HC_INDEX_DATA_SM_ID_SHIFT);
4764 index_data[HC_INDEX_OOO_TX_CQ_CONS].flags |=
4765 (SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT);
4766 index_data[HC_INDEX_ETH_TX_CQ_CONS_COS0].flags |=
4767 (SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT);
4768 index_data[HC_INDEX_ETH_TX_CQ_CONS_COS1].flags |=
4769 (SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT);
4770 index_data[HC_INDEX_ETH_TX_CQ_CONS_COS2].flags |=
4771 (SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT);
4775 bnx2x_init_sb(struct bnx2x_softc *sc, phys_addr_t busaddr, int vfid,
4776 uint8_t vf_valid, int fw_sb_id, int igu_sb_id)
4778 struct hc_status_block_data_e2 sb_data_e2;
4779 struct hc_status_block_data_e1x sb_data_e1x;
4780 struct hc_status_block_sm *hc_sm_p;
4781 uint32_t *sb_data_p;
4785 if (CHIP_INT_MODE_IS_BC(sc)) {
4786 igu_seg_id = HC_SEG_ACCESS_NORM;
4788 igu_seg_id = IGU_SEG_ACCESS_NORM;
4791 bnx2x_zero_fp_sb(sc, fw_sb_id);
4793 if (!CHIP_IS_E1x(sc)) {
4794 memset(&sb_data_e2, 0, sizeof(struct hc_status_block_data_e2));
4795 sb_data_e2.common.state = SB_ENABLED;
4796 sb_data_e2.common.p_func.pf_id = SC_FUNC(sc);
4797 sb_data_e2.common.p_func.vf_id = vfid;
4798 sb_data_e2.common.p_func.vf_valid = vf_valid;
4799 sb_data_e2.common.p_func.vnic_id = SC_VN(sc);
4800 sb_data_e2.common.same_igu_sb_1b = TRUE;
4801 sb_data_e2.common.host_sb_addr.hi = U64_HI(busaddr);
4802 sb_data_e2.common.host_sb_addr.lo = U64_LO(busaddr);
4803 hc_sm_p = sb_data_e2.common.state_machine;
4804 sb_data_p = (uint32_t *) & sb_data_e2;
4805 data_size = (sizeof(struct hc_status_block_data_e2) /
4807 bnx2x_map_sb_state_machines(sb_data_e2.index_data);
4809 memset(&sb_data_e1x, 0,
4810 sizeof(struct hc_status_block_data_e1x));
4811 sb_data_e1x.common.state = SB_ENABLED;
4812 sb_data_e1x.common.p_func.pf_id = SC_FUNC(sc);
4813 sb_data_e1x.common.p_func.vf_id = 0xff;
4814 sb_data_e1x.common.p_func.vf_valid = FALSE;
4815 sb_data_e1x.common.p_func.vnic_id = SC_VN(sc);
4816 sb_data_e1x.common.same_igu_sb_1b = TRUE;
4817 sb_data_e1x.common.host_sb_addr.hi = U64_HI(busaddr);
4818 sb_data_e1x.common.host_sb_addr.lo = U64_LO(busaddr);
4819 hc_sm_p = sb_data_e1x.common.state_machine;
4820 sb_data_p = (uint32_t *) & sb_data_e1x;
4821 data_size = (sizeof(struct hc_status_block_data_e1x) /
4823 bnx2x_map_sb_state_machines(sb_data_e1x.index_data);
4826 bnx2x_setup_ndsb_state_machine(&hc_sm_p[SM_RX_ID], igu_sb_id, igu_seg_id);
4827 bnx2x_setup_ndsb_state_machine(&hc_sm_p[SM_TX_ID], igu_sb_id, igu_seg_id);
4829 /* write indices to HW - PCI guarantees endianity of regpairs */
4830 bnx2x_wr_fp_sb_data(sc, fw_sb_id, sb_data_p, data_size);
4833 static uint8_t bnx2x_fp_qzone_id(struct bnx2x_fastpath *fp)
4835 if (CHIP_IS_E1x(fp->sc)) {
4836 return fp->cl_id + SC_PORT(fp->sc) * ETH_MAX_RX_CLIENTS_E1H;
4843 bnx2x_rx_ustorm_prods_offset(struct bnx2x_softc *sc, struct bnx2x_fastpath *fp)
4845 uint32_t offset = BAR_USTRORM_INTMEM;
4848 return PXP_VF_ADDR_USDM_QUEUES_START +
4849 (sc->acquire_resp.resc.hw_qid[fp->index] *
4850 sizeof(struct ustorm_queue_zone_data));
4851 } else if (!CHIP_IS_E1x(sc)) {
4852 offset += USTORM_RX_PRODS_E2_OFFSET(fp->cl_qzone_id);
4854 offset += USTORM_RX_PRODS_E1X_OFFSET(SC_PORT(sc), fp->cl_id);
4860 static void bnx2x_init_eth_fp(struct bnx2x_softc *sc, int idx)
4862 struct bnx2x_fastpath *fp = &sc->fp[idx];
4863 uint32_t cids[ECORE_MULTI_TX_COS] = { 0 };
4864 unsigned long q_type = 0;
4870 fp->igu_sb_id = (sc->igu_base_sb + idx + CNIC_SUPPORT(sc));
4871 fp->fw_sb_id = (sc->base_fw_ndsb + idx + CNIC_SUPPORT(sc));
4873 if (CHIP_IS_E1x(sc))
4874 fp->cl_id = SC_L_ID(sc) + idx;
4876 /* want client ID same as IGU SB ID for non-E1 */
4877 fp->cl_id = fp->igu_sb_id;
4878 fp->cl_qzone_id = bnx2x_fp_qzone_id(fp);
4880 /* setup sb indices */
4881 if (!CHIP_IS_E1x(sc)) {
4882 fp->sb_index_values = fp->status_block.e2_sb->sb.index_values;
4883 fp->sb_running_index = fp->status_block.e2_sb->sb.running_index;
4885 fp->sb_index_values = fp->status_block.e1x_sb->sb.index_values;
4886 fp->sb_running_index =
4887 fp->status_block.e1x_sb->sb.running_index;
4891 fp->ustorm_rx_prods_offset = bnx2x_rx_ustorm_prods_offset(sc, fp);
4893 fp->rx_cq_cons_sb = &fp->sb_index_values[HC_INDEX_ETH_RX_CQ_CONS];
4895 for (cos = 0; cos < sc->max_cos; cos++) {
4898 fp->tx_cons_sb = &fp->sb_index_values[HC_INDEX_ETH_TX_CQ_CONS_COS0];
4900 /* nothing more for a VF to do */
4905 bnx2x_init_sb(sc, fp->sb_dma.paddr, BNX2X_VF_ID_INVALID, FALSE,
4906 fp->fw_sb_id, fp->igu_sb_id);
4908 bnx2x_update_fp_sb_idx(fp);
4910 /* Configure Queue State object */
4911 bnx2x_set_bit(ECORE_Q_TYPE_HAS_RX, &q_type);
4912 bnx2x_set_bit(ECORE_Q_TYPE_HAS_TX, &q_type);
4914 ecore_init_queue_obj(sc,
4915 &sc->sp_objs[idx].q_obj,
4920 BNX2X_SP(sc, q_rdata),
4921 (phys_addr_t)BNX2X_SP_MAPPING(sc, q_rdata),
4924 /* configure classification DBs */
4925 ecore_init_mac_obj(sc,
4926 &sc->sp_objs[idx].mac_obj,
4930 BNX2X_SP(sc, mac_rdata),
4931 (phys_addr_t)BNX2X_SP_MAPPING(sc, mac_rdata),
4932 ECORE_FILTER_MAC_PENDING, &sc->sp_state,
4933 ECORE_OBJ_TYPE_RX_TX, &sc->macs_pool);
4937 bnx2x_update_rx_prod(struct bnx2x_softc *sc, struct bnx2x_fastpath *fp,
4938 uint16_t rx_bd_prod, uint16_t rx_cq_prod)
4940 union ustorm_eth_rx_producers rx_prods;
4943 /* update producers */
4944 rx_prods.prod.bd_prod = rx_bd_prod;
4945 rx_prods.prod.cqe_prod = rx_cq_prod;
4946 rx_prods.prod.reserved = 0;
4949 * Make sure that the BD and SGE data is updated before updating the
4950 * producers since FW might read the BD/SGE right after the producer
4952 * This is only applicable for weak-ordered memory model archs such
4953 * as IA-64. The following barrier is also mandatory since FW will
4954 * assumes BDs must have buffers.
4958 for (i = 0; i < (sizeof(rx_prods) / 4); i++) {
4960 (fp->ustorm_rx_prods_offset + (i * 4)),
4961 rx_prods.raw_data[i]);
4964 wmb(); /* keep prod updates ordered */
4967 static void bnx2x_init_rx_rings(struct bnx2x_softc *sc)
4969 struct bnx2x_fastpath *fp;
4971 struct bnx2x_rx_queue *rxq;
4973 for (i = 0; i < sc->num_queues; i++) {
4975 rxq = sc->rx_queues[fp->index];
4977 PMD_RX_LOG(ERR, "RX queue is NULL");
4981 rxq->rx_bd_head = 0;
4982 rxq->rx_bd_tail = rxq->nb_rx_desc;
4983 rxq->rx_cq_head = 0;
4984 rxq->rx_cq_tail = TOTAL_RCQ_ENTRIES(rxq);
4985 *fp->rx_cq_cons_sb = 0;
4988 * Activate the BD ring...
4989 * Warning, this will generate an interrupt (to the TSTORM)
4990 * so this can only be done after the chip is initialized
4992 bnx2x_update_rx_prod(sc, fp, rxq->rx_bd_tail, rxq->rx_cq_tail);
5000 static void bnx2x_init_tx_ring_one(struct bnx2x_fastpath *fp)
5002 struct bnx2x_tx_queue *txq = fp->sc->tx_queues[fp->index];
5004 fp->tx_db.data.header.header = 1 << DOORBELL_HDR_DB_TYPE_SHIFT;
5005 fp->tx_db.data.zero_fill1 = 0;
5006 fp->tx_db.data.prod = 0;
5009 PMD_TX_LOG(ERR, "ERROR: TX queue is NULL");
5013 txq->tx_pkt_tail = 0;
5014 txq->tx_pkt_head = 0;
5015 txq->tx_bd_tail = 0;
5016 txq->tx_bd_head = 0;
5019 static void bnx2x_init_tx_rings(struct bnx2x_softc *sc)
5023 for (i = 0; i < sc->num_queues; i++) {
5024 bnx2x_init_tx_ring_one(&sc->fp[i]);
5028 static void bnx2x_init_def_sb(struct bnx2x_softc *sc)
5030 struct host_sp_status_block *def_sb = sc->def_sb;
5031 phys_addr_t mapping = sc->def_sb_dma.paddr;
5032 int igu_sp_sb_index;
5034 int port = SC_PORT(sc);
5035 int func = SC_FUNC(sc);
5036 int reg_offset, reg_offset_en5;
5039 struct hc_sp_status_block_data sp_sb_data;
5041 memset(&sp_sb_data, 0, sizeof(struct hc_sp_status_block_data));
5043 if (CHIP_INT_MODE_IS_BC(sc)) {
5044 igu_sp_sb_index = DEF_SB_IGU_ID;
5045 igu_seg_id = HC_SEG_ACCESS_DEF;
5047 igu_sp_sb_index = sc->igu_dsb_id;
5048 igu_seg_id = IGU_SEG_ACCESS_DEF;
5052 section = ((uint64_t) mapping +
5053 offsetof(struct host_sp_status_block, atten_status_block));
5054 def_sb->atten_status_block.status_block_id = igu_sp_sb_index;
5057 reg_offset = (port) ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 :
5058 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0;
5060 reg_offset_en5 = (port) ? MISC_REG_AEU_ENABLE5_FUNC_1_OUT_0 :
5061 MISC_REG_AEU_ENABLE5_FUNC_0_OUT_0;
5063 for (index = 0; index < MAX_DYNAMIC_ATTN_GRPS; index++) {
5064 /* take care of sig[0]..sig[4] */
5065 for (sindex = 0; sindex < 4; sindex++) {
5066 sc->attn_group[index].sig[sindex] =
5068 (reg_offset + (sindex * 0x4) +
5072 if (!CHIP_IS_E1x(sc)) {
5074 * enable5 is separate from the rest of the registers,
5075 * and the address skip is 4 and not 16 between the
5078 sc->attn_group[index].sig[4] =
5079 REG_RD(sc, (reg_offset_en5 + (0x4 * index)));
5081 sc->attn_group[index].sig[4] = 0;
5085 if (sc->devinfo.int_block == INT_BLOCK_HC) {
5087 port ? HC_REG_ATTN_MSG1_ADDR_L : HC_REG_ATTN_MSG0_ADDR_L;
5088 REG_WR(sc, reg_offset, U64_LO(section));
5089 REG_WR(sc, (reg_offset + 4), U64_HI(section));
5090 } else if (!CHIP_IS_E1x(sc)) {
5091 REG_WR(sc, IGU_REG_ATTN_MSG_ADDR_L, U64_LO(section));
5092 REG_WR(sc, IGU_REG_ATTN_MSG_ADDR_H, U64_HI(section));
5095 section = ((uint64_t) mapping +
5096 offsetof(struct host_sp_status_block, sp_sb));
5098 bnx2x_zero_sp_sb(sc);
5100 /* PCI guarantees endianity of regpair */
5101 sp_sb_data.state = SB_ENABLED;
5102 sp_sb_data.host_sb_addr.lo = U64_LO(section);
5103 sp_sb_data.host_sb_addr.hi = U64_HI(section);
5104 sp_sb_data.igu_sb_id = igu_sp_sb_index;
5105 sp_sb_data.igu_seg_id = igu_seg_id;
5106 sp_sb_data.p_func.pf_id = func;
5107 sp_sb_data.p_func.vnic_id = SC_VN(sc);
5108 sp_sb_data.p_func.vf_id = 0xff;
5110 bnx2x_wr_sp_sb_data(sc, &sp_sb_data);
5112 bnx2x_ack_sb(sc, sc->igu_dsb_id, USTORM_ID, 0, IGU_INT_ENABLE, 0);
5115 static void bnx2x_init_sp_ring(struct bnx2x_softc *sc)
5117 atomic_store_rel_long(&sc->cq_spq_left, MAX_SPQ_PENDING);
5118 sc->spq_prod_idx = 0;
5120 &sc->def_sb->sp_sb.index_values[HC_SP_INDEX_ETH_DEF_CONS];
5121 sc->spq_prod_bd = sc->spq;
5122 sc->spq_last_bd = (sc->spq_prod_bd + MAX_SP_DESC_CNT);
5125 static void bnx2x_init_eq_ring(struct bnx2x_softc *sc)
5127 union event_ring_elem *elem;
5130 for (i = 1; i <= NUM_EQ_PAGES; i++) {
5131 elem = &sc->eq[EQ_DESC_CNT_PAGE * i - 1];
5133 elem->next_page.addr.hi = htole32(U64_HI(sc->eq_dma.paddr +
5135 (i % NUM_EQ_PAGES)));
5136 elem->next_page.addr.lo = htole32(U64_LO(sc->eq_dma.paddr +
5138 (i % NUM_EQ_PAGES)));
5142 sc->eq_prod = NUM_EQ_DESC;
5143 sc->eq_cons_sb = &sc->def_sb->sp_sb.index_values[HC_SP_INDEX_EQ_CONS];
5145 atomic_store_rel_long(&sc->eq_spq_left,
5146 (min((MAX_SP_DESC_CNT - MAX_SPQ_PENDING),
5150 static void bnx2x_init_internal_common(struct bnx2x_softc *sc)
5156 * In switch independent mode, the TSTORM needs to accept
5157 * packets that failed classification, since approximate match
5158 * mac addresses aren't written to NIG LLH.
5161 (BAR_TSTRORM_INTMEM +
5162 TSTORM_ACCEPT_CLASSIFY_FAILED_OFFSET), 2);
5165 (BAR_TSTRORM_INTMEM +
5166 TSTORM_ACCEPT_CLASSIFY_FAILED_OFFSET), 0);
5169 * Zero this manually as its initialization is currently missing
5172 for (i = 0; i < (USTORM_AGG_DATA_SIZE >> 2); i++) {
5174 (BAR_USTRORM_INTMEM + USTORM_AGG_DATA_OFFSET + (i * 4)),
5178 if (!CHIP_IS_E1x(sc)) {
5179 REG_WR8(sc, (BAR_CSTRORM_INTMEM + CSTORM_IGU_MODE_OFFSET),
5180 CHIP_INT_MODE_IS_BC(sc) ? HC_IGU_BC_MODE :
5185 static void bnx2x_init_internal(struct bnx2x_softc *sc, uint32_t load_code)
5187 switch (load_code) {
5188 case FW_MSG_CODE_DRV_LOAD_COMMON:
5189 case FW_MSG_CODE_DRV_LOAD_COMMON_CHIP:
5190 bnx2x_init_internal_common(sc);
5193 case FW_MSG_CODE_DRV_LOAD_PORT:
5197 case FW_MSG_CODE_DRV_LOAD_FUNCTION:
5198 /* internal memory per function is initialized inside bnx2x_pf_init */
5202 PMD_DRV_LOG(NOTICE, "Unknown load_code (0x%x) from MCP",
5209 storm_memset_func_cfg(struct bnx2x_softc *sc,
5210 struct tstorm_eth_function_common_config *tcfg,
5216 addr = (BAR_TSTRORM_INTMEM +
5217 TSTORM_FUNCTION_COMMON_CONFIG_OFFSET(abs_fid));
5218 size = sizeof(struct tstorm_eth_function_common_config);
5219 ecore_storm_memset_struct(sc, addr, size, (uint32_t *) tcfg);
5222 static void bnx2x_func_init(struct bnx2x_softc *sc, struct bnx2x_func_init_params *p)
5224 struct tstorm_eth_function_common_config tcfg = { 0 };
5226 if (CHIP_IS_E1x(sc)) {
5227 storm_memset_func_cfg(sc, &tcfg, p->func_id);
5230 /* Enable the function in the FW */
5231 storm_memset_vf_to_pf(sc, p->func_id, p->pf_id);
5232 storm_memset_func_en(sc, p->func_id, 1);
5235 if (p->func_flgs & FUNC_FLG_SPQ) {
5236 storm_memset_spq_addr(sc, p->spq_map, p->func_id);
5238 (XSEM_REG_FAST_MEMORY +
5239 XSTORM_SPQ_PROD_OFFSET(p->func_id)), p->spq_prod);
5244 * Calculates the sum of vn_min_rates.
5245 * It's needed for further normalizing of the min_rates.
5247 * sum of vn_min_rates.
5249 * 0 - if all the min_rates are 0.
5250 * In the later case fainess algorithm should be deactivated.
5251 * If all min rates are not zero then those that are zeroes will be set to 1.
5253 static void bnx2x_calc_vn_min(struct bnx2x_softc *sc, struct cmng_init_input *input)
5256 uint32_t vn_min_rate;
5260 for (vn = VN_0; vn < SC_MAX_VN_NUM(sc); vn++) {
5261 vn_cfg = sc->devinfo.mf_info.mf_config[vn];
5262 vn_min_rate = (((vn_cfg & FUNC_MF_CFG_MIN_BW_MASK) >>
5263 FUNC_MF_CFG_MIN_BW_SHIFT) * 100);
5265 if (vn_cfg & FUNC_MF_CFG_FUNC_HIDE) {
5266 /* skip hidden VNs */
5268 } else if (!vn_min_rate) {
5269 /* If min rate is zero - set it to 100 */
5270 vn_min_rate = DEF_MIN_RATE;
5275 input->vnic_min_rate[vn] = vn_min_rate;
5278 /* if ETS or all min rates are zeros - disable fairness */
5280 input->flags.cmng_enables &= ~CMNG_FLAGS_PER_PORT_FAIRNESS_VN;
5282 input->flags.cmng_enables |= CMNG_FLAGS_PER_PORT_FAIRNESS_VN;
5287 bnx2x_extract_max_cfg(__rte_unused struct bnx2x_softc *sc, uint32_t mf_cfg)
5289 uint16_t max_cfg = ((mf_cfg & FUNC_MF_CFG_MAX_BW_MASK) >>
5290 FUNC_MF_CFG_MAX_BW_SHIFT);
5294 "Max BW configured to 0 - using 100 instead");
5302 bnx2x_calc_vn_max(struct bnx2x_softc *sc, int vn, struct cmng_init_input *input)
5304 uint16_t vn_max_rate;
5305 uint32_t vn_cfg = sc->devinfo.mf_info.mf_config[vn];
5308 if (vn_cfg & FUNC_MF_CFG_FUNC_HIDE) {
5311 max_cfg = bnx2x_extract_max_cfg(sc, vn_cfg);
5314 /* max_cfg in percents of linkspeed */
5316 ((sc->link_vars.line_speed * max_cfg) / 100);
5317 } else { /* SD modes */
5318 /* max_cfg is absolute in 100Mb units */
5319 vn_max_rate = (max_cfg * 100);
5323 input->vnic_max_rate[vn] = vn_max_rate;
5327 bnx2x_cmng_fns_init(struct bnx2x_softc *sc, uint8_t read_cfg, uint8_t cmng_type)
5329 struct cmng_init_input input;
5332 memset(&input, 0, sizeof(struct cmng_init_input));
5334 input.port_rate = sc->link_vars.line_speed;
5336 if (cmng_type == CMNG_FNS_MINMAX) {
5337 /* read mf conf from shmem */
5339 bnx2x_read_mf_cfg(sc);
5342 /* get VN min rate and enable fairness if not 0 */
5343 bnx2x_calc_vn_min(sc, &input);
5345 /* get VN max rate */
5347 for (vn = VN_0; vn < SC_MAX_VN_NUM(sc); vn++) {
5348 bnx2x_calc_vn_max(sc, vn, &input);
5352 /* always enable rate shaping and fairness */
5353 input.flags.cmng_enables |= CMNG_FLAGS_PER_PORT_RATE_SHAPING_VN;
5355 ecore_init_cmng(&input, &sc->cmng);
5360 static int bnx2x_get_cmng_fns_mode(struct bnx2x_softc *sc)
5362 if (CHIP_REV_IS_SLOW(sc)) {
5363 return CMNG_FNS_NONE;
5367 return CMNG_FNS_MINMAX;
5370 return CMNG_FNS_NONE;
5374 storm_memset_cmng(struct bnx2x_softc *sc, struct cmng_init *cmng, uint8_t port)
5381 addr = (BAR_XSTRORM_INTMEM + XSTORM_CMNG_PER_PORT_VARS_OFFSET(port));
5382 size = sizeof(struct cmng_struct_per_port);
5383 ecore_storm_memset_struct(sc, addr, size, (uint32_t *) & cmng->port);
5385 for (vn = VN_0; vn < SC_MAX_VN_NUM(sc); vn++) {
5386 func = func_by_vn(sc, vn);
5388 addr = (BAR_XSTRORM_INTMEM +
5389 XSTORM_RATE_SHAPING_PER_VN_VARS_OFFSET(func));
5390 size = sizeof(struct rate_shaping_vars_per_vn);
5391 ecore_storm_memset_struct(sc, addr, size,
5392 (uint32_t *) & cmng->
5393 vnic.vnic_max_rate[vn]);
5395 addr = (BAR_XSTRORM_INTMEM +
5396 XSTORM_FAIRNESS_PER_VN_VARS_OFFSET(func));
5397 size = sizeof(struct fairness_vars_per_vn);
5398 ecore_storm_memset_struct(sc, addr, size,
5399 (uint32_t *) & cmng->
5400 vnic.vnic_min_rate[vn]);
5404 static void bnx2x_pf_init(struct bnx2x_softc *sc)
5406 struct bnx2x_func_init_params func_init;
5407 struct event_ring_data eq_data;
5410 memset(&eq_data, 0, sizeof(struct event_ring_data));
5411 memset(&func_init, 0, sizeof(struct bnx2x_func_init_params));
5413 if (!CHIP_IS_E1x(sc)) {
5414 /* reset IGU PF statistics: MSIX + ATTN */
5417 (IGU_REG_STATISTIC_NUM_MESSAGE_SENT +
5418 (BNX2X_IGU_STAS_MSG_VF_CNT * 4) +
5419 ((CHIP_IS_MODE_4_PORT(sc) ? SC_FUNC(sc) : SC_VN(sc)) *
5423 (IGU_REG_STATISTIC_NUM_MESSAGE_SENT +
5424 (BNX2X_IGU_STAS_MSG_VF_CNT * 4) +
5425 (BNX2X_IGU_STAS_MSG_PF_CNT * 4) +
5426 ((CHIP_IS_MODE_4_PORT(sc) ? SC_FUNC(sc) : SC_VN(sc)) *
5430 /* function setup flags */
5431 flags = (FUNC_FLG_STATS | FUNC_FLG_LEADING | FUNC_FLG_SPQ);
5433 func_init.func_flgs = flags;
5434 func_init.pf_id = SC_FUNC(sc);
5435 func_init.func_id = SC_FUNC(sc);
5436 func_init.spq_map = sc->spq_dma.paddr;
5437 func_init.spq_prod = sc->spq_prod_idx;
5439 bnx2x_func_init(sc, &func_init);
5441 memset(&sc->cmng, 0, sizeof(struct cmng_struct_per_port));
5444 * Congestion management values depend on the link rate.
5445 * There is no active link so initial link rate is set to 10Gbps.
5446 * When the link comes up the congestion management values are
5447 * re-calculated according to the actual link rate.
5449 sc->link_vars.line_speed = SPEED_10000;
5450 bnx2x_cmng_fns_init(sc, TRUE, bnx2x_get_cmng_fns_mode(sc));
5452 /* Only the PMF sets the HW */
5454 storm_memset_cmng(sc, &sc->cmng, SC_PORT(sc));
5457 /* init Event Queue - PCI bus guarantees correct endainity */
5458 eq_data.base_addr.hi = U64_HI(sc->eq_dma.paddr);
5459 eq_data.base_addr.lo = U64_LO(sc->eq_dma.paddr);
5460 eq_data.producer = sc->eq_prod;
5461 eq_data.index_id = HC_SP_INDEX_EQ_CONS;
5462 eq_data.sb_id = DEF_SB_ID;
5463 storm_memset_eq_data(sc, &eq_data, SC_FUNC(sc));
5466 static void bnx2x_hc_int_enable(struct bnx2x_softc *sc)
5468 int port = SC_PORT(sc);
5469 uint32_t addr = (port) ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0;
5470 uint32_t val = REG_RD(sc, addr);
5471 uint8_t msix = (sc->interrupt_mode == INTR_MODE_MSIX)
5472 || (sc->interrupt_mode == INTR_MODE_SINGLE_MSIX);
5473 uint8_t single_msix = (sc->interrupt_mode == INTR_MODE_SINGLE_MSIX);
5474 uint8_t msi = (sc->interrupt_mode == INTR_MODE_MSI);
5477 val &= ~(HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
5478 HC_CONFIG_0_REG_INT_LINE_EN_0);
5479 val |= (HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
5480 HC_CONFIG_0_REG_ATTN_BIT_EN_0);
5482 val |= HC_CONFIG_0_REG_SINGLE_ISR_EN_0;
5485 val &= ~HC_CONFIG_0_REG_INT_LINE_EN_0;
5486 val |= (HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
5487 HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
5488 HC_CONFIG_0_REG_ATTN_BIT_EN_0);
5490 val |= (HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
5491 HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
5492 HC_CONFIG_0_REG_INT_LINE_EN_0 |
5493 HC_CONFIG_0_REG_ATTN_BIT_EN_0);
5495 REG_WR(sc, addr, val);
5497 val &= ~HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0;
5500 REG_WR(sc, addr, val);
5502 /* ensure that HC_CONFIG is written before leading/trailing edge config */
5505 /* init leading/trailing edge */
5507 val = (0xee0f | (1 << (SC_VN(sc) + 4)));
5509 /* enable nig and gpio3 attention */
5516 REG_WR(sc, (HC_REG_TRAILING_EDGE_0 + port * 8), val);
5517 REG_WR(sc, (HC_REG_LEADING_EDGE_0 + port * 8), val);
5519 /* make sure that interrupts are indeed enabled from here on */
5523 static void bnx2x_igu_int_enable(struct bnx2x_softc *sc)
5526 uint8_t msix = (sc->interrupt_mode == INTR_MODE_MSIX)
5527 || (sc->interrupt_mode == INTR_MODE_SINGLE_MSIX);
5528 uint8_t single_msix = (sc->interrupt_mode == INTR_MODE_SINGLE_MSIX);
5529 uint8_t msi = (sc->interrupt_mode == INTR_MODE_MSI);
5531 val = REG_RD(sc, IGU_REG_PF_CONFIGURATION);
5534 val &= ~(IGU_PF_CONF_INT_LINE_EN | IGU_PF_CONF_SINGLE_ISR_EN);
5535 val |= (IGU_PF_CONF_MSI_MSIX_EN | IGU_PF_CONF_ATTN_BIT_EN);
5537 val |= IGU_PF_CONF_SINGLE_ISR_EN;
5540 val &= ~IGU_PF_CONF_INT_LINE_EN;
5541 val |= (IGU_PF_CONF_MSI_MSIX_EN |
5542 IGU_PF_CONF_ATTN_BIT_EN | IGU_PF_CONF_SINGLE_ISR_EN);
5544 val &= ~IGU_PF_CONF_MSI_MSIX_EN;
5545 val |= (IGU_PF_CONF_INT_LINE_EN |
5546 IGU_PF_CONF_ATTN_BIT_EN | IGU_PF_CONF_SINGLE_ISR_EN);
5549 /* clean previous status - need to configure igu prior to ack */
5550 if ((!msix) || single_msix) {
5551 REG_WR(sc, IGU_REG_PF_CONFIGURATION, val);
5555 val |= IGU_PF_CONF_FUNC_EN;
5557 PMD_DRV_LOG(DEBUG, "write 0x%x to IGU mode %s",
5558 val, ((msix) ? "MSI-X" : ((msi) ? "MSI" : "INTx")));
5560 REG_WR(sc, IGU_REG_PF_CONFIGURATION, val);
5564 /* init leading/trailing edge */
5566 val = (0xee0f | (1 << (SC_VN(sc) + 4)));
5568 /* enable nig and gpio3 attention */
5575 REG_WR(sc, IGU_REG_TRAILING_EDGE_LATCH, val);
5576 REG_WR(sc, IGU_REG_LEADING_EDGE_LATCH, val);
5578 /* make sure that interrupts are indeed enabled from here on */
5582 static void bnx2x_int_enable(struct bnx2x_softc *sc)
5584 if (sc->devinfo.int_block == INT_BLOCK_HC) {
5585 bnx2x_hc_int_enable(sc);
5587 bnx2x_igu_int_enable(sc);
5591 static void bnx2x_hc_int_disable(struct bnx2x_softc *sc)
5593 int port = SC_PORT(sc);
5594 uint32_t addr = (port) ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0;
5595 uint32_t val = REG_RD(sc, addr);
5597 val &= ~(HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
5598 HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
5599 HC_CONFIG_0_REG_INT_LINE_EN_0 | HC_CONFIG_0_REG_ATTN_BIT_EN_0);
5600 /* flush all outstanding writes */
5603 REG_WR(sc, addr, val);
5604 if (REG_RD(sc, addr) != val) {
5605 PMD_DRV_LOG(ERR, "proper val not read from HC IGU!");
5609 static void bnx2x_igu_int_disable(struct bnx2x_softc *sc)
5611 uint32_t val = REG_RD(sc, IGU_REG_PF_CONFIGURATION);
5613 val &= ~(IGU_PF_CONF_MSI_MSIX_EN |
5614 IGU_PF_CONF_INT_LINE_EN | IGU_PF_CONF_ATTN_BIT_EN);
5616 PMD_DRV_LOG(DEBUG, "write %x to IGU", val);
5618 /* flush all outstanding writes */
5621 REG_WR(sc, IGU_REG_PF_CONFIGURATION, val);
5622 if (REG_RD(sc, IGU_REG_PF_CONFIGURATION) != val) {
5623 PMD_DRV_LOG(ERR, "proper val not read from IGU!");
5627 static void bnx2x_int_disable(struct bnx2x_softc *sc)
5629 if (sc->devinfo.int_block == INT_BLOCK_HC) {
5630 bnx2x_hc_int_disable(sc);
5632 bnx2x_igu_int_disable(sc);
5636 static void bnx2x_nic_init(struct bnx2x_softc *sc, int load_code)
5640 PMD_INIT_FUNC_TRACE();
5642 for (i = 0; i < sc->num_queues; i++) {
5643 bnx2x_init_eth_fp(sc, i);
5646 rmb(); /* ensure status block indices were read */
5648 bnx2x_init_rx_rings(sc);
5649 bnx2x_init_tx_rings(sc);
5652 bnx2x_memset_stats(sc);
5656 /* initialize MOD_ABS interrupts */
5657 elink_init_mod_abs_int(sc, &sc->link_vars,
5658 sc->devinfo.chip_id,
5659 sc->devinfo.shmem_base,
5660 sc->devinfo.shmem2_base, SC_PORT(sc));
5662 bnx2x_init_def_sb(sc);
5663 bnx2x_update_dsb_idx(sc);
5664 bnx2x_init_sp_ring(sc);
5665 bnx2x_init_eq_ring(sc);
5666 bnx2x_init_internal(sc, load_code);
5668 bnx2x_stats_init(sc);
5670 /* flush all before enabling interrupts */
5673 bnx2x_int_enable(sc);
5675 /* check for SPIO5 */
5676 bnx2x_attn_int_deasserted0(sc,
5678 (MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 +
5680 AEU_INPUTS_ATTN_BITS_SPIO5);
5683 static void bnx2x_init_objs(struct bnx2x_softc *sc)
5685 /* mcast rules must be added to tx if tx switching is enabled */
5686 ecore_obj_type o_type;
5687 if (sc->flags & BNX2X_TX_SWITCHING)
5688 o_type = ECORE_OBJ_TYPE_RX_TX;
5690 o_type = ECORE_OBJ_TYPE_RX;
5692 /* RX_MODE controlling object */
5693 ecore_init_rx_mode_obj(sc, &sc->rx_mode_obj);
5695 /* multicast configuration controlling object */
5696 ecore_init_mcast_obj(sc,
5702 BNX2X_SP(sc, mcast_rdata),
5703 (phys_addr_t)BNX2X_SP_MAPPING(sc, mcast_rdata),
5704 ECORE_FILTER_MCAST_PENDING,
5705 &sc->sp_state, o_type);
5707 /* Setup CAM credit pools */
5708 ecore_init_mac_credit_pool(sc,
5711 CHIP_IS_E1x(sc) ? VNICS_PER_PORT(sc) :
5712 VNICS_PER_PATH(sc));
5714 ecore_init_vlan_credit_pool(sc,
5716 SC_ABS_FUNC(sc) >> 1,
5717 CHIP_IS_E1x(sc) ? VNICS_PER_PORT(sc) :
5718 VNICS_PER_PATH(sc));
5720 /* RSS configuration object */
5721 ecore_init_rss_config_obj(&sc->rss_conf_obj,
5726 BNX2X_SP(sc, rss_rdata),
5727 (phys_addr_t)BNX2X_SP_MAPPING(sc, rss_rdata),
5728 ECORE_FILTER_RSS_CONF_PENDING,
5729 &sc->sp_state, ECORE_OBJ_TYPE_RX);
5733 * Initialize the function. This must be called before sending CLIENT_SETUP
5734 * for the first client.
5736 static int bnx2x_func_start(struct bnx2x_softc *sc)
5738 struct ecore_func_state_params func_params = { NULL };
5739 struct ecore_func_start_params *start_params =
5740 &func_params.params.start;
5742 /* Prepare parameters for function state transitions */
5743 bnx2x_set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags);
5745 func_params.f_obj = &sc->func_obj;
5746 func_params.cmd = ECORE_F_CMD_START;
5748 /* Function parameters */
5749 start_params->mf_mode = sc->devinfo.mf_info.mf_mode;
5750 start_params->sd_vlan_tag = OVLAN(sc);
5752 if (CHIP_IS_E2(sc) || CHIP_IS_E3(sc)) {
5753 start_params->network_cos_mode = STATIC_COS;
5754 } else { /* CHIP_IS_E1X */
5755 start_params->network_cos_mode = FW_WRR;
5758 start_params->gre_tunnel_mode = 0;
5759 start_params->gre_tunnel_rss = 0;
5761 return ecore_func_state_change(sc, &func_params);
5764 static int bnx2x_set_power_state(struct bnx2x_softc *sc, uint8_t state)
5768 /* If there is no power capability, silently succeed */
5769 if (!(sc->devinfo.pcie_cap_flags & BNX2X_PM_CAPABLE_FLAG)) {
5770 PMD_DRV_LOG(WARNING, "No power capability");
5774 pci_read(sc, (sc->devinfo.pcie_pm_cap_reg + PCIR_POWER_STATUS), &pmcsr,
5780 (sc->devinfo.pcie_pm_cap_reg +
5782 ((pmcsr & ~PCIM_PSTAT_DMASK) | PCIM_PSTAT_PME));
5784 if (pmcsr & PCIM_PSTAT_DMASK) {
5785 /* delay required during transition out of D3hot */
5792 /* don't shut down the power for emulation and FPGA */
5793 if (CHIP_REV_IS_SLOW(sc)) {
5797 pmcsr &= ~PCIM_PSTAT_DMASK;
5798 pmcsr |= PCIM_PSTAT_D3;
5801 pmcsr |= PCIM_PSTAT_PMEENABLE;
5805 (sc->devinfo.pcie_pm_cap_reg +
5806 PCIR_POWER_STATUS), pmcsr);
5809 * No more memory access after this point until device is brought back
5815 PMD_DRV_LOG(NOTICE, "Can't support PCI power state = %d",
5823 /* return true if succeeded to acquire the lock */
5824 static uint8_t bnx2x_trylock_hw_lock(struct bnx2x_softc *sc, uint32_t resource)
5826 uint32_t lock_status;
5827 uint32_t resource_bit = (1 << resource);
5828 int func = SC_FUNC(sc);
5829 uint32_t hw_lock_control_reg;
5831 /* Validating that the resource is within range */
5832 if (resource > HW_LOCK_MAX_RESOURCE_VALUE) {
5834 "resource(0x%x) > HW_LOCK_MAX_RESOURCE_VALUE(0x%x)",
5835 resource, HW_LOCK_MAX_RESOURCE_VALUE);
5840 hw_lock_control_reg = (MISC_REG_DRIVER_CONTROL_1 + func * 8);
5842 hw_lock_control_reg =
5843 (MISC_REG_DRIVER_CONTROL_7 + (func - 6) * 8);
5846 /* try to acquire the lock */
5847 REG_WR(sc, hw_lock_control_reg + 4, resource_bit);
5848 lock_status = REG_RD(sc, hw_lock_control_reg);
5849 if (lock_status & resource_bit) {
5853 PMD_DRV_LOG(NOTICE, "Failed to get a resource lock 0x%x", resource);
5859 * Get the recovery leader resource id according to the engine this function
5860 * belongs to. Currently only only 2 engines is supported.
5862 static int bnx2x_get_leader_lock_resource(struct bnx2x_softc *sc)
5865 return HW_LOCK_RESOURCE_RECOVERY_LEADER_1;
5867 return HW_LOCK_RESOURCE_RECOVERY_LEADER_0;
5871 /* try to acquire a leader lock for current engine */
5872 static uint8_t bnx2x_trylock_leader_lock(struct bnx2x_softc *sc)
5874 return bnx2x_trylock_hw_lock(sc, bnx2x_get_leader_lock_resource(sc));
5877 static int bnx2x_release_leader_lock(struct bnx2x_softc *sc)
5879 return bnx2x_release_hw_lock(sc, bnx2x_get_leader_lock_resource(sc));
5882 /* close gates #2, #3 and #4 */
5883 static void bnx2x_set_234_gates(struct bnx2x_softc *sc, uint8_t close)
5887 /* gates #2 and #4a are closed/opened */
5889 REG_WR(sc, PXP_REG_HST_DISCARD_DOORBELLS, ! !close);
5891 REG_WR(sc, PXP_REG_HST_DISCARD_INTERNAL_WRITES, ! !close);
5894 if (CHIP_IS_E1x(sc)) {
5895 /* prevent interrupts from HC on both ports */
5896 val = REG_RD(sc, HC_REG_CONFIG_1);
5898 REG_WR(sc, HC_REG_CONFIG_1, (val & ~(uint32_t)
5899 HC_CONFIG_1_REG_BLOCK_DISABLE_1));
5901 REG_WR(sc, HC_REG_CONFIG_1,
5902 (val | HC_CONFIG_1_REG_BLOCK_DISABLE_1));
5904 val = REG_RD(sc, HC_REG_CONFIG_0);
5906 REG_WR(sc, HC_REG_CONFIG_0, (val & ~(uint32_t)
5907 HC_CONFIG_0_REG_BLOCK_DISABLE_0));
5909 REG_WR(sc, HC_REG_CONFIG_0,
5910 (val | HC_CONFIG_0_REG_BLOCK_DISABLE_0));
5913 /* Prevent incoming interrupts in IGU */
5914 val = REG_RD(sc, IGU_REG_BLOCK_CONFIGURATION);
5917 REG_WR(sc, IGU_REG_BLOCK_CONFIGURATION,
5919 IGU_BLOCK_CONFIGURATION_REG_BLOCK_ENABLE));
5921 REG_WR(sc, IGU_REG_BLOCK_CONFIGURATION,
5923 IGU_BLOCK_CONFIGURATION_REG_BLOCK_ENABLE));
5929 /* poll for pending writes bit, it should get cleared in no more than 1s */
5930 static int bnx2x_er_poll_igu_vq(struct bnx2x_softc *sc)
5932 uint32_t cnt = 1000;
5933 uint32_t pend_bits = 0;
5936 pend_bits = REG_RD(sc, IGU_REG_PENDING_BITS_STATUS);
5938 if (pend_bits == 0) {
5943 } while (cnt-- > 0);
5946 PMD_DRV_LOG(NOTICE, "Still pending IGU requests bits=0x%08x!",
5954 #define SHARED_MF_CLP_MAGIC 0x80000000 /* 'magic' bit */
5956 static void bnx2x_clp_reset_prep(struct bnx2x_softc *sc, uint32_t * magic_val)
5958 /* Do some magic... */
5959 uint32_t val = MFCFG_RD(sc, shared_mf_config.clp_mb);
5960 *magic_val = val & SHARED_MF_CLP_MAGIC;
5961 MFCFG_WR(sc, shared_mf_config.clp_mb, val | SHARED_MF_CLP_MAGIC);
5964 /* restore the value of the 'magic' bit */
5965 static void bnx2x_clp_reset_done(struct bnx2x_softc *sc, uint32_t magic_val)
5967 /* Restore the 'magic' bit value... */
5968 uint32_t val = MFCFG_RD(sc, shared_mf_config.clp_mb);
5969 MFCFG_WR(sc, shared_mf_config.clp_mb,
5970 (val & (~SHARED_MF_CLP_MAGIC)) | magic_val);
5973 /* prepare for MCP reset, takes care of CLP configurations */
5974 static void bnx2x_reset_mcp_prep(struct bnx2x_softc *sc, uint32_t * magic_val)
5977 uint32_t validity_offset;
5979 /* set `magic' bit in order to save MF config */
5980 bnx2x_clp_reset_prep(sc, magic_val);
5982 /* get shmem offset */
5983 shmem = REG_RD(sc, MISC_REG_SHARED_MEM_ADDR);
5985 offsetof(struct shmem_region, validity_map[SC_PORT(sc)]);
5987 /* Clear validity map flags */
5989 REG_WR(sc, shmem + validity_offset, 0);
5993 #define MCP_TIMEOUT 5000 /* 5 seconds (in ms) */
5994 #define MCP_ONE_TIMEOUT 100 /* 100 ms */
5996 static void bnx2x_mcp_wait_one(struct bnx2x_softc *sc)
5998 /* special handling for emulation and FPGA (10 times longer) */
5999 if (CHIP_REV_IS_SLOW(sc)) {
6000 DELAY((MCP_ONE_TIMEOUT * 10) * 1000);
6002 DELAY((MCP_ONE_TIMEOUT) * 1000);
6006 /* initialize shmem_base and waits for validity signature to appear */
6007 static int bnx2x_init_shmem(struct bnx2x_softc *sc)
6013 sc->devinfo.shmem_base =
6014 sc->link_params.shmem_base =
6015 REG_RD(sc, MISC_REG_SHARED_MEM_ADDR);
6017 if (sc->devinfo.shmem_base) {
6018 val = SHMEM_RD(sc, validity_map[SC_PORT(sc)]);
6019 if (val & SHR_MEM_VALIDITY_MB)
6023 bnx2x_mcp_wait_one(sc);
6025 } while (cnt++ < (MCP_TIMEOUT / MCP_ONE_TIMEOUT));
6027 PMD_DRV_LOG(NOTICE, "BAD MCP validity signature");
6032 static int bnx2x_reset_mcp_comp(struct bnx2x_softc *sc, uint32_t magic_val)
6034 int rc = bnx2x_init_shmem(sc);
6036 /* Restore the `magic' bit value */
6037 bnx2x_clp_reset_done(sc, magic_val);
6042 static void bnx2x_pxp_prep(struct bnx2x_softc *sc)
6044 REG_WR(sc, PXP2_REG_RD_START_INIT, 0);
6045 REG_WR(sc, PXP2_REG_RQ_RBC_DONE, 0);
6050 * Reset the whole chip except for:
6052 * - PCI Glue, PSWHST, PXP/PXP2 RF (all controlled by one reset bit)
6054 * - MISC (including AEU)
6058 static void bnx2x_process_kill_chip_reset(struct bnx2x_softc *sc, uint8_t global)
6060 uint32_t not_reset_mask1, reset_mask1, not_reset_mask2, reset_mask2;
6061 uint32_t global_bits2, stay_reset2;
6064 * Bits that have to be set in reset_mask2 if we want to reset 'global'
6065 * (per chip) blocks.
6068 MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_CMN_CPU |
6069 MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_CMN_CORE;
6072 * Don't reset the following blocks.
6073 * Important: per port blocks (such as EMAC, BMAC, UMAC) can't be
6074 * reset, as in 4 port device they might still be owned
6075 * by the MCP (there is only one leader per path).
6078 MISC_REGISTERS_RESET_REG_1_RST_HC |
6079 MISC_REGISTERS_RESET_REG_1_RST_PXPV |
6080 MISC_REGISTERS_RESET_REG_1_RST_PXP;
6083 MISC_REGISTERS_RESET_REG_2_RST_PCI_MDIO |
6084 MISC_REGISTERS_RESET_REG_2_RST_EMAC0_HARD_CORE |
6085 MISC_REGISTERS_RESET_REG_2_RST_EMAC1_HARD_CORE |
6086 MISC_REGISTERS_RESET_REG_2_RST_MISC_CORE |
6087 MISC_REGISTERS_RESET_REG_2_RST_RBCN |
6088 MISC_REGISTERS_RESET_REG_2_RST_GRC |
6089 MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_REG_HARD_CORE |
6090 MISC_REGISTERS_RESET_REG_2_RST_MCP_N_HARD_CORE_RST_B |
6091 MISC_REGISTERS_RESET_REG_2_RST_ATC |
6092 MISC_REGISTERS_RESET_REG_2_PGLC |
6093 MISC_REGISTERS_RESET_REG_2_RST_BMAC0 |
6094 MISC_REGISTERS_RESET_REG_2_RST_BMAC1 |
6095 MISC_REGISTERS_RESET_REG_2_RST_EMAC0 |
6096 MISC_REGISTERS_RESET_REG_2_RST_EMAC1 |
6097 MISC_REGISTERS_RESET_REG_2_UMAC0 | MISC_REGISTERS_RESET_REG_2_UMAC1;
6100 * Keep the following blocks in reset:
6101 * - all xxMACs are handled by the elink code.
6104 MISC_REGISTERS_RESET_REG_2_XMAC |
6105 MISC_REGISTERS_RESET_REG_2_XMAC_SOFT;
6107 /* Full reset masks according to the chip */
6108 reset_mask1 = 0xffffffff;
6110 if (CHIP_IS_E1H(sc))
6111 reset_mask2 = 0x1ffff;
6112 else if (CHIP_IS_E2(sc))
6113 reset_mask2 = 0xfffff;
6114 else /* CHIP_IS_E3 */
6115 reset_mask2 = 0x3ffffff;
6117 /* Don't reset global blocks unless we need to */
6119 reset_mask2 &= ~global_bits2;
6122 * In case of attention in the QM, we need to reset PXP
6123 * (MISC_REGISTERS_RESET_REG_2_RST_PXP_RQ_RD_WR) before QM
6124 * because otherwise QM reset would release 'close the gates' shortly
6125 * before resetting the PXP, then the PSWRQ would send a write
6126 * request to PGLUE. Then when PXP is reset, PGLUE would try to
6127 * read the payload data from PSWWR, but PSWWR would not
6128 * respond. The write queue in PGLUE would stuck, dmae commands
6129 * would not return. Therefore it's important to reset the second
6130 * reset register (containing the
6131 * MISC_REGISTERS_RESET_REG_2_RST_PXP_RQ_RD_WR bit) before the
6132 * first one (containing the MISC_REGISTERS_RESET_REG_1_RST_QM
6135 REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
6136 reset_mask2 & (~not_reset_mask2));
6138 REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR,
6139 reset_mask1 & (~not_reset_mask1));
6144 REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET,
6145 reset_mask2 & (~stay_reset2));
6150 REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, reset_mask1);
6154 static int bnx2x_process_kill(struct bnx2x_softc *sc, uint8_t global)
6158 uint32_t sr_cnt, blk_cnt, port_is_idle_0, port_is_idle_1, pgl_exp_rom2;
6159 uint32_t tags_63_32 = 0;
6161 /* Empty the Tetris buffer, wait for 1s */
6163 sr_cnt = REG_RD(sc, PXP2_REG_RD_SR_CNT);
6164 blk_cnt = REG_RD(sc, PXP2_REG_RD_BLK_CNT);
6165 port_is_idle_0 = REG_RD(sc, PXP2_REG_RD_PORT_IS_IDLE_0);
6166 port_is_idle_1 = REG_RD(sc, PXP2_REG_RD_PORT_IS_IDLE_1);
6167 pgl_exp_rom2 = REG_RD(sc, PXP2_REG_PGL_EXP_ROM2);
6168 if (CHIP_IS_E3(sc)) {
6169 tags_63_32 = REG_RD(sc, PGLUE_B_REG_TAGS_63_32);
6172 if ((sr_cnt == 0x7e) && (blk_cnt == 0xa0) &&
6173 ((port_is_idle_0 & 0x1) == 0x1) &&
6174 ((port_is_idle_1 & 0x1) == 0x1) &&
6175 (pgl_exp_rom2 == 0xffffffff) &&
6176 (!CHIP_IS_E3(sc) || (tags_63_32 == 0xffffffff)))
6179 } while (cnt-- > 0);
6183 "ERROR: Tetris buffer didn't get empty or there "
6184 "are still outstanding read requests after 1s! "
6185 "sr_cnt=0x%08x, blk_cnt=0x%08x, port_is_idle_0=0x%08x, "
6186 "port_is_idle_1=0x%08x, pgl_exp_rom2=0x%08x",
6187 sr_cnt, blk_cnt, port_is_idle_0, port_is_idle_1,
6194 /* Close gates #2, #3 and #4 */
6195 bnx2x_set_234_gates(sc, TRUE);
6197 /* Poll for IGU VQs for 57712 and newer chips */
6198 if (!CHIP_IS_E1x(sc) && bnx2x_er_poll_igu_vq(sc)) {
6202 /* clear "unprepared" bit */
6203 REG_WR(sc, MISC_REG_UNPREPARED, 0);
6206 /* Make sure all is written to the chip before the reset */
6210 * Wait for 1ms to empty GLUE and PCI-E core queues,
6211 * PSWHST, GRC and PSWRD Tetris buffer.
6215 /* Prepare to chip reset: */
6218 bnx2x_reset_mcp_prep(sc, &val);
6225 /* reset the chip */
6226 bnx2x_process_kill_chip_reset(sc, global);
6229 /* Recover after reset: */
6231 if (global && bnx2x_reset_mcp_comp(sc, val)) {
6235 /* Open the gates #2, #3 and #4 */
6236 bnx2x_set_234_gates(sc, FALSE);
6241 static int bnx2x_leader_reset(struct bnx2x_softc *sc)
6244 uint8_t global = bnx2x_reset_is_global(sc);
6248 * If not going to reset MCP, load "fake" driver to reset HW while
6249 * driver is owner of the HW.
6251 if (!global && !BNX2X_NOMCP(sc)) {
6252 load_code = bnx2x_fw_command(sc, DRV_MSG_CODE_LOAD_REQ,
6253 DRV_MSG_CODE_LOAD_REQ_WITH_LFA);
6255 PMD_DRV_LOG(NOTICE, "MCP response failure, aborting");
6257 goto exit_leader_reset;
6260 if ((load_code != FW_MSG_CODE_DRV_LOAD_COMMON_CHIP) &&
6261 (load_code != FW_MSG_CODE_DRV_LOAD_COMMON)) {
6263 "MCP unexpected response, aborting");
6265 goto exit_leader_reset2;
6268 load_code = bnx2x_fw_command(sc, DRV_MSG_CODE_LOAD_DONE, 0);
6270 PMD_DRV_LOG(NOTICE, "MCP response failure, aborting");
6272 goto exit_leader_reset2;
6276 /* try to recover after the failure */
6277 if (bnx2x_process_kill(sc, global)) {
6278 PMD_DRV_LOG(NOTICE, "Something bad occurred on engine %d!",
6281 goto exit_leader_reset2;
6285 * Clear the RESET_IN_PROGRESS and RESET_GLOBAL bits and update the driver
6288 bnx2x_set_reset_done(sc);
6290 bnx2x_clear_reset_global(sc);
6295 /* unload "fake driver" if it was loaded */
6296 if (!global &&!BNX2X_NOMCP(sc)) {
6297 bnx2x_fw_command(sc, DRV_MSG_CODE_UNLOAD_REQ_WOL_MCP, 0);
6298 bnx2x_fw_command(sc, DRV_MSG_CODE_UNLOAD_DONE, 0);
6304 bnx2x_release_leader_lock(sc);
6311 * prepare INIT transition, parameters configured:
6312 * - HC configuration
6313 * - Queue's CDU context
6316 bnx2x_pf_q_prep_init(struct bnx2x_softc *sc, struct bnx2x_fastpath *fp,
6317 struct ecore_queue_init_params *init_params)
6320 int cxt_index, cxt_offset;
6322 bnx2x_set_bit(ECORE_Q_FLG_HC, &init_params->rx.flags);
6323 bnx2x_set_bit(ECORE_Q_FLG_HC, &init_params->tx.flags);
6325 bnx2x_set_bit(ECORE_Q_FLG_HC_EN, &init_params->rx.flags);
6326 bnx2x_set_bit(ECORE_Q_FLG_HC_EN, &init_params->tx.flags);
6329 init_params->rx.hc_rate =
6330 sc->hc_rx_ticks ? (1000000 / sc->hc_rx_ticks) : 0;
6331 init_params->tx.hc_rate =
6332 sc->hc_tx_ticks ? (1000000 / sc->hc_tx_ticks) : 0;
6335 init_params->rx.fw_sb_id = init_params->tx.fw_sb_id = fp->fw_sb_id;
6337 /* CQ index among the SB indices */
6338 init_params->rx.sb_cq_index = HC_INDEX_ETH_RX_CQ_CONS;
6339 init_params->tx.sb_cq_index = HC_INDEX_ETH_FIRST_TX_CQ_CONS;
6341 /* set maximum number of COSs supported by this queue */
6342 init_params->max_cos = sc->max_cos;
6344 /* set the context pointers queue object */
6345 for (cos = FIRST_TX_COS_INDEX; cos < init_params->max_cos; cos++) {
6346 cxt_index = fp->index / ILT_PAGE_CIDS;
6347 cxt_offset = fp->index - (cxt_index * ILT_PAGE_CIDS);
6348 init_params->cxts[cos] =
6349 &sc->context[cxt_index].vcxt[cxt_offset].eth;
6353 /* set flags that are common for the Tx-only and not normal connections */
6354 static unsigned long
6355 bnx2x_get_common_flags(struct bnx2x_softc *sc, uint8_t zero_stats)
6357 unsigned long flags = 0;
6359 /* PF driver will always initialize the Queue to an ACTIVE state */
6360 bnx2x_set_bit(ECORE_Q_FLG_ACTIVE, &flags);
6363 * tx only connections collect statistics (on the same index as the
6364 * parent connection). The statistics are zeroed when the parent
6365 * connection is initialized.
6368 bnx2x_set_bit(ECORE_Q_FLG_STATS, &flags);
6370 bnx2x_set_bit(ECORE_Q_FLG_ZERO_STATS, &flags);
6374 * tx only connections can support tx-switching, though their
6375 * CoS-ness doesn't survive the loopback
6377 if (sc->flags & BNX2X_TX_SWITCHING) {
6378 bnx2x_set_bit(ECORE_Q_FLG_TX_SWITCH, &flags);
6381 bnx2x_set_bit(ECORE_Q_FLG_PCSUM_ON_PKT, &flags);
6386 static unsigned long bnx2x_get_q_flags(struct bnx2x_softc *sc, uint8_t leading)
6388 unsigned long flags = 0;
6391 bnx2x_set_bit(ECORE_Q_FLG_OV, &flags);
6395 bnx2x_set_bit(ECORE_Q_FLG_LEADING_RSS, &flags);
6396 bnx2x_set_bit(ECORE_Q_FLG_MCAST, &flags);
6399 bnx2x_set_bit(ECORE_Q_FLG_VLAN, &flags);
6401 /* merge with common flags */
6402 return flags | bnx2x_get_common_flags(sc, TRUE);
6406 bnx2x_pf_q_prep_general(struct bnx2x_softc *sc, struct bnx2x_fastpath *fp,
6407 struct ecore_general_setup_params *gen_init, uint8_t cos)
6409 gen_init->stat_id = bnx2x_stats_id(fp);
6410 gen_init->spcl_id = fp->cl_id;
6411 gen_init->mtu = sc->mtu;
6412 gen_init->cos = cos;
6416 bnx2x_pf_rx_q_prep(struct bnx2x_softc *sc, struct bnx2x_fastpath *fp,
6417 struct rxq_pause_params *pause,
6418 struct ecore_rxq_setup_params *rxq_init)
6420 struct bnx2x_rx_queue *rxq;
6422 rxq = sc->rx_queues[fp->index];
6424 PMD_RX_LOG(ERR, "RX queue is NULL");
6428 pause->bd_th_lo = BD_TH_LO(sc);
6429 pause->bd_th_hi = BD_TH_HI(sc);
6431 pause->rcq_th_lo = RCQ_TH_LO(sc);
6432 pause->rcq_th_hi = RCQ_TH_HI(sc);
6434 /* validate rings have enough entries to cross high thresholds */
6435 if (sc->dropless_fc &&
6436 pause->bd_th_hi + FW_PREFETCH_CNT > sc->rx_ring_size) {
6437 PMD_DRV_LOG(WARNING, "rx bd ring threshold limit");
6440 if (sc->dropless_fc &&
6441 pause->rcq_th_hi + FW_PREFETCH_CNT > USABLE_RCQ_ENTRIES(rxq)) {
6442 PMD_DRV_LOG(WARNING, "rcq ring threshold limit");
6448 rxq_init->dscr_map = (phys_addr_t)rxq->rx_ring_phys_addr;
6449 rxq_init->rcq_map = (phys_addr_t)rxq->cq_ring_phys_addr;
6450 rxq_init->rcq_np_map = (phys_addr_t)(rxq->cq_ring_phys_addr +
6454 * This should be a maximum number of data bytes that may be
6455 * placed on the BD (not including paddings).
6457 rxq_init->buf_sz = (fp->rx_buf_size - IP_HEADER_ALIGNMENT_PADDING);
6459 rxq_init->cl_qzone_id = fp->cl_qzone_id;
6460 rxq_init->rss_engine_id = SC_FUNC(sc);
6461 rxq_init->mcast_engine_id = SC_FUNC(sc);
6463 rxq_init->cache_line_log = BNX2X_RX_ALIGN_SHIFT;
6464 rxq_init->fw_sb_id = fp->fw_sb_id;
6466 rxq_init->sb_cq_index = HC_INDEX_ETH_RX_CQ_CONS;
6469 * configure silent vlan removal
6470 * if multi function mode is afex, then mask default vlan
6472 if (IS_MF_AFEX(sc)) {
6473 rxq_init->silent_removal_value =
6474 sc->devinfo.mf_info.afex_def_vlan_tag;
6475 rxq_init->silent_removal_mask = EVL_VLID_MASK;
6480 bnx2x_pf_tx_q_prep(struct bnx2x_softc *sc, struct bnx2x_fastpath *fp,
6481 struct ecore_txq_setup_params *txq_init, uint8_t cos)
6483 struct bnx2x_tx_queue *txq = fp->sc->tx_queues[fp->index];
6486 PMD_TX_LOG(ERR, "ERROR: TX queue is NULL");
6489 txq_init->dscr_map = (phys_addr_t)txq->tx_ring_phys_addr;
6490 txq_init->sb_cq_index = HC_INDEX_ETH_FIRST_TX_CQ_CONS + cos;
6491 txq_init->traffic_type = LLFC_TRAFFIC_TYPE_NW;
6492 txq_init->fw_sb_id = fp->fw_sb_id;
6495 * set the TSS leading client id for TX classfication to the
6496 * leading RSS client id
6498 txq_init->tss_leading_cl_id = BNX2X_FP(sc, 0, cl_id);
6502 * This function performs 2 steps in a queue state machine:
6507 bnx2x_setup_queue(struct bnx2x_softc *sc, struct bnx2x_fastpath *fp, uint8_t leading)
6509 struct ecore_queue_state_params q_params = { NULL };
6510 struct ecore_queue_setup_params *setup_params = &q_params.params.setup;
6513 PMD_DRV_LOG(DEBUG, "setting up queue %d", fp->index);
6515 bnx2x_ack_sb(sc, fp->igu_sb_id, USTORM_ID, 0, IGU_INT_ENABLE, 0);
6517 q_params.q_obj = &BNX2X_SP_OBJ(sc, fp).q_obj;
6519 /* we want to wait for completion in this context */
6520 bnx2x_set_bit(RAMROD_COMP_WAIT, &q_params.ramrod_flags);
6522 /* prepare the INIT parameters */
6523 bnx2x_pf_q_prep_init(sc, fp, &q_params.params.init);
6525 /* Set the command */
6526 q_params.cmd = ECORE_Q_CMD_INIT;
6528 /* Change the state to INIT */
6529 rc = ecore_queue_state_change(sc, &q_params);
6531 PMD_DRV_LOG(NOTICE, "Queue(%d) INIT failed", fp->index);
6535 PMD_DRV_LOG(DEBUG, "init complete");
6537 /* now move the Queue to the SETUP state */
6538 memset(setup_params, 0, sizeof(*setup_params));
6540 /* set Queue flags */
6541 setup_params->flags = bnx2x_get_q_flags(sc, leading);
6543 /* set general SETUP parameters */
6544 bnx2x_pf_q_prep_general(sc, fp, &setup_params->gen_params,
6545 FIRST_TX_COS_INDEX);
6547 bnx2x_pf_rx_q_prep(sc, fp,
6548 &setup_params->pause_params,
6549 &setup_params->rxq_params);
6551 bnx2x_pf_tx_q_prep(sc, fp, &setup_params->txq_params, FIRST_TX_COS_INDEX);
6553 /* Set the command */
6554 q_params.cmd = ECORE_Q_CMD_SETUP;
6556 /* change the state to SETUP */
6557 rc = ecore_queue_state_change(sc, &q_params);
6559 PMD_DRV_LOG(NOTICE, "Queue(%d) SETUP failed", fp->index);
6566 static int bnx2x_setup_leading(struct bnx2x_softc *sc)
6569 return bnx2x_setup_queue(sc, &sc->fp[0], TRUE);
6571 return bnx2x_vf_setup_queue(sc, &sc->fp[0], TRUE);
6575 bnx2x_config_rss_pf(struct bnx2x_softc *sc, struct ecore_rss_config_obj *rss_obj,
6576 uint8_t config_hash)
6578 struct ecore_config_rss_params params = { NULL };
6582 * Although RSS is meaningless when there is a single HW queue we
6583 * still need it enabled in order to have HW Rx hash generated.
6586 params.rss_obj = rss_obj;
6588 bnx2x_set_bit(RAMROD_COMP_WAIT, ¶ms.ramrod_flags);
6590 bnx2x_set_bit(ECORE_RSS_MODE_REGULAR, ¶ms.rss_flags);
6592 /* RSS configuration */
6593 bnx2x_set_bit(ECORE_RSS_IPV4, ¶ms.rss_flags);
6594 bnx2x_set_bit(ECORE_RSS_IPV4_TCP, ¶ms.rss_flags);
6595 bnx2x_set_bit(ECORE_RSS_IPV6, ¶ms.rss_flags);
6596 bnx2x_set_bit(ECORE_RSS_IPV6_TCP, ¶ms.rss_flags);
6597 if (rss_obj->udp_rss_v4) {
6598 bnx2x_set_bit(ECORE_RSS_IPV4_UDP, ¶ms.rss_flags);
6600 if (rss_obj->udp_rss_v6) {
6601 bnx2x_set_bit(ECORE_RSS_IPV6_UDP, ¶ms.rss_flags);
6605 params.rss_result_mask = MULTI_MASK;
6607 rte_memcpy(params.ind_table, rss_obj->ind_table,
6608 sizeof(params.ind_table));
6612 for (i = 0; i < sizeof(params.rss_key) / 4; i++) {
6613 params.rss_key[i] = (uint32_t) rte_rand();
6616 bnx2x_set_bit(ECORE_RSS_SET_SRCH, ¶ms.rss_flags);
6620 return ecore_config_rss(sc, ¶ms);
6622 return bnx2x_vf_config_rss(sc, ¶ms);
6625 static int bnx2x_config_rss_eth(struct bnx2x_softc *sc, uint8_t config_hash)
6627 return bnx2x_config_rss_pf(sc, &sc->rss_conf_obj, config_hash);
6630 static int bnx2x_init_rss_pf(struct bnx2x_softc *sc)
6632 uint8_t num_eth_queues = BNX2X_NUM_ETH_QUEUES(sc);
6636 * Prepare the initial contents of the indirection table if
6639 for (i = 0; i < sizeof(sc->rss_conf_obj.ind_table); i++) {
6640 sc->rss_conf_obj.ind_table[i] =
6641 (sc->fp->cl_id + (i % num_eth_queues));
6645 sc->rss_conf_obj.udp_rss_v4 = sc->rss_conf_obj.udp_rss_v6 = 1;
6649 * For 57711 SEARCHER configuration (rss_keys) is
6650 * per-port, so if explicit configuration is needed, do it only
6653 * For 57712 and newer it's a per-function configuration.
6655 return bnx2x_config_rss_eth(sc, sc->port.pmf || !CHIP_IS_E1x(sc));
6659 bnx2x_set_mac_one(struct bnx2x_softc *sc, uint8_t * mac,
6660 struct ecore_vlan_mac_obj *obj, uint8_t set, int mac_type,
6661 unsigned long *ramrod_flags)
6663 struct ecore_vlan_mac_ramrod_params ramrod_param;
6666 memset(&ramrod_param, 0, sizeof(ramrod_param));
6668 /* fill in general parameters */
6669 ramrod_param.vlan_mac_obj = obj;
6670 ramrod_param.ramrod_flags = *ramrod_flags;
6672 /* fill a user request section if needed */
6673 if (!bnx2x_test_bit(RAMROD_CONT, ramrod_flags)) {
6674 rte_memcpy(ramrod_param.user_req.u.mac.mac, mac,
6677 bnx2x_set_bit(mac_type, &ramrod_param.user_req.vlan_mac_flags);
6679 /* Set the command: ADD or DEL */
6680 ramrod_param.user_req.cmd = (set) ? ECORE_VLAN_MAC_ADD :
6684 rc = ecore_config_vlan_mac(sc, &ramrod_param);
6686 if (rc == ECORE_EXISTS) {
6687 PMD_DRV_LOG(INFO, "Failed to schedule ADD operations (EEXIST)");
6688 /* do not treat adding same MAC as error */
6690 } else if (rc < 0) {
6692 "%s MAC failed (%d)", (set ? "Set" : "Delete"), rc);
6698 static int bnx2x_set_eth_mac(struct bnx2x_softc *sc, uint8_t set)
6700 unsigned long ramrod_flags = 0;
6702 PMD_DRV_LOG(DEBUG, "Adding Ethernet MAC");
6704 bnx2x_set_bit(RAMROD_COMP_WAIT, &ramrod_flags);
6706 /* Eth MAC is set on RSS leading client (fp[0]) */
6707 return bnx2x_set_mac_one(sc, sc->link_params.mac_addr,
6708 &sc->sp_objs->mac_obj,
6709 set, ECORE_ETH_MAC, &ramrod_flags);
6712 static int bnx2x_get_cur_phy_idx(struct bnx2x_softc *sc)
6714 uint32_t sel_phy_idx = 0;
6716 if (sc->link_params.num_phys <= 1) {
6717 return ELINK_INT_PHY;
6720 if (sc->link_vars.link_up) {
6721 sel_phy_idx = ELINK_EXT_PHY1;
6722 /* In case link is SERDES, check if the ELINK_EXT_PHY2 is the one */
6723 if ((sc->link_vars.link_status & LINK_STATUS_SERDES_LINK) &&
6724 (sc->link_params.phy[ELINK_EXT_PHY2].supported &
6725 ELINK_SUPPORTED_FIBRE))
6726 sel_phy_idx = ELINK_EXT_PHY2;
6728 switch (elink_phy_selection(&sc->link_params)) {
6729 case PORT_HW_CFG_PHY_SELECTION_HARDWARE_DEFAULT:
6730 case PORT_HW_CFG_PHY_SELECTION_FIRST_PHY:
6731 case PORT_HW_CFG_PHY_SELECTION_FIRST_PHY_PRIORITY:
6732 sel_phy_idx = ELINK_EXT_PHY1;
6734 case PORT_HW_CFG_PHY_SELECTION_SECOND_PHY:
6735 case PORT_HW_CFG_PHY_SELECTION_SECOND_PHY_PRIORITY:
6736 sel_phy_idx = ELINK_EXT_PHY2;
6744 static int bnx2x_get_link_cfg_idx(struct bnx2x_softc *sc)
6746 uint32_t sel_phy_idx = bnx2x_get_cur_phy_idx(sc);
6749 * The selected activated PHY is always after swapping (in case PHY
6750 * swapping is enabled). So when swapping is enabled, we need to reverse
6754 if (sc->link_params.multi_phy_config & PORT_HW_CFG_PHY_SWAPPED_ENABLED) {
6755 if (sel_phy_idx == ELINK_EXT_PHY1)
6756 sel_phy_idx = ELINK_EXT_PHY2;
6757 else if (sel_phy_idx == ELINK_EXT_PHY2)
6758 sel_phy_idx = ELINK_EXT_PHY1;
6761 return ELINK_LINK_CONFIG_IDX(sel_phy_idx);
6764 static void bnx2x_set_requested_fc(struct bnx2x_softc *sc)
6767 * Initialize link parameters structure variables
6768 * It is recommended to turn off RX FC for jumbo frames
6769 * for better performance
6771 if (CHIP_IS_E1x(sc) && (sc->mtu > 5000)) {
6772 sc->link_params.req_fc_auto_adv = ELINK_FLOW_CTRL_TX;
6774 sc->link_params.req_fc_auto_adv = ELINK_FLOW_CTRL_BOTH;
6778 static void bnx2x_calc_fc_adv(struct bnx2x_softc *sc)
6780 uint8_t cfg_idx = bnx2x_get_link_cfg_idx(sc);
6781 switch (sc->link_vars.ieee_fc &
6782 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_MASK) {
6783 case MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_NONE:
6785 sc->port.advertising[cfg_idx] &= ~(ADVERTISED_Asym_Pause |
6789 case MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH:
6790 sc->port.advertising[cfg_idx] |= (ADVERTISED_Asym_Pause |
6794 case MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC:
6795 sc->port.advertising[cfg_idx] |= ADVERTISED_Asym_Pause;
6800 static uint16_t bnx2x_get_mf_speed(struct bnx2x_softc *sc)
6802 uint16_t line_speed = sc->link_vars.line_speed;
6804 uint16_t maxCfg = bnx2x_extract_max_cfg(sc,
6806 mf_info.mf_config[SC_VN
6809 /* calculate the current MAX line speed limit for the MF devices */
6811 line_speed = (line_speed * maxCfg) / 100;
6812 } else { /* SD mode */
6813 uint16_t vn_max_rate = maxCfg * 100;
6815 if (vn_max_rate < line_speed) {
6816 line_speed = vn_max_rate;
6825 bnx2x_fill_report_data(struct bnx2x_softc *sc, struct bnx2x_link_report_data *data)
6827 uint16_t line_speed = bnx2x_get_mf_speed(sc);
6829 memset(data, 0, sizeof(*data));
6831 /* fill the report data with the effective line speed */
6832 data->line_speed = line_speed;
6835 if (!sc->link_vars.link_up || (sc->flags & BNX2X_MF_FUNC_DIS)) {
6836 bnx2x_set_bit(BNX2X_LINK_REPORT_LINK_DOWN,
6837 &data->link_report_flags);
6841 if (sc->link_vars.duplex == DUPLEX_FULL) {
6842 bnx2x_set_bit(BNX2X_LINK_REPORT_FULL_DUPLEX,
6843 &data->link_report_flags);
6846 /* Rx Flow Control is ON */
6847 if (sc->link_vars.flow_ctrl & ELINK_FLOW_CTRL_RX) {
6848 bnx2x_set_bit(BNX2X_LINK_REPORT_RX_FC_ON, &data->link_report_flags);
6851 /* Tx Flow Control is ON */
6852 if (sc->link_vars.flow_ctrl & ELINK_FLOW_CTRL_TX) {
6853 bnx2x_set_bit(BNX2X_LINK_REPORT_TX_FC_ON, &data->link_report_flags);
6857 /* report link status to OS, should be called under phy_lock */
6858 static void bnx2x_link_report(struct bnx2x_softc *sc)
6860 struct bnx2x_link_report_data cur_data;
6864 bnx2x_read_mf_cfg(sc);
6867 /* Read the current link report info */
6868 bnx2x_fill_report_data(sc, &cur_data);
6870 /* Don't report link down or exactly the same link status twice */
6871 if (!memcmp(&cur_data, &sc->last_reported_link, sizeof(cur_data)) ||
6872 (bnx2x_test_bit(BNX2X_LINK_REPORT_LINK_DOWN,
6873 &sc->last_reported_link.link_report_flags) &&
6874 bnx2x_test_bit(BNX2X_LINK_REPORT_LINK_DOWN,
6875 &cur_data.link_report_flags))) {
6881 /* report new link params and remember the state for the next time */
6882 rte_memcpy(&sc->last_reported_link, &cur_data, sizeof(cur_data));
6884 if (bnx2x_test_bit(BNX2X_LINK_REPORT_LINK_DOWN,
6885 &cur_data.link_report_flags)) {
6886 PMD_DRV_LOG(INFO, "NIC Link is Down");
6888 __rte_unused const char *duplex;
6889 __rte_unused const char *flow;
6891 if (bnx2x_test_and_clear_bit(BNX2X_LINK_REPORT_FULL_DUPLEX,
6892 &cur_data.link_report_flags)) {
6899 * Handle the FC at the end so that only these flags would be
6900 * possibly set. This way we may easily check if there is no FC
6903 if (cur_data.link_report_flags) {
6904 if (bnx2x_test_bit(BNX2X_LINK_REPORT_RX_FC_ON,
6905 &cur_data.link_report_flags) &&
6906 bnx2x_test_bit(BNX2X_LINK_REPORT_TX_FC_ON,
6907 &cur_data.link_report_flags)) {
6908 flow = "ON - receive & transmit";
6909 } else if (bnx2x_test_bit(BNX2X_LINK_REPORT_RX_FC_ON,
6910 &cur_data.link_report_flags) &&
6911 !bnx2x_test_bit(BNX2X_LINK_REPORT_TX_FC_ON,
6912 &cur_data.link_report_flags)) {
6913 flow = "ON - receive";
6914 } else if (!bnx2x_test_bit(BNX2X_LINK_REPORT_RX_FC_ON,
6915 &cur_data.link_report_flags) &&
6916 bnx2x_test_bit(BNX2X_LINK_REPORT_TX_FC_ON,
6917 &cur_data.link_report_flags)) {
6918 flow = "ON - transmit";
6920 flow = "none"; /* possible? */
6927 "NIC Link is Up, %d Mbps %s duplex, Flow control: %s",
6928 cur_data.line_speed, duplex, flow);
6932 void bnx2x_link_status_update(struct bnx2x_softc *sc)
6934 if (sc->state != BNX2X_STATE_OPEN) {
6938 if (IS_PF(sc) && !CHIP_REV_IS_SLOW(sc)) {
6939 elink_link_status_update(&sc->link_params, &sc->link_vars);
6941 sc->port.supported[0] |= (ELINK_SUPPORTED_10baseT_Half |
6942 ELINK_SUPPORTED_10baseT_Full |
6943 ELINK_SUPPORTED_100baseT_Half |
6944 ELINK_SUPPORTED_100baseT_Full |
6945 ELINK_SUPPORTED_1000baseT_Full |
6946 ELINK_SUPPORTED_2500baseX_Full |
6947 ELINK_SUPPORTED_10000baseT_Full |
6948 ELINK_SUPPORTED_TP |
6949 ELINK_SUPPORTED_FIBRE |
6950 ELINK_SUPPORTED_Autoneg |
6951 ELINK_SUPPORTED_Pause |
6952 ELINK_SUPPORTED_Asym_Pause);
6953 sc->port.advertising[0] = sc->port.supported[0];
6955 sc->link_params.sc = sc;
6956 sc->link_params.port = SC_PORT(sc);
6957 sc->link_params.req_duplex[0] = DUPLEX_FULL;
6958 sc->link_params.req_flow_ctrl[0] = ELINK_FLOW_CTRL_NONE;
6959 sc->link_params.req_line_speed[0] = SPEED_10000;
6960 sc->link_params.speed_cap_mask[0] = 0x7f0000;
6961 sc->link_params.switch_cfg = ELINK_SWITCH_CFG_10G;
6963 if (CHIP_REV_IS_FPGA(sc)) {
6964 sc->link_vars.mac_type = ELINK_MAC_TYPE_EMAC;
6965 sc->link_vars.line_speed = ELINK_SPEED_1000;
6966 sc->link_vars.link_status = (LINK_STATUS_LINK_UP |
6967 LINK_STATUS_SPEED_AND_DUPLEX_1000TFD);
6969 sc->link_vars.mac_type = ELINK_MAC_TYPE_BMAC;
6970 sc->link_vars.line_speed = ELINK_SPEED_10000;
6971 sc->link_vars.link_status = (LINK_STATUS_LINK_UP |
6972 LINK_STATUS_SPEED_AND_DUPLEX_10GTFD);
6975 sc->link_vars.link_up = 1;
6977 sc->link_vars.duplex = DUPLEX_FULL;
6978 sc->link_vars.flow_ctrl = ELINK_FLOW_CTRL_NONE;
6982 NIG_REG_EGRESS_DRAIN0_MODE +
6983 sc->link_params.port * 4, 0);
6984 bnx2x_stats_handle(sc, STATS_EVENT_LINK_UP);
6985 bnx2x_link_report(sc);
6990 if (sc->link_vars.link_up) {
6991 bnx2x_stats_handle(sc, STATS_EVENT_LINK_UP);
6993 bnx2x_stats_handle(sc, STATS_EVENT_STOP);
6995 bnx2x_link_report(sc);
6997 bnx2x_link_report(sc);
6998 bnx2x_stats_handle(sc, STATS_EVENT_LINK_UP);
7002 static void bnx2x_periodic_start(struct bnx2x_softc *sc)
7004 atomic_store_rel_long(&sc->periodic_flags, PERIODIC_GO);
7007 static void bnx2x_periodic_stop(struct bnx2x_softc *sc)
7009 atomic_store_rel_long(&sc->periodic_flags, PERIODIC_STOP);
7012 static int bnx2x_initial_phy_init(struct bnx2x_softc *sc, int load_mode)
7014 int rc, cfg_idx = bnx2x_get_link_cfg_idx(sc);
7015 uint16_t req_line_speed = sc->link_params.req_line_speed[cfg_idx];
7016 struct elink_params *lp = &sc->link_params;
7018 bnx2x_set_requested_fc(sc);
7020 if (load_mode == LOAD_DIAG) {
7021 lp->loopback_mode = ELINK_LOOPBACK_XGXS;
7022 /* Prefer doing PHY loopback at 10G speed, if possible */
7023 if (lp->req_line_speed[cfg_idx] < ELINK_SPEED_10000) {
7024 if (lp->speed_cap_mask[cfg_idx] &
7025 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G) {
7026 lp->req_line_speed[cfg_idx] = ELINK_SPEED_10000;
7028 lp->req_line_speed[cfg_idx] = ELINK_SPEED_1000;
7033 if (load_mode == LOAD_LOOPBACK_EXT) {
7034 lp->loopback_mode = ELINK_LOOPBACK_EXT;
7037 rc = elink_phy_init(&sc->link_params, &sc->link_vars);
7039 bnx2x_calc_fc_adv(sc);
7041 if (sc->link_vars.link_up) {
7042 bnx2x_stats_handle(sc, STATS_EVENT_LINK_UP);
7043 bnx2x_link_report(sc);
7046 if (!CHIP_REV_IS_SLOW(sc)) {
7047 bnx2x_periodic_start(sc);
7050 sc->link_params.req_line_speed[cfg_idx] = req_line_speed;
7054 /* update flags in shmem */
7056 bnx2x_update_drv_flags(struct bnx2x_softc *sc, uint32_t flags, uint32_t set)
7060 if (SHMEM2_HAS(sc, drv_flags)) {
7061 bnx2x_acquire_hw_lock(sc, HW_LOCK_RESOURCE_DRV_FLAGS);
7062 drv_flags = SHMEM2_RD(sc, drv_flags);
7067 drv_flags &= ~flags;
7070 SHMEM2_WR(sc, drv_flags, drv_flags);
7072 bnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_DRV_FLAGS);
7076 /* periodic timer callout routine, only runs when the interface is up */
7077 void bnx2x_periodic_callout(struct bnx2x_softc *sc)
7079 if ((sc->state != BNX2X_STATE_OPEN) ||
7080 (atomic_load_acq_long(&sc->periodic_flags) == PERIODIC_STOP)) {
7081 PMD_DRV_LOG(WARNING, "periodic callout exit (state=0x%x)",
7085 if (!CHIP_REV_IS_SLOW(sc)) {
7087 * This barrier is needed to ensure the ordering between the writing
7088 * to the sc->port.pmf in the bnx2x_nic_load() or bnx2x_pmf_update() and
7093 elink_period_func(&sc->link_params, &sc->link_vars);
7097 if (IS_PF(sc) && !BNX2X_NOMCP(sc)) {
7098 int mb_idx = SC_FW_MB_IDX(sc);
7102 ++sc->fw_drv_pulse_wr_seq;
7103 sc->fw_drv_pulse_wr_seq &= DRV_PULSE_SEQ_MASK;
7105 drv_pulse = sc->fw_drv_pulse_wr_seq;
7106 bnx2x_drv_pulse(sc);
7108 mcp_pulse = (SHMEM_RD(sc, func_mb[mb_idx].mcp_pulse_mb) &
7109 MCP_PULSE_SEQ_MASK);
7112 * The delta between driver pulse and mcp response should
7113 * be 1 (before mcp response) or 0 (after mcp response).
7115 if ((drv_pulse != mcp_pulse) &&
7116 (drv_pulse != ((mcp_pulse + 1) & MCP_PULSE_SEQ_MASK))) {
7117 /* someone lost a heartbeat... */
7119 "drv_pulse (0x%x) != mcp_pulse (0x%x)",
7120 drv_pulse, mcp_pulse);
7126 /* start the controller */
7127 static __rte_noinline
7128 int bnx2x_nic_load(struct bnx2x_softc *sc)
7131 uint32_t load_code = 0;
7134 PMD_INIT_FUNC_TRACE();
7136 sc->state = BNX2X_STATE_OPENING_WAITING_LOAD;
7139 /* must be called before memory allocation and HW init */
7140 bnx2x_ilt_set_info(sc);
7143 bnx2x_set_fp_rx_buf_size(sc);
7146 if (bnx2x_alloc_mem(sc) != 0) {
7147 sc->state = BNX2X_STATE_CLOSED;
7149 goto bnx2x_nic_load_error0;
7153 if (bnx2x_alloc_fw_stats_mem(sc) != 0) {
7154 sc->state = BNX2X_STATE_CLOSED;
7156 goto bnx2x_nic_load_error0;
7160 rc = bnx2x_vf_init(sc);
7162 sc->state = BNX2X_STATE_ERROR;
7163 goto bnx2x_nic_load_error0;
7168 /* set pf load just before approaching the MCP */
7169 bnx2x_set_pf_load(sc);
7171 /* if MCP exists send load request and analyze response */
7172 if (!BNX2X_NOMCP(sc)) {
7173 /* attempt to load pf */
7174 if (bnx2x_nic_load_request(sc, &load_code) != 0) {
7175 sc->state = BNX2X_STATE_CLOSED;
7177 goto bnx2x_nic_load_error1;
7180 /* what did the MCP say? */
7181 if (bnx2x_nic_load_analyze_req(sc, load_code) != 0) {
7182 bnx2x_fw_command(sc, DRV_MSG_CODE_LOAD_DONE, 0);
7183 sc->state = BNX2X_STATE_CLOSED;
7185 goto bnx2x_nic_load_error2;
7188 PMD_DRV_LOG(INFO, "Device has no MCP!");
7189 load_code = bnx2x_nic_load_no_mcp(sc);
7192 /* mark PMF if applicable */
7193 bnx2x_nic_load_pmf(sc, load_code);
7195 /* Init Function state controlling object */
7196 bnx2x_init_func_obj(sc);
7199 if (bnx2x_init_hw(sc, load_code) != 0) {
7200 PMD_DRV_LOG(NOTICE, "HW init failed");
7201 bnx2x_fw_command(sc, DRV_MSG_CODE_LOAD_DONE, 0);
7202 sc->state = BNX2X_STATE_CLOSED;
7204 goto bnx2x_nic_load_error2;
7208 bnx2x_nic_init(sc, load_code);
7210 /* Init per-function objects */
7212 bnx2x_init_objs(sc);
7214 /* set AFEX default VLAN tag to an invalid value */
7215 sc->devinfo.mf_info.afex_def_vlan_tag = -1;
7217 sc->state = BNX2X_STATE_OPENING_WAITING_PORT;
7218 rc = bnx2x_func_start(sc);
7220 PMD_DRV_LOG(NOTICE, "Function start failed!");
7221 bnx2x_fw_command(sc, DRV_MSG_CODE_LOAD_DONE, 0);
7222 sc->state = BNX2X_STATE_ERROR;
7223 goto bnx2x_nic_load_error3;
7226 /* send LOAD_DONE command to MCP */
7227 if (!BNX2X_NOMCP(sc)) {
7229 bnx2x_fw_command(sc, DRV_MSG_CODE_LOAD_DONE, 0);
7232 "MCP response failure, aborting");
7233 sc->state = BNX2X_STATE_ERROR;
7235 goto bnx2x_nic_load_error3;
7240 rc = bnx2x_setup_leading(sc);
7242 PMD_DRV_LOG(NOTICE, "Setup leading failed!");
7243 sc->state = BNX2X_STATE_ERROR;
7244 goto bnx2x_nic_load_error3;
7247 FOR_EACH_NONDEFAULT_ETH_QUEUE(sc, i) {
7249 rc = bnx2x_setup_queue(sc, &sc->fp[i], FALSE);
7250 else /* IS_VF(sc) */
7251 rc = bnx2x_vf_setup_queue(sc, &sc->fp[i], FALSE);
7254 PMD_DRV_LOG(NOTICE, "Queue(%d) setup failed", i);
7255 sc->state = BNX2X_STATE_ERROR;
7256 goto bnx2x_nic_load_error3;
7260 rc = bnx2x_init_rss_pf(sc);
7262 PMD_DRV_LOG(NOTICE, "PF RSS init failed");
7263 sc->state = BNX2X_STATE_ERROR;
7264 goto bnx2x_nic_load_error3;
7267 /* now when Clients are configured we are ready to work */
7268 sc->state = BNX2X_STATE_OPEN;
7270 /* Configure a ucast MAC */
7272 rc = bnx2x_set_eth_mac(sc, TRUE);
7273 } else { /* IS_VF(sc) */
7274 rc = bnx2x_vf_set_mac(sc, TRUE);
7278 PMD_DRV_LOG(NOTICE, "Setting Ethernet MAC failed");
7279 sc->state = BNX2X_STATE_ERROR;
7280 goto bnx2x_nic_load_error3;
7284 rc = bnx2x_initial_phy_init(sc, LOAD_OPEN);
7286 sc->state = BNX2X_STATE_ERROR;
7287 goto bnx2x_nic_load_error3;
7291 sc->link_params.feature_config_flags &=
7292 ~ELINK_FEATURE_CONFIG_BOOT_FROM_SAN;
7295 switch (LOAD_OPEN) {
7301 case LOAD_LOOPBACK_EXT:
7302 sc->state = BNX2X_STATE_DIAG;
7310 bnx2x_update_drv_flags(sc, 1 << DRV_FLAGS_PORT_MASK, 0);
7312 bnx2x_link_status_update(sc);
7315 if (IS_PF(sc) && SHMEM2_HAS(sc, drv_capabilities_flag)) {
7316 /* mark driver is loaded in shmem2 */
7317 val = SHMEM2_RD(sc, drv_capabilities_flag[SC_FW_MB_IDX(sc)]);
7318 SHMEM2_WR(sc, drv_capabilities_flag[SC_FW_MB_IDX(sc)],
7320 DRV_FLAGS_CAPABILITIES_LOADED_SUPPORTED |
7321 DRV_FLAGS_CAPABILITIES_LOADED_L2));
7324 /* start fast path */
7325 /* Initialize Rx filter */
7326 bnx2x_set_rx_mode(sc);
7328 /* wait for all pending SP commands to complete */
7329 if (IS_PF(sc) && !bnx2x_wait_sp_comp(sc, ~0x0UL)) {
7330 PMD_DRV_LOG(NOTICE, "Timeout waiting for all SPs to complete!");
7331 bnx2x_periodic_stop(sc);
7332 bnx2x_nic_unload(sc, UNLOAD_CLOSE, FALSE);
7336 PMD_DRV_LOG(DEBUG, "NIC successfully loaded");
7340 bnx2x_nic_load_error3:
7343 bnx2x_int_disable_sync(sc, 1);
7345 /* clean out queued objects */
7346 bnx2x_squeeze_objects(sc);
7349 bnx2x_nic_load_error2:
7351 if (IS_PF(sc) && !BNX2X_NOMCP(sc)) {
7352 bnx2x_fw_command(sc, DRV_MSG_CODE_UNLOAD_REQ_WOL_MCP, 0);
7353 bnx2x_fw_command(sc, DRV_MSG_CODE_UNLOAD_DONE, 0);
7358 bnx2x_nic_load_error1:
7360 /* clear pf_load status, as it was already set */
7362 bnx2x_clear_pf_load(sc);
7365 bnx2x_nic_load_error0:
7367 bnx2x_free_fw_stats_mem(sc);
7374 * Handles controller initialization.
7376 int bnx2x_init(struct bnx2x_softc *sc)
7378 int other_engine = SC_PATH(sc) ? 0 : 1;
7379 uint8_t other_load_status, load_status;
7380 uint8_t global = FALSE;
7383 /* Check if the driver is still running and bail out if it is. */
7384 if (sc->state != BNX2X_STATE_CLOSED) {
7385 PMD_DRV_LOG(DEBUG, "Init called while driver is running!");
7387 goto bnx2x_init_done;
7390 bnx2x_set_power_state(sc, PCI_PM_D0);
7393 * If parity occurred during the unload, then attentions and/or
7394 * RECOVERY_IN_PROGRESS may still be set. If so we want the first function
7395 * loaded on the current engine to complete the recovery. Parity recovery
7396 * is only relevant for PF driver.
7399 other_load_status = bnx2x_get_load_status(sc, other_engine);
7400 load_status = bnx2x_get_load_status(sc, SC_PATH(sc));
7402 if (!bnx2x_reset_is_done(sc, SC_PATH(sc)) ||
7403 bnx2x_chk_parity_attn(sc, &global, TRUE)) {
7406 * If there are attentions and they are in global blocks, set
7407 * the GLOBAL_RESET bit regardless whether it will be this
7408 * function that will complete the recovery or not.
7411 bnx2x_set_reset_global(sc);
7415 * Only the first function on the current engine should try
7416 * to recover in open. In case of attentions in global blocks
7417 * only the first in the chip should try to recover.
7420 && (!global ||!other_load_status))
7421 && bnx2x_trylock_leader_lock(sc)
7422 && !bnx2x_leader_reset(sc)) {
7424 "Recovered during init");
7428 /* recovery has failed... */
7429 bnx2x_set_power_state(sc, PCI_PM_D3hot);
7431 sc->recovery_state = BNX2X_RECOVERY_FAILED;
7434 "Recovery flow hasn't properly "
7435 "completed yet, try again later. "
7436 "If you still see this message after a "
7437 "few retries then power cycle is required.");
7440 goto bnx2x_init_done;
7445 sc->recovery_state = BNX2X_RECOVERY_DONE;
7447 rc = bnx2x_nic_load(sc);
7452 PMD_DRV_LOG(NOTICE, "Initialization failed, "
7453 "stack notified driver is NOT running!");
7459 static void bnx2x_get_function_num(struct bnx2x_softc *sc)
7464 * Read the ME register to get the function number. The ME register
7465 * holds the relative-function number and absolute-function number. The
7466 * absolute-function number appears only in E2 and above. Before that
7467 * these bits always contained zero, therefore we cannot blindly use them.
7470 val = REG_RD(sc, BAR_ME_REGISTER);
7473 (uint8_t) ((val & ME_REG_PF_NUM) >> ME_REG_PF_NUM_SHIFT);
7475 (uint8_t) ((val & ME_REG_ABS_PF_NUM) >> ME_REG_ABS_PF_NUM_SHIFT) &
7478 if (CHIP_PORT_MODE(sc) == CHIP_4_PORT_MODE) {
7479 sc->pfunc_abs = ((sc->pfunc_rel << 1) | sc->path_id);
7481 sc->pfunc_abs = (sc->pfunc_rel | sc->path_id);
7485 "Relative function %d, Absolute function %d, Path %d",
7486 sc->pfunc_rel, sc->pfunc_abs, sc->path_id);
7489 static uint32_t bnx2x_get_shmem_mf_cfg_base(struct bnx2x_softc *sc)
7491 uint32_t shmem2_size;
7493 uint32_t mf_cfg_offset_value;
7496 offset = (SHMEM_ADDR(sc, func_mb) +
7497 (MAX_FUNC_NUM * sizeof(struct drv_func_mb)));
7500 if (sc->devinfo.shmem2_base != 0) {
7501 shmem2_size = SHMEM2_RD(sc, size);
7502 if (shmem2_size > offsetof(struct shmem2_region, mf_cfg_addr)) {
7503 mf_cfg_offset_value = SHMEM2_RD(sc, mf_cfg_addr);
7504 if (SHMEM_MF_CFG_ADDR_NONE != mf_cfg_offset_value) {
7505 offset = mf_cfg_offset_value;
7513 static uint32_t bnx2x_pcie_capability_read(struct bnx2x_softc *sc, int reg)
7516 struct bnx2x_pci_cap *caps;
7518 /* ensure PCIe capability is enabled */
7519 caps = pci_find_cap(sc, PCIY_EXPRESS, BNX2X_PCI_CAP);
7521 PMD_DRV_LOG(DEBUG, "Found PCIe capability: "
7522 "id=0x%04X type=0x%04X addr=0x%08X",
7523 caps->id, caps->type, caps->addr);
7524 pci_read(sc, (caps->addr + reg), &ret, 2);
7528 PMD_DRV_LOG(WARNING, "PCIe capability NOT FOUND!!!");
7533 static uint8_t bnx2x_is_pcie_pending(struct bnx2x_softc *sc)
7535 return bnx2x_pcie_capability_read(sc, PCIR_EXPRESS_DEVICE_STA) &
7536 PCIM_EXP_STA_TRANSACTION_PND;
7540 * Walk the PCI capabiites list for the device to find what features are
7541 * supported. These capabilites may be enabled/disabled by firmware so it's
7542 * best to walk the list rather than make assumptions.
7544 static void bnx2x_probe_pci_caps(struct bnx2x_softc *sc)
7546 PMD_INIT_FUNC_TRACE();
7548 struct bnx2x_pci_cap *caps;
7549 uint16_t link_status;
7550 #ifdef RTE_LIBRTE_BNX2X_DEBUG
7554 /* check if PCI Power Management is enabled */
7555 caps = pci_find_cap(sc, PCIY_PMG, BNX2X_PCI_CAP);
7557 PMD_DRV_LOG(DEBUG, "Found PM capability: "
7558 "id=0x%04X type=0x%04X addr=0x%08X",
7559 caps->id, caps->type, caps->addr);
7561 sc->devinfo.pcie_cap_flags |= BNX2X_PM_CAPABLE_FLAG;
7562 sc->devinfo.pcie_pm_cap_reg = caps->addr;
7565 link_status = bnx2x_pcie_capability_read(sc, PCIR_EXPRESS_LINK_STA);
7567 sc->devinfo.pcie_link_speed = (link_status & PCIM_LINK_STA_SPEED);
7568 sc->devinfo.pcie_link_width =
7569 ((link_status & PCIM_LINK_STA_WIDTH) >> 4);
7571 PMD_DRV_LOG(DEBUG, "PCIe link speed=%d width=%d",
7572 sc->devinfo.pcie_link_speed, sc->devinfo.pcie_link_width);
7574 sc->devinfo.pcie_cap_flags |= BNX2X_PCIE_CAPABLE_FLAG;
7576 /* check if MSI capability is enabled */
7577 caps = pci_find_cap(sc, PCIY_MSI, BNX2X_PCI_CAP);
7579 PMD_DRV_LOG(DEBUG, "Found MSI capability at 0x%04x", reg);
7581 sc->devinfo.pcie_cap_flags |= BNX2X_MSI_CAPABLE_FLAG;
7582 sc->devinfo.pcie_msi_cap_reg = caps->addr;
7585 /* check if MSI-X capability is enabled */
7586 caps = pci_find_cap(sc, PCIY_MSIX, BNX2X_PCI_CAP);
7588 PMD_DRV_LOG(DEBUG, "Found MSI-X capability at 0x%04x", reg);
7590 sc->devinfo.pcie_cap_flags |= BNX2X_MSIX_CAPABLE_FLAG;
7591 sc->devinfo.pcie_msix_cap_reg = caps->addr;
7595 static int bnx2x_get_shmem_mf_cfg_info_sd(struct bnx2x_softc *sc)
7597 struct bnx2x_mf_info *mf_info = &sc->devinfo.mf_info;
7600 /* get the outer vlan if we're in switch-dependent mode */
7602 val = MFCFG_RD(sc, func_mf_config[SC_ABS_FUNC(sc)].e1hov_tag);
7603 mf_info->ext_id = (uint16_t) val;
7605 mf_info->multi_vnics_mode = 1;
7607 if (!VALID_OVLAN(mf_info->ext_id)) {
7608 PMD_DRV_LOG(NOTICE, "Invalid VLAN (%d)", mf_info->ext_id);
7612 /* get the capabilities */
7613 if ((mf_info->mf_config[SC_VN(sc)] & FUNC_MF_CFG_PROTOCOL_MASK) ==
7614 FUNC_MF_CFG_PROTOCOL_ISCSI) {
7615 mf_info->mf_protos_supported |= MF_PROTO_SUPPORT_ISCSI;
7616 } else if ((mf_info->mf_config[SC_VN(sc)] & FUNC_MF_CFG_PROTOCOL_MASK)
7617 == FUNC_MF_CFG_PROTOCOL_FCOE) {
7618 mf_info->mf_protos_supported |= MF_PROTO_SUPPORT_FCOE;
7620 mf_info->mf_protos_supported |= MF_PROTO_SUPPORT_ETHERNET;
7623 mf_info->vnics_per_port =
7624 (CHIP_PORT_MODE(sc) == CHIP_4_PORT_MODE) ? 2 : 4;
7629 static uint32_t bnx2x_get_shmem_ext_proto_support_flags(struct bnx2x_softc *sc)
7631 uint32_t retval = 0;
7634 val = MFCFG_RD(sc, func_ext_config[SC_ABS_FUNC(sc)].func_cfg);
7636 if (val & MACP_FUNC_CFG_FLAGS_ENABLED) {
7637 if (val & MACP_FUNC_CFG_FLAGS_ETHERNET) {
7638 retval |= MF_PROTO_SUPPORT_ETHERNET;
7640 if (val & MACP_FUNC_CFG_FLAGS_ISCSI_OFFLOAD) {
7641 retval |= MF_PROTO_SUPPORT_ISCSI;
7643 if (val & MACP_FUNC_CFG_FLAGS_FCOE_OFFLOAD) {
7644 retval |= MF_PROTO_SUPPORT_FCOE;
7651 static int bnx2x_get_shmem_mf_cfg_info_si(struct bnx2x_softc *sc)
7653 struct bnx2x_mf_info *mf_info = &sc->devinfo.mf_info;
7657 * There is no outer vlan if we're in switch-independent mode.
7658 * If the mac is valid then assume multi-function.
7661 val = MFCFG_RD(sc, func_ext_config[SC_ABS_FUNC(sc)].func_cfg);
7663 mf_info->multi_vnics_mode = ((val & MACP_FUNC_CFG_FLAGS_MASK) != 0);
7665 mf_info->mf_protos_supported =
7666 bnx2x_get_shmem_ext_proto_support_flags(sc);
7668 mf_info->vnics_per_port =
7669 (CHIP_PORT_MODE(sc) == CHIP_4_PORT_MODE) ? 2 : 4;
7674 static int bnx2x_get_shmem_mf_cfg_info_niv(struct bnx2x_softc *sc)
7676 struct bnx2x_mf_info *mf_info = &sc->devinfo.mf_info;
7678 uint32_t func_config;
7679 uint32_t niv_config;
7681 mf_info->multi_vnics_mode = 1;
7683 e1hov_tag = MFCFG_RD(sc, func_mf_config[SC_ABS_FUNC(sc)].e1hov_tag);
7684 func_config = MFCFG_RD(sc, func_mf_config[SC_ABS_FUNC(sc)].config);
7685 niv_config = MFCFG_RD(sc, func_mf_config[SC_ABS_FUNC(sc)].afex_config);
7688 (uint16_t) ((e1hov_tag & FUNC_MF_CFG_E1HOV_TAG_MASK) >>
7689 FUNC_MF_CFG_E1HOV_TAG_SHIFT);
7691 mf_info->default_vlan =
7692 (uint16_t) ((e1hov_tag & FUNC_MF_CFG_AFEX_VLAN_MASK) >>
7693 FUNC_MF_CFG_AFEX_VLAN_SHIFT);
7695 mf_info->niv_allowed_priorities =
7696 (uint8_t) ((niv_config & FUNC_MF_CFG_AFEX_COS_FILTER_MASK) >>
7697 FUNC_MF_CFG_AFEX_COS_FILTER_SHIFT);
7699 mf_info->niv_default_cos =
7700 (uint8_t) ((func_config & FUNC_MF_CFG_TRANSMIT_PRIORITY_MASK) >>
7701 FUNC_MF_CFG_TRANSMIT_PRIORITY_SHIFT);
7703 mf_info->afex_vlan_mode =
7704 ((niv_config & FUNC_MF_CFG_AFEX_VLAN_MODE_MASK) >>
7705 FUNC_MF_CFG_AFEX_VLAN_MODE_SHIFT);
7707 mf_info->niv_mba_enabled =
7708 ((niv_config & FUNC_MF_CFG_AFEX_MBA_ENABLED_MASK) >>
7709 FUNC_MF_CFG_AFEX_MBA_ENABLED_SHIFT);
7711 mf_info->mf_protos_supported =
7712 bnx2x_get_shmem_ext_proto_support_flags(sc);
7714 mf_info->vnics_per_port =
7715 (CHIP_PORT_MODE(sc) == CHIP_4_PORT_MODE) ? 2 : 4;
7720 static int bnx2x_check_valid_mf_cfg(struct bnx2x_softc *sc)
7722 struct bnx2x_mf_info *mf_info = &sc->devinfo.mf_info;
7729 /* various MF mode sanity checks... */
7731 if (mf_info->mf_config[SC_VN(sc)] & FUNC_MF_CFG_FUNC_HIDE) {
7733 "Enumerated function %d is marked as hidden",
7738 if ((mf_info->vnics_per_port > 1) && !mf_info->multi_vnics_mode) {
7739 PMD_DRV_LOG(NOTICE, "vnics_per_port=%d multi_vnics_mode=%d",
7740 mf_info->vnics_per_port, mf_info->multi_vnics_mode);
7744 if (mf_info->mf_mode == MULTI_FUNCTION_SD) {
7745 /* vnic id > 0 must have valid ovlan in switch-dependent mode */
7746 if ((SC_VN(sc) > 0) && !VALID_OVLAN(OVLAN(sc))) {
7747 PMD_DRV_LOG(NOTICE, "mf_mode=SD vnic_id=%d ovlan=%d",
7748 SC_VN(sc), OVLAN(sc));
7752 if (!VALID_OVLAN(OVLAN(sc)) && mf_info->multi_vnics_mode) {
7754 "mf_mode=SD multi_vnics_mode=%d ovlan=%d",
7755 mf_info->multi_vnics_mode, OVLAN(sc));
7760 * Verify all functions are either MF or SF mode. If MF, make sure
7761 * sure that all non-hidden functions have a valid ovlan. If SF,
7762 * make sure that all non-hidden functions have an invalid ovlan.
7764 FOREACH_ABS_FUNC_IN_PORT(sc, i) {
7765 mf_cfg1 = MFCFG_RD(sc, func_mf_config[i].config);
7766 ovlan1 = MFCFG_RD(sc, func_mf_config[i].e1hov_tag);
7767 if (!(mf_cfg1 & FUNC_MF_CFG_FUNC_HIDE) &&
7768 (((mf_info->multi_vnics_mode)
7769 && !VALID_OVLAN(ovlan1))
7770 || ((!mf_info->multi_vnics_mode)
7771 && VALID_OVLAN(ovlan1)))) {
7773 "mf_mode=SD function %d MF config "
7774 "mismatch, multi_vnics_mode=%d ovlan=%d",
7775 i, mf_info->multi_vnics_mode,
7781 /* Verify all funcs on the same port each have a different ovlan. */
7782 FOREACH_ABS_FUNC_IN_PORT(sc, i) {
7783 mf_cfg1 = MFCFG_RD(sc, func_mf_config[i].config);
7784 ovlan1 = MFCFG_RD(sc, func_mf_config[i].e1hov_tag);
7785 /* iterate from the next function on the port to the max func */
7786 for (j = i + 2; j < MAX_FUNC_NUM; j += 2) {
7788 MFCFG_RD(sc, func_mf_config[j].config);
7790 MFCFG_RD(sc, func_mf_config[j].e1hov_tag);
7791 if (!(mf_cfg1 & FUNC_MF_CFG_FUNC_HIDE)
7792 && VALID_OVLAN(ovlan1)
7793 && !(mf_cfg2 & FUNC_MF_CFG_FUNC_HIDE)
7794 && VALID_OVLAN(ovlan2)
7795 && (ovlan1 == ovlan2)) {
7797 "mf_mode=SD functions %d and %d "
7798 "have the same ovlan (%d)",
7805 /* MULTI_FUNCTION_SD */
7809 static int bnx2x_get_mf_cfg_info(struct bnx2x_softc *sc)
7811 struct bnx2x_mf_info *mf_info = &sc->devinfo.mf_info;
7812 uint32_t val, mac_upper;
7815 /* initialize mf_info defaults */
7816 mf_info->vnics_per_port = 1;
7817 mf_info->multi_vnics_mode = FALSE;
7818 mf_info->path_has_ovlan = FALSE;
7819 mf_info->mf_mode = SINGLE_FUNCTION;
7821 if (!CHIP_IS_MF_CAP(sc)) {
7825 if (sc->devinfo.mf_cfg_base == SHMEM_MF_CFG_ADDR_NONE) {
7826 PMD_DRV_LOG(NOTICE, "Invalid mf_cfg_base!");
7830 /* get the MF mode (switch dependent / independent / single-function) */
7832 val = SHMEM_RD(sc, dev_info.shared_feature_config.config);
7834 switch (val & SHARED_FEAT_CFG_FORCE_SF_MODE_MASK) {
7835 case SHARED_FEAT_CFG_FORCE_SF_MODE_SWITCH_INDEPT:
7838 MFCFG_RD(sc, func_mf_config[SC_ABS_FUNC(sc)].mac_upper);
7840 /* check for legal upper mac bytes */
7841 if (mac_upper != FUNC_MF_CFG_UPPERMAC_DEFAULT) {
7842 mf_info->mf_mode = MULTI_FUNCTION_SI;
7845 "Invalid config for Switch Independent mode");
7850 case SHARED_FEAT_CFG_FORCE_SF_MODE_MF_ALLOWED:
7851 case SHARED_FEAT_CFG_FORCE_SF_MODE_SPIO4:
7853 /* get outer vlan configuration */
7854 val = MFCFG_RD(sc, func_mf_config[SC_ABS_FUNC(sc)].e1hov_tag);
7856 if ((val & FUNC_MF_CFG_E1HOV_TAG_MASK) !=
7857 FUNC_MF_CFG_E1HOV_TAG_DEFAULT) {
7858 mf_info->mf_mode = MULTI_FUNCTION_SD;
7861 "Invalid config for Switch Dependent mode");
7866 case SHARED_FEAT_CFG_FORCE_SF_MODE_FORCED_SF:
7868 /* not in MF mode, vnics_per_port=1 and multi_vnics_mode=FALSE */
7871 case SHARED_FEAT_CFG_FORCE_SF_MODE_AFEX_MODE:
7874 * Mark MF mode as NIV if MCP version includes NPAR-SD support
7875 * and the MAC address is valid.
7878 MFCFG_RD(sc, func_mf_config[SC_ABS_FUNC(sc)].mac_upper);
7880 if ((SHMEM2_HAS(sc, afex_driver_support)) &&
7881 (mac_upper != FUNC_MF_CFG_UPPERMAC_DEFAULT)) {
7882 mf_info->mf_mode = MULTI_FUNCTION_AFEX;
7884 PMD_DRV_LOG(NOTICE, "Invalid config for AFEX mode");
7891 PMD_DRV_LOG(NOTICE, "Unknown MF mode (0x%08x)",
7892 (val & SHARED_FEAT_CFG_FORCE_SF_MODE_MASK));
7897 /* set path mf_mode (which could be different than function mf_mode) */
7898 if (mf_info->mf_mode == MULTI_FUNCTION_SD) {
7899 mf_info->path_has_ovlan = TRUE;
7900 } else if (mf_info->mf_mode == SINGLE_FUNCTION) {
7902 * Decide on path multi vnics mode. If we're not in MF mode and in
7903 * 4-port mode, this is good enough to check vnic-0 of the other port
7906 if (CHIP_PORT_MODE(sc) == CHIP_4_PORT_MODE) {
7907 uint8_t other_port = !(PORT_ID(sc) & 1);
7908 uint8_t abs_func_other_port =
7909 (SC_PATH(sc) + (2 * other_port));
7914 [abs_func_other_port].e1hov_tag);
7916 mf_info->path_has_ovlan = VALID_OVLAN((uint16_t) val);
7920 if (mf_info->mf_mode == SINGLE_FUNCTION) {
7921 /* invalid MF config */
7922 if (SC_VN(sc) >= 1) {
7923 PMD_DRV_LOG(NOTICE, "VNIC ID >= 1 in SF mode");
7930 /* get the MF configuration */
7931 mf_info->mf_config[SC_VN(sc)] =
7932 MFCFG_RD(sc, func_mf_config[SC_ABS_FUNC(sc)].config);
7934 switch (mf_info->mf_mode) {
7935 case MULTI_FUNCTION_SD:
7937 bnx2x_get_shmem_mf_cfg_info_sd(sc);
7940 case MULTI_FUNCTION_SI:
7942 bnx2x_get_shmem_mf_cfg_info_si(sc);
7945 case MULTI_FUNCTION_AFEX:
7947 bnx2x_get_shmem_mf_cfg_info_niv(sc);
7952 PMD_DRV_LOG(NOTICE, "Get MF config failed (mf_mode=0x%08x)",
7957 /* get the congestion management parameters */
7960 FOREACH_ABS_FUNC_IN_PORT(sc, i) {
7961 /* get min/max bw */
7962 val = MFCFG_RD(sc, func_mf_config[i].config);
7963 mf_info->min_bw[vnic] =
7964 ((val & FUNC_MF_CFG_MIN_BW_MASK) >>
7965 FUNC_MF_CFG_MIN_BW_SHIFT);
7966 mf_info->max_bw[vnic] =
7967 ((val & FUNC_MF_CFG_MAX_BW_MASK) >>
7968 FUNC_MF_CFG_MAX_BW_SHIFT);
7972 return bnx2x_check_valid_mf_cfg(sc);
7975 static int bnx2x_get_shmem_info(struct bnx2x_softc *sc)
7978 uint32_t mac_hi, mac_lo, val;
7980 PMD_INIT_FUNC_TRACE();
7983 mac_hi = mac_lo = 0;
7985 sc->link_params.sc = sc;
7986 sc->link_params.port = port;
7988 /* get the hardware config info */
7989 sc->devinfo.hw_config = SHMEM_RD(sc, dev_info.shared_hw_config.config);
7990 sc->devinfo.hw_config2 =
7991 SHMEM_RD(sc, dev_info.shared_hw_config.config2);
7993 sc->link_params.hw_led_mode =
7994 ((sc->devinfo.hw_config & SHARED_HW_CFG_LED_MODE_MASK) >>
7995 SHARED_HW_CFG_LED_MODE_SHIFT);
7997 /* get the port feature config */
7999 SHMEM_RD(sc, dev_info.port_feature_config[port].config);
8001 /* get the link params */
8002 sc->link_params.speed_cap_mask[ELINK_INT_PHY] =
8003 SHMEM_RD(sc, dev_info.port_hw_config[port].speed_capability_mask)
8004 & PORT_HW_CFG_SPEED_CAPABILITY_D0_MASK;
8005 sc->link_params.speed_cap_mask[ELINK_EXT_PHY1] =
8006 SHMEM_RD(sc, dev_info.port_hw_config[port].speed_capability_mask2)
8007 & PORT_HW_CFG_SPEED_CAPABILITY_D0_MASK;
8009 /* get the lane config */
8010 sc->link_params.lane_config =
8011 SHMEM_RD(sc, dev_info.port_hw_config[port].lane_config);
8013 /* get the link config */
8014 val = SHMEM_RD(sc, dev_info.port_feature_config[port].link_config);
8015 sc->port.link_config[ELINK_INT_PHY] = val;
8016 sc->link_params.switch_cfg = (val & PORT_FEATURE_CONNECTED_SWITCH_MASK);
8017 sc->port.link_config[ELINK_EXT_PHY1] =
8018 SHMEM_RD(sc, dev_info.port_feature_config[port].link_config2);
8020 /* get the override preemphasis flag and enable it or turn it off */
8021 val = SHMEM_RD(sc, dev_info.shared_feature_config.config);
8022 if (val & SHARED_FEAT_CFG_OVERRIDE_PREEMPHASIS_CFG_ENABLED) {
8023 sc->link_params.feature_config_flags |=
8024 ELINK_FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED;
8026 sc->link_params.feature_config_flags &=
8027 ~ELINK_FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED;
8030 /* get the initial value of the link params */
8031 sc->link_params.multi_phy_config =
8032 SHMEM_RD(sc, dev_info.port_hw_config[port].multi_phy_config);
8034 /* get external phy info */
8035 sc->port.ext_phy_config =
8036 SHMEM_RD(sc, dev_info.port_hw_config[port].external_phy_config);
8038 /* get the multifunction configuration */
8039 bnx2x_get_mf_cfg_info(sc);
8041 /* get the mac address */
8044 MFCFG_RD(sc, func_mf_config[SC_ABS_FUNC(sc)].mac_upper);
8046 MFCFG_RD(sc, func_mf_config[SC_ABS_FUNC(sc)].mac_lower);
8048 mac_hi = SHMEM_RD(sc, dev_info.port_hw_config[port].mac_upper);
8049 mac_lo = SHMEM_RD(sc, dev_info.port_hw_config[port].mac_lower);
8052 if ((mac_lo == 0) && (mac_hi == 0)) {
8053 *sc->mac_addr_str = 0;
8054 PMD_DRV_LOG(NOTICE, "No Ethernet address programmed!");
8056 sc->link_params.mac_addr[0] = (uint8_t) (mac_hi >> 8);
8057 sc->link_params.mac_addr[1] = (uint8_t) (mac_hi);
8058 sc->link_params.mac_addr[2] = (uint8_t) (mac_lo >> 24);
8059 sc->link_params.mac_addr[3] = (uint8_t) (mac_lo >> 16);
8060 sc->link_params.mac_addr[4] = (uint8_t) (mac_lo >> 8);
8061 sc->link_params.mac_addr[5] = (uint8_t) (mac_lo);
8062 snprintf(sc->mac_addr_str, sizeof(sc->mac_addr_str),
8063 "%02x:%02x:%02x:%02x:%02x:%02x",
8064 sc->link_params.mac_addr[0],
8065 sc->link_params.mac_addr[1],
8066 sc->link_params.mac_addr[2],
8067 sc->link_params.mac_addr[3],
8068 sc->link_params.mac_addr[4],
8069 sc->link_params.mac_addr[5]);
8070 PMD_DRV_LOG(DEBUG, "Ethernet address: %s", sc->mac_addr_str);
8076 static void bnx2x_media_detect(struct bnx2x_softc *sc)
8078 uint32_t phy_idx = bnx2x_get_cur_phy_idx(sc);
8079 switch (sc->link_params.phy[phy_idx].media_type) {
8080 case ELINK_ETH_PHY_SFPP_10G_FIBER:
8081 case ELINK_ETH_PHY_SFP_1G_FIBER:
8082 case ELINK_ETH_PHY_XFP_FIBER:
8083 case ELINK_ETH_PHY_KR:
8084 case ELINK_ETH_PHY_CX4:
8085 PMD_DRV_LOG(INFO, "Found 10GBase-CX4 media.");
8086 sc->media = IFM_10G_CX4;
8088 case ELINK_ETH_PHY_DA_TWINAX:
8089 PMD_DRV_LOG(INFO, "Found 10Gb Twinax media.");
8090 sc->media = IFM_10G_TWINAX;
8092 case ELINK_ETH_PHY_BASE_T:
8093 PMD_DRV_LOG(INFO, "Found 10GBase-T media.");
8094 sc->media = IFM_10G_T;
8096 case ELINK_ETH_PHY_NOT_PRESENT:
8097 PMD_DRV_LOG(INFO, "Media not present.");
8100 case ELINK_ETH_PHY_UNSPECIFIED:
8102 PMD_DRV_LOG(INFO, "Unknown media!");
8108 #define GET_FIELD(value, fname) \
8109 (((value) & (fname##_MASK)) >> (fname##_SHIFT))
8110 #define IGU_FID(val) GET_FIELD((val), IGU_REG_MAPPING_MEMORY_FID)
8111 #define IGU_VEC(val) GET_FIELD((val), IGU_REG_MAPPING_MEMORY_VECTOR)
8113 static int bnx2x_get_igu_cam_info(struct bnx2x_softc *sc)
8115 int pfid = SC_FUNC(sc);
8118 uint8_t fid, igu_sb_cnt = 0;
8120 sc->igu_base_sb = 0xff;
8122 if (CHIP_INT_MODE_IS_BC(sc)) {
8124 igu_sb_cnt = sc->igu_sb_cnt;
8125 sc->igu_base_sb = ((CHIP_IS_MODE_4_PORT(sc) ? pfid : vn) *
8127 sc->igu_dsb_id = (E1HVN_MAX * FP_SB_MAX_E1x +
8128 (CHIP_IS_MODE_4_PORT(sc) ? pfid : vn));
8132 /* IGU in normal mode - read CAM */
8134 igu_sb_id < IGU_REG_MAPPING_MEMORY_SIZE; igu_sb_id++) {
8135 val = REG_RD(sc, IGU_REG_MAPPING_MEMORY + igu_sb_id * 4);
8136 if (!(val & IGU_REG_MAPPING_MEMORY_VALID)) {
8140 if ((fid & IGU_FID_ENCODE_IS_PF)) {
8141 if ((fid & IGU_FID_PF_NUM_MASK) != pfid) {
8144 if (IGU_VEC(val) == 0) {
8145 /* default status block */
8146 sc->igu_dsb_id = igu_sb_id;
8148 if (sc->igu_base_sb == 0xff) {
8149 sc->igu_base_sb = igu_sb_id;
8157 * Due to new PF resource allocation by MFW T7.4 and above, it's optional
8158 * that number of CAM entries will not be equal to the value advertised in
8159 * PCI. Driver should use the minimal value of both as the actual status
8162 sc->igu_sb_cnt = min(sc->igu_sb_cnt, igu_sb_cnt);
8164 if (igu_sb_cnt == 0) {
8165 PMD_DRV_LOG(ERR, "CAM configuration error");
8173 * Gather various information from the device config space, the device itself,
8174 * shmem, and the user input.
8176 static int bnx2x_get_device_info(struct bnx2x_softc *sc)
8181 /* get the chip revision (chip metal comes from pci config space) */
8182 sc->devinfo.chip_id = sc->link_params.chip_id =
8183 (((REG_RD(sc, MISC_REG_CHIP_NUM) & 0xffff) << 16) |
8184 ((REG_RD(sc, MISC_REG_CHIP_REV) & 0xf) << 12) |
8185 (((REG_RD(sc, PCICFG_OFFSET + PCI_ID_VAL3) >> 24) & 0xf) << 4) |
8186 ((REG_RD(sc, MISC_REG_BOND_ID) & 0xf) << 0));
8188 /* force 57811 according to MISC register */
8189 if (REG_RD(sc, MISC_REG_CHIP_TYPE) & MISC_REG_CHIP_TYPE_57811_MASK) {
8190 if (CHIP_IS_57810(sc)) {
8191 sc->devinfo.chip_id = ((CHIP_NUM_57811 << 16) |
8193 devinfo.chip_id & 0x0000ffff));
8194 } else if (CHIP_IS_57810_MF(sc)) {
8195 sc->devinfo.chip_id = ((CHIP_NUM_57811_MF << 16) |
8197 devinfo.chip_id & 0x0000ffff));
8199 sc->devinfo.chip_id |= 0x1;
8203 "chip_id=0x%08x (num=0x%04x rev=0x%01x metal=0x%02x bond=0x%01x)",
8204 sc->devinfo.chip_id,
8205 ((sc->devinfo.chip_id >> 16) & 0xffff),
8206 ((sc->devinfo.chip_id >> 12) & 0xf),
8207 ((sc->devinfo.chip_id >> 4) & 0xff),
8208 ((sc->devinfo.chip_id >> 0) & 0xf));
8210 val = (REG_RD(sc, 0x2874) & 0x55);
8211 if ((sc->devinfo.chip_id & 0x1) || (CHIP_IS_E1H(sc) && (val == 0x55))) {
8212 sc->flags |= BNX2X_ONE_PORT_FLAG;
8213 PMD_DRV_LOG(DEBUG, "single port device");
8216 /* set the doorbell size */
8217 sc->doorbell_size = (1 << BNX2X_DB_SHIFT);
8219 /* determine whether the device is in 2 port or 4 port mode */
8220 sc->devinfo.chip_port_mode = CHIP_PORT_MODE_NONE; /* E1h */
8221 if (CHIP_IS_E2E3(sc)) {
8223 * Read port4mode_en_ovwr[0]:
8224 * If 1, four port mode is in port4mode_en_ovwr[1].
8225 * If 0, four port mode is in port4mode_en[0].
8227 val = REG_RD(sc, MISC_REG_PORT4MODE_EN_OVWR);
8229 val = ((val >> 1) & 1);
8231 val = REG_RD(sc, MISC_REG_PORT4MODE_EN);
8234 sc->devinfo.chip_port_mode =
8235 (val) ? CHIP_4_PORT_MODE : CHIP_2_PORT_MODE;
8237 PMD_DRV_LOG(DEBUG, "Port mode = %s", (val) ? "4" : "2");
8240 /* get the function and path info for the device */
8241 bnx2x_get_function_num(sc);
8243 /* get the shared memory base address */
8244 sc->devinfo.shmem_base =
8245 sc->link_params.shmem_base = REG_RD(sc, MISC_REG_SHARED_MEM_ADDR);
8246 sc->devinfo.shmem2_base =
8247 REG_RD(sc, (SC_PATH(sc) ? MISC_REG_GENERIC_CR_1 :
8248 MISC_REG_GENERIC_CR_0));
8250 if (!sc->devinfo.shmem_base) {
8251 /* this should ONLY prevent upcoming shmem reads */
8252 PMD_DRV_LOG(INFO, "MCP not active");
8253 sc->flags |= BNX2X_NO_MCP_FLAG;
8257 /* make sure the shared memory contents are valid */
8258 val = SHMEM_RD(sc, validity_map[SC_PORT(sc)]);
8259 if ((val & (SHR_MEM_VALIDITY_DEV_INFO | SHR_MEM_VALIDITY_MB)) !=
8260 (SHR_MEM_VALIDITY_DEV_INFO | SHR_MEM_VALIDITY_MB)) {
8261 PMD_DRV_LOG(NOTICE, "Invalid SHMEM validity signature: 0x%08x",
8266 /* get the bootcode version */
8267 sc->devinfo.bc_ver = SHMEM_RD(sc, dev_info.bc_rev);
8268 snprintf(sc->devinfo.bc_ver_str,
8269 sizeof(sc->devinfo.bc_ver_str),
8271 ((sc->devinfo.bc_ver >> 24) & 0xff),
8272 ((sc->devinfo.bc_ver >> 16) & 0xff),
8273 ((sc->devinfo.bc_ver >> 8) & 0xff));
8274 PMD_DRV_LOG(INFO, "Bootcode version: %s", sc->devinfo.bc_ver_str);
8276 /* get the bootcode shmem address */
8277 sc->devinfo.mf_cfg_base = bnx2x_get_shmem_mf_cfg_base(sc);
8279 /* clean indirect addresses as they're not used */
8280 pci_write_long(sc, PCICFG_GRC_ADDRESS, 0);
8282 REG_WR(sc, PXP2_REG_PGL_ADDR_88_F0, 0);
8283 REG_WR(sc, PXP2_REG_PGL_ADDR_8C_F0, 0);
8284 REG_WR(sc, PXP2_REG_PGL_ADDR_90_F0, 0);
8285 REG_WR(sc, PXP2_REG_PGL_ADDR_94_F0, 0);
8286 if (CHIP_IS_E1x(sc)) {
8287 REG_WR(sc, PXP2_REG_PGL_ADDR_88_F1, 0);
8288 REG_WR(sc, PXP2_REG_PGL_ADDR_8C_F1, 0);
8289 REG_WR(sc, PXP2_REG_PGL_ADDR_90_F1, 0);
8290 REG_WR(sc, PXP2_REG_PGL_ADDR_94_F1, 0);
8294 * Enable internal target-read (in case we are probed after PF
8295 * FLR). Must be done prior to any BAR read access. Only for
8298 if (!CHIP_IS_E1x(sc)) {
8299 REG_WR(sc, PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_READ,
8304 /* get the nvram size */
8305 val = REG_RD(sc, MCP_REG_MCPR_NVM_CFG4);
8306 sc->devinfo.flash_size =
8307 (NVRAM_1MB_SIZE << (val & MCPR_NVM_CFG4_FLASH_SIZE));
8309 bnx2x_set_power_state(sc, PCI_PM_D0);
8310 /* get various configuration parameters from shmem */
8311 bnx2x_get_shmem_info(sc);
8313 /* initialize IGU parameters */
8314 if (CHIP_IS_E1x(sc)) {
8315 sc->devinfo.int_block = INT_BLOCK_HC;
8316 sc->igu_dsb_id = DEF_SB_IGU_ID;
8317 sc->igu_base_sb = 0;
8319 sc->devinfo.int_block = INT_BLOCK_IGU;
8321 /* do not allow device reset during IGU info preocessing */
8322 bnx2x_acquire_hw_lock(sc, HW_LOCK_RESOURCE_RESET);
8324 val = REG_RD(sc, IGU_REG_BLOCK_CONFIGURATION);
8326 if (val & IGU_BLOCK_CONFIGURATION_REG_BACKWARD_COMP_EN) {
8329 val &= ~(IGU_BLOCK_CONFIGURATION_REG_BACKWARD_COMP_EN);
8330 REG_WR(sc, IGU_REG_BLOCK_CONFIGURATION, val);
8331 REG_WR(sc, IGU_REG_RESET_MEMORIES, 0x7f);
8333 while (tout && REG_RD(sc, IGU_REG_RESET_MEMORIES)) {
8338 if (REG_RD(sc, IGU_REG_RESET_MEMORIES)) {
8340 "FORCING IGU Normal Mode failed!!!");
8341 bnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_RESET);
8346 if (val & IGU_BLOCK_CONFIGURATION_REG_BACKWARD_COMP_EN) {
8347 PMD_DRV_LOG(DEBUG, "IGU Backward Compatible Mode");
8348 sc->devinfo.int_block |= INT_BLOCK_MODE_BW_COMP;
8350 PMD_DRV_LOG(DEBUG, "IGU Normal Mode");
8353 rc = bnx2x_get_igu_cam_info(sc);
8355 bnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_RESET);
8363 * Get base FW non-default (fast path) status block ID. This value is
8364 * used to initialize the fw_sb_id saved on the fp/queue structure to
8365 * determine the id used by the FW.
8367 if (CHIP_IS_E1x(sc)) {
8369 ((SC_PORT(sc) * FP_SB_MAX_E1x) + SC_L_ID(sc));
8372 * 57712+ - We currently use one FW SB per IGU SB (Rx and Tx of
8373 * the same queue are indicated on the same IGU SB). So we prefer
8374 * FW and IGU SBs to be the same value.
8376 sc->base_fw_ndsb = sc->igu_base_sb;
8379 elink_phy_probe(&sc->link_params);
8385 bnx2x_link_settings_supported(struct bnx2x_softc *sc, uint32_t switch_cfg)
8387 uint32_t cfg_size = 0;
8389 uint8_t port = SC_PORT(sc);
8391 /* aggregation of supported attributes of all external phys */
8392 sc->port.supported[0] = 0;
8393 sc->port.supported[1] = 0;
8395 switch (sc->link_params.num_phys) {
8397 sc->port.supported[0] =
8398 sc->link_params.phy[ELINK_INT_PHY].supported;
8402 sc->port.supported[0] =
8403 sc->link_params.phy[ELINK_EXT_PHY1].supported;
8407 if (sc->link_params.multi_phy_config &
8408 PORT_HW_CFG_PHY_SWAPPED_ENABLED) {
8409 sc->port.supported[1] =
8410 sc->link_params.phy[ELINK_EXT_PHY1].supported;
8411 sc->port.supported[0] =
8412 sc->link_params.phy[ELINK_EXT_PHY2].supported;
8414 sc->port.supported[0] =
8415 sc->link_params.phy[ELINK_EXT_PHY1].supported;
8416 sc->port.supported[1] =
8417 sc->link_params.phy[ELINK_EXT_PHY2].supported;
8423 if (!(sc->port.supported[0] || sc->port.supported[1])) {
8425 "Invalid phy config in NVRAM (PHY1=0x%08x PHY2=0x%08x)",
8427 dev_info.port_hw_config
8428 [port].external_phy_config),
8430 dev_info.port_hw_config
8431 [port].external_phy_config2));
8436 sc->port.phy_addr = REG_RD(sc, MISC_REG_WC0_CTRL_PHY_ADDR);
8438 switch (switch_cfg) {
8439 case ELINK_SWITCH_CFG_1G:
8442 NIG_REG_SERDES0_CTRL_PHY_ADDR + port * 0x10);
8444 case ELINK_SWITCH_CFG_10G:
8447 NIG_REG_XGXS0_CTRL_PHY_ADDR + port * 0x18);
8451 "Invalid switch config in"
8452 "link_config=0x%08x",
8453 sc->port.link_config[0]);
8458 PMD_DRV_LOG(INFO, "PHY addr 0x%08x", sc->port.phy_addr);
8460 /* mask what we support according to speed_cap_mask per configuration */
8461 for (idx = 0; idx < cfg_size; idx++) {
8462 if (!(sc->link_params.speed_cap_mask[idx] &
8463 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_HALF)) {
8464 sc->port.supported[idx] &=
8465 ~ELINK_SUPPORTED_10baseT_Half;
8468 if (!(sc->link_params.speed_cap_mask[idx] &
8469 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL)) {
8470 sc->port.supported[idx] &=
8471 ~ELINK_SUPPORTED_10baseT_Full;
8474 if (!(sc->link_params.speed_cap_mask[idx] &
8475 PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_HALF)) {
8476 sc->port.supported[idx] &=
8477 ~ELINK_SUPPORTED_100baseT_Half;
8480 if (!(sc->link_params.speed_cap_mask[idx] &
8481 PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_FULL)) {
8482 sc->port.supported[idx] &=
8483 ~ELINK_SUPPORTED_100baseT_Full;
8486 if (!(sc->link_params.speed_cap_mask[idx] &
8487 PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)) {
8488 sc->port.supported[idx] &=
8489 ~ELINK_SUPPORTED_1000baseT_Full;
8492 if (!(sc->link_params.speed_cap_mask[idx] &
8493 PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G)) {
8494 sc->port.supported[idx] &=
8495 ~ELINK_SUPPORTED_2500baseX_Full;
8498 if (!(sc->link_params.speed_cap_mask[idx] &
8499 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)) {
8500 sc->port.supported[idx] &=
8501 ~ELINK_SUPPORTED_10000baseT_Full;
8504 if (!(sc->link_params.speed_cap_mask[idx] &
8505 PORT_HW_CFG_SPEED_CAPABILITY_D0_20G)) {
8506 sc->port.supported[idx] &=
8507 ~ELINK_SUPPORTED_20000baseKR2_Full;
8511 PMD_DRV_LOG(INFO, "PHY supported 0=0x%08x 1=0x%08x",
8512 sc->port.supported[0], sc->port.supported[1]);
8515 static void bnx2x_link_settings_requested(struct bnx2x_softc *sc)
8517 uint32_t link_config;
8519 uint32_t cfg_size = 0;
8521 sc->port.advertising[0] = 0;
8522 sc->port.advertising[1] = 0;
8524 switch (sc->link_params.num_phys) {
8534 for (idx = 0; idx < cfg_size; idx++) {
8535 sc->link_params.req_duplex[idx] = DUPLEX_FULL;
8536 link_config = sc->port.link_config[idx];
8538 switch (link_config & PORT_FEATURE_LINK_SPEED_MASK) {
8539 case PORT_FEATURE_LINK_SPEED_AUTO:
8540 if (sc->port.supported[idx] & ELINK_SUPPORTED_Autoneg) {
8541 sc->link_params.req_line_speed[idx] =
8542 ELINK_SPEED_AUTO_NEG;
8543 sc->port.advertising[idx] |=
8544 sc->port.supported[idx];
8545 if (sc->link_params.phy[ELINK_EXT_PHY1].type ==
8546 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X84833)
8547 sc->port.advertising[idx] |=
8548 (ELINK_SUPPORTED_100baseT_Half |
8549 ELINK_SUPPORTED_100baseT_Full);
8551 /* force 10G, no AN */
8552 sc->link_params.req_line_speed[idx] =
8554 sc->port.advertising[idx] |=
8555 (ADVERTISED_10000baseT_Full |
8561 case PORT_FEATURE_LINK_SPEED_10M_FULL:
8563 port.supported[idx] & ELINK_SUPPORTED_10baseT_Full)
8565 sc->link_params.req_line_speed[idx] =
8567 sc->port.advertising[idx] |=
8568 (ADVERTISED_10baseT_Full | ADVERTISED_TP);
8571 "Invalid NVRAM config link_config=0x%08x "
8572 "speed_cap_mask=0x%08x",
8575 link_params.speed_cap_mask[idx]);
8580 case PORT_FEATURE_LINK_SPEED_10M_HALF:
8582 port.supported[idx] & ELINK_SUPPORTED_10baseT_Half)
8584 sc->link_params.req_line_speed[idx] =
8586 sc->link_params.req_duplex[idx] = DUPLEX_HALF;
8587 sc->port.advertising[idx] |=
8588 (ADVERTISED_10baseT_Half | ADVERTISED_TP);
8591 "Invalid NVRAM config link_config=0x%08x "
8592 "speed_cap_mask=0x%08x",
8595 link_params.speed_cap_mask[idx]);
8600 case PORT_FEATURE_LINK_SPEED_100M_FULL:
8602 port.supported[idx] & ELINK_SUPPORTED_100baseT_Full)
8604 sc->link_params.req_line_speed[idx] =
8606 sc->port.advertising[idx] |=
8607 (ADVERTISED_100baseT_Full | ADVERTISED_TP);
8610 "Invalid NVRAM config link_config=0x%08x "
8611 "speed_cap_mask=0x%08x",
8614 link_params.speed_cap_mask[idx]);
8619 case PORT_FEATURE_LINK_SPEED_100M_HALF:
8621 port.supported[idx] & ELINK_SUPPORTED_100baseT_Half)
8623 sc->link_params.req_line_speed[idx] =
8625 sc->link_params.req_duplex[idx] = DUPLEX_HALF;
8626 sc->port.advertising[idx] |=
8627 (ADVERTISED_100baseT_Half | ADVERTISED_TP);
8630 "Invalid NVRAM config link_config=0x%08x "
8631 "speed_cap_mask=0x%08x",
8634 link_params.speed_cap_mask[idx]);
8639 case PORT_FEATURE_LINK_SPEED_1G:
8640 if (sc->port.supported[idx] &
8641 ELINK_SUPPORTED_1000baseT_Full) {
8642 sc->link_params.req_line_speed[idx] =
8644 sc->port.advertising[idx] |=
8645 (ADVERTISED_1000baseT_Full | ADVERTISED_TP);
8648 "Invalid NVRAM config link_config=0x%08x "
8649 "speed_cap_mask=0x%08x",
8652 link_params.speed_cap_mask[idx]);
8657 case PORT_FEATURE_LINK_SPEED_2_5G:
8658 if (sc->port.supported[idx] &
8659 ELINK_SUPPORTED_2500baseX_Full) {
8660 sc->link_params.req_line_speed[idx] =
8662 sc->port.advertising[idx] |=
8663 (ADVERTISED_2500baseX_Full | ADVERTISED_TP);
8666 "Invalid NVRAM config link_config=0x%08x "
8667 "speed_cap_mask=0x%08x",
8670 link_params.speed_cap_mask[idx]);
8675 case PORT_FEATURE_LINK_SPEED_10G_CX4:
8676 if (sc->port.supported[idx] &
8677 ELINK_SUPPORTED_10000baseT_Full) {
8678 sc->link_params.req_line_speed[idx] =
8680 sc->port.advertising[idx] |=
8681 (ADVERTISED_10000baseT_Full |
8685 "Invalid NVRAM config link_config=0x%08x "
8686 "speed_cap_mask=0x%08x",
8689 link_params.speed_cap_mask[idx]);
8694 case PORT_FEATURE_LINK_SPEED_20G:
8695 sc->link_params.req_line_speed[idx] = ELINK_SPEED_20000;
8700 "Invalid NVRAM config link_config=0x%08x "
8701 "speed_cap_mask=0x%08x", link_config,
8702 sc->link_params.speed_cap_mask[idx]);
8703 sc->link_params.req_line_speed[idx] =
8704 ELINK_SPEED_AUTO_NEG;
8705 sc->port.advertising[idx] = sc->port.supported[idx];
8709 sc->link_params.req_flow_ctrl[idx] =
8710 (link_config & PORT_FEATURE_FLOW_CONTROL_MASK);
8712 if (sc->link_params.req_flow_ctrl[idx] == ELINK_FLOW_CTRL_AUTO) {
8715 port.supported[idx] & ELINK_SUPPORTED_Autoneg)) {
8716 sc->link_params.req_flow_ctrl[idx] =
8717 ELINK_FLOW_CTRL_NONE;
8719 bnx2x_set_requested_fc(sc);
8725 static void bnx2x_get_phy_info(struct bnx2x_softc *sc)
8727 uint8_t port = SC_PORT(sc);
8730 PMD_INIT_FUNC_TRACE();
8732 /* shmem data already read in bnx2x_get_shmem_info() */
8734 bnx2x_link_settings_supported(sc, sc->link_params.switch_cfg);
8735 bnx2x_link_settings_requested(sc);
8737 /* configure link feature according to nvram value */
8739 (((SHMEM_RD(sc, dev_info.port_feature_config[port].eee_power_mode))
8740 & PORT_FEAT_CFG_EEE_POWER_MODE_MASK) >>
8741 PORT_FEAT_CFG_EEE_POWER_MODE_SHIFT);
8742 if (eee_mode != PORT_FEAT_CFG_EEE_POWER_MODE_DISABLED) {
8743 sc->link_params.eee_mode = (ELINK_EEE_MODE_ADV_LPI |
8744 ELINK_EEE_MODE_ENABLE_LPI |
8745 ELINK_EEE_MODE_OUTPUT_TIME);
8747 sc->link_params.eee_mode = 0;
8750 /* get the media type */
8751 bnx2x_media_detect(sc);
8754 static void bnx2x_set_modes_bitmap(struct bnx2x_softc *sc)
8756 uint32_t flags = MODE_ASIC | MODE_PORT2;
8758 if (CHIP_IS_E2(sc)) {
8760 } else if (CHIP_IS_E3(sc)) {
8762 if (CHIP_REV(sc) == CHIP_REV_Ax) {
8763 flags |= MODE_E3_A0;
8764 } else { /*if (CHIP_REV(sc) == CHIP_REV_Bx) */
8766 flags |= MODE_E3_B0 | MODE_COS3;
8772 switch (sc->devinfo.mf_info.mf_mode) {
8773 case MULTI_FUNCTION_SD:
8774 flags |= MODE_MF_SD;
8776 case MULTI_FUNCTION_SI:
8777 flags |= MODE_MF_SI;
8779 case MULTI_FUNCTION_AFEX:
8780 flags |= MODE_MF_AFEX;
8787 #if defined(__LITTLE_ENDIAN)
8788 flags |= MODE_LITTLE_ENDIAN;
8789 #else /* __BIG_ENDIAN */
8790 flags |= MODE_BIG_ENDIAN;
8793 INIT_MODE_FLAGS(sc) = flags;
8796 int bnx2x_alloc_hsi_mem(struct bnx2x_softc *sc)
8798 struct bnx2x_fastpath *fp;
8803 /************************/
8804 /* DEFAULT STATUS BLOCK */
8805 /************************/
8807 if (bnx2x_dma_alloc(sc, sizeof(struct host_sp_status_block),
8808 &sc->def_sb_dma, "def_sb",
8809 RTE_CACHE_LINE_SIZE) != 0) {
8814 (struct host_sp_status_block *)sc->def_sb_dma.vaddr;
8819 if (bnx2x_dma_alloc(sc, BNX2X_PAGE_SIZE,
8820 &sc->eq_dma, "ev_queue",
8821 RTE_CACHE_LINE_SIZE) != 0) {
8826 sc->eq = (union event_ring_elem *)sc->eq_dma.vaddr;
8832 if (bnx2x_dma_alloc(sc, sizeof(struct bnx2x_slowpath),
8834 RTE_CACHE_LINE_SIZE) != 0) {
8840 sc->sp = (struct bnx2x_slowpath *)sc->sp_dma.vaddr;
8842 /*******************/
8843 /* SLOW PATH QUEUE */
8844 /*******************/
8846 if (bnx2x_dma_alloc(sc, BNX2X_PAGE_SIZE,
8847 &sc->spq_dma, "sp_queue",
8848 RTE_CACHE_LINE_SIZE) != 0) {
8855 sc->spq = (struct eth_spe *)sc->spq_dma.vaddr;
8857 /***************************/
8858 /* FW DECOMPRESSION BUFFER */
8859 /***************************/
8861 if (bnx2x_dma_alloc(sc, FW_BUF_SIZE, &sc->gz_buf_dma,
8862 "fw_buf", RTE_CACHE_LINE_SIZE) != 0) {
8870 sc->gz_buf = (void *)sc->gz_buf_dma.vaddr;
8877 /* allocate DMA memory for each fastpath structure */
8878 for (i = 0; i < sc->num_queues; i++) {
8883 /*******************/
8884 /* FP STATUS BLOCK */
8885 /*******************/
8887 snprintf(buf, sizeof(buf), "fp_%d_sb", i);
8888 if (bnx2x_dma_alloc(sc, sizeof(union bnx2x_host_hc_status_block),
8889 &fp->sb_dma, buf, RTE_CACHE_LINE_SIZE) != 0) {
8890 PMD_DRV_LOG(NOTICE, "Failed to alloc %s", buf);
8893 if (CHIP_IS_E2E3(sc)) {
8894 fp->status_block.e2_sb =
8895 (struct host_hc_status_block_e2 *)
8898 fp->status_block.e1x_sb =
8899 (struct host_hc_status_block_e1x *)
8908 void bnx2x_free_hsi_mem(struct bnx2x_softc *sc)
8910 struct bnx2x_fastpath *fp;
8913 for (i = 0; i < sc->num_queues; i++) {
8916 /*******************/
8917 /* FP STATUS BLOCK */
8918 /*******************/
8920 memset(&fp->status_block, 0, sizeof(fp->status_block));
8923 /***************************/
8924 /* FW DECOMPRESSION BUFFER */
8925 /***************************/
8929 /*******************/
8930 /* SLOW PATH QUEUE */
8931 /*******************/
8947 /************************/
8948 /* DEFAULT STATUS BLOCK */
8949 /************************/
8956 * Previous driver DMAE transaction may have occurred when pre-boot stage
8957 * ended and boot began. This would invalidate the addresses of the
8958 * transaction, resulting in was-error bit set in the PCI causing all
8959 * hw-to-host PCIe transactions to timeout. If this happened we want to clear
8960 * the interrupt which detected this from the pglueb and the was-done bit
8962 static void bnx2x_prev_interrupted_dmae(struct bnx2x_softc *sc)
8966 if (!CHIP_IS_E1x(sc)) {
8967 val = REG_RD(sc, PGLUE_B_REG_PGLUE_B_INT_STS);
8968 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_WAS_ERROR_ATTN) {
8969 REG_WR(sc, PGLUE_B_REG_WAS_ERROR_PF_7_0_CLR,
8975 static int bnx2x_prev_mcp_done(struct bnx2x_softc *sc)
8977 uint32_t rc = bnx2x_fw_command(sc, DRV_MSG_CODE_UNLOAD_DONE,
8978 DRV_MSG_CODE_UNLOAD_SKIP_LINK_RESET);
8980 PMD_DRV_LOG(NOTICE, "MCP response failure, aborting");
8987 static struct bnx2x_prev_list_node *bnx2x_prev_path_get_entry(struct bnx2x_softc *sc)
8989 struct bnx2x_prev_list_node *tmp;
8991 LIST_FOREACH(tmp, &bnx2x_prev_list, node) {
8992 if ((sc->pcie_bus == tmp->bus) &&
8993 (sc->pcie_device == tmp->slot) &&
8994 (SC_PATH(sc) == tmp->path)) {
9002 static uint8_t bnx2x_prev_is_path_marked(struct bnx2x_softc *sc)
9004 struct bnx2x_prev_list_node *tmp;
9007 rte_spinlock_lock(&bnx2x_prev_mtx);
9009 tmp = bnx2x_prev_path_get_entry(sc);
9013 "Path %d/%d/%d was marked by AER",
9014 sc->pcie_bus, sc->pcie_device, SC_PATH(sc));
9018 "Path %d/%d/%d was already cleaned from previous drivers",
9019 sc->pcie_bus, sc->pcie_device, SC_PATH(sc));
9023 rte_spinlock_unlock(&bnx2x_prev_mtx);
9028 static int bnx2x_prev_mark_path(struct bnx2x_softc *sc, uint8_t after_undi)
9030 struct bnx2x_prev_list_node *tmp;
9032 rte_spinlock_lock(&bnx2x_prev_mtx);
9034 /* Check whether the entry for this path already exists */
9035 tmp = bnx2x_prev_path_get_entry(sc);
9039 "Re-marking AER in path %d/%d/%d",
9040 sc->pcie_bus, sc->pcie_device, SC_PATH(sc));
9043 "Removing AER indication from path %d/%d/%d",
9044 sc->pcie_bus, sc->pcie_device, SC_PATH(sc));
9048 rte_spinlock_unlock(&bnx2x_prev_mtx);
9052 rte_spinlock_unlock(&bnx2x_prev_mtx);
9054 /* Create an entry for this path and add it */
9055 tmp = rte_malloc("", sizeof(struct bnx2x_prev_list_node),
9056 RTE_CACHE_LINE_SIZE);
9058 PMD_DRV_LOG(NOTICE, "Failed to allocate 'bnx2x_prev_list_node'");
9062 tmp->bus = sc->pcie_bus;
9063 tmp->slot = sc->pcie_device;
9064 tmp->path = SC_PATH(sc);
9066 tmp->undi = after_undi ? (1 << SC_PORT(sc)) : 0;
9068 rte_spinlock_lock(&bnx2x_prev_mtx);
9070 LIST_INSERT_HEAD(&bnx2x_prev_list, tmp, node);
9072 rte_spinlock_unlock(&bnx2x_prev_mtx);
9077 static int bnx2x_do_flr(struct bnx2x_softc *sc)
9081 /* only E2 and onwards support FLR */
9082 if (CHIP_IS_E1x(sc)) {
9083 PMD_DRV_LOG(WARNING, "FLR not supported in E1H");
9087 /* only bootcode REQ_BC_VER_4_INITIATE_FLR and onwards support flr */
9088 if (sc->devinfo.bc_ver < REQ_BC_VER_4_INITIATE_FLR) {
9089 PMD_DRV_LOG(WARNING,
9090 "FLR not supported by BC_VER: 0x%08x",
9091 sc->devinfo.bc_ver);
9095 /* Wait for Transaction Pending bit clean */
9096 for (i = 0; i < 4; i++) {
9098 DELAY(((1 << (i - 1)) * 100) * 1000);
9101 if (!bnx2x_is_pcie_pending(sc)) {
9106 PMD_DRV_LOG(NOTICE, "PCIE transaction is not cleared, "
9107 "proceeding with reset anyway");
9110 bnx2x_fw_command(sc, DRV_MSG_CODE_INITIATE_FLR, 0);
9115 struct bnx2x_mac_vals {
9123 uint32_t bmac_val[2];
9127 bnx2x_prev_unload_close_mac(struct bnx2x_softc *sc, struct bnx2x_mac_vals *vals)
9129 uint32_t val, base_addr, offset, mask, reset_reg;
9130 uint8_t mac_stopped = FALSE;
9131 uint8_t port = SC_PORT(sc);
9132 uint32_t wb_data[2];
9134 /* reset addresses as they also mark which values were changed */
9135 vals->bmac_addr = 0;
9136 vals->umac_addr = 0;
9137 vals->xmac_addr = 0;
9138 vals->emac_addr = 0;
9140 reset_reg = REG_RD(sc, MISC_REG_RESET_REG_2);
9142 if (!CHIP_IS_E3(sc)) {
9143 val = REG_RD(sc, NIG_REG_BMAC0_REGS_OUT_EN + port * 4);
9144 mask = MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port;
9145 if ((mask & reset_reg) && val) {
9146 base_addr = SC_PORT(sc) ? NIG_REG_INGRESS_BMAC1_MEM
9147 : NIG_REG_INGRESS_BMAC0_MEM;
9148 offset = CHIP_IS_E2(sc) ? BIGMAC2_REGISTER_BMAC_CONTROL
9149 : BIGMAC_REGISTER_BMAC_CONTROL;
9152 * use rd/wr since we cannot use dmae. This is safe
9153 * since MCP won't access the bus due to the request
9154 * to unload, and no function on the path can be
9155 * loaded at this time.
9157 wb_data[0] = REG_RD(sc, base_addr + offset);
9158 wb_data[1] = REG_RD(sc, base_addr + offset + 0x4);
9159 vals->bmac_addr = base_addr + offset;
9160 vals->bmac_val[0] = wb_data[0];
9161 vals->bmac_val[1] = wb_data[1];
9162 wb_data[0] &= ~ELINK_BMAC_CONTROL_RX_ENABLE;
9163 REG_WR(sc, vals->bmac_addr, wb_data[0]);
9164 REG_WR(sc, vals->bmac_addr + 0x4, wb_data[1]);
9167 vals->emac_addr = NIG_REG_NIG_EMAC0_EN + SC_PORT(sc) * 4;
9168 vals->emac_val = REG_RD(sc, vals->emac_addr);
9169 REG_WR(sc, vals->emac_addr, 0);
9172 if (reset_reg & MISC_REGISTERS_RESET_REG_2_XMAC) {
9173 base_addr = SC_PORT(sc) ? GRCBASE_XMAC1 : GRCBASE_XMAC0;
9174 val = REG_RD(sc, base_addr + XMAC_REG_PFC_CTRL_HI);
9175 REG_WR(sc, base_addr + XMAC_REG_PFC_CTRL_HI,
9177 REG_WR(sc, base_addr + XMAC_REG_PFC_CTRL_HI,
9179 vals->xmac_addr = base_addr + XMAC_REG_CTRL;
9180 vals->xmac_val = REG_RD(sc, vals->xmac_addr);
9181 REG_WR(sc, vals->xmac_addr, 0);
9185 mask = MISC_REGISTERS_RESET_REG_2_UMAC0 << port;
9186 if (mask & reset_reg) {
9187 base_addr = SC_PORT(sc) ? GRCBASE_UMAC1 : GRCBASE_UMAC0;
9188 vals->umac_addr = base_addr + UMAC_REG_COMMAND_CONFIG;
9189 vals->umac_val = REG_RD(sc, vals->umac_addr);
9190 REG_WR(sc, vals->umac_addr, 0);
9200 #define BNX2X_PREV_UNDI_PROD_ADDR(p) (BAR_TSTRORM_INTMEM + 0x1508 + ((p) << 4))
9201 #define BNX2X_PREV_UNDI_RCQ(val) ((val) & 0xffff)
9202 #define BNX2X_PREV_UNDI_BD(val) ((val) >> 16 & 0xffff)
9203 #define BNX2X_PREV_UNDI_PROD(rcq, bd) ((bd) << 16 | (rcq))
9206 bnx2x_prev_unload_undi_inc(struct bnx2x_softc *sc, uint8_t port, uint8_t inc)
9209 uint32_t tmp_reg = REG_RD(sc, BNX2X_PREV_UNDI_PROD_ADDR(port));
9211 rcq = BNX2X_PREV_UNDI_RCQ(tmp_reg) + inc;
9212 bd = BNX2X_PREV_UNDI_BD(tmp_reg) + inc;
9214 tmp_reg = BNX2X_PREV_UNDI_PROD(rcq, bd);
9215 REG_WR(sc, BNX2X_PREV_UNDI_PROD_ADDR(port), tmp_reg);
9218 static int bnx2x_prev_unload_common(struct bnx2x_softc *sc)
9220 uint32_t reset_reg, tmp_reg = 0, rc;
9221 uint8_t prev_undi = FALSE;
9222 struct bnx2x_mac_vals mac_vals;
9223 uint32_t timer_count = 1000;
9227 * It is possible a previous function received 'common' answer,
9228 * but hasn't loaded yet, therefore creating a scenario of
9229 * multiple functions receiving 'common' on the same path.
9231 memset(&mac_vals, 0, sizeof(mac_vals));
9233 if (bnx2x_prev_is_path_marked(sc)) {
9234 return bnx2x_prev_mcp_done(sc);
9237 reset_reg = REG_RD(sc, MISC_REG_RESET_REG_1);
9239 /* Reset should be performed after BRB is emptied */
9240 if (reset_reg & MISC_REGISTERS_RESET_REG_1_RST_BRB1) {
9241 /* Close the MAC Rx to prevent BRB from filling up */
9242 bnx2x_prev_unload_close_mac(sc, &mac_vals);
9244 /* close LLH filters towards the BRB */
9245 elink_set_rx_filter(&sc->link_params, 0);
9248 * Check if the UNDI driver was previously loaded.
9249 * UNDI driver initializes CID offset for normal bell to 0x7
9251 if (reset_reg & MISC_REGISTERS_RESET_REG_1_RST_DORQ) {
9252 tmp_reg = REG_RD(sc, DORQ_REG_NORM_CID_OFST);
9253 if (tmp_reg == 0x7) {
9254 PMD_DRV_LOG(DEBUG, "UNDI previously loaded");
9256 /* clear the UNDI indication */
9257 REG_WR(sc, DORQ_REG_NORM_CID_OFST, 0);
9258 /* clear possible idle check errors */
9259 REG_RD(sc, NIG_REG_NIG_INT_STS_CLR_0);
9263 /* wait until BRB is empty */
9264 tmp_reg = REG_RD(sc, BRB1_REG_NUM_OF_FULL_BLOCKS);
9265 while (timer_count) {
9268 tmp_reg = REG_RD(sc, BRB1_REG_NUM_OF_FULL_BLOCKS);
9273 PMD_DRV_LOG(DEBUG, "BRB still has 0x%08x", tmp_reg);
9275 /* reset timer as long as BRB actually gets emptied */
9276 if (prev_brb > tmp_reg) {
9282 /* If UNDI resides in memory, manually increment it */
9284 bnx2x_prev_unload_undi_inc(sc, SC_PORT(sc), 1);
9291 PMD_DRV_LOG(NOTICE, "Failed to empty BRB");
9295 /* No packets are in the pipeline, path is ready for reset */
9296 bnx2x_reset_common(sc);
9298 if (mac_vals.xmac_addr) {
9299 REG_WR(sc, mac_vals.xmac_addr, mac_vals.xmac_val);
9301 if (mac_vals.umac_addr) {
9302 REG_WR(sc, mac_vals.umac_addr, mac_vals.umac_val);
9304 if (mac_vals.emac_addr) {
9305 REG_WR(sc, mac_vals.emac_addr, mac_vals.emac_val);
9307 if (mac_vals.bmac_addr) {
9308 REG_WR(sc, mac_vals.bmac_addr, mac_vals.bmac_val[0]);
9309 REG_WR(sc, mac_vals.bmac_addr + 4, mac_vals.bmac_val[1]);
9312 rc = bnx2x_prev_mark_path(sc, prev_undi);
9314 bnx2x_prev_mcp_done(sc);
9318 return bnx2x_prev_mcp_done(sc);
9321 static int bnx2x_prev_unload_uncommon(struct bnx2x_softc *sc)
9325 /* Test if previous unload process was already finished for this path */
9326 if (bnx2x_prev_is_path_marked(sc)) {
9327 return bnx2x_prev_mcp_done(sc);
9331 * If function has FLR capabilities, and existing FW version matches
9332 * the one required, then FLR will be sufficient to clean any residue
9333 * left by previous driver
9335 rc = bnx2x_nic_load_analyze_req(sc, FW_MSG_CODE_DRV_LOAD_FUNCTION);
9337 /* fw version is good */
9338 rc = bnx2x_do_flr(sc);
9342 /* FLR was performed */
9346 PMD_DRV_LOG(INFO, "Could not FLR");
9348 /* Close the MCP request, return failure */
9349 rc = bnx2x_prev_mcp_done(sc);
9351 rc = BNX2X_PREV_WAIT_NEEDED;
9357 static int bnx2x_prev_unload(struct bnx2x_softc *sc)
9359 int time_counter = 10;
9360 uint32_t fw, hw_lock_reg, hw_lock_val;
9364 * Clear HW from errors which may have resulted from an interrupted
9367 bnx2x_prev_interrupted_dmae(sc);
9369 /* Release previously held locks */
9370 if (SC_FUNC(sc) <= 5)
9371 hw_lock_reg = (MISC_REG_DRIVER_CONTROL_1 + SC_FUNC(sc) * 8);
9374 (MISC_REG_DRIVER_CONTROL_7 + (SC_FUNC(sc) - 6) * 8);
9376 hw_lock_val = (REG_RD(sc, hw_lock_reg));
9378 if (hw_lock_val & HW_LOCK_RESOURCE_NVRAM) {
9379 REG_WR(sc, MCP_REG_MCPR_NVM_SW_ARB,
9380 (MCPR_NVM_SW_ARB_ARB_REQ_CLR1 << SC_PORT(sc)));
9382 REG_WR(sc, hw_lock_reg, 0xffffffff);
9385 if (MCPR_ACCESS_LOCK_LOCK & REG_RD(sc, MCP_REG_MCPR_ACCESS_LOCK)) {
9386 REG_WR(sc, MCP_REG_MCPR_ACCESS_LOCK, 0);
9390 /* Lock MCP using an unload request */
9391 fw = bnx2x_fw_command(sc, DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS, 0);
9393 PMD_DRV_LOG(NOTICE, "MCP response failure, aborting");
9398 if (fw == FW_MSG_CODE_DRV_UNLOAD_COMMON) {
9399 rc = bnx2x_prev_unload_common(sc);
9403 /* non-common reply from MCP might require looping */
9404 rc = bnx2x_prev_unload_uncommon(sc);
9405 if (rc != BNX2X_PREV_WAIT_NEEDED) {
9410 } while (--time_counter);
9412 if (!time_counter || rc) {
9413 PMD_DRV_LOG(NOTICE, "Failed to unload previous driver!");
9421 bnx2x_dcbx_set_state(struct bnx2x_softc *sc, uint8_t dcb_on, uint32_t dcbx_enabled)
9423 if (!CHIP_IS_E1x(sc)) {
9424 sc->dcb_state = dcb_on;
9425 sc->dcbx_enabled = dcbx_enabled;
9427 sc->dcb_state = FALSE;
9428 sc->dcbx_enabled = BNX2X_DCBX_ENABLED_INVALID;
9431 "DCB state [%s:%s]",
9432 dcb_on ? "ON" : "OFF",
9433 (dcbx_enabled == BNX2X_DCBX_ENABLED_OFF) ? "user-mode" :
9435 BNX2X_DCBX_ENABLED_ON_NEG_OFF) ? "on-chip static"
9437 BNX2X_DCBX_ENABLED_ON_NEG_ON) ?
9438 "on-chip with negotiation" : "invalid");
9441 static int bnx2x_set_qm_cid_count(struct bnx2x_softc *sc)
9443 int cid_count = BNX2X_L2_MAX_CID(sc);
9445 if (CNIC_SUPPORT(sc)) {
9446 cid_count += CNIC_CID_MAX;
9449 return roundup(cid_count, QM_CID_ROUND);
9452 static void bnx2x_init_multi_cos(struct bnx2x_softc *sc)
9456 uint32_t pri_map = 0;
9458 for (pri = 0; pri < BNX2X_MAX_PRIORITY; pri++) {
9459 cos = ((pri_map & (0xf << (pri * 4))) >> (pri * 4));
9460 if (cos < sc->max_cos) {
9461 sc->prio_to_cos[pri] = cos;
9463 PMD_DRV_LOG(WARNING,
9464 "Invalid COS %d for priority %d "
9465 "(max COS is %d), setting to 0", cos, pri,
9467 sc->prio_to_cos[pri] = 0;
9472 static int bnx2x_pci_get_caps(struct bnx2x_softc *sc)
9479 struct bnx2x_pci_cap *cap;
9481 cap = sc->pci_caps = rte_zmalloc("caps", sizeof(struct bnx2x_pci_cap),
9482 RTE_CACHE_LINE_SIZE);
9484 PMD_DRV_LOG(NOTICE, "Failed to allocate memory");
9489 pci_read(sc, PCI_STATUS, &status, 2);
9490 if (!(status & PCI_STATUS_CAP_LIST)) {
9492 pci_read(sc, PCIR_STATUS, &status, 2);
9493 if (!(status & PCIM_STATUS_CAPPRESENT)) {
9495 PMD_DRV_LOG(NOTICE, "PCIe capability reading failed");
9500 pci_read(sc, PCI_CAPABILITY_LIST, &pci_cap.next, 1);
9502 pci_read(sc, PCIR_CAP_PTR, &pci_cap.next, 1);
9504 while (pci_cap.next) {
9505 cap->addr = pci_cap.next & ~3;
9506 pci_read(sc, pci_cap.next & ~3, &pci_cap, 2);
9507 if (pci_cap.id == 0xff)
9509 cap->id = pci_cap.id;
9510 cap->type = BNX2X_PCI_CAP;
9511 cap->next = rte_zmalloc("pci_cap",
9512 sizeof(struct bnx2x_pci_cap),
9513 RTE_CACHE_LINE_SIZE);
9515 PMD_DRV_LOG(NOTICE, "Failed to allocate memory");
9524 static void bnx2x_init_rte(struct bnx2x_softc *sc)
9527 sc->max_tx_queues = min(BNX2X_VF_MAX_QUEUES_PER_VF,
9529 sc->max_rx_queues = min(BNX2X_VF_MAX_QUEUES_PER_VF,
9532 sc->max_rx_queues = BNX2X_MAX_RSS_COUNT(sc);
9533 sc->max_tx_queues = sc->max_rx_queues;
9537 #define FW_HEADER_LEN 104
9538 #define FW_NAME_57711 "/lib/firmware/bnx2x/bnx2x-e1h-7.2.51.0.fw"
9539 #define FW_NAME_57810 "/lib/firmware/bnx2x/bnx2x-e2-7.2.51.0.fw"
9541 void bnx2x_load_firmware(struct bnx2x_softc *sc)
9547 fwname = sc->devinfo.device_id == CHIP_NUM_57711
9548 ? FW_NAME_57711 : FW_NAME_57810;
9549 f = open(fwname, O_RDONLY);
9551 PMD_DRV_LOG(NOTICE, "Can't open firmware file");
9555 if (fstat(f, &st) < 0) {
9556 PMD_DRV_LOG(NOTICE, "Can't stat firmware file");
9561 sc->firmware = rte_zmalloc("bnx2x_fw", st.st_size, RTE_CACHE_LINE_SIZE);
9562 if (!sc->firmware) {
9563 PMD_DRV_LOG(NOTICE, "Can't allocate memory for firmware");
9568 if (read(f, sc->firmware, st.st_size) != st.st_size) {
9569 PMD_DRV_LOG(NOTICE, "Can't read firmware data");
9575 sc->fw_len = st.st_size;
9576 if (sc->fw_len < FW_HEADER_LEN) {
9577 PMD_DRV_LOG(NOTICE, "Invalid fw size: %" PRIu64, sc->fw_len);
9580 PMD_DRV_LOG(DEBUG, "fw_len = %" PRIu64, sc->fw_len);
9584 bnx2x_data_to_init_ops(uint8_t * data, struct raw_op *dst, uint32_t len)
9586 uint32_t *src = (uint32_t *) data;
9589 for (i = 0, j = 0; i < len / 8; ++i, j += 2) {
9590 tmp = rte_be_to_cpu_32(src[j]);
9591 dst[i].op = (tmp >> 24) & 0xFF;
9592 dst[i].offset = tmp & 0xFFFFFF;
9593 dst[i].raw_data = rte_be_to_cpu_32(src[j + 1]);
9598 bnx2x_data_to_init_offsets(uint8_t * data, uint16_t * dst, uint32_t len)
9600 uint16_t *src = (uint16_t *) data;
9603 for (i = 0; i < len / 2; ++i)
9604 dst[i] = rte_be_to_cpu_16(src[i]);
9607 static void bnx2x_data_to_init_data(uint8_t * data, uint32_t * dst, uint32_t len)
9609 uint32_t *src = (uint32_t *) data;
9612 for (i = 0; i < len / 4; ++i)
9613 dst[i] = rte_be_to_cpu_32(src[i]);
9616 static void bnx2x_data_to_iro_array(uint8_t * data, struct iro *dst, uint32_t len)
9618 uint32_t *src = (uint32_t *) data;
9621 for (i = 0, j = 0; i < len / sizeof(struct iro); ++i, ++j) {
9622 dst[i].base = rte_be_to_cpu_32(src[j++]);
9623 tmp = rte_be_to_cpu_32(src[j]);
9624 dst[i].m1 = (tmp >> 16) & 0xFFFF;
9625 dst[i].m2 = tmp & 0xFFFF;
9627 tmp = rte_be_to_cpu_32(src[j]);
9628 dst[i].m3 = (tmp >> 16) & 0xFFFF;
9629 dst[i].size = tmp & 0xFFFF;
9634 * Device attach function.
9636 * Allocates device resources, performs secondary chip identification, and
9637 * initializes driver instance variables. This function is called from driver
9638 * load after a successful probe.
9641 * 0 = Success, >0 = Failure
9643 int bnx2x_attach(struct bnx2x_softc *sc)
9647 PMD_DRV_LOG(DEBUG, "Starting attach...");
9649 rc = bnx2x_pci_get_caps(sc);
9651 PMD_DRV_LOG(NOTICE, "PCIe caps reading was failed");
9655 sc->state = BNX2X_STATE_CLOSED;
9657 pci_write_long(sc, PCICFG_GRC_ADDRESS, PCICFG_VENDOR_ID_OFFSET);
9659 sc->igu_base_addr = IS_VF(sc) ? PXP_VF_ADDR_IGU_START : BAR_IGU_INTMEM;
9661 /* get PCI capabilites */
9662 bnx2x_probe_pci_caps(sc);
9664 if (sc->devinfo.pcie_msix_cap_reg != 0) {
9667 (sc->devinfo.pcie_msix_cap_reg + PCIR_MSIX_CTRL), &val,
9669 sc->igu_sb_cnt = (val & PCIM_MSIXCTRL_TABLE_SIZE) + 1;
9674 /* Init RTE stuff */
9678 /* get device info and set params */
9679 if (bnx2x_get_device_info(sc) != 0) {
9680 PMD_DRV_LOG(NOTICE, "getting device info");
9684 /* get phy settings from shmem and 'and' against admin settings */
9685 bnx2x_get_phy_info(sc);
9687 /* Left mac of VF unfilled, PF should set it for VF */
9688 memset(sc->link_params.mac_addr, 0, ETHER_ADDR_LEN);
9693 /* set the default MTU (changed via ifconfig) */
9694 sc->mtu = ETHER_MTU;
9696 bnx2x_set_modes_bitmap(sc);
9698 /* need to reset chip if UNDI was active */
9699 if (IS_PF(sc) && !BNX2X_NOMCP(sc)) {
9702 (SHMEM_RD(sc, func_mb[SC_FW_MB_IDX(sc)].drv_mb_header) &
9703 DRV_MSG_SEQ_NUMBER_MASK);
9704 bnx2x_prev_unload(sc);
9707 bnx2x_dcbx_set_state(sc, FALSE, BNX2X_DCBX_ENABLED_OFF);
9709 /* calculate qm_cid_count */
9710 sc->qm_cid_count = bnx2x_set_qm_cid_count(sc);
9713 bnx2x_init_multi_cos(sc);
9719 bnx2x_igu_ack_sb(struct bnx2x_softc *sc, uint8_t igu_sb_id, uint8_t segment,
9720 uint16_t index, uint8_t op, uint8_t update)
9722 uint32_t igu_addr = sc->igu_base_addr;
9723 igu_addr += (IGU_CMD_INT_ACK_BASE + igu_sb_id) * 8;
9724 bnx2x_igu_ack_sb_gen(sc, segment, index, op, update, igu_addr);
9728 bnx2x_ack_sb(struct bnx2x_softc *sc, uint8_t igu_sb_id, uint8_t storm,
9729 uint16_t index, uint8_t op, uint8_t update)
9731 if (unlikely(sc->devinfo.int_block == INT_BLOCK_HC))
9732 bnx2x_hc_ack_sb(sc, igu_sb_id, storm, index, op, update);
9735 if (CHIP_INT_MODE_IS_BC(sc)) {
9737 } else if (igu_sb_id != sc->igu_dsb_id) {
9738 segment = IGU_SEG_ACCESS_DEF;
9739 } else if (storm == ATTENTION_ID) {
9740 segment = IGU_SEG_ACCESS_ATTN;
9742 segment = IGU_SEG_ACCESS_DEF;
9744 bnx2x_igu_ack_sb(sc, igu_sb_id, segment, index, op, update);
9749 bnx2x_igu_clear_sb_gen(struct bnx2x_softc *sc, uint8_t func, uint8_t idu_sb_id,
9752 uint32_t data, ctl, cnt = 100;
9753 uint32_t igu_addr_data = IGU_REG_COMMAND_REG_32LSB_DATA;
9754 uint32_t igu_addr_ctl = IGU_REG_COMMAND_REG_CTRL;
9755 uint32_t igu_addr_ack = IGU_REG_CSTORM_TYPE_0_SB_CLEANUP +
9756 (idu_sb_id / 32) * 4;
9757 uint32_t sb_bit = 1 << (idu_sb_id % 32);
9758 uint32_t func_encode = func |
9759 (is_pf ? 1 : 0) << IGU_FID_ENCODE_IS_PF_SHIFT;
9760 uint32_t addr_encode = IGU_CMD_E2_PROD_UPD_BASE + idu_sb_id;
9762 /* Not supported in BC mode */
9763 if (CHIP_INT_MODE_IS_BC(sc)) {
9767 data = ((IGU_USE_REGISTER_cstorm_type_0_sb_cleanup <<
9768 IGU_REGULAR_CLEANUP_TYPE_SHIFT) |
9769 IGU_REGULAR_CLEANUP_SET | IGU_REGULAR_BCLEANUP);
9771 ctl = ((addr_encode << IGU_CTRL_REG_ADDRESS_SHIFT) |
9772 (func_encode << IGU_CTRL_REG_FID_SHIFT) |
9773 (IGU_CTRL_CMD_TYPE_WR << IGU_CTRL_REG_TYPE_SHIFT));
9775 REG_WR(sc, igu_addr_data, data);
9779 PMD_DRV_LOG(DEBUG, "write 0x%08x to IGU(via GRC) addr 0x%x",
9781 REG_WR(sc, igu_addr_ctl, ctl);
9785 /* wait for clean up to finish */
9786 while (!(REG_RD(sc, igu_addr_ack) & sb_bit) && --cnt) {
9790 if (!(REG_RD(sc, igu_addr_ack) & sb_bit)) {
9792 "Unable to finish IGU cleanup: "
9793 "idu_sb_id %d offset %d bit %d (cnt %d)",
9794 idu_sb_id, idu_sb_id / 32, idu_sb_id % 32, cnt);
9798 static void bnx2x_igu_clear_sb(struct bnx2x_softc *sc, uint8_t idu_sb_id)
9800 bnx2x_igu_clear_sb_gen(sc, SC_FUNC(sc), idu_sb_id, TRUE /*PF*/);
9803 /*******************/
9804 /* ECORE CALLBACKS */
9805 /*******************/
9807 static void bnx2x_reset_common(struct bnx2x_softc *sc)
9809 uint32_t val = 0x1400;
9811 PMD_INIT_FUNC_TRACE();
9814 REG_WR(sc, (GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR),
9817 if (CHIP_IS_E3(sc)) {
9818 val |= MISC_REGISTERS_RESET_REG_2_MSTAT0;
9819 val |= MISC_REGISTERS_RESET_REG_2_MSTAT1;
9822 REG_WR(sc, (GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR), val);
9825 static void bnx2x_common_init_phy(struct bnx2x_softc *sc)
9827 uint32_t shmem_base[2];
9828 uint32_t shmem2_base[2];
9830 /* Avoid common init in case MFW supports LFA */
9831 if (SHMEM2_RD(sc, size) >
9832 (uint32_t) offsetof(struct shmem2_region,
9833 lfa_host_addr[SC_PORT(sc)])) {
9837 shmem_base[0] = sc->devinfo.shmem_base;
9838 shmem2_base[0] = sc->devinfo.shmem2_base;
9840 if (!CHIP_IS_E1x(sc)) {
9841 shmem_base[1] = SHMEM2_RD(sc, other_shmem_base_addr);
9842 shmem2_base[1] = SHMEM2_RD(sc, other_shmem2_base_addr);
9845 elink_common_init_phy(sc, shmem_base, shmem2_base,
9846 sc->devinfo.chip_id, 0);
9849 static void bnx2x_pf_disable(struct bnx2x_softc *sc)
9851 uint32_t val = REG_RD(sc, IGU_REG_PF_CONFIGURATION);
9853 val &= ~IGU_PF_CONF_FUNC_EN;
9855 REG_WR(sc, IGU_REG_PF_CONFIGURATION, val);
9856 REG_WR(sc, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 0);
9857 REG_WR(sc, CFC_REG_WEAK_ENABLE_PF, 0);
9860 static void bnx2x_init_pxp(struct bnx2x_softc *sc)
9863 int r_order, w_order;
9865 devctl = bnx2x_pcie_capability_read(sc, PCIR_EXPRESS_DEVICE_CTL);
9867 w_order = ((devctl & PCIM_EXP_CTL_MAX_PAYLOAD) >> 5);
9868 r_order = ((devctl & PCIM_EXP_CTL_MAX_READ_REQUEST) >> 12);
9870 ecore_init_pxp_arb(sc, r_order, w_order);
9873 static uint32_t bnx2x_get_pretend_reg(struct bnx2x_softc *sc)
9875 uint32_t base = PXP2_REG_PGL_PRETEND_FUNC_F0;
9876 uint32_t stride = (PXP2_REG_PGL_PRETEND_FUNC_F1 - base);
9877 return base + (SC_ABS_FUNC(sc)) * stride;
9881 * Called only on E1H or E2.
9882 * When pretending to be PF, the pretend value is the function number 0..7.
9883 * When pretending to be VF, the pretend val is the PF-num:VF-valid:ABS-VFID
9886 static int bnx2x_pretend_func(struct bnx2x_softc *sc, uint16_t pretend_func_val)
9888 uint32_t pretend_reg;
9890 if (CHIP_IS_E1H(sc) && (pretend_func_val > E1H_FUNC_MAX))
9893 /* get my own pretend register */
9894 pretend_reg = bnx2x_get_pretend_reg(sc);
9895 REG_WR(sc, pretend_reg, pretend_func_val);
9896 REG_RD(sc, pretend_reg);
9900 static void bnx2x_setup_fan_failure_detection(struct bnx2x_softc *sc)
9907 val = (SHMEM_RD(sc, dev_info.shared_hw_config.config2) &
9908 SHARED_HW_CFG_FAN_FAILURE_MASK);
9910 if (val == SHARED_HW_CFG_FAN_FAILURE_ENABLED) {
9914 * The fan failure mechanism is usually related to the PHY type since
9915 * the power consumption of the board is affected by the PHY. Currently,
9916 * fan is required for most designs with SFX7101, BNX2X8727 and BNX2X8481.
9918 else if (val == SHARED_HW_CFG_FAN_FAILURE_PHY_TYPE) {
9919 for (port = PORT_0; port < PORT_MAX; port++) {
9920 is_required |= elink_fan_failure_det_req(sc,
9924 devinfo.shmem2_base,
9929 if (is_required == 0) {
9933 /* Fan failure is indicated by SPIO 5 */
9934 bnx2x_set_spio(sc, MISC_SPIO_SPIO5, MISC_SPIO_INPUT_HI_Z);
9936 /* set to active low mode */
9937 val = REG_RD(sc, MISC_REG_SPIO_INT);
9938 val |= (MISC_SPIO_SPIO5 << MISC_SPIO_INT_OLD_SET_POS);
9939 REG_WR(sc, MISC_REG_SPIO_INT, val);
9941 /* enable interrupt to signal the IGU */
9942 val = REG_RD(sc, MISC_REG_SPIO_EVENT_EN);
9943 val |= MISC_SPIO_SPIO5;
9944 REG_WR(sc, MISC_REG_SPIO_EVENT_EN, val);
9947 static void bnx2x_enable_blocks_attention(struct bnx2x_softc *sc)
9951 REG_WR(sc, PXP_REG_PXP_INT_MASK_0, 0);
9952 if (!CHIP_IS_E1x(sc)) {
9953 REG_WR(sc, PXP_REG_PXP_INT_MASK_1, 0x40);
9955 REG_WR(sc, PXP_REG_PXP_INT_MASK_1, 0);
9957 REG_WR(sc, DORQ_REG_DORQ_INT_MASK, 0);
9958 REG_WR(sc, CFC_REG_CFC_INT_MASK, 0);
9960 * mask read length error interrupts in brb for parser
9961 * (parsing unit and 'checksum and crc' unit)
9962 * these errors are legal (PU reads fixed length and CAC can cause
9963 * read length error on truncated packets)
9965 REG_WR(sc, BRB1_REG_BRB1_INT_MASK, 0xFC00);
9966 REG_WR(sc, QM_REG_QM_INT_MASK, 0);
9967 REG_WR(sc, TM_REG_TM_INT_MASK, 0);
9968 REG_WR(sc, XSDM_REG_XSDM_INT_MASK_0, 0);
9969 REG_WR(sc, XSDM_REG_XSDM_INT_MASK_1, 0);
9970 REG_WR(sc, XCM_REG_XCM_INT_MASK, 0);
9971 /* REG_WR(sc, XSEM_REG_XSEM_INT_MASK_0, 0); */
9972 /* REG_WR(sc, XSEM_REG_XSEM_INT_MASK_1, 0); */
9973 REG_WR(sc, USDM_REG_USDM_INT_MASK_0, 0);
9974 REG_WR(sc, USDM_REG_USDM_INT_MASK_1, 0);
9975 REG_WR(sc, UCM_REG_UCM_INT_MASK, 0);
9976 /* REG_WR(sc, USEM_REG_USEM_INT_MASK_0, 0); */
9977 /* REG_WR(sc, USEM_REG_USEM_INT_MASK_1, 0); */
9978 REG_WR(sc, GRCBASE_UPB + PB_REG_PB_INT_MASK, 0);
9979 REG_WR(sc, CSDM_REG_CSDM_INT_MASK_0, 0);
9980 REG_WR(sc, CSDM_REG_CSDM_INT_MASK_1, 0);
9981 REG_WR(sc, CCM_REG_CCM_INT_MASK, 0);
9982 /* REG_WR(sc, CSEM_REG_CSEM_INT_MASK_0, 0); */
9983 /* REG_WR(sc, CSEM_REG_CSEM_INT_MASK_1, 0); */
9985 val = (PXP2_PXP2_INT_MASK_0_REG_PGL_CPL_AFT |
9986 PXP2_PXP2_INT_MASK_0_REG_PGL_CPL_OF |
9987 PXP2_PXP2_INT_MASK_0_REG_PGL_PCIE_ATTN);
9988 if (!CHIP_IS_E1x(sc)) {
9989 val |= (PXP2_PXP2_INT_MASK_0_REG_PGL_READ_BLOCKED |
9990 PXP2_PXP2_INT_MASK_0_REG_PGL_WRITE_BLOCKED);
9992 REG_WR(sc, PXP2_REG_PXP2_INT_MASK_0, val);
9994 REG_WR(sc, TSDM_REG_TSDM_INT_MASK_0, 0);
9995 REG_WR(sc, TSDM_REG_TSDM_INT_MASK_1, 0);
9996 REG_WR(sc, TCM_REG_TCM_INT_MASK, 0);
9997 /* REG_WR(sc, TSEM_REG_TSEM_INT_MASK_0, 0); */
9999 if (!CHIP_IS_E1x(sc)) {
10000 /* enable VFC attentions: bits 11 and 12, bits 31:13 reserved */
10001 REG_WR(sc, TSEM_REG_TSEM_INT_MASK_1, 0x07ff);
10004 REG_WR(sc, CDU_REG_CDU_INT_MASK, 0);
10005 REG_WR(sc, DMAE_REG_DMAE_INT_MASK, 0);
10006 /* REG_WR(sc, MISC_REG_MISC_INT_MASK, 0); */
10007 REG_WR(sc, PBF_REG_PBF_INT_MASK, 0x18); /* bit 3,4 masked */
10011 * bnx2x_init_hw_common - initialize the HW at the COMMON phase.
10013 * @sc: driver handle
10015 static int bnx2x_init_hw_common(struct bnx2x_softc *sc)
10017 uint8_t abs_func_id;
10020 PMD_DRV_LOG(DEBUG, "starting common init for func %d", SC_ABS_FUNC(sc));
10023 * take the RESET lock to protect undi_unload flow from accessing
10024 * registers while we are resetting the chip
10026 bnx2x_acquire_hw_lock(sc, HW_LOCK_RESOURCE_RESET);
10028 bnx2x_reset_common(sc);
10030 REG_WR(sc, (GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET), 0xffffffff);
10033 if (CHIP_IS_E3(sc)) {
10034 val |= MISC_REGISTERS_RESET_REG_2_MSTAT0;
10035 val |= MISC_REGISTERS_RESET_REG_2_MSTAT1;
10038 REG_WR(sc, (GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET), val);
10040 bnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_RESET);
10042 ecore_init_block(sc, BLOCK_MISC, PHASE_COMMON);
10044 if (!CHIP_IS_E1x(sc)) {
10046 * 4-port mode or 2-port mode we need to turn off master-enable for
10047 * everyone. After that we turn it back on for self. So, we disregard
10048 * multi-function, and always disable all functions on the given path,
10049 * this means 0,2,4,6 for path 0 and 1,3,5,7 for path 1
10051 for (abs_func_id = SC_PATH(sc);
10052 abs_func_id < (E2_FUNC_MAX * 2); abs_func_id += 2) {
10053 if (abs_func_id == SC_ABS_FUNC(sc)) {
10055 PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER,
10060 bnx2x_pretend_func(sc, abs_func_id);
10062 /* clear pf enable */
10063 bnx2x_pf_disable(sc);
10065 bnx2x_pretend_func(sc, SC_ABS_FUNC(sc));
10069 ecore_init_block(sc, BLOCK_PXP, PHASE_COMMON);
10071 ecore_init_block(sc, BLOCK_PXP2, PHASE_COMMON);
10072 bnx2x_init_pxp(sc);
10074 #ifdef __BIG_ENDIAN
10075 REG_WR(sc, PXP2_REG_RQ_QM_ENDIAN_M, 1);
10076 REG_WR(sc, PXP2_REG_RQ_TM_ENDIAN_M, 1);
10077 REG_WR(sc, PXP2_REG_RQ_SRC_ENDIAN_M, 1);
10078 REG_WR(sc, PXP2_REG_RQ_CDU_ENDIAN_M, 1);
10079 REG_WR(sc, PXP2_REG_RQ_DBG_ENDIAN_M, 1);
10080 /* make sure this value is 0 */
10081 REG_WR(sc, PXP2_REG_RQ_HC_ENDIAN_M, 0);
10083 //REG_WR(sc, PXP2_REG_RD_PBF_SWAP_MODE, 1);
10084 REG_WR(sc, PXP2_REG_RD_QM_SWAP_MODE, 1);
10085 REG_WR(sc, PXP2_REG_RD_TM_SWAP_MODE, 1);
10086 REG_WR(sc, PXP2_REG_RD_SRC_SWAP_MODE, 1);
10087 REG_WR(sc, PXP2_REG_RD_CDURD_SWAP_MODE, 1);
10090 ecore_ilt_init_page_size(sc, INITOP_SET);
10092 if (CHIP_REV_IS_FPGA(sc) && CHIP_IS_E1H(sc)) {
10093 REG_WR(sc, PXP2_REG_PGL_TAGS_LIMIT, 0x1);
10096 /* let the HW do it's magic... */
10099 /* finish PXP init */
10101 val = REG_RD(sc, PXP2_REG_RQ_CFG_DONE);
10103 PMD_DRV_LOG(NOTICE, "PXP2 CFG failed");
10106 val = REG_RD(sc, PXP2_REG_RD_INIT_DONE);
10108 PMD_DRV_LOG(NOTICE, "PXP2 RD_INIT failed");
10113 * Timer bug workaround for E2 only. We need to set the entire ILT to have
10114 * entries with value "0" and valid bit on. This needs to be done by the
10115 * first PF that is loaded in a path (i.e. common phase)
10117 if (!CHIP_IS_E1x(sc)) {
10119 * In E2 there is a bug in the timers block that can cause function 6 / 7
10120 * (i.e. vnic3) to start even if it is marked as "scan-off".
10121 * This occurs when a different function (func2,3) is being marked
10122 * as "scan-off". Real-life scenario for example: if a driver is being
10123 * load-unloaded while func6,7 are down. This will cause the timer to access
10124 * the ilt, translate to a logical address and send a request to read/write.
10125 * Since the ilt for the function that is down is not valid, this will cause
10126 * a translation error which is unrecoverable.
10127 * The Workaround is intended to make sure that when this happens nothing
10128 * fatal will occur. The workaround:
10129 * 1. First PF driver which loads on a path will:
10130 * a. After taking the chip out of reset, by using pretend,
10131 * it will write "0" to the following registers of
10133 * REG_WR(pdev, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 0);
10134 * REG_WR(pdev, CFC_REG_WEAK_ENABLE_PF,0);
10135 * REG_WR(pdev, CFC_REG_STRONG_ENABLE_PF,0);
10136 * And for itself it will write '1' to
10137 * PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER to enable
10138 * dmae-operations (writing to pram for example.)
10139 * note: can be done for only function 6,7 but cleaner this
10141 * b. Write zero+valid to the entire ILT.
10142 * c. Init the first_timers_ilt_entry, last_timers_ilt_entry of
10143 * VNIC3 (of that port). The range allocated will be the
10144 * entire ILT. This is needed to prevent ILT range error.
10145 * 2. Any PF driver load flow:
10146 * a. ILT update with the physical addresses of the allocated
10148 * b. Wait 20msec. - note that this timeout is needed to make
10149 * sure there are no requests in one of the PXP internal
10150 * queues with "old" ILT addresses.
10151 * c. PF enable in the PGLC.
10152 * d. Clear the was_error of the PF in the PGLC. (could have
10153 * occurred while driver was down)
10154 * e. PF enable in the CFC (WEAK + STRONG)
10155 * f. Timers scan enable
10156 * 3. PF driver unload flow:
10157 * a. Clear the Timers scan_en.
10158 * b. Polling for scan_on=0 for that PF.
10159 * c. Clear the PF enable bit in the PXP.
10160 * d. Clear the PF enable in the CFC (WEAK + STRONG)
10161 * e. Write zero+valid to all ILT entries (The valid bit must
10163 * f. If this is VNIC 3 of a port then also init
10164 * first_timers_ilt_entry to zero and last_timers_ilt_entry
10165 * to the last enrty in the ILT.
10168 * Currently the PF error in the PGLC is non recoverable.
10169 * In the future the there will be a recovery routine for this error.
10170 * Currently attention is masked.
10171 * Having an MCP lock on the load/unload process does not guarantee that
10172 * there is no Timer disable during Func6/7 enable. This is because the
10173 * Timers scan is currently being cleared by the MCP on FLR.
10174 * Step 2.d can be done only for PF6/7 and the driver can also check if
10175 * there is error before clearing it. But the flow above is simpler and
10177 * All ILT entries are written by zero+valid and not just PF6/7
10178 * ILT entries since in the future the ILT entries allocation for
10179 * PF-s might be dynamic.
10181 struct ilt_client_info ilt_cli;
10182 struct ecore_ilt ilt;
10184 memset(&ilt_cli, 0, sizeof(struct ilt_client_info));
10185 memset(&ilt, 0, sizeof(struct ecore_ilt));
10187 /* initialize dummy TM client */
10189 ilt_cli.end = ILT_NUM_PAGE_ENTRIES - 1;
10190 ilt_cli.client_num = ILT_CLIENT_TM;
10193 * Step 1: set zeroes to all ilt page entries with valid bit on
10194 * Step 2: set the timers first/last ilt entry to point
10195 * to the entire range to prevent ILT range error for 3rd/4th
10196 * vnic (this code assumes existence of the vnic)
10198 * both steps performed by call to ecore_ilt_client_init_op()
10199 * with dummy TM client
10201 * we must use pretend since PXP2_REG_RQ_##blk##_FIRST_ILT
10202 * and his brother are split registers
10205 bnx2x_pretend_func(sc, (SC_PATH(sc) + 6));
10206 ecore_ilt_client_init_op_ilt(sc, &ilt, &ilt_cli, INITOP_CLEAR);
10207 bnx2x_pretend_func(sc, SC_ABS_FUNC(sc));
10209 REG_WR(sc, PXP2_REG_RQ_DRAM_ALIGN, BNX2X_PXP_DRAM_ALIGN);
10210 REG_WR(sc, PXP2_REG_RQ_DRAM_ALIGN_RD, BNX2X_PXP_DRAM_ALIGN);
10211 REG_WR(sc, PXP2_REG_RQ_DRAM_ALIGN_SEL, 1);
10214 REG_WR(sc, PXP2_REG_RQ_DISABLE_INPUTS, 0);
10215 REG_WR(sc, PXP2_REG_RD_DISABLE_INPUTS, 0);
10217 if (!CHIP_IS_E1x(sc)) {
10220 ecore_init_block(sc, BLOCK_PGLUE_B, PHASE_COMMON);
10221 ecore_init_block(sc, BLOCK_ATC, PHASE_COMMON);
10223 /* let the HW do it's magic... */
10226 val = REG_RD(sc, ATC_REG_ATC_INIT_DONE);
10227 } while (factor-- && (val != 1));
10230 PMD_DRV_LOG(NOTICE, "ATC_INIT failed");
10235 ecore_init_block(sc, BLOCK_DMAE, PHASE_COMMON);
10237 /* clean the DMAE memory */
10238 sc->dmae_ready = 1;
10239 ecore_init_fill(sc, TSEM_REG_PRAM, 0, 8);
10241 ecore_init_block(sc, BLOCK_TCM, PHASE_COMMON);
10243 ecore_init_block(sc, BLOCK_UCM, PHASE_COMMON);
10245 ecore_init_block(sc, BLOCK_CCM, PHASE_COMMON);
10247 ecore_init_block(sc, BLOCK_XCM, PHASE_COMMON);
10249 bnx2x_read_dmae(sc, XSEM_REG_PASSIVE_BUFFER, 3);
10250 bnx2x_read_dmae(sc, CSEM_REG_PASSIVE_BUFFER, 3);
10251 bnx2x_read_dmae(sc, TSEM_REG_PASSIVE_BUFFER, 3);
10252 bnx2x_read_dmae(sc, USEM_REG_PASSIVE_BUFFER, 3);
10254 ecore_init_block(sc, BLOCK_QM, PHASE_COMMON);
10256 /* QM queues pointers table */
10257 ecore_qm_init_ptr_table(sc, sc->qm_cid_count, INITOP_SET);
10259 /* soft reset pulse */
10260 REG_WR(sc, QM_REG_SOFT_RESET, 1);
10261 REG_WR(sc, QM_REG_SOFT_RESET, 0);
10263 if (CNIC_SUPPORT(sc))
10264 ecore_init_block(sc, BLOCK_TM, PHASE_COMMON);
10266 ecore_init_block(sc, BLOCK_DORQ, PHASE_COMMON);
10267 REG_WR(sc, DORQ_REG_DPM_CID_OFST, BNX2X_DB_SHIFT);
10269 if (!CHIP_REV_IS_SLOW(sc)) {
10270 /* enable hw interrupt from doorbell Q */
10271 REG_WR(sc, DORQ_REG_DORQ_INT_MASK, 0);
10274 ecore_init_block(sc, BLOCK_BRB1, PHASE_COMMON);
10276 ecore_init_block(sc, BLOCK_PRS, PHASE_COMMON);
10277 REG_WR(sc, PRS_REG_A_PRSU_20, 0xf);
10278 REG_WR(sc, PRS_REG_E1HOV_MODE, sc->devinfo.mf_info.path_has_ovlan);
10280 if (!CHIP_IS_E1x(sc) && !CHIP_IS_E3B0(sc)) {
10281 if (IS_MF_AFEX(sc)) {
10283 * configure that AFEX and VLAN headers must be
10284 * received in AFEX mode
10286 REG_WR(sc, PRS_REG_HDRS_AFTER_BASIC, 0xE);
10287 REG_WR(sc, PRS_REG_MUST_HAVE_HDRS, 0xA);
10288 REG_WR(sc, PRS_REG_HDRS_AFTER_TAG_0, 0x6);
10289 REG_WR(sc, PRS_REG_TAG_ETHERTYPE_0, 0x8926);
10290 REG_WR(sc, PRS_REG_TAG_LEN_0, 0x4);
10293 * Bit-map indicating which L2 hdrs may appear
10294 * after the basic Ethernet header
10296 REG_WR(sc, PRS_REG_HDRS_AFTER_BASIC,
10297 sc->devinfo.mf_info.path_has_ovlan ? 7 : 6);
10301 ecore_init_block(sc, BLOCK_TSDM, PHASE_COMMON);
10302 ecore_init_block(sc, BLOCK_CSDM, PHASE_COMMON);
10303 ecore_init_block(sc, BLOCK_USDM, PHASE_COMMON);
10304 ecore_init_block(sc, BLOCK_XSDM, PHASE_COMMON);
10306 if (!CHIP_IS_E1x(sc)) {
10307 /* reset VFC memories */
10308 REG_WR(sc, TSEM_REG_FAST_MEMORY + VFC_REG_MEMORIES_RST,
10309 VFC_MEMORIES_RST_REG_CAM_RST |
10310 VFC_MEMORIES_RST_REG_RAM_RST);
10311 REG_WR(sc, XSEM_REG_FAST_MEMORY + VFC_REG_MEMORIES_RST,
10312 VFC_MEMORIES_RST_REG_CAM_RST |
10313 VFC_MEMORIES_RST_REG_RAM_RST);
10318 ecore_init_block(sc, BLOCK_TSEM, PHASE_COMMON);
10319 ecore_init_block(sc, BLOCK_USEM, PHASE_COMMON);
10320 ecore_init_block(sc, BLOCK_CSEM, PHASE_COMMON);
10321 ecore_init_block(sc, BLOCK_XSEM, PHASE_COMMON);
10323 /* sync semi rtc */
10324 REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR, 0x80000000);
10325 REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, 0x80000000);
10327 ecore_init_block(sc, BLOCK_UPB, PHASE_COMMON);
10328 ecore_init_block(sc, BLOCK_XPB, PHASE_COMMON);
10329 ecore_init_block(sc, BLOCK_PBF, PHASE_COMMON);
10331 if (!CHIP_IS_E1x(sc)) {
10332 if (IS_MF_AFEX(sc)) {
10334 * configure that AFEX and VLAN headers must be
10335 * sent in AFEX mode
10337 REG_WR(sc, PBF_REG_HDRS_AFTER_BASIC, 0xE);
10338 REG_WR(sc, PBF_REG_MUST_HAVE_HDRS, 0xA);
10339 REG_WR(sc, PBF_REG_HDRS_AFTER_TAG_0, 0x6);
10340 REG_WR(sc, PBF_REG_TAG_ETHERTYPE_0, 0x8926);
10341 REG_WR(sc, PBF_REG_TAG_LEN_0, 0x4);
10343 REG_WR(sc, PBF_REG_HDRS_AFTER_BASIC,
10344 sc->devinfo.mf_info.path_has_ovlan ? 7 : 6);
10348 REG_WR(sc, SRC_REG_SOFT_RST, 1);
10350 ecore_init_block(sc, BLOCK_SRC, PHASE_COMMON);
10352 if (CNIC_SUPPORT(sc)) {
10353 REG_WR(sc, SRC_REG_KEYSEARCH_0, 0x63285672);
10354 REG_WR(sc, SRC_REG_KEYSEARCH_1, 0x24b8f2cc);
10355 REG_WR(sc, SRC_REG_KEYSEARCH_2, 0x223aef9b);
10356 REG_WR(sc, SRC_REG_KEYSEARCH_3, 0x26001e3a);
10357 REG_WR(sc, SRC_REG_KEYSEARCH_4, 0x7ae91116);
10358 REG_WR(sc, SRC_REG_KEYSEARCH_5, 0x5ce5230b);
10359 REG_WR(sc, SRC_REG_KEYSEARCH_6, 0x298d8adf);
10360 REG_WR(sc, SRC_REG_KEYSEARCH_7, 0x6eb0ff09);
10361 REG_WR(sc, SRC_REG_KEYSEARCH_8, 0x1830f82f);
10362 REG_WR(sc, SRC_REG_KEYSEARCH_9, 0x01e46be7);
10364 REG_WR(sc, SRC_REG_SOFT_RST, 0);
10366 if (sizeof(union cdu_context) != 1024) {
10367 /* we currently assume that a context is 1024 bytes */
10368 PMD_DRV_LOG(NOTICE,
10369 "please adjust the size of cdu_context(%ld)",
10370 (long)sizeof(union cdu_context));
10373 ecore_init_block(sc, BLOCK_CDU, PHASE_COMMON);
10374 val = (4 << 24) + (0 << 12) + 1024;
10375 REG_WR(sc, CDU_REG_CDU_GLOBAL_PARAMS, val);
10377 ecore_init_block(sc, BLOCK_CFC, PHASE_COMMON);
10379 REG_WR(sc, CFC_REG_INIT_REG, 0x7FF);
10380 /* enable context validation interrupt from CFC */
10381 REG_WR(sc, CFC_REG_CFC_INT_MASK, 0);
10383 /* set the thresholds to prevent CFC/CDU race */
10384 REG_WR(sc, CFC_REG_DEBUG0, 0x20020000);
10385 ecore_init_block(sc, BLOCK_HC, PHASE_COMMON);
10387 if (!CHIP_IS_E1x(sc) && BNX2X_NOMCP(sc)) {
10388 REG_WR(sc, IGU_REG_RESET_MEMORIES, 0x36);
10391 ecore_init_block(sc, BLOCK_IGU, PHASE_COMMON);
10392 ecore_init_block(sc, BLOCK_MISC_AEU, PHASE_COMMON);
10394 /* Reset PCIE errors for debug */
10395 REG_WR(sc, 0x2814, 0xffffffff);
10396 REG_WR(sc, 0x3820, 0xffffffff);
10398 if (!CHIP_IS_E1x(sc)) {
10399 REG_WR(sc, PCICFG_OFFSET + PXPCS_TL_CONTROL_5,
10400 (PXPCS_TL_CONTROL_5_ERR_UNSPPORT1 |
10401 PXPCS_TL_CONTROL_5_ERR_UNSPPORT));
10402 REG_WR(sc, PCICFG_OFFSET + PXPCS_TL_FUNC345_STAT,
10403 (PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT4 |
10404 PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT3 |
10405 PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT2));
10406 REG_WR(sc, PCICFG_OFFSET + PXPCS_TL_FUNC678_STAT,
10407 (PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT7 |
10408 PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT6 |
10409 PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT5));
10412 ecore_init_block(sc, BLOCK_NIG, PHASE_COMMON);
10414 /* in E3 this done in per-port section */
10415 if (!CHIP_IS_E3(sc))
10416 REG_WR(sc, NIG_REG_LLH_MF_MODE, IS_MF(sc));
10418 if (CHIP_IS_E1H(sc)) {
10419 /* not applicable for E2 (and above ...) */
10420 REG_WR(sc, NIG_REG_LLH_E1HOV_MODE, IS_MF_SD(sc));
10423 if (CHIP_REV_IS_SLOW(sc)) {
10427 /* finish CFC init */
10428 val = reg_poll(sc, CFC_REG_LL_INIT_DONE, 1, 100, 10);
10430 PMD_DRV_LOG(NOTICE, "CFC LL_INIT failed");
10433 val = reg_poll(sc, CFC_REG_AC_INIT_DONE, 1, 100, 10);
10435 PMD_DRV_LOG(NOTICE, "CFC AC_INIT failed");
10438 val = reg_poll(sc, CFC_REG_CAM_INIT_DONE, 1, 100, 10);
10440 PMD_DRV_LOG(NOTICE, "CFC CAM_INIT failed");
10443 REG_WR(sc, CFC_REG_DEBUG0, 0);
10445 bnx2x_setup_fan_failure_detection(sc);
10447 /* clear PXP2 attentions */
10448 REG_RD(sc, PXP2_REG_PXP2_INT_STS_CLR_0);
10450 bnx2x_enable_blocks_attention(sc);
10452 if (!CHIP_REV_IS_SLOW(sc)) {
10453 ecore_enable_blocks_parity(sc);
10456 if (!BNX2X_NOMCP(sc)) {
10457 if (CHIP_IS_E1x(sc)) {
10458 bnx2x_common_init_phy(sc);
10466 * bnx2x_init_hw_common_chip - init HW at the COMMON_CHIP phase.
10468 * @sc: driver handle
10470 static int bnx2x_init_hw_common_chip(struct bnx2x_softc *sc)
10472 int rc = bnx2x_init_hw_common(sc);
10478 /* In E2 2-PORT mode, same ext phy is used for the two paths */
10479 if (!BNX2X_NOMCP(sc)) {
10480 bnx2x_common_init_phy(sc);
10486 static int bnx2x_init_hw_port(struct bnx2x_softc *sc)
10488 int port = SC_PORT(sc);
10489 int init_phase = port ? PHASE_PORT1 : PHASE_PORT0;
10490 uint32_t low, high;
10493 PMD_DRV_LOG(DEBUG, "starting port init for port %d", port);
10495 REG_WR(sc, NIG_REG_MASK_INTERRUPT_PORT0 + port * 4, 0);
10497 ecore_init_block(sc, BLOCK_MISC, init_phase);
10498 ecore_init_block(sc, BLOCK_PXP, init_phase);
10499 ecore_init_block(sc, BLOCK_PXP2, init_phase);
10502 * Timers bug workaround: disables the pf_master bit in pglue at
10503 * common phase, we need to enable it here before any dmae access are
10504 * attempted. Therefore we manually added the enable-master to the
10505 * port phase (it also happens in the function phase)
10507 if (!CHIP_IS_E1x(sc)) {
10508 REG_WR(sc, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 1);
10511 ecore_init_block(sc, BLOCK_ATC, init_phase);
10512 ecore_init_block(sc, BLOCK_DMAE, init_phase);
10513 ecore_init_block(sc, BLOCK_PGLUE_B, init_phase);
10514 ecore_init_block(sc, BLOCK_QM, init_phase);
10516 ecore_init_block(sc, BLOCK_TCM, init_phase);
10517 ecore_init_block(sc, BLOCK_UCM, init_phase);
10518 ecore_init_block(sc, BLOCK_CCM, init_phase);
10519 ecore_init_block(sc, BLOCK_XCM, init_phase);
10521 /* QM cid (connection) count */
10522 ecore_qm_init_cid_count(sc, sc->qm_cid_count, INITOP_SET);
10524 if (CNIC_SUPPORT(sc)) {
10525 ecore_init_block(sc, BLOCK_TM, init_phase);
10526 REG_WR(sc, TM_REG_LIN0_SCAN_TIME + port * 4, 20);
10527 REG_WR(sc, TM_REG_LIN0_MAX_ACTIVE_CID + port * 4, 31);
10530 ecore_init_block(sc, BLOCK_DORQ, init_phase);
10532 ecore_init_block(sc, BLOCK_BRB1, init_phase);
10534 if (CHIP_IS_E1H(sc)) {
10536 low = (BNX2X_ONE_PORT(sc) ? 160 : 246);
10537 } else if (sc->mtu > 4096) {
10538 if (BNX2X_ONE_PORT(sc)) {
10542 /* (24*1024 + val*4)/256 */
10543 low = (96 + (val / 64) + ((val % 64) ? 1 : 0));
10546 low = (BNX2X_ONE_PORT(sc) ? 80 : 160);
10548 high = (low + 56); /* 14*1024/256 */
10549 REG_WR(sc, BRB1_REG_PAUSE_LOW_THRESHOLD_0 + port * 4, low);
10550 REG_WR(sc, BRB1_REG_PAUSE_HIGH_THRESHOLD_0 + port * 4, high);
10553 if (CHIP_IS_MODE_4_PORT(sc)) {
10554 REG_WR(sc, SC_PORT(sc) ?
10555 BRB1_REG_MAC_GUARANTIED_1 :
10556 BRB1_REG_MAC_GUARANTIED_0, 40);
10559 ecore_init_block(sc, BLOCK_PRS, init_phase);
10560 if (CHIP_IS_E3B0(sc)) {
10561 if (IS_MF_AFEX(sc)) {
10562 /* configure headers for AFEX mode */
10564 REG_WR(sc, PRS_REG_HDRS_AFTER_BASIC_PORT_1,
10566 REG_WR(sc, PRS_REG_HDRS_AFTER_TAG_0_PORT_1,
10568 REG_WR(sc, PRS_REG_MUST_HAVE_HDRS_PORT_1, 0xA);
10570 REG_WR(sc, PRS_REG_HDRS_AFTER_BASIC_PORT_0,
10572 REG_WR(sc, PRS_REG_HDRS_AFTER_TAG_0_PORT_0,
10574 REG_WR(sc, PRS_REG_MUST_HAVE_HDRS_PORT_0, 0xA);
10577 /* Ovlan exists only if we are in multi-function +
10578 * switch-dependent mode, in switch-independent there
10579 * is no ovlan headers
10581 REG_WR(sc, SC_PORT(sc) ?
10582 PRS_REG_HDRS_AFTER_BASIC_PORT_1 :
10583 PRS_REG_HDRS_AFTER_BASIC_PORT_0,
10584 (sc->devinfo.mf_info.path_has_ovlan ? 7 : 6));
10588 ecore_init_block(sc, BLOCK_TSDM, init_phase);
10589 ecore_init_block(sc, BLOCK_CSDM, init_phase);
10590 ecore_init_block(sc, BLOCK_USDM, init_phase);
10591 ecore_init_block(sc, BLOCK_XSDM, init_phase);
10593 ecore_init_block(sc, BLOCK_TSEM, init_phase);
10594 ecore_init_block(sc, BLOCK_USEM, init_phase);
10595 ecore_init_block(sc, BLOCK_CSEM, init_phase);
10596 ecore_init_block(sc, BLOCK_XSEM, init_phase);
10598 ecore_init_block(sc, BLOCK_UPB, init_phase);
10599 ecore_init_block(sc, BLOCK_XPB, init_phase);
10601 ecore_init_block(sc, BLOCK_PBF, init_phase);
10603 if (CHIP_IS_E1x(sc)) {
10604 /* configure PBF to work without PAUSE mtu 9000 */
10605 REG_WR(sc, PBF_REG_P0_PAUSE_ENABLE + port * 4, 0);
10607 /* update threshold */
10608 REG_WR(sc, PBF_REG_P0_ARB_THRSH + port * 4, (9040 / 16));
10609 /* update init credit */
10610 REG_WR(sc, PBF_REG_P0_INIT_CRD + port * 4,
10611 (9040 / 16) + 553 - 22);
10613 /* probe changes */
10614 REG_WR(sc, PBF_REG_INIT_P0 + port * 4, 1);
10616 REG_WR(sc, PBF_REG_INIT_P0 + port * 4, 0);
10619 if (CNIC_SUPPORT(sc)) {
10620 ecore_init_block(sc, BLOCK_SRC, init_phase);
10623 ecore_init_block(sc, BLOCK_CDU, init_phase);
10624 ecore_init_block(sc, BLOCK_CFC, init_phase);
10625 ecore_init_block(sc, BLOCK_HC, init_phase);
10626 ecore_init_block(sc, BLOCK_IGU, init_phase);
10627 ecore_init_block(sc, BLOCK_MISC_AEU, init_phase);
10628 /* init aeu_mask_attn_func_0/1:
10629 * - SF mode: bits 3-7 are masked. only bits 0-2 are in use
10630 * - MF mode: bit 3 is masked. bits 0-2 are in use as in SF
10631 * bits 4-7 are used for "per vn group attention" */
10632 val = IS_MF(sc) ? 0xF7 : 0x7;
10634 REG_WR(sc, MISC_REG_AEU_MASK_ATTN_FUNC_0 + port * 4, val);
10636 ecore_init_block(sc, BLOCK_NIG, init_phase);
10638 if (!CHIP_IS_E1x(sc)) {
10639 /* Bit-map indicating which L2 hdrs may appear after the
10640 * basic Ethernet header
10642 if (IS_MF_AFEX(sc)) {
10643 REG_WR(sc, SC_PORT(sc) ?
10644 NIG_REG_P1_HDRS_AFTER_BASIC :
10645 NIG_REG_P0_HDRS_AFTER_BASIC, 0xE);
10647 REG_WR(sc, SC_PORT(sc) ?
10648 NIG_REG_P1_HDRS_AFTER_BASIC :
10649 NIG_REG_P0_HDRS_AFTER_BASIC,
10650 IS_MF_SD(sc) ? 7 : 6);
10653 if (CHIP_IS_E3(sc)) {
10654 REG_WR(sc, SC_PORT(sc) ?
10655 NIG_REG_LLH1_MF_MODE :
10656 NIG_REG_LLH_MF_MODE, IS_MF(sc));
10659 if (!CHIP_IS_E3(sc)) {
10660 REG_WR(sc, NIG_REG_XGXS_SERDES0_MODE_SEL + port * 4, 1);
10663 /* 0x2 disable mf_ov, 0x1 enable */
10664 REG_WR(sc, NIG_REG_LLH0_BRB1_DRV_MASK_MF + port * 4,
10665 (IS_MF_SD(sc) ? 0x1 : 0x2));
10667 if (!CHIP_IS_E1x(sc)) {
10669 switch (sc->devinfo.mf_info.mf_mode) {
10670 case MULTI_FUNCTION_SD:
10673 case MULTI_FUNCTION_SI:
10674 case MULTI_FUNCTION_AFEX:
10679 REG_WR(sc, (SC_PORT(sc) ? NIG_REG_LLH1_CLS_TYPE :
10680 NIG_REG_LLH0_CLS_TYPE), val);
10682 REG_WR(sc, NIG_REG_LLFC_ENABLE_0 + port * 4, 0);
10683 REG_WR(sc, NIG_REG_LLFC_OUT_EN_0 + port * 4, 0);
10684 REG_WR(sc, NIG_REG_PAUSE_ENABLE_0 + port * 4, 1);
10686 /* If SPIO5 is set to generate interrupts, enable it for this port */
10687 val = REG_RD(sc, MISC_REG_SPIO_EVENT_EN);
10688 if (val & MISC_SPIO_SPIO5) {
10689 uint32_t reg_addr = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 :
10690 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0);
10691 val = REG_RD(sc, reg_addr);
10692 val |= AEU_INPUTS_ATTN_BITS_SPIO5;
10693 REG_WR(sc, reg_addr, val);
10700 bnx2x_flr_clnup_reg_poll(struct bnx2x_softc *sc, uint32_t reg,
10701 uint32_t expected, uint32_t poll_count)
10703 uint32_t cur_cnt = poll_count;
10706 while ((val = REG_RD(sc, reg)) != expected && cur_cnt--) {
10707 DELAY(FLR_WAIT_INTERVAL);
10714 bnx2x_flr_clnup_poll_hw_counter(struct bnx2x_softc *sc, uint32_t reg,
10715 __rte_unused const char *msg, uint32_t poll_cnt)
10717 uint32_t val = bnx2x_flr_clnup_reg_poll(sc, reg, 0, poll_cnt);
10720 PMD_DRV_LOG(NOTICE, "%s usage count=%d", msg, val);
10727 /* Common routines with VF FLR cleanup */
10728 static uint32_t bnx2x_flr_clnup_poll_count(struct bnx2x_softc *sc)
10730 /* adjust polling timeout */
10731 if (CHIP_REV_IS_EMUL(sc)) {
10732 return FLR_POLL_CNT * 2000;
10735 if (CHIP_REV_IS_FPGA(sc)) {
10736 return FLR_POLL_CNT * 120;
10739 return FLR_POLL_CNT;
10742 static int bnx2x_poll_hw_usage_counters(struct bnx2x_softc *sc, uint32_t poll_cnt)
10744 /* wait for CFC PF usage-counter to zero (includes all the VFs) */
10745 if (bnx2x_flr_clnup_poll_hw_counter(sc,
10746 CFC_REG_NUM_LCIDS_INSIDE_PF,
10747 "CFC PF usage counter timed out",
10752 /* Wait for DQ PF usage-counter to zero (until DQ cleanup) */
10753 if (bnx2x_flr_clnup_poll_hw_counter(sc,
10754 DORQ_REG_PF_USAGE_CNT,
10755 "DQ PF usage counter timed out",
10760 /* Wait for QM PF usage-counter to zero (until DQ cleanup) */
10761 if (bnx2x_flr_clnup_poll_hw_counter(sc,
10762 QM_REG_PF_USG_CNT_0 + 4 * SC_FUNC(sc),
10763 "QM PF usage counter timed out",
10768 /* Wait for Timer PF usage-counters to zero (until DQ cleanup) */
10769 if (bnx2x_flr_clnup_poll_hw_counter(sc,
10770 TM_REG_LIN0_VNIC_UC + 4 * SC_PORT(sc),
10771 "Timers VNIC usage counter timed out",
10776 if (bnx2x_flr_clnup_poll_hw_counter(sc,
10777 TM_REG_LIN0_NUM_SCANS +
10779 "Timers NUM_SCANS usage counter timed out",
10784 /* Wait DMAE PF usage counter to zero */
10785 if (bnx2x_flr_clnup_poll_hw_counter(sc,
10786 dmae_reg_go_c[INIT_DMAE_C(sc)],
10787 "DMAE dommand register timed out",
10795 #define OP_GEN_PARAM(param) \
10796 (((param) << SDM_OP_GEN_COMP_PARAM_SHIFT) & SDM_OP_GEN_COMP_PARAM)
10797 #define OP_GEN_TYPE(type) \
10798 (((type) << SDM_OP_GEN_COMP_TYPE_SHIFT) & SDM_OP_GEN_COMP_TYPE)
10799 #define OP_GEN_AGG_VECT(index) \
10800 (((index) << SDM_OP_GEN_AGG_VECT_IDX_SHIFT) & SDM_OP_GEN_AGG_VECT_IDX)
10803 bnx2x_send_final_clnup(struct bnx2x_softc *sc, uint8_t clnup_func,
10806 uint32_t op_gen_command = 0;
10807 uint32_t comp_addr = (BAR_CSTRORM_INTMEM +
10808 CSTORM_FINAL_CLEANUP_COMPLETE_OFFSET(clnup_func));
10811 if (REG_RD(sc, comp_addr)) {
10812 PMD_DRV_LOG(NOTICE,
10813 "Cleanup complete was not 0 before sending");
10817 op_gen_command |= OP_GEN_PARAM(XSTORM_AGG_INT_FINAL_CLEANUP_INDEX);
10818 op_gen_command |= OP_GEN_TYPE(XSTORM_AGG_INT_FINAL_CLEANUP_COMP_TYPE);
10819 op_gen_command |= OP_GEN_AGG_VECT(clnup_func);
10820 op_gen_command |= 1 << SDM_OP_GEN_AGG_VECT_IDX_VALID_SHIFT;
10822 REG_WR(sc, XSDM_REG_OPERATION_GEN, op_gen_command);
10824 if (bnx2x_flr_clnup_reg_poll(sc, comp_addr, 1, poll_cnt) != 1) {
10825 PMD_DRV_LOG(NOTICE, "FW final cleanup did not succeed");
10826 PMD_DRV_LOG(DEBUG, "At timeout completion address contained %x",
10827 (REG_RD(sc, comp_addr)));
10828 rte_panic("FLR cleanup failed");
10832 /* Zero completion for nxt FLR */
10833 REG_WR(sc, comp_addr, 0);
10839 bnx2x_pbf_pN_buf_flushed(struct bnx2x_softc *sc, struct pbf_pN_buf_regs *regs,
10840 uint32_t poll_count)
10842 uint32_t init_crd, crd, crd_start, crd_freed, crd_freed_start;
10843 uint32_t cur_cnt = poll_count;
10845 crd_freed = crd_freed_start = REG_RD(sc, regs->crd_freed);
10846 crd = crd_start = REG_RD(sc, regs->crd);
10847 init_crd = REG_RD(sc, regs->init_crd);
10849 while ((crd != init_crd) &&
10850 ((uint32_t) ((int32_t) crd_freed - (int32_t) crd_freed_start) <
10851 (init_crd - crd_start))) {
10853 DELAY(FLR_WAIT_INTERVAL);
10854 crd = REG_RD(sc, regs->crd);
10855 crd_freed = REG_RD(sc, regs->crd_freed);
10863 bnx2x_pbf_pN_cmd_flushed(struct bnx2x_softc *sc, struct pbf_pN_cmd_regs *regs,
10864 uint32_t poll_count)
10866 uint32_t occup, to_free, freed, freed_start;
10867 uint32_t cur_cnt = poll_count;
10869 occup = to_free = REG_RD(sc, regs->lines_occup);
10870 freed = freed_start = REG_RD(sc, regs->lines_freed);
10873 ((uint32_t) ((int32_t) freed - (int32_t) freed_start) <
10876 DELAY(FLR_WAIT_INTERVAL);
10877 occup = REG_RD(sc, regs->lines_occup);
10878 freed = REG_RD(sc, regs->lines_freed);
10885 static void bnx2x_tx_hw_flushed(struct bnx2x_softc *sc, uint32_t poll_count)
10887 struct pbf_pN_cmd_regs cmd_regs[] = {
10888 {0, (CHIP_IS_E3B0(sc)) ?
10889 PBF_REG_TQ_OCCUPANCY_Q0 : PBF_REG_P0_TQ_OCCUPANCY,
10890 (CHIP_IS_E3B0(sc)) ?
10891 PBF_REG_TQ_LINES_FREED_CNT_Q0 : PBF_REG_P0_TQ_LINES_FREED_CNT},
10892 {1, (CHIP_IS_E3B0(sc)) ?
10893 PBF_REG_TQ_OCCUPANCY_Q1 : PBF_REG_P1_TQ_OCCUPANCY,
10894 (CHIP_IS_E3B0(sc)) ?
10895 PBF_REG_TQ_LINES_FREED_CNT_Q1 : PBF_REG_P1_TQ_LINES_FREED_CNT},
10896 {4, (CHIP_IS_E3B0(sc)) ?
10897 PBF_REG_TQ_OCCUPANCY_LB_Q : PBF_REG_P4_TQ_OCCUPANCY,
10898 (CHIP_IS_E3B0(sc)) ?
10899 PBF_REG_TQ_LINES_FREED_CNT_LB_Q :
10900 PBF_REG_P4_TQ_LINES_FREED_CNT}
10903 struct pbf_pN_buf_regs buf_regs[] = {
10904 {0, (CHIP_IS_E3B0(sc)) ?
10905 PBF_REG_INIT_CRD_Q0 : PBF_REG_P0_INIT_CRD,
10906 (CHIP_IS_E3B0(sc)) ? PBF_REG_CREDIT_Q0 : PBF_REG_P0_CREDIT,
10907 (CHIP_IS_E3B0(sc)) ?
10908 PBF_REG_INTERNAL_CRD_FREED_CNT_Q0 :
10909 PBF_REG_P0_INTERNAL_CRD_FREED_CNT},
10910 {1, (CHIP_IS_E3B0(sc)) ?
10911 PBF_REG_INIT_CRD_Q1 : PBF_REG_P1_INIT_CRD,
10912 (CHIP_IS_E3B0(sc)) ? PBF_REG_CREDIT_Q1 : PBF_REG_P1_CREDIT,
10913 (CHIP_IS_E3B0(sc)) ?
10914 PBF_REG_INTERNAL_CRD_FREED_CNT_Q1 :
10915 PBF_REG_P1_INTERNAL_CRD_FREED_CNT},
10916 {4, (CHIP_IS_E3B0(sc)) ?
10917 PBF_REG_INIT_CRD_LB_Q : PBF_REG_P4_INIT_CRD,
10918 (CHIP_IS_E3B0(sc)) ? PBF_REG_CREDIT_LB_Q : PBF_REG_P4_CREDIT,
10919 (CHIP_IS_E3B0(sc)) ?
10920 PBF_REG_INTERNAL_CRD_FREED_CNT_LB_Q :
10921 PBF_REG_P4_INTERNAL_CRD_FREED_CNT},
10926 /* Verify the command queues are flushed P0, P1, P4 */
10927 for (i = 0; i < ARRAY_SIZE(cmd_regs); i++) {
10928 bnx2x_pbf_pN_cmd_flushed(sc, &cmd_regs[i], poll_count);
10931 /* Verify the transmission buffers are flushed P0, P1, P4 */
10932 for (i = 0; i < ARRAY_SIZE(buf_regs); i++) {
10933 bnx2x_pbf_pN_buf_flushed(sc, &buf_regs[i], poll_count);
10937 static void bnx2x_hw_enable_status(struct bnx2x_softc *sc)
10939 __rte_unused uint32_t val;
10941 val = REG_RD(sc, CFC_REG_WEAK_ENABLE_PF);
10942 PMD_DRV_LOG(DEBUG, "CFC_REG_WEAK_ENABLE_PF is 0x%x", val);
10944 val = REG_RD(sc, PBF_REG_DISABLE_PF);
10945 PMD_DRV_LOG(DEBUG, "PBF_REG_DISABLE_PF is 0x%x", val);
10947 val = REG_RD(sc, IGU_REG_PCI_PF_MSI_EN);
10948 PMD_DRV_LOG(DEBUG, "IGU_REG_PCI_PF_MSI_EN is 0x%x", val);
10950 val = REG_RD(sc, IGU_REG_PCI_PF_MSIX_EN);
10951 PMD_DRV_LOG(DEBUG, "IGU_REG_PCI_PF_MSIX_EN is 0x%x", val);
10953 val = REG_RD(sc, IGU_REG_PCI_PF_MSIX_FUNC_MASK);
10954 PMD_DRV_LOG(DEBUG, "IGU_REG_PCI_PF_MSIX_FUNC_MASK is 0x%x", val);
10956 val = REG_RD(sc, PGLUE_B_REG_SHADOW_BME_PF_7_0_CLR);
10957 PMD_DRV_LOG(DEBUG, "PGLUE_B_REG_SHADOW_BME_PF_7_0_CLR is 0x%x", val);
10959 val = REG_RD(sc, PGLUE_B_REG_FLR_REQUEST_PF_7_0_CLR);
10960 PMD_DRV_LOG(DEBUG, "PGLUE_B_REG_FLR_REQUEST_PF_7_0_CLR is 0x%x", val);
10962 val = REG_RD(sc, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER);
10963 PMD_DRV_LOG(DEBUG, "PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER is 0x%x",
10968 * bnx2x_pf_flr_clnup
10969 * a. re-enable target read on the PF
10970 * b. poll cfc per function usgae counter
10971 * c. poll the qm perfunction usage counter
10972 * d. poll the tm per function usage counter
10973 * e. poll the tm per function scan-done indication
10974 * f. clear the dmae channel associated wit hthe PF
10975 * g. zero the igu 'trailing edge' and 'leading edge' regs (attentions)
10976 * h. call the common flr cleanup code with -1 (pf indication)
10978 static int bnx2x_pf_flr_clnup(struct bnx2x_softc *sc)
10980 uint32_t poll_cnt = bnx2x_flr_clnup_poll_count(sc);
10982 /* Re-enable PF target read access */
10983 REG_WR(sc, PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_READ, 1);
10985 /* Poll HW usage counters */
10986 if (bnx2x_poll_hw_usage_counters(sc, poll_cnt)) {
10990 /* Zero the igu 'trailing edge' and 'leading edge' */
10992 /* Send the FW cleanup command */
10993 if (bnx2x_send_final_clnup(sc, (uint8_t) SC_FUNC(sc), poll_cnt)) {
10999 /* Verify TX hw is flushed */
11000 bnx2x_tx_hw_flushed(sc, poll_cnt);
11002 /* Wait 100ms (not adjusted according to platform) */
11005 /* Verify no pending pci transactions */
11006 if (bnx2x_is_pcie_pending(sc)) {
11007 PMD_DRV_LOG(NOTICE, "PCIE Transactions still pending");
11011 bnx2x_hw_enable_status(sc);
11014 * Master enable - Due to WB DMAE writes performed before this
11015 * register is re-initialized as part of the regular function init
11017 REG_WR(sc, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 1);
11022 static int bnx2x_init_hw_func(struct bnx2x_softc *sc)
11024 int port = SC_PORT(sc);
11025 int func = SC_FUNC(sc);
11026 int init_phase = PHASE_PF0 + func;
11027 struct ecore_ilt *ilt = sc->ilt;
11028 uint16_t cdu_ilt_start;
11029 uint32_t addr, val;
11030 uint32_t main_mem_base, main_mem_size, main_mem_prty_clr;
11031 int main_mem_width, rc;
11034 PMD_DRV_LOG(DEBUG, "starting func init for func %d", func);
11037 if (!CHIP_IS_E1x(sc)) {
11038 rc = bnx2x_pf_flr_clnup(sc);
11040 PMD_DRV_LOG(NOTICE, "FLR cleanup failed!");
11045 /* set MSI reconfigure capability */
11046 if (sc->devinfo.int_block == INT_BLOCK_HC) {
11047 addr = (port ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0);
11048 val = REG_RD(sc, addr);
11049 val |= HC_CONFIG_0_REG_MSI_ATTN_EN_0;
11050 REG_WR(sc, addr, val);
11053 ecore_init_block(sc, BLOCK_PXP, init_phase);
11054 ecore_init_block(sc, BLOCK_PXP2, init_phase);
11057 cdu_ilt_start = ilt->clients[ILT_CLIENT_CDU].start;
11059 for (i = 0; i < L2_ILT_LINES(sc); i++) {
11060 ilt->lines[cdu_ilt_start + i].page = sc->context[i].vcxt;
11061 ilt->lines[cdu_ilt_start + i].page_mapping =
11062 (phys_addr_t)sc->context[i].vcxt_dma.paddr;
11063 ilt->lines[cdu_ilt_start + i].size = sc->context[i].size;
11065 ecore_ilt_init_op(sc, INITOP_SET);
11067 REG_WR(sc, PRS_REG_NIC_MODE, 1);
11069 if (!CHIP_IS_E1x(sc)) {
11070 uint32_t pf_conf = IGU_PF_CONF_FUNC_EN;
11072 /* Turn on a single ISR mode in IGU if driver is going to use
11075 if ((sc->interrupt_mode != INTR_MODE_MSIX)
11076 || (sc->interrupt_mode != INTR_MODE_SINGLE_MSIX)) {
11077 pf_conf |= IGU_PF_CONF_SINGLE_ISR_EN;
11081 * Timers workaround bug: function init part.
11082 * Need to wait 20msec after initializing ILT,
11083 * needed to make sure there are no requests in
11084 * one of the PXP internal queues with "old" ILT addresses
11089 * Master enable - Due to WB DMAE writes performed before this
11090 * register is re-initialized as part of the regular function
11093 REG_WR(sc, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 1);
11094 /* Enable the function in IGU */
11095 REG_WR(sc, IGU_REG_PF_CONFIGURATION, pf_conf);
11098 sc->dmae_ready = 1;
11100 ecore_init_block(sc, BLOCK_PGLUE_B, init_phase);
11102 if (!CHIP_IS_E1x(sc))
11103 REG_WR(sc, PGLUE_B_REG_WAS_ERROR_PF_7_0_CLR, func);
11105 ecore_init_block(sc, BLOCK_ATC, init_phase);
11106 ecore_init_block(sc, BLOCK_DMAE, init_phase);
11107 ecore_init_block(sc, BLOCK_NIG, init_phase);
11108 ecore_init_block(sc, BLOCK_SRC, init_phase);
11109 ecore_init_block(sc, BLOCK_MISC, init_phase);
11110 ecore_init_block(sc, BLOCK_TCM, init_phase);
11111 ecore_init_block(sc, BLOCK_UCM, init_phase);
11112 ecore_init_block(sc, BLOCK_CCM, init_phase);
11113 ecore_init_block(sc, BLOCK_XCM, init_phase);
11114 ecore_init_block(sc, BLOCK_TSEM, init_phase);
11115 ecore_init_block(sc, BLOCK_USEM, init_phase);
11116 ecore_init_block(sc, BLOCK_CSEM, init_phase);
11117 ecore_init_block(sc, BLOCK_XSEM, init_phase);
11119 if (!CHIP_IS_E1x(sc))
11120 REG_WR(sc, QM_REG_PF_EN, 1);
11122 if (!CHIP_IS_E1x(sc)) {
11123 REG_WR(sc, TSEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func);
11124 REG_WR(sc, USEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func);
11125 REG_WR(sc, CSEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func);
11126 REG_WR(sc, XSEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func);
11128 ecore_init_block(sc, BLOCK_QM, init_phase);
11130 ecore_init_block(sc, BLOCK_TM, init_phase);
11131 ecore_init_block(sc, BLOCK_DORQ, init_phase);
11133 ecore_init_block(sc, BLOCK_BRB1, init_phase);
11134 ecore_init_block(sc, BLOCK_PRS, init_phase);
11135 ecore_init_block(sc, BLOCK_TSDM, init_phase);
11136 ecore_init_block(sc, BLOCK_CSDM, init_phase);
11137 ecore_init_block(sc, BLOCK_USDM, init_phase);
11138 ecore_init_block(sc, BLOCK_XSDM, init_phase);
11139 ecore_init_block(sc, BLOCK_UPB, init_phase);
11140 ecore_init_block(sc, BLOCK_XPB, init_phase);
11141 ecore_init_block(sc, BLOCK_PBF, init_phase);
11142 if (!CHIP_IS_E1x(sc))
11143 REG_WR(sc, PBF_REG_DISABLE_PF, 0);
11145 ecore_init_block(sc, BLOCK_CDU, init_phase);
11147 ecore_init_block(sc, BLOCK_CFC, init_phase);
11149 if (!CHIP_IS_E1x(sc))
11150 REG_WR(sc, CFC_REG_WEAK_ENABLE_PF, 1);
11153 REG_WR(sc, NIG_REG_LLH0_FUNC_EN + port * 8, 1);
11154 REG_WR(sc, NIG_REG_LLH0_FUNC_VLAN_ID + port * 8, OVLAN(sc));
11157 ecore_init_block(sc, BLOCK_MISC_AEU, init_phase);
11159 /* HC init per function */
11160 if (sc->devinfo.int_block == INT_BLOCK_HC) {
11161 if (CHIP_IS_E1H(sc)) {
11162 REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_12 + func * 4, 0);
11164 REG_WR(sc, HC_REG_LEADING_EDGE_0 + port * 8, 0);
11165 REG_WR(sc, HC_REG_TRAILING_EDGE_0 + port * 8, 0);
11167 ecore_init_block(sc, BLOCK_HC, init_phase);
11170 uint32_t num_segs, sb_idx, prod_offset;
11172 REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_12 + func * 4, 0);
11174 if (!CHIP_IS_E1x(sc)) {
11175 REG_WR(sc, IGU_REG_LEADING_EDGE_LATCH, 0);
11176 REG_WR(sc, IGU_REG_TRAILING_EDGE_LATCH, 0);
11179 ecore_init_block(sc, BLOCK_IGU, init_phase);
11181 if (!CHIP_IS_E1x(sc)) {
11185 * E2 mode: address 0-135 match to the mapping memory;
11186 * 136 - PF0 default prod; 137 - PF1 default prod;
11187 * 138 - PF2 default prod; 139 - PF3 default prod;
11188 * 140 - PF0 attn prod; 141 - PF1 attn prod;
11189 * 142 - PF2 attn prod; 143 - PF3 attn prod;
11190 * 144-147 reserved.
11192 * E1.5 mode - In backward compatible mode;
11193 * for non default SB; each even line in the memory
11194 * holds the U producer and each odd line hold
11195 * the C producer. The first 128 producers are for
11196 * NDSB (PF0 - 0-31; PF1 - 32-63 and so on). The last 20
11197 * producers are for the DSB for each PF.
11198 * Each PF has five segments: (the order inside each
11199 * segment is PF0; PF1; PF2; PF3) - 128-131 U prods;
11200 * 132-135 C prods; 136-139 X prods; 140-143 T prods;
11201 * 144-147 attn prods;
11203 /* non-default-status-blocks */
11204 num_segs = CHIP_INT_MODE_IS_BC(sc) ?
11205 IGU_BC_NDSB_NUM_SEGS : IGU_NORM_NDSB_NUM_SEGS;
11206 for (sb_idx = 0; sb_idx < sc->igu_sb_cnt; sb_idx++) {
11207 prod_offset = (sc->igu_base_sb + sb_idx) *
11210 for (i = 0; i < num_segs; i++) {
11211 addr = IGU_REG_PROD_CONS_MEMORY +
11212 (prod_offset + i) * 4;
11213 REG_WR(sc, addr, 0);
11215 /* send consumer update with value 0 */
11216 bnx2x_ack_sb(sc, sc->igu_base_sb + sb_idx,
11217 USTORM_ID, 0, IGU_INT_NOP, 1);
11218 bnx2x_igu_clear_sb(sc, sc->igu_base_sb + sb_idx);
11221 /* default-status-blocks */
11222 num_segs = CHIP_INT_MODE_IS_BC(sc) ?
11223 IGU_BC_DSB_NUM_SEGS : IGU_NORM_DSB_NUM_SEGS;
11225 if (CHIP_IS_MODE_4_PORT(sc))
11226 dsb_idx = SC_FUNC(sc);
11228 dsb_idx = SC_VN(sc);
11230 prod_offset = (CHIP_INT_MODE_IS_BC(sc) ?
11231 IGU_BC_BASE_DSB_PROD + dsb_idx :
11232 IGU_NORM_BASE_DSB_PROD + dsb_idx);
11235 * igu prods come in chunks of E1HVN_MAX (4) -
11236 * does not matters what is the current chip mode
11238 for (i = 0; i < (num_segs * E1HVN_MAX); i += E1HVN_MAX) {
11239 addr = IGU_REG_PROD_CONS_MEMORY +
11240 (prod_offset + i) * 4;
11241 REG_WR(sc, addr, 0);
11243 /* send consumer update with 0 */
11244 if (CHIP_INT_MODE_IS_BC(sc)) {
11245 bnx2x_ack_sb(sc, sc->igu_dsb_id,
11246 USTORM_ID, 0, IGU_INT_NOP, 1);
11247 bnx2x_ack_sb(sc, sc->igu_dsb_id,
11248 CSTORM_ID, 0, IGU_INT_NOP, 1);
11249 bnx2x_ack_sb(sc, sc->igu_dsb_id,
11250 XSTORM_ID, 0, IGU_INT_NOP, 1);
11251 bnx2x_ack_sb(sc, sc->igu_dsb_id,
11252 TSTORM_ID, 0, IGU_INT_NOP, 1);
11253 bnx2x_ack_sb(sc, sc->igu_dsb_id,
11254 ATTENTION_ID, 0, IGU_INT_NOP, 1);
11256 bnx2x_ack_sb(sc, sc->igu_dsb_id,
11257 USTORM_ID, 0, IGU_INT_NOP, 1);
11258 bnx2x_ack_sb(sc, sc->igu_dsb_id,
11259 ATTENTION_ID, 0, IGU_INT_NOP, 1);
11261 bnx2x_igu_clear_sb(sc, sc->igu_dsb_id);
11263 /* !!! these should become driver const once
11264 rf-tool supports split-68 const */
11265 REG_WR(sc, IGU_REG_SB_INT_BEFORE_MASK_LSB, 0);
11266 REG_WR(sc, IGU_REG_SB_INT_BEFORE_MASK_MSB, 0);
11267 REG_WR(sc, IGU_REG_SB_MASK_LSB, 0);
11268 REG_WR(sc, IGU_REG_SB_MASK_MSB, 0);
11269 REG_WR(sc, IGU_REG_PBA_STATUS_LSB, 0);
11270 REG_WR(sc, IGU_REG_PBA_STATUS_MSB, 0);
11274 /* Reset PCIE errors for debug */
11275 REG_WR(sc, 0x2114, 0xffffffff);
11276 REG_WR(sc, 0x2120, 0xffffffff);
11278 if (CHIP_IS_E1x(sc)) {
11279 main_mem_size = HC_REG_MAIN_MEMORY_SIZE / 2; /*dwords */
11280 main_mem_base = HC_REG_MAIN_MEMORY +
11281 SC_PORT(sc) * (main_mem_size * 4);
11282 main_mem_prty_clr = HC_REG_HC_PRTY_STS_CLR;
11283 main_mem_width = 8;
11285 val = REG_RD(sc, main_mem_prty_clr);
11288 "Parity errors in HC block during function init (0x%x)!",
11292 /* Clear "false" parity errors in MSI-X table */
11293 for (i = main_mem_base;
11294 i < main_mem_base + main_mem_size * 4;
11295 i += main_mem_width) {
11296 bnx2x_read_dmae(sc, i, main_mem_width / 4);
11297 bnx2x_write_dmae(sc, BNX2X_SP_MAPPING(sc, wb_data),
11298 i, main_mem_width / 4);
11300 /* Clear HC parity attention */
11301 REG_RD(sc, main_mem_prty_clr);
11304 /* Enable STORMs SP logging */
11305 REG_WR8(sc, BAR_USTRORM_INTMEM +
11306 USTORM_RECORD_SLOW_PATH_OFFSET(SC_FUNC(sc)), 1);
11307 REG_WR8(sc, BAR_TSTRORM_INTMEM +
11308 TSTORM_RECORD_SLOW_PATH_OFFSET(SC_FUNC(sc)), 1);
11309 REG_WR8(sc, BAR_CSTRORM_INTMEM +
11310 CSTORM_RECORD_SLOW_PATH_OFFSET(SC_FUNC(sc)), 1);
11311 REG_WR8(sc, BAR_XSTRORM_INTMEM +
11312 XSTORM_RECORD_SLOW_PATH_OFFSET(SC_FUNC(sc)), 1);
11314 elink_phy_probe(&sc->link_params);
11319 static void bnx2x_link_reset(struct bnx2x_softc *sc)
11321 if (!BNX2X_NOMCP(sc)) {
11322 elink_lfa_reset(&sc->link_params, &sc->link_vars);
11324 if (!CHIP_REV_IS_SLOW(sc)) {
11325 PMD_DRV_LOG(WARNING,
11326 "Bootcode is missing - cannot reset link");
11331 static void bnx2x_reset_port(struct bnx2x_softc *sc)
11333 int port = SC_PORT(sc);
11336 /* reset physical Link */
11337 bnx2x_link_reset(sc);
11339 REG_WR(sc, NIG_REG_MASK_INTERRUPT_PORT0 + port * 4, 0);
11341 /* Do not rcv packets to BRB */
11342 REG_WR(sc, NIG_REG_LLH0_BRB1_DRV_MASK + port * 4, 0x0);
11343 /* Do not direct rcv packets that are not for MCP to the BRB */
11344 REG_WR(sc, (port ? NIG_REG_LLH1_BRB1_NOT_MCP :
11345 NIG_REG_LLH0_BRB1_NOT_MCP), 0x0);
11347 /* Configure AEU */
11348 REG_WR(sc, MISC_REG_AEU_MASK_ATTN_FUNC_0 + port * 4, 0);
11352 /* Check for BRB port occupancy */
11353 val = REG_RD(sc, BRB1_REG_PORT_NUM_OCC_BLOCKS_0 + port * 4);
11356 "BRB1 is not empty, %d blocks are occupied", val);
11360 static void bnx2x_ilt_wr(struct bnx2x_softc *sc, uint32_t index, phys_addr_t addr)
11363 uint32_t wb_write[2];
11365 reg = PXP2_REG_RQ_ONCHIP_AT_B0 + index * 8;
11367 wb_write[0] = ONCHIP_ADDR1(addr);
11368 wb_write[1] = ONCHIP_ADDR2(addr);
11369 REG_WR_DMAE(sc, reg, wb_write, 2);
11372 static void bnx2x_clear_func_ilt(struct bnx2x_softc *sc, uint32_t func)
11374 uint32_t i, base = FUNC_ILT_BASE(func);
11375 for (i = base; i < base + ILT_PER_FUNC; i++) {
11376 bnx2x_ilt_wr(sc, i, 0);
11380 static void bnx2x_reset_func(struct bnx2x_softc *sc)
11382 struct bnx2x_fastpath *fp;
11383 int port = SC_PORT(sc);
11384 int func = SC_FUNC(sc);
11387 /* Disable the function in the FW */
11388 REG_WR8(sc, BAR_XSTRORM_INTMEM + XSTORM_FUNC_EN_OFFSET(func), 0);
11389 REG_WR8(sc, BAR_CSTRORM_INTMEM + CSTORM_FUNC_EN_OFFSET(func), 0);
11390 REG_WR8(sc, BAR_TSTRORM_INTMEM + TSTORM_FUNC_EN_OFFSET(func), 0);
11391 REG_WR8(sc, BAR_USTRORM_INTMEM + USTORM_FUNC_EN_OFFSET(func), 0);
11394 FOR_EACH_ETH_QUEUE(sc, i) {
11396 REG_WR8(sc, BAR_CSTRORM_INTMEM +
11397 CSTORM_STATUS_BLOCK_DATA_STATE_OFFSET(fp->fw_sb_id),
11402 REG_WR8(sc, BAR_CSTRORM_INTMEM +
11403 CSTORM_SP_STATUS_BLOCK_DATA_STATE_OFFSET(func), SB_DISABLED);
11405 for (i = 0; i < XSTORM_SPQ_DATA_SIZE / 4; i++) {
11406 REG_WR(sc, BAR_XSTRORM_INTMEM + XSTORM_SPQ_DATA_OFFSET(func),
11410 /* Configure IGU */
11411 if (sc->devinfo.int_block == INT_BLOCK_HC) {
11412 REG_WR(sc, HC_REG_LEADING_EDGE_0 + port * 8, 0);
11413 REG_WR(sc, HC_REG_TRAILING_EDGE_0 + port * 8, 0);
11415 REG_WR(sc, IGU_REG_LEADING_EDGE_LATCH, 0);
11416 REG_WR(sc, IGU_REG_TRAILING_EDGE_LATCH, 0);
11419 if (CNIC_LOADED(sc)) {
11420 /* Disable Timer scan */
11421 REG_WR(sc, TM_REG_EN_LINEAR0_TIMER + port * 4, 0);
11423 * Wait for at least 10ms and up to 2 second for the timers
11426 for (i = 0; i < 200; i++) {
11428 if (!REG_RD(sc, TM_REG_LIN0_SCAN_ON + port * 4))
11434 bnx2x_clear_func_ilt(sc, func);
11437 * Timers workaround bug for E2: if this is vnic-3,
11438 * we need to set the entire ilt range for this timers.
11440 if (!CHIP_IS_E1x(sc) && SC_VN(sc) == 3) {
11441 struct ilt_client_info ilt_cli;
11442 /* use dummy TM client */
11443 memset(&ilt_cli, 0, sizeof(struct ilt_client_info));
11445 ilt_cli.end = ILT_NUM_PAGE_ENTRIES - 1;
11446 ilt_cli.client_num = ILT_CLIENT_TM;
11448 ecore_ilt_boundry_init_op(sc, &ilt_cli, 0);
11451 /* this assumes that reset_port() called before reset_func() */
11452 if (!CHIP_IS_E1x(sc)) {
11453 bnx2x_pf_disable(sc);
11456 sc->dmae_ready = 0;
11459 static void bnx2x_release_firmware(struct bnx2x_softc *sc)
11461 rte_free(sc->init_ops);
11462 rte_free(sc->init_ops_offsets);
11463 rte_free(sc->init_data);
11464 rte_free(sc->iro_array);
11467 static int bnx2x_init_firmware(struct bnx2x_softc *sc)
11470 uint8_t *p = sc->firmware;
11473 for (i = 0; i < 24; ++i)
11474 off[i] = rte_be_to_cpu_32(*((uint32_t *) sc->firmware + i));
11477 sc->init_ops = rte_zmalloc("", len, RTE_CACHE_LINE_SIZE);
11480 bnx2x_data_to_init_ops(p + off[1], sc->init_ops, len);
11483 sc->init_ops_offsets = rte_zmalloc("", len, RTE_CACHE_LINE_SIZE);
11484 if (!sc->init_ops_offsets)
11486 bnx2x_data_to_init_offsets(p + off[3], sc->init_ops_offsets, len);
11489 sc->init_data = rte_zmalloc("", len, RTE_CACHE_LINE_SIZE);
11490 if (!sc->init_data)
11492 bnx2x_data_to_init_data(p + off[5], sc->init_data, len);
11494 sc->tsem_int_table_data = p + off[7];
11495 sc->tsem_pram_data = p + off[9];
11496 sc->usem_int_table_data = p + off[11];
11497 sc->usem_pram_data = p + off[13];
11498 sc->csem_int_table_data = p + off[15];
11499 sc->csem_pram_data = p + off[17];
11500 sc->xsem_int_table_data = p + off[19];
11501 sc->xsem_pram_data = p + off[21];
11504 sc->iro_array = rte_zmalloc("", len, RTE_CACHE_LINE_SIZE);
11505 if (!sc->iro_array)
11507 bnx2x_data_to_iro_array(p + off[23], sc->iro_array, len);
11512 bnx2x_release_firmware(sc);
11516 static int cut_gzip_prefix(const uint8_t * zbuf, int len)
11518 #define MIN_PREFIX_SIZE (10)
11520 int n = MIN_PREFIX_SIZE;
11523 if (!(zbuf[0] == 0x1f && zbuf[1] == 0x8b && zbuf[2] == Z_DEFLATED) ||
11524 len <= MIN_PREFIX_SIZE) {
11528 /* optional extra fields are present */
11529 if (zbuf[3] & 0x4) {
11536 /* file name is present */
11537 if (zbuf[3] & 0x8) {
11538 while ((zbuf[n++] != 0) && (n < len)) ;
11544 static int ecore_gunzip(struct bnx2x_softc *sc, const uint8_t * zbuf, int len)
11547 int data_begin = cut_gzip_prefix(zbuf, len);
11549 PMD_DRV_LOG(DEBUG, "ecore_gunzip %d", len);
11551 if (data_begin <= 0) {
11552 PMD_DRV_LOG(NOTICE, "bad gzip prefix");
11556 memset(&zlib_stream, 0, sizeof(zlib_stream));
11557 zlib_stream.next_in = zbuf + data_begin;
11558 zlib_stream.avail_in = len - data_begin;
11559 zlib_stream.next_out = sc->gz_buf;
11560 zlib_stream.avail_out = FW_BUF_SIZE;
11562 ret = inflateInit2(&zlib_stream, -MAX_WBITS);
11564 PMD_DRV_LOG(NOTICE, "zlib inflateInit2 error");
11568 ret = inflate(&zlib_stream, Z_FINISH);
11569 if ((ret != Z_STREAM_END) && (ret != Z_OK)) {
11570 PMD_DRV_LOG(NOTICE, "zlib inflate error: %d %s", ret,
11574 sc->gz_outlen = zlib_stream.total_out;
11575 if (sc->gz_outlen & 0x3) {
11576 PMD_DRV_LOG(NOTICE, "firmware is not aligned. gz_outlen == %d",
11579 sc->gz_outlen >>= 2;
11581 inflateEnd(&zlib_stream);
11583 if (ret == Z_STREAM_END)
11590 ecore_write_dmae_phys_len(struct bnx2x_softc *sc, phys_addr_t phys_addr,
11591 uint32_t addr, uint32_t len)
11593 bnx2x_write_dmae_phys_len(sc, phys_addr, addr, len);
11597 ecore_storm_memset_struct(struct bnx2x_softc *sc, uint32_t addr, size_t size,
11601 for (i = 0; i < size / 4; i++) {
11602 REG_WR(sc, addr + (i * 4), data[i]);
11606 static const char *get_ext_phy_type(uint32_t ext_phy_type)
11608 uint32_t phy_type_idx = ext_phy_type >> 8;
11609 static const char *types[] =
11610 { "DIRECT", "BNX2X-8071", "BNX2X-8072", "BNX2X-8073",
11611 "BNX2X-8705", "BNX2X-8706", "BNX2X-8726", "BNX2X-8481", "SFX-7101",
11613 "BNX2X-8727-NOC", "BNX2X-84823", "NOT_CONN", "FAILURE"
11616 if (phy_type_idx < 12)
11617 return types[phy_type_idx];
11618 else if (PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN == ext_phy_type)
11624 static const char *get_state(uint32_t state)
11626 uint32_t state_idx = state >> 12;
11627 static const char *states[] = { "CLOSED", "OPENING_WAIT4_LOAD",
11628 "OPENING_WAIT4_PORT", "OPEN", "CLOSING_WAIT4_HALT",
11629 "CLOSING_WAIT4_DELETE", "CLOSING_WAIT4_UNLOAD",
11630 "UNKNOWN", "UNKNOWN", "UNKNOWN", "UNKNOWN", "UNKNOWN",
11631 "UNKNOWN", "DISABLED", "DIAG", "ERROR", "UNDEFINED"
11634 if (state_idx <= 0xF)
11635 return states[state_idx];
11637 return states[0x10];
11640 static const char *get_recovery_state(uint32_t state)
11642 static const char *states[] = { "NONE", "DONE", "INIT",
11643 "WAIT", "FAILED", "NIC_LOADING"
11645 return states[state];
11648 static const char *get_rx_mode(uint32_t mode)
11650 static const char *modes[] = { "NONE", "NORMAL", "ALLMULTI",
11651 "PROMISC", "MAX_MULTICAST", "ERROR"
11655 return modes[mode];
11656 else if (BNX2X_MAX_MULTICAST == mode)
11662 #define BNX2X_INFO_STR_MAX 256
11663 static const char *get_bnx2x_flags(uint32_t flags)
11666 static const char *flag[] = { "ONE_PORT ", "NO_ISCSI ",
11667 "NO_FCOE ", "NO_WOL ", "USING_DAC ", "USING_MSIX ",
11668 "USING_MSI ", "DISABLE_MSI ", "UNKNOWN ", "NO_MCP ",
11669 "SAFC_TX_FLAG ", "MF_FUNC_DIS ", "TX_SWITCHING "
11671 static char flag_str[BNX2X_INFO_STR_MAX];
11672 memset(flag_str, 0, BNX2X_INFO_STR_MAX);
11674 for (i = 0; i < 5; i++)
11675 if (flags & (1 << i)) {
11676 strcat(flag_str, flag[i]);
11680 static char unknown[BNX2X_INFO_STR_MAX];
11681 snprintf(unknown, 32, "Unknown flag mask %x", flags);
11682 strcat(flag_str, unknown);
11688 * Prints useful adapter info.
11690 void bnx2x_print_adapter_info(struct bnx2x_softc *sc)
11693 __rte_unused uint32_t ext_phy_type;
11695 PMD_INIT_FUNC_TRACE();
11696 if (sc->link_vars.phy_flags & PHY_XGXS_FLAG)
11697 ext_phy_type = ELINK_XGXS_EXT_PHY_TYPE(REG_RD(sc,
11702 dev_info.port_hw_config
11703 [0].external_phy_config)));
11705 ext_phy_type = ELINK_SERDES_EXT_PHY_TYPE(REG_RD(sc,
11711 dev_info.port_hw_config
11712 [0].external_phy_config)));
11714 PMD_INIT_LOG(DEBUG, "\n\n===================================\n");
11715 /* Hardware chip info. */
11716 PMD_INIT_LOG(DEBUG, "%12s : %#08x", "ASIC", sc->devinfo.chip_id);
11717 PMD_INIT_LOG(DEBUG, "%12s : %c%d", "Rev", (CHIP_REV(sc) >> 12) + 'A',
11718 (CHIP_METAL(sc) >> 4));
11721 PMD_INIT_LOG(DEBUG, "%12s : %d, ", "Bus PCIe", sc->devinfo.pcie_link_width);
11722 switch (sc->devinfo.pcie_link_speed) {
11724 PMD_INIT_LOG(DEBUG, "%23s", "2.5 Gbps");
11727 PMD_INIT_LOG(DEBUG, "%21s", "5 Gbps");
11730 PMD_INIT_LOG(DEBUG, "%21s", "8 Gbps");
11733 PMD_INIT_LOG(DEBUG, "%33s", "Unknown link speed");
11736 /* Device features. */
11737 PMD_INIT_LOG(DEBUG, "%12s : ", "Flags");
11739 /* Miscellaneous flags. */
11740 if (sc->devinfo.pcie_cap_flags & BNX2X_MSI_CAPABLE_FLAG) {
11741 PMD_INIT_LOG(DEBUG, "%18s", "MSI");
11745 if (sc->devinfo.pcie_cap_flags & BNX2X_MSIX_CAPABLE_FLAG) {
11747 PMD_INIT_LOG(DEBUG, "|");
11748 PMD_INIT_LOG(DEBUG, "%20s", "MSI-X");
11753 PMD_INIT_LOG(DEBUG, "%12s : ", "Queues");
11754 switch (sc->sp->rss_rdata.rss_mode) {
11755 case ETH_RSS_MODE_DISABLED:
11756 PMD_INIT_LOG(DEBUG, "%19s", "None");
11758 case ETH_RSS_MODE_REGULAR:
11759 PMD_INIT_LOG(DEBUG, "%18s : %d", "RSS", sc->num_queues);
11762 PMD_INIT_LOG(DEBUG, "%22s", "Unknown");
11767 /* RTE and Driver versions */
11768 PMD_INIT_LOG(DEBUG, "%12s : %s", "DPDK",
11770 PMD_INIT_LOG(DEBUG, "%12s : %s", "Driver",
11771 bnx2x_pmd_version());
11773 /* Firmware versions and device features. */
11774 PMD_INIT_LOG(DEBUG, "%12s : %d.%d.%d",
11776 BNX2X_5710_FW_MAJOR_VERSION,
11777 BNX2X_5710_FW_MINOR_VERSION,
11778 BNX2X_5710_FW_REVISION_VERSION);
11779 PMD_INIT_LOG(DEBUG, "%12s : %s",
11780 "Bootcode", sc->devinfo.bc_ver_str);
11782 PMD_INIT_LOG(DEBUG, "\n\n===================================\n");
11783 PMD_INIT_LOG(DEBUG, "%12s : %u", "Bnx2x Func", sc->pcie_func);
11784 PMD_INIT_LOG(DEBUG, "%12s : %s", "Bnx2x Flags", get_bnx2x_flags(sc->flags));
11785 PMD_INIT_LOG(DEBUG, "%12s : %s", "DMAE Is",
11786 (sc->dmae_ready ? "Ready" : "Not Ready"));
11787 PMD_INIT_LOG(DEBUG, "%12s : %s", "OVLAN", (OVLAN(sc) ? "YES" : "NO"));
11788 PMD_INIT_LOG(DEBUG, "%12s : %s", "MF", (IS_MF(sc) ? "YES" : "NO"));
11789 PMD_INIT_LOG(DEBUG, "%12s : %u", "MTU", sc->mtu);
11790 PMD_INIT_LOG(DEBUG, "%12s : %s", "PHY Type", get_ext_phy_type(ext_phy_type));
11791 PMD_INIT_LOG(DEBUG, "%12s : %x:%x:%x:%x:%x:%x", "MAC Addr",
11792 sc->link_params.mac_addr[0],
11793 sc->link_params.mac_addr[1],
11794 sc->link_params.mac_addr[2],
11795 sc->link_params.mac_addr[3],
11796 sc->link_params.mac_addr[4],
11797 sc->link_params.mac_addr[5]);
11798 PMD_INIT_LOG(DEBUG, "%12s : %s", "RX Mode", get_rx_mode(sc->rx_mode));
11799 PMD_INIT_LOG(DEBUG, "%12s : %s", "State", get_state(sc->state));
11800 if (sc->recovery_state)
11801 PMD_INIT_LOG(DEBUG, "%12s : %s", "Recovery",
11802 get_recovery_state(sc->recovery_state));
11803 PMD_INIT_LOG(DEBUG, "%12s : CQ = %lx, EQ = %lx", "SPQ Left",
11804 sc->cq_spq_left, sc->eq_spq_left);
11805 PMD_INIT_LOG(DEBUG, "%12s : %x", "Switch", sc->link_params.switch_cfg);
11806 PMD_INIT_LOG(DEBUG, "\n\n===================================\n");