drivers/net/bnx2x/bnx2x.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright (c) 2007-2013 Broadcom Corporation.
   3  *
   4  * Eric Davis        <edavis@broadcom.com>
   5  * David Christensen <davidch@broadcom.com>
   6  * Gary Zambrano     <zambrano@broadcom.com>
   7  *
   8  * Copyright (c) 2013-2015 Brocade Communications Systems, Inc.
   9  * Copyright (c) 2015-2018 Cavium Inc.
  10  * All rights reserved.
  11  * www.cavium.com
  12  */
  13
  14 #define BNX2X_DRIVER_VERSION "1.78.18"
  15
  16 #include "bnx2x.h"
  17 #include "bnx2x_vfpf.h"
  18 #include "ecore_sp.h"
  19 #include "ecore_init.h"
  20 #include "ecore_init_ops.h"
  21
  22 #include "rte_version.h"
  23
  24 #include <sys/types.h>
  25 #include <sys/stat.h>
  26 #include <fcntl.h>
  27 #include <zlib.h>
  28 #include <rte_string_fns.h>
  29
  30 #define BNX2X_PMD_VER_PREFIX "BNX2X PMD"
  31 #define BNX2X_PMD_VERSION_MAJOR 1
  32 #define BNX2X_PMD_VERSION_MINOR 0
  33 #define BNX2X_PMD_VERSION_REVISION 7
  34 #define BNX2X_PMD_VERSION_PATCH 1
  35
  36 static inline const char *
  37 bnx2x_pmd_version(void)
  38 {
  39         static char version[32];
  40
  41         snprintf(version, sizeof(version), "%s %s_%d.%d.%d.%d",
  42                         BNX2X_PMD_VER_PREFIX,
  43                         BNX2X_DRIVER_VERSION,
  44                         BNX2X_PMD_VERSION_MAJOR,
  45                         BNX2X_PMD_VERSION_MINOR,
  46                         BNX2X_PMD_VERSION_REVISION,
  47                         BNX2X_PMD_VERSION_PATCH);
  48
  49         return version;
  50 }
  51
  52 static z_stream zlib_stream;
  53
  54 #define EVL_VLID_MASK 0x0FFF
  55
  56 #define BNX2X_DEF_SB_ATT_IDX 0x0001
  57 #define BNX2X_DEF_SB_IDX     0x0002
  58
  59 /*
  60  * FLR Support - bnx2x_pf_flr_clnup() is called during nic_load in the per
  61  * function HW initialization.
  62  */
  63 #define FLR_WAIT_USEC     10000 /* 10 msecs */
  64 #define FLR_WAIT_INTERVAL 50    /* usecs */
  65 #define FLR_POLL_CNT      (FLR_WAIT_USEC / FLR_WAIT_INTERVAL)   /* 200 */
  66
  67 struct pbf_pN_buf_regs {
  68         int pN;
  69         uint32_t init_crd;
  70         uint32_t crd;
  71         uint32_t crd_freed;
  72 };
  73
  74 struct pbf_pN_cmd_regs {
  75         int pN;
  76         uint32_t lines_occup;
  77         uint32_t lines_freed;
  78 };
  79
  80 /* resources needed for unloading a previously loaded device */
  81
  82 #define BNX2X_PREV_WAIT_NEEDED 1
  83 rte_spinlock_t bnx2x_prev_mtx;
  84 struct bnx2x_prev_list_node {
  85         LIST_ENTRY(bnx2x_prev_list_node) node;
  86         uint8_t bus;
  87         uint8_t slot;
  88         uint8_t path;
  89         uint8_t aer;
  90         uint8_t undi;
  91 };
  92
  93 static LIST_HEAD(, bnx2x_prev_list_node) bnx2x_prev_list
  94         = LIST_HEAD_INITIALIZER(bnx2x_prev_list);
  95
  96 static int load_count[2][3] = { { 0 } };
  97         /* per-path: 0-common, 1-port0, 2-port1 */
  98
  99 static void bnx2x_cmng_fns_init(struct bnx2x_softc *sc, uint8_t read_cfg,
 100                                 uint8_t cmng_type);
 101 static int bnx2x_get_cmng_fns_mode(struct bnx2x_softc *sc);
 102 static void storm_memset_cmng(struct bnx2x_softc *sc, struct cmng_init *cmng,
 103                               uint8_t port);
 104 static void bnx2x_set_reset_global(struct bnx2x_softc *sc);
 105 static void bnx2x_set_reset_in_progress(struct bnx2x_softc *sc);
 106 static uint8_t bnx2x_reset_is_done(struct bnx2x_softc *sc, int engine);
 107 static uint8_t bnx2x_clear_pf_load(struct bnx2x_softc *sc);
 108 static uint8_t bnx2x_chk_parity_attn(struct bnx2x_softc *sc, uint8_t * global,
 109                                      uint8_t print);
 110 static void bnx2x_int_disable(struct bnx2x_softc *sc);
 111 static int bnx2x_release_leader_lock(struct bnx2x_softc *sc);
 112 static void bnx2x_pf_disable(struct bnx2x_softc *sc);
 113 static void bnx2x_update_rx_prod(struct bnx2x_softc *sc,
 114                                  struct bnx2x_fastpath *fp,
 115                                  uint16_t rx_bd_prod, uint16_t rx_cq_prod);
 116 static void bnx2x_link_report_locked(struct bnx2x_softc *sc);
 117 static void bnx2x_link_report(struct bnx2x_softc *sc);
 118 void bnx2x_link_status_update(struct bnx2x_softc *sc);
 119 static int bnx2x_alloc_mem(struct bnx2x_softc *sc);
 120 static void bnx2x_free_mem(struct bnx2x_softc *sc);
 121 static int bnx2x_alloc_fw_stats_mem(struct bnx2x_softc *sc);
 122 static void bnx2x_free_fw_stats_mem(struct bnx2x_softc *sc);
 123 static __rte_noinline
 124 int bnx2x_nic_load(struct bnx2x_softc *sc);
 125
 126 static int bnx2x_handle_sp_tq(struct bnx2x_softc *sc);
 127 static void bnx2x_handle_fp_tq(struct bnx2x_fastpath *fp);
 128 static void bnx2x_ack_sb(struct bnx2x_softc *sc, uint8_t igu_sb_id,
 129                          uint8_t storm, uint16_t index, uint8_t op,
 130                          uint8_t update);
 131
 132 int bnx2x_test_bit(int nr, volatile unsigned long *addr)
 133 {
 134         int res;
 135
 136         mb();
 137         res = ((*addr) & (1UL << nr)) != 0;
 138         mb();
 139         return res;
 140 }
 141
 142 void bnx2x_set_bit(unsigned int nr, volatile unsigned long *addr)
 143 {
 144         __sync_fetch_and_or(addr, (1UL << nr));
 145 }
 146
 147 void bnx2x_clear_bit(int nr, volatile unsigned long *addr)
 148 {
 149         __sync_fetch_and_and(addr, ~(1UL << nr));
 150 }
 151
 152 int bnx2x_test_and_clear_bit(int nr, volatile unsigned long *addr)
 153 {
 154         unsigned long mask = (1UL << nr);
 155         return __sync_fetch_and_and(addr, ~mask) & mask;
 156 }
 157
 158 int bnx2x_cmpxchg(volatile int *addr, int old, int new)
 159 {
 160         return __sync_val_compare_and_swap(addr, old, new);
 161 }
 162
 163 int
 164 bnx2x_dma_alloc(struct bnx2x_softc *sc, size_t size, struct bnx2x_dma *dma,
 165               const char *msg, uint32_t align)
 166 {
 167         char mz_name[RTE_MEMZONE_NAMESIZE];
 168         const struct rte_memzone *z;
 169
 170         dma->sc = sc;
 171         if (IS_PF(sc))
 172                 snprintf(mz_name, sizeof(mz_name), "bnx2x%d_%s_%" PRIx64, SC_ABS_FUNC(sc), msg,
 173                         rte_get_timer_cycles());
 174         else
 175                 snprintf(mz_name, sizeof(mz_name), "bnx2x%d_%s_%" PRIx64, sc->pcie_device, msg,
 176                         rte_get_timer_cycles());
 177
 178         /* Caller must take care that strlen(mz_name) < RTE_MEMZONE_NAMESIZE */
 179         z = rte_memzone_reserve_aligned(mz_name, (uint64_t)size,
 180                                         SOCKET_ID_ANY,
 181                                         RTE_MEMZONE_IOVA_CONTIG, align);
 182         if (z == NULL) {
 183                 PMD_DRV_LOG(ERR, sc, "DMA alloc failed for %s", msg);
 184                 return -ENOMEM;
 185         }
 186         dma->paddr = (uint64_t) z->iova;
 187         dma->vaddr = z->addr;
 188         dma->mzone = (const void *)z;
 189
 190         PMD_DRV_LOG(DEBUG, sc,
 191                     "%s: virt=%p phys=%" PRIx64, msg, dma->vaddr, dma->paddr);
 192
 193         return 0;
 194 }
 195
 196 void bnx2x_dma_free(struct bnx2x_dma *dma)
 197 {
 198         if (dma->mzone == NULL)
 199                 return;
 200
 201         rte_memzone_free((const struct rte_memzone *)dma->mzone);
 202         dma->sc = NULL;
 203         dma->paddr = 0;
 204         dma->vaddr = NULL;
 205         dma->nseg = 0;
 206         dma->mzone = NULL;
 207 }
 208
 209 static int bnx2x_acquire_hw_lock(struct bnx2x_softc *sc, uint32_t resource)
 210 {
 211         uint32_t lock_status;
 212         uint32_t resource_bit = (1 << resource);
 213         int func = SC_FUNC(sc);
 214         uint32_t hw_lock_control_reg;
 215         int cnt;
 216
 217 #ifndef RTE_LIBRTE_BNX2X_DEBUG_PERIODIC
 218         if (resource)
 219                 PMD_INIT_FUNC_TRACE(sc);
 220 #else
 221         PMD_INIT_FUNC_TRACE(sc);
 222 #endif
 223
 224         /* validate the resource is within range */
 225         if (resource > HW_LOCK_MAX_RESOURCE_VALUE) {
 226                 PMD_DRV_LOG(NOTICE, sc,
 227                             "resource 0x%x > HW_LOCK_MAX_RESOURCE_VALUE",
 228                             resource);
 229                 return -1;
 230         }
 231
 232         if (func <= 5) {
 233                 hw_lock_control_reg = (MISC_REG_DRIVER_CONTROL_1 + (func * 8));
 234         } else {
 235                 hw_lock_control_reg =
 236                     (MISC_REG_DRIVER_CONTROL_7 + ((func - 6) * 8));
 237         }
 238
 239         /* validate the resource is not already taken */
 240         lock_status = REG_RD(sc, hw_lock_control_reg);
 241         if (lock_status & resource_bit) {
 242                 PMD_DRV_LOG(NOTICE, sc,
 243                             "resource in use (status 0x%x bit 0x%x)",
 244                             lock_status, resource_bit);
 245                 return -1;
 246         }
 247
 248         /* try every 5ms for 5 seconds */
 249         for (cnt = 0; cnt < 1000; cnt++) {
 250                 REG_WR(sc, (hw_lock_control_reg + 4), resource_bit);
 251                 lock_status = REG_RD(sc, hw_lock_control_reg);
 252                 if (lock_status & resource_bit) {
 253                         return 0;
 254                 }
 255                 DELAY(5000);
 256         }
 257
 258         PMD_DRV_LOG(NOTICE, sc, "Resource 0x%x resource_bit 0x%x lock timeout!",
 259                     resource, resource_bit);
 260         return -1;
 261 }
 262
 263 static int bnx2x_release_hw_lock(struct bnx2x_softc *sc, uint32_t resource)
 264 {
 265         uint32_t lock_status;
 266         uint32_t resource_bit = (1 << resource);
 267         int func = SC_FUNC(sc);
 268         uint32_t hw_lock_control_reg;
 269
 270 #ifndef RTE_LIBRTE_BNX2X_DEBUG_PERIODIC
 271         if (resource)
 272                 PMD_INIT_FUNC_TRACE(sc);
 273 #else
 274         PMD_INIT_FUNC_TRACE(sc);
 275 #endif
 276
 277         /* validate the resource is within range */
 278         if (resource > HW_LOCK_MAX_RESOURCE_VALUE) {
 279                 PMD_DRV_LOG(NOTICE, sc,
 280                             "(resource 0x%x > HW_LOCK_MAX_RESOURCE_VALUE)"
 281                             " resource_bit 0x%x", resource, resource_bit);
 282                 return -1;
 283         }
 284
 285         if (func <= 5) {
 286                 hw_lock_control_reg = (MISC_REG_DRIVER_CONTROL_1 + (func * 8));
 287         } else {
 288                 hw_lock_control_reg =
 289                     (MISC_REG_DRIVER_CONTROL_7 + ((func - 6) * 8));
 290         }
 291
 292         /* validate the resource is currently taken */
 293         lock_status = REG_RD(sc, hw_lock_control_reg);
 294         if (!(lock_status & resource_bit)) {
 295                 PMD_DRV_LOG(NOTICE, sc,
 296                             "resource not in use (status 0x%x bit 0x%x)",
 297                             lock_status, resource_bit);
 298                 return -1;
 299         }
 300
 301         REG_WR(sc, hw_lock_control_reg, resource_bit);
 302         return 0;
 303 }
 304
 305 static void bnx2x_acquire_phy_lock(struct bnx2x_softc *sc)
 306 {
 307         BNX2X_PHY_LOCK(sc);
 308         bnx2x_acquire_hw_lock(sc, HW_LOCK_RESOURCE_MDIO);
 309 }
 310
 311 static void bnx2x_release_phy_lock(struct bnx2x_softc *sc)
 312 {
 313         bnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_MDIO);
 314         BNX2X_PHY_UNLOCK(sc);
 315 }
 316
 317 /* copy command into DMAE command memory and set DMAE command Go */
 318 void bnx2x_post_dmae(struct bnx2x_softc *sc, struct dmae_command *dmae, int idx)
 319 {
 320         uint32_t cmd_offset;
 321         uint32_t i;
 322
 323         cmd_offset = (DMAE_REG_CMD_MEM + (sizeof(struct dmae_command) * idx));
 324         for (i = 0; i < ((sizeof(struct dmae_command) / 4)); i++) {
 325                 REG_WR(sc, (cmd_offset + (i * 4)), *(((uint32_t *) dmae) + i));
 326         }
 327
 328         REG_WR(sc, dmae_reg_go_c[idx], 1);
 329 }
 330
 331 uint32_t bnx2x_dmae_opcode_add_comp(uint32_t opcode, uint8_t comp_type)
 332 {
 333         return opcode | ((comp_type << DMAE_COMMAND_C_DST_SHIFT) |
 334                           DMAE_COMMAND_C_TYPE_ENABLE);
 335 }
 336
 337 uint32_t bnx2x_dmae_opcode_clr_src_reset(uint32_t opcode)
 338 {
 339         return opcode & ~DMAE_COMMAND_SRC_RESET;
 340 }
 341
 342 uint32_t
 343 bnx2x_dmae_opcode(struct bnx2x_softc * sc, uint8_t src_type, uint8_t dst_type,
 344                 uint8_t with_comp, uint8_t comp_type)
 345 {
 346         uint32_t opcode = 0;
 347
 348         opcode |= ((src_type << DMAE_COMMAND_SRC_SHIFT) |
 349                    (dst_type << DMAE_COMMAND_DST_SHIFT));
 350
 351         opcode |= (DMAE_COMMAND_SRC_RESET | DMAE_COMMAND_DST_RESET);
 352
 353         opcode |= (SC_PORT(sc) ? DMAE_CMD_PORT_1 : DMAE_CMD_PORT_0);
 354
 355         opcode |= ((SC_VN(sc) << DMAE_COMMAND_E1HVN_SHIFT) |
 356                    (SC_VN(sc) << DMAE_COMMAND_DST_VN_SHIFT));
 357
 358         opcode |= (DMAE_COM_SET_ERR << DMAE_COMMAND_ERR_POLICY_SHIFT);
 359
 360 #ifdef __BIG_ENDIAN
 361         opcode |= DMAE_CMD_ENDIANITY_B_DW_SWAP;
 362 #else
 363         opcode |= DMAE_CMD_ENDIANITY_DW_SWAP;
 364 #endif
 365
 366         if (with_comp) {
 367                 opcode = bnx2x_dmae_opcode_add_comp(opcode, comp_type);
 368         }
 369
 370         return opcode;
 371 }
 372
 373 static void
 374 bnx2x_prep_dmae_with_comp(struct bnx2x_softc *sc, struct dmae_command *dmae,
 375                         uint8_t src_type, uint8_t dst_type)
 376 {
 377         memset(dmae, 0, sizeof(struct dmae_command));
 378
 379         /* set the opcode */
 380         dmae->opcode = bnx2x_dmae_opcode(sc, src_type, dst_type,
 381                                        TRUE, DMAE_COMP_PCI);
 382
 383         /* fill in the completion parameters */
 384         dmae->comp_addr_lo = U64_LO(BNX2X_SP_MAPPING(sc, wb_comp));
 385         dmae->comp_addr_hi = U64_HI(BNX2X_SP_MAPPING(sc, wb_comp));
 386         dmae->comp_val = DMAE_COMP_VAL;
 387 }
 388
 389 /* issue a DMAE command over the init channel and wait for completion */
 390 static int
 391 bnx2x_issue_dmae_with_comp(struct bnx2x_softc *sc, struct dmae_command *dmae)
 392 {
 393         uint32_t *wb_comp = BNX2X_SP(sc, wb_comp);
 394         int timeout = CHIP_REV_IS_SLOW(sc) ? 400000 : 4000;
 395
 396         /* reset completion */
 397         *wb_comp = 0;
 398
 399         /* post the command on the channel used for initializations */
 400         bnx2x_post_dmae(sc, dmae, INIT_DMAE_C(sc));
 401
 402         /* wait for completion */
 403         DELAY(500);
 404
 405         while ((*wb_comp & ~DMAE_PCI_ERR_FLAG) != DMAE_COMP_VAL) {
 406                 if (!timeout ||
 407                     (sc->recovery_state != BNX2X_RECOVERY_DONE &&
 408                      sc->recovery_state != BNX2X_RECOVERY_NIC_LOADING)) {
 409                         PMD_DRV_LOG(INFO, sc, "DMAE timeout!");
 410                         return DMAE_TIMEOUT;
 411                 }
 412
 413                 timeout--;
 414                 DELAY(50);
 415         }
 416
 417         if (*wb_comp & DMAE_PCI_ERR_FLAG) {
 418                 PMD_DRV_LOG(INFO, sc, "DMAE PCI error!");
 419                 return DMAE_PCI_ERROR;
 420         }
 421
 422         return 0;
 423 }
 424
 425 void bnx2x_read_dmae(struct bnx2x_softc *sc, uint32_t src_addr, uint32_t len32)
 426 {
 427         struct dmae_command dmae;
 428         uint32_t *data;
 429         uint32_t i;
 430         int rc;
 431
 432         if (!sc->dmae_ready) {
 433                 data = BNX2X_SP(sc, wb_data[0]);
 434
 435                 for (i = 0; i < len32; i++) {
 436                         data[i] = REG_RD(sc, (src_addr + (i * 4)));
 437                 }
 438
 439                 return;
 440         }
 441
 442         /* set opcode and fixed command fields */
 443         bnx2x_prep_dmae_with_comp(sc, &dmae, DMAE_SRC_GRC, DMAE_DST_PCI);
 444
 445         /* fill in addresses and len */
 446         dmae.src_addr_lo = (src_addr >> 2);     /* GRC addr has dword resolution */
 447         dmae.src_addr_hi = 0;
 448         dmae.dst_addr_lo = U64_LO(BNX2X_SP_MAPPING(sc, wb_data));
 449         dmae.dst_addr_hi = U64_HI(BNX2X_SP_MAPPING(sc, wb_data));
 450         dmae.len = len32;
 451
 452         /* issue the command and wait for completion */
 453         if ((rc = bnx2x_issue_dmae_with_comp(sc, &dmae)) != 0) {
 454                 rte_panic("DMAE failed (%d)", rc);
 455         };
 456 }
 457
 458 void
 459 bnx2x_write_dmae(struct bnx2x_softc *sc, rte_iova_t dma_addr, uint32_t dst_addr,
 460                uint32_t len32)
 461 {
 462         struct dmae_command dmae;
 463         int rc;
 464
 465         if (!sc->dmae_ready) {
 466                 ecore_init_str_wr(sc, dst_addr, BNX2X_SP(sc, wb_data[0]), len32);
 467                 return;
 468         }
 469
 470         /* set opcode and fixed command fields */
 471         bnx2x_prep_dmae_with_comp(sc, &dmae, DMAE_SRC_PCI, DMAE_DST_GRC);
 472
 473         /* fill in addresses and len */
 474         dmae.src_addr_lo = U64_LO(dma_addr);
 475         dmae.src_addr_hi = U64_HI(dma_addr);
 476         dmae.dst_addr_lo = (dst_addr >> 2);     /* GRC addr has dword resolution */
 477         dmae.dst_addr_hi = 0;
 478         dmae.len = len32;
 479
 480         /* issue the command and wait for completion */
 481         if ((rc = bnx2x_issue_dmae_with_comp(sc, &dmae)) != 0) {
 482                 rte_panic("DMAE failed (%d)", rc);
 483         }
 484 }
 485
 486 static void
 487 bnx2x_write_dmae_phys_len(struct bnx2x_softc *sc, rte_iova_t phys_addr,
 488                         uint32_t addr, uint32_t len)
 489 {
 490         uint32_t dmae_wr_max = DMAE_LEN32_WR_MAX(sc);
 491         uint32_t offset = 0;
 492
 493         while (len > dmae_wr_max) {
 494                 bnx2x_write_dmae(sc, (phys_addr + offset),      /* src DMA address */
 495                                (addr + offset), /* dst GRC address */
 496                                dmae_wr_max);
 497                 offset += (dmae_wr_max * 4);
 498                 len -= dmae_wr_max;
 499         }
 500
 501         bnx2x_write_dmae(sc, (phys_addr + offset),      /* src DMA address */
 502                        (addr + offset), /* dst GRC address */
 503                        len);
 504 }
 505
 506 void
 507 bnx2x_set_ctx_validation(struct bnx2x_softc *sc, struct eth_context *cxt,
 508                        uint32_t cid)
 509 {
 510         /* ustorm cxt validation */
 511         cxt->ustorm_ag_context.cdu_usage =
 512             CDU_RSRVD_VALUE_TYPE_A(HW_CID(sc, cid),
 513                                    CDU_REGION_NUMBER_UCM_AG,
 514                                    ETH_CONNECTION_TYPE);
 515         /* xcontext validation */
 516         cxt->xstorm_ag_context.cdu_reserved =
 517             CDU_RSRVD_VALUE_TYPE_A(HW_CID(sc, cid),
 518                                    CDU_REGION_NUMBER_XCM_AG,
 519                                    ETH_CONNECTION_TYPE);
 520 }
 521
 522 static void
 523 bnx2x_storm_memset_hc_timeout(struct bnx2x_softc *sc, uint8_t fw_sb_id,
 524                             uint8_t sb_index, uint8_t ticks)
 525 {
 526         uint32_t addr =
 527             (BAR_CSTRORM_INTMEM +
 528              CSTORM_STATUS_BLOCK_DATA_TIMEOUT_OFFSET(fw_sb_id, sb_index));
 529
 530         REG_WR8(sc, addr, ticks);
 531 }
 532
 533 static void
 534 bnx2x_storm_memset_hc_disable(struct bnx2x_softc *sc, uint16_t fw_sb_id,
 535                             uint8_t sb_index, uint8_t disable)
 536 {
 537         uint32_t enable_flag =
 538             (disable) ? 0 : (1 << HC_INDEX_DATA_HC_ENABLED_SHIFT);
 539         uint32_t addr =
 540             (BAR_CSTRORM_INTMEM +
 541              CSTORM_STATUS_BLOCK_DATA_FLAGS_OFFSET(fw_sb_id, sb_index));
 542         uint8_t flags;
 543
 544         /* clear and set */
 545         flags = REG_RD8(sc, addr);
 546         flags &= ~HC_INDEX_DATA_HC_ENABLED;
 547         flags |= enable_flag;
 548         REG_WR8(sc, addr, flags);
 549 }
 550
 551 void
 552 bnx2x_update_coalesce_sb_index(struct bnx2x_softc *sc, uint8_t fw_sb_id,
 553                              uint8_t sb_index, uint8_t disable, uint16_t usec)
 554 {
 555         uint8_t ticks = (usec / 4);
 556
 557         bnx2x_storm_memset_hc_timeout(sc, fw_sb_id, sb_index, ticks);
 558
 559         disable = (disable) ? 1 : ((usec) ? 0 : 1);
 560         bnx2x_storm_memset_hc_disable(sc, fw_sb_id, sb_index, disable);
 561 }
 562
 563 uint32_t elink_cb_reg_read(struct bnx2x_softc *sc, uint32_t reg_addr)
 564 {
 565         return REG_RD(sc, reg_addr);
 566 }
 567
 568 void elink_cb_reg_write(struct bnx2x_softc *sc, uint32_t reg_addr, uint32_t val)
 569 {
 570         REG_WR(sc, reg_addr, val);
 571 }
 572
 573 void
 574 elink_cb_event_log(__rte_unused struct bnx2x_softc *sc,
 575                    __rte_unused const elink_log_id_t elink_log_id, ...)
 576 {
 577         PMD_DRV_LOG(DEBUG, sc, "ELINK EVENT LOG (%d)", elink_log_id);
 578 }
 579
 580 static int bnx2x_set_spio(struct bnx2x_softc *sc, int spio, uint32_t mode)
 581 {
 582         uint32_t spio_reg;
 583
 584         /* Only 2 SPIOs are configurable */
 585         if ((spio != MISC_SPIO_SPIO4) && (spio != MISC_SPIO_SPIO5)) {
 586                 PMD_DRV_LOG(NOTICE, sc, "Invalid SPIO 0x%x", spio);
 587                 return -1;
 588         }
 589
 590         bnx2x_acquire_hw_lock(sc, HW_LOCK_RESOURCE_SPIO);
 591
 592         /* read SPIO and mask except the float bits */
 593         spio_reg = (REG_RD(sc, MISC_REG_SPIO) & MISC_SPIO_FLOAT);
 594
 595         switch (mode) {
 596         case MISC_SPIO_OUTPUT_LOW:
 597                 /* clear FLOAT and set CLR */
 598                 spio_reg &= ~(spio << MISC_SPIO_FLOAT_POS);
 599                 spio_reg |= (spio << MISC_SPIO_CLR_POS);
 600                 break;
 601
 602         case MISC_SPIO_OUTPUT_HIGH:
 603                 /* clear FLOAT and set SET */
 604                 spio_reg &= ~(spio << MISC_SPIO_FLOAT_POS);
 605                 spio_reg |= (spio << MISC_SPIO_SET_POS);
 606                 break;
 607
 608         case MISC_SPIO_INPUT_HI_Z:
 609                 /* set FLOAT */
 610                 spio_reg |= (spio << MISC_SPIO_FLOAT_POS);
 611                 break;
 612
 613         default:
 614                 break;
 615         }
 616
 617         REG_WR(sc, MISC_REG_SPIO, spio_reg);
 618         bnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_SPIO);
 619
 620         return 0;
 621 }
 622
 623 static int bnx2x_gpio_read(struct bnx2x_softc *sc, int gpio_num, uint8_t port)
 624 {
 625         /* The GPIO should be swapped if swap register is set and active */
 626         int gpio_port = ((REG_RD(sc, NIG_REG_PORT_SWAP) &&
 627                           REG_RD(sc, NIG_REG_STRAP_OVERRIDE)) ^ port);
 628         int gpio_shift = gpio_num;
 629         if (gpio_port)
 630                 gpio_shift += MISC_REGISTERS_GPIO_PORT_SHIFT;
 631
 632         uint32_t gpio_mask = (1 << gpio_shift);
 633         uint32_t gpio_reg;
 634
 635         if (gpio_num > MISC_REGISTERS_GPIO_3) {
 636                 PMD_DRV_LOG(NOTICE, sc, "Invalid GPIO %d", gpio_num);
 637                 return -1;
 638         }
 639
 640         /* read GPIO value */
 641         gpio_reg = REG_RD(sc, MISC_REG_GPIO);
 642
 643         /* get the requested pin value */
 644         return ((gpio_reg & gpio_mask) == gpio_mask) ? 1 : 0;
 645 }
 646
 647 static int
 648 bnx2x_gpio_write(struct bnx2x_softc *sc, int gpio_num, uint32_t mode, uint8_t port)
 649 {
 650         /* The GPIO should be swapped if swap register is set and active */
 651         int gpio_port = ((REG_RD(sc, NIG_REG_PORT_SWAP) &&
 652                           REG_RD(sc, NIG_REG_STRAP_OVERRIDE)) ^ port);
 653         int gpio_shift = gpio_num;
 654         if (gpio_port)
 655                 gpio_shift += MISC_REGISTERS_GPIO_PORT_SHIFT;
 656
 657         uint32_t gpio_mask = (1 << gpio_shift);
 658         uint32_t gpio_reg;
 659
 660         if (gpio_num > MISC_REGISTERS_GPIO_3) {
 661                 PMD_DRV_LOG(NOTICE, sc, "Invalid GPIO %d", gpio_num);
 662                 return -1;
 663         }
 664
 665         bnx2x_acquire_hw_lock(sc, HW_LOCK_RESOURCE_GPIO);
 666
 667         /* read GPIO and mask except the float bits */
 668         gpio_reg = (REG_RD(sc, MISC_REG_GPIO) & MISC_REGISTERS_GPIO_FLOAT);
 669
 670         switch (mode) {
 671         case MISC_REGISTERS_GPIO_OUTPUT_LOW:
 672                 /* clear FLOAT and set CLR */
 673                 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS);
 674                 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_CLR_POS);
 675                 break;
 676
 677         case MISC_REGISTERS_GPIO_OUTPUT_HIGH:
 678                 /* clear FLOAT and set SET */
 679                 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS);
 680                 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_SET_POS);
 681                 break;
 682
 683         case MISC_REGISTERS_GPIO_INPUT_HI_Z:
 684                 /* set FLOAT */
 685                 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS);
 686                 break;
 687
 688         default:
 689                 break;
 690         }
 691
 692         REG_WR(sc, MISC_REG_GPIO, gpio_reg);
 693         bnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_GPIO);
 694
 695         return 0;
 696 }
 697
 698 static int
 699 bnx2x_gpio_mult_write(struct bnx2x_softc *sc, uint8_t pins, uint32_t mode)
 700 {
 701         uint32_t gpio_reg;
 702
 703         /* any port swapping should be handled by caller */
 704
 705         bnx2x_acquire_hw_lock(sc, HW_LOCK_RESOURCE_GPIO);
 706
 707         /* read GPIO and mask except the float bits */
 708         gpio_reg = REG_RD(sc, MISC_REG_GPIO);
 709         gpio_reg &= ~(pins << MISC_REGISTERS_GPIO_FLOAT_POS);
 710         gpio_reg &= ~(pins << MISC_REGISTERS_GPIO_CLR_POS);
 711         gpio_reg &= ~(pins << MISC_REGISTERS_GPIO_SET_POS);
 712
 713         switch (mode) {
 714         case MISC_REGISTERS_GPIO_OUTPUT_LOW:
 715                 /* set CLR */
 716                 gpio_reg |= (pins << MISC_REGISTERS_GPIO_CLR_POS);
 717                 break;
 718
 719         case MISC_REGISTERS_GPIO_OUTPUT_HIGH:
 720                 /* set SET */
 721                 gpio_reg |= (pins << MISC_REGISTERS_GPIO_SET_POS);
 722                 break;
 723
 724         case MISC_REGISTERS_GPIO_INPUT_HI_Z:
 725                 /* set FLOAT */
 726                 gpio_reg |= (pins << MISC_REGISTERS_GPIO_FLOAT_POS);
 727                 break;
 728
 729         default:
 730                 PMD_DRV_LOG(NOTICE, sc,
 731                             "Invalid GPIO mode assignment %d", mode);
 732                 bnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_GPIO);
 733                 return -1;
 734         }
 735
 736         REG_WR(sc, MISC_REG_GPIO, gpio_reg);
 737         bnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_GPIO);
 738
 739         return 0;
 740 }
 741
 742 static int
 743 bnx2x_gpio_int_write(struct bnx2x_softc *sc, int gpio_num, uint32_t mode,
 744                    uint8_t port)
 745 {
 746         /* The GPIO should be swapped if swap register is set and active */
 747         int gpio_port = ((REG_RD(sc, NIG_REG_PORT_SWAP) &&
 748                           REG_RD(sc, NIG_REG_STRAP_OVERRIDE)) ^ port);
 749         int gpio_shift = gpio_num;
 750         if (gpio_port)
 751                 gpio_shift += MISC_REGISTERS_GPIO_PORT_SHIFT;
 752
 753         uint32_t gpio_mask = (1 << gpio_shift);
 754         uint32_t gpio_reg;
 755
 756         if (gpio_num > MISC_REGISTERS_GPIO_3) {
 757                 PMD_DRV_LOG(NOTICE, sc, "Invalid GPIO %d", gpio_num);
 758                 return -1;
 759         }
 760
 761         bnx2x_acquire_hw_lock(sc, HW_LOCK_RESOURCE_GPIO);
 762
 763         /* read GPIO int */
 764         gpio_reg = REG_RD(sc, MISC_REG_GPIO_INT);
 765
 766         switch (mode) {
 767         case MISC_REGISTERS_GPIO_INT_OUTPUT_CLR:
 768                 /* clear SET and set CLR */
 769                 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_INT_SET_POS);
 770                 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_INT_CLR_POS);
 771                 break;
 772
 773         case MISC_REGISTERS_GPIO_INT_OUTPUT_SET:
 774                 /* clear CLR and set SET */
 775                 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_INT_CLR_POS);
 776                 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_INT_SET_POS);
 777                 break;
 778
 779         default:
 780                 break;
 781         }
 782
 783         REG_WR(sc, MISC_REG_GPIO_INT, gpio_reg);
 784         bnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_GPIO);
 785
 786         return 0;
 787 }
 788
 789 uint32_t
 790 elink_cb_gpio_read(struct bnx2x_softc * sc, uint16_t gpio_num, uint8_t port)
 791 {
 792         return bnx2x_gpio_read(sc, gpio_num, port);
 793 }
 794
 795 uint8_t elink_cb_gpio_write(struct bnx2x_softc * sc, uint16_t gpio_num, uint8_t mode,   /* 0=low 1=high */
 796                             uint8_t port)
 797 {
 798         return bnx2x_gpio_write(sc, gpio_num, mode, port);
 799 }
 800
 801 uint8_t
 802 elink_cb_gpio_mult_write(struct bnx2x_softc * sc, uint8_t pins,
 803                          uint8_t mode /* 0=low 1=high */ )
 804 {
 805         return bnx2x_gpio_mult_write(sc, pins, mode);
 806 }
 807
 808 uint8_t elink_cb_gpio_int_write(struct bnx2x_softc * sc, uint16_t gpio_num, uint8_t mode,       /* 0=low 1=high */
 809                                 uint8_t port)
 810 {
 811         return bnx2x_gpio_int_write(sc, gpio_num, mode, port);
 812 }
 813
 814 void elink_cb_notify_link_changed(struct bnx2x_softc *sc)
 815 {
 816         REG_WR(sc, (MISC_REG_AEU_GENERAL_ATTN_12 +
 817                     (SC_FUNC(sc) * sizeof(uint32_t))), 1);
 818 }
 819
 820 /* send the MCP a request, block until there is a reply */
 821 uint32_t
 822 elink_cb_fw_command(struct bnx2x_softc *sc, uint32_t command, uint32_t param)
 823 {
 824         int mb_idx = SC_FW_MB_IDX(sc);
 825         uint32_t seq;
 826         uint32_t rc = 0;
 827         uint32_t cnt = 1;
 828         uint8_t delay = CHIP_REV_IS_SLOW(sc) ? 100 : 10;
 829
 830         seq = ++sc->fw_seq;
 831         SHMEM_WR(sc, func_mb[mb_idx].drv_mb_param, param);
 832         SHMEM_WR(sc, func_mb[mb_idx].drv_mb_header, (command | seq));
 833
 834         PMD_DRV_LOG(DEBUG, sc,
 835                     "wrote command 0x%08x to FW MB param 0x%08x",
 836                     (command | seq), param);
 837
 838         /* Let the FW do it's magic. GIve it up to 5 seconds... */
 839         do {
 840                 DELAY(delay * 1000);
 841                 rc = SHMEM_RD(sc, func_mb[mb_idx].fw_mb_header);
 842         } while ((seq != (rc & FW_MSG_SEQ_NUMBER_MASK)) && (cnt++ < 500));
 843
 844         /* is this a reply to our command? */
 845         if (seq == (rc & FW_MSG_SEQ_NUMBER_MASK)) {
 846                 rc &= FW_MSG_CODE_MASK;
 847         } else {
 848                 /* Ruh-roh! */
 849                 PMD_DRV_LOG(NOTICE, sc, "FW failed to respond!");
 850                 rc = 0;
 851         }
 852
 853         return rc;
 854 }
 855
 856 static uint32_t
 857 bnx2x_fw_command(struct bnx2x_softc *sc, uint32_t command, uint32_t param)
 858 {
 859         return elink_cb_fw_command(sc, command, param);
 860 }
 861
 862 static void
 863 __storm_memset_dma_mapping(struct bnx2x_softc *sc, uint32_t addr,
 864                            rte_iova_t mapping)
 865 {
 866         REG_WR(sc, addr, U64_LO(mapping));
 867         REG_WR(sc, (addr + 4), U64_HI(mapping));
 868 }
 869
 870 static void
 871 storm_memset_spq_addr(struct bnx2x_softc *sc, rte_iova_t mapping,
 872                       uint16_t abs_fid)
 873 {
 874         uint32_t addr = (XSEM_REG_FAST_MEMORY +
 875                          XSTORM_SPQ_PAGE_BASE_OFFSET(abs_fid));
 876         __storm_memset_dma_mapping(sc, addr, mapping);
 877 }
 878
 879 static void
 880 storm_memset_vf_to_pf(struct bnx2x_softc *sc, uint16_t abs_fid, uint16_t pf_id)
 881 {
 882         REG_WR8(sc, (BAR_XSTRORM_INTMEM + XSTORM_VF_TO_PF_OFFSET(abs_fid)),
 883                 pf_id);
 884         REG_WR8(sc, (BAR_CSTRORM_INTMEM + CSTORM_VF_TO_PF_OFFSET(abs_fid)),
 885                 pf_id);
 886         REG_WR8(sc, (BAR_TSTRORM_INTMEM + TSTORM_VF_TO_PF_OFFSET(abs_fid)),
 887                 pf_id);
 888         REG_WR8(sc, (BAR_USTRORM_INTMEM + USTORM_VF_TO_PF_OFFSET(abs_fid)),
 889                 pf_id);
 890 }
 891
 892 static void
 893 storm_memset_func_en(struct bnx2x_softc *sc, uint16_t abs_fid, uint8_t enable)
 894 {
 895         REG_WR8(sc, (BAR_XSTRORM_INTMEM + XSTORM_FUNC_EN_OFFSET(abs_fid)),
 896                 enable);
 897         REG_WR8(sc, (BAR_CSTRORM_INTMEM + CSTORM_FUNC_EN_OFFSET(abs_fid)),
 898                 enable);
 899         REG_WR8(sc, (BAR_TSTRORM_INTMEM + TSTORM_FUNC_EN_OFFSET(abs_fid)),
 900                 enable);
 901         REG_WR8(sc, (BAR_USTRORM_INTMEM + USTORM_FUNC_EN_OFFSET(abs_fid)),
 902                 enable);
 903 }
 904
 905 static void
 906 storm_memset_eq_data(struct bnx2x_softc *sc, struct event_ring_data *eq_data,
 907                      uint16_t pfid)
 908 {
 909         uint32_t addr;
 910         size_t size;
 911
 912         addr = (BAR_CSTRORM_INTMEM + CSTORM_EVENT_RING_DATA_OFFSET(pfid));
 913         size = sizeof(struct event_ring_data);
 914         ecore_storm_memset_struct(sc, addr, size, (uint32_t *) eq_data);
 915 }
 916
 917 static void
 918 storm_memset_eq_prod(struct bnx2x_softc *sc, uint16_t eq_prod, uint16_t pfid)
 919 {
 920         uint32_t addr = (BAR_CSTRORM_INTMEM +
 921                          CSTORM_EVENT_RING_PROD_OFFSET(pfid));
 922         REG_WR16(sc, addr, eq_prod);
 923 }
 924
 925 /*
 926  * Post a slowpath command.
 927  *
 928  * A slowpath command is used to propagate a configuration change through
 929  * the controller in a controlled manner, allowing each STORM processor and
 930  * other H/W blocks to phase in the change.  The commands sent on the
 931  * slowpath are referred to as ramrods.  Depending on the ramrod used the
 932  * completion of the ramrod will occur in different ways.  Here's a
 933  * breakdown of ramrods and how they complete:
 934  *
 935  * RAMROD_CMD_ID_ETH_PORT_SETUP
 936  *   Used to setup the leading connection on a port.  Completes on the
 937  *   Receive Completion Queue (RCQ) of that port (typically fp[0]).
 938  *
 939  * RAMROD_CMD_ID_ETH_CLIENT_SETUP
 940  *   Used to setup an additional connection on a port.  Completes on the
 941  *   RCQ of the multi-queue/RSS connection being initialized.
 942  *
 943  * RAMROD_CMD_ID_ETH_STAT_QUERY
 944  *   Used to force the storm processors to update the statistics database
 945  *   in host memory.  This ramrod is send on the leading connection CID and
 946  *   completes as an index increment of the CSTORM on the default status
 947  *   block.
 948  *
 949  * RAMROD_CMD_ID_ETH_UPDATE
 950  *   Used to update the state of the leading connection, usually to udpate
 951  *   the RSS indirection table.  Completes on the RCQ of the leading
 952  *   connection. (Not currently used under FreeBSD until OS support becomes
 953  *   available.)
 954  *
 955  * RAMROD_CMD_ID_ETH_HALT
 956  *   Used when tearing down a connection prior to driver unload.  Completes
 957  *   on the RCQ of the multi-queue/RSS connection being torn down.  Don't
 958  *   use this on the leading connection.
 959  *
 960  * RAMROD_CMD_ID_ETH_SET_MAC
 961  *   Sets the Unicast/Broadcast/Multicast used by the port.  Completes on
 962  *   the RCQ of the leading connection.
 963  *
 964  * RAMROD_CMD_ID_ETH_CFC_DEL
 965  *   Used when tearing down a conneciton prior to driver unload.  Completes
 966  *   on the RCQ of the leading connection (since the current connection
 967  *   has been completely removed from controller memory).
 968  *
 969  * RAMROD_CMD_ID_ETH_PORT_DEL
 970  *   Used to tear down the leading connection prior to driver unload,
 971  *   typically fp[0].  Completes as an index increment of the CSTORM on the
 972  *   default status block.
 973  *
 974  * RAMROD_CMD_ID_ETH_FORWARD_SETUP
 975  *   Used for connection offload.  Completes on the RCQ of the multi-queue
 976  *   RSS connection that is being offloaded.  (Not currently used under
 977  *   FreeBSD.)
 978  *
 979  * There can only be one command pending per function.
 980  *
 981  * Returns:
 982  *   0 = Success, !0 = Failure.
 983  */
 984
 985 /* must be called under the spq lock */
 986 static inline struct eth_spe *bnx2x_sp_get_next(struct bnx2x_softc *sc)
 987 {
 988         struct eth_spe *next_spe = sc->spq_prod_bd;
 989
 990         if (sc->spq_prod_bd == sc->spq_last_bd) {
 991                 /* wrap back to the first eth_spq */
 992                 sc->spq_prod_bd = sc->spq;
 993                 sc->spq_prod_idx = 0;
 994         } else {
 995                 sc->spq_prod_bd++;
 996                 sc->spq_prod_idx++;
 997         }
 998
 999         return next_spe;
1000 }
1001
1002 /* must be called under the spq lock */
1003 static void bnx2x_sp_prod_update(struct bnx2x_softc *sc)
1004 {
1005         int func = SC_FUNC(sc);
1006
1007         /*
1008          * Make sure that BD data is updated before writing the producer.
1009          * BD data is written to the memory, the producer is read from the
1010          * memory, thus we need a full memory barrier to ensure the ordering.
1011          */
1012         mb();
1013
1014         REG_WR16(sc, (BAR_XSTRORM_INTMEM + XSTORM_SPQ_PROD_OFFSET(func)),
1015                  sc->spq_prod_idx);
1016
1017         mb();
1018 }
1019
1020 /**
1021  * bnx2x_is_contextless_ramrod - check if the current command ends on EQ
1022  *
1023  * @cmd:      command to check
1024  * @cmd_type: command type
1025  */
1026 static int bnx2x_is_contextless_ramrod(int cmd, int cmd_type)
1027 {
1028         if ((cmd_type == NONE_CONNECTION_TYPE) ||
1029             (cmd == RAMROD_CMD_ID_ETH_FORWARD_SETUP) ||
1030             (cmd == RAMROD_CMD_ID_ETH_CLASSIFICATION_RULES) ||
1031             (cmd == RAMROD_CMD_ID_ETH_FILTER_RULES) ||
1032             (cmd == RAMROD_CMD_ID_ETH_MULTICAST_RULES) ||
1033             (cmd == RAMROD_CMD_ID_ETH_SET_MAC) ||
1034             (cmd == RAMROD_CMD_ID_ETH_RSS_UPDATE)) {
1035                 return TRUE;
1036         } else {
1037                 return FALSE;
1038         }
1039 }
1040
1041 /**
1042  * bnx2x_sp_post - place a single command on an SP ring
1043  *
1044  * @sc:         driver handle
1045  * @command:    command to place (e.g. SETUP, FILTER_RULES, etc.)
1046  * @cid:        SW CID the command is related to
1047  * @data_hi:    command private data address (high 32 bits)
1048  * @data_lo:    command private data address (low 32 bits)
1049  * @cmd_type:   command type (e.g. NONE, ETH)
1050  *
1051  * SP data is handled as if it's always an address pair, thus data fields are
1052  * not swapped to little endian in upper functions. Instead this function swaps
1053  * data as if it's two uint32 fields.
1054  */
1055 int
1056 bnx2x_sp_post(struct bnx2x_softc *sc, int command, int cid, uint32_t data_hi,
1057             uint32_t data_lo, int cmd_type)
1058 {
1059         struct eth_spe *spe;
1060         uint16_t type;
1061         int common;
1062
1063         common = bnx2x_is_contextless_ramrod(command, cmd_type);
1064
1065         if (common) {
1066                 if (!atomic_load_acq_long(&sc->eq_spq_left)) {
1067                         PMD_DRV_LOG(INFO, sc, "EQ ring is full!");
1068                         return -1;
1069                 }
1070         } else {
1071                 if (!atomic_load_acq_long(&sc->cq_spq_left)) {
1072                         PMD_DRV_LOG(INFO, sc, "SPQ ring is full!");
1073                         return -1;
1074                 }
1075         }
1076
1077         spe = bnx2x_sp_get_next(sc);
1078
1079         /* CID needs port number to be encoded int it */
1080         spe->hdr.conn_and_cmd_data =
1081             htole32((command << SPE_HDR_CMD_ID_SHIFT) | HW_CID(sc, cid));
1082
1083         type = (cmd_type << SPE_HDR_CONN_TYPE_SHIFT) & SPE_HDR_CONN_TYPE;
1084
1085         /* TBD: Check if it works for VFs */
1086         type |= ((SC_FUNC(sc) << SPE_HDR_FUNCTION_ID_SHIFT) &
1087                  SPE_HDR_FUNCTION_ID);
1088
1089         spe->hdr.type = htole16(type);
1090
1091         spe->data.update_data_addr.hi = htole32(data_hi);
1092         spe->data.update_data_addr.lo = htole32(data_lo);
1093
1094         /*
1095          * It's ok if the actual decrement is issued towards the memory
1096          * somewhere between the lock and unlock. Thus no more explict
1097          * memory barrier is needed.
1098          */
1099         if (common) {
1100                 atomic_subtract_acq_long(&sc->eq_spq_left, 1);
1101         } else {
1102                 atomic_subtract_acq_long(&sc->cq_spq_left, 1);
1103         }
1104
1105         PMD_DRV_LOG(DEBUG, sc,
1106                     "SPQE[%x] (%x:%x) (cmd, common?) (%d,%d) hw_cid %x"
1107                     "data (%x:%x) type(0x%x) left (CQ, EQ) (%lx,%lx)",
1108                     sc->spq_prod_idx,
1109                     (uint32_t) U64_HI(sc->spq_dma.paddr),
1110                     (uint32_t) (U64_LO(sc->spq_dma.paddr) +
1111                                 (uint8_t *) sc->spq_prod_bd -
1112                                 (uint8_t *) sc->spq), command, common,
1113                     HW_CID(sc, cid), data_hi, data_lo, type,
1114                     atomic_load_acq_long(&sc->cq_spq_left),
1115                     atomic_load_acq_long(&sc->eq_spq_left));
1116
1117         /* RAMROD completion is processed in bnx2x_intr_legacy()
1118          * which can run from different contexts.
1119          * Ask bnx2x_intr_intr() to process RAMROD
1120          * completion whenever it gets scheduled.
1121          */
1122         rte_atomic32_set(&sc->scan_fp, 1);
1123         bnx2x_sp_prod_update(sc);
1124
1125         return 0;
1126 }
1127
1128 static void bnx2x_drv_pulse(struct bnx2x_softc *sc)
1129 {
1130         SHMEM_WR(sc, func_mb[SC_FW_MB_IDX(sc)].drv_pulse_mb,
1131                  sc->fw_drv_pulse_wr_seq);
1132 }
1133
1134 static int bnx2x_tx_queue_has_work(const struct bnx2x_fastpath *fp)
1135 {
1136         uint16_t hw_cons;
1137         struct bnx2x_tx_queue *txq = fp->sc->tx_queues[fp->index];
1138
1139         if (unlikely(!txq)) {
1140                 PMD_TX_LOG(ERR, "ERROR: TX queue is NULL");
1141                 return 0;
1142         }
1143
1144         mb();                   /* status block fields can change */
1145         hw_cons = le16toh(*fp->tx_cons_sb);
1146         return hw_cons != txq->tx_pkt_head;
1147 }
1148
1149 static uint8_t bnx2x_has_tx_work(struct bnx2x_fastpath *fp)
1150 {
1151         /* expand this for multi-cos if ever supported */
1152         return bnx2x_tx_queue_has_work(fp);
1153 }
1154
1155 static int bnx2x_has_rx_work(struct bnx2x_fastpath *fp)
1156 {
1157         uint16_t rx_cq_cons_sb;
1158         struct bnx2x_rx_queue *rxq;
1159         rxq = fp->sc->rx_queues[fp->index];
1160         if (unlikely(!rxq)) {
1161                 PMD_RX_LOG(ERR, "ERROR: RX queue is NULL");
1162                 return 0;
1163         }
1164
1165         mb();                   /* status block fields can change */
1166         rx_cq_cons_sb = le16toh(*fp->rx_cq_cons_sb);
1167         if (unlikely((rx_cq_cons_sb & MAX_RCQ_ENTRIES(rxq)) ==
1168                      MAX_RCQ_ENTRIES(rxq)))
1169                 rx_cq_cons_sb++;
1170         return rxq->rx_cq_head != rx_cq_cons_sb;
1171 }
1172
1173 static void
1174 bnx2x_sp_event(struct bnx2x_softc *sc, struct bnx2x_fastpath *fp,
1175              union eth_rx_cqe *rr_cqe)
1176 {
1177         int cid = SW_CID(rr_cqe->ramrod_cqe.conn_and_cmd_data);
1178         int command = CQE_CMD(rr_cqe->ramrod_cqe.conn_and_cmd_data);
1179         enum ecore_queue_cmd drv_cmd = ECORE_Q_CMD_MAX;
1180         struct ecore_queue_sp_obj *q_obj = &BNX2X_SP_OBJ(sc, fp).q_obj;
1181
1182         PMD_DRV_LOG(DEBUG, sc,
1183                     "fp=%d cid=%d got ramrod #%d state is %x type is %d",
1184                     fp->index, cid, command, sc->state,
1185                     rr_cqe->ramrod_cqe.ramrod_type);
1186
1187         switch (command) {
1188         case (RAMROD_CMD_ID_ETH_CLIENT_UPDATE):
1189                 PMD_DRV_LOG(DEBUG, sc, "got UPDATE ramrod. CID %d", cid);
1190                 drv_cmd = ECORE_Q_CMD_UPDATE;
1191                 break;
1192
1193         case (RAMROD_CMD_ID_ETH_CLIENT_SETUP):
1194                 PMD_DRV_LOG(DEBUG, sc, "got MULTI[%d] setup ramrod", cid);
1195                 drv_cmd = ECORE_Q_CMD_SETUP;
1196                 break;
1197
1198         case (RAMROD_CMD_ID_ETH_TX_QUEUE_SETUP):
1199                 PMD_DRV_LOG(DEBUG, sc,
1200                             "got MULTI[%d] tx-only setup ramrod", cid);
1201                 drv_cmd = ECORE_Q_CMD_SETUP_TX_ONLY;
1202                 break;
1203
1204         case (RAMROD_CMD_ID_ETH_HALT):
1205                 PMD_DRV_LOG(DEBUG, sc, "got MULTI[%d] halt ramrod", cid);
1206                 drv_cmd = ECORE_Q_CMD_HALT;
1207                 break;
1208
1209         case (RAMROD_CMD_ID_ETH_TERMINATE):
1210                 PMD_DRV_LOG(DEBUG, sc, "got MULTI[%d] teminate ramrod", cid);
1211                 drv_cmd = ECORE_Q_CMD_TERMINATE;
1212                 break;
1213
1214         case (RAMROD_CMD_ID_ETH_EMPTY):
1215                 PMD_DRV_LOG(DEBUG, sc, "got MULTI[%d] empty ramrod", cid);
1216                 drv_cmd = ECORE_Q_CMD_EMPTY;
1217                 break;
1218
1219         default:
1220                 PMD_DRV_LOG(DEBUG, sc,
1221                             "ERROR: unexpected MC reply (%d)"
1222                             "on fp[%d]", command, fp->index);
1223                 return;
1224         }
1225
1226         if ((drv_cmd != ECORE_Q_CMD_MAX) &&
1227             q_obj->complete_cmd(sc, q_obj, drv_cmd)) {
1228                 /*
1229                  * q_obj->complete_cmd() failure means that this was
1230                  * an unexpected completion.
1231                  *
1232                  * In this case we don't want to increase the sc->spq_left
1233                  * because apparently we haven't sent this command the first
1234                  * place.
1235                  */
1236                 // rte_panic("Unexpected SP completion");
1237                 return;
1238         }
1239
1240         atomic_add_acq_long(&sc->cq_spq_left, 1);
1241
1242         PMD_DRV_LOG(DEBUG, sc, "sc->cq_spq_left 0x%lx",
1243                     atomic_load_acq_long(&sc->cq_spq_left));
1244 }
1245
1246 static uint8_t bnx2x_rxeof(struct bnx2x_softc *sc, struct bnx2x_fastpath *fp)
1247 {
1248         struct bnx2x_rx_queue *rxq;
1249         uint16_t bd_cons, bd_prod, bd_prod_fw, comp_ring_cons;
1250         uint16_t hw_cq_cons, sw_cq_cons, sw_cq_prod;
1251
1252         rxq = sc->rx_queues[fp->index];
1253         if (!rxq) {
1254                 PMD_RX_LOG(ERR, "RX queue %d is NULL", fp->index);
1255                 return 0;
1256         }
1257
1258         /* CQ "next element" is of the size of the regular element */
1259         hw_cq_cons = le16toh(*fp->rx_cq_cons_sb);
1260         if (unlikely((hw_cq_cons & USABLE_RCQ_ENTRIES_PER_PAGE) ==
1261                      USABLE_RCQ_ENTRIES_PER_PAGE)) {
1262                 hw_cq_cons++;
1263         }
1264
1265         bd_cons = rxq->rx_bd_head;
1266         bd_prod = rxq->rx_bd_tail;
1267         bd_prod_fw = bd_prod;
1268         sw_cq_cons = rxq->rx_cq_head;
1269         sw_cq_prod = rxq->rx_cq_tail;
1270
1271         /*
1272          * Memory barrier necessary as speculative reads of the rx
1273          * buffer can be ahead of the index in the status block
1274          */
1275         rmb();
1276
1277         while (sw_cq_cons != hw_cq_cons) {
1278                 union eth_rx_cqe *cqe;
1279                 struct eth_fast_path_rx_cqe *cqe_fp;
1280                 uint8_t cqe_fp_flags;
1281                 enum eth_rx_cqe_type cqe_fp_type;
1282
1283                 comp_ring_cons = RCQ_ENTRY(sw_cq_cons, rxq);
1284                 bd_prod = RX_BD(bd_prod, rxq);
1285                 bd_cons = RX_BD(bd_cons, rxq);
1286
1287                 cqe = &rxq->cq_ring[comp_ring_cons];
1288                 cqe_fp = &cqe->fast_path_cqe;
1289                 cqe_fp_flags = cqe_fp->type_error_flags;
1290                 cqe_fp_type = cqe_fp_flags & ETH_FAST_PATH_RX_CQE_TYPE;
1291
1292                 /* is this a slowpath msg? */
1293                 if (CQE_TYPE_SLOW(cqe_fp_type)) {
1294                         bnx2x_sp_event(sc, fp, cqe);
1295                         goto next_cqe;
1296                 }
1297
1298                 /* is this an error packet? */
1299                 if (unlikely(cqe_fp_flags &
1300                              ETH_FAST_PATH_RX_CQE_PHY_DECODE_ERR_FLG)) {
1301                         PMD_RX_LOG(DEBUG, "flags 0x%x rx packet %u",
1302                                    cqe_fp_flags, sw_cq_cons);
1303                         goto next_rx;
1304                 }
1305
1306                 PMD_RX_LOG(DEBUG, "Dropping fastpath called from attn poller!");
1307
1308 next_rx:
1309                 bd_cons = NEXT_RX_BD(bd_cons);
1310                 bd_prod = NEXT_RX_BD(bd_prod);
1311                 bd_prod_fw = NEXT_RX_BD(bd_prod_fw);
1312
1313 next_cqe:
1314                 sw_cq_prod = NEXT_RCQ_IDX(sw_cq_prod);
1315                 sw_cq_cons = NEXT_RCQ_IDX(sw_cq_cons);
1316
1317         }                       /* while work to do */
1318
1319         rxq->rx_bd_head = bd_cons;
1320         rxq->rx_bd_tail = bd_prod_fw;
1321         rxq->rx_cq_head = sw_cq_cons;
1322         rxq->rx_cq_tail = sw_cq_prod;
1323
1324         /* Update producers */
1325         bnx2x_update_rx_prod(sc, fp, bd_prod_fw, sw_cq_prod);
1326
1327         return sw_cq_cons != hw_cq_cons;
1328 }
1329
1330 static uint16_t
1331 bnx2x_free_tx_pkt(__rte_unused struct bnx2x_fastpath *fp, struct bnx2x_tx_queue *txq,
1332                 uint16_t pkt_idx, uint16_t bd_idx)
1333 {
1334         struct eth_tx_start_bd *tx_start_bd =
1335             &txq->tx_ring[TX_BD(bd_idx, txq)].start_bd;
1336         uint16_t nbd = rte_le_to_cpu_16(tx_start_bd->nbd);
1337         struct rte_mbuf *tx_mbuf = txq->sw_ring[TX_BD(pkt_idx, txq)];
1338
1339         if (likely(tx_mbuf != NULL)) {
1340                 rte_pktmbuf_free_seg(tx_mbuf);
1341         } else {
1342                 PMD_RX_LOG(ERR, "fp[%02d] lost mbuf %lu",
1343                            fp->index, (unsigned long)TX_BD(pkt_idx, txq));
1344         }
1345
1346         txq->sw_ring[TX_BD(pkt_idx, txq)] = NULL;
1347         txq->nb_tx_avail += nbd;
1348
1349         while (nbd--)
1350                 bd_idx = NEXT_TX_BD(bd_idx);
1351
1352         return bd_idx;
1353 }
1354
1355 /* processes transmit completions */
1356 uint8_t bnx2x_txeof(__rte_unused struct bnx2x_softc * sc, struct bnx2x_fastpath * fp)
1357 {
1358         uint16_t bd_cons, hw_cons, sw_cons;
1359         __rte_unused uint16_t tx_bd_avail;
1360
1361         struct bnx2x_tx_queue *txq = fp->sc->tx_queues[fp->index];
1362
1363         if (unlikely(!txq)) {
1364                 PMD_TX_LOG(ERR, "ERROR: TX queue is NULL");
1365                 return 0;
1366         }
1367
1368         bd_cons = txq->tx_bd_head;
1369         hw_cons = rte_le_to_cpu_16(*fp->tx_cons_sb);
1370         sw_cons = txq->tx_pkt_head;
1371
1372         while (sw_cons != hw_cons) {
1373                 bd_cons = bnx2x_free_tx_pkt(fp, txq, sw_cons, bd_cons);
1374                 sw_cons++;
1375         }
1376
1377         txq->tx_pkt_head = sw_cons;
1378         txq->tx_bd_head = bd_cons;
1379
1380         tx_bd_avail = txq->nb_tx_avail;
1381
1382         PMD_TX_LOG(DEBUG, "fp[%02d] avail=%u cons_sb=%u, "
1383                    "pkt_head=%u pkt_tail=%u bd_head=%u bd_tail=%u",
1384                    fp->index, tx_bd_avail, hw_cons,
1385                    txq->tx_pkt_head, txq->tx_pkt_tail,
1386                    txq->tx_bd_head, txq->tx_bd_tail);
1387         return TRUE;
1388 }
1389
1390 static void bnx2x_drain_tx_queues(struct bnx2x_softc *sc)
1391 {
1392         struct bnx2x_fastpath *fp;
1393         int i, count;
1394
1395         /* wait until all TX fastpath tasks have completed */
1396         for (i = 0; i < sc->num_queues; i++) {
1397                 fp = &sc->fp[i];
1398
1399                 count = 1000;
1400
1401                 while (bnx2x_has_tx_work(fp)) {
1402                         bnx2x_txeof(sc, fp);
1403
1404                         if (count == 0) {
1405                                 PMD_TX_LOG(ERR,
1406                                            "Timeout waiting for fp[%d] "
1407                                            "transmits to complete!", i);
1408                                 rte_panic("tx drain failure");
1409                                 return;
1410                         }
1411
1412                         count--;
1413                         DELAY(1000);
1414                         rmb();
1415                 }
1416         }
1417
1418         return;
1419 }
1420
1421 static int
1422 bnx2x_del_all_macs(struct bnx2x_softc *sc, struct ecore_vlan_mac_obj *mac_obj,
1423                  int mac_type, uint8_t wait_for_comp)
1424 {
1425         unsigned long ramrod_flags = 0, vlan_mac_flags = 0;
1426         int rc;
1427
1428         /* wait for completion of requested */
1429         if (wait_for_comp) {
1430                 bnx2x_set_bit(RAMROD_COMP_WAIT, &ramrod_flags);
1431         }
1432
1433         /* Set the mac type of addresses we want to clear */
1434         bnx2x_set_bit(mac_type, &vlan_mac_flags);
1435
1436         rc = mac_obj->delete_all(sc, mac_obj, &vlan_mac_flags, &ramrod_flags);
1437         if (rc < 0)
1438                 PMD_DRV_LOG(ERR, sc, "Failed to delete MACs (%d)", rc);
1439
1440         return rc;
1441 }
1442
1443 static int
1444 bnx2x_fill_accept_flags(struct bnx2x_softc *sc, uint32_t rx_mode,
1445                         unsigned long *rx_accept_flags,
1446                         unsigned long *tx_accept_flags)
1447 {
1448         /* Clear the flags first */
1449         *rx_accept_flags = 0;
1450         *tx_accept_flags = 0;
1451
1452         switch (rx_mode) {
1453         case BNX2X_RX_MODE_NONE:
1454                 /*
1455                  * 'drop all' supersedes any accept flags that may have been
1456                  * passed to the function.
1457                  */
1458                 break;
1459
1460         case BNX2X_RX_MODE_NORMAL:
1461                 bnx2x_set_bit(ECORE_ACCEPT_UNICAST, rx_accept_flags);
1462                 bnx2x_set_bit(ECORE_ACCEPT_MULTICAST, rx_accept_flags);
1463                 bnx2x_set_bit(ECORE_ACCEPT_BROADCAST, rx_accept_flags);
1464
1465                 /* internal switching mode */
1466                 bnx2x_set_bit(ECORE_ACCEPT_UNICAST, tx_accept_flags);
1467                 bnx2x_set_bit(ECORE_ACCEPT_MULTICAST, tx_accept_flags);
1468                 bnx2x_set_bit(ECORE_ACCEPT_BROADCAST, tx_accept_flags);
1469
1470                 break;
1471
1472         case BNX2X_RX_MODE_ALLMULTI:
1473                 bnx2x_set_bit(ECORE_ACCEPT_UNICAST, rx_accept_flags);
1474                 bnx2x_set_bit(ECORE_ACCEPT_ALL_MULTICAST, rx_accept_flags);
1475                 bnx2x_set_bit(ECORE_ACCEPT_BROADCAST, rx_accept_flags);
1476
1477                 /* internal switching mode */
1478                 bnx2x_set_bit(ECORE_ACCEPT_UNICAST, tx_accept_flags);
1479                 bnx2x_set_bit(ECORE_ACCEPT_ALL_MULTICAST, tx_accept_flags);
1480                 bnx2x_set_bit(ECORE_ACCEPT_BROADCAST, tx_accept_flags);
1481
1482                 break;
1483
1484         case BNX2X_RX_MODE_ALLMULTI_PROMISC:
1485         case BNX2X_RX_MODE_PROMISC:
1486                 /*
1487                  * According to deffinition of SI mode, iface in promisc mode
1488                  * should receive matched and unmatched (in resolution of port)
1489                  * unicast packets.
1490                  */
1491                 bnx2x_set_bit(ECORE_ACCEPT_UNMATCHED, rx_accept_flags);
1492                 bnx2x_set_bit(ECORE_ACCEPT_UNICAST, rx_accept_flags);
1493                 bnx2x_set_bit(ECORE_ACCEPT_ALL_MULTICAST, rx_accept_flags);
1494                 bnx2x_set_bit(ECORE_ACCEPT_BROADCAST, rx_accept_flags);
1495
1496                 /* internal switching mode */
1497                 bnx2x_set_bit(ECORE_ACCEPT_ALL_MULTICAST, tx_accept_flags);
1498                 bnx2x_set_bit(ECORE_ACCEPT_BROADCAST, tx_accept_flags);
1499
1500                 if (IS_MF_SI(sc)) {
1501                         bnx2x_set_bit(ECORE_ACCEPT_ALL_UNICAST, tx_accept_flags);
1502                 } else {
1503                         bnx2x_set_bit(ECORE_ACCEPT_UNICAST, tx_accept_flags);
1504                 }
1505
1506                 break;
1507
1508         default:
1509                 PMD_RX_LOG(ERR, "Unknown rx_mode (%d)", rx_mode);
1510                 return -1;
1511         }
1512
1513         /* Set ACCEPT_ANY_VLAN as we do not enable filtering by VLAN */
1514         if (rx_mode != BNX2X_RX_MODE_NONE) {
1515                 bnx2x_set_bit(ECORE_ACCEPT_ANY_VLAN, rx_accept_flags);
1516                 bnx2x_set_bit(ECORE_ACCEPT_ANY_VLAN, tx_accept_flags);
1517         }
1518
1519         return 0;
1520 }
1521
1522 static int
1523 bnx2x_set_q_rx_mode(struct bnx2x_softc *sc, uint8_t cl_id,
1524                   unsigned long rx_mode_flags,
1525                   unsigned long rx_accept_flags,
1526                   unsigned long tx_accept_flags, unsigned long ramrod_flags)
1527 {
1528         struct ecore_rx_mode_ramrod_params ramrod_param;
1529         int rc;
1530
1531         memset(&ramrod_param, 0, sizeof(ramrod_param));
1532
1533         /* Prepare ramrod parameters */
1534         ramrod_param.cid = 0;
1535         ramrod_param.cl_id = cl_id;
1536         ramrod_param.rx_mode_obj = &sc->rx_mode_obj;
1537         ramrod_param.func_id = SC_FUNC(sc);
1538
1539         ramrod_param.pstate = &sc->sp_state;
1540         ramrod_param.state = ECORE_FILTER_RX_MODE_PENDING;
1541
1542         ramrod_param.rdata = BNX2X_SP(sc, rx_mode_rdata);
1543         ramrod_param.rdata_mapping =
1544             (rte_iova_t)BNX2X_SP_MAPPING(sc, rx_mode_rdata),
1545             bnx2x_set_bit(ECORE_FILTER_RX_MODE_PENDING, &sc->sp_state);
1546
1547         ramrod_param.ramrod_flags = ramrod_flags;
1548         ramrod_param.rx_mode_flags = rx_mode_flags;
1549
1550         ramrod_param.rx_accept_flags = rx_accept_flags;
1551         ramrod_param.tx_accept_flags = tx_accept_flags;
1552
1553         rc = ecore_config_rx_mode(sc, &ramrod_param);
1554         if (rc < 0) {
1555                 PMD_RX_LOG(ERR, "Set rx_mode %d failed", sc->rx_mode);
1556                 return rc;
1557         }
1558
1559         return 0;
1560 }
1561
1562 int bnx2x_set_storm_rx_mode(struct bnx2x_softc *sc)
1563 {
1564         unsigned long rx_mode_flags = 0, ramrod_flags = 0;
1565         unsigned long rx_accept_flags = 0, tx_accept_flags = 0;
1566         int rc;
1567
1568         rc = bnx2x_fill_accept_flags(sc, sc->rx_mode, &rx_accept_flags,
1569                                    &tx_accept_flags);
1570         if (rc) {
1571                 return rc;
1572         }
1573
1574         bnx2x_set_bit(RAMROD_RX, &ramrod_flags);
1575         bnx2x_set_bit(RAMROD_TX, &ramrod_flags);
1576         bnx2x_set_bit(RAMROD_COMP_WAIT, &ramrod_flags);
1577
1578         return bnx2x_set_q_rx_mode(sc, sc->fp[0].cl_id, rx_mode_flags,
1579                                  rx_accept_flags, tx_accept_flags,
1580                                  ramrod_flags);
1581 }
1582
1583 /* returns the "mcp load_code" according to global load_count array */
1584 static int bnx2x_nic_load_no_mcp(struct bnx2x_softc *sc)
1585 {
1586         int path = SC_PATH(sc);
1587         int port = SC_PORT(sc);
1588
1589         PMD_DRV_LOG(INFO, sc, "NO MCP - load counts[%d]      %d, %d, %d",
1590                     path, load_count[path][0], load_count[path][1],
1591                     load_count[path][2]);
1592
1593         load_count[path][0]++;
1594         load_count[path][1 + port]++;
1595         PMD_DRV_LOG(INFO, sc, "NO MCP - new load counts[%d]  %d, %d, %d",
1596                     path, load_count[path][0], load_count[path][1],
1597                     load_count[path][2]);
1598         if (load_count[path][0] == 1)
1599                 return FW_MSG_CODE_DRV_LOAD_COMMON;
1600         else if (load_count[path][1 + port] == 1)
1601                 return FW_MSG_CODE_DRV_LOAD_PORT;
1602         else
1603                 return FW_MSG_CODE_DRV_LOAD_FUNCTION;
1604 }
1605
1606 /* returns the "mcp load_code" according to global load_count array */
1607 static int bnx2x_nic_unload_no_mcp(struct bnx2x_softc *sc)
1608 {
1609         int port = SC_PORT(sc);
1610         int path = SC_PATH(sc);
1611
1612         PMD_DRV_LOG(INFO, sc, "NO MCP - load counts[%d]      %d, %d, %d",
1613                     path, load_count[path][0], load_count[path][1],
1614                     load_count[path][2]);
1615         load_count[path][0]--;
1616         load_count[path][1 + port]--;
1617         PMD_DRV_LOG(INFO, sc, "NO MCP - new load counts[%d]  %d, %d, %d",
1618                     path, load_count[path][0], load_count[path][1],
1619                     load_count[path][2]);
1620         if (load_count[path][0] == 0) {
1621                 return FW_MSG_CODE_DRV_UNLOAD_COMMON;
1622         } else if (load_count[path][1 + port] == 0) {
1623                 return FW_MSG_CODE_DRV_UNLOAD_PORT;
1624         } else {
1625                 return FW_MSG_CODE_DRV_UNLOAD_FUNCTION;
1626         }
1627 }
1628
1629 /* request unload mode from the MCP: COMMON, PORT or FUNCTION */
1630 static uint32_t bnx2x_send_unload_req(struct bnx2x_softc *sc, int unload_mode)
1631 {
1632         uint32_t reset_code = 0;
1633
1634         /* Select the UNLOAD request mode */
1635         if (unload_mode == UNLOAD_NORMAL) {
1636                 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS;
1637         } else {
1638                 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS;
1639         }
1640
1641         /* Send the request to the MCP */
1642         if (!BNX2X_NOMCP(sc)) {
1643                 reset_code = bnx2x_fw_command(sc, reset_code, 0);
1644         } else {
1645                 reset_code = bnx2x_nic_unload_no_mcp(sc);
1646         }
1647
1648         return reset_code;
1649 }
1650
1651 /* send UNLOAD_DONE command to the MCP */
1652 static void bnx2x_send_unload_done(struct bnx2x_softc *sc, uint8_t keep_link)
1653 {
1654         uint32_t reset_param =
1655             keep_link ? DRV_MSG_CODE_UNLOAD_SKIP_LINK_RESET : 0;
1656
1657         /* Report UNLOAD_DONE to MCP */
1658         if (!BNX2X_NOMCP(sc)) {
1659                 bnx2x_fw_command(sc, DRV_MSG_CODE_UNLOAD_DONE, reset_param);
1660         }
1661 }
1662
1663 static int bnx2x_func_wait_started(struct bnx2x_softc *sc)
1664 {
1665         int tout = 50;
1666
1667         if (!sc->port.pmf) {
1668                 return 0;
1669         }
1670
1671         /*
1672          * (assumption: No Attention from MCP at this stage)
1673          * PMF probably in the middle of TX disable/enable transaction
1674          * 1. Sync IRS for default SB
1675          * 2. Sync SP queue - this guarantees us that attention handling started
1676          * 3. Wait, that TX disable/enable transaction completes
1677          *
1678          * 1+2 guarantee that if DCBX attention was scheduled it already changed
1679          * pending bit of transaction from STARTED-->TX_STOPPED, if we already
1680          * received completion for the transaction the state is TX_STOPPED.
1681          * State will return to STARTED after completion of TX_STOPPED-->STARTED
1682          * transaction.
1683          */
1684
1685         while (ecore_func_get_state(sc, &sc->func_obj) !=
1686                ECORE_F_STATE_STARTED && tout--) {
1687                 DELAY(20000);
1688         }
1689
1690         if (ecore_func_get_state(sc, &sc->func_obj) != ECORE_F_STATE_STARTED) {
1691                 /*
1692                  * Failed to complete the transaction in a "good way"
1693                  * Force both transactions with CLR bit.
1694                  */
1695                 struct ecore_func_state_params func_params = { NULL };
1696
1697                 PMD_DRV_LOG(NOTICE, sc, "Unexpected function state! "
1698                             "Forcing STARTED-->TX_STOPPED-->STARTED");
1699
1700                 func_params.f_obj = &sc->func_obj;
1701                 bnx2x_set_bit(RAMROD_DRV_CLR_ONLY, &func_params.ramrod_flags);
1702
1703                 /* STARTED-->TX_STOPPED */
1704                 func_params.cmd = ECORE_F_CMD_TX_STOP;
1705                 ecore_func_state_change(sc, &func_params);
1706
1707                 /* TX_STOPPED-->STARTED */
1708                 func_params.cmd = ECORE_F_CMD_TX_START;
1709                 return ecore_func_state_change(sc, &func_params);
1710         }
1711
1712         return 0;
1713 }
1714
1715 static int bnx2x_stop_queue(struct bnx2x_softc *sc, int index)
1716 {
1717         struct bnx2x_fastpath *fp = &sc->fp[index];
1718         struct ecore_queue_state_params q_params = { NULL };
1719         int rc;
1720
1721         PMD_DRV_LOG(DEBUG, sc, "stopping queue %d cid %d", index, fp->index);
1722
1723         q_params.q_obj = &sc->sp_objs[fp->index].q_obj;
1724         /* We want to wait for completion in this context */
1725         bnx2x_set_bit(RAMROD_COMP_WAIT, &q_params.ramrod_flags);
1726
1727         /* Stop the primary connection: */
1728
1729         /* ...halt the connection */
1730         q_params.cmd = ECORE_Q_CMD_HALT;
1731         rc = ecore_queue_state_change(sc, &q_params);
1732         if (rc) {
1733                 return rc;
1734         }
1735
1736         /* ...terminate the connection */
1737         q_params.cmd = ECORE_Q_CMD_TERMINATE;
1738         memset(&q_params.params.terminate, 0,
1739                sizeof(q_params.params.terminate));
1740         q_params.params.terminate.cid_index = FIRST_TX_COS_INDEX;
1741         rc = ecore_queue_state_change(sc, &q_params);
1742         if (rc) {
1743                 return rc;
1744         }
1745
1746         /* ...delete cfc entry */
1747         q_params.cmd = ECORE_Q_CMD_CFC_DEL;
1748         memset(&q_params.params.cfc_del, 0, sizeof(q_params.params.cfc_del));
1749         q_params.params.cfc_del.cid_index = FIRST_TX_COS_INDEX;
1750         return ecore_queue_state_change(sc, &q_params);
1751 }
1752
1753 /* wait for the outstanding SP commands */
1754 static uint8_t bnx2x_wait_sp_comp(struct bnx2x_softc *sc, unsigned long mask)
1755 {
1756         unsigned long tmp;
1757         int tout = 5000;        /* wait for 5 secs tops */
1758
1759         while (tout--) {
1760                 mb();
1761                 if (!(atomic_load_acq_long(&sc->sp_state) & mask)) {
1762                         return TRUE;
1763                 }
1764
1765                 DELAY(1000);
1766         }
1767
1768         mb();
1769
1770         tmp = atomic_load_acq_long(&sc->sp_state);
1771         if (tmp & mask) {
1772                 PMD_DRV_LOG(INFO, sc, "Filtering completion timed out: "
1773                             "sp_state 0x%lx, mask 0x%lx", tmp, mask);
1774                 return FALSE;
1775         }
1776
1777         return FALSE;
1778 }
1779
1780 static int bnx2x_func_stop(struct bnx2x_softc *sc)
1781 {
1782         struct ecore_func_state_params func_params = { NULL };
1783         int rc;
1784
1785         /* prepare parameters for function state transitions */
1786         bnx2x_set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags);
1787         func_params.f_obj = &sc->func_obj;
1788         func_params.cmd = ECORE_F_CMD_STOP;
1789
1790         /*
1791          * Try to stop the function the 'good way'. If it fails (in case
1792          * of a parity error during bnx2x_chip_cleanup()) and we are
1793          * not in a debug mode, perform a state transaction in order to
1794          * enable further HW_RESET transaction.
1795          */
1796         rc = ecore_func_state_change(sc, &func_params);
1797         if (rc) {
1798                 PMD_DRV_LOG(NOTICE, sc, "FUNC_STOP ramrod failed. "
1799                             "Running a dry transaction");
1800                 bnx2x_set_bit(RAMROD_DRV_CLR_ONLY, &func_params.ramrod_flags);
1801                 return ecore_func_state_change(sc, &func_params);
1802         }
1803
1804         return 0;
1805 }
1806
1807 static int bnx2x_reset_hw(struct bnx2x_softc *sc, uint32_t load_code)
1808 {
1809         struct ecore_func_state_params func_params = { NULL };
1810
1811         /* Prepare parameters for function state transitions */
1812         bnx2x_set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags);
1813
1814         func_params.f_obj = &sc->func_obj;
1815         func_params.cmd = ECORE_F_CMD_HW_RESET;
1816
1817         func_params.params.hw_init.load_phase = load_code;
1818
1819         return ecore_func_state_change(sc, &func_params);
1820 }
1821
1822 static void bnx2x_int_disable_sync(struct bnx2x_softc *sc, int disable_hw)
1823 {
1824         if (disable_hw) {
1825                 /* prevent the HW from sending interrupts */
1826                 bnx2x_int_disable(sc);
1827         }
1828 }
1829
1830 static void
1831 bnx2x_chip_cleanup(struct bnx2x_softc *sc, uint32_t unload_mode, uint8_t keep_link)
1832 {
1833         int port = SC_PORT(sc);
1834         struct ecore_mcast_ramrod_params rparam = { NULL };
1835         uint32_t reset_code;
1836         int i, rc = 0;
1837
1838         bnx2x_drain_tx_queues(sc);
1839
1840         /* give HW time to discard old tx messages */
1841         DELAY(1000);
1842
1843         /* Clean all ETH MACs */
1844         rc = bnx2x_del_all_macs(sc, &sc->sp_objs[0].mac_obj, ECORE_ETH_MAC,
1845                               FALSE);
1846         if (rc < 0) {
1847                 PMD_DRV_LOG(NOTICE, sc,
1848                             "Failed to delete all ETH MACs (%d)", rc);
1849         }
1850
1851         /* Clean up UC list  */
1852         rc = bnx2x_del_all_macs(sc, &sc->sp_objs[0].mac_obj, ECORE_UC_LIST_MAC,
1853                               TRUE);
1854         if (rc < 0) {
1855                 PMD_DRV_LOG(NOTICE, sc,
1856                             "Failed to delete UC MACs list (%d)", rc);
1857         }
1858
1859         /* Disable LLH */
1860         REG_WR(sc, NIG_REG_LLH0_FUNC_EN + port * 8, 0);
1861
1862         /* Set "drop all" to stop Rx */
1863
1864         /*
1865          * We need to take the if_maddr_lock() here in order to prevent
1866          * a race between the completion code and this code.
1867          */
1868
1869         if (bnx2x_test_bit(ECORE_FILTER_RX_MODE_PENDING, &sc->sp_state)) {
1870                 bnx2x_set_bit(ECORE_FILTER_RX_MODE_SCHED, &sc->sp_state);
1871         } else {
1872                 bnx2x_set_storm_rx_mode(sc);
1873         }
1874
1875         /* Clean up multicast configuration */
1876         rparam.mcast_obj = &sc->mcast_obj;
1877         rc = ecore_config_mcast(sc, &rparam, ECORE_MCAST_CMD_DEL);
1878         if (rc < 0) {
1879                 PMD_DRV_LOG(NOTICE, sc,
1880                             "Failed to send DEL MCAST command (%d)", rc);
1881         }
1882
1883         /*
1884          * Send the UNLOAD_REQUEST to the MCP. This will return if
1885          * this function should perform FUNCTION, PORT, or COMMON HW
1886          * reset.
1887          */
1888         reset_code = bnx2x_send_unload_req(sc, unload_mode);
1889
1890         /*
1891          * (assumption: No Attention from MCP at this stage)
1892          * PMF probably in the middle of TX disable/enable transaction
1893          */
1894         rc = bnx2x_func_wait_started(sc);
1895         if (rc) {
1896                 PMD_DRV_LOG(NOTICE, sc, "bnx2x_func_wait_started failed");
1897         }
1898
1899         /*
1900          * Close multi and leading connections
1901          * Completions for ramrods are collected in a synchronous way
1902          */
1903         for (i = 0; i < sc->num_queues; i++) {
1904                 if (bnx2x_stop_queue(sc, i)) {
1905                         goto unload_error;
1906                 }
1907         }
1908
1909         /*
1910          * If SP settings didn't get completed so far - something
1911          * very wrong has happen.
1912          */
1913         if (!bnx2x_wait_sp_comp(sc, ~0x0UL)) {
1914                 PMD_DRV_LOG(NOTICE, sc, "Common slow path ramrods got stuck!");
1915         }
1916
1917 unload_error:
1918
1919         rc = bnx2x_func_stop(sc);
1920         if (rc) {
1921                 PMD_DRV_LOG(NOTICE, sc, "Function stop failed!");
1922         }
1923
1924         /* disable HW interrupts */
1925         bnx2x_int_disable_sync(sc, TRUE);
1926
1927         /* Reset the chip */
1928         rc = bnx2x_reset_hw(sc, reset_code);
1929         if (rc) {
1930                 PMD_DRV_LOG(NOTICE, sc, "Hardware reset failed");
1931         }
1932
1933         /* Report UNLOAD_DONE to MCP */
1934         bnx2x_send_unload_done(sc, keep_link);
1935 }
1936
1937 static void bnx2x_disable_close_the_gate(struct bnx2x_softc *sc)
1938 {
1939         uint32_t val;
1940
1941         PMD_DRV_LOG(DEBUG, sc, "Disabling 'close the gates'");
1942
1943         val = REG_RD(sc, MISC_REG_AEU_GENERAL_MASK);
1944         val &= ~(MISC_AEU_GENERAL_MASK_REG_AEU_PXP_CLOSE_MASK |
1945                  MISC_AEU_GENERAL_MASK_REG_AEU_NIG_CLOSE_MASK);
1946         REG_WR(sc, MISC_REG_AEU_GENERAL_MASK, val);
1947 }
1948
1949 /*
1950  * Cleans the object that have internal lists without sending
1951  * ramrods. Should be run when interrutps are disabled.
1952  */
1953 static void bnx2x_squeeze_objects(struct bnx2x_softc *sc)
1954 {
1955         unsigned long ramrod_flags = 0, vlan_mac_flags = 0;
1956         struct ecore_mcast_ramrod_params rparam = { NULL };
1957         struct ecore_vlan_mac_obj *mac_obj = &sc->sp_objs->mac_obj;
1958         int rc;
1959
1960         /* Cleanup MACs' object first... */
1961
1962         /* Wait for completion of requested */
1963         bnx2x_set_bit(RAMROD_COMP_WAIT, &ramrod_flags);
1964         /* Perform a dry cleanup */
1965         bnx2x_set_bit(RAMROD_DRV_CLR_ONLY, &ramrod_flags);
1966
1967         /* Clean ETH primary MAC */
1968         bnx2x_set_bit(ECORE_ETH_MAC, &vlan_mac_flags);
1969         rc = mac_obj->delete_all(sc, &sc->sp_objs->mac_obj, &vlan_mac_flags,
1970                                  &ramrod_flags);
1971         if (rc != 0) {
1972                 PMD_DRV_LOG(NOTICE, sc, "Failed to clean ETH MACs (%d)", rc);
1973         }
1974
1975         /* Cleanup UC list */
1976         vlan_mac_flags = 0;
1977         bnx2x_set_bit(ECORE_UC_LIST_MAC, &vlan_mac_flags);
1978         rc = mac_obj->delete_all(sc, mac_obj, &vlan_mac_flags, &ramrod_flags);
1979         if (rc != 0) {
1980                 PMD_DRV_LOG(NOTICE, sc,
1981                             "Failed to clean UC list MACs (%d)", rc);
1982         }
1983
1984         /* Now clean mcast object... */
1985
1986         rparam.mcast_obj = &sc->mcast_obj;
1987         bnx2x_set_bit(RAMROD_DRV_CLR_ONLY, &rparam.ramrod_flags);
1988
1989         /* Add a DEL command... */
1990         rc = ecore_config_mcast(sc, &rparam, ECORE_MCAST_CMD_DEL);
1991         if (rc < 0) {
1992                 PMD_DRV_LOG(NOTICE, sc,
1993                             "Failed to send DEL MCAST command (%d)", rc);
1994         }
1995
1996         /* now wait until all pending commands are cleared */
1997
1998         rc = ecore_config_mcast(sc, &rparam, ECORE_MCAST_CMD_CONT);
1999         while (rc != 0) {
2000                 if (rc < 0) {
2001                         PMD_DRV_LOG(NOTICE, sc,
2002                                     "Failed to clean MCAST object (%d)", rc);
2003                         return;
2004                 }
2005
2006                 rc = ecore_config_mcast(sc, &rparam, ECORE_MCAST_CMD_CONT);
2007         }
2008 }
2009
2010 /* stop the controller */
2011 __rte_noinline
2012 int
2013 bnx2x_nic_unload(struct bnx2x_softc *sc, uint32_t unload_mode, uint8_t keep_link)
2014 {
2015         uint8_t global = FALSE;
2016         uint32_t val;
2017
2018         PMD_DRV_LOG(DEBUG, sc, "Starting NIC unload...");
2019
2020         /* mark driver as unloaded in shmem2 */
2021         if (IS_PF(sc) && SHMEM2_HAS(sc, drv_capabilities_flag)) {
2022                 val = SHMEM2_RD(sc, drv_capabilities_flag[SC_FW_MB_IDX(sc)]);
2023                 SHMEM2_WR(sc, drv_capabilities_flag[SC_FW_MB_IDX(sc)],
2024                           val & ~DRV_FLAGS_CAPABILITIES_LOADED_L2);
2025         }
2026
2027         if (IS_PF(sc) && sc->recovery_state != BNX2X_RECOVERY_DONE &&
2028             (sc->state == BNX2X_STATE_CLOSED || sc->state == BNX2X_STATE_ERROR)) {
2029                 /*
2030                  * We can get here if the driver has been unloaded
2031                  * during parity error recovery and is either waiting for a
2032                  * leader to complete or for other functions to unload and
2033                  * then ifconfig down has been issued. In this case we want to
2034                  * unload and let other functions to complete a recovery
2035                  * process.
2036                  */
2037                 sc->recovery_state = BNX2X_RECOVERY_DONE;
2038                 sc->is_leader = 0;
2039                 bnx2x_release_leader_lock(sc);
2040                 mb();
2041
2042                 PMD_DRV_LOG(NOTICE, sc, "Can't unload in closed or error state");
2043                 return -1;
2044         }
2045
2046         /*
2047          * Nothing to do during unload if previous bnx2x_nic_load()
2048          * did not completed successfully - all resourses are released.
2049          */
2050         if ((sc->state == BNX2X_STATE_CLOSED) || (sc->state == BNX2X_STATE_ERROR)) {
2051                 return 0;
2052         }
2053
2054         sc->state = BNX2X_STATE_CLOSING_WAITING_HALT;
2055         mb();
2056
2057         sc->rx_mode = BNX2X_RX_MODE_NONE;
2058         bnx2x_set_rx_mode(sc);
2059         mb();
2060
2061         if (IS_PF(sc)) {
2062                 /* set ALWAYS_ALIVE bit in shmem */
2063                 sc->fw_drv_pulse_wr_seq |= DRV_PULSE_ALWAYS_ALIVE;
2064
2065                 bnx2x_drv_pulse(sc);
2066
2067                 bnx2x_stats_handle(sc, STATS_EVENT_STOP);
2068                 bnx2x_save_statistics(sc);
2069         }
2070
2071         /* wait till consumers catch up with producers in all queues */
2072         bnx2x_drain_tx_queues(sc);
2073
2074         /* if VF indicate to PF this function is going down (PF will delete sp
2075          * elements and clear initializations
2076          */
2077         if (IS_VF(sc)) {
2078                 bnx2x_vf_unload(sc);
2079         } else if (unload_mode != UNLOAD_RECOVERY) {
2080                 /* if this is a normal/close unload need to clean up chip */
2081                 bnx2x_chip_cleanup(sc, unload_mode, keep_link);
2082         } else {
2083                 /* Send the UNLOAD_REQUEST to the MCP */
2084                 bnx2x_send_unload_req(sc, unload_mode);
2085
2086                 /*
2087                  * Prevent transactions to host from the functions on the
2088                  * engine that doesn't reset global blocks in case of global
2089                  * attention once gloabl blocks are reset and gates are opened
2090                  * (the engine which leader will perform the recovery
2091                  * last).
2092                  */
2093                 if (!CHIP_IS_E1x(sc)) {
2094                         bnx2x_pf_disable(sc);
2095                 }
2096
2097                 /* disable HW interrupts */
2098                 bnx2x_int_disable_sync(sc, TRUE);
2099
2100                 /* Report UNLOAD_DONE to MCP */
2101                 bnx2x_send_unload_done(sc, FALSE);
2102         }
2103
2104         /*
2105          * At this stage no more interrupts will arrive so we may safely clean
2106          * the queue'able objects here in case they failed to get cleaned so far.
2107          */
2108         if (IS_PF(sc)) {
2109                 bnx2x_squeeze_objects(sc);
2110         }
2111
2112         /* There should be no more pending SP commands at this stage */
2113         sc->sp_state = 0;
2114
2115         sc->port.pmf = 0;
2116
2117         if (IS_PF(sc)) {
2118                 bnx2x_free_mem(sc);
2119         }
2120
2121         bnx2x_free_fw_stats_mem(sc);
2122
2123         sc->state = BNX2X_STATE_CLOSED;
2124
2125         /*
2126          * Check if there are pending parity attentions. If there are - set
2127          * RECOVERY_IN_PROGRESS.
2128          */
2129         if (IS_PF(sc) && bnx2x_chk_parity_attn(sc, &global, FALSE)) {
2130                 bnx2x_set_reset_in_progress(sc);
2131
2132                 /* Set RESET_IS_GLOBAL if needed */
2133                 if (global) {
2134                         bnx2x_set_reset_global(sc);
2135                 }
2136         }
2137
2138         /*
2139          * The last driver must disable a "close the gate" if there is no
2140          * parity attention or "process kill" pending.
2141          */
2142         if (IS_PF(sc) && !bnx2x_clear_pf_load(sc) &&
2143             bnx2x_reset_is_done(sc, SC_PATH(sc))) {
2144                 bnx2x_disable_close_the_gate(sc);
2145         }
2146
2147         PMD_DRV_LOG(DEBUG, sc, "Ended NIC unload");
2148
2149         return 0;
2150 }
2151
2152 /*
2153  * Encapsulte an mbuf cluster into the tx bd chain and makes the memory
2154  * visible to the controller.
2155  *
2156  * If an mbuf is submitted to this routine and cannot be given to the
2157  * controller (e.g. it has too many fragments) then the function may free
2158  * the mbuf and return to the caller.
2159  *
2160  * Returns:
2161  *     int: Number of TX BDs used for the mbuf
2162  *
2163  *   Note the side effect that an mbuf may be freed if it causes a problem.
2164  */
2165 int bnx2x_tx_encap(struct bnx2x_tx_queue *txq, struct rte_mbuf *m0)
2166 {
2167         struct eth_tx_start_bd *tx_start_bd;
2168         uint16_t bd_prod, pkt_prod;
2169         struct bnx2x_softc *sc;
2170         uint32_t nbds = 0;
2171
2172         sc = txq->sc;
2173         bd_prod = txq->tx_bd_tail;
2174         pkt_prod = txq->tx_pkt_tail;
2175
2176         txq->sw_ring[TX_BD(pkt_prod, txq)] = m0;
2177
2178         tx_start_bd = &txq->tx_ring[TX_BD(bd_prod, txq)].start_bd;
2179
2180         tx_start_bd->addr =
2181             rte_cpu_to_le_64(rte_mbuf_data_iova(m0));
2182         tx_start_bd->nbytes = rte_cpu_to_le_16(m0->data_len);
2183         tx_start_bd->bd_flags.as_bitfield = ETH_TX_BD_FLAGS_START_BD;
2184         tx_start_bd->general_data =
2185             (1 << ETH_TX_START_BD_HDR_NBDS_SHIFT);
2186
2187         tx_start_bd->nbd = rte_cpu_to_le_16(2);
2188
2189         if (m0->ol_flags & PKT_TX_VLAN_PKT) {
2190                 tx_start_bd->vlan_or_ethertype =
2191                     rte_cpu_to_le_16(m0->vlan_tci);
2192                 tx_start_bd->bd_flags.as_bitfield |=
2193                     (X_ETH_OUTBAND_VLAN <<
2194                      ETH_TX_BD_FLAGS_VLAN_MODE_SHIFT);
2195         } else {
2196                 if (IS_PF(sc))
2197                         tx_start_bd->vlan_or_ethertype =
2198                             rte_cpu_to_le_16(pkt_prod);
2199                 else {
2200                         struct rte_ether_hdr *eh =
2201                             rte_pktmbuf_mtod(m0, struct rte_ether_hdr *);
2202
2203                         tx_start_bd->vlan_or_ethertype =
2204                             rte_cpu_to_le_16(rte_be_to_cpu_16(eh->ether_type));
2205                 }
2206         }
2207
2208         bd_prod = NEXT_TX_BD(bd_prod);
2209         if (IS_VF(sc)) {
2210                 struct eth_tx_parse_bd_e2 *tx_parse_bd;
2211                 const struct rte_ether_hdr *eh =
2212                     rte_pktmbuf_mtod(m0, struct rte_ether_hdr *);
2213                 uint8_t mac_type = UNICAST_ADDRESS;
2214
2215                 tx_parse_bd =
2216                     &txq->tx_ring[TX_BD(bd_prod, txq)].parse_bd_e2;
2217                 if (rte_is_multicast_ether_addr(&eh->d_addr)) {
2218                         if (rte_is_broadcast_ether_addr(&eh->d_addr))
2219                                 mac_type = BROADCAST_ADDRESS;
2220                         else
2221                                 mac_type = MULTICAST_ADDRESS;
2222                 }
2223                 tx_parse_bd->parsing_data =
2224                     (mac_type << ETH_TX_PARSE_BD_E2_ETH_ADDR_TYPE_SHIFT);
2225
2226                 rte_memcpy(&tx_parse_bd->data.mac_addr.dst_hi,
2227                            &eh->d_addr.addr_bytes[0], 2);
2228                 rte_memcpy(&tx_parse_bd->data.mac_addr.dst_mid,
2229                            &eh->d_addr.addr_bytes[2], 2);
2230                 rte_memcpy(&tx_parse_bd->data.mac_addr.dst_lo,
2231                            &eh->d_addr.addr_bytes[4], 2);
2232                 rte_memcpy(&tx_parse_bd->data.mac_addr.src_hi,
2233                            &eh->s_addr.addr_bytes[0], 2);
2234                 rte_memcpy(&tx_parse_bd->data.mac_addr.src_mid,
2235                            &eh->s_addr.addr_bytes[2], 2);
2236                 rte_memcpy(&tx_parse_bd->data.mac_addr.src_lo,
2237                            &eh->s_addr.addr_bytes[4], 2);
2238
2239                 tx_parse_bd->data.mac_addr.dst_hi =
2240                     rte_cpu_to_be_16(tx_parse_bd->data.mac_addr.dst_hi);
2241                 tx_parse_bd->data.mac_addr.dst_mid =
2242                     rte_cpu_to_be_16(tx_parse_bd->data.
2243                                      mac_addr.dst_mid);
2244                 tx_parse_bd->data.mac_addr.dst_lo =
2245                     rte_cpu_to_be_16(tx_parse_bd->data.mac_addr.dst_lo);
2246                 tx_parse_bd->data.mac_addr.src_hi =
2247                     rte_cpu_to_be_16(tx_parse_bd->data.mac_addr.src_hi);
2248                 tx_parse_bd->data.mac_addr.src_mid =
2249                     rte_cpu_to_be_16(tx_parse_bd->data.
2250                                      mac_addr.src_mid);
2251                 tx_parse_bd->data.mac_addr.src_lo =
2252                     rte_cpu_to_be_16(tx_parse_bd->data.mac_addr.src_lo);
2253
2254                 PMD_TX_LOG(DEBUG,
2255                            "PBD dst %x %x %x src %x %x %x p_data %x",
2256                            tx_parse_bd->data.mac_addr.dst_hi,
2257                            tx_parse_bd->data.mac_addr.dst_mid,
2258                            tx_parse_bd->data.mac_addr.dst_lo,
2259                            tx_parse_bd->data.mac_addr.src_hi,
2260                            tx_parse_bd->data.mac_addr.src_mid,
2261                            tx_parse_bd->data.mac_addr.src_lo,
2262                            tx_parse_bd->parsing_data);
2263         }
2264
2265         PMD_TX_LOG(DEBUG,
2266                    "start bd: nbytes %d flags %x vlan %x",
2267                    tx_start_bd->nbytes,
2268                    tx_start_bd->bd_flags.as_bitfield,
2269                    tx_start_bd->vlan_or_ethertype);
2270
2271         bd_prod = NEXT_TX_BD(bd_prod);
2272         pkt_prod++;
2273
2274         if (TX_IDX(bd_prod) < 2)
2275                 nbds++;
2276
2277         txq->nb_tx_avail -= 2;
2278         txq->tx_bd_tail = bd_prod;
2279         txq->tx_pkt_tail = pkt_prod;
2280
2281         return nbds + 2;
2282 }
2283
2284 static uint16_t bnx2x_cid_ilt_lines(struct bnx2x_softc *sc)
2285 {
2286         return L2_ILT_LINES(sc);
2287 }
2288
2289 static void bnx2x_ilt_set_info(struct bnx2x_softc *sc)
2290 {
2291         struct ilt_client_info *ilt_client;
2292         struct ecore_ilt *ilt = sc->ilt;
2293         uint16_t line = 0;
2294
2295         PMD_INIT_FUNC_TRACE(sc);
2296
2297         ilt->start_line = FUNC_ILT_BASE(SC_FUNC(sc));
2298
2299         /* CDU */
2300         ilt_client = &ilt->clients[ILT_CLIENT_CDU];
2301         ilt_client->client_num = ILT_CLIENT_CDU;
2302         ilt_client->page_size = CDU_ILT_PAGE_SZ;
2303         ilt_client->flags = ILT_CLIENT_SKIP_MEM;
2304         ilt_client->start = line;
2305         line += bnx2x_cid_ilt_lines(sc);
2306
2307         if (CNIC_SUPPORT(sc)) {
2308                 line += CNIC_ILT_LINES;
2309         }
2310
2311         ilt_client->end = (line - 1);
2312
2313         /* QM */
2314         if (QM_INIT(sc->qm_cid_count)) {
2315                 ilt_client = &ilt->clients[ILT_CLIENT_QM];
2316                 ilt_client->client_num = ILT_CLIENT_QM;
2317                 ilt_client->page_size = QM_ILT_PAGE_SZ;
2318                 ilt_client->flags = 0;
2319                 ilt_client->start = line;
2320
2321                 /* 4 bytes for each cid */
2322                 line += DIV_ROUND_UP(sc->qm_cid_count * QM_QUEUES_PER_FUNC * 4,
2323                                      QM_ILT_PAGE_SZ);
2324
2325                 ilt_client->end = (line - 1);
2326         }
2327
2328         if (CNIC_SUPPORT(sc)) {
2329                 /* SRC */
2330                 ilt_client = &ilt->clients[ILT_CLIENT_SRC];
2331                 ilt_client->client_num = ILT_CLIENT_SRC;
2332                 ilt_client->page_size = SRC_ILT_PAGE_SZ;
2333                 ilt_client->flags = 0;
2334                 ilt_client->start = line;
2335                 line += SRC_ILT_LINES;
2336                 ilt_client->end = (line - 1);
2337
2338                 /* TM */
2339                 ilt_client = &ilt->clients[ILT_CLIENT_TM];
2340                 ilt_client->client_num = ILT_CLIENT_TM;
2341                 ilt_client->page_size = TM_ILT_PAGE_SZ;
2342                 ilt_client->flags = 0;
2343                 ilt_client->start = line;
2344                 line += TM_ILT_LINES;
2345                 ilt_client->end = (line - 1);
2346         }
2347
2348         assert((line <= ILT_MAX_LINES));
2349 }
2350
2351 static void bnx2x_set_fp_rx_buf_size(struct bnx2x_softc *sc)
2352 {
2353         int i;
2354
2355         for (i = 0; i < sc->num_queues; i++) {
2356                 /* get the Rx buffer size for RX frames */
2357                 sc->fp[i].rx_buf_size =
2358                     (IP_HEADER_ALIGNMENT_PADDING + ETH_OVERHEAD + sc->mtu);
2359         }
2360 }
2361
2362 int bnx2x_alloc_ilt_mem(struct bnx2x_softc *sc)
2363 {
2364
2365         sc->ilt = rte_malloc("", sizeof(struct ecore_ilt), RTE_CACHE_LINE_SIZE);
2366
2367         return sc->ilt == NULL;
2368 }
2369
2370 static int bnx2x_alloc_ilt_lines_mem(struct bnx2x_softc *sc)
2371 {
2372         sc->ilt->lines = rte_calloc("",
2373                                     sizeof(struct ilt_line), ILT_MAX_LINES,
2374                                     RTE_CACHE_LINE_SIZE);
2375         return sc->ilt->lines == NULL;
2376 }
2377
2378 void bnx2x_free_ilt_mem(struct bnx2x_softc *sc)
2379 {
2380         rte_free(sc->ilt);
2381         sc->ilt = NULL;
2382 }
2383
2384 static void bnx2x_free_ilt_lines_mem(struct bnx2x_softc *sc)
2385 {
2386         if (sc->ilt->lines != NULL) {
2387                 rte_free(sc->ilt->lines);
2388                 sc->ilt->lines = NULL;
2389         }
2390 }
2391
2392 static void bnx2x_free_mem(struct bnx2x_softc *sc)
2393 {
2394         uint32_t i;
2395
2396         for (i = 0; i < L2_ILT_LINES(sc); i++) {
2397                 sc->context[i].vcxt = NULL;
2398                 sc->context[i].size = 0;
2399         }
2400
2401         ecore_ilt_mem_op(sc, ILT_MEMOP_FREE);
2402
2403         bnx2x_free_ilt_lines_mem(sc);
2404
2405         /* free the host hardware/software hsi structures */
2406         bnx2x_free_hsi_mem(sc);
2407 }
2408
2409 static int bnx2x_alloc_mem(struct bnx2x_softc *sc)
2410 {
2411         int context_size;
2412         int allocated;
2413         int i;
2414         char cdu_name[RTE_MEMZONE_NAMESIZE];
2415
2416         /*
2417          * Allocate memory for CDU context:
2418          * This memory is allocated separately and not in the generic ILT
2419          * functions because CDU differs in few aspects:
2420          * 1. There can be multiple entities allocating memory for context -
2421          * regular L2, CNIC, and SRIOV drivers. Each separately controls
2422          * its own ILT lines.
2423          * 2. Since CDU page-size is not a single 4KB page (which is the case
2424          * for the other ILT clients), to be efficient we want to support
2425          * allocation of sub-page-size in the last entry.
2426          * 3. Context pointers are used by the driver to pass to FW / update
2427          * the context (for the other ILT clients the pointers are used just to
2428          * free the memory during unload).
2429          */
2430         context_size = (sizeof(union cdu_context) * BNX2X_L2_CID_COUNT(sc));
2431         for (i = 0, allocated = 0; allocated < context_size; i++) {
2432                 sc->context[i].size = min(CDU_ILT_PAGE_SZ,
2433                                           (context_size - allocated));
2434
2435                 snprintf(cdu_name, sizeof(cdu_name), "cdu_%d", i);
2436                 if (bnx2x_dma_alloc(sc, sc->context[i].size,
2437                                   &sc->context[i].vcxt_dma,
2438                                   cdu_name, BNX2X_PAGE_SIZE) != 0) {
2439                         bnx2x_free_mem(sc);
2440                         return -1;
2441                 }
2442
2443                 sc->context[i].vcxt =
2444                     (union cdu_context *)sc->context[i].vcxt_dma.vaddr;
2445
2446                 allocated += sc->context[i].size;
2447         }
2448
2449         bnx2x_alloc_ilt_lines_mem(sc);
2450
2451         if (ecore_ilt_mem_op(sc, ILT_MEMOP_ALLOC)) {
2452                 PMD_DRV_LOG(NOTICE, sc, "ecore_ilt_mem_op ILT_MEMOP_ALLOC failed");
2453                 bnx2x_free_mem(sc);
2454                 return -1;
2455         }
2456
2457         /* allocate the host hardware/software hsi structures */
2458         if (bnx2x_alloc_hsi_mem(sc) != 0) {
2459                 PMD_DRV_LOG(ERR, sc, "bnx2x_alloc_hsi_mem was failed");
2460                 bnx2x_free_mem(sc);
2461                 return -ENXIO;
2462         }
2463
2464         return 0;
2465 }
2466
2467 static void bnx2x_free_fw_stats_mem(struct bnx2x_softc *sc)
2468 {
2469         bnx2x_dma_free(&sc->fw_stats_dma);
2470         sc->fw_stats_num = 0;
2471
2472         sc->fw_stats_req_size = 0;
2473         sc->fw_stats_req = NULL;
2474         sc->fw_stats_req_mapping = 0;
2475
2476         sc->fw_stats_data_size = 0;
2477         sc->fw_stats_data = NULL;
2478         sc->fw_stats_data_mapping = 0;
2479 }
2480
2481 static int bnx2x_alloc_fw_stats_mem(struct bnx2x_softc *sc)
2482 {
2483         uint8_t num_queue_stats;
2484         int num_groups, vf_headroom = 0;
2485
2486         /* number of queues for statistics is number of eth queues */
2487         num_queue_stats = BNX2X_NUM_ETH_QUEUES(sc);
2488
2489         /*
2490          * Total number of FW statistics requests =
2491          *   1 for port stats + 1 for PF stats + num of queues
2492          */
2493         sc->fw_stats_num = (2 + num_queue_stats);
2494
2495         /*
2496          * Request is built from stats_query_header and an array of
2497          * stats_query_cmd_group each of which contains STATS_QUERY_CMD_COUNT
2498          * rules. The real number or requests is configured in the
2499          * stats_query_header.
2500          */
2501         num_groups = (sc->fw_stats_num + vf_headroom) / STATS_QUERY_CMD_COUNT;
2502         if ((sc->fw_stats_num + vf_headroom) % STATS_QUERY_CMD_COUNT)
2503                 num_groups++;
2504
2505         sc->fw_stats_req_size =
2506             (sizeof(struct stats_query_header) +
2507              (num_groups * sizeof(struct stats_query_cmd_group)));
2508
2509         /*
2510          * Data for statistics requests + stats_counter.
2511          * stats_counter holds per-STORM counters that are incremented when
2512          * STORM has finished with the current request. Memory for FCoE
2513          * offloaded statistics are counted anyway, even if they will not be sent.
2514          * VF stats are not accounted for here as the data of VF stats is stored
2515          * in memory allocated by the VF, not here.
2516          */
2517         sc->fw_stats_data_size =
2518             (sizeof(struct stats_counter) +
2519              sizeof(struct per_port_stats) + sizeof(struct per_pf_stats) +
2520              /* sizeof(struct fcoe_statistics_params) + */
2521              (sizeof(struct per_queue_stats) * num_queue_stats));
2522
2523         if (bnx2x_dma_alloc(sc, (sc->fw_stats_req_size + sc->fw_stats_data_size),
2524                           &sc->fw_stats_dma, "fw_stats",
2525                           RTE_CACHE_LINE_SIZE) != 0) {
2526                 bnx2x_free_fw_stats_mem(sc);
2527                 return -1;
2528         }
2529
2530         /* set up the shortcuts */
2531
2532         sc->fw_stats_req = (struct bnx2x_fw_stats_req *)sc->fw_stats_dma.vaddr;
2533         sc->fw_stats_req_mapping = sc->fw_stats_dma.paddr;
2534
2535         sc->fw_stats_data =
2536             (struct bnx2x_fw_stats_data *)((uint8_t *) sc->fw_stats_dma.vaddr +
2537                                          sc->fw_stats_req_size);
2538         sc->fw_stats_data_mapping = (sc->fw_stats_dma.paddr +
2539                                      sc->fw_stats_req_size);
2540
2541         return 0;
2542 }
2543
2544 /*
2545  * Bits map:
2546  * 0-7  - Engine0 load counter.
2547  * 8-15 - Engine1 load counter.
2548  * 16   - Engine0 RESET_IN_PROGRESS bit.
2549  * 17   - Engine1 RESET_IN_PROGRESS bit.
2550  * 18   - Engine0 ONE_IS_LOADED. Set when there is at least one active
2551  *        function on the engine
2552  * 19   - Engine1 ONE_IS_LOADED.
2553  * 20   - Chip reset flow bit. When set none-leader must wait for both engines
2554  *        leader to complete (check for both RESET_IN_PROGRESS bits and not
2555  *        for just the one belonging to its engine).
2556  */
2557 #define BNX2X_RECOVERY_GLOB_REG     MISC_REG_GENERIC_POR_1
2558 #define BNX2X_PATH0_LOAD_CNT_MASK   0x000000ff
2559 #define BNX2X_PATH0_LOAD_CNT_SHIFT  0
2560 #define BNX2X_PATH1_LOAD_CNT_MASK   0x0000ff00
2561 #define BNX2X_PATH1_LOAD_CNT_SHIFT  8
2562 #define BNX2X_PATH0_RST_IN_PROG_BIT 0x00010000
2563 #define BNX2X_PATH1_RST_IN_PROG_BIT 0x00020000
2564 #define BNX2X_GLOBAL_RESET_BIT      0x00040000
2565
2566 /* set the GLOBAL_RESET bit, should be run under rtnl lock */
2567 static void bnx2x_set_reset_global(struct bnx2x_softc *sc)
2568 {
2569         uint32_t val;
2570         bnx2x_acquire_hw_lock(sc, HW_LOCK_RESOURCE_RECOVERY_REG);
2571         val = REG_RD(sc, BNX2X_RECOVERY_GLOB_REG);
2572         REG_WR(sc, BNX2X_RECOVERY_GLOB_REG, val | BNX2X_GLOBAL_RESET_BIT);
2573         bnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_RECOVERY_REG);
2574 }
2575
2576 /* clear the GLOBAL_RESET bit, should be run under rtnl lock */
2577 static void bnx2x_clear_reset_global(struct bnx2x_softc *sc)
2578 {
2579         uint32_t val;
2580         bnx2x_acquire_hw_lock(sc, HW_LOCK_RESOURCE_RECOVERY_REG);
2581         val = REG_RD(sc, BNX2X_RECOVERY_GLOB_REG);
2582         REG_WR(sc, BNX2X_RECOVERY_GLOB_REG, val & (~BNX2X_GLOBAL_RESET_BIT));
2583         bnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_RECOVERY_REG);
2584 }
2585
2586 /* checks the GLOBAL_RESET bit, should be run under rtnl lock */
2587 static uint8_t bnx2x_reset_is_global(struct bnx2x_softc *sc)
2588 {
2589         return REG_RD(sc, BNX2X_RECOVERY_GLOB_REG) & BNX2X_GLOBAL_RESET_BIT;
2590 }
2591
2592 /* clear RESET_IN_PROGRESS bit for the engine, should be run under rtnl lock */
2593 static void bnx2x_set_reset_done(struct bnx2x_softc *sc)
2594 {
2595         uint32_t val;
2596         uint32_t bit = SC_PATH(sc) ? BNX2X_PATH1_RST_IN_PROG_BIT :
2597             BNX2X_PATH0_RST_IN_PROG_BIT;
2598
2599         bnx2x_acquire_hw_lock(sc, HW_LOCK_RESOURCE_RECOVERY_REG);
2600
2601         val = REG_RD(sc, BNX2X_RECOVERY_GLOB_REG);
2602         /* Clear the bit */
2603         val &= ~bit;
2604         REG_WR(sc, BNX2X_RECOVERY_GLOB_REG, val);
2605
2606         bnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_RECOVERY_REG);
2607 }
2608
2609 /* set RESET_IN_PROGRESS for the engine, should be run under rtnl lock */
2610 static void bnx2x_set_reset_in_progress(struct bnx2x_softc *sc)
2611 {
2612         uint32_t val;
2613         uint32_t bit = SC_PATH(sc) ? BNX2X_PATH1_RST_IN_PROG_BIT :
2614             BNX2X_PATH0_RST_IN_PROG_BIT;
2615
2616         bnx2x_acquire_hw_lock(sc, HW_LOCK_RESOURCE_RECOVERY_REG);
2617
2618         val = REG_RD(sc, BNX2X_RECOVERY_GLOB_REG);
2619         /* Set the bit */
2620         val |= bit;
2621         REG_WR(sc, BNX2X_RECOVERY_GLOB_REG, val);
2622
2623         bnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_RECOVERY_REG);
2624 }
2625
2626 /* check RESET_IN_PROGRESS bit for an engine, should be run under rtnl lock */
2627 static uint8_t bnx2x_reset_is_done(struct bnx2x_softc *sc, int engine)
2628 {
2629         uint32_t val = REG_RD(sc, BNX2X_RECOVERY_GLOB_REG);
2630         uint32_t bit = engine ? BNX2X_PATH1_RST_IN_PROG_BIT :
2631             BNX2X_PATH0_RST_IN_PROG_BIT;
2632
2633         /* return false if bit is set */
2634         return (val & bit) ? FALSE : TRUE;
2635 }
2636
2637 /* get the load status for an engine, should be run under rtnl lock */
2638 static uint8_t bnx2x_get_load_status(struct bnx2x_softc *sc, int engine)
2639 {
2640         uint32_t mask = engine ? BNX2X_PATH1_LOAD_CNT_MASK :
2641             BNX2X_PATH0_LOAD_CNT_MASK;
2642         uint32_t shift = engine ? BNX2X_PATH1_LOAD_CNT_SHIFT :
2643             BNX2X_PATH0_LOAD_CNT_SHIFT;
2644         uint32_t val = REG_RD(sc, BNX2X_RECOVERY_GLOB_REG);
2645
2646         val = ((val & mask) >> shift);
2647
2648         return val != 0;
2649 }
2650
2651 /* set pf load mark */
2652 static void bnx2x_set_pf_load(struct bnx2x_softc *sc)
2653 {
2654         uint32_t val;
2655         uint32_t val1;
2656         uint32_t mask = SC_PATH(sc) ? BNX2X_PATH1_LOAD_CNT_MASK :
2657             BNX2X_PATH0_LOAD_CNT_MASK;
2658         uint32_t shift = SC_PATH(sc) ? BNX2X_PATH1_LOAD_CNT_SHIFT :
2659             BNX2X_PATH0_LOAD_CNT_SHIFT;
2660
2661         bnx2x_acquire_hw_lock(sc, HW_LOCK_RESOURCE_RECOVERY_REG);
2662
2663         PMD_INIT_FUNC_TRACE(sc);
2664
2665         val = REG_RD(sc, BNX2X_RECOVERY_GLOB_REG);
2666
2667         /* get the current counter value */
2668         val1 = ((val & mask) >> shift);
2669
2670         /* set bit of this PF */
2671         val1 |= (1 << SC_ABS_FUNC(sc));
2672
2673         /* clear the old value */
2674         val &= ~mask;
2675
2676         /* set the new one */
2677         val |= ((val1 << shift) & mask);
2678
2679         REG_WR(sc, BNX2X_RECOVERY_GLOB_REG, val);
2680
2681         bnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_RECOVERY_REG);
2682 }
2683
2684 /* clear pf load mark */
2685 static uint8_t bnx2x_clear_pf_load(struct bnx2x_softc *sc)
2686 {
2687         uint32_t val1, val;
2688         uint32_t mask = SC_PATH(sc) ? BNX2X_PATH1_LOAD_CNT_MASK :
2689             BNX2X_PATH0_LOAD_CNT_MASK;
2690         uint32_t shift = SC_PATH(sc) ? BNX2X_PATH1_LOAD_CNT_SHIFT :
2691             BNX2X_PATH0_LOAD_CNT_SHIFT;
2692
2693         bnx2x_acquire_hw_lock(sc, HW_LOCK_RESOURCE_RECOVERY_REG);
2694         val = REG_RD(sc, BNX2X_RECOVERY_GLOB_REG);
2695
2696         /* get the current counter value */
2697         val1 = (val & mask) >> shift;
2698
2699         /* clear bit of that PF */
2700         val1 &= ~(1 << SC_ABS_FUNC(sc));
2701
2702         /* clear the old value */
2703         val &= ~mask;
2704
2705         /* set the new one */
2706         val |= ((val1 << shift) & mask);
2707
2708         REG_WR(sc, BNX2X_RECOVERY_GLOB_REG, val);
2709         bnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_RECOVERY_REG);
2710         return val1 != 0;
2711 }
2712
2713 /* send load requrest to mcp and analyze response */
2714 static int bnx2x_nic_load_request(struct bnx2x_softc *sc, uint32_t * load_code)
2715 {
2716         PMD_INIT_FUNC_TRACE(sc);
2717
2718         /* init fw_seq */
2719         sc->fw_seq =
2720             (SHMEM_RD(sc, func_mb[SC_FW_MB_IDX(sc)].drv_mb_header) &
2721              DRV_MSG_SEQ_NUMBER_MASK);
2722
2723         PMD_DRV_LOG(DEBUG, sc, "initial fw_seq 0x%04x", sc->fw_seq);
2724
2725 #ifdef BNX2X_PULSE
2726         /* get the current FW pulse sequence */
2727         sc->fw_drv_pulse_wr_seq =
2728             (SHMEM_RD(sc, func_mb[SC_FW_MB_IDX(sc)].drv_pulse_mb) &
2729              DRV_PULSE_SEQ_MASK);
2730 #else
2731         /* set ALWAYS_ALIVE bit in shmem */
2732         sc->fw_drv_pulse_wr_seq |= DRV_PULSE_ALWAYS_ALIVE;
2733         bnx2x_drv_pulse(sc);
2734 #endif
2735
2736         /* load request */
2737         (*load_code) = bnx2x_fw_command(sc, DRV_MSG_CODE_LOAD_REQ,
2738                                       DRV_MSG_CODE_LOAD_REQ_WITH_LFA);
2739
2740         /* if the MCP fails to respond we must abort */
2741         if (!(*load_code)) {
2742                 PMD_DRV_LOG(NOTICE, sc, "MCP response failure!");
2743                 return -1;
2744         }
2745
2746         /* if MCP refused then must abort */
2747         if ((*load_code) == FW_MSG_CODE_DRV_LOAD_REFUSED) {
2748                 PMD_DRV_LOG(NOTICE, sc, "MCP refused load request");
2749                 return -1;
2750         }
2751
2752         return 0;
2753 }
2754
2755 /*
2756  * Check whether another PF has already loaded FW to chip. In virtualized
2757  * environments a pf from anoth VM may have already initialized the device
2758  * including loading FW.
2759  */
2760 static int bnx2x_nic_load_analyze_req(struct bnx2x_softc *sc, uint32_t load_code)
2761 {
2762         uint32_t my_fw, loaded_fw;
2763
2764         /* is another pf loaded on this engine? */
2765         if ((load_code != FW_MSG_CODE_DRV_LOAD_COMMON_CHIP) &&
2766             (load_code != FW_MSG_CODE_DRV_LOAD_COMMON)) {
2767                 /* build my FW version dword */
2768                 my_fw = (BNX2X_5710_FW_MAJOR_VERSION +
2769                          (BNX2X_5710_FW_MINOR_VERSION << 8) +
2770                          (BNX2X_5710_FW_REVISION_VERSION << 16) +
2771                          (BNX2X_5710_FW_ENGINEERING_VERSION << 24));
2772
2773                 /* read loaded FW from chip */
2774                 loaded_fw = REG_RD(sc, XSEM_REG_PRAM);
2775                 PMD_DRV_LOG(DEBUG, sc, "loaded FW 0x%08x / my FW 0x%08x",
2776                             loaded_fw, my_fw);
2777
2778                 /* abort nic load if version mismatch */
2779                 if (my_fw != loaded_fw) {
2780                         PMD_DRV_LOG(NOTICE, sc,
2781                                     "FW 0x%08x already loaded (mine is 0x%08x)",
2782                                     loaded_fw, my_fw);
2783                         return -1;
2784                 }
2785         }
2786
2787         return 0;
2788 }
2789
2790 /* mark PMF if applicable */
2791 static void bnx2x_nic_load_pmf(struct bnx2x_softc *sc, uint32_t load_code)
2792 {
2793         uint32_t ncsi_oem_data_addr;
2794
2795         PMD_INIT_FUNC_TRACE(sc);
2796
2797         if ((load_code == FW_MSG_CODE_DRV_LOAD_COMMON) ||
2798             (load_code == FW_MSG_CODE_DRV_LOAD_COMMON_CHIP) ||
2799             (load_code == FW_MSG_CODE_DRV_LOAD_PORT)) {
2800                 /*
2801                  * Barrier here for ordering between the writing to sc->port.pmf here
2802                  * and reading it from the periodic task.
2803                  */
2804                 sc->port.pmf = 1;
2805                 mb();
2806         } else {
2807                 sc->port.pmf = 0;
2808         }
2809
2810         PMD_DRV_LOG(DEBUG, sc, "pmf %d", sc->port.pmf);
2811
2812         if (load_code == FW_MSG_CODE_DRV_LOAD_COMMON_CHIP) {
2813                 if (SHMEM2_HAS(sc, ncsi_oem_data_addr)) {
2814                         ncsi_oem_data_addr = SHMEM2_RD(sc, ncsi_oem_data_addr);
2815                         if (ncsi_oem_data_addr) {
2816                                 REG_WR(sc,
2817                                        (ncsi_oem_data_addr +
2818                                         offsetof(struct glob_ncsi_oem_data,
2819                                                  driver_version)), 0);
2820                         }
2821                 }
2822         }
2823 }
2824
2825 static void bnx2x_read_mf_cfg(struct bnx2x_softc *sc)
2826 {
2827         int n = (CHIP_IS_MODE_4_PORT(sc) ? 2 : 1);
2828         int abs_func;
2829         int vn;
2830
2831         if (BNX2X_NOMCP(sc)) {
2832                 return;         /* what should be the default bvalue in this case */
2833         }
2834
2835         /*
2836          * The formula for computing the absolute function number is...
2837          * For 2 port configuration (4 functions per port):
2838          *   abs_func = 2 * vn + SC_PORT + SC_PATH
2839          * For 4 port configuration (2 functions per port):
2840          *   abs_func = 4 * vn + 2 * SC_PORT + SC_PATH
2841          */
2842         for (vn = VN_0; vn < SC_MAX_VN_NUM(sc); vn++) {
2843                 abs_func = (n * (2 * vn + SC_PORT(sc)) + SC_PATH(sc));
2844                 if (abs_func >= E1H_FUNC_MAX) {
2845                         break;
2846                 }
2847                 sc->devinfo.mf_info.mf_config[vn] =
2848                     MFCFG_RD(sc, func_mf_config[abs_func].config);
2849         }
2850
2851         if (sc->devinfo.mf_info.mf_config[SC_VN(sc)] &
2852             FUNC_MF_CFG_FUNC_DISABLED) {
2853                 PMD_DRV_LOG(DEBUG, sc, "mf_cfg function disabled");
2854                 sc->flags |= BNX2X_MF_FUNC_DIS;
2855         } else {
2856                 PMD_DRV_LOG(DEBUG, sc, "mf_cfg function enabled");
2857                 sc->flags &= ~BNX2X_MF_FUNC_DIS;
2858         }
2859 }
2860
2861 /* acquire split MCP access lock register */
2862 static int bnx2x_acquire_alr(struct bnx2x_softc *sc)
2863 {
2864         uint32_t j, val;
2865
2866         for (j = 0; j < 1000; j++) {
2867                 val = (1UL << 31);
2868                 REG_WR(sc, GRCBASE_MCP + 0x9c, val);
2869                 val = REG_RD(sc, GRCBASE_MCP + 0x9c);
2870                 if (val & (1L << 31))
2871                         break;
2872
2873                 DELAY(5000);
2874         }
2875
2876         if (!(val & (1L << 31))) {
2877                 PMD_DRV_LOG(NOTICE, sc, "Cannot acquire MCP access lock register");
2878                 return -1;
2879         }
2880
2881         return 0;
2882 }
2883
2884 /* release split MCP access lock register */
2885 static void bnx2x_release_alr(struct bnx2x_softc *sc)
2886 {
2887         REG_WR(sc, GRCBASE_MCP + 0x9c, 0);
2888 }
2889
2890 static void bnx2x_fan_failure(struct bnx2x_softc *sc)
2891 {
2892         int port = SC_PORT(sc);
2893         uint32_t ext_phy_config;
2894
2895         /* mark the failure */
2896         ext_phy_config =
2897             SHMEM_RD(sc, dev_info.port_hw_config[port].external_phy_config);
2898
2899         ext_phy_config &= ~PORT_HW_CFG_XGXS_EXT_PHY_TYPE_MASK;
2900         ext_phy_config |= PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE;
2901         SHMEM_WR(sc, dev_info.port_hw_config[port].external_phy_config,
2902                  ext_phy_config);
2903
2904         /* log the failure */
2905         PMD_DRV_LOG(INFO, sc,
2906                     "Fan Failure has caused the driver to shutdown "
2907                     "the card to prevent permanent damage. "
2908                     "Please contact OEM Support for assistance");
2909
2910         rte_panic("Schedule task to handle fan failure");
2911 }
2912
2913 /* this function is called upon a link interrupt */
2914 static void bnx2x_link_attn(struct bnx2x_softc *sc)
2915 {
2916         uint32_t pause_enabled = 0;
2917         struct host_port_stats *pstats;
2918         int cmng_fns;
2919
2920         /* Make sure that we are synced with the current statistics */
2921         bnx2x_stats_handle(sc, STATS_EVENT_STOP);
2922
2923         elink_link_update(&sc->link_params, &sc->link_vars);
2924
2925         if (sc->link_vars.link_up) {
2926
2927                 /* dropless flow control */
2928                 if (sc->dropless_fc) {
2929                         pause_enabled = 0;
2930
2931                         if (sc->link_vars.flow_ctrl & ELINK_FLOW_CTRL_TX) {
2932                                 pause_enabled = 1;
2933                         }
2934
2935                         REG_WR(sc,
2936                                (BAR_USTRORM_INTMEM +
2937                                 USTORM_ETH_PAUSE_ENABLED_OFFSET(SC_PORT(sc))),
2938                                pause_enabled);
2939                 }
2940
2941                 if (sc->link_vars.mac_type != ELINK_MAC_TYPE_EMAC) {
2942                         pstats = BNX2X_SP(sc, port_stats);
2943                         /* reset old mac stats */
2944                         memset(&(pstats->mac_stx[0]), 0,
2945                                sizeof(struct mac_stx));
2946                 }
2947
2948                 if (sc->state == BNX2X_STATE_OPEN) {
2949                         bnx2x_stats_handle(sc, STATS_EVENT_LINK_UP);
2950                 }
2951         }
2952
2953         if (sc->link_vars.link_up && sc->link_vars.line_speed) {
2954                 cmng_fns = bnx2x_get_cmng_fns_mode(sc);
2955
2956                 if (cmng_fns != CMNG_FNS_NONE) {
2957                         bnx2x_cmng_fns_init(sc, FALSE, cmng_fns);
2958                         storm_memset_cmng(sc, &sc->cmng, SC_PORT(sc));
2959                 }
2960         }
2961
2962         bnx2x_link_report_locked(sc);
2963
2964         if (IS_MF(sc)) {
2965                 bnx2x_link_sync_notify(sc);
2966         }
2967 }
2968
2969 static void bnx2x_attn_int_asserted(struct bnx2x_softc *sc, uint32_t asserted)
2970 {
2971         int port = SC_PORT(sc);
2972         uint32_t aeu_addr = port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 :
2973             MISC_REG_AEU_MASK_ATTN_FUNC_0;
2974         uint32_t nig_int_mask_addr = port ? NIG_REG_MASK_INTERRUPT_PORT1 :
2975             NIG_REG_MASK_INTERRUPT_PORT0;
2976         uint32_t aeu_mask;
2977         uint32_t nig_mask = 0;
2978         uint32_t reg_addr;
2979         uint32_t igu_acked;
2980         uint32_t cnt;
2981
2982         if (sc->attn_state & asserted) {
2983                 PMD_DRV_LOG(ERR, sc, "IGU ERROR attn=0x%08x", asserted);
2984         }
2985
2986         bnx2x_acquire_hw_lock(sc, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
2987
2988         aeu_mask = REG_RD(sc, aeu_addr);
2989
2990         aeu_mask &= ~(asserted & 0x3ff);
2991
2992         REG_WR(sc, aeu_addr, aeu_mask);
2993
2994         bnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
2995
2996         sc->attn_state |= asserted;
2997
2998         if (asserted & ATTN_HARD_WIRED_MASK) {
2999                 if (asserted & ATTN_NIG_FOR_FUNC) {
3000
3001                         bnx2x_acquire_phy_lock(sc);
3002                         /* save nig interrupt mask */
3003                         nig_mask = REG_RD(sc, nig_int_mask_addr);
3004
3005                         /* If nig_mask is not set, no need to call the update function */
3006                         if (nig_mask) {
3007                                 REG_WR(sc, nig_int_mask_addr, 0);
3008
3009                                 bnx2x_link_attn(sc);
3010                         }
3011
3012                         /* handle unicore attn? */
3013                 }
3014
3015                 if (asserted & ATTN_SW_TIMER_4_FUNC) {
3016                         PMD_DRV_LOG(DEBUG, sc, "ATTN_SW_TIMER_4_FUNC!");
3017                 }
3018
3019                 if (asserted & GPIO_2_FUNC) {
3020                         PMD_DRV_LOG(DEBUG, sc, "GPIO_2_FUNC!");
3021                 }
3022
3023                 if (asserted & GPIO_3_FUNC) {
3024                         PMD_DRV_LOG(DEBUG, sc, "GPIO_3_FUNC!");
3025                 }
3026
3027                 if (asserted & GPIO_4_FUNC) {
3028                         PMD_DRV_LOG(DEBUG, sc, "GPIO_4_FUNC!");
3029                 }
3030
3031                 if (port == 0) {
3032                         if (asserted & ATTN_GENERAL_ATTN_1) {
3033                                 PMD_DRV_LOG(DEBUG, sc, "ATTN_GENERAL_ATTN_1!");
3034                                 REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_1, 0x0);
3035                         }
3036                         if (asserted & ATTN_GENERAL_ATTN_2) {
3037                                 PMD_DRV_LOG(DEBUG, sc, "ATTN_GENERAL_ATTN_2!");
3038                                 REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_2, 0x0);
3039                         }
3040                         if (asserted & ATTN_GENERAL_ATTN_3) {
3041                                 PMD_DRV_LOG(DEBUG, sc, "ATTN_GENERAL_ATTN_3!");
3042                                 REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_3, 0x0);
3043                         }
3044                 } else {
3045                         if (asserted & ATTN_GENERAL_ATTN_4) {
3046                                 PMD_DRV_LOG(DEBUG, sc, "ATTN_GENERAL_ATTN_4!");
3047                                 REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_4, 0x0);
3048                         }
3049                         if (asserted & ATTN_GENERAL_ATTN_5) {
3050                                 PMD_DRV_LOG(DEBUG, sc, "ATTN_GENERAL_ATTN_5!");
3051                                 REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_5, 0x0);
3052                         }
3053                         if (asserted & ATTN_GENERAL_ATTN_6) {
3054                                 PMD_DRV_LOG(DEBUG, sc, "ATTN_GENERAL_ATTN_6!");
3055                                 REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_6, 0x0);
3056                         }
3057                 }
3058         }
3059         /* hardwired */
3060         if (sc->devinfo.int_block == INT_BLOCK_HC) {
3061                 reg_addr =
3062                     (HC_REG_COMMAND_REG + port * 32 +
3063                      COMMAND_REG_ATTN_BITS_SET);
3064         } else {
3065                 reg_addr = (BAR_IGU_INTMEM + IGU_CMD_ATTN_BIT_SET_UPPER * 8);
3066         }
3067
3068         PMD_DRV_LOG(DEBUG, sc, "about to mask 0x%08x at %s addr 0x%08x",
3069                     asserted,
3070                     (sc->devinfo.int_block == INT_BLOCK_HC) ? "HC" : "IGU",
3071                     reg_addr);
3072         REG_WR(sc, reg_addr, asserted);
3073
3074         /* now set back the mask */
3075         if (asserted & ATTN_NIG_FOR_FUNC) {
3076                 /*
3077                  * Verify that IGU ack through BAR was written before restoring
3078                  * NIG mask. This loop should exit after 2-3 iterations max.
3079                  */
3080                 if (sc->devinfo.int_block != INT_BLOCK_HC) {
3081                         cnt = 0;
3082
3083                         do {
3084                                 igu_acked =
3085                                     REG_RD(sc, IGU_REG_ATTENTION_ACK_BITS);
3086                         } while (((igu_acked & ATTN_NIG_FOR_FUNC) == 0)
3087                                  && (++cnt < MAX_IGU_ATTN_ACK_TO));
3088
3089                         if (!igu_acked) {
3090                                 PMD_DRV_LOG(ERR, sc,
3091                                             "Failed to verify IGU ack on time");
3092                         }
3093
3094                         mb();
3095                 }
3096
3097                 REG_WR(sc, nig_int_mask_addr, nig_mask);
3098
3099                 bnx2x_release_phy_lock(sc);
3100         }
3101 }
3102
3103 static void
3104 bnx2x_print_next_block(__rte_unused struct bnx2x_softc *sc, __rte_unused int idx,
3105                      __rte_unused const char *blk)
3106 {
3107         PMD_DRV_LOG(INFO, sc, "%s%s", idx ? ", " : "", blk);
3108 }
3109
3110 static int
3111 bnx2x_check_blocks_with_parity0(struct bnx2x_softc *sc, uint32_t sig, int par_num,
3112                               uint8_t print)
3113 {
3114         uint32_t cur_bit = 0;
3115         int i = 0;
3116
3117         for (i = 0; sig; i++) {
3118                 cur_bit = ((uint32_t) 0x1 << i);
3119                 if (sig & cur_bit) {
3120                         switch (cur_bit) {
3121                         case AEU_INPUTS_ATTN_BITS_BRB_PARITY_ERROR:
3122                                 if (print)
3123                                         bnx2x_print_next_block(sc, par_num++,
3124                                                              "BRB");
3125                                 break;
3126                         case AEU_INPUTS_ATTN_BITS_PARSER_PARITY_ERROR:
3127                                 if (print)
3128                                         bnx2x_print_next_block(sc, par_num++,
3129                                                              "PARSER");
3130                                 break;
3131                         case AEU_INPUTS_ATTN_BITS_TSDM_PARITY_ERROR:
3132                                 if (print)
3133                                         bnx2x_print_next_block(sc, par_num++,
3134                                                              "TSDM");
3135                                 break;
3136                         case AEU_INPUTS_ATTN_BITS_SEARCHER_PARITY_ERROR:
3137                                 if (print)
3138                                         bnx2x_print_next_block(sc, par_num++,
3139                                                              "SEARCHER");
3140                                 break;
3141                         case AEU_INPUTS_ATTN_BITS_TCM_PARITY_ERROR:
3142                                 if (print)
3143                                         bnx2x_print_next_block(sc, par_num++,
3144                                                              "TCM");
3145                                 break;
3146                         case AEU_INPUTS_ATTN_BITS_TSEMI_PARITY_ERROR:
3147                                 if (print)
3148                                         bnx2x_print_next_block(sc, par_num++,
3149                                                              "TSEMI");
3150                                 break;
3151                         case AEU_INPUTS_ATTN_BITS_PBCLIENT_PARITY_ERROR:
3152                                 if (print)
3153                                         bnx2x_print_next_block(sc, par_num++,
3154                                                              "XPB");
3155                                 break;
3156                         }
3157
3158                         /* Clear the bit */
3159                         sig &= ~cur_bit;
3160                 }
3161         }
3162
3163         return par_num;
3164 }
3165
3166 static int
3167 bnx2x_check_blocks_with_parity1(struct bnx2x_softc *sc, uint32_t sig, int par_num,
3168                               uint8_t * global, uint8_t print)
3169 {
3170         int i = 0;
3171         uint32_t cur_bit = 0;
3172         for (i = 0; sig; i++) {
3173                 cur_bit = ((uint32_t) 0x1 << i);
3174                 if (sig & cur_bit) {
3175                         switch (cur_bit) {
3176                         case AEU_INPUTS_ATTN_BITS_PBF_PARITY_ERROR:
3177                                 if (print)
3178                                         bnx2x_print_next_block(sc, par_num++,
3179                                                              "PBF");
3180                                 break;
3181                         case AEU_INPUTS_ATTN_BITS_QM_PARITY_ERROR:
3182                                 if (print)
3183                                         bnx2x_print_next_block(sc, par_num++,
3184                                                              "QM");
3185                                 break;
3186                         case AEU_INPUTS_ATTN_BITS_TIMERS_PARITY_ERROR:
3187                                 if (print)
3188                                         bnx2x_print_next_block(sc, par_num++,
3189                                                              "TM");
3190                                 break;
3191                         case AEU_INPUTS_ATTN_BITS_XSDM_PARITY_ERROR:
3192                                 if (print)
3193                                         bnx2x_print_next_block(sc, par_num++,
3194                                                              "XSDM");
3195                                 break;
3196                         case AEU_INPUTS_ATTN_BITS_XCM_PARITY_ERROR:
3197                                 if (print)
3198                                         bnx2x_print_next_block(sc, par_num++,
3199                                                              "XCM");
3200                                 break;
3201                         case AEU_INPUTS_ATTN_BITS_XSEMI_PARITY_ERROR:
3202                                 if (print)
3203                                         bnx2x_print_next_block(sc, par_num++,
3204                                                              "XSEMI");
3205                                 break;
3206                         case AEU_INPUTS_ATTN_BITS_DOORBELLQ_PARITY_ERROR:
3207                                 if (print)
3208                                         bnx2x_print_next_block(sc, par_num++,
3209                                                              "DOORBELLQ");
3210                                 break;
3211                         case AEU_INPUTS_ATTN_BITS_NIG_PARITY_ERROR:
3212                                 if (print)
3213                                         bnx2x_print_next_block(sc, par_num++,
3214                                                              "NIG");
3215                                 break;
3216                         case AEU_INPUTS_ATTN_BITS_VAUX_PCI_CORE_PARITY_ERROR:
3217                                 if (print)
3218                                         bnx2x_print_next_block(sc, par_num++,
3219                                                              "VAUX PCI CORE");
3220                                 *global = TRUE;
3221                                 break;
3222                         case AEU_INPUTS_ATTN_BITS_DEBUG_PARITY_ERROR:
3223                                 if (print)
3224                                         bnx2x_print_next_block(sc, par_num++,
3225                                                              "DEBUG");
3226                                 break;
3227                         case AEU_INPUTS_ATTN_BITS_USDM_PARITY_ERROR:
3228                                 if (print)
3229                                         bnx2x_print_next_block(sc, par_num++,
3230                                                              "USDM");
3231                                 break;
3232                         case AEU_INPUTS_ATTN_BITS_UCM_PARITY_ERROR:
3233                                 if (print)
3234                                         bnx2x_print_next_block(sc, par_num++,
3235                                                              "UCM");
3236                                 break;
3237                         case AEU_INPUTS_ATTN_BITS_USEMI_PARITY_ERROR:
3238                                 if (print)
3239                                         bnx2x_print_next_block(sc, par_num++,
3240                                                              "USEMI");
3241                                 break;
3242                         case AEU_INPUTS_ATTN_BITS_UPB_PARITY_ERROR:
3243                                 if (print)
3244                                         bnx2x_print_next_block(sc, par_num++,
3245                                                              "UPB");
3246                                 break;
3247                         case AEU_INPUTS_ATTN_BITS_CSDM_PARITY_ERROR:
3248                                 if (print)
3249                                         bnx2x_print_next_block(sc, par_num++,
3250                                                              "CSDM");
3251                                 break;
3252                         case AEU_INPUTS_ATTN_BITS_CCM_PARITY_ERROR:
3253                                 if (print)
3254                                         bnx2x_print_next_block(sc, par_num++,
3255                                                              "CCM");
3256                                 break;
3257                         }
3258
3259                         /* Clear the bit */
3260                         sig &= ~cur_bit;
3261                 }
3262         }
3263
3264         return par_num;
3265 }
3266
3267 static int
3268 bnx2x_check_blocks_with_parity2(struct bnx2x_softc *sc, uint32_t sig, int par_num,
3269                               uint8_t print)
3270 {
3271         uint32_t cur_bit = 0;
3272         int i = 0;
3273
3274         for (i = 0; sig; i++) {
3275                 cur_bit = ((uint32_t) 0x1 << i);
3276                 if (sig & cur_bit) {
3277                         switch (cur_bit) {
3278                         case AEU_INPUTS_ATTN_BITS_CSEMI_PARITY_ERROR:
3279                                 if (print)
3280                                         bnx2x_print_next_block(sc, par_num++,
3281                                                              "CSEMI");
3282                                 break;
3283                         case AEU_INPUTS_ATTN_BITS_PXP_PARITY_ERROR:
3284                                 if (print)
3285                                         bnx2x_print_next_block(sc, par_num++,
3286                                                              "PXP");
3287                                 break;
3288                         case AEU_IN_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR:
3289                                 if (print)
3290                                         bnx2x_print_next_block(sc, par_num++,
3291                                                              "PXPPCICLOCKCLIENT");
3292                                 break;
3293                         case AEU_INPUTS_ATTN_BITS_CFC_PARITY_ERROR:
3294                                 if (print)
3295                                         bnx2x_print_next_block(sc, par_num++,
3296                                                              "CFC");
3297                                 break;
3298                         case AEU_INPUTS_ATTN_BITS_CDU_PARITY_ERROR:
3299                                 if (print)
3300                                         bnx2x_print_next_block(sc, par_num++,
3301                                                              "CDU");
3302                                 break;
3303                         case AEU_INPUTS_ATTN_BITS_DMAE_PARITY_ERROR:
3304                                 if (print)
3305                                         bnx2x_print_next_block(sc, par_num++,
3306                                                              "DMAE");
3307                                 break;
3308                         case AEU_INPUTS_ATTN_BITS_IGU_PARITY_ERROR:
3309                                 if (print)
3310                                         bnx2x_print_next_block(sc, par_num++,
3311                                                              "IGU");
3312                                 break;
3313                         case AEU_INPUTS_ATTN_BITS_MISC_PARITY_ERROR:
3314                                 if (print)
3315                                         bnx2x_print_next_block(sc, par_num++,
3316                                                              "MISC");
3317                                 break;
3318                         }
3319
3320                         /* Clear the bit */
3321                         sig &= ~cur_bit;
3322                 }
3323         }
3324
3325         return par_num;
3326 }
3327
3328 static int
3329 bnx2x_check_blocks_with_parity3(struct bnx2x_softc *sc, uint32_t sig, int par_num,
3330                               uint8_t * global, uint8_t print)
3331 {
3332         uint32_t cur_bit = 0;
3333         int i = 0;
3334
3335         for (i = 0; sig; i++) {
3336                 cur_bit = ((uint32_t) 0x1 << i);
3337                 if (sig & cur_bit) {
3338                         switch (cur_bit) {
3339                         case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_ROM_PARITY:
3340                                 if (print)
3341                                         bnx2x_print_next_block(sc, par_num++,
3342                                                              "MCP ROM");
3343                                 *global = TRUE;
3344                                 break;
3345                         case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_RX_PARITY:
3346                                 if (print)
3347                                         bnx2x_print_next_block(sc, par_num++,
3348                                                              "MCP UMP RX");
3349                                 *global = TRUE;
3350                                 break;
3351                         case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_TX_PARITY:
3352                                 if (print)
3353                                         bnx2x_print_next_block(sc, par_num++,
3354                                                              "MCP UMP TX");
3355                                 *global = TRUE;
3356                                 break;
3357                         case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_SCPAD_PARITY:
3358                                 if (print)
3359                                         bnx2x_print_next_block(sc, par_num++,
3360                                                              "MCP SCPAD");
3361                                 *global = TRUE;
3362                                 break;
3363                         }
3364
3365                         /* Clear the bit */
3366                         sig &= ~cur_bit;
3367                 }
3368         }
3369
3370         return par_num;
3371 }
3372
3373 static int
3374 bnx2x_check_blocks_with_parity4(struct bnx2x_softc *sc, uint32_t sig, int par_num,
3375                               uint8_t print)
3376 {
3377         uint32_t cur_bit = 0;
3378         int i = 0;
3379
3380         for (i = 0; sig; i++) {
3381                 cur_bit = ((uint32_t) 0x1 << i);
3382                 if (sig & cur_bit) {
3383                         switch (cur_bit) {
3384                         case AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR:
3385                                 if (print)
3386                                         bnx2x_print_next_block(sc, par_num++,
3387                                                              "PGLUE_B");
3388                                 break;
3389                         case AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR:
3390                                 if (print)
3391                                         bnx2x_print_next_block(sc, par_num++,
3392                                                              "ATC");
3393                                 break;
3394                         }
3395
3396                         /* Clear the bit */
3397                         sig &= ~cur_bit;
3398                 }
3399         }
3400
3401         return par_num;
3402 }
3403
3404 static uint8_t
3405 bnx2x_parity_attn(struct bnx2x_softc *sc, uint8_t * global, uint8_t print,
3406                 uint32_t * sig)
3407 {
3408         int par_num = 0;
3409
3410         if ((sig[0] & HW_PRTY_ASSERT_SET_0) ||
3411             (sig[1] & HW_PRTY_ASSERT_SET_1) ||
3412             (sig[2] & HW_PRTY_ASSERT_SET_2) ||
3413             (sig[3] & HW_PRTY_ASSERT_SET_3) ||
3414             (sig[4] & HW_PRTY_ASSERT_SET_4)) {
3415                 PMD_DRV_LOG(ERR, sc,
3416                             "Parity error: HW block parity attention:"
3417                             "[0]:0x%08x [1]:0x%08x [2]:0x%08x [3]:0x%08x [4]:0x%08x",
3418                             (uint32_t) (sig[0] & HW_PRTY_ASSERT_SET_0),
3419                             (uint32_t) (sig[1] & HW_PRTY_ASSERT_SET_1),
3420                             (uint32_t) (sig[2] & HW_PRTY_ASSERT_SET_2),
3421                             (uint32_t) (sig[3] & HW_PRTY_ASSERT_SET_3),
3422                             (uint32_t) (sig[4] & HW_PRTY_ASSERT_SET_4));
3423
3424                 if (print)
3425                         PMD_DRV_LOG(INFO, sc, "Parity errors detected in blocks: ");
3426
3427                 par_num =
3428                     bnx2x_check_blocks_with_parity0(sc, sig[0] &
3429                                                   HW_PRTY_ASSERT_SET_0,
3430                                                   par_num, print);
3431                 par_num =
3432                     bnx2x_check_blocks_with_parity1(sc, sig[1] &
3433                                                   HW_PRTY_ASSERT_SET_1,
3434                                                   par_num, global, print);
3435                 par_num =
3436                     bnx2x_check_blocks_with_parity2(sc, sig[2] &
3437                                                   HW_PRTY_ASSERT_SET_2,
3438                                                   par_num, print);
3439                 par_num =
3440                     bnx2x_check_blocks_with_parity3(sc, sig[3] &
3441                                                   HW_PRTY_ASSERT_SET_3,
3442                                                   par_num, global, print);
3443                 par_num =
3444                     bnx2x_check_blocks_with_parity4(sc, sig[4] &
3445                                                   HW_PRTY_ASSERT_SET_4,
3446                                                   par_num, print);
3447
3448                 if (print)
3449                         PMD_DRV_LOG(INFO, sc, "");
3450
3451                 return TRUE;
3452         }
3453
3454         return FALSE;
3455 }
3456
3457 static uint8_t
3458 bnx2x_chk_parity_attn(struct bnx2x_softc *sc, uint8_t * global, uint8_t print)
3459 {
3460         struct attn_route attn = { {0} };
3461         int port = SC_PORT(sc);
3462
3463         attn.sig[0] = REG_RD(sc, MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 + port * 4);
3464         attn.sig[1] = REG_RD(sc, MISC_REG_AEU_AFTER_INVERT_2_FUNC_0 + port * 4);
3465         attn.sig[2] = REG_RD(sc, MISC_REG_AEU_AFTER_INVERT_3_FUNC_0 + port * 4);
3466         attn.sig[3] = REG_RD(sc, MISC_REG_AEU_AFTER_INVERT_4_FUNC_0 + port * 4);
3467
3468         if (!CHIP_IS_E1x(sc))
3469                 attn.sig[4] =
3470                     REG_RD(sc, MISC_REG_AEU_AFTER_INVERT_5_FUNC_0 + port * 4);
3471
3472         return bnx2x_parity_attn(sc, global, print, attn.sig);
3473 }
3474
3475 static void bnx2x_attn_int_deasserted4(struct bnx2x_softc *sc, uint32_t attn)
3476 {
3477         uint32_t val;
3478
3479         if (attn & AEU_INPUTS_ATTN_BITS_PGLUE_HW_INTERRUPT) {
3480                 val = REG_RD(sc, PGLUE_B_REG_PGLUE_B_INT_STS_CLR);
3481                 PMD_DRV_LOG(INFO, sc, "ERROR: PGLUE hw attention 0x%08x", val);
3482                 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_ADDRESS_ERROR)
3483                         PMD_DRV_LOG(INFO, sc,
3484                                     "ERROR: PGLUE_B_PGLUE_B_INT_STS_REG_ADDRESS_ERROR");
3485                 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_INCORRECT_RCV_BEHAVIOR)
3486                         PMD_DRV_LOG(INFO, sc,
3487                                     "ERROR: PGLUE_B_PGLUE_B_INT_STS_REG_INCORRECT_RCV_BEHAVIOR");
3488                 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_WAS_ERROR_ATTN)
3489                         PMD_DRV_LOG(INFO, sc,
3490                                     "ERROR: PGLUE_B_PGLUE_B_INT_STS_REG_WAS_ERROR_ATTN");
3491                 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_VF_LENGTH_VIOLATION_ATTN)
3492                         PMD_DRV_LOG(INFO, sc,
3493                                     "ERROR: PGLUE_B_PGLUE_B_INT_STS_REG_VF_LENGTH_VIOLATION_ATTN");
3494                 if (val &
3495                     PGLUE_B_PGLUE_B_INT_STS_REG_VF_GRC_SPACE_VIOLATION_ATTN)
3496                         PMD_DRV_LOG(INFO, sc,
3497                                     "ERROR: PGLUE_B_PGLUE_B_INT_STS_REG_VF_GRC_SPACE_VIOLATION_ATTN");
3498                 if (val &
3499                     PGLUE_B_PGLUE_B_INT_STS_REG_VF_MSIX_BAR_VIOLATION_ATTN)
3500                         PMD_DRV_LOG(INFO, sc,
3501                                     "ERROR: PGLUE_B_PGLUE_B_INT_STS_REG_VF_MSIX_BAR_VIOLATION_ATTN");
3502                 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_ERROR_ATTN)
3503                         PMD_DRV_LOG(INFO, sc,
3504                                     "ERROR: PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_ERROR_ATTN");
3505                 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_IN_TWO_RCBS_ATTN)
3506                         PMD_DRV_LOG(INFO, sc,
3507                                     "ERROR: PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_IN_TWO_RCBS_ATTN");
3508                 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_CSSNOOP_FIFO_OVERFLOW)
3509                         PMD_DRV_LOG(INFO, sc,
3510                                     "ERROR: PGLUE_B_PGLUE_B_INT_STS_REG_CSSNOOP_FIFO_OVERFLOW");
3511         }
3512
3513         if (attn & AEU_INPUTS_ATTN_BITS_ATC_HW_INTERRUPT) {
3514                 val = REG_RD(sc, ATC_REG_ATC_INT_STS_CLR);
3515                 PMD_DRV_LOG(INFO, sc, "ERROR: ATC hw attention 0x%08x", val);
3516                 if (val & ATC_ATC_INT_STS_REG_ADDRESS_ERROR)
3517                         PMD_DRV_LOG(INFO, sc,
3518                                     "ERROR: ATC_ATC_INT_STS_REG_ADDRESS_ERROR");
3519                 if (val & ATC_ATC_INT_STS_REG_ATC_TCPL_TO_NOT_PEND)
3520                         PMD_DRV_LOG(INFO, sc,
3521                                     "ERROR: ATC_ATC_INT_STS_REG_ATC_TCPL_TO_NOT_PEND");
3522                 if (val & ATC_ATC_INT_STS_REG_ATC_GPA_MULTIPLE_HITS)
3523                         PMD_DRV_LOG(INFO, sc,
3524                                     "ERROR: ATC_ATC_INT_STS_REG_ATC_GPA_MULTIPLE_HITS");
3525                 if (val & ATC_ATC_INT_STS_REG_ATC_RCPL_TO_EMPTY_CNT)
3526                         PMD_DRV_LOG(INFO, sc,
3527                                     "ERROR: ATC_ATC_INT_STS_REG_ATC_RCPL_TO_EMPTY_CNT");
3528                 if (val & ATC_ATC_INT_STS_REG_ATC_TCPL_ERROR)
3529                         PMD_DRV_LOG(INFO, sc,
3530                                     "ERROR: ATC_ATC_INT_STS_REG_ATC_TCPL_ERROR");
3531                 if (val & ATC_ATC_INT_STS_REG_ATC_IREQ_LESS_THAN_STU)
3532                         PMD_DRV_LOG(INFO, sc,
3533                                     "ERROR: ATC_ATC_INT_STS_REG_ATC_IREQ_LESS_THAN_STU");
3534         }
3535
3536         if (attn & (AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR |
3537                     AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR)) {
3538                 PMD_DRV_LOG(INFO, sc,
3539                             "ERROR: FATAL parity attention set4 0x%08x",
3540                             (uint32_t) (attn &
3541                                         (AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR
3542                                          |
3543                                          AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR)));
3544         }
3545 }
3546
3547 static void bnx2x_e1h_disable(struct bnx2x_softc *sc)
3548 {
3549         int port = SC_PORT(sc);
3550
3551         REG_WR(sc, NIG_REG_LLH0_FUNC_EN + port * 8, 0);
3552 }
3553
3554 static void bnx2x_e1h_enable(struct bnx2x_softc *sc)
3555 {
3556         int port = SC_PORT(sc);
3557
3558         REG_WR(sc, NIG_REG_LLH0_FUNC_EN + port * 8, 1);
3559 }
3560
3561 /*
3562  * called due to MCP event (on pmf):
3563  *   reread new bandwidth configuration
3564  *   configure FW
3565  *   notify others function about the change
3566  */
3567 static void bnx2x_config_mf_bw(struct bnx2x_softc *sc)
3568 {
3569         if (sc->link_vars.link_up) {
3570                 bnx2x_cmng_fns_init(sc, TRUE, CMNG_FNS_MINMAX);
3571                 bnx2x_link_sync_notify(sc);
3572         }
3573
3574         storm_memset_cmng(sc, &sc->cmng, SC_PORT(sc));
3575 }
3576
3577 static void bnx2x_set_mf_bw(struct bnx2x_softc *sc)
3578 {
3579         bnx2x_config_mf_bw(sc);
3580         bnx2x_fw_command(sc, DRV_MSG_CODE_SET_MF_BW_ACK, 0);
3581 }
3582
3583 static void bnx2x_handle_eee_event(struct bnx2x_softc *sc)
3584 {
3585         bnx2x_fw_command(sc, DRV_MSG_CODE_EEE_RESULTS_ACK, 0);
3586 }
3587
3588 #define DRV_INFO_ETH_STAT_NUM_MACS_REQUIRED 3
3589
3590 static void bnx2x_drv_info_ether_stat(struct bnx2x_softc *sc)
3591 {
3592         struct eth_stats_info *ether_stat = &sc->sp->drv_info_to_mcp.ether_stat;
3593
3594         strncpy(ether_stat->version, BNX2X_DRIVER_VERSION,
3595                 ETH_STAT_INFO_VERSION_LEN);
3596
3597         sc->sp_objs[0].mac_obj.get_n_elements(sc, &sc->sp_objs[0].mac_obj,
3598                                               DRV_INFO_ETH_STAT_NUM_MACS_REQUIRED,
3599                                               ether_stat->mac_local + MAC_PAD,
3600                                               MAC_PAD, ETH_ALEN);
3601
3602         ether_stat->mtu_size = sc->mtu;
3603
3604         ether_stat->feature_flags |= FEATURE_ETH_CHKSUM_OFFLOAD_MASK;
3605         ether_stat->promiscuous_mode = 0;       // (flags & PROMISC) ? 1 : 0;
3606
3607         ether_stat->txq_size = sc->tx_ring_size;
3608         ether_stat->rxq_size = sc->rx_ring_size;
3609 }
3610
3611 static void bnx2x_handle_drv_info_req(struct bnx2x_softc *sc)
3612 {
3613         enum drv_info_opcode op_code;
3614         uint32_t drv_info_ctl = SHMEM2_RD(sc, drv_info_control);
3615
3616         /* if drv_info version supported by MFW doesn't match - send NACK */
3617         if ((drv_info_ctl & DRV_INFO_CONTROL_VER_MASK) != DRV_INFO_CUR_VER) {
3618                 bnx2x_fw_command(sc, DRV_MSG_CODE_DRV_INFO_NACK, 0);
3619                 return;
3620         }
3621
3622         op_code = ((drv_info_ctl & DRV_INFO_CONTROL_OP_CODE_MASK) >>
3623                    DRV_INFO_CONTROL_OP_CODE_SHIFT);
3624
3625         memset(&sc->sp->drv_info_to_mcp, 0, sizeof(union drv_info_to_mcp));
3626
3627         switch (op_code) {
3628         case ETH_STATS_OPCODE:
3629                 bnx2x_drv_info_ether_stat(sc);
3630                 break;
3631         case FCOE_STATS_OPCODE:
3632         case ISCSI_STATS_OPCODE:
3633         default:
3634                 /* if op code isn't supported - send NACK */
3635                 bnx2x_fw_command(sc, DRV_MSG_CODE_DRV_INFO_NACK, 0);
3636                 return;
3637         }
3638
3639         /*
3640          * If we got drv_info attn from MFW then these fields are defined in
3641          * shmem2 for sure
3642          */
3643         SHMEM2_WR(sc, drv_info_host_addr_lo,
3644                   U64_LO(BNX2X_SP_MAPPING(sc, drv_info_to_mcp)));
3645         SHMEM2_WR(sc, drv_info_host_addr_hi,
3646                   U64_HI(BNX2X_SP_MAPPING(sc, drv_info_to_mcp)));
3647
3648         bnx2x_fw_command(sc, DRV_MSG_CODE_DRV_INFO_ACK, 0);
3649 }
3650
3651 static void bnx2x_dcc_event(struct bnx2x_softc *sc, uint32_t dcc_event)
3652 {
3653         if (dcc_event & DRV_STATUS_DCC_DISABLE_ENABLE_PF) {
3654 /*
3655  * This is the only place besides the function initialization
3656  * where the sc->flags can change so it is done without any
3657  * locks
3658  */
3659                 if (sc->devinfo.
3660                     mf_info.mf_config[SC_VN(sc)] & FUNC_MF_CFG_FUNC_DISABLED) {
3661                         PMD_DRV_LOG(DEBUG, sc, "mf_cfg function disabled");
3662                         sc->flags |= BNX2X_MF_FUNC_DIS;
3663                         bnx2x_e1h_disable(sc);
3664                 } else {
3665                         PMD_DRV_LOG(DEBUG, sc, "mf_cfg function enabled");
3666                         sc->flags &= ~BNX2X_MF_FUNC_DIS;
3667                         bnx2x_e1h_enable(sc);
3668                 }
3669                 dcc_event &= ~DRV_STATUS_DCC_DISABLE_ENABLE_PF;
3670         }
3671
3672         if (dcc_event & DRV_STATUS_DCC_BANDWIDTH_ALLOCATION) {
3673                 bnx2x_config_mf_bw(sc);
3674                 dcc_event &= ~DRV_STATUS_DCC_BANDWIDTH_ALLOCATION;
3675         }
3676
3677         /* Report results to MCP */
3678         if (dcc_event)
3679                 bnx2x_fw_command(sc, DRV_MSG_CODE_DCC_FAILURE, 0);
3680         else
3681                 bnx2x_fw_command(sc, DRV_MSG_CODE_DCC_OK, 0);
3682 }
3683
3684 static void bnx2x_pmf_update(struct bnx2x_softc *sc)
3685 {
3686         int port = SC_PORT(sc);
3687         uint32_t val;
3688
3689         sc->port.pmf = 1;
3690
3691         /*
3692          * We need the mb() to ensure the ordering between the writing to
3693          * sc->port.pmf here and reading it from the bnx2x_periodic_task().
3694          */
3695         mb();
3696
3697         /* enable nig attention */
3698         val = (0xff0f | (1 << (SC_VN(sc) + 4)));
3699         if (sc->devinfo.int_block == INT_BLOCK_HC) {
3700                 REG_WR(sc, HC_REG_TRAILING_EDGE_0 + port * 8, val);
3701                 REG_WR(sc, HC_REG_LEADING_EDGE_0 + port * 8, val);
3702         } else if (!CHIP_IS_E1x(sc)) {
3703                 REG_WR(sc, IGU_REG_TRAILING_EDGE_LATCH, val);
3704                 REG_WR(sc, IGU_REG_LEADING_EDGE_LATCH, val);
3705         }
3706
3707         bnx2x_stats_handle(sc, STATS_EVENT_PMF);
3708 }
3709
3710 static int bnx2x_mc_assert(struct bnx2x_softc *sc)
3711 {
3712         char last_idx;
3713         int i, rc = 0;
3714         __rte_unused uint32_t row0, row1, row2, row3;
3715
3716         /* XSTORM */
3717         last_idx =
3718             REG_RD8(sc, BAR_XSTRORM_INTMEM + XSTORM_ASSERT_LIST_INDEX_OFFSET);
3719         if (last_idx)
3720                 PMD_DRV_LOG(ERR, sc, "XSTORM_ASSERT_LIST_INDEX 0x%x", last_idx);
3721
3722         /* print the asserts */
3723         for (i = 0; i < STORM_ASSERT_ARRAY_SIZE; i++) {
3724
3725                 row0 =
3726                     REG_RD(sc,
3727                            BAR_XSTRORM_INTMEM + XSTORM_ASSERT_LIST_OFFSET(i));
3728                 row1 =
3729                     REG_RD(sc,
3730                            BAR_XSTRORM_INTMEM + XSTORM_ASSERT_LIST_OFFSET(i) +
3731                            4);
3732                 row2 =
3733                     REG_RD(sc,
3734                            BAR_XSTRORM_INTMEM + XSTORM_ASSERT_LIST_OFFSET(i) +
3735                            8);
3736                 row3 =
3737                     REG_RD(sc,
3738                            BAR_XSTRORM_INTMEM + XSTORM_ASSERT_LIST_OFFSET(i) +
3739                            12);
3740
3741                 if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) {
3742                         PMD_DRV_LOG(ERR, sc,
3743                                     "XSTORM_ASSERT_INDEX 0x%x = 0x%08x 0x%08x 0x%08x 0x%08x",
3744                                     i, row3, row2, row1, row0);
3745                         rc++;
3746                 } else {
3747                         break;
3748                 }
3749         }
3750
3751         /* TSTORM */
3752         last_idx =
3753             REG_RD8(sc, BAR_TSTRORM_INTMEM + TSTORM_ASSERT_LIST_INDEX_OFFSET);
3754         if (last_idx) {
3755                 PMD_DRV_LOG(ERR, sc, "TSTORM_ASSERT_LIST_INDEX 0x%x", last_idx);
3756         }
3757
3758         /* print the asserts */
3759         for (i = 0; i < STORM_ASSERT_ARRAY_SIZE; i++) {
3760
3761                 row0 =
3762                     REG_RD(sc,
3763                            BAR_TSTRORM_INTMEM + TSTORM_ASSERT_LIST_OFFSET(i));
3764                 row1 =
3765                     REG_RD(sc,
3766                            BAR_TSTRORM_INTMEM + TSTORM_ASSERT_LIST_OFFSET(i) +
3767                            4);
3768                 row2 =
3769                     REG_RD(sc,
3770                            BAR_TSTRORM_INTMEM + TSTORM_ASSERT_LIST_OFFSET(i) +
3771                            8);
3772                 row3 =
3773                     REG_RD(sc,
3774                            BAR_TSTRORM_INTMEM + TSTORM_ASSERT_LIST_OFFSET(i) +
3775                            12);
3776
3777                 if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) {
3778                         PMD_DRV_LOG(ERR, sc,
3779                                     "TSTORM_ASSERT_INDEX 0x%x = 0x%08x 0x%08x 0x%08x 0x%08x",
3780                                     i, row3, row2, row1, row0);
3781                         rc++;
3782                 } else {
3783                         break;
3784                 }
3785         }
3786
3787         /* CSTORM */
3788         last_idx =
3789             REG_RD8(sc, BAR_CSTRORM_INTMEM + CSTORM_ASSERT_LIST_INDEX_OFFSET);
3790         if (last_idx) {
3791                 PMD_DRV_LOG(ERR, sc, "CSTORM_ASSERT_LIST_INDEX 0x%x", last_idx);
3792         }
3793
3794         /* print the asserts */
3795         for (i = 0; i < STORM_ASSERT_ARRAY_SIZE; i++) {
3796
3797                 row0 =
3798                     REG_RD(sc,
3799                            BAR_CSTRORM_INTMEM + CSTORM_ASSERT_LIST_OFFSET(i));
3800                 row1 =
3801                     REG_RD(sc,
3802                            BAR_CSTRORM_INTMEM + CSTORM_ASSERT_LIST_OFFSET(i) +
3803                            4);
3804                 row2 =
3805                     REG_RD(sc,
3806                            BAR_CSTRORM_INTMEM + CSTORM_ASSERT_LIST_OFFSET(i) +
3807                            8);
3808                 row3 =
3809                     REG_RD(sc,
3810                            BAR_CSTRORM_INTMEM + CSTORM_ASSERT_LIST_OFFSET(i) +
3811                            12);
3812
3813                 if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) {
3814                         PMD_DRV_LOG(ERR, sc,
3815                                     "CSTORM_ASSERT_INDEX 0x%x = 0x%08x 0x%08x 0x%08x 0x%08x",
3816                                     i, row3, row2, row1, row0);
3817                         rc++;
3818                 } else {
3819                         break;
3820                 }
3821         }
3822
3823         /* USTORM */
3824         last_idx =
3825             REG_RD8(sc, BAR_USTRORM_INTMEM + USTORM_ASSERT_LIST_INDEX_OFFSET);
3826         if (last_idx) {
3827                 PMD_DRV_LOG(ERR, sc, "USTORM_ASSERT_LIST_INDEX 0x%x", last_idx);
3828         }
3829
3830         /* print the asserts */
3831         for (i = 0; i < STORM_ASSERT_ARRAY_SIZE; i++) {
3832
3833                 row0 =
3834                     REG_RD(sc,
3835                            BAR_USTRORM_INTMEM + USTORM_ASSERT_LIST_OFFSET(i));
3836                 row1 =
3837                     REG_RD(sc,
3838                            BAR_USTRORM_INTMEM + USTORM_ASSERT_LIST_OFFSET(i) +
3839                            4);
3840                 row2 =
3841                     REG_RD(sc,
3842                            BAR_USTRORM_INTMEM + USTORM_ASSERT_LIST_OFFSET(i) +
3843                            8);
3844                 row3 =
3845                     REG_RD(sc,
3846                            BAR_USTRORM_INTMEM + USTORM_ASSERT_LIST_OFFSET(i) +
3847                            12);
3848
3849                 if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) {
3850                         PMD_DRV_LOG(ERR, sc,
3851                                     "USTORM_ASSERT_INDEX 0x%x = 0x%08x 0x%08x 0x%08x 0x%08x",
3852                                     i, row3, row2, row1, row0);
3853                         rc++;
3854                 } else {
3855                         break;
3856                 }
3857         }
3858
3859         return rc;
3860 }
3861
3862 static void bnx2x_attn_int_deasserted3(struct bnx2x_softc *sc, uint32_t attn)
3863 {
3864         int func = SC_FUNC(sc);
3865         uint32_t val;
3866
3867         if (attn & EVEREST_GEN_ATTN_IN_USE_MASK) {
3868
3869                 if (attn & BNX2X_PMF_LINK_ASSERT(sc)) {
3870
3871                         REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_12 + func * 4, 0);
3872                         bnx2x_read_mf_cfg(sc);
3873                         sc->devinfo.mf_info.mf_config[SC_VN(sc)] =
3874                             MFCFG_RD(sc,
3875                                      func_mf_config[SC_ABS_FUNC(sc)].config);
3876                         val =
3877                             SHMEM_RD(sc, func_mb[SC_FW_MB_IDX(sc)].drv_status);
3878
3879                         if (val & DRV_STATUS_DCC_EVENT_MASK)
3880                                 bnx2x_dcc_event(sc,
3881                                               (val &
3882                                                DRV_STATUS_DCC_EVENT_MASK));
3883
3884                         if (val & DRV_STATUS_SET_MF_BW)
3885                                 bnx2x_set_mf_bw(sc);
3886
3887                         if (val & DRV_STATUS_DRV_INFO_REQ)
3888                                 bnx2x_handle_drv_info_req(sc);
3889
3890                         if ((sc->port.pmf == 0) && (val & DRV_STATUS_PMF))
3891                                 bnx2x_pmf_update(sc);
3892
3893                         if (val & DRV_STATUS_EEE_NEGOTIATION_RESULTS)
3894                                 bnx2x_handle_eee_event(sc);
3895
3896                         if (sc->link_vars.periodic_flags &
3897                             ELINK_PERIODIC_FLAGS_LINK_EVENT) {
3898                                 /* sync with link */
3899                                 bnx2x_acquire_phy_lock(sc);
3900                                 sc->link_vars.periodic_flags &=
3901                                     ~ELINK_PERIODIC_FLAGS_LINK_EVENT;
3902                                 bnx2x_release_phy_lock(sc);
3903                                 if (IS_MF(sc)) {
3904                                         bnx2x_link_sync_notify(sc);
3905                                 }
3906                                 bnx2x_link_report(sc);
3907                         }
3908
3909                         /*
3910                          * Always call it here: bnx2x_link_report() will
3911                          * prevent the link indication duplication.
3912                          */
3913                         bnx2x_link_status_update(sc);
3914
3915                 } else if (attn & BNX2X_MC_ASSERT_BITS) {
3916
3917                         PMD_DRV_LOG(ERR, sc, "MC assert!");
3918                         bnx2x_mc_assert(sc);
3919                         REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_10, 0);
3920                         REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_9, 0);
3921                         REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_8, 0);
3922                         REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_7, 0);
3923                         rte_panic("MC assert!");
3924
3925                 } else if (attn & BNX2X_MCP_ASSERT) {
3926
3927                         PMD_DRV_LOG(ERR, sc, "MCP assert!");
3928                         REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_11, 0);
3929
3930                 } else {
3931                         PMD_DRV_LOG(ERR, sc,
3932                                     "Unknown HW assert! (attn 0x%08x)", attn);
3933                 }
3934         }
3935
3936         if (attn & EVEREST_LATCHED_ATTN_IN_USE_MASK) {
3937                 PMD_DRV_LOG(ERR, sc, "LATCHED attention 0x%08x (masked)", attn);
3938                 if (attn & BNX2X_GRC_TIMEOUT) {
3939                         val = REG_RD(sc, MISC_REG_GRC_TIMEOUT_ATTN);
3940                         PMD_DRV_LOG(ERR, sc, "GRC time-out 0x%08x", val);
3941                 }
3942                 if (attn & BNX2X_GRC_RSV) {
3943                         val = REG_RD(sc, MISC_REG_GRC_RSV_ATTN);
3944                         PMD_DRV_LOG(ERR, sc, "GRC reserved 0x%08x", val);
3945                 }
3946                 REG_WR(sc, MISC_REG_AEU_CLR_LATCH_SIGNAL, 0x7ff);
3947         }
3948 }
3949
3950 static void bnx2x_attn_int_deasserted2(struct bnx2x_softc *sc, uint32_t attn)
3951 {
3952         int port = SC_PORT(sc);
3953         int reg_offset;
3954         uint32_t val0, mask0, val1, mask1;
3955         uint32_t val;
3956
3957         if (attn & AEU_INPUTS_ATTN_BITS_CFC_HW_INTERRUPT) {
3958                 val = REG_RD(sc, CFC_REG_CFC_INT_STS_CLR);
3959                 PMD_DRV_LOG(ERR, sc, "CFC hw attention 0x%08x", val);
3960 /* CFC error attention */
3961                 if (val & 0x2) {
3962                         PMD_DRV_LOG(ERR, sc, "FATAL error from CFC");
3963                 }
3964         }
3965
3966         if (attn & AEU_INPUTS_ATTN_BITS_PXP_HW_INTERRUPT) {
3967                 val = REG_RD(sc, PXP_REG_PXP_INT_STS_CLR_0);
3968                 PMD_DRV_LOG(ERR, sc, "PXP hw attention-0 0x%08x", val);
3969 /* RQ_USDMDP_FIFO_OVERFLOW */
3970                 if (val & 0x18000) {
3971                         PMD_DRV_LOG(ERR, sc, "FATAL error from PXP");
3972                 }
3973
3974                 if (!CHIP_IS_E1x(sc)) {
3975                         val = REG_RD(sc, PXP_REG_PXP_INT_STS_CLR_1);
3976                         PMD_DRV_LOG(ERR, sc, "PXP hw attention-1 0x%08x", val);
3977                 }
3978         }
3979 #define PXP2_EOP_ERROR_BIT  PXP2_PXP2_INT_STS_CLR_0_REG_WR_PGLUE_EOP_ERROR
3980 #define AEU_PXP2_HW_INT_BIT AEU_INPUTS_ATTN_BITS_PXPPCICLOCKCLIENT_HW_INTERRUPT
3981
3982         if (attn & AEU_PXP2_HW_INT_BIT) {
3983 /*  CQ47854 workaround do not panic on
3984  *  PXP2_PXP2_INT_STS_0_REG_WR_PGLUE_EOP_ERROR
3985  */
3986                 if (!CHIP_IS_E1x(sc)) {
3987                         mask0 = REG_RD(sc, PXP2_REG_PXP2_INT_MASK_0);
3988                         val1 = REG_RD(sc, PXP2_REG_PXP2_INT_STS_1);
3989                         mask1 = REG_RD(sc, PXP2_REG_PXP2_INT_MASK_1);
3990                         val0 = REG_RD(sc, PXP2_REG_PXP2_INT_STS_0);
3991                         /*
3992                          * If the only PXP2_EOP_ERROR_BIT is set in
3993                          * STS0 and STS1 - clear it
3994                          *
3995                          * probably we lose additional attentions between
3996                          * STS0 and STS_CLR0, in this case user will not
3997                          * be notified about them
3998                          */
3999                         if (val0 & mask0 & PXP2_EOP_ERROR_BIT &&
4000                             !(val1 & mask1))
4001                                 val0 = REG_RD(sc, PXP2_REG_PXP2_INT_STS_CLR_0);
4002
4003                         /* print the register, since no one can restore it */
4004                         PMD_DRV_LOG(ERR, sc,
4005                                     "PXP2_REG_PXP2_INT_STS_CLR_0 0x%08x", val0);
4006
4007                         /*
4008                          * if PXP2_PXP2_INT_STS_0_REG_WR_PGLUE_EOP_ERROR
4009                          * then notify
4010                          */
4011                         if (val0 & PXP2_EOP_ERROR_BIT) {
4012                                 PMD_DRV_LOG(ERR, sc, "PXP2_WR_PGLUE_EOP_ERROR");
4013
4014                                 /*
4015                                  * if only PXP2_PXP2_INT_STS_0_REG_WR_PGLUE_EOP_ERROR is
4016                                  * set then clear attention from PXP2 block without panic
4017                                  */
4018                                 if (((val0 & mask0) == PXP2_EOP_ERROR_BIT) &&
4019                                     ((val1 & mask1) == 0))
4020                                         attn &= ~AEU_PXP2_HW_INT_BIT;
4021                         }
4022                 }
4023         }
4024
4025         if (attn & HW_INTERRUT_ASSERT_SET_2) {
4026                 reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_2 :
4027                               MISC_REG_AEU_ENABLE1_FUNC_0_OUT_2);
4028
4029                 val = REG_RD(sc, reg_offset);
4030                 val &= ~(attn & HW_INTERRUT_ASSERT_SET_2);
4031                 REG_WR(sc, reg_offset, val);
4032
4033                 PMD_DRV_LOG(ERR, sc,
4034                             "FATAL HW block attention set2 0x%x",
4035                             (uint32_t) (attn & HW_INTERRUT_ASSERT_SET_2));
4036                 rte_panic("HW block attention set2");
4037         }
4038 }
4039
4040 static void bnx2x_attn_int_deasserted1(struct bnx2x_softc *sc, uint32_t attn)
4041 {
4042         int port = SC_PORT(sc);
4043         int reg_offset;
4044         uint32_t val;
4045
4046         if (attn & AEU_INPUTS_ATTN_BITS_DOORBELLQ_HW_INTERRUPT) {
4047                 val = REG_RD(sc, DORQ_REG_DORQ_INT_STS_CLR);
4048                 PMD_DRV_LOG(ERR, sc, "DB hw attention 0x%08x", val);
4049 /* DORQ discard attention */
4050                 if (val & 0x2) {
4051                         PMD_DRV_LOG(ERR, sc, "FATAL error from DORQ");
4052                 }
4053         }
4054
4055         if (attn & HW_INTERRUT_ASSERT_SET_1) {
4056                 reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_1 :
4057                               MISC_REG_AEU_ENABLE1_FUNC_0_OUT_1);
4058
4059                 val = REG_RD(sc, reg_offset);
4060                 val &= ~(attn & HW_INTERRUT_ASSERT_SET_1);
4061                 REG_WR(sc, reg_offset, val);
4062
4063                 PMD_DRV_LOG(ERR, sc,
4064                             "FATAL HW block attention set1 0x%08x",
4065                             (uint32_t) (attn & HW_INTERRUT_ASSERT_SET_1));
4066                 rte_panic("HW block attention set1");
4067         }
4068 }
4069
4070 static void bnx2x_attn_int_deasserted0(struct bnx2x_softc *sc, uint32_t attn)
4071 {
4072         int port = SC_PORT(sc);
4073         int reg_offset;
4074         uint32_t val;
4075
4076         reg_offset = (port) ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 :
4077             MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0;
4078
4079         if (attn & AEU_INPUTS_ATTN_BITS_SPIO5) {
4080                 val = REG_RD(sc, reg_offset);
4081                 val &= ~AEU_INPUTS_ATTN_BITS_SPIO5;
4082                 REG_WR(sc, reg_offset, val);
4083
4084                 PMD_DRV_LOG(WARNING, sc, "SPIO5 hw attention");
4085
4086 /* Fan failure attention */
4087                 elink_hw_reset_phy(&sc->link_params);
4088                 bnx2x_fan_failure(sc);
4089         }
4090
4091         if ((attn & sc->link_vars.aeu_int_mask) && sc->port.pmf) {
4092                 bnx2x_acquire_phy_lock(sc);
4093                 elink_handle_module_detect_int(&sc->link_params);
4094                 bnx2x_release_phy_lock(sc);
4095         }
4096
4097         if (attn & HW_INTERRUT_ASSERT_SET_0) {
4098                 val = REG_RD(sc, reg_offset);
4099                 val &= ~(attn & HW_INTERRUT_ASSERT_SET_0);
4100                 REG_WR(sc, reg_offset, val);
4101
4102                 rte_panic("FATAL HW block attention set0 0x%lx",
4103                           (attn & HW_INTERRUT_ASSERT_SET_0));
4104         }
4105 }
4106
4107 static void bnx2x_attn_int_deasserted(struct bnx2x_softc *sc, uint32_t deasserted)
4108 {
4109         struct attn_route attn;
4110         struct attn_route *group_mask;
4111         int port = SC_PORT(sc);
4112         int index;
4113         uint32_t reg_addr;
4114         uint32_t val;
4115         uint32_t aeu_mask;
4116         uint8_t global = FALSE;
4117
4118         /*
4119          * Need to take HW lock because MCP or other port might also
4120          * try to handle this event.
4121          */
4122         bnx2x_acquire_alr(sc);
4123
4124         if (bnx2x_chk_parity_attn(sc, &global, TRUE)) {
4125                 sc->recovery_state = BNX2X_RECOVERY_INIT;
4126
4127 /* disable HW interrupts */
4128                 bnx2x_int_disable(sc);
4129                 bnx2x_release_alr(sc);
4130                 return;
4131         }
4132
4133         attn.sig[0] = REG_RD(sc, MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 + port * 4);
4134         attn.sig[1] = REG_RD(sc, MISC_REG_AEU_AFTER_INVERT_2_FUNC_0 + port * 4);
4135         attn.sig[2] = REG_RD(sc, MISC_REG_AEU_AFTER_INVERT_3_FUNC_0 + port * 4);
4136         attn.sig[3] = REG_RD(sc, MISC_REG_AEU_AFTER_INVERT_4_FUNC_0 + port * 4);
4137         if (!CHIP_IS_E1x(sc)) {
4138                 attn.sig[4] =
4139                     REG_RD(sc, MISC_REG_AEU_AFTER_INVERT_5_FUNC_0 + port * 4);
4140         } else {
4141                 attn.sig[4] = 0;
4142         }
4143
4144         for (index = 0; index < MAX_DYNAMIC_ATTN_GRPS; index++) {
4145                 if (deasserted & (1 << index)) {
4146                         group_mask = &sc->attn_group[index];
4147
4148                         bnx2x_attn_int_deasserted4(sc,
4149                                                  attn.
4150                                                  sig[4] & group_mask->sig[4]);
4151                         bnx2x_attn_int_deasserted3(sc,
4152                                                  attn.
4153                                                  sig[3] & group_mask->sig[3]);
4154                         bnx2x_attn_int_deasserted1(sc,
4155                                                  attn.
4156                                                  sig[1] & group_mask->sig[1]);
4157                         bnx2x_attn_int_deasserted2(sc,
4158                                                  attn.
4159                                                  sig[2] & group_mask->sig[2]);
4160                         bnx2x_attn_int_deasserted0(sc,
4161                                                  attn.
4162                                                  sig[0] & group_mask->sig[0]);
4163                 }
4164         }
4165
4166         bnx2x_release_alr(sc);
4167
4168         if (sc->devinfo.int_block == INT_BLOCK_HC) {
4169                 reg_addr = (HC_REG_COMMAND_REG + port * 32 +
4170                             COMMAND_REG_ATTN_BITS_CLR);
4171         } else {
4172                 reg_addr = (BAR_IGU_INTMEM + IGU_CMD_ATTN_BIT_CLR_UPPER * 8);
4173         }
4174
4175         val = ~deasserted;
4176         PMD_DRV_LOG(DEBUG, sc,
4177                     "about to mask 0x%08x at %s addr 0x%08x", val,
4178                     (sc->devinfo.int_block == INT_BLOCK_HC) ? "HC" : "IGU",
4179                     reg_addr);
4180         REG_WR(sc, reg_addr, val);
4181
4182         if (~sc->attn_state & deasserted) {
4183                 PMD_DRV_LOG(ERR, sc, "IGU error");
4184         }
4185
4186         reg_addr = port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 :
4187             MISC_REG_AEU_MASK_ATTN_FUNC_0;
4188
4189         bnx2x_acquire_hw_lock(sc, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
4190
4191         aeu_mask = REG_RD(sc, reg_addr);
4192
4193         aeu_mask |= (deasserted & 0x3ff);
4194
4195         REG_WR(sc, reg_addr, aeu_mask);
4196         bnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
4197
4198         sc->attn_state &= ~deasserted;
4199 }
4200
4201 static void bnx2x_attn_int(struct bnx2x_softc *sc)
4202 {
4203         /* read local copy of bits */
4204         uint32_t attn_bits = le32toh(sc->def_sb->atten_status_block.attn_bits);
4205         uint32_t attn_ack =
4206             le32toh(sc->def_sb->atten_status_block.attn_bits_ack);
4207         uint32_t attn_state = sc->attn_state;
4208
4209         /* look for changed bits */
4210         uint32_t asserted = attn_bits & ~attn_ack & ~attn_state;
4211         uint32_t deasserted = ~attn_bits & attn_ack & attn_state;
4212
4213         PMD_DRV_LOG(DEBUG, sc,
4214                     "attn_bits 0x%08x attn_ack 0x%08x asserted 0x%08x deasserted 0x%08x",
4215                     attn_bits, attn_ack, asserted, deasserted);
4216
4217         if (~(attn_bits ^ attn_ack) & (attn_bits ^ attn_state)) {
4218                 PMD_DRV_LOG(ERR, sc, "BAD attention state");
4219         }
4220
4221         /* handle bits that were raised */
4222         if (asserted) {
4223                 bnx2x_attn_int_asserted(sc, asserted);
4224         }
4225
4226         if (deasserted) {
4227                 bnx2x_attn_int_deasserted(sc, deasserted);
4228         }
4229 }
4230
4231 static uint16_t bnx2x_update_dsb_idx(struct bnx2x_softc *sc)
4232 {
4233         struct host_sp_status_block *def_sb = sc->def_sb;
4234         uint16_t rc = 0;
4235
4236         if (!def_sb)
4237                 return 0;
4238
4239         mb();                   /* status block is written to by the chip */
4240
4241         if (sc->def_att_idx != def_sb->atten_status_block.attn_bits_index) {
4242                 sc->def_att_idx = def_sb->atten_status_block.attn_bits_index;
4243                 rc |= BNX2X_DEF_SB_ATT_IDX;
4244         }
4245
4246         if (sc->def_idx != def_sb->sp_sb.running_index) {
4247                 sc->def_idx = def_sb->sp_sb.running_index;
4248                 rc |= BNX2X_DEF_SB_IDX;
4249         }
4250
4251         mb();
4252
4253         return rc;
4254 }
4255
4256 static struct ecore_queue_sp_obj *bnx2x_cid_to_q_obj(struct bnx2x_softc *sc,
4257                                                           uint32_t cid)
4258 {
4259         return &sc->sp_objs[CID_TO_FP(cid, sc)].q_obj;
4260 }
4261
4262 static void bnx2x_handle_mcast_eqe(struct bnx2x_softc *sc)
4263 {
4264         struct ecore_mcast_ramrod_params rparam;
4265         int rc;
4266
4267         memset(&rparam, 0, sizeof(rparam));
4268
4269         rparam.mcast_obj = &sc->mcast_obj;
4270
4271         /* clear pending state for the last command */
4272         sc->mcast_obj.raw.clear_pending(&sc->mcast_obj.raw);
4273
4274         /* if there are pending mcast commands - send them */
4275         if (sc->mcast_obj.check_pending(&sc->mcast_obj)) {
4276                 rc = ecore_config_mcast(sc, &rparam, ECORE_MCAST_CMD_CONT);
4277                 if (rc < 0) {
4278                         PMD_DRV_LOG(INFO, sc,
4279                                     "Failed to send pending mcast commands (%d)",
4280                                     rc);
4281                 }
4282         }
4283 }
4284
4285 static void
4286 bnx2x_handle_classification_eqe(struct bnx2x_softc *sc, union event_ring_elem *elem)
4287 {
4288         unsigned long ramrod_flags = 0;
4289         int rc = 0;
4290         uint32_t cid = elem->message.data.eth_event.echo & BNX2X_SWCID_MASK;
4291         struct ecore_vlan_mac_obj *vlan_mac_obj;
4292
4293         /* always push next commands out, don't wait here */
4294         bnx2x_set_bit(RAMROD_CONT, &ramrod_flags);
4295
4296         switch (le32toh(elem->message.data.eth_event.echo) >> BNX2X_SWCID_SHIFT) {
4297         case ECORE_FILTER_MAC_PENDING:
4298                 PMD_DRV_LOG(DEBUG, sc, "Got SETUP_MAC completions");
4299                 vlan_mac_obj = &sc->sp_objs[cid].mac_obj;
4300                 break;
4301
4302         case ECORE_FILTER_MCAST_PENDING:
4303                 PMD_DRV_LOG(DEBUG, sc, "Got SETUP_MCAST completions");
4304                 bnx2x_handle_mcast_eqe(sc);
4305                 return;
4306
4307         default:
4308                 PMD_DRV_LOG(NOTICE, sc, "Unsupported classification command: %d",
4309                             elem->message.data.eth_event.echo);
4310                 return;
4311         }
4312
4313         rc = vlan_mac_obj->complete(sc, vlan_mac_obj, elem, &ramrod_flags);
4314
4315         if (rc < 0) {
4316                 PMD_DRV_LOG(NOTICE, sc,
4317                             "Failed to schedule new commands (%d)", rc);
4318         } else if (rc > 0) {
4319                 PMD_DRV_LOG(DEBUG, sc, "Scheduled next pending commands...");
4320         }
4321 }
4322
4323 static void bnx2x_handle_rx_mode_eqe(struct bnx2x_softc *sc)
4324 {
4325         bnx2x_clear_bit(ECORE_FILTER_RX_MODE_PENDING, &sc->sp_state);
4326
4327         /* send rx_mode command again if was requested */
4328         if (bnx2x_test_and_clear_bit(ECORE_FILTER_RX_MODE_SCHED, &sc->sp_state)) {
4329                 bnx2x_set_storm_rx_mode(sc);
4330         }
4331 }
4332
4333 static void bnx2x_update_eq_prod(struct bnx2x_softc *sc, uint16_t prod)
4334 {
4335         storm_memset_eq_prod(sc, prod, SC_FUNC(sc));
4336         wmb();                  /* keep prod updates ordered */
4337 }
4338
4339 static void bnx2x_eq_int(struct bnx2x_softc *sc)
4340 {
4341         uint16_t hw_cons, sw_cons, sw_prod;
4342         union event_ring_elem *elem;
4343         uint8_t echo;
4344         uint32_t cid;
4345         uint8_t opcode;
4346         int spqe_cnt = 0;
4347         struct ecore_queue_sp_obj *q_obj;
4348         struct ecore_func_sp_obj *f_obj = &sc->func_obj;
4349         struct ecore_raw_obj *rss_raw = &sc->rss_conf_obj.raw;
4350
4351         hw_cons = le16toh(*sc->eq_cons_sb);
4352
4353         /*
4354          * The hw_cons range is 1-255, 257 - the sw_cons range is 0-254, 256.
4355          * when we get to the next-page we need to adjust so the loop
4356          * condition below will be met. The next element is the size of a
4357          * regular element and hence incrementing by 1
4358          */
4359         if ((hw_cons & EQ_DESC_MAX_PAGE) == EQ_DESC_MAX_PAGE) {
4360                 hw_cons++;
4361         }
4362
4363         /*
4364          * This function may never run in parallel with itself for a
4365          * specific sc and no need for a read memory barrier here.
4366          */
4367         sw_cons = sc->eq_cons;
4368         sw_prod = sc->eq_prod;
4369
4370         for (;
4371              sw_cons != hw_cons;
4372              sw_prod = NEXT_EQ_IDX(sw_prod), sw_cons = NEXT_EQ_IDX(sw_cons)) {
4373
4374                 elem = &sc->eq[EQ_DESC(sw_cons)];
4375
4376 /* elem CID originates from FW, actually LE */
4377                 cid = SW_CID(elem->message.data.cfc_del_event.cid);
4378                 opcode = elem->message.opcode;
4379
4380 /* handle eq element */
4381                 switch (opcode) {
4382                 case EVENT_RING_OPCODE_STAT_QUERY:
4383                         PMD_DEBUG_PERIODIC_LOG(DEBUG, sc, "got statistics completion event %d",
4384                                     sc->stats_comp++);
4385                         /* nothing to do with stats comp */
4386                         goto next_spqe;
4387
4388                 case EVENT_RING_OPCODE_CFC_DEL:
4389                         /* handle according to cid range */
4390                         /* we may want to verify here that the sc state is HALTING */
4391                         PMD_DRV_LOG(DEBUG, sc, "got delete ramrod for MULTI[%d]",
4392                                     cid);
4393                         q_obj = bnx2x_cid_to_q_obj(sc, cid);
4394                         if (q_obj->complete_cmd(sc, q_obj, ECORE_Q_CMD_CFC_DEL)) {
4395                                 break;
4396                         }
4397                         goto next_spqe;
4398
4399                 case EVENT_RING_OPCODE_STOP_TRAFFIC:
4400                         PMD_DRV_LOG(DEBUG, sc, "got STOP TRAFFIC");
4401                         if (f_obj->complete_cmd(sc, f_obj, ECORE_F_CMD_TX_STOP)) {
4402                                 break;
4403                         }
4404                         goto next_spqe;
4405
4406                 case EVENT_RING_OPCODE_START_TRAFFIC:
4407                         PMD_DRV_LOG(DEBUG, sc, "got START TRAFFIC");
4408                         if (f_obj->complete_cmd
4409                             (sc, f_obj, ECORE_F_CMD_TX_START)) {
4410                                 break;
4411                         }
4412                         goto next_spqe;
4413
4414                 case EVENT_RING_OPCODE_FUNCTION_UPDATE:
4415                         echo = elem->message.data.function_update_event.echo;
4416                         if (echo == SWITCH_UPDATE) {
4417                                 PMD_DRV_LOG(DEBUG, sc,
4418                                             "got FUNC_SWITCH_UPDATE ramrod");
4419                                 if (f_obj->complete_cmd(sc, f_obj,
4420                                                         ECORE_F_CMD_SWITCH_UPDATE))
4421                                 {
4422                                         break;
4423                                 }
4424                         } else {
4425                                 PMD_DRV_LOG(DEBUG, sc,
4426                                             "AFEX: ramrod completed FUNCTION_UPDATE");
4427                                 f_obj->complete_cmd(sc, f_obj,
4428                                                     ECORE_F_CMD_AFEX_UPDATE);
4429                         }
4430                         goto next_spqe;
4431
4432                 case EVENT_RING_OPCODE_FORWARD_SETUP:
4433                         q_obj = &bnx2x_fwd_sp_obj(sc, q_obj);
4434                         if (q_obj->complete_cmd(sc, q_obj,
4435                                                 ECORE_Q_CMD_SETUP_TX_ONLY)) {
4436                                 break;
4437                         }
4438                         goto next_spqe;
4439
4440                 case EVENT_RING_OPCODE_FUNCTION_START:
4441                         PMD_DRV_LOG(DEBUG, sc, "got FUNC_START ramrod");
4442                         if (f_obj->complete_cmd(sc, f_obj, ECORE_F_CMD_START)) {
4443                                 break;
4444                         }
4445                         goto next_spqe;
4446
4447                 case EVENT_RING_OPCODE_FUNCTION_STOP:
4448                         PMD_DRV_LOG(DEBUG, sc, "got FUNC_STOP ramrod");
4449                         if (f_obj->complete_cmd(sc, f_obj, ECORE_F_CMD_STOP)) {
4450                                 break;
4451                         }
4452                         goto next_spqe;
4453                 }
4454
4455                 switch (opcode | sc->state) {
4456                 case (EVENT_RING_OPCODE_RSS_UPDATE_RULES | BNX2X_STATE_OPEN):
4457                 case (EVENT_RING_OPCODE_RSS_UPDATE_RULES | BNX2X_STATE_OPENING_WAITING_PORT):
4458                         cid =
4459                             elem->message.data.eth_event.echo & BNX2X_SWCID_MASK;
4460                         PMD_DRV_LOG(DEBUG, sc, "got RSS_UPDATE ramrod. CID %d",
4461                                     cid);
4462                         rss_raw->clear_pending(rss_raw);
4463                         break;
4464
4465                 case (EVENT_RING_OPCODE_SET_MAC | BNX2X_STATE_OPEN):
4466                 case (EVENT_RING_OPCODE_SET_MAC | BNX2X_STATE_DIAG):
4467                 case (EVENT_RING_OPCODE_SET_MAC | BNX2X_STATE_CLOSING_WAITING_HALT):
4468                 case (EVENT_RING_OPCODE_CLASSIFICATION_RULES | BNX2X_STATE_OPEN):
4469                 case (EVENT_RING_OPCODE_CLASSIFICATION_RULES | BNX2X_STATE_DIAG):
4470                 case (EVENT_RING_OPCODE_CLASSIFICATION_RULES | BNX2X_STATE_CLOSING_WAITING_HALT):
4471                         PMD_DRV_LOG(DEBUG, sc,
4472                                     "got (un)set mac ramrod");
4473                         bnx2x_handle_classification_eqe(sc, elem);
4474                         break;
4475
4476                 case (EVENT_RING_OPCODE_MULTICAST_RULES | BNX2X_STATE_OPEN):
4477                 case (EVENT_RING_OPCODE_MULTICAST_RULES | BNX2X_STATE_DIAG):
4478                 case (EVENT_RING_OPCODE_MULTICAST_RULES | BNX2X_STATE_CLOSING_WAITING_HALT):
4479                         PMD_DRV_LOG(DEBUG, sc,
4480                                     "got mcast ramrod");
4481                         bnx2x_handle_mcast_eqe(sc);
4482                         break;
4483
4484                 case (EVENT_RING_OPCODE_FILTERS_RULES | BNX2X_STATE_OPEN):
4485                 case (EVENT_RING_OPCODE_FILTERS_RULES | BNX2X_STATE_DIAG):
4486                 case (EVENT_RING_OPCODE_FILTERS_RULES | BNX2X_STATE_CLOSING_WAITING_HALT):
4487                         PMD_DRV_LOG(DEBUG, sc,
4488                                     "got rx_mode ramrod");
4489                         bnx2x_handle_rx_mode_eqe(sc);
4490                         break;
4491
4492                 default:
4493                         /* unknown event log error and continue */
4494                         PMD_DRV_LOG(INFO, sc, "Unknown EQ event %d, sc->state 0x%x",
4495                                     elem->message.opcode, sc->state);
4496                 }
4497
4498 next_spqe:
4499                 spqe_cnt++;
4500         }                       /* for */
4501
4502         mb();
4503         atomic_add_acq_long(&sc->eq_spq_left, spqe_cnt);
4504
4505         sc->eq_cons = sw_cons;
4506         sc->eq_prod = sw_prod;
4507
4508         /* make sure that above mem writes were issued towards the memory */
4509         wmb();
4510
4511         /* update producer */
4512         bnx2x_update_eq_prod(sc, sc->eq_prod);
4513 }
4514
4515 static int bnx2x_handle_sp_tq(struct bnx2x_softc *sc)
4516 {
4517         uint16_t status;
4518         int rc = 0;
4519
4520         PMD_DRV_LOG(DEBUG, sc, "---> SP TASK <---");
4521
4522         /* what work needs to be performed? */
4523         status = bnx2x_update_dsb_idx(sc);
4524
4525         PMD_DRV_LOG(DEBUG, sc, "dsb status 0x%04x", status);
4526
4527         /* HW attentions */
4528         if (status & BNX2X_DEF_SB_ATT_IDX) {
4529                 PMD_DRV_LOG(DEBUG, sc, "---> ATTN INTR <---");
4530                 bnx2x_attn_int(sc);
4531                 status &= ~BNX2X_DEF_SB_ATT_IDX;
4532                 rc = 1;
4533         }
4534
4535         /* SP events: STAT_QUERY and others */
4536         if (status & BNX2X_DEF_SB_IDX) {
4537 /* handle EQ completions */
4538                 PMD_DRV_LOG(DEBUG, sc, "---> EQ INTR <---");
4539                 bnx2x_eq_int(sc);
4540                 bnx2x_ack_sb(sc, sc->igu_dsb_id, USTORM_ID,
4541                            le16toh(sc->def_idx), IGU_INT_NOP, 1);
4542                 status &= ~BNX2X_DEF_SB_IDX;
4543         }
4544
4545         /* if status is non zero then something went wrong */
4546         if (unlikely(status)) {
4547                 PMD_DRV_LOG(INFO, sc,
4548                             "Got an unknown SP interrupt! (0x%04x)", status);
4549         }
4550
4551         /* ack status block only if something was actually handled */
4552         bnx2x_ack_sb(sc, sc->igu_dsb_id, ATTENTION_ID,
4553                    le16toh(sc->def_att_idx), IGU_INT_ENABLE, 1);
4554
4555         return rc;
4556 }
4557
4558 static void bnx2x_handle_fp_tq(struct bnx2x_fastpath *fp)
4559 {
4560         struct bnx2x_softc *sc = fp->sc;
4561         uint8_t more_rx = FALSE;
4562
4563         /* Make sure FP is initialized */
4564         if (!fp->sb_running_index)
4565                 return;
4566
4567         PMD_DEBUG_PERIODIC_LOG(DEBUG, sc,
4568                                "---> FP TASK QUEUE (%d) <--", fp->index);
4569
4570         /* update the fastpath index */
4571         bnx2x_update_fp_sb_idx(fp);
4572
4573         if (rte_atomic32_read(&sc->scan_fp) == 1) {
4574                 if (bnx2x_has_rx_work(fp)) {
4575                         more_rx = bnx2x_rxeof(sc, fp);
4576                 }
4577
4578                 if (more_rx) {
4579                         /* still more work to do */
4580                         bnx2x_handle_fp_tq(fp);
4581                         return;
4582                 }
4583         }
4584
4585         /* Assuming we have completed slow path completion, clear the flag */
4586         rte_atomic32_set(&sc->scan_fp, 0);
4587         bnx2x_ack_sb(sc, fp->igu_sb_id, USTORM_ID,
4588                    le16toh(fp->fp_hc_idx), IGU_INT_ENABLE, 1);
4589 }
4590
4591 /*
4592  * Legacy interrupt entry point.
4593  *
4594  * Verifies that the controller generated the interrupt and
4595  * then calls a separate routine to handle the various
4596  * interrupt causes: link, RX, and TX.
4597  */
4598 int bnx2x_intr_legacy(struct bnx2x_softc *sc)
4599 {
4600         struct bnx2x_fastpath *fp;
4601         uint32_t status, mask;
4602         int i, rc = 0;
4603
4604         /*
4605          * 0 for ustorm, 1 for cstorm
4606          * the bits returned from ack_int() are 0-15
4607          * bit 0 = attention status block
4608          * bit 1 = fast path status block
4609          * a mask of 0x2 or more = tx/rx event
4610          * a mask of 1 = slow path event
4611          */
4612
4613         status = bnx2x_ack_int(sc);
4614
4615         /* the interrupt is not for us */
4616         if (unlikely(status == 0)) {
4617                 return 0;
4618         }
4619
4620         PMD_DEBUG_PERIODIC_LOG(DEBUG, sc, "Interrupt status 0x%04x", status);
4621         //bnx2x_dump_status_block(sc);
4622
4623         FOR_EACH_ETH_QUEUE(sc, i) {
4624                 fp = &sc->fp[i];
4625                 mask = (0x2 << (fp->index + CNIC_SUPPORT(sc)));
4626                 if (status & mask) {
4627                 /* acknowledge and disable further fastpath interrupts */
4628                         bnx2x_ack_sb(sc, fp->igu_sb_id, USTORM_ID,
4629                                      0, IGU_INT_DISABLE, 0);
4630                         bnx2x_handle_fp_tq(fp);
4631                         status &= ~mask;
4632                 }
4633         }
4634
4635         if (unlikely(status & 0x1)) {
4636                 /* acknowledge and disable further slowpath interrupts */
4637                 bnx2x_ack_sb(sc, sc->igu_dsb_id, USTORM_ID,
4638                              0, IGU_INT_DISABLE, 0);
4639                 rc = bnx2x_handle_sp_tq(sc);
4640                 status &= ~0x1;
4641         }
4642
4643         if (unlikely(status)) {
4644                 PMD_DRV_LOG(WARNING, sc,
4645                             "Unexpected fastpath status (0x%08x)!", status);
4646         }
4647
4648         return rc;
4649 }
4650
4651 static int bnx2x_init_hw_common_chip(struct bnx2x_softc *sc);
4652 static int bnx2x_init_hw_common(struct bnx2x_softc *sc);
4653 static int bnx2x_init_hw_port(struct bnx2x_softc *sc);
4654 static int bnx2x_init_hw_func(struct bnx2x_softc *sc);
4655 static void bnx2x_reset_common(struct bnx2x_softc *sc);
4656 static void bnx2x_reset_port(struct bnx2x_softc *sc);
4657 static void bnx2x_reset_func(struct bnx2x_softc *sc);
4658 static int bnx2x_init_firmware(struct bnx2x_softc *sc);
4659 static void bnx2x_release_firmware(struct bnx2x_softc *sc);
4660
4661 static struct
4662 ecore_func_sp_drv_ops bnx2x_func_sp_drv = {
4663         .init_hw_cmn_chip = bnx2x_init_hw_common_chip,
4664         .init_hw_cmn = bnx2x_init_hw_common,
4665         .init_hw_port = bnx2x_init_hw_port,
4666         .init_hw_func = bnx2x_init_hw_func,
4667
4668         .reset_hw_cmn = bnx2x_reset_common,
4669         .reset_hw_port = bnx2x_reset_port,
4670         .reset_hw_func = bnx2x_reset_func,
4671
4672         .init_fw = bnx2x_init_firmware,
4673         .release_fw = bnx2x_release_firmware,
4674 };
4675
4676 static void bnx2x_init_func_obj(struct bnx2x_softc *sc)
4677 {
4678         sc->dmae_ready = 0;
4679
4680         PMD_INIT_FUNC_TRACE(sc);
4681
4682         ecore_init_func_obj(sc,
4683                             &sc->func_obj,
4684                             BNX2X_SP(sc, func_rdata),
4685                             (rte_iova_t)BNX2X_SP_MAPPING(sc, func_rdata),
4686                             BNX2X_SP(sc, func_afex_rdata),
4687                             (rte_iova_t)BNX2X_SP_MAPPING(sc, func_afex_rdata),
4688                             &bnx2x_func_sp_drv);
4689 }
4690
4691 static int bnx2x_init_hw(struct bnx2x_softc *sc, uint32_t load_code)
4692 {
4693         struct ecore_func_state_params func_params = { NULL };
4694         int rc;
4695
4696         PMD_INIT_FUNC_TRACE(sc);
4697
4698         /* prepare the parameters for function state transitions */
4699         bnx2x_set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags);
4700
4701         func_params.f_obj = &sc->func_obj;
4702         func_params.cmd = ECORE_F_CMD_HW_INIT;
4703
4704         func_params.params.hw_init.load_phase = load_code;
4705
4706         /*
4707          * Via a plethora of function pointers, we will eventually reach
4708          * bnx2x_init_hw_common(), bnx2x_init_hw_port(), or bnx2x_init_hw_func().
4709          */
4710         rc = ecore_func_state_change(sc, &func_params);
4711
4712         return rc;
4713 }
4714
4715 static void
4716 bnx2x_fill(struct bnx2x_softc *sc, uint32_t addr, int fill, uint32_t len)
4717 {
4718         uint32_t i;
4719
4720         if (!(len % 4) && !(addr % 4)) {
4721                 for (i = 0; i < len; i += 4) {
4722                         REG_WR(sc, (addr + i), fill);
4723                 }
4724         } else {
4725                 for (i = 0; i < len; i++) {
4726                         REG_WR8(sc, (addr + i), fill);
4727                 }
4728         }
4729 }
4730
4731 /* writes FP SP data to FW - data_size in dwords */
4732 static void
4733 bnx2x_wr_fp_sb_data(struct bnx2x_softc *sc, int fw_sb_id, uint32_t * sb_data_p,
4734                   uint32_t data_size)
4735 {
4736         uint32_t index;
4737
4738         for (index = 0; index < data_size; index++) {
4739                 REG_WR(sc,
4740                        (BAR_CSTRORM_INTMEM +
4741                         CSTORM_STATUS_BLOCK_DATA_OFFSET(fw_sb_id) +
4742                         (sizeof(uint32_t) * index)), *(sb_data_p + index));
4743         }
4744 }
4745
4746 static void bnx2x_zero_fp_sb(struct bnx2x_softc *sc, int fw_sb_id)
4747 {
4748         struct hc_status_block_data_e2 sb_data_e2;
4749         struct hc_status_block_data_e1x sb_data_e1x;
4750         uint32_t *sb_data_p;
4751         uint32_t data_size = 0;
4752
4753         if (!CHIP_IS_E1x(sc)) {
4754                 memset(&sb_data_e2, 0, sizeof(struct hc_status_block_data_e2));
4755                 sb_data_e2.common.state = SB_DISABLED;
4756                 sb_data_e2.common.p_func.vf_valid = FALSE;
4757                 sb_data_p = (uint32_t *) & sb_data_e2;
4758                 data_size = (sizeof(struct hc_status_block_data_e2) /
4759                              sizeof(uint32_t));
4760         } else {
4761                 memset(&sb_data_e1x, 0,
4762                        sizeof(struct hc_status_block_data_e1x));
4763                 sb_data_e1x.common.state = SB_DISABLED;
4764                 sb_data_e1x.common.p_func.vf_valid = FALSE;
4765                 sb_data_p = (uint32_t *) & sb_data_e1x;
4766                 data_size = (sizeof(struct hc_status_block_data_e1x) /
4767                              sizeof(uint32_t));
4768         }
4769
4770         bnx2x_wr_fp_sb_data(sc, fw_sb_id, sb_data_p, data_size);
4771
4772         bnx2x_fill(sc,
4773                  (BAR_CSTRORM_INTMEM + CSTORM_STATUS_BLOCK_OFFSET(fw_sb_id)), 0,
4774                  CSTORM_STATUS_BLOCK_SIZE);
4775         bnx2x_fill(sc, (BAR_CSTRORM_INTMEM + CSTORM_SYNC_BLOCK_OFFSET(fw_sb_id)),
4776                  0, CSTORM_SYNC_BLOCK_SIZE);
4777 }
4778
4779 static void
4780 bnx2x_wr_sp_sb_data(struct bnx2x_softc *sc,
4781                   struct hc_sp_status_block_data *sp_sb_data)
4782 {
4783         uint32_t i;
4784
4785         for (i = 0;
4786              i < (sizeof(struct hc_sp_status_block_data) / sizeof(uint32_t));
4787              i++) {
4788                 REG_WR(sc,
4789                        (BAR_CSTRORM_INTMEM +
4790                         CSTORM_SP_STATUS_BLOCK_DATA_OFFSET(SC_FUNC(sc)) +
4791                         (i * sizeof(uint32_t))),
4792                        *((uint32_t *) sp_sb_data + i));
4793         }
4794 }
4795
4796 static void bnx2x_zero_sp_sb(struct bnx2x_softc *sc)
4797 {
4798         struct hc_sp_status_block_data sp_sb_data;
4799
4800         memset(&sp_sb_data, 0, sizeof(struct hc_sp_status_block_data));
4801
4802         sp_sb_data.state = SB_DISABLED;
4803         sp_sb_data.p_func.vf_valid = FALSE;
4804
4805         bnx2x_wr_sp_sb_data(sc, &sp_sb_data);
4806
4807         bnx2x_fill(sc,
4808                  (BAR_CSTRORM_INTMEM +
4809                   CSTORM_SP_STATUS_BLOCK_OFFSET(SC_FUNC(sc))),
4810                  0, CSTORM_SP_STATUS_BLOCK_SIZE);
4811         bnx2x_fill(sc,
4812                  (BAR_CSTRORM_INTMEM +
4813                   CSTORM_SP_SYNC_BLOCK_OFFSET(SC_FUNC(sc))),
4814                  0, CSTORM_SP_SYNC_BLOCK_SIZE);
4815 }
4816
4817 static void
4818 bnx2x_setup_ndsb_state_machine(struct hc_status_block_sm *hc_sm, int igu_sb_id,
4819                              int igu_seg_id)
4820 {
4821         hc_sm->igu_sb_id = igu_sb_id;
4822         hc_sm->igu_seg_id = igu_seg_id;
4823         hc_sm->timer_value = 0xFF;
4824         hc_sm->time_to_expire = 0xFFFFFFFF;
4825 }
4826
4827 static void bnx2x_map_sb_state_machines(struct hc_index_data *index_data)
4828 {
4829         /* zero out state machine indices */
4830
4831         /* rx indices */
4832         index_data[HC_INDEX_ETH_RX_CQ_CONS].flags &= ~HC_INDEX_DATA_SM_ID;
4833
4834         /* tx indices */
4835         index_data[HC_INDEX_OOO_TX_CQ_CONS].flags &= ~HC_INDEX_DATA_SM_ID;
4836         index_data[HC_INDEX_ETH_TX_CQ_CONS_COS0].flags &= ~HC_INDEX_DATA_SM_ID;
4837         index_data[HC_INDEX_ETH_TX_CQ_CONS_COS1].flags &= ~HC_INDEX_DATA_SM_ID;
4838         index_data[HC_INDEX_ETH_TX_CQ_CONS_COS2].flags &= ~HC_INDEX_DATA_SM_ID;
4839
4840         /* map indices */
4841
4842         /* rx indices */
4843         index_data[HC_INDEX_ETH_RX_CQ_CONS].flags |=
4844             (SM_RX_ID << HC_INDEX_DATA_SM_ID_SHIFT);
4845
4846         /* tx indices */
4847         index_data[HC_INDEX_OOO_TX_CQ_CONS].flags |=
4848             (SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT);
4849         index_data[HC_INDEX_ETH_TX_CQ_CONS_COS0].flags |=
4850             (SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT);
4851         index_data[HC_INDEX_ETH_TX_CQ_CONS_COS1].flags |=
4852             (SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT);
4853         index_data[HC_INDEX_ETH_TX_CQ_CONS_COS2].flags |=
4854             (SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT);
4855 }
4856
4857 static void
4858 bnx2x_init_sb(struct bnx2x_softc *sc, rte_iova_t busaddr, int vfid,
4859             uint8_t vf_valid, int fw_sb_id, int igu_sb_id)
4860 {
4861         struct hc_status_block_data_e2 sb_data_e2;
4862         struct hc_status_block_data_e1x sb_data_e1x;
4863         struct hc_status_block_sm *hc_sm_p;
4864         uint32_t *sb_data_p;
4865         int igu_seg_id;
4866         int data_size;
4867
4868         if (CHIP_INT_MODE_IS_BC(sc)) {
4869                 igu_seg_id = HC_SEG_ACCESS_NORM;
4870         } else {
4871                 igu_seg_id = IGU_SEG_ACCESS_NORM;
4872         }
4873
4874         bnx2x_zero_fp_sb(sc, fw_sb_id);
4875
4876         if (!CHIP_IS_E1x(sc)) {
4877                 memset(&sb_data_e2, 0, sizeof(struct hc_status_block_data_e2));
4878                 sb_data_e2.common.state = SB_ENABLED;
4879                 sb_data_e2.common.p_func.pf_id = SC_FUNC(sc);
4880                 sb_data_e2.common.p_func.vf_id = vfid;
4881                 sb_data_e2.common.p_func.vf_valid = vf_valid;
4882                 sb_data_e2.common.p_func.vnic_id = SC_VN(sc);
4883                 sb_data_e2.common.same_igu_sb_1b = TRUE;
4884                 sb_data_e2.common.host_sb_addr.hi = U64_HI(busaddr);
4885                 sb_data_e2.common.host_sb_addr.lo = U64_LO(busaddr);
4886                 hc_sm_p = sb_data_e2.common.state_machine;
4887                 sb_data_p = (uint32_t *) & sb_data_e2;
4888                 data_size = (sizeof(struct hc_status_block_data_e2) /
4889                              sizeof(uint32_t));
4890                 bnx2x_map_sb_state_machines(sb_data_e2.index_data);
4891         } else {
4892                 memset(&sb_data_e1x, 0,
4893                        sizeof(struct hc_status_block_data_e1x));
4894                 sb_data_e1x.common.state = SB_ENABLED;
4895                 sb_data_e1x.common.p_func.pf_id = SC_FUNC(sc);
4896                 sb_data_e1x.common.p_func.vf_id = 0xff;
4897                 sb_data_e1x.common.p_func.vf_valid = FALSE;
4898                 sb_data_e1x.common.p_func.vnic_id = SC_VN(sc);
4899                 sb_data_e1x.common.same_igu_sb_1b = TRUE;
4900                 sb_data_e1x.common.host_sb_addr.hi = U64_HI(busaddr);
4901                 sb_data_e1x.common.host_sb_addr.lo = U64_LO(busaddr);
4902                 hc_sm_p = sb_data_e1x.common.state_machine;
4903                 sb_data_p = (uint32_t *) & sb_data_e1x;
4904                 data_size = (sizeof(struct hc_status_block_data_e1x) /
4905                              sizeof(uint32_t));
4906                 bnx2x_map_sb_state_machines(sb_data_e1x.index_data);
4907         }
4908
4909         bnx2x_setup_ndsb_state_machine(&hc_sm_p[SM_RX_ID], igu_sb_id, igu_seg_id);
4910         bnx2x_setup_ndsb_state_machine(&hc_sm_p[SM_TX_ID], igu_sb_id, igu_seg_id);
4911
4912         /* write indices to HW - PCI guarantees endianity of regpairs */
4913         bnx2x_wr_fp_sb_data(sc, fw_sb_id, sb_data_p, data_size);
4914 }
4915
4916 static uint8_t bnx2x_fp_qzone_id(struct bnx2x_fastpath *fp)
4917 {
4918         if (CHIP_IS_E1x(fp->sc)) {
4919                 return fp->cl_id + SC_PORT(fp->sc) * ETH_MAX_RX_CLIENTS_E1H;
4920         } else {
4921                 return fp->cl_id;
4922         }
4923 }
4924
4925 static uint32_t
4926 bnx2x_rx_ustorm_prods_offset(struct bnx2x_softc *sc, struct bnx2x_fastpath *fp)
4927 {
4928         uint32_t offset = BAR_USTRORM_INTMEM;
4929
4930         if (IS_VF(sc)) {
4931                 return PXP_VF_ADDR_USDM_QUEUES_START +
4932                         (sc->acquire_resp.resc.hw_qid[fp->index] *
4933                          sizeof(struct ustorm_queue_zone_data));
4934         } else if (!CHIP_IS_E1x(sc)) {
4935                 offset += USTORM_RX_PRODS_E2_OFFSET(fp->cl_qzone_id);
4936         } else {
4937                 offset += USTORM_RX_PRODS_E1X_OFFSET(SC_PORT(sc), fp->cl_id);
4938         }
4939
4940         return offset;
4941 }
4942
4943 static void bnx2x_init_eth_fp(struct bnx2x_softc *sc, int idx)
4944 {
4945         struct bnx2x_fastpath *fp = &sc->fp[idx];
4946         uint32_t cids[ECORE_MULTI_TX_COS] = { 0 };
4947         unsigned long q_type = 0;
4948         int cos;
4949
4950         fp->sc = sc;
4951         fp->index = idx;
4952
4953         fp->igu_sb_id = (sc->igu_base_sb + idx + CNIC_SUPPORT(sc));
4954         fp->fw_sb_id = (sc->base_fw_ndsb + idx + CNIC_SUPPORT(sc));
4955
4956         if (CHIP_IS_E1x(sc))
4957                 fp->cl_id = SC_L_ID(sc) + idx;
4958         else
4959 /* want client ID same as IGU SB ID for non-E1 */
4960                 fp->cl_id = fp->igu_sb_id;
4961         fp->cl_qzone_id = bnx2x_fp_qzone_id(fp);
4962
4963         /* setup sb indices */
4964         if (!CHIP_IS_E1x(sc)) {
4965                 fp->sb_index_values = fp->status_block.e2_sb->sb.index_values;
4966                 fp->sb_running_index = fp->status_block.e2_sb->sb.running_index;
4967         } else {
4968                 fp->sb_index_values = fp->status_block.e1x_sb->sb.index_values;
4969                 fp->sb_running_index =
4970                     fp->status_block.e1x_sb->sb.running_index;
4971         }
4972
4973         /* init shortcut */
4974         fp->ustorm_rx_prods_offset = bnx2x_rx_ustorm_prods_offset(sc, fp);
4975
4976         fp->rx_cq_cons_sb = &fp->sb_index_values[HC_INDEX_ETH_RX_CQ_CONS];
4977
4978         for (cos = 0; cos < sc->max_cos; cos++) {
4979                 cids[cos] = idx;
4980         }
4981         fp->tx_cons_sb = &fp->sb_index_values[HC_INDEX_ETH_TX_CQ_CONS_COS0];
4982
4983         /* nothing more for a VF to do */
4984         if (IS_VF(sc)) {
4985                 return;
4986         }
4987
4988         bnx2x_init_sb(sc, fp->sb_dma.paddr, BNX2X_VF_ID_INVALID, FALSE,
4989                     fp->fw_sb_id, fp->igu_sb_id);
4990
4991         bnx2x_update_fp_sb_idx(fp);
4992
4993         /* Configure Queue State object */
4994         bnx2x_set_bit(ECORE_Q_TYPE_HAS_RX, &q_type);
4995         bnx2x_set_bit(ECORE_Q_TYPE_HAS_TX, &q_type);
4996
4997         ecore_init_queue_obj(sc,
4998                              &sc->sp_objs[idx].q_obj,
4999                              fp->cl_id,
5000                              cids,
5001                              sc->max_cos,
5002                              SC_FUNC(sc),
5003                              BNX2X_SP(sc, q_rdata),
5004                              (rte_iova_t)BNX2X_SP_MAPPING(sc, q_rdata),
5005                              q_type);
5006
5007         /* configure classification DBs */
5008         ecore_init_mac_obj(sc,
5009                            &sc->sp_objs[idx].mac_obj,
5010                            fp->cl_id,
5011                            idx,
5012                            SC_FUNC(sc),
5013                            BNX2X_SP(sc, mac_rdata),
5014                            (rte_iova_t)BNX2X_SP_MAPPING(sc, mac_rdata),
5015                            ECORE_FILTER_MAC_PENDING, &sc->sp_state,
5016                            ECORE_OBJ_TYPE_RX_TX, &sc->macs_pool);
5017 }
5018
5019 static void
5020 bnx2x_update_rx_prod(struct bnx2x_softc *sc, struct bnx2x_fastpath *fp,
5021                    uint16_t rx_bd_prod, uint16_t rx_cq_prod)
5022 {
5023         union ustorm_eth_rx_producers rx_prods;
5024         uint32_t i;
5025
5026         /* update producers */
5027         rx_prods.prod.bd_prod = rx_bd_prod;
5028         rx_prods.prod.cqe_prod = rx_cq_prod;
5029         rx_prods.prod.reserved = 0;
5030
5031         /*
5032          * Make sure that the BD and SGE data is updated before updating the
5033          * producers since FW might read the BD/SGE right after the producer
5034          * is updated.
5035          * This is only applicable for weak-ordered memory model archs such
5036          * as IA-64. The following barrier is also mandatory since FW will
5037          * assumes BDs must have buffers.
5038          */
5039         wmb();
5040
5041         for (i = 0; i < (sizeof(rx_prods) / 4); i++) {
5042                 REG_WR(sc,
5043                        (fp->ustorm_rx_prods_offset + (i * 4)),
5044                        rx_prods.raw_data[i]);
5045         }
5046
5047         wmb();                  /* keep prod updates ordered */
5048 }
5049
5050 static void bnx2x_init_rx_rings(struct bnx2x_softc *sc)
5051 {
5052         struct bnx2x_fastpath *fp;
5053         int i;
5054         struct bnx2x_rx_queue *rxq;
5055
5056         for (i = 0; i < sc->num_queues; i++) {
5057                 fp = &sc->fp[i];
5058                 rxq = sc->rx_queues[fp->index];
5059                 if (!rxq) {
5060                         PMD_RX_LOG(ERR, "RX queue is NULL");
5061                         return;
5062                 }
5063
5064                 rxq->rx_bd_head = 0;
5065                 rxq->rx_bd_tail = rxq->nb_rx_desc;
5066                 rxq->rx_cq_head = 0;
5067                 rxq->rx_cq_tail = TOTAL_RCQ_ENTRIES(rxq);
5068                 *fp->rx_cq_cons_sb = 0;
5069
5070                 /*
5071                  * Activate the BD ring...
5072                  * Warning, this will generate an interrupt (to the TSTORM)
5073                  * so this can only be done after the chip is initialized
5074                  */
5075                 bnx2x_update_rx_prod(sc, fp, rxq->rx_bd_tail, rxq->rx_cq_tail);
5076
5077                 if (i != 0) {
5078                         continue;
5079                 }
5080         }
5081 }
5082
5083 static void bnx2x_init_tx_ring_one(struct bnx2x_fastpath *fp)
5084 {
5085         struct bnx2x_tx_queue *txq = fp->sc->tx_queues[fp->index];
5086
5087         fp->tx_db.data.header.header = 1 << DOORBELL_HDR_DB_TYPE_SHIFT;
5088         fp->tx_db.data.zero_fill1 = 0;
5089         fp->tx_db.data.prod = 0;
5090
5091         if (!txq) {
5092                 PMD_TX_LOG(ERR, "ERROR: TX queue is NULL");
5093                 return;
5094         }
5095
5096         txq->tx_pkt_tail = 0;
5097         txq->tx_pkt_head = 0;
5098         txq->tx_bd_tail = 0;
5099         txq->tx_bd_head = 0;
5100 }
5101
5102 static void bnx2x_init_tx_rings(struct bnx2x_softc *sc)
5103 {
5104         int i;
5105
5106         for (i = 0; i < sc->num_queues; i++) {
5107                 bnx2x_init_tx_ring_one(&sc->fp[i]);
5108         }
5109 }
5110
5111 static void bnx2x_init_def_sb(struct bnx2x_softc *sc)
5112 {
5113         struct host_sp_status_block *def_sb = sc->def_sb;
5114         rte_iova_t mapping = sc->def_sb_dma.paddr;
5115         int igu_sp_sb_index;
5116         int igu_seg_id;
5117         int port = SC_PORT(sc);
5118         int func = SC_FUNC(sc);
5119         int reg_offset, reg_offset_en5;
5120         uint64_t section;
5121         int index, sindex;
5122         struct hc_sp_status_block_data sp_sb_data;
5123
5124         memset(&sp_sb_data, 0, sizeof(struct hc_sp_status_block_data));
5125
5126         if (CHIP_INT_MODE_IS_BC(sc)) {
5127                 igu_sp_sb_index = DEF_SB_IGU_ID;
5128                 igu_seg_id = HC_SEG_ACCESS_DEF;
5129         } else {
5130                 igu_sp_sb_index = sc->igu_dsb_id;
5131                 igu_seg_id = IGU_SEG_ACCESS_DEF;
5132         }
5133
5134         /* attentions */
5135         section = ((uint64_t) mapping +
5136                    offsetof(struct host_sp_status_block, atten_status_block));
5137         def_sb->atten_status_block.status_block_id = igu_sp_sb_index;
5138         sc->attn_state = 0;
5139
5140         reg_offset = (port) ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 :
5141             MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0;
5142
5143         reg_offset_en5 = (port) ? MISC_REG_AEU_ENABLE5_FUNC_1_OUT_0 :
5144             MISC_REG_AEU_ENABLE5_FUNC_0_OUT_0;
5145
5146         for (index = 0; index < MAX_DYNAMIC_ATTN_GRPS; index++) {
5147 /* take care of sig[0]..sig[4] */
5148                 for (sindex = 0; sindex < 4; sindex++) {
5149                         sc->attn_group[index].sig[sindex] =
5150                             REG_RD(sc,
5151                                    (reg_offset + (sindex * 0x4) +
5152                                     (0x10 * index)));
5153                 }
5154
5155                 if (!CHIP_IS_E1x(sc)) {
5156                         /*
5157                          * enable5 is separate from the rest of the registers,
5158                          * and the address skip is 4 and not 16 between the
5159                          * different groups
5160                          */
5161                         sc->attn_group[index].sig[4] =
5162                             REG_RD(sc, (reg_offset_en5 + (0x4 * index)));
5163                 } else {
5164                         sc->attn_group[index].sig[4] = 0;
5165                 }
5166         }
5167
5168         if (sc->devinfo.int_block == INT_BLOCK_HC) {
5169                 reg_offset =
5170                     port ? HC_REG_ATTN_MSG1_ADDR_L : HC_REG_ATTN_MSG0_ADDR_L;
5171                 REG_WR(sc, reg_offset, U64_LO(section));
5172                 REG_WR(sc, (reg_offset + 4), U64_HI(section));
5173         } else if (!CHIP_IS_E1x(sc)) {
5174                 REG_WR(sc, IGU_REG_ATTN_MSG_ADDR_L, U64_LO(section));
5175                 REG_WR(sc, IGU_REG_ATTN_MSG_ADDR_H, U64_HI(section));
5176         }
5177
5178         section = ((uint64_t) mapping +
5179                    offsetof(struct host_sp_status_block, sp_sb));
5180
5181         bnx2x_zero_sp_sb(sc);
5182
5183         /* PCI guarantees endianity of regpair */
5184         sp_sb_data.state = SB_ENABLED;
5185         sp_sb_data.host_sb_addr.lo = U64_LO(section);
5186         sp_sb_data.host_sb_addr.hi = U64_HI(section);
5187         sp_sb_data.igu_sb_id = igu_sp_sb_index;
5188         sp_sb_data.igu_seg_id = igu_seg_id;
5189         sp_sb_data.p_func.pf_id = func;
5190         sp_sb_data.p_func.vnic_id = SC_VN(sc);
5191         sp_sb_data.p_func.vf_id = 0xff;
5192
5193         bnx2x_wr_sp_sb_data(sc, &sp_sb_data);
5194
5195         bnx2x_ack_sb(sc, sc->igu_dsb_id, USTORM_ID, 0, IGU_INT_ENABLE, 0);
5196 }
5197
5198 static void bnx2x_init_sp_ring(struct bnx2x_softc *sc)
5199 {
5200         atomic_store_rel_long(&sc->cq_spq_left, MAX_SPQ_PENDING);
5201         sc->spq_prod_idx = 0;
5202         sc->dsb_sp_prod =
5203             &sc->def_sb->sp_sb.index_values[HC_SP_INDEX_ETH_DEF_CONS];
5204         sc->spq_prod_bd = sc->spq;
5205         sc->spq_last_bd = (sc->spq_prod_bd + MAX_SP_DESC_CNT);
5206 }
5207
5208 static void bnx2x_init_eq_ring(struct bnx2x_softc *sc)
5209 {
5210         union event_ring_elem *elem;
5211         int i;
5212
5213         for (i = 1; i <= NUM_EQ_PAGES; i++) {
5214                 elem = &sc->eq[EQ_DESC_CNT_PAGE * i - 1];
5215
5216                 elem->next_page.addr.hi = htole32(U64_HI(sc->eq_dma.paddr +
5217                                                          BNX2X_PAGE_SIZE *
5218                                                          (i % NUM_EQ_PAGES)));
5219                 elem->next_page.addr.lo = htole32(U64_LO(sc->eq_dma.paddr +
5220                                                          BNX2X_PAGE_SIZE *
5221                                                          (i % NUM_EQ_PAGES)));
5222         }
5223
5224         sc->eq_cons = 0;
5225         sc->eq_prod = NUM_EQ_DESC;
5226         sc->eq_cons_sb = &sc->def_sb->sp_sb.index_values[HC_SP_INDEX_EQ_CONS];
5227
5228         atomic_store_rel_long(&sc->eq_spq_left,
5229                               (min((MAX_SP_DESC_CNT - MAX_SPQ_PENDING),
5230                                    NUM_EQ_DESC) - 1));
5231 }
5232
5233 static void bnx2x_init_internal_common(struct bnx2x_softc *sc)
5234 {
5235         int i;
5236
5237         if (IS_MF_SI(sc)) {
5238 /*
5239  * In switch independent mode, the TSTORM needs to accept
5240  * packets that failed classification, since approximate match
5241  * mac addresses aren't written to NIG LLH.
5242  */
5243                 REG_WR8(sc,
5244                         (BAR_TSTRORM_INTMEM +
5245                          TSTORM_ACCEPT_CLASSIFY_FAILED_OFFSET), 2);
5246         } else
5247                 REG_WR8(sc,
5248                         (BAR_TSTRORM_INTMEM +
5249                          TSTORM_ACCEPT_CLASSIFY_FAILED_OFFSET), 0);
5250
5251         /*
5252          * Zero this manually as its initialization is currently missing
5253          * in the initTool.
5254          */
5255         for (i = 0; i < (USTORM_AGG_DATA_SIZE >> 2); i++) {
5256                 REG_WR(sc,
5257                        (BAR_USTRORM_INTMEM + USTORM_AGG_DATA_OFFSET + (i * 4)),
5258                        0);
5259         }
5260
5261         if (!CHIP_IS_E1x(sc)) {
5262                 REG_WR8(sc, (BAR_CSTRORM_INTMEM + CSTORM_IGU_MODE_OFFSET),
5263                         CHIP_INT_MODE_IS_BC(sc) ? HC_IGU_BC_MODE :
5264                         HC_IGU_NBC_MODE);
5265         }
5266 }
5267
5268 static void bnx2x_init_internal(struct bnx2x_softc *sc, uint32_t load_code)
5269 {
5270         switch (load_code) {
5271         case FW_MSG_CODE_DRV_LOAD_COMMON:
5272         case FW_MSG_CODE_DRV_LOAD_COMMON_CHIP:
5273                 bnx2x_init_internal_common(sc);
5274                 /* no break */
5275
5276         case FW_MSG_CODE_DRV_LOAD_PORT:
5277                 /* nothing to do */
5278                 /* no break */
5279
5280         case FW_MSG_CODE_DRV_LOAD_FUNCTION:
5281                 /* internal memory per function is initialized inside bnx2x_pf_init */
5282                 break;
5283
5284         default:
5285                 PMD_DRV_LOG(NOTICE, sc, "Unknown load_code (0x%x) from MCP",
5286                             load_code);
5287                 break;
5288         }
5289 }
5290
5291 static void
5292 storm_memset_func_cfg(struct bnx2x_softc *sc,
5293                       struct tstorm_eth_function_common_config *tcfg,
5294                       uint16_t abs_fid)
5295 {
5296         uint32_t addr;
5297         size_t size;
5298
5299         addr = (BAR_TSTRORM_INTMEM +
5300                 TSTORM_FUNCTION_COMMON_CONFIG_OFFSET(abs_fid));
5301         size = sizeof(struct tstorm_eth_function_common_config);
5302         ecore_storm_memset_struct(sc, addr, size, (uint32_t *) tcfg);
5303 }
5304
5305 static void bnx2x_func_init(struct bnx2x_softc *sc, struct bnx2x_func_init_params *p)
5306 {
5307         struct tstorm_eth_function_common_config tcfg = { 0 };
5308
5309         if (CHIP_IS_E1x(sc)) {
5310                 storm_memset_func_cfg(sc, &tcfg, p->func_id);
5311         }
5312
5313         /* Enable the function in the FW */
5314         storm_memset_vf_to_pf(sc, p->func_id, p->pf_id);
5315         storm_memset_func_en(sc, p->func_id, 1);
5316
5317         /* spq */
5318         if (p->func_flgs & FUNC_FLG_SPQ) {
5319                 storm_memset_spq_addr(sc, p->spq_map, p->func_id);
5320                 REG_WR(sc,
5321                        (XSEM_REG_FAST_MEMORY +
5322                         XSTORM_SPQ_PROD_OFFSET(p->func_id)), p->spq_prod);
5323         }
5324 }
5325
5326 /*
5327  * Calculates the sum of vn_min_rates.
5328  * It's needed for further normalizing of the min_rates.
5329  * Returns:
5330  *   sum of vn_min_rates.
5331  *     or
5332  *   0 - if all the min_rates are 0.
5333  * In the later case fainess algorithm should be deactivated.
5334  * If all min rates are not zero then those that are zeroes will be set to 1.
5335  */
5336 static void bnx2x_calc_vn_min(struct bnx2x_softc *sc, struct cmng_init_input *input)
5337 {
5338         uint32_t vn_cfg;
5339         uint32_t vn_min_rate;
5340         int all_zero = 1;
5341         int vn;
5342
5343         for (vn = VN_0; vn < SC_MAX_VN_NUM(sc); vn++) {
5344                 vn_cfg = sc->devinfo.mf_info.mf_config[vn];
5345                 vn_min_rate = (((vn_cfg & FUNC_MF_CFG_MIN_BW_MASK) >>
5346                                 FUNC_MF_CFG_MIN_BW_SHIFT) * 100);
5347
5348                 if (vn_cfg & FUNC_MF_CFG_FUNC_HIDE) {
5349                         /* skip hidden VNs */
5350                         vn_min_rate = 0;
5351                 } else if (!vn_min_rate) {
5352                         /* If min rate is zero - set it to 100 */
5353                         vn_min_rate = DEF_MIN_RATE;
5354                 } else {
5355                         all_zero = 0;
5356                 }
5357
5358                 input->vnic_min_rate[vn] = vn_min_rate;
5359         }
5360
5361         /* if ETS or all min rates are zeros - disable fairness */
5362         if (all_zero) {
5363                 input->flags.cmng_enables &= ~CMNG_FLAGS_PER_PORT_FAIRNESS_VN;
5364         } else {
5365                 input->flags.cmng_enables |= CMNG_FLAGS_PER_PORT_FAIRNESS_VN;
5366         }
5367 }
5368
5369 static uint16_t
5370 bnx2x_extract_max_cfg(__rte_unused struct bnx2x_softc *sc, uint32_t mf_cfg)
5371 {
5372         uint16_t max_cfg = ((mf_cfg & FUNC_MF_CFG_MAX_BW_MASK) >>
5373                             FUNC_MF_CFG_MAX_BW_SHIFT);
5374
5375         if (!max_cfg) {
5376                 PMD_DRV_LOG(DEBUG, sc,
5377                             "Max BW configured to 0 - using 100 instead");
5378                 max_cfg = 100;
5379         }
5380
5381         return max_cfg;
5382 }
5383
5384 static void
5385 bnx2x_calc_vn_max(struct bnx2x_softc *sc, int vn, struct cmng_init_input *input)
5386 {
5387         uint16_t vn_max_rate;
5388         uint32_t vn_cfg = sc->devinfo.mf_info.mf_config[vn];
5389         uint32_t max_cfg;
5390
5391         if (vn_cfg & FUNC_MF_CFG_FUNC_HIDE) {
5392                 vn_max_rate = 0;
5393         } else {
5394                 max_cfg = bnx2x_extract_max_cfg(sc, vn_cfg);
5395
5396                 if (IS_MF_SI(sc)) {
5397                         /* max_cfg in percents of linkspeed */
5398                         vn_max_rate =
5399                             ((sc->link_vars.line_speed * max_cfg) / 100);
5400                 } else {        /* SD modes */
5401                         /* max_cfg is absolute in 100Mb units */
5402                         vn_max_rate = (max_cfg * 100);
5403                 }
5404         }
5405
5406         input->vnic_max_rate[vn] = vn_max_rate;
5407 }
5408
5409 static void
5410 bnx2x_cmng_fns_init(struct bnx2x_softc *sc, uint8_t read_cfg, uint8_t cmng_type)
5411 {
5412         struct cmng_init_input input;
5413         int vn;
5414
5415         memset(&input, 0, sizeof(struct cmng_init_input));
5416
5417         input.port_rate = sc->link_vars.line_speed;
5418
5419         if (cmng_type == CMNG_FNS_MINMAX) {
5420 /* read mf conf from shmem */
5421                 if (read_cfg) {
5422                         bnx2x_read_mf_cfg(sc);
5423                 }
5424
5425 /* get VN min rate and enable fairness if not 0 */
5426                 bnx2x_calc_vn_min(sc, &input);
5427
5428 /* get VN max rate */
5429                 if (sc->port.pmf) {
5430                         for (vn = VN_0; vn < SC_MAX_VN_NUM(sc); vn++) {
5431                                 bnx2x_calc_vn_max(sc, vn, &input);
5432                         }
5433                 }
5434
5435 /* always enable rate shaping and fairness */
5436                 input.flags.cmng_enables |= CMNG_FLAGS_PER_PORT_RATE_SHAPING_VN;
5437
5438                 ecore_init_cmng(&input, &sc->cmng);
5439                 return;
5440         }
5441 }
5442
5443 static int bnx2x_get_cmng_fns_mode(struct bnx2x_softc *sc)
5444 {
5445         if (CHIP_REV_IS_SLOW(sc)) {
5446                 return CMNG_FNS_NONE;
5447         }
5448
5449         if (IS_MF(sc)) {
5450                 return CMNG_FNS_MINMAX;
5451         }
5452
5453         return CMNG_FNS_NONE;
5454 }
5455
5456 static void
5457 storm_memset_cmng(struct bnx2x_softc *sc, struct cmng_init *cmng, uint8_t port)
5458 {
5459         int vn;
5460         int func;
5461         uint32_t addr;
5462         size_t size;
5463
5464         addr = (BAR_XSTRORM_INTMEM + XSTORM_CMNG_PER_PORT_VARS_OFFSET(port));
5465         size = sizeof(struct cmng_struct_per_port);
5466         ecore_storm_memset_struct(sc, addr, size, (uint32_t *) & cmng->port);
5467
5468         for (vn = VN_0; vn < SC_MAX_VN_NUM(sc); vn++) {
5469                 func = func_by_vn(sc, vn);
5470
5471                 addr = (BAR_XSTRORM_INTMEM +
5472                         XSTORM_RATE_SHAPING_PER_VN_VARS_OFFSET(func));
5473                 size = sizeof(struct rate_shaping_vars_per_vn);
5474                 ecore_storm_memset_struct(sc, addr, size,
5475                                           (uint32_t *) & cmng->
5476                                           vnic.vnic_max_rate[vn]);
5477
5478                 addr = (BAR_XSTRORM_INTMEM +
5479                         XSTORM_FAIRNESS_PER_VN_VARS_OFFSET(func));
5480                 size = sizeof(struct fairness_vars_per_vn);
5481                 ecore_storm_memset_struct(sc, addr, size,
5482                                           (uint32_t *) & cmng->
5483                                           vnic.vnic_min_rate[vn]);
5484         }
5485 }
5486
5487 static void bnx2x_pf_init(struct bnx2x_softc *sc)
5488 {
5489         struct bnx2x_func_init_params func_init;
5490         struct event_ring_data eq_data;
5491         uint16_t flags;
5492
5493         memset(&eq_data, 0, sizeof(struct event_ring_data));
5494         memset(&func_init, 0, sizeof(struct bnx2x_func_init_params));
5495
5496         if (!CHIP_IS_E1x(sc)) {
5497 /* reset IGU PF statistics: MSIX + ATTN */
5498 /* PF */
5499                 REG_WR(sc,
5500                        (IGU_REG_STATISTIC_NUM_MESSAGE_SENT +
5501                         (BNX2X_IGU_STAS_MSG_VF_CNT * 4) +
5502                         ((CHIP_IS_MODE_4_PORT(sc) ? SC_FUNC(sc) : SC_VN(sc)) *
5503                          4)), 0);
5504 /* ATTN */
5505                 REG_WR(sc,
5506                        (IGU_REG_STATISTIC_NUM_MESSAGE_SENT +
5507                         (BNX2X_IGU_STAS_MSG_VF_CNT * 4) +
5508                         (BNX2X_IGU_STAS_MSG_PF_CNT * 4) +
5509                         ((CHIP_IS_MODE_4_PORT(sc) ? SC_FUNC(sc) : SC_VN(sc)) *
5510                          4)), 0);
5511         }
5512
5513         /* function setup flags */
5514         flags = (FUNC_FLG_STATS | FUNC_FLG_LEADING | FUNC_FLG_SPQ);
5515
5516         func_init.func_flgs = flags;
5517         func_init.pf_id = SC_FUNC(sc);
5518         func_init.func_id = SC_FUNC(sc);
5519         func_init.spq_map = sc->spq_dma.paddr;
5520         func_init.spq_prod = sc->spq_prod_idx;
5521
5522         bnx2x_func_init(sc, &func_init);
5523
5524         memset(&sc->cmng, 0, sizeof(struct cmng_struct_per_port));
5525
5526         /*
5527          * Congestion management values depend on the link rate.
5528          * There is no active link so initial link rate is set to 10Gbps.
5529          * When the link comes up the congestion management values are
5530          * re-calculated according to the actual link rate.
5531          */
5532         sc->link_vars.line_speed = SPEED_10000;
5533         bnx2x_cmng_fns_init(sc, TRUE, bnx2x_get_cmng_fns_mode(sc));
5534
5535         /* Only the PMF sets the HW */
5536         if (sc->port.pmf) {
5537                 storm_memset_cmng(sc, &sc->cmng, SC_PORT(sc));
5538         }
5539
5540         /* init Event Queue - PCI bus guarantees correct endainity */
5541         eq_data.base_addr.hi = U64_HI(sc->eq_dma.paddr);
5542         eq_data.base_addr.lo = U64_LO(sc->eq_dma.paddr);
5543         eq_data.producer = sc->eq_prod;
5544         eq_data.index_id = HC_SP_INDEX_EQ_CONS;
5545         eq_data.sb_id = DEF_SB_ID;
5546         storm_memset_eq_data(sc, &eq_data, SC_FUNC(sc));
5547 }
5548
5549 static void bnx2x_hc_int_enable(struct bnx2x_softc *sc)
5550 {
5551         int port = SC_PORT(sc);
5552         uint32_t addr = (port) ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0;
5553         uint32_t val = REG_RD(sc, addr);
5554         uint8_t msix = (sc->interrupt_mode == INTR_MODE_MSIX)
5555             || (sc->interrupt_mode == INTR_MODE_SINGLE_MSIX);
5556         uint8_t single_msix = (sc->interrupt_mode == INTR_MODE_SINGLE_MSIX);
5557         uint8_t msi = (sc->interrupt_mode == INTR_MODE_MSI);
5558
5559         if (msix) {
5560                 val &= ~(HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
5561                          HC_CONFIG_0_REG_INT_LINE_EN_0);
5562                 val |= (HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
5563                         HC_CONFIG_0_REG_ATTN_BIT_EN_0);
5564                 if (single_msix) {
5565                         val |= HC_CONFIG_0_REG_SINGLE_ISR_EN_0;
5566                 }
5567         } else if (msi) {
5568                 val &= ~HC_CONFIG_0_REG_INT_LINE_EN_0;
5569                 val |= (HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
5570                         HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
5571                         HC_CONFIG_0_REG_ATTN_BIT_EN_0);
5572         } else {
5573                 val |= (HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
5574                         HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
5575                         HC_CONFIG_0_REG_INT_LINE_EN_0 |
5576                         HC_CONFIG_0_REG_ATTN_BIT_EN_0);
5577
5578                 REG_WR(sc, addr, val);
5579
5580                 val &= ~HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0;
5581         }
5582
5583         REG_WR(sc, addr, val);
5584
5585         /* ensure that HC_CONFIG is written before leading/trailing edge config */
5586         mb();
5587
5588         /* init leading/trailing edge */
5589         if (IS_MF(sc)) {
5590                 val = (0xee0f | (1 << (SC_VN(sc) + 4)));
5591                 if (sc->port.pmf) {
5592                         /* enable nig and gpio3 attention */
5593                         val |= 0x1100;
5594                 }
5595         } else {
5596                 val = 0xffff;
5597         }
5598
5599         REG_WR(sc, (HC_REG_TRAILING_EDGE_0 + port * 8), val);
5600         REG_WR(sc, (HC_REG_LEADING_EDGE_0 + port * 8), val);
5601
5602         /* make sure that interrupts are indeed enabled from here on */
5603         mb();
5604 }
5605
5606 static void bnx2x_igu_int_enable(struct bnx2x_softc *sc)
5607 {
5608         uint32_t val;
5609         uint8_t msix = (sc->interrupt_mode == INTR_MODE_MSIX)
5610             || (sc->interrupt_mode == INTR_MODE_SINGLE_MSIX);
5611         uint8_t single_msix = (sc->interrupt_mode == INTR_MODE_SINGLE_MSIX);
5612         uint8_t msi = (sc->interrupt_mode == INTR_MODE_MSI);
5613
5614         val = REG_RD(sc, IGU_REG_PF_CONFIGURATION);
5615
5616         if (msix) {
5617                 val &= ~(IGU_PF_CONF_INT_LINE_EN | IGU_PF_CONF_SINGLE_ISR_EN);
5618                 val |= (IGU_PF_CONF_MSI_MSIX_EN | IGU_PF_CONF_ATTN_BIT_EN);
5619                 if (single_msix) {
5620                         val |= IGU_PF_CONF_SINGLE_ISR_EN;
5621                 }
5622         } else if (msi) {
5623                 val &= ~IGU_PF_CONF_INT_LINE_EN;
5624                 val |= (IGU_PF_CONF_MSI_MSIX_EN |
5625                         IGU_PF_CONF_ATTN_BIT_EN | IGU_PF_CONF_SINGLE_ISR_EN);
5626         } else {
5627                 val &= ~IGU_PF_CONF_MSI_MSIX_EN;
5628                 val |= (IGU_PF_CONF_INT_LINE_EN |
5629                         IGU_PF_CONF_ATTN_BIT_EN | IGU_PF_CONF_SINGLE_ISR_EN);
5630         }
5631
5632         /* clean previous status - need to configure igu prior to ack */
5633         if ((!msix) || single_msix) {
5634                 REG_WR(sc, IGU_REG_PF_CONFIGURATION, val);
5635                 bnx2x_ack_int(sc);
5636         }
5637
5638         val |= IGU_PF_CONF_FUNC_EN;
5639
5640         PMD_DRV_LOG(DEBUG, sc, "write 0x%x to IGU mode %s",
5641                     val, ((msix) ? "MSI-X" : ((msi) ? "MSI" : "INTx")));
5642
5643         REG_WR(sc, IGU_REG_PF_CONFIGURATION, val);
5644
5645         mb();
5646
5647         /* init leading/trailing edge */
5648         if (IS_MF(sc)) {
5649                 val = (0xee0f | (1 << (SC_VN(sc) + 4)));
5650                 if (sc->port.pmf) {
5651                         /* enable nig and gpio3 attention */
5652                         val |= 0x1100;
5653                 }
5654         } else {
5655                 val = 0xffff;
5656         }
5657
5658         REG_WR(sc, IGU_REG_TRAILING_EDGE_LATCH, val);
5659         REG_WR(sc, IGU_REG_LEADING_EDGE_LATCH, val);
5660
5661         /* make sure that interrupts are indeed enabled from here on */
5662         mb();
5663 }
5664
5665 static void bnx2x_int_enable(struct bnx2x_softc *sc)
5666 {
5667         if (sc->devinfo.int_block == INT_BLOCK_HC) {
5668                 bnx2x_hc_int_enable(sc);
5669         } else {
5670                 bnx2x_igu_int_enable(sc);
5671         }
5672 }
5673
5674 static void bnx2x_hc_int_disable(struct bnx2x_softc *sc)
5675 {
5676         int port = SC_PORT(sc);
5677         uint32_t addr = (port) ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0;
5678         uint32_t val = REG_RD(sc, addr);
5679
5680         val &= ~(HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
5681                  HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
5682                  HC_CONFIG_0_REG_INT_LINE_EN_0 | HC_CONFIG_0_REG_ATTN_BIT_EN_0);
5683         /* flush all outstanding writes */
5684         mb();
5685
5686         REG_WR(sc, addr, val);
5687         if (REG_RD(sc, addr) != val) {
5688                 PMD_DRV_LOG(ERR, sc, "proper val not read from HC IGU!");
5689         }
5690 }
5691
5692 static void bnx2x_igu_int_disable(struct bnx2x_softc *sc)
5693 {
5694         uint32_t val = REG_RD(sc, IGU_REG_PF_CONFIGURATION);
5695
5696         val &= ~(IGU_PF_CONF_MSI_MSIX_EN |
5697                  IGU_PF_CONF_INT_LINE_EN | IGU_PF_CONF_ATTN_BIT_EN);
5698
5699         PMD_DRV_LOG(DEBUG, sc, "write %x to IGU", val);
5700
5701         /* flush all outstanding writes */
5702         mb();
5703
5704         REG_WR(sc, IGU_REG_PF_CONFIGURATION, val);
5705         if (REG_RD(sc, IGU_REG_PF_CONFIGURATION) != val) {
5706                 PMD_DRV_LOG(ERR, sc, "proper val not read from IGU!");
5707         }
5708 }
5709
5710 static void bnx2x_int_disable(struct bnx2x_softc *sc)
5711 {
5712         if (sc->devinfo.int_block == INT_BLOCK_HC) {
5713                 bnx2x_hc_int_disable(sc);
5714         } else {
5715                 bnx2x_igu_int_disable(sc);
5716         }
5717 }
5718
5719 static void bnx2x_nic_init(struct bnx2x_softc *sc, int load_code)
5720 {
5721         int i;
5722
5723         PMD_INIT_FUNC_TRACE(sc);
5724
5725         for (i = 0; i < sc->num_queues; i++) {
5726                 bnx2x_init_eth_fp(sc, i);
5727         }
5728
5729         rmb();                  /* ensure status block indices were read */
5730
5731         bnx2x_init_rx_rings(sc);
5732         bnx2x_init_tx_rings(sc);
5733
5734         if (IS_VF(sc)) {
5735                 bnx2x_memset_stats(sc);
5736                 return;
5737         }
5738
5739         /* initialize MOD_ABS interrupts */
5740         elink_init_mod_abs_int(sc, &sc->link_vars,
5741                                sc->devinfo.chip_id,
5742                                sc->devinfo.shmem_base,
5743                                sc->devinfo.shmem2_base, SC_PORT(sc));
5744
5745         bnx2x_init_def_sb(sc);
5746         bnx2x_update_dsb_idx(sc);
5747         bnx2x_init_sp_ring(sc);
5748         bnx2x_init_eq_ring(sc);
5749         bnx2x_init_internal(sc, load_code);
5750         bnx2x_pf_init(sc);
5751         bnx2x_stats_init(sc);
5752
5753         /* flush all before enabling interrupts */
5754         mb();
5755
5756         bnx2x_int_enable(sc);
5757
5758         /* check for SPIO5 */
5759         bnx2x_attn_int_deasserted0(sc,
5760                                  REG_RD(sc,
5761                                         (MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 +
5762                                          SC_PORT(sc) * 4)) &
5763                                  AEU_INPUTS_ATTN_BITS_SPIO5);
5764 }
5765
5766 static void bnx2x_init_objs(struct bnx2x_softc *sc)
5767 {
5768         /* mcast rules must be added to tx if tx switching is enabled */
5769         ecore_obj_type o_type;
5770         if (sc->flags & BNX2X_TX_SWITCHING)
5771                 o_type = ECORE_OBJ_TYPE_RX_TX;
5772         else
5773                 o_type = ECORE_OBJ_TYPE_RX;
5774
5775         /* RX_MODE controlling object */
5776         ecore_init_rx_mode_obj(sc, &sc->rx_mode_obj);
5777
5778         /* multicast configuration controlling object */
5779         ecore_init_mcast_obj(sc,
5780                              &sc->mcast_obj,
5781                              sc->fp[0].cl_id,
5782                              sc->fp[0].index,
5783                              SC_FUNC(sc),
5784                              SC_FUNC(sc),
5785                              BNX2X_SP(sc, mcast_rdata),
5786                              (rte_iova_t)BNX2X_SP_MAPPING(sc, mcast_rdata),
5787                              ECORE_FILTER_MCAST_PENDING,
5788                              &sc->sp_state, o_type);
5789
5790         /* Setup CAM credit pools */
5791         ecore_init_mac_credit_pool(sc,
5792                                    &sc->macs_pool,
5793                                    SC_FUNC(sc),
5794                                    CHIP_IS_E1x(sc) ? VNICS_PER_PORT(sc) :
5795                                    VNICS_PER_PATH(sc));
5796
5797         ecore_init_vlan_credit_pool(sc,
5798                                     &sc->vlans_pool,
5799                                     SC_ABS_FUNC(sc) >> 1,
5800                                     CHIP_IS_E1x(sc) ? VNICS_PER_PORT(sc) :
5801                                     VNICS_PER_PATH(sc));
5802
5803         /* RSS configuration object */
5804         ecore_init_rss_config_obj(&sc->rss_conf_obj,
5805                                   sc->fp[0].cl_id,
5806                                   sc->fp[0].index,
5807                                   SC_FUNC(sc),
5808                                   SC_FUNC(sc),
5809                                   BNX2X_SP(sc, rss_rdata),
5810                                   (rte_iova_t)BNX2X_SP_MAPPING(sc, rss_rdata),
5811                                   ECORE_FILTER_RSS_CONF_PENDING,
5812                                   &sc->sp_state, ECORE_OBJ_TYPE_RX);
5813 }
5814
5815 /*
5816  * Initialize the function. This must be called before sending CLIENT_SETUP
5817  * for the first client.
5818  */
5819 static int bnx2x_func_start(struct bnx2x_softc *sc)
5820 {
5821         struct ecore_func_state_params func_params = { NULL };
5822         struct ecore_func_start_params *start_params =
5823             &func_params.params.start;
5824
5825         /* Prepare parameters for function state transitions */
5826         bnx2x_set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags);
5827
5828         func_params.f_obj = &sc->func_obj;
5829         func_params.cmd = ECORE_F_CMD_START;
5830
5831         /* Function parameters */
5832         start_params->mf_mode = sc->devinfo.mf_info.mf_mode;
5833         start_params->sd_vlan_tag = OVLAN(sc);
5834
5835         if (CHIP_IS_E2(sc) || CHIP_IS_E3(sc)) {
5836                 start_params->network_cos_mode = STATIC_COS;
5837         } else {                /* CHIP_IS_E1X */
5838                 start_params->network_cos_mode = FW_WRR;
5839         }
5840
5841         start_params->gre_tunnel_mode = 0;
5842         start_params->gre_tunnel_rss = 0;
5843
5844         return ecore_func_state_change(sc, &func_params);
5845 }
5846
5847 static int bnx2x_set_power_state(struct bnx2x_softc *sc, uint8_t state)
5848 {
5849         uint16_t pmcsr;
5850
5851         /* If there is no power capability, silently succeed */
5852         if (!(sc->devinfo.pcie_cap_flags & BNX2X_PM_CAPABLE_FLAG)) {
5853                 PMD_DRV_LOG(INFO, sc, "No power capability");
5854                 return 0;
5855         }
5856
5857         pci_read(sc, (sc->devinfo.pcie_pm_cap_reg + PCIR_POWER_STATUS), &pmcsr,
5858                  2);
5859
5860         switch (state) {
5861         case PCI_PM_D0:
5862                 pci_write_word(sc,
5863                                (sc->devinfo.pcie_pm_cap_reg +
5864                                 PCIR_POWER_STATUS),
5865                                ((pmcsr & ~PCIM_PSTAT_DMASK) | PCIM_PSTAT_PME));
5866
5867                 if (pmcsr & PCIM_PSTAT_DMASK) {
5868                         /* delay required during transition out of D3hot */
5869                         DELAY(20000);
5870                 }
5871
5872                 break;
5873
5874         case PCI_PM_D3hot:
5875                 /* don't shut down the power for emulation and FPGA */
5876                 if (CHIP_REV_IS_SLOW(sc)) {
5877                         return 0;
5878                 }
5879
5880                 pmcsr &= ~PCIM_PSTAT_DMASK;
5881                 pmcsr |= PCIM_PSTAT_D3;
5882
5883                 if (sc->wol) {
5884                         pmcsr |= PCIM_PSTAT_PMEENABLE;
5885                 }
5886
5887                 pci_write_long(sc,
5888                                (sc->devinfo.pcie_pm_cap_reg +
5889                                 PCIR_POWER_STATUS), pmcsr);
5890
5891                 /*
5892                  * No more memory access after this point until device is brought back
5893                  * to D0 state.
5894                  */
5895                 break;
5896
5897         default:
5898                 PMD_DRV_LOG(NOTICE, sc, "Can't support PCI power state = %d",
5899                             state);
5900                 return -1;
5901         }
5902
5903         return 0;
5904 }
5905
5906 /* return true if succeeded to acquire the lock */
5907 static uint8_t bnx2x_trylock_hw_lock(struct bnx2x_softc *sc, uint32_t resource)
5908 {
5909         uint32_t lock_status;
5910         uint32_t resource_bit = (1 << resource);
5911         int func = SC_FUNC(sc);
5912         uint32_t hw_lock_control_reg;
5913
5914         /* Validating that the resource is within range */
5915         if (resource > HW_LOCK_MAX_RESOURCE_VALUE) {
5916                 PMD_DRV_LOG(INFO, sc,
5917                             "resource(0x%x) > HW_LOCK_MAX_RESOURCE_VALUE(0x%x)",
5918                             resource, HW_LOCK_MAX_RESOURCE_VALUE);
5919                 return FALSE;
5920         }
5921
5922         if (func <= 5) {
5923                 hw_lock_control_reg = (MISC_REG_DRIVER_CONTROL_1 + func * 8);
5924         } else {
5925                 hw_lock_control_reg =
5926                     (MISC_REG_DRIVER_CONTROL_7 + (func - 6) * 8);
5927         }
5928
5929         /* try to acquire the lock */
5930         REG_WR(sc, hw_lock_control_reg + 4, resource_bit);
5931         lock_status = REG_RD(sc, hw_lock_control_reg);
5932         if (lock_status & resource_bit) {
5933                 return TRUE;
5934         }
5935
5936         PMD_DRV_LOG(NOTICE, sc, "Failed to get a resource lock 0x%x", resource);
5937
5938         return FALSE;
5939 }
5940
5941 /*
5942  * Get the recovery leader resource id according to the engine this function
5943  * belongs to. Currently only only 2 engines is supported.
5944  */
5945 static int bnx2x_get_leader_lock_resource(struct bnx2x_softc *sc)
5946 {
5947         if (SC_PATH(sc)) {
5948                 return HW_LOCK_RESOURCE_RECOVERY_LEADER_1;
5949         } else {
5950                 return HW_LOCK_RESOURCE_RECOVERY_LEADER_0;
5951         }
5952 }
5953
5954 /* try to acquire a leader lock for current engine */
5955 static uint8_t bnx2x_trylock_leader_lock(struct bnx2x_softc *sc)
5956 {
5957         return bnx2x_trylock_hw_lock(sc, bnx2x_get_leader_lock_resource(sc));
5958 }
5959
5960 static int bnx2x_release_leader_lock(struct bnx2x_softc *sc)
5961 {
5962         return bnx2x_release_hw_lock(sc, bnx2x_get_leader_lock_resource(sc));
5963 }
5964
5965 /* close gates #2, #3 and #4 */
5966 static void bnx2x_set_234_gates(struct bnx2x_softc *sc, uint8_t close)
5967 {
5968         uint32_t val;
5969
5970         /* gates #2 and #4a are closed/opened */
5971         /* #4 */
5972         REG_WR(sc, PXP_REG_HST_DISCARD_DOORBELLS, ! !close);
5973         /* #2 */
5974         REG_WR(sc, PXP_REG_HST_DISCARD_INTERNAL_WRITES, ! !close);
5975
5976         /* #3 */
5977         if (CHIP_IS_E1x(sc)) {
5978 /* prevent interrupts from HC on both ports */
5979                 val = REG_RD(sc, HC_REG_CONFIG_1);
5980                 if (close)
5981                         REG_WR(sc, HC_REG_CONFIG_1, (val & ~(uint32_t)
5982                                                      HC_CONFIG_1_REG_BLOCK_DISABLE_1));
5983                 else
5984                         REG_WR(sc, HC_REG_CONFIG_1,
5985                                (val | HC_CONFIG_1_REG_BLOCK_DISABLE_1));
5986
5987                 val = REG_RD(sc, HC_REG_CONFIG_0);
5988                 if (close)
5989                         REG_WR(sc, HC_REG_CONFIG_0, (val & ~(uint32_t)
5990                                                      HC_CONFIG_0_REG_BLOCK_DISABLE_0));
5991                 else
5992                         REG_WR(sc, HC_REG_CONFIG_0,
5993                                (val | HC_CONFIG_0_REG_BLOCK_DISABLE_0));
5994
5995         } else {
5996 /* Prevent incoming interrupts in IGU */
5997                 val = REG_RD(sc, IGU_REG_BLOCK_CONFIGURATION);
5998
5999                 if (close)
6000                         REG_WR(sc, IGU_REG_BLOCK_CONFIGURATION,
6001                                (val & ~(uint32_t)
6002                                 IGU_BLOCK_CONFIGURATION_REG_BLOCK_ENABLE));
6003                 else
6004                         REG_WR(sc, IGU_REG_BLOCK_CONFIGURATION,
6005                                (val |
6006                                 IGU_BLOCK_CONFIGURATION_REG_BLOCK_ENABLE));
6007         }
6008
6009         wmb();
6010 }
6011
6012 /* poll for pending writes bit, it should get cleared in no more than 1s */
6013 static int bnx2x_er_poll_igu_vq(struct bnx2x_softc *sc)
6014 {
6015         uint32_t cnt = 1000;
6016         uint32_t pend_bits = 0;
6017
6018         do {
6019                 pend_bits = REG_RD(sc, IGU_REG_PENDING_BITS_STATUS);
6020
6021                 if (pend_bits == 0) {
6022                         break;
6023                 }
6024
6025                 DELAY(1000);
6026         } while (cnt-- > 0);
6027
6028         if (cnt <= 0) {
6029                 PMD_DRV_LOG(NOTICE, sc, "Still pending IGU requests bits=0x%08x!",
6030                             pend_bits);
6031                 return -1;
6032         }
6033
6034         return 0;
6035 }
6036
6037 #define SHARED_MF_CLP_MAGIC  0x80000000 /* 'magic' bit */
6038
6039 static void bnx2x_clp_reset_prep(struct bnx2x_softc *sc, uint32_t * magic_val)
6040 {
6041         /* Do some magic... */
6042         uint32_t val = MFCFG_RD(sc, shared_mf_config.clp_mb);
6043         *magic_val = val & SHARED_MF_CLP_MAGIC;
6044         MFCFG_WR(sc, shared_mf_config.clp_mb, val | SHARED_MF_CLP_MAGIC);
6045 }
6046
6047 /* restore the value of the 'magic' bit */
6048 static void bnx2x_clp_reset_done(struct bnx2x_softc *sc, uint32_t magic_val)
6049 {
6050         /* Restore the 'magic' bit value... */
6051         uint32_t val = MFCFG_RD(sc, shared_mf_config.clp_mb);
6052         MFCFG_WR(sc, shared_mf_config.clp_mb,
6053                  (val & (~SHARED_MF_CLP_MAGIC)) | magic_val);
6054 }
6055
6056 /* prepare for MCP reset, takes care of CLP configurations */
6057 static void bnx2x_reset_mcp_prep(struct bnx2x_softc *sc, uint32_t * magic_val)
6058 {
6059         uint32_t shmem;
6060         uint32_t validity_offset;
6061
6062         /* set `magic' bit in order to save MF config */
6063         bnx2x_clp_reset_prep(sc, magic_val);
6064
6065         /* get shmem offset */
6066         shmem = REG_RD(sc, MISC_REG_SHARED_MEM_ADDR);
6067         validity_offset =
6068             offsetof(struct shmem_region, validity_map[SC_PORT(sc)]);
6069
6070         /* Clear validity map flags */
6071         if (shmem > 0) {
6072                 REG_WR(sc, shmem + validity_offset, 0);
6073         }
6074 }
6075
6076 #define MCP_TIMEOUT      5000   /* 5 seconds (in ms) */
6077 #define MCP_ONE_TIMEOUT  100    /* 100 ms */
6078
6079 static void bnx2x_mcp_wait_one(struct bnx2x_softc *sc)
6080 {
6081         /* special handling for emulation and FPGA (10 times longer) */
6082         if (CHIP_REV_IS_SLOW(sc)) {
6083                 DELAY((MCP_ONE_TIMEOUT * 10) * 1000);
6084         } else {
6085                 DELAY((MCP_ONE_TIMEOUT) * 1000);
6086         }
6087 }
6088
6089 /* initialize shmem_base and waits for validity signature to appear */
6090 static int bnx2x_init_shmem(struct bnx2x_softc *sc)
6091 {
6092         int cnt = 0;
6093         uint32_t val = 0;
6094
6095         do {
6096                 sc->devinfo.shmem_base =
6097                     sc->link_params.shmem_base =
6098                     REG_RD(sc, MISC_REG_SHARED_MEM_ADDR);
6099
6100                 if (sc->devinfo.shmem_base) {
6101                         val = SHMEM_RD(sc, validity_map[SC_PORT(sc)]);
6102                         if (val & SHR_MEM_VALIDITY_MB)
6103                                 return 0;
6104                 }
6105
6106                 bnx2x_mcp_wait_one(sc);
6107
6108         } while (cnt++ < (MCP_TIMEOUT / MCP_ONE_TIMEOUT));
6109
6110         PMD_DRV_LOG(NOTICE, sc, "BAD MCP validity signature");
6111
6112         return -1;
6113 }
6114
6115 static int bnx2x_reset_mcp_comp(struct bnx2x_softc *sc, uint32_t magic_val)
6116 {
6117         int rc = bnx2x_init_shmem(sc);
6118
6119         /* Restore the `magic' bit value */
6120         bnx2x_clp_reset_done(sc, magic_val);
6121
6122         return rc;
6123 }
6124
6125 static void bnx2x_pxp_prep(struct bnx2x_softc *sc)
6126 {
6127         REG_WR(sc, PXP2_REG_RD_START_INIT, 0);
6128         REG_WR(sc, PXP2_REG_RQ_RBC_DONE, 0);
6129         wmb();
6130 }
6131
6132 /*
6133  * Reset the whole chip except for:
6134  *      - PCIE core
6135  *      - PCI Glue, PSWHST, PXP/PXP2 RF (all controlled by one reset bit)
6136  *      - IGU
6137  *      - MISC (including AEU)
6138  *      - GRC
6139  *      - RBCN, RBCP
6140  */
6141 static void bnx2x_process_kill_chip_reset(struct bnx2x_softc *sc, uint8_t global)
6142 {
6143         uint32_t not_reset_mask1, reset_mask1, not_reset_mask2, reset_mask2;
6144         uint32_t global_bits2, stay_reset2;
6145
6146         /*
6147          * Bits that have to be set in reset_mask2 if we want to reset 'global'
6148          * (per chip) blocks.
6149          */
6150         global_bits2 =
6151             MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_CMN_CPU |
6152             MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_CMN_CORE;
6153
6154         /*
6155          * Don't reset the following blocks.
6156          * Important: per port blocks (such as EMAC, BMAC, UMAC) can't be
6157          *            reset, as in 4 port device they might still be owned
6158          *            by the MCP (there is only one leader per path).
6159          */
6160         not_reset_mask1 =
6161             MISC_REGISTERS_RESET_REG_1_RST_HC |
6162             MISC_REGISTERS_RESET_REG_1_RST_PXPV |
6163             MISC_REGISTERS_RESET_REG_1_RST_PXP;
6164
6165         not_reset_mask2 =
6166             MISC_REGISTERS_RESET_REG_2_RST_PCI_MDIO |
6167             MISC_REGISTERS_RESET_REG_2_RST_EMAC0_HARD_CORE |
6168             MISC_REGISTERS_RESET_REG_2_RST_EMAC1_HARD_CORE |
6169             MISC_REGISTERS_RESET_REG_2_RST_MISC_CORE |
6170             MISC_REGISTERS_RESET_REG_2_RST_RBCN |
6171             MISC_REGISTERS_RESET_REG_2_RST_GRC |
6172             MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_REG_HARD_CORE |
6173             MISC_REGISTERS_RESET_REG_2_RST_MCP_N_HARD_CORE_RST_B |
6174             MISC_REGISTERS_RESET_REG_2_RST_ATC |
6175             MISC_REGISTERS_RESET_REG_2_PGLC |
6176             MISC_REGISTERS_RESET_REG_2_RST_BMAC0 |
6177             MISC_REGISTERS_RESET_REG_2_RST_BMAC1 |
6178             MISC_REGISTERS_RESET_REG_2_RST_EMAC0 |
6179             MISC_REGISTERS_RESET_REG_2_RST_EMAC1 |
6180             MISC_REGISTERS_RESET_REG_2_UMAC0 | MISC_REGISTERS_RESET_REG_2_UMAC1;
6181
6182         /*
6183          * Keep the following blocks in reset:
6184          *  - all xxMACs are handled by the elink code.
6185          */
6186         stay_reset2 =
6187             MISC_REGISTERS_RESET_REG_2_XMAC |
6188             MISC_REGISTERS_RESET_REG_2_XMAC_SOFT;
6189
6190         /* Full reset masks according to the chip */
6191         reset_mask1 = 0xffffffff;
6192
6193         if (CHIP_IS_E1H(sc))
6194                 reset_mask2 = 0x1ffff;
6195         else if (CHIP_IS_E2(sc))
6196                 reset_mask2 = 0xfffff;
6197         else                    /* CHIP_IS_E3 */
6198                 reset_mask2 = 0x3ffffff;
6199
6200         /* Don't reset global blocks unless we need to */
6201         if (!global)
6202                 reset_mask2 &= ~global_bits2;
6203
6204         /*
6205          * In case of attention in the QM, we need to reset PXP
6206          * (MISC_REGISTERS_RESET_REG_2_RST_PXP_RQ_RD_WR) before QM
6207          * because otherwise QM reset would release 'close the gates' shortly
6208          * before resetting the PXP, then the PSWRQ would send a write
6209          * request to PGLUE. Then when PXP is reset, PGLUE would try to
6210          * read the payload data from PSWWR, but PSWWR would not
6211          * respond. The write queue in PGLUE would stuck, dmae commands
6212          * would not return. Therefore it's important to reset the second
6213          * reset register (containing the
6214          * MISC_REGISTERS_RESET_REG_2_RST_PXP_RQ_RD_WR bit) before the
6215          * first one (containing the MISC_REGISTERS_RESET_REG_1_RST_QM
6216          * bit).
6217          */
6218         REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
6219                reset_mask2 & (~not_reset_mask2));
6220
6221         REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR,
6222                reset_mask1 & (~not_reset_mask1));
6223
6224         mb();
6225         wmb();
6226
6227         REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET,
6228                reset_mask2 & (~stay_reset2));
6229
6230         mb();
6231         wmb();
6232
6233         REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, reset_mask1);
6234         wmb();
6235 }
6236
6237 static int bnx2x_process_kill(struct bnx2x_softc *sc, uint8_t global)
6238 {
6239         int cnt = 1000;
6240         uint32_t val = 0;
6241         uint32_t sr_cnt, blk_cnt, port_is_idle_0, port_is_idle_1, pgl_exp_rom2;
6242         uint32_t tags_63_32 = 0;
6243
6244         /* Empty the Tetris buffer, wait for 1s */
6245         do {
6246                 sr_cnt = REG_RD(sc, PXP2_REG_RD_SR_CNT);
6247                 blk_cnt = REG_RD(sc, PXP2_REG_RD_BLK_CNT);
6248                 port_is_idle_0 = REG_RD(sc, PXP2_REG_RD_PORT_IS_IDLE_0);
6249                 port_is_idle_1 = REG_RD(sc, PXP2_REG_RD_PORT_IS_IDLE_1);
6250                 pgl_exp_rom2 = REG_RD(sc, PXP2_REG_PGL_EXP_ROM2);
6251                 if (CHIP_IS_E3(sc)) {
6252                         tags_63_32 = REG_RD(sc, PGLUE_B_REG_TAGS_63_32);
6253                 }
6254
6255                 if ((sr_cnt == 0x7e) && (blk_cnt == 0xa0) &&
6256                     ((port_is_idle_0 & 0x1) == 0x1) &&
6257                     ((port_is_idle_1 & 0x1) == 0x1) &&
6258                     (pgl_exp_rom2 == 0xffffffff) &&
6259                     (!CHIP_IS_E3(sc) || (tags_63_32 == 0xffffffff)))
6260                         break;
6261                 DELAY(1000);
6262         } while (cnt-- > 0);
6263
6264         if (cnt <= 0) {
6265                 PMD_DRV_LOG(NOTICE, sc,
6266                             "ERROR: Tetris buffer didn't get empty or there "
6267                             "are still outstanding read requests after 1s! "
6268                             "sr_cnt=0x%08x, blk_cnt=0x%08x, port_is_idle_0=0x%08x, "
6269                             "port_is_idle_1=0x%08x, pgl_exp_rom2=0x%08x",
6270                             sr_cnt, blk_cnt, port_is_idle_0, port_is_idle_1,
6271                             pgl_exp_rom2);
6272                 return -1;
6273         }
6274
6275         mb();
6276
6277         /* Close gates #2, #3 and #4 */
6278         bnx2x_set_234_gates(sc, TRUE);
6279
6280         /* Poll for IGU VQs for 57712 and newer chips */
6281         if (!CHIP_IS_E1x(sc) && bnx2x_er_poll_igu_vq(sc)) {
6282                 return -1;
6283         }
6284
6285         /* clear "unprepared" bit */
6286         REG_WR(sc, MISC_REG_UNPREPARED, 0);
6287         mb();
6288
6289         /* Make sure all is written to the chip before the reset */
6290         wmb();
6291
6292         /*
6293          * Wait for 1ms to empty GLUE and PCI-E core queues,
6294          * PSWHST, GRC and PSWRD Tetris buffer.
6295          */
6296         DELAY(1000);
6297
6298         /* Prepare to chip reset: */
6299         /* MCP */
6300         if (global) {
6301                 bnx2x_reset_mcp_prep(sc, &val);
6302         }
6303
6304         /* PXP */
6305         bnx2x_pxp_prep(sc);
6306         mb();
6307
6308         /* reset the chip */
6309         bnx2x_process_kill_chip_reset(sc, global);
6310         mb();
6311
6312         /* Recover after reset: */
6313         /* MCP */
6314         if (global && bnx2x_reset_mcp_comp(sc, val)) {
6315                 return -1;
6316         }
6317
6318         /* Open the gates #2, #3 and #4 */
6319         bnx2x_set_234_gates(sc, FALSE);
6320
6321         return 0;
6322 }
6323
6324 static int bnx2x_leader_reset(struct bnx2x_softc *sc)
6325 {
6326         int rc = 0;
6327         uint8_t global = bnx2x_reset_is_global(sc);
6328         uint32_t load_code;
6329
6330         /*
6331          * If not going to reset MCP, load "fake" driver to reset HW while
6332          * driver is owner of the HW.
6333          */
6334         if (!global && !BNX2X_NOMCP(sc)) {
6335                 load_code = bnx2x_fw_command(sc, DRV_MSG_CODE_LOAD_REQ,
6336                                            DRV_MSG_CODE_LOAD_REQ_WITH_LFA);
6337                 if (!load_code) {
6338                         PMD_DRV_LOG(NOTICE, sc, "MCP response failure, aborting");
6339                         rc = -1;
6340                         goto exit_leader_reset;
6341                 }
6342
6343                 if ((load_code != FW_MSG_CODE_DRV_LOAD_COMMON_CHIP) &&
6344                     (load_code != FW_MSG_CODE_DRV_LOAD_COMMON)) {
6345                         PMD_DRV_LOG(NOTICE, sc,
6346                                     "MCP unexpected response, aborting");
6347                         rc = -1;
6348                         goto exit_leader_reset2;
6349                 }
6350
6351                 load_code = bnx2x_fw_command(sc, DRV_MSG_CODE_LOAD_DONE, 0);
6352                 if (!load_code) {
6353                         PMD_DRV_LOG(NOTICE, sc, "MCP response failure, aborting");
6354                         rc = -1;
6355                         goto exit_leader_reset2;
6356                 }
6357         }
6358
6359         /* try to recover after the failure */
6360         if (bnx2x_process_kill(sc, global)) {
6361                 PMD_DRV_LOG(NOTICE, sc, "Something bad occurred on engine %d!",
6362                             SC_PATH(sc));
6363                 rc = -1;
6364                 goto exit_leader_reset2;
6365         }
6366
6367         /*
6368          * Clear the RESET_IN_PROGRESS and RESET_GLOBAL bits and update the driver
6369          * state.
6370          */
6371         bnx2x_set_reset_done(sc);
6372         if (global) {
6373                 bnx2x_clear_reset_global(sc);
6374         }
6375
6376 exit_leader_reset2:
6377
6378         /* unload "fake driver" if it was loaded */
6379         if (!global &&!BNX2X_NOMCP(sc)) {
6380                 bnx2x_fw_command(sc, DRV_MSG_CODE_UNLOAD_REQ_WOL_MCP, 0);
6381                 bnx2x_fw_command(sc, DRV_MSG_CODE_UNLOAD_DONE, 0);
6382         }
6383
6384 exit_leader_reset:
6385
6386         sc->is_leader = 0;
6387         bnx2x_release_leader_lock(sc);
6388
6389         mb();
6390         return rc;
6391 }
6392
6393 /*
6394  * prepare INIT transition, parameters configured:
6395  *   - HC configuration
6396  *   - Queue's CDU context
6397  */
6398 static void
6399 bnx2x_pf_q_prep_init(struct bnx2x_softc *sc, struct bnx2x_fastpath *fp,
6400                    struct ecore_queue_init_params *init_params)
6401 {
6402         uint8_t cos;
6403         int cxt_index, cxt_offset;
6404
6405         bnx2x_set_bit(ECORE_Q_FLG_HC, &init_params->rx.flags);
6406         bnx2x_set_bit(ECORE_Q_FLG_HC, &init_params->tx.flags);
6407
6408         bnx2x_set_bit(ECORE_Q_FLG_HC_EN, &init_params->rx.flags);
6409         bnx2x_set_bit(ECORE_Q_FLG_HC_EN, &init_params->tx.flags);
6410
6411         /* HC rate */
6412         init_params->rx.hc_rate =
6413             sc->hc_rx_ticks ? (1000000 / sc->hc_rx_ticks) : 0;
6414         init_params->tx.hc_rate =
6415             sc->hc_tx_ticks ? (1000000 / sc->hc_tx_ticks) : 0;
6416
6417         /* FW SB ID */
6418         init_params->rx.fw_sb_id = init_params->tx.fw_sb_id = fp->fw_sb_id;
6419
6420         /* CQ index among the SB indices */
6421         init_params->rx.sb_cq_index = HC_INDEX_ETH_RX_CQ_CONS;
6422         init_params->tx.sb_cq_index = HC_INDEX_ETH_FIRST_TX_CQ_CONS;
6423
6424         /* set maximum number of COSs supported by this queue */
6425         init_params->max_cos = sc->max_cos;
6426
6427         /* set the context pointers queue object */
6428         for (cos = FIRST_TX_COS_INDEX; cos < init_params->max_cos; cos++) {
6429                 cxt_index = fp->index / ILT_PAGE_CIDS;
6430                 cxt_offset = fp->index - (cxt_index * ILT_PAGE_CIDS);
6431                 init_params->cxts[cos] =
6432                     &sc->context[cxt_index].vcxt[cxt_offset].eth;
6433         }
6434 }
6435
6436 /* set flags that are common for the Tx-only and not normal connections */
6437 static unsigned long
6438 bnx2x_get_common_flags(struct bnx2x_softc *sc, uint8_t zero_stats)
6439 {
6440         unsigned long flags = 0;
6441
6442         /* PF driver will always initialize the Queue to an ACTIVE state */
6443         bnx2x_set_bit(ECORE_Q_FLG_ACTIVE, &flags);
6444
6445         /*
6446          * tx only connections collect statistics (on the same index as the
6447          * parent connection). The statistics are zeroed when the parent
6448          * connection is initialized.
6449          */
6450
6451         bnx2x_set_bit(ECORE_Q_FLG_STATS, &flags);
6452         if (zero_stats) {
6453                 bnx2x_set_bit(ECORE_Q_FLG_ZERO_STATS, &flags);
6454         }
6455
6456         /*
6457          * tx only connections can support tx-switching, though their
6458          * CoS-ness doesn't survive the loopback
6459          */
6460         if (sc->flags & BNX2X_TX_SWITCHING) {
6461                 bnx2x_set_bit(ECORE_Q_FLG_TX_SWITCH, &flags);
6462         }
6463
6464         bnx2x_set_bit(ECORE_Q_FLG_PCSUM_ON_PKT, &flags);
6465
6466         return flags;
6467 }
6468
6469 static unsigned long bnx2x_get_q_flags(struct bnx2x_softc *sc, uint8_t leading)
6470 {
6471         unsigned long flags = 0;
6472
6473         if (IS_MF_SD(sc)) {
6474                 bnx2x_set_bit(ECORE_Q_FLG_OV, &flags);
6475         }
6476
6477         if (leading) {
6478                 bnx2x_set_bit(ECORE_Q_FLG_LEADING_RSS, &flags);
6479                 bnx2x_set_bit(ECORE_Q_FLG_MCAST, &flags);
6480         }
6481
6482         bnx2x_set_bit(ECORE_Q_FLG_VLAN, &flags);
6483
6484         /* merge with common flags */
6485         return flags | bnx2x_get_common_flags(sc, TRUE);
6486 }
6487
6488 static void
6489 bnx2x_pf_q_prep_general(struct bnx2x_softc *sc, struct bnx2x_fastpath *fp,
6490                       struct ecore_general_setup_params *gen_init, uint8_t cos)
6491 {
6492         gen_init->stat_id = bnx2x_stats_id(fp);
6493         gen_init->spcl_id = fp->cl_id;
6494         gen_init->mtu = sc->mtu;
6495         gen_init->cos = cos;
6496 }
6497
6498 static void
6499 bnx2x_pf_rx_q_prep(struct bnx2x_softc *sc, struct bnx2x_fastpath *fp,
6500                  struct rxq_pause_params *pause,
6501                  struct ecore_rxq_setup_params *rxq_init)
6502 {
6503         struct bnx2x_rx_queue *rxq;
6504
6505         rxq = sc->rx_queues[fp->index];
6506         if (!rxq) {
6507                 PMD_RX_LOG(ERR, "RX queue is NULL");
6508                 return;
6509         }
6510         /* pause */
6511         pause->bd_th_lo = BD_TH_LO(sc);
6512         pause->bd_th_hi = BD_TH_HI(sc);
6513
6514         pause->rcq_th_lo = RCQ_TH_LO(sc);
6515         pause->rcq_th_hi = RCQ_TH_HI(sc);
6516
6517         /* validate rings have enough entries to cross high thresholds */
6518         if (sc->dropless_fc &&
6519             pause->bd_th_hi + FW_PREFETCH_CNT > sc->rx_ring_size) {
6520                 PMD_DRV_LOG(WARNING, sc, "rx bd ring threshold limit");
6521         }
6522
6523         if (sc->dropless_fc &&
6524             pause->rcq_th_hi + FW_PREFETCH_CNT > USABLE_RCQ_ENTRIES(rxq)) {
6525                 PMD_DRV_LOG(WARNING, sc, "rcq ring threshold limit");
6526         }
6527
6528         pause->pri_map = 1;
6529
6530         /* rxq setup */
6531         rxq_init->dscr_map = (rte_iova_t)rxq->rx_ring_phys_addr;
6532         rxq_init->rcq_map = (rte_iova_t)rxq->cq_ring_phys_addr;
6533         rxq_init->rcq_np_map = (rte_iova_t)(rxq->cq_ring_phys_addr +
6534                                               BNX2X_PAGE_SIZE);
6535
6536         /*
6537          * This should be a maximum number of data bytes that may be
6538          * placed on the BD (not including paddings).
6539          */
6540         rxq_init->buf_sz = (fp->rx_buf_size - IP_HEADER_ALIGNMENT_PADDING);
6541
6542         rxq_init->cl_qzone_id = fp->cl_qzone_id;
6543         rxq_init->rss_engine_id = SC_FUNC(sc);
6544         rxq_init->mcast_engine_id = SC_FUNC(sc);
6545
6546         rxq_init->cache_line_log = BNX2X_RX_ALIGN_SHIFT;
6547         rxq_init->fw_sb_id = fp->fw_sb_id;
6548
6549         rxq_init->sb_cq_index = HC_INDEX_ETH_RX_CQ_CONS;
6550
6551         /*
6552          * configure silent vlan removal
6553          * if multi function mode is afex, then mask default vlan
6554          */
6555         if (IS_MF_AFEX(sc)) {
6556                 rxq_init->silent_removal_value =
6557                     sc->devinfo.mf_info.afex_def_vlan_tag;
6558                 rxq_init->silent_removal_mask = EVL_VLID_MASK;
6559         }
6560 }
6561
6562 static void
6563 bnx2x_pf_tx_q_prep(struct bnx2x_softc *sc, struct bnx2x_fastpath *fp,
6564                  struct ecore_txq_setup_params *txq_init, uint8_t cos)
6565 {
6566         struct bnx2x_tx_queue *txq = fp->sc->tx_queues[fp->index];
6567
6568         if (!txq) {
6569                 PMD_TX_LOG(ERR, "ERROR: TX queue is NULL");
6570                 return;
6571         }
6572         txq_init->dscr_map = (rte_iova_t)txq->tx_ring_phys_addr;
6573         txq_init->sb_cq_index = HC_INDEX_ETH_FIRST_TX_CQ_CONS + cos;
6574         txq_init->traffic_type = LLFC_TRAFFIC_TYPE_NW;
6575         txq_init->fw_sb_id = fp->fw_sb_id;
6576
6577         /*
6578          * set the TSS leading client id for TX classfication to the
6579          * leading RSS client id
6580          */
6581         txq_init->tss_leading_cl_id = BNX2X_FP(sc, 0, cl_id);
6582 }
6583
6584 /*
6585  * This function performs 2 steps in a queue state machine:
6586  *   1) RESET->INIT
6587  *   2) INIT->SETUP
6588  */
6589 static int
6590 bnx2x_setup_queue(struct bnx2x_softc *sc, struct bnx2x_fastpath *fp, uint8_t leading)
6591 {
6592         struct ecore_queue_state_params q_params = { NULL };
6593         struct ecore_queue_setup_params *setup_params = &q_params.params.setup;
6594         int rc;
6595
6596         PMD_DRV_LOG(DEBUG, sc, "setting up queue %d", fp->index);
6597
6598         bnx2x_ack_sb(sc, fp->igu_sb_id, USTORM_ID, 0, IGU_INT_ENABLE, 0);
6599
6600         q_params.q_obj = &BNX2X_SP_OBJ(sc, fp).q_obj;
6601
6602         /* we want to wait for completion in this context */
6603         bnx2x_set_bit(RAMROD_COMP_WAIT, &q_params.ramrod_flags);
6604
6605         /* prepare the INIT parameters */
6606         bnx2x_pf_q_prep_init(sc, fp, &q_params.params.init);
6607
6608         /* Set the command */
6609         q_params.cmd = ECORE_Q_CMD_INIT;
6610
6611         /* Change the state to INIT */
6612         rc = ecore_queue_state_change(sc, &q_params);
6613         if (rc) {
6614                 PMD_DRV_LOG(NOTICE, sc, "Queue(%d) INIT failed", fp->index);
6615                 return rc;
6616         }
6617
6618         PMD_DRV_LOG(DEBUG, sc, "init complete");
6619
6620         /* now move the Queue to the SETUP state */
6621         memset(setup_params, 0, sizeof(*setup_params));
6622
6623         /* set Queue flags */
6624         setup_params->flags = bnx2x_get_q_flags(sc, leading);
6625
6626         /* set general SETUP parameters */
6627         bnx2x_pf_q_prep_general(sc, fp, &setup_params->gen_params,
6628                               FIRST_TX_COS_INDEX);
6629
6630         bnx2x_pf_rx_q_prep(sc, fp,
6631                          &setup_params->pause_params,
6632                          &setup_params->rxq_params);
6633
6634         bnx2x_pf_tx_q_prep(sc, fp, &setup_params->txq_params, FIRST_TX_COS_INDEX);
6635
6636         /* Set the command */
6637         q_params.cmd = ECORE_Q_CMD_SETUP;
6638
6639         /* change the state to SETUP */
6640         rc = ecore_queue_state_change(sc, &q_params);
6641         if (rc) {
6642                 PMD_DRV_LOG(NOTICE, sc, "Queue(%d) SETUP failed", fp->index);
6643                 return rc;
6644         }
6645
6646         return rc;
6647 }
6648
6649 static int bnx2x_setup_leading(struct bnx2x_softc *sc)
6650 {
6651         if (IS_PF(sc))
6652                 return bnx2x_setup_queue(sc, &sc->fp[0], TRUE);
6653         else                    /* VF */
6654                 return bnx2x_vf_setup_queue(sc, &sc->fp[0], TRUE);
6655 }
6656
6657 static int
6658 bnx2x_config_rss_pf(struct bnx2x_softc *sc, struct ecore_rss_config_obj *rss_obj,
6659                   uint8_t config_hash)
6660 {
6661         struct ecore_config_rss_params params = { NULL };
6662         uint32_t i;
6663
6664         /*
6665          * Although RSS is meaningless when there is a single HW queue we
6666          * still need it enabled in order to have HW Rx hash generated.
6667          */
6668
6669         params.rss_obj = rss_obj;
6670
6671         bnx2x_set_bit(RAMROD_COMP_WAIT, &params.ramrod_flags);
6672
6673         bnx2x_set_bit(ECORE_RSS_MODE_REGULAR, &params.rss_flags);
6674
6675         /* RSS configuration */
6676         bnx2x_set_bit(ECORE_RSS_IPV4, &params.rss_flags);
6677         bnx2x_set_bit(ECORE_RSS_IPV4_TCP, &params.rss_flags);
6678         bnx2x_set_bit(ECORE_RSS_IPV6, &params.rss_flags);
6679         bnx2x_set_bit(ECORE_RSS_IPV6_TCP, &params.rss_flags);
6680         if (rss_obj->udp_rss_v4) {
6681                 bnx2x_set_bit(ECORE_RSS_IPV4_UDP, &params.rss_flags);
6682         }
6683         if (rss_obj->udp_rss_v6) {
6684                 bnx2x_set_bit(ECORE_RSS_IPV6_UDP, &params.rss_flags);
6685         }
6686
6687         /* Hash bits */
6688         params.rss_result_mask = MULTI_MASK;
6689
6690         rte_memcpy(params.ind_table, rss_obj->ind_table,
6691                          sizeof(params.ind_table));
6692
6693         if (config_hash) {
6694 /* RSS keys */
6695                 for (i = 0; i < sizeof(params.rss_key) / 4; i++) {
6696                         params.rss_key[i] = (uint32_t) rte_rand();
6697                 }
6698
6699                 bnx2x_set_bit(ECORE_RSS_SET_SRCH, &params.rss_flags);
6700         }
6701
6702         if (IS_PF(sc))
6703                 return ecore_config_rss(sc, &params);
6704         else
6705                 return bnx2x_vf_config_rss(sc, &params);
6706 }
6707
6708 static int bnx2x_config_rss_eth(struct bnx2x_softc *sc, uint8_t config_hash)
6709 {
6710         return bnx2x_config_rss_pf(sc, &sc->rss_conf_obj, config_hash);
6711 }
6712
6713 static int bnx2x_init_rss_pf(struct bnx2x_softc *sc)
6714 {
6715         uint8_t num_eth_queues = BNX2X_NUM_ETH_QUEUES(sc);
6716         uint32_t i;
6717
6718         /*
6719          * Prepare the initial contents of the indirection table if
6720          * RSS is enabled
6721          */
6722         for (i = 0; i < sizeof(sc->rss_conf_obj.ind_table); i++) {
6723                 sc->rss_conf_obj.ind_table[i] =
6724                     (sc->fp->cl_id + (i % num_eth_queues));
6725         }
6726
6727         if (sc->udp_rss) {
6728                 sc->rss_conf_obj.udp_rss_v4 = sc->rss_conf_obj.udp_rss_v6 = 1;
6729         }
6730
6731         /*
6732          * For 57711 SEARCHER configuration (rss_keys) is
6733          * per-port, so if explicit configuration is needed, do it only
6734          * for a PMF.
6735          *
6736          * For 57712 and newer it's a per-function configuration.
6737          */
6738         return bnx2x_config_rss_eth(sc, sc->port.pmf || !CHIP_IS_E1x(sc));
6739 }
6740
6741 static int
6742 bnx2x_set_mac_one(struct bnx2x_softc *sc, uint8_t * mac,
6743                 struct ecore_vlan_mac_obj *obj, uint8_t set, int mac_type,
6744                 unsigned long *ramrod_flags)
6745 {
6746         struct ecore_vlan_mac_ramrod_params ramrod_param;
6747         int rc;
6748
6749         memset(&ramrod_param, 0, sizeof(ramrod_param));
6750
6751         /* fill in general parameters */
6752         ramrod_param.vlan_mac_obj = obj;
6753         ramrod_param.ramrod_flags = *ramrod_flags;
6754
6755         /* fill a user request section if needed */
6756         if (!bnx2x_test_bit(RAMROD_CONT, ramrod_flags)) {
6757                 rte_memcpy(ramrod_param.user_req.u.mac.mac, mac,
6758                                  ETH_ALEN);
6759
6760                 bnx2x_set_bit(mac_type, &ramrod_param.user_req.vlan_mac_flags);
6761
6762 /* Set the command: ADD or DEL */
6763                 ramrod_param.user_req.cmd = (set) ? ECORE_VLAN_MAC_ADD :
6764                     ECORE_VLAN_MAC_DEL;
6765         }
6766
6767         rc = ecore_config_vlan_mac(sc, &ramrod_param);
6768
6769         if (rc == ECORE_EXISTS) {
6770                 PMD_DRV_LOG(INFO, sc, "Failed to schedule ADD operations (EEXIST)");
6771 /* do not treat adding same MAC as error */
6772                 rc = 0;
6773         } else if (rc < 0) {
6774                 PMD_DRV_LOG(ERR, sc,
6775                             "%s MAC failed (%d)", (set ? "Set" : "Delete"), rc);
6776         }
6777
6778         return rc;
6779 }
6780
6781 static int bnx2x_set_eth_mac(struct bnx2x_softc *sc, uint8_t set)
6782 {
6783         unsigned long ramrod_flags = 0;
6784
6785         PMD_DRV_LOG(DEBUG, sc, "Adding Ethernet MAC");
6786
6787         bnx2x_set_bit(RAMROD_COMP_WAIT, &ramrod_flags);
6788
6789         /* Eth MAC is set on RSS leading client (fp[0]) */
6790         return bnx2x_set_mac_one(sc, sc->link_params.mac_addr,
6791                                &sc->sp_objs->mac_obj,
6792                                set, ECORE_ETH_MAC, &ramrod_flags);
6793 }
6794
6795 static int bnx2x_get_cur_phy_idx(struct bnx2x_softc *sc)
6796 {
6797         uint32_t sel_phy_idx = 0;
6798
6799         if (sc->link_params.num_phys <= 1) {
6800                 return ELINK_INT_PHY;
6801         }
6802
6803         if (sc->link_vars.link_up) {
6804                 sel_phy_idx = ELINK_EXT_PHY1;
6805 /* In case link is SERDES, check if the ELINK_EXT_PHY2 is the one */
6806                 if ((sc->link_vars.link_status & LINK_STATUS_SERDES_LINK) &&
6807                     (sc->link_params.phy[ELINK_EXT_PHY2].supported &
6808                      ELINK_SUPPORTED_FIBRE))
6809                         sel_phy_idx = ELINK_EXT_PHY2;
6810         } else {
6811                 switch (elink_phy_selection(&sc->link_params)) {
6812                 case PORT_HW_CFG_PHY_SELECTION_HARDWARE_DEFAULT:
6813                 case PORT_HW_CFG_PHY_SELECTION_FIRST_PHY:
6814                 case PORT_HW_CFG_PHY_SELECTION_FIRST_PHY_PRIORITY:
6815                         sel_phy_idx = ELINK_EXT_PHY1;
6816                         break;
6817                 case PORT_HW_CFG_PHY_SELECTION_SECOND_PHY:
6818                 case PORT_HW_CFG_PHY_SELECTION_SECOND_PHY_PRIORITY:
6819                         sel_phy_idx = ELINK_EXT_PHY2;
6820                         break;
6821                 }
6822         }
6823
6824         return sel_phy_idx;
6825 }
6826
6827 static int bnx2x_get_link_cfg_idx(struct bnx2x_softc *sc)
6828 {
6829         uint32_t sel_phy_idx = bnx2x_get_cur_phy_idx(sc);
6830
6831         /*
6832          * The selected activated PHY is always after swapping (in case PHY
6833          * swapping is enabled). So when swapping is enabled, we need to reverse
6834          * the configuration
6835          */
6836
6837         if (sc->link_params.multi_phy_config & PORT_HW_CFG_PHY_SWAPPED_ENABLED) {
6838                 if (sel_phy_idx == ELINK_EXT_PHY1)
6839                         sel_phy_idx = ELINK_EXT_PHY2;
6840                 else if (sel_phy_idx == ELINK_EXT_PHY2)
6841                         sel_phy_idx = ELINK_EXT_PHY1;
6842         }
6843
6844         return ELINK_LINK_CONFIG_IDX(sel_phy_idx);
6845 }
6846
6847 static void bnx2x_set_requested_fc(struct bnx2x_softc *sc)
6848 {
6849         /*
6850          * Initialize link parameters structure variables
6851          * It is recommended to turn off RX FC for jumbo frames
6852          * for better performance
6853          */
6854         if (CHIP_IS_E1x(sc) && (sc->mtu > 5000)) {
6855                 sc->link_params.req_fc_auto_adv = ELINK_FLOW_CTRL_TX;
6856         } else {
6857                 sc->link_params.req_fc_auto_adv = ELINK_FLOW_CTRL_BOTH;
6858         }
6859 }
6860
6861 static void bnx2x_calc_fc_adv(struct bnx2x_softc *sc)
6862 {
6863         uint8_t cfg_idx = bnx2x_get_link_cfg_idx(sc);
6864         switch (sc->link_vars.ieee_fc &
6865                 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_MASK) {
6866         case MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_NONE:
6867         default:
6868                 sc->port.advertising[cfg_idx] &= ~(ADVERTISED_Asym_Pause |
6869                                                    ADVERTISED_Pause);
6870                 break;
6871
6872         case MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH:
6873                 sc->port.advertising[cfg_idx] |= (ADVERTISED_Asym_Pause |
6874                                                   ADVERTISED_Pause);
6875                 break;
6876
6877         case MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC:
6878                 sc->port.advertising[cfg_idx] |= ADVERTISED_Asym_Pause;
6879                 break;
6880         }
6881 }
6882
6883 static uint16_t bnx2x_get_mf_speed(struct bnx2x_softc *sc)
6884 {
6885         uint16_t line_speed = sc->link_vars.line_speed;
6886         if (IS_MF(sc)) {
6887                 uint16_t maxCfg = bnx2x_extract_max_cfg(sc,
6888                                                       sc->devinfo.
6889                                                       mf_info.mf_config[SC_VN
6890                                                                         (sc)]);
6891
6892 /* calculate the current MAX line speed limit for the MF devices */
6893                 if (IS_MF_SI(sc)) {
6894                         line_speed = (line_speed * maxCfg) / 100;
6895                 } else {        /* SD mode */
6896                         uint16_t vn_max_rate = maxCfg * 100;
6897
6898                         if (vn_max_rate < line_speed) {
6899                                 line_speed = vn_max_rate;
6900                         }
6901                 }
6902         }
6903
6904         return line_speed;
6905 }
6906
6907 static void
6908 bnx2x_fill_report_data(struct bnx2x_softc *sc, struct bnx2x_link_report_data *data)
6909 {
6910         uint16_t line_speed = bnx2x_get_mf_speed(sc);
6911
6912         memset(data, 0, sizeof(*data));
6913
6914         /* fill the report data with the effective line speed */
6915         data->line_speed = line_speed;
6916
6917         /* Link is down */
6918         if (!sc->link_vars.link_up || (sc->flags & BNX2X_MF_FUNC_DIS)) {
6919                 bnx2x_set_bit(BNX2X_LINK_REPORT_LINK_DOWN,
6920                             &data->link_report_flags);
6921         }
6922
6923         /* Full DUPLEX */
6924         if (sc->link_vars.duplex == DUPLEX_FULL) {
6925                 bnx2x_set_bit(BNX2X_LINK_REPORT_FULL_DUPLEX,
6926                             &data->link_report_flags);
6927         }
6928
6929         /* Rx Flow Control is ON */
6930         if (sc->link_vars.flow_ctrl & ELINK_FLOW_CTRL_RX) {
6931                 bnx2x_set_bit(BNX2X_LINK_REPORT_RX_FC_ON, &data->link_report_flags);
6932         }
6933
6934         /* Tx Flow Control is ON */
6935         if (sc->link_vars.flow_ctrl & ELINK_FLOW_CTRL_TX) {
6936                 bnx2x_set_bit(BNX2X_LINK_REPORT_TX_FC_ON, &data->link_report_flags);
6937         }
6938 }
6939
6940 /* report link status to OS, should be called under phy_lock */
6941 static void bnx2x_link_report_locked(struct bnx2x_softc *sc)
6942 {
6943         struct bnx2x_link_report_data cur_data;
6944
6945         /* reread mf_cfg */
6946         if (IS_PF(sc)) {
6947                 bnx2x_read_mf_cfg(sc);
6948         }
6949
6950         /* Read the current link report info */
6951         bnx2x_fill_report_data(sc, &cur_data);
6952
6953         /* Don't report link down or exactly the same link status twice */
6954         if (!memcmp(&cur_data, &sc->last_reported_link, sizeof(cur_data)) ||
6955             (bnx2x_test_bit(BNX2X_LINK_REPORT_LINK_DOWN,
6956                           &sc->last_reported_link.link_report_flags) &&
6957              bnx2x_test_bit(BNX2X_LINK_REPORT_LINK_DOWN,
6958                           &cur_data.link_report_flags))) {
6959                 return;
6960         }
6961
6962         ELINK_DEBUG_P2(sc, "Change in link status : cur_data = %lx, last_reported_link = %lx",
6963                        cur_data.link_report_flags,
6964                        sc->last_reported_link.link_report_flags);
6965
6966         sc->link_cnt++;
6967
6968         ELINK_DEBUG_P1(sc, "link status change count = %x", sc->link_cnt);
6969         /* report new link params and remember the state for the next time */
6970         rte_memcpy(&sc->last_reported_link, &cur_data, sizeof(cur_data));
6971
6972         if (bnx2x_test_bit(BNX2X_LINK_REPORT_LINK_DOWN,
6973                          &cur_data.link_report_flags)) {
6974                 ELINK_DEBUG_P0(sc, "NIC Link is Down");
6975         } else {
6976                 __rte_unused const char *duplex;
6977                 __rte_unused const char *flow;
6978
6979                 if (bnx2x_test_and_clear_bit(BNX2X_LINK_REPORT_FULL_DUPLEX,
6980                                            &cur_data.link_report_flags)) {
6981                         duplex = "full";
6982                                 ELINK_DEBUG_P0(sc, "link set to full duplex");
6983                 } else {
6984                         duplex = "half";
6985                                 ELINK_DEBUG_P0(sc, "link set to half duplex");
6986                 }
6987
6988 /*
6989  * Handle the FC at the end so that only these flags would be
6990  * possibly set. This way we may easily check if there is no FC
6991  * enabled.
6992  */
6993                 if (cur_data.link_report_flags) {
6994                         if (bnx2x_test_bit(BNX2X_LINK_REPORT_RX_FC_ON,
6995                                          &cur_data.link_report_flags) &&
6996                             bnx2x_test_bit(BNX2X_LINK_REPORT_TX_FC_ON,
6997                                          &cur_data.link_report_flags)) {
6998                                 flow = "ON - receive & transmit";
6999                         } else if (bnx2x_test_bit(BNX2X_LINK_REPORT_RX_FC_ON,
7000                                                 &cur_data.link_report_flags) &&
7001                                    !bnx2x_test_bit(BNX2X_LINK_REPORT_TX_FC_ON,
7002                                                  &cur_data.link_report_flags)) {
7003                                 flow = "ON - receive";
7004                         } else if (!bnx2x_test_bit(BNX2X_LINK_REPORT_RX_FC_ON,
7005                                                  &cur_data.link_report_flags) &&
7006                                    bnx2x_test_bit(BNX2X_LINK_REPORT_TX_FC_ON,
7007                                                 &cur_data.link_report_flags)) {
7008                                 flow = "ON - transmit";
7009                         } else {
7010                                 flow = "none";  /* possible? */
7011                         }
7012                 } else {
7013                         flow = "none";
7014                 }
7015
7016                 PMD_DRV_LOG(INFO, sc,
7017                             "NIC Link is Up, %d Mbps %s duplex, Flow control: %s",
7018                             cur_data.line_speed, duplex, flow);
7019         }
7020 }
7021
7022 static void
7023 bnx2x_link_report(struct bnx2x_softc *sc)
7024 {
7025         bnx2x_acquire_phy_lock(sc);
7026         bnx2x_link_report_locked(sc);
7027         bnx2x_release_phy_lock(sc);
7028 }
7029
7030 void bnx2x_link_status_update(struct bnx2x_softc *sc)
7031 {
7032         if (sc->state != BNX2X_STATE_OPEN) {
7033                 return;
7034         }
7035
7036         if (IS_PF(sc) && !CHIP_REV_IS_SLOW(sc)) {
7037                 elink_link_status_update(&sc->link_params, &sc->link_vars);
7038         } else {
7039                 sc->port.supported[0] |= (ELINK_SUPPORTED_10baseT_Half |
7040                                           ELINK_SUPPORTED_10baseT_Full |
7041                                           ELINK_SUPPORTED_100baseT_Half |
7042                                           ELINK_SUPPORTED_100baseT_Full |
7043                                           ELINK_SUPPORTED_1000baseT_Full |
7044                                           ELINK_SUPPORTED_2500baseX_Full |
7045                                           ELINK_SUPPORTED_10000baseT_Full |
7046                                           ELINK_SUPPORTED_TP |
7047                                           ELINK_SUPPORTED_FIBRE |
7048                                           ELINK_SUPPORTED_Autoneg |
7049                                           ELINK_SUPPORTED_Pause |
7050                                           ELINK_SUPPORTED_Asym_Pause);
7051                 sc->port.advertising[0] = sc->port.supported[0];
7052
7053                 sc->link_params.sc = sc;
7054                 sc->link_params.port = SC_PORT(sc);
7055                 sc->link_params.req_duplex[0] = DUPLEX_FULL;
7056                 sc->link_params.req_flow_ctrl[0] = ELINK_FLOW_CTRL_NONE;
7057                 sc->link_params.req_line_speed[0] = SPEED_10000;
7058                 sc->link_params.speed_cap_mask[0] = 0x7f0000;
7059                 sc->link_params.switch_cfg = ELINK_SWITCH_CFG_10G;
7060
7061                 if (CHIP_REV_IS_FPGA(sc)) {
7062                         sc->link_vars.mac_type = ELINK_MAC_TYPE_EMAC;
7063                         sc->link_vars.line_speed = ELINK_SPEED_1000;
7064                         sc->link_vars.link_status = (LINK_STATUS_LINK_UP |
7065                                                      LINK_STATUS_SPEED_AND_DUPLEX_1000TFD);
7066                 } else {
7067                         sc->link_vars.mac_type = ELINK_MAC_TYPE_BMAC;
7068                         sc->link_vars.line_speed = ELINK_SPEED_10000;
7069                         sc->link_vars.link_status = (LINK_STATUS_LINK_UP |
7070                                                      LINK_STATUS_SPEED_AND_DUPLEX_10GTFD);
7071                 }
7072
7073                 sc->link_vars.link_up = 1;
7074
7075                 sc->link_vars.duplex = DUPLEX_FULL;
7076                 sc->link_vars.flow_ctrl = ELINK_FLOW_CTRL_NONE;
7077
7078                 if (IS_PF(sc)) {
7079                         REG_WR(sc,
7080                                NIG_REG_EGRESS_DRAIN0_MODE +
7081                                sc->link_params.port * 4, 0);
7082                         bnx2x_stats_handle(sc, STATS_EVENT_LINK_UP);
7083                         bnx2x_link_report(sc);
7084                 }
7085         }
7086
7087         if (IS_PF(sc)) {
7088                 if (sc->link_vars.link_up) {
7089                         bnx2x_stats_handle(sc, STATS_EVENT_LINK_UP);
7090                 } else {
7091                         bnx2x_stats_handle(sc, STATS_EVENT_STOP);
7092                 }
7093                 bnx2x_link_report(sc);
7094         } else {
7095                 bnx2x_link_report_locked(sc);
7096                 bnx2x_stats_handle(sc, STATS_EVENT_LINK_UP);
7097         }
7098 }
7099
7100 static int bnx2x_initial_phy_init(struct bnx2x_softc *sc, int load_mode)
7101 {
7102         int rc, cfg_idx = bnx2x_get_link_cfg_idx(sc);
7103         uint16_t req_line_speed = sc->link_params.req_line_speed[cfg_idx];
7104         struct elink_params *lp = &sc->link_params;
7105
7106         bnx2x_set_requested_fc(sc);
7107
7108         bnx2x_acquire_phy_lock(sc);
7109
7110         if (load_mode == LOAD_DIAG) {
7111                 lp->loopback_mode = ELINK_LOOPBACK_XGXS;
7112 /* Prefer doing PHY loopback at 10G speed, if possible */
7113                 if (lp->req_line_speed[cfg_idx] < ELINK_SPEED_10000) {
7114                         if (lp->speed_cap_mask[cfg_idx] &
7115                             PORT_HW_CFG_SPEED_CAPABILITY_D0_10G) {
7116                                 lp->req_line_speed[cfg_idx] = ELINK_SPEED_10000;
7117                         } else {
7118                                 lp->req_line_speed[cfg_idx] = ELINK_SPEED_1000;
7119                         }
7120                 }
7121         }
7122
7123         if (load_mode == LOAD_LOOPBACK_EXT) {
7124                 lp->loopback_mode = ELINK_LOOPBACK_EXT;
7125         }
7126
7127         rc = elink_phy_init(&sc->link_params, &sc->link_vars);
7128
7129         bnx2x_release_phy_lock(sc);
7130
7131         bnx2x_calc_fc_adv(sc);
7132
7133         if (sc->link_vars.link_up) {
7134                 bnx2x_stats_handle(sc, STATS_EVENT_LINK_UP);
7135                 bnx2x_link_report(sc);
7136         }
7137
7138         sc->link_params.req_line_speed[cfg_idx] = req_line_speed;
7139         return rc;
7140 }
7141
7142 /* update flags in shmem */
7143 static void
7144 bnx2x_update_drv_flags(struct bnx2x_softc *sc, uint32_t flags, uint32_t set)
7145 {
7146         uint32_t drv_flags;
7147
7148         if (SHMEM2_HAS(sc, drv_flags)) {
7149                 bnx2x_acquire_hw_lock(sc, HW_LOCK_RESOURCE_DRV_FLAGS);
7150                 drv_flags = SHMEM2_RD(sc, drv_flags);
7151
7152                 if (set) {
7153                         drv_flags |= flags;
7154                 } else {
7155                         drv_flags &= ~flags;
7156                 }
7157
7158                 SHMEM2_WR(sc, drv_flags, drv_flags);
7159
7160                 bnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_DRV_FLAGS);
7161         }
7162 }
7163
7164 /* periodic timer callout routine, only runs when the interface is up */
7165 void bnx2x_periodic_callout(struct bnx2x_softc *sc)
7166 {
7167         if ((sc->state != BNX2X_STATE_OPEN) ||
7168             (atomic_load_acq_long(&sc->periodic_flags) == PERIODIC_STOP)) {
7169                 PMD_DRV_LOG(DEBUG, sc, "periodic callout exit (state=0x%x)",
7170                             sc->state);
7171                 return;
7172         }
7173         if (!CHIP_REV_IS_SLOW(sc)) {
7174 /*
7175  * This barrier is needed to ensure the ordering between the writing
7176  * to the sc->port.pmf in the bnx2x_nic_load() or bnx2x_pmf_update() and
7177  * the reading here.
7178  */
7179                 mb();
7180                 if (sc->port.pmf) {
7181                         bnx2x_acquire_phy_lock(sc);
7182                         elink_period_func(&sc->link_params, &sc->link_vars);
7183                         bnx2x_release_phy_lock(sc);
7184                 }
7185         }
7186 #ifdef BNX2X_PULSE
7187         if (IS_PF(sc) && !BNX2X_NOMCP(sc)) {
7188                 int mb_idx = SC_FW_MB_IDX(sc);
7189                 uint32_t drv_pulse;
7190                 uint32_t mcp_pulse;
7191
7192                 ++sc->fw_drv_pulse_wr_seq;
7193                 sc->fw_drv_pulse_wr_seq &= DRV_PULSE_SEQ_MASK;
7194
7195                 drv_pulse = sc->fw_drv_pulse_wr_seq;
7196                 bnx2x_drv_pulse(sc);
7197
7198                 mcp_pulse = (SHMEM_RD(sc, func_mb[mb_idx].mcp_pulse_mb) &
7199                              MCP_PULSE_SEQ_MASK);
7200
7201 /*
7202  * The delta between driver pulse and mcp response should
7203  * be 1 (before mcp response) or 0 (after mcp response).
7204  */
7205                 if ((drv_pulse != mcp_pulse) &&
7206                     (drv_pulse != ((mcp_pulse + 1) & MCP_PULSE_SEQ_MASK))) {
7207                         /* someone lost a heartbeat... */
7208                         PMD_DRV_LOG(ERR, sc,
7209                                     "drv_pulse (0x%x) != mcp_pulse (0x%x)",
7210                                     drv_pulse, mcp_pulse);
7211                 }
7212         }
7213 #endif
7214 }
7215
7216 /* start the controller */
7217 static __rte_noinline
7218 int bnx2x_nic_load(struct bnx2x_softc *sc)
7219 {
7220         uint32_t val;
7221         uint32_t load_code = 0;
7222         int i, rc = 0;
7223
7224         PMD_INIT_FUNC_TRACE(sc);
7225
7226         sc->state = BNX2X_STATE_OPENING_WAITING_LOAD;
7227
7228         if (IS_PF(sc)) {
7229 /* must be called before memory allocation and HW init */
7230                 bnx2x_ilt_set_info(sc);
7231         }
7232
7233         bnx2x_set_fp_rx_buf_size(sc);
7234
7235         if (IS_PF(sc)) {
7236                 if (bnx2x_alloc_mem(sc) != 0) {
7237                         sc->state = BNX2X_STATE_CLOSED;
7238                         rc = -ENOMEM;
7239                         goto bnx2x_nic_load_error0;
7240                 }
7241         }
7242
7243         if (bnx2x_alloc_fw_stats_mem(sc) != 0) {
7244                 sc->state = BNX2X_STATE_CLOSED;
7245                 rc = -ENOMEM;
7246                 goto bnx2x_nic_load_error0;
7247         }
7248
7249         if (IS_VF(sc)) {
7250                 rc = bnx2x_vf_init(sc);
7251                 if (rc) {
7252                         sc->state = BNX2X_STATE_ERROR;
7253                         goto bnx2x_nic_load_error0;
7254                 }
7255         }
7256
7257         if (IS_PF(sc)) {
7258 /* set pf load just before approaching the MCP */
7259                 bnx2x_set_pf_load(sc);
7260
7261 /* if MCP exists send load request and analyze response */
7262                 if (!BNX2X_NOMCP(sc)) {
7263                         /* attempt to load pf */
7264                         if (bnx2x_nic_load_request(sc, &load_code) != 0) {
7265                                 sc->state = BNX2X_STATE_CLOSED;
7266                                 rc = -ENXIO;
7267                                 goto bnx2x_nic_load_error1;
7268                         }
7269
7270                         /* what did the MCP say? */
7271                         if (bnx2x_nic_load_analyze_req(sc, load_code) != 0) {
7272                                 bnx2x_fw_command(sc, DRV_MSG_CODE_LOAD_DONE, 0);
7273                                 sc->state = BNX2X_STATE_CLOSED;
7274                                 rc = -ENXIO;
7275                                 goto bnx2x_nic_load_error2;
7276                         }
7277                 } else {
7278                         PMD_DRV_LOG(INFO, sc, "Device has no MCP!");
7279                         load_code = bnx2x_nic_load_no_mcp(sc);
7280                 }
7281
7282 /* mark PMF if applicable */
7283                 bnx2x_nic_load_pmf(sc, load_code);
7284
7285 /* Init Function state controlling object */
7286                 bnx2x_init_func_obj(sc);
7287
7288 /* Initialize HW */
7289                 if (bnx2x_init_hw(sc, load_code) != 0) {
7290                         PMD_DRV_LOG(NOTICE, sc, "HW init failed");
7291                         bnx2x_fw_command(sc, DRV_MSG_CODE_LOAD_DONE, 0);
7292                         sc->state = BNX2X_STATE_CLOSED;
7293                         rc = -ENXIO;
7294                         goto bnx2x_nic_load_error2;
7295                 }
7296         }
7297
7298         bnx2x_nic_init(sc, load_code);
7299
7300         /* Init per-function objects */
7301         if (IS_PF(sc)) {
7302                 bnx2x_init_objs(sc);
7303
7304 /* set AFEX default VLAN tag to an invalid value */
7305                 sc->devinfo.mf_info.afex_def_vlan_tag = -1;
7306
7307                 sc->state = BNX2X_STATE_OPENING_WAITING_PORT;
7308                 rc = bnx2x_func_start(sc);
7309                 if (rc) {
7310                         PMD_DRV_LOG(NOTICE, sc, "Function start failed!");
7311                         bnx2x_fw_command(sc, DRV_MSG_CODE_LOAD_DONE, 0);
7312                         sc->state = BNX2X_STATE_ERROR;
7313                         goto bnx2x_nic_load_error3;
7314                 }
7315
7316 /* send LOAD_DONE command to MCP */
7317                 if (!BNX2X_NOMCP(sc)) {
7318                         load_code =
7319                             bnx2x_fw_command(sc, DRV_MSG_CODE_LOAD_DONE, 0);
7320                         if (!load_code) {
7321                                 PMD_DRV_LOG(NOTICE, sc,
7322                                             "MCP response failure, aborting");
7323                                 sc->state = BNX2X_STATE_ERROR;
7324                                 rc = -ENXIO;
7325                                 goto bnx2x_nic_load_error3;
7326                         }
7327                 }
7328         }
7329
7330         rc = bnx2x_setup_leading(sc);
7331         if (rc) {
7332                 PMD_DRV_LOG(NOTICE, sc, "Setup leading failed!");
7333                 sc->state = BNX2X_STATE_ERROR;
7334                 goto bnx2x_nic_load_error3;
7335         }
7336
7337         FOR_EACH_NONDEFAULT_ETH_QUEUE(sc, i) {
7338                 if (IS_PF(sc))
7339                         rc = bnx2x_setup_queue(sc, &sc->fp[i], FALSE);
7340                 else            /* IS_VF(sc) */
7341                         rc = bnx2x_vf_setup_queue(sc, &sc->fp[i], FALSE);
7342
7343                 if (rc) {
7344                         PMD_DRV_LOG(NOTICE, sc, "Queue(%d) setup failed", i);
7345                         sc->state = BNX2X_STATE_ERROR;
7346                         goto bnx2x_nic_load_error3;
7347                 }
7348         }
7349
7350         rc = bnx2x_init_rss_pf(sc);
7351         if (rc) {
7352                 PMD_DRV_LOG(NOTICE, sc, "PF RSS init failed");
7353                 sc->state = BNX2X_STATE_ERROR;
7354                 goto bnx2x_nic_load_error3;
7355         }
7356
7357         /* now when Clients are configured we are ready to work */
7358         sc->state = BNX2X_STATE_OPEN;
7359
7360         /* Configure a ucast MAC */
7361         if (IS_PF(sc)) {
7362                 rc = bnx2x_set_eth_mac(sc, TRUE);
7363         } else {                /* IS_VF(sc) */
7364                 rc = bnx2x_vf_set_mac(sc, TRUE);
7365         }
7366
7367         if (rc) {
7368                 PMD_DRV_LOG(NOTICE, sc, "Setting Ethernet MAC failed");
7369                 sc->state = BNX2X_STATE_ERROR;
7370                 goto bnx2x_nic_load_error3;
7371         }
7372
7373         if (sc->port.pmf) {
7374                 rc = bnx2x_initial_phy_init(sc, LOAD_OPEN);
7375                 if (rc) {
7376                         sc->state = BNX2X_STATE_ERROR;
7377                         goto bnx2x_nic_load_error3;
7378                 }
7379         }
7380
7381         sc->link_params.feature_config_flags &=
7382             ~ELINK_FEATURE_CONFIG_BOOT_FROM_SAN;
7383
7384         /* start the Tx */
7385         switch (LOAD_OPEN) {
7386         case LOAD_NORMAL:
7387         case LOAD_OPEN:
7388                 break;
7389
7390         case LOAD_DIAG:
7391         case LOAD_LOOPBACK_EXT:
7392                 sc->state = BNX2X_STATE_DIAG;
7393                 break;
7394
7395         default:
7396                 break;
7397         }
7398
7399         if (sc->port.pmf) {
7400                 bnx2x_update_drv_flags(sc, 1 << DRV_FLAGS_PORT_MASK, 0);
7401         } else {
7402                 bnx2x_link_status_update(sc);
7403         }
7404
7405         if (IS_PF(sc) && SHMEM2_HAS(sc, drv_capabilities_flag)) {
7406 /* mark driver is loaded in shmem2 */
7407                 val = SHMEM2_RD(sc, drv_capabilities_flag[SC_FW_MB_IDX(sc)]);
7408                 SHMEM2_WR(sc, drv_capabilities_flag[SC_FW_MB_IDX(sc)],
7409                           (val |
7410                            DRV_FLAGS_CAPABILITIES_LOADED_SUPPORTED |
7411                            DRV_FLAGS_CAPABILITIES_LOADED_L2));
7412         }
7413
7414         /* start fast path */
7415         /* Initialize Rx filter */
7416         bnx2x_set_rx_mode(sc);
7417
7418         /* wait for all pending SP commands to complete */
7419         if (IS_PF(sc) && !bnx2x_wait_sp_comp(sc, ~0x0UL)) {
7420                 PMD_DRV_LOG(NOTICE, sc, "Timeout waiting for all SPs to complete!");
7421                 bnx2x_periodic_stop(sc);
7422                 bnx2x_nic_unload(sc, UNLOAD_CLOSE, FALSE);
7423                 return -ENXIO;
7424         }
7425
7426         PMD_DRV_LOG(DEBUG, sc, "NIC successfully loaded");
7427
7428         return 0;
7429
7430 bnx2x_nic_load_error3:
7431
7432         if (IS_PF(sc)) {
7433                 bnx2x_int_disable_sync(sc, 1);
7434
7435 /* clean out queued objects */
7436                 bnx2x_squeeze_objects(sc);
7437         }
7438
7439 bnx2x_nic_load_error2:
7440
7441         if (IS_PF(sc) && !BNX2X_NOMCP(sc)) {
7442                 bnx2x_fw_command(sc, DRV_MSG_CODE_UNLOAD_REQ_WOL_MCP, 0);
7443                 bnx2x_fw_command(sc, DRV_MSG_CODE_UNLOAD_DONE, 0);
7444         }
7445
7446         sc->port.pmf = 0;
7447
7448 bnx2x_nic_load_error1:
7449
7450         /* clear pf_load status, as it was already set */
7451         if (IS_PF(sc)) {
7452                 bnx2x_clear_pf_load(sc);
7453         }
7454
7455 bnx2x_nic_load_error0:
7456
7457         bnx2x_free_fw_stats_mem(sc);
7458         bnx2x_free_mem(sc);
7459
7460         return rc;
7461 }
7462
7463 /*
7464 * Handles controller initialization.
7465 */
7466 int bnx2x_init(struct bnx2x_softc *sc)
7467 {
7468         int other_engine = SC_PATH(sc) ? 0 : 1;
7469         uint8_t other_load_status, load_status;
7470         uint8_t global = FALSE;
7471         int rc;
7472
7473         /* Check if the driver is still running and bail out if it is. */
7474         if (sc->state != BNX2X_STATE_CLOSED) {
7475                 PMD_DRV_LOG(DEBUG, sc, "Init called while driver is running!");
7476                 rc = 0;
7477                 goto bnx2x_init_done;
7478         }
7479
7480         bnx2x_set_power_state(sc, PCI_PM_D0);
7481
7482         /*
7483          * If parity occurred during the unload, then attentions and/or
7484          * RECOVERY_IN_PROGRESS may still be set. If so we want the first function
7485          * loaded on the current engine to complete the recovery. Parity recovery
7486          * is only relevant for PF driver.
7487          */
7488         if (IS_PF(sc)) {
7489                 other_load_status = bnx2x_get_load_status(sc, other_engine);
7490                 load_status = bnx2x_get_load_status(sc, SC_PATH(sc));
7491
7492                 if (!bnx2x_reset_is_done(sc, SC_PATH(sc)) ||
7493                     bnx2x_chk_parity_attn(sc, &global, TRUE)) {
7494                         do {
7495                                 /*
7496                                  * If there are attentions and they are in global blocks, set
7497                                  * the GLOBAL_RESET bit regardless whether it will be this
7498                                  * function that will complete the recovery or not.
7499                                  */
7500                                 if (global) {
7501                                         bnx2x_set_reset_global(sc);
7502                                 }
7503
7504                                 /*
7505                                  * Only the first function on the current engine should try
7506                                  * to recover in open. In case of attentions in global blocks
7507                                  * only the first in the chip should try to recover.
7508                                  */
7509                                 if ((!load_status
7510                                      && (!global ||!other_load_status))
7511                                     && bnx2x_trylock_leader_lock(sc)
7512                                     && !bnx2x_leader_reset(sc)) {
7513                                         PMD_DRV_LOG(INFO, sc,
7514                                                     "Recovered during init");
7515                                         break;
7516                                 }
7517
7518                                 /* recovery has failed... */
7519                                 bnx2x_set_power_state(sc, PCI_PM_D3hot);
7520
7521                                 sc->recovery_state = BNX2X_RECOVERY_FAILED;
7522
7523                                 PMD_DRV_LOG(NOTICE, sc,
7524                                             "Recovery flow hasn't properly "
7525                                             "completed yet, try again later. "
7526                                             "If you still see this message after a "
7527                                             "few retries then power cycle is required.");
7528
7529                                 rc = -ENXIO;
7530                                 goto bnx2x_init_done;
7531                         } while (0);
7532                 }
7533         }
7534
7535         sc->recovery_state = BNX2X_RECOVERY_DONE;
7536
7537         rc = bnx2x_nic_load(sc);
7538
7539 bnx2x_init_done:
7540
7541         if (rc) {
7542                 PMD_DRV_LOG(NOTICE, sc, "Initialization failed, "
7543                             "stack notified driver is NOT running!");
7544         }
7545
7546         return rc;
7547 }
7548
7549 static void bnx2x_get_function_num(struct bnx2x_softc *sc)
7550 {
7551         uint32_t val = 0;
7552
7553         /*
7554          * Read the ME register to get the function number. The ME register
7555          * holds the relative-function number and absolute-function number. The
7556          * absolute-function number appears only in E2 and above. Before that
7557          * these bits always contained zero, therefore we cannot blindly use them.
7558          */
7559
7560         val = REG_RD(sc, BAR_ME_REGISTER);
7561
7562         sc->pfunc_rel =
7563             (uint8_t) ((val & ME_REG_PF_NUM) >> ME_REG_PF_NUM_SHIFT);
7564         sc->path_id =
7565             (uint8_t) ((val & ME_REG_ABS_PF_NUM) >> ME_REG_ABS_PF_NUM_SHIFT) &
7566             1;
7567
7568         if (CHIP_PORT_MODE(sc) == CHIP_4_PORT_MODE) {
7569                 sc->pfunc_abs = ((sc->pfunc_rel << 1) | sc->path_id);
7570         } else {
7571                 sc->pfunc_abs = (sc->pfunc_rel | sc->path_id);
7572         }
7573
7574         PMD_DRV_LOG(DEBUG, sc,
7575                     "Relative function %d, Absolute function %d, Path %d",
7576                     sc->pfunc_rel, sc->pfunc_abs, sc->path_id);
7577 }
7578
7579 static uint32_t bnx2x_get_shmem_mf_cfg_base(struct bnx2x_softc *sc)
7580 {
7581         uint32_t shmem2_size;
7582         uint32_t offset;
7583         uint32_t mf_cfg_offset_value;
7584
7585         /* Non 57712 */
7586         offset = (SHMEM_ADDR(sc, func_mb) +
7587                   (MAX_FUNC_NUM * sizeof(struct drv_func_mb)));
7588
7589         /* 57712 plus */
7590         if (sc->devinfo.shmem2_base != 0) {
7591                 shmem2_size = SHMEM2_RD(sc, size);
7592                 if (shmem2_size > offsetof(struct shmem2_region, mf_cfg_addr)) {
7593                         mf_cfg_offset_value = SHMEM2_RD(sc, mf_cfg_addr);
7594                         if (SHMEM_MF_CFG_ADDR_NONE != mf_cfg_offset_value) {
7595                                 offset = mf_cfg_offset_value;
7596                         }
7597                 }
7598         }
7599
7600         return offset;
7601 }
7602
7603 static uint32_t bnx2x_pcie_capability_read(struct bnx2x_softc *sc, int reg)
7604 {
7605         uint32_t ret;
7606         struct bnx2x_pci_cap *caps;
7607
7608         /* ensure PCIe capability is enabled */
7609         caps = pci_find_cap(sc, PCIY_EXPRESS, BNX2X_PCI_CAP);
7610         if (NULL != caps) {
7611                 PMD_DRV_LOG(DEBUG, sc, "Found PCIe capability: "
7612                             "id=0x%04X type=0x%04X addr=0x%08X",
7613                             caps->id, caps->type, caps->addr);
7614                 pci_read(sc, (caps->addr + reg), &ret, 2);
7615                 return ret;
7616         }
7617
7618         PMD_DRV_LOG(WARNING, sc, "PCIe capability NOT FOUND!!!");
7619
7620         return 0;
7621 }
7622
7623 static uint8_t bnx2x_is_pcie_pending(struct bnx2x_softc *sc)
7624 {
7625         return bnx2x_pcie_capability_read(sc, PCIR_EXPRESS_DEVICE_STA) &
7626                 PCIM_EXP_STA_TRANSACTION_PND;
7627 }
7628
7629 /*
7630 * Walk the PCI capabiites list for the device to find what features are
7631 * supported. These capabilites may be enabled/disabled by firmware so it's
7632 * best to walk the list rather than make assumptions.
7633 */
7634 static void bnx2x_probe_pci_caps(struct bnx2x_softc *sc)
7635 {
7636         PMD_INIT_FUNC_TRACE(sc);
7637
7638         struct bnx2x_pci_cap *caps;
7639         uint16_t link_status;
7640         int reg = 0;
7641
7642         /* check if PCI Power Management is enabled */
7643         caps = pci_find_cap(sc, PCIY_PMG, BNX2X_PCI_CAP);
7644         if (NULL != caps) {
7645                 PMD_DRV_LOG(DEBUG, sc, "Found PM capability: "
7646                             "id=0x%04X type=0x%04X addr=0x%08X",
7647                             caps->id, caps->type, caps->addr);
7648
7649                 sc->devinfo.pcie_cap_flags |= BNX2X_PM_CAPABLE_FLAG;
7650                 sc->devinfo.pcie_pm_cap_reg = caps->addr;
7651         }
7652
7653         link_status = bnx2x_pcie_capability_read(sc, PCIR_EXPRESS_LINK_STA);
7654
7655         sc->devinfo.pcie_link_speed = (link_status & PCIM_LINK_STA_SPEED);
7656         sc->devinfo.pcie_link_width =
7657             ((link_status & PCIM_LINK_STA_WIDTH) >> 4);
7658
7659         PMD_DRV_LOG(DEBUG, sc, "PCIe link speed=%d width=%d",
7660                     sc->devinfo.pcie_link_speed, sc->devinfo.pcie_link_width);
7661
7662         sc->devinfo.pcie_cap_flags |= BNX2X_PCIE_CAPABLE_FLAG;
7663
7664         /* check if MSI capability is enabled */
7665         caps = pci_find_cap(sc, PCIY_MSI, BNX2X_PCI_CAP);
7666         if (NULL != caps) {
7667                 PMD_DRV_LOG(DEBUG, sc, "Found MSI capability at 0x%04x", reg);
7668
7669                 sc->devinfo.pcie_cap_flags |= BNX2X_MSI_CAPABLE_FLAG;
7670                 sc->devinfo.pcie_msi_cap_reg = caps->addr;
7671         }
7672
7673         /* check if MSI-X capability is enabled */
7674         caps = pci_find_cap(sc, PCIY_MSIX, BNX2X_PCI_CAP);
7675         if (NULL != caps) {
7676                 PMD_DRV_LOG(DEBUG, sc, "Found MSI-X capability at 0x%04x", reg);
7677
7678                 sc->devinfo.pcie_cap_flags |= BNX2X_MSIX_CAPABLE_FLAG;
7679                 sc->devinfo.pcie_msix_cap_reg = caps->addr;
7680         }
7681 }
7682
7683 static int bnx2x_get_shmem_mf_cfg_info_sd(struct bnx2x_softc *sc)
7684 {
7685         struct bnx2x_mf_info *mf_info = &sc->devinfo.mf_info;
7686         uint32_t val;
7687
7688         /* get the outer vlan if we're in switch-dependent mode */
7689
7690         val = MFCFG_RD(sc, func_mf_config[SC_ABS_FUNC(sc)].e1hov_tag);
7691         mf_info->ext_id = (uint16_t) val;
7692
7693         mf_info->multi_vnics_mode = 1;
7694
7695         if (!VALID_OVLAN(mf_info->ext_id)) {
7696                 PMD_DRV_LOG(NOTICE, sc, "Invalid VLAN (%d)", mf_info->ext_id);
7697                 return 1;
7698         }
7699
7700         /* get the capabilities */
7701         if ((mf_info->mf_config[SC_VN(sc)] & FUNC_MF_CFG_PROTOCOL_MASK) ==
7702             FUNC_MF_CFG_PROTOCOL_ISCSI) {
7703                 mf_info->mf_protos_supported |= MF_PROTO_SUPPORT_ISCSI;
7704         } else if ((mf_info->mf_config[SC_VN(sc)] & FUNC_MF_CFG_PROTOCOL_MASK)
7705                    == FUNC_MF_CFG_PROTOCOL_FCOE) {
7706                 mf_info->mf_protos_supported |= MF_PROTO_SUPPORT_FCOE;
7707         } else {
7708                 mf_info->mf_protos_supported |= MF_PROTO_SUPPORT_ETHERNET;
7709         }
7710
7711         mf_info->vnics_per_port =
7712             (CHIP_PORT_MODE(sc) == CHIP_4_PORT_MODE) ? 2 : 4;
7713
7714         return 0;
7715 }
7716
7717 static uint32_t bnx2x_get_shmem_ext_proto_support_flags(struct bnx2x_softc *sc)
7718 {
7719         uint32_t retval = 0;
7720         uint32_t val;
7721
7722         val = MFCFG_RD(sc, func_ext_config[SC_ABS_FUNC(sc)].func_cfg);
7723
7724         if (val & MACP_FUNC_CFG_FLAGS_ENABLED) {
7725                 if (val & MACP_FUNC_CFG_FLAGS_ETHERNET) {
7726                         retval |= MF_PROTO_SUPPORT_ETHERNET;
7727                 }
7728                 if (val & MACP_FUNC_CFG_FLAGS_ISCSI_OFFLOAD) {
7729                         retval |= MF_PROTO_SUPPORT_ISCSI;
7730                 }
7731                 if (val & MACP_FUNC_CFG_FLAGS_FCOE_OFFLOAD) {
7732                         retval |= MF_PROTO_SUPPORT_FCOE;
7733                 }
7734         }
7735
7736         return retval;
7737 }
7738
7739 static int bnx2x_get_shmem_mf_cfg_info_si(struct bnx2x_softc *sc)
7740 {
7741         struct bnx2x_mf_info *mf_info = &sc->devinfo.mf_info;
7742         uint32_t val;
7743
7744         /*
7745          * There is no outer vlan if we're in switch-independent mode.
7746          * If the mac is valid then assume multi-function.
7747          */
7748
7749         val = MFCFG_RD(sc, func_ext_config[SC_ABS_FUNC(sc)].func_cfg);
7750
7751         mf_info->multi_vnics_mode = ((val & MACP_FUNC_CFG_FLAGS_MASK) != 0);
7752
7753         mf_info->mf_protos_supported =
7754             bnx2x_get_shmem_ext_proto_support_flags(sc);
7755
7756         mf_info->vnics_per_port =
7757             (CHIP_PORT_MODE(sc) == CHIP_4_PORT_MODE) ? 2 : 4;
7758
7759         return 0;
7760 }
7761
7762 static int bnx2x_get_shmem_mf_cfg_info_niv(struct bnx2x_softc *sc)
7763 {
7764         struct bnx2x_mf_info *mf_info = &sc->devinfo.mf_info;
7765         uint32_t e1hov_tag;
7766         uint32_t func_config;
7767         uint32_t niv_config;
7768
7769         mf_info->multi_vnics_mode = 1;
7770
7771         e1hov_tag = MFCFG_RD(sc, func_mf_config[SC_ABS_FUNC(sc)].e1hov_tag);
7772         func_config = MFCFG_RD(sc, func_mf_config[SC_ABS_FUNC(sc)].config);
7773         niv_config = MFCFG_RD(sc, func_mf_config[SC_ABS_FUNC(sc)].afex_config);
7774
7775         mf_info->ext_id =
7776             (uint16_t) ((e1hov_tag & FUNC_MF_CFG_E1HOV_TAG_MASK) >>
7777                         FUNC_MF_CFG_E1HOV_TAG_SHIFT);
7778
7779         mf_info->default_vlan =
7780             (uint16_t) ((e1hov_tag & FUNC_MF_CFG_AFEX_VLAN_MASK) >>
7781                         FUNC_MF_CFG_AFEX_VLAN_SHIFT);
7782
7783         mf_info->niv_allowed_priorities =
7784             (uint8_t) ((niv_config & FUNC_MF_CFG_AFEX_COS_FILTER_MASK) >>
7785                        FUNC_MF_CFG_AFEX_COS_FILTER_SHIFT);
7786
7787         mf_info->niv_default_cos =
7788             (uint8_t) ((func_config & FUNC_MF_CFG_TRANSMIT_PRIORITY_MASK) >>
7789                        FUNC_MF_CFG_TRANSMIT_PRIORITY_SHIFT);
7790
7791         mf_info->afex_vlan_mode =
7792             ((niv_config & FUNC_MF_CFG_AFEX_VLAN_MODE_MASK) >>
7793              FUNC_MF_CFG_AFEX_VLAN_MODE_SHIFT);
7794
7795         mf_info->niv_mba_enabled =
7796             ((niv_config & FUNC_MF_CFG_AFEX_MBA_ENABLED_MASK) >>
7797              FUNC_MF_CFG_AFEX_MBA_ENABLED_SHIFT);
7798
7799         mf_info->mf_protos_supported =
7800             bnx2x_get_shmem_ext_proto_support_flags(sc);
7801
7802         mf_info->vnics_per_port =
7803             (CHIP_PORT_MODE(sc) == CHIP_4_PORT_MODE) ? 2 : 4;
7804
7805         return 0;
7806 }
7807
7808 static int bnx2x_check_valid_mf_cfg(struct bnx2x_softc *sc)
7809 {
7810         struct bnx2x_mf_info *mf_info = &sc->devinfo.mf_info;
7811         uint32_t mf_cfg1;
7812         uint32_t mf_cfg2;
7813         uint32_t ovlan1;
7814         uint32_t ovlan2;
7815         uint8_t i, j;
7816
7817         /* various MF mode sanity checks... */
7818
7819         if (mf_info->mf_config[SC_VN(sc)] & FUNC_MF_CFG_FUNC_HIDE) {
7820                 PMD_DRV_LOG(NOTICE, sc,
7821                             "Enumerated function %d is marked as hidden",
7822                             SC_PORT(sc));
7823                 return 1;
7824         }
7825
7826         if ((mf_info->vnics_per_port > 1) && !mf_info->multi_vnics_mode) {
7827                 PMD_DRV_LOG(NOTICE, sc, "vnics_per_port=%d multi_vnics_mode=%d",
7828                             mf_info->vnics_per_port, mf_info->multi_vnics_mode);
7829                 return 1;
7830         }
7831
7832         if (mf_info->mf_mode == MULTI_FUNCTION_SD) {
7833 /* vnic id > 0 must have valid ovlan in switch-dependent mode */
7834                 if ((SC_VN(sc) > 0) && !VALID_OVLAN(OVLAN(sc))) {
7835                         PMD_DRV_LOG(NOTICE, sc, "mf_mode=SD vnic_id=%d ovlan=%d",
7836                                     SC_VN(sc), OVLAN(sc));
7837                         return 1;
7838                 }
7839
7840                 if (!VALID_OVLAN(OVLAN(sc)) && mf_info->multi_vnics_mode) {
7841                         PMD_DRV_LOG(NOTICE, sc,
7842                                     "mf_mode=SD multi_vnics_mode=%d ovlan=%d",
7843                                     mf_info->multi_vnics_mode, OVLAN(sc));
7844                         return 1;
7845                 }
7846
7847 /*
7848  * Verify all functions are either MF or SF mode. If MF, make sure
7849  * sure that all non-hidden functions have a valid ovlan. If SF,
7850  * make sure that all non-hidden functions have an invalid ovlan.
7851  */
7852                 FOREACH_ABS_FUNC_IN_PORT(sc, i) {
7853                         mf_cfg1 = MFCFG_RD(sc, func_mf_config[i].config);
7854                         ovlan1 = MFCFG_RD(sc, func_mf_config[i].e1hov_tag);
7855                         if (!(mf_cfg1 & FUNC_MF_CFG_FUNC_HIDE) &&
7856                             (((mf_info->multi_vnics_mode)
7857                               && !VALID_OVLAN(ovlan1))
7858                              || ((!mf_info->multi_vnics_mode)
7859                                  && VALID_OVLAN(ovlan1)))) {
7860                                 PMD_DRV_LOG(NOTICE, sc,
7861                                             "mf_mode=SD function %d MF config "
7862                                             "mismatch, multi_vnics_mode=%d ovlan=%d",
7863                                             i, mf_info->multi_vnics_mode,
7864                                             ovlan1);
7865                                 return 1;
7866                         }
7867                 }
7868
7869 /* Verify all funcs on the same port each have a different ovlan. */
7870                 FOREACH_ABS_FUNC_IN_PORT(sc, i) {
7871                         mf_cfg1 = MFCFG_RD(sc, func_mf_config[i].config);
7872                         ovlan1 = MFCFG_RD(sc, func_mf_config[i].e1hov_tag);
7873                         /* iterate from the next function on the port to the max func */
7874                         for (j = i + 2; j < MAX_FUNC_NUM; j += 2) {
7875                                 mf_cfg2 =
7876                                     MFCFG_RD(sc, func_mf_config[j].config);
7877                                 ovlan2 =
7878                                     MFCFG_RD(sc, func_mf_config[j].e1hov_tag);
7879                                 if (!(mf_cfg1 & FUNC_MF_CFG_FUNC_HIDE)
7880                                     && VALID_OVLAN(ovlan1)
7881                                     && !(mf_cfg2 & FUNC_MF_CFG_FUNC_HIDE)
7882                                     && VALID_OVLAN(ovlan2)
7883                                     && (ovlan1 == ovlan2)) {
7884                                         PMD_DRV_LOG(NOTICE, sc,
7885                                                     "mf_mode=SD functions %d and %d "
7886                                                     "have the same ovlan (%d)",
7887                                                     i, j, ovlan1);
7888                                         return 1;
7889                                 }
7890                         }
7891                 }
7892         }
7893         /* MULTI_FUNCTION_SD */
7894         return 0;
7895 }
7896
7897 static int bnx2x_get_mf_cfg_info(struct bnx2x_softc *sc)
7898 {
7899         struct bnx2x_mf_info *mf_info = &sc->devinfo.mf_info;
7900         uint32_t val, mac_upper;
7901         uint8_t i, vnic;
7902
7903         /* initialize mf_info defaults */
7904         mf_info->vnics_per_port = 1;
7905         mf_info->multi_vnics_mode = FALSE;
7906         mf_info->path_has_ovlan = FALSE;
7907         mf_info->mf_mode = SINGLE_FUNCTION;
7908
7909         if (!CHIP_IS_MF_CAP(sc)) {
7910                 return 0;
7911         }
7912
7913         if (sc->devinfo.mf_cfg_base == SHMEM_MF_CFG_ADDR_NONE) {
7914                 PMD_DRV_LOG(NOTICE, sc, "Invalid mf_cfg_base!");
7915                 return 1;
7916         }
7917
7918         /* get the MF mode (switch dependent / independent / single-function) */
7919
7920         val = SHMEM_RD(sc, dev_info.shared_feature_config.config);
7921
7922         switch (val & SHARED_FEAT_CFG_FORCE_SF_MODE_MASK) {
7923         case SHARED_FEAT_CFG_FORCE_SF_MODE_SWITCH_INDEPT:
7924
7925                 mac_upper =
7926                     MFCFG_RD(sc, func_mf_config[SC_ABS_FUNC(sc)].mac_upper);
7927
7928                 /* check for legal upper mac bytes */
7929                 if (mac_upper != FUNC_MF_CFG_UPPERMAC_DEFAULT) {
7930                         mf_info->mf_mode = MULTI_FUNCTION_SI;
7931                 } else {
7932                         PMD_DRV_LOG(NOTICE, sc,
7933                                     "Invalid config for Switch Independent mode");
7934                 }
7935
7936                 break;
7937
7938         case SHARED_FEAT_CFG_FORCE_SF_MODE_MF_ALLOWED:
7939         case SHARED_FEAT_CFG_FORCE_SF_MODE_SPIO4:
7940
7941                 /* get outer vlan configuration */
7942                 val = MFCFG_RD(sc, func_mf_config[SC_ABS_FUNC(sc)].e1hov_tag);
7943
7944                 if ((val & FUNC_MF_CFG_E1HOV_TAG_MASK) !=
7945                     FUNC_MF_CFG_E1HOV_TAG_DEFAULT) {
7946                         mf_info->mf_mode = MULTI_FUNCTION_SD;
7947                 } else {
7948                         PMD_DRV_LOG(NOTICE, sc,
7949                                     "Invalid config for Switch Dependent mode");
7950                 }
7951
7952                 break;
7953
7954         case SHARED_FEAT_CFG_FORCE_SF_MODE_FORCED_SF:
7955
7956                 /* not in MF mode, vnics_per_port=1 and multi_vnics_mode=FALSE */
7957                 return 0;
7958
7959         case SHARED_FEAT_CFG_FORCE_SF_MODE_AFEX_MODE:
7960
7961                 /*
7962                  * Mark MF mode as NIV if MCP version includes NPAR-SD support
7963                  * and the MAC address is valid.
7964                  */
7965                 mac_upper =
7966                     MFCFG_RD(sc, func_mf_config[SC_ABS_FUNC(sc)].mac_upper);
7967
7968                 if ((SHMEM2_HAS(sc, afex_driver_support)) &&
7969                     (mac_upper != FUNC_MF_CFG_UPPERMAC_DEFAULT)) {
7970                         mf_info->mf_mode = MULTI_FUNCTION_AFEX;
7971                 } else {
7972                         PMD_DRV_LOG(NOTICE, sc, "Invalid config for AFEX mode");
7973                 }
7974
7975                 break;
7976
7977         default:
7978
7979                 PMD_DRV_LOG(NOTICE, sc, "Unknown MF mode (0x%08x)",
7980                             (val & SHARED_FEAT_CFG_FORCE_SF_MODE_MASK));
7981
7982                 return 1;
7983         }
7984
7985         /* set path mf_mode (which could be different than function mf_mode) */
7986         if (mf_info->mf_mode == MULTI_FUNCTION_SD) {
7987                 mf_info->path_has_ovlan = TRUE;
7988         } else if (mf_info->mf_mode == SINGLE_FUNCTION) {
7989 /*
7990  * Decide on path multi vnics mode. If we're not in MF mode and in
7991  * 4-port mode, this is good enough to check vnic-0 of the other port
7992  * on the same path
7993  */
7994                 if (CHIP_PORT_MODE(sc) == CHIP_4_PORT_MODE) {
7995                         uint8_t other_port = !(PORT_ID(sc) & 1);
7996                         uint8_t abs_func_other_port =
7997                             (SC_PATH(sc) + (2 * other_port));
7998
7999                         val =
8000                             MFCFG_RD(sc,
8001                                      func_mf_config
8002                                      [abs_func_other_port].e1hov_tag);
8003
8004                         mf_info->path_has_ovlan = VALID_OVLAN((uint16_t) val);
8005                 }
8006         }
8007
8008         if (mf_info->mf_mode == SINGLE_FUNCTION) {
8009 /* invalid MF config */
8010                 if (SC_VN(sc) >= 1) {
8011                         PMD_DRV_LOG(NOTICE, sc, "VNIC ID >= 1 in SF mode");
8012                         return 1;
8013                 }
8014
8015                 return 0;
8016         }
8017
8018         /* get the MF configuration */
8019         mf_info->mf_config[SC_VN(sc)] =
8020             MFCFG_RD(sc, func_mf_config[SC_ABS_FUNC(sc)].config);
8021
8022         switch (mf_info->mf_mode) {
8023         case MULTI_FUNCTION_SD:
8024
8025                 bnx2x_get_shmem_mf_cfg_info_sd(sc);
8026                 break;
8027
8028         case MULTI_FUNCTION_SI:
8029
8030                 bnx2x_get_shmem_mf_cfg_info_si(sc);
8031                 break;
8032
8033         case MULTI_FUNCTION_AFEX:
8034
8035                 bnx2x_get_shmem_mf_cfg_info_niv(sc);
8036                 break;
8037
8038         default:
8039
8040                 PMD_DRV_LOG(NOTICE, sc, "Get MF config failed (mf_mode=0x%08x)",
8041                             mf_info->mf_mode);
8042                 return 1;
8043         }
8044
8045         /* get the congestion management parameters */
8046
8047         vnic = 0;
8048         FOREACH_ABS_FUNC_IN_PORT(sc, i) {
8049 /* get min/max bw */
8050                 val = MFCFG_RD(sc, func_mf_config[i].config);
8051                 mf_info->min_bw[vnic] =
8052                     ((val & FUNC_MF_CFG_MIN_BW_MASK) >>
8053                      FUNC_MF_CFG_MIN_BW_SHIFT);
8054                 mf_info->max_bw[vnic] =
8055                     ((val & FUNC_MF_CFG_MAX_BW_MASK) >>
8056                      FUNC_MF_CFG_MAX_BW_SHIFT);
8057                 vnic++;
8058         }
8059
8060         return bnx2x_check_valid_mf_cfg(sc);
8061 }
8062
8063 static int bnx2x_get_shmem_info(struct bnx2x_softc *sc)
8064 {
8065         int port;
8066         uint32_t mac_hi, mac_lo, val;
8067
8068         PMD_INIT_FUNC_TRACE(sc);
8069
8070         port = SC_PORT(sc);
8071         mac_hi = mac_lo = 0;
8072
8073         sc->link_params.sc = sc;
8074         sc->link_params.port = port;
8075
8076         /* get the hardware config info */
8077         sc->devinfo.hw_config = SHMEM_RD(sc, dev_info.shared_hw_config.config);
8078         sc->devinfo.hw_config2 =
8079             SHMEM_RD(sc, dev_info.shared_hw_config.config2);
8080
8081         sc->link_params.hw_led_mode =
8082             ((sc->devinfo.hw_config & SHARED_HW_CFG_LED_MODE_MASK) >>
8083              SHARED_HW_CFG_LED_MODE_SHIFT);
8084
8085         /* get the port feature config */
8086         sc->port.config =
8087             SHMEM_RD(sc, dev_info.port_feature_config[port].config);
8088
8089         /* get the link params */
8090         sc->link_params.speed_cap_mask[ELINK_INT_PHY] =
8091             SHMEM_RD(sc, dev_info.port_hw_config[port].speed_capability_mask)
8092             & PORT_HW_CFG_SPEED_CAPABILITY_D0_MASK;
8093         sc->link_params.speed_cap_mask[ELINK_EXT_PHY1] =
8094             SHMEM_RD(sc, dev_info.port_hw_config[port].speed_capability_mask2)
8095             & PORT_HW_CFG_SPEED_CAPABILITY_D0_MASK;
8096
8097         /* get the lane config */
8098         sc->link_params.lane_config =
8099             SHMEM_RD(sc, dev_info.port_hw_config[port].lane_config);
8100
8101         /* get the link config */
8102         val = SHMEM_RD(sc, dev_info.port_feature_config[port].link_config);
8103         sc->port.link_config[ELINK_INT_PHY] = val;
8104         sc->link_params.switch_cfg = (val & PORT_FEATURE_CONNECTED_SWITCH_MASK);
8105         sc->port.link_config[ELINK_EXT_PHY1] =
8106             SHMEM_RD(sc, dev_info.port_feature_config[port].link_config2);
8107
8108         /* get the override preemphasis flag and enable it or turn it off */
8109         val = SHMEM_RD(sc, dev_info.shared_feature_config.config);
8110         if (val & SHARED_FEAT_CFG_OVERRIDE_PREEMPHASIS_CFG_ENABLED) {
8111                 sc->link_params.feature_config_flags |=
8112                     ELINK_FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED;
8113         } else {
8114                 sc->link_params.feature_config_flags &=
8115                     ~ELINK_FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED;
8116         }
8117
8118         val = sc->devinfo.bc_ver >> 8;
8119         if (val < BNX2X_BC_VER) {
8120                 /* for now only warn later we might need to enforce this */
8121                 PMD_DRV_LOG(NOTICE, sc, "This driver needs bc_ver %X but found %X, please upgrade BC\n",
8122                             BNX2X_BC_VER, val);
8123         }
8124         sc->link_params.feature_config_flags |=
8125                                 (val >= REQ_BC_VER_4_VRFY_FIRST_PHY_OPT_MDL) ?
8126                                 ELINK_FEATURE_CONFIG_BC_SUPPORTS_OPT_MDL_VRFY :
8127                                 0;
8128
8129         sc->link_params.feature_config_flags |=
8130                 (val >= REQ_BC_VER_4_VRFY_SPECIFIC_PHY_OPT_MDL) ?
8131                 ELINK_FEATURE_CONFIG_BC_SUPPORTS_DUAL_PHY_OPT_MDL_VRFY : 0;
8132         sc->link_params.feature_config_flags |=
8133                 (val >= REQ_BC_VER_4_VRFY_AFEX_SUPPORTED) ?
8134                 ELINK_FEATURE_CONFIG_BC_SUPPORTS_AFEX : 0;
8135         sc->link_params.feature_config_flags |=
8136                 (val >= REQ_BC_VER_4_SFP_TX_DISABLE_SUPPORTED) ?
8137                 ELINK_FEATURE_CONFIG_BC_SUPPORTS_SFP_TX_DISABLED : 0;
8138
8139         /* get the initial value of the link params */
8140         sc->link_params.multi_phy_config =
8141             SHMEM_RD(sc, dev_info.port_hw_config[port].multi_phy_config);
8142
8143         /* get external phy info */
8144         sc->port.ext_phy_config =
8145             SHMEM_RD(sc, dev_info.port_hw_config[port].external_phy_config);
8146
8147         /* get the multifunction configuration */
8148         bnx2x_get_mf_cfg_info(sc);
8149
8150         /* get the mac address */
8151         if (IS_MF(sc)) {
8152                 mac_hi =
8153                     MFCFG_RD(sc, func_mf_config[SC_ABS_FUNC(sc)].mac_upper);
8154                 mac_lo =
8155                     MFCFG_RD(sc, func_mf_config[SC_ABS_FUNC(sc)].mac_lower);
8156         } else {
8157                 mac_hi = SHMEM_RD(sc, dev_info.port_hw_config[port].mac_upper);
8158                 mac_lo = SHMEM_RD(sc, dev_info.port_hw_config[port].mac_lower);
8159         }
8160
8161         if ((mac_lo == 0) && (mac_hi == 0)) {
8162                 *sc->mac_addr_str = 0;
8163                 PMD_DRV_LOG(NOTICE, sc, "No Ethernet address programmed!");
8164         } else {
8165                 sc->link_params.mac_addr[0] = (uint8_t) (mac_hi >> 8);
8166                 sc->link_params.mac_addr[1] = (uint8_t) (mac_hi);
8167                 sc->link_params.mac_addr[2] = (uint8_t) (mac_lo >> 24);
8168                 sc->link_params.mac_addr[3] = (uint8_t) (mac_lo >> 16);
8169                 sc->link_params.mac_addr[4] = (uint8_t) (mac_lo >> 8);
8170                 sc->link_params.mac_addr[5] = (uint8_t) (mac_lo);
8171                 snprintf(sc->mac_addr_str, sizeof(sc->mac_addr_str),
8172                          "%02x:%02x:%02x:%02x:%02x:%02x",
8173                          sc->link_params.mac_addr[0],
8174                          sc->link_params.mac_addr[1],
8175                          sc->link_params.mac_addr[2],
8176                          sc->link_params.mac_addr[3],
8177                          sc->link_params.mac_addr[4],
8178                          sc->link_params.mac_addr[5]);
8179                 PMD_DRV_LOG(DEBUG, sc,
8180                             "Ethernet address: %s", sc->mac_addr_str);
8181         }
8182
8183         return 0;
8184 }
8185
8186 static void bnx2x_media_detect(struct bnx2x_softc *sc)
8187 {
8188         uint32_t phy_idx = bnx2x_get_cur_phy_idx(sc);
8189         switch (sc->link_params.phy[phy_idx].media_type) {
8190         case ELINK_ETH_PHY_SFPP_10G_FIBER:
8191         case ELINK_ETH_PHY_SFP_1G_FIBER:
8192         case ELINK_ETH_PHY_XFP_FIBER:
8193         case ELINK_ETH_PHY_KR:
8194         case ELINK_ETH_PHY_CX4:
8195                 PMD_DRV_LOG(INFO, sc, "Found 10GBase-CX4 media.");
8196                 sc->media = IFM_10G_CX4;
8197                 break;
8198         case ELINK_ETH_PHY_DA_TWINAX:
8199                 PMD_DRV_LOG(INFO, sc, "Found 10Gb Twinax media.");
8200                 sc->media = IFM_10G_TWINAX;
8201                 break;
8202         case ELINK_ETH_PHY_BASE_T:
8203                 PMD_DRV_LOG(INFO, sc, "Found 10GBase-T media.");
8204                 sc->media = IFM_10G_T;
8205                 break;
8206         case ELINK_ETH_PHY_NOT_PRESENT:
8207                 PMD_DRV_LOG(INFO, sc, "Media not present.");
8208                 sc->media = 0;
8209                 break;
8210         case ELINK_ETH_PHY_UNSPECIFIED:
8211         default:
8212                 PMD_DRV_LOG(INFO, sc, "Unknown media!");
8213                 sc->media = 0;
8214                 break;
8215         }
8216 }
8217
8218 #define GET_FIELD(value, fname)                     \
8219 (((value) & (fname##_MASK)) >> (fname##_SHIFT))
8220 #define IGU_FID(val) GET_FIELD((val), IGU_REG_MAPPING_MEMORY_FID)
8221 #define IGU_VEC(val) GET_FIELD((val), IGU_REG_MAPPING_MEMORY_VECTOR)
8222
8223 static int bnx2x_get_igu_cam_info(struct bnx2x_softc *sc)
8224 {
8225         int pfid = SC_FUNC(sc);
8226         int igu_sb_id;
8227         uint32_t val;
8228         uint8_t fid, igu_sb_cnt = 0;
8229
8230         sc->igu_base_sb = 0xff;
8231
8232         if (CHIP_INT_MODE_IS_BC(sc)) {
8233                 int vn = SC_VN(sc);
8234                 igu_sb_cnt = sc->igu_sb_cnt;
8235                 sc->igu_base_sb = ((CHIP_IS_MODE_4_PORT(sc) ? pfid : vn) *
8236                                    FP_SB_MAX_E1x);
8237                 sc->igu_dsb_id = (E1HVN_MAX * FP_SB_MAX_E1x +
8238                                   (CHIP_IS_MODE_4_PORT(sc) ? pfid : vn));
8239                 return 0;
8240         }
8241
8242         /* IGU in normal mode - read CAM */
8243         for (igu_sb_id = 0;
8244              igu_sb_id < IGU_REG_MAPPING_MEMORY_SIZE; igu_sb_id++) {
8245                 val = REG_RD(sc, IGU_REG_MAPPING_MEMORY + igu_sb_id * 4);
8246                 if (!(val & IGU_REG_MAPPING_MEMORY_VALID)) {
8247                         continue;
8248                 }
8249                 fid = IGU_FID(val);
8250                 if (fid & IGU_FID_ENCODE_IS_PF) {
8251                         if ((fid & IGU_FID_PF_NUM_MASK) != pfid) {
8252                                 continue;
8253                         }
8254                         if (IGU_VEC(val) == 0) {
8255                                 /* default status block */
8256                                 sc->igu_dsb_id = igu_sb_id;
8257                         } else {
8258                                 if (sc->igu_base_sb == 0xff) {
8259                                         sc->igu_base_sb = igu_sb_id;
8260                                 }
8261                                 igu_sb_cnt++;
8262                         }
8263                 }
8264         }
8265
8266         /*
8267          * Due to new PF resource allocation by MFW T7.4 and above, it's optional
8268          * that number of CAM entries will not be equal to the value advertised in
8269          * PCI. Driver should use the minimal value of both as the actual status
8270          * block count
8271          */
8272         sc->igu_sb_cnt = min(sc->igu_sb_cnt, igu_sb_cnt);
8273
8274         if (igu_sb_cnt == 0) {
8275                 PMD_DRV_LOG(ERR, sc, "CAM configuration error");
8276                 return -1;
8277         }
8278
8279         return 0;
8280 }
8281
8282 /*
8283 * Gather various information from the device config space, the device itself,
8284 * shmem, and the user input.
8285 */
8286 static int bnx2x_get_device_info(struct bnx2x_softc *sc)
8287 {
8288         uint32_t val;
8289         int rc;
8290
8291         /* get the chip revision (chip metal comes from pci config space) */
8292         sc->devinfo.chip_id = sc->link_params.chip_id =
8293             (((REG_RD(sc, MISC_REG_CHIP_NUM) & 0xffff) << 16) |
8294              ((REG_RD(sc, MISC_REG_CHIP_REV) & 0xf) << 12) |
8295              (((REG_RD(sc, PCICFG_OFFSET + PCI_ID_VAL3) >> 24) & 0xf) << 4) |
8296              ((REG_RD(sc, MISC_REG_BOND_ID) & 0xf) << 0));
8297
8298         /* force 57811 according to MISC register */
8299         if (REG_RD(sc, MISC_REG_CHIP_TYPE) & MISC_REG_CHIP_TYPE_57811_MASK) {
8300                 if (CHIP_IS_57810(sc)) {
8301                         sc->devinfo.chip_id = ((CHIP_NUM_57811 << 16) |
8302                                                (sc->
8303                                                 devinfo.chip_id & 0x0000ffff));
8304                 } else if (CHIP_IS_57810_MF(sc)) {
8305                         sc->devinfo.chip_id = ((CHIP_NUM_57811_MF << 16) |
8306                                                (sc->
8307                                                 devinfo.chip_id & 0x0000ffff));
8308                 }
8309                 sc->devinfo.chip_id |= 0x1;
8310         }
8311
8312         PMD_DRV_LOG(DEBUG, sc,
8313                     "chip_id=0x%08x (num=0x%04x rev=0x%01x metal=0x%02x bond=0x%01x)",
8314                     sc->devinfo.chip_id,
8315                     ((sc->devinfo.chip_id >> 16) & 0xffff),
8316                     ((sc->devinfo.chip_id >> 12) & 0xf),
8317                     ((sc->devinfo.chip_id >> 4) & 0xff),
8318                     ((sc->devinfo.chip_id >> 0) & 0xf));
8319
8320         val = (REG_RD(sc, 0x2874) & 0x55);
8321         if ((sc->devinfo.chip_id & 0x1) || (CHIP_IS_E1H(sc) && (val == 0x55))) {
8322                 sc->flags |= BNX2X_ONE_PORT_FLAG;
8323                 PMD_DRV_LOG(DEBUG, sc, "single port device");
8324         }
8325
8326         /* set the doorbell size */
8327         sc->doorbell_size = (1 << BNX2X_DB_SHIFT);
8328
8329         /* determine whether the device is in 2 port or 4 port mode */
8330         sc->devinfo.chip_port_mode = CHIP_PORT_MODE_NONE;       /* E1h */
8331         if (CHIP_IS_E2E3(sc)) {
8332 /*
8333  * Read port4mode_en_ovwr[0]:
8334  *   If 1, four port mode is in port4mode_en_ovwr[1].
8335  *   If 0, four port mode is in port4mode_en[0].
8336  */
8337                 val = REG_RD(sc, MISC_REG_PORT4MODE_EN_OVWR);
8338                 if (val & 1) {
8339                         val = ((val >> 1) & 1);
8340                 } else {
8341                         val = REG_RD(sc, MISC_REG_PORT4MODE_EN);
8342                 }
8343
8344                 sc->devinfo.chip_port_mode =
8345                     (val) ? CHIP_4_PORT_MODE : CHIP_2_PORT_MODE;
8346
8347                 PMD_DRV_LOG(DEBUG, sc, "Port mode = %s", (val) ? "4" : "2");
8348         }
8349
8350         /* get the function and path info for the device */
8351         bnx2x_get_function_num(sc);
8352
8353         /* get the shared memory base address */
8354         sc->devinfo.shmem_base =
8355             sc->link_params.shmem_base = REG_RD(sc, MISC_REG_SHARED_MEM_ADDR);
8356         sc->devinfo.shmem2_base =
8357             REG_RD(sc, (SC_PATH(sc) ? MISC_REG_GENERIC_CR_1 :
8358                         MISC_REG_GENERIC_CR_0));
8359
8360         if (!sc->devinfo.shmem_base) {
8361 /* this should ONLY prevent upcoming shmem reads */
8362                 PMD_DRV_LOG(INFO, sc, "MCP not active");
8363                 sc->flags |= BNX2X_NO_MCP_FLAG;
8364                 return 0;
8365         }
8366
8367         /* make sure the shared memory contents are valid */
8368         val = SHMEM_RD(sc, validity_map[SC_PORT(sc)]);
8369         if ((val & (SHR_MEM_VALIDITY_DEV_INFO | SHR_MEM_VALIDITY_MB)) !=
8370             (SHR_MEM_VALIDITY_DEV_INFO | SHR_MEM_VALIDITY_MB)) {
8371                 PMD_DRV_LOG(NOTICE, sc, "Invalid SHMEM validity signature: 0x%08x",
8372                             val);
8373                 return 0;
8374         }
8375
8376         /* get the bootcode version */
8377         sc->devinfo.bc_ver = SHMEM_RD(sc, dev_info.bc_rev);
8378         snprintf(sc->devinfo.bc_ver_str,
8379                  sizeof(sc->devinfo.bc_ver_str),
8380                  "%d.%d.%d",
8381                  ((sc->devinfo.bc_ver >> 24) & 0xff),
8382                  ((sc->devinfo.bc_ver >> 16) & 0xff),
8383                  ((sc->devinfo.bc_ver >> 8) & 0xff));
8384         PMD_DRV_LOG(DEBUG, sc, "Bootcode version: %s", sc->devinfo.bc_ver_str);
8385
8386         /* get the bootcode shmem address */
8387         sc->devinfo.mf_cfg_base = bnx2x_get_shmem_mf_cfg_base(sc);
8388
8389         /* clean indirect addresses as they're not used */
8390         pci_write_long(sc, PCICFG_GRC_ADDRESS, 0);
8391         if (IS_PF(sc)) {
8392                 REG_WR(sc, PXP2_REG_PGL_ADDR_88_F0, 0);
8393                 REG_WR(sc, PXP2_REG_PGL_ADDR_8C_F0, 0);
8394                 REG_WR(sc, PXP2_REG_PGL_ADDR_90_F0, 0);
8395                 REG_WR(sc, PXP2_REG_PGL_ADDR_94_F0, 0);
8396                 if (CHIP_IS_E1x(sc)) {
8397                         REG_WR(sc, PXP2_REG_PGL_ADDR_88_F1, 0);
8398                         REG_WR(sc, PXP2_REG_PGL_ADDR_8C_F1, 0);
8399                         REG_WR(sc, PXP2_REG_PGL_ADDR_90_F1, 0);
8400                         REG_WR(sc, PXP2_REG_PGL_ADDR_94_F1, 0);
8401                 }
8402         }
8403
8404         /* get the nvram size */
8405         val = REG_RD(sc, MCP_REG_MCPR_NVM_CFG4);
8406         sc->devinfo.flash_size =
8407             (NVRAM_1MB_SIZE << (val & MCPR_NVM_CFG4_FLASH_SIZE));
8408
8409         bnx2x_set_power_state(sc, PCI_PM_D0);
8410         /* get various configuration parameters from shmem */
8411         bnx2x_get_shmem_info(sc);
8412
8413         /* initialize IGU parameters */
8414         if (CHIP_IS_E1x(sc)) {
8415                 sc->devinfo.int_block = INT_BLOCK_HC;
8416                 sc->igu_dsb_id = DEF_SB_IGU_ID;
8417                 sc->igu_base_sb = 0;
8418         } else {
8419                 sc->devinfo.int_block = INT_BLOCK_IGU;
8420
8421 /* do not allow device reset during IGU info preocessing */
8422                 bnx2x_acquire_hw_lock(sc, HW_LOCK_RESOURCE_RESET);
8423
8424                 val = REG_RD(sc, IGU_REG_BLOCK_CONFIGURATION);
8425
8426                 if (val & IGU_BLOCK_CONFIGURATION_REG_BACKWARD_COMP_EN) {
8427                         int tout = 5000;
8428
8429                         val &= ~(IGU_BLOCK_CONFIGURATION_REG_BACKWARD_COMP_EN);
8430                         REG_WR(sc, IGU_REG_BLOCK_CONFIGURATION, val);
8431                         REG_WR(sc, IGU_REG_RESET_MEMORIES, 0x7f);
8432
8433                         while (tout && REG_RD(sc, IGU_REG_RESET_MEMORIES)) {
8434                                 tout--;
8435                                 DELAY(1000);
8436                         }
8437
8438                         if (REG_RD(sc, IGU_REG_RESET_MEMORIES)) {
8439                                 PMD_DRV_LOG(NOTICE, sc,
8440                                             "FORCING IGU Normal Mode failed!!!");
8441                                 bnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_RESET);
8442                                 return -1;
8443                         }
8444                 }
8445
8446                 if (val & IGU_BLOCK_CONFIGURATION_REG_BACKWARD_COMP_EN) {
8447                         PMD_DRV_LOG(DEBUG, sc, "IGU Backward Compatible Mode");
8448                         sc->devinfo.int_block |= INT_BLOCK_MODE_BW_COMP;
8449                 } else {
8450                         PMD_DRV_LOG(DEBUG, sc, "IGU Normal Mode");
8451                 }
8452
8453                 rc = bnx2x_get_igu_cam_info(sc);
8454
8455                 bnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_RESET);
8456
8457                 if (rc) {
8458                         return rc;
8459                 }
8460         }
8461
8462         /*
8463          * Get base FW non-default (fast path) status block ID. This value is
8464          * used to initialize the fw_sb_id saved on the fp/queue structure to
8465          * determine the id used by the FW.
8466          */
8467         if (CHIP_IS_E1x(sc)) {
8468                 sc->base_fw_ndsb =
8469                     ((SC_PORT(sc) * FP_SB_MAX_E1x) + SC_L_ID(sc));
8470         } else {
8471 /*
8472  * 57712+ - We currently use one FW SB per IGU SB (Rx and Tx of
8473  * the same queue are indicated on the same IGU SB). So we prefer
8474  * FW and IGU SBs to be the same value.
8475  */
8476                 sc->base_fw_ndsb = sc->igu_base_sb;
8477         }
8478
8479         elink_phy_probe(&sc->link_params);
8480
8481         return 0;
8482 }
8483
8484 static void
8485 bnx2x_link_settings_supported(struct bnx2x_softc *sc, uint32_t switch_cfg)
8486 {
8487         uint32_t cfg_size = 0;
8488         uint32_t idx;
8489         uint8_t port = SC_PORT(sc);
8490
8491         /* aggregation of supported attributes of all external phys */
8492         sc->port.supported[0] = 0;
8493         sc->port.supported[1] = 0;
8494
8495         switch (sc->link_params.num_phys) {
8496         case 1:
8497                 sc->port.supported[0] =
8498                     sc->link_params.phy[ELINK_INT_PHY].supported;
8499                 cfg_size = 1;
8500                 break;
8501         case 2:
8502                 sc->port.supported[0] =
8503                     sc->link_params.phy[ELINK_EXT_PHY1].supported;
8504                 cfg_size = 1;
8505                 break;
8506         case 3:
8507                 if (sc->link_params.multi_phy_config &
8508                     PORT_HW_CFG_PHY_SWAPPED_ENABLED) {
8509                         sc->port.supported[1] =
8510                             sc->link_params.phy[ELINK_EXT_PHY1].supported;
8511                         sc->port.supported[0] =
8512                             sc->link_params.phy[ELINK_EXT_PHY2].supported;
8513                 } else {
8514                         sc->port.supported[0] =
8515                             sc->link_params.phy[ELINK_EXT_PHY1].supported;
8516                         sc->port.supported[1] =
8517                             sc->link_params.phy[ELINK_EXT_PHY2].supported;
8518                 }
8519                 cfg_size = 2;
8520                 break;
8521         }
8522
8523         if (!(sc->port.supported[0] || sc->port.supported[1])) {
8524                 PMD_DRV_LOG(ERR, sc,
8525                             "Invalid phy config in NVRAM (PHY1=0x%08x PHY2=0x%08x)",
8526                             SHMEM_RD(sc,
8527                                      dev_info.port_hw_config
8528                                      [port].external_phy_config),
8529                             SHMEM_RD(sc,
8530                                      dev_info.port_hw_config
8531                                      [port].external_phy_config2));
8532                 return;
8533         }
8534
8535         if (CHIP_IS_E3(sc))
8536                 sc->port.phy_addr = REG_RD(sc, MISC_REG_WC0_CTRL_PHY_ADDR);
8537         else {
8538                 switch (switch_cfg) {
8539                 case ELINK_SWITCH_CFG_1G:
8540                         sc->port.phy_addr =
8541                             REG_RD(sc,
8542                                    NIG_REG_SERDES0_CTRL_PHY_ADDR + port * 0x10);
8543                         break;
8544                 case ELINK_SWITCH_CFG_10G:
8545                         sc->port.phy_addr =
8546                             REG_RD(sc,
8547                                    NIG_REG_XGXS0_CTRL_PHY_ADDR + port * 0x18);
8548                         break;
8549                 default:
8550                         PMD_DRV_LOG(ERR, sc,
8551                                     "Invalid switch config in"
8552                                     "link_config=0x%08x",
8553                                     sc->port.link_config[0]);
8554                         return;
8555                 }
8556         }
8557
8558         PMD_DRV_LOG(INFO, sc, "PHY addr 0x%08x", sc->port.phy_addr);
8559
8560         /* mask what we support according to speed_cap_mask per configuration */
8561         for (idx = 0; idx < cfg_size; idx++) {
8562                 if (!(sc->link_params.speed_cap_mask[idx] &
8563                       PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_HALF)) {
8564                         sc->port.supported[idx] &=
8565                             ~ELINK_SUPPORTED_10baseT_Half;
8566                 }
8567
8568                 if (!(sc->link_params.speed_cap_mask[idx] &
8569                       PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL)) {
8570                         sc->port.supported[idx] &=
8571                             ~ELINK_SUPPORTED_10baseT_Full;
8572                 }
8573
8574                 if (!(sc->link_params.speed_cap_mask[idx] &
8575                       PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_HALF)) {
8576                         sc->port.supported[idx] &=
8577                             ~ELINK_SUPPORTED_100baseT_Half;
8578                 }
8579
8580                 if (!(sc->link_params.speed_cap_mask[idx] &
8581                       PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_FULL)) {
8582                         sc->port.supported[idx] &=
8583                             ~ELINK_SUPPORTED_100baseT_Full;
8584                 }
8585
8586                 if (!(sc->link_params.speed_cap_mask[idx] &
8587                       PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)) {
8588                         sc->port.supported[idx] &=
8589                             ~ELINK_SUPPORTED_1000baseT_Full;
8590                 }
8591
8592                 if (!(sc->link_params.speed_cap_mask[idx] &
8593                       PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G)) {
8594                         sc->port.supported[idx] &=
8595                             ~ELINK_SUPPORTED_2500baseX_Full;
8596                 }
8597
8598                 if (!(sc->link_params.speed_cap_mask[idx] &
8599                       PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)) {
8600                         sc->port.supported[idx] &=
8601                             ~ELINK_SUPPORTED_10000baseT_Full;
8602                 }
8603
8604                 if (!(sc->link_params.speed_cap_mask[idx] &
8605                       PORT_HW_CFG_SPEED_CAPABILITY_D0_20G)) {
8606                         sc->port.supported[idx] &=
8607                             ~ELINK_SUPPORTED_20000baseKR2_Full;
8608                 }
8609         }
8610
8611         PMD_DRV_LOG(INFO, sc, "PHY supported 0=0x%08x 1=0x%08x",
8612                     sc->port.supported[0], sc->port.supported[1]);
8613 }
8614
8615 static void bnx2x_link_settings_requested(struct bnx2x_softc *sc)
8616 {
8617         uint32_t link_config;
8618         uint32_t idx;
8619         uint32_t cfg_size = 0;
8620
8621         sc->port.advertising[0] = 0;
8622         sc->port.advertising[1] = 0;
8623
8624         switch (sc->link_params.num_phys) {
8625         case 1:
8626         case 2:
8627                 cfg_size = 1;
8628                 break;
8629         case 3:
8630                 cfg_size = 2;
8631                 break;
8632         }
8633
8634         for (idx = 0; idx < cfg_size; idx++) {
8635                 sc->link_params.req_duplex[idx] = DUPLEX_FULL;
8636                 link_config = sc->port.link_config[idx];
8637
8638                 switch (link_config & PORT_FEATURE_LINK_SPEED_MASK) {
8639                 case PORT_FEATURE_LINK_SPEED_AUTO:
8640                         if (sc->port.supported[idx] & ELINK_SUPPORTED_Autoneg) {
8641                                 sc->link_params.req_line_speed[idx] =
8642                                     ELINK_SPEED_AUTO_NEG;
8643                                 sc->port.advertising[idx] |=
8644                                     sc->port.supported[idx];
8645                                 if (sc->link_params.phy[ELINK_EXT_PHY1].type ==
8646                                     PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X84833)
8647                                         sc->port.advertising[idx] |=
8648                                             (ELINK_SUPPORTED_100baseT_Half |
8649                                              ELINK_SUPPORTED_100baseT_Full);
8650                         } else {
8651                                 /* force 10G, no AN */
8652                                 sc->link_params.req_line_speed[idx] =
8653                                     ELINK_SPEED_10000;
8654                                 sc->port.advertising[idx] |=
8655                                     (ADVERTISED_10000baseT_Full |
8656                                      ADVERTISED_FIBRE);
8657                                 continue;
8658                         }
8659                         break;
8660
8661                 case PORT_FEATURE_LINK_SPEED_10M_FULL:
8662                         if (sc->
8663                             port.supported[idx] & ELINK_SUPPORTED_10baseT_Full)
8664                         {
8665                                 sc->link_params.req_line_speed[idx] =
8666                                     ELINK_SPEED_10;
8667                                 sc->port.advertising[idx] |=
8668                                     (ADVERTISED_10baseT_Full | ADVERTISED_TP);
8669                         } else {
8670                                 PMD_DRV_LOG(ERR, sc,
8671                                             "Invalid NVRAM config link_config=0x%08x "
8672                                             "speed_cap_mask=0x%08x",
8673                                             link_config,
8674                                             sc->
8675                                             link_params.speed_cap_mask[idx]);
8676                                 return;
8677                         }
8678                         break;
8679
8680                 case PORT_FEATURE_LINK_SPEED_10M_HALF:
8681                         if (sc->
8682                             port.supported[idx] & ELINK_SUPPORTED_10baseT_Half)
8683                         {
8684                                 sc->link_params.req_line_speed[idx] =
8685                                     ELINK_SPEED_10;
8686                                 sc->link_params.req_duplex[idx] = DUPLEX_HALF;
8687                                 sc->port.advertising[idx] |=
8688                                     (ADVERTISED_10baseT_Half | ADVERTISED_TP);
8689                         } else {
8690                                 PMD_DRV_LOG(ERR, sc,
8691                                             "Invalid NVRAM config link_config=0x%08x "
8692                                             "speed_cap_mask=0x%08x",
8693                                             link_config,
8694                                             sc->
8695                                             link_params.speed_cap_mask[idx]);
8696                                 return;
8697                         }
8698                         break;
8699
8700                 case PORT_FEATURE_LINK_SPEED_100M_FULL:
8701                         if (sc->
8702                             port.supported[idx] & ELINK_SUPPORTED_100baseT_Full)
8703                         {
8704                                 sc->link_params.req_line_speed[idx] =
8705                                     ELINK_SPEED_100;
8706                                 sc->port.advertising[idx] |=
8707                                     (ADVERTISED_100baseT_Full | ADVERTISED_TP);
8708                         } else {
8709                                 PMD_DRV_LOG(ERR, sc,
8710                                             "Invalid NVRAM config link_config=0x%08x "
8711                                             "speed_cap_mask=0x%08x",
8712                                             link_config,
8713                                             sc->
8714                                             link_params.speed_cap_mask[idx]);
8715                                 return;
8716                         }
8717                         break;
8718
8719                 case PORT_FEATURE_LINK_SPEED_100M_HALF:
8720                         if (sc->
8721                             port.supported[idx] & ELINK_SUPPORTED_100baseT_Half)
8722                         {
8723                                 sc->link_params.req_line_speed[idx] =
8724                                     ELINK_SPEED_100;
8725                                 sc->link_params.req_duplex[idx] = DUPLEX_HALF;
8726                                 sc->port.advertising[idx] |=
8727                                     (ADVERTISED_100baseT_Half | ADVERTISED_TP);
8728                         } else {
8729                                 PMD_DRV_LOG(ERR, sc,
8730                                             "Invalid NVRAM config link_config=0x%08x "
8731                                             "speed_cap_mask=0x%08x",
8732                                             link_config,
8733                                             sc->
8734                                             link_params.speed_cap_mask[idx]);
8735                                 return;
8736                         }
8737                         break;
8738
8739                 case PORT_FEATURE_LINK_SPEED_1G:
8740                         if (sc->port.supported[idx] &
8741                             ELINK_SUPPORTED_1000baseT_Full) {
8742                                 sc->link_params.req_line_speed[idx] =
8743                                     ELINK_SPEED_1000;
8744                                 sc->port.advertising[idx] |=
8745                                     (ADVERTISED_1000baseT_Full | ADVERTISED_TP);
8746                         } else {
8747                                 PMD_DRV_LOG(ERR, sc,
8748                                             "Invalid NVRAM config link_config=0x%08x "
8749                                             "speed_cap_mask=0x%08x",
8750                                             link_config,
8751                                             sc->
8752                                             link_params.speed_cap_mask[idx]);
8753                                 return;
8754                         }
8755                         break;
8756
8757                 case PORT_FEATURE_LINK_SPEED_2_5G:
8758                         if (sc->port.supported[idx] &
8759                             ELINK_SUPPORTED_2500baseX_Full) {
8760                                 sc->link_params.req_line_speed[idx] =
8761                                     ELINK_SPEED_2500;
8762                                 sc->port.advertising[idx] |=
8763                                     (ADVERTISED_2500baseX_Full | ADVERTISED_TP);
8764                         } else {
8765                                 PMD_DRV_LOG(ERR, sc,
8766                                             "Invalid NVRAM config link_config=0x%08x "
8767                                             "speed_cap_mask=0x%08x",
8768                                             link_config,
8769                                             sc->
8770                                             link_params.speed_cap_mask[idx]);
8771                                 return;
8772                         }
8773                         break;
8774
8775                 case PORT_FEATURE_LINK_SPEED_10G_CX4:
8776                         if (sc->port.supported[idx] &
8777                             ELINK_SUPPORTED_10000baseT_Full) {
8778                                 sc->link_params.req_line_speed[idx] =
8779                                     ELINK_SPEED_10000;
8780                                 sc->port.advertising[idx] |=
8781                                     (ADVERTISED_10000baseT_Full |
8782                                      ADVERTISED_FIBRE);
8783                         } else {
8784                                 PMD_DRV_LOG(ERR, sc,
8785                                             "Invalid NVRAM config link_config=0x%08x "
8786                                             "speed_cap_mask=0x%08x",
8787                                             link_config,
8788                                             sc->
8789                                             link_params.speed_cap_mask[idx]);
8790                                 return;
8791                         }
8792                         break;
8793
8794                 case PORT_FEATURE_LINK_SPEED_20G:
8795                         sc->link_params.req_line_speed[idx] = ELINK_SPEED_20000;
8796                         break;
8797
8798                 default:
8799                         PMD_DRV_LOG(ERR, sc,
8800                                     "Invalid NVRAM config link_config=0x%08x "
8801                                     "speed_cap_mask=0x%08x", link_config,
8802                                     sc->link_params.speed_cap_mask[idx]);
8803                         sc->link_params.req_line_speed[idx] =
8804                             ELINK_SPEED_AUTO_NEG;
8805                         sc->port.advertising[idx] = sc->port.supported[idx];
8806                         break;
8807                 }
8808
8809                 sc->link_params.req_flow_ctrl[idx] =
8810                     (link_config & PORT_FEATURE_FLOW_CONTROL_MASK);
8811
8812                 if (sc->link_params.req_flow_ctrl[idx] == ELINK_FLOW_CTRL_AUTO) {
8813                         if (!
8814                             (sc->
8815                              port.supported[idx] & ELINK_SUPPORTED_Autoneg)) {
8816                                 sc->link_params.req_flow_ctrl[idx] =
8817                                     ELINK_FLOW_CTRL_NONE;
8818                         } else {
8819                                 bnx2x_set_requested_fc(sc);
8820                         }
8821                 }
8822         }
8823 }
8824
8825 static void bnx2x_get_phy_info(struct bnx2x_softc *sc)
8826 {
8827         uint8_t port = SC_PORT(sc);
8828         uint32_t eee_mode;
8829
8830         PMD_INIT_FUNC_TRACE(sc);
8831
8832         /* shmem data already read in bnx2x_get_shmem_info() */
8833
8834         bnx2x_link_settings_supported(sc, sc->link_params.switch_cfg);
8835         bnx2x_link_settings_requested(sc);
8836
8837         /* configure link feature according to nvram value */
8838         eee_mode =
8839             (((SHMEM_RD(sc, dev_info.port_feature_config[port].eee_power_mode))
8840               & PORT_FEAT_CFG_EEE_POWER_MODE_MASK) >>
8841              PORT_FEAT_CFG_EEE_POWER_MODE_SHIFT);
8842         if (eee_mode != PORT_FEAT_CFG_EEE_POWER_MODE_DISABLED) {
8843                 sc->link_params.eee_mode = (ELINK_EEE_MODE_ADV_LPI |
8844                                             ELINK_EEE_MODE_ENABLE_LPI |
8845                                             ELINK_EEE_MODE_OUTPUT_TIME);
8846         } else {
8847                 sc->link_params.eee_mode = 0;
8848         }
8849
8850         /* get the media type */
8851         bnx2x_media_detect(sc);
8852 }
8853
8854 static void bnx2x_set_modes_bitmap(struct bnx2x_softc *sc)
8855 {
8856         uint32_t flags = MODE_ASIC | MODE_PORT2;
8857
8858         if (CHIP_IS_E2(sc)) {
8859                 flags |= MODE_E2;
8860         } else if (CHIP_IS_E3(sc)) {
8861                 flags |= MODE_E3;
8862                 if (CHIP_REV(sc) == CHIP_REV_Ax) {
8863                         flags |= MODE_E3_A0;
8864                 } else {        /*if (CHIP_REV(sc) == CHIP_REV_Bx) */
8865
8866                         flags |= MODE_E3_B0 | MODE_COS3;
8867                 }
8868         }
8869
8870         if (IS_MF(sc)) {
8871                 flags |= MODE_MF;
8872                 switch (sc->devinfo.mf_info.mf_mode) {
8873                 case MULTI_FUNCTION_SD:
8874                         flags |= MODE_MF_SD;
8875                         break;
8876                 case MULTI_FUNCTION_SI:
8877                         flags |= MODE_MF_SI;
8878                         break;
8879                 case MULTI_FUNCTION_AFEX:
8880                         flags |= MODE_MF_AFEX;
8881                         break;
8882                 }
8883         } else {
8884                 flags |= MODE_SF;
8885         }
8886
8887 #if defined(__LITTLE_ENDIAN)
8888         flags |= MODE_LITTLE_ENDIAN;
8889 #else /* __BIG_ENDIAN */
8890         flags |= MODE_BIG_ENDIAN;
8891 #endif
8892
8893         INIT_MODE_FLAGS(sc) = flags;
8894 }
8895
8896 int bnx2x_alloc_hsi_mem(struct bnx2x_softc *sc)
8897 {
8898         struct bnx2x_fastpath *fp;
8899         char buf[32];
8900         uint32_t i;
8901
8902         if (IS_PF(sc)) {
8903 /************************/
8904 /* DEFAULT STATUS BLOCK */
8905 /************************/
8906
8907                 if (bnx2x_dma_alloc(sc, sizeof(struct host_sp_status_block),
8908                                   &sc->def_sb_dma, "def_sb",
8909                                   RTE_CACHE_LINE_SIZE) != 0) {
8910                         return -1;
8911                 }
8912
8913                 sc->def_sb =
8914                     (struct host_sp_status_block *)sc->def_sb_dma.vaddr;
8915 /***************/
8916 /* EVENT QUEUE */
8917 /***************/
8918
8919                 if (bnx2x_dma_alloc(sc, BNX2X_PAGE_SIZE,
8920                                   &sc->eq_dma, "ev_queue",
8921                                   RTE_CACHE_LINE_SIZE) != 0) {
8922                         sc->def_sb = NULL;
8923                         return -1;
8924                 }
8925
8926                 sc->eq = (union event_ring_elem *)sc->eq_dma.vaddr;
8927
8928 /*************/
8929 /* SLOW PATH */
8930 /*************/
8931
8932                 if (bnx2x_dma_alloc(sc, sizeof(struct bnx2x_slowpath),
8933                                   &sc->sp_dma, "sp",
8934                                   RTE_CACHE_LINE_SIZE) != 0) {
8935                         sc->eq = NULL;
8936                         sc->def_sb = NULL;
8937                         return -1;
8938                 }
8939
8940                 sc->sp = (struct bnx2x_slowpath *)sc->sp_dma.vaddr;
8941
8942 /*******************/
8943 /* SLOW PATH QUEUE */
8944 /*******************/
8945
8946                 if (bnx2x_dma_alloc(sc, BNX2X_PAGE_SIZE,
8947                                   &sc->spq_dma, "sp_queue",
8948                                   RTE_CACHE_LINE_SIZE) != 0) {
8949                         sc->sp = NULL;
8950                         sc->eq = NULL;
8951                         sc->def_sb = NULL;
8952                         return -1;
8953                 }
8954
8955                 sc->spq = (struct eth_spe *)sc->spq_dma.vaddr;
8956
8957 /***************************/
8958 /* FW DECOMPRESSION BUFFER */
8959 /***************************/
8960
8961                 if (bnx2x_dma_alloc(sc, FW_BUF_SIZE, &sc->gz_buf_dma,
8962                                   "fw_buf", RTE_CACHE_LINE_SIZE) != 0) {
8963                         sc->spq = NULL;
8964                         sc->sp = NULL;
8965                         sc->eq = NULL;
8966                         sc->def_sb = NULL;
8967                         return -1;
8968                 }
8969
8970                 sc->gz_buf = (void *)sc->gz_buf_dma.vaddr;
8971         }
8972
8973         /*************/
8974         /* FASTPATHS */
8975         /*************/
8976
8977         /* allocate DMA memory for each fastpath structure */
8978         for (i = 0; i < sc->num_queues; i++) {
8979                 fp = &sc->fp[i];
8980                 fp->sc = sc;
8981                 fp->index = i;
8982
8983 /*******************/
8984 /* FP STATUS BLOCK */
8985 /*******************/
8986
8987                 snprintf(buf, sizeof(buf), "fp_%d_sb", i);
8988                 if (bnx2x_dma_alloc(sc, sizeof(union bnx2x_host_hc_status_block),
8989                                   &fp->sb_dma, buf, RTE_CACHE_LINE_SIZE) != 0) {
8990                         PMD_DRV_LOG(NOTICE, sc, "Failed to alloc %s", buf);
8991                         return -1;
8992                 } else {
8993                         if (CHIP_IS_E2E3(sc)) {
8994                                 fp->status_block.e2_sb =
8995                                     (struct host_hc_status_block_e2 *)
8996                                     fp->sb_dma.vaddr;
8997                         } else {
8998                                 fp->status_block.e1x_sb =
8999                                     (struct host_hc_status_block_e1x *)
9000                                     fp->sb_dma.vaddr;
9001                         }
9002                 }
9003         }
9004
9005         return 0;
9006 }
9007
9008 void bnx2x_free_hsi_mem(struct bnx2x_softc *sc)
9009 {
9010         struct bnx2x_fastpath *fp;
9011         int i;
9012
9013         for (i = 0; i < sc->num_queues; i++) {
9014                 fp = &sc->fp[i];
9015
9016 /*******************/
9017 /* FP STATUS BLOCK */
9018 /*******************/
9019
9020                 memset(&fp->status_block, 0, sizeof(fp->status_block));
9021                 bnx2x_dma_free(&fp->sb_dma);
9022         }
9023
9024         /***************************/
9025         /* FW DECOMPRESSION BUFFER */
9026         /***************************/
9027
9028         bnx2x_dma_free(&sc->gz_buf_dma);
9029         sc->gz_buf = NULL;
9030
9031         /*******************/
9032         /* SLOW PATH QUEUE */
9033         /*******************/
9034
9035         bnx2x_dma_free(&sc->spq_dma);
9036         sc->spq = NULL;
9037
9038         /*************/
9039         /* SLOW PATH */
9040         /*************/
9041
9042         bnx2x_dma_free(&sc->sp_dma);
9043         sc->sp = NULL;
9044
9045         /***************/
9046         /* EVENT QUEUE */
9047         /***************/
9048
9049         bnx2x_dma_free(&sc->eq_dma);
9050         sc->eq = NULL;
9051
9052         /************************/
9053         /* DEFAULT STATUS BLOCK */
9054         /************************/
9055
9056         bnx2x_dma_free(&sc->def_sb_dma);
9057         sc->def_sb = NULL;
9058
9059 }
9060
9061 /*
9062 * Previous driver DMAE transaction may have occurred when pre-boot stage
9063 * ended and boot began. This would invalidate the addresses of the
9064 * transaction, resulting in was-error bit set in the PCI causing all
9065 * hw-to-host PCIe transactions to timeout. If this happened we want to clear
9066 * the interrupt which detected this from the pglueb and the was-done bit
9067 */
9068 static void bnx2x_prev_interrupted_dmae(struct bnx2x_softc *sc)
9069 {
9070         uint32_t val;
9071
9072         if (!CHIP_IS_E1x(sc)) {
9073                 val = REG_RD(sc, PGLUE_B_REG_PGLUE_B_INT_STS);
9074                 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_WAS_ERROR_ATTN) {
9075                         REG_WR(sc, PGLUE_B_REG_WAS_ERROR_PF_7_0_CLR,
9076                                1 << SC_FUNC(sc));
9077                 }
9078         }
9079 }
9080
9081 static int bnx2x_prev_mcp_done(struct bnx2x_softc *sc)
9082 {
9083         uint32_t rc = bnx2x_fw_command(sc, DRV_MSG_CODE_UNLOAD_DONE,
9084                                      DRV_MSG_CODE_UNLOAD_SKIP_LINK_RESET);
9085         if (!rc) {
9086                 PMD_DRV_LOG(NOTICE, sc, "MCP response failure, aborting");
9087                 return -1;
9088         }
9089
9090         return 0;
9091 }
9092
9093 static struct bnx2x_prev_list_node *bnx2x_prev_path_get_entry(struct bnx2x_softc *sc)
9094 {
9095         struct bnx2x_prev_list_node *tmp;
9096
9097         LIST_FOREACH(tmp, &bnx2x_prev_list, node) {
9098                 if ((sc->pcie_bus == tmp->bus) &&
9099                     (sc->pcie_device == tmp->slot) &&
9100                     (SC_PATH(sc) == tmp->path)) {
9101                         return tmp;
9102                 }
9103         }
9104
9105         return NULL;
9106 }
9107
9108 static uint8_t bnx2x_prev_is_path_marked(struct bnx2x_softc *sc)
9109 {
9110         struct bnx2x_prev_list_node *tmp;
9111         int rc = FALSE;
9112
9113         rte_spinlock_lock(&bnx2x_prev_mtx);
9114
9115         tmp = bnx2x_prev_path_get_entry(sc);
9116         if (tmp) {
9117                 if (tmp->aer) {
9118                         PMD_DRV_LOG(DEBUG, sc,
9119                                     "Path %d/%d/%d was marked by AER",
9120                                     sc->pcie_bus, sc->pcie_device, SC_PATH(sc));
9121                 } else {
9122                         rc = TRUE;
9123                         PMD_DRV_LOG(DEBUG, sc,
9124                                     "Path %d/%d/%d was already cleaned from previous drivers",
9125                                     sc->pcie_bus, sc->pcie_device, SC_PATH(sc));
9126                 }
9127         }
9128
9129         rte_spinlock_unlock(&bnx2x_prev_mtx);
9130
9131         return rc;
9132 }
9133
9134 static int bnx2x_prev_mark_path(struct bnx2x_softc *sc, uint8_t after_undi)
9135 {
9136         struct bnx2x_prev_list_node *tmp;
9137
9138         rte_spinlock_lock(&bnx2x_prev_mtx);
9139
9140         /* Check whether the entry for this path already exists */
9141         tmp = bnx2x_prev_path_get_entry(sc);
9142         if (tmp) {
9143                 if (!tmp->aer) {
9144                         PMD_DRV_LOG(DEBUG, sc,
9145                                     "Re-marking AER in path %d/%d/%d",
9146                                     sc->pcie_bus, sc->pcie_device, SC_PATH(sc));
9147                 } else {
9148                         PMD_DRV_LOG(DEBUG, sc,
9149                                     "Removing AER indication from path %d/%d/%d",
9150                                     sc->pcie_bus, sc->pcie_device, SC_PATH(sc));
9151                         tmp->aer = 0;
9152                 }
9153
9154                 rte_spinlock_unlock(&bnx2x_prev_mtx);
9155                 return 0;
9156         }
9157
9158         rte_spinlock_unlock(&bnx2x_prev_mtx);
9159
9160         /* Create an entry for this path and add it */
9161         tmp = rte_malloc("", sizeof(struct bnx2x_prev_list_node),
9162                          RTE_CACHE_LINE_SIZE);
9163         if (!tmp) {
9164                 PMD_DRV_LOG(NOTICE, sc, "Failed to allocate 'bnx2x_prev_list_node'");
9165                 return -1;
9166         }
9167
9168         tmp->bus = sc->pcie_bus;
9169         tmp->slot = sc->pcie_device;
9170         tmp->path = SC_PATH(sc);
9171         tmp->aer = 0;
9172         tmp->undi = after_undi ? (1 << SC_PORT(sc)) : 0;
9173
9174         rte_spinlock_lock(&bnx2x_prev_mtx);
9175
9176         LIST_INSERT_HEAD(&bnx2x_prev_list, tmp, node);
9177
9178         rte_spinlock_unlock(&bnx2x_prev_mtx);
9179
9180         return 0;
9181 }
9182
9183 static int bnx2x_do_flr(struct bnx2x_softc *sc)
9184 {
9185         int i;
9186
9187         /* only E2 and onwards support FLR */
9188         if (CHIP_IS_E1x(sc)) {
9189                 PMD_DRV_LOG(WARNING, sc, "FLR not supported in E1H");
9190                 return -1;
9191         }
9192
9193         /* only bootcode REQ_BC_VER_4_INITIATE_FLR and onwards support flr */
9194         if (sc->devinfo.bc_ver < REQ_BC_VER_4_INITIATE_FLR) {
9195                 PMD_DRV_LOG(WARNING, sc,
9196                             "FLR not supported by BC_VER: 0x%08x",
9197                             sc->devinfo.bc_ver);
9198                 return -1;
9199         }
9200
9201         /* Wait for Transaction Pending bit clean */
9202         for (i = 0; i < 4; i++) {
9203                 if (i) {
9204                         DELAY(((1 << (i - 1)) * 100) * 1000);
9205                 }
9206
9207                 if (!bnx2x_is_pcie_pending(sc)) {
9208                         goto clear;
9209                 }
9210         }
9211
9212         PMD_DRV_LOG(NOTICE, sc, "PCIE transaction is not cleared, "
9213                     "proceeding with reset anyway");
9214
9215 clear:
9216         bnx2x_fw_command(sc, DRV_MSG_CODE_INITIATE_FLR, 0);
9217
9218         return 0;
9219 }
9220
9221 struct bnx2x_mac_vals {
9222         uint32_t xmac_addr;
9223         uint32_t xmac_val;
9224         uint32_t emac_addr;
9225         uint32_t emac_val;
9226         uint32_t umac_addr;
9227         uint32_t umac_val;
9228         uint32_t bmac_addr;
9229         uint32_t bmac_val[2];
9230 };
9231
9232 static void
9233 bnx2x_prev_unload_close_mac(struct bnx2x_softc *sc, struct bnx2x_mac_vals *vals)
9234 {
9235         uint32_t val, base_addr, offset, mask, reset_reg;
9236         uint8_t mac_stopped = FALSE;
9237         uint8_t port = SC_PORT(sc);
9238         uint32_t wb_data[2];
9239
9240         /* reset addresses as they also mark which values were changed */
9241         vals->bmac_addr = 0;
9242         vals->umac_addr = 0;
9243         vals->xmac_addr = 0;
9244         vals->emac_addr = 0;
9245
9246         reset_reg = REG_RD(sc, MISC_REG_RESET_REG_2);
9247
9248         if (!CHIP_IS_E3(sc)) {
9249                 val = REG_RD(sc, NIG_REG_BMAC0_REGS_OUT_EN + port * 4);
9250                 mask = MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port;
9251                 if ((mask & reset_reg) && val) {
9252                         base_addr = SC_PORT(sc) ? NIG_REG_INGRESS_BMAC1_MEM
9253                             : NIG_REG_INGRESS_BMAC0_MEM;
9254                         offset = CHIP_IS_E2(sc) ? BIGMAC2_REGISTER_BMAC_CONTROL
9255                             : BIGMAC_REGISTER_BMAC_CONTROL;
9256
9257                         /*
9258                          * use rd/wr since we cannot use dmae. This is safe
9259                          * since MCP won't access the bus due to the request
9260                          * to unload, and no function on the path can be
9261                          * loaded at this time.
9262                          */
9263                         wb_data[0] = REG_RD(sc, base_addr + offset);
9264                         wb_data[1] = REG_RD(sc, base_addr + offset + 0x4);
9265                         vals->bmac_addr = base_addr + offset;
9266                         vals->bmac_val[0] = wb_data[0];
9267                         vals->bmac_val[1] = wb_data[1];
9268                         wb_data[0] &= ~ELINK_BMAC_CONTROL_RX_ENABLE;
9269                         REG_WR(sc, vals->bmac_addr, wb_data[0]);
9270                         REG_WR(sc, vals->bmac_addr + 0x4, wb_data[1]);
9271                 }
9272
9273                 vals->emac_addr = NIG_REG_NIG_EMAC0_EN + SC_PORT(sc) * 4;
9274                 vals->emac_val = REG_RD(sc, vals->emac_addr);
9275                 REG_WR(sc, vals->emac_addr, 0);
9276                 mac_stopped = TRUE;
9277         } else {
9278                 if (reset_reg & MISC_REGISTERS_RESET_REG_2_XMAC) {
9279                         base_addr = SC_PORT(sc) ? GRCBASE_XMAC1 : GRCBASE_XMAC0;
9280                         val = REG_RD(sc, base_addr + XMAC_REG_PFC_CTRL_HI);
9281                         REG_WR(sc, base_addr + XMAC_REG_PFC_CTRL_HI,
9282                                val & ~(1 << 1));
9283                         REG_WR(sc, base_addr + XMAC_REG_PFC_CTRL_HI,
9284                                val | (1 << 1));
9285                         vals->xmac_addr = base_addr + XMAC_REG_CTRL;
9286                         vals->xmac_val = REG_RD(sc, vals->xmac_addr);
9287                         REG_WR(sc, vals->xmac_addr, 0);
9288                         mac_stopped = TRUE;
9289                 }
9290
9291                 mask = MISC_REGISTERS_RESET_REG_2_UMAC0 << port;
9292                 if (mask & reset_reg) {
9293                         base_addr = SC_PORT(sc) ? GRCBASE_UMAC1 : GRCBASE_UMAC0;
9294                         vals->umac_addr = base_addr + UMAC_REG_COMMAND_CONFIG;
9295                         vals->umac_val = REG_RD(sc, vals->umac_addr);
9296                         REG_WR(sc, vals->umac_addr, 0);
9297                         mac_stopped = TRUE;
9298                 }
9299         }
9300
9301         if (mac_stopped) {
9302                 DELAY(20000);
9303         }
9304 }
9305
9306 #define BNX2X_PREV_UNDI_PROD_ADDR(p)  (BAR_TSTRORM_INTMEM + 0x1508 + ((p) << 4))
9307 #define BNX2X_PREV_UNDI_RCQ(val)      ((val) & 0xffff)
9308 #define BNX2X_PREV_UNDI_BD(val)       ((val) >> 16 & 0xffff)
9309 #define BNX2X_PREV_UNDI_PROD(rcq, bd) ((bd) << 16 | (rcq))
9310
9311 static void
9312 bnx2x_prev_unload_undi_inc(struct bnx2x_softc *sc, uint8_t port, uint8_t inc)
9313 {
9314         uint16_t rcq, bd;
9315         uint32_t tmp_reg = REG_RD(sc, BNX2X_PREV_UNDI_PROD_ADDR(port));
9316
9317         rcq = BNX2X_PREV_UNDI_RCQ(tmp_reg) + inc;
9318         bd = BNX2X_PREV_UNDI_BD(tmp_reg) + inc;
9319
9320         tmp_reg = BNX2X_PREV_UNDI_PROD(rcq, bd);
9321         REG_WR(sc, BNX2X_PREV_UNDI_PROD_ADDR(port), tmp_reg);
9322 }
9323
9324 static int bnx2x_prev_unload_common(struct bnx2x_softc *sc)
9325 {
9326         uint32_t reset_reg, tmp_reg = 0, rc;
9327         uint8_t prev_undi = FALSE;
9328         struct bnx2x_mac_vals mac_vals;
9329         uint32_t timer_count = 1000;
9330         uint32_t prev_brb;
9331
9332         /*
9333          * It is possible a previous function received 'common' answer,
9334          * but hasn't loaded yet, therefore creating a scenario of
9335          * multiple functions receiving 'common' on the same path.
9336          */
9337         memset(&mac_vals, 0, sizeof(mac_vals));
9338
9339         if (bnx2x_prev_is_path_marked(sc)) {
9340                 return bnx2x_prev_mcp_done(sc);
9341         }
9342
9343         reset_reg = REG_RD(sc, MISC_REG_RESET_REG_1);
9344
9345         /* Reset should be performed after BRB is emptied */
9346         if (reset_reg & MISC_REGISTERS_RESET_REG_1_RST_BRB1) {
9347                 /* Close the MAC Rx to prevent BRB from filling up */
9348                 bnx2x_prev_unload_close_mac(sc, &mac_vals);
9349
9350                 /* close LLH filters towards the BRB */
9351                 elink_set_rx_filter(&sc->link_params, 0);
9352
9353                 /*
9354                  * Check if the UNDI driver was previously loaded.
9355                  * UNDI driver initializes CID offset for normal bell to 0x7
9356                  */
9357                 if (reset_reg & MISC_REGISTERS_RESET_REG_1_RST_DORQ) {
9358                         tmp_reg = REG_RD(sc, DORQ_REG_NORM_CID_OFST);
9359                         if (tmp_reg == 0x7) {
9360                                 PMD_DRV_LOG(DEBUG, sc, "UNDI previously loaded");
9361                                 prev_undi = TRUE;
9362                                 /* clear the UNDI indication */
9363                                 REG_WR(sc, DORQ_REG_NORM_CID_OFST, 0);
9364                                 /* clear possible idle check errors */
9365                                 REG_RD(sc, NIG_REG_NIG_INT_STS_CLR_0);
9366                         }
9367                 }
9368
9369                 /* wait until BRB is empty */
9370                 tmp_reg = REG_RD(sc, BRB1_REG_NUM_OF_FULL_BLOCKS);
9371                 while (timer_count) {
9372                         prev_brb = tmp_reg;
9373
9374                         tmp_reg = REG_RD(sc, BRB1_REG_NUM_OF_FULL_BLOCKS);
9375                         if (!tmp_reg) {
9376                                 break;
9377                         }
9378
9379                         PMD_DRV_LOG(DEBUG, sc, "BRB still has 0x%08x", tmp_reg);
9380
9381                         /* reset timer as long as BRB actually gets emptied */
9382                         if (prev_brb > tmp_reg) {
9383                                 timer_count = 1000;
9384                         } else {
9385                                 timer_count--;
9386                         }
9387
9388                         /* If UNDI resides in memory, manually increment it */
9389                         if (prev_undi) {
9390                                 bnx2x_prev_unload_undi_inc(sc, SC_PORT(sc), 1);
9391                         }
9392
9393                         DELAY(10);
9394                 }
9395
9396                 if (!timer_count) {
9397                         PMD_DRV_LOG(NOTICE, sc, "Failed to empty BRB");
9398                 }
9399         }
9400
9401         /* No packets are in the pipeline, path is ready for reset */
9402         bnx2x_reset_common(sc);
9403
9404         if (mac_vals.xmac_addr) {
9405                 REG_WR(sc, mac_vals.xmac_addr, mac_vals.xmac_val);
9406         }
9407         if (mac_vals.umac_addr) {
9408                 REG_WR(sc, mac_vals.umac_addr, mac_vals.umac_val);
9409         }
9410         if (mac_vals.emac_addr) {
9411                 REG_WR(sc, mac_vals.emac_addr, mac_vals.emac_val);
9412         }
9413         if (mac_vals.bmac_addr) {
9414                 REG_WR(sc, mac_vals.bmac_addr, mac_vals.bmac_val[0]);
9415                 REG_WR(sc, mac_vals.bmac_addr + 4, mac_vals.bmac_val[1]);
9416         }
9417
9418         rc = bnx2x_prev_mark_path(sc, prev_undi);
9419         if (rc) {
9420                 bnx2x_prev_mcp_done(sc);
9421                 return rc;
9422         }
9423
9424         return bnx2x_prev_mcp_done(sc);
9425 }
9426
9427 static int bnx2x_prev_unload_uncommon(struct bnx2x_softc *sc)
9428 {
9429         int rc;
9430
9431         /* Test if previous unload process was already finished for this path */
9432         if (bnx2x_prev_is_path_marked(sc)) {
9433                 return bnx2x_prev_mcp_done(sc);
9434         }
9435
9436         /*
9437          * If function has FLR capabilities, and existing FW version matches
9438          * the one required, then FLR will be sufficient to clean any residue
9439          * left by previous driver
9440          */
9441         rc = bnx2x_nic_load_analyze_req(sc, FW_MSG_CODE_DRV_LOAD_FUNCTION);
9442         if (!rc) {
9443                 /* fw version is good */
9444                 rc = bnx2x_do_flr(sc);
9445         }
9446
9447         if (!rc) {
9448                 /* FLR was performed */
9449                 return 0;
9450         }
9451
9452         PMD_DRV_LOG(INFO, sc, "Could not FLR");
9453
9454         /* Close the MCP request, return failure */
9455         rc = bnx2x_prev_mcp_done(sc);
9456         if (!rc) {
9457                 rc = BNX2X_PREV_WAIT_NEEDED;
9458         }
9459
9460         return rc;
9461 }
9462
9463 static int bnx2x_prev_unload(struct bnx2x_softc *sc)
9464 {
9465         int time_counter = 10;
9466         uint32_t fw, hw_lock_reg, hw_lock_val;
9467         uint32_t rc = 0;
9468
9469         PMD_INIT_FUNC_TRACE(sc);
9470
9471         /*
9472          * Clear HW from errors which may have resulted from an interrupted
9473          * DMAE transaction.
9474          */
9475         bnx2x_prev_interrupted_dmae(sc);
9476
9477         /* Release previously held locks */
9478         hw_lock_reg = (SC_FUNC(sc) <= 5) ?
9479                         (MISC_REG_DRIVER_CONTROL_1 + SC_FUNC(sc) * 8) :
9480                         (MISC_REG_DRIVER_CONTROL_7 + (SC_FUNC(sc) - 6) * 8);
9481
9482         hw_lock_val = (REG_RD(sc, hw_lock_reg));
9483         if (hw_lock_val) {
9484                 if (hw_lock_val & HW_LOCK_RESOURCE_NVRAM) {
9485                         PMD_DRV_LOG(DEBUG, sc, "Releasing previously held NVRAM lock\n");
9486                         REG_WR(sc, MCP_REG_MCPR_NVM_SW_ARB,
9487                                (MCPR_NVM_SW_ARB_ARB_REQ_CLR1 << SC_PORT(sc)));
9488                 }
9489                 PMD_DRV_LOG(DEBUG, sc, "Releasing previously held HW lock\n");
9490                 REG_WR(sc, hw_lock_reg, 0xffffffff);
9491         }
9492
9493         if (MCPR_ACCESS_LOCK_LOCK & REG_RD(sc, MCP_REG_MCPR_ACCESS_LOCK)) {
9494                 PMD_DRV_LOG(DEBUG, sc, "Releasing previously held ALR\n");
9495                 REG_WR(sc, MCP_REG_MCPR_ACCESS_LOCK, 0);
9496         }
9497
9498         do {
9499                 /* Lock MCP using an unload request */
9500                 fw = bnx2x_fw_command(sc, DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS, 0);
9501                 if (!fw) {
9502                         PMD_DRV_LOG(NOTICE, sc, "MCP response failure, aborting");
9503                         rc = -1;
9504                         break;
9505                 }
9506
9507                 if (fw == FW_MSG_CODE_DRV_UNLOAD_COMMON) {
9508                         rc = bnx2x_prev_unload_common(sc);
9509                         break;
9510                 }
9511
9512                 /* non-common reply from MCP might require looping */
9513                 rc = bnx2x_prev_unload_uncommon(sc);
9514                 if (rc != BNX2X_PREV_WAIT_NEEDED) {
9515                         break;
9516                 }
9517
9518                 DELAY(20000);
9519         } while (--time_counter);
9520
9521         if (!time_counter || rc) {
9522                 PMD_DRV_LOG(NOTICE, sc, "Failed to unload previous driver!");
9523                 rc = -1;
9524         }
9525
9526         return rc;
9527 }
9528
9529 static void
9530 bnx2x_dcbx_set_state(struct bnx2x_softc *sc, uint8_t dcb_on, uint32_t dcbx_enabled)
9531 {
9532         if (!CHIP_IS_E1x(sc)) {
9533                 sc->dcb_state = dcb_on;
9534                 sc->dcbx_enabled = dcbx_enabled;
9535         } else {
9536                 sc->dcb_state = FALSE;
9537                 sc->dcbx_enabled = BNX2X_DCBX_ENABLED_INVALID;
9538         }
9539         PMD_DRV_LOG(DEBUG, sc,
9540                     "DCB state [%s:%s]",
9541                     dcb_on ? "ON" : "OFF",
9542                     (dcbx_enabled == BNX2X_DCBX_ENABLED_OFF) ? "user-mode" :
9543                     (dcbx_enabled ==
9544                      BNX2X_DCBX_ENABLED_ON_NEG_OFF) ? "on-chip static"
9545                     : (dcbx_enabled ==
9546                        BNX2X_DCBX_ENABLED_ON_NEG_ON) ?
9547                     "on-chip with negotiation" : "invalid");
9548 }
9549
9550 static int bnx2x_set_qm_cid_count(struct bnx2x_softc *sc)
9551 {
9552         int cid_count = BNX2X_L2_MAX_CID(sc);
9553
9554         if (CNIC_SUPPORT(sc)) {
9555                 cid_count += CNIC_CID_MAX;
9556         }
9557
9558         return roundup(cid_count, QM_CID_ROUND);
9559 }
9560
9561 static void bnx2x_init_multi_cos(struct bnx2x_softc *sc)
9562 {
9563         int pri, cos;
9564
9565         uint32_t pri_map = 0;
9566
9567         for (pri = 0; pri < BNX2X_MAX_PRIORITY; pri++) {
9568                 cos = ((pri_map & (0xf << (pri * 4))) >> (pri * 4));
9569                 if (cos < sc->max_cos) {
9570                         sc->prio_to_cos[pri] = cos;
9571                 } else {
9572                         PMD_DRV_LOG(WARNING, sc,
9573                                     "Invalid COS %d for priority %d "
9574                                     "(max COS is %d), setting to 0", cos, pri,
9575                                     (sc->max_cos - 1));
9576                         sc->prio_to_cos[pri] = 0;
9577                 }
9578         }
9579 }
9580
9581 static int bnx2x_pci_get_caps(struct bnx2x_softc *sc)
9582 {
9583         struct {
9584                 uint8_t id;
9585                 uint8_t next;
9586         } pci_cap;
9587         uint16_t status;
9588         struct bnx2x_pci_cap *cap;
9589
9590         cap = sc->pci_caps = rte_zmalloc("caps", sizeof(struct bnx2x_pci_cap),
9591                                          RTE_CACHE_LINE_SIZE);
9592         if (!cap) {
9593                 PMD_DRV_LOG(NOTICE, sc, "Failed to allocate memory");
9594                 return -ENOMEM;
9595         }
9596
9597 #ifndef __FreeBSD__
9598         pci_read(sc, PCI_STATUS, &status, 2);
9599         if (!(status & PCI_STATUS_CAP_LIST)) {
9600 #else
9601         pci_read(sc, PCIR_STATUS, &status, 2);
9602         if (!(status & PCIM_STATUS_CAPPRESENT)) {
9603 #endif
9604                 PMD_DRV_LOG(NOTICE, sc, "PCIe capability reading failed");
9605                 return -1;
9606         }
9607
9608 #ifndef __FreeBSD__
9609         pci_read(sc, PCI_CAPABILITY_LIST, &pci_cap.next, 1);
9610 #else
9611         pci_read(sc, PCIR_CAP_PTR, &pci_cap.next, 1);
9612 #endif
9613         while (pci_cap.next) {
9614                 cap->addr = pci_cap.next & ~3;
9615                 pci_read(sc, pci_cap.next & ~3, &pci_cap, 2);
9616                 if (pci_cap.id == 0xff)
9617                         break;
9618                 cap->id = pci_cap.id;
9619                 cap->type = BNX2X_PCI_CAP;
9620                 cap->next = rte_zmalloc("pci_cap",
9621                                         sizeof(struct bnx2x_pci_cap),
9622                                         RTE_CACHE_LINE_SIZE);
9623                 if (!cap->next) {
9624                         PMD_DRV_LOG(NOTICE, sc, "Failed to allocate memory");
9625                         return -ENOMEM;
9626                 }
9627                 cap = cap->next;
9628         }
9629
9630         return 0;
9631 }
9632
9633 static void bnx2x_init_rte(struct bnx2x_softc *sc)
9634 {
9635         if (IS_VF(sc)) {
9636                 sc->max_tx_queues = min(BNX2X_VF_MAX_QUEUES_PER_VF,
9637                                         sc->igu_sb_cnt);
9638                 sc->max_rx_queues = min(BNX2X_VF_MAX_QUEUES_PER_VF,
9639                                         sc->igu_sb_cnt);
9640         } else {
9641                 sc->max_rx_queues = BNX2X_MAX_RSS_COUNT(sc);
9642                 sc->max_tx_queues = sc->max_rx_queues;
9643         }
9644 }
9645
9646 #define FW_HEADER_LEN 104
9647 #define FW_NAME_57711 "/lib/firmware/bnx2x/bnx2x-e1h-7.2.51.0.fw"
9648 #define FW_NAME_57810 "/lib/firmware/bnx2x/bnx2x-e2-7.2.51.0.fw"
9649
9650 void bnx2x_load_firmware(struct bnx2x_softc *sc)
9651 {
9652         const char *fwname;
9653         int f;
9654         struct stat st;
9655
9656         fwname = sc->devinfo.device_id == CHIP_NUM_57711
9657                 ? FW_NAME_57711 : FW_NAME_57810;
9658         f = open(fwname, O_RDONLY);
9659         if (f < 0) {
9660                 PMD_DRV_LOG(NOTICE, sc, "Can't open firmware file");
9661                 return;
9662         }
9663
9664         if (fstat(f, &st) < 0) {
9665                 PMD_DRV_LOG(NOTICE, sc, "Can't stat firmware file");
9666                 close(f);
9667                 return;
9668         }
9669
9670         sc->firmware = rte_zmalloc("bnx2x_fw", st.st_size, RTE_CACHE_LINE_SIZE);
9671         if (!sc->firmware) {
9672                 PMD_DRV_LOG(NOTICE, sc, "Can't allocate memory for firmware");
9673                 close(f);
9674                 return;
9675         }
9676
9677         if (read(f, sc->firmware, st.st_size) != st.st_size) {
9678                 PMD_DRV_LOG(NOTICE, sc, "Can't read firmware data");
9679                 close(f);
9680                 return;
9681         }
9682         close(f);
9683
9684         sc->fw_len = st.st_size;
9685         if (sc->fw_len < FW_HEADER_LEN) {
9686                 PMD_DRV_LOG(NOTICE, sc,
9687                             "Invalid fw size: %" PRIu64, sc->fw_len);
9688                 return;
9689         }
9690         PMD_DRV_LOG(DEBUG, sc, "fw_len = %" PRIu64, sc->fw_len);
9691 }
9692
9693 static void
9694 bnx2x_data_to_init_ops(uint8_t * data, struct raw_op *dst, uint32_t len)
9695 {
9696         uint32_t *src = (uint32_t *) data;
9697         uint32_t i, j, tmp;
9698
9699         for (i = 0, j = 0; i < len / 8; ++i, j += 2) {
9700                 tmp = rte_be_to_cpu_32(src[j]);
9701                 dst[i].op = (tmp >> 24) & 0xFF;
9702                 dst[i].offset = tmp & 0xFFFFFF;
9703                 dst[i].raw_data = rte_be_to_cpu_32(src[j + 1]);
9704         }
9705 }
9706
9707 static void
9708 bnx2x_data_to_init_offsets(uint8_t * data, uint16_t * dst, uint32_t len)
9709 {
9710         uint16_t *src = (uint16_t *) data;
9711         uint32_t i;
9712
9713         for (i = 0; i < len / 2; ++i)
9714                 dst[i] = rte_be_to_cpu_16(src[i]);
9715 }
9716
9717 static void bnx2x_data_to_init_data(uint8_t * data, uint32_t * dst, uint32_t len)
9718 {
9719         uint32_t *src = (uint32_t *) data;
9720         uint32_t i;
9721
9722         for (i = 0; i < len / 4; ++i)
9723                 dst[i] = rte_be_to_cpu_32(src[i]);
9724 }
9725
9726 static void bnx2x_data_to_iro_array(uint8_t * data, struct iro *dst, uint32_t len)
9727 {
9728         uint32_t *src = (uint32_t *) data;
9729         uint32_t i, j, tmp;
9730
9731         for (i = 0, j = 0; i < len / sizeof(struct iro); ++i, ++j) {
9732                 dst[i].base = rte_be_to_cpu_32(src[j++]);
9733                 tmp = rte_be_to_cpu_32(src[j]);
9734                 dst[i].m1 = (tmp >> 16) & 0xFFFF;
9735                 dst[i].m2 = tmp & 0xFFFF;
9736                 ++j;
9737                 tmp = rte_be_to_cpu_32(src[j]);
9738                 dst[i].m3 = (tmp >> 16) & 0xFFFF;
9739                 dst[i].size = tmp & 0xFFFF;
9740         }
9741 }
9742
9743 /*
9744 * Device attach function.
9745 *
9746 * Allocates device resources, performs secondary chip identification, and
9747 * initializes driver instance variables. This function is called from driver
9748 * load after a successful probe.
9749 *
9750 * Returns:
9751 *   0 = Success, >0 = Failure
9752 */
9753 int bnx2x_attach(struct bnx2x_softc *sc)
9754 {
9755         int rc;
9756
9757         PMD_DRV_LOG(DEBUG, sc, "Starting attach...");
9758
9759         rc = bnx2x_pci_get_caps(sc);
9760         if (rc) {
9761                 PMD_DRV_LOG(NOTICE, sc, "PCIe caps reading was failed");
9762                 return rc;
9763         }
9764
9765         sc->state = BNX2X_STATE_CLOSED;
9766
9767         pci_write_long(sc, PCICFG_GRC_ADDRESS, PCICFG_VENDOR_ID_OFFSET);
9768
9769         sc->igu_base_addr = IS_VF(sc) ? PXP_VF_ADDR_IGU_START : BAR_IGU_INTMEM;
9770
9771         /* get PCI capabilites */
9772         bnx2x_probe_pci_caps(sc);
9773
9774         if (sc->devinfo.pcie_msix_cap_reg != 0) {
9775                 uint32_t val;
9776                 pci_read(sc,
9777                          (sc->devinfo.pcie_msix_cap_reg + PCIR_MSIX_CTRL), &val,
9778                          2);
9779                 sc->igu_sb_cnt = (val & PCIM_MSIXCTRL_TABLE_SIZE) + 1;
9780         } else {
9781                 sc->igu_sb_cnt = 1;
9782         }
9783
9784         /* Init RTE stuff */
9785         bnx2x_init_rte(sc);
9786
9787         if (IS_PF(sc)) {
9788                 /* Enable internal target-read (in case we are probed after PF
9789                  * FLR). Must be done prior to any BAR read access. Only for
9790                  * 57712 and up
9791                  */
9792                 if (!CHIP_IS_E1x(sc)) {
9793                         REG_WR(sc, PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_READ,
9794                                1);
9795                         DELAY(200000);
9796                 }
9797
9798                 /* get device info and set params */
9799                 if (bnx2x_get_device_info(sc) != 0) {
9800                         PMD_DRV_LOG(NOTICE, sc, "getting device info");
9801                         return -ENXIO;
9802                 }
9803
9804 /* get phy settings from shmem and 'and' against admin settings */
9805                 bnx2x_get_phy_info(sc);
9806         } else {
9807                 /* Left mac of VF unfilled, PF should set it for VF */
9808                 memset(sc->link_params.mac_addr, 0, RTE_ETHER_ADDR_LEN);
9809         }
9810
9811         sc->wol = 0;
9812
9813         /* set the default MTU (changed via ifconfig) */
9814         sc->mtu = RTE_ETHER_MTU;
9815
9816         bnx2x_set_modes_bitmap(sc);
9817
9818         /* need to reset chip if UNDI was active */
9819         if (IS_PF(sc) && !BNX2X_NOMCP(sc)) {
9820 /* init fw_seq */
9821                 sc->fw_seq =
9822                     (SHMEM_RD(sc, func_mb[SC_FW_MB_IDX(sc)].drv_mb_header) &
9823                      DRV_MSG_SEQ_NUMBER_MASK);
9824                 PMD_DRV_LOG(DEBUG, sc, "prev unload fw_seq 0x%04x",
9825                             sc->fw_seq);
9826                 bnx2x_prev_unload(sc);
9827         }
9828
9829         bnx2x_dcbx_set_state(sc, FALSE, BNX2X_DCBX_ENABLED_OFF);
9830
9831         /* calculate qm_cid_count */
9832         sc->qm_cid_count = bnx2x_set_qm_cid_count(sc);
9833
9834         sc->max_cos = 1;
9835         bnx2x_init_multi_cos(sc);
9836
9837         return 0;
9838 }
9839
9840 static void
9841 bnx2x_igu_ack_sb(struct bnx2x_softc *sc, uint8_t igu_sb_id, uint8_t segment,
9842                uint16_t index, uint8_t op, uint8_t update)
9843 {
9844         uint32_t igu_addr = sc->igu_base_addr;
9845         igu_addr += (IGU_CMD_INT_ACK_BASE + igu_sb_id) * 8;
9846         bnx2x_igu_ack_sb_gen(sc, segment, index, op, update, igu_addr);
9847 }
9848
9849 static void
9850 bnx2x_ack_sb(struct bnx2x_softc *sc, uint8_t igu_sb_id, uint8_t storm,
9851            uint16_t index, uint8_t op, uint8_t update)
9852 {
9853         if (unlikely(sc->devinfo.int_block == INT_BLOCK_HC))
9854                 bnx2x_hc_ack_sb(sc, igu_sb_id, storm, index, op, update);
9855         else {
9856                 uint8_t segment;
9857                 if (CHIP_INT_MODE_IS_BC(sc)) {
9858                         segment = storm;
9859                 } else if (igu_sb_id != sc->igu_dsb_id) {
9860                         segment = IGU_SEG_ACCESS_DEF;
9861                 } else if (storm == ATTENTION_ID) {
9862                         segment = IGU_SEG_ACCESS_ATTN;
9863                 } else {
9864                         segment = IGU_SEG_ACCESS_DEF;
9865                 }
9866                 bnx2x_igu_ack_sb(sc, igu_sb_id, segment, index, op, update);
9867         }
9868 }
9869
9870 static void
9871 bnx2x_igu_clear_sb_gen(struct bnx2x_softc *sc, uint8_t func, uint8_t idu_sb_id,
9872                      uint8_t is_pf)
9873 {
9874         uint32_t data, ctl, cnt = 100;
9875         uint32_t igu_addr_data = IGU_REG_COMMAND_REG_32LSB_DATA;
9876         uint32_t igu_addr_ctl = IGU_REG_COMMAND_REG_CTRL;
9877         uint32_t igu_addr_ack = IGU_REG_CSTORM_TYPE_0_SB_CLEANUP +
9878             (idu_sb_id / 32) * 4;
9879         uint32_t sb_bit = 1 << (idu_sb_id % 32);
9880         uint32_t func_encode = func |
9881             (is_pf ? 1 : 0) << IGU_FID_ENCODE_IS_PF_SHIFT;
9882         uint32_t addr_encode = IGU_CMD_E2_PROD_UPD_BASE + idu_sb_id;
9883
9884         /* Not supported in BC mode */
9885         if (CHIP_INT_MODE_IS_BC(sc)) {
9886                 return;
9887         }
9888
9889         data = ((IGU_USE_REGISTER_cstorm_type_0_sb_cleanup <<
9890                  IGU_REGULAR_CLEANUP_TYPE_SHIFT) |
9891                 IGU_REGULAR_CLEANUP_SET | IGU_REGULAR_BCLEANUP);
9892
9893         ctl = ((addr_encode << IGU_CTRL_REG_ADDRESS_SHIFT) |
9894                (func_encode << IGU_CTRL_REG_FID_SHIFT) |
9895                (IGU_CTRL_CMD_TYPE_WR << IGU_CTRL_REG_TYPE_SHIFT));
9896
9897         REG_WR(sc, igu_addr_data, data);
9898
9899         mb();
9900
9901         PMD_DRV_LOG(DEBUG, sc, "write 0x%08x to IGU(via GRC) addr 0x%x",
9902                     ctl, igu_addr_ctl);
9903         REG_WR(sc, igu_addr_ctl, ctl);
9904
9905         mb();
9906
9907         /* wait for clean up to finish */
9908         while (!(REG_RD(sc, igu_addr_ack) & sb_bit) && --cnt) {
9909                 DELAY(20000);
9910         }
9911
9912         if (!(REG_RD(sc, igu_addr_ack) & sb_bit)) {
9913                 PMD_DRV_LOG(DEBUG, sc,
9914                             "Unable to finish IGU cleanup: "
9915                             "idu_sb_id %d offset %d bit %d (cnt %d)",
9916                             idu_sb_id, idu_sb_id / 32, idu_sb_id % 32, cnt);
9917         }
9918 }
9919
9920 static void bnx2x_igu_clear_sb(struct bnx2x_softc *sc, uint8_t idu_sb_id)
9921 {
9922         bnx2x_igu_clear_sb_gen(sc, SC_FUNC(sc), idu_sb_id, TRUE /*PF*/);
9923 }
9924
9925 /*******************/
9926 /* ECORE CALLBACKS */
9927 /*******************/
9928
9929 static void bnx2x_reset_common(struct bnx2x_softc *sc)
9930 {
9931         uint32_t val = 0x1400;
9932
9933         PMD_INIT_FUNC_TRACE(sc);
9934
9935         /* reset_common */
9936         REG_WR(sc, (GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR),
9937                0xd3ffff7f);
9938
9939         if (CHIP_IS_E3(sc)) {
9940                 val |= MISC_REGISTERS_RESET_REG_2_MSTAT0;
9941                 val |= MISC_REGISTERS_RESET_REG_2_MSTAT1;
9942         }
9943
9944         REG_WR(sc, (GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR), val);
9945 }
9946
9947 static void bnx2x_common_init_phy(struct bnx2x_softc *sc)
9948 {
9949         uint32_t shmem_base[2];
9950         uint32_t shmem2_base[2];
9951
9952         /* Avoid common init in case MFW supports LFA */
9953         if (SHMEM2_RD(sc, size) >
9954             (uint32_t) offsetof(struct shmem2_region,
9955                                 lfa_host_addr[SC_PORT(sc)])) {
9956                 return;
9957         }
9958
9959         shmem_base[0] = sc->devinfo.shmem_base;
9960         shmem2_base[0] = sc->devinfo.shmem2_base;
9961
9962         if (!CHIP_IS_E1x(sc)) {
9963                 shmem_base[1] = SHMEM2_RD(sc, other_shmem_base_addr);
9964                 shmem2_base[1] = SHMEM2_RD(sc, other_shmem2_base_addr);
9965         }
9966
9967         bnx2x_acquire_phy_lock(sc);
9968         elink_common_init_phy(sc, shmem_base, shmem2_base,
9969                               sc->devinfo.chip_id, 0);
9970         bnx2x_release_phy_lock(sc);
9971 }
9972
9973 static void bnx2x_pf_disable(struct bnx2x_softc *sc)
9974 {
9975         uint32_t val = REG_RD(sc, IGU_REG_PF_CONFIGURATION);
9976
9977         val &= ~IGU_PF_CONF_FUNC_EN;
9978
9979         REG_WR(sc, IGU_REG_PF_CONFIGURATION, val);
9980         REG_WR(sc, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 0);
9981         REG_WR(sc, CFC_REG_WEAK_ENABLE_PF, 0);
9982 }
9983
9984 static void bnx2x_init_pxp(struct bnx2x_softc *sc)
9985 {
9986         uint16_t devctl;
9987         int r_order, w_order;
9988
9989         devctl = bnx2x_pcie_capability_read(sc, PCIR_EXPRESS_DEVICE_CTL);
9990
9991         w_order = ((devctl & PCIM_EXP_CTL_MAX_PAYLOAD) >> 5);
9992         r_order = ((devctl & PCIM_EXP_CTL_MAX_READ_REQUEST) >> 12);
9993
9994         ecore_init_pxp_arb(sc, r_order, w_order);
9995 }
9996
9997 static uint32_t bnx2x_get_pretend_reg(struct bnx2x_softc *sc)
9998 {
9999         uint32_t base = PXP2_REG_PGL_PRETEND_FUNC_F0;
10000         uint32_t stride = (PXP2_REG_PGL_PRETEND_FUNC_F1 - base);
10001         return base + (SC_ABS_FUNC(sc)) * stride;
10002 }
10003
10004 /*
10005  * Called only on E1H or E2.
10006  * When pretending to be PF, the pretend value is the function number 0..7.
10007  * When pretending to be VF, the pretend val is the PF-num:VF-valid:ABS-VFID
10008  * combination.
10009  */
10010 static int bnx2x_pretend_func(struct bnx2x_softc *sc, uint16_t pretend_func_val)
10011 {
10012         uint32_t pretend_reg;
10013
10014         if (CHIP_IS_E1H(sc) && (pretend_func_val > E1H_FUNC_MAX))
10015                 return -1;
10016
10017         /* get my own pretend register */
10018         pretend_reg = bnx2x_get_pretend_reg(sc);
10019         REG_WR(sc, pretend_reg, pretend_func_val);
10020         REG_RD(sc, pretend_reg);
10021         return 0;
10022 }
10023
10024 static void bnx2x_setup_fan_failure_detection(struct bnx2x_softc *sc)
10025 {
10026         int is_required;
10027         uint32_t val;
10028         int port;
10029
10030         is_required = 0;
10031         val = (SHMEM_RD(sc, dev_info.shared_hw_config.config2) &
10032                SHARED_HW_CFG_FAN_FAILURE_MASK);
10033
10034         if (val == SHARED_HW_CFG_FAN_FAILURE_ENABLED) {
10035                 is_required = 1;
10036         }
10037         /*
10038          * The fan failure mechanism is usually related to the PHY type since
10039          * the power consumption of the board is affected by the PHY. Currently,
10040          * fan is required for most designs with SFX7101, BNX2X8727 and BNX2X8481.
10041          */
10042         else if (val == SHARED_HW_CFG_FAN_FAILURE_PHY_TYPE) {
10043                 for (port = PORT_0; port < PORT_MAX; port++) {
10044                         is_required |= elink_fan_failure_det_req(sc,
10045                                                                  sc->
10046                                                                  devinfo.shmem_base,
10047                                                                  sc->
10048                                                                  devinfo.shmem2_base,
10049                                                                  port);
10050                 }
10051         }
10052
10053         if (is_required == 0) {
10054                 return;
10055         }
10056
10057         /* Fan failure is indicated by SPIO 5 */
10058         bnx2x_set_spio(sc, MISC_SPIO_SPIO5, MISC_SPIO_INPUT_HI_Z);
10059
10060         /* set to active low mode */
10061         val = REG_RD(sc, MISC_REG_SPIO_INT);
10062         val |= (MISC_SPIO_SPIO5 << MISC_SPIO_INT_OLD_SET_POS);
10063         REG_WR(sc, MISC_REG_SPIO_INT, val);
10064
10065         /* enable interrupt to signal the IGU */
10066         val = REG_RD(sc, MISC_REG_SPIO_EVENT_EN);
10067         val |= MISC_SPIO_SPIO5;
10068         REG_WR(sc, MISC_REG_SPIO_EVENT_EN, val);
10069 }
10070
10071 static void bnx2x_enable_blocks_attention(struct bnx2x_softc *sc)
10072 {
10073         uint32_t val;
10074
10075         REG_WR(sc, PXP_REG_PXP_INT_MASK_0, 0);
10076         if (!CHIP_IS_E1x(sc)) {
10077                 REG_WR(sc, PXP_REG_PXP_INT_MASK_1, 0x40);
10078         } else {
10079                 REG_WR(sc, PXP_REG_PXP_INT_MASK_1, 0);
10080         }
10081         REG_WR(sc, DORQ_REG_DORQ_INT_MASK, 0);
10082         REG_WR(sc, CFC_REG_CFC_INT_MASK, 0);
10083         /*
10084          * mask read length error interrupts in brb for parser
10085          * (parsing unit and 'checksum and crc' unit)
10086          * these errors are legal (PU reads fixed length and CAC can cause
10087          * read length error on truncated packets)
10088          */
10089         REG_WR(sc, BRB1_REG_BRB1_INT_MASK, 0xFC00);
10090         REG_WR(sc, QM_REG_QM_INT_MASK, 0);
10091         REG_WR(sc, TM_REG_TM_INT_MASK, 0);
10092         REG_WR(sc, XSDM_REG_XSDM_INT_MASK_0, 0);
10093         REG_WR(sc, XSDM_REG_XSDM_INT_MASK_1, 0);
10094         REG_WR(sc, XCM_REG_XCM_INT_MASK, 0);
10095         /*      REG_WR(sc, XSEM_REG_XSEM_INT_MASK_0, 0); */
10096         /*      REG_WR(sc, XSEM_REG_XSEM_INT_MASK_1, 0); */
10097         REG_WR(sc, USDM_REG_USDM_INT_MASK_0, 0);
10098         REG_WR(sc, USDM_REG_USDM_INT_MASK_1, 0);
10099         REG_WR(sc, UCM_REG_UCM_INT_MASK, 0);
10100         /*      REG_WR(sc, USEM_REG_USEM_INT_MASK_0, 0); */
10101         /*      REG_WR(sc, USEM_REG_USEM_INT_MASK_1, 0); */
10102         REG_WR(sc, GRCBASE_UPB + PB_REG_PB_INT_MASK, 0);
10103         REG_WR(sc, CSDM_REG_CSDM_INT_MASK_0, 0);
10104         REG_WR(sc, CSDM_REG_CSDM_INT_MASK_1, 0);
10105         REG_WR(sc, CCM_REG_CCM_INT_MASK, 0);
10106         /*      REG_WR(sc, CSEM_REG_CSEM_INT_MASK_0, 0); */
10107         /*      REG_WR(sc, CSEM_REG_CSEM_INT_MASK_1, 0); */
10108
10109         val = (PXP2_PXP2_INT_MASK_0_REG_PGL_CPL_AFT |
10110                PXP2_PXP2_INT_MASK_0_REG_PGL_CPL_OF |
10111                PXP2_PXP2_INT_MASK_0_REG_PGL_PCIE_ATTN);
10112         if (!CHIP_IS_E1x(sc)) {
10113                 val |= (PXP2_PXP2_INT_MASK_0_REG_PGL_READ_BLOCKED |
10114                         PXP2_PXP2_INT_MASK_0_REG_PGL_WRITE_BLOCKED);
10115         }
10116         REG_WR(sc, PXP2_REG_PXP2_INT_MASK_0, val);
10117
10118         REG_WR(sc, TSDM_REG_TSDM_INT_MASK_0, 0);
10119         REG_WR(sc, TSDM_REG_TSDM_INT_MASK_1, 0);
10120         REG_WR(sc, TCM_REG_TCM_INT_MASK, 0);
10121         /*      REG_WR(sc, TSEM_REG_TSEM_INT_MASK_0, 0); */
10122
10123         if (!CHIP_IS_E1x(sc)) {
10124 /* enable VFC attentions: bits 11 and 12, bits 31:13 reserved */
10125                 REG_WR(sc, TSEM_REG_TSEM_INT_MASK_1, 0x07ff);
10126         }
10127
10128         REG_WR(sc, CDU_REG_CDU_INT_MASK, 0);
10129         REG_WR(sc, DMAE_REG_DMAE_INT_MASK, 0);
10130         /*      REG_WR(sc, MISC_REG_MISC_INT_MASK, 0); */
10131         REG_WR(sc, PBF_REG_PBF_INT_MASK, 0x18); /* bit 3,4 masked */
10132 }
10133
10134 /**
10135  * bnx2x_init_hw_common - initialize the HW at the COMMON phase.
10136  *
10137  * @sc:     driver handle
10138  */
10139 static int bnx2x_init_hw_common(struct bnx2x_softc *sc)
10140 {
10141         uint8_t abs_func_id;
10142         uint32_t val;
10143
10144         PMD_DRV_LOG(DEBUG, sc,
10145                     "starting common init for func %d", SC_ABS_FUNC(sc));
10146
10147         /*
10148          * take the RESET lock to protect undi_unload flow from accessing
10149          * registers while we are resetting the chip
10150          */
10151         bnx2x_acquire_hw_lock(sc, HW_LOCK_RESOURCE_RESET);
10152
10153         bnx2x_reset_common(sc);
10154
10155         REG_WR(sc, (GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET), 0xffffffff);
10156
10157         val = 0xfffc;
10158         if (CHIP_IS_E3(sc)) {
10159                 val |= MISC_REGISTERS_RESET_REG_2_MSTAT0;
10160                 val |= MISC_REGISTERS_RESET_REG_2_MSTAT1;
10161         }
10162
10163         REG_WR(sc, (GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET), val);
10164
10165         bnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_RESET);
10166
10167         ecore_init_block(sc, BLOCK_MISC, PHASE_COMMON);
10168
10169         if (!CHIP_IS_E1x(sc)) {
10170 /*
10171  * 4-port mode or 2-port mode we need to turn off master-enable for
10172  * everyone. After that we turn it back on for self. So, we disregard
10173  * multi-function, and always disable all functions on the given path,
10174  * this means 0,2,4,6 for path 0 and 1,3,5,7 for path 1
10175  */
10176                 for (abs_func_id = SC_PATH(sc);
10177                      abs_func_id < (E2_FUNC_MAX * 2); abs_func_id += 2) {
10178                         if (abs_func_id == SC_ABS_FUNC(sc)) {
10179                                 REG_WR(sc,
10180                                        PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER,
10181                                        1);
10182                                 continue;
10183                         }
10184
10185                         bnx2x_pretend_func(sc, abs_func_id);
10186
10187                         /* clear pf enable */
10188                         bnx2x_pf_disable(sc);
10189
10190                         bnx2x_pretend_func(sc, SC_ABS_FUNC(sc));
10191                 }
10192         }
10193
10194         ecore_init_block(sc, BLOCK_PXP, PHASE_COMMON);
10195
10196         ecore_init_block(sc, BLOCK_PXP2, PHASE_COMMON);
10197         bnx2x_init_pxp(sc);
10198
10199 #ifdef __BIG_ENDIAN
10200         REG_WR(sc, PXP2_REG_RQ_QM_ENDIAN_M, 1);
10201         REG_WR(sc, PXP2_REG_RQ_TM_ENDIAN_M, 1);
10202         REG_WR(sc, PXP2_REG_RQ_SRC_ENDIAN_M, 1);
10203         REG_WR(sc, PXP2_REG_RQ_CDU_ENDIAN_M, 1);
10204         REG_WR(sc, PXP2_REG_RQ_DBG_ENDIAN_M, 1);
10205         /* make sure this value is 0 */
10206         REG_WR(sc, PXP2_REG_RQ_HC_ENDIAN_M, 0);
10207
10208         //REG_WR(sc, PXP2_REG_RD_PBF_SWAP_MODE, 1);
10209         REG_WR(sc, PXP2_REG_RD_QM_SWAP_MODE, 1);
10210         REG_WR(sc, PXP2_REG_RD_TM_SWAP_MODE, 1);
10211         REG_WR(sc, PXP2_REG_RD_SRC_SWAP_MODE, 1);
10212         REG_WR(sc, PXP2_REG_RD_CDURD_SWAP_MODE, 1);
10213 #endif
10214
10215         ecore_ilt_init_page_size(sc, INITOP_SET);
10216
10217         if (CHIP_REV_IS_FPGA(sc) && CHIP_IS_E1H(sc)) {
10218                 REG_WR(sc, PXP2_REG_PGL_TAGS_LIMIT, 0x1);
10219         }
10220
10221         /* let the HW do it's magic... */
10222         DELAY(100000);
10223
10224         /* finish PXP init */
10225
10226         val = REG_RD(sc, PXP2_REG_RQ_CFG_DONE);
10227         if (val != 1) {
10228                 PMD_DRV_LOG(NOTICE, sc, "PXP2 CFG failed");
10229                 return -1;
10230         }
10231         val = REG_RD(sc, PXP2_REG_RD_INIT_DONE);
10232         if (val != 1) {
10233                 PMD_DRV_LOG(NOTICE, sc, "PXP2 RD_INIT failed");
10234                 return -1;
10235         }
10236
10237         /*
10238          * Timer bug workaround for E2 only. We need to set the entire ILT to have
10239          * entries with value "0" and valid bit on. This needs to be done by the
10240          * first PF that is loaded in a path (i.e. common phase)
10241          */
10242         if (!CHIP_IS_E1x(sc)) {
10243 /*
10244  * In E2 there is a bug in the timers block that can cause function 6 / 7
10245  * (i.e. vnic3) to start even if it is marked as "scan-off".
10246  * This occurs when a different function (func2,3) is being marked
10247  * as "scan-off". Real-life scenario for example: if a driver is being
10248  * load-unloaded while func6,7 are down. This will cause the timer to access
10249  * the ilt, translate to a logical address and send a request to read/write.
10250  * Since the ilt for the function that is down is not valid, this will cause
10251  * a translation error which is unrecoverable.
10252  * The Workaround is intended to make sure that when this happens nothing
10253  * fatal will occur. The workaround:
10254  *  1.  First PF driver which loads on a path will:
10255  *      a.  After taking the chip out of reset, by using pretend,
10256  *          it will write "0" to the following registers of
10257  *          the other vnics.
10258  *          REG_WR(pdev, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 0);
10259  *          REG_WR(pdev, CFC_REG_WEAK_ENABLE_PF,0);
10260  *          REG_WR(pdev, CFC_REG_STRONG_ENABLE_PF,0);
10261  *          And for itself it will write '1' to
10262  *          PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER to enable
10263  *          dmae-operations (writing to pram for example.)
10264  *          note: can be done for only function 6,7 but cleaner this
10265  *            way.
10266  *      b.  Write zero+valid to the entire ILT.
10267  *      c.  Init the first_timers_ilt_entry, last_timers_ilt_entry of
10268  *          VNIC3 (of that port). The range allocated will be the
10269  *          entire ILT. This is needed to prevent  ILT range error.
10270  *  2.  Any PF driver load flow:
10271  *      a.  ILT update with the physical addresses of the allocated
10272  *          logical pages.
10273  *      b.  Wait 20msec. - note that this timeout is needed to make
10274  *          sure there are no requests in one of the PXP internal
10275  *          queues with "old" ILT addresses.
10276  *      c.  PF enable in the PGLC.
10277  *      d.  Clear the was_error of the PF in the PGLC. (could have
10278  *          occurred while driver was down)
10279  *      e.  PF enable in the CFC (WEAK + STRONG)
10280  *      f.  Timers scan enable
10281  *  3.  PF driver unload flow:
10282  *      a.  Clear the Timers scan_en.
10283  *      b.  Polling for scan_on=0 for that PF.
10284  *      c.  Clear the PF enable bit in the PXP.
10285  *      d.  Clear the PF enable in the CFC (WEAK + STRONG)
10286  *      e.  Write zero+valid to all ILT entries (The valid bit must
10287  *          stay set)
10288  *      f.  If this is VNIC 3 of a port then also init
10289  *          first_timers_ilt_entry to zero and last_timers_ilt_entry
10290  *          to the last enrty in the ILT.
10291  *
10292  *      Notes:
10293  *      Currently the PF error in the PGLC is non recoverable.
10294  *      In the future the there will be a recovery routine for this error.
10295  *      Currently attention is masked.
10296  *      Having an MCP lock on the load/unload process does not guarantee that
10297  *      there is no Timer disable during Func6/7 enable. This is because the
10298  *      Timers scan is currently being cleared by the MCP on FLR.
10299  *      Step 2.d can be done only for PF6/7 and the driver can also check if
10300  *      there is error before clearing it. But the flow above is simpler and
10301  *      more general.
10302  *      All ILT entries are written by zero+valid and not just PF6/7
10303  *      ILT entries since in the future the ILT entries allocation for
10304  *      PF-s might be dynamic.
10305  */
10306                 struct ilt_client_info ilt_cli;
10307                 struct ecore_ilt ilt;
10308
10309                 memset(&ilt_cli, 0, sizeof(struct ilt_client_info));
10310                 memset(&ilt, 0, sizeof(struct ecore_ilt));
10311
10312 /* initialize dummy TM client */
10313                 ilt_cli.start = 0;
10314                 ilt_cli.end = ILT_NUM_PAGE_ENTRIES - 1;
10315                 ilt_cli.client_num = ILT_CLIENT_TM;
10316
10317 /*
10318  * Step 1: set zeroes to all ilt page entries with valid bit on
10319  * Step 2: set the timers first/last ilt entry to point
10320  * to the entire range to prevent ILT range error for 3rd/4th
10321  * vnic (this code assumes existence of the vnic)
10322  *
10323  * both steps performed by call to ecore_ilt_client_init_op()
10324  * with dummy TM client
10325  *
10326  * we must use pretend since PXP2_REG_RQ_##blk##_FIRST_ILT
10327  * and his brother are split registers
10328  */
10329
10330                 bnx2x_pretend_func(sc, (SC_PATH(sc) + 6));
10331                 ecore_ilt_client_init_op_ilt(sc, &ilt, &ilt_cli, INITOP_CLEAR);
10332                 bnx2x_pretend_func(sc, SC_ABS_FUNC(sc));
10333
10334                 REG_WR(sc, PXP2_REG_RQ_DRAM_ALIGN, BNX2X_PXP_DRAM_ALIGN);
10335                 REG_WR(sc, PXP2_REG_RQ_DRAM_ALIGN_RD, BNX2X_PXP_DRAM_ALIGN);
10336                 REG_WR(sc, PXP2_REG_RQ_DRAM_ALIGN_SEL, 1);
10337         }
10338
10339         REG_WR(sc, PXP2_REG_RQ_DISABLE_INPUTS, 0);
10340         REG_WR(sc, PXP2_REG_RD_DISABLE_INPUTS, 0);
10341
10342         if (!CHIP_IS_E1x(sc)) {
10343                 int factor = 0;
10344
10345                 ecore_init_block(sc, BLOCK_PGLUE_B, PHASE_COMMON);
10346                 ecore_init_block(sc, BLOCK_ATC, PHASE_COMMON);
10347
10348 /* let the HW do it's magic... */
10349                 do {
10350                         DELAY(200000);
10351                         val = REG_RD(sc, ATC_REG_ATC_INIT_DONE);
10352                 } while (factor-- && (val != 1));
10353
10354                 if (val != 1) {
10355                         PMD_DRV_LOG(NOTICE, sc, "ATC_INIT failed");
10356                         return -1;
10357                 }
10358         }
10359
10360         ecore_init_block(sc, BLOCK_DMAE, PHASE_COMMON);
10361
10362         /* clean the DMAE memory */
10363         sc->dmae_ready = 1;
10364         ecore_init_fill(sc, TSEM_REG_PRAM, 0, 8);
10365
10366         ecore_init_block(sc, BLOCK_TCM, PHASE_COMMON);
10367
10368         ecore_init_block(sc, BLOCK_UCM, PHASE_COMMON);
10369
10370         ecore_init_block(sc, BLOCK_CCM, PHASE_COMMON);
10371
10372         ecore_init_block(sc, BLOCK_XCM, PHASE_COMMON);
10373
10374         bnx2x_read_dmae(sc, XSEM_REG_PASSIVE_BUFFER, 3);
10375         bnx2x_read_dmae(sc, CSEM_REG_PASSIVE_BUFFER, 3);
10376         bnx2x_read_dmae(sc, TSEM_REG_PASSIVE_BUFFER, 3);
10377         bnx2x_read_dmae(sc, USEM_REG_PASSIVE_BUFFER, 3);
10378
10379         ecore_init_block(sc, BLOCK_QM, PHASE_COMMON);
10380
10381         /* QM queues pointers table */
10382         ecore_qm_init_ptr_table(sc, sc->qm_cid_count, INITOP_SET);
10383
10384         /* soft reset pulse */
10385         REG_WR(sc, QM_REG_SOFT_RESET, 1);
10386         REG_WR(sc, QM_REG_SOFT_RESET, 0);
10387
10388         if (CNIC_SUPPORT(sc))
10389                 ecore_init_block(sc, BLOCK_TM, PHASE_COMMON);
10390
10391         ecore_init_block(sc, BLOCK_DORQ, PHASE_COMMON);
10392         REG_WR(sc, DORQ_REG_DPM_CID_OFST, BNX2X_DB_SHIFT);
10393
10394         if (!CHIP_REV_IS_SLOW(sc)) {
10395 /* enable hw interrupt from doorbell Q */
10396                 REG_WR(sc, DORQ_REG_DORQ_INT_MASK, 0);
10397         }
10398
10399         ecore_init_block(sc, BLOCK_BRB1, PHASE_COMMON);
10400
10401         ecore_init_block(sc, BLOCK_PRS, PHASE_COMMON);
10402         REG_WR(sc, PRS_REG_A_PRSU_20, 0xf);
10403         REG_WR(sc, PRS_REG_E1HOV_MODE, sc->devinfo.mf_info.path_has_ovlan);
10404
10405         if (!CHIP_IS_E1x(sc) && !CHIP_IS_E3B0(sc)) {
10406                 if (IS_MF_AFEX(sc)) {
10407                         /*
10408                          * configure that AFEX and VLAN headers must be
10409                          * received in AFEX mode
10410                          */
10411                         REG_WR(sc, PRS_REG_HDRS_AFTER_BASIC, 0xE);
10412                         REG_WR(sc, PRS_REG_MUST_HAVE_HDRS, 0xA);
10413                         REG_WR(sc, PRS_REG_HDRS_AFTER_TAG_0, 0x6);
10414                         REG_WR(sc, PRS_REG_TAG_ETHERTYPE_0, 0x8926);
10415                         REG_WR(sc, PRS_REG_TAG_LEN_0, 0x4);
10416                 } else {
10417                         /*
10418                          * Bit-map indicating which L2 hdrs may appear
10419                          * after the basic Ethernet header
10420                          */
10421                         REG_WR(sc, PRS_REG_HDRS_AFTER_BASIC,
10422                                sc->devinfo.mf_info.path_has_ovlan ? 7 : 6);
10423                 }
10424         }
10425
10426         ecore_init_block(sc, BLOCK_TSDM, PHASE_COMMON);
10427         ecore_init_block(sc, BLOCK_CSDM, PHASE_COMMON);
10428         ecore_init_block(sc, BLOCK_USDM, PHASE_COMMON);
10429         ecore_init_block(sc, BLOCK_XSDM, PHASE_COMMON);
10430
10431         if (!CHIP_IS_E1x(sc)) {
10432 /* reset VFC memories */
10433                 REG_WR(sc, TSEM_REG_FAST_MEMORY + VFC_REG_MEMORIES_RST,
10434                        VFC_MEMORIES_RST_REG_CAM_RST |
10435                        VFC_MEMORIES_RST_REG_RAM_RST);
10436                 REG_WR(sc, XSEM_REG_FAST_MEMORY + VFC_REG_MEMORIES_RST,
10437                        VFC_MEMORIES_RST_REG_CAM_RST |
10438                        VFC_MEMORIES_RST_REG_RAM_RST);
10439
10440                 DELAY(20000);
10441         }
10442
10443         ecore_init_block(sc, BLOCK_TSEM, PHASE_COMMON);
10444         ecore_init_block(sc, BLOCK_USEM, PHASE_COMMON);
10445         ecore_init_block(sc, BLOCK_CSEM, PHASE_COMMON);
10446         ecore_init_block(sc, BLOCK_XSEM, PHASE_COMMON);
10447
10448         /* sync semi rtc */
10449         REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR, 0x80000000);
10450         REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, 0x80000000);
10451
10452         ecore_init_block(sc, BLOCK_UPB, PHASE_COMMON);
10453         ecore_init_block(sc, BLOCK_XPB, PHASE_COMMON);
10454         ecore_init_block(sc, BLOCK_PBF, PHASE_COMMON);
10455
10456         if (!CHIP_IS_E1x(sc)) {
10457                 if (IS_MF_AFEX(sc)) {
10458                         /*
10459                          * configure that AFEX and VLAN headers must be
10460                          * sent in AFEX mode
10461                          */
10462                         REG_WR(sc, PBF_REG_HDRS_AFTER_BASIC, 0xE);
10463                         REG_WR(sc, PBF_REG_MUST_HAVE_HDRS, 0xA);
10464                         REG_WR(sc, PBF_REG_HDRS_AFTER_TAG_0, 0x6);
10465                         REG_WR(sc, PBF_REG_TAG_ETHERTYPE_0, 0x8926);
10466                         REG_WR(sc, PBF_REG_TAG_LEN_0, 0x4);
10467                 } else {
10468                         REG_WR(sc, PBF_REG_HDRS_AFTER_BASIC,
10469                                sc->devinfo.mf_info.path_has_ovlan ? 7 : 6);
10470                 }
10471         }
10472
10473         REG_WR(sc, SRC_REG_SOFT_RST, 1);
10474
10475         ecore_init_block(sc, BLOCK_SRC, PHASE_COMMON);
10476
10477         if (CNIC_SUPPORT(sc)) {
10478                 REG_WR(sc, SRC_REG_KEYSEARCH_0, 0x63285672);
10479                 REG_WR(sc, SRC_REG_KEYSEARCH_1, 0x24b8f2cc);
10480                 REG_WR(sc, SRC_REG_KEYSEARCH_2, 0x223aef9b);
10481                 REG_WR(sc, SRC_REG_KEYSEARCH_3, 0x26001e3a);
10482                 REG_WR(sc, SRC_REG_KEYSEARCH_4, 0x7ae91116);
10483                 REG_WR(sc, SRC_REG_KEYSEARCH_5, 0x5ce5230b);
10484                 REG_WR(sc, SRC_REG_KEYSEARCH_6, 0x298d8adf);
10485                 REG_WR(sc, SRC_REG_KEYSEARCH_7, 0x6eb0ff09);
10486                 REG_WR(sc, SRC_REG_KEYSEARCH_8, 0x1830f82f);
10487                 REG_WR(sc, SRC_REG_KEYSEARCH_9, 0x01e46be7);
10488         }
10489         REG_WR(sc, SRC_REG_SOFT_RST, 0);
10490
10491         if (sizeof(union cdu_context) != 1024) {
10492 /* we currently assume that a context is 1024 bytes */
10493                 PMD_DRV_LOG(NOTICE, sc,
10494                             "please adjust the size of cdu_context(%ld)",
10495                             (long)sizeof(union cdu_context));
10496         }
10497
10498         ecore_init_block(sc, BLOCK_CDU, PHASE_COMMON);
10499         val = (4 << 24) + (0 << 12) + 1024;
10500         REG_WR(sc, CDU_REG_CDU_GLOBAL_PARAMS, val);
10501
10502         ecore_init_block(sc, BLOCK_CFC, PHASE_COMMON);
10503
10504         REG_WR(sc, CFC_REG_INIT_REG, 0x7FF);
10505         /* enable context validation interrupt from CFC */
10506         REG_WR(sc, CFC_REG_CFC_INT_MASK, 0);
10507
10508         /* set the thresholds to prevent CFC/CDU race */
10509         REG_WR(sc, CFC_REG_DEBUG0, 0x20020000);
10510         ecore_init_block(sc, BLOCK_HC, PHASE_COMMON);
10511
10512         if (!CHIP_IS_E1x(sc) && BNX2X_NOMCP(sc)) {
10513                 REG_WR(sc, IGU_REG_RESET_MEMORIES, 0x36);
10514         }
10515
10516         ecore_init_block(sc, BLOCK_IGU, PHASE_COMMON);
10517         ecore_init_block(sc, BLOCK_MISC_AEU, PHASE_COMMON);
10518
10519         /* Reset PCIE errors for debug */
10520         REG_WR(sc, 0x2814, 0xffffffff);
10521         REG_WR(sc, 0x3820, 0xffffffff);
10522
10523         if (!CHIP_IS_E1x(sc)) {
10524                 REG_WR(sc, PCICFG_OFFSET + PXPCS_TL_CONTROL_5,
10525                        (PXPCS_TL_CONTROL_5_ERR_UNSPPORT1 |
10526                         PXPCS_TL_CONTROL_5_ERR_UNSPPORT));
10527                 REG_WR(sc, PCICFG_OFFSET + PXPCS_TL_FUNC345_STAT,
10528                        (PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT4 |
10529                         PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT3 |
10530                         PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT2));
10531                 REG_WR(sc, PCICFG_OFFSET + PXPCS_TL_FUNC678_STAT,
10532                        (PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT7 |
10533                         PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT6 |
10534                         PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT5));
10535         }
10536
10537         ecore_init_block(sc, BLOCK_NIG, PHASE_COMMON);
10538
10539         /* in E3 this done in per-port section */
10540         if (!CHIP_IS_E3(sc))
10541                 REG_WR(sc, NIG_REG_LLH_MF_MODE, IS_MF(sc));
10542
10543         if (CHIP_IS_E1H(sc)) {
10544 /* not applicable for E2 (and above ...) */
10545                 REG_WR(sc, NIG_REG_LLH_E1HOV_MODE, IS_MF_SD(sc));
10546         }
10547
10548         if (CHIP_REV_IS_SLOW(sc)) {
10549                 DELAY(200000);
10550         }
10551
10552         /* finish CFC init */
10553         val = reg_poll(sc, CFC_REG_LL_INIT_DONE, 1, 100, 10);
10554         if (val != 1) {
10555                 PMD_DRV_LOG(NOTICE, sc, "CFC LL_INIT failed");
10556                 return -1;
10557         }
10558         val = reg_poll(sc, CFC_REG_AC_INIT_DONE, 1, 100, 10);
10559         if (val != 1) {
10560                 PMD_DRV_LOG(NOTICE, sc, "CFC AC_INIT failed");
10561                 return -1;
10562         }
10563         val = reg_poll(sc, CFC_REG_CAM_INIT_DONE, 1, 100, 10);
10564         if (val != 1) {
10565                 PMD_DRV_LOG(NOTICE, sc, "CFC CAM_INIT failed");
10566                 return -1;
10567         }
10568         REG_WR(sc, CFC_REG_DEBUG0, 0);
10569
10570         bnx2x_setup_fan_failure_detection(sc);
10571
10572         /* clear PXP2 attentions */
10573         REG_RD(sc, PXP2_REG_PXP2_INT_STS_CLR_0);
10574
10575         bnx2x_enable_blocks_attention(sc);
10576
10577         if (!CHIP_REV_IS_SLOW(sc)) {
10578                 ecore_enable_blocks_parity(sc);
10579         }
10580
10581         if (!BNX2X_NOMCP(sc)) {
10582                 if (CHIP_IS_E1x(sc)) {
10583                         bnx2x_common_init_phy(sc);
10584                 }
10585         }
10586
10587         return 0;
10588 }
10589
10590 /**
10591  * bnx2x_init_hw_common_chip - init HW at the COMMON_CHIP phase.
10592  *
10593  * @sc:     driver handle
10594  */
10595 static int bnx2x_init_hw_common_chip(struct bnx2x_softc *sc)
10596 {
10597         int rc = bnx2x_init_hw_common(sc);
10598
10599         if (rc) {
10600                 return rc;
10601         }
10602
10603         /* In E2 2-PORT mode, same ext phy is used for the two paths */
10604         if (!BNX2X_NOMCP(sc)) {
10605                 bnx2x_common_init_phy(sc);
10606         }
10607
10608         return 0;
10609 }
10610
10611 static int bnx2x_init_hw_port(struct bnx2x_softc *sc)
10612 {
10613         int port = SC_PORT(sc);
10614         int init_phase = port ? PHASE_PORT1 : PHASE_PORT0;
10615         uint32_t low, high;
10616         uint32_t val;
10617
10618         PMD_DRV_LOG(DEBUG, sc, "starting port init for port %d", port);
10619
10620         REG_WR(sc, NIG_REG_MASK_INTERRUPT_PORT0 + port * 4, 0);
10621
10622         ecore_init_block(sc, BLOCK_MISC, init_phase);
10623         ecore_init_block(sc, BLOCK_PXP, init_phase);
10624         ecore_init_block(sc, BLOCK_PXP2, init_phase);
10625
10626         /*
10627          * Timers bug workaround: disables the pf_master bit in pglue at
10628          * common phase, we need to enable it here before any dmae access are
10629          * attempted. Therefore we manually added the enable-master to the
10630          * port phase (it also happens in the function phase)
10631          */
10632         if (!CHIP_IS_E1x(sc)) {
10633                 REG_WR(sc, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 1);
10634         }
10635
10636         ecore_init_block(sc, BLOCK_ATC, init_phase);
10637         ecore_init_block(sc, BLOCK_DMAE, init_phase);
10638         ecore_init_block(sc, BLOCK_PGLUE_B, init_phase);
10639         ecore_init_block(sc, BLOCK_QM, init_phase);
10640
10641         ecore_init_block(sc, BLOCK_TCM, init_phase);
10642         ecore_init_block(sc, BLOCK_UCM, init_phase);
10643         ecore_init_block(sc, BLOCK_CCM, init_phase);
10644         ecore_init_block(sc, BLOCK_XCM, init_phase);
10645
10646         /* QM cid (connection) count */
10647         ecore_qm_init_cid_count(sc, sc->qm_cid_count, INITOP_SET);
10648
10649         if (CNIC_SUPPORT(sc)) {
10650                 ecore_init_block(sc, BLOCK_TM, init_phase);
10651                 REG_WR(sc, TM_REG_LIN0_SCAN_TIME + port * 4, 20);
10652                 REG_WR(sc, TM_REG_LIN0_MAX_ACTIVE_CID + port * 4, 31);
10653         }
10654
10655         ecore_init_block(sc, BLOCK_DORQ, init_phase);
10656
10657         ecore_init_block(sc, BLOCK_BRB1, init_phase);
10658
10659         if (CHIP_IS_E1H(sc)) {
10660                 if (IS_MF(sc)) {
10661                         low = (BNX2X_ONE_PORT(sc) ? 160 : 246);
10662                 } else if (sc->mtu > 4096) {
10663                         if (BNX2X_ONE_PORT(sc)) {
10664                                 low = 160;
10665                         } else {
10666                                 val = sc->mtu;
10667                                 /* (24*1024 + val*4)/256 */
10668                                 low = (96 + (val / 64) + ((val % 64) ? 1 : 0));
10669                         }
10670                 } else {
10671                         low = (BNX2X_ONE_PORT(sc) ? 80 : 160);
10672                 }
10673                 high = (low + 56);      /* 14*1024/256 */
10674                 REG_WR(sc, BRB1_REG_PAUSE_LOW_THRESHOLD_0 + port * 4, low);
10675                 REG_WR(sc, BRB1_REG_PAUSE_HIGH_THRESHOLD_0 + port * 4, high);
10676         }
10677
10678         if (CHIP_IS_MODE_4_PORT(sc)) {
10679                 REG_WR(sc, SC_PORT(sc) ?
10680                        BRB1_REG_MAC_GUARANTIED_1 :
10681                        BRB1_REG_MAC_GUARANTIED_0, 40);
10682         }
10683
10684         ecore_init_block(sc, BLOCK_PRS, init_phase);
10685         if (CHIP_IS_E3B0(sc)) {
10686                 if (IS_MF_AFEX(sc)) {
10687                         /* configure headers for AFEX mode */
10688                         if (SC_PORT(sc)) {
10689                                 REG_WR(sc, PRS_REG_HDRS_AFTER_BASIC_PORT_1,
10690                                        0xE);
10691                                 REG_WR(sc, PRS_REG_HDRS_AFTER_TAG_0_PORT_1,
10692                                        0x6);
10693                                 REG_WR(sc, PRS_REG_MUST_HAVE_HDRS_PORT_1, 0xA);
10694                         } else {
10695                                 REG_WR(sc, PRS_REG_HDRS_AFTER_BASIC_PORT_0,
10696                                        0xE);
10697                                 REG_WR(sc, PRS_REG_HDRS_AFTER_TAG_0_PORT_0,
10698                                        0x6);
10699                                 REG_WR(sc, PRS_REG_MUST_HAVE_HDRS_PORT_0, 0xA);
10700                         }
10701                 } else {
10702                         /* Ovlan exists only if we are in multi-function +
10703                          * switch-dependent mode, in switch-independent there
10704                          * is no ovlan headers
10705                          */
10706                         REG_WR(sc, SC_PORT(sc) ?
10707                                PRS_REG_HDRS_AFTER_BASIC_PORT_1 :
10708                                PRS_REG_HDRS_AFTER_BASIC_PORT_0,
10709                                (sc->devinfo.mf_info.path_has_ovlan ? 7 : 6));
10710                 }
10711         }
10712
10713         ecore_init_block(sc, BLOCK_TSDM, init_phase);
10714         ecore_init_block(sc, BLOCK_CSDM, init_phase);
10715         ecore_init_block(sc, BLOCK_USDM, init_phase);
10716         ecore_init_block(sc, BLOCK_XSDM, init_phase);
10717
10718         ecore_init_block(sc, BLOCK_TSEM, init_phase);
10719         ecore_init_block(sc, BLOCK_USEM, init_phase);
10720         ecore_init_block(sc, BLOCK_CSEM, init_phase);
10721         ecore_init_block(sc, BLOCK_XSEM, init_phase);
10722
10723         ecore_init_block(sc, BLOCK_UPB, init_phase);
10724         ecore_init_block(sc, BLOCK_XPB, init_phase);
10725
10726         ecore_init_block(sc, BLOCK_PBF, init_phase);
10727
10728         if (CHIP_IS_E1x(sc)) {
10729 /* configure PBF to work without PAUSE mtu 9000 */
10730                 REG_WR(sc, PBF_REG_P0_PAUSE_ENABLE + port * 4, 0);
10731
10732 /* update threshold */
10733                 REG_WR(sc, PBF_REG_P0_ARB_THRSH + port * 4, (9040 / 16));
10734 /* update init credit */
10735                 REG_WR(sc, PBF_REG_P0_INIT_CRD + port * 4,
10736                        (9040 / 16) + 553 - 22);
10737
10738 /* probe changes */
10739                 REG_WR(sc, PBF_REG_INIT_P0 + port * 4, 1);
10740                 DELAY(50);
10741                 REG_WR(sc, PBF_REG_INIT_P0 + port * 4, 0);
10742         }
10743
10744         if (CNIC_SUPPORT(sc)) {
10745                 ecore_init_block(sc, BLOCK_SRC, init_phase);
10746         }
10747
10748         ecore_init_block(sc, BLOCK_CDU, init_phase);
10749         ecore_init_block(sc, BLOCK_CFC, init_phase);
10750         ecore_init_block(sc, BLOCK_HC, init_phase);
10751         ecore_init_block(sc, BLOCK_IGU, init_phase);
10752         ecore_init_block(sc, BLOCK_MISC_AEU, init_phase);
10753         /* init aeu_mask_attn_func_0/1:
10754          *  - SF mode: bits 3-7 are masked. only bits 0-2 are in use
10755          *  - MF mode: bit 3 is masked. bits 0-2 are in use as in SF
10756          *             bits 4-7 are used for "per vn group attention" */
10757         val = IS_MF(sc) ? 0xF7 : 0x7;
10758         val |= 0x10;
10759         REG_WR(sc, MISC_REG_AEU_MASK_ATTN_FUNC_0 + port * 4, val);
10760
10761         ecore_init_block(sc, BLOCK_NIG, init_phase);
10762
10763         if (!CHIP_IS_E1x(sc)) {
10764 /* Bit-map indicating which L2 hdrs may appear after the
10765  * basic Ethernet header
10766  */
10767                 if (IS_MF_AFEX(sc)) {
10768                         REG_WR(sc, SC_PORT(sc) ?
10769                                NIG_REG_P1_HDRS_AFTER_BASIC :
10770                                NIG_REG_P0_HDRS_AFTER_BASIC, 0xE);
10771                 } else {
10772                         REG_WR(sc, SC_PORT(sc) ?
10773                                NIG_REG_P1_HDRS_AFTER_BASIC :
10774                                NIG_REG_P0_HDRS_AFTER_BASIC,
10775                                IS_MF_SD(sc) ? 7 : 6);
10776                 }
10777
10778                 if (CHIP_IS_E3(sc)) {
10779                         REG_WR(sc, SC_PORT(sc) ?
10780                                NIG_REG_LLH1_MF_MODE :
10781                                NIG_REG_LLH_MF_MODE, IS_MF(sc));
10782                 }
10783         }
10784         if (!CHIP_IS_E3(sc)) {
10785                 REG_WR(sc, NIG_REG_XGXS_SERDES0_MODE_SEL + port * 4, 1);
10786         }
10787
10788         /* 0x2 disable mf_ov, 0x1 enable */
10789         REG_WR(sc, NIG_REG_LLH0_BRB1_DRV_MASK_MF + port * 4,
10790                (IS_MF_SD(sc) ? 0x1 : 0x2));
10791
10792         if (!CHIP_IS_E1x(sc)) {
10793                 val = 0;
10794                 switch (sc->devinfo.mf_info.mf_mode) {
10795                 case MULTI_FUNCTION_SD:
10796                         val = 1;
10797                         break;
10798                 case MULTI_FUNCTION_SI:
10799                 case MULTI_FUNCTION_AFEX:
10800                         val = 2;
10801                         break;
10802                 }
10803
10804                 REG_WR(sc, (SC_PORT(sc) ? NIG_REG_LLH1_CLS_TYPE :
10805                             NIG_REG_LLH0_CLS_TYPE), val);
10806         }
10807         REG_WR(sc, NIG_REG_LLFC_ENABLE_0 + port * 4, 0);
10808         REG_WR(sc, NIG_REG_LLFC_OUT_EN_0 + port * 4, 0);
10809         REG_WR(sc, NIG_REG_PAUSE_ENABLE_0 + port * 4, 1);
10810
10811         /* If SPIO5 is set to generate interrupts, enable it for this port */
10812         val = REG_RD(sc, MISC_REG_SPIO_EVENT_EN);
10813         if (val & MISC_SPIO_SPIO5) {
10814                 uint32_t reg_addr = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 :
10815                                      MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0);
10816                 val = REG_RD(sc, reg_addr);
10817                 val |= AEU_INPUTS_ATTN_BITS_SPIO5;
10818                 REG_WR(sc, reg_addr, val);
10819         }
10820
10821         return 0;
10822 }
10823
10824 static uint32_t
10825 bnx2x_flr_clnup_reg_poll(struct bnx2x_softc *sc, uint32_t reg,
10826                        uint32_t expected, uint32_t poll_count)
10827 {
10828         uint32_t cur_cnt = poll_count;
10829         uint32_t val;
10830
10831         while ((val = REG_RD(sc, reg)) != expected && cur_cnt--) {
10832                 DELAY(FLR_WAIT_INTERVAL);
10833         }
10834
10835         return val;
10836 }
10837
10838 static int
10839 bnx2x_flr_clnup_poll_hw_counter(struct bnx2x_softc *sc, uint32_t reg,
10840                               __rte_unused const char *msg, uint32_t poll_cnt)
10841 {
10842         uint32_t val = bnx2x_flr_clnup_reg_poll(sc, reg, 0, poll_cnt);
10843
10844         if (val != 0) {
10845                 PMD_DRV_LOG(NOTICE, sc, "%s usage count=%d", msg, val);
10846                 return -1;
10847         }
10848
10849         return 0;
10850 }
10851
10852 /* Common routines with VF FLR cleanup */
10853 static uint32_t bnx2x_flr_clnup_poll_count(struct bnx2x_softc *sc)
10854 {
10855         /* adjust polling timeout */
10856         if (CHIP_REV_IS_EMUL(sc)) {
10857                 return FLR_POLL_CNT * 2000;
10858         }
10859
10860         if (CHIP_REV_IS_FPGA(sc)) {
10861                 return FLR_POLL_CNT * 120;
10862         }
10863
10864         return FLR_POLL_CNT;
10865 }
10866
10867 static int bnx2x_poll_hw_usage_counters(struct bnx2x_softc *sc, uint32_t poll_cnt)
10868 {
10869         /* wait for CFC PF usage-counter to zero (includes all the VFs) */
10870         if (bnx2x_flr_clnup_poll_hw_counter(sc,
10871                                           CFC_REG_NUM_LCIDS_INSIDE_PF,
10872                                           "CFC PF usage counter timed out",
10873                                           poll_cnt)) {
10874                 return -1;
10875         }
10876
10877         /* Wait for DQ PF usage-counter to zero (until DQ cleanup) */
10878         if (bnx2x_flr_clnup_poll_hw_counter(sc,
10879                                           DORQ_REG_PF_USAGE_CNT,
10880                                           "DQ PF usage counter timed out",
10881                                           poll_cnt)) {
10882                 return -1;
10883         }
10884
10885         /* Wait for QM PF usage-counter to zero (until DQ cleanup) */
10886         if (bnx2x_flr_clnup_poll_hw_counter(sc,
10887                                           QM_REG_PF_USG_CNT_0 + 4 * SC_FUNC(sc),
10888                                           "QM PF usage counter timed out",
10889                                           poll_cnt)) {
10890                 return -1;
10891         }
10892
10893         /* Wait for Timer PF usage-counters to zero (until DQ cleanup) */
10894         if (bnx2x_flr_clnup_poll_hw_counter(sc,
10895                                           TM_REG_LIN0_VNIC_UC + 4 * SC_PORT(sc),
10896                                           "Timers VNIC usage counter timed out",
10897                                           poll_cnt)) {
10898                 return -1;
10899         }
10900
10901         if (bnx2x_flr_clnup_poll_hw_counter(sc,
10902                                           TM_REG_LIN0_NUM_SCANS +
10903                                           4 * SC_PORT(sc),
10904                                           "Timers NUM_SCANS usage counter timed out",
10905                                           poll_cnt)) {
10906                 return -1;
10907         }
10908
10909         /* Wait DMAE PF usage counter to zero */
10910         if (bnx2x_flr_clnup_poll_hw_counter(sc,
10911                                           dmae_reg_go_c[INIT_DMAE_C(sc)],
10912                                           "DMAE dommand register timed out",
10913                                           poll_cnt)) {
10914                 return -1;
10915         }
10916
10917         return 0;
10918 }
10919
10920 #define OP_GEN_PARAM(param)                                            \
10921         (((param) << SDM_OP_GEN_COMP_PARAM_SHIFT) & SDM_OP_GEN_COMP_PARAM)
10922 #define OP_GEN_TYPE(type)                                           \
10923         (((type) << SDM_OP_GEN_COMP_TYPE_SHIFT) & SDM_OP_GEN_COMP_TYPE)
10924 #define OP_GEN_AGG_VECT(index)                                             \
10925         (((index) << SDM_OP_GEN_AGG_VECT_IDX_SHIFT) & SDM_OP_GEN_AGG_VECT_IDX)
10926
10927 static int
10928 bnx2x_send_final_clnup(struct bnx2x_softc *sc, uint8_t clnup_func,
10929                      uint32_t poll_cnt)
10930 {
10931         uint32_t op_gen_command = 0;
10932         uint32_t comp_addr = (BAR_CSTRORM_INTMEM +
10933                               CSTORM_FINAL_CLEANUP_COMPLETE_OFFSET(clnup_func));
10934         int ret = 0;
10935
10936         if (REG_RD(sc, comp_addr)) {
10937                 PMD_DRV_LOG(NOTICE, sc,
10938                             "Cleanup complete was not 0 before sending");
10939                 return -1;
10940         }
10941
10942         op_gen_command |= OP_GEN_PARAM(XSTORM_AGG_INT_FINAL_CLEANUP_INDEX);
10943         op_gen_command |= OP_GEN_TYPE(XSTORM_AGG_INT_FINAL_CLEANUP_COMP_TYPE);
10944         op_gen_command |= OP_GEN_AGG_VECT(clnup_func);
10945         op_gen_command |= 1 << SDM_OP_GEN_AGG_VECT_IDX_VALID_SHIFT;
10946
10947         REG_WR(sc, XSDM_REG_OPERATION_GEN, op_gen_command);
10948
10949         if (bnx2x_flr_clnup_reg_poll(sc, comp_addr, 1, poll_cnt) != 1) {
10950                 PMD_DRV_LOG(NOTICE, sc, "FW final cleanup did not succeed");
10951                 PMD_DRV_LOG(DEBUG, sc, "At timeout completion address contained %x",
10952                             (REG_RD(sc, comp_addr)));
10953                 rte_panic("FLR cleanup failed");
10954                 return -1;
10955         }
10956
10957         /* Zero completion for nxt FLR */
10958         REG_WR(sc, comp_addr, 0);
10959
10960         return ret;
10961 }
10962
10963 static void
10964 bnx2x_pbf_pN_buf_flushed(struct bnx2x_softc *sc, struct pbf_pN_buf_regs *regs,
10965                        uint32_t poll_count)
10966 {
10967         uint32_t init_crd, crd, crd_start, crd_freed, crd_freed_start;
10968         uint32_t cur_cnt = poll_count;
10969
10970         crd_freed = crd_freed_start = REG_RD(sc, regs->crd_freed);
10971         crd = crd_start = REG_RD(sc, regs->crd);
10972         init_crd = REG_RD(sc, regs->init_crd);
10973
10974         while ((crd != init_crd) &&
10975                ((uint32_t) ((int32_t) crd_freed - (int32_t) crd_freed_start) <
10976                 (init_crd - crd_start))) {
10977                 if (cur_cnt--) {
10978                         DELAY(FLR_WAIT_INTERVAL);
10979                         crd = REG_RD(sc, regs->crd);
10980                         crd_freed = REG_RD(sc, regs->crd_freed);
10981                 } else {
10982                         break;
10983                 }
10984         }
10985 }
10986
10987 static void
10988 bnx2x_pbf_pN_cmd_flushed(struct bnx2x_softc *sc, struct pbf_pN_cmd_regs *regs,
10989                        uint32_t poll_count)
10990 {
10991         uint32_t occup, to_free, freed, freed_start;
10992         uint32_t cur_cnt = poll_count;
10993
10994         occup = to_free = REG_RD(sc, regs->lines_occup);
10995         freed = freed_start = REG_RD(sc, regs->lines_freed);
10996
10997         while (occup &&
10998                ((uint32_t) ((int32_t) freed - (int32_t) freed_start) <
10999                 to_free)) {
11000                 if (cur_cnt--) {
11001                         DELAY(FLR_WAIT_INTERVAL);
11002                         occup = REG_RD(sc, regs->lines_occup);
11003                         freed = REG_RD(sc, regs->lines_freed);
11004                 } else {
11005                         break;
11006                 }
11007         }
11008 }
11009
11010 static void bnx2x_tx_hw_flushed(struct bnx2x_softc *sc, uint32_t poll_count)
11011 {
11012         struct pbf_pN_cmd_regs cmd_regs[] = {
11013                 {0, (CHIP_IS_E3B0(sc)) ?
11014                  PBF_REG_TQ_OCCUPANCY_Q0 : PBF_REG_P0_TQ_OCCUPANCY,
11015                  (CHIP_IS_E3B0(sc)) ?
11016                  PBF_REG_TQ_LINES_FREED_CNT_Q0 : PBF_REG_P0_TQ_LINES_FREED_CNT},
11017                 {1, (CHIP_IS_E3B0(sc)) ?
11018                  PBF_REG_TQ_OCCUPANCY_Q1 : PBF_REG_P1_TQ_OCCUPANCY,
11019                  (CHIP_IS_E3B0(sc)) ?
11020                  PBF_REG_TQ_LINES_FREED_CNT_Q1 : PBF_REG_P1_TQ_LINES_FREED_CNT},
11021                 {4, (CHIP_IS_E3B0(sc)) ?
11022                  PBF_REG_TQ_OCCUPANCY_LB_Q : PBF_REG_P4_TQ_OCCUPANCY,
11023                  (CHIP_IS_E3B0(sc)) ?
11024                  PBF_REG_TQ_LINES_FREED_CNT_LB_Q :
11025                  PBF_REG_P4_TQ_LINES_FREED_CNT}
11026         };
11027
11028         struct pbf_pN_buf_regs buf_regs[] = {
11029                 {0, (CHIP_IS_E3B0(sc)) ?
11030                  PBF_REG_INIT_CRD_Q0 : PBF_REG_P0_INIT_CRD,
11031                  (CHIP_IS_E3B0(sc)) ? PBF_REG_CREDIT_Q0 : PBF_REG_P0_CREDIT,
11032                  (CHIP_IS_E3B0(sc)) ?
11033                  PBF_REG_INTERNAL_CRD_FREED_CNT_Q0 :
11034                  PBF_REG_P0_INTERNAL_CRD_FREED_CNT},
11035                 {1, (CHIP_IS_E3B0(sc)) ?
11036                  PBF_REG_INIT_CRD_Q1 : PBF_REG_P1_INIT_CRD,
11037                  (CHIP_IS_E3B0(sc)) ? PBF_REG_CREDIT_Q1 : PBF_REG_P1_CREDIT,
11038                  (CHIP_IS_E3B0(sc)) ?
11039                  PBF_REG_INTERNAL_CRD_FREED_CNT_Q1 :
11040                  PBF_REG_P1_INTERNAL_CRD_FREED_CNT},
11041                 {4, (CHIP_IS_E3B0(sc)) ?
11042                  PBF_REG_INIT_CRD_LB_Q : PBF_REG_P4_INIT_CRD,
11043                  (CHIP_IS_E3B0(sc)) ? PBF_REG_CREDIT_LB_Q : PBF_REG_P4_CREDIT,
11044                  (CHIP_IS_E3B0(sc)) ?
11045                  PBF_REG_INTERNAL_CRD_FREED_CNT_LB_Q :
11046                  PBF_REG_P4_INTERNAL_CRD_FREED_CNT},
11047         };
11048
11049         uint32_t i;
11050
11051         /* Verify the command queues are flushed P0, P1, P4 */
11052         for (i = 0; i < ARRAY_SIZE(cmd_regs); i++) {
11053                 bnx2x_pbf_pN_cmd_flushed(sc, &cmd_regs[i], poll_count);
11054         }
11055
11056         /* Verify the transmission buffers are flushed P0, P1, P4 */
11057         for (i = 0; i < ARRAY_SIZE(buf_regs); i++) {
11058                 bnx2x_pbf_pN_buf_flushed(sc, &buf_regs[i], poll_count);
11059         }
11060 }
11061
11062 static void bnx2x_hw_enable_status(struct bnx2x_softc *sc)
11063 {
11064         __rte_unused uint32_t val;
11065
11066         val = REG_RD(sc, CFC_REG_WEAK_ENABLE_PF);
11067         PMD_DRV_LOG(DEBUG, sc, "CFC_REG_WEAK_ENABLE_PF is 0x%x", val);
11068
11069         val = REG_RD(sc, PBF_REG_DISABLE_PF);
11070         PMD_DRV_LOG(DEBUG, sc, "PBF_REG_DISABLE_PF is 0x%x", val);
11071
11072         val = REG_RD(sc, IGU_REG_PCI_PF_MSI_EN);
11073         PMD_DRV_LOG(DEBUG, sc, "IGU_REG_PCI_PF_MSI_EN is 0x%x", val);
11074
11075         val = REG_RD(sc, IGU_REG_PCI_PF_MSIX_EN);
11076         PMD_DRV_LOG(DEBUG, sc, "IGU_REG_PCI_PF_MSIX_EN is 0x%x", val);
11077
11078         val = REG_RD(sc, IGU_REG_PCI_PF_MSIX_FUNC_MASK);
11079         PMD_DRV_LOG(DEBUG, sc, "IGU_REG_PCI_PF_MSIX_FUNC_MASK is 0x%x", val);
11080
11081         val = REG_RD(sc, PGLUE_B_REG_SHADOW_BME_PF_7_0_CLR);
11082         PMD_DRV_LOG(DEBUG, sc,
11083                     "PGLUE_B_REG_SHADOW_BME_PF_7_0_CLR is 0x%x", val);
11084
11085         val = REG_RD(sc, PGLUE_B_REG_FLR_REQUEST_PF_7_0_CLR);
11086         PMD_DRV_LOG(DEBUG, sc,
11087                     "PGLUE_B_REG_FLR_REQUEST_PF_7_0_CLR is 0x%x", val);
11088
11089         val = REG_RD(sc, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER);
11090         PMD_DRV_LOG(DEBUG, sc, "PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER is 0x%x",
11091                     val);
11092 }
11093
11094 /**
11095  *      bnx2x_pf_flr_clnup
11096  *      a. re-enable target read on the PF
11097  *      b. poll cfc per function usgae counter
11098  *      c. poll the qm perfunction usage counter
11099  *      d. poll the tm per function usage counter
11100  *      e. poll the tm per function scan-done indication
11101  *      f. clear the dmae channel associated wit hthe PF
11102  *      g. zero the igu 'trailing edge' and 'leading edge' regs (attentions)
11103  *      h. call the common flr cleanup code with -1 (pf indication)
11104  */
11105 static int bnx2x_pf_flr_clnup(struct bnx2x_softc *sc)
11106 {
11107         uint32_t poll_cnt = bnx2x_flr_clnup_poll_count(sc);
11108
11109         /* Re-enable PF target read access */
11110         REG_WR(sc, PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_READ, 1);
11111
11112         /* Poll HW usage counters */
11113         if (bnx2x_poll_hw_usage_counters(sc, poll_cnt)) {
11114                 return -1;
11115         }
11116
11117         /* Zero the igu 'trailing edge' and 'leading edge' */
11118
11119         /* Send the FW cleanup command */
11120         if (bnx2x_send_final_clnup(sc, (uint8_t) SC_FUNC(sc), poll_cnt)) {
11121                 return -1;
11122         }
11123
11124         /* ATC cleanup */
11125
11126         /* Verify TX hw is flushed */
11127         bnx2x_tx_hw_flushed(sc, poll_cnt);
11128
11129         /* Wait 100ms (not adjusted according to platform) */
11130         DELAY(100000);
11131
11132         /* Verify no pending pci transactions */
11133         if (bnx2x_is_pcie_pending(sc)) {
11134                 PMD_DRV_LOG(NOTICE, sc, "PCIE Transactions still pending");
11135         }
11136
11137         /* Debug */
11138         bnx2x_hw_enable_status(sc);
11139
11140         /*
11141          * Master enable - Due to WB DMAE writes performed before this
11142          * register is re-initialized as part of the regular function init
11143          */
11144         REG_WR(sc, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 1);
11145
11146         return 0;
11147 }
11148
11149 static int bnx2x_init_hw_func(struct bnx2x_softc *sc)
11150 {
11151         int port = SC_PORT(sc);
11152         int func = SC_FUNC(sc);
11153         int init_phase = PHASE_PF0 + func;
11154         struct ecore_ilt *ilt = sc->ilt;
11155         uint16_t cdu_ilt_start;
11156         uint32_t addr, val;
11157         uint32_t main_mem_base, main_mem_size, main_mem_prty_clr;
11158         int main_mem_width, rc;
11159         uint32_t i;
11160
11161         PMD_DRV_LOG(DEBUG, sc, "starting func init for func %d", func);
11162
11163         /* FLR cleanup */
11164         if (!CHIP_IS_E1x(sc)) {
11165                 rc = bnx2x_pf_flr_clnup(sc);
11166                 if (rc) {
11167                         PMD_DRV_LOG(NOTICE, sc, "FLR cleanup failed!");
11168                         return rc;
11169                 }
11170         }
11171
11172         /* set MSI reconfigure capability */
11173         if (sc->devinfo.int_block == INT_BLOCK_HC) {
11174                 addr = (port ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0);
11175                 val = REG_RD(sc, addr);
11176                 val |= HC_CONFIG_0_REG_MSI_ATTN_EN_0;
11177                 REG_WR(sc, addr, val);
11178         }
11179
11180         ecore_init_block(sc, BLOCK_PXP, init_phase);
11181         ecore_init_block(sc, BLOCK_PXP2, init_phase);
11182
11183         ilt = sc->ilt;
11184         cdu_ilt_start = ilt->clients[ILT_CLIENT_CDU].start;
11185
11186         for (i = 0; i < L2_ILT_LINES(sc); i++) {
11187                 ilt->lines[cdu_ilt_start + i].page = sc->context[i].vcxt;
11188                 ilt->lines[cdu_ilt_start + i].page_mapping =
11189                     (rte_iova_t)sc->context[i].vcxt_dma.paddr;
11190                 ilt->lines[cdu_ilt_start + i].size = sc->context[i].size;
11191         }
11192         ecore_ilt_init_op(sc, INITOP_SET);
11193
11194         REG_WR(sc, PRS_REG_NIC_MODE, 1);
11195
11196         if (!CHIP_IS_E1x(sc)) {
11197                 uint32_t pf_conf = IGU_PF_CONF_FUNC_EN;
11198
11199 /* Turn on a single ISR mode in IGU if driver is going to use
11200  * INT#x or MSI
11201  */
11202                 if ((sc->interrupt_mode != INTR_MODE_MSIX)
11203                     || (sc->interrupt_mode != INTR_MODE_SINGLE_MSIX)) {
11204                         pf_conf |= IGU_PF_CONF_SINGLE_ISR_EN;
11205                 }
11206
11207 /*
11208  * Timers workaround bug: function init part.
11209  * Need to wait 20msec after initializing ILT,
11210  * needed to make sure there are no requests in
11211  * one of the PXP internal queues with "old" ILT addresses
11212  */
11213                 DELAY(20000);
11214
11215 /*
11216  * Master enable - Due to WB DMAE writes performed before this
11217  * register is re-initialized as part of the regular function
11218  * init
11219  */
11220                 REG_WR(sc, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 1);
11221 /* Enable the function in IGU */
11222                 REG_WR(sc, IGU_REG_PF_CONFIGURATION, pf_conf);
11223         }
11224
11225         sc->dmae_ready = 1;
11226
11227         ecore_init_block(sc, BLOCK_PGLUE_B, init_phase);
11228
11229         if (!CHIP_IS_E1x(sc))
11230                 REG_WR(sc, PGLUE_B_REG_WAS_ERROR_PF_7_0_CLR, func);
11231
11232         ecore_init_block(sc, BLOCK_ATC, init_phase);
11233         ecore_init_block(sc, BLOCK_DMAE, init_phase);
11234         ecore_init_block(sc, BLOCK_NIG, init_phase);
11235         ecore_init_block(sc, BLOCK_SRC, init_phase);
11236         ecore_init_block(sc, BLOCK_MISC, init_phase);
11237         ecore_init_block(sc, BLOCK_TCM, init_phase);
11238         ecore_init_block(sc, BLOCK_UCM, init_phase);
11239         ecore_init_block(sc, BLOCK_CCM, init_phase);
11240         ecore_init_block(sc, BLOCK_XCM, init_phase);
11241         ecore_init_block(sc, BLOCK_TSEM, init_phase);
11242         ecore_init_block(sc, BLOCK_USEM, init_phase);
11243         ecore_init_block(sc, BLOCK_CSEM, init_phase);
11244         ecore_init_block(sc, BLOCK_XSEM, init_phase);
11245
11246         if (!CHIP_IS_E1x(sc))
11247                 REG_WR(sc, QM_REG_PF_EN, 1);
11248
11249         if (!CHIP_IS_E1x(sc)) {
11250                 REG_WR(sc, TSEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func);
11251                 REG_WR(sc, USEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func);
11252                 REG_WR(sc, CSEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func);
11253                 REG_WR(sc, XSEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func);
11254         }
11255         ecore_init_block(sc, BLOCK_QM, init_phase);
11256
11257         ecore_init_block(sc, BLOCK_TM, init_phase);
11258         ecore_init_block(sc, BLOCK_DORQ, init_phase);
11259
11260         ecore_init_block(sc, BLOCK_BRB1, init_phase);
11261         ecore_init_block(sc, BLOCK_PRS, init_phase);
11262         ecore_init_block(sc, BLOCK_TSDM, init_phase);
11263         ecore_init_block(sc, BLOCK_CSDM, init_phase);
11264         ecore_init_block(sc, BLOCK_USDM, init_phase);
11265         ecore_init_block(sc, BLOCK_XSDM, init_phase);
11266         ecore_init_block(sc, BLOCK_UPB, init_phase);
11267         ecore_init_block(sc, BLOCK_XPB, init_phase);
11268         ecore_init_block(sc, BLOCK_PBF, init_phase);
11269         if (!CHIP_IS_E1x(sc))
11270                 REG_WR(sc, PBF_REG_DISABLE_PF, 0);
11271
11272         ecore_init_block(sc, BLOCK_CDU, init_phase);
11273
11274         ecore_init_block(sc, BLOCK_CFC, init_phase);
11275
11276         if (!CHIP_IS_E1x(sc))
11277                 REG_WR(sc, CFC_REG_WEAK_ENABLE_PF, 1);
11278
11279         if (IS_MF(sc)) {
11280                 REG_WR(sc, NIG_REG_LLH0_FUNC_EN + port * 8, 1);
11281                 REG_WR(sc, NIG_REG_LLH0_FUNC_VLAN_ID + port * 8, OVLAN(sc));
11282         }
11283
11284         ecore_init_block(sc, BLOCK_MISC_AEU, init_phase);
11285
11286         /* HC init per function */
11287         if (sc->devinfo.int_block == INT_BLOCK_HC) {
11288                 if (CHIP_IS_E1H(sc)) {
11289                         REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_12 + func * 4, 0);
11290
11291                         REG_WR(sc, HC_REG_LEADING_EDGE_0 + port * 8, 0);
11292                         REG_WR(sc, HC_REG_TRAILING_EDGE_0 + port * 8, 0);
11293                 }
11294                 ecore_init_block(sc, BLOCK_HC, init_phase);
11295
11296         } else {
11297                 uint32_t num_segs, sb_idx, prod_offset;
11298
11299                 REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_12 + func * 4, 0);
11300
11301                 if (!CHIP_IS_E1x(sc)) {
11302                         REG_WR(sc, IGU_REG_LEADING_EDGE_LATCH, 0);
11303                         REG_WR(sc, IGU_REG_TRAILING_EDGE_LATCH, 0);
11304                 }
11305
11306                 ecore_init_block(sc, BLOCK_IGU, init_phase);
11307
11308                 if (!CHIP_IS_E1x(sc)) {
11309                         int dsb_idx = 0;
11310         /**
11311          * Producer memory:
11312          * E2 mode: address 0-135 match to the mapping memory;
11313          * 136 - PF0 default prod; 137 - PF1 default prod;
11314          * 138 - PF2 default prod; 139 - PF3 default prod;
11315          * 140 - PF0 attn prod;    141 - PF1 attn prod;
11316          * 142 - PF2 attn prod;    143 - PF3 attn prod;
11317          * 144-147 reserved.
11318          *
11319          * E1.5 mode - In backward compatible mode;
11320          * for non default SB; each even line in the memory
11321          * holds the U producer and each odd line hold
11322          * the C producer. The first 128 producers are for
11323          * NDSB (PF0 - 0-31; PF1 - 32-63 and so on). The last 20
11324          * producers are for the DSB for each PF.
11325          * Each PF has five segments: (the order inside each
11326          * segment is PF0; PF1; PF2; PF3) - 128-131 U prods;
11327          * 132-135 C prods; 136-139 X prods; 140-143 T prods;
11328          * 144-147 attn prods;
11329          */
11330                         /* non-default-status-blocks */
11331                         num_segs = CHIP_INT_MODE_IS_BC(sc) ?
11332                             IGU_BC_NDSB_NUM_SEGS : IGU_NORM_NDSB_NUM_SEGS;
11333                         for (sb_idx = 0; sb_idx < sc->igu_sb_cnt; sb_idx++) {
11334                                 prod_offset = (sc->igu_base_sb + sb_idx) *
11335                                     num_segs;
11336
11337                                 for (i = 0; i < num_segs; i++) {
11338                                         addr = IGU_REG_PROD_CONS_MEMORY +
11339                                             (prod_offset + i) * 4;
11340                                         REG_WR(sc, addr, 0);
11341                                 }
11342                                 /* send consumer update with value 0 */
11343                                 bnx2x_ack_sb(sc, sc->igu_base_sb + sb_idx,
11344                                            USTORM_ID, 0, IGU_INT_NOP, 1);
11345                                 bnx2x_igu_clear_sb(sc, sc->igu_base_sb + sb_idx);
11346                         }
11347
11348                         /* default-status-blocks */
11349                         num_segs = CHIP_INT_MODE_IS_BC(sc) ?
11350                             IGU_BC_DSB_NUM_SEGS : IGU_NORM_DSB_NUM_SEGS;
11351
11352                         if (CHIP_IS_MODE_4_PORT(sc))
11353                                 dsb_idx = SC_FUNC(sc);
11354                         else
11355                                 dsb_idx = SC_VN(sc);
11356
11357                         prod_offset = (CHIP_INT_MODE_IS_BC(sc) ?
11358                                        IGU_BC_BASE_DSB_PROD + dsb_idx :
11359                                        IGU_NORM_BASE_DSB_PROD + dsb_idx);
11360
11361                         /*
11362                          * igu prods come in chunks of E1HVN_MAX (4) -
11363                          * does not matters what is the current chip mode
11364                          */
11365                         for (i = 0; i < (num_segs * E1HVN_MAX); i += E1HVN_MAX) {
11366                                 addr = IGU_REG_PROD_CONS_MEMORY +
11367                                     (prod_offset + i) * 4;
11368                                 REG_WR(sc, addr, 0);
11369                         }
11370                         /* send consumer update with 0 */
11371                         if (CHIP_INT_MODE_IS_BC(sc)) {
11372                                 bnx2x_ack_sb(sc, sc->igu_dsb_id,
11373                                            USTORM_ID, 0, IGU_INT_NOP, 1);
11374                                 bnx2x_ack_sb(sc, sc->igu_dsb_id,
11375                                            CSTORM_ID, 0, IGU_INT_NOP, 1);
11376                                 bnx2x_ack_sb(sc, sc->igu_dsb_id,
11377                                            XSTORM_ID, 0, IGU_INT_NOP, 1);
11378                                 bnx2x_ack_sb(sc, sc->igu_dsb_id,
11379                                            TSTORM_ID, 0, IGU_INT_NOP, 1);
11380                                 bnx2x_ack_sb(sc, sc->igu_dsb_id,
11381                                            ATTENTION_ID, 0, IGU_INT_NOP, 1);
11382                         } else {
11383                                 bnx2x_ack_sb(sc, sc->igu_dsb_id,
11384                                            USTORM_ID, 0, IGU_INT_NOP, 1);
11385                                 bnx2x_ack_sb(sc, sc->igu_dsb_id,
11386                                            ATTENTION_ID, 0, IGU_INT_NOP, 1);
11387                         }
11388                         bnx2x_igu_clear_sb(sc, sc->igu_dsb_id);
11389
11390                         /* !!! these should become driver const once
11391                            rf-tool supports split-68 const */
11392                         REG_WR(sc, IGU_REG_SB_INT_BEFORE_MASK_LSB, 0);
11393                         REG_WR(sc, IGU_REG_SB_INT_BEFORE_MASK_MSB, 0);
11394                         REG_WR(sc, IGU_REG_SB_MASK_LSB, 0);
11395                         REG_WR(sc, IGU_REG_SB_MASK_MSB, 0);
11396                         REG_WR(sc, IGU_REG_PBA_STATUS_LSB, 0);
11397                         REG_WR(sc, IGU_REG_PBA_STATUS_MSB, 0);
11398                 }
11399         }
11400
11401         /* Reset PCIE errors for debug */
11402         REG_WR(sc, 0x2114, 0xffffffff);
11403         REG_WR(sc, 0x2120, 0xffffffff);
11404
11405         if (CHIP_IS_E1x(sc)) {
11406                 main_mem_size = HC_REG_MAIN_MEMORY_SIZE / 2;    /*dwords */
11407                 main_mem_base = HC_REG_MAIN_MEMORY +
11408                     SC_PORT(sc) * (main_mem_size * 4);
11409                 main_mem_prty_clr = HC_REG_HC_PRTY_STS_CLR;
11410                 main_mem_width = 8;
11411
11412                 val = REG_RD(sc, main_mem_prty_clr);
11413                 if (val) {
11414                         PMD_DRV_LOG(DEBUG, sc,
11415                                     "Parity errors in HC block during function init (0x%x)!",
11416                                     val);
11417                 }
11418
11419 /* Clear "false" parity errors in MSI-X table */
11420                 for (i = main_mem_base;
11421                      i < main_mem_base + main_mem_size * 4;
11422                      i += main_mem_width) {
11423                         bnx2x_read_dmae(sc, i, main_mem_width / 4);
11424                         bnx2x_write_dmae(sc, BNX2X_SP_MAPPING(sc, wb_data),
11425                                        i, main_mem_width / 4);
11426                 }
11427 /* Clear HC parity attention */
11428                 REG_RD(sc, main_mem_prty_clr);
11429         }
11430
11431         /* Enable STORMs SP logging */
11432         REG_WR8(sc, BAR_USTRORM_INTMEM +
11433                 USTORM_RECORD_SLOW_PATH_OFFSET(SC_FUNC(sc)), 1);
11434         REG_WR8(sc, BAR_TSTRORM_INTMEM +
11435                 TSTORM_RECORD_SLOW_PATH_OFFSET(SC_FUNC(sc)), 1);
11436         REG_WR8(sc, BAR_CSTRORM_INTMEM +
11437                 CSTORM_RECORD_SLOW_PATH_OFFSET(SC_FUNC(sc)), 1);
11438         REG_WR8(sc, BAR_XSTRORM_INTMEM +
11439                 XSTORM_RECORD_SLOW_PATH_OFFSET(SC_FUNC(sc)), 1);
11440
11441         elink_phy_probe(&sc->link_params);
11442
11443         return 0;
11444 }
11445
11446 static void bnx2x_link_reset(struct bnx2x_softc *sc)
11447 {
11448         if (!BNX2X_NOMCP(sc)) {
11449                 bnx2x_acquire_phy_lock(sc);
11450                 elink_lfa_reset(&sc->link_params, &sc->link_vars);
11451                 bnx2x_release_phy_lock(sc);
11452         } else {
11453                 if (!CHIP_REV_IS_SLOW(sc)) {
11454                         PMD_DRV_LOG(WARNING, sc,
11455                                     "Bootcode is missing - cannot reset link");
11456                 }
11457         }
11458 }
11459
11460 static void bnx2x_reset_port(struct bnx2x_softc *sc)
11461 {
11462         int port = SC_PORT(sc);
11463         uint32_t val;
11464
11465         /* reset physical Link */
11466         bnx2x_link_reset(sc);
11467
11468         REG_WR(sc, NIG_REG_MASK_INTERRUPT_PORT0 + port * 4, 0);
11469
11470         /* Do not rcv packets to BRB */
11471         REG_WR(sc, NIG_REG_LLH0_BRB1_DRV_MASK + port * 4, 0x0);
11472         /* Do not direct rcv packets that are not for MCP to the BRB */
11473         REG_WR(sc, (port ? NIG_REG_LLH1_BRB1_NOT_MCP :
11474                     NIG_REG_LLH0_BRB1_NOT_MCP), 0x0);
11475
11476         /* Configure AEU */
11477         REG_WR(sc, MISC_REG_AEU_MASK_ATTN_FUNC_0 + port * 4, 0);
11478
11479         DELAY(100000);
11480
11481         /* Check for BRB port occupancy */
11482         val = REG_RD(sc, BRB1_REG_PORT_NUM_OCC_BLOCKS_0 + port * 4);
11483         if (val) {
11484                 PMD_DRV_LOG(DEBUG, sc,
11485                             "BRB1 is not empty, %d blocks are occupied", val);
11486         }
11487 }
11488
11489 static void bnx2x_ilt_wr(struct bnx2x_softc *sc, uint32_t index, rte_iova_t addr)
11490 {
11491         int reg;
11492         uint32_t wb_write[2];
11493
11494         reg = PXP2_REG_RQ_ONCHIP_AT_B0 + index * 8;
11495
11496         wb_write[0] = ONCHIP_ADDR1(addr);
11497         wb_write[1] = ONCHIP_ADDR2(addr);
11498         REG_WR_DMAE(sc, reg, wb_write, 2);
11499 }
11500
11501 static void bnx2x_clear_func_ilt(struct bnx2x_softc *sc, uint32_t func)
11502 {
11503         uint32_t i, base = FUNC_ILT_BASE(func);
11504         for (i = base; i < base + ILT_PER_FUNC; i++) {
11505                 bnx2x_ilt_wr(sc, i, 0);
11506         }
11507 }
11508
11509 static void bnx2x_reset_func(struct bnx2x_softc *sc)
11510 {
11511         struct bnx2x_fastpath *fp;
11512         int port = SC_PORT(sc);
11513         int func = SC_FUNC(sc);
11514         int i;
11515
11516         /* Disable the function in the FW */
11517         REG_WR8(sc, BAR_XSTRORM_INTMEM + XSTORM_FUNC_EN_OFFSET(func), 0);
11518         REG_WR8(sc, BAR_CSTRORM_INTMEM + CSTORM_FUNC_EN_OFFSET(func), 0);
11519         REG_WR8(sc, BAR_TSTRORM_INTMEM + TSTORM_FUNC_EN_OFFSET(func), 0);
11520         REG_WR8(sc, BAR_USTRORM_INTMEM + USTORM_FUNC_EN_OFFSET(func), 0);
11521
11522         /* FP SBs */
11523         FOR_EACH_ETH_QUEUE(sc, i) {
11524                 fp = &sc->fp[i];
11525                 REG_WR8(sc, BAR_CSTRORM_INTMEM +
11526                         CSTORM_STATUS_BLOCK_DATA_STATE_OFFSET(fp->fw_sb_id),
11527                         SB_DISABLED);
11528         }
11529
11530         /* SP SB */
11531         REG_WR8(sc, BAR_CSTRORM_INTMEM +
11532                 CSTORM_SP_STATUS_BLOCK_DATA_STATE_OFFSET(func), SB_DISABLED);
11533
11534         for (i = 0; i < XSTORM_SPQ_DATA_SIZE / 4; i++) {
11535                 REG_WR(sc, BAR_XSTRORM_INTMEM + XSTORM_SPQ_DATA_OFFSET(func),
11536                        0);
11537         }
11538
11539         /* Configure IGU */
11540         if (sc->devinfo.int_block == INT_BLOCK_HC) {
11541                 REG_WR(sc, HC_REG_LEADING_EDGE_0 + port * 8, 0);
11542                 REG_WR(sc, HC_REG_TRAILING_EDGE_0 + port * 8, 0);
11543         } else {
11544                 REG_WR(sc, IGU_REG_LEADING_EDGE_LATCH, 0);
11545                 REG_WR(sc, IGU_REG_TRAILING_EDGE_LATCH, 0);
11546         }
11547
11548         if (CNIC_LOADED(sc)) {
11549 /* Disable Timer scan */
11550                 REG_WR(sc, TM_REG_EN_LINEAR0_TIMER + port * 4, 0);
11551 /*
11552  * Wait for at least 10ms and up to 2 second for the timers
11553  * scan to complete
11554  */
11555                 for (i = 0; i < 200; i++) {
11556                         DELAY(10000);
11557                         if (!REG_RD(sc, TM_REG_LIN0_SCAN_ON + port * 4))
11558                                 break;
11559                 }
11560         }
11561
11562         /* Clear ILT */
11563         bnx2x_clear_func_ilt(sc, func);
11564
11565         /*
11566          * Timers workaround bug for E2: if this is vnic-3,
11567          * we need to set the entire ilt range for this timers.
11568          */
11569         if (!CHIP_IS_E1x(sc) && SC_VN(sc) == 3) {
11570                 struct ilt_client_info ilt_cli;
11571 /* use dummy TM client */
11572                 memset(&ilt_cli, 0, sizeof(struct ilt_client_info));
11573                 ilt_cli.start = 0;
11574                 ilt_cli.end = ILT_NUM_PAGE_ENTRIES - 1;
11575                 ilt_cli.client_num = ILT_CLIENT_TM;
11576
11577                 ecore_ilt_boundry_init_op(sc, &ilt_cli, 0);
11578         }
11579
11580         /* this assumes that reset_port() called before reset_func() */
11581         if (!CHIP_IS_E1x(sc)) {
11582                 bnx2x_pf_disable(sc);
11583         }
11584
11585         sc->dmae_ready = 0;
11586 }
11587
11588 static void bnx2x_release_firmware(struct bnx2x_softc *sc)
11589 {
11590         rte_free(sc->init_ops);
11591         rte_free(sc->init_ops_offsets);
11592         rte_free(sc->init_data);
11593         rte_free(sc->iro_array);
11594 }
11595
11596 static int bnx2x_init_firmware(struct bnx2x_softc *sc)
11597 {
11598         uint32_t len, i;
11599         uint8_t *p = sc->firmware;
11600         uint32_t off[24];
11601
11602         for (i = 0; i < 24; ++i)
11603                 off[i] = rte_be_to_cpu_32(*((uint32_t *) sc->firmware + i));
11604
11605         len = off[0];
11606         sc->init_ops = rte_zmalloc("", len, RTE_CACHE_LINE_SIZE);
11607         if (!sc->init_ops)
11608                 goto alloc_failed;
11609         bnx2x_data_to_init_ops(p + off[1], sc->init_ops, len);
11610
11611         len = off[2];
11612         sc->init_ops_offsets = rte_zmalloc("", len, RTE_CACHE_LINE_SIZE);
11613         if (!sc->init_ops_offsets)
11614                 goto alloc_failed;
11615         bnx2x_data_to_init_offsets(p + off[3], sc->init_ops_offsets, len);
11616
11617         len = off[4];
11618         sc->init_data = rte_zmalloc("", len, RTE_CACHE_LINE_SIZE);
11619         if (!sc->init_data)
11620                 goto alloc_failed;
11621         bnx2x_data_to_init_data(p + off[5], sc->init_data, len);
11622
11623         sc->tsem_int_table_data = p + off[7];
11624         sc->tsem_pram_data = p + off[9];
11625         sc->usem_int_table_data = p + off[11];
11626         sc->usem_pram_data = p + off[13];
11627         sc->csem_int_table_data = p + off[15];
11628         sc->csem_pram_data = p + off[17];
11629         sc->xsem_int_table_data = p + off[19];
11630         sc->xsem_pram_data = p + off[21];
11631
11632         len = off[22];
11633         sc->iro_array = rte_zmalloc("", len, RTE_CACHE_LINE_SIZE);
11634         if (!sc->iro_array)
11635                 goto alloc_failed;
11636         bnx2x_data_to_iro_array(p + off[23], sc->iro_array, len);
11637
11638         return 0;
11639
11640 alloc_failed:
11641         bnx2x_release_firmware(sc);
11642         return -1;
11643 }
11644
11645 static int cut_gzip_prefix(const uint8_t * zbuf, int len)
11646 {
11647 #define MIN_PREFIX_SIZE (10)
11648
11649         int n = MIN_PREFIX_SIZE;
11650         uint16_t xlen;
11651
11652         if (!(zbuf[0] == 0x1f && zbuf[1] == 0x8b && zbuf[2] == Z_DEFLATED) ||
11653             len <= MIN_PREFIX_SIZE) {
11654                 return -1;
11655         }
11656
11657         /* optional extra fields are present */
11658         if (zbuf[3] & 0x4) {
11659                 xlen = zbuf[13];
11660                 xlen <<= 8;
11661                 xlen += zbuf[12];
11662
11663                 n += xlen;
11664         }
11665         /* file name is present */
11666         if (zbuf[3] & 0x8) {
11667                 while ((zbuf[n++] != 0) && (n < len)) ;
11668         }
11669
11670         return n;
11671 }
11672
11673 static int ecore_gunzip(struct bnx2x_softc *sc, const uint8_t * zbuf, int len)
11674 {
11675         int ret;
11676         int data_begin = cut_gzip_prefix(zbuf, len);
11677
11678         PMD_DRV_LOG(DEBUG, sc, "ecore_gunzip %d", len);
11679
11680         if (data_begin <= 0) {
11681                 PMD_DRV_LOG(NOTICE, sc, "bad gzip prefix");
11682                 return -1;
11683         }
11684
11685         memset(&zlib_stream, 0, sizeof(zlib_stream));
11686         zlib_stream.next_in = zbuf + data_begin;
11687         zlib_stream.avail_in = len - data_begin;
11688         zlib_stream.next_out = sc->gz_buf;
11689         zlib_stream.avail_out = FW_BUF_SIZE;
11690
11691         ret = inflateInit2(&zlib_stream, -MAX_WBITS);
11692         if (ret != Z_OK) {
11693                 PMD_DRV_LOG(NOTICE, sc, "zlib inflateInit2 error");
11694                 return ret;
11695         }
11696
11697         ret = inflate(&zlib_stream, Z_FINISH);
11698         if ((ret != Z_STREAM_END) && (ret != Z_OK)) {
11699                 PMD_DRV_LOG(NOTICE, sc, "zlib inflate error: %d %s", ret,
11700                             zlib_stream.msg);
11701         }
11702
11703         sc->gz_outlen = zlib_stream.total_out;
11704         if (sc->gz_outlen & 0x3) {
11705                 PMD_DRV_LOG(NOTICE, sc, "firmware is not aligned. gz_outlen == %d",
11706                             sc->gz_outlen);
11707         }
11708         sc->gz_outlen >>= 2;
11709
11710         inflateEnd(&zlib_stream);
11711
11712         if (ret == Z_STREAM_END)
11713                 return 0;
11714
11715         return ret;
11716 }
11717
11718 static void
11719 ecore_write_dmae_phys_len(struct bnx2x_softc *sc, rte_iova_t phys_addr,
11720                           uint32_t addr, uint32_t len)
11721 {
11722         bnx2x_write_dmae_phys_len(sc, phys_addr, addr, len);
11723 }
11724
11725 void
11726 ecore_storm_memset_struct(struct bnx2x_softc *sc, uint32_t addr, size_t size,
11727                           uint32_t * data)
11728 {
11729         uint8_t i;
11730         for (i = 0; i < size / 4; i++) {
11731                 REG_WR(sc, addr + (i * 4), data[i]);
11732         }
11733 }
11734
11735 static const char *get_ext_phy_type(uint32_t ext_phy_type)
11736 {
11737         uint32_t phy_type_idx = ext_phy_type >> 8;
11738         static const char *types[] =
11739             { "DIRECT", "BNX2X-8071", "BNX2X-8072", "BNX2X-8073",
11740                 "BNX2X-8705", "BNX2X-8706", "BNX2X-8726", "BNX2X-8481", "SFX-7101",
11741                 "BNX2X-8727",
11742                 "BNX2X-8727-NOC", "BNX2X-84823", "NOT_CONN", "FAILURE"
11743         };
11744
11745         if (phy_type_idx < 12)
11746                 return types[phy_type_idx];
11747         else if (PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN == ext_phy_type)
11748                 return types[12];
11749         else
11750                 return types[13];
11751 }
11752
11753 static const char *get_state(uint32_t state)
11754 {
11755         uint32_t state_idx = state >> 12;
11756         static const char *states[] = { "CLOSED", "OPENING_WAIT4_LOAD",
11757                 "OPENING_WAIT4_PORT", "OPEN", "CLOSING_WAIT4_HALT",
11758                 "CLOSING_WAIT4_DELETE", "CLOSING_WAIT4_UNLOAD",
11759                 "UNKNOWN", "UNKNOWN", "UNKNOWN", "UNKNOWN", "UNKNOWN",
11760                 "UNKNOWN", "DISABLED", "DIAG", "ERROR", "UNDEFINED"
11761         };
11762
11763         if (state_idx <= 0xF)
11764                 return states[state_idx];
11765         else
11766                 return states[0x10];
11767 }
11768
11769 static const char *get_recovery_state(uint32_t state)
11770 {
11771         static const char *states[] = { "NONE", "DONE", "INIT",
11772                 "WAIT", "FAILED", "NIC_LOADING"
11773         };
11774         return states[state];
11775 }
11776
11777 static const char *get_rx_mode(uint32_t mode)
11778 {
11779         static const char *modes[] = { "NONE", "NORMAL", "ALLMULTI",
11780                 "PROMISC", "MAX_MULTICAST", "ERROR"
11781         };
11782
11783         if (mode < 0x4)
11784                 return modes[mode];
11785         else if (BNX2X_MAX_MULTICAST == mode)
11786                 return modes[4];
11787         else
11788                 return modes[5];
11789 }
11790
11791 #define BNX2X_INFO_STR_MAX 256
11792 static const char *get_bnx2x_flags(uint32_t flags)
11793 {
11794         int i;
11795         static const char *flag[] = { "ONE_PORT ", "NO_ISCSI ",
11796                 "NO_FCOE ", "NO_WOL ", "USING_DAC ", "USING_MSIX ",
11797                 "USING_MSI ", "DISABLE_MSI ", "UNKNOWN ", "NO_MCP ",
11798                 "SAFC_TX_FLAG ", "MF_FUNC_DIS ", "TX_SWITCHING "
11799         };
11800         static char flag_str[BNX2X_INFO_STR_MAX];
11801         memset(flag_str, 0, BNX2X_INFO_STR_MAX);
11802
11803         for (i = 0; i < 5; i++)
11804                 if (flags & (1 << i)) {
11805                         strlcat(flag_str, flag[i], sizeof(flag_str));
11806                         flags ^= (1 << i);
11807                 }
11808         if (flags) {
11809                 static char unknown[BNX2X_INFO_STR_MAX];
11810                 snprintf(unknown, 32, "Unknown flag mask %x", flags);
11811                 strlcat(flag_str, unknown, sizeof(flag_str));
11812         }
11813         return flag_str;
11814 }
11815
11816 /* Prints useful adapter info. */
11817 void bnx2x_print_adapter_info(struct bnx2x_softc *sc)
11818 {
11819         int i = 0;
11820
11821         PMD_DRV_LOG(INFO, sc, "========================================");
11822         /* DPDK and Driver versions */
11823         PMD_DRV_LOG(INFO, sc, "%12s : %s", "DPDK",
11824                         rte_version());
11825         PMD_DRV_LOG(INFO, sc, "%12s : %s", "Driver",
11826                         bnx2x_pmd_version());
11827         /* Firmware versions. */
11828         PMD_DRV_LOG(INFO, sc, "%12s : %d.%d.%d",
11829                      "Firmware",
11830                      BNX2X_5710_FW_MAJOR_VERSION,
11831                      BNX2X_5710_FW_MINOR_VERSION,
11832                      BNX2X_5710_FW_REVISION_VERSION);
11833         PMD_DRV_LOG(INFO, sc, "%12s : %s",
11834                      "Bootcode", sc->devinfo.bc_ver_str);
11835         /* Hardware chip info. */
11836         PMD_DRV_LOG(INFO, sc, "%12s : %#08x", "ASIC", sc->devinfo.chip_id);
11837         PMD_DRV_LOG(INFO, sc, "%12s : %c%d", "Rev", (CHIP_REV(sc) >> 12) + 'A',
11838                      (CHIP_METAL(sc) >> 4));
11839         /* Bus PCIe info. */
11840         PMD_DRV_LOG(INFO, sc, "%12s : 0x%x", "Vendor Id",
11841                     sc->devinfo.vendor_id);
11842         PMD_DRV_LOG(INFO, sc, "%12s : 0x%x", "Device Id",
11843                     sc->devinfo.device_id);
11844         PMD_DRV_LOG(INFO, sc, "%12s : width x%d, ", "Bus PCIe",
11845                     sc->devinfo.pcie_link_width);
11846         switch (sc->devinfo.pcie_link_speed) {
11847         case 1:
11848                 PMD_DRV_LOG(INFO, sc, "%23s", "2.5 Gbps");
11849                 break;
11850         case 2:
11851                 PMD_DRV_LOG(INFO, sc, "%21s", "5 Gbps");
11852                 break;
11853         case 4:
11854                 PMD_DRV_LOG(INFO, sc, "%21s", "8 Gbps");
11855                 break;
11856         default:
11857                 PMD_DRV_LOG(INFO, sc, "%33s", "Unknown link speed");
11858         }
11859         /* Device features. */
11860         PMD_DRV_LOG(INFO, sc, "%12s : ", "Flags");
11861         /* Miscellaneous flags. */
11862         if (sc->devinfo.pcie_cap_flags & BNX2X_MSI_CAPABLE_FLAG) {
11863                 PMD_DRV_LOG(INFO, sc, "%18s", "MSI");
11864                 i++;
11865         }
11866         if (sc->devinfo.pcie_cap_flags & BNX2X_MSIX_CAPABLE_FLAG) {
11867                 if (i > 0)
11868                         PMD_DRV_LOG(INFO, sc, "|");
11869                 PMD_DRV_LOG(INFO, sc, "%20s", "MSI-X");
11870                 i++;
11871         }
11872         PMD_DRV_LOG(INFO, sc, "%12s : %s", "OVLAN", (OVLAN(sc) ? "YES" : "NO"));
11873         PMD_DRV_LOG(INFO, sc, "%12s : %s", "MF", (IS_MF(sc) ? "YES" : "NO"));
11874         PMD_DRV_LOG(INFO, sc, "========================================");
11875 }
11876
11877 /* Prints useful device info. */
11878 void bnx2x_print_device_info(struct bnx2x_softc *sc)
11879 {
11880         __rte_unused uint32_t ext_phy_type;
11881         uint32_t offset, reg_val;
11882
11883         PMD_INIT_FUNC_TRACE(sc);
11884         offset = offsetof(struct shmem_region,
11885                           dev_info.port_hw_config[0].external_phy_config);
11886         reg_val = REG_RD(sc, sc->devinfo.shmem_base + offset);
11887         if (sc->link_vars.phy_flags & PHY_XGXS_FLAG)
11888                 ext_phy_type = ELINK_XGXS_EXT_PHY_TYPE(reg_val);
11889         else
11890                 ext_phy_type = ELINK_SERDES_EXT_PHY_TYPE(reg_val);
11891
11892         /* Device features. */
11893         PMD_DRV_LOG(INFO, sc, "%12s : %u", "Bnx2x Func", sc->pcie_func);
11894         PMD_DRV_LOG(INFO, sc,
11895                     "%12s : %s", "Bnx2x Flags", get_bnx2x_flags(sc->flags));
11896         PMD_DRV_LOG(INFO, sc, "%12s : %s", "DMAE Is",
11897                      (sc->dmae_ready ? "Ready" : "Not Ready"));
11898         PMD_DRV_LOG(INFO, sc, "%12s : %u", "MTU", sc->mtu);
11899         PMD_DRV_LOG(INFO, sc,
11900                     "%12s : %s", "PHY Type", get_ext_phy_type(ext_phy_type));
11901         PMD_DRV_LOG(INFO, sc, "%12s : %x:%x:%x:%x:%x:%x", "MAC Addr",
11902                         sc->link_params.mac_addr[0],
11903                         sc->link_params.mac_addr[1],
11904                         sc->link_params.mac_addr[2],
11905                         sc->link_params.mac_addr[3],
11906                         sc->link_params.mac_addr[4],
11907                         sc->link_params.mac_addr[5]);
11908         PMD_DRV_LOG(INFO, sc, "%12s : %s", "RX Mode", get_rx_mode(sc->rx_mode));
11909         PMD_DRV_LOG(INFO, sc, "%12s : %s", "State", get_state(sc->state));
11910         if (sc->recovery_state)
11911                 PMD_DRV_LOG(INFO, sc, "%12s : %s", "Recovery",
11912                              get_recovery_state(sc->recovery_state));
11913         /* Queue info. */
11914         if (IS_PF(sc)) {
11915                 switch (sc->sp->rss_rdata.rss_mode) {
11916                 case ETH_RSS_MODE_DISABLED:
11917                         PMD_DRV_LOG(INFO, sc, "%12s : %s", "Queues", "RSS mode - None");
11918                         break;
11919                 case ETH_RSS_MODE_REGULAR:
11920                         PMD_DRV_LOG(INFO, sc, "%12s : %s,", "Queues", "RSS mode - Regular");
11921                         PMD_DRV_LOG(INFO, sc, "%16d", sc->num_queues);
11922                         break;
11923                 default:
11924                         PMD_DRV_LOG(INFO, sc, "%12s : %s", "Queues", "RSS mode - Unknown");
11925                         break;
11926                 }
11927         }
11928         PMD_DRV_LOG(INFO, sc, "%12s : CQ = %lx,  EQ = %lx", "SPQ Left",
11929                      sc->cq_spq_left, sc->eq_spq_left);
11930
11931         PMD_DRV_LOG(INFO, sc,
11932                     "%12s : %x", "Switch", sc->link_params.switch_cfg);
11933         PMD_DRV_LOG(INFO, sc, "pcie_bus=%d, pcie_device=%d",
11934                         sc->pcie_bus, sc->pcie_device);
11935         PMD_DRV_LOG(INFO, sc, "bar0.addr=%p, bar1.addr=%p",
11936                         sc->bar[BAR0].base_addr, sc->bar[BAR1].base_addr);
11937         PMD_DRV_LOG(INFO, sc, "port=%d, path=%d, vnic=%d, func=%d",
11938                         PORT_ID(sc), PATH_ID(sc), VNIC_ID(sc), FUNC_ID(sc));
11939 }