drivers/net/bnx2x/bnx2x.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright (c) 2007-2013 Broadcom Corporation.
   3  *
   4  * Eric Davis        <edavis@broadcom.com>
   5  * David Christensen <davidch@broadcom.com>
   6  * Gary Zambrano     <zambrano@broadcom.com>
   7  *
   8  * Copyright (c) 2013-2015 Brocade Communications Systems, Inc.
   9  * Copyright (c) 2015-2018 Cavium Inc.
  10  * All rights reserved.
  11  * www.cavium.com
  12  */
  13
  14 #define BNX2X_DRIVER_VERSION "1.78.18"
  15
  16 #include "bnx2x.h"
  17 #include "bnx2x_vfpf.h"
  18 #include "ecore_sp.h"
  19 #include "ecore_init.h"
  20 #include "ecore_init_ops.h"
  21
  22 #include "rte_version.h"
  23
  24 #include <sys/types.h>
  25 #include <sys/stat.h>
  26 #include <fcntl.h>
  27 #include <zlib.h>
  28 #include <rte_string_fns.h>
  29
  30 #define BNX2X_PMD_VER_PREFIX "BNX2X PMD"
  31 #define BNX2X_PMD_VERSION_MAJOR 1
  32 #define BNX2X_PMD_VERSION_MINOR 1
  33 #define BNX2X_PMD_VERSION_REVISION 0
  34 #define BNX2X_PMD_VERSION_PATCH 1
  35
  36 static inline const char *
  37 bnx2x_pmd_version(void)
  38 {
  39         static char version[32];
  40
  41         snprintf(version, sizeof(version), "%s %s_%d.%d.%d.%d",
  42                         BNX2X_PMD_VER_PREFIX,
  43                         BNX2X_DRIVER_VERSION,
  44                         BNX2X_PMD_VERSION_MAJOR,
  45                         BNX2X_PMD_VERSION_MINOR,
  46                         BNX2X_PMD_VERSION_REVISION,
  47                         BNX2X_PMD_VERSION_PATCH);
  48
  49         return version;
  50 }
  51
  52 static z_stream zlib_stream;
  53
  54 #define EVL_VLID_MASK 0x0FFF
  55
  56 #define BNX2X_DEF_SB_ATT_IDX 0x0001
  57 #define BNX2X_DEF_SB_IDX     0x0002
  58
  59 /*
  60  * FLR Support - bnx2x_pf_flr_clnup() is called during nic_load in the per
  61  * function HW initialization.
  62  */
  63 #define FLR_WAIT_USEC     10000 /* 10 msecs */
  64 #define FLR_WAIT_INTERVAL 50    /* usecs */
  65 #define FLR_POLL_CNT      (FLR_WAIT_USEC / FLR_WAIT_INTERVAL)   /* 200 */
  66
  67 struct pbf_pN_buf_regs {
  68         int pN;
  69         uint32_t init_crd;
  70         uint32_t crd;
  71         uint32_t crd_freed;
  72 };
  73
  74 struct pbf_pN_cmd_regs {
  75         int pN;
  76         uint32_t lines_occup;
  77         uint32_t lines_freed;
  78 };
  79
  80 /* resources needed for unloading a previously loaded device */
  81
  82 #define BNX2X_PREV_WAIT_NEEDED 1
  83 rte_spinlock_t bnx2x_prev_mtx;
  84 struct bnx2x_prev_list_node {
  85         LIST_ENTRY(bnx2x_prev_list_node) node;
  86         uint8_t bus;
  87         uint8_t slot;
  88         uint8_t path;
  89         uint8_t aer;
  90         uint8_t undi;
  91 };
  92
  93 static LIST_HEAD(, bnx2x_prev_list_node) bnx2x_prev_list
  94         = LIST_HEAD_INITIALIZER(bnx2x_prev_list);
  95
  96 static int load_count[2][3] = { { 0 } };
  97         /* per-path: 0-common, 1-port0, 2-port1 */
  98
  99 static void bnx2x_cmng_fns_init(struct bnx2x_softc *sc, uint8_t read_cfg,
 100                                 uint8_t cmng_type);
 101 static int bnx2x_get_cmng_fns_mode(struct bnx2x_softc *sc);
 102 static void storm_memset_cmng(struct bnx2x_softc *sc, struct cmng_init *cmng,
 103                               uint8_t port);
 104 static void bnx2x_set_reset_global(struct bnx2x_softc *sc);
 105 static void bnx2x_set_reset_in_progress(struct bnx2x_softc *sc);
 106 static uint8_t bnx2x_reset_is_done(struct bnx2x_softc *sc, int engine);
 107 static uint8_t bnx2x_clear_pf_load(struct bnx2x_softc *sc);
 108 static uint8_t bnx2x_chk_parity_attn(struct bnx2x_softc *sc, uint8_t * global,
 109                                      uint8_t print);
 110 static void bnx2x_int_disable(struct bnx2x_softc *sc);
 111 static int bnx2x_release_leader_lock(struct bnx2x_softc *sc);
 112 static void bnx2x_pf_disable(struct bnx2x_softc *sc);
 113 static void bnx2x_update_rx_prod(struct bnx2x_softc *sc,
 114                                  struct bnx2x_fastpath *fp,
 115                                  uint16_t rx_bd_prod, uint16_t rx_cq_prod);
 116 static void bnx2x_link_report_locked(struct bnx2x_softc *sc);
 117 static void bnx2x_link_report(struct bnx2x_softc *sc);
 118 void bnx2x_link_status_update(struct bnx2x_softc *sc);
 119 static int bnx2x_alloc_mem(struct bnx2x_softc *sc);
 120 static void bnx2x_free_mem(struct bnx2x_softc *sc);
 121 static int bnx2x_alloc_fw_stats_mem(struct bnx2x_softc *sc);
 122 static void bnx2x_free_fw_stats_mem(struct bnx2x_softc *sc);
 123 static __rte_noinline
 124 int bnx2x_nic_load(struct bnx2x_softc *sc);
 125
 126 static int bnx2x_handle_sp_tq(struct bnx2x_softc *sc);
 127 static void bnx2x_handle_fp_tq(struct bnx2x_fastpath *fp);
 128 static void bnx2x_ack_sb(struct bnx2x_softc *sc, uint8_t igu_sb_id,
 129                          uint8_t storm, uint16_t index, uint8_t op,
 130                          uint8_t update);
 131
 132 int bnx2x_test_bit(int nr, volatile unsigned long *addr)
 133 {
 134         int res;
 135
 136         mb();
 137         res = ((*addr) & (1UL << nr)) != 0;
 138         mb();
 139         return res;
 140 }
 141
 142 void bnx2x_set_bit(unsigned int nr, volatile unsigned long *addr)
 143 {
 144         __sync_fetch_and_or(addr, (1UL << nr));
 145 }
 146
 147 void bnx2x_clear_bit(int nr, volatile unsigned long *addr)
 148 {
 149         __sync_fetch_and_and(addr, ~(1UL << nr));
 150 }
 151
 152 int bnx2x_test_and_clear_bit(int nr, volatile unsigned long *addr)
 153 {
 154         unsigned long mask = (1UL << nr);
 155         return __sync_fetch_and_and(addr, ~mask) & mask;
 156 }
 157
 158 int bnx2x_cmpxchg(volatile int *addr, int old, int new)
 159 {
 160         return __sync_val_compare_and_swap(addr, old, new);
 161 }
 162
 163 int
 164 bnx2x_dma_alloc(struct bnx2x_softc *sc, size_t size, struct bnx2x_dma *dma,
 165               const char *msg, uint32_t align)
 166 {
 167         char mz_name[RTE_MEMZONE_NAMESIZE];
 168         const struct rte_memzone *z;
 169
 170         dma->sc = sc;
 171         if (IS_PF(sc))
 172                 snprintf(mz_name, sizeof(mz_name), "bnx2x%d_%s_%" PRIx64, SC_ABS_FUNC(sc), msg,
 173                         rte_get_timer_cycles());
 174         else
 175                 snprintf(mz_name, sizeof(mz_name), "bnx2x%d_%s_%" PRIx64, sc->pcie_device, msg,
 176                         rte_get_timer_cycles());
 177
 178         /* Caller must take care that strlen(mz_name) < RTE_MEMZONE_NAMESIZE */
 179         z = rte_memzone_reserve_aligned(mz_name, (uint64_t)size,
 180                                         SOCKET_ID_ANY,
 181                                         RTE_MEMZONE_IOVA_CONTIG, align);
 182         if (z == NULL) {
 183                 PMD_DRV_LOG(ERR, sc, "DMA alloc failed for %s", msg);
 184                 return -ENOMEM;
 185         }
 186         dma->paddr = (uint64_t) z->iova;
 187         dma->vaddr = z->addr;
 188         dma->mzone = (const void *)z;
 189
 190         PMD_DRV_LOG(DEBUG, sc,
 191                     "%s: virt=%p phys=%" PRIx64, msg, dma->vaddr, dma->paddr);
 192
 193         return 0;
 194 }
 195
 196 void bnx2x_dma_free(struct bnx2x_dma *dma)
 197 {
 198         if (dma->mzone == NULL)
 199                 return;
 200
 201         rte_memzone_free((const struct rte_memzone *)dma->mzone);
 202         dma->sc = NULL;
 203         dma->paddr = 0;
 204         dma->vaddr = NULL;
 205         dma->nseg = 0;
 206         dma->mzone = NULL;
 207 }
 208
 209 static int bnx2x_acquire_hw_lock(struct bnx2x_softc *sc, uint32_t resource)
 210 {
 211         uint32_t lock_status;
 212         uint32_t resource_bit = (1 << resource);
 213         int func = SC_FUNC(sc);
 214         uint32_t hw_lock_control_reg;
 215         int cnt;
 216
 217 #ifndef RTE_LIBRTE_BNX2X_DEBUG_PERIODIC
 218         if (resource)
 219                 PMD_INIT_FUNC_TRACE(sc);
 220 #else
 221         PMD_INIT_FUNC_TRACE(sc);
 222 #endif
 223
 224         /* validate the resource is within range */
 225         if (resource > HW_LOCK_MAX_RESOURCE_VALUE) {
 226                 PMD_DRV_LOG(NOTICE, sc,
 227                             "resource 0x%x > HW_LOCK_MAX_RESOURCE_VALUE",
 228                             resource);
 229                 return -1;
 230         }
 231
 232         if (func <= 5) {
 233                 hw_lock_control_reg = (MISC_REG_DRIVER_CONTROL_1 + (func * 8));
 234         } else {
 235                 hw_lock_control_reg =
 236                     (MISC_REG_DRIVER_CONTROL_7 + ((func - 6) * 8));
 237         }
 238
 239         /* validate the resource is not already taken */
 240         lock_status = REG_RD(sc, hw_lock_control_reg);
 241         if (lock_status & resource_bit) {
 242                 PMD_DRV_LOG(NOTICE, sc,
 243                             "resource in use (status 0x%x bit 0x%x)",
 244                             lock_status, resource_bit);
 245                 return -1;
 246         }
 247
 248         /* try every 5ms for 5 seconds */
 249         for (cnt = 0; cnt < 1000; cnt++) {
 250                 REG_WR(sc, (hw_lock_control_reg + 4), resource_bit);
 251                 lock_status = REG_RD(sc, hw_lock_control_reg);
 252                 if (lock_status & resource_bit) {
 253                         return 0;
 254                 }
 255                 DELAY(5000);
 256         }
 257
 258         PMD_DRV_LOG(NOTICE, sc, "Resource 0x%x resource_bit 0x%x lock timeout!",
 259                     resource, resource_bit);
 260         return -1;
 261 }
 262
 263 static int bnx2x_release_hw_lock(struct bnx2x_softc *sc, uint32_t resource)
 264 {
 265         uint32_t lock_status;
 266         uint32_t resource_bit = (1 << resource);
 267         int func = SC_FUNC(sc);
 268         uint32_t hw_lock_control_reg;
 269
 270 #ifndef RTE_LIBRTE_BNX2X_DEBUG_PERIODIC
 271         if (resource)
 272                 PMD_INIT_FUNC_TRACE(sc);
 273 #else
 274         PMD_INIT_FUNC_TRACE(sc);
 275 #endif
 276
 277         /* validate the resource is within range */
 278         if (resource > HW_LOCK_MAX_RESOURCE_VALUE) {
 279                 PMD_DRV_LOG(NOTICE, sc,
 280                             "(resource 0x%x > HW_LOCK_MAX_RESOURCE_VALUE)"
 281                             " resource_bit 0x%x", resource, resource_bit);
 282                 return -1;
 283         }
 284
 285         if (func <= 5) {
 286                 hw_lock_control_reg = (MISC_REG_DRIVER_CONTROL_1 + (func * 8));
 287         } else {
 288                 hw_lock_control_reg =
 289                     (MISC_REG_DRIVER_CONTROL_7 + ((func - 6) * 8));
 290         }
 291
 292         /* validate the resource is currently taken */
 293         lock_status = REG_RD(sc, hw_lock_control_reg);
 294         if (!(lock_status & resource_bit)) {
 295                 PMD_DRV_LOG(NOTICE, sc,
 296                             "resource not in use (status 0x%x bit 0x%x)",
 297                             lock_status, resource_bit);
 298                 return -1;
 299         }
 300
 301         REG_WR(sc, hw_lock_control_reg, resource_bit);
 302         return 0;
 303 }
 304
 305 static void bnx2x_acquire_phy_lock(struct bnx2x_softc *sc)
 306 {
 307         BNX2X_PHY_LOCK(sc);
 308         bnx2x_acquire_hw_lock(sc, HW_LOCK_RESOURCE_MDIO);
 309 }
 310
 311 static void bnx2x_release_phy_lock(struct bnx2x_softc *sc)
 312 {
 313         bnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_MDIO);
 314         BNX2X_PHY_UNLOCK(sc);
 315 }
 316
 317 /* copy command into DMAE command memory and set DMAE command Go */
 318 void bnx2x_post_dmae(struct bnx2x_softc *sc, struct dmae_command *dmae, int idx)
 319 {
 320         uint32_t cmd_offset;
 321         uint32_t i;
 322
 323         cmd_offset = (DMAE_REG_CMD_MEM + (sizeof(struct dmae_command) * idx));
 324         for (i = 0; i < ((sizeof(struct dmae_command) / 4)); i++) {
 325                 REG_WR(sc, (cmd_offset + (i * 4)), *(((uint32_t *) dmae) + i));
 326         }
 327
 328         REG_WR(sc, dmae_reg_go_c[idx], 1);
 329 }
 330
 331 uint32_t bnx2x_dmae_opcode_add_comp(uint32_t opcode, uint8_t comp_type)
 332 {
 333         return opcode | ((comp_type << DMAE_COMMAND_C_DST_SHIFT) |
 334                           DMAE_COMMAND_C_TYPE_ENABLE);
 335 }
 336
 337 uint32_t bnx2x_dmae_opcode_clr_src_reset(uint32_t opcode)
 338 {
 339         return opcode & ~DMAE_COMMAND_SRC_RESET;
 340 }
 341
 342 uint32_t
 343 bnx2x_dmae_opcode(struct bnx2x_softc * sc, uint8_t src_type, uint8_t dst_type,
 344                 uint8_t with_comp, uint8_t comp_type)
 345 {
 346         uint32_t opcode = 0;
 347
 348         opcode |= ((src_type << DMAE_COMMAND_SRC_SHIFT) |
 349                    (dst_type << DMAE_COMMAND_DST_SHIFT));
 350
 351         opcode |= (DMAE_COMMAND_SRC_RESET | DMAE_COMMAND_DST_RESET);
 352
 353         opcode |= (SC_PORT(sc) ? DMAE_CMD_PORT_1 : DMAE_CMD_PORT_0);
 354
 355         opcode |= ((SC_VN(sc) << DMAE_COMMAND_E1HVN_SHIFT) |
 356                    (SC_VN(sc) << DMAE_COMMAND_DST_VN_SHIFT));
 357
 358         opcode |= (DMAE_COM_SET_ERR << DMAE_COMMAND_ERR_POLICY_SHIFT);
 359
 360 #ifdef __BIG_ENDIAN
 361         opcode |= DMAE_CMD_ENDIANITY_B_DW_SWAP;
 362 #else
 363         opcode |= DMAE_CMD_ENDIANITY_DW_SWAP;
 364 #endif
 365
 366         if (with_comp) {
 367                 opcode = bnx2x_dmae_opcode_add_comp(opcode, comp_type);
 368         }
 369
 370         return opcode;
 371 }
 372
 373 static void
 374 bnx2x_prep_dmae_with_comp(struct bnx2x_softc *sc, struct dmae_command *dmae,
 375                         uint8_t src_type, uint8_t dst_type)
 376 {
 377         memset(dmae, 0, sizeof(struct dmae_command));
 378
 379         /* set the opcode */
 380         dmae->opcode = bnx2x_dmae_opcode(sc, src_type, dst_type,
 381                                        TRUE, DMAE_COMP_PCI);
 382
 383         /* fill in the completion parameters */
 384         dmae->comp_addr_lo = U64_LO(BNX2X_SP_MAPPING(sc, wb_comp));
 385         dmae->comp_addr_hi = U64_HI(BNX2X_SP_MAPPING(sc, wb_comp));
 386         dmae->comp_val = DMAE_COMP_VAL;
 387 }
 388
 389 /* issue a DMAE command over the init channel and wait for completion */
 390 static int
 391 bnx2x_issue_dmae_with_comp(struct bnx2x_softc *sc, struct dmae_command *dmae)
 392 {
 393         uint32_t *wb_comp = BNX2X_SP(sc, wb_comp);
 394         int timeout = CHIP_REV_IS_SLOW(sc) ? 400000 : 4000;
 395
 396         /* reset completion */
 397         *wb_comp = 0;
 398
 399         /* post the command on the channel used for initializations */
 400         bnx2x_post_dmae(sc, dmae, INIT_DMAE_C(sc));
 401
 402         /* wait for completion */
 403         DELAY(500);
 404
 405         while ((*wb_comp & ~DMAE_PCI_ERR_FLAG) != DMAE_COMP_VAL) {
 406                 if (!timeout ||
 407                     (sc->recovery_state != BNX2X_RECOVERY_DONE &&
 408                      sc->recovery_state != BNX2X_RECOVERY_NIC_LOADING)) {
 409                         PMD_DRV_LOG(INFO, sc, "DMAE timeout!");
 410                         return DMAE_TIMEOUT;
 411                 }
 412
 413                 timeout--;
 414                 DELAY(50);
 415         }
 416
 417         if (*wb_comp & DMAE_PCI_ERR_FLAG) {
 418                 PMD_DRV_LOG(INFO, sc, "DMAE PCI error!");
 419                 return DMAE_PCI_ERROR;
 420         }
 421
 422         return 0;
 423 }
 424
 425 void bnx2x_read_dmae(struct bnx2x_softc *sc, uint32_t src_addr, uint32_t len32)
 426 {
 427         struct dmae_command dmae;
 428         uint32_t *data;
 429         uint32_t i;
 430         int rc;
 431
 432         if (!sc->dmae_ready) {
 433                 data = BNX2X_SP(sc, wb_data[0]);
 434
 435                 for (i = 0; i < len32; i++) {
 436                         data[i] = REG_RD(sc, (src_addr + (i * 4)));
 437                 }
 438
 439                 return;
 440         }
 441
 442         /* set opcode and fixed command fields */
 443         bnx2x_prep_dmae_with_comp(sc, &dmae, DMAE_SRC_GRC, DMAE_DST_PCI);
 444
 445         /* fill in addresses and len */
 446         dmae.src_addr_lo = (src_addr >> 2);     /* GRC addr has dword resolution */
 447         dmae.src_addr_hi = 0;
 448         dmae.dst_addr_lo = U64_LO(BNX2X_SP_MAPPING(sc, wb_data));
 449         dmae.dst_addr_hi = U64_HI(BNX2X_SP_MAPPING(sc, wb_data));
 450         dmae.len = len32;
 451
 452         /* issue the command and wait for completion */
 453         if ((rc = bnx2x_issue_dmae_with_comp(sc, &dmae)) != 0) {
 454                 rte_panic("DMAE failed (%d)", rc);
 455         };
 456 }
 457
 458 void
 459 bnx2x_write_dmae(struct bnx2x_softc *sc, rte_iova_t dma_addr, uint32_t dst_addr,
 460                uint32_t len32)
 461 {
 462         struct dmae_command dmae;
 463         int rc;
 464
 465         if (!sc->dmae_ready) {
 466                 ecore_init_str_wr(sc, dst_addr, BNX2X_SP(sc, wb_data[0]), len32);
 467                 return;
 468         }
 469
 470         /* set opcode and fixed command fields */
 471         bnx2x_prep_dmae_with_comp(sc, &dmae, DMAE_SRC_PCI, DMAE_DST_GRC);
 472
 473         /* fill in addresses and len */
 474         dmae.src_addr_lo = U64_LO(dma_addr);
 475         dmae.src_addr_hi = U64_HI(dma_addr);
 476         dmae.dst_addr_lo = (dst_addr >> 2);     /* GRC addr has dword resolution */
 477         dmae.dst_addr_hi = 0;
 478         dmae.len = len32;
 479
 480         /* issue the command and wait for completion */
 481         if ((rc = bnx2x_issue_dmae_with_comp(sc, &dmae)) != 0) {
 482                 rte_panic("DMAE failed (%d)", rc);
 483         }
 484 }
 485
 486 static void
 487 bnx2x_write_dmae_phys_len(struct bnx2x_softc *sc, rte_iova_t phys_addr,
 488                         uint32_t addr, uint32_t len)
 489 {
 490         uint32_t dmae_wr_max = DMAE_LEN32_WR_MAX(sc);
 491         uint32_t offset = 0;
 492
 493         while (len > dmae_wr_max) {
 494                 bnx2x_write_dmae(sc, (phys_addr + offset),      /* src DMA address */
 495                                (addr + offset), /* dst GRC address */
 496                                dmae_wr_max);
 497                 offset += (dmae_wr_max * 4);
 498                 len -= dmae_wr_max;
 499         }
 500
 501         bnx2x_write_dmae(sc, (phys_addr + offset),      /* src DMA address */
 502                        (addr + offset), /* dst GRC address */
 503                        len);
 504 }
 505
 506 void
 507 bnx2x_set_ctx_validation(struct bnx2x_softc *sc, struct eth_context *cxt,
 508                        uint32_t cid)
 509 {
 510         /* ustorm cxt validation */
 511         cxt->ustorm_ag_context.cdu_usage =
 512             CDU_RSRVD_VALUE_TYPE_A(HW_CID(sc, cid),
 513                                    CDU_REGION_NUMBER_UCM_AG,
 514                                    ETH_CONNECTION_TYPE);
 515         /* xcontext validation */
 516         cxt->xstorm_ag_context.cdu_reserved =
 517             CDU_RSRVD_VALUE_TYPE_A(HW_CID(sc, cid),
 518                                    CDU_REGION_NUMBER_XCM_AG,
 519                                    ETH_CONNECTION_TYPE);
 520 }
 521
 522 static void
 523 bnx2x_storm_memset_hc_timeout(struct bnx2x_softc *sc, uint8_t fw_sb_id,
 524                             uint8_t sb_index, uint8_t ticks)
 525 {
 526         uint32_t addr =
 527             (BAR_CSTRORM_INTMEM +
 528              CSTORM_STATUS_BLOCK_DATA_TIMEOUT_OFFSET(fw_sb_id, sb_index));
 529
 530         REG_WR8(sc, addr, ticks);
 531 }
 532
 533 static void
 534 bnx2x_storm_memset_hc_disable(struct bnx2x_softc *sc, uint16_t fw_sb_id,
 535                             uint8_t sb_index, uint8_t disable)
 536 {
 537         uint32_t enable_flag =
 538             (disable) ? 0 : (1 << HC_INDEX_DATA_HC_ENABLED_SHIFT);
 539         uint32_t addr =
 540             (BAR_CSTRORM_INTMEM +
 541              CSTORM_STATUS_BLOCK_DATA_FLAGS_OFFSET(fw_sb_id, sb_index));
 542         uint8_t flags;
 543
 544         /* clear and set */
 545         flags = REG_RD8(sc, addr);
 546         flags &= ~HC_INDEX_DATA_HC_ENABLED;
 547         flags |= enable_flag;
 548         REG_WR8(sc, addr, flags);
 549 }
 550
 551 void
 552 bnx2x_update_coalesce_sb_index(struct bnx2x_softc *sc, uint8_t fw_sb_id,
 553                              uint8_t sb_index, uint8_t disable, uint16_t usec)
 554 {
 555         uint8_t ticks = (usec / 4);
 556
 557         bnx2x_storm_memset_hc_timeout(sc, fw_sb_id, sb_index, ticks);
 558
 559         disable = (disable) ? 1 : ((usec) ? 0 : 1);
 560         bnx2x_storm_memset_hc_disable(sc, fw_sb_id, sb_index, disable);
 561 }
 562
 563 uint32_t elink_cb_reg_read(struct bnx2x_softc *sc, uint32_t reg_addr)
 564 {
 565         return REG_RD(sc, reg_addr);
 566 }
 567
 568 void elink_cb_reg_write(struct bnx2x_softc *sc, uint32_t reg_addr, uint32_t val)
 569 {
 570         REG_WR(sc, reg_addr, val);
 571 }
 572
 573 void
 574 elink_cb_event_log(__rte_unused struct bnx2x_softc *sc,
 575                    __rte_unused const elink_log_id_t elink_log_id, ...)
 576 {
 577         PMD_DRV_LOG(DEBUG, sc, "ELINK EVENT LOG (%d)", elink_log_id);
 578 }
 579
 580 static int bnx2x_set_spio(struct bnx2x_softc *sc, int spio, uint32_t mode)
 581 {
 582         uint32_t spio_reg;
 583
 584         /* Only 2 SPIOs are configurable */
 585         if ((spio != MISC_SPIO_SPIO4) && (spio != MISC_SPIO_SPIO5)) {
 586                 PMD_DRV_LOG(NOTICE, sc, "Invalid SPIO 0x%x", spio);
 587                 return -1;
 588         }
 589
 590         bnx2x_acquire_hw_lock(sc, HW_LOCK_RESOURCE_SPIO);
 591
 592         /* read SPIO and mask except the float bits */
 593         spio_reg = (REG_RD(sc, MISC_REG_SPIO) & MISC_SPIO_FLOAT);
 594
 595         switch (mode) {
 596         case MISC_SPIO_OUTPUT_LOW:
 597                 /* clear FLOAT and set CLR */
 598                 spio_reg &= ~(spio << MISC_SPIO_FLOAT_POS);
 599                 spio_reg |= (spio << MISC_SPIO_CLR_POS);
 600                 break;
 601
 602         case MISC_SPIO_OUTPUT_HIGH:
 603                 /* clear FLOAT and set SET */
 604                 spio_reg &= ~(spio << MISC_SPIO_FLOAT_POS);
 605                 spio_reg |= (spio << MISC_SPIO_SET_POS);
 606                 break;
 607
 608         case MISC_SPIO_INPUT_HI_Z:
 609                 /* set FLOAT */
 610                 spio_reg |= (spio << MISC_SPIO_FLOAT_POS);
 611                 break;
 612
 613         default:
 614                 break;
 615         }
 616
 617         REG_WR(sc, MISC_REG_SPIO, spio_reg);
 618         bnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_SPIO);
 619
 620         return 0;
 621 }
 622
 623 static int bnx2x_gpio_read(struct bnx2x_softc *sc, int gpio_num, uint8_t port)
 624 {
 625         /* The GPIO should be swapped if swap register is set and active */
 626         int gpio_port = ((REG_RD(sc, NIG_REG_PORT_SWAP) &&
 627                           REG_RD(sc, NIG_REG_STRAP_OVERRIDE)) ^ port);
 628         int gpio_shift = gpio_num;
 629         if (gpio_port)
 630                 gpio_shift += MISC_REGISTERS_GPIO_PORT_SHIFT;
 631
 632         uint32_t gpio_mask = (1 << gpio_shift);
 633         uint32_t gpio_reg;
 634
 635         if (gpio_num > MISC_REGISTERS_GPIO_3) {
 636                 PMD_DRV_LOG(NOTICE, sc, "Invalid GPIO %d", gpio_num);
 637                 return -1;
 638         }
 639
 640         /* read GPIO value */
 641         gpio_reg = REG_RD(sc, MISC_REG_GPIO);
 642
 643         /* get the requested pin value */
 644         return ((gpio_reg & gpio_mask) == gpio_mask) ? 1 : 0;
 645 }
 646
 647 static int
 648 bnx2x_gpio_write(struct bnx2x_softc *sc, int gpio_num, uint32_t mode, uint8_t port)
 649 {
 650         /* The GPIO should be swapped if swap register is set and active */
 651         int gpio_port = ((REG_RD(sc, NIG_REG_PORT_SWAP) &&
 652                           REG_RD(sc, NIG_REG_STRAP_OVERRIDE)) ^ port);
 653         int gpio_shift = gpio_num;
 654         if (gpio_port)
 655                 gpio_shift += MISC_REGISTERS_GPIO_PORT_SHIFT;
 656
 657         uint32_t gpio_mask = (1 << gpio_shift);
 658         uint32_t gpio_reg;
 659
 660         if (gpio_num > MISC_REGISTERS_GPIO_3) {
 661                 PMD_DRV_LOG(NOTICE, sc, "Invalid GPIO %d", gpio_num);
 662                 return -1;
 663         }
 664
 665         bnx2x_acquire_hw_lock(sc, HW_LOCK_RESOURCE_GPIO);
 666
 667         /* read GPIO and mask except the float bits */
 668         gpio_reg = (REG_RD(sc, MISC_REG_GPIO) & MISC_REGISTERS_GPIO_FLOAT);
 669
 670         switch (mode) {
 671         case MISC_REGISTERS_GPIO_OUTPUT_LOW:
 672                 /* clear FLOAT and set CLR */
 673                 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS);
 674                 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_CLR_POS);
 675                 break;
 676
 677         case MISC_REGISTERS_GPIO_OUTPUT_HIGH:
 678                 /* clear FLOAT and set SET */
 679                 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS);
 680                 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_SET_POS);
 681                 break;
 682
 683         case MISC_REGISTERS_GPIO_INPUT_HI_Z:
 684                 /* set FLOAT */
 685                 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS);
 686                 break;
 687
 688         default:
 689                 break;
 690         }
 691
 692         REG_WR(sc, MISC_REG_GPIO, gpio_reg);
 693         bnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_GPIO);
 694
 695         return 0;
 696 }
 697
 698 static int
 699 bnx2x_gpio_mult_write(struct bnx2x_softc *sc, uint8_t pins, uint32_t mode)
 700 {
 701         uint32_t gpio_reg;
 702
 703         /* any port swapping should be handled by caller */
 704
 705         bnx2x_acquire_hw_lock(sc, HW_LOCK_RESOURCE_GPIO);
 706
 707         /* read GPIO and mask except the float bits */
 708         gpio_reg = REG_RD(sc, MISC_REG_GPIO);
 709         gpio_reg &= ~(pins << MISC_REGISTERS_GPIO_FLOAT_POS);
 710         gpio_reg &= ~(pins << MISC_REGISTERS_GPIO_CLR_POS);
 711         gpio_reg &= ~(pins << MISC_REGISTERS_GPIO_SET_POS);
 712
 713         switch (mode) {
 714         case MISC_REGISTERS_GPIO_OUTPUT_LOW:
 715                 /* set CLR */
 716                 gpio_reg |= (pins << MISC_REGISTERS_GPIO_CLR_POS);
 717                 break;
 718
 719         case MISC_REGISTERS_GPIO_OUTPUT_HIGH:
 720                 /* set SET */
 721                 gpio_reg |= (pins << MISC_REGISTERS_GPIO_SET_POS);
 722                 break;
 723
 724         case MISC_REGISTERS_GPIO_INPUT_HI_Z:
 725                 /* set FLOAT */
 726                 gpio_reg |= (pins << MISC_REGISTERS_GPIO_FLOAT_POS);
 727                 break;
 728
 729         default:
 730                 PMD_DRV_LOG(NOTICE, sc,
 731                             "Invalid GPIO mode assignment %d", mode);
 732                 bnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_GPIO);
 733                 return -1;
 734         }
 735
 736         REG_WR(sc, MISC_REG_GPIO, gpio_reg);
 737         bnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_GPIO);
 738
 739         return 0;
 740 }
 741
 742 static int
 743 bnx2x_gpio_int_write(struct bnx2x_softc *sc, int gpio_num, uint32_t mode,
 744                    uint8_t port)
 745 {
 746         /* The GPIO should be swapped if swap register is set and active */
 747         int gpio_port = ((REG_RD(sc, NIG_REG_PORT_SWAP) &&
 748                           REG_RD(sc, NIG_REG_STRAP_OVERRIDE)) ^ port);
 749         int gpio_shift = gpio_num;
 750         if (gpio_port)
 751                 gpio_shift += MISC_REGISTERS_GPIO_PORT_SHIFT;
 752
 753         uint32_t gpio_mask = (1 << gpio_shift);
 754         uint32_t gpio_reg;
 755
 756         if (gpio_num > MISC_REGISTERS_GPIO_3) {
 757                 PMD_DRV_LOG(NOTICE, sc, "Invalid GPIO %d", gpio_num);
 758                 return -1;
 759         }
 760
 761         bnx2x_acquire_hw_lock(sc, HW_LOCK_RESOURCE_GPIO);
 762
 763         /* read GPIO int */
 764         gpio_reg = REG_RD(sc, MISC_REG_GPIO_INT);
 765
 766         switch (mode) {
 767         case MISC_REGISTERS_GPIO_INT_OUTPUT_CLR:
 768                 /* clear SET and set CLR */
 769                 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_INT_SET_POS);
 770                 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_INT_CLR_POS);
 771                 break;
 772
 773         case MISC_REGISTERS_GPIO_INT_OUTPUT_SET:
 774                 /* clear CLR and set SET */
 775                 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_INT_CLR_POS);
 776                 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_INT_SET_POS);
 777                 break;
 778
 779         default:
 780                 break;
 781         }
 782
 783         REG_WR(sc, MISC_REG_GPIO_INT, gpio_reg);
 784         bnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_GPIO);
 785
 786         return 0;
 787 }
 788
 789 uint32_t
 790 elink_cb_gpio_read(struct bnx2x_softc * sc, uint16_t gpio_num, uint8_t port)
 791 {
 792         return bnx2x_gpio_read(sc, gpio_num, port);
 793 }
 794
 795 uint8_t elink_cb_gpio_write(struct bnx2x_softc * sc, uint16_t gpio_num, uint8_t mode,   /* 0=low 1=high */
 796                             uint8_t port)
 797 {
 798         return bnx2x_gpio_write(sc, gpio_num, mode, port);
 799 }
 800
 801 uint8_t
 802 elink_cb_gpio_mult_write(struct bnx2x_softc * sc, uint8_t pins,
 803                          uint8_t mode /* 0=low 1=high */ )
 804 {
 805         return bnx2x_gpio_mult_write(sc, pins, mode);
 806 }
 807
 808 uint8_t elink_cb_gpio_int_write(struct bnx2x_softc * sc, uint16_t gpio_num, uint8_t mode,       /* 0=low 1=high */
 809                                 uint8_t port)
 810 {
 811         return bnx2x_gpio_int_write(sc, gpio_num, mode, port);
 812 }
 813
 814 void elink_cb_notify_link_changed(struct bnx2x_softc *sc)
 815 {
 816         REG_WR(sc, (MISC_REG_AEU_GENERAL_ATTN_12 +
 817                     (SC_FUNC(sc) * sizeof(uint32_t))), 1);
 818 }
 819
 820 /* send the MCP a request, block until there is a reply */
 821 uint32_t
 822 elink_cb_fw_command(struct bnx2x_softc *sc, uint32_t command, uint32_t param)
 823 {
 824         int mb_idx = SC_FW_MB_IDX(sc);
 825         uint32_t seq;
 826         uint32_t rc = 0;
 827         uint32_t cnt = 1;
 828         uint8_t delay = CHIP_REV_IS_SLOW(sc) ? 100 : 10;
 829
 830         seq = ++sc->fw_seq;
 831         SHMEM_WR(sc, func_mb[mb_idx].drv_mb_param, param);
 832         SHMEM_WR(sc, func_mb[mb_idx].drv_mb_header, (command | seq));
 833
 834         PMD_DRV_LOG(DEBUG, sc,
 835                     "wrote command 0x%08x to FW MB param 0x%08x",
 836                     (command | seq), param);
 837
 838         /* Let the FW do it's magic. GIve it up to 5 seconds... */
 839         do {
 840                 DELAY(delay * 1000);
 841                 rc = SHMEM_RD(sc, func_mb[mb_idx].fw_mb_header);
 842         } while ((seq != (rc & FW_MSG_SEQ_NUMBER_MASK)) && (cnt++ < 500));
 843
 844         /* is this a reply to our command? */
 845         if (seq == (rc & FW_MSG_SEQ_NUMBER_MASK)) {
 846                 rc &= FW_MSG_CODE_MASK;
 847         } else {
 848                 /* Ruh-roh! */
 849                 PMD_DRV_LOG(NOTICE, sc, "FW failed to respond!");
 850                 rc = 0;
 851         }
 852
 853         return rc;
 854 }
 855
 856 static uint32_t
 857 bnx2x_fw_command(struct bnx2x_softc *sc, uint32_t command, uint32_t param)
 858 {
 859         return elink_cb_fw_command(sc, command, param);
 860 }
 861
 862 static void
 863 __storm_memset_dma_mapping(struct bnx2x_softc *sc, uint32_t addr,
 864                            rte_iova_t mapping)
 865 {
 866         REG_WR(sc, addr, U64_LO(mapping));
 867         REG_WR(sc, (addr + 4), U64_HI(mapping));
 868 }
 869
 870 static void
 871 storm_memset_spq_addr(struct bnx2x_softc *sc, rte_iova_t mapping,
 872                       uint16_t abs_fid)
 873 {
 874         uint32_t addr = (XSEM_REG_FAST_MEMORY +
 875                          XSTORM_SPQ_PAGE_BASE_OFFSET(abs_fid));
 876         __storm_memset_dma_mapping(sc, addr, mapping);
 877 }
 878
 879 static void
 880 storm_memset_vf_to_pf(struct bnx2x_softc *sc, uint16_t abs_fid, uint16_t pf_id)
 881 {
 882         REG_WR8(sc, (BAR_XSTRORM_INTMEM + XSTORM_VF_TO_PF_OFFSET(abs_fid)),
 883                 pf_id);
 884         REG_WR8(sc, (BAR_CSTRORM_INTMEM + CSTORM_VF_TO_PF_OFFSET(abs_fid)),
 885                 pf_id);
 886         REG_WR8(sc, (BAR_TSTRORM_INTMEM + TSTORM_VF_TO_PF_OFFSET(abs_fid)),
 887                 pf_id);
 888         REG_WR8(sc, (BAR_USTRORM_INTMEM + USTORM_VF_TO_PF_OFFSET(abs_fid)),
 889                 pf_id);
 890 }
 891
 892 static void
 893 storm_memset_func_en(struct bnx2x_softc *sc, uint16_t abs_fid, uint8_t enable)
 894 {
 895         REG_WR8(sc, (BAR_XSTRORM_INTMEM + XSTORM_FUNC_EN_OFFSET(abs_fid)),
 896                 enable);
 897         REG_WR8(sc, (BAR_CSTRORM_INTMEM + CSTORM_FUNC_EN_OFFSET(abs_fid)),
 898                 enable);
 899         REG_WR8(sc, (BAR_TSTRORM_INTMEM + TSTORM_FUNC_EN_OFFSET(abs_fid)),
 900                 enable);
 901         REG_WR8(sc, (BAR_USTRORM_INTMEM + USTORM_FUNC_EN_OFFSET(abs_fid)),
 902                 enable);
 903 }
 904
 905 static void
 906 storm_memset_eq_data(struct bnx2x_softc *sc, struct event_ring_data *eq_data,
 907                      uint16_t pfid)
 908 {
 909         uint32_t addr;
 910         size_t size;
 911
 912         addr = (BAR_CSTRORM_INTMEM + CSTORM_EVENT_RING_DATA_OFFSET(pfid));
 913         size = sizeof(struct event_ring_data);
 914         ecore_storm_memset_struct(sc, addr, size, (uint32_t *) eq_data);
 915 }
 916
 917 static void
 918 storm_memset_eq_prod(struct bnx2x_softc *sc, uint16_t eq_prod, uint16_t pfid)
 919 {
 920         uint32_t addr = (BAR_CSTRORM_INTMEM +
 921                          CSTORM_EVENT_RING_PROD_OFFSET(pfid));
 922         REG_WR16(sc, addr, eq_prod);
 923 }
 924
 925 /*
 926  * Post a slowpath command.
 927  *
 928  * A slowpath command is used to propagate a configuration change through
 929  * the controller in a controlled manner, allowing each STORM processor and
 930  * other H/W blocks to phase in the change.  The commands sent on the
 931  * slowpath are referred to as ramrods.  Depending on the ramrod used the
 932  * completion of the ramrod will occur in different ways.  Here's a
 933  * breakdown of ramrods and how they complete:
 934  *
 935  * RAMROD_CMD_ID_ETH_PORT_SETUP
 936  *   Used to setup the leading connection on a port.  Completes on the
 937  *   Receive Completion Queue (RCQ) of that port (typically fp[0]).
 938  *
 939  * RAMROD_CMD_ID_ETH_CLIENT_SETUP
 940  *   Used to setup an additional connection on a port.  Completes on the
 941  *   RCQ of the multi-queue/RSS connection being initialized.
 942  *
 943  * RAMROD_CMD_ID_ETH_STAT_QUERY
 944  *   Used to force the storm processors to update the statistics database
 945  *   in host memory.  This ramrod is send on the leading connection CID and
 946  *   completes as an index increment of the CSTORM on the default status
 947  *   block.
 948  *
 949  * RAMROD_CMD_ID_ETH_UPDATE
 950  *   Used to update the state of the leading connection, usually to udpate
 951  *   the RSS indirection table.  Completes on the RCQ of the leading
 952  *   connection. (Not currently used under FreeBSD until OS support becomes
 953  *   available.)
 954  *
 955  * RAMROD_CMD_ID_ETH_HALT
 956  *   Used when tearing down a connection prior to driver unload.  Completes
 957  *   on the RCQ of the multi-queue/RSS connection being torn down.  Don't
 958  *   use this on the leading connection.
 959  *
 960  * RAMROD_CMD_ID_ETH_SET_MAC
 961  *   Sets the Unicast/Broadcast/Multicast used by the port.  Completes on
 962  *   the RCQ of the leading connection.
 963  *
 964  * RAMROD_CMD_ID_ETH_CFC_DEL
 965  *   Used when tearing down a conneciton prior to driver unload.  Completes
 966  *   on the RCQ of the leading connection (since the current connection
 967  *   has been completely removed from controller memory).
 968  *
 969  * RAMROD_CMD_ID_ETH_PORT_DEL
 970  *   Used to tear down the leading connection prior to driver unload,
 971  *   typically fp[0].  Completes as an index increment of the CSTORM on the
 972  *   default status block.
 973  *
 974  * RAMROD_CMD_ID_ETH_FORWARD_SETUP
 975  *   Used for connection offload.  Completes on the RCQ of the multi-queue
 976  *   RSS connection that is being offloaded.  (Not currently used under
 977  *   FreeBSD.)
 978  *
 979  * There can only be one command pending per function.
 980  *
 981  * Returns:
 982  *   0 = Success, !0 = Failure.
 983  */
 984
 985 /* must be called under the spq lock */
 986 static inline struct eth_spe *bnx2x_sp_get_next(struct bnx2x_softc *sc)
 987 {
 988         struct eth_spe *next_spe = sc->spq_prod_bd;
 989
 990         if (sc->spq_prod_bd == sc->spq_last_bd) {
 991                 /* wrap back to the first eth_spq */
 992                 sc->spq_prod_bd = sc->spq;
 993                 sc->spq_prod_idx = 0;
 994         } else {
 995                 sc->spq_prod_bd++;
 996                 sc->spq_prod_idx++;
 997         }
 998
 999         return next_spe;
1000 }
1001
1002 /* must be called under the spq lock */
1003 static void bnx2x_sp_prod_update(struct bnx2x_softc *sc)
1004 {
1005         int func = SC_FUNC(sc);
1006
1007         /*
1008          * Make sure that BD data is updated before writing the producer.
1009          * BD data is written to the memory, the producer is read from the
1010          * memory, thus we need a full memory barrier to ensure the ordering.
1011          */
1012         mb();
1013
1014         REG_WR16(sc, (BAR_XSTRORM_INTMEM + XSTORM_SPQ_PROD_OFFSET(func)),
1015                  sc->spq_prod_idx);
1016
1017         mb();
1018 }
1019
1020 /**
1021  * bnx2x_is_contextless_ramrod - check if the current command ends on EQ
1022  *
1023  * @cmd:      command to check
1024  * @cmd_type: command type
1025  */
1026 static int bnx2x_is_contextless_ramrod(int cmd, int cmd_type)
1027 {
1028         if ((cmd_type == NONE_CONNECTION_TYPE) ||
1029             (cmd == RAMROD_CMD_ID_ETH_FORWARD_SETUP) ||
1030             (cmd == RAMROD_CMD_ID_ETH_CLASSIFICATION_RULES) ||
1031             (cmd == RAMROD_CMD_ID_ETH_FILTER_RULES) ||
1032             (cmd == RAMROD_CMD_ID_ETH_MULTICAST_RULES) ||
1033             (cmd == RAMROD_CMD_ID_ETH_SET_MAC) ||
1034             (cmd == RAMROD_CMD_ID_ETH_RSS_UPDATE)) {
1035                 return TRUE;
1036         } else {
1037                 return FALSE;
1038         }
1039 }
1040
1041 /**
1042  * bnx2x_sp_post - place a single command on an SP ring
1043  *
1044  * @sc:         driver handle
1045  * @command:    command to place (e.g. SETUP, FILTER_RULES, etc.)
1046  * @cid:        SW CID the command is related to
1047  * @data_hi:    command private data address (high 32 bits)
1048  * @data_lo:    command private data address (low 32 bits)
1049  * @cmd_type:   command type (e.g. NONE, ETH)
1050  *
1051  * SP data is handled as if it's always an address pair, thus data fields are
1052  * not swapped to little endian in upper functions. Instead this function swaps
1053  * data as if it's two uint32 fields.
1054  */
1055 int
1056 bnx2x_sp_post(struct bnx2x_softc *sc, int command, int cid, uint32_t data_hi,
1057             uint32_t data_lo, int cmd_type)
1058 {
1059         struct eth_spe *spe;
1060         uint16_t type;
1061         int common;
1062
1063         common = bnx2x_is_contextless_ramrod(command, cmd_type);
1064
1065         if (common) {
1066                 if (!atomic_load_acq_long(&sc->eq_spq_left)) {
1067                         PMD_DRV_LOG(INFO, sc, "EQ ring is full!");
1068                         return -1;
1069                 }
1070         } else {
1071                 if (!atomic_load_acq_long(&sc->cq_spq_left)) {
1072                         PMD_DRV_LOG(INFO, sc, "SPQ ring is full!");
1073                         return -1;
1074                 }
1075         }
1076
1077         spe = bnx2x_sp_get_next(sc);
1078
1079         /* CID needs port number to be encoded int it */
1080         spe->hdr.conn_and_cmd_data =
1081             htole32((command << SPE_HDR_CMD_ID_SHIFT) | HW_CID(sc, cid));
1082
1083         type = (cmd_type << SPE_HDR_CONN_TYPE_SHIFT) & SPE_HDR_CONN_TYPE;
1084
1085         /* TBD: Check if it works for VFs */
1086         type |= ((SC_FUNC(sc) << SPE_HDR_FUNCTION_ID_SHIFT) &
1087                  SPE_HDR_FUNCTION_ID);
1088
1089         spe->hdr.type = htole16(type);
1090
1091         spe->data.update_data_addr.hi = htole32(data_hi);
1092         spe->data.update_data_addr.lo = htole32(data_lo);
1093
1094         /*
1095          * It's ok if the actual decrement is issued towards the memory
1096          * somewhere between the lock and unlock. Thus no more explict
1097          * memory barrier is needed.
1098          */
1099         if (common) {
1100                 atomic_subtract_acq_long(&sc->eq_spq_left, 1);
1101         } else {
1102                 atomic_subtract_acq_long(&sc->cq_spq_left, 1);
1103         }
1104
1105         PMD_DRV_LOG(DEBUG, sc,
1106                     "SPQE[%x] (%x:%x) (cmd, common?) (%d,%d) hw_cid %x"
1107                     "data (%x:%x) type(0x%x) left (CQ, EQ) (%lx,%lx)",
1108                     sc->spq_prod_idx,
1109                     (uint32_t) U64_HI(sc->spq_dma.paddr),
1110                     (uint32_t) (U64_LO(sc->spq_dma.paddr) +
1111                                 (uint8_t *) sc->spq_prod_bd -
1112                                 (uint8_t *) sc->spq), command, common,
1113                     HW_CID(sc, cid), data_hi, data_lo, type,
1114                     atomic_load_acq_long(&sc->cq_spq_left),
1115                     atomic_load_acq_long(&sc->eq_spq_left));
1116
1117         /* RAMROD completion is processed in bnx2x_intr_legacy()
1118          * which can run from different contexts.
1119          * Ask bnx2x_intr_intr() to process RAMROD
1120          * completion whenever it gets scheduled.
1121          */
1122         rte_atomic32_set(&sc->scan_fp, 1);
1123         bnx2x_sp_prod_update(sc);
1124
1125         return 0;
1126 }
1127
1128 static void bnx2x_drv_pulse(struct bnx2x_softc *sc)
1129 {
1130         SHMEM_WR(sc, func_mb[SC_FW_MB_IDX(sc)].drv_pulse_mb,
1131                  sc->fw_drv_pulse_wr_seq);
1132 }
1133
1134 static int bnx2x_tx_queue_has_work(const struct bnx2x_fastpath *fp)
1135 {
1136         uint16_t hw_cons;
1137         struct bnx2x_tx_queue *txq = fp->sc->tx_queues[fp->index];
1138
1139         if (unlikely(!txq)) {
1140                 PMD_TX_LOG(ERR, "ERROR: TX queue is NULL");
1141                 return 0;
1142         }
1143
1144         mb();                   /* status block fields can change */
1145         hw_cons = le16toh(*fp->tx_cons_sb);
1146         return hw_cons != txq->tx_pkt_head;
1147 }
1148
1149 static uint8_t bnx2x_has_tx_work(struct bnx2x_fastpath *fp)
1150 {
1151         /* expand this for multi-cos if ever supported */
1152         return bnx2x_tx_queue_has_work(fp);
1153 }
1154
1155 static int bnx2x_has_rx_work(struct bnx2x_fastpath *fp)
1156 {
1157         uint16_t rx_cq_cons_sb;
1158         struct bnx2x_rx_queue *rxq;
1159         rxq = fp->sc->rx_queues[fp->index];
1160         if (unlikely(!rxq)) {
1161                 PMD_RX_LOG(ERR, "ERROR: RX queue is NULL");
1162                 return 0;
1163         }
1164
1165         mb();                   /* status block fields can change */
1166         rx_cq_cons_sb = le16toh(*fp->rx_cq_cons_sb);
1167         if (unlikely((rx_cq_cons_sb & MAX_RCQ_ENTRIES(rxq)) ==
1168                      MAX_RCQ_ENTRIES(rxq)))
1169                 rx_cq_cons_sb++;
1170
1171         PMD_RX_LOG(DEBUG, "hw CQ cons = %d, sw CQ cons = %d",
1172                    rx_cq_cons_sb, rxq->rx_cq_head);
1173
1174         return rxq->rx_cq_head != rx_cq_cons_sb;
1175 }
1176
1177 static void
1178 bnx2x_sp_event(struct bnx2x_softc *sc, struct bnx2x_fastpath *fp,
1179              union eth_rx_cqe *rr_cqe)
1180 {
1181         int cid = SW_CID(rr_cqe->ramrod_cqe.conn_and_cmd_data);
1182         int command = CQE_CMD(rr_cqe->ramrod_cqe.conn_and_cmd_data);
1183         enum ecore_queue_cmd drv_cmd = ECORE_Q_CMD_MAX;
1184         struct ecore_queue_sp_obj *q_obj = &BNX2X_SP_OBJ(sc, fp).q_obj;
1185
1186         PMD_DRV_LOG(DEBUG, sc,
1187                     "fp=%d cid=%d got ramrod #%d state is %x type is %d",
1188                     fp->index, cid, command, sc->state,
1189                     rr_cqe->ramrod_cqe.ramrod_type);
1190
1191         switch (command) {
1192         case (RAMROD_CMD_ID_ETH_CLIENT_UPDATE):
1193                 PMD_DRV_LOG(DEBUG, sc, "got UPDATE ramrod. CID %d", cid);
1194                 drv_cmd = ECORE_Q_CMD_UPDATE;
1195                 break;
1196
1197         case (RAMROD_CMD_ID_ETH_CLIENT_SETUP):
1198                 PMD_DRV_LOG(DEBUG, sc, "got MULTI[%d] setup ramrod", cid);
1199                 drv_cmd = ECORE_Q_CMD_SETUP;
1200                 break;
1201
1202         case (RAMROD_CMD_ID_ETH_TX_QUEUE_SETUP):
1203                 PMD_DRV_LOG(DEBUG, sc,
1204                             "got MULTI[%d] tx-only setup ramrod", cid);
1205                 drv_cmd = ECORE_Q_CMD_SETUP_TX_ONLY;
1206                 break;
1207
1208         case (RAMROD_CMD_ID_ETH_HALT):
1209                 PMD_DRV_LOG(DEBUG, sc, "got MULTI[%d] halt ramrod", cid);
1210                 drv_cmd = ECORE_Q_CMD_HALT;
1211                 break;
1212
1213         case (RAMROD_CMD_ID_ETH_TERMINATE):
1214                 PMD_DRV_LOG(DEBUG, sc, "got MULTI[%d] teminate ramrod", cid);
1215                 drv_cmd = ECORE_Q_CMD_TERMINATE;
1216                 break;
1217
1218         case (RAMROD_CMD_ID_ETH_EMPTY):
1219                 PMD_DRV_LOG(DEBUG, sc, "got MULTI[%d] empty ramrod", cid);
1220                 drv_cmd = ECORE_Q_CMD_EMPTY;
1221                 break;
1222
1223         default:
1224                 PMD_DRV_LOG(DEBUG, sc,
1225                             "ERROR: unexpected MC reply (%d)"
1226                             "on fp[%d]", command, fp->index);
1227                 return;
1228         }
1229
1230         if ((drv_cmd != ECORE_Q_CMD_MAX) &&
1231             q_obj->complete_cmd(sc, q_obj, drv_cmd)) {
1232                 /*
1233                  * q_obj->complete_cmd() failure means that this was
1234                  * an unexpected completion.
1235                  *
1236                  * In this case we don't want to increase the sc->spq_left
1237                  * because apparently we haven't sent this command the first
1238                  * place.
1239                  */
1240                 // rte_panic("Unexpected SP completion");
1241                 return;
1242         }
1243
1244         atomic_add_acq_long(&sc->cq_spq_left, 1);
1245
1246         PMD_DRV_LOG(DEBUG, sc, "sc->cq_spq_left 0x%lx",
1247                     atomic_load_acq_long(&sc->cq_spq_left));
1248 }
1249
1250 static uint8_t bnx2x_rxeof(struct bnx2x_softc *sc, struct bnx2x_fastpath *fp)
1251 {
1252         struct bnx2x_rx_queue *rxq;
1253         uint16_t bd_cons, bd_prod, bd_prod_fw, comp_ring_cons;
1254         uint16_t hw_cq_cons, sw_cq_cons, sw_cq_prod;
1255
1256         rte_spinlock_lock(&(fp)->rx_mtx);
1257
1258         rxq = sc->rx_queues[fp->index];
1259         if (!rxq) {
1260                 PMD_RX_LOG(ERR, "RX queue %d is NULL", fp->index);
1261                 rte_spinlock_unlock(&(fp)->rx_mtx);
1262                 return 0;
1263         }
1264
1265         /* CQ "next element" is of the size of the regular element */
1266         hw_cq_cons = le16toh(*fp->rx_cq_cons_sb);
1267         if (unlikely((hw_cq_cons & USABLE_RCQ_ENTRIES_PER_PAGE) ==
1268                      USABLE_RCQ_ENTRIES_PER_PAGE)) {
1269                 hw_cq_cons++;
1270         }
1271
1272         bd_cons = rxq->rx_bd_head;
1273         bd_prod = rxq->rx_bd_tail;
1274         bd_prod_fw = bd_prod;
1275         sw_cq_cons = rxq->rx_cq_head;
1276         sw_cq_prod = rxq->rx_cq_tail;
1277
1278         /*
1279          * Memory barrier necessary as speculative reads of the rx
1280          * buffer can be ahead of the index in the status block
1281          */
1282         rmb();
1283
1284         while (sw_cq_cons != hw_cq_cons) {
1285                 union eth_rx_cqe *cqe;
1286                 struct eth_fast_path_rx_cqe *cqe_fp;
1287                 uint8_t cqe_fp_flags;
1288                 enum eth_rx_cqe_type cqe_fp_type;
1289
1290                 comp_ring_cons = RCQ_ENTRY(sw_cq_cons, rxq);
1291                 bd_prod = RX_BD(bd_prod, rxq);
1292                 bd_cons = RX_BD(bd_cons, rxq);
1293
1294                 cqe = &rxq->cq_ring[comp_ring_cons];
1295                 cqe_fp = &cqe->fast_path_cqe;
1296                 cqe_fp_flags = cqe_fp->type_error_flags;
1297                 cqe_fp_type = cqe_fp_flags & ETH_FAST_PATH_RX_CQE_TYPE;
1298
1299                 /* is this a slowpath msg? */
1300                 if (CQE_TYPE_SLOW(cqe_fp_type)) {
1301                         bnx2x_sp_event(sc, fp, cqe);
1302                         goto next_cqe;
1303                 }
1304
1305                 /* is this an error packet? */
1306                 if (unlikely(cqe_fp_flags &
1307                              ETH_FAST_PATH_RX_CQE_PHY_DECODE_ERR_FLG)) {
1308                         PMD_RX_LOG(DEBUG, "flags 0x%x rx packet %u",
1309                                    cqe_fp_flags, sw_cq_cons);
1310                         goto next_rx;
1311                 }
1312
1313                 PMD_RX_LOG(DEBUG, "Dropping fastpath called from attn poller!");
1314
1315 next_rx:
1316                 bd_cons = NEXT_RX_BD(bd_cons);
1317                 bd_prod = NEXT_RX_BD(bd_prod);
1318                 bd_prod_fw = NEXT_RX_BD(bd_prod_fw);
1319
1320 next_cqe:
1321                 sw_cq_prod = NEXT_RCQ_IDX(sw_cq_prod);
1322                 sw_cq_cons = NEXT_RCQ_IDX(sw_cq_cons);
1323
1324         }                       /* while work to do */
1325
1326         rxq->rx_bd_head = bd_cons;
1327         rxq->rx_bd_tail = bd_prod_fw;
1328         rxq->rx_cq_head = sw_cq_cons;
1329         rxq->rx_cq_tail = sw_cq_prod;
1330
1331         PMD_RX_LOG(DEBUG, "BD prod = %d, sw CQ prod = %d",
1332                    bd_prod_fw, sw_cq_prod);
1333
1334         /* Update producers */
1335         bnx2x_update_rx_prod(sc, fp, bd_prod_fw, sw_cq_prod);
1336
1337         rte_spinlock_unlock(&(fp)->rx_mtx);
1338
1339         return sw_cq_cons != hw_cq_cons;
1340 }
1341
1342 static uint16_t
1343 bnx2x_free_tx_pkt(__rte_unused struct bnx2x_fastpath *fp, struct bnx2x_tx_queue *txq,
1344                 uint16_t pkt_idx, uint16_t bd_idx)
1345 {
1346         struct eth_tx_start_bd *tx_start_bd =
1347             &txq->tx_ring[TX_BD(bd_idx, txq)].start_bd;
1348         uint16_t nbd = rte_le_to_cpu_16(tx_start_bd->nbd);
1349         struct rte_mbuf *tx_mbuf = txq->sw_ring[TX_BD(pkt_idx, txq)];
1350
1351         if (likely(tx_mbuf != NULL)) {
1352                 rte_pktmbuf_free_seg(tx_mbuf);
1353         } else {
1354                 PMD_RX_LOG(ERR, "fp[%02d] lost mbuf %lu",
1355                            fp->index, (unsigned long)TX_BD(pkt_idx, txq));
1356         }
1357
1358         txq->sw_ring[TX_BD(pkt_idx, txq)] = NULL;
1359         txq->nb_tx_avail += nbd;
1360
1361         while (nbd--)
1362                 bd_idx = NEXT_TX_BD(bd_idx);
1363
1364         return bd_idx;
1365 }
1366
1367 /* processes transmit completions */
1368 uint8_t bnx2x_txeof(__rte_unused struct bnx2x_softc * sc, struct bnx2x_fastpath * fp)
1369 {
1370         uint16_t bd_cons, hw_cons, sw_cons;
1371         __rte_unused uint16_t tx_bd_avail;
1372
1373         struct bnx2x_tx_queue *txq = fp->sc->tx_queues[fp->index];
1374
1375         if (unlikely(!txq)) {
1376                 PMD_TX_LOG(ERR, "ERROR: TX queue is NULL");
1377                 return 0;
1378         }
1379
1380         bd_cons = txq->tx_bd_head;
1381         hw_cons = rte_le_to_cpu_16(*fp->tx_cons_sb);
1382         sw_cons = txq->tx_pkt_head;
1383
1384         while (sw_cons != hw_cons) {
1385                 bd_cons = bnx2x_free_tx_pkt(fp, txq, sw_cons, bd_cons);
1386                 sw_cons++;
1387         }
1388
1389         txq->tx_pkt_head = sw_cons;
1390         txq->tx_bd_head = bd_cons;
1391
1392         tx_bd_avail = txq->nb_tx_avail;
1393
1394         PMD_TX_LOG(DEBUG, "fp[%02d] avail=%u cons_sb=%u, "
1395                    "pkt_head=%u pkt_tail=%u bd_head=%u bd_tail=%u",
1396                    fp->index, tx_bd_avail, hw_cons,
1397                    txq->tx_pkt_head, txq->tx_pkt_tail,
1398                    txq->tx_bd_head, txq->tx_bd_tail);
1399         return TRUE;
1400 }
1401
1402 static void bnx2x_drain_tx_queues(struct bnx2x_softc *sc)
1403 {
1404         struct bnx2x_fastpath *fp;
1405         int i, count;
1406
1407         /* wait until all TX fastpath tasks have completed */
1408         for (i = 0; i < sc->num_queues; i++) {
1409                 fp = &sc->fp[i];
1410
1411                 count = 1000;
1412
1413                 while (bnx2x_has_tx_work(fp)) {
1414                         bnx2x_txeof(sc, fp);
1415
1416                         if (count == 0) {
1417                                 PMD_TX_LOG(ERR,
1418                                            "Timeout waiting for fp[%d] "
1419                                            "transmits to complete!", i);
1420                                 rte_panic("tx drain failure");
1421                                 return;
1422                         }
1423
1424                         count--;
1425                         DELAY(1000);
1426                         rmb();
1427                 }
1428         }
1429
1430         return;
1431 }
1432
1433 static int
1434 bnx2x_del_all_macs(struct bnx2x_softc *sc, struct ecore_vlan_mac_obj *mac_obj,
1435                  int mac_type, uint8_t wait_for_comp)
1436 {
1437         unsigned long ramrod_flags = 0, vlan_mac_flags = 0;
1438         int rc;
1439
1440         /* wait for completion of requested */
1441         if (wait_for_comp) {
1442                 bnx2x_set_bit(RAMROD_COMP_WAIT, &ramrod_flags);
1443         }
1444
1445         /* Set the mac type of addresses we want to clear */
1446         bnx2x_set_bit(mac_type, &vlan_mac_flags);
1447
1448         rc = mac_obj->delete_all(sc, mac_obj, &vlan_mac_flags, &ramrod_flags);
1449         if (rc < 0)
1450                 PMD_DRV_LOG(ERR, sc, "Failed to delete MACs (%d)", rc);
1451
1452         return rc;
1453 }
1454
1455 static int
1456 bnx2x_fill_accept_flags(struct bnx2x_softc *sc, uint32_t rx_mode,
1457                         unsigned long *rx_accept_flags,
1458                         unsigned long *tx_accept_flags)
1459 {
1460         /* Clear the flags first */
1461         *rx_accept_flags = 0;
1462         *tx_accept_flags = 0;
1463
1464         switch (rx_mode) {
1465         case BNX2X_RX_MODE_NONE:
1466                 /*
1467                  * 'drop all' supersedes any accept flags that may have been
1468                  * passed to the function.
1469                  */
1470                 break;
1471
1472         case BNX2X_RX_MODE_NORMAL:
1473                 bnx2x_set_bit(ECORE_ACCEPT_UNICAST, rx_accept_flags);
1474                 bnx2x_set_bit(ECORE_ACCEPT_MULTICAST, rx_accept_flags);
1475                 bnx2x_set_bit(ECORE_ACCEPT_BROADCAST, rx_accept_flags);
1476
1477                 /* internal switching mode */
1478                 bnx2x_set_bit(ECORE_ACCEPT_UNICAST, tx_accept_flags);
1479                 bnx2x_set_bit(ECORE_ACCEPT_MULTICAST, tx_accept_flags);
1480                 bnx2x_set_bit(ECORE_ACCEPT_BROADCAST, tx_accept_flags);
1481
1482                 break;
1483
1484         case BNX2X_RX_MODE_ALLMULTI:
1485                 bnx2x_set_bit(ECORE_ACCEPT_UNICAST, rx_accept_flags);
1486                 bnx2x_set_bit(ECORE_ACCEPT_ALL_MULTICAST, rx_accept_flags);
1487                 bnx2x_set_bit(ECORE_ACCEPT_BROADCAST, rx_accept_flags);
1488
1489                 /* internal switching mode */
1490                 bnx2x_set_bit(ECORE_ACCEPT_UNICAST, tx_accept_flags);
1491                 bnx2x_set_bit(ECORE_ACCEPT_ALL_MULTICAST, tx_accept_flags);
1492                 bnx2x_set_bit(ECORE_ACCEPT_BROADCAST, tx_accept_flags);
1493
1494                 break;
1495
1496         case BNX2X_RX_MODE_ALLMULTI_PROMISC:
1497         case BNX2X_RX_MODE_PROMISC:
1498                 /*
1499                  * According to deffinition of SI mode, iface in promisc mode
1500                  * should receive matched and unmatched (in resolution of port)
1501                  * unicast packets.
1502                  */
1503                 bnx2x_set_bit(ECORE_ACCEPT_UNMATCHED, rx_accept_flags);
1504                 bnx2x_set_bit(ECORE_ACCEPT_UNICAST, rx_accept_flags);
1505                 bnx2x_set_bit(ECORE_ACCEPT_ALL_MULTICAST, rx_accept_flags);
1506                 bnx2x_set_bit(ECORE_ACCEPT_BROADCAST, rx_accept_flags);
1507
1508                 /* internal switching mode */
1509                 bnx2x_set_bit(ECORE_ACCEPT_ALL_MULTICAST, tx_accept_flags);
1510                 bnx2x_set_bit(ECORE_ACCEPT_BROADCAST, tx_accept_flags);
1511
1512                 if (IS_MF_SI(sc)) {
1513                         bnx2x_set_bit(ECORE_ACCEPT_ALL_UNICAST, tx_accept_flags);
1514                 } else {
1515                         bnx2x_set_bit(ECORE_ACCEPT_UNICAST, tx_accept_flags);
1516                 }
1517
1518                 break;
1519
1520         default:
1521                 PMD_RX_LOG(ERR, "Unknown rx_mode (%d)", rx_mode);
1522                 return -1;
1523         }
1524
1525         /* Set ACCEPT_ANY_VLAN as we do not enable filtering by VLAN */
1526         if (rx_mode != BNX2X_RX_MODE_NONE) {
1527                 bnx2x_set_bit(ECORE_ACCEPT_ANY_VLAN, rx_accept_flags);
1528                 bnx2x_set_bit(ECORE_ACCEPT_ANY_VLAN, tx_accept_flags);
1529         }
1530
1531         return 0;
1532 }
1533
1534 static int
1535 bnx2x_set_q_rx_mode(struct bnx2x_softc *sc, uint8_t cl_id,
1536                   unsigned long rx_mode_flags,
1537                   unsigned long rx_accept_flags,
1538                   unsigned long tx_accept_flags, unsigned long ramrod_flags)
1539 {
1540         struct ecore_rx_mode_ramrod_params ramrod_param;
1541         int rc;
1542
1543         memset(&ramrod_param, 0, sizeof(ramrod_param));
1544
1545         /* Prepare ramrod parameters */
1546         ramrod_param.cid = 0;
1547         ramrod_param.cl_id = cl_id;
1548         ramrod_param.rx_mode_obj = &sc->rx_mode_obj;
1549         ramrod_param.func_id = SC_FUNC(sc);
1550
1551         ramrod_param.pstate = &sc->sp_state;
1552         ramrod_param.state = ECORE_FILTER_RX_MODE_PENDING;
1553
1554         ramrod_param.rdata = BNX2X_SP(sc, rx_mode_rdata);
1555         ramrod_param.rdata_mapping =
1556             (rte_iova_t)BNX2X_SP_MAPPING(sc, rx_mode_rdata),
1557             bnx2x_set_bit(ECORE_FILTER_RX_MODE_PENDING, &sc->sp_state);
1558
1559         ramrod_param.ramrod_flags = ramrod_flags;
1560         ramrod_param.rx_mode_flags = rx_mode_flags;
1561
1562         ramrod_param.rx_accept_flags = rx_accept_flags;
1563         ramrod_param.tx_accept_flags = tx_accept_flags;
1564
1565         rc = ecore_config_rx_mode(sc, &ramrod_param);
1566         if (rc < 0) {
1567                 PMD_RX_LOG(ERR, "Set rx_mode %d failed", sc->rx_mode);
1568                 return rc;
1569         }
1570
1571         return 0;
1572 }
1573
1574 int bnx2x_set_storm_rx_mode(struct bnx2x_softc *sc)
1575 {
1576         unsigned long rx_mode_flags = 0, ramrod_flags = 0;
1577         unsigned long rx_accept_flags = 0, tx_accept_flags = 0;
1578         int rc;
1579
1580         rc = bnx2x_fill_accept_flags(sc, sc->rx_mode, &rx_accept_flags,
1581                                    &tx_accept_flags);
1582         if (rc) {
1583                 return rc;
1584         }
1585
1586         bnx2x_set_bit(RAMROD_RX, &ramrod_flags);
1587         bnx2x_set_bit(RAMROD_TX, &ramrod_flags);
1588         bnx2x_set_bit(RAMROD_COMP_WAIT, &ramrod_flags);
1589
1590         return bnx2x_set_q_rx_mode(sc, sc->fp[0].cl_id, rx_mode_flags,
1591                                  rx_accept_flags, tx_accept_flags,
1592                                  ramrod_flags);
1593 }
1594
1595 /* returns the "mcp load_code" according to global load_count array */
1596 static int bnx2x_nic_load_no_mcp(struct bnx2x_softc *sc)
1597 {
1598         int path = SC_PATH(sc);
1599         int port = SC_PORT(sc);
1600
1601         PMD_DRV_LOG(INFO, sc, "NO MCP - load counts[%d]      %d, %d, %d",
1602                     path, load_count[path][0], load_count[path][1],
1603                     load_count[path][2]);
1604
1605         load_count[path][0]++;
1606         load_count[path][1 + port]++;
1607         PMD_DRV_LOG(INFO, sc, "NO MCP - new load counts[%d]  %d, %d, %d",
1608                     path, load_count[path][0], load_count[path][1],
1609                     load_count[path][2]);
1610         if (load_count[path][0] == 1)
1611                 return FW_MSG_CODE_DRV_LOAD_COMMON;
1612         else if (load_count[path][1 + port] == 1)
1613                 return FW_MSG_CODE_DRV_LOAD_PORT;
1614         else
1615                 return FW_MSG_CODE_DRV_LOAD_FUNCTION;
1616 }
1617
1618 /* returns the "mcp load_code" according to global load_count array */
1619 static int bnx2x_nic_unload_no_mcp(struct bnx2x_softc *sc)
1620 {
1621         int port = SC_PORT(sc);
1622         int path = SC_PATH(sc);
1623
1624         PMD_DRV_LOG(INFO, sc, "NO MCP - load counts[%d]      %d, %d, %d",
1625                     path, load_count[path][0], load_count[path][1],
1626                     load_count[path][2]);
1627         load_count[path][0]--;
1628         load_count[path][1 + port]--;
1629         PMD_DRV_LOG(INFO, sc, "NO MCP - new load counts[%d]  %d, %d, %d",
1630                     path, load_count[path][0], load_count[path][1],
1631                     load_count[path][2]);
1632         if (load_count[path][0] == 0) {
1633                 return FW_MSG_CODE_DRV_UNLOAD_COMMON;
1634         } else if (load_count[path][1 + port] == 0) {
1635                 return FW_MSG_CODE_DRV_UNLOAD_PORT;
1636         } else {
1637                 return FW_MSG_CODE_DRV_UNLOAD_FUNCTION;
1638         }
1639 }
1640
1641 /* request unload mode from the MCP: COMMON, PORT or FUNCTION */
1642 static uint32_t bnx2x_send_unload_req(struct bnx2x_softc *sc, int unload_mode)
1643 {
1644         uint32_t reset_code = 0;
1645
1646         /* Select the UNLOAD request mode */
1647         if (unload_mode == UNLOAD_NORMAL) {
1648                 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS;
1649         } else {
1650                 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS;
1651         }
1652
1653         /* Send the request to the MCP */
1654         if (!BNX2X_NOMCP(sc)) {
1655                 reset_code = bnx2x_fw_command(sc, reset_code, 0);
1656         } else {
1657                 reset_code = bnx2x_nic_unload_no_mcp(sc);
1658         }
1659
1660         return reset_code;
1661 }
1662
1663 /* send UNLOAD_DONE command to the MCP */
1664 static void bnx2x_send_unload_done(struct bnx2x_softc *sc, uint8_t keep_link)
1665 {
1666         uint32_t reset_param =
1667             keep_link ? DRV_MSG_CODE_UNLOAD_SKIP_LINK_RESET : 0;
1668
1669         /* Report UNLOAD_DONE to MCP */
1670         if (!BNX2X_NOMCP(sc)) {
1671                 bnx2x_fw_command(sc, DRV_MSG_CODE_UNLOAD_DONE, reset_param);
1672         }
1673 }
1674
1675 static int bnx2x_func_wait_started(struct bnx2x_softc *sc)
1676 {
1677         int tout = 50;
1678
1679         if (!sc->port.pmf) {
1680                 return 0;
1681         }
1682
1683         /*
1684          * (assumption: No Attention from MCP at this stage)
1685          * PMF probably in the middle of TX disable/enable transaction
1686          * 1. Sync IRS for default SB
1687          * 2. Sync SP queue - this guarantees us that attention handling started
1688          * 3. Wait, that TX disable/enable transaction completes
1689          *
1690          * 1+2 guarantee that if DCBX attention was scheduled it already changed
1691          * pending bit of transaction from STARTED-->TX_STOPPED, if we already
1692          * received completion for the transaction the state is TX_STOPPED.
1693          * State will return to STARTED after completion of TX_STOPPED-->STARTED
1694          * transaction.
1695          */
1696
1697         while (ecore_func_get_state(sc, &sc->func_obj) !=
1698                ECORE_F_STATE_STARTED && tout--) {
1699                 DELAY(20000);
1700         }
1701
1702         if (ecore_func_get_state(sc, &sc->func_obj) != ECORE_F_STATE_STARTED) {
1703                 /*
1704                  * Failed to complete the transaction in a "good way"
1705                  * Force both transactions with CLR bit.
1706                  */
1707                 struct ecore_func_state_params func_params = { NULL };
1708
1709                 PMD_DRV_LOG(NOTICE, sc, "Unexpected function state! "
1710                             "Forcing STARTED-->TX_STOPPED-->STARTED");
1711
1712                 func_params.f_obj = &sc->func_obj;
1713                 bnx2x_set_bit(RAMROD_DRV_CLR_ONLY, &func_params.ramrod_flags);
1714
1715                 /* STARTED-->TX_STOPPED */
1716                 func_params.cmd = ECORE_F_CMD_TX_STOP;
1717                 ecore_func_state_change(sc, &func_params);
1718
1719                 /* TX_STOPPED-->STARTED */
1720                 func_params.cmd = ECORE_F_CMD_TX_START;
1721                 return ecore_func_state_change(sc, &func_params);
1722         }
1723
1724         return 0;
1725 }
1726
1727 static int bnx2x_stop_queue(struct bnx2x_softc *sc, int index)
1728 {
1729         struct bnx2x_fastpath *fp = &sc->fp[index];
1730         struct ecore_queue_state_params q_params = { NULL };
1731         int rc;
1732
1733         PMD_DRV_LOG(DEBUG, sc, "stopping queue %d cid %d", index, fp->index);
1734
1735         q_params.q_obj = &sc->sp_objs[fp->index].q_obj;
1736         /* We want to wait for completion in this context */
1737         bnx2x_set_bit(RAMROD_COMP_WAIT, &q_params.ramrod_flags);
1738
1739         /* Stop the primary connection: */
1740
1741         /* ...halt the connection */
1742         q_params.cmd = ECORE_Q_CMD_HALT;
1743         rc = ecore_queue_state_change(sc, &q_params);
1744         if (rc) {
1745                 return rc;
1746         }
1747
1748         /* ...terminate the connection */
1749         q_params.cmd = ECORE_Q_CMD_TERMINATE;
1750         memset(&q_params.params.terminate, 0,
1751                sizeof(q_params.params.terminate));
1752         q_params.params.terminate.cid_index = FIRST_TX_COS_INDEX;
1753         rc = ecore_queue_state_change(sc, &q_params);
1754         if (rc) {
1755                 return rc;
1756         }
1757
1758         /* ...delete cfc entry */
1759         q_params.cmd = ECORE_Q_CMD_CFC_DEL;
1760         memset(&q_params.params.cfc_del, 0, sizeof(q_params.params.cfc_del));
1761         q_params.params.cfc_del.cid_index = FIRST_TX_COS_INDEX;
1762         return ecore_queue_state_change(sc, &q_params);
1763 }
1764
1765 /* wait for the outstanding SP commands */
1766 static uint8_t bnx2x_wait_sp_comp(struct bnx2x_softc *sc, unsigned long mask)
1767 {
1768         unsigned long tmp;
1769         int tout = 5000;        /* wait for 5 secs tops */
1770
1771         while (tout--) {
1772                 mb();
1773                 if (!(atomic_load_acq_long(&sc->sp_state) & mask)) {
1774                         return TRUE;
1775                 }
1776
1777                 DELAY(1000);
1778         }
1779
1780         mb();
1781
1782         tmp = atomic_load_acq_long(&sc->sp_state);
1783         if (tmp & mask) {
1784                 PMD_DRV_LOG(INFO, sc, "Filtering completion timed out: "
1785                             "sp_state 0x%lx, mask 0x%lx", tmp, mask);
1786                 return FALSE;
1787         }
1788
1789         return FALSE;
1790 }
1791
1792 static int bnx2x_func_stop(struct bnx2x_softc *sc)
1793 {
1794         struct ecore_func_state_params func_params = { NULL };
1795         int rc;
1796
1797         /* prepare parameters for function state transitions */
1798         bnx2x_set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags);
1799         func_params.f_obj = &sc->func_obj;
1800         func_params.cmd = ECORE_F_CMD_STOP;
1801
1802         /*
1803          * Try to stop the function the 'good way'. If it fails (in case
1804          * of a parity error during bnx2x_chip_cleanup()) and we are
1805          * not in a debug mode, perform a state transaction in order to
1806          * enable further HW_RESET transaction.
1807          */
1808         rc = ecore_func_state_change(sc, &func_params);
1809         if (rc) {
1810                 PMD_DRV_LOG(NOTICE, sc, "FUNC_STOP ramrod failed. "
1811                             "Running a dry transaction");
1812                 bnx2x_set_bit(RAMROD_DRV_CLR_ONLY, &func_params.ramrod_flags);
1813                 return ecore_func_state_change(sc, &func_params);
1814         }
1815
1816         return 0;
1817 }
1818
1819 static int bnx2x_reset_hw(struct bnx2x_softc *sc, uint32_t load_code)
1820 {
1821         struct ecore_func_state_params func_params = { NULL };
1822
1823         /* Prepare parameters for function state transitions */
1824         bnx2x_set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags);
1825
1826         func_params.f_obj = &sc->func_obj;
1827         func_params.cmd = ECORE_F_CMD_HW_RESET;
1828
1829         func_params.params.hw_init.load_phase = load_code;
1830
1831         return ecore_func_state_change(sc, &func_params);
1832 }
1833
1834 static void bnx2x_int_disable_sync(struct bnx2x_softc *sc, int disable_hw)
1835 {
1836         if (disable_hw) {
1837                 /* prevent the HW from sending interrupts */
1838                 bnx2x_int_disable(sc);
1839         }
1840 }
1841
1842 static void
1843 bnx2x_chip_cleanup(struct bnx2x_softc *sc, uint32_t unload_mode, uint8_t keep_link)
1844 {
1845         int port = SC_PORT(sc);
1846         struct ecore_mcast_ramrod_params rparam = { NULL };
1847         uint32_t reset_code;
1848         int i, rc = 0;
1849
1850         bnx2x_drain_tx_queues(sc);
1851
1852         /* give HW time to discard old tx messages */
1853         DELAY(1000);
1854
1855         /* Clean all ETH MACs */
1856         rc = bnx2x_del_all_macs(sc, &sc->sp_objs[0].mac_obj, ECORE_ETH_MAC,
1857                               FALSE);
1858         if (rc < 0) {
1859                 PMD_DRV_LOG(NOTICE, sc,
1860                             "Failed to delete all ETH MACs (%d)", rc);
1861         }
1862
1863         /* Clean up UC list  */
1864         rc = bnx2x_del_all_macs(sc, &sc->sp_objs[0].mac_obj, ECORE_UC_LIST_MAC,
1865                               TRUE);
1866         if (rc < 0) {
1867                 PMD_DRV_LOG(NOTICE, sc,
1868                             "Failed to delete UC MACs list (%d)", rc);
1869         }
1870
1871         /* Disable LLH */
1872         REG_WR(sc, NIG_REG_LLH0_FUNC_EN + port * 8, 0);
1873
1874         /* Set "drop all" to stop Rx */
1875
1876         /*
1877          * We need to take the if_maddr_lock() here in order to prevent
1878          * a race between the completion code and this code.
1879          */
1880
1881         if (bnx2x_test_bit(ECORE_FILTER_RX_MODE_PENDING, &sc->sp_state)) {
1882                 bnx2x_set_bit(ECORE_FILTER_RX_MODE_SCHED, &sc->sp_state);
1883         } else {
1884                 bnx2x_set_storm_rx_mode(sc);
1885         }
1886
1887         /* Clean up multicast configuration */
1888         rparam.mcast_obj = &sc->mcast_obj;
1889         rc = ecore_config_mcast(sc, &rparam, ECORE_MCAST_CMD_DEL);
1890         if (rc < 0) {
1891                 PMD_DRV_LOG(NOTICE, sc,
1892                             "Failed to send DEL MCAST command (%d)", rc);
1893         }
1894
1895         /*
1896          * Send the UNLOAD_REQUEST to the MCP. This will return if
1897          * this function should perform FUNCTION, PORT, or COMMON HW
1898          * reset.
1899          */
1900         reset_code = bnx2x_send_unload_req(sc, unload_mode);
1901
1902         /*
1903          * (assumption: No Attention from MCP at this stage)
1904          * PMF probably in the middle of TX disable/enable transaction
1905          */
1906         rc = bnx2x_func_wait_started(sc);
1907         if (rc) {
1908                 PMD_DRV_LOG(NOTICE, sc, "bnx2x_func_wait_started failed");
1909         }
1910
1911         /*
1912          * Close multi and leading connections
1913          * Completions for ramrods are collected in a synchronous way
1914          */
1915         for (i = 0; i < sc->num_queues; i++) {
1916                 if (bnx2x_stop_queue(sc, i)) {
1917                         goto unload_error;
1918                 }
1919         }
1920
1921         /*
1922          * If SP settings didn't get completed so far - something
1923          * very wrong has happen.
1924          */
1925         if (!bnx2x_wait_sp_comp(sc, ~0x0UL)) {
1926                 PMD_DRV_LOG(NOTICE, sc, "Common slow path ramrods got stuck!");
1927         }
1928
1929 unload_error:
1930
1931         rc = bnx2x_func_stop(sc);
1932         if (rc) {
1933                 PMD_DRV_LOG(NOTICE, sc, "Function stop failed!");
1934         }
1935
1936         /* disable HW interrupts */
1937         bnx2x_int_disable_sync(sc, TRUE);
1938
1939         /* Reset the chip */
1940         rc = bnx2x_reset_hw(sc, reset_code);
1941         if (rc) {
1942                 PMD_DRV_LOG(NOTICE, sc, "Hardware reset failed");
1943         }
1944
1945         /* Report UNLOAD_DONE to MCP */
1946         bnx2x_send_unload_done(sc, keep_link);
1947 }
1948
1949 static void bnx2x_disable_close_the_gate(struct bnx2x_softc *sc)
1950 {
1951         uint32_t val;
1952
1953         PMD_DRV_LOG(DEBUG, sc, "Disabling 'close the gates'");
1954
1955         val = REG_RD(sc, MISC_REG_AEU_GENERAL_MASK);
1956         val &= ~(MISC_AEU_GENERAL_MASK_REG_AEU_PXP_CLOSE_MASK |
1957                  MISC_AEU_GENERAL_MASK_REG_AEU_NIG_CLOSE_MASK);
1958         REG_WR(sc, MISC_REG_AEU_GENERAL_MASK, val);
1959 }
1960
1961 /*
1962  * Cleans the object that have internal lists without sending
1963  * ramrods. Should be run when interrutps are disabled.
1964  */
1965 static void bnx2x_squeeze_objects(struct bnx2x_softc *sc)
1966 {
1967         unsigned long ramrod_flags = 0, vlan_mac_flags = 0;
1968         struct ecore_mcast_ramrod_params rparam = { NULL };
1969         struct ecore_vlan_mac_obj *mac_obj = &sc->sp_objs->mac_obj;
1970         int rc;
1971
1972         /* Cleanup MACs' object first... */
1973
1974         /* Wait for completion of requested */
1975         bnx2x_set_bit(RAMROD_COMP_WAIT, &ramrod_flags);
1976         /* Perform a dry cleanup */
1977         bnx2x_set_bit(RAMROD_DRV_CLR_ONLY, &ramrod_flags);
1978
1979         /* Clean ETH primary MAC */
1980         bnx2x_set_bit(ECORE_ETH_MAC, &vlan_mac_flags);
1981         rc = mac_obj->delete_all(sc, &sc->sp_objs->mac_obj, &vlan_mac_flags,
1982                                  &ramrod_flags);
1983         if (rc != 0) {
1984                 PMD_DRV_LOG(NOTICE, sc, "Failed to clean ETH MACs (%d)", rc);
1985         }
1986
1987         /* Cleanup UC list */
1988         vlan_mac_flags = 0;
1989         bnx2x_set_bit(ECORE_UC_LIST_MAC, &vlan_mac_flags);
1990         rc = mac_obj->delete_all(sc, mac_obj, &vlan_mac_flags, &ramrod_flags);
1991         if (rc != 0) {
1992                 PMD_DRV_LOG(NOTICE, sc,
1993                             "Failed to clean UC list MACs (%d)", rc);
1994         }
1995
1996         /* Now clean mcast object... */
1997
1998         rparam.mcast_obj = &sc->mcast_obj;
1999         bnx2x_set_bit(RAMROD_DRV_CLR_ONLY, &rparam.ramrod_flags);
2000
2001         /* Add a DEL command... */
2002         rc = ecore_config_mcast(sc, &rparam, ECORE_MCAST_CMD_DEL);
2003         if (rc < 0) {
2004                 PMD_DRV_LOG(NOTICE, sc,
2005                             "Failed to send DEL MCAST command (%d)", rc);
2006         }
2007
2008         /* now wait until all pending commands are cleared */
2009
2010         rc = ecore_config_mcast(sc, &rparam, ECORE_MCAST_CMD_CONT);
2011         while (rc != 0) {
2012                 if (rc < 0) {
2013                         PMD_DRV_LOG(NOTICE, sc,
2014                                     "Failed to clean MCAST object (%d)", rc);
2015                         return;
2016                 }
2017
2018                 rc = ecore_config_mcast(sc, &rparam, ECORE_MCAST_CMD_CONT);
2019         }
2020 }
2021
2022 /* stop the controller */
2023 __rte_noinline
2024 int
2025 bnx2x_nic_unload(struct bnx2x_softc *sc, uint32_t unload_mode, uint8_t keep_link)
2026 {
2027         uint8_t global = FALSE;
2028         uint32_t val;
2029
2030         PMD_INIT_FUNC_TRACE(sc);
2031
2032         PMD_DRV_LOG(DEBUG, sc, "Starting NIC unload...");
2033
2034         /* mark driver as unloaded in shmem2 */
2035         if (IS_PF(sc) && SHMEM2_HAS(sc, drv_capabilities_flag)) {
2036                 val = SHMEM2_RD(sc, drv_capabilities_flag[SC_FW_MB_IDX(sc)]);
2037                 SHMEM2_WR(sc, drv_capabilities_flag[SC_FW_MB_IDX(sc)],
2038                           val & ~DRV_FLAGS_CAPABILITIES_LOADED_L2);
2039         }
2040
2041         if (IS_PF(sc) && sc->recovery_state != BNX2X_RECOVERY_DONE &&
2042             (sc->state == BNX2X_STATE_CLOSED || sc->state == BNX2X_STATE_ERROR)) {
2043                 /*
2044                  * We can get here if the driver has been unloaded
2045                  * during parity error recovery and is either waiting for a
2046                  * leader to complete or for other functions to unload and
2047                  * then ifconfig down has been issued. In this case we want to
2048                  * unload and let other functions to complete a recovery
2049                  * process.
2050                  */
2051                 sc->recovery_state = BNX2X_RECOVERY_DONE;
2052                 sc->is_leader = 0;
2053                 bnx2x_release_leader_lock(sc);
2054                 mb();
2055
2056                 PMD_DRV_LOG(NOTICE, sc, "Can't unload in closed or error state");
2057                 return -1;
2058         }
2059
2060         /*
2061          * Nothing to do during unload if previous bnx2x_nic_load()
2062          * did not completed successfully - all resourses are released.
2063          */
2064         if ((sc->state == BNX2X_STATE_CLOSED) || (sc->state == BNX2X_STATE_ERROR)) {
2065                 return 0;
2066         }
2067
2068         sc->state = BNX2X_STATE_CLOSING_WAITING_HALT;
2069         mb();
2070
2071         sc->rx_mode = BNX2X_RX_MODE_NONE;
2072         bnx2x_set_rx_mode(sc);
2073         mb();
2074
2075         if (IS_PF(sc)) {
2076                 /* set ALWAYS_ALIVE bit in shmem */
2077                 sc->fw_drv_pulse_wr_seq |= DRV_PULSE_ALWAYS_ALIVE;
2078
2079                 bnx2x_drv_pulse(sc);
2080
2081                 bnx2x_stats_handle(sc, STATS_EVENT_STOP);
2082                 bnx2x_save_statistics(sc);
2083         }
2084
2085         /* wait till consumers catch up with producers in all queues */
2086         bnx2x_drain_tx_queues(sc);
2087
2088         /* if VF indicate to PF this function is going down (PF will delete sp
2089          * elements and clear initializations
2090          */
2091         if (IS_VF(sc)) {
2092                 bnx2x_vf_unload(sc);
2093         } else if (unload_mode != UNLOAD_RECOVERY) {
2094                 /* if this is a normal/close unload need to clean up chip */
2095                 bnx2x_chip_cleanup(sc, unload_mode, keep_link);
2096         } else {
2097                 /* Send the UNLOAD_REQUEST to the MCP */
2098                 bnx2x_send_unload_req(sc, unload_mode);
2099
2100                 /*
2101                  * Prevent transactions to host from the functions on the
2102                  * engine that doesn't reset global blocks in case of global
2103                  * attention once gloabl blocks are reset and gates are opened
2104                  * (the engine which leader will perform the recovery
2105                  * last).
2106                  */
2107                 if (!CHIP_IS_E1x(sc)) {
2108                         bnx2x_pf_disable(sc);
2109                 }
2110
2111                 /* disable HW interrupts */
2112                 bnx2x_int_disable_sync(sc, TRUE);
2113
2114                 /* Report UNLOAD_DONE to MCP */
2115                 bnx2x_send_unload_done(sc, FALSE);
2116         }
2117
2118         /*
2119          * At this stage no more interrupts will arrive so we may safely clean
2120          * the queue'able objects here in case they failed to get cleaned so far.
2121          */
2122         if (IS_PF(sc)) {
2123                 bnx2x_squeeze_objects(sc);
2124         }
2125
2126         /* There should be no more pending SP commands at this stage */
2127         sc->sp_state = 0;
2128
2129         sc->port.pmf = 0;
2130
2131         if (IS_PF(sc)) {
2132                 bnx2x_free_mem(sc);
2133         }
2134
2135         /* free the host hardware/software hsi structures */
2136         bnx2x_free_hsi_mem(sc);
2137
2138         bnx2x_free_fw_stats_mem(sc);
2139
2140         sc->state = BNX2X_STATE_CLOSED;
2141
2142         /*
2143          * Check if there are pending parity attentions. If there are - set
2144          * RECOVERY_IN_PROGRESS.
2145          */
2146         if (IS_PF(sc) && bnx2x_chk_parity_attn(sc, &global, FALSE)) {
2147                 bnx2x_set_reset_in_progress(sc);
2148
2149                 /* Set RESET_IS_GLOBAL if needed */
2150                 if (global) {
2151                         bnx2x_set_reset_global(sc);
2152                 }
2153         }
2154
2155         /*
2156          * The last driver must disable a "close the gate" if there is no
2157          * parity attention or "process kill" pending.
2158          */
2159         if (IS_PF(sc) && !bnx2x_clear_pf_load(sc) &&
2160             bnx2x_reset_is_done(sc, SC_PATH(sc))) {
2161                 bnx2x_disable_close_the_gate(sc);
2162         }
2163
2164         PMD_DRV_LOG(DEBUG, sc, "Ended NIC unload");
2165
2166         return 0;
2167 }
2168
2169 /*
2170  * Encapsulte an mbuf cluster into the tx bd chain and makes the memory
2171  * visible to the controller.
2172  *
2173  * If an mbuf is submitted to this routine and cannot be given to the
2174  * controller (e.g. it has too many fragments) then the function may free
2175  * the mbuf and return to the caller.
2176  *
2177  * Returns:
2178  *     int: Number of TX BDs used for the mbuf
2179  *
2180  *   Note the side effect that an mbuf may be freed if it causes a problem.
2181  */
2182 int bnx2x_tx_encap(struct bnx2x_tx_queue *txq, struct rte_mbuf *m0)
2183 {
2184         struct eth_tx_start_bd *tx_start_bd;
2185         uint16_t bd_prod, pkt_prod;
2186         struct bnx2x_softc *sc;
2187         uint32_t nbds = 0;
2188
2189         sc = txq->sc;
2190         bd_prod = txq->tx_bd_tail;
2191         pkt_prod = txq->tx_pkt_tail;
2192
2193         txq->sw_ring[TX_BD(pkt_prod, txq)] = m0;
2194
2195         tx_start_bd = &txq->tx_ring[TX_BD(bd_prod, txq)].start_bd;
2196
2197         tx_start_bd->addr_lo =
2198             rte_cpu_to_le_32(U64_LO(rte_mbuf_data_iova(m0)));
2199         tx_start_bd->addr_hi =
2200             rte_cpu_to_le_32(U64_HI(rte_mbuf_data_iova(m0)));
2201         tx_start_bd->nbytes = rte_cpu_to_le_16(m0->data_len);
2202         tx_start_bd->bd_flags.as_bitfield = ETH_TX_BD_FLAGS_START_BD;
2203         tx_start_bd->general_data =
2204             (1 << ETH_TX_START_BD_HDR_NBDS_SHIFT);
2205
2206         tx_start_bd->nbd = rte_cpu_to_le_16(2);
2207
2208         if (m0->ol_flags & PKT_TX_VLAN_PKT) {
2209                 tx_start_bd->vlan_or_ethertype =
2210                     rte_cpu_to_le_16(m0->vlan_tci);
2211                 tx_start_bd->bd_flags.as_bitfield |=
2212                     (X_ETH_OUTBAND_VLAN <<
2213                      ETH_TX_BD_FLAGS_VLAN_MODE_SHIFT);
2214         } else {
2215                 if (IS_PF(sc))
2216                         tx_start_bd->vlan_or_ethertype =
2217                             rte_cpu_to_le_16(pkt_prod);
2218                 else {
2219                         struct rte_ether_hdr *eh =
2220                             rte_pktmbuf_mtod(m0, struct rte_ether_hdr *);
2221
2222                         tx_start_bd->vlan_or_ethertype =
2223                             rte_cpu_to_le_16(rte_be_to_cpu_16(eh->ether_type));
2224                 }
2225         }
2226
2227         bd_prod = NEXT_TX_BD(bd_prod);
2228         if (IS_VF(sc)) {
2229                 struct eth_tx_parse_bd_e2 *tx_parse_bd;
2230                 const struct rte_ether_hdr *eh =
2231                     rte_pktmbuf_mtod(m0, struct rte_ether_hdr *);
2232                 uint8_t mac_type = UNICAST_ADDRESS;
2233
2234                 tx_parse_bd =
2235                     &txq->tx_ring[TX_BD(bd_prod, txq)].parse_bd_e2;
2236                 if (rte_is_multicast_ether_addr(&eh->d_addr)) {
2237                         if (rte_is_broadcast_ether_addr(&eh->d_addr))
2238                                 mac_type = BROADCAST_ADDRESS;
2239                         else
2240                                 mac_type = MULTICAST_ADDRESS;
2241                 }
2242                 tx_parse_bd->parsing_data =
2243                     (mac_type << ETH_TX_PARSE_BD_E2_ETH_ADDR_TYPE_SHIFT);
2244
2245                 rte_memcpy(&tx_parse_bd->data.mac_addr.dst_hi,
2246                            &eh->d_addr.addr_bytes[0], 2);
2247                 rte_memcpy(&tx_parse_bd->data.mac_addr.dst_mid,
2248                            &eh->d_addr.addr_bytes[2], 2);
2249                 rte_memcpy(&tx_parse_bd->data.mac_addr.dst_lo,
2250                            &eh->d_addr.addr_bytes[4], 2);
2251                 rte_memcpy(&tx_parse_bd->data.mac_addr.src_hi,
2252                            &eh->s_addr.addr_bytes[0], 2);
2253                 rte_memcpy(&tx_parse_bd->data.mac_addr.src_mid,
2254                            &eh->s_addr.addr_bytes[2], 2);
2255                 rte_memcpy(&tx_parse_bd->data.mac_addr.src_lo,
2256                            &eh->s_addr.addr_bytes[4], 2);
2257
2258                 tx_parse_bd->data.mac_addr.dst_hi =
2259                     rte_cpu_to_be_16(tx_parse_bd->data.mac_addr.dst_hi);
2260                 tx_parse_bd->data.mac_addr.dst_mid =
2261                     rte_cpu_to_be_16(tx_parse_bd->data.
2262                                      mac_addr.dst_mid);
2263                 tx_parse_bd->data.mac_addr.dst_lo =
2264                     rte_cpu_to_be_16(tx_parse_bd->data.mac_addr.dst_lo);
2265                 tx_parse_bd->data.mac_addr.src_hi =
2266                     rte_cpu_to_be_16(tx_parse_bd->data.mac_addr.src_hi);
2267                 tx_parse_bd->data.mac_addr.src_mid =
2268                     rte_cpu_to_be_16(tx_parse_bd->data.
2269                                      mac_addr.src_mid);
2270                 tx_parse_bd->data.mac_addr.src_lo =
2271                     rte_cpu_to_be_16(tx_parse_bd->data.mac_addr.src_lo);
2272
2273                 PMD_TX_LOG(DEBUG,
2274                            "PBD dst %x %x %x src %x %x %x p_data %x",
2275                            tx_parse_bd->data.mac_addr.dst_hi,
2276                            tx_parse_bd->data.mac_addr.dst_mid,
2277                            tx_parse_bd->data.mac_addr.dst_lo,
2278                            tx_parse_bd->data.mac_addr.src_hi,
2279                            tx_parse_bd->data.mac_addr.src_mid,
2280                            tx_parse_bd->data.mac_addr.src_lo,
2281                            tx_parse_bd->parsing_data);
2282         }
2283
2284         PMD_TX_LOG(DEBUG,
2285                    "start bd: nbytes %d flags %x vlan %x",
2286                    tx_start_bd->nbytes,
2287                    tx_start_bd->bd_flags.as_bitfield,
2288                    tx_start_bd->vlan_or_ethertype);
2289
2290         bd_prod = NEXT_TX_BD(bd_prod);
2291         pkt_prod++;
2292
2293         if (TX_IDX(bd_prod) < 2)
2294                 nbds++;
2295
2296         txq->nb_tx_avail -= 2;
2297         txq->tx_bd_tail = bd_prod;
2298         txq->tx_pkt_tail = pkt_prod;
2299
2300         return nbds + 2;
2301 }
2302
2303 static uint16_t bnx2x_cid_ilt_lines(struct bnx2x_softc *sc)
2304 {
2305         return L2_ILT_LINES(sc);
2306 }
2307
2308 static void bnx2x_ilt_set_info(struct bnx2x_softc *sc)
2309 {
2310         struct ilt_client_info *ilt_client;
2311         struct ecore_ilt *ilt = sc->ilt;
2312         uint16_t line = 0;
2313
2314         PMD_INIT_FUNC_TRACE(sc);
2315
2316         ilt->start_line = FUNC_ILT_BASE(SC_FUNC(sc));
2317
2318         /* CDU */
2319         ilt_client = &ilt->clients[ILT_CLIENT_CDU];
2320         ilt_client->client_num = ILT_CLIENT_CDU;
2321         ilt_client->page_size = CDU_ILT_PAGE_SZ;
2322         ilt_client->flags = ILT_CLIENT_SKIP_MEM;
2323         ilt_client->start = line;
2324         line += bnx2x_cid_ilt_lines(sc);
2325
2326         if (CNIC_SUPPORT(sc)) {
2327                 line += CNIC_ILT_LINES;
2328         }
2329
2330         ilt_client->end = (line - 1);
2331
2332         /* QM */
2333         if (QM_INIT(sc->qm_cid_count)) {
2334                 ilt_client = &ilt->clients[ILT_CLIENT_QM];
2335                 ilt_client->client_num = ILT_CLIENT_QM;
2336                 ilt_client->page_size = QM_ILT_PAGE_SZ;
2337                 ilt_client->flags = 0;
2338                 ilt_client->start = line;
2339
2340                 /* 4 bytes for each cid */
2341                 line += DIV_ROUND_UP(sc->qm_cid_count * QM_QUEUES_PER_FUNC * 4,
2342                                      QM_ILT_PAGE_SZ);
2343
2344                 ilt_client->end = (line - 1);
2345         }
2346
2347         if (CNIC_SUPPORT(sc)) {
2348                 /* SRC */
2349                 ilt_client = &ilt->clients[ILT_CLIENT_SRC];
2350                 ilt_client->client_num = ILT_CLIENT_SRC;
2351                 ilt_client->page_size = SRC_ILT_PAGE_SZ;
2352                 ilt_client->flags = 0;
2353                 ilt_client->start = line;
2354                 line += SRC_ILT_LINES;
2355                 ilt_client->end = (line - 1);
2356
2357                 /* TM */
2358                 ilt_client = &ilt->clients[ILT_CLIENT_TM];
2359                 ilt_client->client_num = ILT_CLIENT_TM;
2360                 ilt_client->page_size = TM_ILT_PAGE_SZ;
2361                 ilt_client->flags = 0;
2362                 ilt_client->start = line;
2363                 line += TM_ILT_LINES;
2364                 ilt_client->end = (line - 1);
2365         }
2366
2367         assert((line <= ILT_MAX_LINES));
2368 }
2369
2370 static void bnx2x_set_fp_rx_buf_size(struct bnx2x_softc *sc)
2371 {
2372         int i;
2373
2374         for (i = 0; i < sc->num_queues; i++) {
2375                 /* get the Rx buffer size for RX frames */
2376                 sc->fp[i].rx_buf_size =
2377                     (IP_HEADER_ALIGNMENT_PADDING + ETH_OVERHEAD + sc->mtu);
2378         }
2379 }
2380
2381 int bnx2x_alloc_ilt_mem(struct bnx2x_softc *sc)
2382 {
2383
2384         sc->ilt = rte_malloc("", sizeof(struct ecore_ilt), RTE_CACHE_LINE_SIZE);
2385
2386         return sc->ilt == NULL;
2387 }
2388
2389 static int bnx2x_alloc_ilt_lines_mem(struct bnx2x_softc *sc)
2390 {
2391         sc->ilt->lines = rte_calloc("",
2392                                     sizeof(struct ilt_line), ILT_MAX_LINES,
2393                                     RTE_CACHE_LINE_SIZE);
2394         return sc->ilt->lines == NULL;
2395 }
2396
2397 void bnx2x_free_ilt_mem(struct bnx2x_softc *sc)
2398 {
2399         rte_free(sc->ilt);
2400         sc->ilt = NULL;
2401 }
2402
2403 static void bnx2x_free_ilt_lines_mem(struct bnx2x_softc *sc)
2404 {
2405         if (sc->ilt->lines != NULL) {
2406                 rte_free(sc->ilt->lines);
2407                 sc->ilt->lines = NULL;
2408         }
2409 }
2410
2411 static void bnx2x_free_mem(struct bnx2x_softc *sc)
2412 {
2413         uint32_t i;
2414
2415         for (i = 0; i < L2_ILT_LINES(sc); i++) {
2416                 sc->context[i].vcxt = NULL;
2417                 sc->context[i].size = 0;
2418         }
2419
2420         ecore_ilt_mem_op(sc, ILT_MEMOP_FREE);
2421
2422         bnx2x_free_ilt_lines_mem(sc);
2423 }
2424
2425 static int bnx2x_alloc_mem(struct bnx2x_softc *sc)
2426 {
2427         int context_size;
2428         int allocated;
2429         int i;
2430         char cdu_name[RTE_MEMZONE_NAMESIZE];
2431
2432         /*
2433          * Allocate memory for CDU context:
2434          * This memory is allocated separately and not in the generic ILT
2435          * functions because CDU differs in few aspects:
2436          * 1. There can be multiple entities allocating memory for context -
2437          * regular L2, CNIC, and SRIOV drivers. Each separately controls
2438          * its own ILT lines.
2439          * 2. Since CDU page-size is not a single 4KB page (which is the case
2440          * for the other ILT clients), to be efficient we want to support
2441          * allocation of sub-page-size in the last entry.
2442          * 3. Context pointers are used by the driver to pass to FW / update
2443          * the context (for the other ILT clients the pointers are used just to
2444          * free the memory during unload).
2445          */
2446         context_size = (sizeof(union cdu_context) * BNX2X_L2_CID_COUNT(sc));
2447         for (i = 0, allocated = 0; allocated < context_size; i++) {
2448                 sc->context[i].size = min(CDU_ILT_PAGE_SZ,
2449                                           (context_size - allocated));
2450
2451                 snprintf(cdu_name, sizeof(cdu_name), "cdu_%d", i);
2452                 if (bnx2x_dma_alloc(sc, sc->context[i].size,
2453                                   &sc->context[i].vcxt_dma,
2454                                   cdu_name, BNX2X_PAGE_SIZE) != 0) {
2455                         bnx2x_free_mem(sc);
2456                         return -1;
2457                 }
2458
2459                 sc->context[i].vcxt =
2460                     (union cdu_context *)sc->context[i].vcxt_dma.vaddr;
2461
2462                 allocated += sc->context[i].size;
2463         }
2464
2465         bnx2x_alloc_ilt_lines_mem(sc);
2466
2467         if (ecore_ilt_mem_op(sc, ILT_MEMOP_ALLOC)) {
2468                 PMD_DRV_LOG(NOTICE, sc, "ecore_ilt_mem_op ILT_MEMOP_ALLOC failed");
2469                 bnx2x_free_mem(sc);
2470                 return -1;
2471         }
2472
2473         return 0;
2474 }
2475
2476 static void bnx2x_free_fw_stats_mem(struct bnx2x_softc *sc)
2477 {
2478         bnx2x_dma_free(&sc->fw_stats_dma);
2479         sc->fw_stats_num = 0;
2480
2481         sc->fw_stats_req_size = 0;
2482         sc->fw_stats_req = NULL;
2483         sc->fw_stats_req_mapping = 0;
2484
2485         sc->fw_stats_data_size = 0;
2486         sc->fw_stats_data = NULL;
2487         sc->fw_stats_data_mapping = 0;
2488 }
2489
2490 static int bnx2x_alloc_fw_stats_mem(struct bnx2x_softc *sc)
2491 {
2492         uint8_t num_queue_stats;
2493         int num_groups, vf_headroom = 0;
2494
2495         /* number of queues for statistics is number of eth queues */
2496         num_queue_stats = BNX2X_NUM_ETH_QUEUES(sc);
2497
2498         /*
2499          * Total number of FW statistics requests =
2500          *   1 for port stats + 1 for PF stats + num of queues
2501          */
2502         sc->fw_stats_num = (2 + num_queue_stats);
2503
2504         /*
2505          * Request is built from stats_query_header and an array of
2506          * stats_query_cmd_group each of which contains STATS_QUERY_CMD_COUNT
2507          * rules. The real number or requests is configured in the
2508          * stats_query_header.
2509          */
2510         num_groups = (sc->fw_stats_num + vf_headroom) / STATS_QUERY_CMD_COUNT;
2511         if ((sc->fw_stats_num + vf_headroom) % STATS_QUERY_CMD_COUNT)
2512                 num_groups++;
2513
2514         sc->fw_stats_req_size =
2515             (sizeof(struct stats_query_header) +
2516              (num_groups * sizeof(struct stats_query_cmd_group)));
2517
2518         /*
2519          * Data for statistics requests + stats_counter.
2520          * stats_counter holds per-STORM counters that are incremented when
2521          * STORM has finished with the current request. Memory for FCoE
2522          * offloaded statistics are counted anyway, even if they will not be sent.
2523          * VF stats are not accounted for here as the data of VF stats is stored
2524          * in memory allocated by the VF, not here.
2525          */
2526         sc->fw_stats_data_size =
2527             (sizeof(struct stats_counter) +
2528              sizeof(struct per_port_stats) + sizeof(struct per_pf_stats) +
2529              /* sizeof(struct fcoe_statistics_params) + */
2530              (sizeof(struct per_queue_stats) * num_queue_stats));
2531
2532         if (bnx2x_dma_alloc(sc, (sc->fw_stats_req_size + sc->fw_stats_data_size),
2533                           &sc->fw_stats_dma, "fw_stats",
2534                           RTE_CACHE_LINE_SIZE) != 0) {
2535                 bnx2x_free_fw_stats_mem(sc);
2536                 return -1;
2537         }
2538
2539         /* set up the shortcuts */
2540
2541         sc->fw_stats_req = (struct bnx2x_fw_stats_req *)sc->fw_stats_dma.vaddr;
2542         sc->fw_stats_req_mapping = sc->fw_stats_dma.paddr;
2543
2544         sc->fw_stats_data =
2545             (struct bnx2x_fw_stats_data *)((uint8_t *) sc->fw_stats_dma.vaddr +
2546                                          sc->fw_stats_req_size);
2547         sc->fw_stats_data_mapping = (sc->fw_stats_dma.paddr +
2548                                      sc->fw_stats_req_size);
2549
2550         return 0;
2551 }
2552
2553 /*
2554  * Bits map:
2555  * 0-7  - Engine0 load counter.
2556  * 8-15 - Engine1 load counter.
2557  * 16   - Engine0 RESET_IN_PROGRESS bit.
2558  * 17   - Engine1 RESET_IN_PROGRESS bit.
2559  * 18   - Engine0 ONE_IS_LOADED. Set when there is at least one active
2560  *        function on the engine
2561  * 19   - Engine1 ONE_IS_LOADED.
2562  * 20   - Chip reset flow bit. When set none-leader must wait for both engines
2563  *        leader to complete (check for both RESET_IN_PROGRESS bits and not
2564  *        for just the one belonging to its engine).
2565  */
2566 #define BNX2X_RECOVERY_GLOB_REG     MISC_REG_GENERIC_POR_1
2567 #define BNX2X_PATH0_LOAD_CNT_MASK   0x000000ff
2568 #define BNX2X_PATH0_LOAD_CNT_SHIFT  0
2569 #define BNX2X_PATH1_LOAD_CNT_MASK   0x0000ff00
2570 #define BNX2X_PATH1_LOAD_CNT_SHIFT  8
2571 #define BNX2X_PATH0_RST_IN_PROG_BIT 0x00010000
2572 #define BNX2X_PATH1_RST_IN_PROG_BIT 0x00020000
2573 #define BNX2X_GLOBAL_RESET_BIT      0x00040000
2574
2575 /* set the GLOBAL_RESET bit, should be run under rtnl lock */
2576 static void bnx2x_set_reset_global(struct bnx2x_softc *sc)
2577 {
2578         uint32_t val;
2579         bnx2x_acquire_hw_lock(sc, HW_LOCK_RESOURCE_RECOVERY_REG);
2580         val = REG_RD(sc, BNX2X_RECOVERY_GLOB_REG);
2581         REG_WR(sc, BNX2X_RECOVERY_GLOB_REG, val | BNX2X_GLOBAL_RESET_BIT);
2582         bnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_RECOVERY_REG);
2583 }
2584
2585 /* clear the GLOBAL_RESET bit, should be run under rtnl lock */
2586 static void bnx2x_clear_reset_global(struct bnx2x_softc *sc)
2587 {
2588         uint32_t val;
2589         bnx2x_acquire_hw_lock(sc, HW_LOCK_RESOURCE_RECOVERY_REG);
2590         val = REG_RD(sc, BNX2X_RECOVERY_GLOB_REG);
2591         REG_WR(sc, BNX2X_RECOVERY_GLOB_REG, val & (~BNX2X_GLOBAL_RESET_BIT));
2592         bnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_RECOVERY_REG);
2593 }
2594
2595 /* checks the GLOBAL_RESET bit, should be run under rtnl lock */
2596 static uint8_t bnx2x_reset_is_global(struct bnx2x_softc *sc)
2597 {
2598         return REG_RD(sc, BNX2X_RECOVERY_GLOB_REG) & BNX2X_GLOBAL_RESET_BIT;
2599 }
2600
2601 /* clear RESET_IN_PROGRESS bit for the engine, should be run under rtnl lock */
2602 static void bnx2x_set_reset_done(struct bnx2x_softc *sc)
2603 {
2604         uint32_t val;
2605         uint32_t bit = SC_PATH(sc) ? BNX2X_PATH1_RST_IN_PROG_BIT :
2606             BNX2X_PATH0_RST_IN_PROG_BIT;
2607
2608         bnx2x_acquire_hw_lock(sc, HW_LOCK_RESOURCE_RECOVERY_REG);
2609
2610         val = REG_RD(sc, BNX2X_RECOVERY_GLOB_REG);
2611         /* Clear the bit */
2612         val &= ~bit;
2613         REG_WR(sc, BNX2X_RECOVERY_GLOB_REG, val);
2614
2615         bnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_RECOVERY_REG);
2616 }
2617
2618 /* set RESET_IN_PROGRESS for the engine, should be run under rtnl lock */
2619 static void bnx2x_set_reset_in_progress(struct bnx2x_softc *sc)
2620 {
2621         uint32_t val;
2622         uint32_t bit = SC_PATH(sc) ? BNX2X_PATH1_RST_IN_PROG_BIT :
2623             BNX2X_PATH0_RST_IN_PROG_BIT;
2624
2625         bnx2x_acquire_hw_lock(sc, HW_LOCK_RESOURCE_RECOVERY_REG);
2626
2627         val = REG_RD(sc, BNX2X_RECOVERY_GLOB_REG);
2628         /* Set the bit */
2629         val |= bit;
2630         REG_WR(sc, BNX2X_RECOVERY_GLOB_REG, val);
2631
2632         bnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_RECOVERY_REG);
2633 }
2634
2635 /* check RESET_IN_PROGRESS bit for an engine, should be run under rtnl lock */
2636 static uint8_t bnx2x_reset_is_done(struct bnx2x_softc *sc, int engine)
2637 {
2638         uint32_t val = REG_RD(sc, BNX2X_RECOVERY_GLOB_REG);
2639         uint32_t bit = engine ? BNX2X_PATH1_RST_IN_PROG_BIT :
2640             BNX2X_PATH0_RST_IN_PROG_BIT;
2641
2642         /* return false if bit is set */
2643         return (val & bit) ? FALSE : TRUE;
2644 }
2645
2646 /* get the load status for an engine, should be run under rtnl lock */
2647 static uint8_t bnx2x_get_load_status(struct bnx2x_softc *sc, int engine)
2648 {
2649         uint32_t mask = engine ? BNX2X_PATH1_LOAD_CNT_MASK :
2650             BNX2X_PATH0_LOAD_CNT_MASK;
2651         uint32_t shift = engine ? BNX2X_PATH1_LOAD_CNT_SHIFT :
2652             BNX2X_PATH0_LOAD_CNT_SHIFT;
2653         uint32_t val = REG_RD(sc, BNX2X_RECOVERY_GLOB_REG);
2654
2655         val = ((val & mask) >> shift);
2656
2657         return val != 0;
2658 }
2659
2660 /* set pf load mark */
2661 static void bnx2x_set_pf_load(struct bnx2x_softc *sc)
2662 {
2663         uint32_t val;
2664         uint32_t val1;
2665         uint32_t mask = SC_PATH(sc) ? BNX2X_PATH1_LOAD_CNT_MASK :
2666             BNX2X_PATH0_LOAD_CNT_MASK;
2667         uint32_t shift = SC_PATH(sc) ? BNX2X_PATH1_LOAD_CNT_SHIFT :
2668             BNX2X_PATH0_LOAD_CNT_SHIFT;
2669
2670         bnx2x_acquire_hw_lock(sc, HW_LOCK_RESOURCE_RECOVERY_REG);
2671
2672         PMD_INIT_FUNC_TRACE(sc);
2673
2674         val = REG_RD(sc, BNX2X_RECOVERY_GLOB_REG);
2675
2676         /* get the current counter value */
2677         val1 = ((val & mask) >> shift);
2678
2679         /* set bit of this PF */
2680         val1 |= (1 << SC_ABS_FUNC(sc));
2681
2682         /* clear the old value */
2683         val &= ~mask;
2684
2685         /* set the new one */
2686         val |= ((val1 << shift) & mask);
2687
2688         REG_WR(sc, BNX2X_RECOVERY_GLOB_REG, val);
2689
2690         bnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_RECOVERY_REG);
2691 }
2692
2693 /* clear pf load mark */
2694 static uint8_t bnx2x_clear_pf_load(struct bnx2x_softc *sc)
2695 {
2696         uint32_t val1, val;
2697         uint32_t mask = SC_PATH(sc) ? BNX2X_PATH1_LOAD_CNT_MASK :
2698             BNX2X_PATH0_LOAD_CNT_MASK;
2699         uint32_t shift = SC_PATH(sc) ? BNX2X_PATH1_LOAD_CNT_SHIFT :
2700             BNX2X_PATH0_LOAD_CNT_SHIFT;
2701
2702         bnx2x_acquire_hw_lock(sc, HW_LOCK_RESOURCE_RECOVERY_REG);
2703         val = REG_RD(sc, BNX2X_RECOVERY_GLOB_REG);
2704
2705         /* get the current counter value */
2706         val1 = (val & mask) >> shift;
2707
2708         /* clear bit of that PF */
2709         val1 &= ~(1 << SC_ABS_FUNC(sc));
2710
2711         /* clear the old value */
2712         val &= ~mask;
2713
2714         /* set the new one */
2715         val |= ((val1 << shift) & mask);
2716
2717         REG_WR(sc, BNX2X_RECOVERY_GLOB_REG, val);
2718         bnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_RECOVERY_REG);
2719         return val1 != 0;
2720 }
2721
2722 /* send load requrest to mcp and analyze response */
2723 static int bnx2x_nic_load_request(struct bnx2x_softc *sc, uint32_t * load_code)
2724 {
2725         PMD_INIT_FUNC_TRACE(sc);
2726
2727         /* init fw_seq */
2728         sc->fw_seq =
2729             (SHMEM_RD(sc, func_mb[SC_FW_MB_IDX(sc)].drv_mb_header) &
2730              DRV_MSG_SEQ_NUMBER_MASK);
2731
2732         PMD_DRV_LOG(DEBUG, sc, "initial fw_seq 0x%04x", sc->fw_seq);
2733
2734 #ifdef BNX2X_PULSE
2735         /* get the current FW pulse sequence */
2736         sc->fw_drv_pulse_wr_seq =
2737             (SHMEM_RD(sc, func_mb[SC_FW_MB_IDX(sc)].drv_pulse_mb) &
2738              DRV_PULSE_SEQ_MASK);
2739 #else
2740         /* set ALWAYS_ALIVE bit in shmem */
2741         sc->fw_drv_pulse_wr_seq |= DRV_PULSE_ALWAYS_ALIVE;
2742         bnx2x_drv_pulse(sc);
2743 #endif
2744
2745         /* load request */
2746         (*load_code) = bnx2x_fw_command(sc, DRV_MSG_CODE_LOAD_REQ,
2747                                       DRV_MSG_CODE_LOAD_REQ_WITH_LFA);
2748
2749         /* if the MCP fails to respond we must abort */
2750         if (!(*load_code)) {
2751                 PMD_DRV_LOG(NOTICE, sc, "MCP response failure!");
2752                 return -1;
2753         }
2754
2755         /* if MCP refused then must abort */
2756         if ((*load_code) == FW_MSG_CODE_DRV_LOAD_REFUSED) {
2757                 PMD_DRV_LOG(NOTICE, sc, "MCP refused load request");
2758                 return -1;
2759         }
2760
2761         return 0;
2762 }
2763
2764 /*
2765  * Check whether another PF has already loaded FW to chip. In virtualized
2766  * environments a pf from anoth VM may have already initialized the device
2767  * including loading FW.
2768  */
2769 static int bnx2x_nic_load_analyze_req(struct bnx2x_softc *sc, uint32_t load_code)
2770 {
2771         uint32_t my_fw, loaded_fw;
2772
2773         /* is another pf loaded on this engine? */
2774         if ((load_code != FW_MSG_CODE_DRV_LOAD_COMMON_CHIP) &&
2775             (load_code != FW_MSG_CODE_DRV_LOAD_COMMON)) {
2776                 /* build my FW version dword */
2777                 my_fw = (BNX2X_5710_FW_MAJOR_VERSION +
2778                          (BNX2X_5710_FW_MINOR_VERSION << 8) +
2779                          (BNX2X_5710_FW_REVISION_VERSION << 16) +
2780                          (BNX2X_5710_FW_ENGINEERING_VERSION << 24));
2781
2782                 /* read loaded FW from chip */
2783                 loaded_fw = REG_RD(sc, XSEM_REG_PRAM);
2784                 PMD_DRV_LOG(DEBUG, sc, "loaded FW 0x%08x / my FW 0x%08x",
2785                             loaded_fw, my_fw);
2786
2787                 /* abort nic load if version mismatch */
2788                 if (my_fw != loaded_fw) {
2789                         PMD_DRV_LOG(NOTICE, sc,
2790                                     "FW 0x%08x already loaded (mine is 0x%08x)",
2791                                     loaded_fw, my_fw);
2792                         return -1;
2793                 }
2794         }
2795
2796         return 0;
2797 }
2798
2799 /* mark PMF if applicable */
2800 static void bnx2x_nic_load_pmf(struct bnx2x_softc *sc, uint32_t load_code)
2801 {
2802         uint32_t ncsi_oem_data_addr;
2803
2804         PMD_INIT_FUNC_TRACE(sc);
2805
2806         if ((load_code == FW_MSG_CODE_DRV_LOAD_COMMON) ||
2807             (load_code == FW_MSG_CODE_DRV_LOAD_COMMON_CHIP) ||
2808             (load_code == FW_MSG_CODE_DRV_LOAD_PORT)) {
2809                 /*
2810                  * Barrier here for ordering between the writing to sc->port.pmf here
2811                  * and reading it from the periodic task.
2812                  */
2813                 sc->port.pmf = 1;
2814                 mb();
2815         } else {
2816                 sc->port.pmf = 0;
2817         }
2818
2819         PMD_DRV_LOG(DEBUG, sc, "pmf %d", sc->port.pmf);
2820
2821         if (load_code == FW_MSG_CODE_DRV_LOAD_COMMON_CHIP) {
2822                 if (SHMEM2_HAS(sc, ncsi_oem_data_addr)) {
2823                         ncsi_oem_data_addr = SHMEM2_RD(sc, ncsi_oem_data_addr);
2824                         if (ncsi_oem_data_addr) {
2825                                 REG_WR(sc,
2826                                        (ncsi_oem_data_addr +
2827                                         offsetof(struct glob_ncsi_oem_data,
2828                                                  driver_version)), 0);
2829                         }
2830                 }
2831         }
2832 }
2833
2834 static void bnx2x_read_mf_cfg(struct bnx2x_softc *sc)
2835 {
2836         int n = (CHIP_IS_MODE_4_PORT(sc) ? 2 : 1);
2837         int abs_func;
2838         int vn;
2839
2840         if (BNX2X_NOMCP(sc)) {
2841                 return;         /* what should be the default bvalue in this case */
2842         }
2843
2844         /*
2845          * The formula for computing the absolute function number is...
2846          * For 2 port configuration (4 functions per port):
2847          *   abs_func = 2 * vn + SC_PORT + SC_PATH
2848          * For 4 port configuration (2 functions per port):
2849          *   abs_func = 4 * vn + 2 * SC_PORT + SC_PATH
2850          */
2851         for (vn = VN_0; vn < SC_MAX_VN_NUM(sc); vn++) {
2852                 abs_func = (n * (2 * vn + SC_PORT(sc)) + SC_PATH(sc));
2853                 if (abs_func >= E1H_FUNC_MAX) {
2854                         break;
2855                 }
2856                 sc->devinfo.mf_info.mf_config[vn] =
2857                     MFCFG_RD(sc, func_mf_config[abs_func].config);
2858         }
2859
2860         if (sc->devinfo.mf_info.mf_config[SC_VN(sc)] &
2861             FUNC_MF_CFG_FUNC_DISABLED) {
2862                 PMD_DRV_LOG(DEBUG, sc, "mf_cfg function disabled");
2863                 sc->flags |= BNX2X_MF_FUNC_DIS;
2864         } else {
2865                 PMD_DRV_LOG(DEBUG, sc, "mf_cfg function enabled");
2866                 sc->flags &= ~BNX2X_MF_FUNC_DIS;
2867         }
2868 }
2869
2870 /* acquire split MCP access lock register */
2871 static int bnx2x_acquire_alr(struct bnx2x_softc *sc)
2872 {
2873         uint32_t j, val;
2874
2875         for (j = 0; j < 1000; j++) {
2876                 val = (1UL << 31);
2877                 REG_WR(sc, GRCBASE_MCP + 0x9c, val);
2878                 val = REG_RD(sc, GRCBASE_MCP + 0x9c);
2879                 if (val & (1L << 31))
2880                         break;
2881
2882                 DELAY(5000);
2883         }
2884
2885         if (!(val & (1L << 31))) {
2886                 PMD_DRV_LOG(NOTICE, sc, "Cannot acquire MCP access lock register");
2887                 return -1;
2888         }
2889
2890         return 0;
2891 }
2892
2893 /* release split MCP access lock register */
2894 static void bnx2x_release_alr(struct bnx2x_softc *sc)
2895 {
2896         REG_WR(sc, GRCBASE_MCP + 0x9c, 0);
2897 }
2898
2899 static void bnx2x_fan_failure(struct bnx2x_softc *sc)
2900 {
2901         int port = SC_PORT(sc);
2902         uint32_t ext_phy_config;
2903
2904         /* mark the failure */
2905         ext_phy_config =
2906             SHMEM_RD(sc, dev_info.port_hw_config[port].external_phy_config);
2907
2908         ext_phy_config &= ~PORT_HW_CFG_XGXS_EXT_PHY_TYPE_MASK;
2909         ext_phy_config |= PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE;
2910         SHMEM_WR(sc, dev_info.port_hw_config[port].external_phy_config,
2911                  ext_phy_config);
2912
2913         /* log the failure */
2914         PMD_DRV_LOG(INFO, sc,
2915                     "Fan Failure has caused the driver to shutdown "
2916                     "the card to prevent permanent damage. "
2917                     "Please contact OEM Support for assistance");
2918
2919         rte_panic("Schedule task to handle fan failure");
2920 }
2921
2922 /* this function is called upon a link interrupt */
2923 static void bnx2x_link_attn(struct bnx2x_softc *sc)
2924 {
2925         uint32_t pause_enabled = 0;
2926         struct host_port_stats *pstats;
2927         int cmng_fns;
2928
2929         /* Make sure that we are synced with the current statistics */
2930         bnx2x_stats_handle(sc, STATS_EVENT_STOP);
2931
2932         elink_link_update(&sc->link_params, &sc->link_vars);
2933
2934         if (sc->link_vars.link_up) {
2935
2936                 /* dropless flow control */
2937                 if (sc->dropless_fc) {
2938                         pause_enabled = 0;
2939
2940                         if (sc->link_vars.flow_ctrl & ELINK_FLOW_CTRL_TX) {
2941                                 pause_enabled = 1;
2942                         }
2943
2944                         REG_WR(sc,
2945                                (BAR_USTRORM_INTMEM +
2946                                 USTORM_ETH_PAUSE_ENABLED_OFFSET(SC_PORT(sc))),
2947                                pause_enabled);
2948                 }
2949
2950                 if (sc->link_vars.mac_type != ELINK_MAC_TYPE_EMAC) {
2951                         pstats = BNX2X_SP(sc, port_stats);
2952                         /* reset old mac stats */
2953                         memset(&(pstats->mac_stx[0]), 0,
2954                                sizeof(struct mac_stx));
2955                 }
2956
2957                 if (sc->state == BNX2X_STATE_OPEN) {
2958                         bnx2x_stats_handle(sc, STATS_EVENT_LINK_UP);
2959                 }
2960         }
2961
2962         if (sc->link_vars.link_up && sc->link_vars.line_speed) {
2963                 cmng_fns = bnx2x_get_cmng_fns_mode(sc);
2964
2965                 if (cmng_fns != CMNG_FNS_NONE) {
2966                         bnx2x_cmng_fns_init(sc, FALSE, cmng_fns);
2967                         storm_memset_cmng(sc, &sc->cmng, SC_PORT(sc));
2968                 }
2969         }
2970
2971         bnx2x_link_report_locked(sc);
2972
2973         if (IS_MF(sc)) {
2974                 bnx2x_link_sync_notify(sc);
2975         }
2976 }
2977
2978 static void bnx2x_attn_int_asserted(struct bnx2x_softc *sc, uint32_t asserted)
2979 {
2980         int port = SC_PORT(sc);
2981         uint32_t aeu_addr = port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 :
2982             MISC_REG_AEU_MASK_ATTN_FUNC_0;
2983         uint32_t nig_int_mask_addr = port ? NIG_REG_MASK_INTERRUPT_PORT1 :
2984             NIG_REG_MASK_INTERRUPT_PORT0;
2985         uint32_t aeu_mask;
2986         uint32_t nig_mask = 0;
2987         uint32_t reg_addr;
2988         uint32_t igu_acked;
2989         uint32_t cnt;
2990
2991         if (sc->attn_state & asserted) {
2992                 PMD_DRV_LOG(ERR, sc, "IGU ERROR attn=0x%08x", asserted);
2993         }
2994
2995         bnx2x_acquire_hw_lock(sc, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
2996
2997         aeu_mask = REG_RD(sc, aeu_addr);
2998
2999         aeu_mask &= ~(asserted & 0x3ff);
3000
3001         REG_WR(sc, aeu_addr, aeu_mask);
3002
3003         bnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
3004
3005         sc->attn_state |= asserted;
3006
3007         if (asserted & ATTN_HARD_WIRED_MASK) {
3008                 if (asserted & ATTN_NIG_FOR_FUNC) {
3009
3010                         bnx2x_acquire_phy_lock(sc);
3011                         /* save nig interrupt mask */
3012                         nig_mask = REG_RD(sc, nig_int_mask_addr);
3013
3014                         /* If nig_mask is not set, no need to call the update function */
3015                         if (nig_mask) {
3016                                 REG_WR(sc, nig_int_mask_addr, 0);
3017
3018                                 bnx2x_link_attn(sc);
3019                         }
3020
3021                         /* handle unicore attn? */
3022                 }
3023
3024                 if (asserted & ATTN_SW_TIMER_4_FUNC) {
3025                         PMD_DRV_LOG(DEBUG, sc, "ATTN_SW_TIMER_4_FUNC!");
3026                 }
3027
3028                 if (asserted & GPIO_2_FUNC) {
3029                         PMD_DRV_LOG(DEBUG, sc, "GPIO_2_FUNC!");
3030                 }
3031
3032                 if (asserted & GPIO_3_FUNC) {
3033                         PMD_DRV_LOG(DEBUG, sc, "GPIO_3_FUNC!");
3034                 }
3035
3036                 if (asserted & GPIO_4_FUNC) {
3037                         PMD_DRV_LOG(DEBUG, sc, "GPIO_4_FUNC!");
3038                 }
3039
3040                 if (port == 0) {
3041                         if (asserted & ATTN_GENERAL_ATTN_1) {
3042                                 PMD_DRV_LOG(DEBUG, sc, "ATTN_GENERAL_ATTN_1!");
3043                                 REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_1, 0x0);
3044                         }
3045                         if (asserted & ATTN_GENERAL_ATTN_2) {
3046                                 PMD_DRV_LOG(DEBUG, sc, "ATTN_GENERAL_ATTN_2!");
3047                                 REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_2, 0x0);
3048                         }
3049                         if (asserted & ATTN_GENERAL_ATTN_3) {
3050                                 PMD_DRV_LOG(DEBUG, sc, "ATTN_GENERAL_ATTN_3!");
3051                                 REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_3, 0x0);
3052                         }
3053                 } else {
3054                         if (asserted & ATTN_GENERAL_ATTN_4) {
3055                                 PMD_DRV_LOG(DEBUG, sc, "ATTN_GENERAL_ATTN_4!");
3056                                 REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_4, 0x0);
3057                         }
3058                         if (asserted & ATTN_GENERAL_ATTN_5) {
3059                                 PMD_DRV_LOG(DEBUG, sc, "ATTN_GENERAL_ATTN_5!");
3060                                 REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_5, 0x0);
3061                         }
3062                         if (asserted & ATTN_GENERAL_ATTN_6) {
3063                                 PMD_DRV_LOG(DEBUG, sc, "ATTN_GENERAL_ATTN_6!");
3064                                 REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_6, 0x0);
3065                         }
3066                 }
3067         }
3068         /* hardwired */
3069         if (sc->devinfo.int_block == INT_BLOCK_HC) {
3070                 reg_addr =
3071                     (HC_REG_COMMAND_REG + port * 32 +
3072                      COMMAND_REG_ATTN_BITS_SET);
3073         } else {
3074                 reg_addr = (BAR_IGU_INTMEM + IGU_CMD_ATTN_BIT_SET_UPPER * 8);
3075         }
3076
3077         PMD_DRV_LOG(DEBUG, sc, "about to mask 0x%08x at %s addr 0x%08x",
3078                     asserted,
3079                     (sc->devinfo.int_block == INT_BLOCK_HC) ? "HC" : "IGU",
3080                     reg_addr);
3081         REG_WR(sc, reg_addr, asserted);
3082
3083         /* now set back the mask */
3084         if (asserted & ATTN_NIG_FOR_FUNC) {
3085                 /*
3086                  * Verify that IGU ack through BAR was written before restoring
3087                  * NIG mask. This loop should exit after 2-3 iterations max.
3088                  */
3089                 if (sc->devinfo.int_block != INT_BLOCK_HC) {
3090                         cnt = 0;
3091
3092                         do {
3093                                 igu_acked =
3094                                     REG_RD(sc, IGU_REG_ATTENTION_ACK_BITS);
3095                         } while (((igu_acked & ATTN_NIG_FOR_FUNC) == 0)
3096                                  && (++cnt < MAX_IGU_ATTN_ACK_TO));
3097
3098                         if (!igu_acked) {
3099                                 PMD_DRV_LOG(ERR, sc,
3100                                             "Failed to verify IGU ack on time");
3101                         }
3102
3103                         mb();
3104                 }
3105
3106                 REG_WR(sc, nig_int_mask_addr, nig_mask);
3107
3108                 bnx2x_release_phy_lock(sc);
3109         }
3110 }
3111
3112 static void
3113 bnx2x_print_next_block(__rte_unused struct bnx2x_softc *sc, __rte_unused int idx,
3114                      __rte_unused const char *blk)
3115 {
3116         PMD_DRV_LOG(INFO, sc, "%s%s", idx ? ", " : "", blk);
3117 }
3118
3119 static int
3120 bnx2x_check_blocks_with_parity0(struct bnx2x_softc *sc, uint32_t sig, int par_num,
3121                               uint8_t print)
3122 {
3123         uint32_t cur_bit = 0;
3124         int i = 0;
3125
3126         for (i = 0; sig; i++) {
3127                 cur_bit = ((uint32_t) 0x1 << i);
3128                 if (sig & cur_bit) {
3129                         switch (cur_bit) {
3130                         case AEU_INPUTS_ATTN_BITS_BRB_PARITY_ERROR:
3131                                 if (print)
3132                                         bnx2x_print_next_block(sc, par_num++,
3133                                                              "BRB");
3134                                 break;
3135                         case AEU_INPUTS_ATTN_BITS_PARSER_PARITY_ERROR:
3136                                 if (print)
3137                                         bnx2x_print_next_block(sc, par_num++,
3138                                                              "PARSER");
3139                                 break;
3140                         case AEU_INPUTS_ATTN_BITS_TSDM_PARITY_ERROR:
3141                                 if (print)
3142                                         bnx2x_print_next_block(sc, par_num++,
3143                                                              "TSDM");
3144                                 break;
3145                         case AEU_INPUTS_ATTN_BITS_SEARCHER_PARITY_ERROR:
3146                                 if (print)
3147                                         bnx2x_print_next_block(sc, par_num++,
3148                                                              "SEARCHER");
3149                                 break;
3150                         case AEU_INPUTS_ATTN_BITS_TCM_PARITY_ERROR:
3151                                 if (print)
3152                                         bnx2x_print_next_block(sc, par_num++,
3153                                                              "TCM");
3154                                 break;
3155                         case AEU_INPUTS_ATTN_BITS_TSEMI_PARITY_ERROR:
3156                                 if (print)
3157                                         bnx2x_print_next_block(sc, par_num++,
3158                                                              "TSEMI");
3159                                 break;
3160                         case AEU_INPUTS_ATTN_BITS_PBCLIENT_PARITY_ERROR:
3161                                 if (print)
3162                                         bnx2x_print_next_block(sc, par_num++,
3163                                                              "XPB");
3164                                 break;
3165                         }
3166
3167                         /* Clear the bit */
3168                         sig &= ~cur_bit;
3169                 }
3170         }
3171
3172         return par_num;
3173 }
3174
3175 static int
3176 bnx2x_check_blocks_with_parity1(struct bnx2x_softc *sc, uint32_t sig, int par_num,
3177                               uint8_t * global, uint8_t print)
3178 {
3179         int i = 0;
3180         uint32_t cur_bit = 0;
3181         for (i = 0; sig; i++) {
3182                 cur_bit = ((uint32_t) 0x1 << i);
3183                 if (sig & cur_bit) {
3184                         switch (cur_bit) {
3185                         case AEU_INPUTS_ATTN_BITS_PBF_PARITY_ERROR:
3186                                 if (print)
3187                                         bnx2x_print_next_block(sc, par_num++,
3188                                                              "PBF");
3189                                 break;
3190                         case AEU_INPUTS_ATTN_BITS_QM_PARITY_ERROR:
3191                                 if (print)
3192                                         bnx2x_print_next_block(sc, par_num++,
3193                                                              "QM");
3194                                 break;
3195                         case AEU_INPUTS_ATTN_BITS_TIMERS_PARITY_ERROR:
3196                                 if (print)
3197                                         bnx2x_print_next_block(sc, par_num++,
3198                                                              "TM");
3199                                 break;
3200                         case AEU_INPUTS_ATTN_BITS_XSDM_PARITY_ERROR:
3201                                 if (print)
3202                                         bnx2x_print_next_block(sc, par_num++,
3203                                                              "XSDM");
3204                                 break;
3205                         case AEU_INPUTS_ATTN_BITS_XCM_PARITY_ERROR:
3206                                 if (print)
3207                                         bnx2x_print_next_block(sc, par_num++,
3208                                                              "XCM");
3209                                 break;
3210                         case AEU_INPUTS_ATTN_BITS_XSEMI_PARITY_ERROR:
3211                                 if (print)
3212                                         bnx2x_print_next_block(sc, par_num++,
3213                                                              "XSEMI");
3214                                 break;
3215                         case AEU_INPUTS_ATTN_BITS_DOORBELLQ_PARITY_ERROR:
3216                                 if (print)
3217                                         bnx2x_print_next_block(sc, par_num++,
3218                                                              "DOORBELLQ");
3219                                 break;
3220                         case AEU_INPUTS_ATTN_BITS_NIG_PARITY_ERROR:
3221                                 if (print)
3222                                         bnx2x_print_next_block(sc, par_num++,
3223                                                              "NIG");
3224                                 break;
3225                         case AEU_INPUTS_ATTN_BITS_VAUX_PCI_CORE_PARITY_ERROR:
3226                                 if (print)
3227                                         bnx2x_print_next_block(sc, par_num++,
3228                                                              "VAUX PCI CORE");
3229                                 *global = TRUE;
3230                                 break;
3231                         case AEU_INPUTS_ATTN_BITS_DEBUG_PARITY_ERROR:
3232                                 if (print)
3233                                         bnx2x_print_next_block(sc, par_num++,
3234                                                              "DEBUG");
3235                                 break;
3236                         case AEU_INPUTS_ATTN_BITS_USDM_PARITY_ERROR:
3237                                 if (print)
3238                                         bnx2x_print_next_block(sc, par_num++,
3239                                                              "USDM");
3240                                 break;
3241                         case AEU_INPUTS_ATTN_BITS_UCM_PARITY_ERROR:
3242                                 if (print)
3243                                         bnx2x_print_next_block(sc, par_num++,
3244                                                              "UCM");
3245                                 break;
3246                         case AEU_INPUTS_ATTN_BITS_USEMI_PARITY_ERROR:
3247                                 if (print)
3248                                         bnx2x_print_next_block(sc, par_num++,
3249                                                              "USEMI");
3250                                 break;
3251                         case AEU_INPUTS_ATTN_BITS_UPB_PARITY_ERROR:
3252                                 if (print)
3253                                         bnx2x_print_next_block(sc, par_num++,
3254                                                              "UPB");
3255                                 break;
3256                         case AEU_INPUTS_ATTN_BITS_CSDM_PARITY_ERROR:
3257                                 if (print)
3258                                         bnx2x_print_next_block(sc, par_num++,
3259                                                              "CSDM");
3260                                 break;
3261                         case AEU_INPUTS_ATTN_BITS_CCM_PARITY_ERROR:
3262                                 if (print)
3263                                         bnx2x_print_next_block(sc, par_num++,
3264                                                              "CCM");
3265                                 break;
3266                         }
3267
3268                         /* Clear the bit */
3269                         sig &= ~cur_bit;
3270                 }
3271         }
3272
3273         return par_num;
3274 }
3275
3276 static int
3277 bnx2x_check_blocks_with_parity2(struct bnx2x_softc *sc, uint32_t sig, int par_num,
3278                               uint8_t print)
3279 {
3280         uint32_t cur_bit = 0;
3281         int i = 0;
3282
3283         for (i = 0; sig; i++) {
3284                 cur_bit = ((uint32_t) 0x1 << i);
3285                 if (sig & cur_bit) {
3286                         switch (cur_bit) {
3287                         case AEU_INPUTS_ATTN_BITS_CSEMI_PARITY_ERROR:
3288                                 if (print)
3289                                         bnx2x_print_next_block(sc, par_num++,
3290                                                              "CSEMI");
3291                                 break;
3292                         case AEU_INPUTS_ATTN_BITS_PXP_PARITY_ERROR:
3293                                 if (print)
3294                                         bnx2x_print_next_block(sc, par_num++,
3295                                                              "PXP");
3296                                 break;
3297                         case AEU_IN_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR:
3298                                 if (print)
3299                                         bnx2x_print_next_block(sc, par_num++,
3300                                                              "PXPPCICLOCKCLIENT");
3301                                 break;
3302                         case AEU_INPUTS_ATTN_BITS_CFC_PARITY_ERROR:
3303                                 if (print)
3304                                         bnx2x_print_next_block(sc, par_num++,
3305                                                              "CFC");
3306                                 break;
3307                         case AEU_INPUTS_ATTN_BITS_CDU_PARITY_ERROR:
3308                                 if (print)
3309                                         bnx2x_print_next_block(sc, par_num++,
3310                                                              "CDU");
3311                                 break;
3312                         case AEU_INPUTS_ATTN_BITS_DMAE_PARITY_ERROR:
3313                                 if (print)
3314                                         bnx2x_print_next_block(sc, par_num++,
3315                                                              "DMAE");
3316                                 break;
3317                         case AEU_INPUTS_ATTN_BITS_IGU_PARITY_ERROR:
3318                                 if (print)
3319                                         bnx2x_print_next_block(sc, par_num++,
3320                                                              "IGU");
3321                                 break;
3322                         case AEU_INPUTS_ATTN_BITS_MISC_PARITY_ERROR:
3323                                 if (print)
3324                                         bnx2x_print_next_block(sc, par_num++,
3325                                                              "MISC");
3326                                 break;
3327                         }
3328
3329                         /* Clear the bit */
3330                         sig &= ~cur_bit;
3331                 }
3332         }
3333
3334         return par_num;
3335 }
3336
3337 static int
3338 bnx2x_check_blocks_with_parity3(struct bnx2x_softc *sc, uint32_t sig, int par_num,
3339                               uint8_t * global, uint8_t print)
3340 {
3341         uint32_t cur_bit = 0;
3342         int i = 0;
3343
3344         for (i = 0; sig; i++) {
3345                 cur_bit = ((uint32_t) 0x1 << i);
3346                 if (sig & cur_bit) {
3347                         switch (cur_bit) {
3348                         case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_ROM_PARITY:
3349                                 if (print)
3350                                         bnx2x_print_next_block(sc, par_num++,
3351                                                              "MCP ROM");
3352                                 *global = TRUE;
3353                                 break;
3354                         case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_RX_PARITY:
3355                                 if (print)
3356                                         bnx2x_print_next_block(sc, par_num++,
3357                                                              "MCP UMP RX");
3358                                 *global = TRUE;
3359                                 break;
3360                         case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_TX_PARITY:
3361                                 if (print)
3362                                         bnx2x_print_next_block(sc, par_num++,
3363                                                              "MCP UMP TX");
3364                                 *global = TRUE;
3365                                 break;
3366                         case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_SCPAD_PARITY:
3367                                 if (print)
3368                                         bnx2x_print_next_block(sc, par_num++,
3369                                                              "MCP SCPAD");
3370                                 *global = TRUE;
3371                                 break;
3372                         }
3373
3374                         /* Clear the bit */
3375                         sig &= ~cur_bit;
3376                 }
3377         }
3378
3379         return par_num;
3380 }
3381
3382 static int
3383 bnx2x_check_blocks_with_parity4(struct bnx2x_softc *sc, uint32_t sig, int par_num,
3384                               uint8_t print)
3385 {
3386         uint32_t cur_bit = 0;
3387         int i = 0;
3388
3389         for (i = 0; sig; i++) {
3390                 cur_bit = ((uint32_t) 0x1 << i);
3391                 if (sig & cur_bit) {
3392                         switch (cur_bit) {
3393                         case AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR:
3394                                 if (print)
3395                                         bnx2x_print_next_block(sc, par_num++,
3396                                                              "PGLUE_B");
3397                                 break;
3398                         case AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR:
3399                                 if (print)
3400                                         bnx2x_print_next_block(sc, par_num++,
3401                                                              "ATC");
3402                                 break;
3403                         }
3404
3405                         /* Clear the bit */
3406                         sig &= ~cur_bit;
3407                 }
3408         }
3409
3410         return par_num;
3411 }
3412
3413 static uint8_t
3414 bnx2x_parity_attn(struct bnx2x_softc *sc, uint8_t * global, uint8_t print,
3415                 uint32_t * sig)
3416 {
3417         int par_num = 0;
3418
3419         if ((sig[0] & HW_PRTY_ASSERT_SET_0) ||
3420             (sig[1] & HW_PRTY_ASSERT_SET_1) ||
3421             (sig[2] & HW_PRTY_ASSERT_SET_2) ||
3422             (sig[3] & HW_PRTY_ASSERT_SET_3) ||
3423             (sig[4] & HW_PRTY_ASSERT_SET_4)) {
3424                 PMD_DRV_LOG(ERR, sc,
3425                             "Parity error: HW block parity attention:"
3426                             "[0]:0x%08x [1]:0x%08x [2]:0x%08x [3]:0x%08x [4]:0x%08x",
3427                             (uint32_t) (sig[0] & HW_PRTY_ASSERT_SET_0),
3428                             (uint32_t) (sig[1] & HW_PRTY_ASSERT_SET_1),
3429                             (uint32_t) (sig[2] & HW_PRTY_ASSERT_SET_2),
3430                             (uint32_t) (sig[3] & HW_PRTY_ASSERT_SET_3),
3431                             (uint32_t) (sig[4] & HW_PRTY_ASSERT_SET_4));
3432
3433                 if (print)
3434                         PMD_DRV_LOG(INFO, sc, "Parity errors detected in blocks: ");
3435
3436                 par_num =
3437                     bnx2x_check_blocks_with_parity0(sc, sig[0] &
3438                                                   HW_PRTY_ASSERT_SET_0,
3439                                                   par_num, print);
3440                 par_num =
3441                     bnx2x_check_blocks_with_parity1(sc, sig[1] &
3442                                                   HW_PRTY_ASSERT_SET_1,
3443                                                   par_num, global, print);
3444                 par_num =
3445                     bnx2x_check_blocks_with_parity2(sc, sig[2] &
3446                                                   HW_PRTY_ASSERT_SET_2,
3447                                                   par_num, print);
3448                 par_num =
3449                     bnx2x_check_blocks_with_parity3(sc, sig[3] &
3450                                                   HW_PRTY_ASSERT_SET_3,
3451                                                   par_num, global, print);
3452                 par_num =
3453                     bnx2x_check_blocks_with_parity4(sc, sig[4] &
3454                                                   HW_PRTY_ASSERT_SET_4,
3455                                                   par_num, print);
3456
3457                 if (print)
3458                         PMD_DRV_LOG(INFO, sc, "");
3459
3460                 return TRUE;
3461         }
3462
3463         return FALSE;
3464 }
3465
3466 static uint8_t
3467 bnx2x_chk_parity_attn(struct bnx2x_softc *sc, uint8_t * global, uint8_t print)
3468 {
3469         struct attn_route attn = { {0} };
3470         int port = SC_PORT(sc);
3471
3472         attn.sig[0] = REG_RD(sc, MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 + port * 4);
3473         attn.sig[1] = REG_RD(sc, MISC_REG_AEU_AFTER_INVERT_2_FUNC_0 + port * 4);
3474         attn.sig[2] = REG_RD(sc, MISC_REG_AEU_AFTER_INVERT_3_FUNC_0 + port * 4);
3475         attn.sig[3] = REG_RD(sc, MISC_REG_AEU_AFTER_INVERT_4_FUNC_0 + port * 4);
3476
3477         if (!CHIP_IS_E1x(sc))
3478                 attn.sig[4] =
3479                     REG_RD(sc, MISC_REG_AEU_AFTER_INVERT_5_FUNC_0 + port * 4);
3480
3481         return bnx2x_parity_attn(sc, global, print, attn.sig);
3482 }
3483
3484 static void bnx2x_attn_int_deasserted4(struct bnx2x_softc *sc, uint32_t attn)
3485 {
3486         uint32_t val;
3487
3488         if (attn & AEU_INPUTS_ATTN_BITS_PGLUE_HW_INTERRUPT) {
3489                 val = REG_RD(sc, PGLUE_B_REG_PGLUE_B_INT_STS_CLR);
3490                 PMD_DRV_LOG(INFO, sc, "ERROR: PGLUE hw attention 0x%08x", val);
3491                 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_ADDRESS_ERROR)
3492                         PMD_DRV_LOG(INFO, sc,
3493                                     "ERROR: PGLUE_B_PGLUE_B_INT_STS_REG_ADDRESS_ERROR");
3494                 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_INCORRECT_RCV_BEHAVIOR)
3495                         PMD_DRV_LOG(INFO, sc,
3496                                     "ERROR: PGLUE_B_PGLUE_B_INT_STS_REG_INCORRECT_RCV_BEHAVIOR");
3497                 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_WAS_ERROR_ATTN)
3498                         PMD_DRV_LOG(INFO, sc,
3499                                     "ERROR: PGLUE_B_PGLUE_B_INT_STS_REG_WAS_ERROR_ATTN");
3500                 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_VF_LENGTH_VIOLATION_ATTN)
3501                         PMD_DRV_LOG(INFO, sc,
3502                                     "ERROR: PGLUE_B_PGLUE_B_INT_STS_REG_VF_LENGTH_VIOLATION_ATTN");
3503                 if (val &
3504                     PGLUE_B_PGLUE_B_INT_STS_REG_VF_GRC_SPACE_VIOLATION_ATTN)
3505                         PMD_DRV_LOG(INFO, sc,
3506                                     "ERROR: PGLUE_B_PGLUE_B_INT_STS_REG_VF_GRC_SPACE_VIOLATION_ATTN");
3507                 if (val &
3508                     PGLUE_B_PGLUE_B_INT_STS_REG_VF_MSIX_BAR_VIOLATION_ATTN)
3509                         PMD_DRV_LOG(INFO, sc,
3510                                     "ERROR: PGLUE_B_PGLUE_B_INT_STS_REG_VF_MSIX_BAR_VIOLATION_ATTN");
3511                 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_ERROR_ATTN)
3512                         PMD_DRV_LOG(INFO, sc,
3513                                     "ERROR: PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_ERROR_ATTN");
3514                 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_IN_TWO_RCBS_ATTN)
3515                         PMD_DRV_LOG(INFO, sc,
3516                                     "ERROR: PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_IN_TWO_RCBS_ATTN");
3517                 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_CSSNOOP_FIFO_OVERFLOW)
3518                         PMD_DRV_LOG(INFO, sc,
3519                                     "ERROR: PGLUE_B_PGLUE_B_INT_STS_REG_CSSNOOP_FIFO_OVERFLOW");
3520         }
3521
3522         if (attn & AEU_INPUTS_ATTN_BITS_ATC_HW_INTERRUPT) {
3523                 val = REG_RD(sc, ATC_REG_ATC_INT_STS_CLR);
3524                 PMD_DRV_LOG(INFO, sc, "ERROR: ATC hw attention 0x%08x", val);
3525                 if (val & ATC_ATC_INT_STS_REG_ADDRESS_ERROR)
3526                         PMD_DRV_LOG(INFO, sc,
3527                                     "ERROR: ATC_ATC_INT_STS_REG_ADDRESS_ERROR");
3528                 if (val & ATC_ATC_INT_STS_REG_ATC_TCPL_TO_NOT_PEND)
3529                         PMD_DRV_LOG(INFO, sc,
3530                                     "ERROR: ATC_ATC_INT_STS_REG_ATC_TCPL_TO_NOT_PEND");
3531                 if (val & ATC_ATC_INT_STS_REG_ATC_GPA_MULTIPLE_HITS)
3532                         PMD_DRV_LOG(INFO, sc,
3533                                     "ERROR: ATC_ATC_INT_STS_REG_ATC_GPA_MULTIPLE_HITS");
3534                 if (val & ATC_ATC_INT_STS_REG_ATC_RCPL_TO_EMPTY_CNT)
3535                         PMD_DRV_LOG(INFO, sc,
3536                                     "ERROR: ATC_ATC_INT_STS_REG_ATC_RCPL_TO_EMPTY_CNT");
3537                 if (val & ATC_ATC_INT_STS_REG_ATC_TCPL_ERROR)
3538                         PMD_DRV_LOG(INFO, sc,
3539                                     "ERROR: ATC_ATC_INT_STS_REG_ATC_TCPL_ERROR");
3540                 if (val & ATC_ATC_INT_STS_REG_ATC_IREQ_LESS_THAN_STU)
3541                         PMD_DRV_LOG(INFO, sc,
3542                                     "ERROR: ATC_ATC_INT_STS_REG_ATC_IREQ_LESS_THAN_STU");
3543         }
3544
3545         if (attn & (AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR |
3546                     AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR)) {
3547                 PMD_DRV_LOG(INFO, sc,
3548                             "ERROR: FATAL parity attention set4 0x%08x",
3549                             (uint32_t) (attn &
3550                                         (AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR
3551                                          |
3552                                          AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR)));
3553         }
3554 }
3555
3556 static void bnx2x_e1h_disable(struct bnx2x_softc *sc)
3557 {
3558         int port = SC_PORT(sc);
3559
3560         REG_WR(sc, NIG_REG_LLH0_FUNC_EN + port * 8, 0);
3561 }
3562
3563 static void bnx2x_e1h_enable(struct bnx2x_softc *sc)
3564 {
3565         int port = SC_PORT(sc);
3566
3567         REG_WR(sc, NIG_REG_LLH0_FUNC_EN + port * 8, 1);
3568 }
3569
3570 /*
3571  * called due to MCP event (on pmf):
3572  *   reread new bandwidth configuration
3573  *   configure FW
3574  *   notify others function about the change
3575  */
3576 static void bnx2x_config_mf_bw(struct bnx2x_softc *sc)
3577 {
3578         if (sc->link_vars.link_up) {
3579                 bnx2x_cmng_fns_init(sc, TRUE, CMNG_FNS_MINMAX);
3580                 bnx2x_link_sync_notify(sc);
3581         }
3582
3583         storm_memset_cmng(sc, &sc->cmng, SC_PORT(sc));
3584 }
3585
3586 static void bnx2x_set_mf_bw(struct bnx2x_softc *sc)
3587 {
3588         bnx2x_config_mf_bw(sc);
3589         bnx2x_fw_command(sc, DRV_MSG_CODE_SET_MF_BW_ACK, 0);
3590 }
3591
3592 static void bnx2x_handle_eee_event(struct bnx2x_softc *sc)
3593 {
3594         bnx2x_fw_command(sc, DRV_MSG_CODE_EEE_RESULTS_ACK, 0);
3595 }
3596
3597 #define DRV_INFO_ETH_STAT_NUM_MACS_REQUIRED 3
3598
3599 static void bnx2x_drv_info_ether_stat(struct bnx2x_softc *sc)
3600 {
3601         struct eth_stats_info *ether_stat = &sc->sp->drv_info_to_mcp.ether_stat;
3602
3603         strncpy(ether_stat->version, BNX2X_DRIVER_VERSION,
3604                 ETH_STAT_INFO_VERSION_LEN);
3605
3606         sc->sp_objs[0].mac_obj.get_n_elements(sc, &sc->sp_objs[0].mac_obj,
3607                                               DRV_INFO_ETH_STAT_NUM_MACS_REQUIRED,
3608                                               ether_stat->mac_local + MAC_PAD,
3609                                               MAC_PAD, ETH_ALEN);
3610
3611         ether_stat->mtu_size = sc->mtu;
3612
3613         ether_stat->feature_flags |= FEATURE_ETH_CHKSUM_OFFLOAD_MASK;
3614         ether_stat->promiscuous_mode = 0;       // (flags & PROMISC) ? 1 : 0;
3615
3616         ether_stat->txq_size = sc->tx_ring_size;
3617         ether_stat->rxq_size = sc->rx_ring_size;
3618 }
3619
3620 static void bnx2x_handle_drv_info_req(struct bnx2x_softc *sc)
3621 {
3622         enum drv_info_opcode op_code;
3623         uint32_t drv_info_ctl = SHMEM2_RD(sc, drv_info_control);
3624
3625         /* if drv_info version supported by MFW doesn't match - send NACK */
3626         if ((drv_info_ctl & DRV_INFO_CONTROL_VER_MASK) != DRV_INFO_CUR_VER) {
3627                 bnx2x_fw_command(sc, DRV_MSG_CODE_DRV_INFO_NACK, 0);
3628                 return;
3629         }
3630
3631         op_code = ((drv_info_ctl & DRV_INFO_CONTROL_OP_CODE_MASK) >>
3632                    DRV_INFO_CONTROL_OP_CODE_SHIFT);
3633
3634         memset(&sc->sp->drv_info_to_mcp, 0, sizeof(union drv_info_to_mcp));
3635
3636         switch (op_code) {
3637         case ETH_STATS_OPCODE:
3638                 bnx2x_drv_info_ether_stat(sc);
3639                 break;
3640         case FCOE_STATS_OPCODE:
3641         case ISCSI_STATS_OPCODE:
3642         default:
3643                 /* if op code isn't supported - send NACK */
3644                 bnx2x_fw_command(sc, DRV_MSG_CODE_DRV_INFO_NACK, 0);
3645                 return;
3646         }
3647
3648         /*
3649          * If we got drv_info attn from MFW then these fields are defined in
3650          * shmem2 for sure
3651          */
3652         SHMEM2_WR(sc, drv_info_host_addr_lo,
3653                   U64_LO(BNX2X_SP_MAPPING(sc, drv_info_to_mcp)));
3654         SHMEM2_WR(sc, drv_info_host_addr_hi,
3655                   U64_HI(BNX2X_SP_MAPPING(sc, drv_info_to_mcp)));
3656
3657         bnx2x_fw_command(sc, DRV_MSG_CODE_DRV_INFO_ACK, 0);
3658 }
3659
3660 static void bnx2x_dcc_event(struct bnx2x_softc *sc, uint32_t dcc_event)
3661 {
3662         if (dcc_event & DRV_STATUS_DCC_DISABLE_ENABLE_PF) {
3663 /*
3664  * This is the only place besides the function initialization
3665  * where the sc->flags can change so it is done without any
3666  * locks
3667  */
3668                 if (sc->devinfo.
3669                     mf_info.mf_config[SC_VN(sc)] & FUNC_MF_CFG_FUNC_DISABLED) {
3670                         PMD_DRV_LOG(DEBUG, sc, "mf_cfg function disabled");
3671                         sc->flags |= BNX2X_MF_FUNC_DIS;
3672                         bnx2x_e1h_disable(sc);
3673                 } else {
3674                         PMD_DRV_LOG(DEBUG, sc, "mf_cfg function enabled");
3675                         sc->flags &= ~BNX2X_MF_FUNC_DIS;
3676                         bnx2x_e1h_enable(sc);
3677                 }
3678                 dcc_event &= ~DRV_STATUS_DCC_DISABLE_ENABLE_PF;
3679         }
3680
3681         if (dcc_event & DRV_STATUS_DCC_BANDWIDTH_ALLOCATION) {
3682                 bnx2x_config_mf_bw(sc);
3683                 dcc_event &= ~DRV_STATUS_DCC_BANDWIDTH_ALLOCATION;
3684         }
3685
3686         /* Report results to MCP */
3687         if (dcc_event)
3688                 bnx2x_fw_command(sc, DRV_MSG_CODE_DCC_FAILURE, 0);
3689         else
3690                 bnx2x_fw_command(sc, DRV_MSG_CODE_DCC_OK, 0);
3691 }
3692
3693 static void bnx2x_pmf_update(struct bnx2x_softc *sc)
3694 {
3695         int port = SC_PORT(sc);
3696         uint32_t val;
3697
3698         sc->port.pmf = 1;
3699
3700         /*
3701          * We need the mb() to ensure the ordering between the writing to
3702          * sc->port.pmf here and reading it from the bnx2x_periodic_task().
3703          */
3704         mb();
3705
3706         /* enable nig attention */
3707         val = (0xff0f | (1 << (SC_VN(sc) + 4)));
3708         if (sc->devinfo.int_block == INT_BLOCK_HC) {
3709                 REG_WR(sc, HC_REG_TRAILING_EDGE_0 + port * 8, val);
3710                 REG_WR(sc, HC_REG_LEADING_EDGE_0 + port * 8, val);
3711         } else if (!CHIP_IS_E1x(sc)) {
3712                 REG_WR(sc, IGU_REG_TRAILING_EDGE_LATCH, val);
3713                 REG_WR(sc, IGU_REG_LEADING_EDGE_LATCH, val);
3714         }
3715
3716         bnx2x_stats_handle(sc, STATS_EVENT_PMF);
3717 }
3718
3719 static int bnx2x_mc_assert(struct bnx2x_softc *sc)
3720 {
3721         char last_idx;
3722         int i, rc = 0;
3723         __rte_unused uint32_t row0, row1, row2, row3;
3724
3725         /* XSTORM */
3726         last_idx =
3727             REG_RD8(sc, BAR_XSTRORM_INTMEM + XSTORM_ASSERT_LIST_INDEX_OFFSET);
3728         if (last_idx)
3729                 PMD_DRV_LOG(ERR, sc, "XSTORM_ASSERT_LIST_INDEX 0x%x", last_idx);
3730
3731         /* print the asserts */
3732         for (i = 0; i < STORM_ASSERT_ARRAY_SIZE; i++) {
3733
3734                 row0 =
3735                     REG_RD(sc,
3736                            BAR_XSTRORM_INTMEM + XSTORM_ASSERT_LIST_OFFSET(i));
3737                 row1 =
3738                     REG_RD(sc,
3739                            BAR_XSTRORM_INTMEM + XSTORM_ASSERT_LIST_OFFSET(i) +
3740                            4);
3741                 row2 =
3742                     REG_RD(sc,
3743                            BAR_XSTRORM_INTMEM + XSTORM_ASSERT_LIST_OFFSET(i) +
3744                            8);
3745                 row3 =
3746                     REG_RD(sc,
3747                            BAR_XSTRORM_INTMEM + XSTORM_ASSERT_LIST_OFFSET(i) +
3748                            12);
3749
3750                 if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) {
3751                         PMD_DRV_LOG(ERR, sc,
3752                                     "XSTORM_ASSERT_INDEX 0x%x = 0x%08x 0x%08x 0x%08x 0x%08x",
3753                                     i, row3, row2, row1, row0);
3754                         rc++;
3755                 } else {
3756                         break;
3757                 }
3758         }
3759
3760         /* TSTORM */
3761         last_idx =
3762             REG_RD8(sc, BAR_TSTRORM_INTMEM + TSTORM_ASSERT_LIST_INDEX_OFFSET);
3763         if (last_idx) {
3764                 PMD_DRV_LOG(ERR, sc, "TSTORM_ASSERT_LIST_INDEX 0x%x", last_idx);
3765         }
3766
3767         /* print the asserts */
3768         for (i = 0; i < STORM_ASSERT_ARRAY_SIZE; i++) {
3769
3770                 row0 =
3771                     REG_RD(sc,
3772                            BAR_TSTRORM_INTMEM + TSTORM_ASSERT_LIST_OFFSET(i));
3773                 row1 =
3774                     REG_RD(sc,
3775                            BAR_TSTRORM_INTMEM + TSTORM_ASSERT_LIST_OFFSET(i) +
3776                            4);
3777                 row2 =
3778                     REG_RD(sc,
3779                            BAR_TSTRORM_INTMEM + TSTORM_ASSERT_LIST_OFFSET(i) +
3780                            8);
3781                 row3 =
3782                     REG_RD(sc,
3783                            BAR_TSTRORM_INTMEM + TSTORM_ASSERT_LIST_OFFSET(i) +
3784                            12);
3785
3786                 if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) {
3787                         PMD_DRV_LOG(ERR, sc,
3788                                     "TSTORM_ASSERT_INDEX 0x%x = 0x%08x 0x%08x 0x%08x 0x%08x",
3789                                     i, row3, row2, row1, row0);
3790                         rc++;
3791                 } else {
3792                         break;
3793                 }
3794         }
3795
3796         /* CSTORM */
3797         last_idx =
3798             REG_RD8(sc, BAR_CSTRORM_INTMEM + CSTORM_ASSERT_LIST_INDEX_OFFSET);
3799         if (last_idx) {
3800                 PMD_DRV_LOG(ERR, sc, "CSTORM_ASSERT_LIST_INDEX 0x%x", last_idx);
3801         }
3802
3803         /* print the asserts */
3804         for (i = 0; i < STORM_ASSERT_ARRAY_SIZE; i++) {
3805
3806                 row0 =
3807                     REG_RD(sc,
3808                            BAR_CSTRORM_INTMEM + CSTORM_ASSERT_LIST_OFFSET(i));
3809                 row1 =
3810                     REG_RD(sc,
3811                            BAR_CSTRORM_INTMEM + CSTORM_ASSERT_LIST_OFFSET(i) +
3812                            4);
3813                 row2 =
3814                     REG_RD(sc,
3815                            BAR_CSTRORM_INTMEM + CSTORM_ASSERT_LIST_OFFSET(i) +
3816                            8);
3817                 row3 =
3818                     REG_RD(sc,
3819                            BAR_CSTRORM_INTMEM + CSTORM_ASSERT_LIST_OFFSET(i) +
3820                            12);
3821
3822                 if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) {
3823                         PMD_DRV_LOG(ERR, sc,
3824                                     "CSTORM_ASSERT_INDEX 0x%x = 0x%08x 0x%08x 0x%08x 0x%08x",
3825                                     i, row3, row2, row1, row0);
3826                         rc++;
3827                 } else {
3828                         break;
3829                 }
3830         }
3831
3832         /* USTORM */
3833         last_idx =
3834             REG_RD8(sc, BAR_USTRORM_INTMEM + USTORM_ASSERT_LIST_INDEX_OFFSET);
3835         if (last_idx) {
3836                 PMD_DRV_LOG(ERR, sc, "USTORM_ASSERT_LIST_INDEX 0x%x", last_idx);
3837         }
3838
3839         /* print the asserts */
3840         for (i = 0; i < STORM_ASSERT_ARRAY_SIZE; i++) {
3841
3842                 row0 =
3843                     REG_RD(sc,
3844                            BAR_USTRORM_INTMEM + USTORM_ASSERT_LIST_OFFSET(i));
3845                 row1 =
3846                     REG_RD(sc,
3847                            BAR_USTRORM_INTMEM + USTORM_ASSERT_LIST_OFFSET(i) +
3848                            4);
3849                 row2 =
3850                     REG_RD(sc,
3851                            BAR_USTRORM_INTMEM + USTORM_ASSERT_LIST_OFFSET(i) +
3852                            8);
3853                 row3 =
3854                     REG_RD(sc,
3855                            BAR_USTRORM_INTMEM + USTORM_ASSERT_LIST_OFFSET(i) +
3856                            12);
3857
3858                 if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) {
3859                         PMD_DRV_LOG(ERR, sc,
3860                                     "USTORM_ASSERT_INDEX 0x%x = 0x%08x 0x%08x 0x%08x 0x%08x",
3861                                     i, row3, row2, row1, row0);
3862                         rc++;
3863                 } else {
3864                         break;
3865                 }
3866         }
3867
3868         return rc;
3869 }
3870
3871 static void bnx2x_attn_int_deasserted3(struct bnx2x_softc *sc, uint32_t attn)
3872 {
3873         int func = SC_FUNC(sc);
3874         uint32_t val;
3875
3876         if (attn & EVEREST_GEN_ATTN_IN_USE_MASK) {
3877
3878                 if (attn & BNX2X_PMF_LINK_ASSERT(sc)) {
3879
3880                         REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_12 + func * 4, 0);
3881                         bnx2x_read_mf_cfg(sc);
3882                         sc->devinfo.mf_info.mf_config[SC_VN(sc)] =
3883                             MFCFG_RD(sc,
3884                                      func_mf_config[SC_ABS_FUNC(sc)].config);
3885                         val =
3886                             SHMEM_RD(sc, func_mb[SC_FW_MB_IDX(sc)].drv_status);
3887
3888                         if (val & DRV_STATUS_DCC_EVENT_MASK)
3889                                 bnx2x_dcc_event(sc,
3890                                               (val &
3891                                                DRV_STATUS_DCC_EVENT_MASK));
3892
3893                         if (val & DRV_STATUS_SET_MF_BW)
3894                                 bnx2x_set_mf_bw(sc);
3895
3896                         if (val & DRV_STATUS_DRV_INFO_REQ)
3897                                 bnx2x_handle_drv_info_req(sc);
3898
3899                         if ((sc->port.pmf == 0) && (val & DRV_STATUS_PMF))
3900                                 bnx2x_pmf_update(sc);
3901
3902                         if (val & DRV_STATUS_EEE_NEGOTIATION_RESULTS)
3903                                 bnx2x_handle_eee_event(sc);
3904
3905                         if (sc->link_vars.periodic_flags &
3906                             ELINK_PERIODIC_FLAGS_LINK_EVENT) {
3907                                 /* sync with link */
3908                                 bnx2x_acquire_phy_lock(sc);
3909                                 sc->link_vars.periodic_flags &=
3910                                     ~ELINK_PERIODIC_FLAGS_LINK_EVENT;
3911                                 bnx2x_release_phy_lock(sc);
3912                                 if (IS_MF(sc)) {
3913                                         bnx2x_link_sync_notify(sc);
3914                                 }
3915                                 bnx2x_link_report(sc);
3916                         }
3917
3918                         /*
3919                          * Always call it here: bnx2x_link_report() will
3920                          * prevent the link indication duplication.
3921                          */
3922                         bnx2x_link_status_update(sc);
3923
3924                 } else if (attn & BNX2X_MC_ASSERT_BITS) {
3925
3926                         PMD_DRV_LOG(ERR, sc, "MC assert!");
3927                         bnx2x_mc_assert(sc);
3928                         REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_10, 0);
3929                         REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_9, 0);
3930                         REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_8, 0);
3931                         REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_7, 0);
3932                         rte_panic("MC assert!");
3933
3934                 } else if (attn & BNX2X_MCP_ASSERT) {
3935
3936                         PMD_DRV_LOG(ERR, sc, "MCP assert!");
3937                         REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_11, 0);
3938
3939                 } else {
3940                         PMD_DRV_LOG(ERR, sc,
3941                                     "Unknown HW assert! (attn 0x%08x)", attn);
3942                 }
3943         }
3944
3945         if (attn & EVEREST_LATCHED_ATTN_IN_USE_MASK) {
3946                 PMD_DRV_LOG(ERR, sc, "LATCHED attention 0x%08x (masked)", attn);
3947                 if (attn & BNX2X_GRC_TIMEOUT) {
3948                         val = REG_RD(sc, MISC_REG_GRC_TIMEOUT_ATTN);
3949                         PMD_DRV_LOG(ERR, sc, "GRC time-out 0x%08x", val);
3950                 }
3951                 if (attn & BNX2X_GRC_RSV) {
3952                         val = REG_RD(sc, MISC_REG_GRC_RSV_ATTN);
3953                         PMD_DRV_LOG(ERR, sc, "GRC reserved 0x%08x", val);
3954                 }
3955                 REG_WR(sc, MISC_REG_AEU_CLR_LATCH_SIGNAL, 0x7ff);
3956         }
3957 }
3958
3959 static void bnx2x_attn_int_deasserted2(struct bnx2x_softc *sc, uint32_t attn)
3960 {
3961         int port = SC_PORT(sc);
3962         int reg_offset;
3963         uint32_t val0, mask0, val1, mask1;
3964         uint32_t val;
3965
3966         if (attn & AEU_INPUTS_ATTN_BITS_CFC_HW_INTERRUPT) {
3967                 val = REG_RD(sc, CFC_REG_CFC_INT_STS_CLR);
3968                 PMD_DRV_LOG(ERR, sc, "CFC hw attention 0x%08x", val);
3969 /* CFC error attention */
3970                 if (val & 0x2) {
3971                         PMD_DRV_LOG(ERR, sc, "FATAL error from CFC");
3972                 }
3973         }
3974
3975         if (attn & AEU_INPUTS_ATTN_BITS_PXP_HW_INTERRUPT) {
3976                 val = REG_RD(sc, PXP_REG_PXP_INT_STS_CLR_0);
3977                 PMD_DRV_LOG(ERR, sc, "PXP hw attention-0 0x%08x", val);
3978 /* RQ_USDMDP_FIFO_OVERFLOW */
3979                 if (val & 0x18000) {
3980                         PMD_DRV_LOG(ERR, sc, "FATAL error from PXP");
3981                 }
3982
3983                 if (!CHIP_IS_E1x(sc)) {
3984                         val = REG_RD(sc, PXP_REG_PXP_INT_STS_CLR_1);
3985                         PMD_DRV_LOG(ERR, sc, "PXP hw attention-1 0x%08x", val);
3986                 }
3987         }
3988 #define PXP2_EOP_ERROR_BIT  PXP2_PXP2_INT_STS_CLR_0_REG_WR_PGLUE_EOP_ERROR
3989 #define AEU_PXP2_HW_INT_BIT AEU_INPUTS_ATTN_BITS_PXPPCICLOCKCLIENT_HW_INTERRUPT
3990
3991         if (attn & AEU_PXP2_HW_INT_BIT) {
3992 /*  CQ47854 workaround do not panic on
3993  *  PXP2_PXP2_INT_STS_0_REG_WR_PGLUE_EOP_ERROR
3994  */
3995                 if (!CHIP_IS_E1x(sc)) {
3996                         mask0 = REG_RD(sc, PXP2_REG_PXP2_INT_MASK_0);
3997                         val1 = REG_RD(sc, PXP2_REG_PXP2_INT_STS_1);
3998                         mask1 = REG_RD(sc, PXP2_REG_PXP2_INT_MASK_1);
3999                         val0 = REG_RD(sc, PXP2_REG_PXP2_INT_STS_0);
4000                         /*
4001                          * If the only PXP2_EOP_ERROR_BIT is set in
4002                          * STS0 and STS1 - clear it
4003                          *
4004                          * probably we lose additional attentions between
4005                          * STS0 and STS_CLR0, in this case user will not
4006                          * be notified about them
4007                          */
4008                         if (val0 & mask0 & PXP2_EOP_ERROR_BIT &&
4009                             !(val1 & mask1))
4010                                 val0 = REG_RD(sc, PXP2_REG_PXP2_INT_STS_CLR_0);
4011
4012                         /* print the register, since no one can restore it */
4013                         PMD_DRV_LOG(ERR, sc,
4014                                     "PXP2_REG_PXP2_INT_STS_CLR_0 0x%08x", val0);
4015
4016                         /*
4017                          * if PXP2_PXP2_INT_STS_0_REG_WR_PGLUE_EOP_ERROR
4018                          * then notify
4019                          */
4020                         if (val0 & PXP2_EOP_ERROR_BIT) {
4021                                 PMD_DRV_LOG(ERR, sc, "PXP2_WR_PGLUE_EOP_ERROR");
4022
4023                                 /*
4024                                  * if only PXP2_PXP2_INT_STS_0_REG_WR_PGLUE_EOP_ERROR is
4025                                  * set then clear attention from PXP2 block without panic
4026                                  */
4027                                 if (((val0 & mask0) == PXP2_EOP_ERROR_BIT) &&
4028                                     ((val1 & mask1) == 0))
4029                                         attn &= ~AEU_PXP2_HW_INT_BIT;
4030                         }
4031                 }
4032         }
4033
4034         if (attn & HW_INTERRUT_ASSERT_SET_2) {
4035                 reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_2 :
4036                               MISC_REG_AEU_ENABLE1_FUNC_0_OUT_2);
4037
4038                 val = REG_RD(sc, reg_offset);
4039                 val &= ~(attn & HW_INTERRUT_ASSERT_SET_2);
4040                 REG_WR(sc, reg_offset, val);
4041
4042                 PMD_DRV_LOG(ERR, sc,
4043                             "FATAL HW block attention set2 0x%x",
4044                             (uint32_t) (attn & HW_INTERRUT_ASSERT_SET_2));
4045                 rte_panic("HW block attention set2");
4046         }
4047 }
4048
4049 static void bnx2x_attn_int_deasserted1(struct bnx2x_softc *sc, uint32_t attn)
4050 {
4051         int port = SC_PORT(sc);
4052         int reg_offset;
4053         uint32_t val;
4054
4055         if (attn & AEU_INPUTS_ATTN_BITS_DOORBELLQ_HW_INTERRUPT) {
4056                 val = REG_RD(sc, DORQ_REG_DORQ_INT_STS_CLR);
4057                 PMD_DRV_LOG(ERR, sc, "DB hw attention 0x%08x", val);
4058 /* DORQ discard attention */
4059                 if (val & 0x2) {
4060                         PMD_DRV_LOG(ERR, sc, "FATAL error from DORQ");
4061                 }
4062         }
4063
4064         if (attn & HW_INTERRUT_ASSERT_SET_1) {
4065                 reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_1 :
4066                               MISC_REG_AEU_ENABLE1_FUNC_0_OUT_1);
4067
4068                 val = REG_RD(sc, reg_offset);
4069                 val &= ~(attn & HW_INTERRUT_ASSERT_SET_1);
4070                 REG_WR(sc, reg_offset, val);
4071
4072                 PMD_DRV_LOG(ERR, sc,
4073                             "FATAL HW block attention set1 0x%08x",
4074                             (uint32_t) (attn & HW_INTERRUT_ASSERT_SET_1));
4075                 rte_panic("HW block attention set1");
4076         }
4077 }
4078
4079 static void bnx2x_attn_int_deasserted0(struct bnx2x_softc *sc, uint32_t attn)
4080 {
4081         int port = SC_PORT(sc);
4082         int reg_offset;
4083         uint32_t val;
4084
4085         reg_offset = (port) ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 :
4086             MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0;
4087
4088         if (attn & AEU_INPUTS_ATTN_BITS_SPIO5) {
4089                 val = REG_RD(sc, reg_offset);
4090                 val &= ~AEU_INPUTS_ATTN_BITS_SPIO5;
4091                 REG_WR(sc, reg_offset, val);
4092
4093                 PMD_DRV_LOG(WARNING, sc, "SPIO5 hw attention");
4094
4095 /* Fan failure attention */
4096                 elink_hw_reset_phy(&sc->link_params);
4097                 bnx2x_fan_failure(sc);
4098         }
4099
4100         if ((attn & sc->link_vars.aeu_int_mask) && sc->port.pmf) {
4101                 bnx2x_acquire_phy_lock(sc);
4102                 elink_handle_module_detect_int(&sc->link_params);
4103                 bnx2x_release_phy_lock(sc);
4104         }
4105
4106         if (attn & HW_INTERRUT_ASSERT_SET_0) {
4107                 val = REG_RD(sc, reg_offset);
4108                 val &= ~(attn & HW_INTERRUT_ASSERT_SET_0);
4109                 REG_WR(sc, reg_offset, val);
4110
4111                 rte_panic("FATAL HW block attention set0 0x%lx",
4112                           (attn & (unsigned long)HW_INTERRUT_ASSERT_SET_0));
4113         }
4114 }
4115
4116 static void bnx2x_attn_int_deasserted(struct bnx2x_softc *sc, uint32_t deasserted)
4117 {
4118         struct attn_route attn;
4119         struct attn_route *group_mask;
4120         int port = SC_PORT(sc);
4121         int index;
4122         uint32_t reg_addr;
4123         uint32_t val;
4124         uint32_t aeu_mask;
4125         uint8_t global = FALSE;
4126
4127         /*
4128          * Need to take HW lock because MCP or other port might also
4129          * try to handle this event.
4130          */
4131         bnx2x_acquire_alr(sc);
4132
4133         if (bnx2x_chk_parity_attn(sc, &global, TRUE)) {
4134                 sc->recovery_state = BNX2X_RECOVERY_INIT;
4135
4136 /* disable HW interrupts */
4137                 bnx2x_int_disable(sc);
4138                 bnx2x_release_alr(sc);
4139                 return;
4140         }
4141
4142         attn.sig[0] = REG_RD(sc, MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 + port * 4);
4143         attn.sig[1] = REG_RD(sc, MISC_REG_AEU_AFTER_INVERT_2_FUNC_0 + port * 4);
4144         attn.sig[2] = REG_RD(sc, MISC_REG_AEU_AFTER_INVERT_3_FUNC_0 + port * 4);
4145         attn.sig[3] = REG_RD(sc, MISC_REG_AEU_AFTER_INVERT_4_FUNC_0 + port * 4);
4146         if (!CHIP_IS_E1x(sc)) {
4147                 attn.sig[4] =
4148                     REG_RD(sc, MISC_REG_AEU_AFTER_INVERT_5_FUNC_0 + port * 4);
4149         } else {
4150                 attn.sig[4] = 0;
4151         }
4152
4153         for (index = 0; index < MAX_DYNAMIC_ATTN_GRPS; index++) {
4154                 if (deasserted & (1 << index)) {
4155                         group_mask = &sc->attn_group[index];
4156
4157                         bnx2x_attn_int_deasserted4(sc,
4158                                                  attn.
4159                                                  sig[4] & group_mask->sig[4]);
4160                         bnx2x_attn_int_deasserted3(sc,
4161                                                  attn.
4162                                                  sig[3] & group_mask->sig[3]);
4163                         bnx2x_attn_int_deasserted1(sc,
4164                                                  attn.
4165                                                  sig[1] & group_mask->sig[1]);
4166                         bnx2x_attn_int_deasserted2(sc,
4167                                                  attn.
4168                                                  sig[2] & group_mask->sig[2]);
4169                         bnx2x_attn_int_deasserted0(sc,
4170                                                  attn.
4171                                                  sig[0] & group_mask->sig[0]);
4172                 }
4173         }
4174
4175         bnx2x_release_alr(sc);
4176
4177         if (sc->devinfo.int_block == INT_BLOCK_HC) {
4178                 reg_addr = (HC_REG_COMMAND_REG + port * 32 +
4179                             COMMAND_REG_ATTN_BITS_CLR);
4180         } else {
4181                 reg_addr = (BAR_IGU_INTMEM + IGU_CMD_ATTN_BIT_CLR_UPPER * 8);
4182         }
4183
4184         val = ~deasserted;
4185         PMD_DRV_LOG(DEBUG, sc,
4186                     "about to mask 0x%08x at %s addr 0x%08x", val,
4187                     (sc->devinfo.int_block == INT_BLOCK_HC) ? "HC" : "IGU",
4188                     reg_addr);
4189         REG_WR(sc, reg_addr, val);
4190
4191         if (~sc->attn_state & deasserted) {
4192                 PMD_DRV_LOG(ERR, sc, "IGU error");
4193         }
4194
4195         reg_addr = port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 :
4196             MISC_REG_AEU_MASK_ATTN_FUNC_0;
4197
4198         bnx2x_acquire_hw_lock(sc, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
4199
4200         aeu_mask = REG_RD(sc, reg_addr);
4201
4202         aeu_mask |= (deasserted & 0x3ff);
4203
4204         REG_WR(sc, reg_addr, aeu_mask);
4205         bnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
4206
4207         sc->attn_state &= ~deasserted;
4208 }
4209
4210 static void bnx2x_attn_int(struct bnx2x_softc *sc)
4211 {
4212         /* read local copy of bits */
4213         uint32_t attn_bits = le32toh(sc->def_sb->atten_status_block.attn_bits);
4214         uint32_t attn_ack =
4215             le32toh(sc->def_sb->atten_status_block.attn_bits_ack);
4216         uint32_t attn_state = sc->attn_state;
4217
4218         /* look for changed bits */
4219         uint32_t asserted = attn_bits & ~attn_ack & ~attn_state;
4220         uint32_t deasserted = ~attn_bits & attn_ack & attn_state;
4221
4222         PMD_DRV_LOG(DEBUG, sc,
4223                     "attn_bits 0x%08x attn_ack 0x%08x asserted 0x%08x deasserted 0x%08x",
4224                     attn_bits, attn_ack, asserted, deasserted);
4225
4226         if (~(attn_bits ^ attn_ack) & (attn_bits ^ attn_state)) {
4227                 PMD_DRV_LOG(ERR, sc, "BAD attention state");
4228         }
4229
4230         /* handle bits that were raised */
4231         if (asserted) {
4232                 bnx2x_attn_int_asserted(sc, asserted);
4233         }
4234
4235         if (deasserted) {
4236                 bnx2x_attn_int_deasserted(sc, deasserted);
4237         }
4238 }
4239
4240 static uint16_t bnx2x_update_dsb_idx(struct bnx2x_softc *sc)
4241 {
4242         struct host_sp_status_block *def_sb = sc->def_sb;
4243         uint16_t rc = 0;
4244
4245         if (!def_sb)
4246                 return 0;
4247
4248         mb();                   /* status block is written to by the chip */
4249
4250         if (sc->def_att_idx != def_sb->atten_status_block.attn_bits_index) {
4251                 sc->def_att_idx = def_sb->atten_status_block.attn_bits_index;
4252                 rc |= BNX2X_DEF_SB_ATT_IDX;
4253         }
4254
4255         if (sc->def_idx != def_sb->sp_sb.running_index) {
4256                 sc->def_idx = def_sb->sp_sb.running_index;
4257                 rc |= BNX2X_DEF_SB_IDX;
4258         }
4259
4260         mb();
4261
4262         return rc;
4263 }
4264
4265 static struct ecore_queue_sp_obj *bnx2x_cid_to_q_obj(struct bnx2x_softc *sc,
4266                                                           uint32_t cid)
4267 {
4268         return &sc->sp_objs[CID_TO_FP(cid, sc)].q_obj;
4269 }
4270
4271 static void bnx2x_handle_mcast_eqe(struct bnx2x_softc *sc)
4272 {
4273         struct ecore_mcast_ramrod_params rparam;
4274         int rc;
4275
4276         memset(&rparam, 0, sizeof(rparam));
4277
4278         rparam.mcast_obj = &sc->mcast_obj;
4279
4280         /* clear pending state for the last command */
4281         sc->mcast_obj.raw.clear_pending(&sc->mcast_obj.raw);
4282
4283         /* if there are pending mcast commands - send them */
4284         if (sc->mcast_obj.check_pending(&sc->mcast_obj)) {
4285                 rc = ecore_config_mcast(sc, &rparam, ECORE_MCAST_CMD_CONT);
4286                 if (rc < 0) {
4287                         PMD_DRV_LOG(INFO, sc,
4288                                     "Failed to send pending mcast commands (%d)",
4289                                     rc);
4290                 }
4291         }
4292 }
4293
4294 static void
4295 bnx2x_handle_classification_eqe(struct bnx2x_softc *sc, union event_ring_elem *elem)
4296 {
4297         unsigned long ramrod_flags = 0;
4298         int rc = 0;
4299         uint32_t cid = elem->message.data.eth_event.echo & BNX2X_SWCID_MASK;
4300         struct ecore_vlan_mac_obj *vlan_mac_obj;
4301
4302         /* always push next commands out, don't wait here */
4303         bnx2x_set_bit(RAMROD_CONT, &ramrod_flags);
4304
4305         switch (le32toh(elem->message.data.eth_event.echo) >> BNX2X_SWCID_SHIFT) {
4306         case ECORE_FILTER_MAC_PENDING:
4307                 PMD_DRV_LOG(DEBUG, sc, "Got SETUP_MAC completions");
4308                 vlan_mac_obj = &sc->sp_objs[cid].mac_obj;
4309                 break;
4310
4311         case ECORE_FILTER_MCAST_PENDING:
4312                 PMD_DRV_LOG(DEBUG, sc, "Got SETUP_MCAST completions");
4313                 bnx2x_handle_mcast_eqe(sc);
4314                 return;
4315
4316         default:
4317                 PMD_DRV_LOG(NOTICE, sc, "Unsupported classification command: %d",
4318                             elem->message.data.eth_event.echo);
4319                 return;
4320         }
4321
4322         rc = vlan_mac_obj->complete(sc, vlan_mac_obj, elem, &ramrod_flags);
4323
4324         if (rc < 0) {
4325                 PMD_DRV_LOG(NOTICE, sc,
4326                             "Failed to schedule new commands (%d)", rc);
4327         } else if (rc > 0) {
4328                 PMD_DRV_LOG(DEBUG, sc, "Scheduled next pending commands...");
4329         }
4330 }
4331
4332 static void bnx2x_handle_rx_mode_eqe(struct bnx2x_softc *sc)
4333 {
4334         bnx2x_clear_bit(ECORE_FILTER_RX_MODE_PENDING, &sc->sp_state);
4335
4336         /* send rx_mode command again if was requested */
4337         if (bnx2x_test_and_clear_bit(ECORE_FILTER_RX_MODE_SCHED, &sc->sp_state)) {
4338                 bnx2x_set_storm_rx_mode(sc);
4339         }
4340 }
4341
4342 static void bnx2x_update_eq_prod(struct bnx2x_softc *sc, uint16_t prod)
4343 {
4344         storm_memset_eq_prod(sc, prod, SC_FUNC(sc));
4345         wmb();                  /* keep prod updates ordered */
4346 }
4347
4348 static void bnx2x_eq_int(struct bnx2x_softc *sc)
4349 {
4350         uint16_t hw_cons, sw_cons, sw_prod;
4351         union event_ring_elem *elem;
4352         uint8_t echo;
4353         uint32_t cid;
4354         uint8_t opcode;
4355         int spqe_cnt = 0;
4356         struct ecore_queue_sp_obj *q_obj;
4357         struct ecore_func_sp_obj *f_obj = &sc->func_obj;
4358         struct ecore_raw_obj *rss_raw = &sc->rss_conf_obj.raw;
4359
4360         hw_cons = le16toh(*sc->eq_cons_sb);
4361
4362         /*
4363          * The hw_cons range is 1-255, 257 - the sw_cons range is 0-254, 256.
4364          * when we get to the next-page we need to adjust so the loop
4365          * condition below will be met. The next element is the size of a
4366          * regular element and hence incrementing by 1
4367          */
4368         if ((hw_cons & EQ_DESC_MAX_PAGE) == EQ_DESC_MAX_PAGE) {
4369                 hw_cons++;
4370         }
4371
4372         /*
4373          * This function may never run in parallel with itself for a
4374          * specific sc and no need for a read memory barrier here.
4375          */
4376         sw_cons = sc->eq_cons;
4377         sw_prod = sc->eq_prod;
4378
4379         for (;
4380              sw_cons != hw_cons;
4381              sw_prod = NEXT_EQ_IDX(sw_prod), sw_cons = NEXT_EQ_IDX(sw_cons)) {
4382
4383                 elem = &sc->eq[EQ_DESC(sw_cons)];
4384
4385 /* elem CID originates from FW, actually LE */
4386                 cid = SW_CID(elem->message.data.cfc_del_event.cid);
4387                 opcode = elem->message.opcode;
4388
4389 /* handle eq element */
4390                 switch (opcode) {
4391                 case EVENT_RING_OPCODE_STAT_QUERY:
4392                         PMD_DEBUG_PERIODIC_LOG(DEBUG, sc, "got statistics completion event %d",
4393                                     sc->stats_comp++);
4394                         /* nothing to do with stats comp */
4395                         goto next_spqe;
4396
4397                 case EVENT_RING_OPCODE_CFC_DEL:
4398                         /* handle according to cid range */
4399                         /* we may want to verify here that the sc state is HALTING */
4400                         PMD_DRV_LOG(DEBUG, sc, "got delete ramrod for MULTI[%d]",
4401                                     cid);
4402                         q_obj = bnx2x_cid_to_q_obj(sc, cid);
4403                         if (q_obj->complete_cmd(sc, q_obj, ECORE_Q_CMD_CFC_DEL)) {
4404                                 break;
4405                         }
4406                         goto next_spqe;
4407
4408                 case EVENT_RING_OPCODE_STOP_TRAFFIC:
4409                         PMD_DRV_LOG(DEBUG, sc, "got STOP TRAFFIC");
4410                         if (f_obj->complete_cmd(sc, f_obj, ECORE_F_CMD_TX_STOP)) {
4411                                 break;
4412                         }
4413                         goto next_spqe;
4414
4415                 case EVENT_RING_OPCODE_START_TRAFFIC:
4416                         PMD_DRV_LOG(DEBUG, sc, "got START TRAFFIC");
4417                         if (f_obj->complete_cmd
4418                             (sc, f_obj, ECORE_F_CMD_TX_START)) {
4419                                 break;
4420                         }
4421                         goto next_spqe;
4422
4423                 case EVENT_RING_OPCODE_FUNCTION_UPDATE:
4424                         echo = elem->message.data.function_update_event.echo;
4425                         if (echo == SWITCH_UPDATE) {
4426                                 PMD_DRV_LOG(DEBUG, sc,
4427                                             "got FUNC_SWITCH_UPDATE ramrod");
4428                                 if (f_obj->complete_cmd(sc, f_obj,
4429                                                         ECORE_F_CMD_SWITCH_UPDATE))
4430                                 {
4431                                         break;
4432                                 }
4433                         } else {
4434                                 PMD_DRV_LOG(DEBUG, sc,
4435                                             "AFEX: ramrod completed FUNCTION_UPDATE");
4436                                 f_obj->complete_cmd(sc, f_obj,
4437                                                     ECORE_F_CMD_AFEX_UPDATE);
4438                         }
4439                         goto next_spqe;
4440
4441                 case EVENT_RING_OPCODE_FORWARD_SETUP:
4442                         q_obj = &bnx2x_fwd_sp_obj(sc, q_obj);
4443                         if (q_obj->complete_cmd(sc, q_obj,
4444                                                 ECORE_Q_CMD_SETUP_TX_ONLY)) {
4445                                 break;
4446                         }
4447                         goto next_spqe;
4448
4449                 case EVENT_RING_OPCODE_FUNCTION_START:
4450                         PMD_DRV_LOG(DEBUG, sc, "got FUNC_START ramrod");
4451                         if (f_obj->complete_cmd(sc, f_obj, ECORE_F_CMD_START)) {
4452                                 break;
4453                         }
4454                         goto next_spqe;
4455
4456                 case EVENT_RING_OPCODE_FUNCTION_STOP:
4457                         PMD_DRV_LOG(DEBUG, sc, "got FUNC_STOP ramrod");
4458                         if (f_obj->complete_cmd(sc, f_obj, ECORE_F_CMD_STOP)) {
4459                                 break;
4460                         }
4461                         goto next_spqe;
4462                 }
4463
4464                 switch (opcode | sc->state) {
4465                 case (EVENT_RING_OPCODE_RSS_UPDATE_RULES | BNX2X_STATE_OPEN):
4466                 case (EVENT_RING_OPCODE_RSS_UPDATE_RULES | BNX2X_STATE_OPENING_WAITING_PORT):
4467                         cid =
4468                             elem->message.data.eth_event.echo & BNX2X_SWCID_MASK;
4469                         PMD_DRV_LOG(DEBUG, sc, "got RSS_UPDATE ramrod. CID %d",
4470                                     cid);
4471                         rss_raw->clear_pending(rss_raw);
4472                         break;
4473
4474                 case (EVENT_RING_OPCODE_SET_MAC | BNX2X_STATE_OPEN):
4475                 case (EVENT_RING_OPCODE_SET_MAC | BNX2X_STATE_DIAG):
4476                 case (EVENT_RING_OPCODE_SET_MAC | BNX2X_STATE_CLOSING_WAITING_HALT):
4477                 case (EVENT_RING_OPCODE_CLASSIFICATION_RULES | BNX2X_STATE_OPEN):
4478                 case (EVENT_RING_OPCODE_CLASSIFICATION_RULES | BNX2X_STATE_DIAG):
4479                 case (EVENT_RING_OPCODE_CLASSIFICATION_RULES | BNX2X_STATE_CLOSING_WAITING_HALT):
4480                         PMD_DRV_LOG(DEBUG, sc,
4481                                     "got (un)set mac ramrod");
4482                         bnx2x_handle_classification_eqe(sc, elem);
4483                         break;
4484
4485                 case (EVENT_RING_OPCODE_MULTICAST_RULES | BNX2X_STATE_OPEN):
4486                 case (EVENT_RING_OPCODE_MULTICAST_RULES | BNX2X_STATE_DIAG):
4487                 case (EVENT_RING_OPCODE_MULTICAST_RULES | BNX2X_STATE_CLOSING_WAITING_HALT):
4488                         PMD_DRV_LOG(DEBUG, sc,
4489                                     "got mcast ramrod");
4490                         bnx2x_handle_mcast_eqe(sc);
4491                         break;
4492
4493                 case (EVENT_RING_OPCODE_FILTERS_RULES | BNX2X_STATE_OPEN):
4494                 case (EVENT_RING_OPCODE_FILTERS_RULES | BNX2X_STATE_DIAG):
4495                 case (EVENT_RING_OPCODE_FILTERS_RULES | BNX2X_STATE_CLOSING_WAITING_HALT):
4496                         PMD_DRV_LOG(DEBUG, sc,
4497                                     "got rx_mode ramrod");
4498                         bnx2x_handle_rx_mode_eqe(sc);
4499                         break;
4500
4501                 default:
4502                         /* unknown event log error and continue */
4503                         PMD_DRV_LOG(INFO, sc, "Unknown EQ event %d, sc->state 0x%x",
4504                                     elem->message.opcode, sc->state);
4505                 }
4506
4507 next_spqe:
4508                 spqe_cnt++;
4509         }                       /* for */
4510
4511         mb();
4512         atomic_add_acq_long(&sc->eq_spq_left, spqe_cnt);
4513
4514         sc->eq_cons = sw_cons;
4515         sc->eq_prod = sw_prod;
4516
4517         /* make sure that above mem writes were issued towards the memory */
4518         wmb();
4519
4520         /* update producer */
4521         bnx2x_update_eq_prod(sc, sc->eq_prod);
4522 }
4523
4524 static int bnx2x_handle_sp_tq(struct bnx2x_softc *sc)
4525 {
4526         uint16_t status;
4527         int rc = 0;
4528
4529         PMD_DRV_LOG(DEBUG, sc, "---> SP TASK <---");
4530
4531         /* what work needs to be performed? */
4532         status = bnx2x_update_dsb_idx(sc);
4533
4534         PMD_DRV_LOG(DEBUG, sc, "dsb status 0x%04x", status);
4535
4536         /* HW attentions */
4537         if (status & BNX2X_DEF_SB_ATT_IDX) {
4538                 PMD_DRV_LOG(DEBUG, sc, "---> ATTN INTR <---");
4539                 bnx2x_attn_int(sc);
4540                 status &= ~BNX2X_DEF_SB_ATT_IDX;
4541                 rc = 1;
4542         }
4543
4544         /* SP events: STAT_QUERY and others */
4545         if (status & BNX2X_DEF_SB_IDX) {
4546 /* handle EQ completions */
4547                 PMD_DRV_LOG(DEBUG, sc, "---> EQ INTR <---");
4548                 bnx2x_eq_int(sc);
4549                 bnx2x_ack_sb(sc, sc->igu_dsb_id, USTORM_ID,
4550                            le16toh(sc->def_idx), IGU_INT_NOP, 1);
4551                 status &= ~BNX2X_DEF_SB_IDX;
4552         }
4553
4554         /* if status is non zero then something went wrong */
4555         if (unlikely(status)) {
4556                 PMD_DRV_LOG(INFO, sc,
4557                             "Got an unknown SP interrupt! (0x%04x)", status);
4558         }
4559
4560         /* ack status block only if something was actually handled */
4561         bnx2x_ack_sb(sc, sc->igu_dsb_id, ATTENTION_ID,
4562                    le16toh(sc->def_att_idx), IGU_INT_ENABLE, 1);
4563
4564         return rc;
4565 }
4566
4567 static void bnx2x_handle_fp_tq(struct bnx2x_fastpath *fp)
4568 {
4569         struct bnx2x_softc *sc = fp->sc;
4570         uint8_t more_rx = FALSE;
4571
4572         /* Make sure FP is initialized */
4573         if (!fp->sb_running_index)
4574                 return;
4575
4576         PMD_DEBUG_PERIODIC_LOG(DEBUG, sc,
4577                                "---> FP TASK QUEUE (%d) <--", fp->index);
4578
4579         /* update the fastpath index */
4580         bnx2x_update_fp_sb_idx(fp);
4581
4582         if (rte_atomic32_read(&sc->scan_fp) == 1) {
4583                 if (bnx2x_has_rx_work(fp)) {
4584                         more_rx = bnx2x_rxeof(sc, fp);
4585                 }
4586
4587                 if (more_rx) {
4588                         /* still more work to do */
4589                         bnx2x_handle_fp_tq(fp);
4590                         return;
4591                 }
4592                 /* We have completed slow path completion, clear the flag */
4593                 rte_atomic32_set(&sc->scan_fp, 0);
4594         }
4595
4596         bnx2x_ack_sb(sc, fp->igu_sb_id, USTORM_ID,
4597                    le16toh(fp->fp_hc_idx), IGU_INT_ENABLE, 1);
4598 }
4599
4600 /*
4601  * Legacy interrupt entry point.
4602  *
4603  * Verifies that the controller generated the interrupt and
4604  * then calls a separate routine to handle the various
4605  * interrupt causes: link, RX, and TX.
4606  */
4607 int bnx2x_intr_legacy(struct bnx2x_softc *sc)
4608 {
4609         struct bnx2x_fastpath *fp;
4610         uint32_t status, mask;
4611         int i, rc = 0;
4612
4613         /*
4614          * 0 for ustorm, 1 for cstorm
4615          * the bits returned from ack_int() are 0-15
4616          * bit 0 = attention status block
4617          * bit 1 = fast path status block
4618          * a mask of 0x2 or more = tx/rx event
4619          * a mask of 1 = slow path event
4620          */
4621
4622         status = bnx2x_ack_int(sc);
4623
4624         /* the interrupt is not for us */
4625         if (unlikely(status == 0)) {
4626                 return 0;
4627         }
4628
4629         PMD_DEBUG_PERIODIC_LOG(DEBUG, sc, "Interrupt status 0x%04x", status);
4630         //bnx2x_dump_status_block(sc);
4631
4632         FOR_EACH_ETH_QUEUE(sc, i) {
4633                 fp = &sc->fp[i];
4634                 mask = (0x2 << (fp->index + CNIC_SUPPORT(sc)));
4635                 if (status & mask) {
4636                 /* acknowledge and disable further fastpath interrupts */
4637                         bnx2x_ack_sb(sc, fp->igu_sb_id, USTORM_ID,
4638                                      0, IGU_INT_DISABLE, 0);
4639                         bnx2x_handle_fp_tq(fp);
4640                         status &= ~mask;
4641                 }
4642         }
4643
4644         if (unlikely(status & 0x1)) {
4645                 /* acknowledge and disable further slowpath interrupts */
4646                 bnx2x_ack_sb(sc, sc->igu_dsb_id, USTORM_ID,
4647                              0, IGU_INT_DISABLE, 0);
4648                 rc = bnx2x_handle_sp_tq(sc);
4649                 status &= ~0x1;
4650         }
4651
4652         if (unlikely(status)) {
4653                 PMD_DRV_LOG(WARNING, sc,
4654                             "Unexpected fastpath status (0x%08x)!", status);
4655         }
4656
4657         return rc;
4658 }
4659
4660 static int bnx2x_init_hw_common_chip(struct bnx2x_softc *sc);
4661 static int bnx2x_init_hw_common(struct bnx2x_softc *sc);
4662 static int bnx2x_init_hw_port(struct bnx2x_softc *sc);
4663 static int bnx2x_init_hw_func(struct bnx2x_softc *sc);
4664 static void bnx2x_reset_common(struct bnx2x_softc *sc);
4665 static void bnx2x_reset_port(struct bnx2x_softc *sc);
4666 static void bnx2x_reset_func(struct bnx2x_softc *sc);
4667 static int bnx2x_init_firmware(struct bnx2x_softc *sc);
4668 static void bnx2x_release_firmware(struct bnx2x_softc *sc);
4669
4670 static struct
4671 ecore_func_sp_drv_ops bnx2x_func_sp_drv = {
4672         .init_hw_cmn_chip = bnx2x_init_hw_common_chip,
4673         .init_hw_cmn = bnx2x_init_hw_common,
4674         .init_hw_port = bnx2x_init_hw_port,
4675         .init_hw_func = bnx2x_init_hw_func,
4676
4677         .reset_hw_cmn = bnx2x_reset_common,
4678         .reset_hw_port = bnx2x_reset_port,
4679         .reset_hw_func = bnx2x_reset_func,
4680
4681         .init_fw = bnx2x_init_firmware,
4682         .release_fw = bnx2x_release_firmware,
4683 };
4684
4685 static void bnx2x_init_func_obj(struct bnx2x_softc *sc)
4686 {
4687         sc->dmae_ready = 0;
4688
4689         PMD_INIT_FUNC_TRACE(sc);
4690
4691         ecore_init_func_obj(sc,
4692                             &sc->func_obj,
4693                             BNX2X_SP(sc, func_rdata),
4694                             (rte_iova_t)BNX2X_SP_MAPPING(sc, func_rdata),
4695                             BNX2X_SP(sc, func_afex_rdata),
4696                             (rte_iova_t)BNX2X_SP_MAPPING(sc, func_afex_rdata),
4697                             &bnx2x_func_sp_drv);
4698 }
4699
4700 static int bnx2x_init_hw(struct bnx2x_softc *sc, uint32_t load_code)
4701 {
4702         struct ecore_func_state_params func_params = { NULL };
4703         int rc;
4704
4705         PMD_INIT_FUNC_TRACE(sc);
4706
4707         /* prepare the parameters for function state transitions */
4708         bnx2x_set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags);
4709
4710         func_params.f_obj = &sc->func_obj;
4711         func_params.cmd = ECORE_F_CMD_HW_INIT;
4712
4713         func_params.params.hw_init.load_phase = load_code;
4714
4715         /*
4716          * Via a plethora of function pointers, we will eventually reach
4717          * bnx2x_init_hw_common(), bnx2x_init_hw_port(), or bnx2x_init_hw_func().
4718          */
4719         rc = ecore_func_state_change(sc, &func_params);
4720
4721         return rc;
4722 }
4723
4724 static void
4725 bnx2x_fill(struct bnx2x_softc *sc, uint32_t addr, int fill, uint32_t len)
4726 {
4727         uint32_t i;
4728
4729         if (!(len % 4) && !(addr % 4)) {
4730                 for (i = 0; i < len; i += 4) {
4731                         REG_WR(sc, (addr + i), fill);
4732                 }
4733         } else {
4734                 for (i = 0; i < len; i++) {
4735                         REG_WR8(sc, (addr + i), fill);
4736                 }
4737         }
4738 }
4739
4740 /* writes FP SP data to FW - data_size in dwords */
4741 static void
4742 bnx2x_wr_fp_sb_data(struct bnx2x_softc *sc, int fw_sb_id, uint32_t * sb_data_p,
4743                   uint32_t data_size)
4744 {
4745         uint32_t index;
4746
4747         for (index = 0; index < data_size; index++) {
4748                 REG_WR(sc,
4749                        (BAR_CSTRORM_INTMEM +
4750                         CSTORM_STATUS_BLOCK_DATA_OFFSET(fw_sb_id) +
4751                         (sizeof(uint32_t) * index)), *(sb_data_p + index));
4752         }
4753 }
4754
4755 static void bnx2x_zero_fp_sb(struct bnx2x_softc *sc, int fw_sb_id)
4756 {
4757         struct hc_status_block_data_e2 sb_data_e2;
4758         struct hc_status_block_data_e1x sb_data_e1x;
4759         uint32_t *sb_data_p;
4760         uint32_t data_size = 0;
4761
4762         if (!CHIP_IS_E1x(sc)) {
4763                 memset(&sb_data_e2, 0, sizeof(struct hc_status_block_data_e2));
4764                 sb_data_e2.common.state = SB_DISABLED;
4765                 sb_data_e2.common.p_func.vf_valid = FALSE;
4766                 sb_data_p = (uint32_t *) & sb_data_e2;
4767                 data_size = (sizeof(struct hc_status_block_data_e2) /
4768                              sizeof(uint32_t));
4769         } else {
4770                 memset(&sb_data_e1x, 0,
4771                        sizeof(struct hc_status_block_data_e1x));
4772                 sb_data_e1x.common.state = SB_DISABLED;
4773                 sb_data_e1x.common.p_func.vf_valid = FALSE;
4774                 sb_data_p = (uint32_t *) & sb_data_e1x;
4775                 data_size = (sizeof(struct hc_status_block_data_e1x) /
4776                              sizeof(uint32_t));
4777         }
4778
4779         bnx2x_wr_fp_sb_data(sc, fw_sb_id, sb_data_p, data_size);
4780
4781         bnx2x_fill(sc,
4782                  (BAR_CSTRORM_INTMEM + CSTORM_STATUS_BLOCK_OFFSET(fw_sb_id)), 0,
4783                  CSTORM_STATUS_BLOCK_SIZE);
4784         bnx2x_fill(sc, (BAR_CSTRORM_INTMEM + CSTORM_SYNC_BLOCK_OFFSET(fw_sb_id)),
4785                  0, CSTORM_SYNC_BLOCK_SIZE);
4786 }
4787
4788 static void
4789 bnx2x_wr_sp_sb_data(struct bnx2x_softc *sc,
4790                   struct hc_sp_status_block_data *sp_sb_data)
4791 {
4792         uint32_t i;
4793
4794         for (i = 0;
4795              i < (sizeof(struct hc_sp_status_block_data) / sizeof(uint32_t));
4796              i++) {
4797                 REG_WR(sc,
4798                        (BAR_CSTRORM_INTMEM +
4799                         CSTORM_SP_STATUS_BLOCK_DATA_OFFSET(SC_FUNC(sc)) +
4800                         (i * sizeof(uint32_t))),
4801                        *((uint32_t *) sp_sb_data + i));
4802         }
4803 }
4804
4805 static void bnx2x_zero_sp_sb(struct bnx2x_softc *sc)
4806 {
4807         struct hc_sp_status_block_data sp_sb_data;
4808
4809         memset(&sp_sb_data, 0, sizeof(struct hc_sp_status_block_data));
4810
4811         sp_sb_data.state = SB_DISABLED;
4812         sp_sb_data.p_func.vf_valid = FALSE;
4813
4814         bnx2x_wr_sp_sb_data(sc, &sp_sb_data);
4815
4816         bnx2x_fill(sc,
4817                  (BAR_CSTRORM_INTMEM +
4818                   CSTORM_SP_STATUS_BLOCK_OFFSET(SC_FUNC(sc))),
4819                  0, CSTORM_SP_STATUS_BLOCK_SIZE);
4820         bnx2x_fill(sc,
4821                  (BAR_CSTRORM_INTMEM +
4822                   CSTORM_SP_SYNC_BLOCK_OFFSET(SC_FUNC(sc))),
4823                  0, CSTORM_SP_SYNC_BLOCK_SIZE);
4824 }
4825
4826 static void
4827 bnx2x_setup_ndsb_state_machine(struct hc_status_block_sm *hc_sm, int igu_sb_id,
4828                              int igu_seg_id)
4829 {
4830         hc_sm->igu_sb_id = igu_sb_id;
4831         hc_sm->igu_seg_id = igu_seg_id;
4832         hc_sm->timer_value = 0xFF;
4833         hc_sm->time_to_expire = 0xFFFFFFFF;
4834 }
4835
4836 static void bnx2x_map_sb_state_machines(struct hc_index_data *index_data)
4837 {
4838         /* zero out state machine indices */
4839
4840         /* rx indices */
4841         index_data[HC_INDEX_ETH_RX_CQ_CONS].flags &= ~HC_INDEX_DATA_SM_ID;
4842
4843         /* tx indices */
4844         index_data[HC_INDEX_OOO_TX_CQ_CONS].flags &= ~HC_INDEX_DATA_SM_ID;
4845         index_data[HC_INDEX_ETH_TX_CQ_CONS_COS0].flags &= ~HC_INDEX_DATA_SM_ID;
4846         index_data[HC_INDEX_ETH_TX_CQ_CONS_COS1].flags &= ~HC_INDEX_DATA_SM_ID;
4847         index_data[HC_INDEX_ETH_TX_CQ_CONS_COS2].flags &= ~HC_INDEX_DATA_SM_ID;
4848
4849         /* map indices */
4850
4851         /* rx indices */
4852         index_data[HC_INDEX_ETH_RX_CQ_CONS].flags |=
4853             (SM_RX_ID << HC_INDEX_DATA_SM_ID_SHIFT);
4854
4855         /* tx indices */
4856         index_data[HC_INDEX_OOO_TX_CQ_CONS].flags |=
4857             (SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT);
4858         index_data[HC_INDEX_ETH_TX_CQ_CONS_COS0].flags |=
4859             (SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT);
4860         index_data[HC_INDEX_ETH_TX_CQ_CONS_COS1].flags |=
4861             (SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT);
4862         index_data[HC_INDEX_ETH_TX_CQ_CONS_COS2].flags |=
4863             (SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT);
4864 }
4865
4866 static void
4867 bnx2x_init_sb(struct bnx2x_softc *sc, rte_iova_t busaddr, int vfid,
4868             uint8_t vf_valid, int fw_sb_id, int igu_sb_id)
4869 {
4870         struct hc_status_block_data_e2 sb_data_e2;
4871         struct hc_status_block_data_e1x sb_data_e1x;
4872         struct hc_status_block_sm *hc_sm_p;
4873         uint32_t *sb_data_p;
4874         int igu_seg_id;
4875         int data_size;
4876
4877         if (CHIP_INT_MODE_IS_BC(sc)) {
4878                 igu_seg_id = HC_SEG_ACCESS_NORM;
4879         } else {
4880                 igu_seg_id = IGU_SEG_ACCESS_NORM;
4881         }
4882
4883         bnx2x_zero_fp_sb(sc, fw_sb_id);
4884
4885         if (!CHIP_IS_E1x(sc)) {
4886                 memset(&sb_data_e2, 0, sizeof(struct hc_status_block_data_e2));
4887                 sb_data_e2.common.state = SB_ENABLED;
4888                 sb_data_e2.common.p_func.pf_id = SC_FUNC(sc);
4889                 sb_data_e2.common.p_func.vf_id = vfid;
4890                 sb_data_e2.common.p_func.vf_valid = vf_valid;
4891                 sb_data_e2.common.p_func.vnic_id = SC_VN(sc);
4892                 sb_data_e2.common.same_igu_sb_1b = TRUE;
4893                 sb_data_e2.common.host_sb_addr.hi = U64_HI(busaddr);
4894                 sb_data_e2.common.host_sb_addr.lo = U64_LO(busaddr);
4895                 hc_sm_p = sb_data_e2.common.state_machine;
4896                 sb_data_p = (uint32_t *) & sb_data_e2;
4897                 data_size = (sizeof(struct hc_status_block_data_e2) /
4898                              sizeof(uint32_t));
4899                 bnx2x_map_sb_state_machines(sb_data_e2.index_data);
4900         } else {
4901                 memset(&sb_data_e1x, 0,
4902                        sizeof(struct hc_status_block_data_e1x));
4903                 sb_data_e1x.common.state = SB_ENABLED;
4904                 sb_data_e1x.common.p_func.pf_id = SC_FUNC(sc);
4905                 sb_data_e1x.common.p_func.vf_id = 0xff;
4906                 sb_data_e1x.common.p_func.vf_valid = FALSE;
4907                 sb_data_e1x.common.p_func.vnic_id = SC_VN(sc);
4908                 sb_data_e1x.common.same_igu_sb_1b = TRUE;
4909                 sb_data_e1x.common.host_sb_addr.hi = U64_HI(busaddr);
4910                 sb_data_e1x.common.host_sb_addr.lo = U64_LO(busaddr);
4911                 hc_sm_p = sb_data_e1x.common.state_machine;
4912                 sb_data_p = (uint32_t *) & sb_data_e1x;
4913                 data_size = (sizeof(struct hc_status_block_data_e1x) /
4914                              sizeof(uint32_t));
4915                 bnx2x_map_sb_state_machines(sb_data_e1x.index_data);
4916         }
4917
4918         bnx2x_setup_ndsb_state_machine(&hc_sm_p[SM_RX_ID], igu_sb_id, igu_seg_id);
4919         bnx2x_setup_ndsb_state_machine(&hc_sm_p[SM_TX_ID], igu_sb_id, igu_seg_id);
4920
4921         /* write indices to HW - PCI guarantees endianity of regpairs */
4922         bnx2x_wr_fp_sb_data(sc, fw_sb_id, sb_data_p, data_size);
4923 }
4924
4925 static uint8_t bnx2x_fp_qzone_id(struct bnx2x_fastpath *fp)
4926 {
4927         if (CHIP_IS_E1x(fp->sc)) {
4928                 return fp->cl_id + SC_PORT(fp->sc) * ETH_MAX_RX_CLIENTS_E1H;
4929         } else {
4930                 return fp->cl_id;
4931         }
4932 }
4933
4934 static uint32_t
4935 bnx2x_rx_ustorm_prods_offset(struct bnx2x_softc *sc, struct bnx2x_fastpath *fp)
4936 {
4937         uint32_t offset = BAR_USTRORM_INTMEM;
4938
4939         if (IS_VF(sc)) {
4940                 return PXP_VF_ADDR_USDM_QUEUES_START +
4941                         (sc->acquire_resp.resc.hw_qid[fp->index] *
4942                          sizeof(struct ustorm_queue_zone_data));
4943         } else if (!CHIP_IS_E1x(sc)) {
4944                 offset += USTORM_RX_PRODS_E2_OFFSET(fp->cl_qzone_id);
4945         } else {
4946                 offset += USTORM_RX_PRODS_E1X_OFFSET(SC_PORT(sc), fp->cl_id);
4947         }
4948
4949         return offset;
4950 }
4951
4952 static void bnx2x_init_eth_fp(struct bnx2x_softc *sc, int idx)
4953 {
4954         struct bnx2x_fastpath *fp = &sc->fp[idx];
4955         uint32_t cids[ECORE_MULTI_TX_COS] = { 0 };
4956         unsigned long q_type = 0;
4957         int cos;
4958
4959         fp->sc = sc;
4960         fp->index = idx;
4961
4962         fp->igu_sb_id = (sc->igu_base_sb + idx + CNIC_SUPPORT(sc));
4963         fp->fw_sb_id = (sc->base_fw_ndsb + idx + CNIC_SUPPORT(sc));
4964
4965         if (CHIP_IS_E1x(sc))
4966                 fp->cl_id = SC_L_ID(sc) + idx;
4967         else
4968 /* want client ID same as IGU SB ID for non-E1 */
4969                 fp->cl_id = fp->igu_sb_id;
4970         fp->cl_qzone_id = bnx2x_fp_qzone_id(fp);
4971
4972         /* setup sb indices */
4973         if (!CHIP_IS_E1x(sc)) {
4974                 fp->sb_index_values = fp->status_block.e2_sb->sb.index_values;
4975                 fp->sb_running_index = fp->status_block.e2_sb->sb.running_index;
4976         } else {
4977                 fp->sb_index_values = fp->status_block.e1x_sb->sb.index_values;
4978                 fp->sb_running_index =
4979                     fp->status_block.e1x_sb->sb.running_index;
4980         }
4981
4982         /* init shortcut */
4983         fp->ustorm_rx_prods_offset = bnx2x_rx_ustorm_prods_offset(sc, fp);
4984
4985         fp->rx_cq_cons_sb = &fp->sb_index_values[HC_INDEX_ETH_RX_CQ_CONS];
4986
4987         for (cos = 0; cos < sc->max_cos; cos++) {
4988                 cids[cos] = idx;
4989         }
4990         fp->tx_cons_sb = &fp->sb_index_values[HC_INDEX_ETH_TX_CQ_CONS_COS0];
4991
4992         /* nothing more for a VF to do */
4993         if (IS_VF(sc)) {
4994                 return;
4995         }
4996
4997         bnx2x_init_sb(sc, fp->sb_dma.paddr, BNX2X_VF_ID_INVALID, FALSE,
4998                     fp->fw_sb_id, fp->igu_sb_id);
4999
5000         bnx2x_update_fp_sb_idx(fp);
5001
5002         /* Configure Queue State object */
5003         bnx2x_set_bit(ECORE_Q_TYPE_HAS_RX, &q_type);
5004         bnx2x_set_bit(ECORE_Q_TYPE_HAS_TX, &q_type);
5005
5006         ecore_init_queue_obj(sc,
5007                              &sc->sp_objs[idx].q_obj,
5008                              fp->cl_id,
5009                              cids,
5010                              sc->max_cos,
5011                              SC_FUNC(sc),
5012                              BNX2X_SP(sc, q_rdata),
5013                              (rte_iova_t)BNX2X_SP_MAPPING(sc, q_rdata),
5014                              q_type);
5015
5016         /* configure classification DBs */
5017         ecore_init_mac_obj(sc,
5018                            &sc->sp_objs[idx].mac_obj,
5019                            fp->cl_id,
5020                            idx,
5021                            SC_FUNC(sc),
5022                            BNX2X_SP(sc, mac_rdata),
5023                            (rte_iova_t)BNX2X_SP_MAPPING(sc, mac_rdata),
5024                            ECORE_FILTER_MAC_PENDING, &sc->sp_state,
5025                            ECORE_OBJ_TYPE_RX_TX, &sc->macs_pool);
5026 }
5027
5028 static void
5029 bnx2x_update_rx_prod(struct bnx2x_softc *sc, struct bnx2x_fastpath *fp,
5030                    uint16_t rx_bd_prod, uint16_t rx_cq_prod)
5031 {
5032         struct ustorm_eth_rx_producers rx_prods;
5033         uint32_t i;
5034
5035         memset(&rx_prods, 0, sizeof(rx_prods));
5036
5037         /* update producers */
5038         rx_prods.bd_prod = rx_bd_prod;
5039         rx_prods.cqe_prod = rx_cq_prod;
5040
5041         /*
5042          * Make sure that the BD and SGE data is updated before updating the
5043          * producers since FW might read the BD/SGE right after the producer
5044          * is updated.
5045          * This is only applicable for weak-ordered memory model archs such
5046          * as IA-64. The following barrier is also mandatory since FW will
5047          * assumes BDs must have buffers.
5048          */
5049         wmb();
5050
5051         for (i = 0; i < (sizeof(rx_prods) / 4); i++) {
5052                 REG_WR(sc, (fp->ustorm_rx_prods_offset + (i * 4)),
5053                        ((uint32_t *)&rx_prods)[i]);
5054         }
5055
5056         wmb();                  /* keep prod updates ordered */
5057 }
5058
5059 static void bnx2x_init_rx_rings(struct bnx2x_softc *sc)
5060 {
5061         struct bnx2x_fastpath *fp;
5062         int i;
5063         struct bnx2x_rx_queue *rxq;
5064
5065         for (i = 0; i < sc->num_queues; i++) {
5066                 fp = &sc->fp[i];
5067                 rxq = sc->rx_queues[fp->index];
5068                 if (!rxq) {
5069                         PMD_RX_LOG(ERR, "RX queue is NULL");
5070                         return;
5071                 }
5072
5073                 rxq->rx_bd_head = 0;
5074                 rxq->rx_bd_tail = rxq->nb_rx_desc;
5075                 rxq->rx_cq_head = 0;
5076                 rxq->rx_cq_tail = TOTAL_RCQ_ENTRIES(rxq);
5077                 *fp->rx_cq_cons_sb = 0;
5078
5079                 /*
5080                  * Activate the BD ring...
5081                  * Warning, this will generate an interrupt (to the TSTORM)
5082                  * so this can only be done after the chip is initialized
5083                  */
5084                 bnx2x_update_rx_prod(sc, fp, rxq->rx_bd_tail, rxq->rx_cq_tail);
5085
5086                 if (i != 0) {
5087                         continue;
5088                 }
5089         }
5090 }
5091
5092 static void bnx2x_init_tx_ring_one(struct bnx2x_fastpath *fp)
5093 {
5094         struct bnx2x_tx_queue *txq = fp->sc->tx_queues[fp->index];
5095
5096         fp->tx_db.data.header.header = 1 << DOORBELL_HDR_DB_TYPE_SHIFT;
5097         fp->tx_db.data.zero_fill1 = 0;
5098         fp->tx_db.data.prod = 0;
5099
5100         if (!txq) {
5101                 PMD_TX_LOG(ERR, "ERROR: TX queue is NULL");
5102                 return;
5103         }
5104
5105         txq->tx_pkt_tail = 0;
5106         txq->tx_pkt_head = 0;
5107         txq->tx_bd_tail = 0;
5108         txq->tx_bd_head = 0;
5109 }
5110
5111 static void bnx2x_init_tx_rings(struct bnx2x_softc *sc)
5112 {
5113         int i;
5114
5115         for (i = 0; i < sc->num_queues; i++) {
5116                 bnx2x_init_tx_ring_one(&sc->fp[i]);
5117         }
5118 }
5119
5120 static void bnx2x_init_def_sb(struct bnx2x_softc *sc)
5121 {
5122         struct host_sp_status_block *def_sb = sc->def_sb;
5123         rte_iova_t mapping = sc->def_sb_dma.paddr;
5124         int igu_sp_sb_index;
5125         int igu_seg_id;
5126         int port = SC_PORT(sc);
5127         int func = SC_FUNC(sc);
5128         int reg_offset, reg_offset_en5;
5129         uint64_t section;
5130         int index, sindex;
5131         struct hc_sp_status_block_data sp_sb_data;
5132
5133         memset(&sp_sb_data, 0, sizeof(struct hc_sp_status_block_data));
5134
5135         if (CHIP_INT_MODE_IS_BC(sc)) {
5136                 igu_sp_sb_index = DEF_SB_IGU_ID;
5137                 igu_seg_id = HC_SEG_ACCESS_DEF;
5138         } else {
5139                 igu_sp_sb_index = sc->igu_dsb_id;
5140                 igu_seg_id = IGU_SEG_ACCESS_DEF;
5141         }
5142
5143         /* attentions */
5144         section = ((uint64_t) mapping +
5145                    offsetof(struct host_sp_status_block, atten_status_block));
5146         def_sb->atten_status_block.status_block_id = igu_sp_sb_index;
5147         sc->attn_state = 0;
5148
5149         reg_offset = (port) ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 :
5150             MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0;
5151
5152         reg_offset_en5 = (port) ? MISC_REG_AEU_ENABLE5_FUNC_1_OUT_0 :
5153             MISC_REG_AEU_ENABLE5_FUNC_0_OUT_0;
5154
5155         for (index = 0; index < MAX_DYNAMIC_ATTN_GRPS; index++) {
5156 /* take care of sig[0]..sig[4] */
5157                 for (sindex = 0; sindex < 4; sindex++) {
5158                         sc->attn_group[index].sig[sindex] =
5159                             REG_RD(sc,
5160                                    (reg_offset + (sindex * 0x4) +
5161                                     (0x10 * index)));
5162                 }
5163
5164                 if (!CHIP_IS_E1x(sc)) {
5165                         /*
5166                          * enable5 is separate from the rest of the registers,
5167                          * and the address skip is 4 and not 16 between the
5168                          * different groups
5169                          */
5170                         sc->attn_group[index].sig[4] =
5171                             REG_RD(sc, (reg_offset_en5 + (0x4 * index)));
5172                 } else {
5173                         sc->attn_group[index].sig[4] = 0;
5174                 }
5175         }
5176
5177         if (sc->devinfo.int_block == INT_BLOCK_HC) {
5178                 reg_offset =
5179                     port ? HC_REG_ATTN_MSG1_ADDR_L : HC_REG_ATTN_MSG0_ADDR_L;
5180                 REG_WR(sc, reg_offset, U64_LO(section));
5181                 REG_WR(sc, (reg_offset + 4), U64_HI(section));
5182         } else if (!CHIP_IS_E1x(sc)) {
5183                 REG_WR(sc, IGU_REG_ATTN_MSG_ADDR_L, U64_LO(section));
5184                 REG_WR(sc, IGU_REG_ATTN_MSG_ADDR_H, U64_HI(section));
5185         }
5186
5187         section = ((uint64_t) mapping +
5188                    offsetof(struct host_sp_status_block, sp_sb));
5189
5190         bnx2x_zero_sp_sb(sc);
5191
5192         /* PCI guarantees endianity of regpair */
5193         sp_sb_data.state = SB_ENABLED;
5194         sp_sb_data.host_sb_addr.lo = U64_LO(section);
5195         sp_sb_data.host_sb_addr.hi = U64_HI(section);
5196         sp_sb_data.igu_sb_id = igu_sp_sb_index;
5197         sp_sb_data.igu_seg_id = igu_seg_id;
5198         sp_sb_data.p_func.pf_id = func;
5199         sp_sb_data.p_func.vnic_id = SC_VN(sc);
5200         sp_sb_data.p_func.vf_id = 0xff;
5201
5202         bnx2x_wr_sp_sb_data(sc, &sp_sb_data);
5203
5204         bnx2x_ack_sb(sc, sc->igu_dsb_id, USTORM_ID, 0, IGU_INT_ENABLE, 0);
5205 }
5206
5207 static void bnx2x_init_sp_ring(struct bnx2x_softc *sc)
5208 {
5209         atomic_store_rel_long(&sc->cq_spq_left, MAX_SPQ_PENDING);
5210         sc->spq_prod_idx = 0;
5211         sc->dsb_sp_prod =
5212             &sc->def_sb->sp_sb.index_values[HC_SP_INDEX_ETH_DEF_CONS];
5213         sc->spq_prod_bd = sc->spq;
5214         sc->spq_last_bd = (sc->spq_prod_bd + MAX_SP_DESC_CNT);
5215 }
5216
5217 static void bnx2x_init_eq_ring(struct bnx2x_softc *sc)
5218 {
5219         union event_ring_elem *elem;
5220         int i;
5221
5222         for (i = 1; i <= NUM_EQ_PAGES; i++) {
5223                 elem = &sc->eq[EQ_DESC_CNT_PAGE * i - 1];
5224
5225                 elem->next_page.addr.hi = htole32(U64_HI(sc->eq_dma.paddr +
5226                                                          BNX2X_PAGE_SIZE *
5227                                                          (i % NUM_EQ_PAGES)));
5228                 elem->next_page.addr.lo = htole32(U64_LO(sc->eq_dma.paddr +
5229                                                          BNX2X_PAGE_SIZE *
5230                                                          (i % NUM_EQ_PAGES)));
5231         }
5232
5233         sc->eq_cons = 0;
5234         sc->eq_prod = NUM_EQ_DESC;
5235         sc->eq_cons_sb = &sc->def_sb->sp_sb.index_values[HC_SP_INDEX_EQ_CONS];
5236
5237         atomic_store_rel_long(&sc->eq_spq_left,
5238                               (min((MAX_SP_DESC_CNT - MAX_SPQ_PENDING),
5239                                    NUM_EQ_DESC) - 1));
5240 }
5241
5242 static void bnx2x_init_internal_common(struct bnx2x_softc *sc)
5243 {
5244         int i;
5245
5246         /*
5247          * Zero this manually as its initialization is currently missing
5248          * in the initTool.
5249          */
5250         for (i = 0; i < (USTORM_AGG_DATA_SIZE >> 2); i++) {
5251                 REG_WR(sc,
5252                        (BAR_USTRORM_INTMEM + USTORM_AGG_DATA_OFFSET + (i * 4)),
5253                        0);
5254         }
5255
5256         if (!CHIP_IS_E1x(sc)) {
5257                 REG_WR8(sc, (BAR_CSTRORM_INTMEM + CSTORM_IGU_MODE_OFFSET),
5258                         CHIP_INT_MODE_IS_BC(sc) ? HC_IGU_BC_MODE :
5259                         HC_IGU_NBC_MODE);
5260         }
5261 }
5262
5263 static void bnx2x_init_internal(struct bnx2x_softc *sc, uint32_t load_code)
5264 {
5265         switch (load_code) {
5266         case FW_MSG_CODE_DRV_LOAD_COMMON:
5267         case FW_MSG_CODE_DRV_LOAD_COMMON_CHIP:
5268                 bnx2x_init_internal_common(sc);
5269                 /* no break */
5270
5271         case FW_MSG_CODE_DRV_LOAD_PORT:
5272                 /* nothing to do */
5273                 /* no break */
5274
5275         case FW_MSG_CODE_DRV_LOAD_FUNCTION:
5276                 /* internal memory per function is initialized inside bnx2x_pf_init */
5277                 break;
5278
5279         default:
5280                 PMD_DRV_LOG(NOTICE, sc, "Unknown load_code (0x%x) from MCP",
5281                             load_code);
5282                 break;
5283         }
5284 }
5285
5286 static void
5287 storm_memset_func_cfg(struct bnx2x_softc *sc,
5288                       struct tstorm_eth_function_common_config *tcfg,
5289                       uint16_t abs_fid)
5290 {
5291         uint32_t addr;
5292         size_t size;
5293
5294         addr = (BAR_TSTRORM_INTMEM +
5295                 TSTORM_FUNCTION_COMMON_CONFIG_OFFSET(abs_fid));
5296         size = sizeof(struct tstorm_eth_function_common_config);
5297         ecore_storm_memset_struct(sc, addr, size, (uint32_t *) tcfg);
5298 }
5299
5300 static void bnx2x_func_init(struct bnx2x_softc *sc, struct bnx2x_func_init_params *p)
5301 {
5302         struct tstorm_eth_function_common_config tcfg = { 0 };
5303
5304         if (CHIP_IS_E1x(sc)) {
5305                 storm_memset_func_cfg(sc, &tcfg, p->func_id);
5306         }
5307
5308         /* Enable the function in the FW */
5309         storm_memset_vf_to_pf(sc, p->func_id, p->pf_id);
5310         storm_memset_func_en(sc, p->func_id, 1);
5311
5312         /* spq */
5313         if (p->func_flgs & FUNC_FLG_SPQ) {
5314                 storm_memset_spq_addr(sc, p->spq_map, p->func_id);
5315                 REG_WR(sc,
5316                        (XSEM_REG_FAST_MEMORY +
5317                         XSTORM_SPQ_PROD_OFFSET(p->func_id)), p->spq_prod);
5318         }
5319 }
5320
5321 /*
5322  * Calculates the sum of vn_min_rates.
5323  * It's needed for further normalizing of the min_rates.
5324  * Returns:
5325  *   sum of vn_min_rates.
5326  *     or
5327  *   0 - if all the min_rates are 0.
5328  * In the later case fainess algorithm should be deactivated.
5329  * If all min rates are not zero then those that are zeroes will be set to 1.
5330  */
5331 static void bnx2x_calc_vn_min(struct bnx2x_softc *sc, struct cmng_init_input *input)
5332 {
5333         uint32_t vn_cfg;
5334         uint32_t vn_min_rate;
5335         int all_zero = 1;
5336         int vn;
5337
5338         for (vn = VN_0; vn < SC_MAX_VN_NUM(sc); vn++) {
5339                 vn_cfg = sc->devinfo.mf_info.mf_config[vn];
5340                 vn_min_rate = (((vn_cfg & FUNC_MF_CFG_MIN_BW_MASK) >>
5341                                 FUNC_MF_CFG_MIN_BW_SHIFT) * 100);
5342
5343                 if (vn_cfg & FUNC_MF_CFG_FUNC_HIDE) {
5344                         /* skip hidden VNs */
5345                         vn_min_rate = 0;
5346                 } else if (!vn_min_rate) {
5347                         /* If min rate is zero - set it to 100 */
5348                         vn_min_rate = DEF_MIN_RATE;
5349                 } else {
5350                         all_zero = 0;
5351                 }
5352
5353                 input->vnic_min_rate[vn] = vn_min_rate;
5354         }
5355
5356         /* if ETS or all min rates are zeros - disable fairness */
5357         if (all_zero) {
5358                 input->flags.cmng_enables &= ~CMNG_FLAGS_PER_PORT_FAIRNESS_VN;
5359         } else {
5360                 input->flags.cmng_enables |= CMNG_FLAGS_PER_PORT_FAIRNESS_VN;
5361         }
5362 }
5363
5364 static uint16_t
5365 bnx2x_extract_max_cfg(__rte_unused struct bnx2x_softc *sc, uint32_t mf_cfg)
5366 {
5367         uint16_t max_cfg = ((mf_cfg & FUNC_MF_CFG_MAX_BW_MASK) >>
5368                             FUNC_MF_CFG_MAX_BW_SHIFT);
5369
5370         if (!max_cfg) {
5371                 PMD_DRV_LOG(DEBUG, sc,
5372                             "Max BW configured to 0 - using 100 instead");
5373                 max_cfg = 100;
5374         }
5375
5376         return max_cfg;
5377 }
5378
5379 static void
5380 bnx2x_calc_vn_max(struct bnx2x_softc *sc, int vn, struct cmng_init_input *input)
5381 {
5382         uint16_t vn_max_rate;
5383         uint32_t vn_cfg = sc->devinfo.mf_info.mf_config[vn];
5384         uint32_t max_cfg;
5385
5386         if (vn_cfg & FUNC_MF_CFG_FUNC_HIDE) {
5387                 vn_max_rate = 0;
5388         } else {
5389                 max_cfg = bnx2x_extract_max_cfg(sc, vn_cfg);
5390
5391                 if (IS_MF_SI(sc)) {
5392                         /* max_cfg in percents of linkspeed */
5393                         vn_max_rate =
5394                             ((sc->link_vars.line_speed * max_cfg) / 100);
5395                 } else {        /* SD modes */
5396                         /* max_cfg is absolute in 100Mb units */
5397                         vn_max_rate = (max_cfg * 100);
5398                 }
5399         }
5400
5401         input->vnic_max_rate[vn] = vn_max_rate;
5402 }
5403
5404 static void
5405 bnx2x_cmng_fns_init(struct bnx2x_softc *sc, uint8_t read_cfg, uint8_t cmng_type)
5406 {
5407         struct cmng_init_input input;
5408         int vn;
5409
5410         memset(&input, 0, sizeof(struct cmng_init_input));
5411
5412         input.port_rate = sc->link_vars.line_speed;
5413
5414         if (cmng_type == CMNG_FNS_MINMAX) {
5415 /* read mf conf from shmem */
5416                 if (read_cfg) {
5417                         bnx2x_read_mf_cfg(sc);
5418                 }
5419
5420 /* get VN min rate and enable fairness if not 0 */
5421                 bnx2x_calc_vn_min(sc, &input);
5422
5423 /* get VN max rate */
5424                 if (sc->port.pmf) {
5425                         for (vn = VN_0; vn < SC_MAX_VN_NUM(sc); vn++) {
5426                                 bnx2x_calc_vn_max(sc, vn, &input);
5427                         }
5428                 }
5429
5430 /* always enable rate shaping and fairness */
5431                 input.flags.cmng_enables |= CMNG_FLAGS_PER_PORT_RATE_SHAPING_VN;
5432
5433                 ecore_init_cmng(&input, &sc->cmng);
5434                 return;
5435         }
5436 }
5437
5438 static int bnx2x_get_cmng_fns_mode(struct bnx2x_softc *sc)
5439 {
5440         if (CHIP_REV_IS_SLOW(sc)) {
5441                 return CMNG_FNS_NONE;
5442         }
5443
5444         if (IS_MF(sc)) {
5445                 return CMNG_FNS_MINMAX;
5446         }
5447
5448         return CMNG_FNS_NONE;
5449 }
5450
5451 static void
5452 storm_memset_cmng(struct bnx2x_softc *sc, struct cmng_init *cmng, uint8_t port)
5453 {
5454         int vn;
5455         int func;
5456         uint32_t addr;
5457         size_t size;
5458
5459         addr = (BAR_XSTRORM_INTMEM + XSTORM_CMNG_PER_PORT_VARS_OFFSET(port));
5460         size = sizeof(struct cmng_struct_per_port);
5461         ecore_storm_memset_struct(sc, addr, size, (uint32_t *) & cmng->port);
5462
5463         for (vn = VN_0; vn < SC_MAX_VN_NUM(sc); vn++) {
5464                 func = func_by_vn(sc, vn);
5465
5466                 addr = (BAR_XSTRORM_INTMEM +
5467                         XSTORM_RATE_SHAPING_PER_VN_VARS_OFFSET(func));
5468                 size = sizeof(struct rate_shaping_vars_per_vn);
5469                 ecore_storm_memset_struct(sc, addr, size,
5470                                           (uint32_t *) & cmng->
5471                                           vnic.vnic_max_rate[vn]);
5472
5473                 addr = (BAR_XSTRORM_INTMEM +
5474                         XSTORM_FAIRNESS_PER_VN_VARS_OFFSET(func));
5475                 size = sizeof(struct fairness_vars_per_vn);
5476                 ecore_storm_memset_struct(sc, addr, size,
5477                                           (uint32_t *) & cmng->
5478                                           vnic.vnic_min_rate[vn]);
5479         }
5480 }
5481
5482 static void bnx2x_pf_init(struct bnx2x_softc *sc)
5483 {
5484         struct bnx2x_func_init_params func_init;
5485         struct event_ring_data eq_data;
5486         uint16_t flags;
5487
5488         memset(&eq_data, 0, sizeof(struct event_ring_data));
5489         memset(&func_init, 0, sizeof(struct bnx2x_func_init_params));
5490
5491         if (!CHIP_IS_E1x(sc)) {
5492 /* reset IGU PF statistics: MSIX + ATTN */
5493 /* PF */
5494                 REG_WR(sc,
5495                        (IGU_REG_STATISTIC_NUM_MESSAGE_SENT +
5496                         (BNX2X_IGU_STAS_MSG_VF_CNT * 4) +
5497                         ((CHIP_IS_MODE_4_PORT(sc) ? SC_FUNC(sc) : SC_VN(sc)) *
5498                          4)), 0);
5499 /* ATTN */
5500                 REG_WR(sc,
5501                        (IGU_REG_STATISTIC_NUM_MESSAGE_SENT +
5502                         (BNX2X_IGU_STAS_MSG_VF_CNT * 4) +
5503                         (BNX2X_IGU_STAS_MSG_PF_CNT * 4) +
5504                         ((CHIP_IS_MODE_4_PORT(sc) ? SC_FUNC(sc) : SC_VN(sc)) *
5505                          4)), 0);
5506         }
5507
5508         /* function setup flags */
5509         flags = (FUNC_FLG_STATS | FUNC_FLG_LEADING | FUNC_FLG_SPQ);
5510
5511         func_init.func_flgs = flags;
5512         func_init.pf_id = SC_FUNC(sc);
5513         func_init.func_id = SC_FUNC(sc);
5514         func_init.spq_map = sc->spq_dma.paddr;
5515         func_init.spq_prod = sc->spq_prod_idx;
5516
5517         bnx2x_func_init(sc, &func_init);
5518
5519         memset(&sc->cmng, 0, sizeof(struct cmng_struct_per_port));
5520
5521         /*
5522          * Congestion management values depend on the link rate.
5523          * There is no active link so initial link rate is set to 10Gbps.
5524          * When the link comes up the congestion management values are
5525          * re-calculated according to the actual link rate.
5526          */
5527         sc->link_vars.line_speed = SPEED_10000;
5528         bnx2x_cmng_fns_init(sc, TRUE, bnx2x_get_cmng_fns_mode(sc));
5529
5530         /* Only the PMF sets the HW */
5531         if (sc->port.pmf) {
5532                 storm_memset_cmng(sc, &sc->cmng, SC_PORT(sc));
5533         }
5534
5535         /* init Event Queue - PCI bus guarantees correct endainity */
5536         eq_data.base_addr.hi = U64_HI(sc->eq_dma.paddr);
5537         eq_data.base_addr.lo = U64_LO(sc->eq_dma.paddr);
5538         eq_data.producer = sc->eq_prod;
5539         eq_data.index_id = HC_SP_INDEX_EQ_CONS;
5540         eq_data.sb_id = DEF_SB_ID;
5541         storm_memset_eq_data(sc, &eq_data, SC_FUNC(sc));
5542 }
5543
5544 static void bnx2x_hc_int_enable(struct bnx2x_softc *sc)
5545 {
5546         int port = SC_PORT(sc);
5547         uint32_t addr = (port) ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0;
5548         uint32_t val = REG_RD(sc, addr);
5549         uint8_t msix = (sc->interrupt_mode == INTR_MODE_MSIX)
5550             || (sc->interrupt_mode == INTR_MODE_SINGLE_MSIX);
5551         uint8_t single_msix = (sc->interrupt_mode == INTR_MODE_SINGLE_MSIX);
5552         uint8_t msi = (sc->interrupt_mode == INTR_MODE_MSI);
5553
5554         if (msix) {
5555                 val &= ~(HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
5556                          HC_CONFIG_0_REG_INT_LINE_EN_0);
5557                 val |= (HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
5558                         HC_CONFIG_0_REG_ATTN_BIT_EN_0);
5559                 if (single_msix) {
5560                         val |= HC_CONFIG_0_REG_SINGLE_ISR_EN_0;
5561                 }
5562         } else if (msi) {
5563                 val &= ~HC_CONFIG_0_REG_INT_LINE_EN_0;
5564                 val |= (HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
5565                         HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
5566                         HC_CONFIG_0_REG_ATTN_BIT_EN_0);
5567         } else {
5568                 val |= (HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
5569                         HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
5570                         HC_CONFIG_0_REG_INT_LINE_EN_0 |
5571                         HC_CONFIG_0_REG_ATTN_BIT_EN_0);
5572
5573                 REG_WR(sc, addr, val);
5574
5575                 val &= ~HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0;
5576         }
5577
5578         REG_WR(sc, addr, val);
5579
5580         /* ensure that HC_CONFIG is written before leading/trailing edge config */
5581         mb();
5582
5583         /* init leading/trailing edge */
5584         if (IS_MF(sc)) {
5585                 val = (0xee0f | (1 << (SC_VN(sc) + 4)));
5586                 if (sc->port.pmf) {
5587                         /* enable nig and gpio3 attention */
5588                         val |= 0x1100;
5589                 }
5590         } else {
5591                 val = 0xffff;
5592         }
5593
5594         REG_WR(sc, (HC_REG_TRAILING_EDGE_0 + port * 8), val);
5595         REG_WR(sc, (HC_REG_LEADING_EDGE_0 + port * 8), val);
5596
5597         /* make sure that interrupts are indeed enabled from here on */
5598         mb();
5599 }
5600
5601 static void bnx2x_igu_int_enable(struct bnx2x_softc *sc)
5602 {
5603         uint32_t val;
5604         uint8_t msix = (sc->interrupt_mode == INTR_MODE_MSIX)
5605             || (sc->interrupt_mode == INTR_MODE_SINGLE_MSIX);
5606         uint8_t single_msix = (sc->interrupt_mode == INTR_MODE_SINGLE_MSIX);
5607         uint8_t msi = (sc->interrupt_mode == INTR_MODE_MSI);
5608
5609         val = REG_RD(sc, IGU_REG_PF_CONFIGURATION);
5610
5611         if (msix) {
5612                 val &= ~(IGU_PF_CONF_INT_LINE_EN | IGU_PF_CONF_SINGLE_ISR_EN);
5613                 val |= (IGU_PF_CONF_MSI_MSIX_EN | IGU_PF_CONF_ATTN_BIT_EN);
5614                 if (single_msix) {
5615                         val |= IGU_PF_CONF_SINGLE_ISR_EN;
5616                 }
5617         } else if (msi) {
5618                 val &= ~IGU_PF_CONF_INT_LINE_EN;
5619                 val |= (IGU_PF_CONF_MSI_MSIX_EN |
5620                         IGU_PF_CONF_ATTN_BIT_EN | IGU_PF_CONF_SINGLE_ISR_EN);
5621         } else {
5622                 val &= ~IGU_PF_CONF_MSI_MSIX_EN;
5623                 val |= (IGU_PF_CONF_INT_LINE_EN |
5624                         IGU_PF_CONF_ATTN_BIT_EN | IGU_PF_CONF_SINGLE_ISR_EN);
5625         }
5626
5627         /* clean previous status - need to configure igu prior to ack */
5628         if ((!msix) || single_msix) {
5629                 REG_WR(sc, IGU_REG_PF_CONFIGURATION, val);
5630                 bnx2x_ack_int(sc);
5631         }
5632
5633         val |= IGU_PF_CONF_FUNC_EN;
5634
5635         PMD_DRV_LOG(DEBUG, sc, "write 0x%x to IGU mode %s",
5636                     val, ((msix) ? "MSI-X" : ((msi) ? "MSI" : "INTx")));
5637
5638         REG_WR(sc, IGU_REG_PF_CONFIGURATION, val);
5639
5640         mb();
5641
5642         /* init leading/trailing edge */
5643         if (IS_MF(sc)) {
5644                 val = (0xee0f | (1 << (SC_VN(sc) + 4)));
5645                 if (sc->port.pmf) {
5646                         /* enable nig and gpio3 attention */
5647                         val |= 0x1100;
5648                 }
5649         } else {
5650                 val = 0xffff;
5651         }
5652
5653         REG_WR(sc, IGU_REG_TRAILING_EDGE_LATCH, val);
5654         REG_WR(sc, IGU_REG_LEADING_EDGE_LATCH, val);
5655
5656         /* make sure that interrupts are indeed enabled from here on */
5657         mb();
5658 }
5659
5660 static void bnx2x_int_enable(struct bnx2x_softc *sc)
5661 {
5662         if (sc->devinfo.int_block == INT_BLOCK_HC) {
5663                 bnx2x_hc_int_enable(sc);
5664         } else {
5665                 bnx2x_igu_int_enable(sc);
5666         }
5667 }
5668
5669 static void bnx2x_hc_int_disable(struct bnx2x_softc *sc)
5670 {
5671         int port = SC_PORT(sc);
5672         uint32_t addr = (port) ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0;
5673         uint32_t val = REG_RD(sc, addr);
5674
5675         val &= ~(HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
5676                  HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
5677                  HC_CONFIG_0_REG_INT_LINE_EN_0 | HC_CONFIG_0_REG_ATTN_BIT_EN_0);
5678         /* flush all outstanding writes */
5679         mb();
5680
5681         REG_WR(sc, addr, val);
5682         if (REG_RD(sc, addr) != val) {
5683                 PMD_DRV_LOG(ERR, sc, "proper val not read from HC IGU!");
5684         }
5685 }
5686
5687 static void bnx2x_igu_int_disable(struct bnx2x_softc *sc)
5688 {
5689         uint32_t val = REG_RD(sc, IGU_REG_PF_CONFIGURATION);
5690
5691         val &= ~(IGU_PF_CONF_MSI_MSIX_EN |
5692                  IGU_PF_CONF_INT_LINE_EN | IGU_PF_CONF_ATTN_BIT_EN);
5693
5694         PMD_DRV_LOG(DEBUG, sc, "write %x to IGU", val);
5695
5696         /* flush all outstanding writes */
5697         mb();
5698
5699         REG_WR(sc, IGU_REG_PF_CONFIGURATION, val);
5700         if (REG_RD(sc, IGU_REG_PF_CONFIGURATION) != val) {
5701                 PMD_DRV_LOG(ERR, sc, "proper val not read from IGU!");
5702         }
5703 }
5704
5705 static void bnx2x_int_disable(struct bnx2x_softc *sc)
5706 {
5707         if (sc->devinfo.int_block == INT_BLOCK_HC) {
5708                 bnx2x_hc_int_disable(sc);
5709         } else {
5710                 bnx2x_igu_int_disable(sc);
5711         }
5712 }
5713
5714 static void bnx2x_nic_init(struct bnx2x_softc *sc, int load_code)
5715 {
5716         int i;
5717
5718         PMD_INIT_FUNC_TRACE(sc);
5719
5720         for (i = 0; i < sc->num_queues; i++) {
5721                 bnx2x_init_eth_fp(sc, i);
5722         }
5723
5724         rmb();                  /* ensure status block indices were read */
5725
5726         bnx2x_init_rx_rings(sc);
5727         bnx2x_init_tx_rings(sc);
5728
5729         if (IS_VF(sc)) {
5730                 bnx2x_memset_stats(sc);
5731                 return;
5732         }
5733
5734         /* initialize MOD_ABS interrupts */
5735         elink_init_mod_abs_int(sc, &sc->link_vars,
5736                                sc->devinfo.chip_id,
5737                                sc->devinfo.shmem_base,
5738                                sc->devinfo.shmem2_base, SC_PORT(sc));
5739
5740         bnx2x_init_def_sb(sc);
5741         bnx2x_update_dsb_idx(sc);
5742         bnx2x_init_sp_ring(sc);
5743         bnx2x_init_eq_ring(sc);
5744         bnx2x_init_internal(sc, load_code);
5745         bnx2x_pf_init(sc);
5746         bnx2x_stats_init(sc);
5747
5748         /* flush all before enabling interrupts */
5749         mb();
5750
5751         bnx2x_int_enable(sc);
5752
5753         /* check for SPIO5 */
5754         bnx2x_attn_int_deasserted0(sc,
5755                                  REG_RD(sc,
5756                                         (MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 +
5757                                          SC_PORT(sc) * 4)) &
5758                                  AEU_INPUTS_ATTN_BITS_SPIO5);
5759 }
5760
5761 static void bnx2x_init_objs(struct bnx2x_softc *sc)
5762 {
5763         /* mcast rules must be added to tx if tx switching is enabled */
5764         ecore_obj_type o_type;
5765         if (sc->flags & BNX2X_TX_SWITCHING)
5766                 o_type = ECORE_OBJ_TYPE_RX_TX;
5767         else
5768                 o_type = ECORE_OBJ_TYPE_RX;
5769
5770         /* RX_MODE controlling object */
5771         ecore_init_rx_mode_obj(sc, &sc->rx_mode_obj);
5772
5773         /* multicast configuration controlling object */
5774         ecore_init_mcast_obj(sc,
5775                              &sc->mcast_obj,
5776                              sc->fp[0].cl_id,
5777                              sc->fp[0].index,
5778                              SC_FUNC(sc),
5779                              SC_FUNC(sc),
5780                              BNX2X_SP(sc, mcast_rdata),
5781                              (rte_iova_t)BNX2X_SP_MAPPING(sc, mcast_rdata),
5782                              ECORE_FILTER_MCAST_PENDING,
5783                              &sc->sp_state, o_type);
5784
5785         /* Setup CAM credit pools */
5786         ecore_init_mac_credit_pool(sc,
5787                                    &sc->macs_pool,
5788                                    SC_FUNC(sc),
5789                                    CHIP_IS_E1x(sc) ? VNICS_PER_PORT(sc) :
5790                                    VNICS_PER_PATH(sc));
5791
5792         ecore_init_vlan_credit_pool(sc,
5793                                     &sc->vlans_pool,
5794                                     SC_ABS_FUNC(sc) >> 1,
5795                                     CHIP_IS_E1x(sc) ? VNICS_PER_PORT(sc) :
5796                                     VNICS_PER_PATH(sc));
5797
5798         /* RSS configuration object */
5799         ecore_init_rss_config_obj(sc, &sc->rss_conf_obj, sc->fp->cl_id,
5800                                   sc->fp->index, SC_FUNC(sc), SC_FUNC(sc),
5801                                   BNX2X_SP(sc, rss_rdata),
5802                                   (rte_iova_t)BNX2X_SP_MAPPING(sc, rss_rdata),
5803                                   ECORE_FILTER_RSS_CONF_PENDING, &sc->sp_state,
5804                                   ECORE_OBJ_TYPE_RX);
5805 }
5806
5807 /*
5808  * Initialize the function. This must be called before sending CLIENT_SETUP
5809  * for the first client.
5810  */
5811 static int bnx2x_func_start(struct bnx2x_softc *sc)
5812 {
5813         struct ecore_func_state_params func_params = { NULL };
5814         struct ecore_func_start_params *start_params =
5815             &func_params.params.start;
5816
5817         /* Prepare parameters for function state transitions */
5818         bnx2x_set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags);
5819
5820         func_params.f_obj = &sc->func_obj;
5821         func_params.cmd = ECORE_F_CMD_START;
5822
5823         /* Function parameters */
5824         start_params->mf_mode = sc->devinfo.mf_info.mf_mode;
5825         start_params->sd_vlan_tag = OVLAN(sc);
5826
5827         if (CHIP_IS_E2(sc) || CHIP_IS_E3(sc)) {
5828                 start_params->network_cos_mode = STATIC_COS;
5829         } else {                /* CHIP_IS_E1X */
5830                 start_params->network_cos_mode = FW_WRR;
5831         }
5832
5833         return ecore_func_state_change(sc, &func_params);
5834 }
5835
5836 static int bnx2x_set_power_state(struct bnx2x_softc *sc, uint8_t state)
5837 {
5838         uint16_t pmcsr;
5839
5840         /* If there is no power capability, silently succeed */
5841         if (!(sc->devinfo.pcie_cap_flags & BNX2X_PM_CAPABLE_FLAG)) {
5842                 PMD_DRV_LOG(INFO, sc, "No power capability");
5843                 return 0;
5844         }
5845
5846         pci_read(sc, (sc->devinfo.pcie_pm_cap_reg + PCIR_POWER_STATUS), &pmcsr,
5847                  2);
5848
5849         switch (state) {
5850         case PCI_PM_D0:
5851                 pci_write_word(sc,
5852                                (sc->devinfo.pcie_pm_cap_reg +
5853                                 PCIR_POWER_STATUS),
5854                                ((pmcsr & ~PCIM_PSTAT_DMASK) | PCIM_PSTAT_PME));
5855
5856                 if (pmcsr & PCIM_PSTAT_DMASK) {
5857                         /* delay required during transition out of D3hot */
5858                         DELAY(20000);
5859                 }
5860
5861                 break;
5862
5863         case PCI_PM_D3hot:
5864                 /* don't shut down the power for emulation and FPGA */
5865                 if (CHIP_REV_IS_SLOW(sc)) {
5866                         return 0;
5867                 }
5868
5869                 pmcsr &= ~PCIM_PSTAT_DMASK;
5870                 pmcsr |= PCIM_PSTAT_D3;
5871
5872                 if (sc->wol) {
5873                         pmcsr |= PCIM_PSTAT_PMEENABLE;
5874                 }
5875
5876                 pci_write_long(sc,
5877                                (sc->devinfo.pcie_pm_cap_reg +
5878                                 PCIR_POWER_STATUS), pmcsr);
5879
5880                 /*
5881                  * No more memory access after this point until device is brought back
5882                  * to D0 state.
5883                  */
5884                 break;
5885
5886         default:
5887                 PMD_DRV_LOG(NOTICE, sc, "Can't support PCI power state = %d",
5888                             state);
5889                 return -1;
5890         }
5891
5892         return 0;
5893 }
5894
5895 /* return true if succeeded to acquire the lock */
5896 static uint8_t bnx2x_trylock_hw_lock(struct bnx2x_softc *sc, uint32_t resource)
5897 {
5898         uint32_t lock_status;
5899         uint32_t resource_bit = (1 << resource);
5900         int func = SC_FUNC(sc);
5901         uint32_t hw_lock_control_reg;
5902
5903         /* Validating that the resource is within range */
5904         if (resource > HW_LOCK_MAX_RESOURCE_VALUE) {
5905                 PMD_DRV_LOG(INFO, sc,
5906                             "resource(0x%x) > HW_LOCK_MAX_RESOURCE_VALUE(0x%x)",
5907                             resource, HW_LOCK_MAX_RESOURCE_VALUE);
5908                 return FALSE;
5909         }
5910
5911         if (func <= 5) {
5912                 hw_lock_control_reg = (MISC_REG_DRIVER_CONTROL_1 + func * 8);
5913         } else {
5914                 hw_lock_control_reg =
5915                     (MISC_REG_DRIVER_CONTROL_7 + (func - 6) * 8);
5916         }
5917
5918         /* try to acquire the lock */
5919         REG_WR(sc, hw_lock_control_reg + 4, resource_bit);
5920         lock_status = REG_RD(sc, hw_lock_control_reg);
5921         if (lock_status & resource_bit) {
5922                 return TRUE;
5923         }
5924
5925         PMD_DRV_LOG(NOTICE, sc, "Failed to get a resource lock 0x%x", resource);
5926
5927         return FALSE;
5928 }
5929
5930 /*
5931  * Get the recovery leader resource id according to the engine this function
5932  * belongs to. Currently only only 2 engines is supported.
5933  */
5934 static int bnx2x_get_leader_lock_resource(struct bnx2x_softc *sc)
5935 {
5936         if (SC_PATH(sc)) {
5937                 return HW_LOCK_RESOURCE_RECOVERY_LEADER_1;
5938         } else {
5939                 return HW_LOCK_RESOURCE_RECOVERY_LEADER_0;
5940         }
5941 }
5942
5943 /* try to acquire a leader lock for current engine */
5944 static uint8_t bnx2x_trylock_leader_lock(struct bnx2x_softc *sc)
5945 {
5946         return bnx2x_trylock_hw_lock(sc, bnx2x_get_leader_lock_resource(sc));
5947 }
5948
5949 static int bnx2x_release_leader_lock(struct bnx2x_softc *sc)
5950 {
5951         return bnx2x_release_hw_lock(sc, bnx2x_get_leader_lock_resource(sc));
5952 }
5953
5954 /* close gates #2, #3 and #4 */
5955 static void bnx2x_set_234_gates(struct bnx2x_softc *sc, uint8_t close)
5956 {
5957         uint32_t val;
5958
5959         /* gates #2 and #4a are closed/opened */
5960         /* #4 */
5961         REG_WR(sc, PXP_REG_HST_DISCARD_DOORBELLS, ! !close);
5962         /* #2 */
5963         REG_WR(sc, PXP_REG_HST_DISCARD_INTERNAL_WRITES, ! !close);
5964
5965         /* #3 */
5966         if (CHIP_IS_E1x(sc)) {
5967 /* prevent interrupts from HC on both ports */
5968                 val = REG_RD(sc, HC_REG_CONFIG_1);
5969                 if (close)
5970                         REG_WR(sc, HC_REG_CONFIG_1, (val & ~(uint32_t)
5971                                                      HC_CONFIG_1_REG_BLOCK_DISABLE_1));
5972                 else
5973                         REG_WR(sc, HC_REG_CONFIG_1,
5974                                (val | HC_CONFIG_1_REG_BLOCK_DISABLE_1));
5975
5976                 val = REG_RD(sc, HC_REG_CONFIG_0);
5977                 if (close)
5978                         REG_WR(sc, HC_REG_CONFIG_0, (val & ~(uint32_t)
5979                                                      HC_CONFIG_0_REG_BLOCK_DISABLE_0));
5980                 else
5981                         REG_WR(sc, HC_REG_CONFIG_0,
5982                                (val | HC_CONFIG_0_REG_BLOCK_DISABLE_0));
5983
5984         } else {
5985 /* Prevent incoming interrupts in IGU */
5986                 val = REG_RD(sc, IGU_REG_BLOCK_CONFIGURATION);
5987
5988                 if (close)
5989                         REG_WR(sc, IGU_REG_BLOCK_CONFIGURATION,
5990                                (val & ~(uint32_t)
5991                                 IGU_BLOCK_CONFIGURATION_REG_BLOCK_ENABLE));
5992                 else
5993                         REG_WR(sc, IGU_REG_BLOCK_CONFIGURATION,
5994                                (val |
5995                                 IGU_BLOCK_CONFIGURATION_REG_BLOCK_ENABLE));
5996         }
5997
5998         wmb();
5999 }
6000
6001 /* poll for pending writes bit, it should get cleared in no more than 1s */
6002 static int bnx2x_er_poll_igu_vq(struct bnx2x_softc *sc)
6003 {
6004         uint32_t cnt = 1000;
6005         uint32_t pend_bits = 0;
6006
6007         do {
6008                 pend_bits = REG_RD(sc, IGU_REG_PENDING_BITS_STATUS);
6009
6010                 if (pend_bits == 0) {
6011                         break;
6012                 }
6013
6014                 DELAY(1000);
6015         } while (cnt-- > 0);
6016
6017         if (cnt <= 0) {
6018                 PMD_DRV_LOG(NOTICE, sc, "Still pending IGU requests bits=0x%08x!",
6019                             pend_bits);
6020                 return -1;
6021         }
6022
6023         return 0;
6024 }
6025
6026 #define SHARED_MF_CLP_MAGIC  0x80000000 /* 'magic' bit */
6027
6028 static void bnx2x_clp_reset_prep(struct bnx2x_softc *sc, uint32_t * magic_val)
6029 {
6030         /* Do some magic... */
6031         uint32_t val = MFCFG_RD(sc, shared_mf_config.clp_mb);
6032         *magic_val = val & SHARED_MF_CLP_MAGIC;
6033         MFCFG_WR(sc, shared_mf_config.clp_mb, val | SHARED_MF_CLP_MAGIC);
6034 }
6035
6036 /* restore the value of the 'magic' bit */
6037 static void bnx2x_clp_reset_done(struct bnx2x_softc *sc, uint32_t magic_val)
6038 {
6039         /* Restore the 'magic' bit value... */
6040         uint32_t val = MFCFG_RD(sc, shared_mf_config.clp_mb);
6041         MFCFG_WR(sc, shared_mf_config.clp_mb,
6042                  (val & (~SHARED_MF_CLP_MAGIC)) | magic_val);
6043 }
6044
6045 /* prepare for MCP reset, takes care of CLP configurations */
6046 static void bnx2x_reset_mcp_prep(struct bnx2x_softc *sc, uint32_t * magic_val)
6047 {
6048         uint32_t shmem;
6049         uint32_t validity_offset;
6050
6051         /* set `magic' bit in order to save MF config */
6052         bnx2x_clp_reset_prep(sc, magic_val);
6053
6054         /* get shmem offset */
6055         shmem = REG_RD(sc, MISC_REG_SHARED_MEM_ADDR);
6056         validity_offset =
6057             offsetof(struct shmem_region, validity_map[SC_PORT(sc)]);
6058
6059         /* Clear validity map flags */
6060         if (shmem > 0) {
6061                 REG_WR(sc, shmem + validity_offset, 0);
6062         }
6063 }
6064
6065 #define MCP_TIMEOUT      5000   /* 5 seconds (in ms) */
6066 #define MCP_ONE_TIMEOUT  100    /* 100 ms */
6067
6068 static void bnx2x_mcp_wait_one(struct bnx2x_softc *sc)
6069 {
6070         /* special handling for emulation and FPGA (10 times longer) */
6071         if (CHIP_REV_IS_SLOW(sc)) {
6072                 DELAY((MCP_ONE_TIMEOUT * 10) * 1000);
6073         } else {
6074                 DELAY((MCP_ONE_TIMEOUT) * 1000);
6075         }
6076 }
6077
6078 /* initialize shmem_base and waits for validity signature to appear */
6079 static int bnx2x_init_shmem(struct bnx2x_softc *sc)
6080 {
6081         int cnt = 0;
6082         uint32_t val = 0;
6083
6084         do {
6085                 sc->devinfo.shmem_base =
6086                     sc->link_params.shmem_base =
6087                     REG_RD(sc, MISC_REG_SHARED_MEM_ADDR);
6088
6089                 if (sc->devinfo.shmem_base) {
6090                         val = SHMEM_RD(sc, validity_map[SC_PORT(sc)]);
6091                         if (val & SHR_MEM_VALIDITY_MB)
6092                                 return 0;
6093                 }
6094
6095                 bnx2x_mcp_wait_one(sc);
6096
6097         } while (cnt++ < (MCP_TIMEOUT / MCP_ONE_TIMEOUT));
6098
6099         PMD_DRV_LOG(NOTICE, sc, "BAD MCP validity signature");
6100
6101         return -1;
6102 }
6103
6104 static int bnx2x_reset_mcp_comp(struct bnx2x_softc *sc, uint32_t magic_val)
6105 {
6106         int rc = bnx2x_init_shmem(sc);
6107
6108         /* Restore the `magic' bit value */
6109         bnx2x_clp_reset_done(sc, magic_val);
6110
6111         return rc;
6112 }
6113
6114 static void bnx2x_pxp_prep(struct bnx2x_softc *sc)
6115 {
6116         REG_WR(sc, PXP2_REG_RD_START_INIT, 0);
6117         REG_WR(sc, PXP2_REG_RQ_RBC_DONE, 0);
6118         wmb();
6119 }
6120
6121 /*
6122  * Reset the whole chip except for:
6123  *      - PCIE core
6124  *      - PCI Glue, PSWHST, PXP/PXP2 RF (all controlled by one reset bit)
6125  *      - IGU
6126  *      - MISC (including AEU)
6127  *      - GRC
6128  *      - RBCN, RBCP
6129  */
6130 static void bnx2x_process_kill_chip_reset(struct bnx2x_softc *sc, uint8_t global)
6131 {
6132         uint32_t not_reset_mask1, reset_mask1, not_reset_mask2, reset_mask2;
6133         uint32_t global_bits2, stay_reset2;
6134
6135         /*
6136          * Bits that have to be set in reset_mask2 if we want to reset 'global'
6137          * (per chip) blocks.
6138          */
6139         global_bits2 =
6140             MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_CMN_CPU |
6141             MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_CMN_CORE;
6142
6143         /*
6144          * Don't reset the following blocks.
6145          * Important: per port blocks (such as EMAC, BMAC, UMAC) can't be
6146          *            reset, as in 4 port device they might still be owned
6147          *            by the MCP (there is only one leader per path).
6148          */
6149         not_reset_mask1 =
6150             MISC_REGISTERS_RESET_REG_1_RST_HC |
6151             MISC_REGISTERS_RESET_REG_1_RST_PXPV |
6152             MISC_REGISTERS_RESET_REG_1_RST_PXP;
6153
6154         not_reset_mask2 =
6155             MISC_REGISTERS_RESET_REG_2_RST_PCI_MDIO |
6156             MISC_REGISTERS_RESET_REG_2_RST_EMAC0_HARD_CORE |
6157             MISC_REGISTERS_RESET_REG_2_RST_EMAC1_HARD_CORE |
6158             MISC_REGISTERS_RESET_REG_2_RST_MISC_CORE |
6159             MISC_REGISTERS_RESET_REG_2_RST_RBCN |
6160             MISC_REGISTERS_RESET_REG_2_RST_GRC |
6161             MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_REG_HARD_CORE |
6162             MISC_REGISTERS_RESET_REG_2_RST_MCP_N_HARD_CORE_RST_B |
6163             MISC_REGISTERS_RESET_REG_2_RST_ATC |
6164             MISC_REGISTERS_RESET_REG_2_PGLC |
6165             MISC_REGISTERS_RESET_REG_2_RST_BMAC0 |
6166             MISC_REGISTERS_RESET_REG_2_RST_BMAC1 |
6167             MISC_REGISTERS_RESET_REG_2_RST_EMAC0 |
6168             MISC_REGISTERS_RESET_REG_2_RST_EMAC1 |
6169             MISC_REGISTERS_RESET_REG_2_UMAC0 | MISC_REGISTERS_RESET_REG_2_UMAC1;
6170
6171         /*
6172          * Keep the following blocks in reset:
6173          *  - all xxMACs are handled by the elink code.
6174          */
6175         stay_reset2 =
6176             MISC_REGISTERS_RESET_REG_2_XMAC |
6177             MISC_REGISTERS_RESET_REG_2_XMAC_SOFT;
6178
6179         /* Full reset masks according to the chip */
6180         reset_mask1 = 0xffffffff;
6181
6182         if (CHIP_IS_E1H(sc))
6183                 reset_mask2 = 0x1ffff;
6184         else if (CHIP_IS_E2(sc))
6185                 reset_mask2 = 0xfffff;
6186         else                    /* CHIP_IS_E3 */
6187                 reset_mask2 = 0x3ffffff;
6188
6189         /* Don't reset global blocks unless we need to */
6190         if (!global)
6191                 reset_mask2 &= ~global_bits2;
6192
6193         /*
6194          * In case of attention in the QM, we need to reset PXP
6195          * (MISC_REGISTERS_RESET_REG_2_RST_PXP_RQ_RD_WR) before QM
6196          * because otherwise QM reset would release 'close the gates' shortly
6197          * before resetting the PXP, then the PSWRQ would send a write
6198          * request to PGLUE. Then when PXP is reset, PGLUE would try to
6199          * read the payload data from PSWWR, but PSWWR would not
6200          * respond. The write queue in PGLUE would stuck, dmae commands
6201          * would not return. Therefore it's important to reset the second
6202          * reset register (containing the
6203          * MISC_REGISTERS_RESET_REG_2_RST_PXP_RQ_RD_WR bit) before the
6204          * first one (containing the MISC_REGISTERS_RESET_REG_1_RST_QM
6205          * bit).
6206          */
6207         REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
6208                reset_mask2 & (~not_reset_mask2));
6209
6210         REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR,
6211                reset_mask1 & (~not_reset_mask1));
6212
6213         mb();
6214         wmb();
6215
6216         REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET,
6217                reset_mask2 & (~stay_reset2));
6218
6219         mb();
6220         wmb();
6221
6222         REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, reset_mask1);
6223         wmb();
6224 }
6225
6226 static int bnx2x_process_kill(struct bnx2x_softc *sc, uint8_t global)
6227 {
6228         int cnt = 1000;
6229         uint32_t val = 0;
6230         uint32_t sr_cnt, blk_cnt, port_is_idle_0, port_is_idle_1, pgl_exp_rom2;
6231         uint32_t tags_63_32 = 0;
6232
6233         /* Empty the Tetris buffer, wait for 1s */
6234         do {
6235                 sr_cnt = REG_RD(sc, PXP2_REG_RD_SR_CNT);
6236                 blk_cnt = REG_RD(sc, PXP2_REG_RD_BLK_CNT);
6237                 port_is_idle_0 = REG_RD(sc, PXP2_REG_RD_PORT_IS_IDLE_0);
6238                 port_is_idle_1 = REG_RD(sc, PXP2_REG_RD_PORT_IS_IDLE_1);
6239                 pgl_exp_rom2 = REG_RD(sc, PXP2_REG_PGL_EXP_ROM2);
6240                 if (CHIP_IS_E3(sc)) {
6241                         tags_63_32 = REG_RD(sc, PGLUE_B_REG_TAGS_63_32);
6242                 }
6243
6244                 if ((sr_cnt == 0x7e) && (blk_cnt == 0xa0) &&
6245                     ((port_is_idle_0 & 0x1) == 0x1) &&
6246                     ((port_is_idle_1 & 0x1) == 0x1) &&
6247                     (pgl_exp_rom2 == 0xffffffff) &&
6248                     (!CHIP_IS_E3(sc) || (tags_63_32 == 0xffffffff)))
6249                         break;
6250                 DELAY(1000);
6251         } while (cnt-- > 0);
6252
6253         if (cnt <= 0) {
6254                 PMD_DRV_LOG(NOTICE, sc,
6255                             "ERROR: Tetris buffer didn't get empty or there "
6256                             "are still outstanding read requests after 1s! "
6257                             "sr_cnt=0x%08x, blk_cnt=0x%08x, port_is_idle_0=0x%08x, "
6258                             "port_is_idle_1=0x%08x, pgl_exp_rom2=0x%08x",
6259                             sr_cnt, blk_cnt, port_is_idle_0, port_is_idle_1,
6260                             pgl_exp_rom2);
6261                 return -1;
6262         }
6263
6264         mb();
6265
6266         /* Close gates #2, #3 and #4 */
6267         bnx2x_set_234_gates(sc, TRUE);
6268
6269         /* Poll for IGU VQs for 57712 and newer chips */
6270         if (!CHIP_IS_E1x(sc) && bnx2x_er_poll_igu_vq(sc)) {
6271                 return -1;
6272         }
6273
6274         /* clear "unprepared" bit */
6275         REG_WR(sc, MISC_REG_UNPREPARED, 0);
6276         mb();
6277
6278         /* Make sure all is written to the chip before the reset */
6279         wmb();
6280
6281         /*
6282          * Wait for 1ms to empty GLUE and PCI-E core queues,
6283          * PSWHST, GRC and PSWRD Tetris buffer.
6284          */
6285         DELAY(1000);
6286
6287         /* Prepare to chip reset: */
6288         /* MCP */
6289         if (global) {
6290                 bnx2x_reset_mcp_prep(sc, &val);
6291         }
6292
6293         /* PXP */
6294         bnx2x_pxp_prep(sc);
6295         mb();
6296
6297         /* reset the chip */
6298         bnx2x_process_kill_chip_reset(sc, global);
6299         mb();
6300
6301         /* Recover after reset: */
6302         /* MCP */
6303         if (global && bnx2x_reset_mcp_comp(sc, val)) {
6304                 return -1;
6305         }
6306
6307         /* Open the gates #2, #3 and #4 */
6308         bnx2x_set_234_gates(sc, FALSE);
6309
6310         return 0;
6311 }
6312
6313 static int bnx2x_leader_reset(struct bnx2x_softc *sc)
6314 {
6315         int rc = 0;
6316         uint8_t global = bnx2x_reset_is_global(sc);
6317         uint32_t load_code;
6318
6319         /*
6320          * If not going to reset MCP, load "fake" driver to reset HW while
6321          * driver is owner of the HW.
6322          */
6323         if (!global && !BNX2X_NOMCP(sc)) {
6324                 load_code = bnx2x_fw_command(sc, DRV_MSG_CODE_LOAD_REQ,
6325                                            DRV_MSG_CODE_LOAD_REQ_WITH_LFA);
6326                 if (!load_code) {
6327                         PMD_DRV_LOG(NOTICE, sc, "MCP response failure, aborting");
6328                         rc = -1;
6329                         goto exit_leader_reset;
6330                 }
6331
6332                 if ((load_code != FW_MSG_CODE_DRV_LOAD_COMMON_CHIP) &&
6333                     (load_code != FW_MSG_CODE_DRV_LOAD_COMMON)) {
6334                         PMD_DRV_LOG(NOTICE, sc,
6335                                     "MCP unexpected response, aborting");
6336                         rc = -1;
6337                         goto exit_leader_reset2;
6338                 }
6339
6340                 load_code = bnx2x_fw_command(sc, DRV_MSG_CODE_LOAD_DONE, 0);
6341                 if (!load_code) {
6342                         PMD_DRV_LOG(NOTICE, sc, "MCP response failure, aborting");
6343                         rc = -1;
6344                         goto exit_leader_reset2;
6345                 }
6346         }
6347
6348         /* try to recover after the failure */
6349         if (bnx2x_process_kill(sc, global)) {
6350                 PMD_DRV_LOG(NOTICE, sc, "Something bad occurred on engine %d!",
6351                             SC_PATH(sc));
6352                 rc = -1;
6353                 goto exit_leader_reset2;
6354         }
6355
6356         /*
6357          * Clear the RESET_IN_PROGRESS and RESET_GLOBAL bits and update the driver
6358          * state.
6359          */
6360         bnx2x_set_reset_done(sc);
6361         if (global) {
6362                 bnx2x_clear_reset_global(sc);
6363         }
6364
6365 exit_leader_reset2:
6366
6367         /* unload "fake driver" if it was loaded */
6368         if (!global &&!BNX2X_NOMCP(sc)) {
6369                 bnx2x_fw_command(sc, DRV_MSG_CODE_UNLOAD_REQ_WOL_MCP, 0);
6370                 bnx2x_fw_command(sc, DRV_MSG_CODE_UNLOAD_DONE, 0);
6371         }
6372
6373 exit_leader_reset:
6374
6375         sc->is_leader = 0;
6376         bnx2x_release_leader_lock(sc);
6377
6378         mb();
6379         return rc;
6380 }
6381
6382 /*
6383  * prepare INIT transition, parameters configured:
6384  *   - HC configuration
6385  *   - Queue's CDU context
6386  */
6387 static void
6388 bnx2x_pf_q_prep_init(struct bnx2x_softc *sc, struct bnx2x_fastpath *fp,
6389                    struct ecore_queue_init_params *init_params)
6390 {
6391         uint8_t cos;
6392         int cxt_index, cxt_offset;
6393
6394         bnx2x_set_bit(ECORE_Q_FLG_HC, &init_params->rx.flags);
6395         bnx2x_set_bit(ECORE_Q_FLG_HC, &init_params->tx.flags);
6396
6397         bnx2x_set_bit(ECORE_Q_FLG_HC_EN, &init_params->rx.flags);
6398         bnx2x_set_bit(ECORE_Q_FLG_HC_EN, &init_params->tx.flags);
6399
6400         /* HC rate */
6401         init_params->rx.hc_rate =
6402             sc->hc_rx_ticks ? (1000000 / sc->hc_rx_ticks) : 0;
6403         init_params->tx.hc_rate =
6404             sc->hc_tx_ticks ? (1000000 / sc->hc_tx_ticks) : 0;
6405
6406         /* FW SB ID */
6407         init_params->rx.fw_sb_id = init_params->tx.fw_sb_id = fp->fw_sb_id;
6408
6409         /* CQ index among the SB indices */
6410         init_params->rx.sb_cq_index = HC_INDEX_ETH_RX_CQ_CONS;
6411         init_params->tx.sb_cq_index = HC_INDEX_ETH_FIRST_TX_CQ_CONS;
6412
6413         /* set maximum number of COSs supported by this queue */
6414         init_params->max_cos = sc->max_cos;
6415
6416         /* set the context pointers queue object */
6417         for (cos = FIRST_TX_COS_INDEX; cos < init_params->max_cos; cos++) {
6418                 cxt_index = fp->index / ILT_PAGE_CIDS;
6419                 cxt_offset = fp->index - (cxt_index * ILT_PAGE_CIDS);
6420                 init_params->cxts[cos] =
6421                     &sc->context[cxt_index].vcxt[cxt_offset].eth;
6422         }
6423 }
6424
6425 /* set flags that are common for the Tx-only and not normal connections */
6426 static unsigned long
6427 bnx2x_get_common_flags(struct bnx2x_softc *sc, uint8_t zero_stats)
6428 {
6429         unsigned long flags = 0;
6430
6431         /* PF driver will always initialize the Queue to an ACTIVE state */
6432         bnx2x_set_bit(ECORE_Q_FLG_ACTIVE, &flags);
6433
6434         /*
6435          * tx only connections collect statistics (on the same index as the
6436          * parent connection). The statistics are zeroed when the parent
6437          * connection is initialized.
6438          */
6439
6440         bnx2x_set_bit(ECORE_Q_FLG_STATS, &flags);
6441         if (zero_stats) {
6442                 bnx2x_set_bit(ECORE_Q_FLG_ZERO_STATS, &flags);
6443         }
6444
6445         /*
6446          * tx only connections can support tx-switching, though their
6447          * CoS-ness doesn't survive the loopback
6448          */
6449         if (sc->flags & BNX2X_TX_SWITCHING) {
6450                 bnx2x_set_bit(ECORE_Q_FLG_TX_SWITCH, &flags);
6451         }
6452
6453         bnx2x_set_bit(ECORE_Q_FLG_PCSUM_ON_PKT, &flags);
6454
6455         return flags;
6456 }
6457
6458 static unsigned long bnx2x_get_q_flags(struct bnx2x_softc *sc, uint8_t leading)
6459 {
6460         unsigned long flags = 0;
6461
6462         if (IS_MF_SD(sc)) {
6463                 bnx2x_set_bit(ECORE_Q_FLG_OV, &flags);
6464         }
6465
6466         if (leading) {
6467                 bnx2x_set_bit(ECORE_Q_FLG_LEADING_RSS, &flags);
6468                 bnx2x_set_bit(ECORE_Q_FLG_MCAST, &flags);
6469         }
6470
6471         bnx2x_set_bit(ECORE_Q_FLG_VLAN, &flags);
6472
6473         /* merge with common flags */
6474         return flags | bnx2x_get_common_flags(sc, TRUE);
6475 }
6476
6477 static void
6478 bnx2x_pf_q_prep_general(struct bnx2x_softc *sc, struct bnx2x_fastpath *fp,
6479                       struct ecore_general_setup_params *gen_init, uint8_t cos)
6480 {
6481         gen_init->stat_id = bnx2x_stats_id(fp);
6482         gen_init->spcl_id = fp->cl_id;
6483         gen_init->mtu = sc->mtu;
6484         gen_init->cos = cos;
6485 }
6486
6487 static void
6488 bnx2x_pf_rx_q_prep(struct bnx2x_softc *sc, struct bnx2x_fastpath *fp,
6489                  struct rxq_pause_params *pause,
6490                  struct ecore_rxq_setup_params *rxq_init)
6491 {
6492         struct bnx2x_rx_queue *rxq;
6493
6494         rxq = sc->rx_queues[fp->index];
6495         if (!rxq) {
6496                 PMD_RX_LOG(ERR, "RX queue is NULL");
6497                 return;
6498         }
6499         /* pause */
6500         pause->bd_th_lo = BD_TH_LO(sc);
6501         pause->bd_th_hi = BD_TH_HI(sc);
6502
6503         pause->rcq_th_lo = RCQ_TH_LO(sc);
6504         pause->rcq_th_hi = RCQ_TH_HI(sc);
6505
6506         /* validate rings have enough entries to cross high thresholds */
6507         if (sc->dropless_fc &&
6508             pause->bd_th_hi + FW_PREFETCH_CNT > sc->rx_ring_size) {
6509                 PMD_DRV_LOG(WARNING, sc, "rx bd ring threshold limit");
6510         }
6511
6512         if (sc->dropless_fc &&
6513             pause->rcq_th_hi + FW_PREFETCH_CNT > USABLE_RCQ_ENTRIES(rxq)) {
6514                 PMD_DRV_LOG(WARNING, sc, "rcq ring threshold limit");
6515         }
6516
6517         pause->pri_map = 1;
6518
6519         /* rxq setup */
6520         rxq_init->dscr_map = (rte_iova_t)rxq->rx_ring_phys_addr;
6521         rxq_init->rcq_map = (rte_iova_t)rxq->cq_ring_phys_addr;
6522         rxq_init->rcq_np_map = (rte_iova_t)(rxq->cq_ring_phys_addr +
6523                                               BNX2X_PAGE_SIZE);
6524
6525         /*
6526          * This should be a maximum number of data bytes that may be
6527          * placed on the BD (not including paddings).
6528          */
6529         rxq_init->buf_sz = (fp->rx_buf_size - IP_HEADER_ALIGNMENT_PADDING);
6530
6531         rxq_init->cl_qzone_id = fp->cl_qzone_id;
6532         rxq_init->rss_engine_id = SC_FUNC(sc);
6533         rxq_init->mcast_engine_id = SC_FUNC(sc);
6534
6535         rxq_init->cache_line_log = BNX2X_RX_ALIGN_SHIFT;
6536         rxq_init->fw_sb_id = fp->fw_sb_id;
6537
6538         rxq_init->sb_cq_index = HC_INDEX_ETH_RX_CQ_CONS;
6539
6540         /*
6541          * configure silent vlan removal
6542          * if multi function mode is afex, then mask default vlan
6543          */
6544         if (IS_MF_AFEX(sc)) {
6545                 rxq_init->silent_removal_value =
6546                     sc->devinfo.mf_info.afex_def_vlan_tag;
6547                 rxq_init->silent_removal_mask = EVL_VLID_MASK;
6548         }
6549 }
6550
6551 static void
6552 bnx2x_pf_tx_q_prep(struct bnx2x_softc *sc, struct bnx2x_fastpath *fp,
6553                  struct ecore_txq_setup_params *txq_init, uint8_t cos)
6554 {
6555         struct bnx2x_tx_queue *txq = fp->sc->tx_queues[fp->index];
6556
6557         if (!txq) {
6558                 PMD_TX_LOG(ERR, "ERROR: TX queue is NULL");
6559                 return;
6560         }
6561         txq_init->dscr_map = (rte_iova_t)txq->tx_ring_phys_addr;
6562         txq_init->sb_cq_index = HC_INDEX_ETH_FIRST_TX_CQ_CONS + cos;
6563         txq_init->traffic_type = LLFC_TRAFFIC_TYPE_NW;
6564         txq_init->fw_sb_id = fp->fw_sb_id;
6565
6566         /*
6567          * set the TSS leading client id for TX classfication to the
6568          * leading RSS client id
6569          */
6570         txq_init->tss_leading_cl_id = BNX2X_FP(sc, 0, cl_id);
6571 }
6572
6573 /*
6574  * This function performs 2 steps in a queue state machine:
6575  *   1) RESET->INIT
6576  *   2) INIT->SETUP
6577  */
6578 static int
6579 bnx2x_setup_queue(struct bnx2x_softc *sc, struct bnx2x_fastpath *fp, uint8_t leading)
6580 {
6581         struct ecore_queue_state_params q_params = { NULL };
6582         struct ecore_queue_setup_params *setup_params = &q_params.params.setup;
6583         int rc;
6584
6585         PMD_DRV_LOG(DEBUG, sc, "setting up queue %d", fp->index);
6586
6587         bnx2x_ack_sb(sc, fp->igu_sb_id, USTORM_ID, 0, IGU_INT_ENABLE, 0);
6588
6589         q_params.q_obj = &BNX2X_SP_OBJ(sc, fp).q_obj;
6590
6591         /* we want to wait for completion in this context */
6592         bnx2x_set_bit(RAMROD_COMP_WAIT, &q_params.ramrod_flags);
6593
6594         /* prepare the INIT parameters */
6595         bnx2x_pf_q_prep_init(sc, fp, &q_params.params.init);
6596
6597         /* Set the command */
6598         q_params.cmd = ECORE_Q_CMD_INIT;
6599
6600         /* Change the state to INIT */
6601         rc = ecore_queue_state_change(sc, &q_params);
6602         if (rc) {
6603                 PMD_DRV_LOG(NOTICE, sc, "Queue(%d) INIT failed", fp->index);
6604                 return rc;
6605         }
6606
6607         PMD_DRV_LOG(DEBUG, sc, "init complete");
6608
6609         /* now move the Queue to the SETUP state */
6610         memset(setup_params, 0, sizeof(*setup_params));
6611
6612         /* set Queue flags */
6613         setup_params->flags = bnx2x_get_q_flags(sc, leading);
6614
6615         /* set general SETUP parameters */
6616         bnx2x_pf_q_prep_general(sc, fp, &setup_params->gen_params,
6617                               FIRST_TX_COS_INDEX);
6618
6619         bnx2x_pf_rx_q_prep(sc, fp,
6620                          &setup_params->pause_params,
6621                          &setup_params->rxq_params);
6622
6623         bnx2x_pf_tx_q_prep(sc, fp, &setup_params->txq_params, FIRST_TX_COS_INDEX);
6624
6625         /* Set the command */
6626         q_params.cmd = ECORE_Q_CMD_SETUP;
6627
6628         /* change the state to SETUP */
6629         rc = ecore_queue_state_change(sc, &q_params);
6630         if (rc) {
6631                 PMD_DRV_LOG(NOTICE, sc, "Queue(%d) SETUP failed", fp->index);
6632                 return rc;
6633         }
6634
6635         return rc;
6636 }
6637
6638 static int bnx2x_setup_leading(struct bnx2x_softc *sc)
6639 {
6640         if (IS_PF(sc))
6641                 return bnx2x_setup_queue(sc, &sc->fp[0], TRUE);
6642         else                    /* VF */
6643                 return bnx2x_vf_setup_queue(sc, &sc->fp[0], TRUE);
6644 }
6645
6646 static int
6647 bnx2x_config_rss_pf(struct bnx2x_softc *sc, struct ecore_rss_config_obj *rss_obj,
6648                   uint8_t config_hash)
6649 {
6650         struct ecore_config_rss_params params = { NULL };
6651         uint32_t i;
6652
6653         /*
6654          * Although RSS is meaningless when there is a single HW queue we
6655          * still need it enabled in order to have HW Rx hash generated.
6656          */
6657
6658         params.rss_obj = rss_obj;
6659
6660         bnx2x_set_bit(RAMROD_COMP_WAIT, &params.ramrod_flags);
6661
6662         bnx2x_set_bit(ECORE_RSS_MODE_REGULAR, &params.rss_flags);
6663
6664         /* RSS configuration */
6665         bnx2x_set_bit(ECORE_RSS_IPV4, &params.rss_flags);
6666         bnx2x_set_bit(ECORE_RSS_IPV4_TCP, &params.rss_flags);
6667         bnx2x_set_bit(ECORE_RSS_IPV6, &params.rss_flags);
6668         bnx2x_set_bit(ECORE_RSS_IPV6_TCP, &params.rss_flags);
6669         if (rss_obj->udp_rss_v4) {
6670                 bnx2x_set_bit(ECORE_RSS_IPV4_UDP, &params.rss_flags);
6671         }
6672         if (rss_obj->udp_rss_v6) {
6673                 bnx2x_set_bit(ECORE_RSS_IPV6_UDP, &params.rss_flags);
6674         }
6675
6676         /* Hash bits */
6677         params.rss_result_mask = MULTI_MASK;
6678
6679         rte_memcpy(params.ind_table, rss_obj->ind_table,
6680                          sizeof(params.ind_table));
6681
6682         if (config_hash) {
6683 /* RSS keys */
6684                 for (i = 0; i < sizeof(params.rss_key) / 4; i++) {
6685                         params.rss_key[i] = (uint32_t) rte_rand();
6686                 }
6687
6688                 bnx2x_set_bit(ECORE_RSS_SET_SRCH, &params.rss_flags);
6689         }
6690
6691         if (IS_PF(sc))
6692                 return ecore_config_rss(sc, &params);
6693         else
6694                 return bnx2x_vf_config_rss(sc, &params);
6695 }
6696
6697 static int bnx2x_config_rss_eth(struct bnx2x_softc *sc, uint8_t config_hash)
6698 {
6699         return bnx2x_config_rss_pf(sc, &sc->rss_conf_obj, config_hash);
6700 }
6701
6702 static int bnx2x_init_rss_pf(struct bnx2x_softc *sc)
6703 {
6704         uint8_t num_eth_queues = BNX2X_NUM_ETH_QUEUES(sc);
6705         uint32_t i;
6706
6707         /*
6708          * Prepare the initial contents of the indirection table if
6709          * RSS is enabled
6710          */
6711         for (i = 0; i < sizeof(sc->rss_conf_obj.ind_table); i++) {
6712                 sc->rss_conf_obj.ind_table[i] =
6713                     (sc->fp->cl_id + (i % num_eth_queues));
6714         }
6715
6716         if (sc->udp_rss) {
6717                 sc->rss_conf_obj.udp_rss_v4 = sc->rss_conf_obj.udp_rss_v6 = 1;
6718         }
6719
6720         /*
6721          * For 57711 SEARCHER configuration (rss_keys) is
6722          * per-port, so if explicit configuration is needed, do it only
6723          * for a PMF.
6724          *
6725          * For 57712 and newer it's a per-function configuration.
6726          */
6727         return bnx2x_config_rss_eth(sc, sc->port.pmf || !CHIP_IS_E1x(sc));
6728 }
6729
6730 static int
6731 bnx2x_set_mac_one(struct bnx2x_softc *sc, uint8_t * mac,
6732                 struct ecore_vlan_mac_obj *obj, uint8_t set, int mac_type,
6733                 unsigned long *ramrod_flags)
6734 {
6735         struct ecore_vlan_mac_ramrod_params ramrod_param;
6736         int rc;
6737
6738         memset(&ramrod_param, 0, sizeof(ramrod_param));
6739
6740         /* fill in general parameters */
6741         ramrod_param.vlan_mac_obj = obj;
6742         ramrod_param.ramrod_flags = *ramrod_flags;
6743
6744         /* fill a user request section if needed */
6745         if (!bnx2x_test_bit(RAMROD_CONT, ramrod_flags)) {
6746                 rte_memcpy(ramrod_param.user_req.u.mac.mac, mac,
6747                                  ETH_ALEN);
6748
6749                 bnx2x_set_bit(mac_type, &ramrod_param.user_req.vlan_mac_flags);
6750
6751 /* Set the command: ADD or DEL */
6752                 ramrod_param.user_req.cmd = (set) ? ECORE_VLAN_MAC_ADD :
6753                     ECORE_VLAN_MAC_DEL;
6754         }
6755
6756         rc = ecore_config_vlan_mac(sc, &ramrod_param);
6757
6758         if (rc == ECORE_EXISTS) {
6759                 PMD_DRV_LOG(INFO, sc, "Failed to schedule ADD operations (EEXIST)");
6760 /* do not treat adding same MAC as error */
6761                 rc = 0;
6762         } else if (rc < 0) {
6763                 PMD_DRV_LOG(ERR, sc,
6764                             "%s MAC failed (%d)", (set ? "Set" : "Delete"), rc);
6765         }
6766
6767         return rc;
6768 }
6769
6770 static int bnx2x_set_eth_mac(struct bnx2x_softc *sc, uint8_t set)
6771 {
6772         unsigned long ramrod_flags = 0;
6773
6774         PMD_DRV_LOG(DEBUG, sc, "Adding Ethernet MAC");
6775
6776         bnx2x_set_bit(RAMROD_COMP_WAIT, &ramrod_flags);
6777
6778         /* Eth MAC is set on RSS leading client (fp[0]) */
6779         return bnx2x_set_mac_one(sc, sc->link_params.mac_addr,
6780                                &sc->sp_objs->mac_obj,
6781                                set, ECORE_ETH_MAC, &ramrod_flags);
6782 }
6783
6784 static int bnx2x_get_cur_phy_idx(struct bnx2x_softc *sc)
6785 {
6786         uint32_t sel_phy_idx = 0;
6787
6788         if (sc->link_params.num_phys <= 1) {
6789                 return ELINK_INT_PHY;
6790         }
6791
6792         if (sc->link_vars.link_up) {
6793                 sel_phy_idx = ELINK_EXT_PHY1;
6794 /* In case link is SERDES, check if the ELINK_EXT_PHY2 is the one */
6795                 if ((sc->link_vars.link_status & LINK_STATUS_SERDES_LINK) &&
6796                     (sc->link_params.phy[ELINK_EXT_PHY2].supported &
6797                      ELINK_SUPPORTED_FIBRE))
6798                         sel_phy_idx = ELINK_EXT_PHY2;
6799         } else {
6800                 switch (elink_phy_selection(&sc->link_params)) {
6801                 case PORT_HW_CFG_PHY_SELECTION_HARDWARE_DEFAULT:
6802                 case PORT_HW_CFG_PHY_SELECTION_FIRST_PHY:
6803                 case PORT_HW_CFG_PHY_SELECTION_FIRST_PHY_PRIORITY:
6804                         sel_phy_idx = ELINK_EXT_PHY1;
6805                         break;
6806                 case PORT_HW_CFG_PHY_SELECTION_SECOND_PHY:
6807                 case PORT_HW_CFG_PHY_SELECTION_SECOND_PHY_PRIORITY:
6808                         sel_phy_idx = ELINK_EXT_PHY2;
6809                         break;
6810                 }
6811         }
6812
6813         return sel_phy_idx;
6814 }
6815
6816 static int bnx2x_get_link_cfg_idx(struct bnx2x_softc *sc)
6817 {
6818         uint32_t sel_phy_idx = bnx2x_get_cur_phy_idx(sc);
6819
6820         /*
6821          * The selected activated PHY is always after swapping (in case PHY
6822          * swapping is enabled). So when swapping is enabled, we need to reverse
6823          * the configuration
6824          */
6825
6826         if (sc->link_params.multi_phy_config & PORT_HW_CFG_PHY_SWAPPED_ENABLED) {
6827                 if (sel_phy_idx == ELINK_EXT_PHY1)
6828                         sel_phy_idx = ELINK_EXT_PHY2;
6829                 else if (sel_phy_idx == ELINK_EXT_PHY2)
6830                         sel_phy_idx = ELINK_EXT_PHY1;
6831         }
6832
6833         return ELINK_LINK_CONFIG_IDX(sel_phy_idx);
6834 }
6835
6836 static void bnx2x_set_requested_fc(struct bnx2x_softc *sc)
6837 {
6838         /*
6839          * Initialize link parameters structure variables
6840          * It is recommended to turn off RX FC for jumbo frames
6841          * for better performance
6842          */
6843         if (CHIP_IS_E1x(sc) && (sc->mtu > 5000)) {
6844                 sc->link_params.req_fc_auto_adv = ELINK_FLOW_CTRL_TX;
6845         } else {
6846                 sc->link_params.req_fc_auto_adv = ELINK_FLOW_CTRL_BOTH;
6847         }
6848 }
6849
6850 static void bnx2x_calc_fc_adv(struct bnx2x_softc *sc)
6851 {
6852         uint8_t cfg_idx = bnx2x_get_link_cfg_idx(sc);
6853         switch (sc->link_vars.ieee_fc &
6854                 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_MASK) {
6855         case MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_NONE:
6856         default:
6857                 sc->port.advertising[cfg_idx] &= ~(ADVERTISED_Asym_Pause |
6858                                                    ADVERTISED_Pause);
6859                 break;
6860
6861         case MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH:
6862                 sc->port.advertising[cfg_idx] |= (ADVERTISED_Asym_Pause |
6863                                                   ADVERTISED_Pause);
6864                 break;
6865
6866         case MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC:
6867                 sc->port.advertising[cfg_idx] |= ADVERTISED_Asym_Pause;
6868                 break;
6869         }
6870 }
6871
6872 static uint16_t bnx2x_get_mf_speed(struct bnx2x_softc *sc)
6873 {
6874         uint16_t line_speed = sc->link_vars.line_speed;
6875         if (IS_MF(sc)) {
6876                 uint16_t maxCfg = bnx2x_extract_max_cfg(sc,
6877                                                       sc->devinfo.
6878                                                       mf_info.mf_config[SC_VN
6879                                                                         (sc)]);
6880
6881 /* calculate the current MAX line speed limit for the MF devices */
6882                 if (IS_MF_SI(sc)) {
6883                         line_speed = (line_speed * maxCfg) / 100;
6884                 } else {        /* SD mode */
6885                         uint16_t vn_max_rate = maxCfg * 100;
6886
6887                         if (vn_max_rate < line_speed) {
6888                                 line_speed = vn_max_rate;
6889                         }
6890                 }
6891         }
6892
6893         return line_speed;
6894 }
6895
6896 static void
6897 bnx2x_fill_report_data(struct bnx2x_softc *sc, struct bnx2x_link_report_data *data)
6898 {
6899         uint16_t line_speed = bnx2x_get_mf_speed(sc);
6900
6901         memset(data, 0, sizeof(*data));
6902
6903         /* fill the report data with the effective line speed */
6904         data->line_speed = line_speed;
6905
6906         /* Link is down */
6907         if (!sc->link_vars.link_up || (sc->flags & BNX2X_MF_FUNC_DIS)) {
6908                 bnx2x_set_bit(BNX2X_LINK_REPORT_LINK_DOWN,
6909                             &data->link_report_flags);
6910         }
6911
6912         /* Full DUPLEX */
6913         if (sc->link_vars.duplex == DUPLEX_FULL) {
6914                 bnx2x_set_bit(BNX2X_LINK_REPORT_FULL_DUPLEX,
6915                             &data->link_report_flags);
6916         }
6917
6918         /* Rx Flow Control is ON */
6919         if (sc->link_vars.flow_ctrl & ELINK_FLOW_CTRL_RX) {
6920                 bnx2x_set_bit(BNX2X_LINK_REPORT_RX_FC_ON, &data->link_report_flags);
6921         }
6922
6923         /* Tx Flow Control is ON */
6924         if (sc->link_vars.flow_ctrl & ELINK_FLOW_CTRL_TX) {
6925                 bnx2x_set_bit(BNX2X_LINK_REPORT_TX_FC_ON, &data->link_report_flags);
6926         }
6927 }
6928
6929 /* report link status to OS, should be called under phy_lock */
6930 static void bnx2x_link_report_locked(struct bnx2x_softc *sc)
6931 {
6932         struct bnx2x_link_report_data cur_data;
6933
6934         /* reread mf_cfg */
6935         if (IS_PF(sc)) {
6936                 bnx2x_read_mf_cfg(sc);
6937         }
6938
6939         /* Read the current link report info */
6940         bnx2x_fill_report_data(sc, &cur_data);
6941
6942         /* Don't report link down or exactly the same link status twice */
6943         if (!memcmp(&cur_data, &sc->last_reported_link, sizeof(cur_data)) ||
6944             (bnx2x_test_bit(BNX2X_LINK_REPORT_LINK_DOWN,
6945                           &sc->last_reported_link.link_report_flags) &&
6946              bnx2x_test_bit(BNX2X_LINK_REPORT_LINK_DOWN,
6947                           &cur_data.link_report_flags))) {
6948                 return;
6949         }
6950
6951         ELINK_DEBUG_P2(sc, "Change in link status : cur_data = %lx, last_reported_link = %lx",
6952                        cur_data.link_report_flags,
6953                        sc->last_reported_link.link_report_flags);
6954
6955         sc->link_cnt++;
6956
6957         ELINK_DEBUG_P1(sc, "link status change count = %x", sc->link_cnt);
6958         /* report new link params and remember the state for the next time */
6959         rte_memcpy(&sc->last_reported_link, &cur_data, sizeof(cur_data));
6960
6961         if (bnx2x_test_bit(BNX2X_LINK_REPORT_LINK_DOWN,
6962                          &cur_data.link_report_flags)) {
6963                 ELINK_DEBUG_P0(sc, "NIC Link is Down");
6964         } else {
6965                 __rte_unused const char *duplex;
6966                 __rte_unused const char *flow;
6967
6968                 if (bnx2x_test_and_clear_bit(BNX2X_LINK_REPORT_FULL_DUPLEX,
6969                                            &cur_data.link_report_flags)) {
6970                         duplex = "full";
6971                                 ELINK_DEBUG_P0(sc, "link set to full duplex");
6972                 } else {
6973                         duplex = "half";
6974                                 ELINK_DEBUG_P0(sc, "link set to half duplex");
6975                 }
6976
6977 /*
6978  * Handle the FC at the end so that only these flags would be
6979  * possibly set. This way we may easily check if there is no FC
6980  * enabled.
6981  */
6982                 if (cur_data.link_report_flags) {
6983                         if (bnx2x_test_bit(BNX2X_LINK_REPORT_RX_FC_ON,
6984                                          &cur_data.link_report_flags) &&
6985                             bnx2x_test_bit(BNX2X_LINK_REPORT_TX_FC_ON,
6986                                          &cur_data.link_report_flags)) {
6987                                 flow = "ON - receive & transmit";
6988                         } else if (bnx2x_test_bit(BNX2X_LINK_REPORT_RX_FC_ON,
6989                                                 &cur_data.link_report_flags) &&
6990                                    !bnx2x_test_bit(BNX2X_LINK_REPORT_TX_FC_ON,
6991                                                  &cur_data.link_report_flags)) {
6992                                 flow = "ON - receive";
6993                         } else if (!bnx2x_test_bit(BNX2X_LINK_REPORT_RX_FC_ON,
6994                                                  &cur_data.link_report_flags) &&
6995                                    bnx2x_test_bit(BNX2X_LINK_REPORT_TX_FC_ON,
6996                                                 &cur_data.link_report_flags)) {
6997                                 flow = "ON - transmit";
6998                         } else {
6999                                 flow = "none";  /* possible? */
7000                         }
7001                 } else {
7002                         flow = "none";
7003                 }
7004
7005                 PMD_DRV_LOG(INFO, sc,
7006                             "NIC Link is Up, %d Mbps %s duplex, Flow control: %s",
7007                             cur_data.line_speed, duplex, flow);
7008         }
7009 }
7010
7011 static void
7012 bnx2x_link_report(struct bnx2x_softc *sc)
7013 {
7014         bnx2x_acquire_phy_lock(sc);
7015         bnx2x_link_report_locked(sc);
7016         bnx2x_release_phy_lock(sc);
7017 }
7018
7019 void bnx2x_link_status_update(struct bnx2x_softc *sc)
7020 {
7021         if (sc->state != BNX2X_STATE_OPEN) {
7022                 return;
7023         }
7024
7025         if (IS_PF(sc) && !CHIP_REV_IS_SLOW(sc)) {
7026                 elink_link_status_update(&sc->link_params, &sc->link_vars);
7027         } else {
7028                 sc->port.supported[0] |= (ELINK_SUPPORTED_10baseT_Half |
7029                                           ELINK_SUPPORTED_10baseT_Full |
7030                                           ELINK_SUPPORTED_100baseT_Half |
7031                                           ELINK_SUPPORTED_100baseT_Full |
7032                                           ELINK_SUPPORTED_1000baseT_Full |
7033                                           ELINK_SUPPORTED_2500baseX_Full |
7034                                           ELINK_SUPPORTED_10000baseT_Full |
7035                                           ELINK_SUPPORTED_TP |
7036                                           ELINK_SUPPORTED_FIBRE |
7037                                           ELINK_SUPPORTED_Autoneg |
7038                                           ELINK_SUPPORTED_Pause |
7039                                           ELINK_SUPPORTED_Asym_Pause);
7040                 sc->port.advertising[0] = sc->port.supported[0];
7041
7042                 sc->link_params.sc = sc;
7043                 sc->link_params.port = SC_PORT(sc);
7044                 sc->link_params.req_duplex[0] = DUPLEX_FULL;
7045                 sc->link_params.req_flow_ctrl[0] = ELINK_FLOW_CTRL_NONE;
7046                 sc->link_params.req_line_speed[0] = SPEED_10000;
7047                 sc->link_params.speed_cap_mask[0] = 0x7f0000;
7048                 sc->link_params.switch_cfg = ELINK_SWITCH_CFG_10G;
7049
7050                 if (CHIP_REV_IS_FPGA(sc)) {
7051                         sc->link_vars.mac_type = ELINK_MAC_TYPE_EMAC;
7052                         sc->link_vars.line_speed = ELINK_SPEED_1000;
7053                         sc->link_vars.link_status = (LINK_STATUS_LINK_UP |
7054                                                      LINK_STATUS_SPEED_AND_DUPLEX_1000TFD);
7055                 } else {
7056                         sc->link_vars.mac_type = ELINK_MAC_TYPE_BMAC;
7057                         sc->link_vars.line_speed = ELINK_SPEED_10000;
7058                         sc->link_vars.link_status = (LINK_STATUS_LINK_UP |
7059                                                      LINK_STATUS_SPEED_AND_DUPLEX_10GTFD);
7060                 }
7061
7062                 sc->link_vars.link_up = 1;
7063
7064                 sc->link_vars.duplex = DUPLEX_FULL;
7065                 sc->link_vars.flow_ctrl = ELINK_FLOW_CTRL_NONE;
7066
7067                 if (IS_PF(sc)) {
7068                         REG_WR(sc,
7069                                NIG_REG_EGRESS_DRAIN0_MODE +
7070                                sc->link_params.port * 4, 0);
7071                         bnx2x_stats_handle(sc, STATS_EVENT_LINK_UP);
7072                         bnx2x_link_report(sc);
7073                 }
7074         }
7075
7076         if (IS_PF(sc)) {
7077                 if (sc->link_vars.link_up) {
7078                         bnx2x_stats_handle(sc, STATS_EVENT_LINK_UP);
7079                 } else {
7080                         bnx2x_stats_handle(sc, STATS_EVENT_STOP);
7081                 }
7082                 bnx2x_link_report(sc);
7083         } else {
7084                 bnx2x_link_report_locked(sc);
7085                 bnx2x_stats_handle(sc, STATS_EVENT_LINK_UP);
7086         }
7087 }
7088
7089 static int bnx2x_initial_phy_init(struct bnx2x_softc *sc, int load_mode)
7090 {
7091         int rc, cfg_idx = bnx2x_get_link_cfg_idx(sc);
7092         uint16_t req_line_speed = sc->link_params.req_line_speed[cfg_idx];
7093         struct elink_params *lp = &sc->link_params;
7094
7095         bnx2x_set_requested_fc(sc);
7096
7097         bnx2x_acquire_phy_lock(sc);
7098
7099         if (load_mode == LOAD_DIAG) {
7100                 lp->loopback_mode = ELINK_LOOPBACK_XGXS;
7101 /* Prefer doing PHY loopback at 10G speed, if possible */
7102                 if (lp->req_line_speed[cfg_idx] < ELINK_SPEED_10000) {
7103                         if (lp->speed_cap_mask[cfg_idx] &
7104                             PORT_HW_CFG_SPEED_CAPABILITY_D0_10G) {
7105                                 lp->req_line_speed[cfg_idx] = ELINK_SPEED_10000;
7106                         } else {
7107                                 lp->req_line_speed[cfg_idx] = ELINK_SPEED_1000;
7108                         }
7109                 }
7110         }
7111
7112         if (load_mode == LOAD_LOOPBACK_EXT) {
7113                 lp->loopback_mode = ELINK_LOOPBACK_EXT;
7114         }
7115
7116         rc = elink_phy_init(&sc->link_params, &sc->link_vars);
7117
7118         bnx2x_release_phy_lock(sc);
7119
7120         bnx2x_calc_fc_adv(sc);
7121
7122         if (sc->link_vars.link_up) {
7123                 bnx2x_stats_handle(sc, STATS_EVENT_LINK_UP);
7124                 bnx2x_link_report(sc);
7125         }
7126
7127         sc->link_params.req_line_speed[cfg_idx] = req_line_speed;
7128         return rc;
7129 }
7130
7131 /* update flags in shmem */
7132 static void
7133 bnx2x_update_drv_flags(struct bnx2x_softc *sc, uint32_t flags, uint32_t set)
7134 {
7135         uint32_t drv_flags;
7136
7137         if (SHMEM2_HAS(sc, drv_flags)) {
7138                 bnx2x_acquire_hw_lock(sc, HW_LOCK_RESOURCE_DRV_FLAGS);
7139                 drv_flags = SHMEM2_RD(sc, drv_flags);
7140
7141                 if (set) {
7142                         drv_flags |= flags;
7143                 } else {
7144                         drv_flags &= ~flags;
7145                 }
7146
7147                 SHMEM2_WR(sc, drv_flags, drv_flags);
7148
7149                 bnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_DRV_FLAGS);
7150         }
7151 }
7152
7153 /* periodic timer callout routine, only runs when the interface is up */
7154 void bnx2x_periodic_callout(struct bnx2x_softc *sc)
7155 {
7156         if ((sc->state != BNX2X_STATE_OPEN) ||
7157             (atomic_load_acq_long(&sc->periodic_flags) == PERIODIC_STOP)) {
7158                 PMD_DRV_LOG(DEBUG, sc, "periodic callout exit (state=0x%x)",
7159                             sc->state);
7160                 return;
7161         }
7162         if (!CHIP_REV_IS_SLOW(sc)) {
7163 /*
7164  * This barrier is needed to ensure the ordering between the writing
7165  * to the sc->port.pmf in the bnx2x_nic_load() or bnx2x_pmf_update() and
7166  * the reading here.
7167  */
7168                 mb();
7169                 if (sc->port.pmf) {
7170                         bnx2x_acquire_phy_lock(sc);
7171                         elink_period_func(&sc->link_params, &sc->link_vars);
7172                         bnx2x_release_phy_lock(sc);
7173                 }
7174         }
7175 #ifdef BNX2X_PULSE
7176         if (IS_PF(sc) && !BNX2X_NOMCP(sc)) {
7177                 int mb_idx = SC_FW_MB_IDX(sc);
7178                 uint32_t drv_pulse;
7179                 uint32_t mcp_pulse;
7180
7181                 ++sc->fw_drv_pulse_wr_seq;
7182                 sc->fw_drv_pulse_wr_seq &= DRV_PULSE_SEQ_MASK;
7183
7184                 drv_pulse = sc->fw_drv_pulse_wr_seq;
7185                 bnx2x_drv_pulse(sc);
7186
7187                 mcp_pulse = (SHMEM_RD(sc, func_mb[mb_idx].mcp_pulse_mb) &
7188                              MCP_PULSE_SEQ_MASK);
7189
7190 /*
7191  * The delta between driver pulse and mcp response should
7192  * be 1 (before mcp response) or 0 (after mcp response).
7193  */
7194                 if ((drv_pulse != mcp_pulse) &&
7195                     (drv_pulse != ((mcp_pulse + 1) & MCP_PULSE_SEQ_MASK))) {
7196                         /* someone lost a heartbeat... */
7197                         PMD_DRV_LOG(ERR, sc,
7198                                     "drv_pulse (0x%x) != mcp_pulse (0x%x)",
7199                                     drv_pulse, mcp_pulse);
7200                 }
7201         }
7202 #endif
7203 }
7204
7205 /* start the controller */
7206 static __rte_noinline
7207 int bnx2x_nic_load(struct bnx2x_softc *sc)
7208 {
7209         uint32_t val;
7210         uint32_t load_code = 0;
7211         int i, rc = 0;
7212
7213         PMD_INIT_FUNC_TRACE(sc);
7214
7215         sc->state = BNX2X_STATE_OPENING_WAITING_LOAD;
7216
7217         if (IS_PF(sc)) {
7218 /* must be called before memory allocation and HW init */
7219                 bnx2x_ilt_set_info(sc);
7220         }
7221
7222         bnx2x_set_fp_rx_buf_size(sc);
7223
7224         if (IS_PF(sc)) {
7225                 if (bnx2x_alloc_mem(sc) != 0) {
7226                         sc->state = BNX2X_STATE_CLOSED;
7227                         rc = -ENOMEM;
7228                         goto bnx2x_nic_load_error0;
7229                 }
7230         }
7231
7232         /* allocate the host hardware/software hsi structures */
7233         if (bnx2x_alloc_hsi_mem(sc) != 0) {
7234                 PMD_DRV_LOG(ERR, sc, "bnx2x_alloc_hsi_mem was failed");
7235                 sc->state = BNX2X_STATE_CLOSED;
7236                 rc = -ENOMEM;
7237                 goto bnx2x_nic_load_error0;
7238         }
7239
7240         if (bnx2x_alloc_fw_stats_mem(sc) != 0) {
7241                 sc->state = BNX2X_STATE_CLOSED;
7242                 rc = -ENOMEM;
7243                 goto bnx2x_nic_load_error0;
7244         }
7245
7246         if (IS_VF(sc)) {
7247                 rc = bnx2x_vf_init(sc);
7248                 if (rc) {
7249                         sc->state = BNX2X_STATE_ERROR;
7250                         goto bnx2x_nic_load_error0;
7251                 }
7252         }
7253
7254         if (IS_PF(sc)) {
7255 /* set pf load just before approaching the MCP */
7256                 bnx2x_set_pf_load(sc);
7257
7258 /* if MCP exists send load request and analyze response */
7259                 if (!BNX2X_NOMCP(sc)) {
7260                         /* attempt to load pf */
7261                         if (bnx2x_nic_load_request(sc, &load_code) != 0) {
7262                                 sc->state = BNX2X_STATE_CLOSED;
7263                                 rc = -ENXIO;
7264                                 goto bnx2x_nic_load_error1;
7265                         }
7266
7267                         /* what did the MCP say? */
7268                         if (bnx2x_nic_load_analyze_req(sc, load_code) != 0) {
7269                                 bnx2x_fw_command(sc, DRV_MSG_CODE_LOAD_DONE, 0);
7270                                 sc->state = BNX2X_STATE_CLOSED;
7271                                 rc = -ENXIO;
7272                                 goto bnx2x_nic_load_error2;
7273                         }
7274                 } else {
7275                         PMD_DRV_LOG(INFO, sc, "Device has no MCP!");
7276                         load_code = bnx2x_nic_load_no_mcp(sc);
7277                 }
7278
7279 /* mark PMF if applicable */
7280                 bnx2x_nic_load_pmf(sc, load_code);
7281
7282 /* Init Function state controlling object */
7283                 bnx2x_init_func_obj(sc);
7284
7285 /* Initialize HW */
7286                 if (bnx2x_init_hw(sc, load_code) != 0) {
7287                         PMD_DRV_LOG(NOTICE, sc, "HW init failed");
7288                         bnx2x_fw_command(sc, DRV_MSG_CODE_LOAD_DONE, 0);
7289                         sc->state = BNX2X_STATE_CLOSED;
7290                         rc = -ENXIO;
7291                         goto bnx2x_nic_load_error2;
7292                 }
7293         }
7294
7295         bnx2x_nic_init(sc, load_code);
7296
7297         /* Init per-function objects */
7298         if (IS_PF(sc)) {
7299                 bnx2x_init_objs(sc);
7300
7301 /* set AFEX default VLAN tag to an invalid value */
7302                 sc->devinfo.mf_info.afex_def_vlan_tag = -1;
7303
7304                 sc->state = BNX2X_STATE_OPENING_WAITING_PORT;
7305                 rc = bnx2x_func_start(sc);
7306                 if (rc) {
7307                         PMD_DRV_LOG(NOTICE, sc, "Function start failed!");
7308                         bnx2x_fw_command(sc, DRV_MSG_CODE_LOAD_DONE, 0);
7309                         sc->state = BNX2X_STATE_ERROR;
7310                         goto bnx2x_nic_load_error3;
7311                 }
7312
7313 /* send LOAD_DONE command to MCP */
7314                 if (!BNX2X_NOMCP(sc)) {
7315                         load_code =
7316                             bnx2x_fw_command(sc, DRV_MSG_CODE_LOAD_DONE, 0);
7317                         if (!load_code) {
7318                                 PMD_DRV_LOG(NOTICE, sc,
7319                                             "MCP response failure, aborting");
7320                                 sc->state = BNX2X_STATE_ERROR;
7321                                 rc = -ENXIO;
7322                                 goto bnx2x_nic_load_error3;
7323                         }
7324                 }
7325         }
7326
7327         rc = bnx2x_setup_leading(sc);
7328         if (rc) {
7329                 PMD_DRV_LOG(NOTICE, sc, "Setup leading failed!");
7330                 sc->state = BNX2X_STATE_ERROR;
7331                 goto bnx2x_nic_load_error3;
7332         }
7333
7334         FOR_EACH_NONDEFAULT_ETH_QUEUE(sc, i) {
7335                 if (IS_PF(sc))
7336                         rc = bnx2x_setup_queue(sc, &sc->fp[i], FALSE);
7337                 else            /* IS_VF(sc) */
7338                         rc = bnx2x_vf_setup_queue(sc, &sc->fp[i], FALSE);
7339
7340                 if (rc) {
7341                         PMD_DRV_LOG(NOTICE, sc, "Queue(%d) setup failed", i);
7342                         sc->state = BNX2X_STATE_ERROR;
7343                         goto bnx2x_nic_load_error3;
7344                 }
7345         }
7346
7347         rc = bnx2x_init_rss_pf(sc);
7348         if (rc) {
7349                 PMD_DRV_LOG(NOTICE, sc, "PF RSS init failed");
7350                 sc->state = BNX2X_STATE_ERROR;
7351                 goto bnx2x_nic_load_error3;
7352         }
7353
7354         /* now when Clients are configured we are ready to work */
7355         sc->state = BNX2X_STATE_OPEN;
7356
7357         /* Configure a ucast MAC */
7358         if (IS_PF(sc)) {
7359                 rc = bnx2x_set_eth_mac(sc, TRUE);
7360         } else {                /* IS_VF(sc) */
7361                 rc = bnx2x_vf_set_mac(sc, TRUE);
7362         }
7363
7364         if (rc) {
7365                 PMD_DRV_LOG(NOTICE, sc, "Setting Ethernet MAC failed");
7366                 sc->state = BNX2X_STATE_ERROR;
7367                 goto bnx2x_nic_load_error3;
7368         }
7369
7370         if (sc->port.pmf) {
7371                 rc = bnx2x_initial_phy_init(sc, LOAD_OPEN);
7372                 if (rc) {
7373                         sc->state = BNX2X_STATE_ERROR;
7374                         goto bnx2x_nic_load_error3;
7375                 }
7376         }
7377
7378         sc->link_params.feature_config_flags &=
7379             ~ELINK_FEATURE_CONFIG_BOOT_FROM_SAN;
7380
7381         /* start the Tx */
7382         switch (LOAD_OPEN) {
7383         case LOAD_NORMAL:
7384         case LOAD_OPEN:
7385                 break;
7386
7387         case LOAD_DIAG:
7388         case LOAD_LOOPBACK_EXT:
7389                 sc->state = BNX2X_STATE_DIAG;
7390                 break;
7391
7392         default:
7393                 break;
7394         }
7395
7396         if (sc->port.pmf) {
7397                 bnx2x_update_drv_flags(sc, 1 << DRV_FLAGS_PORT_MASK, 0);
7398         } else {
7399                 bnx2x_link_status_update(sc);
7400         }
7401
7402         if (IS_PF(sc) && SHMEM2_HAS(sc, drv_capabilities_flag)) {
7403 /* mark driver is loaded in shmem2 */
7404                 val = SHMEM2_RD(sc, drv_capabilities_flag[SC_FW_MB_IDX(sc)]);
7405                 SHMEM2_WR(sc, drv_capabilities_flag[SC_FW_MB_IDX(sc)],
7406                           (val |
7407                            DRV_FLAGS_CAPABILITIES_LOADED_SUPPORTED |
7408                            DRV_FLAGS_CAPABILITIES_LOADED_L2));
7409         }
7410
7411         /* start fast path */
7412         /* Initialize Rx filter */
7413         bnx2x_set_rx_mode(sc);
7414
7415         /* wait for all pending SP commands to complete */
7416         if (IS_PF(sc) && !bnx2x_wait_sp_comp(sc, ~0x0UL)) {
7417                 PMD_DRV_LOG(NOTICE, sc, "Timeout waiting for all SPs to complete!");
7418                 bnx2x_periodic_stop(sc);
7419                 bnx2x_nic_unload(sc, UNLOAD_CLOSE, FALSE);
7420                 return -ENXIO;
7421         }
7422
7423         PMD_DRV_LOG(DEBUG, sc, "NIC successfully loaded");
7424
7425         return 0;
7426
7427 bnx2x_nic_load_error3:
7428
7429         if (IS_PF(sc)) {
7430                 bnx2x_int_disable_sync(sc, 1);
7431
7432 /* clean out queued objects */
7433                 bnx2x_squeeze_objects(sc);
7434         }
7435
7436 bnx2x_nic_load_error2:
7437
7438         if (IS_PF(sc) && !BNX2X_NOMCP(sc)) {
7439                 bnx2x_fw_command(sc, DRV_MSG_CODE_UNLOAD_REQ_WOL_MCP, 0);
7440                 bnx2x_fw_command(sc, DRV_MSG_CODE_UNLOAD_DONE, 0);
7441         }
7442
7443         sc->port.pmf = 0;
7444
7445 bnx2x_nic_load_error1:
7446
7447         /* clear pf_load status, as it was already set */
7448         if (IS_PF(sc)) {
7449                 bnx2x_clear_pf_load(sc);
7450         }
7451
7452 bnx2x_nic_load_error0:
7453
7454         bnx2x_free_fw_stats_mem(sc);
7455         bnx2x_free_hsi_mem(sc);
7456         bnx2x_free_mem(sc);
7457
7458         return rc;
7459 }
7460
7461 /*
7462 * Handles controller initialization.
7463 */
7464 int bnx2x_init(struct bnx2x_softc *sc)
7465 {
7466         int other_engine = SC_PATH(sc) ? 0 : 1;
7467         uint8_t other_load_status, load_status;
7468         uint8_t global = FALSE;
7469         int rc;
7470
7471         /* Check if the driver is still running and bail out if it is. */
7472         if (sc->state != BNX2X_STATE_CLOSED) {
7473                 PMD_DRV_LOG(DEBUG, sc, "Init called while driver is running!");
7474                 rc = 0;
7475                 goto bnx2x_init_done;
7476         }
7477
7478         bnx2x_set_power_state(sc, PCI_PM_D0);
7479
7480         /*
7481          * If parity occurred during the unload, then attentions and/or
7482          * RECOVERY_IN_PROGRESS may still be set. If so we want the first function
7483          * loaded on the current engine to complete the recovery. Parity recovery
7484          * is only relevant for PF driver.
7485          */
7486         if (IS_PF(sc)) {
7487                 other_load_status = bnx2x_get_load_status(sc, other_engine);
7488                 load_status = bnx2x_get_load_status(sc, SC_PATH(sc));
7489
7490                 if (!bnx2x_reset_is_done(sc, SC_PATH(sc)) ||
7491                     bnx2x_chk_parity_attn(sc, &global, TRUE)) {
7492                         do {
7493                                 /*
7494                                  * If there are attentions and they are in global blocks, set
7495                                  * the GLOBAL_RESET bit regardless whether it will be this
7496                                  * function that will complete the recovery or not.
7497                                  */
7498                                 if (global) {
7499                                         bnx2x_set_reset_global(sc);
7500                                 }
7501
7502                                 /*
7503                                  * Only the first function on the current engine should try
7504                                  * to recover in open. In case of attentions in global blocks
7505                                  * only the first in the chip should try to recover.
7506                                  */
7507                                 if ((!load_status
7508                                      && (!global ||!other_load_status))
7509                                     && bnx2x_trylock_leader_lock(sc)
7510                                     && !bnx2x_leader_reset(sc)) {
7511                                         PMD_DRV_LOG(INFO, sc,
7512                                                     "Recovered during init");
7513                                         break;
7514                                 }
7515
7516                                 /* recovery has failed... */
7517                                 bnx2x_set_power_state(sc, PCI_PM_D3hot);
7518
7519                                 sc->recovery_state = BNX2X_RECOVERY_FAILED;
7520
7521                                 PMD_DRV_LOG(NOTICE, sc,
7522                                             "Recovery flow hasn't properly "
7523                                             "completed yet, try again later. "
7524                                             "If you still see this message after a "
7525                                             "few retries then power cycle is required.");
7526
7527                                 rc = -ENXIO;
7528                                 goto bnx2x_init_done;
7529                         } while (0);
7530                 }
7531         }
7532
7533         sc->recovery_state = BNX2X_RECOVERY_DONE;
7534
7535         rc = bnx2x_nic_load(sc);
7536
7537 bnx2x_init_done:
7538
7539         if (rc) {
7540                 PMD_DRV_LOG(NOTICE, sc, "Initialization failed, "
7541                             "stack notified driver is NOT running!");
7542         }
7543
7544         return rc;
7545 }
7546
7547 static void bnx2x_get_function_num(struct bnx2x_softc *sc)
7548 {
7549         uint32_t val = 0;
7550
7551         /*
7552          * Read the ME register to get the function number. The ME register
7553          * holds the relative-function number and absolute-function number. The
7554          * absolute-function number appears only in E2 and above. Before that
7555          * these bits always contained zero, therefore we cannot blindly use them.
7556          */
7557
7558         val = REG_RD(sc, BAR_ME_REGISTER);
7559
7560         sc->pfunc_rel =
7561             (uint8_t) ((val & ME_REG_PF_NUM) >> ME_REG_PF_NUM_SHIFT);
7562         sc->path_id =
7563             (uint8_t) ((val & ME_REG_ABS_PF_NUM) >> ME_REG_ABS_PF_NUM_SHIFT) &
7564             1;
7565
7566         if (CHIP_PORT_MODE(sc) == CHIP_4_PORT_MODE) {
7567                 sc->pfunc_abs = ((sc->pfunc_rel << 1) | sc->path_id);
7568         } else {
7569                 sc->pfunc_abs = (sc->pfunc_rel | sc->path_id);
7570         }
7571
7572         PMD_DRV_LOG(DEBUG, sc,
7573                     "Relative function %d, Absolute function %d, Path %d",
7574                     sc->pfunc_rel, sc->pfunc_abs, sc->path_id);
7575 }
7576
7577 static uint32_t bnx2x_get_shmem_mf_cfg_base(struct bnx2x_softc *sc)
7578 {
7579         uint32_t shmem2_size;
7580         uint32_t offset;
7581         uint32_t mf_cfg_offset_value;
7582
7583         /* Non 57712 */
7584         offset = (SHMEM_ADDR(sc, func_mb) +
7585                   (MAX_FUNC_NUM * sizeof(struct drv_func_mb)));
7586
7587         /* 57712 plus */
7588         if (sc->devinfo.shmem2_base != 0) {
7589                 shmem2_size = SHMEM2_RD(sc, size);
7590                 if (shmem2_size > offsetof(struct shmem2_region, mf_cfg_addr)) {
7591                         mf_cfg_offset_value = SHMEM2_RD(sc, mf_cfg_addr);
7592                         if (SHMEM_MF_CFG_ADDR_NONE != mf_cfg_offset_value) {
7593                                 offset = mf_cfg_offset_value;
7594                         }
7595                 }
7596         }
7597
7598         return offset;
7599 }
7600
7601 static uint32_t bnx2x_pcie_capability_read(struct bnx2x_softc *sc, int reg)
7602 {
7603         uint32_t ret;
7604         struct bnx2x_pci_cap *caps;
7605
7606         /* ensure PCIe capability is enabled */
7607         caps = pci_find_cap(sc, PCIY_EXPRESS, BNX2X_PCI_CAP);
7608         if (NULL != caps) {
7609                 PMD_DRV_LOG(DEBUG, sc, "Found PCIe capability: "
7610                             "id=0x%04X type=0x%04X addr=0x%08X",
7611                             caps->id, caps->type, caps->addr);
7612                 pci_read(sc, (caps->addr + reg), &ret, 2);
7613                 return ret;
7614         }
7615
7616         PMD_DRV_LOG(WARNING, sc, "PCIe capability NOT FOUND!!!");
7617
7618         return 0;
7619 }
7620
7621 static uint8_t bnx2x_is_pcie_pending(struct bnx2x_softc *sc)
7622 {
7623         return bnx2x_pcie_capability_read(sc, PCIR_EXPRESS_DEVICE_STA) &
7624                 PCIM_EXP_STA_TRANSACTION_PND;
7625 }
7626
7627 /*
7628 * Walk the PCI capabiites list for the device to find what features are
7629 * supported. These capabilites may be enabled/disabled by firmware so it's
7630 * best to walk the list rather than make assumptions.
7631 */
7632 static void bnx2x_probe_pci_caps(struct bnx2x_softc *sc)
7633 {
7634         PMD_INIT_FUNC_TRACE(sc);
7635
7636         struct bnx2x_pci_cap *caps;
7637         uint16_t link_status;
7638         int reg = 0;
7639
7640         /* check if PCI Power Management is enabled */
7641         caps = pci_find_cap(sc, PCIY_PMG, BNX2X_PCI_CAP);
7642         if (NULL != caps) {
7643                 PMD_DRV_LOG(DEBUG, sc, "Found PM capability: "
7644                             "id=0x%04X type=0x%04X addr=0x%08X",
7645                             caps->id, caps->type, caps->addr);
7646
7647                 sc->devinfo.pcie_cap_flags |= BNX2X_PM_CAPABLE_FLAG;
7648                 sc->devinfo.pcie_pm_cap_reg = caps->addr;
7649         }
7650
7651         link_status = bnx2x_pcie_capability_read(sc, PCIR_EXPRESS_LINK_STA);
7652
7653         sc->devinfo.pcie_link_speed = (link_status & PCIM_LINK_STA_SPEED);
7654         sc->devinfo.pcie_link_width =
7655             ((link_status & PCIM_LINK_STA_WIDTH) >> 4);
7656
7657         PMD_DRV_LOG(DEBUG, sc, "PCIe link speed=%d width=%d",
7658                     sc->devinfo.pcie_link_speed, sc->devinfo.pcie_link_width);
7659
7660         sc->devinfo.pcie_cap_flags |= BNX2X_PCIE_CAPABLE_FLAG;
7661
7662         /* check if MSI capability is enabled */
7663         caps = pci_find_cap(sc, PCIY_MSI, BNX2X_PCI_CAP);
7664         if (NULL != caps) {
7665                 PMD_DRV_LOG(DEBUG, sc, "Found MSI capability at 0x%04x", reg);
7666
7667                 sc->devinfo.pcie_cap_flags |= BNX2X_MSI_CAPABLE_FLAG;
7668                 sc->devinfo.pcie_msi_cap_reg = caps->addr;
7669         }
7670
7671         /* check if MSI-X capability is enabled */
7672         caps = pci_find_cap(sc, PCIY_MSIX, BNX2X_PCI_CAP);
7673         if (NULL != caps) {
7674                 PMD_DRV_LOG(DEBUG, sc, "Found MSI-X capability at 0x%04x", reg);
7675
7676                 sc->devinfo.pcie_cap_flags |= BNX2X_MSIX_CAPABLE_FLAG;
7677                 sc->devinfo.pcie_msix_cap_reg = caps->addr;
7678         }
7679 }
7680
7681 static int bnx2x_get_shmem_mf_cfg_info_sd(struct bnx2x_softc *sc)
7682 {
7683         struct bnx2x_mf_info *mf_info = &sc->devinfo.mf_info;
7684         uint32_t val;
7685
7686         /* get the outer vlan if we're in switch-dependent mode */
7687
7688         val = MFCFG_RD(sc, func_mf_config[SC_ABS_FUNC(sc)].e1hov_tag);
7689         mf_info->ext_id = (uint16_t) val;
7690
7691         mf_info->multi_vnics_mode = 1;
7692
7693         if (!VALID_OVLAN(mf_info->ext_id)) {
7694                 PMD_DRV_LOG(NOTICE, sc, "Invalid VLAN (%d)", mf_info->ext_id);
7695                 return 1;
7696         }
7697
7698         /* get the capabilities */
7699         if ((mf_info->mf_config[SC_VN(sc)] & FUNC_MF_CFG_PROTOCOL_MASK) ==
7700             FUNC_MF_CFG_PROTOCOL_ISCSI) {
7701                 mf_info->mf_protos_supported |= MF_PROTO_SUPPORT_ISCSI;
7702         } else if ((mf_info->mf_config[SC_VN(sc)] & FUNC_MF_CFG_PROTOCOL_MASK)
7703                    == FUNC_MF_CFG_PROTOCOL_FCOE) {
7704                 mf_info->mf_protos_supported |= MF_PROTO_SUPPORT_FCOE;
7705         } else {
7706                 mf_info->mf_protos_supported |= MF_PROTO_SUPPORT_ETHERNET;
7707         }
7708
7709         mf_info->vnics_per_port =
7710             (CHIP_PORT_MODE(sc) == CHIP_4_PORT_MODE) ? 2 : 4;
7711
7712         return 0;
7713 }
7714
7715 static uint32_t bnx2x_get_shmem_ext_proto_support_flags(struct bnx2x_softc *sc)
7716 {
7717         uint32_t retval = 0;
7718         uint32_t val;
7719
7720         val = MFCFG_RD(sc, func_ext_config[SC_ABS_FUNC(sc)].func_cfg);
7721
7722         if (val & MACP_FUNC_CFG_FLAGS_ENABLED) {
7723                 if (val & MACP_FUNC_CFG_FLAGS_ETHERNET) {
7724                         retval |= MF_PROTO_SUPPORT_ETHERNET;
7725                 }
7726                 if (val & MACP_FUNC_CFG_FLAGS_ISCSI_OFFLOAD) {
7727                         retval |= MF_PROTO_SUPPORT_ISCSI;
7728                 }
7729                 if (val & MACP_FUNC_CFG_FLAGS_FCOE_OFFLOAD) {
7730                         retval |= MF_PROTO_SUPPORT_FCOE;
7731                 }
7732         }
7733
7734         return retval;
7735 }
7736
7737 static int bnx2x_get_shmem_mf_cfg_info_si(struct bnx2x_softc *sc)
7738 {
7739         struct bnx2x_mf_info *mf_info = &sc->devinfo.mf_info;
7740         uint32_t val;
7741
7742         /*
7743          * There is no outer vlan if we're in switch-independent mode.
7744          * If the mac is valid then assume multi-function.
7745          */
7746
7747         val = MFCFG_RD(sc, func_ext_config[SC_ABS_FUNC(sc)].func_cfg);
7748
7749         mf_info->multi_vnics_mode = ((val & MACP_FUNC_CFG_FLAGS_MASK) != 0);
7750
7751         mf_info->mf_protos_supported =
7752             bnx2x_get_shmem_ext_proto_support_flags(sc);
7753
7754         mf_info->vnics_per_port =
7755             (CHIP_PORT_MODE(sc) == CHIP_4_PORT_MODE) ? 2 : 4;
7756
7757         return 0;
7758 }
7759
7760 static int bnx2x_get_shmem_mf_cfg_info_niv(struct bnx2x_softc *sc)
7761 {
7762         struct bnx2x_mf_info *mf_info = &sc->devinfo.mf_info;
7763         uint32_t e1hov_tag;
7764         uint32_t func_config;
7765         uint32_t niv_config;
7766
7767         mf_info->multi_vnics_mode = 1;
7768
7769         e1hov_tag = MFCFG_RD(sc, func_mf_config[SC_ABS_FUNC(sc)].e1hov_tag);
7770         func_config = MFCFG_RD(sc, func_mf_config[SC_ABS_FUNC(sc)].config);
7771         niv_config = MFCFG_RD(sc, func_mf_config[SC_ABS_FUNC(sc)].afex_config);
7772
7773         mf_info->ext_id =
7774             (uint16_t) ((e1hov_tag & FUNC_MF_CFG_E1HOV_TAG_MASK) >>
7775                         FUNC_MF_CFG_E1HOV_TAG_SHIFT);
7776
7777         mf_info->default_vlan =
7778             (uint16_t) ((e1hov_tag & FUNC_MF_CFG_AFEX_VLAN_MASK) >>
7779                         FUNC_MF_CFG_AFEX_VLAN_SHIFT);
7780
7781         mf_info->niv_allowed_priorities =
7782             (uint8_t) ((niv_config & FUNC_MF_CFG_AFEX_COS_FILTER_MASK) >>
7783                        FUNC_MF_CFG_AFEX_COS_FILTER_SHIFT);
7784
7785         mf_info->niv_default_cos =
7786             (uint8_t) ((func_config & FUNC_MF_CFG_TRANSMIT_PRIORITY_MASK) >>
7787                        FUNC_MF_CFG_TRANSMIT_PRIORITY_SHIFT);
7788
7789         mf_info->afex_vlan_mode =
7790             ((niv_config & FUNC_MF_CFG_AFEX_VLAN_MODE_MASK) >>
7791              FUNC_MF_CFG_AFEX_VLAN_MODE_SHIFT);
7792
7793         mf_info->niv_mba_enabled =
7794             ((niv_config & FUNC_MF_CFG_AFEX_MBA_ENABLED_MASK) >>
7795              FUNC_MF_CFG_AFEX_MBA_ENABLED_SHIFT);
7796
7797         mf_info->mf_protos_supported =
7798             bnx2x_get_shmem_ext_proto_support_flags(sc);
7799
7800         mf_info->vnics_per_port =
7801             (CHIP_PORT_MODE(sc) == CHIP_4_PORT_MODE) ? 2 : 4;
7802
7803         return 0;
7804 }
7805
7806 static int bnx2x_check_valid_mf_cfg(struct bnx2x_softc *sc)
7807 {
7808         struct bnx2x_mf_info *mf_info = &sc->devinfo.mf_info;
7809         uint32_t mf_cfg1;
7810         uint32_t mf_cfg2;
7811         uint32_t ovlan1;
7812         uint32_t ovlan2;
7813         uint8_t i, j;
7814
7815         /* various MF mode sanity checks... */
7816
7817         if (mf_info->mf_config[SC_VN(sc)] & FUNC_MF_CFG_FUNC_HIDE) {
7818                 PMD_DRV_LOG(NOTICE, sc,
7819                             "Enumerated function %d is marked as hidden",
7820                             SC_PORT(sc));
7821                 return 1;
7822         }
7823
7824         if ((mf_info->vnics_per_port > 1) && !mf_info->multi_vnics_mode) {
7825                 PMD_DRV_LOG(NOTICE, sc, "vnics_per_port=%d multi_vnics_mode=%d",
7826                             mf_info->vnics_per_port, mf_info->multi_vnics_mode);
7827                 return 1;
7828         }
7829
7830         if (mf_info->mf_mode == MULTI_FUNCTION_SD) {
7831 /* vnic id > 0 must have valid ovlan in switch-dependent mode */
7832                 if ((SC_VN(sc) > 0) && !VALID_OVLAN(OVLAN(sc))) {
7833                         PMD_DRV_LOG(NOTICE, sc, "mf_mode=SD vnic_id=%d ovlan=%d",
7834                                     SC_VN(sc), OVLAN(sc));
7835                         return 1;
7836                 }
7837
7838                 if (!VALID_OVLAN(OVLAN(sc)) && mf_info->multi_vnics_mode) {
7839                         PMD_DRV_LOG(NOTICE, sc,
7840                                     "mf_mode=SD multi_vnics_mode=%d ovlan=%d",
7841                                     mf_info->multi_vnics_mode, OVLAN(sc));
7842                         return 1;
7843                 }
7844
7845 /*
7846  * Verify all functions are either MF or SF mode. If MF, make sure
7847  * sure that all non-hidden functions have a valid ovlan. If SF,
7848  * make sure that all non-hidden functions have an invalid ovlan.
7849  */
7850                 FOREACH_ABS_FUNC_IN_PORT(sc, i) {
7851                         mf_cfg1 = MFCFG_RD(sc, func_mf_config[i].config);
7852                         ovlan1 = MFCFG_RD(sc, func_mf_config[i].e1hov_tag);
7853                         if (!(mf_cfg1 & FUNC_MF_CFG_FUNC_HIDE) &&
7854                             (((mf_info->multi_vnics_mode)
7855                               && !VALID_OVLAN(ovlan1))
7856                              || ((!mf_info->multi_vnics_mode)
7857                                  && VALID_OVLAN(ovlan1)))) {
7858                                 PMD_DRV_LOG(NOTICE, sc,
7859                                             "mf_mode=SD function %d MF config "
7860                                             "mismatch, multi_vnics_mode=%d ovlan=%d",
7861                                             i, mf_info->multi_vnics_mode,
7862                                             ovlan1);
7863                                 return 1;
7864                         }
7865                 }
7866
7867 /* Verify all funcs on the same port each have a different ovlan. */
7868                 FOREACH_ABS_FUNC_IN_PORT(sc, i) {
7869                         mf_cfg1 = MFCFG_RD(sc, func_mf_config[i].config);
7870                         ovlan1 = MFCFG_RD(sc, func_mf_config[i].e1hov_tag);
7871                         /* iterate from the next function on the port to the max func */
7872                         for (j = i + 2; j < MAX_FUNC_NUM; j += 2) {
7873                                 mf_cfg2 =
7874                                     MFCFG_RD(sc, func_mf_config[j].config);
7875                                 ovlan2 =
7876                                     MFCFG_RD(sc, func_mf_config[j].e1hov_tag);
7877                                 if (!(mf_cfg1 & FUNC_MF_CFG_FUNC_HIDE)
7878                                     && VALID_OVLAN(ovlan1)
7879                                     && !(mf_cfg2 & FUNC_MF_CFG_FUNC_HIDE)
7880                                     && VALID_OVLAN(ovlan2)
7881                                     && (ovlan1 == ovlan2)) {
7882                                         PMD_DRV_LOG(NOTICE, sc,
7883                                                     "mf_mode=SD functions %d and %d "
7884                                                     "have the same ovlan (%d)",
7885                                                     i, j, ovlan1);
7886                                         return 1;
7887                                 }
7888                         }
7889                 }
7890         }
7891         /* MULTI_FUNCTION_SD */
7892         return 0;
7893 }
7894
7895 static int bnx2x_get_mf_cfg_info(struct bnx2x_softc *sc)
7896 {
7897         struct bnx2x_mf_info *mf_info = &sc->devinfo.mf_info;
7898         uint32_t val, mac_upper;
7899         uint8_t i, vnic;
7900
7901         /* initialize mf_info defaults */
7902         mf_info->vnics_per_port = 1;
7903         mf_info->multi_vnics_mode = FALSE;
7904         mf_info->path_has_ovlan = FALSE;
7905         mf_info->mf_mode = SINGLE_FUNCTION;
7906
7907         if (!CHIP_IS_MF_CAP(sc)) {
7908                 return 0;
7909         }
7910
7911         if (sc->devinfo.mf_cfg_base == SHMEM_MF_CFG_ADDR_NONE) {
7912                 PMD_DRV_LOG(NOTICE, sc, "Invalid mf_cfg_base!");
7913                 return 1;
7914         }
7915
7916         /* get the MF mode (switch dependent / independent / single-function) */
7917
7918         val = SHMEM_RD(sc, dev_info.shared_feature_config.config);
7919
7920         switch (val & SHARED_FEAT_CFG_FORCE_SF_MODE_MASK) {
7921         case SHARED_FEAT_CFG_FORCE_SF_MODE_SWITCH_INDEPT:
7922
7923                 mac_upper =
7924                     MFCFG_RD(sc, func_mf_config[SC_ABS_FUNC(sc)].mac_upper);
7925
7926                 /* check for legal upper mac bytes */
7927                 if (mac_upper != FUNC_MF_CFG_UPPERMAC_DEFAULT) {
7928                         mf_info->mf_mode = MULTI_FUNCTION_SI;
7929                 } else {
7930                         PMD_DRV_LOG(NOTICE, sc,
7931                                     "Invalid config for Switch Independent mode");
7932                 }
7933
7934                 break;
7935
7936         case SHARED_FEAT_CFG_FORCE_SF_MODE_MF_ALLOWED:
7937         case SHARED_FEAT_CFG_FORCE_SF_MODE_SPIO4:
7938
7939                 /* get outer vlan configuration */
7940                 val = MFCFG_RD(sc, func_mf_config[SC_ABS_FUNC(sc)].e1hov_tag);
7941
7942                 if ((val & FUNC_MF_CFG_E1HOV_TAG_MASK) !=
7943                     FUNC_MF_CFG_E1HOV_TAG_DEFAULT) {
7944                         mf_info->mf_mode = MULTI_FUNCTION_SD;
7945                 } else {
7946                         PMD_DRV_LOG(NOTICE, sc,
7947                                     "Invalid config for Switch Dependent mode");
7948                 }
7949
7950                 break;
7951
7952         case SHARED_FEAT_CFG_FORCE_SF_MODE_FORCED_SF:
7953
7954                 /* not in MF mode, vnics_per_port=1 and multi_vnics_mode=FALSE */
7955                 return 0;
7956
7957         case SHARED_FEAT_CFG_FORCE_SF_MODE_AFEX_MODE:
7958
7959                 /*
7960                  * Mark MF mode as NIV if MCP version includes NPAR-SD support
7961                  * and the MAC address is valid.
7962                  */
7963                 mac_upper =
7964                     MFCFG_RD(sc, func_mf_config[SC_ABS_FUNC(sc)].mac_upper);
7965
7966                 if ((SHMEM2_HAS(sc, afex_driver_support)) &&
7967                     (mac_upper != FUNC_MF_CFG_UPPERMAC_DEFAULT)) {
7968                         mf_info->mf_mode = MULTI_FUNCTION_AFEX;
7969                 } else {
7970                         PMD_DRV_LOG(NOTICE, sc, "Invalid config for AFEX mode");
7971                 }
7972
7973                 break;
7974
7975         default:
7976
7977                 PMD_DRV_LOG(NOTICE, sc, "Unknown MF mode (0x%08x)",
7978                             (val & SHARED_FEAT_CFG_FORCE_SF_MODE_MASK));
7979
7980                 return 1;
7981         }
7982
7983         /* set path mf_mode (which could be different than function mf_mode) */
7984         if (mf_info->mf_mode == MULTI_FUNCTION_SD) {
7985                 mf_info->path_has_ovlan = TRUE;
7986         } else if (mf_info->mf_mode == SINGLE_FUNCTION) {
7987 /*
7988  * Decide on path multi vnics mode. If we're not in MF mode and in
7989  * 4-port mode, this is good enough to check vnic-0 of the other port
7990  * on the same path
7991  */
7992                 if (CHIP_PORT_MODE(sc) == CHIP_4_PORT_MODE) {
7993                         uint8_t other_port = !(PORT_ID(sc) & 1);
7994                         uint8_t abs_func_other_port =
7995                             (SC_PATH(sc) + (2 * other_port));
7996
7997                         val =
7998                             MFCFG_RD(sc,
7999                                      func_mf_config
8000                                      [abs_func_other_port].e1hov_tag);
8001
8002                         mf_info->path_has_ovlan = VALID_OVLAN((uint16_t) val);
8003                 }
8004         }
8005
8006         if (mf_info->mf_mode == SINGLE_FUNCTION) {
8007 /* invalid MF config */
8008                 if (SC_VN(sc) >= 1) {
8009                         PMD_DRV_LOG(NOTICE, sc, "VNIC ID >= 1 in SF mode");
8010                         return 1;
8011                 }
8012
8013                 return 0;
8014         }
8015
8016         /* get the MF configuration */
8017         mf_info->mf_config[SC_VN(sc)] =
8018             MFCFG_RD(sc, func_mf_config[SC_ABS_FUNC(sc)].config);
8019
8020         switch (mf_info->mf_mode) {
8021         case MULTI_FUNCTION_SD:
8022
8023                 bnx2x_get_shmem_mf_cfg_info_sd(sc);
8024                 break;
8025
8026         case MULTI_FUNCTION_SI:
8027
8028                 bnx2x_get_shmem_mf_cfg_info_si(sc);
8029                 break;
8030
8031         case MULTI_FUNCTION_AFEX:
8032
8033                 bnx2x_get_shmem_mf_cfg_info_niv(sc);
8034                 break;
8035
8036         default:
8037
8038                 PMD_DRV_LOG(NOTICE, sc, "Get MF config failed (mf_mode=0x%08x)",
8039                             mf_info->mf_mode);
8040                 return 1;
8041         }
8042
8043         /* get the congestion management parameters */
8044
8045         vnic = 0;
8046         FOREACH_ABS_FUNC_IN_PORT(sc, i) {
8047 /* get min/max bw */
8048                 val = MFCFG_RD(sc, func_mf_config[i].config);
8049                 mf_info->min_bw[vnic] =
8050                     ((val & FUNC_MF_CFG_MIN_BW_MASK) >>
8051                      FUNC_MF_CFG_MIN_BW_SHIFT);
8052                 mf_info->max_bw[vnic] =
8053                     ((val & FUNC_MF_CFG_MAX_BW_MASK) >>
8054                      FUNC_MF_CFG_MAX_BW_SHIFT);
8055                 vnic++;
8056         }
8057
8058         return bnx2x_check_valid_mf_cfg(sc);
8059 }
8060
8061 static int bnx2x_get_shmem_info(struct bnx2x_softc *sc)
8062 {
8063         int port;
8064         uint32_t mac_hi, mac_lo, val;
8065
8066         PMD_INIT_FUNC_TRACE(sc);
8067
8068         port = SC_PORT(sc);
8069         mac_hi = mac_lo = 0;
8070
8071         sc->link_params.sc = sc;
8072         sc->link_params.port = port;
8073
8074         /* get the hardware config info */
8075         sc->devinfo.hw_config = SHMEM_RD(sc, dev_info.shared_hw_config.config);
8076         sc->devinfo.hw_config2 =
8077             SHMEM_RD(sc, dev_info.shared_hw_config.config2);
8078
8079         sc->link_params.hw_led_mode =
8080             ((sc->devinfo.hw_config & SHARED_HW_CFG_LED_MODE_MASK) >>
8081              SHARED_HW_CFG_LED_MODE_SHIFT);
8082
8083         /* get the port feature config */
8084         sc->port.config =
8085             SHMEM_RD(sc, dev_info.port_feature_config[port].config);
8086
8087         /* get the link params */
8088         sc->link_params.speed_cap_mask[ELINK_INT_PHY] =
8089             SHMEM_RD(sc, dev_info.port_hw_config[port].speed_capability_mask)
8090             & PORT_HW_CFG_SPEED_CAPABILITY_D0_MASK;
8091         sc->link_params.speed_cap_mask[ELINK_EXT_PHY1] =
8092             SHMEM_RD(sc, dev_info.port_hw_config[port].speed_capability_mask2)
8093             & PORT_HW_CFG_SPEED_CAPABILITY_D0_MASK;
8094
8095         /* get the lane config */
8096         sc->link_params.lane_config =
8097             SHMEM_RD(sc, dev_info.port_hw_config[port].lane_config);
8098
8099         /* get the link config */
8100         val = SHMEM_RD(sc, dev_info.port_feature_config[port].link_config);
8101         sc->port.link_config[ELINK_INT_PHY] = val;
8102         sc->link_params.switch_cfg = (val & PORT_FEATURE_CONNECTED_SWITCH_MASK);
8103         sc->port.link_config[ELINK_EXT_PHY1] =
8104             SHMEM_RD(sc, dev_info.port_feature_config[port].link_config2);
8105
8106         /* get the override preemphasis flag and enable it or turn it off */
8107         val = SHMEM_RD(sc, dev_info.shared_feature_config.config);
8108         if (val & SHARED_FEAT_CFG_OVERRIDE_PREEMPHASIS_CFG_ENABLED) {
8109                 sc->link_params.feature_config_flags |=
8110                     ELINK_FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED;
8111         } else {
8112                 sc->link_params.feature_config_flags &=
8113                     ~ELINK_FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED;
8114         }
8115
8116         val = sc->devinfo.bc_ver >> 8;
8117         if (val < BNX2X_BC_VER) {
8118                 /* for now only warn later we might need to enforce this */
8119                 PMD_DRV_LOG(NOTICE, sc, "This driver needs bc_ver %X but found %X, please upgrade BC\n",
8120                             BNX2X_BC_VER, val);
8121         }
8122         sc->link_params.feature_config_flags |=
8123                                 (val >= REQ_BC_VER_4_VRFY_FIRST_PHY_OPT_MDL) ?
8124                                 ELINK_FEATURE_CONFIG_BC_SUPPORTS_OPT_MDL_VRFY :
8125                                 0;
8126
8127         sc->link_params.feature_config_flags |=
8128                 (val >= REQ_BC_VER_4_VRFY_SPECIFIC_PHY_OPT_MDL) ?
8129                 ELINK_FEATURE_CONFIG_BC_SUPPORTS_DUAL_PHY_OPT_MDL_VRFY : 0;
8130         sc->link_params.feature_config_flags |=
8131                 (val >= REQ_BC_VER_4_VRFY_AFEX_SUPPORTED) ?
8132                 ELINK_FEATURE_CONFIG_BC_SUPPORTS_AFEX : 0;
8133         sc->link_params.feature_config_flags |=
8134                 (val >= REQ_BC_VER_4_SFP_TX_DISABLE_SUPPORTED) ?
8135                 ELINK_FEATURE_CONFIG_BC_SUPPORTS_SFP_TX_DISABLED : 0;
8136
8137         /* get the initial value of the link params */
8138         sc->link_params.multi_phy_config =
8139             SHMEM_RD(sc, dev_info.port_hw_config[port].multi_phy_config);
8140
8141         /* get external phy info */
8142         sc->port.ext_phy_config =
8143             SHMEM_RD(sc, dev_info.port_hw_config[port].external_phy_config);
8144
8145         /* get the multifunction configuration */
8146         bnx2x_get_mf_cfg_info(sc);
8147
8148         /* get the mac address */
8149         if (IS_MF(sc)) {
8150                 mac_hi =
8151                     MFCFG_RD(sc, func_mf_config[SC_ABS_FUNC(sc)].mac_upper);
8152                 mac_lo =
8153                     MFCFG_RD(sc, func_mf_config[SC_ABS_FUNC(sc)].mac_lower);
8154         } else {
8155                 mac_hi = SHMEM_RD(sc, dev_info.port_hw_config[port].mac_upper);
8156                 mac_lo = SHMEM_RD(sc, dev_info.port_hw_config[port].mac_lower);
8157         }
8158
8159         if ((mac_lo == 0) && (mac_hi == 0)) {
8160                 *sc->mac_addr_str = 0;
8161                 PMD_DRV_LOG(NOTICE, sc, "No Ethernet address programmed!");
8162         } else {
8163                 sc->link_params.mac_addr[0] = (uint8_t) (mac_hi >> 8);
8164                 sc->link_params.mac_addr[1] = (uint8_t) (mac_hi);
8165                 sc->link_params.mac_addr[2] = (uint8_t) (mac_lo >> 24);
8166                 sc->link_params.mac_addr[3] = (uint8_t) (mac_lo >> 16);
8167                 sc->link_params.mac_addr[4] = (uint8_t) (mac_lo >> 8);
8168                 sc->link_params.mac_addr[5] = (uint8_t) (mac_lo);
8169                 snprintf(sc->mac_addr_str, sizeof(sc->mac_addr_str),
8170                          "%02x:%02x:%02x:%02x:%02x:%02x",
8171                          sc->link_params.mac_addr[0],
8172                          sc->link_params.mac_addr[1],
8173                          sc->link_params.mac_addr[2],
8174                          sc->link_params.mac_addr[3],
8175                          sc->link_params.mac_addr[4],
8176                          sc->link_params.mac_addr[5]);
8177                 PMD_DRV_LOG(DEBUG, sc,
8178                             "Ethernet address: %s", sc->mac_addr_str);
8179         }
8180
8181         return 0;
8182 }
8183
8184 static void bnx2x_media_detect(struct bnx2x_softc *sc)
8185 {
8186         uint32_t phy_idx = bnx2x_get_cur_phy_idx(sc);
8187         switch (sc->link_params.phy[phy_idx].media_type) {
8188         case ELINK_ETH_PHY_SFPP_10G_FIBER:
8189         case ELINK_ETH_PHY_SFP_1G_FIBER:
8190         case ELINK_ETH_PHY_XFP_FIBER:
8191         case ELINK_ETH_PHY_KR:
8192         case ELINK_ETH_PHY_CX4:
8193                 PMD_DRV_LOG(INFO, sc, "Found 10GBase-CX4 media.");
8194                 sc->media = IFM_10G_CX4;
8195                 break;
8196         case ELINK_ETH_PHY_DA_TWINAX:
8197                 PMD_DRV_LOG(INFO, sc, "Found 10Gb Twinax media.");
8198                 sc->media = IFM_10G_TWINAX;
8199                 break;
8200         case ELINK_ETH_PHY_BASE_T:
8201                 PMD_DRV_LOG(INFO, sc, "Found 10GBase-T media.");
8202                 sc->media = IFM_10G_T;
8203                 break;
8204         case ELINK_ETH_PHY_NOT_PRESENT:
8205                 PMD_DRV_LOG(INFO, sc, "Media not present.");
8206                 sc->media = 0;
8207                 break;
8208         case ELINK_ETH_PHY_UNSPECIFIED:
8209         default:
8210                 PMD_DRV_LOG(INFO, sc, "Unknown media!");
8211                 sc->media = 0;
8212                 break;
8213         }
8214 }
8215
8216 #define GET_FIELD(value, fname)                     \
8217 (((value) & (fname##_MASK)) >> (fname##_SHIFT))
8218 #define IGU_FID(val) GET_FIELD((val), IGU_REG_MAPPING_MEMORY_FID)
8219 #define IGU_VEC(val) GET_FIELD((val), IGU_REG_MAPPING_MEMORY_VECTOR)
8220
8221 static int bnx2x_get_igu_cam_info(struct bnx2x_softc *sc)
8222 {
8223         int pfid = SC_FUNC(sc);
8224         int igu_sb_id;
8225         uint32_t val;
8226         uint8_t fid, igu_sb_cnt = 0;
8227
8228         sc->igu_base_sb = 0xff;
8229
8230         if (CHIP_INT_MODE_IS_BC(sc)) {
8231                 int vn = SC_VN(sc);
8232                 igu_sb_cnt = sc->igu_sb_cnt;
8233                 sc->igu_base_sb = ((CHIP_IS_MODE_4_PORT(sc) ? pfid : vn) *
8234                                    FP_SB_MAX_E1x);
8235                 sc->igu_dsb_id = (E1HVN_MAX * FP_SB_MAX_E1x +
8236                                   (CHIP_IS_MODE_4_PORT(sc) ? pfid : vn));
8237                 return 0;
8238         }
8239
8240         /* IGU in normal mode - read CAM */
8241         for (igu_sb_id = 0;
8242              igu_sb_id < IGU_REG_MAPPING_MEMORY_SIZE; igu_sb_id++) {
8243                 val = REG_RD(sc, IGU_REG_MAPPING_MEMORY + igu_sb_id * 4);
8244                 if (!(val & IGU_REG_MAPPING_MEMORY_VALID)) {
8245                         continue;
8246                 }
8247                 fid = IGU_FID(val);
8248                 if (fid & IGU_FID_ENCODE_IS_PF) {
8249                         if ((fid & IGU_FID_PF_NUM_MASK) != pfid) {
8250                                 continue;
8251                         }
8252                         if (IGU_VEC(val) == 0) {
8253                                 /* default status block */
8254                                 sc->igu_dsb_id = igu_sb_id;
8255                         } else {
8256                                 if (sc->igu_base_sb == 0xff) {
8257                                         sc->igu_base_sb = igu_sb_id;
8258                                 }
8259                                 igu_sb_cnt++;
8260                         }
8261                 }
8262         }
8263
8264         /*
8265          * Due to new PF resource allocation by MFW T7.4 and above, it's optional
8266          * that number of CAM entries will not be equal to the value advertised in
8267          * PCI. Driver should use the minimal value of both as the actual status
8268          * block count
8269          */
8270         sc->igu_sb_cnt = min(sc->igu_sb_cnt, igu_sb_cnt);
8271
8272         if (igu_sb_cnt == 0) {
8273                 PMD_DRV_LOG(ERR, sc, "CAM configuration error");
8274                 return -1;
8275         }
8276
8277         return 0;
8278 }
8279
8280 /*
8281 * Gather various information from the device config space, the device itself,
8282 * shmem, and the user input.
8283 */
8284 static int bnx2x_get_device_info(struct bnx2x_softc *sc)
8285 {
8286         uint32_t val;
8287         int rc;
8288
8289         /* get the chip revision (chip metal comes from pci config space) */
8290         sc->devinfo.chip_id = sc->link_params.chip_id =
8291             (((REG_RD(sc, MISC_REG_CHIP_NUM) & 0xffff) << 16) |
8292              ((REG_RD(sc, MISC_REG_CHIP_REV) & 0xf) << 12) |
8293              (((REG_RD(sc, PCICFG_OFFSET + PCI_ID_VAL3) >> 24) & 0xf) << 4) |
8294              ((REG_RD(sc, MISC_REG_BOND_ID) & 0xf) << 0));
8295
8296         /* force 57811 according to MISC register */
8297         if (REG_RD(sc, MISC_REG_CHIP_TYPE) & MISC_REG_CHIP_TYPE_57811_MASK) {
8298                 if (CHIP_IS_57810(sc)) {
8299                         sc->devinfo.chip_id = ((CHIP_NUM_57811 << 16) |
8300                                                (sc->
8301                                                 devinfo.chip_id & 0x0000ffff));
8302                 } else if (CHIP_IS_57810_MF(sc)) {
8303                         sc->devinfo.chip_id = ((CHIP_NUM_57811_MF << 16) |
8304                                                (sc->
8305                                                 devinfo.chip_id & 0x0000ffff));
8306                 }
8307                 sc->devinfo.chip_id |= 0x1;
8308         }
8309
8310         PMD_DRV_LOG(DEBUG, sc,
8311                     "chip_id=0x%08x (num=0x%04x rev=0x%01x metal=0x%02x bond=0x%01x)",
8312                     sc->devinfo.chip_id,
8313                     ((sc->devinfo.chip_id >> 16) & 0xffff),
8314                     ((sc->devinfo.chip_id >> 12) & 0xf),
8315                     ((sc->devinfo.chip_id >> 4) & 0xff),
8316                     ((sc->devinfo.chip_id >> 0) & 0xf));
8317
8318         val = (REG_RD(sc, 0x2874) & 0x55);
8319         if ((sc->devinfo.chip_id & 0x1) || (CHIP_IS_E1H(sc) && (val == 0x55))) {
8320                 sc->flags |= BNX2X_ONE_PORT_FLAG;
8321                 PMD_DRV_LOG(DEBUG, sc, "single port device");
8322         }
8323
8324         /* set the doorbell size */
8325         sc->doorbell_size = (1 << BNX2X_DB_SHIFT);
8326
8327         /* determine whether the device is in 2 port or 4 port mode */
8328         sc->devinfo.chip_port_mode = CHIP_PORT_MODE_NONE;       /* E1h */
8329         if (CHIP_IS_E2E3(sc)) {
8330 /*
8331  * Read port4mode_en_ovwr[0]:
8332  *   If 1, four port mode is in port4mode_en_ovwr[1].
8333  *   If 0, four port mode is in port4mode_en[0].
8334  */
8335                 val = REG_RD(sc, MISC_REG_PORT4MODE_EN_OVWR);
8336                 if (val & 1) {
8337                         val = ((val >> 1) & 1);
8338                 } else {
8339                         val = REG_RD(sc, MISC_REG_PORT4MODE_EN);
8340                 }
8341
8342                 sc->devinfo.chip_port_mode =
8343                     (val) ? CHIP_4_PORT_MODE : CHIP_2_PORT_MODE;
8344
8345                 PMD_DRV_LOG(DEBUG, sc, "Port mode = %s", (val) ? "4" : "2");
8346         }
8347
8348         /* get the function and path info for the device */
8349         bnx2x_get_function_num(sc);
8350
8351         /* get the shared memory base address */
8352         sc->devinfo.shmem_base =
8353             sc->link_params.shmem_base = REG_RD(sc, MISC_REG_SHARED_MEM_ADDR);
8354         sc->devinfo.shmem2_base =
8355             REG_RD(sc, (SC_PATH(sc) ? MISC_REG_GENERIC_CR_1 :
8356                         MISC_REG_GENERIC_CR_0));
8357
8358         if (!sc->devinfo.shmem_base) {
8359 /* this should ONLY prevent upcoming shmem reads */
8360                 PMD_DRV_LOG(INFO, sc, "MCP not active");
8361                 sc->flags |= BNX2X_NO_MCP_FLAG;
8362                 return 0;
8363         }
8364
8365         /* make sure the shared memory contents are valid */
8366         val = SHMEM_RD(sc, validity_map[SC_PORT(sc)]);
8367         if ((val & (SHR_MEM_VALIDITY_DEV_INFO | SHR_MEM_VALIDITY_MB)) !=
8368             (SHR_MEM_VALIDITY_DEV_INFO | SHR_MEM_VALIDITY_MB)) {
8369                 PMD_DRV_LOG(NOTICE, sc, "Invalid SHMEM validity signature: 0x%08x",
8370                             val);
8371                 return 0;
8372         }
8373
8374         /* get the bootcode version */
8375         sc->devinfo.bc_ver = SHMEM_RD(sc, dev_info.bc_rev);
8376         snprintf(sc->devinfo.bc_ver_str,
8377                  sizeof(sc->devinfo.bc_ver_str),
8378                  "%d.%d.%d",
8379                  ((sc->devinfo.bc_ver >> 24) & 0xff),
8380                  ((sc->devinfo.bc_ver >> 16) & 0xff),
8381                  ((sc->devinfo.bc_ver >> 8) & 0xff));
8382         PMD_DRV_LOG(DEBUG, sc, "Bootcode version: %s", sc->devinfo.bc_ver_str);
8383
8384         /* get the bootcode shmem address */
8385         sc->devinfo.mf_cfg_base = bnx2x_get_shmem_mf_cfg_base(sc);
8386
8387         /* clean indirect addresses as they're not used */
8388         pci_write_long(sc, PCICFG_GRC_ADDRESS, 0);
8389         if (IS_PF(sc)) {
8390                 REG_WR(sc, PXP2_REG_PGL_ADDR_88_F0, 0);
8391                 REG_WR(sc, PXP2_REG_PGL_ADDR_8C_F0, 0);
8392                 REG_WR(sc, PXP2_REG_PGL_ADDR_90_F0, 0);
8393                 REG_WR(sc, PXP2_REG_PGL_ADDR_94_F0, 0);
8394                 if (CHIP_IS_E1x(sc)) {
8395                         REG_WR(sc, PXP2_REG_PGL_ADDR_88_F1, 0);
8396                         REG_WR(sc, PXP2_REG_PGL_ADDR_8C_F1, 0);
8397                         REG_WR(sc, PXP2_REG_PGL_ADDR_90_F1, 0);
8398                         REG_WR(sc, PXP2_REG_PGL_ADDR_94_F1, 0);
8399                 }
8400         }
8401
8402         /* get the nvram size */
8403         val = REG_RD(sc, MCP_REG_MCPR_NVM_CFG4);
8404         sc->devinfo.flash_size =
8405             (NVRAM_1MB_SIZE << (val & MCPR_NVM_CFG4_FLASH_SIZE));
8406
8407         bnx2x_set_power_state(sc, PCI_PM_D0);
8408         /* get various configuration parameters from shmem */
8409         bnx2x_get_shmem_info(sc);
8410
8411         /* initialize IGU parameters */
8412         if (CHIP_IS_E1x(sc)) {
8413                 sc->devinfo.int_block = INT_BLOCK_HC;
8414                 sc->igu_dsb_id = DEF_SB_IGU_ID;
8415                 sc->igu_base_sb = 0;
8416         } else {
8417                 sc->devinfo.int_block = INT_BLOCK_IGU;
8418
8419 /* do not allow device reset during IGU info preocessing */
8420                 bnx2x_acquire_hw_lock(sc, HW_LOCK_RESOURCE_RESET);
8421
8422                 val = REG_RD(sc, IGU_REG_BLOCK_CONFIGURATION);
8423
8424                 if (val & IGU_BLOCK_CONFIGURATION_REG_BACKWARD_COMP_EN) {
8425                         int tout = 5000;
8426
8427                         val &= ~(IGU_BLOCK_CONFIGURATION_REG_BACKWARD_COMP_EN);
8428                         REG_WR(sc, IGU_REG_BLOCK_CONFIGURATION, val);
8429                         REG_WR(sc, IGU_REG_RESET_MEMORIES, 0x7f);
8430
8431                         while (tout && REG_RD(sc, IGU_REG_RESET_MEMORIES)) {
8432                                 tout--;
8433                                 DELAY(1000);
8434                         }
8435
8436                         if (REG_RD(sc, IGU_REG_RESET_MEMORIES)) {
8437                                 PMD_DRV_LOG(NOTICE, sc,
8438                                             "FORCING IGU Normal Mode failed!!!");
8439                                 bnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_RESET);
8440                                 return -1;
8441                         }
8442                 }
8443
8444                 if (val & IGU_BLOCK_CONFIGURATION_REG_BACKWARD_COMP_EN) {
8445                         PMD_DRV_LOG(DEBUG, sc, "IGU Backward Compatible Mode");
8446                         sc->devinfo.int_block |= INT_BLOCK_MODE_BW_COMP;
8447                 } else {
8448                         PMD_DRV_LOG(DEBUG, sc, "IGU Normal Mode");
8449                 }
8450
8451                 rc = bnx2x_get_igu_cam_info(sc);
8452
8453                 bnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_RESET);
8454
8455                 if (rc) {
8456                         return rc;
8457                 }
8458         }
8459
8460         /*
8461          * Get base FW non-default (fast path) status block ID. This value is
8462          * used to initialize the fw_sb_id saved on the fp/queue structure to
8463          * determine the id used by the FW.
8464          */
8465         if (CHIP_IS_E1x(sc)) {
8466                 sc->base_fw_ndsb =
8467                     ((SC_PORT(sc) * FP_SB_MAX_E1x) + SC_L_ID(sc));
8468         } else {
8469 /*
8470  * 57712+ - We currently use one FW SB per IGU SB (Rx and Tx of
8471  * the same queue are indicated on the same IGU SB). So we prefer
8472  * FW and IGU SBs to be the same value.
8473  */
8474                 sc->base_fw_ndsb = sc->igu_base_sb;
8475         }
8476
8477         elink_phy_probe(&sc->link_params);
8478
8479         return 0;
8480 }
8481
8482 static void
8483 bnx2x_link_settings_supported(struct bnx2x_softc *sc, uint32_t switch_cfg)
8484 {
8485         uint32_t cfg_size = 0;
8486         uint32_t idx;
8487         uint8_t port = SC_PORT(sc);
8488
8489         /* aggregation of supported attributes of all external phys */
8490         sc->port.supported[0] = 0;
8491         sc->port.supported[1] = 0;
8492
8493         switch (sc->link_params.num_phys) {
8494         case 1:
8495                 sc->port.supported[0] =
8496                     sc->link_params.phy[ELINK_INT_PHY].supported;
8497                 cfg_size = 1;
8498                 break;
8499         case 2:
8500                 sc->port.supported[0] =
8501                     sc->link_params.phy[ELINK_EXT_PHY1].supported;
8502                 cfg_size = 1;
8503                 break;
8504         case 3:
8505                 if (sc->link_params.multi_phy_config &
8506                     PORT_HW_CFG_PHY_SWAPPED_ENABLED) {
8507                         sc->port.supported[1] =
8508                             sc->link_params.phy[ELINK_EXT_PHY1].supported;
8509                         sc->port.supported[0] =
8510                             sc->link_params.phy[ELINK_EXT_PHY2].supported;
8511                 } else {
8512                         sc->port.supported[0] =
8513                             sc->link_params.phy[ELINK_EXT_PHY1].supported;
8514                         sc->port.supported[1] =
8515                             sc->link_params.phy[ELINK_EXT_PHY2].supported;
8516                 }
8517                 cfg_size = 2;
8518                 break;
8519         }
8520
8521         if (!(sc->port.supported[0] || sc->port.supported[1])) {
8522                 PMD_DRV_LOG(ERR, sc,
8523                             "Invalid phy config in NVRAM (PHY1=0x%08x PHY2=0x%08x)",
8524                             SHMEM_RD(sc,
8525                                      dev_info.port_hw_config
8526                                      [port].external_phy_config),
8527                             SHMEM_RD(sc,
8528                                      dev_info.port_hw_config
8529                                      [port].external_phy_config2));
8530                 return;
8531         }
8532
8533         if (CHIP_IS_E3(sc))
8534                 sc->port.phy_addr = REG_RD(sc, MISC_REG_WC0_CTRL_PHY_ADDR);
8535         else {
8536                 switch (switch_cfg) {
8537                 case ELINK_SWITCH_CFG_1G:
8538                         sc->port.phy_addr =
8539                             REG_RD(sc,
8540                                    NIG_REG_SERDES0_CTRL_PHY_ADDR + port * 0x10);
8541                         break;
8542                 case ELINK_SWITCH_CFG_10G:
8543                         sc->port.phy_addr =
8544                             REG_RD(sc,
8545                                    NIG_REG_XGXS0_CTRL_PHY_ADDR + port * 0x18);
8546                         break;
8547                 default:
8548                         PMD_DRV_LOG(ERR, sc,
8549                                     "Invalid switch config in"
8550                                     "link_config=0x%08x",
8551                                     sc->port.link_config[0]);
8552                         return;
8553                 }
8554         }
8555
8556         PMD_DRV_LOG(INFO, sc, "PHY addr 0x%08x", sc->port.phy_addr);
8557
8558         /* mask what we support according to speed_cap_mask per configuration */
8559         for (idx = 0; idx < cfg_size; idx++) {
8560                 if (!(sc->link_params.speed_cap_mask[idx] &
8561                       PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_HALF)) {
8562                         sc->port.supported[idx] &=
8563                             ~ELINK_SUPPORTED_10baseT_Half;
8564                 }
8565
8566                 if (!(sc->link_params.speed_cap_mask[idx] &
8567                       PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL)) {
8568                         sc->port.supported[idx] &=
8569                             ~ELINK_SUPPORTED_10baseT_Full;
8570                 }
8571
8572                 if (!(sc->link_params.speed_cap_mask[idx] &
8573                       PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_HALF)) {
8574                         sc->port.supported[idx] &=
8575                             ~ELINK_SUPPORTED_100baseT_Half;
8576                 }
8577
8578                 if (!(sc->link_params.speed_cap_mask[idx] &
8579                       PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_FULL)) {
8580                         sc->port.supported[idx] &=
8581                             ~ELINK_SUPPORTED_100baseT_Full;
8582                 }
8583
8584                 if (!(sc->link_params.speed_cap_mask[idx] &
8585                       PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)) {
8586                         sc->port.supported[idx] &=
8587                             ~ELINK_SUPPORTED_1000baseT_Full;
8588                 }
8589
8590                 if (!(sc->link_params.speed_cap_mask[idx] &
8591                       PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G)) {
8592                         sc->port.supported[idx] &=
8593                             ~ELINK_SUPPORTED_2500baseX_Full;
8594                 }
8595
8596                 if (!(sc->link_params.speed_cap_mask[idx] &
8597                       PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)) {
8598                         sc->port.supported[idx] &=
8599                             ~ELINK_SUPPORTED_10000baseT_Full;
8600                 }
8601
8602                 if (!(sc->link_params.speed_cap_mask[idx] &
8603                       PORT_HW_CFG_SPEED_CAPABILITY_D0_20G)) {
8604                         sc->port.supported[idx] &=
8605                             ~ELINK_SUPPORTED_20000baseKR2_Full;
8606                 }
8607         }
8608
8609         PMD_DRV_LOG(INFO, sc, "PHY supported 0=0x%08x 1=0x%08x",
8610                     sc->port.supported[0], sc->port.supported[1]);
8611 }
8612
8613 static void bnx2x_link_settings_requested(struct bnx2x_softc *sc)
8614 {
8615         uint32_t link_config;
8616         uint32_t idx;
8617         uint32_t cfg_size = 0;
8618
8619         sc->port.advertising[0] = 0;
8620         sc->port.advertising[1] = 0;
8621
8622         switch (sc->link_params.num_phys) {
8623         case 1:
8624         case 2:
8625                 cfg_size = 1;
8626                 break;
8627         case 3:
8628                 cfg_size = 2;
8629                 break;
8630         }
8631
8632         for (idx = 0; idx < cfg_size; idx++) {
8633                 sc->link_params.req_duplex[idx] = DUPLEX_FULL;
8634                 link_config = sc->port.link_config[idx];
8635
8636                 switch (link_config & PORT_FEATURE_LINK_SPEED_MASK) {
8637                 case PORT_FEATURE_LINK_SPEED_AUTO:
8638                         if (sc->port.supported[idx] & ELINK_SUPPORTED_Autoneg) {
8639                                 sc->link_params.req_line_speed[idx] =
8640                                     ELINK_SPEED_AUTO_NEG;
8641                                 sc->port.advertising[idx] |=
8642                                     sc->port.supported[idx];
8643                                 if (sc->link_params.phy[ELINK_EXT_PHY1].type ==
8644                                     PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X84833)
8645                                         sc->port.advertising[idx] |=
8646                                             (ELINK_SUPPORTED_100baseT_Half |
8647                                              ELINK_SUPPORTED_100baseT_Full);
8648                         } else {
8649                                 /* force 10G, no AN */
8650                                 sc->link_params.req_line_speed[idx] =
8651                                     ELINK_SPEED_10000;
8652                                 sc->port.advertising[idx] |=
8653                                     (ADVERTISED_10000baseT_Full |
8654                                      ADVERTISED_FIBRE);
8655                                 continue;
8656                         }
8657                         break;
8658
8659                 case PORT_FEATURE_LINK_SPEED_10M_FULL:
8660                         if (sc->
8661                             port.supported[idx] & ELINK_SUPPORTED_10baseT_Full)
8662                         {
8663                                 sc->link_params.req_line_speed[idx] =
8664                                     ELINK_SPEED_10;
8665                                 sc->port.advertising[idx] |=
8666                                     (ADVERTISED_10baseT_Full | ADVERTISED_TP);
8667                         } else {
8668                                 PMD_DRV_LOG(ERR, sc,
8669                                             "Invalid NVRAM config link_config=0x%08x "
8670                                             "speed_cap_mask=0x%08x",
8671                                             link_config,
8672                                             sc->
8673                                             link_params.speed_cap_mask[idx]);
8674                                 return;
8675                         }
8676                         break;
8677
8678                 case PORT_FEATURE_LINK_SPEED_10M_HALF:
8679                         if (sc->
8680                             port.supported[idx] & ELINK_SUPPORTED_10baseT_Half)
8681                         {
8682                                 sc->link_params.req_line_speed[idx] =
8683                                     ELINK_SPEED_10;
8684                                 sc->link_params.req_duplex[idx] = DUPLEX_HALF;
8685                                 sc->port.advertising[idx] |=
8686                                     (ADVERTISED_10baseT_Half | ADVERTISED_TP);
8687                         } else {
8688                                 PMD_DRV_LOG(ERR, sc,
8689                                             "Invalid NVRAM config link_config=0x%08x "
8690                                             "speed_cap_mask=0x%08x",
8691                                             link_config,
8692                                             sc->
8693                                             link_params.speed_cap_mask[idx]);
8694                                 return;
8695                         }
8696                         break;
8697
8698                 case PORT_FEATURE_LINK_SPEED_100M_FULL:
8699                         if (sc->
8700                             port.supported[idx] & ELINK_SUPPORTED_100baseT_Full)
8701                         {
8702                                 sc->link_params.req_line_speed[idx] =
8703                                     ELINK_SPEED_100;
8704                                 sc->port.advertising[idx] |=
8705                                     (ADVERTISED_100baseT_Full | ADVERTISED_TP);
8706                         } else {
8707                                 PMD_DRV_LOG(ERR, sc,
8708                                             "Invalid NVRAM config link_config=0x%08x "
8709                                             "speed_cap_mask=0x%08x",
8710                                             link_config,
8711                                             sc->
8712                                             link_params.speed_cap_mask[idx]);
8713                                 return;
8714                         }
8715                         break;
8716
8717                 case PORT_FEATURE_LINK_SPEED_100M_HALF:
8718                         if (sc->
8719                             port.supported[idx] & ELINK_SUPPORTED_100baseT_Half)
8720                         {
8721                                 sc->link_params.req_line_speed[idx] =
8722                                     ELINK_SPEED_100;
8723                                 sc->link_params.req_duplex[idx] = DUPLEX_HALF;
8724                                 sc->port.advertising[idx] |=
8725                                     (ADVERTISED_100baseT_Half | ADVERTISED_TP);
8726                         } else {
8727                                 PMD_DRV_LOG(ERR, sc,
8728                                             "Invalid NVRAM config link_config=0x%08x "
8729                                             "speed_cap_mask=0x%08x",
8730                                             link_config,
8731                                             sc->
8732                                             link_params.speed_cap_mask[idx]);
8733                                 return;
8734                         }
8735                         break;
8736
8737                 case PORT_FEATURE_LINK_SPEED_1G:
8738                         if (sc->port.supported[idx] &
8739                             ELINK_SUPPORTED_1000baseT_Full) {
8740                                 sc->link_params.req_line_speed[idx] =
8741                                     ELINK_SPEED_1000;
8742                                 sc->port.advertising[idx] |=
8743                                     (ADVERTISED_1000baseT_Full | ADVERTISED_TP);
8744                         } else {
8745                                 PMD_DRV_LOG(ERR, sc,
8746                                             "Invalid NVRAM config link_config=0x%08x "
8747                                             "speed_cap_mask=0x%08x",
8748                                             link_config,
8749                                             sc->
8750                                             link_params.speed_cap_mask[idx]);
8751                                 return;
8752                         }
8753                         break;
8754
8755                 case PORT_FEATURE_LINK_SPEED_2_5G:
8756                         if (sc->port.supported[idx] &
8757                             ELINK_SUPPORTED_2500baseX_Full) {
8758                                 sc->link_params.req_line_speed[idx] =
8759                                     ELINK_SPEED_2500;
8760                                 sc->port.advertising[idx] |=
8761                                     (ADVERTISED_2500baseX_Full | ADVERTISED_TP);
8762                         } else {
8763                                 PMD_DRV_LOG(ERR, sc,
8764                                             "Invalid NVRAM config link_config=0x%08x "
8765                                             "speed_cap_mask=0x%08x",
8766                                             link_config,
8767                                             sc->
8768                                             link_params.speed_cap_mask[idx]);
8769                                 return;
8770                         }
8771                         break;
8772
8773                 case PORT_FEATURE_LINK_SPEED_10G_CX4:
8774                         if (sc->port.supported[idx] &
8775                             ELINK_SUPPORTED_10000baseT_Full) {
8776                                 sc->link_params.req_line_speed[idx] =
8777                                     ELINK_SPEED_10000;
8778                                 sc->port.advertising[idx] |=
8779                                     (ADVERTISED_10000baseT_Full |
8780                                      ADVERTISED_FIBRE);
8781                         } else {
8782                                 PMD_DRV_LOG(ERR, sc,
8783                                             "Invalid NVRAM config link_config=0x%08x "
8784                                             "speed_cap_mask=0x%08x",
8785                                             link_config,
8786                                             sc->
8787                                             link_params.speed_cap_mask[idx]);
8788                                 return;
8789                         }
8790                         break;
8791
8792                 case PORT_FEATURE_LINK_SPEED_20G:
8793                         sc->link_params.req_line_speed[idx] = ELINK_SPEED_20000;
8794                         break;
8795
8796                 default:
8797                         PMD_DRV_LOG(ERR, sc,
8798                                     "Invalid NVRAM config link_config=0x%08x "
8799                                     "speed_cap_mask=0x%08x", link_config,
8800                                     sc->link_params.speed_cap_mask[idx]);
8801                         sc->link_params.req_line_speed[idx] =
8802                             ELINK_SPEED_AUTO_NEG;
8803                         sc->port.advertising[idx] = sc->port.supported[idx];
8804                         break;
8805                 }
8806
8807                 sc->link_params.req_flow_ctrl[idx] =
8808                     (link_config & PORT_FEATURE_FLOW_CONTROL_MASK);
8809
8810                 if (sc->link_params.req_flow_ctrl[idx] == ELINK_FLOW_CTRL_AUTO) {
8811                         if (!
8812                             (sc->
8813                              port.supported[idx] & ELINK_SUPPORTED_Autoneg)) {
8814                                 sc->link_params.req_flow_ctrl[idx] =
8815                                     ELINK_FLOW_CTRL_NONE;
8816                         } else {
8817                                 bnx2x_set_requested_fc(sc);
8818                         }
8819                 }
8820         }
8821 }
8822
8823 static void bnx2x_get_phy_info(struct bnx2x_softc *sc)
8824 {
8825         uint8_t port = SC_PORT(sc);
8826         uint32_t eee_mode;
8827
8828         PMD_INIT_FUNC_TRACE(sc);
8829
8830         /* shmem data already read in bnx2x_get_shmem_info() */
8831
8832         bnx2x_link_settings_supported(sc, sc->link_params.switch_cfg);
8833         bnx2x_link_settings_requested(sc);
8834
8835         /* configure link feature according to nvram value */
8836         eee_mode =
8837             (((SHMEM_RD(sc, dev_info.port_feature_config[port].eee_power_mode))
8838               & PORT_FEAT_CFG_EEE_POWER_MODE_MASK) >>
8839              PORT_FEAT_CFG_EEE_POWER_MODE_SHIFT);
8840         if (eee_mode != PORT_FEAT_CFG_EEE_POWER_MODE_DISABLED) {
8841                 sc->link_params.eee_mode = (ELINK_EEE_MODE_ADV_LPI |
8842                                             ELINK_EEE_MODE_ENABLE_LPI |
8843                                             ELINK_EEE_MODE_OUTPUT_TIME);
8844         } else {
8845                 sc->link_params.eee_mode = 0;
8846         }
8847
8848         /* get the media type */
8849         bnx2x_media_detect(sc);
8850 }
8851
8852 static void bnx2x_set_modes_bitmap(struct bnx2x_softc *sc)
8853 {
8854         uint32_t flags = MODE_ASIC | MODE_PORT2;
8855
8856         if (CHIP_IS_E2(sc)) {
8857                 flags |= MODE_E2;
8858         } else if (CHIP_IS_E3(sc)) {
8859                 flags |= MODE_E3;
8860                 if (CHIP_REV(sc) == CHIP_REV_Ax) {
8861                         flags |= MODE_E3_A0;
8862                 } else {        /*if (CHIP_REV(sc) == CHIP_REV_Bx) */
8863
8864                         flags |= MODE_E3_B0 | MODE_COS3;
8865                 }
8866         }
8867
8868         if (IS_MF(sc)) {
8869                 flags |= MODE_MF;
8870                 switch (sc->devinfo.mf_info.mf_mode) {
8871                 case MULTI_FUNCTION_SD:
8872                         flags |= MODE_MF_SD;
8873                         break;
8874                 case MULTI_FUNCTION_SI:
8875                         flags |= MODE_MF_SI;
8876                         break;
8877                 case MULTI_FUNCTION_AFEX:
8878                         flags |= MODE_MF_AFEX;
8879                         break;
8880                 }
8881         } else {
8882                 flags |= MODE_SF;
8883         }
8884
8885 #if defined(__LITTLE_ENDIAN)
8886         flags |= MODE_LITTLE_ENDIAN;
8887 #else /* __BIG_ENDIAN */
8888         flags |= MODE_BIG_ENDIAN;
8889 #endif
8890
8891         INIT_MODE_FLAGS(sc) = flags;
8892 }
8893
8894 int bnx2x_alloc_hsi_mem(struct bnx2x_softc *sc)
8895 {
8896         struct bnx2x_fastpath *fp;
8897         char buf[32];
8898         uint32_t i;
8899
8900         if (IS_PF(sc)) {
8901                 /************************/
8902                 /* DEFAULT STATUS BLOCK */
8903                 /************************/
8904
8905                 if (bnx2x_dma_alloc(sc, sizeof(struct host_sp_status_block),
8906                                   &sc->def_sb_dma, "def_sb",
8907                                   RTE_CACHE_LINE_SIZE) != 0) {
8908                         return -1;
8909                 }
8910
8911                 sc->def_sb =
8912                     (struct host_sp_status_block *)sc->def_sb_dma.vaddr;
8913                 /***************/
8914                 /* EVENT QUEUE */
8915                 /***************/
8916
8917                 if (bnx2x_dma_alloc(sc, BNX2X_PAGE_SIZE,
8918                                   &sc->eq_dma, "ev_queue",
8919                                   RTE_CACHE_LINE_SIZE) != 0) {
8920                         sc->def_sb = NULL;
8921                         return -1;
8922                 }
8923
8924                 sc->eq = (union event_ring_elem *)sc->eq_dma.vaddr;
8925
8926                 /*************/
8927                 /* SLOW PATH */
8928                 /*************/
8929
8930                 if (bnx2x_dma_alloc(sc, sizeof(struct bnx2x_slowpath),
8931                                   &sc->sp_dma, "sp",
8932                                   RTE_CACHE_LINE_SIZE) != 0) {
8933                         sc->eq = NULL;
8934                         sc->def_sb = NULL;
8935                         return -1;
8936                 }
8937
8938                 sc->sp = (struct bnx2x_slowpath *)sc->sp_dma.vaddr;
8939
8940                 /*******************/
8941                 /* SLOW PATH QUEUE */
8942                 /*******************/
8943
8944                 if (bnx2x_dma_alloc(sc, BNX2X_PAGE_SIZE,
8945                                   &sc->spq_dma, "sp_queue",
8946                                   RTE_CACHE_LINE_SIZE) != 0) {
8947                         sc->sp = NULL;
8948                         sc->eq = NULL;
8949                         sc->def_sb = NULL;
8950                         return -1;
8951                 }
8952
8953                 sc->spq = (struct eth_spe *)sc->spq_dma.vaddr;
8954
8955                 /***************************/
8956                 /* FW DECOMPRESSION BUFFER */
8957                 /***************************/
8958
8959                 if (bnx2x_dma_alloc(sc, FW_BUF_SIZE, &sc->gz_buf_dma,
8960                                   "fw_buf", RTE_CACHE_LINE_SIZE) != 0) {
8961                         sc->spq = NULL;
8962                         sc->sp = NULL;
8963                         sc->eq = NULL;
8964                         sc->def_sb = NULL;
8965                         return -1;
8966                 }
8967
8968                 sc->gz_buf = (void *)sc->gz_buf_dma.vaddr;
8969         }
8970
8971         /*************/
8972         /* FASTPATHS */
8973         /*************/
8974
8975         /* allocate DMA memory for each fastpath structure */
8976         for (i = 0; i < sc->num_queues; i++) {
8977                 fp = &sc->fp[i];
8978                 fp->sc = sc;
8979                 fp->index = i;
8980
8981                 /*******************/
8982                 /* FP STATUS BLOCK */
8983                 /*******************/
8984
8985                 snprintf(buf, sizeof(buf), "fp_%d_sb", i);
8986                 if (bnx2x_dma_alloc(sc, sizeof(union bnx2x_host_hc_status_block),
8987                                   &fp->sb_dma, buf, RTE_CACHE_LINE_SIZE) != 0) {
8988                         PMD_DRV_LOG(NOTICE, sc, "Failed to alloc %s", buf);
8989                         return -1;
8990                 } else {
8991                         if (CHIP_IS_E2E3(sc)) {
8992                                 fp->status_block.e2_sb =
8993                                     (struct host_hc_status_block_e2 *)
8994                                     fp->sb_dma.vaddr;
8995                         } else {
8996                                 fp->status_block.e1x_sb =
8997                                     (struct host_hc_status_block_e1x *)
8998                                     fp->sb_dma.vaddr;
8999                         }
9000                 }
9001         }
9002
9003         return 0;
9004 }
9005
9006 void bnx2x_free_hsi_mem(struct bnx2x_softc *sc)
9007 {
9008         struct bnx2x_fastpath *fp;
9009         int i;
9010
9011         for (i = 0; i < sc->num_queues; i++) {
9012                 fp = &sc->fp[i];
9013
9014                 /*******************/
9015                 /* FP STATUS BLOCK */
9016                 /*******************/
9017
9018                 memset(&fp->status_block, 0, sizeof(fp->status_block));
9019                 bnx2x_dma_free(&fp->sb_dma);
9020         }
9021
9022         if (IS_PF(sc)) {
9023                 /***************************/
9024                 /* FW DECOMPRESSION BUFFER */
9025                 /***************************/
9026
9027                 bnx2x_dma_free(&sc->gz_buf_dma);
9028                 sc->gz_buf = NULL;
9029
9030                 /*******************/
9031                 /* SLOW PATH QUEUE */
9032                 /*******************/
9033
9034                 bnx2x_dma_free(&sc->spq_dma);
9035                 sc->spq = NULL;
9036
9037                 /*************/
9038                 /* SLOW PATH */
9039                 /*************/
9040
9041                 bnx2x_dma_free(&sc->sp_dma);
9042                 sc->sp = NULL;
9043
9044                 /***************/
9045                 /* EVENT QUEUE */
9046                 /***************/
9047
9048                 bnx2x_dma_free(&sc->eq_dma);
9049                 sc->eq = NULL;
9050
9051                 /************************/
9052                 /* DEFAULT STATUS BLOCK */
9053                 /************************/
9054
9055                 bnx2x_dma_free(&sc->def_sb_dma);
9056                 sc->def_sb = NULL;
9057         }
9058 }
9059
9060 /*
9061 * Previous driver DMAE transaction may have occurred when pre-boot stage
9062 * ended and boot began. This would invalidate the addresses of the
9063 * transaction, resulting in was-error bit set in the PCI causing all
9064 * hw-to-host PCIe transactions to timeout. If this happened we want to clear
9065 * the interrupt which detected this from the pglueb and the was-done bit
9066 */
9067 static void bnx2x_prev_interrupted_dmae(struct bnx2x_softc *sc)
9068 {
9069         uint32_t val;
9070
9071         if (!CHIP_IS_E1x(sc)) {
9072                 val = REG_RD(sc, PGLUE_B_REG_PGLUE_B_INT_STS);
9073                 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_WAS_ERROR_ATTN) {
9074                         REG_WR(sc, PGLUE_B_REG_WAS_ERROR_PF_7_0_CLR,
9075                                1 << SC_FUNC(sc));
9076                 }
9077         }
9078 }
9079
9080 static int bnx2x_prev_mcp_done(struct bnx2x_softc *sc)
9081 {
9082         uint32_t rc = bnx2x_fw_command(sc, DRV_MSG_CODE_UNLOAD_DONE,
9083                                      DRV_MSG_CODE_UNLOAD_SKIP_LINK_RESET);
9084         if (!rc) {
9085                 PMD_DRV_LOG(NOTICE, sc, "MCP response failure, aborting");
9086                 return -1;
9087         }
9088
9089         return 0;
9090 }
9091
9092 static struct bnx2x_prev_list_node *bnx2x_prev_path_get_entry(struct bnx2x_softc *sc)
9093 {
9094         struct bnx2x_prev_list_node *tmp;
9095
9096         LIST_FOREACH(tmp, &bnx2x_prev_list, node) {
9097                 if ((sc->pcie_bus == tmp->bus) &&
9098                     (sc->pcie_device == tmp->slot) &&
9099                     (SC_PATH(sc) == tmp->path)) {
9100                         return tmp;
9101                 }
9102         }
9103
9104         return NULL;
9105 }
9106
9107 static uint8_t bnx2x_prev_is_path_marked(struct bnx2x_softc *sc)
9108 {
9109         struct bnx2x_prev_list_node *tmp;
9110         int rc = FALSE;
9111
9112         rte_spinlock_lock(&bnx2x_prev_mtx);
9113
9114         tmp = bnx2x_prev_path_get_entry(sc);
9115         if (tmp) {
9116                 if (tmp->aer) {
9117                         PMD_DRV_LOG(DEBUG, sc,
9118                                     "Path %d/%d/%d was marked by AER",
9119                                     sc->pcie_bus, sc->pcie_device, SC_PATH(sc));
9120                 } else {
9121                         rc = TRUE;
9122                         PMD_DRV_LOG(DEBUG, sc,
9123                                     "Path %d/%d/%d was already cleaned from previous drivers",
9124                                     sc->pcie_bus, sc->pcie_device, SC_PATH(sc));
9125                 }
9126         }
9127
9128         rte_spinlock_unlock(&bnx2x_prev_mtx);
9129
9130         return rc;
9131 }
9132
9133 static int bnx2x_prev_mark_path(struct bnx2x_softc *sc, uint8_t after_undi)
9134 {
9135         struct bnx2x_prev_list_node *tmp;
9136
9137         rte_spinlock_lock(&bnx2x_prev_mtx);
9138
9139         /* Check whether the entry for this path already exists */
9140         tmp = bnx2x_prev_path_get_entry(sc);
9141         if (tmp) {
9142                 if (!tmp->aer) {
9143                         PMD_DRV_LOG(DEBUG, sc,
9144                                     "Re-marking AER in path %d/%d/%d",
9145                                     sc->pcie_bus, sc->pcie_device, SC_PATH(sc));
9146                 } else {
9147                         PMD_DRV_LOG(DEBUG, sc,
9148                                     "Removing AER indication from path %d/%d/%d",
9149                                     sc->pcie_bus, sc->pcie_device, SC_PATH(sc));
9150                         tmp->aer = 0;
9151                 }
9152
9153                 rte_spinlock_unlock(&bnx2x_prev_mtx);
9154                 return 0;
9155         }
9156
9157         rte_spinlock_unlock(&bnx2x_prev_mtx);
9158
9159         /* Create an entry for this path and add it */
9160         tmp = rte_malloc("", sizeof(struct bnx2x_prev_list_node),
9161                          RTE_CACHE_LINE_SIZE);
9162         if (!tmp) {
9163                 PMD_DRV_LOG(NOTICE, sc, "Failed to allocate 'bnx2x_prev_list_node'");
9164                 return -1;
9165         }
9166
9167         tmp->bus = sc->pcie_bus;
9168         tmp->slot = sc->pcie_device;
9169         tmp->path = SC_PATH(sc);
9170         tmp->aer = 0;
9171         tmp->undi = after_undi ? (1 << SC_PORT(sc)) : 0;
9172
9173         rte_spinlock_lock(&bnx2x_prev_mtx);
9174
9175         LIST_INSERT_HEAD(&bnx2x_prev_list, tmp, node);
9176
9177         rte_spinlock_unlock(&bnx2x_prev_mtx);
9178
9179         return 0;
9180 }
9181
9182 static int bnx2x_do_flr(struct bnx2x_softc *sc)
9183 {
9184         int i;
9185
9186         /* only E2 and onwards support FLR */
9187         if (CHIP_IS_E1x(sc)) {
9188                 PMD_DRV_LOG(WARNING, sc, "FLR not supported in E1H");
9189                 return -1;
9190         }
9191
9192         /* only bootcode REQ_BC_VER_4_INITIATE_FLR and onwards support flr */
9193         if (sc->devinfo.bc_ver < REQ_BC_VER_4_INITIATE_FLR) {
9194                 PMD_DRV_LOG(WARNING, sc,
9195                             "FLR not supported by BC_VER: 0x%08x",
9196                             sc->devinfo.bc_ver);
9197                 return -1;
9198         }
9199
9200         /* Wait for Transaction Pending bit clean */
9201         for (i = 0; i < 4; i++) {
9202                 if (i) {
9203                         DELAY(((1 << (i - 1)) * 100) * 1000);
9204                 }
9205
9206                 if (!bnx2x_is_pcie_pending(sc)) {
9207                         goto clear;
9208                 }
9209         }
9210
9211         PMD_DRV_LOG(NOTICE, sc, "PCIE transaction is not cleared, "
9212                     "proceeding with reset anyway");
9213
9214 clear:
9215         bnx2x_fw_command(sc, DRV_MSG_CODE_INITIATE_FLR, 0);
9216
9217         return 0;
9218 }
9219
9220 struct bnx2x_mac_vals {
9221         uint32_t xmac_addr;
9222         uint32_t xmac_val;
9223         uint32_t emac_addr;
9224         uint32_t emac_val;
9225         uint32_t umac_addr;
9226         uint32_t umac_val;
9227         uint32_t bmac_addr;
9228         uint32_t bmac_val[2];
9229 };
9230
9231 static void
9232 bnx2x_prev_unload_close_mac(struct bnx2x_softc *sc, struct bnx2x_mac_vals *vals)
9233 {
9234         uint32_t val, base_addr, offset, mask, reset_reg;
9235         uint8_t mac_stopped = FALSE;
9236         uint8_t port = SC_PORT(sc);
9237         uint32_t wb_data[2];
9238
9239         /* reset addresses as they also mark which values were changed */
9240         vals->bmac_addr = 0;
9241         vals->umac_addr = 0;
9242         vals->xmac_addr = 0;
9243         vals->emac_addr = 0;
9244
9245         reset_reg = REG_RD(sc, MISC_REG_RESET_REG_2);
9246
9247         if (!CHIP_IS_E3(sc)) {
9248                 val = REG_RD(sc, NIG_REG_BMAC0_REGS_OUT_EN + port * 4);
9249                 mask = MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port;
9250                 if ((mask & reset_reg) && val) {
9251                         base_addr = SC_PORT(sc) ? NIG_REG_INGRESS_BMAC1_MEM
9252                             : NIG_REG_INGRESS_BMAC0_MEM;
9253                         offset = CHIP_IS_E2(sc) ? BIGMAC2_REGISTER_BMAC_CONTROL
9254                             : BIGMAC_REGISTER_BMAC_CONTROL;
9255
9256                         /*
9257                          * use rd/wr since we cannot use dmae. This is safe
9258                          * since MCP won't access the bus due to the request
9259                          * to unload, and no function on the path can be
9260                          * loaded at this time.
9261                          */
9262                         wb_data[0] = REG_RD(sc, base_addr + offset);
9263                         wb_data[1] = REG_RD(sc, base_addr + offset + 0x4);
9264                         vals->bmac_addr = base_addr + offset;
9265                         vals->bmac_val[0] = wb_data[0];
9266                         vals->bmac_val[1] = wb_data[1];
9267                         wb_data[0] &= ~ELINK_BMAC_CONTROL_RX_ENABLE;
9268                         REG_WR(sc, vals->bmac_addr, wb_data[0]);
9269                         REG_WR(sc, vals->bmac_addr + 0x4, wb_data[1]);
9270                 }
9271
9272                 vals->emac_addr = NIG_REG_NIG_EMAC0_EN + SC_PORT(sc) * 4;
9273                 vals->emac_val = REG_RD(sc, vals->emac_addr);
9274                 REG_WR(sc, vals->emac_addr, 0);
9275                 mac_stopped = TRUE;
9276         } else {
9277                 if (reset_reg & MISC_REGISTERS_RESET_REG_2_XMAC) {
9278                         base_addr = SC_PORT(sc) ? GRCBASE_XMAC1 : GRCBASE_XMAC0;
9279                         val = REG_RD(sc, base_addr + XMAC_REG_PFC_CTRL_HI);
9280                         REG_WR(sc, base_addr + XMAC_REG_PFC_CTRL_HI,
9281                                val & ~(1 << 1));
9282                         REG_WR(sc, base_addr + XMAC_REG_PFC_CTRL_HI,
9283                                val | (1 << 1));
9284                         vals->xmac_addr = base_addr + XMAC_REG_CTRL;
9285                         vals->xmac_val = REG_RD(sc, vals->xmac_addr);
9286                         REG_WR(sc, vals->xmac_addr, 0);
9287                         mac_stopped = TRUE;
9288                 }
9289
9290                 mask = MISC_REGISTERS_RESET_REG_2_UMAC0 << port;
9291                 if (mask & reset_reg) {
9292                         base_addr = SC_PORT(sc) ? GRCBASE_UMAC1 : GRCBASE_UMAC0;
9293                         vals->umac_addr = base_addr + UMAC_REG_COMMAND_CONFIG;
9294                         vals->umac_val = REG_RD(sc, vals->umac_addr);
9295                         REG_WR(sc, vals->umac_addr, 0);
9296                         mac_stopped = TRUE;
9297                 }
9298         }
9299
9300         if (mac_stopped) {
9301                 DELAY(20000);
9302         }
9303 }
9304
9305 #define BNX2X_PREV_UNDI_PROD_ADDR(p)  (BAR_TSTRORM_INTMEM + 0x1508 + ((p) << 4))
9306 #define BNX2X_PREV_UNDI_RCQ(val)      ((val) & 0xffff)
9307 #define BNX2X_PREV_UNDI_BD(val)       ((val) >> 16 & 0xffff)
9308 #define BNX2X_PREV_UNDI_PROD(rcq, bd) ((bd) << 16 | (rcq))
9309
9310 static void
9311 bnx2x_prev_unload_undi_inc(struct bnx2x_softc *sc, uint8_t port, uint8_t inc)
9312 {
9313         uint16_t rcq, bd;
9314         uint32_t tmp_reg = REG_RD(sc, BNX2X_PREV_UNDI_PROD_ADDR(port));
9315
9316         rcq = BNX2X_PREV_UNDI_RCQ(tmp_reg) + inc;
9317         bd = BNX2X_PREV_UNDI_BD(tmp_reg) + inc;
9318
9319         tmp_reg = BNX2X_PREV_UNDI_PROD(rcq, bd);
9320         REG_WR(sc, BNX2X_PREV_UNDI_PROD_ADDR(port), tmp_reg);
9321 }
9322
9323 static int bnx2x_prev_unload_common(struct bnx2x_softc *sc)
9324 {
9325         uint32_t reset_reg, tmp_reg = 0, rc;
9326         uint8_t prev_undi = FALSE;
9327         struct bnx2x_mac_vals mac_vals;
9328         uint32_t timer_count = 1000;
9329         uint32_t prev_brb;
9330
9331         /*
9332          * It is possible a previous function received 'common' answer,
9333          * but hasn't loaded yet, therefore creating a scenario of
9334          * multiple functions receiving 'common' on the same path.
9335          */
9336         memset(&mac_vals, 0, sizeof(mac_vals));
9337
9338         if (bnx2x_prev_is_path_marked(sc)) {
9339                 return bnx2x_prev_mcp_done(sc);
9340         }
9341
9342         reset_reg = REG_RD(sc, MISC_REG_RESET_REG_1);
9343
9344         /* Reset should be performed after BRB is emptied */
9345         if (reset_reg & MISC_REGISTERS_RESET_REG_1_RST_BRB1) {
9346                 /* Close the MAC Rx to prevent BRB from filling up */
9347                 bnx2x_prev_unload_close_mac(sc, &mac_vals);
9348
9349                 /* close LLH filters towards the BRB */
9350                 elink_set_rx_filter(&sc->link_params, 0);
9351
9352                 /*
9353                  * Check if the UNDI driver was previously loaded.
9354                  * UNDI driver initializes CID offset for normal bell to 0x7
9355                  */
9356                 if (reset_reg & MISC_REGISTERS_RESET_REG_1_RST_DORQ) {
9357                         tmp_reg = REG_RD(sc, DORQ_REG_NORM_CID_OFST);
9358                         if (tmp_reg == 0x7) {
9359                                 PMD_DRV_LOG(DEBUG, sc, "UNDI previously loaded");
9360                                 prev_undi = TRUE;
9361                                 /* clear the UNDI indication */
9362                                 REG_WR(sc, DORQ_REG_NORM_CID_OFST, 0);
9363                                 /* clear possible idle check errors */
9364                                 REG_RD(sc, NIG_REG_NIG_INT_STS_CLR_0);
9365                         }
9366                 }
9367
9368                 /* wait until BRB is empty */
9369                 tmp_reg = REG_RD(sc, BRB1_REG_NUM_OF_FULL_BLOCKS);
9370                 while (timer_count) {
9371                         prev_brb = tmp_reg;
9372
9373                         tmp_reg = REG_RD(sc, BRB1_REG_NUM_OF_FULL_BLOCKS);
9374                         if (!tmp_reg) {
9375                                 break;
9376                         }
9377
9378                         PMD_DRV_LOG(DEBUG, sc, "BRB still has 0x%08x", tmp_reg);
9379
9380                         /* reset timer as long as BRB actually gets emptied */
9381                         if (prev_brb > tmp_reg) {
9382                                 timer_count = 1000;
9383                         } else {
9384                                 timer_count--;
9385                         }
9386
9387                         /* If UNDI resides in memory, manually increment it */
9388                         if (prev_undi) {
9389                                 bnx2x_prev_unload_undi_inc(sc, SC_PORT(sc), 1);
9390                         }
9391
9392                         DELAY(10);
9393                 }
9394
9395                 if (!timer_count) {
9396                         PMD_DRV_LOG(NOTICE, sc, "Failed to empty BRB");
9397                 }
9398         }
9399
9400         /* No packets are in the pipeline, path is ready for reset */
9401         bnx2x_reset_common(sc);
9402
9403         if (mac_vals.xmac_addr) {
9404                 REG_WR(sc, mac_vals.xmac_addr, mac_vals.xmac_val);
9405         }
9406         if (mac_vals.umac_addr) {
9407                 REG_WR(sc, mac_vals.umac_addr, mac_vals.umac_val);
9408         }
9409         if (mac_vals.emac_addr) {
9410                 REG_WR(sc, mac_vals.emac_addr, mac_vals.emac_val);
9411         }
9412         if (mac_vals.bmac_addr) {
9413                 REG_WR(sc, mac_vals.bmac_addr, mac_vals.bmac_val[0]);
9414                 REG_WR(sc, mac_vals.bmac_addr + 4, mac_vals.bmac_val[1]);
9415         }
9416
9417         rc = bnx2x_prev_mark_path(sc, prev_undi);
9418         if (rc) {
9419                 bnx2x_prev_mcp_done(sc);
9420                 return rc;
9421         }
9422
9423         return bnx2x_prev_mcp_done(sc);
9424 }
9425
9426 static int bnx2x_prev_unload_uncommon(struct bnx2x_softc *sc)
9427 {
9428         int rc;
9429
9430         /* Test if previous unload process was already finished for this path */
9431         if (bnx2x_prev_is_path_marked(sc)) {
9432                 return bnx2x_prev_mcp_done(sc);
9433         }
9434
9435         /*
9436          * If function has FLR capabilities, and existing FW version matches
9437          * the one required, then FLR will be sufficient to clean any residue
9438          * left by previous driver
9439          */
9440         rc = bnx2x_nic_load_analyze_req(sc, FW_MSG_CODE_DRV_LOAD_FUNCTION);
9441         if (!rc) {
9442                 /* fw version is good */
9443                 rc = bnx2x_do_flr(sc);
9444         }
9445
9446         if (!rc) {
9447                 /* FLR was performed */
9448                 return 0;
9449         }
9450
9451         PMD_DRV_LOG(INFO, sc, "Could not FLR");
9452
9453         /* Close the MCP request, return failure */
9454         rc = bnx2x_prev_mcp_done(sc);
9455         if (!rc) {
9456                 rc = BNX2X_PREV_WAIT_NEEDED;
9457         }
9458
9459         return rc;
9460 }
9461
9462 static int bnx2x_prev_unload(struct bnx2x_softc *sc)
9463 {
9464         int time_counter = 10;
9465         uint32_t fw, hw_lock_reg, hw_lock_val;
9466         uint32_t rc = 0;
9467
9468         PMD_INIT_FUNC_TRACE(sc);
9469
9470         /*
9471          * Clear HW from errors which may have resulted from an interrupted
9472          * DMAE transaction.
9473          */
9474         bnx2x_prev_interrupted_dmae(sc);
9475
9476         /* Release previously held locks */
9477         hw_lock_reg = (SC_FUNC(sc) <= 5) ?
9478                         (MISC_REG_DRIVER_CONTROL_1 + SC_FUNC(sc) * 8) :
9479                         (MISC_REG_DRIVER_CONTROL_7 + (SC_FUNC(sc) - 6) * 8);
9480
9481         hw_lock_val = (REG_RD(sc, hw_lock_reg));
9482         if (hw_lock_val) {
9483                 if (hw_lock_val & HW_LOCK_RESOURCE_NVRAM) {
9484                         PMD_DRV_LOG(DEBUG, sc, "Releasing previously held NVRAM lock\n");
9485                         REG_WR(sc, MCP_REG_MCPR_NVM_SW_ARB,
9486                                (MCPR_NVM_SW_ARB_ARB_REQ_CLR1 << SC_PORT(sc)));
9487                 }
9488                 PMD_DRV_LOG(DEBUG, sc, "Releasing previously held HW lock\n");
9489                 REG_WR(sc, hw_lock_reg, 0xffffffff);
9490         }
9491
9492         if (MCPR_ACCESS_LOCK_LOCK & REG_RD(sc, MCP_REG_MCPR_ACCESS_LOCK)) {
9493                 PMD_DRV_LOG(DEBUG, sc, "Releasing previously held ALR\n");
9494                 REG_WR(sc, MCP_REG_MCPR_ACCESS_LOCK, 0);
9495         }
9496
9497         do {
9498                 /* Lock MCP using an unload request */
9499                 fw = bnx2x_fw_command(sc, DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS, 0);
9500                 if (!fw) {
9501                         PMD_DRV_LOG(NOTICE, sc, "MCP response failure, aborting");
9502                         rc = -1;
9503                         break;
9504                 }
9505
9506                 if (fw == FW_MSG_CODE_DRV_UNLOAD_COMMON) {
9507                         rc = bnx2x_prev_unload_common(sc);
9508                         break;
9509                 }
9510
9511                 /* non-common reply from MCP might require looping */
9512                 rc = bnx2x_prev_unload_uncommon(sc);
9513                 if (rc != BNX2X_PREV_WAIT_NEEDED) {
9514                         break;
9515                 }
9516
9517                 DELAY(20000);
9518         } while (--time_counter);
9519
9520         if (!time_counter || rc) {
9521                 PMD_DRV_LOG(NOTICE, sc, "Failed to unload previous driver!");
9522                 rc = -1;
9523         }
9524
9525         return rc;
9526 }
9527
9528 static void
9529 bnx2x_dcbx_set_state(struct bnx2x_softc *sc, uint8_t dcb_on, uint32_t dcbx_enabled)
9530 {
9531         if (!CHIP_IS_E1x(sc)) {
9532                 sc->dcb_state = dcb_on;
9533                 sc->dcbx_enabled = dcbx_enabled;
9534         } else {
9535                 sc->dcb_state = FALSE;
9536                 sc->dcbx_enabled = BNX2X_DCBX_ENABLED_INVALID;
9537         }
9538         PMD_DRV_LOG(DEBUG, sc,
9539                     "DCB state [%s:%s]",
9540                     dcb_on ? "ON" : "OFF",
9541                     (dcbx_enabled == BNX2X_DCBX_ENABLED_OFF) ? "user-mode" :
9542                     (dcbx_enabled ==
9543                      BNX2X_DCBX_ENABLED_ON_NEG_OFF) ? "on-chip static"
9544                     : (dcbx_enabled ==
9545                        BNX2X_DCBX_ENABLED_ON_NEG_ON) ?
9546                     "on-chip with negotiation" : "invalid");
9547 }
9548
9549 static int bnx2x_set_qm_cid_count(struct bnx2x_softc *sc)
9550 {
9551         int cid_count = BNX2X_L2_MAX_CID(sc);
9552
9553         if (CNIC_SUPPORT(sc)) {
9554                 cid_count += CNIC_CID_MAX;
9555         }
9556
9557         return roundup(cid_count, QM_CID_ROUND);
9558 }
9559
9560 static void bnx2x_init_multi_cos(struct bnx2x_softc *sc)
9561 {
9562         int pri, cos;
9563
9564         uint32_t pri_map = 0;
9565
9566         for (pri = 0; pri < BNX2X_MAX_PRIORITY; pri++) {
9567                 cos = ((pri_map & (0xf << (pri * 4))) >> (pri * 4));
9568                 if (cos < sc->max_cos) {
9569                         sc->prio_to_cos[pri] = cos;
9570                 } else {
9571                         PMD_DRV_LOG(WARNING, sc,
9572                                     "Invalid COS %d for priority %d "
9573                                     "(max COS is %d), setting to 0", cos, pri,
9574                                     (sc->max_cos - 1));
9575                         sc->prio_to_cos[pri] = 0;
9576                 }
9577         }
9578 }
9579
9580 static int bnx2x_pci_get_caps(struct bnx2x_softc *sc)
9581 {
9582         struct {
9583                 uint8_t id;
9584                 uint8_t next;
9585         } pci_cap;
9586         uint16_t status;
9587         struct bnx2x_pci_cap *cap;
9588
9589         cap = sc->pci_caps = rte_zmalloc("caps", sizeof(struct bnx2x_pci_cap),
9590                                          RTE_CACHE_LINE_SIZE);
9591         if (!cap) {
9592                 PMD_DRV_LOG(NOTICE, sc, "Failed to allocate memory");
9593                 return -ENOMEM;
9594         }
9595
9596 #ifndef RTE_EXEC_ENV_FREEBSD
9597         pci_read(sc, PCI_STATUS, &status, 2);
9598         if (!(status & PCI_STATUS_CAP_LIST)) {
9599 #else
9600         pci_read(sc, PCIR_STATUS, &status, 2);
9601         if (!(status & PCIM_STATUS_CAPPRESENT)) {
9602 #endif
9603                 PMD_DRV_LOG(NOTICE, sc, "PCIe capability reading failed");
9604                 return -1;
9605         }
9606
9607 #ifndef RTE_EXEC_ENV_FREEBSD
9608         pci_read(sc, PCI_CAPABILITY_LIST, &pci_cap.next, 1);
9609 #else
9610         pci_read(sc, PCIR_CAP_PTR, &pci_cap.next, 1);
9611 #endif
9612         while (pci_cap.next) {
9613                 cap->addr = pci_cap.next & ~3;
9614                 pci_read(sc, pci_cap.next & ~3, &pci_cap, 2);
9615                 if (pci_cap.id == 0xff)
9616                         break;
9617                 cap->id = pci_cap.id;
9618                 cap->type = BNX2X_PCI_CAP;
9619                 cap->next = rte_zmalloc("pci_cap",
9620                                         sizeof(struct bnx2x_pci_cap),
9621                                         RTE_CACHE_LINE_SIZE);
9622                 if (!cap->next) {
9623                         PMD_DRV_LOG(NOTICE, sc, "Failed to allocate memory");
9624                         return -ENOMEM;
9625                 }
9626                 cap = cap->next;
9627         }
9628
9629         return 0;
9630 }
9631
9632 static void bnx2x_init_rte(struct bnx2x_softc *sc)
9633 {
9634         if (IS_VF(sc)) {
9635                 sc->max_tx_queues = min(BNX2X_VF_MAX_QUEUES_PER_VF,
9636                                         sc->igu_sb_cnt);
9637                 sc->max_rx_queues = min(BNX2X_VF_MAX_QUEUES_PER_VF,
9638                                         sc->igu_sb_cnt);
9639         } else {
9640                 sc->max_rx_queues = BNX2X_MAX_RSS_COUNT(sc);
9641                 sc->max_tx_queues = sc->max_rx_queues;
9642         }
9643 }
9644
9645 #define FW_HEADER_LEN 104
9646 #define FW_NAME_57711 "/lib/firmware/bnx2x/bnx2x-e1h-7.13.11.0.fw"
9647 #define FW_NAME_57810 "/lib/firmware/bnx2x/bnx2x-e2-7.13.11.0.fw"
9648
9649 void bnx2x_load_firmware(struct bnx2x_softc *sc)
9650 {
9651         const char *fwname;
9652         int f;
9653         struct stat st;
9654
9655         fwname = sc->devinfo.device_id == CHIP_NUM_57711
9656                 ? FW_NAME_57711 : FW_NAME_57810;
9657         f = open(fwname, O_RDONLY);
9658         if (f < 0) {
9659                 PMD_DRV_LOG(NOTICE, sc, "Can't open firmware file");
9660                 return;
9661         }
9662
9663         if (fstat(f, &st) < 0) {
9664                 PMD_DRV_LOG(NOTICE, sc, "Can't stat firmware file");
9665                 close(f);
9666                 return;
9667         }
9668
9669         sc->firmware = rte_zmalloc("bnx2x_fw", st.st_size, RTE_CACHE_LINE_SIZE);
9670         if (!sc->firmware) {
9671                 PMD_DRV_LOG(NOTICE, sc, "Can't allocate memory for firmware");
9672                 close(f);
9673                 return;
9674         }
9675
9676         if (read(f, sc->firmware, st.st_size) != st.st_size) {
9677                 PMD_DRV_LOG(NOTICE, sc, "Can't read firmware data");
9678                 close(f);
9679                 return;
9680         }
9681         close(f);
9682
9683         sc->fw_len = st.st_size;
9684         if (sc->fw_len < FW_HEADER_LEN) {
9685                 PMD_DRV_LOG(NOTICE, sc,
9686                             "Invalid fw size: %" PRIu64, sc->fw_len);
9687                 return;
9688         }
9689         PMD_DRV_LOG(DEBUG, sc, "fw_len = %" PRIu64, sc->fw_len);
9690 }
9691
9692 static void
9693 bnx2x_data_to_init_ops(uint8_t * data, struct raw_op *dst, uint32_t len)
9694 {
9695         uint32_t *src = (uint32_t *) data;
9696         uint32_t i, j, tmp;
9697
9698         for (i = 0, j = 0; i < len / 8; ++i, j += 2) {
9699                 tmp = rte_be_to_cpu_32(src[j]);
9700                 dst[i].op = (tmp >> 24) & 0xFF;
9701                 dst[i].offset = tmp & 0xFFFFFF;
9702                 dst[i].raw_data = rte_be_to_cpu_32(src[j + 1]);
9703         }
9704 }
9705
9706 static void
9707 bnx2x_data_to_init_offsets(uint8_t * data, uint16_t * dst, uint32_t len)
9708 {
9709         uint16_t *src = (uint16_t *) data;
9710         uint32_t i;
9711
9712         for (i = 0; i < len / 2; ++i)
9713                 dst[i] = rte_be_to_cpu_16(src[i]);
9714 }
9715
9716 static void bnx2x_data_to_init_data(uint8_t * data, uint32_t * dst, uint32_t len)
9717 {
9718         uint32_t *src = (uint32_t *) data;
9719         uint32_t i;
9720
9721         for (i = 0; i < len / 4; ++i)
9722                 dst[i] = rte_be_to_cpu_32(src[i]);
9723 }
9724
9725 static void bnx2x_data_to_iro_array(uint8_t * data, struct iro *dst, uint32_t len)
9726 {
9727         uint32_t *src = (uint32_t *) data;
9728         uint32_t i, j, tmp;
9729
9730         for (i = 0, j = 0; i < len / sizeof(struct iro); ++i, ++j) {
9731                 dst[i].base = rte_be_to_cpu_32(src[j++]);
9732                 tmp = rte_be_to_cpu_32(src[j]);
9733                 dst[i].m1 = (tmp >> 16) & 0xFFFF;
9734                 dst[i].m2 = tmp & 0xFFFF;
9735                 ++j;
9736                 tmp = rte_be_to_cpu_32(src[j]);
9737                 dst[i].m3 = (tmp >> 16) & 0xFFFF;
9738                 dst[i].size = tmp & 0xFFFF;
9739         }
9740 }
9741
9742 /*
9743 * Device attach function.
9744 *
9745 * Allocates device resources, performs secondary chip identification, and
9746 * initializes driver instance variables. This function is called from driver
9747 * load after a successful probe.
9748 *
9749 * Returns:
9750 *   0 = Success, >0 = Failure
9751 */
9752 int bnx2x_attach(struct bnx2x_softc *sc)
9753 {
9754         int rc;
9755
9756         PMD_DRV_LOG(DEBUG, sc, "Starting attach...");
9757
9758         rc = bnx2x_pci_get_caps(sc);
9759         if (rc) {
9760                 PMD_DRV_LOG(NOTICE, sc, "PCIe caps reading was failed");
9761                 return rc;
9762         }
9763
9764         sc->state = BNX2X_STATE_CLOSED;
9765
9766         pci_write_long(sc, PCICFG_GRC_ADDRESS, PCICFG_VENDOR_ID_OFFSET);
9767
9768         sc->igu_base_addr = IS_VF(sc) ? PXP_VF_ADDR_IGU_START : BAR_IGU_INTMEM;
9769
9770         /* get PCI capabilites */
9771         bnx2x_probe_pci_caps(sc);
9772
9773         if (sc->devinfo.pcie_msix_cap_reg != 0) {
9774                 uint32_t val;
9775                 pci_read(sc,
9776                          (sc->devinfo.pcie_msix_cap_reg + PCIR_MSIX_CTRL), &val,
9777                          2);
9778                 sc->igu_sb_cnt = (val & PCIM_MSIXCTRL_TABLE_SIZE) + 1;
9779         } else {
9780                 sc->igu_sb_cnt = 1;
9781         }
9782
9783         /* Init RTE stuff */
9784         bnx2x_init_rte(sc);
9785
9786         if (IS_PF(sc)) {
9787                 /* Enable internal target-read (in case we are probed after PF
9788                  * FLR). Must be done prior to any BAR read access. Only for
9789                  * 57712 and up
9790                  */
9791                 if (!CHIP_IS_E1x(sc)) {
9792                         REG_WR(sc, PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_READ,
9793                                1);
9794                         DELAY(200000);
9795                 }
9796
9797                 /* get device info and set params */
9798                 if (bnx2x_get_device_info(sc) != 0) {
9799                         PMD_DRV_LOG(NOTICE, sc, "getting device info");
9800                         return -ENXIO;
9801                 }
9802
9803 /* get phy settings from shmem and 'and' against admin settings */
9804                 bnx2x_get_phy_info(sc);
9805         } else {
9806                 /* Left mac of VF unfilled, PF should set it for VF */
9807                 memset(sc->link_params.mac_addr, 0, RTE_ETHER_ADDR_LEN);
9808         }
9809
9810         sc->wol = 0;
9811
9812         /* set the default MTU (changed via ifconfig) */
9813         sc->mtu = RTE_ETHER_MTU;
9814
9815         bnx2x_set_modes_bitmap(sc);
9816
9817         /* need to reset chip if UNDI was active */
9818         if (IS_PF(sc) && !BNX2X_NOMCP(sc)) {
9819 /* init fw_seq */
9820                 sc->fw_seq =
9821                     (SHMEM_RD(sc, func_mb[SC_FW_MB_IDX(sc)].drv_mb_header) &
9822                      DRV_MSG_SEQ_NUMBER_MASK);
9823                 PMD_DRV_LOG(DEBUG, sc, "prev unload fw_seq 0x%04x",
9824                             sc->fw_seq);
9825                 bnx2x_prev_unload(sc);
9826         }
9827
9828         bnx2x_dcbx_set_state(sc, FALSE, BNX2X_DCBX_ENABLED_OFF);
9829
9830         /* calculate qm_cid_count */
9831         sc->qm_cid_count = bnx2x_set_qm_cid_count(sc);
9832
9833         sc->max_cos = 1;
9834         bnx2x_init_multi_cos(sc);
9835
9836         return 0;
9837 }
9838
9839 static void
9840 bnx2x_igu_ack_sb(struct bnx2x_softc *sc, uint8_t igu_sb_id, uint8_t segment,
9841                uint16_t index, uint8_t op, uint8_t update)
9842 {
9843         uint32_t igu_addr = sc->igu_base_addr;
9844         igu_addr += (IGU_CMD_INT_ACK_BASE + igu_sb_id) * 8;
9845         bnx2x_igu_ack_sb_gen(sc, segment, index, op, update, igu_addr);
9846 }
9847
9848 static void
9849 bnx2x_ack_sb(struct bnx2x_softc *sc, uint8_t igu_sb_id, uint8_t storm,
9850            uint16_t index, uint8_t op, uint8_t update)
9851 {
9852         if (unlikely(sc->devinfo.int_block == INT_BLOCK_HC))
9853                 bnx2x_hc_ack_sb(sc, igu_sb_id, storm, index, op, update);
9854         else {
9855                 uint8_t segment;
9856                 if (CHIP_INT_MODE_IS_BC(sc)) {
9857                         segment = storm;
9858                 } else if (igu_sb_id != sc->igu_dsb_id) {
9859                         segment = IGU_SEG_ACCESS_DEF;
9860                 } else if (storm == ATTENTION_ID) {
9861                         segment = IGU_SEG_ACCESS_ATTN;
9862                 } else {
9863                         segment = IGU_SEG_ACCESS_DEF;
9864                 }
9865                 bnx2x_igu_ack_sb(sc, igu_sb_id, segment, index, op, update);
9866         }
9867 }
9868
9869 static void
9870 bnx2x_igu_clear_sb_gen(struct bnx2x_softc *sc, uint8_t func, uint8_t idu_sb_id,
9871                      uint8_t is_pf)
9872 {
9873         uint32_t data, ctl, cnt = 100;
9874         uint32_t igu_addr_data = IGU_REG_COMMAND_REG_32LSB_DATA;
9875         uint32_t igu_addr_ctl = IGU_REG_COMMAND_REG_CTRL;
9876         uint32_t igu_addr_ack = IGU_REG_CSTORM_TYPE_0_SB_CLEANUP +
9877             (idu_sb_id / 32) * 4;
9878         uint32_t sb_bit = 1 << (idu_sb_id % 32);
9879         uint32_t func_encode = func |
9880             (is_pf ? 1 : 0) << IGU_FID_ENCODE_IS_PF_SHIFT;
9881         uint32_t addr_encode = IGU_CMD_E2_PROD_UPD_BASE + idu_sb_id;
9882
9883         /* Not supported in BC mode */
9884         if (CHIP_INT_MODE_IS_BC(sc)) {
9885                 return;
9886         }
9887
9888         data = ((IGU_USE_REGISTER_cstorm_type_0_sb_cleanup <<
9889                  IGU_REGULAR_CLEANUP_TYPE_SHIFT) |
9890                 IGU_REGULAR_CLEANUP_SET | IGU_REGULAR_BCLEANUP);
9891
9892         ctl = ((addr_encode << IGU_CTRL_REG_ADDRESS_SHIFT) |
9893                (func_encode << IGU_CTRL_REG_FID_SHIFT) |
9894                (IGU_CTRL_CMD_TYPE_WR << IGU_CTRL_REG_TYPE_SHIFT));
9895
9896         REG_WR(sc, igu_addr_data, data);
9897
9898         mb();
9899
9900         PMD_DRV_LOG(DEBUG, sc, "write 0x%08x to IGU(via GRC) addr 0x%x",
9901                     ctl, igu_addr_ctl);
9902         REG_WR(sc, igu_addr_ctl, ctl);
9903
9904         mb();
9905
9906         /* wait for clean up to finish */
9907         while (!(REG_RD(sc, igu_addr_ack) & sb_bit) && --cnt) {
9908                 DELAY(20000);
9909         }
9910
9911         if (!(REG_RD(sc, igu_addr_ack) & sb_bit)) {
9912                 PMD_DRV_LOG(DEBUG, sc,
9913                             "Unable to finish IGU cleanup: "
9914                             "idu_sb_id %d offset %d bit %d (cnt %d)",
9915                             idu_sb_id, idu_sb_id / 32, idu_sb_id % 32, cnt);
9916         }
9917 }
9918
9919 static void bnx2x_igu_clear_sb(struct bnx2x_softc *sc, uint8_t idu_sb_id)
9920 {
9921         bnx2x_igu_clear_sb_gen(sc, SC_FUNC(sc), idu_sb_id, TRUE /*PF*/);
9922 }
9923
9924 /*******************/
9925 /* ECORE CALLBACKS */
9926 /*******************/
9927
9928 static void bnx2x_reset_common(struct bnx2x_softc *sc)
9929 {
9930         uint32_t val = 0x1400;
9931
9932         PMD_INIT_FUNC_TRACE(sc);
9933
9934         /* reset_common */
9935         REG_WR(sc, (GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR),
9936                0xd3ffff7f);
9937
9938         if (CHIP_IS_E3(sc)) {
9939                 val |= MISC_REGISTERS_RESET_REG_2_MSTAT0;
9940                 val |= MISC_REGISTERS_RESET_REG_2_MSTAT1;
9941         }
9942
9943         REG_WR(sc, (GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR), val);
9944 }
9945
9946 static void bnx2x_common_init_phy(struct bnx2x_softc *sc)
9947 {
9948         uint32_t shmem_base[2];
9949         uint32_t shmem2_base[2];
9950
9951         /* Avoid common init in case MFW supports LFA */
9952         if (SHMEM2_RD(sc, size) >
9953             (uint32_t) offsetof(struct shmem2_region,
9954                                 lfa_host_addr[SC_PORT(sc)])) {
9955                 return;
9956         }
9957
9958         shmem_base[0] = sc->devinfo.shmem_base;
9959         shmem2_base[0] = sc->devinfo.shmem2_base;
9960
9961         if (!CHIP_IS_E1x(sc)) {
9962                 shmem_base[1] = SHMEM2_RD(sc, other_shmem_base_addr);
9963                 shmem2_base[1] = SHMEM2_RD(sc, other_shmem2_base_addr);
9964         }
9965
9966         bnx2x_acquire_phy_lock(sc);
9967         elink_common_init_phy(sc, shmem_base, shmem2_base,
9968                               sc->devinfo.chip_id, 0);
9969         bnx2x_release_phy_lock(sc);
9970 }
9971
9972 static void bnx2x_pf_disable(struct bnx2x_softc *sc)
9973 {
9974         uint32_t val = REG_RD(sc, IGU_REG_PF_CONFIGURATION);
9975
9976         val &= ~IGU_PF_CONF_FUNC_EN;
9977
9978         REG_WR(sc, IGU_REG_PF_CONFIGURATION, val);
9979         REG_WR(sc, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 0);
9980         REG_WR(sc, CFC_REG_WEAK_ENABLE_PF, 0);
9981 }
9982
9983 static void bnx2x_init_pxp(struct bnx2x_softc *sc)
9984 {
9985         uint16_t devctl;
9986         int r_order, w_order;
9987
9988         devctl = bnx2x_pcie_capability_read(sc, PCIR_EXPRESS_DEVICE_CTL);
9989
9990         w_order = ((devctl & PCIM_EXP_CTL_MAX_PAYLOAD) >> 5);
9991         r_order = ((devctl & PCIM_EXP_CTL_MAX_READ_REQUEST) >> 12);
9992
9993         ecore_init_pxp_arb(sc, r_order, w_order);
9994 }
9995
9996 static uint32_t bnx2x_get_pretend_reg(struct bnx2x_softc *sc)
9997 {
9998         uint32_t base = PXP2_REG_PGL_PRETEND_FUNC_F0;
9999         uint32_t stride = (PXP2_REG_PGL_PRETEND_FUNC_F1 - base);
10000         return base + (SC_ABS_FUNC(sc)) * stride;
10001 }
10002
10003 /*
10004  * Called only on E1H or E2.
10005  * When pretending to be PF, the pretend value is the function number 0..7.
10006  * When pretending to be VF, the pretend val is the PF-num:VF-valid:ABS-VFID
10007  * combination.
10008  */
10009 static int bnx2x_pretend_func(struct bnx2x_softc *sc, uint16_t pretend_func_val)
10010 {
10011         uint32_t pretend_reg;
10012
10013         if (CHIP_IS_E1H(sc) && (pretend_func_val > E1H_FUNC_MAX))
10014                 return -1;
10015
10016         /* get my own pretend register */
10017         pretend_reg = bnx2x_get_pretend_reg(sc);
10018         REG_WR(sc, pretend_reg, pretend_func_val);
10019         REG_RD(sc, pretend_reg);
10020         return 0;
10021 }
10022
10023 static void bnx2x_setup_fan_failure_detection(struct bnx2x_softc *sc)
10024 {
10025         int is_required;
10026         uint32_t val;
10027         int port;
10028
10029         is_required = 0;
10030         val = (SHMEM_RD(sc, dev_info.shared_hw_config.config2) &
10031                SHARED_HW_CFG_FAN_FAILURE_MASK);
10032
10033         if (val == SHARED_HW_CFG_FAN_FAILURE_ENABLED) {
10034                 is_required = 1;
10035         }
10036         /*
10037          * The fan failure mechanism is usually related to the PHY type since
10038          * the power consumption of the board is affected by the PHY. Currently,
10039          * fan is required for most designs with SFX7101, BNX2X8727 and BNX2X8481.
10040          */
10041         else if (val == SHARED_HW_CFG_FAN_FAILURE_PHY_TYPE) {
10042                 for (port = PORT_0; port < PORT_MAX; port++) {
10043                         is_required |= elink_fan_failure_det_req(sc,
10044                                                                  sc->
10045                                                                  devinfo.shmem_base,
10046                                                                  sc->
10047                                                                  devinfo.shmem2_base,
10048                                                                  port);
10049                 }
10050         }
10051
10052         if (is_required == 0) {
10053                 return;
10054         }
10055
10056         /* Fan failure is indicated by SPIO 5 */
10057         bnx2x_set_spio(sc, MISC_SPIO_SPIO5, MISC_SPIO_INPUT_HI_Z);
10058
10059         /* set to active low mode */
10060         val = REG_RD(sc, MISC_REG_SPIO_INT);
10061         val |= (MISC_SPIO_SPIO5 << MISC_SPIO_INT_OLD_SET_POS);
10062         REG_WR(sc, MISC_REG_SPIO_INT, val);
10063
10064         /* enable interrupt to signal the IGU */
10065         val = REG_RD(sc, MISC_REG_SPIO_EVENT_EN);
10066         val |= MISC_SPIO_SPIO5;
10067         REG_WR(sc, MISC_REG_SPIO_EVENT_EN, val);
10068 }
10069
10070 static void bnx2x_enable_blocks_attention(struct bnx2x_softc *sc)
10071 {
10072         uint32_t val;
10073
10074         REG_WR(sc, PXP_REG_PXP_INT_MASK_0, 0);
10075         if (!CHIP_IS_E1x(sc)) {
10076                 REG_WR(sc, PXP_REG_PXP_INT_MASK_1, 0x40);
10077         } else {
10078                 REG_WR(sc, PXP_REG_PXP_INT_MASK_1, 0);
10079         }
10080         REG_WR(sc, DORQ_REG_DORQ_INT_MASK, 0);
10081         REG_WR(sc, CFC_REG_CFC_INT_MASK, 0);
10082         /*
10083          * mask read length error interrupts in brb for parser
10084          * (parsing unit and 'checksum and crc' unit)
10085          * these errors are legal (PU reads fixed length and CAC can cause
10086          * read length error on truncated packets)
10087          */
10088         REG_WR(sc, BRB1_REG_BRB1_INT_MASK, 0xFC00);
10089         REG_WR(sc, QM_REG_QM_INT_MASK, 0);
10090         REG_WR(sc, TM_REG_TM_INT_MASK, 0);
10091         REG_WR(sc, XSDM_REG_XSDM_INT_MASK_0, 0);
10092         REG_WR(sc, XSDM_REG_XSDM_INT_MASK_1, 0);
10093         REG_WR(sc, XCM_REG_XCM_INT_MASK, 0);
10094         /*      REG_WR(sc, XSEM_REG_XSEM_INT_MASK_0, 0); */
10095         /*      REG_WR(sc, XSEM_REG_XSEM_INT_MASK_1, 0); */
10096         REG_WR(sc, USDM_REG_USDM_INT_MASK_0, 0);
10097         REG_WR(sc, USDM_REG_USDM_INT_MASK_1, 0);
10098         REG_WR(sc, UCM_REG_UCM_INT_MASK, 0);
10099         /*      REG_WR(sc, USEM_REG_USEM_INT_MASK_0, 0); */
10100         /*      REG_WR(sc, USEM_REG_USEM_INT_MASK_1, 0); */
10101         REG_WR(sc, GRCBASE_UPB + PB_REG_PB_INT_MASK, 0);
10102         REG_WR(sc, CSDM_REG_CSDM_INT_MASK_0, 0);
10103         REG_WR(sc, CSDM_REG_CSDM_INT_MASK_1, 0);
10104         REG_WR(sc, CCM_REG_CCM_INT_MASK, 0);
10105         /*      REG_WR(sc, CSEM_REG_CSEM_INT_MASK_0, 0); */
10106         /*      REG_WR(sc, CSEM_REG_CSEM_INT_MASK_1, 0); */
10107
10108         val = (PXP2_PXP2_INT_MASK_0_REG_PGL_CPL_AFT |
10109                PXP2_PXP2_INT_MASK_0_REG_PGL_CPL_OF |
10110                PXP2_PXP2_INT_MASK_0_REG_PGL_PCIE_ATTN);
10111         if (!CHIP_IS_E1x(sc)) {
10112                 val |= (PXP2_PXP2_INT_MASK_0_REG_PGL_READ_BLOCKED |
10113                         PXP2_PXP2_INT_MASK_0_REG_PGL_WRITE_BLOCKED);
10114         }
10115         REG_WR(sc, PXP2_REG_PXP2_INT_MASK_0, val);
10116
10117         REG_WR(sc, TSDM_REG_TSDM_INT_MASK_0, 0);
10118         REG_WR(sc, TSDM_REG_TSDM_INT_MASK_1, 0);
10119         REG_WR(sc, TCM_REG_TCM_INT_MASK, 0);
10120         /*      REG_WR(sc, TSEM_REG_TSEM_INT_MASK_0, 0); */
10121
10122         if (!CHIP_IS_E1x(sc)) {
10123 /* enable VFC attentions: bits 11 and 12, bits 31:13 reserved */
10124                 REG_WR(sc, TSEM_REG_TSEM_INT_MASK_1, 0x07ff);
10125         }
10126
10127         REG_WR(sc, CDU_REG_CDU_INT_MASK, 0);
10128         REG_WR(sc, DMAE_REG_DMAE_INT_MASK, 0);
10129         /*      REG_WR(sc, MISC_REG_MISC_INT_MASK, 0); */
10130         REG_WR(sc, PBF_REG_PBF_INT_MASK, 0x18); /* bit 3,4 masked */
10131 }
10132
10133 /**
10134  * bnx2x_init_hw_common - initialize the HW at the COMMON phase.
10135  *
10136  * @sc:     driver handle
10137  */
10138 static int bnx2x_init_hw_common(struct bnx2x_softc *sc)
10139 {
10140         uint8_t abs_func_id;
10141         uint32_t val;
10142
10143         PMD_DRV_LOG(DEBUG, sc,
10144                     "starting common init for func %d", SC_ABS_FUNC(sc));
10145
10146         /*
10147          * take the RESET lock to protect undi_unload flow from accessing
10148          * registers while we are resetting the chip
10149          */
10150         bnx2x_acquire_hw_lock(sc, HW_LOCK_RESOURCE_RESET);
10151
10152         bnx2x_reset_common(sc);
10153
10154         REG_WR(sc, (GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET), 0xffffffff);
10155
10156         val = 0xfffc;
10157         if (CHIP_IS_E3(sc)) {
10158                 val |= MISC_REGISTERS_RESET_REG_2_MSTAT0;
10159                 val |= MISC_REGISTERS_RESET_REG_2_MSTAT1;
10160         }
10161
10162         REG_WR(sc, (GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET), val);
10163
10164         bnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_RESET);
10165
10166         ecore_init_block(sc, BLOCK_MISC, PHASE_COMMON);
10167
10168         if (!CHIP_IS_E1x(sc)) {
10169 /*
10170  * 4-port mode or 2-port mode we need to turn off master-enable for
10171  * everyone. After that we turn it back on for self. So, we disregard
10172  * multi-function, and always disable all functions on the given path,
10173  * this means 0,2,4,6 for path 0 and 1,3,5,7 for path 1
10174  */
10175                 for (abs_func_id = SC_PATH(sc);
10176                      abs_func_id < (E2_FUNC_MAX * 2); abs_func_id += 2) {
10177                         if (abs_func_id == SC_ABS_FUNC(sc)) {
10178                                 REG_WR(sc,
10179                                        PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER,
10180                                        1);
10181                                 continue;
10182                         }
10183
10184                         bnx2x_pretend_func(sc, abs_func_id);
10185
10186                         /* clear pf enable */
10187                         bnx2x_pf_disable(sc);
10188
10189                         bnx2x_pretend_func(sc, SC_ABS_FUNC(sc));
10190                 }
10191         }
10192
10193         ecore_init_block(sc, BLOCK_PXP, PHASE_COMMON);
10194
10195         ecore_init_block(sc, BLOCK_PXP2, PHASE_COMMON);
10196         bnx2x_init_pxp(sc);
10197
10198 #ifdef __BIG_ENDIAN
10199         REG_WR(sc, PXP2_REG_RQ_QM_ENDIAN_M, 1);
10200         REG_WR(sc, PXP2_REG_RQ_TM_ENDIAN_M, 1);
10201         REG_WR(sc, PXP2_REG_RQ_SRC_ENDIAN_M, 1);
10202         REG_WR(sc, PXP2_REG_RQ_CDU_ENDIAN_M, 1);
10203         REG_WR(sc, PXP2_REG_RQ_DBG_ENDIAN_M, 1);
10204         /* make sure this value is 0 */
10205         REG_WR(sc, PXP2_REG_RQ_HC_ENDIAN_M, 0);
10206
10207         //REG_WR(sc, PXP2_REG_RD_PBF_SWAP_MODE, 1);
10208         REG_WR(sc, PXP2_REG_RD_QM_SWAP_MODE, 1);
10209         REG_WR(sc, PXP2_REG_RD_TM_SWAP_MODE, 1);
10210         REG_WR(sc, PXP2_REG_RD_SRC_SWAP_MODE, 1);
10211         REG_WR(sc, PXP2_REG_RD_CDURD_SWAP_MODE, 1);
10212 #endif
10213
10214         ecore_ilt_init_page_size(sc, INITOP_SET);
10215
10216         if (CHIP_REV_IS_FPGA(sc) && CHIP_IS_E1H(sc)) {
10217                 REG_WR(sc, PXP2_REG_PGL_TAGS_LIMIT, 0x1);
10218         }
10219
10220         /* let the HW do it's magic... */
10221         DELAY(100000);
10222
10223         /* finish PXP init */
10224
10225         val = REG_RD(sc, PXP2_REG_RQ_CFG_DONE);
10226         if (val != 1) {
10227                 PMD_DRV_LOG(NOTICE, sc, "PXP2 CFG failed");
10228                 return -1;
10229         }
10230         val = REG_RD(sc, PXP2_REG_RD_INIT_DONE);
10231         if (val != 1) {
10232                 PMD_DRV_LOG(NOTICE, sc, "PXP2 RD_INIT failed");
10233                 return -1;
10234         }
10235
10236         /*
10237          * Timer bug workaround for E2 only. We need to set the entire ILT to have
10238          * entries with value "0" and valid bit on. This needs to be done by the
10239          * first PF that is loaded in a path (i.e. common phase)
10240          */
10241         if (!CHIP_IS_E1x(sc)) {
10242 /*
10243  * In E2 there is a bug in the timers block that can cause function 6 / 7
10244  * (i.e. vnic3) to start even if it is marked as "scan-off".
10245  * This occurs when a different function (func2,3) is being marked
10246  * as "scan-off". Real-life scenario for example: if a driver is being
10247  * load-unloaded while func6,7 are down. This will cause the timer to access
10248  * the ilt, translate to a logical address and send a request to read/write.
10249  * Since the ilt for the function that is down is not valid, this will cause
10250  * a translation error which is unrecoverable.
10251  * The Workaround is intended to make sure that when this happens nothing
10252  * fatal will occur. The workaround:
10253  *  1.  First PF driver which loads on a path will:
10254  *      a.  After taking the chip out of reset, by using pretend,
10255  *          it will write "0" to the following registers of
10256  *          the other vnics.
10257  *          REG_WR(pdev, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 0);
10258  *          REG_WR(pdev, CFC_REG_WEAK_ENABLE_PF,0);
10259  *          REG_WR(pdev, CFC_REG_STRONG_ENABLE_PF,0);
10260  *          And for itself it will write '1' to
10261  *          PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER to enable
10262  *          dmae-operations (writing to pram for example.)
10263  *          note: can be done for only function 6,7 but cleaner this
10264  *            way.
10265  *      b.  Write zero+valid to the entire ILT.
10266  *      c.  Init the first_timers_ilt_entry, last_timers_ilt_entry of
10267  *          VNIC3 (of that port). The range allocated will be the
10268  *          entire ILT. This is needed to prevent  ILT range error.
10269  *  2.  Any PF driver load flow:
10270  *      a.  ILT update with the physical addresses of the allocated
10271  *          logical pages.
10272  *      b.  Wait 20msec. - note that this timeout is needed to make
10273  *          sure there are no requests in one of the PXP internal
10274  *          queues with "old" ILT addresses.
10275  *      c.  PF enable in the PGLC.
10276  *      d.  Clear the was_error of the PF in the PGLC. (could have
10277  *          occurred while driver was down)
10278  *      e.  PF enable in the CFC (WEAK + STRONG)
10279  *      f.  Timers scan enable
10280  *  3.  PF driver unload flow:
10281  *      a.  Clear the Timers scan_en.
10282  *      b.  Polling for scan_on=0 for that PF.
10283  *      c.  Clear the PF enable bit in the PXP.
10284  *      d.  Clear the PF enable in the CFC (WEAK + STRONG)
10285  *      e.  Write zero+valid to all ILT entries (The valid bit must
10286  *          stay set)
10287  *      f.  If this is VNIC 3 of a port then also init
10288  *          first_timers_ilt_entry to zero and last_timers_ilt_entry
10289  *          to the last enrty in the ILT.
10290  *
10291  *      Notes:
10292  *      Currently the PF error in the PGLC is non recoverable.
10293  *      In the future the there will be a recovery routine for this error.
10294  *      Currently attention is masked.
10295  *      Having an MCP lock on the load/unload process does not guarantee that
10296  *      there is no Timer disable during Func6/7 enable. This is because the
10297  *      Timers scan is currently being cleared by the MCP on FLR.
10298  *      Step 2.d can be done only for PF6/7 and the driver can also check if
10299  *      there is error before clearing it. But the flow above is simpler and
10300  *      more general.
10301  *      All ILT entries are written by zero+valid and not just PF6/7
10302  *      ILT entries since in the future the ILT entries allocation for
10303  *      PF-s might be dynamic.
10304  */
10305                 struct ilt_client_info ilt_cli;
10306                 struct ecore_ilt ilt;
10307
10308                 memset(&ilt_cli, 0, sizeof(struct ilt_client_info));
10309                 memset(&ilt, 0, sizeof(struct ecore_ilt));
10310
10311 /* initialize dummy TM client */
10312                 ilt_cli.start = 0;
10313                 ilt_cli.end = ILT_NUM_PAGE_ENTRIES - 1;
10314                 ilt_cli.client_num = ILT_CLIENT_TM;
10315
10316 /*
10317  * Step 1: set zeroes to all ilt page entries with valid bit on
10318  * Step 2: set the timers first/last ilt entry to point
10319  * to the entire range to prevent ILT range error for 3rd/4th
10320  * vnic (this code assumes existence of the vnic)
10321  *
10322  * both steps performed by call to ecore_ilt_client_init_op()
10323  * with dummy TM client
10324  *
10325  * we must use pretend since PXP2_REG_RQ_##blk##_FIRST_ILT
10326  * and his brother are split registers
10327  */
10328
10329                 bnx2x_pretend_func(sc, (SC_PATH(sc) + 6));
10330                 ecore_ilt_client_init_op_ilt(sc, &ilt, &ilt_cli, INITOP_CLEAR);
10331                 bnx2x_pretend_func(sc, SC_ABS_FUNC(sc));
10332
10333                 REG_WR(sc, PXP2_REG_RQ_DRAM_ALIGN, BNX2X_PXP_DRAM_ALIGN);
10334                 REG_WR(sc, PXP2_REG_RQ_DRAM_ALIGN_RD, BNX2X_PXP_DRAM_ALIGN);
10335                 REG_WR(sc, PXP2_REG_RQ_DRAM_ALIGN_SEL, 1);
10336         }
10337
10338         REG_WR(sc, PXP2_REG_RQ_DISABLE_INPUTS, 0);
10339         REG_WR(sc, PXP2_REG_RD_DISABLE_INPUTS, 0);
10340
10341         if (!CHIP_IS_E1x(sc)) {
10342                 int factor = 0;
10343
10344                 ecore_init_block(sc, BLOCK_PGLUE_B, PHASE_COMMON);
10345                 ecore_init_block(sc, BLOCK_ATC, PHASE_COMMON);
10346
10347 /* let the HW do it's magic... */
10348                 do {
10349                         DELAY(200000);
10350                         val = REG_RD(sc, ATC_REG_ATC_INIT_DONE);
10351                 } while (factor-- && (val != 1));
10352
10353                 if (val != 1) {
10354                         PMD_DRV_LOG(NOTICE, sc, "ATC_INIT failed");
10355                         return -1;
10356                 }
10357         }
10358
10359         ecore_init_block(sc, BLOCK_DMAE, PHASE_COMMON);
10360
10361         /* clean the DMAE memory */
10362         sc->dmae_ready = 1;
10363         ecore_init_fill(sc, TSEM_REG_PRAM, 0, 8, 1);
10364
10365         ecore_init_block(sc, BLOCK_TCM, PHASE_COMMON);
10366
10367         ecore_init_block(sc, BLOCK_UCM, PHASE_COMMON);
10368
10369         ecore_init_block(sc, BLOCK_CCM, PHASE_COMMON);
10370
10371         ecore_init_block(sc, BLOCK_XCM, PHASE_COMMON);
10372
10373         bnx2x_read_dmae(sc, XSEM_REG_PASSIVE_BUFFER, 3);
10374         bnx2x_read_dmae(sc, CSEM_REG_PASSIVE_BUFFER, 3);
10375         bnx2x_read_dmae(sc, TSEM_REG_PASSIVE_BUFFER, 3);
10376         bnx2x_read_dmae(sc, USEM_REG_PASSIVE_BUFFER, 3);
10377
10378         ecore_init_block(sc, BLOCK_QM, PHASE_COMMON);
10379
10380         /* QM queues pointers table */
10381         ecore_qm_init_ptr_table(sc, sc->qm_cid_count, INITOP_SET);
10382
10383         /* soft reset pulse */
10384         REG_WR(sc, QM_REG_SOFT_RESET, 1);
10385         REG_WR(sc, QM_REG_SOFT_RESET, 0);
10386
10387         if (CNIC_SUPPORT(sc))
10388                 ecore_init_block(sc, BLOCK_TM, PHASE_COMMON);
10389
10390         ecore_init_block(sc, BLOCK_DORQ, PHASE_COMMON);
10391
10392         if (!CHIP_REV_IS_SLOW(sc)) {
10393 /* enable hw interrupt from doorbell Q */
10394                 REG_WR(sc, DORQ_REG_DORQ_INT_MASK, 0);
10395         }
10396
10397         ecore_init_block(sc, BLOCK_BRB1, PHASE_COMMON);
10398
10399         ecore_init_block(sc, BLOCK_PRS, PHASE_COMMON);
10400         REG_WR(sc, PRS_REG_A_PRSU_20, 0xf);
10401         REG_WR(sc, PRS_REG_E1HOV_MODE, sc->devinfo.mf_info.path_has_ovlan);
10402
10403         if (!CHIP_IS_E1x(sc) && !CHIP_IS_E3B0(sc)) {
10404                 if (IS_MF_AFEX(sc)) {
10405                         /*
10406                          * configure that AFEX and VLAN headers must be
10407                          * received in AFEX mode
10408                          */
10409                         REG_WR(sc, PRS_REG_HDRS_AFTER_BASIC, 0xE);
10410                         REG_WR(sc, PRS_REG_MUST_HAVE_HDRS, 0xA);
10411                         REG_WR(sc, PRS_REG_HDRS_AFTER_TAG_0, 0x6);
10412                         REG_WR(sc, PRS_REG_TAG_ETHERTYPE_0, 0x8926);
10413                         REG_WR(sc, PRS_REG_TAG_LEN_0, 0x4);
10414                 } else {
10415                         /*
10416                          * Bit-map indicating which L2 hdrs may appear
10417                          * after the basic Ethernet header
10418                          */
10419                         REG_WR(sc, PRS_REG_HDRS_AFTER_BASIC,
10420                                sc->devinfo.mf_info.path_has_ovlan ? 7 : 6);
10421                 }
10422         }
10423
10424         ecore_init_block(sc, BLOCK_TSDM, PHASE_COMMON);
10425         ecore_init_block(sc, BLOCK_CSDM, PHASE_COMMON);
10426         ecore_init_block(sc, BLOCK_USDM, PHASE_COMMON);
10427         ecore_init_block(sc, BLOCK_XSDM, PHASE_COMMON);
10428
10429         if (!CHIP_IS_E1x(sc)) {
10430 /* reset VFC memories */
10431                 REG_WR(sc, TSEM_REG_FAST_MEMORY + VFC_REG_MEMORIES_RST,
10432                        VFC_MEMORIES_RST_REG_CAM_RST |
10433                        VFC_MEMORIES_RST_REG_RAM_RST);
10434                 REG_WR(sc, XSEM_REG_FAST_MEMORY + VFC_REG_MEMORIES_RST,
10435                        VFC_MEMORIES_RST_REG_CAM_RST |
10436                        VFC_MEMORIES_RST_REG_RAM_RST);
10437
10438                 DELAY(20000);
10439         }
10440
10441         ecore_init_block(sc, BLOCK_TSEM, PHASE_COMMON);
10442         ecore_init_block(sc, BLOCK_USEM, PHASE_COMMON);
10443         ecore_init_block(sc, BLOCK_CSEM, PHASE_COMMON);
10444         ecore_init_block(sc, BLOCK_XSEM, PHASE_COMMON);
10445
10446         /* sync semi rtc */
10447         REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR, 0x80000000);
10448         REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, 0x80000000);
10449
10450         ecore_init_block(sc, BLOCK_UPB, PHASE_COMMON);
10451         ecore_init_block(sc, BLOCK_XPB, PHASE_COMMON);
10452         ecore_init_block(sc, BLOCK_PBF, PHASE_COMMON);
10453
10454         if (!CHIP_IS_E1x(sc)) {
10455                 if (IS_MF_AFEX(sc)) {
10456                         /*
10457                          * configure that AFEX and VLAN headers must be
10458                          * sent in AFEX mode
10459                          */
10460                         REG_WR(sc, PBF_REG_HDRS_AFTER_BASIC, 0xE);
10461                         REG_WR(sc, PBF_REG_MUST_HAVE_HDRS, 0xA);
10462                         REG_WR(sc, PBF_REG_HDRS_AFTER_TAG_0, 0x6);
10463                         REG_WR(sc, PBF_REG_TAG_ETHERTYPE_0, 0x8926);
10464                         REG_WR(sc, PBF_REG_TAG_LEN_0, 0x4);
10465                 } else {
10466                         REG_WR(sc, PBF_REG_HDRS_AFTER_BASIC,
10467                                sc->devinfo.mf_info.path_has_ovlan ? 7 : 6);
10468                 }
10469         }
10470
10471         REG_WR(sc, SRC_REG_SOFT_RST, 1);
10472
10473         ecore_init_block(sc, BLOCK_SRC, PHASE_COMMON);
10474
10475         if (CNIC_SUPPORT(sc)) {
10476                 REG_WR(sc, SRC_REG_KEYSEARCH_0, 0x63285672);
10477                 REG_WR(sc, SRC_REG_KEYSEARCH_1, 0x24b8f2cc);
10478                 REG_WR(sc, SRC_REG_KEYSEARCH_2, 0x223aef9b);
10479                 REG_WR(sc, SRC_REG_KEYSEARCH_3, 0x26001e3a);
10480                 REG_WR(sc, SRC_REG_KEYSEARCH_4, 0x7ae91116);
10481                 REG_WR(sc, SRC_REG_KEYSEARCH_5, 0x5ce5230b);
10482                 REG_WR(sc, SRC_REG_KEYSEARCH_6, 0x298d8adf);
10483                 REG_WR(sc, SRC_REG_KEYSEARCH_7, 0x6eb0ff09);
10484                 REG_WR(sc, SRC_REG_KEYSEARCH_8, 0x1830f82f);
10485                 REG_WR(sc, SRC_REG_KEYSEARCH_9, 0x01e46be7);
10486         }
10487         REG_WR(sc, SRC_REG_SOFT_RST, 0);
10488
10489         if (sizeof(union cdu_context) != 1024) {
10490 /* we currently assume that a context is 1024 bytes */
10491                 PMD_DRV_LOG(NOTICE, sc,
10492                             "please adjust the size of cdu_context(%ld)",
10493                             (long)sizeof(union cdu_context));
10494         }
10495
10496         ecore_init_block(sc, BLOCK_CDU, PHASE_COMMON);
10497         val = (4 << 24) + (0 << 12) + 1024;
10498         REG_WR(sc, CDU_REG_CDU_GLOBAL_PARAMS, val);
10499
10500         ecore_init_block(sc, BLOCK_CFC, PHASE_COMMON);
10501
10502         REG_WR(sc, CFC_REG_INIT_REG, 0x7FF);
10503         /* enable context validation interrupt from CFC */
10504         REG_WR(sc, CFC_REG_CFC_INT_MASK, 0);
10505
10506         /* set the thresholds to prevent CFC/CDU race */
10507         REG_WR(sc, CFC_REG_DEBUG0, 0x20020000);
10508         ecore_init_block(sc, BLOCK_HC, PHASE_COMMON);
10509
10510         if (!CHIP_IS_E1x(sc) && BNX2X_NOMCP(sc)) {
10511                 REG_WR(sc, IGU_REG_RESET_MEMORIES, 0x36);
10512         }
10513
10514         ecore_init_block(sc, BLOCK_IGU, PHASE_COMMON);
10515         ecore_init_block(sc, BLOCK_MISC_AEU, PHASE_COMMON);
10516
10517         /* Reset PCIE errors for debug */
10518         REG_WR(sc, 0x2814, 0xffffffff);
10519         REG_WR(sc, 0x3820, 0xffffffff);
10520
10521         if (!CHIP_IS_E1x(sc)) {
10522                 REG_WR(sc, PCICFG_OFFSET + PXPCS_TL_CONTROL_5,
10523                        (PXPCS_TL_CONTROL_5_ERR_UNSPPORT1 |
10524                         PXPCS_TL_CONTROL_5_ERR_UNSPPORT));
10525                 REG_WR(sc, PCICFG_OFFSET + PXPCS_TL_FUNC345_STAT,
10526                        (PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT4 |
10527                         PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT3 |
10528                         PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT2));
10529                 REG_WR(sc, PCICFG_OFFSET + PXPCS_TL_FUNC678_STAT,
10530                        (PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT7 |
10531                         PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT6 |
10532                         PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT5));
10533         }
10534
10535         ecore_init_block(sc, BLOCK_NIG, PHASE_COMMON);
10536
10537         /* in E3 this done in per-port section */
10538         if (!CHIP_IS_E3(sc))
10539                 REG_WR(sc, NIG_REG_LLH_MF_MODE, IS_MF(sc));
10540
10541         if (CHIP_IS_E1H(sc)) {
10542 /* not applicable for E2 (and above ...) */
10543                 REG_WR(sc, NIG_REG_LLH_E1HOV_MODE, IS_MF_SD(sc));
10544         }
10545
10546         if (CHIP_REV_IS_SLOW(sc)) {
10547                 DELAY(200000);
10548         }
10549
10550         /* finish CFC init */
10551         val = reg_poll(sc, CFC_REG_LL_INIT_DONE, 1, 100, 10);
10552         if (val != 1) {
10553                 PMD_DRV_LOG(NOTICE, sc, "CFC LL_INIT failed");
10554                 return -1;
10555         }
10556         val = reg_poll(sc, CFC_REG_AC_INIT_DONE, 1, 100, 10);
10557         if (val != 1) {
10558                 PMD_DRV_LOG(NOTICE, sc, "CFC AC_INIT failed");
10559                 return -1;
10560         }
10561         val = reg_poll(sc, CFC_REG_CAM_INIT_DONE, 1, 100, 10);
10562         if (val != 1) {
10563                 PMD_DRV_LOG(NOTICE, sc, "CFC CAM_INIT failed");
10564                 return -1;
10565         }
10566         REG_WR(sc, CFC_REG_DEBUG0, 0);
10567
10568         bnx2x_setup_fan_failure_detection(sc);
10569
10570         /* clear PXP2 attentions */
10571         REG_RD(sc, PXP2_REG_PXP2_INT_STS_CLR_0);
10572
10573         bnx2x_enable_blocks_attention(sc);
10574
10575         if (!CHIP_REV_IS_SLOW(sc)) {
10576                 ecore_enable_blocks_parity(sc);
10577         }
10578
10579         if (!BNX2X_NOMCP(sc)) {
10580                 if (CHIP_IS_E1x(sc)) {
10581                         bnx2x_common_init_phy(sc);
10582                 }
10583         }
10584
10585         return 0;
10586 }
10587
10588 /**
10589  * bnx2x_init_hw_common_chip - init HW at the COMMON_CHIP phase.
10590  *
10591  * @sc:     driver handle
10592  */
10593 static int bnx2x_init_hw_common_chip(struct bnx2x_softc *sc)
10594 {
10595         int rc = bnx2x_init_hw_common(sc);
10596
10597         if (rc) {
10598                 return rc;
10599         }
10600
10601         /* In E2 2-PORT mode, same ext phy is used for the two paths */
10602         if (!BNX2X_NOMCP(sc)) {
10603                 bnx2x_common_init_phy(sc);
10604         }
10605
10606         return 0;
10607 }
10608
10609 static int bnx2x_init_hw_port(struct bnx2x_softc *sc)
10610 {
10611         int port = SC_PORT(sc);
10612         int init_phase = port ? PHASE_PORT1 : PHASE_PORT0;
10613         uint32_t low, high;
10614         uint32_t val;
10615
10616         PMD_DRV_LOG(DEBUG, sc, "starting port init for port %d", port);
10617
10618         REG_WR(sc, NIG_REG_MASK_INTERRUPT_PORT0 + port * 4, 0);
10619
10620         ecore_init_block(sc, BLOCK_MISC, init_phase);
10621         ecore_init_block(sc, BLOCK_PXP, init_phase);
10622         ecore_init_block(sc, BLOCK_PXP2, init_phase);
10623
10624         /*
10625          * Timers bug workaround: disables the pf_master bit in pglue at
10626          * common phase, we need to enable it here before any dmae access are
10627          * attempted. Therefore we manually added the enable-master to the
10628          * port phase (it also happens in the function phase)
10629          */
10630         if (!CHIP_IS_E1x(sc)) {
10631                 REG_WR(sc, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 1);
10632         }
10633
10634         ecore_init_block(sc, BLOCK_ATC, init_phase);
10635         ecore_init_block(sc, BLOCK_DMAE, init_phase);
10636         ecore_init_block(sc, BLOCK_PGLUE_B, init_phase);
10637         ecore_init_block(sc, BLOCK_QM, init_phase);
10638
10639         ecore_init_block(sc, BLOCK_TCM, init_phase);
10640         ecore_init_block(sc, BLOCK_UCM, init_phase);
10641         ecore_init_block(sc, BLOCK_CCM, init_phase);
10642         ecore_init_block(sc, BLOCK_XCM, init_phase);
10643
10644         /* QM cid (connection) count */
10645         ecore_qm_init_cid_count(sc, sc->qm_cid_count, INITOP_SET);
10646
10647         if (CNIC_SUPPORT(sc)) {
10648                 ecore_init_block(sc, BLOCK_TM, init_phase);
10649                 REG_WR(sc, TM_REG_LIN0_SCAN_TIME + port * 4, 20);
10650                 REG_WR(sc, TM_REG_LIN0_MAX_ACTIVE_CID + port * 4, 31);
10651         }
10652
10653         ecore_init_block(sc, BLOCK_DORQ, init_phase);
10654
10655         ecore_init_block(sc, BLOCK_BRB1, init_phase);
10656
10657         if (CHIP_IS_E1H(sc)) {
10658                 if (IS_MF(sc)) {
10659                         low = (BNX2X_ONE_PORT(sc) ? 160 : 246);
10660                 } else if (sc->mtu > 4096) {
10661                         if (BNX2X_ONE_PORT(sc)) {
10662                                 low = 160;
10663                         } else {
10664                                 val = sc->mtu;
10665                                 /* (24*1024 + val*4)/256 */
10666                                 low = (96 + (val / 64) + ((val % 64) ? 1 : 0));
10667                         }
10668                 } else {
10669                         low = (BNX2X_ONE_PORT(sc) ? 80 : 160);
10670                 }
10671                 high = (low + 56);      /* 14*1024/256 */
10672                 REG_WR(sc, BRB1_REG_PAUSE_LOW_THRESHOLD_0 + port * 4, low);
10673                 REG_WR(sc, BRB1_REG_PAUSE_HIGH_THRESHOLD_0 + port * 4, high);
10674         }
10675
10676         if (CHIP_IS_MODE_4_PORT(sc)) {
10677                 REG_WR(sc, SC_PORT(sc) ?
10678                        BRB1_REG_MAC_GUARANTIED_1 :
10679                        BRB1_REG_MAC_GUARANTIED_0, 40);
10680         }
10681
10682         ecore_init_block(sc, BLOCK_PRS, init_phase);
10683         if (CHIP_IS_E3B0(sc)) {
10684                 if (IS_MF_AFEX(sc)) {
10685                         /* configure headers for AFEX mode */
10686                         if (SC_PORT(sc)) {
10687                                 REG_WR(sc, PRS_REG_HDRS_AFTER_BASIC_PORT_1,
10688                                        0xE);
10689                                 REG_WR(sc, PRS_REG_HDRS_AFTER_TAG_0_PORT_1,
10690                                        0x6);
10691                                 REG_WR(sc, PRS_REG_MUST_HAVE_HDRS_PORT_1, 0xA);
10692                         } else {
10693                                 REG_WR(sc, PRS_REG_HDRS_AFTER_BASIC_PORT_0,
10694                                        0xE);
10695                                 REG_WR(sc, PRS_REG_HDRS_AFTER_TAG_0_PORT_0,
10696                                        0x6);
10697                                 REG_WR(sc, PRS_REG_MUST_HAVE_HDRS_PORT_0, 0xA);
10698                         }
10699                 } else {
10700                         /* Ovlan exists only if we are in multi-function +
10701                          * switch-dependent mode, in switch-independent there
10702                          * is no ovlan headers
10703                          */
10704                         REG_WR(sc, SC_PORT(sc) ?
10705                                PRS_REG_HDRS_AFTER_BASIC_PORT_1 :
10706                                PRS_REG_HDRS_AFTER_BASIC_PORT_0,
10707                                (sc->devinfo.mf_info.path_has_ovlan ? 7 : 6));
10708                 }
10709         }
10710
10711         ecore_init_block(sc, BLOCK_TSDM, init_phase);
10712         ecore_init_block(sc, BLOCK_CSDM, init_phase);
10713         ecore_init_block(sc, BLOCK_USDM, init_phase);
10714         ecore_init_block(sc, BLOCK_XSDM, init_phase);
10715
10716         ecore_init_block(sc, BLOCK_TSEM, init_phase);
10717         ecore_init_block(sc, BLOCK_USEM, init_phase);
10718         ecore_init_block(sc, BLOCK_CSEM, init_phase);
10719         ecore_init_block(sc, BLOCK_XSEM, init_phase);
10720
10721         ecore_init_block(sc, BLOCK_UPB, init_phase);
10722         ecore_init_block(sc, BLOCK_XPB, init_phase);
10723
10724         ecore_init_block(sc, BLOCK_PBF, init_phase);
10725
10726         if (CHIP_IS_E1x(sc)) {
10727 /* configure PBF to work without PAUSE mtu 9000 */
10728                 REG_WR(sc, PBF_REG_P0_PAUSE_ENABLE + port * 4, 0);
10729
10730 /* update threshold */
10731                 REG_WR(sc, PBF_REG_P0_ARB_THRSH + port * 4, (9040 / 16));
10732 /* update init credit */
10733                 REG_WR(sc, PBF_REG_P0_INIT_CRD + port * 4,
10734                        (9040 / 16) + 553 - 22);
10735
10736 /* probe changes */
10737                 REG_WR(sc, PBF_REG_INIT_P0 + port * 4, 1);
10738                 DELAY(50);
10739                 REG_WR(sc, PBF_REG_INIT_P0 + port * 4, 0);
10740         }
10741
10742         if (CNIC_SUPPORT(sc)) {
10743                 ecore_init_block(sc, BLOCK_SRC, init_phase);
10744         }
10745
10746         ecore_init_block(sc, BLOCK_CDU, init_phase);
10747         ecore_init_block(sc, BLOCK_CFC, init_phase);
10748         ecore_init_block(sc, BLOCK_HC, init_phase);
10749         ecore_init_block(sc, BLOCK_IGU, init_phase);
10750         ecore_init_block(sc, BLOCK_MISC_AEU, init_phase);
10751         /* init aeu_mask_attn_func_0/1:
10752          *  - SF mode: bits 3-7 are masked. only bits 0-2 are in use
10753          *  - MF mode: bit 3 is masked. bits 0-2 are in use as in SF
10754          *             bits 4-7 are used for "per vn group attention" */
10755         val = IS_MF(sc) ? 0xF7 : 0x7;
10756         val |= 0x10;
10757         REG_WR(sc, MISC_REG_AEU_MASK_ATTN_FUNC_0 + port * 4, val);
10758
10759         ecore_init_block(sc, BLOCK_NIG, init_phase);
10760
10761         if (!CHIP_IS_E1x(sc)) {
10762 /* Bit-map indicating which L2 hdrs may appear after the
10763  * basic Ethernet header
10764  */
10765                 if (IS_MF_AFEX(sc)) {
10766                         REG_WR(sc, SC_PORT(sc) ?
10767                                NIG_REG_P1_HDRS_AFTER_BASIC :
10768                                NIG_REG_P0_HDRS_AFTER_BASIC, 0xE);
10769                 } else {
10770                         REG_WR(sc, SC_PORT(sc) ?
10771                                NIG_REG_P1_HDRS_AFTER_BASIC :
10772                                NIG_REG_P0_HDRS_AFTER_BASIC,
10773                                IS_MF_SD(sc) ? 7 : 6);
10774                 }
10775
10776                 if (CHIP_IS_E3(sc)) {
10777                         REG_WR(sc, SC_PORT(sc) ?
10778                                NIG_REG_LLH1_MF_MODE :
10779                                NIG_REG_LLH_MF_MODE, IS_MF(sc));
10780                 }
10781         }
10782         if (!CHIP_IS_E3(sc)) {
10783                 REG_WR(sc, NIG_REG_XGXS_SERDES0_MODE_SEL + port * 4, 1);
10784         }
10785
10786         /* 0x2 disable mf_ov, 0x1 enable */
10787         REG_WR(sc, NIG_REG_LLH0_BRB1_DRV_MASK_MF + port * 4,
10788                (IS_MF_SD(sc) ? 0x1 : 0x2));
10789
10790         if (!CHIP_IS_E1x(sc)) {
10791                 val = 0;
10792                 switch (sc->devinfo.mf_info.mf_mode) {
10793                 case MULTI_FUNCTION_SD:
10794                         val = 1;
10795                         break;
10796                 case MULTI_FUNCTION_SI:
10797                 case MULTI_FUNCTION_AFEX:
10798                         val = 2;
10799                         break;
10800                 }
10801
10802                 REG_WR(sc, (SC_PORT(sc) ? NIG_REG_LLH1_CLS_TYPE :
10803                             NIG_REG_LLH0_CLS_TYPE), val);
10804         }
10805         REG_WR(sc, NIG_REG_LLFC_ENABLE_0 + port * 4, 0);
10806         REG_WR(sc, NIG_REG_LLFC_OUT_EN_0 + port * 4, 0);
10807         REG_WR(sc, NIG_REG_PAUSE_ENABLE_0 + port * 4, 1);
10808
10809         /* If SPIO5 is set to generate interrupts, enable it for this port */
10810         val = REG_RD(sc, MISC_REG_SPIO_EVENT_EN);
10811         if (val & MISC_SPIO_SPIO5) {
10812                 uint32_t reg_addr = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 :
10813                                      MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0);
10814                 val = REG_RD(sc, reg_addr);
10815                 val |= AEU_INPUTS_ATTN_BITS_SPIO5;
10816                 REG_WR(sc, reg_addr, val);
10817         }
10818
10819         return 0;
10820 }
10821
10822 static uint32_t
10823 bnx2x_flr_clnup_reg_poll(struct bnx2x_softc *sc, uint32_t reg,
10824                        uint32_t expected, uint32_t poll_count)
10825 {
10826         uint32_t cur_cnt = poll_count;
10827         uint32_t val;
10828
10829         while ((val = REG_RD(sc, reg)) != expected && cur_cnt--) {
10830                 DELAY(FLR_WAIT_INTERVAL);
10831         }
10832
10833         return val;
10834 }
10835
10836 static int
10837 bnx2x_flr_clnup_poll_hw_counter(struct bnx2x_softc *sc, uint32_t reg,
10838                               __rte_unused const char *msg, uint32_t poll_cnt)
10839 {
10840         uint32_t val = bnx2x_flr_clnup_reg_poll(sc, reg, 0, poll_cnt);
10841
10842         if (val != 0) {
10843                 PMD_DRV_LOG(NOTICE, sc, "%s usage count=%d", msg, val);
10844                 return -1;
10845         }
10846
10847         return 0;
10848 }
10849
10850 /* Common routines with VF FLR cleanup */
10851 static uint32_t bnx2x_flr_clnup_poll_count(struct bnx2x_softc *sc)
10852 {
10853         /* adjust polling timeout */
10854         if (CHIP_REV_IS_EMUL(sc)) {
10855                 return FLR_POLL_CNT * 2000;
10856         }
10857
10858         if (CHIP_REV_IS_FPGA(sc)) {
10859                 return FLR_POLL_CNT * 120;
10860         }
10861
10862         return FLR_POLL_CNT;
10863 }
10864
10865 static int bnx2x_poll_hw_usage_counters(struct bnx2x_softc *sc, uint32_t poll_cnt)
10866 {
10867         /* wait for CFC PF usage-counter to zero (includes all the VFs) */
10868         if (bnx2x_flr_clnup_poll_hw_counter(sc,
10869                                           CFC_REG_NUM_LCIDS_INSIDE_PF,
10870                                           "CFC PF usage counter timed out",
10871                                           poll_cnt)) {
10872                 return -1;
10873         }
10874
10875         /* Wait for DQ PF usage-counter to zero (until DQ cleanup) */
10876         if (bnx2x_flr_clnup_poll_hw_counter(sc,
10877                                           DORQ_REG_PF_USAGE_CNT,
10878                                           "DQ PF usage counter timed out",
10879                                           poll_cnt)) {
10880                 return -1;
10881         }
10882
10883         /* Wait for QM PF usage-counter to zero (until DQ cleanup) */
10884         if (bnx2x_flr_clnup_poll_hw_counter(sc,
10885                                           QM_REG_PF_USG_CNT_0 + 4 * SC_FUNC(sc),
10886                                           "QM PF usage counter timed out",
10887                                           poll_cnt)) {
10888                 return -1;
10889         }
10890
10891         /* Wait for Timer PF usage-counters to zero (until DQ cleanup) */
10892         if (bnx2x_flr_clnup_poll_hw_counter(sc,
10893                                           TM_REG_LIN0_VNIC_UC + 4 * SC_PORT(sc),
10894                                           "Timers VNIC usage counter timed out",
10895                                           poll_cnt)) {
10896                 return -1;
10897         }
10898
10899         if (bnx2x_flr_clnup_poll_hw_counter(sc,
10900                                           TM_REG_LIN0_NUM_SCANS +
10901                                           4 * SC_PORT(sc),
10902                                           "Timers NUM_SCANS usage counter timed out",
10903                                           poll_cnt)) {
10904                 return -1;
10905         }
10906
10907         /* Wait DMAE PF usage counter to zero */
10908         if (bnx2x_flr_clnup_poll_hw_counter(sc,
10909                                           dmae_reg_go_c[INIT_DMAE_C(sc)],
10910                                           "DMAE dommand register timed out",
10911                                           poll_cnt)) {
10912                 return -1;
10913         }
10914
10915         return 0;
10916 }
10917
10918 #define OP_GEN_PARAM(param)                                            \
10919         (((param) << SDM_OP_GEN_COMP_PARAM_SHIFT) & SDM_OP_GEN_COMP_PARAM)
10920 #define OP_GEN_TYPE(type)                                           \
10921         (((type) << SDM_OP_GEN_COMP_TYPE_SHIFT) & SDM_OP_GEN_COMP_TYPE)
10922 #define OP_GEN_AGG_VECT(index)                                             \
10923         (((index) << SDM_OP_GEN_AGG_VECT_IDX_SHIFT) & SDM_OP_GEN_AGG_VECT_IDX)
10924
10925 static int
10926 bnx2x_send_final_clnup(struct bnx2x_softc *sc, uint8_t clnup_func,
10927                      uint32_t poll_cnt)
10928 {
10929         uint32_t op_gen_command = 0;
10930         uint32_t comp_addr = (BAR_CSTRORM_INTMEM +
10931                               CSTORM_FINAL_CLEANUP_COMPLETE_OFFSET(clnup_func));
10932         int ret = 0;
10933
10934         if (REG_RD(sc, comp_addr)) {
10935                 PMD_DRV_LOG(NOTICE, sc,
10936                             "Cleanup complete was not 0 before sending");
10937                 return -1;
10938         }
10939
10940         op_gen_command |= OP_GEN_PARAM(XSTORM_AGG_INT_FINAL_CLEANUP_INDEX);
10941         op_gen_command |= OP_GEN_TYPE(XSTORM_AGG_INT_FINAL_CLEANUP_COMP_TYPE);
10942         op_gen_command |= OP_GEN_AGG_VECT(clnup_func);
10943         op_gen_command |= 1 << SDM_OP_GEN_AGG_VECT_IDX_VALID_SHIFT;
10944
10945         REG_WR(sc, XSDM_REG_OPERATION_GEN, op_gen_command);
10946
10947         if (bnx2x_flr_clnup_reg_poll(sc, comp_addr, 1, poll_cnt) != 1) {
10948                 PMD_DRV_LOG(NOTICE, sc, "FW final cleanup did not succeed");
10949                 PMD_DRV_LOG(DEBUG, sc, "At timeout completion address contained %x",
10950                             (REG_RD(sc, comp_addr)));
10951                 rte_panic("FLR cleanup failed");
10952                 return -1;
10953         }
10954
10955         /* Zero completion for nxt FLR */
10956         REG_WR(sc, comp_addr, 0);
10957
10958         return ret;
10959 }
10960
10961 static void
10962 bnx2x_pbf_pN_buf_flushed(struct bnx2x_softc *sc, struct pbf_pN_buf_regs *regs,
10963                        uint32_t poll_count)
10964 {
10965         uint32_t init_crd, crd, crd_start, crd_freed, crd_freed_start;
10966         uint32_t cur_cnt = poll_count;
10967
10968         crd_freed = crd_freed_start = REG_RD(sc, regs->crd_freed);
10969         crd = crd_start = REG_RD(sc, regs->crd);
10970         init_crd = REG_RD(sc, regs->init_crd);
10971
10972         while ((crd != init_crd) &&
10973                ((uint32_t) ((int32_t) crd_freed - (int32_t) crd_freed_start) <
10974                 (init_crd - crd_start))) {
10975                 if (cur_cnt--) {
10976                         DELAY(FLR_WAIT_INTERVAL);
10977                         crd = REG_RD(sc, regs->crd);
10978                         crd_freed = REG_RD(sc, regs->crd_freed);
10979                 } else {
10980                         break;
10981                 }
10982         }
10983 }
10984
10985 static void
10986 bnx2x_pbf_pN_cmd_flushed(struct bnx2x_softc *sc, struct pbf_pN_cmd_regs *regs,
10987                        uint32_t poll_count)
10988 {
10989         uint32_t occup, to_free, freed, freed_start;
10990         uint32_t cur_cnt = poll_count;
10991
10992         occup = to_free = REG_RD(sc, regs->lines_occup);
10993         freed = freed_start = REG_RD(sc, regs->lines_freed);
10994
10995         while (occup &&
10996                ((uint32_t) ((int32_t) freed - (int32_t) freed_start) <
10997                 to_free)) {
10998                 if (cur_cnt--) {
10999                         DELAY(FLR_WAIT_INTERVAL);
11000                         occup = REG_RD(sc, regs->lines_occup);
11001                         freed = REG_RD(sc, regs->lines_freed);
11002                 } else {
11003                         break;
11004                 }
11005         }
11006 }
11007
11008 static void bnx2x_tx_hw_flushed(struct bnx2x_softc *sc, uint32_t poll_count)
11009 {
11010         struct pbf_pN_cmd_regs cmd_regs[] = {
11011                 {0, (CHIP_IS_E3B0(sc)) ?
11012                  PBF_REG_TQ_OCCUPANCY_Q0 : PBF_REG_P0_TQ_OCCUPANCY,
11013                  (CHIP_IS_E3B0(sc)) ?
11014                  PBF_REG_TQ_LINES_FREED_CNT_Q0 : PBF_REG_P0_TQ_LINES_FREED_CNT},
11015                 {1, (CHIP_IS_E3B0(sc)) ?
11016                  PBF_REG_TQ_OCCUPANCY_Q1 : PBF_REG_P1_TQ_OCCUPANCY,
11017                  (CHIP_IS_E3B0(sc)) ?
11018                  PBF_REG_TQ_LINES_FREED_CNT_Q1 : PBF_REG_P1_TQ_LINES_FREED_CNT},
11019                 {4, (CHIP_IS_E3B0(sc)) ?
11020                  PBF_REG_TQ_OCCUPANCY_LB_Q : PBF_REG_P4_TQ_OCCUPANCY,
11021                  (CHIP_IS_E3B0(sc)) ?
11022                  PBF_REG_TQ_LINES_FREED_CNT_LB_Q :
11023                  PBF_REG_P4_TQ_LINES_FREED_CNT}
11024         };
11025
11026         struct pbf_pN_buf_regs buf_regs[] = {
11027                 {0, (CHIP_IS_E3B0(sc)) ?
11028                  PBF_REG_INIT_CRD_Q0 : PBF_REG_P0_INIT_CRD,
11029                  (CHIP_IS_E3B0(sc)) ? PBF_REG_CREDIT_Q0 : PBF_REG_P0_CREDIT,
11030                  (CHIP_IS_E3B0(sc)) ?
11031                  PBF_REG_INTERNAL_CRD_FREED_CNT_Q0 :
11032                  PBF_REG_P0_INTERNAL_CRD_FREED_CNT},
11033                 {1, (CHIP_IS_E3B0(sc)) ?
11034                  PBF_REG_INIT_CRD_Q1 : PBF_REG_P1_INIT_CRD,
11035                  (CHIP_IS_E3B0(sc)) ? PBF_REG_CREDIT_Q1 : PBF_REG_P1_CREDIT,
11036                  (CHIP_IS_E3B0(sc)) ?
11037                  PBF_REG_INTERNAL_CRD_FREED_CNT_Q1 :
11038                  PBF_REG_P1_INTERNAL_CRD_FREED_CNT},
11039                 {4, (CHIP_IS_E3B0(sc)) ?
11040                  PBF_REG_INIT_CRD_LB_Q : PBF_REG_P4_INIT_CRD,
11041                  (CHIP_IS_E3B0(sc)) ? PBF_REG_CREDIT_LB_Q : PBF_REG_P4_CREDIT,
11042                  (CHIP_IS_E3B0(sc)) ?
11043                  PBF_REG_INTERNAL_CRD_FREED_CNT_LB_Q :
11044                  PBF_REG_P4_INTERNAL_CRD_FREED_CNT},
11045         };
11046
11047         uint32_t i;
11048
11049         /* Verify the command queues are flushed P0, P1, P4 */
11050         for (i = 0; i < ARRAY_SIZE(cmd_regs); i++) {
11051                 bnx2x_pbf_pN_cmd_flushed(sc, &cmd_regs[i], poll_count);
11052         }
11053
11054         /* Verify the transmission buffers are flushed P0, P1, P4 */
11055         for (i = 0; i < ARRAY_SIZE(buf_regs); i++) {
11056                 bnx2x_pbf_pN_buf_flushed(sc, &buf_regs[i], poll_count);
11057         }
11058 }
11059
11060 static void bnx2x_hw_enable_status(struct bnx2x_softc *sc)
11061 {
11062         __rte_unused uint32_t val;
11063
11064         val = REG_RD(sc, CFC_REG_WEAK_ENABLE_PF);
11065         PMD_DRV_LOG(DEBUG, sc, "CFC_REG_WEAK_ENABLE_PF is 0x%x", val);
11066
11067         val = REG_RD(sc, PBF_REG_DISABLE_PF);
11068         PMD_DRV_LOG(DEBUG, sc, "PBF_REG_DISABLE_PF is 0x%x", val);
11069
11070         val = REG_RD(sc, IGU_REG_PCI_PF_MSI_EN);
11071         PMD_DRV_LOG(DEBUG, sc, "IGU_REG_PCI_PF_MSI_EN is 0x%x", val);
11072
11073         val = REG_RD(sc, IGU_REG_PCI_PF_MSIX_EN);
11074         PMD_DRV_LOG(DEBUG, sc, "IGU_REG_PCI_PF_MSIX_EN is 0x%x", val);
11075
11076         val = REG_RD(sc, IGU_REG_PCI_PF_MSIX_FUNC_MASK);
11077         PMD_DRV_LOG(DEBUG, sc, "IGU_REG_PCI_PF_MSIX_FUNC_MASK is 0x%x", val);
11078
11079         val = REG_RD(sc, PGLUE_B_REG_SHADOW_BME_PF_7_0_CLR);
11080         PMD_DRV_LOG(DEBUG, sc,
11081                     "PGLUE_B_REG_SHADOW_BME_PF_7_0_CLR is 0x%x", val);
11082
11083         val = REG_RD(sc, PGLUE_B_REG_FLR_REQUEST_PF_7_0_CLR);
11084         PMD_DRV_LOG(DEBUG, sc,
11085                     "PGLUE_B_REG_FLR_REQUEST_PF_7_0_CLR is 0x%x", val);
11086
11087         val = REG_RD(sc, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER);
11088         PMD_DRV_LOG(DEBUG, sc, "PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER is 0x%x",
11089                     val);
11090 }
11091
11092 /**
11093  *      bnx2x_pf_flr_clnup
11094  *      a. re-enable target read on the PF
11095  *      b. poll cfc per function usgae counter
11096  *      c. poll the qm perfunction usage counter
11097  *      d. poll the tm per function usage counter
11098  *      e. poll the tm per function scan-done indication
11099  *      f. clear the dmae channel associated wit hthe PF
11100  *      g. zero the igu 'trailing edge' and 'leading edge' regs (attentions)
11101  *      h. call the common flr cleanup code with -1 (pf indication)
11102  */
11103 static int bnx2x_pf_flr_clnup(struct bnx2x_softc *sc)
11104 {
11105         uint32_t poll_cnt = bnx2x_flr_clnup_poll_count(sc);
11106
11107         /* Re-enable PF target read access */
11108         REG_WR(sc, PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_READ, 1);
11109
11110         /* Poll HW usage counters */
11111         if (bnx2x_poll_hw_usage_counters(sc, poll_cnt)) {
11112                 return -1;
11113         }
11114
11115         /* Zero the igu 'trailing edge' and 'leading edge' */
11116
11117         /* Send the FW cleanup command */
11118         if (bnx2x_send_final_clnup(sc, (uint8_t) SC_FUNC(sc), poll_cnt)) {
11119                 return -1;
11120         }
11121
11122         /* ATC cleanup */
11123
11124         /* Verify TX hw is flushed */
11125         bnx2x_tx_hw_flushed(sc, poll_cnt);
11126
11127         /* Wait 100ms (not adjusted according to platform) */
11128         DELAY(100000);
11129
11130         /* Verify no pending pci transactions */
11131         if (bnx2x_is_pcie_pending(sc)) {
11132                 PMD_DRV_LOG(NOTICE, sc, "PCIE Transactions still pending");
11133         }
11134
11135         /* Debug */
11136         bnx2x_hw_enable_status(sc);
11137
11138         /*
11139          * Master enable - Due to WB DMAE writes performed before this
11140          * register is re-initialized as part of the regular function init
11141          */
11142         REG_WR(sc, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 1);
11143
11144         return 0;
11145 }
11146
11147 static int bnx2x_init_hw_func(struct bnx2x_softc *sc)
11148 {
11149         int port = SC_PORT(sc);
11150         int func = SC_FUNC(sc);
11151         int init_phase = PHASE_PF0 + func;
11152         struct ecore_ilt *ilt = sc->ilt;
11153         uint16_t cdu_ilt_start;
11154         uint32_t addr, val;
11155         uint32_t main_mem_base, main_mem_size, main_mem_prty_clr;
11156         int main_mem_width, rc;
11157         uint32_t i;
11158
11159         PMD_DRV_LOG(DEBUG, sc, "starting func init for func %d", func);
11160
11161         /* FLR cleanup */
11162         if (!CHIP_IS_E1x(sc)) {
11163                 rc = bnx2x_pf_flr_clnup(sc);
11164                 if (rc) {
11165                         PMD_DRV_LOG(NOTICE, sc, "FLR cleanup failed!");
11166                         return rc;
11167                 }
11168         }
11169
11170         /* set MSI reconfigure capability */
11171         if (sc->devinfo.int_block == INT_BLOCK_HC) {
11172                 addr = (port ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0);
11173                 val = REG_RD(sc, addr);
11174                 val |= HC_CONFIG_0_REG_MSI_ATTN_EN_0;
11175                 REG_WR(sc, addr, val);
11176         }
11177
11178         ecore_init_block(sc, BLOCK_PXP, init_phase);
11179         ecore_init_block(sc, BLOCK_PXP2, init_phase);
11180
11181         ilt = sc->ilt;
11182         cdu_ilt_start = ilt->clients[ILT_CLIENT_CDU].start;
11183
11184         for (i = 0; i < L2_ILT_LINES(sc); i++) {
11185                 ilt->lines[cdu_ilt_start + i].page = sc->context[i].vcxt;
11186                 ilt->lines[cdu_ilt_start + i].page_mapping =
11187                     (rte_iova_t)sc->context[i].vcxt_dma.paddr;
11188                 ilt->lines[cdu_ilt_start + i].size = sc->context[i].size;
11189         }
11190         ecore_ilt_init_op(sc, INITOP_SET);
11191
11192         REG_WR(sc, PRS_REG_NIC_MODE, 1);
11193
11194         if (!CHIP_IS_E1x(sc)) {
11195                 uint32_t pf_conf = IGU_PF_CONF_FUNC_EN;
11196
11197 /* Turn on a single ISR mode in IGU if driver is going to use
11198  * INT#x or MSI
11199  */
11200                 if ((sc->interrupt_mode != INTR_MODE_MSIX)
11201                     || (sc->interrupt_mode != INTR_MODE_SINGLE_MSIX)) {
11202                         pf_conf |= IGU_PF_CONF_SINGLE_ISR_EN;
11203                 }
11204
11205 /*
11206  * Timers workaround bug: function init part.
11207  * Need to wait 20msec after initializing ILT,
11208  * needed to make sure there are no requests in
11209  * one of the PXP internal queues with "old" ILT addresses
11210  */
11211                 DELAY(20000);
11212
11213 /*
11214  * Master enable - Due to WB DMAE writes performed before this
11215  * register is re-initialized as part of the regular function
11216  * init
11217  */
11218                 REG_WR(sc, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 1);
11219 /* Enable the function in IGU */
11220                 REG_WR(sc, IGU_REG_PF_CONFIGURATION, pf_conf);
11221         }
11222
11223         sc->dmae_ready = 1;
11224
11225         ecore_init_block(sc, BLOCK_PGLUE_B, init_phase);
11226
11227         if (!CHIP_IS_E1x(sc))
11228                 REG_WR(sc, PGLUE_B_REG_WAS_ERROR_PF_7_0_CLR, func);
11229
11230         ecore_init_block(sc, BLOCK_ATC, init_phase);
11231         ecore_init_block(sc, BLOCK_DMAE, init_phase);
11232         ecore_init_block(sc, BLOCK_NIG, init_phase);
11233         ecore_init_block(sc, BLOCK_SRC, init_phase);
11234         ecore_init_block(sc, BLOCK_MISC, init_phase);
11235         ecore_init_block(sc, BLOCK_TCM, init_phase);
11236         ecore_init_block(sc, BLOCK_UCM, init_phase);
11237         ecore_init_block(sc, BLOCK_CCM, init_phase);
11238         ecore_init_block(sc, BLOCK_XCM, init_phase);
11239         ecore_init_block(sc, BLOCK_TSEM, init_phase);
11240         ecore_init_block(sc, BLOCK_USEM, init_phase);
11241         ecore_init_block(sc, BLOCK_CSEM, init_phase);
11242         ecore_init_block(sc, BLOCK_XSEM, init_phase);
11243
11244         if (!CHIP_IS_E1x(sc))
11245                 REG_WR(sc, QM_REG_PF_EN, 1);
11246
11247         if (!CHIP_IS_E1x(sc)) {
11248                 REG_WR(sc, TSEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func);
11249                 REG_WR(sc, USEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func);
11250                 REG_WR(sc, CSEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func);
11251                 REG_WR(sc, XSEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func);
11252         }
11253         ecore_init_block(sc, BLOCK_QM, init_phase);
11254
11255         ecore_init_block(sc, BLOCK_TM, init_phase);
11256         ecore_init_block(sc, BLOCK_DORQ, init_phase);
11257
11258         ecore_init_block(sc, BLOCK_BRB1, init_phase);
11259         ecore_init_block(sc, BLOCK_PRS, init_phase);
11260         ecore_init_block(sc, BLOCK_TSDM, init_phase);
11261         ecore_init_block(sc, BLOCK_CSDM, init_phase);
11262         ecore_init_block(sc, BLOCK_USDM, init_phase);
11263         ecore_init_block(sc, BLOCK_XSDM, init_phase);
11264         ecore_init_block(sc, BLOCK_UPB, init_phase);
11265         ecore_init_block(sc, BLOCK_XPB, init_phase);
11266         ecore_init_block(sc, BLOCK_PBF, init_phase);
11267         if (!CHIP_IS_E1x(sc))
11268                 REG_WR(sc, PBF_REG_DISABLE_PF, 0);
11269
11270         ecore_init_block(sc, BLOCK_CDU, init_phase);
11271
11272         ecore_init_block(sc, BLOCK_CFC, init_phase);
11273
11274         if (!CHIP_IS_E1x(sc))
11275                 REG_WR(sc, CFC_REG_WEAK_ENABLE_PF, 1);
11276
11277         if (IS_MF(sc)) {
11278                 REG_WR(sc, NIG_REG_LLH0_FUNC_EN + port * 8, 1);
11279                 REG_WR(sc, NIG_REG_LLH0_FUNC_VLAN_ID + port * 8, OVLAN(sc));
11280         }
11281
11282         ecore_init_block(sc, BLOCK_MISC_AEU, init_phase);
11283
11284         /* HC init per function */
11285         if (sc->devinfo.int_block == INT_BLOCK_HC) {
11286                 if (CHIP_IS_E1H(sc)) {
11287                         REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_12 + func * 4, 0);
11288
11289                         REG_WR(sc, HC_REG_LEADING_EDGE_0 + port * 8, 0);
11290                         REG_WR(sc, HC_REG_TRAILING_EDGE_0 + port * 8, 0);
11291                 }
11292                 ecore_init_block(sc, BLOCK_HC, init_phase);
11293
11294         } else {
11295                 uint32_t num_segs, sb_idx, prod_offset;
11296
11297                 REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_12 + func * 4, 0);
11298
11299                 if (!CHIP_IS_E1x(sc)) {
11300                         REG_WR(sc, IGU_REG_LEADING_EDGE_LATCH, 0);
11301                         REG_WR(sc, IGU_REG_TRAILING_EDGE_LATCH, 0);
11302                 }
11303
11304                 ecore_init_block(sc, BLOCK_IGU, init_phase);
11305
11306                 if (!CHIP_IS_E1x(sc)) {
11307                         int dsb_idx = 0;
11308         /**
11309          * Producer memory:
11310          * E2 mode: address 0-135 match to the mapping memory;
11311          * 136 - PF0 default prod; 137 - PF1 default prod;
11312          * 138 - PF2 default prod; 139 - PF3 default prod;
11313          * 140 - PF0 attn prod;    141 - PF1 attn prod;
11314          * 142 - PF2 attn prod;    143 - PF3 attn prod;
11315          * 144-147 reserved.
11316          *
11317          * E1.5 mode - In backward compatible mode;
11318          * for non default SB; each even line in the memory
11319          * holds the U producer and each odd line hold
11320          * the C producer. The first 128 producers are for
11321          * NDSB (PF0 - 0-31; PF1 - 32-63 and so on). The last 20
11322          * producers are for the DSB for each PF.
11323          * Each PF has five segments: (the order inside each
11324          * segment is PF0; PF1; PF2; PF3) - 128-131 U prods;
11325          * 132-135 C prods; 136-139 X prods; 140-143 T prods;
11326          * 144-147 attn prods;
11327          */
11328                         /* non-default-status-blocks */
11329                         num_segs = CHIP_INT_MODE_IS_BC(sc) ?
11330                             IGU_BC_NDSB_NUM_SEGS : IGU_NORM_NDSB_NUM_SEGS;
11331                         for (sb_idx = 0; sb_idx < sc->igu_sb_cnt; sb_idx++) {
11332                                 prod_offset = (sc->igu_base_sb + sb_idx) *
11333                                     num_segs;
11334
11335                                 for (i = 0; i < num_segs; i++) {
11336                                         addr = IGU_REG_PROD_CONS_MEMORY +
11337                                             (prod_offset + i) * 4;
11338                                         REG_WR(sc, addr, 0);
11339                                 }
11340                                 /* send consumer update with value 0 */
11341                                 bnx2x_ack_sb(sc, sc->igu_base_sb + sb_idx,
11342                                            USTORM_ID, 0, IGU_INT_NOP, 1);
11343                                 bnx2x_igu_clear_sb(sc, sc->igu_base_sb + sb_idx);
11344                         }
11345
11346                         /* default-status-blocks */
11347                         num_segs = CHIP_INT_MODE_IS_BC(sc) ?
11348                             IGU_BC_DSB_NUM_SEGS : IGU_NORM_DSB_NUM_SEGS;
11349
11350                         if (CHIP_IS_MODE_4_PORT(sc))
11351                                 dsb_idx = SC_FUNC(sc);
11352                         else
11353                                 dsb_idx = SC_VN(sc);
11354
11355                         prod_offset = (CHIP_INT_MODE_IS_BC(sc) ?
11356                                        IGU_BC_BASE_DSB_PROD + dsb_idx :
11357                                        IGU_NORM_BASE_DSB_PROD + dsb_idx);
11358
11359                         /*
11360                          * igu prods come in chunks of E1HVN_MAX (4) -
11361                          * does not matters what is the current chip mode
11362                          */
11363                         for (i = 0; i < (num_segs * E1HVN_MAX); i += E1HVN_MAX) {
11364                                 addr = IGU_REG_PROD_CONS_MEMORY +
11365                                     (prod_offset + i) * 4;
11366                                 REG_WR(sc, addr, 0);
11367                         }
11368                         /* send consumer update with 0 */
11369                         if (CHIP_INT_MODE_IS_BC(sc)) {
11370                                 bnx2x_ack_sb(sc, sc->igu_dsb_id,
11371                                            USTORM_ID, 0, IGU_INT_NOP, 1);
11372                                 bnx2x_ack_sb(sc, sc->igu_dsb_id,
11373                                            CSTORM_ID, 0, IGU_INT_NOP, 1);
11374                                 bnx2x_ack_sb(sc, sc->igu_dsb_id,
11375                                            XSTORM_ID, 0, IGU_INT_NOP, 1);
11376                                 bnx2x_ack_sb(sc, sc->igu_dsb_id,
11377                                            TSTORM_ID, 0, IGU_INT_NOP, 1);
11378                                 bnx2x_ack_sb(sc, sc->igu_dsb_id,
11379                                            ATTENTION_ID, 0, IGU_INT_NOP, 1);
11380                         } else {
11381                                 bnx2x_ack_sb(sc, sc->igu_dsb_id,
11382                                            USTORM_ID, 0, IGU_INT_NOP, 1);
11383                                 bnx2x_ack_sb(sc, sc->igu_dsb_id,
11384                                            ATTENTION_ID, 0, IGU_INT_NOP, 1);
11385                         }
11386                         bnx2x_igu_clear_sb(sc, sc->igu_dsb_id);
11387
11388                         /* !!! these should become driver const once
11389                            rf-tool supports split-68 const */
11390                         REG_WR(sc, IGU_REG_SB_INT_BEFORE_MASK_LSB, 0);
11391                         REG_WR(sc, IGU_REG_SB_INT_BEFORE_MASK_MSB, 0);
11392                         REG_WR(sc, IGU_REG_SB_MASK_LSB, 0);
11393                         REG_WR(sc, IGU_REG_SB_MASK_MSB, 0);
11394                         REG_WR(sc, IGU_REG_PBA_STATUS_LSB, 0);
11395                         REG_WR(sc, IGU_REG_PBA_STATUS_MSB, 0);
11396                 }
11397         }
11398
11399         /* Reset PCIE errors for debug */
11400         REG_WR(sc, 0x2114, 0xffffffff);
11401         REG_WR(sc, 0x2120, 0xffffffff);
11402
11403         if (CHIP_IS_E1x(sc)) {
11404                 main_mem_size = HC_REG_MAIN_MEMORY_SIZE / 2;    /*dwords */
11405                 main_mem_base = HC_REG_MAIN_MEMORY +
11406                     SC_PORT(sc) * (main_mem_size * 4);
11407                 main_mem_prty_clr = HC_REG_HC_PRTY_STS_CLR;
11408                 main_mem_width = 8;
11409
11410                 val = REG_RD(sc, main_mem_prty_clr);
11411                 if (val) {
11412                         PMD_DRV_LOG(DEBUG, sc,
11413                                     "Parity errors in HC block during function init (0x%x)!",
11414                                     val);
11415                 }
11416
11417 /* Clear "false" parity errors in MSI-X table */
11418                 for (i = main_mem_base;
11419                      i < main_mem_base + main_mem_size * 4;
11420                      i += main_mem_width) {
11421                         bnx2x_read_dmae(sc, i, main_mem_width / 4);
11422                         bnx2x_write_dmae(sc, BNX2X_SP_MAPPING(sc, wb_data),
11423                                        i, main_mem_width / 4);
11424                 }
11425 /* Clear HC parity attention */
11426                 REG_RD(sc, main_mem_prty_clr);
11427         }
11428
11429         /* Enable STORMs SP logging */
11430         REG_WR8(sc, BAR_USTRORM_INTMEM +
11431                 USTORM_RECORD_SLOW_PATH_OFFSET(SC_FUNC(sc)), 1);
11432         REG_WR8(sc, BAR_TSTRORM_INTMEM +
11433                 TSTORM_RECORD_SLOW_PATH_OFFSET(SC_FUNC(sc)), 1);
11434         REG_WR8(sc, BAR_CSTRORM_INTMEM +
11435                 CSTORM_RECORD_SLOW_PATH_OFFSET(SC_FUNC(sc)), 1);
11436         REG_WR8(sc, BAR_XSTRORM_INTMEM +
11437                 XSTORM_RECORD_SLOW_PATH_OFFSET(SC_FUNC(sc)), 1);
11438
11439         elink_phy_probe(&sc->link_params);
11440
11441         return 0;
11442 }
11443
11444 static void bnx2x_link_reset(struct bnx2x_softc *sc)
11445 {
11446         if (!BNX2X_NOMCP(sc)) {
11447                 bnx2x_acquire_phy_lock(sc);
11448                 elink_lfa_reset(&sc->link_params, &sc->link_vars);
11449                 bnx2x_release_phy_lock(sc);
11450         } else {
11451                 if (!CHIP_REV_IS_SLOW(sc)) {
11452                         PMD_DRV_LOG(WARNING, sc,
11453                                     "Bootcode is missing - cannot reset link");
11454                 }
11455         }
11456 }
11457
11458 static void bnx2x_reset_port(struct bnx2x_softc *sc)
11459 {
11460         int port = SC_PORT(sc);
11461         uint32_t val;
11462
11463         /* reset physical Link */
11464         bnx2x_link_reset(sc);
11465
11466         REG_WR(sc, NIG_REG_MASK_INTERRUPT_PORT0 + port * 4, 0);
11467
11468         /* Do not rcv packets to BRB */
11469         REG_WR(sc, NIG_REG_LLH0_BRB1_DRV_MASK + port * 4, 0x0);
11470         /* Do not direct rcv packets that are not for MCP to the BRB */
11471         REG_WR(sc, (port ? NIG_REG_LLH1_BRB1_NOT_MCP :
11472                     NIG_REG_LLH0_BRB1_NOT_MCP), 0x0);
11473
11474         /* Configure AEU */
11475         REG_WR(sc, MISC_REG_AEU_MASK_ATTN_FUNC_0 + port * 4, 0);
11476
11477         DELAY(100000);
11478
11479         /* Check for BRB port occupancy */
11480         val = REG_RD(sc, BRB1_REG_PORT_NUM_OCC_BLOCKS_0 + port * 4);
11481         if (val) {
11482                 PMD_DRV_LOG(DEBUG, sc,
11483                             "BRB1 is not empty, %d blocks are occupied", val);
11484         }
11485 }
11486
11487 static void bnx2x_ilt_wr(struct bnx2x_softc *sc, uint32_t index, rte_iova_t addr)
11488 {
11489         int reg;
11490         uint32_t wb_write[2];
11491
11492         reg = PXP2_REG_RQ_ONCHIP_AT_B0 + index * 8;
11493
11494         wb_write[0] = ONCHIP_ADDR1(addr);
11495         wb_write[1] = ONCHIP_ADDR2(addr);
11496         REG_WR_DMAE(sc, reg, wb_write, 2);
11497 }
11498
11499 static void bnx2x_clear_func_ilt(struct bnx2x_softc *sc, uint32_t func)
11500 {
11501         uint32_t i, base = FUNC_ILT_BASE(func);
11502         for (i = base; i < base + ILT_PER_FUNC; i++) {
11503                 bnx2x_ilt_wr(sc, i, 0);
11504         }
11505 }
11506
11507 static void bnx2x_reset_func(struct bnx2x_softc *sc)
11508 {
11509         struct bnx2x_fastpath *fp;
11510         int port = SC_PORT(sc);
11511         int func = SC_FUNC(sc);
11512         int i;
11513
11514         /* Disable the function in the FW */
11515         REG_WR8(sc, BAR_XSTRORM_INTMEM + XSTORM_FUNC_EN_OFFSET(func), 0);
11516         REG_WR8(sc, BAR_CSTRORM_INTMEM + CSTORM_FUNC_EN_OFFSET(func), 0);
11517         REG_WR8(sc, BAR_TSTRORM_INTMEM + TSTORM_FUNC_EN_OFFSET(func), 0);
11518         REG_WR8(sc, BAR_USTRORM_INTMEM + USTORM_FUNC_EN_OFFSET(func), 0);
11519
11520         /* FP SBs */
11521         FOR_EACH_ETH_QUEUE(sc, i) {
11522                 fp = &sc->fp[i];
11523                 REG_WR8(sc, BAR_CSTRORM_INTMEM +
11524                         CSTORM_STATUS_BLOCK_DATA_STATE_OFFSET(fp->fw_sb_id),
11525                         SB_DISABLED);
11526         }
11527
11528         /* SP SB */
11529         REG_WR8(sc, BAR_CSTRORM_INTMEM +
11530                 CSTORM_SP_STATUS_BLOCK_DATA_STATE_OFFSET(func), SB_DISABLED);
11531
11532         for (i = 0; i < XSTORM_SPQ_DATA_SIZE / 4; i++) {
11533                 REG_WR(sc, BAR_XSTRORM_INTMEM + XSTORM_SPQ_DATA_OFFSET(func),
11534                        0);
11535         }
11536
11537         /* Configure IGU */
11538         if (sc->devinfo.int_block == INT_BLOCK_HC) {
11539                 REG_WR(sc, HC_REG_LEADING_EDGE_0 + port * 8, 0);
11540                 REG_WR(sc, HC_REG_TRAILING_EDGE_0 + port * 8, 0);
11541         } else {
11542                 REG_WR(sc, IGU_REG_LEADING_EDGE_LATCH, 0);
11543                 REG_WR(sc, IGU_REG_TRAILING_EDGE_LATCH, 0);
11544         }
11545
11546         if (CNIC_LOADED(sc)) {
11547 /* Disable Timer scan */
11548                 REG_WR(sc, TM_REG_EN_LINEAR0_TIMER + port * 4, 0);
11549 /*
11550  * Wait for at least 10ms and up to 2 second for the timers
11551  * scan to complete
11552  */
11553                 for (i = 0; i < 200; i++) {
11554                         DELAY(10000);
11555                         if (!REG_RD(sc, TM_REG_LIN0_SCAN_ON + port * 4))
11556                                 break;
11557                 }
11558         }
11559
11560         /* Clear ILT */
11561         bnx2x_clear_func_ilt(sc, func);
11562
11563         /*
11564          * Timers workaround bug for E2: if this is vnic-3,
11565          * we need to set the entire ilt range for this timers.
11566          */
11567         if (!CHIP_IS_E1x(sc) && SC_VN(sc) == 3) {
11568                 struct ilt_client_info ilt_cli;
11569 /* use dummy TM client */
11570                 memset(&ilt_cli, 0, sizeof(struct ilt_client_info));
11571                 ilt_cli.start = 0;
11572                 ilt_cli.end = ILT_NUM_PAGE_ENTRIES - 1;
11573                 ilt_cli.client_num = ILT_CLIENT_TM;
11574
11575                 ecore_ilt_boundary_init_op(sc, &ilt_cli, 0, INITOP_CLEAR);
11576         }
11577
11578         /* this assumes that reset_port() called before reset_func() */
11579         if (!CHIP_IS_E1x(sc)) {
11580                 bnx2x_pf_disable(sc);
11581         }
11582
11583         sc->dmae_ready = 0;
11584 }
11585
11586 static void bnx2x_release_firmware(struct bnx2x_softc *sc)
11587 {
11588         rte_free(sc->init_ops);
11589         rte_free(sc->init_ops_offsets);
11590         rte_free(sc->init_data);
11591         rte_free(sc->iro_array);
11592 }
11593
11594 static int bnx2x_init_firmware(struct bnx2x_softc *sc)
11595 {
11596         uint32_t len, i;
11597         uint8_t *p = sc->firmware;
11598         uint32_t off[24];
11599
11600         for (i = 0; i < 24; ++i)
11601                 off[i] = rte_be_to_cpu_32(*((uint32_t *) sc->firmware + i));
11602
11603         len = off[0];
11604         sc->init_ops = rte_zmalloc("", len, RTE_CACHE_LINE_SIZE);
11605         if (!sc->init_ops)
11606                 goto alloc_failed;
11607         bnx2x_data_to_init_ops(p + off[1], sc->init_ops, len);
11608
11609         len = off[2];
11610         sc->init_ops_offsets = rte_zmalloc("", len, RTE_CACHE_LINE_SIZE);
11611         if (!sc->init_ops_offsets)
11612                 goto alloc_failed;
11613         bnx2x_data_to_init_offsets(p + off[3], sc->init_ops_offsets, len);
11614
11615         len = off[4];
11616         sc->init_data = rte_zmalloc("", len, RTE_CACHE_LINE_SIZE);
11617         if (!sc->init_data)
11618                 goto alloc_failed;
11619         bnx2x_data_to_init_data(p + off[5], sc->init_data, len);
11620
11621         sc->tsem_int_table_data = p + off[7];
11622         sc->tsem_pram_data = p + off[9];
11623         sc->usem_int_table_data = p + off[11];
11624         sc->usem_pram_data = p + off[13];
11625         sc->csem_int_table_data = p + off[15];
11626         sc->csem_pram_data = p + off[17];
11627         sc->xsem_int_table_data = p + off[19];
11628         sc->xsem_pram_data = p + off[21];
11629
11630         len = off[22];
11631         sc->iro_array = rte_zmalloc("", len, RTE_CACHE_LINE_SIZE);
11632         if (!sc->iro_array)
11633                 goto alloc_failed;
11634         bnx2x_data_to_iro_array(p + off[23], sc->iro_array, len);
11635
11636         return 0;
11637
11638 alloc_failed:
11639         bnx2x_release_firmware(sc);
11640         return -1;
11641 }
11642
11643 static int cut_gzip_prefix(const uint8_t * zbuf, int len)
11644 {
11645 #define MIN_PREFIX_SIZE (10)
11646
11647         int n = MIN_PREFIX_SIZE;
11648         uint16_t xlen;
11649
11650         if (!(zbuf[0] == 0x1f && zbuf[1] == 0x8b && zbuf[2] == Z_DEFLATED) ||
11651             len <= MIN_PREFIX_SIZE) {
11652                 return -1;
11653         }
11654
11655         /* optional extra fields are present */
11656         if (zbuf[3] & 0x4) {
11657                 xlen = zbuf[13];
11658                 xlen <<= 8;
11659                 xlen += zbuf[12];
11660
11661                 n += xlen;
11662         }
11663         /* file name is present */
11664         if (zbuf[3] & 0x8) {
11665                 while ((zbuf[n++] != 0) && (n < len)) ;
11666         }
11667
11668         return n;
11669 }
11670
11671 static int ecore_gunzip(struct bnx2x_softc *sc, const uint8_t * zbuf, int len)
11672 {
11673         int ret;
11674         int data_begin = cut_gzip_prefix(zbuf, len);
11675
11676         PMD_DRV_LOG(DEBUG, sc, "ecore_gunzip %d", len);
11677
11678         if (data_begin <= 0) {
11679                 PMD_DRV_LOG(NOTICE, sc, "bad gzip prefix");
11680                 return -1;
11681         }
11682
11683         memset(&zlib_stream, 0, sizeof(zlib_stream));
11684         zlib_stream.next_in = zbuf + data_begin;
11685         zlib_stream.avail_in = len - data_begin;
11686         zlib_stream.next_out = sc->gz_buf;
11687         zlib_stream.avail_out = FW_BUF_SIZE;
11688
11689         ret = inflateInit2(&zlib_stream, -MAX_WBITS);
11690         if (ret != Z_OK) {
11691                 PMD_DRV_LOG(NOTICE, sc, "zlib inflateInit2 error");
11692                 return ret;
11693         }
11694
11695         ret = inflate(&zlib_stream, Z_FINISH);
11696         if ((ret != Z_STREAM_END) && (ret != Z_OK)) {
11697                 PMD_DRV_LOG(NOTICE, sc, "zlib inflate error: %d %s", ret,
11698                             zlib_stream.msg);
11699         }
11700
11701         sc->gz_outlen = zlib_stream.total_out;
11702         if (sc->gz_outlen & 0x3) {
11703                 PMD_DRV_LOG(NOTICE, sc, "firmware is not aligned. gz_outlen == %d",
11704                             sc->gz_outlen);
11705         }
11706         sc->gz_outlen >>= 2;
11707
11708         inflateEnd(&zlib_stream);
11709
11710         if (ret == Z_STREAM_END)
11711                 return 0;
11712
11713         return ret;
11714 }
11715
11716 static void
11717 ecore_write_dmae_phys_len(struct bnx2x_softc *sc, rte_iova_t phys_addr,
11718                           uint32_t addr, uint32_t len)
11719 {
11720         bnx2x_write_dmae_phys_len(sc, phys_addr, addr, len);
11721 }
11722
11723 void
11724 ecore_storm_memset_struct(struct bnx2x_softc *sc, uint32_t addr, size_t size,
11725                           uint32_t * data)
11726 {
11727         uint8_t i;
11728         for (i = 0; i < size / 4; i++) {
11729                 REG_WR(sc, addr + (i * 4), data[i]);
11730         }
11731 }
11732
11733 static const char *get_ext_phy_type(uint32_t ext_phy_type)
11734 {
11735         uint32_t phy_type_idx = ext_phy_type >> 8;
11736         static const char *types[] =
11737             { "DIRECT", "BNX2X-8071", "BNX2X-8072", "BNX2X-8073",
11738                 "BNX2X-8705", "BNX2X-8706", "BNX2X-8726", "BNX2X-8481", "SFX-7101",
11739                 "BNX2X-8727",
11740                 "BNX2X-8727-NOC", "BNX2X-84823", "NOT_CONN", "FAILURE"
11741         };
11742
11743         if (phy_type_idx < 12)
11744                 return types[phy_type_idx];
11745         else if (PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN == ext_phy_type)
11746                 return types[12];
11747         else
11748                 return types[13];
11749 }
11750
11751 static const char *get_state(uint32_t state)
11752 {
11753         uint32_t state_idx = state >> 12;
11754         static const char *states[] = { "CLOSED", "OPENING_WAIT4_LOAD",
11755                 "OPENING_WAIT4_PORT", "OPEN", "CLOSING_WAIT4_HALT",
11756                 "CLOSING_WAIT4_DELETE", "CLOSING_WAIT4_UNLOAD",
11757                 "UNKNOWN", "UNKNOWN", "UNKNOWN", "UNKNOWN", "UNKNOWN",
11758                 "UNKNOWN", "DISABLED", "DIAG", "ERROR", "UNDEFINED"
11759         };
11760
11761         if (state_idx <= 0xF)
11762                 return states[state_idx];
11763         else
11764                 return states[0x10];
11765 }
11766
11767 static const char *get_recovery_state(uint32_t state)
11768 {
11769         static const char *states[] = { "NONE", "DONE", "INIT",
11770                 "WAIT", "FAILED", "NIC_LOADING"
11771         };
11772         return states[state];
11773 }
11774
11775 static const char *get_rx_mode(uint32_t mode)
11776 {
11777         static const char *modes[] = { "NONE", "NORMAL", "ALLMULTI",
11778                 "PROMISC", "MAX_MULTICAST", "ERROR"
11779         };
11780
11781         if (mode < 0x4)
11782                 return modes[mode];
11783         else if (BNX2X_MAX_MULTICAST == mode)
11784                 return modes[4];
11785         else
11786                 return modes[5];
11787 }
11788
11789 #define BNX2X_INFO_STR_MAX 256
11790 static const char *get_bnx2x_flags(uint32_t flags)
11791 {
11792         int i;
11793         static const char *flag[] = { "ONE_PORT ", "NO_ISCSI ",
11794                 "NO_FCOE ", "NO_WOL ", "USING_DAC ", "USING_MSIX ",
11795                 "USING_MSI ", "DISABLE_MSI ", "UNKNOWN ", "NO_MCP ",
11796                 "SAFC_TX_FLAG ", "MF_FUNC_DIS ", "TX_SWITCHING "
11797         };
11798         static char flag_str[BNX2X_INFO_STR_MAX];
11799         memset(flag_str, 0, BNX2X_INFO_STR_MAX);
11800
11801         for (i = 0; i < 5; i++)
11802                 if (flags & (1 << i)) {
11803                         strlcat(flag_str, flag[i], sizeof(flag_str));
11804                         flags ^= (1 << i);
11805                 }
11806         if (flags) {
11807                 static char unknown[BNX2X_INFO_STR_MAX];
11808                 snprintf(unknown, 32, "Unknown flag mask %x", flags);
11809                 strlcat(flag_str, unknown, sizeof(flag_str));
11810         }
11811         return flag_str;
11812 }
11813
11814 /* Prints useful adapter info. */
11815 void bnx2x_print_adapter_info(struct bnx2x_softc *sc)
11816 {
11817         int i = 0;
11818
11819         PMD_DRV_LOG(INFO, sc, "========================================");
11820         /* DPDK and Driver versions */
11821         PMD_DRV_LOG(INFO, sc, "%12s : %s", "DPDK",
11822                         rte_version());
11823         PMD_DRV_LOG(INFO, sc, "%12s : %s", "Driver",
11824                         bnx2x_pmd_version());
11825         /* Firmware versions. */
11826         PMD_DRV_LOG(INFO, sc, "%12s : %d.%d.%d",
11827                      "Firmware",
11828                      BNX2X_5710_FW_MAJOR_VERSION,
11829                      BNX2X_5710_FW_MINOR_VERSION,
11830                      BNX2X_5710_FW_REVISION_VERSION);
11831         PMD_DRV_LOG(INFO, sc, "%12s : %s",
11832                      "Bootcode", sc->devinfo.bc_ver_str);
11833         /* Hardware chip info. */
11834         PMD_DRV_LOG(INFO, sc, "%12s : %#08x", "ASIC", sc->devinfo.chip_id);
11835         PMD_DRV_LOG(INFO, sc, "%12s : %c%d", "Rev", (CHIP_REV(sc) >> 12) + 'A',
11836                      (CHIP_METAL(sc) >> 4));
11837         /* Bus PCIe info. */
11838         PMD_DRV_LOG(INFO, sc, "%12s : 0x%x", "Vendor Id",
11839                     sc->devinfo.vendor_id);
11840         PMD_DRV_LOG(INFO, sc, "%12s : 0x%x", "Device Id",
11841                     sc->devinfo.device_id);
11842         PMD_DRV_LOG(INFO, sc, "%12s : width x%d, ", "Bus PCIe",
11843                     sc->devinfo.pcie_link_width);
11844         switch (sc->devinfo.pcie_link_speed) {
11845         case 1:
11846                 PMD_DRV_LOG(INFO, sc, "%23s", "2.5 Gbps");
11847                 break;
11848         case 2:
11849                 PMD_DRV_LOG(INFO, sc, "%21s", "5 Gbps");
11850                 break;
11851         case 4:
11852                 PMD_DRV_LOG(INFO, sc, "%21s", "8 Gbps");
11853                 break;
11854         default:
11855                 PMD_DRV_LOG(INFO, sc, "%33s", "Unknown link speed");
11856         }
11857         /* Device features. */
11858         PMD_DRV_LOG(INFO, sc, "%12s : ", "Flags");
11859         /* Miscellaneous flags. */
11860         if (sc->devinfo.pcie_cap_flags & BNX2X_MSI_CAPABLE_FLAG) {
11861                 PMD_DRV_LOG(INFO, sc, "%18s", "MSI");
11862                 i++;
11863         }
11864         if (sc->devinfo.pcie_cap_flags & BNX2X_MSIX_CAPABLE_FLAG) {
11865                 if (i > 0)
11866                         PMD_DRV_LOG(INFO, sc, "|");
11867                 PMD_DRV_LOG(INFO, sc, "%20s", "MSI-X");
11868                 i++;
11869         }
11870         PMD_DRV_LOG(INFO, sc, "%12s : %s", "OVLAN", (OVLAN(sc) ? "YES" : "NO"));
11871         PMD_DRV_LOG(INFO, sc, "%12s : %s", "MF", (IS_MF(sc) ? "YES" : "NO"));
11872         PMD_DRV_LOG(INFO, sc, "========================================");
11873 }
11874
11875 /* Prints useful device info. */
11876 void bnx2x_print_device_info(struct bnx2x_softc *sc)
11877 {
11878         __rte_unused uint32_t ext_phy_type;
11879         uint32_t offset, reg_val;
11880
11881         PMD_INIT_FUNC_TRACE(sc);
11882         offset = offsetof(struct shmem_region,
11883                           dev_info.port_hw_config[0].external_phy_config);
11884         reg_val = REG_RD(sc, sc->devinfo.shmem_base + offset);
11885         if (sc->link_vars.phy_flags & PHY_XGXS_FLAG)
11886                 ext_phy_type = ELINK_XGXS_EXT_PHY_TYPE(reg_val);
11887         else
11888                 ext_phy_type = ELINK_SERDES_EXT_PHY_TYPE(reg_val);
11889
11890         /* Device features. */
11891         PMD_DRV_LOG(INFO, sc, "%12s : %u", "Bnx2x Func", sc->pcie_func);
11892         PMD_DRV_LOG(INFO, sc,
11893                     "%12s : %s", "Bnx2x Flags", get_bnx2x_flags(sc->flags));
11894         PMD_DRV_LOG(INFO, sc, "%12s : %s", "DMAE Is",
11895                      (sc->dmae_ready ? "Ready" : "Not Ready"));
11896         PMD_DRV_LOG(INFO, sc, "%12s : %u", "MTU", sc->mtu);
11897         PMD_DRV_LOG(INFO, sc,
11898                     "%12s : %s", "PHY Type", get_ext_phy_type(ext_phy_type));
11899         PMD_DRV_LOG(INFO, sc, "%12s : %x:%x:%x:%x:%x:%x", "MAC Addr",
11900                         sc->link_params.mac_addr[0],
11901                         sc->link_params.mac_addr[1],
11902                         sc->link_params.mac_addr[2],
11903                         sc->link_params.mac_addr[3],
11904                         sc->link_params.mac_addr[4],
11905                         sc->link_params.mac_addr[5]);
11906         PMD_DRV_LOG(INFO, sc, "%12s : %s", "RX Mode", get_rx_mode(sc->rx_mode));
11907         PMD_DRV_LOG(INFO, sc, "%12s : %s", "State", get_state(sc->state));
11908         if (sc->recovery_state)
11909                 PMD_DRV_LOG(INFO, sc, "%12s : %s", "Recovery",
11910                              get_recovery_state(sc->recovery_state));
11911         /* Queue info. */
11912         if (IS_PF(sc)) {
11913                 switch (sc->sp->rss_rdata.rss_mode) {
11914                 case ETH_RSS_MODE_DISABLED:
11915                         PMD_DRV_LOG(INFO, sc, "%12s : %s", "Queues", "RSS mode - None");
11916                         break;
11917                 case ETH_RSS_MODE_REGULAR:
11918                         PMD_DRV_LOG(INFO, sc, "%12s : %s,", "Queues", "RSS mode - Regular");
11919                         PMD_DRV_LOG(INFO, sc, "%16d", sc->num_queues);
11920                         break;
11921                 default:
11922                         PMD_DRV_LOG(INFO, sc, "%12s : %s", "Queues", "RSS mode - Unknown");
11923                         break;
11924                 }
11925         }
11926         PMD_DRV_LOG(INFO, sc, "%12s : CQ = %lx,  EQ = %lx", "SPQ Left",
11927                      sc->cq_spq_left, sc->eq_spq_left);
11928
11929         PMD_DRV_LOG(INFO, sc,
11930                     "%12s : %x", "Switch", sc->link_params.switch_cfg);
11931         PMD_DRV_LOG(INFO, sc, "pcie_bus=%d, pcie_device=%d",
11932                         sc->pcie_bus, sc->pcie_device);
11933         PMD_DRV_LOG(INFO, sc, "bar0.addr=%p, bar1.addr=%p",
11934                         sc->bar[BAR0].base_addr, sc->bar[BAR1].base_addr);
11935         PMD_DRV_LOG(INFO, sc, "port=%d, path=%d, vnic=%d, func=%d",
11936                         PORT_ID(sc), PATH_ID(sc), VNIC_ID(sc), FUNC_ID(sc));
11937 }