drivers/net/bnx2x/bnx2x.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright (c) 2007-2013 Broadcom Corporation.
   3  *
   4  * Eric Davis        <edavis@broadcom.com>
   5  * David Christensen <davidch@broadcom.com>
   6  * Gary Zambrano     <zambrano@broadcom.com>
   7  *
   8  * Copyright (c) 2013-2015 Brocade Communications Systems, Inc.
   9  * Copyright (c) 2015-2018 Cavium Inc.
  10  * All rights reserved.
  11  * www.cavium.com
  12  */
  13
  14 #define BNX2X_DRIVER_VERSION "1.78.18"
  15
  16 #include "bnx2x.h"
  17 #include "bnx2x_vfpf.h"
  18 #include "ecore_sp.h"
  19 #include "ecore_init.h"
  20 #include "ecore_init_ops.h"
  21
  22 #include "rte_version.h"
  23
  24 #include <sys/types.h>
  25 #include <sys/stat.h>
  26 #include <fcntl.h>
  27 #include <zlib.h>
  28
  29 #define BNX2X_PMD_VER_PREFIX "BNX2X PMD"
  30 #define BNX2X_PMD_VERSION_MAJOR 1
  31 #define BNX2X_PMD_VERSION_MINOR 0
  32 #define BNX2X_PMD_VERSION_REVISION 7
  33 #define BNX2X_PMD_VERSION_PATCH 1
  34
  35 static inline const char *
  36 bnx2x_pmd_version(void)
  37 {
  38         static char version[32];
  39
  40         snprintf(version, sizeof(version), "%s %s_%d.%d.%d.%d",
  41                         BNX2X_PMD_VER_PREFIX,
  42                         BNX2X_DRIVER_VERSION,
  43                         BNX2X_PMD_VERSION_MAJOR,
  44                         BNX2X_PMD_VERSION_MINOR,
  45                         BNX2X_PMD_VERSION_REVISION,
  46                         BNX2X_PMD_VERSION_PATCH);
  47
  48         return version;
  49 }
  50
  51 static z_stream zlib_stream;
  52
  53 #define EVL_VLID_MASK 0x0FFF
  54
  55 #define BNX2X_DEF_SB_ATT_IDX 0x0001
  56 #define BNX2X_DEF_SB_IDX     0x0002
  57
  58 /*
  59  * FLR Support - bnx2x_pf_flr_clnup() is called during nic_load in the per
  60  * function HW initialization.
  61  */
  62 #define FLR_WAIT_USEC     10000 /* 10 msecs */
  63 #define FLR_WAIT_INTERVAL 50    /* usecs */
  64 #define FLR_POLL_CNT      (FLR_WAIT_USEC / FLR_WAIT_INTERVAL)   /* 200 */
  65
  66 struct pbf_pN_buf_regs {
  67         int pN;
  68         uint32_t init_crd;
  69         uint32_t crd;
  70         uint32_t crd_freed;
  71 };
  72
  73 struct pbf_pN_cmd_regs {
  74         int pN;
  75         uint32_t lines_occup;
  76         uint32_t lines_freed;
  77 };
  78
  79 /* resources needed for unloading a previously loaded device */
  80
  81 #define BNX2X_PREV_WAIT_NEEDED 1
  82 rte_spinlock_t bnx2x_prev_mtx;
  83 struct bnx2x_prev_list_node {
  84         LIST_ENTRY(bnx2x_prev_list_node) node;
  85         uint8_t bus;
  86         uint8_t slot;
  87         uint8_t path;
  88         uint8_t aer;
  89         uint8_t undi;
  90 };
  91
  92 static LIST_HEAD(, bnx2x_prev_list_node) bnx2x_prev_list
  93         = LIST_HEAD_INITIALIZER(bnx2x_prev_list);
  94
  95 static int load_count[2][3] = { { 0 } };
  96         /* per-path: 0-common, 1-port0, 2-port1 */
  97
  98 static void bnx2x_cmng_fns_init(struct bnx2x_softc *sc, uint8_t read_cfg,
  99                                 uint8_t cmng_type);
 100 static int bnx2x_get_cmng_fns_mode(struct bnx2x_softc *sc);
 101 static void storm_memset_cmng(struct bnx2x_softc *sc, struct cmng_init *cmng,
 102                               uint8_t port);
 103 static void bnx2x_set_reset_global(struct bnx2x_softc *sc);
 104 static void bnx2x_set_reset_in_progress(struct bnx2x_softc *sc);
 105 static uint8_t bnx2x_reset_is_done(struct bnx2x_softc *sc, int engine);
 106 static uint8_t bnx2x_clear_pf_load(struct bnx2x_softc *sc);
 107 static uint8_t bnx2x_chk_parity_attn(struct bnx2x_softc *sc, uint8_t * global,
 108                                      uint8_t print);
 109 static void bnx2x_int_disable(struct bnx2x_softc *sc);
 110 static int bnx2x_release_leader_lock(struct bnx2x_softc *sc);
 111 static void bnx2x_pf_disable(struct bnx2x_softc *sc);
 112 static void bnx2x_update_rx_prod(struct bnx2x_softc *sc,
 113                                  struct bnx2x_fastpath *fp,
 114                                  uint16_t rx_bd_prod, uint16_t rx_cq_prod);
 115 static void bnx2x_link_report_locked(struct bnx2x_softc *sc);
 116 static void bnx2x_link_report(struct bnx2x_softc *sc);
 117 void bnx2x_link_status_update(struct bnx2x_softc *sc);
 118 static int bnx2x_alloc_mem(struct bnx2x_softc *sc);
 119 static void bnx2x_free_mem(struct bnx2x_softc *sc);
 120 static int bnx2x_alloc_fw_stats_mem(struct bnx2x_softc *sc);
 121 static void bnx2x_free_fw_stats_mem(struct bnx2x_softc *sc);
 122 static __rte_noinline
 123 int bnx2x_nic_load(struct bnx2x_softc *sc);
 124
 125 static int bnx2x_handle_sp_tq(struct bnx2x_softc *sc);
 126 static void bnx2x_handle_fp_tq(struct bnx2x_fastpath *fp, int scan_fp);
 127 static void bnx2x_ack_sb(struct bnx2x_softc *sc, uint8_t igu_sb_id,
 128                          uint8_t storm, uint16_t index, uint8_t op,
 129                          uint8_t update);
 130
 131 int bnx2x_test_bit(int nr, volatile unsigned long *addr)
 132 {
 133         int res;
 134
 135         mb();
 136         res = ((*addr) & (1UL << nr)) != 0;
 137         mb();
 138         return res;
 139 }
 140
 141 void bnx2x_set_bit(unsigned int nr, volatile unsigned long *addr)
 142 {
 143         __sync_fetch_and_or(addr, (1UL << nr));
 144 }
 145
 146 void bnx2x_clear_bit(int nr, volatile unsigned long *addr)
 147 {
 148         __sync_fetch_and_and(addr, ~(1UL << nr));
 149 }
 150
 151 int bnx2x_test_and_clear_bit(int nr, volatile unsigned long *addr)
 152 {
 153         unsigned long mask = (1UL << nr);
 154         return __sync_fetch_and_and(addr, ~mask) & mask;
 155 }
 156
 157 int bnx2x_cmpxchg(volatile int *addr, int old, int new)
 158 {
 159         return __sync_val_compare_and_swap(addr, old, new);
 160 }
 161
 162 int
 163 bnx2x_dma_alloc(struct bnx2x_softc *sc, size_t size, struct bnx2x_dma *dma,
 164               const char *msg, uint32_t align)
 165 {
 166         char mz_name[RTE_MEMZONE_NAMESIZE];
 167         const struct rte_memzone *z;
 168
 169         dma->sc = sc;
 170         if (IS_PF(sc))
 171                 snprintf(mz_name, sizeof(mz_name), "bnx2x%d_%s_%" PRIx64, SC_ABS_FUNC(sc), msg,
 172                         rte_get_timer_cycles());
 173         else
 174                 snprintf(mz_name, sizeof(mz_name), "bnx2x%d_%s_%" PRIx64, sc->pcie_device, msg,
 175                         rte_get_timer_cycles());
 176
 177         /* Caller must take care that strlen(mz_name) < RTE_MEMZONE_NAMESIZE */
 178         z = rte_memzone_reserve_aligned(mz_name, (uint64_t)size,
 179                                         SOCKET_ID_ANY,
 180                                         RTE_MEMZONE_IOVA_CONTIG, align);
 181         if (z == NULL) {
 182                 PMD_DRV_LOG(ERR, sc, "DMA alloc failed for %s", msg);
 183                 return -ENOMEM;
 184         }
 185         dma->paddr = (uint64_t) z->iova;
 186         dma->vaddr = z->addr;
 187
 188         PMD_DRV_LOG(DEBUG, sc,
 189                     "%s: virt=%p phys=%" PRIx64, msg, dma->vaddr, dma->paddr);
 190
 191         return 0;
 192 }
 193
 194 static int bnx2x_acquire_hw_lock(struct bnx2x_softc *sc, uint32_t resource)
 195 {
 196         uint32_t lock_status;
 197         uint32_t resource_bit = (1 << resource);
 198         int func = SC_FUNC(sc);
 199         uint32_t hw_lock_control_reg;
 200         int cnt;
 201
 202 #ifndef RTE_LIBRTE_BNX2X_DEBUG_PERIODIC
 203         if (resource)
 204                 PMD_INIT_FUNC_TRACE(sc);
 205 #else
 206         PMD_INIT_FUNC_TRACE(sc);
 207 #endif
 208
 209         /* validate the resource is within range */
 210         if (resource > HW_LOCK_MAX_RESOURCE_VALUE) {
 211                 PMD_DRV_LOG(NOTICE, sc,
 212                             "resource 0x%x > HW_LOCK_MAX_RESOURCE_VALUE",
 213                             resource);
 214                 return -1;
 215         }
 216
 217         if (func <= 5) {
 218                 hw_lock_control_reg = (MISC_REG_DRIVER_CONTROL_1 + (func * 8));
 219         } else {
 220                 hw_lock_control_reg =
 221                     (MISC_REG_DRIVER_CONTROL_7 + ((func - 6) * 8));
 222         }
 223
 224         /* validate the resource is not already taken */
 225         lock_status = REG_RD(sc, hw_lock_control_reg);
 226         if (lock_status & resource_bit) {
 227                 PMD_DRV_LOG(NOTICE, sc,
 228                             "resource in use (status 0x%x bit 0x%x)",
 229                             lock_status, resource_bit);
 230                 return -1;
 231         }
 232
 233         /* try every 5ms for 5 seconds */
 234         for (cnt = 0; cnt < 1000; cnt++) {
 235                 REG_WR(sc, (hw_lock_control_reg + 4), resource_bit);
 236                 lock_status = REG_RD(sc, hw_lock_control_reg);
 237                 if (lock_status & resource_bit) {
 238                         return 0;
 239                 }
 240                 DELAY(5000);
 241         }
 242
 243         PMD_DRV_LOG(NOTICE, sc, "Resource 0x%x resource_bit 0x%x lock timeout!",
 244                     resource, resource_bit);
 245         return -1;
 246 }
 247
 248 static int bnx2x_release_hw_lock(struct bnx2x_softc *sc, uint32_t resource)
 249 {
 250         uint32_t lock_status;
 251         uint32_t resource_bit = (1 << resource);
 252         int func = SC_FUNC(sc);
 253         uint32_t hw_lock_control_reg;
 254
 255 #ifndef RTE_LIBRTE_BNX2X_DEBUG_PERIODIC
 256         if (resource)
 257                 PMD_INIT_FUNC_TRACE(sc);
 258 #else
 259         PMD_INIT_FUNC_TRACE(sc);
 260 #endif
 261
 262         /* validate the resource is within range */
 263         if (resource > HW_LOCK_MAX_RESOURCE_VALUE) {
 264                 PMD_DRV_LOG(NOTICE, sc,
 265                             "(resource 0x%x > HW_LOCK_MAX_RESOURCE_VALUE)"
 266                             " resource_bit 0x%x", resource, resource_bit);
 267                 return -1;
 268         }
 269
 270         if (func <= 5) {
 271                 hw_lock_control_reg = (MISC_REG_DRIVER_CONTROL_1 + (func * 8));
 272         } else {
 273                 hw_lock_control_reg =
 274                     (MISC_REG_DRIVER_CONTROL_7 + ((func - 6) * 8));
 275         }
 276
 277         /* validate the resource is currently taken */
 278         lock_status = REG_RD(sc, hw_lock_control_reg);
 279         if (!(lock_status & resource_bit)) {
 280                 PMD_DRV_LOG(NOTICE, sc,
 281                             "resource not in use (status 0x%x bit 0x%x)",
 282                             lock_status, resource_bit);
 283                 return -1;
 284         }
 285
 286         REG_WR(sc, hw_lock_control_reg, resource_bit);
 287         return 0;
 288 }
 289
 290 static void bnx2x_acquire_phy_lock(struct bnx2x_softc *sc)
 291 {
 292         BNX2X_PHY_LOCK(sc);
 293         bnx2x_acquire_hw_lock(sc, HW_LOCK_RESOURCE_MDIO);
 294 }
 295
 296 static void bnx2x_release_phy_lock(struct bnx2x_softc *sc)
 297 {
 298         bnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_MDIO);
 299         BNX2X_PHY_UNLOCK(sc);
 300 }
 301
 302 /* copy command into DMAE command memory and set DMAE command Go */
 303 void bnx2x_post_dmae(struct bnx2x_softc *sc, struct dmae_command *dmae, int idx)
 304 {
 305         uint32_t cmd_offset;
 306         uint32_t i;
 307
 308         cmd_offset = (DMAE_REG_CMD_MEM + (sizeof(struct dmae_command) * idx));
 309         for (i = 0; i < ((sizeof(struct dmae_command) / 4)); i++) {
 310                 REG_WR(sc, (cmd_offset + (i * 4)), *(((uint32_t *) dmae) + i));
 311         }
 312
 313         REG_WR(sc, dmae_reg_go_c[idx], 1);
 314 }
 315
 316 uint32_t bnx2x_dmae_opcode_add_comp(uint32_t opcode, uint8_t comp_type)
 317 {
 318         return opcode | ((comp_type << DMAE_COMMAND_C_DST_SHIFT) |
 319                           DMAE_COMMAND_C_TYPE_ENABLE);
 320 }
 321
 322 uint32_t bnx2x_dmae_opcode_clr_src_reset(uint32_t opcode)
 323 {
 324         return opcode & ~DMAE_COMMAND_SRC_RESET;
 325 }
 326
 327 uint32_t
 328 bnx2x_dmae_opcode(struct bnx2x_softc * sc, uint8_t src_type, uint8_t dst_type,
 329                 uint8_t with_comp, uint8_t comp_type)
 330 {
 331         uint32_t opcode = 0;
 332
 333         opcode |= ((src_type << DMAE_COMMAND_SRC_SHIFT) |
 334                    (dst_type << DMAE_COMMAND_DST_SHIFT));
 335
 336         opcode |= (DMAE_COMMAND_SRC_RESET | DMAE_COMMAND_DST_RESET);
 337
 338         opcode |= (SC_PORT(sc) ? DMAE_CMD_PORT_1 : DMAE_CMD_PORT_0);
 339
 340         opcode |= ((SC_VN(sc) << DMAE_COMMAND_E1HVN_SHIFT) |
 341                    (SC_VN(sc) << DMAE_COMMAND_DST_VN_SHIFT));
 342
 343         opcode |= (DMAE_COM_SET_ERR << DMAE_COMMAND_ERR_POLICY_SHIFT);
 344
 345 #ifdef __BIG_ENDIAN
 346         opcode |= DMAE_CMD_ENDIANITY_B_DW_SWAP;
 347 #else
 348         opcode |= DMAE_CMD_ENDIANITY_DW_SWAP;
 349 #endif
 350
 351         if (with_comp) {
 352                 opcode = bnx2x_dmae_opcode_add_comp(opcode, comp_type);
 353         }
 354
 355         return opcode;
 356 }
 357
 358 static void
 359 bnx2x_prep_dmae_with_comp(struct bnx2x_softc *sc, struct dmae_command *dmae,
 360                         uint8_t src_type, uint8_t dst_type)
 361 {
 362         memset(dmae, 0, sizeof(struct dmae_command));
 363
 364         /* set the opcode */
 365         dmae->opcode = bnx2x_dmae_opcode(sc, src_type, dst_type,
 366                                        TRUE, DMAE_COMP_PCI);
 367
 368         /* fill in the completion parameters */
 369         dmae->comp_addr_lo = U64_LO(BNX2X_SP_MAPPING(sc, wb_comp));
 370         dmae->comp_addr_hi = U64_HI(BNX2X_SP_MAPPING(sc, wb_comp));
 371         dmae->comp_val = DMAE_COMP_VAL;
 372 }
 373
 374 /* issue a DMAE command over the init channel and wait for completion */
 375 static int
 376 bnx2x_issue_dmae_with_comp(struct bnx2x_softc *sc, struct dmae_command *dmae)
 377 {
 378         uint32_t *wb_comp = BNX2X_SP(sc, wb_comp);
 379         int timeout = CHIP_REV_IS_SLOW(sc) ? 400000 : 4000;
 380
 381         /* reset completion */
 382         *wb_comp = 0;
 383
 384         /* post the command on the channel used for initializations */
 385         bnx2x_post_dmae(sc, dmae, INIT_DMAE_C(sc));
 386
 387         /* wait for completion */
 388         DELAY(500);
 389
 390         while ((*wb_comp & ~DMAE_PCI_ERR_FLAG) != DMAE_COMP_VAL) {
 391                 if (!timeout ||
 392                     (sc->recovery_state != BNX2X_RECOVERY_DONE &&
 393                      sc->recovery_state != BNX2X_RECOVERY_NIC_LOADING)) {
 394                         PMD_DRV_LOG(INFO, sc, "DMAE timeout!");
 395                         return DMAE_TIMEOUT;
 396                 }
 397
 398                 timeout--;
 399                 DELAY(50);
 400         }
 401
 402         if (*wb_comp & DMAE_PCI_ERR_FLAG) {
 403                 PMD_DRV_LOG(INFO, sc, "DMAE PCI error!");
 404                 return DMAE_PCI_ERROR;
 405         }
 406
 407         return 0;
 408 }
 409
 410 void bnx2x_read_dmae(struct bnx2x_softc *sc, uint32_t src_addr, uint32_t len32)
 411 {
 412         struct dmae_command dmae;
 413         uint32_t *data;
 414         uint32_t i;
 415         int rc;
 416
 417         if (!sc->dmae_ready) {
 418                 data = BNX2X_SP(sc, wb_data[0]);
 419
 420                 for (i = 0; i < len32; i++) {
 421                         data[i] = REG_RD(sc, (src_addr + (i * 4)));
 422                 }
 423
 424                 return;
 425         }
 426
 427         /* set opcode and fixed command fields */
 428         bnx2x_prep_dmae_with_comp(sc, &dmae, DMAE_SRC_GRC, DMAE_DST_PCI);
 429
 430         /* fill in addresses and len */
 431         dmae.src_addr_lo = (src_addr >> 2);     /* GRC addr has dword resolution */
 432         dmae.src_addr_hi = 0;
 433         dmae.dst_addr_lo = U64_LO(BNX2X_SP_MAPPING(sc, wb_data));
 434         dmae.dst_addr_hi = U64_HI(BNX2X_SP_MAPPING(sc, wb_data));
 435         dmae.len = len32;
 436
 437         /* issue the command and wait for completion */
 438         if ((rc = bnx2x_issue_dmae_with_comp(sc, &dmae)) != 0) {
 439                 rte_panic("DMAE failed (%d)", rc);
 440         };
 441 }
 442
 443 void
 444 bnx2x_write_dmae(struct bnx2x_softc *sc, rte_iova_t dma_addr, uint32_t dst_addr,
 445                uint32_t len32)
 446 {
 447         struct dmae_command dmae;
 448         int rc;
 449
 450         if (!sc->dmae_ready) {
 451                 ecore_init_str_wr(sc, dst_addr, BNX2X_SP(sc, wb_data[0]), len32);
 452                 return;
 453         }
 454
 455         /* set opcode and fixed command fields */
 456         bnx2x_prep_dmae_with_comp(sc, &dmae, DMAE_SRC_PCI, DMAE_DST_GRC);
 457
 458         /* fill in addresses and len */
 459         dmae.src_addr_lo = U64_LO(dma_addr);
 460         dmae.src_addr_hi = U64_HI(dma_addr);
 461         dmae.dst_addr_lo = (dst_addr >> 2);     /* GRC addr has dword resolution */
 462         dmae.dst_addr_hi = 0;
 463         dmae.len = len32;
 464
 465         /* issue the command and wait for completion */
 466         if ((rc = bnx2x_issue_dmae_with_comp(sc, &dmae)) != 0) {
 467                 rte_panic("DMAE failed (%d)", rc);
 468         }
 469 }
 470
 471 static void
 472 bnx2x_write_dmae_phys_len(struct bnx2x_softc *sc, rte_iova_t phys_addr,
 473                         uint32_t addr, uint32_t len)
 474 {
 475         uint32_t dmae_wr_max = DMAE_LEN32_WR_MAX(sc);
 476         uint32_t offset = 0;
 477
 478         while (len > dmae_wr_max) {
 479                 bnx2x_write_dmae(sc, (phys_addr + offset),      /* src DMA address */
 480                                (addr + offset), /* dst GRC address */
 481                                dmae_wr_max);
 482                 offset += (dmae_wr_max * 4);
 483                 len -= dmae_wr_max;
 484         }
 485
 486         bnx2x_write_dmae(sc, (phys_addr + offset),      /* src DMA address */
 487                        (addr + offset), /* dst GRC address */
 488                        len);
 489 }
 490
 491 void
 492 bnx2x_set_ctx_validation(struct bnx2x_softc *sc, struct eth_context *cxt,
 493                        uint32_t cid)
 494 {
 495         /* ustorm cxt validation */
 496         cxt->ustorm_ag_context.cdu_usage =
 497             CDU_RSRVD_VALUE_TYPE_A(HW_CID(sc, cid),
 498                                    CDU_REGION_NUMBER_UCM_AG,
 499                                    ETH_CONNECTION_TYPE);
 500         /* xcontext validation */
 501         cxt->xstorm_ag_context.cdu_reserved =
 502             CDU_RSRVD_VALUE_TYPE_A(HW_CID(sc, cid),
 503                                    CDU_REGION_NUMBER_XCM_AG,
 504                                    ETH_CONNECTION_TYPE);
 505 }
 506
 507 static void
 508 bnx2x_storm_memset_hc_timeout(struct bnx2x_softc *sc, uint8_t fw_sb_id,
 509                             uint8_t sb_index, uint8_t ticks)
 510 {
 511         uint32_t addr =
 512             (BAR_CSTRORM_INTMEM +
 513              CSTORM_STATUS_BLOCK_DATA_TIMEOUT_OFFSET(fw_sb_id, sb_index));
 514
 515         REG_WR8(sc, addr, ticks);
 516 }
 517
 518 static void
 519 bnx2x_storm_memset_hc_disable(struct bnx2x_softc *sc, uint16_t fw_sb_id,
 520                             uint8_t sb_index, uint8_t disable)
 521 {
 522         uint32_t enable_flag =
 523             (disable) ? 0 : (1 << HC_INDEX_DATA_HC_ENABLED_SHIFT);
 524         uint32_t addr =
 525             (BAR_CSTRORM_INTMEM +
 526              CSTORM_STATUS_BLOCK_DATA_FLAGS_OFFSET(fw_sb_id, sb_index));
 527         uint8_t flags;
 528
 529         /* clear and set */
 530         flags = REG_RD8(sc, addr);
 531         flags &= ~HC_INDEX_DATA_HC_ENABLED;
 532         flags |= enable_flag;
 533         REG_WR8(sc, addr, flags);
 534 }
 535
 536 void
 537 bnx2x_update_coalesce_sb_index(struct bnx2x_softc *sc, uint8_t fw_sb_id,
 538                              uint8_t sb_index, uint8_t disable, uint16_t usec)
 539 {
 540         uint8_t ticks = (usec / 4);
 541
 542         bnx2x_storm_memset_hc_timeout(sc, fw_sb_id, sb_index, ticks);
 543
 544         disable = (disable) ? 1 : ((usec) ? 0 : 1);
 545         bnx2x_storm_memset_hc_disable(sc, fw_sb_id, sb_index, disable);
 546 }
 547
 548 uint32_t elink_cb_reg_read(struct bnx2x_softc *sc, uint32_t reg_addr)
 549 {
 550         return REG_RD(sc, reg_addr);
 551 }
 552
 553 void elink_cb_reg_write(struct bnx2x_softc *sc, uint32_t reg_addr, uint32_t val)
 554 {
 555         REG_WR(sc, reg_addr, val);
 556 }
 557
 558 void
 559 elink_cb_event_log(__rte_unused struct bnx2x_softc *sc,
 560                    __rte_unused const elink_log_id_t elink_log_id, ...)
 561 {
 562         PMD_DRV_LOG(DEBUG, sc, "ELINK EVENT LOG (%d)", elink_log_id);
 563 }
 564
 565 static int bnx2x_set_spio(struct bnx2x_softc *sc, int spio, uint32_t mode)
 566 {
 567         uint32_t spio_reg;
 568
 569         /* Only 2 SPIOs are configurable */
 570         if ((spio != MISC_SPIO_SPIO4) && (spio != MISC_SPIO_SPIO5)) {
 571                 PMD_DRV_LOG(NOTICE, sc, "Invalid SPIO 0x%x", spio);
 572                 return -1;
 573         }
 574
 575         bnx2x_acquire_hw_lock(sc, HW_LOCK_RESOURCE_SPIO);
 576
 577         /* read SPIO and mask except the float bits */
 578         spio_reg = (REG_RD(sc, MISC_REG_SPIO) & MISC_SPIO_FLOAT);
 579
 580         switch (mode) {
 581         case MISC_SPIO_OUTPUT_LOW:
 582                 /* clear FLOAT and set CLR */
 583                 spio_reg &= ~(spio << MISC_SPIO_FLOAT_POS);
 584                 spio_reg |= (spio << MISC_SPIO_CLR_POS);
 585                 break;
 586
 587         case MISC_SPIO_OUTPUT_HIGH:
 588                 /* clear FLOAT and set SET */
 589                 spio_reg &= ~(spio << MISC_SPIO_FLOAT_POS);
 590                 spio_reg |= (spio << MISC_SPIO_SET_POS);
 591                 break;
 592
 593         case MISC_SPIO_INPUT_HI_Z:
 594                 /* set FLOAT */
 595                 spio_reg |= (spio << MISC_SPIO_FLOAT_POS);
 596                 break;
 597
 598         default:
 599                 break;
 600         }
 601
 602         REG_WR(sc, MISC_REG_SPIO, spio_reg);
 603         bnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_SPIO);
 604
 605         return 0;
 606 }
 607
 608 static int bnx2x_gpio_read(struct bnx2x_softc *sc, int gpio_num, uint8_t port)
 609 {
 610         /* The GPIO should be swapped if swap register is set and active */
 611         int gpio_port = ((REG_RD(sc, NIG_REG_PORT_SWAP) &&
 612                           REG_RD(sc, NIG_REG_STRAP_OVERRIDE)) ^ port);
 613         int gpio_shift = gpio_num;
 614         if (gpio_port)
 615                 gpio_shift += MISC_REGISTERS_GPIO_PORT_SHIFT;
 616
 617         uint32_t gpio_mask = (1 << gpio_shift);
 618         uint32_t gpio_reg;
 619
 620         if (gpio_num > MISC_REGISTERS_GPIO_3) {
 621                 PMD_DRV_LOG(NOTICE, sc, "Invalid GPIO %d", gpio_num);
 622                 return -1;
 623         }
 624
 625         /* read GPIO value */
 626         gpio_reg = REG_RD(sc, MISC_REG_GPIO);
 627
 628         /* get the requested pin value */
 629         return ((gpio_reg & gpio_mask) == gpio_mask) ? 1 : 0;
 630 }
 631
 632 static int
 633 bnx2x_gpio_write(struct bnx2x_softc *sc, int gpio_num, uint32_t mode, uint8_t port)
 634 {
 635         /* The GPIO should be swapped if swap register is set and active */
 636         int gpio_port = ((REG_RD(sc, NIG_REG_PORT_SWAP) &&
 637                           REG_RD(sc, NIG_REG_STRAP_OVERRIDE)) ^ port);
 638         int gpio_shift = gpio_num;
 639         if (gpio_port)
 640                 gpio_shift += MISC_REGISTERS_GPIO_PORT_SHIFT;
 641
 642         uint32_t gpio_mask = (1 << gpio_shift);
 643         uint32_t gpio_reg;
 644
 645         if (gpio_num > MISC_REGISTERS_GPIO_3) {
 646                 PMD_DRV_LOG(NOTICE, sc, "Invalid GPIO %d", gpio_num);
 647                 return -1;
 648         }
 649
 650         bnx2x_acquire_hw_lock(sc, HW_LOCK_RESOURCE_GPIO);
 651
 652         /* read GPIO and mask except the float bits */
 653         gpio_reg = (REG_RD(sc, MISC_REG_GPIO) & MISC_REGISTERS_GPIO_FLOAT);
 654
 655         switch (mode) {
 656         case MISC_REGISTERS_GPIO_OUTPUT_LOW:
 657                 /* clear FLOAT and set CLR */
 658                 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS);
 659                 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_CLR_POS);
 660                 break;
 661
 662         case MISC_REGISTERS_GPIO_OUTPUT_HIGH:
 663                 /* clear FLOAT and set SET */
 664                 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS);
 665                 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_SET_POS);
 666                 break;
 667
 668         case MISC_REGISTERS_GPIO_INPUT_HI_Z:
 669                 /* set FLOAT */
 670                 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS);
 671                 break;
 672
 673         default:
 674                 break;
 675         }
 676
 677         REG_WR(sc, MISC_REG_GPIO, gpio_reg);
 678         bnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_GPIO);
 679
 680         return 0;
 681 }
 682
 683 static int
 684 bnx2x_gpio_mult_write(struct bnx2x_softc *sc, uint8_t pins, uint32_t mode)
 685 {
 686         uint32_t gpio_reg;
 687
 688         /* any port swapping should be handled by caller */
 689
 690         bnx2x_acquire_hw_lock(sc, HW_LOCK_RESOURCE_GPIO);
 691
 692         /* read GPIO and mask except the float bits */
 693         gpio_reg = REG_RD(sc, MISC_REG_GPIO);
 694         gpio_reg &= ~(pins << MISC_REGISTERS_GPIO_FLOAT_POS);
 695         gpio_reg &= ~(pins << MISC_REGISTERS_GPIO_CLR_POS);
 696         gpio_reg &= ~(pins << MISC_REGISTERS_GPIO_SET_POS);
 697
 698         switch (mode) {
 699         case MISC_REGISTERS_GPIO_OUTPUT_LOW:
 700                 /* set CLR */
 701                 gpio_reg |= (pins << MISC_REGISTERS_GPIO_CLR_POS);
 702                 break;
 703
 704         case MISC_REGISTERS_GPIO_OUTPUT_HIGH:
 705                 /* set SET */
 706                 gpio_reg |= (pins << MISC_REGISTERS_GPIO_SET_POS);
 707                 break;
 708
 709         case MISC_REGISTERS_GPIO_INPUT_HI_Z:
 710                 /* set FLOAT */
 711                 gpio_reg |= (pins << MISC_REGISTERS_GPIO_FLOAT_POS);
 712                 break;
 713
 714         default:
 715                 PMD_DRV_LOG(NOTICE, sc,
 716                             "Invalid GPIO mode assignment %d", mode);
 717                 bnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_GPIO);
 718                 return -1;
 719         }
 720
 721         REG_WR(sc, MISC_REG_GPIO, gpio_reg);
 722         bnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_GPIO);
 723
 724         return 0;
 725 }
 726
 727 static int
 728 bnx2x_gpio_int_write(struct bnx2x_softc *sc, int gpio_num, uint32_t mode,
 729                    uint8_t port)
 730 {
 731         /* The GPIO should be swapped if swap register is set and active */
 732         int gpio_port = ((REG_RD(sc, NIG_REG_PORT_SWAP) &&
 733                           REG_RD(sc, NIG_REG_STRAP_OVERRIDE)) ^ port);
 734         int gpio_shift = gpio_num;
 735         if (gpio_port)
 736                 gpio_shift += MISC_REGISTERS_GPIO_PORT_SHIFT;
 737
 738         uint32_t gpio_mask = (1 << gpio_shift);
 739         uint32_t gpio_reg;
 740
 741         if (gpio_num > MISC_REGISTERS_GPIO_3) {
 742                 PMD_DRV_LOG(NOTICE, sc, "Invalid GPIO %d", gpio_num);
 743                 return -1;
 744         }
 745
 746         bnx2x_acquire_hw_lock(sc, HW_LOCK_RESOURCE_GPIO);
 747
 748         /* read GPIO int */
 749         gpio_reg = REG_RD(sc, MISC_REG_GPIO_INT);
 750
 751         switch (mode) {
 752         case MISC_REGISTERS_GPIO_INT_OUTPUT_CLR:
 753                 /* clear SET and set CLR */
 754                 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_INT_SET_POS);
 755                 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_INT_CLR_POS);
 756                 break;
 757
 758         case MISC_REGISTERS_GPIO_INT_OUTPUT_SET:
 759                 /* clear CLR and set SET */
 760                 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_INT_CLR_POS);
 761                 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_INT_SET_POS);
 762                 break;
 763
 764         default:
 765                 break;
 766         }
 767
 768         REG_WR(sc, MISC_REG_GPIO_INT, gpio_reg);
 769         bnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_GPIO);
 770
 771         return 0;
 772 }
 773
 774 uint32_t
 775 elink_cb_gpio_read(struct bnx2x_softc * sc, uint16_t gpio_num, uint8_t port)
 776 {
 777         return bnx2x_gpio_read(sc, gpio_num, port);
 778 }
 779
 780 uint8_t elink_cb_gpio_write(struct bnx2x_softc * sc, uint16_t gpio_num, uint8_t mode,   /* 0=low 1=high */
 781                             uint8_t port)
 782 {
 783         return bnx2x_gpio_write(sc, gpio_num, mode, port);
 784 }
 785
 786 uint8_t
 787 elink_cb_gpio_mult_write(struct bnx2x_softc * sc, uint8_t pins,
 788                          uint8_t mode /* 0=low 1=high */ )
 789 {
 790         return bnx2x_gpio_mult_write(sc, pins, mode);
 791 }
 792
 793 uint8_t elink_cb_gpio_int_write(struct bnx2x_softc * sc, uint16_t gpio_num, uint8_t mode,       /* 0=low 1=high */
 794                                 uint8_t port)
 795 {
 796         return bnx2x_gpio_int_write(sc, gpio_num, mode, port);
 797 }
 798
 799 void elink_cb_notify_link_changed(struct bnx2x_softc *sc)
 800 {
 801         REG_WR(sc, (MISC_REG_AEU_GENERAL_ATTN_12 +
 802                     (SC_FUNC(sc) * sizeof(uint32_t))), 1);
 803 }
 804
 805 /* send the MCP a request, block until there is a reply */
 806 uint32_t
 807 elink_cb_fw_command(struct bnx2x_softc *sc, uint32_t command, uint32_t param)
 808 {
 809         int mb_idx = SC_FW_MB_IDX(sc);
 810         uint32_t seq;
 811         uint32_t rc = 0;
 812         uint32_t cnt = 1;
 813         uint8_t delay = CHIP_REV_IS_SLOW(sc) ? 100 : 10;
 814
 815         seq = ++sc->fw_seq;
 816         SHMEM_WR(sc, func_mb[mb_idx].drv_mb_param, param);
 817         SHMEM_WR(sc, func_mb[mb_idx].drv_mb_header, (command | seq));
 818
 819         PMD_DRV_LOG(DEBUG, sc,
 820                     "wrote command 0x%08x to FW MB param 0x%08x",
 821                     (command | seq), param);
 822
 823         /* Let the FW do it's magic. GIve it up to 5 seconds... */
 824         do {
 825                 DELAY(delay * 1000);
 826                 rc = SHMEM_RD(sc, func_mb[mb_idx].fw_mb_header);
 827         } while ((seq != (rc & FW_MSG_SEQ_NUMBER_MASK)) && (cnt++ < 500));
 828
 829         /* is this a reply to our command? */
 830         if (seq == (rc & FW_MSG_SEQ_NUMBER_MASK)) {
 831                 rc &= FW_MSG_CODE_MASK;
 832         } else {
 833                 /* Ruh-roh! */
 834                 PMD_DRV_LOG(NOTICE, sc, "FW failed to respond!");
 835                 rc = 0;
 836         }
 837
 838         return rc;
 839 }
 840
 841 static uint32_t
 842 bnx2x_fw_command(struct bnx2x_softc *sc, uint32_t command, uint32_t param)
 843 {
 844         return elink_cb_fw_command(sc, command, param);
 845 }
 846
 847 static void
 848 __storm_memset_dma_mapping(struct bnx2x_softc *sc, uint32_t addr,
 849                            rte_iova_t mapping)
 850 {
 851         REG_WR(sc, addr, U64_LO(mapping));
 852         REG_WR(sc, (addr + 4), U64_HI(mapping));
 853 }
 854
 855 static void
 856 storm_memset_spq_addr(struct bnx2x_softc *sc, rte_iova_t mapping,
 857                       uint16_t abs_fid)
 858 {
 859         uint32_t addr = (XSEM_REG_FAST_MEMORY +
 860                          XSTORM_SPQ_PAGE_BASE_OFFSET(abs_fid));
 861         __storm_memset_dma_mapping(sc, addr, mapping);
 862 }
 863
 864 static void
 865 storm_memset_vf_to_pf(struct bnx2x_softc *sc, uint16_t abs_fid, uint16_t pf_id)
 866 {
 867         REG_WR8(sc, (BAR_XSTRORM_INTMEM + XSTORM_VF_TO_PF_OFFSET(abs_fid)),
 868                 pf_id);
 869         REG_WR8(sc, (BAR_CSTRORM_INTMEM + CSTORM_VF_TO_PF_OFFSET(abs_fid)),
 870                 pf_id);
 871         REG_WR8(sc, (BAR_TSTRORM_INTMEM + TSTORM_VF_TO_PF_OFFSET(abs_fid)),
 872                 pf_id);
 873         REG_WR8(sc, (BAR_USTRORM_INTMEM + USTORM_VF_TO_PF_OFFSET(abs_fid)),
 874                 pf_id);
 875 }
 876
 877 static void
 878 storm_memset_func_en(struct bnx2x_softc *sc, uint16_t abs_fid, uint8_t enable)
 879 {
 880         REG_WR8(sc, (BAR_XSTRORM_INTMEM + XSTORM_FUNC_EN_OFFSET(abs_fid)),
 881                 enable);
 882         REG_WR8(sc, (BAR_CSTRORM_INTMEM + CSTORM_FUNC_EN_OFFSET(abs_fid)),
 883                 enable);
 884         REG_WR8(sc, (BAR_TSTRORM_INTMEM + TSTORM_FUNC_EN_OFFSET(abs_fid)),
 885                 enable);
 886         REG_WR8(sc, (BAR_USTRORM_INTMEM + USTORM_FUNC_EN_OFFSET(abs_fid)),
 887                 enable);
 888 }
 889
 890 static void
 891 storm_memset_eq_data(struct bnx2x_softc *sc, struct event_ring_data *eq_data,
 892                      uint16_t pfid)
 893 {
 894         uint32_t addr;
 895         size_t size;
 896
 897         addr = (BAR_CSTRORM_INTMEM + CSTORM_EVENT_RING_DATA_OFFSET(pfid));
 898         size = sizeof(struct event_ring_data);
 899         ecore_storm_memset_struct(sc, addr, size, (uint32_t *) eq_data);
 900 }
 901
 902 static void
 903 storm_memset_eq_prod(struct bnx2x_softc *sc, uint16_t eq_prod, uint16_t pfid)
 904 {
 905         uint32_t addr = (BAR_CSTRORM_INTMEM +
 906                          CSTORM_EVENT_RING_PROD_OFFSET(pfid));
 907         REG_WR16(sc, addr, eq_prod);
 908 }
 909
 910 /*
 911  * Post a slowpath command.
 912  *
 913  * A slowpath command is used to propagate a configuration change through
 914  * the controller in a controlled manner, allowing each STORM processor and
 915  * other H/W blocks to phase in the change.  The commands sent on the
 916  * slowpath are referred to as ramrods.  Depending on the ramrod used the
 917  * completion of the ramrod will occur in different ways.  Here's a
 918  * breakdown of ramrods and how they complete:
 919  *
 920  * RAMROD_CMD_ID_ETH_PORT_SETUP
 921  *   Used to setup the leading connection on a port.  Completes on the
 922  *   Receive Completion Queue (RCQ) of that port (typically fp[0]).
 923  *
 924  * RAMROD_CMD_ID_ETH_CLIENT_SETUP
 925  *   Used to setup an additional connection on a port.  Completes on the
 926  *   RCQ of the multi-queue/RSS connection being initialized.
 927  *
 928  * RAMROD_CMD_ID_ETH_STAT_QUERY
 929  *   Used to force the storm processors to update the statistics database
 930  *   in host memory.  This ramrod is send on the leading connection CID and
 931  *   completes as an index increment of the CSTORM on the default status
 932  *   block.
 933  *
 934  * RAMROD_CMD_ID_ETH_UPDATE
 935  *   Used to update the state of the leading connection, usually to udpate
 936  *   the RSS indirection table.  Completes on the RCQ of the leading
 937  *   connection. (Not currently used under FreeBSD until OS support becomes
 938  *   available.)
 939  *
 940  * RAMROD_CMD_ID_ETH_HALT
 941  *   Used when tearing down a connection prior to driver unload.  Completes
 942  *   on the RCQ of the multi-queue/RSS connection being torn down.  Don't
 943  *   use this on the leading connection.
 944  *
 945  * RAMROD_CMD_ID_ETH_SET_MAC
 946  *   Sets the Unicast/Broadcast/Multicast used by the port.  Completes on
 947  *   the RCQ of the leading connection.
 948  *
 949  * RAMROD_CMD_ID_ETH_CFC_DEL
 950  *   Used when tearing down a conneciton prior to driver unload.  Completes
 951  *   on the RCQ of the leading connection (since the current connection
 952  *   has been completely removed from controller memory).
 953  *
 954  * RAMROD_CMD_ID_ETH_PORT_DEL
 955  *   Used to tear down the leading connection prior to driver unload,
 956  *   typically fp[0].  Completes as an index increment of the CSTORM on the
 957  *   default status block.
 958  *
 959  * RAMROD_CMD_ID_ETH_FORWARD_SETUP
 960  *   Used for connection offload.  Completes on the RCQ of the multi-queue
 961  *   RSS connection that is being offloaded.  (Not currently used under
 962  *   FreeBSD.)
 963  *
 964  * There can only be one command pending per function.
 965  *
 966  * Returns:
 967  *   0 = Success, !0 = Failure.
 968  */
 969
 970 /* must be called under the spq lock */
 971 static inline struct eth_spe *bnx2x_sp_get_next(struct bnx2x_softc *sc)
 972 {
 973         struct eth_spe *next_spe = sc->spq_prod_bd;
 974
 975         if (sc->spq_prod_bd == sc->spq_last_bd) {
 976                 /* wrap back to the first eth_spq */
 977                 sc->spq_prod_bd = sc->spq;
 978                 sc->spq_prod_idx = 0;
 979         } else {
 980                 sc->spq_prod_bd++;
 981                 sc->spq_prod_idx++;
 982         }
 983
 984         return next_spe;
 985 }
 986
 987 /* must be called under the spq lock */
 988 static void bnx2x_sp_prod_update(struct bnx2x_softc *sc)
 989 {
 990         int func = SC_FUNC(sc);
 991
 992         /*
 993          * Make sure that BD data is updated before writing the producer.
 994          * BD data is written to the memory, the producer is read from the
 995          * memory, thus we need a full memory barrier to ensure the ordering.
 996          */
 997         mb();
 998
 999         REG_WR16(sc, (BAR_XSTRORM_INTMEM + XSTORM_SPQ_PROD_OFFSET(func)),
1000                  sc->spq_prod_idx);
1001
1002         mb();
1003 }
1004
1005 /**
1006  * bnx2x_is_contextless_ramrod - check if the current command ends on EQ
1007  *
1008  * @cmd:      command to check
1009  * @cmd_type: command type
1010  */
1011 static int bnx2x_is_contextless_ramrod(int cmd, int cmd_type)
1012 {
1013         if ((cmd_type == NONE_CONNECTION_TYPE) ||
1014             (cmd == RAMROD_CMD_ID_ETH_FORWARD_SETUP) ||
1015             (cmd == RAMROD_CMD_ID_ETH_CLASSIFICATION_RULES) ||
1016             (cmd == RAMROD_CMD_ID_ETH_FILTER_RULES) ||
1017             (cmd == RAMROD_CMD_ID_ETH_MULTICAST_RULES) ||
1018             (cmd == RAMROD_CMD_ID_ETH_SET_MAC) ||
1019             (cmd == RAMROD_CMD_ID_ETH_RSS_UPDATE)) {
1020                 return TRUE;
1021         } else {
1022                 return FALSE;
1023         }
1024 }
1025
1026 /**
1027  * bnx2x_sp_post - place a single command on an SP ring
1028  *
1029  * @sc:         driver handle
1030  * @command:    command to place (e.g. SETUP, FILTER_RULES, etc.)
1031  * @cid:        SW CID the command is related to
1032  * @data_hi:    command private data address (high 32 bits)
1033  * @data_lo:    command private data address (low 32 bits)
1034  * @cmd_type:   command type (e.g. NONE, ETH)
1035  *
1036  * SP data is handled as if it's always an address pair, thus data fields are
1037  * not swapped to little endian in upper functions. Instead this function swaps
1038  * data as if it's two uint32 fields.
1039  */
1040 int
1041 bnx2x_sp_post(struct bnx2x_softc *sc, int command, int cid, uint32_t data_hi,
1042             uint32_t data_lo, int cmd_type)
1043 {
1044         struct eth_spe *spe;
1045         uint16_t type;
1046         int common;
1047
1048         common = bnx2x_is_contextless_ramrod(command, cmd_type);
1049
1050         if (common) {
1051                 if (!atomic_load_acq_long(&sc->eq_spq_left)) {
1052                         PMD_DRV_LOG(INFO, sc, "EQ ring is full!");
1053                         return -1;
1054                 }
1055         } else {
1056                 if (!atomic_load_acq_long(&sc->cq_spq_left)) {
1057                         PMD_DRV_LOG(INFO, sc, "SPQ ring is full!");
1058                         return -1;
1059                 }
1060         }
1061
1062         spe = bnx2x_sp_get_next(sc);
1063
1064         /* CID needs port number to be encoded int it */
1065         spe->hdr.conn_and_cmd_data =
1066             htole32((command << SPE_HDR_CMD_ID_SHIFT) | HW_CID(sc, cid));
1067
1068         type = (cmd_type << SPE_HDR_CONN_TYPE_SHIFT) & SPE_HDR_CONN_TYPE;
1069
1070         /* TBD: Check if it works for VFs */
1071         type |= ((SC_FUNC(sc) << SPE_HDR_FUNCTION_ID_SHIFT) &
1072                  SPE_HDR_FUNCTION_ID);
1073
1074         spe->hdr.type = htole16(type);
1075
1076         spe->data.update_data_addr.hi = htole32(data_hi);
1077         spe->data.update_data_addr.lo = htole32(data_lo);
1078
1079         /*
1080          * It's ok if the actual decrement is issued towards the memory
1081          * somewhere between the lock and unlock. Thus no more explict
1082          * memory barrier is needed.
1083          */
1084         if (common) {
1085                 atomic_subtract_acq_long(&sc->eq_spq_left, 1);
1086         } else {
1087                 atomic_subtract_acq_long(&sc->cq_spq_left, 1);
1088         }
1089
1090         PMD_DRV_LOG(DEBUG, sc,
1091                     "SPQE[%x] (%x:%x) (cmd, common?) (%d,%d) hw_cid %x"
1092                     "data (%x:%x) type(0x%x) left (CQ, EQ) (%lx,%lx)",
1093                     sc->spq_prod_idx,
1094                     (uint32_t) U64_HI(sc->spq_dma.paddr),
1095                     (uint32_t) (U64_LO(sc->spq_dma.paddr) +
1096                                 (uint8_t *) sc->spq_prod_bd -
1097                                 (uint8_t *) sc->spq), command, common,
1098                     HW_CID(sc, cid), data_hi, data_lo, type,
1099                     atomic_load_acq_long(&sc->cq_spq_left),
1100                     atomic_load_acq_long(&sc->eq_spq_left));
1101
1102         bnx2x_sp_prod_update(sc);
1103
1104         return 0;
1105 }
1106
1107 static void bnx2x_drv_pulse(struct bnx2x_softc *sc)
1108 {
1109         SHMEM_WR(sc, func_mb[SC_FW_MB_IDX(sc)].drv_pulse_mb,
1110                  sc->fw_drv_pulse_wr_seq);
1111 }
1112
1113 static int bnx2x_tx_queue_has_work(const struct bnx2x_fastpath *fp)
1114 {
1115         uint16_t hw_cons;
1116         struct bnx2x_tx_queue *txq = fp->sc->tx_queues[fp->index];
1117
1118         if (unlikely(!txq)) {
1119                 PMD_TX_LOG(ERR, "ERROR: TX queue is NULL");
1120                 return 0;
1121         }
1122
1123         mb();                   /* status block fields can change */
1124         hw_cons = le16toh(*fp->tx_cons_sb);
1125         return hw_cons != txq->tx_pkt_head;
1126 }
1127
1128 static uint8_t bnx2x_has_tx_work(struct bnx2x_fastpath *fp)
1129 {
1130         /* expand this for multi-cos if ever supported */
1131         return bnx2x_tx_queue_has_work(fp);
1132 }
1133
1134 static int bnx2x_has_rx_work(struct bnx2x_fastpath *fp)
1135 {
1136         uint16_t rx_cq_cons_sb;
1137         struct bnx2x_rx_queue *rxq;
1138         rxq = fp->sc->rx_queues[fp->index];
1139         if (unlikely(!rxq)) {
1140                 PMD_RX_LOG(ERR, "ERROR: RX queue is NULL");
1141                 return 0;
1142         }
1143
1144         mb();                   /* status block fields can change */
1145         rx_cq_cons_sb = le16toh(*fp->rx_cq_cons_sb);
1146         if (unlikely((rx_cq_cons_sb & MAX_RCQ_ENTRIES(rxq)) ==
1147                      MAX_RCQ_ENTRIES(rxq)))
1148                 rx_cq_cons_sb++;
1149         return rxq->rx_cq_head != rx_cq_cons_sb;
1150 }
1151
1152 static void
1153 bnx2x_sp_event(struct bnx2x_softc *sc, struct bnx2x_fastpath *fp,
1154              union eth_rx_cqe *rr_cqe)
1155 {
1156         int cid = SW_CID(rr_cqe->ramrod_cqe.conn_and_cmd_data);
1157         int command = CQE_CMD(rr_cqe->ramrod_cqe.conn_and_cmd_data);
1158         enum ecore_queue_cmd drv_cmd = ECORE_Q_CMD_MAX;
1159         struct ecore_queue_sp_obj *q_obj = &BNX2X_SP_OBJ(sc, fp).q_obj;
1160
1161         PMD_DRV_LOG(DEBUG, sc,
1162                     "fp=%d cid=%d got ramrod #%d state is %x type is %d",
1163                     fp->index, cid, command, sc->state,
1164                     rr_cqe->ramrod_cqe.ramrod_type);
1165
1166         switch (command) {
1167         case (RAMROD_CMD_ID_ETH_CLIENT_UPDATE):
1168                 PMD_DRV_LOG(DEBUG, sc, "got UPDATE ramrod. CID %d", cid);
1169                 drv_cmd = ECORE_Q_CMD_UPDATE;
1170                 break;
1171
1172         case (RAMROD_CMD_ID_ETH_CLIENT_SETUP):
1173                 PMD_DRV_LOG(DEBUG, sc, "got MULTI[%d] setup ramrod", cid);
1174                 drv_cmd = ECORE_Q_CMD_SETUP;
1175                 break;
1176
1177         case (RAMROD_CMD_ID_ETH_TX_QUEUE_SETUP):
1178                 PMD_DRV_LOG(DEBUG, sc,
1179                             "got MULTI[%d] tx-only setup ramrod", cid);
1180                 drv_cmd = ECORE_Q_CMD_SETUP_TX_ONLY;
1181                 break;
1182
1183         case (RAMROD_CMD_ID_ETH_HALT):
1184                 PMD_DRV_LOG(DEBUG, sc, "got MULTI[%d] halt ramrod", cid);
1185                 drv_cmd = ECORE_Q_CMD_HALT;
1186                 break;
1187
1188         case (RAMROD_CMD_ID_ETH_TERMINATE):
1189                 PMD_DRV_LOG(DEBUG, sc, "got MULTI[%d] teminate ramrod", cid);
1190                 drv_cmd = ECORE_Q_CMD_TERMINATE;
1191                 break;
1192
1193         case (RAMROD_CMD_ID_ETH_EMPTY):
1194                 PMD_DRV_LOG(DEBUG, sc, "got MULTI[%d] empty ramrod", cid);
1195                 drv_cmd = ECORE_Q_CMD_EMPTY;
1196                 break;
1197
1198         default:
1199                 PMD_DRV_LOG(DEBUG, sc,
1200                             "ERROR: unexpected MC reply (%d)"
1201                             "on fp[%d]", command, fp->index);
1202                 return;
1203         }
1204
1205         if ((drv_cmd != ECORE_Q_CMD_MAX) &&
1206             q_obj->complete_cmd(sc, q_obj, drv_cmd)) {
1207                 /*
1208                  * q_obj->complete_cmd() failure means that this was
1209                  * an unexpected completion.
1210                  *
1211                  * In this case we don't want to increase the sc->spq_left
1212                  * because apparently we haven't sent this command the first
1213                  * place.
1214                  */
1215                 // rte_panic("Unexpected SP completion");
1216                 return;
1217         }
1218
1219         atomic_add_acq_long(&sc->cq_spq_left, 1);
1220
1221         PMD_DRV_LOG(DEBUG, sc, "sc->cq_spq_left 0x%lx",
1222                     atomic_load_acq_long(&sc->cq_spq_left));
1223 }
1224
1225 static uint8_t bnx2x_rxeof(struct bnx2x_softc *sc, struct bnx2x_fastpath *fp)
1226 {
1227         struct bnx2x_rx_queue *rxq;
1228         uint16_t bd_cons, bd_prod, bd_prod_fw, comp_ring_cons;
1229         uint16_t hw_cq_cons, sw_cq_cons, sw_cq_prod;
1230
1231         rxq = sc->rx_queues[fp->index];
1232         if (!rxq) {
1233                 PMD_RX_LOG(ERR, "RX queue %d is NULL", fp->index);
1234                 return 0;
1235         }
1236
1237         /* CQ "next element" is of the size of the regular element */
1238         hw_cq_cons = le16toh(*fp->rx_cq_cons_sb);
1239         if (unlikely((hw_cq_cons & USABLE_RCQ_ENTRIES_PER_PAGE) ==
1240                      USABLE_RCQ_ENTRIES_PER_PAGE)) {
1241                 hw_cq_cons++;
1242         }
1243
1244         bd_cons = rxq->rx_bd_head;
1245         bd_prod = rxq->rx_bd_tail;
1246         bd_prod_fw = bd_prod;
1247         sw_cq_cons = rxq->rx_cq_head;
1248         sw_cq_prod = rxq->rx_cq_tail;
1249
1250         /*
1251          * Memory barrier necessary as speculative reads of the rx
1252          * buffer can be ahead of the index in the status block
1253          */
1254         rmb();
1255
1256         while (sw_cq_cons != hw_cq_cons) {
1257                 union eth_rx_cqe *cqe;
1258                 struct eth_fast_path_rx_cqe *cqe_fp;
1259                 uint8_t cqe_fp_flags;
1260                 enum eth_rx_cqe_type cqe_fp_type;
1261
1262                 comp_ring_cons = RCQ_ENTRY(sw_cq_cons, rxq);
1263                 bd_prod = RX_BD(bd_prod, rxq);
1264                 bd_cons = RX_BD(bd_cons, rxq);
1265
1266                 cqe = &rxq->cq_ring[comp_ring_cons];
1267                 cqe_fp = &cqe->fast_path_cqe;
1268                 cqe_fp_flags = cqe_fp->type_error_flags;
1269                 cqe_fp_type = cqe_fp_flags & ETH_FAST_PATH_RX_CQE_TYPE;
1270
1271                 /* is this a slowpath msg? */
1272                 if (CQE_TYPE_SLOW(cqe_fp_type)) {
1273                         bnx2x_sp_event(sc, fp, cqe);
1274                         goto next_cqe;
1275                 }
1276
1277                 /* is this an error packet? */
1278                 if (unlikely(cqe_fp_flags &
1279                              ETH_FAST_PATH_RX_CQE_PHY_DECODE_ERR_FLG)) {
1280                         PMD_RX_LOG(DEBUG, "flags 0x%x rx packet %u",
1281                                    cqe_fp_flags, sw_cq_cons);
1282                         goto next_rx;
1283                 }
1284
1285                 PMD_RX_LOG(DEBUG, "Dropping fastpath called from attn poller!");
1286
1287 next_rx:
1288                 bd_cons = NEXT_RX_BD(bd_cons);
1289                 bd_prod = NEXT_RX_BD(bd_prod);
1290                 bd_prod_fw = NEXT_RX_BD(bd_prod_fw);
1291
1292 next_cqe:
1293                 sw_cq_prod = NEXT_RCQ_IDX(sw_cq_prod);
1294                 sw_cq_cons = NEXT_RCQ_IDX(sw_cq_cons);
1295
1296         }                       /* while work to do */
1297
1298         rxq->rx_bd_head = bd_cons;
1299         rxq->rx_bd_tail = bd_prod_fw;
1300         rxq->rx_cq_head = sw_cq_cons;
1301         rxq->rx_cq_tail = sw_cq_prod;
1302
1303         /* Update producers */
1304         bnx2x_update_rx_prod(sc, fp, bd_prod_fw, sw_cq_prod);
1305
1306         return sw_cq_cons != hw_cq_cons;
1307 }
1308
1309 static uint16_t
1310 bnx2x_free_tx_pkt(__rte_unused struct bnx2x_fastpath *fp, struct bnx2x_tx_queue *txq,
1311                 uint16_t pkt_idx, uint16_t bd_idx)
1312 {
1313         struct eth_tx_start_bd *tx_start_bd =
1314             &txq->tx_ring[TX_BD(bd_idx, txq)].start_bd;
1315         uint16_t nbd = rte_le_to_cpu_16(tx_start_bd->nbd);
1316         struct rte_mbuf *tx_mbuf = txq->sw_ring[TX_BD(pkt_idx, txq)];
1317
1318         if (likely(tx_mbuf != NULL)) {
1319                 rte_pktmbuf_free_seg(tx_mbuf);
1320         } else {
1321                 PMD_RX_LOG(ERR, "fp[%02d] lost mbuf %lu",
1322                            fp->index, (unsigned long)TX_BD(pkt_idx, txq));
1323         }
1324
1325         txq->sw_ring[TX_BD(pkt_idx, txq)] = NULL;
1326         txq->nb_tx_avail += nbd;
1327
1328         while (nbd--)
1329                 bd_idx = NEXT_TX_BD(bd_idx);
1330
1331         return bd_idx;
1332 }
1333
1334 /* processes transmit completions */
1335 uint8_t bnx2x_txeof(__rte_unused struct bnx2x_softc * sc, struct bnx2x_fastpath * fp)
1336 {
1337         uint16_t bd_cons, hw_cons, sw_cons;
1338         __rte_unused uint16_t tx_bd_avail;
1339
1340         struct bnx2x_tx_queue *txq = fp->sc->tx_queues[fp->index];
1341
1342         if (unlikely(!txq)) {
1343                 PMD_TX_LOG(ERR, "ERROR: TX queue is NULL");
1344                 return 0;
1345         }
1346
1347         bd_cons = txq->tx_bd_head;
1348         hw_cons = rte_le_to_cpu_16(*fp->tx_cons_sb);
1349         sw_cons = txq->tx_pkt_head;
1350
1351         while (sw_cons != hw_cons) {
1352                 bd_cons = bnx2x_free_tx_pkt(fp, txq, sw_cons, bd_cons);
1353                 sw_cons++;
1354         }
1355
1356         txq->tx_pkt_head = sw_cons;
1357         txq->tx_bd_head = bd_cons;
1358
1359         tx_bd_avail = txq->nb_tx_avail;
1360
1361         PMD_TX_LOG(DEBUG, "fp[%02d] avail=%u cons_sb=%u, "
1362                    "pkt_head=%u pkt_tail=%u bd_head=%u bd_tail=%u",
1363                    fp->index, tx_bd_avail, hw_cons,
1364                    txq->tx_pkt_head, txq->tx_pkt_tail,
1365                    txq->tx_bd_head, txq->tx_bd_tail);
1366         return TRUE;
1367 }
1368
1369 static void bnx2x_drain_tx_queues(struct bnx2x_softc *sc)
1370 {
1371         struct bnx2x_fastpath *fp;
1372         int i, count;
1373
1374         /* wait until all TX fastpath tasks have completed */
1375         for (i = 0; i < sc->num_queues; i++) {
1376                 fp = &sc->fp[i];
1377
1378                 count = 1000;
1379
1380                 while (bnx2x_has_tx_work(fp)) {
1381                         bnx2x_txeof(sc, fp);
1382
1383                         if (count == 0) {
1384                                 PMD_TX_LOG(ERR,
1385                                            "Timeout waiting for fp[%d] "
1386                                            "transmits to complete!", i);
1387                                 rte_panic("tx drain failure");
1388                                 return;
1389                         }
1390
1391                         count--;
1392                         DELAY(1000);
1393                         rmb();
1394                 }
1395         }
1396
1397         return;
1398 }
1399
1400 static int
1401 bnx2x_del_all_macs(struct bnx2x_softc *sc, struct ecore_vlan_mac_obj *mac_obj,
1402                  int mac_type, uint8_t wait_for_comp)
1403 {
1404         unsigned long ramrod_flags = 0, vlan_mac_flags = 0;
1405         int rc;
1406
1407         /* wait for completion of requested */
1408         if (wait_for_comp) {
1409                 bnx2x_set_bit(RAMROD_COMP_WAIT, &ramrod_flags);
1410         }
1411
1412         /* Set the mac type of addresses we want to clear */
1413         bnx2x_set_bit(mac_type, &vlan_mac_flags);
1414
1415         rc = mac_obj->delete_all(sc, mac_obj, &vlan_mac_flags, &ramrod_flags);
1416         if (rc < 0)
1417                 PMD_DRV_LOG(ERR, sc, "Failed to delete MACs (%d)", rc);
1418
1419         return rc;
1420 }
1421
1422 static int
1423 bnx2x_fill_accept_flags(struct bnx2x_softc *sc, uint32_t rx_mode,
1424                         unsigned long *rx_accept_flags,
1425                         unsigned long *tx_accept_flags)
1426 {
1427         /* Clear the flags first */
1428         *rx_accept_flags = 0;
1429         *tx_accept_flags = 0;
1430
1431         switch (rx_mode) {
1432         case BNX2X_RX_MODE_NONE:
1433                 /*
1434                  * 'drop all' supersedes any accept flags that may have been
1435                  * passed to the function.
1436                  */
1437                 break;
1438
1439         case BNX2X_RX_MODE_NORMAL:
1440                 bnx2x_set_bit(ECORE_ACCEPT_UNICAST, rx_accept_flags);
1441                 bnx2x_set_bit(ECORE_ACCEPT_MULTICAST, rx_accept_flags);
1442                 bnx2x_set_bit(ECORE_ACCEPT_BROADCAST, rx_accept_flags);
1443
1444                 /* internal switching mode */
1445                 bnx2x_set_bit(ECORE_ACCEPT_UNICAST, tx_accept_flags);
1446                 bnx2x_set_bit(ECORE_ACCEPT_MULTICAST, tx_accept_flags);
1447                 bnx2x_set_bit(ECORE_ACCEPT_BROADCAST, tx_accept_flags);
1448
1449                 break;
1450
1451         case BNX2X_RX_MODE_ALLMULTI:
1452                 bnx2x_set_bit(ECORE_ACCEPT_UNICAST, rx_accept_flags);
1453                 bnx2x_set_bit(ECORE_ACCEPT_ALL_MULTICAST, rx_accept_flags);
1454                 bnx2x_set_bit(ECORE_ACCEPT_BROADCAST, rx_accept_flags);
1455
1456                 /* internal switching mode */
1457                 bnx2x_set_bit(ECORE_ACCEPT_UNICAST, tx_accept_flags);
1458                 bnx2x_set_bit(ECORE_ACCEPT_ALL_MULTICAST, tx_accept_flags);
1459                 bnx2x_set_bit(ECORE_ACCEPT_BROADCAST, tx_accept_flags);
1460
1461                 break;
1462
1463         case BNX2X_RX_MODE_ALLMULTI_PROMISC:
1464         case BNX2X_RX_MODE_PROMISC:
1465                 /*
1466                  * According to deffinition of SI mode, iface in promisc mode
1467                  * should receive matched and unmatched (in resolution of port)
1468                  * unicast packets.
1469                  */
1470                 bnx2x_set_bit(ECORE_ACCEPT_UNMATCHED, rx_accept_flags);
1471                 bnx2x_set_bit(ECORE_ACCEPT_UNICAST, rx_accept_flags);
1472                 bnx2x_set_bit(ECORE_ACCEPT_ALL_MULTICAST, rx_accept_flags);
1473                 bnx2x_set_bit(ECORE_ACCEPT_BROADCAST, rx_accept_flags);
1474
1475                 /* internal switching mode */
1476                 bnx2x_set_bit(ECORE_ACCEPT_ALL_MULTICAST, tx_accept_flags);
1477                 bnx2x_set_bit(ECORE_ACCEPT_BROADCAST, tx_accept_flags);
1478
1479                 if (IS_MF_SI(sc)) {
1480                         bnx2x_set_bit(ECORE_ACCEPT_ALL_UNICAST, tx_accept_flags);
1481                 } else {
1482                         bnx2x_set_bit(ECORE_ACCEPT_UNICAST, tx_accept_flags);
1483                 }
1484
1485                 break;
1486
1487         default:
1488                 PMD_RX_LOG(ERR, "Unknown rx_mode (%d)", rx_mode);
1489                 return -1;
1490         }
1491
1492         /* Set ACCEPT_ANY_VLAN as we do not enable filtering by VLAN */
1493         if (rx_mode != BNX2X_RX_MODE_NONE) {
1494                 bnx2x_set_bit(ECORE_ACCEPT_ANY_VLAN, rx_accept_flags);
1495                 bnx2x_set_bit(ECORE_ACCEPT_ANY_VLAN, tx_accept_flags);
1496         }
1497
1498         return 0;
1499 }
1500
1501 static int
1502 bnx2x_set_q_rx_mode(struct bnx2x_softc *sc, uint8_t cl_id,
1503                   unsigned long rx_mode_flags,
1504                   unsigned long rx_accept_flags,
1505                   unsigned long tx_accept_flags, unsigned long ramrod_flags)
1506 {
1507         struct ecore_rx_mode_ramrod_params ramrod_param;
1508         int rc;
1509
1510         memset(&ramrod_param, 0, sizeof(ramrod_param));
1511
1512         /* Prepare ramrod parameters */
1513         ramrod_param.cid = 0;
1514         ramrod_param.cl_id = cl_id;
1515         ramrod_param.rx_mode_obj = &sc->rx_mode_obj;
1516         ramrod_param.func_id = SC_FUNC(sc);
1517
1518         ramrod_param.pstate = &sc->sp_state;
1519         ramrod_param.state = ECORE_FILTER_RX_MODE_PENDING;
1520
1521         ramrod_param.rdata = BNX2X_SP(sc, rx_mode_rdata);
1522         ramrod_param.rdata_mapping =
1523             (rte_iova_t)BNX2X_SP_MAPPING(sc, rx_mode_rdata),
1524             bnx2x_set_bit(ECORE_FILTER_RX_MODE_PENDING, &sc->sp_state);
1525
1526         ramrod_param.ramrod_flags = ramrod_flags;
1527         ramrod_param.rx_mode_flags = rx_mode_flags;
1528
1529         ramrod_param.rx_accept_flags = rx_accept_flags;
1530         ramrod_param.tx_accept_flags = tx_accept_flags;
1531
1532         rc = ecore_config_rx_mode(sc, &ramrod_param);
1533         if (rc < 0) {
1534                 PMD_RX_LOG(ERR, "Set rx_mode %d failed", sc->rx_mode);
1535                 return rc;
1536         }
1537
1538         return 0;
1539 }
1540
1541 int bnx2x_set_storm_rx_mode(struct bnx2x_softc *sc)
1542 {
1543         unsigned long rx_mode_flags = 0, ramrod_flags = 0;
1544         unsigned long rx_accept_flags = 0, tx_accept_flags = 0;
1545         int rc;
1546
1547         rc = bnx2x_fill_accept_flags(sc, sc->rx_mode, &rx_accept_flags,
1548                                    &tx_accept_flags);
1549         if (rc) {
1550                 return rc;
1551         }
1552
1553         bnx2x_set_bit(RAMROD_RX, &ramrod_flags);
1554         bnx2x_set_bit(RAMROD_TX, &ramrod_flags);
1555         bnx2x_set_bit(RAMROD_COMP_WAIT, &ramrod_flags);
1556
1557         return bnx2x_set_q_rx_mode(sc, sc->fp[0].cl_id, rx_mode_flags,
1558                                  rx_accept_flags, tx_accept_flags,
1559                                  ramrod_flags);
1560 }
1561
1562 /* returns the "mcp load_code" according to global load_count array */
1563 static int bnx2x_nic_load_no_mcp(struct bnx2x_softc *sc)
1564 {
1565         int path = SC_PATH(sc);
1566         int port = SC_PORT(sc);
1567
1568         PMD_DRV_LOG(INFO, sc, "NO MCP - load counts[%d]      %d, %d, %d",
1569                     path, load_count[path][0], load_count[path][1],
1570                     load_count[path][2]);
1571
1572         load_count[path][0]++;
1573         load_count[path][1 + port]++;
1574         PMD_DRV_LOG(INFO, sc, "NO MCP - new load counts[%d]  %d, %d, %d",
1575                     path, load_count[path][0], load_count[path][1],
1576                     load_count[path][2]);
1577         if (load_count[path][0] == 1)
1578                 return FW_MSG_CODE_DRV_LOAD_COMMON;
1579         else if (load_count[path][1 + port] == 1)
1580                 return FW_MSG_CODE_DRV_LOAD_PORT;
1581         else
1582                 return FW_MSG_CODE_DRV_LOAD_FUNCTION;
1583 }
1584
1585 /* returns the "mcp load_code" according to global load_count array */
1586 static int bnx2x_nic_unload_no_mcp(struct bnx2x_softc *sc)
1587 {
1588         int port = SC_PORT(sc);
1589         int path = SC_PATH(sc);
1590
1591         PMD_DRV_LOG(INFO, sc, "NO MCP - load counts[%d]      %d, %d, %d",
1592                     path, load_count[path][0], load_count[path][1],
1593                     load_count[path][2]);
1594         load_count[path][0]--;
1595         load_count[path][1 + port]--;
1596         PMD_DRV_LOG(INFO, sc, "NO MCP - new load counts[%d]  %d, %d, %d",
1597                     path, load_count[path][0], load_count[path][1],
1598                     load_count[path][2]);
1599         if (load_count[path][0] == 0) {
1600                 return FW_MSG_CODE_DRV_UNLOAD_COMMON;
1601         } else if (load_count[path][1 + port] == 0) {
1602                 return FW_MSG_CODE_DRV_UNLOAD_PORT;
1603         } else {
1604                 return FW_MSG_CODE_DRV_UNLOAD_FUNCTION;
1605         }
1606 }
1607
1608 /* request unload mode from the MCP: COMMON, PORT or FUNCTION */
1609 static uint32_t bnx2x_send_unload_req(struct bnx2x_softc *sc, int unload_mode)
1610 {
1611         uint32_t reset_code = 0;
1612
1613         /* Select the UNLOAD request mode */
1614         if (unload_mode == UNLOAD_NORMAL) {
1615                 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS;
1616         } else {
1617                 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS;
1618         }
1619
1620         /* Send the request to the MCP */
1621         if (!BNX2X_NOMCP(sc)) {
1622                 reset_code = bnx2x_fw_command(sc, reset_code, 0);
1623         } else {
1624                 reset_code = bnx2x_nic_unload_no_mcp(sc);
1625         }
1626
1627         return reset_code;
1628 }
1629
1630 /* send UNLOAD_DONE command to the MCP */
1631 static void bnx2x_send_unload_done(struct bnx2x_softc *sc, uint8_t keep_link)
1632 {
1633         uint32_t reset_param =
1634             keep_link ? DRV_MSG_CODE_UNLOAD_SKIP_LINK_RESET : 0;
1635
1636         /* Report UNLOAD_DONE to MCP */
1637         if (!BNX2X_NOMCP(sc)) {
1638                 bnx2x_fw_command(sc, DRV_MSG_CODE_UNLOAD_DONE, reset_param);
1639         }
1640 }
1641
1642 static int bnx2x_func_wait_started(struct bnx2x_softc *sc)
1643 {
1644         int tout = 50;
1645
1646         if (!sc->port.pmf) {
1647                 return 0;
1648         }
1649
1650         /*
1651          * (assumption: No Attention from MCP at this stage)
1652          * PMF probably in the middle of TX disable/enable transaction
1653          * 1. Sync IRS for default SB
1654          * 2. Sync SP queue - this guarantees us that attention handling started
1655          * 3. Wait, that TX disable/enable transaction completes
1656          *
1657          * 1+2 guarantee that if DCBX attention was scheduled it already changed
1658          * pending bit of transaction from STARTED-->TX_STOPPED, if we already
1659          * received completion for the transaction the state is TX_STOPPED.
1660          * State will return to STARTED after completion of TX_STOPPED-->STARTED
1661          * transaction.
1662          */
1663
1664         while (ecore_func_get_state(sc, &sc->func_obj) !=
1665                ECORE_F_STATE_STARTED && tout--) {
1666                 DELAY(20000);
1667         }
1668
1669         if (ecore_func_get_state(sc, &sc->func_obj) != ECORE_F_STATE_STARTED) {
1670                 /*
1671                  * Failed to complete the transaction in a "good way"
1672                  * Force both transactions with CLR bit.
1673                  */
1674                 struct ecore_func_state_params func_params = { NULL };
1675
1676                 PMD_DRV_LOG(NOTICE, sc, "Unexpected function state! "
1677                             "Forcing STARTED-->TX_STOPPED-->STARTED");
1678
1679                 func_params.f_obj = &sc->func_obj;
1680                 bnx2x_set_bit(RAMROD_DRV_CLR_ONLY, &func_params.ramrod_flags);
1681
1682                 /* STARTED-->TX_STOPPED */
1683                 func_params.cmd = ECORE_F_CMD_TX_STOP;
1684                 ecore_func_state_change(sc, &func_params);
1685
1686                 /* TX_STOPPED-->STARTED */
1687                 func_params.cmd = ECORE_F_CMD_TX_START;
1688                 return ecore_func_state_change(sc, &func_params);
1689         }
1690
1691         return 0;
1692 }
1693
1694 static int bnx2x_stop_queue(struct bnx2x_softc *sc, int index)
1695 {
1696         struct bnx2x_fastpath *fp = &sc->fp[index];
1697         struct ecore_queue_state_params q_params = { NULL };
1698         int rc;
1699
1700         PMD_DRV_LOG(DEBUG, sc, "stopping queue %d cid %d", index, fp->index);
1701
1702         q_params.q_obj = &sc->sp_objs[fp->index].q_obj;
1703         /* We want to wait for completion in this context */
1704         bnx2x_set_bit(RAMROD_COMP_WAIT, &q_params.ramrod_flags);
1705
1706         /* Stop the primary connection: */
1707
1708         /* ...halt the connection */
1709         q_params.cmd = ECORE_Q_CMD_HALT;
1710         rc = ecore_queue_state_change(sc, &q_params);
1711         if (rc) {
1712                 return rc;
1713         }
1714
1715         /* ...terminate the connection */
1716         q_params.cmd = ECORE_Q_CMD_TERMINATE;
1717         memset(&q_params.params.terminate, 0,
1718                sizeof(q_params.params.terminate));
1719         q_params.params.terminate.cid_index = FIRST_TX_COS_INDEX;
1720         rc = ecore_queue_state_change(sc, &q_params);
1721         if (rc) {
1722                 return rc;
1723         }
1724
1725         /* ...delete cfc entry */
1726         q_params.cmd = ECORE_Q_CMD_CFC_DEL;
1727         memset(&q_params.params.cfc_del, 0, sizeof(q_params.params.cfc_del));
1728         q_params.params.cfc_del.cid_index = FIRST_TX_COS_INDEX;
1729         return ecore_queue_state_change(sc, &q_params);
1730 }
1731
1732 /* wait for the outstanding SP commands */
1733 static uint8_t bnx2x_wait_sp_comp(struct bnx2x_softc *sc, unsigned long mask)
1734 {
1735         unsigned long tmp;
1736         int tout = 5000;        /* wait for 5 secs tops */
1737
1738         while (tout--) {
1739                 mb();
1740                 if (!(atomic_load_acq_long(&sc->sp_state) & mask)) {
1741                         return TRUE;
1742                 }
1743
1744                 DELAY(1000);
1745         }
1746
1747         mb();
1748
1749         tmp = atomic_load_acq_long(&sc->sp_state);
1750         if (tmp & mask) {
1751                 PMD_DRV_LOG(INFO, sc, "Filtering completion timed out: "
1752                             "sp_state 0x%lx, mask 0x%lx", tmp, mask);
1753                 return FALSE;
1754         }
1755
1756         return FALSE;
1757 }
1758
1759 static int bnx2x_func_stop(struct bnx2x_softc *sc)
1760 {
1761         struct ecore_func_state_params func_params = { NULL };
1762         int rc;
1763
1764         /* prepare parameters for function state transitions */
1765         bnx2x_set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags);
1766         func_params.f_obj = &sc->func_obj;
1767         func_params.cmd = ECORE_F_CMD_STOP;
1768
1769         /*
1770          * Try to stop the function the 'good way'. If it fails (in case
1771          * of a parity error during bnx2x_chip_cleanup()) and we are
1772          * not in a debug mode, perform a state transaction in order to
1773          * enable further HW_RESET transaction.
1774          */
1775         rc = ecore_func_state_change(sc, &func_params);
1776         if (rc) {
1777                 PMD_DRV_LOG(NOTICE, sc, "FUNC_STOP ramrod failed. "
1778                             "Running a dry transaction");
1779                 bnx2x_set_bit(RAMROD_DRV_CLR_ONLY, &func_params.ramrod_flags);
1780                 return ecore_func_state_change(sc, &func_params);
1781         }
1782
1783         return 0;
1784 }
1785
1786 static int bnx2x_reset_hw(struct bnx2x_softc *sc, uint32_t load_code)
1787 {
1788         struct ecore_func_state_params func_params = { NULL };
1789
1790         /* Prepare parameters for function state transitions */
1791         bnx2x_set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags);
1792
1793         func_params.f_obj = &sc->func_obj;
1794         func_params.cmd = ECORE_F_CMD_HW_RESET;
1795
1796         func_params.params.hw_init.load_phase = load_code;
1797
1798         return ecore_func_state_change(sc, &func_params);
1799 }
1800
1801 static void bnx2x_int_disable_sync(struct bnx2x_softc *sc, int disable_hw)
1802 {
1803         if (disable_hw) {
1804                 /* prevent the HW from sending interrupts */
1805                 bnx2x_int_disable(sc);
1806         }
1807 }
1808
1809 static void
1810 bnx2x_chip_cleanup(struct bnx2x_softc *sc, uint32_t unload_mode, uint8_t keep_link)
1811 {
1812         int port = SC_PORT(sc);
1813         struct ecore_mcast_ramrod_params rparam = { NULL };
1814         uint32_t reset_code;
1815         int i, rc = 0;
1816
1817         bnx2x_drain_tx_queues(sc);
1818
1819         /* give HW time to discard old tx messages */
1820         DELAY(1000);
1821
1822         /* Clean all ETH MACs */
1823         rc = bnx2x_del_all_macs(sc, &sc->sp_objs[0].mac_obj, ECORE_ETH_MAC,
1824                               FALSE);
1825         if (rc < 0) {
1826                 PMD_DRV_LOG(NOTICE, sc,
1827                             "Failed to delete all ETH MACs (%d)", rc);
1828         }
1829
1830         /* Clean up UC list  */
1831         rc = bnx2x_del_all_macs(sc, &sc->sp_objs[0].mac_obj, ECORE_UC_LIST_MAC,
1832                               TRUE);
1833         if (rc < 0) {
1834                 PMD_DRV_LOG(NOTICE, sc,
1835                             "Failed to delete UC MACs list (%d)", rc);
1836         }
1837
1838         /* Disable LLH */
1839         REG_WR(sc, NIG_REG_LLH0_FUNC_EN + port * 8, 0);
1840
1841         /* Set "drop all" to stop Rx */
1842
1843         /*
1844          * We need to take the if_maddr_lock() here in order to prevent
1845          * a race between the completion code and this code.
1846          */
1847
1848         if (bnx2x_test_bit(ECORE_FILTER_RX_MODE_PENDING, &sc->sp_state)) {
1849                 bnx2x_set_bit(ECORE_FILTER_RX_MODE_SCHED, &sc->sp_state);
1850         } else {
1851                 bnx2x_set_storm_rx_mode(sc);
1852         }
1853
1854         /* Clean up multicast configuration */
1855         rparam.mcast_obj = &sc->mcast_obj;
1856         rc = ecore_config_mcast(sc, &rparam, ECORE_MCAST_CMD_DEL);
1857         if (rc < 0) {
1858                 PMD_DRV_LOG(NOTICE, sc,
1859                             "Failed to send DEL MCAST command (%d)", rc);
1860         }
1861
1862         /*
1863          * Send the UNLOAD_REQUEST to the MCP. This will return if
1864          * this function should perform FUNCTION, PORT, or COMMON HW
1865          * reset.
1866          */
1867         reset_code = bnx2x_send_unload_req(sc, unload_mode);
1868
1869         /*
1870          * (assumption: No Attention from MCP at this stage)
1871          * PMF probably in the middle of TX disable/enable transaction
1872          */
1873         rc = bnx2x_func_wait_started(sc);
1874         if (rc) {
1875                 PMD_DRV_LOG(NOTICE, sc, "bnx2x_func_wait_started failed");
1876         }
1877
1878         /*
1879          * Close multi and leading connections
1880          * Completions for ramrods are collected in a synchronous way
1881          */
1882         for (i = 0; i < sc->num_queues; i++) {
1883                 if (bnx2x_stop_queue(sc, i)) {
1884                         goto unload_error;
1885                 }
1886         }
1887
1888         /*
1889          * If SP settings didn't get completed so far - something
1890          * very wrong has happen.
1891          */
1892         if (!bnx2x_wait_sp_comp(sc, ~0x0UL)) {
1893                 PMD_DRV_LOG(NOTICE, sc, "Common slow path ramrods got stuck!");
1894         }
1895
1896 unload_error:
1897
1898         rc = bnx2x_func_stop(sc);
1899         if (rc) {
1900                 PMD_DRV_LOG(NOTICE, sc, "Function stop failed!");
1901         }
1902
1903         /* disable HW interrupts */
1904         bnx2x_int_disable_sync(sc, TRUE);
1905
1906         /* Reset the chip */
1907         rc = bnx2x_reset_hw(sc, reset_code);
1908         if (rc) {
1909                 PMD_DRV_LOG(NOTICE, sc, "Hardware reset failed");
1910         }
1911
1912         /* Report UNLOAD_DONE to MCP */
1913         bnx2x_send_unload_done(sc, keep_link);
1914 }
1915
1916 static void bnx2x_disable_close_the_gate(struct bnx2x_softc *sc)
1917 {
1918         uint32_t val;
1919
1920         PMD_DRV_LOG(DEBUG, sc, "Disabling 'close the gates'");
1921
1922         val = REG_RD(sc, MISC_REG_AEU_GENERAL_MASK);
1923         val &= ~(MISC_AEU_GENERAL_MASK_REG_AEU_PXP_CLOSE_MASK |
1924                  MISC_AEU_GENERAL_MASK_REG_AEU_NIG_CLOSE_MASK);
1925         REG_WR(sc, MISC_REG_AEU_GENERAL_MASK, val);
1926 }
1927
1928 /*
1929  * Cleans the object that have internal lists without sending
1930  * ramrods. Should be run when interrutps are disabled.
1931  */
1932 static void bnx2x_squeeze_objects(struct bnx2x_softc *sc)
1933 {
1934         unsigned long ramrod_flags = 0, vlan_mac_flags = 0;
1935         struct ecore_mcast_ramrod_params rparam = { NULL };
1936         struct ecore_vlan_mac_obj *mac_obj = &sc->sp_objs->mac_obj;
1937         int rc;
1938
1939         /* Cleanup MACs' object first... */
1940
1941         /* Wait for completion of requested */
1942         bnx2x_set_bit(RAMROD_COMP_WAIT, &ramrod_flags);
1943         /* Perform a dry cleanup */
1944         bnx2x_set_bit(RAMROD_DRV_CLR_ONLY, &ramrod_flags);
1945
1946         /* Clean ETH primary MAC */
1947         bnx2x_set_bit(ECORE_ETH_MAC, &vlan_mac_flags);
1948         rc = mac_obj->delete_all(sc, &sc->sp_objs->mac_obj, &vlan_mac_flags,
1949                                  &ramrod_flags);
1950         if (rc != 0) {
1951                 PMD_DRV_LOG(NOTICE, sc, "Failed to clean ETH MACs (%d)", rc);
1952         }
1953
1954         /* Cleanup UC list */
1955         vlan_mac_flags = 0;
1956         bnx2x_set_bit(ECORE_UC_LIST_MAC, &vlan_mac_flags);
1957         rc = mac_obj->delete_all(sc, mac_obj, &vlan_mac_flags, &ramrod_flags);
1958         if (rc != 0) {
1959                 PMD_DRV_LOG(NOTICE, sc,
1960                             "Failed to clean UC list MACs (%d)", rc);
1961         }
1962
1963         /* Now clean mcast object... */
1964
1965         rparam.mcast_obj = &sc->mcast_obj;
1966         bnx2x_set_bit(RAMROD_DRV_CLR_ONLY, &rparam.ramrod_flags);
1967
1968         /* Add a DEL command... */
1969         rc = ecore_config_mcast(sc, &rparam, ECORE_MCAST_CMD_DEL);
1970         if (rc < 0) {
1971                 PMD_DRV_LOG(NOTICE, sc,
1972                             "Failed to send DEL MCAST command (%d)", rc);
1973         }
1974
1975         /* now wait until all pending commands are cleared */
1976
1977         rc = ecore_config_mcast(sc, &rparam, ECORE_MCAST_CMD_CONT);
1978         while (rc != 0) {
1979                 if (rc < 0) {
1980                         PMD_DRV_LOG(NOTICE, sc,
1981                                     "Failed to clean MCAST object (%d)", rc);
1982                         return;
1983                 }
1984
1985                 rc = ecore_config_mcast(sc, &rparam, ECORE_MCAST_CMD_CONT);
1986         }
1987 }
1988
1989 /* stop the controller */
1990 __rte_noinline
1991 int
1992 bnx2x_nic_unload(struct bnx2x_softc *sc, uint32_t unload_mode, uint8_t keep_link)
1993 {
1994         uint8_t global = FALSE;
1995         uint32_t val;
1996
1997         PMD_DRV_LOG(DEBUG, sc, "Starting NIC unload...");
1998
1999         /* mark driver as unloaded in shmem2 */
2000         if (IS_PF(sc) && SHMEM2_HAS(sc, drv_capabilities_flag)) {
2001                 val = SHMEM2_RD(sc, drv_capabilities_flag[SC_FW_MB_IDX(sc)]);
2002                 SHMEM2_WR(sc, drv_capabilities_flag[SC_FW_MB_IDX(sc)],
2003                           val & ~DRV_FLAGS_CAPABILITIES_LOADED_L2);
2004         }
2005
2006         if (IS_PF(sc) && sc->recovery_state != BNX2X_RECOVERY_DONE &&
2007             (sc->state == BNX2X_STATE_CLOSED || sc->state == BNX2X_STATE_ERROR)) {
2008                 /*
2009                  * We can get here if the driver has been unloaded
2010                  * during parity error recovery and is either waiting for a
2011                  * leader to complete or for other functions to unload and
2012                  * then ifconfig down has been issued. In this case we want to
2013                  * unload and let other functions to complete a recovery
2014                  * process.
2015                  */
2016                 sc->recovery_state = BNX2X_RECOVERY_DONE;
2017                 sc->is_leader = 0;
2018                 bnx2x_release_leader_lock(sc);
2019                 mb();
2020
2021                 PMD_DRV_LOG(NOTICE, sc, "Can't unload in closed or error state");
2022                 return -1;
2023         }
2024
2025         /*
2026          * Nothing to do during unload if previous bnx2x_nic_load()
2027          * did not completed successfully - all resourses are released.
2028          */
2029         if ((sc->state == BNX2X_STATE_CLOSED) || (sc->state == BNX2X_STATE_ERROR)) {
2030                 return 0;
2031         }
2032
2033         sc->state = BNX2X_STATE_CLOSING_WAITING_HALT;
2034         mb();
2035
2036         sc->rx_mode = BNX2X_RX_MODE_NONE;
2037         bnx2x_set_rx_mode(sc);
2038         mb();
2039
2040         if (IS_PF(sc)) {
2041                 /* set ALWAYS_ALIVE bit in shmem */
2042                 sc->fw_drv_pulse_wr_seq |= DRV_PULSE_ALWAYS_ALIVE;
2043
2044                 bnx2x_drv_pulse(sc);
2045
2046                 bnx2x_stats_handle(sc, STATS_EVENT_STOP);
2047                 bnx2x_save_statistics(sc);
2048         }
2049
2050         /* wait till consumers catch up with producers in all queues */
2051         bnx2x_drain_tx_queues(sc);
2052
2053         /* if VF indicate to PF this function is going down (PF will delete sp
2054          * elements and clear initializations
2055          */
2056         if (IS_VF(sc)) {
2057                 bnx2x_vf_unload(sc);
2058         } else if (unload_mode != UNLOAD_RECOVERY) {
2059                 /* if this is a normal/close unload need to clean up chip */
2060                 bnx2x_chip_cleanup(sc, unload_mode, keep_link);
2061         } else {
2062                 /* Send the UNLOAD_REQUEST to the MCP */
2063                 bnx2x_send_unload_req(sc, unload_mode);
2064
2065                 /*
2066                  * Prevent transactions to host from the functions on the
2067                  * engine that doesn't reset global blocks in case of global
2068                  * attention once gloabl blocks are reset and gates are opened
2069                  * (the engine which leader will perform the recovery
2070                  * last).
2071                  */
2072                 if (!CHIP_IS_E1x(sc)) {
2073                         bnx2x_pf_disable(sc);
2074                 }
2075
2076                 /* disable HW interrupts */
2077                 bnx2x_int_disable_sync(sc, TRUE);
2078
2079                 /* Report UNLOAD_DONE to MCP */
2080                 bnx2x_send_unload_done(sc, FALSE);
2081         }
2082
2083         /*
2084          * At this stage no more interrupts will arrive so we may safely clean
2085          * the queue'able objects here in case they failed to get cleaned so far.
2086          */
2087         if (IS_PF(sc)) {
2088                 bnx2x_squeeze_objects(sc);
2089         }
2090
2091         /* There should be no more pending SP commands at this stage */
2092         sc->sp_state = 0;
2093
2094         sc->port.pmf = 0;
2095
2096         if (IS_PF(sc)) {
2097                 bnx2x_free_mem(sc);
2098         }
2099
2100         bnx2x_free_fw_stats_mem(sc);
2101
2102         sc->state = BNX2X_STATE_CLOSED;
2103
2104         /*
2105          * Check if there are pending parity attentions. If there are - set
2106          * RECOVERY_IN_PROGRESS.
2107          */
2108         if (IS_PF(sc) && bnx2x_chk_parity_attn(sc, &global, FALSE)) {
2109                 bnx2x_set_reset_in_progress(sc);
2110
2111                 /* Set RESET_IS_GLOBAL if needed */
2112                 if (global) {
2113                         bnx2x_set_reset_global(sc);
2114                 }
2115         }
2116
2117         /*
2118          * The last driver must disable a "close the gate" if there is no
2119          * parity attention or "process kill" pending.
2120          */
2121         if (IS_PF(sc) && !bnx2x_clear_pf_load(sc) &&
2122             bnx2x_reset_is_done(sc, SC_PATH(sc))) {
2123                 bnx2x_disable_close_the_gate(sc);
2124         }
2125
2126         PMD_DRV_LOG(DEBUG, sc, "Ended NIC unload");
2127
2128         return 0;
2129 }
2130
2131 /*
2132  * Encapsulte an mbuf cluster into the tx bd chain and makes the memory
2133  * visible to the controller.
2134  *
2135  * If an mbuf is submitted to this routine and cannot be given to the
2136  * controller (e.g. it has too many fragments) then the function may free
2137  * the mbuf and return to the caller.
2138  *
2139  * Returns:
2140  *     int: Number of TX BDs used for the mbuf
2141  *
2142  *   Note the side effect that an mbuf may be freed if it causes a problem.
2143  */
2144 int bnx2x_tx_encap(struct bnx2x_tx_queue *txq, struct rte_mbuf *m0)
2145 {
2146         struct eth_tx_start_bd *tx_start_bd;
2147         uint16_t bd_prod, pkt_prod;
2148         struct bnx2x_softc *sc;
2149         uint32_t nbds = 0;
2150
2151         sc = txq->sc;
2152         bd_prod = txq->tx_bd_tail;
2153         pkt_prod = txq->tx_pkt_tail;
2154
2155         txq->sw_ring[TX_BD(pkt_prod, txq)] = m0;
2156
2157         tx_start_bd = &txq->tx_ring[TX_BD(bd_prod, txq)].start_bd;
2158
2159         tx_start_bd->addr =
2160             rte_cpu_to_le_64(rte_mbuf_data_iova(m0));
2161         tx_start_bd->nbytes = rte_cpu_to_le_16(m0->data_len);
2162         tx_start_bd->bd_flags.as_bitfield = ETH_TX_BD_FLAGS_START_BD;
2163         tx_start_bd->general_data =
2164             (1 << ETH_TX_START_BD_HDR_NBDS_SHIFT);
2165
2166         tx_start_bd->nbd = rte_cpu_to_le_16(2);
2167
2168         if (m0->ol_flags & PKT_TX_VLAN_PKT) {
2169                 tx_start_bd->vlan_or_ethertype =
2170                     rte_cpu_to_le_16(m0->vlan_tci);
2171                 tx_start_bd->bd_flags.as_bitfield |=
2172                     (X_ETH_OUTBAND_VLAN <<
2173                      ETH_TX_BD_FLAGS_VLAN_MODE_SHIFT);
2174         } else {
2175                 if (IS_PF(sc))
2176                         tx_start_bd->vlan_or_ethertype =
2177                             rte_cpu_to_le_16(pkt_prod);
2178                 else {
2179                         struct ether_hdr *eh =
2180                             rte_pktmbuf_mtod(m0, struct ether_hdr *);
2181
2182                         tx_start_bd->vlan_or_ethertype =
2183                             rte_cpu_to_le_16(rte_be_to_cpu_16(eh->ether_type));
2184                 }
2185         }
2186
2187         bd_prod = NEXT_TX_BD(bd_prod);
2188         if (IS_VF(sc)) {
2189                 struct eth_tx_parse_bd_e2 *tx_parse_bd;
2190                 const struct ether_hdr *eh =
2191                     rte_pktmbuf_mtod(m0, struct ether_hdr *);
2192                 uint8_t mac_type = UNICAST_ADDRESS;
2193
2194                 tx_parse_bd =
2195                     &txq->tx_ring[TX_BD(bd_prod, txq)].parse_bd_e2;
2196                 if (is_multicast_ether_addr(&eh->d_addr)) {
2197                         if (is_broadcast_ether_addr(&eh->d_addr))
2198                                 mac_type = BROADCAST_ADDRESS;
2199                         else
2200                                 mac_type = MULTICAST_ADDRESS;
2201                 }
2202                 tx_parse_bd->parsing_data =
2203                     (mac_type << ETH_TX_PARSE_BD_E2_ETH_ADDR_TYPE_SHIFT);
2204
2205                 rte_memcpy(&tx_parse_bd->data.mac_addr.dst_hi,
2206                            &eh->d_addr.addr_bytes[0], 2);
2207                 rte_memcpy(&tx_parse_bd->data.mac_addr.dst_mid,
2208                            &eh->d_addr.addr_bytes[2], 2);
2209                 rte_memcpy(&tx_parse_bd->data.mac_addr.dst_lo,
2210                            &eh->d_addr.addr_bytes[4], 2);
2211                 rte_memcpy(&tx_parse_bd->data.mac_addr.src_hi,
2212                            &eh->s_addr.addr_bytes[0], 2);
2213                 rte_memcpy(&tx_parse_bd->data.mac_addr.src_mid,
2214                            &eh->s_addr.addr_bytes[2], 2);
2215                 rte_memcpy(&tx_parse_bd->data.mac_addr.src_lo,
2216                            &eh->s_addr.addr_bytes[4], 2);
2217
2218                 tx_parse_bd->data.mac_addr.dst_hi =
2219                     rte_cpu_to_be_16(tx_parse_bd->data.mac_addr.dst_hi);
2220                 tx_parse_bd->data.mac_addr.dst_mid =
2221                     rte_cpu_to_be_16(tx_parse_bd->data.
2222                                      mac_addr.dst_mid);
2223                 tx_parse_bd->data.mac_addr.dst_lo =
2224                     rte_cpu_to_be_16(tx_parse_bd->data.mac_addr.dst_lo);
2225                 tx_parse_bd->data.mac_addr.src_hi =
2226                     rte_cpu_to_be_16(tx_parse_bd->data.mac_addr.src_hi);
2227                 tx_parse_bd->data.mac_addr.src_mid =
2228                     rte_cpu_to_be_16(tx_parse_bd->data.
2229                                      mac_addr.src_mid);
2230                 tx_parse_bd->data.mac_addr.src_lo =
2231                     rte_cpu_to_be_16(tx_parse_bd->data.mac_addr.src_lo);
2232
2233                 PMD_TX_LOG(DEBUG,
2234                            "PBD dst %x %x %x src %x %x %x p_data %x",
2235                            tx_parse_bd->data.mac_addr.dst_hi,
2236                            tx_parse_bd->data.mac_addr.dst_mid,
2237                            tx_parse_bd->data.mac_addr.dst_lo,
2238                            tx_parse_bd->data.mac_addr.src_hi,
2239                            tx_parse_bd->data.mac_addr.src_mid,
2240                            tx_parse_bd->data.mac_addr.src_lo,
2241                            tx_parse_bd->parsing_data);
2242         }
2243
2244         PMD_TX_LOG(DEBUG,
2245                    "start bd: nbytes %d flags %x vlan %x",
2246                    tx_start_bd->nbytes,
2247                    tx_start_bd->bd_flags.as_bitfield,
2248                    tx_start_bd->vlan_or_ethertype);
2249
2250         bd_prod = NEXT_TX_BD(bd_prod);
2251         pkt_prod++;
2252
2253         if (TX_IDX(bd_prod) < 2)
2254                 nbds++;
2255
2256         txq->nb_tx_avail -= 2;
2257         txq->tx_bd_tail = bd_prod;
2258         txq->tx_pkt_tail = pkt_prod;
2259
2260         return nbds + 2;
2261 }
2262
2263 static uint16_t bnx2x_cid_ilt_lines(struct bnx2x_softc *sc)
2264 {
2265         return L2_ILT_LINES(sc);
2266 }
2267
2268 static void bnx2x_ilt_set_info(struct bnx2x_softc *sc)
2269 {
2270         struct ilt_client_info *ilt_client;
2271         struct ecore_ilt *ilt = sc->ilt;
2272         uint16_t line = 0;
2273
2274         PMD_INIT_FUNC_TRACE(sc);
2275
2276         ilt->start_line = FUNC_ILT_BASE(SC_FUNC(sc));
2277
2278         /* CDU */
2279         ilt_client = &ilt->clients[ILT_CLIENT_CDU];
2280         ilt_client->client_num = ILT_CLIENT_CDU;
2281         ilt_client->page_size = CDU_ILT_PAGE_SZ;
2282         ilt_client->flags = ILT_CLIENT_SKIP_MEM;
2283         ilt_client->start = line;
2284         line += bnx2x_cid_ilt_lines(sc);
2285
2286         if (CNIC_SUPPORT(sc)) {
2287                 line += CNIC_ILT_LINES;
2288         }
2289
2290         ilt_client->end = (line - 1);
2291
2292         /* QM */
2293         if (QM_INIT(sc->qm_cid_count)) {
2294                 ilt_client = &ilt->clients[ILT_CLIENT_QM];
2295                 ilt_client->client_num = ILT_CLIENT_QM;
2296                 ilt_client->page_size = QM_ILT_PAGE_SZ;
2297                 ilt_client->flags = 0;
2298                 ilt_client->start = line;
2299
2300                 /* 4 bytes for each cid */
2301                 line += DIV_ROUND_UP(sc->qm_cid_count * QM_QUEUES_PER_FUNC * 4,
2302                                      QM_ILT_PAGE_SZ);
2303
2304                 ilt_client->end = (line - 1);
2305         }
2306
2307         if (CNIC_SUPPORT(sc)) {
2308                 /* SRC */
2309                 ilt_client = &ilt->clients[ILT_CLIENT_SRC];
2310                 ilt_client->client_num = ILT_CLIENT_SRC;
2311                 ilt_client->page_size = SRC_ILT_PAGE_SZ;
2312                 ilt_client->flags = 0;
2313                 ilt_client->start = line;
2314                 line += SRC_ILT_LINES;
2315                 ilt_client->end = (line - 1);
2316
2317                 /* TM */
2318                 ilt_client = &ilt->clients[ILT_CLIENT_TM];
2319                 ilt_client->client_num = ILT_CLIENT_TM;
2320                 ilt_client->page_size = TM_ILT_PAGE_SZ;
2321                 ilt_client->flags = 0;
2322                 ilt_client->start = line;
2323                 line += TM_ILT_LINES;
2324                 ilt_client->end = (line - 1);
2325         }
2326
2327         assert((line <= ILT_MAX_LINES));
2328 }
2329
2330 static void bnx2x_set_fp_rx_buf_size(struct bnx2x_softc *sc)
2331 {
2332         int i;
2333
2334         for (i = 0; i < sc->num_queues; i++) {
2335                 /* get the Rx buffer size for RX frames */
2336                 sc->fp[i].rx_buf_size =
2337                     (IP_HEADER_ALIGNMENT_PADDING + ETH_OVERHEAD + sc->mtu);
2338         }
2339 }
2340
2341 int bnx2x_alloc_ilt_mem(struct bnx2x_softc *sc)
2342 {
2343
2344         sc->ilt = rte_malloc("", sizeof(struct ecore_ilt), RTE_CACHE_LINE_SIZE);
2345
2346         return sc->ilt == NULL;
2347 }
2348
2349 static int bnx2x_alloc_ilt_lines_mem(struct bnx2x_softc *sc)
2350 {
2351         sc->ilt->lines = rte_calloc("",
2352                                     sizeof(struct ilt_line), ILT_MAX_LINES,
2353                                     RTE_CACHE_LINE_SIZE);
2354         return sc->ilt->lines == NULL;
2355 }
2356
2357 void bnx2x_free_ilt_mem(struct bnx2x_softc *sc)
2358 {
2359         rte_free(sc->ilt);
2360         sc->ilt = NULL;
2361 }
2362
2363 static void bnx2x_free_ilt_lines_mem(struct bnx2x_softc *sc)
2364 {
2365         if (sc->ilt->lines != NULL) {
2366                 rte_free(sc->ilt->lines);
2367                 sc->ilt->lines = NULL;
2368         }
2369 }
2370
2371 static void bnx2x_free_mem(struct bnx2x_softc *sc)
2372 {
2373         uint32_t i;
2374
2375         for (i = 0; i < L2_ILT_LINES(sc); i++) {
2376                 sc->context[i].vcxt = NULL;
2377                 sc->context[i].size = 0;
2378         }
2379
2380         ecore_ilt_mem_op(sc, ILT_MEMOP_FREE);
2381
2382         bnx2x_free_ilt_lines_mem(sc);
2383 }
2384
2385 static int bnx2x_alloc_mem(struct bnx2x_softc *sc)
2386 {
2387         int context_size;
2388         int allocated;
2389         int i;
2390         char cdu_name[RTE_MEMZONE_NAMESIZE];
2391
2392         /*
2393          * Allocate memory for CDU context:
2394          * This memory is allocated separately and not in the generic ILT
2395          * functions because CDU differs in few aspects:
2396          * 1. There can be multiple entities allocating memory for context -
2397          * regular L2, CNIC, and SRIOV drivers. Each separately controls
2398          * its own ILT lines.
2399          * 2. Since CDU page-size is not a single 4KB page (which is the case
2400          * for the other ILT clients), to be efficient we want to support
2401          * allocation of sub-page-size in the last entry.
2402          * 3. Context pointers are used by the driver to pass to FW / update
2403          * the context (for the other ILT clients the pointers are used just to
2404          * free the memory during unload).
2405          */
2406         context_size = (sizeof(union cdu_context) * BNX2X_L2_CID_COUNT(sc));
2407         for (i = 0, allocated = 0; allocated < context_size; i++) {
2408                 sc->context[i].size = min(CDU_ILT_PAGE_SZ,
2409                                           (context_size - allocated));
2410
2411                 snprintf(cdu_name, sizeof(cdu_name), "cdu_%d", i);
2412                 if (bnx2x_dma_alloc(sc, sc->context[i].size,
2413                                   &sc->context[i].vcxt_dma,
2414                                   cdu_name, BNX2X_PAGE_SIZE) != 0) {
2415                         bnx2x_free_mem(sc);
2416                         return -1;
2417                 }
2418
2419                 sc->context[i].vcxt =
2420                     (union cdu_context *)sc->context[i].vcxt_dma.vaddr;
2421
2422                 allocated += sc->context[i].size;
2423         }
2424
2425         bnx2x_alloc_ilt_lines_mem(sc);
2426
2427         if (ecore_ilt_mem_op(sc, ILT_MEMOP_ALLOC)) {
2428                 PMD_DRV_LOG(NOTICE, sc, "ecore_ilt_mem_op ILT_MEMOP_ALLOC failed");
2429                 bnx2x_free_mem(sc);
2430                 return -1;
2431         }
2432
2433         return 0;
2434 }
2435
2436 static void bnx2x_free_fw_stats_mem(struct bnx2x_softc *sc)
2437 {
2438         sc->fw_stats_num = 0;
2439
2440         sc->fw_stats_req_size = 0;
2441         sc->fw_stats_req = NULL;
2442         sc->fw_stats_req_mapping = 0;
2443
2444         sc->fw_stats_data_size = 0;
2445         sc->fw_stats_data = NULL;
2446         sc->fw_stats_data_mapping = 0;
2447 }
2448
2449 static int bnx2x_alloc_fw_stats_mem(struct bnx2x_softc *sc)
2450 {
2451         uint8_t num_queue_stats;
2452         int num_groups, vf_headroom = 0;
2453
2454         /* number of queues for statistics is number of eth queues */
2455         num_queue_stats = BNX2X_NUM_ETH_QUEUES(sc);
2456
2457         /*
2458          * Total number of FW statistics requests =
2459          *   1 for port stats + 1 for PF stats + num of queues
2460          */
2461         sc->fw_stats_num = (2 + num_queue_stats);
2462
2463         /*
2464          * Request is built from stats_query_header and an array of
2465          * stats_query_cmd_group each of which contains STATS_QUERY_CMD_COUNT
2466          * rules. The real number or requests is configured in the
2467          * stats_query_header.
2468          */
2469         num_groups = (sc->fw_stats_num + vf_headroom) / STATS_QUERY_CMD_COUNT;
2470         if ((sc->fw_stats_num + vf_headroom) % STATS_QUERY_CMD_COUNT)
2471                 num_groups++;
2472
2473         sc->fw_stats_req_size =
2474             (sizeof(struct stats_query_header) +
2475              (num_groups * sizeof(struct stats_query_cmd_group)));
2476
2477         /*
2478          * Data for statistics requests + stats_counter.
2479          * stats_counter holds per-STORM counters that are incremented when
2480          * STORM has finished with the current request. Memory for FCoE
2481          * offloaded statistics are counted anyway, even if they will not be sent.
2482          * VF stats are not accounted for here as the data of VF stats is stored
2483          * in memory allocated by the VF, not here.
2484          */
2485         sc->fw_stats_data_size =
2486             (sizeof(struct stats_counter) +
2487              sizeof(struct per_port_stats) + sizeof(struct per_pf_stats) +
2488              /* sizeof(struct fcoe_statistics_params) + */
2489              (sizeof(struct per_queue_stats) * num_queue_stats));
2490
2491         if (bnx2x_dma_alloc(sc, (sc->fw_stats_req_size + sc->fw_stats_data_size),
2492                           &sc->fw_stats_dma, "fw_stats",
2493                           RTE_CACHE_LINE_SIZE) != 0) {
2494                 bnx2x_free_fw_stats_mem(sc);
2495                 return -1;
2496         }
2497
2498         /* set up the shortcuts */
2499
2500         sc->fw_stats_req = (struct bnx2x_fw_stats_req *)sc->fw_stats_dma.vaddr;
2501         sc->fw_stats_req_mapping = sc->fw_stats_dma.paddr;
2502
2503         sc->fw_stats_data =
2504             (struct bnx2x_fw_stats_data *)((uint8_t *) sc->fw_stats_dma.vaddr +
2505                                          sc->fw_stats_req_size);
2506         sc->fw_stats_data_mapping = (sc->fw_stats_dma.paddr +
2507                                      sc->fw_stats_req_size);
2508
2509         return 0;
2510 }
2511
2512 /*
2513  * Bits map:
2514  * 0-7  - Engine0 load counter.
2515  * 8-15 - Engine1 load counter.
2516  * 16   - Engine0 RESET_IN_PROGRESS bit.
2517  * 17   - Engine1 RESET_IN_PROGRESS bit.
2518  * 18   - Engine0 ONE_IS_LOADED. Set when there is at least one active
2519  *        function on the engine
2520  * 19   - Engine1 ONE_IS_LOADED.
2521  * 20   - Chip reset flow bit. When set none-leader must wait for both engines
2522  *        leader to complete (check for both RESET_IN_PROGRESS bits and not
2523  *        for just the one belonging to its engine).
2524  */
2525 #define BNX2X_RECOVERY_GLOB_REG     MISC_REG_GENERIC_POR_1
2526 #define BNX2X_PATH0_LOAD_CNT_MASK   0x000000ff
2527 #define BNX2X_PATH0_LOAD_CNT_SHIFT  0
2528 #define BNX2X_PATH1_LOAD_CNT_MASK   0x0000ff00
2529 #define BNX2X_PATH1_LOAD_CNT_SHIFT  8
2530 #define BNX2X_PATH0_RST_IN_PROG_BIT 0x00010000
2531 #define BNX2X_PATH1_RST_IN_PROG_BIT 0x00020000
2532 #define BNX2X_GLOBAL_RESET_BIT      0x00040000
2533
2534 /* set the GLOBAL_RESET bit, should be run under rtnl lock */
2535 static void bnx2x_set_reset_global(struct bnx2x_softc *sc)
2536 {
2537         uint32_t val;
2538         bnx2x_acquire_hw_lock(sc, HW_LOCK_RESOURCE_RECOVERY_REG);
2539         val = REG_RD(sc, BNX2X_RECOVERY_GLOB_REG);
2540         REG_WR(sc, BNX2X_RECOVERY_GLOB_REG, val | BNX2X_GLOBAL_RESET_BIT);
2541         bnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_RECOVERY_REG);
2542 }
2543
2544 /* clear the GLOBAL_RESET bit, should be run under rtnl lock */
2545 static void bnx2x_clear_reset_global(struct bnx2x_softc *sc)
2546 {
2547         uint32_t val;
2548         bnx2x_acquire_hw_lock(sc, HW_LOCK_RESOURCE_RECOVERY_REG);
2549         val = REG_RD(sc, BNX2X_RECOVERY_GLOB_REG);
2550         REG_WR(sc, BNX2X_RECOVERY_GLOB_REG, val & (~BNX2X_GLOBAL_RESET_BIT));
2551         bnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_RECOVERY_REG);
2552 }
2553
2554 /* checks the GLOBAL_RESET bit, should be run under rtnl lock */
2555 static uint8_t bnx2x_reset_is_global(struct bnx2x_softc *sc)
2556 {
2557         return REG_RD(sc, BNX2X_RECOVERY_GLOB_REG) & BNX2X_GLOBAL_RESET_BIT;
2558 }
2559
2560 /* clear RESET_IN_PROGRESS bit for the engine, should be run under rtnl lock */
2561 static void bnx2x_set_reset_done(struct bnx2x_softc *sc)
2562 {
2563         uint32_t val;
2564         uint32_t bit = SC_PATH(sc) ? BNX2X_PATH1_RST_IN_PROG_BIT :
2565             BNX2X_PATH0_RST_IN_PROG_BIT;
2566
2567         bnx2x_acquire_hw_lock(sc, HW_LOCK_RESOURCE_RECOVERY_REG);
2568
2569         val = REG_RD(sc, BNX2X_RECOVERY_GLOB_REG);
2570         /* Clear the bit */
2571         val &= ~bit;
2572         REG_WR(sc, BNX2X_RECOVERY_GLOB_REG, val);
2573
2574         bnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_RECOVERY_REG);
2575 }
2576
2577 /* set RESET_IN_PROGRESS for the engine, should be run under rtnl lock */
2578 static void bnx2x_set_reset_in_progress(struct bnx2x_softc *sc)
2579 {
2580         uint32_t val;
2581         uint32_t bit = SC_PATH(sc) ? BNX2X_PATH1_RST_IN_PROG_BIT :
2582             BNX2X_PATH0_RST_IN_PROG_BIT;
2583
2584         bnx2x_acquire_hw_lock(sc, HW_LOCK_RESOURCE_RECOVERY_REG);
2585
2586         val = REG_RD(sc, BNX2X_RECOVERY_GLOB_REG);
2587         /* Set the bit */
2588         val |= bit;
2589         REG_WR(sc, BNX2X_RECOVERY_GLOB_REG, val);
2590
2591         bnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_RECOVERY_REG);
2592 }
2593
2594 /* check RESET_IN_PROGRESS bit for an engine, should be run under rtnl lock */
2595 static uint8_t bnx2x_reset_is_done(struct bnx2x_softc *sc, int engine)
2596 {
2597         uint32_t val = REG_RD(sc, BNX2X_RECOVERY_GLOB_REG);
2598         uint32_t bit = engine ? BNX2X_PATH1_RST_IN_PROG_BIT :
2599             BNX2X_PATH0_RST_IN_PROG_BIT;
2600
2601         /* return false if bit is set */
2602         return (val & bit) ? FALSE : TRUE;
2603 }
2604
2605 /* get the load status for an engine, should be run under rtnl lock */
2606 static uint8_t bnx2x_get_load_status(struct bnx2x_softc *sc, int engine)
2607 {
2608         uint32_t mask = engine ? BNX2X_PATH1_LOAD_CNT_MASK :
2609             BNX2X_PATH0_LOAD_CNT_MASK;
2610         uint32_t shift = engine ? BNX2X_PATH1_LOAD_CNT_SHIFT :
2611             BNX2X_PATH0_LOAD_CNT_SHIFT;
2612         uint32_t val = REG_RD(sc, BNX2X_RECOVERY_GLOB_REG);
2613
2614         val = ((val & mask) >> shift);
2615
2616         return val != 0;
2617 }
2618
2619 /* set pf load mark */
2620 static void bnx2x_set_pf_load(struct bnx2x_softc *sc)
2621 {
2622         uint32_t val;
2623         uint32_t val1;
2624         uint32_t mask = SC_PATH(sc) ? BNX2X_PATH1_LOAD_CNT_MASK :
2625             BNX2X_PATH0_LOAD_CNT_MASK;
2626         uint32_t shift = SC_PATH(sc) ? BNX2X_PATH1_LOAD_CNT_SHIFT :
2627             BNX2X_PATH0_LOAD_CNT_SHIFT;
2628
2629         bnx2x_acquire_hw_lock(sc, HW_LOCK_RESOURCE_RECOVERY_REG);
2630
2631         PMD_INIT_FUNC_TRACE(sc);
2632
2633         val = REG_RD(sc, BNX2X_RECOVERY_GLOB_REG);
2634
2635         /* get the current counter value */
2636         val1 = ((val & mask) >> shift);
2637
2638         /* set bit of this PF */
2639         val1 |= (1 << SC_ABS_FUNC(sc));
2640
2641         /* clear the old value */
2642         val &= ~mask;
2643
2644         /* set the new one */
2645         val |= ((val1 << shift) & mask);
2646
2647         REG_WR(sc, BNX2X_RECOVERY_GLOB_REG, val);
2648
2649         bnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_RECOVERY_REG);
2650 }
2651
2652 /* clear pf load mark */
2653 static uint8_t bnx2x_clear_pf_load(struct bnx2x_softc *sc)
2654 {
2655         uint32_t val1, val;
2656         uint32_t mask = SC_PATH(sc) ? BNX2X_PATH1_LOAD_CNT_MASK :
2657             BNX2X_PATH0_LOAD_CNT_MASK;
2658         uint32_t shift = SC_PATH(sc) ? BNX2X_PATH1_LOAD_CNT_SHIFT :
2659             BNX2X_PATH0_LOAD_CNT_SHIFT;
2660
2661         bnx2x_acquire_hw_lock(sc, HW_LOCK_RESOURCE_RECOVERY_REG);
2662         val = REG_RD(sc, BNX2X_RECOVERY_GLOB_REG);
2663
2664         /* get the current counter value */
2665         val1 = (val & mask) >> shift;
2666
2667         /* clear bit of that PF */
2668         val1 &= ~(1 << SC_ABS_FUNC(sc));
2669
2670         /* clear the old value */
2671         val &= ~mask;
2672
2673         /* set the new one */
2674         val |= ((val1 << shift) & mask);
2675
2676         REG_WR(sc, BNX2X_RECOVERY_GLOB_REG, val);
2677         bnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_RECOVERY_REG);
2678         return val1 != 0;
2679 }
2680
2681 /* send load requrest to mcp and analyze response */
2682 static int bnx2x_nic_load_request(struct bnx2x_softc *sc, uint32_t * load_code)
2683 {
2684         PMD_INIT_FUNC_TRACE(sc);
2685
2686         /* init fw_seq */
2687         sc->fw_seq =
2688             (SHMEM_RD(sc, func_mb[SC_FW_MB_IDX(sc)].drv_mb_header) &
2689              DRV_MSG_SEQ_NUMBER_MASK);
2690
2691         PMD_DRV_LOG(DEBUG, sc, "initial fw_seq 0x%04x", sc->fw_seq);
2692
2693 #ifdef BNX2X_PULSE
2694         /* get the current FW pulse sequence */
2695         sc->fw_drv_pulse_wr_seq =
2696             (SHMEM_RD(sc, func_mb[SC_FW_MB_IDX(sc)].drv_pulse_mb) &
2697              DRV_PULSE_SEQ_MASK);
2698 #else
2699         /* set ALWAYS_ALIVE bit in shmem */
2700         sc->fw_drv_pulse_wr_seq |= DRV_PULSE_ALWAYS_ALIVE;
2701         bnx2x_drv_pulse(sc);
2702 #endif
2703
2704         /* load request */
2705         (*load_code) = bnx2x_fw_command(sc, DRV_MSG_CODE_LOAD_REQ,
2706                                       DRV_MSG_CODE_LOAD_REQ_WITH_LFA);
2707
2708         /* if the MCP fails to respond we must abort */
2709         if (!(*load_code)) {
2710                 PMD_DRV_LOG(NOTICE, sc, "MCP response failure!");
2711                 return -1;
2712         }
2713
2714         /* if MCP refused then must abort */
2715         if ((*load_code) == FW_MSG_CODE_DRV_LOAD_REFUSED) {
2716                 PMD_DRV_LOG(NOTICE, sc, "MCP refused load request");
2717                 return -1;
2718         }
2719
2720         return 0;
2721 }
2722
2723 /*
2724  * Check whether another PF has already loaded FW to chip. In virtualized
2725  * environments a pf from anoth VM may have already initialized the device
2726  * including loading FW.
2727  */
2728 static int bnx2x_nic_load_analyze_req(struct bnx2x_softc *sc, uint32_t load_code)
2729 {
2730         uint32_t my_fw, loaded_fw;
2731
2732         /* is another pf loaded on this engine? */
2733         if ((load_code != FW_MSG_CODE_DRV_LOAD_COMMON_CHIP) &&
2734             (load_code != FW_MSG_CODE_DRV_LOAD_COMMON)) {
2735                 /* build my FW version dword */
2736                 my_fw = (BNX2X_5710_FW_MAJOR_VERSION +
2737                          (BNX2X_5710_FW_MINOR_VERSION << 8) +
2738                          (BNX2X_5710_FW_REVISION_VERSION << 16) +
2739                          (BNX2X_5710_FW_ENGINEERING_VERSION << 24));
2740
2741                 /* read loaded FW from chip */
2742                 loaded_fw = REG_RD(sc, XSEM_REG_PRAM);
2743                 PMD_DRV_LOG(DEBUG, sc, "loaded FW 0x%08x / my FW 0x%08x",
2744                             loaded_fw, my_fw);
2745
2746                 /* abort nic load if version mismatch */
2747                 if (my_fw != loaded_fw) {
2748                         PMD_DRV_LOG(NOTICE, sc,
2749                                     "FW 0x%08x already loaded (mine is 0x%08x)",
2750                                     loaded_fw, my_fw);
2751                         return -1;
2752                 }
2753         }
2754
2755         return 0;
2756 }
2757
2758 /* mark PMF if applicable */
2759 static void bnx2x_nic_load_pmf(struct bnx2x_softc *sc, uint32_t load_code)
2760 {
2761         uint32_t ncsi_oem_data_addr;
2762
2763         PMD_INIT_FUNC_TRACE(sc);
2764
2765         if ((load_code == FW_MSG_CODE_DRV_LOAD_COMMON) ||
2766             (load_code == FW_MSG_CODE_DRV_LOAD_COMMON_CHIP) ||
2767             (load_code == FW_MSG_CODE_DRV_LOAD_PORT)) {
2768                 /*
2769                  * Barrier here for ordering between the writing to sc->port.pmf here
2770                  * and reading it from the periodic task.
2771                  */
2772                 sc->port.pmf = 1;
2773                 mb();
2774         } else {
2775                 sc->port.pmf = 0;
2776         }
2777
2778         PMD_DRV_LOG(DEBUG, sc, "pmf %d", sc->port.pmf);
2779
2780         if (load_code == FW_MSG_CODE_DRV_LOAD_COMMON_CHIP) {
2781                 if (SHMEM2_HAS(sc, ncsi_oem_data_addr)) {
2782                         ncsi_oem_data_addr = SHMEM2_RD(sc, ncsi_oem_data_addr);
2783                         if (ncsi_oem_data_addr) {
2784                                 REG_WR(sc,
2785                                        (ncsi_oem_data_addr +
2786                                         offsetof(struct glob_ncsi_oem_data,
2787                                                  driver_version)), 0);
2788                         }
2789                 }
2790         }
2791 }
2792
2793 static void bnx2x_read_mf_cfg(struct bnx2x_softc *sc)
2794 {
2795         int n = (CHIP_IS_MODE_4_PORT(sc) ? 2 : 1);
2796         int abs_func;
2797         int vn;
2798
2799         if (BNX2X_NOMCP(sc)) {
2800                 return;         /* what should be the default bvalue in this case */
2801         }
2802
2803         /*
2804          * The formula for computing the absolute function number is...
2805          * For 2 port configuration (4 functions per port):
2806          *   abs_func = 2 * vn + SC_PORT + SC_PATH
2807          * For 4 port configuration (2 functions per port):
2808          *   abs_func = 4 * vn + 2 * SC_PORT + SC_PATH
2809          */
2810         for (vn = VN_0; vn < SC_MAX_VN_NUM(sc); vn++) {
2811                 abs_func = (n * (2 * vn + SC_PORT(sc)) + SC_PATH(sc));
2812                 if (abs_func >= E1H_FUNC_MAX) {
2813                         break;
2814                 }
2815                 sc->devinfo.mf_info.mf_config[vn] =
2816                     MFCFG_RD(sc, func_mf_config[abs_func].config);
2817         }
2818
2819         if (sc->devinfo.mf_info.mf_config[SC_VN(sc)] &
2820             FUNC_MF_CFG_FUNC_DISABLED) {
2821                 PMD_DRV_LOG(DEBUG, sc, "mf_cfg function disabled");
2822                 sc->flags |= BNX2X_MF_FUNC_DIS;
2823         } else {
2824                 PMD_DRV_LOG(DEBUG, sc, "mf_cfg function enabled");
2825                 sc->flags &= ~BNX2X_MF_FUNC_DIS;
2826         }
2827 }
2828
2829 /* acquire split MCP access lock register */
2830 static int bnx2x_acquire_alr(struct bnx2x_softc *sc)
2831 {
2832         uint32_t j, val;
2833
2834         for (j = 0; j < 1000; j++) {
2835                 val = (1UL << 31);
2836                 REG_WR(sc, GRCBASE_MCP + 0x9c, val);
2837                 val = REG_RD(sc, GRCBASE_MCP + 0x9c);
2838                 if (val & (1L << 31))
2839                         break;
2840
2841                 DELAY(5000);
2842         }
2843
2844         if (!(val & (1L << 31))) {
2845                 PMD_DRV_LOG(NOTICE, sc, "Cannot acquire MCP access lock register");
2846                 return -1;
2847         }
2848
2849         return 0;
2850 }
2851
2852 /* release split MCP access lock register */
2853 static void bnx2x_release_alr(struct bnx2x_softc *sc)
2854 {
2855         REG_WR(sc, GRCBASE_MCP + 0x9c, 0);
2856 }
2857
2858 static void bnx2x_fan_failure(struct bnx2x_softc *sc)
2859 {
2860         int port = SC_PORT(sc);
2861         uint32_t ext_phy_config;
2862
2863         /* mark the failure */
2864         ext_phy_config =
2865             SHMEM_RD(sc, dev_info.port_hw_config[port].external_phy_config);
2866
2867         ext_phy_config &= ~PORT_HW_CFG_XGXS_EXT_PHY_TYPE_MASK;
2868         ext_phy_config |= PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE;
2869         SHMEM_WR(sc, dev_info.port_hw_config[port].external_phy_config,
2870                  ext_phy_config);
2871
2872         /* log the failure */
2873         PMD_DRV_LOG(INFO, sc,
2874                     "Fan Failure has caused the driver to shutdown "
2875                     "the card to prevent permanent damage. "
2876                     "Please contact OEM Support for assistance");
2877
2878         rte_panic("Schedule task to handle fan failure");
2879 }
2880
2881 /* this function is called upon a link interrupt */
2882 static void bnx2x_link_attn(struct bnx2x_softc *sc)
2883 {
2884         uint32_t pause_enabled = 0;
2885         struct host_port_stats *pstats;
2886         int cmng_fns;
2887
2888         /* Make sure that we are synced with the current statistics */
2889         bnx2x_stats_handle(sc, STATS_EVENT_STOP);
2890
2891         elink_link_update(&sc->link_params, &sc->link_vars);
2892
2893         if (sc->link_vars.link_up) {
2894
2895                 /* dropless flow control */
2896                 if (sc->dropless_fc) {
2897                         pause_enabled = 0;
2898
2899                         if (sc->link_vars.flow_ctrl & ELINK_FLOW_CTRL_TX) {
2900                                 pause_enabled = 1;
2901                         }
2902
2903                         REG_WR(sc,
2904                                (BAR_USTRORM_INTMEM +
2905                                 USTORM_ETH_PAUSE_ENABLED_OFFSET(SC_PORT(sc))),
2906                                pause_enabled);
2907                 }
2908
2909                 if (sc->link_vars.mac_type != ELINK_MAC_TYPE_EMAC) {
2910                         pstats = BNX2X_SP(sc, port_stats);
2911                         /* reset old mac stats */
2912                         memset(&(pstats->mac_stx[0]), 0,
2913                                sizeof(struct mac_stx));
2914                 }
2915
2916                 if (sc->state == BNX2X_STATE_OPEN) {
2917                         bnx2x_stats_handle(sc, STATS_EVENT_LINK_UP);
2918                 }
2919         }
2920
2921         if (sc->link_vars.link_up && sc->link_vars.line_speed) {
2922                 cmng_fns = bnx2x_get_cmng_fns_mode(sc);
2923
2924                 if (cmng_fns != CMNG_FNS_NONE) {
2925                         bnx2x_cmng_fns_init(sc, FALSE, cmng_fns);
2926                         storm_memset_cmng(sc, &sc->cmng, SC_PORT(sc));
2927                 }
2928         }
2929
2930         bnx2x_link_report_locked(sc);
2931
2932         if (IS_MF(sc)) {
2933                 bnx2x_link_sync_notify(sc);
2934         }
2935 }
2936
2937 static void bnx2x_attn_int_asserted(struct bnx2x_softc *sc, uint32_t asserted)
2938 {
2939         int port = SC_PORT(sc);
2940         uint32_t aeu_addr = port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 :
2941             MISC_REG_AEU_MASK_ATTN_FUNC_0;
2942         uint32_t nig_int_mask_addr = port ? NIG_REG_MASK_INTERRUPT_PORT1 :
2943             NIG_REG_MASK_INTERRUPT_PORT0;
2944         uint32_t aeu_mask;
2945         uint32_t nig_mask = 0;
2946         uint32_t reg_addr;
2947         uint32_t igu_acked;
2948         uint32_t cnt;
2949
2950         if (sc->attn_state & asserted) {
2951                 PMD_DRV_LOG(ERR, sc, "IGU ERROR attn=0x%08x", asserted);
2952         }
2953
2954         bnx2x_acquire_hw_lock(sc, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
2955
2956         aeu_mask = REG_RD(sc, aeu_addr);
2957
2958         aeu_mask &= ~(asserted & 0x3ff);
2959
2960         REG_WR(sc, aeu_addr, aeu_mask);
2961
2962         bnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
2963
2964         sc->attn_state |= asserted;
2965
2966         if (asserted & ATTN_HARD_WIRED_MASK) {
2967                 if (asserted & ATTN_NIG_FOR_FUNC) {
2968
2969                         bnx2x_acquire_phy_lock(sc);
2970                         /* save nig interrupt mask */
2971                         nig_mask = REG_RD(sc, nig_int_mask_addr);
2972
2973                         /* If nig_mask is not set, no need to call the update function */
2974                         if (nig_mask) {
2975                                 REG_WR(sc, nig_int_mask_addr, 0);
2976
2977                                 bnx2x_link_attn(sc);
2978                         }
2979
2980                         /* handle unicore attn? */
2981                 }
2982
2983                 if (asserted & ATTN_SW_TIMER_4_FUNC) {
2984                         PMD_DRV_LOG(DEBUG, sc, "ATTN_SW_TIMER_4_FUNC!");
2985                 }
2986
2987                 if (asserted & GPIO_2_FUNC) {
2988                         PMD_DRV_LOG(DEBUG, sc, "GPIO_2_FUNC!");
2989                 }
2990
2991                 if (asserted & GPIO_3_FUNC) {
2992                         PMD_DRV_LOG(DEBUG, sc, "GPIO_3_FUNC!");
2993                 }
2994
2995                 if (asserted & GPIO_4_FUNC) {
2996                         PMD_DRV_LOG(DEBUG, sc, "GPIO_4_FUNC!");
2997                 }
2998
2999                 if (port == 0) {
3000                         if (asserted & ATTN_GENERAL_ATTN_1) {
3001                                 PMD_DRV_LOG(DEBUG, sc, "ATTN_GENERAL_ATTN_1!");
3002                                 REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_1, 0x0);
3003                         }
3004                         if (asserted & ATTN_GENERAL_ATTN_2) {
3005                                 PMD_DRV_LOG(DEBUG, sc, "ATTN_GENERAL_ATTN_2!");
3006                                 REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_2, 0x0);
3007                         }
3008                         if (asserted & ATTN_GENERAL_ATTN_3) {
3009                                 PMD_DRV_LOG(DEBUG, sc, "ATTN_GENERAL_ATTN_3!");
3010                                 REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_3, 0x0);
3011                         }
3012                 } else {
3013                         if (asserted & ATTN_GENERAL_ATTN_4) {
3014                                 PMD_DRV_LOG(DEBUG, sc, "ATTN_GENERAL_ATTN_4!");
3015                                 REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_4, 0x0);
3016                         }
3017                         if (asserted & ATTN_GENERAL_ATTN_5) {
3018                                 PMD_DRV_LOG(DEBUG, sc, "ATTN_GENERAL_ATTN_5!");
3019                                 REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_5, 0x0);
3020                         }
3021                         if (asserted & ATTN_GENERAL_ATTN_6) {
3022                                 PMD_DRV_LOG(DEBUG, sc, "ATTN_GENERAL_ATTN_6!");
3023                                 REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_6, 0x0);
3024                         }
3025                 }
3026         }
3027         /* hardwired */
3028         if (sc->devinfo.int_block == INT_BLOCK_HC) {
3029                 reg_addr =
3030                     (HC_REG_COMMAND_REG + port * 32 +
3031                      COMMAND_REG_ATTN_BITS_SET);
3032         } else {
3033                 reg_addr = (BAR_IGU_INTMEM + IGU_CMD_ATTN_BIT_SET_UPPER * 8);
3034         }
3035
3036         PMD_DRV_LOG(DEBUG, sc, "about to mask 0x%08x at %s addr 0x%08x",
3037                     asserted,
3038                     (sc->devinfo.int_block == INT_BLOCK_HC) ? "HC" : "IGU",
3039                     reg_addr);
3040         REG_WR(sc, reg_addr, asserted);
3041
3042         /* now set back the mask */
3043         if (asserted & ATTN_NIG_FOR_FUNC) {
3044                 /*
3045                  * Verify that IGU ack through BAR was written before restoring
3046                  * NIG mask. This loop should exit after 2-3 iterations max.
3047                  */
3048                 if (sc->devinfo.int_block != INT_BLOCK_HC) {
3049                         cnt = 0;
3050
3051                         do {
3052                                 igu_acked =
3053                                     REG_RD(sc, IGU_REG_ATTENTION_ACK_BITS);
3054                         } while (((igu_acked & ATTN_NIG_FOR_FUNC) == 0)
3055                                  && (++cnt < MAX_IGU_ATTN_ACK_TO));
3056
3057                         if (!igu_acked) {
3058                                 PMD_DRV_LOG(ERR, sc,
3059                                             "Failed to verify IGU ack on time");
3060                         }
3061
3062                         mb();
3063                 }
3064
3065                 REG_WR(sc, nig_int_mask_addr, nig_mask);
3066
3067                 bnx2x_release_phy_lock(sc);
3068         }
3069 }
3070
3071 static void
3072 bnx2x_print_next_block(__rte_unused struct bnx2x_softc *sc, __rte_unused int idx,
3073                      __rte_unused const char *blk)
3074 {
3075         PMD_DRV_LOG(INFO, sc, "%s%s", idx ? ", " : "", blk);
3076 }
3077
3078 static int
3079 bnx2x_check_blocks_with_parity0(struct bnx2x_softc *sc, uint32_t sig, int par_num,
3080                               uint8_t print)
3081 {
3082         uint32_t cur_bit = 0;
3083         int i = 0;
3084
3085         for (i = 0; sig; i++) {
3086                 cur_bit = ((uint32_t) 0x1 << i);
3087                 if (sig & cur_bit) {
3088                         switch (cur_bit) {
3089                         case AEU_INPUTS_ATTN_BITS_BRB_PARITY_ERROR:
3090                                 if (print)
3091                                         bnx2x_print_next_block(sc, par_num++,
3092                                                              "BRB");
3093                                 break;
3094                         case AEU_INPUTS_ATTN_BITS_PARSER_PARITY_ERROR:
3095                                 if (print)
3096                                         bnx2x_print_next_block(sc, par_num++,
3097                                                              "PARSER");
3098                                 break;
3099                         case AEU_INPUTS_ATTN_BITS_TSDM_PARITY_ERROR:
3100                                 if (print)
3101                                         bnx2x_print_next_block(sc, par_num++,
3102                                                              "TSDM");
3103                                 break;
3104                         case AEU_INPUTS_ATTN_BITS_SEARCHER_PARITY_ERROR:
3105                                 if (print)
3106                                         bnx2x_print_next_block(sc, par_num++,
3107                                                              "SEARCHER");
3108                                 break;
3109                         case AEU_INPUTS_ATTN_BITS_TCM_PARITY_ERROR:
3110                                 if (print)
3111                                         bnx2x_print_next_block(sc, par_num++,
3112                                                              "TCM");
3113                                 break;
3114                         case AEU_INPUTS_ATTN_BITS_TSEMI_PARITY_ERROR:
3115                                 if (print)
3116                                         bnx2x_print_next_block(sc, par_num++,
3117                                                              "TSEMI");
3118                                 break;
3119                         case AEU_INPUTS_ATTN_BITS_PBCLIENT_PARITY_ERROR:
3120                                 if (print)
3121                                         bnx2x_print_next_block(sc, par_num++,
3122                                                              "XPB");
3123                                 break;
3124                         }
3125
3126                         /* Clear the bit */
3127                         sig &= ~cur_bit;
3128                 }
3129         }
3130
3131         return par_num;
3132 }
3133
3134 static int
3135 bnx2x_check_blocks_with_parity1(struct bnx2x_softc *sc, uint32_t sig, int par_num,
3136                               uint8_t * global, uint8_t print)
3137 {
3138         int i = 0;
3139         uint32_t cur_bit = 0;
3140         for (i = 0; sig; i++) {
3141                 cur_bit = ((uint32_t) 0x1 << i);
3142                 if (sig & cur_bit) {
3143                         switch (cur_bit) {
3144                         case AEU_INPUTS_ATTN_BITS_PBF_PARITY_ERROR:
3145                                 if (print)
3146                                         bnx2x_print_next_block(sc, par_num++,
3147                                                              "PBF");
3148                                 break;
3149                         case AEU_INPUTS_ATTN_BITS_QM_PARITY_ERROR:
3150                                 if (print)
3151                                         bnx2x_print_next_block(sc, par_num++,
3152                                                              "QM");
3153                                 break;
3154                         case AEU_INPUTS_ATTN_BITS_TIMERS_PARITY_ERROR:
3155                                 if (print)
3156                                         bnx2x_print_next_block(sc, par_num++,
3157                                                              "TM");
3158                                 break;
3159                         case AEU_INPUTS_ATTN_BITS_XSDM_PARITY_ERROR:
3160                                 if (print)
3161                                         bnx2x_print_next_block(sc, par_num++,
3162                                                              "XSDM");
3163                                 break;
3164                         case AEU_INPUTS_ATTN_BITS_XCM_PARITY_ERROR:
3165                                 if (print)
3166                                         bnx2x_print_next_block(sc, par_num++,
3167                                                              "XCM");
3168                                 break;
3169                         case AEU_INPUTS_ATTN_BITS_XSEMI_PARITY_ERROR:
3170                                 if (print)
3171                                         bnx2x_print_next_block(sc, par_num++,
3172                                                              "XSEMI");
3173                                 break;
3174                         case AEU_INPUTS_ATTN_BITS_DOORBELLQ_PARITY_ERROR:
3175                                 if (print)
3176                                         bnx2x_print_next_block(sc, par_num++,
3177                                                              "DOORBELLQ");
3178                                 break;
3179                         case AEU_INPUTS_ATTN_BITS_NIG_PARITY_ERROR:
3180                                 if (print)
3181                                         bnx2x_print_next_block(sc, par_num++,
3182                                                              "NIG");
3183                                 break;
3184                         case AEU_INPUTS_ATTN_BITS_VAUX_PCI_CORE_PARITY_ERROR:
3185                                 if (print)
3186                                         bnx2x_print_next_block(sc, par_num++,
3187                                                              "VAUX PCI CORE");
3188                                 *global = TRUE;
3189                                 break;
3190                         case AEU_INPUTS_ATTN_BITS_DEBUG_PARITY_ERROR:
3191                                 if (print)
3192                                         bnx2x_print_next_block(sc, par_num++,
3193                                                              "DEBUG");
3194                                 break;
3195                         case AEU_INPUTS_ATTN_BITS_USDM_PARITY_ERROR:
3196                                 if (print)
3197                                         bnx2x_print_next_block(sc, par_num++,
3198                                                              "USDM");
3199                                 break;
3200                         case AEU_INPUTS_ATTN_BITS_UCM_PARITY_ERROR:
3201                                 if (print)
3202                                         bnx2x_print_next_block(sc, par_num++,
3203                                                              "UCM");
3204                                 break;
3205                         case AEU_INPUTS_ATTN_BITS_USEMI_PARITY_ERROR:
3206                                 if (print)
3207                                         bnx2x_print_next_block(sc, par_num++,
3208                                                              "USEMI");
3209                                 break;
3210                         case AEU_INPUTS_ATTN_BITS_UPB_PARITY_ERROR:
3211                                 if (print)
3212                                         bnx2x_print_next_block(sc, par_num++,
3213                                                              "UPB");
3214                                 break;
3215                         case AEU_INPUTS_ATTN_BITS_CSDM_PARITY_ERROR:
3216                                 if (print)
3217                                         bnx2x_print_next_block(sc, par_num++,
3218                                                              "CSDM");
3219                                 break;
3220                         case AEU_INPUTS_ATTN_BITS_CCM_PARITY_ERROR:
3221                                 if (print)
3222                                         bnx2x_print_next_block(sc, par_num++,
3223                                                              "CCM");
3224                                 break;
3225                         }
3226
3227                         /* Clear the bit */
3228                         sig &= ~cur_bit;
3229                 }
3230         }
3231
3232         return par_num;
3233 }
3234
3235 static int
3236 bnx2x_check_blocks_with_parity2(struct bnx2x_softc *sc, uint32_t sig, int par_num,
3237                               uint8_t print)
3238 {
3239         uint32_t cur_bit = 0;
3240         int i = 0;
3241
3242         for (i = 0; sig; i++) {
3243                 cur_bit = ((uint32_t) 0x1 << i);
3244                 if (sig & cur_bit) {
3245                         switch (cur_bit) {
3246                         case AEU_INPUTS_ATTN_BITS_CSEMI_PARITY_ERROR:
3247                                 if (print)
3248                                         bnx2x_print_next_block(sc, par_num++,
3249                                                              "CSEMI");
3250                                 break;
3251                         case AEU_INPUTS_ATTN_BITS_PXP_PARITY_ERROR:
3252                                 if (print)
3253                                         bnx2x_print_next_block(sc, par_num++,
3254                                                              "PXP");
3255                                 break;
3256                         case AEU_IN_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR:
3257                                 if (print)
3258                                         bnx2x_print_next_block(sc, par_num++,
3259                                                              "PXPPCICLOCKCLIENT");
3260                                 break;
3261                         case AEU_INPUTS_ATTN_BITS_CFC_PARITY_ERROR:
3262                                 if (print)
3263                                         bnx2x_print_next_block(sc, par_num++,
3264                                                              "CFC");
3265                                 break;
3266                         case AEU_INPUTS_ATTN_BITS_CDU_PARITY_ERROR:
3267                                 if (print)
3268                                         bnx2x_print_next_block(sc, par_num++,
3269                                                              "CDU");
3270                                 break;
3271                         case AEU_INPUTS_ATTN_BITS_DMAE_PARITY_ERROR:
3272                                 if (print)
3273                                         bnx2x_print_next_block(sc, par_num++,
3274                                                              "DMAE");
3275                                 break;
3276                         case AEU_INPUTS_ATTN_BITS_IGU_PARITY_ERROR:
3277                                 if (print)
3278                                         bnx2x_print_next_block(sc, par_num++,
3279                                                              "IGU");
3280                                 break;
3281                         case AEU_INPUTS_ATTN_BITS_MISC_PARITY_ERROR:
3282                                 if (print)
3283                                         bnx2x_print_next_block(sc, par_num++,
3284                                                              "MISC");
3285                                 break;
3286                         }
3287
3288                         /* Clear the bit */
3289                         sig &= ~cur_bit;
3290                 }
3291         }
3292
3293         return par_num;
3294 }
3295
3296 static int
3297 bnx2x_check_blocks_with_parity3(struct bnx2x_softc *sc, uint32_t sig, int par_num,
3298                               uint8_t * global, uint8_t print)
3299 {
3300         uint32_t cur_bit = 0;
3301         int i = 0;
3302
3303         for (i = 0; sig; i++) {
3304                 cur_bit = ((uint32_t) 0x1 << i);
3305                 if (sig & cur_bit) {
3306                         switch (cur_bit) {
3307                         case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_ROM_PARITY:
3308                                 if (print)
3309                                         bnx2x_print_next_block(sc, par_num++,
3310                                                              "MCP ROM");
3311                                 *global = TRUE;
3312                                 break;
3313                         case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_RX_PARITY:
3314                                 if (print)
3315                                         bnx2x_print_next_block(sc, par_num++,
3316                                                              "MCP UMP RX");
3317                                 *global = TRUE;
3318                                 break;
3319                         case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_TX_PARITY:
3320                                 if (print)
3321                                         bnx2x_print_next_block(sc, par_num++,
3322                                                              "MCP UMP TX");
3323                                 *global = TRUE;
3324                                 break;
3325                         case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_SCPAD_PARITY:
3326                                 if (print)
3327                                         bnx2x_print_next_block(sc, par_num++,
3328                                                              "MCP SCPAD");
3329                                 *global = TRUE;
3330                                 break;
3331                         }
3332
3333                         /* Clear the bit */
3334                         sig &= ~cur_bit;
3335                 }
3336         }
3337
3338         return par_num;
3339 }
3340
3341 static int
3342 bnx2x_check_blocks_with_parity4(struct bnx2x_softc *sc, uint32_t sig, int par_num,
3343                               uint8_t print)
3344 {
3345         uint32_t cur_bit = 0;
3346         int i = 0;
3347
3348         for (i = 0; sig; i++) {
3349                 cur_bit = ((uint32_t) 0x1 << i);
3350                 if (sig & cur_bit) {
3351                         switch (cur_bit) {
3352                         case AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR:
3353                                 if (print)
3354                                         bnx2x_print_next_block(sc, par_num++,
3355                                                              "PGLUE_B");
3356                                 break;
3357                         case AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR:
3358                                 if (print)
3359                                         bnx2x_print_next_block(sc, par_num++,
3360                                                              "ATC");
3361                                 break;
3362                         }
3363
3364                         /* Clear the bit */
3365                         sig &= ~cur_bit;
3366                 }
3367         }
3368
3369         return par_num;
3370 }
3371
3372 static uint8_t
3373 bnx2x_parity_attn(struct bnx2x_softc *sc, uint8_t * global, uint8_t print,
3374                 uint32_t * sig)
3375 {
3376         int par_num = 0;
3377
3378         if ((sig[0] & HW_PRTY_ASSERT_SET_0) ||
3379             (sig[1] & HW_PRTY_ASSERT_SET_1) ||
3380             (sig[2] & HW_PRTY_ASSERT_SET_2) ||
3381             (sig[3] & HW_PRTY_ASSERT_SET_3) ||
3382             (sig[4] & HW_PRTY_ASSERT_SET_4)) {
3383                 PMD_DRV_LOG(ERR, sc,
3384                             "Parity error: HW block parity attention:"
3385                             "[0]:0x%08x [1]:0x%08x [2]:0x%08x [3]:0x%08x [4]:0x%08x",
3386                             (uint32_t) (sig[0] & HW_PRTY_ASSERT_SET_0),
3387                             (uint32_t) (sig[1] & HW_PRTY_ASSERT_SET_1),
3388                             (uint32_t) (sig[2] & HW_PRTY_ASSERT_SET_2),
3389                             (uint32_t) (sig[3] & HW_PRTY_ASSERT_SET_3),
3390                             (uint32_t) (sig[4] & HW_PRTY_ASSERT_SET_4));
3391
3392                 if (print)
3393                         PMD_DRV_LOG(INFO, sc, "Parity errors detected in blocks: ");
3394
3395                 par_num =
3396                     bnx2x_check_blocks_with_parity0(sc, sig[0] &
3397                                                   HW_PRTY_ASSERT_SET_0,
3398                                                   par_num, print);
3399                 par_num =
3400                     bnx2x_check_blocks_with_parity1(sc, sig[1] &
3401                                                   HW_PRTY_ASSERT_SET_1,
3402                                                   par_num, global, print);
3403                 par_num =
3404                     bnx2x_check_blocks_with_parity2(sc, sig[2] &
3405                                                   HW_PRTY_ASSERT_SET_2,
3406                                                   par_num, print);
3407                 par_num =
3408                     bnx2x_check_blocks_with_parity3(sc, sig[3] &
3409                                                   HW_PRTY_ASSERT_SET_3,
3410                                                   par_num, global, print);
3411                 par_num =
3412                     bnx2x_check_blocks_with_parity4(sc, sig[4] &
3413                                                   HW_PRTY_ASSERT_SET_4,
3414                                                   par_num, print);
3415
3416                 if (print)
3417                         PMD_DRV_LOG(INFO, sc, "");
3418
3419                 return TRUE;
3420         }
3421
3422         return FALSE;
3423 }
3424
3425 static uint8_t
3426 bnx2x_chk_parity_attn(struct bnx2x_softc *sc, uint8_t * global, uint8_t print)
3427 {
3428         struct attn_route attn = { {0} };
3429         int port = SC_PORT(sc);
3430
3431         attn.sig[0] = REG_RD(sc, MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 + port * 4);
3432         attn.sig[1] = REG_RD(sc, MISC_REG_AEU_AFTER_INVERT_2_FUNC_0 + port * 4);
3433         attn.sig[2] = REG_RD(sc, MISC_REG_AEU_AFTER_INVERT_3_FUNC_0 + port * 4);
3434         attn.sig[3] = REG_RD(sc, MISC_REG_AEU_AFTER_INVERT_4_FUNC_0 + port * 4);
3435
3436         if (!CHIP_IS_E1x(sc))
3437                 attn.sig[4] =
3438                     REG_RD(sc, MISC_REG_AEU_AFTER_INVERT_5_FUNC_0 + port * 4);
3439
3440         return bnx2x_parity_attn(sc, global, print, attn.sig);
3441 }
3442
3443 static void bnx2x_attn_int_deasserted4(struct bnx2x_softc *sc, uint32_t attn)
3444 {
3445         uint32_t val;
3446
3447         if (attn & AEU_INPUTS_ATTN_BITS_PGLUE_HW_INTERRUPT) {
3448                 val = REG_RD(sc, PGLUE_B_REG_PGLUE_B_INT_STS_CLR);
3449                 PMD_DRV_LOG(INFO, sc, "ERROR: PGLUE hw attention 0x%08x", val);
3450                 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_ADDRESS_ERROR)
3451                         PMD_DRV_LOG(INFO, sc,
3452                                     "ERROR: PGLUE_B_PGLUE_B_INT_STS_REG_ADDRESS_ERROR");
3453                 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_INCORRECT_RCV_BEHAVIOR)
3454                         PMD_DRV_LOG(INFO, sc,
3455                                     "ERROR: PGLUE_B_PGLUE_B_INT_STS_REG_INCORRECT_RCV_BEHAVIOR");
3456                 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_WAS_ERROR_ATTN)
3457                         PMD_DRV_LOG(INFO, sc,
3458                                     "ERROR: PGLUE_B_PGLUE_B_INT_STS_REG_WAS_ERROR_ATTN");
3459                 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_VF_LENGTH_VIOLATION_ATTN)
3460                         PMD_DRV_LOG(INFO, sc,
3461                                     "ERROR: PGLUE_B_PGLUE_B_INT_STS_REG_VF_LENGTH_VIOLATION_ATTN");
3462                 if (val &
3463                     PGLUE_B_PGLUE_B_INT_STS_REG_VF_GRC_SPACE_VIOLATION_ATTN)
3464                         PMD_DRV_LOG(INFO, sc,
3465                                     "ERROR: PGLUE_B_PGLUE_B_INT_STS_REG_VF_GRC_SPACE_VIOLATION_ATTN");
3466                 if (val &
3467                     PGLUE_B_PGLUE_B_INT_STS_REG_VF_MSIX_BAR_VIOLATION_ATTN)
3468                         PMD_DRV_LOG(INFO, sc,
3469                                     "ERROR: PGLUE_B_PGLUE_B_INT_STS_REG_VF_MSIX_BAR_VIOLATION_ATTN");
3470                 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_ERROR_ATTN)
3471                         PMD_DRV_LOG(INFO, sc,
3472                                     "ERROR: PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_ERROR_ATTN");
3473                 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_IN_TWO_RCBS_ATTN)
3474                         PMD_DRV_LOG(INFO, sc,
3475                                     "ERROR: PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_IN_TWO_RCBS_ATTN");
3476                 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_CSSNOOP_FIFO_OVERFLOW)
3477                         PMD_DRV_LOG(INFO, sc,
3478                                     "ERROR: PGLUE_B_PGLUE_B_INT_STS_REG_CSSNOOP_FIFO_OVERFLOW");
3479         }
3480
3481         if (attn & AEU_INPUTS_ATTN_BITS_ATC_HW_INTERRUPT) {
3482                 val = REG_RD(sc, ATC_REG_ATC_INT_STS_CLR);
3483                 PMD_DRV_LOG(INFO, sc, "ERROR: ATC hw attention 0x%08x", val);
3484                 if (val & ATC_ATC_INT_STS_REG_ADDRESS_ERROR)
3485                         PMD_DRV_LOG(INFO, sc,
3486                                     "ERROR: ATC_ATC_INT_STS_REG_ADDRESS_ERROR");
3487                 if (val & ATC_ATC_INT_STS_REG_ATC_TCPL_TO_NOT_PEND)
3488                         PMD_DRV_LOG(INFO, sc,
3489                                     "ERROR: ATC_ATC_INT_STS_REG_ATC_TCPL_TO_NOT_PEND");
3490                 if (val & ATC_ATC_INT_STS_REG_ATC_GPA_MULTIPLE_HITS)
3491                         PMD_DRV_LOG(INFO, sc,
3492                                     "ERROR: ATC_ATC_INT_STS_REG_ATC_GPA_MULTIPLE_HITS");
3493                 if (val & ATC_ATC_INT_STS_REG_ATC_RCPL_TO_EMPTY_CNT)
3494                         PMD_DRV_LOG(INFO, sc,
3495                                     "ERROR: ATC_ATC_INT_STS_REG_ATC_RCPL_TO_EMPTY_CNT");
3496                 if (val & ATC_ATC_INT_STS_REG_ATC_TCPL_ERROR)
3497                         PMD_DRV_LOG(INFO, sc,
3498                                     "ERROR: ATC_ATC_INT_STS_REG_ATC_TCPL_ERROR");
3499                 if (val & ATC_ATC_INT_STS_REG_ATC_IREQ_LESS_THAN_STU)
3500                         PMD_DRV_LOG(INFO, sc,
3501                                     "ERROR: ATC_ATC_INT_STS_REG_ATC_IREQ_LESS_THAN_STU");
3502         }
3503
3504         if (attn & (AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR |
3505                     AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR)) {
3506                 PMD_DRV_LOG(INFO, sc,
3507                             "ERROR: FATAL parity attention set4 0x%08x",
3508                             (uint32_t) (attn &
3509                                         (AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR
3510                                          |
3511                                          AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR)));
3512         }
3513 }
3514
3515 static void bnx2x_e1h_disable(struct bnx2x_softc *sc)
3516 {
3517         int port = SC_PORT(sc);
3518
3519         REG_WR(sc, NIG_REG_LLH0_FUNC_EN + port * 8, 0);
3520 }
3521
3522 static void bnx2x_e1h_enable(struct bnx2x_softc *sc)
3523 {
3524         int port = SC_PORT(sc);
3525
3526         REG_WR(sc, NIG_REG_LLH0_FUNC_EN + port * 8, 1);
3527 }
3528
3529 /*
3530  * called due to MCP event (on pmf):
3531  *   reread new bandwidth configuration
3532  *   configure FW
3533  *   notify others function about the change
3534  */
3535 static void bnx2x_config_mf_bw(struct bnx2x_softc *sc)
3536 {
3537         if (sc->link_vars.link_up) {
3538                 bnx2x_cmng_fns_init(sc, TRUE, CMNG_FNS_MINMAX);
3539                 bnx2x_link_sync_notify(sc);
3540         }
3541
3542         storm_memset_cmng(sc, &sc->cmng, SC_PORT(sc));
3543 }
3544
3545 static void bnx2x_set_mf_bw(struct bnx2x_softc *sc)
3546 {
3547         bnx2x_config_mf_bw(sc);
3548         bnx2x_fw_command(sc, DRV_MSG_CODE_SET_MF_BW_ACK, 0);
3549 }
3550
3551 static void bnx2x_handle_eee_event(struct bnx2x_softc *sc)
3552 {
3553         bnx2x_fw_command(sc, DRV_MSG_CODE_EEE_RESULTS_ACK, 0);
3554 }
3555
3556 #define DRV_INFO_ETH_STAT_NUM_MACS_REQUIRED 3
3557
3558 static void bnx2x_drv_info_ether_stat(struct bnx2x_softc *sc)
3559 {
3560         struct eth_stats_info *ether_stat = &sc->sp->drv_info_to_mcp.ether_stat;
3561
3562         strncpy(ether_stat->version, BNX2X_DRIVER_VERSION,
3563                 ETH_STAT_INFO_VERSION_LEN);
3564
3565         sc->sp_objs[0].mac_obj.get_n_elements(sc, &sc->sp_objs[0].mac_obj,
3566                                               DRV_INFO_ETH_STAT_NUM_MACS_REQUIRED,
3567                                               ether_stat->mac_local + MAC_PAD,
3568                                               MAC_PAD, ETH_ALEN);
3569
3570         ether_stat->mtu_size = sc->mtu;
3571
3572         ether_stat->feature_flags |= FEATURE_ETH_CHKSUM_OFFLOAD_MASK;
3573         ether_stat->promiscuous_mode = 0;       // (flags & PROMISC) ? 1 : 0;
3574
3575         ether_stat->txq_size = sc->tx_ring_size;
3576         ether_stat->rxq_size = sc->rx_ring_size;
3577 }
3578
3579 static void bnx2x_handle_drv_info_req(struct bnx2x_softc *sc)
3580 {
3581         enum drv_info_opcode op_code;
3582         uint32_t drv_info_ctl = SHMEM2_RD(sc, drv_info_control);
3583
3584         /* if drv_info version supported by MFW doesn't match - send NACK */
3585         if ((drv_info_ctl & DRV_INFO_CONTROL_VER_MASK) != DRV_INFO_CUR_VER) {
3586                 bnx2x_fw_command(sc, DRV_MSG_CODE_DRV_INFO_NACK, 0);
3587                 return;
3588         }
3589
3590         op_code = ((drv_info_ctl & DRV_INFO_CONTROL_OP_CODE_MASK) >>
3591                    DRV_INFO_CONTROL_OP_CODE_SHIFT);
3592
3593         memset(&sc->sp->drv_info_to_mcp, 0, sizeof(union drv_info_to_mcp));
3594
3595         switch (op_code) {
3596         case ETH_STATS_OPCODE:
3597                 bnx2x_drv_info_ether_stat(sc);
3598                 break;
3599         case FCOE_STATS_OPCODE:
3600         case ISCSI_STATS_OPCODE:
3601         default:
3602                 /* if op code isn't supported - send NACK */
3603                 bnx2x_fw_command(sc, DRV_MSG_CODE_DRV_INFO_NACK, 0);
3604                 return;
3605         }
3606
3607         /*
3608          * If we got drv_info attn from MFW then these fields are defined in
3609          * shmem2 for sure
3610          */
3611         SHMEM2_WR(sc, drv_info_host_addr_lo,
3612                   U64_LO(BNX2X_SP_MAPPING(sc, drv_info_to_mcp)));
3613         SHMEM2_WR(sc, drv_info_host_addr_hi,
3614                   U64_HI(BNX2X_SP_MAPPING(sc, drv_info_to_mcp)));
3615
3616         bnx2x_fw_command(sc, DRV_MSG_CODE_DRV_INFO_ACK, 0);
3617 }
3618
3619 static void bnx2x_dcc_event(struct bnx2x_softc *sc, uint32_t dcc_event)
3620 {
3621         if (dcc_event & DRV_STATUS_DCC_DISABLE_ENABLE_PF) {
3622 /*
3623  * This is the only place besides the function initialization
3624  * where the sc->flags can change so it is done without any
3625  * locks
3626  */
3627                 if (sc->devinfo.
3628                     mf_info.mf_config[SC_VN(sc)] & FUNC_MF_CFG_FUNC_DISABLED) {
3629                         PMD_DRV_LOG(DEBUG, sc, "mf_cfg function disabled");
3630                         sc->flags |= BNX2X_MF_FUNC_DIS;
3631                         bnx2x_e1h_disable(sc);
3632                 } else {
3633                         PMD_DRV_LOG(DEBUG, sc, "mf_cfg function enabled");
3634                         sc->flags &= ~BNX2X_MF_FUNC_DIS;
3635                         bnx2x_e1h_enable(sc);
3636                 }
3637                 dcc_event &= ~DRV_STATUS_DCC_DISABLE_ENABLE_PF;
3638         }
3639
3640         if (dcc_event & DRV_STATUS_DCC_BANDWIDTH_ALLOCATION) {
3641                 bnx2x_config_mf_bw(sc);
3642                 dcc_event &= ~DRV_STATUS_DCC_BANDWIDTH_ALLOCATION;
3643         }
3644
3645         /* Report results to MCP */
3646         if (dcc_event)
3647                 bnx2x_fw_command(sc, DRV_MSG_CODE_DCC_FAILURE, 0);
3648         else
3649                 bnx2x_fw_command(sc, DRV_MSG_CODE_DCC_OK, 0);
3650 }
3651
3652 static void bnx2x_pmf_update(struct bnx2x_softc *sc)
3653 {
3654         int port = SC_PORT(sc);
3655         uint32_t val;
3656
3657         sc->port.pmf = 1;
3658
3659         /*
3660          * We need the mb() to ensure the ordering between the writing to
3661          * sc->port.pmf here and reading it from the bnx2x_periodic_task().
3662          */
3663         mb();
3664
3665         /* enable nig attention */
3666         val = (0xff0f | (1 << (SC_VN(sc) + 4)));
3667         if (sc->devinfo.int_block == INT_BLOCK_HC) {
3668                 REG_WR(sc, HC_REG_TRAILING_EDGE_0 + port * 8, val);
3669                 REG_WR(sc, HC_REG_LEADING_EDGE_0 + port * 8, val);
3670         } else if (!CHIP_IS_E1x(sc)) {
3671                 REG_WR(sc, IGU_REG_TRAILING_EDGE_LATCH, val);
3672                 REG_WR(sc, IGU_REG_LEADING_EDGE_LATCH, val);
3673         }
3674
3675         bnx2x_stats_handle(sc, STATS_EVENT_PMF);
3676 }
3677
3678 static int bnx2x_mc_assert(struct bnx2x_softc *sc)
3679 {
3680         char last_idx;
3681         int i, rc = 0;
3682         __rte_unused uint32_t row0, row1, row2, row3;
3683
3684         /* XSTORM */
3685         last_idx =
3686             REG_RD8(sc, BAR_XSTRORM_INTMEM + XSTORM_ASSERT_LIST_INDEX_OFFSET);
3687         if (last_idx)
3688                 PMD_DRV_LOG(ERR, sc, "XSTORM_ASSERT_LIST_INDEX 0x%x", last_idx);
3689
3690         /* print the asserts */
3691         for (i = 0; i < STORM_ASSERT_ARRAY_SIZE; i++) {
3692
3693                 row0 =
3694                     REG_RD(sc,
3695                            BAR_XSTRORM_INTMEM + XSTORM_ASSERT_LIST_OFFSET(i));
3696                 row1 =
3697                     REG_RD(sc,
3698                            BAR_XSTRORM_INTMEM + XSTORM_ASSERT_LIST_OFFSET(i) +
3699                            4);
3700                 row2 =
3701                     REG_RD(sc,
3702                            BAR_XSTRORM_INTMEM + XSTORM_ASSERT_LIST_OFFSET(i) +
3703                            8);
3704                 row3 =
3705                     REG_RD(sc,
3706                            BAR_XSTRORM_INTMEM + XSTORM_ASSERT_LIST_OFFSET(i) +
3707                            12);
3708
3709                 if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) {
3710                         PMD_DRV_LOG(ERR, sc,
3711                                     "XSTORM_ASSERT_INDEX 0x%x = 0x%08x 0x%08x 0x%08x 0x%08x",
3712                                     i, row3, row2, row1, row0);
3713                         rc++;
3714                 } else {
3715                         break;
3716                 }
3717         }
3718
3719         /* TSTORM */
3720         last_idx =
3721             REG_RD8(sc, BAR_TSTRORM_INTMEM + TSTORM_ASSERT_LIST_INDEX_OFFSET);
3722         if (last_idx) {
3723                 PMD_DRV_LOG(ERR, sc, "TSTORM_ASSERT_LIST_INDEX 0x%x", last_idx);
3724         }
3725
3726         /* print the asserts */
3727         for (i = 0; i < STORM_ASSERT_ARRAY_SIZE; i++) {
3728
3729                 row0 =
3730                     REG_RD(sc,
3731                            BAR_TSTRORM_INTMEM + TSTORM_ASSERT_LIST_OFFSET(i));
3732                 row1 =
3733                     REG_RD(sc,
3734                            BAR_TSTRORM_INTMEM + TSTORM_ASSERT_LIST_OFFSET(i) +
3735                            4);
3736                 row2 =
3737                     REG_RD(sc,
3738                            BAR_TSTRORM_INTMEM + TSTORM_ASSERT_LIST_OFFSET(i) +
3739                            8);
3740                 row3 =
3741                     REG_RD(sc,
3742                            BAR_TSTRORM_INTMEM + TSTORM_ASSERT_LIST_OFFSET(i) +
3743                            12);
3744
3745                 if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) {
3746                         PMD_DRV_LOG(ERR, sc,
3747                                     "TSTORM_ASSERT_INDEX 0x%x = 0x%08x 0x%08x 0x%08x 0x%08x",
3748                                     i, row3, row2, row1, row0);
3749                         rc++;
3750                 } else {
3751                         break;
3752                 }
3753         }
3754
3755         /* CSTORM */
3756         last_idx =
3757             REG_RD8(sc, BAR_CSTRORM_INTMEM + CSTORM_ASSERT_LIST_INDEX_OFFSET);
3758         if (last_idx) {
3759                 PMD_DRV_LOG(ERR, sc, "CSTORM_ASSERT_LIST_INDEX 0x%x", last_idx);
3760         }
3761
3762         /* print the asserts */
3763         for (i = 0; i < STORM_ASSERT_ARRAY_SIZE; i++) {
3764
3765                 row0 =
3766                     REG_RD(sc,
3767                            BAR_CSTRORM_INTMEM + CSTORM_ASSERT_LIST_OFFSET(i));
3768                 row1 =
3769                     REG_RD(sc,
3770                            BAR_CSTRORM_INTMEM + CSTORM_ASSERT_LIST_OFFSET(i) +
3771                            4);
3772                 row2 =
3773                     REG_RD(sc,
3774                            BAR_CSTRORM_INTMEM + CSTORM_ASSERT_LIST_OFFSET(i) +
3775                            8);
3776                 row3 =
3777                     REG_RD(sc,
3778                            BAR_CSTRORM_INTMEM + CSTORM_ASSERT_LIST_OFFSET(i) +
3779                            12);
3780
3781                 if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) {
3782                         PMD_DRV_LOG(ERR, sc,
3783                                     "CSTORM_ASSERT_INDEX 0x%x = 0x%08x 0x%08x 0x%08x 0x%08x",
3784                                     i, row3, row2, row1, row0);
3785                         rc++;
3786                 } else {
3787                         break;
3788                 }
3789         }
3790
3791         /* USTORM */
3792         last_idx =
3793             REG_RD8(sc, BAR_USTRORM_INTMEM + USTORM_ASSERT_LIST_INDEX_OFFSET);
3794         if (last_idx) {
3795                 PMD_DRV_LOG(ERR, sc, "USTORM_ASSERT_LIST_INDEX 0x%x", last_idx);
3796         }
3797
3798         /* print the asserts */
3799         for (i = 0; i < STORM_ASSERT_ARRAY_SIZE; i++) {
3800
3801                 row0 =
3802                     REG_RD(sc,
3803                            BAR_USTRORM_INTMEM + USTORM_ASSERT_LIST_OFFSET(i));
3804                 row1 =
3805                     REG_RD(sc,
3806                            BAR_USTRORM_INTMEM + USTORM_ASSERT_LIST_OFFSET(i) +
3807                            4);
3808                 row2 =
3809                     REG_RD(sc,
3810                            BAR_USTRORM_INTMEM + USTORM_ASSERT_LIST_OFFSET(i) +
3811                            8);
3812                 row3 =
3813                     REG_RD(sc,
3814                            BAR_USTRORM_INTMEM + USTORM_ASSERT_LIST_OFFSET(i) +
3815                            12);
3816
3817                 if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) {
3818                         PMD_DRV_LOG(ERR, sc,
3819                                     "USTORM_ASSERT_INDEX 0x%x = 0x%08x 0x%08x 0x%08x 0x%08x",
3820                                     i, row3, row2, row1, row0);
3821                         rc++;
3822                 } else {
3823                         break;
3824                 }
3825         }
3826
3827         return rc;
3828 }
3829
3830 static void bnx2x_attn_int_deasserted3(struct bnx2x_softc *sc, uint32_t attn)
3831 {
3832         int func = SC_FUNC(sc);
3833         uint32_t val;
3834
3835         if (attn & EVEREST_GEN_ATTN_IN_USE_MASK) {
3836
3837                 if (attn & BNX2X_PMF_LINK_ASSERT(sc)) {
3838
3839                         REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_12 + func * 4, 0);
3840                         bnx2x_read_mf_cfg(sc);
3841                         sc->devinfo.mf_info.mf_config[SC_VN(sc)] =
3842                             MFCFG_RD(sc,
3843                                      func_mf_config[SC_ABS_FUNC(sc)].config);
3844                         val =
3845                             SHMEM_RD(sc, func_mb[SC_FW_MB_IDX(sc)].drv_status);
3846
3847                         if (val & DRV_STATUS_DCC_EVENT_MASK)
3848                                 bnx2x_dcc_event(sc,
3849                                               (val &
3850                                                DRV_STATUS_DCC_EVENT_MASK));
3851
3852                         if (val & DRV_STATUS_SET_MF_BW)
3853                                 bnx2x_set_mf_bw(sc);
3854
3855                         if (val & DRV_STATUS_DRV_INFO_REQ)
3856                                 bnx2x_handle_drv_info_req(sc);
3857
3858                         if ((sc->port.pmf == 0) && (val & DRV_STATUS_PMF))
3859                                 bnx2x_pmf_update(sc);
3860
3861                         if (val & DRV_STATUS_EEE_NEGOTIATION_RESULTS)
3862                                 bnx2x_handle_eee_event(sc);
3863
3864                         if (sc->link_vars.periodic_flags &
3865                             ELINK_PERIODIC_FLAGS_LINK_EVENT) {
3866                                 /* sync with link */
3867                                 bnx2x_acquire_phy_lock(sc);
3868                                 sc->link_vars.periodic_flags &=
3869                                     ~ELINK_PERIODIC_FLAGS_LINK_EVENT;
3870                                 bnx2x_release_phy_lock(sc);
3871                                 if (IS_MF(sc)) {
3872                                         bnx2x_link_sync_notify(sc);
3873                                 }
3874                                 bnx2x_link_report(sc);
3875                         }
3876
3877                         /*
3878                          * Always call it here: bnx2x_link_report() will
3879                          * prevent the link indication duplication.
3880                          */
3881                         bnx2x_link_status_update(sc);
3882
3883                 } else if (attn & BNX2X_MC_ASSERT_BITS) {
3884
3885                         PMD_DRV_LOG(ERR, sc, "MC assert!");
3886                         bnx2x_mc_assert(sc);
3887                         REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_10, 0);
3888                         REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_9, 0);
3889                         REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_8, 0);
3890                         REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_7, 0);
3891                         rte_panic("MC assert!");
3892
3893                 } else if (attn & BNX2X_MCP_ASSERT) {
3894
3895                         PMD_DRV_LOG(ERR, sc, "MCP assert!");
3896                         REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_11, 0);
3897
3898                 } else {
3899                         PMD_DRV_LOG(ERR, sc,
3900                                     "Unknown HW assert! (attn 0x%08x)", attn);
3901                 }
3902         }
3903
3904         if (attn & EVEREST_LATCHED_ATTN_IN_USE_MASK) {
3905                 PMD_DRV_LOG(ERR, sc, "LATCHED attention 0x%08x (masked)", attn);
3906                 if (attn & BNX2X_GRC_TIMEOUT) {
3907                         val = REG_RD(sc, MISC_REG_GRC_TIMEOUT_ATTN);
3908                         PMD_DRV_LOG(ERR, sc, "GRC time-out 0x%08x", val);
3909                 }
3910                 if (attn & BNX2X_GRC_RSV) {
3911                         val = REG_RD(sc, MISC_REG_GRC_RSV_ATTN);
3912                         PMD_DRV_LOG(ERR, sc, "GRC reserved 0x%08x", val);
3913                 }
3914                 REG_WR(sc, MISC_REG_AEU_CLR_LATCH_SIGNAL, 0x7ff);
3915         }
3916 }
3917
3918 static void bnx2x_attn_int_deasserted2(struct bnx2x_softc *sc, uint32_t attn)
3919 {
3920         int port = SC_PORT(sc);
3921         int reg_offset;
3922         uint32_t val0, mask0, val1, mask1;
3923         uint32_t val;
3924
3925         if (attn & AEU_INPUTS_ATTN_BITS_CFC_HW_INTERRUPT) {
3926                 val = REG_RD(sc, CFC_REG_CFC_INT_STS_CLR);
3927                 PMD_DRV_LOG(ERR, sc, "CFC hw attention 0x%08x", val);
3928 /* CFC error attention */
3929                 if (val & 0x2) {
3930                         PMD_DRV_LOG(ERR, sc, "FATAL error from CFC");
3931                 }
3932         }
3933
3934         if (attn & AEU_INPUTS_ATTN_BITS_PXP_HW_INTERRUPT) {
3935                 val = REG_RD(sc, PXP_REG_PXP_INT_STS_CLR_0);
3936                 PMD_DRV_LOG(ERR, sc, "PXP hw attention-0 0x%08x", val);
3937 /* RQ_USDMDP_FIFO_OVERFLOW */
3938                 if (val & 0x18000) {
3939                         PMD_DRV_LOG(ERR, sc, "FATAL error from PXP");
3940                 }
3941
3942                 if (!CHIP_IS_E1x(sc)) {
3943                         val = REG_RD(sc, PXP_REG_PXP_INT_STS_CLR_1);
3944                         PMD_DRV_LOG(ERR, sc, "PXP hw attention-1 0x%08x", val);
3945                 }
3946         }
3947 #define PXP2_EOP_ERROR_BIT  PXP2_PXP2_INT_STS_CLR_0_REG_WR_PGLUE_EOP_ERROR
3948 #define AEU_PXP2_HW_INT_BIT AEU_INPUTS_ATTN_BITS_PXPPCICLOCKCLIENT_HW_INTERRUPT
3949
3950         if (attn & AEU_PXP2_HW_INT_BIT) {
3951 /*  CQ47854 workaround do not panic on
3952  *  PXP2_PXP2_INT_STS_0_REG_WR_PGLUE_EOP_ERROR
3953  */
3954                 if (!CHIP_IS_E1x(sc)) {
3955                         mask0 = REG_RD(sc, PXP2_REG_PXP2_INT_MASK_0);
3956                         val1 = REG_RD(sc, PXP2_REG_PXP2_INT_STS_1);
3957                         mask1 = REG_RD(sc, PXP2_REG_PXP2_INT_MASK_1);
3958                         val0 = REG_RD(sc, PXP2_REG_PXP2_INT_STS_0);
3959                         /*
3960                          * If the only PXP2_EOP_ERROR_BIT is set in
3961                          * STS0 and STS1 - clear it
3962                          *
3963                          * probably we lose additional attentions between
3964                          * STS0 and STS_CLR0, in this case user will not
3965                          * be notified about them
3966                          */
3967                         if (val0 & mask0 & PXP2_EOP_ERROR_BIT &&
3968                             !(val1 & mask1))
3969                                 val0 = REG_RD(sc, PXP2_REG_PXP2_INT_STS_CLR_0);
3970
3971                         /* print the register, since no one can restore it */
3972                         PMD_DRV_LOG(ERR, sc,
3973                                     "PXP2_REG_PXP2_INT_STS_CLR_0 0x%08x", val0);
3974
3975                         /*
3976                          * if PXP2_PXP2_INT_STS_0_REG_WR_PGLUE_EOP_ERROR
3977                          * then notify
3978                          */
3979                         if (val0 & PXP2_EOP_ERROR_BIT) {
3980                                 PMD_DRV_LOG(ERR, sc, "PXP2_WR_PGLUE_EOP_ERROR");
3981
3982                                 /*
3983                                  * if only PXP2_PXP2_INT_STS_0_REG_WR_PGLUE_EOP_ERROR is
3984                                  * set then clear attention from PXP2 block without panic
3985                                  */
3986                                 if (((val0 & mask0) == PXP2_EOP_ERROR_BIT) &&
3987                                     ((val1 & mask1) == 0))
3988                                         attn &= ~AEU_PXP2_HW_INT_BIT;
3989                         }
3990                 }
3991         }
3992
3993         if (attn & HW_INTERRUT_ASSERT_SET_2) {
3994                 reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_2 :
3995                               MISC_REG_AEU_ENABLE1_FUNC_0_OUT_2);
3996
3997                 val = REG_RD(sc, reg_offset);
3998                 val &= ~(attn & HW_INTERRUT_ASSERT_SET_2);
3999                 REG_WR(sc, reg_offset, val);
4000
4001                 PMD_DRV_LOG(ERR, sc,
4002                             "FATAL HW block attention set2 0x%x",
4003                             (uint32_t) (attn & HW_INTERRUT_ASSERT_SET_2));
4004                 rte_panic("HW block attention set2");
4005         }
4006 }
4007
4008 static void bnx2x_attn_int_deasserted1(struct bnx2x_softc *sc, uint32_t attn)
4009 {
4010         int port = SC_PORT(sc);
4011         int reg_offset;
4012         uint32_t val;
4013
4014         if (attn & AEU_INPUTS_ATTN_BITS_DOORBELLQ_HW_INTERRUPT) {
4015                 val = REG_RD(sc, DORQ_REG_DORQ_INT_STS_CLR);
4016                 PMD_DRV_LOG(ERR, sc, "DB hw attention 0x%08x", val);
4017 /* DORQ discard attention */
4018                 if (val & 0x2) {
4019                         PMD_DRV_LOG(ERR, sc, "FATAL error from DORQ");
4020                 }
4021         }
4022
4023         if (attn & HW_INTERRUT_ASSERT_SET_1) {
4024                 reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_1 :
4025                               MISC_REG_AEU_ENABLE1_FUNC_0_OUT_1);
4026
4027                 val = REG_RD(sc, reg_offset);
4028                 val &= ~(attn & HW_INTERRUT_ASSERT_SET_1);
4029                 REG_WR(sc, reg_offset, val);
4030
4031                 PMD_DRV_LOG(ERR, sc,
4032                             "FATAL HW block attention set1 0x%08x",
4033                             (uint32_t) (attn & HW_INTERRUT_ASSERT_SET_1));
4034                 rte_panic("HW block attention set1");
4035         }
4036 }
4037
4038 static void bnx2x_attn_int_deasserted0(struct bnx2x_softc *sc, uint32_t attn)
4039 {
4040         int port = SC_PORT(sc);
4041         int reg_offset;
4042         uint32_t val;
4043
4044         reg_offset = (port) ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 :
4045             MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0;
4046
4047         if (attn & AEU_INPUTS_ATTN_BITS_SPIO5) {
4048                 val = REG_RD(sc, reg_offset);
4049                 val &= ~AEU_INPUTS_ATTN_BITS_SPIO5;
4050                 REG_WR(sc, reg_offset, val);
4051
4052                 PMD_DRV_LOG(WARNING, sc, "SPIO5 hw attention");
4053
4054 /* Fan failure attention */
4055                 elink_hw_reset_phy(&sc->link_params);
4056                 bnx2x_fan_failure(sc);
4057         }
4058
4059         if ((attn & sc->link_vars.aeu_int_mask) && sc->port.pmf) {
4060                 bnx2x_acquire_phy_lock(sc);
4061                 elink_handle_module_detect_int(&sc->link_params);
4062                 bnx2x_release_phy_lock(sc);
4063         }
4064
4065         if (attn & HW_INTERRUT_ASSERT_SET_0) {
4066                 val = REG_RD(sc, reg_offset);
4067                 val &= ~(attn & HW_INTERRUT_ASSERT_SET_0);
4068                 REG_WR(sc, reg_offset, val);
4069
4070                 rte_panic("FATAL HW block attention set0 0x%lx",
4071                           (attn & HW_INTERRUT_ASSERT_SET_0));
4072         }
4073 }
4074
4075 static void bnx2x_attn_int_deasserted(struct bnx2x_softc *sc, uint32_t deasserted)
4076 {
4077         struct attn_route attn;
4078         struct attn_route *group_mask;
4079         int port = SC_PORT(sc);
4080         int index;
4081         uint32_t reg_addr;
4082         uint32_t val;
4083         uint32_t aeu_mask;
4084         uint8_t global = FALSE;
4085
4086         /*
4087          * Need to take HW lock because MCP or other port might also
4088          * try to handle this event.
4089          */
4090         bnx2x_acquire_alr(sc);
4091
4092         if (bnx2x_chk_parity_attn(sc, &global, TRUE)) {
4093                 sc->recovery_state = BNX2X_RECOVERY_INIT;
4094
4095 /* disable HW interrupts */
4096                 bnx2x_int_disable(sc);
4097                 bnx2x_release_alr(sc);
4098                 return;
4099         }
4100
4101         attn.sig[0] = REG_RD(sc, MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 + port * 4);
4102         attn.sig[1] = REG_RD(sc, MISC_REG_AEU_AFTER_INVERT_2_FUNC_0 + port * 4);
4103         attn.sig[2] = REG_RD(sc, MISC_REG_AEU_AFTER_INVERT_3_FUNC_0 + port * 4);
4104         attn.sig[3] = REG_RD(sc, MISC_REG_AEU_AFTER_INVERT_4_FUNC_0 + port * 4);
4105         if (!CHIP_IS_E1x(sc)) {
4106                 attn.sig[4] =
4107                     REG_RD(sc, MISC_REG_AEU_AFTER_INVERT_5_FUNC_0 + port * 4);
4108         } else {
4109                 attn.sig[4] = 0;
4110         }
4111
4112         for (index = 0; index < MAX_DYNAMIC_ATTN_GRPS; index++) {
4113                 if (deasserted & (1 << index)) {
4114                         group_mask = &sc->attn_group[index];
4115
4116                         bnx2x_attn_int_deasserted4(sc,
4117                                                  attn.
4118                                                  sig[4] & group_mask->sig[4]);
4119                         bnx2x_attn_int_deasserted3(sc,
4120                                                  attn.
4121                                                  sig[3] & group_mask->sig[3]);
4122                         bnx2x_attn_int_deasserted1(sc,
4123                                                  attn.
4124                                                  sig[1] & group_mask->sig[1]);
4125                         bnx2x_attn_int_deasserted2(sc,
4126                                                  attn.
4127                                                  sig[2] & group_mask->sig[2]);
4128                         bnx2x_attn_int_deasserted0(sc,
4129                                                  attn.
4130                                                  sig[0] & group_mask->sig[0]);
4131                 }
4132         }
4133
4134         bnx2x_release_alr(sc);
4135
4136         if (sc->devinfo.int_block == INT_BLOCK_HC) {
4137                 reg_addr = (HC_REG_COMMAND_REG + port * 32 +
4138                             COMMAND_REG_ATTN_BITS_CLR);
4139         } else {
4140                 reg_addr = (BAR_IGU_INTMEM + IGU_CMD_ATTN_BIT_CLR_UPPER * 8);
4141         }
4142
4143         val = ~deasserted;
4144         PMD_DRV_LOG(DEBUG, sc,
4145                     "about to mask 0x%08x at %s addr 0x%08x", val,
4146                     (sc->devinfo.int_block == INT_BLOCK_HC) ? "HC" : "IGU",
4147                     reg_addr);
4148         REG_WR(sc, reg_addr, val);
4149
4150         if (~sc->attn_state & deasserted) {
4151                 PMD_DRV_LOG(ERR, sc, "IGU error");
4152         }
4153
4154         reg_addr = port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 :
4155             MISC_REG_AEU_MASK_ATTN_FUNC_0;
4156
4157         bnx2x_acquire_hw_lock(sc, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
4158
4159         aeu_mask = REG_RD(sc, reg_addr);
4160
4161         aeu_mask |= (deasserted & 0x3ff);
4162
4163         REG_WR(sc, reg_addr, aeu_mask);
4164         bnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
4165
4166         sc->attn_state &= ~deasserted;
4167 }
4168
4169 static void bnx2x_attn_int(struct bnx2x_softc *sc)
4170 {
4171         /* read local copy of bits */
4172         uint32_t attn_bits = le32toh(sc->def_sb->atten_status_block.attn_bits);
4173         uint32_t attn_ack =
4174             le32toh(sc->def_sb->atten_status_block.attn_bits_ack);
4175         uint32_t attn_state = sc->attn_state;
4176
4177         /* look for changed bits */
4178         uint32_t asserted = attn_bits & ~attn_ack & ~attn_state;
4179         uint32_t deasserted = ~attn_bits & attn_ack & attn_state;
4180
4181         PMD_DRV_LOG(DEBUG, sc,
4182                     "attn_bits 0x%08x attn_ack 0x%08x asserted 0x%08x deasserted 0x%08x",
4183                     attn_bits, attn_ack, asserted, deasserted);
4184
4185         if (~(attn_bits ^ attn_ack) & (attn_bits ^ attn_state)) {
4186                 PMD_DRV_LOG(ERR, sc, "BAD attention state");
4187         }
4188
4189         /* handle bits that were raised */
4190         if (asserted) {
4191                 bnx2x_attn_int_asserted(sc, asserted);
4192         }
4193
4194         if (deasserted) {
4195                 bnx2x_attn_int_deasserted(sc, deasserted);
4196         }
4197 }
4198
4199 static uint16_t bnx2x_update_dsb_idx(struct bnx2x_softc *sc)
4200 {
4201         struct host_sp_status_block *def_sb = sc->def_sb;
4202         uint16_t rc = 0;
4203
4204         mb();                   /* status block is written to by the chip */
4205
4206         if (sc->def_att_idx != def_sb->atten_status_block.attn_bits_index) {
4207                 sc->def_att_idx = def_sb->atten_status_block.attn_bits_index;
4208                 rc |= BNX2X_DEF_SB_ATT_IDX;
4209         }
4210
4211         if (sc->def_idx != def_sb->sp_sb.running_index) {
4212                 sc->def_idx = def_sb->sp_sb.running_index;
4213                 rc |= BNX2X_DEF_SB_IDX;
4214         }
4215
4216         mb();
4217
4218         return rc;
4219 }
4220
4221 static struct ecore_queue_sp_obj *bnx2x_cid_to_q_obj(struct bnx2x_softc *sc,
4222                                                           uint32_t cid)
4223 {
4224         return &sc->sp_objs[CID_TO_FP(cid, sc)].q_obj;
4225 }
4226
4227 static void bnx2x_handle_mcast_eqe(struct bnx2x_softc *sc)
4228 {
4229         struct ecore_mcast_ramrod_params rparam;
4230         int rc;
4231
4232         memset(&rparam, 0, sizeof(rparam));
4233
4234         rparam.mcast_obj = &sc->mcast_obj;
4235
4236         /* clear pending state for the last command */
4237         sc->mcast_obj.raw.clear_pending(&sc->mcast_obj.raw);
4238
4239         /* if there are pending mcast commands - send them */
4240         if (sc->mcast_obj.check_pending(&sc->mcast_obj)) {
4241                 rc = ecore_config_mcast(sc, &rparam, ECORE_MCAST_CMD_CONT);
4242                 if (rc < 0) {
4243                         PMD_DRV_LOG(INFO, sc,
4244                                     "Failed to send pending mcast commands (%d)",
4245                                     rc);
4246                 }
4247         }
4248 }
4249
4250 static void
4251 bnx2x_handle_classification_eqe(struct bnx2x_softc *sc, union event_ring_elem *elem)
4252 {
4253         unsigned long ramrod_flags = 0;
4254         int rc = 0;
4255         uint32_t cid = elem->message.data.eth_event.echo & BNX2X_SWCID_MASK;
4256         struct ecore_vlan_mac_obj *vlan_mac_obj;
4257
4258         /* always push next commands out, don't wait here */
4259         bnx2x_set_bit(RAMROD_CONT, &ramrod_flags);
4260
4261         switch (le32toh(elem->message.data.eth_event.echo) >> BNX2X_SWCID_SHIFT) {
4262         case ECORE_FILTER_MAC_PENDING:
4263                 PMD_DRV_LOG(DEBUG, sc, "Got SETUP_MAC completions");
4264                 vlan_mac_obj = &sc->sp_objs[cid].mac_obj;
4265                 break;
4266
4267         case ECORE_FILTER_MCAST_PENDING:
4268                 PMD_DRV_LOG(DEBUG, sc, "Got SETUP_MCAST completions");
4269                 bnx2x_handle_mcast_eqe(sc);
4270                 return;
4271
4272         default:
4273                 PMD_DRV_LOG(NOTICE, sc, "Unsupported classification command: %d",
4274                             elem->message.data.eth_event.echo);
4275                 return;
4276         }
4277
4278         rc = vlan_mac_obj->complete(sc, vlan_mac_obj, elem, &ramrod_flags);
4279
4280         if (rc < 0) {
4281                 PMD_DRV_LOG(NOTICE, sc,
4282                             "Failed to schedule new commands (%d)", rc);
4283         } else if (rc > 0) {
4284                 PMD_DRV_LOG(DEBUG, sc, "Scheduled next pending commands...");
4285         }
4286 }
4287
4288 static void bnx2x_handle_rx_mode_eqe(struct bnx2x_softc *sc)
4289 {
4290         bnx2x_clear_bit(ECORE_FILTER_RX_MODE_PENDING, &sc->sp_state);
4291
4292         /* send rx_mode command again if was requested */
4293         if (bnx2x_test_and_clear_bit(ECORE_FILTER_RX_MODE_SCHED, &sc->sp_state)) {
4294                 bnx2x_set_storm_rx_mode(sc);
4295         }
4296 }
4297
4298 static void bnx2x_update_eq_prod(struct bnx2x_softc *sc, uint16_t prod)
4299 {
4300         storm_memset_eq_prod(sc, prod, SC_FUNC(sc));
4301         wmb();                  /* keep prod updates ordered */
4302 }
4303
4304 static void bnx2x_eq_int(struct bnx2x_softc *sc)
4305 {
4306         uint16_t hw_cons, sw_cons, sw_prod;
4307         union event_ring_elem *elem;
4308         uint8_t echo;
4309         uint32_t cid;
4310         uint8_t opcode;
4311         int spqe_cnt = 0;
4312         struct ecore_queue_sp_obj *q_obj;
4313         struct ecore_func_sp_obj *f_obj = &sc->func_obj;
4314         struct ecore_raw_obj *rss_raw = &sc->rss_conf_obj.raw;
4315
4316         hw_cons = le16toh(*sc->eq_cons_sb);
4317
4318         /*
4319          * The hw_cons range is 1-255, 257 - the sw_cons range is 0-254, 256.
4320          * when we get to the next-page we need to adjust so the loop
4321          * condition below will be met. The next element is the size of a
4322          * regular element and hence incrementing by 1
4323          */
4324         if ((hw_cons & EQ_DESC_MAX_PAGE) == EQ_DESC_MAX_PAGE) {
4325                 hw_cons++;
4326         }
4327
4328         /*
4329          * This function may never run in parallel with itself for a
4330          * specific sc and no need for a read memory barrier here.
4331          */
4332         sw_cons = sc->eq_cons;
4333         sw_prod = sc->eq_prod;
4334
4335         for (;
4336              sw_cons != hw_cons;
4337              sw_prod = NEXT_EQ_IDX(sw_prod), sw_cons = NEXT_EQ_IDX(sw_cons)) {
4338
4339                 elem = &sc->eq[EQ_DESC(sw_cons)];
4340
4341 /* elem CID originates from FW, actually LE */
4342                 cid = SW_CID(elem->message.data.cfc_del_event.cid);
4343                 opcode = elem->message.opcode;
4344
4345 /* handle eq element */
4346                 switch (opcode) {
4347                 case EVENT_RING_OPCODE_STAT_QUERY:
4348                         PMD_DEBUG_PERIODIC_LOG(DEBUG, sc, "got statistics completion event %d",
4349                                     sc->stats_comp++);
4350                         /* nothing to do with stats comp */
4351                         goto next_spqe;
4352
4353                 case EVENT_RING_OPCODE_CFC_DEL:
4354                         /* handle according to cid range */
4355                         /* we may want to verify here that the sc state is HALTING */
4356                         PMD_DRV_LOG(DEBUG, sc, "got delete ramrod for MULTI[%d]",
4357                                     cid);
4358                         q_obj = bnx2x_cid_to_q_obj(sc, cid);
4359                         if (q_obj->complete_cmd(sc, q_obj, ECORE_Q_CMD_CFC_DEL)) {
4360                                 break;
4361                         }
4362                         goto next_spqe;
4363
4364                 case EVENT_RING_OPCODE_STOP_TRAFFIC:
4365                         PMD_DRV_LOG(DEBUG, sc, "got STOP TRAFFIC");
4366                         if (f_obj->complete_cmd(sc, f_obj, ECORE_F_CMD_TX_STOP)) {
4367                                 break;
4368                         }
4369                         goto next_spqe;
4370
4371                 case EVENT_RING_OPCODE_START_TRAFFIC:
4372                         PMD_DRV_LOG(DEBUG, sc, "got START TRAFFIC");
4373                         if (f_obj->complete_cmd
4374                             (sc, f_obj, ECORE_F_CMD_TX_START)) {
4375                                 break;
4376                         }
4377                         goto next_spqe;
4378
4379                 case EVENT_RING_OPCODE_FUNCTION_UPDATE:
4380                         echo = elem->message.data.function_update_event.echo;
4381                         if (echo == SWITCH_UPDATE) {
4382                                 PMD_DRV_LOG(DEBUG, sc,
4383                                             "got FUNC_SWITCH_UPDATE ramrod");
4384                                 if (f_obj->complete_cmd(sc, f_obj,
4385                                                         ECORE_F_CMD_SWITCH_UPDATE))
4386                                 {
4387                                         break;
4388                                 }
4389                         } else {
4390                                 PMD_DRV_LOG(DEBUG, sc,
4391                                             "AFEX: ramrod completed FUNCTION_UPDATE");
4392                                 f_obj->complete_cmd(sc, f_obj,
4393                                                     ECORE_F_CMD_AFEX_UPDATE);
4394                         }
4395                         goto next_spqe;
4396
4397                 case EVENT_RING_OPCODE_FORWARD_SETUP:
4398                         q_obj = &bnx2x_fwd_sp_obj(sc, q_obj);
4399                         if (q_obj->complete_cmd(sc, q_obj,
4400                                                 ECORE_Q_CMD_SETUP_TX_ONLY)) {
4401                                 break;
4402                         }
4403                         goto next_spqe;
4404
4405                 case EVENT_RING_OPCODE_FUNCTION_START:
4406                         PMD_DRV_LOG(DEBUG, sc, "got FUNC_START ramrod");
4407                         if (f_obj->complete_cmd(sc, f_obj, ECORE_F_CMD_START)) {
4408                                 break;
4409                         }
4410                         goto next_spqe;
4411
4412                 case EVENT_RING_OPCODE_FUNCTION_STOP:
4413                         PMD_DRV_LOG(DEBUG, sc, "got FUNC_STOP ramrod");
4414                         if (f_obj->complete_cmd(sc, f_obj, ECORE_F_CMD_STOP)) {
4415                                 break;
4416                         }
4417                         goto next_spqe;
4418                 }
4419
4420                 switch (opcode | sc->state) {
4421                 case (EVENT_RING_OPCODE_RSS_UPDATE_RULES | BNX2X_STATE_OPEN):
4422                 case (EVENT_RING_OPCODE_RSS_UPDATE_RULES | BNX2X_STATE_OPENING_WAITING_PORT):
4423                         cid =
4424                             elem->message.data.eth_event.echo & BNX2X_SWCID_MASK;
4425                         PMD_DRV_LOG(DEBUG, sc, "got RSS_UPDATE ramrod. CID %d",
4426                                     cid);
4427                         rss_raw->clear_pending(rss_raw);
4428                         break;
4429
4430                 case (EVENT_RING_OPCODE_SET_MAC | BNX2X_STATE_OPEN):
4431                 case (EVENT_RING_OPCODE_SET_MAC | BNX2X_STATE_DIAG):
4432                 case (EVENT_RING_OPCODE_SET_MAC | BNX2X_STATE_CLOSING_WAITING_HALT):
4433                 case (EVENT_RING_OPCODE_CLASSIFICATION_RULES | BNX2X_STATE_OPEN):
4434                 case (EVENT_RING_OPCODE_CLASSIFICATION_RULES | BNX2X_STATE_DIAG):
4435                 case (EVENT_RING_OPCODE_CLASSIFICATION_RULES | BNX2X_STATE_CLOSING_WAITING_HALT):
4436                         PMD_DRV_LOG(DEBUG, sc,
4437                                     "got (un)set mac ramrod");
4438                         bnx2x_handle_classification_eqe(sc, elem);
4439                         break;
4440
4441                 case (EVENT_RING_OPCODE_MULTICAST_RULES | BNX2X_STATE_OPEN):
4442                 case (EVENT_RING_OPCODE_MULTICAST_RULES | BNX2X_STATE_DIAG):
4443                 case (EVENT_RING_OPCODE_MULTICAST_RULES | BNX2X_STATE_CLOSING_WAITING_HALT):
4444                         PMD_DRV_LOG(DEBUG, sc,
4445                                     "got mcast ramrod");
4446                         bnx2x_handle_mcast_eqe(sc);
4447                         break;
4448
4449                 case (EVENT_RING_OPCODE_FILTERS_RULES | BNX2X_STATE_OPEN):
4450                 case (EVENT_RING_OPCODE_FILTERS_RULES | BNX2X_STATE_DIAG):
4451                 case (EVENT_RING_OPCODE_FILTERS_RULES | BNX2X_STATE_CLOSING_WAITING_HALT):
4452                         PMD_DRV_LOG(DEBUG, sc,
4453                                     "got rx_mode ramrod");
4454                         bnx2x_handle_rx_mode_eqe(sc);
4455                         break;
4456
4457                 default:
4458                         /* unknown event log error and continue */
4459                         PMD_DRV_LOG(INFO, sc, "Unknown EQ event %d, sc->state 0x%x",
4460                                     elem->message.opcode, sc->state);
4461                 }
4462
4463 next_spqe:
4464                 spqe_cnt++;
4465         }                       /* for */
4466
4467         mb();
4468         atomic_add_acq_long(&sc->eq_spq_left, spqe_cnt);
4469
4470         sc->eq_cons = sw_cons;
4471         sc->eq_prod = sw_prod;
4472
4473         /* make sure that above mem writes were issued towards the memory */
4474         wmb();
4475
4476         /* update producer */
4477         bnx2x_update_eq_prod(sc, sc->eq_prod);
4478 }
4479
4480 static int bnx2x_handle_sp_tq(struct bnx2x_softc *sc)
4481 {
4482         uint16_t status;
4483         int rc = 0;
4484
4485         PMD_DRV_LOG(DEBUG, sc, "---> SP TASK <---");
4486
4487         /* what work needs to be performed? */
4488         status = bnx2x_update_dsb_idx(sc);
4489
4490         PMD_DRV_LOG(DEBUG, sc, "dsb status 0x%04x", status);
4491
4492         /* HW attentions */
4493         if (status & BNX2X_DEF_SB_ATT_IDX) {
4494                 PMD_DRV_LOG(DEBUG, sc, "---> ATTN INTR <---");
4495                 bnx2x_attn_int(sc);
4496                 status &= ~BNX2X_DEF_SB_ATT_IDX;
4497                 rc = 1;
4498         }
4499
4500         /* SP events: STAT_QUERY and others */
4501         if (status & BNX2X_DEF_SB_IDX) {
4502 /* handle EQ completions */
4503                 PMD_DRV_LOG(DEBUG, sc, "---> EQ INTR <---");
4504                 bnx2x_eq_int(sc);
4505                 bnx2x_ack_sb(sc, sc->igu_dsb_id, USTORM_ID,
4506                            le16toh(sc->def_idx), IGU_INT_NOP, 1);
4507                 status &= ~BNX2X_DEF_SB_IDX;
4508         }
4509
4510         /* if status is non zero then something went wrong */
4511         if (unlikely(status)) {
4512                 PMD_DRV_LOG(INFO, sc,
4513                             "Got an unknown SP interrupt! (0x%04x)", status);
4514         }
4515
4516         /* ack status block only if something was actually handled */
4517         bnx2x_ack_sb(sc, sc->igu_dsb_id, ATTENTION_ID,
4518                    le16toh(sc->def_att_idx), IGU_INT_ENABLE, 1);
4519
4520         return rc;
4521 }
4522
4523 static void bnx2x_handle_fp_tq(struct bnx2x_fastpath *fp, int scan_fp)
4524 {
4525         struct bnx2x_softc *sc = fp->sc;
4526         uint8_t more_rx = FALSE;
4527
4528         PMD_DEBUG_PERIODIC_LOG(DEBUG, sc,
4529                                "---> FP TASK QUEUE (%d) <--", fp->index);
4530
4531         /* update the fastpath index */
4532         bnx2x_update_fp_sb_idx(fp);
4533
4534         if (scan_fp) {
4535                 if (bnx2x_has_rx_work(fp)) {
4536                         more_rx = bnx2x_rxeof(sc, fp);
4537                 }
4538
4539                 if (more_rx) {
4540                         /* still more work to do */
4541                         bnx2x_handle_fp_tq(fp, scan_fp);
4542                         return;
4543                 }
4544         }
4545
4546         bnx2x_ack_sb(sc, fp->igu_sb_id, USTORM_ID,
4547                    le16toh(fp->fp_hc_idx), IGU_INT_ENABLE, 1);
4548 }
4549
4550 /*
4551  * Legacy interrupt entry point.
4552  *
4553  * Verifies that the controller generated the interrupt and
4554  * then calls a separate routine to handle the various
4555  * interrupt causes: link, RX, and TX.
4556  */
4557 int bnx2x_intr_legacy(struct bnx2x_softc *sc, int scan_fp)
4558 {
4559         struct bnx2x_fastpath *fp;
4560         uint32_t status, mask;
4561         int i, rc = 0;
4562
4563         /*
4564          * 0 for ustorm, 1 for cstorm
4565          * the bits returned from ack_int() are 0-15
4566          * bit 0 = attention status block
4567          * bit 1 = fast path status block
4568          * a mask of 0x2 or more = tx/rx event
4569          * a mask of 1 = slow path event
4570          */
4571
4572         status = bnx2x_ack_int(sc);
4573
4574         /* the interrupt is not for us */
4575         if (unlikely(status == 0)) {
4576                 return 0;
4577         }
4578
4579         PMD_DEBUG_PERIODIC_LOG(DEBUG, sc, "Interrupt status 0x%04x", status);
4580         //bnx2x_dump_status_block(sc);
4581
4582         FOR_EACH_ETH_QUEUE(sc, i) {
4583                 fp = &sc->fp[i];
4584                 mask = (0x2 << (fp->index + CNIC_SUPPORT(sc)));
4585                 if (status & mask) {
4586                 /* acknowledge and disable further fastpath interrupts */
4587                         bnx2x_ack_sb(sc, fp->igu_sb_id, USTORM_ID,
4588                                      0, IGU_INT_DISABLE, 0);
4589                         bnx2x_handle_fp_tq(fp, scan_fp);
4590                         status &= ~mask;
4591                 }
4592         }
4593
4594         if (unlikely(status & 0x1)) {
4595                 /* acknowledge and disable further slowpath interrupts */
4596                 bnx2x_ack_sb(sc, sc->igu_dsb_id, USTORM_ID,
4597                              0, IGU_INT_DISABLE, 0);
4598                 rc = bnx2x_handle_sp_tq(sc);
4599                 status &= ~0x1;
4600         }
4601
4602         if (unlikely(status)) {
4603                 PMD_DRV_LOG(WARNING, sc,
4604                             "Unexpected fastpath status (0x%08x)!", status);
4605         }
4606
4607         return rc;
4608 }
4609
4610 static int bnx2x_init_hw_common_chip(struct bnx2x_softc *sc);
4611 static int bnx2x_init_hw_common(struct bnx2x_softc *sc);
4612 static int bnx2x_init_hw_port(struct bnx2x_softc *sc);
4613 static int bnx2x_init_hw_func(struct bnx2x_softc *sc);
4614 static void bnx2x_reset_common(struct bnx2x_softc *sc);
4615 static void bnx2x_reset_port(struct bnx2x_softc *sc);
4616 static void bnx2x_reset_func(struct bnx2x_softc *sc);
4617 static int bnx2x_init_firmware(struct bnx2x_softc *sc);
4618 static void bnx2x_release_firmware(struct bnx2x_softc *sc);
4619
4620 static struct
4621 ecore_func_sp_drv_ops bnx2x_func_sp_drv = {
4622         .init_hw_cmn_chip = bnx2x_init_hw_common_chip,
4623         .init_hw_cmn = bnx2x_init_hw_common,
4624         .init_hw_port = bnx2x_init_hw_port,
4625         .init_hw_func = bnx2x_init_hw_func,
4626
4627         .reset_hw_cmn = bnx2x_reset_common,
4628         .reset_hw_port = bnx2x_reset_port,
4629         .reset_hw_func = bnx2x_reset_func,
4630
4631         .init_fw = bnx2x_init_firmware,
4632         .release_fw = bnx2x_release_firmware,
4633 };
4634
4635 static void bnx2x_init_func_obj(struct bnx2x_softc *sc)
4636 {
4637         sc->dmae_ready = 0;
4638
4639         PMD_INIT_FUNC_TRACE(sc);
4640
4641         ecore_init_func_obj(sc,
4642                             &sc->func_obj,
4643                             BNX2X_SP(sc, func_rdata),
4644                             (rte_iova_t)BNX2X_SP_MAPPING(sc, func_rdata),
4645                             BNX2X_SP(sc, func_afex_rdata),
4646                             (rte_iova_t)BNX2X_SP_MAPPING(sc, func_afex_rdata),
4647                             &bnx2x_func_sp_drv);
4648 }
4649
4650 static int bnx2x_init_hw(struct bnx2x_softc *sc, uint32_t load_code)
4651 {
4652         struct ecore_func_state_params func_params = { NULL };
4653         int rc;
4654
4655         PMD_INIT_FUNC_TRACE(sc);
4656
4657         /* prepare the parameters for function state transitions */
4658         bnx2x_set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags);
4659
4660         func_params.f_obj = &sc->func_obj;
4661         func_params.cmd = ECORE_F_CMD_HW_INIT;
4662
4663         func_params.params.hw_init.load_phase = load_code;
4664
4665         /*
4666          * Via a plethora of function pointers, we will eventually reach
4667          * bnx2x_init_hw_common(), bnx2x_init_hw_port(), or bnx2x_init_hw_func().
4668          */
4669         rc = ecore_func_state_change(sc, &func_params);
4670
4671         return rc;
4672 }
4673
4674 static void
4675 bnx2x_fill(struct bnx2x_softc *sc, uint32_t addr, int fill, uint32_t len)
4676 {
4677         uint32_t i;
4678
4679         if (!(len % 4) && !(addr % 4)) {
4680                 for (i = 0; i < len; i += 4) {
4681                         REG_WR(sc, (addr + i), fill);
4682                 }
4683         } else {
4684                 for (i = 0; i < len; i++) {
4685                         REG_WR8(sc, (addr + i), fill);
4686                 }
4687         }
4688 }
4689
4690 /* writes FP SP data to FW - data_size in dwords */
4691 static void
4692 bnx2x_wr_fp_sb_data(struct bnx2x_softc *sc, int fw_sb_id, uint32_t * sb_data_p,
4693                   uint32_t data_size)
4694 {
4695         uint32_t index;
4696
4697         for (index = 0; index < data_size; index++) {
4698                 REG_WR(sc,
4699                        (BAR_CSTRORM_INTMEM +
4700                         CSTORM_STATUS_BLOCK_DATA_OFFSET(fw_sb_id) +
4701                         (sizeof(uint32_t) * index)), *(sb_data_p + index));
4702         }
4703 }
4704
4705 static void bnx2x_zero_fp_sb(struct bnx2x_softc *sc, int fw_sb_id)
4706 {
4707         struct hc_status_block_data_e2 sb_data_e2;
4708         struct hc_status_block_data_e1x sb_data_e1x;
4709         uint32_t *sb_data_p;
4710         uint32_t data_size = 0;
4711
4712         if (!CHIP_IS_E1x(sc)) {
4713                 memset(&sb_data_e2, 0, sizeof(struct hc_status_block_data_e2));
4714                 sb_data_e2.common.state = SB_DISABLED;
4715                 sb_data_e2.common.p_func.vf_valid = FALSE;
4716                 sb_data_p = (uint32_t *) & sb_data_e2;
4717                 data_size = (sizeof(struct hc_status_block_data_e2) /
4718                              sizeof(uint32_t));
4719         } else {
4720                 memset(&sb_data_e1x, 0,
4721                        sizeof(struct hc_status_block_data_e1x));
4722                 sb_data_e1x.common.state = SB_DISABLED;
4723                 sb_data_e1x.common.p_func.vf_valid = FALSE;
4724                 sb_data_p = (uint32_t *) & sb_data_e1x;
4725                 data_size = (sizeof(struct hc_status_block_data_e1x) /
4726                              sizeof(uint32_t));
4727         }
4728
4729         bnx2x_wr_fp_sb_data(sc, fw_sb_id, sb_data_p, data_size);
4730
4731         bnx2x_fill(sc,
4732                  (BAR_CSTRORM_INTMEM + CSTORM_STATUS_BLOCK_OFFSET(fw_sb_id)), 0,
4733                  CSTORM_STATUS_BLOCK_SIZE);
4734         bnx2x_fill(sc, (BAR_CSTRORM_INTMEM + CSTORM_SYNC_BLOCK_OFFSET(fw_sb_id)),
4735                  0, CSTORM_SYNC_BLOCK_SIZE);
4736 }
4737
4738 static void
4739 bnx2x_wr_sp_sb_data(struct bnx2x_softc *sc,
4740                   struct hc_sp_status_block_data *sp_sb_data)
4741 {
4742         uint32_t i;
4743
4744         for (i = 0;
4745              i < (sizeof(struct hc_sp_status_block_data) / sizeof(uint32_t));
4746              i++) {
4747                 REG_WR(sc,
4748                        (BAR_CSTRORM_INTMEM +
4749                         CSTORM_SP_STATUS_BLOCK_DATA_OFFSET(SC_FUNC(sc)) +
4750                         (i * sizeof(uint32_t))),
4751                        *((uint32_t *) sp_sb_data + i));
4752         }
4753 }
4754
4755 static void bnx2x_zero_sp_sb(struct bnx2x_softc *sc)
4756 {
4757         struct hc_sp_status_block_data sp_sb_data;
4758
4759         memset(&sp_sb_data, 0, sizeof(struct hc_sp_status_block_data));
4760
4761         sp_sb_data.state = SB_DISABLED;
4762         sp_sb_data.p_func.vf_valid = FALSE;
4763
4764         bnx2x_wr_sp_sb_data(sc, &sp_sb_data);
4765
4766         bnx2x_fill(sc,
4767                  (BAR_CSTRORM_INTMEM +
4768                   CSTORM_SP_STATUS_BLOCK_OFFSET(SC_FUNC(sc))),
4769                  0, CSTORM_SP_STATUS_BLOCK_SIZE);
4770         bnx2x_fill(sc,
4771                  (BAR_CSTRORM_INTMEM +
4772                   CSTORM_SP_SYNC_BLOCK_OFFSET(SC_FUNC(sc))),
4773                  0, CSTORM_SP_SYNC_BLOCK_SIZE);
4774 }
4775
4776 static void
4777 bnx2x_setup_ndsb_state_machine(struct hc_status_block_sm *hc_sm, int igu_sb_id,
4778                              int igu_seg_id)
4779 {
4780         hc_sm->igu_sb_id = igu_sb_id;
4781         hc_sm->igu_seg_id = igu_seg_id;
4782         hc_sm->timer_value = 0xFF;
4783         hc_sm->time_to_expire = 0xFFFFFFFF;
4784 }
4785
4786 static void bnx2x_map_sb_state_machines(struct hc_index_data *index_data)
4787 {
4788         /* zero out state machine indices */
4789
4790         /* rx indices */
4791         index_data[HC_INDEX_ETH_RX_CQ_CONS].flags &= ~HC_INDEX_DATA_SM_ID;
4792
4793         /* tx indices */
4794         index_data[HC_INDEX_OOO_TX_CQ_CONS].flags &= ~HC_INDEX_DATA_SM_ID;
4795         index_data[HC_INDEX_ETH_TX_CQ_CONS_COS0].flags &= ~HC_INDEX_DATA_SM_ID;
4796         index_data[HC_INDEX_ETH_TX_CQ_CONS_COS1].flags &= ~HC_INDEX_DATA_SM_ID;
4797         index_data[HC_INDEX_ETH_TX_CQ_CONS_COS2].flags &= ~HC_INDEX_DATA_SM_ID;
4798
4799         /* map indices */
4800
4801         /* rx indices */
4802         index_data[HC_INDEX_ETH_RX_CQ_CONS].flags |=
4803             (SM_RX_ID << HC_INDEX_DATA_SM_ID_SHIFT);
4804
4805         /* tx indices */
4806         index_data[HC_INDEX_OOO_TX_CQ_CONS].flags |=
4807             (SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT);
4808         index_data[HC_INDEX_ETH_TX_CQ_CONS_COS0].flags |=
4809             (SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT);
4810         index_data[HC_INDEX_ETH_TX_CQ_CONS_COS1].flags |=
4811             (SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT);
4812         index_data[HC_INDEX_ETH_TX_CQ_CONS_COS2].flags |=
4813             (SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT);
4814 }
4815
4816 static void
4817 bnx2x_init_sb(struct bnx2x_softc *sc, rte_iova_t busaddr, int vfid,
4818             uint8_t vf_valid, int fw_sb_id, int igu_sb_id)
4819 {
4820         struct hc_status_block_data_e2 sb_data_e2;
4821         struct hc_status_block_data_e1x sb_data_e1x;
4822         struct hc_status_block_sm *hc_sm_p;
4823         uint32_t *sb_data_p;
4824         int igu_seg_id;
4825         int data_size;
4826
4827         if (CHIP_INT_MODE_IS_BC(sc)) {
4828                 igu_seg_id = HC_SEG_ACCESS_NORM;
4829         } else {
4830                 igu_seg_id = IGU_SEG_ACCESS_NORM;
4831         }
4832
4833         bnx2x_zero_fp_sb(sc, fw_sb_id);
4834
4835         if (!CHIP_IS_E1x(sc)) {
4836                 memset(&sb_data_e2, 0, sizeof(struct hc_status_block_data_e2));
4837                 sb_data_e2.common.state = SB_ENABLED;
4838                 sb_data_e2.common.p_func.pf_id = SC_FUNC(sc);
4839                 sb_data_e2.common.p_func.vf_id = vfid;
4840                 sb_data_e2.common.p_func.vf_valid = vf_valid;
4841                 sb_data_e2.common.p_func.vnic_id = SC_VN(sc);
4842                 sb_data_e2.common.same_igu_sb_1b = TRUE;
4843                 sb_data_e2.common.host_sb_addr.hi = U64_HI(busaddr);
4844                 sb_data_e2.common.host_sb_addr.lo = U64_LO(busaddr);
4845                 hc_sm_p = sb_data_e2.common.state_machine;
4846                 sb_data_p = (uint32_t *) & sb_data_e2;
4847                 data_size = (sizeof(struct hc_status_block_data_e2) /
4848                              sizeof(uint32_t));
4849                 bnx2x_map_sb_state_machines(sb_data_e2.index_data);
4850         } else {
4851                 memset(&sb_data_e1x, 0,
4852                        sizeof(struct hc_status_block_data_e1x));
4853                 sb_data_e1x.common.state = SB_ENABLED;
4854                 sb_data_e1x.common.p_func.pf_id = SC_FUNC(sc);
4855                 sb_data_e1x.common.p_func.vf_id = 0xff;
4856                 sb_data_e1x.common.p_func.vf_valid = FALSE;
4857                 sb_data_e1x.common.p_func.vnic_id = SC_VN(sc);
4858                 sb_data_e1x.common.same_igu_sb_1b = TRUE;
4859                 sb_data_e1x.common.host_sb_addr.hi = U64_HI(busaddr);
4860                 sb_data_e1x.common.host_sb_addr.lo = U64_LO(busaddr);
4861                 hc_sm_p = sb_data_e1x.common.state_machine;
4862                 sb_data_p = (uint32_t *) & sb_data_e1x;
4863                 data_size = (sizeof(struct hc_status_block_data_e1x) /
4864                              sizeof(uint32_t));
4865                 bnx2x_map_sb_state_machines(sb_data_e1x.index_data);
4866         }
4867
4868         bnx2x_setup_ndsb_state_machine(&hc_sm_p[SM_RX_ID], igu_sb_id, igu_seg_id);
4869         bnx2x_setup_ndsb_state_machine(&hc_sm_p[SM_TX_ID], igu_sb_id, igu_seg_id);
4870
4871         /* write indices to HW - PCI guarantees endianity of regpairs */
4872         bnx2x_wr_fp_sb_data(sc, fw_sb_id, sb_data_p, data_size);
4873 }
4874
4875 static uint8_t bnx2x_fp_qzone_id(struct bnx2x_fastpath *fp)
4876 {
4877         if (CHIP_IS_E1x(fp->sc)) {
4878                 return fp->cl_id + SC_PORT(fp->sc) * ETH_MAX_RX_CLIENTS_E1H;
4879         } else {
4880                 return fp->cl_id;
4881         }
4882 }
4883
4884 static uint32_t
4885 bnx2x_rx_ustorm_prods_offset(struct bnx2x_softc *sc, struct bnx2x_fastpath *fp)
4886 {
4887         uint32_t offset = BAR_USTRORM_INTMEM;
4888
4889         if (IS_VF(sc)) {
4890                 return PXP_VF_ADDR_USDM_QUEUES_START +
4891                         (sc->acquire_resp.resc.hw_qid[fp->index] *
4892                          sizeof(struct ustorm_queue_zone_data));
4893         } else if (!CHIP_IS_E1x(sc)) {
4894                 offset += USTORM_RX_PRODS_E2_OFFSET(fp->cl_qzone_id);
4895         } else {
4896                 offset += USTORM_RX_PRODS_E1X_OFFSET(SC_PORT(sc), fp->cl_id);
4897         }
4898
4899         return offset;
4900 }
4901
4902 static void bnx2x_init_eth_fp(struct bnx2x_softc *sc, int idx)
4903 {
4904         struct bnx2x_fastpath *fp = &sc->fp[idx];
4905         uint32_t cids[ECORE_MULTI_TX_COS] = { 0 };
4906         unsigned long q_type = 0;
4907         int cos;
4908
4909         fp->sc = sc;
4910         fp->index = idx;
4911
4912         fp->igu_sb_id = (sc->igu_base_sb + idx + CNIC_SUPPORT(sc));
4913         fp->fw_sb_id = (sc->base_fw_ndsb + idx + CNIC_SUPPORT(sc));
4914
4915         if (CHIP_IS_E1x(sc))
4916                 fp->cl_id = SC_L_ID(sc) + idx;
4917         else
4918 /* want client ID same as IGU SB ID for non-E1 */
4919                 fp->cl_id = fp->igu_sb_id;
4920         fp->cl_qzone_id = bnx2x_fp_qzone_id(fp);
4921
4922         /* setup sb indices */
4923         if (!CHIP_IS_E1x(sc)) {
4924                 fp->sb_index_values = fp->status_block.e2_sb->sb.index_values;
4925                 fp->sb_running_index = fp->status_block.e2_sb->sb.running_index;
4926         } else {
4927                 fp->sb_index_values = fp->status_block.e1x_sb->sb.index_values;
4928                 fp->sb_running_index =
4929                     fp->status_block.e1x_sb->sb.running_index;
4930         }
4931
4932         /* init shortcut */
4933         fp->ustorm_rx_prods_offset = bnx2x_rx_ustorm_prods_offset(sc, fp);
4934
4935         fp->rx_cq_cons_sb = &fp->sb_index_values[HC_INDEX_ETH_RX_CQ_CONS];
4936
4937         for (cos = 0; cos < sc->max_cos; cos++) {
4938                 cids[cos] = idx;
4939         }
4940         fp->tx_cons_sb = &fp->sb_index_values[HC_INDEX_ETH_TX_CQ_CONS_COS0];
4941
4942         /* nothing more for a VF to do */
4943         if (IS_VF(sc)) {
4944                 return;
4945         }
4946
4947         bnx2x_init_sb(sc, fp->sb_dma.paddr, BNX2X_VF_ID_INVALID, FALSE,
4948                     fp->fw_sb_id, fp->igu_sb_id);
4949
4950         bnx2x_update_fp_sb_idx(fp);
4951
4952         /* Configure Queue State object */
4953         bnx2x_set_bit(ECORE_Q_TYPE_HAS_RX, &q_type);
4954         bnx2x_set_bit(ECORE_Q_TYPE_HAS_TX, &q_type);
4955
4956         ecore_init_queue_obj(sc,
4957                              &sc->sp_objs[idx].q_obj,
4958                              fp->cl_id,
4959                              cids,
4960                              sc->max_cos,
4961                              SC_FUNC(sc),
4962                              BNX2X_SP(sc, q_rdata),
4963                              (rte_iova_t)BNX2X_SP_MAPPING(sc, q_rdata),
4964                              q_type);
4965
4966         /* configure classification DBs */
4967         ecore_init_mac_obj(sc,
4968                            &sc->sp_objs[idx].mac_obj,
4969                            fp->cl_id,
4970                            idx,
4971                            SC_FUNC(sc),
4972                            BNX2X_SP(sc, mac_rdata),
4973                            (rte_iova_t)BNX2X_SP_MAPPING(sc, mac_rdata),
4974                            ECORE_FILTER_MAC_PENDING, &sc->sp_state,
4975                            ECORE_OBJ_TYPE_RX_TX, &sc->macs_pool);
4976 }
4977
4978 static void
4979 bnx2x_update_rx_prod(struct bnx2x_softc *sc, struct bnx2x_fastpath *fp,
4980                    uint16_t rx_bd_prod, uint16_t rx_cq_prod)
4981 {
4982         union ustorm_eth_rx_producers rx_prods;
4983         uint32_t i;
4984
4985         /* update producers */
4986         rx_prods.prod.bd_prod = rx_bd_prod;
4987         rx_prods.prod.cqe_prod = rx_cq_prod;
4988         rx_prods.prod.reserved = 0;
4989
4990         /*
4991          * Make sure that the BD and SGE data is updated before updating the
4992          * producers since FW might read the BD/SGE right after the producer
4993          * is updated.
4994          * This is only applicable for weak-ordered memory model archs such
4995          * as IA-64. The following barrier is also mandatory since FW will
4996          * assumes BDs must have buffers.
4997          */
4998         wmb();
4999
5000         for (i = 0; i < (sizeof(rx_prods) / 4); i++) {
5001                 REG_WR(sc,
5002                        (fp->ustorm_rx_prods_offset + (i * 4)),
5003                        rx_prods.raw_data[i]);
5004         }
5005
5006         wmb();                  /* keep prod updates ordered */
5007 }
5008
5009 static void bnx2x_init_rx_rings(struct bnx2x_softc *sc)
5010 {
5011         struct bnx2x_fastpath *fp;
5012         int i;
5013         struct bnx2x_rx_queue *rxq;
5014
5015         for (i = 0; i < sc->num_queues; i++) {
5016                 fp = &sc->fp[i];
5017                 rxq = sc->rx_queues[fp->index];
5018                 if (!rxq) {
5019                         PMD_RX_LOG(ERR, "RX queue is NULL");
5020                         return;
5021                 }
5022
5023                 rxq->rx_bd_head = 0;
5024                 rxq->rx_bd_tail = rxq->nb_rx_desc;
5025                 rxq->rx_cq_head = 0;
5026                 rxq->rx_cq_tail = TOTAL_RCQ_ENTRIES(rxq);
5027                 *fp->rx_cq_cons_sb = 0;
5028
5029                 /*
5030                  * Activate the BD ring...
5031                  * Warning, this will generate an interrupt (to the TSTORM)
5032                  * so this can only be done after the chip is initialized
5033                  */
5034                 bnx2x_update_rx_prod(sc, fp, rxq->rx_bd_tail, rxq->rx_cq_tail);
5035
5036                 if (i != 0) {
5037                         continue;
5038                 }
5039         }
5040 }
5041
5042 static void bnx2x_init_tx_ring_one(struct bnx2x_fastpath *fp)
5043 {
5044         struct bnx2x_tx_queue *txq = fp->sc->tx_queues[fp->index];
5045
5046         fp->tx_db.data.header.header = 1 << DOORBELL_HDR_DB_TYPE_SHIFT;
5047         fp->tx_db.data.zero_fill1 = 0;
5048         fp->tx_db.data.prod = 0;
5049
5050         if (!txq) {
5051                 PMD_TX_LOG(ERR, "ERROR: TX queue is NULL");
5052                 return;
5053         }
5054
5055         txq->tx_pkt_tail = 0;
5056         txq->tx_pkt_head = 0;
5057         txq->tx_bd_tail = 0;
5058         txq->tx_bd_head = 0;
5059 }
5060
5061 static void bnx2x_init_tx_rings(struct bnx2x_softc *sc)
5062 {
5063         int i;
5064
5065         for (i = 0; i < sc->num_queues; i++) {
5066                 bnx2x_init_tx_ring_one(&sc->fp[i]);
5067         }
5068 }
5069
5070 static void bnx2x_init_def_sb(struct bnx2x_softc *sc)
5071 {
5072         struct host_sp_status_block *def_sb = sc->def_sb;
5073         rte_iova_t mapping = sc->def_sb_dma.paddr;
5074         int igu_sp_sb_index;
5075         int igu_seg_id;
5076         int port = SC_PORT(sc);
5077         int func = SC_FUNC(sc);
5078         int reg_offset, reg_offset_en5;
5079         uint64_t section;
5080         int index, sindex;
5081         struct hc_sp_status_block_data sp_sb_data;
5082
5083         memset(&sp_sb_data, 0, sizeof(struct hc_sp_status_block_data));
5084
5085         if (CHIP_INT_MODE_IS_BC(sc)) {
5086                 igu_sp_sb_index = DEF_SB_IGU_ID;
5087                 igu_seg_id = HC_SEG_ACCESS_DEF;
5088         } else {
5089                 igu_sp_sb_index = sc->igu_dsb_id;
5090                 igu_seg_id = IGU_SEG_ACCESS_DEF;
5091         }
5092
5093         /* attentions */
5094         section = ((uint64_t) mapping +
5095                    offsetof(struct host_sp_status_block, atten_status_block));
5096         def_sb->atten_status_block.status_block_id = igu_sp_sb_index;
5097         sc->attn_state = 0;
5098
5099         reg_offset = (port) ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 :
5100             MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0;
5101
5102         reg_offset_en5 = (port) ? MISC_REG_AEU_ENABLE5_FUNC_1_OUT_0 :
5103             MISC_REG_AEU_ENABLE5_FUNC_0_OUT_0;
5104
5105         for (index = 0; index < MAX_DYNAMIC_ATTN_GRPS; index++) {
5106 /* take care of sig[0]..sig[4] */
5107                 for (sindex = 0; sindex < 4; sindex++) {
5108                         sc->attn_group[index].sig[sindex] =
5109                             REG_RD(sc,
5110                                    (reg_offset + (sindex * 0x4) +
5111                                     (0x10 * index)));
5112                 }
5113
5114                 if (!CHIP_IS_E1x(sc)) {
5115                         /*
5116                          * enable5 is separate from the rest of the registers,
5117                          * and the address skip is 4 and not 16 between the
5118                          * different groups
5119                          */
5120                         sc->attn_group[index].sig[4] =
5121                             REG_RD(sc, (reg_offset_en5 + (0x4 * index)));
5122                 } else {
5123                         sc->attn_group[index].sig[4] = 0;
5124                 }
5125         }
5126
5127         if (sc->devinfo.int_block == INT_BLOCK_HC) {
5128                 reg_offset =
5129                     port ? HC_REG_ATTN_MSG1_ADDR_L : HC_REG_ATTN_MSG0_ADDR_L;
5130                 REG_WR(sc, reg_offset, U64_LO(section));
5131                 REG_WR(sc, (reg_offset + 4), U64_HI(section));
5132         } else if (!CHIP_IS_E1x(sc)) {
5133                 REG_WR(sc, IGU_REG_ATTN_MSG_ADDR_L, U64_LO(section));
5134                 REG_WR(sc, IGU_REG_ATTN_MSG_ADDR_H, U64_HI(section));
5135         }
5136
5137         section = ((uint64_t) mapping +
5138                    offsetof(struct host_sp_status_block, sp_sb));
5139
5140         bnx2x_zero_sp_sb(sc);
5141
5142         /* PCI guarantees endianity of regpair */
5143         sp_sb_data.state = SB_ENABLED;
5144         sp_sb_data.host_sb_addr.lo = U64_LO(section);
5145         sp_sb_data.host_sb_addr.hi = U64_HI(section);
5146         sp_sb_data.igu_sb_id = igu_sp_sb_index;
5147         sp_sb_data.igu_seg_id = igu_seg_id;
5148         sp_sb_data.p_func.pf_id = func;
5149         sp_sb_data.p_func.vnic_id = SC_VN(sc);
5150         sp_sb_data.p_func.vf_id = 0xff;
5151
5152         bnx2x_wr_sp_sb_data(sc, &sp_sb_data);
5153
5154         bnx2x_ack_sb(sc, sc->igu_dsb_id, USTORM_ID, 0, IGU_INT_ENABLE, 0);
5155 }
5156
5157 static void bnx2x_init_sp_ring(struct bnx2x_softc *sc)
5158 {
5159         atomic_store_rel_long(&sc->cq_spq_left, MAX_SPQ_PENDING);
5160         sc->spq_prod_idx = 0;
5161         sc->dsb_sp_prod =
5162             &sc->def_sb->sp_sb.index_values[HC_SP_INDEX_ETH_DEF_CONS];
5163         sc->spq_prod_bd = sc->spq;
5164         sc->spq_last_bd = (sc->spq_prod_bd + MAX_SP_DESC_CNT);
5165 }
5166
5167 static void bnx2x_init_eq_ring(struct bnx2x_softc *sc)
5168 {
5169         union event_ring_elem *elem;
5170         int i;
5171
5172         for (i = 1; i <= NUM_EQ_PAGES; i++) {
5173                 elem = &sc->eq[EQ_DESC_CNT_PAGE * i - 1];
5174
5175                 elem->next_page.addr.hi = htole32(U64_HI(sc->eq_dma.paddr +
5176                                                          BNX2X_PAGE_SIZE *
5177                                                          (i % NUM_EQ_PAGES)));
5178                 elem->next_page.addr.lo = htole32(U64_LO(sc->eq_dma.paddr +
5179                                                          BNX2X_PAGE_SIZE *
5180                                                          (i % NUM_EQ_PAGES)));
5181         }
5182
5183         sc->eq_cons = 0;
5184         sc->eq_prod = NUM_EQ_DESC;
5185         sc->eq_cons_sb = &sc->def_sb->sp_sb.index_values[HC_SP_INDEX_EQ_CONS];
5186
5187         atomic_store_rel_long(&sc->eq_spq_left,
5188                               (min((MAX_SP_DESC_CNT - MAX_SPQ_PENDING),
5189                                    NUM_EQ_DESC) - 1));
5190 }
5191
5192 static void bnx2x_init_internal_common(struct bnx2x_softc *sc)
5193 {
5194         int i;
5195
5196         if (IS_MF_SI(sc)) {
5197 /*
5198  * In switch independent mode, the TSTORM needs to accept
5199  * packets that failed classification, since approximate match
5200  * mac addresses aren't written to NIG LLH.
5201  */
5202                 REG_WR8(sc,
5203                         (BAR_TSTRORM_INTMEM +
5204                          TSTORM_ACCEPT_CLASSIFY_FAILED_OFFSET), 2);
5205         } else
5206                 REG_WR8(sc,
5207                         (BAR_TSTRORM_INTMEM +
5208                          TSTORM_ACCEPT_CLASSIFY_FAILED_OFFSET), 0);
5209
5210         /*
5211          * Zero this manually as its initialization is currently missing
5212          * in the initTool.
5213          */
5214         for (i = 0; i < (USTORM_AGG_DATA_SIZE >> 2); i++) {
5215                 REG_WR(sc,
5216                        (BAR_USTRORM_INTMEM + USTORM_AGG_DATA_OFFSET + (i * 4)),
5217                        0);
5218         }
5219
5220         if (!CHIP_IS_E1x(sc)) {
5221                 REG_WR8(sc, (BAR_CSTRORM_INTMEM + CSTORM_IGU_MODE_OFFSET),
5222                         CHIP_INT_MODE_IS_BC(sc) ? HC_IGU_BC_MODE :
5223                         HC_IGU_NBC_MODE);
5224         }
5225 }
5226
5227 static void bnx2x_init_internal(struct bnx2x_softc *sc, uint32_t load_code)
5228 {
5229         switch (load_code) {
5230         case FW_MSG_CODE_DRV_LOAD_COMMON:
5231         case FW_MSG_CODE_DRV_LOAD_COMMON_CHIP:
5232                 bnx2x_init_internal_common(sc);
5233                 /* no break */
5234
5235         case FW_MSG_CODE_DRV_LOAD_PORT:
5236                 /* nothing to do */
5237                 /* no break */
5238
5239         case FW_MSG_CODE_DRV_LOAD_FUNCTION:
5240                 /* internal memory per function is initialized inside bnx2x_pf_init */
5241                 break;
5242
5243         default:
5244                 PMD_DRV_LOG(NOTICE, sc, "Unknown load_code (0x%x) from MCP",
5245                             load_code);
5246                 break;
5247         }
5248 }
5249
5250 static void
5251 storm_memset_func_cfg(struct bnx2x_softc *sc,
5252                       struct tstorm_eth_function_common_config *tcfg,
5253                       uint16_t abs_fid)
5254 {
5255         uint32_t addr;
5256         size_t size;
5257
5258         addr = (BAR_TSTRORM_INTMEM +
5259                 TSTORM_FUNCTION_COMMON_CONFIG_OFFSET(abs_fid));
5260         size = sizeof(struct tstorm_eth_function_common_config);
5261         ecore_storm_memset_struct(sc, addr, size, (uint32_t *) tcfg);
5262 }
5263
5264 static void bnx2x_func_init(struct bnx2x_softc *sc, struct bnx2x_func_init_params *p)
5265 {
5266         struct tstorm_eth_function_common_config tcfg = { 0 };
5267
5268         if (CHIP_IS_E1x(sc)) {
5269                 storm_memset_func_cfg(sc, &tcfg, p->func_id);
5270         }
5271
5272         /* Enable the function in the FW */
5273         storm_memset_vf_to_pf(sc, p->func_id, p->pf_id);
5274         storm_memset_func_en(sc, p->func_id, 1);
5275
5276         /* spq */
5277         if (p->func_flgs & FUNC_FLG_SPQ) {
5278                 storm_memset_spq_addr(sc, p->spq_map, p->func_id);
5279                 REG_WR(sc,
5280                        (XSEM_REG_FAST_MEMORY +
5281                         XSTORM_SPQ_PROD_OFFSET(p->func_id)), p->spq_prod);
5282         }
5283 }
5284
5285 /*
5286  * Calculates the sum of vn_min_rates.
5287  * It's needed for further normalizing of the min_rates.
5288  * Returns:
5289  *   sum of vn_min_rates.
5290  *     or
5291  *   0 - if all the min_rates are 0.
5292  * In the later case fainess algorithm should be deactivated.
5293  * If all min rates are not zero then those that are zeroes will be set to 1.
5294  */
5295 static void bnx2x_calc_vn_min(struct bnx2x_softc *sc, struct cmng_init_input *input)
5296 {
5297         uint32_t vn_cfg;
5298         uint32_t vn_min_rate;
5299         int all_zero = 1;
5300         int vn;
5301
5302         for (vn = VN_0; vn < SC_MAX_VN_NUM(sc); vn++) {
5303                 vn_cfg = sc->devinfo.mf_info.mf_config[vn];
5304                 vn_min_rate = (((vn_cfg & FUNC_MF_CFG_MIN_BW_MASK) >>
5305                                 FUNC_MF_CFG_MIN_BW_SHIFT) * 100);
5306
5307                 if (vn_cfg & FUNC_MF_CFG_FUNC_HIDE) {
5308                         /* skip hidden VNs */
5309                         vn_min_rate = 0;
5310                 } else if (!vn_min_rate) {
5311                         /* If min rate is zero - set it to 100 */
5312                         vn_min_rate = DEF_MIN_RATE;
5313                 } else {
5314                         all_zero = 0;
5315                 }
5316
5317                 input->vnic_min_rate[vn] = vn_min_rate;
5318         }
5319
5320         /* if ETS or all min rates are zeros - disable fairness */
5321         if (all_zero) {
5322                 input->flags.cmng_enables &= ~CMNG_FLAGS_PER_PORT_FAIRNESS_VN;
5323         } else {
5324                 input->flags.cmng_enables |= CMNG_FLAGS_PER_PORT_FAIRNESS_VN;
5325         }
5326 }
5327
5328 static uint16_t
5329 bnx2x_extract_max_cfg(__rte_unused struct bnx2x_softc *sc, uint32_t mf_cfg)
5330 {
5331         uint16_t max_cfg = ((mf_cfg & FUNC_MF_CFG_MAX_BW_MASK) >>
5332                             FUNC_MF_CFG_MAX_BW_SHIFT);
5333
5334         if (!max_cfg) {
5335                 PMD_DRV_LOG(DEBUG, sc,
5336                             "Max BW configured to 0 - using 100 instead");
5337                 max_cfg = 100;
5338         }
5339
5340         return max_cfg;
5341 }
5342
5343 static void
5344 bnx2x_calc_vn_max(struct bnx2x_softc *sc, int vn, struct cmng_init_input *input)
5345 {
5346         uint16_t vn_max_rate;
5347         uint32_t vn_cfg = sc->devinfo.mf_info.mf_config[vn];
5348         uint32_t max_cfg;
5349
5350         if (vn_cfg & FUNC_MF_CFG_FUNC_HIDE) {
5351                 vn_max_rate = 0;
5352         } else {
5353                 max_cfg = bnx2x_extract_max_cfg(sc, vn_cfg);
5354
5355                 if (IS_MF_SI(sc)) {
5356                         /* max_cfg in percents of linkspeed */
5357                         vn_max_rate =
5358                             ((sc->link_vars.line_speed * max_cfg) / 100);
5359                 } else {        /* SD modes */
5360                         /* max_cfg is absolute in 100Mb units */
5361                         vn_max_rate = (max_cfg * 100);
5362                 }
5363         }
5364
5365         input->vnic_max_rate[vn] = vn_max_rate;
5366 }
5367
5368 static void
5369 bnx2x_cmng_fns_init(struct bnx2x_softc *sc, uint8_t read_cfg, uint8_t cmng_type)
5370 {
5371         struct cmng_init_input input;
5372         int vn;
5373
5374         memset(&input, 0, sizeof(struct cmng_init_input));
5375
5376         input.port_rate = sc->link_vars.line_speed;
5377
5378         if (cmng_type == CMNG_FNS_MINMAX) {
5379 /* read mf conf from shmem */
5380                 if (read_cfg) {
5381                         bnx2x_read_mf_cfg(sc);
5382                 }
5383
5384 /* get VN min rate and enable fairness if not 0 */
5385                 bnx2x_calc_vn_min(sc, &input);
5386
5387 /* get VN max rate */
5388                 if (sc->port.pmf) {
5389                         for (vn = VN_0; vn < SC_MAX_VN_NUM(sc); vn++) {
5390                                 bnx2x_calc_vn_max(sc, vn, &input);
5391                         }
5392                 }
5393
5394 /* always enable rate shaping and fairness */
5395                 input.flags.cmng_enables |= CMNG_FLAGS_PER_PORT_RATE_SHAPING_VN;
5396
5397                 ecore_init_cmng(&input, &sc->cmng);
5398                 return;
5399         }
5400 }
5401
5402 static int bnx2x_get_cmng_fns_mode(struct bnx2x_softc *sc)
5403 {
5404         if (CHIP_REV_IS_SLOW(sc)) {
5405                 return CMNG_FNS_NONE;
5406         }
5407
5408         if (IS_MF(sc)) {
5409                 return CMNG_FNS_MINMAX;
5410         }
5411
5412         return CMNG_FNS_NONE;
5413 }
5414
5415 static void
5416 storm_memset_cmng(struct bnx2x_softc *sc, struct cmng_init *cmng, uint8_t port)
5417 {
5418         int vn;
5419         int func;
5420         uint32_t addr;
5421         size_t size;
5422
5423         addr = (BAR_XSTRORM_INTMEM + XSTORM_CMNG_PER_PORT_VARS_OFFSET(port));
5424         size = sizeof(struct cmng_struct_per_port);
5425         ecore_storm_memset_struct(sc, addr, size, (uint32_t *) & cmng->port);
5426
5427         for (vn = VN_0; vn < SC_MAX_VN_NUM(sc); vn++) {
5428                 func = func_by_vn(sc, vn);
5429
5430                 addr = (BAR_XSTRORM_INTMEM +
5431                         XSTORM_RATE_SHAPING_PER_VN_VARS_OFFSET(func));
5432                 size = sizeof(struct rate_shaping_vars_per_vn);
5433                 ecore_storm_memset_struct(sc, addr, size,
5434                                           (uint32_t *) & cmng->
5435                                           vnic.vnic_max_rate[vn]);
5436
5437                 addr = (BAR_XSTRORM_INTMEM +
5438                         XSTORM_FAIRNESS_PER_VN_VARS_OFFSET(func));
5439                 size = sizeof(struct fairness_vars_per_vn);
5440                 ecore_storm_memset_struct(sc, addr, size,
5441                                           (uint32_t *) & cmng->
5442                                           vnic.vnic_min_rate[vn]);
5443         }
5444 }
5445
5446 static void bnx2x_pf_init(struct bnx2x_softc *sc)
5447 {
5448         struct bnx2x_func_init_params func_init;
5449         struct event_ring_data eq_data;
5450         uint16_t flags;
5451
5452         memset(&eq_data, 0, sizeof(struct event_ring_data));
5453         memset(&func_init, 0, sizeof(struct bnx2x_func_init_params));
5454
5455         if (!CHIP_IS_E1x(sc)) {
5456 /* reset IGU PF statistics: MSIX + ATTN */
5457 /* PF */
5458                 REG_WR(sc,
5459                        (IGU_REG_STATISTIC_NUM_MESSAGE_SENT +
5460                         (BNX2X_IGU_STAS_MSG_VF_CNT * 4) +
5461                         ((CHIP_IS_MODE_4_PORT(sc) ? SC_FUNC(sc) : SC_VN(sc)) *
5462                          4)), 0);
5463 /* ATTN */
5464                 REG_WR(sc,
5465                        (IGU_REG_STATISTIC_NUM_MESSAGE_SENT +
5466                         (BNX2X_IGU_STAS_MSG_VF_CNT * 4) +
5467                         (BNX2X_IGU_STAS_MSG_PF_CNT * 4) +
5468                         ((CHIP_IS_MODE_4_PORT(sc) ? SC_FUNC(sc) : SC_VN(sc)) *
5469                          4)), 0);
5470         }
5471
5472         /* function setup flags */
5473         flags = (FUNC_FLG_STATS | FUNC_FLG_LEADING | FUNC_FLG_SPQ);
5474
5475         func_init.func_flgs = flags;
5476         func_init.pf_id = SC_FUNC(sc);
5477         func_init.func_id = SC_FUNC(sc);
5478         func_init.spq_map = sc->spq_dma.paddr;
5479         func_init.spq_prod = sc->spq_prod_idx;
5480
5481         bnx2x_func_init(sc, &func_init);
5482
5483         memset(&sc->cmng, 0, sizeof(struct cmng_struct_per_port));
5484
5485         /*
5486          * Congestion management values depend on the link rate.
5487          * There is no active link so initial link rate is set to 10Gbps.
5488          * When the link comes up the congestion management values are
5489          * re-calculated according to the actual link rate.
5490          */
5491         sc->link_vars.line_speed = SPEED_10000;
5492         bnx2x_cmng_fns_init(sc, TRUE, bnx2x_get_cmng_fns_mode(sc));
5493
5494         /* Only the PMF sets the HW */
5495         if (sc->port.pmf) {
5496                 storm_memset_cmng(sc, &sc->cmng, SC_PORT(sc));
5497         }
5498
5499         /* init Event Queue - PCI bus guarantees correct endainity */
5500         eq_data.base_addr.hi = U64_HI(sc->eq_dma.paddr);
5501         eq_data.base_addr.lo = U64_LO(sc->eq_dma.paddr);
5502         eq_data.producer = sc->eq_prod;
5503         eq_data.index_id = HC_SP_INDEX_EQ_CONS;
5504         eq_data.sb_id = DEF_SB_ID;
5505         storm_memset_eq_data(sc, &eq_data, SC_FUNC(sc));
5506 }
5507
5508 static void bnx2x_hc_int_enable(struct bnx2x_softc *sc)
5509 {
5510         int port = SC_PORT(sc);
5511         uint32_t addr = (port) ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0;
5512         uint32_t val = REG_RD(sc, addr);
5513         uint8_t msix = (sc->interrupt_mode == INTR_MODE_MSIX)
5514             || (sc->interrupt_mode == INTR_MODE_SINGLE_MSIX);
5515         uint8_t single_msix = (sc->interrupt_mode == INTR_MODE_SINGLE_MSIX);
5516         uint8_t msi = (sc->interrupt_mode == INTR_MODE_MSI);
5517
5518         if (msix) {
5519                 val &= ~(HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
5520                          HC_CONFIG_0_REG_INT_LINE_EN_0);
5521                 val |= (HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
5522                         HC_CONFIG_0_REG_ATTN_BIT_EN_0);
5523                 if (single_msix) {
5524                         val |= HC_CONFIG_0_REG_SINGLE_ISR_EN_0;
5525                 }
5526         } else if (msi) {
5527                 val &= ~HC_CONFIG_0_REG_INT_LINE_EN_0;
5528                 val |= (HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
5529                         HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
5530                         HC_CONFIG_0_REG_ATTN_BIT_EN_0);
5531         } else {
5532                 val |= (HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
5533                         HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
5534                         HC_CONFIG_0_REG_INT_LINE_EN_0 |
5535                         HC_CONFIG_0_REG_ATTN_BIT_EN_0);
5536
5537                 REG_WR(sc, addr, val);
5538
5539                 val &= ~HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0;
5540         }
5541
5542         REG_WR(sc, addr, val);
5543
5544         /* ensure that HC_CONFIG is written before leading/trailing edge config */
5545         mb();
5546
5547         /* init leading/trailing edge */
5548         if (IS_MF(sc)) {
5549                 val = (0xee0f | (1 << (SC_VN(sc) + 4)));
5550                 if (sc->port.pmf) {
5551                         /* enable nig and gpio3 attention */
5552                         val |= 0x1100;
5553                 }
5554         } else {
5555                 val = 0xffff;
5556         }
5557
5558         REG_WR(sc, (HC_REG_TRAILING_EDGE_0 + port * 8), val);
5559         REG_WR(sc, (HC_REG_LEADING_EDGE_0 + port * 8), val);
5560
5561         /* make sure that interrupts are indeed enabled from here on */
5562         mb();
5563 }
5564
5565 static void bnx2x_igu_int_enable(struct bnx2x_softc *sc)
5566 {
5567         uint32_t val;
5568         uint8_t msix = (sc->interrupt_mode == INTR_MODE_MSIX)
5569             || (sc->interrupt_mode == INTR_MODE_SINGLE_MSIX);
5570         uint8_t single_msix = (sc->interrupt_mode == INTR_MODE_SINGLE_MSIX);
5571         uint8_t msi = (sc->interrupt_mode == INTR_MODE_MSI);
5572
5573         val = REG_RD(sc, IGU_REG_PF_CONFIGURATION);
5574
5575         if (msix) {
5576                 val &= ~(IGU_PF_CONF_INT_LINE_EN | IGU_PF_CONF_SINGLE_ISR_EN);
5577                 val |= (IGU_PF_CONF_MSI_MSIX_EN | IGU_PF_CONF_ATTN_BIT_EN);
5578                 if (single_msix) {
5579                         val |= IGU_PF_CONF_SINGLE_ISR_EN;
5580                 }
5581         } else if (msi) {
5582                 val &= ~IGU_PF_CONF_INT_LINE_EN;
5583                 val |= (IGU_PF_CONF_MSI_MSIX_EN |
5584                         IGU_PF_CONF_ATTN_BIT_EN | IGU_PF_CONF_SINGLE_ISR_EN);
5585         } else {
5586                 val &= ~IGU_PF_CONF_MSI_MSIX_EN;
5587                 val |= (IGU_PF_CONF_INT_LINE_EN |
5588                         IGU_PF_CONF_ATTN_BIT_EN | IGU_PF_CONF_SINGLE_ISR_EN);
5589         }
5590
5591         /* clean previous status - need to configure igu prior to ack */
5592         if ((!msix) || single_msix) {
5593                 REG_WR(sc, IGU_REG_PF_CONFIGURATION, val);
5594                 bnx2x_ack_int(sc);
5595         }
5596
5597         val |= IGU_PF_CONF_FUNC_EN;
5598
5599         PMD_DRV_LOG(DEBUG, sc, "write 0x%x to IGU mode %s",
5600                     val, ((msix) ? "MSI-X" : ((msi) ? "MSI" : "INTx")));
5601
5602         REG_WR(sc, IGU_REG_PF_CONFIGURATION, val);
5603
5604         mb();
5605
5606         /* init leading/trailing edge */
5607         if (IS_MF(sc)) {
5608                 val = (0xee0f | (1 << (SC_VN(sc) + 4)));
5609                 if (sc->port.pmf) {
5610                         /* enable nig and gpio3 attention */
5611                         val |= 0x1100;
5612                 }
5613         } else {
5614                 val = 0xffff;
5615         }
5616
5617         REG_WR(sc, IGU_REG_TRAILING_EDGE_LATCH, val);
5618         REG_WR(sc, IGU_REG_LEADING_EDGE_LATCH, val);
5619
5620         /* make sure that interrupts are indeed enabled from here on */
5621         mb();
5622 }
5623
5624 static void bnx2x_int_enable(struct bnx2x_softc *sc)
5625 {
5626         if (sc->devinfo.int_block == INT_BLOCK_HC) {
5627                 bnx2x_hc_int_enable(sc);
5628         } else {
5629                 bnx2x_igu_int_enable(sc);
5630         }
5631 }
5632
5633 static void bnx2x_hc_int_disable(struct bnx2x_softc *sc)
5634 {
5635         int port = SC_PORT(sc);
5636         uint32_t addr = (port) ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0;
5637         uint32_t val = REG_RD(sc, addr);
5638
5639         val &= ~(HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
5640                  HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
5641                  HC_CONFIG_0_REG_INT_LINE_EN_0 | HC_CONFIG_0_REG_ATTN_BIT_EN_0);
5642         /* flush all outstanding writes */
5643         mb();
5644
5645         REG_WR(sc, addr, val);
5646         if (REG_RD(sc, addr) != val) {
5647                 PMD_DRV_LOG(ERR, sc, "proper val not read from HC IGU!");
5648         }
5649 }
5650
5651 static void bnx2x_igu_int_disable(struct bnx2x_softc *sc)
5652 {
5653         uint32_t val = REG_RD(sc, IGU_REG_PF_CONFIGURATION);
5654
5655         val &= ~(IGU_PF_CONF_MSI_MSIX_EN |
5656                  IGU_PF_CONF_INT_LINE_EN | IGU_PF_CONF_ATTN_BIT_EN);
5657
5658         PMD_DRV_LOG(DEBUG, sc, "write %x to IGU", val);
5659
5660         /* flush all outstanding writes */
5661         mb();
5662
5663         REG_WR(sc, IGU_REG_PF_CONFIGURATION, val);
5664         if (REG_RD(sc, IGU_REG_PF_CONFIGURATION) != val) {
5665                 PMD_DRV_LOG(ERR, sc, "proper val not read from IGU!");
5666         }
5667 }
5668
5669 static void bnx2x_int_disable(struct bnx2x_softc *sc)
5670 {
5671         if (sc->devinfo.int_block == INT_BLOCK_HC) {
5672                 bnx2x_hc_int_disable(sc);
5673         } else {
5674                 bnx2x_igu_int_disable(sc);
5675         }
5676 }
5677
5678 static void bnx2x_nic_init(struct bnx2x_softc *sc, int load_code)
5679 {
5680         int i;
5681
5682         PMD_INIT_FUNC_TRACE(sc);
5683
5684         for (i = 0; i < sc->num_queues; i++) {
5685                 bnx2x_init_eth_fp(sc, i);
5686         }
5687
5688         rmb();                  /* ensure status block indices were read */
5689
5690         bnx2x_init_rx_rings(sc);
5691         bnx2x_init_tx_rings(sc);
5692
5693         if (IS_VF(sc)) {
5694                 bnx2x_memset_stats(sc);
5695                 return;
5696         }
5697
5698         /* initialize MOD_ABS interrupts */
5699         elink_init_mod_abs_int(sc, &sc->link_vars,
5700                                sc->devinfo.chip_id,
5701                                sc->devinfo.shmem_base,
5702                                sc->devinfo.shmem2_base, SC_PORT(sc));
5703
5704         bnx2x_init_def_sb(sc);
5705         bnx2x_update_dsb_idx(sc);
5706         bnx2x_init_sp_ring(sc);
5707         bnx2x_init_eq_ring(sc);
5708         bnx2x_init_internal(sc, load_code);
5709         bnx2x_pf_init(sc);
5710         bnx2x_stats_init(sc);
5711
5712         /* flush all before enabling interrupts */
5713         mb();
5714
5715         bnx2x_int_enable(sc);
5716
5717         /* check for SPIO5 */
5718         bnx2x_attn_int_deasserted0(sc,
5719                                  REG_RD(sc,
5720                                         (MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 +
5721                                          SC_PORT(sc) * 4)) &
5722                                  AEU_INPUTS_ATTN_BITS_SPIO5);
5723 }
5724
5725 static void bnx2x_init_objs(struct bnx2x_softc *sc)
5726 {
5727         /* mcast rules must be added to tx if tx switching is enabled */
5728         ecore_obj_type o_type;
5729         if (sc->flags & BNX2X_TX_SWITCHING)
5730                 o_type = ECORE_OBJ_TYPE_RX_TX;
5731         else
5732                 o_type = ECORE_OBJ_TYPE_RX;
5733
5734         /* RX_MODE controlling object */
5735         ecore_init_rx_mode_obj(sc, &sc->rx_mode_obj);
5736
5737         /* multicast configuration controlling object */
5738         ecore_init_mcast_obj(sc,
5739                              &sc->mcast_obj,
5740                              sc->fp[0].cl_id,
5741                              sc->fp[0].index,
5742                              SC_FUNC(sc),
5743                              SC_FUNC(sc),
5744                              BNX2X_SP(sc, mcast_rdata),
5745                              (rte_iova_t)BNX2X_SP_MAPPING(sc, mcast_rdata),
5746                              ECORE_FILTER_MCAST_PENDING,
5747                              &sc->sp_state, o_type);
5748
5749         /* Setup CAM credit pools */
5750         ecore_init_mac_credit_pool(sc,
5751                                    &sc->macs_pool,
5752                                    SC_FUNC(sc),
5753                                    CHIP_IS_E1x(sc) ? VNICS_PER_PORT(sc) :
5754                                    VNICS_PER_PATH(sc));
5755
5756         ecore_init_vlan_credit_pool(sc,
5757                                     &sc->vlans_pool,
5758                                     SC_ABS_FUNC(sc) >> 1,
5759                                     CHIP_IS_E1x(sc) ? VNICS_PER_PORT(sc) :
5760                                     VNICS_PER_PATH(sc));
5761
5762         /* RSS configuration object */
5763         ecore_init_rss_config_obj(&sc->rss_conf_obj,
5764                                   sc->fp[0].cl_id,
5765                                   sc->fp[0].index,
5766                                   SC_FUNC(sc),
5767                                   SC_FUNC(sc),
5768                                   BNX2X_SP(sc, rss_rdata),
5769                                   (rte_iova_t)BNX2X_SP_MAPPING(sc, rss_rdata),
5770                                   ECORE_FILTER_RSS_CONF_PENDING,
5771                                   &sc->sp_state, ECORE_OBJ_TYPE_RX);
5772 }
5773
5774 /*
5775  * Initialize the function. This must be called before sending CLIENT_SETUP
5776  * for the first client.
5777  */
5778 static int bnx2x_func_start(struct bnx2x_softc *sc)
5779 {
5780         struct ecore_func_state_params func_params = { NULL };
5781         struct ecore_func_start_params *start_params =
5782             &func_params.params.start;
5783
5784         /* Prepare parameters for function state transitions */
5785         bnx2x_set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags);
5786
5787         func_params.f_obj = &sc->func_obj;
5788         func_params.cmd = ECORE_F_CMD_START;
5789
5790         /* Function parameters */
5791         start_params->mf_mode = sc->devinfo.mf_info.mf_mode;
5792         start_params->sd_vlan_tag = OVLAN(sc);
5793
5794         if (CHIP_IS_E2(sc) || CHIP_IS_E3(sc)) {
5795                 start_params->network_cos_mode = STATIC_COS;
5796         } else {                /* CHIP_IS_E1X */
5797                 start_params->network_cos_mode = FW_WRR;
5798         }
5799
5800         start_params->gre_tunnel_mode = 0;
5801         start_params->gre_tunnel_rss = 0;
5802
5803         return ecore_func_state_change(sc, &func_params);
5804 }
5805
5806 static int bnx2x_set_power_state(struct bnx2x_softc *sc, uint8_t state)
5807 {
5808         uint16_t pmcsr;
5809
5810         /* If there is no power capability, silently succeed */
5811         if (!(sc->devinfo.pcie_cap_flags & BNX2X_PM_CAPABLE_FLAG)) {
5812                 PMD_DRV_LOG(WARNING, sc, "No power capability");
5813                 return 0;
5814         }
5815
5816         pci_read(sc, (sc->devinfo.pcie_pm_cap_reg + PCIR_POWER_STATUS), &pmcsr,
5817                  2);
5818
5819         switch (state) {
5820         case PCI_PM_D0:
5821                 pci_write_word(sc,
5822                                (sc->devinfo.pcie_pm_cap_reg +
5823                                 PCIR_POWER_STATUS),
5824                                ((pmcsr & ~PCIM_PSTAT_DMASK) | PCIM_PSTAT_PME));
5825
5826                 if (pmcsr & PCIM_PSTAT_DMASK) {
5827                         /* delay required during transition out of D3hot */
5828                         DELAY(20000);
5829                 }
5830
5831                 break;
5832
5833         case PCI_PM_D3hot:
5834                 /* don't shut down the power for emulation and FPGA */
5835                 if (CHIP_REV_IS_SLOW(sc)) {
5836                         return 0;
5837                 }
5838
5839                 pmcsr &= ~PCIM_PSTAT_DMASK;
5840                 pmcsr |= PCIM_PSTAT_D3;
5841
5842                 if (sc->wol) {
5843                         pmcsr |= PCIM_PSTAT_PMEENABLE;
5844                 }
5845
5846                 pci_write_long(sc,
5847                                (sc->devinfo.pcie_pm_cap_reg +
5848                                 PCIR_POWER_STATUS), pmcsr);
5849
5850                 /*
5851                  * No more memory access after this point until device is brought back
5852                  * to D0 state.
5853                  */
5854                 break;
5855
5856         default:
5857                 PMD_DRV_LOG(NOTICE, sc, "Can't support PCI power state = %d",
5858                             state);
5859                 return -1;
5860         }
5861
5862         return 0;
5863 }
5864
5865 /* return true if succeeded to acquire the lock */
5866 static uint8_t bnx2x_trylock_hw_lock(struct bnx2x_softc *sc, uint32_t resource)
5867 {
5868         uint32_t lock_status;
5869         uint32_t resource_bit = (1 << resource);
5870         int func = SC_FUNC(sc);
5871         uint32_t hw_lock_control_reg;
5872
5873         /* Validating that the resource is within range */
5874         if (resource > HW_LOCK_MAX_RESOURCE_VALUE) {
5875                 PMD_DRV_LOG(INFO, sc,
5876                             "resource(0x%x) > HW_LOCK_MAX_RESOURCE_VALUE(0x%x)",
5877                             resource, HW_LOCK_MAX_RESOURCE_VALUE);
5878                 return FALSE;
5879         }
5880
5881         if (func <= 5) {
5882                 hw_lock_control_reg = (MISC_REG_DRIVER_CONTROL_1 + func * 8);
5883         } else {
5884                 hw_lock_control_reg =
5885                     (MISC_REG_DRIVER_CONTROL_7 + (func - 6) * 8);
5886         }
5887
5888         /* try to acquire the lock */
5889         REG_WR(sc, hw_lock_control_reg + 4, resource_bit);
5890         lock_status = REG_RD(sc, hw_lock_control_reg);
5891         if (lock_status & resource_bit) {
5892                 return TRUE;
5893         }
5894
5895         PMD_DRV_LOG(NOTICE, sc, "Failed to get a resource lock 0x%x", resource);
5896
5897         return FALSE;
5898 }
5899
5900 /*
5901  * Get the recovery leader resource id according to the engine this function
5902  * belongs to. Currently only only 2 engines is supported.
5903  */
5904 static int bnx2x_get_leader_lock_resource(struct bnx2x_softc *sc)
5905 {
5906         if (SC_PATH(sc)) {
5907                 return HW_LOCK_RESOURCE_RECOVERY_LEADER_1;
5908         } else {
5909                 return HW_LOCK_RESOURCE_RECOVERY_LEADER_0;
5910         }
5911 }
5912
5913 /* try to acquire a leader lock for current engine */
5914 static uint8_t bnx2x_trylock_leader_lock(struct bnx2x_softc *sc)
5915 {
5916         return bnx2x_trylock_hw_lock(sc, bnx2x_get_leader_lock_resource(sc));
5917 }
5918
5919 static int bnx2x_release_leader_lock(struct bnx2x_softc *sc)
5920 {
5921         return bnx2x_release_hw_lock(sc, bnx2x_get_leader_lock_resource(sc));
5922 }
5923
5924 /* close gates #2, #3 and #4 */
5925 static void bnx2x_set_234_gates(struct bnx2x_softc *sc, uint8_t close)
5926 {
5927         uint32_t val;
5928
5929         /* gates #2 and #4a are closed/opened */
5930         /* #4 */
5931         REG_WR(sc, PXP_REG_HST_DISCARD_DOORBELLS, ! !close);
5932         /* #2 */
5933         REG_WR(sc, PXP_REG_HST_DISCARD_INTERNAL_WRITES, ! !close);
5934
5935         /* #3 */
5936         if (CHIP_IS_E1x(sc)) {
5937 /* prevent interrupts from HC on both ports */
5938                 val = REG_RD(sc, HC_REG_CONFIG_1);
5939                 if (close)
5940                         REG_WR(sc, HC_REG_CONFIG_1, (val & ~(uint32_t)
5941                                                      HC_CONFIG_1_REG_BLOCK_DISABLE_1));
5942                 else
5943                         REG_WR(sc, HC_REG_CONFIG_1,
5944                                (val | HC_CONFIG_1_REG_BLOCK_DISABLE_1));
5945
5946                 val = REG_RD(sc, HC_REG_CONFIG_0);
5947                 if (close)
5948                         REG_WR(sc, HC_REG_CONFIG_0, (val & ~(uint32_t)
5949                                                      HC_CONFIG_0_REG_BLOCK_DISABLE_0));
5950                 else
5951                         REG_WR(sc, HC_REG_CONFIG_0,
5952                                (val | HC_CONFIG_0_REG_BLOCK_DISABLE_0));
5953
5954         } else {
5955 /* Prevent incoming interrupts in IGU */
5956                 val = REG_RD(sc, IGU_REG_BLOCK_CONFIGURATION);
5957
5958                 if (close)
5959                         REG_WR(sc, IGU_REG_BLOCK_CONFIGURATION,
5960                                (val & ~(uint32_t)
5961                                 IGU_BLOCK_CONFIGURATION_REG_BLOCK_ENABLE));
5962                 else
5963                         REG_WR(sc, IGU_REG_BLOCK_CONFIGURATION,
5964                                (val |
5965                                 IGU_BLOCK_CONFIGURATION_REG_BLOCK_ENABLE));
5966         }
5967
5968         wmb();
5969 }
5970
5971 /* poll for pending writes bit, it should get cleared in no more than 1s */
5972 static int bnx2x_er_poll_igu_vq(struct bnx2x_softc *sc)
5973 {
5974         uint32_t cnt = 1000;
5975         uint32_t pend_bits = 0;
5976
5977         do {
5978                 pend_bits = REG_RD(sc, IGU_REG_PENDING_BITS_STATUS);
5979
5980                 if (pend_bits == 0) {
5981                         break;
5982                 }
5983
5984                 DELAY(1000);
5985         } while (cnt-- > 0);
5986
5987         if (cnt <= 0) {
5988                 PMD_DRV_LOG(NOTICE, sc, "Still pending IGU requests bits=0x%08x!",
5989                             pend_bits);
5990                 return -1;
5991         }
5992
5993         return 0;
5994 }
5995
5996 #define SHARED_MF_CLP_MAGIC  0x80000000 /* 'magic' bit */
5997
5998 static void bnx2x_clp_reset_prep(struct bnx2x_softc *sc, uint32_t * magic_val)
5999 {
6000         /* Do some magic... */
6001         uint32_t val = MFCFG_RD(sc, shared_mf_config.clp_mb);
6002         *magic_val = val & SHARED_MF_CLP_MAGIC;
6003         MFCFG_WR(sc, shared_mf_config.clp_mb, val | SHARED_MF_CLP_MAGIC);
6004 }
6005
6006 /* restore the value of the 'magic' bit */
6007 static void bnx2x_clp_reset_done(struct bnx2x_softc *sc, uint32_t magic_val)
6008 {
6009         /* Restore the 'magic' bit value... */
6010         uint32_t val = MFCFG_RD(sc, shared_mf_config.clp_mb);
6011         MFCFG_WR(sc, shared_mf_config.clp_mb,
6012                  (val & (~SHARED_MF_CLP_MAGIC)) | magic_val);
6013 }
6014
6015 /* prepare for MCP reset, takes care of CLP configurations */
6016 static void bnx2x_reset_mcp_prep(struct bnx2x_softc *sc, uint32_t * magic_val)
6017 {
6018         uint32_t shmem;
6019         uint32_t validity_offset;
6020
6021         /* set `magic' bit in order to save MF config */
6022         bnx2x_clp_reset_prep(sc, magic_val);
6023
6024         /* get shmem offset */
6025         shmem = REG_RD(sc, MISC_REG_SHARED_MEM_ADDR);
6026         validity_offset =
6027             offsetof(struct shmem_region, validity_map[SC_PORT(sc)]);
6028
6029         /* Clear validity map flags */
6030         if (shmem > 0) {
6031                 REG_WR(sc, shmem + validity_offset, 0);
6032         }
6033 }
6034
6035 #define MCP_TIMEOUT      5000   /* 5 seconds (in ms) */
6036 #define MCP_ONE_TIMEOUT  100    /* 100 ms */
6037
6038 static void bnx2x_mcp_wait_one(struct bnx2x_softc *sc)
6039 {
6040         /* special handling for emulation and FPGA (10 times longer) */
6041         if (CHIP_REV_IS_SLOW(sc)) {
6042                 DELAY((MCP_ONE_TIMEOUT * 10) * 1000);
6043         } else {
6044                 DELAY((MCP_ONE_TIMEOUT) * 1000);
6045         }
6046 }
6047
6048 /* initialize shmem_base and waits for validity signature to appear */
6049 static int bnx2x_init_shmem(struct bnx2x_softc *sc)
6050 {
6051         int cnt = 0;
6052         uint32_t val = 0;
6053
6054         do {
6055                 sc->devinfo.shmem_base =
6056                     sc->link_params.shmem_base =
6057                     REG_RD(sc, MISC_REG_SHARED_MEM_ADDR);
6058
6059                 if (sc->devinfo.shmem_base) {
6060                         val = SHMEM_RD(sc, validity_map[SC_PORT(sc)]);
6061                         if (val & SHR_MEM_VALIDITY_MB)
6062                                 return 0;
6063                 }
6064
6065                 bnx2x_mcp_wait_one(sc);
6066
6067         } while (cnt++ < (MCP_TIMEOUT / MCP_ONE_TIMEOUT));
6068
6069         PMD_DRV_LOG(NOTICE, sc, "BAD MCP validity signature");
6070
6071         return -1;
6072 }
6073
6074 static int bnx2x_reset_mcp_comp(struct bnx2x_softc *sc, uint32_t magic_val)
6075 {
6076         int rc = bnx2x_init_shmem(sc);
6077
6078         /* Restore the `magic' bit value */
6079         bnx2x_clp_reset_done(sc, magic_val);
6080
6081         return rc;
6082 }
6083
6084 static void bnx2x_pxp_prep(struct bnx2x_softc *sc)
6085 {
6086         REG_WR(sc, PXP2_REG_RD_START_INIT, 0);
6087         REG_WR(sc, PXP2_REG_RQ_RBC_DONE, 0);
6088         wmb();
6089 }
6090
6091 /*
6092  * Reset the whole chip except for:
6093  *      - PCIE core
6094  *      - PCI Glue, PSWHST, PXP/PXP2 RF (all controlled by one reset bit)
6095  *      - IGU
6096  *      - MISC (including AEU)
6097  *      - GRC
6098  *      - RBCN, RBCP
6099  */
6100 static void bnx2x_process_kill_chip_reset(struct bnx2x_softc *sc, uint8_t global)
6101 {
6102         uint32_t not_reset_mask1, reset_mask1, not_reset_mask2, reset_mask2;
6103         uint32_t global_bits2, stay_reset2;
6104
6105         /*
6106          * Bits that have to be set in reset_mask2 if we want to reset 'global'
6107          * (per chip) blocks.
6108          */
6109         global_bits2 =
6110             MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_CMN_CPU |
6111             MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_CMN_CORE;
6112
6113         /*
6114          * Don't reset the following blocks.
6115          * Important: per port blocks (such as EMAC, BMAC, UMAC) can't be
6116          *            reset, as in 4 port device they might still be owned
6117          *            by the MCP (there is only one leader per path).
6118          */
6119         not_reset_mask1 =
6120             MISC_REGISTERS_RESET_REG_1_RST_HC |
6121             MISC_REGISTERS_RESET_REG_1_RST_PXPV |
6122             MISC_REGISTERS_RESET_REG_1_RST_PXP;
6123
6124         not_reset_mask2 =
6125             MISC_REGISTERS_RESET_REG_2_RST_PCI_MDIO |
6126             MISC_REGISTERS_RESET_REG_2_RST_EMAC0_HARD_CORE |
6127             MISC_REGISTERS_RESET_REG_2_RST_EMAC1_HARD_CORE |
6128             MISC_REGISTERS_RESET_REG_2_RST_MISC_CORE |
6129             MISC_REGISTERS_RESET_REG_2_RST_RBCN |
6130             MISC_REGISTERS_RESET_REG_2_RST_GRC |
6131             MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_REG_HARD_CORE |
6132             MISC_REGISTERS_RESET_REG_2_RST_MCP_N_HARD_CORE_RST_B |
6133             MISC_REGISTERS_RESET_REG_2_RST_ATC |
6134             MISC_REGISTERS_RESET_REG_2_PGLC |
6135             MISC_REGISTERS_RESET_REG_2_RST_BMAC0 |
6136             MISC_REGISTERS_RESET_REG_2_RST_BMAC1 |
6137             MISC_REGISTERS_RESET_REG_2_RST_EMAC0 |
6138             MISC_REGISTERS_RESET_REG_2_RST_EMAC1 |
6139             MISC_REGISTERS_RESET_REG_2_UMAC0 | MISC_REGISTERS_RESET_REG_2_UMAC1;
6140
6141         /*
6142          * Keep the following blocks in reset:
6143          *  - all xxMACs are handled by the elink code.
6144          */
6145         stay_reset2 =
6146             MISC_REGISTERS_RESET_REG_2_XMAC |
6147             MISC_REGISTERS_RESET_REG_2_XMAC_SOFT;
6148
6149         /* Full reset masks according to the chip */
6150         reset_mask1 = 0xffffffff;
6151
6152         if (CHIP_IS_E1H(sc))
6153                 reset_mask2 = 0x1ffff;
6154         else if (CHIP_IS_E2(sc))
6155                 reset_mask2 = 0xfffff;
6156         else                    /* CHIP_IS_E3 */
6157                 reset_mask2 = 0x3ffffff;
6158
6159         /* Don't reset global blocks unless we need to */
6160         if (!global)
6161                 reset_mask2 &= ~global_bits2;
6162
6163         /*
6164          * In case of attention in the QM, we need to reset PXP
6165          * (MISC_REGISTERS_RESET_REG_2_RST_PXP_RQ_RD_WR) before QM
6166          * because otherwise QM reset would release 'close the gates' shortly
6167          * before resetting the PXP, then the PSWRQ would send a write
6168          * request to PGLUE. Then when PXP is reset, PGLUE would try to
6169          * read the payload data from PSWWR, but PSWWR would not
6170          * respond. The write queue in PGLUE would stuck, dmae commands
6171          * would not return. Therefore it's important to reset the second
6172          * reset register (containing the
6173          * MISC_REGISTERS_RESET_REG_2_RST_PXP_RQ_RD_WR bit) before the
6174          * first one (containing the MISC_REGISTERS_RESET_REG_1_RST_QM
6175          * bit).
6176          */
6177         REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
6178                reset_mask2 & (~not_reset_mask2));
6179
6180         REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR,
6181                reset_mask1 & (~not_reset_mask1));
6182
6183         mb();
6184         wmb();
6185
6186         REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET,
6187                reset_mask2 & (~stay_reset2));
6188
6189         mb();
6190         wmb();
6191
6192         REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, reset_mask1);
6193         wmb();
6194 }
6195
6196 static int bnx2x_process_kill(struct bnx2x_softc *sc, uint8_t global)
6197 {
6198         int cnt = 1000;
6199         uint32_t val = 0;
6200         uint32_t sr_cnt, blk_cnt, port_is_idle_0, port_is_idle_1, pgl_exp_rom2;
6201         uint32_t tags_63_32 = 0;
6202
6203         /* Empty the Tetris buffer, wait for 1s */
6204         do {
6205                 sr_cnt = REG_RD(sc, PXP2_REG_RD_SR_CNT);
6206                 blk_cnt = REG_RD(sc, PXP2_REG_RD_BLK_CNT);
6207                 port_is_idle_0 = REG_RD(sc, PXP2_REG_RD_PORT_IS_IDLE_0);
6208                 port_is_idle_1 = REG_RD(sc, PXP2_REG_RD_PORT_IS_IDLE_1);
6209                 pgl_exp_rom2 = REG_RD(sc, PXP2_REG_PGL_EXP_ROM2);
6210                 if (CHIP_IS_E3(sc)) {
6211                         tags_63_32 = REG_RD(sc, PGLUE_B_REG_TAGS_63_32);
6212                 }
6213
6214                 if ((sr_cnt == 0x7e) && (blk_cnt == 0xa0) &&
6215                     ((port_is_idle_0 & 0x1) == 0x1) &&
6216                     ((port_is_idle_1 & 0x1) == 0x1) &&
6217                     (pgl_exp_rom2 == 0xffffffff) &&
6218                     (!CHIP_IS_E3(sc) || (tags_63_32 == 0xffffffff)))
6219                         break;
6220                 DELAY(1000);
6221         } while (cnt-- > 0);
6222
6223         if (cnt <= 0) {
6224                 PMD_DRV_LOG(NOTICE, sc,
6225                             "ERROR: Tetris buffer didn't get empty or there "
6226                             "are still outstanding read requests after 1s! "
6227                             "sr_cnt=0x%08x, blk_cnt=0x%08x, port_is_idle_0=0x%08x, "
6228                             "port_is_idle_1=0x%08x, pgl_exp_rom2=0x%08x",
6229                             sr_cnt, blk_cnt, port_is_idle_0, port_is_idle_1,
6230                             pgl_exp_rom2);
6231                 return -1;
6232         }
6233
6234         mb();
6235
6236         /* Close gates #2, #3 and #4 */
6237         bnx2x_set_234_gates(sc, TRUE);
6238
6239         /* Poll for IGU VQs for 57712 and newer chips */
6240         if (!CHIP_IS_E1x(sc) && bnx2x_er_poll_igu_vq(sc)) {
6241                 return -1;
6242         }
6243
6244         /* clear "unprepared" bit */
6245         REG_WR(sc, MISC_REG_UNPREPARED, 0);
6246         mb();
6247
6248         /* Make sure all is written to the chip before the reset */
6249         wmb();
6250
6251         /*
6252          * Wait for 1ms to empty GLUE and PCI-E core queues,
6253          * PSWHST, GRC and PSWRD Tetris buffer.
6254          */
6255         DELAY(1000);
6256
6257         /* Prepare to chip reset: */
6258         /* MCP */
6259         if (global) {
6260                 bnx2x_reset_mcp_prep(sc, &val);
6261         }
6262
6263         /* PXP */
6264         bnx2x_pxp_prep(sc);
6265         mb();
6266
6267         /* reset the chip */
6268         bnx2x_process_kill_chip_reset(sc, global);
6269         mb();
6270
6271         /* Recover after reset: */
6272         /* MCP */
6273         if (global && bnx2x_reset_mcp_comp(sc, val)) {
6274                 return -1;
6275         }
6276
6277         /* Open the gates #2, #3 and #4 */
6278         bnx2x_set_234_gates(sc, FALSE);
6279
6280         return 0;
6281 }
6282
6283 static int bnx2x_leader_reset(struct bnx2x_softc *sc)
6284 {
6285         int rc = 0;
6286         uint8_t global = bnx2x_reset_is_global(sc);
6287         uint32_t load_code;
6288
6289         /*
6290          * If not going to reset MCP, load "fake" driver to reset HW while
6291          * driver is owner of the HW.
6292          */
6293         if (!global && !BNX2X_NOMCP(sc)) {
6294                 load_code = bnx2x_fw_command(sc, DRV_MSG_CODE_LOAD_REQ,
6295                                            DRV_MSG_CODE_LOAD_REQ_WITH_LFA);
6296                 if (!load_code) {
6297                         PMD_DRV_LOG(NOTICE, sc, "MCP response failure, aborting");
6298                         rc = -1;
6299                         goto exit_leader_reset;
6300                 }
6301
6302                 if ((load_code != FW_MSG_CODE_DRV_LOAD_COMMON_CHIP) &&
6303                     (load_code != FW_MSG_CODE_DRV_LOAD_COMMON)) {
6304                         PMD_DRV_LOG(NOTICE, sc,
6305                                     "MCP unexpected response, aborting");
6306                         rc = -1;
6307                         goto exit_leader_reset2;
6308                 }
6309
6310                 load_code = bnx2x_fw_command(sc, DRV_MSG_CODE_LOAD_DONE, 0);
6311                 if (!load_code) {
6312                         PMD_DRV_LOG(NOTICE, sc, "MCP response failure, aborting");
6313                         rc = -1;
6314                         goto exit_leader_reset2;
6315                 }
6316         }
6317
6318         /* try to recover after the failure */
6319         if (bnx2x_process_kill(sc, global)) {
6320                 PMD_DRV_LOG(NOTICE, sc, "Something bad occurred on engine %d!",
6321                             SC_PATH(sc));
6322                 rc = -1;
6323                 goto exit_leader_reset2;
6324         }
6325
6326         /*
6327          * Clear the RESET_IN_PROGRESS and RESET_GLOBAL bits and update the driver
6328          * state.
6329          */
6330         bnx2x_set_reset_done(sc);
6331         if (global) {
6332                 bnx2x_clear_reset_global(sc);
6333         }
6334
6335 exit_leader_reset2:
6336
6337         /* unload "fake driver" if it was loaded */
6338         if (!global &&!BNX2X_NOMCP(sc)) {
6339                 bnx2x_fw_command(sc, DRV_MSG_CODE_UNLOAD_REQ_WOL_MCP, 0);
6340                 bnx2x_fw_command(sc, DRV_MSG_CODE_UNLOAD_DONE, 0);
6341         }
6342
6343 exit_leader_reset:
6344
6345         sc->is_leader = 0;
6346         bnx2x_release_leader_lock(sc);
6347
6348         mb();
6349         return rc;
6350 }
6351
6352 /*
6353  * prepare INIT transition, parameters configured:
6354  *   - HC configuration
6355  *   - Queue's CDU context
6356  */
6357 static void
6358 bnx2x_pf_q_prep_init(struct bnx2x_softc *sc, struct bnx2x_fastpath *fp,
6359                    struct ecore_queue_init_params *init_params)
6360 {
6361         uint8_t cos;
6362         int cxt_index, cxt_offset;
6363
6364         bnx2x_set_bit(ECORE_Q_FLG_HC, &init_params->rx.flags);
6365         bnx2x_set_bit(ECORE_Q_FLG_HC, &init_params->tx.flags);
6366
6367         bnx2x_set_bit(ECORE_Q_FLG_HC_EN, &init_params->rx.flags);
6368         bnx2x_set_bit(ECORE_Q_FLG_HC_EN, &init_params->tx.flags);
6369
6370         /* HC rate */
6371         init_params->rx.hc_rate =
6372             sc->hc_rx_ticks ? (1000000 / sc->hc_rx_ticks) : 0;
6373         init_params->tx.hc_rate =
6374             sc->hc_tx_ticks ? (1000000 / sc->hc_tx_ticks) : 0;
6375
6376         /* FW SB ID */
6377         init_params->rx.fw_sb_id = init_params->tx.fw_sb_id = fp->fw_sb_id;
6378
6379         /* CQ index among the SB indices */
6380         init_params->rx.sb_cq_index = HC_INDEX_ETH_RX_CQ_CONS;
6381         init_params->tx.sb_cq_index = HC_INDEX_ETH_FIRST_TX_CQ_CONS;
6382
6383         /* set maximum number of COSs supported by this queue */
6384         init_params->max_cos = sc->max_cos;
6385
6386         /* set the context pointers queue object */
6387         for (cos = FIRST_TX_COS_INDEX; cos < init_params->max_cos; cos++) {
6388                 cxt_index = fp->index / ILT_PAGE_CIDS;
6389                 cxt_offset = fp->index - (cxt_index * ILT_PAGE_CIDS);
6390                 init_params->cxts[cos] =
6391                     &sc->context[cxt_index].vcxt[cxt_offset].eth;
6392         }
6393 }
6394
6395 /* set flags that are common for the Tx-only and not normal connections */
6396 static unsigned long
6397 bnx2x_get_common_flags(struct bnx2x_softc *sc, uint8_t zero_stats)
6398 {
6399         unsigned long flags = 0;
6400
6401         /* PF driver will always initialize the Queue to an ACTIVE state */
6402         bnx2x_set_bit(ECORE_Q_FLG_ACTIVE, &flags);
6403
6404         /*
6405          * tx only connections collect statistics (on the same index as the
6406          * parent connection). The statistics are zeroed when the parent
6407          * connection is initialized.
6408          */
6409
6410         bnx2x_set_bit(ECORE_Q_FLG_STATS, &flags);
6411         if (zero_stats) {
6412                 bnx2x_set_bit(ECORE_Q_FLG_ZERO_STATS, &flags);
6413         }
6414
6415         /*
6416          * tx only connections can support tx-switching, though their
6417          * CoS-ness doesn't survive the loopback
6418          */
6419         if (sc->flags & BNX2X_TX_SWITCHING) {
6420                 bnx2x_set_bit(ECORE_Q_FLG_TX_SWITCH, &flags);
6421         }
6422
6423         bnx2x_set_bit(ECORE_Q_FLG_PCSUM_ON_PKT, &flags);
6424
6425         return flags;
6426 }
6427
6428 static unsigned long bnx2x_get_q_flags(struct bnx2x_softc *sc, uint8_t leading)
6429 {
6430         unsigned long flags = 0;
6431
6432         if (IS_MF_SD(sc)) {
6433                 bnx2x_set_bit(ECORE_Q_FLG_OV, &flags);
6434         }
6435
6436         if (leading) {
6437                 bnx2x_set_bit(ECORE_Q_FLG_LEADING_RSS, &flags);
6438                 bnx2x_set_bit(ECORE_Q_FLG_MCAST, &flags);
6439         }
6440
6441         bnx2x_set_bit(ECORE_Q_FLG_VLAN, &flags);
6442
6443         /* merge with common flags */
6444         return flags | bnx2x_get_common_flags(sc, TRUE);
6445 }
6446
6447 static void
6448 bnx2x_pf_q_prep_general(struct bnx2x_softc *sc, struct bnx2x_fastpath *fp,
6449                       struct ecore_general_setup_params *gen_init, uint8_t cos)
6450 {
6451         gen_init->stat_id = bnx2x_stats_id(fp);
6452         gen_init->spcl_id = fp->cl_id;
6453         gen_init->mtu = sc->mtu;
6454         gen_init->cos = cos;
6455 }
6456
6457 static void
6458 bnx2x_pf_rx_q_prep(struct bnx2x_softc *sc, struct bnx2x_fastpath *fp,
6459                  struct rxq_pause_params *pause,
6460                  struct ecore_rxq_setup_params *rxq_init)
6461 {
6462         struct bnx2x_rx_queue *rxq;
6463
6464         rxq = sc->rx_queues[fp->index];
6465         if (!rxq) {
6466                 PMD_RX_LOG(ERR, "RX queue is NULL");
6467                 return;
6468         }
6469         /* pause */
6470         pause->bd_th_lo = BD_TH_LO(sc);
6471         pause->bd_th_hi = BD_TH_HI(sc);
6472
6473         pause->rcq_th_lo = RCQ_TH_LO(sc);
6474         pause->rcq_th_hi = RCQ_TH_HI(sc);
6475
6476         /* validate rings have enough entries to cross high thresholds */
6477         if (sc->dropless_fc &&
6478             pause->bd_th_hi + FW_PREFETCH_CNT > sc->rx_ring_size) {
6479                 PMD_DRV_LOG(WARNING, sc, "rx bd ring threshold limit");
6480         }
6481
6482         if (sc->dropless_fc &&
6483             pause->rcq_th_hi + FW_PREFETCH_CNT > USABLE_RCQ_ENTRIES(rxq)) {
6484                 PMD_DRV_LOG(WARNING, sc, "rcq ring threshold limit");
6485         }
6486
6487         pause->pri_map = 1;
6488
6489         /* rxq setup */
6490         rxq_init->dscr_map = (rte_iova_t)rxq->rx_ring_phys_addr;
6491         rxq_init->rcq_map = (rte_iova_t)rxq->cq_ring_phys_addr;
6492         rxq_init->rcq_np_map = (rte_iova_t)(rxq->cq_ring_phys_addr +
6493                                               BNX2X_PAGE_SIZE);
6494
6495         /*
6496          * This should be a maximum number of data bytes that may be
6497          * placed on the BD (not including paddings).
6498          */
6499         rxq_init->buf_sz = (fp->rx_buf_size - IP_HEADER_ALIGNMENT_PADDING);
6500
6501         rxq_init->cl_qzone_id = fp->cl_qzone_id;
6502         rxq_init->rss_engine_id = SC_FUNC(sc);
6503         rxq_init->mcast_engine_id = SC_FUNC(sc);
6504
6505         rxq_init->cache_line_log = BNX2X_RX_ALIGN_SHIFT;
6506         rxq_init->fw_sb_id = fp->fw_sb_id;
6507
6508         rxq_init->sb_cq_index = HC_INDEX_ETH_RX_CQ_CONS;
6509
6510         /*
6511          * configure silent vlan removal
6512          * if multi function mode is afex, then mask default vlan
6513          */
6514         if (IS_MF_AFEX(sc)) {
6515                 rxq_init->silent_removal_value =
6516                     sc->devinfo.mf_info.afex_def_vlan_tag;
6517                 rxq_init->silent_removal_mask = EVL_VLID_MASK;
6518         }
6519 }
6520
6521 static void
6522 bnx2x_pf_tx_q_prep(struct bnx2x_softc *sc, struct bnx2x_fastpath *fp,
6523                  struct ecore_txq_setup_params *txq_init, uint8_t cos)
6524 {
6525         struct bnx2x_tx_queue *txq = fp->sc->tx_queues[fp->index];
6526
6527         if (!txq) {
6528                 PMD_TX_LOG(ERR, "ERROR: TX queue is NULL");
6529                 return;
6530         }
6531         txq_init->dscr_map = (rte_iova_t)txq->tx_ring_phys_addr;
6532         txq_init->sb_cq_index = HC_INDEX_ETH_FIRST_TX_CQ_CONS + cos;
6533         txq_init->traffic_type = LLFC_TRAFFIC_TYPE_NW;
6534         txq_init->fw_sb_id = fp->fw_sb_id;
6535
6536         /*
6537          * set the TSS leading client id for TX classfication to the
6538          * leading RSS client id
6539          */
6540         txq_init->tss_leading_cl_id = BNX2X_FP(sc, 0, cl_id);
6541 }
6542
6543 /*
6544  * This function performs 2 steps in a queue state machine:
6545  *   1) RESET->INIT
6546  *   2) INIT->SETUP
6547  */
6548 static int
6549 bnx2x_setup_queue(struct bnx2x_softc *sc, struct bnx2x_fastpath *fp, uint8_t leading)
6550 {
6551         struct ecore_queue_state_params q_params = { NULL };
6552         struct ecore_queue_setup_params *setup_params = &q_params.params.setup;
6553         int rc;
6554
6555         PMD_DRV_LOG(DEBUG, sc, "setting up queue %d", fp->index);
6556
6557         bnx2x_ack_sb(sc, fp->igu_sb_id, USTORM_ID, 0, IGU_INT_ENABLE, 0);
6558
6559         q_params.q_obj = &BNX2X_SP_OBJ(sc, fp).q_obj;
6560
6561         /* we want to wait for completion in this context */
6562         bnx2x_set_bit(RAMROD_COMP_WAIT, &q_params.ramrod_flags);
6563
6564         /* prepare the INIT parameters */
6565         bnx2x_pf_q_prep_init(sc, fp, &q_params.params.init);
6566
6567         /* Set the command */
6568         q_params.cmd = ECORE_Q_CMD_INIT;
6569
6570         /* Change the state to INIT */
6571         rc = ecore_queue_state_change(sc, &q_params);
6572         if (rc) {
6573                 PMD_DRV_LOG(NOTICE, sc, "Queue(%d) INIT failed", fp->index);
6574                 return rc;
6575         }
6576
6577         PMD_DRV_LOG(DEBUG, sc, "init complete");
6578
6579         /* now move the Queue to the SETUP state */
6580         memset(setup_params, 0, sizeof(*setup_params));
6581
6582         /* set Queue flags */
6583         setup_params->flags = bnx2x_get_q_flags(sc, leading);
6584
6585         /* set general SETUP parameters */
6586         bnx2x_pf_q_prep_general(sc, fp, &setup_params->gen_params,
6587                               FIRST_TX_COS_INDEX);
6588
6589         bnx2x_pf_rx_q_prep(sc, fp,
6590                          &setup_params->pause_params,
6591                          &setup_params->rxq_params);
6592
6593         bnx2x_pf_tx_q_prep(sc, fp, &setup_params->txq_params, FIRST_TX_COS_INDEX);
6594
6595         /* Set the command */
6596         q_params.cmd = ECORE_Q_CMD_SETUP;
6597
6598         /* change the state to SETUP */
6599         rc = ecore_queue_state_change(sc, &q_params);
6600         if (rc) {
6601                 PMD_DRV_LOG(NOTICE, sc, "Queue(%d) SETUP failed", fp->index);
6602                 return rc;
6603         }
6604
6605         return rc;
6606 }
6607
6608 static int bnx2x_setup_leading(struct bnx2x_softc *sc)
6609 {
6610         if (IS_PF(sc))
6611                 return bnx2x_setup_queue(sc, &sc->fp[0], TRUE);
6612         else                    /* VF */
6613                 return bnx2x_vf_setup_queue(sc, &sc->fp[0], TRUE);
6614 }
6615
6616 static int
6617 bnx2x_config_rss_pf(struct bnx2x_softc *sc, struct ecore_rss_config_obj *rss_obj,
6618                   uint8_t config_hash)
6619 {
6620         struct ecore_config_rss_params params = { NULL };
6621         uint32_t i;
6622
6623         /*
6624          * Although RSS is meaningless when there is a single HW queue we
6625          * still need it enabled in order to have HW Rx hash generated.
6626          */
6627
6628         params.rss_obj = rss_obj;
6629
6630         bnx2x_set_bit(RAMROD_COMP_WAIT, &params.ramrod_flags);
6631
6632         bnx2x_set_bit(ECORE_RSS_MODE_REGULAR, &params.rss_flags);
6633
6634         /* RSS configuration */
6635         bnx2x_set_bit(ECORE_RSS_IPV4, &params.rss_flags);
6636         bnx2x_set_bit(ECORE_RSS_IPV4_TCP, &params.rss_flags);
6637         bnx2x_set_bit(ECORE_RSS_IPV6, &params.rss_flags);
6638         bnx2x_set_bit(ECORE_RSS_IPV6_TCP, &params.rss_flags);
6639         if (rss_obj->udp_rss_v4) {
6640                 bnx2x_set_bit(ECORE_RSS_IPV4_UDP, &params.rss_flags);
6641         }
6642         if (rss_obj->udp_rss_v6) {
6643                 bnx2x_set_bit(ECORE_RSS_IPV6_UDP, &params.rss_flags);
6644         }
6645
6646         /* Hash bits */
6647         params.rss_result_mask = MULTI_MASK;
6648
6649         rte_memcpy(params.ind_table, rss_obj->ind_table,
6650                          sizeof(params.ind_table));
6651
6652         if (config_hash) {
6653 /* RSS keys */
6654                 for (i = 0; i < sizeof(params.rss_key) / 4; i++) {
6655                         params.rss_key[i] = (uint32_t) rte_rand();
6656                 }
6657
6658                 bnx2x_set_bit(ECORE_RSS_SET_SRCH, &params.rss_flags);
6659         }
6660
6661         if (IS_PF(sc))
6662                 return ecore_config_rss(sc, &params);
6663         else
6664                 return bnx2x_vf_config_rss(sc, &params);
6665 }
6666
6667 static int bnx2x_config_rss_eth(struct bnx2x_softc *sc, uint8_t config_hash)
6668 {
6669         return bnx2x_config_rss_pf(sc, &sc->rss_conf_obj, config_hash);
6670 }
6671
6672 static int bnx2x_init_rss_pf(struct bnx2x_softc *sc)
6673 {
6674         uint8_t num_eth_queues = BNX2X_NUM_ETH_QUEUES(sc);
6675         uint32_t i;
6676
6677         /*
6678          * Prepare the initial contents of the indirection table if
6679          * RSS is enabled
6680          */
6681         for (i = 0; i < sizeof(sc->rss_conf_obj.ind_table); i++) {
6682                 sc->rss_conf_obj.ind_table[i] =
6683                     (sc->fp->cl_id + (i % num_eth_queues));
6684         }
6685
6686         if (sc->udp_rss) {
6687                 sc->rss_conf_obj.udp_rss_v4 = sc->rss_conf_obj.udp_rss_v6 = 1;
6688         }
6689
6690         /*
6691          * For 57711 SEARCHER configuration (rss_keys) is
6692          * per-port, so if explicit configuration is needed, do it only
6693          * for a PMF.
6694          *
6695          * For 57712 and newer it's a per-function configuration.
6696          */
6697         return bnx2x_config_rss_eth(sc, sc->port.pmf || !CHIP_IS_E1x(sc));
6698 }
6699
6700 static int
6701 bnx2x_set_mac_one(struct bnx2x_softc *sc, uint8_t * mac,
6702                 struct ecore_vlan_mac_obj *obj, uint8_t set, int mac_type,
6703                 unsigned long *ramrod_flags)
6704 {
6705         struct ecore_vlan_mac_ramrod_params ramrod_param;
6706         int rc;
6707
6708         memset(&ramrod_param, 0, sizeof(ramrod_param));
6709
6710         /* fill in general parameters */
6711         ramrod_param.vlan_mac_obj = obj;
6712         ramrod_param.ramrod_flags = *ramrod_flags;
6713
6714         /* fill a user request section if needed */
6715         if (!bnx2x_test_bit(RAMROD_CONT, ramrod_flags)) {
6716                 rte_memcpy(ramrod_param.user_req.u.mac.mac, mac,
6717                                  ETH_ALEN);
6718
6719                 bnx2x_set_bit(mac_type, &ramrod_param.user_req.vlan_mac_flags);
6720
6721 /* Set the command: ADD or DEL */
6722                 ramrod_param.user_req.cmd = (set) ? ECORE_VLAN_MAC_ADD :
6723                     ECORE_VLAN_MAC_DEL;
6724         }
6725
6726         rc = ecore_config_vlan_mac(sc, &ramrod_param);
6727
6728         if (rc == ECORE_EXISTS) {
6729                 PMD_DRV_LOG(INFO, sc, "Failed to schedule ADD operations (EEXIST)");
6730 /* do not treat adding same MAC as error */
6731                 rc = 0;
6732         } else if (rc < 0) {
6733                 PMD_DRV_LOG(ERR, sc,
6734                             "%s MAC failed (%d)", (set ? "Set" : "Delete"), rc);
6735         }
6736
6737         return rc;
6738 }
6739
6740 static int bnx2x_set_eth_mac(struct bnx2x_softc *sc, uint8_t set)
6741 {
6742         unsigned long ramrod_flags = 0;
6743
6744         PMD_DRV_LOG(DEBUG, sc, "Adding Ethernet MAC");
6745
6746         bnx2x_set_bit(RAMROD_COMP_WAIT, &ramrod_flags);
6747
6748         /* Eth MAC is set on RSS leading client (fp[0]) */
6749         return bnx2x_set_mac_one(sc, sc->link_params.mac_addr,
6750                                &sc->sp_objs->mac_obj,
6751                                set, ECORE_ETH_MAC, &ramrod_flags);
6752 }
6753
6754 static int bnx2x_get_cur_phy_idx(struct bnx2x_softc *sc)
6755 {
6756         uint32_t sel_phy_idx = 0;
6757
6758         if (sc->link_params.num_phys <= 1) {
6759                 return ELINK_INT_PHY;
6760         }
6761
6762         if (sc->link_vars.link_up) {
6763                 sel_phy_idx = ELINK_EXT_PHY1;
6764 /* In case link is SERDES, check if the ELINK_EXT_PHY2 is the one */
6765                 if ((sc->link_vars.link_status & LINK_STATUS_SERDES_LINK) &&
6766                     (sc->link_params.phy[ELINK_EXT_PHY2].supported &
6767                      ELINK_SUPPORTED_FIBRE))
6768                         sel_phy_idx = ELINK_EXT_PHY2;
6769         } else {
6770                 switch (elink_phy_selection(&sc->link_params)) {
6771                 case PORT_HW_CFG_PHY_SELECTION_HARDWARE_DEFAULT:
6772                 case PORT_HW_CFG_PHY_SELECTION_FIRST_PHY:
6773                 case PORT_HW_CFG_PHY_SELECTION_FIRST_PHY_PRIORITY:
6774                         sel_phy_idx = ELINK_EXT_PHY1;
6775                         break;
6776                 case PORT_HW_CFG_PHY_SELECTION_SECOND_PHY:
6777                 case PORT_HW_CFG_PHY_SELECTION_SECOND_PHY_PRIORITY:
6778                         sel_phy_idx = ELINK_EXT_PHY2;
6779                         break;
6780                 }
6781         }
6782
6783         return sel_phy_idx;
6784 }
6785
6786 static int bnx2x_get_link_cfg_idx(struct bnx2x_softc *sc)
6787 {
6788         uint32_t sel_phy_idx = bnx2x_get_cur_phy_idx(sc);
6789
6790         /*
6791          * The selected activated PHY is always after swapping (in case PHY
6792          * swapping is enabled). So when swapping is enabled, we need to reverse
6793          * the configuration
6794          */
6795
6796         if (sc->link_params.multi_phy_config & PORT_HW_CFG_PHY_SWAPPED_ENABLED) {
6797                 if (sel_phy_idx == ELINK_EXT_PHY1)
6798                         sel_phy_idx = ELINK_EXT_PHY2;
6799                 else if (sel_phy_idx == ELINK_EXT_PHY2)
6800                         sel_phy_idx = ELINK_EXT_PHY1;
6801         }
6802
6803         return ELINK_LINK_CONFIG_IDX(sel_phy_idx);
6804 }
6805
6806 static void bnx2x_set_requested_fc(struct bnx2x_softc *sc)
6807 {
6808         /*
6809          * Initialize link parameters structure variables
6810          * It is recommended to turn off RX FC for jumbo frames
6811          * for better performance
6812          */
6813         if (CHIP_IS_E1x(sc) && (sc->mtu > 5000)) {
6814                 sc->link_params.req_fc_auto_adv = ELINK_FLOW_CTRL_TX;
6815         } else {
6816                 sc->link_params.req_fc_auto_adv = ELINK_FLOW_CTRL_BOTH;
6817         }
6818 }
6819
6820 static void bnx2x_calc_fc_adv(struct bnx2x_softc *sc)
6821 {
6822         uint8_t cfg_idx = bnx2x_get_link_cfg_idx(sc);
6823         switch (sc->link_vars.ieee_fc &
6824                 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_MASK) {
6825         case MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_NONE:
6826         default:
6827                 sc->port.advertising[cfg_idx] &= ~(ADVERTISED_Asym_Pause |
6828                                                    ADVERTISED_Pause);
6829                 break;
6830
6831         case MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH:
6832                 sc->port.advertising[cfg_idx] |= (ADVERTISED_Asym_Pause |
6833                                                   ADVERTISED_Pause);
6834                 break;
6835
6836         case MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC:
6837                 sc->port.advertising[cfg_idx] |= ADVERTISED_Asym_Pause;
6838                 break;
6839         }
6840 }
6841
6842 static uint16_t bnx2x_get_mf_speed(struct bnx2x_softc *sc)
6843 {
6844         uint16_t line_speed = sc->link_vars.line_speed;
6845         if (IS_MF(sc)) {
6846                 uint16_t maxCfg = bnx2x_extract_max_cfg(sc,
6847                                                       sc->devinfo.
6848                                                       mf_info.mf_config[SC_VN
6849                                                                         (sc)]);
6850
6851 /* calculate the current MAX line speed limit for the MF devices */
6852                 if (IS_MF_SI(sc)) {
6853                         line_speed = (line_speed * maxCfg) / 100;
6854                 } else {        /* SD mode */
6855                         uint16_t vn_max_rate = maxCfg * 100;
6856
6857                         if (vn_max_rate < line_speed) {
6858                                 line_speed = vn_max_rate;
6859                         }
6860                 }
6861         }
6862
6863         return line_speed;
6864 }
6865
6866 static void
6867 bnx2x_fill_report_data(struct bnx2x_softc *sc, struct bnx2x_link_report_data *data)
6868 {
6869         uint16_t line_speed = bnx2x_get_mf_speed(sc);
6870
6871         memset(data, 0, sizeof(*data));
6872
6873         /* fill the report data with the effective line speed */
6874         data->line_speed = line_speed;
6875
6876         /* Link is down */
6877         if (!sc->link_vars.link_up || (sc->flags & BNX2X_MF_FUNC_DIS)) {
6878                 bnx2x_set_bit(BNX2X_LINK_REPORT_LINK_DOWN,
6879                             &data->link_report_flags);
6880         }
6881
6882         /* Full DUPLEX */
6883         if (sc->link_vars.duplex == DUPLEX_FULL) {
6884                 bnx2x_set_bit(BNX2X_LINK_REPORT_FULL_DUPLEX,
6885                             &data->link_report_flags);
6886         }
6887
6888         /* Rx Flow Control is ON */
6889         if (sc->link_vars.flow_ctrl & ELINK_FLOW_CTRL_RX) {
6890                 bnx2x_set_bit(BNX2X_LINK_REPORT_RX_FC_ON, &data->link_report_flags);
6891         }
6892
6893         /* Tx Flow Control is ON */
6894         if (sc->link_vars.flow_ctrl & ELINK_FLOW_CTRL_TX) {
6895                 bnx2x_set_bit(BNX2X_LINK_REPORT_TX_FC_ON, &data->link_report_flags);
6896         }
6897 }
6898
6899 /* report link status to OS, should be called under phy_lock */
6900 static void bnx2x_link_report_locked(struct bnx2x_softc *sc)
6901 {
6902         struct bnx2x_link_report_data cur_data;
6903
6904         /* reread mf_cfg */
6905         if (IS_PF(sc)) {
6906                 bnx2x_read_mf_cfg(sc);
6907         }
6908
6909         /* Read the current link report info */
6910         bnx2x_fill_report_data(sc, &cur_data);
6911
6912         /* Don't report link down or exactly the same link status twice */
6913         if (!memcmp(&cur_data, &sc->last_reported_link, sizeof(cur_data)) ||
6914             (bnx2x_test_bit(BNX2X_LINK_REPORT_LINK_DOWN,
6915                           &sc->last_reported_link.link_report_flags) &&
6916              bnx2x_test_bit(BNX2X_LINK_REPORT_LINK_DOWN,
6917                           &cur_data.link_report_flags))) {
6918                 return;
6919         }
6920
6921         PMD_DRV_LOG(INFO, sc, "Change in link status : cur_data = %lx, last_reported_link = %lx\n",
6922                     cur_data.link_report_flags,
6923                     sc->last_reported_link.link_report_flags);
6924
6925         sc->link_cnt++;
6926
6927         PMD_DRV_LOG(INFO, sc, "link status change count = %x\n", sc->link_cnt);
6928         /* report new link params and remember the state for the next time */
6929         rte_memcpy(&sc->last_reported_link, &cur_data, sizeof(cur_data));
6930
6931         if (bnx2x_test_bit(BNX2X_LINK_REPORT_LINK_DOWN,
6932                          &cur_data.link_report_flags)) {
6933                 PMD_DRV_LOG(INFO, sc, "NIC Link is Down");
6934         } else {
6935                 __rte_unused const char *duplex;
6936                 __rte_unused const char *flow;
6937
6938                 if (bnx2x_test_and_clear_bit(BNX2X_LINK_REPORT_FULL_DUPLEX,
6939                                            &cur_data.link_report_flags)) {
6940                         duplex = "full";
6941                 } else {
6942                         duplex = "half";
6943                 }
6944
6945 /*
6946  * Handle the FC at the end so that only these flags would be
6947  * possibly set. This way we may easily check if there is no FC
6948  * enabled.
6949  */
6950                 if (cur_data.link_report_flags) {
6951                         if (bnx2x_test_bit(BNX2X_LINK_REPORT_RX_FC_ON,
6952                                          &cur_data.link_report_flags) &&
6953                             bnx2x_test_bit(BNX2X_LINK_REPORT_TX_FC_ON,
6954                                          &cur_data.link_report_flags)) {
6955                                 flow = "ON - receive & transmit";
6956                         } else if (bnx2x_test_bit(BNX2X_LINK_REPORT_RX_FC_ON,
6957                                                 &cur_data.link_report_flags) &&
6958                                    !bnx2x_test_bit(BNX2X_LINK_REPORT_TX_FC_ON,
6959                                                  &cur_data.link_report_flags)) {
6960                                 flow = "ON - receive";
6961                         } else if (!bnx2x_test_bit(BNX2X_LINK_REPORT_RX_FC_ON,
6962                                                  &cur_data.link_report_flags) &&
6963                                    bnx2x_test_bit(BNX2X_LINK_REPORT_TX_FC_ON,
6964                                                 &cur_data.link_report_flags)) {
6965                                 flow = "ON - transmit";
6966                         } else {
6967                                 flow = "none";  /* possible? */
6968                         }
6969                 } else {
6970                         flow = "none";
6971                 }
6972
6973                 PMD_DRV_LOG(INFO, sc,
6974                             "NIC Link is Up, %d Mbps %s duplex, Flow control: %s",
6975                             cur_data.line_speed, duplex, flow);
6976         }
6977 }
6978
6979 static void
6980 bnx2x_link_report(struct bnx2x_softc *sc)
6981 {
6982         bnx2x_acquire_phy_lock(sc);
6983         bnx2x_link_report_locked(sc);
6984         bnx2x_release_phy_lock(sc);
6985 }
6986
6987 void bnx2x_link_status_update(struct bnx2x_softc *sc)
6988 {
6989         if (sc->state != BNX2X_STATE_OPEN) {
6990                 return;
6991         }
6992
6993         if (IS_PF(sc) && !CHIP_REV_IS_SLOW(sc)) {
6994                 elink_link_status_update(&sc->link_params, &sc->link_vars);
6995         } else {
6996                 sc->port.supported[0] |= (ELINK_SUPPORTED_10baseT_Half |
6997                                           ELINK_SUPPORTED_10baseT_Full |
6998                                           ELINK_SUPPORTED_100baseT_Half |
6999                                           ELINK_SUPPORTED_100baseT_Full |
7000                                           ELINK_SUPPORTED_1000baseT_Full |
7001                                           ELINK_SUPPORTED_2500baseX_Full |
7002                                           ELINK_SUPPORTED_10000baseT_Full |
7003                                           ELINK_SUPPORTED_TP |
7004                                           ELINK_SUPPORTED_FIBRE |
7005                                           ELINK_SUPPORTED_Autoneg |
7006                                           ELINK_SUPPORTED_Pause |
7007                                           ELINK_SUPPORTED_Asym_Pause);
7008                 sc->port.advertising[0] = sc->port.supported[0];
7009
7010                 sc->link_params.sc = sc;
7011                 sc->link_params.port = SC_PORT(sc);
7012                 sc->link_params.req_duplex[0] = DUPLEX_FULL;
7013                 sc->link_params.req_flow_ctrl[0] = ELINK_FLOW_CTRL_NONE;
7014                 sc->link_params.req_line_speed[0] = SPEED_10000;
7015                 sc->link_params.speed_cap_mask[0] = 0x7f0000;
7016                 sc->link_params.switch_cfg = ELINK_SWITCH_CFG_10G;
7017
7018                 if (CHIP_REV_IS_FPGA(sc)) {
7019                         sc->link_vars.mac_type = ELINK_MAC_TYPE_EMAC;
7020                         sc->link_vars.line_speed = ELINK_SPEED_1000;
7021                         sc->link_vars.link_status = (LINK_STATUS_LINK_UP |
7022                                                      LINK_STATUS_SPEED_AND_DUPLEX_1000TFD);
7023                 } else {
7024                         sc->link_vars.mac_type = ELINK_MAC_TYPE_BMAC;
7025                         sc->link_vars.line_speed = ELINK_SPEED_10000;
7026                         sc->link_vars.link_status = (LINK_STATUS_LINK_UP |
7027                                                      LINK_STATUS_SPEED_AND_DUPLEX_10GTFD);
7028                 }
7029
7030                 sc->link_vars.link_up = 1;
7031
7032                 sc->link_vars.duplex = DUPLEX_FULL;
7033                 sc->link_vars.flow_ctrl = ELINK_FLOW_CTRL_NONE;
7034
7035                 if (IS_PF(sc)) {
7036                         REG_WR(sc,
7037                                NIG_REG_EGRESS_DRAIN0_MODE +
7038                                sc->link_params.port * 4, 0);
7039                         bnx2x_stats_handle(sc, STATS_EVENT_LINK_UP);
7040                         bnx2x_link_report(sc);
7041                 }
7042         }
7043
7044         if (IS_PF(sc)) {
7045                 if (sc->link_vars.link_up) {
7046                         bnx2x_stats_handle(sc, STATS_EVENT_LINK_UP);
7047                 } else {
7048                         bnx2x_stats_handle(sc, STATS_EVENT_STOP);
7049                 }
7050                 bnx2x_link_report(sc);
7051         } else {
7052                 bnx2x_link_report_locked(sc);
7053                 bnx2x_stats_handle(sc, STATS_EVENT_LINK_UP);
7054         }
7055 }
7056
7057 static int bnx2x_initial_phy_init(struct bnx2x_softc *sc, int load_mode)
7058 {
7059         int rc, cfg_idx = bnx2x_get_link_cfg_idx(sc);
7060         uint16_t req_line_speed = sc->link_params.req_line_speed[cfg_idx];
7061         struct elink_params *lp = &sc->link_params;
7062
7063         bnx2x_set_requested_fc(sc);
7064
7065         bnx2x_acquire_phy_lock(sc);
7066
7067         if (load_mode == LOAD_DIAG) {
7068                 lp->loopback_mode = ELINK_LOOPBACK_XGXS;
7069 /* Prefer doing PHY loopback at 10G speed, if possible */
7070                 if (lp->req_line_speed[cfg_idx] < ELINK_SPEED_10000) {
7071                         if (lp->speed_cap_mask[cfg_idx] &
7072                             PORT_HW_CFG_SPEED_CAPABILITY_D0_10G) {
7073                                 lp->req_line_speed[cfg_idx] = ELINK_SPEED_10000;
7074                         } else {
7075                                 lp->req_line_speed[cfg_idx] = ELINK_SPEED_1000;
7076                         }
7077                 }
7078         }
7079
7080         if (load_mode == LOAD_LOOPBACK_EXT) {
7081                 lp->loopback_mode = ELINK_LOOPBACK_EXT;
7082         }
7083
7084         rc = elink_phy_init(&sc->link_params, &sc->link_vars);
7085
7086         bnx2x_release_phy_lock(sc);
7087
7088         bnx2x_calc_fc_adv(sc);
7089
7090         if (sc->link_vars.link_up) {
7091                 bnx2x_stats_handle(sc, STATS_EVENT_LINK_UP);
7092                 bnx2x_link_report(sc);
7093         }
7094
7095         sc->link_params.req_line_speed[cfg_idx] = req_line_speed;
7096         return rc;
7097 }
7098
7099 /* update flags in shmem */
7100 static void
7101 bnx2x_update_drv_flags(struct bnx2x_softc *sc, uint32_t flags, uint32_t set)
7102 {
7103         uint32_t drv_flags;
7104
7105         if (SHMEM2_HAS(sc, drv_flags)) {
7106                 bnx2x_acquire_hw_lock(sc, HW_LOCK_RESOURCE_DRV_FLAGS);
7107                 drv_flags = SHMEM2_RD(sc, drv_flags);
7108
7109                 if (set) {
7110                         drv_flags |= flags;
7111                 } else {
7112                         drv_flags &= ~flags;
7113                 }
7114
7115                 SHMEM2_WR(sc, drv_flags, drv_flags);
7116
7117                 bnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_DRV_FLAGS);
7118         }
7119 }
7120
7121 /* periodic timer callout routine, only runs when the interface is up */
7122 void bnx2x_periodic_callout(struct bnx2x_softc *sc)
7123 {
7124         if ((sc->state != BNX2X_STATE_OPEN) ||
7125             (atomic_load_acq_long(&sc->periodic_flags) == PERIODIC_STOP)) {
7126                 PMD_DRV_LOG(INFO, sc, "periodic callout exit (state=0x%x)",
7127                             sc->state);
7128                 return;
7129         }
7130         if (!CHIP_REV_IS_SLOW(sc)) {
7131 /*
7132  * This barrier is needed to ensure the ordering between the writing
7133  * to the sc->port.pmf in the bnx2x_nic_load() or bnx2x_pmf_update() and
7134  * the reading here.
7135  */
7136                 mb();
7137                 if (sc->port.pmf) {
7138                         bnx2x_acquire_phy_lock(sc);
7139                         elink_period_func(&sc->link_params, &sc->link_vars);
7140                         bnx2x_release_phy_lock(sc);
7141                 }
7142         }
7143 #ifdef BNX2X_PULSE
7144         if (IS_PF(sc) && !BNX2X_NOMCP(sc)) {
7145                 int mb_idx = SC_FW_MB_IDX(sc);
7146                 uint32_t drv_pulse;
7147                 uint32_t mcp_pulse;
7148
7149                 ++sc->fw_drv_pulse_wr_seq;
7150                 sc->fw_drv_pulse_wr_seq &= DRV_PULSE_SEQ_MASK;
7151
7152                 drv_pulse = sc->fw_drv_pulse_wr_seq;
7153                 bnx2x_drv_pulse(sc);
7154
7155                 mcp_pulse = (SHMEM_RD(sc, func_mb[mb_idx].mcp_pulse_mb) &
7156                              MCP_PULSE_SEQ_MASK);
7157
7158 /*
7159  * The delta between driver pulse and mcp response should
7160  * be 1 (before mcp response) or 0 (after mcp response).
7161  */
7162                 if ((drv_pulse != mcp_pulse) &&
7163                     (drv_pulse != ((mcp_pulse + 1) & MCP_PULSE_SEQ_MASK))) {
7164                         /* someone lost a heartbeat... */
7165                         PMD_DRV_LOG(ERR, sc,
7166                                     "drv_pulse (0x%x) != mcp_pulse (0x%x)",
7167                                     drv_pulse, mcp_pulse);
7168                 }
7169         }
7170 #endif
7171 }
7172
7173 /* start the controller */
7174 static __rte_noinline
7175 int bnx2x_nic_load(struct bnx2x_softc *sc)
7176 {
7177         uint32_t val;
7178         uint32_t load_code = 0;
7179         int i, rc = 0;
7180
7181         PMD_INIT_FUNC_TRACE(sc);
7182
7183         sc->state = BNX2X_STATE_OPENING_WAITING_LOAD;
7184
7185         if (IS_PF(sc)) {
7186 /* must be called before memory allocation and HW init */
7187                 bnx2x_ilt_set_info(sc);
7188         }
7189
7190         bnx2x_set_fp_rx_buf_size(sc);
7191
7192         if (IS_PF(sc)) {
7193                 if (bnx2x_alloc_mem(sc) != 0) {
7194                         sc->state = BNX2X_STATE_CLOSED;
7195                         rc = -ENOMEM;
7196                         goto bnx2x_nic_load_error0;
7197                 }
7198         }
7199
7200         if (bnx2x_alloc_fw_stats_mem(sc) != 0) {
7201                 sc->state = BNX2X_STATE_CLOSED;
7202                 rc = -ENOMEM;
7203                 goto bnx2x_nic_load_error0;
7204         }
7205
7206         if (IS_VF(sc)) {
7207                 rc = bnx2x_vf_init(sc);
7208                 if (rc) {
7209                         sc->state = BNX2X_STATE_ERROR;
7210                         goto bnx2x_nic_load_error0;
7211                 }
7212         }
7213
7214         if (IS_PF(sc)) {
7215 /* set pf load just before approaching the MCP */
7216                 bnx2x_set_pf_load(sc);
7217
7218 /* if MCP exists send load request and analyze response */
7219                 if (!BNX2X_NOMCP(sc)) {
7220                         /* attempt to load pf */
7221                         if (bnx2x_nic_load_request(sc, &load_code) != 0) {
7222                                 sc->state = BNX2X_STATE_CLOSED;
7223                                 rc = -ENXIO;
7224                                 goto bnx2x_nic_load_error1;
7225                         }
7226
7227                         /* what did the MCP say? */
7228                         if (bnx2x_nic_load_analyze_req(sc, load_code) != 0) {
7229                                 bnx2x_fw_command(sc, DRV_MSG_CODE_LOAD_DONE, 0);
7230                                 sc->state = BNX2X_STATE_CLOSED;
7231                                 rc = -ENXIO;
7232                                 goto bnx2x_nic_load_error2;
7233                         }
7234                 } else {
7235                         PMD_DRV_LOG(INFO, sc, "Device has no MCP!");
7236                         load_code = bnx2x_nic_load_no_mcp(sc);
7237                 }
7238
7239 /* mark PMF if applicable */
7240                 bnx2x_nic_load_pmf(sc, load_code);
7241
7242 /* Init Function state controlling object */
7243                 bnx2x_init_func_obj(sc);
7244
7245 /* Initialize HW */
7246                 if (bnx2x_init_hw(sc, load_code) != 0) {
7247                         PMD_DRV_LOG(NOTICE, sc, "HW init failed");
7248                         bnx2x_fw_command(sc, DRV_MSG_CODE_LOAD_DONE, 0);
7249                         sc->state = BNX2X_STATE_CLOSED;
7250                         rc = -ENXIO;
7251                         goto bnx2x_nic_load_error2;
7252                 }
7253         }
7254
7255         bnx2x_nic_init(sc, load_code);
7256
7257         /* Init per-function objects */
7258         if (IS_PF(sc)) {
7259                 bnx2x_init_objs(sc);
7260
7261 /* set AFEX default VLAN tag to an invalid value */
7262                 sc->devinfo.mf_info.afex_def_vlan_tag = -1;
7263
7264                 sc->state = BNX2X_STATE_OPENING_WAITING_PORT;
7265                 rc = bnx2x_func_start(sc);
7266                 if (rc) {
7267                         PMD_DRV_LOG(NOTICE, sc, "Function start failed!");
7268                         bnx2x_fw_command(sc, DRV_MSG_CODE_LOAD_DONE, 0);
7269                         sc->state = BNX2X_STATE_ERROR;
7270                         goto bnx2x_nic_load_error3;
7271                 }
7272
7273 /* send LOAD_DONE command to MCP */
7274                 if (!BNX2X_NOMCP(sc)) {
7275                         load_code =
7276                             bnx2x_fw_command(sc, DRV_MSG_CODE_LOAD_DONE, 0);
7277                         if (!load_code) {
7278                                 PMD_DRV_LOG(NOTICE, sc,
7279                                             "MCP response failure, aborting");
7280                                 sc->state = BNX2X_STATE_ERROR;
7281                                 rc = -ENXIO;
7282                                 goto bnx2x_nic_load_error3;
7283                         }
7284                 }
7285         }
7286
7287         rc = bnx2x_setup_leading(sc);
7288         if (rc) {
7289                 PMD_DRV_LOG(NOTICE, sc, "Setup leading failed!");
7290                 sc->state = BNX2X_STATE_ERROR;
7291                 goto bnx2x_nic_load_error3;
7292         }
7293
7294         FOR_EACH_NONDEFAULT_ETH_QUEUE(sc, i) {
7295                 if (IS_PF(sc))
7296                         rc = bnx2x_setup_queue(sc, &sc->fp[i], FALSE);
7297                 else            /* IS_VF(sc) */
7298                         rc = bnx2x_vf_setup_queue(sc, &sc->fp[i], FALSE);
7299
7300                 if (rc) {
7301                         PMD_DRV_LOG(NOTICE, sc, "Queue(%d) setup failed", i);
7302                         sc->state = BNX2X_STATE_ERROR;
7303                         goto bnx2x_nic_load_error3;
7304                 }
7305         }
7306
7307         rc = bnx2x_init_rss_pf(sc);
7308         if (rc) {
7309                 PMD_DRV_LOG(NOTICE, sc, "PF RSS init failed");
7310                 sc->state = BNX2X_STATE_ERROR;
7311                 goto bnx2x_nic_load_error3;
7312         }
7313
7314         /* now when Clients are configured we are ready to work */
7315         sc->state = BNX2X_STATE_OPEN;
7316
7317         /* Configure a ucast MAC */
7318         if (IS_PF(sc)) {
7319                 rc = bnx2x_set_eth_mac(sc, TRUE);
7320         } else {                /* IS_VF(sc) */
7321                 rc = bnx2x_vf_set_mac(sc, TRUE);
7322         }
7323
7324         if (rc) {
7325                 PMD_DRV_LOG(NOTICE, sc, "Setting Ethernet MAC failed");
7326                 sc->state = BNX2X_STATE_ERROR;
7327                 goto bnx2x_nic_load_error3;
7328         }
7329
7330         if (sc->port.pmf) {
7331                 rc = bnx2x_initial_phy_init(sc, LOAD_OPEN);
7332                 if (rc) {
7333                         sc->state = BNX2X_STATE_ERROR;
7334                         goto bnx2x_nic_load_error3;
7335                 }
7336         }
7337
7338         sc->link_params.feature_config_flags &=
7339             ~ELINK_FEATURE_CONFIG_BOOT_FROM_SAN;
7340
7341         /* start the Tx */
7342         switch (LOAD_OPEN) {
7343         case LOAD_NORMAL:
7344         case LOAD_OPEN:
7345                 break;
7346
7347         case LOAD_DIAG:
7348         case LOAD_LOOPBACK_EXT:
7349                 sc->state = BNX2X_STATE_DIAG;
7350                 break;
7351
7352         default:
7353                 break;
7354         }
7355
7356         if (sc->port.pmf) {
7357                 bnx2x_update_drv_flags(sc, 1 << DRV_FLAGS_PORT_MASK, 0);
7358         } else {
7359                 bnx2x_link_status_update(sc);
7360         }
7361
7362         if (IS_PF(sc) && SHMEM2_HAS(sc, drv_capabilities_flag)) {
7363 /* mark driver is loaded in shmem2 */
7364                 val = SHMEM2_RD(sc, drv_capabilities_flag[SC_FW_MB_IDX(sc)]);
7365                 SHMEM2_WR(sc, drv_capabilities_flag[SC_FW_MB_IDX(sc)],
7366                           (val |
7367                            DRV_FLAGS_CAPABILITIES_LOADED_SUPPORTED |
7368                            DRV_FLAGS_CAPABILITIES_LOADED_L2));
7369         }
7370
7371         /* start fast path */
7372         /* Initialize Rx filter */
7373         bnx2x_set_rx_mode(sc);
7374
7375         /* wait for all pending SP commands to complete */
7376         if (IS_PF(sc) && !bnx2x_wait_sp_comp(sc, ~0x0UL)) {
7377                 PMD_DRV_LOG(NOTICE, sc, "Timeout waiting for all SPs to complete!");
7378                 bnx2x_periodic_stop(sc);
7379                 bnx2x_nic_unload(sc, UNLOAD_CLOSE, FALSE);
7380                 return -ENXIO;
7381         }
7382
7383         PMD_DRV_LOG(DEBUG, sc, "NIC successfully loaded");
7384
7385         return 0;
7386
7387 bnx2x_nic_load_error3:
7388
7389         if (IS_PF(sc)) {
7390                 bnx2x_int_disable_sync(sc, 1);
7391
7392 /* clean out queued objects */
7393                 bnx2x_squeeze_objects(sc);
7394         }
7395
7396 bnx2x_nic_load_error2:
7397
7398         if (IS_PF(sc) && !BNX2X_NOMCP(sc)) {
7399                 bnx2x_fw_command(sc, DRV_MSG_CODE_UNLOAD_REQ_WOL_MCP, 0);
7400                 bnx2x_fw_command(sc, DRV_MSG_CODE_UNLOAD_DONE, 0);
7401         }
7402
7403         sc->port.pmf = 0;
7404
7405 bnx2x_nic_load_error1:
7406
7407         /* clear pf_load status, as it was already set */
7408         if (IS_PF(sc)) {
7409                 bnx2x_clear_pf_load(sc);
7410         }
7411
7412 bnx2x_nic_load_error0:
7413
7414         bnx2x_free_fw_stats_mem(sc);
7415         bnx2x_free_mem(sc);
7416
7417         return rc;
7418 }
7419
7420 /*
7421 * Handles controller initialization.
7422 */
7423 int bnx2x_init(struct bnx2x_softc *sc)
7424 {
7425         int other_engine = SC_PATH(sc) ? 0 : 1;
7426         uint8_t other_load_status, load_status;
7427         uint8_t global = FALSE;
7428         int rc;
7429
7430         /* Check if the driver is still running and bail out if it is. */
7431         if (sc->state != BNX2X_STATE_CLOSED) {
7432                 PMD_DRV_LOG(DEBUG, sc, "Init called while driver is running!");
7433                 rc = 0;
7434                 goto bnx2x_init_done;
7435         }
7436
7437         bnx2x_set_power_state(sc, PCI_PM_D0);
7438
7439         /*
7440          * If parity occurred during the unload, then attentions and/or
7441          * RECOVERY_IN_PROGRESS may still be set. If so we want the first function
7442          * loaded on the current engine to complete the recovery. Parity recovery
7443          * is only relevant for PF driver.
7444          */
7445         if (IS_PF(sc)) {
7446                 other_load_status = bnx2x_get_load_status(sc, other_engine);
7447                 load_status = bnx2x_get_load_status(sc, SC_PATH(sc));
7448
7449                 if (!bnx2x_reset_is_done(sc, SC_PATH(sc)) ||
7450                     bnx2x_chk_parity_attn(sc, &global, TRUE)) {
7451                         do {
7452                                 /*
7453                                  * If there are attentions and they are in global blocks, set
7454                                  * the GLOBAL_RESET bit regardless whether it will be this
7455                                  * function that will complete the recovery or not.
7456                                  */
7457                                 if (global) {
7458                                         bnx2x_set_reset_global(sc);
7459                                 }
7460
7461                                 /*
7462                                  * Only the first function on the current engine should try
7463                                  * to recover in open. In case of attentions in global blocks
7464                                  * only the first in the chip should try to recover.
7465                                  */
7466                                 if ((!load_status
7467                                      && (!global ||!other_load_status))
7468                                     && bnx2x_trylock_leader_lock(sc)
7469                                     && !bnx2x_leader_reset(sc)) {
7470                                         PMD_DRV_LOG(INFO, sc,
7471                                                     "Recovered during init");
7472                                         break;
7473                                 }
7474
7475                                 /* recovery has failed... */
7476                                 bnx2x_set_power_state(sc, PCI_PM_D3hot);
7477
7478                                 sc->recovery_state = BNX2X_RECOVERY_FAILED;
7479
7480                                 PMD_DRV_LOG(NOTICE, sc,
7481                                             "Recovery flow hasn't properly "
7482                                             "completed yet, try again later. "
7483                                             "If you still see this message after a "
7484                                             "few retries then power cycle is required.");
7485
7486                                 rc = -ENXIO;
7487                                 goto bnx2x_init_done;
7488                         } while (0);
7489                 }
7490         }
7491
7492         sc->recovery_state = BNX2X_RECOVERY_DONE;
7493
7494         rc = bnx2x_nic_load(sc);
7495
7496 bnx2x_init_done:
7497
7498         if (rc) {
7499                 PMD_DRV_LOG(NOTICE, sc, "Initialization failed, "
7500                             "stack notified driver is NOT running!");
7501         }
7502
7503         return rc;
7504 }
7505
7506 static void bnx2x_get_function_num(struct bnx2x_softc *sc)
7507 {
7508         uint32_t val = 0;
7509
7510         /*
7511          * Read the ME register to get the function number. The ME register
7512          * holds the relative-function number and absolute-function number. The
7513          * absolute-function number appears only in E2 and above. Before that
7514          * these bits always contained zero, therefore we cannot blindly use them.
7515          */
7516
7517         val = REG_RD(sc, BAR_ME_REGISTER);
7518
7519         sc->pfunc_rel =
7520             (uint8_t) ((val & ME_REG_PF_NUM) >> ME_REG_PF_NUM_SHIFT);
7521         sc->path_id =
7522             (uint8_t) ((val & ME_REG_ABS_PF_NUM) >> ME_REG_ABS_PF_NUM_SHIFT) &
7523             1;
7524
7525         if (CHIP_PORT_MODE(sc) == CHIP_4_PORT_MODE) {
7526                 sc->pfunc_abs = ((sc->pfunc_rel << 1) | sc->path_id);
7527         } else {
7528                 sc->pfunc_abs = (sc->pfunc_rel | sc->path_id);
7529         }
7530
7531         PMD_DRV_LOG(DEBUG, sc,
7532                     "Relative function %d, Absolute function %d, Path %d",
7533                     sc->pfunc_rel, sc->pfunc_abs, sc->path_id);
7534 }
7535
7536 static uint32_t bnx2x_get_shmem_mf_cfg_base(struct bnx2x_softc *sc)
7537 {
7538         uint32_t shmem2_size;
7539         uint32_t offset;
7540         uint32_t mf_cfg_offset_value;
7541
7542         /* Non 57712 */
7543         offset = (SHMEM_ADDR(sc, func_mb) +
7544                   (MAX_FUNC_NUM * sizeof(struct drv_func_mb)));
7545
7546         /* 57712 plus */
7547         if (sc->devinfo.shmem2_base != 0) {
7548                 shmem2_size = SHMEM2_RD(sc, size);
7549                 if (shmem2_size > offsetof(struct shmem2_region, mf_cfg_addr)) {
7550                         mf_cfg_offset_value = SHMEM2_RD(sc, mf_cfg_addr);
7551                         if (SHMEM_MF_CFG_ADDR_NONE != mf_cfg_offset_value) {
7552                                 offset = mf_cfg_offset_value;
7553                         }
7554                 }
7555         }
7556
7557         return offset;
7558 }
7559
7560 static uint32_t bnx2x_pcie_capability_read(struct bnx2x_softc *sc, int reg)
7561 {
7562         uint32_t ret;
7563         struct bnx2x_pci_cap *caps;
7564
7565         /* ensure PCIe capability is enabled */
7566         caps = pci_find_cap(sc, PCIY_EXPRESS, BNX2X_PCI_CAP);
7567         if (NULL != caps) {
7568                 PMD_DRV_LOG(DEBUG, sc, "Found PCIe capability: "
7569                             "id=0x%04X type=0x%04X addr=0x%08X",
7570                             caps->id, caps->type, caps->addr);
7571                 pci_read(sc, (caps->addr + reg), &ret, 2);
7572                 return ret;
7573         }
7574
7575         PMD_DRV_LOG(WARNING, sc, "PCIe capability NOT FOUND!!!");
7576
7577         return 0;
7578 }
7579
7580 static uint8_t bnx2x_is_pcie_pending(struct bnx2x_softc *sc)
7581 {
7582         return bnx2x_pcie_capability_read(sc, PCIR_EXPRESS_DEVICE_STA) &
7583                 PCIM_EXP_STA_TRANSACTION_PND;
7584 }
7585
7586 /*
7587 * Walk the PCI capabiites list for the device to find what features are
7588 * supported. These capabilites may be enabled/disabled by firmware so it's
7589 * best to walk the list rather than make assumptions.
7590 */
7591 static void bnx2x_probe_pci_caps(struct bnx2x_softc *sc)
7592 {
7593         PMD_INIT_FUNC_TRACE(sc);
7594
7595         struct bnx2x_pci_cap *caps;
7596         uint16_t link_status;
7597         int reg = 0;
7598
7599         /* check if PCI Power Management is enabled */
7600         caps = pci_find_cap(sc, PCIY_PMG, BNX2X_PCI_CAP);
7601         if (NULL != caps) {
7602                 PMD_DRV_LOG(DEBUG, sc, "Found PM capability: "
7603                             "id=0x%04X type=0x%04X addr=0x%08X",
7604                             caps->id, caps->type, caps->addr);
7605
7606                 sc->devinfo.pcie_cap_flags |= BNX2X_PM_CAPABLE_FLAG;
7607                 sc->devinfo.pcie_pm_cap_reg = caps->addr;
7608         }
7609
7610         link_status = bnx2x_pcie_capability_read(sc, PCIR_EXPRESS_LINK_STA);
7611
7612         sc->devinfo.pcie_link_speed = (link_status & PCIM_LINK_STA_SPEED);
7613         sc->devinfo.pcie_link_width =
7614             ((link_status & PCIM_LINK_STA_WIDTH) >> 4);
7615
7616         PMD_DRV_LOG(DEBUG, sc, "PCIe link speed=%d width=%d",
7617                     sc->devinfo.pcie_link_speed, sc->devinfo.pcie_link_width);
7618
7619         sc->devinfo.pcie_cap_flags |= BNX2X_PCIE_CAPABLE_FLAG;
7620
7621         /* check if MSI capability is enabled */
7622         caps = pci_find_cap(sc, PCIY_MSI, BNX2X_PCI_CAP);
7623         if (NULL != caps) {
7624                 PMD_DRV_LOG(DEBUG, sc, "Found MSI capability at 0x%04x", reg);
7625
7626                 sc->devinfo.pcie_cap_flags |= BNX2X_MSI_CAPABLE_FLAG;
7627                 sc->devinfo.pcie_msi_cap_reg = caps->addr;
7628         }
7629
7630         /* check if MSI-X capability is enabled */
7631         caps = pci_find_cap(sc, PCIY_MSIX, BNX2X_PCI_CAP);
7632         if (NULL != caps) {
7633                 PMD_DRV_LOG(DEBUG, sc, "Found MSI-X capability at 0x%04x", reg);
7634
7635                 sc->devinfo.pcie_cap_flags |= BNX2X_MSIX_CAPABLE_FLAG;
7636                 sc->devinfo.pcie_msix_cap_reg = caps->addr;
7637         }
7638 }
7639
7640 static int bnx2x_get_shmem_mf_cfg_info_sd(struct bnx2x_softc *sc)
7641 {
7642         struct bnx2x_mf_info *mf_info = &sc->devinfo.mf_info;
7643         uint32_t val;
7644
7645         /* get the outer vlan if we're in switch-dependent mode */
7646
7647         val = MFCFG_RD(sc, func_mf_config[SC_ABS_FUNC(sc)].e1hov_tag);
7648         mf_info->ext_id = (uint16_t) val;
7649
7650         mf_info->multi_vnics_mode = 1;
7651
7652         if (!VALID_OVLAN(mf_info->ext_id)) {
7653                 PMD_DRV_LOG(NOTICE, sc, "Invalid VLAN (%d)", mf_info->ext_id);
7654                 return 1;
7655         }
7656
7657         /* get the capabilities */
7658         if ((mf_info->mf_config[SC_VN(sc)] & FUNC_MF_CFG_PROTOCOL_MASK) ==
7659             FUNC_MF_CFG_PROTOCOL_ISCSI) {
7660                 mf_info->mf_protos_supported |= MF_PROTO_SUPPORT_ISCSI;
7661         } else if ((mf_info->mf_config[SC_VN(sc)] & FUNC_MF_CFG_PROTOCOL_MASK)
7662                    == FUNC_MF_CFG_PROTOCOL_FCOE) {
7663                 mf_info->mf_protos_supported |= MF_PROTO_SUPPORT_FCOE;
7664         } else {
7665                 mf_info->mf_protos_supported |= MF_PROTO_SUPPORT_ETHERNET;
7666         }
7667
7668         mf_info->vnics_per_port =
7669             (CHIP_PORT_MODE(sc) == CHIP_4_PORT_MODE) ? 2 : 4;
7670
7671         return 0;
7672 }
7673
7674 static uint32_t bnx2x_get_shmem_ext_proto_support_flags(struct bnx2x_softc *sc)
7675 {
7676         uint32_t retval = 0;
7677         uint32_t val;
7678
7679         val = MFCFG_RD(sc, func_ext_config[SC_ABS_FUNC(sc)].func_cfg);
7680
7681         if (val & MACP_FUNC_CFG_FLAGS_ENABLED) {
7682                 if (val & MACP_FUNC_CFG_FLAGS_ETHERNET) {
7683                         retval |= MF_PROTO_SUPPORT_ETHERNET;
7684                 }
7685                 if (val & MACP_FUNC_CFG_FLAGS_ISCSI_OFFLOAD) {
7686                         retval |= MF_PROTO_SUPPORT_ISCSI;
7687                 }
7688                 if (val & MACP_FUNC_CFG_FLAGS_FCOE_OFFLOAD) {
7689                         retval |= MF_PROTO_SUPPORT_FCOE;
7690                 }
7691         }
7692
7693         return retval;
7694 }
7695
7696 static int bnx2x_get_shmem_mf_cfg_info_si(struct bnx2x_softc *sc)
7697 {
7698         struct bnx2x_mf_info *mf_info = &sc->devinfo.mf_info;
7699         uint32_t val;
7700
7701         /*
7702          * There is no outer vlan if we're in switch-independent mode.
7703          * If the mac is valid then assume multi-function.
7704          */
7705
7706         val = MFCFG_RD(sc, func_ext_config[SC_ABS_FUNC(sc)].func_cfg);
7707
7708         mf_info->multi_vnics_mode = ((val & MACP_FUNC_CFG_FLAGS_MASK) != 0);
7709
7710         mf_info->mf_protos_supported =
7711             bnx2x_get_shmem_ext_proto_support_flags(sc);
7712
7713         mf_info->vnics_per_port =
7714             (CHIP_PORT_MODE(sc) == CHIP_4_PORT_MODE) ? 2 : 4;
7715
7716         return 0;
7717 }
7718
7719 static int bnx2x_get_shmem_mf_cfg_info_niv(struct bnx2x_softc *sc)
7720 {
7721         struct bnx2x_mf_info *mf_info = &sc->devinfo.mf_info;
7722         uint32_t e1hov_tag;
7723         uint32_t func_config;
7724         uint32_t niv_config;
7725
7726         mf_info->multi_vnics_mode = 1;
7727
7728         e1hov_tag = MFCFG_RD(sc, func_mf_config[SC_ABS_FUNC(sc)].e1hov_tag);
7729         func_config = MFCFG_RD(sc, func_mf_config[SC_ABS_FUNC(sc)].config);
7730         niv_config = MFCFG_RD(sc, func_mf_config[SC_ABS_FUNC(sc)].afex_config);
7731
7732         mf_info->ext_id =
7733             (uint16_t) ((e1hov_tag & FUNC_MF_CFG_E1HOV_TAG_MASK) >>
7734                         FUNC_MF_CFG_E1HOV_TAG_SHIFT);
7735
7736         mf_info->default_vlan =
7737             (uint16_t) ((e1hov_tag & FUNC_MF_CFG_AFEX_VLAN_MASK) >>
7738                         FUNC_MF_CFG_AFEX_VLAN_SHIFT);
7739
7740         mf_info->niv_allowed_priorities =
7741             (uint8_t) ((niv_config & FUNC_MF_CFG_AFEX_COS_FILTER_MASK) >>
7742                        FUNC_MF_CFG_AFEX_COS_FILTER_SHIFT);
7743
7744         mf_info->niv_default_cos =
7745             (uint8_t) ((func_config & FUNC_MF_CFG_TRANSMIT_PRIORITY_MASK) >>
7746                        FUNC_MF_CFG_TRANSMIT_PRIORITY_SHIFT);
7747
7748         mf_info->afex_vlan_mode =
7749             ((niv_config & FUNC_MF_CFG_AFEX_VLAN_MODE_MASK) >>
7750              FUNC_MF_CFG_AFEX_VLAN_MODE_SHIFT);
7751
7752         mf_info->niv_mba_enabled =
7753             ((niv_config & FUNC_MF_CFG_AFEX_MBA_ENABLED_MASK) >>
7754              FUNC_MF_CFG_AFEX_MBA_ENABLED_SHIFT);
7755
7756         mf_info->mf_protos_supported =
7757             bnx2x_get_shmem_ext_proto_support_flags(sc);
7758
7759         mf_info->vnics_per_port =
7760             (CHIP_PORT_MODE(sc) == CHIP_4_PORT_MODE) ? 2 : 4;
7761
7762         return 0;
7763 }
7764
7765 static int bnx2x_check_valid_mf_cfg(struct bnx2x_softc *sc)
7766 {
7767         struct bnx2x_mf_info *mf_info = &sc->devinfo.mf_info;
7768         uint32_t mf_cfg1;
7769         uint32_t mf_cfg2;
7770         uint32_t ovlan1;
7771         uint32_t ovlan2;
7772         uint8_t i, j;
7773
7774         /* various MF mode sanity checks... */
7775
7776         if (mf_info->mf_config[SC_VN(sc)] & FUNC_MF_CFG_FUNC_HIDE) {
7777                 PMD_DRV_LOG(NOTICE, sc,
7778                             "Enumerated function %d is marked as hidden",
7779                             SC_PORT(sc));
7780                 return 1;
7781         }
7782
7783         if ((mf_info->vnics_per_port > 1) && !mf_info->multi_vnics_mode) {
7784                 PMD_DRV_LOG(NOTICE, sc, "vnics_per_port=%d multi_vnics_mode=%d",
7785                             mf_info->vnics_per_port, mf_info->multi_vnics_mode);
7786                 return 1;
7787         }
7788
7789         if (mf_info->mf_mode == MULTI_FUNCTION_SD) {
7790 /* vnic id > 0 must have valid ovlan in switch-dependent mode */
7791                 if ((SC_VN(sc) > 0) && !VALID_OVLAN(OVLAN(sc))) {
7792                         PMD_DRV_LOG(NOTICE, sc, "mf_mode=SD vnic_id=%d ovlan=%d",
7793                                     SC_VN(sc), OVLAN(sc));
7794                         return 1;
7795                 }
7796
7797                 if (!VALID_OVLAN(OVLAN(sc)) && mf_info->multi_vnics_mode) {
7798                         PMD_DRV_LOG(NOTICE, sc,
7799                                     "mf_mode=SD multi_vnics_mode=%d ovlan=%d",
7800                                     mf_info->multi_vnics_mode, OVLAN(sc));
7801                         return 1;
7802                 }
7803
7804 /*
7805  * Verify all functions are either MF or SF mode. If MF, make sure
7806  * sure that all non-hidden functions have a valid ovlan. If SF,
7807  * make sure that all non-hidden functions have an invalid ovlan.
7808  */
7809                 FOREACH_ABS_FUNC_IN_PORT(sc, i) {
7810                         mf_cfg1 = MFCFG_RD(sc, func_mf_config[i].config);
7811                         ovlan1 = MFCFG_RD(sc, func_mf_config[i].e1hov_tag);
7812                         if (!(mf_cfg1 & FUNC_MF_CFG_FUNC_HIDE) &&
7813                             (((mf_info->multi_vnics_mode)
7814                               && !VALID_OVLAN(ovlan1))
7815                              || ((!mf_info->multi_vnics_mode)
7816                                  && VALID_OVLAN(ovlan1)))) {
7817                                 PMD_DRV_LOG(NOTICE, sc,
7818                                             "mf_mode=SD function %d MF config "
7819                                             "mismatch, multi_vnics_mode=%d ovlan=%d",
7820                                             i, mf_info->multi_vnics_mode,
7821                                             ovlan1);
7822                                 return 1;
7823                         }
7824                 }
7825
7826 /* Verify all funcs on the same port each have a different ovlan. */
7827                 FOREACH_ABS_FUNC_IN_PORT(sc, i) {
7828                         mf_cfg1 = MFCFG_RD(sc, func_mf_config[i].config);
7829                         ovlan1 = MFCFG_RD(sc, func_mf_config[i].e1hov_tag);
7830                         /* iterate from the next function on the port to the max func */
7831                         for (j = i + 2; j < MAX_FUNC_NUM; j += 2) {
7832                                 mf_cfg2 =
7833                                     MFCFG_RD(sc, func_mf_config[j].config);
7834                                 ovlan2 =
7835                                     MFCFG_RD(sc, func_mf_config[j].e1hov_tag);
7836                                 if (!(mf_cfg1 & FUNC_MF_CFG_FUNC_HIDE)
7837                                     && VALID_OVLAN(ovlan1)
7838                                     && !(mf_cfg2 & FUNC_MF_CFG_FUNC_HIDE)
7839                                     && VALID_OVLAN(ovlan2)
7840                                     && (ovlan1 == ovlan2)) {
7841                                         PMD_DRV_LOG(NOTICE, sc,
7842                                                     "mf_mode=SD functions %d and %d "
7843                                                     "have the same ovlan (%d)",
7844                                                     i, j, ovlan1);
7845                                         return 1;
7846                                 }
7847                         }
7848                 }
7849         }
7850         /* MULTI_FUNCTION_SD */
7851         return 0;
7852 }
7853
7854 static int bnx2x_get_mf_cfg_info(struct bnx2x_softc *sc)
7855 {
7856         struct bnx2x_mf_info *mf_info = &sc->devinfo.mf_info;
7857         uint32_t val, mac_upper;
7858         uint8_t i, vnic;
7859
7860         /* initialize mf_info defaults */
7861         mf_info->vnics_per_port = 1;
7862         mf_info->multi_vnics_mode = FALSE;
7863         mf_info->path_has_ovlan = FALSE;
7864         mf_info->mf_mode = SINGLE_FUNCTION;
7865
7866         if (!CHIP_IS_MF_CAP(sc)) {
7867                 return 0;
7868         }
7869
7870         if (sc->devinfo.mf_cfg_base == SHMEM_MF_CFG_ADDR_NONE) {
7871                 PMD_DRV_LOG(NOTICE, sc, "Invalid mf_cfg_base!");
7872                 return 1;
7873         }
7874
7875         /* get the MF mode (switch dependent / independent / single-function) */
7876
7877         val = SHMEM_RD(sc, dev_info.shared_feature_config.config);
7878
7879         switch (val & SHARED_FEAT_CFG_FORCE_SF_MODE_MASK) {
7880         case SHARED_FEAT_CFG_FORCE_SF_MODE_SWITCH_INDEPT:
7881
7882                 mac_upper =
7883                     MFCFG_RD(sc, func_mf_config[SC_ABS_FUNC(sc)].mac_upper);
7884
7885                 /* check for legal upper mac bytes */
7886                 if (mac_upper != FUNC_MF_CFG_UPPERMAC_DEFAULT) {
7887                         mf_info->mf_mode = MULTI_FUNCTION_SI;
7888                 } else {
7889                         PMD_DRV_LOG(NOTICE, sc,
7890                                     "Invalid config for Switch Independent mode");
7891                 }
7892
7893                 break;
7894
7895         case SHARED_FEAT_CFG_FORCE_SF_MODE_MF_ALLOWED:
7896         case SHARED_FEAT_CFG_FORCE_SF_MODE_SPIO4:
7897
7898                 /* get outer vlan configuration */
7899                 val = MFCFG_RD(sc, func_mf_config[SC_ABS_FUNC(sc)].e1hov_tag);
7900
7901                 if ((val & FUNC_MF_CFG_E1HOV_TAG_MASK) !=
7902                     FUNC_MF_CFG_E1HOV_TAG_DEFAULT) {
7903                         mf_info->mf_mode = MULTI_FUNCTION_SD;
7904                 } else {
7905                         PMD_DRV_LOG(NOTICE, sc,
7906                                     "Invalid config for Switch Dependent mode");
7907                 }
7908
7909                 break;
7910
7911         case SHARED_FEAT_CFG_FORCE_SF_MODE_FORCED_SF:
7912
7913                 /* not in MF mode, vnics_per_port=1 and multi_vnics_mode=FALSE */
7914                 return 0;
7915
7916         case SHARED_FEAT_CFG_FORCE_SF_MODE_AFEX_MODE:
7917
7918                 /*
7919                  * Mark MF mode as NIV if MCP version includes NPAR-SD support
7920                  * and the MAC address is valid.
7921                  */
7922                 mac_upper =
7923                     MFCFG_RD(sc, func_mf_config[SC_ABS_FUNC(sc)].mac_upper);
7924
7925                 if ((SHMEM2_HAS(sc, afex_driver_support)) &&
7926                     (mac_upper != FUNC_MF_CFG_UPPERMAC_DEFAULT)) {
7927                         mf_info->mf_mode = MULTI_FUNCTION_AFEX;
7928                 } else {
7929                         PMD_DRV_LOG(NOTICE, sc, "Invalid config for AFEX mode");
7930                 }
7931
7932                 break;
7933
7934         default:
7935
7936                 PMD_DRV_LOG(NOTICE, sc, "Unknown MF mode (0x%08x)",
7937                             (val & SHARED_FEAT_CFG_FORCE_SF_MODE_MASK));
7938
7939                 return 1;
7940         }
7941
7942         /* set path mf_mode (which could be different than function mf_mode) */
7943         if (mf_info->mf_mode == MULTI_FUNCTION_SD) {
7944                 mf_info->path_has_ovlan = TRUE;
7945         } else if (mf_info->mf_mode == SINGLE_FUNCTION) {
7946 /*
7947  * Decide on path multi vnics mode. If we're not in MF mode and in
7948  * 4-port mode, this is good enough to check vnic-0 of the other port
7949  * on the same path
7950  */
7951                 if (CHIP_PORT_MODE(sc) == CHIP_4_PORT_MODE) {
7952                         uint8_t other_port = !(PORT_ID(sc) & 1);
7953                         uint8_t abs_func_other_port =
7954                             (SC_PATH(sc) + (2 * other_port));
7955
7956                         val =
7957                             MFCFG_RD(sc,
7958                                      func_mf_config
7959                                      [abs_func_other_port].e1hov_tag);
7960
7961                         mf_info->path_has_ovlan = VALID_OVLAN((uint16_t) val);
7962                 }
7963         }
7964
7965         if (mf_info->mf_mode == SINGLE_FUNCTION) {
7966 /* invalid MF config */
7967                 if (SC_VN(sc) >= 1) {
7968                         PMD_DRV_LOG(NOTICE, sc, "VNIC ID >= 1 in SF mode");
7969                         return 1;
7970                 }
7971
7972                 return 0;
7973         }
7974
7975         /* get the MF configuration */
7976         mf_info->mf_config[SC_VN(sc)] =
7977             MFCFG_RD(sc, func_mf_config[SC_ABS_FUNC(sc)].config);
7978
7979         switch (mf_info->mf_mode) {
7980         case MULTI_FUNCTION_SD:
7981
7982                 bnx2x_get_shmem_mf_cfg_info_sd(sc);
7983                 break;
7984
7985         case MULTI_FUNCTION_SI:
7986
7987                 bnx2x_get_shmem_mf_cfg_info_si(sc);
7988                 break;
7989
7990         case MULTI_FUNCTION_AFEX:
7991
7992                 bnx2x_get_shmem_mf_cfg_info_niv(sc);
7993                 break;
7994
7995         default:
7996
7997                 PMD_DRV_LOG(NOTICE, sc, "Get MF config failed (mf_mode=0x%08x)",
7998                             mf_info->mf_mode);
7999                 return 1;
8000         }
8001
8002         /* get the congestion management parameters */
8003
8004         vnic = 0;
8005         FOREACH_ABS_FUNC_IN_PORT(sc, i) {
8006 /* get min/max bw */
8007                 val = MFCFG_RD(sc, func_mf_config[i].config);
8008                 mf_info->min_bw[vnic] =
8009                     ((val & FUNC_MF_CFG_MIN_BW_MASK) >>
8010                      FUNC_MF_CFG_MIN_BW_SHIFT);
8011                 mf_info->max_bw[vnic] =
8012                     ((val & FUNC_MF_CFG_MAX_BW_MASK) >>
8013                      FUNC_MF_CFG_MAX_BW_SHIFT);
8014                 vnic++;
8015         }
8016
8017         return bnx2x_check_valid_mf_cfg(sc);
8018 }
8019
8020 static int bnx2x_get_shmem_info(struct bnx2x_softc *sc)
8021 {
8022         int port;
8023         uint32_t mac_hi, mac_lo, val;
8024
8025         PMD_INIT_FUNC_TRACE(sc);
8026
8027         port = SC_PORT(sc);
8028         mac_hi = mac_lo = 0;
8029
8030         sc->link_params.sc = sc;
8031         sc->link_params.port = port;
8032
8033         /* get the hardware config info */
8034         sc->devinfo.hw_config = SHMEM_RD(sc, dev_info.shared_hw_config.config);
8035         sc->devinfo.hw_config2 =
8036             SHMEM_RD(sc, dev_info.shared_hw_config.config2);
8037
8038         sc->link_params.hw_led_mode =
8039             ((sc->devinfo.hw_config & SHARED_HW_CFG_LED_MODE_MASK) >>
8040              SHARED_HW_CFG_LED_MODE_SHIFT);
8041
8042         /* get the port feature config */
8043         sc->port.config =
8044             SHMEM_RD(sc, dev_info.port_feature_config[port].config);
8045
8046         /* get the link params */
8047         sc->link_params.speed_cap_mask[ELINK_INT_PHY] =
8048             SHMEM_RD(sc, dev_info.port_hw_config[port].speed_capability_mask)
8049             & PORT_HW_CFG_SPEED_CAPABILITY_D0_MASK;
8050         sc->link_params.speed_cap_mask[ELINK_EXT_PHY1] =
8051             SHMEM_RD(sc, dev_info.port_hw_config[port].speed_capability_mask2)
8052             & PORT_HW_CFG_SPEED_CAPABILITY_D0_MASK;
8053
8054         /* get the lane config */
8055         sc->link_params.lane_config =
8056             SHMEM_RD(sc, dev_info.port_hw_config[port].lane_config);
8057
8058         /* get the link config */
8059         val = SHMEM_RD(sc, dev_info.port_feature_config[port].link_config);
8060         sc->port.link_config[ELINK_INT_PHY] = val;
8061         sc->link_params.switch_cfg = (val & PORT_FEATURE_CONNECTED_SWITCH_MASK);
8062         sc->port.link_config[ELINK_EXT_PHY1] =
8063             SHMEM_RD(sc, dev_info.port_feature_config[port].link_config2);
8064
8065         /* get the override preemphasis flag and enable it or turn it off */
8066         val = SHMEM_RD(sc, dev_info.shared_feature_config.config);
8067         if (val & SHARED_FEAT_CFG_OVERRIDE_PREEMPHASIS_CFG_ENABLED) {
8068                 sc->link_params.feature_config_flags |=
8069                     ELINK_FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED;
8070         } else {
8071                 sc->link_params.feature_config_flags &=
8072                     ~ELINK_FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED;
8073         }
8074
8075         /* get the initial value of the link params */
8076         sc->link_params.multi_phy_config =
8077             SHMEM_RD(sc, dev_info.port_hw_config[port].multi_phy_config);
8078
8079         /* get external phy info */
8080         sc->port.ext_phy_config =
8081             SHMEM_RD(sc, dev_info.port_hw_config[port].external_phy_config);
8082
8083         /* get the multifunction configuration */
8084         bnx2x_get_mf_cfg_info(sc);
8085
8086         /* get the mac address */
8087         if (IS_MF(sc)) {
8088                 mac_hi =
8089                     MFCFG_RD(sc, func_mf_config[SC_ABS_FUNC(sc)].mac_upper);
8090                 mac_lo =
8091                     MFCFG_RD(sc, func_mf_config[SC_ABS_FUNC(sc)].mac_lower);
8092         } else {
8093                 mac_hi = SHMEM_RD(sc, dev_info.port_hw_config[port].mac_upper);
8094                 mac_lo = SHMEM_RD(sc, dev_info.port_hw_config[port].mac_lower);
8095         }
8096
8097         if ((mac_lo == 0) && (mac_hi == 0)) {
8098                 *sc->mac_addr_str = 0;
8099                 PMD_DRV_LOG(NOTICE, sc, "No Ethernet address programmed!");
8100         } else {
8101                 sc->link_params.mac_addr[0] = (uint8_t) (mac_hi >> 8);
8102                 sc->link_params.mac_addr[1] = (uint8_t) (mac_hi);
8103                 sc->link_params.mac_addr[2] = (uint8_t) (mac_lo >> 24);
8104                 sc->link_params.mac_addr[3] = (uint8_t) (mac_lo >> 16);
8105                 sc->link_params.mac_addr[4] = (uint8_t) (mac_lo >> 8);
8106                 sc->link_params.mac_addr[5] = (uint8_t) (mac_lo);
8107                 snprintf(sc->mac_addr_str, sizeof(sc->mac_addr_str),
8108                          "%02x:%02x:%02x:%02x:%02x:%02x",
8109                          sc->link_params.mac_addr[0],
8110                          sc->link_params.mac_addr[1],
8111                          sc->link_params.mac_addr[2],
8112                          sc->link_params.mac_addr[3],
8113                          sc->link_params.mac_addr[4],
8114                          sc->link_params.mac_addr[5]);
8115                 PMD_DRV_LOG(DEBUG, sc,
8116                             "Ethernet address: %s", sc->mac_addr_str);
8117         }
8118
8119         return 0;
8120 }
8121
8122 static void bnx2x_media_detect(struct bnx2x_softc *sc)
8123 {
8124         uint32_t phy_idx = bnx2x_get_cur_phy_idx(sc);
8125         switch (sc->link_params.phy[phy_idx].media_type) {
8126         case ELINK_ETH_PHY_SFPP_10G_FIBER:
8127         case ELINK_ETH_PHY_SFP_1G_FIBER:
8128         case ELINK_ETH_PHY_XFP_FIBER:
8129         case ELINK_ETH_PHY_KR:
8130         case ELINK_ETH_PHY_CX4:
8131                 PMD_DRV_LOG(INFO, sc, "Found 10GBase-CX4 media.");
8132                 sc->media = IFM_10G_CX4;
8133                 break;
8134         case ELINK_ETH_PHY_DA_TWINAX:
8135                 PMD_DRV_LOG(INFO, sc, "Found 10Gb Twinax media.");
8136                 sc->media = IFM_10G_TWINAX;
8137                 break;
8138         case ELINK_ETH_PHY_BASE_T:
8139                 PMD_DRV_LOG(INFO, sc, "Found 10GBase-T media.");
8140                 sc->media = IFM_10G_T;
8141                 break;
8142         case ELINK_ETH_PHY_NOT_PRESENT:
8143                 PMD_DRV_LOG(INFO, sc, "Media not present.");
8144                 sc->media = 0;
8145                 break;
8146         case ELINK_ETH_PHY_UNSPECIFIED:
8147         default:
8148                 PMD_DRV_LOG(INFO, sc, "Unknown media!");
8149                 sc->media = 0;
8150                 break;
8151         }
8152 }
8153
8154 #define GET_FIELD(value, fname)                     \
8155 (((value) & (fname##_MASK)) >> (fname##_SHIFT))
8156 #define IGU_FID(val) GET_FIELD((val), IGU_REG_MAPPING_MEMORY_FID)
8157 #define IGU_VEC(val) GET_FIELD((val), IGU_REG_MAPPING_MEMORY_VECTOR)
8158
8159 static int bnx2x_get_igu_cam_info(struct bnx2x_softc *sc)
8160 {
8161         int pfid = SC_FUNC(sc);
8162         int igu_sb_id;
8163         uint32_t val;
8164         uint8_t fid, igu_sb_cnt = 0;
8165
8166         sc->igu_base_sb = 0xff;
8167
8168         if (CHIP_INT_MODE_IS_BC(sc)) {
8169                 int vn = SC_VN(sc);
8170                 igu_sb_cnt = sc->igu_sb_cnt;
8171                 sc->igu_base_sb = ((CHIP_IS_MODE_4_PORT(sc) ? pfid : vn) *
8172                                    FP_SB_MAX_E1x);
8173                 sc->igu_dsb_id = (E1HVN_MAX * FP_SB_MAX_E1x +
8174                                   (CHIP_IS_MODE_4_PORT(sc) ? pfid : vn));
8175                 return 0;
8176         }
8177
8178         /* IGU in normal mode - read CAM */
8179         for (igu_sb_id = 0;
8180              igu_sb_id < IGU_REG_MAPPING_MEMORY_SIZE; igu_sb_id++) {
8181                 val = REG_RD(sc, IGU_REG_MAPPING_MEMORY + igu_sb_id * 4);
8182                 if (!(val & IGU_REG_MAPPING_MEMORY_VALID)) {
8183                         continue;
8184                 }
8185                 fid = IGU_FID(val);
8186                 if (fid & IGU_FID_ENCODE_IS_PF) {
8187                         if ((fid & IGU_FID_PF_NUM_MASK) != pfid) {
8188                                 continue;
8189                         }
8190                         if (IGU_VEC(val) == 0) {
8191                                 /* default status block */
8192                                 sc->igu_dsb_id = igu_sb_id;
8193                         } else {
8194                                 if (sc->igu_base_sb == 0xff) {
8195                                         sc->igu_base_sb = igu_sb_id;
8196                                 }
8197                                 igu_sb_cnt++;
8198                         }
8199                 }
8200         }
8201
8202         /*
8203          * Due to new PF resource allocation by MFW T7.4 and above, it's optional
8204          * that number of CAM entries will not be equal to the value advertised in
8205          * PCI. Driver should use the minimal value of both as the actual status
8206          * block count
8207          */
8208         sc->igu_sb_cnt = min(sc->igu_sb_cnt, igu_sb_cnt);
8209
8210         if (igu_sb_cnt == 0) {
8211                 PMD_DRV_LOG(ERR, sc, "CAM configuration error");
8212                 return -1;
8213         }
8214
8215         return 0;
8216 }
8217
8218 /*
8219 * Gather various information from the device config space, the device itself,
8220 * shmem, and the user input.
8221 */
8222 static int bnx2x_get_device_info(struct bnx2x_softc *sc)
8223 {
8224         uint32_t val;
8225         int rc;
8226
8227         /* get the chip revision (chip metal comes from pci config space) */
8228         sc->devinfo.chip_id = sc->link_params.chip_id =
8229             (((REG_RD(sc, MISC_REG_CHIP_NUM) & 0xffff) << 16) |
8230              ((REG_RD(sc, MISC_REG_CHIP_REV) & 0xf) << 12) |
8231              (((REG_RD(sc, PCICFG_OFFSET + PCI_ID_VAL3) >> 24) & 0xf) << 4) |
8232              ((REG_RD(sc, MISC_REG_BOND_ID) & 0xf) << 0));
8233
8234         /* force 57811 according to MISC register */
8235         if (REG_RD(sc, MISC_REG_CHIP_TYPE) & MISC_REG_CHIP_TYPE_57811_MASK) {
8236                 if (CHIP_IS_57810(sc)) {
8237                         sc->devinfo.chip_id = ((CHIP_NUM_57811 << 16) |
8238                                                (sc->
8239                                                 devinfo.chip_id & 0x0000ffff));
8240                 } else if (CHIP_IS_57810_MF(sc)) {
8241                         sc->devinfo.chip_id = ((CHIP_NUM_57811_MF << 16) |
8242                                                (sc->
8243                                                 devinfo.chip_id & 0x0000ffff));
8244                 }
8245                 sc->devinfo.chip_id |= 0x1;
8246         }
8247
8248         PMD_DRV_LOG(DEBUG, sc,
8249                     "chip_id=0x%08x (num=0x%04x rev=0x%01x metal=0x%02x bond=0x%01x)",
8250                     sc->devinfo.chip_id,
8251                     ((sc->devinfo.chip_id >> 16) & 0xffff),
8252                     ((sc->devinfo.chip_id >> 12) & 0xf),
8253                     ((sc->devinfo.chip_id >> 4) & 0xff),
8254                     ((sc->devinfo.chip_id >> 0) & 0xf));
8255
8256         val = (REG_RD(sc, 0x2874) & 0x55);
8257         if ((sc->devinfo.chip_id & 0x1) || (CHIP_IS_E1H(sc) && (val == 0x55))) {
8258                 sc->flags |= BNX2X_ONE_PORT_FLAG;
8259                 PMD_DRV_LOG(DEBUG, sc, "single port device");
8260         }
8261
8262         /* set the doorbell size */
8263         sc->doorbell_size = (1 << BNX2X_DB_SHIFT);
8264
8265         /* determine whether the device is in 2 port or 4 port mode */
8266         sc->devinfo.chip_port_mode = CHIP_PORT_MODE_NONE;       /* E1h */
8267         if (CHIP_IS_E2E3(sc)) {
8268 /*
8269  * Read port4mode_en_ovwr[0]:
8270  *   If 1, four port mode is in port4mode_en_ovwr[1].
8271  *   If 0, four port mode is in port4mode_en[0].
8272  */
8273                 val = REG_RD(sc, MISC_REG_PORT4MODE_EN_OVWR);
8274                 if (val & 1) {
8275                         val = ((val >> 1) & 1);
8276                 } else {
8277                         val = REG_RD(sc, MISC_REG_PORT4MODE_EN);
8278                 }
8279
8280                 sc->devinfo.chip_port_mode =
8281                     (val) ? CHIP_4_PORT_MODE : CHIP_2_PORT_MODE;
8282
8283                 PMD_DRV_LOG(DEBUG, sc, "Port mode = %s", (val) ? "4" : "2");
8284         }
8285
8286         /* get the function and path info for the device */
8287         bnx2x_get_function_num(sc);
8288
8289         /* get the shared memory base address */
8290         sc->devinfo.shmem_base =
8291             sc->link_params.shmem_base = REG_RD(sc, MISC_REG_SHARED_MEM_ADDR);
8292         sc->devinfo.shmem2_base =
8293             REG_RD(sc, (SC_PATH(sc) ? MISC_REG_GENERIC_CR_1 :
8294                         MISC_REG_GENERIC_CR_0));
8295
8296         if (!sc->devinfo.shmem_base) {
8297 /* this should ONLY prevent upcoming shmem reads */
8298                 PMD_DRV_LOG(INFO, sc, "MCP not active");
8299                 sc->flags |= BNX2X_NO_MCP_FLAG;
8300                 return 0;
8301         }
8302
8303         /* make sure the shared memory contents are valid */
8304         val = SHMEM_RD(sc, validity_map[SC_PORT(sc)]);
8305         if ((val & (SHR_MEM_VALIDITY_DEV_INFO | SHR_MEM_VALIDITY_MB)) !=
8306             (SHR_MEM_VALIDITY_DEV_INFO | SHR_MEM_VALIDITY_MB)) {
8307                 PMD_DRV_LOG(NOTICE, sc, "Invalid SHMEM validity signature: 0x%08x",
8308                             val);
8309                 return 0;
8310         }
8311
8312         /* get the bootcode version */
8313         sc->devinfo.bc_ver = SHMEM_RD(sc, dev_info.bc_rev);
8314         snprintf(sc->devinfo.bc_ver_str,
8315                  sizeof(sc->devinfo.bc_ver_str),
8316                  "%d.%d.%d",
8317                  ((sc->devinfo.bc_ver >> 24) & 0xff),
8318                  ((sc->devinfo.bc_ver >> 16) & 0xff),
8319                  ((sc->devinfo.bc_ver >> 8) & 0xff));
8320         PMD_DRV_LOG(INFO, sc, "Bootcode version: %s", sc->devinfo.bc_ver_str);
8321
8322         /* get the bootcode shmem address */
8323         sc->devinfo.mf_cfg_base = bnx2x_get_shmem_mf_cfg_base(sc);
8324
8325         /* clean indirect addresses as they're not used */
8326         pci_write_long(sc, PCICFG_GRC_ADDRESS, 0);
8327         if (IS_PF(sc)) {
8328                 REG_WR(sc, PXP2_REG_PGL_ADDR_88_F0, 0);
8329                 REG_WR(sc, PXP2_REG_PGL_ADDR_8C_F0, 0);
8330                 REG_WR(sc, PXP2_REG_PGL_ADDR_90_F0, 0);
8331                 REG_WR(sc, PXP2_REG_PGL_ADDR_94_F0, 0);
8332                 if (CHIP_IS_E1x(sc)) {
8333                         REG_WR(sc, PXP2_REG_PGL_ADDR_88_F1, 0);
8334                         REG_WR(sc, PXP2_REG_PGL_ADDR_8C_F1, 0);
8335                         REG_WR(sc, PXP2_REG_PGL_ADDR_90_F1, 0);
8336                         REG_WR(sc, PXP2_REG_PGL_ADDR_94_F1, 0);
8337                 }
8338         }
8339
8340         /* get the nvram size */
8341         val = REG_RD(sc, MCP_REG_MCPR_NVM_CFG4);
8342         sc->devinfo.flash_size =
8343             (NVRAM_1MB_SIZE << (val & MCPR_NVM_CFG4_FLASH_SIZE));
8344
8345         bnx2x_set_power_state(sc, PCI_PM_D0);
8346         /* get various configuration parameters from shmem */
8347         bnx2x_get_shmem_info(sc);
8348
8349         /* initialize IGU parameters */
8350         if (CHIP_IS_E1x(sc)) {
8351                 sc->devinfo.int_block = INT_BLOCK_HC;
8352                 sc->igu_dsb_id = DEF_SB_IGU_ID;
8353                 sc->igu_base_sb = 0;
8354         } else {
8355                 sc->devinfo.int_block = INT_BLOCK_IGU;
8356
8357 /* do not allow device reset during IGU info preocessing */
8358                 bnx2x_acquire_hw_lock(sc, HW_LOCK_RESOURCE_RESET);
8359
8360                 val = REG_RD(sc, IGU_REG_BLOCK_CONFIGURATION);
8361
8362                 if (val & IGU_BLOCK_CONFIGURATION_REG_BACKWARD_COMP_EN) {
8363                         int tout = 5000;
8364
8365                         val &= ~(IGU_BLOCK_CONFIGURATION_REG_BACKWARD_COMP_EN);
8366                         REG_WR(sc, IGU_REG_BLOCK_CONFIGURATION, val);
8367                         REG_WR(sc, IGU_REG_RESET_MEMORIES, 0x7f);
8368
8369                         while (tout && REG_RD(sc, IGU_REG_RESET_MEMORIES)) {
8370                                 tout--;
8371                                 DELAY(1000);
8372                         }
8373
8374                         if (REG_RD(sc, IGU_REG_RESET_MEMORIES)) {
8375                                 PMD_DRV_LOG(NOTICE, sc,
8376                                             "FORCING IGU Normal Mode failed!!!");
8377                                 bnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_RESET);
8378                                 return -1;
8379                         }
8380                 }
8381
8382                 if (val & IGU_BLOCK_CONFIGURATION_REG_BACKWARD_COMP_EN) {
8383                         PMD_DRV_LOG(DEBUG, sc, "IGU Backward Compatible Mode");
8384                         sc->devinfo.int_block |= INT_BLOCK_MODE_BW_COMP;
8385                 } else {
8386                         PMD_DRV_LOG(DEBUG, sc, "IGU Normal Mode");
8387                 }
8388
8389                 rc = bnx2x_get_igu_cam_info(sc);
8390
8391                 bnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_RESET);
8392
8393                 if (rc) {
8394                         return rc;
8395                 }
8396         }
8397
8398         /*
8399          * Get base FW non-default (fast path) status block ID. This value is
8400          * used to initialize the fw_sb_id saved on the fp/queue structure to
8401          * determine the id used by the FW.
8402          */
8403         if (CHIP_IS_E1x(sc)) {
8404                 sc->base_fw_ndsb =
8405                     ((SC_PORT(sc) * FP_SB_MAX_E1x) + SC_L_ID(sc));
8406         } else {
8407 /*
8408  * 57712+ - We currently use one FW SB per IGU SB (Rx and Tx of
8409  * the same queue are indicated on the same IGU SB). So we prefer
8410  * FW and IGU SBs to be the same value.
8411  */
8412                 sc->base_fw_ndsb = sc->igu_base_sb;
8413         }
8414
8415         elink_phy_probe(&sc->link_params);
8416
8417         return 0;
8418 }
8419
8420 static void
8421 bnx2x_link_settings_supported(struct bnx2x_softc *sc, uint32_t switch_cfg)
8422 {
8423         uint32_t cfg_size = 0;
8424         uint32_t idx;
8425         uint8_t port = SC_PORT(sc);
8426
8427         /* aggregation of supported attributes of all external phys */
8428         sc->port.supported[0] = 0;
8429         sc->port.supported[1] = 0;
8430
8431         switch (sc->link_params.num_phys) {
8432         case 1:
8433                 sc->port.supported[0] =
8434                     sc->link_params.phy[ELINK_INT_PHY].supported;
8435                 cfg_size = 1;
8436                 break;
8437         case 2:
8438                 sc->port.supported[0] =
8439                     sc->link_params.phy[ELINK_EXT_PHY1].supported;
8440                 cfg_size = 1;
8441                 break;
8442         case 3:
8443                 if (sc->link_params.multi_phy_config &
8444                     PORT_HW_CFG_PHY_SWAPPED_ENABLED) {
8445                         sc->port.supported[1] =
8446                             sc->link_params.phy[ELINK_EXT_PHY1].supported;
8447                         sc->port.supported[0] =
8448                             sc->link_params.phy[ELINK_EXT_PHY2].supported;
8449                 } else {
8450                         sc->port.supported[0] =
8451                             sc->link_params.phy[ELINK_EXT_PHY1].supported;
8452                         sc->port.supported[1] =
8453                             sc->link_params.phy[ELINK_EXT_PHY2].supported;
8454                 }
8455                 cfg_size = 2;
8456                 break;
8457         }
8458
8459         if (!(sc->port.supported[0] || sc->port.supported[1])) {
8460                 PMD_DRV_LOG(ERR, sc,
8461                             "Invalid phy config in NVRAM (PHY1=0x%08x PHY2=0x%08x)",
8462                             SHMEM_RD(sc,
8463                                      dev_info.port_hw_config
8464                                      [port].external_phy_config),
8465                             SHMEM_RD(sc,
8466                                      dev_info.port_hw_config
8467                                      [port].external_phy_config2));
8468                 return;
8469         }
8470
8471         if (CHIP_IS_E3(sc))
8472                 sc->port.phy_addr = REG_RD(sc, MISC_REG_WC0_CTRL_PHY_ADDR);
8473         else {
8474                 switch (switch_cfg) {
8475                 case ELINK_SWITCH_CFG_1G:
8476                         sc->port.phy_addr =
8477                             REG_RD(sc,
8478                                    NIG_REG_SERDES0_CTRL_PHY_ADDR + port * 0x10);
8479                         break;
8480                 case ELINK_SWITCH_CFG_10G:
8481                         sc->port.phy_addr =
8482                             REG_RD(sc,
8483                                    NIG_REG_XGXS0_CTRL_PHY_ADDR + port * 0x18);
8484                         break;
8485                 default:
8486                         PMD_DRV_LOG(ERR, sc,
8487                                     "Invalid switch config in"
8488                                     "link_config=0x%08x",
8489                                     sc->port.link_config[0]);
8490                         return;
8491                 }
8492         }
8493
8494         PMD_DRV_LOG(INFO, sc, "PHY addr 0x%08x", sc->port.phy_addr);
8495
8496         /* mask what we support according to speed_cap_mask per configuration */
8497         for (idx = 0; idx < cfg_size; idx++) {
8498                 if (!(sc->link_params.speed_cap_mask[idx] &
8499                       PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_HALF)) {
8500                         sc->port.supported[idx] &=
8501                             ~ELINK_SUPPORTED_10baseT_Half;
8502                 }
8503
8504                 if (!(sc->link_params.speed_cap_mask[idx] &
8505                       PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL)) {
8506                         sc->port.supported[idx] &=
8507                             ~ELINK_SUPPORTED_10baseT_Full;
8508                 }
8509
8510                 if (!(sc->link_params.speed_cap_mask[idx] &
8511                       PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_HALF)) {
8512                         sc->port.supported[idx] &=
8513                             ~ELINK_SUPPORTED_100baseT_Half;
8514                 }
8515
8516                 if (!(sc->link_params.speed_cap_mask[idx] &
8517                       PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_FULL)) {
8518                         sc->port.supported[idx] &=
8519                             ~ELINK_SUPPORTED_100baseT_Full;
8520                 }
8521
8522                 if (!(sc->link_params.speed_cap_mask[idx] &
8523                       PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)) {
8524                         sc->port.supported[idx] &=
8525                             ~ELINK_SUPPORTED_1000baseT_Full;
8526                 }
8527
8528                 if (!(sc->link_params.speed_cap_mask[idx] &
8529                       PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G)) {
8530                         sc->port.supported[idx] &=
8531                             ~ELINK_SUPPORTED_2500baseX_Full;
8532                 }
8533
8534                 if (!(sc->link_params.speed_cap_mask[idx] &
8535                       PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)) {
8536                         sc->port.supported[idx] &=
8537                             ~ELINK_SUPPORTED_10000baseT_Full;
8538                 }
8539
8540                 if (!(sc->link_params.speed_cap_mask[idx] &
8541                       PORT_HW_CFG_SPEED_CAPABILITY_D0_20G)) {
8542                         sc->port.supported[idx] &=
8543                             ~ELINK_SUPPORTED_20000baseKR2_Full;
8544                 }
8545         }
8546
8547         PMD_DRV_LOG(INFO, sc, "PHY supported 0=0x%08x 1=0x%08x",
8548                     sc->port.supported[0], sc->port.supported[1]);
8549 }
8550
8551 static void bnx2x_link_settings_requested(struct bnx2x_softc *sc)
8552 {
8553         uint32_t link_config;
8554         uint32_t idx;
8555         uint32_t cfg_size = 0;
8556
8557         sc->port.advertising[0] = 0;
8558         sc->port.advertising[1] = 0;
8559
8560         switch (sc->link_params.num_phys) {
8561         case 1:
8562         case 2:
8563                 cfg_size = 1;
8564                 break;
8565         case 3:
8566                 cfg_size = 2;
8567                 break;
8568         }
8569
8570         for (idx = 0; idx < cfg_size; idx++) {
8571                 sc->link_params.req_duplex[idx] = DUPLEX_FULL;
8572                 link_config = sc->port.link_config[idx];
8573
8574                 switch (link_config & PORT_FEATURE_LINK_SPEED_MASK) {
8575                 case PORT_FEATURE_LINK_SPEED_AUTO:
8576                         if (sc->port.supported[idx] & ELINK_SUPPORTED_Autoneg) {
8577                                 sc->link_params.req_line_speed[idx] =
8578                                     ELINK_SPEED_AUTO_NEG;
8579                                 sc->port.advertising[idx] |=
8580                                     sc->port.supported[idx];
8581                                 if (sc->link_params.phy[ELINK_EXT_PHY1].type ==
8582                                     PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X84833)
8583                                         sc->port.advertising[idx] |=
8584                                             (ELINK_SUPPORTED_100baseT_Half |
8585                                              ELINK_SUPPORTED_100baseT_Full);
8586                         } else {
8587                                 /* force 10G, no AN */
8588                                 sc->link_params.req_line_speed[idx] =
8589                                     ELINK_SPEED_10000;
8590                                 sc->port.advertising[idx] |=
8591                                     (ADVERTISED_10000baseT_Full |
8592                                      ADVERTISED_FIBRE);
8593                                 continue;
8594                         }
8595                         break;
8596
8597                 case PORT_FEATURE_LINK_SPEED_10M_FULL:
8598                         if (sc->
8599                             port.supported[idx] & ELINK_SUPPORTED_10baseT_Full)
8600                         {
8601                                 sc->link_params.req_line_speed[idx] =
8602                                     ELINK_SPEED_10;
8603                                 sc->port.advertising[idx] |=
8604                                     (ADVERTISED_10baseT_Full | ADVERTISED_TP);
8605                         } else {
8606                                 PMD_DRV_LOG(ERR, sc,
8607                                             "Invalid NVRAM config link_config=0x%08x "
8608                                             "speed_cap_mask=0x%08x",
8609                                             link_config,
8610                                             sc->
8611                                             link_params.speed_cap_mask[idx]);
8612                                 return;
8613                         }
8614                         break;
8615
8616                 case PORT_FEATURE_LINK_SPEED_10M_HALF:
8617                         if (sc->
8618                             port.supported[idx] & ELINK_SUPPORTED_10baseT_Half)
8619                         {
8620                                 sc->link_params.req_line_speed[idx] =
8621                                     ELINK_SPEED_10;
8622                                 sc->link_params.req_duplex[idx] = DUPLEX_HALF;
8623                                 sc->port.advertising[idx] |=
8624                                     (ADVERTISED_10baseT_Half | ADVERTISED_TP);
8625                         } else {
8626                                 PMD_DRV_LOG(ERR, sc,
8627                                             "Invalid NVRAM config link_config=0x%08x "
8628                                             "speed_cap_mask=0x%08x",
8629                                             link_config,
8630                                             sc->
8631                                             link_params.speed_cap_mask[idx]);
8632                                 return;
8633                         }
8634                         break;
8635
8636                 case PORT_FEATURE_LINK_SPEED_100M_FULL:
8637                         if (sc->
8638                             port.supported[idx] & ELINK_SUPPORTED_100baseT_Full)
8639                         {
8640                                 sc->link_params.req_line_speed[idx] =
8641                                     ELINK_SPEED_100;
8642                                 sc->port.advertising[idx] |=
8643                                     (ADVERTISED_100baseT_Full | ADVERTISED_TP);
8644                         } else {
8645                                 PMD_DRV_LOG(ERR, sc,
8646                                             "Invalid NVRAM config link_config=0x%08x "
8647                                             "speed_cap_mask=0x%08x",
8648                                             link_config,
8649                                             sc->
8650                                             link_params.speed_cap_mask[idx]);
8651                                 return;
8652                         }
8653                         break;
8654
8655                 case PORT_FEATURE_LINK_SPEED_100M_HALF:
8656                         if (sc->
8657                             port.supported[idx] & ELINK_SUPPORTED_100baseT_Half)
8658                         {
8659                                 sc->link_params.req_line_speed[idx] =
8660                                     ELINK_SPEED_100;
8661                                 sc->link_params.req_duplex[idx] = DUPLEX_HALF;
8662                                 sc->port.advertising[idx] |=
8663                                     (ADVERTISED_100baseT_Half | ADVERTISED_TP);
8664                         } else {
8665                                 PMD_DRV_LOG(ERR, sc,
8666                                             "Invalid NVRAM config link_config=0x%08x "
8667                                             "speed_cap_mask=0x%08x",
8668                                             link_config,
8669                                             sc->
8670                                             link_params.speed_cap_mask[idx]);
8671                                 return;
8672                         }
8673                         break;
8674
8675                 case PORT_FEATURE_LINK_SPEED_1G:
8676                         if (sc->port.supported[idx] &
8677                             ELINK_SUPPORTED_1000baseT_Full) {
8678                                 sc->link_params.req_line_speed[idx] =
8679                                     ELINK_SPEED_1000;
8680                                 sc->port.advertising[idx] |=
8681                                     (ADVERTISED_1000baseT_Full | ADVERTISED_TP);
8682                         } else {
8683                                 PMD_DRV_LOG(ERR, sc,
8684                                             "Invalid NVRAM config link_config=0x%08x "
8685                                             "speed_cap_mask=0x%08x",
8686                                             link_config,
8687                                             sc->
8688                                             link_params.speed_cap_mask[idx]);
8689                                 return;
8690                         }
8691                         break;
8692
8693                 case PORT_FEATURE_LINK_SPEED_2_5G:
8694                         if (sc->port.supported[idx] &
8695                             ELINK_SUPPORTED_2500baseX_Full) {
8696                                 sc->link_params.req_line_speed[idx] =
8697                                     ELINK_SPEED_2500;
8698                                 sc->port.advertising[idx] |=
8699                                     (ADVERTISED_2500baseX_Full | ADVERTISED_TP);
8700                         } else {
8701                                 PMD_DRV_LOG(ERR, sc,
8702                                             "Invalid NVRAM config link_config=0x%08x "
8703                                             "speed_cap_mask=0x%08x",
8704                                             link_config,
8705                                             sc->
8706                                             link_params.speed_cap_mask[idx]);
8707                                 return;
8708                         }
8709                         break;
8710
8711                 case PORT_FEATURE_LINK_SPEED_10G_CX4:
8712                         if (sc->port.supported[idx] &
8713                             ELINK_SUPPORTED_10000baseT_Full) {
8714                                 sc->link_params.req_line_speed[idx] =
8715                                     ELINK_SPEED_10000;
8716                                 sc->port.advertising[idx] |=
8717                                     (ADVERTISED_10000baseT_Full |
8718                                      ADVERTISED_FIBRE);
8719                         } else {
8720                                 PMD_DRV_LOG(ERR, sc,
8721                                             "Invalid NVRAM config link_config=0x%08x "
8722                                             "speed_cap_mask=0x%08x",
8723                                             link_config,
8724                                             sc->
8725                                             link_params.speed_cap_mask[idx]);
8726                                 return;
8727                         }
8728                         break;
8729
8730                 case PORT_FEATURE_LINK_SPEED_20G:
8731                         sc->link_params.req_line_speed[idx] = ELINK_SPEED_20000;
8732                         break;
8733
8734                 default:
8735                         PMD_DRV_LOG(ERR, sc,
8736                                     "Invalid NVRAM config link_config=0x%08x "
8737                                     "speed_cap_mask=0x%08x", link_config,
8738                                     sc->link_params.speed_cap_mask[idx]);
8739                         sc->link_params.req_line_speed[idx] =
8740                             ELINK_SPEED_AUTO_NEG;
8741                         sc->port.advertising[idx] = sc->port.supported[idx];
8742                         break;
8743                 }
8744
8745                 sc->link_params.req_flow_ctrl[idx] =
8746                     (link_config & PORT_FEATURE_FLOW_CONTROL_MASK);
8747
8748                 if (sc->link_params.req_flow_ctrl[idx] == ELINK_FLOW_CTRL_AUTO) {
8749                         if (!
8750                             (sc->
8751                              port.supported[idx] & ELINK_SUPPORTED_Autoneg)) {
8752                                 sc->link_params.req_flow_ctrl[idx] =
8753                                     ELINK_FLOW_CTRL_NONE;
8754                         } else {
8755                                 bnx2x_set_requested_fc(sc);
8756                         }
8757                 }
8758         }
8759 }
8760
8761 static void bnx2x_get_phy_info(struct bnx2x_softc *sc)
8762 {
8763         uint8_t port = SC_PORT(sc);
8764         uint32_t eee_mode;
8765
8766         PMD_INIT_FUNC_TRACE(sc);
8767
8768         /* shmem data already read in bnx2x_get_shmem_info() */
8769
8770         bnx2x_link_settings_supported(sc, sc->link_params.switch_cfg);
8771         bnx2x_link_settings_requested(sc);
8772
8773         /* configure link feature according to nvram value */
8774         eee_mode =
8775             (((SHMEM_RD(sc, dev_info.port_feature_config[port].eee_power_mode))
8776               & PORT_FEAT_CFG_EEE_POWER_MODE_MASK) >>
8777              PORT_FEAT_CFG_EEE_POWER_MODE_SHIFT);
8778         if (eee_mode != PORT_FEAT_CFG_EEE_POWER_MODE_DISABLED) {
8779                 sc->link_params.eee_mode = (ELINK_EEE_MODE_ADV_LPI |
8780                                             ELINK_EEE_MODE_ENABLE_LPI |
8781                                             ELINK_EEE_MODE_OUTPUT_TIME);
8782         } else {
8783                 sc->link_params.eee_mode = 0;
8784         }
8785
8786         /* get the media type */
8787         bnx2x_media_detect(sc);
8788 }
8789
8790 static void bnx2x_set_modes_bitmap(struct bnx2x_softc *sc)
8791 {
8792         uint32_t flags = MODE_ASIC | MODE_PORT2;
8793
8794         if (CHIP_IS_E2(sc)) {
8795                 flags |= MODE_E2;
8796         } else if (CHIP_IS_E3(sc)) {
8797                 flags |= MODE_E3;
8798                 if (CHIP_REV(sc) == CHIP_REV_Ax) {
8799                         flags |= MODE_E3_A0;
8800                 } else {        /*if (CHIP_REV(sc) == CHIP_REV_Bx) */
8801
8802                         flags |= MODE_E3_B0 | MODE_COS3;
8803                 }
8804         }
8805
8806         if (IS_MF(sc)) {
8807                 flags |= MODE_MF;
8808                 switch (sc->devinfo.mf_info.mf_mode) {
8809                 case MULTI_FUNCTION_SD:
8810                         flags |= MODE_MF_SD;
8811                         break;
8812                 case MULTI_FUNCTION_SI:
8813                         flags |= MODE_MF_SI;
8814                         break;
8815                 case MULTI_FUNCTION_AFEX:
8816                         flags |= MODE_MF_AFEX;
8817                         break;
8818                 }
8819         } else {
8820                 flags |= MODE_SF;
8821         }
8822
8823 #if defined(__LITTLE_ENDIAN)
8824         flags |= MODE_LITTLE_ENDIAN;
8825 #else /* __BIG_ENDIAN */
8826         flags |= MODE_BIG_ENDIAN;
8827 #endif
8828
8829         INIT_MODE_FLAGS(sc) = flags;
8830 }
8831
8832 int bnx2x_alloc_hsi_mem(struct bnx2x_softc *sc)
8833 {
8834         struct bnx2x_fastpath *fp;
8835         char buf[32];
8836         uint32_t i;
8837
8838         if (IS_PF(sc)) {
8839 /************************/
8840 /* DEFAULT STATUS BLOCK */
8841 /************************/
8842
8843                 if (bnx2x_dma_alloc(sc, sizeof(struct host_sp_status_block),
8844                                   &sc->def_sb_dma, "def_sb",
8845                                   RTE_CACHE_LINE_SIZE) != 0) {
8846                         return -1;
8847                 }
8848
8849                 sc->def_sb =
8850                     (struct host_sp_status_block *)sc->def_sb_dma.vaddr;
8851 /***************/
8852 /* EVENT QUEUE */
8853 /***************/
8854
8855                 if (bnx2x_dma_alloc(sc, BNX2X_PAGE_SIZE,
8856                                   &sc->eq_dma, "ev_queue",
8857                                   RTE_CACHE_LINE_SIZE) != 0) {
8858                         sc->def_sb = NULL;
8859                         return -1;
8860                 }
8861
8862                 sc->eq = (union event_ring_elem *)sc->eq_dma.vaddr;
8863
8864 /*************/
8865 /* SLOW PATH */
8866 /*************/
8867
8868                 if (bnx2x_dma_alloc(sc, sizeof(struct bnx2x_slowpath),
8869                                   &sc->sp_dma, "sp",
8870                                   RTE_CACHE_LINE_SIZE) != 0) {
8871                         sc->eq = NULL;
8872                         sc->def_sb = NULL;
8873                         return -1;
8874                 }
8875
8876                 sc->sp = (struct bnx2x_slowpath *)sc->sp_dma.vaddr;
8877
8878 /*******************/
8879 /* SLOW PATH QUEUE */
8880 /*******************/
8881
8882                 if (bnx2x_dma_alloc(sc, BNX2X_PAGE_SIZE,
8883                                   &sc->spq_dma, "sp_queue",
8884                                   RTE_CACHE_LINE_SIZE) != 0) {
8885                         sc->sp = NULL;
8886                         sc->eq = NULL;
8887                         sc->def_sb = NULL;
8888                         return -1;
8889                 }
8890
8891                 sc->spq = (struct eth_spe *)sc->spq_dma.vaddr;
8892
8893 /***************************/
8894 /* FW DECOMPRESSION BUFFER */
8895 /***************************/
8896
8897                 if (bnx2x_dma_alloc(sc, FW_BUF_SIZE, &sc->gz_buf_dma,
8898                                   "fw_buf", RTE_CACHE_LINE_SIZE) != 0) {
8899                         sc->spq = NULL;
8900                         sc->sp = NULL;
8901                         sc->eq = NULL;
8902                         sc->def_sb = NULL;
8903                         return -1;
8904                 }
8905
8906                 sc->gz_buf = (void *)sc->gz_buf_dma.vaddr;
8907         }
8908
8909         /*************/
8910         /* FASTPATHS */
8911         /*************/
8912
8913         /* allocate DMA memory for each fastpath structure */
8914         for (i = 0; i < sc->num_queues; i++) {
8915                 fp = &sc->fp[i];
8916                 fp->sc = sc;
8917                 fp->index = i;
8918
8919 /*******************/
8920 /* FP STATUS BLOCK */
8921 /*******************/
8922
8923                 snprintf(buf, sizeof(buf), "fp_%d_sb", i);
8924                 if (bnx2x_dma_alloc(sc, sizeof(union bnx2x_host_hc_status_block),
8925                                   &fp->sb_dma, buf, RTE_CACHE_LINE_SIZE) != 0) {
8926                         PMD_DRV_LOG(NOTICE, sc, "Failed to alloc %s", buf);
8927                         return -1;
8928                 } else {
8929                         if (CHIP_IS_E2E3(sc)) {
8930                                 fp->status_block.e2_sb =
8931                                     (struct host_hc_status_block_e2 *)
8932                                     fp->sb_dma.vaddr;
8933                         } else {
8934                                 fp->status_block.e1x_sb =
8935                                     (struct host_hc_status_block_e1x *)
8936                                     fp->sb_dma.vaddr;
8937                         }
8938                 }
8939         }
8940
8941         return 0;
8942 }
8943
8944 void bnx2x_free_hsi_mem(struct bnx2x_softc *sc)
8945 {
8946         struct bnx2x_fastpath *fp;
8947         int i;
8948
8949         for (i = 0; i < sc->num_queues; i++) {
8950                 fp = &sc->fp[i];
8951
8952 /*******************/
8953 /* FP STATUS BLOCK */
8954 /*******************/
8955
8956                 memset(&fp->status_block, 0, sizeof(fp->status_block));
8957         }
8958
8959         /***************************/
8960         /* FW DECOMPRESSION BUFFER */
8961         /***************************/
8962
8963         sc->gz_buf = NULL;
8964
8965         /*******************/
8966         /* SLOW PATH QUEUE */
8967         /*******************/
8968
8969         sc->spq = NULL;
8970
8971         /*************/
8972         /* SLOW PATH */
8973         /*************/
8974
8975         sc->sp = NULL;
8976
8977         /***************/
8978         /* EVENT QUEUE */
8979         /***************/
8980
8981         sc->eq = NULL;
8982
8983         /************************/
8984         /* DEFAULT STATUS BLOCK */
8985         /************************/
8986
8987         sc->def_sb = NULL;
8988
8989 }
8990
8991 /*
8992 * Previous driver DMAE transaction may have occurred when pre-boot stage
8993 * ended and boot began. This would invalidate the addresses of the
8994 * transaction, resulting in was-error bit set in the PCI causing all
8995 * hw-to-host PCIe transactions to timeout. If this happened we want to clear
8996 * the interrupt which detected this from the pglueb and the was-done bit
8997 */
8998 static void bnx2x_prev_interrupted_dmae(struct bnx2x_softc *sc)
8999 {
9000         uint32_t val;
9001
9002         if (!CHIP_IS_E1x(sc)) {
9003                 val = REG_RD(sc, PGLUE_B_REG_PGLUE_B_INT_STS);
9004                 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_WAS_ERROR_ATTN) {
9005                         REG_WR(sc, PGLUE_B_REG_WAS_ERROR_PF_7_0_CLR,
9006                                1 << SC_FUNC(sc));
9007                 }
9008         }
9009 }
9010
9011 static int bnx2x_prev_mcp_done(struct bnx2x_softc *sc)
9012 {
9013         uint32_t rc = bnx2x_fw_command(sc, DRV_MSG_CODE_UNLOAD_DONE,
9014                                      DRV_MSG_CODE_UNLOAD_SKIP_LINK_RESET);
9015         if (!rc) {
9016                 PMD_DRV_LOG(NOTICE, sc, "MCP response failure, aborting");
9017                 return -1;
9018         }
9019
9020         return 0;
9021 }
9022
9023 static struct bnx2x_prev_list_node *bnx2x_prev_path_get_entry(struct bnx2x_softc *sc)
9024 {
9025         struct bnx2x_prev_list_node *tmp;
9026
9027         LIST_FOREACH(tmp, &bnx2x_prev_list, node) {
9028                 if ((sc->pcie_bus == tmp->bus) &&
9029                     (sc->pcie_device == tmp->slot) &&
9030                     (SC_PATH(sc) == tmp->path)) {
9031                         return tmp;
9032                 }
9033         }
9034
9035         return NULL;
9036 }
9037
9038 static uint8_t bnx2x_prev_is_path_marked(struct bnx2x_softc *sc)
9039 {
9040         struct bnx2x_prev_list_node *tmp;
9041         int rc = FALSE;
9042
9043         rte_spinlock_lock(&bnx2x_prev_mtx);
9044
9045         tmp = bnx2x_prev_path_get_entry(sc);
9046         if (tmp) {
9047                 if (tmp->aer) {
9048                         PMD_DRV_LOG(DEBUG, sc,
9049                                     "Path %d/%d/%d was marked by AER",
9050                                     sc->pcie_bus, sc->pcie_device, SC_PATH(sc));
9051                 } else {
9052                         rc = TRUE;
9053                         PMD_DRV_LOG(DEBUG, sc,
9054                                     "Path %d/%d/%d was already cleaned from previous drivers",
9055                                     sc->pcie_bus, sc->pcie_device, SC_PATH(sc));
9056                 }
9057         }
9058
9059         rte_spinlock_unlock(&bnx2x_prev_mtx);
9060
9061         return rc;
9062 }
9063
9064 static int bnx2x_prev_mark_path(struct bnx2x_softc *sc, uint8_t after_undi)
9065 {
9066         struct bnx2x_prev_list_node *tmp;
9067
9068         rte_spinlock_lock(&bnx2x_prev_mtx);
9069
9070         /* Check whether the entry for this path already exists */
9071         tmp = bnx2x_prev_path_get_entry(sc);
9072         if (tmp) {
9073                 if (!tmp->aer) {
9074                         PMD_DRV_LOG(DEBUG, sc,
9075                                     "Re-marking AER in path %d/%d/%d",
9076                                     sc->pcie_bus, sc->pcie_device, SC_PATH(sc));
9077                 } else {
9078                         PMD_DRV_LOG(DEBUG, sc,
9079                                     "Removing AER indication from path %d/%d/%d",
9080                                     sc->pcie_bus, sc->pcie_device, SC_PATH(sc));
9081                         tmp->aer = 0;
9082                 }
9083
9084                 rte_spinlock_unlock(&bnx2x_prev_mtx);
9085                 return 0;
9086         }
9087
9088         rte_spinlock_unlock(&bnx2x_prev_mtx);
9089
9090         /* Create an entry for this path and add it */
9091         tmp = rte_malloc("", sizeof(struct bnx2x_prev_list_node),
9092                          RTE_CACHE_LINE_SIZE);
9093         if (!tmp) {
9094                 PMD_DRV_LOG(NOTICE, sc, "Failed to allocate 'bnx2x_prev_list_node'");
9095                 return -1;
9096         }
9097
9098         tmp->bus = sc->pcie_bus;
9099         tmp->slot = sc->pcie_device;
9100         tmp->path = SC_PATH(sc);
9101         tmp->aer = 0;
9102         tmp->undi = after_undi ? (1 << SC_PORT(sc)) : 0;
9103
9104         rte_spinlock_lock(&bnx2x_prev_mtx);
9105
9106         LIST_INSERT_HEAD(&bnx2x_prev_list, tmp, node);
9107
9108         rte_spinlock_unlock(&bnx2x_prev_mtx);
9109
9110         return 0;
9111 }
9112
9113 static int bnx2x_do_flr(struct bnx2x_softc *sc)
9114 {
9115         int i;
9116
9117         /* only E2 and onwards support FLR */
9118         if (CHIP_IS_E1x(sc)) {
9119                 PMD_DRV_LOG(WARNING, sc, "FLR not supported in E1H");
9120                 return -1;
9121         }
9122
9123         /* only bootcode REQ_BC_VER_4_INITIATE_FLR and onwards support flr */
9124         if (sc->devinfo.bc_ver < REQ_BC_VER_4_INITIATE_FLR) {
9125                 PMD_DRV_LOG(WARNING, sc,
9126                             "FLR not supported by BC_VER: 0x%08x",
9127                             sc->devinfo.bc_ver);
9128                 return -1;
9129         }
9130
9131         /* Wait for Transaction Pending bit clean */
9132         for (i = 0; i < 4; i++) {
9133                 if (i) {
9134                         DELAY(((1 << (i - 1)) * 100) * 1000);
9135                 }
9136
9137                 if (!bnx2x_is_pcie_pending(sc)) {
9138                         goto clear;
9139                 }
9140         }
9141
9142         PMD_DRV_LOG(NOTICE, sc, "PCIE transaction is not cleared, "
9143                     "proceeding with reset anyway");
9144
9145 clear:
9146         bnx2x_fw_command(sc, DRV_MSG_CODE_INITIATE_FLR, 0);
9147
9148         return 0;
9149 }
9150
9151 struct bnx2x_mac_vals {
9152         uint32_t xmac_addr;
9153         uint32_t xmac_val;
9154         uint32_t emac_addr;
9155         uint32_t emac_val;
9156         uint32_t umac_addr;
9157         uint32_t umac_val;
9158         uint32_t bmac_addr;
9159         uint32_t bmac_val[2];
9160 };
9161
9162 static void
9163 bnx2x_prev_unload_close_mac(struct bnx2x_softc *sc, struct bnx2x_mac_vals *vals)
9164 {
9165         uint32_t val, base_addr, offset, mask, reset_reg;
9166         uint8_t mac_stopped = FALSE;
9167         uint8_t port = SC_PORT(sc);
9168         uint32_t wb_data[2];
9169
9170         /* reset addresses as they also mark which values were changed */
9171         vals->bmac_addr = 0;
9172         vals->umac_addr = 0;
9173         vals->xmac_addr = 0;
9174         vals->emac_addr = 0;
9175
9176         reset_reg = REG_RD(sc, MISC_REG_RESET_REG_2);
9177
9178         if (!CHIP_IS_E3(sc)) {
9179                 val = REG_RD(sc, NIG_REG_BMAC0_REGS_OUT_EN + port * 4);
9180                 mask = MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port;
9181                 if ((mask & reset_reg) && val) {
9182                         base_addr = SC_PORT(sc) ? NIG_REG_INGRESS_BMAC1_MEM
9183                             : NIG_REG_INGRESS_BMAC0_MEM;
9184                         offset = CHIP_IS_E2(sc) ? BIGMAC2_REGISTER_BMAC_CONTROL
9185                             : BIGMAC_REGISTER_BMAC_CONTROL;
9186
9187                         /*
9188                          * use rd/wr since we cannot use dmae. This is safe
9189                          * since MCP won't access the bus due to the request
9190                          * to unload, and no function on the path can be
9191                          * loaded at this time.
9192                          */
9193                         wb_data[0] = REG_RD(sc, base_addr + offset);
9194                         wb_data[1] = REG_RD(sc, base_addr + offset + 0x4);
9195                         vals->bmac_addr = base_addr + offset;
9196                         vals->bmac_val[0] = wb_data[0];
9197                         vals->bmac_val[1] = wb_data[1];
9198                         wb_data[0] &= ~ELINK_BMAC_CONTROL_RX_ENABLE;
9199                         REG_WR(sc, vals->bmac_addr, wb_data[0]);
9200                         REG_WR(sc, vals->bmac_addr + 0x4, wb_data[1]);
9201                 }
9202
9203                 vals->emac_addr = NIG_REG_NIG_EMAC0_EN + SC_PORT(sc) * 4;
9204                 vals->emac_val = REG_RD(sc, vals->emac_addr);
9205                 REG_WR(sc, vals->emac_addr, 0);
9206                 mac_stopped = TRUE;
9207         } else {
9208                 if (reset_reg & MISC_REGISTERS_RESET_REG_2_XMAC) {
9209                         base_addr = SC_PORT(sc) ? GRCBASE_XMAC1 : GRCBASE_XMAC0;
9210                         val = REG_RD(sc, base_addr + XMAC_REG_PFC_CTRL_HI);
9211                         REG_WR(sc, base_addr + XMAC_REG_PFC_CTRL_HI,
9212                                val & ~(1 << 1));
9213                         REG_WR(sc, base_addr + XMAC_REG_PFC_CTRL_HI,
9214                                val | (1 << 1));
9215                         vals->xmac_addr = base_addr + XMAC_REG_CTRL;
9216                         vals->xmac_val = REG_RD(sc, vals->xmac_addr);
9217                         REG_WR(sc, vals->xmac_addr, 0);
9218                         mac_stopped = TRUE;
9219                 }
9220
9221                 mask = MISC_REGISTERS_RESET_REG_2_UMAC0 << port;
9222                 if (mask & reset_reg) {
9223                         base_addr = SC_PORT(sc) ? GRCBASE_UMAC1 : GRCBASE_UMAC0;
9224                         vals->umac_addr = base_addr + UMAC_REG_COMMAND_CONFIG;
9225                         vals->umac_val = REG_RD(sc, vals->umac_addr);
9226                         REG_WR(sc, vals->umac_addr, 0);
9227                         mac_stopped = TRUE;
9228                 }
9229         }
9230
9231         if (mac_stopped) {
9232                 DELAY(20000);
9233         }
9234 }
9235
9236 #define BNX2X_PREV_UNDI_PROD_ADDR(p)  (BAR_TSTRORM_INTMEM + 0x1508 + ((p) << 4))
9237 #define BNX2X_PREV_UNDI_RCQ(val)      ((val) & 0xffff)
9238 #define BNX2X_PREV_UNDI_BD(val)       ((val) >> 16 & 0xffff)
9239 #define BNX2X_PREV_UNDI_PROD(rcq, bd) ((bd) << 16 | (rcq))
9240
9241 static void
9242 bnx2x_prev_unload_undi_inc(struct bnx2x_softc *sc, uint8_t port, uint8_t inc)
9243 {
9244         uint16_t rcq, bd;
9245         uint32_t tmp_reg = REG_RD(sc, BNX2X_PREV_UNDI_PROD_ADDR(port));
9246
9247         rcq = BNX2X_PREV_UNDI_RCQ(tmp_reg) + inc;
9248         bd = BNX2X_PREV_UNDI_BD(tmp_reg) + inc;
9249
9250         tmp_reg = BNX2X_PREV_UNDI_PROD(rcq, bd);
9251         REG_WR(sc, BNX2X_PREV_UNDI_PROD_ADDR(port), tmp_reg);
9252 }
9253
9254 static int bnx2x_prev_unload_common(struct bnx2x_softc *sc)
9255 {
9256         uint32_t reset_reg, tmp_reg = 0, rc;
9257         uint8_t prev_undi = FALSE;
9258         struct bnx2x_mac_vals mac_vals;
9259         uint32_t timer_count = 1000;
9260         uint32_t prev_brb;
9261
9262         /*
9263          * It is possible a previous function received 'common' answer,
9264          * but hasn't loaded yet, therefore creating a scenario of
9265          * multiple functions receiving 'common' on the same path.
9266          */
9267         memset(&mac_vals, 0, sizeof(mac_vals));
9268
9269         if (bnx2x_prev_is_path_marked(sc)) {
9270                 return bnx2x_prev_mcp_done(sc);
9271         }
9272
9273         reset_reg = REG_RD(sc, MISC_REG_RESET_REG_1);
9274
9275         /* Reset should be performed after BRB is emptied */
9276         if (reset_reg & MISC_REGISTERS_RESET_REG_1_RST_BRB1) {
9277                 /* Close the MAC Rx to prevent BRB from filling up */
9278                 bnx2x_prev_unload_close_mac(sc, &mac_vals);
9279
9280                 /* close LLH filters towards the BRB */
9281                 elink_set_rx_filter(&sc->link_params, 0);
9282
9283                 /*
9284                  * Check if the UNDI driver was previously loaded.
9285                  * UNDI driver initializes CID offset for normal bell to 0x7
9286                  */
9287                 if (reset_reg & MISC_REGISTERS_RESET_REG_1_RST_DORQ) {
9288                         tmp_reg = REG_RD(sc, DORQ_REG_NORM_CID_OFST);
9289                         if (tmp_reg == 0x7) {
9290                                 PMD_DRV_LOG(DEBUG, sc, "UNDI previously loaded");
9291                                 prev_undi = TRUE;
9292                                 /* clear the UNDI indication */
9293                                 REG_WR(sc, DORQ_REG_NORM_CID_OFST, 0);
9294                                 /* clear possible idle check errors */
9295                                 REG_RD(sc, NIG_REG_NIG_INT_STS_CLR_0);
9296                         }
9297                 }
9298
9299                 /* wait until BRB is empty */
9300                 tmp_reg = REG_RD(sc, BRB1_REG_NUM_OF_FULL_BLOCKS);
9301                 while (timer_count) {
9302                         prev_brb = tmp_reg;
9303
9304                         tmp_reg = REG_RD(sc, BRB1_REG_NUM_OF_FULL_BLOCKS);
9305                         if (!tmp_reg) {
9306                                 break;
9307                         }
9308
9309                         PMD_DRV_LOG(DEBUG, sc, "BRB still has 0x%08x", tmp_reg);
9310
9311                         /* reset timer as long as BRB actually gets emptied */
9312                         if (prev_brb > tmp_reg) {
9313                                 timer_count = 1000;
9314                         } else {
9315                                 timer_count--;
9316                         }
9317
9318                         /* If UNDI resides in memory, manually increment it */
9319                         if (prev_undi) {
9320                                 bnx2x_prev_unload_undi_inc(sc, SC_PORT(sc), 1);
9321                         }
9322
9323                         DELAY(10);
9324                 }
9325
9326                 if (!timer_count) {
9327                         PMD_DRV_LOG(NOTICE, sc, "Failed to empty BRB");
9328                 }
9329         }
9330
9331         /* No packets are in the pipeline, path is ready for reset */
9332         bnx2x_reset_common(sc);
9333
9334         if (mac_vals.xmac_addr) {
9335                 REG_WR(sc, mac_vals.xmac_addr, mac_vals.xmac_val);
9336         }
9337         if (mac_vals.umac_addr) {
9338                 REG_WR(sc, mac_vals.umac_addr, mac_vals.umac_val);
9339         }
9340         if (mac_vals.emac_addr) {
9341                 REG_WR(sc, mac_vals.emac_addr, mac_vals.emac_val);
9342         }
9343         if (mac_vals.bmac_addr) {
9344                 REG_WR(sc, mac_vals.bmac_addr, mac_vals.bmac_val[0]);
9345                 REG_WR(sc, mac_vals.bmac_addr + 4, mac_vals.bmac_val[1]);
9346         }
9347
9348         rc = bnx2x_prev_mark_path(sc, prev_undi);
9349         if (rc) {
9350                 bnx2x_prev_mcp_done(sc);
9351                 return rc;
9352         }
9353
9354         return bnx2x_prev_mcp_done(sc);
9355 }
9356
9357 static int bnx2x_prev_unload_uncommon(struct bnx2x_softc *sc)
9358 {
9359         int rc;
9360
9361         /* Test if previous unload process was already finished for this path */
9362         if (bnx2x_prev_is_path_marked(sc)) {
9363                 return bnx2x_prev_mcp_done(sc);
9364         }
9365
9366         /*
9367          * If function has FLR capabilities, and existing FW version matches
9368          * the one required, then FLR will be sufficient to clean any residue
9369          * left by previous driver
9370          */
9371         rc = bnx2x_nic_load_analyze_req(sc, FW_MSG_CODE_DRV_LOAD_FUNCTION);
9372         if (!rc) {
9373                 /* fw version is good */
9374                 rc = bnx2x_do_flr(sc);
9375         }
9376
9377         if (!rc) {
9378                 /* FLR was performed */
9379                 return 0;
9380         }
9381
9382         PMD_DRV_LOG(INFO, sc, "Could not FLR");
9383
9384         /* Close the MCP request, return failure */
9385         rc = bnx2x_prev_mcp_done(sc);
9386         if (!rc) {
9387                 rc = BNX2X_PREV_WAIT_NEEDED;
9388         }
9389
9390         return rc;
9391 }
9392
9393 static int bnx2x_prev_unload(struct bnx2x_softc *sc)
9394 {
9395         int time_counter = 10;
9396         uint32_t fw, hw_lock_reg, hw_lock_val;
9397         uint32_t rc = 0;
9398
9399         PMD_INIT_FUNC_TRACE(sc);
9400
9401         /*
9402          * Clear HW from errors which may have resulted from an interrupted
9403          * DMAE transaction.
9404          */
9405         bnx2x_prev_interrupted_dmae(sc);
9406
9407         /* Release previously held locks */
9408         hw_lock_reg = (SC_FUNC(sc) <= 5) ?
9409                         (MISC_REG_DRIVER_CONTROL_1 + SC_FUNC(sc) * 8) :
9410                         (MISC_REG_DRIVER_CONTROL_7 + (SC_FUNC(sc) - 6) * 8);
9411
9412         hw_lock_val = (REG_RD(sc, hw_lock_reg));
9413         if (hw_lock_val) {
9414                 if (hw_lock_val & HW_LOCK_RESOURCE_NVRAM) {
9415                         PMD_DRV_LOG(DEBUG, sc, "Releasing previously held NVRAM lock\n");
9416                         REG_WR(sc, MCP_REG_MCPR_NVM_SW_ARB,
9417                                (MCPR_NVM_SW_ARB_ARB_REQ_CLR1 << SC_PORT(sc)));
9418                 }
9419                 PMD_DRV_LOG(DEBUG, sc, "Releasing previously held HW lock\n");
9420                 REG_WR(sc, hw_lock_reg, 0xffffffff);
9421         }
9422
9423         if (MCPR_ACCESS_LOCK_LOCK & REG_RD(sc, MCP_REG_MCPR_ACCESS_LOCK)) {
9424                 PMD_DRV_LOG(DEBUG, sc, "Releasing previously held ALR\n");
9425                 REG_WR(sc, MCP_REG_MCPR_ACCESS_LOCK, 0);
9426         }
9427
9428         do {
9429                 /* Lock MCP using an unload request */
9430                 fw = bnx2x_fw_command(sc, DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS, 0);
9431                 if (!fw) {
9432                         PMD_DRV_LOG(NOTICE, sc, "MCP response failure, aborting");
9433                         rc = -1;
9434                         break;
9435                 }
9436
9437                 if (fw == FW_MSG_CODE_DRV_UNLOAD_COMMON) {
9438                         rc = bnx2x_prev_unload_common(sc);
9439                         break;
9440                 }
9441
9442                 /* non-common reply from MCP might require looping */
9443                 rc = bnx2x_prev_unload_uncommon(sc);
9444                 if (rc != BNX2X_PREV_WAIT_NEEDED) {
9445                         break;
9446                 }
9447
9448                 DELAY(20000);
9449         } while (--time_counter);
9450
9451         if (!time_counter || rc) {
9452                 PMD_DRV_LOG(NOTICE, sc, "Failed to unload previous driver!");
9453                 rc = -1;
9454         }
9455
9456         return rc;
9457 }
9458
9459 static void
9460 bnx2x_dcbx_set_state(struct bnx2x_softc *sc, uint8_t dcb_on, uint32_t dcbx_enabled)
9461 {
9462         if (!CHIP_IS_E1x(sc)) {
9463                 sc->dcb_state = dcb_on;
9464                 sc->dcbx_enabled = dcbx_enabled;
9465         } else {
9466                 sc->dcb_state = FALSE;
9467                 sc->dcbx_enabled = BNX2X_DCBX_ENABLED_INVALID;
9468         }
9469         PMD_DRV_LOG(DEBUG, sc,
9470                     "DCB state [%s:%s]",
9471                     dcb_on ? "ON" : "OFF",
9472                     (dcbx_enabled == BNX2X_DCBX_ENABLED_OFF) ? "user-mode" :
9473                     (dcbx_enabled ==
9474                      BNX2X_DCBX_ENABLED_ON_NEG_OFF) ? "on-chip static"
9475                     : (dcbx_enabled ==
9476                        BNX2X_DCBX_ENABLED_ON_NEG_ON) ?
9477                     "on-chip with negotiation" : "invalid");
9478 }
9479
9480 static int bnx2x_set_qm_cid_count(struct bnx2x_softc *sc)
9481 {
9482         int cid_count = BNX2X_L2_MAX_CID(sc);
9483
9484         if (CNIC_SUPPORT(sc)) {
9485                 cid_count += CNIC_CID_MAX;
9486         }
9487
9488         return roundup(cid_count, QM_CID_ROUND);
9489 }
9490
9491 static void bnx2x_init_multi_cos(struct bnx2x_softc *sc)
9492 {
9493         int pri, cos;
9494
9495         uint32_t pri_map = 0;
9496
9497         for (pri = 0; pri < BNX2X_MAX_PRIORITY; pri++) {
9498                 cos = ((pri_map & (0xf << (pri * 4))) >> (pri * 4));
9499                 if (cos < sc->max_cos) {
9500                         sc->prio_to_cos[pri] = cos;
9501                 } else {
9502                         PMD_DRV_LOG(WARNING, sc,
9503                                     "Invalid COS %d for priority %d "
9504                                     "(max COS is %d), setting to 0", cos, pri,
9505                                     (sc->max_cos - 1));
9506                         sc->prio_to_cos[pri] = 0;
9507                 }
9508         }
9509 }
9510
9511 static int bnx2x_pci_get_caps(struct bnx2x_softc *sc)
9512 {
9513         struct {
9514                 uint8_t id;
9515                 uint8_t next;
9516         } pci_cap;
9517         uint16_t status;
9518         struct bnx2x_pci_cap *cap;
9519
9520         cap = sc->pci_caps = rte_zmalloc("caps", sizeof(struct bnx2x_pci_cap),
9521                                          RTE_CACHE_LINE_SIZE);
9522         if (!cap) {
9523                 PMD_DRV_LOG(NOTICE, sc, "Failed to allocate memory");
9524                 return -ENOMEM;
9525         }
9526
9527 #ifndef __FreeBSD__
9528         pci_read(sc, PCI_STATUS, &status, 2);
9529         if (!(status & PCI_STATUS_CAP_LIST)) {
9530 #else
9531         pci_read(sc, PCIR_STATUS, &status, 2);
9532         if (!(status & PCIM_STATUS_CAPPRESENT)) {
9533 #endif
9534                 PMD_DRV_LOG(NOTICE, sc, "PCIe capability reading failed");
9535                 return -1;
9536         }
9537
9538 #ifndef __FreeBSD__
9539         pci_read(sc, PCI_CAPABILITY_LIST, &pci_cap.next, 1);
9540 #else
9541         pci_read(sc, PCIR_CAP_PTR, &pci_cap.next, 1);
9542 #endif
9543         while (pci_cap.next) {
9544                 cap->addr = pci_cap.next & ~3;
9545                 pci_read(sc, pci_cap.next & ~3, &pci_cap, 2);
9546                 if (pci_cap.id == 0xff)
9547                         break;
9548                 cap->id = pci_cap.id;
9549                 cap->type = BNX2X_PCI_CAP;
9550                 cap->next = rte_zmalloc("pci_cap",
9551                                         sizeof(struct bnx2x_pci_cap),
9552                                         RTE_CACHE_LINE_SIZE);
9553                 if (!cap->next) {
9554                         PMD_DRV_LOG(NOTICE, sc, "Failed to allocate memory");
9555                         return -ENOMEM;
9556                 }
9557                 cap = cap->next;
9558         }
9559
9560         return 0;
9561 }
9562
9563 static void bnx2x_init_rte(struct bnx2x_softc *sc)
9564 {
9565         if (IS_VF(sc)) {
9566                 sc->max_tx_queues = min(BNX2X_VF_MAX_QUEUES_PER_VF,
9567                                         sc->igu_sb_cnt);
9568                 sc->max_rx_queues = min(BNX2X_VF_MAX_QUEUES_PER_VF,
9569                                         sc->igu_sb_cnt);
9570         } else {
9571                 sc->max_rx_queues = BNX2X_MAX_RSS_COUNT(sc);
9572                 sc->max_tx_queues = sc->max_rx_queues;
9573         }
9574 }
9575
9576 #define FW_HEADER_LEN 104
9577 #define FW_NAME_57711 "/lib/firmware/bnx2x/bnx2x-e1h-7.2.51.0.fw"
9578 #define FW_NAME_57810 "/lib/firmware/bnx2x/bnx2x-e2-7.2.51.0.fw"
9579
9580 void bnx2x_load_firmware(struct bnx2x_softc *sc)
9581 {
9582         const char *fwname;
9583         int f;
9584         struct stat st;
9585
9586         fwname = sc->devinfo.device_id == CHIP_NUM_57711
9587                 ? FW_NAME_57711 : FW_NAME_57810;
9588         f = open(fwname, O_RDONLY);
9589         if (f < 0) {
9590                 PMD_DRV_LOG(NOTICE, sc, "Can't open firmware file");
9591                 return;
9592         }
9593
9594         if (fstat(f, &st) < 0) {
9595                 PMD_DRV_LOG(NOTICE, sc, "Can't stat firmware file");
9596                 close(f);
9597                 return;
9598         }
9599
9600         sc->firmware = rte_zmalloc("bnx2x_fw", st.st_size, RTE_CACHE_LINE_SIZE);
9601         if (!sc->firmware) {
9602                 PMD_DRV_LOG(NOTICE, sc, "Can't allocate memory for firmware");
9603                 close(f);
9604                 return;
9605         }
9606
9607         if (read(f, sc->firmware, st.st_size) != st.st_size) {
9608                 PMD_DRV_LOG(NOTICE, sc, "Can't read firmware data");
9609                 close(f);
9610                 return;
9611         }
9612         close(f);
9613
9614         sc->fw_len = st.st_size;
9615         if (sc->fw_len < FW_HEADER_LEN) {
9616                 PMD_DRV_LOG(NOTICE, sc,
9617                             "Invalid fw size: %" PRIu64, sc->fw_len);
9618                 return;
9619         }
9620         PMD_DRV_LOG(DEBUG, sc, "fw_len = %" PRIu64, sc->fw_len);
9621 }
9622
9623 static void
9624 bnx2x_data_to_init_ops(uint8_t * data, struct raw_op *dst, uint32_t len)
9625 {
9626         uint32_t *src = (uint32_t *) data;
9627         uint32_t i, j, tmp;
9628
9629         for (i = 0, j = 0; i < len / 8; ++i, j += 2) {
9630                 tmp = rte_be_to_cpu_32(src[j]);
9631                 dst[i].op = (tmp >> 24) & 0xFF;
9632                 dst[i].offset = tmp & 0xFFFFFF;
9633                 dst[i].raw_data = rte_be_to_cpu_32(src[j + 1]);
9634         }
9635 }
9636
9637 static void
9638 bnx2x_data_to_init_offsets(uint8_t * data, uint16_t * dst, uint32_t len)
9639 {
9640         uint16_t *src = (uint16_t *) data;
9641         uint32_t i;
9642
9643         for (i = 0; i < len / 2; ++i)
9644                 dst[i] = rte_be_to_cpu_16(src[i]);
9645 }
9646
9647 static void bnx2x_data_to_init_data(uint8_t * data, uint32_t * dst, uint32_t len)
9648 {
9649         uint32_t *src = (uint32_t *) data;
9650         uint32_t i;
9651
9652         for (i = 0; i < len / 4; ++i)
9653                 dst[i] = rte_be_to_cpu_32(src[i]);
9654 }
9655
9656 static void bnx2x_data_to_iro_array(uint8_t * data, struct iro *dst, uint32_t len)
9657 {
9658         uint32_t *src = (uint32_t *) data;
9659         uint32_t i, j, tmp;
9660
9661         for (i = 0, j = 0; i < len / sizeof(struct iro); ++i, ++j) {
9662                 dst[i].base = rte_be_to_cpu_32(src[j++]);
9663                 tmp = rte_be_to_cpu_32(src[j]);
9664                 dst[i].m1 = (tmp >> 16) & 0xFFFF;
9665                 dst[i].m2 = tmp & 0xFFFF;
9666                 ++j;
9667                 tmp = rte_be_to_cpu_32(src[j]);
9668                 dst[i].m3 = (tmp >> 16) & 0xFFFF;
9669                 dst[i].size = tmp & 0xFFFF;
9670         }
9671 }
9672
9673 /*
9674 * Device attach function.
9675 *
9676 * Allocates device resources, performs secondary chip identification, and
9677 * initializes driver instance variables. This function is called from driver
9678 * load after a successful probe.
9679 *
9680 * Returns:
9681 *   0 = Success, >0 = Failure
9682 */
9683 int bnx2x_attach(struct bnx2x_softc *sc)
9684 {
9685         int rc;
9686
9687         PMD_DRV_LOG(DEBUG, sc, "Starting attach...");
9688
9689         rc = bnx2x_pci_get_caps(sc);
9690         if (rc) {
9691                 PMD_DRV_LOG(NOTICE, sc, "PCIe caps reading was failed");
9692                 return rc;
9693         }
9694
9695         sc->state = BNX2X_STATE_CLOSED;
9696
9697         pci_write_long(sc, PCICFG_GRC_ADDRESS, PCICFG_VENDOR_ID_OFFSET);
9698
9699         sc->igu_base_addr = IS_VF(sc) ? PXP_VF_ADDR_IGU_START : BAR_IGU_INTMEM;
9700
9701         /* get PCI capabilites */
9702         bnx2x_probe_pci_caps(sc);
9703
9704         if (sc->devinfo.pcie_msix_cap_reg != 0) {
9705                 uint32_t val;
9706                 pci_read(sc,
9707                          (sc->devinfo.pcie_msix_cap_reg + PCIR_MSIX_CTRL), &val,
9708                          2);
9709                 sc->igu_sb_cnt = (val & PCIM_MSIXCTRL_TABLE_SIZE) + 1;
9710         } else {
9711                 sc->igu_sb_cnt = 1;
9712         }
9713
9714         /* Init RTE stuff */
9715         bnx2x_init_rte(sc);
9716
9717         if (IS_PF(sc)) {
9718                 /* Enable internal target-read (in case we are probed after PF
9719                  * FLR). Must be done prior to any BAR read access. Only for
9720                  * 57712 and up
9721                  */
9722                 if (!CHIP_IS_E1x(sc)) {
9723                         REG_WR(sc, PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_READ,
9724                                1);
9725                         DELAY(200000);
9726                 }
9727
9728                 /* get device info and set params */
9729                 if (bnx2x_get_device_info(sc) != 0) {
9730                         PMD_DRV_LOG(NOTICE, sc, "getting device info");
9731                         return -ENXIO;
9732                 }
9733
9734 /* get phy settings from shmem and 'and' against admin settings */
9735                 bnx2x_get_phy_info(sc);
9736         } else {
9737                 /* Left mac of VF unfilled, PF should set it for VF */
9738                 memset(sc->link_params.mac_addr, 0, ETHER_ADDR_LEN);
9739         }
9740
9741         sc->wol = 0;
9742
9743         /* set the default MTU (changed via ifconfig) */
9744         sc->mtu = ETHER_MTU;
9745
9746         bnx2x_set_modes_bitmap(sc);
9747
9748         /* need to reset chip if UNDI was active */
9749         if (IS_PF(sc) && !BNX2X_NOMCP(sc)) {
9750 /* init fw_seq */
9751                 sc->fw_seq =
9752                     (SHMEM_RD(sc, func_mb[SC_FW_MB_IDX(sc)].drv_mb_header) &
9753                      DRV_MSG_SEQ_NUMBER_MASK);
9754                 PMD_DRV_LOG(DEBUG, sc, "prev unload fw_seq 0x%04x",
9755                             sc->fw_seq);
9756                 bnx2x_prev_unload(sc);
9757         }
9758
9759         bnx2x_dcbx_set_state(sc, FALSE, BNX2X_DCBX_ENABLED_OFF);
9760
9761         /* calculate qm_cid_count */
9762         sc->qm_cid_count = bnx2x_set_qm_cid_count(sc);
9763
9764         sc->max_cos = 1;
9765         bnx2x_init_multi_cos(sc);
9766
9767         return 0;
9768 }
9769
9770 static void
9771 bnx2x_igu_ack_sb(struct bnx2x_softc *sc, uint8_t igu_sb_id, uint8_t segment,
9772                uint16_t index, uint8_t op, uint8_t update)
9773 {
9774         uint32_t igu_addr = sc->igu_base_addr;
9775         igu_addr += (IGU_CMD_INT_ACK_BASE + igu_sb_id) * 8;
9776         bnx2x_igu_ack_sb_gen(sc, segment, index, op, update, igu_addr);
9777 }
9778
9779 static void
9780 bnx2x_ack_sb(struct bnx2x_softc *sc, uint8_t igu_sb_id, uint8_t storm,
9781            uint16_t index, uint8_t op, uint8_t update)
9782 {
9783         if (unlikely(sc->devinfo.int_block == INT_BLOCK_HC))
9784                 bnx2x_hc_ack_sb(sc, igu_sb_id, storm, index, op, update);
9785         else {
9786                 uint8_t segment;
9787                 if (CHIP_INT_MODE_IS_BC(sc)) {
9788                         segment = storm;
9789                 } else if (igu_sb_id != sc->igu_dsb_id) {
9790                         segment = IGU_SEG_ACCESS_DEF;
9791                 } else if (storm == ATTENTION_ID) {
9792                         segment = IGU_SEG_ACCESS_ATTN;
9793                 } else {
9794                         segment = IGU_SEG_ACCESS_DEF;
9795                 }
9796                 bnx2x_igu_ack_sb(sc, igu_sb_id, segment, index, op, update);
9797         }
9798 }
9799
9800 static void
9801 bnx2x_igu_clear_sb_gen(struct bnx2x_softc *sc, uint8_t func, uint8_t idu_sb_id,
9802                      uint8_t is_pf)
9803 {
9804         uint32_t data, ctl, cnt = 100;
9805         uint32_t igu_addr_data = IGU_REG_COMMAND_REG_32LSB_DATA;
9806         uint32_t igu_addr_ctl = IGU_REG_COMMAND_REG_CTRL;
9807         uint32_t igu_addr_ack = IGU_REG_CSTORM_TYPE_0_SB_CLEANUP +
9808             (idu_sb_id / 32) * 4;
9809         uint32_t sb_bit = 1 << (idu_sb_id % 32);
9810         uint32_t func_encode = func |
9811             (is_pf ? 1 : 0) << IGU_FID_ENCODE_IS_PF_SHIFT;
9812         uint32_t addr_encode = IGU_CMD_E2_PROD_UPD_BASE + idu_sb_id;
9813
9814         /* Not supported in BC mode */
9815         if (CHIP_INT_MODE_IS_BC(sc)) {
9816                 return;
9817         }
9818
9819         data = ((IGU_USE_REGISTER_cstorm_type_0_sb_cleanup <<
9820                  IGU_REGULAR_CLEANUP_TYPE_SHIFT) |
9821                 IGU_REGULAR_CLEANUP_SET | IGU_REGULAR_BCLEANUP);
9822
9823         ctl = ((addr_encode << IGU_CTRL_REG_ADDRESS_SHIFT) |
9824                (func_encode << IGU_CTRL_REG_FID_SHIFT) |
9825                (IGU_CTRL_CMD_TYPE_WR << IGU_CTRL_REG_TYPE_SHIFT));
9826
9827         REG_WR(sc, igu_addr_data, data);
9828
9829         mb();
9830
9831         PMD_DRV_LOG(DEBUG, sc, "write 0x%08x to IGU(via GRC) addr 0x%x",
9832                     ctl, igu_addr_ctl);
9833         REG_WR(sc, igu_addr_ctl, ctl);
9834
9835         mb();
9836
9837         /* wait for clean up to finish */
9838         while (!(REG_RD(sc, igu_addr_ack) & sb_bit) && --cnt) {
9839                 DELAY(20000);
9840         }
9841
9842         if (!(REG_RD(sc, igu_addr_ack) & sb_bit)) {
9843                 PMD_DRV_LOG(DEBUG, sc,
9844                             "Unable to finish IGU cleanup: "
9845                             "idu_sb_id %d offset %d bit %d (cnt %d)",
9846                             idu_sb_id, idu_sb_id / 32, idu_sb_id % 32, cnt);
9847         }
9848 }
9849
9850 static void bnx2x_igu_clear_sb(struct bnx2x_softc *sc, uint8_t idu_sb_id)
9851 {
9852         bnx2x_igu_clear_sb_gen(sc, SC_FUNC(sc), idu_sb_id, TRUE /*PF*/);
9853 }
9854
9855 /*******************/
9856 /* ECORE CALLBACKS */
9857 /*******************/
9858
9859 static void bnx2x_reset_common(struct bnx2x_softc *sc)
9860 {
9861         uint32_t val = 0x1400;
9862
9863         PMD_INIT_FUNC_TRACE(sc);
9864
9865         /* reset_common */
9866         REG_WR(sc, (GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR),
9867                0xd3ffff7f);
9868
9869         if (CHIP_IS_E3(sc)) {
9870                 val |= MISC_REGISTERS_RESET_REG_2_MSTAT0;
9871                 val |= MISC_REGISTERS_RESET_REG_2_MSTAT1;
9872         }
9873
9874         REG_WR(sc, (GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR), val);
9875 }
9876
9877 static void bnx2x_common_init_phy(struct bnx2x_softc *sc)
9878 {
9879         uint32_t shmem_base[2];
9880         uint32_t shmem2_base[2];
9881
9882         /* Avoid common init in case MFW supports LFA */
9883         if (SHMEM2_RD(sc, size) >
9884             (uint32_t) offsetof(struct shmem2_region,
9885                                 lfa_host_addr[SC_PORT(sc)])) {
9886                 return;
9887         }
9888
9889         shmem_base[0] = sc->devinfo.shmem_base;
9890         shmem2_base[0] = sc->devinfo.shmem2_base;
9891
9892         if (!CHIP_IS_E1x(sc)) {
9893                 shmem_base[1] = SHMEM2_RD(sc, other_shmem_base_addr);
9894                 shmem2_base[1] = SHMEM2_RD(sc, other_shmem2_base_addr);
9895         }
9896
9897         bnx2x_acquire_phy_lock(sc);
9898         elink_common_init_phy(sc, shmem_base, shmem2_base,
9899                               sc->devinfo.chip_id, 0);
9900         bnx2x_release_phy_lock(sc);
9901 }
9902
9903 static void bnx2x_pf_disable(struct bnx2x_softc *sc)
9904 {
9905         uint32_t val = REG_RD(sc, IGU_REG_PF_CONFIGURATION);
9906
9907         val &= ~IGU_PF_CONF_FUNC_EN;
9908
9909         REG_WR(sc, IGU_REG_PF_CONFIGURATION, val);
9910         REG_WR(sc, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 0);
9911         REG_WR(sc, CFC_REG_WEAK_ENABLE_PF, 0);
9912 }
9913
9914 static void bnx2x_init_pxp(struct bnx2x_softc *sc)
9915 {
9916         uint16_t devctl;
9917         int r_order, w_order;
9918
9919         devctl = bnx2x_pcie_capability_read(sc, PCIR_EXPRESS_DEVICE_CTL);
9920
9921         w_order = ((devctl & PCIM_EXP_CTL_MAX_PAYLOAD) >> 5);
9922         r_order = ((devctl & PCIM_EXP_CTL_MAX_READ_REQUEST) >> 12);
9923
9924         ecore_init_pxp_arb(sc, r_order, w_order);
9925 }
9926
9927 static uint32_t bnx2x_get_pretend_reg(struct bnx2x_softc *sc)
9928 {
9929         uint32_t base = PXP2_REG_PGL_PRETEND_FUNC_F0;
9930         uint32_t stride = (PXP2_REG_PGL_PRETEND_FUNC_F1 - base);
9931         return base + (SC_ABS_FUNC(sc)) * stride;
9932 }
9933
9934 /*
9935  * Called only on E1H or E2.
9936  * When pretending to be PF, the pretend value is the function number 0..7.
9937  * When pretending to be VF, the pretend val is the PF-num:VF-valid:ABS-VFID
9938  * combination.
9939  */
9940 static int bnx2x_pretend_func(struct bnx2x_softc *sc, uint16_t pretend_func_val)
9941 {
9942         uint32_t pretend_reg;
9943
9944         if (CHIP_IS_E1H(sc) && (pretend_func_val > E1H_FUNC_MAX))
9945                 return -1;
9946
9947         /* get my own pretend register */
9948         pretend_reg = bnx2x_get_pretend_reg(sc);
9949         REG_WR(sc, pretend_reg, pretend_func_val);
9950         REG_RD(sc, pretend_reg);
9951         return 0;
9952 }
9953
9954 static void bnx2x_setup_fan_failure_detection(struct bnx2x_softc *sc)
9955 {
9956         int is_required;
9957         uint32_t val;
9958         int port;
9959
9960         is_required = 0;
9961         val = (SHMEM_RD(sc, dev_info.shared_hw_config.config2) &
9962                SHARED_HW_CFG_FAN_FAILURE_MASK);
9963
9964         if (val == SHARED_HW_CFG_FAN_FAILURE_ENABLED) {
9965                 is_required = 1;
9966         }
9967         /*
9968          * The fan failure mechanism is usually related to the PHY type since
9969          * the power consumption of the board is affected by the PHY. Currently,
9970          * fan is required for most designs with SFX7101, BNX2X8727 and BNX2X8481.
9971          */
9972         else if (val == SHARED_HW_CFG_FAN_FAILURE_PHY_TYPE) {
9973                 for (port = PORT_0; port < PORT_MAX; port++) {
9974                         is_required |= elink_fan_failure_det_req(sc,
9975                                                                  sc->
9976                                                                  devinfo.shmem_base,
9977                                                                  sc->
9978                                                                  devinfo.shmem2_base,
9979                                                                  port);
9980                 }
9981         }
9982
9983         if (is_required == 0) {
9984                 return;
9985         }
9986
9987         /* Fan failure is indicated by SPIO 5 */
9988         bnx2x_set_spio(sc, MISC_SPIO_SPIO5, MISC_SPIO_INPUT_HI_Z);
9989
9990         /* set to active low mode */
9991         val = REG_RD(sc, MISC_REG_SPIO_INT);
9992         val |= (MISC_SPIO_SPIO5 << MISC_SPIO_INT_OLD_SET_POS);
9993         REG_WR(sc, MISC_REG_SPIO_INT, val);
9994
9995         /* enable interrupt to signal the IGU */
9996         val = REG_RD(sc, MISC_REG_SPIO_EVENT_EN);
9997         val |= MISC_SPIO_SPIO5;
9998         REG_WR(sc, MISC_REG_SPIO_EVENT_EN, val);
9999 }
10000
10001 static void bnx2x_enable_blocks_attention(struct bnx2x_softc *sc)
10002 {
10003         uint32_t val;
10004
10005         REG_WR(sc, PXP_REG_PXP_INT_MASK_0, 0);
10006         if (!CHIP_IS_E1x(sc)) {
10007                 REG_WR(sc, PXP_REG_PXP_INT_MASK_1, 0x40);
10008         } else {
10009                 REG_WR(sc, PXP_REG_PXP_INT_MASK_1, 0);
10010         }
10011         REG_WR(sc, DORQ_REG_DORQ_INT_MASK, 0);
10012         REG_WR(sc, CFC_REG_CFC_INT_MASK, 0);
10013         /*
10014          * mask read length error interrupts in brb for parser
10015          * (parsing unit and 'checksum and crc' unit)
10016          * these errors are legal (PU reads fixed length and CAC can cause
10017          * read length error on truncated packets)
10018          */
10019         REG_WR(sc, BRB1_REG_BRB1_INT_MASK, 0xFC00);
10020         REG_WR(sc, QM_REG_QM_INT_MASK, 0);
10021         REG_WR(sc, TM_REG_TM_INT_MASK, 0);
10022         REG_WR(sc, XSDM_REG_XSDM_INT_MASK_0, 0);
10023         REG_WR(sc, XSDM_REG_XSDM_INT_MASK_1, 0);
10024         REG_WR(sc, XCM_REG_XCM_INT_MASK, 0);
10025         /*      REG_WR(sc, XSEM_REG_XSEM_INT_MASK_0, 0); */
10026         /*      REG_WR(sc, XSEM_REG_XSEM_INT_MASK_1, 0); */
10027         REG_WR(sc, USDM_REG_USDM_INT_MASK_0, 0);
10028         REG_WR(sc, USDM_REG_USDM_INT_MASK_1, 0);
10029         REG_WR(sc, UCM_REG_UCM_INT_MASK, 0);
10030         /*      REG_WR(sc, USEM_REG_USEM_INT_MASK_0, 0); */
10031         /*      REG_WR(sc, USEM_REG_USEM_INT_MASK_1, 0); */
10032         REG_WR(sc, GRCBASE_UPB + PB_REG_PB_INT_MASK, 0);
10033         REG_WR(sc, CSDM_REG_CSDM_INT_MASK_0, 0);
10034         REG_WR(sc, CSDM_REG_CSDM_INT_MASK_1, 0);
10035         REG_WR(sc, CCM_REG_CCM_INT_MASK, 0);
10036         /*      REG_WR(sc, CSEM_REG_CSEM_INT_MASK_0, 0); */
10037         /*      REG_WR(sc, CSEM_REG_CSEM_INT_MASK_1, 0); */
10038
10039         val = (PXP2_PXP2_INT_MASK_0_REG_PGL_CPL_AFT |
10040                PXP2_PXP2_INT_MASK_0_REG_PGL_CPL_OF |
10041                PXP2_PXP2_INT_MASK_0_REG_PGL_PCIE_ATTN);
10042         if (!CHIP_IS_E1x(sc)) {
10043                 val |= (PXP2_PXP2_INT_MASK_0_REG_PGL_READ_BLOCKED |
10044                         PXP2_PXP2_INT_MASK_0_REG_PGL_WRITE_BLOCKED);
10045         }
10046         REG_WR(sc, PXP2_REG_PXP2_INT_MASK_0, val);
10047
10048         REG_WR(sc, TSDM_REG_TSDM_INT_MASK_0, 0);
10049         REG_WR(sc, TSDM_REG_TSDM_INT_MASK_1, 0);
10050         REG_WR(sc, TCM_REG_TCM_INT_MASK, 0);
10051         /*      REG_WR(sc, TSEM_REG_TSEM_INT_MASK_0, 0); */
10052
10053         if (!CHIP_IS_E1x(sc)) {
10054 /* enable VFC attentions: bits 11 and 12, bits 31:13 reserved */
10055                 REG_WR(sc, TSEM_REG_TSEM_INT_MASK_1, 0x07ff);
10056         }
10057
10058         REG_WR(sc, CDU_REG_CDU_INT_MASK, 0);
10059         REG_WR(sc, DMAE_REG_DMAE_INT_MASK, 0);
10060         /*      REG_WR(sc, MISC_REG_MISC_INT_MASK, 0); */
10061         REG_WR(sc, PBF_REG_PBF_INT_MASK, 0x18); /* bit 3,4 masked */
10062 }
10063
10064 /**
10065  * bnx2x_init_hw_common - initialize the HW at the COMMON phase.
10066  *
10067  * @sc:     driver handle
10068  */
10069 static int bnx2x_init_hw_common(struct bnx2x_softc *sc)
10070 {
10071         uint8_t abs_func_id;
10072         uint32_t val;
10073
10074         PMD_DRV_LOG(DEBUG, sc,
10075                     "starting common init for func %d", SC_ABS_FUNC(sc));
10076
10077         /*
10078          * take the RESET lock to protect undi_unload flow from accessing
10079          * registers while we are resetting the chip
10080          */
10081         bnx2x_acquire_hw_lock(sc, HW_LOCK_RESOURCE_RESET);
10082
10083         bnx2x_reset_common(sc);
10084
10085         REG_WR(sc, (GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET), 0xffffffff);
10086
10087         val = 0xfffc;
10088         if (CHIP_IS_E3(sc)) {
10089                 val |= MISC_REGISTERS_RESET_REG_2_MSTAT0;
10090                 val |= MISC_REGISTERS_RESET_REG_2_MSTAT1;
10091         }
10092
10093         REG_WR(sc, (GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET), val);
10094
10095         bnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_RESET);
10096
10097         ecore_init_block(sc, BLOCK_MISC, PHASE_COMMON);
10098
10099         if (!CHIP_IS_E1x(sc)) {
10100 /*
10101  * 4-port mode or 2-port mode we need to turn off master-enable for
10102  * everyone. After that we turn it back on for self. So, we disregard
10103  * multi-function, and always disable all functions on the given path,
10104  * this means 0,2,4,6 for path 0 and 1,3,5,7 for path 1
10105  */
10106                 for (abs_func_id = SC_PATH(sc);
10107                      abs_func_id < (E2_FUNC_MAX * 2); abs_func_id += 2) {
10108                         if (abs_func_id == SC_ABS_FUNC(sc)) {
10109                                 REG_WR(sc,
10110                                        PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER,
10111                                        1);
10112                                 continue;
10113                         }
10114
10115                         bnx2x_pretend_func(sc, abs_func_id);
10116
10117                         /* clear pf enable */
10118                         bnx2x_pf_disable(sc);
10119
10120                         bnx2x_pretend_func(sc, SC_ABS_FUNC(sc));
10121                 }
10122         }
10123
10124         ecore_init_block(sc, BLOCK_PXP, PHASE_COMMON);
10125
10126         ecore_init_block(sc, BLOCK_PXP2, PHASE_COMMON);
10127         bnx2x_init_pxp(sc);
10128
10129 #ifdef __BIG_ENDIAN
10130         REG_WR(sc, PXP2_REG_RQ_QM_ENDIAN_M, 1);
10131         REG_WR(sc, PXP2_REG_RQ_TM_ENDIAN_M, 1);
10132         REG_WR(sc, PXP2_REG_RQ_SRC_ENDIAN_M, 1);
10133         REG_WR(sc, PXP2_REG_RQ_CDU_ENDIAN_M, 1);
10134         REG_WR(sc, PXP2_REG_RQ_DBG_ENDIAN_M, 1);
10135         /* make sure this value is 0 */
10136         REG_WR(sc, PXP2_REG_RQ_HC_ENDIAN_M, 0);
10137
10138         //REG_WR(sc, PXP2_REG_RD_PBF_SWAP_MODE, 1);
10139         REG_WR(sc, PXP2_REG_RD_QM_SWAP_MODE, 1);
10140         REG_WR(sc, PXP2_REG_RD_TM_SWAP_MODE, 1);
10141         REG_WR(sc, PXP2_REG_RD_SRC_SWAP_MODE, 1);
10142         REG_WR(sc, PXP2_REG_RD_CDURD_SWAP_MODE, 1);
10143 #endif
10144
10145         ecore_ilt_init_page_size(sc, INITOP_SET);
10146
10147         if (CHIP_REV_IS_FPGA(sc) && CHIP_IS_E1H(sc)) {
10148                 REG_WR(sc, PXP2_REG_PGL_TAGS_LIMIT, 0x1);
10149         }
10150
10151         /* let the HW do it's magic... */
10152         DELAY(100000);
10153
10154         /* finish PXP init */
10155
10156         val = REG_RD(sc, PXP2_REG_RQ_CFG_DONE);
10157         if (val != 1) {
10158                 PMD_DRV_LOG(NOTICE, sc, "PXP2 CFG failed");
10159                 return -1;
10160         }
10161         val = REG_RD(sc, PXP2_REG_RD_INIT_DONE);
10162         if (val != 1) {
10163                 PMD_DRV_LOG(NOTICE, sc, "PXP2 RD_INIT failed");
10164                 return -1;
10165         }
10166
10167         /*
10168          * Timer bug workaround for E2 only. We need to set the entire ILT to have
10169          * entries with value "0" and valid bit on. This needs to be done by the
10170          * first PF that is loaded in a path (i.e. common phase)
10171          */
10172         if (!CHIP_IS_E1x(sc)) {
10173 /*
10174  * In E2 there is a bug in the timers block that can cause function 6 / 7
10175  * (i.e. vnic3) to start even if it is marked as "scan-off".
10176  * This occurs when a different function (func2,3) is being marked
10177  * as "scan-off". Real-life scenario for example: if a driver is being
10178  * load-unloaded while func6,7 are down. This will cause the timer to access
10179  * the ilt, translate to a logical address and send a request to read/write.
10180  * Since the ilt for the function that is down is not valid, this will cause
10181  * a translation error which is unrecoverable.
10182  * The Workaround is intended to make sure that when this happens nothing
10183  * fatal will occur. The workaround:
10184  *  1.  First PF driver which loads on a path will:
10185  *      a.  After taking the chip out of reset, by using pretend,
10186  *          it will write "0" to the following registers of
10187  *          the other vnics.
10188  *          REG_WR(pdev, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 0);
10189  *          REG_WR(pdev, CFC_REG_WEAK_ENABLE_PF,0);
10190  *          REG_WR(pdev, CFC_REG_STRONG_ENABLE_PF,0);
10191  *          And for itself it will write '1' to
10192  *          PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER to enable
10193  *          dmae-operations (writing to pram for example.)
10194  *          note: can be done for only function 6,7 but cleaner this
10195  *            way.
10196  *      b.  Write zero+valid to the entire ILT.
10197  *      c.  Init the first_timers_ilt_entry, last_timers_ilt_entry of
10198  *          VNIC3 (of that port). The range allocated will be the
10199  *          entire ILT. This is needed to prevent  ILT range error.
10200  *  2.  Any PF driver load flow:
10201  *      a.  ILT update with the physical addresses of the allocated
10202  *          logical pages.
10203  *      b.  Wait 20msec. - note that this timeout is needed to make
10204  *          sure there are no requests in one of the PXP internal
10205  *          queues with "old" ILT addresses.
10206  *      c.  PF enable in the PGLC.
10207  *      d.  Clear the was_error of the PF in the PGLC. (could have
10208  *          occurred while driver was down)
10209  *      e.  PF enable in the CFC (WEAK + STRONG)
10210  *      f.  Timers scan enable
10211  *  3.  PF driver unload flow:
10212  *      a.  Clear the Timers scan_en.
10213  *      b.  Polling for scan_on=0 for that PF.
10214  *      c.  Clear the PF enable bit in the PXP.
10215  *      d.  Clear the PF enable in the CFC (WEAK + STRONG)
10216  *      e.  Write zero+valid to all ILT entries (The valid bit must
10217  *          stay set)
10218  *      f.  If this is VNIC 3 of a port then also init
10219  *          first_timers_ilt_entry to zero and last_timers_ilt_entry
10220  *          to the last enrty in the ILT.
10221  *
10222  *      Notes:
10223  *      Currently the PF error in the PGLC is non recoverable.
10224  *      In the future the there will be a recovery routine for this error.
10225  *      Currently attention is masked.
10226  *      Having an MCP lock on the load/unload process does not guarantee that
10227  *      there is no Timer disable during Func6/7 enable. This is because the
10228  *      Timers scan is currently being cleared by the MCP on FLR.
10229  *      Step 2.d can be done only for PF6/7 and the driver can also check if
10230  *      there is error before clearing it. But the flow above is simpler and
10231  *      more general.
10232  *      All ILT entries are written by zero+valid and not just PF6/7
10233  *      ILT entries since in the future the ILT entries allocation for
10234  *      PF-s might be dynamic.
10235  */
10236                 struct ilt_client_info ilt_cli;
10237                 struct ecore_ilt ilt;
10238
10239                 memset(&ilt_cli, 0, sizeof(struct ilt_client_info));
10240                 memset(&ilt, 0, sizeof(struct ecore_ilt));
10241
10242 /* initialize dummy TM client */
10243                 ilt_cli.start = 0;
10244                 ilt_cli.end = ILT_NUM_PAGE_ENTRIES - 1;
10245                 ilt_cli.client_num = ILT_CLIENT_TM;
10246
10247 /*
10248  * Step 1: set zeroes to all ilt page entries with valid bit on
10249  * Step 2: set the timers first/last ilt entry to point
10250  * to the entire range to prevent ILT range error for 3rd/4th
10251  * vnic (this code assumes existence of the vnic)
10252  *
10253  * both steps performed by call to ecore_ilt_client_init_op()
10254  * with dummy TM client
10255  *
10256  * we must use pretend since PXP2_REG_RQ_##blk##_FIRST_ILT
10257  * and his brother are split registers
10258  */
10259
10260                 bnx2x_pretend_func(sc, (SC_PATH(sc) + 6));
10261                 ecore_ilt_client_init_op_ilt(sc, &ilt, &ilt_cli, INITOP_CLEAR);
10262                 bnx2x_pretend_func(sc, SC_ABS_FUNC(sc));
10263
10264                 REG_WR(sc, PXP2_REG_RQ_DRAM_ALIGN, BNX2X_PXP_DRAM_ALIGN);
10265                 REG_WR(sc, PXP2_REG_RQ_DRAM_ALIGN_RD, BNX2X_PXP_DRAM_ALIGN);
10266                 REG_WR(sc, PXP2_REG_RQ_DRAM_ALIGN_SEL, 1);
10267         }
10268
10269         REG_WR(sc, PXP2_REG_RQ_DISABLE_INPUTS, 0);
10270         REG_WR(sc, PXP2_REG_RD_DISABLE_INPUTS, 0);
10271
10272         if (!CHIP_IS_E1x(sc)) {
10273                 int factor = 0;
10274
10275                 ecore_init_block(sc, BLOCK_PGLUE_B, PHASE_COMMON);
10276                 ecore_init_block(sc, BLOCK_ATC, PHASE_COMMON);
10277
10278 /* let the HW do it's magic... */
10279                 do {
10280                         DELAY(200000);
10281                         val = REG_RD(sc, ATC_REG_ATC_INIT_DONE);
10282                 } while (factor-- && (val != 1));
10283
10284                 if (val != 1) {
10285                         PMD_DRV_LOG(NOTICE, sc, "ATC_INIT failed");
10286                         return -1;
10287                 }
10288         }
10289
10290         ecore_init_block(sc, BLOCK_DMAE, PHASE_COMMON);
10291
10292         /* clean the DMAE memory */
10293         sc->dmae_ready = 1;
10294         ecore_init_fill(sc, TSEM_REG_PRAM, 0, 8);
10295
10296         ecore_init_block(sc, BLOCK_TCM, PHASE_COMMON);
10297
10298         ecore_init_block(sc, BLOCK_UCM, PHASE_COMMON);
10299
10300         ecore_init_block(sc, BLOCK_CCM, PHASE_COMMON);
10301
10302         ecore_init_block(sc, BLOCK_XCM, PHASE_COMMON);
10303
10304         bnx2x_read_dmae(sc, XSEM_REG_PASSIVE_BUFFER, 3);
10305         bnx2x_read_dmae(sc, CSEM_REG_PASSIVE_BUFFER, 3);
10306         bnx2x_read_dmae(sc, TSEM_REG_PASSIVE_BUFFER, 3);
10307         bnx2x_read_dmae(sc, USEM_REG_PASSIVE_BUFFER, 3);
10308
10309         ecore_init_block(sc, BLOCK_QM, PHASE_COMMON);
10310
10311         /* QM queues pointers table */
10312         ecore_qm_init_ptr_table(sc, sc->qm_cid_count, INITOP_SET);
10313
10314         /* soft reset pulse */
10315         REG_WR(sc, QM_REG_SOFT_RESET, 1);
10316         REG_WR(sc, QM_REG_SOFT_RESET, 0);
10317
10318         if (CNIC_SUPPORT(sc))
10319                 ecore_init_block(sc, BLOCK_TM, PHASE_COMMON);
10320
10321         ecore_init_block(sc, BLOCK_DORQ, PHASE_COMMON);
10322         REG_WR(sc, DORQ_REG_DPM_CID_OFST, BNX2X_DB_SHIFT);
10323
10324         if (!CHIP_REV_IS_SLOW(sc)) {
10325 /* enable hw interrupt from doorbell Q */
10326                 REG_WR(sc, DORQ_REG_DORQ_INT_MASK, 0);
10327         }
10328
10329         ecore_init_block(sc, BLOCK_BRB1, PHASE_COMMON);
10330
10331         ecore_init_block(sc, BLOCK_PRS, PHASE_COMMON);
10332         REG_WR(sc, PRS_REG_A_PRSU_20, 0xf);
10333         REG_WR(sc, PRS_REG_E1HOV_MODE, sc->devinfo.mf_info.path_has_ovlan);
10334
10335         if (!CHIP_IS_E1x(sc) && !CHIP_IS_E3B0(sc)) {
10336                 if (IS_MF_AFEX(sc)) {
10337                         /*
10338                          * configure that AFEX and VLAN headers must be
10339                          * received in AFEX mode
10340                          */
10341                         REG_WR(sc, PRS_REG_HDRS_AFTER_BASIC, 0xE);
10342                         REG_WR(sc, PRS_REG_MUST_HAVE_HDRS, 0xA);
10343                         REG_WR(sc, PRS_REG_HDRS_AFTER_TAG_0, 0x6);
10344                         REG_WR(sc, PRS_REG_TAG_ETHERTYPE_0, 0x8926);
10345                         REG_WR(sc, PRS_REG_TAG_LEN_0, 0x4);
10346                 } else {
10347                         /*
10348                          * Bit-map indicating which L2 hdrs may appear
10349                          * after the basic Ethernet header
10350                          */
10351                         REG_WR(sc, PRS_REG_HDRS_AFTER_BASIC,
10352                                sc->devinfo.mf_info.path_has_ovlan ? 7 : 6);
10353                 }
10354         }
10355
10356         ecore_init_block(sc, BLOCK_TSDM, PHASE_COMMON);
10357         ecore_init_block(sc, BLOCK_CSDM, PHASE_COMMON);
10358         ecore_init_block(sc, BLOCK_USDM, PHASE_COMMON);
10359         ecore_init_block(sc, BLOCK_XSDM, PHASE_COMMON);
10360
10361         if (!CHIP_IS_E1x(sc)) {
10362 /* reset VFC memories */
10363                 REG_WR(sc, TSEM_REG_FAST_MEMORY + VFC_REG_MEMORIES_RST,
10364                        VFC_MEMORIES_RST_REG_CAM_RST |
10365                        VFC_MEMORIES_RST_REG_RAM_RST);
10366                 REG_WR(sc, XSEM_REG_FAST_MEMORY + VFC_REG_MEMORIES_RST,
10367                        VFC_MEMORIES_RST_REG_CAM_RST |
10368                        VFC_MEMORIES_RST_REG_RAM_RST);
10369
10370                 DELAY(20000);
10371         }
10372
10373         ecore_init_block(sc, BLOCK_TSEM, PHASE_COMMON);
10374         ecore_init_block(sc, BLOCK_USEM, PHASE_COMMON);
10375         ecore_init_block(sc, BLOCK_CSEM, PHASE_COMMON);
10376         ecore_init_block(sc, BLOCK_XSEM, PHASE_COMMON);
10377
10378         /* sync semi rtc */
10379         REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR, 0x80000000);
10380         REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, 0x80000000);
10381
10382         ecore_init_block(sc, BLOCK_UPB, PHASE_COMMON);
10383         ecore_init_block(sc, BLOCK_XPB, PHASE_COMMON);
10384         ecore_init_block(sc, BLOCK_PBF, PHASE_COMMON);
10385
10386         if (!CHIP_IS_E1x(sc)) {
10387                 if (IS_MF_AFEX(sc)) {
10388                         /*
10389                          * configure that AFEX and VLAN headers must be
10390                          * sent in AFEX mode
10391                          */
10392                         REG_WR(sc, PBF_REG_HDRS_AFTER_BASIC, 0xE);
10393                         REG_WR(sc, PBF_REG_MUST_HAVE_HDRS, 0xA);
10394                         REG_WR(sc, PBF_REG_HDRS_AFTER_TAG_0, 0x6);
10395                         REG_WR(sc, PBF_REG_TAG_ETHERTYPE_0, 0x8926);
10396                         REG_WR(sc, PBF_REG_TAG_LEN_0, 0x4);
10397                 } else {
10398                         REG_WR(sc, PBF_REG_HDRS_AFTER_BASIC,
10399                                sc->devinfo.mf_info.path_has_ovlan ? 7 : 6);
10400                 }
10401         }
10402
10403         REG_WR(sc, SRC_REG_SOFT_RST, 1);
10404
10405         ecore_init_block(sc, BLOCK_SRC, PHASE_COMMON);
10406
10407         if (CNIC_SUPPORT(sc)) {
10408                 REG_WR(sc, SRC_REG_KEYSEARCH_0, 0x63285672);
10409                 REG_WR(sc, SRC_REG_KEYSEARCH_1, 0x24b8f2cc);
10410                 REG_WR(sc, SRC_REG_KEYSEARCH_2, 0x223aef9b);
10411                 REG_WR(sc, SRC_REG_KEYSEARCH_3, 0x26001e3a);
10412                 REG_WR(sc, SRC_REG_KEYSEARCH_4, 0x7ae91116);
10413                 REG_WR(sc, SRC_REG_KEYSEARCH_5, 0x5ce5230b);
10414                 REG_WR(sc, SRC_REG_KEYSEARCH_6, 0x298d8adf);
10415                 REG_WR(sc, SRC_REG_KEYSEARCH_7, 0x6eb0ff09);
10416                 REG_WR(sc, SRC_REG_KEYSEARCH_8, 0x1830f82f);
10417                 REG_WR(sc, SRC_REG_KEYSEARCH_9, 0x01e46be7);
10418         }
10419         REG_WR(sc, SRC_REG_SOFT_RST, 0);
10420
10421         if (sizeof(union cdu_context) != 1024) {
10422 /* we currently assume that a context is 1024 bytes */
10423                 PMD_DRV_LOG(NOTICE, sc,
10424                             "please adjust the size of cdu_context(%ld)",
10425                             (long)sizeof(union cdu_context));
10426         }
10427
10428         ecore_init_block(sc, BLOCK_CDU, PHASE_COMMON);
10429         val = (4 << 24) + (0 << 12) + 1024;
10430         REG_WR(sc, CDU_REG_CDU_GLOBAL_PARAMS, val);
10431
10432         ecore_init_block(sc, BLOCK_CFC, PHASE_COMMON);
10433
10434         REG_WR(sc, CFC_REG_INIT_REG, 0x7FF);
10435         /* enable context validation interrupt from CFC */
10436         REG_WR(sc, CFC_REG_CFC_INT_MASK, 0);
10437
10438         /* set the thresholds to prevent CFC/CDU race */
10439         REG_WR(sc, CFC_REG_DEBUG0, 0x20020000);
10440         ecore_init_block(sc, BLOCK_HC, PHASE_COMMON);
10441
10442         if (!CHIP_IS_E1x(sc) && BNX2X_NOMCP(sc)) {
10443                 REG_WR(sc, IGU_REG_RESET_MEMORIES, 0x36);
10444         }
10445
10446         ecore_init_block(sc, BLOCK_IGU, PHASE_COMMON);
10447         ecore_init_block(sc, BLOCK_MISC_AEU, PHASE_COMMON);
10448
10449         /* Reset PCIE errors for debug */
10450         REG_WR(sc, 0x2814, 0xffffffff);
10451         REG_WR(sc, 0x3820, 0xffffffff);
10452
10453         if (!CHIP_IS_E1x(sc)) {
10454                 REG_WR(sc, PCICFG_OFFSET + PXPCS_TL_CONTROL_5,
10455                        (PXPCS_TL_CONTROL_5_ERR_UNSPPORT1 |
10456                         PXPCS_TL_CONTROL_5_ERR_UNSPPORT));
10457                 REG_WR(sc, PCICFG_OFFSET + PXPCS_TL_FUNC345_STAT,
10458                        (PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT4 |
10459                         PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT3 |
10460                         PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT2));
10461                 REG_WR(sc, PCICFG_OFFSET + PXPCS_TL_FUNC678_STAT,
10462                        (PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT7 |
10463                         PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT6 |
10464                         PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT5));
10465         }
10466
10467         ecore_init_block(sc, BLOCK_NIG, PHASE_COMMON);
10468
10469         /* in E3 this done in per-port section */
10470         if (!CHIP_IS_E3(sc))
10471                 REG_WR(sc, NIG_REG_LLH_MF_MODE, IS_MF(sc));
10472
10473         if (CHIP_IS_E1H(sc)) {
10474 /* not applicable for E2 (and above ...) */
10475                 REG_WR(sc, NIG_REG_LLH_E1HOV_MODE, IS_MF_SD(sc));
10476         }
10477
10478         if (CHIP_REV_IS_SLOW(sc)) {
10479                 DELAY(200000);
10480         }
10481
10482         /* finish CFC init */
10483         val = reg_poll(sc, CFC_REG_LL_INIT_DONE, 1, 100, 10);
10484         if (val != 1) {
10485                 PMD_DRV_LOG(NOTICE, sc, "CFC LL_INIT failed");
10486                 return -1;
10487         }
10488         val = reg_poll(sc, CFC_REG_AC_INIT_DONE, 1, 100, 10);
10489         if (val != 1) {
10490                 PMD_DRV_LOG(NOTICE, sc, "CFC AC_INIT failed");
10491                 return -1;
10492         }
10493         val = reg_poll(sc, CFC_REG_CAM_INIT_DONE, 1, 100, 10);
10494         if (val != 1) {
10495                 PMD_DRV_LOG(NOTICE, sc, "CFC CAM_INIT failed");
10496                 return -1;
10497         }
10498         REG_WR(sc, CFC_REG_DEBUG0, 0);
10499
10500         bnx2x_setup_fan_failure_detection(sc);
10501
10502         /* clear PXP2 attentions */
10503         REG_RD(sc, PXP2_REG_PXP2_INT_STS_CLR_0);
10504
10505         bnx2x_enable_blocks_attention(sc);
10506
10507         if (!CHIP_REV_IS_SLOW(sc)) {
10508                 ecore_enable_blocks_parity(sc);
10509         }
10510
10511         if (!BNX2X_NOMCP(sc)) {
10512                 if (CHIP_IS_E1x(sc)) {
10513                         bnx2x_common_init_phy(sc);
10514                 }
10515         }
10516
10517         return 0;
10518 }
10519
10520 /**
10521  * bnx2x_init_hw_common_chip - init HW at the COMMON_CHIP phase.
10522  *
10523  * @sc:     driver handle
10524  */
10525 static int bnx2x_init_hw_common_chip(struct bnx2x_softc *sc)
10526 {
10527         int rc = bnx2x_init_hw_common(sc);
10528
10529         if (rc) {
10530                 return rc;
10531         }
10532
10533         /* In E2 2-PORT mode, same ext phy is used for the two paths */
10534         if (!BNX2X_NOMCP(sc)) {
10535                 bnx2x_common_init_phy(sc);
10536         }
10537
10538         return 0;
10539 }
10540
10541 static int bnx2x_init_hw_port(struct bnx2x_softc *sc)
10542 {
10543         int port = SC_PORT(sc);
10544         int init_phase = port ? PHASE_PORT1 : PHASE_PORT0;
10545         uint32_t low, high;
10546         uint32_t val;
10547
10548         PMD_DRV_LOG(DEBUG, sc, "starting port init for port %d", port);
10549
10550         REG_WR(sc, NIG_REG_MASK_INTERRUPT_PORT0 + port * 4, 0);
10551
10552         ecore_init_block(sc, BLOCK_MISC, init_phase);
10553         ecore_init_block(sc, BLOCK_PXP, init_phase);
10554         ecore_init_block(sc, BLOCK_PXP2, init_phase);
10555
10556         /*
10557          * Timers bug workaround: disables the pf_master bit in pglue at
10558          * common phase, we need to enable it here before any dmae access are
10559          * attempted. Therefore we manually added the enable-master to the
10560          * port phase (it also happens in the function phase)
10561          */
10562         if (!CHIP_IS_E1x(sc)) {
10563                 REG_WR(sc, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 1);
10564         }
10565
10566         ecore_init_block(sc, BLOCK_ATC, init_phase);
10567         ecore_init_block(sc, BLOCK_DMAE, init_phase);
10568         ecore_init_block(sc, BLOCK_PGLUE_B, init_phase);
10569         ecore_init_block(sc, BLOCK_QM, init_phase);
10570
10571         ecore_init_block(sc, BLOCK_TCM, init_phase);
10572         ecore_init_block(sc, BLOCK_UCM, init_phase);
10573         ecore_init_block(sc, BLOCK_CCM, init_phase);
10574         ecore_init_block(sc, BLOCK_XCM, init_phase);
10575
10576         /* QM cid (connection) count */
10577         ecore_qm_init_cid_count(sc, sc->qm_cid_count, INITOP_SET);
10578
10579         if (CNIC_SUPPORT(sc)) {
10580                 ecore_init_block(sc, BLOCK_TM, init_phase);
10581                 REG_WR(sc, TM_REG_LIN0_SCAN_TIME + port * 4, 20);
10582                 REG_WR(sc, TM_REG_LIN0_MAX_ACTIVE_CID + port * 4, 31);
10583         }
10584
10585         ecore_init_block(sc, BLOCK_DORQ, init_phase);
10586
10587         ecore_init_block(sc, BLOCK_BRB1, init_phase);
10588
10589         if (CHIP_IS_E1H(sc)) {
10590                 if (IS_MF(sc)) {
10591                         low = (BNX2X_ONE_PORT(sc) ? 160 : 246);
10592                 } else if (sc->mtu > 4096) {
10593                         if (BNX2X_ONE_PORT(sc)) {
10594                                 low = 160;
10595                         } else {
10596                                 val = sc->mtu;
10597                                 /* (24*1024 + val*4)/256 */
10598                                 low = (96 + (val / 64) + ((val % 64) ? 1 : 0));
10599                         }
10600                 } else {
10601                         low = (BNX2X_ONE_PORT(sc) ? 80 : 160);
10602                 }
10603                 high = (low + 56);      /* 14*1024/256 */
10604                 REG_WR(sc, BRB1_REG_PAUSE_LOW_THRESHOLD_0 + port * 4, low);
10605                 REG_WR(sc, BRB1_REG_PAUSE_HIGH_THRESHOLD_0 + port * 4, high);
10606         }
10607
10608         if (CHIP_IS_MODE_4_PORT(sc)) {
10609                 REG_WR(sc, SC_PORT(sc) ?
10610                        BRB1_REG_MAC_GUARANTIED_1 :
10611                        BRB1_REG_MAC_GUARANTIED_0, 40);
10612         }
10613
10614         ecore_init_block(sc, BLOCK_PRS, init_phase);
10615         if (CHIP_IS_E3B0(sc)) {
10616                 if (IS_MF_AFEX(sc)) {
10617                         /* configure headers for AFEX mode */
10618                         if (SC_PORT(sc)) {
10619                                 REG_WR(sc, PRS_REG_HDRS_AFTER_BASIC_PORT_1,
10620                                        0xE);
10621                                 REG_WR(sc, PRS_REG_HDRS_AFTER_TAG_0_PORT_1,
10622                                        0x6);
10623                                 REG_WR(sc, PRS_REG_MUST_HAVE_HDRS_PORT_1, 0xA);
10624                         } else {
10625                                 REG_WR(sc, PRS_REG_HDRS_AFTER_BASIC_PORT_0,
10626                                        0xE);
10627                                 REG_WR(sc, PRS_REG_HDRS_AFTER_TAG_0_PORT_0,
10628                                        0x6);
10629                                 REG_WR(sc, PRS_REG_MUST_HAVE_HDRS_PORT_0, 0xA);
10630                         }
10631                 } else {
10632                         /* Ovlan exists only if we are in multi-function +
10633                          * switch-dependent mode, in switch-independent there
10634                          * is no ovlan headers
10635                          */
10636                         REG_WR(sc, SC_PORT(sc) ?
10637                                PRS_REG_HDRS_AFTER_BASIC_PORT_1 :
10638                                PRS_REG_HDRS_AFTER_BASIC_PORT_0,
10639                                (sc->devinfo.mf_info.path_has_ovlan ? 7 : 6));
10640                 }
10641         }
10642
10643         ecore_init_block(sc, BLOCK_TSDM, init_phase);
10644         ecore_init_block(sc, BLOCK_CSDM, init_phase);
10645         ecore_init_block(sc, BLOCK_USDM, init_phase);
10646         ecore_init_block(sc, BLOCK_XSDM, init_phase);
10647
10648         ecore_init_block(sc, BLOCK_TSEM, init_phase);
10649         ecore_init_block(sc, BLOCK_USEM, init_phase);
10650         ecore_init_block(sc, BLOCK_CSEM, init_phase);
10651         ecore_init_block(sc, BLOCK_XSEM, init_phase);
10652
10653         ecore_init_block(sc, BLOCK_UPB, init_phase);
10654         ecore_init_block(sc, BLOCK_XPB, init_phase);
10655
10656         ecore_init_block(sc, BLOCK_PBF, init_phase);
10657
10658         if (CHIP_IS_E1x(sc)) {
10659 /* configure PBF to work without PAUSE mtu 9000 */
10660                 REG_WR(sc, PBF_REG_P0_PAUSE_ENABLE + port * 4, 0);
10661
10662 /* update threshold */
10663                 REG_WR(sc, PBF_REG_P0_ARB_THRSH + port * 4, (9040 / 16));
10664 /* update init credit */
10665                 REG_WR(sc, PBF_REG_P0_INIT_CRD + port * 4,
10666                        (9040 / 16) + 553 - 22);
10667
10668 /* probe changes */
10669                 REG_WR(sc, PBF_REG_INIT_P0 + port * 4, 1);
10670                 DELAY(50);
10671                 REG_WR(sc, PBF_REG_INIT_P0 + port * 4, 0);
10672         }
10673
10674         if (CNIC_SUPPORT(sc)) {
10675                 ecore_init_block(sc, BLOCK_SRC, init_phase);
10676         }
10677
10678         ecore_init_block(sc, BLOCK_CDU, init_phase);
10679         ecore_init_block(sc, BLOCK_CFC, init_phase);
10680         ecore_init_block(sc, BLOCK_HC, init_phase);
10681         ecore_init_block(sc, BLOCK_IGU, init_phase);
10682         ecore_init_block(sc, BLOCK_MISC_AEU, init_phase);
10683         /* init aeu_mask_attn_func_0/1:
10684          *  - SF mode: bits 3-7 are masked. only bits 0-2 are in use
10685          *  - MF mode: bit 3 is masked. bits 0-2 are in use as in SF
10686          *             bits 4-7 are used for "per vn group attention" */
10687         val = IS_MF(sc) ? 0xF7 : 0x7;
10688         val |= 0x10;
10689         REG_WR(sc, MISC_REG_AEU_MASK_ATTN_FUNC_0 + port * 4, val);
10690
10691         ecore_init_block(sc, BLOCK_NIG, init_phase);
10692
10693         if (!CHIP_IS_E1x(sc)) {
10694 /* Bit-map indicating which L2 hdrs may appear after the
10695  * basic Ethernet header
10696  */
10697                 if (IS_MF_AFEX(sc)) {
10698                         REG_WR(sc, SC_PORT(sc) ?
10699                                NIG_REG_P1_HDRS_AFTER_BASIC :
10700                                NIG_REG_P0_HDRS_AFTER_BASIC, 0xE);
10701                 } else {
10702                         REG_WR(sc, SC_PORT(sc) ?
10703                                NIG_REG_P1_HDRS_AFTER_BASIC :
10704                                NIG_REG_P0_HDRS_AFTER_BASIC,
10705                                IS_MF_SD(sc) ? 7 : 6);
10706                 }
10707
10708                 if (CHIP_IS_E3(sc)) {
10709                         REG_WR(sc, SC_PORT(sc) ?
10710                                NIG_REG_LLH1_MF_MODE :
10711                                NIG_REG_LLH_MF_MODE, IS_MF(sc));
10712                 }
10713         }
10714         if (!CHIP_IS_E3(sc)) {
10715                 REG_WR(sc, NIG_REG_XGXS_SERDES0_MODE_SEL + port * 4, 1);
10716         }
10717
10718         /* 0x2 disable mf_ov, 0x1 enable */
10719         REG_WR(sc, NIG_REG_LLH0_BRB1_DRV_MASK_MF + port * 4,
10720                (IS_MF_SD(sc) ? 0x1 : 0x2));
10721
10722         if (!CHIP_IS_E1x(sc)) {
10723                 val = 0;
10724                 switch (sc->devinfo.mf_info.mf_mode) {
10725                 case MULTI_FUNCTION_SD:
10726                         val = 1;
10727                         break;
10728                 case MULTI_FUNCTION_SI:
10729                 case MULTI_FUNCTION_AFEX:
10730                         val = 2;
10731                         break;
10732                 }
10733
10734                 REG_WR(sc, (SC_PORT(sc) ? NIG_REG_LLH1_CLS_TYPE :
10735                             NIG_REG_LLH0_CLS_TYPE), val);
10736         }
10737         REG_WR(sc, NIG_REG_LLFC_ENABLE_0 + port * 4, 0);
10738         REG_WR(sc, NIG_REG_LLFC_OUT_EN_0 + port * 4, 0);
10739         REG_WR(sc, NIG_REG_PAUSE_ENABLE_0 + port * 4, 1);
10740
10741         /* If SPIO5 is set to generate interrupts, enable it for this port */
10742         val = REG_RD(sc, MISC_REG_SPIO_EVENT_EN);
10743         if (val & MISC_SPIO_SPIO5) {
10744                 uint32_t reg_addr = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 :
10745                                      MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0);
10746                 val = REG_RD(sc, reg_addr);
10747                 val |= AEU_INPUTS_ATTN_BITS_SPIO5;
10748                 REG_WR(sc, reg_addr, val);
10749         }
10750
10751         return 0;
10752 }
10753
10754 static uint32_t
10755 bnx2x_flr_clnup_reg_poll(struct bnx2x_softc *sc, uint32_t reg,
10756                        uint32_t expected, uint32_t poll_count)
10757 {
10758         uint32_t cur_cnt = poll_count;
10759         uint32_t val;
10760
10761         while ((val = REG_RD(sc, reg)) != expected && cur_cnt--) {
10762                 DELAY(FLR_WAIT_INTERVAL);
10763         }
10764
10765         return val;
10766 }
10767
10768 static int
10769 bnx2x_flr_clnup_poll_hw_counter(struct bnx2x_softc *sc, uint32_t reg,
10770                               __rte_unused const char *msg, uint32_t poll_cnt)
10771 {
10772         uint32_t val = bnx2x_flr_clnup_reg_poll(sc, reg, 0, poll_cnt);
10773
10774         if (val != 0) {
10775                 PMD_DRV_LOG(NOTICE, sc, "%s usage count=%d", msg, val);
10776                 return -1;
10777         }
10778
10779         return 0;
10780 }
10781
10782 /* Common routines with VF FLR cleanup */
10783 static uint32_t bnx2x_flr_clnup_poll_count(struct bnx2x_softc *sc)
10784 {
10785         /* adjust polling timeout */
10786         if (CHIP_REV_IS_EMUL(sc)) {
10787                 return FLR_POLL_CNT * 2000;
10788         }
10789
10790         if (CHIP_REV_IS_FPGA(sc)) {
10791                 return FLR_POLL_CNT * 120;
10792         }
10793
10794         return FLR_POLL_CNT;
10795 }
10796
10797 static int bnx2x_poll_hw_usage_counters(struct bnx2x_softc *sc, uint32_t poll_cnt)
10798 {
10799         /* wait for CFC PF usage-counter to zero (includes all the VFs) */
10800         if (bnx2x_flr_clnup_poll_hw_counter(sc,
10801                                           CFC_REG_NUM_LCIDS_INSIDE_PF,
10802                                           "CFC PF usage counter timed out",
10803                                           poll_cnt)) {
10804                 return -1;
10805         }
10806
10807         /* Wait for DQ PF usage-counter to zero (until DQ cleanup) */
10808         if (bnx2x_flr_clnup_poll_hw_counter(sc,
10809                                           DORQ_REG_PF_USAGE_CNT,
10810                                           "DQ PF usage counter timed out",
10811                                           poll_cnt)) {
10812                 return -1;
10813         }
10814
10815         /* Wait for QM PF usage-counter to zero (until DQ cleanup) */
10816         if (bnx2x_flr_clnup_poll_hw_counter(sc,
10817                                           QM_REG_PF_USG_CNT_0 + 4 * SC_FUNC(sc),
10818                                           "QM PF usage counter timed out",
10819                                           poll_cnt)) {
10820                 return -1;
10821         }
10822
10823         /* Wait for Timer PF usage-counters to zero (until DQ cleanup) */
10824         if (bnx2x_flr_clnup_poll_hw_counter(sc,
10825                                           TM_REG_LIN0_VNIC_UC + 4 * SC_PORT(sc),
10826                                           "Timers VNIC usage counter timed out",
10827                                           poll_cnt)) {
10828                 return -1;
10829         }
10830
10831         if (bnx2x_flr_clnup_poll_hw_counter(sc,
10832                                           TM_REG_LIN0_NUM_SCANS +
10833                                           4 * SC_PORT(sc),
10834                                           "Timers NUM_SCANS usage counter timed out",
10835                                           poll_cnt)) {
10836                 return -1;
10837         }
10838
10839         /* Wait DMAE PF usage counter to zero */
10840         if (bnx2x_flr_clnup_poll_hw_counter(sc,
10841                                           dmae_reg_go_c[INIT_DMAE_C(sc)],
10842                                           "DMAE dommand register timed out",
10843                                           poll_cnt)) {
10844                 return -1;
10845         }
10846
10847         return 0;
10848 }
10849
10850 #define OP_GEN_PARAM(param)                                            \
10851         (((param) << SDM_OP_GEN_COMP_PARAM_SHIFT) & SDM_OP_GEN_COMP_PARAM)
10852 #define OP_GEN_TYPE(type)                                           \
10853         (((type) << SDM_OP_GEN_COMP_TYPE_SHIFT) & SDM_OP_GEN_COMP_TYPE)
10854 #define OP_GEN_AGG_VECT(index)                                             \
10855         (((index) << SDM_OP_GEN_AGG_VECT_IDX_SHIFT) & SDM_OP_GEN_AGG_VECT_IDX)
10856
10857 static int
10858 bnx2x_send_final_clnup(struct bnx2x_softc *sc, uint8_t clnup_func,
10859                      uint32_t poll_cnt)
10860 {
10861         uint32_t op_gen_command = 0;
10862         uint32_t comp_addr = (BAR_CSTRORM_INTMEM +
10863                               CSTORM_FINAL_CLEANUP_COMPLETE_OFFSET(clnup_func));
10864         int ret = 0;
10865
10866         if (REG_RD(sc, comp_addr)) {
10867                 PMD_DRV_LOG(NOTICE, sc,
10868                             "Cleanup complete was not 0 before sending");
10869                 return -1;
10870         }
10871
10872         op_gen_command |= OP_GEN_PARAM(XSTORM_AGG_INT_FINAL_CLEANUP_INDEX);
10873         op_gen_command |= OP_GEN_TYPE(XSTORM_AGG_INT_FINAL_CLEANUP_COMP_TYPE);
10874         op_gen_command |= OP_GEN_AGG_VECT(clnup_func);
10875         op_gen_command |= 1 << SDM_OP_GEN_AGG_VECT_IDX_VALID_SHIFT;
10876
10877         REG_WR(sc, XSDM_REG_OPERATION_GEN, op_gen_command);
10878
10879         if (bnx2x_flr_clnup_reg_poll(sc, comp_addr, 1, poll_cnt) != 1) {
10880                 PMD_DRV_LOG(NOTICE, sc, "FW final cleanup did not succeed");
10881                 PMD_DRV_LOG(DEBUG, sc, "At timeout completion address contained %x",
10882                             (REG_RD(sc, comp_addr)));
10883                 rte_panic("FLR cleanup failed");
10884                 return -1;
10885         }
10886
10887         /* Zero completion for nxt FLR */
10888         REG_WR(sc, comp_addr, 0);
10889
10890         return ret;
10891 }
10892
10893 static void
10894 bnx2x_pbf_pN_buf_flushed(struct bnx2x_softc *sc, struct pbf_pN_buf_regs *regs,
10895                        uint32_t poll_count)
10896 {
10897         uint32_t init_crd, crd, crd_start, crd_freed, crd_freed_start;
10898         uint32_t cur_cnt = poll_count;
10899
10900         crd_freed = crd_freed_start = REG_RD(sc, regs->crd_freed);
10901         crd = crd_start = REG_RD(sc, regs->crd);
10902         init_crd = REG_RD(sc, regs->init_crd);
10903
10904         while ((crd != init_crd) &&
10905                ((uint32_t) ((int32_t) crd_freed - (int32_t) crd_freed_start) <
10906                 (init_crd - crd_start))) {
10907                 if (cur_cnt--) {
10908                         DELAY(FLR_WAIT_INTERVAL);
10909                         crd = REG_RD(sc, regs->crd);
10910                         crd_freed = REG_RD(sc, regs->crd_freed);
10911                 } else {
10912                         break;
10913                 }
10914         }
10915 }
10916
10917 static void
10918 bnx2x_pbf_pN_cmd_flushed(struct bnx2x_softc *sc, struct pbf_pN_cmd_regs *regs,
10919                        uint32_t poll_count)
10920 {
10921         uint32_t occup, to_free, freed, freed_start;
10922         uint32_t cur_cnt = poll_count;
10923
10924         occup = to_free = REG_RD(sc, regs->lines_occup);
10925         freed = freed_start = REG_RD(sc, regs->lines_freed);
10926
10927         while (occup &&
10928                ((uint32_t) ((int32_t) freed - (int32_t) freed_start) <
10929                 to_free)) {
10930                 if (cur_cnt--) {
10931                         DELAY(FLR_WAIT_INTERVAL);
10932                         occup = REG_RD(sc, regs->lines_occup);
10933                         freed = REG_RD(sc, regs->lines_freed);
10934                 } else {
10935                         break;
10936                 }
10937         }
10938 }
10939
10940 static void bnx2x_tx_hw_flushed(struct bnx2x_softc *sc, uint32_t poll_count)
10941 {
10942         struct pbf_pN_cmd_regs cmd_regs[] = {
10943                 {0, (CHIP_IS_E3B0(sc)) ?
10944                  PBF_REG_TQ_OCCUPANCY_Q0 : PBF_REG_P0_TQ_OCCUPANCY,
10945                  (CHIP_IS_E3B0(sc)) ?
10946                  PBF_REG_TQ_LINES_FREED_CNT_Q0 : PBF_REG_P0_TQ_LINES_FREED_CNT},
10947                 {1, (CHIP_IS_E3B0(sc)) ?
10948                  PBF_REG_TQ_OCCUPANCY_Q1 : PBF_REG_P1_TQ_OCCUPANCY,
10949                  (CHIP_IS_E3B0(sc)) ?
10950                  PBF_REG_TQ_LINES_FREED_CNT_Q1 : PBF_REG_P1_TQ_LINES_FREED_CNT},
10951                 {4, (CHIP_IS_E3B0(sc)) ?
10952                  PBF_REG_TQ_OCCUPANCY_LB_Q : PBF_REG_P4_TQ_OCCUPANCY,
10953                  (CHIP_IS_E3B0(sc)) ?
10954                  PBF_REG_TQ_LINES_FREED_CNT_LB_Q :
10955                  PBF_REG_P4_TQ_LINES_FREED_CNT}
10956         };
10957
10958         struct pbf_pN_buf_regs buf_regs[] = {
10959                 {0, (CHIP_IS_E3B0(sc)) ?
10960                  PBF_REG_INIT_CRD_Q0 : PBF_REG_P0_INIT_CRD,
10961                  (CHIP_IS_E3B0(sc)) ? PBF_REG_CREDIT_Q0 : PBF_REG_P0_CREDIT,
10962                  (CHIP_IS_E3B0(sc)) ?
10963                  PBF_REG_INTERNAL_CRD_FREED_CNT_Q0 :
10964                  PBF_REG_P0_INTERNAL_CRD_FREED_CNT},
10965                 {1, (CHIP_IS_E3B0(sc)) ?
10966                  PBF_REG_INIT_CRD_Q1 : PBF_REG_P1_INIT_CRD,
10967                  (CHIP_IS_E3B0(sc)) ? PBF_REG_CREDIT_Q1 : PBF_REG_P1_CREDIT,
10968                  (CHIP_IS_E3B0(sc)) ?
10969                  PBF_REG_INTERNAL_CRD_FREED_CNT_Q1 :
10970                  PBF_REG_P1_INTERNAL_CRD_FREED_CNT},
10971                 {4, (CHIP_IS_E3B0(sc)) ?
10972                  PBF_REG_INIT_CRD_LB_Q : PBF_REG_P4_INIT_CRD,
10973                  (CHIP_IS_E3B0(sc)) ? PBF_REG_CREDIT_LB_Q : PBF_REG_P4_CREDIT,
10974                  (CHIP_IS_E3B0(sc)) ?
10975                  PBF_REG_INTERNAL_CRD_FREED_CNT_LB_Q :
10976                  PBF_REG_P4_INTERNAL_CRD_FREED_CNT},
10977         };
10978
10979         uint32_t i;
10980
10981         /* Verify the command queues are flushed P0, P1, P4 */
10982         for (i = 0; i < ARRAY_SIZE(cmd_regs); i++) {
10983                 bnx2x_pbf_pN_cmd_flushed(sc, &cmd_regs[i], poll_count);
10984         }
10985
10986         /* Verify the transmission buffers are flushed P0, P1, P4 */
10987         for (i = 0; i < ARRAY_SIZE(buf_regs); i++) {
10988                 bnx2x_pbf_pN_buf_flushed(sc, &buf_regs[i], poll_count);
10989         }
10990 }
10991
10992 static void bnx2x_hw_enable_status(struct bnx2x_softc *sc)
10993 {
10994         __rte_unused uint32_t val;
10995
10996         val = REG_RD(sc, CFC_REG_WEAK_ENABLE_PF);
10997         PMD_DRV_LOG(DEBUG, sc, "CFC_REG_WEAK_ENABLE_PF is 0x%x", val);
10998
10999         val = REG_RD(sc, PBF_REG_DISABLE_PF);
11000         PMD_DRV_LOG(DEBUG, sc, "PBF_REG_DISABLE_PF is 0x%x", val);
11001
11002         val = REG_RD(sc, IGU_REG_PCI_PF_MSI_EN);
11003         PMD_DRV_LOG(DEBUG, sc, "IGU_REG_PCI_PF_MSI_EN is 0x%x", val);
11004
11005         val = REG_RD(sc, IGU_REG_PCI_PF_MSIX_EN);
11006         PMD_DRV_LOG(DEBUG, sc, "IGU_REG_PCI_PF_MSIX_EN is 0x%x", val);
11007
11008         val = REG_RD(sc, IGU_REG_PCI_PF_MSIX_FUNC_MASK);
11009         PMD_DRV_LOG(DEBUG, sc, "IGU_REG_PCI_PF_MSIX_FUNC_MASK is 0x%x", val);
11010
11011         val = REG_RD(sc, PGLUE_B_REG_SHADOW_BME_PF_7_0_CLR);
11012         PMD_DRV_LOG(DEBUG, sc,
11013                     "PGLUE_B_REG_SHADOW_BME_PF_7_0_CLR is 0x%x", val);
11014
11015         val = REG_RD(sc, PGLUE_B_REG_FLR_REQUEST_PF_7_0_CLR);
11016         PMD_DRV_LOG(DEBUG, sc,
11017                     "PGLUE_B_REG_FLR_REQUEST_PF_7_0_CLR is 0x%x", val);
11018
11019         val = REG_RD(sc, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER);
11020         PMD_DRV_LOG(DEBUG, sc, "PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER is 0x%x",
11021                     val);
11022 }
11023
11024 /**
11025  *      bnx2x_pf_flr_clnup
11026  *      a. re-enable target read on the PF
11027  *      b. poll cfc per function usgae counter
11028  *      c. poll the qm perfunction usage counter
11029  *      d. poll the tm per function usage counter
11030  *      e. poll the tm per function scan-done indication
11031  *      f. clear the dmae channel associated wit hthe PF
11032  *      g. zero the igu 'trailing edge' and 'leading edge' regs (attentions)
11033  *      h. call the common flr cleanup code with -1 (pf indication)
11034  */
11035 static int bnx2x_pf_flr_clnup(struct bnx2x_softc *sc)
11036 {
11037         uint32_t poll_cnt = bnx2x_flr_clnup_poll_count(sc);
11038
11039         /* Re-enable PF target read access */
11040         REG_WR(sc, PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_READ, 1);
11041
11042         /* Poll HW usage counters */
11043         if (bnx2x_poll_hw_usage_counters(sc, poll_cnt)) {
11044                 return -1;
11045         }
11046
11047         /* Zero the igu 'trailing edge' and 'leading edge' */
11048
11049         /* Send the FW cleanup command */
11050         if (bnx2x_send_final_clnup(sc, (uint8_t) SC_FUNC(sc), poll_cnt)) {
11051                 return -1;
11052         }
11053
11054         /* ATC cleanup */
11055
11056         /* Verify TX hw is flushed */
11057         bnx2x_tx_hw_flushed(sc, poll_cnt);
11058
11059         /* Wait 100ms (not adjusted according to platform) */
11060         DELAY(100000);
11061
11062         /* Verify no pending pci transactions */
11063         if (bnx2x_is_pcie_pending(sc)) {
11064                 PMD_DRV_LOG(NOTICE, sc, "PCIE Transactions still pending");
11065         }
11066
11067         /* Debug */
11068         bnx2x_hw_enable_status(sc);
11069
11070         /*
11071          * Master enable - Due to WB DMAE writes performed before this
11072          * register is re-initialized as part of the regular function init
11073          */
11074         REG_WR(sc, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 1);
11075
11076         return 0;
11077 }
11078
11079 static int bnx2x_init_hw_func(struct bnx2x_softc *sc)
11080 {
11081         int port = SC_PORT(sc);
11082         int func = SC_FUNC(sc);
11083         int init_phase = PHASE_PF0 + func;
11084         struct ecore_ilt *ilt = sc->ilt;
11085         uint16_t cdu_ilt_start;
11086         uint32_t addr, val;
11087         uint32_t main_mem_base, main_mem_size, main_mem_prty_clr;
11088         int main_mem_width, rc;
11089         uint32_t i;
11090
11091         PMD_DRV_LOG(DEBUG, sc, "starting func init for func %d", func);
11092
11093         /* FLR cleanup */
11094         if (!CHIP_IS_E1x(sc)) {
11095                 rc = bnx2x_pf_flr_clnup(sc);
11096                 if (rc) {
11097                         PMD_DRV_LOG(NOTICE, sc, "FLR cleanup failed!");
11098                         return rc;
11099                 }
11100         }
11101
11102         /* set MSI reconfigure capability */
11103         if (sc->devinfo.int_block == INT_BLOCK_HC) {
11104                 addr = (port ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0);
11105                 val = REG_RD(sc, addr);
11106                 val |= HC_CONFIG_0_REG_MSI_ATTN_EN_0;
11107                 REG_WR(sc, addr, val);
11108         }
11109
11110         ecore_init_block(sc, BLOCK_PXP, init_phase);
11111         ecore_init_block(sc, BLOCK_PXP2, init_phase);
11112
11113         ilt = sc->ilt;
11114         cdu_ilt_start = ilt->clients[ILT_CLIENT_CDU].start;
11115
11116         for (i = 0; i < L2_ILT_LINES(sc); i++) {
11117                 ilt->lines[cdu_ilt_start + i].page = sc->context[i].vcxt;
11118                 ilt->lines[cdu_ilt_start + i].page_mapping =
11119                     (rte_iova_t)sc->context[i].vcxt_dma.paddr;
11120                 ilt->lines[cdu_ilt_start + i].size = sc->context[i].size;
11121         }
11122         ecore_ilt_init_op(sc, INITOP_SET);
11123
11124         REG_WR(sc, PRS_REG_NIC_MODE, 1);
11125
11126         if (!CHIP_IS_E1x(sc)) {
11127                 uint32_t pf_conf = IGU_PF_CONF_FUNC_EN;
11128
11129 /* Turn on a single ISR mode in IGU if driver is going to use
11130  * INT#x or MSI
11131  */
11132                 if ((sc->interrupt_mode != INTR_MODE_MSIX)
11133                     || (sc->interrupt_mode != INTR_MODE_SINGLE_MSIX)) {
11134                         pf_conf |= IGU_PF_CONF_SINGLE_ISR_EN;
11135                 }
11136
11137 /*
11138  * Timers workaround bug: function init part.
11139  * Need to wait 20msec after initializing ILT,
11140  * needed to make sure there are no requests in
11141  * one of the PXP internal queues with "old" ILT addresses
11142  */
11143                 DELAY(20000);
11144
11145 /*
11146  * Master enable - Due to WB DMAE writes performed before this
11147  * register is re-initialized as part of the regular function
11148  * init
11149  */
11150                 REG_WR(sc, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 1);
11151 /* Enable the function in IGU */
11152                 REG_WR(sc, IGU_REG_PF_CONFIGURATION, pf_conf);
11153         }
11154
11155         sc->dmae_ready = 1;
11156
11157         ecore_init_block(sc, BLOCK_PGLUE_B, init_phase);
11158
11159         if (!CHIP_IS_E1x(sc))
11160                 REG_WR(sc, PGLUE_B_REG_WAS_ERROR_PF_7_0_CLR, func);
11161
11162         ecore_init_block(sc, BLOCK_ATC, init_phase);
11163         ecore_init_block(sc, BLOCK_DMAE, init_phase);
11164         ecore_init_block(sc, BLOCK_NIG, init_phase);
11165         ecore_init_block(sc, BLOCK_SRC, init_phase);
11166         ecore_init_block(sc, BLOCK_MISC, init_phase);
11167         ecore_init_block(sc, BLOCK_TCM, init_phase);
11168         ecore_init_block(sc, BLOCK_UCM, init_phase);
11169         ecore_init_block(sc, BLOCK_CCM, init_phase);
11170         ecore_init_block(sc, BLOCK_XCM, init_phase);
11171         ecore_init_block(sc, BLOCK_TSEM, init_phase);
11172         ecore_init_block(sc, BLOCK_USEM, init_phase);
11173         ecore_init_block(sc, BLOCK_CSEM, init_phase);
11174         ecore_init_block(sc, BLOCK_XSEM, init_phase);
11175
11176         if (!CHIP_IS_E1x(sc))
11177                 REG_WR(sc, QM_REG_PF_EN, 1);
11178
11179         if (!CHIP_IS_E1x(sc)) {
11180                 REG_WR(sc, TSEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func);
11181                 REG_WR(sc, USEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func);
11182                 REG_WR(sc, CSEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func);
11183                 REG_WR(sc, XSEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func);
11184         }
11185         ecore_init_block(sc, BLOCK_QM, init_phase);
11186
11187         ecore_init_block(sc, BLOCK_TM, init_phase);
11188         ecore_init_block(sc, BLOCK_DORQ, init_phase);
11189
11190         ecore_init_block(sc, BLOCK_BRB1, init_phase);
11191         ecore_init_block(sc, BLOCK_PRS, init_phase);
11192         ecore_init_block(sc, BLOCK_TSDM, init_phase);
11193         ecore_init_block(sc, BLOCK_CSDM, init_phase);
11194         ecore_init_block(sc, BLOCK_USDM, init_phase);
11195         ecore_init_block(sc, BLOCK_XSDM, init_phase);
11196         ecore_init_block(sc, BLOCK_UPB, init_phase);
11197         ecore_init_block(sc, BLOCK_XPB, init_phase);
11198         ecore_init_block(sc, BLOCK_PBF, init_phase);
11199         if (!CHIP_IS_E1x(sc))
11200                 REG_WR(sc, PBF_REG_DISABLE_PF, 0);
11201
11202         ecore_init_block(sc, BLOCK_CDU, init_phase);
11203
11204         ecore_init_block(sc, BLOCK_CFC, init_phase);
11205
11206         if (!CHIP_IS_E1x(sc))
11207                 REG_WR(sc, CFC_REG_WEAK_ENABLE_PF, 1);
11208
11209         if (IS_MF(sc)) {
11210                 REG_WR(sc, NIG_REG_LLH0_FUNC_EN + port * 8, 1);
11211                 REG_WR(sc, NIG_REG_LLH0_FUNC_VLAN_ID + port * 8, OVLAN(sc));
11212         }
11213
11214         ecore_init_block(sc, BLOCK_MISC_AEU, init_phase);
11215
11216         /* HC init per function */
11217         if (sc->devinfo.int_block == INT_BLOCK_HC) {
11218                 if (CHIP_IS_E1H(sc)) {
11219                         REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_12 + func * 4, 0);
11220
11221                         REG_WR(sc, HC_REG_LEADING_EDGE_0 + port * 8, 0);
11222                         REG_WR(sc, HC_REG_TRAILING_EDGE_0 + port * 8, 0);
11223                 }
11224                 ecore_init_block(sc, BLOCK_HC, init_phase);
11225
11226         } else {
11227                 uint32_t num_segs, sb_idx, prod_offset;
11228
11229                 REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_12 + func * 4, 0);
11230
11231                 if (!CHIP_IS_E1x(sc)) {
11232                         REG_WR(sc, IGU_REG_LEADING_EDGE_LATCH, 0);
11233                         REG_WR(sc, IGU_REG_TRAILING_EDGE_LATCH, 0);
11234                 }
11235
11236                 ecore_init_block(sc, BLOCK_IGU, init_phase);
11237
11238                 if (!CHIP_IS_E1x(sc)) {
11239                         int dsb_idx = 0;
11240         /**
11241          * Producer memory:
11242          * E2 mode: address 0-135 match to the mapping memory;
11243          * 136 - PF0 default prod; 137 - PF1 default prod;
11244          * 138 - PF2 default prod; 139 - PF3 default prod;
11245          * 140 - PF0 attn prod;    141 - PF1 attn prod;
11246          * 142 - PF2 attn prod;    143 - PF3 attn prod;
11247          * 144-147 reserved.
11248          *
11249          * E1.5 mode - In backward compatible mode;
11250          * for non default SB; each even line in the memory
11251          * holds the U producer and each odd line hold
11252          * the C producer. The first 128 producers are for
11253          * NDSB (PF0 - 0-31; PF1 - 32-63 and so on). The last 20
11254          * producers are for the DSB for each PF.
11255          * Each PF has five segments: (the order inside each
11256          * segment is PF0; PF1; PF2; PF3) - 128-131 U prods;
11257          * 132-135 C prods; 136-139 X prods; 140-143 T prods;
11258          * 144-147 attn prods;
11259          */
11260                         /* non-default-status-blocks */
11261                         num_segs = CHIP_INT_MODE_IS_BC(sc) ?
11262                             IGU_BC_NDSB_NUM_SEGS : IGU_NORM_NDSB_NUM_SEGS;
11263                         for (sb_idx = 0; sb_idx < sc->igu_sb_cnt; sb_idx++) {
11264                                 prod_offset = (sc->igu_base_sb + sb_idx) *
11265                                     num_segs;
11266
11267                                 for (i = 0; i < num_segs; i++) {
11268                                         addr = IGU_REG_PROD_CONS_MEMORY +
11269                                             (prod_offset + i) * 4;
11270                                         REG_WR(sc, addr, 0);
11271                                 }
11272                                 /* send consumer update with value 0 */
11273                                 bnx2x_ack_sb(sc, sc->igu_base_sb + sb_idx,
11274                                            USTORM_ID, 0, IGU_INT_NOP, 1);
11275                                 bnx2x_igu_clear_sb(sc, sc->igu_base_sb + sb_idx);
11276                         }
11277
11278                         /* default-status-blocks */
11279                         num_segs = CHIP_INT_MODE_IS_BC(sc) ?
11280                             IGU_BC_DSB_NUM_SEGS : IGU_NORM_DSB_NUM_SEGS;
11281
11282                         if (CHIP_IS_MODE_4_PORT(sc))
11283                                 dsb_idx = SC_FUNC(sc);
11284                         else
11285                                 dsb_idx = SC_VN(sc);
11286
11287                         prod_offset = (CHIP_INT_MODE_IS_BC(sc) ?
11288                                        IGU_BC_BASE_DSB_PROD + dsb_idx :
11289                                        IGU_NORM_BASE_DSB_PROD + dsb_idx);
11290
11291                         /*
11292                          * igu prods come in chunks of E1HVN_MAX (4) -
11293                          * does not matters what is the current chip mode
11294                          */
11295                         for (i = 0; i < (num_segs * E1HVN_MAX); i += E1HVN_MAX) {
11296                                 addr = IGU_REG_PROD_CONS_MEMORY +
11297                                     (prod_offset + i) * 4;
11298                                 REG_WR(sc, addr, 0);
11299                         }
11300                         /* send consumer update with 0 */
11301                         if (CHIP_INT_MODE_IS_BC(sc)) {
11302                                 bnx2x_ack_sb(sc, sc->igu_dsb_id,
11303                                            USTORM_ID, 0, IGU_INT_NOP, 1);
11304                                 bnx2x_ack_sb(sc, sc->igu_dsb_id,
11305                                            CSTORM_ID, 0, IGU_INT_NOP, 1);
11306                                 bnx2x_ack_sb(sc, sc->igu_dsb_id,
11307                                            XSTORM_ID, 0, IGU_INT_NOP, 1);
11308                                 bnx2x_ack_sb(sc, sc->igu_dsb_id,
11309                                            TSTORM_ID, 0, IGU_INT_NOP, 1);
11310                                 bnx2x_ack_sb(sc, sc->igu_dsb_id,
11311                                            ATTENTION_ID, 0, IGU_INT_NOP, 1);
11312                         } else {
11313                                 bnx2x_ack_sb(sc, sc->igu_dsb_id,
11314                                            USTORM_ID, 0, IGU_INT_NOP, 1);
11315                                 bnx2x_ack_sb(sc, sc->igu_dsb_id,
11316                                            ATTENTION_ID, 0, IGU_INT_NOP, 1);
11317                         }
11318                         bnx2x_igu_clear_sb(sc, sc->igu_dsb_id);
11319
11320                         /* !!! these should become driver const once
11321                            rf-tool supports split-68 const */
11322                         REG_WR(sc, IGU_REG_SB_INT_BEFORE_MASK_LSB, 0);
11323                         REG_WR(sc, IGU_REG_SB_INT_BEFORE_MASK_MSB, 0);
11324                         REG_WR(sc, IGU_REG_SB_MASK_LSB, 0);
11325                         REG_WR(sc, IGU_REG_SB_MASK_MSB, 0);
11326                         REG_WR(sc, IGU_REG_PBA_STATUS_LSB, 0);
11327                         REG_WR(sc, IGU_REG_PBA_STATUS_MSB, 0);
11328                 }
11329         }
11330
11331         /* Reset PCIE errors for debug */
11332         REG_WR(sc, 0x2114, 0xffffffff);
11333         REG_WR(sc, 0x2120, 0xffffffff);
11334
11335         if (CHIP_IS_E1x(sc)) {
11336                 main_mem_size = HC_REG_MAIN_MEMORY_SIZE / 2;    /*dwords */
11337                 main_mem_base = HC_REG_MAIN_MEMORY +
11338                     SC_PORT(sc) * (main_mem_size * 4);
11339                 main_mem_prty_clr = HC_REG_HC_PRTY_STS_CLR;
11340                 main_mem_width = 8;
11341
11342                 val = REG_RD(sc, main_mem_prty_clr);
11343                 if (val) {
11344                         PMD_DRV_LOG(DEBUG, sc,
11345                                     "Parity errors in HC block during function init (0x%x)!",
11346                                     val);
11347                 }
11348
11349 /* Clear "false" parity errors in MSI-X table */
11350                 for (i = main_mem_base;
11351                      i < main_mem_base + main_mem_size * 4;
11352                      i += main_mem_width) {
11353                         bnx2x_read_dmae(sc, i, main_mem_width / 4);
11354                         bnx2x_write_dmae(sc, BNX2X_SP_MAPPING(sc, wb_data),
11355                                        i, main_mem_width / 4);
11356                 }
11357 /* Clear HC parity attention */
11358                 REG_RD(sc, main_mem_prty_clr);
11359         }
11360
11361         /* Enable STORMs SP logging */
11362         REG_WR8(sc, BAR_USTRORM_INTMEM +
11363                 USTORM_RECORD_SLOW_PATH_OFFSET(SC_FUNC(sc)), 1);
11364         REG_WR8(sc, BAR_TSTRORM_INTMEM +
11365                 TSTORM_RECORD_SLOW_PATH_OFFSET(SC_FUNC(sc)), 1);
11366         REG_WR8(sc, BAR_CSTRORM_INTMEM +
11367                 CSTORM_RECORD_SLOW_PATH_OFFSET(SC_FUNC(sc)), 1);
11368         REG_WR8(sc, BAR_XSTRORM_INTMEM +
11369                 XSTORM_RECORD_SLOW_PATH_OFFSET(SC_FUNC(sc)), 1);
11370
11371         elink_phy_probe(&sc->link_params);
11372
11373         return 0;
11374 }
11375
11376 static void bnx2x_link_reset(struct bnx2x_softc *sc)
11377 {
11378         if (!BNX2X_NOMCP(sc)) {
11379                 bnx2x_acquire_phy_lock(sc);
11380                 elink_lfa_reset(&sc->link_params, &sc->link_vars);
11381                 bnx2x_release_phy_lock(sc);
11382         } else {
11383                 if (!CHIP_REV_IS_SLOW(sc)) {
11384                         PMD_DRV_LOG(WARNING, sc,
11385                                     "Bootcode is missing - cannot reset link");
11386                 }
11387         }
11388 }
11389
11390 static void bnx2x_reset_port(struct bnx2x_softc *sc)
11391 {
11392         int port = SC_PORT(sc);
11393         uint32_t val;
11394
11395         /* reset physical Link */
11396         bnx2x_link_reset(sc);
11397
11398         REG_WR(sc, NIG_REG_MASK_INTERRUPT_PORT0 + port * 4, 0);
11399
11400         /* Do not rcv packets to BRB */
11401         REG_WR(sc, NIG_REG_LLH0_BRB1_DRV_MASK + port * 4, 0x0);
11402         /* Do not direct rcv packets that are not for MCP to the BRB */
11403         REG_WR(sc, (port ? NIG_REG_LLH1_BRB1_NOT_MCP :
11404                     NIG_REG_LLH0_BRB1_NOT_MCP), 0x0);
11405
11406         /* Configure AEU */
11407         REG_WR(sc, MISC_REG_AEU_MASK_ATTN_FUNC_0 + port * 4, 0);
11408
11409         DELAY(100000);
11410
11411         /* Check for BRB port occupancy */
11412         val = REG_RD(sc, BRB1_REG_PORT_NUM_OCC_BLOCKS_0 + port * 4);
11413         if (val) {
11414                 PMD_DRV_LOG(DEBUG, sc,
11415                             "BRB1 is not empty, %d blocks are occupied", val);
11416         }
11417 }
11418
11419 static void bnx2x_ilt_wr(struct bnx2x_softc *sc, uint32_t index, rte_iova_t addr)
11420 {
11421         int reg;
11422         uint32_t wb_write[2];
11423
11424         reg = PXP2_REG_RQ_ONCHIP_AT_B0 + index * 8;
11425
11426         wb_write[0] = ONCHIP_ADDR1(addr);
11427         wb_write[1] = ONCHIP_ADDR2(addr);
11428         REG_WR_DMAE(sc, reg, wb_write, 2);
11429 }
11430
11431 static void bnx2x_clear_func_ilt(struct bnx2x_softc *sc, uint32_t func)
11432 {
11433         uint32_t i, base = FUNC_ILT_BASE(func);
11434         for (i = base; i < base + ILT_PER_FUNC; i++) {
11435                 bnx2x_ilt_wr(sc, i, 0);
11436         }
11437 }
11438
11439 static void bnx2x_reset_func(struct bnx2x_softc *sc)
11440 {
11441         struct bnx2x_fastpath *fp;
11442         int port = SC_PORT(sc);
11443         int func = SC_FUNC(sc);
11444         int i;
11445
11446         /* Disable the function in the FW */
11447         REG_WR8(sc, BAR_XSTRORM_INTMEM + XSTORM_FUNC_EN_OFFSET(func), 0);
11448         REG_WR8(sc, BAR_CSTRORM_INTMEM + CSTORM_FUNC_EN_OFFSET(func), 0);
11449         REG_WR8(sc, BAR_TSTRORM_INTMEM + TSTORM_FUNC_EN_OFFSET(func), 0);
11450         REG_WR8(sc, BAR_USTRORM_INTMEM + USTORM_FUNC_EN_OFFSET(func), 0);
11451
11452         /* FP SBs */
11453         FOR_EACH_ETH_QUEUE(sc, i) {
11454                 fp = &sc->fp[i];
11455                 REG_WR8(sc, BAR_CSTRORM_INTMEM +
11456                         CSTORM_STATUS_BLOCK_DATA_STATE_OFFSET(fp->fw_sb_id),
11457                         SB_DISABLED);
11458         }
11459
11460         /* SP SB */
11461         REG_WR8(sc, BAR_CSTRORM_INTMEM +
11462                 CSTORM_SP_STATUS_BLOCK_DATA_STATE_OFFSET(func), SB_DISABLED);
11463
11464         for (i = 0; i < XSTORM_SPQ_DATA_SIZE / 4; i++) {
11465                 REG_WR(sc, BAR_XSTRORM_INTMEM + XSTORM_SPQ_DATA_OFFSET(func),
11466                        0);
11467         }
11468
11469         /* Configure IGU */
11470         if (sc->devinfo.int_block == INT_BLOCK_HC) {
11471                 REG_WR(sc, HC_REG_LEADING_EDGE_0 + port * 8, 0);
11472                 REG_WR(sc, HC_REG_TRAILING_EDGE_0 + port * 8, 0);
11473         } else {
11474                 REG_WR(sc, IGU_REG_LEADING_EDGE_LATCH, 0);
11475                 REG_WR(sc, IGU_REG_TRAILING_EDGE_LATCH, 0);
11476         }
11477
11478         if (CNIC_LOADED(sc)) {
11479 /* Disable Timer scan */
11480                 REG_WR(sc, TM_REG_EN_LINEAR0_TIMER + port * 4, 0);
11481 /*
11482  * Wait for at least 10ms and up to 2 second for the timers
11483  * scan to complete
11484  */
11485                 for (i = 0; i < 200; i++) {
11486                         DELAY(10000);
11487                         if (!REG_RD(sc, TM_REG_LIN0_SCAN_ON + port * 4))
11488                                 break;
11489                 }
11490         }
11491
11492         /* Clear ILT */
11493         bnx2x_clear_func_ilt(sc, func);
11494
11495         /*
11496          * Timers workaround bug for E2: if this is vnic-3,
11497          * we need to set the entire ilt range for this timers.
11498          */
11499         if (!CHIP_IS_E1x(sc) && SC_VN(sc) == 3) {
11500                 struct ilt_client_info ilt_cli;
11501 /* use dummy TM client */
11502                 memset(&ilt_cli, 0, sizeof(struct ilt_client_info));
11503                 ilt_cli.start = 0;
11504                 ilt_cli.end = ILT_NUM_PAGE_ENTRIES - 1;
11505                 ilt_cli.client_num = ILT_CLIENT_TM;
11506
11507                 ecore_ilt_boundry_init_op(sc, &ilt_cli, 0);
11508         }
11509
11510         /* this assumes that reset_port() called before reset_func() */
11511         if (!CHIP_IS_E1x(sc)) {
11512                 bnx2x_pf_disable(sc);
11513         }
11514
11515         sc->dmae_ready = 0;
11516 }
11517
11518 static void bnx2x_release_firmware(struct bnx2x_softc *sc)
11519 {
11520         rte_free(sc->init_ops);
11521         rte_free(sc->init_ops_offsets);
11522         rte_free(sc->init_data);
11523         rte_free(sc->iro_array);
11524 }
11525
11526 static int bnx2x_init_firmware(struct bnx2x_softc *sc)
11527 {
11528         uint32_t len, i;
11529         uint8_t *p = sc->firmware;
11530         uint32_t off[24];
11531
11532         for (i = 0; i < 24; ++i)
11533                 off[i] = rte_be_to_cpu_32(*((uint32_t *) sc->firmware + i));
11534
11535         len = off[0];
11536         sc->init_ops = rte_zmalloc("", len, RTE_CACHE_LINE_SIZE);
11537         if (!sc->init_ops)
11538                 goto alloc_failed;
11539         bnx2x_data_to_init_ops(p + off[1], sc->init_ops, len);
11540
11541         len = off[2];
11542         sc->init_ops_offsets = rte_zmalloc("", len, RTE_CACHE_LINE_SIZE);
11543         if (!sc->init_ops_offsets)
11544                 goto alloc_failed;
11545         bnx2x_data_to_init_offsets(p + off[3], sc->init_ops_offsets, len);
11546
11547         len = off[4];
11548         sc->init_data = rte_zmalloc("", len, RTE_CACHE_LINE_SIZE);
11549         if (!sc->init_data)
11550                 goto alloc_failed;
11551         bnx2x_data_to_init_data(p + off[5], sc->init_data, len);
11552
11553         sc->tsem_int_table_data = p + off[7];
11554         sc->tsem_pram_data = p + off[9];
11555         sc->usem_int_table_data = p + off[11];
11556         sc->usem_pram_data = p + off[13];
11557         sc->csem_int_table_data = p + off[15];
11558         sc->csem_pram_data = p + off[17];
11559         sc->xsem_int_table_data = p + off[19];
11560         sc->xsem_pram_data = p + off[21];
11561
11562         len = off[22];
11563         sc->iro_array = rte_zmalloc("", len, RTE_CACHE_LINE_SIZE);
11564         if (!sc->iro_array)
11565                 goto alloc_failed;
11566         bnx2x_data_to_iro_array(p + off[23], sc->iro_array, len);
11567
11568         return 0;
11569
11570 alloc_failed:
11571         bnx2x_release_firmware(sc);
11572         return -1;
11573 }
11574
11575 static int cut_gzip_prefix(const uint8_t * zbuf, int len)
11576 {
11577 #define MIN_PREFIX_SIZE (10)
11578
11579         int n = MIN_PREFIX_SIZE;
11580         uint16_t xlen;
11581
11582         if (!(zbuf[0] == 0x1f && zbuf[1] == 0x8b && zbuf[2] == Z_DEFLATED) ||
11583             len <= MIN_PREFIX_SIZE) {
11584                 return -1;
11585         }
11586
11587         /* optional extra fields are present */
11588         if (zbuf[3] & 0x4) {
11589                 xlen = zbuf[13];
11590                 xlen <<= 8;
11591                 xlen += zbuf[12];
11592
11593                 n += xlen;
11594         }
11595         /* file name is present */
11596         if (zbuf[3] & 0x8) {
11597                 while ((zbuf[n++] != 0) && (n < len)) ;
11598         }
11599
11600         return n;
11601 }
11602
11603 static int ecore_gunzip(struct bnx2x_softc *sc, const uint8_t * zbuf, int len)
11604 {
11605         int ret;
11606         int data_begin = cut_gzip_prefix(zbuf, len);
11607
11608         PMD_DRV_LOG(DEBUG, sc, "ecore_gunzip %d", len);
11609
11610         if (data_begin <= 0) {
11611                 PMD_DRV_LOG(NOTICE, sc, "bad gzip prefix");
11612                 return -1;
11613         }
11614
11615         memset(&zlib_stream, 0, sizeof(zlib_stream));
11616         zlib_stream.next_in = zbuf + data_begin;
11617         zlib_stream.avail_in = len - data_begin;
11618         zlib_stream.next_out = sc->gz_buf;
11619         zlib_stream.avail_out = FW_BUF_SIZE;
11620
11621         ret = inflateInit2(&zlib_stream, -MAX_WBITS);
11622         if (ret != Z_OK) {
11623                 PMD_DRV_LOG(NOTICE, sc, "zlib inflateInit2 error");
11624                 return ret;
11625         }
11626
11627         ret = inflate(&zlib_stream, Z_FINISH);
11628         if ((ret != Z_STREAM_END) && (ret != Z_OK)) {
11629                 PMD_DRV_LOG(NOTICE, sc, "zlib inflate error: %d %s", ret,
11630                             zlib_stream.msg);
11631         }
11632
11633         sc->gz_outlen = zlib_stream.total_out;
11634         if (sc->gz_outlen & 0x3) {
11635                 PMD_DRV_LOG(NOTICE, sc, "firmware is not aligned. gz_outlen == %d",
11636                             sc->gz_outlen);
11637         }
11638         sc->gz_outlen >>= 2;
11639
11640         inflateEnd(&zlib_stream);
11641
11642         if (ret == Z_STREAM_END)
11643                 return 0;
11644
11645         return ret;
11646 }
11647
11648 static void
11649 ecore_write_dmae_phys_len(struct bnx2x_softc *sc, rte_iova_t phys_addr,
11650                           uint32_t addr, uint32_t len)
11651 {
11652         bnx2x_write_dmae_phys_len(sc, phys_addr, addr, len);
11653 }
11654
11655 void
11656 ecore_storm_memset_struct(struct bnx2x_softc *sc, uint32_t addr, size_t size,
11657                           uint32_t * data)
11658 {
11659         uint8_t i;
11660         for (i = 0; i < size / 4; i++) {
11661                 REG_WR(sc, addr + (i * 4), data[i]);
11662         }
11663 }
11664
11665 static const char *get_ext_phy_type(uint32_t ext_phy_type)
11666 {
11667         uint32_t phy_type_idx = ext_phy_type >> 8;
11668         static const char *types[] =
11669             { "DIRECT", "BNX2X-8071", "BNX2X-8072", "BNX2X-8073",
11670                 "BNX2X-8705", "BNX2X-8706", "BNX2X-8726", "BNX2X-8481", "SFX-7101",
11671                 "BNX2X-8727",
11672                 "BNX2X-8727-NOC", "BNX2X-84823", "NOT_CONN", "FAILURE"
11673         };
11674
11675         if (phy_type_idx < 12)
11676                 return types[phy_type_idx];
11677         else if (PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN == ext_phy_type)
11678                 return types[12];
11679         else
11680                 return types[13];
11681 }
11682
11683 static const char *get_state(uint32_t state)
11684 {
11685         uint32_t state_idx = state >> 12;
11686         static const char *states[] = { "CLOSED", "OPENING_WAIT4_LOAD",
11687                 "OPENING_WAIT4_PORT", "OPEN", "CLOSING_WAIT4_HALT",
11688                 "CLOSING_WAIT4_DELETE", "CLOSING_WAIT4_UNLOAD",
11689                 "UNKNOWN", "UNKNOWN", "UNKNOWN", "UNKNOWN", "UNKNOWN",
11690                 "UNKNOWN", "DISABLED", "DIAG", "ERROR", "UNDEFINED"
11691         };
11692
11693         if (state_idx <= 0xF)
11694                 return states[state_idx];
11695         else
11696                 return states[0x10];
11697 }
11698
11699 static const char *get_recovery_state(uint32_t state)
11700 {
11701         static const char *states[] = { "NONE", "DONE", "INIT",
11702                 "WAIT", "FAILED", "NIC_LOADING"
11703         };
11704         return states[state];
11705 }
11706
11707 static const char *get_rx_mode(uint32_t mode)
11708 {
11709         static const char *modes[] = { "NONE", "NORMAL", "ALLMULTI",
11710                 "PROMISC", "MAX_MULTICAST", "ERROR"
11711         };
11712
11713         if (mode < 0x4)
11714                 return modes[mode];
11715         else if (BNX2X_MAX_MULTICAST == mode)
11716                 return modes[4];
11717         else
11718                 return modes[5];
11719 }
11720
11721 #define BNX2X_INFO_STR_MAX 256
11722 static const char *get_bnx2x_flags(uint32_t flags)
11723 {
11724         int i;
11725         static const char *flag[] = { "ONE_PORT ", "NO_ISCSI ",
11726                 "NO_FCOE ", "NO_WOL ", "USING_DAC ", "USING_MSIX ",
11727                 "USING_MSI ", "DISABLE_MSI ", "UNKNOWN ", "NO_MCP ",
11728                 "SAFC_TX_FLAG ", "MF_FUNC_DIS ", "TX_SWITCHING "
11729         };
11730         static char flag_str[BNX2X_INFO_STR_MAX];
11731         memset(flag_str, 0, BNX2X_INFO_STR_MAX);
11732
11733         for (i = 0; i < 5; i++)
11734                 if (flags & (1 << i)) {
11735                         strcat(flag_str, flag[i]);
11736                         flags ^= (1 << i);
11737                 }
11738         if (flags) {
11739                 static char unknown[BNX2X_INFO_STR_MAX];
11740                 snprintf(unknown, 32, "Unknown flag mask %x", flags);
11741                 strcat(flag_str, unknown);
11742         }
11743         return flag_str;
11744 }
11745
11746 /*
11747  * Prints useful adapter info.
11748  */
11749 void bnx2x_print_adapter_info(struct bnx2x_softc *sc)
11750 {
11751         int i = 0;
11752         __rte_unused uint32_t ext_phy_type;
11753
11754         PMD_INIT_FUNC_TRACE(sc);
11755         if (sc->link_vars.phy_flags & PHY_XGXS_FLAG)
11756                 ext_phy_type = ELINK_XGXS_EXT_PHY_TYPE(REG_RD(sc,
11757                                                               sc->
11758                                                               devinfo.shmem_base
11759                                                               + offsetof(struct
11760                                                                          shmem_region,
11761                                                                          dev_info.port_hw_config
11762                                                                          [0].external_phy_config)));
11763         else
11764                 ext_phy_type = ELINK_SERDES_EXT_PHY_TYPE(REG_RD(sc,
11765                                                                 sc->
11766                                                                 devinfo.shmem_base
11767                                                                 +
11768                                                                 offsetof(struct
11769                                                                          shmem_region,
11770                                                                          dev_info.port_hw_config
11771                                                                          [0].external_phy_config)));
11772
11773         PMD_DRV_LOG(INFO, sc, "\n\n===================================\n");
11774         /* Hardware chip info. */
11775         PMD_DRV_LOG(INFO, sc, "%12s : %#08x", "ASIC", sc->devinfo.chip_id);
11776         PMD_DRV_LOG(INFO, sc, "%12s : %c%d", "Rev", (CHIP_REV(sc) >> 12) + 'A',
11777                      (CHIP_METAL(sc) >> 4));
11778
11779         /* Bus info. */
11780         PMD_DRV_LOG(INFO, sc,
11781                     "%12s : %d, ", "Bus PCIe", sc->devinfo.pcie_link_width);
11782         switch (sc->devinfo.pcie_link_speed) {
11783         case 1:
11784                 PMD_DRV_LOG(INFO, sc, "%23s", "2.5 Gbps");
11785                 break;
11786         case 2:
11787                 PMD_DRV_LOG(INFO, sc, "%21s", "5 Gbps");
11788                 break;
11789         case 4:
11790                 PMD_DRV_LOG(INFO, sc, "%21s", "8 Gbps");
11791                 break;
11792         default:
11793                 PMD_DRV_LOG(INFO, sc, "%33s", "Unknown link speed");
11794         }
11795
11796         /* Device features. */
11797         PMD_DRV_LOG(INFO, sc, "%12s : ", "Flags");
11798
11799         /* Miscellaneous flags. */
11800         if (sc->devinfo.pcie_cap_flags & BNX2X_MSI_CAPABLE_FLAG) {
11801                 PMD_DRV_LOG(INFO, sc, "%18s", "MSI");
11802                 i++;
11803         }
11804
11805         if (sc->devinfo.pcie_cap_flags & BNX2X_MSIX_CAPABLE_FLAG) {
11806                 if (i > 0)
11807                         PMD_DRV_LOG(INFO, sc, "|");
11808                 PMD_DRV_LOG(INFO, sc, "%20s", "MSI-X");
11809                 i++;
11810         }
11811
11812         if (IS_PF(sc)) {
11813                 PMD_DRV_LOG(INFO, sc, "%12s : ", "Queues");
11814                 switch (sc->sp->rss_rdata.rss_mode) {
11815                 case ETH_RSS_MODE_DISABLED:
11816                         PMD_DRV_LOG(INFO, sc, "%19s", "None");
11817                         break;
11818                 case ETH_RSS_MODE_REGULAR:
11819                         PMD_DRV_LOG(INFO, sc,
11820                                     "%18s : %d", "RSS", sc->num_queues);
11821                         break;
11822                 default:
11823                         PMD_DRV_LOG(INFO, sc, "%22s", "Unknown");
11824                         break;
11825                 }
11826         }
11827
11828         /* RTE and Driver versions */
11829         PMD_DRV_LOG(INFO, sc, "%12s : %s", "DPDK",
11830                         rte_version());
11831         PMD_DRV_LOG(INFO, sc, "%12s : %s", "Driver",
11832                         bnx2x_pmd_version());
11833
11834         /* Firmware versions and device features. */
11835         PMD_DRV_LOG(INFO, sc, "%12s : %d.%d.%d",
11836                      "Firmware",
11837                      BNX2X_5710_FW_MAJOR_VERSION,
11838                      BNX2X_5710_FW_MINOR_VERSION,
11839                      BNX2X_5710_FW_REVISION_VERSION);
11840         PMD_DRV_LOG(INFO, sc, "%12s : %s",
11841                      "Bootcode", sc->devinfo.bc_ver_str);
11842
11843         PMD_DRV_LOG(INFO, sc, "\n\n===================================\n");
11844         PMD_DRV_LOG(INFO, sc, "%12s : %u", "Bnx2x Func", sc->pcie_func);
11845         PMD_DRV_LOG(INFO, sc,
11846                     "%12s : %s", "Bnx2x Flags", get_bnx2x_flags(sc->flags));
11847         PMD_DRV_LOG(INFO, sc, "%12s : %s", "DMAE Is",
11848                      (sc->dmae_ready ? "Ready" : "Not Ready"));
11849         PMD_DRV_LOG(INFO, sc, "%12s : %s", "OVLAN", (OVLAN(sc) ? "YES" : "NO"));
11850         PMD_DRV_LOG(INFO, sc, "%12s : %s", "MF", (IS_MF(sc) ? "YES" : "NO"));
11851         PMD_DRV_LOG(INFO, sc, "%12s : %u", "MTU", sc->mtu);
11852         PMD_DRV_LOG(INFO, sc,
11853                     "%12s : %s", "PHY Type", get_ext_phy_type(ext_phy_type));
11854         PMD_DRV_LOG(INFO, sc, "%12s : %x:%x:%x:%x:%x:%x", "MAC Addr",
11855                         sc->link_params.mac_addr[0],
11856                         sc->link_params.mac_addr[1],
11857                         sc->link_params.mac_addr[2],
11858                         sc->link_params.mac_addr[3],
11859                         sc->link_params.mac_addr[4],
11860                         sc->link_params.mac_addr[5]);
11861         PMD_DRV_LOG(INFO, sc, "%12s : %s", "RX Mode", get_rx_mode(sc->rx_mode));
11862         PMD_DRV_LOG(INFO, sc, "%12s : %s", "State", get_state(sc->state));
11863         if (sc->recovery_state)
11864                 PMD_DRV_LOG(INFO, sc, "%12s : %s", "Recovery",
11865                              get_recovery_state(sc->recovery_state));
11866         PMD_DRV_LOG(INFO, sc, "%12s : CQ = %lx,  EQ = %lx", "SPQ Left",
11867                      sc->cq_spq_left, sc->eq_spq_left);
11868         PMD_DRV_LOG(INFO, sc,
11869                     "%12s : %x", "Switch", sc->link_params.switch_cfg);
11870         PMD_DRV_LOG(INFO, sc, "\n\n===================================\n");
11871 }