drivers/net/bnx2x/bnx2x.c

   1 /*-
   2  * Copyright (c) 2007-2013 Broadcom Corporation.
   3  *
   4  * Eric Davis        <edavis@broadcom.com>
   5  * David Christensen <davidch@broadcom.com>
   6  * Gary Zambrano     <zambrano@broadcom.com>
   7  *
   8  * Copyright (c) 2013-2015 Brocade Communications Systems, Inc.
   9  * Copyright (c) 2015-2018 Cavium Inc.
  10  * All rights reserved.
  11  * www.cavium.com
  12  *
  13  * See LICENSE.bnx2x_pmd for copyright and licensing details.
  14  */
  15
  16 #define BNX2X_DRIVER_VERSION "1.78.18"
  17
  18 #include "bnx2x.h"
  19 #include "bnx2x_vfpf.h"
  20 #include "ecore_sp.h"
  21 #include "ecore_init.h"
  22 #include "ecore_init_ops.h"
  23
  24 #include "rte_version.h"
  25
  26 #include <sys/types.h>
  27 #include <sys/stat.h>
  28 #include <fcntl.h>
  29 #include <zlib.h>
  30
  31 #define BNX2X_PMD_VER_PREFIX "BNX2X PMD"
  32 #define BNX2X_PMD_VERSION_MAJOR 1
  33 #define BNX2X_PMD_VERSION_MINOR 0
  34 #define BNX2X_PMD_VERSION_REVISION 5
  35 #define BNX2X_PMD_VERSION_PATCH 1
  36
  37 static inline const char *
  38 bnx2x_pmd_version(void)
  39 {
  40         static char version[32];
  41
  42         snprintf(version, sizeof(version), "%s %s_%d.%d.%d.%d",
  43                         BNX2X_PMD_VER_PREFIX,
  44                         BNX2X_DRIVER_VERSION,
  45                         BNX2X_PMD_VERSION_MAJOR,
  46                         BNX2X_PMD_VERSION_MINOR,
  47                         BNX2X_PMD_VERSION_REVISION,
  48                         BNX2X_PMD_VERSION_PATCH);
  49
  50         return version;
  51 }
  52
  53 static z_stream zlib_stream;
  54
  55 #define EVL_VLID_MASK 0x0FFF
  56
  57 #define BNX2X_DEF_SB_ATT_IDX 0x0001
  58 #define BNX2X_DEF_SB_IDX     0x0002
  59
  60 /*
  61  * FLR Support - bnx2x_pf_flr_clnup() is called during nic_load in the per
  62  * function HW initialization.
  63  */
  64 #define FLR_WAIT_USEC     10000 /* 10 msecs */
  65 #define FLR_WAIT_INTERVAL 50    /* usecs */
  66 #define FLR_POLL_CNT      (FLR_WAIT_USEC / FLR_WAIT_INTERVAL)   /* 200 */
  67
  68 struct pbf_pN_buf_regs {
  69         int pN;
  70         uint32_t init_crd;
  71         uint32_t crd;
  72         uint32_t crd_freed;
  73 };
  74
  75 struct pbf_pN_cmd_regs {
  76         int pN;
  77         uint32_t lines_occup;
  78         uint32_t lines_freed;
  79 };
  80
  81 /* resources needed for unloading a previously loaded device */
  82
  83 #define BNX2X_PREV_WAIT_NEEDED 1
  84 rte_spinlock_t bnx2x_prev_mtx;
  85 struct bnx2x_prev_list_node {
  86         LIST_ENTRY(bnx2x_prev_list_node) node;
  87         uint8_t bus;
  88         uint8_t slot;
  89         uint8_t path;
  90         uint8_t aer;
  91         uint8_t undi;
  92 };
  93
  94 static LIST_HEAD(, bnx2x_prev_list_node) bnx2x_prev_list
  95         = LIST_HEAD_INITIALIZER(bnx2x_prev_list);
  96
  97 static int load_count[2][3] = { { 0 } };
  98         /* per-path: 0-common, 1-port0, 2-port1 */
  99
 100 static void bnx2x_cmng_fns_init(struct bnx2x_softc *sc, uint8_t read_cfg,
 101                                 uint8_t cmng_type);
 102 static int bnx2x_get_cmng_fns_mode(struct bnx2x_softc *sc);
 103 static void storm_memset_cmng(struct bnx2x_softc *sc, struct cmng_init *cmng,
 104                               uint8_t port);
 105 static void bnx2x_set_reset_global(struct bnx2x_softc *sc);
 106 static void bnx2x_set_reset_in_progress(struct bnx2x_softc *sc);
 107 static uint8_t bnx2x_reset_is_done(struct bnx2x_softc *sc, int engine);
 108 static uint8_t bnx2x_clear_pf_load(struct bnx2x_softc *sc);
 109 static uint8_t bnx2x_chk_parity_attn(struct bnx2x_softc *sc, uint8_t * global,
 110                                      uint8_t print);
 111 static void bnx2x_int_disable(struct bnx2x_softc *sc);
 112 static int bnx2x_release_leader_lock(struct bnx2x_softc *sc);
 113 static void bnx2x_pf_disable(struct bnx2x_softc *sc);
 114 static void bnx2x_update_rx_prod(struct bnx2x_softc *sc,
 115                                  struct bnx2x_fastpath *fp,
 116                                  uint16_t rx_bd_prod, uint16_t rx_cq_prod);
 117 static void bnx2x_link_report(struct bnx2x_softc *sc);
 118 void bnx2x_link_status_update(struct bnx2x_softc *sc);
 119 static int bnx2x_alloc_mem(struct bnx2x_softc *sc);
 120 static void bnx2x_free_mem(struct bnx2x_softc *sc);
 121 static int bnx2x_alloc_fw_stats_mem(struct bnx2x_softc *sc);
 122 static void bnx2x_free_fw_stats_mem(struct bnx2x_softc *sc);
 123 static __rte_noinline
 124 int bnx2x_nic_load(struct bnx2x_softc *sc);
 125
 126 static int bnx2x_handle_sp_tq(struct bnx2x_softc *sc);
 127 static void bnx2x_handle_fp_tq(struct bnx2x_fastpath *fp, int scan_fp);
 128 static void bnx2x_periodic_stop(struct bnx2x_softc *sc);
 129 static void bnx2x_ack_sb(struct bnx2x_softc *sc, uint8_t igu_sb_id,
 130                          uint8_t storm, uint16_t index, uint8_t op,
 131                          uint8_t update);
 132
 133 int bnx2x_test_bit(int nr, volatile unsigned long *addr)
 134 {
 135         int res;
 136
 137         mb();
 138         res = ((*addr) & (1UL << nr)) != 0;
 139         mb();
 140         return res;
 141 }
 142
 143 void bnx2x_set_bit(unsigned int nr, volatile unsigned long *addr)
 144 {
 145         __sync_fetch_and_or(addr, (1UL << nr));
 146 }
 147
 148 void bnx2x_clear_bit(int nr, volatile unsigned long *addr)
 149 {
 150         __sync_fetch_and_and(addr, ~(1UL << nr));
 151 }
 152
 153 int bnx2x_test_and_clear_bit(int nr, volatile unsigned long *addr)
 154 {
 155         unsigned long mask = (1UL << nr);
 156         return __sync_fetch_and_and(addr, ~mask) & mask;
 157 }
 158
 159 int bnx2x_cmpxchg(volatile int *addr, int old, int new)
 160 {
 161         return __sync_val_compare_and_swap(addr, old, new);
 162 }
 163
 164 int
 165 bnx2x_dma_alloc(struct bnx2x_softc *sc, size_t size, struct bnx2x_dma *dma,
 166               const char *msg, uint32_t align)
 167 {
 168         char mz_name[RTE_MEMZONE_NAMESIZE];
 169         const struct rte_memzone *z;
 170
 171         dma->sc = sc;
 172         if (IS_PF(sc))
 173                 snprintf(mz_name, sizeof(mz_name), "bnx2x%d_%s_%" PRIx64, SC_ABS_FUNC(sc), msg,
 174                         rte_get_timer_cycles());
 175         else
 176                 snprintf(mz_name, sizeof(mz_name), "bnx2x%d_%s_%" PRIx64, sc->pcie_device, msg,
 177                         rte_get_timer_cycles());
 178
 179         /* Caller must take care that strlen(mz_name) < RTE_MEMZONE_NAMESIZE */
 180         z = rte_memzone_reserve_aligned(mz_name, (uint64_t)size,
 181                                         SOCKET_ID_ANY,
 182                                         RTE_MEMZONE_IOVA_CONTIG, align);
 183         if (z == NULL) {
 184                 PMD_DRV_LOG(ERR, "DMA alloc failed for %s", msg);
 185                 return -ENOMEM;
 186         }
 187         dma->paddr = (uint64_t) z->iova;
 188         dma->vaddr = z->addr;
 189
 190         PMD_DRV_LOG(DEBUG, "%s: virt=%p phys=%" PRIx64, msg, dma->vaddr, dma->paddr);
 191
 192         return 0;
 193 }
 194
 195 static int bnx2x_acquire_hw_lock(struct bnx2x_softc *sc, uint32_t resource)
 196 {
 197         uint32_t lock_status;
 198         uint32_t resource_bit = (1 << resource);
 199         int func = SC_FUNC(sc);
 200         uint32_t hw_lock_control_reg;
 201         int cnt;
 202
 203         PMD_INIT_FUNC_TRACE();
 204
 205         /* validate the resource is within range */
 206         if (resource > HW_LOCK_MAX_RESOURCE_VALUE) {
 207                 PMD_DRV_LOG(NOTICE,
 208                             "resource 0x%x > HW_LOCK_MAX_RESOURCE_VALUE",
 209                             resource);
 210                 return -1;
 211         }
 212
 213         if (func <= 5) {
 214                 hw_lock_control_reg = (MISC_REG_DRIVER_CONTROL_1 + (func * 8));
 215         } else {
 216                 hw_lock_control_reg =
 217                     (MISC_REG_DRIVER_CONTROL_7 + ((func - 6) * 8));
 218         }
 219
 220         /* validate the resource is not already taken */
 221         lock_status = REG_RD(sc, hw_lock_control_reg);
 222         if (lock_status & resource_bit) {
 223                 PMD_DRV_LOG(NOTICE,
 224                             "resource in use (status 0x%x bit 0x%x)",
 225                             lock_status, resource_bit);
 226                 return -1;
 227         }
 228
 229         /* try every 5ms for 5 seconds */
 230         for (cnt = 0; cnt < 1000; cnt++) {
 231                 REG_WR(sc, (hw_lock_control_reg + 4), resource_bit);
 232                 lock_status = REG_RD(sc, hw_lock_control_reg);
 233                 if (lock_status & resource_bit) {
 234                         return 0;
 235                 }
 236                 DELAY(5000);
 237         }
 238
 239         PMD_DRV_LOG(NOTICE, "Resource lock timeout!");
 240         return -1;
 241 }
 242
 243 static int bnx2x_release_hw_lock(struct bnx2x_softc *sc, uint32_t resource)
 244 {
 245         uint32_t lock_status;
 246         uint32_t resource_bit = (1 << resource);
 247         int func = SC_FUNC(sc);
 248         uint32_t hw_lock_control_reg;
 249
 250         PMD_INIT_FUNC_TRACE();
 251
 252         /* validate the resource is within range */
 253         if (resource > HW_LOCK_MAX_RESOURCE_VALUE) {
 254                 PMD_DRV_LOG(NOTICE,
 255                             "resource 0x%x > HW_LOCK_MAX_RESOURCE_VALUE",
 256                             resource);
 257                 return -1;
 258         }
 259
 260         if (func <= 5) {
 261                 hw_lock_control_reg = (MISC_REG_DRIVER_CONTROL_1 + (func * 8));
 262         } else {
 263                 hw_lock_control_reg =
 264                     (MISC_REG_DRIVER_CONTROL_7 + ((func - 6) * 8));
 265         }
 266
 267         /* validate the resource is currently taken */
 268         lock_status = REG_RD(sc, hw_lock_control_reg);
 269         if (!(lock_status & resource_bit)) {
 270                 PMD_DRV_LOG(NOTICE,
 271                             "resource not in use (status 0x%x bit 0x%x)",
 272                             lock_status, resource_bit);
 273                 return -1;
 274         }
 275
 276         REG_WR(sc, hw_lock_control_reg, resource_bit);
 277         return 0;
 278 }
 279
 280 /* copy command into DMAE command memory and set DMAE command Go */
 281 void bnx2x_post_dmae(struct bnx2x_softc *sc, struct dmae_command *dmae, int idx)
 282 {
 283         uint32_t cmd_offset;
 284         uint32_t i;
 285
 286         cmd_offset = (DMAE_REG_CMD_MEM + (sizeof(struct dmae_command) * idx));
 287         for (i = 0; i < ((sizeof(struct dmae_command) / 4)); i++) {
 288                 REG_WR(sc, (cmd_offset + (i * 4)), *(((uint32_t *) dmae) + i));
 289         }
 290
 291         REG_WR(sc, dmae_reg_go_c[idx], 1);
 292 }
 293
 294 uint32_t bnx2x_dmae_opcode_add_comp(uint32_t opcode, uint8_t comp_type)
 295 {
 296         return opcode | ((comp_type << DMAE_COMMAND_C_DST_SHIFT) |
 297                           DMAE_COMMAND_C_TYPE_ENABLE);
 298 }
 299
 300 uint32_t bnx2x_dmae_opcode_clr_src_reset(uint32_t opcode)
 301 {
 302         return opcode & ~DMAE_COMMAND_SRC_RESET;
 303 }
 304
 305 uint32_t
 306 bnx2x_dmae_opcode(struct bnx2x_softc * sc, uint8_t src_type, uint8_t dst_type,
 307                 uint8_t with_comp, uint8_t comp_type)
 308 {
 309         uint32_t opcode = 0;
 310
 311         opcode |= ((src_type << DMAE_COMMAND_SRC_SHIFT) |
 312                    (dst_type << DMAE_COMMAND_DST_SHIFT));
 313
 314         opcode |= (DMAE_COMMAND_SRC_RESET | DMAE_COMMAND_DST_RESET);
 315
 316         opcode |= (SC_PORT(sc) ? DMAE_CMD_PORT_1 : DMAE_CMD_PORT_0);
 317
 318         opcode |= ((SC_VN(sc) << DMAE_COMMAND_E1HVN_SHIFT) |
 319                    (SC_VN(sc) << DMAE_COMMAND_DST_VN_SHIFT));
 320
 321         opcode |= (DMAE_COM_SET_ERR << DMAE_COMMAND_ERR_POLICY_SHIFT);
 322
 323 #ifdef __BIG_ENDIAN
 324         opcode |= DMAE_CMD_ENDIANITY_B_DW_SWAP;
 325 #else
 326         opcode |= DMAE_CMD_ENDIANITY_DW_SWAP;
 327 #endif
 328
 329         if (with_comp) {
 330                 opcode = bnx2x_dmae_opcode_add_comp(opcode, comp_type);
 331         }
 332
 333         return opcode;
 334 }
 335
 336 static void
 337 bnx2x_prep_dmae_with_comp(struct bnx2x_softc *sc, struct dmae_command *dmae,
 338                         uint8_t src_type, uint8_t dst_type)
 339 {
 340         memset(dmae, 0, sizeof(struct dmae_command));
 341
 342         /* set the opcode */
 343         dmae->opcode = bnx2x_dmae_opcode(sc, src_type, dst_type,
 344                                        TRUE, DMAE_COMP_PCI);
 345
 346         /* fill in the completion parameters */
 347         dmae->comp_addr_lo = U64_LO(BNX2X_SP_MAPPING(sc, wb_comp));
 348         dmae->comp_addr_hi = U64_HI(BNX2X_SP_MAPPING(sc, wb_comp));
 349         dmae->comp_val = DMAE_COMP_VAL;
 350 }
 351
 352 /* issue a DMAE command over the init channel and wait for completion */
 353 static int
 354 bnx2x_issue_dmae_with_comp(struct bnx2x_softc *sc, struct dmae_command *dmae)
 355 {
 356         uint32_t *wb_comp = BNX2X_SP(sc, wb_comp);
 357         int timeout = CHIP_REV_IS_SLOW(sc) ? 400000 : 4000;
 358
 359         /* reset completion */
 360         *wb_comp = 0;
 361
 362         /* post the command on the channel used for initializations */
 363         bnx2x_post_dmae(sc, dmae, INIT_DMAE_C(sc));
 364
 365         /* wait for completion */
 366         DELAY(500);
 367
 368         while ((*wb_comp & ~DMAE_PCI_ERR_FLAG) != DMAE_COMP_VAL) {
 369                 if (!timeout ||
 370                     (sc->recovery_state != BNX2X_RECOVERY_DONE &&
 371                      sc->recovery_state != BNX2X_RECOVERY_NIC_LOADING)) {
 372                         PMD_DRV_LOG(INFO, "DMAE timeout!");
 373                         return DMAE_TIMEOUT;
 374                 }
 375
 376                 timeout--;
 377                 DELAY(50);
 378         }
 379
 380         if (*wb_comp & DMAE_PCI_ERR_FLAG) {
 381                 PMD_DRV_LOG(INFO, "DMAE PCI error!");
 382                 return DMAE_PCI_ERROR;
 383         }
 384
 385         return 0;
 386 }
 387
 388 void bnx2x_read_dmae(struct bnx2x_softc *sc, uint32_t src_addr, uint32_t len32)
 389 {
 390         struct dmae_command dmae;
 391         uint32_t *data;
 392         uint32_t i;
 393         int rc;
 394
 395         if (!sc->dmae_ready) {
 396                 data = BNX2X_SP(sc, wb_data[0]);
 397
 398                 for (i = 0; i < len32; i++) {
 399                         data[i] = REG_RD(sc, (src_addr + (i * 4)));
 400                 }
 401
 402                 return;
 403         }
 404
 405         /* set opcode and fixed command fields */
 406         bnx2x_prep_dmae_with_comp(sc, &dmae, DMAE_SRC_GRC, DMAE_DST_PCI);
 407
 408         /* fill in addresses and len */
 409         dmae.src_addr_lo = (src_addr >> 2);     /* GRC addr has dword resolution */
 410         dmae.src_addr_hi = 0;
 411         dmae.dst_addr_lo = U64_LO(BNX2X_SP_MAPPING(sc, wb_data));
 412         dmae.dst_addr_hi = U64_HI(BNX2X_SP_MAPPING(sc, wb_data));
 413         dmae.len = len32;
 414
 415         /* issue the command and wait for completion */
 416         if ((rc = bnx2x_issue_dmae_with_comp(sc, &dmae)) != 0) {
 417                 rte_panic("DMAE failed (%d)", rc);
 418         };
 419 }
 420
 421 void
 422 bnx2x_write_dmae(struct bnx2x_softc *sc, rte_iova_t dma_addr, uint32_t dst_addr,
 423                uint32_t len32)
 424 {
 425         struct dmae_command dmae;
 426         int rc;
 427
 428         if (!sc->dmae_ready) {
 429                 ecore_init_str_wr(sc, dst_addr, BNX2X_SP(sc, wb_data[0]), len32);
 430                 return;
 431         }
 432
 433         /* set opcode and fixed command fields */
 434         bnx2x_prep_dmae_with_comp(sc, &dmae, DMAE_SRC_PCI, DMAE_DST_GRC);
 435
 436         /* fill in addresses and len */
 437         dmae.src_addr_lo = U64_LO(dma_addr);
 438         dmae.src_addr_hi = U64_HI(dma_addr);
 439         dmae.dst_addr_lo = (dst_addr >> 2);     /* GRC addr has dword resolution */
 440         dmae.dst_addr_hi = 0;
 441         dmae.len = len32;
 442
 443         /* issue the command and wait for completion */
 444         if ((rc = bnx2x_issue_dmae_with_comp(sc, &dmae)) != 0) {
 445                 rte_panic("DMAE failed (%d)", rc);
 446         }
 447 }
 448
 449 static void
 450 bnx2x_write_dmae_phys_len(struct bnx2x_softc *sc, rte_iova_t phys_addr,
 451                         uint32_t addr, uint32_t len)
 452 {
 453         uint32_t dmae_wr_max = DMAE_LEN32_WR_MAX(sc);
 454         uint32_t offset = 0;
 455
 456         while (len > dmae_wr_max) {
 457                 bnx2x_write_dmae(sc, (phys_addr + offset),      /* src DMA address */
 458                                (addr + offset), /* dst GRC address */
 459                                dmae_wr_max);
 460                 offset += (dmae_wr_max * 4);
 461                 len -= dmae_wr_max;
 462         }
 463
 464         bnx2x_write_dmae(sc, (phys_addr + offset),      /* src DMA address */
 465                        (addr + offset), /* dst GRC address */
 466                        len);
 467 }
 468
 469 void
 470 bnx2x_set_ctx_validation(struct bnx2x_softc *sc, struct eth_context *cxt,
 471                        uint32_t cid)
 472 {
 473         /* ustorm cxt validation */
 474         cxt->ustorm_ag_context.cdu_usage =
 475             CDU_RSRVD_VALUE_TYPE_A(HW_CID(sc, cid),
 476                                    CDU_REGION_NUMBER_UCM_AG,
 477                                    ETH_CONNECTION_TYPE);
 478         /* xcontext validation */
 479         cxt->xstorm_ag_context.cdu_reserved =
 480             CDU_RSRVD_VALUE_TYPE_A(HW_CID(sc, cid),
 481                                    CDU_REGION_NUMBER_XCM_AG,
 482                                    ETH_CONNECTION_TYPE);
 483 }
 484
 485 static void
 486 bnx2x_storm_memset_hc_timeout(struct bnx2x_softc *sc, uint8_t fw_sb_id,
 487                             uint8_t sb_index, uint8_t ticks)
 488 {
 489         uint32_t addr =
 490             (BAR_CSTRORM_INTMEM +
 491              CSTORM_STATUS_BLOCK_DATA_TIMEOUT_OFFSET(fw_sb_id, sb_index));
 492
 493         REG_WR8(sc, addr, ticks);
 494 }
 495
 496 static void
 497 bnx2x_storm_memset_hc_disable(struct bnx2x_softc *sc, uint16_t fw_sb_id,
 498                             uint8_t sb_index, uint8_t disable)
 499 {
 500         uint32_t enable_flag =
 501             (disable) ? 0 : (1 << HC_INDEX_DATA_HC_ENABLED_SHIFT);
 502         uint32_t addr =
 503             (BAR_CSTRORM_INTMEM +
 504              CSTORM_STATUS_BLOCK_DATA_FLAGS_OFFSET(fw_sb_id, sb_index));
 505         uint8_t flags;
 506
 507         /* clear and set */
 508         flags = REG_RD8(sc, addr);
 509         flags &= ~HC_INDEX_DATA_HC_ENABLED;
 510         flags |= enable_flag;
 511         REG_WR8(sc, addr, flags);
 512 }
 513
 514 void
 515 bnx2x_update_coalesce_sb_index(struct bnx2x_softc *sc, uint8_t fw_sb_id,
 516                              uint8_t sb_index, uint8_t disable, uint16_t usec)
 517 {
 518         uint8_t ticks = (usec / 4);
 519
 520         bnx2x_storm_memset_hc_timeout(sc, fw_sb_id, sb_index, ticks);
 521
 522         disable = (disable) ? 1 : ((usec) ? 0 : 1);
 523         bnx2x_storm_memset_hc_disable(sc, fw_sb_id, sb_index, disable);
 524 }
 525
 526 uint32_t elink_cb_reg_read(struct bnx2x_softc *sc, uint32_t reg_addr)
 527 {
 528         return REG_RD(sc, reg_addr);
 529 }
 530
 531 void elink_cb_reg_write(struct bnx2x_softc *sc, uint32_t reg_addr, uint32_t val)
 532 {
 533         REG_WR(sc, reg_addr, val);
 534 }
 535
 536 void
 537 elink_cb_event_log(__rte_unused struct bnx2x_softc *sc,
 538                    __rte_unused const elink_log_id_t elink_log_id, ...)
 539 {
 540         PMD_DRV_LOG(DEBUG, "ELINK EVENT LOG (%d)", elink_log_id);
 541 }
 542
 543 static int bnx2x_set_spio(struct bnx2x_softc *sc, int spio, uint32_t mode)
 544 {
 545         uint32_t spio_reg;
 546
 547         /* Only 2 SPIOs are configurable */
 548         if ((spio != MISC_SPIO_SPIO4) && (spio != MISC_SPIO_SPIO5)) {
 549                 PMD_DRV_LOG(NOTICE, "Invalid SPIO 0x%x", spio);
 550                 return -1;
 551         }
 552
 553         bnx2x_acquire_hw_lock(sc, HW_LOCK_RESOURCE_SPIO);
 554
 555         /* read SPIO and mask except the float bits */
 556         spio_reg = (REG_RD(sc, MISC_REG_SPIO) & MISC_SPIO_FLOAT);
 557
 558         switch (mode) {
 559         case MISC_SPIO_OUTPUT_LOW:
 560                 /* clear FLOAT and set CLR */
 561                 spio_reg &= ~(spio << MISC_SPIO_FLOAT_POS);
 562                 spio_reg |= (spio << MISC_SPIO_CLR_POS);
 563                 break;
 564
 565         case MISC_SPIO_OUTPUT_HIGH:
 566                 /* clear FLOAT and set SET */
 567                 spio_reg &= ~(spio << MISC_SPIO_FLOAT_POS);
 568                 spio_reg |= (spio << MISC_SPIO_SET_POS);
 569                 break;
 570
 571         case MISC_SPIO_INPUT_HI_Z:
 572                 /* set FLOAT */
 573                 spio_reg |= (spio << MISC_SPIO_FLOAT_POS);
 574                 break;
 575
 576         default:
 577                 break;
 578         }
 579
 580         REG_WR(sc, MISC_REG_SPIO, spio_reg);
 581         bnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_SPIO);
 582
 583         return 0;
 584 }
 585
 586 static int bnx2x_gpio_read(struct bnx2x_softc *sc, int gpio_num, uint8_t port)
 587 {
 588         /* The GPIO should be swapped if swap register is set and active */
 589         int gpio_port = ((REG_RD(sc, NIG_REG_PORT_SWAP) &&
 590                           REG_RD(sc, NIG_REG_STRAP_OVERRIDE)) ^ port);
 591         int gpio_shift = gpio_num;
 592         if (gpio_port)
 593                 gpio_shift += MISC_REGISTERS_GPIO_PORT_SHIFT;
 594
 595         uint32_t gpio_mask = (1 << gpio_shift);
 596         uint32_t gpio_reg;
 597
 598         if (gpio_num > MISC_REGISTERS_GPIO_3) {
 599                 PMD_DRV_LOG(NOTICE, "Invalid GPIO %d", gpio_num);
 600                 return -1;
 601         }
 602
 603         /* read GPIO value */
 604         gpio_reg = REG_RD(sc, MISC_REG_GPIO);
 605
 606         /* get the requested pin value */
 607         return ((gpio_reg & gpio_mask) == gpio_mask) ? 1 : 0;
 608 }
 609
 610 static int
 611 bnx2x_gpio_write(struct bnx2x_softc *sc, int gpio_num, uint32_t mode, uint8_t port)
 612 {
 613         /* The GPIO should be swapped if swap register is set and active */
 614         int gpio_port = ((REG_RD(sc, NIG_REG_PORT_SWAP) &&
 615                           REG_RD(sc, NIG_REG_STRAP_OVERRIDE)) ^ port);
 616         int gpio_shift = gpio_num;
 617         if (gpio_port)
 618                 gpio_shift += MISC_REGISTERS_GPIO_PORT_SHIFT;
 619
 620         uint32_t gpio_mask = (1 << gpio_shift);
 621         uint32_t gpio_reg;
 622
 623         if (gpio_num > MISC_REGISTERS_GPIO_3) {
 624                 PMD_DRV_LOG(NOTICE, "Invalid GPIO %d", gpio_num);
 625                 return -1;
 626         }
 627
 628         bnx2x_acquire_hw_lock(sc, HW_LOCK_RESOURCE_GPIO);
 629
 630         /* read GPIO and mask except the float bits */
 631         gpio_reg = (REG_RD(sc, MISC_REG_GPIO) & MISC_REGISTERS_GPIO_FLOAT);
 632
 633         switch (mode) {
 634         case MISC_REGISTERS_GPIO_OUTPUT_LOW:
 635                 /* clear FLOAT and set CLR */
 636                 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS);
 637                 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_CLR_POS);
 638                 break;
 639
 640         case MISC_REGISTERS_GPIO_OUTPUT_HIGH:
 641                 /* clear FLOAT and set SET */
 642                 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS);
 643                 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_SET_POS);
 644                 break;
 645
 646         case MISC_REGISTERS_GPIO_INPUT_HI_Z:
 647                 /* set FLOAT */
 648                 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS);
 649                 break;
 650
 651         default:
 652                 break;
 653         }
 654
 655         REG_WR(sc, MISC_REG_GPIO, gpio_reg);
 656         bnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_GPIO);
 657
 658         return 0;
 659 }
 660
 661 static int
 662 bnx2x_gpio_mult_write(struct bnx2x_softc *sc, uint8_t pins, uint32_t mode)
 663 {
 664         uint32_t gpio_reg;
 665
 666         /* any port swapping should be handled by caller */
 667
 668         bnx2x_acquire_hw_lock(sc, HW_LOCK_RESOURCE_GPIO);
 669
 670         /* read GPIO and mask except the float bits */
 671         gpio_reg = REG_RD(sc, MISC_REG_GPIO);
 672         gpio_reg &= ~(pins << MISC_REGISTERS_GPIO_FLOAT_POS);
 673         gpio_reg &= ~(pins << MISC_REGISTERS_GPIO_CLR_POS);
 674         gpio_reg &= ~(pins << MISC_REGISTERS_GPIO_SET_POS);
 675
 676         switch (mode) {
 677         case MISC_REGISTERS_GPIO_OUTPUT_LOW:
 678                 /* set CLR */
 679                 gpio_reg |= (pins << MISC_REGISTERS_GPIO_CLR_POS);
 680                 break;
 681
 682         case MISC_REGISTERS_GPIO_OUTPUT_HIGH:
 683                 /* set SET */
 684                 gpio_reg |= (pins << MISC_REGISTERS_GPIO_SET_POS);
 685                 break;
 686
 687         case MISC_REGISTERS_GPIO_INPUT_HI_Z:
 688                 /* set FLOAT */
 689                 gpio_reg |= (pins << MISC_REGISTERS_GPIO_FLOAT_POS);
 690                 break;
 691
 692         default:
 693                 PMD_DRV_LOG(NOTICE, "Invalid GPIO mode assignment %d", mode);
 694                 bnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_GPIO);
 695                 return -1;
 696         }
 697
 698         REG_WR(sc, MISC_REG_GPIO, gpio_reg);
 699         bnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_GPIO);
 700
 701         return 0;
 702 }
 703
 704 static int
 705 bnx2x_gpio_int_write(struct bnx2x_softc *sc, int gpio_num, uint32_t mode,
 706                    uint8_t port)
 707 {
 708         /* The GPIO should be swapped if swap register is set and active */
 709         int gpio_port = ((REG_RD(sc, NIG_REG_PORT_SWAP) &&
 710                           REG_RD(sc, NIG_REG_STRAP_OVERRIDE)) ^ port);
 711         int gpio_shift = gpio_num;
 712         if (gpio_port)
 713                 gpio_shift += MISC_REGISTERS_GPIO_PORT_SHIFT;
 714
 715         uint32_t gpio_mask = (1 << gpio_shift);
 716         uint32_t gpio_reg;
 717
 718         if (gpio_num > MISC_REGISTERS_GPIO_3) {
 719                 PMD_DRV_LOG(NOTICE, "Invalid GPIO %d", gpio_num);
 720                 return -1;
 721         }
 722
 723         bnx2x_acquire_hw_lock(sc, HW_LOCK_RESOURCE_GPIO);
 724
 725         /* read GPIO int */
 726         gpio_reg = REG_RD(sc, MISC_REG_GPIO_INT);
 727
 728         switch (mode) {
 729         case MISC_REGISTERS_GPIO_INT_OUTPUT_CLR:
 730                 /* clear SET and set CLR */
 731                 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_INT_SET_POS);
 732                 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_INT_CLR_POS);
 733                 break;
 734
 735         case MISC_REGISTERS_GPIO_INT_OUTPUT_SET:
 736                 /* clear CLR and set SET */
 737                 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_INT_CLR_POS);
 738                 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_INT_SET_POS);
 739                 break;
 740
 741         default:
 742                 break;
 743         }
 744
 745         REG_WR(sc, MISC_REG_GPIO_INT, gpio_reg);
 746         bnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_GPIO);
 747
 748         return 0;
 749 }
 750
 751 uint32_t
 752 elink_cb_gpio_read(struct bnx2x_softc * sc, uint16_t gpio_num, uint8_t port)
 753 {
 754         return bnx2x_gpio_read(sc, gpio_num, port);
 755 }
 756
 757 uint8_t elink_cb_gpio_write(struct bnx2x_softc * sc, uint16_t gpio_num, uint8_t mode,   /* 0=low 1=high */
 758                             uint8_t port)
 759 {
 760         return bnx2x_gpio_write(sc, gpio_num, mode, port);
 761 }
 762
 763 uint8_t
 764 elink_cb_gpio_mult_write(struct bnx2x_softc * sc, uint8_t pins,
 765                          uint8_t mode /* 0=low 1=high */ )
 766 {
 767         return bnx2x_gpio_mult_write(sc, pins, mode);
 768 }
 769
 770 uint8_t elink_cb_gpio_int_write(struct bnx2x_softc * sc, uint16_t gpio_num, uint8_t mode,       /* 0=low 1=high */
 771                                 uint8_t port)
 772 {
 773         return bnx2x_gpio_int_write(sc, gpio_num, mode, port);
 774 }
 775
 776 void elink_cb_notify_link_changed(struct bnx2x_softc *sc)
 777 {
 778         REG_WR(sc, (MISC_REG_AEU_GENERAL_ATTN_12 +
 779                     (SC_FUNC(sc) * sizeof(uint32_t))), 1);
 780 }
 781
 782 /* send the MCP a request, block until there is a reply */
 783 uint32_t
 784 elink_cb_fw_command(struct bnx2x_softc *sc, uint32_t command, uint32_t param)
 785 {
 786         int mb_idx = SC_FW_MB_IDX(sc);
 787         uint32_t seq;
 788         uint32_t rc = 0;
 789         uint32_t cnt = 1;
 790         uint8_t delay = CHIP_REV_IS_SLOW(sc) ? 100 : 10;
 791
 792         seq = ++sc->fw_seq;
 793         SHMEM_WR(sc, func_mb[mb_idx].drv_mb_param, param);
 794         SHMEM_WR(sc, func_mb[mb_idx].drv_mb_header, (command | seq));
 795
 796         PMD_DRV_LOG(DEBUG,
 797                     "wrote command 0x%08x to FW MB param 0x%08x",
 798                     (command | seq), param);
 799
 800         /* Let the FW do it's magic. GIve it up to 5 seconds... */
 801         do {
 802                 DELAY(delay * 1000);
 803                 rc = SHMEM_RD(sc, func_mb[mb_idx].fw_mb_header);
 804         } while ((seq != (rc & FW_MSG_SEQ_NUMBER_MASK)) && (cnt++ < 500));
 805
 806         /* is this a reply to our command? */
 807         if (seq == (rc & FW_MSG_SEQ_NUMBER_MASK)) {
 808                 rc &= FW_MSG_CODE_MASK;
 809         } else {
 810                 /* Ruh-roh! */
 811                 PMD_DRV_LOG(NOTICE, "FW failed to respond!");
 812                 rc = 0;
 813         }
 814
 815         return rc;
 816 }
 817
 818 static uint32_t
 819 bnx2x_fw_command(struct bnx2x_softc *sc, uint32_t command, uint32_t param)
 820 {
 821         return elink_cb_fw_command(sc, command, param);
 822 }
 823
 824 static void
 825 __storm_memset_dma_mapping(struct bnx2x_softc *sc, uint32_t addr,
 826                            rte_iova_t mapping)
 827 {
 828         REG_WR(sc, addr, U64_LO(mapping));
 829         REG_WR(sc, (addr + 4), U64_HI(mapping));
 830 }
 831
 832 static void
 833 storm_memset_spq_addr(struct bnx2x_softc *sc, rte_iova_t mapping,
 834                       uint16_t abs_fid)
 835 {
 836         uint32_t addr = (XSEM_REG_FAST_MEMORY +
 837                          XSTORM_SPQ_PAGE_BASE_OFFSET(abs_fid));
 838         __storm_memset_dma_mapping(sc, addr, mapping);
 839 }
 840
 841 static void
 842 storm_memset_vf_to_pf(struct bnx2x_softc *sc, uint16_t abs_fid, uint16_t pf_id)
 843 {
 844         REG_WR8(sc, (BAR_XSTRORM_INTMEM + XSTORM_VF_TO_PF_OFFSET(abs_fid)),
 845                 pf_id);
 846         REG_WR8(sc, (BAR_CSTRORM_INTMEM + CSTORM_VF_TO_PF_OFFSET(abs_fid)),
 847                 pf_id);
 848         REG_WR8(sc, (BAR_TSTRORM_INTMEM + TSTORM_VF_TO_PF_OFFSET(abs_fid)),
 849                 pf_id);
 850         REG_WR8(sc, (BAR_USTRORM_INTMEM + USTORM_VF_TO_PF_OFFSET(abs_fid)),
 851                 pf_id);
 852 }
 853
 854 static void
 855 storm_memset_func_en(struct bnx2x_softc *sc, uint16_t abs_fid, uint8_t enable)
 856 {
 857         REG_WR8(sc, (BAR_XSTRORM_INTMEM + XSTORM_FUNC_EN_OFFSET(abs_fid)),
 858                 enable);
 859         REG_WR8(sc, (BAR_CSTRORM_INTMEM + CSTORM_FUNC_EN_OFFSET(abs_fid)),
 860                 enable);
 861         REG_WR8(sc, (BAR_TSTRORM_INTMEM + TSTORM_FUNC_EN_OFFSET(abs_fid)),
 862                 enable);
 863         REG_WR8(sc, (BAR_USTRORM_INTMEM + USTORM_FUNC_EN_OFFSET(abs_fid)),
 864                 enable);
 865 }
 866
 867 static void
 868 storm_memset_eq_data(struct bnx2x_softc *sc, struct event_ring_data *eq_data,
 869                      uint16_t pfid)
 870 {
 871         uint32_t addr;
 872         size_t size;
 873
 874         addr = (BAR_CSTRORM_INTMEM + CSTORM_EVENT_RING_DATA_OFFSET(pfid));
 875         size = sizeof(struct event_ring_data);
 876         ecore_storm_memset_struct(sc, addr, size, (uint32_t *) eq_data);
 877 }
 878
 879 static void
 880 storm_memset_eq_prod(struct bnx2x_softc *sc, uint16_t eq_prod, uint16_t pfid)
 881 {
 882         uint32_t addr = (BAR_CSTRORM_INTMEM +
 883                          CSTORM_EVENT_RING_PROD_OFFSET(pfid));
 884         REG_WR16(sc, addr, eq_prod);
 885 }
 886
 887 /*
 888  * Post a slowpath command.
 889  *
 890  * A slowpath command is used to propagate a configuration change through
 891  * the controller in a controlled manner, allowing each STORM processor and
 892  * other H/W blocks to phase in the change.  The commands sent on the
 893  * slowpath are referred to as ramrods.  Depending on the ramrod used the
 894  * completion of the ramrod will occur in different ways.  Here's a
 895  * breakdown of ramrods and how they complete:
 896  *
 897  * RAMROD_CMD_ID_ETH_PORT_SETUP
 898  *   Used to setup the leading connection on a port.  Completes on the
 899  *   Receive Completion Queue (RCQ) of that port (typically fp[0]).
 900  *
 901  * RAMROD_CMD_ID_ETH_CLIENT_SETUP
 902  *   Used to setup an additional connection on a port.  Completes on the
 903  *   RCQ of the multi-queue/RSS connection being initialized.
 904  *
 905  * RAMROD_CMD_ID_ETH_STAT_QUERY
 906  *   Used to force the storm processors to update the statistics database
 907  *   in host memory.  This ramrod is send on the leading connection CID and
 908  *   completes as an index increment of the CSTORM on the default status
 909  *   block.
 910  *
 911  * RAMROD_CMD_ID_ETH_UPDATE
 912  *   Used to update the state of the leading connection, usually to udpate
 913  *   the RSS indirection table.  Completes on the RCQ of the leading
 914  *   connection. (Not currently used under FreeBSD until OS support becomes
 915  *   available.)
 916  *
 917  * RAMROD_CMD_ID_ETH_HALT
 918  *   Used when tearing down a connection prior to driver unload.  Completes
 919  *   on the RCQ of the multi-queue/RSS connection being torn down.  Don't
 920  *   use this on the leading connection.
 921  *
 922  * RAMROD_CMD_ID_ETH_SET_MAC
 923  *   Sets the Unicast/Broadcast/Multicast used by the port.  Completes on
 924  *   the RCQ of the leading connection.
 925  *
 926  * RAMROD_CMD_ID_ETH_CFC_DEL
 927  *   Used when tearing down a conneciton prior to driver unload.  Completes
 928  *   on the RCQ of the leading connection (since the current connection
 929  *   has been completely removed from controller memory).
 930  *
 931  * RAMROD_CMD_ID_ETH_PORT_DEL
 932  *   Used to tear down the leading connection prior to driver unload,
 933  *   typically fp[0].  Completes as an index increment of the CSTORM on the
 934  *   default status block.
 935  *
 936  * RAMROD_CMD_ID_ETH_FORWARD_SETUP
 937  *   Used for connection offload.  Completes on the RCQ of the multi-queue
 938  *   RSS connection that is being offloaded.  (Not currently used under
 939  *   FreeBSD.)
 940  *
 941  * There can only be one command pending per function.
 942  *
 943  * Returns:
 944  *   0 = Success, !0 = Failure.
 945  */
 946
 947 /* must be called under the spq lock */
 948 static inline struct eth_spe *bnx2x_sp_get_next(struct bnx2x_softc *sc)
 949 {
 950         struct eth_spe *next_spe = sc->spq_prod_bd;
 951
 952         if (sc->spq_prod_bd == sc->spq_last_bd) {
 953                 /* wrap back to the first eth_spq */
 954                 sc->spq_prod_bd = sc->spq;
 955                 sc->spq_prod_idx = 0;
 956         } else {
 957                 sc->spq_prod_bd++;
 958                 sc->spq_prod_idx++;
 959         }
 960
 961         return next_spe;
 962 }
 963
 964 /* must be called under the spq lock */
 965 static void bnx2x_sp_prod_update(struct bnx2x_softc *sc)
 966 {
 967         int func = SC_FUNC(sc);
 968
 969         /*
 970          * Make sure that BD data is updated before writing the producer.
 971          * BD data is written to the memory, the producer is read from the
 972          * memory, thus we need a full memory barrier to ensure the ordering.
 973          */
 974         mb();
 975
 976         REG_WR16(sc, (BAR_XSTRORM_INTMEM + XSTORM_SPQ_PROD_OFFSET(func)),
 977                  sc->spq_prod_idx);
 978
 979         mb();
 980 }
 981
 982 /**
 983  * bnx2x_is_contextless_ramrod - check if the current command ends on EQ
 984  *
 985  * @cmd:      command to check
 986  * @cmd_type: command type
 987  */
 988 static int bnx2x_is_contextless_ramrod(int cmd, int cmd_type)
 989 {
 990         if ((cmd_type == NONE_CONNECTION_TYPE) ||
 991             (cmd == RAMROD_CMD_ID_ETH_FORWARD_SETUP) ||
 992             (cmd == RAMROD_CMD_ID_ETH_CLASSIFICATION_RULES) ||
 993             (cmd == RAMROD_CMD_ID_ETH_FILTER_RULES) ||
 994             (cmd == RAMROD_CMD_ID_ETH_MULTICAST_RULES) ||
 995             (cmd == RAMROD_CMD_ID_ETH_SET_MAC) ||
 996             (cmd == RAMROD_CMD_ID_ETH_RSS_UPDATE)) {
 997                 return TRUE;
 998         } else {
 999                 return FALSE;
1000         }
1001 }
1002
1003 /**
1004  * bnx2x_sp_post - place a single command on an SP ring
1005  *
1006  * @sc:         driver handle
1007  * @command:    command to place (e.g. SETUP, FILTER_RULES, etc.)
1008  * @cid:        SW CID the command is related to
1009  * @data_hi:    command private data address (high 32 bits)
1010  * @data_lo:    command private data address (low 32 bits)
1011  * @cmd_type:   command type (e.g. NONE, ETH)
1012  *
1013  * SP data is handled as if it's always an address pair, thus data fields are
1014  * not swapped to little endian in upper functions. Instead this function swaps
1015  * data as if it's two uint32 fields.
1016  */
1017 int
1018 bnx2x_sp_post(struct bnx2x_softc *sc, int command, int cid, uint32_t data_hi,
1019             uint32_t data_lo, int cmd_type)
1020 {
1021         struct eth_spe *spe;
1022         uint16_t type;
1023         int common;
1024
1025         common = bnx2x_is_contextless_ramrod(command, cmd_type);
1026
1027         if (common) {
1028                 if (!atomic_load_acq_long(&sc->eq_spq_left)) {
1029                         PMD_DRV_LOG(INFO, "EQ ring is full!");
1030                         return -1;
1031                 }
1032         } else {
1033                 if (!atomic_load_acq_long(&sc->cq_spq_left)) {
1034                         PMD_DRV_LOG(INFO, "SPQ ring is full!");
1035                         return -1;
1036                 }
1037         }
1038
1039         spe = bnx2x_sp_get_next(sc);
1040
1041         /* CID needs port number to be encoded int it */
1042         spe->hdr.conn_and_cmd_data =
1043             htole32((command << SPE_HDR_CMD_ID_SHIFT) | HW_CID(sc, cid));
1044
1045         type = (cmd_type << SPE_HDR_CONN_TYPE_SHIFT) & SPE_HDR_CONN_TYPE;
1046
1047         /* TBD: Check if it works for VFs */
1048         type |= ((SC_FUNC(sc) << SPE_HDR_FUNCTION_ID_SHIFT) &
1049                  SPE_HDR_FUNCTION_ID);
1050
1051         spe->hdr.type = htole16(type);
1052
1053         spe->data.update_data_addr.hi = htole32(data_hi);
1054         spe->data.update_data_addr.lo = htole32(data_lo);
1055
1056         /*
1057          * It's ok if the actual decrement is issued towards the memory
1058          * somewhere between the lock and unlock. Thus no more explict
1059          * memory barrier is needed.
1060          */
1061         if (common) {
1062                 atomic_subtract_acq_long(&sc->eq_spq_left, 1);
1063         } else {
1064                 atomic_subtract_acq_long(&sc->cq_spq_left, 1);
1065         }
1066
1067         PMD_DRV_LOG(DEBUG,
1068                     "SPQE[%x] (%x:%x) (cmd, common?) (%d,%d) hw_cid %x"
1069                     "data (%x:%x) type(0x%x) left (CQ, EQ) (%lx,%lx)",
1070                     sc->spq_prod_idx,
1071                     (uint32_t) U64_HI(sc->spq_dma.paddr),
1072                     (uint32_t) (U64_LO(sc->spq_dma.paddr) +
1073                                 (uint8_t *) sc->spq_prod_bd -
1074                                 (uint8_t *) sc->spq), command, common,
1075                     HW_CID(sc, cid), data_hi, data_lo, type,
1076                     atomic_load_acq_long(&sc->cq_spq_left),
1077                     atomic_load_acq_long(&sc->eq_spq_left));
1078
1079         bnx2x_sp_prod_update(sc);
1080
1081         return 0;
1082 }
1083
1084 static void bnx2x_drv_pulse(struct bnx2x_softc *sc)
1085 {
1086         SHMEM_WR(sc, func_mb[SC_FW_MB_IDX(sc)].drv_pulse_mb,
1087                  sc->fw_drv_pulse_wr_seq);
1088 }
1089
1090 static int bnx2x_tx_queue_has_work(const struct bnx2x_fastpath *fp)
1091 {
1092         uint16_t hw_cons;
1093         struct bnx2x_tx_queue *txq = fp->sc->tx_queues[fp->index];
1094
1095         if (unlikely(!txq)) {
1096                 PMD_TX_LOG(ERR, "ERROR: TX queue is NULL");
1097                 return 0;
1098         }
1099
1100         mb();                   /* status block fields can change */
1101         hw_cons = le16toh(*fp->tx_cons_sb);
1102         return hw_cons != txq->tx_pkt_head;
1103 }
1104
1105 static uint8_t bnx2x_has_tx_work(struct bnx2x_fastpath *fp)
1106 {
1107         /* expand this for multi-cos if ever supported */
1108         return bnx2x_tx_queue_has_work(fp);
1109 }
1110
1111 static int bnx2x_has_rx_work(struct bnx2x_fastpath *fp)
1112 {
1113         uint16_t rx_cq_cons_sb;
1114         struct bnx2x_rx_queue *rxq;
1115         rxq = fp->sc->rx_queues[fp->index];
1116         if (unlikely(!rxq)) {
1117                 PMD_RX_LOG(ERR, "ERROR: RX queue is NULL");
1118                 return 0;
1119         }
1120
1121         mb();                   /* status block fields can change */
1122         rx_cq_cons_sb = le16toh(*fp->rx_cq_cons_sb);
1123         if (unlikely((rx_cq_cons_sb & MAX_RCQ_ENTRIES(rxq)) ==
1124                      MAX_RCQ_ENTRIES(rxq)))
1125                 rx_cq_cons_sb++;
1126         return rxq->rx_cq_head != rx_cq_cons_sb;
1127 }
1128
1129 static void
1130 bnx2x_sp_event(struct bnx2x_softc *sc, struct bnx2x_fastpath *fp,
1131              union eth_rx_cqe *rr_cqe)
1132 {
1133         int cid = SW_CID(rr_cqe->ramrod_cqe.conn_and_cmd_data);
1134         int command = CQE_CMD(rr_cqe->ramrod_cqe.conn_and_cmd_data);
1135         enum ecore_queue_cmd drv_cmd = ECORE_Q_CMD_MAX;
1136         struct ecore_queue_sp_obj *q_obj = &BNX2X_SP_OBJ(sc, fp).q_obj;
1137
1138         PMD_DRV_LOG(DEBUG,
1139                     "fp=%d cid=%d got ramrod #%d state is %x type is %d",
1140                     fp->index, cid, command, sc->state,
1141                     rr_cqe->ramrod_cqe.ramrod_type);
1142
1143         switch (command) {
1144         case (RAMROD_CMD_ID_ETH_CLIENT_UPDATE):
1145                 PMD_DRV_LOG(DEBUG, "got UPDATE ramrod. CID %d", cid);
1146                 drv_cmd = ECORE_Q_CMD_UPDATE;
1147                 break;
1148
1149         case (RAMROD_CMD_ID_ETH_CLIENT_SETUP):
1150                 PMD_DRV_LOG(DEBUG, "got MULTI[%d] setup ramrod", cid);
1151                 drv_cmd = ECORE_Q_CMD_SETUP;
1152                 break;
1153
1154         case (RAMROD_CMD_ID_ETH_TX_QUEUE_SETUP):
1155                 PMD_DRV_LOG(DEBUG, "got MULTI[%d] tx-only setup ramrod", cid);
1156                 drv_cmd = ECORE_Q_CMD_SETUP_TX_ONLY;
1157                 break;
1158
1159         case (RAMROD_CMD_ID_ETH_HALT):
1160                 PMD_DRV_LOG(DEBUG, "got MULTI[%d] halt ramrod", cid);
1161                 drv_cmd = ECORE_Q_CMD_HALT;
1162                 break;
1163
1164         case (RAMROD_CMD_ID_ETH_TERMINATE):
1165                 PMD_DRV_LOG(DEBUG, "got MULTI[%d] teminate ramrod", cid);
1166                 drv_cmd = ECORE_Q_CMD_TERMINATE;
1167                 break;
1168
1169         case (RAMROD_CMD_ID_ETH_EMPTY):
1170                 PMD_DRV_LOG(DEBUG, "got MULTI[%d] empty ramrod", cid);
1171                 drv_cmd = ECORE_Q_CMD_EMPTY;
1172                 break;
1173
1174         default:
1175                 PMD_DRV_LOG(DEBUG,
1176                             "ERROR: unexpected MC reply (%d)"
1177                             "on fp[%d]", command, fp->index);
1178                 return;
1179         }
1180
1181         if ((drv_cmd != ECORE_Q_CMD_MAX) &&
1182             q_obj->complete_cmd(sc, q_obj, drv_cmd)) {
1183                 /*
1184                  * q_obj->complete_cmd() failure means that this was
1185                  * an unexpected completion.
1186                  *
1187                  * In this case we don't want to increase the sc->spq_left
1188                  * because apparently we haven't sent this command the first
1189                  * place.
1190                  */
1191                 // rte_panic("Unexpected SP completion");
1192                 return;
1193         }
1194
1195         atomic_add_acq_long(&sc->cq_spq_left, 1);
1196
1197         PMD_DRV_LOG(DEBUG, "sc->cq_spq_left 0x%lx",
1198                     atomic_load_acq_long(&sc->cq_spq_left));
1199 }
1200
1201 static uint8_t bnx2x_rxeof(struct bnx2x_softc *sc, struct bnx2x_fastpath *fp)
1202 {
1203         struct bnx2x_rx_queue *rxq;
1204         uint16_t bd_cons, bd_prod, bd_prod_fw, comp_ring_cons;
1205         uint16_t hw_cq_cons, sw_cq_cons, sw_cq_prod;
1206
1207         rxq = sc->rx_queues[fp->index];
1208         if (!rxq) {
1209                 PMD_RX_LOG(ERR, "RX queue %d is NULL", fp->index);
1210                 return 0;
1211         }
1212
1213         /* CQ "next element" is of the size of the regular element */
1214         hw_cq_cons = le16toh(*fp->rx_cq_cons_sb);
1215         if (unlikely((hw_cq_cons & USABLE_RCQ_ENTRIES_PER_PAGE) ==
1216                      USABLE_RCQ_ENTRIES_PER_PAGE)) {
1217                 hw_cq_cons++;
1218         }
1219
1220         bd_cons = rxq->rx_bd_head;
1221         bd_prod = rxq->rx_bd_tail;
1222         bd_prod_fw = bd_prod;
1223         sw_cq_cons = rxq->rx_cq_head;
1224         sw_cq_prod = rxq->rx_cq_tail;
1225
1226         /*
1227          * Memory barrier necessary as speculative reads of the rx
1228          * buffer can be ahead of the index in the status block
1229          */
1230         rmb();
1231
1232         while (sw_cq_cons != hw_cq_cons) {
1233                 union eth_rx_cqe *cqe;
1234                 struct eth_fast_path_rx_cqe *cqe_fp;
1235                 uint8_t cqe_fp_flags;
1236                 enum eth_rx_cqe_type cqe_fp_type;
1237
1238                 comp_ring_cons = RCQ_ENTRY(sw_cq_cons, rxq);
1239                 bd_prod = RX_BD(bd_prod, rxq);
1240                 bd_cons = RX_BD(bd_cons, rxq);
1241
1242                 cqe = &rxq->cq_ring[comp_ring_cons];
1243                 cqe_fp = &cqe->fast_path_cqe;
1244                 cqe_fp_flags = cqe_fp->type_error_flags;
1245                 cqe_fp_type = cqe_fp_flags & ETH_FAST_PATH_RX_CQE_TYPE;
1246
1247                 /* is this a slowpath msg? */
1248                 if (CQE_TYPE_SLOW(cqe_fp_type)) {
1249                         bnx2x_sp_event(sc, fp, cqe);
1250                         goto next_cqe;
1251                 }
1252
1253                 /* is this an error packet? */
1254                 if (unlikely(cqe_fp_flags &
1255                              ETH_FAST_PATH_RX_CQE_PHY_DECODE_ERR_FLG)) {
1256                         PMD_RX_LOG(DEBUG, "flags 0x%x rx packet %u",
1257                                    cqe_fp_flags, sw_cq_cons);
1258                         goto next_rx;
1259                 }
1260
1261                 PMD_RX_LOG(DEBUG, "Dropping fastpath called from attn poller!");
1262
1263 next_rx:
1264                 bd_cons = NEXT_RX_BD(bd_cons);
1265                 bd_prod = NEXT_RX_BD(bd_prod);
1266                 bd_prod_fw = NEXT_RX_BD(bd_prod_fw);
1267
1268 next_cqe:
1269                 sw_cq_prod = NEXT_RCQ_IDX(sw_cq_prod);
1270                 sw_cq_cons = NEXT_RCQ_IDX(sw_cq_cons);
1271
1272         }                       /* while work to do */
1273
1274         rxq->rx_bd_head = bd_cons;
1275         rxq->rx_bd_tail = bd_prod_fw;
1276         rxq->rx_cq_head = sw_cq_cons;
1277         rxq->rx_cq_tail = sw_cq_prod;
1278
1279         /* Update producers */
1280         bnx2x_update_rx_prod(sc, fp, bd_prod_fw, sw_cq_prod);
1281
1282         return sw_cq_cons != hw_cq_cons;
1283 }
1284
1285 static uint16_t
1286 bnx2x_free_tx_pkt(__rte_unused struct bnx2x_fastpath *fp, struct bnx2x_tx_queue *txq,
1287                 uint16_t pkt_idx, uint16_t bd_idx)
1288 {
1289         struct eth_tx_start_bd *tx_start_bd =
1290             &txq->tx_ring[TX_BD(bd_idx, txq)].start_bd;
1291         uint16_t nbd = rte_le_to_cpu_16(tx_start_bd->nbd);
1292         struct rte_mbuf *tx_mbuf = txq->sw_ring[TX_BD(pkt_idx, txq)];
1293
1294         if (likely(tx_mbuf != NULL)) {
1295                 rte_pktmbuf_free_seg(tx_mbuf);
1296         } else {
1297                 PMD_RX_LOG(ERR, "fp[%02d] lost mbuf %lu",
1298                            fp->index, (unsigned long)TX_BD(pkt_idx, txq));
1299         }
1300
1301         txq->sw_ring[TX_BD(pkt_idx, txq)] = NULL;
1302         txq->nb_tx_avail += nbd;
1303
1304         while (nbd--)
1305                 bd_idx = NEXT_TX_BD(bd_idx);
1306
1307         return bd_idx;
1308 }
1309
1310 /* processes transmit completions */
1311 uint8_t bnx2x_txeof(__rte_unused struct bnx2x_softc * sc, struct bnx2x_fastpath * fp)
1312 {
1313         uint16_t bd_cons, hw_cons, sw_cons;
1314         __rte_unused uint16_t tx_bd_avail;
1315
1316         struct bnx2x_tx_queue *txq = fp->sc->tx_queues[fp->index];
1317
1318         if (unlikely(!txq)) {
1319                 PMD_TX_LOG(ERR, "ERROR: TX queue is NULL");
1320                 return 0;
1321         }
1322
1323         bd_cons = txq->tx_bd_head;
1324         hw_cons = rte_le_to_cpu_16(*fp->tx_cons_sb);
1325         sw_cons = txq->tx_pkt_head;
1326
1327         while (sw_cons != hw_cons) {
1328                 bd_cons = bnx2x_free_tx_pkt(fp, txq, sw_cons, bd_cons);
1329                 sw_cons++;
1330         }
1331
1332         txq->tx_pkt_head = sw_cons;
1333         txq->tx_bd_head = bd_cons;
1334
1335         tx_bd_avail = txq->nb_tx_avail;
1336
1337         PMD_TX_LOG(DEBUG, "fp[%02d] avail=%u cons_sb=%u, "
1338                    "pkt_head=%u pkt_tail=%u bd_head=%u bd_tail=%u",
1339                    fp->index, tx_bd_avail, hw_cons,
1340                    txq->tx_pkt_head, txq->tx_pkt_tail,
1341                    txq->tx_bd_head, txq->tx_bd_tail);
1342         return TRUE;
1343 }
1344
1345 static void bnx2x_drain_tx_queues(struct bnx2x_softc *sc)
1346 {
1347         struct bnx2x_fastpath *fp;
1348         int i, count;
1349
1350         /* wait until all TX fastpath tasks have completed */
1351         for (i = 0; i < sc->num_queues; i++) {
1352                 fp = &sc->fp[i];
1353
1354                 count = 1000;
1355
1356                 while (bnx2x_has_tx_work(fp)) {
1357                         bnx2x_txeof(sc, fp);
1358
1359                         if (count == 0) {
1360                                 PMD_TX_LOG(ERR,
1361                                            "Timeout waiting for fp[%d] "
1362                                            "transmits to complete!", i);
1363                                 rte_panic("tx drain failure");
1364                                 return;
1365                         }
1366
1367                         count--;
1368                         DELAY(1000);
1369                         rmb();
1370                 }
1371         }
1372
1373         return;
1374 }
1375
1376 static int
1377 bnx2x_del_all_macs(struct bnx2x_softc *sc, struct ecore_vlan_mac_obj *mac_obj,
1378                  int mac_type, uint8_t wait_for_comp)
1379 {
1380         unsigned long ramrod_flags = 0, vlan_mac_flags = 0;
1381         int rc;
1382
1383         /* wait for completion of requested */
1384         if (wait_for_comp) {
1385                 bnx2x_set_bit(RAMROD_COMP_WAIT, &ramrod_flags);
1386         }
1387
1388         /* Set the mac type of addresses we want to clear */
1389         bnx2x_set_bit(mac_type, &vlan_mac_flags);
1390
1391         rc = mac_obj->delete_all(sc, mac_obj, &vlan_mac_flags, &ramrod_flags);
1392         if (rc < 0)
1393                 PMD_DRV_LOG(ERR, "Failed to delete MACs (%d)", rc);
1394
1395         return rc;
1396 }
1397
1398 static int
1399 bnx2x_fill_accept_flags(struct bnx2x_softc *sc, uint32_t rx_mode,
1400                         unsigned long *rx_accept_flags,
1401                         unsigned long *tx_accept_flags)
1402 {
1403         /* Clear the flags first */
1404         *rx_accept_flags = 0;
1405         *tx_accept_flags = 0;
1406
1407         switch (rx_mode) {
1408         case BNX2X_RX_MODE_NONE:
1409                 /*
1410                  * 'drop all' supersedes any accept flags that may have been
1411                  * passed to the function.
1412                  */
1413                 break;
1414
1415         case BNX2X_RX_MODE_NORMAL:
1416                 bnx2x_set_bit(ECORE_ACCEPT_UNICAST, rx_accept_flags);
1417                 bnx2x_set_bit(ECORE_ACCEPT_MULTICAST, rx_accept_flags);
1418                 bnx2x_set_bit(ECORE_ACCEPT_BROADCAST, rx_accept_flags);
1419
1420                 /* internal switching mode */
1421                 bnx2x_set_bit(ECORE_ACCEPT_UNICAST, tx_accept_flags);
1422                 bnx2x_set_bit(ECORE_ACCEPT_MULTICAST, tx_accept_flags);
1423                 bnx2x_set_bit(ECORE_ACCEPT_BROADCAST, tx_accept_flags);
1424
1425                 break;
1426
1427         case BNX2X_RX_MODE_ALLMULTI:
1428                 bnx2x_set_bit(ECORE_ACCEPT_UNICAST, rx_accept_flags);
1429                 bnx2x_set_bit(ECORE_ACCEPT_ALL_MULTICAST, rx_accept_flags);
1430                 bnx2x_set_bit(ECORE_ACCEPT_BROADCAST, rx_accept_flags);
1431
1432                 /* internal switching mode */
1433                 bnx2x_set_bit(ECORE_ACCEPT_UNICAST, tx_accept_flags);
1434                 bnx2x_set_bit(ECORE_ACCEPT_ALL_MULTICAST, tx_accept_flags);
1435                 bnx2x_set_bit(ECORE_ACCEPT_BROADCAST, tx_accept_flags);
1436
1437                 break;
1438
1439         case BNX2X_RX_MODE_ALLMULTI_PROMISC:
1440         case BNX2X_RX_MODE_PROMISC:
1441                 /*
1442                  * According to deffinition of SI mode, iface in promisc mode
1443                  * should receive matched and unmatched (in resolution of port)
1444                  * unicast packets.
1445                  */
1446                 bnx2x_set_bit(ECORE_ACCEPT_UNMATCHED, rx_accept_flags);
1447                 bnx2x_set_bit(ECORE_ACCEPT_UNICAST, rx_accept_flags);
1448                 bnx2x_set_bit(ECORE_ACCEPT_ALL_MULTICAST, rx_accept_flags);
1449                 bnx2x_set_bit(ECORE_ACCEPT_BROADCAST, rx_accept_flags);
1450
1451                 /* internal switching mode */
1452                 bnx2x_set_bit(ECORE_ACCEPT_ALL_MULTICAST, tx_accept_flags);
1453                 bnx2x_set_bit(ECORE_ACCEPT_BROADCAST, tx_accept_flags);
1454
1455                 if (IS_MF_SI(sc)) {
1456                         bnx2x_set_bit(ECORE_ACCEPT_ALL_UNICAST, tx_accept_flags);
1457                 } else {
1458                         bnx2x_set_bit(ECORE_ACCEPT_UNICAST, tx_accept_flags);
1459                 }
1460
1461                 break;
1462
1463         default:
1464                 PMD_RX_LOG(ERR, "Unknown rx_mode (%d)", rx_mode);
1465                 return -1;
1466         }
1467
1468         /* Set ACCEPT_ANY_VLAN as we do not enable filtering by VLAN */
1469         if (rx_mode != BNX2X_RX_MODE_NONE) {
1470                 bnx2x_set_bit(ECORE_ACCEPT_ANY_VLAN, rx_accept_flags);
1471                 bnx2x_set_bit(ECORE_ACCEPT_ANY_VLAN, tx_accept_flags);
1472         }
1473
1474         return 0;
1475 }
1476
1477 static int
1478 bnx2x_set_q_rx_mode(struct bnx2x_softc *sc, uint8_t cl_id,
1479                   unsigned long rx_mode_flags,
1480                   unsigned long rx_accept_flags,
1481                   unsigned long tx_accept_flags, unsigned long ramrod_flags)
1482 {
1483         struct ecore_rx_mode_ramrod_params ramrod_param;
1484         int rc;
1485
1486         memset(&ramrod_param, 0, sizeof(ramrod_param));
1487
1488         /* Prepare ramrod parameters */
1489         ramrod_param.cid = 0;
1490         ramrod_param.cl_id = cl_id;
1491         ramrod_param.rx_mode_obj = &sc->rx_mode_obj;
1492         ramrod_param.func_id = SC_FUNC(sc);
1493
1494         ramrod_param.pstate = &sc->sp_state;
1495         ramrod_param.state = ECORE_FILTER_RX_MODE_PENDING;
1496
1497         ramrod_param.rdata = BNX2X_SP(sc, rx_mode_rdata);
1498         ramrod_param.rdata_mapping =
1499             (rte_iova_t)BNX2X_SP_MAPPING(sc, rx_mode_rdata),
1500             bnx2x_set_bit(ECORE_FILTER_RX_MODE_PENDING, &sc->sp_state);
1501
1502         ramrod_param.ramrod_flags = ramrod_flags;
1503         ramrod_param.rx_mode_flags = rx_mode_flags;
1504
1505         ramrod_param.rx_accept_flags = rx_accept_flags;
1506         ramrod_param.tx_accept_flags = tx_accept_flags;
1507
1508         rc = ecore_config_rx_mode(sc, &ramrod_param);
1509         if (rc < 0) {
1510                 PMD_RX_LOG(ERR, "Set rx_mode %d failed", sc->rx_mode);
1511                 return rc;
1512         }
1513
1514         return 0;
1515 }
1516
1517 int bnx2x_set_storm_rx_mode(struct bnx2x_softc *sc)
1518 {
1519         unsigned long rx_mode_flags = 0, ramrod_flags = 0;
1520         unsigned long rx_accept_flags = 0, tx_accept_flags = 0;
1521         int rc;
1522
1523         rc = bnx2x_fill_accept_flags(sc, sc->rx_mode, &rx_accept_flags,
1524                                    &tx_accept_flags);
1525         if (rc) {
1526                 return rc;
1527         }
1528
1529         bnx2x_set_bit(RAMROD_RX, &ramrod_flags);
1530         bnx2x_set_bit(RAMROD_TX, &ramrod_flags);
1531         bnx2x_set_bit(RAMROD_COMP_WAIT, &ramrod_flags);
1532
1533         return bnx2x_set_q_rx_mode(sc, sc->fp[0].cl_id, rx_mode_flags,
1534                                  rx_accept_flags, tx_accept_flags,
1535                                  ramrod_flags);
1536 }
1537
1538 /* returns the "mcp load_code" according to global load_count array */
1539 static int bnx2x_nic_load_no_mcp(struct bnx2x_softc *sc)
1540 {
1541         int path = SC_PATH(sc);
1542         int port = SC_PORT(sc);
1543
1544         PMD_DRV_LOG(INFO, "NO MCP - load counts[%d]      %d, %d, %d",
1545                     path, load_count[path][0], load_count[path][1],
1546                     load_count[path][2]);
1547
1548         load_count[path][0]++;
1549         load_count[path][1 + port]++;
1550         PMD_DRV_LOG(INFO, "NO MCP - new load counts[%d]  %d, %d, %d",
1551                     path, load_count[path][0], load_count[path][1],
1552                     load_count[path][2]);
1553         if (load_count[path][0] == 1)
1554                 return FW_MSG_CODE_DRV_LOAD_COMMON;
1555         else if (load_count[path][1 + port] == 1)
1556                 return FW_MSG_CODE_DRV_LOAD_PORT;
1557         else
1558                 return FW_MSG_CODE_DRV_LOAD_FUNCTION;
1559 }
1560
1561 /* returns the "mcp load_code" according to global load_count array */
1562 static int bnx2x_nic_unload_no_mcp(struct bnx2x_softc *sc)
1563 {
1564         int port = SC_PORT(sc);
1565         int path = SC_PATH(sc);
1566
1567         PMD_DRV_LOG(INFO, "NO MCP - load counts[%d]      %d, %d, %d",
1568                     path, load_count[path][0], load_count[path][1],
1569                     load_count[path][2]);
1570         load_count[path][0]--;
1571         load_count[path][1 + port]--;
1572         PMD_DRV_LOG(INFO, "NO MCP - new load counts[%d]  %d, %d, %d",
1573                     path, load_count[path][0], load_count[path][1],
1574                     load_count[path][2]);
1575         if (load_count[path][0] == 0) {
1576                 return FW_MSG_CODE_DRV_UNLOAD_COMMON;
1577         } else if (load_count[path][1 + port] == 0) {
1578                 return FW_MSG_CODE_DRV_UNLOAD_PORT;
1579         } else {
1580                 return FW_MSG_CODE_DRV_UNLOAD_FUNCTION;
1581         }
1582 }
1583
1584 /* request unload mode from the MCP: COMMON, PORT or FUNCTION */
1585 static uint32_t bnx2x_send_unload_req(struct bnx2x_softc *sc, int unload_mode)
1586 {
1587         uint32_t reset_code = 0;
1588
1589         /* Select the UNLOAD request mode */
1590         if (unload_mode == UNLOAD_NORMAL) {
1591                 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS;
1592         } else {
1593                 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS;
1594         }
1595
1596         /* Send the request to the MCP */
1597         if (!BNX2X_NOMCP(sc)) {
1598                 reset_code = bnx2x_fw_command(sc, reset_code, 0);
1599         } else {
1600                 reset_code = bnx2x_nic_unload_no_mcp(sc);
1601         }
1602
1603         return reset_code;
1604 }
1605
1606 /* send UNLOAD_DONE command to the MCP */
1607 static void bnx2x_send_unload_done(struct bnx2x_softc *sc, uint8_t keep_link)
1608 {
1609         uint32_t reset_param =
1610             keep_link ? DRV_MSG_CODE_UNLOAD_SKIP_LINK_RESET : 0;
1611
1612         /* Report UNLOAD_DONE to MCP */
1613         if (!BNX2X_NOMCP(sc)) {
1614                 bnx2x_fw_command(sc, DRV_MSG_CODE_UNLOAD_DONE, reset_param);
1615         }
1616 }
1617
1618 static int bnx2x_func_wait_started(struct bnx2x_softc *sc)
1619 {
1620         int tout = 50;
1621
1622         if (!sc->port.pmf) {
1623                 return 0;
1624         }
1625
1626         /*
1627          * (assumption: No Attention from MCP at this stage)
1628          * PMF probably in the middle of TX disable/enable transaction
1629          * 1. Sync IRS for default SB
1630          * 2. Sync SP queue - this guarantees us that attention handling started
1631          * 3. Wait, that TX disable/enable transaction completes
1632          *
1633          * 1+2 guarantee that if DCBX attention was scheduled it already changed
1634          * pending bit of transaction from STARTED-->TX_STOPPED, if we already
1635          * received completion for the transaction the state is TX_STOPPED.
1636          * State will return to STARTED after completion of TX_STOPPED-->STARTED
1637          * transaction.
1638          */
1639
1640         while (ecore_func_get_state(sc, &sc->func_obj) !=
1641                ECORE_F_STATE_STARTED && tout--) {
1642                 DELAY(20000);
1643         }
1644
1645         if (ecore_func_get_state(sc, &sc->func_obj) != ECORE_F_STATE_STARTED) {
1646                 /*
1647                  * Failed to complete the transaction in a "good way"
1648                  * Force both transactions with CLR bit.
1649                  */
1650                 struct ecore_func_state_params func_params = { NULL };
1651
1652                 PMD_DRV_LOG(NOTICE, "Unexpected function state! "
1653                             "Forcing STARTED-->TX_STOPPED-->STARTED");
1654
1655                 func_params.f_obj = &sc->func_obj;
1656                 bnx2x_set_bit(RAMROD_DRV_CLR_ONLY, &func_params.ramrod_flags);
1657
1658                 /* STARTED-->TX_STOPPED */
1659                 func_params.cmd = ECORE_F_CMD_TX_STOP;
1660                 ecore_func_state_change(sc, &func_params);
1661
1662                 /* TX_STOPPED-->STARTED */
1663                 func_params.cmd = ECORE_F_CMD_TX_START;
1664                 return ecore_func_state_change(sc, &func_params);
1665         }
1666
1667         return 0;
1668 }
1669
1670 static int bnx2x_stop_queue(struct bnx2x_softc *sc, int index)
1671 {
1672         struct bnx2x_fastpath *fp = &sc->fp[index];
1673         struct ecore_queue_state_params q_params = { NULL };
1674         int rc;
1675
1676         PMD_DRV_LOG(DEBUG, "stopping queue %d cid %d", index, fp->index);
1677
1678         q_params.q_obj = &sc->sp_objs[fp->index].q_obj;
1679         /* We want to wait for completion in this context */
1680         bnx2x_set_bit(RAMROD_COMP_WAIT, &q_params.ramrod_flags);
1681
1682         /* Stop the primary connection: */
1683
1684         /* ...halt the connection */
1685         q_params.cmd = ECORE_Q_CMD_HALT;
1686         rc = ecore_queue_state_change(sc, &q_params);
1687         if (rc) {
1688                 return rc;
1689         }
1690
1691         /* ...terminate the connection */
1692         q_params.cmd = ECORE_Q_CMD_TERMINATE;
1693         memset(&q_params.params.terminate, 0,
1694                sizeof(q_params.params.terminate));
1695         q_params.params.terminate.cid_index = FIRST_TX_COS_INDEX;
1696         rc = ecore_queue_state_change(sc, &q_params);
1697         if (rc) {
1698                 return rc;
1699         }
1700
1701         /* ...delete cfc entry */
1702         q_params.cmd = ECORE_Q_CMD_CFC_DEL;
1703         memset(&q_params.params.cfc_del, 0, sizeof(q_params.params.cfc_del));
1704         q_params.params.cfc_del.cid_index = FIRST_TX_COS_INDEX;
1705         return ecore_queue_state_change(sc, &q_params);
1706 }
1707
1708 /* wait for the outstanding SP commands */
1709 static uint8_t bnx2x_wait_sp_comp(struct bnx2x_softc *sc, unsigned long mask)
1710 {
1711         unsigned long tmp;
1712         int tout = 5000;        /* wait for 5 secs tops */
1713
1714         while (tout--) {
1715                 mb();
1716                 if (!(atomic_load_acq_long(&sc->sp_state) & mask)) {
1717                         return TRUE;
1718                 }
1719
1720                 DELAY(1000);
1721         }
1722
1723         mb();
1724
1725         tmp = atomic_load_acq_long(&sc->sp_state);
1726         if (tmp & mask) {
1727                 PMD_DRV_LOG(INFO, "Filtering completion timed out: "
1728                             "sp_state 0x%lx, mask 0x%lx", tmp, mask);
1729                 return FALSE;
1730         }
1731
1732         return FALSE;
1733 }
1734
1735 static int bnx2x_func_stop(struct bnx2x_softc *sc)
1736 {
1737         struct ecore_func_state_params func_params = { NULL };
1738         int rc;
1739
1740         /* prepare parameters for function state transitions */
1741         bnx2x_set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags);
1742         func_params.f_obj = &sc->func_obj;
1743         func_params.cmd = ECORE_F_CMD_STOP;
1744
1745         /*
1746          * Try to stop the function the 'good way'. If it fails (in case
1747          * of a parity error during bnx2x_chip_cleanup()) and we are
1748          * not in a debug mode, perform a state transaction in order to
1749          * enable further HW_RESET transaction.
1750          */
1751         rc = ecore_func_state_change(sc, &func_params);
1752         if (rc) {
1753                 PMD_DRV_LOG(NOTICE, "FUNC_STOP ramrod failed. "
1754                             "Running a dry transaction");
1755                 bnx2x_set_bit(RAMROD_DRV_CLR_ONLY, &func_params.ramrod_flags);
1756                 return ecore_func_state_change(sc, &func_params);
1757         }
1758
1759         return 0;
1760 }
1761
1762 static int bnx2x_reset_hw(struct bnx2x_softc *sc, uint32_t load_code)
1763 {
1764         struct ecore_func_state_params func_params = { NULL };
1765
1766         /* Prepare parameters for function state transitions */
1767         bnx2x_set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags);
1768
1769         func_params.f_obj = &sc->func_obj;
1770         func_params.cmd = ECORE_F_CMD_HW_RESET;
1771
1772         func_params.params.hw_init.load_phase = load_code;
1773
1774         return ecore_func_state_change(sc, &func_params);
1775 }
1776
1777 static void bnx2x_int_disable_sync(struct bnx2x_softc *sc, int disable_hw)
1778 {
1779         if (disable_hw) {
1780                 /* prevent the HW from sending interrupts */
1781                 bnx2x_int_disable(sc);
1782         }
1783 }
1784
1785 static void
1786 bnx2x_chip_cleanup(struct bnx2x_softc *sc, uint32_t unload_mode, uint8_t keep_link)
1787 {
1788         int port = SC_PORT(sc);
1789         struct ecore_mcast_ramrod_params rparam = { NULL };
1790         uint32_t reset_code;
1791         int i, rc = 0;
1792
1793         bnx2x_drain_tx_queues(sc);
1794
1795         /* give HW time to discard old tx messages */
1796         DELAY(1000);
1797
1798         /* Clean all ETH MACs */
1799         rc = bnx2x_del_all_macs(sc, &sc->sp_objs[0].mac_obj, ECORE_ETH_MAC,
1800                               FALSE);
1801         if (rc < 0) {
1802                 PMD_DRV_LOG(NOTICE, "Failed to delete all ETH MACs (%d)", rc);
1803         }
1804
1805         /* Clean up UC list  */
1806         rc = bnx2x_del_all_macs(sc, &sc->sp_objs[0].mac_obj, ECORE_UC_LIST_MAC,
1807                               TRUE);
1808         if (rc < 0) {
1809                 PMD_DRV_LOG(NOTICE, "Failed to delete UC MACs list (%d)", rc);
1810         }
1811
1812         /* Disable LLH */
1813         REG_WR(sc, NIG_REG_LLH0_FUNC_EN + port * 8, 0);
1814
1815         /* Set "drop all" to stop Rx */
1816
1817         /*
1818          * We need to take the if_maddr_lock() here in order to prevent
1819          * a race between the completion code and this code.
1820          */
1821
1822         if (bnx2x_test_bit(ECORE_FILTER_RX_MODE_PENDING, &sc->sp_state)) {
1823                 bnx2x_set_bit(ECORE_FILTER_RX_MODE_SCHED, &sc->sp_state);
1824         } else {
1825                 bnx2x_set_storm_rx_mode(sc);
1826         }
1827
1828         /* Clean up multicast configuration */
1829         rparam.mcast_obj = &sc->mcast_obj;
1830         rc = ecore_config_mcast(sc, &rparam, ECORE_MCAST_CMD_DEL);
1831         if (rc < 0) {
1832                 PMD_DRV_LOG(NOTICE,
1833                             "Failed to send DEL MCAST command (%d)", rc);
1834         }
1835
1836         /*
1837          * Send the UNLOAD_REQUEST to the MCP. This will return if
1838          * this function should perform FUNCTION, PORT, or COMMON HW
1839          * reset.
1840          */
1841         reset_code = bnx2x_send_unload_req(sc, unload_mode);
1842
1843         /*
1844          * (assumption: No Attention from MCP at this stage)
1845          * PMF probably in the middle of TX disable/enable transaction
1846          */
1847         rc = bnx2x_func_wait_started(sc);
1848         if (rc) {
1849                 PMD_DRV_LOG(NOTICE, "bnx2x_func_wait_started failed");
1850         }
1851
1852         /*
1853          * Close multi and leading connections
1854          * Completions for ramrods are collected in a synchronous way
1855          */
1856         for (i = 0; i < sc->num_queues; i++) {
1857                 if (bnx2x_stop_queue(sc, i)) {
1858                         goto unload_error;
1859                 }
1860         }
1861
1862         /*
1863          * If SP settings didn't get completed so far - something
1864          * very wrong has happen.
1865          */
1866         if (!bnx2x_wait_sp_comp(sc, ~0x0UL)) {
1867                 PMD_DRV_LOG(NOTICE, "Common slow path ramrods got stuck!");
1868         }
1869
1870 unload_error:
1871
1872         rc = bnx2x_func_stop(sc);
1873         if (rc) {
1874                 PMD_DRV_LOG(NOTICE, "Function stop failed!");
1875         }
1876
1877         /* disable HW interrupts */
1878         bnx2x_int_disable_sync(sc, TRUE);
1879
1880         /* Reset the chip */
1881         rc = bnx2x_reset_hw(sc, reset_code);
1882         if (rc) {
1883                 PMD_DRV_LOG(NOTICE, "Hardware reset failed");
1884         }
1885
1886         /* Report UNLOAD_DONE to MCP */
1887         bnx2x_send_unload_done(sc, keep_link);
1888 }
1889
1890 static void bnx2x_disable_close_the_gate(struct bnx2x_softc *sc)
1891 {
1892         uint32_t val;
1893
1894         PMD_DRV_LOG(DEBUG, "Disabling 'close the gates'");
1895
1896         val = REG_RD(sc, MISC_REG_AEU_GENERAL_MASK);
1897         val &= ~(MISC_AEU_GENERAL_MASK_REG_AEU_PXP_CLOSE_MASK |
1898                  MISC_AEU_GENERAL_MASK_REG_AEU_NIG_CLOSE_MASK);
1899         REG_WR(sc, MISC_REG_AEU_GENERAL_MASK, val);
1900 }
1901
1902 /*
1903  * Cleans the object that have internal lists without sending
1904  * ramrods. Should be run when interrutps are disabled.
1905  */
1906 static void bnx2x_squeeze_objects(struct bnx2x_softc *sc)
1907 {
1908         unsigned long ramrod_flags = 0, vlan_mac_flags = 0;
1909         struct ecore_mcast_ramrod_params rparam = { NULL };
1910         struct ecore_vlan_mac_obj *mac_obj = &sc->sp_objs->mac_obj;
1911         int rc;
1912
1913         /* Cleanup MACs' object first... */
1914
1915         /* Wait for completion of requested */
1916         bnx2x_set_bit(RAMROD_COMP_WAIT, &ramrod_flags);
1917         /* Perform a dry cleanup */
1918         bnx2x_set_bit(RAMROD_DRV_CLR_ONLY, &ramrod_flags);
1919
1920         /* Clean ETH primary MAC */
1921         bnx2x_set_bit(ECORE_ETH_MAC, &vlan_mac_flags);
1922         rc = mac_obj->delete_all(sc, &sc->sp_objs->mac_obj, &vlan_mac_flags,
1923                                  &ramrod_flags);
1924         if (rc != 0) {
1925                 PMD_DRV_LOG(NOTICE, "Failed to clean ETH MACs (%d)", rc);
1926         }
1927
1928         /* Cleanup UC list */
1929         vlan_mac_flags = 0;
1930         bnx2x_set_bit(ECORE_UC_LIST_MAC, &vlan_mac_flags);
1931         rc = mac_obj->delete_all(sc, mac_obj, &vlan_mac_flags, &ramrod_flags);
1932         if (rc != 0) {
1933                 PMD_DRV_LOG(NOTICE, "Failed to clean UC list MACs (%d)", rc);
1934         }
1935
1936         /* Now clean mcast object... */
1937
1938         rparam.mcast_obj = &sc->mcast_obj;
1939         bnx2x_set_bit(RAMROD_DRV_CLR_ONLY, &rparam.ramrod_flags);
1940
1941         /* Add a DEL command... */
1942         rc = ecore_config_mcast(sc, &rparam, ECORE_MCAST_CMD_DEL);
1943         if (rc < 0) {
1944                 PMD_DRV_LOG(NOTICE,
1945                             "Failed to send DEL MCAST command (%d)", rc);
1946         }
1947
1948         /* now wait until all pending commands are cleared */
1949
1950         rc = ecore_config_mcast(sc, &rparam, ECORE_MCAST_CMD_CONT);
1951         while (rc != 0) {
1952                 if (rc < 0) {
1953                         PMD_DRV_LOG(NOTICE,
1954                                     "Failed to clean MCAST object (%d)", rc);
1955                         return;
1956                 }
1957
1958                 rc = ecore_config_mcast(sc, &rparam, ECORE_MCAST_CMD_CONT);
1959         }
1960 }
1961
1962 /* stop the controller */
1963 __rte_noinline
1964 int
1965 bnx2x_nic_unload(struct bnx2x_softc *sc, uint32_t unload_mode, uint8_t keep_link)
1966 {
1967         uint8_t global = FALSE;
1968         uint32_t val;
1969
1970         PMD_DRV_LOG(DEBUG, "Starting NIC unload...");
1971
1972         /* stop the periodic callout */
1973         bnx2x_periodic_stop(sc);
1974
1975         /* mark driver as unloaded in shmem2 */
1976         if (IS_PF(sc) && SHMEM2_HAS(sc, drv_capabilities_flag)) {
1977                 val = SHMEM2_RD(sc, drv_capabilities_flag[SC_FW_MB_IDX(sc)]);
1978                 SHMEM2_WR(sc, drv_capabilities_flag[SC_FW_MB_IDX(sc)],
1979                           val & ~DRV_FLAGS_CAPABILITIES_LOADED_L2);
1980         }
1981
1982         if (IS_PF(sc) && sc->recovery_state != BNX2X_RECOVERY_DONE &&
1983             (sc->state == BNX2X_STATE_CLOSED || sc->state == BNX2X_STATE_ERROR)) {
1984                 /*
1985                  * We can get here if the driver has been unloaded
1986                  * during parity error recovery and is either waiting for a
1987                  * leader to complete or for other functions to unload and
1988                  * then ifconfig down has been issued. In this case we want to
1989                  * unload and let other functions to complete a recovery
1990                  * process.
1991                  */
1992                 sc->recovery_state = BNX2X_RECOVERY_DONE;
1993                 sc->is_leader = 0;
1994                 bnx2x_release_leader_lock(sc);
1995                 mb();
1996
1997                 PMD_DRV_LOG(NOTICE, "Can't unload in closed or error state");
1998                 return -1;
1999         }
2000
2001         /*
2002          * Nothing to do during unload if previous bnx2x_nic_load()
2003          * did not completed successfully - all resourses are released.
2004          */
2005         if ((sc->state == BNX2X_STATE_CLOSED) || (sc->state == BNX2X_STATE_ERROR)) {
2006                 return 0;
2007         }
2008
2009         sc->state = BNX2X_STATE_CLOSING_WAITING_HALT;
2010         mb();
2011
2012         sc->rx_mode = BNX2X_RX_MODE_NONE;
2013         bnx2x_set_rx_mode(sc);
2014         mb();
2015
2016         if (IS_PF(sc)) {
2017                 /* set ALWAYS_ALIVE bit in shmem */
2018                 sc->fw_drv_pulse_wr_seq |= DRV_PULSE_ALWAYS_ALIVE;
2019
2020                 bnx2x_drv_pulse(sc);
2021
2022                 bnx2x_stats_handle(sc, STATS_EVENT_STOP);
2023                 bnx2x_save_statistics(sc);
2024         }
2025
2026         /* wait till consumers catch up with producers in all queues */
2027         bnx2x_drain_tx_queues(sc);
2028
2029         /* if VF indicate to PF this function is going down (PF will delete sp
2030          * elements and clear initializations
2031          */
2032         if (IS_VF(sc)) {
2033                 bnx2x_vf_unload(sc);
2034         } else if (unload_mode != UNLOAD_RECOVERY) {
2035                 /* if this is a normal/close unload need to clean up chip */
2036                 bnx2x_chip_cleanup(sc, unload_mode, keep_link);
2037         } else {
2038                 /* Send the UNLOAD_REQUEST to the MCP */
2039                 bnx2x_send_unload_req(sc, unload_mode);
2040
2041                 /*
2042                  * Prevent transactions to host from the functions on the
2043                  * engine that doesn't reset global blocks in case of global
2044                  * attention once gloabl blocks are reset and gates are opened
2045                  * (the engine which leader will perform the recovery
2046                  * last).
2047                  */
2048                 if (!CHIP_IS_E1x(sc)) {
2049                         bnx2x_pf_disable(sc);
2050                 }
2051
2052                 /* disable HW interrupts */
2053                 bnx2x_int_disable_sync(sc, TRUE);
2054
2055                 /* Report UNLOAD_DONE to MCP */
2056                 bnx2x_send_unload_done(sc, FALSE);
2057         }
2058
2059         /*
2060          * At this stage no more interrupts will arrive so we may safely clean
2061          * the queue'able objects here in case they failed to get cleaned so far.
2062          */
2063         if (IS_PF(sc)) {
2064                 bnx2x_squeeze_objects(sc);
2065         }
2066
2067         /* There should be no more pending SP commands at this stage */
2068         sc->sp_state = 0;
2069
2070         sc->port.pmf = 0;
2071
2072         if (IS_PF(sc)) {
2073                 bnx2x_free_mem(sc);
2074         }
2075
2076         bnx2x_free_fw_stats_mem(sc);
2077
2078         sc->state = BNX2X_STATE_CLOSED;
2079
2080         /*
2081          * Check if there are pending parity attentions. If there are - set
2082          * RECOVERY_IN_PROGRESS.
2083          */
2084         if (IS_PF(sc) && bnx2x_chk_parity_attn(sc, &global, FALSE)) {
2085                 bnx2x_set_reset_in_progress(sc);
2086
2087                 /* Set RESET_IS_GLOBAL if needed */
2088                 if (global) {
2089                         bnx2x_set_reset_global(sc);
2090                 }
2091         }
2092
2093         /*
2094          * The last driver must disable a "close the gate" if there is no
2095          * parity attention or "process kill" pending.
2096          */
2097         if (IS_PF(sc) && !bnx2x_clear_pf_load(sc) &&
2098             bnx2x_reset_is_done(sc, SC_PATH(sc))) {
2099                 bnx2x_disable_close_the_gate(sc);
2100         }
2101
2102         PMD_DRV_LOG(DEBUG, "Ended NIC unload");
2103
2104         return 0;
2105 }
2106
2107 /*
2108  * Encapsulte an mbuf cluster into the tx bd chain and makes the memory
2109  * visible to the controller.
2110  *
2111  * If an mbuf is submitted to this routine and cannot be given to the
2112  * controller (e.g. it has too many fragments) then the function may free
2113  * the mbuf and return to the caller.
2114  *
2115  * Returns:
2116  *     int: Number of TX BDs used for the mbuf
2117  *
2118  *   Note the side effect that an mbuf may be freed if it causes a problem.
2119  */
2120 int bnx2x_tx_encap(struct bnx2x_tx_queue *txq, struct rte_mbuf *m0)
2121 {
2122         struct eth_tx_start_bd *tx_start_bd;
2123         uint16_t bd_prod, pkt_prod;
2124         struct bnx2x_softc *sc;
2125         uint32_t nbds = 0;
2126
2127         sc = txq->sc;
2128         bd_prod = txq->tx_bd_tail;
2129         pkt_prod = txq->tx_pkt_tail;
2130
2131         txq->sw_ring[TX_BD(pkt_prod, txq)] = m0;
2132
2133         tx_start_bd = &txq->tx_ring[TX_BD(bd_prod, txq)].start_bd;
2134
2135         tx_start_bd->addr =
2136             rte_cpu_to_le_64(rte_mbuf_data_iova(m0));
2137         tx_start_bd->nbytes = rte_cpu_to_le_16(m0->data_len);
2138         tx_start_bd->bd_flags.as_bitfield = ETH_TX_BD_FLAGS_START_BD;
2139         tx_start_bd->general_data =
2140             (1 << ETH_TX_START_BD_HDR_NBDS_SHIFT);
2141
2142         tx_start_bd->nbd = rte_cpu_to_le_16(2);
2143
2144         if (m0->ol_flags & PKT_TX_VLAN_PKT) {
2145                 tx_start_bd->vlan_or_ethertype =
2146                     rte_cpu_to_le_16(m0->vlan_tci);
2147                 tx_start_bd->bd_flags.as_bitfield |=
2148                     (X_ETH_OUTBAND_VLAN <<
2149                      ETH_TX_BD_FLAGS_VLAN_MODE_SHIFT);
2150         } else {
2151                 if (IS_PF(sc))
2152                         tx_start_bd->vlan_or_ethertype =
2153                             rte_cpu_to_le_16(pkt_prod);
2154                 else {
2155                         struct ether_hdr *eh =
2156                             rte_pktmbuf_mtod(m0, struct ether_hdr *);
2157
2158                         tx_start_bd->vlan_or_ethertype =
2159                             rte_cpu_to_le_16(rte_be_to_cpu_16(eh->ether_type));
2160                 }
2161         }
2162
2163         bd_prod = NEXT_TX_BD(bd_prod);
2164         if (IS_VF(sc)) {
2165                 struct eth_tx_parse_bd_e2 *tx_parse_bd;
2166                 const struct ether_hdr *eh =
2167                     rte_pktmbuf_mtod(m0, struct ether_hdr *);
2168                 uint8_t mac_type = UNICAST_ADDRESS;
2169
2170                 tx_parse_bd =
2171                     &txq->tx_ring[TX_BD(bd_prod, txq)].parse_bd_e2;
2172                 if (is_multicast_ether_addr(&eh->d_addr)) {
2173                         if (is_broadcast_ether_addr(&eh->d_addr))
2174                                 mac_type = BROADCAST_ADDRESS;
2175                         else
2176                                 mac_type = MULTICAST_ADDRESS;
2177                 }
2178                 tx_parse_bd->parsing_data =
2179                     (mac_type << ETH_TX_PARSE_BD_E2_ETH_ADDR_TYPE_SHIFT);
2180
2181                 rte_memcpy(&tx_parse_bd->data.mac_addr.dst_hi,
2182                            &eh->d_addr.addr_bytes[0], 2);
2183                 rte_memcpy(&tx_parse_bd->data.mac_addr.dst_mid,
2184                            &eh->d_addr.addr_bytes[2], 2);
2185                 rte_memcpy(&tx_parse_bd->data.mac_addr.dst_lo,
2186                            &eh->d_addr.addr_bytes[4], 2);
2187                 rte_memcpy(&tx_parse_bd->data.mac_addr.src_hi,
2188                            &eh->s_addr.addr_bytes[0], 2);
2189                 rte_memcpy(&tx_parse_bd->data.mac_addr.src_mid,
2190                            &eh->s_addr.addr_bytes[2], 2);
2191                 rte_memcpy(&tx_parse_bd->data.mac_addr.src_lo,
2192                            &eh->s_addr.addr_bytes[4], 2);
2193
2194                 tx_parse_bd->data.mac_addr.dst_hi =
2195                     rte_cpu_to_be_16(tx_parse_bd->data.mac_addr.dst_hi);
2196                 tx_parse_bd->data.mac_addr.dst_mid =
2197                     rte_cpu_to_be_16(tx_parse_bd->data.
2198                                      mac_addr.dst_mid);
2199                 tx_parse_bd->data.mac_addr.dst_lo =
2200                     rte_cpu_to_be_16(tx_parse_bd->data.mac_addr.dst_lo);
2201                 tx_parse_bd->data.mac_addr.src_hi =
2202                     rte_cpu_to_be_16(tx_parse_bd->data.mac_addr.src_hi);
2203                 tx_parse_bd->data.mac_addr.src_mid =
2204                     rte_cpu_to_be_16(tx_parse_bd->data.
2205                                      mac_addr.src_mid);
2206                 tx_parse_bd->data.mac_addr.src_lo =
2207                     rte_cpu_to_be_16(tx_parse_bd->data.mac_addr.src_lo);
2208
2209                 PMD_TX_LOG(DEBUG,
2210                            "PBD dst %x %x %x src %x %x %x p_data %x",
2211                            tx_parse_bd->data.mac_addr.dst_hi,
2212                            tx_parse_bd->data.mac_addr.dst_mid,
2213                            tx_parse_bd->data.mac_addr.dst_lo,
2214                            tx_parse_bd->data.mac_addr.src_hi,
2215                            tx_parse_bd->data.mac_addr.src_mid,
2216                            tx_parse_bd->data.mac_addr.src_lo,
2217                            tx_parse_bd->parsing_data);
2218         }
2219
2220         PMD_TX_LOG(DEBUG,
2221                    "start bd: nbytes %d flags %x vlan %x",
2222                    tx_start_bd->nbytes,
2223                    tx_start_bd->bd_flags.as_bitfield,
2224                    tx_start_bd->vlan_or_ethertype);
2225
2226         bd_prod = NEXT_TX_BD(bd_prod);
2227         pkt_prod++;
2228
2229         if (TX_IDX(bd_prod) < 2)
2230                 nbds++;
2231
2232         txq->nb_tx_avail -= 2;
2233         txq->tx_bd_tail = bd_prod;
2234         txq->tx_pkt_tail = pkt_prod;
2235
2236         return nbds + 2;
2237 }
2238
2239 static uint16_t bnx2x_cid_ilt_lines(struct bnx2x_softc *sc)
2240 {
2241         return L2_ILT_LINES(sc);
2242 }
2243
2244 static void bnx2x_ilt_set_info(struct bnx2x_softc *sc)
2245 {
2246         struct ilt_client_info *ilt_client;
2247         struct ecore_ilt *ilt = sc->ilt;
2248         uint16_t line = 0;
2249
2250         PMD_INIT_FUNC_TRACE();
2251
2252         ilt->start_line = FUNC_ILT_BASE(SC_FUNC(sc));
2253
2254         /* CDU */
2255         ilt_client = &ilt->clients[ILT_CLIENT_CDU];
2256         ilt_client->client_num = ILT_CLIENT_CDU;
2257         ilt_client->page_size = CDU_ILT_PAGE_SZ;
2258         ilt_client->flags = ILT_CLIENT_SKIP_MEM;
2259         ilt_client->start = line;
2260         line += bnx2x_cid_ilt_lines(sc);
2261
2262         if (CNIC_SUPPORT(sc)) {
2263                 line += CNIC_ILT_LINES;
2264         }
2265
2266         ilt_client->end = (line - 1);
2267
2268         /* QM */
2269         if (QM_INIT(sc->qm_cid_count)) {
2270                 ilt_client = &ilt->clients[ILT_CLIENT_QM];
2271                 ilt_client->client_num = ILT_CLIENT_QM;
2272                 ilt_client->page_size = QM_ILT_PAGE_SZ;
2273                 ilt_client->flags = 0;
2274                 ilt_client->start = line;
2275
2276                 /* 4 bytes for each cid */
2277                 line += DIV_ROUND_UP(sc->qm_cid_count * QM_QUEUES_PER_FUNC * 4,
2278                                      QM_ILT_PAGE_SZ);
2279
2280                 ilt_client->end = (line - 1);
2281         }
2282
2283         if (CNIC_SUPPORT(sc)) {
2284                 /* SRC */
2285                 ilt_client = &ilt->clients[ILT_CLIENT_SRC];
2286                 ilt_client->client_num = ILT_CLIENT_SRC;
2287                 ilt_client->page_size = SRC_ILT_PAGE_SZ;
2288                 ilt_client->flags = 0;
2289                 ilt_client->start = line;
2290                 line += SRC_ILT_LINES;
2291                 ilt_client->end = (line - 1);
2292
2293                 /* TM */
2294                 ilt_client = &ilt->clients[ILT_CLIENT_TM];
2295                 ilt_client->client_num = ILT_CLIENT_TM;
2296                 ilt_client->page_size = TM_ILT_PAGE_SZ;
2297                 ilt_client->flags = 0;
2298                 ilt_client->start = line;
2299                 line += TM_ILT_LINES;
2300                 ilt_client->end = (line - 1);
2301         }
2302
2303         assert((line <= ILT_MAX_LINES));
2304 }
2305
2306 static void bnx2x_set_fp_rx_buf_size(struct bnx2x_softc *sc)
2307 {
2308         int i;
2309
2310         for (i = 0; i < sc->num_queues; i++) {
2311                 /* get the Rx buffer size for RX frames */
2312                 sc->fp[i].rx_buf_size =
2313                     (IP_HEADER_ALIGNMENT_PADDING + ETH_OVERHEAD + sc->mtu);
2314         }
2315 }
2316
2317 int bnx2x_alloc_ilt_mem(struct bnx2x_softc *sc)
2318 {
2319
2320         sc->ilt = rte_malloc("", sizeof(struct ecore_ilt), RTE_CACHE_LINE_SIZE);
2321
2322         return sc->ilt == NULL;
2323 }
2324
2325 static int bnx2x_alloc_ilt_lines_mem(struct bnx2x_softc *sc)
2326 {
2327         sc->ilt->lines = rte_calloc("",
2328                                     sizeof(struct ilt_line), ILT_MAX_LINES,
2329                                     RTE_CACHE_LINE_SIZE);
2330         return sc->ilt->lines == NULL;
2331 }
2332
2333 void bnx2x_free_ilt_mem(struct bnx2x_softc *sc)
2334 {
2335         rte_free(sc->ilt);
2336         sc->ilt = NULL;
2337 }
2338
2339 static void bnx2x_free_ilt_lines_mem(struct bnx2x_softc *sc)
2340 {
2341         if (sc->ilt->lines != NULL) {
2342                 rte_free(sc->ilt->lines);
2343                 sc->ilt->lines = NULL;
2344         }
2345 }
2346
2347 static void bnx2x_free_mem(struct bnx2x_softc *sc)
2348 {
2349         uint32_t i;
2350
2351         for (i = 0; i < L2_ILT_LINES(sc); i++) {
2352                 sc->context[i].vcxt = NULL;
2353                 sc->context[i].size = 0;
2354         }
2355
2356         ecore_ilt_mem_op(sc, ILT_MEMOP_FREE);
2357
2358         bnx2x_free_ilt_lines_mem(sc);
2359 }
2360
2361 static int bnx2x_alloc_mem(struct bnx2x_softc *sc)
2362 {
2363         int context_size;
2364         int allocated;
2365         int i;
2366         char cdu_name[RTE_MEMZONE_NAMESIZE];
2367
2368         /*
2369          * Allocate memory for CDU context:
2370          * This memory is allocated separately and not in the generic ILT
2371          * functions because CDU differs in few aspects:
2372          * 1. There can be multiple entities allocating memory for context -
2373          * regular L2, CNIC, and SRIOV drivers. Each separately controls
2374          * its own ILT lines.
2375          * 2. Since CDU page-size is not a single 4KB page (which is the case
2376          * for the other ILT clients), to be efficient we want to support
2377          * allocation of sub-page-size in the last entry.
2378          * 3. Context pointers are used by the driver to pass to FW / update
2379          * the context (for the other ILT clients the pointers are used just to
2380          * free the memory during unload).
2381          */
2382         context_size = (sizeof(union cdu_context) * BNX2X_L2_CID_COUNT(sc));
2383         for (i = 0, allocated = 0; allocated < context_size; i++) {
2384                 sc->context[i].size = min(CDU_ILT_PAGE_SZ,
2385                                           (context_size - allocated));
2386
2387                 snprintf(cdu_name, sizeof(cdu_name), "cdu_%d", i);
2388                 if (bnx2x_dma_alloc(sc, sc->context[i].size,
2389                                   &sc->context[i].vcxt_dma,
2390                                   cdu_name, BNX2X_PAGE_SIZE) != 0) {
2391                         bnx2x_free_mem(sc);
2392                         return -1;
2393                 }
2394
2395                 sc->context[i].vcxt =
2396                     (union cdu_context *)sc->context[i].vcxt_dma.vaddr;
2397
2398                 allocated += sc->context[i].size;
2399         }
2400
2401         bnx2x_alloc_ilt_lines_mem(sc);
2402
2403         if (ecore_ilt_mem_op(sc, ILT_MEMOP_ALLOC)) {
2404                 PMD_DRV_LOG(NOTICE, "ecore_ilt_mem_op ILT_MEMOP_ALLOC failed");
2405                 bnx2x_free_mem(sc);
2406                 return -1;
2407         }
2408
2409         return 0;
2410 }
2411
2412 static void bnx2x_free_fw_stats_mem(struct bnx2x_softc *sc)
2413 {
2414         sc->fw_stats_num = 0;
2415
2416         sc->fw_stats_req_size = 0;
2417         sc->fw_stats_req = NULL;
2418         sc->fw_stats_req_mapping = 0;
2419
2420         sc->fw_stats_data_size = 0;
2421         sc->fw_stats_data = NULL;
2422         sc->fw_stats_data_mapping = 0;
2423 }
2424
2425 static int bnx2x_alloc_fw_stats_mem(struct bnx2x_softc *sc)
2426 {
2427         uint8_t num_queue_stats;
2428         int num_groups, vf_headroom = 0;
2429
2430         /* number of queues for statistics is number of eth queues */
2431         num_queue_stats = BNX2X_NUM_ETH_QUEUES(sc);
2432
2433         /*
2434          * Total number of FW statistics requests =
2435          *   1 for port stats + 1 for PF stats + num of queues
2436          */
2437         sc->fw_stats_num = (2 + num_queue_stats);
2438
2439         /*
2440          * Request is built from stats_query_header and an array of
2441          * stats_query_cmd_group each of which contains STATS_QUERY_CMD_COUNT
2442          * rules. The real number or requests is configured in the
2443          * stats_query_header.
2444          */
2445         num_groups = (sc->fw_stats_num + vf_headroom) / STATS_QUERY_CMD_COUNT;
2446         if ((sc->fw_stats_num + vf_headroom) % STATS_QUERY_CMD_COUNT)
2447                 num_groups++;
2448
2449         sc->fw_stats_req_size =
2450             (sizeof(struct stats_query_header) +
2451              (num_groups * sizeof(struct stats_query_cmd_group)));
2452
2453         /*
2454          * Data for statistics requests + stats_counter.
2455          * stats_counter holds per-STORM counters that are incremented when
2456          * STORM has finished with the current request. Memory for FCoE
2457          * offloaded statistics are counted anyway, even if they will not be sent.
2458          * VF stats are not accounted for here as the data of VF stats is stored
2459          * in memory allocated by the VF, not here.
2460          */
2461         sc->fw_stats_data_size =
2462             (sizeof(struct stats_counter) +
2463              sizeof(struct per_port_stats) + sizeof(struct per_pf_stats) +
2464              /* sizeof(struct fcoe_statistics_params) + */
2465              (sizeof(struct per_queue_stats) * num_queue_stats));
2466
2467         if (bnx2x_dma_alloc(sc, (sc->fw_stats_req_size + sc->fw_stats_data_size),
2468                           &sc->fw_stats_dma, "fw_stats",
2469                           RTE_CACHE_LINE_SIZE) != 0) {
2470                 bnx2x_free_fw_stats_mem(sc);
2471                 return -1;
2472         }
2473
2474         /* set up the shortcuts */
2475
2476         sc->fw_stats_req = (struct bnx2x_fw_stats_req *)sc->fw_stats_dma.vaddr;
2477         sc->fw_stats_req_mapping = sc->fw_stats_dma.paddr;
2478
2479         sc->fw_stats_data =
2480             (struct bnx2x_fw_stats_data *)((uint8_t *) sc->fw_stats_dma.vaddr +
2481                                          sc->fw_stats_req_size);
2482         sc->fw_stats_data_mapping = (sc->fw_stats_dma.paddr +
2483                                      sc->fw_stats_req_size);
2484
2485         return 0;
2486 }
2487
2488 /*
2489  * Bits map:
2490  * 0-7  - Engine0 load counter.
2491  * 8-15 - Engine1 load counter.
2492  * 16   - Engine0 RESET_IN_PROGRESS bit.
2493  * 17   - Engine1 RESET_IN_PROGRESS bit.
2494  * 18   - Engine0 ONE_IS_LOADED. Set when there is at least one active
2495  *        function on the engine
2496  * 19   - Engine1 ONE_IS_LOADED.
2497  * 20   - Chip reset flow bit. When set none-leader must wait for both engines
2498  *        leader to complete (check for both RESET_IN_PROGRESS bits and not
2499  *        for just the one belonging to its engine).
2500  */
2501 #define BNX2X_RECOVERY_GLOB_REG     MISC_REG_GENERIC_POR_1
2502 #define BNX2X_PATH0_LOAD_CNT_MASK   0x000000ff
2503 #define BNX2X_PATH0_LOAD_CNT_SHIFT  0
2504 #define BNX2X_PATH1_LOAD_CNT_MASK   0x0000ff00
2505 #define BNX2X_PATH1_LOAD_CNT_SHIFT  8
2506 #define BNX2X_PATH0_RST_IN_PROG_BIT 0x00010000
2507 #define BNX2X_PATH1_RST_IN_PROG_BIT 0x00020000
2508 #define BNX2X_GLOBAL_RESET_BIT      0x00040000
2509
2510 /* set the GLOBAL_RESET bit, should be run under rtnl lock */
2511 static void bnx2x_set_reset_global(struct bnx2x_softc *sc)
2512 {
2513         uint32_t val;
2514         bnx2x_acquire_hw_lock(sc, HW_LOCK_RESOURCE_RECOVERY_REG);
2515         val = REG_RD(sc, BNX2X_RECOVERY_GLOB_REG);
2516         REG_WR(sc, BNX2X_RECOVERY_GLOB_REG, val | BNX2X_GLOBAL_RESET_BIT);
2517         bnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_RECOVERY_REG);
2518 }
2519
2520 /* clear the GLOBAL_RESET bit, should be run under rtnl lock */
2521 static void bnx2x_clear_reset_global(struct bnx2x_softc *sc)
2522 {
2523         uint32_t val;
2524         bnx2x_acquire_hw_lock(sc, HW_LOCK_RESOURCE_RECOVERY_REG);
2525         val = REG_RD(sc, BNX2X_RECOVERY_GLOB_REG);
2526         REG_WR(sc, BNX2X_RECOVERY_GLOB_REG, val & (~BNX2X_GLOBAL_RESET_BIT));
2527         bnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_RECOVERY_REG);
2528 }
2529
2530 /* checks the GLOBAL_RESET bit, should be run under rtnl lock */
2531 static uint8_t bnx2x_reset_is_global(struct bnx2x_softc *sc)
2532 {
2533         return REG_RD(sc, BNX2X_RECOVERY_GLOB_REG) & BNX2X_GLOBAL_RESET_BIT;
2534 }
2535
2536 /* clear RESET_IN_PROGRESS bit for the engine, should be run under rtnl lock */
2537 static void bnx2x_set_reset_done(struct bnx2x_softc *sc)
2538 {
2539         uint32_t val;
2540         uint32_t bit = SC_PATH(sc) ? BNX2X_PATH1_RST_IN_PROG_BIT :
2541             BNX2X_PATH0_RST_IN_PROG_BIT;
2542
2543         bnx2x_acquire_hw_lock(sc, HW_LOCK_RESOURCE_RECOVERY_REG);
2544
2545         val = REG_RD(sc, BNX2X_RECOVERY_GLOB_REG);
2546         /* Clear the bit */
2547         val &= ~bit;
2548         REG_WR(sc, BNX2X_RECOVERY_GLOB_REG, val);
2549
2550         bnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_RECOVERY_REG);
2551 }
2552
2553 /* set RESET_IN_PROGRESS for the engine, should be run under rtnl lock */
2554 static void bnx2x_set_reset_in_progress(struct bnx2x_softc *sc)
2555 {
2556         uint32_t val;
2557         uint32_t bit = SC_PATH(sc) ? BNX2X_PATH1_RST_IN_PROG_BIT :
2558             BNX2X_PATH0_RST_IN_PROG_BIT;
2559
2560         bnx2x_acquire_hw_lock(sc, HW_LOCK_RESOURCE_RECOVERY_REG);
2561
2562         val = REG_RD(sc, BNX2X_RECOVERY_GLOB_REG);
2563         /* Set the bit */
2564         val |= bit;
2565         REG_WR(sc, BNX2X_RECOVERY_GLOB_REG, val);
2566
2567         bnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_RECOVERY_REG);
2568 }
2569
2570 /* check RESET_IN_PROGRESS bit for an engine, should be run under rtnl lock */
2571 static uint8_t bnx2x_reset_is_done(struct bnx2x_softc *sc, int engine)
2572 {
2573         uint32_t val = REG_RD(sc, BNX2X_RECOVERY_GLOB_REG);
2574         uint32_t bit = engine ? BNX2X_PATH1_RST_IN_PROG_BIT :
2575             BNX2X_PATH0_RST_IN_PROG_BIT;
2576
2577         /* return false if bit is set */
2578         return (val & bit) ? FALSE : TRUE;
2579 }
2580
2581 /* get the load status for an engine, should be run under rtnl lock */
2582 static uint8_t bnx2x_get_load_status(struct bnx2x_softc *sc, int engine)
2583 {
2584         uint32_t mask = engine ? BNX2X_PATH1_LOAD_CNT_MASK :
2585             BNX2X_PATH0_LOAD_CNT_MASK;
2586         uint32_t shift = engine ? BNX2X_PATH1_LOAD_CNT_SHIFT :
2587             BNX2X_PATH0_LOAD_CNT_SHIFT;
2588         uint32_t val = REG_RD(sc, BNX2X_RECOVERY_GLOB_REG);
2589
2590         val = ((val & mask) >> shift);
2591
2592         return val != 0;
2593 }
2594
2595 /* set pf load mark */
2596 static void bnx2x_set_pf_load(struct bnx2x_softc *sc)
2597 {
2598         uint32_t val;
2599         uint32_t val1;
2600         uint32_t mask = SC_PATH(sc) ? BNX2X_PATH1_LOAD_CNT_MASK :
2601             BNX2X_PATH0_LOAD_CNT_MASK;
2602         uint32_t shift = SC_PATH(sc) ? BNX2X_PATH1_LOAD_CNT_SHIFT :
2603             BNX2X_PATH0_LOAD_CNT_SHIFT;
2604
2605         bnx2x_acquire_hw_lock(sc, HW_LOCK_RESOURCE_RECOVERY_REG);
2606
2607         PMD_INIT_FUNC_TRACE();
2608
2609         val = REG_RD(sc, BNX2X_RECOVERY_GLOB_REG);
2610
2611         /* get the current counter value */
2612         val1 = ((val & mask) >> shift);
2613
2614         /* set bit of this PF */
2615         val1 |= (1 << SC_ABS_FUNC(sc));
2616
2617         /* clear the old value */
2618         val &= ~mask;
2619
2620         /* set the new one */
2621         val |= ((val1 << shift) & mask);
2622
2623         REG_WR(sc, BNX2X_RECOVERY_GLOB_REG, val);
2624
2625         bnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_RECOVERY_REG);
2626 }
2627
2628 /* clear pf load mark */
2629 static uint8_t bnx2x_clear_pf_load(struct bnx2x_softc *sc)
2630 {
2631         uint32_t val1, val;
2632         uint32_t mask = SC_PATH(sc) ? BNX2X_PATH1_LOAD_CNT_MASK :
2633             BNX2X_PATH0_LOAD_CNT_MASK;
2634         uint32_t shift = SC_PATH(sc) ? BNX2X_PATH1_LOAD_CNT_SHIFT :
2635             BNX2X_PATH0_LOAD_CNT_SHIFT;
2636
2637         bnx2x_acquire_hw_lock(sc, HW_LOCK_RESOURCE_RECOVERY_REG);
2638         val = REG_RD(sc, BNX2X_RECOVERY_GLOB_REG);
2639
2640         /* get the current counter value */
2641         val1 = (val & mask) >> shift;
2642
2643         /* clear bit of that PF */
2644         val1 &= ~(1 << SC_ABS_FUNC(sc));
2645
2646         /* clear the old value */
2647         val &= ~mask;
2648
2649         /* set the new one */
2650         val |= ((val1 << shift) & mask);
2651
2652         REG_WR(sc, BNX2X_RECOVERY_GLOB_REG, val);
2653         bnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_RECOVERY_REG);
2654         return val1 != 0;
2655 }
2656
2657 /* send load requrest to mcp and analyze response */
2658 static int bnx2x_nic_load_request(struct bnx2x_softc *sc, uint32_t * load_code)
2659 {
2660         PMD_INIT_FUNC_TRACE();
2661
2662         /* init fw_seq */
2663         sc->fw_seq =
2664             (SHMEM_RD(sc, func_mb[SC_FW_MB_IDX(sc)].drv_mb_header) &
2665              DRV_MSG_SEQ_NUMBER_MASK);
2666
2667         PMD_DRV_LOG(DEBUG, "initial fw_seq 0x%04x", sc->fw_seq);
2668
2669 #ifdef BNX2X_PULSE
2670         /* get the current FW pulse sequence */
2671         sc->fw_drv_pulse_wr_seq =
2672             (SHMEM_RD(sc, func_mb[SC_FW_MB_IDX(sc)].drv_pulse_mb) &
2673              DRV_PULSE_SEQ_MASK);
2674 #else
2675         /* set ALWAYS_ALIVE bit in shmem */
2676         sc->fw_drv_pulse_wr_seq |= DRV_PULSE_ALWAYS_ALIVE;
2677         bnx2x_drv_pulse(sc);
2678 #endif
2679
2680         /* load request */
2681         (*load_code) = bnx2x_fw_command(sc, DRV_MSG_CODE_LOAD_REQ,
2682                                       DRV_MSG_CODE_LOAD_REQ_WITH_LFA);
2683
2684         /* if the MCP fails to respond we must abort */
2685         if (!(*load_code)) {
2686                 PMD_DRV_LOG(NOTICE, "MCP response failure!");
2687                 return -1;
2688         }
2689
2690         /* if MCP refused then must abort */
2691         if ((*load_code) == FW_MSG_CODE_DRV_LOAD_REFUSED) {
2692                 PMD_DRV_LOG(NOTICE, "MCP refused load request");
2693                 return -1;
2694         }
2695
2696         return 0;
2697 }
2698
2699 /*
2700  * Check whether another PF has already loaded FW to chip. In virtualized
2701  * environments a pf from anoth VM may have already initialized the device
2702  * including loading FW.
2703  */
2704 static int bnx2x_nic_load_analyze_req(struct bnx2x_softc *sc, uint32_t load_code)
2705 {
2706         uint32_t my_fw, loaded_fw;
2707
2708         /* is another pf loaded on this engine? */
2709         if ((load_code != FW_MSG_CODE_DRV_LOAD_COMMON_CHIP) &&
2710             (load_code != FW_MSG_CODE_DRV_LOAD_COMMON)) {
2711                 /* build my FW version dword */
2712                 my_fw = (BNX2X_5710_FW_MAJOR_VERSION +
2713                          (BNX2X_5710_FW_MINOR_VERSION << 8) +
2714                          (BNX2X_5710_FW_REVISION_VERSION << 16) +
2715                          (BNX2X_5710_FW_ENGINEERING_VERSION << 24));
2716
2717                 /* read loaded FW from chip */
2718                 loaded_fw = REG_RD(sc, XSEM_REG_PRAM);
2719                 PMD_DRV_LOG(DEBUG, "loaded FW 0x%08x / my FW 0x%08x",
2720                             loaded_fw, my_fw);
2721
2722                 /* abort nic load if version mismatch */
2723                 if (my_fw != loaded_fw) {
2724                         PMD_DRV_LOG(NOTICE,
2725                                     "FW 0x%08x already loaded (mine is 0x%08x)",
2726                                     loaded_fw, my_fw);
2727                         return -1;
2728                 }
2729         }
2730
2731         return 0;
2732 }
2733
2734 /* mark PMF if applicable */
2735 static void bnx2x_nic_load_pmf(struct bnx2x_softc *sc, uint32_t load_code)
2736 {
2737         uint32_t ncsi_oem_data_addr;
2738
2739         PMD_INIT_FUNC_TRACE();
2740
2741         if ((load_code == FW_MSG_CODE_DRV_LOAD_COMMON) ||
2742             (load_code == FW_MSG_CODE_DRV_LOAD_COMMON_CHIP) ||
2743             (load_code == FW_MSG_CODE_DRV_LOAD_PORT)) {
2744                 /*
2745                  * Barrier here for ordering between the writing to sc->port.pmf here
2746                  * and reading it from the periodic task.
2747                  */
2748                 sc->port.pmf = 1;
2749                 mb();
2750         } else {
2751                 sc->port.pmf = 0;
2752         }
2753
2754         PMD_DRV_LOG(DEBUG, "pmf %d", sc->port.pmf);
2755
2756         if (load_code == FW_MSG_CODE_DRV_LOAD_COMMON_CHIP) {
2757                 if (SHMEM2_HAS(sc, ncsi_oem_data_addr)) {
2758                         ncsi_oem_data_addr = SHMEM2_RD(sc, ncsi_oem_data_addr);
2759                         if (ncsi_oem_data_addr) {
2760                                 REG_WR(sc,
2761                                        (ncsi_oem_data_addr +
2762                                         offsetof(struct glob_ncsi_oem_data,
2763                                                  driver_version)), 0);
2764                         }
2765                 }
2766         }
2767 }
2768
2769 static void bnx2x_read_mf_cfg(struct bnx2x_softc *sc)
2770 {
2771         int n = (CHIP_IS_MODE_4_PORT(sc) ? 2 : 1);
2772         int abs_func;
2773         int vn;
2774
2775         if (BNX2X_NOMCP(sc)) {
2776                 return;         /* what should be the default bvalue in this case */
2777         }
2778
2779         /*
2780          * The formula for computing the absolute function number is...
2781          * For 2 port configuration (4 functions per port):
2782          *   abs_func = 2 * vn + SC_PORT + SC_PATH
2783          * For 4 port configuration (2 functions per port):
2784          *   abs_func = 4 * vn + 2 * SC_PORT + SC_PATH
2785          */
2786         for (vn = VN_0; vn < SC_MAX_VN_NUM(sc); vn++) {
2787                 abs_func = (n * (2 * vn + SC_PORT(sc)) + SC_PATH(sc));
2788                 if (abs_func >= E1H_FUNC_MAX) {
2789                         break;
2790                 }
2791                 sc->devinfo.mf_info.mf_config[vn] =
2792                     MFCFG_RD(sc, func_mf_config[abs_func].config);
2793         }
2794
2795         if (sc->devinfo.mf_info.mf_config[SC_VN(sc)] &
2796             FUNC_MF_CFG_FUNC_DISABLED) {
2797                 PMD_DRV_LOG(DEBUG, "mf_cfg function disabled");
2798                 sc->flags |= BNX2X_MF_FUNC_DIS;
2799         } else {
2800                 PMD_DRV_LOG(DEBUG, "mf_cfg function enabled");
2801                 sc->flags &= ~BNX2X_MF_FUNC_DIS;
2802         }
2803 }
2804
2805 /* acquire split MCP access lock register */
2806 static int bnx2x_acquire_alr(struct bnx2x_softc *sc)
2807 {
2808         uint32_t j, val;
2809
2810         for (j = 0; j < 1000; j++) {
2811                 val = (1UL << 31);
2812                 REG_WR(sc, GRCBASE_MCP + 0x9c, val);
2813                 val = REG_RD(sc, GRCBASE_MCP + 0x9c);
2814                 if (val & (1L << 31))
2815                         break;
2816
2817                 DELAY(5000);
2818         }
2819
2820         if (!(val & (1L << 31))) {
2821                 PMD_DRV_LOG(NOTICE, "Cannot acquire MCP access lock register");
2822                 return -1;
2823         }
2824
2825         return 0;
2826 }
2827
2828 /* release split MCP access lock register */
2829 static void bnx2x_release_alr(struct bnx2x_softc *sc)
2830 {
2831         REG_WR(sc, GRCBASE_MCP + 0x9c, 0);
2832 }
2833
2834 static void bnx2x_fan_failure(struct bnx2x_softc *sc)
2835 {
2836         int port = SC_PORT(sc);
2837         uint32_t ext_phy_config;
2838
2839         /* mark the failure */
2840         ext_phy_config =
2841             SHMEM_RD(sc, dev_info.port_hw_config[port].external_phy_config);
2842
2843         ext_phy_config &= ~PORT_HW_CFG_XGXS_EXT_PHY_TYPE_MASK;
2844         ext_phy_config |= PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE;
2845         SHMEM_WR(sc, dev_info.port_hw_config[port].external_phy_config,
2846                  ext_phy_config);
2847
2848         /* log the failure */
2849         PMD_DRV_LOG(INFO,
2850                     "Fan Failure has caused the driver to shutdown "
2851                     "the card to prevent permanent damage. "
2852                     "Please contact OEM Support for assistance");
2853
2854         rte_panic("Schedule task to handle fan failure");
2855 }
2856
2857 /* this function is called upon a link interrupt */
2858 static void bnx2x_link_attn(struct bnx2x_softc *sc)
2859 {
2860         uint32_t pause_enabled = 0;
2861         struct host_port_stats *pstats;
2862         int cmng_fns;
2863
2864         /* Make sure that we are synced with the current statistics */
2865         bnx2x_stats_handle(sc, STATS_EVENT_STOP);
2866
2867         elink_link_update(&sc->link_params, &sc->link_vars);
2868
2869         if (sc->link_vars.link_up) {
2870
2871                 /* dropless flow control */
2872                 if (sc->dropless_fc) {
2873                         pause_enabled = 0;
2874
2875                         if (sc->link_vars.flow_ctrl & ELINK_FLOW_CTRL_TX) {
2876                                 pause_enabled = 1;
2877                         }
2878
2879                         REG_WR(sc,
2880                                (BAR_USTRORM_INTMEM +
2881                                 USTORM_ETH_PAUSE_ENABLED_OFFSET(SC_PORT(sc))),
2882                                pause_enabled);
2883                 }
2884
2885                 if (sc->link_vars.mac_type != ELINK_MAC_TYPE_EMAC) {
2886                         pstats = BNX2X_SP(sc, port_stats);
2887                         /* reset old mac stats */
2888                         memset(&(pstats->mac_stx[0]), 0,
2889                                sizeof(struct mac_stx));
2890                 }
2891
2892                 if (sc->state == BNX2X_STATE_OPEN) {
2893                         bnx2x_stats_handle(sc, STATS_EVENT_LINK_UP);
2894                 }
2895         }
2896
2897         if (sc->link_vars.link_up && sc->link_vars.line_speed) {
2898                 cmng_fns = bnx2x_get_cmng_fns_mode(sc);
2899
2900                 if (cmng_fns != CMNG_FNS_NONE) {
2901                         bnx2x_cmng_fns_init(sc, FALSE, cmng_fns);
2902                         storm_memset_cmng(sc, &sc->cmng, SC_PORT(sc));
2903                 }
2904         }
2905
2906         bnx2x_link_report(sc);
2907
2908         if (IS_MF(sc)) {
2909                 bnx2x_link_sync_notify(sc);
2910         }
2911 }
2912
2913 static void bnx2x_attn_int_asserted(struct bnx2x_softc *sc, uint32_t asserted)
2914 {
2915         int port = SC_PORT(sc);
2916         uint32_t aeu_addr = port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 :
2917             MISC_REG_AEU_MASK_ATTN_FUNC_0;
2918         uint32_t nig_int_mask_addr = port ? NIG_REG_MASK_INTERRUPT_PORT1 :
2919             NIG_REG_MASK_INTERRUPT_PORT0;
2920         uint32_t aeu_mask;
2921         uint32_t nig_mask = 0;
2922         uint32_t reg_addr;
2923         uint32_t igu_acked;
2924         uint32_t cnt;
2925
2926         if (sc->attn_state & asserted) {
2927                 PMD_DRV_LOG(ERR, "IGU ERROR attn=0x%08x", asserted);
2928         }
2929
2930         bnx2x_acquire_hw_lock(sc, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
2931
2932         aeu_mask = REG_RD(sc, aeu_addr);
2933
2934         aeu_mask &= ~(asserted & 0x3ff);
2935
2936         REG_WR(sc, aeu_addr, aeu_mask);
2937
2938         bnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
2939
2940         sc->attn_state |= asserted;
2941
2942         if (asserted & ATTN_HARD_WIRED_MASK) {
2943                 if (asserted & ATTN_NIG_FOR_FUNC) {
2944
2945                         /* save nig interrupt mask */
2946                         nig_mask = REG_RD(sc, nig_int_mask_addr);
2947
2948                         /* If nig_mask is not set, no need to call the update function */
2949                         if (nig_mask) {
2950                                 REG_WR(sc, nig_int_mask_addr, 0);
2951
2952                                 bnx2x_link_attn(sc);
2953                         }
2954
2955                         /* handle unicore attn? */
2956                 }
2957
2958                 if (asserted & ATTN_SW_TIMER_4_FUNC) {
2959                         PMD_DRV_LOG(DEBUG, "ATTN_SW_TIMER_4_FUNC!");
2960                 }
2961
2962                 if (asserted & GPIO_2_FUNC) {
2963                         PMD_DRV_LOG(DEBUG, "GPIO_2_FUNC!");
2964                 }
2965
2966                 if (asserted & GPIO_3_FUNC) {
2967                         PMD_DRV_LOG(DEBUG, "GPIO_3_FUNC!");
2968                 }
2969
2970                 if (asserted & GPIO_4_FUNC) {
2971                         PMD_DRV_LOG(DEBUG, "GPIO_4_FUNC!");
2972                 }
2973
2974                 if (port == 0) {
2975                         if (asserted & ATTN_GENERAL_ATTN_1) {
2976                                 PMD_DRV_LOG(DEBUG, "ATTN_GENERAL_ATTN_1!");
2977                                 REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_1, 0x0);
2978                         }
2979                         if (asserted & ATTN_GENERAL_ATTN_2) {
2980                                 PMD_DRV_LOG(DEBUG, "ATTN_GENERAL_ATTN_2!");
2981                                 REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_2, 0x0);
2982                         }
2983                         if (asserted & ATTN_GENERAL_ATTN_3) {
2984                                 PMD_DRV_LOG(DEBUG, "ATTN_GENERAL_ATTN_3!");
2985                                 REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_3, 0x0);
2986                         }
2987                 } else {
2988                         if (asserted & ATTN_GENERAL_ATTN_4) {
2989                                 PMD_DRV_LOG(DEBUG, "ATTN_GENERAL_ATTN_4!");
2990                                 REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_4, 0x0);
2991                         }
2992                         if (asserted & ATTN_GENERAL_ATTN_5) {
2993                                 PMD_DRV_LOG(DEBUG, "ATTN_GENERAL_ATTN_5!");
2994                                 REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_5, 0x0);
2995                         }
2996                         if (asserted & ATTN_GENERAL_ATTN_6) {
2997                                 PMD_DRV_LOG(DEBUG, "ATTN_GENERAL_ATTN_6!");
2998                                 REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_6, 0x0);
2999                         }
3000                 }
3001         }
3002         /* hardwired */
3003         if (sc->devinfo.int_block == INT_BLOCK_HC) {
3004                 reg_addr =
3005                     (HC_REG_COMMAND_REG + port * 32 +
3006                      COMMAND_REG_ATTN_BITS_SET);
3007         } else {
3008                 reg_addr = (BAR_IGU_INTMEM + IGU_CMD_ATTN_BIT_SET_UPPER * 8);
3009         }
3010
3011         PMD_DRV_LOG(DEBUG, "about to mask 0x%08x at %s addr 0x%08x",
3012                     asserted,
3013                     (sc->devinfo.int_block == INT_BLOCK_HC) ? "HC" : "IGU",
3014                     reg_addr);
3015         REG_WR(sc, reg_addr, asserted);
3016
3017         /* now set back the mask */
3018         if (asserted & ATTN_NIG_FOR_FUNC) {
3019                 /*
3020                  * Verify that IGU ack through BAR was written before restoring
3021                  * NIG mask. This loop should exit after 2-3 iterations max.
3022                  */
3023                 if (sc->devinfo.int_block != INT_BLOCK_HC) {
3024                         cnt = 0;
3025
3026                         do {
3027                                 igu_acked =
3028                                     REG_RD(sc, IGU_REG_ATTENTION_ACK_BITS);
3029                         } while (((igu_acked & ATTN_NIG_FOR_FUNC) == 0)
3030                                  && (++cnt < MAX_IGU_ATTN_ACK_TO));
3031
3032                         if (!igu_acked) {
3033                                 PMD_DRV_LOG(ERR,
3034                                             "Failed to verify IGU ack on time");
3035                         }
3036
3037                         mb();
3038                 }
3039
3040                 REG_WR(sc, nig_int_mask_addr, nig_mask);
3041
3042         }
3043 }
3044
3045 static void
3046 bnx2x_print_next_block(__rte_unused struct bnx2x_softc *sc, __rte_unused int idx,
3047                      __rte_unused const char *blk)
3048 {
3049         PMD_DRV_LOG(INFO, "%s%s", idx ? ", " : "", blk);
3050 }
3051
3052 static int
3053 bnx2x_check_blocks_with_parity0(struct bnx2x_softc *sc, uint32_t sig, int par_num,
3054                               uint8_t print)
3055 {
3056         uint32_t cur_bit = 0;
3057         int i = 0;
3058
3059         for (i = 0; sig; i++) {
3060                 cur_bit = ((uint32_t) 0x1 << i);
3061                 if (sig & cur_bit) {
3062                         switch (cur_bit) {
3063                         case AEU_INPUTS_ATTN_BITS_BRB_PARITY_ERROR:
3064                                 if (print)
3065                                         bnx2x_print_next_block(sc, par_num++,
3066                                                              "BRB");
3067                                 break;
3068                         case AEU_INPUTS_ATTN_BITS_PARSER_PARITY_ERROR:
3069                                 if (print)
3070                                         bnx2x_print_next_block(sc, par_num++,
3071                                                              "PARSER");
3072                                 break;
3073                         case AEU_INPUTS_ATTN_BITS_TSDM_PARITY_ERROR:
3074                                 if (print)
3075                                         bnx2x_print_next_block(sc, par_num++,
3076                                                              "TSDM");
3077                                 break;
3078                         case AEU_INPUTS_ATTN_BITS_SEARCHER_PARITY_ERROR:
3079                                 if (print)
3080                                         bnx2x_print_next_block(sc, par_num++,
3081                                                              "SEARCHER");
3082                                 break;
3083                         case AEU_INPUTS_ATTN_BITS_TCM_PARITY_ERROR:
3084                                 if (print)
3085                                         bnx2x_print_next_block(sc, par_num++,
3086                                                              "TCM");
3087                                 break;
3088                         case AEU_INPUTS_ATTN_BITS_TSEMI_PARITY_ERROR:
3089                                 if (print)
3090                                         bnx2x_print_next_block(sc, par_num++,
3091                                                              "TSEMI");
3092                                 break;
3093                         case AEU_INPUTS_ATTN_BITS_PBCLIENT_PARITY_ERROR:
3094                                 if (print)
3095                                         bnx2x_print_next_block(sc, par_num++,
3096                                                              "XPB");
3097                                 break;
3098                         }
3099
3100                         /* Clear the bit */
3101                         sig &= ~cur_bit;
3102                 }
3103         }
3104
3105         return par_num;
3106 }
3107
3108 static int
3109 bnx2x_check_blocks_with_parity1(struct bnx2x_softc *sc, uint32_t sig, int par_num,
3110                               uint8_t * global, uint8_t print)
3111 {
3112         int i = 0;
3113         uint32_t cur_bit = 0;
3114         for (i = 0; sig; i++) {
3115                 cur_bit = ((uint32_t) 0x1 << i);
3116                 if (sig & cur_bit) {
3117                         switch (cur_bit) {
3118                         case AEU_INPUTS_ATTN_BITS_PBF_PARITY_ERROR:
3119                                 if (print)
3120                                         bnx2x_print_next_block(sc, par_num++,
3121                                                              "PBF");
3122                                 break;
3123                         case AEU_INPUTS_ATTN_BITS_QM_PARITY_ERROR:
3124                                 if (print)
3125                                         bnx2x_print_next_block(sc, par_num++,
3126                                                              "QM");
3127                                 break;
3128                         case AEU_INPUTS_ATTN_BITS_TIMERS_PARITY_ERROR:
3129                                 if (print)
3130                                         bnx2x_print_next_block(sc, par_num++,
3131                                                              "TM");
3132                                 break;
3133                         case AEU_INPUTS_ATTN_BITS_XSDM_PARITY_ERROR:
3134                                 if (print)
3135                                         bnx2x_print_next_block(sc, par_num++,
3136                                                              "XSDM");
3137                                 break;
3138                         case AEU_INPUTS_ATTN_BITS_XCM_PARITY_ERROR:
3139                                 if (print)
3140                                         bnx2x_print_next_block(sc, par_num++,
3141                                                              "XCM");
3142                                 break;
3143                         case AEU_INPUTS_ATTN_BITS_XSEMI_PARITY_ERROR:
3144                                 if (print)
3145                                         bnx2x_print_next_block(sc, par_num++,
3146                                                              "XSEMI");
3147                                 break;
3148                         case AEU_INPUTS_ATTN_BITS_DOORBELLQ_PARITY_ERROR:
3149                                 if (print)
3150                                         bnx2x_print_next_block(sc, par_num++,
3151                                                              "DOORBELLQ");
3152                                 break;
3153                         case AEU_INPUTS_ATTN_BITS_NIG_PARITY_ERROR:
3154                                 if (print)
3155                                         bnx2x_print_next_block(sc, par_num++,
3156                                                              "NIG");
3157                                 break;
3158                         case AEU_INPUTS_ATTN_BITS_VAUX_PCI_CORE_PARITY_ERROR:
3159                                 if (print)
3160                                         bnx2x_print_next_block(sc, par_num++,
3161                                                              "VAUX PCI CORE");
3162                                 *global = TRUE;
3163                                 break;
3164                         case AEU_INPUTS_ATTN_BITS_DEBUG_PARITY_ERROR:
3165                                 if (print)
3166                                         bnx2x_print_next_block(sc, par_num++,
3167                                                              "DEBUG");
3168                                 break;
3169                         case AEU_INPUTS_ATTN_BITS_USDM_PARITY_ERROR:
3170                                 if (print)
3171                                         bnx2x_print_next_block(sc, par_num++,
3172                                                              "USDM");
3173                                 break;
3174                         case AEU_INPUTS_ATTN_BITS_UCM_PARITY_ERROR:
3175                                 if (print)
3176                                         bnx2x_print_next_block(sc, par_num++,
3177                                                              "UCM");
3178                                 break;
3179                         case AEU_INPUTS_ATTN_BITS_USEMI_PARITY_ERROR:
3180                                 if (print)
3181                                         bnx2x_print_next_block(sc, par_num++,
3182                                                              "USEMI");
3183                                 break;
3184                         case AEU_INPUTS_ATTN_BITS_UPB_PARITY_ERROR:
3185                                 if (print)
3186                                         bnx2x_print_next_block(sc, par_num++,
3187                                                              "UPB");
3188                                 break;
3189                         case AEU_INPUTS_ATTN_BITS_CSDM_PARITY_ERROR:
3190                                 if (print)
3191                                         bnx2x_print_next_block(sc, par_num++,
3192                                                              "CSDM");
3193                                 break;
3194                         case AEU_INPUTS_ATTN_BITS_CCM_PARITY_ERROR:
3195                                 if (print)
3196                                         bnx2x_print_next_block(sc, par_num++,
3197                                                              "CCM");
3198                                 break;
3199                         }
3200
3201                         /* Clear the bit */
3202                         sig &= ~cur_bit;
3203                 }
3204         }
3205
3206         return par_num;
3207 }
3208
3209 static int
3210 bnx2x_check_blocks_with_parity2(struct bnx2x_softc *sc, uint32_t sig, int par_num,
3211                               uint8_t print)
3212 {
3213         uint32_t cur_bit = 0;
3214         int i = 0;
3215
3216         for (i = 0; sig; i++) {
3217                 cur_bit = ((uint32_t) 0x1 << i);
3218                 if (sig & cur_bit) {
3219                         switch (cur_bit) {
3220                         case AEU_INPUTS_ATTN_BITS_CSEMI_PARITY_ERROR:
3221                                 if (print)
3222                                         bnx2x_print_next_block(sc, par_num++,
3223                                                              "CSEMI");
3224                                 break;
3225                         case AEU_INPUTS_ATTN_BITS_PXP_PARITY_ERROR:
3226                                 if (print)
3227                                         bnx2x_print_next_block(sc, par_num++,
3228                                                              "PXP");
3229                                 break;
3230                         case AEU_IN_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR:
3231                                 if (print)
3232                                         bnx2x_print_next_block(sc, par_num++,
3233                                                              "PXPPCICLOCKCLIENT");
3234                                 break;
3235                         case AEU_INPUTS_ATTN_BITS_CFC_PARITY_ERROR:
3236                                 if (print)
3237                                         bnx2x_print_next_block(sc, par_num++,
3238                                                              "CFC");
3239                                 break;
3240                         case AEU_INPUTS_ATTN_BITS_CDU_PARITY_ERROR:
3241                                 if (print)
3242                                         bnx2x_print_next_block(sc, par_num++,
3243                                                              "CDU");
3244                                 break;
3245                         case AEU_INPUTS_ATTN_BITS_DMAE_PARITY_ERROR:
3246                                 if (print)
3247                                         bnx2x_print_next_block(sc, par_num++,
3248                                                              "DMAE");
3249                                 break;
3250                         case AEU_INPUTS_ATTN_BITS_IGU_PARITY_ERROR:
3251                                 if (print)
3252                                         bnx2x_print_next_block(sc, par_num++,
3253                                                              "IGU");
3254                                 break;
3255                         case AEU_INPUTS_ATTN_BITS_MISC_PARITY_ERROR:
3256                                 if (print)
3257                                         bnx2x_print_next_block(sc, par_num++,
3258                                                              "MISC");
3259                                 break;
3260                         }
3261
3262                         /* Clear the bit */
3263                         sig &= ~cur_bit;
3264                 }
3265         }
3266
3267         return par_num;
3268 }
3269
3270 static int
3271 bnx2x_check_blocks_with_parity3(struct bnx2x_softc *sc, uint32_t sig, int par_num,
3272                               uint8_t * global, uint8_t print)
3273 {
3274         uint32_t cur_bit = 0;
3275         int i = 0;
3276
3277         for (i = 0; sig; i++) {
3278                 cur_bit = ((uint32_t) 0x1 << i);
3279                 if (sig & cur_bit) {
3280                         switch (cur_bit) {
3281                         case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_ROM_PARITY:
3282                                 if (print)
3283                                         bnx2x_print_next_block(sc, par_num++,
3284                                                              "MCP ROM");
3285                                 *global = TRUE;
3286                                 break;
3287                         case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_RX_PARITY:
3288                                 if (print)
3289                                         bnx2x_print_next_block(sc, par_num++,
3290                                                              "MCP UMP RX");
3291                                 *global = TRUE;
3292                                 break;
3293                         case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_TX_PARITY:
3294                                 if (print)
3295                                         bnx2x_print_next_block(sc, par_num++,
3296                                                              "MCP UMP TX");
3297                                 *global = TRUE;
3298                                 break;
3299                         case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_SCPAD_PARITY:
3300                                 if (print)
3301                                         bnx2x_print_next_block(sc, par_num++,
3302                                                              "MCP SCPAD");
3303                                 *global = TRUE;
3304                                 break;
3305                         }
3306
3307                         /* Clear the bit */
3308                         sig &= ~cur_bit;
3309                 }
3310         }
3311
3312         return par_num;
3313 }
3314
3315 static int
3316 bnx2x_check_blocks_with_parity4(struct bnx2x_softc *sc, uint32_t sig, int par_num,
3317                               uint8_t print)
3318 {
3319         uint32_t cur_bit = 0;
3320         int i = 0;
3321
3322         for (i = 0; sig; i++) {
3323                 cur_bit = ((uint32_t) 0x1 << i);
3324                 if (sig & cur_bit) {
3325                         switch (cur_bit) {
3326                         case AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR:
3327                                 if (print)
3328                                         bnx2x_print_next_block(sc, par_num++,
3329                                                              "PGLUE_B");
3330                                 break;
3331                         case AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR:
3332                                 if (print)
3333                                         bnx2x_print_next_block(sc, par_num++,
3334                                                              "ATC");
3335                                 break;
3336                         }
3337
3338                         /* Clear the bit */
3339                         sig &= ~cur_bit;
3340                 }
3341         }
3342
3343         return par_num;
3344 }
3345
3346 static uint8_t
3347 bnx2x_parity_attn(struct bnx2x_softc *sc, uint8_t * global, uint8_t print,
3348                 uint32_t * sig)
3349 {
3350         int par_num = 0;
3351
3352         if ((sig[0] & HW_PRTY_ASSERT_SET_0) ||
3353             (sig[1] & HW_PRTY_ASSERT_SET_1) ||
3354             (sig[2] & HW_PRTY_ASSERT_SET_2) ||
3355             (sig[3] & HW_PRTY_ASSERT_SET_3) ||
3356             (sig[4] & HW_PRTY_ASSERT_SET_4)) {
3357                 PMD_DRV_LOG(ERR,
3358                             "Parity error: HW block parity attention:"
3359                             "[0]:0x%08x [1]:0x%08x [2]:0x%08x [3]:0x%08x [4]:0x%08x",
3360                             (uint32_t) (sig[0] & HW_PRTY_ASSERT_SET_0),
3361                             (uint32_t) (sig[1] & HW_PRTY_ASSERT_SET_1),
3362                             (uint32_t) (sig[2] & HW_PRTY_ASSERT_SET_2),
3363                             (uint32_t) (sig[3] & HW_PRTY_ASSERT_SET_3),
3364                             (uint32_t) (sig[4] & HW_PRTY_ASSERT_SET_4));
3365
3366                 if (print)
3367                         PMD_DRV_LOG(INFO, "Parity errors detected in blocks: ");
3368
3369                 par_num =
3370                     bnx2x_check_blocks_with_parity0(sc, sig[0] &
3371                                                   HW_PRTY_ASSERT_SET_0,
3372                                                   par_num, print);
3373                 par_num =
3374                     bnx2x_check_blocks_with_parity1(sc, sig[1] &
3375                                                   HW_PRTY_ASSERT_SET_1,
3376                                                   par_num, global, print);
3377                 par_num =
3378                     bnx2x_check_blocks_with_parity2(sc, sig[2] &
3379                                                   HW_PRTY_ASSERT_SET_2,
3380                                                   par_num, print);
3381                 par_num =
3382                     bnx2x_check_blocks_with_parity3(sc, sig[3] &
3383                                                   HW_PRTY_ASSERT_SET_3,
3384                                                   par_num, global, print);
3385                 par_num =
3386                     bnx2x_check_blocks_with_parity4(sc, sig[4] &
3387                                                   HW_PRTY_ASSERT_SET_4,
3388                                                   par_num, print);
3389
3390                 if (print)
3391                         PMD_DRV_LOG(INFO, "");
3392
3393                 return TRUE;
3394         }
3395
3396         return FALSE;
3397 }
3398
3399 static uint8_t
3400 bnx2x_chk_parity_attn(struct bnx2x_softc *sc, uint8_t * global, uint8_t print)
3401 {
3402         struct attn_route attn = { {0} };
3403         int port = SC_PORT(sc);
3404
3405         attn.sig[0] = REG_RD(sc, MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 + port * 4);
3406         attn.sig[1] = REG_RD(sc, MISC_REG_AEU_AFTER_INVERT_2_FUNC_0 + port * 4);
3407         attn.sig[2] = REG_RD(sc, MISC_REG_AEU_AFTER_INVERT_3_FUNC_0 + port * 4);
3408         attn.sig[3] = REG_RD(sc, MISC_REG_AEU_AFTER_INVERT_4_FUNC_0 + port * 4);
3409
3410         if (!CHIP_IS_E1x(sc))
3411                 attn.sig[4] =
3412                     REG_RD(sc, MISC_REG_AEU_AFTER_INVERT_5_FUNC_0 + port * 4);
3413
3414         return bnx2x_parity_attn(sc, global, print, attn.sig);
3415 }
3416
3417 static void bnx2x_attn_int_deasserted4(struct bnx2x_softc *sc, uint32_t attn)
3418 {
3419         uint32_t val;
3420
3421         if (attn & AEU_INPUTS_ATTN_BITS_PGLUE_HW_INTERRUPT) {
3422                 val = REG_RD(sc, PGLUE_B_REG_PGLUE_B_INT_STS_CLR);
3423                 PMD_DRV_LOG(INFO, "ERROR: PGLUE hw attention 0x%08x", val);
3424                 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_ADDRESS_ERROR)
3425                         PMD_DRV_LOG(INFO,
3426                                     "ERROR: PGLUE_B_PGLUE_B_INT_STS_REG_ADDRESS_ERROR");
3427                 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_INCORRECT_RCV_BEHAVIOR)
3428                         PMD_DRV_LOG(INFO,
3429                                     "ERROR: PGLUE_B_PGLUE_B_INT_STS_REG_INCORRECT_RCV_BEHAVIOR");
3430                 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_WAS_ERROR_ATTN)
3431                         PMD_DRV_LOG(INFO,
3432                                     "ERROR: PGLUE_B_PGLUE_B_INT_STS_REG_WAS_ERROR_ATTN");
3433                 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_VF_LENGTH_VIOLATION_ATTN)
3434                         PMD_DRV_LOG(INFO,
3435                                     "ERROR: PGLUE_B_PGLUE_B_INT_STS_REG_VF_LENGTH_VIOLATION_ATTN");
3436                 if (val &
3437                     PGLUE_B_PGLUE_B_INT_STS_REG_VF_GRC_SPACE_VIOLATION_ATTN)
3438                         PMD_DRV_LOG(INFO,
3439                                     "ERROR: PGLUE_B_PGLUE_B_INT_STS_REG_VF_GRC_SPACE_VIOLATION_ATTN");
3440                 if (val &
3441                     PGLUE_B_PGLUE_B_INT_STS_REG_VF_MSIX_BAR_VIOLATION_ATTN)
3442                         PMD_DRV_LOG(INFO,
3443                                     "ERROR: PGLUE_B_PGLUE_B_INT_STS_REG_VF_MSIX_BAR_VIOLATION_ATTN");
3444                 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_ERROR_ATTN)
3445                         PMD_DRV_LOG(INFO,
3446                                     "ERROR: PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_ERROR_ATTN");
3447                 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_IN_TWO_RCBS_ATTN)
3448                         PMD_DRV_LOG(INFO,
3449                                     "ERROR: PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_IN_TWO_RCBS_ATTN");
3450                 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_CSSNOOP_FIFO_OVERFLOW)
3451                         PMD_DRV_LOG(INFO,
3452                                     "ERROR: PGLUE_B_PGLUE_B_INT_STS_REG_CSSNOOP_FIFO_OVERFLOW");
3453         }
3454
3455         if (attn & AEU_INPUTS_ATTN_BITS_ATC_HW_INTERRUPT) {
3456                 val = REG_RD(sc, ATC_REG_ATC_INT_STS_CLR);
3457                 PMD_DRV_LOG(INFO, "ERROR: ATC hw attention 0x%08x", val);
3458                 if (val & ATC_ATC_INT_STS_REG_ADDRESS_ERROR)
3459                         PMD_DRV_LOG(INFO,
3460                                     "ERROR: ATC_ATC_INT_STS_REG_ADDRESS_ERROR");
3461                 if (val & ATC_ATC_INT_STS_REG_ATC_TCPL_TO_NOT_PEND)
3462                         PMD_DRV_LOG(INFO,
3463                                     "ERROR: ATC_ATC_INT_STS_REG_ATC_TCPL_TO_NOT_PEND");
3464                 if (val & ATC_ATC_INT_STS_REG_ATC_GPA_MULTIPLE_HITS)
3465                         PMD_DRV_LOG(INFO,
3466                                     "ERROR: ATC_ATC_INT_STS_REG_ATC_GPA_MULTIPLE_HITS");
3467                 if (val & ATC_ATC_INT_STS_REG_ATC_RCPL_TO_EMPTY_CNT)
3468                         PMD_DRV_LOG(INFO,
3469                                     "ERROR: ATC_ATC_INT_STS_REG_ATC_RCPL_TO_EMPTY_CNT");
3470                 if (val & ATC_ATC_INT_STS_REG_ATC_TCPL_ERROR)
3471                         PMD_DRV_LOG(INFO,
3472                                     "ERROR: ATC_ATC_INT_STS_REG_ATC_TCPL_ERROR");
3473                 if (val & ATC_ATC_INT_STS_REG_ATC_IREQ_LESS_THAN_STU)
3474                         PMD_DRV_LOG(INFO,
3475                                     "ERROR: ATC_ATC_INT_STS_REG_ATC_IREQ_LESS_THAN_STU");
3476         }
3477
3478         if (attn & (AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR |
3479                     AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR)) {
3480                 PMD_DRV_LOG(INFO,
3481                             "ERROR: FATAL parity attention set4 0x%08x",
3482                             (uint32_t) (attn &
3483                                         (AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR
3484                                          |
3485                                          AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR)));
3486         }
3487 }
3488
3489 static void bnx2x_e1h_disable(struct bnx2x_softc *sc)
3490 {
3491         int port = SC_PORT(sc);
3492
3493         REG_WR(sc, NIG_REG_LLH0_FUNC_EN + port * 8, 0);
3494 }
3495
3496 static void bnx2x_e1h_enable(struct bnx2x_softc *sc)
3497 {
3498         int port = SC_PORT(sc);
3499
3500         REG_WR(sc, NIG_REG_LLH0_FUNC_EN + port * 8, 1);
3501 }
3502
3503 /*
3504  * called due to MCP event (on pmf):
3505  *   reread new bandwidth configuration
3506  *   configure FW
3507  *   notify others function about the change
3508  */
3509 static void bnx2x_config_mf_bw(struct bnx2x_softc *sc)
3510 {
3511         if (sc->link_vars.link_up) {
3512                 bnx2x_cmng_fns_init(sc, TRUE, CMNG_FNS_MINMAX);
3513                 bnx2x_link_sync_notify(sc);
3514         }
3515
3516         storm_memset_cmng(sc, &sc->cmng, SC_PORT(sc));
3517 }
3518
3519 static void bnx2x_set_mf_bw(struct bnx2x_softc *sc)
3520 {
3521         bnx2x_config_mf_bw(sc);
3522         bnx2x_fw_command(sc, DRV_MSG_CODE_SET_MF_BW_ACK, 0);
3523 }
3524
3525 static void bnx2x_handle_eee_event(struct bnx2x_softc *sc)
3526 {
3527         bnx2x_fw_command(sc, DRV_MSG_CODE_EEE_RESULTS_ACK, 0);
3528 }
3529
3530 #define DRV_INFO_ETH_STAT_NUM_MACS_REQUIRED 3
3531
3532 static void bnx2x_drv_info_ether_stat(struct bnx2x_softc *sc)
3533 {
3534         struct eth_stats_info *ether_stat = &sc->sp->drv_info_to_mcp.ether_stat;
3535
3536         strncpy(ether_stat->version, BNX2X_DRIVER_VERSION,
3537                 ETH_STAT_INFO_VERSION_LEN);
3538
3539         sc->sp_objs[0].mac_obj.get_n_elements(sc, &sc->sp_objs[0].mac_obj,
3540                                               DRV_INFO_ETH_STAT_NUM_MACS_REQUIRED,
3541                                               ether_stat->mac_local + MAC_PAD,
3542                                               MAC_PAD, ETH_ALEN);
3543
3544         ether_stat->mtu_size = sc->mtu;
3545
3546         ether_stat->feature_flags |= FEATURE_ETH_CHKSUM_OFFLOAD_MASK;
3547         ether_stat->promiscuous_mode = 0;       // (flags & PROMISC) ? 1 : 0;
3548
3549         ether_stat->txq_size = sc->tx_ring_size;
3550         ether_stat->rxq_size = sc->rx_ring_size;
3551 }
3552
3553 static void bnx2x_handle_drv_info_req(struct bnx2x_softc *sc)
3554 {
3555         enum drv_info_opcode op_code;
3556         uint32_t drv_info_ctl = SHMEM2_RD(sc, drv_info_control);
3557
3558         /* if drv_info version supported by MFW doesn't match - send NACK */
3559         if ((drv_info_ctl & DRV_INFO_CONTROL_VER_MASK) != DRV_INFO_CUR_VER) {
3560                 bnx2x_fw_command(sc, DRV_MSG_CODE_DRV_INFO_NACK, 0);
3561                 return;
3562         }
3563
3564         op_code = ((drv_info_ctl & DRV_INFO_CONTROL_OP_CODE_MASK) >>
3565                    DRV_INFO_CONTROL_OP_CODE_SHIFT);
3566
3567         memset(&sc->sp->drv_info_to_mcp, 0, sizeof(union drv_info_to_mcp));
3568
3569         switch (op_code) {
3570         case ETH_STATS_OPCODE:
3571                 bnx2x_drv_info_ether_stat(sc);
3572                 break;
3573         case FCOE_STATS_OPCODE:
3574         case ISCSI_STATS_OPCODE:
3575         default:
3576                 /* if op code isn't supported - send NACK */
3577                 bnx2x_fw_command(sc, DRV_MSG_CODE_DRV_INFO_NACK, 0);
3578                 return;
3579         }
3580
3581         /*
3582          * If we got drv_info attn from MFW then these fields are defined in
3583          * shmem2 for sure
3584          */
3585         SHMEM2_WR(sc, drv_info_host_addr_lo,
3586                   U64_LO(BNX2X_SP_MAPPING(sc, drv_info_to_mcp)));
3587         SHMEM2_WR(sc, drv_info_host_addr_hi,
3588                   U64_HI(BNX2X_SP_MAPPING(sc, drv_info_to_mcp)));
3589
3590         bnx2x_fw_command(sc, DRV_MSG_CODE_DRV_INFO_ACK, 0);
3591 }
3592
3593 static void bnx2x_dcc_event(struct bnx2x_softc *sc, uint32_t dcc_event)
3594 {
3595         if (dcc_event & DRV_STATUS_DCC_DISABLE_ENABLE_PF) {
3596 /*
3597  * This is the only place besides the function initialization
3598  * where the sc->flags can change so it is done without any
3599  * locks
3600  */
3601                 if (sc->devinfo.
3602                     mf_info.mf_config[SC_VN(sc)] & FUNC_MF_CFG_FUNC_DISABLED) {
3603                         PMD_DRV_LOG(DEBUG, "mf_cfg function disabled");
3604                         sc->flags |= BNX2X_MF_FUNC_DIS;
3605                         bnx2x_e1h_disable(sc);
3606                 } else {
3607                         PMD_DRV_LOG(DEBUG, "mf_cfg function enabled");
3608                         sc->flags &= ~BNX2X_MF_FUNC_DIS;
3609                         bnx2x_e1h_enable(sc);
3610                 }
3611                 dcc_event &= ~DRV_STATUS_DCC_DISABLE_ENABLE_PF;
3612         }
3613
3614         if (dcc_event & DRV_STATUS_DCC_BANDWIDTH_ALLOCATION) {
3615                 bnx2x_config_mf_bw(sc);
3616                 dcc_event &= ~DRV_STATUS_DCC_BANDWIDTH_ALLOCATION;
3617         }
3618
3619         /* Report results to MCP */
3620         if (dcc_event)
3621                 bnx2x_fw_command(sc, DRV_MSG_CODE_DCC_FAILURE, 0);
3622         else
3623                 bnx2x_fw_command(sc, DRV_MSG_CODE_DCC_OK, 0);
3624 }
3625
3626 static void bnx2x_pmf_update(struct bnx2x_softc *sc)
3627 {
3628         int port = SC_PORT(sc);
3629         uint32_t val;
3630
3631         sc->port.pmf = 1;
3632
3633         /*
3634          * We need the mb() to ensure the ordering between the writing to
3635          * sc->port.pmf here and reading it from the bnx2x_periodic_task().
3636          */
3637         mb();
3638
3639         /* enable nig attention */
3640         val = (0xff0f | (1 << (SC_VN(sc) + 4)));
3641         if (sc->devinfo.int_block == INT_BLOCK_HC) {
3642                 REG_WR(sc, HC_REG_TRAILING_EDGE_0 + port * 8, val);
3643                 REG_WR(sc, HC_REG_LEADING_EDGE_0 + port * 8, val);
3644         } else if (!CHIP_IS_E1x(sc)) {
3645                 REG_WR(sc, IGU_REG_TRAILING_EDGE_LATCH, val);
3646                 REG_WR(sc, IGU_REG_LEADING_EDGE_LATCH, val);
3647         }
3648
3649         bnx2x_stats_handle(sc, STATS_EVENT_PMF);
3650 }
3651
3652 static int bnx2x_mc_assert(struct bnx2x_softc *sc)
3653 {
3654         char last_idx;
3655         int i, rc = 0;
3656         __rte_unused uint32_t row0, row1, row2, row3;
3657
3658         /* XSTORM */
3659         last_idx =
3660             REG_RD8(sc, BAR_XSTRORM_INTMEM + XSTORM_ASSERT_LIST_INDEX_OFFSET);
3661         if (last_idx)
3662                 PMD_DRV_LOG(ERR, "XSTORM_ASSERT_LIST_INDEX 0x%x", last_idx);
3663
3664         /* print the asserts */
3665         for (i = 0; i < STORM_ASSERT_ARRAY_SIZE; i++) {
3666
3667                 row0 =
3668                     REG_RD(sc,
3669                            BAR_XSTRORM_INTMEM + XSTORM_ASSERT_LIST_OFFSET(i));
3670                 row1 =
3671                     REG_RD(sc,
3672                            BAR_XSTRORM_INTMEM + XSTORM_ASSERT_LIST_OFFSET(i) +
3673                            4);
3674                 row2 =
3675                     REG_RD(sc,
3676                            BAR_XSTRORM_INTMEM + XSTORM_ASSERT_LIST_OFFSET(i) +
3677                            8);
3678                 row3 =
3679                     REG_RD(sc,
3680                            BAR_XSTRORM_INTMEM + XSTORM_ASSERT_LIST_OFFSET(i) +
3681                            12);
3682
3683                 if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) {
3684                         PMD_DRV_LOG(ERR,
3685                                     "XSTORM_ASSERT_INDEX 0x%x = 0x%08x 0x%08x 0x%08x 0x%08x",
3686                                     i, row3, row2, row1, row0);
3687                         rc++;
3688                 } else {
3689                         break;
3690                 }
3691         }
3692
3693         /* TSTORM */
3694         last_idx =
3695             REG_RD8(sc, BAR_TSTRORM_INTMEM + TSTORM_ASSERT_LIST_INDEX_OFFSET);
3696         if (last_idx) {
3697                 PMD_DRV_LOG(ERR, "TSTORM_ASSERT_LIST_INDEX 0x%x", last_idx);
3698         }
3699
3700         /* print the asserts */
3701         for (i = 0; i < STORM_ASSERT_ARRAY_SIZE; i++) {
3702
3703                 row0 =
3704                     REG_RD(sc,
3705                            BAR_TSTRORM_INTMEM + TSTORM_ASSERT_LIST_OFFSET(i));
3706                 row1 =
3707                     REG_RD(sc,
3708                            BAR_TSTRORM_INTMEM + TSTORM_ASSERT_LIST_OFFSET(i) +
3709                            4);
3710                 row2 =
3711                     REG_RD(sc,
3712                            BAR_TSTRORM_INTMEM + TSTORM_ASSERT_LIST_OFFSET(i) +
3713                            8);
3714                 row3 =
3715                     REG_RD(sc,
3716                            BAR_TSTRORM_INTMEM + TSTORM_ASSERT_LIST_OFFSET(i) +
3717                            12);
3718
3719                 if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) {
3720                         PMD_DRV_LOG(ERR,
3721                                     "TSTORM_ASSERT_INDEX 0x%x = 0x%08x 0x%08x 0x%08x 0x%08x",
3722                                     i, row3, row2, row1, row0);
3723                         rc++;
3724                 } else {
3725                         break;
3726                 }
3727         }
3728
3729         /* CSTORM */
3730         last_idx =
3731             REG_RD8(sc, BAR_CSTRORM_INTMEM + CSTORM_ASSERT_LIST_INDEX_OFFSET);
3732         if (last_idx) {
3733                 PMD_DRV_LOG(ERR, "CSTORM_ASSERT_LIST_INDEX 0x%x", last_idx);
3734         }
3735
3736         /* print the asserts */
3737         for (i = 0; i < STORM_ASSERT_ARRAY_SIZE; i++) {
3738
3739                 row0 =
3740                     REG_RD(sc,
3741                            BAR_CSTRORM_INTMEM + CSTORM_ASSERT_LIST_OFFSET(i));
3742                 row1 =
3743                     REG_RD(sc,
3744                            BAR_CSTRORM_INTMEM + CSTORM_ASSERT_LIST_OFFSET(i) +
3745                            4);
3746                 row2 =
3747                     REG_RD(sc,
3748                            BAR_CSTRORM_INTMEM + CSTORM_ASSERT_LIST_OFFSET(i) +
3749                            8);
3750                 row3 =
3751                     REG_RD(sc,
3752                            BAR_CSTRORM_INTMEM + CSTORM_ASSERT_LIST_OFFSET(i) +
3753                            12);
3754
3755                 if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) {
3756                         PMD_DRV_LOG(ERR,
3757                                     "CSTORM_ASSERT_INDEX 0x%x = 0x%08x 0x%08x 0x%08x 0x%08x",
3758                                     i, row3, row2, row1, row0);
3759                         rc++;
3760                 } else {
3761                         break;
3762                 }
3763         }
3764
3765         /* USTORM */
3766         last_idx =
3767             REG_RD8(sc, BAR_USTRORM_INTMEM + USTORM_ASSERT_LIST_INDEX_OFFSET);
3768         if (last_idx) {
3769                 PMD_DRV_LOG(ERR, "USTORM_ASSERT_LIST_INDEX 0x%x", last_idx);
3770         }
3771
3772         /* print the asserts */
3773         for (i = 0; i < STORM_ASSERT_ARRAY_SIZE; i++) {
3774
3775                 row0 =
3776                     REG_RD(sc,
3777                            BAR_USTRORM_INTMEM + USTORM_ASSERT_LIST_OFFSET(i));
3778                 row1 =
3779                     REG_RD(sc,
3780                            BAR_USTRORM_INTMEM + USTORM_ASSERT_LIST_OFFSET(i) +
3781                            4);
3782                 row2 =
3783                     REG_RD(sc,
3784                            BAR_USTRORM_INTMEM + USTORM_ASSERT_LIST_OFFSET(i) +
3785                            8);
3786                 row3 =
3787                     REG_RD(sc,
3788                            BAR_USTRORM_INTMEM + USTORM_ASSERT_LIST_OFFSET(i) +
3789                            12);
3790
3791                 if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) {
3792                         PMD_DRV_LOG(ERR,
3793                                     "USTORM_ASSERT_INDEX 0x%x = 0x%08x 0x%08x 0x%08x 0x%08x",
3794                                     i, row3, row2, row1, row0);
3795                         rc++;
3796                 } else {
3797                         break;
3798                 }
3799         }
3800
3801         return rc;
3802 }
3803
3804 static void bnx2x_attn_int_deasserted3(struct bnx2x_softc *sc, uint32_t attn)
3805 {
3806         int func = SC_FUNC(sc);
3807         uint32_t val;
3808
3809         if (attn & EVEREST_GEN_ATTN_IN_USE_MASK) {
3810
3811                 if (attn & BNX2X_PMF_LINK_ASSERT(sc)) {
3812
3813                         REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_12 + func * 4, 0);
3814                         bnx2x_read_mf_cfg(sc);
3815                         sc->devinfo.mf_info.mf_config[SC_VN(sc)] =
3816                             MFCFG_RD(sc,
3817                                      func_mf_config[SC_ABS_FUNC(sc)].config);
3818                         val =
3819                             SHMEM_RD(sc, func_mb[SC_FW_MB_IDX(sc)].drv_status);
3820
3821                         if (val & DRV_STATUS_DCC_EVENT_MASK)
3822                                 bnx2x_dcc_event(sc,
3823                                               (val &
3824                                                DRV_STATUS_DCC_EVENT_MASK));
3825
3826                         if (val & DRV_STATUS_SET_MF_BW)
3827                                 bnx2x_set_mf_bw(sc);
3828
3829                         if (val & DRV_STATUS_DRV_INFO_REQ)
3830                                 bnx2x_handle_drv_info_req(sc);
3831
3832                         if ((sc->port.pmf == 0) && (val & DRV_STATUS_PMF))
3833                                 bnx2x_pmf_update(sc);
3834
3835                         if (val & DRV_STATUS_EEE_NEGOTIATION_RESULTS)
3836                                 bnx2x_handle_eee_event(sc);
3837
3838                         if (sc->link_vars.periodic_flags &
3839                             ELINK_PERIODIC_FLAGS_LINK_EVENT) {
3840                                 /* sync with link */
3841                                 sc->link_vars.periodic_flags &=
3842                                     ~ELINK_PERIODIC_FLAGS_LINK_EVENT;
3843                                 if (IS_MF(sc)) {
3844                                         bnx2x_link_sync_notify(sc);
3845                                 }
3846                                 bnx2x_link_report(sc);
3847                         }
3848
3849                         /*
3850                          * Always call it here: bnx2x_link_report() will
3851                          * prevent the link indication duplication.
3852                          */
3853                         bnx2x_link_status_update(sc);
3854
3855                 } else if (attn & BNX2X_MC_ASSERT_BITS) {
3856
3857                         PMD_DRV_LOG(ERR, "MC assert!");
3858                         bnx2x_mc_assert(sc);
3859                         REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_10, 0);
3860                         REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_9, 0);
3861                         REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_8, 0);
3862                         REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_7, 0);
3863                         rte_panic("MC assert!");
3864
3865                 } else if (attn & BNX2X_MCP_ASSERT) {
3866
3867                         PMD_DRV_LOG(ERR, "MCP assert!");
3868                         REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_11, 0);
3869
3870                 } else {
3871                         PMD_DRV_LOG(ERR,
3872                                     "Unknown HW assert! (attn 0x%08x)", attn);
3873                 }
3874         }
3875
3876         if (attn & EVEREST_LATCHED_ATTN_IN_USE_MASK) {
3877                 PMD_DRV_LOG(ERR, "LATCHED attention 0x%08x (masked)", attn);
3878                 if (attn & BNX2X_GRC_TIMEOUT) {
3879                         val = REG_RD(sc, MISC_REG_GRC_TIMEOUT_ATTN);
3880                         PMD_DRV_LOG(ERR, "GRC time-out 0x%08x", val);
3881                 }
3882                 if (attn & BNX2X_GRC_RSV) {
3883                         val = REG_RD(sc, MISC_REG_GRC_RSV_ATTN);
3884                         PMD_DRV_LOG(ERR, "GRC reserved 0x%08x", val);
3885                 }
3886                 REG_WR(sc, MISC_REG_AEU_CLR_LATCH_SIGNAL, 0x7ff);
3887         }
3888 }
3889
3890 static void bnx2x_attn_int_deasserted2(struct bnx2x_softc *sc, uint32_t attn)
3891 {
3892         int port = SC_PORT(sc);
3893         int reg_offset;
3894         uint32_t val0, mask0, val1, mask1;
3895         uint32_t val;
3896
3897         if (attn & AEU_INPUTS_ATTN_BITS_CFC_HW_INTERRUPT) {
3898                 val = REG_RD(sc, CFC_REG_CFC_INT_STS_CLR);
3899                 PMD_DRV_LOG(ERR, "CFC hw attention 0x%08x", val);
3900 /* CFC error attention */
3901                 if (val & 0x2) {
3902                         PMD_DRV_LOG(ERR, "FATAL error from CFC");
3903                 }
3904         }
3905
3906         if (attn & AEU_INPUTS_ATTN_BITS_PXP_HW_INTERRUPT) {
3907                 val = REG_RD(sc, PXP_REG_PXP_INT_STS_CLR_0);
3908                 PMD_DRV_LOG(ERR, "PXP hw attention-0 0x%08x", val);
3909 /* RQ_USDMDP_FIFO_OVERFLOW */
3910                 if (val & 0x18000) {
3911                         PMD_DRV_LOG(ERR, "FATAL error from PXP");
3912                 }
3913
3914                 if (!CHIP_IS_E1x(sc)) {
3915                         val = REG_RD(sc, PXP_REG_PXP_INT_STS_CLR_1);
3916                         PMD_DRV_LOG(ERR, "PXP hw attention-1 0x%08x", val);
3917                 }
3918         }
3919 #define PXP2_EOP_ERROR_BIT  PXP2_PXP2_INT_STS_CLR_0_REG_WR_PGLUE_EOP_ERROR
3920 #define AEU_PXP2_HW_INT_BIT AEU_INPUTS_ATTN_BITS_PXPPCICLOCKCLIENT_HW_INTERRUPT
3921
3922         if (attn & AEU_PXP2_HW_INT_BIT) {
3923 /*  CQ47854 workaround do not panic on
3924  *  PXP2_PXP2_INT_STS_0_REG_WR_PGLUE_EOP_ERROR
3925  */
3926                 if (!CHIP_IS_E1x(sc)) {
3927                         mask0 = REG_RD(sc, PXP2_REG_PXP2_INT_MASK_0);
3928                         val1 = REG_RD(sc, PXP2_REG_PXP2_INT_STS_1);
3929                         mask1 = REG_RD(sc, PXP2_REG_PXP2_INT_MASK_1);
3930                         val0 = REG_RD(sc, PXP2_REG_PXP2_INT_STS_0);
3931                         /*
3932                          * If the only PXP2_EOP_ERROR_BIT is set in
3933                          * STS0 and STS1 - clear it
3934                          *
3935                          * probably we lose additional attentions between
3936                          * STS0 and STS_CLR0, in this case user will not
3937                          * be notified about them
3938                          */
3939                         if (val0 & mask0 & PXP2_EOP_ERROR_BIT &&
3940                             !(val1 & mask1))
3941                                 val0 = REG_RD(sc, PXP2_REG_PXP2_INT_STS_CLR_0);
3942
3943                         /* print the register, since no one can restore it */
3944                         PMD_DRV_LOG(ERR,
3945                                     "PXP2_REG_PXP2_INT_STS_CLR_0 0x%08x", val0);
3946
3947                         /*
3948                          * if PXP2_PXP2_INT_STS_0_REG_WR_PGLUE_EOP_ERROR
3949                          * then notify
3950                          */
3951                         if (val0 & PXP2_EOP_ERROR_BIT) {
3952                                 PMD_DRV_LOG(ERR, "PXP2_WR_PGLUE_EOP_ERROR");
3953
3954                                 /*
3955                                  * if only PXP2_PXP2_INT_STS_0_REG_WR_PGLUE_EOP_ERROR is
3956                                  * set then clear attention from PXP2 block without panic
3957                                  */
3958                                 if (((val0 & mask0) == PXP2_EOP_ERROR_BIT) &&
3959                                     ((val1 & mask1) == 0))
3960                                         attn &= ~AEU_PXP2_HW_INT_BIT;
3961                         }
3962                 }
3963         }
3964
3965         if (attn & HW_INTERRUT_ASSERT_SET_2) {
3966                 reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_2 :
3967                               MISC_REG_AEU_ENABLE1_FUNC_0_OUT_2);
3968
3969                 val = REG_RD(sc, reg_offset);
3970                 val &= ~(attn & HW_INTERRUT_ASSERT_SET_2);
3971                 REG_WR(sc, reg_offset, val);
3972
3973                 PMD_DRV_LOG(ERR,
3974                             "FATAL HW block attention set2 0x%x",
3975                             (uint32_t) (attn & HW_INTERRUT_ASSERT_SET_2));
3976                 rte_panic("HW block attention set2");
3977         }
3978 }
3979
3980 static void bnx2x_attn_int_deasserted1(struct bnx2x_softc *sc, uint32_t attn)
3981 {
3982         int port = SC_PORT(sc);
3983         int reg_offset;
3984         uint32_t val;
3985
3986         if (attn & AEU_INPUTS_ATTN_BITS_DOORBELLQ_HW_INTERRUPT) {
3987                 val = REG_RD(sc, DORQ_REG_DORQ_INT_STS_CLR);
3988                 PMD_DRV_LOG(ERR, "DB hw attention 0x%08x", val);
3989 /* DORQ discard attention */
3990                 if (val & 0x2) {
3991                         PMD_DRV_LOG(ERR, "FATAL error from DORQ");
3992                 }
3993         }
3994
3995         if (attn & HW_INTERRUT_ASSERT_SET_1) {
3996                 reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_1 :
3997                               MISC_REG_AEU_ENABLE1_FUNC_0_OUT_1);
3998
3999                 val = REG_RD(sc, reg_offset);
4000                 val &= ~(attn & HW_INTERRUT_ASSERT_SET_1);
4001                 REG_WR(sc, reg_offset, val);
4002
4003                 PMD_DRV_LOG(ERR,
4004                             "FATAL HW block attention set1 0x%08x",
4005                             (uint32_t) (attn & HW_INTERRUT_ASSERT_SET_1));
4006                 rte_panic("HW block attention set1");
4007         }
4008 }
4009
4010 static void bnx2x_attn_int_deasserted0(struct bnx2x_softc *sc, uint32_t attn)
4011 {
4012         int port = SC_PORT(sc);
4013         int reg_offset;
4014         uint32_t val;
4015
4016         reg_offset = (port) ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 :
4017             MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0;
4018
4019         if (attn & AEU_INPUTS_ATTN_BITS_SPIO5) {
4020                 val = REG_RD(sc, reg_offset);
4021                 val &= ~AEU_INPUTS_ATTN_BITS_SPIO5;
4022                 REG_WR(sc, reg_offset, val);
4023
4024                 PMD_DRV_LOG(WARNING, "SPIO5 hw attention");
4025
4026 /* Fan failure attention */
4027                 elink_hw_reset_phy(&sc->link_params);
4028                 bnx2x_fan_failure(sc);
4029         }
4030
4031         if ((attn & sc->link_vars.aeu_int_mask) && sc->port.pmf) {
4032                 elink_handle_module_detect_int(&sc->link_params);
4033         }
4034
4035         if (attn & HW_INTERRUT_ASSERT_SET_0) {
4036                 val = REG_RD(sc, reg_offset);
4037                 val &= ~(attn & HW_INTERRUT_ASSERT_SET_0);
4038                 REG_WR(sc, reg_offset, val);
4039
4040                 rte_panic("FATAL HW block attention set0 0x%lx",
4041                           (attn & HW_INTERRUT_ASSERT_SET_0));
4042         }
4043 }
4044
4045 static void bnx2x_attn_int_deasserted(struct bnx2x_softc *sc, uint32_t deasserted)
4046 {
4047         struct attn_route attn;
4048         struct attn_route *group_mask;
4049         int port = SC_PORT(sc);
4050         int index;
4051         uint32_t reg_addr;
4052         uint32_t val;
4053         uint32_t aeu_mask;
4054         uint8_t global = FALSE;
4055
4056         /*
4057          * Need to take HW lock because MCP or other port might also
4058          * try to handle this event.
4059          */
4060         bnx2x_acquire_alr(sc);
4061
4062         if (bnx2x_chk_parity_attn(sc, &global, TRUE)) {
4063                 sc->recovery_state = BNX2X_RECOVERY_INIT;
4064
4065 /* disable HW interrupts */
4066                 bnx2x_int_disable(sc);
4067                 bnx2x_release_alr(sc);
4068                 return;
4069         }
4070
4071         attn.sig[0] = REG_RD(sc, MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 + port * 4);
4072         attn.sig[1] = REG_RD(sc, MISC_REG_AEU_AFTER_INVERT_2_FUNC_0 + port * 4);
4073         attn.sig[2] = REG_RD(sc, MISC_REG_AEU_AFTER_INVERT_3_FUNC_0 + port * 4);
4074         attn.sig[3] = REG_RD(sc, MISC_REG_AEU_AFTER_INVERT_4_FUNC_0 + port * 4);
4075         if (!CHIP_IS_E1x(sc)) {
4076                 attn.sig[4] =
4077                     REG_RD(sc, MISC_REG_AEU_AFTER_INVERT_5_FUNC_0 + port * 4);
4078         } else {
4079                 attn.sig[4] = 0;
4080         }
4081
4082         for (index = 0; index < MAX_DYNAMIC_ATTN_GRPS; index++) {
4083                 if (deasserted & (1 << index)) {
4084                         group_mask = &sc->attn_group[index];
4085
4086                         bnx2x_attn_int_deasserted4(sc,
4087                                                  attn.
4088                                                  sig[4] & group_mask->sig[4]);
4089                         bnx2x_attn_int_deasserted3(sc,
4090                                                  attn.
4091                                                  sig[3] & group_mask->sig[3]);
4092                         bnx2x_attn_int_deasserted1(sc,
4093                                                  attn.
4094                                                  sig[1] & group_mask->sig[1]);
4095                         bnx2x_attn_int_deasserted2(sc,
4096                                                  attn.
4097                                                  sig[2] & group_mask->sig[2]);
4098                         bnx2x_attn_int_deasserted0(sc,
4099                                                  attn.
4100                                                  sig[0] & group_mask->sig[0]);
4101                 }
4102         }
4103
4104         bnx2x_release_alr(sc);
4105
4106         if (sc->devinfo.int_block == INT_BLOCK_HC) {
4107                 reg_addr = (HC_REG_COMMAND_REG + port * 32 +
4108                             COMMAND_REG_ATTN_BITS_CLR);
4109         } else {
4110                 reg_addr = (BAR_IGU_INTMEM + IGU_CMD_ATTN_BIT_CLR_UPPER * 8);
4111         }
4112
4113         val = ~deasserted;
4114         PMD_DRV_LOG(DEBUG,
4115                     "about to mask 0x%08x at %s addr 0x%08x", val,
4116                     (sc->devinfo.int_block == INT_BLOCK_HC) ? "HC" : "IGU",
4117                     reg_addr);
4118         REG_WR(sc, reg_addr, val);
4119
4120         if (~sc->attn_state & deasserted) {
4121                 PMD_DRV_LOG(ERR, "IGU error");
4122         }
4123
4124         reg_addr = port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 :
4125             MISC_REG_AEU_MASK_ATTN_FUNC_0;
4126
4127         bnx2x_acquire_hw_lock(sc, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
4128
4129         aeu_mask = REG_RD(sc, reg_addr);
4130
4131         aeu_mask |= (deasserted & 0x3ff);
4132
4133         REG_WR(sc, reg_addr, aeu_mask);
4134         bnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
4135
4136         sc->attn_state &= ~deasserted;
4137 }
4138
4139 static void bnx2x_attn_int(struct bnx2x_softc *sc)
4140 {
4141         /* read local copy of bits */
4142         uint32_t attn_bits = le32toh(sc->def_sb->atten_status_block.attn_bits);
4143         uint32_t attn_ack =
4144             le32toh(sc->def_sb->atten_status_block.attn_bits_ack);
4145         uint32_t attn_state = sc->attn_state;
4146
4147         /* look for changed bits */
4148         uint32_t asserted = attn_bits & ~attn_ack & ~attn_state;
4149         uint32_t deasserted = ~attn_bits & attn_ack & attn_state;
4150
4151         PMD_DRV_LOG(DEBUG,
4152                     "attn_bits 0x%08x attn_ack 0x%08x asserted 0x%08x deasserted 0x%08x",
4153                     attn_bits, attn_ack, asserted, deasserted);
4154
4155         if (~(attn_bits ^ attn_ack) & (attn_bits ^ attn_state)) {
4156                 PMD_DRV_LOG(ERR, "BAD attention state");
4157         }
4158
4159         /* handle bits that were raised */
4160         if (asserted) {
4161                 bnx2x_attn_int_asserted(sc, asserted);
4162         }
4163
4164         if (deasserted) {
4165                 bnx2x_attn_int_deasserted(sc, deasserted);
4166         }
4167 }
4168
4169 static uint16_t bnx2x_update_dsb_idx(struct bnx2x_softc *sc)
4170 {
4171         struct host_sp_status_block *def_sb = sc->def_sb;
4172         uint16_t rc = 0;
4173
4174         mb();                   /* status block is written to by the chip */
4175
4176         if (sc->def_att_idx != def_sb->atten_status_block.attn_bits_index) {
4177                 sc->def_att_idx = def_sb->atten_status_block.attn_bits_index;
4178                 rc |= BNX2X_DEF_SB_ATT_IDX;
4179         }
4180
4181         if (sc->def_idx != def_sb->sp_sb.running_index) {
4182                 sc->def_idx = def_sb->sp_sb.running_index;
4183                 rc |= BNX2X_DEF_SB_IDX;
4184         }
4185
4186         mb();
4187
4188         return rc;
4189 }
4190
4191 static struct ecore_queue_sp_obj *bnx2x_cid_to_q_obj(struct bnx2x_softc *sc,
4192                                                           uint32_t cid)
4193 {
4194         return &sc->sp_objs[CID_TO_FP(cid, sc)].q_obj;
4195 }
4196
4197 static void bnx2x_handle_mcast_eqe(struct bnx2x_softc *sc)
4198 {
4199         struct ecore_mcast_ramrod_params rparam;
4200         int rc;
4201
4202         memset(&rparam, 0, sizeof(rparam));
4203
4204         rparam.mcast_obj = &sc->mcast_obj;
4205
4206         /* clear pending state for the last command */
4207         sc->mcast_obj.raw.clear_pending(&sc->mcast_obj.raw);
4208
4209         /* if there are pending mcast commands - send them */
4210         if (sc->mcast_obj.check_pending(&sc->mcast_obj)) {
4211                 rc = ecore_config_mcast(sc, &rparam, ECORE_MCAST_CMD_CONT);
4212                 if (rc < 0) {
4213                         PMD_DRV_LOG(INFO,
4214                                     "Failed to send pending mcast commands (%d)",
4215                                     rc);
4216                 }
4217         }
4218 }
4219
4220 static void
4221 bnx2x_handle_classification_eqe(struct bnx2x_softc *sc, union event_ring_elem *elem)
4222 {
4223         unsigned long ramrod_flags = 0;
4224         int rc = 0;
4225         uint32_t cid = elem->message.data.eth_event.echo & BNX2X_SWCID_MASK;
4226         struct ecore_vlan_mac_obj *vlan_mac_obj;
4227
4228         /* always push next commands out, don't wait here */
4229         bnx2x_set_bit(RAMROD_CONT, &ramrod_flags);
4230
4231         switch (le32toh(elem->message.data.eth_event.echo) >> BNX2X_SWCID_SHIFT) {
4232         case ECORE_FILTER_MAC_PENDING:
4233                 PMD_DRV_LOG(DEBUG, "Got SETUP_MAC completions");
4234                 vlan_mac_obj = &sc->sp_objs[cid].mac_obj;
4235                 break;
4236
4237         case ECORE_FILTER_MCAST_PENDING:
4238                 PMD_DRV_LOG(DEBUG, "Got SETUP_MCAST completions");
4239                 bnx2x_handle_mcast_eqe(sc);
4240                 return;
4241
4242         default:
4243                 PMD_DRV_LOG(NOTICE, "Unsupported classification command: %d",
4244                             elem->message.data.eth_event.echo);
4245                 return;
4246         }
4247
4248         rc = vlan_mac_obj->complete(sc, vlan_mac_obj, elem, &ramrod_flags);
4249
4250         if (rc < 0) {
4251                 PMD_DRV_LOG(NOTICE, "Failed to schedule new commands (%d)", rc);
4252         } else if (rc > 0) {
4253                 PMD_DRV_LOG(DEBUG, "Scheduled next pending commands...");
4254         }
4255 }
4256
4257 static void bnx2x_handle_rx_mode_eqe(struct bnx2x_softc *sc)
4258 {
4259         bnx2x_clear_bit(ECORE_FILTER_RX_MODE_PENDING, &sc->sp_state);
4260
4261         /* send rx_mode command again if was requested */
4262         if (bnx2x_test_and_clear_bit(ECORE_FILTER_RX_MODE_SCHED, &sc->sp_state)) {
4263                 bnx2x_set_storm_rx_mode(sc);
4264         }
4265 }
4266
4267 static void bnx2x_update_eq_prod(struct bnx2x_softc *sc, uint16_t prod)
4268 {
4269         storm_memset_eq_prod(sc, prod, SC_FUNC(sc));
4270         wmb();                  /* keep prod updates ordered */
4271 }
4272
4273 static void bnx2x_eq_int(struct bnx2x_softc *sc)
4274 {
4275         uint16_t hw_cons, sw_cons, sw_prod;
4276         union event_ring_elem *elem;
4277         uint8_t echo;
4278         uint32_t cid;
4279         uint8_t opcode;
4280         int spqe_cnt = 0;
4281         struct ecore_queue_sp_obj *q_obj;
4282         struct ecore_func_sp_obj *f_obj = &sc->func_obj;
4283         struct ecore_raw_obj *rss_raw = &sc->rss_conf_obj.raw;
4284
4285         hw_cons = le16toh(*sc->eq_cons_sb);
4286
4287         /*
4288          * The hw_cons range is 1-255, 257 - the sw_cons range is 0-254, 256.
4289          * when we get to the next-page we need to adjust so the loop
4290          * condition below will be met. The next element is the size of a
4291          * regular element and hence incrementing by 1
4292          */
4293         if ((hw_cons & EQ_DESC_MAX_PAGE) == EQ_DESC_MAX_PAGE) {
4294                 hw_cons++;
4295         }
4296
4297         /*
4298          * This function may never run in parallel with itself for a
4299          * specific sc and no need for a read memory barrier here.
4300          */
4301         sw_cons = sc->eq_cons;
4302         sw_prod = sc->eq_prod;
4303
4304         for (;
4305              sw_cons != hw_cons;
4306              sw_prod = NEXT_EQ_IDX(sw_prod), sw_cons = NEXT_EQ_IDX(sw_cons)) {
4307
4308                 elem = &sc->eq[EQ_DESC(sw_cons)];
4309
4310 /* elem CID originates from FW, actually LE */
4311                 cid = SW_CID(elem->message.data.cfc_del_event.cid);
4312                 opcode = elem->message.opcode;
4313
4314 /* handle eq element */
4315                 switch (opcode) {
4316                 case EVENT_RING_OPCODE_STAT_QUERY:
4317                         PMD_DEBUG_PERIODIC_LOG(DEBUG, "got statistics completion event %d",
4318                                     sc->stats_comp++);
4319                         /* nothing to do with stats comp */
4320                         goto next_spqe;
4321
4322                 case EVENT_RING_OPCODE_CFC_DEL:
4323                         /* handle according to cid range */
4324                         /* we may want to verify here that the sc state is HALTING */
4325                         PMD_DRV_LOG(DEBUG, "got delete ramrod for MULTI[%d]",
4326                                     cid);
4327                         q_obj = bnx2x_cid_to_q_obj(sc, cid);
4328                         if (q_obj->complete_cmd(sc, q_obj, ECORE_Q_CMD_CFC_DEL)) {
4329                                 break;
4330                         }
4331                         goto next_spqe;
4332
4333                 case EVENT_RING_OPCODE_STOP_TRAFFIC:
4334                         PMD_DRV_LOG(DEBUG, "got STOP TRAFFIC");
4335                         if (f_obj->complete_cmd(sc, f_obj, ECORE_F_CMD_TX_STOP)) {
4336                                 break;
4337                         }
4338                         goto next_spqe;
4339
4340                 case EVENT_RING_OPCODE_START_TRAFFIC:
4341                         PMD_DRV_LOG(DEBUG, "got START TRAFFIC");
4342                         if (f_obj->complete_cmd
4343                             (sc, f_obj, ECORE_F_CMD_TX_START)) {
4344                                 break;
4345                         }
4346                         goto next_spqe;
4347
4348                 case EVENT_RING_OPCODE_FUNCTION_UPDATE:
4349                         echo = elem->message.data.function_update_event.echo;
4350                         if (echo == SWITCH_UPDATE) {
4351                                 PMD_DRV_LOG(DEBUG,
4352                                             "got FUNC_SWITCH_UPDATE ramrod");
4353                                 if (f_obj->complete_cmd(sc, f_obj,
4354                                                         ECORE_F_CMD_SWITCH_UPDATE))
4355                                 {
4356                                         break;
4357                                 }
4358                         } else {
4359                                 PMD_DRV_LOG(DEBUG,
4360                                             "AFEX: ramrod completed FUNCTION_UPDATE");
4361                                 f_obj->complete_cmd(sc, f_obj,
4362                                                     ECORE_F_CMD_AFEX_UPDATE);
4363                         }
4364                         goto next_spqe;
4365
4366                 case EVENT_RING_OPCODE_FORWARD_SETUP:
4367                         q_obj = &bnx2x_fwd_sp_obj(sc, q_obj);
4368                         if (q_obj->complete_cmd(sc, q_obj,
4369                                                 ECORE_Q_CMD_SETUP_TX_ONLY)) {
4370                                 break;
4371                         }
4372                         goto next_spqe;
4373
4374                 case EVENT_RING_OPCODE_FUNCTION_START:
4375                         PMD_DRV_LOG(DEBUG, "got FUNC_START ramrod");
4376                         if (f_obj->complete_cmd(sc, f_obj, ECORE_F_CMD_START)) {
4377                                 break;
4378                         }
4379                         goto next_spqe;
4380
4381                 case EVENT_RING_OPCODE_FUNCTION_STOP:
4382                         PMD_DRV_LOG(DEBUG, "got FUNC_STOP ramrod");
4383                         if (f_obj->complete_cmd(sc, f_obj, ECORE_F_CMD_STOP)) {
4384                                 break;
4385                         }
4386                         goto next_spqe;
4387                 }
4388
4389                 switch (opcode | sc->state) {
4390                 case (EVENT_RING_OPCODE_RSS_UPDATE_RULES | BNX2X_STATE_OPEN):
4391                 case (EVENT_RING_OPCODE_RSS_UPDATE_RULES | BNX2X_STATE_OPENING_WAITING_PORT):
4392                         cid =
4393                             elem->message.data.eth_event.echo & BNX2X_SWCID_MASK;
4394                         PMD_DRV_LOG(DEBUG, "got RSS_UPDATE ramrod. CID %d",
4395                                     cid);
4396                         rss_raw->clear_pending(rss_raw);
4397                         break;
4398
4399                 case (EVENT_RING_OPCODE_SET_MAC | BNX2X_STATE_OPEN):
4400                 case (EVENT_RING_OPCODE_SET_MAC | BNX2X_STATE_DIAG):
4401                 case (EVENT_RING_OPCODE_SET_MAC | BNX2X_STATE_CLOSING_WAITING_HALT):
4402                 case (EVENT_RING_OPCODE_CLASSIFICATION_RULES | BNX2X_STATE_OPEN):
4403                 case (EVENT_RING_OPCODE_CLASSIFICATION_RULES | BNX2X_STATE_DIAG):
4404                 case (EVENT_RING_OPCODE_CLASSIFICATION_RULES | BNX2X_STATE_CLOSING_WAITING_HALT):
4405                         PMD_DRV_LOG(DEBUG,
4406                                     "got (un)set mac ramrod");
4407                         bnx2x_handle_classification_eqe(sc, elem);
4408                         break;
4409
4410                 case (EVENT_RING_OPCODE_MULTICAST_RULES | BNX2X_STATE_OPEN):
4411                 case (EVENT_RING_OPCODE_MULTICAST_RULES | BNX2X_STATE_DIAG):
4412                 case (EVENT_RING_OPCODE_MULTICAST_RULES | BNX2X_STATE_CLOSING_WAITING_HALT):
4413                         PMD_DRV_LOG(DEBUG,
4414                                     "got mcast ramrod");
4415                         bnx2x_handle_mcast_eqe(sc);
4416                         break;
4417
4418                 case (EVENT_RING_OPCODE_FILTERS_RULES | BNX2X_STATE_OPEN):
4419                 case (EVENT_RING_OPCODE_FILTERS_RULES | BNX2X_STATE_DIAG):
4420                 case (EVENT_RING_OPCODE_FILTERS_RULES | BNX2X_STATE_CLOSING_WAITING_HALT):
4421                         PMD_DRV_LOG(DEBUG,
4422                                     "got rx_mode ramrod");
4423                         bnx2x_handle_rx_mode_eqe(sc);
4424                         break;
4425
4426                 default:
4427                         /* unknown event log error and continue */
4428                         PMD_DRV_LOG(INFO, "Unknown EQ event %d, sc->state 0x%x",
4429                                     elem->message.opcode, sc->state);
4430                 }
4431
4432 next_spqe:
4433                 spqe_cnt++;
4434         }                       /* for */
4435
4436         mb();
4437         atomic_add_acq_long(&sc->eq_spq_left, spqe_cnt);
4438
4439         sc->eq_cons = sw_cons;
4440         sc->eq_prod = sw_prod;
4441
4442         /* make sure that above mem writes were issued towards the memory */
4443         wmb();
4444
4445         /* update producer */
4446         bnx2x_update_eq_prod(sc, sc->eq_prod);
4447 }
4448
4449 static int bnx2x_handle_sp_tq(struct bnx2x_softc *sc)
4450 {
4451         uint16_t status;
4452         int rc = 0;
4453
4454         /* what work needs to be performed? */
4455         status = bnx2x_update_dsb_idx(sc);
4456
4457         /* HW attentions */
4458         if (status & BNX2X_DEF_SB_ATT_IDX) {
4459                 PMD_DRV_LOG(DEBUG, "---> ATTN INTR <---");
4460                 bnx2x_attn_int(sc);
4461                 status &= ~BNX2X_DEF_SB_ATT_IDX;
4462                 rc = 1;
4463         }
4464
4465         /* SP events: STAT_QUERY and others */
4466         if (status & BNX2X_DEF_SB_IDX) {
4467 /* handle EQ completions */
4468                 PMD_DEBUG_PERIODIC_LOG(DEBUG, "---> EQ INTR <---");
4469                 bnx2x_eq_int(sc);
4470                 bnx2x_ack_sb(sc, sc->igu_dsb_id, USTORM_ID,
4471                            le16toh(sc->def_idx), IGU_INT_NOP, 1);
4472                 status &= ~BNX2X_DEF_SB_IDX;
4473         }
4474
4475         /* if status is non zero then something went wrong */
4476         if (unlikely(status)) {
4477                 PMD_DRV_LOG(INFO,
4478                             "Got an unknown SP interrupt! (0x%04x)", status);
4479         }
4480
4481         /* ack status block only if something was actually handled */
4482         bnx2x_ack_sb(sc, sc->igu_dsb_id, ATTENTION_ID,
4483                    le16toh(sc->def_att_idx), IGU_INT_ENABLE, 1);
4484
4485         return rc;
4486 }
4487
4488 static void bnx2x_handle_fp_tq(struct bnx2x_fastpath *fp, int scan_fp)
4489 {
4490         struct bnx2x_softc *sc = fp->sc;
4491         uint8_t more_rx = FALSE;
4492
4493         PMD_DRV_LOG(DEBUG, "---> FP TASK QUEUE (%d) <--", fp->index);
4494
4495         /* update the fastpath index */
4496         bnx2x_update_fp_sb_idx(fp);
4497
4498         if (scan_fp) {
4499                 if (bnx2x_has_rx_work(fp)) {
4500                         more_rx = bnx2x_rxeof(sc, fp);
4501                 }
4502
4503                 if (more_rx) {
4504                         /* still more work to do */
4505                         bnx2x_handle_fp_tq(fp, scan_fp);
4506                         return;
4507                 }
4508         }
4509
4510         bnx2x_ack_sb(sc, fp->igu_sb_id, USTORM_ID,
4511                    le16toh(fp->fp_hc_idx), IGU_INT_ENABLE, 1);
4512 }
4513
4514 /*
4515  * Legacy interrupt entry point.
4516  *
4517  * Verifies that the controller generated the interrupt and
4518  * then calls a separate routine to handle the various
4519  * interrupt causes: link, RX, and TX.
4520  */
4521 int bnx2x_intr_legacy(struct bnx2x_softc *sc, int scan_fp)
4522 {
4523         struct bnx2x_fastpath *fp;
4524         uint32_t status, mask;
4525         int i, rc = 0;
4526
4527         /*
4528          * 0 for ustorm, 1 for cstorm
4529          * the bits returned from ack_int() are 0-15
4530          * bit 0 = attention status block
4531          * bit 1 = fast path status block
4532          * a mask of 0x2 or more = tx/rx event
4533          * a mask of 1 = slow path event
4534          */
4535
4536         status = bnx2x_ack_int(sc);
4537
4538         /* the interrupt is not for us */
4539         if (unlikely(status == 0)) {
4540                 return 0;
4541         }
4542
4543         PMD_DEBUG_PERIODIC_LOG(DEBUG, "Interrupt status 0x%04x", status);
4544         //bnx2x_dump_status_block(sc);
4545
4546         FOR_EACH_ETH_QUEUE(sc, i) {
4547                 fp = &sc->fp[i];
4548                 mask = (0x2 << (fp->index + CNIC_SUPPORT(sc)));
4549                 if (status & mask) {
4550                         bnx2x_handle_fp_tq(fp, scan_fp);
4551                         status &= ~mask;
4552                 }
4553         }
4554
4555         if (unlikely(status & 0x1)) {
4556                 rc = bnx2x_handle_sp_tq(sc);
4557                 status &= ~0x1;
4558         }
4559
4560         if (unlikely(status)) {
4561                 PMD_DRV_LOG(WARNING,
4562                             "Unexpected fastpath status (0x%08x)!", status);
4563         }
4564
4565         return rc;
4566 }
4567
4568 static int bnx2x_init_hw_common_chip(struct bnx2x_softc *sc);
4569 static int bnx2x_init_hw_common(struct bnx2x_softc *sc);
4570 static int bnx2x_init_hw_port(struct bnx2x_softc *sc);
4571 static int bnx2x_init_hw_func(struct bnx2x_softc *sc);
4572 static void bnx2x_reset_common(struct bnx2x_softc *sc);
4573 static void bnx2x_reset_port(struct bnx2x_softc *sc);
4574 static void bnx2x_reset_func(struct bnx2x_softc *sc);
4575 static int bnx2x_init_firmware(struct bnx2x_softc *sc);
4576 static void bnx2x_release_firmware(struct bnx2x_softc *sc);
4577
4578 static struct
4579 ecore_func_sp_drv_ops bnx2x_func_sp_drv = {
4580         .init_hw_cmn_chip = bnx2x_init_hw_common_chip,
4581         .init_hw_cmn = bnx2x_init_hw_common,
4582         .init_hw_port = bnx2x_init_hw_port,
4583         .init_hw_func = bnx2x_init_hw_func,
4584
4585         .reset_hw_cmn = bnx2x_reset_common,
4586         .reset_hw_port = bnx2x_reset_port,
4587         .reset_hw_func = bnx2x_reset_func,
4588
4589         .init_fw = bnx2x_init_firmware,
4590         .release_fw = bnx2x_release_firmware,
4591 };
4592
4593 static void bnx2x_init_func_obj(struct bnx2x_softc *sc)
4594 {
4595         sc->dmae_ready = 0;
4596
4597         PMD_INIT_FUNC_TRACE();
4598
4599         ecore_init_func_obj(sc,
4600                             &sc->func_obj,
4601                             BNX2X_SP(sc, func_rdata),
4602                             (rte_iova_t)BNX2X_SP_MAPPING(sc, func_rdata),
4603                             BNX2X_SP(sc, func_afex_rdata),
4604                             (rte_iova_t)BNX2X_SP_MAPPING(sc, func_afex_rdata),
4605                             &bnx2x_func_sp_drv);
4606 }
4607
4608 static int bnx2x_init_hw(struct bnx2x_softc *sc, uint32_t load_code)
4609 {
4610         struct ecore_func_state_params func_params = { NULL };
4611         int rc;
4612
4613         PMD_INIT_FUNC_TRACE();
4614
4615         /* prepare the parameters for function state transitions */
4616         bnx2x_set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags);
4617
4618         func_params.f_obj = &sc->func_obj;
4619         func_params.cmd = ECORE_F_CMD_HW_INIT;
4620
4621         func_params.params.hw_init.load_phase = load_code;
4622
4623         /*
4624          * Via a plethora of function pointers, we will eventually reach
4625          * bnx2x_init_hw_common(), bnx2x_init_hw_port(), or bnx2x_init_hw_func().
4626          */
4627         rc = ecore_func_state_change(sc, &func_params);
4628
4629         return rc;
4630 }
4631
4632 static void
4633 bnx2x_fill(struct bnx2x_softc *sc, uint32_t addr, int fill, uint32_t len)
4634 {
4635         uint32_t i;
4636
4637         if (!(len % 4) && !(addr % 4)) {
4638                 for (i = 0; i < len; i += 4) {
4639                         REG_WR(sc, (addr + i), fill);
4640                 }
4641         } else {
4642                 for (i = 0; i < len; i++) {
4643                         REG_WR8(sc, (addr + i), fill);
4644                 }
4645         }
4646 }
4647
4648 /* writes FP SP data to FW - data_size in dwords */
4649 static void
4650 bnx2x_wr_fp_sb_data(struct bnx2x_softc *sc, int fw_sb_id, uint32_t * sb_data_p,
4651                   uint32_t data_size)
4652 {
4653         uint32_t index;
4654
4655         for (index = 0; index < data_size; index++) {
4656                 REG_WR(sc,
4657                        (BAR_CSTRORM_INTMEM +
4658                         CSTORM_STATUS_BLOCK_DATA_OFFSET(fw_sb_id) +
4659                         (sizeof(uint32_t) * index)), *(sb_data_p + index));
4660         }
4661 }
4662
4663 static void bnx2x_zero_fp_sb(struct bnx2x_softc *sc, int fw_sb_id)
4664 {
4665         struct hc_status_block_data_e2 sb_data_e2;
4666         struct hc_status_block_data_e1x sb_data_e1x;
4667         uint32_t *sb_data_p;
4668         uint32_t data_size = 0;
4669
4670         if (!CHIP_IS_E1x(sc)) {
4671                 memset(&sb_data_e2, 0, sizeof(struct hc_status_block_data_e2));
4672                 sb_data_e2.common.state = SB_DISABLED;
4673                 sb_data_e2.common.p_func.vf_valid = FALSE;
4674                 sb_data_p = (uint32_t *) & sb_data_e2;
4675                 data_size = (sizeof(struct hc_status_block_data_e2) /
4676                              sizeof(uint32_t));
4677         } else {
4678                 memset(&sb_data_e1x, 0,
4679                        sizeof(struct hc_status_block_data_e1x));
4680                 sb_data_e1x.common.state = SB_DISABLED;
4681                 sb_data_e1x.common.p_func.vf_valid = FALSE;
4682                 sb_data_p = (uint32_t *) & sb_data_e1x;
4683                 data_size = (sizeof(struct hc_status_block_data_e1x) /
4684                              sizeof(uint32_t));
4685         }
4686
4687         bnx2x_wr_fp_sb_data(sc, fw_sb_id, sb_data_p, data_size);
4688
4689         bnx2x_fill(sc,
4690                  (BAR_CSTRORM_INTMEM + CSTORM_STATUS_BLOCK_OFFSET(fw_sb_id)), 0,
4691                  CSTORM_STATUS_BLOCK_SIZE);
4692         bnx2x_fill(sc, (BAR_CSTRORM_INTMEM + CSTORM_SYNC_BLOCK_OFFSET(fw_sb_id)),
4693                  0, CSTORM_SYNC_BLOCK_SIZE);
4694 }
4695
4696 static void
4697 bnx2x_wr_sp_sb_data(struct bnx2x_softc *sc,
4698                   struct hc_sp_status_block_data *sp_sb_data)
4699 {
4700         uint32_t i;
4701
4702         for (i = 0;
4703              i < (sizeof(struct hc_sp_status_block_data) / sizeof(uint32_t));
4704              i++) {
4705                 REG_WR(sc,
4706                        (BAR_CSTRORM_INTMEM +
4707                         CSTORM_SP_STATUS_BLOCK_DATA_OFFSET(SC_FUNC(sc)) +
4708                         (i * sizeof(uint32_t))),
4709                        *((uint32_t *) sp_sb_data + i));
4710         }
4711 }
4712
4713 static void bnx2x_zero_sp_sb(struct bnx2x_softc *sc)
4714 {
4715         struct hc_sp_status_block_data sp_sb_data;
4716
4717         memset(&sp_sb_data, 0, sizeof(struct hc_sp_status_block_data));
4718
4719         sp_sb_data.state = SB_DISABLED;
4720         sp_sb_data.p_func.vf_valid = FALSE;
4721
4722         bnx2x_wr_sp_sb_data(sc, &sp_sb_data);
4723
4724         bnx2x_fill(sc,
4725                  (BAR_CSTRORM_INTMEM +
4726                   CSTORM_SP_STATUS_BLOCK_OFFSET(SC_FUNC(sc))),
4727                  0, CSTORM_SP_STATUS_BLOCK_SIZE);
4728         bnx2x_fill(sc,
4729                  (BAR_CSTRORM_INTMEM +
4730                   CSTORM_SP_SYNC_BLOCK_OFFSET(SC_FUNC(sc))),
4731                  0, CSTORM_SP_SYNC_BLOCK_SIZE);
4732 }
4733
4734 static void
4735 bnx2x_setup_ndsb_state_machine(struct hc_status_block_sm *hc_sm, int igu_sb_id,
4736                              int igu_seg_id)
4737 {
4738         hc_sm->igu_sb_id = igu_sb_id;
4739         hc_sm->igu_seg_id = igu_seg_id;
4740         hc_sm->timer_value = 0xFF;
4741         hc_sm->time_to_expire = 0xFFFFFFFF;
4742 }
4743
4744 static void bnx2x_map_sb_state_machines(struct hc_index_data *index_data)
4745 {
4746         /* zero out state machine indices */
4747
4748         /* rx indices */
4749         index_data[HC_INDEX_ETH_RX_CQ_CONS].flags &= ~HC_INDEX_DATA_SM_ID;
4750
4751         /* tx indices */
4752         index_data[HC_INDEX_OOO_TX_CQ_CONS].flags &= ~HC_INDEX_DATA_SM_ID;
4753         index_data[HC_INDEX_ETH_TX_CQ_CONS_COS0].flags &= ~HC_INDEX_DATA_SM_ID;
4754         index_data[HC_INDEX_ETH_TX_CQ_CONS_COS1].flags &= ~HC_INDEX_DATA_SM_ID;
4755         index_data[HC_INDEX_ETH_TX_CQ_CONS_COS2].flags &= ~HC_INDEX_DATA_SM_ID;
4756
4757         /* map indices */
4758
4759         /* rx indices */
4760         index_data[HC_INDEX_ETH_RX_CQ_CONS].flags |=
4761             (SM_RX_ID << HC_INDEX_DATA_SM_ID_SHIFT);
4762
4763         /* tx indices */
4764         index_data[HC_INDEX_OOO_TX_CQ_CONS].flags |=
4765             (SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT);
4766         index_data[HC_INDEX_ETH_TX_CQ_CONS_COS0].flags |=
4767             (SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT);
4768         index_data[HC_INDEX_ETH_TX_CQ_CONS_COS1].flags |=
4769             (SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT);
4770         index_data[HC_INDEX_ETH_TX_CQ_CONS_COS2].flags |=
4771             (SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT);
4772 }
4773
4774 static void
4775 bnx2x_init_sb(struct bnx2x_softc *sc, rte_iova_t busaddr, int vfid,
4776             uint8_t vf_valid, int fw_sb_id, int igu_sb_id)
4777 {
4778         struct hc_status_block_data_e2 sb_data_e2;
4779         struct hc_status_block_data_e1x sb_data_e1x;
4780         struct hc_status_block_sm *hc_sm_p;
4781         uint32_t *sb_data_p;
4782         int igu_seg_id;
4783         int data_size;
4784
4785         if (CHIP_INT_MODE_IS_BC(sc)) {
4786                 igu_seg_id = HC_SEG_ACCESS_NORM;
4787         } else {
4788                 igu_seg_id = IGU_SEG_ACCESS_NORM;
4789         }
4790
4791         bnx2x_zero_fp_sb(sc, fw_sb_id);
4792
4793         if (!CHIP_IS_E1x(sc)) {
4794                 memset(&sb_data_e2, 0, sizeof(struct hc_status_block_data_e2));
4795                 sb_data_e2.common.state = SB_ENABLED;
4796                 sb_data_e2.common.p_func.pf_id = SC_FUNC(sc);
4797                 sb_data_e2.common.p_func.vf_id = vfid;
4798                 sb_data_e2.common.p_func.vf_valid = vf_valid;
4799                 sb_data_e2.common.p_func.vnic_id = SC_VN(sc);
4800                 sb_data_e2.common.same_igu_sb_1b = TRUE;
4801                 sb_data_e2.common.host_sb_addr.hi = U64_HI(busaddr);
4802                 sb_data_e2.common.host_sb_addr.lo = U64_LO(busaddr);
4803                 hc_sm_p = sb_data_e2.common.state_machine;
4804                 sb_data_p = (uint32_t *) & sb_data_e2;
4805                 data_size = (sizeof(struct hc_status_block_data_e2) /
4806                              sizeof(uint32_t));
4807                 bnx2x_map_sb_state_machines(sb_data_e2.index_data);
4808         } else {
4809                 memset(&sb_data_e1x, 0,
4810                        sizeof(struct hc_status_block_data_e1x));
4811                 sb_data_e1x.common.state = SB_ENABLED;
4812                 sb_data_e1x.common.p_func.pf_id = SC_FUNC(sc);
4813                 sb_data_e1x.common.p_func.vf_id = 0xff;
4814                 sb_data_e1x.common.p_func.vf_valid = FALSE;
4815                 sb_data_e1x.common.p_func.vnic_id = SC_VN(sc);
4816                 sb_data_e1x.common.same_igu_sb_1b = TRUE;
4817                 sb_data_e1x.common.host_sb_addr.hi = U64_HI(busaddr);
4818                 sb_data_e1x.common.host_sb_addr.lo = U64_LO(busaddr);
4819                 hc_sm_p = sb_data_e1x.common.state_machine;
4820                 sb_data_p = (uint32_t *) & sb_data_e1x;
4821                 data_size = (sizeof(struct hc_status_block_data_e1x) /
4822                              sizeof(uint32_t));
4823                 bnx2x_map_sb_state_machines(sb_data_e1x.index_data);
4824         }
4825
4826         bnx2x_setup_ndsb_state_machine(&hc_sm_p[SM_RX_ID], igu_sb_id, igu_seg_id);
4827         bnx2x_setup_ndsb_state_machine(&hc_sm_p[SM_TX_ID], igu_sb_id, igu_seg_id);
4828
4829         /* write indices to HW - PCI guarantees endianity of regpairs */
4830         bnx2x_wr_fp_sb_data(sc, fw_sb_id, sb_data_p, data_size);
4831 }
4832
4833 static uint8_t bnx2x_fp_qzone_id(struct bnx2x_fastpath *fp)
4834 {
4835         if (CHIP_IS_E1x(fp->sc)) {
4836                 return fp->cl_id + SC_PORT(fp->sc) * ETH_MAX_RX_CLIENTS_E1H;
4837         } else {
4838                 return fp->cl_id;
4839         }
4840 }
4841
4842 static uint32_t
4843 bnx2x_rx_ustorm_prods_offset(struct bnx2x_softc *sc, struct bnx2x_fastpath *fp)
4844 {
4845         uint32_t offset = BAR_USTRORM_INTMEM;
4846
4847         if (IS_VF(sc)) {
4848                 return PXP_VF_ADDR_USDM_QUEUES_START +
4849                         (sc->acquire_resp.resc.hw_qid[fp->index] *
4850                          sizeof(struct ustorm_queue_zone_data));
4851         } else if (!CHIP_IS_E1x(sc)) {
4852                 offset += USTORM_RX_PRODS_E2_OFFSET(fp->cl_qzone_id);
4853         } else {
4854                 offset += USTORM_RX_PRODS_E1X_OFFSET(SC_PORT(sc), fp->cl_id);
4855         }
4856
4857         return offset;
4858 }
4859
4860 static void bnx2x_init_eth_fp(struct bnx2x_softc *sc, int idx)
4861 {
4862         struct bnx2x_fastpath *fp = &sc->fp[idx];
4863         uint32_t cids[ECORE_MULTI_TX_COS] = { 0 };
4864         unsigned long q_type = 0;
4865         int cos;
4866
4867         fp->sc = sc;
4868         fp->index = idx;
4869
4870         fp->igu_sb_id = (sc->igu_base_sb + idx + CNIC_SUPPORT(sc));
4871         fp->fw_sb_id = (sc->base_fw_ndsb + idx + CNIC_SUPPORT(sc));
4872
4873         if (CHIP_IS_E1x(sc))
4874                 fp->cl_id = SC_L_ID(sc) + idx;
4875         else
4876 /* want client ID same as IGU SB ID for non-E1 */
4877                 fp->cl_id = fp->igu_sb_id;
4878         fp->cl_qzone_id = bnx2x_fp_qzone_id(fp);
4879
4880         /* setup sb indices */
4881         if (!CHIP_IS_E1x(sc)) {
4882                 fp->sb_index_values = fp->status_block.e2_sb->sb.index_values;
4883                 fp->sb_running_index = fp->status_block.e2_sb->sb.running_index;
4884         } else {
4885                 fp->sb_index_values = fp->status_block.e1x_sb->sb.index_values;
4886                 fp->sb_running_index =
4887                     fp->status_block.e1x_sb->sb.running_index;
4888         }
4889
4890         /* init shortcut */
4891         fp->ustorm_rx_prods_offset = bnx2x_rx_ustorm_prods_offset(sc, fp);
4892
4893         fp->rx_cq_cons_sb = &fp->sb_index_values[HC_INDEX_ETH_RX_CQ_CONS];
4894
4895         for (cos = 0; cos < sc->max_cos; cos++) {
4896                 cids[cos] = idx;
4897         }
4898         fp->tx_cons_sb = &fp->sb_index_values[HC_INDEX_ETH_TX_CQ_CONS_COS0];
4899
4900         /* nothing more for a VF to do */
4901         if (IS_VF(sc)) {
4902                 return;
4903         }
4904
4905         bnx2x_init_sb(sc, fp->sb_dma.paddr, BNX2X_VF_ID_INVALID, FALSE,
4906                     fp->fw_sb_id, fp->igu_sb_id);
4907
4908         bnx2x_update_fp_sb_idx(fp);
4909
4910         /* Configure Queue State object */
4911         bnx2x_set_bit(ECORE_Q_TYPE_HAS_RX, &q_type);
4912         bnx2x_set_bit(ECORE_Q_TYPE_HAS_TX, &q_type);
4913
4914         ecore_init_queue_obj(sc,
4915                              &sc->sp_objs[idx].q_obj,
4916                              fp->cl_id,
4917                              cids,
4918                              sc->max_cos,
4919                              SC_FUNC(sc),
4920                              BNX2X_SP(sc, q_rdata),
4921                              (rte_iova_t)BNX2X_SP_MAPPING(sc, q_rdata),
4922                              q_type);
4923
4924         /* configure classification DBs */
4925         ecore_init_mac_obj(sc,
4926                            &sc->sp_objs[idx].mac_obj,
4927                            fp->cl_id,
4928                            idx,
4929                            SC_FUNC(sc),
4930                            BNX2X_SP(sc, mac_rdata),
4931                            (rte_iova_t)BNX2X_SP_MAPPING(sc, mac_rdata),
4932                            ECORE_FILTER_MAC_PENDING, &sc->sp_state,
4933                            ECORE_OBJ_TYPE_RX_TX, &sc->macs_pool);
4934 }
4935
4936 static void
4937 bnx2x_update_rx_prod(struct bnx2x_softc *sc, struct bnx2x_fastpath *fp,
4938                    uint16_t rx_bd_prod, uint16_t rx_cq_prod)
4939 {
4940         union ustorm_eth_rx_producers rx_prods;
4941         uint32_t i;
4942
4943         /* update producers */
4944         rx_prods.prod.bd_prod = rx_bd_prod;
4945         rx_prods.prod.cqe_prod = rx_cq_prod;
4946         rx_prods.prod.reserved = 0;
4947
4948         /*
4949          * Make sure that the BD and SGE data is updated before updating the
4950          * producers since FW might read the BD/SGE right after the producer
4951          * is updated.
4952          * This is only applicable for weak-ordered memory model archs such
4953          * as IA-64. The following barrier is also mandatory since FW will
4954          * assumes BDs must have buffers.
4955          */
4956         wmb();
4957
4958         for (i = 0; i < (sizeof(rx_prods) / 4); i++) {
4959                 REG_WR(sc,
4960                        (fp->ustorm_rx_prods_offset + (i * 4)),
4961                        rx_prods.raw_data[i]);
4962         }
4963
4964         wmb();                  /* keep prod updates ordered */
4965 }
4966
4967 static void bnx2x_init_rx_rings(struct bnx2x_softc *sc)
4968 {
4969         struct bnx2x_fastpath *fp;
4970         int i;
4971         struct bnx2x_rx_queue *rxq;
4972
4973         for (i = 0; i < sc->num_queues; i++) {
4974                 fp = &sc->fp[i];
4975                 rxq = sc->rx_queues[fp->index];
4976                 if (!rxq) {
4977                         PMD_RX_LOG(ERR, "RX queue is NULL");
4978                         return;
4979                 }
4980
4981                 rxq->rx_bd_head = 0;
4982                 rxq->rx_bd_tail = rxq->nb_rx_desc;
4983                 rxq->rx_cq_head = 0;
4984                 rxq->rx_cq_tail = TOTAL_RCQ_ENTRIES(rxq);
4985                 *fp->rx_cq_cons_sb = 0;
4986
4987                 /*
4988                  * Activate the BD ring...
4989                  * Warning, this will generate an interrupt (to the TSTORM)
4990                  * so this can only be done after the chip is initialized
4991                  */
4992                 bnx2x_update_rx_prod(sc, fp, rxq->rx_bd_tail, rxq->rx_cq_tail);
4993
4994                 if (i != 0) {
4995                         continue;
4996                 }
4997         }
4998 }
4999
5000 static void bnx2x_init_tx_ring_one(struct bnx2x_fastpath *fp)
5001 {
5002         struct bnx2x_tx_queue *txq = fp->sc->tx_queues[fp->index];
5003
5004         fp->tx_db.data.header.header = 1 << DOORBELL_HDR_DB_TYPE_SHIFT;
5005         fp->tx_db.data.zero_fill1 = 0;
5006         fp->tx_db.data.prod = 0;
5007
5008         if (!txq) {
5009                 PMD_TX_LOG(ERR, "ERROR: TX queue is NULL");
5010                 return;
5011         }
5012
5013         txq->tx_pkt_tail = 0;
5014         txq->tx_pkt_head = 0;
5015         txq->tx_bd_tail = 0;
5016         txq->tx_bd_head = 0;
5017 }
5018
5019 static void bnx2x_init_tx_rings(struct bnx2x_softc *sc)
5020 {
5021         int i;
5022
5023         for (i = 0; i < sc->num_queues; i++) {
5024                 bnx2x_init_tx_ring_one(&sc->fp[i]);
5025         }
5026 }
5027
5028 static void bnx2x_init_def_sb(struct bnx2x_softc *sc)
5029 {
5030         struct host_sp_status_block *def_sb = sc->def_sb;
5031         rte_iova_t mapping = sc->def_sb_dma.paddr;
5032         int igu_sp_sb_index;
5033         int igu_seg_id;
5034         int port = SC_PORT(sc);
5035         int func = SC_FUNC(sc);
5036         int reg_offset, reg_offset_en5;
5037         uint64_t section;
5038         int index, sindex;
5039         struct hc_sp_status_block_data sp_sb_data;
5040
5041         memset(&sp_sb_data, 0, sizeof(struct hc_sp_status_block_data));
5042
5043         if (CHIP_INT_MODE_IS_BC(sc)) {
5044                 igu_sp_sb_index = DEF_SB_IGU_ID;
5045                 igu_seg_id = HC_SEG_ACCESS_DEF;
5046         } else {
5047                 igu_sp_sb_index = sc->igu_dsb_id;
5048                 igu_seg_id = IGU_SEG_ACCESS_DEF;
5049         }
5050
5051         /* attentions */
5052         section = ((uint64_t) mapping +
5053                    offsetof(struct host_sp_status_block, atten_status_block));
5054         def_sb->atten_status_block.status_block_id = igu_sp_sb_index;
5055         sc->attn_state = 0;
5056
5057         reg_offset = (port) ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 :
5058             MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0;
5059
5060         reg_offset_en5 = (port) ? MISC_REG_AEU_ENABLE5_FUNC_1_OUT_0 :
5061             MISC_REG_AEU_ENABLE5_FUNC_0_OUT_0;
5062
5063         for (index = 0; index < MAX_DYNAMIC_ATTN_GRPS; index++) {
5064 /* take care of sig[0]..sig[4] */
5065                 for (sindex = 0; sindex < 4; sindex++) {
5066                         sc->attn_group[index].sig[sindex] =
5067                             REG_RD(sc,
5068                                    (reg_offset + (sindex * 0x4) +
5069                                     (0x10 * index)));
5070                 }
5071
5072                 if (!CHIP_IS_E1x(sc)) {
5073                         /*
5074                          * enable5 is separate from the rest of the registers,
5075                          * and the address skip is 4 and not 16 between the
5076                          * different groups
5077                          */
5078                         sc->attn_group[index].sig[4] =
5079                             REG_RD(sc, (reg_offset_en5 + (0x4 * index)));
5080                 } else {
5081                         sc->attn_group[index].sig[4] = 0;
5082                 }
5083         }
5084
5085         if (sc->devinfo.int_block == INT_BLOCK_HC) {
5086                 reg_offset =
5087                     port ? HC_REG_ATTN_MSG1_ADDR_L : HC_REG_ATTN_MSG0_ADDR_L;
5088                 REG_WR(sc, reg_offset, U64_LO(section));
5089                 REG_WR(sc, (reg_offset + 4), U64_HI(section));
5090         } else if (!CHIP_IS_E1x(sc)) {
5091                 REG_WR(sc, IGU_REG_ATTN_MSG_ADDR_L, U64_LO(section));
5092                 REG_WR(sc, IGU_REG_ATTN_MSG_ADDR_H, U64_HI(section));
5093         }
5094
5095         section = ((uint64_t) mapping +
5096                    offsetof(struct host_sp_status_block, sp_sb));
5097
5098         bnx2x_zero_sp_sb(sc);
5099
5100         /* PCI guarantees endianity of regpair */
5101         sp_sb_data.state = SB_ENABLED;
5102         sp_sb_data.host_sb_addr.lo = U64_LO(section);
5103         sp_sb_data.host_sb_addr.hi = U64_HI(section);
5104         sp_sb_data.igu_sb_id = igu_sp_sb_index;
5105         sp_sb_data.igu_seg_id = igu_seg_id;
5106         sp_sb_data.p_func.pf_id = func;
5107         sp_sb_data.p_func.vnic_id = SC_VN(sc);
5108         sp_sb_data.p_func.vf_id = 0xff;
5109
5110         bnx2x_wr_sp_sb_data(sc, &sp_sb_data);
5111
5112         bnx2x_ack_sb(sc, sc->igu_dsb_id, USTORM_ID, 0, IGU_INT_ENABLE, 0);
5113 }
5114
5115 static void bnx2x_init_sp_ring(struct bnx2x_softc *sc)
5116 {
5117         atomic_store_rel_long(&sc->cq_spq_left, MAX_SPQ_PENDING);
5118         sc->spq_prod_idx = 0;
5119         sc->dsb_sp_prod =
5120             &sc->def_sb->sp_sb.index_values[HC_SP_INDEX_ETH_DEF_CONS];
5121         sc->spq_prod_bd = sc->spq;
5122         sc->spq_last_bd = (sc->spq_prod_bd + MAX_SP_DESC_CNT);
5123 }
5124
5125 static void bnx2x_init_eq_ring(struct bnx2x_softc *sc)
5126 {
5127         union event_ring_elem *elem;
5128         int i;
5129
5130         for (i = 1; i <= NUM_EQ_PAGES; i++) {
5131                 elem = &sc->eq[EQ_DESC_CNT_PAGE * i - 1];
5132
5133                 elem->next_page.addr.hi = htole32(U64_HI(sc->eq_dma.paddr +
5134                                                          BNX2X_PAGE_SIZE *
5135                                                          (i % NUM_EQ_PAGES)));
5136                 elem->next_page.addr.lo = htole32(U64_LO(sc->eq_dma.paddr +
5137                                                          BNX2X_PAGE_SIZE *
5138                                                          (i % NUM_EQ_PAGES)));
5139         }
5140
5141         sc->eq_cons = 0;
5142         sc->eq_prod = NUM_EQ_DESC;
5143         sc->eq_cons_sb = &sc->def_sb->sp_sb.index_values[HC_SP_INDEX_EQ_CONS];
5144
5145         atomic_store_rel_long(&sc->eq_spq_left,
5146                               (min((MAX_SP_DESC_CNT - MAX_SPQ_PENDING),
5147                                    NUM_EQ_DESC) - 1));
5148 }
5149
5150 static void bnx2x_init_internal_common(struct bnx2x_softc *sc)
5151 {
5152         int i;
5153
5154         if (IS_MF_SI(sc)) {
5155 /*
5156  * In switch independent mode, the TSTORM needs to accept
5157  * packets that failed classification, since approximate match
5158  * mac addresses aren't written to NIG LLH.
5159  */
5160                 REG_WR8(sc,
5161                         (BAR_TSTRORM_INTMEM +
5162                          TSTORM_ACCEPT_CLASSIFY_FAILED_OFFSET), 2);
5163         } else
5164                 REG_WR8(sc,
5165                         (BAR_TSTRORM_INTMEM +
5166                          TSTORM_ACCEPT_CLASSIFY_FAILED_OFFSET), 0);
5167
5168         /*
5169          * Zero this manually as its initialization is currently missing
5170          * in the initTool.
5171          */
5172         for (i = 0; i < (USTORM_AGG_DATA_SIZE >> 2); i++) {
5173                 REG_WR(sc,
5174                        (BAR_USTRORM_INTMEM + USTORM_AGG_DATA_OFFSET + (i * 4)),
5175                        0);
5176         }
5177
5178         if (!CHIP_IS_E1x(sc)) {
5179                 REG_WR8(sc, (BAR_CSTRORM_INTMEM + CSTORM_IGU_MODE_OFFSET),
5180                         CHIP_INT_MODE_IS_BC(sc) ? HC_IGU_BC_MODE :
5181                         HC_IGU_NBC_MODE);
5182         }
5183 }
5184
5185 static void bnx2x_init_internal(struct bnx2x_softc *sc, uint32_t load_code)
5186 {
5187         switch (load_code) {
5188         case FW_MSG_CODE_DRV_LOAD_COMMON:
5189         case FW_MSG_CODE_DRV_LOAD_COMMON_CHIP:
5190                 bnx2x_init_internal_common(sc);
5191                 /* no break */
5192
5193         case FW_MSG_CODE_DRV_LOAD_PORT:
5194                 /* nothing to do */
5195                 /* no break */
5196
5197         case FW_MSG_CODE_DRV_LOAD_FUNCTION:
5198                 /* internal memory per function is initialized inside bnx2x_pf_init */
5199                 break;
5200
5201         default:
5202                 PMD_DRV_LOG(NOTICE, "Unknown load_code (0x%x) from MCP",
5203                             load_code);
5204                 break;
5205         }
5206 }
5207
5208 static void
5209 storm_memset_func_cfg(struct bnx2x_softc *sc,
5210                       struct tstorm_eth_function_common_config *tcfg,
5211                       uint16_t abs_fid)
5212 {
5213         uint32_t addr;
5214         size_t size;
5215
5216         addr = (BAR_TSTRORM_INTMEM +
5217                 TSTORM_FUNCTION_COMMON_CONFIG_OFFSET(abs_fid));
5218         size = sizeof(struct tstorm_eth_function_common_config);
5219         ecore_storm_memset_struct(sc, addr, size, (uint32_t *) tcfg);
5220 }
5221
5222 static void bnx2x_func_init(struct bnx2x_softc *sc, struct bnx2x_func_init_params *p)
5223 {
5224         struct tstorm_eth_function_common_config tcfg = { 0 };
5225
5226         if (CHIP_IS_E1x(sc)) {
5227                 storm_memset_func_cfg(sc, &tcfg, p->func_id);
5228         }
5229
5230         /* Enable the function in the FW */
5231         storm_memset_vf_to_pf(sc, p->func_id, p->pf_id);
5232         storm_memset_func_en(sc, p->func_id, 1);
5233
5234         /* spq */
5235         if (p->func_flgs & FUNC_FLG_SPQ) {
5236                 storm_memset_spq_addr(sc, p->spq_map, p->func_id);
5237                 REG_WR(sc,
5238                        (XSEM_REG_FAST_MEMORY +
5239                         XSTORM_SPQ_PROD_OFFSET(p->func_id)), p->spq_prod);
5240         }
5241 }
5242
5243 /*
5244  * Calculates the sum of vn_min_rates.
5245  * It's needed for further normalizing of the min_rates.
5246  * Returns:
5247  *   sum of vn_min_rates.
5248  *     or
5249  *   0 - if all the min_rates are 0.
5250  * In the later case fainess algorithm should be deactivated.
5251  * If all min rates are not zero then those that are zeroes will be set to 1.
5252  */
5253 static void bnx2x_calc_vn_min(struct bnx2x_softc *sc, struct cmng_init_input *input)
5254 {
5255         uint32_t vn_cfg;
5256         uint32_t vn_min_rate;
5257         int all_zero = 1;
5258         int vn;
5259
5260         for (vn = VN_0; vn < SC_MAX_VN_NUM(sc); vn++) {
5261                 vn_cfg = sc->devinfo.mf_info.mf_config[vn];
5262                 vn_min_rate = (((vn_cfg & FUNC_MF_CFG_MIN_BW_MASK) >>
5263                                 FUNC_MF_CFG_MIN_BW_SHIFT) * 100);
5264
5265                 if (vn_cfg & FUNC_MF_CFG_FUNC_HIDE) {
5266                         /* skip hidden VNs */
5267                         vn_min_rate = 0;
5268                 } else if (!vn_min_rate) {
5269                         /* If min rate is zero - set it to 100 */
5270                         vn_min_rate = DEF_MIN_RATE;
5271                 } else {
5272                         all_zero = 0;
5273                 }
5274
5275                 input->vnic_min_rate[vn] = vn_min_rate;
5276         }
5277
5278         /* if ETS or all min rates are zeros - disable fairness */
5279         if (all_zero) {
5280                 input->flags.cmng_enables &= ~CMNG_FLAGS_PER_PORT_FAIRNESS_VN;
5281         } else {
5282                 input->flags.cmng_enables |= CMNG_FLAGS_PER_PORT_FAIRNESS_VN;
5283         }
5284 }
5285
5286 static uint16_t
5287 bnx2x_extract_max_cfg(__rte_unused struct bnx2x_softc *sc, uint32_t mf_cfg)
5288 {
5289         uint16_t max_cfg = ((mf_cfg & FUNC_MF_CFG_MAX_BW_MASK) >>
5290                             FUNC_MF_CFG_MAX_BW_SHIFT);
5291
5292         if (!max_cfg) {
5293                 PMD_DRV_LOG(DEBUG,
5294                             "Max BW configured to 0 - using 100 instead");
5295                 max_cfg = 100;
5296         }
5297
5298         return max_cfg;
5299 }
5300
5301 static void
5302 bnx2x_calc_vn_max(struct bnx2x_softc *sc, int vn, struct cmng_init_input *input)
5303 {
5304         uint16_t vn_max_rate;
5305         uint32_t vn_cfg = sc->devinfo.mf_info.mf_config[vn];
5306         uint32_t max_cfg;
5307
5308         if (vn_cfg & FUNC_MF_CFG_FUNC_HIDE) {
5309                 vn_max_rate = 0;
5310         } else {
5311                 max_cfg = bnx2x_extract_max_cfg(sc, vn_cfg);
5312
5313                 if (IS_MF_SI(sc)) {
5314                         /* max_cfg in percents of linkspeed */
5315                         vn_max_rate =
5316                             ((sc->link_vars.line_speed * max_cfg) / 100);
5317                 } else {        /* SD modes */
5318                         /* max_cfg is absolute in 100Mb units */
5319                         vn_max_rate = (max_cfg * 100);
5320                 }
5321         }
5322
5323         input->vnic_max_rate[vn] = vn_max_rate;
5324 }
5325
5326 static void
5327 bnx2x_cmng_fns_init(struct bnx2x_softc *sc, uint8_t read_cfg, uint8_t cmng_type)
5328 {
5329         struct cmng_init_input input;
5330         int vn;
5331
5332         memset(&input, 0, sizeof(struct cmng_init_input));
5333
5334         input.port_rate = sc->link_vars.line_speed;
5335
5336         if (cmng_type == CMNG_FNS_MINMAX) {
5337 /* read mf conf from shmem */
5338                 if (read_cfg) {
5339                         bnx2x_read_mf_cfg(sc);
5340                 }
5341
5342 /* get VN min rate and enable fairness if not 0 */
5343                 bnx2x_calc_vn_min(sc, &input);
5344
5345 /* get VN max rate */
5346                 if (sc->port.pmf) {
5347                         for (vn = VN_0; vn < SC_MAX_VN_NUM(sc); vn++) {
5348                                 bnx2x_calc_vn_max(sc, vn, &input);
5349                         }
5350                 }
5351
5352 /* always enable rate shaping and fairness */
5353                 input.flags.cmng_enables |= CMNG_FLAGS_PER_PORT_RATE_SHAPING_VN;
5354
5355                 ecore_init_cmng(&input, &sc->cmng);
5356                 return;
5357         }
5358 }
5359
5360 static int bnx2x_get_cmng_fns_mode(struct bnx2x_softc *sc)
5361 {
5362         if (CHIP_REV_IS_SLOW(sc)) {
5363                 return CMNG_FNS_NONE;
5364         }
5365
5366         if (IS_MF(sc)) {
5367                 return CMNG_FNS_MINMAX;
5368         }
5369
5370         return CMNG_FNS_NONE;
5371 }
5372
5373 static void
5374 storm_memset_cmng(struct bnx2x_softc *sc, struct cmng_init *cmng, uint8_t port)
5375 {
5376         int vn;
5377         int func;
5378         uint32_t addr;
5379         size_t size;
5380
5381         addr = (BAR_XSTRORM_INTMEM + XSTORM_CMNG_PER_PORT_VARS_OFFSET(port));
5382         size = sizeof(struct cmng_struct_per_port);
5383         ecore_storm_memset_struct(sc, addr, size, (uint32_t *) & cmng->port);
5384
5385         for (vn = VN_0; vn < SC_MAX_VN_NUM(sc); vn++) {
5386                 func = func_by_vn(sc, vn);
5387
5388                 addr = (BAR_XSTRORM_INTMEM +
5389                         XSTORM_RATE_SHAPING_PER_VN_VARS_OFFSET(func));
5390                 size = sizeof(struct rate_shaping_vars_per_vn);
5391                 ecore_storm_memset_struct(sc, addr, size,
5392                                           (uint32_t *) & cmng->
5393                                           vnic.vnic_max_rate[vn]);
5394
5395                 addr = (BAR_XSTRORM_INTMEM +
5396                         XSTORM_FAIRNESS_PER_VN_VARS_OFFSET(func));
5397                 size = sizeof(struct fairness_vars_per_vn);
5398                 ecore_storm_memset_struct(sc, addr, size,
5399                                           (uint32_t *) & cmng->
5400                                           vnic.vnic_min_rate[vn]);
5401         }
5402 }
5403
5404 static void bnx2x_pf_init(struct bnx2x_softc *sc)
5405 {
5406         struct bnx2x_func_init_params func_init;
5407         struct event_ring_data eq_data;
5408         uint16_t flags;
5409
5410         memset(&eq_data, 0, sizeof(struct event_ring_data));
5411         memset(&func_init, 0, sizeof(struct bnx2x_func_init_params));
5412
5413         if (!CHIP_IS_E1x(sc)) {
5414 /* reset IGU PF statistics: MSIX + ATTN */
5415 /* PF */
5416                 REG_WR(sc,
5417                        (IGU_REG_STATISTIC_NUM_MESSAGE_SENT +
5418                         (BNX2X_IGU_STAS_MSG_VF_CNT * 4) +
5419                         ((CHIP_IS_MODE_4_PORT(sc) ? SC_FUNC(sc) : SC_VN(sc)) *
5420                          4)), 0);
5421 /* ATTN */
5422                 REG_WR(sc,
5423                        (IGU_REG_STATISTIC_NUM_MESSAGE_SENT +
5424                         (BNX2X_IGU_STAS_MSG_VF_CNT * 4) +
5425                         (BNX2X_IGU_STAS_MSG_PF_CNT * 4) +
5426                         ((CHIP_IS_MODE_4_PORT(sc) ? SC_FUNC(sc) : SC_VN(sc)) *
5427                          4)), 0);
5428         }
5429
5430         /* function setup flags */
5431         flags = (FUNC_FLG_STATS | FUNC_FLG_LEADING | FUNC_FLG_SPQ);
5432
5433         func_init.func_flgs = flags;
5434         func_init.pf_id = SC_FUNC(sc);
5435         func_init.func_id = SC_FUNC(sc);
5436         func_init.spq_map = sc->spq_dma.paddr;
5437         func_init.spq_prod = sc->spq_prod_idx;
5438
5439         bnx2x_func_init(sc, &func_init);
5440
5441         memset(&sc->cmng, 0, sizeof(struct cmng_struct_per_port));
5442
5443         /*
5444          * Congestion management values depend on the link rate.
5445          * There is no active link so initial link rate is set to 10Gbps.
5446          * When the link comes up the congestion management values are
5447          * re-calculated according to the actual link rate.
5448          */
5449         sc->link_vars.line_speed = SPEED_10000;
5450         bnx2x_cmng_fns_init(sc, TRUE, bnx2x_get_cmng_fns_mode(sc));
5451
5452         /* Only the PMF sets the HW */
5453         if (sc->port.pmf) {
5454                 storm_memset_cmng(sc, &sc->cmng, SC_PORT(sc));
5455         }
5456
5457         /* init Event Queue - PCI bus guarantees correct endainity */
5458         eq_data.base_addr.hi = U64_HI(sc->eq_dma.paddr);
5459         eq_data.base_addr.lo = U64_LO(sc->eq_dma.paddr);
5460         eq_data.producer = sc->eq_prod;
5461         eq_data.index_id = HC_SP_INDEX_EQ_CONS;
5462         eq_data.sb_id = DEF_SB_ID;
5463         storm_memset_eq_data(sc, &eq_data, SC_FUNC(sc));
5464 }
5465
5466 static void bnx2x_hc_int_enable(struct bnx2x_softc *sc)
5467 {
5468         int port = SC_PORT(sc);
5469         uint32_t addr = (port) ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0;
5470         uint32_t val = REG_RD(sc, addr);
5471         uint8_t msix = (sc->interrupt_mode == INTR_MODE_MSIX)
5472             || (sc->interrupt_mode == INTR_MODE_SINGLE_MSIX);
5473         uint8_t single_msix = (sc->interrupt_mode == INTR_MODE_SINGLE_MSIX);
5474         uint8_t msi = (sc->interrupt_mode == INTR_MODE_MSI);
5475
5476         if (msix) {
5477                 val &= ~(HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
5478                          HC_CONFIG_0_REG_INT_LINE_EN_0);
5479                 val |= (HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
5480                         HC_CONFIG_0_REG_ATTN_BIT_EN_0);
5481                 if (single_msix) {
5482                         val |= HC_CONFIG_0_REG_SINGLE_ISR_EN_0;
5483                 }
5484         } else if (msi) {
5485                 val &= ~HC_CONFIG_0_REG_INT_LINE_EN_0;
5486                 val |= (HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
5487                         HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
5488                         HC_CONFIG_0_REG_ATTN_BIT_EN_0);
5489         } else {
5490                 val |= (HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
5491                         HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
5492                         HC_CONFIG_0_REG_INT_LINE_EN_0 |
5493                         HC_CONFIG_0_REG_ATTN_BIT_EN_0);
5494
5495                 REG_WR(sc, addr, val);
5496
5497                 val &= ~HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0;
5498         }
5499
5500         REG_WR(sc, addr, val);
5501
5502         /* ensure that HC_CONFIG is written before leading/trailing edge config */
5503         mb();
5504
5505         /* init leading/trailing edge */
5506         if (IS_MF(sc)) {
5507                 val = (0xee0f | (1 << (SC_VN(sc) + 4)));
5508                 if (sc->port.pmf) {
5509                         /* enable nig and gpio3 attention */
5510                         val |= 0x1100;
5511                 }
5512         } else {
5513                 val = 0xffff;
5514         }
5515
5516         REG_WR(sc, (HC_REG_TRAILING_EDGE_0 + port * 8), val);
5517         REG_WR(sc, (HC_REG_LEADING_EDGE_0 + port * 8), val);
5518
5519         /* make sure that interrupts are indeed enabled from here on */
5520         mb();
5521 }
5522
5523 static void bnx2x_igu_int_enable(struct bnx2x_softc *sc)
5524 {
5525         uint32_t val;
5526         uint8_t msix = (sc->interrupt_mode == INTR_MODE_MSIX)
5527             || (sc->interrupt_mode == INTR_MODE_SINGLE_MSIX);
5528         uint8_t single_msix = (sc->interrupt_mode == INTR_MODE_SINGLE_MSIX);
5529         uint8_t msi = (sc->interrupt_mode == INTR_MODE_MSI);
5530
5531         val = REG_RD(sc, IGU_REG_PF_CONFIGURATION);
5532
5533         if (msix) {
5534                 val &= ~(IGU_PF_CONF_INT_LINE_EN | IGU_PF_CONF_SINGLE_ISR_EN);
5535                 val |= (IGU_PF_CONF_MSI_MSIX_EN | IGU_PF_CONF_ATTN_BIT_EN);
5536                 if (single_msix) {
5537                         val |= IGU_PF_CONF_SINGLE_ISR_EN;
5538                 }
5539         } else if (msi) {
5540                 val &= ~IGU_PF_CONF_INT_LINE_EN;
5541                 val |= (IGU_PF_CONF_MSI_MSIX_EN |
5542                         IGU_PF_CONF_ATTN_BIT_EN | IGU_PF_CONF_SINGLE_ISR_EN);
5543         } else {
5544                 val &= ~IGU_PF_CONF_MSI_MSIX_EN;
5545                 val |= (IGU_PF_CONF_INT_LINE_EN |
5546                         IGU_PF_CONF_ATTN_BIT_EN | IGU_PF_CONF_SINGLE_ISR_EN);
5547         }
5548
5549         /* clean previous status - need to configure igu prior to ack */
5550         if ((!msix) || single_msix) {
5551                 REG_WR(sc, IGU_REG_PF_CONFIGURATION, val);
5552                 bnx2x_ack_int(sc);
5553         }
5554
5555         val |= IGU_PF_CONF_FUNC_EN;
5556
5557         PMD_DRV_LOG(DEBUG, "write 0x%x to IGU mode %s",
5558                     val, ((msix) ? "MSI-X" : ((msi) ? "MSI" : "INTx")));
5559
5560         REG_WR(sc, IGU_REG_PF_CONFIGURATION, val);
5561
5562         mb();
5563
5564         /* init leading/trailing edge */
5565         if (IS_MF(sc)) {
5566                 val = (0xee0f | (1 << (SC_VN(sc) + 4)));
5567                 if (sc->port.pmf) {
5568                         /* enable nig and gpio3 attention */
5569                         val |= 0x1100;
5570                 }
5571         } else {
5572                 val = 0xffff;
5573         }
5574
5575         REG_WR(sc, IGU_REG_TRAILING_EDGE_LATCH, val);
5576         REG_WR(sc, IGU_REG_LEADING_EDGE_LATCH, val);
5577
5578         /* make sure that interrupts are indeed enabled from here on */
5579         mb();
5580 }
5581
5582 static void bnx2x_int_enable(struct bnx2x_softc *sc)
5583 {
5584         if (sc->devinfo.int_block == INT_BLOCK_HC) {
5585                 bnx2x_hc_int_enable(sc);
5586         } else {
5587                 bnx2x_igu_int_enable(sc);
5588         }
5589 }
5590
5591 static void bnx2x_hc_int_disable(struct bnx2x_softc *sc)
5592 {
5593         int port = SC_PORT(sc);
5594         uint32_t addr = (port) ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0;
5595         uint32_t val = REG_RD(sc, addr);
5596
5597         val &= ~(HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
5598                  HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
5599                  HC_CONFIG_0_REG_INT_LINE_EN_0 | HC_CONFIG_0_REG_ATTN_BIT_EN_0);
5600         /* flush all outstanding writes */
5601         mb();
5602
5603         REG_WR(sc, addr, val);
5604         if (REG_RD(sc, addr) != val) {
5605                 PMD_DRV_LOG(ERR, "proper val not read from HC IGU!");
5606         }
5607 }
5608
5609 static void bnx2x_igu_int_disable(struct bnx2x_softc *sc)
5610 {
5611         uint32_t val = REG_RD(sc, IGU_REG_PF_CONFIGURATION);
5612
5613         val &= ~(IGU_PF_CONF_MSI_MSIX_EN |
5614                  IGU_PF_CONF_INT_LINE_EN | IGU_PF_CONF_ATTN_BIT_EN);
5615
5616         PMD_DRV_LOG(DEBUG, "write %x to IGU", val);
5617
5618         /* flush all outstanding writes */
5619         mb();
5620
5621         REG_WR(sc, IGU_REG_PF_CONFIGURATION, val);
5622         if (REG_RD(sc, IGU_REG_PF_CONFIGURATION) != val) {
5623                 PMD_DRV_LOG(ERR, "proper val not read from IGU!");
5624         }
5625 }
5626
5627 static void bnx2x_int_disable(struct bnx2x_softc *sc)
5628 {
5629         if (sc->devinfo.int_block == INT_BLOCK_HC) {
5630                 bnx2x_hc_int_disable(sc);
5631         } else {
5632                 bnx2x_igu_int_disable(sc);
5633         }
5634 }
5635
5636 static void bnx2x_nic_init(struct bnx2x_softc *sc, int load_code)
5637 {
5638         int i;
5639
5640         PMD_INIT_FUNC_TRACE();
5641
5642         for (i = 0; i < sc->num_queues; i++) {
5643                 bnx2x_init_eth_fp(sc, i);
5644         }
5645
5646         rmb();                  /* ensure status block indices were read */
5647
5648         bnx2x_init_rx_rings(sc);
5649         bnx2x_init_tx_rings(sc);
5650
5651         if (IS_VF(sc)) {
5652                 bnx2x_memset_stats(sc);
5653                 return;
5654         }
5655
5656         /* initialize MOD_ABS interrupts */
5657         elink_init_mod_abs_int(sc, &sc->link_vars,
5658                                sc->devinfo.chip_id,
5659                                sc->devinfo.shmem_base,
5660                                sc->devinfo.shmem2_base, SC_PORT(sc));
5661
5662         bnx2x_init_def_sb(sc);
5663         bnx2x_update_dsb_idx(sc);
5664         bnx2x_init_sp_ring(sc);
5665         bnx2x_init_eq_ring(sc);
5666         bnx2x_init_internal(sc, load_code);
5667         bnx2x_pf_init(sc);
5668         bnx2x_stats_init(sc);
5669
5670         /* flush all before enabling interrupts */
5671         mb();
5672
5673         bnx2x_int_enable(sc);
5674
5675         /* check for SPIO5 */
5676         bnx2x_attn_int_deasserted0(sc,
5677                                  REG_RD(sc,
5678                                         (MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 +
5679                                          SC_PORT(sc) * 4)) &
5680                                  AEU_INPUTS_ATTN_BITS_SPIO5);
5681 }
5682
5683 static void bnx2x_init_objs(struct bnx2x_softc *sc)
5684 {
5685         /* mcast rules must be added to tx if tx switching is enabled */
5686         ecore_obj_type o_type;
5687         if (sc->flags & BNX2X_TX_SWITCHING)
5688                 o_type = ECORE_OBJ_TYPE_RX_TX;
5689         else
5690                 o_type = ECORE_OBJ_TYPE_RX;
5691
5692         /* RX_MODE controlling object */
5693         ecore_init_rx_mode_obj(sc, &sc->rx_mode_obj);
5694
5695         /* multicast configuration controlling object */
5696         ecore_init_mcast_obj(sc,
5697                              &sc->mcast_obj,
5698                              sc->fp[0].cl_id,
5699                              sc->fp[0].index,
5700                              SC_FUNC(sc),
5701                              SC_FUNC(sc),
5702                              BNX2X_SP(sc, mcast_rdata),
5703                              (rte_iova_t)BNX2X_SP_MAPPING(sc, mcast_rdata),
5704                              ECORE_FILTER_MCAST_PENDING,
5705                              &sc->sp_state, o_type);
5706
5707         /* Setup CAM credit pools */
5708         ecore_init_mac_credit_pool(sc,
5709                                    &sc->macs_pool,
5710                                    SC_FUNC(sc),
5711                                    CHIP_IS_E1x(sc) ? VNICS_PER_PORT(sc) :
5712                                    VNICS_PER_PATH(sc));
5713
5714         ecore_init_vlan_credit_pool(sc,
5715                                     &sc->vlans_pool,
5716                                     SC_ABS_FUNC(sc) >> 1,
5717                                     CHIP_IS_E1x(sc) ? VNICS_PER_PORT(sc) :
5718                                     VNICS_PER_PATH(sc));
5719
5720         /* RSS configuration object */
5721         ecore_init_rss_config_obj(&sc->rss_conf_obj,
5722                                   sc->fp[0].cl_id,
5723                                   sc->fp[0].index,
5724                                   SC_FUNC(sc),
5725                                   SC_FUNC(sc),
5726                                   BNX2X_SP(sc, rss_rdata),
5727                                   (rte_iova_t)BNX2X_SP_MAPPING(sc, rss_rdata),
5728                                   ECORE_FILTER_RSS_CONF_PENDING,
5729                                   &sc->sp_state, ECORE_OBJ_TYPE_RX);
5730 }
5731
5732 /*
5733  * Initialize the function. This must be called before sending CLIENT_SETUP
5734  * for the first client.
5735  */
5736 static int bnx2x_func_start(struct bnx2x_softc *sc)
5737 {
5738         struct ecore_func_state_params func_params = { NULL };
5739         struct ecore_func_start_params *start_params =
5740             &func_params.params.start;
5741
5742         /* Prepare parameters for function state transitions */
5743         bnx2x_set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags);
5744
5745         func_params.f_obj = &sc->func_obj;
5746         func_params.cmd = ECORE_F_CMD_START;
5747
5748         /* Function parameters */
5749         start_params->mf_mode = sc->devinfo.mf_info.mf_mode;
5750         start_params->sd_vlan_tag = OVLAN(sc);
5751
5752         if (CHIP_IS_E2(sc) || CHIP_IS_E3(sc)) {
5753                 start_params->network_cos_mode = STATIC_COS;
5754         } else {                /* CHIP_IS_E1X */
5755                 start_params->network_cos_mode = FW_WRR;
5756         }
5757
5758         start_params->gre_tunnel_mode = 0;
5759         start_params->gre_tunnel_rss = 0;
5760
5761         return ecore_func_state_change(sc, &func_params);
5762 }
5763
5764 static int bnx2x_set_power_state(struct bnx2x_softc *sc, uint8_t state)
5765 {
5766         uint16_t pmcsr;
5767
5768         /* If there is no power capability, silently succeed */
5769         if (!(sc->devinfo.pcie_cap_flags & BNX2X_PM_CAPABLE_FLAG)) {
5770                 PMD_DRV_LOG(WARNING, "No power capability");
5771                 return 0;
5772         }
5773
5774         pci_read(sc, (sc->devinfo.pcie_pm_cap_reg + PCIR_POWER_STATUS), &pmcsr,
5775                  2);
5776
5777         switch (state) {
5778         case PCI_PM_D0:
5779                 pci_write_word(sc,
5780                                (sc->devinfo.pcie_pm_cap_reg +
5781                                 PCIR_POWER_STATUS),
5782                                ((pmcsr & ~PCIM_PSTAT_DMASK) | PCIM_PSTAT_PME));
5783
5784                 if (pmcsr & PCIM_PSTAT_DMASK) {
5785                         /* delay required during transition out of D3hot */
5786                         DELAY(20000);
5787                 }
5788
5789                 break;
5790
5791         case PCI_PM_D3hot:
5792                 /* don't shut down the power for emulation and FPGA */
5793                 if (CHIP_REV_IS_SLOW(sc)) {
5794                         return 0;
5795                 }
5796
5797                 pmcsr &= ~PCIM_PSTAT_DMASK;
5798                 pmcsr |= PCIM_PSTAT_D3;
5799
5800                 if (sc->wol) {
5801                         pmcsr |= PCIM_PSTAT_PMEENABLE;
5802                 }
5803
5804                 pci_write_long(sc,
5805                                (sc->devinfo.pcie_pm_cap_reg +
5806                                 PCIR_POWER_STATUS), pmcsr);
5807
5808                 /*
5809                  * No more memory access after this point until device is brought back
5810                  * to D0 state.
5811                  */
5812                 break;
5813
5814         default:
5815                 PMD_DRV_LOG(NOTICE, "Can't support PCI power state = %d",
5816                             state);
5817                 return -1;
5818         }
5819
5820         return 0;
5821 }
5822
5823 /* return true if succeeded to acquire the lock */
5824 static uint8_t bnx2x_trylock_hw_lock(struct bnx2x_softc *sc, uint32_t resource)
5825 {
5826         uint32_t lock_status;
5827         uint32_t resource_bit = (1 << resource);
5828         int func = SC_FUNC(sc);
5829         uint32_t hw_lock_control_reg;
5830
5831         /* Validating that the resource is within range */
5832         if (resource > HW_LOCK_MAX_RESOURCE_VALUE) {
5833                 PMD_DRV_LOG(INFO,
5834                             "resource(0x%x) > HW_LOCK_MAX_RESOURCE_VALUE(0x%x)",
5835                             resource, HW_LOCK_MAX_RESOURCE_VALUE);
5836                 return FALSE;
5837         }
5838
5839         if (func <= 5) {
5840                 hw_lock_control_reg = (MISC_REG_DRIVER_CONTROL_1 + func * 8);
5841         } else {
5842                 hw_lock_control_reg =
5843                     (MISC_REG_DRIVER_CONTROL_7 + (func - 6) * 8);
5844         }
5845
5846         /* try to acquire the lock */
5847         REG_WR(sc, hw_lock_control_reg + 4, resource_bit);
5848         lock_status = REG_RD(sc, hw_lock_control_reg);
5849         if (lock_status & resource_bit) {
5850                 return TRUE;
5851         }
5852
5853         PMD_DRV_LOG(NOTICE, "Failed to get a resource lock 0x%x", resource);
5854
5855         return FALSE;
5856 }
5857
5858 /*
5859  * Get the recovery leader resource id according to the engine this function
5860  * belongs to. Currently only only 2 engines is supported.
5861  */
5862 static int bnx2x_get_leader_lock_resource(struct bnx2x_softc *sc)
5863 {
5864         if (SC_PATH(sc)) {
5865                 return HW_LOCK_RESOURCE_RECOVERY_LEADER_1;
5866         } else {
5867                 return HW_LOCK_RESOURCE_RECOVERY_LEADER_0;
5868         }
5869 }
5870
5871 /* try to acquire a leader lock for current engine */
5872 static uint8_t bnx2x_trylock_leader_lock(struct bnx2x_softc *sc)
5873 {
5874         return bnx2x_trylock_hw_lock(sc, bnx2x_get_leader_lock_resource(sc));
5875 }
5876
5877 static int bnx2x_release_leader_lock(struct bnx2x_softc *sc)
5878 {
5879         return bnx2x_release_hw_lock(sc, bnx2x_get_leader_lock_resource(sc));
5880 }
5881
5882 /* close gates #2, #3 and #4 */
5883 static void bnx2x_set_234_gates(struct bnx2x_softc *sc, uint8_t close)
5884 {
5885         uint32_t val;
5886
5887         /* gates #2 and #4a are closed/opened */
5888         /* #4 */
5889         REG_WR(sc, PXP_REG_HST_DISCARD_DOORBELLS, ! !close);
5890         /* #2 */
5891         REG_WR(sc, PXP_REG_HST_DISCARD_INTERNAL_WRITES, ! !close);
5892
5893         /* #3 */
5894         if (CHIP_IS_E1x(sc)) {
5895 /* prevent interrupts from HC on both ports */
5896                 val = REG_RD(sc, HC_REG_CONFIG_1);
5897                 if (close)
5898                         REG_WR(sc, HC_REG_CONFIG_1, (val & ~(uint32_t)
5899                                                      HC_CONFIG_1_REG_BLOCK_DISABLE_1));
5900                 else
5901                         REG_WR(sc, HC_REG_CONFIG_1,
5902                                (val | HC_CONFIG_1_REG_BLOCK_DISABLE_1));
5903
5904                 val = REG_RD(sc, HC_REG_CONFIG_0);
5905                 if (close)
5906                         REG_WR(sc, HC_REG_CONFIG_0, (val & ~(uint32_t)
5907                                                      HC_CONFIG_0_REG_BLOCK_DISABLE_0));
5908                 else
5909                         REG_WR(sc, HC_REG_CONFIG_0,
5910                                (val | HC_CONFIG_0_REG_BLOCK_DISABLE_0));
5911
5912         } else {
5913 /* Prevent incoming interrupts in IGU */
5914                 val = REG_RD(sc, IGU_REG_BLOCK_CONFIGURATION);
5915
5916                 if (close)
5917                         REG_WR(sc, IGU_REG_BLOCK_CONFIGURATION,
5918                                (val & ~(uint32_t)
5919                                 IGU_BLOCK_CONFIGURATION_REG_BLOCK_ENABLE));
5920                 else
5921                         REG_WR(sc, IGU_REG_BLOCK_CONFIGURATION,
5922                                (val |
5923                                 IGU_BLOCK_CONFIGURATION_REG_BLOCK_ENABLE));
5924         }
5925
5926         wmb();
5927 }
5928
5929 /* poll for pending writes bit, it should get cleared in no more than 1s */
5930 static int bnx2x_er_poll_igu_vq(struct bnx2x_softc *sc)
5931 {
5932         uint32_t cnt = 1000;
5933         uint32_t pend_bits = 0;
5934
5935         do {
5936                 pend_bits = REG_RD(sc, IGU_REG_PENDING_BITS_STATUS);
5937
5938                 if (pend_bits == 0) {
5939                         break;
5940                 }
5941
5942                 DELAY(1000);
5943         } while (cnt-- > 0);
5944
5945         if (cnt <= 0) {
5946                 PMD_DRV_LOG(NOTICE, "Still pending IGU requests bits=0x%08x!",
5947                             pend_bits);
5948                 return -1;
5949         }
5950
5951         return 0;
5952 }
5953
5954 #define SHARED_MF_CLP_MAGIC  0x80000000 /* 'magic' bit */
5955
5956 static void bnx2x_clp_reset_prep(struct bnx2x_softc *sc, uint32_t * magic_val)
5957 {
5958         /* Do some magic... */
5959         uint32_t val = MFCFG_RD(sc, shared_mf_config.clp_mb);
5960         *magic_val = val & SHARED_MF_CLP_MAGIC;
5961         MFCFG_WR(sc, shared_mf_config.clp_mb, val | SHARED_MF_CLP_MAGIC);
5962 }
5963
5964 /* restore the value of the 'magic' bit */
5965 static void bnx2x_clp_reset_done(struct bnx2x_softc *sc, uint32_t magic_val)
5966 {
5967         /* Restore the 'magic' bit value... */
5968         uint32_t val = MFCFG_RD(sc, shared_mf_config.clp_mb);
5969         MFCFG_WR(sc, shared_mf_config.clp_mb,
5970                  (val & (~SHARED_MF_CLP_MAGIC)) | magic_val);
5971 }
5972
5973 /* prepare for MCP reset, takes care of CLP configurations */
5974 static void bnx2x_reset_mcp_prep(struct bnx2x_softc *sc, uint32_t * magic_val)
5975 {
5976         uint32_t shmem;
5977         uint32_t validity_offset;
5978
5979         /* set `magic' bit in order to save MF config */
5980         bnx2x_clp_reset_prep(sc, magic_val);
5981
5982         /* get shmem offset */
5983         shmem = REG_RD(sc, MISC_REG_SHARED_MEM_ADDR);
5984         validity_offset =
5985             offsetof(struct shmem_region, validity_map[SC_PORT(sc)]);
5986
5987         /* Clear validity map flags */
5988         if (shmem > 0) {
5989                 REG_WR(sc, shmem + validity_offset, 0);
5990         }
5991 }
5992
5993 #define MCP_TIMEOUT      5000   /* 5 seconds (in ms) */
5994 #define MCP_ONE_TIMEOUT  100    /* 100 ms */
5995
5996 static void bnx2x_mcp_wait_one(struct bnx2x_softc *sc)
5997 {
5998         /* special handling for emulation and FPGA (10 times longer) */
5999         if (CHIP_REV_IS_SLOW(sc)) {
6000                 DELAY((MCP_ONE_TIMEOUT * 10) * 1000);
6001         } else {
6002                 DELAY((MCP_ONE_TIMEOUT) * 1000);
6003         }
6004 }
6005
6006 /* initialize shmem_base and waits for validity signature to appear */
6007 static int bnx2x_init_shmem(struct bnx2x_softc *sc)
6008 {
6009         int cnt = 0;
6010         uint32_t val = 0;
6011
6012         do {
6013                 sc->devinfo.shmem_base =
6014                     sc->link_params.shmem_base =
6015                     REG_RD(sc, MISC_REG_SHARED_MEM_ADDR);
6016
6017                 if (sc->devinfo.shmem_base) {
6018                         val = SHMEM_RD(sc, validity_map[SC_PORT(sc)]);
6019                         if (val & SHR_MEM_VALIDITY_MB)
6020                                 return 0;
6021                 }
6022
6023                 bnx2x_mcp_wait_one(sc);
6024
6025         } while (cnt++ < (MCP_TIMEOUT / MCP_ONE_TIMEOUT));
6026
6027         PMD_DRV_LOG(NOTICE, "BAD MCP validity signature");
6028
6029         return -1;
6030 }
6031
6032 static int bnx2x_reset_mcp_comp(struct bnx2x_softc *sc, uint32_t magic_val)
6033 {
6034         int rc = bnx2x_init_shmem(sc);
6035
6036         /* Restore the `magic' bit value */
6037         bnx2x_clp_reset_done(sc, magic_val);
6038
6039         return rc;
6040 }
6041
6042 static void bnx2x_pxp_prep(struct bnx2x_softc *sc)
6043 {
6044         REG_WR(sc, PXP2_REG_RD_START_INIT, 0);
6045         REG_WR(sc, PXP2_REG_RQ_RBC_DONE, 0);
6046         wmb();
6047 }
6048
6049 /*
6050  * Reset the whole chip except for:
6051  *      - PCIE core
6052  *      - PCI Glue, PSWHST, PXP/PXP2 RF (all controlled by one reset bit)
6053  *      - IGU
6054  *      - MISC (including AEU)
6055  *      - GRC
6056  *      - RBCN, RBCP
6057  */
6058 static void bnx2x_process_kill_chip_reset(struct bnx2x_softc *sc, uint8_t global)
6059 {
6060         uint32_t not_reset_mask1, reset_mask1, not_reset_mask2, reset_mask2;
6061         uint32_t global_bits2, stay_reset2;
6062
6063         /*
6064          * Bits that have to be set in reset_mask2 if we want to reset 'global'
6065          * (per chip) blocks.
6066          */
6067         global_bits2 =
6068             MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_CMN_CPU |
6069             MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_CMN_CORE;
6070
6071         /*
6072          * Don't reset the following blocks.
6073          * Important: per port blocks (such as EMAC, BMAC, UMAC) can't be
6074          *            reset, as in 4 port device they might still be owned
6075          *            by the MCP (there is only one leader per path).
6076          */
6077         not_reset_mask1 =
6078             MISC_REGISTERS_RESET_REG_1_RST_HC |
6079             MISC_REGISTERS_RESET_REG_1_RST_PXPV |
6080             MISC_REGISTERS_RESET_REG_1_RST_PXP;
6081
6082         not_reset_mask2 =
6083             MISC_REGISTERS_RESET_REG_2_RST_PCI_MDIO |
6084             MISC_REGISTERS_RESET_REG_2_RST_EMAC0_HARD_CORE |
6085             MISC_REGISTERS_RESET_REG_2_RST_EMAC1_HARD_CORE |
6086             MISC_REGISTERS_RESET_REG_2_RST_MISC_CORE |
6087             MISC_REGISTERS_RESET_REG_2_RST_RBCN |
6088             MISC_REGISTERS_RESET_REG_2_RST_GRC |
6089             MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_REG_HARD_CORE |
6090             MISC_REGISTERS_RESET_REG_2_RST_MCP_N_HARD_CORE_RST_B |
6091             MISC_REGISTERS_RESET_REG_2_RST_ATC |
6092             MISC_REGISTERS_RESET_REG_2_PGLC |
6093             MISC_REGISTERS_RESET_REG_2_RST_BMAC0 |
6094             MISC_REGISTERS_RESET_REG_2_RST_BMAC1 |
6095             MISC_REGISTERS_RESET_REG_2_RST_EMAC0 |
6096             MISC_REGISTERS_RESET_REG_2_RST_EMAC1 |
6097             MISC_REGISTERS_RESET_REG_2_UMAC0 | MISC_REGISTERS_RESET_REG_2_UMAC1;
6098
6099         /*
6100          * Keep the following blocks in reset:
6101          *  - all xxMACs are handled by the elink code.
6102          */
6103         stay_reset2 =
6104             MISC_REGISTERS_RESET_REG_2_XMAC |
6105             MISC_REGISTERS_RESET_REG_2_XMAC_SOFT;
6106
6107         /* Full reset masks according to the chip */
6108         reset_mask1 = 0xffffffff;
6109
6110         if (CHIP_IS_E1H(sc))
6111                 reset_mask2 = 0x1ffff;
6112         else if (CHIP_IS_E2(sc))
6113                 reset_mask2 = 0xfffff;
6114         else                    /* CHIP_IS_E3 */
6115                 reset_mask2 = 0x3ffffff;
6116
6117         /* Don't reset global blocks unless we need to */
6118         if (!global)
6119                 reset_mask2 &= ~global_bits2;
6120
6121         /*
6122          * In case of attention in the QM, we need to reset PXP
6123          * (MISC_REGISTERS_RESET_REG_2_RST_PXP_RQ_RD_WR) before QM
6124          * because otherwise QM reset would release 'close the gates' shortly
6125          * before resetting the PXP, then the PSWRQ would send a write
6126          * request to PGLUE. Then when PXP is reset, PGLUE would try to
6127          * read the payload data from PSWWR, but PSWWR would not
6128          * respond. The write queue in PGLUE would stuck, dmae commands
6129          * would not return. Therefore it's important to reset the second
6130          * reset register (containing the
6131          * MISC_REGISTERS_RESET_REG_2_RST_PXP_RQ_RD_WR bit) before the
6132          * first one (containing the MISC_REGISTERS_RESET_REG_1_RST_QM
6133          * bit).
6134          */
6135         REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
6136                reset_mask2 & (~not_reset_mask2));
6137
6138         REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR,
6139                reset_mask1 & (~not_reset_mask1));
6140
6141         mb();
6142         wmb();
6143
6144         REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET,
6145                reset_mask2 & (~stay_reset2));
6146
6147         mb();
6148         wmb();
6149
6150         REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, reset_mask1);
6151         wmb();
6152 }
6153
6154 static int bnx2x_process_kill(struct bnx2x_softc *sc, uint8_t global)
6155 {
6156         int cnt = 1000;
6157         uint32_t val = 0;
6158         uint32_t sr_cnt, blk_cnt, port_is_idle_0, port_is_idle_1, pgl_exp_rom2;
6159         uint32_t tags_63_32 = 0;
6160
6161         /* Empty the Tetris buffer, wait for 1s */
6162         do {
6163                 sr_cnt = REG_RD(sc, PXP2_REG_RD_SR_CNT);
6164                 blk_cnt = REG_RD(sc, PXP2_REG_RD_BLK_CNT);
6165                 port_is_idle_0 = REG_RD(sc, PXP2_REG_RD_PORT_IS_IDLE_0);
6166                 port_is_idle_1 = REG_RD(sc, PXP2_REG_RD_PORT_IS_IDLE_1);
6167                 pgl_exp_rom2 = REG_RD(sc, PXP2_REG_PGL_EXP_ROM2);
6168                 if (CHIP_IS_E3(sc)) {
6169                         tags_63_32 = REG_RD(sc, PGLUE_B_REG_TAGS_63_32);
6170                 }
6171
6172                 if ((sr_cnt == 0x7e) && (blk_cnt == 0xa0) &&
6173                     ((port_is_idle_0 & 0x1) == 0x1) &&
6174                     ((port_is_idle_1 & 0x1) == 0x1) &&
6175                     (pgl_exp_rom2 == 0xffffffff) &&
6176                     (!CHIP_IS_E3(sc) || (tags_63_32 == 0xffffffff)))
6177                         break;
6178                 DELAY(1000);
6179         } while (cnt-- > 0);
6180
6181         if (cnt <= 0) {
6182                 PMD_DRV_LOG(NOTICE,
6183                             "ERROR: Tetris buffer didn't get empty or there "
6184                             "are still outstanding read requests after 1s! "
6185                             "sr_cnt=0x%08x, blk_cnt=0x%08x, port_is_idle_0=0x%08x, "
6186                             "port_is_idle_1=0x%08x, pgl_exp_rom2=0x%08x",
6187                             sr_cnt, blk_cnt, port_is_idle_0, port_is_idle_1,
6188                             pgl_exp_rom2);
6189                 return -1;
6190         }
6191
6192         mb();
6193
6194         /* Close gates #2, #3 and #4 */
6195         bnx2x_set_234_gates(sc, TRUE);
6196
6197         /* Poll for IGU VQs for 57712 and newer chips */
6198         if (!CHIP_IS_E1x(sc) && bnx2x_er_poll_igu_vq(sc)) {
6199                 return -1;
6200         }
6201
6202         /* clear "unprepared" bit */
6203         REG_WR(sc, MISC_REG_UNPREPARED, 0);
6204         mb();
6205
6206         /* Make sure all is written to the chip before the reset */
6207         wmb();
6208
6209         /*
6210          * Wait for 1ms to empty GLUE and PCI-E core queues,
6211          * PSWHST, GRC and PSWRD Tetris buffer.
6212          */
6213         DELAY(1000);
6214
6215         /* Prepare to chip reset: */
6216         /* MCP */
6217         if (global) {
6218                 bnx2x_reset_mcp_prep(sc, &val);
6219         }
6220
6221         /* PXP */
6222         bnx2x_pxp_prep(sc);
6223         mb();
6224
6225         /* reset the chip */
6226         bnx2x_process_kill_chip_reset(sc, global);
6227         mb();
6228
6229         /* Recover after reset: */
6230         /* MCP */
6231         if (global && bnx2x_reset_mcp_comp(sc, val)) {
6232                 return -1;
6233         }
6234
6235         /* Open the gates #2, #3 and #4 */
6236         bnx2x_set_234_gates(sc, FALSE);
6237
6238         return 0;
6239 }
6240
6241 static int bnx2x_leader_reset(struct bnx2x_softc *sc)
6242 {
6243         int rc = 0;
6244         uint8_t global = bnx2x_reset_is_global(sc);
6245         uint32_t load_code;
6246
6247         /*
6248          * If not going to reset MCP, load "fake" driver to reset HW while
6249          * driver is owner of the HW.
6250          */
6251         if (!global && !BNX2X_NOMCP(sc)) {
6252                 load_code = bnx2x_fw_command(sc, DRV_MSG_CODE_LOAD_REQ,
6253                                            DRV_MSG_CODE_LOAD_REQ_WITH_LFA);
6254                 if (!load_code) {
6255                         PMD_DRV_LOG(NOTICE, "MCP response failure, aborting");
6256                         rc = -1;
6257                         goto exit_leader_reset;
6258                 }
6259
6260                 if ((load_code != FW_MSG_CODE_DRV_LOAD_COMMON_CHIP) &&
6261                     (load_code != FW_MSG_CODE_DRV_LOAD_COMMON)) {
6262                         PMD_DRV_LOG(NOTICE,
6263                                     "MCP unexpected response, aborting");
6264                         rc = -1;
6265                         goto exit_leader_reset2;
6266                 }
6267
6268                 load_code = bnx2x_fw_command(sc, DRV_MSG_CODE_LOAD_DONE, 0);
6269                 if (!load_code) {
6270                         PMD_DRV_LOG(NOTICE, "MCP response failure, aborting");
6271                         rc = -1;
6272                         goto exit_leader_reset2;
6273                 }
6274         }
6275
6276         /* try to recover after the failure */
6277         if (bnx2x_process_kill(sc, global)) {
6278                 PMD_DRV_LOG(NOTICE, "Something bad occurred on engine %d!",
6279                             SC_PATH(sc));
6280                 rc = -1;
6281                 goto exit_leader_reset2;
6282         }
6283
6284         /*
6285          * Clear the RESET_IN_PROGRESS and RESET_GLOBAL bits and update the driver
6286          * state.
6287          */
6288         bnx2x_set_reset_done(sc);
6289         if (global) {
6290                 bnx2x_clear_reset_global(sc);
6291         }
6292
6293 exit_leader_reset2:
6294
6295         /* unload "fake driver" if it was loaded */
6296         if (!global &&!BNX2X_NOMCP(sc)) {
6297                 bnx2x_fw_command(sc, DRV_MSG_CODE_UNLOAD_REQ_WOL_MCP, 0);
6298                 bnx2x_fw_command(sc, DRV_MSG_CODE_UNLOAD_DONE, 0);
6299         }
6300
6301 exit_leader_reset:
6302
6303         sc->is_leader = 0;
6304         bnx2x_release_leader_lock(sc);
6305
6306         mb();
6307         return rc;
6308 }
6309
6310 /*
6311  * prepare INIT transition, parameters configured:
6312  *   - HC configuration
6313  *   - Queue's CDU context
6314  */
6315 static void
6316 bnx2x_pf_q_prep_init(struct bnx2x_softc *sc, struct bnx2x_fastpath *fp,
6317                    struct ecore_queue_init_params *init_params)
6318 {
6319         uint8_t cos;
6320         int cxt_index, cxt_offset;
6321
6322         bnx2x_set_bit(ECORE_Q_FLG_HC, &init_params->rx.flags);
6323         bnx2x_set_bit(ECORE_Q_FLG_HC, &init_params->tx.flags);
6324
6325         bnx2x_set_bit(ECORE_Q_FLG_HC_EN, &init_params->rx.flags);
6326         bnx2x_set_bit(ECORE_Q_FLG_HC_EN, &init_params->tx.flags);
6327
6328         /* HC rate */
6329         init_params->rx.hc_rate =
6330             sc->hc_rx_ticks ? (1000000 / sc->hc_rx_ticks) : 0;
6331         init_params->tx.hc_rate =
6332             sc->hc_tx_ticks ? (1000000 / sc->hc_tx_ticks) : 0;
6333
6334         /* FW SB ID */
6335         init_params->rx.fw_sb_id = init_params->tx.fw_sb_id = fp->fw_sb_id;
6336
6337         /* CQ index among the SB indices */
6338         init_params->rx.sb_cq_index = HC_INDEX_ETH_RX_CQ_CONS;
6339         init_params->tx.sb_cq_index = HC_INDEX_ETH_FIRST_TX_CQ_CONS;
6340
6341         /* set maximum number of COSs supported by this queue */
6342         init_params->max_cos = sc->max_cos;
6343
6344         /* set the context pointers queue object */
6345         for (cos = FIRST_TX_COS_INDEX; cos < init_params->max_cos; cos++) {
6346                 cxt_index = fp->index / ILT_PAGE_CIDS;
6347                 cxt_offset = fp->index - (cxt_index * ILT_PAGE_CIDS);
6348                 init_params->cxts[cos] =
6349                     &sc->context[cxt_index].vcxt[cxt_offset].eth;
6350         }
6351 }
6352
6353 /* set flags that are common for the Tx-only and not normal connections */
6354 static unsigned long
6355 bnx2x_get_common_flags(struct bnx2x_softc *sc, uint8_t zero_stats)
6356 {
6357         unsigned long flags = 0;
6358
6359         /* PF driver will always initialize the Queue to an ACTIVE state */
6360         bnx2x_set_bit(ECORE_Q_FLG_ACTIVE, &flags);
6361
6362         /*
6363          * tx only connections collect statistics (on the same index as the
6364          * parent connection). The statistics are zeroed when the parent
6365          * connection is initialized.
6366          */
6367
6368         bnx2x_set_bit(ECORE_Q_FLG_STATS, &flags);
6369         if (zero_stats) {
6370                 bnx2x_set_bit(ECORE_Q_FLG_ZERO_STATS, &flags);
6371         }
6372
6373         /*
6374          * tx only connections can support tx-switching, though their
6375          * CoS-ness doesn't survive the loopback
6376          */
6377         if (sc->flags & BNX2X_TX_SWITCHING) {
6378                 bnx2x_set_bit(ECORE_Q_FLG_TX_SWITCH, &flags);
6379         }
6380
6381         bnx2x_set_bit(ECORE_Q_FLG_PCSUM_ON_PKT, &flags);
6382
6383         return flags;
6384 }
6385
6386 static unsigned long bnx2x_get_q_flags(struct bnx2x_softc *sc, uint8_t leading)
6387 {
6388         unsigned long flags = 0;
6389
6390         if (IS_MF_SD(sc)) {
6391                 bnx2x_set_bit(ECORE_Q_FLG_OV, &flags);
6392         }
6393
6394         if (leading) {
6395                 bnx2x_set_bit(ECORE_Q_FLG_LEADING_RSS, &flags);
6396                 bnx2x_set_bit(ECORE_Q_FLG_MCAST, &flags);
6397         }
6398
6399         bnx2x_set_bit(ECORE_Q_FLG_VLAN, &flags);
6400
6401         /* merge with common flags */
6402         return flags | bnx2x_get_common_flags(sc, TRUE);
6403 }
6404
6405 static void
6406 bnx2x_pf_q_prep_general(struct bnx2x_softc *sc, struct bnx2x_fastpath *fp,
6407                       struct ecore_general_setup_params *gen_init, uint8_t cos)
6408 {
6409         gen_init->stat_id = bnx2x_stats_id(fp);
6410         gen_init->spcl_id = fp->cl_id;
6411         gen_init->mtu = sc->mtu;
6412         gen_init->cos = cos;
6413 }
6414
6415 static void
6416 bnx2x_pf_rx_q_prep(struct bnx2x_softc *sc, struct bnx2x_fastpath *fp,
6417                  struct rxq_pause_params *pause,
6418                  struct ecore_rxq_setup_params *rxq_init)
6419 {
6420         struct bnx2x_rx_queue *rxq;
6421
6422         rxq = sc->rx_queues[fp->index];
6423         if (!rxq) {
6424                 PMD_RX_LOG(ERR, "RX queue is NULL");
6425                 return;
6426         }
6427         /* pause */
6428         pause->bd_th_lo = BD_TH_LO(sc);
6429         pause->bd_th_hi = BD_TH_HI(sc);
6430
6431         pause->rcq_th_lo = RCQ_TH_LO(sc);
6432         pause->rcq_th_hi = RCQ_TH_HI(sc);
6433
6434         /* validate rings have enough entries to cross high thresholds */
6435         if (sc->dropless_fc &&
6436             pause->bd_th_hi + FW_PREFETCH_CNT > sc->rx_ring_size) {
6437                 PMD_DRV_LOG(WARNING, "rx bd ring threshold limit");
6438         }
6439
6440         if (sc->dropless_fc &&
6441             pause->rcq_th_hi + FW_PREFETCH_CNT > USABLE_RCQ_ENTRIES(rxq)) {
6442                 PMD_DRV_LOG(WARNING, "rcq ring threshold limit");
6443         }
6444
6445         pause->pri_map = 1;
6446
6447         /* rxq setup */
6448         rxq_init->dscr_map = (rte_iova_t)rxq->rx_ring_phys_addr;
6449         rxq_init->rcq_map = (rte_iova_t)rxq->cq_ring_phys_addr;
6450         rxq_init->rcq_np_map = (rte_iova_t)(rxq->cq_ring_phys_addr +
6451                                               BNX2X_PAGE_SIZE);
6452
6453         /*
6454          * This should be a maximum number of data bytes that may be
6455          * placed on the BD (not including paddings).
6456          */
6457         rxq_init->buf_sz = (fp->rx_buf_size - IP_HEADER_ALIGNMENT_PADDING);
6458
6459         rxq_init->cl_qzone_id = fp->cl_qzone_id;
6460         rxq_init->rss_engine_id = SC_FUNC(sc);
6461         rxq_init->mcast_engine_id = SC_FUNC(sc);
6462
6463         rxq_init->cache_line_log = BNX2X_RX_ALIGN_SHIFT;
6464         rxq_init->fw_sb_id = fp->fw_sb_id;
6465
6466         rxq_init->sb_cq_index = HC_INDEX_ETH_RX_CQ_CONS;
6467
6468         /*
6469          * configure silent vlan removal
6470          * if multi function mode is afex, then mask default vlan
6471          */
6472         if (IS_MF_AFEX(sc)) {
6473                 rxq_init->silent_removal_value =
6474                     sc->devinfo.mf_info.afex_def_vlan_tag;
6475                 rxq_init->silent_removal_mask = EVL_VLID_MASK;
6476         }
6477 }
6478
6479 static void
6480 bnx2x_pf_tx_q_prep(struct bnx2x_softc *sc, struct bnx2x_fastpath *fp,
6481                  struct ecore_txq_setup_params *txq_init, uint8_t cos)
6482 {
6483         struct bnx2x_tx_queue *txq = fp->sc->tx_queues[fp->index];
6484
6485         if (!txq) {
6486                 PMD_TX_LOG(ERR, "ERROR: TX queue is NULL");
6487                 return;
6488         }
6489         txq_init->dscr_map = (rte_iova_t)txq->tx_ring_phys_addr;
6490         txq_init->sb_cq_index = HC_INDEX_ETH_FIRST_TX_CQ_CONS + cos;
6491         txq_init->traffic_type = LLFC_TRAFFIC_TYPE_NW;
6492         txq_init->fw_sb_id = fp->fw_sb_id;
6493
6494         /*
6495          * set the TSS leading client id for TX classfication to the
6496          * leading RSS client id
6497          */
6498         txq_init->tss_leading_cl_id = BNX2X_FP(sc, 0, cl_id);
6499 }
6500
6501 /*
6502  * This function performs 2 steps in a queue state machine:
6503  *   1) RESET->INIT
6504  *   2) INIT->SETUP
6505  */
6506 static int
6507 bnx2x_setup_queue(struct bnx2x_softc *sc, struct bnx2x_fastpath *fp, uint8_t leading)
6508 {
6509         struct ecore_queue_state_params q_params = { NULL };
6510         struct ecore_queue_setup_params *setup_params = &q_params.params.setup;
6511         int rc;
6512
6513         PMD_DRV_LOG(DEBUG, "setting up queue %d", fp->index);
6514
6515         bnx2x_ack_sb(sc, fp->igu_sb_id, USTORM_ID, 0, IGU_INT_ENABLE, 0);
6516
6517         q_params.q_obj = &BNX2X_SP_OBJ(sc, fp).q_obj;
6518
6519         /* we want to wait for completion in this context */
6520         bnx2x_set_bit(RAMROD_COMP_WAIT, &q_params.ramrod_flags);
6521
6522         /* prepare the INIT parameters */
6523         bnx2x_pf_q_prep_init(sc, fp, &q_params.params.init);
6524
6525         /* Set the command */
6526         q_params.cmd = ECORE_Q_CMD_INIT;
6527
6528         /* Change the state to INIT */
6529         rc = ecore_queue_state_change(sc, &q_params);
6530         if (rc) {
6531                 PMD_DRV_LOG(NOTICE, "Queue(%d) INIT failed", fp->index);
6532                 return rc;
6533         }
6534
6535         PMD_DRV_LOG(DEBUG, "init complete");
6536
6537         /* now move the Queue to the SETUP state */
6538         memset(setup_params, 0, sizeof(*setup_params));
6539
6540         /* set Queue flags */
6541         setup_params->flags = bnx2x_get_q_flags(sc, leading);
6542
6543         /* set general SETUP parameters */
6544         bnx2x_pf_q_prep_general(sc, fp, &setup_params->gen_params,
6545                               FIRST_TX_COS_INDEX);
6546
6547         bnx2x_pf_rx_q_prep(sc, fp,
6548                          &setup_params->pause_params,
6549                          &setup_params->rxq_params);
6550
6551         bnx2x_pf_tx_q_prep(sc, fp, &setup_params->txq_params, FIRST_TX_COS_INDEX);
6552
6553         /* Set the command */
6554         q_params.cmd = ECORE_Q_CMD_SETUP;
6555
6556         /* change the state to SETUP */
6557         rc = ecore_queue_state_change(sc, &q_params);
6558         if (rc) {
6559                 PMD_DRV_LOG(NOTICE, "Queue(%d) SETUP failed", fp->index);
6560                 return rc;
6561         }
6562
6563         return rc;
6564 }
6565
6566 static int bnx2x_setup_leading(struct bnx2x_softc *sc)
6567 {
6568         if (IS_PF(sc))
6569                 return bnx2x_setup_queue(sc, &sc->fp[0], TRUE);
6570         else                    /* VF */
6571                 return bnx2x_vf_setup_queue(sc, &sc->fp[0], TRUE);
6572 }
6573
6574 static int
6575 bnx2x_config_rss_pf(struct bnx2x_softc *sc, struct ecore_rss_config_obj *rss_obj,
6576                   uint8_t config_hash)
6577 {
6578         struct ecore_config_rss_params params = { NULL };
6579         uint32_t i;
6580
6581         /*
6582          * Although RSS is meaningless when there is a single HW queue we
6583          * still need it enabled in order to have HW Rx hash generated.
6584          */
6585
6586         params.rss_obj = rss_obj;
6587
6588         bnx2x_set_bit(RAMROD_COMP_WAIT, &params.ramrod_flags);
6589
6590         bnx2x_set_bit(ECORE_RSS_MODE_REGULAR, &params.rss_flags);
6591
6592         /* RSS configuration */
6593         bnx2x_set_bit(ECORE_RSS_IPV4, &params.rss_flags);
6594         bnx2x_set_bit(ECORE_RSS_IPV4_TCP, &params.rss_flags);
6595         bnx2x_set_bit(ECORE_RSS_IPV6, &params.rss_flags);
6596         bnx2x_set_bit(ECORE_RSS_IPV6_TCP, &params.rss_flags);
6597         if (rss_obj->udp_rss_v4) {
6598                 bnx2x_set_bit(ECORE_RSS_IPV4_UDP, &params.rss_flags);
6599         }
6600         if (rss_obj->udp_rss_v6) {
6601                 bnx2x_set_bit(ECORE_RSS_IPV6_UDP, &params.rss_flags);
6602         }
6603
6604         /* Hash bits */
6605         params.rss_result_mask = MULTI_MASK;
6606
6607         rte_memcpy(params.ind_table, rss_obj->ind_table,
6608                          sizeof(params.ind_table));
6609
6610         if (config_hash) {
6611 /* RSS keys */
6612                 for (i = 0; i < sizeof(params.rss_key) / 4; i++) {
6613                         params.rss_key[i] = (uint32_t) rte_rand();
6614                 }
6615
6616                 bnx2x_set_bit(ECORE_RSS_SET_SRCH, &params.rss_flags);
6617         }
6618
6619         if (IS_PF(sc))
6620                 return ecore_config_rss(sc, &params);
6621         else
6622                 return bnx2x_vf_config_rss(sc, &params);
6623 }
6624
6625 static int bnx2x_config_rss_eth(struct bnx2x_softc *sc, uint8_t config_hash)
6626 {
6627         return bnx2x_config_rss_pf(sc, &sc->rss_conf_obj, config_hash);
6628 }
6629
6630 static int bnx2x_init_rss_pf(struct bnx2x_softc *sc)
6631 {
6632         uint8_t num_eth_queues = BNX2X_NUM_ETH_QUEUES(sc);
6633         uint32_t i;
6634
6635         /*
6636          * Prepare the initial contents of the indirection table if
6637          * RSS is enabled
6638          */
6639         for (i = 0; i < sizeof(sc->rss_conf_obj.ind_table); i++) {
6640                 sc->rss_conf_obj.ind_table[i] =
6641                     (sc->fp->cl_id + (i % num_eth_queues));
6642         }
6643
6644         if (sc->udp_rss) {
6645                 sc->rss_conf_obj.udp_rss_v4 = sc->rss_conf_obj.udp_rss_v6 = 1;
6646         }
6647
6648         /*
6649          * For 57711 SEARCHER configuration (rss_keys) is
6650          * per-port, so if explicit configuration is needed, do it only
6651          * for a PMF.
6652          *
6653          * For 57712 and newer it's a per-function configuration.
6654          */
6655         return bnx2x_config_rss_eth(sc, sc->port.pmf || !CHIP_IS_E1x(sc));
6656 }
6657
6658 static int
6659 bnx2x_set_mac_one(struct bnx2x_softc *sc, uint8_t * mac,
6660                 struct ecore_vlan_mac_obj *obj, uint8_t set, int mac_type,
6661                 unsigned long *ramrod_flags)
6662 {
6663         struct ecore_vlan_mac_ramrod_params ramrod_param;
6664         int rc;
6665
6666         memset(&ramrod_param, 0, sizeof(ramrod_param));
6667
6668         /* fill in general parameters */
6669         ramrod_param.vlan_mac_obj = obj;
6670         ramrod_param.ramrod_flags = *ramrod_flags;
6671
6672         /* fill a user request section if needed */
6673         if (!bnx2x_test_bit(RAMROD_CONT, ramrod_flags)) {
6674                 rte_memcpy(ramrod_param.user_req.u.mac.mac, mac,
6675                                  ETH_ALEN);
6676
6677                 bnx2x_set_bit(mac_type, &ramrod_param.user_req.vlan_mac_flags);
6678
6679 /* Set the command: ADD or DEL */
6680                 ramrod_param.user_req.cmd = (set) ? ECORE_VLAN_MAC_ADD :
6681                     ECORE_VLAN_MAC_DEL;
6682         }
6683
6684         rc = ecore_config_vlan_mac(sc, &ramrod_param);
6685
6686         if (rc == ECORE_EXISTS) {
6687                 PMD_DRV_LOG(INFO, "Failed to schedule ADD operations (EEXIST)");
6688 /* do not treat adding same MAC as error */
6689                 rc = 0;
6690         } else if (rc < 0) {
6691                 PMD_DRV_LOG(ERR,
6692                             "%s MAC failed (%d)", (set ? "Set" : "Delete"), rc);
6693         }
6694
6695         return rc;
6696 }
6697
6698 static int bnx2x_set_eth_mac(struct bnx2x_softc *sc, uint8_t set)
6699 {
6700         unsigned long ramrod_flags = 0;
6701
6702         PMD_DRV_LOG(DEBUG, "Adding Ethernet MAC");
6703
6704         bnx2x_set_bit(RAMROD_COMP_WAIT, &ramrod_flags);
6705
6706         /* Eth MAC is set on RSS leading client (fp[0]) */
6707         return bnx2x_set_mac_one(sc, sc->link_params.mac_addr,
6708                                &sc->sp_objs->mac_obj,
6709                                set, ECORE_ETH_MAC, &ramrod_flags);
6710 }
6711
6712 static int bnx2x_get_cur_phy_idx(struct bnx2x_softc *sc)
6713 {
6714         uint32_t sel_phy_idx = 0;
6715
6716         if (sc->link_params.num_phys <= 1) {
6717                 return ELINK_INT_PHY;
6718         }
6719
6720         if (sc->link_vars.link_up) {
6721                 sel_phy_idx = ELINK_EXT_PHY1;
6722 /* In case link is SERDES, check if the ELINK_EXT_PHY2 is the one */
6723                 if ((sc->link_vars.link_status & LINK_STATUS_SERDES_LINK) &&
6724                     (sc->link_params.phy[ELINK_EXT_PHY2].supported &
6725                      ELINK_SUPPORTED_FIBRE))
6726                         sel_phy_idx = ELINK_EXT_PHY2;
6727         } else {
6728                 switch (elink_phy_selection(&sc->link_params)) {
6729                 case PORT_HW_CFG_PHY_SELECTION_HARDWARE_DEFAULT:
6730                 case PORT_HW_CFG_PHY_SELECTION_FIRST_PHY:
6731                 case PORT_HW_CFG_PHY_SELECTION_FIRST_PHY_PRIORITY:
6732                         sel_phy_idx = ELINK_EXT_PHY1;
6733                         break;
6734                 case PORT_HW_CFG_PHY_SELECTION_SECOND_PHY:
6735                 case PORT_HW_CFG_PHY_SELECTION_SECOND_PHY_PRIORITY:
6736                         sel_phy_idx = ELINK_EXT_PHY2;
6737                         break;
6738                 }
6739         }
6740
6741         return sel_phy_idx;
6742 }
6743
6744 static int bnx2x_get_link_cfg_idx(struct bnx2x_softc *sc)
6745 {
6746         uint32_t sel_phy_idx = bnx2x_get_cur_phy_idx(sc);
6747
6748         /*
6749          * The selected activated PHY is always after swapping (in case PHY
6750          * swapping is enabled). So when swapping is enabled, we need to reverse
6751          * the configuration
6752          */
6753
6754         if (sc->link_params.multi_phy_config & PORT_HW_CFG_PHY_SWAPPED_ENABLED) {
6755                 if (sel_phy_idx == ELINK_EXT_PHY1)
6756                         sel_phy_idx = ELINK_EXT_PHY2;
6757                 else if (sel_phy_idx == ELINK_EXT_PHY2)
6758                         sel_phy_idx = ELINK_EXT_PHY1;
6759         }
6760
6761         return ELINK_LINK_CONFIG_IDX(sel_phy_idx);
6762 }
6763
6764 static void bnx2x_set_requested_fc(struct bnx2x_softc *sc)
6765 {
6766         /*
6767          * Initialize link parameters structure variables
6768          * It is recommended to turn off RX FC for jumbo frames
6769          * for better performance
6770          */
6771         if (CHIP_IS_E1x(sc) && (sc->mtu > 5000)) {
6772                 sc->link_params.req_fc_auto_adv = ELINK_FLOW_CTRL_TX;
6773         } else {
6774                 sc->link_params.req_fc_auto_adv = ELINK_FLOW_CTRL_BOTH;
6775         }
6776 }
6777
6778 static void bnx2x_calc_fc_adv(struct bnx2x_softc *sc)
6779 {
6780         uint8_t cfg_idx = bnx2x_get_link_cfg_idx(sc);
6781         switch (sc->link_vars.ieee_fc &
6782                 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_MASK) {
6783         case MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_NONE:
6784         default:
6785                 sc->port.advertising[cfg_idx] &= ~(ADVERTISED_Asym_Pause |
6786                                                    ADVERTISED_Pause);
6787                 break;
6788
6789         case MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH:
6790                 sc->port.advertising[cfg_idx] |= (ADVERTISED_Asym_Pause |
6791                                                   ADVERTISED_Pause);
6792                 break;
6793
6794         case MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC:
6795                 sc->port.advertising[cfg_idx] |= ADVERTISED_Asym_Pause;
6796                 break;
6797         }
6798 }
6799
6800 static uint16_t bnx2x_get_mf_speed(struct bnx2x_softc *sc)
6801 {
6802         uint16_t line_speed = sc->link_vars.line_speed;
6803         if (IS_MF(sc)) {
6804                 uint16_t maxCfg = bnx2x_extract_max_cfg(sc,
6805                                                       sc->devinfo.
6806                                                       mf_info.mf_config[SC_VN
6807                                                                         (sc)]);
6808
6809 /* calculate the current MAX line speed limit for the MF devices */
6810                 if (IS_MF_SI(sc)) {
6811                         line_speed = (line_speed * maxCfg) / 100;
6812                 } else {        /* SD mode */
6813                         uint16_t vn_max_rate = maxCfg * 100;
6814
6815                         if (vn_max_rate < line_speed) {
6816                                 line_speed = vn_max_rate;
6817                         }
6818                 }
6819         }
6820
6821         return line_speed;
6822 }
6823
6824 static void
6825 bnx2x_fill_report_data(struct bnx2x_softc *sc, struct bnx2x_link_report_data *data)
6826 {
6827         uint16_t line_speed = bnx2x_get_mf_speed(sc);
6828
6829         memset(data, 0, sizeof(*data));
6830
6831         /* fill the report data with the effective line speed */
6832         data->line_speed = line_speed;
6833
6834         /* Link is down */
6835         if (!sc->link_vars.link_up || (sc->flags & BNX2X_MF_FUNC_DIS)) {
6836                 bnx2x_set_bit(BNX2X_LINK_REPORT_LINK_DOWN,
6837                             &data->link_report_flags);
6838         }
6839
6840         /* Full DUPLEX */
6841         if (sc->link_vars.duplex == DUPLEX_FULL) {
6842                 bnx2x_set_bit(BNX2X_LINK_REPORT_FULL_DUPLEX,
6843                             &data->link_report_flags);
6844         }
6845
6846         /* Rx Flow Control is ON */
6847         if (sc->link_vars.flow_ctrl & ELINK_FLOW_CTRL_RX) {
6848                 bnx2x_set_bit(BNX2X_LINK_REPORT_RX_FC_ON, &data->link_report_flags);
6849         }
6850
6851         /* Tx Flow Control is ON */
6852         if (sc->link_vars.flow_ctrl & ELINK_FLOW_CTRL_TX) {
6853                 bnx2x_set_bit(BNX2X_LINK_REPORT_TX_FC_ON, &data->link_report_flags);
6854         }
6855 }
6856
6857 /* report link status to OS, should be called under phy_lock */
6858 static void bnx2x_link_report(struct bnx2x_softc *sc)
6859 {
6860         struct bnx2x_link_report_data cur_data;
6861
6862         /* reread mf_cfg */
6863         if (IS_PF(sc)) {
6864                 bnx2x_read_mf_cfg(sc);
6865         }
6866
6867         /* Read the current link report info */
6868         bnx2x_fill_report_data(sc, &cur_data);
6869
6870         /* Don't report link down or exactly the same link status twice */
6871         if (!memcmp(&cur_data, &sc->last_reported_link, sizeof(cur_data)) ||
6872             (bnx2x_test_bit(BNX2X_LINK_REPORT_LINK_DOWN,
6873                           &sc->last_reported_link.link_report_flags) &&
6874              bnx2x_test_bit(BNX2X_LINK_REPORT_LINK_DOWN,
6875                           &cur_data.link_report_flags))) {
6876                 return;
6877         }
6878
6879         sc->link_cnt++;
6880
6881         /* report new link params and remember the state for the next time */
6882         rte_memcpy(&sc->last_reported_link, &cur_data, sizeof(cur_data));
6883
6884         if (bnx2x_test_bit(BNX2X_LINK_REPORT_LINK_DOWN,
6885                          &cur_data.link_report_flags)) {
6886                 PMD_DRV_LOG(INFO, "NIC Link is Down");
6887         } else {
6888                 __rte_unused const char *duplex;
6889                 __rte_unused const char *flow;
6890
6891                 if (bnx2x_test_and_clear_bit(BNX2X_LINK_REPORT_FULL_DUPLEX,
6892                                            &cur_data.link_report_flags)) {
6893                         duplex = "full";
6894                 } else {
6895                         duplex = "half";
6896                 }
6897
6898 /*
6899  * Handle the FC at the end so that only these flags would be
6900  * possibly set. This way we may easily check if there is no FC
6901  * enabled.
6902  */
6903                 if (cur_data.link_report_flags) {
6904                         if (bnx2x_test_bit(BNX2X_LINK_REPORT_RX_FC_ON,
6905                                          &cur_data.link_report_flags) &&
6906                             bnx2x_test_bit(BNX2X_LINK_REPORT_TX_FC_ON,
6907                                          &cur_data.link_report_flags)) {
6908                                 flow = "ON - receive & transmit";
6909                         } else if (bnx2x_test_bit(BNX2X_LINK_REPORT_RX_FC_ON,
6910                                                 &cur_data.link_report_flags) &&
6911                                    !bnx2x_test_bit(BNX2X_LINK_REPORT_TX_FC_ON,
6912                                                  &cur_data.link_report_flags)) {
6913                                 flow = "ON - receive";
6914                         } else if (!bnx2x_test_bit(BNX2X_LINK_REPORT_RX_FC_ON,
6915                                                  &cur_data.link_report_flags) &&
6916                                    bnx2x_test_bit(BNX2X_LINK_REPORT_TX_FC_ON,
6917                                                 &cur_data.link_report_flags)) {
6918                                 flow = "ON - transmit";
6919                         } else {
6920                                 flow = "none";  /* possible? */
6921                         }
6922                 } else {
6923                         flow = "none";
6924                 }
6925
6926                 PMD_DRV_LOG(INFO,
6927                             "NIC Link is Up, %d Mbps %s duplex, Flow control: %s",
6928                             cur_data.line_speed, duplex, flow);
6929         }
6930 }
6931
6932 void bnx2x_link_status_update(struct bnx2x_softc *sc)
6933 {
6934         if (sc->state != BNX2X_STATE_OPEN) {
6935                 return;
6936         }
6937
6938         if (IS_PF(sc) && !CHIP_REV_IS_SLOW(sc)) {
6939                 elink_link_status_update(&sc->link_params, &sc->link_vars);
6940         } else {
6941                 sc->port.supported[0] |= (ELINK_SUPPORTED_10baseT_Half |
6942                                           ELINK_SUPPORTED_10baseT_Full |
6943                                           ELINK_SUPPORTED_100baseT_Half |
6944                                           ELINK_SUPPORTED_100baseT_Full |
6945                                           ELINK_SUPPORTED_1000baseT_Full |
6946                                           ELINK_SUPPORTED_2500baseX_Full |
6947                                           ELINK_SUPPORTED_10000baseT_Full |
6948                                           ELINK_SUPPORTED_TP |
6949                                           ELINK_SUPPORTED_FIBRE |
6950                                           ELINK_SUPPORTED_Autoneg |
6951                                           ELINK_SUPPORTED_Pause |
6952                                           ELINK_SUPPORTED_Asym_Pause);
6953                 sc->port.advertising[0] = sc->port.supported[0];
6954
6955                 sc->link_params.sc = sc;
6956                 sc->link_params.port = SC_PORT(sc);
6957                 sc->link_params.req_duplex[0] = DUPLEX_FULL;
6958                 sc->link_params.req_flow_ctrl[0] = ELINK_FLOW_CTRL_NONE;
6959                 sc->link_params.req_line_speed[0] = SPEED_10000;
6960                 sc->link_params.speed_cap_mask[0] = 0x7f0000;
6961                 sc->link_params.switch_cfg = ELINK_SWITCH_CFG_10G;
6962
6963                 if (CHIP_REV_IS_FPGA(sc)) {
6964                         sc->link_vars.mac_type = ELINK_MAC_TYPE_EMAC;
6965                         sc->link_vars.line_speed = ELINK_SPEED_1000;
6966                         sc->link_vars.link_status = (LINK_STATUS_LINK_UP |
6967                                                      LINK_STATUS_SPEED_AND_DUPLEX_1000TFD);
6968                 } else {
6969                         sc->link_vars.mac_type = ELINK_MAC_TYPE_BMAC;
6970                         sc->link_vars.line_speed = ELINK_SPEED_10000;
6971                         sc->link_vars.link_status = (LINK_STATUS_LINK_UP |
6972                                                      LINK_STATUS_SPEED_AND_DUPLEX_10GTFD);
6973                 }
6974
6975                 sc->link_vars.link_up = 1;
6976
6977                 sc->link_vars.duplex = DUPLEX_FULL;
6978                 sc->link_vars.flow_ctrl = ELINK_FLOW_CTRL_NONE;
6979
6980                 if (IS_PF(sc)) {
6981                         REG_WR(sc,
6982                                NIG_REG_EGRESS_DRAIN0_MODE +
6983                                sc->link_params.port * 4, 0);
6984                         bnx2x_stats_handle(sc, STATS_EVENT_LINK_UP);
6985                         bnx2x_link_report(sc);
6986                 }
6987         }
6988
6989         if (IS_PF(sc)) {
6990                 if (sc->link_vars.link_up) {
6991                         bnx2x_stats_handle(sc, STATS_EVENT_LINK_UP);
6992                 } else {
6993                         bnx2x_stats_handle(sc, STATS_EVENT_STOP);
6994                 }
6995                 bnx2x_link_report(sc);
6996         } else {
6997                 bnx2x_link_report(sc);
6998                 bnx2x_stats_handle(sc, STATS_EVENT_LINK_UP);
6999         }
7000 }
7001
7002 static void bnx2x_periodic_start(struct bnx2x_softc *sc)
7003 {
7004         atomic_store_rel_long(&sc->periodic_flags, PERIODIC_GO);
7005 }
7006
7007 static void bnx2x_periodic_stop(struct bnx2x_softc *sc)
7008 {
7009         atomic_store_rel_long(&sc->periodic_flags, PERIODIC_STOP);
7010 }
7011
7012 static int bnx2x_initial_phy_init(struct bnx2x_softc *sc, int load_mode)
7013 {
7014         int rc, cfg_idx = bnx2x_get_link_cfg_idx(sc);
7015         uint16_t req_line_speed = sc->link_params.req_line_speed[cfg_idx];
7016         struct elink_params *lp = &sc->link_params;
7017
7018         bnx2x_set_requested_fc(sc);
7019
7020         if (load_mode == LOAD_DIAG) {
7021                 lp->loopback_mode = ELINK_LOOPBACK_XGXS;
7022 /* Prefer doing PHY loopback at 10G speed, if possible */
7023                 if (lp->req_line_speed[cfg_idx] < ELINK_SPEED_10000) {
7024                         if (lp->speed_cap_mask[cfg_idx] &
7025                             PORT_HW_CFG_SPEED_CAPABILITY_D0_10G) {
7026                                 lp->req_line_speed[cfg_idx] = ELINK_SPEED_10000;
7027                         } else {
7028                                 lp->req_line_speed[cfg_idx] = ELINK_SPEED_1000;
7029                         }
7030                 }
7031         }
7032
7033         if (load_mode == LOAD_LOOPBACK_EXT) {
7034                 lp->loopback_mode = ELINK_LOOPBACK_EXT;
7035         }
7036
7037         rc = elink_phy_init(&sc->link_params, &sc->link_vars);
7038
7039         bnx2x_calc_fc_adv(sc);
7040
7041         if (sc->link_vars.link_up) {
7042                 bnx2x_stats_handle(sc, STATS_EVENT_LINK_UP);
7043                 bnx2x_link_report(sc);
7044         }
7045
7046         if (!CHIP_REV_IS_SLOW(sc)) {
7047                 bnx2x_periodic_start(sc);
7048         }
7049
7050         sc->link_params.req_line_speed[cfg_idx] = req_line_speed;
7051         return rc;
7052 }
7053
7054 /* update flags in shmem */
7055 static void
7056 bnx2x_update_drv_flags(struct bnx2x_softc *sc, uint32_t flags, uint32_t set)
7057 {
7058         uint32_t drv_flags;
7059
7060         if (SHMEM2_HAS(sc, drv_flags)) {
7061                 bnx2x_acquire_hw_lock(sc, HW_LOCK_RESOURCE_DRV_FLAGS);
7062                 drv_flags = SHMEM2_RD(sc, drv_flags);
7063
7064                 if (set) {
7065                         drv_flags |= flags;
7066                 } else {
7067                         drv_flags &= ~flags;
7068                 }
7069
7070                 SHMEM2_WR(sc, drv_flags, drv_flags);
7071
7072                 bnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_DRV_FLAGS);
7073         }
7074 }
7075
7076 /* periodic timer callout routine, only runs when the interface is up */
7077 void bnx2x_periodic_callout(struct bnx2x_softc *sc)
7078 {
7079         if ((sc->state != BNX2X_STATE_OPEN) ||
7080             (atomic_load_acq_long(&sc->periodic_flags) == PERIODIC_STOP)) {
7081                 PMD_DRV_LOG(WARNING, "periodic callout exit (state=0x%x)",
7082                             sc->state);
7083                 return;
7084         }
7085         if (!CHIP_REV_IS_SLOW(sc)) {
7086 /*
7087  * This barrier is needed to ensure the ordering between the writing
7088  * to the sc->port.pmf in the bnx2x_nic_load() or bnx2x_pmf_update() and
7089  * the reading here.
7090  */
7091                 mb();
7092                 if (sc->port.pmf) {
7093                         elink_period_func(&sc->link_params, &sc->link_vars);
7094                 }
7095         }
7096 #ifdef BNX2X_PULSE
7097         if (IS_PF(sc) && !BNX2X_NOMCP(sc)) {
7098                 int mb_idx = SC_FW_MB_IDX(sc);
7099                 uint32_t drv_pulse;
7100                 uint32_t mcp_pulse;
7101
7102                 ++sc->fw_drv_pulse_wr_seq;
7103                 sc->fw_drv_pulse_wr_seq &= DRV_PULSE_SEQ_MASK;
7104
7105                 drv_pulse = sc->fw_drv_pulse_wr_seq;
7106                 bnx2x_drv_pulse(sc);
7107
7108                 mcp_pulse = (SHMEM_RD(sc, func_mb[mb_idx].mcp_pulse_mb) &
7109                              MCP_PULSE_SEQ_MASK);
7110
7111 /*
7112  * The delta between driver pulse and mcp response should
7113  * be 1 (before mcp response) or 0 (after mcp response).
7114  */
7115                 if ((drv_pulse != mcp_pulse) &&
7116                     (drv_pulse != ((mcp_pulse + 1) & MCP_PULSE_SEQ_MASK))) {
7117                         /* someone lost a heartbeat... */
7118                         PMD_DRV_LOG(ERR,
7119                                     "drv_pulse (0x%x) != mcp_pulse (0x%x)",
7120                                     drv_pulse, mcp_pulse);
7121                 }
7122         }
7123 #endif
7124 }
7125
7126 /* start the controller */
7127 static __rte_noinline
7128 int bnx2x_nic_load(struct bnx2x_softc *sc)
7129 {
7130         uint32_t val;
7131         uint32_t load_code = 0;
7132         int i, rc = 0;
7133
7134         PMD_INIT_FUNC_TRACE();
7135
7136         sc->state = BNX2X_STATE_OPENING_WAITING_LOAD;
7137
7138         if (IS_PF(sc)) {
7139 /* must be called before memory allocation and HW init */
7140                 bnx2x_ilt_set_info(sc);
7141         }
7142
7143         bnx2x_set_fp_rx_buf_size(sc);
7144
7145         if (IS_PF(sc)) {
7146                 if (bnx2x_alloc_mem(sc) != 0) {
7147                         sc->state = BNX2X_STATE_CLOSED;
7148                         rc = -ENOMEM;
7149                         goto bnx2x_nic_load_error0;
7150                 }
7151         }
7152
7153         if (bnx2x_alloc_fw_stats_mem(sc) != 0) {
7154                 sc->state = BNX2X_STATE_CLOSED;
7155                 rc = -ENOMEM;
7156                 goto bnx2x_nic_load_error0;
7157         }
7158
7159         if (IS_VF(sc)) {
7160                 rc = bnx2x_vf_init(sc);
7161                 if (rc) {
7162                         sc->state = BNX2X_STATE_ERROR;
7163                         goto bnx2x_nic_load_error0;
7164                 }
7165         }
7166
7167         if (IS_PF(sc)) {
7168 /* set pf load just before approaching the MCP */
7169                 bnx2x_set_pf_load(sc);
7170
7171 /* if MCP exists send load request and analyze response */
7172                 if (!BNX2X_NOMCP(sc)) {
7173                         /* attempt to load pf */
7174                         if (bnx2x_nic_load_request(sc, &load_code) != 0) {
7175                                 sc->state = BNX2X_STATE_CLOSED;
7176                                 rc = -ENXIO;
7177                                 goto bnx2x_nic_load_error1;
7178                         }
7179
7180                         /* what did the MCP say? */
7181                         if (bnx2x_nic_load_analyze_req(sc, load_code) != 0) {
7182                                 bnx2x_fw_command(sc, DRV_MSG_CODE_LOAD_DONE, 0);
7183                                 sc->state = BNX2X_STATE_CLOSED;
7184                                 rc = -ENXIO;
7185                                 goto bnx2x_nic_load_error2;
7186                         }
7187                 } else {
7188                         PMD_DRV_LOG(INFO, "Device has no MCP!");
7189                         load_code = bnx2x_nic_load_no_mcp(sc);
7190                 }
7191
7192 /* mark PMF if applicable */
7193                 bnx2x_nic_load_pmf(sc, load_code);
7194
7195 /* Init Function state controlling object */
7196                 bnx2x_init_func_obj(sc);
7197
7198 /* Initialize HW */
7199                 if (bnx2x_init_hw(sc, load_code) != 0) {
7200                         PMD_DRV_LOG(NOTICE, "HW init failed");
7201                         bnx2x_fw_command(sc, DRV_MSG_CODE_LOAD_DONE, 0);
7202                         sc->state = BNX2X_STATE_CLOSED;
7203                         rc = -ENXIO;
7204                         goto bnx2x_nic_load_error2;
7205                 }
7206         }
7207
7208         bnx2x_nic_init(sc, load_code);
7209
7210         /* Init per-function objects */
7211         if (IS_PF(sc)) {
7212                 bnx2x_init_objs(sc);
7213
7214 /* set AFEX default VLAN tag to an invalid value */
7215                 sc->devinfo.mf_info.afex_def_vlan_tag = -1;
7216
7217                 sc->state = BNX2X_STATE_OPENING_WAITING_PORT;
7218                 rc = bnx2x_func_start(sc);
7219                 if (rc) {
7220                         PMD_DRV_LOG(NOTICE, "Function start failed!");
7221                         bnx2x_fw_command(sc, DRV_MSG_CODE_LOAD_DONE, 0);
7222                         sc->state = BNX2X_STATE_ERROR;
7223                         goto bnx2x_nic_load_error3;
7224                 }
7225
7226 /* send LOAD_DONE command to MCP */
7227                 if (!BNX2X_NOMCP(sc)) {
7228                         load_code =
7229                             bnx2x_fw_command(sc, DRV_MSG_CODE_LOAD_DONE, 0);
7230                         if (!load_code) {
7231                                 PMD_DRV_LOG(NOTICE,
7232                                             "MCP response failure, aborting");
7233                                 sc->state = BNX2X_STATE_ERROR;
7234                                 rc = -ENXIO;
7235                                 goto bnx2x_nic_load_error3;
7236                         }
7237                 }
7238         }
7239
7240         rc = bnx2x_setup_leading(sc);
7241         if (rc) {
7242                 PMD_DRV_LOG(NOTICE, "Setup leading failed!");
7243                 sc->state = BNX2X_STATE_ERROR;
7244                 goto bnx2x_nic_load_error3;
7245         }
7246
7247         FOR_EACH_NONDEFAULT_ETH_QUEUE(sc, i) {
7248                 if (IS_PF(sc))
7249                         rc = bnx2x_setup_queue(sc, &sc->fp[i], FALSE);
7250                 else            /* IS_VF(sc) */
7251                         rc = bnx2x_vf_setup_queue(sc, &sc->fp[i], FALSE);
7252
7253                 if (rc) {
7254                         PMD_DRV_LOG(NOTICE, "Queue(%d) setup failed", i);
7255                         sc->state = BNX2X_STATE_ERROR;
7256                         goto bnx2x_nic_load_error3;
7257                 }
7258         }
7259
7260         rc = bnx2x_init_rss_pf(sc);
7261         if (rc) {
7262                 PMD_DRV_LOG(NOTICE, "PF RSS init failed");
7263                 sc->state = BNX2X_STATE_ERROR;
7264                 goto bnx2x_nic_load_error3;
7265         }
7266
7267         /* now when Clients are configured we are ready to work */
7268         sc->state = BNX2X_STATE_OPEN;
7269
7270         /* Configure a ucast MAC */
7271         if (IS_PF(sc)) {
7272                 rc = bnx2x_set_eth_mac(sc, TRUE);
7273         } else {                /* IS_VF(sc) */
7274                 rc = bnx2x_vf_set_mac(sc, TRUE);
7275         }
7276
7277         if (rc) {
7278                 PMD_DRV_LOG(NOTICE, "Setting Ethernet MAC failed");
7279                 sc->state = BNX2X_STATE_ERROR;
7280                 goto bnx2x_nic_load_error3;
7281         }
7282
7283         if (sc->port.pmf) {
7284                 rc = bnx2x_initial_phy_init(sc, LOAD_OPEN);
7285                 if (rc) {
7286                         sc->state = BNX2X_STATE_ERROR;
7287                         goto bnx2x_nic_load_error3;
7288                 }
7289         }
7290
7291         sc->link_params.feature_config_flags &=
7292             ~ELINK_FEATURE_CONFIG_BOOT_FROM_SAN;
7293
7294         /* start the Tx */
7295         switch (LOAD_OPEN) {
7296         case LOAD_NORMAL:
7297         case LOAD_OPEN:
7298                 break;
7299
7300         case LOAD_DIAG:
7301         case LOAD_LOOPBACK_EXT:
7302                 sc->state = BNX2X_STATE_DIAG;
7303                 break;
7304
7305         default:
7306                 break;
7307         }
7308
7309         if (sc->port.pmf) {
7310                 bnx2x_update_drv_flags(sc, 1 << DRV_FLAGS_PORT_MASK, 0);
7311         } else {
7312                 bnx2x_link_status_update(sc);
7313         }
7314
7315         if (IS_PF(sc) && SHMEM2_HAS(sc, drv_capabilities_flag)) {
7316 /* mark driver is loaded in shmem2 */
7317                 val = SHMEM2_RD(sc, drv_capabilities_flag[SC_FW_MB_IDX(sc)]);
7318                 SHMEM2_WR(sc, drv_capabilities_flag[SC_FW_MB_IDX(sc)],
7319                           (val |
7320                            DRV_FLAGS_CAPABILITIES_LOADED_SUPPORTED |
7321                            DRV_FLAGS_CAPABILITIES_LOADED_L2));
7322         }
7323
7324         /* start fast path */
7325         /* Initialize Rx filter */
7326         bnx2x_set_rx_mode(sc);
7327
7328         /* wait for all pending SP commands to complete */
7329         if (IS_PF(sc) && !bnx2x_wait_sp_comp(sc, ~0x0UL)) {
7330                 PMD_DRV_LOG(NOTICE, "Timeout waiting for all SPs to complete!");
7331                 bnx2x_periodic_stop(sc);
7332                 bnx2x_nic_unload(sc, UNLOAD_CLOSE, FALSE);
7333                 return -ENXIO;
7334         }
7335
7336         PMD_DRV_LOG(DEBUG, "NIC successfully loaded");
7337
7338         return 0;
7339
7340 bnx2x_nic_load_error3:
7341
7342         if (IS_PF(sc)) {
7343                 bnx2x_int_disable_sync(sc, 1);
7344
7345 /* clean out queued objects */
7346                 bnx2x_squeeze_objects(sc);
7347         }
7348
7349 bnx2x_nic_load_error2:
7350
7351         if (IS_PF(sc) && !BNX2X_NOMCP(sc)) {
7352                 bnx2x_fw_command(sc, DRV_MSG_CODE_UNLOAD_REQ_WOL_MCP, 0);
7353                 bnx2x_fw_command(sc, DRV_MSG_CODE_UNLOAD_DONE, 0);
7354         }
7355
7356         sc->port.pmf = 0;
7357
7358 bnx2x_nic_load_error1:
7359
7360         /* clear pf_load status, as it was already set */
7361         if (IS_PF(sc)) {
7362                 bnx2x_clear_pf_load(sc);
7363         }
7364
7365 bnx2x_nic_load_error0:
7366
7367         bnx2x_free_fw_stats_mem(sc);
7368         bnx2x_free_mem(sc);
7369
7370         return rc;
7371 }
7372
7373 /*
7374 * Handles controller initialization.
7375 */
7376 int bnx2x_init(struct bnx2x_softc *sc)
7377 {
7378         int other_engine = SC_PATH(sc) ? 0 : 1;
7379         uint8_t other_load_status, load_status;
7380         uint8_t global = FALSE;
7381         int rc;
7382
7383         /* Check if the driver is still running and bail out if it is. */
7384         if (sc->state != BNX2X_STATE_CLOSED) {
7385                 PMD_DRV_LOG(DEBUG, "Init called while driver is running!");
7386                 rc = 0;
7387                 goto bnx2x_init_done;
7388         }
7389
7390         bnx2x_set_power_state(sc, PCI_PM_D0);
7391
7392         /*
7393          * If parity occurred during the unload, then attentions and/or
7394          * RECOVERY_IN_PROGRESS may still be set. If so we want the first function
7395          * loaded on the current engine to complete the recovery. Parity recovery
7396          * is only relevant for PF driver.
7397          */
7398         if (IS_PF(sc)) {
7399                 other_load_status = bnx2x_get_load_status(sc, other_engine);
7400                 load_status = bnx2x_get_load_status(sc, SC_PATH(sc));
7401
7402                 if (!bnx2x_reset_is_done(sc, SC_PATH(sc)) ||
7403                     bnx2x_chk_parity_attn(sc, &global, TRUE)) {
7404                         do {
7405                                 /*
7406                                  * If there are attentions and they are in global blocks, set
7407                                  * the GLOBAL_RESET bit regardless whether it will be this
7408                                  * function that will complete the recovery or not.
7409                                  */
7410                                 if (global) {
7411                                         bnx2x_set_reset_global(sc);
7412                                 }
7413
7414                                 /*
7415                                  * Only the first function on the current engine should try
7416                                  * to recover in open. In case of attentions in global blocks
7417                                  * only the first in the chip should try to recover.
7418                                  */
7419                                 if ((!load_status
7420                                      && (!global ||!other_load_status))
7421                                     && bnx2x_trylock_leader_lock(sc)
7422                                     && !bnx2x_leader_reset(sc)) {
7423                                         PMD_DRV_LOG(INFO,
7424                                                     "Recovered during init");
7425                                         break;
7426                                 }
7427
7428                                 /* recovery has failed... */
7429                                 bnx2x_set_power_state(sc, PCI_PM_D3hot);
7430
7431                                 sc->recovery_state = BNX2X_RECOVERY_FAILED;
7432
7433                                 PMD_DRV_LOG(NOTICE,
7434                                             "Recovery flow hasn't properly "
7435                                             "completed yet, try again later. "
7436                                             "If you still see this message after a "
7437                                             "few retries then power cycle is required.");
7438
7439                                 rc = -ENXIO;
7440                                 goto bnx2x_init_done;
7441                         } while (0);
7442                 }
7443         }
7444
7445         sc->recovery_state = BNX2X_RECOVERY_DONE;
7446
7447         rc = bnx2x_nic_load(sc);
7448
7449 bnx2x_init_done:
7450
7451         if (rc) {
7452                 PMD_DRV_LOG(NOTICE, "Initialization failed, "
7453                             "stack notified driver is NOT running!");
7454         }
7455
7456         return rc;
7457 }
7458
7459 static void bnx2x_get_function_num(struct bnx2x_softc *sc)
7460 {
7461         uint32_t val = 0;
7462
7463         /*
7464          * Read the ME register to get the function number. The ME register
7465          * holds the relative-function number and absolute-function number. The
7466          * absolute-function number appears only in E2 and above. Before that
7467          * these bits always contained zero, therefore we cannot blindly use them.
7468          */
7469
7470         val = REG_RD(sc, BAR_ME_REGISTER);
7471
7472         sc->pfunc_rel =
7473             (uint8_t) ((val & ME_REG_PF_NUM) >> ME_REG_PF_NUM_SHIFT);
7474         sc->path_id =
7475             (uint8_t) ((val & ME_REG_ABS_PF_NUM) >> ME_REG_ABS_PF_NUM_SHIFT) &
7476             1;
7477
7478         if (CHIP_PORT_MODE(sc) == CHIP_4_PORT_MODE) {
7479                 sc->pfunc_abs = ((sc->pfunc_rel << 1) | sc->path_id);
7480         } else {
7481                 sc->pfunc_abs = (sc->pfunc_rel | sc->path_id);
7482         }
7483
7484         PMD_DRV_LOG(DEBUG,
7485                     "Relative function %d, Absolute function %d, Path %d",
7486                     sc->pfunc_rel, sc->pfunc_abs, sc->path_id);
7487 }
7488
7489 static uint32_t bnx2x_get_shmem_mf_cfg_base(struct bnx2x_softc *sc)
7490 {
7491         uint32_t shmem2_size;
7492         uint32_t offset;
7493         uint32_t mf_cfg_offset_value;
7494
7495         /* Non 57712 */
7496         offset = (SHMEM_ADDR(sc, func_mb) +
7497                   (MAX_FUNC_NUM * sizeof(struct drv_func_mb)));
7498
7499         /* 57712 plus */
7500         if (sc->devinfo.shmem2_base != 0) {
7501                 shmem2_size = SHMEM2_RD(sc, size);
7502                 if (shmem2_size > offsetof(struct shmem2_region, mf_cfg_addr)) {
7503                         mf_cfg_offset_value = SHMEM2_RD(sc, mf_cfg_addr);
7504                         if (SHMEM_MF_CFG_ADDR_NONE != mf_cfg_offset_value) {
7505                                 offset = mf_cfg_offset_value;
7506                         }
7507                 }
7508         }
7509
7510         return offset;
7511 }
7512
7513 static uint32_t bnx2x_pcie_capability_read(struct bnx2x_softc *sc, int reg)
7514 {
7515         uint32_t ret;
7516         struct bnx2x_pci_cap *caps;
7517
7518         /* ensure PCIe capability is enabled */
7519         caps = pci_find_cap(sc, PCIY_EXPRESS, BNX2X_PCI_CAP);
7520         if (NULL != caps) {
7521                 PMD_DRV_LOG(DEBUG, "Found PCIe capability: "
7522                             "id=0x%04X type=0x%04X addr=0x%08X",
7523                             caps->id, caps->type, caps->addr);
7524                 pci_read(sc, (caps->addr + reg), &ret, 2);
7525                 return ret;
7526         }
7527
7528         PMD_DRV_LOG(WARNING, "PCIe capability NOT FOUND!!!");
7529
7530         return 0;
7531 }
7532
7533 static uint8_t bnx2x_is_pcie_pending(struct bnx2x_softc *sc)
7534 {
7535         return bnx2x_pcie_capability_read(sc, PCIR_EXPRESS_DEVICE_STA) &
7536                 PCIM_EXP_STA_TRANSACTION_PND;
7537 }
7538
7539 /*
7540 * Walk the PCI capabiites list for the device to find what features are
7541 * supported. These capabilites may be enabled/disabled by firmware so it's
7542 * best to walk the list rather than make assumptions.
7543 */
7544 static void bnx2x_probe_pci_caps(struct bnx2x_softc *sc)
7545 {
7546         PMD_INIT_FUNC_TRACE();
7547
7548         struct bnx2x_pci_cap *caps;
7549         uint16_t link_status;
7550         int reg = 0;
7551
7552         /* check if PCI Power Management is enabled */
7553         caps = pci_find_cap(sc, PCIY_PMG, BNX2X_PCI_CAP);
7554         if (NULL != caps) {
7555                 PMD_DRV_LOG(DEBUG, "Found PM capability: "
7556                             "id=0x%04X type=0x%04X addr=0x%08X",
7557                             caps->id, caps->type, caps->addr);
7558
7559                 sc->devinfo.pcie_cap_flags |= BNX2X_PM_CAPABLE_FLAG;
7560                 sc->devinfo.pcie_pm_cap_reg = caps->addr;
7561         }
7562
7563         link_status = bnx2x_pcie_capability_read(sc, PCIR_EXPRESS_LINK_STA);
7564
7565         sc->devinfo.pcie_link_speed = (link_status & PCIM_LINK_STA_SPEED);
7566         sc->devinfo.pcie_link_width =
7567             ((link_status & PCIM_LINK_STA_WIDTH) >> 4);
7568
7569         PMD_DRV_LOG(DEBUG, "PCIe link speed=%d width=%d",
7570                     sc->devinfo.pcie_link_speed, sc->devinfo.pcie_link_width);
7571
7572         sc->devinfo.pcie_cap_flags |= BNX2X_PCIE_CAPABLE_FLAG;
7573
7574         /* check if MSI capability is enabled */
7575         caps = pci_find_cap(sc, PCIY_MSI, BNX2X_PCI_CAP);
7576         if (NULL != caps) {
7577                 PMD_DRV_LOG(DEBUG, "Found MSI capability at 0x%04x", reg);
7578
7579                 sc->devinfo.pcie_cap_flags |= BNX2X_MSI_CAPABLE_FLAG;
7580                 sc->devinfo.pcie_msi_cap_reg = caps->addr;
7581         }
7582
7583         /* check if MSI-X capability is enabled */
7584         caps = pci_find_cap(sc, PCIY_MSIX, BNX2X_PCI_CAP);
7585         if (NULL != caps) {
7586                 PMD_DRV_LOG(DEBUG, "Found MSI-X capability at 0x%04x", reg);
7587
7588                 sc->devinfo.pcie_cap_flags |= BNX2X_MSIX_CAPABLE_FLAG;
7589                 sc->devinfo.pcie_msix_cap_reg = caps->addr;
7590         }
7591 }
7592
7593 static int bnx2x_get_shmem_mf_cfg_info_sd(struct bnx2x_softc *sc)
7594 {
7595         struct bnx2x_mf_info *mf_info = &sc->devinfo.mf_info;
7596         uint32_t val;
7597
7598         /* get the outer vlan if we're in switch-dependent mode */
7599
7600         val = MFCFG_RD(sc, func_mf_config[SC_ABS_FUNC(sc)].e1hov_tag);
7601         mf_info->ext_id = (uint16_t) val;
7602
7603         mf_info->multi_vnics_mode = 1;
7604
7605         if (!VALID_OVLAN(mf_info->ext_id)) {
7606                 PMD_DRV_LOG(NOTICE, "Invalid VLAN (%d)", mf_info->ext_id);
7607                 return 1;
7608         }
7609
7610         /* get the capabilities */
7611         if ((mf_info->mf_config[SC_VN(sc)] & FUNC_MF_CFG_PROTOCOL_MASK) ==
7612             FUNC_MF_CFG_PROTOCOL_ISCSI) {
7613                 mf_info->mf_protos_supported |= MF_PROTO_SUPPORT_ISCSI;
7614         } else if ((mf_info->mf_config[SC_VN(sc)] & FUNC_MF_CFG_PROTOCOL_MASK)
7615                    == FUNC_MF_CFG_PROTOCOL_FCOE) {
7616                 mf_info->mf_protos_supported |= MF_PROTO_SUPPORT_FCOE;
7617         } else {
7618                 mf_info->mf_protos_supported |= MF_PROTO_SUPPORT_ETHERNET;
7619         }
7620
7621         mf_info->vnics_per_port =
7622             (CHIP_PORT_MODE(sc) == CHIP_4_PORT_MODE) ? 2 : 4;
7623
7624         return 0;
7625 }
7626
7627 static uint32_t bnx2x_get_shmem_ext_proto_support_flags(struct bnx2x_softc *sc)
7628 {
7629         uint32_t retval = 0;
7630         uint32_t val;
7631
7632         val = MFCFG_RD(sc, func_ext_config[SC_ABS_FUNC(sc)].func_cfg);
7633
7634         if (val & MACP_FUNC_CFG_FLAGS_ENABLED) {
7635                 if (val & MACP_FUNC_CFG_FLAGS_ETHERNET) {
7636                         retval |= MF_PROTO_SUPPORT_ETHERNET;
7637                 }
7638                 if (val & MACP_FUNC_CFG_FLAGS_ISCSI_OFFLOAD) {
7639                         retval |= MF_PROTO_SUPPORT_ISCSI;
7640                 }
7641                 if (val & MACP_FUNC_CFG_FLAGS_FCOE_OFFLOAD) {
7642                         retval |= MF_PROTO_SUPPORT_FCOE;
7643                 }
7644         }
7645
7646         return retval;
7647 }
7648
7649 static int bnx2x_get_shmem_mf_cfg_info_si(struct bnx2x_softc *sc)
7650 {
7651         struct bnx2x_mf_info *mf_info = &sc->devinfo.mf_info;
7652         uint32_t val;
7653
7654         /*
7655          * There is no outer vlan if we're in switch-independent mode.
7656          * If the mac is valid then assume multi-function.
7657          */
7658
7659         val = MFCFG_RD(sc, func_ext_config[SC_ABS_FUNC(sc)].func_cfg);
7660
7661         mf_info->multi_vnics_mode = ((val & MACP_FUNC_CFG_FLAGS_MASK) != 0);
7662
7663         mf_info->mf_protos_supported =
7664             bnx2x_get_shmem_ext_proto_support_flags(sc);
7665
7666         mf_info->vnics_per_port =
7667             (CHIP_PORT_MODE(sc) == CHIP_4_PORT_MODE) ? 2 : 4;
7668
7669         return 0;
7670 }
7671
7672 static int bnx2x_get_shmem_mf_cfg_info_niv(struct bnx2x_softc *sc)
7673 {
7674         struct bnx2x_mf_info *mf_info = &sc->devinfo.mf_info;
7675         uint32_t e1hov_tag;
7676         uint32_t func_config;
7677         uint32_t niv_config;
7678
7679         mf_info->multi_vnics_mode = 1;
7680
7681         e1hov_tag = MFCFG_RD(sc, func_mf_config[SC_ABS_FUNC(sc)].e1hov_tag);
7682         func_config = MFCFG_RD(sc, func_mf_config[SC_ABS_FUNC(sc)].config);
7683         niv_config = MFCFG_RD(sc, func_mf_config[SC_ABS_FUNC(sc)].afex_config);
7684
7685         mf_info->ext_id =
7686             (uint16_t) ((e1hov_tag & FUNC_MF_CFG_E1HOV_TAG_MASK) >>
7687                         FUNC_MF_CFG_E1HOV_TAG_SHIFT);
7688
7689         mf_info->default_vlan =
7690             (uint16_t) ((e1hov_tag & FUNC_MF_CFG_AFEX_VLAN_MASK) >>
7691                         FUNC_MF_CFG_AFEX_VLAN_SHIFT);
7692
7693         mf_info->niv_allowed_priorities =
7694             (uint8_t) ((niv_config & FUNC_MF_CFG_AFEX_COS_FILTER_MASK) >>
7695                        FUNC_MF_CFG_AFEX_COS_FILTER_SHIFT);
7696
7697         mf_info->niv_default_cos =
7698             (uint8_t) ((func_config & FUNC_MF_CFG_TRANSMIT_PRIORITY_MASK) >>
7699                        FUNC_MF_CFG_TRANSMIT_PRIORITY_SHIFT);
7700
7701         mf_info->afex_vlan_mode =
7702             ((niv_config & FUNC_MF_CFG_AFEX_VLAN_MODE_MASK) >>
7703              FUNC_MF_CFG_AFEX_VLAN_MODE_SHIFT);
7704
7705         mf_info->niv_mba_enabled =
7706             ((niv_config & FUNC_MF_CFG_AFEX_MBA_ENABLED_MASK) >>
7707              FUNC_MF_CFG_AFEX_MBA_ENABLED_SHIFT);
7708
7709         mf_info->mf_protos_supported =
7710             bnx2x_get_shmem_ext_proto_support_flags(sc);
7711
7712         mf_info->vnics_per_port =
7713             (CHIP_PORT_MODE(sc) == CHIP_4_PORT_MODE) ? 2 : 4;
7714
7715         return 0;
7716 }
7717
7718 static int bnx2x_check_valid_mf_cfg(struct bnx2x_softc *sc)
7719 {
7720         struct bnx2x_mf_info *mf_info = &sc->devinfo.mf_info;
7721         uint32_t mf_cfg1;
7722         uint32_t mf_cfg2;
7723         uint32_t ovlan1;
7724         uint32_t ovlan2;
7725         uint8_t i, j;
7726
7727         /* various MF mode sanity checks... */
7728
7729         if (mf_info->mf_config[SC_VN(sc)] & FUNC_MF_CFG_FUNC_HIDE) {
7730                 PMD_DRV_LOG(NOTICE,
7731                             "Enumerated function %d is marked as hidden",
7732                             SC_PORT(sc));
7733                 return 1;
7734         }
7735
7736         if ((mf_info->vnics_per_port > 1) && !mf_info->multi_vnics_mode) {
7737                 PMD_DRV_LOG(NOTICE, "vnics_per_port=%d multi_vnics_mode=%d",
7738                             mf_info->vnics_per_port, mf_info->multi_vnics_mode);
7739                 return 1;
7740         }
7741
7742         if (mf_info->mf_mode == MULTI_FUNCTION_SD) {
7743 /* vnic id > 0 must have valid ovlan in switch-dependent mode */
7744                 if ((SC_VN(sc) > 0) && !VALID_OVLAN(OVLAN(sc))) {
7745                         PMD_DRV_LOG(NOTICE, "mf_mode=SD vnic_id=%d ovlan=%d",
7746                                     SC_VN(sc), OVLAN(sc));
7747                         return 1;
7748                 }
7749
7750                 if (!VALID_OVLAN(OVLAN(sc)) && mf_info->multi_vnics_mode) {
7751                         PMD_DRV_LOG(NOTICE,
7752                                     "mf_mode=SD multi_vnics_mode=%d ovlan=%d",
7753                                     mf_info->multi_vnics_mode, OVLAN(sc));
7754                         return 1;
7755                 }
7756
7757 /*
7758  * Verify all functions are either MF or SF mode. If MF, make sure
7759  * sure that all non-hidden functions have a valid ovlan. If SF,
7760  * make sure that all non-hidden functions have an invalid ovlan.
7761  */
7762                 FOREACH_ABS_FUNC_IN_PORT(sc, i) {
7763                         mf_cfg1 = MFCFG_RD(sc, func_mf_config[i].config);
7764                         ovlan1 = MFCFG_RD(sc, func_mf_config[i].e1hov_tag);
7765                         if (!(mf_cfg1 & FUNC_MF_CFG_FUNC_HIDE) &&
7766                             (((mf_info->multi_vnics_mode)
7767                               && !VALID_OVLAN(ovlan1))
7768                              || ((!mf_info->multi_vnics_mode)
7769                                  && VALID_OVLAN(ovlan1)))) {
7770                                 PMD_DRV_LOG(NOTICE,
7771                                             "mf_mode=SD function %d MF config "
7772                                             "mismatch, multi_vnics_mode=%d ovlan=%d",
7773                                             i, mf_info->multi_vnics_mode,
7774                                             ovlan1);
7775                                 return 1;
7776                         }
7777                 }
7778
7779 /* Verify all funcs on the same port each have a different ovlan. */
7780                 FOREACH_ABS_FUNC_IN_PORT(sc, i) {
7781                         mf_cfg1 = MFCFG_RD(sc, func_mf_config[i].config);
7782                         ovlan1 = MFCFG_RD(sc, func_mf_config[i].e1hov_tag);
7783                         /* iterate from the next function on the port to the max func */
7784                         for (j = i + 2; j < MAX_FUNC_NUM; j += 2) {
7785                                 mf_cfg2 =
7786                                     MFCFG_RD(sc, func_mf_config[j].config);
7787                                 ovlan2 =
7788                                     MFCFG_RD(sc, func_mf_config[j].e1hov_tag);
7789                                 if (!(mf_cfg1 & FUNC_MF_CFG_FUNC_HIDE)
7790                                     && VALID_OVLAN(ovlan1)
7791                                     && !(mf_cfg2 & FUNC_MF_CFG_FUNC_HIDE)
7792                                     && VALID_OVLAN(ovlan2)
7793                                     && (ovlan1 == ovlan2)) {
7794                                         PMD_DRV_LOG(NOTICE,
7795                                                     "mf_mode=SD functions %d and %d "
7796                                                     "have the same ovlan (%d)",
7797                                                     i, j, ovlan1);
7798                                         return 1;
7799                                 }
7800                         }
7801                 }
7802         }
7803         /* MULTI_FUNCTION_SD */
7804         return 0;
7805 }
7806
7807 static int bnx2x_get_mf_cfg_info(struct bnx2x_softc *sc)
7808 {
7809         struct bnx2x_mf_info *mf_info = &sc->devinfo.mf_info;
7810         uint32_t val, mac_upper;
7811         uint8_t i, vnic;
7812
7813         /* initialize mf_info defaults */
7814         mf_info->vnics_per_port = 1;
7815         mf_info->multi_vnics_mode = FALSE;
7816         mf_info->path_has_ovlan = FALSE;
7817         mf_info->mf_mode = SINGLE_FUNCTION;
7818
7819         if (!CHIP_IS_MF_CAP(sc)) {
7820                 return 0;
7821         }
7822
7823         if (sc->devinfo.mf_cfg_base == SHMEM_MF_CFG_ADDR_NONE) {
7824                 PMD_DRV_LOG(NOTICE, "Invalid mf_cfg_base!");
7825                 return 1;
7826         }
7827
7828         /* get the MF mode (switch dependent / independent / single-function) */
7829
7830         val = SHMEM_RD(sc, dev_info.shared_feature_config.config);
7831
7832         switch (val & SHARED_FEAT_CFG_FORCE_SF_MODE_MASK) {
7833         case SHARED_FEAT_CFG_FORCE_SF_MODE_SWITCH_INDEPT:
7834
7835                 mac_upper =
7836                     MFCFG_RD(sc, func_mf_config[SC_ABS_FUNC(sc)].mac_upper);
7837
7838                 /* check for legal upper mac bytes */
7839                 if (mac_upper != FUNC_MF_CFG_UPPERMAC_DEFAULT) {
7840                         mf_info->mf_mode = MULTI_FUNCTION_SI;
7841                 } else {
7842                         PMD_DRV_LOG(NOTICE,
7843                                     "Invalid config for Switch Independent mode");
7844                 }
7845
7846                 break;
7847
7848         case SHARED_FEAT_CFG_FORCE_SF_MODE_MF_ALLOWED:
7849         case SHARED_FEAT_CFG_FORCE_SF_MODE_SPIO4:
7850
7851                 /* get outer vlan configuration */
7852                 val = MFCFG_RD(sc, func_mf_config[SC_ABS_FUNC(sc)].e1hov_tag);
7853
7854                 if ((val & FUNC_MF_CFG_E1HOV_TAG_MASK) !=
7855                     FUNC_MF_CFG_E1HOV_TAG_DEFAULT) {
7856                         mf_info->mf_mode = MULTI_FUNCTION_SD;
7857                 } else {
7858                         PMD_DRV_LOG(NOTICE,
7859                                     "Invalid config for Switch Dependent mode");
7860                 }
7861
7862                 break;
7863
7864         case SHARED_FEAT_CFG_FORCE_SF_MODE_FORCED_SF:
7865
7866                 /* not in MF mode, vnics_per_port=1 and multi_vnics_mode=FALSE */
7867                 return 0;
7868
7869         case SHARED_FEAT_CFG_FORCE_SF_MODE_AFEX_MODE:
7870
7871                 /*
7872                  * Mark MF mode as NIV if MCP version includes NPAR-SD support
7873                  * and the MAC address is valid.
7874                  */
7875                 mac_upper =
7876                     MFCFG_RD(sc, func_mf_config[SC_ABS_FUNC(sc)].mac_upper);
7877
7878                 if ((SHMEM2_HAS(sc, afex_driver_support)) &&
7879                     (mac_upper != FUNC_MF_CFG_UPPERMAC_DEFAULT)) {
7880                         mf_info->mf_mode = MULTI_FUNCTION_AFEX;
7881                 } else {
7882                         PMD_DRV_LOG(NOTICE, "Invalid config for AFEX mode");
7883                 }
7884
7885                 break;
7886
7887         default:
7888
7889                 PMD_DRV_LOG(NOTICE, "Unknown MF mode (0x%08x)",
7890                             (val & SHARED_FEAT_CFG_FORCE_SF_MODE_MASK));
7891
7892                 return 1;
7893         }
7894
7895         /* set path mf_mode (which could be different than function mf_mode) */
7896         if (mf_info->mf_mode == MULTI_FUNCTION_SD) {
7897                 mf_info->path_has_ovlan = TRUE;
7898         } else if (mf_info->mf_mode == SINGLE_FUNCTION) {
7899 /*
7900  * Decide on path multi vnics mode. If we're not in MF mode and in
7901  * 4-port mode, this is good enough to check vnic-0 of the other port
7902  * on the same path
7903  */
7904                 if (CHIP_PORT_MODE(sc) == CHIP_4_PORT_MODE) {
7905                         uint8_t other_port = !(PORT_ID(sc) & 1);
7906                         uint8_t abs_func_other_port =
7907                             (SC_PATH(sc) + (2 * other_port));
7908
7909                         val =
7910                             MFCFG_RD(sc,
7911                                      func_mf_config
7912                                      [abs_func_other_port].e1hov_tag);
7913
7914                         mf_info->path_has_ovlan = VALID_OVLAN((uint16_t) val);
7915                 }
7916         }
7917
7918         if (mf_info->mf_mode == SINGLE_FUNCTION) {
7919 /* invalid MF config */
7920                 if (SC_VN(sc) >= 1) {
7921                         PMD_DRV_LOG(NOTICE, "VNIC ID >= 1 in SF mode");
7922                         return 1;
7923                 }
7924
7925                 return 0;
7926         }
7927
7928         /* get the MF configuration */
7929         mf_info->mf_config[SC_VN(sc)] =
7930             MFCFG_RD(sc, func_mf_config[SC_ABS_FUNC(sc)].config);
7931
7932         switch (mf_info->mf_mode) {
7933         case MULTI_FUNCTION_SD:
7934
7935                 bnx2x_get_shmem_mf_cfg_info_sd(sc);
7936                 break;
7937
7938         case MULTI_FUNCTION_SI:
7939
7940                 bnx2x_get_shmem_mf_cfg_info_si(sc);
7941                 break;
7942
7943         case MULTI_FUNCTION_AFEX:
7944
7945                 bnx2x_get_shmem_mf_cfg_info_niv(sc);
7946                 break;
7947
7948         default:
7949
7950                 PMD_DRV_LOG(NOTICE, "Get MF config failed (mf_mode=0x%08x)",
7951                             mf_info->mf_mode);
7952                 return 1;
7953         }
7954
7955         /* get the congestion management parameters */
7956
7957         vnic = 0;
7958         FOREACH_ABS_FUNC_IN_PORT(sc, i) {
7959 /* get min/max bw */
7960                 val = MFCFG_RD(sc, func_mf_config[i].config);
7961                 mf_info->min_bw[vnic] =
7962                     ((val & FUNC_MF_CFG_MIN_BW_MASK) >>
7963                      FUNC_MF_CFG_MIN_BW_SHIFT);
7964                 mf_info->max_bw[vnic] =
7965                     ((val & FUNC_MF_CFG_MAX_BW_MASK) >>
7966                      FUNC_MF_CFG_MAX_BW_SHIFT);
7967                 vnic++;
7968         }
7969
7970         return bnx2x_check_valid_mf_cfg(sc);
7971 }
7972
7973 static int bnx2x_get_shmem_info(struct bnx2x_softc *sc)
7974 {
7975         int port;
7976         uint32_t mac_hi, mac_lo, val;
7977
7978         PMD_INIT_FUNC_TRACE();
7979
7980         port = SC_PORT(sc);
7981         mac_hi = mac_lo = 0;
7982
7983         sc->link_params.sc = sc;
7984         sc->link_params.port = port;
7985
7986         /* get the hardware config info */
7987         sc->devinfo.hw_config = SHMEM_RD(sc, dev_info.shared_hw_config.config);
7988         sc->devinfo.hw_config2 =
7989             SHMEM_RD(sc, dev_info.shared_hw_config.config2);
7990
7991         sc->link_params.hw_led_mode =
7992             ((sc->devinfo.hw_config & SHARED_HW_CFG_LED_MODE_MASK) >>
7993              SHARED_HW_CFG_LED_MODE_SHIFT);
7994
7995         /* get the port feature config */
7996         sc->port.config =
7997             SHMEM_RD(sc, dev_info.port_feature_config[port].config);
7998
7999         /* get the link params */
8000         sc->link_params.speed_cap_mask[ELINK_INT_PHY] =
8001             SHMEM_RD(sc, dev_info.port_hw_config[port].speed_capability_mask)
8002             & PORT_HW_CFG_SPEED_CAPABILITY_D0_MASK;
8003         sc->link_params.speed_cap_mask[ELINK_EXT_PHY1] =
8004             SHMEM_RD(sc, dev_info.port_hw_config[port].speed_capability_mask2)
8005             & PORT_HW_CFG_SPEED_CAPABILITY_D0_MASK;
8006
8007         /* get the lane config */
8008         sc->link_params.lane_config =
8009             SHMEM_RD(sc, dev_info.port_hw_config[port].lane_config);
8010
8011         /* get the link config */
8012         val = SHMEM_RD(sc, dev_info.port_feature_config[port].link_config);
8013         sc->port.link_config[ELINK_INT_PHY] = val;
8014         sc->link_params.switch_cfg = (val & PORT_FEATURE_CONNECTED_SWITCH_MASK);
8015         sc->port.link_config[ELINK_EXT_PHY1] =
8016             SHMEM_RD(sc, dev_info.port_feature_config[port].link_config2);
8017
8018         /* get the override preemphasis flag and enable it or turn it off */
8019         val = SHMEM_RD(sc, dev_info.shared_feature_config.config);
8020         if (val & SHARED_FEAT_CFG_OVERRIDE_PREEMPHASIS_CFG_ENABLED) {
8021                 sc->link_params.feature_config_flags |=
8022                     ELINK_FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED;
8023         } else {
8024                 sc->link_params.feature_config_flags &=
8025                     ~ELINK_FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED;
8026         }
8027
8028         /* get the initial value of the link params */
8029         sc->link_params.multi_phy_config =
8030             SHMEM_RD(sc, dev_info.port_hw_config[port].multi_phy_config);
8031
8032         /* get external phy info */
8033         sc->port.ext_phy_config =
8034             SHMEM_RD(sc, dev_info.port_hw_config[port].external_phy_config);
8035
8036         /* get the multifunction configuration */
8037         bnx2x_get_mf_cfg_info(sc);
8038
8039         /* get the mac address */
8040         if (IS_MF(sc)) {
8041                 mac_hi =
8042                     MFCFG_RD(sc, func_mf_config[SC_ABS_FUNC(sc)].mac_upper);
8043                 mac_lo =
8044                     MFCFG_RD(sc, func_mf_config[SC_ABS_FUNC(sc)].mac_lower);
8045         } else {
8046                 mac_hi = SHMEM_RD(sc, dev_info.port_hw_config[port].mac_upper);
8047                 mac_lo = SHMEM_RD(sc, dev_info.port_hw_config[port].mac_lower);
8048         }
8049
8050         if ((mac_lo == 0) && (mac_hi == 0)) {
8051                 *sc->mac_addr_str = 0;
8052                 PMD_DRV_LOG(NOTICE, "No Ethernet address programmed!");
8053         } else {
8054                 sc->link_params.mac_addr[0] = (uint8_t) (mac_hi >> 8);
8055                 sc->link_params.mac_addr[1] = (uint8_t) (mac_hi);
8056                 sc->link_params.mac_addr[2] = (uint8_t) (mac_lo >> 24);
8057                 sc->link_params.mac_addr[3] = (uint8_t) (mac_lo >> 16);
8058                 sc->link_params.mac_addr[4] = (uint8_t) (mac_lo >> 8);
8059                 sc->link_params.mac_addr[5] = (uint8_t) (mac_lo);
8060                 snprintf(sc->mac_addr_str, sizeof(sc->mac_addr_str),
8061                          "%02x:%02x:%02x:%02x:%02x:%02x",
8062                          sc->link_params.mac_addr[0],
8063                          sc->link_params.mac_addr[1],
8064                          sc->link_params.mac_addr[2],
8065                          sc->link_params.mac_addr[3],
8066                          sc->link_params.mac_addr[4],
8067                          sc->link_params.mac_addr[5]);
8068                 PMD_DRV_LOG(DEBUG, "Ethernet address: %s", sc->mac_addr_str);
8069         }
8070
8071         return 0;
8072 }
8073
8074 static void bnx2x_media_detect(struct bnx2x_softc *sc)
8075 {
8076         uint32_t phy_idx = bnx2x_get_cur_phy_idx(sc);
8077         switch (sc->link_params.phy[phy_idx].media_type) {
8078         case ELINK_ETH_PHY_SFPP_10G_FIBER:
8079         case ELINK_ETH_PHY_SFP_1G_FIBER:
8080         case ELINK_ETH_PHY_XFP_FIBER:
8081         case ELINK_ETH_PHY_KR:
8082         case ELINK_ETH_PHY_CX4:
8083                 PMD_DRV_LOG(INFO, "Found 10GBase-CX4 media.");
8084                 sc->media = IFM_10G_CX4;
8085                 break;
8086         case ELINK_ETH_PHY_DA_TWINAX:
8087                 PMD_DRV_LOG(INFO, "Found 10Gb Twinax media.");
8088                 sc->media = IFM_10G_TWINAX;
8089                 break;
8090         case ELINK_ETH_PHY_BASE_T:
8091                 PMD_DRV_LOG(INFO, "Found 10GBase-T media.");
8092                 sc->media = IFM_10G_T;
8093                 break;
8094         case ELINK_ETH_PHY_NOT_PRESENT:
8095                 PMD_DRV_LOG(INFO, "Media not present.");
8096                 sc->media = 0;
8097                 break;
8098         case ELINK_ETH_PHY_UNSPECIFIED:
8099         default:
8100                 PMD_DRV_LOG(INFO, "Unknown media!");
8101                 sc->media = 0;
8102                 break;
8103         }
8104 }
8105
8106 #define GET_FIELD(value, fname)                     \
8107 (((value) & (fname##_MASK)) >> (fname##_SHIFT))
8108 #define IGU_FID(val) GET_FIELD((val), IGU_REG_MAPPING_MEMORY_FID)
8109 #define IGU_VEC(val) GET_FIELD((val), IGU_REG_MAPPING_MEMORY_VECTOR)
8110
8111 static int bnx2x_get_igu_cam_info(struct bnx2x_softc *sc)
8112 {
8113         int pfid = SC_FUNC(sc);
8114         int igu_sb_id;
8115         uint32_t val;
8116         uint8_t fid, igu_sb_cnt = 0;
8117
8118         sc->igu_base_sb = 0xff;
8119
8120         if (CHIP_INT_MODE_IS_BC(sc)) {
8121                 int vn = SC_VN(sc);
8122                 igu_sb_cnt = sc->igu_sb_cnt;
8123                 sc->igu_base_sb = ((CHIP_IS_MODE_4_PORT(sc) ? pfid : vn) *
8124                                    FP_SB_MAX_E1x);
8125                 sc->igu_dsb_id = (E1HVN_MAX * FP_SB_MAX_E1x +
8126                                   (CHIP_IS_MODE_4_PORT(sc) ? pfid : vn));
8127                 return 0;
8128         }
8129
8130         /* IGU in normal mode - read CAM */
8131         for (igu_sb_id = 0;
8132              igu_sb_id < IGU_REG_MAPPING_MEMORY_SIZE; igu_sb_id++) {
8133                 val = REG_RD(sc, IGU_REG_MAPPING_MEMORY + igu_sb_id * 4);
8134                 if (!(val & IGU_REG_MAPPING_MEMORY_VALID)) {
8135                         continue;
8136                 }
8137                 fid = IGU_FID(val);
8138                 if (fid & IGU_FID_ENCODE_IS_PF) {
8139                         if ((fid & IGU_FID_PF_NUM_MASK) != pfid) {
8140                                 continue;
8141                         }
8142                         if (IGU_VEC(val) == 0) {
8143                                 /* default status block */
8144                                 sc->igu_dsb_id = igu_sb_id;
8145                         } else {
8146                                 if (sc->igu_base_sb == 0xff) {
8147                                         sc->igu_base_sb = igu_sb_id;
8148                                 }
8149                                 igu_sb_cnt++;
8150                         }
8151                 }
8152         }
8153
8154         /*
8155          * Due to new PF resource allocation by MFW T7.4 and above, it's optional
8156          * that number of CAM entries will not be equal to the value advertised in
8157          * PCI. Driver should use the minimal value of both as the actual status
8158          * block count
8159          */
8160         sc->igu_sb_cnt = min(sc->igu_sb_cnt, igu_sb_cnt);
8161
8162         if (igu_sb_cnt == 0) {
8163                 PMD_DRV_LOG(ERR, "CAM configuration error");
8164                 return -1;
8165         }
8166
8167         return 0;
8168 }
8169
8170 /*
8171 * Gather various information from the device config space, the device itself,
8172 * shmem, and the user input.
8173 */
8174 static int bnx2x_get_device_info(struct bnx2x_softc *sc)
8175 {
8176         uint32_t val;
8177         int rc;
8178
8179         /* get the chip revision (chip metal comes from pci config space) */
8180         sc->devinfo.chip_id = sc->link_params.chip_id =
8181             (((REG_RD(sc, MISC_REG_CHIP_NUM) & 0xffff) << 16) |
8182              ((REG_RD(sc, MISC_REG_CHIP_REV) & 0xf) << 12) |
8183              (((REG_RD(sc, PCICFG_OFFSET + PCI_ID_VAL3) >> 24) & 0xf) << 4) |
8184              ((REG_RD(sc, MISC_REG_BOND_ID) & 0xf) << 0));
8185
8186         /* force 57811 according to MISC register */
8187         if (REG_RD(sc, MISC_REG_CHIP_TYPE) & MISC_REG_CHIP_TYPE_57811_MASK) {
8188                 if (CHIP_IS_57810(sc)) {
8189                         sc->devinfo.chip_id = ((CHIP_NUM_57811 << 16) |
8190                                                (sc->
8191                                                 devinfo.chip_id & 0x0000ffff));
8192                 } else if (CHIP_IS_57810_MF(sc)) {
8193                         sc->devinfo.chip_id = ((CHIP_NUM_57811_MF << 16) |
8194                                                (sc->
8195                                                 devinfo.chip_id & 0x0000ffff));
8196                 }
8197                 sc->devinfo.chip_id |= 0x1;
8198         }
8199
8200         PMD_DRV_LOG(DEBUG,
8201                     "chip_id=0x%08x (num=0x%04x rev=0x%01x metal=0x%02x bond=0x%01x)",
8202                     sc->devinfo.chip_id,
8203                     ((sc->devinfo.chip_id >> 16) & 0xffff),
8204                     ((sc->devinfo.chip_id >> 12) & 0xf),
8205                     ((sc->devinfo.chip_id >> 4) & 0xff),
8206                     ((sc->devinfo.chip_id >> 0) & 0xf));
8207
8208         val = (REG_RD(sc, 0x2874) & 0x55);
8209         if ((sc->devinfo.chip_id & 0x1) || (CHIP_IS_E1H(sc) && (val == 0x55))) {
8210                 sc->flags |= BNX2X_ONE_PORT_FLAG;
8211                 PMD_DRV_LOG(DEBUG, "single port device");
8212         }
8213
8214         /* set the doorbell size */
8215         sc->doorbell_size = (1 << BNX2X_DB_SHIFT);
8216
8217         /* determine whether the device is in 2 port or 4 port mode */
8218         sc->devinfo.chip_port_mode = CHIP_PORT_MODE_NONE;       /* E1h */
8219         if (CHIP_IS_E2E3(sc)) {
8220 /*
8221  * Read port4mode_en_ovwr[0]:
8222  *   If 1, four port mode is in port4mode_en_ovwr[1].
8223  *   If 0, four port mode is in port4mode_en[0].
8224  */
8225                 val = REG_RD(sc, MISC_REG_PORT4MODE_EN_OVWR);
8226                 if (val & 1) {
8227                         val = ((val >> 1) & 1);
8228                 } else {
8229                         val = REG_RD(sc, MISC_REG_PORT4MODE_EN);
8230                 }
8231
8232                 sc->devinfo.chip_port_mode =
8233                     (val) ? CHIP_4_PORT_MODE : CHIP_2_PORT_MODE;
8234
8235                 PMD_DRV_LOG(DEBUG, "Port mode = %s", (val) ? "4" : "2");
8236         }
8237
8238         /* get the function and path info for the device */
8239         bnx2x_get_function_num(sc);
8240
8241         /* get the shared memory base address */
8242         sc->devinfo.shmem_base =
8243             sc->link_params.shmem_base = REG_RD(sc, MISC_REG_SHARED_MEM_ADDR);
8244         sc->devinfo.shmem2_base =
8245             REG_RD(sc, (SC_PATH(sc) ? MISC_REG_GENERIC_CR_1 :
8246                         MISC_REG_GENERIC_CR_0));
8247
8248         if (!sc->devinfo.shmem_base) {
8249 /* this should ONLY prevent upcoming shmem reads */
8250                 PMD_DRV_LOG(INFO, "MCP not active");
8251                 sc->flags |= BNX2X_NO_MCP_FLAG;
8252                 return 0;
8253         }
8254
8255         /* make sure the shared memory contents are valid */
8256         val = SHMEM_RD(sc, validity_map[SC_PORT(sc)]);
8257         if ((val & (SHR_MEM_VALIDITY_DEV_INFO | SHR_MEM_VALIDITY_MB)) !=
8258             (SHR_MEM_VALIDITY_DEV_INFO | SHR_MEM_VALIDITY_MB)) {
8259                 PMD_DRV_LOG(NOTICE, "Invalid SHMEM validity signature: 0x%08x",
8260                             val);
8261                 return 0;
8262         }
8263
8264         /* get the bootcode version */
8265         sc->devinfo.bc_ver = SHMEM_RD(sc, dev_info.bc_rev);
8266         snprintf(sc->devinfo.bc_ver_str,
8267                  sizeof(sc->devinfo.bc_ver_str),
8268                  "%d.%d.%d",
8269                  ((sc->devinfo.bc_ver >> 24) & 0xff),
8270                  ((sc->devinfo.bc_ver >> 16) & 0xff),
8271                  ((sc->devinfo.bc_ver >> 8) & 0xff));
8272         PMD_DRV_LOG(INFO, "Bootcode version: %s", sc->devinfo.bc_ver_str);
8273
8274         /* get the bootcode shmem address */
8275         sc->devinfo.mf_cfg_base = bnx2x_get_shmem_mf_cfg_base(sc);
8276
8277         /* clean indirect addresses as they're not used */
8278         pci_write_long(sc, PCICFG_GRC_ADDRESS, 0);
8279         if (IS_PF(sc)) {
8280                 REG_WR(sc, PXP2_REG_PGL_ADDR_88_F0, 0);
8281                 REG_WR(sc, PXP2_REG_PGL_ADDR_8C_F0, 0);
8282                 REG_WR(sc, PXP2_REG_PGL_ADDR_90_F0, 0);
8283                 REG_WR(sc, PXP2_REG_PGL_ADDR_94_F0, 0);
8284                 if (CHIP_IS_E1x(sc)) {
8285                         REG_WR(sc, PXP2_REG_PGL_ADDR_88_F1, 0);
8286                         REG_WR(sc, PXP2_REG_PGL_ADDR_8C_F1, 0);
8287                         REG_WR(sc, PXP2_REG_PGL_ADDR_90_F1, 0);
8288                         REG_WR(sc, PXP2_REG_PGL_ADDR_94_F1, 0);
8289                 }
8290         }
8291
8292         /* get the nvram size */
8293         val = REG_RD(sc, MCP_REG_MCPR_NVM_CFG4);
8294         sc->devinfo.flash_size =
8295             (NVRAM_1MB_SIZE << (val & MCPR_NVM_CFG4_FLASH_SIZE));
8296
8297         bnx2x_set_power_state(sc, PCI_PM_D0);
8298         /* get various configuration parameters from shmem */
8299         bnx2x_get_shmem_info(sc);
8300
8301         /* initialize IGU parameters */
8302         if (CHIP_IS_E1x(sc)) {
8303                 sc->devinfo.int_block = INT_BLOCK_HC;
8304                 sc->igu_dsb_id = DEF_SB_IGU_ID;
8305                 sc->igu_base_sb = 0;
8306         } else {
8307                 sc->devinfo.int_block = INT_BLOCK_IGU;
8308
8309 /* do not allow device reset during IGU info preocessing */
8310                 bnx2x_acquire_hw_lock(sc, HW_LOCK_RESOURCE_RESET);
8311
8312                 val = REG_RD(sc, IGU_REG_BLOCK_CONFIGURATION);
8313
8314                 if (val & IGU_BLOCK_CONFIGURATION_REG_BACKWARD_COMP_EN) {
8315                         int tout = 5000;
8316
8317                         val &= ~(IGU_BLOCK_CONFIGURATION_REG_BACKWARD_COMP_EN);
8318                         REG_WR(sc, IGU_REG_BLOCK_CONFIGURATION, val);
8319                         REG_WR(sc, IGU_REG_RESET_MEMORIES, 0x7f);
8320
8321                         while (tout && REG_RD(sc, IGU_REG_RESET_MEMORIES)) {
8322                                 tout--;
8323                                 DELAY(1000);
8324                         }
8325
8326                         if (REG_RD(sc, IGU_REG_RESET_MEMORIES)) {
8327                                 PMD_DRV_LOG(NOTICE,
8328                                             "FORCING IGU Normal Mode failed!!!");
8329                                 bnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_RESET);
8330                                 return -1;
8331                         }
8332                 }
8333
8334                 if (val & IGU_BLOCK_CONFIGURATION_REG_BACKWARD_COMP_EN) {
8335                         PMD_DRV_LOG(DEBUG, "IGU Backward Compatible Mode");
8336                         sc->devinfo.int_block |= INT_BLOCK_MODE_BW_COMP;
8337                 } else {
8338                         PMD_DRV_LOG(DEBUG, "IGU Normal Mode");
8339                 }
8340
8341                 rc = bnx2x_get_igu_cam_info(sc);
8342
8343                 bnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_RESET);
8344
8345                 if (rc) {
8346                         return rc;
8347                 }
8348         }
8349
8350         /*
8351          * Get base FW non-default (fast path) status block ID. This value is
8352          * used to initialize the fw_sb_id saved on the fp/queue structure to
8353          * determine the id used by the FW.
8354          */
8355         if (CHIP_IS_E1x(sc)) {
8356                 sc->base_fw_ndsb =
8357                     ((SC_PORT(sc) * FP_SB_MAX_E1x) + SC_L_ID(sc));
8358         } else {
8359 /*
8360  * 57712+ - We currently use one FW SB per IGU SB (Rx and Tx of
8361  * the same queue are indicated on the same IGU SB). So we prefer
8362  * FW and IGU SBs to be the same value.
8363  */
8364                 sc->base_fw_ndsb = sc->igu_base_sb;
8365         }
8366
8367         elink_phy_probe(&sc->link_params);
8368
8369         return 0;
8370 }
8371
8372 static void
8373 bnx2x_link_settings_supported(struct bnx2x_softc *sc, uint32_t switch_cfg)
8374 {
8375         uint32_t cfg_size = 0;
8376         uint32_t idx;
8377         uint8_t port = SC_PORT(sc);
8378
8379         /* aggregation of supported attributes of all external phys */
8380         sc->port.supported[0] = 0;
8381         sc->port.supported[1] = 0;
8382
8383         switch (sc->link_params.num_phys) {
8384         case 1:
8385                 sc->port.supported[0] =
8386                     sc->link_params.phy[ELINK_INT_PHY].supported;
8387                 cfg_size = 1;
8388                 break;
8389         case 2:
8390                 sc->port.supported[0] =
8391                     sc->link_params.phy[ELINK_EXT_PHY1].supported;
8392                 cfg_size = 1;
8393                 break;
8394         case 3:
8395                 if (sc->link_params.multi_phy_config &
8396                     PORT_HW_CFG_PHY_SWAPPED_ENABLED) {
8397                         sc->port.supported[1] =
8398                             sc->link_params.phy[ELINK_EXT_PHY1].supported;
8399                         sc->port.supported[0] =
8400                             sc->link_params.phy[ELINK_EXT_PHY2].supported;
8401                 } else {
8402                         sc->port.supported[0] =
8403                             sc->link_params.phy[ELINK_EXT_PHY1].supported;
8404                         sc->port.supported[1] =
8405                             sc->link_params.phy[ELINK_EXT_PHY2].supported;
8406                 }
8407                 cfg_size = 2;
8408                 break;
8409         }
8410
8411         if (!(sc->port.supported[0] || sc->port.supported[1])) {
8412                 PMD_DRV_LOG(ERR,
8413                             "Invalid phy config in NVRAM (PHY1=0x%08x PHY2=0x%08x)",
8414                             SHMEM_RD(sc,
8415                                      dev_info.port_hw_config
8416                                      [port].external_phy_config),
8417                             SHMEM_RD(sc,
8418                                      dev_info.port_hw_config
8419                                      [port].external_phy_config2));
8420                 return;
8421         }
8422
8423         if (CHIP_IS_E3(sc))
8424                 sc->port.phy_addr = REG_RD(sc, MISC_REG_WC0_CTRL_PHY_ADDR);
8425         else {
8426                 switch (switch_cfg) {
8427                 case ELINK_SWITCH_CFG_1G:
8428                         sc->port.phy_addr =
8429                             REG_RD(sc,
8430                                    NIG_REG_SERDES0_CTRL_PHY_ADDR + port * 0x10);
8431                         break;
8432                 case ELINK_SWITCH_CFG_10G:
8433                         sc->port.phy_addr =
8434                             REG_RD(sc,
8435                                    NIG_REG_XGXS0_CTRL_PHY_ADDR + port * 0x18);
8436                         break;
8437                 default:
8438                         PMD_DRV_LOG(ERR,
8439                                     "Invalid switch config in"
8440                                     "link_config=0x%08x",
8441                                     sc->port.link_config[0]);
8442                         return;
8443                 }
8444         }
8445
8446         PMD_DRV_LOG(INFO, "PHY addr 0x%08x", sc->port.phy_addr);
8447
8448         /* mask what we support according to speed_cap_mask per configuration */
8449         for (idx = 0; idx < cfg_size; idx++) {
8450                 if (!(sc->link_params.speed_cap_mask[idx] &
8451                       PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_HALF)) {
8452                         sc->port.supported[idx] &=
8453                             ~ELINK_SUPPORTED_10baseT_Half;
8454                 }
8455
8456                 if (!(sc->link_params.speed_cap_mask[idx] &
8457                       PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL)) {
8458                         sc->port.supported[idx] &=
8459                             ~ELINK_SUPPORTED_10baseT_Full;
8460                 }
8461
8462                 if (!(sc->link_params.speed_cap_mask[idx] &
8463                       PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_HALF)) {
8464                         sc->port.supported[idx] &=
8465                             ~ELINK_SUPPORTED_100baseT_Half;
8466                 }
8467
8468                 if (!(sc->link_params.speed_cap_mask[idx] &
8469                       PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_FULL)) {
8470                         sc->port.supported[idx] &=
8471                             ~ELINK_SUPPORTED_100baseT_Full;
8472                 }
8473
8474                 if (!(sc->link_params.speed_cap_mask[idx] &
8475                       PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)) {
8476                         sc->port.supported[idx] &=
8477                             ~ELINK_SUPPORTED_1000baseT_Full;
8478                 }
8479
8480                 if (!(sc->link_params.speed_cap_mask[idx] &
8481                       PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G)) {
8482                         sc->port.supported[idx] &=
8483                             ~ELINK_SUPPORTED_2500baseX_Full;
8484                 }
8485
8486                 if (!(sc->link_params.speed_cap_mask[idx] &
8487                       PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)) {
8488                         sc->port.supported[idx] &=
8489                             ~ELINK_SUPPORTED_10000baseT_Full;
8490                 }
8491
8492                 if (!(sc->link_params.speed_cap_mask[idx] &
8493                       PORT_HW_CFG_SPEED_CAPABILITY_D0_20G)) {
8494                         sc->port.supported[idx] &=
8495                             ~ELINK_SUPPORTED_20000baseKR2_Full;
8496                 }
8497         }
8498
8499         PMD_DRV_LOG(INFO, "PHY supported 0=0x%08x 1=0x%08x",
8500                     sc->port.supported[0], sc->port.supported[1]);
8501 }
8502
8503 static void bnx2x_link_settings_requested(struct bnx2x_softc *sc)
8504 {
8505         uint32_t link_config;
8506         uint32_t idx;
8507         uint32_t cfg_size = 0;
8508
8509         sc->port.advertising[0] = 0;
8510         sc->port.advertising[1] = 0;
8511
8512         switch (sc->link_params.num_phys) {
8513         case 1:
8514         case 2:
8515                 cfg_size = 1;
8516                 break;
8517         case 3:
8518                 cfg_size = 2;
8519                 break;
8520         }
8521
8522         for (idx = 0; idx < cfg_size; idx++) {
8523                 sc->link_params.req_duplex[idx] = DUPLEX_FULL;
8524                 link_config = sc->port.link_config[idx];
8525
8526                 switch (link_config & PORT_FEATURE_LINK_SPEED_MASK) {
8527                 case PORT_FEATURE_LINK_SPEED_AUTO:
8528                         if (sc->port.supported[idx] & ELINK_SUPPORTED_Autoneg) {
8529                                 sc->link_params.req_line_speed[idx] =
8530                                     ELINK_SPEED_AUTO_NEG;
8531                                 sc->port.advertising[idx] |=
8532                                     sc->port.supported[idx];
8533                                 if (sc->link_params.phy[ELINK_EXT_PHY1].type ==
8534                                     PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X84833)
8535                                         sc->port.advertising[idx] |=
8536                                             (ELINK_SUPPORTED_100baseT_Half |
8537                                              ELINK_SUPPORTED_100baseT_Full);
8538                         } else {
8539                                 /* force 10G, no AN */
8540                                 sc->link_params.req_line_speed[idx] =
8541                                     ELINK_SPEED_10000;
8542                                 sc->port.advertising[idx] |=
8543                                     (ADVERTISED_10000baseT_Full |
8544                                      ADVERTISED_FIBRE);
8545                                 continue;
8546                         }
8547                         break;
8548
8549                 case PORT_FEATURE_LINK_SPEED_10M_FULL:
8550                         if (sc->
8551                             port.supported[idx] & ELINK_SUPPORTED_10baseT_Full)
8552                         {
8553                                 sc->link_params.req_line_speed[idx] =
8554                                     ELINK_SPEED_10;
8555                                 sc->port.advertising[idx] |=
8556                                     (ADVERTISED_10baseT_Full | ADVERTISED_TP);
8557                         } else {
8558                                 PMD_DRV_LOG(ERR,
8559                                             "Invalid NVRAM config link_config=0x%08x "
8560                                             "speed_cap_mask=0x%08x",
8561                                             link_config,
8562                                             sc->
8563                                             link_params.speed_cap_mask[idx]);
8564                                 return;
8565                         }
8566                         break;
8567
8568                 case PORT_FEATURE_LINK_SPEED_10M_HALF:
8569                         if (sc->
8570                             port.supported[idx] & ELINK_SUPPORTED_10baseT_Half)
8571                         {
8572                                 sc->link_params.req_line_speed[idx] =
8573                                     ELINK_SPEED_10;
8574                                 sc->link_params.req_duplex[idx] = DUPLEX_HALF;
8575                                 sc->port.advertising[idx] |=
8576                                     (ADVERTISED_10baseT_Half | ADVERTISED_TP);
8577                         } else {
8578                                 PMD_DRV_LOG(ERR,
8579                                             "Invalid NVRAM config link_config=0x%08x "
8580                                             "speed_cap_mask=0x%08x",
8581                                             link_config,
8582                                             sc->
8583                                             link_params.speed_cap_mask[idx]);
8584                                 return;
8585                         }
8586                         break;
8587
8588                 case PORT_FEATURE_LINK_SPEED_100M_FULL:
8589                         if (sc->
8590                             port.supported[idx] & ELINK_SUPPORTED_100baseT_Full)
8591                         {
8592                                 sc->link_params.req_line_speed[idx] =
8593                                     ELINK_SPEED_100;
8594                                 sc->port.advertising[idx] |=
8595                                     (ADVERTISED_100baseT_Full | ADVERTISED_TP);
8596                         } else {
8597                                 PMD_DRV_LOG(ERR,
8598                                             "Invalid NVRAM config link_config=0x%08x "
8599                                             "speed_cap_mask=0x%08x",
8600                                             link_config,
8601                                             sc->
8602                                             link_params.speed_cap_mask[idx]);
8603                                 return;
8604                         }
8605                         break;
8606
8607                 case PORT_FEATURE_LINK_SPEED_100M_HALF:
8608                         if (sc->
8609                             port.supported[idx] & ELINK_SUPPORTED_100baseT_Half)
8610                         {
8611                                 sc->link_params.req_line_speed[idx] =
8612                                     ELINK_SPEED_100;
8613                                 sc->link_params.req_duplex[idx] = DUPLEX_HALF;
8614                                 sc->port.advertising[idx] |=
8615                                     (ADVERTISED_100baseT_Half | ADVERTISED_TP);
8616                         } else {
8617                                 PMD_DRV_LOG(ERR,
8618                                             "Invalid NVRAM config link_config=0x%08x "
8619                                             "speed_cap_mask=0x%08x",
8620                                             link_config,
8621                                             sc->
8622                                             link_params.speed_cap_mask[idx]);
8623                                 return;
8624                         }
8625                         break;
8626
8627                 case PORT_FEATURE_LINK_SPEED_1G:
8628                         if (sc->port.supported[idx] &
8629                             ELINK_SUPPORTED_1000baseT_Full) {
8630                                 sc->link_params.req_line_speed[idx] =
8631                                     ELINK_SPEED_1000;
8632                                 sc->port.advertising[idx] |=
8633                                     (ADVERTISED_1000baseT_Full | ADVERTISED_TP);
8634                         } else {
8635                                 PMD_DRV_LOG(ERR,
8636                                             "Invalid NVRAM config link_config=0x%08x "
8637                                             "speed_cap_mask=0x%08x",
8638                                             link_config,
8639                                             sc->
8640                                             link_params.speed_cap_mask[idx]);
8641                                 return;
8642                         }
8643                         break;
8644
8645                 case PORT_FEATURE_LINK_SPEED_2_5G:
8646                         if (sc->port.supported[idx] &
8647                             ELINK_SUPPORTED_2500baseX_Full) {
8648                                 sc->link_params.req_line_speed[idx] =
8649                                     ELINK_SPEED_2500;
8650                                 sc->port.advertising[idx] |=
8651                                     (ADVERTISED_2500baseX_Full | ADVERTISED_TP);
8652                         } else {
8653                                 PMD_DRV_LOG(ERR,
8654                                             "Invalid NVRAM config link_config=0x%08x "
8655                                             "speed_cap_mask=0x%08x",
8656                                             link_config,
8657                                             sc->
8658                                             link_params.speed_cap_mask[idx]);
8659                                 return;
8660                         }
8661                         break;
8662
8663                 case PORT_FEATURE_LINK_SPEED_10G_CX4:
8664                         if (sc->port.supported[idx] &
8665                             ELINK_SUPPORTED_10000baseT_Full) {
8666                                 sc->link_params.req_line_speed[idx] =
8667                                     ELINK_SPEED_10000;
8668                                 sc->port.advertising[idx] |=
8669                                     (ADVERTISED_10000baseT_Full |
8670                                      ADVERTISED_FIBRE);
8671                         } else {
8672                                 PMD_DRV_LOG(ERR,
8673                                             "Invalid NVRAM config link_config=0x%08x "
8674                                             "speed_cap_mask=0x%08x",
8675                                             link_config,
8676                                             sc->
8677                                             link_params.speed_cap_mask[idx]);
8678                                 return;
8679                         }
8680                         break;
8681
8682                 case PORT_FEATURE_LINK_SPEED_20G:
8683                         sc->link_params.req_line_speed[idx] = ELINK_SPEED_20000;
8684                         break;
8685
8686                 default:
8687                         PMD_DRV_LOG(ERR,
8688                                     "Invalid NVRAM config link_config=0x%08x "
8689                                     "speed_cap_mask=0x%08x", link_config,
8690                                     sc->link_params.speed_cap_mask[idx]);
8691                         sc->link_params.req_line_speed[idx] =
8692                             ELINK_SPEED_AUTO_NEG;
8693                         sc->port.advertising[idx] = sc->port.supported[idx];
8694                         break;
8695                 }
8696
8697                 sc->link_params.req_flow_ctrl[idx] =
8698                     (link_config & PORT_FEATURE_FLOW_CONTROL_MASK);
8699
8700                 if (sc->link_params.req_flow_ctrl[idx] == ELINK_FLOW_CTRL_AUTO) {
8701                         if (!
8702                             (sc->
8703                              port.supported[idx] & ELINK_SUPPORTED_Autoneg)) {
8704                                 sc->link_params.req_flow_ctrl[idx] =
8705                                     ELINK_FLOW_CTRL_NONE;
8706                         } else {
8707                                 bnx2x_set_requested_fc(sc);
8708                         }
8709                 }
8710         }
8711 }
8712
8713 static void bnx2x_get_phy_info(struct bnx2x_softc *sc)
8714 {
8715         uint8_t port = SC_PORT(sc);
8716         uint32_t eee_mode;
8717
8718         PMD_INIT_FUNC_TRACE();
8719
8720         /* shmem data already read in bnx2x_get_shmem_info() */
8721
8722         bnx2x_link_settings_supported(sc, sc->link_params.switch_cfg);
8723         bnx2x_link_settings_requested(sc);
8724
8725         /* configure link feature according to nvram value */
8726         eee_mode =
8727             (((SHMEM_RD(sc, dev_info.port_feature_config[port].eee_power_mode))
8728               & PORT_FEAT_CFG_EEE_POWER_MODE_MASK) >>
8729              PORT_FEAT_CFG_EEE_POWER_MODE_SHIFT);
8730         if (eee_mode != PORT_FEAT_CFG_EEE_POWER_MODE_DISABLED) {
8731                 sc->link_params.eee_mode = (ELINK_EEE_MODE_ADV_LPI |
8732                                             ELINK_EEE_MODE_ENABLE_LPI |
8733                                             ELINK_EEE_MODE_OUTPUT_TIME);
8734         } else {
8735                 sc->link_params.eee_mode = 0;
8736         }
8737
8738         /* get the media type */
8739         bnx2x_media_detect(sc);
8740 }
8741
8742 static void bnx2x_set_modes_bitmap(struct bnx2x_softc *sc)
8743 {
8744         uint32_t flags = MODE_ASIC | MODE_PORT2;
8745
8746         if (CHIP_IS_E2(sc)) {
8747                 flags |= MODE_E2;
8748         } else if (CHIP_IS_E3(sc)) {
8749                 flags |= MODE_E3;
8750                 if (CHIP_REV(sc) == CHIP_REV_Ax) {
8751                         flags |= MODE_E3_A0;
8752                 } else {        /*if (CHIP_REV(sc) == CHIP_REV_Bx) */
8753
8754                         flags |= MODE_E3_B0 | MODE_COS3;
8755                 }
8756         }
8757
8758         if (IS_MF(sc)) {
8759                 flags |= MODE_MF;
8760                 switch (sc->devinfo.mf_info.mf_mode) {
8761                 case MULTI_FUNCTION_SD:
8762                         flags |= MODE_MF_SD;
8763                         break;
8764                 case MULTI_FUNCTION_SI:
8765                         flags |= MODE_MF_SI;
8766                         break;
8767                 case MULTI_FUNCTION_AFEX:
8768                         flags |= MODE_MF_AFEX;
8769                         break;
8770                 }
8771         } else {
8772                 flags |= MODE_SF;
8773         }
8774
8775 #if defined(__LITTLE_ENDIAN)
8776         flags |= MODE_LITTLE_ENDIAN;
8777 #else /* __BIG_ENDIAN */
8778         flags |= MODE_BIG_ENDIAN;
8779 #endif
8780
8781         INIT_MODE_FLAGS(sc) = flags;
8782 }
8783
8784 int bnx2x_alloc_hsi_mem(struct bnx2x_softc *sc)
8785 {
8786         struct bnx2x_fastpath *fp;
8787         char buf[32];
8788         uint32_t i;
8789
8790         if (IS_PF(sc)) {
8791 /************************/
8792 /* DEFAULT STATUS BLOCK */
8793 /************************/
8794
8795                 if (bnx2x_dma_alloc(sc, sizeof(struct host_sp_status_block),
8796                                   &sc->def_sb_dma, "def_sb",
8797                                   RTE_CACHE_LINE_SIZE) != 0) {
8798                         return -1;
8799                 }
8800
8801                 sc->def_sb =
8802                     (struct host_sp_status_block *)sc->def_sb_dma.vaddr;
8803 /***************/
8804 /* EVENT QUEUE */
8805 /***************/
8806
8807                 if (bnx2x_dma_alloc(sc, BNX2X_PAGE_SIZE,
8808                                   &sc->eq_dma, "ev_queue",
8809                                   RTE_CACHE_LINE_SIZE) != 0) {
8810                         sc->def_sb = NULL;
8811                         return -1;
8812                 }
8813
8814                 sc->eq = (union event_ring_elem *)sc->eq_dma.vaddr;
8815
8816 /*************/
8817 /* SLOW PATH */
8818 /*************/
8819
8820                 if (bnx2x_dma_alloc(sc, sizeof(struct bnx2x_slowpath),
8821                                   &sc->sp_dma, "sp",
8822                                   RTE_CACHE_LINE_SIZE) != 0) {
8823                         sc->eq = NULL;
8824                         sc->def_sb = NULL;
8825                         return -1;
8826                 }
8827
8828                 sc->sp = (struct bnx2x_slowpath *)sc->sp_dma.vaddr;
8829
8830 /*******************/
8831 /* SLOW PATH QUEUE */
8832 /*******************/
8833
8834                 if (bnx2x_dma_alloc(sc, BNX2X_PAGE_SIZE,
8835                                   &sc->spq_dma, "sp_queue",
8836                                   RTE_CACHE_LINE_SIZE) != 0) {
8837                         sc->sp = NULL;
8838                         sc->eq = NULL;
8839                         sc->def_sb = NULL;
8840                         return -1;
8841                 }
8842
8843                 sc->spq = (struct eth_spe *)sc->spq_dma.vaddr;
8844
8845 /***************************/
8846 /* FW DECOMPRESSION BUFFER */
8847 /***************************/
8848
8849                 if (bnx2x_dma_alloc(sc, FW_BUF_SIZE, &sc->gz_buf_dma,
8850                                   "fw_buf", RTE_CACHE_LINE_SIZE) != 0) {
8851                         sc->spq = NULL;
8852                         sc->sp = NULL;
8853                         sc->eq = NULL;
8854                         sc->def_sb = NULL;
8855                         return -1;
8856                 }
8857
8858                 sc->gz_buf = (void *)sc->gz_buf_dma.vaddr;
8859         }
8860
8861         /*************/
8862         /* FASTPATHS */
8863         /*************/
8864
8865         /* allocate DMA memory for each fastpath structure */
8866         for (i = 0; i < sc->num_queues; i++) {
8867                 fp = &sc->fp[i];
8868                 fp->sc = sc;
8869                 fp->index = i;
8870
8871 /*******************/
8872 /* FP STATUS BLOCK */
8873 /*******************/
8874
8875                 snprintf(buf, sizeof(buf), "fp_%d_sb", i);
8876                 if (bnx2x_dma_alloc(sc, sizeof(union bnx2x_host_hc_status_block),
8877                                   &fp->sb_dma, buf, RTE_CACHE_LINE_SIZE) != 0) {
8878                         PMD_DRV_LOG(NOTICE, "Failed to alloc %s", buf);
8879                         return -1;
8880                 } else {
8881                         if (CHIP_IS_E2E3(sc)) {
8882                                 fp->status_block.e2_sb =
8883                                     (struct host_hc_status_block_e2 *)
8884                                     fp->sb_dma.vaddr;
8885                         } else {
8886                                 fp->status_block.e1x_sb =
8887                                     (struct host_hc_status_block_e1x *)
8888                                     fp->sb_dma.vaddr;
8889                         }
8890                 }
8891         }
8892
8893         return 0;
8894 }
8895
8896 void bnx2x_free_hsi_mem(struct bnx2x_softc *sc)
8897 {
8898         struct bnx2x_fastpath *fp;
8899         int i;
8900
8901         for (i = 0; i < sc->num_queues; i++) {
8902                 fp = &sc->fp[i];
8903
8904 /*******************/
8905 /* FP STATUS BLOCK */
8906 /*******************/
8907
8908                 memset(&fp->status_block, 0, sizeof(fp->status_block));
8909         }
8910
8911         /***************************/
8912         /* FW DECOMPRESSION BUFFER */
8913         /***************************/
8914
8915         sc->gz_buf = NULL;
8916
8917         /*******************/
8918         /* SLOW PATH QUEUE */
8919         /*******************/
8920
8921         sc->spq = NULL;
8922
8923         /*************/
8924         /* SLOW PATH */
8925         /*************/
8926
8927         sc->sp = NULL;
8928
8929         /***************/
8930         /* EVENT QUEUE */
8931         /***************/
8932
8933         sc->eq = NULL;
8934
8935         /************************/
8936         /* DEFAULT STATUS BLOCK */
8937         /************************/
8938
8939         sc->def_sb = NULL;
8940
8941 }
8942
8943 /*
8944 * Previous driver DMAE transaction may have occurred when pre-boot stage
8945 * ended and boot began. This would invalidate the addresses of the
8946 * transaction, resulting in was-error bit set in the PCI causing all
8947 * hw-to-host PCIe transactions to timeout. If this happened we want to clear
8948 * the interrupt which detected this from the pglueb and the was-done bit
8949 */
8950 static void bnx2x_prev_interrupted_dmae(struct bnx2x_softc *sc)
8951 {
8952         uint32_t val;
8953
8954         if (!CHIP_IS_E1x(sc)) {
8955                 val = REG_RD(sc, PGLUE_B_REG_PGLUE_B_INT_STS);
8956                 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_WAS_ERROR_ATTN) {
8957                         REG_WR(sc, PGLUE_B_REG_WAS_ERROR_PF_7_0_CLR,
8958                                1 << SC_FUNC(sc));
8959                 }
8960         }
8961 }
8962
8963 static int bnx2x_prev_mcp_done(struct bnx2x_softc *sc)
8964 {
8965         uint32_t rc = bnx2x_fw_command(sc, DRV_MSG_CODE_UNLOAD_DONE,
8966                                      DRV_MSG_CODE_UNLOAD_SKIP_LINK_RESET);
8967         if (!rc) {
8968                 PMD_DRV_LOG(NOTICE, "MCP response failure, aborting");
8969                 return -1;
8970         }
8971
8972         return 0;
8973 }
8974
8975 static struct bnx2x_prev_list_node *bnx2x_prev_path_get_entry(struct bnx2x_softc *sc)
8976 {
8977         struct bnx2x_prev_list_node *tmp;
8978
8979         LIST_FOREACH(tmp, &bnx2x_prev_list, node) {
8980                 if ((sc->pcie_bus == tmp->bus) &&
8981                     (sc->pcie_device == tmp->slot) &&
8982                     (SC_PATH(sc) == tmp->path)) {
8983                         return tmp;
8984                 }
8985         }
8986
8987         return NULL;
8988 }
8989
8990 static uint8_t bnx2x_prev_is_path_marked(struct bnx2x_softc *sc)
8991 {
8992         struct bnx2x_prev_list_node *tmp;
8993         int rc = FALSE;
8994
8995         rte_spinlock_lock(&bnx2x_prev_mtx);
8996
8997         tmp = bnx2x_prev_path_get_entry(sc);
8998         if (tmp) {
8999                 if (tmp->aer) {
9000                         PMD_DRV_LOG(DEBUG,
9001                                     "Path %d/%d/%d was marked by AER",
9002                                     sc->pcie_bus, sc->pcie_device, SC_PATH(sc));
9003                 } else {
9004                         rc = TRUE;
9005                         PMD_DRV_LOG(DEBUG,
9006                                     "Path %d/%d/%d was already cleaned from previous drivers",
9007                                     sc->pcie_bus, sc->pcie_device, SC_PATH(sc));
9008                 }
9009         }
9010
9011         rte_spinlock_unlock(&bnx2x_prev_mtx);
9012
9013         return rc;
9014 }
9015
9016 static int bnx2x_prev_mark_path(struct bnx2x_softc *sc, uint8_t after_undi)
9017 {
9018         struct bnx2x_prev_list_node *tmp;
9019
9020         rte_spinlock_lock(&bnx2x_prev_mtx);
9021
9022         /* Check whether the entry for this path already exists */
9023         tmp = bnx2x_prev_path_get_entry(sc);
9024         if (tmp) {
9025                 if (!tmp->aer) {
9026                         PMD_DRV_LOG(DEBUG,
9027                                     "Re-marking AER in path %d/%d/%d",
9028                                     sc->pcie_bus, sc->pcie_device, SC_PATH(sc));
9029                 } else {
9030                         PMD_DRV_LOG(DEBUG,
9031                                     "Removing AER indication from path %d/%d/%d",
9032                                     sc->pcie_bus, sc->pcie_device, SC_PATH(sc));
9033                         tmp->aer = 0;
9034                 }
9035
9036                 rte_spinlock_unlock(&bnx2x_prev_mtx);
9037                 return 0;
9038         }
9039
9040         rte_spinlock_unlock(&bnx2x_prev_mtx);
9041
9042         /* Create an entry for this path and add it */
9043         tmp = rte_malloc("", sizeof(struct bnx2x_prev_list_node),
9044                          RTE_CACHE_LINE_SIZE);
9045         if (!tmp) {
9046                 PMD_DRV_LOG(NOTICE, "Failed to allocate 'bnx2x_prev_list_node'");
9047                 return -1;
9048         }
9049
9050         tmp->bus = sc->pcie_bus;
9051         tmp->slot = sc->pcie_device;
9052         tmp->path = SC_PATH(sc);
9053         tmp->aer = 0;
9054         tmp->undi = after_undi ? (1 << SC_PORT(sc)) : 0;
9055
9056         rte_spinlock_lock(&bnx2x_prev_mtx);
9057
9058         LIST_INSERT_HEAD(&bnx2x_prev_list, tmp, node);
9059
9060         rte_spinlock_unlock(&bnx2x_prev_mtx);
9061
9062         return 0;
9063 }
9064
9065 static int bnx2x_do_flr(struct bnx2x_softc *sc)
9066 {
9067         int i;
9068
9069         /* only E2 and onwards support FLR */
9070         if (CHIP_IS_E1x(sc)) {
9071                 PMD_DRV_LOG(WARNING, "FLR not supported in E1H");
9072                 return -1;
9073         }
9074
9075         /* only bootcode REQ_BC_VER_4_INITIATE_FLR and onwards support flr */
9076         if (sc->devinfo.bc_ver < REQ_BC_VER_4_INITIATE_FLR) {
9077                 PMD_DRV_LOG(WARNING,
9078                             "FLR not supported by BC_VER: 0x%08x",
9079                             sc->devinfo.bc_ver);
9080                 return -1;
9081         }
9082
9083         /* Wait for Transaction Pending bit clean */
9084         for (i = 0; i < 4; i++) {
9085                 if (i) {
9086                         DELAY(((1 << (i - 1)) * 100) * 1000);
9087                 }
9088
9089                 if (!bnx2x_is_pcie_pending(sc)) {
9090                         goto clear;
9091                 }
9092         }
9093
9094         PMD_DRV_LOG(NOTICE, "PCIE transaction is not cleared, "
9095                     "proceeding with reset anyway");
9096
9097 clear:
9098         bnx2x_fw_command(sc, DRV_MSG_CODE_INITIATE_FLR, 0);
9099
9100         return 0;
9101 }
9102
9103 struct bnx2x_mac_vals {
9104         uint32_t xmac_addr;
9105         uint32_t xmac_val;
9106         uint32_t emac_addr;
9107         uint32_t emac_val;
9108         uint32_t umac_addr;
9109         uint32_t umac_val;
9110         uint32_t bmac_addr;
9111         uint32_t bmac_val[2];
9112 };
9113
9114 static void
9115 bnx2x_prev_unload_close_mac(struct bnx2x_softc *sc, struct bnx2x_mac_vals *vals)
9116 {
9117         uint32_t val, base_addr, offset, mask, reset_reg;
9118         uint8_t mac_stopped = FALSE;
9119         uint8_t port = SC_PORT(sc);
9120         uint32_t wb_data[2];
9121
9122         /* reset addresses as they also mark which values were changed */
9123         vals->bmac_addr = 0;
9124         vals->umac_addr = 0;
9125         vals->xmac_addr = 0;
9126         vals->emac_addr = 0;
9127
9128         reset_reg = REG_RD(sc, MISC_REG_RESET_REG_2);
9129
9130         if (!CHIP_IS_E3(sc)) {
9131                 val = REG_RD(sc, NIG_REG_BMAC0_REGS_OUT_EN + port * 4);
9132                 mask = MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port;
9133                 if ((mask & reset_reg) && val) {
9134                         base_addr = SC_PORT(sc) ? NIG_REG_INGRESS_BMAC1_MEM
9135                             : NIG_REG_INGRESS_BMAC0_MEM;
9136                         offset = CHIP_IS_E2(sc) ? BIGMAC2_REGISTER_BMAC_CONTROL
9137                             : BIGMAC_REGISTER_BMAC_CONTROL;
9138
9139                         /*
9140                          * use rd/wr since we cannot use dmae. This is safe
9141                          * since MCP won't access the bus due to the request
9142                          * to unload, and no function on the path can be
9143                          * loaded at this time.
9144                          */
9145                         wb_data[0] = REG_RD(sc, base_addr + offset);
9146                         wb_data[1] = REG_RD(sc, base_addr + offset + 0x4);
9147                         vals->bmac_addr = base_addr + offset;
9148                         vals->bmac_val[0] = wb_data[0];
9149                         vals->bmac_val[1] = wb_data[1];
9150                         wb_data[0] &= ~ELINK_BMAC_CONTROL_RX_ENABLE;
9151                         REG_WR(sc, vals->bmac_addr, wb_data[0]);
9152                         REG_WR(sc, vals->bmac_addr + 0x4, wb_data[1]);
9153                 }
9154
9155                 vals->emac_addr = NIG_REG_NIG_EMAC0_EN + SC_PORT(sc) * 4;
9156                 vals->emac_val = REG_RD(sc, vals->emac_addr);
9157                 REG_WR(sc, vals->emac_addr, 0);
9158                 mac_stopped = TRUE;
9159         } else {
9160                 if (reset_reg & MISC_REGISTERS_RESET_REG_2_XMAC) {
9161                         base_addr = SC_PORT(sc) ? GRCBASE_XMAC1 : GRCBASE_XMAC0;
9162                         val = REG_RD(sc, base_addr + XMAC_REG_PFC_CTRL_HI);
9163                         REG_WR(sc, base_addr + XMAC_REG_PFC_CTRL_HI,
9164                                val & ~(1 << 1));
9165                         REG_WR(sc, base_addr + XMAC_REG_PFC_CTRL_HI,
9166                                val | (1 << 1));
9167                         vals->xmac_addr = base_addr + XMAC_REG_CTRL;
9168                         vals->xmac_val = REG_RD(sc, vals->xmac_addr);
9169                         REG_WR(sc, vals->xmac_addr, 0);
9170                         mac_stopped = TRUE;
9171                 }
9172
9173                 mask = MISC_REGISTERS_RESET_REG_2_UMAC0 << port;
9174                 if (mask & reset_reg) {
9175                         base_addr = SC_PORT(sc) ? GRCBASE_UMAC1 : GRCBASE_UMAC0;
9176                         vals->umac_addr = base_addr + UMAC_REG_COMMAND_CONFIG;
9177                         vals->umac_val = REG_RD(sc, vals->umac_addr);
9178                         REG_WR(sc, vals->umac_addr, 0);
9179                         mac_stopped = TRUE;
9180                 }
9181         }
9182
9183         if (mac_stopped) {
9184                 DELAY(20000);
9185         }
9186 }
9187
9188 #define BNX2X_PREV_UNDI_PROD_ADDR(p)  (BAR_TSTRORM_INTMEM + 0x1508 + ((p) << 4))
9189 #define BNX2X_PREV_UNDI_RCQ(val)      ((val) & 0xffff)
9190 #define BNX2X_PREV_UNDI_BD(val)       ((val) >> 16 & 0xffff)
9191 #define BNX2X_PREV_UNDI_PROD(rcq, bd) ((bd) << 16 | (rcq))
9192
9193 static void
9194 bnx2x_prev_unload_undi_inc(struct bnx2x_softc *sc, uint8_t port, uint8_t inc)
9195 {
9196         uint16_t rcq, bd;
9197         uint32_t tmp_reg = REG_RD(sc, BNX2X_PREV_UNDI_PROD_ADDR(port));
9198
9199         rcq = BNX2X_PREV_UNDI_RCQ(tmp_reg) + inc;
9200         bd = BNX2X_PREV_UNDI_BD(tmp_reg) + inc;
9201
9202         tmp_reg = BNX2X_PREV_UNDI_PROD(rcq, bd);
9203         REG_WR(sc, BNX2X_PREV_UNDI_PROD_ADDR(port), tmp_reg);
9204 }
9205
9206 static int bnx2x_prev_unload_common(struct bnx2x_softc *sc)
9207 {
9208         uint32_t reset_reg, tmp_reg = 0, rc;
9209         uint8_t prev_undi = FALSE;
9210         struct bnx2x_mac_vals mac_vals;
9211         uint32_t timer_count = 1000;
9212         uint32_t prev_brb;
9213
9214         /*
9215          * It is possible a previous function received 'common' answer,
9216          * but hasn't loaded yet, therefore creating a scenario of
9217          * multiple functions receiving 'common' on the same path.
9218          */
9219         memset(&mac_vals, 0, sizeof(mac_vals));
9220
9221         if (bnx2x_prev_is_path_marked(sc)) {
9222                 return bnx2x_prev_mcp_done(sc);
9223         }
9224
9225         reset_reg = REG_RD(sc, MISC_REG_RESET_REG_1);
9226
9227         /* Reset should be performed after BRB is emptied */
9228         if (reset_reg & MISC_REGISTERS_RESET_REG_1_RST_BRB1) {
9229                 /* Close the MAC Rx to prevent BRB from filling up */
9230                 bnx2x_prev_unload_close_mac(sc, &mac_vals);
9231
9232                 /* close LLH filters towards the BRB */
9233                 elink_set_rx_filter(&sc->link_params, 0);
9234
9235                 /*
9236                  * Check if the UNDI driver was previously loaded.
9237                  * UNDI driver initializes CID offset for normal bell to 0x7
9238                  */
9239                 if (reset_reg & MISC_REGISTERS_RESET_REG_1_RST_DORQ) {
9240                         tmp_reg = REG_RD(sc, DORQ_REG_NORM_CID_OFST);
9241                         if (tmp_reg == 0x7) {
9242                                 PMD_DRV_LOG(DEBUG, "UNDI previously loaded");
9243                                 prev_undi = TRUE;
9244                                 /* clear the UNDI indication */
9245                                 REG_WR(sc, DORQ_REG_NORM_CID_OFST, 0);
9246                                 /* clear possible idle check errors */
9247                                 REG_RD(sc, NIG_REG_NIG_INT_STS_CLR_0);
9248                         }
9249                 }
9250
9251                 /* wait until BRB is empty */
9252                 tmp_reg = REG_RD(sc, BRB1_REG_NUM_OF_FULL_BLOCKS);
9253                 while (timer_count) {
9254                         prev_brb = tmp_reg;
9255
9256                         tmp_reg = REG_RD(sc, BRB1_REG_NUM_OF_FULL_BLOCKS);
9257                         if (!tmp_reg) {
9258                                 break;
9259                         }
9260
9261                         PMD_DRV_LOG(DEBUG, "BRB still has 0x%08x", tmp_reg);
9262
9263                         /* reset timer as long as BRB actually gets emptied */
9264                         if (prev_brb > tmp_reg) {
9265                                 timer_count = 1000;
9266                         } else {
9267                                 timer_count--;
9268                         }
9269
9270                         /* If UNDI resides in memory, manually increment it */
9271                         if (prev_undi) {
9272                                 bnx2x_prev_unload_undi_inc(sc, SC_PORT(sc), 1);
9273                         }
9274
9275                         DELAY(10);
9276                 }
9277
9278                 if (!timer_count) {
9279                         PMD_DRV_LOG(NOTICE, "Failed to empty BRB");
9280                 }
9281         }
9282
9283         /* No packets are in the pipeline, path is ready for reset */
9284         bnx2x_reset_common(sc);
9285
9286         if (mac_vals.xmac_addr) {
9287                 REG_WR(sc, mac_vals.xmac_addr, mac_vals.xmac_val);
9288         }
9289         if (mac_vals.umac_addr) {
9290                 REG_WR(sc, mac_vals.umac_addr, mac_vals.umac_val);
9291         }
9292         if (mac_vals.emac_addr) {
9293                 REG_WR(sc, mac_vals.emac_addr, mac_vals.emac_val);
9294         }
9295         if (mac_vals.bmac_addr) {
9296                 REG_WR(sc, mac_vals.bmac_addr, mac_vals.bmac_val[0]);
9297                 REG_WR(sc, mac_vals.bmac_addr + 4, mac_vals.bmac_val[1]);
9298         }
9299
9300         rc = bnx2x_prev_mark_path(sc, prev_undi);
9301         if (rc) {
9302                 bnx2x_prev_mcp_done(sc);
9303                 return rc;
9304         }
9305
9306         return bnx2x_prev_mcp_done(sc);
9307 }
9308
9309 static int bnx2x_prev_unload_uncommon(struct bnx2x_softc *sc)
9310 {
9311         int rc;
9312
9313         /* Test if previous unload process was already finished for this path */
9314         if (bnx2x_prev_is_path_marked(sc)) {
9315                 return bnx2x_prev_mcp_done(sc);
9316         }
9317
9318         /*
9319          * If function has FLR capabilities, and existing FW version matches
9320          * the one required, then FLR will be sufficient to clean any residue
9321          * left by previous driver
9322          */
9323         rc = bnx2x_nic_load_analyze_req(sc, FW_MSG_CODE_DRV_LOAD_FUNCTION);
9324         if (!rc) {
9325                 /* fw version is good */
9326                 rc = bnx2x_do_flr(sc);
9327         }
9328
9329         if (!rc) {
9330                 /* FLR was performed */
9331                 return 0;
9332         }
9333
9334         PMD_DRV_LOG(INFO, "Could not FLR");
9335
9336         /* Close the MCP request, return failure */
9337         rc = bnx2x_prev_mcp_done(sc);
9338         if (!rc) {
9339                 rc = BNX2X_PREV_WAIT_NEEDED;
9340         }
9341
9342         return rc;
9343 }
9344
9345 static int bnx2x_prev_unload(struct bnx2x_softc *sc)
9346 {
9347         int time_counter = 10;
9348         uint32_t fw, hw_lock_reg, hw_lock_val;
9349         uint32_t rc = 0;
9350
9351         /*
9352          * Clear HW from errors which may have resulted from an interrupted
9353          * DMAE transaction.
9354          */
9355         bnx2x_prev_interrupted_dmae(sc);
9356
9357         /* Release previously held locks */
9358         if (SC_FUNC(sc) <= 5)
9359                 hw_lock_reg = (MISC_REG_DRIVER_CONTROL_1 + SC_FUNC(sc) * 8);
9360         else
9361                 hw_lock_reg =
9362                     (MISC_REG_DRIVER_CONTROL_7 + (SC_FUNC(sc) - 6) * 8);
9363
9364         hw_lock_val = (REG_RD(sc, hw_lock_reg));
9365         if (hw_lock_val) {
9366                 if (hw_lock_val & HW_LOCK_RESOURCE_NVRAM) {
9367                         REG_WR(sc, MCP_REG_MCPR_NVM_SW_ARB,
9368                                (MCPR_NVM_SW_ARB_ARB_REQ_CLR1 << SC_PORT(sc)));
9369                 }
9370                 REG_WR(sc, hw_lock_reg, 0xffffffff);
9371         }
9372
9373         if (MCPR_ACCESS_LOCK_LOCK & REG_RD(sc, MCP_REG_MCPR_ACCESS_LOCK)) {
9374                 REG_WR(sc, MCP_REG_MCPR_ACCESS_LOCK, 0);
9375         }
9376
9377         do {
9378                 /* Lock MCP using an unload request */
9379                 fw = bnx2x_fw_command(sc, DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS, 0);
9380                 if (!fw) {
9381                         PMD_DRV_LOG(NOTICE, "MCP response failure, aborting");
9382                         rc = -1;
9383                         break;
9384                 }
9385
9386                 if (fw == FW_MSG_CODE_DRV_UNLOAD_COMMON) {
9387                         rc = bnx2x_prev_unload_common(sc);
9388                         break;
9389                 }
9390
9391                 /* non-common reply from MCP might require looping */
9392                 rc = bnx2x_prev_unload_uncommon(sc);
9393                 if (rc != BNX2X_PREV_WAIT_NEEDED) {
9394                         break;
9395                 }
9396
9397                 DELAY(20000);
9398         } while (--time_counter);
9399
9400         if (!time_counter || rc) {
9401                 PMD_DRV_LOG(NOTICE, "Failed to unload previous driver!");
9402                 rc = -1;
9403         }
9404
9405         return rc;
9406 }
9407
9408 static void
9409 bnx2x_dcbx_set_state(struct bnx2x_softc *sc, uint8_t dcb_on, uint32_t dcbx_enabled)
9410 {
9411         if (!CHIP_IS_E1x(sc)) {
9412                 sc->dcb_state = dcb_on;
9413                 sc->dcbx_enabled = dcbx_enabled;
9414         } else {
9415                 sc->dcb_state = FALSE;
9416                 sc->dcbx_enabled = BNX2X_DCBX_ENABLED_INVALID;
9417         }
9418         PMD_DRV_LOG(DEBUG,
9419                     "DCB state [%s:%s]",
9420                     dcb_on ? "ON" : "OFF",
9421                     (dcbx_enabled == BNX2X_DCBX_ENABLED_OFF) ? "user-mode" :
9422                     (dcbx_enabled ==
9423                      BNX2X_DCBX_ENABLED_ON_NEG_OFF) ? "on-chip static"
9424                     : (dcbx_enabled ==
9425                        BNX2X_DCBX_ENABLED_ON_NEG_ON) ?
9426                     "on-chip with negotiation" : "invalid");
9427 }
9428
9429 static int bnx2x_set_qm_cid_count(struct bnx2x_softc *sc)
9430 {
9431         int cid_count = BNX2X_L2_MAX_CID(sc);
9432
9433         if (CNIC_SUPPORT(sc)) {
9434                 cid_count += CNIC_CID_MAX;
9435         }
9436
9437         return roundup(cid_count, QM_CID_ROUND);
9438 }
9439
9440 static void bnx2x_init_multi_cos(struct bnx2x_softc *sc)
9441 {
9442         int pri, cos;
9443
9444         uint32_t pri_map = 0;
9445
9446         for (pri = 0; pri < BNX2X_MAX_PRIORITY; pri++) {
9447                 cos = ((pri_map & (0xf << (pri * 4))) >> (pri * 4));
9448                 if (cos < sc->max_cos) {
9449                         sc->prio_to_cos[pri] = cos;
9450                 } else {
9451                         PMD_DRV_LOG(WARNING,
9452                                     "Invalid COS %d for priority %d "
9453                                     "(max COS is %d), setting to 0", cos, pri,
9454                                     (sc->max_cos - 1));
9455                         sc->prio_to_cos[pri] = 0;
9456                 }
9457         }
9458 }
9459
9460 static int bnx2x_pci_get_caps(struct bnx2x_softc *sc)
9461 {
9462         struct {
9463                 uint8_t id;
9464                 uint8_t next;
9465         } pci_cap;
9466         uint16_t status;
9467         struct bnx2x_pci_cap *cap;
9468
9469         cap = sc->pci_caps = rte_zmalloc("caps", sizeof(struct bnx2x_pci_cap),
9470                                          RTE_CACHE_LINE_SIZE);
9471         if (!cap) {
9472                 PMD_DRV_LOG(NOTICE, "Failed to allocate memory");
9473                 return -ENOMEM;
9474         }
9475
9476 #ifndef __FreeBSD__
9477         pci_read(sc, PCI_STATUS, &status, 2);
9478         if (!(status & PCI_STATUS_CAP_LIST)) {
9479 #else
9480         pci_read(sc, PCIR_STATUS, &status, 2);
9481         if (!(status & PCIM_STATUS_CAPPRESENT)) {
9482 #endif
9483                 PMD_DRV_LOG(NOTICE, "PCIe capability reading failed");
9484                 return -1;
9485         }
9486
9487 #ifndef __FreeBSD__
9488         pci_read(sc, PCI_CAPABILITY_LIST, &pci_cap.next, 1);
9489 #else
9490         pci_read(sc, PCIR_CAP_PTR, &pci_cap.next, 1);
9491 #endif
9492         while (pci_cap.next) {
9493                 cap->addr = pci_cap.next & ~3;
9494                 pci_read(sc, pci_cap.next & ~3, &pci_cap, 2);
9495                 if (pci_cap.id == 0xff)
9496                         break;
9497                 cap->id = pci_cap.id;
9498                 cap->type = BNX2X_PCI_CAP;
9499                 cap->next = rte_zmalloc("pci_cap",
9500                                         sizeof(struct bnx2x_pci_cap),
9501                                         RTE_CACHE_LINE_SIZE);
9502                 if (!cap->next) {
9503                         PMD_DRV_LOG(NOTICE, "Failed to allocate memory");
9504                         return -ENOMEM;
9505                 }
9506                 cap = cap->next;
9507         }
9508
9509         return 0;
9510 }
9511
9512 static void bnx2x_init_rte(struct bnx2x_softc *sc)
9513 {
9514         if (IS_VF(sc)) {
9515                 sc->max_tx_queues = min(BNX2X_VF_MAX_QUEUES_PER_VF,
9516                                         sc->igu_sb_cnt);
9517                 sc->max_rx_queues = min(BNX2X_VF_MAX_QUEUES_PER_VF,
9518                                         sc->igu_sb_cnt);
9519         } else {
9520                 sc->max_rx_queues = BNX2X_MAX_RSS_COUNT(sc);
9521                 sc->max_tx_queues = sc->max_rx_queues;
9522         }
9523 }
9524
9525 #define FW_HEADER_LEN 104
9526 #define FW_NAME_57711 "/lib/firmware/bnx2x/bnx2x-e1h-7.2.51.0.fw"
9527 #define FW_NAME_57810 "/lib/firmware/bnx2x/bnx2x-e2-7.2.51.0.fw"
9528
9529 void bnx2x_load_firmware(struct bnx2x_softc *sc)
9530 {
9531         const char *fwname;
9532         int f;
9533         struct stat st;
9534
9535         fwname = sc->devinfo.device_id == CHIP_NUM_57711
9536                 ? FW_NAME_57711 : FW_NAME_57810;
9537         f = open(fwname, O_RDONLY);
9538         if (f < 0) {
9539                 PMD_DRV_LOG(NOTICE, "Can't open firmware file");
9540                 return;
9541         }
9542
9543         if (fstat(f, &st) < 0) {
9544                 PMD_DRV_LOG(NOTICE, "Can't stat firmware file");
9545                 close(f);
9546                 return;
9547         }
9548
9549         sc->firmware = rte_zmalloc("bnx2x_fw", st.st_size, RTE_CACHE_LINE_SIZE);
9550         if (!sc->firmware) {
9551                 PMD_DRV_LOG(NOTICE, "Can't allocate memory for firmware");
9552                 close(f);
9553                 return;
9554         }
9555
9556         if (read(f, sc->firmware, st.st_size) != st.st_size) {
9557                 PMD_DRV_LOG(NOTICE, "Can't read firmware data");
9558                 close(f);
9559                 return;
9560         }
9561         close(f);
9562
9563         sc->fw_len = st.st_size;
9564         if (sc->fw_len < FW_HEADER_LEN) {
9565                 PMD_DRV_LOG(NOTICE, "Invalid fw size: %" PRIu64, sc->fw_len);
9566                 return;
9567         }
9568         PMD_DRV_LOG(DEBUG, "fw_len = %" PRIu64, sc->fw_len);
9569 }
9570
9571 static void
9572 bnx2x_data_to_init_ops(uint8_t * data, struct raw_op *dst, uint32_t len)
9573 {
9574         uint32_t *src = (uint32_t *) data;
9575         uint32_t i, j, tmp;
9576
9577         for (i = 0, j = 0; i < len / 8; ++i, j += 2) {
9578                 tmp = rte_be_to_cpu_32(src[j]);
9579                 dst[i].op = (tmp >> 24) & 0xFF;
9580                 dst[i].offset = tmp & 0xFFFFFF;
9581                 dst[i].raw_data = rte_be_to_cpu_32(src[j + 1]);
9582         }
9583 }
9584
9585 static void
9586 bnx2x_data_to_init_offsets(uint8_t * data, uint16_t * dst, uint32_t len)
9587 {
9588         uint16_t *src = (uint16_t *) data;
9589         uint32_t i;
9590
9591         for (i = 0; i < len / 2; ++i)
9592                 dst[i] = rte_be_to_cpu_16(src[i]);
9593 }
9594
9595 static void bnx2x_data_to_init_data(uint8_t * data, uint32_t * dst, uint32_t len)
9596 {
9597         uint32_t *src = (uint32_t *) data;
9598         uint32_t i;
9599
9600         for (i = 0; i < len / 4; ++i)
9601                 dst[i] = rte_be_to_cpu_32(src[i]);
9602 }
9603
9604 static void bnx2x_data_to_iro_array(uint8_t * data, struct iro *dst, uint32_t len)
9605 {
9606         uint32_t *src = (uint32_t *) data;
9607         uint32_t i, j, tmp;
9608
9609         for (i = 0, j = 0; i < len / sizeof(struct iro); ++i, ++j) {
9610                 dst[i].base = rte_be_to_cpu_32(src[j++]);
9611                 tmp = rte_be_to_cpu_32(src[j]);
9612                 dst[i].m1 = (tmp >> 16) & 0xFFFF;
9613                 dst[i].m2 = tmp & 0xFFFF;
9614                 ++j;
9615                 tmp = rte_be_to_cpu_32(src[j]);
9616                 dst[i].m3 = (tmp >> 16) & 0xFFFF;
9617                 dst[i].size = tmp & 0xFFFF;
9618         }
9619 }
9620
9621 /*
9622 * Device attach function.
9623 *
9624 * Allocates device resources, performs secondary chip identification, and
9625 * initializes driver instance variables. This function is called from driver
9626 * load after a successful probe.
9627 *
9628 * Returns:
9629 *   0 = Success, >0 = Failure
9630 */
9631 int bnx2x_attach(struct bnx2x_softc *sc)
9632 {
9633         int rc;
9634
9635         PMD_DRV_LOG(DEBUG, "Starting attach...");
9636
9637         rc = bnx2x_pci_get_caps(sc);
9638         if (rc) {
9639                 PMD_DRV_LOG(NOTICE, "PCIe caps reading was failed");
9640                 return rc;
9641         }
9642
9643         sc->state = BNX2X_STATE_CLOSED;
9644
9645         pci_write_long(sc, PCICFG_GRC_ADDRESS, PCICFG_VENDOR_ID_OFFSET);
9646
9647         sc->igu_base_addr = IS_VF(sc) ? PXP_VF_ADDR_IGU_START : BAR_IGU_INTMEM;
9648
9649         /* get PCI capabilites */
9650         bnx2x_probe_pci_caps(sc);
9651
9652         if (sc->devinfo.pcie_msix_cap_reg != 0) {
9653                 uint32_t val;
9654                 pci_read(sc,
9655                          (sc->devinfo.pcie_msix_cap_reg + PCIR_MSIX_CTRL), &val,
9656                          2);
9657                 sc->igu_sb_cnt = (val & PCIM_MSIXCTRL_TABLE_SIZE) + 1;
9658         } else {
9659                 sc->igu_sb_cnt = 1;
9660         }
9661
9662         /* Init RTE stuff */
9663         bnx2x_init_rte(sc);
9664
9665         if (IS_PF(sc)) {
9666                 /* Enable internal target-read (in case we are probed after PF
9667                  * FLR). Must be done prior to any BAR read access. Only for
9668                  * 57712 and up
9669                  */
9670                 if (!CHIP_IS_E1x(sc)) {
9671                         REG_WR(sc, PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_READ,
9672                                1);
9673                         DELAY(200000);
9674                 }
9675
9676                 /* get device info and set params */
9677                 if (bnx2x_get_device_info(sc) != 0) {
9678                         PMD_DRV_LOG(NOTICE, "getting device info");
9679                         return -ENXIO;
9680                 }
9681
9682 /* get phy settings from shmem and 'and' against admin settings */
9683                 bnx2x_get_phy_info(sc);
9684         } else {
9685                 /* Left mac of VF unfilled, PF should set it for VF */
9686                 memset(sc->link_params.mac_addr, 0, ETHER_ADDR_LEN);
9687         }
9688
9689         sc->wol = 0;
9690
9691         /* set the default MTU (changed via ifconfig) */
9692         sc->mtu = ETHER_MTU;
9693
9694         bnx2x_set_modes_bitmap(sc);
9695
9696         /* need to reset chip if UNDI was active */
9697         if (IS_PF(sc) && !BNX2X_NOMCP(sc)) {
9698 /* init fw_seq */
9699                 sc->fw_seq =
9700                     (SHMEM_RD(sc, func_mb[SC_FW_MB_IDX(sc)].drv_mb_header) &
9701                      DRV_MSG_SEQ_NUMBER_MASK);
9702                 bnx2x_prev_unload(sc);
9703         }
9704
9705         bnx2x_dcbx_set_state(sc, FALSE, BNX2X_DCBX_ENABLED_OFF);
9706
9707         /* calculate qm_cid_count */
9708         sc->qm_cid_count = bnx2x_set_qm_cid_count(sc);
9709
9710         sc->max_cos = 1;
9711         bnx2x_init_multi_cos(sc);
9712
9713         return 0;
9714 }
9715
9716 static void
9717 bnx2x_igu_ack_sb(struct bnx2x_softc *sc, uint8_t igu_sb_id, uint8_t segment,
9718                uint16_t index, uint8_t op, uint8_t update)
9719 {
9720         uint32_t igu_addr = sc->igu_base_addr;
9721         igu_addr += (IGU_CMD_INT_ACK_BASE + igu_sb_id) * 8;
9722         bnx2x_igu_ack_sb_gen(sc, segment, index, op, update, igu_addr);
9723 }
9724
9725 static void
9726 bnx2x_ack_sb(struct bnx2x_softc *sc, uint8_t igu_sb_id, uint8_t storm,
9727            uint16_t index, uint8_t op, uint8_t update)
9728 {
9729         if (unlikely(sc->devinfo.int_block == INT_BLOCK_HC))
9730                 bnx2x_hc_ack_sb(sc, igu_sb_id, storm, index, op, update);
9731         else {
9732                 uint8_t segment;
9733                 if (CHIP_INT_MODE_IS_BC(sc)) {
9734                         segment = storm;
9735                 } else if (igu_sb_id != sc->igu_dsb_id) {
9736                         segment = IGU_SEG_ACCESS_DEF;
9737                 } else if (storm == ATTENTION_ID) {
9738                         segment = IGU_SEG_ACCESS_ATTN;
9739                 } else {
9740                         segment = IGU_SEG_ACCESS_DEF;
9741                 }
9742                 bnx2x_igu_ack_sb(sc, igu_sb_id, segment, index, op, update);
9743         }
9744 }
9745
9746 static void
9747 bnx2x_igu_clear_sb_gen(struct bnx2x_softc *sc, uint8_t func, uint8_t idu_sb_id,
9748                      uint8_t is_pf)
9749 {
9750         uint32_t data, ctl, cnt = 100;
9751         uint32_t igu_addr_data = IGU_REG_COMMAND_REG_32LSB_DATA;
9752         uint32_t igu_addr_ctl = IGU_REG_COMMAND_REG_CTRL;
9753         uint32_t igu_addr_ack = IGU_REG_CSTORM_TYPE_0_SB_CLEANUP +
9754             (idu_sb_id / 32) * 4;
9755         uint32_t sb_bit = 1 << (idu_sb_id % 32);
9756         uint32_t func_encode = func |
9757             (is_pf ? 1 : 0) << IGU_FID_ENCODE_IS_PF_SHIFT;
9758         uint32_t addr_encode = IGU_CMD_E2_PROD_UPD_BASE + idu_sb_id;
9759
9760         /* Not supported in BC mode */
9761         if (CHIP_INT_MODE_IS_BC(sc)) {
9762                 return;
9763         }
9764
9765         data = ((IGU_USE_REGISTER_cstorm_type_0_sb_cleanup <<
9766                  IGU_REGULAR_CLEANUP_TYPE_SHIFT) |
9767                 IGU_REGULAR_CLEANUP_SET | IGU_REGULAR_BCLEANUP);
9768
9769         ctl = ((addr_encode << IGU_CTRL_REG_ADDRESS_SHIFT) |
9770                (func_encode << IGU_CTRL_REG_FID_SHIFT) |
9771                (IGU_CTRL_CMD_TYPE_WR << IGU_CTRL_REG_TYPE_SHIFT));
9772
9773         REG_WR(sc, igu_addr_data, data);
9774
9775         mb();
9776
9777         PMD_DRV_LOG(DEBUG, "write 0x%08x to IGU(via GRC) addr 0x%x",
9778                     ctl, igu_addr_ctl);
9779         REG_WR(sc, igu_addr_ctl, ctl);
9780
9781         mb();
9782
9783         /* wait for clean up to finish */
9784         while (!(REG_RD(sc, igu_addr_ack) & sb_bit) && --cnt) {
9785                 DELAY(20000);
9786         }
9787
9788         if (!(REG_RD(sc, igu_addr_ack) & sb_bit)) {
9789                 PMD_DRV_LOG(DEBUG,
9790                             "Unable to finish IGU cleanup: "
9791                             "idu_sb_id %d offset %d bit %d (cnt %d)",
9792                             idu_sb_id, idu_sb_id / 32, idu_sb_id % 32, cnt);
9793         }
9794 }
9795
9796 static void bnx2x_igu_clear_sb(struct bnx2x_softc *sc, uint8_t idu_sb_id)
9797 {
9798         bnx2x_igu_clear_sb_gen(sc, SC_FUNC(sc), idu_sb_id, TRUE /*PF*/);
9799 }
9800
9801 /*******************/
9802 /* ECORE CALLBACKS */
9803 /*******************/
9804
9805 static void bnx2x_reset_common(struct bnx2x_softc *sc)
9806 {
9807         uint32_t val = 0x1400;
9808
9809         PMD_INIT_FUNC_TRACE();
9810
9811         /* reset_common */
9812         REG_WR(sc, (GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR),
9813                0xd3ffff7f);
9814
9815         if (CHIP_IS_E3(sc)) {
9816                 val |= MISC_REGISTERS_RESET_REG_2_MSTAT0;
9817                 val |= MISC_REGISTERS_RESET_REG_2_MSTAT1;
9818         }
9819
9820         REG_WR(sc, (GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR), val);
9821 }
9822
9823 static void bnx2x_common_init_phy(struct bnx2x_softc *sc)
9824 {
9825         uint32_t shmem_base[2];
9826         uint32_t shmem2_base[2];
9827
9828         /* Avoid common init in case MFW supports LFA */
9829         if (SHMEM2_RD(sc, size) >
9830             (uint32_t) offsetof(struct shmem2_region,
9831                                 lfa_host_addr[SC_PORT(sc)])) {
9832                 return;
9833         }
9834
9835         shmem_base[0] = sc->devinfo.shmem_base;
9836         shmem2_base[0] = sc->devinfo.shmem2_base;
9837
9838         if (!CHIP_IS_E1x(sc)) {
9839                 shmem_base[1] = SHMEM2_RD(sc, other_shmem_base_addr);
9840                 shmem2_base[1] = SHMEM2_RD(sc, other_shmem2_base_addr);
9841         }
9842
9843         elink_common_init_phy(sc, shmem_base, shmem2_base,
9844                               sc->devinfo.chip_id, 0);
9845 }
9846
9847 static void bnx2x_pf_disable(struct bnx2x_softc *sc)
9848 {
9849         uint32_t val = REG_RD(sc, IGU_REG_PF_CONFIGURATION);
9850
9851         val &= ~IGU_PF_CONF_FUNC_EN;
9852
9853         REG_WR(sc, IGU_REG_PF_CONFIGURATION, val);
9854         REG_WR(sc, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 0);
9855         REG_WR(sc, CFC_REG_WEAK_ENABLE_PF, 0);
9856 }
9857
9858 static void bnx2x_init_pxp(struct bnx2x_softc *sc)
9859 {
9860         uint16_t devctl;
9861         int r_order, w_order;
9862
9863         devctl = bnx2x_pcie_capability_read(sc, PCIR_EXPRESS_DEVICE_CTL);
9864
9865         w_order = ((devctl & PCIM_EXP_CTL_MAX_PAYLOAD) >> 5);
9866         r_order = ((devctl & PCIM_EXP_CTL_MAX_READ_REQUEST) >> 12);
9867
9868         ecore_init_pxp_arb(sc, r_order, w_order);
9869 }
9870
9871 static uint32_t bnx2x_get_pretend_reg(struct bnx2x_softc *sc)
9872 {
9873         uint32_t base = PXP2_REG_PGL_PRETEND_FUNC_F0;
9874         uint32_t stride = (PXP2_REG_PGL_PRETEND_FUNC_F1 - base);
9875         return base + (SC_ABS_FUNC(sc)) * stride;
9876 }
9877
9878 /*
9879  * Called only on E1H or E2.
9880  * When pretending to be PF, the pretend value is the function number 0..7.
9881  * When pretending to be VF, the pretend val is the PF-num:VF-valid:ABS-VFID
9882  * combination.
9883  */
9884 static int bnx2x_pretend_func(struct bnx2x_softc *sc, uint16_t pretend_func_val)
9885 {
9886         uint32_t pretend_reg;
9887
9888         if (CHIP_IS_E1H(sc) && (pretend_func_val > E1H_FUNC_MAX))
9889                 return -1;
9890
9891         /* get my own pretend register */
9892         pretend_reg = bnx2x_get_pretend_reg(sc);
9893         REG_WR(sc, pretend_reg, pretend_func_val);
9894         REG_RD(sc, pretend_reg);
9895         return 0;
9896 }
9897
9898 static void bnx2x_setup_fan_failure_detection(struct bnx2x_softc *sc)
9899 {
9900         int is_required;
9901         uint32_t val;
9902         int port;
9903
9904         is_required = 0;
9905         val = (SHMEM_RD(sc, dev_info.shared_hw_config.config2) &
9906                SHARED_HW_CFG_FAN_FAILURE_MASK);
9907
9908         if (val == SHARED_HW_CFG_FAN_FAILURE_ENABLED) {
9909                 is_required = 1;
9910         }
9911         /*
9912          * The fan failure mechanism is usually related to the PHY type since
9913          * the power consumption of the board is affected by the PHY. Currently,
9914          * fan is required for most designs with SFX7101, BNX2X8727 and BNX2X8481.
9915          */
9916         else if (val == SHARED_HW_CFG_FAN_FAILURE_PHY_TYPE) {
9917                 for (port = PORT_0; port < PORT_MAX; port++) {
9918                         is_required |= elink_fan_failure_det_req(sc,
9919                                                                  sc->
9920                                                                  devinfo.shmem_base,
9921                                                                  sc->
9922                                                                  devinfo.shmem2_base,
9923                                                                  port);
9924                 }
9925         }
9926
9927         if (is_required == 0) {
9928                 return;
9929         }
9930
9931         /* Fan failure is indicated by SPIO 5 */
9932         bnx2x_set_spio(sc, MISC_SPIO_SPIO5, MISC_SPIO_INPUT_HI_Z);
9933
9934         /* set to active low mode */
9935         val = REG_RD(sc, MISC_REG_SPIO_INT);
9936         val |= (MISC_SPIO_SPIO5 << MISC_SPIO_INT_OLD_SET_POS);
9937         REG_WR(sc, MISC_REG_SPIO_INT, val);
9938
9939         /* enable interrupt to signal the IGU */
9940         val = REG_RD(sc, MISC_REG_SPIO_EVENT_EN);
9941         val |= MISC_SPIO_SPIO5;
9942         REG_WR(sc, MISC_REG_SPIO_EVENT_EN, val);
9943 }
9944
9945 static void bnx2x_enable_blocks_attention(struct bnx2x_softc *sc)
9946 {
9947         uint32_t val;
9948
9949         REG_WR(sc, PXP_REG_PXP_INT_MASK_0, 0);
9950         if (!CHIP_IS_E1x(sc)) {
9951                 REG_WR(sc, PXP_REG_PXP_INT_MASK_1, 0x40);
9952         } else {
9953                 REG_WR(sc, PXP_REG_PXP_INT_MASK_1, 0);
9954         }
9955         REG_WR(sc, DORQ_REG_DORQ_INT_MASK, 0);
9956         REG_WR(sc, CFC_REG_CFC_INT_MASK, 0);
9957         /*
9958          * mask read length error interrupts in brb for parser
9959          * (parsing unit and 'checksum and crc' unit)
9960          * these errors are legal (PU reads fixed length and CAC can cause
9961          * read length error on truncated packets)
9962          */
9963         REG_WR(sc, BRB1_REG_BRB1_INT_MASK, 0xFC00);
9964         REG_WR(sc, QM_REG_QM_INT_MASK, 0);
9965         REG_WR(sc, TM_REG_TM_INT_MASK, 0);
9966         REG_WR(sc, XSDM_REG_XSDM_INT_MASK_0, 0);
9967         REG_WR(sc, XSDM_REG_XSDM_INT_MASK_1, 0);
9968         REG_WR(sc, XCM_REG_XCM_INT_MASK, 0);
9969         /*      REG_WR(sc, XSEM_REG_XSEM_INT_MASK_0, 0); */
9970         /*      REG_WR(sc, XSEM_REG_XSEM_INT_MASK_1, 0); */
9971         REG_WR(sc, USDM_REG_USDM_INT_MASK_0, 0);
9972         REG_WR(sc, USDM_REG_USDM_INT_MASK_1, 0);
9973         REG_WR(sc, UCM_REG_UCM_INT_MASK, 0);
9974         /*      REG_WR(sc, USEM_REG_USEM_INT_MASK_0, 0); */
9975         /*      REG_WR(sc, USEM_REG_USEM_INT_MASK_1, 0); */
9976         REG_WR(sc, GRCBASE_UPB + PB_REG_PB_INT_MASK, 0);
9977         REG_WR(sc, CSDM_REG_CSDM_INT_MASK_0, 0);
9978         REG_WR(sc, CSDM_REG_CSDM_INT_MASK_1, 0);
9979         REG_WR(sc, CCM_REG_CCM_INT_MASK, 0);
9980         /*      REG_WR(sc, CSEM_REG_CSEM_INT_MASK_0, 0); */
9981         /*      REG_WR(sc, CSEM_REG_CSEM_INT_MASK_1, 0); */
9982
9983         val = (PXP2_PXP2_INT_MASK_0_REG_PGL_CPL_AFT |
9984                PXP2_PXP2_INT_MASK_0_REG_PGL_CPL_OF |
9985                PXP2_PXP2_INT_MASK_0_REG_PGL_PCIE_ATTN);
9986         if (!CHIP_IS_E1x(sc)) {
9987                 val |= (PXP2_PXP2_INT_MASK_0_REG_PGL_READ_BLOCKED |
9988                         PXP2_PXP2_INT_MASK_0_REG_PGL_WRITE_BLOCKED);
9989         }
9990         REG_WR(sc, PXP2_REG_PXP2_INT_MASK_0, val);
9991
9992         REG_WR(sc, TSDM_REG_TSDM_INT_MASK_0, 0);
9993         REG_WR(sc, TSDM_REG_TSDM_INT_MASK_1, 0);
9994         REG_WR(sc, TCM_REG_TCM_INT_MASK, 0);
9995         /*      REG_WR(sc, TSEM_REG_TSEM_INT_MASK_0, 0); */
9996
9997         if (!CHIP_IS_E1x(sc)) {
9998 /* enable VFC attentions: bits 11 and 12, bits 31:13 reserved */
9999                 REG_WR(sc, TSEM_REG_TSEM_INT_MASK_1, 0x07ff);
10000         }
10001
10002         REG_WR(sc, CDU_REG_CDU_INT_MASK, 0);
10003         REG_WR(sc, DMAE_REG_DMAE_INT_MASK, 0);
10004         /*      REG_WR(sc, MISC_REG_MISC_INT_MASK, 0); */
10005         REG_WR(sc, PBF_REG_PBF_INT_MASK, 0x18); /* bit 3,4 masked */
10006 }
10007
10008 /**
10009  * bnx2x_init_hw_common - initialize the HW at the COMMON phase.
10010  *
10011  * @sc:     driver handle
10012  */
10013 static int bnx2x_init_hw_common(struct bnx2x_softc *sc)
10014 {
10015         uint8_t abs_func_id;
10016         uint32_t val;
10017
10018         PMD_DRV_LOG(DEBUG, "starting common init for func %d", SC_ABS_FUNC(sc));
10019
10020         /*
10021          * take the RESET lock to protect undi_unload flow from accessing
10022          * registers while we are resetting the chip
10023          */
10024         bnx2x_acquire_hw_lock(sc, HW_LOCK_RESOURCE_RESET);
10025
10026         bnx2x_reset_common(sc);
10027
10028         REG_WR(sc, (GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET), 0xffffffff);
10029
10030         val = 0xfffc;
10031         if (CHIP_IS_E3(sc)) {
10032                 val |= MISC_REGISTERS_RESET_REG_2_MSTAT0;
10033                 val |= MISC_REGISTERS_RESET_REG_2_MSTAT1;
10034         }
10035
10036         REG_WR(sc, (GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET), val);
10037
10038         bnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_RESET);
10039
10040         ecore_init_block(sc, BLOCK_MISC, PHASE_COMMON);
10041
10042         if (!CHIP_IS_E1x(sc)) {
10043 /*
10044  * 4-port mode or 2-port mode we need to turn off master-enable for
10045  * everyone. After that we turn it back on for self. So, we disregard
10046  * multi-function, and always disable all functions on the given path,
10047  * this means 0,2,4,6 for path 0 and 1,3,5,7 for path 1
10048  */
10049                 for (abs_func_id = SC_PATH(sc);
10050                      abs_func_id < (E2_FUNC_MAX * 2); abs_func_id += 2) {
10051                         if (abs_func_id == SC_ABS_FUNC(sc)) {
10052                                 REG_WR(sc,
10053                                        PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER,
10054                                        1);
10055                                 continue;
10056                         }
10057
10058                         bnx2x_pretend_func(sc, abs_func_id);
10059
10060                         /* clear pf enable */
10061                         bnx2x_pf_disable(sc);
10062
10063                         bnx2x_pretend_func(sc, SC_ABS_FUNC(sc));
10064                 }
10065         }
10066
10067         ecore_init_block(sc, BLOCK_PXP, PHASE_COMMON);
10068
10069         ecore_init_block(sc, BLOCK_PXP2, PHASE_COMMON);
10070         bnx2x_init_pxp(sc);
10071
10072 #ifdef __BIG_ENDIAN
10073         REG_WR(sc, PXP2_REG_RQ_QM_ENDIAN_M, 1);
10074         REG_WR(sc, PXP2_REG_RQ_TM_ENDIAN_M, 1);
10075         REG_WR(sc, PXP2_REG_RQ_SRC_ENDIAN_M, 1);
10076         REG_WR(sc, PXP2_REG_RQ_CDU_ENDIAN_M, 1);
10077         REG_WR(sc, PXP2_REG_RQ_DBG_ENDIAN_M, 1);
10078         /* make sure this value is 0 */
10079         REG_WR(sc, PXP2_REG_RQ_HC_ENDIAN_M, 0);
10080
10081         //REG_WR(sc, PXP2_REG_RD_PBF_SWAP_MODE, 1);
10082         REG_WR(sc, PXP2_REG_RD_QM_SWAP_MODE, 1);
10083         REG_WR(sc, PXP2_REG_RD_TM_SWAP_MODE, 1);
10084         REG_WR(sc, PXP2_REG_RD_SRC_SWAP_MODE, 1);
10085         REG_WR(sc, PXP2_REG_RD_CDURD_SWAP_MODE, 1);
10086 #endif
10087
10088         ecore_ilt_init_page_size(sc, INITOP_SET);
10089
10090         if (CHIP_REV_IS_FPGA(sc) && CHIP_IS_E1H(sc)) {
10091                 REG_WR(sc, PXP2_REG_PGL_TAGS_LIMIT, 0x1);
10092         }
10093
10094         /* let the HW do it's magic... */
10095         DELAY(100000);
10096
10097         /* finish PXP init */
10098
10099         val = REG_RD(sc, PXP2_REG_RQ_CFG_DONE);
10100         if (val != 1) {
10101                 PMD_DRV_LOG(NOTICE, "PXP2 CFG failed");
10102                 return -1;
10103         }
10104         val = REG_RD(sc, PXP2_REG_RD_INIT_DONE);
10105         if (val != 1) {
10106                 PMD_DRV_LOG(NOTICE, "PXP2 RD_INIT failed");
10107                 return -1;
10108         }
10109
10110         /*
10111          * Timer bug workaround for E2 only. We need to set the entire ILT to have
10112          * entries with value "0" and valid bit on. This needs to be done by the
10113          * first PF that is loaded in a path (i.e. common phase)
10114          */
10115         if (!CHIP_IS_E1x(sc)) {
10116 /*
10117  * In E2 there is a bug in the timers block that can cause function 6 / 7
10118  * (i.e. vnic3) to start even if it is marked as "scan-off".
10119  * This occurs when a different function (func2,3) is being marked
10120  * as "scan-off". Real-life scenario for example: if a driver is being
10121  * load-unloaded while func6,7 are down. This will cause the timer to access
10122  * the ilt, translate to a logical address and send a request to read/write.
10123  * Since the ilt for the function that is down is not valid, this will cause
10124  * a translation error which is unrecoverable.
10125  * The Workaround is intended to make sure that when this happens nothing
10126  * fatal will occur. The workaround:
10127  *  1.  First PF driver which loads on a path will:
10128  *      a.  After taking the chip out of reset, by using pretend,
10129  *          it will write "0" to the following registers of
10130  *          the other vnics.
10131  *          REG_WR(pdev, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 0);
10132  *          REG_WR(pdev, CFC_REG_WEAK_ENABLE_PF,0);
10133  *          REG_WR(pdev, CFC_REG_STRONG_ENABLE_PF,0);
10134  *          And for itself it will write '1' to
10135  *          PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER to enable
10136  *          dmae-operations (writing to pram for example.)
10137  *          note: can be done for only function 6,7 but cleaner this
10138  *            way.
10139  *      b.  Write zero+valid to the entire ILT.
10140  *      c.  Init the first_timers_ilt_entry, last_timers_ilt_entry of
10141  *          VNIC3 (of that port). The range allocated will be the
10142  *          entire ILT. This is needed to prevent  ILT range error.
10143  *  2.  Any PF driver load flow:
10144  *      a.  ILT update with the physical addresses of the allocated
10145  *          logical pages.
10146  *      b.  Wait 20msec. - note that this timeout is needed to make
10147  *          sure there are no requests in one of the PXP internal
10148  *          queues with "old" ILT addresses.
10149  *      c.  PF enable in the PGLC.
10150  *      d.  Clear the was_error of the PF in the PGLC. (could have
10151  *          occurred while driver was down)
10152  *      e.  PF enable in the CFC (WEAK + STRONG)
10153  *      f.  Timers scan enable
10154  *  3.  PF driver unload flow:
10155  *      a.  Clear the Timers scan_en.
10156  *      b.  Polling for scan_on=0 for that PF.
10157  *      c.  Clear the PF enable bit in the PXP.
10158  *      d.  Clear the PF enable in the CFC (WEAK + STRONG)
10159  *      e.  Write zero+valid to all ILT entries (The valid bit must
10160  *          stay set)
10161  *      f.  If this is VNIC 3 of a port then also init
10162  *          first_timers_ilt_entry to zero and last_timers_ilt_entry
10163  *          to the last enrty in the ILT.
10164  *
10165  *      Notes:
10166  *      Currently the PF error in the PGLC is non recoverable.
10167  *      In the future the there will be a recovery routine for this error.
10168  *      Currently attention is masked.
10169  *      Having an MCP lock on the load/unload process does not guarantee that
10170  *      there is no Timer disable during Func6/7 enable. This is because the
10171  *      Timers scan is currently being cleared by the MCP on FLR.
10172  *      Step 2.d can be done only for PF6/7 and the driver can also check if
10173  *      there is error before clearing it. But the flow above is simpler and
10174  *      more general.
10175  *      All ILT entries are written by zero+valid and not just PF6/7
10176  *      ILT entries since in the future the ILT entries allocation for
10177  *      PF-s might be dynamic.
10178  */
10179                 struct ilt_client_info ilt_cli;
10180                 struct ecore_ilt ilt;
10181
10182                 memset(&ilt_cli, 0, sizeof(struct ilt_client_info));
10183                 memset(&ilt, 0, sizeof(struct ecore_ilt));
10184
10185 /* initialize dummy TM client */
10186                 ilt_cli.start = 0;
10187                 ilt_cli.end = ILT_NUM_PAGE_ENTRIES - 1;
10188                 ilt_cli.client_num = ILT_CLIENT_TM;
10189
10190 /*
10191  * Step 1: set zeroes to all ilt page entries with valid bit on
10192  * Step 2: set the timers first/last ilt entry to point
10193  * to the entire range to prevent ILT range error for 3rd/4th
10194  * vnic (this code assumes existence of the vnic)
10195  *
10196  * both steps performed by call to ecore_ilt_client_init_op()
10197  * with dummy TM client
10198  *
10199  * we must use pretend since PXP2_REG_RQ_##blk##_FIRST_ILT
10200  * and his brother are split registers
10201  */
10202
10203                 bnx2x_pretend_func(sc, (SC_PATH(sc) + 6));
10204                 ecore_ilt_client_init_op_ilt(sc, &ilt, &ilt_cli, INITOP_CLEAR);
10205                 bnx2x_pretend_func(sc, SC_ABS_FUNC(sc));
10206
10207                 REG_WR(sc, PXP2_REG_RQ_DRAM_ALIGN, BNX2X_PXP_DRAM_ALIGN);
10208                 REG_WR(sc, PXP2_REG_RQ_DRAM_ALIGN_RD, BNX2X_PXP_DRAM_ALIGN);
10209                 REG_WR(sc, PXP2_REG_RQ_DRAM_ALIGN_SEL, 1);
10210         }
10211
10212         REG_WR(sc, PXP2_REG_RQ_DISABLE_INPUTS, 0);
10213         REG_WR(sc, PXP2_REG_RD_DISABLE_INPUTS, 0);
10214
10215         if (!CHIP_IS_E1x(sc)) {
10216                 int factor = 0;
10217
10218                 ecore_init_block(sc, BLOCK_PGLUE_B, PHASE_COMMON);
10219                 ecore_init_block(sc, BLOCK_ATC, PHASE_COMMON);
10220
10221 /* let the HW do it's magic... */
10222                 do {
10223                         DELAY(200000);
10224                         val = REG_RD(sc, ATC_REG_ATC_INIT_DONE);
10225                 } while (factor-- && (val != 1));
10226
10227                 if (val != 1) {
10228                         PMD_DRV_LOG(NOTICE, "ATC_INIT failed");
10229                         return -1;
10230                 }
10231         }
10232
10233         ecore_init_block(sc, BLOCK_DMAE, PHASE_COMMON);
10234
10235         /* clean the DMAE memory */
10236         sc->dmae_ready = 1;
10237         ecore_init_fill(sc, TSEM_REG_PRAM, 0, 8);
10238
10239         ecore_init_block(sc, BLOCK_TCM, PHASE_COMMON);
10240
10241         ecore_init_block(sc, BLOCK_UCM, PHASE_COMMON);
10242
10243         ecore_init_block(sc, BLOCK_CCM, PHASE_COMMON);
10244
10245         ecore_init_block(sc, BLOCK_XCM, PHASE_COMMON);
10246
10247         bnx2x_read_dmae(sc, XSEM_REG_PASSIVE_BUFFER, 3);
10248         bnx2x_read_dmae(sc, CSEM_REG_PASSIVE_BUFFER, 3);
10249         bnx2x_read_dmae(sc, TSEM_REG_PASSIVE_BUFFER, 3);
10250         bnx2x_read_dmae(sc, USEM_REG_PASSIVE_BUFFER, 3);
10251
10252         ecore_init_block(sc, BLOCK_QM, PHASE_COMMON);
10253
10254         /* QM queues pointers table */
10255         ecore_qm_init_ptr_table(sc, sc->qm_cid_count, INITOP_SET);
10256
10257         /* soft reset pulse */
10258         REG_WR(sc, QM_REG_SOFT_RESET, 1);
10259         REG_WR(sc, QM_REG_SOFT_RESET, 0);
10260
10261         if (CNIC_SUPPORT(sc))
10262                 ecore_init_block(sc, BLOCK_TM, PHASE_COMMON);
10263
10264         ecore_init_block(sc, BLOCK_DORQ, PHASE_COMMON);
10265         REG_WR(sc, DORQ_REG_DPM_CID_OFST, BNX2X_DB_SHIFT);
10266
10267         if (!CHIP_REV_IS_SLOW(sc)) {
10268 /* enable hw interrupt from doorbell Q */
10269                 REG_WR(sc, DORQ_REG_DORQ_INT_MASK, 0);
10270         }
10271
10272         ecore_init_block(sc, BLOCK_BRB1, PHASE_COMMON);
10273
10274         ecore_init_block(sc, BLOCK_PRS, PHASE_COMMON);
10275         REG_WR(sc, PRS_REG_A_PRSU_20, 0xf);
10276         REG_WR(sc, PRS_REG_E1HOV_MODE, sc->devinfo.mf_info.path_has_ovlan);
10277
10278         if (!CHIP_IS_E1x(sc) && !CHIP_IS_E3B0(sc)) {
10279                 if (IS_MF_AFEX(sc)) {
10280                         /*
10281                          * configure that AFEX and VLAN headers must be
10282                          * received in AFEX mode
10283                          */
10284                         REG_WR(sc, PRS_REG_HDRS_AFTER_BASIC, 0xE);
10285                         REG_WR(sc, PRS_REG_MUST_HAVE_HDRS, 0xA);
10286                         REG_WR(sc, PRS_REG_HDRS_AFTER_TAG_0, 0x6);
10287                         REG_WR(sc, PRS_REG_TAG_ETHERTYPE_0, 0x8926);
10288                         REG_WR(sc, PRS_REG_TAG_LEN_0, 0x4);
10289                 } else {
10290                         /*
10291                          * Bit-map indicating which L2 hdrs may appear
10292                          * after the basic Ethernet header
10293                          */
10294                         REG_WR(sc, PRS_REG_HDRS_AFTER_BASIC,
10295                                sc->devinfo.mf_info.path_has_ovlan ? 7 : 6);
10296                 }
10297         }
10298
10299         ecore_init_block(sc, BLOCK_TSDM, PHASE_COMMON);
10300         ecore_init_block(sc, BLOCK_CSDM, PHASE_COMMON);
10301         ecore_init_block(sc, BLOCK_USDM, PHASE_COMMON);
10302         ecore_init_block(sc, BLOCK_XSDM, PHASE_COMMON);
10303
10304         if (!CHIP_IS_E1x(sc)) {
10305 /* reset VFC memories */
10306                 REG_WR(sc, TSEM_REG_FAST_MEMORY + VFC_REG_MEMORIES_RST,
10307                        VFC_MEMORIES_RST_REG_CAM_RST |
10308                        VFC_MEMORIES_RST_REG_RAM_RST);
10309                 REG_WR(sc, XSEM_REG_FAST_MEMORY + VFC_REG_MEMORIES_RST,
10310                        VFC_MEMORIES_RST_REG_CAM_RST |
10311                        VFC_MEMORIES_RST_REG_RAM_RST);
10312
10313                 DELAY(20000);
10314         }
10315
10316         ecore_init_block(sc, BLOCK_TSEM, PHASE_COMMON);
10317         ecore_init_block(sc, BLOCK_USEM, PHASE_COMMON);
10318         ecore_init_block(sc, BLOCK_CSEM, PHASE_COMMON);
10319         ecore_init_block(sc, BLOCK_XSEM, PHASE_COMMON);
10320
10321         /* sync semi rtc */
10322         REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR, 0x80000000);
10323         REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, 0x80000000);
10324
10325         ecore_init_block(sc, BLOCK_UPB, PHASE_COMMON);
10326         ecore_init_block(sc, BLOCK_XPB, PHASE_COMMON);
10327         ecore_init_block(sc, BLOCK_PBF, PHASE_COMMON);
10328
10329         if (!CHIP_IS_E1x(sc)) {
10330                 if (IS_MF_AFEX(sc)) {
10331                         /*
10332                          * configure that AFEX and VLAN headers must be
10333                          * sent in AFEX mode
10334                          */
10335                         REG_WR(sc, PBF_REG_HDRS_AFTER_BASIC, 0xE);
10336                         REG_WR(sc, PBF_REG_MUST_HAVE_HDRS, 0xA);
10337                         REG_WR(sc, PBF_REG_HDRS_AFTER_TAG_0, 0x6);
10338                         REG_WR(sc, PBF_REG_TAG_ETHERTYPE_0, 0x8926);
10339                         REG_WR(sc, PBF_REG_TAG_LEN_0, 0x4);
10340                 } else {
10341                         REG_WR(sc, PBF_REG_HDRS_AFTER_BASIC,
10342                                sc->devinfo.mf_info.path_has_ovlan ? 7 : 6);
10343                 }
10344         }
10345
10346         REG_WR(sc, SRC_REG_SOFT_RST, 1);
10347
10348         ecore_init_block(sc, BLOCK_SRC, PHASE_COMMON);
10349
10350         if (CNIC_SUPPORT(sc)) {
10351                 REG_WR(sc, SRC_REG_KEYSEARCH_0, 0x63285672);
10352                 REG_WR(sc, SRC_REG_KEYSEARCH_1, 0x24b8f2cc);
10353                 REG_WR(sc, SRC_REG_KEYSEARCH_2, 0x223aef9b);
10354                 REG_WR(sc, SRC_REG_KEYSEARCH_3, 0x26001e3a);
10355                 REG_WR(sc, SRC_REG_KEYSEARCH_4, 0x7ae91116);
10356                 REG_WR(sc, SRC_REG_KEYSEARCH_5, 0x5ce5230b);
10357                 REG_WR(sc, SRC_REG_KEYSEARCH_6, 0x298d8adf);
10358                 REG_WR(sc, SRC_REG_KEYSEARCH_7, 0x6eb0ff09);
10359                 REG_WR(sc, SRC_REG_KEYSEARCH_8, 0x1830f82f);
10360                 REG_WR(sc, SRC_REG_KEYSEARCH_9, 0x01e46be7);
10361         }
10362         REG_WR(sc, SRC_REG_SOFT_RST, 0);
10363
10364         if (sizeof(union cdu_context) != 1024) {
10365 /* we currently assume that a context is 1024 bytes */
10366                 PMD_DRV_LOG(NOTICE,
10367                             "please adjust the size of cdu_context(%ld)",
10368                             (long)sizeof(union cdu_context));
10369         }
10370
10371         ecore_init_block(sc, BLOCK_CDU, PHASE_COMMON);
10372         val = (4 << 24) + (0 << 12) + 1024;
10373         REG_WR(sc, CDU_REG_CDU_GLOBAL_PARAMS, val);
10374
10375         ecore_init_block(sc, BLOCK_CFC, PHASE_COMMON);
10376
10377         REG_WR(sc, CFC_REG_INIT_REG, 0x7FF);
10378         /* enable context validation interrupt from CFC */
10379         REG_WR(sc, CFC_REG_CFC_INT_MASK, 0);
10380
10381         /* set the thresholds to prevent CFC/CDU race */
10382         REG_WR(sc, CFC_REG_DEBUG0, 0x20020000);
10383         ecore_init_block(sc, BLOCK_HC, PHASE_COMMON);
10384
10385         if (!CHIP_IS_E1x(sc) && BNX2X_NOMCP(sc)) {
10386                 REG_WR(sc, IGU_REG_RESET_MEMORIES, 0x36);
10387         }
10388
10389         ecore_init_block(sc, BLOCK_IGU, PHASE_COMMON);
10390         ecore_init_block(sc, BLOCK_MISC_AEU, PHASE_COMMON);
10391
10392         /* Reset PCIE errors for debug */
10393         REG_WR(sc, 0x2814, 0xffffffff);
10394         REG_WR(sc, 0x3820, 0xffffffff);
10395
10396         if (!CHIP_IS_E1x(sc)) {
10397                 REG_WR(sc, PCICFG_OFFSET + PXPCS_TL_CONTROL_5,
10398                        (PXPCS_TL_CONTROL_5_ERR_UNSPPORT1 |
10399                         PXPCS_TL_CONTROL_5_ERR_UNSPPORT));
10400                 REG_WR(sc, PCICFG_OFFSET + PXPCS_TL_FUNC345_STAT,
10401                        (PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT4 |
10402                         PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT3 |
10403                         PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT2));
10404                 REG_WR(sc, PCICFG_OFFSET + PXPCS_TL_FUNC678_STAT,
10405                        (PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT7 |
10406                         PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT6 |
10407                         PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT5));
10408         }
10409
10410         ecore_init_block(sc, BLOCK_NIG, PHASE_COMMON);
10411
10412         /* in E3 this done in per-port section */
10413         if (!CHIP_IS_E3(sc))
10414                 REG_WR(sc, NIG_REG_LLH_MF_MODE, IS_MF(sc));
10415
10416         if (CHIP_IS_E1H(sc)) {
10417 /* not applicable for E2 (and above ...) */
10418                 REG_WR(sc, NIG_REG_LLH_E1HOV_MODE, IS_MF_SD(sc));
10419         }
10420
10421         if (CHIP_REV_IS_SLOW(sc)) {
10422                 DELAY(200000);
10423         }
10424
10425         /* finish CFC init */
10426         val = reg_poll(sc, CFC_REG_LL_INIT_DONE, 1, 100, 10);
10427         if (val != 1) {
10428                 PMD_DRV_LOG(NOTICE, "CFC LL_INIT failed");
10429                 return -1;
10430         }
10431         val = reg_poll(sc, CFC_REG_AC_INIT_DONE, 1, 100, 10);
10432         if (val != 1) {
10433                 PMD_DRV_LOG(NOTICE, "CFC AC_INIT failed");
10434                 return -1;
10435         }
10436         val = reg_poll(sc, CFC_REG_CAM_INIT_DONE, 1, 100, 10);
10437         if (val != 1) {
10438                 PMD_DRV_LOG(NOTICE, "CFC CAM_INIT failed");
10439                 return -1;
10440         }
10441         REG_WR(sc, CFC_REG_DEBUG0, 0);
10442
10443         bnx2x_setup_fan_failure_detection(sc);
10444
10445         /* clear PXP2 attentions */
10446         REG_RD(sc, PXP2_REG_PXP2_INT_STS_CLR_0);
10447
10448         bnx2x_enable_blocks_attention(sc);
10449
10450         if (!CHIP_REV_IS_SLOW(sc)) {
10451                 ecore_enable_blocks_parity(sc);
10452         }
10453
10454         if (!BNX2X_NOMCP(sc)) {
10455                 if (CHIP_IS_E1x(sc)) {
10456                         bnx2x_common_init_phy(sc);
10457                 }
10458         }
10459
10460         return 0;
10461 }
10462
10463 /**
10464  * bnx2x_init_hw_common_chip - init HW at the COMMON_CHIP phase.
10465  *
10466  * @sc:     driver handle
10467  */
10468 static int bnx2x_init_hw_common_chip(struct bnx2x_softc *sc)
10469 {
10470         int rc = bnx2x_init_hw_common(sc);
10471
10472         if (rc) {
10473                 return rc;
10474         }
10475
10476         /* In E2 2-PORT mode, same ext phy is used for the two paths */
10477         if (!BNX2X_NOMCP(sc)) {
10478                 bnx2x_common_init_phy(sc);
10479         }
10480
10481         return 0;
10482 }
10483
10484 static int bnx2x_init_hw_port(struct bnx2x_softc *sc)
10485 {
10486         int port = SC_PORT(sc);
10487         int init_phase = port ? PHASE_PORT1 : PHASE_PORT0;
10488         uint32_t low, high;
10489         uint32_t val;
10490
10491         PMD_DRV_LOG(DEBUG, "starting port init for port %d", port);
10492
10493         REG_WR(sc, NIG_REG_MASK_INTERRUPT_PORT0 + port * 4, 0);
10494
10495         ecore_init_block(sc, BLOCK_MISC, init_phase);
10496         ecore_init_block(sc, BLOCK_PXP, init_phase);
10497         ecore_init_block(sc, BLOCK_PXP2, init_phase);
10498
10499         /*
10500          * Timers bug workaround: disables the pf_master bit in pglue at
10501          * common phase, we need to enable it here before any dmae access are
10502          * attempted. Therefore we manually added the enable-master to the
10503          * port phase (it also happens in the function phase)
10504          */
10505         if (!CHIP_IS_E1x(sc)) {
10506                 REG_WR(sc, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 1);
10507         }
10508
10509         ecore_init_block(sc, BLOCK_ATC, init_phase);
10510         ecore_init_block(sc, BLOCK_DMAE, init_phase);
10511         ecore_init_block(sc, BLOCK_PGLUE_B, init_phase);
10512         ecore_init_block(sc, BLOCK_QM, init_phase);
10513
10514         ecore_init_block(sc, BLOCK_TCM, init_phase);
10515         ecore_init_block(sc, BLOCK_UCM, init_phase);
10516         ecore_init_block(sc, BLOCK_CCM, init_phase);
10517         ecore_init_block(sc, BLOCK_XCM, init_phase);
10518
10519         /* QM cid (connection) count */
10520         ecore_qm_init_cid_count(sc, sc->qm_cid_count, INITOP_SET);
10521
10522         if (CNIC_SUPPORT(sc)) {
10523                 ecore_init_block(sc, BLOCK_TM, init_phase);
10524                 REG_WR(sc, TM_REG_LIN0_SCAN_TIME + port * 4, 20);
10525                 REG_WR(sc, TM_REG_LIN0_MAX_ACTIVE_CID + port * 4, 31);
10526         }
10527
10528         ecore_init_block(sc, BLOCK_DORQ, init_phase);
10529
10530         ecore_init_block(sc, BLOCK_BRB1, init_phase);
10531
10532         if (CHIP_IS_E1H(sc)) {
10533                 if (IS_MF(sc)) {
10534                         low = (BNX2X_ONE_PORT(sc) ? 160 : 246);
10535                 } else if (sc->mtu > 4096) {
10536                         if (BNX2X_ONE_PORT(sc)) {
10537                                 low = 160;
10538                         } else {
10539                                 val = sc->mtu;
10540                                 /* (24*1024 + val*4)/256 */
10541                                 low = (96 + (val / 64) + ((val % 64) ? 1 : 0));
10542                         }
10543                 } else {
10544                         low = (BNX2X_ONE_PORT(sc) ? 80 : 160);
10545                 }
10546                 high = (low + 56);      /* 14*1024/256 */
10547                 REG_WR(sc, BRB1_REG_PAUSE_LOW_THRESHOLD_0 + port * 4, low);
10548                 REG_WR(sc, BRB1_REG_PAUSE_HIGH_THRESHOLD_0 + port * 4, high);
10549         }
10550
10551         if (CHIP_IS_MODE_4_PORT(sc)) {
10552                 REG_WR(sc, SC_PORT(sc) ?
10553                        BRB1_REG_MAC_GUARANTIED_1 :
10554                        BRB1_REG_MAC_GUARANTIED_0, 40);
10555         }
10556
10557         ecore_init_block(sc, BLOCK_PRS, init_phase);
10558         if (CHIP_IS_E3B0(sc)) {
10559                 if (IS_MF_AFEX(sc)) {
10560                         /* configure headers for AFEX mode */
10561                         if (SC_PORT(sc)) {
10562                                 REG_WR(sc, PRS_REG_HDRS_AFTER_BASIC_PORT_1,
10563                                        0xE);
10564                                 REG_WR(sc, PRS_REG_HDRS_AFTER_TAG_0_PORT_1,
10565                                        0x6);
10566                                 REG_WR(sc, PRS_REG_MUST_HAVE_HDRS_PORT_1, 0xA);
10567                         } else {
10568                                 REG_WR(sc, PRS_REG_HDRS_AFTER_BASIC_PORT_0,
10569                                        0xE);
10570                                 REG_WR(sc, PRS_REG_HDRS_AFTER_TAG_0_PORT_0,
10571                                        0x6);
10572                                 REG_WR(sc, PRS_REG_MUST_HAVE_HDRS_PORT_0, 0xA);
10573                         }
10574                 } else {
10575                         /* Ovlan exists only if we are in multi-function +
10576                          * switch-dependent mode, in switch-independent there
10577                          * is no ovlan headers
10578                          */
10579                         REG_WR(sc, SC_PORT(sc) ?
10580                                PRS_REG_HDRS_AFTER_BASIC_PORT_1 :
10581                                PRS_REG_HDRS_AFTER_BASIC_PORT_0,
10582                                (sc->devinfo.mf_info.path_has_ovlan ? 7 : 6));
10583                 }
10584         }
10585
10586         ecore_init_block(sc, BLOCK_TSDM, init_phase);
10587         ecore_init_block(sc, BLOCK_CSDM, init_phase);
10588         ecore_init_block(sc, BLOCK_USDM, init_phase);
10589         ecore_init_block(sc, BLOCK_XSDM, init_phase);
10590
10591         ecore_init_block(sc, BLOCK_TSEM, init_phase);
10592         ecore_init_block(sc, BLOCK_USEM, init_phase);
10593         ecore_init_block(sc, BLOCK_CSEM, init_phase);
10594         ecore_init_block(sc, BLOCK_XSEM, init_phase);
10595
10596         ecore_init_block(sc, BLOCK_UPB, init_phase);
10597         ecore_init_block(sc, BLOCK_XPB, init_phase);
10598
10599         ecore_init_block(sc, BLOCK_PBF, init_phase);
10600
10601         if (CHIP_IS_E1x(sc)) {
10602 /* configure PBF to work without PAUSE mtu 9000 */
10603                 REG_WR(sc, PBF_REG_P0_PAUSE_ENABLE + port * 4, 0);
10604
10605 /* update threshold */
10606                 REG_WR(sc, PBF_REG_P0_ARB_THRSH + port * 4, (9040 / 16));
10607 /* update init credit */
10608                 REG_WR(sc, PBF_REG_P0_INIT_CRD + port * 4,
10609                        (9040 / 16) + 553 - 22);
10610
10611 /* probe changes */
10612                 REG_WR(sc, PBF_REG_INIT_P0 + port * 4, 1);
10613                 DELAY(50);
10614                 REG_WR(sc, PBF_REG_INIT_P0 + port * 4, 0);
10615         }
10616
10617         if (CNIC_SUPPORT(sc)) {
10618                 ecore_init_block(sc, BLOCK_SRC, init_phase);
10619         }
10620
10621         ecore_init_block(sc, BLOCK_CDU, init_phase);
10622         ecore_init_block(sc, BLOCK_CFC, init_phase);
10623         ecore_init_block(sc, BLOCK_HC, init_phase);
10624         ecore_init_block(sc, BLOCK_IGU, init_phase);
10625         ecore_init_block(sc, BLOCK_MISC_AEU, init_phase);
10626         /* init aeu_mask_attn_func_0/1:
10627          *  - SF mode: bits 3-7 are masked. only bits 0-2 are in use
10628          *  - MF mode: bit 3 is masked. bits 0-2 are in use as in SF
10629          *             bits 4-7 are used for "per vn group attention" */
10630         val = IS_MF(sc) ? 0xF7 : 0x7;
10631         val |= 0x10;
10632         REG_WR(sc, MISC_REG_AEU_MASK_ATTN_FUNC_0 + port * 4, val);
10633
10634         ecore_init_block(sc, BLOCK_NIG, init_phase);
10635
10636         if (!CHIP_IS_E1x(sc)) {
10637 /* Bit-map indicating which L2 hdrs may appear after the
10638  * basic Ethernet header
10639  */
10640                 if (IS_MF_AFEX(sc)) {
10641                         REG_WR(sc, SC_PORT(sc) ?
10642                                NIG_REG_P1_HDRS_AFTER_BASIC :
10643                                NIG_REG_P0_HDRS_AFTER_BASIC, 0xE);
10644                 } else {
10645                         REG_WR(sc, SC_PORT(sc) ?
10646                                NIG_REG_P1_HDRS_AFTER_BASIC :
10647                                NIG_REG_P0_HDRS_AFTER_BASIC,
10648                                IS_MF_SD(sc) ? 7 : 6);
10649                 }
10650
10651                 if (CHIP_IS_E3(sc)) {
10652                         REG_WR(sc, SC_PORT(sc) ?
10653                                NIG_REG_LLH1_MF_MODE :
10654                                NIG_REG_LLH_MF_MODE, IS_MF(sc));
10655                 }
10656         }
10657         if (!CHIP_IS_E3(sc)) {
10658                 REG_WR(sc, NIG_REG_XGXS_SERDES0_MODE_SEL + port * 4, 1);
10659         }
10660
10661         /* 0x2 disable mf_ov, 0x1 enable */
10662         REG_WR(sc, NIG_REG_LLH0_BRB1_DRV_MASK_MF + port * 4,
10663                (IS_MF_SD(sc) ? 0x1 : 0x2));
10664
10665         if (!CHIP_IS_E1x(sc)) {
10666                 val = 0;
10667                 switch (sc->devinfo.mf_info.mf_mode) {
10668                 case MULTI_FUNCTION_SD:
10669                         val = 1;
10670                         break;
10671                 case MULTI_FUNCTION_SI:
10672                 case MULTI_FUNCTION_AFEX:
10673                         val = 2;
10674                         break;
10675                 }
10676
10677                 REG_WR(sc, (SC_PORT(sc) ? NIG_REG_LLH1_CLS_TYPE :
10678                             NIG_REG_LLH0_CLS_TYPE), val);
10679         }
10680         REG_WR(sc, NIG_REG_LLFC_ENABLE_0 + port * 4, 0);
10681         REG_WR(sc, NIG_REG_LLFC_OUT_EN_0 + port * 4, 0);
10682         REG_WR(sc, NIG_REG_PAUSE_ENABLE_0 + port * 4, 1);
10683
10684         /* If SPIO5 is set to generate interrupts, enable it for this port */
10685         val = REG_RD(sc, MISC_REG_SPIO_EVENT_EN);
10686         if (val & MISC_SPIO_SPIO5) {
10687                 uint32_t reg_addr = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 :
10688                                      MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0);
10689                 val = REG_RD(sc, reg_addr);
10690                 val |= AEU_INPUTS_ATTN_BITS_SPIO5;
10691                 REG_WR(sc, reg_addr, val);
10692         }
10693
10694         return 0;
10695 }
10696
10697 static uint32_t
10698 bnx2x_flr_clnup_reg_poll(struct bnx2x_softc *sc, uint32_t reg,
10699                        uint32_t expected, uint32_t poll_count)
10700 {
10701         uint32_t cur_cnt = poll_count;
10702         uint32_t val;
10703
10704         while ((val = REG_RD(sc, reg)) != expected && cur_cnt--) {
10705                 DELAY(FLR_WAIT_INTERVAL);
10706         }
10707
10708         return val;
10709 }
10710
10711 static int
10712 bnx2x_flr_clnup_poll_hw_counter(struct bnx2x_softc *sc, uint32_t reg,
10713                               __rte_unused const char *msg, uint32_t poll_cnt)
10714 {
10715         uint32_t val = bnx2x_flr_clnup_reg_poll(sc, reg, 0, poll_cnt);
10716
10717         if (val != 0) {
10718                 PMD_DRV_LOG(NOTICE, "%s usage count=%d", msg, val);
10719                 return -1;
10720         }
10721
10722         return 0;
10723 }
10724
10725 /* Common routines with VF FLR cleanup */
10726 static uint32_t bnx2x_flr_clnup_poll_count(struct bnx2x_softc *sc)
10727 {
10728         /* adjust polling timeout */
10729         if (CHIP_REV_IS_EMUL(sc)) {
10730                 return FLR_POLL_CNT * 2000;
10731         }
10732
10733         if (CHIP_REV_IS_FPGA(sc)) {
10734                 return FLR_POLL_CNT * 120;
10735         }
10736
10737         return FLR_POLL_CNT;
10738 }
10739
10740 static int bnx2x_poll_hw_usage_counters(struct bnx2x_softc *sc, uint32_t poll_cnt)
10741 {
10742         /* wait for CFC PF usage-counter to zero (includes all the VFs) */
10743         if (bnx2x_flr_clnup_poll_hw_counter(sc,
10744                                           CFC_REG_NUM_LCIDS_INSIDE_PF,
10745                                           "CFC PF usage counter timed out",
10746                                           poll_cnt)) {
10747                 return -1;
10748         }
10749
10750         /* Wait for DQ PF usage-counter to zero (until DQ cleanup) */
10751         if (bnx2x_flr_clnup_poll_hw_counter(sc,
10752                                           DORQ_REG_PF_USAGE_CNT,
10753                                           "DQ PF usage counter timed out",
10754                                           poll_cnt)) {
10755                 return -1;
10756         }
10757
10758         /* Wait for QM PF usage-counter to zero (until DQ cleanup) */
10759         if (bnx2x_flr_clnup_poll_hw_counter(sc,
10760                                           QM_REG_PF_USG_CNT_0 + 4 * SC_FUNC(sc),
10761                                           "QM PF usage counter timed out",
10762                                           poll_cnt)) {
10763                 return -1;
10764         }
10765
10766         /* Wait for Timer PF usage-counters to zero (until DQ cleanup) */
10767         if (bnx2x_flr_clnup_poll_hw_counter(sc,
10768                                           TM_REG_LIN0_VNIC_UC + 4 * SC_PORT(sc),
10769                                           "Timers VNIC usage counter timed out",
10770                                           poll_cnt)) {
10771                 return -1;
10772         }
10773
10774         if (bnx2x_flr_clnup_poll_hw_counter(sc,
10775                                           TM_REG_LIN0_NUM_SCANS +
10776                                           4 * SC_PORT(sc),
10777                                           "Timers NUM_SCANS usage counter timed out",
10778                                           poll_cnt)) {
10779                 return -1;
10780         }
10781
10782         /* Wait DMAE PF usage counter to zero */
10783         if (bnx2x_flr_clnup_poll_hw_counter(sc,
10784                                           dmae_reg_go_c[INIT_DMAE_C(sc)],
10785                                           "DMAE dommand register timed out",
10786                                           poll_cnt)) {
10787                 return -1;
10788         }
10789
10790         return 0;
10791 }
10792
10793 #define OP_GEN_PARAM(param)                                            \
10794         (((param) << SDM_OP_GEN_COMP_PARAM_SHIFT) & SDM_OP_GEN_COMP_PARAM)
10795 #define OP_GEN_TYPE(type)                                           \
10796         (((type) << SDM_OP_GEN_COMP_TYPE_SHIFT) & SDM_OP_GEN_COMP_TYPE)
10797 #define OP_GEN_AGG_VECT(index)                                             \
10798         (((index) << SDM_OP_GEN_AGG_VECT_IDX_SHIFT) & SDM_OP_GEN_AGG_VECT_IDX)
10799
10800 static int
10801 bnx2x_send_final_clnup(struct bnx2x_softc *sc, uint8_t clnup_func,
10802                      uint32_t poll_cnt)
10803 {
10804         uint32_t op_gen_command = 0;
10805         uint32_t comp_addr = (BAR_CSTRORM_INTMEM +
10806                               CSTORM_FINAL_CLEANUP_COMPLETE_OFFSET(clnup_func));
10807         int ret = 0;
10808
10809         if (REG_RD(sc, comp_addr)) {
10810                 PMD_DRV_LOG(NOTICE,
10811                             "Cleanup complete was not 0 before sending");
10812                 return -1;
10813         }
10814
10815         op_gen_command |= OP_GEN_PARAM(XSTORM_AGG_INT_FINAL_CLEANUP_INDEX);
10816         op_gen_command |= OP_GEN_TYPE(XSTORM_AGG_INT_FINAL_CLEANUP_COMP_TYPE);
10817         op_gen_command |= OP_GEN_AGG_VECT(clnup_func);
10818         op_gen_command |= 1 << SDM_OP_GEN_AGG_VECT_IDX_VALID_SHIFT;
10819
10820         REG_WR(sc, XSDM_REG_OPERATION_GEN, op_gen_command);
10821
10822         if (bnx2x_flr_clnup_reg_poll(sc, comp_addr, 1, poll_cnt) != 1) {
10823                 PMD_DRV_LOG(NOTICE, "FW final cleanup did not succeed");
10824                 PMD_DRV_LOG(DEBUG, "At timeout completion address contained %x",
10825                             (REG_RD(sc, comp_addr)));
10826                 rte_panic("FLR cleanup failed");
10827                 return -1;
10828         }
10829
10830         /* Zero completion for nxt FLR */
10831         REG_WR(sc, comp_addr, 0);
10832
10833         return ret;
10834 }
10835
10836 static void
10837 bnx2x_pbf_pN_buf_flushed(struct bnx2x_softc *sc, struct pbf_pN_buf_regs *regs,
10838                        uint32_t poll_count)
10839 {
10840         uint32_t init_crd, crd, crd_start, crd_freed, crd_freed_start;
10841         uint32_t cur_cnt = poll_count;
10842
10843         crd_freed = crd_freed_start = REG_RD(sc, regs->crd_freed);
10844         crd = crd_start = REG_RD(sc, regs->crd);
10845         init_crd = REG_RD(sc, regs->init_crd);
10846
10847         while ((crd != init_crd) &&
10848                ((uint32_t) ((int32_t) crd_freed - (int32_t) crd_freed_start) <
10849                 (init_crd - crd_start))) {
10850                 if (cur_cnt--) {
10851                         DELAY(FLR_WAIT_INTERVAL);
10852                         crd = REG_RD(sc, regs->crd);
10853                         crd_freed = REG_RD(sc, regs->crd_freed);
10854                 } else {
10855                         break;
10856                 }
10857         }
10858 }
10859
10860 static void
10861 bnx2x_pbf_pN_cmd_flushed(struct bnx2x_softc *sc, struct pbf_pN_cmd_regs *regs,
10862                        uint32_t poll_count)
10863 {
10864         uint32_t occup, to_free, freed, freed_start;
10865         uint32_t cur_cnt = poll_count;
10866
10867         occup = to_free = REG_RD(sc, regs->lines_occup);
10868         freed = freed_start = REG_RD(sc, regs->lines_freed);
10869
10870         while (occup &&
10871                ((uint32_t) ((int32_t) freed - (int32_t) freed_start) <
10872                 to_free)) {
10873                 if (cur_cnt--) {
10874                         DELAY(FLR_WAIT_INTERVAL);
10875                         occup = REG_RD(sc, regs->lines_occup);
10876                         freed = REG_RD(sc, regs->lines_freed);
10877                 } else {
10878                         break;
10879                 }
10880         }
10881 }
10882
10883 static void bnx2x_tx_hw_flushed(struct bnx2x_softc *sc, uint32_t poll_count)
10884 {
10885         struct pbf_pN_cmd_regs cmd_regs[] = {
10886                 {0, (CHIP_IS_E3B0(sc)) ?
10887                  PBF_REG_TQ_OCCUPANCY_Q0 : PBF_REG_P0_TQ_OCCUPANCY,
10888                  (CHIP_IS_E3B0(sc)) ?
10889                  PBF_REG_TQ_LINES_FREED_CNT_Q0 : PBF_REG_P0_TQ_LINES_FREED_CNT},
10890                 {1, (CHIP_IS_E3B0(sc)) ?
10891                  PBF_REG_TQ_OCCUPANCY_Q1 : PBF_REG_P1_TQ_OCCUPANCY,
10892                  (CHIP_IS_E3B0(sc)) ?
10893                  PBF_REG_TQ_LINES_FREED_CNT_Q1 : PBF_REG_P1_TQ_LINES_FREED_CNT},
10894                 {4, (CHIP_IS_E3B0(sc)) ?
10895                  PBF_REG_TQ_OCCUPANCY_LB_Q : PBF_REG_P4_TQ_OCCUPANCY,
10896                  (CHIP_IS_E3B0(sc)) ?
10897                  PBF_REG_TQ_LINES_FREED_CNT_LB_Q :
10898                  PBF_REG_P4_TQ_LINES_FREED_CNT}
10899         };
10900
10901         struct pbf_pN_buf_regs buf_regs[] = {
10902                 {0, (CHIP_IS_E3B0(sc)) ?
10903                  PBF_REG_INIT_CRD_Q0 : PBF_REG_P0_INIT_CRD,
10904                  (CHIP_IS_E3B0(sc)) ? PBF_REG_CREDIT_Q0 : PBF_REG_P0_CREDIT,
10905                  (CHIP_IS_E3B0(sc)) ?
10906                  PBF_REG_INTERNAL_CRD_FREED_CNT_Q0 :
10907                  PBF_REG_P0_INTERNAL_CRD_FREED_CNT},
10908                 {1, (CHIP_IS_E3B0(sc)) ?
10909                  PBF_REG_INIT_CRD_Q1 : PBF_REG_P1_INIT_CRD,
10910                  (CHIP_IS_E3B0(sc)) ? PBF_REG_CREDIT_Q1 : PBF_REG_P1_CREDIT,
10911                  (CHIP_IS_E3B0(sc)) ?
10912                  PBF_REG_INTERNAL_CRD_FREED_CNT_Q1 :
10913                  PBF_REG_P1_INTERNAL_CRD_FREED_CNT},
10914                 {4, (CHIP_IS_E3B0(sc)) ?
10915                  PBF_REG_INIT_CRD_LB_Q : PBF_REG_P4_INIT_CRD,
10916                  (CHIP_IS_E3B0(sc)) ? PBF_REG_CREDIT_LB_Q : PBF_REG_P4_CREDIT,
10917                  (CHIP_IS_E3B0(sc)) ?
10918                  PBF_REG_INTERNAL_CRD_FREED_CNT_LB_Q :
10919                  PBF_REG_P4_INTERNAL_CRD_FREED_CNT},
10920         };
10921
10922         uint32_t i;
10923
10924         /* Verify the command queues are flushed P0, P1, P4 */
10925         for (i = 0; i < ARRAY_SIZE(cmd_regs); i++) {
10926                 bnx2x_pbf_pN_cmd_flushed(sc, &cmd_regs[i], poll_count);
10927         }
10928
10929         /* Verify the transmission buffers are flushed P0, P1, P4 */
10930         for (i = 0; i < ARRAY_SIZE(buf_regs); i++) {
10931                 bnx2x_pbf_pN_buf_flushed(sc, &buf_regs[i], poll_count);
10932         }
10933 }
10934
10935 static void bnx2x_hw_enable_status(struct bnx2x_softc *sc)
10936 {
10937         __rte_unused uint32_t val;
10938
10939         val = REG_RD(sc, CFC_REG_WEAK_ENABLE_PF);
10940         PMD_DRV_LOG(DEBUG, "CFC_REG_WEAK_ENABLE_PF is 0x%x", val);
10941
10942         val = REG_RD(sc, PBF_REG_DISABLE_PF);
10943         PMD_DRV_LOG(DEBUG, "PBF_REG_DISABLE_PF is 0x%x", val);
10944
10945         val = REG_RD(sc, IGU_REG_PCI_PF_MSI_EN);
10946         PMD_DRV_LOG(DEBUG, "IGU_REG_PCI_PF_MSI_EN is 0x%x", val);
10947
10948         val = REG_RD(sc, IGU_REG_PCI_PF_MSIX_EN);
10949         PMD_DRV_LOG(DEBUG, "IGU_REG_PCI_PF_MSIX_EN is 0x%x", val);
10950
10951         val = REG_RD(sc, IGU_REG_PCI_PF_MSIX_FUNC_MASK);
10952         PMD_DRV_LOG(DEBUG, "IGU_REG_PCI_PF_MSIX_FUNC_MASK is 0x%x", val);
10953
10954         val = REG_RD(sc, PGLUE_B_REG_SHADOW_BME_PF_7_0_CLR);
10955         PMD_DRV_LOG(DEBUG, "PGLUE_B_REG_SHADOW_BME_PF_7_0_CLR is 0x%x", val);
10956
10957         val = REG_RD(sc, PGLUE_B_REG_FLR_REQUEST_PF_7_0_CLR);
10958         PMD_DRV_LOG(DEBUG, "PGLUE_B_REG_FLR_REQUEST_PF_7_0_CLR is 0x%x", val);
10959
10960         val = REG_RD(sc, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER);
10961         PMD_DRV_LOG(DEBUG, "PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER is 0x%x",
10962                     val);
10963 }
10964
10965 /**
10966  *      bnx2x_pf_flr_clnup
10967  *      a. re-enable target read on the PF
10968  *      b. poll cfc per function usgae counter
10969  *      c. poll the qm perfunction usage counter
10970  *      d. poll the tm per function usage counter
10971  *      e. poll the tm per function scan-done indication
10972  *      f. clear the dmae channel associated wit hthe PF
10973  *      g. zero the igu 'trailing edge' and 'leading edge' regs (attentions)
10974  *      h. call the common flr cleanup code with -1 (pf indication)
10975  */
10976 static int bnx2x_pf_flr_clnup(struct bnx2x_softc *sc)
10977 {
10978         uint32_t poll_cnt = bnx2x_flr_clnup_poll_count(sc);
10979
10980         /* Re-enable PF target read access */
10981         REG_WR(sc, PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_READ, 1);
10982
10983         /* Poll HW usage counters */
10984         if (bnx2x_poll_hw_usage_counters(sc, poll_cnt)) {
10985                 return -1;
10986         }
10987
10988         /* Zero the igu 'trailing edge' and 'leading edge' */
10989
10990         /* Send the FW cleanup command */
10991         if (bnx2x_send_final_clnup(sc, (uint8_t) SC_FUNC(sc), poll_cnt)) {
10992                 return -1;
10993         }
10994
10995         /* ATC cleanup */
10996
10997         /* Verify TX hw is flushed */
10998         bnx2x_tx_hw_flushed(sc, poll_cnt);
10999
11000         /* Wait 100ms (not adjusted according to platform) */
11001         DELAY(100000);
11002
11003         /* Verify no pending pci transactions */
11004         if (bnx2x_is_pcie_pending(sc)) {
11005                 PMD_DRV_LOG(NOTICE, "PCIE Transactions still pending");
11006         }
11007
11008         /* Debug */
11009         bnx2x_hw_enable_status(sc);
11010
11011         /*
11012          * Master enable - Due to WB DMAE writes performed before this
11013          * register is re-initialized as part of the regular function init
11014          */
11015         REG_WR(sc, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 1);
11016
11017         return 0;
11018 }
11019
11020 static int bnx2x_init_hw_func(struct bnx2x_softc *sc)
11021 {
11022         int port = SC_PORT(sc);
11023         int func = SC_FUNC(sc);
11024         int init_phase = PHASE_PF0 + func;
11025         struct ecore_ilt *ilt = sc->ilt;
11026         uint16_t cdu_ilt_start;
11027         uint32_t addr, val;
11028         uint32_t main_mem_base, main_mem_size, main_mem_prty_clr;
11029         int main_mem_width, rc;
11030         uint32_t i;
11031
11032         PMD_DRV_LOG(DEBUG, "starting func init for func %d", func);
11033
11034         /* FLR cleanup */
11035         if (!CHIP_IS_E1x(sc)) {
11036                 rc = bnx2x_pf_flr_clnup(sc);
11037                 if (rc) {
11038                         PMD_DRV_LOG(NOTICE, "FLR cleanup failed!");
11039                         return rc;
11040                 }
11041         }
11042
11043         /* set MSI reconfigure capability */
11044         if (sc->devinfo.int_block == INT_BLOCK_HC) {
11045                 addr = (port ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0);
11046                 val = REG_RD(sc, addr);
11047                 val |= HC_CONFIG_0_REG_MSI_ATTN_EN_0;
11048                 REG_WR(sc, addr, val);
11049         }
11050
11051         ecore_init_block(sc, BLOCK_PXP, init_phase);
11052         ecore_init_block(sc, BLOCK_PXP2, init_phase);
11053
11054         ilt = sc->ilt;
11055         cdu_ilt_start = ilt->clients[ILT_CLIENT_CDU].start;
11056
11057         for (i = 0; i < L2_ILT_LINES(sc); i++) {
11058                 ilt->lines[cdu_ilt_start + i].page = sc->context[i].vcxt;
11059                 ilt->lines[cdu_ilt_start + i].page_mapping =
11060                     (rte_iova_t)sc->context[i].vcxt_dma.paddr;
11061                 ilt->lines[cdu_ilt_start + i].size = sc->context[i].size;
11062         }
11063         ecore_ilt_init_op(sc, INITOP_SET);
11064
11065         REG_WR(sc, PRS_REG_NIC_MODE, 1);
11066
11067         if (!CHIP_IS_E1x(sc)) {
11068                 uint32_t pf_conf = IGU_PF_CONF_FUNC_EN;
11069
11070 /* Turn on a single ISR mode in IGU if driver is going to use
11071  * INT#x or MSI
11072  */
11073                 if ((sc->interrupt_mode != INTR_MODE_MSIX)
11074                     || (sc->interrupt_mode != INTR_MODE_SINGLE_MSIX)) {
11075                         pf_conf |= IGU_PF_CONF_SINGLE_ISR_EN;
11076                 }
11077
11078 /*
11079  * Timers workaround bug: function init part.
11080  * Need to wait 20msec after initializing ILT,
11081  * needed to make sure there are no requests in
11082  * one of the PXP internal queues with "old" ILT addresses
11083  */
11084                 DELAY(20000);
11085
11086 /*
11087  * Master enable - Due to WB DMAE writes performed before this
11088  * register is re-initialized as part of the regular function
11089  * init
11090  */
11091                 REG_WR(sc, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 1);
11092 /* Enable the function in IGU */
11093                 REG_WR(sc, IGU_REG_PF_CONFIGURATION, pf_conf);
11094         }
11095
11096         sc->dmae_ready = 1;
11097
11098         ecore_init_block(sc, BLOCK_PGLUE_B, init_phase);
11099
11100         if (!CHIP_IS_E1x(sc))
11101                 REG_WR(sc, PGLUE_B_REG_WAS_ERROR_PF_7_0_CLR, func);
11102
11103         ecore_init_block(sc, BLOCK_ATC, init_phase);
11104         ecore_init_block(sc, BLOCK_DMAE, init_phase);
11105         ecore_init_block(sc, BLOCK_NIG, init_phase);
11106         ecore_init_block(sc, BLOCK_SRC, init_phase);
11107         ecore_init_block(sc, BLOCK_MISC, init_phase);
11108         ecore_init_block(sc, BLOCK_TCM, init_phase);
11109         ecore_init_block(sc, BLOCK_UCM, init_phase);
11110         ecore_init_block(sc, BLOCK_CCM, init_phase);
11111         ecore_init_block(sc, BLOCK_XCM, init_phase);
11112         ecore_init_block(sc, BLOCK_TSEM, init_phase);
11113         ecore_init_block(sc, BLOCK_USEM, init_phase);
11114         ecore_init_block(sc, BLOCK_CSEM, init_phase);
11115         ecore_init_block(sc, BLOCK_XSEM, init_phase);
11116
11117         if (!CHIP_IS_E1x(sc))
11118                 REG_WR(sc, QM_REG_PF_EN, 1);
11119
11120         if (!CHIP_IS_E1x(sc)) {
11121                 REG_WR(sc, TSEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func);
11122                 REG_WR(sc, USEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func);
11123                 REG_WR(sc, CSEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func);
11124                 REG_WR(sc, XSEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func);
11125         }
11126         ecore_init_block(sc, BLOCK_QM, init_phase);
11127
11128         ecore_init_block(sc, BLOCK_TM, init_phase);
11129         ecore_init_block(sc, BLOCK_DORQ, init_phase);
11130
11131         ecore_init_block(sc, BLOCK_BRB1, init_phase);
11132         ecore_init_block(sc, BLOCK_PRS, init_phase);
11133         ecore_init_block(sc, BLOCK_TSDM, init_phase);
11134         ecore_init_block(sc, BLOCK_CSDM, init_phase);
11135         ecore_init_block(sc, BLOCK_USDM, init_phase);
11136         ecore_init_block(sc, BLOCK_XSDM, init_phase);
11137         ecore_init_block(sc, BLOCK_UPB, init_phase);
11138         ecore_init_block(sc, BLOCK_XPB, init_phase);
11139         ecore_init_block(sc, BLOCK_PBF, init_phase);
11140         if (!CHIP_IS_E1x(sc))
11141                 REG_WR(sc, PBF_REG_DISABLE_PF, 0);
11142
11143         ecore_init_block(sc, BLOCK_CDU, init_phase);
11144
11145         ecore_init_block(sc, BLOCK_CFC, init_phase);
11146
11147         if (!CHIP_IS_E1x(sc))
11148                 REG_WR(sc, CFC_REG_WEAK_ENABLE_PF, 1);
11149
11150         if (IS_MF(sc)) {
11151                 REG_WR(sc, NIG_REG_LLH0_FUNC_EN + port * 8, 1);
11152                 REG_WR(sc, NIG_REG_LLH0_FUNC_VLAN_ID + port * 8, OVLAN(sc));
11153         }
11154
11155         ecore_init_block(sc, BLOCK_MISC_AEU, init_phase);
11156
11157         /* HC init per function */
11158         if (sc->devinfo.int_block == INT_BLOCK_HC) {
11159                 if (CHIP_IS_E1H(sc)) {
11160                         REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_12 + func * 4, 0);
11161
11162                         REG_WR(sc, HC_REG_LEADING_EDGE_0 + port * 8, 0);
11163                         REG_WR(sc, HC_REG_TRAILING_EDGE_0 + port * 8, 0);
11164                 }
11165                 ecore_init_block(sc, BLOCK_HC, init_phase);
11166
11167         } else {
11168                 uint32_t num_segs, sb_idx, prod_offset;
11169
11170                 REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_12 + func * 4, 0);
11171
11172                 if (!CHIP_IS_E1x(sc)) {
11173                         REG_WR(sc, IGU_REG_LEADING_EDGE_LATCH, 0);
11174                         REG_WR(sc, IGU_REG_TRAILING_EDGE_LATCH, 0);
11175                 }
11176
11177                 ecore_init_block(sc, BLOCK_IGU, init_phase);
11178
11179                 if (!CHIP_IS_E1x(sc)) {
11180                         int dsb_idx = 0;
11181         /**
11182          * Producer memory:
11183          * E2 mode: address 0-135 match to the mapping memory;
11184          * 136 - PF0 default prod; 137 - PF1 default prod;
11185          * 138 - PF2 default prod; 139 - PF3 default prod;
11186          * 140 - PF0 attn prod;    141 - PF1 attn prod;
11187          * 142 - PF2 attn prod;    143 - PF3 attn prod;
11188          * 144-147 reserved.
11189          *
11190          * E1.5 mode - In backward compatible mode;
11191          * for non default SB; each even line in the memory
11192          * holds the U producer and each odd line hold
11193          * the C producer. The first 128 producers are for
11194          * NDSB (PF0 - 0-31; PF1 - 32-63 and so on). The last 20
11195          * producers are for the DSB for each PF.
11196          * Each PF has five segments: (the order inside each
11197          * segment is PF0; PF1; PF2; PF3) - 128-131 U prods;
11198          * 132-135 C prods; 136-139 X prods; 140-143 T prods;
11199          * 144-147 attn prods;
11200          */
11201                         /* non-default-status-blocks */
11202                         num_segs = CHIP_INT_MODE_IS_BC(sc) ?
11203                             IGU_BC_NDSB_NUM_SEGS : IGU_NORM_NDSB_NUM_SEGS;
11204                         for (sb_idx = 0; sb_idx < sc->igu_sb_cnt; sb_idx++) {
11205                                 prod_offset = (sc->igu_base_sb + sb_idx) *
11206                                     num_segs;
11207
11208                                 for (i = 0; i < num_segs; i++) {
11209                                         addr = IGU_REG_PROD_CONS_MEMORY +
11210                                             (prod_offset + i) * 4;
11211                                         REG_WR(sc, addr, 0);
11212                                 }
11213                                 /* send consumer update with value 0 */
11214                                 bnx2x_ack_sb(sc, sc->igu_base_sb + sb_idx,
11215                                            USTORM_ID, 0, IGU_INT_NOP, 1);
11216                                 bnx2x_igu_clear_sb(sc, sc->igu_base_sb + sb_idx);
11217                         }
11218
11219                         /* default-status-blocks */
11220                         num_segs = CHIP_INT_MODE_IS_BC(sc) ?
11221                             IGU_BC_DSB_NUM_SEGS : IGU_NORM_DSB_NUM_SEGS;
11222
11223                         if (CHIP_IS_MODE_4_PORT(sc))
11224                                 dsb_idx = SC_FUNC(sc);
11225                         else
11226                                 dsb_idx = SC_VN(sc);
11227
11228                         prod_offset = (CHIP_INT_MODE_IS_BC(sc) ?
11229                                        IGU_BC_BASE_DSB_PROD + dsb_idx :
11230                                        IGU_NORM_BASE_DSB_PROD + dsb_idx);
11231
11232                         /*
11233                          * igu prods come in chunks of E1HVN_MAX (4) -
11234                          * does not matters what is the current chip mode
11235                          */
11236                         for (i = 0; i < (num_segs * E1HVN_MAX); i += E1HVN_MAX) {
11237                                 addr = IGU_REG_PROD_CONS_MEMORY +
11238                                     (prod_offset + i) * 4;
11239                                 REG_WR(sc, addr, 0);
11240                         }
11241                         /* send consumer update with 0 */
11242                         if (CHIP_INT_MODE_IS_BC(sc)) {
11243                                 bnx2x_ack_sb(sc, sc->igu_dsb_id,
11244                                            USTORM_ID, 0, IGU_INT_NOP, 1);
11245                                 bnx2x_ack_sb(sc, sc->igu_dsb_id,
11246                                            CSTORM_ID, 0, IGU_INT_NOP, 1);
11247                                 bnx2x_ack_sb(sc, sc->igu_dsb_id,
11248                                            XSTORM_ID, 0, IGU_INT_NOP, 1);
11249                                 bnx2x_ack_sb(sc, sc->igu_dsb_id,
11250                                            TSTORM_ID, 0, IGU_INT_NOP, 1);
11251                                 bnx2x_ack_sb(sc, sc->igu_dsb_id,
11252                                            ATTENTION_ID, 0, IGU_INT_NOP, 1);
11253                         } else {
11254                                 bnx2x_ack_sb(sc, sc->igu_dsb_id,
11255                                            USTORM_ID, 0, IGU_INT_NOP, 1);
11256                                 bnx2x_ack_sb(sc, sc->igu_dsb_id,
11257                                            ATTENTION_ID, 0, IGU_INT_NOP, 1);
11258                         }
11259                         bnx2x_igu_clear_sb(sc, sc->igu_dsb_id);
11260
11261                         /* !!! these should become driver const once
11262                            rf-tool supports split-68 const */
11263                         REG_WR(sc, IGU_REG_SB_INT_BEFORE_MASK_LSB, 0);
11264                         REG_WR(sc, IGU_REG_SB_INT_BEFORE_MASK_MSB, 0);
11265                         REG_WR(sc, IGU_REG_SB_MASK_LSB, 0);
11266                         REG_WR(sc, IGU_REG_SB_MASK_MSB, 0);
11267                         REG_WR(sc, IGU_REG_PBA_STATUS_LSB, 0);
11268                         REG_WR(sc, IGU_REG_PBA_STATUS_MSB, 0);
11269                 }
11270         }
11271
11272         /* Reset PCIE errors for debug */
11273         REG_WR(sc, 0x2114, 0xffffffff);
11274         REG_WR(sc, 0x2120, 0xffffffff);
11275
11276         if (CHIP_IS_E1x(sc)) {
11277                 main_mem_size = HC_REG_MAIN_MEMORY_SIZE / 2;    /*dwords */
11278                 main_mem_base = HC_REG_MAIN_MEMORY +
11279                     SC_PORT(sc) * (main_mem_size * 4);
11280                 main_mem_prty_clr = HC_REG_HC_PRTY_STS_CLR;
11281                 main_mem_width = 8;
11282
11283                 val = REG_RD(sc, main_mem_prty_clr);
11284                 if (val) {
11285                         PMD_DRV_LOG(DEBUG,
11286                                     "Parity errors in HC block during function init (0x%x)!",
11287                                     val);
11288                 }
11289
11290 /* Clear "false" parity errors in MSI-X table */
11291                 for (i = main_mem_base;
11292                      i < main_mem_base + main_mem_size * 4;
11293                      i += main_mem_width) {
11294                         bnx2x_read_dmae(sc, i, main_mem_width / 4);
11295                         bnx2x_write_dmae(sc, BNX2X_SP_MAPPING(sc, wb_data),
11296                                        i, main_mem_width / 4);
11297                 }
11298 /* Clear HC parity attention */
11299                 REG_RD(sc, main_mem_prty_clr);
11300         }
11301
11302         /* Enable STORMs SP logging */
11303         REG_WR8(sc, BAR_USTRORM_INTMEM +
11304                 USTORM_RECORD_SLOW_PATH_OFFSET(SC_FUNC(sc)), 1);
11305         REG_WR8(sc, BAR_TSTRORM_INTMEM +
11306                 TSTORM_RECORD_SLOW_PATH_OFFSET(SC_FUNC(sc)), 1);
11307         REG_WR8(sc, BAR_CSTRORM_INTMEM +
11308                 CSTORM_RECORD_SLOW_PATH_OFFSET(SC_FUNC(sc)), 1);
11309         REG_WR8(sc, BAR_XSTRORM_INTMEM +
11310                 XSTORM_RECORD_SLOW_PATH_OFFSET(SC_FUNC(sc)), 1);
11311
11312         elink_phy_probe(&sc->link_params);
11313
11314         return 0;
11315 }
11316
11317 static void bnx2x_link_reset(struct bnx2x_softc *sc)
11318 {
11319         if (!BNX2X_NOMCP(sc)) {
11320                 elink_lfa_reset(&sc->link_params, &sc->link_vars);
11321         } else {
11322                 if (!CHIP_REV_IS_SLOW(sc)) {
11323                         PMD_DRV_LOG(WARNING,
11324                                     "Bootcode is missing - cannot reset link");
11325                 }
11326         }
11327 }
11328
11329 static void bnx2x_reset_port(struct bnx2x_softc *sc)
11330 {
11331         int port = SC_PORT(sc);
11332         uint32_t val;
11333
11334         /* reset physical Link */
11335         bnx2x_link_reset(sc);
11336
11337         REG_WR(sc, NIG_REG_MASK_INTERRUPT_PORT0 + port * 4, 0);
11338
11339         /* Do not rcv packets to BRB */
11340         REG_WR(sc, NIG_REG_LLH0_BRB1_DRV_MASK + port * 4, 0x0);
11341         /* Do not direct rcv packets that are not for MCP to the BRB */
11342         REG_WR(sc, (port ? NIG_REG_LLH1_BRB1_NOT_MCP :
11343                     NIG_REG_LLH0_BRB1_NOT_MCP), 0x0);
11344
11345         /* Configure AEU */
11346         REG_WR(sc, MISC_REG_AEU_MASK_ATTN_FUNC_0 + port * 4, 0);
11347
11348         DELAY(100000);
11349
11350         /* Check for BRB port occupancy */
11351         val = REG_RD(sc, BRB1_REG_PORT_NUM_OCC_BLOCKS_0 + port * 4);
11352         if (val) {
11353                 PMD_DRV_LOG(DEBUG,
11354                             "BRB1 is not empty, %d blocks are occupied", val);
11355         }
11356 }
11357
11358 static void bnx2x_ilt_wr(struct bnx2x_softc *sc, uint32_t index, rte_iova_t addr)
11359 {
11360         int reg;
11361         uint32_t wb_write[2];
11362
11363         reg = PXP2_REG_RQ_ONCHIP_AT_B0 + index * 8;
11364
11365         wb_write[0] = ONCHIP_ADDR1(addr);
11366         wb_write[1] = ONCHIP_ADDR2(addr);
11367         REG_WR_DMAE(sc, reg, wb_write, 2);
11368 }
11369
11370 static void bnx2x_clear_func_ilt(struct bnx2x_softc *sc, uint32_t func)
11371 {
11372         uint32_t i, base = FUNC_ILT_BASE(func);
11373         for (i = base; i < base + ILT_PER_FUNC; i++) {
11374                 bnx2x_ilt_wr(sc, i, 0);
11375         }
11376 }
11377
11378 static void bnx2x_reset_func(struct bnx2x_softc *sc)
11379 {
11380         struct bnx2x_fastpath *fp;
11381         int port = SC_PORT(sc);
11382         int func = SC_FUNC(sc);
11383         int i;
11384
11385         /* Disable the function in the FW */
11386         REG_WR8(sc, BAR_XSTRORM_INTMEM + XSTORM_FUNC_EN_OFFSET(func), 0);
11387         REG_WR8(sc, BAR_CSTRORM_INTMEM + CSTORM_FUNC_EN_OFFSET(func), 0);
11388         REG_WR8(sc, BAR_TSTRORM_INTMEM + TSTORM_FUNC_EN_OFFSET(func), 0);
11389         REG_WR8(sc, BAR_USTRORM_INTMEM + USTORM_FUNC_EN_OFFSET(func), 0);
11390
11391         /* FP SBs */
11392         FOR_EACH_ETH_QUEUE(sc, i) {
11393                 fp = &sc->fp[i];
11394                 REG_WR8(sc, BAR_CSTRORM_INTMEM +
11395                         CSTORM_STATUS_BLOCK_DATA_STATE_OFFSET(fp->fw_sb_id),
11396                         SB_DISABLED);
11397         }
11398
11399         /* SP SB */
11400         REG_WR8(sc, BAR_CSTRORM_INTMEM +
11401                 CSTORM_SP_STATUS_BLOCK_DATA_STATE_OFFSET(func), SB_DISABLED);
11402
11403         for (i = 0; i < XSTORM_SPQ_DATA_SIZE / 4; i++) {
11404                 REG_WR(sc, BAR_XSTRORM_INTMEM + XSTORM_SPQ_DATA_OFFSET(func),
11405                        0);
11406         }
11407
11408         /* Configure IGU */
11409         if (sc->devinfo.int_block == INT_BLOCK_HC) {
11410                 REG_WR(sc, HC_REG_LEADING_EDGE_0 + port * 8, 0);
11411                 REG_WR(sc, HC_REG_TRAILING_EDGE_0 + port * 8, 0);
11412         } else {
11413                 REG_WR(sc, IGU_REG_LEADING_EDGE_LATCH, 0);
11414                 REG_WR(sc, IGU_REG_TRAILING_EDGE_LATCH, 0);
11415         }
11416
11417         if (CNIC_LOADED(sc)) {
11418 /* Disable Timer scan */
11419                 REG_WR(sc, TM_REG_EN_LINEAR0_TIMER + port * 4, 0);
11420 /*
11421  * Wait for at least 10ms and up to 2 second for the timers
11422  * scan to complete
11423  */
11424                 for (i = 0; i < 200; i++) {
11425                         DELAY(10000);
11426                         if (!REG_RD(sc, TM_REG_LIN0_SCAN_ON + port * 4))
11427                                 break;
11428                 }
11429         }
11430
11431         /* Clear ILT */
11432         bnx2x_clear_func_ilt(sc, func);
11433
11434         /*
11435          * Timers workaround bug for E2: if this is vnic-3,
11436          * we need to set the entire ilt range for this timers.
11437          */
11438         if (!CHIP_IS_E1x(sc) && SC_VN(sc) == 3) {
11439                 struct ilt_client_info ilt_cli;
11440 /* use dummy TM client */
11441                 memset(&ilt_cli, 0, sizeof(struct ilt_client_info));
11442                 ilt_cli.start = 0;
11443                 ilt_cli.end = ILT_NUM_PAGE_ENTRIES - 1;
11444                 ilt_cli.client_num = ILT_CLIENT_TM;
11445
11446                 ecore_ilt_boundry_init_op(sc, &ilt_cli, 0);
11447         }
11448
11449         /* this assumes that reset_port() called before reset_func() */
11450         if (!CHIP_IS_E1x(sc)) {
11451                 bnx2x_pf_disable(sc);
11452         }
11453
11454         sc->dmae_ready = 0;
11455 }
11456
11457 static void bnx2x_release_firmware(struct bnx2x_softc *sc)
11458 {
11459         rte_free(sc->init_ops);
11460         rte_free(sc->init_ops_offsets);
11461         rte_free(sc->init_data);
11462         rte_free(sc->iro_array);
11463 }
11464
11465 static int bnx2x_init_firmware(struct bnx2x_softc *sc)
11466 {
11467         uint32_t len, i;
11468         uint8_t *p = sc->firmware;
11469         uint32_t off[24];
11470
11471         for (i = 0; i < 24; ++i)
11472                 off[i] = rte_be_to_cpu_32(*((uint32_t *) sc->firmware + i));
11473
11474         len = off[0];
11475         sc->init_ops = rte_zmalloc("", len, RTE_CACHE_LINE_SIZE);
11476         if (!sc->init_ops)
11477                 goto alloc_failed;
11478         bnx2x_data_to_init_ops(p + off[1], sc->init_ops, len);
11479
11480         len = off[2];
11481         sc->init_ops_offsets = rte_zmalloc("", len, RTE_CACHE_LINE_SIZE);
11482         if (!sc->init_ops_offsets)
11483                 goto alloc_failed;
11484         bnx2x_data_to_init_offsets(p + off[3], sc->init_ops_offsets, len);
11485
11486         len = off[4];
11487         sc->init_data = rte_zmalloc("", len, RTE_CACHE_LINE_SIZE);
11488         if (!sc->init_data)
11489                 goto alloc_failed;
11490         bnx2x_data_to_init_data(p + off[5], sc->init_data, len);
11491
11492         sc->tsem_int_table_data = p + off[7];
11493         sc->tsem_pram_data = p + off[9];
11494         sc->usem_int_table_data = p + off[11];
11495         sc->usem_pram_data = p + off[13];
11496         sc->csem_int_table_data = p + off[15];
11497         sc->csem_pram_data = p + off[17];
11498         sc->xsem_int_table_data = p + off[19];
11499         sc->xsem_pram_data = p + off[21];
11500
11501         len = off[22];
11502         sc->iro_array = rte_zmalloc("", len, RTE_CACHE_LINE_SIZE);
11503         if (!sc->iro_array)
11504                 goto alloc_failed;
11505         bnx2x_data_to_iro_array(p + off[23], sc->iro_array, len);
11506
11507         return 0;
11508
11509 alloc_failed:
11510         bnx2x_release_firmware(sc);
11511         return -1;
11512 }
11513
11514 static int cut_gzip_prefix(const uint8_t * zbuf, int len)
11515 {
11516 #define MIN_PREFIX_SIZE (10)
11517
11518         int n = MIN_PREFIX_SIZE;
11519         uint16_t xlen;
11520
11521         if (!(zbuf[0] == 0x1f && zbuf[1] == 0x8b && zbuf[2] == Z_DEFLATED) ||
11522             len <= MIN_PREFIX_SIZE) {
11523                 return -1;
11524         }
11525
11526         /* optional extra fields are present */
11527         if (zbuf[3] & 0x4) {
11528                 xlen = zbuf[13];
11529                 xlen <<= 8;
11530                 xlen += zbuf[12];
11531
11532                 n += xlen;
11533         }
11534         /* file name is present */
11535         if (zbuf[3] & 0x8) {
11536                 while ((zbuf[n++] != 0) && (n < len)) ;
11537         }
11538
11539         return n;
11540 }
11541
11542 static int ecore_gunzip(struct bnx2x_softc *sc, const uint8_t * zbuf, int len)
11543 {
11544         int ret;
11545         int data_begin = cut_gzip_prefix(zbuf, len);
11546
11547         PMD_DRV_LOG(DEBUG, "ecore_gunzip %d", len);
11548
11549         if (data_begin <= 0) {
11550                 PMD_DRV_LOG(NOTICE, "bad gzip prefix");
11551                 return -1;
11552         }
11553
11554         memset(&zlib_stream, 0, sizeof(zlib_stream));
11555         zlib_stream.next_in = zbuf + data_begin;
11556         zlib_stream.avail_in = len - data_begin;
11557         zlib_stream.next_out = sc->gz_buf;
11558         zlib_stream.avail_out = FW_BUF_SIZE;
11559
11560         ret = inflateInit2(&zlib_stream, -MAX_WBITS);
11561         if (ret != Z_OK) {
11562                 PMD_DRV_LOG(NOTICE, "zlib inflateInit2 error");
11563                 return ret;
11564         }
11565
11566         ret = inflate(&zlib_stream, Z_FINISH);
11567         if ((ret != Z_STREAM_END) && (ret != Z_OK)) {
11568                 PMD_DRV_LOG(NOTICE, "zlib inflate error: %d %s", ret,
11569                             zlib_stream.msg);
11570         }
11571
11572         sc->gz_outlen = zlib_stream.total_out;
11573         if (sc->gz_outlen & 0x3) {
11574                 PMD_DRV_LOG(NOTICE, "firmware is not aligned. gz_outlen == %d",
11575                             sc->gz_outlen);
11576         }
11577         sc->gz_outlen >>= 2;
11578
11579         inflateEnd(&zlib_stream);
11580
11581         if (ret == Z_STREAM_END)
11582                 return 0;
11583
11584         return ret;
11585 }
11586
11587 static void
11588 ecore_write_dmae_phys_len(struct bnx2x_softc *sc, rte_iova_t phys_addr,
11589                           uint32_t addr, uint32_t len)
11590 {
11591         bnx2x_write_dmae_phys_len(sc, phys_addr, addr, len);
11592 }
11593
11594 void
11595 ecore_storm_memset_struct(struct bnx2x_softc *sc, uint32_t addr, size_t size,
11596                           uint32_t * data)
11597 {
11598         uint8_t i;
11599         for (i = 0; i < size / 4; i++) {
11600                 REG_WR(sc, addr + (i * 4), data[i]);
11601         }
11602 }
11603
11604 static const char *get_ext_phy_type(uint32_t ext_phy_type)
11605 {
11606         uint32_t phy_type_idx = ext_phy_type >> 8;
11607         static const char *types[] =
11608             { "DIRECT", "BNX2X-8071", "BNX2X-8072", "BNX2X-8073",
11609                 "BNX2X-8705", "BNX2X-8706", "BNX2X-8726", "BNX2X-8481", "SFX-7101",
11610                 "BNX2X-8727",
11611                 "BNX2X-8727-NOC", "BNX2X-84823", "NOT_CONN", "FAILURE"
11612         };
11613
11614         if (phy_type_idx < 12)
11615                 return types[phy_type_idx];
11616         else if (PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN == ext_phy_type)
11617                 return types[12];
11618         else
11619                 return types[13];
11620 }
11621
11622 static const char *get_state(uint32_t state)
11623 {
11624         uint32_t state_idx = state >> 12;
11625         static const char *states[] = { "CLOSED", "OPENING_WAIT4_LOAD",
11626                 "OPENING_WAIT4_PORT", "OPEN", "CLOSING_WAIT4_HALT",
11627                 "CLOSING_WAIT4_DELETE", "CLOSING_WAIT4_UNLOAD",
11628                 "UNKNOWN", "UNKNOWN", "UNKNOWN", "UNKNOWN", "UNKNOWN",
11629                 "UNKNOWN", "DISABLED", "DIAG", "ERROR", "UNDEFINED"
11630         };
11631
11632         if (state_idx <= 0xF)
11633                 return states[state_idx];
11634         else
11635                 return states[0x10];
11636 }
11637
11638 static const char *get_recovery_state(uint32_t state)
11639 {
11640         static const char *states[] = { "NONE", "DONE", "INIT",
11641                 "WAIT", "FAILED", "NIC_LOADING"
11642         };
11643         return states[state];
11644 }
11645
11646 static const char *get_rx_mode(uint32_t mode)
11647 {
11648         static const char *modes[] = { "NONE", "NORMAL", "ALLMULTI",
11649                 "PROMISC", "MAX_MULTICAST", "ERROR"
11650         };
11651
11652         if (mode < 0x4)
11653                 return modes[mode];
11654         else if (BNX2X_MAX_MULTICAST == mode)
11655                 return modes[4];
11656         else
11657                 return modes[5];
11658 }
11659
11660 #define BNX2X_INFO_STR_MAX 256
11661 static const char *get_bnx2x_flags(uint32_t flags)
11662 {
11663         int i;
11664         static const char *flag[] = { "ONE_PORT ", "NO_ISCSI ",
11665                 "NO_FCOE ", "NO_WOL ", "USING_DAC ", "USING_MSIX ",
11666                 "USING_MSI ", "DISABLE_MSI ", "UNKNOWN ", "NO_MCP ",
11667                 "SAFC_TX_FLAG ", "MF_FUNC_DIS ", "TX_SWITCHING "
11668         };
11669         static char flag_str[BNX2X_INFO_STR_MAX];
11670         memset(flag_str, 0, BNX2X_INFO_STR_MAX);
11671
11672         for (i = 0; i < 5; i++)
11673                 if (flags & (1 << i)) {
11674                         strcat(flag_str, flag[i]);
11675                         flags ^= (1 << i);
11676                 }
11677         if (flags) {
11678                 static char unknown[BNX2X_INFO_STR_MAX];
11679                 snprintf(unknown, 32, "Unknown flag mask %x", flags);
11680                 strcat(flag_str, unknown);
11681         }
11682         return flag_str;
11683 }
11684
11685 /*
11686  * Prints useful adapter info.
11687  */
11688 void bnx2x_print_adapter_info(struct bnx2x_softc *sc)
11689 {
11690         int i = 0;
11691         __rte_unused uint32_t ext_phy_type;
11692
11693         PMD_INIT_FUNC_TRACE();
11694         if (sc->link_vars.phy_flags & PHY_XGXS_FLAG)
11695                 ext_phy_type = ELINK_XGXS_EXT_PHY_TYPE(REG_RD(sc,
11696                                                               sc->
11697                                                               devinfo.shmem_base
11698                                                               + offsetof(struct
11699                                                                          shmem_region,
11700                                                                          dev_info.port_hw_config
11701                                                                          [0].external_phy_config)));
11702         else
11703                 ext_phy_type = ELINK_SERDES_EXT_PHY_TYPE(REG_RD(sc,
11704                                                                 sc->
11705                                                                 devinfo.shmem_base
11706                                                                 +
11707                                                                 offsetof(struct
11708                                                                          shmem_region,
11709                                                                          dev_info.port_hw_config
11710                                                                          [0].external_phy_config)));
11711
11712         PMD_INIT_LOG(DEBUG, "\n\n===================================\n");
11713         /* Hardware chip info. */
11714         PMD_INIT_LOG(DEBUG, "%12s : %#08x", "ASIC", sc->devinfo.chip_id);
11715         PMD_INIT_LOG(DEBUG, "%12s : %c%d", "Rev", (CHIP_REV(sc) >> 12) + 'A',
11716                      (CHIP_METAL(sc) >> 4));
11717
11718         /* Bus info. */
11719         PMD_INIT_LOG(DEBUG, "%12s : %d, ", "Bus PCIe", sc->devinfo.pcie_link_width);
11720         switch (sc->devinfo.pcie_link_speed) {
11721         case 1:
11722                 PMD_INIT_LOG(DEBUG, "%23s", "2.5 Gbps");
11723                 break;
11724         case 2:
11725                 PMD_INIT_LOG(DEBUG, "%21s", "5 Gbps");
11726                 break;
11727         case 4:
11728                 PMD_INIT_LOG(DEBUG, "%21s", "8 Gbps");
11729                 break;
11730         default:
11731                 PMD_INIT_LOG(DEBUG, "%33s", "Unknown link speed");
11732         }
11733
11734         /* Device features. */
11735         PMD_INIT_LOG(DEBUG, "%12s : ", "Flags");
11736
11737         /* Miscellaneous flags. */
11738         if (sc->devinfo.pcie_cap_flags & BNX2X_MSI_CAPABLE_FLAG) {
11739                 PMD_INIT_LOG(DEBUG, "%18s", "MSI");
11740                 i++;
11741         }
11742
11743         if (sc->devinfo.pcie_cap_flags & BNX2X_MSIX_CAPABLE_FLAG) {
11744                 if (i > 0)
11745                         PMD_INIT_LOG(DEBUG, "|");
11746                 PMD_INIT_LOG(DEBUG, "%20s", "MSI-X");
11747                 i++;
11748         }
11749
11750         if (IS_PF(sc)) {
11751                 PMD_INIT_LOG(DEBUG, "%12s : ", "Queues");
11752                 switch (sc->sp->rss_rdata.rss_mode) {
11753                 case ETH_RSS_MODE_DISABLED:
11754                         PMD_INIT_LOG(DEBUG, "%19s", "None");
11755                         break;
11756                 case ETH_RSS_MODE_REGULAR:
11757                         PMD_INIT_LOG(DEBUG, "%18s : %d", "RSS", sc->num_queues);
11758                         break;
11759                 default:
11760                         PMD_INIT_LOG(DEBUG, "%22s", "Unknown");
11761                         break;
11762                 }
11763         }
11764
11765         /* RTE and Driver versions */
11766         PMD_INIT_LOG(DEBUG, "%12s : %s", "DPDK",
11767                      rte_version());
11768         PMD_INIT_LOG(DEBUG, "%12s : %s", "Driver",
11769                      bnx2x_pmd_version());
11770
11771         /* Firmware versions and device features. */
11772         PMD_INIT_LOG(DEBUG, "%12s : %d.%d.%d",
11773                      "Firmware",
11774                      BNX2X_5710_FW_MAJOR_VERSION,
11775                      BNX2X_5710_FW_MINOR_VERSION,
11776                      BNX2X_5710_FW_REVISION_VERSION);
11777         PMD_INIT_LOG(DEBUG, "%12s : %s",
11778                      "Bootcode", sc->devinfo.bc_ver_str);
11779
11780         PMD_INIT_LOG(DEBUG, "\n\n===================================\n");
11781         PMD_INIT_LOG(DEBUG, "%12s : %u", "Bnx2x Func", sc->pcie_func);
11782         PMD_INIT_LOG(DEBUG, "%12s : %s", "Bnx2x Flags", get_bnx2x_flags(sc->flags));
11783         PMD_INIT_LOG(DEBUG, "%12s : %s", "DMAE Is",
11784                      (sc->dmae_ready ? "Ready" : "Not Ready"));
11785         PMD_INIT_LOG(DEBUG, "%12s : %s", "OVLAN", (OVLAN(sc) ? "YES" : "NO"));
11786         PMD_INIT_LOG(DEBUG, "%12s : %s", "MF", (IS_MF(sc) ? "YES" : "NO"));
11787         PMD_INIT_LOG(DEBUG, "%12s : %u", "MTU", sc->mtu);
11788         PMD_INIT_LOG(DEBUG, "%12s : %s", "PHY Type", get_ext_phy_type(ext_phy_type));
11789         PMD_INIT_LOG(DEBUG, "%12s : %x:%x:%x:%x:%x:%x", "MAC Addr",
11790                         sc->link_params.mac_addr[0],
11791                         sc->link_params.mac_addr[1],
11792                         sc->link_params.mac_addr[2],
11793                         sc->link_params.mac_addr[3],
11794                         sc->link_params.mac_addr[4],
11795                         sc->link_params.mac_addr[5]);
11796         PMD_INIT_LOG(DEBUG, "%12s : %s", "RX Mode", get_rx_mode(sc->rx_mode));
11797         PMD_INIT_LOG(DEBUG, "%12s : %s", "State", get_state(sc->state));
11798         if (sc->recovery_state)
11799                 PMD_INIT_LOG(DEBUG, "%12s : %s", "Recovery",
11800                              get_recovery_state(sc->recovery_state));
11801         PMD_INIT_LOG(DEBUG, "%12s : CQ = %lx,  EQ = %lx", "SPQ Left",
11802                      sc->cq_spq_left, sc->eq_spq_left);
11803         PMD_INIT_LOG(DEBUG, "%12s : %x", "Switch", sc->link_params.switch_cfg);
11804         PMD_INIT_LOG(DEBUG, "\n\n===================================\n");
11805 }