net/bnx2x: change copyright info to Cavium
[dpdk.git] / drivers / net / bnx2x / elink.c
1 /*
2  * Copyright (c) 2007-2013 Cavium Inc. All rights reserved.
3  *
4  * Eric Davis        <edavis@broadcom.com>
5  * David Christensen <davidch@broadcom.com>
6  * Gary Zambrano     <zambrano@broadcom.com>
7  *
8  * Copyright (c) 2013-2015 Brocade Communications Systems, Inc.
9  * Copyright (c) 2015-2018 Cavium Inc.
10  * All rights reserved.
11  * www.cavium.com
12  *
13  * See LICENSE.bnx2x_pmd for copyright and licensing details.
14  */
15
16 #include "bnx2x.h"
17 #include "elink.h"
18 #include "ecore_mfw_req.h"
19 #include "ecore_fw_defs.h"
20 #include "ecore_hsi.h"
21 #include "ecore_reg.h"
22
23 static elink_status_t elink_link_reset(struct elink_params *params,
24                                        struct elink_vars *vars,
25                                        uint8_t reset_ext_phy);
26 static elink_status_t elink_check_half_open_conn(struct elink_params *params,
27                                                  struct elink_vars *vars,
28                                                  uint8_t notify);
29 static elink_status_t elink_sfp_module_detection(struct elink_phy *phy,
30                                                  struct elink_params *params);
31
32 #define MDIO_REG_BANK_CL73_IEEEB0                       0x0
33 #define MDIO_CL73_IEEEB0_CL73_AN_CONTROL                0x0
34 #define MDIO_CL73_IEEEB0_CL73_AN_CONTROL_RESTART_AN     0x0200
35 #define MDIO_CL73_IEEEB0_CL73_AN_CONTROL_AN_EN          0x1000
36 #define MDIO_CL73_IEEEB0_CL73_AN_CONTROL_MAIN_RST       0x8000
37
38 #define MDIO_REG_BANK_CL73_IEEEB1                       0x10
39 #define MDIO_CL73_IEEEB1_AN_ADV1                        0x00
40 #define MDIO_CL73_IEEEB1_AN_ADV1_PAUSE                  0x0400
41 #define MDIO_CL73_IEEEB1_AN_ADV1_ASYMMETRIC             0x0800
42 #define MDIO_CL73_IEEEB1_AN_ADV1_PAUSE_BOTH             0x0C00
43 #define MDIO_CL73_IEEEB1_AN_ADV1_PAUSE_MASK             0x0C00
44 #define MDIO_CL73_IEEEB1_AN_ADV2                                0x01
45 #define MDIO_CL73_IEEEB1_AN_ADV2_ADVR_1000M             0x0000
46 #define MDIO_CL73_IEEEB1_AN_ADV2_ADVR_1000M_KX          0x0020
47 #define MDIO_CL73_IEEEB1_AN_ADV2_ADVR_10G_KX4           0x0040
48 #define MDIO_CL73_IEEEB1_AN_ADV2_ADVR_10G_KR            0x0080
49 #define MDIO_CL73_IEEEB1_AN_LP_ADV1                     0x03
50 #define MDIO_CL73_IEEEB1_AN_LP_ADV1_PAUSE               0x0400
51 #define MDIO_CL73_IEEEB1_AN_LP_ADV1_ASYMMETRIC          0x0800
52 #define MDIO_CL73_IEEEB1_AN_LP_ADV1_PAUSE_BOTH          0x0C00
53 #define MDIO_CL73_IEEEB1_AN_LP_ADV1_PAUSE_MASK          0x0C00
54 #define MDIO_CL73_IEEEB1_AN_LP_ADV2                     0x04
55
56 #define MDIO_REG_BANK_RX0                               0x80b0
57 #define MDIO_RX0_RX_STATUS                              0x10
58 #define MDIO_RX0_RX_STATUS_SIGDET                       0x8000
59 #define MDIO_RX0_RX_STATUS_RX_SEQ_DONE                  0x1000
60 #define MDIO_RX0_RX_EQ_BOOST                            0x1c
61 #define MDIO_RX0_RX_EQ_BOOST_EQUALIZER_CTRL_MASK        0x7
62 #define MDIO_RX0_RX_EQ_BOOST_OFFSET_CTRL                0x10
63
64 #define MDIO_REG_BANK_RX1                               0x80c0
65 #define MDIO_RX1_RX_EQ_BOOST                            0x1c
66 #define MDIO_RX1_RX_EQ_BOOST_EQUALIZER_CTRL_MASK        0x7
67 #define MDIO_RX1_RX_EQ_BOOST_OFFSET_CTRL                0x10
68
69 #define MDIO_REG_BANK_RX2                               0x80d0
70 #define MDIO_RX2_RX_EQ_BOOST                            0x1c
71 #define MDIO_RX2_RX_EQ_BOOST_EQUALIZER_CTRL_MASK        0x7
72 #define MDIO_RX2_RX_EQ_BOOST_OFFSET_CTRL                0x10
73
74 #define MDIO_REG_BANK_RX3                               0x80e0
75 #define MDIO_RX3_RX_EQ_BOOST                            0x1c
76 #define MDIO_RX3_RX_EQ_BOOST_EQUALIZER_CTRL_MASK        0x7
77 #define MDIO_RX3_RX_EQ_BOOST_OFFSET_CTRL                0x10
78
79 #define MDIO_REG_BANK_RX_ALL                            0x80f0
80 #define MDIO_RX_ALL_RX_EQ_BOOST                         0x1c
81 #define MDIO_RX_ALL_RX_EQ_BOOST_EQUALIZER_CTRL_MASK     0x7
82 #define MDIO_RX_ALL_RX_EQ_BOOST_OFFSET_CTRL     0x10
83
84 #define MDIO_REG_BANK_TX0                               0x8060
85 #define MDIO_TX0_TX_DRIVER                              0x17
86 #define MDIO_TX0_TX_DRIVER_PREEMPHASIS_MASK             0xf000
87 #define MDIO_TX0_TX_DRIVER_PREEMPHASIS_SHIFT            12
88 #define MDIO_TX0_TX_DRIVER_IDRIVER_MASK                 0x0f00
89 #define MDIO_TX0_TX_DRIVER_IDRIVER_SHIFT                8
90 #define MDIO_TX0_TX_DRIVER_IPREDRIVER_MASK              0x00f0
91 #define MDIO_TX0_TX_DRIVER_IPREDRIVER_SHIFT             4
92 #define MDIO_TX0_TX_DRIVER_IFULLSPD_MASK                0x000e
93 #define MDIO_TX0_TX_DRIVER_IFULLSPD_SHIFT               1
94 #define MDIO_TX0_TX_DRIVER_ICBUF1T                      1
95
96 #define MDIO_REG_BANK_TX1                               0x8070
97 #define MDIO_TX1_TX_DRIVER                              0x17
98 #define MDIO_TX0_TX_DRIVER_PREEMPHASIS_MASK             0xf000
99 #define MDIO_TX0_TX_DRIVER_PREEMPHASIS_SHIFT            12
100 #define MDIO_TX0_TX_DRIVER_IDRIVER_MASK                 0x0f00
101 #define MDIO_TX0_TX_DRIVER_IDRIVER_SHIFT                8
102 #define MDIO_TX0_TX_DRIVER_IPREDRIVER_MASK              0x00f0
103 #define MDIO_TX0_TX_DRIVER_IPREDRIVER_SHIFT             4
104 #define MDIO_TX0_TX_DRIVER_IFULLSPD_MASK                0x000e
105 #define MDIO_TX0_TX_DRIVER_IFULLSPD_SHIFT               1
106 #define MDIO_TX0_TX_DRIVER_ICBUF1T                      1
107
108 #define MDIO_REG_BANK_TX2                               0x8080
109 #define MDIO_TX2_TX_DRIVER                              0x17
110 #define MDIO_TX0_TX_DRIVER_PREEMPHASIS_MASK             0xf000
111 #define MDIO_TX0_TX_DRIVER_PREEMPHASIS_SHIFT            12
112 #define MDIO_TX0_TX_DRIVER_IDRIVER_MASK                 0x0f00
113 #define MDIO_TX0_TX_DRIVER_IDRIVER_SHIFT                8
114 #define MDIO_TX0_TX_DRIVER_IPREDRIVER_MASK              0x00f0
115 #define MDIO_TX0_TX_DRIVER_IPREDRIVER_SHIFT             4
116 #define MDIO_TX0_TX_DRIVER_IFULLSPD_MASK                0x000e
117 #define MDIO_TX0_TX_DRIVER_IFULLSPD_SHIFT               1
118 #define MDIO_TX0_TX_DRIVER_ICBUF1T                      1
119
120 #define MDIO_REG_BANK_TX3                               0x8090
121 #define MDIO_TX3_TX_DRIVER                              0x17
122 #define MDIO_TX0_TX_DRIVER_PREEMPHASIS_MASK             0xf000
123 #define MDIO_TX0_TX_DRIVER_PREEMPHASIS_SHIFT            12
124 #define MDIO_TX0_TX_DRIVER_IDRIVER_MASK                 0x0f00
125 #define MDIO_TX0_TX_DRIVER_IDRIVER_SHIFT                8
126 #define MDIO_TX0_TX_DRIVER_IPREDRIVER_MASK              0x00f0
127 #define MDIO_TX0_TX_DRIVER_IPREDRIVER_SHIFT             4
128 #define MDIO_TX0_TX_DRIVER_IFULLSPD_MASK                0x000e
129 #define MDIO_TX0_TX_DRIVER_IFULLSPD_SHIFT               1
130 #define MDIO_TX0_TX_DRIVER_ICBUF1T                      1
131
132 #define MDIO_REG_BANK_XGXS_BLOCK0                       0x8000
133 #define MDIO_BLOCK0_XGXS_CONTROL                        0x10
134
135 #define MDIO_REG_BANK_XGXS_BLOCK1                       0x8010
136 #define MDIO_BLOCK1_LANE_CTRL0                          0x15
137 #define MDIO_BLOCK1_LANE_CTRL1                          0x16
138 #define MDIO_BLOCK1_LANE_CTRL2                          0x17
139 #define MDIO_BLOCK1_LANE_PRBS                           0x19
140
141 #define MDIO_REG_BANK_XGXS_BLOCK2                       0x8100
142 #define MDIO_XGXS_BLOCK2_RX_LN_SWAP                     0x10
143 #define MDIO_XGXS_BLOCK2_RX_LN_SWAP_ENABLE              0x8000
144 #define MDIO_XGXS_BLOCK2_RX_LN_SWAP_FORCE_ENABLE        0x4000
145 #define MDIO_XGXS_BLOCK2_TX_LN_SWAP             0x11
146 #define MDIO_XGXS_BLOCK2_TX_LN_SWAP_ENABLE              0x8000
147 #define MDIO_XGXS_BLOCK2_UNICORE_MODE_10G       0x14
148 #define MDIO_XGXS_BLOCK2_UNICORE_MODE_10G_CX4_XGXS      0x0001
149 #define MDIO_XGXS_BLOCK2_UNICORE_MODE_10G_HIGIG_XGXS    0x0010
150 #define MDIO_XGXS_BLOCK2_TEST_MODE_LANE         0x15
151
152 #define MDIO_REG_BANK_GP_STATUS                         0x8120
153 #define MDIO_GP_STATUS_TOP_AN_STATUS1                           0x1B
154 #define MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_AUTONEG_COMPLETE     0x0001
155 #define MDIO_GP_STATUS_TOP_AN_STATUS1_CL37_AUTONEG_COMPLETE     0x0002
156 #define MDIO_GP_STATUS_TOP_AN_STATUS1_LINK_STATUS               0x0004
157 #define MDIO_GP_STATUS_TOP_AN_STATUS1_DUPLEX_STATUS             0x0008
158 #define MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_MR_LP_NP_AN_ABLE     0x0010
159 #define MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_LP_NP_BAM_ABLE       0x0020
160 #define MDIO_GP_STATUS_TOP_AN_STATUS1_PAUSE_RSOLUTION_TXSIDE    0x0040
161 #define MDIO_GP_STATUS_TOP_AN_STATUS1_PAUSE_RSOLUTION_RXSIDE    0x0080
162 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_MASK         0x3f00
163 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10M          0x0000
164 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_100M         0x0100
165 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_1G           0x0200
166 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_2_5G         0x0300
167 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_5G           0x0400
168 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_6G           0x0500
169 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_HIG      0x0600
170 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_CX4      0x0700
171 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_12G_HIG      0x0800
172 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_12_5G        0x0900
173 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_13G          0x0A00
174 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_15G          0x0B00
175 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_16G          0x0C00
176 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_1G_KX        0x0D00
177 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_KX4      0x0E00
178 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_KR       0x0F00
179 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_XFI      0x1B00
180 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_20G_DXGXS    0x1E00
181 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_SFI      0x1F00
182 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_20G_KR2      0x3900
183
184 #define MDIO_REG_BANK_10G_PARALLEL_DETECT               0x8130
185 #define MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_STATUS             0x10
186 #define MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_STATUS_PD_LINK             0x8000
187 #define MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_CONTROL            0x11
188 #define MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_CONTROL_PARDET10G_EN       0x1
189 #define MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_LINK               0x13
190 #define MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_LINK_CNT           (0xb71<<1)
191
192 #define MDIO_REG_BANK_SERDES_DIGITAL                    0x8300
193 #define MDIO_SERDES_DIGITAL_A_1000X_CONTROL1                    0x10
194 #define MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_FIBER_MODE                 0x0001
195 #define MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_TBI_IF                     0x0002
196 #define MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_SIGNAL_DETECT_EN           0x0004
197 #define MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_INVERT_SIGNAL_DETECT       0x0008
198 #define MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_AUTODET                    0x0010
199 #define MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_MSTR_MODE                  0x0020
200 #define MDIO_SERDES_DIGITAL_A_1000X_CONTROL2                    0x11
201 #define MDIO_SERDES_DIGITAL_A_1000X_CONTROL2_PRL_DT_EN                  0x0001
202 #define MDIO_SERDES_DIGITAL_A_1000X_CONTROL2_AN_FST_TMR                 0x0040
203 #define MDIO_SERDES_DIGITAL_A_1000X_STATUS1                     0x14
204 #define MDIO_SERDES_DIGITAL_A_1000X_STATUS1_SGMII                       0x0001
205 #define MDIO_SERDES_DIGITAL_A_1000X_STATUS1_LINK                        0x0002
206 #define MDIO_SERDES_DIGITAL_A_1000X_STATUS1_DUPLEX                      0x0004
207 #define MDIO_SERDES_DIGITAL_A_1000X_STATUS1_SPEED_MASK                  0x0018
208 #define MDIO_SERDES_DIGITAL_A_1000X_STATUS1_SPEED_SHIFT                 3
209 #define MDIO_SERDES_DIGITAL_A_1000X_STATUS1_SPEED_2_5G                  0x0018
210 #define MDIO_SERDES_DIGITAL_A_1000X_STATUS1_SPEED_1G                    0x0010
211 #define MDIO_SERDES_DIGITAL_A_1000X_STATUS1_SPEED_100M                  0x0008
212 #define MDIO_SERDES_DIGITAL_A_1000X_STATUS1_SPEED_10M                   0x0000
213 #define MDIO_SERDES_DIGITAL_A_1000X_STATUS2                     0x15
214 #define MDIO_SERDES_DIGITAL_A_1000X_STATUS2_AN_DISABLED                 0x0002
215 #define MDIO_SERDES_DIGITAL_MISC1                               0x18
216 #define MDIO_SERDES_DIGITAL_MISC1_REFCLK_SEL_MASK                       0xE000
217 #define MDIO_SERDES_DIGITAL_MISC1_REFCLK_SEL_25M                        0x0000
218 #define MDIO_SERDES_DIGITAL_MISC1_REFCLK_SEL_100M                       0x2000
219 #define MDIO_SERDES_DIGITAL_MISC1_REFCLK_SEL_125M                       0x4000
220 #define MDIO_SERDES_DIGITAL_MISC1_REFCLK_SEL_156_25M                    0x6000
221 #define MDIO_SERDES_DIGITAL_MISC1_REFCLK_SEL_187_5M                     0x8000
222 #define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_SEL                       0x0010
223 #define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_MASK                      0x000f
224 #define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_2_5G                      0x0000
225 #define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_5G                        0x0001
226 #define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_6G                        0x0002
227 #define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_10G_HIG                   0x0003
228 #define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_10G_CX4                   0x0004
229 #define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_12G                       0x0005
230 #define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_12_5G                     0x0006
231 #define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_13G                       0x0007
232 #define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_15G                       0x0008
233 #define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_16G                       0x0009
234
235 #define MDIO_REG_BANK_OVER_1G                           0x8320
236 #define MDIO_OVER_1G_DIGCTL_3_4                                 0x14
237 #define MDIO_OVER_1G_DIGCTL_3_4_MP_ID_MASK                              0xffe0
238 #define MDIO_OVER_1G_DIGCTL_3_4_MP_ID_SHIFT                             5
239 #define MDIO_OVER_1G_UP1                                        0x19
240 #define MDIO_OVER_1G_UP1_2_5G                                           0x0001
241 #define MDIO_OVER_1G_UP1_5G                                             0x0002
242 #define MDIO_OVER_1G_UP1_6G                                             0x0004
243 #define MDIO_OVER_1G_UP1_10G                                            0x0010
244 #define MDIO_OVER_1G_UP1_10GH                                           0x0008
245 #define MDIO_OVER_1G_UP1_12G                                            0x0020
246 #define MDIO_OVER_1G_UP1_12_5G                                          0x0040
247 #define MDIO_OVER_1G_UP1_13G                                            0x0080
248 #define MDIO_OVER_1G_UP1_15G                                            0x0100
249 #define MDIO_OVER_1G_UP1_16G                                            0x0200
250 #define MDIO_OVER_1G_UP2                                        0x1A
251 #define MDIO_OVER_1G_UP2_IPREDRIVER_MASK                                0x0007
252 #define MDIO_OVER_1G_UP2_IDRIVER_MASK                                   0x0038
253 #define MDIO_OVER_1G_UP2_PREEMPHASIS_MASK                               0x03C0
254 #define MDIO_OVER_1G_UP3                                        0x1B
255 #define MDIO_OVER_1G_UP3_HIGIG2                                         0x0001
256 #define MDIO_OVER_1G_LP_UP1                                     0x1C
257 #define MDIO_OVER_1G_LP_UP2                                     0x1D
258 #define MDIO_OVER_1G_LP_UP2_MR_ADV_OVER_1G_MASK                         0x03ff
259 #define MDIO_OVER_1G_LP_UP2_PREEMPHASIS_MASK                            0x0780
260 #define MDIO_OVER_1G_LP_UP2_PREEMPHASIS_SHIFT                           7
261 #define MDIO_OVER_1G_LP_UP3                                             0x1E
262
263 #define MDIO_REG_BANK_REMOTE_PHY                        0x8330
264 #define MDIO_REMOTE_PHY_MISC_RX_STATUS                          0x10
265 #define MDIO_REMOTE_PHY_MISC_RX_STATUS_CL37_FSM_RECEIVED_OVER1G_MSG     0x0010
266 #define MDIO_REMOTE_PHY_MISC_RX_STATUS_CL37_FSM_RECEIVED_BRCM_OUI_MSG   0x0600
267
268 #define MDIO_REG_BANK_BAM_NEXT_PAGE                     0x8350
269 #define MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL                   0x10
270 #define MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_BAM_MODE                  0x0001
271 #define MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_TETON_AN                  0x0002
272
273 #define MDIO_REG_BANK_CL73_USERB0               0x8370
274 #define MDIO_CL73_USERB0_CL73_UCTRL                             0x10
275 #define MDIO_CL73_USERB0_CL73_UCTRL_USTAT1_MUXSEL                       0x0002
276 #define MDIO_CL73_USERB0_CL73_USTAT1                            0x11
277 #define MDIO_CL73_USERB0_CL73_USTAT1_LINK_STATUS_CHECK                  0x0100
278 #define MDIO_CL73_USERB0_CL73_USTAT1_AN_GOOD_CHECK_BAM37                0x0400
279 #define MDIO_CL73_USERB0_CL73_BAM_CTRL1                         0x12
280 #define MDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_EN                          0x8000
281 #define MDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_STATION_MNGR_EN             0x4000
282 #define MDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_NP_AFTER_BP_EN              0x2000
283 #define MDIO_CL73_USERB0_CL73_BAM_CTRL3                         0x14
284 #define MDIO_CL73_USERB0_CL73_BAM_CTRL3_USE_CL73_HCD_MR                 0x0001
285
286 #define MDIO_REG_BANK_AER_BLOCK                 0xFFD0
287 #define MDIO_AER_BLOCK_AER_REG                                  0x1E
288
289 #define MDIO_REG_BANK_COMBO_IEEE0               0xFFE0
290 #define MDIO_COMBO_IEEE0_MII_CONTROL                            0x10
291 #define MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_MASK                   0x2040
292 #define MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_10                     0x0000
293 #define MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_100                    0x2000
294 #define MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_1000                   0x0040
295 #define MDIO_COMBO_IEEO_MII_CONTROL_FULL_DUPLEX                         0x0100
296 #define MDIO_COMBO_IEEO_MII_CONTROL_RESTART_AN                          0x0200
297 #define MDIO_COMBO_IEEO_MII_CONTROL_AN_EN                               0x1000
298 #define MDIO_COMBO_IEEO_MII_CONTROL_LOOPBACK                            0x4000
299 #define MDIO_COMBO_IEEO_MII_CONTROL_RESET                               0x8000
300 #define MDIO_COMBO_IEEE0_MII_STATUS                             0x11
301 #define MDIO_COMBO_IEEE0_MII_STATUS_LINK_PASS                           0x0004
302 #define MDIO_COMBO_IEEE0_MII_STATUS_AUTONEG_COMPLETE                    0x0020
303 #define MDIO_COMBO_IEEE0_AUTO_NEG_ADV                           0x14
304 #define MDIO_COMBO_IEEE0_AUTO_NEG_ADV_FULL_DUPLEX                       0x0020
305 #define MDIO_COMBO_IEEE0_AUTO_NEG_ADV_HALF_DUPLEX                       0x0040
306 #define MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_MASK                        0x0180
307 #define MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_NONE                        0x0000
308 #define MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_SYMMETRIC                   0x0080
309 #define MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC                  0x0100
310 #define MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH                        0x0180
311 #define MDIO_COMBO_IEEE0_AUTO_NEG_ADV_NEXT_PAGE                         0x8000
312 #define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1         0x15
313 #define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1_NEXT_PAGE       0x8000
314 #define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1_ACK             0x4000
315 #define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1_PAUSE_MASK      0x0180
316 #define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1_PAUSE_NONE      0x0000
317 #define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1_PAUSE_BOTH      0x0180
318 #define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1_HALF_DUP_CAP    0x0040
319 #define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1_FULL_DUP_CAP    0x0020
320 /*WhenthelinkpartnerisinSGMIImode(bit0=1),then
321 bit15=link,bit12=duplex,bits11:10=speed,bit14=acknowledge.
322 Theotherbitsarereservedandshouldbezero*/
323 #define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1_SGMII_MODE      0x0001
324
325 #define MDIO_PMA_DEVAD                  0x1
326 /*ieee*/
327 #define MDIO_PMA_REG_CTRL               0x0
328 #define MDIO_PMA_REG_STATUS             0x1
329 #define MDIO_PMA_REG_10G_CTRL2          0x7
330 #define MDIO_PMA_REG_TX_DISABLE         0x0009
331 #define MDIO_PMA_REG_RX_SD              0xa
332 /*bnx2x*/
333 #define MDIO_PMA_REG_BNX2X_CTRL         0x0096
334 #define MDIO_PMA_REG_FEC_CTRL           0x00ab
335 #define MDIO_PMA_LASI_RXCTRL            0x9000
336 #define MDIO_PMA_LASI_TXCTRL            0x9001
337 #define MDIO_PMA_LASI_CTRL              0x9002
338 #define MDIO_PMA_LASI_RXSTAT            0x9003
339 #define MDIO_PMA_LASI_TXSTAT            0x9004
340 #define MDIO_PMA_LASI_STAT              0x9005
341 #define MDIO_PMA_REG_PHY_IDENTIFIER     0xc800
342 #define MDIO_PMA_REG_DIGITAL_CTRL       0xc808
343 #define MDIO_PMA_REG_DIGITAL_STATUS     0xc809
344 #define MDIO_PMA_REG_TX_POWER_DOWN      0xca02
345 #define MDIO_PMA_REG_CMU_PLL_BYPASS     0xca09
346 #define MDIO_PMA_REG_MISC_CTRL          0xca0a
347 #define MDIO_PMA_REG_GEN_CTRL           0xca10
348 #define MDIO_PMA_REG_GEN_CTRL_ROM_RESET_INTERNAL_MP     0x0188
349 #define MDIO_PMA_REG_GEN_CTRL_ROM_MICRO_RESET           0x018a
350 #define MDIO_PMA_REG_M8051_MSGIN_REG    0xca12
351 #define MDIO_PMA_REG_M8051_MSGOUT_REG   0xca13
352 #define MDIO_PMA_REG_ROM_VER1           0xca19
353 #define MDIO_PMA_REG_ROM_VER2           0xca1a
354 #define MDIO_PMA_REG_EDC_FFE_MAIN       0xca1b
355 #define MDIO_PMA_REG_PLL_BANDWIDTH      0xca1d
356 #define MDIO_PMA_REG_PLL_CTRL           0xca1e
357 #define MDIO_PMA_REG_MISC_CTRL0         0xca23
358 #define MDIO_PMA_REG_LRM_MODE           0xca3f
359 #define MDIO_PMA_REG_CDR_BANDWIDTH      0xca46
360 #define MDIO_PMA_REG_MISC_CTRL1         0xca85
361
362 #define MDIO_PMA_REG_SFP_TWO_WIRE_CTRL          0x8000
363 #define MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK      0x000c
364 #define MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_IDLE           0x0000
365 #define MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_COMPLETE       0x0004
366 #define MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_IN_PROGRESS    0x0008
367 #define MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_FAILED         0x000c
368 #define MDIO_PMA_REG_SFP_TWO_WIRE_BYTE_CNT      0x8002
369 #define MDIO_PMA_REG_SFP_TWO_WIRE_MEM_ADDR      0x8003
370 #define MDIO_PMA_REG_8726_TWO_WIRE_DATA_BUF     0xc820
371 #define MDIO_PMA_REG_8726_TWO_WIRE_DATA_MASK 0xff
372 #define MDIO_PMA_REG_8726_TX_CTRL1              0xca01
373 #define MDIO_PMA_REG_8726_TX_CTRL2              0xca05
374
375 #define MDIO_PMA_REG_8727_TWO_WIRE_SLAVE_ADDR   0x8005
376 #define MDIO_PMA_REG_8727_TWO_WIRE_DATA_BUF     0x8007
377 #define MDIO_PMA_REG_8727_TWO_WIRE_DATA_MASK 0xff
378 #define MDIO_PMA_REG_8727_MISC_CTRL             0x8309
379 #define MDIO_PMA_REG_8727_TX_CTRL1              0xca02
380 #define MDIO_PMA_REG_8727_TX_CTRL2              0xca05
381 #define MDIO_PMA_REG_8727_PCS_OPT_CTRL          0xc808
382 #define MDIO_PMA_REG_8727_GPIO_CTRL             0xc80e
383 #define MDIO_PMA_REG_8727_PCS_GP                0xc842
384 #define MDIO_PMA_REG_8727_OPT_CFG_REG           0xc8e4
385
386 #define MDIO_AN_REG_8727_MISC_CTRL              0x8309
387 #define MDIO_PMA_REG_8073_CHIP_REV                      0xc801
388 #define MDIO_PMA_REG_8073_SPEED_LINK_STATUS             0xc820
389 #define MDIO_PMA_REG_8073_XAUI_WA                       0xc841
390 #define MDIO_PMA_REG_8073_OPT_DIGITAL_CTRL              0xcd08
391
392 #define MDIO_PMA_REG_7101_RESET         0xc000
393 #define MDIO_PMA_REG_7107_LED_CNTL      0xc007
394 #define MDIO_PMA_REG_7107_LINK_LED_CNTL 0xc009
395 #define MDIO_PMA_REG_7101_VER1          0xc026
396 #define MDIO_PMA_REG_7101_VER2          0xc027
397
398 #define MDIO_PMA_REG_8481_PMD_SIGNAL    0xa811
399 #define MDIO_PMA_REG_8481_LED1_MASK     0xa82c
400 #define MDIO_PMA_REG_8481_LED2_MASK     0xa82f
401 #define MDIO_PMA_REG_8481_LED3_MASK     0xa832
402 #define MDIO_PMA_REG_8481_LED3_BLINK    0xa834
403 #define MDIO_PMA_REG_8481_LED5_MASK                     0xa838
404 #define MDIO_PMA_REG_8481_SIGNAL_MASK   0xa835
405 #define MDIO_PMA_REG_8481_LINK_SIGNAL   0xa83b
406 #define MDIO_PMA_REG_8481_LINK_SIGNAL_LED4_ENABLE_MASK  0x800
407 #define MDIO_PMA_REG_8481_LINK_SIGNAL_LED4_ENABLE_SHIFT 11
408
409 #define MDIO_WIS_DEVAD                  0x2
410 /*bnx2x*/
411 #define MDIO_WIS_REG_LASI_CNTL          0x9002
412 #define MDIO_WIS_REG_LASI_STATUS        0x9005
413
414 #define MDIO_PCS_DEVAD                  0x3
415 #define MDIO_PCS_REG_STATUS             0x0020
416 #define MDIO_PCS_REG_LASI_STATUS        0x9005
417 #define MDIO_PCS_REG_7101_DSP_ACCESS    0xD000
418 #define MDIO_PCS_REG_7101_SPI_MUX       0xD008
419 #define MDIO_PCS_REG_7101_SPI_CTRL_ADDR 0xE12A
420 #define MDIO_PCS_REG_7101_SPI_RESET_BIT (5)
421 #define MDIO_PCS_REG_7101_SPI_FIFO_ADDR 0xE02A
422 #define MDIO_PCS_REG_7101_SPI_FIFO_ADDR_WRITE_ENABLE_CMD (6)
423 #define MDIO_PCS_REG_7101_SPI_FIFO_ADDR_BULK_ERASE_CMD   (0xC7)
424 #define MDIO_PCS_REG_7101_SPI_FIFO_ADDR_PAGE_PROGRAM_CMD (2)
425 #define MDIO_PCS_REG_7101_SPI_BYTES_TO_TRANSFER_ADDR 0xE028
426
427 #define MDIO_XS_DEVAD                   0x4
428 #define MDIO_XS_REG_STATUS              0x0001
429 #define MDIO_XS_PLL_SEQUENCER           0x8000
430 #define MDIO_XS_SFX7101_XGXS_TEST1      0xc00a
431
432 #define MDIO_XS_8706_REG_BANK_RX0       0x80bc
433 #define MDIO_XS_8706_REG_BANK_RX1       0x80cc
434 #define MDIO_XS_8706_REG_BANK_RX2       0x80dc
435 #define MDIO_XS_8706_REG_BANK_RX3       0x80ec
436 #define MDIO_XS_8706_REG_BANK_RXA       0x80fc
437
438 #define MDIO_XS_REG_8073_RX_CTRL_PCIE   0x80FA
439
440 #define MDIO_AN_DEVAD                   0x7
441 /*ieee*/
442 #define MDIO_AN_REG_CTRL                0x0000
443 #define MDIO_AN_REG_STATUS              0x0001
444 #define MDIO_AN_REG_STATUS_AN_COMPLETE          0x0020
445 #define MDIO_AN_REG_ADV_PAUSE           0x0010
446 #define MDIO_AN_REG_ADV_PAUSE_PAUSE             0x0400
447 #define MDIO_AN_REG_ADV_PAUSE_ASYMMETRIC        0x0800
448 #define MDIO_AN_REG_ADV_PAUSE_BOTH              0x0C00
449 #define MDIO_AN_REG_ADV_PAUSE_MASK              0x0C00
450 #define MDIO_AN_REG_ADV                 0x0011
451 #define MDIO_AN_REG_ADV2                0x0012
452 #define MDIO_AN_REG_LP_AUTO_NEG         0x0013
453 #define MDIO_AN_REG_LP_AUTO_NEG2        0x0014
454 #define MDIO_AN_REG_MASTER_STATUS       0x0021
455 #define MDIO_AN_REG_EEE_ADV             0x003c
456 #define MDIO_AN_REG_LP_EEE_ADV          0x003d
457 /*bnx2x*/
458 #define MDIO_AN_REG_LINK_STATUS         0x8304
459 #define MDIO_AN_REG_CL37_CL73           0x8370
460 #define MDIO_AN_REG_CL37_AN             0xffe0
461 #define MDIO_AN_REG_CL37_FC_LD          0xffe4
462 #define         MDIO_AN_REG_CL37_FC_LP          0xffe5
463 #define         MDIO_AN_REG_1000T_STATUS        0xffea
464
465 #define MDIO_AN_REG_8073_2_5G           0x8329
466 #define MDIO_AN_REG_8073_BAM            0x8350
467
468 #define MDIO_AN_REG_8481_10GBASE_T_AN_CTRL      0x0020
469 #define MDIO_AN_REG_8481_LEGACY_MII_CTRL        0xffe0
470 #define MDIO_AN_REG_8481_MII_CTRL_FORCE_1G      0x40
471 #define MDIO_AN_REG_8481_LEGACY_MII_STATUS      0xffe1
472 #define MDIO_AN_REG_8481_LEGACY_AN_ADV          0xffe4
473 #define MDIO_AN_REG_8481_LEGACY_AN_EXPANSION    0xffe6
474 #define MDIO_AN_REG_8481_1000T_CTRL             0xffe9
475 #define MDIO_AN_REG_8481_1G_100T_EXT_CTRL       0xfff0
476 #define MIDO_AN_REG_8481_EXT_CTRL_FORCE_LEDS_OFF        0x0008
477 #define MDIO_AN_REG_8481_EXPANSION_REG_RD_RW    0xfff5
478 #define MDIO_AN_REG_8481_EXPANSION_REG_ACCESS   0xfff7
479 #define MDIO_AN_REG_8481_AUX_CTRL               0xfff8
480 #define MDIO_AN_REG_8481_LEGACY_SHADOW          0xfffc
481
482 /* BNX2X84823 only */
483 #define MDIO_CTL_DEVAD                  0x1e
484 #define MDIO_CTL_REG_84823_MEDIA                0x401a
485 #define MDIO_CTL_REG_84823_MEDIA_MAC_MASK               0x0018
486         /* These pins configure the BNX2X84823 interface to MAC after reset. */
487 #define MDIO_CTL_REG_84823_CTRL_MAC_XFI                 0x0008
488 #define MDIO_CTL_REG_84823_MEDIA_MAC_XAUI_M             0x0010
489         /* These pins configure the BNX2X84823 interface to Line after reset. */
490 #define MDIO_CTL_REG_84823_MEDIA_LINE_MASK              0x0060
491 #define MDIO_CTL_REG_84823_MEDIA_LINE_XAUI_L            0x0020
492 #define MDIO_CTL_REG_84823_MEDIA_LINE_XFI               0x0040
493         /* When this pin is active high during reset, 10GBASE-T core is power
494          * down, When it is active low the 10GBASE-T is power up
495          */
496 #define MDIO_CTL_REG_84823_MEDIA_COPPER_CORE_DOWN       0x0080
497 #define MDIO_CTL_REG_84823_MEDIA_PRIORITY_MASK          0x0100
498 #define MDIO_CTL_REG_84823_MEDIA_PRIORITY_COPPER        0x0000
499 #define MDIO_CTL_REG_84823_MEDIA_PRIORITY_FIBER         0x0100
500 #define MDIO_CTL_REG_84823_MEDIA_FIBER_1G                       0x1000
501 #define MDIO_CTL_REG_84823_USER_CTRL_REG                        0x4005
502 #define MDIO_CTL_REG_84823_USER_CTRL_CMS                        0x0080
503 #define MDIO_PMA_REG_84823_CTL_SLOW_CLK_CNT_HIGH                0xa82b
504 #define MDIO_PMA_REG_84823_BLINK_RATE_VAL_15P9HZ        0x2f
505 #define MDIO_PMA_REG_84823_CTL_LED_CTL_1                        0xa8e3
506 #define MDIO_PMA_REG_84833_CTL_LED_CTL_1                        0xa8ec
507 #define MDIO_PMA_REG_84823_LED3_STRETCH_EN                      0x0080
508
509 /* BNX2X84833 only */
510 #define MDIO_84833_TOP_CFG_FW_REV                       0x400f
511 #define MDIO_84833_TOP_CFG_FW_EEE               0x10b1
512 #define MDIO_84833_TOP_CFG_FW_NO_EEE            0x1f81
513 #define MDIO_84833_TOP_CFG_XGPHY_STRAP1                 0x401a
514 #define MDIO_84833_SUPER_ISOLATE                0x8000
515 /* These are mailbox register set used by 84833. */
516 #define MDIO_84833_TOP_CFG_SCRATCH_REG0                 0x4005
517 #define MDIO_84833_TOP_CFG_SCRATCH_REG1                 0x4006
518 #define MDIO_84833_TOP_CFG_SCRATCH_REG2                 0x4007
519 #define MDIO_84833_TOP_CFG_SCRATCH_REG3                 0x4008
520 #define MDIO_84833_TOP_CFG_SCRATCH_REG4                 0x4009
521 #define MDIO_84833_TOP_CFG_SCRATCH_REG26                0x4037
522 #define MDIO_84833_TOP_CFG_SCRATCH_REG27                0x4038
523 #define MDIO_84833_TOP_CFG_SCRATCH_REG28                0x4039
524 #define MDIO_84833_TOP_CFG_SCRATCH_REG29                0x403a
525 #define MDIO_84833_TOP_CFG_SCRATCH_REG30                0x403b
526 #define MDIO_84833_TOP_CFG_SCRATCH_REG31                0x403c
527 #define MDIO_84833_CMD_HDLR_COMMAND     MDIO_84833_TOP_CFG_SCRATCH_REG0
528 #define MDIO_84833_CMD_HDLR_STATUS      MDIO_84833_TOP_CFG_SCRATCH_REG26
529 #define MDIO_84833_CMD_HDLR_DATA1       MDIO_84833_TOP_CFG_SCRATCH_REG27
530 #define MDIO_84833_CMD_HDLR_DATA2       MDIO_84833_TOP_CFG_SCRATCH_REG28
531 #define MDIO_84833_CMD_HDLR_DATA3       MDIO_84833_TOP_CFG_SCRATCH_REG29
532 #define MDIO_84833_CMD_HDLR_DATA4       MDIO_84833_TOP_CFG_SCRATCH_REG30
533 #define MDIO_84833_CMD_HDLR_DATA5       MDIO_84833_TOP_CFG_SCRATCH_REG31
534
535 /* Mailbox command set used by 84833. */
536 #define PHY84833_CMD_SET_PAIR_SWAP                      0x8001
537 #define PHY84833_CMD_GET_EEE_MODE                       0x8008
538 #define PHY84833_CMD_SET_EEE_MODE                       0x8009
539 #define PHY84833_CMD_GET_CURRENT_TEMP                   0x8031
540 /* Mailbox status set used by 84833. */
541 #define PHY84833_STATUS_CMD_RECEIVED                    0x0001
542 #define PHY84833_STATUS_CMD_IN_PROGRESS                 0x0002
543 #define PHY84833_STATUS_CMD_COMPLETE_PASS               0x0004
544 #define PHY84833_STATUS_CMD_COMPLETE_ERROR              0x0008
545 #define PHY84833_STATUS_CMD_OPEN_FOR_CMDS               0x0010
546 #define PHY84833_STATUS_CMD_SYSTEM_BOOT                 0x0020
547 #define PHY84833_STATUS_CMD_NOT_OPEN_FOR_CMDS           0x0040
548 #define PHY84833_STATUS_CMD_CLEAR_COMPLETE              0x0080
549 #define PHY84833_STATUS_CMD_OPEN_OVERRIDE               0xa5a5
550
551 /* Warpcore clause 45 addressing */
552 #define MDIO_WC_DEVAD                                   0x3
553 #define MDIO_WC_REG_IEEE0BLK_MIICNTL                    0x0
554 #define MDIO_WC_REG_IEEE0BLK_AUTONEGNP                  0x7
555 #define MDIO_WC_REG_AN_IEEE1BLK_AN_ADVERTISEMENT0       0x10
556 #define MDIO_WC_REG_AN_IEEE1BLK_AN_ADVERTISEMENT1       0x11
557 #define MDIO_WC_REG_AN_IEEE1BLK_AN_ADVERTISEMENT2       0x12
558 #define MDIO_WC_REG_AN_IEEE1BLK_AN_ADV2_FEC_ABILITY     0x4000
559 #define MDIO_WC_REG_AN_IEEE1BLK_AN_ADV2_FEC_REQ         0x8000
560 #define MDIO_WC_REG_PCS_STATUS2                         0x0021
561 #define MDIO_WC_REG_PMD_KR_CONTROL                      0x0096
562 #define MDIO_WC_REG_XGXSBLK0_XGXSCONTROL                0x8000
563 #define MDIO_WC_REG_XGXSBLK0_MISCCONTROL1               0x800e
564 #define MDIO_WC_REG_XGXSBLK1_DESKEW                     0x8010
565 #define MDIO_WC_REG_XGXSBLK1_LANECTRL0                  0x8015
566 #define MDIO_WC_REG_XGXSBLK1_LANECTRL1                  0x8016
567 #define MDIO_WC_REG_XGXSBLK1_LANECTRL2                  0x8017
568 #define MDIO_WC_REG_XGXSBLK1_LANECTRL3                  0x8018
569 #define MDIO_WC_REG_XGXSBLK1_LANETEST0                  0x801a
570 #define MDIO_WC_REG_TX0_ANA_CTRL0                       0x8061
571 #define MDIO_WC_REG_TX1_ANA_CTRL0                       0x8071
572 #define MDIO_WC_REG_TX2_ANA_CTRL0                       0x8081
573 #define MDIO_WC_REG_TX3_ANA_CTRL0                       0x8091
574 #define MDIO_WC_REG_TX0_TX_DRIVER                       0x8067
575 #define MDIO_WC_REG_TX0_TX_DRIVER_IPRE_DRIVER_OFFSET            0x04
576 #define MDIO_WC_REG_TX0_TX_DRIVER_IPRE_DRIVER_MASK                      0x00f0
577 #define MDIO_WC_REG_TX0_TX_DRIVER_IDRIVER_OFFSET                0x08
578 #define MDIO_WC_REG_TX0_TX_DRIVER_IDRIVER_MASK                          0x0f00
579 #define MDIO_WC_REG_TX0_TX_DRIVER_POST2_COEFF_OFFSET            0x0c
580 #define MDIO_WC_REG_TX0_TX_DRIVER_POST2_COEFF_MASK                      0x7000
581 #define MDIO_WC_REG_TX1_TX_DRIVER                       0x8077
582 #define MDIO_WC_REG_TX2_TX_DRIVER                       0x8087
583 #define MDIO_WC_REG_TX3_TX_DRIVER                       0x8097
584 #define MDIO_WC_REG_RX0_ANARXCONTROL1G                  0x80b9
585 #define MDIO_WC_REG_RX2_ANARXCONTROL1G                  0x80d9
586 #define MDIO_WC_REG_RX0_PCI_CTRL                        0x80ba
587 #define MDIO_WC_REG_RX1_PCI_CTRL                        0x80ca
588 #define MDIO_WC_REG_RX2_PCI_CTRL                        0x80da
589 #define MDIO_WC_REG_RX3_PCI_CTRL                        0x80ea
590 #define MDIO_WC_REG_XGXSBLK2_UNICORE_MODE_10G           0x8104
591 #define MDIO_WC_REG_XGXS_STATUS3                        0x8129
592 #define MDIO_WC_REG_PAR_DET_10G_STATUS                  0x8130
593 #define MDIO_WC_REG_PAR_DET_10G_CTRL                    0x8131
594 #define MDIO_WC_REG_XGXS_STATUS4                        0x813c
595 #define MDIO_WC_REG_XGXS_X2_CONTROL2                    0x8141
596 #define MDIO_WC_REG_XGXS_X2_CONTROL3                    0x8142
597 #define MDIO_WC_REG_XGXS_RX_LN_SWAP1                    0x816B
598 #define MDIO_WC_REG_XGXS_TX_LN_SWAP1                    0x8169
599 #define MDIO_WC_REG_GP2_STATUS_GP_2_0                   0x81d0
600 #define MDIO_WC_REG_GP2_STATUS_GP_2_1                   0x81d1
601 #define MDIO_WC_REG_GP2_STATUS_GP_2_2                   0x81d2
602 #define MDIO_WC_REG_GP2_STATUS_GP_2_3                   0x81d3
603 #define MDIO_WC_REG_GP2_STATUS_GP_2_4                   0x81d4
604 #define MDIO_WC_REG_GP2_STATUS_GP_2_4_CL73_AN_CMPL 0x1000
605 #define MDIO_WC_REG_GP2_STATUS_GP_2_4_CL37_AN_CMPL 0x0100
606 #define MDIO_WC_REG_GP2_STATUS_GP_2_4_CL37_LP_AN_CAP 0x0010
607 #define MDIO_WC_REG_GP2_STATUS_GP_2_4_CL37_AN_CAP 0x1
608 #define MDIO_WC_REG_UC_INFO_B0_DEAD_TRAP                0x81EE
609 #define MDIO_WC_REG_UC_INFO_B1_VERSION                  0x81F0
610 #define MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE            0x81F2
611 #define MDIO_WC_REG_UC_INFO_B1_FIRMWARE_LANE0_OFFSET    0x0
612 #define MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE_DEFAULT        0x0
613 #define MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE_SFP_OPT_LR     0x1
614 #define MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE_SFP_DAC        0x2
615 #define MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE_SFP_XLAUI      0x3
616 #define MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE_LONG_CH_6G     0x4
617 #define MDIO_WC_REG_UC_INFO_B1_FIRMWARE_LANE1_OFFSET    0x4
618 #define MDIO_WC_REG_UC_INFO_B1_FIRMWARE_LANE2_OFFSET    0x8
619 #define MDIO_WC_REG_UC_INFO_B1_FIRMWARE_LANE3_OFFSET    0xc
620 #define MDIO_WC_REG_UC_INFO_B1_CRC                      0x81FE
621 #define MDIO_WC_REG_DSC1B0_UC_CTRL                              0x820e
622 #define MDIO_WC_REG_DSC1B0_UC_CTRL_RDY4CMD                      (1<<7)
623 #define MDIO_WC_REG_DSC_SMC                             0x8213
624 #define MDIO_WC_REG_DSC2B0_DSC_MISC_CTRL0               0x821e
625 #define MDIO_WC_REG_TX_FIR_TAP                          0x82e2
626 #define MDIO_WC_REG_TX_FIR_TAP_PRE_TAP_OFFSET           0x00
627 #define MDIO_WC_REG_TX_FIR_TAP_PRE_TAP_MASK                     0x000f
628 #define MDIO_WC_REG_TX_FIR_TAP_MAIN_TAP_OFFSET          0x04
629 #define MDIO_WC_REG_TX_FIR_TAP_MAIN_TAP_MASK            0x03f0
630 #define MDIO_WC_REG_TX_FIR_TAP_POST_TAP_OFFSET          0x0a
631 #define MDIO_WC_REG_TX_FIR_TAP_POST_TAP_MASK            0x7c00
632 #define MDIO_WC_REG_TX_FIR_TAP_ENABLE           0x8000
633 #define MDIO_WC_REG_CL72_USERB0_CL72_TX_FIR_TAP         0x82e2
634 #define MDIO_WC_REG_CL72_USERB0_CL72_MISC1_CONTROL      0x82e3
635 #define MDIO_WC_REG_CL72_USERB0_CL72_OS_DEF_CTRL        0x82e6
636 #define MDIO_WC_REG_CL72_USERB0_CL72_BR_DEF_CTRL        0x82e7
637 #define MDIO_WC_REG_CL72_USERB0_CL72_2P5_DEF_CTRL       0x82e8
638 #define MDIO_WC_REG_CL72_USERB0_CL72_MISC4_CONTROL      0x82ec
639 #define MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1         0x8300
640 #define MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2         0x8301
641 #define MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X3         0x8302
642 #define MDIO_WC_REG_SERDESDIGITAL_STATUS1000X1          0x8304
643 #define MDIO_WC_REG_SERDESDIGITAL_MISC1                 0x8308
644 #define MDIO_WC_REG_SERDESDIGITAL_MISC2                 0x8309
645 #define MDIO_WC_REG_DIGITAL3_UP1                        0x8329
646 #define MDIO_WC_REG_DIGITAL3_LP_UP1                     0x832c
647 #define MDIO_WC_REG_DIGITAL4_MISC3                      0x833c
648 #define MDIO_WC_REG_DIGITAL4_MISC5                      0x833e
649 #define MDIO_WC_REG_DIGITAL5_MISC6                      0x8345
650 #define MDIO_WC_REG_DIGITAL5_MISC7                      0x8349
651 #define MDIO_WC_REG_DIGITAL5_LINK_STATUS                0x834d
652 #define MDIO_WC_REG_DIGITAL5_ACTUAL_SPEED               0x834e
653 #define MDIO_WC_REG_DIGITAL6_MP5_NEXTPAGECTRL           0x8350
654 #define MDIO_WC_REG_CL49_USERB0_CTRL                    0x8368
655 #define MDIO_WC_REG_CL73_USERB0_CTRL                    0x8370
656 #define MDIO_WC_REG_CL73_USERB0_USTAT                   0x8371
657 #define MDIO_WC_REG_CL73_BAM_CTRL1                      0x8372
658 #define MDIO_WC_REG_CL73_BAM_CTRL2                      0x8373
659 #define MDIO_WC_REG_CL73_BAM_CTRL3                      0x8374
660 #define MDIO_WC_REG_CL73_BAM_CODE_FIELD                 0x837b
661 #define MDIO_WC_REG_EEE_COMBO_CONTROL0                  0x8390
662 #define MDIO_WC_REG_TX66_CONTROL                        0x83b0
663 #define MDIO_WC_REG_RX66_CONTROL                        0x83c0
664 #define MDIO_WC_REG_RX66_SCW0                           0x83c2
665 #define MDIO_WC_REG_RX66_SCW1                           0x83c3
666 #define MDIO_WC_REG_RX66_SCW2                           0x83c4
667 #define MDIO_WC_REG_RX66_SCW3                           0x83c5
668 #define MDIO_WC_REG_RX66_SCW0_MASK                      0x83c6
669 #define MDIO_WC_REG_RX66_SCW1_MASK                      0x83c7
670 #define MDIO_WC_REG_RX66_SCW2_MASK                      0x83c8
671 #define MDIO_WC_REG_RX66_SCW3_MASK                      0x83c9
672 #define MDIO_WC_REG_FX100_CTRL1                         0x8400
673 #define MDIO_WC_REG_FX100_CTRL3                         0x8402
674 #define MDIO_WC_REG_CL82_USERB1_TX_CTRL5                0x8436
675 #define MDIO_WC_REG_CL82_USERB1_TX_CTRL6                0x8437
676 #define MDIO_WC_REG_CL82_USERB1_TX_CTRL7                0x8438
677 #define MDIO_WC_REG_CL82_USERB1_TX_CTRL9                0x8439
678 #define MDIO_WC_REG_CL82_USERB1_RX_CTRL10               0x843a
679 #define MDIO_WC_REG_CL82_USERB1_RX_CTRL11               0x843b
680 #define MDIO_WC_REG_ETA_CL73_OUI1                       0x8453
681 #define MDIO_WC_REG_ETA_CL73_OUI2                       0x8454
682 #define MDIO_WC_REG_ETA_CL73_OUI3                       0x8455
683 #define MDIO_WC_REG_ETA_CL73_LD_BAM_CODE                0x8456
684 #define MDIO_WC_REG_ETA_CL73_LD_UD_CODE                 0x8457
685 #define MDIO_WC_REG_MICROBLK_CMD                        0xffc2
686 #define MDIO_WC_REG_MICROBLK_DL_STATUS                  0xffc5
687 #define MDIO_WC_REG_MICROBLK_CMD3                       0xffcc
688
689 #define MDIO_WC_REG_AERBLK_AER                          0xffde
690 #define MDIO_WC_REG_COMBO_IEEE0_MIICTRL                 0xffe0
691 #define MDIO_WC_REG_COMBO_IEEE0_MIIISTAT                0xffe1
692
693 #define MDIO_WC0_XGXS_BLK2_LANE_RESET                   0x810A
694 #define MDIO_WC0_XGXS_BLK2_LANE_RESET_RX_BITSHIFT       0
695 #define MDIO_WC0_XGXS_BLK2_LANE_RESET_TX_BITSHIFT       4
696
697 #define MDIO_WC0_XGXS_BLK6_XGXS_X2_CONTROL2             0x8141
698
699 #define DIGITAL5_ACTUAL_SPEED_TX_MASK                   0x003f
700
701 /* 54618se */
702 #define MDIO_REG_GPHY_MII_STATUS                        0x1
703 #define MDIO_REG_GPHY_PHYID_LSB                         0x3
704 #define MDIO_REG_GPHY_CL45_ADDR_REG                     0xd
705 #define MDIO_REG_GPHY_CL45_REG_WRITE            0x4000
706 #define MDIO_REG_GPHY_CL45_REG_READ             0xc000
707 #define MDIO_REG_GPHY_CL45_DATA_REG                     0xe
708 #define MDIO_REG_GPHY_EEE_RESOLVED              0x803e
709 #define MDIO_REG_GPHY_EXP_ACCESS_GATE                   0x15
710 #define MDIO_REG_GPHY_EXP_ACCESS                        0x17
711 #define MDIO_REG_GPHY_EXP_ACCESS_TOP            0xd00
712 #define MDIO_REG_GPHY_EXP_TOP_2K_BUF            0x40
713 #define MDIO_REG_GPHY_AUX_STATUS                        0x19
714 #define MDIO_REG_INTR_STATUS                            0x1a
715 #define MDIO_REG_INTR_MASK                              0x1b
716 #define MDIO_REG_INTR_MASK_LINK_STATUS                  (0x1 << 1)
717 #define MDIO_REG_GPHY_SHADOW                            0x1c
718 #define MDIO_REG_GPHY_SHADOW_LED_SEL1                   (0x0d << 10)
719 #define MDIO_REG_GPHY_SHADOW_LED_SEL2                   (0x0e << 10)
720 #define MDIO_REG_GPHY_SHADOW_WR_ENA                     (0x1 << 15)
721 #define MDIO_REG_GPHY_SHADOW_AUTO_DET_MED               (0x1e << 10)
722 #define MDIO_REG_GPHY_SHADOW_INVERT_FIB_SD              (0x1 << 8)
723
724 typedef elink_status_t(*read_sfp_module_eeprom_func_p) (struct elink_phy * phy,
725                                                         struct elink_params *
726                                                         params,
727                                                         uint8_t dev_addr,
728                                                         uint16_t addr,
729                                                         uint8_t byte_cnt,
730                                                         uint8_t * o_buf,
731                                                         uint8_t);
732 /********************************************************/
733 #define ELINK_ETH_HLEN                  14
734 /* L2 header size + 2*VLANs (8 bytes) + LLC SNAP (8 bytes) */
735 #define ELINK_ETH_OVREHEAD                      (ELINK_ETH_HLEN + 8 + 8)
736 #define ELINK_ETH_MIN_PACKET_SIZE               60
737 #define ELINK_ETH_MAX_PACKET_SIZE               1500
738 #define ELINK_ETH_MAX_JUMBO_PACKET_SIZE 9600
739 #define ELINK_MDIO_ACCESS_TIMEOUT               1000
740 #define WC_LANE_MAX                     4
741 #define I2C_SWITCH_WIDTH                2
742 #define I2C_BSC0                        0
743 #define I2C_BSC1                        1
744 #define I2C_WA_RETRY_CNT                3
745 #define I2C_WA_PWR_ITER                 (I2C_WA_RETRY_CNT - 1)
746 #define MCPR_IMC_COMMAND_READ_OP        1
747 #define MCPR_IMC_COMMAND_WRITE_OP       2
748
749 /* LED Blink rate that will achieve ~15.9Hz */
750 #define LED_BLINK_RATE_VAL_E3           354
751 #define LED_BLINK_RATE_VAL_E1X_E2       480
752 /***********************************************************/
753 /*                      Shortcut definitions               */
754 /***********************************************************/
755
756 #define ELINK_NIG_LATCH_BC_ENABLE_MI_INT 0
757
758 #define ELINK_NIG_STATUS_EMAC0_MI_INT \
759                 NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_EMAC0_MISC_MI_INT
760 #define ELINK_NIG_STATUS_XGXS0_LINK10G \
761                 NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_LINK10G
762 #define ELINK_NIG_STATUS_XGXS0_LINK_STATUS \
763                 NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_LINK_STATUS
764 #define ELINK_NIG_STATUS_XGXS0_LINK_STATUS_SIZE \
765                 NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_LINK_STATUS_SIZE
766 #define ELINK_NIG_STATUS_SERDES0_LINK_STATUS \
767                 NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_SERDES0_LINK_STATUS
768 #define ELINK_NIG_MASK_MI_INT \
769                 NIG_MASK_INTERRUPT_PORT0_REG_MASK_EMAC0_MISC_MI_INT
770 #define ELINK_NIG_MASK_XGXS0_LINK10G \
771                 NIG_MASK_INTERRUPT_PORT0_REG_MASK_XGXS0_LINK10G
772 #define ELINK_NIG_MASK_XGXS0_LINK_STATUS \
773                 NIG_MASK_INTERRUPT_PORT0_REG_MASK_XGXS0_LINK_STATUS
774 #define ELINK_NIG_MASK_SERDES0_LINK_STATUS \
775                 NIG_MASK_INTERRUPT_PORT0_REG_MASK_SERDES0_LINK_STATUS
776
777 #define ELINK_MDIO_AN_CL73_OR_37_COMPLETE \
778                 (MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_AUTONEG_COMPLETE | \
779                  MDIO_GP_STATUS_TOP_AN_STATUS1_CL37_AUTONEG_COMPLETE)
780
781 #define ELINK_XGXS_RESET_BITS \
782         (MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_RSTB_HW |   \
783          MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_IDDQ |      \
784          MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_PWRDWN |    \
785          MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_PWRDWN_SD | \
786          MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_TXD_FIFO_RSTB)
787
788 #define ELINK_SERDES_RESET_BITS \
789         (MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_RSTB_HW | \
790          MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_IDDQ |    \
791          MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_PWRDWN |  \
792          MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_PWRDWN_SD)
793
794 #define ELINK_AUTONEG_CL37              SHARED_HW_CFG_AN_ENABLE_CL37
795 #define ELINK_AUTONEG_CL73              SHARED_HW_CFG_AN_ENABLE_CL73
796 #define ELINK_AUTONEG_BAM               SHARED_HW_CFG_AN_ENABLE_BAM
797 #define ELINK_AUTONEG_PARALLEL \
798                                 SHARED_HW_CFG_AN_ENABLE_PARALLEL_DETECTION
799 #define ELINK_AUTONEG_SGMII_FIBER_AUTODET \
800                                 SHARED_HW_CFG_AN_EN_SGMII_FIBER_AUTO_DETECT
801 #define ELINK_AUTONEG_REMOTE_PHY        SHARED_HW_CFG_AN_ENABLE_REMOTE_PHY
802
803 #define ELINK_GP_STATUS_PAUSE_RSOLUTION_TXSIDE \
804                         MDIO_GP_STATUS_TOP_AN_STATUS1_PAUSE_RSOLUTION_TXSIDE
805 #define ELINK_GP_STATUS_PAUSE_RSOLUTION_RXSIDE \
806                         MDIO_GP_STATUS_TOP_AN_STATUS1_PAUSE_RSOLUTION_RXSIDE
807 #define ELINK_GP_STATUS_SPEED_MASK \
808                         MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_MASK
809 #define ELINK_GP_STATUS_10M     MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10M
810 #define ELINK_GP_STATUS_100M    MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_100M
811 #define ELINK_GP_STATUS_1G      MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_1G
812 #define ELINK_GP_STATUS_2_5G    MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_2_5G
813 #define ELINK_GP_STATUS_5G      MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_5G
814 #define ELINK_GP_STATUS_6G      MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_6G
815 #define ELINK_GP_STATUS_10G_HIG \
816                         MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_HIG
817 #define ELINK_GP_STATUS_10G_CX4 \
818                         MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_CX4
819 #define ELINK_GP_STATUS_1G_KX MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_1G_KX
820 #define ELINK_GP_STATUS_10G_KX4 \
821                         MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_KX4
822 #define ELINK_GP_STATUS_10G_KR MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_KR
823 #define ELINK_GP_STATUS_10G_XFI   MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_XFI
824 #define ELINK_GP_STATUS_20G_DXGXS MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_20G_DXGXS
825 #define ELINK_GP_STATUS_10G_SFI   MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_SFI
826 #define ELINK_GP_STATUS_20G_KR2 MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_20G_KR2
827 #define ELINK_LINK_10THD                LINK_STATUS_SPEED_AND_DUPLEX_10THD
828 #define ELINK_LINK_10TFD                LINK_STATUS_SPEED_AND_DUPLEX_10TFD
829 #define ELINK_LINK_100TXHD              LINK_STATUS_SPEED_AND_DUPLEX_100TXHD
830 #define ELINK_LINK_100T4                LINK_STATUS_SPEED_AND_DUPLEX_100T4
831 #define ELINK_LINK_100TXFD              LINK_STATUS_SPEED_AND_DUPLEX_100TXFD
832 #define ELINK_LINK_1000THD              LINK_STATUS_SPEED_AND_DUPLEX_1000THD
833 #define ELINK_LINK_1000TFD              LINK_STATUS_SPEED_AND_DUPLEX_1000TFD
834 #define ELINK_LINK_1000XFD              LINK_STATUS_SPEED_AND_DUPLEX_1000XFD
835 #define ELINK_LINK_2500THD              LINK_STATUS_SPEED_AND_DUPLEX_2500THD
836 #define ELINK_LINK_2500TFD              LINK_STATUS_SPEED_AND_DUPLEX_2500TFD
837 #define ELINK_LINK_2500XFD              LINK_STATUS_SPEED_AND_DUPLEX_2500XFD
838 #define ELINK_LINK_10GTFD               LINK_STATUS_SPEED_AND_DUPLEX_10GTFD
839 #define ELINK_LINK_10GXFD               LINK_STATUS_SPEED_AND_DUPLEX_10GXFD
840 #define ELINK_LINK_20GTFD               LINK_STATUS_SPEED_AND_DUPLEX_20GTFD
841 #define ELINK_LINK_20GXFD               LINK_STATUS_SPEED_AND_DUPLEX_20GXFD
842
843 #define ELINK_LINK_UPDATE_MASK \
844                         (LINK_STATUS_SPEED_AND_DUPLEX_MASK | \
845                          LINK_STATUS_LINK_UP | \
846                          LINK_STATUS_PHYSICAL_LINK_FLAG | \
847                          LINK_STATUS_AUTO_NEGOTIATE_COMPLETE | \
848                          LINK_STATUS_RX_FLOW_CONTROL_FLAG_MASK | \
849                          LINK_STATUS_TX_FLOW_CONTROL_FLAG_MASK | \
850                          LINK_STATUS_PARALLEL_DETECTION_FLAG_MASK | \
851                          LINK_STATUS_LINK_PARTNER_SYMMETRIC_PAUSE | \
852                          LINK_STATUS_LINK_PARTNER_ASYMMETRIC_PAUSE)
853
854 #define ELINK_SFP_EEPROM_CON_TYPE_ADDR          0x2
855 #define ELINK_SFP_EEPROM_CON_TYPE_VAL_LC        0x7
856 #define ELINK_SFP_EEPROM_CON_TYPE_VAL_COPPER    0x21
857 #define ELINK_SFP_EEPROM_CON_TYPE_VAL_RJ45      0x22
858
859 #define ELINK_SFP_EEPROM_COMP_CODE_ADDR         0x3
860 #define ELINK_SFP_EEPROM_COMP_CODE_SR_MASK      (1<<4)
861 #define ELINK_SFP_EEPROM_COMP_CODE_LR_MASK      (1<<5)
862 #define ELINK_SFP_EEPROM_COMP_CODE_LRM_MASK     (1<<6)
863
864 #define ELINK_SFP_EEPROM_FC_TX_TECH_ADDR                0x8
865 #define ELINK_SFP_EEPROM_FC_TX_TECH_BITMASK_COPPER_PASSIVE 0x4
866 #define ELINK_SFP_EEPROM_FC_TX_TECH_BITMASK_COPPER_ACTIVE  0x8
867
868 #define ELINK_SFP_EEPROM_OPTIONS_ADDR                   0x40
869 #define ELINK_SFP_EEPROM_OPTIONS_LINEAR_RX_OUT_MASK 0x1
870 #define ELINK_SFP_EEPROM_OPTIONS_SIZE                   2
871
872 #define ELINK_EDC_MODE_LINEAR                           0x0022
873 #define ELINK_EDC_MODE_LIMITING                         0x0044
874 #define ELINK_EDC_MODE_PASSIVE_DAC                      0x0055
875 #define ELINK_EDC_MODE_ACTIVE_DAC                       0x0066
876
877 /* ETS defines*/
878 #define DCBX_INVALID_COS                                        (0xFF)
879
880 #define ELINK_ETS_BW_LIMIT_CREDIT_UPPER_BOUND           (0x5000)
881 #define ELINK_ETS_BW_LIMIT_CREDIT_WEIGHT                (0x5000)
882 #define ELINK_ETS_E3B0_NIG_MIN_W_VAL_UP_TO_10GBPS               (1360)
883 #define ELINK_ETS_E3B0_NIG_MIN_W_VAL_20GBPS                     (2720)
884 #define ELINK_ETS_E3B0_PBF_MIN_W_VAL                            (10000)
885
886 #define ELINK_MAX_PACKET_SIZE                                   (9700)
887 #define MAX_KR_LINK_RETRY                               4
888
889 /**********************************************************/
890 /*                     INTERFACE                          */
891 /**********************************************************/
892
893 #define CL22_WR_OVER_CL45(_sc, _phy, _bank, _addr, _val) \
894         elink_cl45_write(_sc, _phy, \
895                 (_phy)->def_md_devad, \
896                 (_bank + (_addr & 0xf)), \
897                 _val)
898
899 #define CL22_RD_OVER_CL45(_sc, _phy, _bank, _addr, _val) \
900         elink_cl45_read(_sc, _phy, \
901                 (_phy)->def_md_devad, \
902                 (_bank + (_addr & 0xf)), \
903                 _val)
904
905 static uint32_t elink_bits_en(struct bnx2x_softc *sc, uint32_t reg, uint32_t bits)
906 {
907         uint32_t val = REG_RD(sc, reg);
908
909         val |= bits;
910         REG_WR(sc, reg, val);
911         return val;
912 }
913
914 static uint32_t elink_bits_dis(struct bnx2x_softc *sc, uint32_t reg,
915                                uint32_t bits)
916 {
917         uint32_t val = REG_RD(sc, reg);
918
919         val &= ~bits;
920         REG_WR(sc, reg, val);
921         return val;
922 }
923
924 /*
925  * elink_check_lfa - This function checks if link reinitialization is required,
926  *                   or link flap can be avoided.
927  *
928  * @params:     link parameters
929  * Returns 0 if Link Flap Avoidance conditions are met otherwise, the failed
930  *         condition code.
931  */
932 static int elink_check_lfa(struct elink_params *params)
933 {
934         uint32_t link_status, cfg_idx, lfa_mask, cfg_size;
935         uint32_t cur_speed_cap_mask, cur_req_fc_auto_adv, additional_config;
936         uint32_t saved_val, req_val, eee_status;
937         struct bnx2x_softc *sc = params->sc;
938
939         additional_config =
940             REG_RD(sc, params->lfa_base +
941                    offsetof(struct shmem_lfa, additional_config));
942
943         /* NOTE: must be first condition checked -
944          * to verify DCC bit is cleared in any case!
945          */
946         if (additional_config & NO_LFA_DUE_TO_DCC_MASK) {
947                 PMD_DRV_LOG(DEBUG, "No LFA due to DCC flap after clp exit");
948                 REG_WR(sc, params->lfa_base +
949                        offsetof(struct shmem_lfa, additional_config),
950                        additional_config & ~NO_LFA_DUE_TO_DCC_MASK);
951                 return LFA_DCC_LFA_DISABLED;
952         }
953
954         /* Verify that link is up */
955         link_status = REG_RD(sc, params->shmem_base +
956                              offsetof(struct shmem_region,
957                                       port_mb[params->port].link_status));
958         if (!(link_status & LINK_STATUS_LINK_UP))
959                 return LFA_LINK_DOWN;
960
961         /* if loaded after BOOT from SAN, don't flap the link in any case and
962          * rely on link set by preboot driver
963          */
964         if (params->feature_config_flags & ELINK_FEATURE_CONFIG_BOOT_FROM_SAN)
965                 return 0;
966
967         /* Verify that loopback mode is not set */
968         if (params->loopback_mode)
969                 return LFA_LOOPBACK_ENABLED;
970
971         /* Verify that MFW supports LFA */
972         if (!params->lfa_base)
973                 return LFA_MFW_IS_TOO_OLD;
974
975         if (params->num_phys == 3) {
976                 cfg_size = 2;
977                 lfa_mask = 0xffffffff;
978         } else {
979                 cfg_size = 1;
980                 lfa_mask = 0xffff;
981         }
982
983         /* Compare Duplex */
984         saved_val = REG_RD(sc, params->lfa_base +
985                            offsetof(struct shmem_lfa, req_duplex));
986         req_val = params->req_duplex[0] | (params->req_duplex[1] << 16);
987         if ((saved_val & lfa_mask) != (req_val & lfa_mask)) {
988                 PMD_DRV_LOG(INFO, "Duplex mismatch %x vs. %x",
989                             (saved_val & lfa_mask), (req_val & lfa_mask));
990                 return LFA_DUPLEX_MISMATCH;
991         }
992         /* Compare Flow Control */
993         saved_val = REG_RD(sc, params->lfa_base +
994                            offsetof(struct shmem_lfa, req_flow_ctrl));
995         req_val = params->req_flow_ctrl[0] | (params->req_flow_ctrl[1] << 16);
996         if ((saved_val & lfa_mask) != (req_val & lfa_mask)) {
997                 PMD_DRV_LOG(DEBUG, "Flow control mismatch %x vs. %x",
998                             (saved_val & lfa_mask), (req_val & lfa_mask));
999                 return LFA_FLOW_CTRL_MISMATCH;
1000         }
1001         /* Compare Link Speed */
1002         saved_val = REG_RD(sc, params->lfa_base +
1003                            offsetof(struct shmem_lfa, req_line_speed));
1004         req_val = params->req_line_speed[0] | (params->req_line_speed[1] << 16);
1005         if ((saved_val & lfa_mask) != (req_val & lfa_mask)) {
1006                 PMD_DRV_LOG(DEBUG, "Link speed mismatch %x vs. %x",
1007                             (saved_val & lfa_mask), (req_val & lfa_mask));
1008                 return LFA_LINK_SPEED_MISMATCH;
1009         }
1010
1011         for (cfg_idx = 0; cfg_idx < cfg_size; cfg_idx++) {
1012                 cur_speed_cap_mask = REG_RD(sc, params->lfa_base +
1013                                             offsetof(struct shmem_lfa,
1014                                                      speed_cap_mask[cfg_idx]));
1015
1016                 if (cur_speed_cap_mask != params->speed_cap_mask[cfg_idx]) {
1017                         PMD_DRV_LOG(DEBUG, "Speed Cap mismatch %x vs. %x",
1018                                     cur_speed_cap_mask,
1019                                     params->speed_cap_mask[cfg_idx]);
1020                         return LFA_SPEED_CAP_MISMATCH;
1021                 }
1022         }
1023
1024         cur_req_fc_auto_adv =
1025             REG_RD(sc, params->lfa_base +
1026                    offsetof(struct shmem_lfa, additional_config)) &
1027             REQ_FC_AUTO_ADV_MASK;
1028
1029         if ((uint16_t) cur_req_fc_auto_adv != params->req_fc_auto_adv) {
1030                 PMD_DRV_LOG(DEBUG, "Flow Ctrl AN mismatch %x vs. %x",
1031                             cur_req_fc_auto_adv, params->req_fc_auto_adv);
1032                 return LFA_FLOW_CTRL_MISMATCH;
1033         }
1034
1035         eee_status = REG_RD(sc, params->shmem2_base +
1036                             offsetof(struct shmem2_region,
1037                                      eee_status[params->port]));
1038
1039         if (((eee_status & SHMEM_EEE_LPI_REQUESTED_BIT) ^
1040              (params->eee_mode & ELINK_EEE_MODE_ENABLE_LPI)) ||
1041             ((eee_status & SHMEM_EEE_REQUESTED_BIT) ^
1042              (params->eee_mode & ELINK_EEE_MODE_ADV_LPI))) {
1043                 PMD_DRV_LOG(DEBUG, "EEE mismatch %x vs. %x", params->eee_mode,
1044                             eee_status);
1045                 return LFA_EEE_MISMATCH;
1046         }
1047
1048         /* LFA conditions are met */
1049         return 0;
1050 }
1051
1052 /******************************************************************/
1053 /*                      EPIO/GPIO section                         */
1054 /******************************************************************/
1055 static void elink_get_epio(struct bnx2x_softc *sc, uint32_t epio_pin,
1056                            uint32_t * en)
1057 {
1058         uint32_t epio_mask, gp_oenable;
1059         *en = 0;
1060         /* Sanity check */
1061         if (epio_pin > 31) {
1062                 PMD_DRV_LOG(DEBUG, "Invalid EPIO pin %d to get", epio_pin);
1063                 return;
1064         }
1065
1066         epio_mask = 1 << epio_pin;
1067         /* Set this EPIO to output */
1068         gp_oenable = REG_RD(sc, MCP_REG_MCPR_GP_OENABLE);
1069         REG_WR(sc, MCP_REG_MCPR_GP_OENABLE, gp_oenable & ~epio_mask);
1070
1071         *en = (REG_RD(sc, MCP_REG_MCPR_GP_INPUTS) & epio_mask) >> epio_pin;
1072 }
1073
1074 static void elink_set_epio(struct bnx2x_softc *sc, uint32_t epio_pin, uint32_t en)
1075 {
1076         uint32_t epio_mask, gp_output, gp_oenable;
1077
1078         /* Sanity check */
1079         if (epio_pin > 31) {
1080                 PMD_DRV_LOG(DEBUG, "Invalid EPIO pin %d to set", epio_pin);
1081                 return;
1082         }
1083         PMD_DRV_LOG(DEBUG, "Setting EPIO pin %d to %d", epio_pin, en);
1084         epio_mask = 1 << epio_pin;
1085         /* Set this EPIO to output */
1086         gp_output = REG_RD(sc, MCP_REG_MCPR_GP_OUTPUTS);
1087         if (en)
1088                 gp_output |= epio_mask;
1089         else
1090                 gp_output &= ~epio_mask;
1091
1092         REG_WR(sc, MCP_REG_MCPR_GP_OUTPUTS, gp_output);
1093
1094         /* Set the value for this EPIO */
1095         gp_oenable = REG_RD(sc, MCP_REG_MCPR_GP_OENABLE);
1096         REG_WR(sc, MCP_REG_MCPR_GP_OENABLE, gp_oenable | epio_mask);
1097 }
1098
1099 static void elink_set_cfg_pin(struct bnx2x_softc *sc, uint32_t pin_cfg,
1100                               uint32_t val)
1101 {
1102         if (pin_cfg == PIN_CFG_NA)
1103                 return;
1104         if (pin_cfg >= PIN_CFG_EPIO0) {
1105                 elink_set_epio(sc, pin_cfg - PIN_CFG_EPIO0, val);
1106         } else {
1107                 uint8_t gpio_num = (pin_cfg - PIN_CFG_GPIO0_P0) & 0x3;
1108                 uint8_t gpio_port = (pin_cfg - PIN_CFG_GPIO0_P0) >> 2;
1109                 elink_cb_gpio_write(sc, gpio_num, (uint8_t) val, gpio_port);
1110         }
1111 }
1112
1113 static uint32_t elink_get_cfg_pin(struct bnx2x_softc *sc, uint32_t pin_cfg,
1114                                   uint32_t * val)
1115 {
1116         if (pin_cfg == PIN_CFG_NA)
1117                 return ELINK_STATUS_ERROR;
1118         if (pin_cfg >= PIN_CFG_EPIO0) {
1119                 elink_get_epio(sc, pin_cfg - PIN_CFG_EPIO0, val);
1120         } else {
1121                 uint8_t gpio_num = (pin_cfg - PIN_CFG_GPIO0_P0) & 0x3;
1122                 uint8_t gpio_port = (pin_cfg - PIN_CFG_GPIO0_P0) >> 2;
1123                 *val = elink_cb_gpio_read(sc, gpio_num, gpio_port);
1124         }
1125         return ELINK_STATUS_OK;
1126
1127 }
1128
1129 /******************************************************************/
1130 /*                      PFC section                               */
1131 /******************************************************************/
1132 static void elink_update_pfc_xmac(struct elink_params *params,
1133                                   struct elink_vars *vars)
1134 {
1135         struct bnx2x_softc *sc = params->sc;
1136         uint32_t xmac_base;
1137         uint32_t pause_val, pfc0_val, pfc1_val;
1138
1139         /* XMAC base adrr */
1140         xmac_base = (params->port) ? GRCBASE_XMAC1 : GRCBASE_XMAC0;
1141
1142         /* Initialize pause and pfc registers */
1143         pause_val = 0x18000;
1144         pfc0_val = 0xFFFF8000;
1145         pfc1_val = 0x2;
1146
1147         /* No PFC support */
1148         if (!(params->feature_config_flags & ELINK_FEATURE_CONFIG_PFC_ENABLED)) {
1149
1150                 /* RX flow control - Process pause frame in receive direction
1151                  */
1152                 if (vars->flow_ctrl & ELINK_FLOW_CTRL_RX)
1153                         pause_val |= XMAC_PAUSE_CTRL_REG_RX_PAUSE_EN;
1154
1155                 /* TX flow control - Send pause packet when buffer is full */
1156                 if (vars->flow_ctrl & ELINK_FLOW_CTRL_TX)
1157                         pause_val |= XMAC_PAUSE_CTRL_REG_TX_PAUSE_EN;
1158         } else {                /* PFC support */
1159                 pfc1_val |= XMAC_PFC_CTRL_HI_REG_PFC_REFRESH_EN |
1160                     XMAC_PFC_CTRL_HI_REG_PFC_STATS_EN |
1161                     XMAC_PFC_CTRL_HI_REG_RX_PFC_EN |
1162                     XMAC_PFC_CTRL_HI_REG_TX_PFC_EN |
1163                     XMAC_PFC_CTRL_HI_REG_FORCE_PFC_XON;
1164                 /* Write pause and PFC registers */
1165                 REG_WR(sc, xmac_base + XMAC_REG_PAUSE_CTRL, pause_val);
1166                 REG_WR(sc, xmac_base + XMAC_REG_PFC_CTRL, pfc0_val);
1167                 REG_WR(sc, xmac_base + XMAC_REG_PFC_CTRL_HI, pfc1_val);
1168                 pfc1_val &= ~XMAC_PFC_CTRL_HI_REG_FORCE_PFC_XON;
1169
1170         }
1171
1172         /* Write pause and PFC registers */
1173         REG_WR(sc, xmac_base + XMAC_REG_PAUSE_CTRL, pause_val);
1174         REG_WR(sc, xmac_base + XMAC_REG_PFC_CTRL, pfc0_val);
1175         REG_WR(sc, xmac_base + XMAC_REG_PFC_CTRL_HI, pfc1_val);
1176
1177         /* Set MAC address for source TX Pause/PFC frames */
1178         REG_WR(sc, xmac_base + XMAC_REG_CTRL_SA_LO,
1179                ((params->mac_addr[2] << 24) |
1180                 (params->mac_addr[3] << 16) |
1181                 (params->mac_addr[4] << 8) | (params->mac_addr[5])));
1182         REG_WR(sc, xmac_base + XMAC_REG_CTRL_SA_HI,
1183                ((params->mac_addr[0] << 8) | (params->mac_addr[1])));
1184
1185         DELAY(30);
1186 }
1187
1188 /******************************************************************/
1189 /*                      MAC/PBF section                           */
1190 /******************************************************************/
1191 static void elink_set_mdio_clk(struct bnx2x_softc *sc, uint32_t emac_base)
1192 {
1193         uint32_t new_mode, cur_mode;
1194         uint32_t clc_cnt;
1195         /* Set clause 45 mode, slow down the MDIO clock to 2.5MHz
1196          * (a value of 49==0x31) and make sure that the AUTO poll is off
1197          */
1198         cur_mode = REG_RD(sc, emac_base + EMAC_REG_EMAC_MDIO_MODE);
1199
1200         if (USES_WARPCORE(sc))
1201                 clc_cnt = 74L << EMAC_MDIO_MODE_CLOCK_CNT_BITSHIFT;
1202         else
1203                 clc_cnt = 49L << EMAC_MDIO_MODE_CLOCK_CNT_BITSHIFT;
1204
1205         if (((cur_mode & EMAC_MDIO_MODE_CLOCK_CNT) == clc_cnt) &&
1206             (cur_mode & (EMAC_MDIO_MODE_CLAUSE_45)))
1207                 return;
1208
1209         new_mode = cur_mode &
1210             ~(EMAC_MDIO_MODE_AUTO_POLL | EMAC_MDIO_MODE_CLOCK_CNT);
1211         new_mode |= clc_cnt;
1212         new_mode |= (EMAC_MDIO_MODE_CLAUSE_45);
1213
1214         PMD_DRV_LOG(DEBUG, "Changing emac_mode from 0x%x to 0x%x",
1215                     cur_mode, new_mode);
1216         REG_WR(sc, emac_base + EMAC_REG_EMAC_MDIO_MODE, new_mode);
1217         DELAY(40);
1218 }
1219
1220 static void elink_set_mdio_emac_per_phy(struct bnx2x_softc *sc,
1221                                         struct elink_params *params)
1222 {
1223         uint8_t phy_index;
1224         /* Set mdio clock per phy */
1225         for (phy_index = ELINK_INT_PHY; phy_index < params->num_phys;
1226              phy_index++)
1227                 elink_set_mdio_clk(sc, params->phy[phy_index].mdio_ctrl);
1228 }
1229
1230 static uint8_t elink_is_4_port_mode(struct bnx2x_softc *sc)
1231 {
1232         uint32_t port4mode_ovwr_val;
1233         /* Check 4-port override enabled */
1234         port4mode_ovwr_val = REG_RD(sc, MISC_REG_PORT4MODE_EN_OVWR);
1235         if (port4mode_ovwr_val & (1 << 0)) {
1236                 /* Return 4-port mode override value */
1237                 return (port4mode_ovwr_val & (1 << 1)) == (1 << 1);
1238         }
1239         /* Return 4-port mode from input pin */
1240         return (uint8_t) REG_RD(sc, MISC_REG_PORT4MODE_EN);
1241 }
1242
1243 static void elink_emac_init(struct elink_params *params)
1244 {
1245         /* reset and unreset the emac core */
1246         struct bnx2x_softc *sc = params->sc;
1247         uint8_t port = params->port;
1248         uint32_t emac_base = port ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
1249         uint32_t val;
1250         uint16_t timeout;
1251
1252         REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
1253                (MISC_REGISTERS_RESET_REG_2_RST_EMAC0_HARD_CORE << port));
1254         DELAY(5);
1255         REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET,
1256                (MISC_REGISTERS_RESET_REG_2_RST_EMAC0_HARD_CORE << port));
1257
1258         /* init emac - use read-modify-write */
1259         /* self clear reset */
1260         val = REG_RD(sc, emac_base + EMAC_REG_EMAC_MODE);
1261         elink_cb_reg_write(sc, emac_base + EMAC_REG_EMAC_MODE,
1262                            (val | EMAC_MODE_RESET));
1263
1264         timeout = 200;
1265         do {
1266                 val = REG_RD(sc, emac_base + EMAC_REG_EMAC_MODE);
1267                 PMD_DRV_LOG(DEBUG, "EMAC reset reg is %u", val);
1268                 if (!timeout) {
1269                         PMD_DRV_LOG(DEBUG, "EMAC timeout!");
1270                         return;
1271                 }
1272                 timeout--;
1273         } while (val & EMAC_MODE_RESET);
1274
1275         elink_set_mdio_emac_per_phy(sc, params);
1276         /* Set mac address */
1277         val = ((params->mac_addr[0] << 8) | params->mac_addr[1]);
1278         elink_cb_reg_write(sc, emac_base + EMAC_REG_EMAC_MAC_MATCH, val);
1279
1280         val = ((params->mac_addr[2] << 24) |
1281                (params->mac_addr[3] << 16) |
1282                (params->mac_addr[4] << 8) | params->mac_addr[5]);
1283         elink_cb_reg_write(sc, emac_base + EMAC_REG_EMAC_MAC_MATCH + 4, val);
1284 }
1285
1286 static void elink_set_xumac_nig(struct elink_params *params,
1287                                 uint16_t tx_pause_en, uint8_t enable)
1288 {
1289         struct bnx2x_softc *sc = params->sc;
1290
1291         REG_WR(sc, params->port ? NIG_REG_P1_MAC_IN_EN : NIG_REG_P0_MAC_IN_EN,
1292                enable);
1293         REG_WR(sc, params->port ? NIG_REG_P1_MAC_OUT_EN : NIG_REG_P0_MAC_OUT_EN,
1294                enable);
1295         REG_WR(sc, params->port ? NIG_REG_P1_MAC_PAUSE_OUT_EN :
1296                NIG_REG_P0_MAC_PAUSE_OUT_EN, tx_pause_en);
1297 }
1298
1299 static void elink_set_umac_rxtx(struct elink_params *params, uint8_t en)
1300 {
1301         uint32_t umac_base = params->port ? GRCBASE_UMAC1 : GRCBASE_UMAC0;
1302         uint32_t val;
1303         struct bnx2x_softc *sc = params->sc;
1304         if (!(REG_RD(sc, MISC_REG_RESET_REG_2) &
1305               (MISC_REGISTERS_RESET_REG_2_UMAC0 << params->port)))
1306                 return;
1307         val = REG_RD(sc, umac_base + UMAC_REG_COMMAND_CONFIG);
1308         if (en)
1309                 val |= (UMAC_COMMAND_CONFIG_REG_TX_ENA |
1310                         UMAC_COMMAND_CONFIG_REG_RX_ENA);
1311         else
1312                 val &= ~(UMAC_COMMAND_CONFIG_REG_TX_ENA |
1313                          UMAC_COMMAND_CONFIG_REG_RX_ENA);
1314         /* Disable RX and TX */
1315         REG_WR(sc, umac_base + UMAC_REG_COMMAND_CONFIG, val);
1316 }
1317
1318 static void elink_umac_enable(struct elink_params *params,
1319                               struct elink_vars *vars, uint8_t lb)
1320 {
1321         uint32_t val;
1322         uint32_t umac_base = params->port ? GRCBASE_UMAC1 : GRCBASE_UMAC0;
1323         struct bnx2x_softc *sc = params->sc;
1324         /* Reset UMAC */
1325         REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
1326                (MISC_REGISTERS_RESET_REG_2_UMAC0 << params->port));
1327         DELAY(1000 * 1);
1328
1329         REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET,
1330                (MISC_REGISTERS_RESET_REG_2_UMAC0 << params->port));
1331
1332         PMD_DRV_LOG(DEBUG, "enabling UMAC");
1333
1334         /* This register opens the gate for the UMAC despite its name */
1335         REG_WR(sc, NIG_REG_EGRESS_EMAC0_PORT + params->port * 4, 1);
1336
1337         val = UMAC_COMMAND_CONFIG_REG_PROMIS_EN |
1338             UMAC_COMMAND_CONFIG_REG_PAD_EN |
1339             UMAC_COMMAND_CONFIG_REG_SW_RESET |
1340             UMAC_COMMAND_CONFIG_REG_NO_LGTH_CHECK;
1341         switch (vars->line_speed) {
1342         case ELINK_SPEED_10:
1343                 val |= (0 << 2);
1344                 break;
1345         case ELINK_SPEED_100:
1346                 val |= (1 << 2);
1347                 break;
1348         case ELINK_SPEED_1000:
1349                 val |= (2 << 2);
1350                 break;
1351         case ELINK_SPEED_2500:
1352                 val |= (3 << 2);
1353                 break;
1354         default:
1355                 PMD_DRV_LOG(DEBUG, "Invalid speed for UMAC %d",
1356                             vars->line_speed);
1357                 break;
1358         }
1359         if (!(vars->flow_ctrl & ELINK_FLOW_CTRL_TX))
1360                 val |= UMAC_COMMAND_CONFIG_REG_IGNORE_TX_PAUSE;
1361
1362         if (!(vars->flow_ctrl & ELINK_FLOW_CTRL_RX))
1363                 val |= UMAC_COMMAND_CONFIG_REG_PAUSE_IGNORE;
1364
1365         if (vars->duplex == DUPLEX_HALF)
1366                 val |= UMAC_COMMAND_CONFIG_REG_HD_ENA;
1367
1368         REG_WR(sc, umac_base + UMAC_REG_COMMAND_CONFIG, val);
1369         DELAY(50);
1370
1371         /* Configure UMAC for EEE */
1372         if (vars->eee_status & SHMEM_EEE_ADV_STATUS_MASK) {
1373                 PMD_DRV_LOG(DEBUG, "configured UMAC for EEE");
1374                 REG_WR(sc, umac_base + UMAC_REG_UMAC_EEE_CTRL,
1375                        UMAC_UMAC_EEE_CTRL_REG_EEE_EN);
1376                 REG_WR(sc, umac_base + UMAC_REG_EEE_WAKE_TIMER, 0x11);
1377         } else {
1378                 REG_WR(sc, umac_base + UMAC_REG_UMAC_EEE_CTRL, 0x0);
1379         }
1380
1381         /* Set MAC address for source TX Pause/PFC frames (under SW reset) */
1382         REG_WR(sc, umac_base + UMAC_REG_MAC_ADDR0,
1383                ((params->mac_addr[2] << 24) |
1384                 (params->mac_addr[3] << 16) |
1385                 (params->mac_addr[4] << 8) | (params->mac_addr[5])));
1386         REG_WR(sc, umac_base + UMAC_REG_MAC_ADDR1,
1387                ((params->mac_addr[0] << 8) | (params->mac_addr[1])));
1388
1389         /* Enable RX and TX */
1390         val &= ~UMAC_COMMAND_CONFIG_REG_PAD_EN;
1391         val |= UMAC_COMMAND_CONFIG_REG_TX_ENA | UMAC_COMMAND_CONFIG_REG_RX_ENA;
1392         REG_WR(sc, umac_base + UMAC_REG_COMMAND_CONFIG, val);
1393         DELAY(50);
1394
1395         /* Remove SW Reset */
1396         val &= ~UMAC_COMMAND_CONFIG_REG_SW_RESET;
1397
1398         /* Check loopback mode */
1399         if (lb)
1400                 val |= UMAC_COMMAND_CONFIG_REG_LOOP_ENA;
1401         REG_WR(sc, umac_base + UMAC_REG_COMMAND_CONFIG, val);
1402
1403         /* Maximum Frame Length (RW). Defines a 14-Bit maximum frame
1404          * length used by the MAC receive logic to check frames.
1405          */
1406         REG_WR(sc, umac_base + UMAC_REG_MAXFR, 0x2710);
1407         elink_set_xumac_nig(params,
1408                             ((vars->flow_ctrl & ELINK_FLOW_CTRL_TX) != 0), 1);
1409         vars->mac_type = ELINK_MAC_TYPE_UMAC;
1410
1411 }
1412
1413 /* Define the XMAC mode */
1414 static void elink_xmac_init(struct elink_params *params, uint32_t max_speed)
1415 {
1416         struct bnx2x_softc *sc = params->sc;
1417         uint32_t is_port4mode = elink_is_4_port_mode(sc);
1418
1419         /* In 4-port mode, need to set the mode only once, so if XMAC is
1420          * already out of reset, it means the mode has already been set,
1421          * and it must not* reset the XMAC again, since it controls both
1422          * ports of the path
1423          */
1424
1425         if (((CHIP_NUM(sc) == CHIP_NUM_57840_4_10) ||
1426              (CHIP_NUM(sc) == CHIP_NUM_57840_2_20) ||
1427              (CHIP_NUM(sc) == CHIP_NUM_57840_OBS)) &&
1428             is_port4mode &&
1429             (REG_RD(sc, MISC_REG_RESET_REG_2) &
1430              MISC_REGISTERS_RESET_REG_2_XMAC)) {
1431                 PMD_DRV_LOG(DEBUG, "XMAC already out of reset in 4-port mode");
1432                 return;
1433         }
1434
1435         /* Hard reset */
1436         REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
1437                MISC_REGISTERS_RESET_REG_2_XMAC);
1438         DELAY(1000 * 1);
1439
1440         REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET,
1441                MISC_REGISTERS_RESET_REG_2_XMAC);
1442         if (is_port4mode) {
1443                 PMD_DRV_LOG(DEBUG, "Init XMAC to 2 ports x 10G per path");
1444
1445                 /* Set the number of ports on the system side to up to 2 */
1446                 REG_WR(sc, MISC_REG_XMAC_CORE_PORT_MODE, 1);
1447
1448                 /* Set the number of ports on the Warp Core to 10G */
1449                 REG_WR(sc, MISC_REG_XMAC_PHY_PORT_MODE, 3);
1450         } else {
1451                 /* Set the number of ports on the system side to 1 */
1452                 REG_WR(sc, MISC_REG_XMAC_CORE_PORT_MODE, 0);
1453                 if (max_speed == ELINK_SPEED_10000) {
1454                         PMD_DRV_LOG(DEBUG,
1455                                     "Init XMAC to 10G x 1 port per path");
1456                         /* Set the number of ports on the Warp Core to 10G */
1457                         REG_WR(sc, MISC_REG_XMAC_PHY_PORT_MODE, 3);
1458                 } else {
1459                         PMD_DRV_LOG(DEBUG,
1460                                     "Init XMAC to 20G x 2 ports per path");
1461                         /* Set the number of ports on the Warp Core to 20G */
1462                         REG_WR(sc, MISC_REG_XMAC_PHY_PORT_MODE, 1);
1463                 }
1464         }
1465         /* Soft reset */
1466         REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
1467                MISC_REGISTERS_RESET_REG_2_XMAC_SOFT);
1468         DELAY(1000 * 1);
1469
1470         REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET,
1471                MISC_REGISTERS_RESET_REG_2_XMAC_SOFT);
1472
1473 }
1474
1475 static void elink_set_xmac_rxtx(struct elink_params *params, uint8_t en)
1476 {
1477         uint8_t port = params->port;
1478         struct bnx2x_softc *sc = params->sc;
1479         uint32_t pfc_ctrl, xmac_base = (port) ? GRCBASE_XMAC1 : GRCBASE_XMAC0;
1480         uint32_t val;
1481
1482         if (REG_RD(sc, MISC_REG_RESET_REG_2) & MISC_REGISTERS_RESET_REG_2_XMAC) {
1483                 /* Send an indication to change the state in the NIG back to XON
1484                  * Clearing this bit enables the next set of this bit to get
1485                  * rising edge
1486                  */
1487                 pfc_ctrl = REG_RD(sc, xmac_base + XMAC_REG_PFC_CTRL_HI);
1488                 REG_WR(sc, xmac_base + XMAC_REG_PFC_CTRL_HI,
1489                        (pfc_ctrl & ~(1 << 1)));
1490                 REG_WR(sc, xmac_base + XMAC_REG_PFC_CTRL_HI,
1491                        (pfc_ctrl | (1 << 1)));
1492                 PMD_DRV_LOG(DEBUG, "Disable XMAC on port %x", port);
1493                 val = REG_RD(sc, xmac_base + XMAC_REG_CTRL);
1494                 if (en)
1495                         val |= (XMAC_CTRL_REG_TX_EN | XMAC_CTRL_REG_RX_EN);
1496                 else
1497                         val &= ~(XMAC_CTRL_REG_TX_EN | XMAC_CTRL_REG_RX_EN);
1498                 REG_WR(sc, xmac_base + XMAC_REG_CTRL, val);
1499         }
1500 }
1501
1502 static elink_status_t elink_xmac_enable(struct elink_params *params,
1503                                         struct elink_vars *vars, uint8_t lb)
1504 {
1505         uint32_t val, xmac_base;
1506         struct bnx2x_softc *sc = params->sc;
1507         PMD_DRV_LOG(DEBUG, "enabling XMAC");
1508
1509         xmac_base = (params->port) ? GRCBASE_XMAC1 : GRCBASE_XMAC0;
1510
1511         elink_xmac_init(params, vars->line_speed);
1512
1513         /* This register determines on which events the MAC will assert
1514          * error on the i/f to the NIG along w/ EOP.
1515          */
1516
1517         /* This register tells the NIG whether to send traffic to UMAC
1518          * or XMAC
1519          */
1520         REG_WR(sc, NIG_REG_EGRESS_EMAC0_PORT + params->port * 4, 0);
1521
1522         /* When XMAC is in XLGMII mode, disable sending idles for fault
1523          * detection.
1524          */
1525         if (!(params->phy[ELINK_INT_PHY].flags & ELINK_FLAGS_TX_ERROR_CHECK)) {
1526                 REG_WR(sc, xmac_base + XMAC_REG_RX_LSS_CTRL,
1527                        (XMAC_RX_LSS_CTRL_REG_LOCAL_FAULT_DISABLE |
1528                         XMAC_RX_LSS_CTRL_REG_REMOTE_FAULT_DISABLE));
1529                 REG_WR(sc, xmac_base + XMAC_REG_CLEAR_RX_LSS_STATUS, 0);
1530                 REG_WR(sc, xmac_base + XMAC_REG_CLEAR_RX_LSS_STATUS,
1531                        XMAC_CLEAR_RX_LSS_STATUS_REG_CLEAR_LOCAL_FAULT_STATUS |
1532                        XMAC_CLEAR_RX_LSS_STATUS_REG_CLEAR_REMOTE_FAULT_STATUS);
1533         }
1534         /* Set Max packet size */
1535         REG_WR(sc, xmac_base + XMAC_REG_RX_MAX_SIZE, 0x2710);
1536
1537         /* CRC append for Tx packets */
1538         REG_WR(sc, xmac_base + XMAC_REG_TX_CTRL, 0xC800);
1539
1540         /* update PFC */
1541         elink_update_pfc_xmac(params, vars);
1542
1543         if (vars->eee_status & SHMEM_EEE_ADV_STATUS_MASK) {
1544                 PMD_DRV_LOG(DEBUG, "Setting XMAC for EEE");
1545                 REG_WR(sc, xmac_base + XMAC_REG_EEE_TIMERS_HI, 0x1380008);
1546                 REG_WR(sc, xmac_base + XMAC_REG_EEE_CTRL, 0x1);
1547         } else {
1548                 REG_WR(sc, xmac_base + XMAC_REG_EEE_CTRL, 0x0);
1549         }
1550
1551         /* Enable TX and RX */
1552         val = XMAC_CTRL_REG_TX_EN | XMAC_CTRL_REG_RX_EN;
1553
1554         /* Set MAC in XLGMII mode for dual-mode */
1555         if ((vars->line_speed == ELINK_SPEED_20000) &&
1556             (params->phy[ELINK_INT_PHY].supported &
1557              ELINK_SUPPORTED_20000baseKR2_Full))
1558                 val |= XMAC_CTRL_REG_XLGMII_ALIGN_ENB;
1559
1560         /* Check loopback mode */
1561         if (lb)
1562                 val |= XMAC_CTRL_REG_LINE_LOCAL_LPBK;
1563         REG_WR(sc, xmac_base + XMAC_REG_CTRL, val);
1564         elink_set_xumac_nig(params,
1565                             ((vars->flow_ctrl & ELINK_FLOW_CTRL_TX) != 0), 1);
1566
1567         vars->mac_type = ELINK_MAC_TYPE_XMAC;
1568
1569         return ELINK_STATUS_OK;
1570 }
1571
1572 static elink_status_t elink_emac_enable(struct elink_params *params,
1573                                         struct elink_vars *vars, uint8_t lb)
1574 {
1575         struct bnx2x_softc *sc = params->sc;
1576         uint8_t port = params->port;
1577         uint32_t emac_base = port ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
1578         uint32_t val;
1579
1580         PMD_DRV_LOG(DEBUG, "enabling EMAC");
1581
1582         /* Disable BMAC */
1583         REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
1584                (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port));
1585
1586         /* enable emac and not bmac */
1587         REG_WR(sc, NIG_REG_EGRESS_EMAC0_PORT + port * 4, 1);
1588
1589         if (vars->phy_flags & PHY_XGXS_FLAG) {
1590                 uint32_t ser_lane = ((params->lane_config &
1591                                       PORT_HW_CFG_LANE_SWAP_CFG_MASTER_MASK) >>
1592                                      PORT_HW_CFG_LANE_SWAP_CFG_MASTER_SHIFT);
1593
1594                 PMD_DRV_LOG(DEBUG, "XGXS");
1595                 /* select the master lanes (out of 0-3) */
1596                 REG_WR(sc, NIG_REG_XGXS_LANE_SEL_P0 + port * 4, ser_lane);
1597                 /* select XGXS */
1598                 REG_WR(sc, NIG_REG_XGXS_SERDES0_MODE_SEL + port * 4, 1);
1599
1600         } else {                /* SerDes */
1601                 PMD_DRV_LOG(DEBUG, "SerDes");
1602                 /* select SerDes */
1603                 REG_WR(sc, NIG_REG_XGXS_SERDES0_MODE_SEL + port * 4, 0);
1604         }
1605
1606         elink_bits_en(sc, emac_base + EMAC_REG_EMAC_RX_MODE,
1607                       EMAC_RX_MODE_RESET);
1608         elink_bits_en(sc, emac_base + EMAC_REG_EMAC_TX_MODE,
1609                       EMAC_TX_MODE_RESET);
1610
1611         /* pause enable/disable */
1612         elink_bits_dis(sc, emac_base + EMAC_REG_EMAC_RX_MODE,
1613                        EMAC_RX_MODE_FLOW_EN);
1614
1615         elink_bits_dis(sc, emac_base + EMAC_REG_EMAC_TX_MODE,
1616                        (EMAC_TX_MODE_EXT_PAUSE_EN |
1617                         EMAC_TX_MODE_FLOW_EN));
1618         if (!(params->feature_config_flags &
1619               ELINK_FEATURE_CONFIG_PFC_ENABLED)) {
1620                 if (vars->flow_ctrl & ELINK_FLOW_CTRL_RX)
1621                         elink_bits_en(sc, emac_base +
1622                                       EMAC_REG_EMAC_RX_MODE,
1623                                       EMAC_RX_MODE_FLOW_EN);
1624
1625                 if (vars->flow_ctrl & ELINK_FLOW_CTRL_TX)
1626                         elink_bits_en(sc, emac_base +
1627                                       EMAC_REG_EMAC_TX_MODE,
1628                                       (EMAC_TX_MODE_EXT_PAUSE_EN |
1629                                        EMAC_TX_MODE_FLOW_EN));
1630         } else
1631                 elink_bits_en(sc, emac_base + EMAC_REG_EMAC_TX_MODE,
1632                               EMAC_TX_MODE_FLOW_EN);
1633
1634         /* KEEP_VLAN_TAG, promiscuous */
1635         val = REG_RD(sc, emac_base + EMAC_REG_EMAC_RX_MODE);
1636         val |= EMAC_RX_MODE_KEEP_VLAN_TAG | EMAC_RX_MODE_PROMISCUOUS;
1637
1638         /* Setting this bit causes MAC control frames (except for pause
1639          * frames) to be passed on for processing. This setting has no
1640          * affect on the operation of the pause frames. This bit effects
1641          * all packets regardless of RX Parser packet sorting logic.
1642          * Turn the PFC off to make sure we are in Xon state before
1643          * enabling it.
1644          */
1645         elink_cb_reg_write(sc, emac_base + EMAC_REG_RX_PFC_MODE, 0);
1646         if (params->feature_config_flags & ELINK_FEATURE_CONFIG_PFC_ENABLED) {
1647                 PMD_DRV_LOG(DEBUG, "PFC is enabled");
1648                 /* Enable PFC again */
1649                 elink_cb_reg_write(sc, emac_base + EMAC_REG_RX_PFC_MODE,
1650                                    EMAC_REG_RX_PFC_MODE_RX_EN |
1651                                    EMAC_REG_RX_PFC_MODE_TX_EN |
1652                                    EMAC_REG_RX_PFC_MODE_PRIORITIES);
1653
1654                 elink_cb_reg_write(sc, emac_base + EMAC_REG_RX_PFC_PARAM,
1655                                    ((0x0101 <<
1656                                      EMAC_REG_RX_PFC_PARAM_OPCODE_BITSHIFT) |
1657                                     (0x00ff <<
1658                                      EMAC_REG_RX_PFC_PARAM_PRIORITY_EN_BITSHIFT)));
1659                 val |= EMAC_RX_MODE_KEEP_MAC_CONTROL;
1660         }
1661         elink_cb_reg_write(sc, emac_base + EMAC_REG_EMAC_RX_MODE, val);
1662
1663         /* Set Loopback */
1664         val = REG_RD(sc, emac_base + EMAC_REG_EMAC_MODE);
1665         if (lb)
1666                 val |= 0x810;
1667         else
1668                 val &= ~0x810;
1669         elink_cb_reg_write(sc, emac_base + EMAC_REG_EMAC_MODE, val);
1670
1671         /* Enable emac */
1672         REG_WR(sc, NIG_REG_NIG_EMAC0_EN + port * 4, 1);
1673
1674         /* Enable emac for jumbo packets */
1675         elink_cb_reg_write(sc, emac_base + EMAC_REG_EMAC_RX_MTU_SIZE,
1676                            (EMAC_RX_MTU_SIZE_JUMBO_ENA |
1677                             (ELINK_ETH_MAX_JUMBO_PACKET_SIZE +
1678                              ELINK_ETH_OVREHEAD)));
1679
1680         /* Strip CRC */
1681         REG_WR(sc, NIG_REG_NIG_INGRESS_EMAC0_NO_CRC + port * 4, 0x1);
1682
1683         /* Disable the NIG in/out to the bmac */
1684         REG_WR(sc, NIG_REG_BMAC0_IN_EN + port * 4, 0x0);
1685         REG_WR(sc, NIG_REG_BMAC0_PAUSE_OUT_EN + port * 4, 0x0);
1686         REG_WR(sc, NIG_REG_BMAC0_OUT_EN + port * 4, 0x0);
1687
1688         /* Enable the NIG in/out to the emac */
1689         REG_WR(sc, NIG_REG_EMAC0_IN_EN + port * 4, 0x1);
1690         val = 0;
1691         if ((params->feature_config_flags &
1692              ELINK_FEATURE_CONFIG_PFC_ENABLED) ||
1693             (vars->flow_ctrl & ELINK_FLOW_CTRL_TX))
1694                 val = 1;
1695
1696         REG_WR(sc, NIG_REG_EMAC0_PAUSE_OUT_EN + port * 4, val);
1697         REG_WR(sc, NIG_REG_EGRESS_EMAC0_OUT_EN + port * 4, 0x1);
1698
1699         REG_WR(sc, NIG_REG_BMAC0_REGS_OUT_EN + port * 4, 0x0);
1700
1701         vars->mac_type = ELINK_MAC_TYPE_EMAC;
1702         return ELINK_STATUS_OK;
1703 }
1704
1705 static void elink_update_pfc_bmac1(struct elink_params *params,
1706                                    struct elink_vars *vars)
1707 {
1708         uint32_t wb_data[2];
1709         struct bnx2x_softc *sc = params->sc;
1710         uint32_t bmac_addr = params->port ? NIG_REG_INGRESS_BMAC1_MEM :
1711             NIG_REG_INGRESS_BMAC0_MEM;
1712
1713         uint32_t val = 0x14;
1714         if ((!(params->feature_config_flags &
1715                ELINK_FEATURE_CONFIG_PFC_ENABLED)) &&
1716             (vars->flow_ctrl & ELINK_FLOW_CTRL_RX))
1717                 /* Enable BigMAC to react on received Pause packets */
1718                 val |= (1 << 5);
1719         wb_data[0] = val;
1720         wb_data[1] = 0;
1721         REG_WR_DMAE(sc, bmac_addr + BIGMAC_REGISTER_RX_CONTROL, wb_data, 2);
1722
1723         /* TX control */
1724         val = 0xc0;
1725         if (!(params->feature_config_flags &
1726               ELINK_FEATURE_CONFIG_PFC_ENABLED) &&
1727             (vars->flow_ctrl & ELINK_FLOW_CTRL_TX))
1728                 val |= 0x800000;
1729         wb_data[0] = val;
1730         wb_data[1] = 0;
1731         REG_WR_DMAE(sc, bmac_addr + BIGMAC_REGISTER_TX_CONTROL, wb_data, 2);
1732 }
1733
1734 static void elink_update_pfc_bmac2(struct elink_params *params,
1735                                    struct elink_vars *vars, uint8_t is_lb)
1736 {
1737         /* Set rx control: Strip CRC and enable BigMAC to relay
1738          * control packets to the system as well
1739          */
1740         uint32_t wb_data[2];
1741         struct bnx2x_softc *sc = params->sc;
1742         uint32_t bmac_addr = params->port ? NIG_REG_INGRESS_BMAC1_MEM :
1743             NIG_REG_INGRESS_BMAC0_MEM;
1744         uint32_t val = 0x14;
1745
1746         if ((!(params->feature_config_flags &
1747                ELINK_FEATURE_CONFIG_PFC_ENABLED)) &&
1748             (vars->flow_ctrl & ELINK_FLOW_CTRL_RX))
1749                 /* Enable BigMAC to react on received Pause packets */
1750                 val |= (1 << 5);
1751         wb_data[0] = val;
1752         wb_data[1] = 0;
1753         REG_WR_DMAE(sc, bmac_addr + BIGMAC2_REGISTER_RX_CONTROL, wb_data, 2);
1754         DELAY(30);
1755
1756         /* Tx control */
1757         val = 0xc0;
1758         if (!(params->feature_config_flags &
1759               ELINK_FEATURE_CONFIG_PFC_ENABLED) &&
1760             (vars->flow_ctrl & ELINK_FLOW_CTRL_TX))
1761                 val |= 0x800000;
1762         wb_data[0] = val;
1763         wb_data[1] = 0;
1764         REG_WR_DMAE(sc, bmac_addr + BIGMAC2_REGISTER_TX_CONTROL, wb_data, 2);
1765
1766         if (params->feature_config_flags & ELINK_FEATURE_CONFIG_PFC_ENABLED) {
1767                 PMD_DRV_LOG(DEBUG, "PFC is enabled");
1768                 /* Enable PFC RX & TX & STATS and set 8 COS  */
1769                 wb_data[0] = 0x0;
1770                 wb_data[0] |= (1 << 0); /* RX */
1771                 wb_data[0] |= (1 << 1); /* TX */
1772                 wb_data[0] |= (1 << 2); /* Force initial Xon */
1773                 wb_data[0] |= (1 << 3); /* 8 cos */
1774                 wb_data[0] |= (1 << 5); /* STATS */
1775                 wb_data[1] = 0;
1776                 REG_WR_DMAE(sc, bmac_addr + BIGMAC2_REGISTER_PFC_CONTROL,
1777                             wb_data, 2);
1778                 /* Clear the force Xon */
1779                 wb_data[0] &= ~(1 << 2);
1780         } else {
1781                 PMD_DRV_LOG(DEBUG, "PFC is disabled");
1782                 /* Disable PFC RX & TX & STATS and set 8 COS */
1783                 wb_data[0] = 0x8;
1784                 wb_data[1] = 0;
1785         }
1786
1787         REG_WR_DMAE(sc, bmac_addr + BIGMAC2_REGISTER_PFC_CONTROL, wb_data, 2);
1788
1789         /* Set Time (based unit is 512 bit time) between automatic
1790          * re-sending of PP packets amd enable automatic re-send of
1791          * Per-Priroity Packet as long as pp_gen is asserted and
1792          * pp_disable is low.
1793          */
1794         val = 0x8000;
1795         if (params->feature_config_flags & ELINK_FEATURE_CONFIG_PFC_ENABLED)
1796                 val |= (1 << 16);       /* enable automatic re-send */
1797
1798         wb_data[0] = val;
1799         wb_data[1] = 0;
1800         REG_WR_DMAE(sc, bmac_addr + BIGMAC2_REGISTER_TX_PAUSE_CONTROL,
1801                     wb_data, 2);
1802
1803         /* mac control */
1804         val = 0x3;              /* Enable RX and TX */
1805         if (is_lb) {
1806                 val |= 0x4;     /* Local loopback */
1807                 PMD_DRV_LOG(DEBUG, "enable bmac loopback");
1808         }
1809         /* When PFC enabled, Pass pause frames towards the NIG. */
1810         if (params->feature_config_flags & ELINK_FEATURE_CONFIG_PFC_ENABLED)
1811                 val |= ((1 << 6) | (1 << 5));
1812
1813         wb_data[0] = val;
1814         wb_data[1] = 0;
1815         REG_WR_DMAE(sc, bmac_addr + BIGMAC2_REGISTER_BMAC_CONTROL, wb_data, 2);
1816 }
1817
1818 /******************************************************************************
1819 * Description:
1820 *  This function is needed because NIG ARB_CREDIT_WEIGHT_X are
1821 *  not continues and ARB_CREDIT_WEIGHT_0 + offset is suitable.
1822 ******************************************************************************/
1823 static elink_status_t elink_pfc_nig_rx_priority_mask(struct bnx2x_softc *sc,
1824                                                      uint8_t cos_entry,
1825                                                      uint32_t priority_mask,
1826                                                      uint8_t port)
1827 {
1828         uint32_t nig_reg_rx_priority_mask_add = 0;
1829
1830         switch (cos_entry) {
1831         case 0:
1832                 nig_reg_rx_priority_mask_add = (port) ?
1833                     NIG_REG_P1_RX_COS0_PRIORITY_MASK :
1834                     NIG_REG_P0_RX_COS0_PRIORITY_MASK;
1835                 break;
1836         case 1:
1837                 nig_reg_rx_priority_mask_add = (port) ?
1838                     NIG_REG_P1_RX_COS1_PRIORITY_MASK :
1839                     NIG_REG_P0_RX_COS1_PRIORITY_MASK;
1840                 break;
1841         case 2:
1842                 nig_reg_rx_priority_mask_add = (port) ?
1843                     NIG_REG_P1_RX_COS2_PRIORITY_MASK :
1844                     NIG_REG_P0_RX_COS2_PRIORITY_MASK;
1845                 break;
1846         case 3:
1847                 if (port)
1848                         return ELINK_STATUS_ERROR;
1849                 nig_reg_rx_priority_mask_add = NIG_REG_P0_RX_COS3_PRIORITY_MASK;
1850                 break;
1851         case 4:
1852                 if (port)
1853                         return ELINK_STATUS_ERROR;
1854                 nig_reg_rx_priority_mask_add = NIG_REG_P0_RX_COS4_PRIORITY_MASK;
1855                 break;
1856         case 5:
1857                 if (port)
1858                         return ELINK_STATUS_ERROR;
1859                 nig_reg_rx_priority_mask_add = NIG_REG_P0_RX_COS5_PRIORITY_MASK;
1860                 break;
1861         }
1862
1863         REG_WR(sc, nig_reg_rx_priority_mask_add, priority_mask);
1864
1865         return ELINK_STATUS_OK;
1866 }
1867
1868 static void elink_update_mng(struct elink_params *params, uint32_t link_status)
1869 {
1870         struct bnx2x_softc *sc = params->sc;
1871
1872         REG_WR(sc, params->shmem_base +
1873                offsetof(struct shmem_region,
1874                         port_mb[params->port].link_status), link_status);
1875 }
1876
1877 static void elink_update_link_attr(struct elink_params *params,
1878                                    uint32_t link_attr)
1879 {
1880         struct bnx2x_softc *sc = params->sc;
1881
1882         if (SHMEM2_HAS(sc, link_attr_sync))
1883                 REG_WR(sc, params->shmem2_base +
1884                        offsetof(struct shmem2_region,
1885                                 link_attr_sync[params->port]), link_attr);
1886 }
1887
1888 static void elink_update_pfc_nig(struct elink_params *params,
1889                                  struct elink_nig_brb_pfc_port_params
1890                                  *nig_params)
1891 {
1892         uint32_t xcm_mask = 0, ppp_enable = 0, pause_enable = 0, llfc_out_en =
1893             0;
1894         uint32_t llfc_enable = 0, xcm_out_en = 0, hwpfc_enable = 0;
1895         uint32_t pkt_priority_to_cos = 0;
1896         struct bnx2x_softc *sc = params->sc;
1897         uint8_t port = params->port;
1898
1899         int set_pfc = params->feature_config_flags &
1900             ELINK_FEATURE_CONFIG_PFC_ENABLED;
1901         PMD_DRV_LOG(DEBUG, "updating pfc nig parameters");
1902
1903         /* When NIG_LLH0_XCM_MASK_REG_LLHX_XCM_MASK_BCN bit is set
1904          * MAC control frames (that are not pause packets)
1905          * will be forwarded to the XCM.
1906          */
1907         xcm_mask = REG_RD(sc, port ? NIG_REG_LLH1_XCM_MASK :
1908                           NIG_REG_LLH0_XCM_MASK);
1909         /* NIG params will override non PFC params, since it's possible to
1910          * do transition from PFC to SAFC
1911          */
1912         if (set_pfc) {
1913                 pause_enable = 0;
1914                 llfc_out_en = 0;
1915                 llfc_enable = 0;
1916                 if (CHIP_IS_E3(sc))
1917                         ppp_enable = 0;
1918                 else
1919                         ppp_enable = 1;
1920                 xcm_mask &= ~(port ? NIG_LLH1_XCM_MASK_REG_LLH1_XCM_MASK_BCN :
1921                               NIG_LLH0_XCM_MASK_REG_LLH0_XCM_MASK_BCN);
1922                 xcm_out_en = 0;
1923                 hwpfc_enable = 1;
1924         } else {
1925                 if (nig_params) {
1926                         llfc_out_en = nig_params->llfc_out_en;
1927                         llfc_enable = nig_params->llfc_enable;
1928                         pause_enable = nig_params->pause_enable;
1929                 } else          /* Default non PFC mode - PAUSE */
1930                         pause_enable = 1;
1931
1932                 xcm_mask |= (port ? NIG_LLH1_XCM_MASK_REG_LLH1_XCM_MASK_BCN :
1933                              NIG_LLH0_XCM_MASK_REG_LLH0_XCM_MASK_BCN);
1934                 xcm_out_en = 1;
1935         }
1936
1937         if (CHIP_IS_E3(sc))
1938                 REG_WR(sc, port ? NIG_REG_BRB1_PAUSE_IN_EN :
1939                        NIG_REG_BRB0_PAUSE_IN_EN, pause_enable);
1940         REG_WR(sc, port ? NIG_REG_LLFC_OUT_EN_1 :
1941                NIG_REG_LLFC_OUT_EN_0, llfc_out_en);
1942         REG_WR(sc, port ? NIG_REG_LLFC_ENABLE_1 :
1943                NIG_REG_LLFC_ENABLE_0, llfc_enable);
1944         REG_WR(sc, port ? NIG_REG_PAUSE_ENABLE_1 :
1945                NIG_REG_PAUSE_ENABLE_0, pause_enable);
1946
1947         REG_WR(sc, port ? NIG_REG_PPP_ENABLE_1 :
1948                NIG_REG_PPP_ENABLE_0, ppp_enable);
1949
1950         REG_WR(sc, port ? NIG_REG_LLH1_XCM_MASK :
1951                NIG_REG_LLH0_XCM_MASK, xcm_mask);
1952
1953         REG_WR(sc, port ? NIG_REG_LLFC_EGRESS_SRC_ENABLE_1 :
1954                NIG_REG_LLFC_EGRESS_SRC_ENABLE_0, 0x7);
1955
1956         /* Output enable for RX_XCM # IF */
1957         REG_WR(sc, port ? NIG_REG_XCM1_OUT_EN :
1958                NIG_REG_XCM0_OUT_EN, xcm_out_en);
1959
1960         /* HW PFC TX enable */
1961         REG_WR(sc, port ? NIG_REG_P1_HWPFC_ENABLE :
1962                NIG_REG_P0_HWPFC_ENABLE, hwpfc_enable);
1963
1964         if (nig_params) {
1965                 uint8_t i = 0;
1966                 pkt_priority_to_cos = nig_params->pkt_priority_to_cos;
1967
1968                 for (i = 0; i < nig_params->num_of_rx_cos_priority_mask; i++)
1969                         elink_pfc_nig_rx_priority_mask(sc, i,
1970                                                        nig_params->
1971                                                        rx_cos_priority_mask[i],
1972                                                        port);
1973
1974                 REG_WR(sc, port ? NIG_REG_LLFC_HIGH_PRIORITY_CLASSES_1 :
1975                        NIG_REG_LLFC_HIGH_PRIORITY_CLASSES_0,
1976                        nig_params->llfc_high_priority_classes);
1977
1978                 REG_WR(sc, port ? NIG_REG_LLFC_LOW_PRIORITY_CLASSES_1 :
1979                        NIG_REG_LLFC_LOW_PRIORITY_CLASSES_0,
1980                        nig_params->llfc_low_priority_classes);
1981         }
1982         REG_WR(sc, port ? NIG_REG_P1_PKT_PRIORITY_TO_COS :
1983                NIG_REG_P0_PKT_PRIORITY_TO_COS, pkt_priority_to_cos);
1984 }
1985
1986 elink_status_t elink_update_pfc(struct elink_params *params,
1987                                 struct elink_vars *vars,
1988                                 struct elink_nig_brb_pfc_port_params
1989                                 *pfc_params)
1990 {
1991         /* The PFC and pause are orthogonal to one another, meaning when
1992          * PFC is enabled, the pause are disabled, and when PFC is
1993          * disabled, pause are set according to the pause result.
1994          */
1995         uint32_t val;
1996         struct bnx2x_softc *sc = params->sc;
1997         elink_status_t elink_status = ELINK_STATUS_OK;
1998         uint8_t bmac_loopback = (params->loopback_mode == ELINK_LOOPBACK_BMAC);
1999
2000         if (params->feature_config_flags & ELINK_FEATURE_CONFIG_PFC_ENABLED)
2001                 vars->link_status |= LINK_STATUS_PFC_ENABLED;
2002         else
2003                 vars->link_status &= ~LINK_STATUS_PFC_ENABLED;
2004
2005         elink_update_mng(params, vars->link_status);
2006
2007         /* Update NIG params */
2008         elink_update_pfc_nig(params, pfc_params);
2009
2010         if (!vars->link_up)
2011                 return elink_status;
2012
2013         PMD_DRV_LOG(DEBUG, "About to update PFC in BMAC");
2014
2015         if (CHIP_IS_E3(sc)) {
2016                 if (vars->mac_type == ELINK_MAC_TYPE_XMAC)
2017                         elink_update_pfc_xmac(params, vars);
2018         } else {
2019                 val = REG_RD(sc, MISC_REG_RESET_REG_2);
2020                 if ((val &
2021                      (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << params->port))
2022                     == 0) {
2023                         PMD_DRV_LOG(DEBUG, "About to update PFC in EMAC");
2024                         elink_emac_enable(params, vars, 0);
2025                         return elink_status;
2026                 }
2027                 if (CHIP_IS_E2(sc))
2028                         elink_update_pfc_bmac2(params, vars, bmac_loopback);
2029                 else
2030                         elink_update_pfc_bmac1(params, vars);
2031
2032                 val = 0;
2033                 if ((params->feature_config_flags &
2034                      ELINK_FEATURE_CONFIG_PFC_ENABLED) ||
2035                     (vars->flow_ctrl & ELINK_FLOW_CTRL_TX))
2036                         val = 1;
2037                 REG_WR(sc, NIG_REG_BMAC0_PAUSE_OUT_EN + params->port * 4, val);
2038         }
2039         return elink_status;
2040 }
2041
2042 static elink_status_t elink_bmac1_enable(struct elink_params *params,
2043                                          struct elink_vars *vars, uint8_t is_lb)
2044 {
2045         struct bnx2x_softc *sc = params->sc;
2046         uint8_t port = params->port;
2047         uint32_t bmac_addr = port ? NIG_REG_INGRESS_BMAC1_MEM :
2048             NIG_REG_INGRESS_BMAC0_MEM;
2049         uint32_t wb_data[2];
2050         uint32_t val;
2051
2052         PMD_DRV_LOG(DEBUG, "Enabling BigMAC1");
2053
2054         /* XGXS control */
2055         wb_data[0] = 0x3c;
2056         wb_data[1] = 0;
2057         REG_WR_DMAE(sc, bmac_addr + BIGMAC_REGISTER_BMAC_XGXS_CONTROL,
2058                     wb_data, 2);
2059
2060         /* TX MAC SA */
2061         wb_data[0] = ((params->mac_addr[2] << 24) |
2062                       (params->mac_addr[3] << 16) |
2063                       (params->mac_addr[4] << 8) | params->mac_addr[5]);
2064         wb_data[1] = ((params->mac_addr[0] << 8) | params->mac_addr[1]);
2065         REG_WR_DMAE(sc, bmac_addr + BIGMAC_REGISTER_TX_SOURCE_ADDR, wb_data, 2);
2066
2067         /* MAC control */
2068         val = 0x3;
2069         if (is_lb) {
2070                 val |= 0x4;
2071                 PMD_DRV_LOG(DEBUG, "enable bmac loopback");
2072         }
2073         wb_data[0] = val;
2074         wb_data[1] = 0;
2075         REG_WR_DMAE(sc, bmac_addr + BIGMAC_REGISTER_BMAC_CONTROL, wb_data, 2);
2076
2077         /* Set rx mtu */
2078         wb_data[0] = ELINK_ETH_MAX_JUMBO_PACKET_SIZE + ELINK_ETH_OVREHEAD;
2079         wb_data[1] = 0;
2080         REG_WR_DMAE(sc, bmac_addr + BIGMAC_REGISTER_RX_MAX_SIZE, wb_data, 2);
2081
2082         elink_update_pfc_bmac1(params, vars);
2083
2084         /* Set tx mtu */
2085         wb_data[0] = ELINK_ETH_MAX_JUMBO_PACKET_SIZE + ELINK_ETH_OVREHEAD;
2086         wb_data[1] = 0;
2087         REG_WR_DMAE(sc, bmac_addr + BIGMAC_REGISTER_TX_MAX_SIZE, wb_data, 2);
2088
2089         /* Set cnt max size */
2090         wb_data[0] = ELINK_ETH_MAX_JUMBO_PACKET_SIZE + ELINK_ETH_OVREHEAD;
2091         wb_data[1] = 0;
2092         REG_WR_DMAE(sc, bmac_addr + BIGMAC_REGISTER_CNT_MAX_SIZE, wb_data, 2);
2093
2094         /* Configure SAFC */
2095         wb_data[0] = 0x1000200;
2096         wb_data[1] = 0;
2097         REG_WR_DMAE(sc, bmac_addr + BIGMAC_REGISTER_RX_LLFC_MSG_FLDS,
2098                     wb_data, 2);
2099
2100         return ELINK_STATUS_OK;
2101 }
2102
2103 static elink_status_t elink_bmac2_enable(struct elink_params *params,
2104                                          struct elink_vars *vars, uint8_t is_lb)
2105 {
2106         struct bnx2x_softc *sc = params->sc;
2107         uint8_t port = params->port;
2108         uint32_t bmac_addr = port ? NIG_REG_INGRESS_BMAC1_MEM :
2109             NIG_REG_INGRESS_BMAC0_MEM;
2110         uint32_t wb_data[2];
2111
2112         PMD_DRV_LOG(DEBUG, "Enabling BigMAC2");
2113
2114         wb_data[0] = 0;
2115         wb_data[1] = 0;
2116         REG_WR_DMAE(sc, bmac_addr + BIGMAC2_REGISTER_BMAC_CONTROL, wb_data, 2);
2117         DELAY(30);
2118
2119         /* XGXS control: Reset phy HW, MDIO registers, PHY PLL and BMAC */
2120         wb_data[0] = 0x3c;
2121         wb_data[1] = 0;
2122         REG_WR_DMAE(sc, bmac_addr + BIGMAC2_REGISTER_BMAC_XGXS_CONTROL,
2123                     wb_data, 2);
2124
2125         DELAY(30);
2126
2127         /* TX MAC SA */
2128         wb_data[0] = ((params->mac_addr[2] << 24) |
2129                       (params->mac_addr[3] << 16) |
2130                       (params->mac_addr[4] << 8) | params->mac_addr[5]);
2131         wb_data[1] = ((params->mac_addr[0] << 8) | params->mac_addr[1]);
2132         REG_WR_DMAE(sc, bmac_addr + BIGMAC2_REGISTER_TX_SOURCE_ADDR,
2133                     wb_data, 2);
2134
2135         DELAY(30);
2136
2137         /* Configure SAFC */
2138         wb_data[0] = 0x1000200;
2139         wb_data[1] = 0;
2140         REG_WR_DMAE(sc, bmac_addr + BIGMAC2_REGISTER_RX_LLFC_MSG_FLDS,
2141                     wb_data, 2);
2142         DELAY(30);
2143
2144         /* Set RX MTU */
2145         wb_data[0] = ELINK_ETH_MAX_JUMBO_PACKET_SIZE + ELINK_ETH_OVREHEAD;
2146         wb_data[1] = 0;
2147         REG_WR_DMAE(sc, bmac_addr + BIGMAC2_REGISTER_RX_MAX_SIZE, wb_data, 2);
2148         DELAY(30);
2149
2150         /* Set TX MTU */
2151         wb_data[0] = ELINK_ETH_MAX_JUMBO_PACKET_SIZE + ELINK_ETH_OVREHEAD;
2152         wb_data[1] = 0;
2153         REG_WR_DMAE(sc, bmac_addr + BIGMAC2_REGISTER_TX_MAX_SIZE, wb_data, 2);
2154         DELAY(30);
2155         /* Set cnt max size */
2156         wb_data[0] = ELINK_ETH_MAX_JUMBO_PACKET_SIZE + ELINK_ETH_OVREHEAD - 2;
2157         wb_data[1] = 0;
2158         REG_WR_DMAE(sc, bmac_addr + BIGMAC2_REGISTER_CNT_MAX_SIZE, wb_data, 2);
2159         DELAY(30);
2160         elink_update_pfc_bmac2(params, vars, is_lb);
2161
2162         return ELINK_STATUS_OK;
2163 }
2164
2165 static elink_status_t elink_bmac_enable(struct elink_params *params,
2166                                         struct elink_vars *vars,
2167                                         uint8_t is_lb, uint8_t reset_bmac)
2168 {
2169         elink_status_t rc = ELINK_STATUS_OK;
2170         uint8_t port = params->port;
2171         struct bnx2x_softc *sc = params->sc;
2172         uint32_t val;
2173         /* Reset and unreset the BigMac */
2174         if (reset_bmac) {
2175                 REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
2176                        (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port));
2177                 DELAY(1000 * 1);
2178         }
2179
2180         REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET,
2181                (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port));
2182
2183         /* Enable access for bmac registers */
2184         REG_WR(sc, NIG_REG_BMAC0_REGS_OUT_EN + port * 4, 0x1);
2185
2186         /* Enable BMAC according to BMAC type */
2187         if (CHIP_IS_E2(sc))
2188                 rc = elink_bmac2_enable(params, vars, is_lb);
2189         else
2190                 rc = elink_bmac1_enable(params, vars, is_lb);
2191         REG_WR(sc, NIG_REG_XGXS_SERDES0_MODE_SEL + port * 4, 0x1);
2192         REG_WR(sc, NIG_REG_XGXS_LANE_SEL_P0 + port * 4, 0x0);
2193         REG_WR(sc, NIG_REG_EGRESS_EMAC0_PORT + port * 4, 0x0);
2194         val = 0;
2195         if ((params->feature_config_flags &
2196              ELINK_FEATURE_CONFIG_PFC_ENABLED) ||
2197             (vars->flow_ctrl & ELINK_FLOW_CTRL_TX))
2198                 val = 1;
2199         REG_WR(sc, NIG_REG_BMAC0_PAUSE_OUT_EN + port * 4, val);
2200         REG_WR(sc, NIG_REG_EGRESS_EMAC0_OUT_EN + port * 4, 0x0);
2201         REG_WR(sc, NIG_REG_EMAC0_IN_EN + port * 4, 0x0);
2202         REG_WR(sc, NIG_REG_EMAC0_PAUSE_OUT_EN + port * 4, 0x0);
2203         REG_WR(sc, NIG_REG_BMAC0_IN_EN + port * 4, 0x1);
2204         REG_WR(sc, NIG_REG_BMAC0_OUT_EN + port * 4, 0x1);
2205
2206         vars->mac_type = ELINK_MAC_TYPE_BMAC;
2207         return rc;
2208 }
2209
2210 static void elink_set_bmac_rx(struct bnx2x_softc *sc, uint8_t port, uint8_t en)
2211 {
2212         uint32_t bmac_addr = port ? NIG_REG_INGRESS_BMAC1_MEM :
2213             NIG_REG_INGRESS_BMAC0_MEM;
2214         uint32_t wb_data[2];
2215         uint32_t nig_bmac_enable =
2216             REG_RD(sc, NIG_REG_BMAC0_REGS_OUT_EN + port * 4);
2217
2218         if (CHIP_IS_E2(sc))
2219                 bmac_addr += BIGMAC2_REGISTER_BMAC_CONTROL;
2220         else
2221                 bmac_addr += BIGMAC_REGISTER_BMAC_CONTROL;
2222         /* Only if the bmac is out of reset */
2223         if (REG_RD(sc, MISC_REG_RESET_REG_2) &
2224             (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port) && nig_bmac_enable) {
2225                 /* Clear Rx Enable bit in BMAC_CONTROL register */
2226                 REG_RD_DMAE(sc, bmac_addr, wb_data, 2);
2227                 if (en)
2228                         wb_data[0] |= ELINK_BMAC_CONTROL_RX_ENABLE;
2229                 else
2230                         wb_data[0] &= ~ELINK_BMAC_CONTROL_RX_ENABLE;
2231                 REG_WR_DMAE(sc, bmac_addr, wb_data, 2);
2232                 DELAY(1000 * 1);
2233         }
2234 }
2235
2236 static elink_status_t elink_pbf_update(struct elink_params *params,
2237                                        uint32_t flow_ctrl, uint32_t line_speed)
2238 {
2239         struct bnx2x_softc *sc = params->sc;
2240         uint8_t port = params->port;
2241         uint32_t init_crd, crd;
2242         uint32_t count = 1000;
2243
2244         /* Disable port */
2245         REG_WR(sc, PBF_REG_DISABLE_NEW_TASK_PROC_P0 + port * 4, 0x1);
2246
2247         /* Wait for init credit */
2248         init_crd = REG_RD(sc, PBF_REG_P0_INIT_CRD + port * 4);
2249         crd = REG_RD(sc, PBF_REG_P0_CREDIT + port * 8);
2250         PMD_DRV_LOG(DEBUG, "init_crd 0x%x  crd 0x%x", init_crd, crd);
2251
2252         while ((init_crd != crd) && count) {
2253                 DELAY(1000 * 5);
2254                 crd = REG_RD(sc, PBF_REG_P0_CREDIT + port * 8);
2255                 count--;
2256         }
2257         crd = REG_RD(sc, PBF_REG_P0_CREDIT + port * 8);
2258         if (init_crd != crd) {
2259                 PMD_DRV_LOG(DEBUG, "BUG! init_crd 0x%x != crd 0x%x",
2260                             init_crd, crd);
2261                 return ELINK_STATUS_ERROR;
2262         }
2263
2264         if (flow_ctrl & ELINK_FLOW_CTRL_RX ||
2265             line_speed == ELINK_SPEED_10 ||
2266             line_speed == ELINK_SPEED_100 ||
2267             line_speed == ELINK_SPEED_1000 || line_speed == ELINK_SPEED_2500) {
2268                 REG_WR(sc, PBF_REG_P0_PAUSE_ENABLE + port * 4, 1);
2269                 /* Update threshold */
2270                 REG_WR(sc, PBF_REG_P0_ARB_THRSH + port * 4, 0);
2271                 /* Update init credit */
2272                 init_crd = 778; /* (800-18-4) */
2273
2274         } else {
2275                 uint32_t thresh = (ELINK_ETH_MAX_JUMBO_PACKET_SIZE +
2276                                    ELINK_ETH_OVREHEAD) / 16;
2277                 REG_WR(sc, PBF_REG_P0_PAUSE_ENABLE + port * 4, 0);
2278                 /* Update threshold */
2279                 REG_WR(sc, PBF_REG_P0_ARB_THRSH + port * 4, thresh);
2280                 /* Update init credit */
2281                 switch (line_speed) {
2282                 case ELINK_SPEED_10000:
2283                         init_crd = thresh + 553 - 22;
2284                         break;
2285                 default:
2286                         PMD_DRV_LOG(DEBUG, "Invalid line_speed 0x%x",
2287                                     line_speed);
2288                         return ELINK_STATUS_ERROR;
2289                 }
2290         }
2291         REG_WR(sc, PBF_REG_P0_INIT_CRD + port * 4, init_crd);
2292         PMD_DRV_LOG(DEBUG, "PBF updated to speed %d credit %d",
2293                     line_speed, init_crd);
2294
2295         /* Probe the credit changes */
2296         REG_WR(sc, PBF_REG_INIT_P0 + port * 4, 0x1);
2297         DELAY(1000 * 5);
2298         REG_WR(sc, PBF_REG_INIT_P0 + port * 4, 0x0);
2299
2300         /* Enable port */
2301         REG_WR(sc, PBF_REG_DISABLE_NEW_TASK_PROC_P0 + port * 4, 0x0);
2302         return ELINK_STATUS_OK;
2303 }
2304
2305 /**
2306  * elink_get_emac_base - retrive emac base address
2307  *
2308  * @bp:                 driver handle
2309  * @mdc_mdio_access:    access type
2310  * @port:               port id
2311  *
2312  * This function selects the MDC/MDIO access (through emac0 or
2313  * emac1) depend on the mdc_mdio_access, port, port swapped. Each
2314  * phy has a default access mode, which could also be overridden
2315  * by nvram configuration. This parameter, whether this is the
2316  * default phy configuration, or the nvram overrun
2317  * configuration, is passed here as mdc_mdio_access and selects
2318  * the emac_base for the CL45 read/writes operations
2319  */
2320 static uint32_t elink_get_emac_base(struct bnx2x_softc *sc,
2321                                     uint32_t mdc_mdio_access, uint8_t port)
2322 {
2323         uint32_t emac_base = 0;
2324         switch (mdc_mdio_access) {
2325         case SHARED_HW_CFG_MDC_MDIO_ACCESS1_PHY_TYPE:
2326                 break;
2327         case SHARED_HW_CFG_MDC_MDIO_ACCESS1_EMAC0:
2328                 if (REG_RD(sc, NIG_REG_PORT_SWAP))
2329                         emac_base = GRCBASE_EMAC1;
2330                 else
2331                         emac_base = GRCBASE_EMAC0;
2332                 break;
2333         case SHARED_HW_CFG_MDC_MDIO_ACCESS1_EMAC1:
2334                 if (REG_RD(sc, NIG_REG_PORT_SWAP))
2335                         emac_base = GRCBASE_EMAC0;
2336                 else
2337                         emac_base = GRCBASE_EMAC1;
2338                 break;
2339         case SHARED_HW_CFG_MDC_MDIO_ACCESS1_BOTH:
2340                 emac_base = (port) ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
2341                 break;
2342         case SHARED_HW_CFG_MDC_MDIO_ACCESS1_SWAPPED:
2343                 emac_base = (port) ? GRCBASE_EMAC0 : GRCBASE_EMAC1;
2344                 break;
2345         default:
2346                 break;
2347         }
2348         return emac_base;
2349
2350 }
2351
2352 /******************************************************************/
2353 /*                      CL22 access functions                     */
2354 /******************************************************************/
2355 static elink_status_t elink_cl22_write(struct bnx2x_softc *sc,
2356                                        struct elink_phy *phy,
2357                                        uint16_t reg, uint16_t val)
2358 {
2359         uint32_t tmp, mode;
2360         uint8_t i;
2361         elink_status_t rc = ELINK_STATUS_OK;
2362         /* Switch to CL22 */
2363         mode = REG_RD(sc, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE);
2364         REG_WR(sc, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE,
2365                mode & ~EMAC_MDIO_MODE_CLAUSE_45);
2366
2367         /* Address */
2368         tmp = ((phy->addr << 21) | (reg << 16) | val |
2369                EMAC_MDIO_COMM_COMMAND_WRITE_22 | EMAC_MDIO_COMM_START_BUSY);
2370         REG_WR(sc, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, tmp);
2371
2372         for (i = 0; i < 50; i++) {
2373                 DELAY(10);
2374
2375                 tmp = REG_RD(sc, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM);
2376                 if (!(tmp & EMAC_MDIO_COMM_START_BUSY)) {
2377                         DELAY(5);
2378                         break;
2379                 }
2380         }
2381         if (tmp & EMAC_MDIO_COMM_START_BUSY) {
2382                 PMD_DRV_LOG(DEBUG, "write phy register failed");
2383                 rc = ELINK_STATUS_TIMEOUT;
2384         }
2385         REG_WR(sc, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE, mode);
2386         return rc;
2387 }
2388
2389 static elink_status_t elink_cl22_read(struct bnx2x_softc *sc,
2390                                       struct elink_phy *phy,
2391                                       uint16_t reg, uint16_t * ret_val)
2392 {
2393         uint32_t val, mode;
2394         uint16_t i;
2395         elink_status_t rc = ELINK_STATUS_OK;
2396
2397         /* Switch to CL22 */
2398         mode = REG_RD(sc, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE);
2399         REG_WR(sc, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE,
2400                mode & ~EMAC_MDIO_MODE_CLAUSE_45);
2401
2402         /* Address */
2403         val = ((phy->addr << 21) | (reg << 16) |
2404                EMAC_MDIO_COMM_COMMAND_READ_22 | EMAC_MDIO_COMM_START_BUSY);
2405         REG_WR(sc, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, val);
2406
2407         for (i = 0; i < 50; i++) {
2408                 DELAY(10);
2409
2410                 val = REG_RD(sc, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM);
2411                 if (!(val & EMAC_MDIO_COMM_START_BUSY)) {
2412                         *ret_val = (uint16_t) (val & EMAC_MDIO_COMM_DATA);
2413                         DELAY(5);
2414                         break;
2415                 }
2416         }
2417         if (val & EMAC_MDIO_COMM_START_BUSY) {
2418                 PMD_DRV_LOG(DEBUG, "read phy register failed");
2419
2420                 *ret_val = 0;
2421                 rc = ELINK_STATUS_TIMEOUT;
2422         }
2423         REG_WR(sc, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE, mode);
2424         return rc;
2425 }
2426
2427 /******************************************************************/
2428 /*                      CL45 access functions                     */
2429 /******************************************************************/
2430 static elink_status_t elink_cl45_read(struct bnx2x_softc *sc,
2431                                       struct elink_phy *phy, uint8_t devad,
2432                                       uint16_t reg, uint16_t * ret_val)
2433 {
2434         uint32_t val;
2435         uint16_t i;
2436         elink_status_t rc = ELINK_STATUS_OK;
2437         if (phy->flags & ELINK_FLAGS_MDC_MDIO_WA_G) {
2438                 elink_set_mdio_clk(sc, phy->mdio_ctrl);
2439         }
2440
2441         if (phy->flags & ELINK_FLAGS_MDC_MDIO_WA_B0)
2442                 elink_bits_en(sc, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_STATUS,
2443                               EMAC_MDIO_STATUS_10MB);
2444         /* Address */
2445         val = ((phy->addr << 21) | (devad << 16) | reg |
2446                EMAC_MDIO_COMM_COMMAND_ADDRESS | EMAC_MDIO_COMM_START_BUSY);
2447         REG_WR(sc, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, val);
2448
2449         for (i = 0; i < 50; i++) {
2450                 DELAY(10);
2451
2452                 val = REG_RD(sc, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM);
2453                 if (!(val & EMAC_MDIO_COMM_START_BUSY)) {
2454                         DELAY(5);
2455                         break;
2456                 }
2457         }
2458         if (val & EMAC_MDIO_COMM_START_BUSY) {
2459                 PMD_DRV_LOG(DEBUG, "read phy register failed");
2460                 elink_cb_event_log(sc, ELINK_LOG_ID_MDIO_ACCESS_TIMEOUT);       // "MDC/MDIO access timeout"
2461
2462                 *ret_val = 0;
2463                 rc = ELINK_STATUS_TIMEOUT;
2464         } else {
2465                 /* Data */
2466                 val = ((phy->addr << 21) | (devad << 16) |
2467                        EMAC_MDIO_COMM_COMMAND_READ_45 |
2468                        EMAC_MDIO_COMM_START_BUSY);
2469                 REG_WR(sc, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, val);
2470
2471                 for (i = 0; i < 50; i++) {
2472                         DELAY(10);
2473
2474                         val = REG_RD(sc, phy->mdio_ctrl +
2475                                      EMAC_REG_EMAC_MDIO_COMM);
2476                         if (!(val & EMAC_MDIO_COMM_START_BUSY)) {
2477                                 *ret_val =
2478                                     (uint16_t) (val & EMAC_MDIO_COMM_DATA);
2479                                 break;
2480                         }
2481                 }
2482                 if (val & EMAC_MDIO_COMM_START_BUSY) {
2483                         PMD_DRV_LOG(DEBUG, "read phy register failed");
2484                         elink_cb_event_log(sc, ELINK_LOG_ID_MDIO_ACCESS_TIMEOUT);       // "MDC/MDIO access timeout"
2485
2486                         *ret_val = 0;
2487                         rc = ELINK_STATUS_TIMEOUT;
2488                 }
2489         }
2490         /* Work around for E3 A0 */
2491         if (phy->flags & ELINK_FLAGS_MDC_MDIO_WA) {
2492                 phy->flags ^= ELINK_FLAGS_DUMMY_READ;
2493                 if (phy->flags & ELINK_FLAGS_DUMMY_READ) {
2494                         uint16_t temp_val;
2495                         elink_cl45_read(sc, phy, devad, 0xf, &temp_val);
2496                 }
2497         }
2498
2499         if (phy->flags & ELINK_FLAGS_MDC_MDIO_WA_B0)
2500                 elink_bits_dis(sc, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_STATUS,
2501                                EMAC_MDIO_STATUS_10MB);
2502         return rc;
2503 }
2504
2505 static elink_status_t elink_cl45_write(struct bnx2x_softc *sc,
2506                                        struct elink_phy *phy, uint8_t devad,
2507                                        uint16_t reg, uint16_t val)
2508 {
2509         uint32_t tmp;
2510         uint8_t i;
2511         elink_status_t rc = ELINK_STATUS_OK;
2512         if (phy->flags & ELINK_FLAGS_MDC_MDIO_WA_G) {
2513                 elink_set_mdio_clk(sc, phy->mdio_ctrl);
2514         }
2515
2516         if (phy->flags & ELINK_FLAGS_MDC_MDIO_WA_B0)
2517                 elink_bits_en(sc, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_STATUS,
2518                               EMAC_MDIO_STATUS_10MB);
2519
2520         /* Address */
2521         tmp = ((phy->addr << 21) | (devad << 16) | reg |
2522                EMAC_MDIO_COMM_COMMAND_ADDRESS | EMAC_MDIO_COMM_START_BUSY);
2523         REG_WR(sc, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, tmp);
2524
2525         for (i = 0; i < 50; i++) {
2526                 DELAY(10);
2527
2528                 tmp = REG_RD(sc, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM);
2529                 if (!(tmp & EMAC_MDIO_COMM_START_BUSY)) {
2530                         DELAY(5);
2531                         break;
2532                 }
2533         }
2534         if (tmp & EMAC_MDIO_COMM_START_BUSY) {
2535                 PMD_DRV_LOG(DEBUG, "write phy register failed");
2536                 elink_cb_event_log(sc, ELINK_LOG_ID_MDIO_ACCESS_TIMEOUT);       // "MDC/MDIO access timeout"
2537
2538                 rc = ELINK_STATUS_TIMEOUT;
2539         } else {
2540                 /* Data */
2541                 tmp = ((phy->addr << 21) | (devad << 16) | val |
2542                        EMAC_MDIO_COMM_COMMAND_WRITE_45 |
2543                        EMAC_MDIO_COMM_START_BUSY);
2544                 REG_WR(sc, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, tmp);
2545
2546                 for (i = 0; i < 50; i++) {
2547                         DELAY(10);
2548
2549                         tmp = REG_RD(sc, phy->mdio_ctrl +
2550                                      EMAC_REG_EMAC_MDIO_COMM);
2551                         if (!(tmp & EMAC_MDIO_COMM_START_BUSY)) {
2552                                 DELAY(5);
2553                                 break;
2554                         }
2555                 }
2556                 if (tmp & EMAC_MDIO_COMM_START_BUSY) {
2557                         PMD_DRV_LOG(DEBUG, "write phy register failed");
2558                         elink_cb_event_log(sc, ELINK_LOG_ID_MDIO_ACCESS_TIMEOUT);       // "MDC/MDIO access timeout"
2559
2560                         rc = ELINK_STATUS_TIMEOUT;
2561                 }
2562         }
2563         /* Work around for E3 A0 */
2564         if (phy->flags & ELINK_FLAGS_MDC_MDIO_WA) {
2565                 phy->flags ^= ELINK_FLAGS_DUMMY_READ;
2566                 if (phy->flags & ELINK_FLAGS_DUMMY_READ) {
2567                         uint16_t temp_val;
2568                         elink_cl45_read(sc, phy, devad, 0xf, &temp_val);
2569                 }
2570         }
2571         if (phy->flags & ELINK_FLAGS_MDC_MDIO_WA_B0)
2572                 elink_bits_dis(sc, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_STATUS,
2573                                EMAC_MDIO_STATUS_10MB);
2574         return rc;
2575 }
2576
2577 /******************************************************************/
2578 /*                      EEE section                                */
2579 /******************************************************************/
2580 static uint8_t elink_eee_has_cap(struct elink_params *params)
2581 {
2582         struct bnx2x_softc *sc = params->sc;
2583
2584         if (REG_RD(sc, params->shmem2_base) <=
2585             offsetof(struct shmem2_region, eee_status[params->port]))
2586                  return 0;
2587
2588         return 1;
2589 }
2590
2591 static elink_status_t elink_eee_nvram_to_time(uint32_t nvram_mode,
2592                                               uint32_t * idle_timer)
2593 {
2594         switch (nvram_mode) {
2595         case PORT_FEAT_CFG_EEE_POWER_MODE_BALANCED:
2596                 *idle_timer = ELINK_EEE_MODE_NVRAM_BALANCED_TIME;
2597                 break;
2598         case PORT_FEAT_CFG_EEE_POWER_MODE_AGGRESSIVE:
2599                 *idle_timer = ELINK_EEE_MODE_NVRAM_AGGRESSIVE_TIME;
2600                 break;
2601         case PORT_FEAT_CFG_EEE_POWER_MODE_LOW_LATENCY:
2602                 *idle_timer = ELINK_EEE_MODE_NVRAM_LATENCY_TIME;
2603                 break;
2604         default:
2605                 *idle_timer = 0;
2606                 break;
2607         }
2608
2609         return ELINK_STATUS_OK;
2610 }
2611
2612 static elink_status_t elink_eee_time_to_nvram(uint32_t idle_timer,
2613                                               uint32_t * nvram_mode)
2614 {
2615         switch (idle_timer) {
2616         case ELINK_EEE_MODE_NVRAM_BALANCED_TIME:
2617                 *nvram_mode = PORT_FEAT_CFG_EEE_POWER_MODE_BALANCED;
2618                 break;
2619         case ELINK_EEE_MODE_NVRAM_AGGRESSIVE_TIME:
2620                 *nvram_mode = PORT_FEAT_CFG_EEE_POWER_MODE_AGGRESSIVE;
2621                 break;
2622         case ELINK_EEE_MODE_NVRAM_LATENCY_TIME:
2623                 *nvram_mode = PORT_FEAT_CFG_EEE_POWER_MODE_LOW_LATENCY;
2624                 break;
2625         default:
2626                 *nvram_mode = PORT_FEAT_CFG_EEE_POWER_MODE_DISABLED;
2627                 break;
2628         }
2629
2630         return ELINK_STATUS_OK;
2631 }
2632
2633 static uint32_t elink_eee_calc_timer(struct elink_params *params)
2634 {
2635         uint32_t eee_mode, eee_idle;
2636         struct bnx2x_softc *sc = params->sc;
2637
2638         if (params->eee_mode & ELINK_EEE_MODE_OVERRIDE_NVRAM) {
2639                 if (params->eee_mode & ELINK_EEE_MODE_OUTPUT_TIME) {
2640                         /* time value in eee_mode --> used directly */
2641                         eee_idle = params->eee_mode & ELINK_EEE_MODE_TIMER_MASK;
2642                 } else {
2643                         /* hsi value in eee_mode --> time */
2644                         if (elink_eee_nvram_to_time(params->eee_mode &
2645                                                     ELINK_EEE_MODE_NVRAM_MASK,
2646                                                     &eee_idle))
2647                                 return 0;
2648                 }
2649         } else {
2650                 /* hsi values in nvram --> time */
2651                 eee_mode = ((REG_RD(sc, params->shmem_base +
2652                                     offsetof(struct shmem_region,
2653                                              dev_info.port_feature_config
2654                                              [params->
2655                                               port].eee_power_mode)) &
2656                              PORT_FEAT_CFG_EEE_POWER_MODE_MASK) >>
2657                             PORT_FEAT_CFG_EEE_POWER_MODE_SHIFT);
2658
2659                 if (elink_eee_nvram_to_time(eee_mode, &eee_idle))
2660                         return 0;
2661         }
2662
2663         return eee_idle;
2664 }
2665
2666 static elink_status_t elink_eee_set_timers(struct elink_params *params,
2667                                            struct elink_vars *vars)
2668 {
2669         uint32_t eee_idle = 0, eee_mode;
2670         struct bnx2x_softc *sc = params->sc;
2671
2672         eee_idle = elink_eee_calc_timer(params);
2673
2674         if (eee_idle) {
2675                 REG_WR(sc, MISC_REG_CPMU_LP_IDLE_THR_P0 + (params->port << 2),
2676                        eee_idle);
2677         } else if ((params->eee_mode & ELINK_EEE_MODE_ENABLE_LPI) &&
2678                    (params->eee_mode & ELINK_EEE_MODE_OVERRIDE_NVRAM) &&
2679                    (params->eee_mode & ELINK_EEE_MODE_OUTPUT_TIME)) {
2680                 PMD_DRV_LOG(DEBUG, "Error: Tx LPI is enabled with timer 0");
2681                 return ELINK_STATUS_ERROR;
2682         }
2683
2684         vars->eee_status &= ~(SHMEM_EEE_TIMER_MASK | SHMEM_EEE_TIME_OUTPUT_BIT);
2685         if (params->eee_mode & ELINK_EEE_MODE_OUTPUT_TIME) {
2686                 /* eee_idle in 1u --> eee_status in 16u */
2687                 eee_idle >>= 4;
2688                 vars->eee_status |= (eee_idle & SHMEM_EEE_TIMER_MASK) |
2689                     SHMEM_EEE_TIME_OUTPUT_BIT;
2690         } else {
2691                 if (elink_eee_time_to_nvram(eee_idle, &eee_mode))
2692                         return ELINK_STATUS_ERROR;
2693                 vars->eee_status |= eee_mode;
2694         }
2695
2696         return ELINK_STATUS_OK;
2697 }
2698
2699 static elink_status_t elink_eee_initial_config(struct elink_params *params,
2700                                                struct elink_vars *vars,
2701                                                uint8_t mode)
2702 {
2703         vars->eee_status |= ((uint32_t) mode) << SHMEM_EEE_SUPPORTED_SHIFT;
2704
2705         /* Propagate params' bits --> vars (for migration exposure) */
2706         if (params->eee_mode & ELINK_EEE_MODE_ENABLE_LPI)
2707                 vars->eee_status |= SHMEM_EEE_LPI_REQUESTED_BIT;
2708         else
2709                 vars->eee_status &= ~SHMEM_EEE_LPI_REQUESTED_BIT;
2710
2711         if (params->eee_mode & ELINK_EEE_MODE_ADV_LPI)
2712                 vars->eee_status |= SHMEM_EEE_REQUESTED_BIT;
2713         else
2714                 vars->eee_status &= ~SHMEM_EEE_REQUESTED_BIT;
2715
2716         return elink_eee_set_timers(params, vars);
2717 }
2718
2719 static elink_status_t elink_eee_disable(struct elink_phy *phy,
2720                                         struct elink_params *params,
2721                                         struct elink_vars *vars)
2722 {
2723         struct bnx2x_softc *sc = params->sc;
2724
2725         /* Make Certain LPI is disabled */
2726         REG_WR(sc, MISC_REG_CPMU_LP_FW_ENABLE_P0 + (params->port << 2), 0);
2727
2728         elink_cl45_write(sc, phy, MDIO_AN_DEVAD, MDIO_AN_REG_EEE_ADV, 0x0);
2729
2730         vars->eee_status &= ~SHMEM_EEE_ADV_STATUS_MASK;
2731
2732         return ELINK_STATUS_OK;
2733 }
2734
2735 static elink_status_t elink_eee_advertise(struct elink_phy *phy,
2736                                           struct elink_params *params,
2737                                           struct elink_vars *vars,
2738                                           uint8_t modes)
2739 {
2740         struct bnx2x_softc *sc = params->sc;
2741         uint16_t val = 0;
2742
2743         /* Mask events preventing LPI generation */
2744         REG_WR(sc, MISC_REG_CPMU_LP_MASK_EXT_P0 + (params->port << 2), 0xfc20);
2745
2746         if (modes & SHMEM_EEE_10G_ADV) {
2747                 PMD_DRV_LOG(DEBUG, "Advertise 10GBase-T EEE");
2748                 val |= 0x8;
2749         }
2750         if (modes & SHMEM_EEE_1G_ADV) {
2751                 PMD_DRV_LOG(DEBUG, "Advertise 1GBase-T EEE");
2752                 val |= 0x4;
2753         }
2754
2755         elink_cl45_write(sc, phy, MDIO_AN_DEVAD, MDIO_AN_REG_EEE_ADV, val);
2756
2757         vars->eee_status &= ~SHMEM_EEE_ADV_STATUS_MASK;
2758         vars->eee_status |= (modes << SHMEM_EEE_ADV_STATUS_SHIFT);
2759
2760         return ELINK_STATUS_OK;
2761 }
2762
2763 static void elink_update_mng_eee(struct elink_params *params,
2764                                  uint32_t eee_status)
2765 {
2766         struct bnx2x_softc *sc = params->sc;
2767
2768         if (elink_eee_has_cap(params))
2769                 REG_WR(sc, params->shmem2_base +
2770                        offsetof(struct shmem2_region,
2771                                 eee_status[params->port]), eee_status);
2772 }
2773
2774 static void elink_eee_an_resolve(struct elink_phy *phy,
2775                                  struct elink_params *params,
2776                                  struct elink_vars *vars)
2777 {
2778         struct bnx2x_softc *sc = params->sc;
2779         uint16_t adv = 0, lp = 0;
2780         uint32_t lp_adv = 0;
2781         uint8_t neg = 0;
2782
2783         elink_cl45_read(sc, phy, MDIO_AN_DEVAD, MDIO_AN_REG_EEE_ADV, &adv);
2784         elink_cl45_read(sc, phy, MDIO_AN_DEVAD, MDIO_AN_REG_LP_EEE_ADV, &lp);
2785
2786         if (lp & 0x2) {
2787                 lp_adv |= SHMEM_EEE_100M_ADV;
2788                 if (adv & 0x2) {
2789                         if (vars->line_speed == ELINK_SPEED_100)
2790                                 neg = 1;
2791                         PMD_DRV_LOG(DEBUG, "EEE negotiated - 100M");
2792                 }
2793         }
2794         if (lp & 0x14) {
2795                 lp_adv |= SHMEM_EEE_1G_ADV;
2796                 if (adv & 0x14) {
2797                         if (vars->line_speed == ELINK_SPEED_1000)
2798                                 neg = 1;
2799                         PMD_DRV_LOG(DEBUG, "EEE negotiated - 1G");
2800                 }
2801         }
2802         if (lp & 0x68) {
2803                 lp_adv |= SHMEM_EEE_10G_ADV;
2804                 if (adv & 0x68) {
2805                         if (vars->line_speed == ELINK_SPEED_10000)
2806                                 neg = 1;
2807                         PMD_DRV_LOG(DEBUG, "EEE negotiated - 10G");
2808                 }
2809         }
2810
2811         vars->eee_status &= ~SHMEM_EEE_LP_ADV_STATUS_MASK;
2812         vars->eee_status |= (lp_adv << SHMEM_EEE_LP_ADV_STATUS_SHIFT);
2813
2814         if (neg) {
2815                 PMD_DRV_LOG(DEBUG, "EEE is active");
2816                 vars->eee_status |= SHMEM_EEE_ACTIVE_BIT;
2817         }
2818 }
2819
2820 /******************************************************************/
2821 /*                      BSC access functions from E3              */
2822 /******************************************************************/
2823 static void elink_bsc_module_sel(struct elink_params *params)
2824 {
2825         int idx;
2826         uint32_t board_cfg, sfp_ctrl;
2827         uint32_t i2c_pins[I2C_SWITCH_WIDTH], i2c_val[I2C_SWITCH_WIDTH];
2828         struct bnx2x_softc *sc = params->sc;
2829         uint8_t port = params->port;
2830         /* Read I2C output PINs */
2831         board_cfg = REG_RD(sc, params->shmem_base +
2832                            offsetof(struct shmem_region,
2833                                     dev_info.shared_hw_config.board));
2834         i2c_pins[I2C_BSC0] = board_cfg & SHARED_HW_CFG_E3_I2C_MUX0_MASK;
2835         i2c_pins[I2C_BSC1] = (board_cfg & SHARED_HW_CFG_E3_I2C_MUX1_MASK) >>
2836             SHARED_HW_CFG_E3_I2C_MUX1_SHIFT;
2837
2838         /* Read I2C output value */
2839         sfp_ctrl = REG_RD(sc, params->shmem_base +
2840                           offsetof(struct shmem_region,
2841                                    dev_info.port_hw_config[port].
2842                                    e3_cmn_pin_cfg));
2843         i2c_val[I2C_BSC0] = (sfp_ctrl & PORT_HW_CFG_E3_I2C_MUX0_MASK) > 0;
2844         i2c_val[I2C_BSC1] = (sfp_ctrl & PORT_HW_CFG_E3_I2C_MUX1_MASK) > 0;
2845         PMD_DRV_LOG(DEBUG, "Setting BSC switch");
2846         for (idx = 0; idx < I2C_SWITCH_WIDTH; idx++)
2847                 elink_set_cfg_pin(sc, i2c_pins[idx], i2c_val[idx]);
2848 }
2849
2850 static elink_status_t elink_bsc_read(struct elink_params *params,
2851                                      struct bnx2x_softc *sc,
2852                                      uint8_t sl_devid,
2853                                      uint16_t sl_addr,
2854                                      uint8_t lc_addr,
2855                                      uint8_t xfer_cnt, uint32_t * data_array)
2856 {
2857         uint32_t val, i;
2858         elink_status_t rc = ELINK_STATUS_OK;
2859
2860         if (xfer_cnt > 16) {
2861                 PMD_DRV_LOG(DEBUG, "invalid xfer_cnt %d. Max is 16 bytes",
2862                             xfer_cnt);
2863                 return ELINK_STATUS_ERROR;
2864         }
2865         if (params)
2866                 elink_bsc_module_sel(params);
2867
2868         xfer_cnt = 16 - lc_addr;
2869
2870         /* Enable the engine */
2871         val = REG_RD(sc, MCP_REG_MCPR_IMC_COMMAND);
2872         val |= MCPR_IMC_COMMAND_ENABLE;
2873         REG_WR(sc, MCP_REG_MCPR_IMC_COMMAND, val);
2874
2875         /* Program slave device ID */
2876         val = (sl_devid << 16) | sl_addr;
2877         REG_WR(sc, MCP_REG_MCPR_IMC_SLAVE_CONTROL, val);
2878
2879         /* Start xfer with 0 byte to update the address pointer ??? */
2880         val = (MCPR_IMC_COMMAND_ENABLE) |
2881             (MCPR_IMC_COMMAND_WRITE_OP <<
2882              MCPR_IMC_COMMAND_OPERATION_BITSHIFT) |
2883             (lc_addr << MCPR_IMC_COMMAND_TRANSFER_ADDRESS_BITSHIFT) | (0);
2884         REG_WR(sc, MCP_REG_MCPR_IMC_COMMAND, val);
2885
2886         /* Poll for completion */
2887         i = 0;
2888         val = REG_RD(sc, MCP_REG_MCPR_IMC_COMMAND);
2889         while (((val >> MCPR_IMC_COMMAND_IMC_STATUS_BITSHIFT) & 0x3) != 1) {
2890                 DELAY(10);
2891                 val = REG_RD(sc, MCP_REG_MCPR_IMC_COMMAND);
2892                 if (i++ > 1000) {
2893                         PMD_DRV_LOG(DEBUG, "wr 0 byte timed out after %d try",
2894                                     i);
2895                         rc = ELINK_STATUS_TIMEOUT;
2896                         break;
2897                 }
2898         }
2899         if (rc == ELINK_STATUS_TIMEOUT)
2900                 return rc;
2901
2902         /* Start xfer with read op */
2903         val = (MCPR_IMC_COMMAND_ENABLE) |
2904             (MCPR_IMC_COMMAND_READ_OP <<
2905              MCPR_IMC_COMMAND_OPERATION_BITSHIFT) |
2906             (lc_addr << MCPR_IMC_COMMAND_TRANSFER_ADDRESS_BITSHIFT) |
2907             (xfer_cnt);
2908         REG_WR(sc, MCP_REG_MCPR_IMC_COMMAND, val);
2909
2910         /* Poll for completion */
2911         i = 0;
2912         val = REG_RD(sc, MCP_REG_MCPR_IMC_COMMAND);
2913         while (((val >> MCPR_IMC_COMMAND_IMC_STATUS_BITSHIFT) & 0x3) != 1) {
2914                 DELAY(10);
2915                 val = REG_RD(sc, MCP_REG_MCPR_IMC_COMMAND);
2916                 if (i++ > 1000) {
2917                         PMD_DRV_LOG(DEBUG, "rd op timed out after %d try", i);
2918                         rc = ELINK_STATUS_TIMEOUT;
2919                         break;
2920                 }
2921         }
2922         if (rc == ELINK_STATUS_TIMEOUT)
2923                 return rc;
2924
2925         for (i = (lc_addr >> 2); i < 4; i++) {
2926                 data_array[i] = REG_RD(sc, (MCP_REG_MCPR_IMC_DATAREG0 + i * 4));
2927 #ifdef __BIG_ENDIAN
2928                 data_array[i] = ((data_array[i] & 0x000000ff) << 24) |
2929                     ((data_array[i] & 0x0000ff00) << 8) |
2930                     ((data_array[i] & 0x00ff0000) >> 8) |
2931                     ((data_array[i] & 0xff000000) >> 24);
2932 #endif
2933         }
2934         return rc;
2935 }
2936
2937 static void elink_cl45_read_or_write(struct bnx2x_softc *sc,
2938                                      struct elink_phy *phy, uint8_t devad,
2939                                      uint16_t reg, uint16_t or_val)
2940 {
2941         uint16_t val;
2942         elink_cl45_read(sc, phy, devad, reg, &val);
2943         elink_cl45_write(sc, phy, devad, reg, val | or_val);
2944 }
2945
2946 static void elink_cl45_read_and_write(struct bnx2x_softc *sc,
2947                                       struct elink_phy *phy,
2948                                       uint8_t devad, uint16_t reg,
2949                                       uint16_t and_val)
2950 {
2951         uint16_t val;
2952         elink_cl45_read(sc, phy, devad, reg, &val);
2953         elink_cl45_write(sc, phy, devad, reg, val & and_val);
2954 }
2955
2956 static uint8_t elink_get_warpcore_lane(struct elink_params *params)
2957 {
2958         uint8_t lane = 0;
2959         struct bnx2x_softc *sc = params->sc;
2960         uint32_t path_swap, path_swap_ovr;
2961         uint8_t path, port;
2962
2963         path = SC_PATH(sc);
2964         port = params->port;
2965
2966         if (elink_is_4_port_mode(sc)) {
2967                 uint32_t port_swap, port_swap_ovr;
2968
2969                 /* Figure out path swap value */
2970                 path_swap_ovr = REG_RD(sc, MISC_REG_FOUR_PORT_PATH_SWAP_OVWR);
2971                 if (path_swap_ovr & 0x1)
2972                         path_swap = (path_swap_ovr & 0x2);
2973                 else
2974                         path_swap = REG_RD(sc, MISC_REG_FOUR_PORT_PATH_SWAP);
2975
2976                 if (path_swap)
2977                         path = path ^ 1;
2978
2979                 /* Figure out port swap value */
2980                 port_swap_ovr = REG_RD(sc, MISC_REG_FOUR_PORT_PORT_SWAP_OVWR);
2981                 if (port_swap_ovr & 0x1)
2982                         port_swap = (port_swap_ovr & 0x2);
2983                 else
2984                         port_swap = REG_RD(sc, MISC_REG_FOUR_PORT_PORT_SWAP);
2985
2986                 if (port_swap)
2987                         port = port ^ 1;
2988
2989                 lane = (port << 1) + path;
2990         } else {                /* Two port mode - no port swap */
2991
2992                 /* Figure out path swap value */
2993                 path_swap_ovr = REG_RD(sc, MISC_REG_TWO_PORT_PATH_SWAP_OVWR);
2994                 if (path_swap_ovr & 0x1) {
2995                         path_swap = (path_swap_ovr & 0x2);
2996                 } else {
2997                         path_swap = REG_RD(sc, MISC_REG_TWO_PORT_PATH_SWAP);
2998                 }
2999                 if (path_swap)
3000                         path = path ^ 1;
3001
3002                 lane = path << 1;
3003         }
3004         return lane;
3005 }
3006
3007 static void elink_set_aer_mmd(struct elink_params *params,
3008                               struct elink_phy *phy)
3009 {
3010         uint32_t ser_lane;
3011         uint16_t offset, aer_val;
3012         struct bnx2x_softc *sc = params->sc;
3013         ser_lane = ((params->lane_config &
3014                      PORT_HW_CFG_LANE_SWAP_CFG_MASTER_MASK) >>
3015                     PORT_HW_CFG_LANE_SWAP_CFG_MASTER_SHIFT);
3016
3017         offset = (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT) ?
3018             (phy->addr + ser_lane) : 0;
3019
3020         if (USES_WARPCORE(sc)) {
3021                 aer_val = elink_get_warpcore_lane(params);
3022                 /* In Dual-lane mode, two lanes are joined together,
3023                  * so in order to configure them, the AER broadcast method is
3024                  * used here.
3025                  * 0x200 is the broadcast address for lanes 0,1
3026                  * 0x201 is the broadcast address for lanes 2,3
3027                  */
3028                 if (phy->flags & ELINK_FLAGS_WC_DUAL_MODE)
3029                         aer_val = (aer_val >> 1) | 0x200;
3030         } else if (CHIP_IS_E2(sc))
3031                 aer_val = 0x3800 + offset - 1;
3032         else
3033                 aer_val = 0x3800 + offset;
3034
3035         CL22_WR_OVER_CL45(sc, phy, MDIO_REG_BANK_AER_BLOCK,
3036                           MDIO_AER_BLOCK_AER_REG, aer_val);
3037
3038 }
3039
3040 /******************************************************************/
3041 /*                      Internal phy section                      */
3042 /******************************************************************/
3043
3044 static void elink_set_serdes_access(struct bnx2x_softc *sc, uint8_t port)
3045 {
3046         uint32_t emac_base = (port) ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
3047
3048         /* Set Clause 22 */
3049         REG_WR(sc, NIG_REG_SERDES0_CTRL_MD_ST + port * 0x10, 1);
3050         REG_WR(sc, emac_base + EMAC_REG_EMAC_MDIO_COMM, 0x245f8000);
3051         DELAY(500);
3052         REG_WR(sc, emac_base + EMAC_REG_EMAC_MDIO_COMM, 0x245d000f);
3053         DELAY(500);
3054         /* Set Clause 45 */
3055         REG_WR(sc, NIG_REG_SERDES0_CTRL_MD_ST + port * 0x10, 0);
3056 }
3057
3058 static void elink_serdes_deassert(struct bnx2x_softc *sc, uint8_t port)
3059 {
3060         uint32_t val;
3061
3062         PMD_DRV_LOG(DEBUG, "elink_serdes_deassert");
3063
3064         val = ELINK_SERDES_RESET_BITS << (port * 16);
3065
3066         /* Reset and unreset the SerDes/XGXS */
3067         REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_3_CLEAR, val);
3068         DELAY(500);
3069         REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_3_SET, val);
3070
3071         elink_set_serdes_access(sc, port);
3072
3073         REG_WR(sc, NIG_REG_SERDES0_CTRL_MD_DEVAD + port * 0x10,
3074                ELINK_DEFAULT_PHY_DEV_ADDR);
3075 }
3076
3077 static void elink_xgxs_specific_func(struct elink_phy *phy,
3078                                      struct elink_params *params,
3079                                      uint32_t action)
3080 {
3081         struct bnx2x_softc *sc = params->sc;
3082         switch (action) {
3083         case ELINK_PHY_INIT:
3084                 /* Set correct devad */
3085                 REG_WR(sc, NIG_REG_XGXS0_CTRL_MD_ST + params->port * 0x18, 0);
3086                 REG_WR(sc, NIG_REG_XGXS0_CTRL_MD_DEVAD + params->port * 0x18,
3087                        phy->def_md_devad);
3088                 break;
3089         }
3090 }
3091
3092 static void elink_xgxs_deassert(struct elink_params *params)
3093 {
3094         struct bnx2x_softc *sc = params->sc;
3095         uint8_t port;
3096         uint32_t val;
3097         PMD_DRV_LOG(DEBUG, "elink_xgxs_deassert");
3098         port = params->port;
3099
3100         val = ELINK_XGXS_RESET_BITS << (port * 16);
3101
3102         /* Reset and unreset the SerDes/XGXS */
3103         REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_3_CLEAR, val);
3104         DELAY(500);
3105         REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_3_SET, val);
3106         elink_xgxs_specific_func(&params->phy[ELINK_INT_PHY], params,
3107                                  ELINK_PHY_INIT);
3108 }
3109
3110 static void elink_calc_ieee_aneg_adv(struct elink_phy *phy,
3111                                      struct elink_params *params,
3112                                      uint16_t * ieee_fc)
3113 {
3114         *ieee_fc = MDIO_COMBO_IEEE0_AUTO_NEG_ADV_FULL_DUPLEX;
3115         /* Resolve pause mode and advertisement Please refer to Table
3116          * 28B-3 of the 802.3ab-1999 spec
3117          */
3118
3119         switch (phy->req_flow_ctrl) {
3120         case ELINK_FLOW_CTRL_AUTO:
3121                 switch (params->req_fc_auto_adv) {
3122                 case ELINK_FLOW_CTRL_BOTH:
3123                         *ieee_fc |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH;
3124                         break;
3125                 case ELINK_FLOW_CTRL_RX:
3126                 case ELINK_FLOW_CTRL_TX:
3127                         *ieee_fc |=
3128                             MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC;
3129                         break;
3130                 default:
3131                         break;
3132                 }
3133                 break;
3134         case ELINK_FLOW_CTRL_TX:
3135                 *ieee_fc |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC;
3136                 break;
3137
3138         case ELINK_FLOW_CTRL_RX:
3139         case ELINK_FLOW_CTRL_BOTH:
3140                 *ieee_fc |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH;
3141                 break;
3142
3143         case ELINK_FLOW_CTRL_NONE:
3144         default:
3145                 *ieee_fc |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_NONE;
3146                 break;
3147         }
3148         PMD_DRV_LOG(DEBUG, "ieee_fc = 0x%x", *ieee_fc);
3149 }
3150
3151 static void set_phy_vars(struct elink_params *params, struct elink_vars *vars)
3152 {
3153         uint8_t actual_phy_idx, phy_index, link_cfg_idx;
3154         uint8_t phy_config_swapped = params->multi_phy_config &
3155             PORT_HW_CFG_PHY_SWAPPED_ENABLED;
3156         for (phy_index = ELINK_INT_PHY; phy_index < params->num_phys;
3157              phy_index++) {
3158                 link_cfg_idx = ELINK_LINK_CONFIG_IDX(phy_index);
3159                 actual_phy_idx = phy_index;
3160                 if (phy_config_swapped) {
3161                         if (phy_index == ELINK_EXT_PHY1)
3162                                 actual_phy_idx = ELINK_EXT_PHY2;
3163                         else if (phy_index == ELINK_EXT_PHY2)
3164                                 actual_phy_idx = ELINK_EXT_PHY1;
3165                 }
3166                 params->phy[actual_phy_idx].req_flow_ctrl =
3167                     params->req_flow_ctrl[link_cfg_idx];
3168
3169                 params->phy[actual_phy_idx].req_line_speed =
3170                     params->req_line_speed[link_cfg_idx];
3171
3172                 params->phy[actual_phy_idx].speed_cap_mask =
3173                     params->speed_cap_mask[link_cfg_idx];
3174
3175                 params->phy[actual_phy_idx].req_duplex =
3176                     params->req_duplex[link_cfg_idx];
3177
3178                 if (params->req_line_speed[link_cfg_idx] ==
3179                     ELINK_SPEED_AUTO_NEG)
3180                         vars->link_status |= LINK_STATUS_AUTO_NEGOTIATE_ENABLED;
3181
3182                 PMD_DRV_LOG(DEBUG, "req_flow_ctrl %x, req_line_speed %x,"
3183                             " speed_cap_mask %x",
3184                             params->phy[actual_phy_idx].req_flow_ctrl,
3185                             params->phy[actual_phy_idx].req_line_speed,
3186                             params->phy[actual_phy_idx].speed_cap_mask);
3187         }
3188 }
3189
3190 static void elink_ext_phy_set_pause(struct elink_params *params,
3191                                     struct elink_phy *phy,
3192                                     struct elink_vars *vars)
3193 {
3194         uint16_t val;
3195         struct bnx2x_softc *sc = params->sc;
3196         /* Read modify write pause advertizing */
3197         elink_cl45_read(sc, phy, MDIO_AN_DEVAD, MDIO_AN_REG_ADV_PAUSE, &val);
3198
3199         val &= ~MDIO_AN_REG_ADV_PAUSE_BOTH;
3200
3201         /* Please refer to Table 28B-3 of 802.3ab-1999 spec. */
3202         elink_calc_ieee_aneg_adv(phy, params, &vars->ieee_fc);
3203         if ((vars->ieee_fc &
3204              MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC) ==
3205             MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC) {
3206                 val |= MDIO_AN_REG_ADV_PAUSE_ASYMMETRIC;
3207         }
3208         if ((vars->ieee_fc &
3209              MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) ==
3210             MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) {
3211                 val |= MDIO_AN_REG_ADV_PAUSE_PAUSE;
3212         }
3213         PMD_DRV_LOG(DEBUG, "Ext phy AN advertize 0x%x", val);
3214         elink_cl45_write(sc, phy, MDIO_AN_DEVAD, MDIO_AN_REG_ADV_PAUSE, val);
3215 }
3216
3217 static void elink_pause_resolve(struct elink_vars *vars, uint32_t pause_result)
3218 {                               /*  LD      LP   */
3219         switch (pause_result) { /* ASYM P ASYM P */
3220         case 0xb:               /*   1  0   1  1 */
3221                 vars->flow_ctrl = ELINK_FLOW_CTRL_TX;
3222                 break;
3223
3224         case 0xe:               /*   1  1   1  0 */
3225                 vars->flow_ctrl = ELINK_FLOW_CTRL_RX;
3226                 break;
3227
3228         case 0x5:               /*   0  1   0  1 */
3229         case 0x7:               /*   0  1   1  1 */
3230         case 0xd:               /*   1  1   0  1 */
3231         case 0xf:               /*   1  1   1  1 */
3232                 vars->flow_ctrl = ELINK_FLOW_CTRL_BOTH;
3233                 break;
3234
3235         default:
3236                 break;
3237         }
3238         if (pause_result & (1 << 0))
3239                 vars->link_status |= LINK_STATUS_LINK_PARTNER_SYMMETRIC_PAUSE;
3240         if (pause_result & (1 << 1))
3241                 vars->link_status |= LINK_STATUS_LINK_PARTNER_ASYMMETRIC_PAUSE;
3242
3243 }
3244
3245 static void elink_ext_phy_update_adv_fc(struct elink_phy *phy,
3246                                         struct elink_params *params,
3247                                         struct elink_vars *vars)
3248 {
3249         uint16_t ld_pause;      /* local */
3250         uint16_t lp_pause;      /* link partner */
3251         uint16_t pause_result;
3252         struct bnx2x_softc *sc = params->sc;
3253         if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X54618SE) {
3254                 elink_cl22_read(sc, phy, 0x4, &ld_pause);
3255                 elink_cl22_read(sc, phy, 0x5, &lp_pause);
3256         } else if (CHIP_IS_E3(sc) && ELINK_SINGLE_MEDIA_DIRECT(params)) {
3257                 uint8_t lane = elink_get_warpcore_lane(params);
3258                 uint16_t gp_status, gp_mask;
3259                 elink_cl45_read(sc, phy,
3260                                 MDIO_AN_DEVAD, MDIO_WC_REG_GP2_STATUS_GP_2_4,
3261                                 &gp_status);
3262                 gp_mask = (MDIO_WC_REG_GP2_STATUS_GP_2_4_CL73_AN_CMPL |
3263                            MDIO_WC_REG_GP2_STATUS_GP_2_4_CL37_LP_AN_CAP) <<
3264                     lane;
3265                 if ((gp_status & gp_mask) == gp_mask) {
3266                         elink_cl45_read(sc, phy, MDIO_AN_DEVAD,
3267                                         MDIO_AN_REG_ADV_PAUSE, &ld_pause);
3268                         elink_cl45_read(sc, phy, MDIO_AN_DEVAD,
3269                                         MDIO_AN_REG_LP_AUTO_NEG, &lp_pause);
3270                 } else {
3271                         elink_cl45_read(sc, phy, MDIO_AN_DEVAD,
3272                                         MDIO_AN_REG_CL37_FC_LD, &ld_pause);
3273                         elink_cl45_read(sc, phy, MDIO_AN_DEVAD,
3274                                         MDIO_AN_REG_CL37_FC_LP, &lp_pause);
3275                         ld_pause = ((ld_pause &
3276                                      MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH)
3277                                     << 3);
3278                         lp_pause = ((lp_pause &
3279                                      MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH)
3280                                     << 3);
3281                 }
3282         } else {
3283                 elink_cl45_read(sc, phy,
3284                                 MDIO_AN_DEVAD,
3285                                 MDIO_AN_REG_ADV_PAUSE, &ld_pause);
3286                 elink_cl45_read(sc, phy,
3287                                 MDIO_AN_DEVAD,
3288                                 MDIO_AN_REG_LP_AUTO_NEG, &lp_pause);
3289         }
3290         pause_result = (ld_pause & MDIO_AN_REG_ADV_PAUSE_MASK) >> 8;
3291         pause_result |= (lp_pause & MDIO_AN_REG_ADV_PAUSE_MASK) >> 10;
3292         PMD_DRV_LOG(DEBUG, "Ext PHY pause result 0x%x", pause_result);
3293         elink_pause_resolve(vars, pause_result);
3294
3295 }
3296
3297 static uint8_t elink_ext_phy_resolve_fc(struct elink_phy *phy,
3298                                         struct elink_params *params,
3299                                         struct elink_vars *vars)
3300 {
3301         uint8_t ret = 0;
3302         vars->flow_ctrl = ELINK_FLOW_CTRL_NONE;
3303         if (phy->req_flow_ctrl != ELINK_FLOW_CTRL_AUTO) {
3304                 /* Update the advertised flow-controled of LD/LP in AN */
3305                 if (phy->req_line_speed == ELINK_SPEED_AUTO_NEG)
3306                         elink_ext_phy_update_adv_fc(phy, params, vars);
3307                 /* But set the flow-control result as the requested one */
3308                 vars->flow_ctrl = phy->req_flow_ctrl;
3309         } else if (phy->req_line_speed != ELINK_SPEED_AUTO_NEG)
3310                 vars->flow_ctrl = params->req_fc_auto_adv;
3311         else if (vars->link_status & LINK_STATUS_AUTO_NEGOTIATE_COMPLETE) {
3312                 ret = 1;
3313                 elink_ext_phy_update_adv_fc(phy, params, vars);
3314         }
3315         return ret;
3316 }
3317
3318 /******************************************************************/
3319 /*                      Warpcore section                          */
3320 /******************************************************************/
3321 /* The init_internal_warpcore should mirror the xgxs,
3322  * i.e. reset the lane (if needed), set aer for the
3323  * init configuration, and set/clear SGMII flag. Internal
3324  * phy init is done purely in phy_init stage.
3325  */
3326 #define WC_TX_DRIVER(post2, idriver, ipre) \
3327         ((post2 << MDIO_WC_REG_TX0_TX_DRIVER_POST2_COEFF_OFFSET) | \
3328          (idriver << MDIO_WC_REG_TX0_TX_DRIVER_IDRIVER_OFFSET) | \
3329          (ipre << MDIO_WC_REG_TX0_TX_DRIVER_IPRE_DRIVER_OFFSET))
3330
3331 #define WC_TX_FIR(post, main, pre) \
3332         ((post << MDIO_WC_REG_TX_FIR_TAP_POST_TAP_OFFSET) | \
3333          (main << MDIO_WC_REG_TX_FIR_TAP_MAIN_TAP_OFFSET) | \
3334          (pre << MDIO_WC_REG_TX_FIR_TAP_PRE_TAP_OFFSET))
3335
3336 static void elink_warpcore_enable_AN_KR2(struct elink_phy *phy,
3337                                          struct elink_params *params,
3338                                          struct elink_vars *vars)
3339 {
3340         struct bnx2x_softc *sc = params->sc;
3341         uint16_t i;
3342         static struct elink_reg_set reg_set[] = {
3343                 /* Step 1 - Program the TX/RX alignment markers */
3344                 {MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_TX_CTRL5, 0xa157},
3345                 {MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_TX_CTRL7, 0xcbe2},
3346                 {MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_TX_CTRL6, 0x7537},
3347                 {MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_TX_CTRL9, 0xa157},
3348                 {MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_RX_CTRL11, 0xcbe2},
3349                 {MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_RX_CTRL10, 0x7537},
3350                 /* Step 2 - Configure the NP registers */
3351                 {MDIO_WC_DEVAD, MDIO_WC_REG_CL73_USERB0_CTRL, 0x000a},
3352                 {MDIO_WC_DEVAD, MDIO_WC_REG_CL73_BAM_CTRL1, 0x6400},
3353                 {MDIO_WC_DEVAD, MDIO_WC_REG_CL73_BAM_CTRL3, 0x0620},
3354                 {MDIO_WC_DEVAD, MDIO_WC_REG_CL73_BAM_CODE_FIELD, 0x0157},
3355                 {MDIO_WC_DEVAD, MDIO_WC_REG_ETA_CL73_OUI1, 0x6464},
3356                 {MDIO_WC_DEVAD, MDIO_WC_REG_ETA_CL73_OUI2, 0x3150},
3357                 {MDIO_WC_DEVAD, MDIO_WC_REG_ETA_CL73_OUI3, 0x3150},
3358                 {MDIO_WC_DEVAD, MDIO_WC_REG_ETA_CL73_LD_BAM_CODE, 0x0157},
3359                 {MDIO_WC_DEVAD, MDIO_WC_REG_ETA_CL73_LD_UD_CODE, 0x0620}
3360         };
3361         PMD_DRV_LOG(DEBUG, "Enabling 20G-KR2");
3362
3363         elink_cl45_read_or_write(sc, phy, MDIO_WC_DEVAD,
3364                                  MDIO_WC_REG_CL49_USERB0_CTRL, (3 << 6));
3365
3366         for (i = 0; i < ARRAY_SIZE(reg_set); i++)
3367                 elink_cl45_write(sc, phy, reg_set[i].devad, reg_set[i].reg,
3368                                  reg_set[i].val);
3369
3370         /* Start KR2 work-around timer which handles BNX2X8073 link-parner */
3371         vars->link_attr_sync |= LINK_ATTR_SYNC_KR2_ENABLE;
3372         elink_update_link_attr(params, vars->link_attr_sync);
3373 }
3374
3375 static void elink_disable_kr2(struct elink_params *params,
3376                               struct elink_vars *vars, struct elink_phy *phy)
3377 {
3378         struct bnx2x_softc *sc = params->sc;
3379         uint32_t i;
3380         static struct elink_reg_set reg_set[] = {
3381                 /* Step 1 - Program the TX/RX alignment markers */
3382                 {MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_TX_CTRL5, 0x7690},
3383                 {MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_TX_CTRL7, 0xe647},
3384                 {MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_TX_CTRL6, 0xc4f0},
3385                 {MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_TX_CTRL9, 0x7690},
3386                 {MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_RX_CTRL11, 0xe647},
3387                 {MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_RX_CTRL10, 0xc4f0},
3388                 {MDIO_WC_DEVAD, MDIO_WC_REG_CL73_USERB0_CTRL, 0x000c},
3389                 {MDIO_WC_DEVAD, MDIO_WC_REG_CL73_BAM_CTRL1, 0x6000},
3390                 {MDIO_WC_DEVAD, MDIO_WC_REG_CL73_BAM_CTRL3, 0x0000},
3391                 {MDIO_WC_DEVAD, MDIO_WC_REG_CL73_BAM_CODE_FIELD, 0x0002},
3392                 {MDIO_WC_DEVAD, MDIO_WC_REG_ETA_CL73_OUI1, 0x0000},
3393                 {MDIO_WC_DEVAD, MDIO_WC_REG_ETA_CL73_OUI2, 0x0af7},
3394                 {MDIO_WC_DEVAD, MDIO_WC_REG_ETA_CL73_OUI3, 0x0af7},
3395                 {MDIO_WC_DEVAD, MDIO_WC_REG_ETA_CL73_LD_BAM_CODE, 0x0002},
3396                 {MDIO_WC_DEVAD, MDIO_WC_REG_ETA_CL73_LD_UD_CODE, 0x0000}
3397         };
3398         PMD_DRV_LOG(DEBUG, "Disabling 20G-KR2");
3399
3400         for (i = 0; i < ARRAY_SIZE(reg_set); i++)
3401                 elink_cl45_write(sc, phy, reg_set[i].devad, reg_set[i].reg,
3402                                  reg_set[i].val);
3403         vars->link_attr_sync &= ~LINK_ATTR_SYNC_KR2_ENABLE;
3404         elink_update_link_attr(params, vars->link_attr_sync);
3405
3406         vars->check_kr2_recovery_cnt = ELINK_CHECK_KR2_RECOVERY_CNT;
3407 }
3408
3409 static void elink_warpcore_set_lpi_passthrough(struct elink_phy *phy,
3410                                                struct elink_params *params)
3411 {
3412         struct bnx2x_softc *sc = params->sc;
3413
3414         PMD_DRV_LOG(DEBUG, "Configure WC for LPI pass through");
3415         elink_cl45_write(sc, phy, MDIO_WC_DEVAD,
3416                          MDIO_WC_REG_EEE_COMBO_CONTROL0, 0x7c);
3417         elink_cl45_read_or_write(sc, phy, MDIO_WC_DEVAD,
3418                                  MDIO_WC_REG_DIGITAL4_MISC5, 0xc000);
3419 }
3420
3421 static void elink_warpcore_restart_AN_KR(struct elink_phy *phy,
3422                                          struct elink_params *params)
3423 {
3424         /* Restart autoneg on the leading lane only */
3425         struct bnx2x_softc *sc = params->sc;
3426         uint16_t lane = elink_get_warpcore_lane(params);
3427         CL22_WR_OVER_CL45(sc, phy, MDIO_REG_BANK_AER_BLOCK,
3428                           MDIO_AER_BLOCK_AER_REG, lane);
3429         elink_cl45_write(sc, phy, MDIO_AN_DEVAD,
3430                          MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x1200);
3431
3432         /* Restore AER */
3433         elink_set_aer_mmd(params, phy);
3434 }
3435
3436 static void elink_warpcore_enable_AN_KR(struct elink_phy *phy,
3437                                         struct elink_params *params,
3438                                         struct elink_vars *vars)
3439 {
3440         uint16_t lane, i, cl72_ctrl, an_adv = 0;
3441         struct bnx2x_softc *sc = params->sc;
3442         static struct elink_reg_set reg_set[] = {
3443                 {MDIO_WC_DEVAD, MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2, 0x7},
3444                 {MDIO_PMA_DEVAD, MDIO_WC_REG_IEEE0BLK_AUTONEGNP, 0x0},
3445                 {MDIO_WC_DEVAD, MDIO_WC_REG_RX66_CONTROL, 0x7415},
3446                 {MDIO_WC_DEVAD, MDIO_WC_REG_SERDESDIGITAL_MISC2, 0x6190},
3447                 /* Disable Autoneg: re-enable it after adv is done. */
3448                 {MDIO_AN_DEVAD, MDIO_WC_REG_IEEE0BLK_MIICNTL, 0},
3449                 {MDIO_PMA_DEVAD, MDIO_WC_REG_PMD_KR_CONTROL, 0x2},
3450                 {MDIO_WC_DEVAD, MDIO_WC_REG_CL72_USERB0_CL72_TX_FIR_TAP, 0},
3451         };
3452         PMD_DRV_LOG(DEBUG, "Enable Auto Negotiation for KR");
3453         /* Set to default registers that may be overridden by 10G force */
3454         for (i = 0; i < ARRAY_SIZE(reg_set); i++)
3455                 elink_cl45_write(sc, phy, reg_set[i].devad, reg_set[i].reg,
3456                                  reg_set[i].val);
3457
3458         elink_cl45_read(sc, phy, MDIO_WC_DEVAD,
3459                         MDIO_WC_REG_CL72_USERB0_CL72_MISC1_CONTROL, &cl72_ctrl);
3460         cl72_ctrl &= 0x08ff;
3461         cl72_ctrl |= 0x3800;
3462         elink_cl45_write(sc, phy, MDIO_WC_DEVAD,
3463                          MDIO_WC_REG_CL72_USERB0_CL72_MISC1_CONTROL, cl72_ctrl);
3464
3465         /* Check adding advertisement for 1G KX */
3466         if (((vars->line_speed == ELINK_SPEED_AUTO_NEG) &&
3467              (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)) ||
3468             (vars->line_speed == ELINK_SPEED_1000)) {
3469                 uint16_t addr = MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2;
3470                 an_adv |= (1 << 5);
3471
3472                 /* Enable CL37 1G Parallel Detect */
3473                 elink_cl45_read_or_write(sc, phy, MDIO_WC_DEVAD, addr, 0x1);
3474                 PMD_DRV_LOG(DEBUG, "Advertize 1G");
3475         }
3476         if (((vars->line_speed == ELINK_SPEED_AUTO_NEG) &&
3477              (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)) ||
3478             (vars->line_speed == ELINK_SPEED_10000)) {
3479                 /* Check adding advertisement for 10G KR */
3480                 an_adv |= (1 << 7);
3481                 /* Enable 10G Parallel Detect */
3482                 CL22_WR_OVER_CL45(sc, phy, MDIO_REG_BANK_AER_BLOCK,
3483                                   MDIO_AER_BLOCK_AER_REG, 0);
3484
3485                 elink_cl45_write(sc, phy, MDIO_AN_DEVAD,
3486                                  MDIO_WC_REG_PAR_DET_10G_CTRL, 1);
3487                 elink_set_aer_mmd(params, phy);
3488                 PMD_DRV_LOG(DEBUG, "Advertize 10G");
3489         }
3490
3491         /* Set Transmit PMD settings */
3492         lane = elink_get_warpcore_lane(params);
3493         elink_cl45_write(sc, phy, MDIO_WC_DEVAD,
3494                          MDIO_WC_REG_TX0_TX_DRIVER + 0x10 * lane,
3495                          WC_TX_DRIVER(0x02, 0x06, 0x09));
3496         /* Configure the next lane if dual mode */
3497         if (phy->flags & ELINK_FLAGS_WC_DUAL_MODE)
3498                 elink_cl45_write(sc, phy, MDIO_WC_DEVAD,
3499                                  MDIO_WC_REG_TX0_TX_DRIVER + 0x10 * (lane + 1),
3500                                  WC_TX_DRIVER(0x02, 0x06, 0x09));
3501         elink_cl45_write(sc, phy, MDIO_WC_DEVAD,
3502                          MDIO_WC_REG_CL72_USERB0_CL72_OS_DEF_CTRL, 0x03f0);
3503         elink_cl45_write(sc, phy, MDIO_WC_DEVAD,
3504                          MDIO_WC_REG_CL72_USERB0_CL72_2P5_DEF_CTRL, 0x03f0);
3505
3506         /* Advertised speeds */
3507         elink_cl45_write(sc, phy, MDIO_AN_DEVAD,
3508                          MDIO_WC_REG_AN_IEEE1BLK_AN_ADVERTISEMENT1, an_adv);
3509
3510         /* Advertised and set FEC (Forward Error Correction) */
3511         elink_cl45_write(sc, phy, MDIO_AN_DEVAD,
3512                          MDIO_WC_REG_AN_IEEE1BLK_AN_ADVERTISEMENT2,
3513                          (MDIO_WC_REG_AN_IEEE1BLK_AN_ADV2_FEC_ABILITY |
3514                           MDIO_WC_REG_AN_IEEE1BLK_AN_ADV2_FEC_REQ));
3515
3516         /* Enable CL37 BAM */
3517         if (REG_RD(sc, params->shmem_base +
3518                    offsetof(struct shmem_region,
3519                             dev_info.port_hw_config[params->port].
3520                             default_cfg)) &
3521             PORT_HW_CFG_ENABLE_BAM_ON_KR_ENABLED) {
3522                 elink_cl45_read_or_write(sc, phy, MDIO_WC_DEVAD,
3523                                          MDIO_WC_REG_DIGITAL6_MP5_NEXTPAGECTRL,
3524                                          1);
3525                 PMD_DRV_LOG(DEBUG, "Enable CL37 BAM on KR");
3526         }
3527
3528         /* Advertise pause */
3529         elink_ext_phy_set_pause(params, phy, vars);
3530         vars->rx_tx_asic_rst = MAX_KR_LINK_RETRY;
3531         elink_cl45_read_or_write(sc, phy, MDIO_WC_DEVAD,
3532                                  MDIO_WC_REG_DIGITAL5_MISC7, 0x100);
3533
3534         /* Over 1G - AN local device user page 1 */
3535         elink_cl45_write(sc, phy, MDIO_WC_DEVAD,
3536                          MDIO_WC_REG_DIGITAL3_UP1, 0x1f);
3537
3538         if (((phy->req_line_speed == ELINK_SPEED_AUTO_NEG) &&
3539              (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_20G)) ||
3540             (phy->req_line_speed == ELINK_SPEED_20000)) {
3541
3542                 CL22_WR_OVER_CL45(sc, phy, MDIO_REG_BANK_AER_BLOCK,
3543                                   MDIO_AER_BLOCK_AER_REG, lane);
3544
3545                 elink_cl45_read_or_write(sc, phy, MDIO_WC_DEVAD,
3546                                          MDIO_WC_REG_RX1_PCI_CTRL +
3547                                          (0x10 * lane), (1 << 11));
3548
3549                 elink_cl45_write(sc, phy, MDIO_WC_DEVAD,
3550                                  MDIO_WC_REG_XGXS_X2_CONTROL3, 0x7);
3551                 elink_set_aer_mmd(params, phy);
3552
3553                 elink_warpcore_enable_AN_KR2(phy, params, vars);
3554         } else {
3555                 elink_disable_kr2(params, vars, phy);
3556         }
3557
3558         /* Enable Autoneg: only on the main lane */
3559         elink_warpcore_restart_AN_KR(phy, params);
3560 }
3561
3562 static void elink_warpcore_set_10G_KR(struct elink_phy *phy,
3563                                       struct elink_params *params)
3564 {
3565         struct bnx2x_softc *sc = params->sc;
3566         uint16_t val16, i, lane;
3567         static struct elink_reg_set reg_set[] = {
3568                 /* Disable Autoneg */
3569                 {MDIO_WC_DEVAD, MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2, 0x7},
3570                 {MDIO_WC_DEVAD, MDIO_WC_REG_CL72_USERB0_CL72_MISC1_CONTROL,
3571                  0x3f00},
3572                 {MDIO_AN_DEVAD, MDIO_WC_REG_AN_IEEE1BLK_AN_ADVERTISEMENT1, 0},
3573                 {MDIO_AN_DEVAD, MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x0},
3574                 {MDIO_WC_DEVAD, MDIO_WC_REG_DIGITAL3_UP1, 0x1},
3575                 {MDIO_WC_DEVAD, MDIO_WC_REG_DIGITAL5_MISC7, 0xa},
3576                 /* Leave cl72 training enable, needed for KR */
3577                 {MDIO_PMA_DEVAD, MDIO_WC_REG_PMD_KR_CONTROL, 0x2}
3578         };
3579
3580         for (i = 0; i < ARRAY_SIZE(reg_set); i++)
3581                 elink_cl45_write(sc, phy, reg_set[i].devad, reg_set[i].reg,
3582                                  reg_set[i].val);
3583
3584         lane = elink_get_warpcore_lane(params);
3585         /* Global registers */
3586         CL22_WR_OVER_CL45(sc, phy, MDIO_REG_BANK_AER_BLOCK,
3587                           MDIO_AER_BLOCK_AER_REG, 0);
3588         /* Disable CL36 PCS Tx */
3589         elink_cl45_read(sc, phy, MDIO_WC_DEVAD,
3590                         MDIO_WC_REG_XGXSBLK1_LANECTRL0, &val16);
3591         val16 &= ~(0x0011 << lane);
3592         elink_cl45_write(sc, phy, MDIO_WC_DEVAD,
3593                          MDIO_WC_REG_XGXSBLK1_LANECTRL0, val16);
3594
3595         elink_cl45_read(sc, phy, MDIO_WC_DEVAD,
3596                         MDIO_WC_REG_XGXSBLK1_LANECTRL1, &val16);
3597         val16 |= (0x0303 << (lane << 1));
3598         elink_cl45_write(sc, phy, MDIO_WC_DEVAD,
3599                          MDIO_WC_REG_XGXSBLK1_LANECTRL1, val16);
3600         /* Restore AER */
3601         elink_set_aer_mmd(params, phy);
3602         /* Set speed via PMA/PMD register */
3603         elink_cl45_write(sc, phy, MDIO_PMA_DEVAD,
3604                          MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x2040);
3605
3606         elink_cl45_write(sc, phy, MDIO_PMA_DEVAD,
3607                          MDIO_WC_REG_IEEE0BLK_AUTONEGNP, 0xB);
3608
3609         /* Enable encoded forced speed */
3610         elink_cl45_write(sc, phy, MDIO_WC_DEVAD,
3611                          MDIO_WC_REG_SERDESDIGITAL_MISC2, 0x30);
3612
3613         /* Turn TX scramble payload only the 64/66 scrambler */
3614         elink_cl45_write(sc, phy, MDIO_WC_DEVAD, MDIO_WC_REG_TX66_CONTROL, 0x9);
3615
3616         /* Turn RX scramble payload only the 64/66 scrambler */
3617         elink_cl45_read_or_write(sc, phy, MDIO_WC_DEVAD,
3618                                  MDIO_WC_REG_RX66_CONTROL, 0xF9);
3619
3620         /* Set and clear loopback to cause a reset to 64/66 decoder */
3621         elink_cl45_write(sc, phy, MDIO_WC_DEVAD,
3622                          MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x4000);
3623         elink_cl45_write(sc, phy, MDIO_WC_DEVAD,
3624                          MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x0);
3625
3626 }
3627
3628 static void elink_warpcore_set_10G_XFI(struct elink_phy *phy,
3629                                        struct elink_params *params,
3630                                        uint8_t is_xfi)
3631 {
3632         struct bnx2x_softc *sc = params->sc;
3633         uint16_t misc1_val, tap_val, tx_driver_val, lane, val;
3634         uint32_t cfg_tap_val, tx_drv_brdct, tx_equal;
3635
3636         /* Hold rxSeqStart */
3637         elink_cl45_read_or_write(sc, phy, MDIO_WC_DEVAD,
3638                                  MDIO_WC_REG_DSC2B0_DSC_MISC_CTRL0, 0x8000);
3639
3640         /* Hold tx_fifo_reset */
3641         elink_cl45_read_or_write(sc, phy, MDIO_WC_DEVAD,
3642                                  MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X3, 0x1);
3643
3644         /* Disable CL73 AN */
3645         elink_cl45_write(sc, phy, MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0);
3646
3647         /* Disable 100FX Enable and Auto-Detect */
3648         elink_cl45_read_and_write(sc, phy, MDIO_WC_DEVAD,
3649                                   MDIO_WC_REG_FX100_CTRL1, 0xFFFA);
3650
3651         /* Disable 100FX Idle detect */
3652         elink_cl45_read_or_write(sc, phy, MDIO_WC_DEVAD,
3653                                  MDIO_WC_REG_FX100_CTRL3, 0x0080);
3654
3655         /* Set Block address to Remote PHY & Clear forced_speed[5] */
3656         elink_cl45_read_and_write(sc, phy, MDIO_WC_DEVAD,
3657                                   MDIO_WC_REG_DIGITAL4_MISC3, 0xFF7F);
3658
3659         /* Turn off auto-detect & fiber mode */
3660         elink_cl45_read_and_write(sc, phy, MDIO_WC_DEVAD,
3661                                   MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1,
3662                                   0xFFEE);
3663
3664         /* Set filter_force_link, disable_false_link and parallel_detect */
3665         elink_cl45_read(sc, phy, MDIO_WC_DEVAD,
3666                         MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2, &val);
3667         elink_cl45_write(sc, phy, MDIO_WC_DEVAD,
3668                          MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2,
3669                          ((val | 0x0006) & 0xFFFE));
3670
3671         /* Set XFI / SFI */
3672         elink_cl45_read(sc, phy, MDIO_WC_DEVAD,
3673                         MDIO_WC_REG_SERDESDIGITAL_MISC1, &misc1_val);
3674
3675         misc1_val &= ~(0x1f);
3676
3677         if (is_xfi) {
3678                 misc1_val |= 0x5;
3679                 tap_val = WC_TX_FIR(0x08, 0x37, 0x00);
3680                 tx_driver_val = WC_TX_DRIVER(0x00, 0x02, 0x03);
3681         } else {
3682                 cfg_tap_val = REG_RD(sc, params->shmem_base +
3683                                      offsetof(struct shmem_region,
3684                                               dev_info.port_hw_config[params->
3685                                                                       port].sfi_tap_values));
3686
3687                 tx_equal = cfg_tap_val & PORT_HW_CFG_TX_EQUALIZATION_MASK;
3688
3689                 tx_drv_brdct = (cfg_tap_val &
3690                                 PORT_HW_CFG_TX_DRV_BROADCAST_MASK) >>
3691                     PORT_HW_CFG_TX_DRV_BROADCAST_SHIFT;
3692
3693                 misc1_val |= 0x9;
3694
3695                 /* TAP values are controlled by nvram, if value there isn't 0 */
3696                 if (tx_equal)
3697                         tap_val = (uint16_t) tx_equal;
3698                 else
3699                         tap_val = WC_TX_FIR(0x0f, 0x2b, 0x02);
3700
3701                 if (tx_drv_brdct)
3702                         tx_driver_val =
3703                             WC_TX_DRIVER(0x03, (uint16_t) tx_drv_brdct, 0x06);
3704                 else
3705                         tx_driver_val = WC_TX_DRIVER(0x03, 0x02, 0x06);
3706         }
3707         elink_cl45_write(sc, phy, MDIO_WC_DEVAD,
3708                          MDIO_WC_REG_SERDESDIGITAL_MISC1, misc1_val);
3709
3710         /* Set Transmit PMD settings */
3711         lane = elink_get_warpcore_lane(params);
3712         elink_cl45_write(sc, phy, MDIO_WC_DEVAD,
3713                          MDIO_WC_REG_TX_FIR_TAP,
3714                          tap_val | MDIO_WC_REG_TX_FIR_TAP_ENABLE);
3715         elink_cl45_write(sc, phy, MDIO_WC_DEVAD,
3716                          MDIO_WC_REG_TX0_TX_DRIVER + 0x10 * lane,
3717                          tx_driver_val);
3718
3719         /* Enable fiber mode, enable and invert sig_det */
3720         elink_cl45_read_or_write(sc, phy, MDIO_WC_DEVAD,
3721                                  MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1, 0xd);
3722
3723         /* Set Block address to Remote PHY & Set forced_speed[5], 40bit mode */
3724         elink_cl45_read_or_write(sc, phy, MDIO_WC_DEVAD,
3725                                  MDIO_WC_REG_DIGITAL4_MISC3, 0x8080);
3726
3727         elink_warpcore_set_lpi_passthrough(phy, params);
3728
3729         /* 10G XFI Full Duplex */
3730         elink_cl45_write(sc, phy, MDIO_WC_DEVAD,
3731                          MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x100);
3732
3733         /* Release tx_fifo_reset */
3734         elink_cl45_read_and_write(sc, phy, MDIO_WC_DEVAD,
3735                                   MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X3,
3736                                   0xFFFE);
3737         /* Release rxSeqStart */
3738         elink_cl45_read_and_write(sc, phy, MDIO_WC_DEVAD,
3739                                   MDIO_WC_REG_DSC2B0_DSC_MISC_CTRL0, 0x7FFF);
3740 }
3741
3742 static void elink_warpcore_set_20G_force_KR2(struct elink_phy *phy,
3743                                              struct elink_params *params)
3744 {
3745         uint16_t val;
3746         struct bnx2x_softc *sc = params->sc;
3747         /* Set global registers, so set AER lane to 0 */
3748         CL22_WR_OVER_CL45(sc, phy, MDIO_REG_BANK_AER_BLOCK,
3749                           MDIO_AER_BLOCK_AER_REG, 0);
3750
3751         /* Disable sequencer */
3752         elink_cl45_read_and_write(sc, phy, MDIO_WC_DEVAD,
3753                                   MDIO_WC_REG_XGXSBLK0_XGXSCONTROL, ~(1 << 13));
3754
3755         elink_set_aer_mmd(params, phy);
3756
3757         elink_cl45_read_and_write(sc, phy, MDIO_PMA_DEVAD,
3758                                   MDIO_WC_REG_PMD_KR_CONTROL, ~(1 << 1));
3759         elink_cl45_write(sc, phy, MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0);
3760         /* Turn off CL73 */
3761         elink_cl45_read(sc, phy, MDIO_WC_DEVAD,
3762                         MDIO_WC_REG_CL73_USERB0_CTRL, &val);
3763         val &= ~(1 << 5);
3764         val |= (1 << 6);
3765         elink_cl45_write(sc, phy, MDIO_WC_DEVAD,
3766                          MDIO_WC_REG_CL73_USERB0_CTRL, val);
3767
3768         /* Set 20G KR2 force speed */
3769         elink_cl45_read_or_write(sc, phy, MDIO_WC_DEVAD,
3770                                  MDIO_WC_REG_SERDESDIGITAL_MISC1, 0x1f);
3771
3772         elink_cl45_read_or_write(sc, phy, MDIO_WC_DEVAD,
3773                                  MDIO_WC_REG_DIGITAL4_MISC3, (1 << 7));
3774
3775         elink_cl45_read(sc, phy, MDIO_WC_DEVAD,
3776                         MDIO_WC_REG_CL72_USERB0_CL72_MISC1_CONTROL, &val);
3777         val &= ~(3 << 14);
3778         val |= (1 << 15);
3779         elink_cl45_write(sc, phy, MDIO_WC_DEVAD,
3780                          MDIO_WC_REG_CL72_USERB0_CL72_MISC1_CONTROL, val);
3781         elink_cl45_write(sc, phy, MDIO_WC_DEVAD,
3782                          MDIO_WC_REG_CL72_USERB0_CL72_TX_FIR_TAP, 0x835A);
3783
3784         /* Enable sequencer (over lane 0) */
3785         CL22_WR_OVER_CL45(sc, phy, MDIO_REG_BANK_AER_BLOCK,
3786                           MDIO_AER_BLOCK_AER_REG, 0);
3787
3788         elink_cl45_read_or_write(sc, phy, MDIO_WC_DEVAD,
3789                                  MDIO_WC_REG_XGXSBLK0_XGXSCONTROL, (1 << 13));
3790
3791         elink_set_aer_mmd(params, phy);
3792 }
3793
3794 static void elink_warpcore_set_20G_DXGXS(struct bnx2x_softc *sc,
3795                                          struct elink_phy *phy, uint16_t lane)
3796 {
3797         /* Rx0 anaRxControl1G */
3798         elink_cl45_write(sc, phy, MDIO_WC_DEVAD,
3799                          MDIO_WC_REG_RX0_ANARXCONTROL1G, 0x90);
3800
3801         /* Rx2 anaRxControl1G */
3802         elink_cl45_write(sc, phy, MDIO_WC_DEVAD,
3803                          MDIO_WC_REG_RX2_ANARXCONTROL1G, 0x90);
3804
3805         elink_cl45_write(sc, phy, MDIO_WC_DEVAD, MDIO_WC_REG_RX66_SCW0, 0xE070);
3806
3807         elink_cl45_write(sc, phy, MDIO_WC_DEVAD, MDIO_WC_REG_RX66_SCW1, 0xC0D0);
3808
3809         elink_cl45_write(sc, phy, MDIO_WC_DEVAD, MDIO_WC_REG_RX66_SCW2, 0xA0B0);
3810
3811         elink_cl45_write(sc, phy, MDIO_WC_DEVAD, MDIO_WC_REG_RX66_SCW3, 0x8090);
3812
3813         elink_cl45_write(sc, phy, MDIO_WC_DEVAD,
3814                          MDIO_WC_REG_RX66_SCW0_MASK, 0xF0F0);
3815
3816         elink_cl45_write(sc, phy, MDIO_WC_DEVAD,
3817                          MDIO_WC_REG_RX66_SCW1_MASK, 0xF0F0);
3818
3819         elink_cl45_write(sc, phy, MDIO_WC_DEVAD,
3820                          MDIO_WC_REG_RX66_SCW2_MASK, 0xF0F0);
3821
3822         elink_cl45_write(sc, phy, MDIO_WC_DEVAD,
3823                          MDIO_WC_REG_RX66_SCW3_MASK, 0xF0F0);
3824
3825         /* Serdes Digital Misc1 */
3826         elink_cl45_write(sc, phy, MDIO_WC_DEVAD,
3827                          MDIO_WC_REG_SERDESDIGITAL_MISC1, 0x6008);
3828
3829         /* Serdes Digital4 Misc3 */
3830         elink_cl45_write(sc, phy, MDIO_WC_DEVAD,
3831                          MDIO_WC_REG_DIGITAL4_MISC3, 0x8088);
3832
3833         /* Set Transmit PMD settings */
3834         elink_cl45_write(sc, phy, MDIO_WC_DEVAD,
3835                          MDIO_WC_REG_TX_FIR_TAP,
3836                          (WC_TX_FIR(0x12, 0x2d, 0x00) |
3837                           MDIO_WC_REG_TX_FIR_TAP_ENABLE));
3838         elink_cl45_write(sc, phy, MDIO_WC_DEVAD,
3839                          MDIO_WC_REG_TX0_TX_DRIVER + 0x10 * lane,
3840                          WC_TX_DRIVER(0x02, 0x02, 0x02));
3841 }
3842
3843 static void elink_warpcore_set_sgmii_speed(struct elink_phy *phy,
3844                                            struct elink_params *params,
3845                                            uint8_t fiber_mode,
3846                                            uint8_t always_autoneg)
3847 {
3848         struct bnx2x_softc *sc = params->sc;
3849         uint16_t val16, digctrl_kx1, digctrl_kx2;
3850
3851         /* Clear XFI clock comp in non-10G single lane mode. */
3852         elink_cl45_read_and_write(sc, phy, MDIO_WC_DEVAD,
3853                                   MDIO_WC_REG_RX66_CONTROL, ~(3 << 13));
3854
3855         elink_warpcore_set_lpi_passthrough(phy, params);
3856
3857         if (always_autoneg || phy->req_line_speed == ELINK_SPEED_AUTO_NEG) {
3858                 /* SGMII Autoneg */
3859                 elink_cl45_read_or_write(sc, phy, MDIO_WC_DEVAD,
3860                                          MDIO_WC_REG_COMBO_IEEE0_MIICTRL,
3861                                          0x1000);
3862                 PMD_DRV_LOG(DEBUG, "set SGMII AUTONEG");
3863         } else {
3864                 elink_cl45_read(sc, phy, MDIO_WC_DEVAD,
3865                                 MDIO_WC_REG_COMBO_IEEE0_MIICTRL, &val16);
3866                 val16 &= 0xcebf;
3867                 switch (phy->req_line_speed) {
3868                 case ELINK_SPEED_10:
3869                         break;
3870                 case ELINK_SPEED_100:
3871                         val16 |= 0x2000;
3872                         break;
3873                 case ELINK_SPEED_1000:
3874                         val16 |= 0x0040;
3875                         break;
3876                 default:
3877                         PMD_DRV_LOG(DEBUG,
3878                                     "Speed not supported: 0x%x",
3879                                     phy->req_line_speed);
3880                         return;
3881                 }
3882
3883                 if (phy->req_duplex == DUPLEX_FULL)
3884                         val16 |= 0x0100;
3885
3886                 elink_cl45_write(sc, phy, MDIO_WC_DEVAD,
3887                                  MDIO_WC_REG_COMBO_IEEE0_MIICTRL, val16);
3888
3889                 PMD_DRV_LOG(DEBUG, "set SGMII force speed %d",
3890                             phy->req_line_speed);
3891                 elink_cl45_read(sc, phy, MDIO_WC_DEVAD,
3892                                 MDIO_WC_REG_COMBO_IEEE0_MIICTRL, &val16);
3893                 PMD_DRV_LOG(DEBUG, "  (readback) %x", val16);
3894         }
3895
3896         /* SGMII Slave mode and disable signal detect */
3897         elink_cl45_read(sc, phy, MDIO_WC_DEVAD,
3898                         MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1, &digctrl_kx1);
3899         if (fiber_mode)
3900                 digctrl_kx1 = 1;
3901         else
3902                 digctrl_kx1 &= 0xff4a;
3903
3904         elink_cl45_write(sc, phy, MDIO_WC_DEVAD,
3905                          MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1, digctrl_kx1);
3906
3907         /* Turn off parallel detect */
3908         elink_cl45_read(sc, phy, MDIO_WC_DEVAD,
3909                         MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2, &digctrl_kx2);
3910         elink_cl45_write(sc, phy, MDIO_WC_DEVAD,
3911                          MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2,
3912                          (digctrl_kx2 & ~(1 << 2)));
3913
3914         /* Re-enable parallel detect */
3915         elink_cl45_write(sc, phy, MDIO_WC_DEVAD,
3916                          MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2,
3917                          (digctrl_kx2 | (1 << 2)));
3918
3919         /* Enable autodet */
3920         elink_cl45_write(sc, phy, MDIO_WC_DEVAD,
3921                          MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1,
3922                          (digctrl_kx1 | 0x10));
3923 }
3924
3925 static void elink_warpcore_reset_lane(struct bnx2x_softc *sc,
3926                                       struct elink_phy *phy, uint8_t reset)
3927 {
3928         uint16_t val;
3929         /* Take lane out of reset after configuration is finished */
3930         elink_cl45_read(sc, phy, MDIO_WC_DEVAD,
3931                         MDIO_WC_REG_DIGITAL5_MISC6, &val);
3932         if (reset)
3933                 val |= 0xC000;
3934         else
3935                 val &= 0x3FFF;
3936         elink_cl45_write(sc, phy, MDIO_WC_DEVAD,
3937                          MDIO_WC_REG_DIGITAL5_MISC6, val);
3938         elink_cl45_read(sc, phy, MDIO_WC_DEVAD,
3939                         MDIO_WC_REG_DIGITAL5_MISC6, &val);
3940 }
3941
3942 /* Clear SFI/XFI link settings registers */
3943 static void elink_warpcore_clear_regs(struct elink_phy *phy,
3944                                       struct elink_params *params,
3945                                       uint16_t lane)
3946 {
3947         struct bnx2x_softc *sc = params->sc;
3948         uint16_t i;
3949         static struct elink_reg_set wc_regs[] = {
3950                 {MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0},
3951                 {MDIO_WC_DEVAD, MDIO_WC_REG_FX100_CTRL1, 0x014a},
3952                 {MDIO_WC_DEVAD, MDIO_WC_REG_FX100_CTRL3, 0x0800},
3953                 {MDIO_WC_DEVAD, MDIO_WC_REG_DIGITAL4_MISC3, 0x8008},
3954                 {MDIO_WC_DEVAD, MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1,
3955                  0x0195},
3956                 {MDIO_WC_DEVAD, MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2,
3957                  0x0007},
3958                 {MDIO_WC_DEVAD, MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X3,
3959                  0x0002},
3960                 {MDIO_WC_DEVAD, MDIO_WC_REG_SERDESDIGITAL_MISC1, 0x6000},
3961                 {MDIO_WC_DEVAD, MDIO_WC_REG_TX_FIR_TAP, 0x0000},
3962                 {MDIO_WC_DEVAD, MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x2040},
3963                 {MDIO_WC_DEVAD, MDIO_WC_REG_COMBO_IEEE0_MIICTRL, 0x0140}
3964         };
3965         /* Set XFI clock comp as default. */
3966         elink_cl45_read_or_write(sc, phy, MDIO_WC_DEVAD,
3967                                  MDIO_WC_REG_RX66_CONTROL, (3 << 13));
3968
3969         for (i = 0; i < ARRAY_SIZE(wc_regs); i++)
3970                 elink_cl45_write(sc, phy, wc_regs[i].devad, wc_regs[i].reg,
3971                                  wc_regs[i].val);
3972
3973         lane = elink_get_warpcore_lane(params);
3974         elink_cl45_write(sc, phy, MDIO_WC_DEVAD,
3975                          MDIO_WC_REG_TX0_TX_DRIVER + 0x10 * lane, 0x0990);
3976
3977 }
3978
3979 static elink_status_t elink_get_mod_abs_int_cfg(struct bnx2x_softc *sc,
3980                                                 uint32_t shmem_base,
3981                                                 uint8_t port,
3982                                                 uint8_t * gpio_num,
3983                                                 uint8_t * gpio_port)
3984 {
3985         uint32_t cfg_pin;
3986         *gpio_num = 0;
3987         *gpio_port = 0;
3988         if (CHIP_IS_E3(sc)) {
3989                 cfg_pin = (REG_RD(sc, shmem_base +
3990                                   offsetof(struct shmem_region,
3991                                            dev_info.port_hw_config[port].
3992                                            e3_sfp_ctrl)) &
3993                            PORT_HW_CFG_E3_MOD_ABS_MASK) >>
3994                     PORT_HW_CFG_E3_MOD_ABS_SHIFT;
3995
3996                 /* Should not happen. This function called upon interrupt
3997                  * triggered by GPIO ( since EPIO can only generate interrupts
3998                  * to MCP).
3999                  * So if this function was called and none of the GPIOs was set,
4000                  * it means the shit hit the fan.
4001                  */
4002                 if ((cfg_pin < PIN_CFG_GPIO0_P0) ||
4003                     (cfg_pin > PIN_CFG_GPIO3_P1)) {
4004                         PMD_DRV_LOG(DEBUG,
4005                                     "No cfg pin %x for module detect indication",
4006                                     cfg_pin);
4007                         return ELINK_STATUS_ERROR;
4008                 }
4009
4010                 *gpio_num = (cfg_pin - PIN_CFG_GPIO0_P0) & 0x3;
4011                 *gpio_port = (cfg_pin - PIN_CFG_GPIO0_P0) >> 2;
4012         } else {
4013                 *gpio_num = MISC_REGISTERS_GPIO_3;
4014                 *gpio_port = port;
4015         }
4016
4017         return ELINK_STATUS_OK;
4018 }
4019
4020 static int elink_is_sfp_module_plugged(struct elink_params *params)
4021 {
4022         struct bnx2x_softc *sc = params->sc;
4023         uint8_t gpio_num, gpio_port;
4024         uint32_t gpio_val;
4025         if (elink_get_mod_abs_int_cfg(sc,
4026                                       params->shmem_base, params->port,
4027                                       &gpio_num, &gpio_port) != ELINK_STATUS_OK)
4028                 return 0;
4029         gpio_val = elink_cb_gpio_read(sc, gpio_num, gpio_port);
4030
4031         /* Call the handling function in case module is detected */
4032         if (gpio_val == 0)
4033                 return 1;
4034         else
4035                 return 0;
4036 }
4037
4038 static int elink_warpcore_get_sigdet(struct elink_phy *phy,
4039                                      struct elink_params *params)
4040 {
4041         uint16_t gp2_status_reg0, lane;
4042         struct bnx2x_softc *sc = params->sc;
4043
4044         lane = elink_get_warpcore_lane(params);
4045
4046         elink_cl45_read(sc, phy, MDIO_WC_DEVAD, MDIO_WC_REG_GP2_STATUS_GP_2_0,
4047                         &gp2_status_reg0);
4048
4049         return (gp2_status_reg0 >> (8 + lane)) & 0x1;
4050 }
4051
4052 static void elink_warpcore_config_runtime(struct elink_phy *phy,
4053                                           struct elink_params *params,
4054                                           struct elink_vars *vars)
4055 {
4056         struct bnx2x_softc *sc = params->sc;
4057         uint32_t serdes_net_if;
4058         uint16_t gp_status1 = 0, lnkup = 0, lnkup_kr = 0;
4059
4060         vars->turn_to_run_wc_rt = vars->turn_to_run_wc_rt ? 0 : 1;
4061
4062         if (!vars->turn_to_run_wc_rt)
4063                 return;
4064
4065         if (vars->rx_tx_asic_rst) {
4066                 uint16_t lane = elink_get_warpcore_lane(params);
4067                 serdes_net_if = (REG_RD(sc, params->shmem_base +
4068                                         offsetof(struct shmem_region,
4069                                                  dev_info.port_hw_config
4070                                                  [params->port].
4071                                                  default_cfg)) &
4072                                  PORT_HW_CFG_NET_SERDES_IF_MASK);
4073
4074                 switch (serdes_net_if) {
4075                 case PORT_HW_CFG_NET_SERDES_IF_KR:
4076                         /* Do we get link yet? */
4077                         elink_cl45_read(sc, phy, MDIO_WC_DEVAD, 0x81d1,
4078                                         &gp_status1);
4079                         lnkup = (gp_status1 >> (8 + lane)) & 0x1;       /* 1G */
4080                         /*10G KR */
4081                         lnkup_kr = (gp_status1 >> (12 + lane)) & 0x1;
4082
4083                         if (lnkup_kr || lnkup) {
4084                                 vars->rx_tx_asic_rst = 0;
4085                         } else {
4086                                 /* Reset the lane to see if link comes up. */
4087                                 elink_warpcore_reset_lane(sc, phy, 1);
4088                                 elink_warpcore_reset_lane(sc, phy, 0);
4089
4090                                 /* Restart Autoneg */
4091                                 elink_cl45_write(sc, phy, MDIO_AN_DEVAD,
4092                                                  MDIO_WC_REG_IEEE0BLK_MIICNTL,
4093                                                  0x1200);
4094
4095                                 vars->rx_tx_asic_rst--;
4096                                 PMD_DRV_LOG(DEBUG, "0x%x retry left",
4097                                             vars->rx_tx_asic_rst);
4098                         }
4099                         break;
4100
4101                 default:
4102                         break;
4103                 }
4104
4105         }
4106         /*params->rx_tx_asic_rst */
4107 }
4108
4109 static void elink_warpcore_config_sfi(struct elink_phy *phy,
4110                                       struct elink_params *params)
4111 {
4112         uint16_t lane = elink_get_warpcore_lane(params);
4113
4114         elink_warpcore_clear_regs(phy, params, lane);
4115         if ((params->req_line_speed[ELINK_LINK_CONFIG_IDX(ELINK_INT_PHY)] ==
4116              ELINK_SPEED_10000) &&
4117             (phy->media_type != ELINK_ETH_PHY_SFP_1G_FIBER)) {
4118                 PMD_DRV_LOG(DEBUG, "Setting 10G SFI");
4119                 elink_warpcore_set_10G_XFI(phy, params, 0);
4120         } else {
4121                 PMD_DRV_LOG(DEBUG, "Setting 1G Fiber");
4122                 elink_warpcore_set_sgmii_speed(phy, params, 1, 0);
4123         }
4124 }
4125
4126 static void elink_sfp_e3_set_transmitter(struct elink_params *params,
4127                                          struct elink_phy *phy, uint8_t tx_en)
4128 {
4129         struct bnx2x_softc *sc = params->sc;
4130         uint32_t cfg_pin;
4131         uint8_t port = params->port;
4132
4133         cfg_pin = REG_RD(sc, params->shmem_base +
4134                          offsetof(struct shmem_region,
4135                                   dev_info.port_hw_config[port].e3_sfp_ctrl)) &
4136             PORT_HW_CFG_E3_TX_LASER_MASK;
4137         /* Set the !tx_en since this pin is DISABLE_TX_LASER */
4138         PMD_DRV_LOG(DEBUG, "Setting WC TX to %d", tx_en);
4139
4140         /* For 20G, the expected pin to be used is 3 pins after the current */
4141         elink_set_cfg_pin(sc, cfg_pin, tx_en ^ 1);
4142         if (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_20G)
4143                 elink_set_cfg_pin(sc, cfg_pin + 3, tx_en ^ 1);
4144 }
4145
4146 static uint8_t elink_warpcore_config_init(struct elink_phy *phy,
4147                                           struct elink_params *params,
4148                                           struct elink_vars *vars)
4149 {
4150         struct bnx2x_softc *sc = params->sc;
4151         uint32_t serdes_net_if;
4152         uint8_t fiber_mode;
4153         uint16_t lane = elink_get_warpcore_lane(params);
4154         serdes_net_if = (REG_RD(sc, params->shmem_base +
4155                                 offsetof(struct shmem_region,
4156                                          dev_info.port_hw_config[params->port].
4157                                          default_cfg)) &
4158                          PORT_HW_CFG_NET_SERDES_IF_MASK);
4159         PMD_DRV_LOG(DEBUG,
4160                     "Begin Warpcore init, link_speed %d, "
4161                     "serdes_net_if = 0x%x", vars->line_speed, serdes_net_if);
4162         elink_set_aer_mmd(params, phy);
4163         elink_warpcore_reset_lane(sc, phy, 1);
4164         vars->phy_flags |= PHY_XGXS_FLAG;
4165         if ((serdes_net_if == PORT_HW_CFG_NET_SERDES_IF_SGMII) ||
4166             (phy->req_line_speed &&
4167              ((phy->req_line_speed == ELINK_SPEED_100) ||
4168               (phy->req_line_speed == ELINK_SPEED_10)))) {
4169                 vars->phy_flags |= PHY_SGMII_FLAG;
4170                 PMD_DRV_LOG(DEBUG, "Setting SGMII mode");
4171                 elink_warpcore_clear_regs(phy, params, lane);
4172                 elink_warpcore_set_sgmii_speed(phy, params, 0, 1);
4173         } else {
4174                 switch (serdes_net_if) {
4175                 case PORT_HW_CFG_NET_SERDES_IF_KR:
4176                         /* Enable KR Auto Neg */
4177                         if (params->loopback_mode != ELINK_LOOPBACK_EXT)
4178                                 elink_warpcore_enable_AN_KR(phy, params, vars);
4179                         else {
4180                                 PMD_DRV_LOG(DEBUG, "Setting KR 10G-Force");
4181                                 elink_warpcore_set_10G_KR(phy, params);
4182                         }
4183                         break;
4184
4185                 case PORT_HW_CFG_NET_SERDES_IF_XFI:
4186                         elink_warpcore_clear_regs(phy, params, lane);
4187                         if (vars->line_speed == ELINK_SPEED_10000) {
4188                                 PMD_DRV_LOG(DEBUG, "Setting 10G XFI");
4189                                 elink_warpcore_set_10G_XFI(phy, params, 1);
4190                         } else {
4191                                 if (ELINK_SINGLE_MEDIA_DIRECT(params)) {
4192                                         PMD_DRV_LOG(DEBUG, "1G Fiber");
4193                                         fiber_mode = 1;
4194                                 } else {
4195                                         PMD_DRV_LOG(DEBUG, "10/100/1G SGMII");
4196                                         fiber_mode = 0;
4197                                 }
4198                                 elink_warpcore_set_sgmii_speed(phy,
4199                                                                params,
4200                                                                fiber_mode, 0);
4201                         }
4202
4203                         break;
4204
4205                 case PORT_HW_CFG_NET_SERDES_IF_SFI:
4206                         /* Issue Module detection if module is plugged, or
4207                          * enabled transmitter to avoid current leakage in case
4208                          * no module is connected
4209                          */
4210                         if ((params->loopback_mode == ELINK_LOOPBACK_NONE) ||
4211                             (params->loopback_mode == ELINK_LOOPBACK_EXT)) {
4212                                 if (elink_is_sfp_module_plugged(params))
4213                                         elink_sfp_module_detection(phy, params);
4214                                 else
4215                                         elink_sfp_e3_set_transmitter(params,
4216                                                                      phy, 1);
4217                         }
4218
4219                         elink_warpcore_config_sfi(phy, params);
4220                         break;
4221
4222                 case PORT_HW_CFG_NET_SERDES_IF_DXGXS:
4223                         if (vars->line_speed != ELINK_SPEED_20000) {
4224                                 PMD_DRV_LOG(DEBUG, "Speed not supported yet");
4225                                 return 0;
4226                         }
4227                         PMD_DRV_LOG(DEBUG, "Setting 20G DXGXS");
4228                         elink_warpcore_set_20G_DXGXS(sc, phy, lane);
4229                         /* Issue Module detection */
4230
4231                         elink_sfp_module_detection(phy, params);
4232                         break;
4233                 case PORT_HW_CFG_NET_SERDES_IF_KR2:
4234                         if (!params->loopback_mode) {
4235                                 elink_warpcore_enable_AN_KR(phy, params, vars);
4236                         } else {
4237                                 PMD_DRV_LOG(DEBUG, "Setting KR 20G-Force");
4238                                 elink_warpcore_set_20G_force_KR2(phy, params);
4239                         }
4240                         break;
4241                 default:
4242                         PMD_DRV_LOG(DEBUG,
4243                                     "Unsupported Serdes Net Interface 0x%x",
4244                                     serdes_net_if);
4245                         return 0;
4246                 }
4247         }
4248
4249         /* Take lane out of reset after configuration is finished */
4250         elink_warpcore_reset_lane(sc, phy, 0);
4251         PMD_DRV_LOG(DEBUG, "Exit config init");
4252
4253         return 0;
4254 }
4255
4256 static void elink_warpcore_link_reset(struct elink_phy *phy,
4257                                       struct elink_params *params)
4258 {
4259         struct bnx2x_softc *sc = params->sc;
4260         uint16_t val16, lane;
4261         elink_sfp_e3_set_transmitter(params, phy, 0);
4262         elink_set_mdio_emac_per_phy(sc, params);
4263         elink_set_aer_mmd(params, phy);
4264         /* Global register */
4265         elink_warpcore_reset_lane(sc, phy, 1);
4266
4267         /* Clear loopback settings (if any) */
4268         /* 10G & 20G */
4269         elink_cl45_read_and_write(sc, phy, MDIO_WC_DEVAD,
4270                                   MDIO_WC_REG_COMBO_IEEE0_MIICTRL, 0xBFFF);
4271
4272         elink_cl45_read_and_write(sc, phy, MDIO_WC_DEVAD,
4273                                   MDIO_WC_REG_IEEE0BLK_MIICNTL, 0xfffe);
4274
4275         /* Update those 1-copy registers */
4276         CL22_WR_OVER_CL45(sc, phy, MDIO_REG_BANK_AER_BLOCK,
4277                           MDIO_AER_BLOCK_AER_REG, 0);
4278         /* Enable 1G MDIO (1-copy) */
4279         elink_cl45_read_and_write(sc, phy, MDIO_WC_DEVAD,
4280                                   MDIO_WC_REG_XGXSBLK0_XGXSCONTROL, ~0x10);
4281
4282         elink_cl45_read_and_write(sc, phy, MDIO_WC_DEVAD,
4283                                   MDIO_WC_REG_XGXSBLK1_LANECTRL2, 0xff00);
4284         lane = elink_get_warpcore_lane(params);
4285         /* Disable CL36 PCS Tx */
4286         elink_cl45_read(sc, phy, MDIO_WC_DEVAD,
4287                         MDIO_WC_REG_XGXSBLK1_LANECTRL0, &val16);
4288         val16 |= (0x11 << lane);
4289         if (phy->flags & ELINK_FLAGS_WC_DUAL_MODE)
4290                 val16 |= (0x22 << lane);
4291         elink_cl45_write(sc, phy, MDIO_WC_DEVAD,
4292                          MDIO_WC_REG_XGXSBLK1_LANECTRL0, val16);
4293
4294         elink_cl45_read(sc, phy, MDIO_WC_DEVAD,
4295                         MDIO_WC_REG_XGXSBLK1_LANECTRL1, &val16);
4296         val16 &= ~(0x0303 << (lane << 1));
4297         val16 |= (0x0101 << (lane << 1));
4298         if (phy->flags & ELINK_FLAGS_WC_DUAL_MODE) {
4299                 val16 &= ~(0x0c0c << (lane << 1));
4300                 val16 |= (0x0404 << (lane << 1));
4301         }
4302
4303         elink_cl45_write(sc, phy, MDIO_WC_DEVAD,
4304                          MDIO_WC_REG_XGXSBLK1_LANECTRL1, val16);
4305         /* Restore AER */
4306         elink_set_aer_mmd(params, phy);
4307
4308 }
4309
4310 static void elink_set_warpcore_loopback(struct elink_phy *phy,
4311                                         struct elink_params *params)
4312 {
4313         struct bnx2x_softc *sc = params->sc;
4314         uint16_t val16;
4315         uint32_t lane;
4316         PMD_DRV_LOG(DEBUG, "Setting Warpcore loopback type %x, speed %d",
4317                     params->loopback_mode, phy->req_line_speed);
4318
4319         if (phy->req_line_speed < ELINK_SPEED_10000 ||
4320             phy->supported & ELINK_SUPPORTED_20000baseKR2_Full) {
4321                 /* 10/100/1000/20G-KR2 */
4322
4323                 /* Update those 1-copy registers */
4324                 CL22_WR_OVER_CL45(sc, phy, MDIO_REG_BANK_AER_BLOCK,
4325                                   MDIO_AER_BLOCK_AER_REG, 0);
4326                 /* Enable 1G MDIO (1-copy) */
4327                 elink_cl45_read_or_write(sc, phy, MDIO_WC_DEVAD,
4328                                          MDIO_WC_REG_XGXSBLK0_XGXSCONTROL,
4329                                          0x10);
4330                 /* Set 1G loopback based on lane (1-copy) */
4331                 lane = elink_get_warpcore_lane(params);
4332                 elink_cl45_read(sc, phy, MDIO_WC_DEVAD,
4333                                 MDIO_WC_REG_XGXSBLK1_LANECTRL2, &val16);
4334                 val16 |= (1 << lane);
4335                 if (phy->flags & ELINK_FLAGS_WC_DUAL_MODE)
4336                         val16 |= (2 << lane);
4337                 elink_cl45_write(sc, phy, MDIO_WC_DEVAD,
4338                                  MDIO_WC_REG_XGXSBLK1_LANECTRL2, val16);
4339
4340                 /* Switch back to 4-copy registers */
4341                 elink_set_aer_mmd(params, phy);
4342         } else {
4343                 /* 10G / 20G-DXGXS */
4344                 elink_cl45_read_or_write(sc, phy, MDIO_WC_DEVAD,
4345                                          MDIO_WC_REG_COMBO_IEEE0_MIICTRL,
4346                                          0x4000);
4347                 elink_cl45_read_or_write(sc, phy, MDIO_WC_DEVAD,
4348                                          MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x1);
4349         }
4350 }
4351
4352 static void elink_sync_link(struct elink_params *params,
4353                             struct elink_vars *vars)
4354 {
4355         struct bnx2x_softc *sc = params->sc;
4356         uint8_t link_10g_plus;
4357         if (vars->link_status & LINK_STATUS_PHYSICAL_LINK_FLAG)
4358                 vars->phy_flags |= PHY_PHYSICAL_LINK_FLAG;
4359         vars->link_up = (vars->link_status & LINK_STATUS_LINK_UP);
4360         if (vars->link_up) {
4361                 PMD_DRV_LOG(DEBUG, "phy link up");
4362
4363                 vars->phy_link_up = 1;
4364                 vars->duplex = DUPLEX_FULL;
4365                 switch (vars->link_status & LINK_STATUS_SPEED_AND_DUPLEX_MASK) {
4366                 case ELINK_LINK_10THD:
4367                         vars->duplex = DUPLEX_HALF;
4368                         /* Fall through */
4369                 case ELINK_LINK_10TFD:
4370                         vars->line_speed = ELINK_SPEED_10;
4371                         break;
4372
4373                 case ELINK_LINK_100TXHD:
4374                         vars->duplex = DUPLEX_HALF;
4375                         /* Fall through */
4376                 case ELINK_LINK_100T4:
4377                 case ELINK_LINK_100TXFD:
4378                         vars->line_speed = ELINK_SPEED_100;
4379                         break;
4380
4381                 case ELINK_LINK_1000THD:
4382                         vars->duplex = DUPLEX_HALF;
4383                         /* Fall through */
4384                 case ELINK_LINK_1000TFD:
4385                         vars->line_speed = ELINK_SPEED_1000;
4386                         break;
4387
4388                 case ELINK_LINK_2500THD:
4389                         vars->duplex = DUPLEX_HALF;
4390                         /* Fall through */
4391                 case ELINK_LINK_2500TFD:
4392                         vars->line_speed = ELINK_SPEED_2500;
4393                         break;
4394
4395                 case ELINK_LINK_10GTFD:
4396                         vars->line_speed = ELINK_SPEED_10000;
4397                         break;
4398                 case ELINK_LINK_20GTFD:
4399                         vars->line_speed = ELINK_SPEED_20000;
4400                         break;
4401                 default:
4402                         break;
4403                 }
4404                 vars->flow_ctrl = 0;
4405                 if (vars->link_status & LINK_STATUS_TX_FLOW_CONTROL_ENABLED)
4406                         vars->flow_ctrl |= ELINK_FLOW_CTRL_TX;
4407
4408                 if (vars->link_status & LINK_STATUS_RX_FLOW_CONTROL_ENABLED)
4409                         vars->flow_ctrl |= ELINK_FLOW_CTRL_RX;
4410
4411                 if (!vars->flow_ctrl)
4412                         vars->flow_ctrl = ELINK_FLOW_CTRL_NONE;
4413
4414                 if (vars->line_speed &&
4415                     ((vars->line_speed == ELINK_SPEED_10) ||
4416                      (vars->line_speed == ELINK_SPEED_100))) {
4417                         vars->phy_flags |= PHY_SGMII_FLAG;
4418                 } else {
4419                         vars->phy_flags &= ~PHY_SGMII_FLAG;
4420                 }
4421                 if (vars->line_speed &&
4422                     USES_WARPCORE(sc) && (vars->line_speed == ELINK_SPEED_1000))
4423                         vars->phy_flags |= PHY_SGMII_FLAG;
4424                 /* Anything 10 and over uses the bmac */
4425                 link_10g_plus = (vars->line_speed >= ELINK_SPEED_10000);
4426
4427                 if (link_10g_plus) {
4428                         if (USES_WARPCORE(sc))
4429                                 vars->mac_type = ELINK_MAC_TYPE_XMAC;
4430                         else
4431                                 vars->mac_type = ELINK_MAC_TYPE_BMAC;
4432                 } else {
4433                         if (USES_WARPCORE(sc))
4434                                 vars->mac_type = ELINK_MAC_TYPE_UMAC;
4435                         else
4436                                 vars->mac_type = ELINK_MAC_TYPE_EMAC;
4437                 }
4438         } else {                /* Link down */
4439                 PMD_DRV_LOG(DEBUG, "phy link down");
4440
4441                 vars->phy_link_up = 0;
4442
4443                 vars->line_speed = 0;
4444                 vars->duplex = DUPLEX_FULL;
4445                 vars->flow_ctrl = ELINK_FLOW_CTRL_NONE;
4446
4447                 /* Indicate no mac active */
4448                 vars->mac_type = ELINK_MAC_TYPE_NONE;
4449                 if (vars->link_status & LINK_STATUS_PHYSICAL_LINK_FLAG)
4450                         vars->phy_flags |= PHY_HALF_OPEN_CONN_FLAG;
4451                 if (vars->link_status & LINK_STATUS_SFP_TX_FAULT)
4452                         vars->phy_flags |= PHY_SFP_TX_FAULT_FLAG;
4453         }
4454 }
4455
4456 void elink_link_status_update(struct elink_params *params,
4457                               struct elink_vars *vars)
4458 {
4459         struct bnx2x_softc *sc = params->sc;
4460         uint8_t port = params->port;
4461         uint32_t sync_offset, media_types;
4462         /* Update PHY configuration */
4463         set_phy_vars(params, vars);
4464
4465         vars->link_status = REG_RD(sc, params->shmem_base +
4466                                    offsetof(struct shmem_region,
4467                                             port_mb[port].link_status));
4468
4469         /* Force link UP in non LOOPBACK_EXT loopback mode(s) */
4470         if (params->loopback_mode != ELINK_LOOPBACK_NONE &&
4471             params->loopback_mode != ELINK_LOOPBACK_EXT)
4472                 vars->link_status |= LINK_STATUS_LINK_UP;
4473
4474         if (elink_eee_has_cap(params))
4475                 vars->eee_status = REG_RD(sc, params->shmem2_base +
4476                                           offsetof(struct shmem2_region,
4477                                                    eee_status[params->port]));
4478
4479         vars->phy_flags = PHY_XGXS_FLAG;
4480         elink_sync_link(params, vars);
4481         /* Sync media type */
4482         sync_offset = params->shmem_base +
4483             offsetof(struct shmem_region,
4484                      dev_info.port_hw_config[port].media_type);
4485         media_types = REG_RD(sc, sync_offset);
4486
4487         params->phy[ELINK_INT_PHY].media_type =
4488             (media_types & PORT_HW_CFG_MEDIA_TYPE_PHY0_MASK) >>
4489             PORT_HW_CFG_MEDIA_TYPE_PHY0_SHIFT;
4490         params->phy[ELINK_EXT_PHY1].media_type =
4491             (media_types & PORT_HW_CFG_MEDIA_TYPE_PHY1_MASK) >>
4492             PORT_HW_CFG_MEDIA_TYPE_PHY1_SHIFT;
4493         params->phy[ELINK_EXT_PHY2].media_type =
4494             (media_types & PORT_HW_CFG_MEDIA_TYPE_PHY2_MASK) >>
4495             PORT_HW_CFG_MEDIA_TYPE_PHY2_SHIFT;
4496         PMD_DRV_LOG(DEBUG, "media_types = 0x%x", media_types);
4497
4498         /* Sync AEU offset */
4499         sync_offset = params->shmem_base +
4500             offsetof(struct shmem_region,
4501                      dev_info.port_hw_config[port].aeu_int_mask);
4502
4503         vars->aeu_int_mask = REG_RD(sc, sync_offset);
4504
4505         /* Sync PFC status */
4506         if (vars->link_status & LINK_STATUS_PFC_ENABLED)
4507                 params->feature_config_flags |=
4508                     ELINK_FEATURE_CONFIG_PFC_ENABLED;
4509         else
4510                 params->feature_config_flags &=
4511                     ~ELINK_FEATURE_CONFIG_PFC_ENABLED;
4512
4513         if (SHMEM2_HAS(sc, link_attr_sync))
4514                 vars->link_attr_sync = SHMEM2_RD(sc,
4515                                                  link_attr_sync[params->port]);
4516
4517         PMD_DRV_LOG(DEBUG, "link_status 0x%x  phy_link_up %x int_mask 0x%x",
4518                     vars->link_status, vars->phy_link_up, vars->aeu_int_mask);
4519         PMD_DRV_LOG(DEBUG, "line_speed %x  duplex %x  flow_ctrl 0x%x",
4520                     vars->line_speed, vars->duplex, vars->flow_ctrl);
4521 }
4522
4523 static void elink_set_master_ln(struct elink_params *params,
4524                                 struct elink_phy *phy)
4525 {
4526         struct bnx2x_softc *sc = params->sc;
4527         uint16_t new_master_ln, ser_lane;
4528         ser_lane = ((params->lane_config &
4529                      PORT_HW_CFG_LANE_SWAP_CFG_MASTER_MASK) >>
4530                     PORT_HW_CFG_LANE_SWAP_CFG_MASTER_SHIFT);
4531
4532         /* Set the master_ln for AN */
4533         CL22_RD_OVER_CL45(sc, phy,
4534                           MDIO_REG_BANK_XGXS_BLOCK2,
4535                           MDIO_XGXS_BLOCK2_TEST_MODE_LANE, &new_master_ln);
4536
4537         CL22_WR_OVER_CL45(sc, phy,
4538                           MDIO_REG_BANK_XGXS_BLOCK2,
4539                           MDIO_XGXS_BLOCK2_TEST_MODE_LANE,
4540                           (new_master_ln | ser_lane));
4541 }
4542
4543 static elink_status_t elink_reset_unicore(struct elink_params *params,
4544                                           struct elink_phy *phy,
4545                                           uint8_t set_serdes)
4546 {
4547         struct bnx2x_softc *sc = params->sc;
4548         uint16_t mii_control;
4549         uint16_t i;
4550         CL22_RD_OVER_CL45(sc, phy,
4551                           MDIO_REG_BANK_COMBO_IEEE0,
4552                           MDIO_COMBO_IEEE0_MII_CONTROL, &mii_control);
4553
4554         /* Reset the unicore */
4555         CL22_WR_OVER_CL45(sc, phy,
4556                           MDIO_REG_BANK_COMBO_IEEE0,
4557                           MDIO_COMBO_IEEE0_MII_CONTROL,
4558                           (mii_control | MDIO_COMBO_IEEO_MII_CONTROL_RESET));
4559         if (set_serdes)
4560                 elink_set_serdes_access(sc, params->port);
4561
4562         /* Wait for the reset to self clear */
4563         for (i = 0; i < ELINK_MDIO_ACCESS_TIMEOUT; i++) {
4564                 DELAY(5);
4565
4566                 /* The reset erased the previous bank value */
4567                 CL22_RD_OVER_CL45(sc, phy,
4568                                   MDIO_REG_BANK_COMBO_IEEE0,
4569                                   MDIO_COMBO_IEEE0_MII_CONTROL, &mii_control);
4570
4571                 if (!(mii_control & MDIO_COMBO_IEEO_MII_CONTROL_RESET)) {
4572                         DELAY(5);
4573                         return ELINK_STATUS_OK;
4574                 }
4575         }
4576
4577         elink_cb_event_log(sc, ELINK_LOG_ID_PHY_UNINITIALIZED, params->port);   // "Warning: PHY was not initialized,"
4578         // " Port %d",
4579
4580         PMD_DRV_LOG(DEBUG, "BUG! XGXS is still in reset!");
4581         return ELINK_STATUS_ERROR;
4582
4583 }
4584
4585 static void elink_set_swap_lanes(struct elink_params *params,
4586                                  struct elink_phy *phy)
4587 {
4588         struct bnx2x_softc *sc = params->sc;
4589         /* Each two bits represents a lane number:
4590          * No swap is 0123 => 0x1b no need to enable the swap
4591          */
4592         uint16_t rx_lane_swap, tx_lane_swap;
4593
4594         rx_lane_swap = ((params->lane_config &
4595                          PORT_HW_CFG_LANE_SWAP_CFG_RX_MASK) >>
4596                         PORT_HW_CFG_LANE_SWAP_CFG_RX_SHIFT);
4597         tx_lane_swap = ((params->lane_config &
4598                          PORT_HW_CFG_LANE_SWAP_CFG_TX_MASK) >>
4599                         PORT_HW_CFG_LANE_SWAP_CFG_TX_SHIFT);
4600
4601         if (rx_lane_swap != 0x1b) {
4602                 CL22_WR_OVER_CL45(sc, phy,
4603                                   MDIO_REG_BANK_XGXS_BLOCK2,
4604                                   MDIO_XGXS_BLOCK2_RX_LN_SWAP,
4605                                   (rx_lane_swap |
4606                                    MDIO_XGXS_BLOCK2_RX_LN_SWAP_ENABLE |
4607                                    MDIO_XGXS_BLOCK2_RX_LN_SWAP_FORCE_ENABLE));
4608         } else {
4609                 CL22_WR_OVER_CL45(sc, phy,
4610                                   MDIO_REG_BANK_XGXS_BLOCK2,
4611                                   MDIO_XGXS_BLOCK2_RX_LN_SWAP, 0);
4612         }
4613
4614         if (tx_lane_swap != 0x1b) {
4615                 CL22_WR_OVER_CL45(sc, phy,
4616                                   MDIO_REG_BANK_XGXS_BLOCK2,
4617                                   MDIO_XGXS_BLOCK2_TX_LN_SWAP,
4618                                   (tx_lane_swap |
4619                                    MDIO_XGXS_BLOCK2_TX_LN_SWAP_ENABLE));
4620         } else {
4621                 CL22_WR_OVER_CL45(sc, phy,
4622                                   MDIO_REG_BANK_XGXS_BLOCK2,
4623                                   MDIO_XGXS_BLOCK2_TX_LN_SWAP, 0);
4624         }
4625 }
4626
4627 static void elink_set_parallel_detection(struct elink_phy *phy,
4628                                          struct elink_params *params)
4629 {
4630         struct bnx2x_softc *sc = params->sc;
4631         uint16_t control2;
4632         CL22_RD_OVER_CL45(sc, phy,
4633                           MDIO_REG_BANK_SERDES_DIGITAL,
4634                           MDIO_SERDES_DIGITAL_A_1000X_CONTROL2, &control2);
4635         if (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)
4636                 control2 |= MDIO_SERDES_DIGITAL_A_1000X_CONTROL2_PRL_DT_EN;
4637         else
4638                 control2 &= ~MDIO_SERDES_DIGITAL_A_1000X_CONTROL2_PRL_DT_EN;
4639         PMD_DRV_LOG(DEBUG, "phy->speed_cap_mask = 0x%x, control2 = 0x%x",
4640                     phy->speed_cap_mask, control2);
4641         CL22_WR_OVER_CL45(sc, phy,
4642                           MDIO_REG_BANK_SERDES_DIGITAL,
4643                           MDIO_SERDES_DIGITAL_A_1000X_CONTROL2, control2);
4644
4645         if ((phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT) &&
4646             (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)) {
4647                 PMD_DRV_LOG(DEBUG, "XGXS");
4648
4649                 CL22_WR_OVER_CL45(sc, phy,
4650                                   MDIO_REG_BANK_10G_PARALLEL_DETECT,
4651                                   MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_LINK,
4652                                   MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_LINK_CNT);
4653
4654                 CL22_RD_OVER_CL45(sc, phy,
4655                                   MDIO_REG_BANK_10G_PARALLEL_DETECT,
4656                                   MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_CONTROL,
4657                                   &control2);
4658
4659                 control2 |=
4660                     MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_CONTROL_PARDET10G_EN;
4661
4662                 CL22_WR_OVER_CL45(sc, phy,
4663                                   MDIO_REG_BANK_10G_PARALLEL_DETECT,
4664                                   MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_CONTROL,
4665                                   control2);
4666
4667                 /* Disable parallel detection of HiG */
4668                 CL22_WR_OVER_CL45(sc, phy,
4669                                   MDIO_REG_BANK_XGXS_BLOCK2,
4670                                   MDIO_XGXS_BLOCK2_UNICORE_MODE_10G,
4671                                   MDIO_XGXS_BLOCK2_UNICORE_MODE_10G_CX4_XGXS |
4672                                   MDIO_XGXS_BLOCK2_UNICORE_MODE_10G_HIGIG_XGXS);
4673         }
4674 }
4675
4676 static void elink_set_autoneg(struct elink_phy *phy,
4677                               struct elink_params *params,
4678                               struct elink_vars *vars, uint8_t enable_cl73)
4679 {
4680         struct bnx2x_softc *sc = params->sc;
4681         uint16_t reg_val;
4682
4683         /* CL37 Autoneg */
4684         CL22_RD_OVER_CL45(sc, phy,
4685                           MDIO_REG_BANK_COMBO_IEEE0,
4686                           MDIO_COMBO_IEEE0_MII_CONTROL, &reg_val);
4687
4688         /* CL37 Autoneg Enabled */
4689         if (vars->line_speed == ELINK_SPEED_AUTO_NEG)
4690                 reg_val |= MDIO_COMBO_IEEO_MII_CONTROL_AN_EN;
4691         else                    /* CL37 Autoneg Disabled */
4692                 reg_val &= ~(MDIO_COMBO_IEEO_MII_CONTROL_AN_EN |
4693                              MDIO_COMBO_IEEO_MII_CONTROL_RESTART_AN);
4694
4695         CL22_WR_OVER_CL45(sc, phy,
4696                           MDIO_REG_BANK_COMBO_IEEE0,
4697                           MDIO_COMBO_IEEE0_MII_CONTROL, reg_val);
4698
4699         /* Enable/Disable Autodetection */
4700
4701         CL22_RD_OVER_CL45(sc, phy,
4702                           MDIO_REG_BANK_SERDES_DIGITAL,
4703                           MDIO_SERDES_DIGITAL_A_1000X_CONTROL1, &reg_val);
4704         reg_val &= ~(MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_SIGNAL_DETECT_EN |
4705                      MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_INVERT_SIGNAL_DETECT);
4706         reg_val |= MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_FIBER_MODE;
4707         if (vars->line_speed == ELINK_SPEED_AUTO_NEG)
4708                 reg_val |= MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_AUTODET;
4709         else
4710                 reg_val &= ~MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_AUTODET;
4711
4712         CL22_WR_OVER_CL45(sc, phy,
4713                           MDIO_REG_BANK_SERDES_DIGITAL,
4714                           MDIO_SERDES_DIGITAL_A_1000X_CONTROL1, reg_val);
4715
4716         /* Enable TetonII and BAM autoneg */
4717         CL22_RD_OVER_CL45(sc, phy,
4718                           MDIO_REG_BANK_BAM_NEXT_PAGE,
4719                           MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL, &reg_val);
4720         if (vars->line_speed == ELINK_SPEED_AUTO_NEG) {
4721                 /* Enable BAM aneg Mode and TetonII aneg Mode */
4722                 reg_val |= (MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_BAM_MODE |
4723                             MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_TETON_AN);
4724         } else {
4725                 /* TetonII and BAM Autoneg Disabled */
4726                 reg_val &= ~(MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_BAM_MODE |
4727                              MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_TETON_AN);
4728         }
4729         CL22_WR_OVER_CL45(sc, phy,
4730                           MDIO_REG_BANK_BAM_NEXT_PAGE,
4731                           MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL, reg_val);
4732
4733         if (enable_cl73) {
4734                 /* Enable Cl73 FSM status bits */
4735                 CL22_WR_OVER_CL45(sc, phy,
4736                                   MDIO_REG_BANK_CL73_USERB0,
4737                                   MDIO_CL73_USERB0_CL73_UCTRL, 0xe);
4738
4739                 /* Enable BAM Station Manager */
4740                 CL22_WR_OVER_CL45(sc, phy,
4741                                   MDIO_REG_BANK_CL73_USERB0,
4742                                   MDIO_CL73_USERB0_CL73_BAM_CTRL1,
4743                                   MDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_EN |
4744                                   MDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_STATION_MNGR_EN
4745                                   |
4746                                   MDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_NP_AFTER_BP_EN);
4747
4748                 /* Advertise CL73 link speeds */
4749                 CL22_RD_OVER_CL45(sc, phy,
4750                                   MDIO_REG_BANK_CL73_IEEEB1,
4751                                   MDIO_CL73_IEEEB1_AN_ADV2, &reg_val);
4752                 if (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)
4753                         reg_val |= MDIO_CL73_IEEEB1_AN_ADV2_ADVR_10G_KX4;
4754                 if (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)
4755                         reg_val |= MDIO_CL73_IEEEB1_AN_ADV2_ADVR_1000M_KX;
4756
4757                 CL22_WR_OVER_CL45(sc, phy,
4758                                   MDIO_REG_BANK_CL73_IEEEB1,
4759                                   MDIO_CL73_IEEEB1_AN_ADV2, reg_val);
4760
4761                 /* CL73 Autoneg Enabled */
4762                 reg_val = MDIO_CL73_IEEEB0_CL73_AN_CONTROL_AN_EN;
4763
4764         } else                  /* CL73 Autoneg Disabled */
4765                 reg_val = 0;
4766
4767         CL22_WR_OVER_CL45(sc, phy,
4768                           MDIO_REG_BANK_CL73_IEEEB0,
4769                           MDIO_CL73_IEEEB0_CL73_AN_CONTROL, reg_val);
4770 }
4771
4772 /* Program SerDes, forced speed */
4773 static void elink_program_serdes(struct elink_phy *phy,
4774                                  struct elink_params *params,
4775                                  struct elink_vars *vars)
4776 {
4777         struct bnx2x_softc *sc = params->sc;
4778         uint16_t reg_val;
4779
4780         /* Program duplex, disable autoneg and sgmii */
4781         CL22_RD_OVER_CL45(sc, phy,
4782                           MDIO_REG_BANK_COMBO_IEEE0,
4783                           MDIO_COMBO_IEEE0_MII_CONTROL, &reg_val);
4784         reg_val &= ~(MDIO_COMBO_IEEO_MII_CONTROL_FULL_DUPLEX |
4785                      MDIO_COMBO_IEEO_MII_CONTROL_AN_EN |
4786                      MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_MASK);
4787         if (phy->req_duplex == DUPLEX_FULL)
4788                 reg_val |= MDIO_COMBO_IEEO_MII_CONTROL_FULL_DUPLEX;
4789         CL22_WR_OVER_CL45(sc, phy,
4790                           MDIO_REG_BANK_COMBO_IEEE0,
4791                           MDIO_COMBO_IEEE0_MII_CONTROL, reg_val);
4792
4793         /* Program speed
4794          *  - needed only if the speed is greater than 1G (2.5G or 10G)
4795          */
4796         CL22_RD_OVER_CL45(sc, phy,
4797                           MDIO_REG_BANK_SERDES_DIGITAL,
4798                           MDIO_SERDES_DIGITAL_MISC1, &reg_val);
4799         /* Clearing the speed value before setting the right speed */
4800         PMD_DRV_LOG(DEBUG, "MDIO_REG_BANK_SERDES_DIGITAL = 0x%x", reg_val);
4801
4802         reg_val &= ~(MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_MASK |
4803                      MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_SEL);
4804
4805         if (!((vars->line_speed == ELINK_SPEED_1000) ||
4806               (vars->line_speed == ELINK_SPEED_100) ||
4807               (vars->line_speed == ELINK_SPEED_10))) {
4808
4809                 reg_val |= (MDIO_SERDES_DIGITAL_MISC1_REFCLK_SEL_156_25M |
4810                             MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_SEL);
4811                 if (vars->line_speed == ELINK_SPEED_10000)
4812                         reg_val |=
4813                             MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_10G_CX4;
4814         }
4815
4816         CL22_WR_OVER_CL45(sc, phy,
4817                           MDIO_REG_BANK_SERDES_DIGITAL,
4818                           MDIO_SERDES_DIGITAL_MISC1, reg_val);
4819
4820 }
4821
4822 static void elink_set_brcm_cl37_advertisement(struct elink_phy *phy,
4823                                               struct elink_params *params)
4824 {
4825         struct bnx2x_softc *sc = params->sc;
4826         uint16_t val = 0;
4827
4828         /* Set extended capabilities */
4829         if (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G)
4830                 val |= MDIO_OVER_1G_UP1_2_5G;
4831         if (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)
4832                 val |= MDIO_OVER_1G_UP1_10G;
4833         CL22_WR_OVER_CL45(sc, phy,
4834                           MDIO_REG_BANK_OVER_1G, MDIO_OVER_1G_UP1, val);
4835
4836         CL22_WR_OVER_CL45(sc, phy,
4837                           MDIO_REG_BANK_OVER_1G, MDIO_OVER_1G_UP3, 0x400);
4838 }
4839
4840 static void elink_set_ieee_aneg_advertisement(struct elink_phy *phy,
4841                                               struct elink_params *params,
4842                                               uint16_t ieee_fc)
4843 {
4844         struct bnx2x_softc *sc = params->sc;
4845         uint16_t val;
4846         /* For AN, we are always publishing full duplex */
4847
4848         CL22_WR_OVER_CL45(sc, phy,
4849                           MDIO_REG_BANK_COMBO_IEEE0,
4850                           MDIO_COMBO_IEEE0_AUTO_NEG_ADV, ieee_fc);
4851         CL22_RD_OVER_CL45(sc, phy,
4852                           MDIO_REG_BANK_CL73_IEEEB1,
4853                           MDIO_CL73_IEEEB1_AN_ADV1, &val);
4854         val &= ~MDIO_CL73_IEEEB1_AN_ADV1_PAUSE_BOTH;
4855         val |= ((ieee_fc << 3) & MDIO_CL73_IEEEB1_AN_ADV1_PAUSE_MASK);
4856         CL22_WR_OVER_CL45(sc, phy,
4857                           MDIO_REG_BANK_CL73_IEEEB1,
4858                           MDIO_CL73_IEEEB1_AN_ADV1, val);
4859 }
4860
4861 static void elink_restart_autoneg(struct elink_phy *phy,
4862                                   struct elink_params *params,
4863                                   uint8_t enable_cl73)
4864 {
4865         struct bnx2x_softc *sc = params->sc;
4866         uint16_t mii_control;
4867
4868         PMD_DRV_LOG(DEBUG, "elink_restart_autoneg");
4869         /* Enable and restart BAM/CL37 aneg */
4870
4871         if (enable_cl73) {
4872                 CL22_RD_OVER_CL45(sc, phy,
4873                                   MDIO_REG_BANK_CL73_IEEEB0,
4874                                   MDIO_CL73_IEEEB0_CL73_AN_CONTROL,
4875                                   &mii_control);
4876
4877                 CL22_WR_OVER_CL45(sc, phy,
4878                                   MDIO_REG_BANK_CL73_IEEEB0,
4879                                   MDIO_CL73_IEEEB0_CL73_AN_CONTROL,
4880                                   (mii_control |
4881                                    MDIO_CL73_IEEEB0_CL73_AN_CONTROL_AN_EN |
4882                                    MDIO_CL73_IEEEB0_CL73_AN_CONTROL_RESTART_AN));
4883         } else {
4884
4885                 CL22_RD_OVER_CL45(sc, phy,
4886                                   MDIO_REG_BANK_COMBO_IEEE0,
4887                                   MDIO_COMBO_IEEE0_MII_CONTROL, &mii_control);
4888                 PMD_DRV_LOG(DEBUG,
4889                             "elink_restart_autoneg mii_control before = 0x%x",
4890                             mii_control);
4891                 CL22_WR_OVER_CL45(sc, phy,
4892                                   MDIO_REG_BANK_COMBO_IEEE0,
4893                                   MDIO_COMBO_IEEE0_MII_CONTROL,
4894                                   (mii_control |
4895                                    MDIO_COMBO_IEEO_MII_CONTROL_AN_EN |
4896                                    MDIO_COMBO_IEEO_MII_CONTROL_RESTART_AN));
4897         }
4898 }
4899
4900 static void elink_initialize_sgmii_process(struct elink_phy *phy,
4901                                            struct elink_params *params,
4902                                            struct elink_vars *vars)
4903 {
4904         struct bnx2x_softc *sc = params->sc;
4905         uint16_t control1;
4906
4907         /* In SGMII mode, the unicore is always slave */
4908
4909         CL22_RD_OVER_CL45(sc, phy,
4910                           MDIO_REG_BANK_SERDES_DIGITAL,
4911                           MDIO_SERDES_DIGITAL_A_1000X_CONTROL1, &control1);
4912         control1 |= MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_INVERT_SIGNAL_DETECT;
4913         /* Set sgmii mode (and not fiber) */
4914         control1 &= ~(MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_FIBER_MODE |
4915                       MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_AUTODET |
4916                       MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_MSTR_MODE);
4917         CL22_WR_OVER_CL45(sc, phy,
4918                           MDIO_REG_BANK_SERDES_DIGITAL,
4919                           MDIO_SERDES_DIGITAL_A_1000X_CONTROL1, control1);
4920
4921         /* If forced speed */
4922         if (!(vars->line_speed == ELINK_SPEED_AUTO_NEG)) {
4923                 /* Set speed, disable autoneg */
4924                 uint16_t mii_control;
4925
4926                 CL22_RD_OVER_CL45(sc, phy,
4927                                   MDIO_REG_BANK_COMBO_IEEE0,
4928                                   MDIO_COMBO_IEEE0_MII_CONTROL, &mii_control);
4929                 mii_control &= ~(MDIO_COMBO_IEEO_MII_CONTROL_AN_EN |
4930                                  MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_MASK |
4931                                  MDIO_COMBO_IEEO_MII_CONTROL_FULL_DUPLEX);
4932
4933                 switch (vars->line_speed) {
4934                 case ELINK_SPEED_100:
4935                         mii_control |=
4936                             MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_100;
4937                         break;
4938                 case ELINK_SPEED_1000:
4939                         mii_control |=
4940                             MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_1000;
4941                         break;
4942                 case ELINK_SPEED_10:
4943                         /* There is nothing to set for 10M */
4944                         break;
4945                 default:
4946                         /* Invalid speed for SGMII */
4947                         PMD_DRV_LOG(DEBUG, "Invalid line_speed 0x%x",
4948                                     vars->line_speed);
4949                         break;
4950                 }
4951
4952                 /* Setting the full duplex */
4953                 if (phy->req_duplex == DUPLEX_FULL)
4954                         mii_control |= MDIO_COMBO_IEEO_MII_CONTROL_FULL_DUPLEX;
4955                 CL22_WR_OVER_CL45(sc, phy,
4956                                   MDIO_REG_BANK_COMBO_IEEE0,
4957                                   MDIO_COMBO_IEEE0_MII_CONTROL, mii_control);
4958
4959         } else {                /* AN mode */
4960                 /* Enable and restart AN */
4961                 elink_restart_autoneg(phy, params, 0);
4962         }
4963 }
4964
4965 /* Link management
4966  */
4967 static elink_status_t elink_direct_parallel_detect_used(struct elink_phy *phy,
4968                                                         struct elink_params
4969                                                         *params)
4970 {
4971         struct bnx2x_softc *sc = params->sc;
4972         uint16_t pd_10g, status2_1000x;
4973         if (phy->req_line_speed != ELINK_SPEED_AUTO_NEG)
4974                 return ELINK_STATUS_OK;
4975         CL22_RD_OVER_CL45(sc, phy,
4976                           MDIO_REG_BANK_SERDES_DIGITAL,
4977                           MDIO_SERDES_DIGITAL_A_1000X_STATUS2, &status2_1000x);
4978         CL22_RD_OVER_CL45(sc, phy,
4979                           MDIO_REG_BANK_SERDES_DIGITAL,
4980                           MDIO_SERDES_DIGITAL_A_1000X_STATUS2, &status2_1000x);
4981         if (status2_1000x & MDIO_SERDES_DIGITAL_A_1000X_STATUS2_AN_DISABLED) {
4982                 PMD_DRV_LOG(DEBUG, "1G parallel detect link on port %d",
4983                             params->port);
4984                 return ELINK_STATUS_ERROR;
4985         }
4986
4987         CL22_RD_OVER_CL45(sc, phy,
4988                           MDIO_REG_BANK_10G_PARALLEL_DETECT,
4989                           MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_STATUS, &pd_10g);
4990
4991         if (pd_10g & MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_STATUS_PD_LINK) {
4992                 PMD_DRV_LOG(DEBUG, "10G parallel detect link on port %d",
4993                             params->port);
4994                 return ELINK_STATUS_ERROR;
4995         }
4996         return ELINK_STATUS_OK;
4997 }
4998
4999 static void elink_update_adv_fc(struct elink_phy *phy,
5000                                 struct elink_params *params,
5001                                 struct elink_vars *vars, uint32_t gp_status)
5002 {
5003         uint16_t ld_pause;      /* local driver */
5004         uint16_t lp_pause;      /* link partner */
5005         uint16_t pause_result;
5006         struct bnx2x_softc *sc = params->sc;
5007         if ((gp_status &
5008              (MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_AUTONEG_COMPLETE |
5009               MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_MR_LP_NP_AN_ABLE)) ==
5010             (MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_AUTONEG_COMPLETE |
5011              MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_MR_LP_NP_AN_ABLE)) {
5012
5013                 CL22_RD_OVER_CL45(sc, phy,
5014                                   MDIO_REG_BANK_CL73_IEEEB1,
5015                                   MDIO_CL73_IEEEB1_AN_ADV1, &ld_pause);
5016                 CL22_RD_OVER_CL45(sc, phy,
5017                                   MDIO_REG_BANK_CL73_IEEEB1,
5018                                   MDIO_CL73_IEEEB1_AN_LP_ADV1, &lp_pause);
5019                 pause_result = (ld_pause &
5020                                 MDIO_CL73_IEEEB1_AN_ADV1_PAUSE_MASK) >> 8;
5021                 pause_result |= (lp_pause &
5022                                  MDIO_CL73_IEEEB1_AN_LP_ADV1_PAUSE_MASK) >> 10;
5023                 PMD_DRV_LOG(DEBUG, "pause_result CL73 0x%x", pause_result);
5024         } else {
5025                 CL22_RD_OVER_CL45(sc, phy,
5026                                   MDIO_REG_BANK_COMBO_IEEE0,
5027                                   MDIO_COMBO_IEEE0_AUTO_NEG_ADV, &ld_pause);
5028                 CL22_RD_OVER_CL45(sc, phy,
5029                                   MDIO_REG_BANK_COMBO_IEEE0,
5030                                   MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1,
5031                                   &lp_pause);
5032                 pause_result = (ld_pause &
5033                                 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_MASK) >> 5;
5034                 pause_result |= (lp_pause &
5035                                  MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_MASK) >> 7;
5036                 PMD_DRV_LOG(DEBUG, "pause_result CL37 0x%x", pause_result);
5037         }
5038         elink_pause_resolve(vars, pause_result);
5039
5040 }
5041
5042 static void elink_flow_ctrl_resolve(struct elink_phy *phy,
5043                                     struct elink_params *params,
5044                                     struct elink_vars *vars, uint32_t gp_status)
5045 {
5046         vars->flow_ctrl = ELINK_FLOW_CTRL_NONE;
5047
5048         /* Resolve from gp_status in case of AN complete and not sgmii */
5049         if (phy->req_flow_ctrl != ELINK_FLOW_CTRL_AUTO) {
5050                 /* Update the advertised flow-controled of LD/LP in AN */
5051                 if (phy->req_line_speed == ELINK_SPEED_AUTO_NEG)
5052                         elink_update_adv_fc(phy, params, vars, gp_status);
5053                 /* But set the flow-control result as the requested one */
5054                 vars->flow_ctrl = phy->req_flow_ctrl;
5055         } else if (phy->req_line_speed != ELINK_SPEED_AUTO_NEG)
5056                 vars->flow_ctrl = params->req_fc_auto_adv;
5057         else if ((gp_status & ELINK_MDIO_AN_CL73_OR_37_COMPLETE) &&
5058                  (!(vars->phy_flags & PHY_SGMII_FLAG))) {
5059                 if (elink_direct_parallel_detect_used(phy, params)) {
5060                         vars->flow_ctrl = params->req_fc_auto_adv;
5061                         return;
5062                 }
5063                 elink_update_adv_fc(phy, params, vars, gp_status);
5064         }
5065         PMD_DRV_LOG(DEBUG, "flow_ctrl 0x%x", vars->flow_ctrl);
5066 }
5067
5068 static void elink_check_fallback_to_cl37(struct elink_phy *phy,
5069                                          struct elink_params *params)
5070 {
5071         struct bnx2x_softc *sc = params->sc;
5072         uint16_t rx_status, ustat_val, cl37_fsm_received;
5073         PMD_DRV_LOG(DEBUG, "elink_check_fallback_to_cl37");
5074         /* Step 1: Make sure signal is detected */
5075         CL22_RD_OVER_CL45(sc, phy,
5076                           MDIO_REG_BANK_RX0, MDIO_RX0_RX_STATUS, &rx_status);
5077         if ((rx_status & MDIO_RX0_RX_STATUS_SIGDET) !=
5078             (MDIO_RX0_RX_STATUS_SIGDET)) {
5079                 PMD_DRV_LOG(DEBUG, "Signal is not detected. Restoring CL73."
5080                             "rx_status(0x80b0) = 0x%x", rx_status);
5081                 CL22_WR_OVER_CL45(sc, phy,
5082                                   MDIO_REG_BANK_CL73_IEEEB0,
5083                                   MDIO_CL73_IEEEB0_CL73_AN_CONTROL,
5084                                   MDIO_CL73_IEEEB0_CL73_AN_CONTROL_AN_EN);
5085                 return;
5086         }
5087         /* Step 2: Check CL73 state machine */
5088         CL22_RD_OVER_CL45(sc, phy,
5089                           MDIO_REG_BANK_CL73_USERB0,
5090                           MDIO_CL73_USERB0_CL73_USTAT1, &ustat_val);
5091         if ((ustat_val &
5092              (MDIO_CL73_USERB0_CL73_USTAT1_LINK_STATUS_CHECK |
5093               MDIO_CL73_USERB0_CL73_USTAT1_AN_GOOD_CHECK_BAM37)) !=
5094             (MDIO_CL73_USERB0_CL73_USTAT1_LINK_STATUS_CHECK |
5095              MDIO_CL73_USERB0_CL73_USTAT1_AN_GOOD_CHECK_BAM37)) {
5096                 PMD_DRV_LOG(DEBUG, "CL73 state-machine is not stable. "
5097                             "ustat_val(0x8371) = 0x%x", ustat_val);
5098                 return;
5099         }
5100         /* Step 3: Check CL37 Message Pages received to indicate LP
5101          * supports only CL37
5102          */
5103         CL22_RD_OVER_CL45(sc, phy,
5104                           MDIO_REG_BANK_REMOTE_PHY,
5105                           MDIO_REMOTE_PHY_MISC_RX_STATUS, &cl37_fsm_received);
5106         if ((cl37_fsm_received &
5107              (MDIO_REMOTE_PHY_MISC_RX_STATUS_CL37_FSM_RECEIVED_OVER1G_MSG |
5108               MDIO_REMOTE_PHY_MISC_RX_STATUS_CL37_FSM_RECEIVED_BRCM_OUI_MSG)) !=
5109             (MDIO_REMOTE_PHY_MISC_RX_STATUS_CL37_FSM_RECEIVED_OVER1G_MSG |
5110              MDIO_REMOTE_PHY_MISC_RX_STATUS_CL37_FSM_RECEIVED_BRCM_OUI_MSG)) {
5111                 PMD_DRV_LOG(DEBUG, "No CL37 FSM were received. "
5112                             "misc_rx_status(0x8330) = 0x%x", cl37_fsm_received);
5113                 return;
5114         }
5115         /* The combined cl37/cl73 fsm state information indicating that
5116          * we are connected to a device which does not support cl73, but
5117          * does support cl37 BAM. In this case we disable cl73 and
5118          * restart cl37 auto-neg
5119          */
5120
5121         /* Disable CL73 */
5122         CL22_WR_OVER_CL45(sc, phy,
5123                           MDIO_REG_BANK_CL73_IEEEB0,
5124                           MDIO_CL73_IEEEB0_CL73_AN_CONTROL, 0);
5125         /* Restart CL37 autoneg */
5126         elink_restart_autoneg(phy, params, 0);
5127         PMD_DRV_LOG(DEBUG, "Disabling CL73, and restarting CL37 autoneg");
5128 }
5129
5130 static void elink_xgxs_an_resolve(struct elink_phy *phy,
5131                                   struct elink_params *params,
5132                                   struct elink_vars *vars, uint32_t gp_status)
5133 {
5134         if (gp_status & ELINK_MDIO_AN_CL73_OR_37_COMPLETE)
5135                 vars->link_status |= LINK_STATUS_AUTO_NEGOTIATE_COMPLETE;
5136
5137         if (elink_direct_parallel_detect_used(phy, params))
5138                 vars->link_status |= LINK_STATUS_PARALLEL_DETECTION_USED;
5139 }
5140
5141 static elink_status_t elink_get_link_speed_duplex(struct elink_phy *phy,
5142                                                   struct elink_params *params __rte_unused,
5143                                                   struct elink_vars *vars,
5144                                                   uint16_t is_link_up,
5145                                                   uint16_t speed_mask,
5146                                                   uint16_t is_duplex)
5147 {
5148         if (phy->req_line_speed == ELINK_SPEED_AUTO_NEG)
5149                 vars->link_status |= LINK_STATUS_AUTO_NEGOTIATE_ENABLED;
5150         if (is_link_up) {
5151                 PMD_DRV_LOG(DEBUG, "phy link up");
5152
5153                 vars->phy_link_up = 1;
5154                 vars->link_status |= LINK_STATUS_LINK_UP;
5155
5156                 switch (speed_mask) {
5157                 case ELINK_GP_STATUS_10M:
5158                         vars->line_speed = ELINK_SPEED_10;
5159                         if (is_duplex == DUPLEX_FULL)
5160                                 vars->link_status |= ELINK_LINK_10TFD;
5161                         else
5162                                 vars->link_status |= ELINK_LINK_10THD;
5163                         break;
5164
5165                 case ELINK_GP_STATUS_100M:
5166                         vars->line_speed = ELINK_SPEED_100;
5167                         if (is_duplex == DUPLEX_FULL)
5168                                 vars->link_status |= ELINK_LINK_100TXFD;
5169                         else
5170                                 vars->link_status |= ELINK_LINK_100TXHD;
5171                         break;
5172
5173                 case ELINK_GP_STATUS_1G:
5174                 case ELINK_GP_STATUS_1G_KX:
5175                         vars->line_speed = ELINK_SPEED_1000;
5176                         if (is_duplex == DUPLEX_FULL)
5177                                 vars->link_status |= ELINK_LINK_1000TFD;
5178                         else
5179                                 vars->link_status |= ELINK_LINK_1000THD;
5180                         break;
5181
5182                 case ELINK_GP_STATUS_2_5G:
5183                         vars->line_speed = ELINK_SPEED_2500;
5184                         if (is_duplex == DUPLEX_FULL)
5185                                 vars->link_status |= ELINK_LINK_2500TFD;
5186                         else
5187                                 vars->link_status |= ELINK_LINK_2500THD;
5188                         break;
5189
5190                 case ELINK_GP_STATUS_5G:
5191                 case ELINK_GP_STATUS_6G:
5192                         PMD_DRV_LOG(DEBUG,
5193                                     "link speed unsupported  gp_status 0x%x",
5194                                     speed_mask);
5195                         return ELINK_STATUS_ERROR;
5196
5197                 case ELINK_GP_STATUS_10G_KX4:
5198                 case ELINK_GP_STATUS_10G_HIG:
5199                 case ELINK_GP_STATUS_10G_CX4:
5200                 case ELINK_GP_STATUS_10G_KR:
5201                 case ELINK_GP_STATUS_10G_SFI:
5202                 case ELINK_GP_STATUS_10G_XFI:
5203                         vars->line_speed = ELINK_SPEED_10000;
5204                         vars->link_status |= ELINK_LINK_10GTFD;
5205                         break;
5206                 case ELINK_GP_STATUS_20G_DXGXS:
5207                 case ELINK_GP_STATUS_20G_KR2:
5208                         vars->line_speed = ELINK_SPEED_20000;
5209                         vars->link_status |= ELINK_LINK_20GTFD;
5210                         break;
5211                 default:
5212                         PMD_DRV_LOG(DEBUG,
5213                                     "link speed unsupported gp_status 0x%x",
5214                                     speed_mask);
5215                         return ELINK_STATUS_ERROR;
5216                 }
5217         } else {                /* link_down */
5218                 PMD_DRV_LOG(DEBUG, "phy link down");
5219
5220                 vars->phy_link_up = 0;
5221
5222                 vars->duplex = DUPLEX_FULL;
5223                 vars->flow_ctrl = ELINK_FLOW_CTRL_NONE;
5224                 vars->mac_type = ELINK_MAC_TYPE_NONE;
5225         }
5226         PMD_DRV_LOG(DEBUG, " phy_link_up %x line_speed %d",
5227                     vars->phy_link_up, vars->line_speed);
5228         return ELINK_STATUS_OK;
5229 }
5230
5231 static uint8_t elink_link_settings_status(struct elink_phy *phy,
5232                                           struct elink_params *params,
5233                                           struct elink_vars *vars)
5234 {
5235         struct bnx2x_softc *sc = params->sc;
5236
5237         uint16_t gp_status, duplex = DUPLEX_HALF, link_up = 0, speed_mask;
5238         elink_status_t rc = ELINK_STATUS_OK;
5239
5240         /* Read gp_status */
5241         CL22_RD_OVER_CL45(sc, phy,
5242                           MDIO_REG_BANK_GP_STATUS,
5243                           MDIO_GP_STATUS_TOP_AN_STATUS1, &gp_status);
5244         if (gp_status & MDIO_GP_STATUS_TOP_AN_STATUS1_DUPLEX_STATUS)
5245                 duplex = DUPLEX_FULL;
5246         if (gp_status & MDIO_GP_STATUS_TOP_AN_STATUS1_LINK_STATUS)
5247                 link_up = 1;
5248         speed_mask = gp_status & ELINK_GP_STATUS_SPEED_MASK;
5249         PMD_DRV_LOG(DEBUG, "gp_status 0x%x, is_link_up %d, speed_mask 0x%x",
5250                     gp_status, link_up, speed_mask);
5251         rc = elink_get_link_speed_duplex(phy, params, vars, link_up, speed_mask,
5252                                          duplex);
5253         if (rc == ELINK_STATUS_ERROR)
5254                 return rc;
5255
5256         if (gp_status & MDIO_GP_STATUS_TOP_AN_STATUS1_LINK_STATUS) {
5257                 if (ELINK_SINGLE_MEDIA_DIRECT(params)) {
5258                         vars->duplex = duplex;
5259                         elink_flow_ctrl_resolve(phy, params, vars, gp_status);
5260                         if (phy->req_line_speed == ELINK_SPEED_AUTO_NEG)
5261                                 elink_xgxs_an_resolve(phy, params, vars,
5262                                                       gp_status);
5263                 }
5264         } else {                /* Link_down */
5265                 if ((phy->req_line_speed == ELINK_SPEED_AUTO_NEG) &&
5266                     ELINK_SINGLE_MEDIA_DIRECT(params)) {
5267                         /* Check signal is detected */
5268                         elink_check_fallback_to_cl37(phy, params);
5269                 }
5270         }
5271
5272         /* Read LP advertised speeds */
5273         if (ELINK_SINGLE_MEDIA_DIRECT(params) &&
5274             (vars->link_status & LINK_STATUS_AUTO_NEGOTIATE_COMPLETE)) {
5275                 uint16_t val;
5276
5277                 CL22_RD_OVER_CL45(sc, phy, MDIO_REG_BANK_CL73_IEEEB1,
5278                                   MDIO_CL73_IEEEB1_AN_LP_ADV2, &val);
5279
5280                 if (val & MDIO_CL73_IEEEB1_AN_ADV2_ADVR_1000M_KX)
5281                         vars->link_status |=
5282                             LINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE;
5283                 if (val & (MDIO_CL73_IEEEB1_AN_ADV2_ADVR_10G_KX4 |
5284                            MDIO_CL73_IEEEB1_AN_ADV2_ADVR_10G_KR))
5285                         vars->link_status |=
5286                             LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE;
5287
5288                 CL22_RD_OVER_CL45(sc, phy, MDIO_REG_BANK_OVER_1G,
5289                                   MDIO_OVER_1G_LP_UP1, &val);
5290
5291                 if (val & MDIO_OVER_1G_UP1_2_5G)
5292                         vars->link_status |=
5293                             LINK_STATUS_LINK_PARTNER_2500XFD_CAPABLE;
5294                 if (val & (MDIO_OVER_1G_UP1_10G | MDIO_OVER_1G_UP1_10GH))
5295                         vars->link_status |=
5296                             LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE;
5297         }
5298
5299         PMD_DRV_LOG(DEBUG, "duplex %x  flow_ctrl 0x%x link_status 0x%x",
5300                     vars->duplex, vars->flow_ctrl, vars->link_status);
5301         return rc;
5302 }
5303
5304 static uint8_t elink_warpcore_read_status(struct elink_phy *phy,
5305                                           struct elink_params *params,
5306                                           struct elink_vars *vars)
5307 {
5308         struct bnx2x_softc *sc = params->sc;
5309         uint8_t lane;
5310         uint16_t gp_status1, gp_speed, link_up, duplex = DUPLEX_FULL;
5311         elink_status_t rc = ELINK_STATUS_OK;
5312         lane = elink_get_warpcore_lane(params);
5313         /* Read gp_status */
5314         if ((params->loopback_mode) && (phy->flags & ELINK_FLAGS_WC_DUAL_MODE)) {
5315                 elink_cl45_read(sc, phy, MDIO_WC_DEVAD,
5316                                 MDIO_WC_REG_DIGITAL5_LINK_STATUS, &link_up);
5317                 elink_cl45_read(sc, phy, MDIO_WC_DEVAD,
5318                                 MDIO_WC_REG_DIGITAL5_LINK_STATUS, &link_up);
5319                 link_up &= 0x1;
5320         } else if ((phy->req_line_speed > ELINK_SPEED_10000) &&
5321                    (phy->supported & ELINK_SUPPORTED_20000baseMLD2_Full)) {
5322                 uint16_t temp_link_up;
5323                 elink_cl45_read(sc, phy, MDIO_WC_DEVAD, 1, &temp_link_up);
5324                 elink_cl45_read(sc, phy, MDIO_WC_DEVAD, 1, &link_up);
5325                 PMD_DRV_LOG(DEBUG, "PCS RX link status = 0x%x-->0x%x",
5326                             temp_link_up, link_up);
5327                 link_up &= (1 << 2);
5328                 if (link_up)
5329                         elink_ext_phy_resolve_fc(phy, params, vars);
5330         } else {
5331                 elink_cl45_read(sc, phy, MDIO_WC_DEVAD,
5332                                 MDIO_WC_REG_GP2_STATUS_GP_2_1, &gp_status1);
5333                 PMD_DRV_LOG(DEBUG, "0x81d1 = 0x%x", gp_status1);
5334                 /* Check for either KR, 1G, or AN up. */
5335                 link_up = ((gp_status1 >> 8) |
5336                            (gp_status1 >> 12) | (gp_status1)) & (1 << lane);
5337                 if (phy->supported & ELINK_SUPPORTED_20000baseKR2_Full) {
5338                         uint16_t an_link;
5339                         elink_cl45_read(sc, phy, MDIO_AN_DEVAD,
5340                                         MDIO_AN_REG_STATUS, &an_link);
5341                         elink_cl45_read(sc, phy, MDIO_AN_DEVAD,
5342                                         MDIO_AN_REG_STATUS, &an_link);
5343                         link_up |= (an_link & (1 << 2));
5344                 }
5345                 if (link_up && ELINK_SINGLE_MEDIA_DIRECT(params)) {
5346                         uint16_t pd, gp_status4;
5347                         if (phy->req_line_speed == ELINK_SPEED_AUTO_NEG) {
5348                                 /* Check Autoneg complete */
5349                                 elink_cl45_read(sc, phy, MDIO_WC_DEVAD,
5350                                                 MDIO_WC_REG_GP2_STATUS_GP_2_4,
5351                                                 &gp_status4);
5352                                 if (gp_status4 & ((1 << 12) << lane))
5353                                         vars->link_status |=
5354                                             LINK_STATUS_AUTO_NEGOTIATE_COMPLETE;
5355
5356                                 /* Check parallel detect used */
5357                                 elink_cl45_read(sc, phy, MDIO_WC_DEVAD,
5358                                                 MDIO_WC_REG_PAR_DET_10G_STATUS,
5359                                                 &pd);
5360                                 if (pd & (1 << 15))
5361                                         vars->link_status |=
5362                                             LINK_STATUS_PARALLEL_DETECTION_USED;
5363                         }
5364                         elink_ext_phy_resolve_fc(phy, params, vars);
5365                         vars->duplex = duplex;
5366                 }
5367         }
5368
5369         if ((vars->link_status & LINK_STATUS_AUTO_NEGOTIATE_COMPLETE) &&
5370             ELINK_SINGLE_MEDIA_DIRECT(params)) {
5371                 uint16_t val;
5372
5373                 elink_cl45_read(sc, phy, MDIO_AN_DEVAD,
5374                                 MDIO_AN_REG_LP_AUTO_NEG2, &val);
5375
5376                 if (val & MDIO_CL73_IEEEB1_AN_ADV2_ADVR_1000M_KX)
5377                         vars->link_status |=
5378                             LINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE;
5379                 if (val & (MDIO_CL73_IEEEB1_AN_ADV2_ADVR_10G_KX4 |
5380                            MDIO_CL73_IEEEB1_AN_ADV2_ADVR_10G_KR))
5381                         vars->link_status |=
5382                             LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE;
5383
5384                 elink_cl45_read(sc, phy, MDIO_WC_DEVAD,
5385                                 MDIO_WC_REG_DIGITAL3_LP_UP1, &val);
5386
5387                 if (val & MDIO_OVER_1G_UP1_2_5G)
5388                         vars->link_status |=
5389                             LINK_STATUS_LINK_PARTNER_2500XFD_CAPABLE;
5390                 if (val & (MDIO_OVER_1G_UP1_10G | MDIO_OVER_1G_UP1_10GH))
5391                         vars->link_status |=
5392                             LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE;
5393
5394         }
5395
5396         if (lane < 2) {
5397                 elink_cl45_read(sc, phy, MDIO_WC_DEVAD,
5398                                 MDIO_WC_REG_GP2_STATUS_GP_2_2, &gp_speed);
5399         } else {
5400                 elink_cl45_read(sc, phy, MDIO_WC_DEVAD,
5401                                 MDIO_WC_REG_GP2_STATUS_GP_2_3, &gp_speed);
5402         }
5403         PMD_DRV_LOG(DEBUG, "lane %d gp_speed 0x%x", lane, gp_speed);
5404
5405         if ((lane & 1) == 0)
5406                 gp_speed <<= 8;
5407         gp_speed &= 0x3f00;
5408         link_up = ! !link_up;
5409
5410         /* Reset the TX FIFO to fix SGMII issue */
5411         rc = elink_get_link_speed_duplex(phy, params, vars, link_up, gp_speed,
5412                                          duplex);
5413
5414         /* In case of KR link down, start up the recovering procedure */
5415         if ((!link_up) && (phy->media_type == ELINK_ETH_PHY_KR) &&
5416             (!(phy->flags & ELINK_FLAGS_WC_DUAL_MODE)))
5417                 vars->rx_tx_asic_rst = MAX_KR_LINK_RETRY;
5418
5419         PMD_DRV_LOG(DEBUG, "duplex %x  flow_ctrl 0x%x link_status 0x%x",
5420                     vars->duplex, vars->flow_ctrl, vars->link_status);
5421         return rc;
5422 }
5423
5424 static void elink_set_gmii_tx_driver(struct elink_params *params)
5425 {
5426         struct bnx2x_softc *sc = params->sc;
5427         struct elink_phy *phy = &params->phy[ELINK_INT_PHY];
5428         uint16_t lp_up2;
5429         uint16_t tx_driver;
5430         uint16_t bank;
5431
5432         /* Read precomp */
5433         CL22_RD_OVER_CL45(sc, phy,
5434                           MDIO_REG_BANK_OVER_1G, MDIO_OVER_1G_LP_UP2, &lp_up2);
5435
5436         /* Bits [10:7] at lp_up2, positioned at [15:12] */
5437         lp_up2 = (((lp_up2 & MDIO_OVER_1G_LP_UP2_PREEMPHASIS_MASK) >>
5438                    MDIO_OVER_1G_LP_UP2_PREEMPHASIS_SHIFT) <<
5439                   MDIO_TX0_TX_DRIVER_PREEMPHASIS_SHIFT);
5440
5441         if (lp_up2 == 0)
5442                 return;
5443
5444         for (bank = MDIO_REG_BANK_TX0; bank <= MDIO_REG_BANK_TX3;
5445              bank += (MDIO_REG_BANK_TX1 - MDIO_REG_BANK_TX0)) {
5446                 CL22_RD_OVER_CL45(sc, phy,
5447                                   bank, MDIO_TX0_TX_DRIVER, &tx_driver);
5448
5449                 /* Replace tx_driver bits [15:12] */
5450                 if (lp_up2 != (tx_driver & MDIO_TX0_TX_DRIVER_PREEMPHASIS_MASK)) {
5451                         tx_driver &= ~MDIO_TX0_TX_DRIVER_PREEMPHASIS_MASK;
5452                         tx_driver |= lp_up2;
5453                         CL22_WR_OVER_CL45(sc, phy,
5454                                           bank, MDIO_TX0_TX_DRIVER, tx_driver);
5455                 }
5456         }
5457 }
5458
5459 static elink_status_t elink_emac_program(struct elink_params *params,
5460                                          struct elink_vars *vars)
5461 {
5462         struct bnx2x_softc *sc = params->sc;
5463         uint8_t port = params->port;
5464         uint16_t mode = 0;
5465
5466         PMD_DRV_LOG(DEBUG, "setting link speed & duplex");
5467         elink_bits_dis(sc, GRCBASE_EMAC0 + port * 0x400 +
5468                        EMAC_REG_EMAC_MODE,
5469                        (EMAC_MODE_25G_MODE |
5470                         EMAC_MODE_PORT_MII_10M | EMAC_MODE_HALF_DUPLEX));
5471         switch (vars->line_speed) {
5472         case ELINK_SPEED_10:
5473                 mode |= EMAC_MODE_PORT_MII_10M;
5474                 break;
5475
5476         case ELINK_SPEED_100:
5477                 mode |= EMAC_MODE_PORT_MII;
5478                 break;
5479
5480         case ELINK_SPEED_1000:
5481                 mode |= EMAC_MODE_PORT_GMII;
5482                 break;
5483
5484         case ELINK_SPEED_2500:
5485                 mode |= (EMAC_MODE_25G_MODE | EMAC_MODE_PORT_GMII);
5486                 break;
5487
5488         default:
5489                 /* 10G not valid for EMAC */
5490                 PMD_DRV_LOG(DEBUG, "Invalid line_speed 0x%x", vars->line_speed);
5491                 return ELINK_STATUS_ERROR;
5492         }
5493
5494         if (vars->duplex == DUPLEX_HALF)
5495                 mode |= EMAC_MODE_HALF_DUPLEX;
5496         elink_bits_en(sc,
5497                       GRCBASE_EMAC0 + port * 0x400 + EMAC_REG_EMAC_MODE, mode);
5498
5499         elink_set_led(params, vars, ELINK_LED_MODE_OPER, vars->line_speed);
5500         return ELINK_STATUS_OK;
5501 }
5502
5503 static void elink_set_preemphasis(struct elink_phy *phy,
5504                                   struct elink_params *params)
5505 {
5506
5507         uint16_t bank, i = 0;
5508         struct bnx2x_softc *sc = params->sc;
5509
5510         for (bank = MDIO_REG_BANK_RX0, i = 0; bank <= MDIO_REG_BANK_RX3;
5511              bank += (MDIO_REG_BANK_RX1 - MDIO_REG_BANK_RX0), i++) {
5512                 CL22_WR_OVER_CL45(sc, phy,
5513                                   bank,
5514                                   MDIO_RX0_RX_EQ_BOOST, phy->rx_preemphasis[i]);
5515         }
5516
5517         for (bank = MDIO_REG_BANK_TX0, i = 0; bank <= MDIO_REG_BANK_TX3;
5518              bank += (MDIO_REG_BANK_TX1 - MDIO_REG_BANK_TX0), i++) {
5519                 CL22_WR_OVER_CL45(sc, phy,
5520                                   bank,
5521                                   MDIO_TX0_TX_DRIVER, phy->tx_preemphasis[i]);
5522         }
5523 }
5524
5525 static uint8_t elink_xgxs_config_init(struct elink_phy *phy,
5526                                       struct elink_params *params,
5527                                       struct elink_vars *vars)
5528 {
5529         uint8_t enable_cl73 = (ELINK_SINGLE_MEDIA_DIRECT(params) ||
5530                                (params->loopback_mode == ELINK_LOOPBACK_XGXS));
5531
5532         if (!(vars->phy_flags & PHY_SGMII_FLAG)) {
5533                 if (ELINK_SINGLE_MEDIA_DIRECT(params) &&
5534                     (params->feature_config_flags &
5535                      ELINK_FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED))
5536                         elink_set_preemphasis(phy, params);
5537
5538                 /* Forced speed requested? */
5539                 if (vars->line_speed != ELINK_SPEED_AUTO_NEG ||
5540                     (ELINK_SINGLE_MEDIA_DIRECT(params) &&
5541                      params->loopback_mode == ELINK_LOOPBACK_EXT)) {
5542                         PMD_DRV_LOG(DEBUG, "not SGMII, no AN");
5543
5544                         /* Disable autoneg */
5545                         elink_set_autoneg(phy, params, vars, 0);
5546
5547                         /* Program speed and duplex */
5548                         elink_program_serdes(phy, params, vars);
5549
5550                 } else {        /* AN_mode */
5551                         PMD_DRV_LOG(DEBUG, "not SGMII, AN");
5552
5553                         /* AN enabled */
5554                         elink_set_brcm_cl37_advertisement(phy, params);
5555
5556                         /* Program duplex & pause advertisement (for aneg) */
5557                         elink_set_ieee_aneg_advertisement(phy, params,
5558                                                           vars->ieee_fc);
5559
5560                         /* Enable autoneg */
5561                         elink_set_autoneg(phy, params, vars, enable_cl73);
5562
5563                         /* Enable and restart AN */
5564                         elink_restart_autoneg(phy, params, enable_cl73);
5565                 }
5566
5567         } else {                /* SGMII mode */
5568                 PMD_DRV_LOG(DEBUG, "SGMII");
5569
5570                 elink_initialize_sgmii_process(phy, params, vars);
5571         }
5572
5573         return 0;
5574 }
5575
5576 static elink_status_t elink_prepare_xgxs(struct elink_phy *phy,
5577                                          struct elink_params *params,
5578                                          struct elink_vars *vars)
5579 {
5580         elink_status_t rc;
5581         vars->phy_flags |= PHY_XGXS_FLAG;
5582         if ((phy->req_line_speed &&
5583              ((phy->req_line_speed == ELINK_SPEED_100) ||
5584               (phy->req_line_speed == ELINK_SPEED_10))) ||
5585             (!phy->req_line_speed &&
5586              (phy->speed_cap_mask >=
5587               PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL) &&
5588              (phy->speed_cap_mask <
5589               PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)) ||
5590             (phy->type == PORT_HW_CFG_SERDES_EXT_PHY_TYPE_DIRECT_SD))
5591                 vars->phy_flags |= PHY_SGMII_FLAG;
5592         else
5593                 vars->phy_flags &= ~PHY_SGMII_FLAG;
5594
5595         elink_calc_ieee_aneg_adv(phy, params, &vars->ieee_fc);
5596         elink_set_aer_mmd(params, phy);
5597         if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT)
5598                 elink_set_master_ln(params, phy);
5599
5600         rc = elink_reset_unicore(params, phy, 0);
5601         /* Reset the SerDes and wait for reset bit return low */
5602         if (rc != ELINK_STATUS_OK)
5603                 return rc;
5604
5605         elink_set_aer_mmd(params, phy);
5606         /* Setting the masterLn_def again after the reset */
5607         if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT) {
5608                 elink_set_master_ln(params, phy);
5609                 elink_set_swap_lanes(params, phy);
5610         }
5611
5612         return rc;
5613 }
5614
5615 static uint16_t elink_wait_reset_complete(struct bnx2x_softc *sc,
5616                                           struct elink_phy *phy,
5617                                           struct elink_params *params)
5618 {
5619         uint16_t cnt, ctrl;
5620         /* Wait for soft reset to get cleared up to 1 sec */
5621         for (cnt = 0; cnt < 1000; cnt++) {
5622                 if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X54618SE)
5623                         elink_cl22_read(sc, phy, MDIO_PMA_REG_CTRL, &ctrl);
5624                 else
5625                         elink_cl45_read(sc, phy,
5626                                         MDIO_PMA_DEVAD,
5627                                         MDIO_PMA_REG_CTRL, &ctrl);
5628                 if (!(ctrl & (1 << 15)))
5629                         break;
5630                 DELAY(1000 * 1);
5631         }
5632
5633         if (cnt == 1000)
5634                 elink_cb_event_log(sc, ELINK_LOG_ID_PHY_UNINITIALIZED, params->port);   // "Warning: PHY was not initialized,"
5635         // " Port %d",
5636
5637         PMD_DRV_LOG(DEBUG, "control reg 0x%x (after %d ms)", ctrl, cnt);
5638         return cnt;
5639 }
5640
5641 static void elink_link_int_enable(struct elink_params *params)
5642 {
5643         uint8_t port = params->port;
5644         uint32_t mask;
5645         struct bnx2x_softc *sc = params->sc;
5646
5647         /* Setting the status to report on link up for either XGXS or SerDes */
5648         if (CHIP_IS_E3(sc)) {
5649                 mask = ELINK_NIG_MASK_XGXS0_LINK_STATUS;
5650                 if (!(ELINK_SINGLE_MEDIA_DIRECT(params)))
5651                         mask |= ELINK_NIG_MASK_MI_INT;
5652         } else if (params->switch_cfg == ELINK_SWITCH_CFG_10G) {
5653                 mask = (ELINK_NIG_MASK_XGXS0_LINK10G |
5654                         ELINK_NIG_MASK_XGXS0_LINK_STATUS);
5655                 PMD_DRV_LOG(DEBUG, "enabled XGXS interrupt");
5656                 if (!(ELINK_SINGLE_MEDIA_DIRECT(params)) &&
5657                     params->phy[ELINK_INT_PHY].type !=
5658                     PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE) {
5659                         mask |= ELINK_NIG_MASK_MI_INT;
5660                         PMD_DRV_LOG(DEBUG, "enabled external phy int");
5661                 }
5662
5663         } else {                /* SerDes */
5664                 mask = ELINK_NIG_MASK_SERDES0_LINK_STATUS;
5665                 PMD_DRV_LOG(DEBUG, "enabled SerDes interrupt");
5666                 if (!(ELINK_SINGLE_MEDIA_DIRECT(params)) &&
5667                     params->phy[ELINK_INT_PHY].type !=
5668                     PORT_HW_CFG_SERDES_EXT_PHY_TYPE_NOT_CONN) {
5669                         mask |= ELINK_NIG_MASK_MI_INT;
5670                         PMD_DRV_LOG(DEBUG, "enabled external phy int");
5671                 }
5672         }
5673         elink_bits_en(sc, NIG_REG_MASK_INTERRUPT_PORT0 + port * 4, mask);
5674
5675         PMD_DRV_LOG(DEBUG, "port %x, is_xgxs %x, int_status 0x%x", port,
5676                     (params->switch_cfg == ELINK_SWITCH_CFG_10G),
5677                     REG_RD(sc, NIG_REG_STATUS_INTERRUPT_PORT0 + port * 4));
5678         PMD_DRV_LOG(DEBUG, " int_mask 0x%x, MI_INT %x, SERDES_LINK %x",
5679                     REG_RD(sc, NIG_REG_MASK_INTERRUPT_PORT0 + port * 4),
5680                     REG_RD(sc, NIG_REG_EMAC0_STATUS_MISC_MI_INT + port * 0x18),
5681                     REG_RD(sc,
5682                            NIG_REG_SERDES0_STATUS_LINK_STATUS + port * 0x3c));
5683         PMD_DRV_LOG(DEBUG, " 10G %x, XGXS_LINK %x",
5684                     REG_RD(sc, NIG_REG_XGXS0_STATUS_LINK10G + port * 0x68),
5685                     REG_RD(sc, NIG_REG_XGXS0_STATUS_LINK_STATUS + port * 0x68));
5686 }
5687
5688 static void elink_rearm_latch_signal(struct bnx2x_softc *sc, uint8_t port,
5689                                      uint8_t exp_mi_int)
5690 {
5691         uint32_t latch_status = 0;
5692
5693         /* Disable the MI INT ( external phy int ) by writing 1 to the
5694          * status register. Link down indication is high-active-signal,
5695          * so in this case we need to write the status to clear the XOR
5696          */
5697         /* Read Latched signals */
5698         latch_status = REG_RD(sc, NIG_REG_LATCH_STATUS_0 + port * 8);
5699         PMD_DRV_LOG(DEBUG, "latch_status = 0x%x", latch_status);
5700         /* Handle only those with latched-signal=up. */
5701         if (exp_mi_int)
5702                 elink_bits_en(sc,
5703                               NIG_REG_STATUS_INTERRUPT_PORT0
5704                               + port * 4, ELINK_NIG_STATUS_EMAC0_MI_INT);
5705         else
5706                 elink_bits_dis(sc,
5707                                NIG_REG_STATUS_INTERRUPT_PORT0
5708                                + port * 4, ELINK_NIG_STATUS_EMAC0_MI_INT);
5709
5710         if (latch_status & 1) {
5711
5712                 /* For all latched-signal=up : Re-Arm Latch signals */
5713                 REG_WR(sc, NIG_REG_LATCH_STATUS_0 + port * 8,
5714                        (latch_status & 0xfffe) | (latch_status & 1));
5715         }
5716         /* For all latched-signal=up,Write original_signal to status */
5717 }
5718
5719 static void elink_link_int_ack(struct elink_params *params,
5720                                struct elink_vars *vars, uint8_t is_10g_plus)
5721 {
5722         struct bnx2x_softc *sc = params->sc;
5723         uint8_t port = params->port;
5724         uint32_t mask;
5725         /* First reset all status we assume only one line will be
5726          * change at a time
5727          */
5728         elink_bits_dis(sc, NIG_REG_STATUS_INTERRUPT_PORT0 + port * 4,
5729                        (ELINK_NIG_STATUS_XGXS0_LINK10G |
5730                         ELINK_NIG_STATUS_XGXS0_LINK_STATUS |
5731                         ELINK_NIG_STATUS_SERDES0_LINK_STATUS));
5732         if (vars->phy_link_up) {
5733                 if (USES_WARPCORE(sc))
5734                         mask = ELINK_NIG_STATUS_XGXS0_LINK_STATUS;
5735                 else {
5736                         if (is_10g_plus)
5737                                 mask = ELINK_NIG_STATUS_XGXS0_LINK10G;
5738                         else if (params->switch_cfg == ELINK_SWITCH_CFG_10G) {
5739                                 /* Disable the link interrupt by writing 1 to
5740                                  * the relevant lane in the status register
5741                                  */
5742                                 uint32_t ser_lane =
5743                                     ((params->lane_config &
5744                                       PORT_HW_CFG_LANE_SWAP_CFG_MASTER_MASK) >>
5745                                      PORT_HW_CFG_LANE_SWAP_CFG_MASTER_SHIFT);
5746                                 mask = ((1 << ser_lane) <<
5747                                         ELINK_NIG_STATUS_XGXS0_LINK_STATUS_SIZE);
5748                         } else
5749                                 mask = ELINK_NIG_STATUS_SERDES0_LINK_STATUS;
5750                 }
5751                 PMD_DRV_LOG(DEBUG, "Ack link up interrupt with mask 0x%x",
5752                             mask);
5753                 elink_bits_en(sc,
5754                               NIG_REG_STATUS_INTERRUPT_PORT0 + port * 4, mask);
5755         }
5756 }
5757
5758 static uint8_t elink_format_ver(uint32_t num, uint8_t * str,
5759                                 uint16_t * len)
5760 {
5761         uint8_t *str_ptr = str;
5762         uint32_t mask = 0xf0000000;
5763         uint8_t shift = 8 * 4;
5764         uint8_t digit;
5765         uint8_t remove_leading_zeros = 1;
5766         if (*len < 10) {
5767                 /* Need more than 10chars for this format */
5768                 *str_ptr = '\0';
5769                 (*len)--;
5770                 return ELINK_STATUS_ERROR;
5771         }
5772         while (shift > 0) {
5773
5774                 shift -= 4;
5775                 digit = ((num & mask) >> shift);
5776                 if (digit == 0 && remove_leading_zeros) {
5777                         mask = mask >> 4;
5778                         continue;
5779                 } else if (digit < 0xa)
5780                         *str_ptr = digit + '0';
5781                 else
5782                         *str_ptr = digit - 0xa + 'a';
5783                 remove_leading_zeros = 0;
5784                 str_ptr++;
5785                 (*len)--;
5786                 mask = mask >> 4;
5787                 if (shift == 4 * 4) {
5788                         *str_ptr = '.';
5789                         str_ptr++;
5790                         (*len)--;
5791                         remove_leading_zeros = 1;
5792                 }
5793         }
5794         return ELINK_STATUS_OK;
5795 }
5796
5797 static uint8_t elink_null_format_ver(__rte_unused uint32_t spirom_ver,
5798                                      uint8_t * str, uint16_t * len)
5799 {
5800         str[0] = '\0';
5801         (*len)--;
5802         return ELINK_STATUS_OK;
5803 }
5804
5805 static void elink_set_xgxs_loopback(struct elink_phy *phy,
5806                                     struct elink_params *params)
5807 {
5808         uint8_t port = params->port;
5809         struct bnx2x_softc *sc = params->sc;
5810
5811         if (phy->req_line_speed != ELINK_SPEED_1000) {
5812                 uint32_t md_devad = 0;
5813
5814                 PMD_DRV_LOG(DEBUG, "XGXS 10G loopback enable");
5815
5816                 if (!CHIP_IS_E3(sc)) {
5817                         /* Change the uni_phy_addr in the nig */
5818                         md_devad = REG_RD(sc, (NIG_REG_XGXS0_CTRL_MD_DEVAD +
5819                                                port * 0x18));
5820
5821                         REG_WR(sc, NIG_REG_XGXS0_CTRL_MD_DEVAD + port * 0x18,
5822                                0x5);
5823                 }
5824
5825                 elink_cl45_write(sc, phy,
5826                                  5,
5827                                  (MDIO_REG_BANK_AER_BLOCK +
5828                                   (MDIO_AER_BLOCK_AER_REG & 0xf)), 0x2800);
5829
5830                 elink_cl45_write(sc, phy,
5831                                  5,
5832                                  (MDIO_REG_BANK_CL73_IEEEB0 +
5833                                   (MDIO_CL73_IEEEB0_CL73_AN_CONTROL & 0xf)),
5834                                  0x6041);
5835                 DELAY(1000 * 200);
5836                 /* Set aer mmd back */
5837                 elink_set_aer_mmd(params, phy);
5838
5839                 if (!CHIP_IS_E3(sc)) {
5840                         /* And md_devad */
5841                         REG_WR(sc, NIG_REG_XGXS0_CTRL_MD_DEVAD + port * 0x18,
5842                                md_devad);
5843                 }
5844         } else {
5845                 uint16_t mii_ctrl;
5846                 PMD_DRV_LOG(DEBUG, "XGXS 1G loopback enable");
5847                 elink_cl45_read(sc, phy, 5,
5848                                 (MDIO_REG_BANK_COMBO_IEEE0 +
5849                                  (MDIO_COMBO_IEEE0_MII_CONTROL & 0xf)),
5850                                 &mii_ctrl);
5851                 elink_cl45_write(sc, phy, 5,
5852                                  (MDIO_REG_BANK_COMBO_IEEE0 +
5853                                   (MDIO_COMBO_IEEE0_MII_CONTROL & 0xf)),
5854                                  mii_ctrl |
5855                                  MDIO_COMBO_IEEO_MII_CONTROL_LOOPBACK);
5856         }
5857 }
5858
5859 elink_status_t elink_set_led(struct elink_params *params,
5860                              struct elink_vars *vars, uint8_t mode,
5861                              uint32_t speed)
5862 {
5863         uint8_t port = params->port;
5864         uint16_t hw_led_mode = params->hw_led_mode;
5865         elink_status_t rc = ELINK_STATUS_OK;
5866         uint8_t phy_idx;
5867         uint32_t tmp;
5868         uint32_t emac_base = port ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
5869         struct bnx2x_softc *sc = params->sc;
5870         PMD_DRV_LOG(DEBUG, "elink_set_led: port %x, mode %d", port, mode);
5871         PMD_DRV_LOG(DEBUG, "speed 0x%x, hw_led_mode 0x%x", speed, hw_led_mode);
5872         /* In case */
5873         for (phy_idx = ELINK_EXT_PHY1; phy_idx < ELINK_MAX_PHYS; phy_idx++) {
5874                 if (params->phy[phy_idx].set_link_led) {
5875                         params->phy[phy_idx].set_link_led(&params->phy[phy_idx],
5876                                                           params, mode);
5877                 }
5878         }
5879
5880         switch (mode) {
5881         case ELINK_LED_MODE_FRONT_PANEL_OFF:
5882         case ELINK_LED_MODE_OFF:
5883                 REG_WR(sc, NIG_REG_LED_10G_P0 + port * 4, 0);
5884                 REG_WR(sc, NIG_REG_LED_MODE_P0 + port * 4,
5885                        SHARED_HW_CFG_LED_MAC1);
5886
5887                 tmp = elink_cb_reg_read(sc, emac_base + EMAC_REG_EMAC_LED);
5888                 if (params->phy[ELINK_EXT_PHY1].type ==
5889                     PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X54618SE)
5890                         tmp &= ~(EMAC_LED_1000MB_OVERRIDE |
5891                                  EMAC_LED_100MB_OVERRIDE |
5892                                  EMAC_LED_10MB_OVERRIDE);
5893                 else
5894                         tmp |= EMAC_LED_OVERRIDE;
5895
5896                 elink_cb_reg_write(sc, emac_base + EMAC_REG_EMAC_LED, tmp);
5897                 break;
5898
5899         case ELINK_LED_MODE_OPER:
5900                 /* For all other phys, OPER mode is same as ON, so in case
5901                  * link is down, do nothing
5902                  */
5903                 if (!vars->link_up)
5904                         break;
5905                 /* fall-through */
5906         case ELINK_LED_MODE_ON:
5907                 if (((params->phy[ELINK_EXT_PHY1].type ==
5908                       PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X8727) ||
5909                      (params->phy[ELINK_EXT_PHY1].type ==
5910                       PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X8722)) &&
5911                     CHIP_IS_E2(sc) && params->num_phys == 2) {
5912                         /* This is a work-around for E2+8727 Configurations */
5913                         if (mode == ELINK_LED_MODE_ON ||
5914                             speed == ELINK_SPEED_10000) {
5915                                 REG_WR(sc, NIG_REG_LED_MODE_P0 + port * 4, 0);
5916                                 REG_WR(sc, NIG_REG_LED_10G_P0 + port * 4, 1);
5917
5918                                 tmp =
5919                                     elink_cb_reg_read(sc,
5920                                                       emac_base +
5921                                                       EMAC_REG_EMAC_LED);
5922                                 elink_cb_reg_write(sc,
5923                                                    emac_base +
5924                                                    EMAC_REG_EMAC_LED,
5925                                                    (tmp | EMAC_LED_OVERRIDE));
5926                                 /* Return here without enabling traffic
5927                                  * LED blink and setting rate in ON mode.
5928                                  * In oper mode, enabling LED blink
5929                                  * and setting rate is needed.
5930                                  */
5931                                 if (mode == ELINK_LED_MODE_ON)
5932                                         return rc;
5933                         }
5934                 } else if (ELINK_SINGLE_MEDIA_DIRECT(params)) {
5935                         /* This is a work-around for HW issue found when link
5936                          * is up in CL73
5937                          */
5938                         if ((!CHIP_IS_E3(sc)) ||
5939                             (CHIP_IS_E3(sc) && mode == ELINK_LED_MODE_ON))
5940                                 REG_WR(sc, NIG_REG_LED_10G_P0 + port * 4, 1);
5941
5942                         if (CHIP_IS_E1x(sc) ||
5943                             CHIP_IS_E2(sc) || (mode == ELINK_LED_MODE_ON))
5944                                 REG_WR(sc, NIG_REG_LED_MODE_P0 + port * 4, 0);
5945                         else
5946                                 REG_WR(sc, NIG_REG_LED_MODE_P0 + port * 4,
5947                                        hw_led_mode);
5948                 } else if ((params->phy[ELINK_EXT_PHY1].type ==
5949                             PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X54618SE) &&
5950                            (mode == ELINK_LED_MODE_ON)) {
5951                         REG_WR(sc, NIG_REG_LED_MODE_P0 + port * 4, 0);
5952                         tmp =
5953                             elink_cb_reg_read(sc,
5954                                               emac_base + EMAC_REG_EMAC_LED);
5955                         elink_cb_reg_write(sc, emac_base + EMAC_REG_EMAC_LED,
5956                                            tmp | EMAC_LED_OVERRIDE |
5957                                            EMAC_LED_1000MB_OVERRIDE);
5958                         /* Break here; otherwise, it'll disable the
5959                          * intended override.
5960                          */
5961                         break;
5962                 } else {
5963                         uint32_t nig_led_mode = ((params->hw_led_mode <<
5964                                                   SHARED_HW_CFG_LED_MODE_SHIFT)
5965                                                  ==
5966                                                  SHARED_HW_CFG_LED_EXTPHY2)
5967                             ? (SHARED_HW_CFG_LED_PHY1 >>
5968                                SHARED_HW_CFG_LED_MODE_SHIFT) : hw_led_mode;
5969                         REG_WR(sc, NIG_REG_LED_MODE_P0 + port * 4,
5970                                nig_led_mode);
5971                 }
5972
5973                 REG_WR(sc, NIG_REG_LED_CONTROL_OVERRIDE_TRAFFIC_P0 + port * 4,
5974                        0);
5975                 /* Set blinking rate to ~15.9Hz */
5976                 if (CHIP_IS_E3(sc))
5977                         REG_WR(sc, NIG_REG_LED_CONTROL_BLINK_RATE_P0 + port * 4,
5978                                LED_BLINK_RATE_VAL_E3);
5979                 else
5980                         REG_WR(sc, NIG_REG_LED_CONTROL_BLINK_RATE_P0 + port * 4,
5981                                LED_BLINK_RATE_VAL_E1X_E2);
5982                 REG_WR(sc, NIG_REG_LED_CONTROL_BLINK_RATE_ENA_P0 + port * 4, 1);
5983                 tmp = elink_cb_reg_read(sc, emac_base + EMAC_REG_EMAC_LED);
5984                 elink_cb_reg_write(sc, emac_base + EMAC_REG_EMAC_LED,
5985                                    (tmp & (~EMAC_LED_OVERRIDE)));
5986
5987                 break;
5988
5989         default:
5990                 rc = ELINK_STATUS_ERROR;
5991                 PMD_DRV_LOG(DEBUG, "elink_set_led: Invalid led mode %d", mode);
5992                 break;
5993         }
5994         return rc;
5995
5996 }
5997
5998 static elink_status_t elink_link_initialize(struct elink_params *params,
5999                                             struct elink_vars *vars)
6000 {
6001         elink_status_t rc = ELINK_STATUS_OK;
6002         uint8_t phy_index, non_ext_phy;
6003         struct bnx2x_softc *sc = params->sc;
6004         /* In case of external phy existence, the line speed would be the
6005          * line speed linked up by the external phy. In case it is direct
6006          * only, then the line_speed during initialization will be
6007          * equal to the req_line_speed
6008          */
6009         vars->line_speed = params->phy[ELINK_INT_PHY].req_line_speed;
6010
6011         /* Initialize the internal phy in case this is a direct board
6012          * (no external phys), or this board has external phy which requires
6013          * to first.
6014          */
6015         if (!USES_WARPCORE(sc))
6016                 elink_prepare_xgxs(&params->phy[ELINK_INT_PHY], params, vars);
6017         /* init ext phy and enable link state int */
6018         non_ext_phy = (ELINK_SINGLE_MEDIA_DIRECT(params) ||
6019                        (params->loopback_mode == ELINK_LOOPBACK_XGXS));
6020
6021         if (non_ext_phy ||
6022             (params->phy[ELINK_EXT_PHY1].flags & ELINK_FLAGS_INIT_XGXS_FIRST) ||
6023             (params->loopback_mode == ELINK_LOOPBACK_EXT_PHY)) {
6024                 struct elink_phy *phy = &params->phy[ELINK_INT_PHY];
6025                 if (vars->line_speed == ELINK_SPEED_AUTO_NEG &&
6026                     (CHIP_IS_E1x(sc) || CHIP_IS_E2(sc)))
6027                         elink_set_parallel_detection(phy, params);
6028                 if (params->phy[ELINK_INT_PHY].config_init)
6029                         params->phy[ELINK_INT_PHY].config_init(phy,
6030                                                                params, vars);
6031         }
6032
6033         /* Re-read this value in case it was changed inside config_init due to
6034          * limitations of optic module
6035          */
6036         vars->line_speed = params->phy[ELINK_INT_PHY].req_line_speed;
6037
6038         /* Init external phy */
6039         if (non_ext_phy) {
6040                 if (params->phy[ELINK_INT_PHY].supported &
6041                     ELINK_SUPPORTED_FIBRE)
6042                         vars->link_status |= LINK_STATUS_SERDES_LINK;
6043         } else {
6044                 for (phy_index = ELINK_EXT_PHY1; phy_index < params->num_phys;
6045                      phy_index++) {
6046                         /* No need to initialize second phy in case of first
6047                          * phy only selection. In case of second phy, we do
6048                          * need to initialize the first phy, since they are
6049                          * connected.
6050                          */
6051                         if (params->phy[phy_index].supported &
6052                             ELINK_SUPPORTED_FIBRE)
6053                                 vars->link_status |= LINK_STATUS_SERDES_LINK;
6054
6055                         if (phy_index == ELINK_EXT_PHY2 &&
6056                             (elink_phy_selection(params) ==
6057                              PORT_HW_CFG_PHY_SELECTION_FIRST_PHY)) {
6058                                 PMD_DRV_LOG(DEBUG,
6059                                             "Not initializing second phy");
6060                                 continue;
6061                         }
6062                         params->phy[phy_index].config_init(&params->
6063                                                            phy[phy_index],
6064                                                            params, vars);
6065                 }
6066         }
6067         /* Reset the interrupt indication after phy was initialized */
6068         elink_bits_dis(sc, NIG_REG_STATUS_INTERRUPT_PORT0 +
6069                        params->port * 4,
6070                        (ELINK_NIG_STATUS_XGXS0_LINK10G |
6071                         ELINK_NIG_STATUS_XGXS0_LINK_STATUS |
6072                         ELINK_NIG_STATUS_SERDES0_LINK_STATUS |
6073                         ELINK_NIG_MASK_MI_INT));
6074         return rc;
6075 }
6076
6077 static void elink_int_link_reset(__rte_unused struct elink_phy *phy,
6078                                  struct elink_params *params)
6079 {
6080         /* Reset the SerDes/XGXS */
6081         REG_WR(params->sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_3_CLEAR,
6082                (0x1ff << (params->port * 16)));
6083 }
6084
6085 static void elink_common_ext_link_reset(__rte_unused struct elink_phy *phy,
6086                                         struct elink_params *params)
6087 {
6088         struct bnx2x_softc *sc = params->sc;
6089         uint8_t gpio_port;
6090         /* HW reset */
6091         if (CHIP_IS_E2(sc))
6092                 gpio_port = SC_PATH(sc);
6093         else
6094                 gpio_port = params->port;
6095         elink_cb_gpio_write(sc, MISC_REGISTERS_GPIO_1,
6096                             MISC_REGISTERS_GPIO_OUTPUT_LOW, gpio_port);
6097         elink_cb_gpio_write(sc, MISC_REGISTERS_GPIO_2,
6098                             MISC_REGISTERS_GPIO_OUTPUT_LOW, gpio_port);
6099         PMD_DRV_LOG(DEBUG, "reset external PHY");
6100 }
6101
6102 static elink_status_t elink_update_link_down(struct elink_params *params,
6103                                              struct elink_vars *vars)
6104 {
6105         struct bnx2x_softc *sc = params->sc;
6106         uint8_t port = params->port;
6107
6108         PMD_DRV_LOG(DEBUG, "Port %x: Link is down", port);
6109         elink_set_led(params, vars, ELINK_LED_MODE_OFF, 0);
6110         vars->phy_flags &= ~PHY_PHYSICAL_LINK_FLAG;
6111         /* Indicate no mac active */
6112         vars->mac_type = ELINK_MAC_TYPE_NONE;
6113
6114         /* Update shared memory */
6115         vars->link_status &= ~ELINK_LINK_UPDATE_MASK;
6116         vars->line_speed = 0;
6117         elink_update_mng(params, vars->link_status);
6118
6119         /* Activate nig drain */
6120         REG_WR(sc, NIG_REG_EGRESS_DRAIN0_MODE + port * 4, 1);
6121
6122         /* Disable emac */
6123         if (!CHIP_IS_E3(sc))
6124                 REG_WR(sc, NIG_REG_NIG_EMAC0_EN + port * 4, 0);
6125
6126         DELAY(1000 * 10);
6127         /* Reset BigMac/Xmac */
6128         if (CHIP_IS_E1x(sc) || CHIP_IS_E2(sc))
6129                 elink_set_bmac_rx(sc, params->port, 0);
6130
6131         if (CHIP_IS_E3(sc)) {
6132                 /* Prevent LPI Generation by chip */
6133                 REG_WR(sc, MISC_REG_CPMU_LP_FW_ENABLE_P0 + (params->port << 2),
6134                        0);
6135                 REG_WR(sc, MISC_REG_CPMU_LP_MASK_ENT_P0 + (params->port << 2),
6136                        0);
6137                 vars->eee_status &= ~(SHMEM_EEE_LP_ADV_STATUS_MASK |
6138                                       SHMEM_EEE_ACTIVE_BIT);
6139
6140                 elink_update_mng_eee(params, vars->eee_status);
6141                 elink_set_xmac_rxtx(params, 0);
6142                 elink_set_umac_rxtx(params, 0);
6143         }
6144
6145         return ELINK_STATUS_OK;
6146 }
6147
6148 static elink_status_t elink_update_link_up(struct elink_params *params,
6149                                            struct elink_vars *vars,
6150                                            uint8_t link_10g)
6151 {
6152         struct bnx2x_softc *sc = params->sc;
6153         uint8_t phy_idx, port = params->port;
6154         elink_status_t rc = ELINK_STATUS_OK;
6155
6156         vars->link_status |= (LINK_STATUS_LINK_UP |
6157                               LINK_STATUS_PHYSICAL_LINK_FLAG);
6158         vars->phy_flags |= PHY_PHYSICAL_LINK_FLAG;
6159
6160         if (vars->flow_ctrl & ELINK_FLOW_CTRL_TX)
6161                 vars->link_status |= LINK_STATUS_TX_FLOW_CONTROL_ENABLED;
6162
6163         if (vars->flow_ctrl & ELINK_FLOW_CTRL_RX)
6164                 vars->link_status |= LINK_STATUS_RX_FLOW_CONTROL_ENABLED;
6165         if (USES_WARPCORE(sc)) {
6166                 if (link_10g) {
6167                         if (elink_xmac_enable(params, vars, 0) ==
6168                             ELINK_STATUS_NO_LINK) {
6169                                 PMD_DRV_LOG(DEBUG, "Found errors on XMAC");
6170                                 vars->link_up = 0;
6171                                 vars->phy_flags |= PHY_HALF_OPEN_CONN_FLAG;
6172                                 vars->link_status &= ~LINK_STATUS_LINK_UP;
6173                         }
6174                 } else
6175                         elink_umac_enable(params, vars, 0);
6176                 elink_set_led(params, vars,
6177                               ELINK_LED_MODE_OPER, vars->line_speed);
6178
6179                 if ((vars->eee_status & SHMEM_EEE_ACTIVE_BIT) &&
6180                     (vars->eee_status & SHMEM_EEE_LPI_REQUESTED_BIT)) {
6181                         PMD_DRV_LOG(DEBUG, "Enabling LPI assertion");
6182                         REG_WR(sc, MISC_REG_CPMU_LP_FW_ENABLE_P0 +
6183                                (params->port << 2), 1);
6184                         REG_WR(sc, MISC_REG_CPMU_LP_DR_ENABLE, 1);
6185                         REG_WR(sc, MISC_REG_CPMU_LP_MASK_ENT_P0 +
6186                                (params->port << 2), 0xfc20);
6187                 }
6188         }
6189         if ((CHIP_IS_E1x(sc) || CHIP_IS_E2(sc))) {
6190                 if (link_10g) {
6191                         if (elink_bmac_enable(params, vars, 0, 1) ==
6192                             ELINK_STATUS_NO_LINK) {
6193                                 PMD_DRV_LOG(DEBUG, "Found errors on BMAC");
6194                                 vars->link_up = 0;
6195                                 vars->phy_flags |= PHY_HALF_OPEN_CONN_FLAG;
6196                                 vars->link_status &= ~LINK_STATUS_LINK_UP;
6197                         }
6198
6199                         elink_set_led(params, vars,
6200                                       ELINK_LED_MODE_OPER, ELINK_SPEED_10000);
6201                 } else {
6202                         rc = elink_emac_program(params, vars);
6203                         elink_emac_enable(params, vars, 0);
6204
6205                         /* AN complete? */
6206                         if ((vars->link_status &
6207                              LINK_STATUS_AUTO_NEGOTIATE_COMPLETE)
6208                             && (!(vars->phy_flags & PHY_SGMII_FLAG)) &&
6209                             ELINK_SINGLE_MEDIA_DIRECT(params))
6210                                 elink_set_gmii_tx_driver(params);
6211                 }
6212         }
6213
6214         /* PBF - link up */
6215         if (CHIP_IS_E1x(sc))
6216                 rc |= elink_pbf_update(params, vars->flow_ctrl,
6217                                        vars->line_speed);
6218
6219         /* Disable drain */
6220         REG_WR(sc, NIG_REG_EGRESS_DRAIN0_MODE + port * 4, 0);
6221
6222         /* Update shared memory */
6223         elink_update_mng(params, vars->link_status);
6224         elink_update_mng_eee(params, vars->eee_status);
6225         /* Check remote fault */
6226         for (phy_idx = ELINK_INT_PHY; phy_idx < ELINK_MAX_PHYS; phy_idx++) {
6227                 if (params->phy[phy_idx].flags & ELINK_FLAGS_TX_ERROR_CHECK) {
6228                         elink_check_half_open_conn(params, vars, 0);
6229                         break;
6230                 }
6231         }
6232         DELAY(1000 * 20);
6233         return rc;
6234 }
6235
6236 /* The elink_link_update function should be called upon link
6237  * interrupt.
6238  * Link is considered up as follows:
6239  * - DIRECT_SINGLE_MEDIA - Only XGXS link (internal link) needs
6240  *   to be up
6241  * - SINGLE_MEDIA - The link between the 577xx and the external
6242  *   phy (XGXS) need to up as well as the external link of the
6243  *   phy (PHY_EXT1)
6244  * - DUAL_MEDIA - The link between the 577xx and the first
6245  *   external phy needs to be up, and at least one of the 2
6246  *   external phy link must be up.
6247  */
6248 elink_status_t elink_link_update(struct elink_params * params,
6249                                  struct elink_vars * vars)
6250 {
6251         struct bnx2x_softc *sc = params->sc;
6252         struct elink_vars phy_vars[ELINK_MAX_PHYS];
6253         uint8_t port = params->port;
6254         uint8_t link_10g_plus, phy_index;
6255         uint8_t ext_phy_link_up = 0, cur_link_up;
6256         elink_status_t rc = ELINK_STATUS_OK;
6257         __rte_unused uint8_t is_mi_int = 0;
6258         uint16_t ext_phy_line_speed = 0, prev_line_speed = vars->line_speed;
6259         uint8_t active_external_phy = ELINK_INT_PHY;
6260         vars->phy_flags &= ~PHY_HALF_OPEN_CONN_FLAG;
6261         vars->link_status &= ~ELINK_LINK_UPDATE_MASK;
6262         for (phy_index = ELINK_INT_PHY; phy_index < params->num_phys;
6263              phy_index++) {
6264                 phy_vars[phy_index].flow_ctrl = 0;
6265                 phy_vars[phy_index].link_status = ETH_LINK_DOWN;
6266                 phy_vars[phy_index].line_speed = 0;
6267                 phy_vars[phy_index].duplex = DUPLEX_FULL;
6268                 phy_vars[phy_index].phy_link_up = 0;
6269                 phy_vars[phy_index].link_up = 0;
6270                 phy_vars[phy_index].fault_detected = 0;
6271                 /* different consideration, since vars holds inner state */
6272                 phy_vars[phy_index].eee_status = vars->eee_status;
6273         }
6274
6275         if (USES_WARPCORE(sc))
6276                 elink_set_aer_mmd(params, &params->phy[ELINK_INT_PHY]);
6277
6278         PMD_DRV_LOG(DEBUG, "port %x, XGXS?%x, int_status 0x%x",
6279                     port, (vars->phy_flags & PHY_XGXS_FLAG),
6280                     REG_RD(sc, NIG_REG_STATUS_INTERRUPT_PORT0 + port * 4));
6281
6282         is_mi_int = (uint8_t) (REG_RD(sc, NIG_REG_EMAC0_STATUS_MISC_MI_INT +
6283                                       port * 0x18) > 0);
6284         PMD_DRV_LOG(DEBUG, "int_mask 0x%x MI_INT %x, SERDES_LINK %x",
6285                     REG_RD(sc, NIG_REG_MASK_INTERRUPT_PORT0 + port * 4),
6286                     is_mi_int,
6287                     REG_RD(sc,
6288                            NIG_REG_SERDES0_STATUS_LINK_STATUS + port * 0x3c));
6289
6290         PMD_DRV_LOG(DEBUG, " 10G %x, XGXS_LINK %x",
6291                     REG_RD(sc, NIG_REG_XGXS0_STATUS_LINK10G + port * 0x68),
6292                     REG_RD(sc, NIG_REG_XGXS0_STATUS_LINK_STATUS + port * 0x68));
6293
6294         /* Disable emac */
6295         if (!CHIP_IS_E3(sc))
6296                 REG_WR(sc, NIG_REG_NIG_EMAC0_EN + port * 4, 0);
6297
6298         /* Step 1:
6299          * Check external link change only for external phys, and apply
6300          * priority selection between them in case the link on both phys
6301          * is up. Note that instead of the common vars, a temporary
6302          * vars argument is used since each phy may have different link/
6303          * speed/duplex result
6304          */
6305         for (phy_index = ELINK_EXT_PHY1; phy_index < params->num_phys;
6306              phy_index++) {
6307                 struct elink_phy *phy = &params->phy[phy_index];
6308                 if (!phy->read_status)
6309                         continue;
6310                 /* Read link status and params of this ext phy */
6311                 cur_link_up = phy->read_status(phy, params,
6312                                                &phy_vars[phy_index]);
6313                 if (cur_link_up) {
6314                         PMD_DRV_LOG(DEBUG, "phy in index %d link is up",
6315                                     phy_index);
6316                 } else {
6317                         PMD_DRV_LOG(DEBUG, "phy in index %d link is down",
6318                                     phy_index);
6319                         continue;
6320                 }
6321
6322                 if (!ext_phy_link_up) {
6323                         ext_phy_link_up = 1;
6324                         active_external_phy = phy_index;
6325                 } else {
6326                         switch (elink_phy_selection(params)) {
6327                         case PORT_HW_CFG_PHY_SELECTION_HARDWARE_DEFAULT:
6328                         case PORT_HW_CFG_PHY_SELECTION_FIRST_PHY_PRIORITY:
6329                                 /* In this option, the first PHY makes sure to pass the
6330                                  * traffic through itself only.
6331                                  * Its not clear how to reset the link on the second phy
6332                                  */
6333                                 active_external_phy = ELINK_EXT_PHY1;
6334                                 break;
6335                         case PORT_HW_CFG_PHY_SELECTION_SECOND_PHY_PRIORITY:
6336                                 /* In this option, the first PHY makes sure to pass the
6337                                  * traffic through the second PHY.
6338                                  */
6339                                 active_external_phy = ELINK_EXT_PHY2;
6340                                 break;
6341                         default:
6342                                 /* Link indication on both PHYs with the following cases
6343                                  * is invalid:
6344                                  * - FIRST_PHY means that second phy wasn't initialized,
6345                                  * hence its link is expected to be down
6346                                  * - SECOND_PHY means that first phy should not be able
6347                                  * to link up by itself (using configuration)
6348                                  * - DEFAULT should be overridden during initialization
6349                                  */
6350                                 PMD_DRV_LOG(DEBUG, "Invalid link indication"
6351                                             "mpc=0x%x. DISABLING LINK !!!",
6352                                             params->multi_phy_config);
6353                                 ext_phy_link_up = 0;
6354                                 break;
6355                         }
6356                 }
6357         }
6358         prev_line_speed = vars->line_speed;
6359         /* Step 2:
6360          * Read the status of the internal phy. In case of
6361          * DIRECT_SINGLE_MEDIA board, this link is the external link,
6362          * otherwise this is the link between the 577xx and the first
6363          * external phy
6364          */
6365         if (params->phy[ELINK_INT_PHY].read_status)
6366                 params->phy[ELINK_INT_PHY].read_status(&params->
6367                                                        phy[ELINK_INT_PHY],
6368                                                        params, vars);
6369         /* The INT_PHY flow control reside in the vars. This include the
6370          * case where the speed or flow control are not set to AUTO.
6371          * Otherwise, the active external phy flow control result is set
6372          * to the vars. The ext_phy_line_speed is needed to check if the
6373          * speed is different between the internal phy and external phy.
6374          * This case may be result of intermediate link speed change.
6375          */
6376         if (active_external_phy > ELINK_INT_PHY) {
6377                 vars->flow_ctrl = phy_vars[active_external_phy].flow_ctrl;
6378                 /* Link speed is taken from the XGXS. AN and FC result from
6379                  * the external phy.
6380                  */
6381                 vars->link_status |= phy_vars[active_external_phy].link_status;
6382
6383                 /* if active_external_phy is first PHY and link is up - disable
6384                  * disable TX on second external PHY
6385                  */
6386                 if (active_external_phy == ELINK_EXT_PHY1) {
6387                         if (params->phy[ELINK_EXT_PHY2].phy_specific_func) {
6388                                 PMD_DRV_LOG(DEBUG, "Disabling TX on EXT_PHY2");
6389                                 params->phy[ELINK_EXT_PHY2].
6390                                     phy_specific_func(&params->
6391                                                       phy[ELINK_EXT_PHY2],
6392                                                       params, ELINK_DISABLE_TX);
6393                         }
6394                 }
6395
6396                 ext_phy_line_speed = phy_vars[active_external_phy].line_speed;
6397                 vars->duplex = phy_vars[active_external_phy].duplex;
6398                 if (params->phy[active_external_phy].supported &
6399                     ELINK_SUPPORTED_FIBRE)
6400                         vars->link_status |= LINK_STATUS_SERDES_LINK;
6401                 else
6402                         vars->link_status &= ~LINK_STATUS_SERDES_LINK;
6403
6404                 vars->eee_status = phy_vars[active_external_phy].eee_status;
6405
6406                 PMD_DRV_LOG(DEBUG, "Active external phy selected: %x",
6407                             active_external_phy);
6408         }
6409
6410         for (phy_index = ELINK_EXT_PHY1; phy_index < params->num_phys;
6411              phy_index++) {
6412                 if (params->phy[phy_index].flags &
6413                     ELINK_FLAGS_REARM_LATCH_SIGNAL) {
6414                         elink_rearm_latch_signal(sc, port,
6415                                                  phy_index ==
6416                                                  active_external_phy);
6417                         break;
6418                 }
6419         }
6420         PMD_DRV_LOG(DEBUG, "vars->flow_ctrl = 0x%x, vars->link_status = 0x%x,"
6421                     " ext_phy_line_speed = %d", vars->flow_ctrl,
6422                     vars->link_status, ext_phy_line_speed);
6423         /* Upon link speed change set the NIG into drain mode. Comes to
6424          * deals with possible FIFO glitch due to clk change when speed
6425          * is decreased without link down indicator
6426          */
6427
6428         if (vars->phy_link_up) {
6429                 if (!(ELINK_SINGLE_MEDIA_DIRECT(params)) && ext_phy_link_up &&
6430                     (ext_phy_line_speed != vars->line_speed)) {
6431                         PMD_DRV_LOG(DEBUG, "Internal link speed %d is"
6432                                     " different than the external"
6433                                     " link speed %d", vars->line_speed,
6434                                     ext_phy_line_speed);
6435                         vars->phy_link_up = 0;
6436                 } else if (prev_line_speed != vars->line_speed) {
6437                         REG_WR(sc,
6438                                NIG_REG_EGRESS_DRAIN0_MODE + params->port * 4,
6439                                0);
6440                         DELAY(1000 * 1);
6441                 }
6442         }
6443
6444         /* Anything 10 and over uses the bmac */
6445         link_10g_plus = (vars->line_speed >= ELINK_SPEED_10000);
6446
6447         elink_link_int_ack(params, vars, link_10g_plus);
6448
6449         /* In case external phy link is up, and internal link is down
6450          * (not initialized yet probably after link initialization, it
6451          * needs to be initialized.
6452          * Note that after link down-up as result of cable plug, the xgxs
6453          * link would probably become up again without the need
6454          * initialize it
6455          */
6456         if (!(ELINK_SINGLE_MEDIA_DIRECT(params))) {
6457                 PMD_DRV_LOG(DEBUG, "ext_phy_link_up = %d, int_link_up = %d,"
6458                             " init_preceding = %d", ext_phy_link_up,
6459                             vars->phy_link_up,
6460                             params->phy[ELINK_EXT_PHY1].flags &
6461                             ELINK_FLAGS_INIT_XGXS_FIRST);
6462                 if (!(params->phy[ELINK_EXT_PHY1].flags &
6463                       ELINK_FLAGS_INIT_XGXS_FIRST)
6464                     && ext_phy_link_up && !vars->phy_link_up) {
6465                         vars->line_speed = ext_phy_line_speed;
6466                         if (vars->line_speed < ELINK_SPEED_1000)
6467                                 vars->phy_flags |= PHY_SGMII_FLAG;
6468                         else
6469                                 vars->phy_flags &= ~PHY_SGMII_FLAG;
6470
6471                         if (params->phy[ELINK_INT_PHY].config_init)
6472                                 params->phy[ELINK_INT_PHY].config_init(&params->
6473                                                                        phy
6474                                                                        [ELINK_INT_PHY],
6475                                                                        params,
6476                                                                        vars);
6477                 }
6478         }
6479         /* Link is up only if both local phy and external phy (in case of
6480          * non-direct board) are up and no fault detected on active PHY.
6481          */
6482         vars->link_up = (vars->phy_link_up &&
6483                          (ext_phy_link_up ||
6484                           ELINK_SINGLE_MEDIA_DIRECT(params)) &&
6485                          (phy_vars[active_external_phy].fault_detected == 0));
6486
6487         /* Update the PFC configuration in case it was changed */
6488         if (params->feature_config_flags & ELINK_FEATURE_CONFIG_PFC_ENABLED)
6489                 vars->link_status |= LINK_STATUS_PFC_ENABLED;
6490         else
6491                 vars->link_status &= ~LINK_STATUS_PFC_ENABLED;
6492
6493         if (vars->link_up)
6494                 rc = elink_update_link_up(params, vars, link_10g_plus);
6495         else
6496                 rc = elink_update_link_down(params, vars);
6497
6498         /* Update MCP link status was changed */
6499         if (params->
6500             feature_config_flags & ELINK_FEATURE_CONFIG_BC_SUPPORTS_AFEX)
6501                 elink_cb_fw_command(sc, DRV_MSG_CODE_LINK_STATUS_CHANGED, 0);
6502
6503         return rc;
6504 }
6505
6506 /*****************************************************************************/
6507 /*                          External Phy section                             */
6508 /*****************************************************************************/
6509 static void elink_ext_phy_hw_reset(struct bnx2x_softc *sc, uint8_t port)
6510 {
6511         elink_cb_gpio_write(sc, MISC_REGISTERS_GPIO_1,
6512                             MISC_REGISTERS_GPIO_OUTPUT_LOW, port);
6513         DELAY(1000 * 1);
6514         elink_cb_gpio_write(sc, MISC_REGISTERS_GPIO_1,
6515                             MISC_REGISTERS_GPIO_OUTPUT_HIGH, port);
6516 }
6517
6518 static void elink_save_spirom_version(struct bnx2x_softc *sc,
6519                                       __rte_unused uint8_t port,
6520                                       uint32_t spirom_ver, uint32_t ver_addr)
6521 {
6522         PMD_DRV_LOG(DEBUG, "FW version 0x%x:0x%x for port %d",
6523                     (uint16_t) (spirom_ver >> 16), (uint16_t) spirom_ver, port);
6524
6525         if (ver_addr)
6526                 REG_WR(sc, ver_addr, spirom_ver);
6527 }
6528
6529 static void elink_save_bnx2x_spirom_ver(struct bnx2x_softc *sc,
6530                                       struct elink_phy *phy, uint8_t port)
6531 {
6532         uint16_t fw_ver1, fw_ver2;
6533
6534         elink_cl45_read(sc, phy, MDIO_PMA_DEVAD,
6535                         MDIO_PMA_REG_ROM_VER1, &fw_ver1);
6536         elink_cl45_read(sc, phy, MDIO_PMA_DEVAD,
6537                         MDIO_PMA_REG_ROM_VER2, &fw_ver2);
6538         elink_save_spirom_version(sc, port,
6539                                   (uint32_t) (fw_ver1 << 16 | fw_ver2),
6540                                   phy->ver_addr);
6541 }
6542
6543 static void elink_ext_phy_10G_an_resolve(struct bnx2x_softc *sc,
6544                                          struct elink_phy *phy,
6545                                          struct elink_vars *vars)
6546 {
6547         uint16_t val;
6548         elink_cl45_read(sc, phy, MDIO_AN_DEVAD, MDIO_AN_REG_STATUS, &val);
6549         elink_cl45_read(sc, phy, MDIO_AN_DEVAD, MDIO_AN_REG_STATUS, &val);
6550         if (val & (1 << 5))
6551                 vars->link_status |= LINK_STATUS_AUTO_NEGOTIATE_COMPLETE;
6552         if ((val & (1 << 0)) == 0)
6553                 vars->link_status |= LINK_STATUS_PARALLEL_DETECTION_USED;
6554 }
6555
6556 /******************************************************************/
6557 /*              common BNX2X8073/BNX2X8727 PHY SECTION            */
6558 /******************************************************************/
6559 static void elink_8073_resolve_fc(struct elink_phy *phy,
6560                                   struct elink_params *params,
6561                                   struct elink_vars *vars)
6562 {
6563         struct bnx2x_softc *sc = params->sc;
6564         if (phy->req_line_speed == ELINK_SPEED_10 ||
6565             phy->req_line_speed == ELINK_SPEED_100) {
6566                 vars->flow_ctrl = phy->req_flow_ctrl;
6567                 return;
6568         }
6569
6570         if (elink_ext_phy_resolve_fc(phy, params, vars) &&
6571             (vars->flow_ctrl == ELINK_FLOW_CTRL_NONE)) {
6572                 uint16_t pause_result;
6573                 uint16_t ld_pause;      /* local */
6574                 uint16_t lp_pause;      /* link partner */
6575                 elink_cl45_read(sc, phy,
6576                                 MDIO_AN_DEVAD,
6577                                 MDIO_AN_REG_CL37_FC_LD, &ld_pause);
6578
6579                 elink_cl45_read(sc, phy,
6580                                 MDIO_AN_DEVAD,
6581                                 MDIO_AN_REG_CL37_FC_LP, &lp_pause);
6582                 pause_result = (ld_pause &
6583                                 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) >> 5;
6584                 pause_result |= (lp_pause &
6585                                  MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) >> 7;
6586
6587                 elink_pause_resolve(vars, pause_result);
6588                 PMD_DRV_LOG(DEBUG, "Ext PHY CL37 pause result 0x%x",
6589                             pause_result);
6590         }
6591 }
6592
6593 static elink_status_t elink_8073_8727_external_rom_boot(struct bnx2x_softc *sc,
6594                                                         struct elink_phy *phy,
6595                                                         uint8_t port)
6596 {
6597         uint32_t count = 0;
6598         uint16_t fw_ver1 = 0, fw_msgout;
6599         elink_status_t rc = ELINK_STATUS_OK;
6600
6601         /* Boot port from external ROM  */
6602         /* EDC grst */
6603         elink_cl45_write(sc, phy,
6604                          MDIO_PMA_DEVAD, MDIO_PMA_REG_GEN_CTRL, 0x0001);
6605
6606         /* Ucode reboot and rst */
6607         elink_cl45_write(sc, phy,
6608                          MDIO_PMA_DEVAD, MDIO_PMA_REG_GEN_CTRL, 0x008c);
6609
6610         elink_cl45_write(sc, phy,
6611                          MDIO_PMA_DEVAD, MDIO_PMA_REG_MISC_CTRL1, 0x0001);
6612
6613         /* Reset internal microprocessor */
6614         elink_cl45_write(sc, phy,
6615                          MDIO_PMA_DEVAD,
6616                          MDIO_PMA_REG_GEN_CTRL,
6617                          MDIO_PMA_REG_GEN_CTRL_ROM_MICRO_RESET);
6618
6619         /* Release srst bit */
6620         elink_cl45_write(sc, phy,
6621                          MDIO_PMA_DEVAD,
6622                          MDIO_PMA_REG_GEN_CTRL,
6623                          MDIO_PMA_REG_GEN_CTRL_ROM_RESET_INTERNAL_MP);
6624
6625         /* Delay 100ms per the PHY specifications */
6626         DELAY(1000 * 100);
6627
6628         /* 8073 sometimes taking longer to download */
6629         do {
6630                 count++;
6631                 if (count > 300) {
6632                         PMD_DRV_LOG(DEBUG,
6633                                     "elink_8073_8727_external_rom_boot port %x:"
6634                                     "Download failed. fw version = 0x%x",
6635                                     port, fw_ver1);
6636                         rc = ELINK_STATUS_ERROR;
6637                         break;
6638                 }
6639
6640                 elink_cl45_read(sc, phy,
6641                                 MDIO_PMA_DEVAD,
6642                                 MDIO_PMA_REG_ROM_VER1, &fw_ver1);
6643                 elink_cl45_read(sc, phy,
6644                                 MDIO_PMA_DEVAD,
6645                                 MDIO_PMA_REG_M8051_MSGOUT_REG, &fw_msgout);
6646
6647                 DELAY(1000 * 1);
6648         } while (fw_ver1 == 0 || fw_ver1 == 0x4321 ||
6649                  ((fw_msgout & 0xff) != 0x03 && (phy->type ==
6650                                                  PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X8073)));
6651
6652         /* Clear ser_boot_ctl bit */
6653         elink_cl45_write(sc, phy,
6654                          MDIO_PMA_DEVAD, MDIO_PMA_REG_MISC_CTRL1, 0x0000);
6655         elink_save_bnx2x_spirom_ver(sc, phy, port);
6656
6657         PMD_DRV_LOG(DEBUG,
6658                     "elink_8073_8727_external_rom_boot port %x:"
6659                     "Download complete. fw version = 0x%x", port, fw_ver1);
6660
6661         return rc;
6662 }
6663
6664 /******************************************************************/
6665 /*                      BNX2X8073 PHY SECTION                     */
6666 /******************************************************************/
6667 static elink_status_t elink_8073_is_snr_needed(struct bnx2x_softc *sc,
6668                                                struct elink_phy *phy)
6669 {
6670         /* This is only required for 8073A1, version 102 only */
6671         uint16_t val;
6672
6673         /* Read 8073 HW revision */
6674         elink_cl45_read(sc, phy,
6675                         MDIO_PMA_DEVAD, MDIO_PMA_REG_8073_CHIP_REV, &val);
6676
6677         if (val != 1) {
6678                 /* No need to workaround in 8073 A1 */
6679                 return ELINK_STATUS_OK;
6680         }
6681
6682         elink_cl45_read(sc, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_ROM_VER2, &val);
6683
6684         /* SNR should be applied only for version 0x102 */
6685         if (val != 0x102)
6686                 return ELINK_STATUS_OK;
6687
6688         return ELINK_STATUS_ERROR;
6689 }
6690
6691 static elink_status_t elink_8073_xaui_wa(struct bnx2x_softc *sc,
6692                                          struct elink_phy *phy)
6693 {
6694         uint16_t val, cnt, cnt1;
6695
6696         elink_cl45_read(sc, phy,
6697                         MDIO_PMA_DEVAD, MDIO_PMA_REG_8073_CHIP_REV, &val);
6698
6699         if (val > 0) {
6700                 /* No need to workaround in 8073 A1 */
6701                 return ELINK_STATUS_OK;
6702         }
6703         /* XAUI workaround in 8073 A0: */
6704
6705         /* After loading the boot ROM and restarting Autoneg, poll
6706          * Dev1, Reg $C820:
6707          */
6708
6709         for (cnt = 0; cnt < 1000; cnt++) {
6710                 elink_cl45_read(sc, phy,
6711                                 MDIO_PMA_DEVAD,
6712                                 MDIO_PMA_REG_8073_SPEED_LINK_STATUS, &val);
6713                 /* If bit [14] = 0 or bit [13] = 0, continue on with
6714                  * system initialization (XAUI work-around not required, as
6715                  * these bits indicate 2.5G or 1G link up).
6716                  */
6717                 if (!(val & (1 << 14)) || !(val & (1 << 13))) {
6718                         PMD_DRV_LOG(DEBUG, "XAUI work-around not required");
6719                         return ELINK_STATUS_OK;
6720                 } else if (!(val & (1 << 15))) {
6721                         PMD_DRV_LOG(DEBUG, "bit 15 went off");
6722                         /* If bit 15 is 0, then poll Dev1, Reg $C841 until it's
6723                          * MSB (bit15) goes to 1 (indicating that the XAUI
6724                          * workaround has completed), then continue on with
6725                          * system initialization.
6726                          */
6727                         for (cnt1 = 0; cnt1 < 1000; cnt1++) {
6728                                 elink_cl45_read(sc, phy,
6729                                                 MDIO_PMA_DEVAD,
6730                                                 MDIO_PMA_REG_8073_XAUI_WA,
6731                                                 &val);
6732                                 if (val & (1 << 15)) {
6733                                         PMD_DRV_LOG(DEBUG,
6734                                                     "XAUI workaround has completed");
6735                                         return ELINK_STATUS_OK;
6736                                 }
6737                                 DELAY(1000 * 3);
6738                         }
6739                         break;
6740                 }
6741                 DELAY(1000 * 3);
6742         }
6743         PMD_DRV_LOG(DEBUG, "Warning: XAUI work-around timeout !!!");
6744         return ELINK_STATUS_ERROR;
6745 }
6746
6747 static void elink_807x_force_10G(struct bnx2x_softc *sc, struct elink_phy *phy)
6748 {
6749         /* Force KR or KX */
6750         elink_cl45_write(sc, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x2040);
6751         elink_cl45_write(sc, phy,
6752                          MDIO_PMA_DEVAD, MDIO_PMA_REG_10G_CTRL2, 0x000b);
6753         elink_cl45_write(sc, phy,
6754                          MDIO_PMA_DEVAD, MDIO_PMA_REG_BNX2X_CTRL, 0x0000);
6755         elink_cl45_write(sc, phy, MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0x0000);
6756 }
6757
6758 static void elink_8073_set_pause_cl37(struct elink_params *params,
6759                                       struct elink_phy *phy,
6760                                       struct elink_vars *vars)
6761 {
6762         uint16_t cl37_val;
6763         struct bnx2x_softc *sc = params->sc;
6764         elink_cl45_read(sc, phy,
6765                         MDIO_AN_DEVAD, MDIO_AN_REG_CL37_FC_LD, &cl37_val);
6766
6767         cl37_val &= ~MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH;
6768         /* Please refer to Table 28B-3 of 802.3ab-1999 spec. */
6769         elink_calc_ieee_aneg_adv(phy, params, &vars->ieee_fc);
6770         if ((vars->ieee_fc &
6771              MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_SYMMETRIC) ==
6772             MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_SYMMETRIC) {
6773                 cl37_val |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_SYMMETRIC;
6774         }
6775         if ((vars->ieee_fc &
6776              MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC) ==
6777             MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC) {
6778                 cl37_val |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC;
6779         }
6780         if ((vars->ieee_fc &
6781              MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) ==
6782             MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) {
6783                 cl37_val |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH;
6784         }
6785         PMD_DRV_LOG(DEBUG, "Ext phy AN advertize cl37 0x%x", cl37_val);
6786
6787         elink_cl45_write(sc, phy,
6788                          MDIO_AN_DEVAD, MDIO_AN_REG_CL37_FC_LD, cl37_val);
6789         DELAY(1000 * 500);
6790 }
6791
6792 static void elink_8073_specific_func(struct elink_phy *phy,
6793                                      struct elink_params *params,
6794                                      uint32_t action)
6795 {
6796         struct bnx2x_softc *sc = params->sc;
6797         switch (action) {
6798         case ELINK_PHY_INIT:
6799                 /* Enable LASI */
6800                 elink_cl45_write(sc, phy,
6801                                  MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXCTRL,
6802                                  (1 << 2));
6803                 elink_cl45_write(sc, phy, MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL,
6804                                  0x0004);
6805                 break;
6806         }
6807 }
6808
6809 static uint8_t elink_8073_config_init(struct elink_phy *phy,
6810                                       struct elink_params *params,
6811                                       struct elink_vars *vars)
6812 {
6813         struct bnx2x_softc *sc = params->sc;
6814         uint16_t val = 0, tmp1;
6815         uint8_t gpio_port;
6816         PMD_DRV_LOG(DEBUG, "Init 8073");
6817
6818         if (CHIP_IS_E2(sc))
6819                 gpio_port = SC_PATH(sc);
6820         else
6821                 gpio_port = params->port;
6822         /* Restore normal power mode */
6823         elink_cb_gpio_write(sc, MISC_REGISTERS_GPIO_2,
6824                             MISC_REGISTERS_GPIO_OUTPUT_HIGH, gpio_port);
6825
6826         elink_cb_gpio_write(sc, MISC_REGISTERS_GPIO_1,
6827                             MISC_REGISTERS_GPIO_OUTPUT_HIGH, gpio_port);
6828
6829         elink_8073_specific_func(phy, params, ELINK_PHY_INIT);
6830         elink_8073_set_pause_cl37(params, phy, vars);
6831
6832         elink_cl45_read(sc, phy,
6833                         MDIO_PMA_DEVAD, MDIO_PMA_REG_M8051_MSGOUT_REG, &tmp1);
6834
6835         elink_cl45_read(sc, phy, MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXSTAT, &tmp1);
6836
6837         PMD_DRV_LOG(DEBUG, "Before rom RX_ALARM(port1): 0x%x", tmp1);
6838
6839         /* Swap polarity if required - Must be done only in non-1G mode */
6840         if (params->lane_config & PORT_HW_CFG_SWAP_PHY_POLARITY_ENABLED) {
6841                 /* Configure the 8073 to swap _P and _N of the KR lines */
6842                 PMD_DRV_LOG(DEBUG, "Swapping polarity for the 8073");
6843                 /* 10G Rx/Tx and 1G Tx signal polarity swap */
6844                 elink_cl45_read(sc, phy,
6845                                 MDIO_PMA_DEVAD,
6846                                 MDIO_PMA_REG_8073_OPT_DIGITAL_CTRL, &val);
6847                 elink_cl45_write(sc, phy,
6848                                  MDIO_PMA_DEVAD,
6849                                  MDIO_PMA_REG_8073_OPT_DIGITAL_CTRL,
6850                                  (val | (3 << 9)));
6851         }
6852
6853         /* Enable CL37 BAM */
6854         if (REG_RD(sc, params->shmem_base +
6855                    offsetof(struct shmem_region,
6856                             dev_info.port_hw_config[params->port].
6857                             default_cfg)) &
6858             PORT_HW_CFG_ENABLE_BAM_ON_KR_ENABLED) {
6859
6860                 elink_cl45_read(sc, phy,
6861                                 MDIO_AN_DEVAD, MDIO_AN_REG_8073_BAM, &val);
6862                 elink_cl45_write(sc, phy,
6863                                  MDIO_AN_DEVAD, MDIO_AN_REG_8073_BAM, val | 1);
6864                 PMD_DRV_LOG(DEBUG, "Enable CL37 BAM on KR");
6865         }
6866         if (params->loopback_mode == ELINK_LOOPBACK_EXT) {
6867                 elink_807x_force_10G(sc, phy);
6868                 PMD_DRV_LOG(DEBUG, "Forced speed 10G on 807X");
6869                 return ELINK_STATUS_OK;
6870         } else {
6871                 elink_cl45_write(sc, phy,
6872                                  MDIO_PMA_DEVAD, MDIO_PMA_REG_BNX2X_CTRL, 0x0002);
6873         }
6874         if (phy->req_line_speed != ELINK_SPEED_AUTO_NEG) {
6875                 if (phy->req_line_speed == ELINK_SPEED_10000) {
6876                         val = (1 << 7);
6877                 } else if (phy->req_line_speed == ELINK_SPEED_2500) {
6878                         val = (1 << 5);
6879                         /* Note that 2.5G works only when used with 1G
6880                          * advertisement
6881                          */
6882                 } else
6883                         val = (1 << 5);
6884         } else {
6885                 val = 0;
6886                 if (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)
6887                         val |= (1 << 7);
6888
6889                 /* Note that 2.5G works only when used with 1G advertisement */
6890                 if (phy->speed_cap_mask &
6891                     (PORT_HW_CFG_SPEED_CAPABILITY_D0_1G |
6892                      PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G))
6893                         val |= (1 << 5);
6894                 PMD_DRV_LOG(DEBUG, "807x autoneg val = 0x%x", val);
6895         }
6896
6897         elink_cl45_write(sc, phy, MDIO_AN_DEVAD, MDIO_AN_REG_ADV, val);
6898         elink_cl45_read(sc, phy, MDIO_AN_DEVAD, MDIO_AN_REG_8073_2_5G, &tmp1);
6899
6900         if (((phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G) &&
6901              (phy->req_line_speed == ELINK_SPEED_AUTO_NEG)) ||
6902             (phy->req_line_speed == ELINK_SPEED_2500)) {
6903                 uint16_t phy_ver;
6904                 /* Allow 2.5G for A1 and above */
6905                 elink_cl45_read(sc, phy,
6906                                 MDIO_PMA_DEVAD, MDIO_PMA_REG_8073_CHIP_REV,
6907                                 &phy_ver);
6908                 PMD_DRV_LOG(DEBUG, "Add 2.5G");
6909                 if (phy_ver > 0)
6910                         tmp1 |= 1;
6911                 else
6912                         tmp1 &= 0xfffe;
6913         } else {
6914                 PMD_DRV_LOG(DEBUG, "Disable 2.5G");
6915                 tmp1 &= 0xfffe;
6916         }
6917
6918         elink_cl45_write(sc, phy, MDIO_AN_DEVAD, MDIO_AN_REG_8073_2_5G, tmp1);
6919         /* Add support for CL37 (passive mode) II */
6920
6921         elink_cl45_read(sc, phy, MDIO_AN_DEVAD, MDIO_AN_REG_CL37_FC_LD, &tmp1);
6922         elink_cl45_write(sc, phy, MDIO_AN_DEVAD, MDIO_AN_REG_CL37_FC_LD,
6923                          (tmp1 | ((phy->req_duplex == DUPLEX_FULL) ?
6924                                   0x20 : 0x40)));
6925
6926         /* Add support for CL37 (passive mode) III */
6927         elink_cl45_write(sc, phy, MDIO_AN_DEVAD, MDIO_AN_REG_CL37_AN, 0x1000);
6928
6929         /* The SNR will improve about 2db by changing BW and FEE main
6930          * tap. Rest commands are executed after link is up
6931          * Change FFE main cursor to 5 in EDC register
6932          */
6933         if (elink_8073_is_snr_needed(sc, phy))
6934                 elink_cl45_write(sc, phy,
6935                                  MDIO_PMA_DEVAD, MDIO_PMA_REG_EDC_FFE_MAIN,
6936                                  0xFB0C);
6937
6938         /* Enable FEC (Forware Error Correction) Request in the AN */
6939         elink_cl45_read(sc, phy, MDIO_AN_DEVAD, MDIO_AN_REG_ADV2, &tmp1);
6940         tmp1 |= (1 << 15);
6941         elink_cl45_write(sc, phy, MDIO_AN_DEVAD, MDIO_AN_REG_ADV2, tmp1);
6942
6943         elink_ext_phy_set_pause(params, phy, vars);
6944
6945         /* Restart autoneg */
6946         DELAY(1000 * 500);
6947         elink_cl45_write(sc, phy, MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0x1200);
6948         PMD_DRV_LOG(DEBUG, "807x Autoneg Restart: Advertise 1G=%x, 10G=%x",
6949                     ((val & (1 << 5)) > 0), ((val & (1 << 7)) > 0));
6950         return ELINK_STATUS_OK;
6951 }
6952
6953 static uint8_t elink_8073_read_status(struct elink_phy *phy,
6954                                       struct elink_params *params,
6955                                       struct elink_vars *vars)
6956 {
6957         struct bnx2x_softc *sc = params->sc;
6958         uint8_t link_up = 0;
6959         uint16_t val1, val2;
6960         uint16_t link_status = 0;
6961         uint16_t an1000_status = 0;
6962
6963         elink_cl45_read(sc, phy, MDIO_PMA_DEVAD, MDIO_PMA_LASI_STAT, &val1);
6964
6965         PMD_DRV_LOG(DEBUG, "8703 LASI status 0x%x", val1);
6966
6967         /* Clear the interrupt LASI status register */
6968         elink_cl45_read(sc, phy, MDIO_PCS_DEVAD, MDIO_PCS_REG_STATUS, &val2);
6969         elink_cl45_read(sc, phy, MDIO_PCS_DEVAD, MDIO_PCS_REG_STATUS, &val1);
6970         PMD_DRV_LOG(DEBUG, "807x PCS status 0x%x->0x%x", val2, val1);
6971         /* Clear MSG-OUT */
6972         elink_cl45_read(sc, phy,
6973                         MDIO_PMA_DEVAD, MDIO_PMA_REG_M8051_MSGOUT_REG, &val1);
6974
6975         /* Check the LASI */
6976         elink_cl45_read(sc, phy, MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXSTAT, &val2);
6977
6978         PMD_DRV_LOG(DEBUG, "KR 0x9003 0x%x", val2);
6979
6980         /* Check the link status */
6981         elink_cl45_read(sc, phy, MDIO_PCS_DEVAD, MDIO_PCS_REG_STATUS, &val2);
6982         PMD_DRV_LOG(DEBUG, "KR PCS status 0x%x", val2);
6983
6984         elink_cl45_read(sc, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_STATUS, &val2);
6985         elink_cl45_read(sc, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_STATUS, &val1);
6986         link_up = ((val1 & 4) == 4);
6987         PMD_DRV_LOG(DEBUG, "PMA_REG_STATUS=0x%x", val1);
6988
6989         if (link_up && ((phy->req_line_speed != ELINK_SPEED_10000))) {
6990                 if (elink_8073_xaui_wa(sc, phy) != 0)
6991                         return 0;
6992         }
6993         elink_cl45_read(sc, phy,
6994                         MDIO_AN_DEVAD, MDIO_AN_REG_LINK_STATUS, &an1000_status);
6995         elink_cl45_read(sc, phy,
6996                         MDIO_AN_DEVAD, MDIO_AN_REG_LINK_STATUS, &an1000_status);
6997
6998         /* Check the link status on 1.1.2 */
6999         elink_cl45_read(sc, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_STATUS, &val2);
7000         elink_cl45_read(sc, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_STATUS, &val1);
7001         PMD_DRV_LOG(DEBUG, "KR PMA status 0x%x->0x%x,"
7002                     "an_link_status=0x%x", val2, val1, an1000_status);
7003
7004         link_up = (((val1 & 4) == 4) || (an1000_status & (1 << 1)));
7005         if (link_up && elink_8073_is_snr_needed(sc, phy)) {
7006                 /* The SNR will improve about 2dbby changing the BW and FEE main
7007                  * tap. The 1st write to change FFE main tap is set before
7008                  * restart AN. Change PLL Bandwidth in EDC register
7009                  */
7010                 elink_cl45_write(sc, phy,
7011                                  MDIO_PMA_DEVAD, MDIO_PMA_REG_PLL_BANDWIDTH,
7012                                  0x26BC);
7013
7014                 /* Change CDR Bandwidth in EDC register */
7015                 elink_cl45_write(sc, phy,
7016                                  MDIO_PMA_DEVAD, MDIO_PMA_REG_CDR_BANDWIDTH,
7017                                  0x0333);
7018         }
7019         elink_cl45_read(sc, phy,
7020                         MDIO_PMA_DEVAD, MDIO_PMA_REG_8073_SPEED_LINK_STATUS,
7021                         &link_status);
7022
7023         /* Bits 0..2 --> speed detected, bits 13..15--> link is down */
7024         if ((link_status & (1 << 2)) && (!(link_status & (1 << 15)))) {
7025                 link_up = 1;
7026                 vars->line_speed = ELINK_SPEED_10000;
7027                 PMD_DRV_LOG(DEBUG, "port %x: External link up in 10G",
7028                             params->port);
7029         } else if ((link_status & (1 << 1)) && (!(link_status & (1 << 14)))) {
7030                 link_up = 1;
7031                 vars->line_speed = ELINK_SPEED_2500;
7032                 PMD_DRV_LOG(DEBUG, "port %x: External link up in 2.5G",
7033                             params->port);
7034         } else if ((link_status & (1 << 0)) && (!(link_status & (1 << 13)))) {
7035                 link_up = 1;
7036                 vars->line_speed = ELINK_SPEED_1000;
7037                 PMD_DRV_LOG(DEBUG, "port %x: External link up in 1G",
7038                             params->port);
7039         } else {
7040                 link_up = 0;
7041                 PMD_DRV_LOG(DEBUG, "port %x: External link is down",
7042                             params->port);
7043         }
7044
7045         if (link_up) {
7046                 /* Swap polarity if required */
7047                 if (params->lane_config & PORT_HW_CFG_SWAP_PHY_POLARITY_ENABLED) {
7048                         /* Configure the 8073 to swap P and N of the KR lines */
7049                         elink_cl45_read(sc, phy,
7050                                         MDIO_XS_DEVAD,
7051                                         MDIO_XS_REG_8073_RX_CTRL_PCIE, &val1);
7052                         /* Set bit 3 to invert Rx in 1G mode and clear this bit
7053                          * when it`s in 10G mode.
7054                          */
7055                         if (vars->line_speed == ELINK_SPEED_1000) {
7056                                 PMD_DRV_LOG(DEBUG, "Swapping 1G polarity for"
7057                                             "the 8073");
7058                                 val1 |= (1 << 3);
7059                         } else
7060                                 val1 &= ~(1 << 3);
7061
7062                         elink_cl45_write(sc, phy,
7063                                          MDIO_XS_DEVAD,
7064                                          MDIO_XS_REG_8073_RX_CTRL_PCIE, val1);
7065                 }
7066                 elink_ext_phy_10G_an_resolve(sc, phy, vars);
7067                 elink_8073_resolve_fc(phy, params, vars);
7068                 vars->duplex = DUPLEX_FULL;
7069         }
7070
7071         if (vars->link_status & LINK_STATUS_AUTO_NEGOTIATE_COMPLETE) {
7072                 elink_cl45_read(sc, phy, MDIO_AN_DEVAD,
7073                                 MDIO_AN_REG_LP_AUTO_NEG2, &val1);
7074
7075                 if (val1 & (1 << 5))
7076                         vars->link_status |=
7077                             LINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE;
7078                 if (val1 & (1 << 7))
7079                         vars->link_status |=
7080                             LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE;
7081         }
7082
7083         return link_up;
7084 }
7085
7086 static void elink_8073_link_reset(__rte_unused struct elink_phy *phy,
7087                                   struct elink_params *params)
7088 {
7089         struct bnx2x_softc *sc = params->sc;
7090         uint8_t gpio_port;
7091         if (CHIP_IS_E2(sc))
7092                 gpio_port = SC_PATH(sc);
7093         else
7094                 gpio_port = params->port;
7095         PMD_DRV_LOG(DEBUG, "Setting 8073 port %d into low power mode",
7096                     gpio_port);
7097         elink_cb_gpio_write(sc, MISC_REGISTERS_GPIO_2,
7098                             MISC_REGISTERS_GPIO_OUTPUT_LOW, gpio_port);
7099 }
7100
7101 /******************************************************************/
7102 /*                      BNX2X8705 PHY SECTION                     */
7103 /******************************************************************/
7104 static uint8_t elink_8705_config_init(struct elink_phy *phy,
7105                                       struct elink_params *params,
7106                                       __rte_unused struct elink_vars
7107                                              *vars)
7108 {
7109         struct bnx2x_softc *sc = params->sc;
7110         PMD_DRV_LOG(DEBUG, "init 8705");
7111         /* Restore normal power mode */
7112         elink_cb_gpio_write(sc, MISC_REGISTERS_GPIO_2,
7113                             MISC_REGISTERS_GPIO_OUTPUT_HIGH, params->port);
7114         /* HW reset */
7115         elink_ext_phy_hw_reset(sc, params->port);
7116         elink_cl45_write(sc, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0xa040);
7117         elink_wait_reset_complete(sc, phy, params);
7118
7119         elink_cl45_write(sc, phy,
7120                          MDIO_PMA_DEVAD, MDIO_PMA_REG_MISC_CTRL, 0x8288);
7121         elink_cl45_write(sc, phy,
7122                          MDIO_PMA_DEVAD, MDIO_PMA_REG_PHY_IDENTIFIER, 0x7fbf);
7123         elink_cl45_write(sc, phy,
7124                          MDIO_PMA_DEVAD, MDIO_PMA_REG_CMU_PLL_BYPASS, 0x0100);
7125         elink_cl45_write(sc, phy, MDIO_WIS_DEVAD, MDIO_WIS_REG_LASI_CNTL, 0x1);
7126         /* BNX2X8705 doesn't have microcode, hence the 0 */
7127         elink_save_spirom_version(sc, params->port, params->shmem_base, 0);
7128         return ELINK_STATUS_OK;
7129 }
7130
7131 static uint8_t elink_8705_read_status(struct elink_phy *phy,
7132                                       struct elink_params *params,
7133                                       struct elink_vars *vars)
7134 {
7135         uint8_t link_up = 0;
7136         uint16_t val1, rx_sd;
7137         struct bnx2x_softc *sc = params->sc;
7138         PMD_DRV_LOG(DEBUG, "read status 8705");
7139         elink_cl45_read(sc, phy,
7140                         MDIO_WIS_DEVAD, MDIO_WIS_REG_LASI_STATUS, &val1);
7141         PMD_DRV_LOG(DEBUG, "8705 LASI status 0x%x", val1);
7142
7143         elink_cl45_read(sc, phy,
7144                         MDIO_WIS_DEVAD, MDIO_WIS_REG_LASI_STATUS, &val1);
7145         PMD_DRV_LOG(DEBUG, "8705 LASI status 0x%x", val1);
7146
7147         elink_cl45_read(sc, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_RX_SD, &rx_sd);
7148
7149         elink_cl45_read(sc, phy, MDIO_PMA_DEVAD, 0xc809, &val1);
7150         elink_cl45_read(sc, phy, MDIO_PMA_DEVAD, 0xc809, &val1);
7151
7152         PMD_DRV_LOG(DEBUG, "8705 1.c809 val=0x%x", val1);
7153         link_up = ((rx_sd & 0x1) && (val1 & (1 << 9))
7154                    && ((val1 & (1 << 8)) == 0));
7155         if (link_up) {
7156                 vars->line_speed = ELINK_SPEED_10000;
7157                 elink_ext_phy_resolve_fc(phy, params, vars);
7158         }
7159         return link_up;
7160 }
7161
7162 /******************************************************************/
7163 /*                      SFP+ module Section                       */
7164 /******************************************************************/
7165 static void elink_set_disable_pmd_transmit(struct elink_params *params,
7166                                            struct elink_phy *phy,
7167                                            uint8_t pmd_dis)
7168 {
7169         struct bnx2x_softc *sc = params->sc;
7170         /* Disable transmitter only for bootcodes which can enable it afterwards
7171          * (for D3 link)
7172          */
7173         if (pmd_dis) {
7174                 if (params->feature_config_flags &
7175                     ELINK_FEATURE_CONFIG_BC_SUPPORTS_SFP_TX_DISABLED) {
7176                         PMD_DRV_LOG(DEBUG, "Disabling PMD transmitter");
7177                 } else {
7178                         PMD_DRV_LOG(DEBUG, "NOT disabling PMD transmitter");
7179                         return;
7180                 }
7181         } else {
7182                 PMD_DRV_LOG(DEBUG, "Enabling PMD transmitter");
7183         }
7184         elink_cl45_write(sc, phy,
7185                          MDIO_PMA_DEVAD, MDIO_PMA_REG_TX_DISABLE, pmd_dis);
7186 }
7187
7188 static uint8_t elink_get_gpio_port(struct elink_params *params)
7189 {
7190         uint8_t gpio_port;
7191         uint32_t swap_val, swap_override;
7192         struct bnx2x_softc *sc = params->sc;
7193         if (CHIP_IS_E2(sc)) {
7194                 gpio_port = SC_PATH(sc);
7195         } else {
7196                 gpio_port = params->port;
7197         }
7198         swap_val = REG_RD(sc, NIG_REG_PORT_SWAP);
7199         swap_override = REG_RD(sc, NIG_REG_STRAP_OVERRIDE);
7200         return gpio_port ^ (swap_val && swap_override);
7201 }
7202
7203 static void elink_sfp_e1e2_set_transmitter(struct elink_params *params,
7204                                            struct elink_phy *phy, uint8_t tx_en)
7205 {
7206         uint16_t val;
7207         uint8_t port = params->port;
7208         struct bnx2x_softc *sc = params->sc;
7209         uint32_t tx_en_mode;
7210
7211         /* Disable/Enable transmitter ( TX laser of the SFP+ module.) */
7212         tx_en_mode = REG_RD(sc, params->shmem_base +
7213                             offsetof(struct shmem_region,
7214                                      dev_info.port_hw_config[port].sfp_ctrl)) &
7215             PORT_HW_CFG_TX_LASER_MASK;
7216         PMD_DRV_LOG(DEBUG, "Setting transmitter tx_en=%x for port %x "
7217                     "mode = %x", tx_en, port, tx_en_mode);
7218         switch (tx_en_mode) {
7219         case PORT_HW_CFG_TX_LASER_MDIO:
7220
7221                 elink_cl45_read(sc, phy,
7222                                 MDIO_PMA_DEVAD,
7223                                 MDIO_PMA_REG_PHY_IDENTIFIER, &val);
7224
7225                 if (tx_en)
7226                         val &= ~(1 << 15);
7227                 else
7228                         val |= (1 << 15);
7229
7230                 elink_cl45_write(sc, phy,
7231                                  MDIO_PMA_DEVAD,
7232                                  MDIO_PMA_REG_PHY_IDENTIFIER, val);
7233                 break;
7234         case PORT_HW_CFG_TX_LASER_GPIO0:
7235         case PORT_HW_CFG_TX_LASER_GPIO1:
7236         case PORT_HW_CFG_TX_LASER_GPIO2:
7237         case PORT_HW_CFG_TX_LASER_GPIO3:
7238                 {
7239                         uint16_t gpio_pin;
7240                         uint8_t gpio_port, gpio_mode;
7241                         if (tx_en)
7242                                 gpio_mode = MISC_REGISTERS_GPIO_OUTPUT_HIGH;
7243                         else
7244                                 gpio_mode = MISC_REGISTERS_GPIO_OUTPUT_LOW;
7245
7246                         gpio_pin = tx_en_mode - PORT_HW_CFG_TX_LASER_GPIO0;
7247                         gpio_port = elink_get_gpio_port(params);
7248                         elink_cb_gpio_write(sc, gpio_pin, gpio_mode, gpio_port);
7249                         break;
7250                 }
7251         default:
7252                 PMD_DRV_LOG(DEBUG, "Invalid TX_LASER_MDIO 0x%x", tx_en_mode);
7253                 break;
7254         }
7255 }
7256
7257 static void elink_sfp_set_transmitter(struct elink_params *params,
7258                                       struct elink_phy *phy, uint8_t tx_en)
7259 {
7260         struct bnx2x_softc *sc = params->sc;
7261         PMD_DRV_LOG(DEBUG, "Setting SFP+ transmitter to %d", tx_en);
7262         if (CHIP_IS_E3(sc))
7263                 elink_sfp_e3_set_transmitter(params, phy, tx_en);
7264         else
7265                 elink_sfp_e1e2_set_transmitter(params, phy, tx_en);
7266 }
7267
7268 static elink_status_t elink_8726_read_sfp_module_eeprom(struct elink_phy *phy,
7269                                                         struct elink_params
7270                                                         *params,
7271                                                         uint8_t dev_addr,
7272                                                         uint16_t addr,
7273                                                         uint8_t byte_cnt,
7274                                                         uint8_t * o_buf,
7275                                                         __rte_unused uint8_t
7276                                                         is_init)
7277 {
7278         struct bnx2x_softc *sc = params->sc;
7279         uint16_t val = 0;
7280         uint16_t i;
7281         if (byte_cnt > ELINK_SFP_EEPROM_PAGE_SIZE) {
7282                 PMD_DRV_LOG(DEBUG, "Reading from eeprom is limited to 0xf");
7283                 return ELINK_STATUS_ERROR;
7284         }
7285         /* Set the read command byte count */
7286         elink_cl45_write(sc, phy,
7287                          MDIO_PMA_DEVAD, MDIO_PMA_REG_SFP_TWO_WIRE_BYTE_CNT,
7288                          (byte_cnt | (dev_addr << 8)));
7289
7290         /* Set the read command address */
7291         elink_cl45_write(sc, phy,
7292                          MDIO_PMA_DEVAD, MDIO_PMA_REG_SFP_TWO_WIRE_MEM_ADDR,
7293                          addr);
7294
7295         /* Activate read command */
7296         elink_cl45_write(sc, phy,
7297                          MDIO_PMA_DEVAD, MDIO_PMA_REG_SFP_TWO_WIRE_CTRL,
7298                          0x2c0f);
7299
7300         /* Wait up to 500us for command complete status */
7301         for (i = 0; i < 100; i++) {
7302                 elink_cl45_read(sc, phy,
7303                                 MDIO_PMA_DEVAD,
7304                                 MDIO_PMA_REG_SFP_TWO_WIRE_CTRL, &val);
7305                 if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) ==
7306                     MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_COMPLETE)
7307                         break;
7308                 DELAY(5);
7309         }
7310
7311         if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) !=
7312             MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_COMPLETE) {
7313                 PMD_DRV_LOG(DEBUG,
7314                             "Got bad status 0x%x when reading from SFP+ EEPROM",
7315                             (val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK));
7316                 return ELINK_STATUS_ERROR;
7317         }
7318
7319         /* Read the buffer */
7320         for (i = 0; i < byte_cnt; i++) {
7321                 elink_cl45_read(sc, phy,
7322                                 MDIO_PMA_DEVAD,
7323                                 MDIO_PMA_REG_8726_TWO_WIRE_DATA_BUF + i, &val);
7324                 o_buf[i] =
7325                     (uint8_t) (val & MDIO_PMA_REG_8726_TWO_WIRE_DATA_MASK);
7326         }
7327
7328         for (i = 0; i < 100; i++) {
7329                 elink_cl45_read(sc, phy,
7330                                 MDIO_PMA_DEVAD,
7331                                 MDIO_PMA_REG_SFP_TWO_WIRE_CTRL, &val);
7332                 if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) ==
7333                     MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_IDLE)
7334                         return ELINK_STATUS_OK;
7335                 DELAY(1000 * 1);
7336         }
7337         return ELINK_STATUS_ERROR;
7338 }
7339
7340 static void elink_warpcore_power_module(struct elink_params *params,
7341                                         uint8_t power)
7342 {
7343         uint32_t pin_cfg;
7344         struct bnx2x_softc *sc = params->sc;
7345
7346         pin_cfg = (REG_RD(sc, params->shmem_base +
7347                           offsetof(struct shmem_region,
7348                                    dev_info.port_hw_config[params->port].
7349                                    e3_sfp_ctrl)) & PORT_HW_CFG_E3_PWR_DIS_MASK)
7350             >> PORT_HW_CFG_E3_PWR_DIS_SHIFT;
7351
7352         if (pin_cfg == PIN_CFG_NA)
7353                 return;
7354         PMD_DRV_LOG(DEBUG, "Setting SFP+ module power to %d using pin cfg %d",
7355                     power, pin_cfg);
7356         /* Low ==> corresponding SFP+ module is powered
7357          * high ==> the SFP+ module is powered down
7358          */
7359         elink_set_cfg_pin(sc, pin_cfg, power ^ 1);
7360 }
7361
7362 static elink_status_t elink_warpcore_read_sfp_module_eeprom(__rte_unused struct
7363                                                             elink_phy *phy,
7364                                                             struct elink_params
7365                                                             *params,
7366                                                             uint8_t dev_addr,
7367                                                             uint16_t addr,
7368                                                             uint8_t byte_cnt,
7369                                                             uint8_t * o_buf,
7370                                                             uint8_t is_init)
7371 {
7372         elink_status_t rc = ELINK_STATUS_OK;
7373         uint8_t i, j = 0, cnt = 0;
7374         uint32_t data_array[4];
7375         uint16_t addr32;
7376         struct bnx2x_softc *sc = params->sc;
7377
7378         if (byte_cnt > ELINK_SFP_EEPROM_PAGE_SIZE) {
7379                 PMD_DRV_LOG(DEBUG,
7380                             "Reading from eeprom is limited to 16 bytes");
7381                 return ELINK_STATUS_ERROR;
7382         }
7383
7384         /* 4 byte aligned address */
7385         addr32 = addr & (~0x3);
7386         do {
7387                 if ((!is_init) && (cnt == I2C_WA_PWR_ITER)) {
7388                         elink_warpcore_power_module(params, 0);
7389                         /* Note that 100us are not enough here */
7390                         DELAY(1000 * 1);
7391                         elink_warpcore_power_module(params, 1);
7392                 }
7393                 rc = elink_bsc_read(params, sc, dev_addr, addr32, 0, byte_cnt,
7394                                     data_array);
7395         } while ((rc != ELINK_STATUS_OK) && (++cnt < I2C_WA_RETRY_CNT));
7396
7397         if (rc == ELINK_STATUS_OK) {
7398                 for (i = (addr - addr32); i < byte_cnt + (addr - addr32); i++) {
7399                         o_buf[j] = *((uint8_t *) data_array + i);
7400                         j++;
7401                 }
7402         }
7403
7404         return rc;
7405 }
7406
7407 static elink_status_t elink_8727_read_sfp_module_eeprom(struct elink_phy *phy,
7408                                                         struct elink_params
7409                                                         *params,
7410                                                         uint8_t dev_addr,
7411                                                         uint16_t addr,
7412                                                         uint8_t byte_cnt,
7413                                                         uint8_t * o_buf,
7414                                                         __rte_unused uint8_t
7415                                                         is_init)
7416 {
7417         struct bnx2x_softc *sc = params->sc;
7418         uint16_t val, i;
7419
7420         if (byte_cnt > ELINK_SFP_EEPROM_PAGE_SIZE) {
7421                 PMD_DRV_LOG(DEBUG, "Reading from eeprom is limited to 0xf");
7422                 return ELINK_STATUS_ERROR;
7423         }
7424
7425         /* Set 2-wire transfer rate of SFP+ module EEPROM
7426          * to 100Khz since some DACs(direct attached cables) do
7427          * not work at 400Khz.
7428          */
7429         elink_cl45_write(sc, phy,
7430                          MDIO_PMA_DEVAD,
7431                          MDIO_PMA_REG_8727_TWO_WIRE_SLAVE_ADDR,
7432                          ((dev_addr << 8) | 1));
7433
7434         /* Need to read from 1.8000 to clear it */
7435         elink_cl45_read(sc, phy,
7436                         MDIO_PMA_DEVAD, MDIO_PMA_REG_SFP_TWO_WIRE_CTRL, &val);
7437
7438         /* Set the read command byte count */
7439         elink_cl45_write(sc, phy,
7440                          MDIO_PMA_DEVAD,
7441                          MDIO_PMA_REG_SFP_TWO_WIRE_BYTE_CNT,
7442                          ((byte_cnt < 2) ? 2 : byte_cnt));
7443
7444         /* Set the read command address */
7445         elink_cl45_write(sc, phy,
7446                          MDIO_PMA_DEVAD,
7447                          MDIO_PMA_REG_SFP_TWO_WIRE_MEM_ADDR, addr);
7448         /* Set the destination address */
7449         elink_cl45_write(sc, phy,
7450                          MDIO_PMA_DEVAD,
7451                          0x8004, MDIO_PMA_REG_8727_TWO_WIRE_DATA_BUF);
7452
7453         /* Activate read command */
7454         elink_cl45_write(sc, phy,
7455                          MDIO_PMA_DEVAD,
7456                          MDIO_PMA_REG_SFP_TWO_WIRE_CTRL, 0x8002);
7457         /* Wait appropriate time for two-wire command to finish before
7458          * polling the status register
7459          */
7460         DELAY(1000 * 1);
7461
7462         /* Wait up to 500us for command complete status */
7463         for (i = 0; i < 100; i++) {
7464                 elink_cl45_read(sc, phy,
7465                                 MDIO_PMA_DEVAD,
7466                                 MDIO_PMA_REG_SFP_TWO_WIRE_CTRL, &val);
7467                 if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) ==
7468                     MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_COMPLETE)
7469                         break;
7470                 DELAY(5);
7471         }
7472
7473         if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) !=
7474             MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_COMPLETE) {
7475                 PMD_DRV_LOG(DEBUG,
7476                             "Got bad status 0x%x when reading from SFP+ EEPROM",
7477                             (val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK));
7478                 return ELINK_STATUS_TIMEOUT;
7479         }
7480
7481         /* Read the buffer */
7482         for (i = 0; i < byte_cnt; i++) {
7483                 elink_cl45_read(sc, phy,
7484                                 MDIO_PMA_DEVAD,
7485                                 MDIO_PMA_REG_8727_TWO_WIRE_DATA_BUF + i, &val);
7486                 o_buf[i] =
7487                     (uint8_t) (val & MDIO_PMA_REG_8727_TWO_WIRE_DATA_MASK);
7488         }
7489
7490         for (i = 0; i < 100; i++) {
7491                 elink_cl45_read(sc, phy,
7492                                 MDIO_PMA_DEVAD,
7493                                 MDIO_PMA_REG_SFP_TWO_WIRE_CTRL, &val);
7494                 if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) ==
7495                     MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_IDLE)
7496                         return ELINK_STATUS_OK;
7497                 DELAY(1000 * 1);
7498         }
7499
7500         return ELINK_STATUS_ERROR;
7501 }
7502
7503 static elink_status_t elink_read_sfp_module_eeprom(struct elink_phy *phy,
7504                                                    struct elink_params *params,
7505                                                    uint8_t dev_addr,
7506                                                    uint16_t addr,
7507                                                    uint16_t byte_cnt,
7508                                                    uint8_t * o_buf)
7509 {
7510         elink_status_t rc = ELINK_STATUS_OK;
7511         uint8_t xfer_size;
7512         uint8_t *user_data = o_buf;
7513         read_sfp_module_eeprom_func_p read_func;
7514
7515         if ((dev_addr != 0xa0) && (dev_addr != 0xa2)) {
7516                 PMD_DRV_LOG(DEBUG, "invalid dev_addr 0x%x", dev_addr);
7517                 return ELINK_STATUS_ERROR;
7518         }
7519
7520         switch (phy->type) {
7521         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X8726:
7522                 read_func = elink_8726_read_sfp_module_eeprom;
7523                 break;
7524         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X8727:
7525         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X8722:
7526                 read_func = elink_8727_read_sfp_module_eeprom;
7527                 break;
7528         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT:
7529                 read_func = elink_warpcore_read_sfp_module_eeprom;
7530                 break;
7531         default:
7532                 return ELINK_OP_NOT_SUPPORTED;
7533         }
7534
7535         while (!rc && (byte_cnt > 0)) {
7536                 xfer_size = (byte_cnt > ELINK_SFP_EEPROM_PAGE_SIZE) ?
7537                     ELINK_SFP_EEPROM_PAGE_SIZE : byte_cnt;
7538                 rc = read_func(phy, params, dev_addr, addr, xfer_size,
7539                                user_data, 0);
7540                 byte_cnt -= xfer_size;
7541                 user_data += xfer_size;
7542                 addr += xfer_size;
7543         }
7544         return rc;
7545 }
7546
7547 static elink_status_t elink_get_edc_mode(struct elink_phy *phy,
7548                                          struct elink_params *params,
7549                                          uint16_t * edc_mode)
7550 {
7551         struct bnx2x_softc *sc = params->sc;
7552         uint32_t sync_offset = 0, phy_idx, media_types;
7553         uint8_t gport, val[2], check_limiting_mode = 0;
7554         *edc_mode = ELINK_EDC_MODE_LIMITING;
7555         phy->media_type = ELINK_ETH_PHY_UNSPECIFIED;
7556         /* First check for copper cable */
7557         if (elink_read_sfp_module_eeprom(phy,
7558                                          params,
7559                                          ELINK_I2C_DEV_ADDR_A0,
7560                                          ELINK_SFP_EEPROM_CON_TYPE_ADDR,
7561                                          2, (uint8_t *) val) != 0) {
7562                 PMD_DRV_LOG(DEBUG, "Failed to read from SFP+ module EEPROM");
7563                 return ELINK_STATUS_ERROR;
7564         }
7565
7566         switch (val[0]) {
7567         case ELINK_SFP_EEPROM_CON_TYPE_VAL_COPPER:
7568                 {
7569                         uint8_t copper_module_type;
7570                         phy->media_type = ELINK_ETH_PHY_DA_TWINAX;
7571                         /* Check if its active cable (includes SFP+ module)
7572                          * of passive cable
7573                          */
7574                         if (elink_read_sfp_module_eeprom(phy,
7575                                                          params,
7576                                                          ELINK_I2C_DEV_ADDR_A0,
7577                                                          ELINK_SFP_EEPROM_FC_TX_TECH_ADDR,
7578                                                          1,
7579                                                          &copper_module_type) !=
7580                             0) {
7581                                 PMD_DRV_LOG(DEBUG,
7582                                             "Failed to read copper-cable-type"
7583                                             " from SFP+ EEPROM");
7584                                 return ELINK_STATUS_ERROR;
7585                         }
7586
7587                         if (copper_module_type &
7588                             ELINK_SFP_EEPROM_FC_TX_TECH_BITMASK_COPPER_ACTIVE) {
7589                                 PMD_DRV_LOG(DEBUG,
7590                                             "Active Copper cable detected");
7591                                 if (phy->type ==
7592                                     PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT)
7593                                         *edc_mode = ELINK_EDC_MODE_ACTIVE_DAC;
7594                                 else
7595                                         check_limiting_mode = 1;
7596                         } else if (copper_module_type &
7597                                    ELINK_SFP_EEPROM_FC_TX_TECH_BITMASK_COPPER_PASSIVE)
7598                         {
7599                                 PMD_DRV_LOG(DEBUG,
7600                                             "Passive Copper cable detected");
7601                                 *edc_mode = ELINK_EDC_MODE_PASSIVE_DAC;
7602                         } else {
7603                                 PMD_DRV_LOG(DEBUG,
7604                                             "Unknown copper-cable-type 0x%x !!!",
7605                                             copper_module_type);
7606                                 return ELINK_STATUS_ERROR;
7607                         }
7608                         break;
7609                 }
7610         case ELINK_SFP_EEPROM_CON_TYPE_VAL_LC:
7611         case ELINK_SFP_EEPROM_CON_TYPE_VAL_RJ45:
7612                 check_limiting_mode = 1;
7613                 if ((val[1] & (ELINK_SFP_EEPROM_COMP_CODE_SR_MASK |
7614                                ELINK_SFP_EEPROM_COMP_CODE_LR_MASK |
7615                                ELINK_SFP_EEPROM_COMP_CODE_LRM_MASK)) == 0) {
7616                         PMD_DRV_LOG(DEBUG, "1G SFP module detected");
7617                         gport = params->port;
7618                         phy->media_type = ELINK_ETH_PHY_SFP_1G_FIBER;
7619                         if (phy->req_line_speed != ELINK_SPEED_1000) {
7620                                 phy->req_line_speed = ELINK_SPEED_1000;
7621                                 if (!CHIP_IS_E1x(sc)) {
7622                                         gport = SC_PATH(sc) +
7623                                             (params->port << 1);
7624                                 }
7625                                 elink_cb_event_log(sc, ELINK_LOG_ID_NON_10G_MODULE, gport);     //"Warning: Link speed was forced to 1000Mbps."
7626                                 // " Current SFP module in port %d is not"
7627                                 // " compliant with 10G Ethernet",
7628
7629                         }
7630                 } else {
7631                         int idx, cfg_idx = 0;
7632                         PMD_DRV_LOG(DEBUG, "10G Optic module detected");
7633                         for (idx = ELINK_INT_PHY; idx < ELINK_MAX_PHYS; idx++) {
7634                                 if (params->phy[idx].type == phy->type) {
7635                                         cfg_idx = ELINK_LINK_CONFIG_IDX(idx);
7636                                         break;
7637                                 }
7638                         }
7639                         phy->media_type = ELINK_ETH_PHY_SFPP_10G_FIBER;
7640                         phy->req_line_speed = params->req_line_speed[cfg_idx];
7641                 }
7642                 break;
7643         default:
7644                 PMD_DRV_LOG(DEBUG, "Unable to determine module type 0x%x !!!",
7645                             val[0]);
7646                 return ELINK_STATUS_ERROR;
7647         }
7648         sync_offset = params->shmem_base +
7649             offsetof(struct shmem_region,
7650                      dev_info.port_hw_config[params->port].media_type);
7651         media_types = REG_RD(sc, sync_offset);
7652         /* Update media type for non-PMF sync */
7653         for (phy_idx = ELINK_INT_PHY; phy_idx < ELINK_MAX_PHYS; phy_idx++) {
7654                 if (&(params->phy[phy_idx]) == phy) {
7655                         media_types &= ~(PORT_HW_CFG_MEDIA_TYPE_PHY0_MASK <<
7656                                          (PORT_HW_CFG_MEDIA_TYPE_PHY1_SHIFT *
7657                                           phy_idx));
7658                         media_types |=
7659                             ((phy->
7660                               media_type & PORT_HW_CFG_MEDIA_TYPE_PHY0_MASK) <<
7661                              (PORT_HW_CFG_MEDIA_TYPE_PHY1_SHIFT * phy_idx));
7662                         break;
7663                 }
7664         }
7665         REG_WR(sc, sync_offset, media_types);
7666         if (check_limiting_mode) {
7667                 uint8_t options[ELINK_SFP_EEPROM_OPTIONS_SIZE];
7668                 if (elink_read_sfp_module_eeprom(phy,
7669                                                  params,
7670                                                  ELINK_I2C_DEV_ADDR_A0,
7671                                                  ELINK_SFP_EEPROM_OPTIONS_ADDR,
7672                                                  ELINK_SFP_EEPROM_OPTIONS_SIZE,
7673                                                  options) != 0) {
7674                         PMD_DRV_LOG(DEBUG,
7675                                     "Failed to read Option field from module EEPROM");
7676                         return ELINK_STATUS_ERROR;
7677                 }
7678                 if ((options[0] & ELINK_SFP_EEPROM_OPTIONS_LINEAR_RX_OUT_MASK))
7679                         *edc_mode = ELINK_EDC_MODE_LINEAR;
7680                 else
7681                         *edc_mode = ELINK_EDC_MODE_LIMITING;
7682         }
7683         PMD_DRV_LOG(DEBUG, "EDC mode is set to 0x%x", *edc_mode);
7684         return ELINK_STATUS_OK;
7685 }
7686
7687 /* This function read the relevant field from the module (SFP+), and verify it
7688  * is compliant with this board
7689  */
7690 static elink_status_t elink_verify_sfp_module(struct elink_phy *phy,
7691                                               struct elink_params *params)
7692 {
7693         struct bnx2x_softc *sc = params->sc;
7694         uint32_t val, cmd;
7695         uint32_t fw_resp, fw_cmd_param;
7696         char vendor_name[ELINK_SFP_EEPROM_VENDOR_NAME_SIZE + 1];
7697         char vendor_pn[ELINK_SFP_EEPROM_PART_NO_SIZE + 1];
7698         phy->flags &= ~ELINK_FLAGS_SFP_NOT_APPROVED;
7699         val = REG_RD(sc, params->shmem_base +
7700                      offsetof(struct shmem_region,
7701                               dev_info.port_feature_config[params->port].
7702                               config));
7703         if ((val & PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK) ==
7704             PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_NO_ENFORCEMENT) {
7705                 PMD_DRV_LOG(DEBUG, "NOT enforcing module verification");
7706                 return ELINK_STATUS_OK;
7707         }
7708
7709         if (params->feature_config_flags &
7710             ELINK_FEATURE_CONFIG_BC_SUPPORTS_DUAL_PHY_OPT_MDL_VRFY) {
7711                 /* Use specific phy request */
7712                 cmd = DRV_MSG_CODE_VRFY_SPECIFIC_PHY_OPT_MDL;
7713         } else if (params->feature_config_flags &
7714                    ELINK_FEATURE_CONFIG_BC_SUPPORTS_OPT_MDL_VRFY) {
7715                 /* Use first phy request only in case of non-dual media */
7716                 if (ELINK_DUAL_MEDIA(params)) {
7717                         PMD_DRV_LOG(DEBUG,
7718                                     "FW does not support OPT MDL verification");
7719                         return ELINK_STATUS_ERROR;
7720                 }
7721                 cmd = DRV_MSG_CODE_VRFY_FIRST_PHY_OPT_MDL;
7722         } else {
7723                 /* No support in OPT MDL detection */
7724                 PMD_DRV_LOG(DEBUG, "FW does not support OPT MDL verification");
7725                 return ELINK_STATUS_ERROR;
7726         }
7727
7728         fw_cmd_param = ELINK_FW_PARAM_SET(phy->addr, phy->type, phy->mdio_ctrl);
7729         fw_resp = elink_cb_fw_command(sc, cmd, fw_cmd_param);
7730         if (fw_resp == FW_MSG_CODE_VRFY_OPT_MDL_SUCCESS) {
7731                 PMD_DRV_LOG(DEBUG, "Approved module");
7732                 return ELINK_STATUS_OK;
7733         }
7734
7735         /* Format the warning message */
7736         if (elink_read_sfp_module_eeprom(phy,
7737                                          params,
7738                                          ELINK_I2C_DEV_ADDR_A0,
7739                                          ELINK_SFP_EEPROM_VENDOR_NAME_ADDR,
7740                                          ELINK_SFP_EEPROM_VENDOR_NAME_SIZE,
7741                                          (uint8_t *) vendor_name))
7742                 vendor_name[0] = '\0';
7743         else
7744                 vendor_name[ELINK_SFP_EEPROM_VENDOR_NAME_SIZE] = '\0';
7745         if (elink_read_sfp_module_eeprom(phy,
7746                                          params,
7747                                          ELINK_I2C_DEV_ADDR_A0,
7748                                          ELINK_SFP_EEPROM_PART_NO_ADDR,
7749                                          ELINK_SFP_EEPROM_PART_NO_SIZE,
7750                                          (uint8_t *) vendor_pn))
7751                 vendor_pn[0] = '\0';
7752         else
7753                 vendor_pn[ELINK_SFP_EEPROM_PART_NO_SIZE] = '\0';
7754
7755         elink_cb_event_log(sc, ELINK_LOG_ID_UNQUAL_IO_MODULE, params->port, vendor_name, vendor_pn);    // "Warning: Unqualified SFP+ module detected,"
7756         // " Port %d from %s part number %s",
7757
7758         if ((val & PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK) !=
7759             PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_WARNING_MSG)
7760                 phy->flags |= ELINK_FLAGS_SFP_NOT_APPROVED;
7761         return ELINK_STATUS_ERROR;
7762 }
7763
7764 static elink_status_t elink_wait_for_sfp_module_initialized(struct elink_phy
7765                                                             *phy,
7766                                                             struct elink_params
7767                                                             *params)
7768 {
7769         uint8_t val;
7770         elink_status_t rc;
7771         uint16_t timeout;
7772         /* Initialization time after hot-plug may take up to 300ms for
7773          * some phys type ( e.g. JDSU )
7774          */
7775
7776         for (timeout = 0; timeout < 60; timeout++) {
7777                 if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT)
7778                         rc = elink_warpcore_read_sfp_module_eeprom(phy, params,
7779                                                                    ELINK_I2C_DEV_ADDR_A0,
7780                                                                    1, 1, &val,
7781                                                                    1);
7782                 else
7783                         rc = elink_read_sfp_module_eeprom(phy, params,
7784                                                           ELINK_I2C_DEV_ADDR_A0,
7785                                                           1, 1, &val);
7786                 if (rc == 0) {
7787                         PMD_DRV_LOG(DEBUG,
7788                                     "SFP+ module initialization took %d ms",
7789                                     timeout * 5);
7790                         return ELINK_STATUS_OK;
7791                 }
7792                 DELAY(1000 * 5);
7793         }
7794         rc = elink_read_sfp_module_eeprom(phy, params, ELINK_I2C_DEV_ADDR_A0,
7795                                           1, 1, &val);
7796         return rc;
7797 }
7798
7799 static void elink_8727_power_module(struct bnx2x_softc *sc,
7800                                     struct elink_phy *phy, uint8_t is_power_up)
7801 {
7802         /* Make sure GPIOs are not using for LED mode */
7803         uint16_t val;
7804         /* In the GPIO register, bit 4 is use to determine if the GPIOs are
7805          * operating as INPUT or as OUTPUT. Bit 1 is for input, and 0 for
7806          * output
7807          * Bits 0-1 determine the GPIOs value for OUTPUT in case bit 4 val is 0
7808          * Bits 8-9 determine the GPIOs value for INPUT in case bit 4 val is 1
7809          * where the 1st bit is the over-current(only input), and 2nd bit is
7810          * for power( only output )
7811          *
7812          * In case of NOC feature is disabled and power is up, set GPIO control
7813          *  as input to enable listening of over-current indication
7814          */
7815         if (phy->flags & ELINK_FLAGS_NOC)
7816                 return;
7817         if (is_power_up)
7818                 val = (1 << 4);
7819         else
7820                 /* Set GPIO control to OUTPUT, and set the power bit
7821                  * to according to the is_power_up
7822                  */
7823                 val = (1 << 1);
7824
7825         elink_cl45_write(sc, phy,
7826                          MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_GPIO_CTRL, val);
7827 }
7828
7829 static elink_status_t elink_8726_set_limiting_mode(struct bnx2x_softc *sc,
7830                                                    struct elink_phy *phy,
7831                                                    uint16_t edc_mode)
7832 {
7833         uint16_t cur_limiting_mode;
7834
7835         elink_cl45_read(sc, phy,
7836                         MDIO_PMA_DEVAD,
7837                         MDIO_PMA_REG_ROM_VER2, &cur_limiting_mode);
7838         PMD_DRV_LOG(DEBUG, "Current Limiting mode is 0x%x", cur_limiting_mode);
7839
7840         if (edc_mode == ELINK_EDC_MODE_LIMITING) {
7841                 PMD_DRV_LOG(DEBUG, "Setting LIMITING MODE");
7842                 elink_cl45_write(sc, phy,
7843                                  MDIO_PMA_DEVAD,
7844                                  MDIO_PMA_REG_ROM_VER2,
7845                                  ELINK_EDC_MODE_LIMITING);
7846         } else {                /* LRM mode ( default ) */
7847
7848                 PMD_DRV_LOG(DEBUG, "Setting LRM MODE");
7849
7850                 /* Changing to LRM mode takes quite few seconds. So do it only
7851                  * if current mode is limiting (default is LRM)
7852                  */
7853                 if (cur_limiting_mode != ELINK_EDC_MODE_LIMITING)
7854                         return ELINK_STATUS_OK;
7855
7856                 elink_cl45_write(sc, phy,
7857                                  MDIO_PMA_DEVAD, MDIO_PMA_REG_LRM_MODE, 0);
7858                 elink_cl45_write(sc, phy,
7859                                  MDIO_PMA_DEVAD, MDIO_PMA_REG_ROM_VER2, 0x128);
7860                 elink_cl45_write(sc, phy,
7861                                  MDIO_PMA_DEVAD,
7862                                  MDIO_PMA_REG_MISC_CTRL0, 0x4008);
7863                 elink_cl45_write(sc, phy,
7864                                  MDIO_PMA_DEVAD, MDIO_PMA_REG_LRM_MODE, 0xaaaa);
7865         }
7866         return ELINK_STATUS_OK;
7867 }
7868
7869 static elink_status_t elink_8727_set_limiting_mode(struct bnx2x_softc *sc,
7870                                                    struct elink_phy *phy,
7871                                                    uint16_t edc_mode)
7872 {
7873         uint16_t phy_identifier;
7874         uint16_t rom_ver2_val;
7875         elink_cl45_read(sc, phy,
7876                         MDIO_PMA_DEVAD,
7877                         MDIO_PMA_REG_PHY_IDENTIFIER, &phy_identifier);
7878
7879         elink_cl45_write(sc, phy,
7880                          MDIO_PMA_DEVAD,
7881                          MDIO_PMA_REG_PHY_IDENTIFIER,
7882                          (phy_identifier & ~(1 << 9)));
7883
7884         elink_cl45_read(sc, phy,
7885                         MDIO_PMA_DEVAD, MDIO_PMA_REG_ROM_VER2, &rom_ver2_val);
7886         /* Keep the MSB 8-bits, and set the LSB 8-bits with the edc_mode */
7887         elink_cl45_write(sc, phy,
7888                          MDIO_PMA_DEVAD,
7889                          MDIO_PMA_REG_ROM_VER2,
7890                          (rom_ver2_val & 0xff00) | (edc_mode & 0x00ff));
7891
7892         elink_cl45_write(sc, phy,
7893                          MDIO_PMA_DEVAD,
7894                          MDIO_PMA_REG_PHY_IDENTIFIER,
7895                          (phy_identifier | (1 << 9)));
7896
7897         return ELINK_STATUS_OK;
7898 }
7899
7900 static void elink_8727_specific_func(struct elink_phy *phy,
7901                                      struct elink_params *params,
7902                                      uint32_t action)
7903 {
7904         struct bnx2x_softc *sc = params->sc;
7905         uint16_t val;
7906         switch (action) {
7907         case ELINK_DISABLE_TX:
7908                 elink_sfp_set_transmitter(params, phy, 0);
7909                 break;
7910         case ELINK_ENABLE_TX:
7911                 if (!(phy->flags & ELINK_FLAGS_SFP_NOT_APPROVED))
7912                         elink_sfp_set_transmitter(params, phy, 1);
7913                 break;
7914         case ELINK_PHY_INIT:
7915                 elink_cl45_write(sc, phy,
7916                                  MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXCTRL,
7917                                  (1 << 2) | (1 << 5));
7918                 elink_cl45_write(sc, phy,
7919                                  MDIO_PMA_DEVAD, MDIO_PMA_LASI_TXCTRL, 0);
7920                 elink_cl45_write(sc, phy,
7921                                  MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, 0x0006);
7922                 /* Make MOD_ABS give interrupt on change */
7923                 elink_cl45_read(sc, phy, MDIO_PMA_DEVAD,
7924                                 MDIO_PMA_REG_8727_PCS_OPT_CTRL, &val);
7925                 val |= (1 << 12);
7926                 if (phy->flags & ELINK_FLAGS_NOC)
7927                         val |= (3 << 5);
7928                 /* Set 8727 GPIOs to input to allow reading from the 8727 GPIO0
7929                  * status which reflect SFP+ module over-current
7930                  */
7931                 if (!(phy->flags & ELINK_FLAGS_NOC))
7932                         val &= 0xff8f;  /* Reset bits 4-6 */
7933                 elink_cl45_write(sc, phy,
7934                                  MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_PCS_OPT_CTRL,
7935                                  val);
7936                 break;
7937         default:
7938                 PMD_DRV_LOG(DEBUG, "Function 0x%x not supported by 8727",
7939                             action);
7940                 return;
7941         }
7942 }
7943
7944 static void elink_set_e1e2_module_fault_led(struct elink_params *params,
7945                                             uint8_t gpio_mode)
7946 {
7947         struct bnx2x_softc *sc = params->sc;
7948
7949         uint32_t fault_led_gpio = REG_RD(sc, params->shmem_base +
7950                                          offsetof(struct shmem_region,
7951                                                   dev_info.
7952                                                   port_hw_config[params->port].
7953                                                   sfp_ctrl)) &
7954             PORT_HW_CFG_FAULT_MODULE_LED_MASK;
7955         switch (fault_led_gpio) {
7956         case PORT_HW_CFG_FAULT_MODULE_LED_DISABLED:
7957                 return;
7958         case PORT_HW_CFG_FAULT_MODULE_LED_GPIO0:
7959         case PORT_HW_CFG_FAULT_MODULE_LED_GPIO1:
7960         case PORT_HW_CFG_FAULT_MODULE_LED_GPIO2:
7961         case PORT_HW_CFG_FAULT_MODULE_LED_GPIO3:
7962                 {
7963                         uint8_t gpio_port = elink_get_gpio_port(params);
7964                         uint16_t gpio_pin = fault_led_gpio -
7965                             PORT_HW_CFG_FAULT_MODULE_LED_GPIO0;
7966                         PMD_DRV_LOG(DEBUG, "Set fault module-detected led "
7967                                     "pin %x port %x mode %x",
7968                                     gpio_pin, gpio_port, gpio_mode);
7969                         elink_cb_gpio_write(sc, gpio_pin, gpio_mode, gpio_port);
7970                 }
7971                 break;
7972         default:
7973                 PMD_DRV_LOG(DEBUG, "Error: Invalid fault led mode 0x%x",
7974                             fault_led_gpio);
7975         }
7976 }
7977
7978 static void elink_set_e3_module_fault_led(struct elink_params *params,
7979                                           uint8_t gpio_mode)
7980 {
7981         uint32_t pin_cfg;
7982         uint8_t port = params->port;
7983         struct bnx2x_softc *sc = params->sc;
7984         pin_cfg = (REG_RD(sc, params->shmem_base +
7985                           offsetof(struct shmem_region,
7986                                    dev_info.port_hw_config[port].e3_sfp_ctrl)) &
7987                    PORT_HW_CFG_E3_FAULT_MDL_LED_MASK) >>
7988             PORT_HW_CFG_E3_FAULT_MDL_LED_SHIFT;
7989         PMD_DRV_LOG(DEBUG, "Setting Fault LED to %d using pin cfg %d",
7990                     gpio_mode, pin_cfg);
7991         elink_set_cfg_pin(sc, pin_cfg, gpio_mode);
7992 }
7993
7994 static void elink_set_sfp_module_fault_led(struct elink_params *params,
7995                                            uint8_t gpio_mode)
7996 {
7997         struct bnx2x_softc *sc = params->sc;
7998         PMD_DRV_LOG(DEBUG, "Setting SFP+ module fault LED to %d", gpio_mode);
7999         if (CHIP_IS_E3(sc)) {
8000                 /* Low ==> if SFP+ module is supported otherwise
8001                  * High ==> if SFP+ module is not on the approved vendor list
8002                  */
8003                 elink_set_e3_module_fault_led(params, gpio_mode);
8004         } else
8005                 elink_set_e1e2_module_fault_led(params, gpio_mode);
8006 }
8007
8008 static void elink_warpcore_hw_reset(__rte_unused struct elink_phy *phy,
8009                                     struct elink_params *params)
8010 {
8011         struct bnx2x_softc *sc = params->sc;
8012         elink_warpcore_power_module(params, 0);
8013         /* Put Warpcore in low power mode */
8014         REG_WR(sc, MISC_REG_WC0_RESET, 0x0c0e);
8015
8016         /* Put LCPLL in low power mode */
8017         REG_WR(sc, MISC_REG_LCPLL_E40_PWRDWN, 1);
8018         REG_WR(sc, MISC_REG_LCPLL_E40_RESETB_ANA, 0);
8019         REG_WR(sc, MISC_REG_LCPLL_E40_RESETB_DIG, 0);
8020 }
8021
8022 static void elink_power_sfp_module(struct elink_params *params,
8023                                    struct elink_phy *phy, uint8_t power)
8024 {
8025         PMD_DRV_LOG(DEBUG, "Setting SFP+ power to %x", power);
8026
8027         switch (phy->type) {
8028         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X8727:
8029         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X8722:
8030                 elink_8727_power_module(params->sc, phy, power);
8031                 break;
8032         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT:
8033                 elink_warpcore_power_module(params, power);
8034                 break;
8035         default:
8036                 break;
8037         }
8038 }
8039
8040 static void elink_warpcore_set_limiting_mode(struct elink_params *params,
8041                                              struct elink_phy *phy,
8042                                              uint16_t edc_mode)
8043 {
8044         uint16_t val = 0;
8045         uint16_t mode = MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE_DEFAULT;
8046         struct bnx2x_softc *sc = params->sc;
8047
8048         uint8_t lane = elink_get_warpcore_lane(params);
8049         /* This is a global register which controls all lanes */
8050         elink_cl45_read(sc, phy, MDIO_WC_DEVAD,
8051                         MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE, &val);
8052         val &= ~(0xf << (lane << 2));
8053
8054         switch (edc_mode) {
8055         case ELINK_EDC_MODE_LINEAR:
8056         case ELINK_EDC_MODE_LIMITING:
8057                 mode = MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE_DEFAULT;
8058                 break;
8059         case ELINK_EDC_MODE_PASSIVE_DAC:
8060         case ELINK_EDC_MODE_ACTIVE_DAC:
8061                 mode = MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE_SFP_DAC;
8062                 break;
8063         default:
8064                 break;
8065         }
8066
8067         val |= (mode << (lane << 2));
8068         elink_cl45_write(sc, phy, MDIO_WC_DEVAD,
8069                          MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE, val);
8070         /* A must read */
8071         elink_cl45_read(sc, phy, MDIO_WC_DEVAD,
8072                         MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE, &val);
8073
8074         /* Restart microcode to re-read the new mode */
8075         elink_warpcore_reset_lane(sc, phy, 1);
8076         elink_warpcore_reset_lane(sc, phy, 0);
8077
8078 }
8079
8080 static void elink_set_limiting_mode(struct elink_params *params,
8081                                     struct elink_phy *phy, uint16_t edc_mode)
8082 {
8083         switch (phy->type) {
8084         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X8726:
8085                 elink_8726_set_limiting_mode(params->sc, phy, edc_mode);
8086                 break;
8087         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X8727:
8088         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X8722:
8089                 elink_8727_set_limiting_mode(params->sc, phy, edc_mode);
8090                 break;
8091         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT:
8092                 elink_warpcore_set_limiting_mode(params, phy, edc_mode);
8093                 break;
8094         }
8095 }
8096
8097 static elink_status_t elink_sfp_module_detection(struct elink_phy *phy,
8098                                                  struct elink_params *params)
8099 {
8100         struct bnx2x_softc *sc = params->sc;
8101         uint16_t edc_mode;
8102         elink_status_t rc = ELINK_STATUS_OK;
8103
8104         uint32_t val = REG_RD(sc, params->shmem_base +
8105                               offsetof(struct shmem_region,
8106                                        dev_info.port_feature_config[params->
8107                                                                     port].
8108                                        config));
8109         /* Enabled transmitter by default */
8110         elink_sfp_set_transmitter(params, phy, 1);
8111         PMD_DRV_LOG(DEBUG, "SFP+ module plugged in/out detected on port %d",
8112                     params->port);
8113         /* Power up module */
8114         elink_power_sfp_module(params, phy, 1);
8115         if (elink_get_edc_mode(phy, params, &edc_mode) != 0) {
8116                 PMD_DRV_LOG(DEBUG, "Failed to get valid module type");
8117                 return ELINK_STATUS_ERROR;
8118         } else if (elink_verify_sfp_module(phy, params) != 0) {
8119                 /* Check SFP+ module compatibility */
8120                 PMD_DRV_LOG(DEBUG, "Module verification failed!!");
8121                 rc = ELINK_STATUS_ERROR;
8122                 /* Turn on fault module-detected led */
8123                 elink_set_sfp_module_fault_led(params,
8124                                                MISC_REGISTERS_GPIO_HIGH);
8125
8126                 /* Check if need to power down the SFP+ module */
8127                 if ((val & PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK) ==
8128                     PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_POWER_DOWN) {
8129                         PMD_DRV_LOG(DEBUG, "Shutdown SFP+ module!!");
8130                         elink_power_sfp_module(params, phy, 0);
8131                         return rc;
8132                 }
8133         } else {
8134                 /* Turn off fault module-detected led */
8135                 elink_set_sfp_module_fault_led(params, MISC_REGISTERS_GPIO_LOW);
8136         }
8137
8138         /* Check and set limiting mode / LRM mode on 8726. On 8727 it
8139          * is done automatically
8140          */
8141         elink_set_limiting_mode(params, phy, edc_mode);
8142
8143         /* Disable transmit for this module if the module is not approved, and
8144          * laser needs to be disabled.
8145          */
8146         if ((rc != 0) &&
8147             ((val & PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK) ==
8148              PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_DISABLE_TX_LASER))
8149                 elink_sfp_set_transmitter(params, phy, 0);
8150
8151         return rc;
8152 }
8153
8154 void elink_handle_module_detect_int(struct elink_params *params)
8155 {
8156         struct bnx2x_softc *sc = params->sc;
8157         struct elink_phy *phy;
8158         uint32_t gpio_val;
8159         uint8_t gpio_num, gpio_port;
8160         if (CHIP_IS_E3(sc)) {
8161                 phy = &params->phy[ELINK_INT_PHY];
8162                 /* Always enable TX laser,will be disabled in case of fault */
8163                 elink_sfp_set_transmitter(params, phy, 1);
8164         } else {
8165                 phy = &params->phy[ELINK_EXT_PHY1];
8166         }
8167         if (elink_get_mod_abs_int_cfg(sc, params->shmem_base,
8168                                       params->port, &gpio_num, &gpio_port) ==
8169             ELINK_STATUS_ERROR) {
8170                 PMD_DRV_LOG(DEBUG, "Failed to get MOD_ABS interrupt config");
8171                 return;
8172         }
8173
8174         /* Set valid module led off */
8175         elink_set_sfp_module_fault_led(params, MISC_REGISTERS_GPIO_HIGH);
8176
8177         /* Get current gpio val reflecting module plugged in / out */
8178         gpio_val = elink_cb_gpio_read(sc, gpio_num, gpio_port);
8179
8180         /* Call the handling function in case module is detected */
8181         if (gpio_val == 0) {
8182                 elink_set_mdio_emac_per_phy(sc, params);
8183                 elink_set_aer_mmd(params, phy);
8184
8185                 elink_power_sfp_module(params, phy, 1);
8186                 elink_cb_gpio_int_write(sc, gpio_num,
8187                                         MISC_REGISTERS_GPIO_INT_OUTPUT_CLR,
8188                                         gpio_port);
8189                 if (elink_wait_for_sfp_module_initialized(phy, params) == 0) {
8190                         elink_sfp_module_detection(phy, params);
8191                         if (CHIP_IS_E3(sc)) {
8192                                 uint16_t rx_tx_in_reset;
8193                                 /* In case WC is out of reset, reconfigure the
8194                                  * link speed while taking into account 1G
8195                                  * module limitation.
8196                                  */
8197                                 elink_cl45_read(sc, phy,
8198                                                 MDIO_WC_DEVAD,
8199                                                 MDIO_WC_REG_DIGITAL5_MISC6,
8200                                                 &rx_tx_in_reset);
8201                                 if ((!rx_tx_in_reset) &&
8202                                     (params->link_flags &
8203                                      ELINK_PHY_INITIALIZED)) {
8204                                         elink_warpcore_reset_lane(sc, phy, 1);
8205                                         elink_warpcore_config_sfi(phy, params);
8206                                         elink_warpcore_reset_lane(sc, phy, 0);
8207                                 }
8208                         }
8209                 } else {
8210                         PMD_DRV_LOG(DEBUG, "SFP+ module is not initialized");
8211                 }
8212         } else {
8213                 elink_cb_gpio_int_write(sc, gpio_num,
8214                                         MISC_REGISTERS_GPIO_INT_OUTPUT_SET,
8215                                         gpio_port);
8216                 /* Module was plugged out.
8217                  * Disable transmit for this module
8218                  */
8219                 phy->media_type = ELINK_ETH_PHY_NOT_PRESENT;
8220         }
8221 }
8222
8223 /******************************************************************/
8224 /*              Used by 8706 and 8727                             */
8225 /******************************************************************/
8226 static void elink_sfp_mask_fault(struct bnx2x_softc *sc,
8227                                  struct elink_phy *phy,
8228                                  uint16_t alarm_status_offset,
8229                                  uint16_t alarm_ctrl_offset)
8230 {
8231         uint16_t alarm_status, val;
8232         elink_cl45_read(sc, phy,
8233                         MDIO_PMA_DEVAD, alarm_status_offset, &alarm_status);
8234         elink_cl45_read(sc, phy,
8235                         MDIO_PMA_DEVAD, alarm_status_offset, &alarm_status);
8236         /* Mask or enable the fault event. */
8237         elink_cl45_read(sc, phy, MDIO_PMA_DEVAD, alarm_ctrl_offset, &val);
8238         if (alarm_status & (1 << 0))
8239                 val &= ~(1 << 0);
8240         else
8241                 val |= (1 << 0);
8242         elink_cl45_write(sc, phy, MDIO_PMA_DEVAD, alarm_ctrl_offset, val);
8243 }
8244
8245 /******************************************************************/
8246 /*              common BNX2X8706/BNX2X8726 PHY SECTION            */
8247 /******************************************************************/
8248 static uint8_t elink_8706_8726_read_status(struct elink_phy *phy,
8249                                            struct elink_params *params,
8250                                            struct elink_vars *vars)
8251 {
8252         uint8_t link_up = 0;
8253         uint16_t val1, val2, rx_sd, pcs_status;
8254         struct bnx2x_softc *sc = params->sc;
8255         PMD_DRV_LOG(DEBUG, "XGXS 8706/8726");
8256         /* Clear RX Alarm */
8257         elink_cl45_read(sc, phy, MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXSTAT, &val2);
8258
8259         elink_sfp_mask_fault(sc, phy, MDIO_PMA_LASI_TXSTAT,
8260                              MDIO_PMA_LASI_TXCTRL);
8261
8262         /* Clear LASI indication */
8263         elink_cl45_read(sc, phy, MDIO_PMA_DEVAD, MDIO_PMA_LASI_STAT, &val1);
8264         elink_cl45_read(sc, phy, MDIO_PMA_DEVAD, MDIO_PMA_LASI_STAT, &val2);
8265         PMD_DRV_LOG(DEBUG, "8706/8726 LASI status 0x%x--> 0x%x", val1, val2);
8266
8267         elink_cl45_read(sc, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_RX_SD, &rx_sd);
8268         elink_cl45_read(sc, phy,
8269                         MDIO_PCS_DEVAD, MDIO_PCS_REG_STATUS, &pcs_status);
8270         elink_cl45_read(sc, phy, MDIO_AN_DEVAD, MDIO_AN_REG_LINK_STATUS, &val2);
8271         elink_cl45_read(sc, phy, MDIO_AN_DEVAD, MDIO_AN_REG_LINK_STATUS, &val2);
8272
8273         PMD_DRV_LOG(DEBUG, "8706/8726 rx_sd 0x%x pcs_status 0x%x 1Gbps"
8274                     " link_status 0x%x", rx_sd, pcs_status, val2);
8275         /* Link is up if both bit 0 of pmd_rx_sd and bit 0 of pcs_status
8276          * are set, or if the autoneg bit 1 is set
8277          */
8278         link_up = ((rx_sd & pcs_status & 0x1) || (val2 & (1 << 1)));
8279         if (link_up) {
8280                 if (val2 & (1 << 1))
8281                         vars->line_speed = ELINK_SPEED_1000;
8282                 else
8283                         vars->line_speed = ELINK_SPEED_10000;
8284                 elink_ext_phy_resolve_fc(phy, params, vars);
8285                 vars->duplex = DUPLEX_FULL;
8286         }
8287
8288         /* Capture 10G link fault. Read twice to clear stale value. */
8289         if (vars->line_speed == ELINK_SPEED_10000) {
8290                 elink_cl45_read(sc, phy, MDIO_PMA_DEVAD,
8291                                 MDIO_PMA_LASI_TXSTAT, &val1);
8292                 elink_cl45_read(sc, phy, MDIO_PMA_DEVAD,
8293                                 MDIO_PMA_LASI_TXSTAT, &val1);
8294                 if (val1 & (1 << 0))
8295                         vars->fault_detected = 1;
8296         }
8297
8298         return link_up;
8299 }
8300
8301 /******************************************************************/
8302 /*                      BNX2X8706 PHY SECTION                     */
8303 /******************************************************************/
8304 static uint8_t elink_8706_config_init(struct elink_phy *phy,
8305                                       struct elink_params *params,
8306                                       __rte_unused struct elink_vars *vars)
8307 {
8308         uint32_t tx_en_mode;
8309         uint16_t cnt, val, tmp1;
8310         struct bnx2x_softc *sc = params->sc;
8311
8312         elink_cb_gpio_write(sc, MISC_REGISTERS_GPIO_2,
8313                             MISC_REGISTERS_GPIO_OUTPUT_HIGH, params->port);
8314         /* HW reset */
8315         elink_ext_phy_hw_reset(sc, params->port);
8316         elink_cl45_write(sc, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0xa040);
8317         elink_wait_reset_complete(sc, phy, params);
8318
8319         /* Wait until fw is loaded */
8320         for (cnt = 0; cnt < 100; cnt++) {
8321                 elink_cl45_read(sc, phy,
8322                                 MDIO_PMA_DEVAD, MDIO_PMA_REG_ROM_VER1, &val);
8323                 if (val)
8324                         break;
8325                 DELAY(1000 * 10);
8326         }
8327         PMD_DRV_LOG(DEBUG, "XGXS 8706 is initialized after %d ms", cnt);
8328         if ((params->feature_config_flags &
8329              ELINK_FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED)) {
8330                 uint8_t i;
8331                 uint16_t reg;
8332                 for (i = 0; i < 4; i++) {
8333                         reg = MDIO_XS_8706_REG_BANK_RX0 +
8334                             i * (MDIO_XS_8706_REG_BANK_RX1 -
8335                                  MDIO_XS_8706_REG_BANK_RX0);
8336                         elink_cl45_read(sc, phy, MDIO_XS_DEVAD, reg, &val);
8337                         /* Clear first 3 bits of the control */
8338                         val &= ~0x7;
8339                         /* Set control bits according to configuration */
8340                         val |= (phy->rx_preemphasis[i] & 0x7);
8341                         PMD_DRV_LOG(DEBUG, "Setting RX Equalizer to BNX2X8706"
8342                                     " reg 0x%x <-- val 0x%x", reg, val);
8343                         elink_cl45_write(sc, phy, MDIO_XS_DEVAD, reg, val);
8344                 }
8345         }
8346         /* Force speed */
8347         if (phy->req_line_speed == ELINK_SPEED_10000) {
8348                 PMD_DRV_LOG(DEBUG, "XGXS 8706 force 10Gbps");
8349
8350                 elink_cl45_write(sc, phy,
8351                                  MDIO_PMA_DEVAD,
8352                                  MDIO_PMA_REG_DIGITAL_CTRL, 0x400);
8353                 elink_cl45_write(sc, phy,
8354                                  MDIO_PMA_DEVAD, MDIO_PMA_LASI_TXCTRL, 0);
8355                 /* Arm LASI for link and Tx fault. */
8356                 elink_cl45_write(sc, phy,
8357                                  MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, 3);
8358         } else {
8359                 /* Force 1Gbps using autoneg with 1G advertisement */
8360
8361                 /* Allow CL37 through CL73 */
8362                 PMD_DRV_LOG(DEBUG, "XGXS 8706 AutoNeg");
8363                 elink_cl45_write(sc, phy,
8364                                  MDIO_AN_DEVAD, MDIO_AN_REG_CL37_CL73, 0x040c);
8365
8366                 /* Enable Full-Duplex advertisement on CL37 */
8367                 elink_cl45_write(sc, phy,
8368                                  MDIO_AN_DEVAD, MDIO_AN_REG_CL37_FC_LP, 0x0020);
8369                 /* Enable CL37 AN */
8370                 elink_cl45_write(sc, phy,
8371                                  MDIO_AN_DEVAD, MDIO_AN_REG_CL37_AN, 0x1000);
8372                 /* 1G support */
8373                 elink_cl45_write(sc, phy,
8374                                  MDIO_AN_DEVAD, MDIO_AN_REG_ADV, (1 << 5));
8375
8376                 /* Enable clause 73 AN */
8377                 elink_cl45_write(sc, phy,
8378                                  MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0x1200);
8379                 elink_cl45_write(sc, phy,
8380                                  MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXCTRL, 0x0400);
8381                 elink_cl45_write(sc, phy,
8382                                  MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, 0x0004);
8383         }
8384         elink_save_bnx2x_spirom_ver(sc, phy, params->port);
8385
8386         /* If TX Laser is controlled by GPIO_0, do not let PHY go into low
8387          * power mode, if TX Laser is disabled
8388          */
8389
8390         tx_en_mode = REG_RD(sc, params->shmem_base +
8391                             offsetof(struct shmem_region,
8392                                      dev_info.port_hw_config[params->port].
8393                                      sfp_ctrl))
8394         & PORT_HW_CFG_TX_LASER_MASK;
8395
8396         if (tx_en_mode == PORT_HW_CFG_TX_LASER_GPIO0) {
8397                 PMD_DRV_LOG(DEBUG, "Enabling TXONOFF_PWRDN_DIS");
8398                 elink_cl45_read(sc, phy,
8399                                 MDIO_PMA_DEVAD, MDIO_PMA_REG_DIGITAL_CTRL,
8400                                 &tmp1);
8401                 tmp1 |= 0x1;
8402                 elink_cl45_write(sc, phy,
8403                                  MDIO_PMA_DEVAD, MDIO_PMA_REG_DIGITAL_CTRL,
8404                                  tmp1);
8405         }
8406
8407         return ELINK_STATUS_OK;
8408 }
8409
8410 static uint8_t elink_8706_read_status(struct elink_phy *phy,
8411                                       struct elink_params *params,
8412                                       struct elink_vars *vars)
8413 {
8414         return elink_8706_8726_read_status(phy, params, vars);
8415 }
8416
8417 /******************************************************************/
8418 /*                      BNX2X8726 PHY SECTION                     */
8419 /******************************************************************/
8420 static void elink_8726_config_loopback(struct elink_phy *phy,
8421                                        struct elink_params *params)
8422 {
8423         struct bnx2x_softc *sc = params->sc;
8424         PMD_DRV_LOG(DEBUG, "PMA/PMD ext_phy_loopback: 8726");
8425         elink_cl45_write(sc, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x0001);
8426 }
8427
8428 static void elink_8726_external_rom_boot(struct elink_phy *phy,
8429                                          struct elink_params *params)
8430 {
8431         struct bnx2x_softc *sc = params->sc;
8432         /* Need to wait 100ms after reset */
8433         DELAY(1000 * 100);
8434
8435         /* Micro controller re-boot */
8436         elink_cl45_write(sc, phy,
8437                          MDIO_PMA_DEVAD, MDIO_PMA_REG_GEN_CTRL, 0x018B);
8438
8439         /* Set soft reset */
8440         elink_cl45_write(sc, phy,
8441                          MDIO_PMA_DEVAD,
8442                          MDIO_PMA_REG_GEN_CTRL,
8443                          MDIO_PMA_REG_GEN_CTRL_ROM_MICRO_RESET);
8444
8445         elink_cl45_write(sc, phy,
8446                          MDIO_PMA_DEVAD, MDIO_PMA_REG_MISC_CTRL1, 0x0001);
8447
8448         elink_cl45_write(sc, phy,
8449                          MDIO_PMA_DEVAD,
8450                          MDIO_PMA_REG_GEN_CTRL,
8451                          MDIO_PMA_REG_GEN_CTRL_ROM_RESET_INTERNAL_MP);
8452
8453         /* Wait for 150ms for microcode load */
8454         DELAY(1000 * 150);
8455
8456         /* Disable serial boot control, tristates pins SS_N, SCK, MOSI, MISO */
8457         elink_cl45_write(sc, phy,
8458                          MDIO_PMA_DEVAD, MDIO_PMA_REG_MISC_CTRL1, 0x0000);
8459
8460         DELAY(1000 * 200);
8461         elink_save_bnx2x_spirom_ver(sc, phy, params->port);
8462 }
8463
8464 static uint8_t elink_8726_read_status(struct elink_phy *phy,
8465                                       struct elink_params *params,
8466                                       struct elink_vars *vars)
8467 {
8468         struct bnx2x_softc *sc = params->sc;
8469         uint16_t val1;
8470         uint8_t link_up = elink_8706_8726_read_status(phy, params, vars);
8471         if (link_up) {
8472                 elink_cl45_read(sc, phy,
8473                                 MDIO_PMA_DEVAD, MDIO_PMA_REG_PHY_IDENTIFIER,
8474                                 &val1);
8475                 if (val1 & (1 << 15)) {
8476                         PMD_DRV_LOG(DEBUG, "Tx is disabled");
8477                         link_up = 0;
8478                         vars->line_speed = 0;
8479                 }
8480         }
8481         return link_up;
8482 }
8483
8484 static uint8_t elink_8726_config_init(struct elink_phy *phy,
8485                                       struct elink_params *params,
8486                                       struct elink_vars *vars)
8487 {
8488         struct bnx2x_softc *sc = params->sc;
8489         PMD_DRV_LOG(DEBUG, "Initializing BNX2X8726");
8490
8491         elink_cl45_write(sc, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 1 << 15);
8492         elink_wait_reset_complete(sc, phy, params);
8493
8494         elink_8726_external_rom_boot(phy, params);
8495
8496         /* Need to call module detected on initialization since the module
8497          * detection triggered by actual module insertion might occur before
8498          * driver is loaded, and when driver is loaded, it reset all
8499          * registers, including the transmitter
8500          */
8501         elink_sfp_module_detection(phy, params);
8502
8503         if (phy->req_line_speed == ELINK_SPEED_1000) {
8504                 PMD_DRV_LOG(DEBUG, "Setting 1G force");
8505                 elink_cl45_write(sc, phy,
8506                                  MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x40);
8507                 elink_cl45_write(sc, phy,
8508                                  MDIO_PMA_DEVAD, MDIO_PMA_REG_10G_CTRL2, 0xD);
8509                 elink_cl45_write(sc, phy,
8510                                  MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, 0x5);
8511                 elink_cl45_write(sc, phy,
8512                                  MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXCTRL, 0x400);
8513         } else if ((phy->req_line_speed == ELINK_SPEED_AUTO_NEG) &&
8514                    (phy->speed_cap_mask &
8515                     PORT_HW_CFG_SPEED_CAPABILITY_D0_1G) &&
8516                    ((phy->speed_cap_mask &
8517                      PORT_HW_CFG_SPEED_CAPABILITY_D0_10G) !=
8518                     PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)) {
8519                 PMD_DRV_LOG(DEBUG, "Setting 1G clause37");
8520                 /* Set Flow control */
8521                 elink_ext_phy_set_pause(params, phy, vars);
8522                 elink_cl45_write(sc, phy, MDIO_AN_DEVAD, MDIO_AN_REG_ADV, 0x20);
8523                 elink_cl45_write(sc, phy,
8524                                  MDIO_AN_DEVAD, MDIO_AN_REG_CL37_CL73, 0x040c);
8525                 elink_cl45_write(sc, phy,
8526                                  MDIO_AN_DEVAD, MDIO_AN_REG_CL37_FC_LD, 0x0020);
8527                 elink_cl45_write(sc, phy,
8528                                  MDIO_AN_DEVAD, MDIO_AN_REG_CL37_AN, 0x1000);
8529                 elink_cl45_write(sc, phy,
8530                                  MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0x1200);
8531                 /* Enable RX-ALARM control to receive interrupt for 1G speed
8532                  * change
8533                  */
8534                 elink_cl45_write(sc, phy,
8535                                  MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, 0x4);
8536                 elink_cl45_write(sc, phy,
8537                                  MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXCTRL, 0x400);
8538
8539         } else {                /* Default 10G. Set only LASI control */
8540                 elink_cl45_write(sc, phy,
8541                                  MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, 1);
8542         }
8543
8544         /* Set TX PreEmphasis if needed */
8545         if ((params->feature_config_flags &
8546              ELINK_FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED)) {
8547                 PMD_DRV_LOG(DEBUG,
8548                             "Setting TX_CTRL1 0x%x, TX_CTRL2 0x%x",
8549                             phy->tx_preemphasis[0], phy->tx_preemphasis[1]);
8550                 elink_cl45_write(sc, phy,
8551                                  MDIO_PMA_DEVAD,
8552                                  MDIO_PMA_REG_8726_TX_CTRL1,
8553                                  phy->tx_preemphasis[0]);
8554
8555                 elink_cl45_write(sc, phy,
8556                                  MDIO_PMA_DEVAD,
8557                                  MDIO_PMA_REG_8726_TX_CTRL2,
8558                                  phy->tx_preemphasis[1]);
8559         }
8560
8561         return ELINK_STATUS_OK;
8562
8563 }
8564
8565 static void elink_8726_link_reset(struct elink_phy *phy,
8566                                   struct elink_params *params)
8567 {
8568         struct bnx2x_softc *sc = params->sc;
8569         PMD_DRV_LOG(DEBUG, "elink_8726_link_reset port %d", params->port);
8570         /* Set serial boot control for external load */
8571         elink_cl45_write(sc, phy,
8572                          MDIO_PMA_DEVAD, MDIO_PMA_REG_GEN_CTRL, 0x0001);
8573 }
8574
8575 /******************************************************************/
8576 /*                      BNX2X8727 PHY SECTION                     */
8577 /******************************************************************/
8578
8579 static void elink_8727_set_link_led(struct elink_phy *phy,
8580                                     struct elink_params *params, uint8_t mode)
8581 {
8582         struct bnx2x_softc *sc = params->sc;
8583         uint16_t led_mode_bitmask = 0;
8584         uint16_t gpio_pins_bitmask = 0;
8585         uint16_t val;
8586         /* Only NOC flavor requires to set the LED specifically */
8587         if (!(phy->flags & ELINK_FLAGS_NOC))
8588                 return;
8589         switch (mode) {
8590         case ELINK_LED_MODE_FRONT_PANEL_OFF:
8591         case ELINK_LED_MODE_OFF:
8592                 led_mode_bitmask = 0;
8593                 gpio_pins_bitmask = 0x03;
8594                 break;
8595         case ELINK_LED_MODE_ON:
8596                 led_mode_bitmask = 0;
8597                 gpio_pins_bitmask = 0x02;
8598                 break;
8599         case ELINK_LED_MODE_OPER:
8600                 led_mode_bitmask = 0x60;
8601                 gpio_pins_bitmask = 0x11;
8602                 break;
8603         }
8604         elink_cl45_read(sc, phy,
8605                         MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_PCS_OPT_CTRL, &val);
8606         val &= 0xff8f;
8607         val |= led_mode_bitmask;
8608         elink_cl45_write(sc, phy,
8609                          MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_PCS_OPT_CTRL, val);
8610         elink_cl45_read(sc, phy,
8611                         MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_GPIO_CTRL, &val);
8612         val &= 0xffe0;
8613         val |= gpio_pins_bitmask;
8614         elink_cl45_write(sc, phy,
8615                          MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_GPIO_CTRL, val);
8616 }
8617
8618 static void elink_8727_hw_reset(__rte_unused struct elink_phy *phy,
8619                                 struct elink_params *params)
8620 {
8621         uint32_t swap_val, swap_override;
8622         uint8_t port;
8623         /* The PHY reset is controlled by GPIO 1. Fake the port number
8624          * to cancel the swap done in set_gpio()
8625          */
8626         struct bnx2x_softc *sc = params->sc;
8627         swap_val = REG_RD(sc, NIG_REG_PORT_SWAP);
8628         swap_override = REG_RD(sc, NIG_REG_STRAP_OVERRIDE);
8629         port = (swap_val && swap_override) ^ 1;
8630         elink_cb_gpio_write(sc, MISC_REGISTERS_GPIO_1,
8631                             MISC_REGISTERS_GPIO_OUTPUT_LOW, port);
8632 }
8633
8634 static void elink_8727_config_speed(struct elink_phy *phy,
8635                                     struct elink_params *params)
8636 {
8637         struct bnx2x_softc *sc = params->sc;
8638         uint16_t tmp1, val;
8639         /* Set option 1G speed */
8640         if ((phy->req_line_speed == ELINK_SPEED_1000) ||
8641             (phy->media_type == ELINK_ETH_PHY_SFP_1G_FIBER)) {
8642                 PMD_DRV_LOG(DEBUG, "Setting 1G force");
8643                 elink_cl45_write(sc, phy,
8644                                  MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x40);
8645                 elink_cl45_write(sc, phy,
8646                                  MDIO_PMA_DEVAD, MDIO_PMA_REG_10G_CTRL2, 0xD);
8647                 elink_cl45_read(sc, phy,
8648                                 MDIO_PMA_DEVAD, MDIO_PMA_REG_10G_CTRL2, &tmp1);
8649                 PMD_DRV_LOG(DEBUG, "1.7 = 0x%x", tmp1);
8650                 /* Power down the XAUI until link is up in case of dual-media
8651                  * and 1G
8652                  */
8653                 if (ELINK_DUAL_MEDIA(params)) {
8654                         elink_cl45_read(sc, phy,
8655                                         MDIO_PMA_DEVAD,
8656                                         MDIO_PMA_REG_8727_PCS_GP, &val);
8657                         val |= (3 << 10);
8658                         elink_cl45_write(sc, phy,
8659                                          MDIO_PMA_DEVAD,
8660                                          MDIO_PMA_REG_8727_PCS_GP, val);
8661                 }
8662         } else if ((phy->req_line_speed == ELINK_SPEED_AUTO_NEG) &&
8663                    ((phy->speed_cap_mask &
8664                      PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)) &&
8665                    ((phy->speed_cap_mask &
8666                      PORT_HW_CFG_SPEED_CAPABILITY_D0_10G) !=
8667                     PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)) {
8668
8669                 PMD_DRV_LOG(DEBUG, "Setting 1G clause37");
8670                 elink_cl45_write(sc, phy,
8671                                  MDIO_AN_DEVAD, MDIO_AN_REG_8727_MISC_CTRL, 0);
8672                 elink_cl45_write(sc, phy,
8673                                  MDIO_AN_DEVAD, MDIO_AN_REG_CL37_AN, 0x1300);
8674         } else {
8675                 /* Since the 8727 has only single reset pin, need to set the 10G
8676                  * registers although it is default
8677                  */
8678                 elink_cl45_write(sc, phy,
8679                                  MDIO_AN_DEVAD, MDIO_AN_REG_8727_MISC_CTRL,
8680                                  0x0020);
8681                 elink_cl45_write(sc, phy,
8682                                  MDIO_AN_DEVAD, MDIO_AN_REG_CL37_AN, 0x0100);
8683                 elink_cl45_write(sc, phy,
8684                                  MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x2040);
8685                 elink_cl45_write(sc, phy,
8686                                  MDIO_PMA_DEVAD, MDIO_PMA_REG_10G_CTRL2,
8687                                  0x0008);
8688         }
8689 }
8690
8691 static uint8_t elink_8727_config_init(struct elink_phy *phy,
8692                                       struct elink_params *params,
8693                                       __rte_unused struct elink_vars
8694                                              *vars)
8695 {
8696         uint32_t tx_en_mode;
8697         uint16_t tmp1, mod_abs, tmp2;
8698         struct bnx2x_softc *sc = params->sc;
8699         /* Enable PMD link, MOD_ABS_FLT, and 1G link alarm */
8700
8701         elink_wait_reset_complete(sc, phy, params);
8702
8703         PMD_DRV_LOG(DEBUG, "Initializing BNX2X8727");
8704
8705         elink_8727_specific_func(phy, params, ELINK_PHY_INIT);
8706         /* Initially configure MOD_ABS to interrupt when module is
8707          * presence( bit 8)
8708          */
8709         elink_cl45_read(sc, phy,
8710                         MDIO_PMA_DEVAD, MDIO_PMA_REG_PHY_IDENTIFIER, &mod_abs);
8711         /* Set EDC off by setting OPTXLOS signal input to low (bit 9).
8712          * When the EDC is off it locks onto a reference clock and avoids
8713          * becoming 'lost'
8714          */
8715         mod_abs &= ~(1 << 8);
8716         if (!(phy->flags & ELINK_FLAGS_NOC))
8717                 mod_abs &= ~(1 << 9);
8718         elink_cl45_write(sc, phy,
8719                          MDIO_PMA_DEVAD, MDIO_PMA_REG_PHY_IDENTIFIER, mod_abs);
8720
8721         /* Enable/Disable PHY transmitter output */
8722         elink_set_disable_pmd_transmit(params, phy, 0);
8723
8724         elink_8727_power_module(sc, phy, 1);
8725
8726         elink_cl45_read(sc, phy,
8727                         MDIO_PMA_DEVAD, MDIO_PMA_REG_M8051_MSGOUT_REG, &tmp1);
8728
8729         elink_cl45_read(sc, phy, MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXSTAT, &tmp1);
8730
8731         elink_8727_config_speed(phy, params);
8732
8733         /* Set TX PreEmphasis if needed */
8734         if ((params->feature_config_flags &
8735              ELINK_FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED)) {
8736                 PMD_DRV_LOG(DEBUG, "Setting TX_CTRL1 0x%x, TX_CTRL2 0x%x",
8737                             phy->tx_preemphasis[0], phy->tx_preemphasis[1]);
8738                 elink_cl45_write(sc, phy,
8739                                  MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_TX_CTRL1,
8740                                  phy->tx_preemphasis[0]);
8741
8742                 elink_cl45_write(sc, phy,
8743                                  MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_TX_CTRL2,
8744                                  phy->tx_preemphasis[1]);
8745         }
8746
8747         /* If TX Laser is controlled by GPIO_0, do not let PHY go into low
8748          * power mode, if TX Laser is disabled
8749          */
8750         tx_en_mode = REG_RD(sc, params->shmem_base +
8751                             offsetof(struct shmem_region,
8752                                      dev_info.port_hw_config[params->port].
8753                                      sfp_ctrl))
8754         & PORT_HW_CFG_TX_LASER_MASK;
8755
8756         if (tx_en_mode == PORT_HW_CFG_TX_LASER_GPIO0) {
8757
8758                 PMD_DRV_LOG(DEBUG, "Enabling TXONOFF_PWRDN_DIS");
8759                 elink_cl45_read(sc, phy,
8760                                 MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_OPT_CFG_REG,
8761                                 &tmp2);
8762                 tmp2 |= 0x1000;
8763                 tmp2 &= 0xFFEF;
8764                 elink_cl45_write(sc, phy,
8765                                  MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_OPT_CFG_REG,
8766                                  tmp2);
8767                 elink_cl45_read(sc, phy, MDIO_PMA_DEVAD,
8768                                 MDIO_PMA_REG_PHY_IDENTIFIER, &tmp2);
8769                 elink_cl45_write(sc, phy, MDIO_PMA_DEVAD,
8770                                  MDIO_PMA_REG_PHY_IDENTIFIER, (tmp2 & 0x7fff));
8771         }
8772
8773         return ELINK_STATUS_OK;
8774 }
8775
8776 static void elink_8727_handle_mod_abs(struct elink_phy *phy,
8777                                       struct elink_params *params)
8778 {
8779         struct bnx2x_softc *sc = params->sc;
8780         uint16_t mod_abs, rx_alarm_status;
8781         uint32_t val = REG_RD(sc, params->shmem_base +
8782                               offsetof(struct shmem_region,
8783                                        dev_info.port_feature_config[params->
8784                                                                     port].config));
8785         elink_cl45_read(sc, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_PHY_IDENTIFIER,
8786                         &mod_abs);
8787         if (mod_abs & (1 << 8)) {
8788
8789                 /* Module is absent */
8790                 PMD_DRV_LOG(DEBUG, "MOD_ABS indication show module is absent");
8791                 phy->media_type = ELINK_ETH_PHY_NOT_PRESENT;
8792                 /* 1. Set mod_abs to detect next module
8793                  *    presence event
8794                  * 2. Set EDC off by setting OPTXLOS signal input to low
8795                  *    (bit 9).
8796                  *    When the EDC is off it locks onto a reference clock and
8797                  *    avoids becoming 'lost'.
8798                  */
8799                 mod_abs &= ~(1 << 8);
8800                 if (!(phy->flags & ELINK_FLAGS_NOC))
8801                         mod_abs &= ~(1 << 9);
8802                 elink_cl45_write(sc, phy,
8803                                  MDIO_PMA_DEVAD,
8804                                  MDIO_PMA_REG_PHY_IDENTIFIER, mod_abs);
8805
8806                 /* Clear RX alarm since it stays up as long as
8807                  * the mod_abs wasn't changed
8808                  */
8809                 elink_cl45_read(sc, phy,
8810                                 MDIO_PMA_DEVAD,
8811                                 MDIO_PMA_LASI_RXSTAT, &rx_alarm_status);
8812
8813         } else {
8814                 /* Module is present */
8815                 PMD_DRV_LOG(DEBUG, "MOD_ABS indication show module is present");
8816                 /* First disable transmitter, and if the module is ok, the
8817                  * module_detection will enable it
8818                  * 1. Set mod_abs to detect next module absent event ( bit 8)
8819                  * 2. Restore the default polarity of the OPRXLOS signal and
8820                  * this signal will then correctly indicate the presence or
8821                  * absence of the Rx signal. (bit 9)
8822                  */
8823                 mod_abs |= (1 << 8);
8824                 if (!(phy->flags & ELINK_FLAGS_NOC))
8825                         mod_abs |= (1 << 9);
8826                 elink_cl45_write(sc, phy,
8827                                  MDIO_PMA_DEVAD,
8828                                  MDIO_PMA_REG_PHY_IDENTIFIER, mod_abs);
8829
8830                 /* Clear RX alarm since it stays up as long as the mod_abs
8831                  * wasn't changed. This is need to be done before calling the
8832                  * module detection, otherwise it will clear* the link update
8833                  * alarm
8834                  */
8835                 elink_cl45_read(sc, phy,
8836                                 MDIO_PMA_DEVAD,
8837                                 MDIO_PMA_LASI_RXSTAT, &rx_alarm_status);
8838
8839                 if ((val & PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK) ==
8840                     PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_DISABLE_TX_LASER)
8841                         elink_sfp_set_transmitter(params, phy, 0);
8842
8843                 if (elink_wait_for_sfp_module_initialized(phy, params) == 0) {
8844                         elink_sfp_module_detection(phy, params);
8845                 } else {
8846                         PMD_DRV_LOG(DEBUG, "SFP+ module is not initialized");
8847                 }
8848
8849                 /* Reconfigure link speed based on module type limitations */
8850                 elink_8727_config_speed(phy, params);
8851         }
8852
8853         PMD_DRV_LOG(DEBUG, "8727 RX_ALARM_STATUS 0x%x", rx_alarm_status);
8854         /* No need to check link status in case of module plugged in/out */
8855 }
8856
8857 static uint8_t elink_8727_read_status(struct elink_phy *phy,
8858                                       struct elink_params *params,
8859                                       struct elink_vars *vars)
8860 {
8861         struct bnx2x_softc *sc = params->sc;
8862         uint8_t link_up = 0, oc_port = params->port;
8863         uint16_t link_status = 0;
8864         uint16_t rx_alarm_status, lasi_ctrl, val1;
8865
8866         /* If PHY is not initialized, do not check link status */
8867         elink_cl45_read(sc, phy,
8868                         MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, &lasi_ctrl);
8869         if (!lasi_ctrl)
8870                 return 0;
8871
8872         /* Check the LASI on Rx */
8873         elink_cl45_read(sc, phy,
8874                         MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXSTAT, &rx_alarm_status);
8875         vars->line_speed = 0;
8876         PMD_DRV_LOG(DEBUG, "8727 RX_ALARM_STATUS  0x%x", rx_alarm_status);
8877
8878         elink_sfp_mask_fault(sc, phy, MDIO_PMA_LASI_TXSTAT,
8879                              MDIO_PMA_LASI_TXCTRL);
8880
8881         elink_cl45_read(sc, phy, MDIO_PMA_DEVAD, MDIO_PMA_LASI_STAT, &val1);
8882
8883         PMD_DRV_LOG(DEBUG, "8727 LASI status 0x%x", val1);
8884
8885         /* Clear MSG-OUT */
8886         elink_cl45_read(sc, phy,
8887                         MDIO_PMA_DEVAD, MDIO_PMA_REG_M8051_MSGOUT_REG, &val1);
8888
8889         /* If a module is present and there is need to check
8890          * for over current
8891          */
8892         if (!(phy->flags & ELINK_FLAGS_NOC) && !(rx_alarm_status & (1 << 5))) {
8893                 /* Check over-current using 8727 GPIO0 input */
8894                 elink_cl45_read(sc, phy,
8895                                 MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_GPIO_CTRL,
8896                                 &val1);
8897
8898                 if ((val1 & (1 << 8)) == 0) {
8899                         if (!CHIP_IS_E1x(sc))
8900                                 oc_port = SC_PATH(sc) + (params->port << 1);
8901                         PMD_DRV_LOG(DEBUG,
8902                                     "8727 Power fault has been detected on port %d",
8903                                     oc_port);
8904                         elink_cb_event_log(sc, ELINK_LOG_ID_OVER_CURRENT, oc_port);     //"Error: Power fault on Port %d has "
8905                         //  "been detected and the power to "
8906                         //  "that SFP+ module has been removed "
8907                         //  "to prevent failure of the card. "
8908                         //  "Please remove the SFP+ module and "
8909                         //  "restart the system to clear this "
8910                         //  "error.",
8911                         /* Disable all RX_ALARMs except for mod_abs */
8912                         elink_cl45_write(sc, phy,
8913                                          MDIO_PMA_DEVAD,
8914                                          MDIO_PMA_LASI_RXCTRL, (1 << 5));
8915
8916                         elink_cl45_read(sc, phy,
8917                                         MDIO_PMA_DEVAD,
8918                                         MDIO_PMA_REG_PHY_IDENTIFIER, &val1);
8919                         /* Wait for module_absent_event */
8920                         val1 |= (1 << 8);
8921                         elink_cl45_write(sc, phy,
8922                                          MDIO_PMA_DEVAD,
8923                                          MDIO_PMA_REG_PHY_IDENTIFIER, val1);
8924                         /* Clear RX alarm */
8925                         elink_cl45_read(sc, phy,
8926                                         MDIO_PMA_DEVAD,
8927                                         MDIO_PMA_LASI_RXSTAT, &rx_alarm_status);
8928                         elink_8727_power_module(params->sc, phy, 0);
8929                         return 0;
8930                 }
8931         }
8932
8933         /* Over current check */
8934         /* When module absent bit is set, check module */
8935         if (rx_alarm_status & (1 << 5)) {
8936                 elink_8727_handle_mod_abs(phy, params);
8937                 /* Enable all mod_abs and link detection bits */
8938                 elink_cl45_write(sc, phy,
8939                                  MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXCTRL,
8940                                  ((1 << 5) | (1 << 2)));
8941         }
8942
8943         if (!(phy->flags & ELINK_FLAGS_SFP_NOT_APPROVED)) {
8944                 PMD_DRV_LOG(DEBUG, "Enabling 8727 TX laser");
8945                 elink_sfp_set_transmitter(params, phy, 1);
8946         } else {
8947                 PMD_DRV_LOG(DEBUG, "Tx is disabled");
8948                 return 0;
8949         }
8950
8951         elink_cl45_read(sc, phy,
8952                         MDIO_PMA_DEVAD,
8953                         MDIO_PMA_REG_8073_SPEED_LINK_STATUS, &link_status);
8954
8955         /* Bits 0..2 --> speed detected,
8956          * Bits 13..15--> link is down
8957          */
8958         if ((link_status & (1 << 2)) && (!(link_status & (1 << 15)))) {
8959                 link_up = 1;
8960                 vars->line_speed = ELINK_SPEED_10000;
8961                 PMD_DRV_LOG(DEBUG, "port %x: External link up in 10G",
8962                             params->port);
8963         } else if ((link_status & (1 << 0)) && (!(link_status & (1 << 13)))) {
8964                 link_up = 1;
8965                 vars->line_speed = ELINK_SPEED_1000;
8966                 PMD_DRV_LOG(DEBUG, "port %x: External link up in 1G",
8967                             params->port);
8968         } else {
8969                 link_up = 0;
8970                 PMD_DRV_LOG(DEBUG, "port %x: External link is down",
8971                             params->port);
8972         }
8973
8974         /* Capture 10G link fault. */
8975         if (vars->line_speed == ELINK_SPEED_10000) {
8976                 elink_cl45_read(sc, phy, MDIO_PMA_DEVAD,
8977                                 MDIO_PMA_LASI_TXSTAT, &val1);
8978
8979                 elink_cl45_read(sc, phy, MDIO_PMA_DEVAD,
8980                                 MDIO_PMA_LASI_TXSTAT, &val1);
8981
8982                 if (val1 & (1 << 0)) {
8983                         vars->fault_detected = 1;
8984                 }
8985         }
8986
8987         if (link_up) {
8988                 elink_ext_phy_resolve_fc(phy, params, vars);
8989                 vars->duplex = DUPLEX_FULL;
8990                 PMD_DRV_LOG(DEBUG, "duplex = 0x%x", vars->duplex);
8991         }
8992
8993         if ((ELINK_DUAL_MEDIA(params)) &&
8994             (phy->req_line_speed == ELINK_SPEED_1000)) {
8995                 elink_cl45_read(sc, phy,
8996                                 MDIO_PMA_DEVAD,
8997                                 MDIO_PMA_REG_8727_PCS_GP, &val1);
8998                 /* In case of dual-media board and 1G, power up the XAUI side,
8999                  * otherwise power it down. For 10G it is done automatically
9000                  */
9001                 if (link_up)
9002                         val1 &= ~(3 << 10);
9003                 else
9004                         val1 |= (3 << 10);
9005                 elink_cl45_write(sc, phy,
9006                                  MDIO_PMA_DEVAD,
9007                                  MDIO_PMA_REG_8727_PCS_GP, val1);
9008         }
9009         return link_up;
9010 }
9011
9012 static void elink_8727_link_reset(struct elink_phy *phy,
9013                                   struct elink_params *params)
9014 {
9015         struct bnx2x_softc *sc = params->sc;
9016
9017         /* Enable/Disable PHY transmitter output */
9018         elink_set_disable_pmd_transmit(params, phy, 1);
9019
9020         /* Disable Transmitter */
9021         elink_sfp_set_transmitter(params, phy, 0);
9022         /* Clear LASI */
9023         elink_cl45_write(sc, phy, MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, 0);
9024
9025 }
9026
9027 /******************************************************************/
9028 /*              BNX2X8481/BNX2X84823/BNX2X84833 PHY SECTION               */
9029 /******************************************************************/
9030 static void elink_save_848xx_spirom_version(struct elink_phy *phy,
9031                                             struct bnx2x_softc *sc, uint8_t port)
9032 {
9033         uint16_t val, fw_ver2, cnt, i;
9034         static struct elink_reg_set reg_set[] = {
9035                 {MDIO_PMA_DEVAD, 0xA819, 0x0014},
9036                 {MDIO_PMA_DEVAD, 0xA81A, 0xc200},
9037                 {MDIO_PMA_DEVAD, 0xA81B, 0x0000},
9038                 {MDIO_PMA_DEVAD, 0xA81C, 0x0300},
9039                 {MDIO_PMA_DEVAD, 0xA817, 0x0009}
9040         };
9041         uint16_t fw_ver1;
9042
9043         if ((phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X84833) ||
9044             (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X84834)) {
9045                 elink_cl45_read(sc, phy, MDIO_CTL_DEVAD, 0x400f, &fw_ver1);
9046                 elink_save_spirom_version(sc, port, fw_ver1 & 0xfff,
9047                                           phy->ver_addr);
9048         } else {
9049                 /* For 32-bit registers in 848xx, access via MDIO2ARM i/f. */
9050                 /* (1) set reg 0xc200_0014(SPI_BRIDGE_CTRL_2) to 0x03000000 */
9051                 for (i = 0; i < ARRAY_SIZE(reg_set); i++)
9052                         elink_cl45_write(sc, phy, reg_set[i].devad,
9053                                          reg_set[i].reg, reg_set[i].val);
9054
9055                 for (cnt = 0; cnt < 100; cnt++) {
9056                         elink_cl45_read(sc, phy, MDIO_PMA_DEVAD, 0xA818, &val);
9057                         if (val & 1)
9058                                 break;
9059                         DELAY(5);
9060                 }
9061                 if (cnt == 100) {
9062                         PMD_DRV_LOG(DEBUG, "Unable to read 848xx "
9063                                     "phy fw version(1)");
9064                         elink_save_spirom_version(sc, port, 0, phy->ver_addr);
9065                         return;
9066                 }
9067
9068                 /* 2) read register 0xc200_0000 (SPI_FW_STATUS) */
9069                 elink_cl45_write(sc, phy, MDIO_PMA_DEVAD, 0xA819, 0x0000);
9070                 elink_cl45_write(sc, phy, MDIO_PMA_DEVAD, 0xA81A, 0xc200);
9071                 elink_cl45_write(sc, phy, MDIO_PMA_DEVAD, 0xA817, 0x000A);
9072                 for (cnt = 0; cnt < 100; cnt++) {
9073                         elink_cl45_read(sc, phy, MDIO_PMA_DEVAD, 0xA818, &val);
9074                         if (val & 1)
9075                                 break;
9076                         DELAY(5);
9077                 }
9078                 if (cnt == 100) {
9079                         PMD_DRV_LOG(DEBUG, "Unable to read 848xx phy fw "
9080                                     "version(2)");
9081                         elink_save_spirom_version(sc, port, 0, phy->ver_addr);
9082                         return;
9083                 }
9084
9085                 /* lower 16 bits of the register SPI_FW_STATUS */
9086                 elink_cl45_read(sc, phy, MDIO_PMA_DEVAD, 0xA81B, &fw_ver1);
9087                 /* upper 16 bits of register SPI_FW_STATUS */
9088                 elink_cl45_read(sc, phy, MDIO_PMA_DEVAD, 0xA81C, &fw_ver2);
9089
9090                 elink_save_spirom_version(sc, port, (fw_ver2 << 16) | fw_ver1,
9091                                           phy->ver_addr);
9092         }
9093
9094 }
9095
9096 static void elink_848xx_set_led(struct bnx2x_softc *sc, struct elink_phy *phy)
9097 {
9098         uint16_t val, offset, i;
9099         static struct elink_reg_set reg_set[] = {
9100                 {MDIO_PMA_DEVAD, MDIO_PMA_REG_8481_LED1_MASK, 0x0080},
9101                 {MDIO_PMA_DEVAD, MDIO_PMA_REG_8481_LED2_MASK, 0x0018},
9102                 {MDIO_PMA_DEVAD, MDIO_PMA_REG_8481_LED3_MASK, 0x0006},
9103                 {MDIO_PMA_DEVAD, MDIO_PMA_REG_8481_LED3_BLINK, 0x0000},
9104                 {MDIO_PMA_DEVAD, MDIO_PMA_REG_84823_CTL_SLOW_CLK_CNT_HIGH,
9105                  MDIO_PMA_REG_84823_BLINK_RATE_VAL_15P9HZ},
9106                 {MDIO_AN_DEVAD, 0xFFFB, 0xFFFD}
9107         };
9108         /* PHYC_CTL_LED_CTL */
9109         elink_cl45_read(sc, phy,
9110                         MDIO_PMA_DEVAD, MDIO_PMA_REG_8481_LINK_SIGNAL, &val);
9111         val &= 0xFE00;
9112         val |= 0x0092;
9113
9114         elink_cl45_write(sc, phy,
9115                          MDIO_PMA_DEVAD, MDIO_PMA_REG_8481_LINK_SIGNAL, val);
9116
9117         for (i = 0; i < ARRAY_SIZE(reg_set); i++)
9118                 elink_cl45_write(sc, phy, reg_set[i].devad, reg_set[i].reg,
9119                                  reg_set[i].val);
9120
9121         if ((phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X84833) ||
9122             (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X84834))
9123                 offset = MDIO_PMA_REG_84833_CTL_LED_CTL_1;
9124         else
9125                 offset = MDIO_PMA_REG_84823_CTL_LED_CTL_1;
9126
9127         /* stretch_en for LED3 */
9128         elink_cl45_read_or_write(sc, phy,
9129                                  MDIO_PMA_DEVAD, offset,
9130                                  MDIO_PMA_REG_84823_LED3_STRETCH_EN);
9131 }
9132
9133 static void elink_848xx_specific_func(struct elink_phy *phy,
9134                                       struct elink_params *params,
9135                                       uint32_t action)
9136 {
9137         struct bnx2x_softc *sc = params->sc;
9138         switch (action) {
9139         case ELINK_PHY_INIT:
9140                 if ((phy->type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X84833) &&
9141                     (phy->type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X84834)) {
9142                         /* Save spirom version */
9143                         elink_save_848xx_spirom_version(phy, sc, params->port);
9144                 }
9145                 /* This phy uses the NIG latch mechanism since link indication
9146                  * arrives through its LED4 and not via its LASI signal, so we
9147                  * get steady signal instead of clear on read
9148                  */
9149                 elink_bits_en(sc, NIG_REG_LATCH_BC_0 + params->port * 4,
9150                               1 << ELINK_NIG_LATCH_BC_ENABLE_MI_INT);
9151
9152                 elink_848xx_set_led(sc, phy);
9153                 break;
9154         }
9155 }
9156
9157 static elink_status_t elink_848xx_cmn_config_init(struct elink_phy *phy,
9158                                                   struct elink_params *params,
9159                                                   struct elink_vars *vars)
9160 {
9161         struct bnx2x_softc *sc = params->sc;
9162         uint16_t autoneg_val, an_1000_val, an_10_100_val;
9163
9164         elink_848xx_specific_func(phy, params, ELINK_PHY_INIT);
9165         elink_cl45_write(sc, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x0000);
9166
9167         /* set 1000 speed advertisement */
9168         elink_cl45_read(sc, phy,
9169                         MDIO_AN_DEVAD, MDIO_AN_REG_8481_1000T_CTRL,
9170                         &an_1000_val);
9171
9172         elink_ext_phy_set_pause(params, phy, vars);
9173         elink_cl45_read(sc, phy,
9174                         MDIO_AN_DEVAD,
9175                         MDIO_AN_REG_8481_LEGACY_AN_ADV, &an_10_100_val);
9176         elink_cl45_read(sc, phy,
9177                         MDIO_AN_DEVAD, MDIO_AN_REG_8481_LEGACY_MII_CTRL,
9178                         &autoneg_val);
9179         /* Disable forced speed */
9180         autoneg_val &=
9181             ~((1 << 6) | (1 << 8) | (1 << 9) | (1 << 12) | (1 << 13));
9182         an_10_100_val &= ~((1 << 5) | (1 << 6) | (1 << 7) | (1 << 8));
9183
9184         if (((phy->req_line_speed == ELINK_SPEED_AUTO_NEG) &&
9185              (phy->speed_cap_mask &
9186               PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)) ||
9187             (phy->req_line_speed == ELINK_SPEED_1000)) {
9188                 an_1000_val |= (1 << 8);
9189                 autoneg_val |= (1 << 9 | 1 << 12);
9190                 if (phy->req_duplex == DUPLEX_FULL)
9191                         an_1000_val |= (1 << 9);
9192                 PMD_DRV_LOG(DEBUG, "Advertising 1G");
9193         } else
9194                 an_1000_val &= ~((1 << 8) | (1 << 9));
9195
9196         elink_cl45_write(sc, phy,
9197                          MDIO_AN_DEVAD, MDIO_AN_REG_8481_1000T_CTRL,
9198                          an_1000_val);
9199
9200         /* Set 10/100 speed advertisement */
9201         if (phy->req_line_speed == ELINK_SPEED_AUTO_NEG) {
9202                 if (phy->speed_cap_mask &
9203                     PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_FULL) {
9204                         /* Enable autoneg and restart autoneg for legacy speeds
9205                          */
9206                         autoneg_val |= (1 << 9 | 1 << 12);
9207                         an_10_100_val |= (1 << 8);
9208                         PMD_DRV_LOG(DEBUG, "Advertising 100M-FD");
9209                 }
9210
9211                 if (phy->speed_cap_mask &
9212                     PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_HALF) {
9213                         /* Enable autoneg and restart autoneg for legacy speeds
9214                          */
9215                         autoneg_val |= (1 << 9 | 1 << 12);
9216                         an_10_100_val |= (1 << 7);
9217                         PMD_DRV_LOG(DEBUG, "Advertising 100M-HD");
9218                 }
9219
9220                 if ((phy->speed_cap_mask &
9221                      PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL) &&
9222                     (phy->supported & ELINK_SUPPORTED_10baseT_Full)) {
9223                         an_10_100_val |= (1 << 6);
9224                         autoneg_val |= (1 << 9 | 1 << 12);
9225                         PMD_DRV_LOG(DEBUG, "Advertising 10M-FD");
9226                 }
9227
9228                 if ((phy->speed_cap_mask &
9229                      PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_HALF) &&
9230                     (phy->supported & ELINK_SUPPORTED_10baseT_Half)) {
9231                         an_10_100_val |= (1 << 5);
9232                         autoneg_val |= (1 << 9 | 1 << 12);
9233                         PMD_DRV_LOG(DEBUG, "Advertising 10M-HD");
9234                 }
9235         }
9236
9237         /* Only 10/100 are allowed to work in FORCE mode */
9238         if ((phy->req_line_speed == ELINK_SPEED_100) &&
9239             (phy->supported &
9240              (ELINK_SUPPORTED_100baseT_Half | ELINK_SUPPORTED_100baseT_Full))) {
9241                 autoneg_val |= (1 << 13);
9242                 /* Enabled AUTO-MDIX when autoneg is disabled */
9243                 elink_cl45_write(sc, phy,
9244                                  MDIO_AN_DEVAD, MDIO_AN_REG_8481_AUX_CTRL,
9245                                  (1 << 15 | 1 << 9 | 7 << 0));
9246                 /* The PHY needs this set even for forced link. */
9247                 an_10_100_val |= (1 << 8) | (1 << 7);
9248                 PMD_DRV_LOG(DEBUG, "Setting 100M force");
9249         }
9250         if ((phy->req_line_speed == ELINK_SPEED_10) &&
9251             (phy->supported &
9252              (ELINK_SUPPORTED_10baseT_Half | ELINK_SUPPORTED_10baseT_Full))) {
9253                 /* Enabled AUTO-MDIX when autoneg is disabled */
9254                 elink_cl45_write(sc, phy,
9255                                  MDIO_AN_DEVAD, MDIO_AN_REG_8481_AUX_CTRL,
9256                                  (1 << 15 | 1 << 9 | 7 << 0));
9257                 PMD_DRV_LOG(DEBUG, "Setting 10M force");
9258         }
9259
9260         elink_cl45_write(sc, phy,
9261                          MDIO_AN_DEVAD, MDIO_AN_REG_8481_LEGACY_AN_ADV,
9262                          an_10_100_val);
9263
9264         if (phy->req_duplex == DUPLEX_FULL)
9265                 autoneg_val |= (1 << 8);
9266
9267         /* Always write this if this is not 84833/4.
9268          * For 84833/4, write it only when it's a forced speed.
9269          */
9270         if (((phy->type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X84833) &&
9271              (phy->type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X84834)) ||
9272             ((autoneg_val & (1 << 12)) == 0))
9273                 elink_cl45_write(sc, phy,
9274                                  MDIO_AN_DEVAD,
9275                                  MDIO_AN_REG_8481_LEGACY_MII_CTRL, autoneg_val);
9276
9277         if (((phy->req_line_speed == ELINK_SPEED_AUTO_NEG) &&
9278              (phy->speed_cap_mask &
9279               PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)) ||
9280             (phy->req_line_speed == ELINK_SPEED_10000)) {
9281                 PMD_DRV_LOG(DEBUG, "Advertising 10G");
9282                 /* Restart autoneg for 10G */
9283
9284                 elink_cl45_read_or_write(sc, phy,
9285                                          MDIO_AN_DEVAD,
9286                                          MDIO_AN_REG_8481_10GBASE_T_AN_CTRL,
9287                                          0x1000);
9288                 elink_cl45_write(sc, phy,
9289                                  MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0x3200);
9290         } else
9291                 elink_cl45_write(sc, phy,
9292                                  MDIO_AN_DEVAD,
9293                                  MDIO_AN_REG_8481_10GBASE_T_AN_CTRL, 1);
9294
9295         return ELINK_STATUS_OK;
9296 }
9297
9298 static uint8_t elink_8481_config_init(struct elink_phy *phy,
9299                                              struct elink_params *params,
9300                                              struct elink_vars *vars)
9301 {
9302         struct bnx2x_softc *sc = params->sc;
9303         /* Restore normal power mode */
9304         elink_cb_gpio_write(sc, MISC_REGISTERS_GPIO_2,
9305                             MISC_REGISTERS_GPIO_OUTPUT_HIGH, params->port);
9306
9307         /* HW reset */
9308         elink_ext_phy_hw_reset(sc, params->port);
9309         elink_wait_reset_complete(sc, phy, params);
9310
9311         elink_cl45_write(sc, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 1 << 15);
9312         return elink_848xx_cmn_config_init(phy, params, vars);
9313 }
9314
9315 #define PHY84833_CMDHDLR_WAIT 300
9316 #define PHY84833_CMDHDLR_MAX_ARGS 5
9317 static elink_status_t elink_84833_cmd_hdlr(struct elink_phy *phy,
9318                                            struct elink_params *params,
9319                                            uint16_t fw_cmd, uint16_t cmd_args[],
9320                                            int argc)
9321 {
9322         int idx;
9323         uint16_t val;
9324         struct bnx2x_softc *sc = params->sc;
9325         /* Write CMD_OPEN_OVERRIDE to STATUS reg */
9326         elink_cl45_write(sc, phy, MDIO_CTL_DEVAD,
9327                          MDIO_84833_CMD_HDLR_STATUS,
9328                          PHY84833_STATUS_CMD_OPEN_OVERRIDE);
9329         for (idx = 0; idx < PHY84833_CMDHDLR_WAIT; idx++) {
9330                 elink_cl45_read(sc, phy, MDIO_CTL_DEVAD,
9331                                 MDIO_84833_CMD_HDLR_STATUS, &val);
9332                 if (val == PHY84833_STATUS_CMD_OPEN_FOR_CMDS)
9333                         break;
9334                 DELAY(1000 * 1);
9335         }
9336         if (idx >= PHY84833_CMDHDLR_WAIT) {
9337                 PMD_DRV_LOG(DEBUG, "FW cmd: FW not ready.");
9338                 return ELINK_STATUS_ERROR;
9339         }
9340
9341         /* Prepare argument(s) and issue command */
9342         for (idx = 0; idx < argc; idx++) {
9343                 elink_cl45_write(sc, phy, MDIO_CTL_DEVAD,
9344                                  MDIO_84833_CMD_HDLR_DATA1 + idx,
9345                                  cmd_args[idx]);
9346         }
9347         elink_cl45_write(sc, phy, MDIO_CTL_DEVAD,
9348                          MDIO_84833_CMD_HDLR_COMMAND, fw_cmd);
9349         for (idx = 0; idx < PHY84833_CMDHDLR_WAIT; idx++) {
9350                 elink_cl45_read(sc, phy, MDIO_CTL_DEVAD,
9351                                 MDIO_84833_CMD_HDLR_STATUS, &val);
9352                 if ((val == PHY84833_STATUS_CMD_COMPLETE_PASS) ||
9353                     (val == PHY84833_STATUS_CMD_COMPLETE_ERROR))
9354                         break;
9355                 DELAY(1000 * 1);
9356         }
9357         if ((idx >= PHY84833_CMDHDLR_WAIT) ||
9358             (val == PHY84833_STATUS_CMD_COMPLETE_ERROR)) {
9359                 PMD_DRV_LOG(DEBUG, "FW cmd failed.");
9360                 return ELINK_STATUS_ERROR;
9361         }
9362         /* Gather returning data */
9363         for (idx = 0; idx < argc; idx++) {
9364                 elink_cl45_read(sc, phy, MDIO_CTL_DEVAD,
9365                                 MDIO_84833_CMD_HDLR_DATA1 + idx,
9366                                 &cmd_args[idx]);
9367         }
9368         elink_cl45_write(sc, phy, MDIO_CTL_DEVAD,
9369                          MDIO_84833_CMD_HDLR_STATUS,
9370                          PHY84833_STATUS_CMD_CLEAR_COMPLETE);
9371         return ELINK_STATUS_OK;
9372 }
9373
9374 static elink_status_t elink_84833_pair_swap_cfg(struct elink_phy *phy,
9375                                                 struct elink_params *params,
9376                                                 __rte_unused struct elink_vars
9377                                                 *vars)
9378 {
9379         uint32_t pair_swap;
9380         uint16_t data[PHY84833_CMDHDLR_MAX_ARGS];
9381         elink_status_t status;
9382         struct bnx2x_softc *sc = params->sc;
9383
9384         /* Check for configuration. */
9385         pair_swap = REG_RD(sc, params->shmem_base +
9386                            offsetof(struct shmem_region,
9387                                     dev_info.port_hw_config[params->port].
9388                                     xgbt_phy_cfg)) &
9389             PORT_HW_CFG_RJ45_PAIR_SWAP_MASK;
9390
9391         if (pair_swap == 0)
9392                 return ELINK_STATUS_OK;
9393
9394         /* Only the second argument is used for this command */
9395         data[1] = (uint16_t) pair_swap;
9396
9397         status = elink_84833_cmd_hdlr(phy, params,
9398                                       PHY84833_CMD_SET_PAIR_SWAP, data,
9399                                       PHY84833_CMDHDLR_MAX_ARGS);
9400         if (status == ELINK_STATUS_OK) {
9401                 PMD_DRV_LOG(DEBUG, "Pairswap OK, val=0x%x", data[1]);
9402         }
9403
9404         return status;
9405 }
9406
9407 static uint8_t elink_84833_get_reset_gpios(struct bnx2x_softc *sc,
9408                                            uint32_t shmem_base_path[],
9409                                            __rte_unused uint32_t chip_id)
9410 {
9411         uint32_t reset_pin[2];
9412         uint32_t idx;
9413         uint8_t reset_gpios;
9414         if (CHIP_IS_E3(sc)) {
9415                 /* Assume that these will be GPIOs, not EPIOs. */
9416                 for (idx = 0; idx < 2; idx++) {
9417                         /* Map config param to register bit. */
9418                         reset_pin[idx] = REG_RD(sc, shmem_base_path[idx] +
9419                                                 offsetof(struct shmem_region,
9420                                                          dev_info.
9421                                                          port_hw_config[0].
9422                                                          e3_cmn_pin_cfg));
9423                         reset_pin[idx] =
9424                             (reset_pin[idx] & PORT_HW_CFG_E3_PHY_RESET_MASK) >>
9425                             PORT_HW_CFG_E3_PHY_RESET_SHIFT;
9426                         reset_pin[idx] -= PIN_CFG_GPIO0_P0;
9427                         reset_pin[idx] = (1 << reset_pin[idx]);
9428                 }
9429                 reset_gpios = (uint8_t) (reset_pin[0] | reset_pin[1]);
9430         } else {
9431                 /* E2, look from diff place of shmem. */
9432                 for (idx = 0; idx < 2; idx++) {
9433                         reset_pin[idx] = REG_RD(sc, shmem_base_path[idx] +
9434                                                 offsetof(struct shmem_region,
9435                                                          dev_info.
9436                                                          port_hw_config[0].
9437                                                          default_cfg));
9438                         reset_pin[idx] &= PORT_HW_CFG_EXT_PHY_GPIO_RST_MASK;
9439                         reset_pin[idx] -= PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO0_P0;
9440                         reset_pin[idx] >>= PORT_HW_CFG_EXT_PHY_GPIO_RST_SHIFT;
9441                         reset_pin[idx] = (1 << reset_pin[idx]);
9442                 }
9443                 reset_gpios = (uint8_t) (reset_pin[0] | reset_pin[1]);
9444         }
9445
9446         return reset_gpios;
9447 }
9448
9449 static void elink_84833_hw_reset_phy(struct elink_phy *phy,
9450                                         struct elink_params *params)
9451 {
9452         struct bnx2x_softc *sc = params->sc;
9453         uint8_t reset_gpios;
9454         uint32_t other_shmem_base_addr = REG_RD(sc, params->shmem2_base +
9455                                                 offsetof(struct shmem2_region,
9456                                                          other_shmem_base_addr));
9457
9458         uint32_t shmem_base_path[2];
9459
9460         /* Work around for 84833 LED failure inside RESET status */
9461         elink_cl45_write(sc, phy, MDIO_AN_DEVAD,
9462                          MDIO_AN_REG_8481_LEGACY_MII_CTRL,
9463                          MDIO_AN_REG_8481_MII_CTRL_FORCE_1G);
9464         elink_cl45_write(sc, phy, MDIO_AN_DEVAD,
9465                          MDIO_AN_REG_8481_1G_100T_EXT_CTRL,
9466                          MIDO_AN_REG_8481_EXT_CTRL_FORCE_LEDS_OFF);
9467
9468         shmem_base_path[0] = params->shmem_base;
9469         shmem_base_path[1] = other_shmem_base_addr;
9470
9471         reset_gpios = elink_84833_get_reset_gpios(sc, shmem_base_path,
9472                                                   params->chip_id);
9473
9474         elink_cb_gpio_mult_write(sc, reset_gpios,
9475                                  MISC_REGISTERS_GPIO_OUTPUT_LOW);
9476         DELAY(10);
9477         PMD_DRV_LOG(DEBUG, "84833 hw reset on pin values 0x%x", reset_gpios);
9478 }
9479
9480 static elink_status_t elink_8483x_disable_eee(struct elink_phy *phy,
9481                                               struct elink_params *params,
9482                                               struct elink_vars *vars)
9483 {
9484         elink_status_t rc;
9485         uint16_t cmd_args = 0;
9486
9487         PMD_DRV_LOG(DEBUG, "Don't Advertise 10GBase-T EEE");
9488
9489         /* Prevent Phy from working in EEE and advertising it */
9490         rc = elink_84833_cmd_hdlr(phy, params,
9491                                   PHY84833_CMD_SET_EEE_MODE, &cmd_args, 1);
9492         if (rc != ELINK_STATUS_OK) {
9493                 PMD_DRV_LOG(DEBUG, "EEE disable failed.");
9494                 return rc;
9495         }
9496
9497         return elink_eee_disable(phy, params, vars);
9498 }
9499
9500 static elink_status_t elink_8483x_enable_eee(struct elink_phy *phy,
9501                                              struct elink_params *params,
9502                                              struct elink_vars *vars)
9503 {
9504         elink_status_t rc;
9505         uint16_t cmd_args = 1;
9506
9507         rc = elink_84833_cmd_hdlr(phy, params,
9508                                   PHY84833_CMD_SET_EEE_MODE, &cmd_args, 1);
9509         if (rc != ELINK_STATUS_OK) {
9510                 PMD_DRV_LOG(DEBUG, "EEE enable failed.");
9511                 return rc;
9512         }
9513
9514         return elink_eee_advertise(phy, params, vars, SHMEM_EEE_10G_ADV);
9515 }
9516
9517 #define PHY84833_CONSTANT_LATENCY 1193
9518 static uint8_t elink_848x3_config_init(struct elink_phy *phy,
9519                                        struct elink_params *params,
9520                                        struct elink_vars *vars)
9521 {
9522         struct bnx2x_softc *sc = params->sc;
9523         uint8_t port, initialize = 1;
9524         uint16_t val;
9525         uint32_t actual_phy_selection;
9526         uint16_t cmd_args[PHY84833_CMDHDLR_MAX_ARGS];
9527         elink_status_t rc = ELINK_STATUS_OK;
9528
9529         DELAY(1000 * 1);
9530
9531         if (!(CHIP_IS_E1x(sc)))
9532                 port = SC_PATH(sc);
9533         else
9534                 port = params->port;
9535
9536         if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X84823) {
9537                 elink_cb_gpio_write(sc, MISC_REGISTERS_GPIO_3,
9538                                     MISC_REGISTERS_GPIO_OUTPUT_HIGH, port);
9539         } else {
9540                 /* MDIO reset */
9541                 elink_cl45_write(sc, phy,
9542                                  MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x8000);
9543         }
9544
9545         elink_wait_reset_complete(sc, phy, params);
9546
9547         /* Wait for GPHY to come out of reset */
9548         DELAY(1000 * 50);
9549         if ((phy->type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X84833) &&
9550             (phy->type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X84834)) {
9551                 /* BNX2X84823 requires that XGXS links up first @ 10G for normal
9552                  * behavior.
9553                  */
9554                 uint16_t temp;
9555                 temp = vars->line_speed;
9556                 vars->line_speed = ELINK_SPEED_10000;
9557                 elink_set_autoneg(&params->phy[ELINK_INT_PHY], params, vars, 0);
9558                 elink_program_serdes(&params->phy[ELINK_INT_PHY], params, vars);
9559                 vars->line_speed = temp;
9560         }
9561
9562         elink_cl45_read(sc, phy, MDIO_CTL_DEVAD,
9563                         MDIO_CTL_REG_84823_MEDIA, &val);
9564         val &= ~(MDIO_CTL_REG_84823_MEDIA_MAC_MASK |
9565                  MDIO_CTL_REG_84823_MEDIA_LINE_MASK |
9566                  MDIO_CTL_REG_84823_MEDIA_COPPER_CORE_DOWN |
9567                  MDIO_CTL_REG_84823_MEDIA_PRIORITY_MASK |
9568                  MDIO_CTL_REG_84823_MEDIA_FIBER_1G);
9569
9570         if (CHIP_IS_E3(sc)) {
9571                 val &= ~(MDIO_CTL_REG_84823_MEDIA_MAC_MASK |
9572                          MDIO_CTL_REG_84823_MEDIA_LINE_MASK);
9573         } else {
9574                 val |= (MDIO_CTL_REG_84823_CTRL_MAC_XFI |
9575                         MDIO_CTL_REG_84823_MEDIA_LINE_XAUI_L);
9576         }
9577
9578         actual_phy_selection = elink_phy_selection(params);
9579
9580         switch (actual_phy_selection) {
9581         case PORT_HW_CFG_PHY_SELECTION_HARDWARE_DEFAULT:
9582                 /* Do nothing. Essentially this is like the priority copper */
9583                 break;
9584         case PORT_HW_CFG_PHY_SELECTION_FIRST_PHY_PRIORITY:
9585                 val |= MDIO_CTL_REG_84823_MEDIA_PRIORITY_COPPER;
9586                 break;
9587         case PORT_HW_CFG_PHY_SELECTION_SECOND_PHY_PRIORITY:
9588                 val |= MDIO_CTL_REG_84823_MEDIA_PRIORITY_FIBER;
9589                 break;
9590         case PORT_HW_CFG_PHY_SELECTION_FIRST_PHY:
9591                 /* Do nothing here. The first PHY won't be initialized at all */
9592                 break;
9593         case PORT_HW_CFG_PHY_SELECTION_SECOND_PHY:
9594                 val |= MDIO_CTL_REG_84823_MEDIA_COPPER_CORE_DOWN;
9595                 initialize = 0;
9596                 break;
9597         }
9598         if (params->phy[ELINK_EXT_PHY2].req_line_speed == ELINK_SPEED_1000)
9599                 val |= MDIO_CTL_REG_84823_MEDIA_FIBER_1G;
9600
9601         elink_cl45_write(sc, phy, MDIO_CTL_DEVAD,
9602                          MDIO_CTL_REG_84823_MEDIA, val);
9603         PMD_DRV_LOG(DEBUG, "Multi_phy config = 0x%x, Media control = 0x%x",
9604                     params->multi_phy_config, val);
9605
9606         if ((phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X84833) ||
9607             (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X84834)) {
9608                 elink_84833_pair_swap_cfg(phy, params, vars);
9609
9610                 /* Keep AutogrEEEn disabled. */
9611                 cmd_args[0] = 0x0;
9612                 cmd_args[1] = 0x0;
9613                 cmd_args[2] = PHY84833_CONSTANT_LATENCY + 1;
9614                 cmd_args[3] = PHY84833_CONSTANT_LATENCY;
9615                 rc = elink_84833_cmd_hdlr(phy, params,
9616                                           PHY84833_CMD_SET_EEE_MODE, cmd_args,
9617                                           PHY84833_CMDHDLR_MAX_ARGS);
9618                 if (rc != ELINK_STATUS_OK) {
9619                         PMD_DRV_LOG(DEBUG, "Cfg AutogrEEEn failed.");
9620                 }
9621         }
9622         if (initialize) {
9623                 rc = elink_848xx_cmn_config_init(phy, params, vars);
9624         } else {
9625                 elink_save_848xx_spirom_version(phy, sc, params->port);
9626         }
9627         /* 84833 PHY has a better feature and doesn't need to support this. */
9628         if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X84823) {
9629                 uint32_t cms_enable = REG_RD(sc, params->shmem_base +
9630                                              offsetof(struct shmem_region,
9631                                                       dev_info.
9632                                                       port_hw_config[params->
9633                                                                      port].
9634                                                       default_cfg)) &
9635                     PORT_HW_CFG_ENABLE_CMS_MASK;
9636
9637                 elink_cl45_read(sc, phy, MDIO_CTL_DEVAD,
9638                                 MDIO_CTL_REG_84823_USER_CTRL_REG, &val);
9639                 if (cms_enable)
9640                         val |= MDIO_CTL_REG_84823_USER_CTRL_CMS;
9641                 else
9642                         val &= ~MDIO_CTL_REG_84823_USER_CTRL_CMS;
9643                 elink_cl45_write(sc, phy, MDIO_CTL_DEVAD,
9644                                  MDIO_CTL_REG_84823_USER_CTRL_REG, val);
9645         }
9646
9647         elink_cl45_read(sc, phy, MDIO_CTL_DEVAD,
9648                         MDIO_84833_TOP_CFG_FW_REV, &val);
9649
9650         /* Configure EEE support */
9651         if ((val >= MDIO_84833_TOP_CFG_FW_EEE) &&
9652             (val != MDIO_84833_TOP_CFG_FW_NO_EEE) &&
9653             elink_eee_has_cap(params)) {
9654                 rc = elink_eee_initial_config(params, vars, SHMEM_EEE_10G_ADV);
9655                 if (rc != ELINK_STATUS_OK) {
9656                         PMD_DRV_LOG(DEBUG, "Failed to configure EEE timers");
9657                         elink_8483x_disable_eee(phy, params, vars);
9658                         return rc;
9659                 }
9660
9661                 if ((phy->req_duplex == DUPLEX_FULL) &&
9662                     (params->eee_mode & ELINK_EEE_MODE_ADV_LPI) &&
9663                     (elink_eee_calc_timer(params) ||
9664                      !(params->eee_mode & ELINK_EEE_MODE_ENABLE_LPI)))
9665                         rc = elink_8483x_enable_eee(phy, params, vars);
9666                 else
9667                         rc = elink_8483x_disable_eee(phy, params, vars);
9668                 if (rc != ELINK_STATUS_OK) {
9669                         PMD_DRV_LOG(DEBUG, "Failed to set EEE advertisement");
9670                         return rc;
9671                 }
9672         } else {
9673                 vars->eee_status &= ~SHMEM_EEE_SUPPORTED_MASK;
9674         }
9675
9676         if ((phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X84833) ||
9677             (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X84834)) {
9678                 /* Bring PHY out of super isolate mode as the final step. */
9679                 elink_cl45_read_and_write(sc, phy,
9680                                           MDIO_CTL_DEVAD,
9681                                           MDIO_84833_TOP_CFG_XGPHY_STRAP1,
9682                                           (uint16_t) ~
9683                                           MDIO_84833_SUPER_ISOLATE);
9684         }
9685         return rc;
9686 }
9687
9688 static uint8_t elink_848xx_read_status(struct elink_phy *phy,
9689                                        struct elink_params *params,
9690                                        struct elink_vars *vars)
9691 {
9692         struct bnx2x_softc *sc = params->sc;
9693         uint16_t val, val1, val2;
9694         uint8_t link_up = 0;
9695
9696         /* Check 10G-BaseT link status */
9697         /* Check PMD signal ok */
9698         elink_cl45_read(sc, phy, MDIO_AN_DEVAD, 0xFFFA, &val1);
9699         elink_cl45_read(sc, phy,
9700                         MDIO_PMA_DEVAD, MDIO_PMA_REG_8481_PMD_SIGNAL, &val2);
9701         PMD_DRV_LOG(DEBUG, "BNX2X848xx: PMD_SIGNAL 1.a811 = 0x%x", val2);
9702
9703         /* Check link 10G */
9704         if (val2 & (1 << 11)) {
9705                 vars->line_speed = ELINK_SPEED_10000;
9706                 vars->duplex = DUPLEX_FULL;
9707                 link_up = 1;
9708                 elink_ext_phy_10G_an_resolve(sc, phy, vars);
9709         } else {                /* Check Legacy speed link */
9710                 uint16_t legacy_status, legacy_speed, mii_ctrl;
9711
9712                 /* Enable expansion register 0x42 (Operation mode status) */
9713                 elink_cl45_write(sc, phy,
9714                                  MDIO_AN_DEVAD,
9715                                  MDIO_AN_REG_8481_EXPANSION_REG_ACCESS, 0xf42);
9716
9717                 /* Get legacy speed operation status */
9718                 elink_cl45_read(sc, phy,
9719                                 MDIO_AN_DEVAD,
9720                                 MDIO_AN_REG_8481_EXPANSION_REG_RD_RW,
9721                                 &legacy_status);
9722
9723                 PMD_DRV_LOG(DEBUG, "Legacy speed status = 0x%x", legacy_status);
9724                 link_up = ((legacy_status & (1 << 11)) == (1 << 11));
9725                 legacy_speed = (legacy_status & (3 << 9));
9726                 if (legacy_speed == (0 << 9))
9727                         vars->line_speed = ELINK_SPEED_10;
9728                 else if (legacy_speed == (1 << 9))
9729                         vars->line_speed = ELINK_SPEED_100;
9730                 else if (legacy_speed == (2 << 9))
9731                         vars->line_speed = ELINK_SPEED_1000;
9732                 else {          /* Should not happen: Treat as link down */
9733                         vars->line_speed = 0;
9734                         link_up = 0;
9735                 }
9736
9737                 if (params->feature_config_flags &
9738                     ELINK_FEATURE_CONFIG_IEEE_PHY_TEST) {
9739                         elink_cl45_read(sc, phy,
9740                                         MDIO_AN_DEVAD,
9741                                         MDIO_AN_REG_8481_LEGACY_MII_CTRL,
9742                                         &mii_ctrl);
9743                         /* For IEEE testing, check for a fake link. */
9744                         link_up |= ((mii_ctrl & 0x3040) == 0x40);
9745                 }
9746
9747                 if (link_up) {
9748                         if (legacy_status & (1 << 8))
9749                                 vars->duplex = DUPLEX_FULL;
9750                         else
9751                                 vars->duplex = DUPLEX_HALF;
9752
9753                         PMD_DRV_LOG(DEBUG,
9754                                     "Link is up in %dMbps, is_duplex_full= %d",
9755                                     vars->line_speed,
9756                                     (vars->duplex == DUPLEX_FULL));
9757                         /* Check legacy speed AN resolution */
9758                         elink_cl45_read(sc, phy,
9759                                         MDIO_AN_DEVAD,
9760                                         MDIO_AN_REG_8481_LEGACY_MII_STATUS,
9761                                         &val);
9762                         if (val & (1 << 5))
9763                                 vars->link_status |=
9764                                     LINK_STATUS_AUTO_NEGOTIATE_COMPLETE;
9765                         elink_cl45_read(sc, phy,
9766                                         MDIO_AN_DEVAD,
9767                                         MDIO_AN_REG_8481_LEGACY_AN_EXPANSION,
9768                                         &val);
9769                         if ((val & (1 << 0)) == 0)
9770                                 vars->link_status |=
9771                                     LINK_STATUS_PARALLEL_DETECTION_USED;
9772                 }
9773         }
9774         if (link_up) {
9775                 PMD_DRV_LOG(DEBUG, "BNX2X848x3: link speed is %d",
9776                             vars->line_speed);
9777                 elink_ext_phy_resolve_fc(phy, params, vars);
9778
9779                 /* Read LP advertised speeds */
9780                 elink_cl45_read(sc, phy, MDIO_AN_DEVAD,
9781                                 MDIO_AN_REG_CL37_FC_LP, &val);
9782                 if (val & (1 << 5))
9783                         vars->link_status |=
9784                             LINK_STATUS_LINK_PARTNER_10THD_CAPABLE;
9785                 if (val & (1 << 6))
9786                         vars->link_status |=
9787                             LINK_STATUS_LINK_PARTNER_10TFD_CAPABLE;
9788                 if (val & (1 << 7))
9789                         vars->link_status |=
9790                             LINK_STATUS_LINK_PARTNER_100TXHD_CAPABLE;
9791                 if (val & (1 << 8))
9792                         vars->link_status |=
9793                             LINK_STATUS_LINK_PARTNER_100TXFD_CAPABLE;
9794                 if (val & (1 << 9))
9795                         vars->link_status |=
9796                             LINK_STATUS_LINK_PARTNER_100T4_CAPABLE;
9797
9798                 elink_cl45_read(sc, phy, MDIO_AN_DEVAD,
9799                                 MDIO_AN_REG_1000T_STATUS, &val);
9800
9801                 if (val & (1 << 10))
9802                         vars->link_status |=
9803                             LINK_STATUS_LINK_PARTNER_1000THD_CAPABLE;
9804                 if (val & (1 << 11))
9805                         vars->link_status |=
9806                             LINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE;
9807
9808                 elink_cl45_read(sc, phy, MDIO_AN_DEVAD,
9809                                 MDIO_AN_REG_MASTER_STATUS, &val);
9810
9811                 if (val & (1 << 11))
9812                         vars->link_status |=
9813                             LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE;
9814
9815                 /* Determine if EEE was negotiated */
9816                 if ((phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X84833) ||
9817                     (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X84834))
9818                         elink_eee_an_resolve(phy, params, vars);
9819         }
9820
9821         return link_up;
9822 }
9823
9824 static uint8_t elink_848xx_format_ver(uint32_t raw_ver, uint8_t * str,
9825                                              uint16_t * len)
9826 {
9827         elink_status_t status = ELINK_STATUS_OK;
9828         uint32_t spirom_ver;
9829         spirom_ver = ((raw_ver & 0xF80) >> 7) << 16 | (raw_ver & 0x7F);
9830         status = elink_format_ver(spirom_ver, str, len);
9831         return status;
9832 }
9833
9834 static void elink_8481_hw_reset(__rte_unused struct elink_phy *phy,
9835                                 struct elink_params *params)
9836 {
9837         elink_cb_gpio_write(params->sc, MISC_REGISTERS_GPIO_1,
9838                             MISC_REGISTERS_GPIO_OUTPUT_LOW, 0);
9839         elink_cb_gpio_write(params->sc, MISC_REGISTERS_GPIO_1,
9840                             MISC_REGISTERS_GPIO_OUTPUT_LOW, 1);
9841 }
9842
9843 static void elink_8481_link_reset(struct elink_phy *phy,
9844                                   struct elink_params *params)
9845 {
9846         elink_cl45_write(params->sc, phy,
9847                          MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0x0000);
9848         elink_cl45_write(params->sc, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 1);
9849 }
9850
9851 static void elink_848x3_link_reset(struct elink_phy *phy,
9852                                    struct elink_params *params)
9853 {
9854         struct bnx2x_softc *sc = params->sc;
9855         uint8_t port;
9856         uint16_t val16;
9857
9858         if (!(CHIP_IS_E1x(sc)))
9859                 port = SC_PATH(sc);
9860         else
9861                 port = params->port;
9862
9863         if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X84823) {
9864                 elink_cb_gpio_write(sc, MISC_REGISTERS_GPIO_3,
9865                                     MISC_REGISTERS_GPIO_OUTPUT_LOW, port);
9866         } else {
9867                 elink_cl45_read(sc, phy,
9868                                 MDIO_CTL_DEVAD,
9869                                 MDIO_84833_TOP_CFG_XGPHY_STRAP1, &val16);
9870                 val16 |= MDIO_84833_SUPER_ISOLATE;
9871                 elink_cl45_write(sc, phy,
9872                                  MDIO_CTL_DEVAD,
9873                                  MDIO_84833_TOP_CFG_XGPHY_STRAP1, val16);
9874         }
9875 }
9876
9877 static void elink_848xx_set_link_led(struct elink_phy *phy,
9878                                      struct elink_params *params, uint8_t mode)
9879 {
9880         struct bnx2x_softc *sc = params->sc;
9881         uint16_t val;
9882         __rte_unused uint8_t port;
9883
9884         if (!(CHIP_IS_E1x(sc)))
9885                 port = SC_PATH(sc);
9886         else
9887                 port = params->port;
9888
9889         switch (mode) {
9890         case ELINK_LED_MODE_OFF:
9891
9892                 PMD_DRV_LOG(DEBUG, "Port 0x%x: LED MODE OFF", port);
9893
9894                 if ((params->hw_led_mode << SHARED_HW_CFG_LED_MODE_SHIFT) ==
9895                     SHARED_HW_CFG_LED_EXTPHY1) {
9896
9897                         /* Set LED masks */
9898                         elink_cl45_write(sc, phy,
9899                                          MDIO_PMA_DEVAD,
9900                                          MDIO_PMA_REG_8481_LED1_MASK, 0x0);
9901
9902                         elink_cl45_write(sc, phy,
9903                                          MDIO_PMA_DEVAD,
9904                                          MDIO_PMA_REG_8481_LED2_MASK, 0x0);
9905
9906                         elink_cl45_write(sc, phy,
9907                                          MDIO_PMA_DEVAD,
9908                                          MDIO_PMA_REG_8481_LED3_MASK, 0x0);
9909
9910                         elink_cl45_write(sc, phy,
9911                                          MDIO_PMA_DEVAD,
9912                                          MDIO_PMA_REG_8481_LED5_MASK, 0x0);
9913
9914                 } else {
9915                         elink_cl45_write(sc, phy,
9916                                          MDIO_PMA_DEVAD,
9917                                          MDIO_PMA_REG_8481_LED1_MASK, 0x0);
9918                 }
9919                 break;
9920         case ELINK_LED_MODE_FRONT_PANEL_OFF:
9921
9922                 PMD_DRV_LOG(DEBUG, "Port 0x%x: LED MODE FRONT PANEL OFF", port);
9923
9924                 if ((params->hw_led_mode << SHARED_HW_CFG_LED_MODE_SHIFT) ==
9925                     SHARED_HW_CFG_LED_EXTPHY1) {
9926
9927                         /* Set LED masks */
9928                         elink_cl45_write(sc, phy,
9929                                          MDIO_PMA_DEVAD,
9930                                          MDIO_PMA_REG_8481_LED1_MASK, 0x0);
9931
9932                         elink_cl45_write(sc, phy,
9933                                          MDIO_PMA_DEVAD,
9934                                          MDIO_PMA_REG_8481_LED2_MASK, 0x0);
9935
9936                         elink_cl45_write(sc, phy,
9937                                          MDIO_PMA_DEVAD,
9938                                          MDIO_PMA_REG_8481_LED3_MASK, 0x0);
9939
9940                         elink_cl45_write(sc, phy,
9941                                          MDIO_PMA_DEVAD,
9942                                          MDIO_PMA_REG_8481_LED5_MASK, 0x20);
9943
9944                 } else {
9945                         elink_cl45_write(sc, phy,
9946                                          MDIO_PMA_DEVAD,
9947                                          MDIO_PMA_REG_8481_LED1_MASK, 0x0);
9948                         if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X84834) {
9949                                 /* Disable MI_INT interrupt before setting LED4
9950                                  * source to constant off.
9951                                  */
9952                                 if (REG_RD(sc, NIG_REG_MASK_INTERRUPT_PORT0 +
9953                                            params->port * 4) &
9954                                     ELINK_NIG_MASK_MI_INT) {
9955                                         params->link_flags |=
9956                                             ELINK_LINK_FLAGS_INT_DISABLED;
9957
9958                                         elink_bits_dis(sc,
9959                                                        NIG_REG_MASK_INTERRUPT_PORT0
9960                                                        + params->port * 4,
9961                                                        ELINK_NIG_MASK_MI_INT);
9962                                 }
9963                                 elink_cl45_write(sc, phy,
9964                                                  MDIO_PMA_DEVAD,
9965                                                  MDIO_PMA_REG_8481_SIGNAL_MASK,
9966                                                  0x0);
9967                         }
9968                 }
9969                 break;
9970         case ELINK_LED_MODE_ON:
9971
9972                 PMD_DRV_LOG(DEBUG, "Port 0x%x: LED MODE ON", port);
9973
9974                 if ((params->hw_led_mode << SHARED_HW_CFG_LED_MODE_SHIFT) ==
9975                     SHARED_HW_CFG_LED_EXTPHY1) {
9976                         /* Set control reg */
9977                         elink_cl45_read(sc, phy,
9978                                         MDIO_PMA_DEVAD,
9979                                         MDIO_PMA_REG_8481_LINK_SIGNAL, &val);
9980                         val &= 0x8000;
9981                         val |= 0x2492;
9982
9983                         elink_cl45_write(sc, phy,
9984                                          MDIO_PMA_DEVAD,
9985                                          MDIO_PMA_REG_8481_LINK_SIGNAL, val);
9986
9987                         /* Set LED masks */
9988                         elink_cl45_write(sc, phy,
9989                                          MDIO_PMA_DEVAD,
9990                                          MDIO_PMA_REG_8481_LED1_MASK, 0x0);
9991
9992                         elink_cl45_write(sc, phy,
9993                                          MDIO_PMA_DEVAD,
9994                                          MDIO_PMA_REG_8481_LED2_MASK, 0x20);
9995
9996                         elink_cl45_write(sc, phy,
9997                                          MDIO_PMA_DEVAD,
9998                                          MDIO_PMA_REG_8481_LED3_MASK, 0x20);
9999
10000                         elink_cl45_write(sc, phy,
10001                                          MDIO_PMA_DEVAD,
10002                                          MDIO_PMA_REG_8481_LED5_MASK, 0x0);
10003                 } else {
10004                         elink_cl45_write(sc, phy,
10005                                          MDIO_PMA_DEVAD,
10006                                          MDIO_PMA_REG_8481_LED1_MASK, 0x20);
10007                         if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X84834) {
10008                                 /* Disable MI_INT interrupt before setting LED4
10009                                  * source to constant on.
10010                                  */
10011                                 if (REG_RD(sc, NIG_REG_MASK_INTERRUPT_PORT0 +
10012                                            params->port * 4) &
10013                                     ELINK_NIG_MASK_MI_INT) {
10014                                         params->link_flags |=
10015                                             ELINK_LINK_FLAGS_INT_DISABLED;
10016
10017                                         elink_bits_dis(sc,
10018                                                        NIG_REG_MASK_INTERRUPT_PORT0
10019                                                        + params->port * 4,
10020                                                        ELINK_NIG_MASK_MI_INT);
10021                                 }
10022                                 elink_cl45_write(sc, phy,
10023                                                  MDIO_PMA_DEVAD,
10024                                                  MDIO_PMA_REG_8481_SIGNAL_MASK,
10025                                                  0x20);
10026                         }
10027                 }
10028                 break;
10029
10030         case ELINK_LED_MODE_OPER:
10031
10032                 PMD_DRV_LOG(DEBUG, "Port 0x%x: LED MODE OPER", port);
10033
10034                 if ((params->hw_led_mode << SHARED_HW_CFG_LED_MODE_SHIFT) ==
10035                     SHARED_HW_CFG_LED_EXTPHY1) {
10036
10037                         /* Set control reg */
10038                         elink_cl45_read(sc, phy,
10039                                         MDIO_PMA_DEVAD,
10040                                         MDIO_PMA_REG_8481_LINK_SIGNAL, &val);
10041
10042                         if (!((val &
10043                                MDIO_PMA_REG_8481_LINK_SIGNAL_LED4_ENABLE_MASK)
10044                               >>
10045                               MDIO_PMA_REG_8481_LINK_SIGNAL_LED4_ENABLE_SHIFT))
10046                         {
10047                                 PMD_DRV_LOG(DEBUG, "Setting LINK_SIGNAL");
10048                                 elink_cl45_write(sc, phy,
10049                                                  MDIO_PMA_DEVAD,
10050                                                  MDIO_PMA_REG_8481_LINK_SIGNAL,
10051                                                  0xa492);
10052                         }
10053
10054                         /* Set LED masks */
10055                         elink_cl45_write(sc, phy,
10056                                          MDIO_PMA_DEVAD,
10057                                          MDIO_PMA_REG_8481_LED1_MASK, 0x10);
10058
10059                         elink_cl45_write(sc, phy,
10060                                          MDIO_PMA_DEVAD,
10061                                          MDIO_PMA_REG_8481_LED2_MASK, 0x80);
10062
10063                         elink_cl45_write(sc, phy,
10064                                          MDIO_PMA_DEVAD,
10065                                          MDIO_PMA_REG_8481_LED3_MASK, 0x98);
10066
10067                         elink_cl45_write(sc, phy,
10068                                          MDIO_PMA_DEVAD,
10069                                          MDIO_PMA_REG_8481_LED5_MASK, 0x40);
10070
10071                 } else {
10072                         /* EXTPHY2 LED mode indicate that the 100M/1G/10G LED
10073                          * sources are all wired through LED1, rather than only
10074                          * 10G in other modes.
10075                          */
10076                         val = ((params->hw_led_mode <<
10077                                 SHARED_HW_CFG_LED_MODE_SHIFT) ==
10078                                SHARED_HW_CFG_LED_EXTPHY2) ? 0x98 : 0x80;
10079
10080                         elink_cl45_write(sc, phy,
10081                                          MDIO_PMA_DEVAD,
10082                                          MDIO_PMA_REG_8481_LED1_MASK, val);
10083
10084                         /* Tell LED3 to blink on source */
10085                         elink_cl45_read(sc, phy,
10086                                         MDIO_PMA_DEVAD,
10087                                         MDIO_PMA_REG_8481_LINK_SIGNAL, &val);
10088                         val &= ~(7 << 6);
10089                         val |= (1 << 6);        /* A83B[8:6]= 1 */
10090                         elink_cl45_write(sc, phy,
10091                                          MDIO_PMA_DEVAD,
10092                                          MDIO_PMA_REG_8481_LINK_SIGNAL, val);
10093                         if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X84834) {
10094                                 /* Restore LED4 source to external link,
10095                                  * and re-enable interrupts.
10096                                  */
10097                                 elink_cl45_write(sc, phy,
10098                                                  MDIO_PMA_DEVAD,
10099                                                  MDIO_PMA_REG_8481_SIGNAL_MASK,
10100                                                  0x40);
10101                                 if (params->link_flags &
10102                                     ELINK_LINK_FLAGS_INT_DISABLED) {
10103                                         elink_link_int_enable(params);
10104                                         params->link_flags &=
10105                                             ~ELINK_LINK_FLAGS_INT_DISABLED;
10106                                 }
10107                         }
10108                 }
10109                 break;
10110         }
10111
10112         /* This is a workaround for E3+84833 until autoneg
10113          * restart is fixed in f/w
10114          */
10115         if (CHIP_IS_E3(sc)) {
10116                 elink_cl45_read(sc, phy, MDIO_WC_DEVAD,
10117                                 MDIO_WC_REG_GP2_STATUS_GP_2_1, &val);
10118         }
10119 }
10120
10121 /******************************************************************/
10122 /*                      54618SE PHY SECTION                       */
10123 /******************************************************************/
10124 static void elink_54618se_specific_func(struct elink_phy *phy,
10125                                         struct elink_params *params,
10126                                         uint32_t action)
10127 {
10128         struct bnx2x_softc *sc = params->sc;
10129         uint16_t temp;
10130         switch (action) {
10131         case ELINK_PHY_INIT:
10132                 /* Configure LED4: set to INTR (0x6). */
10133                 /* Accessing shadow register 0xe. */
10134                 elink_cl22_write(sc, phy,
10135                                  MDIO_REG_GPHY_SHADOW,
10136                                  MDIO_REG_GPHY_SHADOW_LED_SEL2);
10137                 elink_cl22_read(sc, phy, MDIO_REG_GPHY_SHADOW, &temp);
10138                 temp &= ~(0xf << 4);
10139                 temp |= (0x6 << 4);
10140                 elink_cl22_write(sc, phy,
10141                                  MDIO_REG_GPHY_SHADOW,
10142                                  MDIO_REG_GPHY_SHADOW_WR_ENA | temp);
10143                 /* Configure INTR based on link status change. */
10144                 elink_cl22_write(sc, phy,
10145                                  MDIO_REG_INTR_MASK,
10146                                  ~MDIO_REG_INTR_MASK_LINK_STATUS);
10147                 break;
10148         }
10149 }
10150
10151 static uint8_t elink_54618se_config_init(struct elink_phy *phy,
10152                                          struct elink_params *params,
10153                                          struct elink_vars *vars)
10154 {
10155         struct bnx2x_softc *sc = params->sc;
10156         uint8_t port;
10157         uint16_t autoneg_val, an_1000_val, an_10_100_val, fc_val, temp;
10158         uint32_t cfg_pin;
10159
10160         PMD_DRV_LOG(DEBUG, "54618SE cfg init");
10161         DELAY(1000 * 1);
10162
10163         /* This works with E3 only, no need to check the chip
10164          * before determining the port.
10165          */
10166         port = params->port;
10167
10168         cfg_pin = (REG_RD(sc, params->shmem_base +
10169                           offsetof(struct shmem_region,
10170                                    dev_info.port_hw_config[port].
10171                                    e3_cmn_pin_cfg)) &
10172                    PORT_HW_CFG_E3_PHY_RESET_MASK) >>
10173             PORT_HW_CFG_E3_PHY_RESET_SHIFT;
10174
10175         /* Drive pin high to bring the GPHY out of reset. */
10176         elink_set_cfg_pin(sc, cfg_pin, 1);
10177
10178         /* wait for GPHY to reset */
10179         DELAY(1000 * 50);
10180
10181         /* reset phy */
10182         elink_cl22_write(sc, phy, MDIO_PMA_REG_CTRL, 0x8000);
10183         elink_wait_reset_complete(sc, phy, params);
10184
10185         /* Wait for GPHY to reset */
10186         DELAY(1000 * 50);
10187
10188         elink_54618se_specific_func(phy, params, ELINK_PHY_INIT);
10189         /* Flip the signal detect polarity (set 0x1c.0x1e[8]). */
10190         elink_cl22_write(sc, phy,
10191                          MDIO_REG_GPHY_SHADOW,
10192                          MDIO_REG_GPHY_SHADOW_AUTO_DET_MED);
10193         elink_cl22_read(sc, phy, MDIO_REG_GPHY_SHADOW, &temp);
10194         temp |= MDIO_REG_GPHY_SHADOW_INVERT_FIB_SD;
10195         elink_cl22_write(sc, phy,
10196                          MDIO_REG_GPHY_SHADOW,
10197                          MDIO_REG_GPHY_SHADOW_WR_ENA | temp);
10198
10199         /* Set up fc */
10200         /* Please refer to Table 28B-3 of 802.3ab-1999 spec. */
10201         elink_calc_ieee_aneg_adv(phy, params, &vars->ieee_fc);
10202         fc_val = 0;
10203         if ((vars->ieee_fc & MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC) ==
10204             MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC)
10205                 fc_val |= MDIO_AN_REG_ADV_PAUSE_ASYMMETRIC;
10206
10207         if ((vars->ieee_fc & MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) ==
10208             MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH)
10209                 fc_val |= MDIO_AN_REG_ADV_PAUSE_PAUSE;
10210
10211         /* Read all advertisement */
10212         elink_cl22_read(sc, phy, 0x09, &an_1000_val);
10213
10214         elink_cl22_read(sc, phy, 0x04, &an_10_100_val);
10215
10216         elink_cl22_read(sc, phy, MDIO_PMA_REG_CTRL, &autoneg_val);
10217
10218         /* Disable forced speed */
10219         autoneg_val &=
10220             ~((1 << 6) | (1 << 8) | (1 << 9) | (1 << 12) | (1 << 13));
10221         an_10_100_val &=
10222             ~((1 << 5) | (1 << 6) | (1 << 7) | (1 << 8) | (1 << 10) |
10223               (1 << 11));
10224
10225         if (((phy->req_line_speed == ELINK_SPEED_AUTO_NEG) &&
10226              (phy->speed_cap_mask &
10227               PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)) ||
10228             (phy->req_line_speed == ELINK_SPEED_1000)) {
10229                 an_1000_val |= (1 << 8);
10230                 autoneg_val |= (1 << 9 | 1 << 12);
10231                 if (phy->req_duplex == DUPLEX_FULL)
10232                         an_1000_val |= (1 << 9);
10233                 PMD_DRV_LOG(DEBUG, "Advertising 1G");
10234         } else
10235                 an_1000_val &= ~((1 << 8) | (1 << 9));
10236
10237         elink_cl22_write(sc, phy, 0x09, an_1000_val);
10238         elink_cl22_read(sc, phy, 0x09, &an_1000_val);
10239
10240         /* Advertise 10/100 link speed */
10241         if (phy->req_line_speed == ELINK_SPEED_AUTO_NEG) {
10242                 if (phy->speed_cap_mask &
10243                     PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_HALF) {
10244                         an_10_100_val |= (1 << 5);
10245                         autoneg_val |= (1 << 9 | 1 << 12);
10246                         PMD_DRV_LOG(DEBUG, "Advertising 10M-HD");
10247                 }
10248                 if (phy->speed_cap_mask &
10249                     PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_HALF) {
10250                         an_10_100_val |= (1 << 6);
10251                         autoneg_val |= (1 << 9 | 1 << 12);
10252                         PMD_DRV_LOG(DEBUG, "Advertising 10M-FD");
10253                 }
10254                 if (phy->speed_cap_mask &
10255                     PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_HALF) {
10256                         an_10_100_val |= (1 << 7);
10257                         autoneg_val |= (1 << 9 | 1 << 12);
10258                         PMD_DRV_LOG(DEBUG, "Advertising 100M-HD");
10259                 }
10260                 if (phy->speed_cap_mask &
10261                     PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_FULL) {
10262                         an_10_100_val |= (1 << 8);
10263                         autoneg_val |= (1 << 9 | 1 << 12);
10264                         PMD_DRV_LOG(DEBUG, "Advertising 100M-FD");
10265                 }
10266         }
10267
10268         /* Only 10/100 are allowed to work in FORCE mode */
10269         if (phy->req_line_speed == ELINK_SPEED_100) {
10270                 autoneg_val |= (1 << 13);
10271                 /* Enabled AUTO-MDIX when autoneg is disabled */
10272                 elink_cl22_write(sc, phy, 0x18, (1 << 15 | 1 << 9 | 7 << 0));
10273                 PMD_DRV_LOG(DEBUG, "Setting 100M force");
10274         }
10275         if (phy->req_line_speed == ELINK_SPEED_10) {
10276                 /* Enabled AUTO-MDIX when autoneg is disabled */
10277                 elink_cl22_write(sc, phy, 0x18, (1 << 15 | 1 << 9 | 7 << 0));
10278                 PMD_DRV_LOG(DEBUG, "Setting 10M force");
10279         }
10280
10281         if ((phy->flags & ELINK_FLAGS_EEE) && elink_eee_has_cap(params)) {
10282                 elink_status_t rc;
10283
10284                 elink_cl22_write(sc, phy, MDIO_REG_GPHY_EXP_ACCESS,
10285                                  MDIO_REG_GPHY_EXP_ACCESS_TOP |
10286                                  MDIO_REG_GPHY_EXP_TOP_2K_BUF);
10287                 elink_cl22_read(sc, phy, MDIO_REG_GPHY_EXP_ACCESS_GATE, &temp);
10288                 temp &= 0xfffe;
10289                 elink_cl22_write(sc, phy, MDIO_REG_GPHY_EXP_ACCESS_GATE, temp);
10290
10291                 rc = elink_eee_initial_config(params, vars, SHMEM_EEE_1G_ADV);
10292                 if (rc != ELINK_STATUS_OK) {
10293                         PMD_DRV_LOG(DEBUG, "Failed to configure EEE timers");
10294                         elink_eee_disable(phy, params, vars);
10295                 } else if ((params->eee_mode & ELINK_EEE_MODE_ADV_LPI) &&
10296                            (phy->req_duplex == DUPLEX_FULL) &&
10297                            (elink_eee_calc_timer(params) ||
10298                             !(params->eee_mode & ELINK_EEE_MODE_ENABLE_LPI))) {
10299                         /* Need to advertise EEE only when requested,
10300                          * and either no LPI assertion was requested,
10301                          * or it was requested and a valid timer was set.
10302                          * Also notice full duplex is required for EEE.
10303                          */
10304                         elink_eee_advertise(phy, params, vars,
10305                                             SHMEM_EEE_1G_ADV);
10306                 } else {
10307                         PMD_DRV_LOG(DEBUG, "Don't Advertise 1GBase-T EEE");
10308                         elink_eee_disable(phy, params, vars);
10309                 }
10310         } else {
10311                 vars->eee_status &= ~SHMEM_EEE_1G_ADV <<
10312                     SHMEM_EEE_SUPPORTED_SHIFT;
10313
10314                 if (phy->flags & ELINK_FLAGS_EEE) {
10315                         /* Handle legacy auto-grEEEn */
10316                         if (params->feature_config_flags &
10317                             ELINK_FEATURE_CONFIG_AUTOGREEEN_ENABLED) {
10318                                 temp = 6;
10319                                 PMD_DRV_LOG(DEBUG, "Enabling Auto-GrEEEn");
10320                         } else {
10321                                 temp = 0;
10322                                 PMD_DRV_LOG(DEBUG, "Don't Adv. EEE");
10323                         }
10324                         elink_cl45_write(sc, phy, MDIO_AN_DEVAD,
10325                                          MDIO_AN_REG_EEE_ADV, temp);
10326                 }
10327         }
10328
10329         elink_cl22_write(sc, phy, 0x04, an_10_100_val | fc_val);
10330
10331         if (phy->req_duplex == DUPLEX_FULL)
10332                 autoneg_val |= (1 << 8);
10333
10334         elink_cl22_write(sc, phy, MDIO_PMA_REG_CTRL, autoneg_val);
10335
10336         return ELINK_STATUS_OK;
10337 }
10338
10339 static void elink_5461x_set_link_led(struct elink_phy *phy,
10340                                      struct elink_params *params, uint8_t mode)
10341 {
10342         struct bnx2x_softc *sc = params->sc;
10343         uint16_t temp;
10344
10345         elink_cl22_write(sc, phy,
10346                          MDIO_REG_GPHY_SHADOW, MDIO_REG_GPHY_SHADOW_LED_SEL1);
10347         elink_cl22_read(sc, phy, MDIO_REG_GPHY_SHADOW, &temp);
10348         temp &= 0xff00;
10349
10350         PMD_DRV_LOG(DEBUG, "54618x set link led (mode=%x)", mode);
10351         switch (mode) {
10352         case ELINK_LED_MODE_FRONT_PANEL_OFF:
10353         case ELINK_LED_MODE_OFF:
10354                 temp |= 0x00ee;
10355                 break;
10356         case ELINK_LED_MODE_OPER:
10357                 temp |= 0x0001;
10358                 break;
10359         case ELINK_LED_MODE_ON:
10360                 temp |= 0x00ff;
10361                 break;
10362         default:
10363                 break;
10364         }
10365         elink_cl22_write(sc, phy,
10366                          MDIO_REG_GPHY_SHADOW,
10367                          MDIO_REG_GPHY_SHADOW_WR_ENA | temp);
10368         return;
10369 }
10370
10371 static void elink_54618se_link_reset(struct elink_phy *phy,
10372                                      struct elink_params *params)
10373 {
10374         struct bnx2x_softc *sc = params->sc;
10375         uint32_t cfg_pin;
10376         uint8_t port;
10377
10378         /* In case of no EPIO routed to reset the GPHY, put it
10379          * in low power mode.
10380          */
10381         elink_cl22_write(sc, phy, MDIO_PMA_REG_CTRL, 0x800);
10382         /* This works with E3 only, no need to check the chip
10383          * before determining the port.
10384          */
10385         port = params->port;
10386         cfg_pin = (REG_RD(sc, params->shmem_base +
10387                           offsetof(struct shmem_region,
10388                                    dev_info.port_hw_config[port].
10389                                    e3_cmn_pin_cfg)) &
10390                    PORT_HW_CFG_E3_PHY_RESET_MASK) >>
10391             PORT_HW_CFG_E3_PHY_RESET_SHIFT;
10392
10393         /* Drive pin low to put GPHY in reset. */
10394         elink_set_cfg_pin(sc, cfg_pin, 0);
10395 }
10396
10397 static uint8_t elink_54618se_read_status(struct elink_phy *phy,
10398                                          struct elink_params *params,
10399                                          struct elink_vars *vars)
10400 {
10401         struct bnx2x_softc *sc = params->sc;
10402         uint16_t val;
10403         uint8_t link_up = 0;
10404         uint16_t legacy_status, legacy_speed;
10405
10406         /* Get speed operation status */
10407         elink_cl22_read(sc, phy, MDIO_REG_GPHY_AUX_STATUS, &legacy_status);
10408         PMD_DRV_LOG(DEBUG, "54618SE read_status: 0x%x", legacy_status);
10409
10410         /* Read status to clear the PHY interrupt. */
10411         elink_cl22_read(sc, phy, MDIO_REG_INTR_STATUS, &val);
10412
10413         link_up = ((legacy_status & (1 << 2)) == (1 << 2));
10414
10415         if (link_up) {
10416                 legacy_speed = (legacy_status & (7 << 8));
10417                 if (legacy_speed == (7 << 8)) {
10418                         vars->line_speed = ELINK_SPEED_1000;
10419                         vars->duplex = DUPLEX_FULL;
10420                 } else if (legacy_speed == (6 << 8)) {
10421                         vars->line_speed = ELINK_SPEED_1000;
10422                         vars->duplex = DUPLEX_HALF;
10423                 } else if (legacy_speed == (5 << 8)) {
10424                         vars->line_speed = ELINK_SPEED_100;
10425                         vars->duplex = DUPLEX_FULL;
10426                 }
10427                 /* Omitting 100Base-T4 for now */
10428                 else if (legacy_speed == (3 << 8)) {
10429                         vars->line_speed = ELINK_SPEED_100;
10430                         vars->duplex = DUPLEX_HALF;
10431                 } else if (legacy_speed == (2 << 8)) {
10432                         vars->line_speed = ELINK_SPEED_10;
10433                         vars->duplex = DUPLEX_FULL;
10434                 } else if (legacy_speed == (1 << 8)) {
10435                         vars->line_speed = ELINK_SPEED_10;
10436                         vars->duplex = DUPLEX_HALF;
10437                 } else          /* Should not happen */
10438                         vars->line_speed = 0;
10439
10440                 PMD_DRV_LOG(DEBUG,
10441                             "Link is up in %dMbps, is_duplex_full= %d",
10442                             vars->line_speed, (vars->duplex == DUPLEX_FULL));
10443
10444                 /* Check legacy speed AN resolution */
10445                 elink_cl22_read(sc, phy, 0x01, &val);
10446                 if (val & (1 << 5))
10447                         vars->link_status |=
10448                             LINK_STATUS_AUTO_NEGOTIATE_COMPLETE;
10449                 elink_cl22_read(sc, phy, 0x06, &val);
10450                 if ((val & (1 << 0)) == 0)
10451                         vars->link_status |=
10452                             LINK_STATUS_PARALLEL_DETECTION_USED;
10453
10454                 PMD_DRV_LOG(DEBUG, "BNX2X54618SE: link speed is %d",
10455                             vars->line_speed);
10456
10457                 elink_ext_phy_resolve_fc(phy, params, vars);
10458
10459                 if (vars->link_status & LINK_STATUS_AUTO_NEGOTIATE_COMPLETE) {
10460                         /* Report LP advertised speeds */
10461                         elink_cl22_read(sc, phy, 0x5, &val);
10462
10463                         if (val & (1 << 5))
10464                                 vars->link_status |=
10465                                     LINK_STATUS_LINK_PARTNER_10THD_CAPABLE;
10466                         if (val & (1 << 6))
10467                                 vars->link_status |=
10468                                     LINK_STATUS_LINK_PARTNER_10TFD_CAPABLE;
10469                         if (val & (1 << 7))
10470                                 vars->link_status |=
10471                                     LINK_STATUS_LINK_PARTNER_100TXHD_CAPABLE;
10472                         if (val & (1 << 8))
10473                                 vars->link_status |=
10474                                     LINK_STATUS_LINK_PARTNER_100TXFD_CAPABLE;
10475                         if (val & (1 << 9))
10476                                 vars->link_status |=
10477                                     LINK_STATUS_LINK_PARTNER_100T4_CAPABLE;
10478
10479                         elink_cl22_read(sc, phy, 0xa, &val);
10480                         if (val & (1 << 10))
10481                                 vars->link_status |=
10482                                     LINK_STATUS_LINK_PARTNER_1000THD_CAPABLE;
10483                         if (val & (1 << 11))
10484                                 vars->link_status |=
10485                                     LINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE;
10486
10487                         if ((phy->flags & ELINK_FLAGS_EEE) &&
10488                             elink_eee_has_cap(params))
10489                                 elink_eee_an_resolve(phy, params, vars);
10490                 }
10491         }
10492         return link_up;
10493 }
10494
10495 static void elink_54618se_config_loopback(struct elink_phy *phy,
10496                                           struct elink_params *params)
10497 {
10498         struct bnx2x_softc *sc = params->sc;
10499         uint16_t val;
10500         uint32_t umac_base = params->port ? GRCBASE_UMAC1 : GRCBASE_UMAC0;
10501
10502         PMD_DRV_LOG(DEBUG, "2PMA/PMD ext_phy_loopback: 54618se");
10503
10504         /* Enable master/slave manual mmode and set to master */
10505         /* mii write 9 [bits set 11 12] */
10506         elink_cl22_write(sc, phy, 0x09, 3 << 11);
10507
10508         /* forced 1G and disable autoneg */
10509         /* set val [mii read 0] */
10510         /* set val [expr $val & [bits clear 6 12 13]] */
10511         /* set val [expr $val | [bits set 6 8]] */
10512         /* mii write 0 $val */
10513         elink_cl22_read(sc, phy, 0x00, &val);
10514         val &= ~((1 << 6) | (1 << 12) | (1 << 13));
10515         val |= (1 << 6) | (1 << 8);
10516         elink_cl22_write(sc, phy, 0x00, val);
10517
10518         /* Set external loopback and Tx using 6dB coding */
10519         /* mii write 0x18 7 */
10520         /* set val [mii read 0x18] */
10521         /* mii write 0x18 [expr $val | [bits set 10 15]] */
10522         elink_cl22_write(sc, phy, 0x18, 7);
10523         elink_cl22_read(sc, phy, 0x18, &val);
10524         elink_cl22_write(sc, phy, 0x18, val | (1 << 10) | (1 << 15));
10525
10526         /* This register opens the gate for the UMAC despite its name */
10527         REG_WR(sc, NIG_REG_EGRESS_EMAC0_PORT + params->port * 4, 1);
10528
10529         /* Maximum Frame Length (RW). Defines a 14-Bit maximum frame
10530          * length used by the MAC receive logic to check frames.
10531          */
10532         REG_WR(sc, umac_base + UMAC_REG_MAXFR, 0x2710);
10533 }
10534
10535 /******************************************************************/
10536 /*                      SFX7101 PHY SECTION                       */
10537 /******************************************************************/
10538 static void elink_7101_config_loopback(struct elink_phy *phy,
10539                                        struct elink_params *params)
10540 {
10541         struct bnx2x_softc *sc = params->sc;
10542         /* SFX7101_XGXS_TEST1 */
10543         elink_cl45_write(sc, phy,
10544                          MDIO_XS_DEVAD, MDIO_XS_SFX7101_XGXS_TEST1, 0x100);
10545 }
10546
10547 static uint8_t elink_7101_config_init(struct elink_phy *phy,
10548                                       struct elink_params *params,
10549                                       struct elink_vars *vars)
10550 {
10551         uint16_t fw_ver1, fw_ver2, val;
10552         struct bnx2x_softc *sc = params->sc;
10553         PMD_DRV_LOG(DEBUG, "Setting the SFX7101 LASI indication");
10554
10555         /* Restore normal power mode */
10556         elink_cb_gpio_write(sc, MISC_REGISTERS_GPIO_2,
10557                             MISC_REGISTERS_GPIO_OUTPUT_HIGH, params->port);
10558         /* HW reset */
10559         elink_ext_phy_hw_reset(sc, params->port);
10560         elink_wait_reset_complete(sc, phy, params);
10561
10562         elink_cl45_write(sc, phy, MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, 0x1);
10563         PMD_DRV_LOG(DEBUG, "Setting the SFX7101 LED to blink on traffic");
10564         elink_cl45_write(sc, phy,
10565                          MDIO_PMA_DEVAD, MDIO_PMA_REG_7107_LED_CNTL, (1 << 3));
10566
10567         elink_ext_phy_set_pause(params, phy, vars);
10568         /* Restart autoneg */
10569         elink_cl45_read(sc, phy, MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, &val);
10570         val |= 0x200;
10571         elink_cl45_write(sc, phy, MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, val);
10572
10573         /* Save spirom version */
10574         elink_cl45_read(sc, phy,
10575                         MDIO_PMA_DEVAD, MDIO_PMA_REG_7101_VER1, &fw_ver1);
10576
10577         elink_cl45_read(sc, phy,
10578                         MDIO_PMA_DEVAD, MDIO_PMA_REG_7101_VER2, &fw_ver2);
10579         elink_save_spirom_version(sc, params->port,
10580                                   (uint32_t) (fw_ver1 << 16 | fw_ver2),
10581                                   phy->ver_addr);
10582         return ELINK_STATUS_OK;
10583 }
10584
10585 static uint8_t elink_7101_read_status(struct elink_phy *phy,
10586                                       struct elink_params *params,
10587                                       struct elink_vars *vars)
10588 {
10589         struct bnx2x_softc *sc = params->sc;
10590         uint8_t link_up;
10591         uint16_t val1, val2;
10592         elink_cl45_read(sc, phy, MDIO_PMA_DEVAD, MDIO_PMA_LASI_STAT, &val2);
10593         elink_cl45_read(sc, phy, MDIO_PMA_DEVAD, MDIO_PMA_LASI_STAT, &val1);
10594         PMD_DRV_LOG(DEBUG, "10G-base-T LASI status 0x%x->0x%x", val2, val1);
10595         elink_cl45_read(sc, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_STATUS, &val2);
10596         elink_cl45_read(sc, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_STATUS, &val1);
10597         PMD_DRV_LOG(DEBUG, "10G-base-T PMA status 0x%x->0x%x", val2, val1);
10598         link_up = ((val1 & 4) == 4);
10599         /* If link is up print the AN outcome of the SFX7101 PHY */
10600         if (link_up) {
10601                 elink_cl45_read(sc, phy,
10602                                 MDIO_AN_DEVAD, MDIO_AN_REG_MASTER_STATUS,
10603                                 &val2);
10604                 vars->line_speed = ELINK_SPEED_10000;
10605                 vars->duplex = DUPLEX_FULL;
10606                 PMD_DRV_LOG(DEBUG, "SFX7101 AN status 0x%x->Master=%x",
10607                             val2, (val2 & (1 << 14)));
10608                 elink_ext_phy_10G_an_resolve(sc, phy, vars);
10609                 elink_ext_phy_resolve_fc(phy, params, vars);
10610
10611                 /* Read LP advertised speeds */
10612                 if (val2 & (1 << 11))
10613                         vars->link_status |=
10614                             LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE;
10615         }
10616         return link_up;
10617 }
10618
10619 static uint8_t elink_7101_format_ver(uint32_t spirom_ver, uint8_t * str,
10620                                      uint16_t * len)
10621 {
10622         if (*len < 5)
10623                 return ELINK_STATUS_ERROR;
10624         str[0] = (spirom_ver & 0xFF);
10625         str[1] = (spirom_ver & 0xFF00) >> 8;
10626         str[2] = (spirom_ver & 0xFF0000) >> 16;
10627         str[3] = (spirom_ver & 0xFF000000) >> 24;
10628         str[4] = '\0';
10629         *len -= 5;
10630         return ELINK_STATUS_OK;
10631 }
10632
10633 static void elink_7101_hw_reset(__rte_unused struct elink_phy *phy,
10634                                 struct elink_params *params)
10635 {
10636         /* Low power mode is controlled by GPIO 2 */
10637         elink_cb_gpio_write(params->sc, MISC_REGISTERS_GPIO_2,
10638                             MISC_REGISTERS_GPIO_OUTPUT_LOW, params->port);
10639         /* The PHY reset is controlled by GPIO 1 */
10640         elink_cb_gpio_write(params->sc, MISC_REGISTERS_GPIO_1,
10641                             MISC_REGISTERS_GPIO_OUTPUT_LOW, params->port);
10642 }
10643
10644 static void elink_7101_set_link_led(struct elink_phy *phy,
10645                                     struct elink_params *params, uint8_t mode)
10646 {
10647         uint16_t val = 0;
10648         struct bnx2x_softc *sc = params->sc;
10649         switch (mode) {
10650         case ELINK_LED_MODE_FRONT_PANEL_OFF:
10651         case ELINK_LED_MODE_OFF:
10652                 val = 2;
10653                 break;
10654         case ELINK_LED_MODE_ON:
10655                 val = 1;
10656                 break;
10657         case ELINK_LED_MODE_OPER:
10658                 val = 0;
10659                 break;
10660         }
10661         elink_cl45_write(sc, phy,
10662                          MDIO_PMA_DEVAD, MDIO_PMA_REG_7107_LINK_LED_CNTL, val);
10663 }
10664
10665 /******************************************************************/
10666 /*                      STATIC PHY DECLARATION                    */
10667 /******************************************************************/
10668
10669 static const struct elink_phy phy_null = {
10670         .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN,
10671         .addr = 0,
10672         .def_md_devad = 0,
10673         .flags = ELINK_FLAGS_INIT_XGXS_FIRST,
10674         .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
10675         .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
10676         .mdio_ctrl = 0,
10677         .supported = 0,
10678         .media_type = ELINK_ETH_PHY_NOT_PRESENT,
10679         .ver_addr = 0,
10680         .req_flow_ctrl = 0,
10681         .req_line_speed = 0,
10682         .speed_cap_mask = 0,
10683         .req_duplex = 0,
10684         .rsrv = 0,
10685         .config_init = NULL,
10686         .read_status = NULL,
10687         .link_reset = NULL,
10688         .config_loopback = NULL,
10689         .format_fw_ver = NULL,
10690         .hw_reset = NULL,
10691         .set_link_led = NULL,
10692         .phy_specific_func = NULL
10693 };
10694
10695 static const struct elink_phy phy_serdes = {
10696         .type = PORT_HW_CFG_SERDES_EXT_PHY_TYPE_DIRECT,
10697         .addr = 0xff,
10698         .def_md_devad = 0,
10699         .flags = 0,
10700         .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
10701         .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
10702         .mdio_ctrl = 0,
10703         .supported = (ELINK_SUPPORTED_10baseT_Half |
10704                       ELINK_SUPPORTED_10baseT_Full |
10705                       ELINK_SUPPORTED_100baseT_Half |
10706                       ELINK_SUPPORTED_100baseT_Full |
10707                       ELINK_SUPPORTED_1000baseT_Full |
10708                       ELINK_SUPPORTED_2500baseX_Full |
10709                       ELINK_SUPPORTED_TP |
10710                       ELINK_SUPPORTED_Autoneg |
10711                       ELINK_SUPPORTED_Pause | ELINK_SUPPORTED_Asym_Pause),
10712         .media_type = ELINK_ETH_PHY_BASE_T,
10713         .ver_addr = 0,
10714         .req_flow_ctrl = 0,
10715         .req_line_speed = 0,
10716         .speed_cap_mask = 0,
10717         .req_duplex = 0,
10718         .rsrv = 0,
10719         .config_init = elink_xgxs_config_init,
10720         .read_status = elink_link_settings_status,
10721         .link_reset = elink_int_link_reset,
10722         .config_loopback = NULL,
10723         .format_fw_ver = NULL,
10724         .hw_reset = NULL,
10725         .set_link_led = NULL,
10726         .phy_specific_func = NULL
10727 };
10728
10729 static const struct elink_phy phy_xgxs = {
10730         .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT,
10731         .addr = 0xff,
10732         .def_md_devad = 0,
10733         .flags = 0,
10734         .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
10735         .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
10736         .mdio_ctrl = 0,
10737         .supported = (ELINK_SUPPORTED_10baseT_Half |
10738                       ELINK_SUPPORTED_10baseT_Full |
10739                       ELINK_SUPPORTED_100baseT_Half |
10740                       ELINK_SUPPORTED_100baseT_Full |
10741                       ELINK_SUPPORTED_1000baseT_Full |
10742                       ELINK_SUPPORTED_2500baseX_Full |
10743                       ELINK_SUPPORTED_10000baseT_Full |
10744                       ELINK_SUPPORTED_FIBRE |
10745                       ELINK_SUPPORTED_Autoneg |
10746                       ELINK_SUPPORTED_Pause | ELINK_SUPPORTED_Asym_Pause),
10747         .media_type = ELINK_ETH_PHY_CX4,
10748         .ver_addr = 0,
10749         .req_flow_ctrl = 0,
10750         .req_line_speed = 0,
10751         .speed_cap_mask = 0,
10752         .req_duplex = 0,
10753         .rsrv = 0,
10754         .config_init = elink_xgxs_config_init,
10755         .read_status = elink_link_settings_status,
10756         .link_reset = elink_int_link_reset,
10757         .config_loopback = elink_set_xgxs_loopback,
10758         .format_fw_ver = NULL,
10759         .hw_reset = NULL,
10760         .set_link_led = NULL,
10761         .phy_specific_func = elink_xgxs_specific_func
10762 };
10763
10764 static const struct elink_phy phy_warpcore = {
10765         .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT,
10766         .addr = 0xff,
10767         .def_md_devad = 0,
10768         .flags = ELINK_FLAGS_TX_ERROR_CHECK,
10769         .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
10770         .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
10771         .mdio_ctrl = 0,
10772         .supported = (ELINK_SUPPORTED_10baseT_Half |
10773                       ELINK_SUPPORTED_10baseT_Full |
10774                       ELINK_SUPPORTED_100baseT_Half |
10775                       ELINK_SUPPORTED_100baseT_Full |
10776                       ELINK_SUPPORTED_1000baseT_Full |
10777                       ELINK_SUPPORTED_10000baseT_Full |
10778                       ELINK_SUPPORTED_20000baseKR2_Full |
10779                       ELINK_SUPPORTED_20000baseMLD2_Full |
10780                       ELINK_SUPPORTED_FIBRE |
10781                       ELINK_SUPPORTED_Autoneg |
10782                       ELINK_SUPPORTED_Pause | ELINK_SUPPORTED_Asym_Pause),
10783         .media_type = ELINK_ETH_PHY_UNSPECIFIED,
10784         .ver_addr = 0,
10785         .req_flow_ctrl = 0,
10786         .req_line_speed = 0,
10787         .speed_cap_mask = 0,
10788         /* req_duplex = */ 0,
10789         /* rsrv = */ 0,
10790         .config_init = elink_warpcore_config_init,
10791         .read_status = elink_warpcore_read_status,
10792         .link_reset = elink_warpcore_link_reset,
10793         .config_loopback = elink_set_warpcore_loopback,
10794         .format_fw_ver = NULL,
10795         .hw_reset = elink_warpcore_hw_reset,
10796         .set_link_led = NULL,
10797         .phy_specific_func = NULL
10798 };
10799
10800 static const struct elink_phy phy_7101 = {
10801         .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101,
10802         .addr = 0xff,
10803         .def_md_devad = 0,
10804         .flags = ELINK_FLAGS_FAN_FAILURE_DET_REQ,
10805         .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
10806         .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
10807         .mdio_ctrl = 0,
10808         .supported = (ELINK_SUPPORTED_10000baseT_Full |
10809                       ELINK_SUPPORTED_TP |
10810                       ELINK_SUPPORTED_Autoneg |
10811                       ELINK_SUPPORTED_Pause | ELINK_SUPPORTED_Asym_Pause),
10812         .media_type = ELINK_ETH_PHY_BASE_T,
10813         .ver_addr = 0,
10814         .req_flow_ctrl = 0,
10815         .req_line_speed = 0,
10816         .speed_cap_mask = 0,
10817         .req_duplex = 0,
10818         .rsrv = 0,
10819         .config_init = elink_7101_config_init,
10820         .read_status = elink_7101_read_status,
10821         .link_reset = elink_common_ext_link_reset,
10822         .config_loopback = elink_7101_config_loopback,
10823         .format_fw_ver = elink_7101_format_ver,
10824         .hw_reset = elink_7101_hw_reset,
10825         .set_link_led = elink_7101_set_link_led,
10826         .phy_specific_func = NULL
10827 };
10828
10829 static const struct elink_phy phy_8073 = {
10830         .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X8073,
10831         .addr = 0xff,
10832         .def_md_devad = 0,
10833         .flags = 0,
10834         .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
10835         .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
10836         .mdio_ctrl = 0,
10837         .supported = (ELINK_SUPPORTED_10000baseT_Full |
10838                       ELINK_SUPPORTED_2500baseX_Full |
10839                       ELINK_SUPPORTED_1000baseT_Full |
10840                       ELINK_SUPPORTED_FIBRE |
10841                       ELINK_SUPPORTED_Autoneg |
10842                       ELINK_SUPPORTED_Pause | ELINK_SUPPORTED_Asym_Pause),
10843         .media_type = ELINK_ETH_PHY_KR,
10844         .ver_addr = 0,
10845         .req_flow_ctrl = 0,
10846         .req_line_speed = 0,
10847         .speed_cap_mask = 0,
10848         .req_duplex = 0,
10849         .rsrv = 0,
10850         .config_init = elink_8073_config_init,
10851         .read_status = elink_8073_read_status,
10852         .link_reset = elink_8073_link_reset,
10853         .config_loopback = NULL,
10854         .format_fw_ver = elink_format_ver,
10855         .hw_reset = NULL,
10856         .set_link_led = NULL,
10857         .phy_specific_func = elink_8073_specific_func
10858 };
10859
10860 static const struct elink_phy phy_8705 = {
10861         .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X8705,
10862         .addr = 0xff,
10863         .def_md_devad = 0,
10864         .flags = ELINK_FLAGS_INIT_XGXS_FIRST,
10865         .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
10866         .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
10867         .mdio_ctrl = 0,
10868         .supported = (ELINK_SUPPORTED_10000baseT_Full |
10869                       ELINK_SUPPORTED_FIBRE |
10870                       ELINK_SUPPORTED_Pause | ELINK_SUPPORTED_Asym_Pause),
10871         .media_type = ELINK_ETH_PHY_XFP_FIBER,
10872         .ver_addr = 0,
10873         .req_flow_ctrl = 0,
10874         .req_line_speed = 0,
10875         .speed_cap_mask = 0,
10876         .req_duplex = 0,
10877         .rsrv = 0,
10878         .config_init = elink_8705_config_init,
10879         .read_status = elink_8705_read_status,
10880         .link_reset = elink_common_ext_link_reset,
10881         .config_loopback = NULL,
10882         .format_fw_ver = elink_null_format_ver,
10883         .hw_reset = NULL,
10884         .set_link_led = NULL,
10885         .phy_specific_func = NULL
10886 };
10887
10888 static const struct elink_phy phy_8706 = {
10889         .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X8706,
10890         .addr = 0xff,
10891         .def_md_devad = 0,
10892         .flags = ELINK_FLAGS_INIT_XGXS_FIRST,
10893         .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
10894         .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
10895         .mdio_ctrl = 0,
10896         .supported = (ELINK_SUPPORTED_10000baseT_Full |
10897                       ELINK_SUPPORTED_1000baseT_Full |
10898                       ELINK_SUPPORTED_FIBRE |
10899                       ELINK_SUPPORTED_Pause | ELINK_SUPPORTED_Asym_Pause),
10900         .media_type = ELINK_ETH_PHY_SFPP_10G_FIBER,
10901         .ver_addr = 0,
10902         .req_flow_ctrl = 0,
10903         .req_line_speed = 0,
10904         .speed_cap_mask = 0,
10905         .req_duplex = 0,
10906         .rsrv = 0,
10907         .config_init = elink_8706_config_init,
10908         .read_status = elink_8706_read_status,
10909         .link_reset = elink_common_ext_link_reset,
10910         .config_loopback = NULL,
10911         .format_fw_ver = elink_format_ver,
10912         .hw_reset = NULL,
10913         .set_link_led = NULL,
10914         .phy_specific_func = NULL
10915 };
10916
10917 static const struct elink_phy phy_8726 = {
10918         .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X8726,
10919         .addr = 0xff,
10920         .def_md_devad = 0,
10921         .flags = (ELINK_FLAGS_INIT_XGXS_FIRST | ELINK_FLAGS_TX_ERROR_CHECK),
10922         .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
10923         .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
10924         .mdio_ctrl = 0,
10925         .supported = (ELINK_SUPPORTED_10000baseT_Full |
10926                       ELINK_SUPPORTED_1000baseT_Full |
10927                       ELINK_SUPPORTED_Autoneg |
10928                       ELINK_SUPPORTED_FIBRE |
10929                       ELINK_SUPPORTED_Pause | ELINK_SUPPORTED_Asym_Pause),
10930         .media_type = ELINK_ETH_PHY_NOT_PRESENT,
10931         .ver_addr = 0,
10932         .req_flow_ctrl = 0,
10933         .req_line_speed = 0,
10934         .speed_cap_mask = 0,
10935         .req_duplex = 0,
10936         .rsrv = 0,
10937         .config_init = elink_8726_config_init,
10938         .read_status = elink_8726_read_status,
10939         .link_reset = elink_8726_link_reset,
10940         .config_loopback = elink_8726_config_loopback,
10941         .format_fw_ver = elink_format_ver,
10942         .hw_reset = NULL,
10943         .set_link_led = NULL,
10944         .phy_specific_func = NULL
10945 };
10946
10947 static const struct elink_phy phy_8727 = {
10948         .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X8727,
10949         .addr = 0xff,
10950         .def_md_devad = 0,
10951         .flags = (ELINK_FLAGS_FAN_FAILURE_DET_REQ | ELINK_FLAGS_TX_ERROR_CHECK),
10952         .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
10953         .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
10954         .mdio_ctrl = 0,
10955         .supported = (ELINK_SUPPORTED_10000baseT_Full |
10956                       ELINK_SUPPORTED_1000baseT_Full |
10957                       ELINK_SUPPORTED_FIBRE |
10958                       ELINK_SUPPORTED_Pause | ELINK_SUPPORTED_Asym_Pause),
10959         .media_type = ELINK_ETH_PHY_NOT_PRESENT,
10960         .ver_addr = 0,
10961         .req_flow_ctrl = 0,
10962         .req_line_speed = 0,
10963         .speed_cap_mask = 0,
10964         .req_duplex = 0,
10965         .rsrv = 0,
10966         .config_init = elink_8727_config_init,
10967         .read_status = elink_8727_read_status,
10968         .link_reset = elink_8727_link_reset,
10969         .config_loopback = NULL,
10970         .format_fw_ver = elink_format_ver,
10971         .hw_reset = elink_8727_hw_reset,
10972         .set_link_led = elink_8727_set_link_led,
10973         .phy_specific_func = elink_8727_specific_func
10974 };
10975
10976 static const struct elink_phy phy_8481 = {
10977         .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X8481,
10978         .addr = 0xff,
10979         .def_md_devad = 0,
10980         .flags = ELINK_FLAGS_FAN_FAILURE_DET_REQ |
10981             ELINK_FLAGS_REARM_LATCH_SIGNAL,
10982         .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
10983         .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
10984         .mdio_ctrl = 0,
10985         .supported = (ELINK_SUPPORTED_10baseT_Half |
10986                       ELINK_SUPPORTED_10baseT_Full |
10987                       ELINK_SUPPORTED_100baseT_Half |
10988                       ELINK_SUPPORTED_100baseT_Full |
10989                       ELINK_SUPPORTED_1000baseT_Full |
10990                       ELINK_SUPPORTED_10000baseT_Full |
10991                       ELINK_SUPPORTED_TP |
10992                       ELINK_SUPPORTED_Autoneg |
10993                       ELINK_SUPPORTED_Pause | ELINK_SUPPORTED_Asym_Pause),
10994         .media_type = ELINK_ETH_PHY_BASE_T,
10995         .ver_addr = 0,
10996         .req_flow_ctrl = 0,
10997         .req_line_speed = 0,
10998         .speed_cap_mask = 0,
10999         .req_duplex = 0,
11000         .rsrv = 0,
11001         .config_init = elink_8481_config_init,
11002         .read_status = elink_848xx_read_status,
11003         .link_reset = elink_8481_link_reset,
11004         .config_loopback = NULL,
11005         .format_fw_ver = elink_848xx_format_ver,
11006         .hw_reset = elink_8481_hw_reset,
11007         .set_link_led = elink_848xx_set_link_led,
11008         .phy_specific_func = NULL
11009 };
11010
11011 static const struct elink_phy phy_84823 = {
11012         .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X84823,
11013         .addr = 0xff,
11014         .def_md_devad = 0,
11015         .flags = (ELINK_FLAGS_FAN_FAILURE_DET_REQ |
11016                   ELINK_FLAGS_REARM_LATCH_SIGNAL | ELINK_FLAGS_TX_ERROR_CHECK),
11017         .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11018         .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11019         .mdio_ctrl = 0,
11020         .supported = (ELINK_SUPPORTED_10baseT_Half |
11021                       ELINK_SUPPORTED_10baseT_Full |
11022                       ELINK_SUPPORTED_100baseT_Half |
11023                       ELINK_SUPPORTED_100baseT_Full |
11024                       ELINK_SUPPORTED_1000baseT_Full |
11025                       ELINK_SUPPORTED_10000baseT_Full |
11026                       ELINK_SUPPORTED_TP |
11027                       ELINK_SUPPORTED_Autoneg |
11028                       ELINK_SUPPORTED_Pause | ELINK_SUPPORTED_Asym_Pause),
11029         .media_type = ELINK_ETH_PHY_BASE_T,
11030         .ver_addr = 0,
11031         .req_flow_ctrl = 0,
11032         .req_line_speed = 0,
11033         .speed_cap_mask = 0,
11034         .req_duplex = 0,
11035         .rsrv = 0,
11036         .config_init = elink_848x3_config_init,
11037         .read_status = elink_848xx_read_status,
11038         .link_reset = elink_848x3_link_reset,
11039         .config_loopback = NULL,
11040         .format_fw_ver = elink_848xx_format_ver,
11041         .hw_reset = NULL,
11042         .set_link_led = elink_848xx_set_link_led,
11043         .phy_specific_func = elink_848xx_specific_func
11044 };
11045
11046 static const struct elink_phy phy_84833 = {
11047         .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X84833,
11048         .addr = 0xff,
11049         .def_md_devad = 0,
11050         .flags = (ELINK_FLAGS_FAN_FAILURE_DET_REQ |
11051                   ELINK_FLAGS_REARM_LATCH_SIGNAL |
11052                   ELINK_FLAGS_TX_ERROR_CHECK | ELINK_FLAGS_TEMPERATURE),
11053         .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11054         .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11055         .mdio_ctrl = 0,
11056         .supported = (ELINK_SUPPORTED_100baseT_Half |
11057                       ELINK_SUPPORTED_100baseT_Full |
11058                       ELINK_SUPPORTED_1000baseT_Full |
11059                       ELINK_SUPPORTED_10000baseT_Full |
11060                       ELINK_SUPPORTED_TP |
11061                       ELINK_SUPPORTED_Autoneg |
11062                       ELINK_SUPPORTED_Pause | ELINK_SUPPORTED_Asym_Pause),
11063         .media_type = ELINK_ETH_PHY_BASE_T,
11064         .ver_addr = 0,
11065         .req_flow_ctrl = 0,
11066         .req_line_speed = 0,
11067         .speed_cap_mask = 0,
11068         .req_duplex = 0,
11069         .rsrv = 0,
11070         .config_init = elink_848x3_config_init,
11071         .read_status = elink_848xx_read_status,
11072         .link_reset = elink_848x3_link_reset,
11073         .config_loopback = NULL,
11074         .format_fw_ver = elink_848xx_format_ver,
11075         .hw_reset = elink_84833_hw_reset_phy,
11076         .set_link_led = elink_848xx_set_link_led,
11077         .phy_specific_func = elink_848xx_specific_func
11078 };
11079
11080 static const struct elink_phy phy_84834 = {
11081         .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X84834,
11082         .addr = 0xff,
11083         .def_md_devad = 0,
11084         .flags = ELINK_FLAGS_FAN_FAILURE_DET_REQ |
11085             ELINK_FLAGS_REARM_LATCH_SIGNAL,
11086         .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11087         .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11088         .mdio_ctrl = 0,
11089         .supported = (ELINK_SUPPORTED_100baseT_Half |
11090                       ELINK_SUPPORTED_100baseT_Full |
11091                       ELINK_SUPPORTED_1000baseT_Full |
11092                       ELINK_SUPPORTED_10000baseT_Full |
11093                       ELINK_SUPPORTED_TP |
11094                       ELINK_SUPPORTED_Autoneg |
11095                       ELINK_SUPPORTED_Pause | ELINK_SUPPORTED_Asym_Pause),
11096         .media_type = ELINK_ETH_PHY_BASE_T,
11097         .ver_addr = 0,
11098         .req_flow_ctrl = 0,
11099         .req_line_speed = 0,
11100         .speed_cap_mask = 0,
11101         .req_duplex = 0,
11102         .rsrv = 0,
11103         .config_init = elink_848x3_config_init,
11104         .read_status = elink_848xx_read_status,
11105         .link_reset = elink_848x3_link_reset,
11106         .config_loopback = NULL,
11107         .format_fw_ver = elink_848xx_format_ver,
11108         .hw_reset = elink_84833_hw_reset_phy,
11109         .set_link_led = elink_848xx_set_link_led,
11110         .phy_specific_func = elink_848xx_specific_func
11111 };
11112
11113 static const struct elink_phy phy_54618se = {
11114         .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X54618SE,
11115         .addr = 0xff,
11116         .def_md_devad = 0,
11117         .flags = ELINK_FLAGS_INIT_XGXS_FIRST,
11118         .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11119         .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11120         .mdio_ctrl = 0,
11121         .supported = (ELINK_SUPPORTED_10baseT_Half |
11122                       ELINK_SUPPORTED_10baseT_Full |
11123                       ELINK_SUPPORTED_100baseT_Half |
11124                       ELINK_SUPPORTED_100baseT_Full |
11125                       ELINK_SUPPORTED_1000baseT_Full |
11126                       ELINK_SUPPORTED_TP |
11127                       ELINK_SUPPORTED_Autoneg |
11128                       ELINK_SUPPORTED_Pause | ELINK_SUPPORTED_Asym_Pause),
11129         .media_type = ELINK_ETH_PHY_BASE_T,
11130         .ver_addr = 0,
11131         .req_flow_ctrl = 0,
11132         .req_line_speed = 0,
11133         .speed_cap_mask = 0,
11134         /* req_duplex = */ 0,
11135         /* rsrv = */ 0,
11136         .config_init = elink_54618se_config_init,
11137         .read_status = elink_54618se_read_status,
11138         .link_reset = elink_54618se_link_reset,
11139         .config_loopback = elink_54618se_config_loopback,
11140         .format_fw_ver = NULL,
11141         .hw_reset = NULL,
11142         .set_link_led = elink_5461x_set_link_led,
11143         .phy_specific_func = elink_54618se_specific_func
11144 };
11145
11146 /*****************************************************************/
11147 /*                                                               */
11148 /* Populate the phy according. Main function: elink_populate_phy   */
11149 /*                                                               */
11150 /*****************************************************************/
11151
11152 static void elink_populate_preemphasis(struct bnx2x_softc *sc,
11153                                        uint32_t shmem_base,
11154                                        struct elink_phy *phy, uint8_t port,
11155                                        uint8_t phy_index)
11156 {
11157         /* Get the 4 lanes xgxs config rx and tx */
11158         uint32_t rx = 0, tx = 0, i;
11159         for (i = 0; i < 2; i++) {
11160                 /* INT_PHY and ELINK_EXT_PHY1 share the same value location in
11161                  * the shmem. When num_phys is greater than 1, than this value
11162                  * applies only to ELINK_EXT_PHY1
11163                  */
11164                 if (phy_index == ELINK_INT_PHY || phy_index == ELINK_EXT_PHY1) {
11165                         rx = REG_RD(sc, shmem_base +
11166                                     offsetof(struct shmem_region,
11167                                              dev_info.port_hw_config[port].
11168                                              xgxs_config_rx[i << 1]));
11169
11170                         tx = REG_RD(sc, shmem_base +
11171                                     offsetof(struct shmem_region,
11172                                              dev_info.port_hw_config[port].
11173                                              xgxs_config_tx[i << 1]));
11174                 } else {
11175                         rx = REG_RD(sc, shmem_base +
11176                                     offsetof(struct shmem_region,
11177                                              dev_info.port_hw_config[port].
11178                                              xgxs_config2_rx[i << 1]));
11179
11180                         tx = REG_RD(sc, shmem_base +
11181                                     offsetof(struct shmem_region,
11182                                              dev_info.port_hw_config[port].
11183                                              xgxs_config2_rx[i << 1]));
11184                 }
11185
11186                 phy->rx_preemphasis[i << 1] = ((rx >> 16) & 0xffff);
11187                 phy->rx_preemphasis[(i << 1) + 1] = (rx & 0xffff);
11188
11189                 phy->tx_preemphasis[i << 1] = ((tx >> 16) & 0xffff);
11190                 phy->tx_preemphasis[(i << 1) + 1] = (tx & 0xffff);
11191         }
11192 }
11193
11194 static uint32_t elink_get_ext_phy_config(struct bnx2x_softc *sc,
11195                                          uint32_t shmem_base, uint8_t phy_index,
11196                                          uint8_t port)
11197 {
11198         uint32_t ext_phy_config = 0;
11199         switch (phy_index) {
11200         case ELINK_EXT_PHY1:
11201                 ext_phy_config = REG_RD(sc, shmem_base +
11202                                         offsetof(struct shmem_region,
11203                                                  dev_info.port_hw_config[port].
11204                                                  external_phy_config));
11205                 break;
11206         case ELINK_EXT_PHY2:
11207                 ext_phy_config = REG_RD(sc, shmem_base +
11208                                         offsetof(struct shmem_region,
11209                                                  dev_info.port_hw_config[port].
11210                                                  external_phy_config2));
11211                 break;
11212         default:
11213                 PMD_DRV_LOG(DEBUG, "Invalid phy_index %d", phy_index);
11214                 return ELINK_STATUS_ERROR;
11215         }
11216
11217         return ext_phy_config;
11218 }
11219
11220 static elink_status_t elink_populate_int_phy(struct bnx2x_softc *sc,
11221                                              uint32_t shmem_base, uint8_t port,
11222                                              struct elink_phy *phy)
11223 {
11224         uint32_t phy_addr;
11225         __rte_unused uint32_t chip_id;
11226         uint32_t switch_cfg = (REG_RD(sc, shmem_base +
11227                                       offsetof(struct shmem_region,
11228                                                dev_info.
11229                                                port_feature_config[port].
11230                                                link_config)) &
11231                                PORT_FEATURE_CONNECTED_SWITCH_MASK);
11232         chip_id =
11233             (REG_RD(sc, MISC_REG_CHIP_NUM) << 16) |
11234             ((REG_RD(sc, MISC_REG_CHIP_REV) & 0xf) << 12);
11235
11236         PMD_DRV_LOG(DEBUG, ":chip_id = 0x%x", chip_id);
11237         if (USES_WARPCORE(sc)) {
11238                 uint32_t serdes_net_if;
11239                 phy_addr = REG_RD(sc, MISC_REG_WC0_CTRL_PHY_ADDR);
11240                 *phy = phy_warpcore;
11241                 if (REG_RD(sc, MISC_REG_PORT4MODE_EN_OVWR) == 0x3)
11242                         phy->flags |= ELINK_FLAGS_4_PORT_MODE;
11243                 else
11244                         phy->flags &= ~ELINK_FLAGS_4_PORT_MODE;
11245                 /* Check Dual mode */
11246                 serdes_net_if = (REG_RD(sc, shmem_base +
11247                                         offsetof(struct shmem_region,
11248                                                  dev_info.port_hw_config[port].
11249                                                  default_cfg)) &
11250                                  PORT_HW_CFG_NET_SERDES_IF_MASK);
11251                 /* Set the appropriate supported and flags indications per
11252                  * interface type of the chip
11253                  */
11254                 switch (serdes_net_if) {
11255                 case PORT_HW_CFG_NET_SERDES_IF_SGMII:
11256                         phy->supported &= (ELINK_SUPPORTED_10baseT_Half |
11257                                            ELINK_SUPPORTED_10baseT_Full |
11258                                            ELINK_SUPPORTED_100baseT_Half |
11259                                            ELINK_SUPPORTED_100baseT_Full |
11260                                            ELINK_SUPPORTED_1000baseT_Full |
11261                                            ELINK_SUPPORTED_FIBRE |
11262                                            ELINK_SUPPORTED_Autoneg |
11263                                            ELINK_SUPPORTED_Pause |
11264                                            ELINK_SUPPORTED_Asym_Pause);
11265                         phy->media_type = ELINK_ETH_PHY_BASE_T;
11266                         break;
11267                 case PORT_HW_CFG_NET_SERDES_IF_XFI:
11268                         phy->supported &= (ELINK_SUPPORTED_1000baseT_Full |
11269                                            ELINK_SUPPORTED_10000baseT_Full |
11270                                            ELINK_SUPPORTED_FIBRE |
11271                                            ELINK_SUPPORTED_Pause |
11272                                            ELINK_SUPPORTED_Asym_Pause);
11273                         phy->media_type = ELINK_ETH_PHY_XFP_FIBER;
11274                         break;
11275                 case PORT_HW_CFG_NET_SERDES_IF_SFI:
11276                         phy->supported &= (ELINK_SUPPORTED_1000baseT_Full |
11277                                            ELINK_SUPPORTED_10000baseT_Full |
11278                                            ELINK_SUPPORTED_FIBRE |
11279                                            ELINK_SUPPORTED_Pause |
11280                                            ELINK_SUPPORTED_Asym_Pause);
11281                         phy->media_type = ELINK_ETH_PHY_SFPP_10G_FIBER;
11282                         break;
11283                 case PORT_HW_CFG_NET_SERDES_IF_KR:
11284                         phy->media_type = ELINK_ETH_PHY_KR;
11285                         phy->supported &= (ELINK_SUPPORTED_1000baseT_Full |
11286                                            ELINK_SUPPORTED_10000baseT_Full |
11287                                            ELINK_SUPPORTED_FIBRE |
11288                                            ELINK_SUPPORTED_Autoneg |
11289                                            ELINK_SUPPORTED_Pause |
11290                                            ELINK_SUPPORTED_Asym_Pause);
11291                         break;
11292                 case PORT_HW_CFG_NET_SERDES_IF_DXGXS:
11293                         phy->media_type = ELINK_ETH_PHY_KR;
11294                         phy->flags |= ELINK_FLAGS_WC_DUAL_MODE;
11295                         phy->supported &= (ELINK_SUPPORTED_20000baseMLD2_Full |
11296                                            ELINK_SUPPORTED_FIBRE |
11297                                            ELINK_SUPPORTED_Pause |
11298                                            ELINK_SUPPORTED_Asym_Pause);
11299                         break;
11300                 case PORT_HW_CFG_NET_SERDES_IF_KR2:
11301                         phy->media_type = ELINK_ETH_PHY_KR;
11302                         phy->flags |= ELINK_FLAGS_WC_DUAL_MODE;
11303                         phy->supported &= (ELINK_SUPPORTED_20000baseKR2_Full |
11304                                            ELINK_SUPPORTED_10000baseT_Full |
11305                                            ELINK_SUPPORTED_1000baseT_Full |
11306                                            ELINK_SUPPORTED_Autoneg |
11307                                            ELINK_SUPPORTED_FIBRE |
11308                                            ELINK_SUPPORTED_Pause |
11309                                            ELINK_SUPPORTED_Asym_Pause);
11310                         phy->flags &= ~ELINK_FLAGS_TX_ERROR_CHECK;
11311                         break;
11312                 default:
11313                         PMD_DRV_LOG(DEBUG, "Unknown WC interface type 0x%x",
11314                                     serdes_net_if);
11315                         break;
11316                 }
11317
11318                 /* Enable MDC/MDIO work-around for E3 A0 since free running MDC
11319                  * was not set as expected. For B0, ECO will be enabled so there
11320                  * won't be an issue there
11321                  */
11322                 if (CHIP_REV(sc) == CHIP_REV_Ax)
11323                         phy->flags |= ELINK_FLAGS_MDC_MDIO_WA;
11324                 else
11325                         phy->flags |= ELINK_FLAGS_MDC_MDIO_WA_B0;
11326         } else {
11327                 switch (switch_cfg) {
11328                 case ELINK_SWITCH_CFG_1G:
11329                         phy_addr = REG_RD(sc,
11330                                           NIG_REG_SERDES0_CTRL_PHY_ADDR +
11331                                           port * 0x10);
11332                         *phy = phy_serdes;
11333                         break;
11334                 case ELINK_SWITCH_CFG_10G:
11335                         phy_addr = REG_RD(sc,
11336                                           NIG_REG_XGXS0_CTRL_PHY_ADDR +
11337                                           port * 0x18);
11338                         *phy = phy_xgxs;
11339                         break;
11340                 default:
11341                         PMD_DRV_LOG(DEBUG, "Invalid switch_cfg");
11342                         return ELINK_STATUS_ERROR;
11343                 }
11344         }
11345         phy->addr = (uint8_t) phy_addr;
11346         phy->mdio_ctrl = elink_get_emac_base(sc,
11347                                              SHARED_HW_CFG_MDC_MDIO_ACCESS1_BOTH,
11348                                              port);
11349         if (CHIP_IS_E2(sc))
11350                 phy->def_md_devad = ELINK_E2_DEFAULT_PHY_DEV_ADDR;
11351         else
11352                 phy->def_md_devad = ELINK_DEFAULT_PHY_DEV_ADDR;
11353
11354         PMD_DRV_LOG(DEBUG, "Internal phy port=%d, addr=0x%x, mdio_ctl=0x%x",
11355                     port, phy->addr, phy->mdio_ctrl);
11356
11357         elink_populate_preemphasis(sc, shmem_base, phy, port, ELINK_INT_PHY);
11358         return ELINK_STATUS_OK;
11359 }
11360
11361 static elink_status_t elink_populate_ext_phy(struct bnx2x_softc *sc,
11362                                              uint8_t phy_index,
11363                                              uint32_t shmem_base,
11364                                              uint32_t shmem2_base,
11365                                              uint8_t port,
11366                                              struct elink_phy *phy)
11367 {
11368         uint32_t ext_phy_config, phy_type, config2;
11369         uint32_t mdc_mdio_access = SHARED_HW_CFG_MDC_MDIO_ACCESS1_BOTH;
11370         ext_phy_config = elink_get_ext_phy_config(sc, shmem_base,
11371                                                   phy_index, port);
11372         phy_type = ELINK_XGXS_EXT_PHY_TYPE(ext_phy_config);
11373         /* Select the phy type */
11374         switch (phy_type) {
11375         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X8073:
11376                 mdc_mdio_access = SHARED_HW_CFG_MDC_MDIO_ACCESS1_SWAPPED;
11377                 *phy = phy_8073;
11378                 break;
11379         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X8705:
11380                 *phy = phy_8705;
11381                 break;
11382         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X8706:
11383                 *phy = phy_8706;
11384                 break;
11385         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X8726:
11386                 mdc_mdio_access = SHARED_HW_CFG_MDC_MDIO_ACCESS1_EMAC1;
11387                 *phy = phy_8726;
11388                 break;
11389         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X8727_NOC:
11390                 /* BNX2X8727_NOC => BNX2X8727 no over current */
11391                 mdc_mdio_access = SHARED_HW_CFG_MDC_MDIO_ACCESS1_EMAC1;
11392                 *phy = phy_8727;
11393                 phy->flags |= ELINK_FLAGS_NOC;
11394                 break;
11395         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X8722:
11396         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X8727:
11397                 mdc_mdio_access = SHARED_HW_CFG_MDC_MDIO_ACCESS1_EMAC1;
11398                 *phy = phy_8727;
11399                 break;
11400         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X8481:
11401                 *phy = phy_8481;
11402                 break;
11403         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X84823:
11404                 *phy = phy_84823;
11405                 break;
11406         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X84833:
11407                 *phy = phy_84833;
11408                 break;
11409         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X84834:
11410                 *phy = phy_84834;
11411                 break;
11412         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X54616:
11413         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X54618SE:
11414                 *phy = phy_54618se;
11415                 if (phy_type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X54618SE)
11416                         phy->flags |= ELINK_FLAGS_EEE;
11417                 break;
11418         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101:
11419                 *phy = phy_7101;
11420                 break;
11421         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE:
11422                 *phy = phy_null;
11423                 return ELINK_STATUS_ERROR;
11424         default:
11425                 *phy = phy_null;
11426                 /* In case external PHY wasn't found */
11427                 if ((phy_type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT) &&
11428                     (phy_type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN))
11429                         return ELINK_STATUS_ERROR;
11430                 return ELINK_STATUS_OK;
11431         }
11432
11433         phy->addr = ELINK_XGXS_EXT_PHY_ADDR(ext_phy_config);
11434         elink_populate_preemphasis(sc, shmem_base, phy, port, phy_index);
11435
11436         /* The shmem address of the phy version is located on different
11437          * structures. In case this structure is too old, do not set
11438          * the address
11439          */
11440         config2 = REG_RD(sc, shmem_base + offsetof(struct shmem_region,
11441                                                    dev_info.shared_hw_config.
11442                                                    config2));
11443         if (phy_index == ELINK_EXT_PHY1) {
11444                 phy->ver_addr = shmem_base + offsetof(struct shmem_region,
11445                                                       port_mb[port].
11446                                                       ext_phy_fw_version);
11447
11448                 /* Check specific mdc mdio settings */
11449                 if (config2 & SHARED_HW_CFG_MDC_MDIO_ACCESS1_MASK)
11450                         mdc_mdio_access = config2 &
11451                             SHARED_HW_CFG_MDC_MDIO_ACCESS1_MASK;
11452         } else {
11453                 uint32_t size = REG_RD(sc, shmem2_base);
11454
11455                 if (size > offsetof(struct shmem2_region, ext_phy_fw_version2)) {
11456                         phy->ver_addr = shmem2_base +
11457                             offsetof(struct shmem2_region,
11458                                      ext_phy_fw_version2[port]);
11459                 }
11460                 /* Check specific mdc mdio settings */
11461                 if (config2 & SHARED_HW_CFG_MDC_MDIO_ACCESS2_MASK)
11462                         mdc_mdio_access = (config2 &
11463                                            SHARED_HW_CFG_MDC_MDIO_ACCESS2_MASK)
11464                             >> (SHARED_HW_CFG_MDC_MDIO_ACCESS2_SHIFT -
11465                                 SHARED_HW_CFG_MDC_MDIO_ACCESS1_SHIFT);
11466         }
11467         phy->mdio_ctrl = elink_get_emac_base(sc, mdc_mdio_access, port);
11468
11469         if (((phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X84833) ||
11470              (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X84834)) &&
11471             (phy->ver_addr)) {
11472                 /* Remove 100Mb link supported for BNX2X84833/4 when phy fw
11473                  * version lower than or equal to 1.39
11474                  */
11475                 uint32_t raw_ver = REG_RD(sc, phy->ver_addr);
11476                 if (((raw_ver & 0x7F) <= 39) && (((raw_ver & 0xF80) >> 7) <= 1))
11477                         phy->supported &= ~(ELINK_SUPPORTED_100baseT_Half |
11478                                             ELINK_SUPPORTED_100baseT_Full);
11479         }
11480
11481         PMD_DRV_LOG(DEBUG, "phy_type 0x%x port %d found in index %d",
11482                     phy_type, port, phy_index);
11483         PMD_DRV_LOG(DEBUG, "             addr=0x%x, mdio_ctl=0x%x",
11484                     phy->addr, phy->mdio_ctrl);
11485         return ELINK_STATUS_OK;
11486 }
11487
11488 static elink_status_t elink_populate_phy(struct bnx2x_softc *sc,
11489                                          uint8_t phy_index, uint32_t shmem_base,
11490                                          uint32_t shmem2_base, uint8_t port,
11491                                          struct elink_phy *phy)
11492 {
11493         elink_status_t status = ELINK_STATUS_OK;
11494         phy->type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN;
11495         if (phy_index == ELINK_INT_PHY)
11496                 return elink_populate_int_phy(sc, shmem_base, port, phy);
11497         status = elink_populate_ext_phy(sc, phy_index, shmem_base, shmem2_base,
11498                                         port, phy);
11499         return status;
11500 }
11501
11502 static void elink_phy_def_cfg(struct elink_params *params,
11503                               struct elink_phy *phy, uint8_t phy_index)
11504 {
11505         struct bnx2x_softc *sc = params->sc;
11506         uint32_t link_config;
11507         /* Populate the default phy configuration for MF mode */
11508         if (phy_index == ELINK_EXT_PHY2) {
11509                 link_config = REG_RD(sc, params->shmem_base +
11510                                      offsetof(struct shmem_region,
11511                                               dev_info.port_feature_config
11512                                               [params->port].link_config2));
11513                 phy->speed_cap_mask =
11514                     REG_RD(sc,
11515                            params->shmem_base + offsetof(struct shmem_region,
11516                                                          dev_info.port_hw_config
11517                                                          [params->port].
11518                                                          speed_capability_mask2));
11519         } else {
11520                 link_config = REG_RD(sc, params->shmem_base +
11521                                      offsetof(struct shmem_region,
11522                                               dev_info.port_feature_config
11523                                               [params->port].link_config));
11524                 phy->speed_cap_mask =
11525                     REG_RD(sc,
11526                            params->shmem_base + offsetof(struct shmem_region,
11527                                                          dev_info.port_hw_config
11528                                                          [params->port].
11529                                                          speed_capability_mask));
11530         }
11531
11532         PMD_DRV_LOG(DEBUG,
11533                     "Default config phy idx %x cfg 0x%x speed_cap_mask 0x%x",
11534                     phy_index, link_config, phy->speed_cap_mask);
11535
11536         phy->req_duplex = DUPLEX_FULL;
11537         switch (link_config & PORT_FEATURE_LINK_SPEED_MASK) {
11538         case PORT_FEATURE_LINK_SPEED_10M_HALF:
11539                 phy->req_duplex = DUPLEX_HALF;
11540                 /* fall-through */
11541         case PORT_FEATURE_LINK_SPEED_10M_FULL:
11542                 phy->req_line_speed = ELINK_SPEED_10;
11543                 break;
11544         case PORT_FEATURE_LINK_SPEED_100M_HALF:
11545                 phy->req_duplex = DUPLEX_HALF;
11546                 /* fall-through */
11547         case PORT_FEATURE_LINK_SPEED_100M_FULL:
11548                 phy->req_line_speed = ELINK_SPEED_100;
11549                 break;
11550         case PORT_FEATURE_LINK_SPEED_1G:
11551                 phy->req_line_speed = ELINK_SPEED_1000;
11552                 break;
11553         case PORT_FEATURE_LINK_SPEED_2_5G:
11554                 phy->req_line_speed = ELINK_SPEED_2500;
11555                 break;
11556         case PORT_FEATURE_LINK_SPEED_10G_CX4:
11557                 phy->req_line_speed = ELINK_SPEED_10000;
11558                 break;
11559         default:
11560                 phy->req_line_speed = ELINK_SPEED_AUTO_NEG;
11561                 break;
11562         }
11563
11564         switch (link_config & PORT_FEATURE_FLOW_CONTROL_MASK) {
11565         case PORT_FEATURE_FLOW_CONTROL_AUTO:
11566                 phy->req_flow_ctrl = ELINK_FLOW_CTRL_AUTO;
11567                 break;
11568         case PORT_FEATURE_FLOW_CONTROL_TX:
11569                 phy->req_flow_ctrl = ELINK_FLOW_CTRL_TX;
11570                 break;
11571         case PORT_FEATURE_FLOW_CONTROL_RX:
11572                 phy->req_flow_ctrl = ELINK_FLOW_CTRL_RX;
11573                 break;
11574         case PORT_FEATURE_FLOW_CONTROL_BOTH:
11575                 phy->req_flow_ctrl = ELINK_FLOW_CTRL_BOTH;
11576                 break;
11577         default:
11578                 phy->req_flow_ctrl = ELINK_FLOW_CTRL_NONE;
11579                 break;
11580         }
11581 }
11582
11583 uint32_t elink_phy_selection(struct elink_params *params)
11584 {
11585         uint32_t phy_config_swapped, prio_cfg;
11586         uint32_t return_cfg = PORT_HW_CFG_PHY_SELECTION_HARDWARE_DEFAULT;
11587
11588         phy_config_swapped = params->multi_phy_config &
11589             PORT_HW_CFG_PHY_SWAPPED_ENABLED;
11590
11591         prio_cfg = params->multi_phy_config & PORT_HW_CFG_PHY_SELECTION_MASK;
11592
11593         if (phy_config_swapped) {
11594                 switch (prio_cfg) {
11595                 case PORT_HW_CFG_PHY_SELECTION_FIRST_PHY_PRIORITY:
11596                         return_cfg =
11597                             PORT_HW_CFG_PHY_SELECTION_SECOND_PHY_PRIORITY;
11598                         break;
11599                 case PORT_HW_CFG_PHY_SELECTION_SECOND_PHY_PRIORITY:
11600                         return_cfg =
11601                             PORT_HW_CFG_PHY_SELECTION_FIRST_PHY_PRIORITY;
11602                         break;
11603                 case PORT_HW_CFG_PHY_SELECTION_SECOND_PHY:
11604                         return_cfg = PORT_HW_CFG_PHY_SELECTION_FIRST_PHY;
11605                         break;
11606                 case PORT_HW_CFG_PHY_SELECTION_FIRST_PHY:
11607                         return_cfg = PORT_HW_CFG_PHY_SELECTION_SECOND_PHY;
11608                         break;
11609                 }
11610         } else
11611                 return_cfg = prio_cfg;
11612
11613         return return_cfg;
11614 }
11615
11616 elink_status_t elink_phy_probe(struct elink_params * params)
11617 {
11618         uint8_t phy_index, actual_phy_idx;
11619         uint32_t phy_config_swapped, sync_offset, media_types;
11620         struct bnx2x_softc *sc = params->sc;
11621         struct elink_phy *phy;
11622         params->num_phys = 0;
11623         PMD_DRV_LOG(DEBUG, "Begin phy probe");
11624
11625         phy_config_swapped = params->multi_phy_config &
11626             PORT_HW_CFG_PHY_SWAPPED_ENABLED;
11627
11628         for (phy_index = ELINK_INT_PHY; phy_index < ELINK_MAX_PHYS; phy_index++) {
11629                 actual_phy_idx = phy_index;
11630                 if (phy_config_swapped) {
11631                         if (phy_index == ELINK_EXT_PHY1)
11632                                 actual_phy_idx = ELINK_EXT_PHY2;
11633                         else if (phy_index == ELINK_EXT_PHY2)
11634                                 actual_phy_idx = ELINK_EXT_PHY1;
11635                 }
11636                 PMD_DRV_LOG(DEBUG, "phy_config_swapped %x, phy_index %x,"
11637                             " actual_phy_idx %x", phy_config_swapped,
11638                             phy_index, actual_phy_idx);
11639                 phy = &params->phy[actual_phy_idx];
11640                 if (elink_populate_phy(sc, phy_index, params->shmem_base,
11641                                        params->shmem2_base, params->port,
11642                                        phy) != ELINK_STATUS_OK) {
11643                         params->num_phys = 0;
11644                         PMD_DRV_LOG(DEBUG, "phy probe failed in phy index %d",
11645                                     phy_index);
11646                         for (phy_index = ELINK_INT_PHY;
11647                              phy_index < ELINK_MAX_PHYS; phy_index++)
11648                                 *phy = phy_null;
11649                         return ELINK_STATUS_ERROR;
11650                 }
11651                 if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN)
11652                         break;
11653
11654                 if (params->feature_config_flags &
11655                     ELINK_FEATURE_CONFIG_DISABLE_REMOTE_FAULT_DET)
11656                         phy->flags &= ~ELINK_FLAGS_TX_ERROR_CHECK;
11657
11658                 if (!(params->feature_config_flags &
11659                       ELINK_FEATURE_CONFIG_MT_SUPPORT))
11660                         phy->flags |= ELINK_FLAGS_MDC_MDIO_WA_G;
11661
11662                 sync_offset = params->shmem_base +
11663                     offsetof(struct shmem_region,
11664                              dev_info.port_hw_config[params->port].media_type);
11665                 media_types = REG_RD(sc, sync_offset);
11666
11667                 /* Update media type for non-PMF sync only for the first time
11668                  * In case the media type changes afterwards, it will be updated
11669                  * using the update_status function
11670                  */
11671                 if ((media_types & (PORT_HW_CFG_MEDIA_TYPE_PHY0_MASK <<
11672                                     (PORT_HW_CFG_MEDIA_TYPE_PHY1_SHIFT *
11673                                      actual_phy_idx))) == 0) {
11674                         media_types |= ((phy->media_type &
11675                                          PORT_HW_CFG_MEDIA_TYPE_PHY0_MASK) <<
11676                                         (PORT_HW_CFG_MEDIA_TYPE_PHY1_SHIFT *
11677                                          actual_phy_idx));
11678                 }
11679                 REG_WR(sc, sync_offset, media_types);
11680
11681                 elink_phy_def_cfg(params, phy, phy_index);
11682                 params->num_phys++;
11683         }
11684
11685         PMD_DRV_LOG(DEBUG, "End phy probe. #phys found %x", params->num_phys);
11686         return ELINK_STATUS_OK;
11687 }
11688
11689 static void elink_init_bmac_loopback(struct elink_params *params,
11690                                      struct elink_vars *vars)
11691 {
11692         struct bnx2x_softc *sc = params->sc;
11693         vars->link_up = 1;
11694         vars->line_speed = ELINK_SPEED_10000;
11695         vars->duplex = DUPLEX_FULL;
11696         vars->flow_ctrl = ELINK_FLOW_CTRL_NONE;
11697         vars->mac_type = ELINK_MAC_TYPE_BMAC;
11698
11699         vars->phy_flags = PHY_XGXS_FLAG;
11700
11701         elink_xgxs_deassert(params);
11702
11703         /* Set bmac loopback */
11704         elink_bmac_enable(params, vars, 1, 1);
11705
11706         REG_WR(sc, NIG_REG_EGRESS_DRAIN0_MODE + params->port * 4, 0);
11707 }
11708
11709 static void elink_init_emac_loopback(struct elink_params *params,
11710                                      struct elink_vars *vars)
11711 {
11712         struct bnx2x_softc *sc = params->sc;
11713         vars->link_up = 1;
11714         vars->line_speed = ELINK_SPEED_1000;
11715         vars->duplex = DUPLEX_FULL;
11716         vars->flow_ctrl = ELINK_FLOW_CTRL_NONE;
11717         vars->mac_type = ELINK_MAC_TYPE_EMAC;
11718
11719         vars->phy_flags = PHY_XGXS_FLAG;
11720
11721         elink_xgxs_deassert(params);
11722         /* Set bmac loopback */
11723         elink_emac_enable(params, vars, 1);
11724         elink_emac_program(params, vars);
11725         REG_WR(sc, NIG_REG_EGRESS_DRAIN0_MODE + params->port * 4, 0);
11726 }
11727
11728 static void elink_init_xmac_loopback(struct elink_params *params,
11729                                      struct elink_vars *vars)
11730 {
11731         struct bnx2x_softc *sc = params->sc;
11732         vars->link_up = 1;
11733         if (!params->req_line_speed[0])
11734                 vars->line_speed = ELINK_SPEED_10000;
11735         else
11736                 vars->line_speed = params->req_line_speed[0];
11737         vars->duplex = DUPLEX_FULL;
11738         vars->flow_ctrl = ELINK_FLOW_CTRL_NONE;
11739         vars->mac_type = ELINK_MAC_TYPE_XMAC;
11740         vars->phy_flags = PHY_XGXS_FLAG;
11741         /* Set WC to loopback mode since link is required to provide clock
11742          * to the XMAC in 20G mode
11743          */
11744         elink_set_aer_mmd(params, &params->phy[0]);
11745         elink_warpcore_reset_lane(sc, &params->phy[0], 0);
11746         params->phy[ELINK_INT_PHY].config_loopback(&params->phy[ELINK_INT_PHY],
11747                                                    params);
11748
11749         elink_xmac_enable(params, vars, 1);
11750         REG_WR(sc, NIG_REG_EGRESS_DRAIN0_MODE + params->port * 4, 0);
11751 }
11752
11753 static void elink_init_umac_loopback(struct elink_params *params,
11754                                      struct elink_vars *vars)
11755 {
11756         struct bnx2x_softc *sc = params->sc;
11757         vars->link_up = 1;
11758         vars->line_speed = ELINK_SPEED_1000;
11759         vars->duplex = DUPLEX_FULL;
11760         vars->flow_ctrl = ELINK_FLOW_CTRL_NONE;
11761         vars->mac_type = ELINK_MAC_TYPE_UMAC;
11762         vars->phy_flags = PHY_XGXS_FLAG;
11763         elink_umac_enable(params, vars, 1);
11764
11765         REG_WR(sc, NIG_REG_EGRESS_DRAIN0_MODE + params->port * 4, 0);
11766 }
11767
11768 static void elink_init_xgxs_loopback(struct elink_params *params,
11769                                      struct elink_vars *vars)
11770 {
11771         struct bnx2x_softc *sc = params->sc;
11772         struct elink_phy *int_phy = &params->phy[ELINK_INT_PHY];
11773         vars->link_up = 1;
11774         vars->flow_ctrl = ELINK_FLOW_CTRL_NONE;
11775         vars->duplex = DUPLEX_FULL;
11776         if (params->req_line_speed[0] == ELINK_SPEED_1000)
11777                 vars->line_speed = ELINK_SPEED_1000;
11778         else if ((params->req_line_speed[0] == ELINK_SPEED_20000) ||
11779                  (int_phy->flags & ELINK_FLAGS_WC_DUAL_MODE))
11780                 vars->line_speed = ELINK_SPEED_20000;
11781         else
11782                 vars->line_speed = ELINK_SPEED_10000;
11783
11784         if (!USES_WARPCORE(sc))
11785                 elink_xgxs_deassert(params);
11786         elink_link_initialize(params, vars);
11787
11788         if (params->req_line_speed[0] == ELINK_SPEED_1000) {
11789                 if (USES_WARPCORE(sc))
11790                         elink_umac_enable(params, vars, 0);
11791                 else {
11792                         elink_emac_program(params, vars);
11793                         elink_emac_enable(params, vars, 0);
11794                 }
11795         } else {
11796                 if (USES_WARPCORE(sc))
11797                         elink_xmac_enable(params, vars, 0);
11798                 else
11799                         elink_bmac_enable(params, vars, 0, 1);
11800         }
11801
11802         if (params->loopback_mode == ELINK_LOOPBACK_XGXS) {
11803                 /* Set 10G XGXS loopback */
11804                 int_phy->config_loopback(int_phy, params);
11805         } else {
11806                 /* Set external phy loopback */
11807                 uint8_t phy_index;
11808                 for (phy_index = ELINK_EXT_PHY1;
11809                      phy_index < params->num_phys; phy_index++)
11810                         if (params->phy[phy_index].config_loopback)
11811                                 params->phy[phy_index].config_loopback(&params->
11812                                                                        phy
11813                                                                        [phy_index],
11814                                                                        params);
11815         }
11816         REG_WR(sc, NIG_REG_EGRESS_DRAIN0_MODE + params->port * 4, 0);
11817
11818         elink_set_led(params, vars, ELINK_LED_MODE_OPER, vars->line_speed);
11819 }
11820
11821 void elink_set_rx_filter(struct elink_params *params, uint8_t en)
11822 {
11823         struct bnx2x_softc *sc = params->sc;
11824         uint8_t val = en * 0x1F;
11825
11826         /* Open / close the gate between the NIG and the BRB */
11827         if (!CHIP_IS_E1x(sc))
11828                 val |= en * 0x20;
11829         REG_WR(sc, NIG_REG_LLH0_BRB1_DRV_MASK + params->port * 4, val);
11830
11831         REG_WR(sc, NIG_REG_LLH0_BRB1_DRV_MASK_MF + params->port * 4, en * 0x3);
11832
11833         REG_WR(sc, (params->port ? NIG_REG_LLH1_BRB1_NOT_MCP :
11834                     NIG_REG_LLH0_BRB1_NOT_MCP), en);
11835 }
11836
11837 static elink_status_t elink_avoid_link_flap(struct elink_params *params,
11838                                             struct elink_vars *vars)
11839 {
11840         uint32_t phy_idx;
11841         uint32_t dont_clear_stat, lfa_sts;
11842         struct bnx2x_softc *sc = params->sc;
11843
11844         /* Sync the link parameters */
11845         elink_link_status_update(params, vars);
11846
11847         /*
11848          * The module verification was already done by previous link owner,
11849          * so this call is meant only to get warning message
11850          */
11851
11852         for (phy_idx = ELINK_INT_PHY; phy_idx < params->num_phys; phy_idx++) {
11853                 struct elink_phy *phy = &params->phy[phy_idx];
11854                 if (phy->phy_specific_func) {
11855                         PMD_DRV_LOG(DEBUG, "Calling PHY specific func");
11856                         phy->phy_specific_func(phy, params, ELINK_PHY_INIT);
11857                 }
11858                 if ((phy->media_type == ELINK_ETH_PHY_SFPP_10G_FIBER) ||
11859                     (phy->media_type == ELINK_ETH_PHY_SFP_1G_FIBER) ||
11860                     (phy->media_type == ELINK_ETH_PHY_DA_TWINAX))
11861                         elink_verify_sfp_module(phy, params);
11862         }
11863         lfa_sts = REG_RD(sc, params->lfa_base +
11864                          offsetof(struct shmem_lfa, lfa_sts));
11865
11866         dont_clear_stat = lfa_sts & SHMEM_LFA_DONT_CLEAR_STAT;
11867
11868         /* Re-enable the NIG/MAC */
11869         if (CHIP_IS_E3(sc)) {
11870                 if (!dont_clear_stat) {
11871                         REG_WR(sc, GRCBASE_MISC +
11872                                MISC_REGISTERS_RESET_REG_2_CLEAR,
11873                                (MISC_REGISTERS_RESET_REG_2_MSTAT0 <<
11874                                 params->port));
11875                         REG_WR(sc, GRCBASE_MISC +
11876                                MISC_REGISTERS_RESET_REG_2_SET,
11877                                (MISC_REGISTERS_RESET_REG_2_MSTAT0 <<
11878                                 params->port));
11879                 }
11880                 if (vars->line_speed < ELINK_SPEED_10000)
11881                         elink_umac_enable(params, vars, 0);
11882                 else
11883                         elink_xmac_enable(params, vars, 0);
11884         } else {
11885                 if (vars->line_speed < ELINK_SPEED_10000)
11886                         elink_emac_enable(params, vars, 0);
11887                 else
11888                         elink_bmac_enable(params, vars, 0, !dont_clear_stat);
11889         }
11890
11891         /* Increment LFA count */
11892         lfa_sts = ((lfa_sts & ~LINK_FLAP_AVOIDANCE_COUNT_MASK) |
11893                    (((((lfa_sts & LINK_FLAP_AVOIDANCE_COUNT_MASK) >>
11894                        LINK_FLAP_AVOIDANCE_COUNT_OFFSET) + 1) & 0xff)
11895                     << LINK_FLAP_AVOIDANCE_COUNT_OFFSET));
11896         /* Clear link flap reason */
11897         lfa_sts &= ~LFA_LINK_FLAP_REASON_MASK;
11898
11899         REG_WR(sc, params->lfa_base +
11900                offsetof(struct shmem_lfa, lfa_sts), lfa_sts);
11901
11902         /* Disable NIG DRAIN */
11903         REG_WR(sc, NIG_REG_EGRESS_DRAIN0_MODE + params->port * 4, 0);
11904
11905         /* Enable interrupts */
11906         elink_link_int_enable(params);
11907         return ELINK_STATUS_OK;
11908 }
11909
11910 static void elink_cannot_avoid_link_flap(struct elink_params *params,
11911                                          struct elink_vars *vars,
11912                                          int lfa_status)
11913 {
11914         uint32_t lfa_sts, cfg_idx, tmp_val;
11915         struct bnx2x_softc *sc = params->sc;
11916
11917         elink_link_reset(params, vars, 1);
11918
11919         if (!params->lfa_base)
11920                 return;
11921         /* Store the new link parameters */
11922         REG_WR(sc, params->lfa_base +
11923                offsetof(struct shmem_lfa, req_duplex),
11924                params->req_duplex[0] | (params->req_duplex[1] << 16));
11925
11926         REG_WR(sc, params->lfa_base +
11927                offsetof(struct shmem_lfa, req_flow_ctrl),
11928                params->req_flow_ctrl[0] | (params->req_flow_ctrl[1] << 16));
11929
11930         REG_WR(sc, params->lfa_base +
11931                offsetof(struct shmem_lfa, req_line_speed),
11932                params->req_line_speed[0] | (params->req_line_speed[1] << 16));
11933
11934         for (cfg_idx = 0; cfg_idx < SHMEM_LINK_CONFIG_SIZE; cfg_idx++) {
11935                 REG_WR(sc, params->lfa_base +
11936                        offsetof(struct shmem_lfa,
11937                                 speed_cap_mask[cfg_idx]),
11938                        params->speed_cap_mask[cfg_idx]);
11939         }
11940
11941         tmp_val = REG_RD(sc, params->lfa_base +
11942                          offsetof(struct shmem_lfa, additional_config));
11943         tmp_val &= ~REQ_FC_AUTO_ADV_MASK;
11944         tmp_val |= params->req_fc_auto_adv;
11945
11946         REG_WR(sc, params->lfa_base +
11947                offsetof(struct shmem_lfa, additional_config), tmp_val);
11948
11949         lfa_sts = REG_RD(sc, params->lfa_base +
11950                          offsetof(struct shmem_lfa, lfa_sts));
11951
11952         /* Clear the "Don't Clear Statistics" bit, and set reason */
11953         lfa_sts &= ~SHMEM_LFA_DONT_CLEAR_STAT;
11954
11955         /* Set link flap reason */
11956         lfa_sts &= ~LFA_LINK_FLAP_REASON_MASK;
11957         lfa_sts |= ((lfa_status & LFA_LINK_FLAP_REASON_MASK) <<
11958                     LFA_LINK_FLAP_REASON_OFFSET);
11959
11960         /* Increment link flap counter */
11961         lfa_sts = ((lfa_sts & ~LINK_FLAP_COUNT_MASK) |
11962                    (((((lfa_sts & LINK_FLAP_COUNT_MASK) >>
11963                        LINK_FLAP_COUNT_OFFSET) + 1) & 0xff)
11964                     << LINK_FLAP_COUNT_OFFSET));
11965         REG_WR(sc, params->lfa_base +
11966                offsetof(struct shmem_lfa, lfa_sts), lfa_sts);
11967         /* Proceed with regular link initialization */
11968 }
11969
11970 elink_status_t elink_phy_init(struct elink_params *params,
11971                               struct elink_vars *vars)
11972 {
11973         int lfa_status;
11974         struct bnx2x_softc *sc = params->sc;
11975         PMD_DRV_LOG(DEBUG, "Phy Initialization started");
11976         PMD_DRV_LOG(DEBUG, "(1) req_speed %d, req_flowctrl %d",
11977                     params->req_line_speed[0], params->req_flow_ctrl[0]);
11978         PMD_DRV_LOG(DEBUG, "(2) req_speed %d, req_flowctrl %d",
11979                     params->req_line_speed[1], params->req_flow_ctrl[1]);
11980         PMD_DRV_LOG(DEBUG, "req_adv_flow_ctrl 0x%x", params->req_fc_auto_adv);
11981         vars->link_status = 0;
11982         vars->phy_link_up = 0;
11983         vars->link_up = 0;
11984         vars->line_speed = 0;
11985         vars->duplex = DUPLEX_FULL;
11986         vars->flow_ctrl = ELINK_FLOW_CTRL_NONE;
11987         vars->mac_type = ELINK_MAC_TYPE_NONE;
11988         vars->phy_flags = 0;
11989         vars->check_kr2_recovery_cnt = 0;
11990         params->link_flags = ELINK_PHY_INITIALIZED;
11991         /* Driver opens NIG-BRB filters */
11992         elink_set_rx_filter(params, 1);
11993         /* Check if link flap can be avoided */
11994         lfa_status = elink_check_lfa(params);
11995
11996         if (lfa_status == 0) {
11997                 PMD_DRV_LOG(DEBUG, "Link Flap Avoidance in progress");
11998                 return elink_avoid_link_flap(params, vars);
11999         }
12000
12001         PMD_DRV_LOG(DEBUG, "Cannot avoid link flap lfa_sta=0x%x", lfa_status);
12002         elink_cannot_avoid_link_flap(params, vars, lfa_status);
12003
12004         /* Disable attentions */
12005         elink_bits_dis(sc, NIG_REG_MASK_INTERRUPT_PORT0 + params->port * 4,
12006                        (ELINK_NIG_MASK_XGXS0_LINK_STATUS |
12007                         ELINK_NIG_MASK_XGXS0_LINK10G |
12008                         ELINK_NIG_MASK_SERDES0_LINK_STATUS |
12009                         ELINK_NIG_MASK_MI_INT));
12010
12011         elink_emac_init(params);
12012
12013         if (params->feature_config_flags & ELINK_FEATURE_CONFIG_PFC_ENABLED)
12014                 vars->link_status |= LINK_STATUS_PFC_ENABLED;
12015
12016         if ((params->num_phys == 0) && !CHIP_REV_IS_SLOW(sc)) {
12017                 PMD_DRV_LOG(DEBUG, "No phy found for initialization !!");
12018                 return ELINK_STATUS_ERROR;
12019         }
12020         set_phy_vars(params, vars);
12021
12022         PMD_DRV_LOG(DEBUG, "Num of phys on board: %d", params->num_phys);
12023
12024         switch (params->loopback_mode) {
12025         case ELINK_LOOPBACK_BMAC:
12026                 elink_init_bmac_loopback(params, vars);
12027                 break;
12028         case ELINK_LOOPBACK_EMAC:
12029                 elink_init_emac_loopback(params, vars);
12030                 break;
12031         case ELINK_LOOPBACK_XMAC:
12032                 elink_init_xmac_loopback(params, vars);
12033                 break;
12034         case ELINK_LOOPBACK_UMAC:
12035                 elink_init_umac_loopback(params, vars);
12036                 break;
12037         case ELINK_LOOPBACK_XGXS:
12038         case ELINK_LOOPBACK_EXT_PHY:
12039                 elink_init_xgxs_loopback(params, vars);
12040                 break;
12041         default:
12042                 if (!CHIP_IS_E3(sc)) {
12043                         if (params->switch_cfg == ELINK_SWITCH_CFG_10G)
12044                                 elink_xgxs_deassert(params);
12045                         else
12046                                 elink_serdes_deassert(sc, params->port);
12047                 }
12048                 elink_link_initialize(params, vars);
12049                 DELAY(1000 * 30);
12050                 elink_link_int_enable(params);
12051                 break;
12052         }
12053         elink_update_mng(params, vars->link_status);
12054
12055         elink_update_mng_eee(params, vars->eee_status);
12056         return ELINK_STATUS_OK;
12057 }
12058
12059 static elink_status_t elink_link_reset(struct elink_params *params,
12060                                        struct elink_vars *vars,
12061                                        uint8_t reset_ext_phy)
12062 {
12063         struct bnx2x_softc *sc = params->sc;
12064         uint8_t phy_index, port = params->port, clear_latch_ind = 0;
12065         PMD_DRV_LOG(DEBUG, "Resetting the link of port %d", port);
12066         /* Disable attentions */
12067         vars->link_status = 0;
12068         elink_update_mng(params, vars->link_status);
12069         vars->eee_status &= ~(SHMEM_EEE_LP_ADV_STATUS_MASK |
12070                               SHMEM_EEE_ACTIVE_BIT);
12071         elink_update_mng_eee(params, vars->eee_status);
12072         elink_bits_dis(sc, NIG_REG_MASK_INTERRUPT_PORT0 + port * 4,
12073                        (ELINK_NIG_MASK_XGXS0_LINK_STATUS |
12074                         ELINK_NIG_MASK_XGXS0_LINK10G |
12075                         ELINK_NIG_MASK_SERDES0_LINK_STATUS |
12076                         ELINK_NIG_MASK_MI_INT));
12077
12078         /* Activate nig drain */
12079         REG_WR(sc, NIG_REG_EGRESS_DRAIN0_MODE + port * 4, 1);
12080
12081         /* Disable nig egress interface */
12082         if (!CHIP_IS_E3(sc)) {
12083                 REG_WR(sc, NIG_REG_BMAC0_OUT_EN + port * 4, 0);
12084                 REG_WR(sc, NIG_REG_EGRESS_EMAC0_OUT_EN + port * 4, 0);
12085         }
12086         if (!CHIP_IS_E3(sc))
12087                 elink_set_bmac_rx(sc, port, 0);
12088         if (CHIP_IS_E3(sc) && !CHIP_REV_IS_FPGA(sc)) {
12089                 elink_set_xmac_rxtx(params, 0);
12090                 elink_set_umac_rxtx(params, 0);
12091         }
12092         /* Disable emac */
12093         if (!CHIP_IS_E3(sc))
12094                 REG_WR(sc, NIG_REG_NIG_EMAC0_EN + port * 4, 0);
12095
12096         DELAY(1000 * 10);
12097         /* The PHY reset is controlled by GPIO 1
12098          * Hold it as vars low
12099          */
12100         /* Clear link led */
12101         elink_set_mdio_emac_per_phy(sc, params);
12102         elink_set_led(params, vars, ELINK_LED_MODE_OFF, 0);
12103
12104         if (reset_ext_phy && (!CHIP_REV_IS_SLOW(sc))) {
12105                 for (phy_index = ELINK_EXT_PHY1; phy_index < params->num_phys;
12106                      phy_index++) {
12107                         if (params->phy[phy_index].link_reset) {
12108                                 elink_set_aer_mmd(params,
12109                                                   &params->phy[phy_index]);
12110                                 params->phy[phy_index].link_reset(&params->
12111                                                                   phy
12112                                                                   [phy_index],
12113                                                                   params);
12114                         }
12115                         if (params->phy[phy_index].flags &
12116                             ELINK_FLAGS_REARM_LATCH_SIGNAL)
12117                                 clear_latch_ind = 1;
12118                 }
12119         }
12120
12121         if (clear_latch_ind) {
12122                 /* Clear latching indication */
12123                 elink_rearm_latch_signal(sc, port, 0);
12124                 elink_bits_dis(sc, NIG_REG_LATCH_BC_0 + port * 4,
12125                                1 << ELINK_NIG_LATCH_BC_ENABLE_MI_INT);
12126         }
12127         if (params->phy[ELINK_INT_PHY].link_reset)
12128                 params->phy[ELINK_INT_PHY].link_reset(&params->
12129                                                       phy
12130                                                       [ELINK_INT_PHY],
12131                                                       params);
12132
12133         /* Disable nig ingress interface */
12134         if (!CHIP_IS_E3(sc)) {
12135                 /* Reset BigMac */
12136                 REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
12137                        (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port));
12138                 REG_WR(sc, NIG_REG_BMAC0_IN_EN + port * 4, 0);
12139                 REG_WR(sc, NIG_REG_EMAC0_IN_EN + port * 4, 0);
12140         } else {
12141                 uint32_t xmac_base =
12142                     (params->port) ? GRCBASE_XMAC1 : GRCBASE_XMAC0;
12143                 elink_set_xumac_nig(params, 0, 0);
12144                 if (REG_RD(sc, MISC_REG_RESET_REG_2) &
12145                     MISC_REGISTERS_RESET_REG_2_XMAC)
12146                         REG_WR(sc, xmac_base + XMAC_REG_CTRL,
12147                                XMAC_CTRL_REG_SOFT_RESET);
12148         }
12149         vars->link_up = 0;
12150         vars->phy_flags = 0;
12151         return ELINK_STATUS_OK;
12152 }
12153
12154 elink_status_t elink_lfa_reset(struct elink_params * params,
12155                                struct elink_vars * vars)
12156 {
12157         struct bnx2x_softc *sc = params->sc;
12158         vars->link_up = 0;
12159         vars->phy_flags = 0;
12160         params->link_flags &= ~ELINK_PHY_INITIALIZED;
12161         if (!params->lfa_base)
12162                 return elink_link_reset(params, vars, 1);
12163         /*
12164          * Activate NIG drain so that during this time the device won't send
12165          * anything while it is unable to response.
12166          */
12167         REG_WR(sc, NIG_REG_EGRESS_DRAIN0_MODE + params->port * 4, 1);
12168
12169         /*
12170          * Close gracefully the gate from BMAC to NIG such that no half packets
12171          * are passed.
12172          */
12173         if (!CHIP_IS_E3(sc))
12174                 elink_set_bmac_rx(sc, params->port, 0);
12175
12176         if (CHIP_IS_E3(sc)) {
12177                 elink_set_xmac_rxtx(params, 0);
12178                 elink_set_umac_rxtx(params, 0);
12179         }
12180         /* Wait 10ms for the pipe to clean up */
12181         DELAY(1000 * 10);
12182
12183         /* Clean the NIG-BRB using the network filters in a way that will
12184          * not cut a packet in the middle.
12185          */
12186         elink_set_rx_filter(params, 0);
12187
12188         /*
12189          * Re-open the gate between the BMAC and the NIG, after verifying the
12190          * gate to the BRB is closed, otherwise packets may arrive to the
12191          * firmware before driver had initialized it. The target is to achieve
12192          * minimum management protocol down time.
12193          */
12194         if (!CHIP_IS_E3(sc))
12195                 elink_set_bmac_rx(sc, params->port, 1);
12196
12197         if (CHIP_IS_E3(sc)) {
12198                 elink_set_xmac_rxtx(params, 1);
12199                 elink_set_umac_rxtx(params, 1);
12200         }
12201         /* Disable NIG drain */
12202         REG_WR(sc, NIG_REG_EGRESS_DRAIN0_MODE + params->port * 4, 0);
12203         return ELINK_STATUS_OK;
12204 }
12205
12206 /****************************************************************************/
12207 /*                              Common function                             */
12208 /****************************************************************************/
12209 static elink_status_t elink_8073_common_init_phy(struct bnx2x_softc *sc,
12210                                                  uint32_t shmem_base_path[],
12211                                                  uint32_t shmem2_base_path[],
12212                                                  uint8_t phy_index,
12213                                                  __rte_unused uint32_t chip_id)
12214 {
12215         struct elink_phy phy[PORT_MAX];
12216         struct elink_phy *phy_blk[PORT_MAX];
12217         uint16_t val;
12218         int8_t port = 0;
12219         int8_t port_of_path = 0;
12220         uint32_t swap_val, swap_override;
12221         swap_val = REG_RD(sc, NIG_REG_PORT_SWAP);
12222         swap_override = REG_RD(sc, NIG_REG_STRAP_OVERRIDE);
12223         port ^= (swap_val && swap_override);
12224         elink_ext_phy_hw_reset(sc, port);
12225         /* PART1 - Reset both phys */
12226         for (port = PORT_MAX - 1; port >= PORT_0; port--) {
12227                 uint32_t shmem_base, shmem2_base;
12228                 /* In E2, same phy is using for port0 of the two paths */
12229                 if (CHIP_IS_E1x(sc)) {
12230                         shmem_base = shmem_base_path[0];
12231                         shmem2_base = shmem2_base_path[0];
12232                         port_of_path = port;
12233                 } else {
12234                         shmem_base = shmem_base_path[port];
12235                         shmem2_base = shmem2_base_path[port];
12236                         port_of_path = 0;
12237                 }
12238
12239                 /* Extract the ext phy address for the port */
12240                 if (elink_populate_phy(sc, phy_index, shmem_base, shmem2_base,
12241                                        port_of_path, &phy[port]) !=
12242                     ELINK_STATUS_OK) {
12243                         PMD_DRV_LOG(DEBUG, "populate_phy failed");
12244                         return ELINK_STATUS_ERROR;
12245                 }
12246                 /* Disable attentions */
12247                 elink_bits_dis(sc, NIG_REG_MASK_INTERRUPT_PORT0 +
12248                                port_of_path * 4,
12249                                (ELINK_NIG_MASK_XGXS0_LINK_STATUS |
12250                                 ELINK_NIG_MASK_XGXS0_LINK10G |
12251                                 ELINK_NIG_MASK_SERDES0_LINK_STATUS |
12252                                 ELINK_NIG_MASK_MI_INT));
12253
12254                 /* Need to take the phy out of low power mode in order
12255                  * to write to access its registers
12256                  */
12257                 elink_cb_gpio_write(sc, MISC_REGISTERS_GPIO_2,
12258                                     MISC_REGISTERS_GPIO_OUTPUT_HIGH, port);
12259
12260                 /* Reset the phy */
12261                 elink_cl45_write(sc, &phy[port],
12262                                  MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 1 << 15);
12263         }
12264
12265         /* Add delay of 150ms after reset */
12266         DELAY(1000 * 150);
12267
12268         if (phy[PORT_0].addr & 0x1) {
12269                 phy_blk[PORT_0] = &(phy[PORT_1]);
12270                 phy_blk[PORT_1] = &(phy[PORT_0]);
12271         } else {
12272                 phy_blk[PORT_0] = &(phy[PORT_0]);
12273                 phy_blk[PORT_1] = &(phy[PORT_1]);
12274         }
12275
12276         /* PART2 - Download firmware to both phys */
12277         for (port = PORT_MAX - 1; port >= PORT_0; port--) {
12278                 if (CHIP_IS_E1x(sc))
12279                         port_of_path = port;
12280                 else
12281                         port_of_path = 0;
12282
12283                 PMD_DRV_LOG(DEBUG, "Loading spirom for phy address 0x%x",
12284                             phy_blk[port]->addr);
12285                 if (elink_8073_8727_external_rom_boot(sc, phy_blk[port],
12286                                                       port_of_path))
12287                         return ELINK_STATUS_ERROR;
12288
12289                 /* Only set bit 10 = 1 (Tx power down) */
12290                 elink_cl45_read(sc, phy_blk[port],
12291                                 MDIO_PMA_DEVAD,
12292                                 MDIO_PMA_REG_TX_POWER_DOWN, &val);
12293
12294                 /* Phase1 of TX_POWER_DOWN reset */
12295                 elink_cl45_write(sc, phy_blk[port],
12296                                  MDIO_PMA_DEVAD,
12297                                  MDIO_PMA_REG_TX_POWER_DOWN, (val | 1 << 10));
12298         }
12299
12300         /* Toggle Transmitter: Power down and then up with 600ms delay
12301          * between
12302          */
12303         DELAY(1000 * 600);
12304
12305         /* PART3 - complete TX_POWER_DOWN process, and set GPIO2 back to low */
12306         for (port = PORT_MAX - 1; port >= PORT_0; port--) {
12307                 /* Phase2 of POWER_DOWN_RESET */
12308                 /* Release bit 10 (Release Tx power down) */
12309                 elink_cl45_read(sc, phy_blk[port],
12310                                 MDIO_PMA_DEVAD,
12311                                 MDIO_PMA_REG_TX_POWER_DOWN, &val);
12312
12313                 elink_cl45_write(sc, phy_blk[port],
12314                                  MDIO_PMA_DEVAD,
12315                                  MDIO_PMA_REG_TX_POWER_DOWN,
12316                                  (val & (~(1 << 10))));
12317                 DELAY(1000 * 15);
12318
12319                 /* Read modify write the SPI-ROM version select register */
12320                 elink_cl45_read(sc, phy_blk[port],
12321                                 MDIO_PMA_DEVAD,
12322                                 MDIO_PMA_REG_EDC_FFE_MAIN, &val);
12323                 elink_cl45_write(sc, phy_blk[port],
12324                                  MDIO_PMA_DEVAD,
12325                                  MDIO_PMA_REG_EDC_FFE_MAIN, (val | (1 << 12)));
12326
12327                 /* set GPIO2 back to LOW */
12328                 elink_cb_gpio_write(sc, MISC_REGISTERS_GPIO_2,
12329                                     MISC_REGISTERS_GPIO_OUTPUT_LOW, port);
12330         }
12331         return ELINK_STATUS_OK;
12332 }
12333
12334 static elink_status_t elink_8726_common_init_phy(struct bnx2x_softc *sc,
12335                                                  uint32_t shmem_base_path[],
12336                                                  uint32_t shmem2_base_path[],
12337                                                  uint8_t phy_index,
12338                                                  __rte_unused uint32_t chip_id)
12339 {
12340         uint32_t val;
12341         int8_t port;
12342         struct elink_phy phy;
12343         /* Use port1 because of the static port-swap */
12344         /* Enable the module detection interrupt */
12345         val = REG_RD(sc, MISC_REG_GPIO_EVENT_EN);
12346         val |= ((1 << MISC_REGISTERS_GPIO_3) |
12347                 (1 <<
12348                  (MISC_REGISTERS_GPIO_3 + MISC_REGISTERS_GPIO_PORT_SHIFT)));
12349         REG_WR(sc, MISC_REG_GPIO_EVENT_EN, val);
12350
12351         elink_ext_phy_hw_reset(sc, 0);
12352         DELAY(1000 * 5);
12353         for (port = 0; port < PORT_MAX; port++) {
12354                 uint32_t shmem_base, shmem2_base;
12355
12356                 /* In E2, same phy is using for port0 of the two paths */
12357                 if (CHIP_IS_E1x(sc)) {
12358                         shmem_base = shmem_base_path[0];
12359                         shmem2_base = shmem2_base_path[0];
12360                 } else {
12361                         shmem_base = shmem_base_path[port];
12362                         shmem2_base = shmem2_base_path[port];
12363                 }
12364                 /* Extract the ext phy address for the port */
12365                 if (elink_populate_phy(sc, phy_index, shmem_base, shmem2_base,
12366                                        port, &phy) != ELINK_STATUS_OK) {
12367                         PMD_DRV_LOG(DEBUG, "populate phy failed");
12368                         return ELINK_STATUS_ERROR;
12369                 }
12370
12371                 /* Reset phy */
12372                 elink_cl45_write(sc, &phy,
12373                                  MDIO_PMA_DEVAD, MDIO_PMA_REG_GEN_CTRL, 0x0001);
12374
12375                 /* Set fault module detected LED on */
12376                 elink_cb_gpio_write(sc, MISC_REGISTERS_GPIO_0,
12377                                     MISC_REGISTERS_GPIO_HIGH, port);
12378         }
12379
12380         return ELINK_STATUS_OK;
12381 }
12382
12383 static void elink_get_ext_phy_reset_gpio(struct bnx2x_softc *sc,
12384                                          uint32_t shmem_base, uint8_t * io_gpio,
12385                                          uint8_t * io_port)
12386 {
12387
12388         uint32_t phy_gpio_reset = REG_RD(sc, shmem_base +
12389                                          offsetof(struct shmem_region,
12390                                                   dev_info.
12391                                                   port_hw_config[PORT_0].
12392                                                   default_cfg));
12393         switch (phy_gpio_reset) {
12394         case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO0_P0:
12395                 *io_gpio = 0;
12396                 *io_port = 0;
12397                 break;
12398         case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO1_P0:
12399                 *io_gpio = 1;
12400                 *io_port = 0;
12401                 break;
12402         case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO2_P0:
12403                 *io_gpio = 2;
12404                 *io_port = 0;
12405                 break;
12406         case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO3_P0:
12407                 *io_gpio = 3;
12408                 *io_port = 0;
12409                 break;
12410         case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO0_P1:
12411                 *io_gpio = 0;
12412                 *io_port = 1;
12413                 break;
12414         case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO1_P1:
12415                 *io_gpio = 1;
12416                 *io_port = 1;
12417                 break;
12418         case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO2_P1:
12419                 *io_gpio = 2;
12420                 *io_port = 1;
12421                 break;
12422         case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO3_P1:
12423                 *io_gpio = 3;
12424                 *io_port = 1;
12425                 break;
12426         default:
12427                 /* Don't override the io_gpio and io_port */
12428                 break;
12429         }
12430 }
12431
12432 static elink_status_t elink_8727_common_init_phy(struct bnx2x_softc *sc,
12433                                                  uint32_t shmem_base_path[],
12434                                                  uint32_t shmem2_base_path[],
12435                                                  uint8_t phy_index,
12436                                                  __rte_unused uint32_t chip_id)
12437 {
12438         int8_t port, reset_gpio;
12439         uint32_t swap_val, swap_override;
12440         struct elink_phy phy[PORT_MAX];
12441         struct elink_phy *phy_blk[PORT_MAX];
12442         int8_t port_of_path;
12443         swap_val = REG_RD(sc, NIG_REG_PORT_SWAP);
12444         swap_override = REG_RD(sc, NIG_REG_STRAP_OVERRIDE);
12445
12446         reset_gpio = MISC_REGISTERS_GPIO_1;
12447         port = 1;
12448
12449         /* Retrieve the reset gpio/port which control the reset.
12450          * Default is GPIO1, PORT1
12451          */
12452         elink_get_ext_phy_reset_gpio(sc, shmem_base_path[0],
12453                                      (uint8_t *) & reset_gpio,
12454                                      (uint8_t *) & port);
12455
12456         /* Calculate the port based on port swap */
12457         port ^= (swap_val && swap_override);
12458
12459         /* Initiate PHY reset */
12460         elink_cb_gpio_write(sc, reset_gpio, MISC_REGISTERS_GPIO_OUTPUT_LOW,
12461                             port);
12462         DELAY(1000 * 1);
12463         elink_cb_gpio_write(sc, reset_gpio, MISC_REGISTERS_GPIO_OUTPUT_HIGH,
12464                             port);
12465
12466         DELAY(1000 * 5);
12467
12468         /* PART1 - Reset both phys */
12469         for (port = PORT_MAX - 1; port >= PORT_0; port--) {
12470                 uint32_t shmem_base, shmem2_base;
12471
12472                 /* In E2, same phy is using for port0 of the two paths */
12473                 if (CHIP_IS_E1x(sc)) {
12474                         shmem_base = shmem_base_path[0];
12475                         shmem2_base = shmem2_base_path[0];
12476                         port_of_path = port;
12477                 } else {
12478                         shmem_base = shmem_base_path[port];
12479                         shmem2_base = shmem2_base_path[port];
12480                         port_of_path = 0;
12481                 }
12482
12483                 /* Extract the ext phy address for the port */
12484                 if (elink_populate_phy(sc, phy_index, shmem_base, shmem2_base,
12485                                        port_of_path, &phy[port]) !=
12486                     ELINK_STATUS_OK) {
12487                         PMD_DRV_LOG(DEBUG, "populate phy failed");
12488                         return ELINK_STATUS_ERROR;
12489                 }
12490                 /* disable attentions */
12491                 elink_bits_dis(sc, NIG_REG_MASK_INTERRUPT_PORT0 +
12492                                port_of_path * 4,
12493                                (ELINK_NIG_MASK_XGXS0_LINK_STATUS |
12494                                 ELINK_NIG_MASK_XGXS0_LINK10G |
12495                                 ELINK_NIG_MASK_SERDES0_LINK_STATUS |
12496                                 ELINK_NIG_MASK_MI_INT));
12497
12498                 /* Reset the phy */
12499                 elink_cl45_write(sc, &phy[port],
12500                                  MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 1 << 15);
12501         }
12502
12503         /* Add delay of 150ms after reset */
12504         DELAY(1000 * 150);
12505         if (phy[PORT_0].addr & 0x1) {
12506                 phy_blk[PORT_0] = &(phy[PORT_1]);
12507                 phy_blk[PORT_1] = &(phy[PORT_0]);
12508         } else {
12509                 phy_blk[PORT_0] = &(phy[PORT_0]);
12510                 phy_blk[PORT_1] = &(phy[PORT_1]);
12511         }
12512         /* PART2 - Download firmware to both phys */
12513         for (port = PORT_MAX - 1; port >= PORT_0; port--) {
12514                 if (CHIP_IS_E1x(sc))
12515                         port_of_path = port;
12516                 else
12517                         port_of_path = 0;
12518                 PMD_DRV_LOG(DEBUG, "Loading spirom for phy address 0x%x",
12519                             phy_blk[port]->addr);
12520                 if (elink_8073_8727_external_rom_boot(sc, phy_blk[port],
12521                                                       port_of_path))
12522                         return ELINK_STATUS_ERROR;
12523                 /* Disable PHY transmitter output */
12524                 elink_cl45_write(sc, phy_blk[port],
12525                                  MDIO_PMA_DEVAD, MDIO_PMA_REG_TX_DISABLE, 1);
12526
12527         }
12528         return ELINK_STATUS_OK;
12529 }
12530
12531 static elink_status_t elink_84833_common_init_phy(struct bnx2x_softc *sc,
12532                                                   uint32_t shmem_base_path[],
12533                                                   __rte_unused uint32_t
12534                                                   shmem2_base_path[],
12535                                                   __rte_unused uint8_t
12536                                                   phy_index, uint32_t chip_id)
12537 {
12538         uint8_t reset_gpios;
12539         reset_gpios = elink_84833_get_reset_gpios(sc, shmem_base_path, chip_id);
12540         elink_cb_gpio_mult_write(sc, reset_gpios,
12541                                  MISC_REGISTERS_GPIO_OUTPUT_LOW);
12542         DELAY(10);
12543         elink_cb_gpio_mult_write(sc, reset_gpios,
12544                                  MISC_REGISTERS_GPIO_OUTPUT_HIGH);
12545         PMD_DRV_LOG(DEBUG, "84833 reset pulse on pin values 0x%x", reset_gpios);
12546         return ELINK_STATUS_OK;
12547 }
12548
12549 static elink_status_t elink_ext_phy_common_init(struct bnx2x_softc *sc,
12550                                                 uint32_t shmem_base_path[],
12551                                                 uint32_t shmem2_base_path[],
12552                                                 uint8_t phy_index,
12553                                                 uint32_t ext_phy_type,
12554                                                 uint32_t chip_id)
12555 {
12556         elink_status_t rc = ELINK_STATUS_OK;
12557
12558         switch (ext_phy_type) {
12559         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X8073:
12560                 rc = elink_8073_common_init_phy(sc, shmem_base_path,
12561                                                 shmem2_base_path,
12562                                                 phy_index, chip_id);
12563                 break;
12564         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X8722:
12565         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X8727:
12566         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X8727_NOC:
12567                 rc = elink_8727_common_init_phy(sc, shmem_base_path,
12568                                                 shmem2_base_path,
12569                                                 phy_index, chip_id);
12570                 break;
12571
12572         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X8726:
12573                 /* GPIO1 affects both ports, so there's need to pull
12574                  * it for single port alone
12575                  */
12576                 rc = elink_8726_common_init_phy(sc, shmem_base_path,
12577                                                 shmem2_base_path,
12578                                                 phy_index, chip_id);
12579                 break;
12580         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X84833:
12581         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X84834:
12582                 /* GPIO3's are linked, and so both need to be toggled
12583                  * to obtain required 2us pulse.
12584                  */
12585                 rc = elink_84833_common_init_phy(sc, shmem_base_path,
12586                                                  shmem2_base_path,
12587                                                  phy_index, chip_id);
12588                 break;
12589         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE:
12590                 rc = ELINK_STATUS_ERROR;
12591                 break;
12592         default:
12593                 PMD_DRV_LOG(DEBUG,
12594                             "ext_phy 0x%x common init not required",
12595                             ext_phy_type);
12596                 break;
12597         }
12598
12599         if (rc != ELINK_STATUS_OK)
12600                 elink_cb_event_log(sc, ELINK_LOG_ID_PHY_UNINITIALIZED, 0);      // "Warning: PHY was not initialized,"
12601         // " Port %d",
12602
12603         return rc;
12604 }
12605
12606 elink_status_t elink_common_init_phy(struct bnx2x_softc * sc,
12607                                      uint32_t shmem_base_path[],
12608                                      uint32_t shmem2_base_path[],
12609                                      uint32_t chip_id,
12610                                      __rte_unused uint8_t one_port_enabled)
12611 {
12612         elink_status_t rc = ELINK_STATUS_OK;
12613         uint32_t phy_ver, val;
12614         uint8_t phy_index = 0;
12615         uint32_t ext_phy_type, ext_phy_config;
12616
12617         elink_set_mdio_clk(sc, GRCBASE_EMAC0);
12618         elink_set_mdio_clk(sc, GRCBASE_EMAC1);
12619         PMD_DRV_LOG(DEBUG, "Begin common phy init");
12620         if (CHIP_IS_E3(sc)) {
12621                 /* Enable EPIO */
12622                 val = REG_RD(sc, MISC_REG_GEN_PURP_HWG);
12623                 REG_WR(sc, MISC_REG_GEN_PURP_HWG, val | 1);
12624         }
12625         /* Check if common init was already done */
12626         phy_ver = REG_RD(sc, shmem_base_path[0] +
12627                          offsetof(struct shmem_region,
12628                                   port_mb[PORT_0].ext_phy_fw_version));
12629         if (phy_ver) {
12630                 PMD_DRV_LOG(DEBUG, "Not doing common init; phy ver is 0x%x",
12631                             phy_ver);
12632                 return ELINK_STATUS_OK;
12633         }
12634
12635         /* Read the ext_phy_type for arbitrary port(0) */
12636         for (phy_index = ELINK_EXT_PHY1; phy_index < ELINK_MAX_PHYS;
12637              phy_index++) {
12638                 ext_phy_config = elink_get_ext_phy_config(sc,
12639                                                           shmem_base_path[0],
12640                                                           phy_index, 0);
12641                 ext_phy_type = ELINK_XGXS_EXT_PHY_TYPE(ext_phy_config);
12642                 rc |= elink_ext_phy_common_init(sc, shmem_base_path,
12643                                                 shmem2_base_path,
12644                                                 phy_index, ext_phy_type,
12645                                                 chip_id);
12646         }
12647         return rc;
12648 }
12649
12650 static void elink_check_over_curr(struct elink_params *params,
12651                                   struct elink_vars *vars)
12652 {
12653         struct bnx2x_softc *sc = params->sc;
12654         uint32_t cfg_pin;
12655         uint8_t port = params->port;
12656         uint32_t pin_val;
12657
12658         cfg_pin = (REG_RD(sc, params->shmem_base +
12659                           offsetof(struct shmem_region,
12660                                    dev_info.port_hw_config[port].
12661                                    e3_cmn_pin_cfg1)) &
12662                    PORT_HW_CFG_E3_OVER_CURRENT_MASK) >>
12663             PORT_HW_CFG_E3_OVER_CURRENT_SHIFT;
12664
12665         /* Ignore check if no external input PIN available */
12666         if (elink_get_cfg_pin(sc, cfg_pin, &pin_val) != ELINK_STATUS_OK)
12667                 return;
12668
12669         if (!pin_val) {
12670                 if ((vars->phy_flags & PHY_OVER_CURRENT_FLAG) == 0) {
12671                         elink_cb_event_log(sc, ELINK_LOG_ID_OVER_CURRENT, params->port);        //"Error:  Power fault on Port %d has"
12672                         //  " been detected and the power to "
12673                         //  "that SFP+ module has been removed"
12674                         //  " to prevent failure of the card."
12675                         //  " Please remove the SFP+ module and"
12676                         //  " restart the system to clear this"
12677                         //  " error.",
12678                         vars->phy_flags |= PHY_OVER_CURRENT_FLAG;
12679                         elink_warpcore_power_module(params, 0);
12680                 }
12681         } else
12682                 vars->phy_flags &= ~PHY_OVER_CURRENT_FLAG;
12683 }
12684
12685 /* Returns 0 if no change occurred since last check; 1 otherwise. */
12686 static uint8_t elink_analyze_link_error(struct elink_params *params,
12687                                         struct elink_vars *vars,
12688                                         uint32_t status, uint32_t phy_flag,
12689                                         uint32_t link_flag, uint8_t notify)
12690 {
12691         struct bnx2x_softc *sc = params->sc;
12692         /* Compare new value with previous value */
12693         uint8_t led_mode;
12694         uint32_t old_status = (vars->phy_flags & phy_flag) ? 1 : 0;
12695
12696         if ((status ^ old_status) == 0)
12697                 return 0;
12698
12699         /* If values differ */
12700         switch (phy_flag) {
12701         case PHY_HALF_OPEN_CONN_FLAG:
12702                 PMD_DRV_LOG(DEBUG, "Analyze Remote Fault");
12703                 break;
12704         case PHY_SFP_TX_FAULT_FLAG:
12705                 PMD_DRV_LOG(DEBUG, "Analyze TX Fault");
12706                 break;
12707         default:
12708                 PMD_DRV_LOG(DEBUG, "Analyze UNKNOWN");
12709         }
12710         PMD_DRV_LOG(DEBUG, "Link changed:[%x %x]->%x", vars->link_up,
12711                     old_status, status);
12712
12713         /* a. Update shmem->link_status accordingly
12714          * b. Update elink_vars->link_up
12715          */
12716         if (status) {
12717                 vars->link_status &= ~LINK_STATUS_LINK_UP;
12718                 vars->link_status |= link_flag;
12719                 vars->link_up = 0;
12720                 vars->phy_flags |= phy_flag;
12721
12722                 /* activate nig drain */
12723                 REG_WR(sc, NIG_REG_EGRESS_DRAIN0_MODE + params->port * 4, 1);
12724                 /* Set LED mode to off since the PHY doesn't know about these
12725                  * errors
12726                  */
12727                 led_mode = ELINK_LED_MODE_OFF;
12728         } else {
12729                 vars->link_status |= LINK_STATUS_LINK_UP;
12730                 vars->link_status &= ~link_flag;
12731                 vars->link_up = 1;
12732                 vars->phy_flags &= ~phy_flag;
12733                 led_mode = ELINK_LED_MODE_OPER;
12734
12735                 /* Clear nig drain */
12736                 REG_WR(sc, NIG_REG_EGRESS_DRAIN0_MODE + params->port * 4, 0);
12737         }
12738         elink_sync_link(params, vars);
12739         /* Update the LED according to the link state */
12740         elink_set_led(params, vars, led_mode, ELINK_SPEED_10000);
12741
12742         /* Update link status in the shared memory */
12743         elink_update_mng(params, vars->link_status);
12744
12745         /* C. Trigger General Attention */
12746         vars->periodic_flags |= ELINK_PERIODIC_FLAGS_LINK_EVENT;
12747         if (notify)
12748                 elink_cb_notify_link_changed(sc);
12749
12750         return 1;
12751 }
12752
12753 /******************************************************************************
12754 * Description:
12755 *       This function checks for half opened connection change indication.
12756 *       When such change occurs, it calls the elink_analyze_link_error
12757 *       to check if Remote Fault is set or cleared. Reception of remote fault
12758 *       status message in the MAC indicates that the peer's MAC has detected
12759 *       a fault, for example, due to break in the TX side of fiber.
12760 *
12761 ******************************************************************************/
12762 static elink_status_t elink_check_half_open_conn(struct elink_params *params,
12763                                                  struct elink_vars *vars,
12764                                                  uint8_t notify)
12765 {
12766         struct bnx2x_softc *sc = params->sc;
12767         uint32_t lss_status = 0;
12768         uint32_t mac_base;
12769         /* In case link status is physically up @ 10G do */
12770         if (((vars->phy_flags & PHY_PHYSICAL_LINK_FLAG) == 0) ||
12771             (REG_RD(sc, NIG_REG_EGRESS_EMAC0_PORT + params->port * 4)))
12772                 return ELINK_STATUS_OK;
12773
12774         if (CHIP_IS_E3(sc) &&
12775             (REG_RD(sc, MISC_REG_RESET_REG_2) &
12776              (MISC_REGISTERS_RESET_REG_2_XMAC))) {
12777                 /* Check E3 XMAC */
12778                 /* Note that link speed cannot be queried here, since it may be
12779                  * zero while link is down. In case UMAC is active, LSS will
12780                  * simply not be set
12781                  */
12782                 mac_base = (params->port) ? GRCBASE_XMAC1 : GRCBASE_XMAC0;
12783
12784                 /* Clear stick bits (Requires rising edge) */
12785                 REG_WR(sc, mac_base + XMAC_REG_CLEAR_RX_LSS_STATUS, 0);
12786                 REG_WR(sc, mac_base + XMAC_REG_CLEAR_RX_LSS_STATUS,
12787                        XMAC_CLEAR_RX_LSS_STATUS_REG_CLEAR_LOCAL_FAULT_STATUS |
12788                        XMAC_CLEAR_RX_LSS_STATUS_REG_CLEAR_REMOTE_FAULT_STATUS);
12789                 if (REG_RD(sc, mac_base + XMAC_REG_RX_LSS_STATUS))
12790                         lss_status = 1;
12791
12792                 elink_analyze_link_error(params, vars, lss_status,
12793                                          PHY_HALF_OPEN_CONN_FLAG,
12794                                          LINK_STATUS_NONE, notify);
12795         } else if (REG_RD(sc, MISC_REG_RESET_REG_2) &
12796                    (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << params->port)) {
12797                 /* Check E1X / E2 BMAC */
12798                 uint32_t lss_status_reg;
12799                 uint32_t wb_data[2];
12800                 mac_base = params->port ? NIG_REG_INGRESS_BMAC1_MEM :
12801                     NIG_REG_INGRESS_BMAC0_MEM;
12802                 /*  Read BIGMAC_REGISTER_RX_LSS_STATUS */
12803                 if (CHIP_IS_E2(sc))
12804                         lss_status_reg = BIGMAC2_REGISTER_RX_LSS_STAT;
12805                 else
12806                         lss_status_reg = BIGMAC_REGISTER_RX_LSS_STATUS;
12807
12808                 REG_RD_DMAE(sc, mac_base + lss_status_reg, wb_data, 2);
12809                 lss_status = (wb_data[0] > 0);
12810
12811                 elink_analyze_link_error(params, vars, lss_status,
12812                                          PHY_HALF_OPEN_CONN_FLAG,
12813                                          LINK_STATUS_NONE, notify);
12814         }
12815         return ELINK_STATUS_OK;
12816 }
12817
12818 static void elink_sfp_tx_fault_detection(struct elink_phy *phy,
12819                                          struct elink_params *params,
12820                                          struct elink_vars *vars)
12821 {
12822         struct bnx2x_softc *sc = params->sc;
12823         uint32_t cfg_pin, value = 0;
12824         uint8_t led_change, port = params->port;
12825
12826         /* Get The SFP+ TX_Fault controlling pin ([eg]pio) */
12827         cfg_pin = (REG_RD(sc, params->shmem_base + offsetof(struct shmem_region,
12828                                                             dev_info.
12829                                                             port_hw_config
12830                                                             [port].
12831                                                             e3_cmn_pin_cfg)) &
12832                    PORT_HW_CFG_E3_TX_FAULT_MASK) >>
12833             PORT_HW_CFG_E3_TX_FAULT_SHIFT;
12834
12835         if (elink_get_cfg_pin(sc, cfg_pin, &value)) {
12836                 PMD_DRV_LOG(DEBUG, "Failed to read pin 0x%02x", cfg_pin);
12837                 return;
12838         }
12839
12840         led_change = elink_analyze_link_error(params, vars, value,
12841                                               PHY_SFP_TX_FAULT_FLAG,
12842                                               LINK_STATUS_SFP_TX_FAULT, 1);
12843
12844         if (led_change) {
12845                 /* Change TX_Fault led, set link status for further syncs */
12846                 uint8_t led_mode;
12847
12848                 if (vars->phy_flags & PHY_SFP_TX_FAULT_FLAG) {
12849                         led_mode = MISC_REGISTERS_GPIO_HIGH;
12850                         vars->link_status |= LINK_STATUS_SFP_TX_FAULT;
12851                 } else {
12852                         led_mode = MISC_REGISTERS_GPIO_LOW;
12853                         vars->link_status &= ~LINK_STATUS_SFP_TX_FAULT;
12854                 }
12855
12856                 /* If module is unapproved, led should be on regardless */
12857                 if (!(phy->flags & ELINK_FLAGS_SFP_NOT_APPROVED)) {
12858                         PMD_DRV_LOG(DEBUG, "Change TX_Fault LED: ->%x",
12859                                     led_mode);
12860                         elink_set_e3_module_fault_led(params, led_mode);
12861                 }
12862         }
12863 }
12864
12865 static void elink_kr2_recovery(struct elink_params *params,
12866                                struct elink_vars *vars, struct elink_phy *phy)
12867 {
12868         PMD_DRV_LOG(DEBUG, "KR2 recovery");
12869
12870         elink_warpcore_enable_AN_KR2(phy, params, vars);
12871         elink_warpcore_restart_AN_KR(phy, params);
12872 }
12873
12874 static void elink_check_kr2_wa(struct elink_params *params,
12875                                struct elink_vars *vars, struct elink_phy *phy)
12876 {
12877         struct bnx2x_softc *sc = params->sc;
12878         uint16_t base_page, next_page, not_kr2_device, lane;
12879         int sigdet;
12880
12881         /* Once KR2 was disabled, wait 5 seconds before checking KR2 recovery
12882          * Since some switches tend to reinit the AN process and clear the
12883          * the advertised BP/NP after ~2 seconds causing the KR2 to be disabled
12884          * and recovered many times
12885          */
12886         if (vars->check_kr2_recovery_cnt > 0) {
12887                 vars->check_kr2_recovery_cnt--;
12888                 return;
12889         }
12890
12891         sigdet = elink_warpcore_get_sigdet(phy, params);
12892         if (!sigdet) {
12893                 if (!(vars->link_attr_sync & LINK_ATTR_SYNC_KR2_ENABLE)) {
12894                         elink_kr2_recovery(params, vars, phy);
12895                         PMD_DRV_LOG(DEBUG, "No sigdet");
12896                 }
12897                 return;
12898         }
12899
12900         lane = elink_get_warpcore_lane(params);
12901         CL22_WR_OVER_CL45(sc, phy, MDIO_REG_BANK_AER_BLOCK,
12902                           MDIO_AER_BLOCK_AER_REG, lane);
12903         elink_cl45_read(sc, phy, MDIO_AN_DEVAD,
12904                         MDIO_AN_REG_LP_AUTO_NEG, &base_page);
12905         elink_cl45_read(sc, phy, MDIO_AN_DEVAD,
12906                         MDIO_AN_REG_LP_AUTO_NEG2, &next_page);
12907         elink_set_aer_mmd(params, phy);
12908
12909         /* CL73 has not begun yet */
12910         if (base_page == 0) {
12911                 if (!(vars->link_attr_sync & LINK_ATTR_SYNC_KR2_ENABLE)) {
12912                         elink_kr2_recovery(params, vars, phy);
12913                         PMD_DRV_LOG(DEBUG, "No BP");
12914                 }
12915                 return;
12916         }
12917
12918         /* In case NP bit is not set in the BasePage, or it is set,
12919          * but only KX is advertised, declare this link partner as non-KR2
12920          * device.
12921          */
12922         not_kr2_device = (((base_page & 0x8000) == 0) ||
12923                           (((base_page & 0x8000) &&
12924                             ((next_page & 0xe0) == 0x20))));
12925
12926         /* In case KR2 is already disabled, check if we need to re-enable it */
12927         if (!(vars->link_attr_sync & LINK_ATTR_SYNC_KR2_ENABLE)) {
12928                 if (!not_kr2_device) {
12929                         PMD_DRV_LOG(DEBUG, "BP=0x%x, NP=0x%x", base_page,
12930                                     next_page);
12931                         elink_kr2_recovery(params, vars, phy);
12932                 }
12933                 return;
12934         }
12935         /* KR2 is enabled, but not KR2 device */
12936         if (not_kr2_device) {
12937                 /* Disable KR2 on both lanes */
12938                 PMD_DRV_LOG(DEBUG, "BP=0x%x, NP=0x%x", base_page, next_page);
12939                 elink_disable_kr2(params, vars, phy);
12940                 /* Restart AN on leading lane */
12941                 elink_warpcore_restart_AN_KR(phy, params);
12942                 return;
12943         }
12944 }
12945
12946 void elink_period_func(struct elink_params *params, struct elink_vars *vars)
12947 {
12948         uint16_t phy_idx;
12949         struct bnx2x_softc *sc = params->sc;
12950         for (phy_idx = ELINK_INT_PHY; phy_idx < ELINK_MAX_PHYS; phy_idx++) {
12951                 if (params->phy[phy_idx].flags & ELINK_FLAGS_TX_ERROR_CHECK) {
12952                         elink_set_aer_mmd(params, &params->phy[phy_idx]);
12953                         if (elink_check_half_open_conn(params, vars, 1) !=
12954                             ELINK_STATUS_OK) {
12955                                 PMD_DRV_LOG(DEBUG, "Fault detection failed");
12956                         }
12957                         break;
12958                 }
12959         }
12960
12961         if (CHIP_IS_E3(sc)) {
12962                 struct elink_phy *phy = &params->phy[ELINK_INT_PHY];
12963                 elink_set_aer_mmd(params, phy);
12964                 if ((phy->supported & ELINK_SUPPORTED_20000baseKR2_Full) &&
12965                     (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_20G))
12966                         elink_check_kr2_wa(params, vars, phy);
12967                 elink_check_over_curr(params, vars);
12968                 if (vars->rx_tx_asic_rst)
12969                         elink_warpcore_config_runtime(phy, params, vars);
12970
12971                 if ((REG_RD(sc, params->shmem_base +
12972                             offsetof(struct shmem_region,
12973                                      dev_info.port_hw_config[params->port].
12974                                      default_cfg))
12975                      & PORT_HW_CFG_NET_SERDES_IF_MASK) ==
12976                     PORT_HW_CFG_NET_SERDES_IF_SFI) {
12977                         if (elink_is_sfp_module_plugged(params)) {
12978                                 elink_sfp_tx_fault_detection(phy, params, vars);
12979                         } else if (vars->link_status & LINK_STATUS_SFP_TX_FAULT) {
12980                                 /* Clean trail, interrupt corrects the leds */
12981                                 vars->link_status &= ~LINK_STATUS_SFP_TX_FAULT;
12982                                 vars->phy_flags &= ~PHY_SFP_TX_FAULT_FLAG;
12983                                 /* Update link status in the shared memory */
12984                                 elink_update_mng(params, vars->link_status);
12985                         }
12986                 }
12987         }
12988 }
12989
12990 uint8_t elink_fan_failure_det_req(struct bnx2x_softc *sc,
12991                                   uint32_t shmem_base,
12992                                   uint32_t shmem2_base, uint8_t port)
12993 {
12994         uint8_t phy_index, fan_failure_det_req = 0;
12995         struct elink_phy phy;
12996         for (phy_index = ELINK_EXT_PHY1; phy_index < ELINK_MAX_PHYS;
12997              phy_index++) {
12998                 if (elink_populate_phy(sc, phy_index, shmem_base, shmem2_base,
12999                                        port, &phy)
13000                     != ELINK_STATUS_OK) {
13001                         PMD_DRV_LOG(DEBUG, "populate phy failed");
13002                         return 0;
13003                 }
13004                 fan_failure_det_req |= (phy.flags &
13005                                         ELINK_FLAGS_FAN_FAILURE_DET_REQ);
13006         }
13007         return fan_failure_det_req;
13008 }
13009
13010 void elink_hw_reset_phy(struct elink_params *params)
13011 {
13012         uint8_t phy_index;
13013         struct bnx2x_softc *sc = params->sc;
13014         elink_update_mng(params, 0);
13015         elink_bits_dis(sc, NIG_REG_MASK_INTERRUPT_PORT0 + params->port * 4,
13016                        (ELINK_NIG_MASK_XGXS0_LINK_STATUS |
13017                         ELINK_NIG_MASK_XGXS0_LINK10G |
13018                         ELINK_NIG_MASK_SERDES0_LINK_STATUS |
13019                         ELINK_NIG_MASK_MI_INT));
13020
13021         for (phy_index = ELINK_INT_PHY; phy_index < ELINK_MAX_PHYS; phy_index++) {
13022                 if (params->phy[phy_index].hw_reset) {
13023                         params->phy[phy_index].hw_reset(&params->phy[phy_index],
13024                                                         params);
13025                         params->phy[phy_index] = phy_null;
13026                 }
13027         }
13028 }
13029
13030 void elink_init_mod_abs_int(struct bnx2x_softc *sc, struct elink_vars *vars,
13031                             __rte_unused uint32_t chip_id, uint32_t shmem_base,
13032                             uint32_t shmem2_base, uint8_t port)
13033 {
13034         uint8_t gpio_num = 0xff, gpio_port = 0xff, phy_index;
13035         uint32_t val;
13036         uint32_t offset, aeu_mask, swap_val, swap_override, sync_offset;
13037         if (CHIP_IS_E3(sc)) {
13038                 if (elink_get_mod_abs_int_cfg(sc,
13039                                               shmem_base,
13040                                               port,
13041                                               &gpio_num,
13042                                               &gpio_port) != ELINK_STATUS_OK)
13043                         return;
13044         } else {
13045                 struct elink_phy phy;
13046                 for (phy_index = ELINK_EXT_PHY1; phy_index < ELINK_MAX_PHYS;
13047                      phy_index++) {
13048                         if (elink_populate_phy(sc, phy_index, shmem_base,
13049                                                shmem2_base, port, &phy)
13050                             != ELINK_STATUS_OK) {
13051                                 PMD_DRV_LOG(DEBUG, "populate phy failed");
13052                                 return;
13053                         }
13054                         if (phy.type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X8726) {
13055                                 gpio_num = MISC_REGISTERS_GPIO_3;
13056                                 gpio_port = port;
13057                                 break;
13058                         }
13059                 }
13060         }
13061
13062         if (gpio_num == 0xff)
13063                 return;
13064
13065         /* Set GPIO3 to trigger SFP+ module insertion/removal */
13066         elink_cb_gpio_write(sc, gpio_num, MISC_REGISTERS_GPIO_INPUT_HI_Z,
13067                             gpio_port);
13068
13069         swap_val = REG_RD(sc, NIG_REG_PORT_SWAP);
13070         swap_override = REG_RD(sc, NIG_REG_STRAP_OVERRIDE);
13071         gpio_port ^= (swap_val && swap_override);
13072
13073         vars->aeu_int_mask = AEU_INPUTS_ATTN_BITS_GPIO0_FUNCTION_0 <<
13074             (gpio_num + (gpio_port << 2));
13075
13076         sync_offset = shmem_base +
13077             offsetof(struct shmem_region,
13078                      dev_info.port_hw_config[port].aeu_int_mask);
13079         REG_WR(sc, sync_offset, vars->aeu_int_mask);
13080
13081         PMD_DRV_LOG(DEBUG, "Setting MOD_ABS (GPIO%d_P%d) AEU to 0x%x",
13082                     gpio_num, gpio_port, vars->aeu_int_mask);
13083
13084         if (port == 0)
13085                 offset = MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0;
13086         else
13087                 offset = MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0;
13088
13089         /* Open appropriate AEU for interrupts */
13090         aeu_mask = REG_RD(sc, offset);
13091         aeu_mask |= vars->aeu_int_mask;
13092         REG_WR(sc, offset, aeu_mask);
13093
13094         /* Enable the GPIO to trigger interrupt */
13095         val = REG_RD(sc, MISC_REG_GPIO_EVENT_EN);
13096         val |= 1 << (gpio_num + (gpio_port << 2));
13097         REG_WR(sc, MISC_REG_GPIO_EVENT_EN, val);
13098 }