drivers/net/bnxt/bnxt_ethdev.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2014-2018 Broadcom
   3  * All rights reserved.
   4  */
   5
   6 #include <inttypes.h>
   7 #include <stdbool.h>
   8
   9 #include <rte_dev.h>
  10 #include <rte_ethdev_driver.h>
  11 #include <rte_ethdev_pci.h>
  12 #include <rte_malloc.h>
  13 #include <rte_cycles.h>
  14 #include <rte_alarm.h>
  15
  16 #include "bnxt.h"
  17 #include "bnxt_cpr.h"
  18 #include "bnxt_filter.h"
  19 #include "bnxt_hwrm.h"
  20 #include "bnxt_irq.h"
  21 #include "bnxt_ring.h"
  22 #include "bnxt_rxq.h"
  23 #include "bnxt_rxr.h"
  24 #include "bnxt_stats.h"
  25 #include "bnxt_txq.h"
  26 #include "bnxt_txr.h"
  27 #include "bnxt_vnic.h"
  28 #include "hsi_struct_def_dpdk.h"
  29 #include "bnxt_nvm_defs.h"
  30 #include "bnxt_util.h"
  31
  32 #define DRV_MODULE_NAME         "bnxt"
  33 static const char bnxt_version[] =
  34         "Broadcom NetXtreme driver " DRV_MODULE_NAME;
  35 int bnxt_logtype_driver;
  36
  37 #define PCI_VENDOR_ID_BROADCOM 0x14E4
  38
  39 #define BROADCOM_DEV_ID_STRATUS_NIC_VF1 0x1606
  40 #define BROADCOM_DEV_ID_STRATUS_NIC_VF2 0x1609
  41 #define BROADCOM_DEV_ID_STRATUS_NIC 0x1614
  42 #define BROADCOM_DEV_ID_57414_VF 0x16c1
  43 #define BROADCOM_DEV_ID_57301 0x16c8
  44 #define BROADCOM_DEV_ID_57302 0x16c9
  45 #define BROADCOM_DEV_ID_57304_PF 0x16ca
  46 #define BROADCOM_DEV_ID_57304_VF 0x16cb
  47 #define BROADCOM_DEV_ID_57417_MF 0x16cc
  48 #define BROADCOM_DEV_ID_NS2 0x16cd
  49 #define BROADCOM_DEV_ID_57311 0x16ce
  50 #define BROADCOM_DEV_ID_57312 0x16cf
  51 #define BROADCOM_DEV_ID_57402 0x16d0
  52 #define BROADCOM_DEV_ID_57404 0x16d1
  53 #define BROADCOM_DEV_ID_57406_PF 0x16d2
  54 #define BROADCOM_DEV_ID_57406_VF 0x16d3
  55 #define BROADCOM_DEV_ID_57402_MF 0x16d4
  56 #define BROADCOM_DEV_ID_57407_RJ45 0x16d5
  57 #define BROADCOM_DEV_ID_57412 0x16d6
  58 #define BROADCOM_DEV_ID_57414 0x16d7
  59 #define BROADCOM_DEV_ID_57416_RJ45 0x16d8
  60 #define BROADCOM_DEV_ID_57417_RJ45 0x16d9
  61 #define BROADCOM_DEV_ID_5741X_VF 0x16dc
  62 #define BROADCOM_DEV_ID_57412_MF 0x16de
  63 #define BROADCOM_DEV_ID_57314 0x16df
  64 #define BROADCOM_DEV_ID_57317_RJ45 0x16e0
  65 #define BROADCOM_DEV_ID_5731X_VF 0x16e1
  66 #define BROADCOM_DEV_ID_57417_SFP 0x16e2
  67 #define BROADCOM_DEV_ID_57416_SFP 0x16e3
  68 #define BROADCOM_DEV_ID_57317_SFP 0x16e4
  69 #define BROADCOM_DEV_ID_57404_MF 0x16e7
  70 #define BROADCOM_DEV_ID_57406_MF 0x16e8
  71 #define BROADCOM_DEV_ID_57407_SFP 0x16e9
  72 #define BROADCOM_DEV_ID_57407_MF 0x16ea
  73 #define BROADCOM_DEV_ID_57414_MF 0x16ec
  74 #define BROADCOM_DEV_ID_57416_MF 0x16ee
  75 #define BROADCOM_DEV_ID_57508 0x1750
  76 #define BROADCOM_DEV_ID_57504 0x1751
  77 #define BROADCOM_DEV_ID_57502 0x1752
  78 #define BROADCOM_DEV_ID_57500_VF1 0x1806
  79 #define BROADCOM_DEV_ID_57500_VF2 0x1807
  80 #define BROADCOM_DEV_ID_58802 0xd802
  81 #define BROADCOM_DEV_ID_58804 0xd804
  82 #define BROADCOM_DEV_ID_58808 0x16f0
  83 #define BROADCOM_DEV_ID_58802_VF 0xd800
  84
  85 static const struct rte_pci_id bnxt_pci_id_map[] = {
  86         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM,
  87                          BROADCOM_DEV_ID_STRATUS_NIC_VF1) },
  88         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM,
  89                          BROADCOM_DEV_ID_STRATUS_NIC_VF2) },
  90         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_STRATUS_NIC) },
  91         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414_VF) },
  92         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57301) },
  93         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57302) },
  94         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57304_PF) },
  95         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57304_VF) },
  96         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_NS2) },
  97         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57402) },
  98         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57404) },
  99         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57406_PF) },
 100         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57406_VF) },
 101         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57402_MF) },
 102         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57407_RJ45) },
 103         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57404_MF) },
 104         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57406_MF) },
 105         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57407_SFP) },
 106         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57407_MF) },
 107         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_5741X_VF) },
 108         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_5731X_VF) },
 109         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57314) },
 110         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_MF) },
 111         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57311) },
 112         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57312) },
 113         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57412) },
 114         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414) },
 115         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_RJ45) },
 116         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_RJ45) },
 117         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57412_MF) },
 118         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57317_RJ45) },
 119         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_SFP) },
 120         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_SFP) },
 121         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57317_SFP) },
 122         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414_MF) },
 123         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_MF) },
 124         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58802) },
 125         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58804) },
 126         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58808) },
 127         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58802_VF) },
 128         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57508) },
 129         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57504) },
 130         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57502) },
 131         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57500_VF1) },
 132         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57500_VF2) },
 133         { .vendor_id = 0, /* sentinel */ },
 134 };
 135
 136 #define BNXT_ETH_RSS_SUPPORT (  \
 137         ETH_RSS_IPV4 |          \
 138         ETH_RSS_NONFRAG_IPV4_TCP |      \
 139         ETH_RSS_NONFRAG_IPV4_UDP |      \
 140         ETH_RSS_IPV6 |          \
 141         ETH_RSS_NONFRAG_IPV6_TCP |      \
 142         ETH_RSS_NONFRAG_IPV6_UDP)
 143
 144 #define BNXT_DEV_TX_OFFLOAD_SUPPORT (DEV_TX_OFFLOAD_VLAN_INSERT | \
 145                                      DEV_TX_OFFLOAD_IPV4_CKSUM | \
 146                                      DEV_TX_OFFLOAD_TCP_CKSUM | \
 147                                      DEV_TX_OFFLOAD_UDP_CKSUM | \
 148                                      DEV_TX_OFFLOAD_TCP_TSO | \
 149                                      DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM | \
 150                                      DEV_TX_OFFLOAD_VXLAN_TNL_TSO | \
 151                                      DEV_TX_OFFLOAD_GRE_TNL_TSO | \
 152                                      DEV_TX_OFFLOAD_IPIP_TNL_TSO | \
 153                                      DEV_TX_OFFLOAD_GENEVE_TNL_TSO | \
 154                                      DEV_TX_OFFLOAD_MULTI_SEGS)
 155
 156 #define BNXT_DEV_RX_OFFLOAD_SUPPORT (DEV_RX_OFFLOAD_VLAN_FILTER | \
 157                                      DEV_RX_OFFLOAD_VLAN_STRIP | \
 158                                      DEV_RX_OFFLOAD_IPV4_CKSUM | \
 159                                      DEV_RX_OFFLOAD_UDP_CKSUM | \
 160                                      DEV_RX_OFFLOAD_TCP_CKSUM | \
 161                                      DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM | \
 162                                      DEV_RX_OFFLOAD_JUMBO_FRAME | \
 163                                      DEV_RX_OFFLOAD_KEEP_CRC | \
 164                                      DEV_RX_OFFLOAD_TCP_LRO)
 165
 166 static int bnxt_vlan_offload_set_op(struct rte_eth_dev *dev, int mask);
 167 static void bnxt_print_link_info(struct rte_eth_dev *eth_dev);
 168 static int bnxt_mtu_set_op(struct rte_eth_dev *eth_dev, uint16_t new_mtu);
 169 static int bnxt_dev_uninit(struct rte_eth_dev *eth_dev);
 170 static int bnxt_init_resources(struct bnxt *bp, bool reconfig_dev);
 171 static int bnxt_uninit_resources(struct bnxt *bp, bool reconfig_dev);
 172 static void bnxt_cancel_fw_health_check(struct bnxt *bp);
 173
 174 int is_bnxt_in_error(struct bnxt *bp)
 175 {
 176         if (bp->flags & BNXT_FLAG_FATAL_ERROR)
 177                 return -EIO;
 178         if (bp->flags & BNXT_FLAG_FW_RESET)
 179                 return -EBUSY;
 180
 181         return 0;
 182 }
 183
 184 /***********************/
 185
 186 /*
 187  * High level utility functions
 188  */
 189
 190 static uint16_t bnxt_rss_ctxts(const struct bnxt *bp)
 191 {
 192         if (!BNXT_CHIP_THOR(bp))
 193                 return 1;
 194
 195         return RTE_ALIGN_MUL_CEIL(bp->rx_nr_rings,
 196                                   BNXT_RSS_ENTRIES_PER_CTX_THOR) /
 197                                     BNXT_RSS_ENTRIES_PER_CTX_THOR;
 198 }
 199
 200 static uint16_t  bnxt_rss_hash_tbl_size(const struct bnxt *bp)
 201 {
 202         if (!BNXT_CHIP_THOR(bp))
 203                 return HW_HASH_INDEX_SIZE;
 204
 205         return bnxt_rss_ctxts(bp) * BNXT_RSS_ENTRIES_PER_CTX_THOR;
 206 }
 207
 208 static void bnxt_free_mem(struct bnxt *bp, bool reconfig)
 209 {
 210         bnxt_free_filter_mem(bp);
 211         bnxt_free_vnic_attributes(bp);
 212         bnxt_free_vnic_mem(bp);
 213
 214         /* tx/rx rings are configured as part of *_queue_setup callbacks.
 215          * If the number of rings change across fw update,
 216          * we don't have much choice except to warn the user.
 217          */
 218         if (!reconfig) {
 219                 bnxt_free_stats(bp);
 220                 bnxt_free_tx_rings(bp);
 221                 bnxt_free_rx_rings(bp);
 222         }
 223         bnxt_free_async_cp_ring(bp);
 224 }
 225
 226 static int bnxt_alloc_mem(struct bnxt *bp, bool reconfig)
 227 {
 228         int rc;
 229
 230         rc = bnxt_alloc_ring_grps(bp);
 231         if (rc)
 232                 goto alloc_mem_err;
 233
 234         rc = bnxt_alloc_async_ring_struct(bp);
 235         if (rc)
 236                 goto alloc_mem_err;
 237
 238         rc = bnxt_alloc_vnic_mem(bp);
 239         if (rc)
 240                 goto alloc_mem_err;
 241
 242         rc = bnxt_alloc_vnic_attributes(bp);
 243         if (rc)
 244                 goto alloc_mem_err;
 245
 246         rc = bnxt_alloc_filter_mem(bp);
 247         if (rc)
 248                 goto alloc_mem_err;
 249
 250         rc = bnxt_alloc_async_cp_ring(bp);
 251         if (rc)
 252                 goto alloc_mem_err;
 253
 254         return 0;
 255
 256 alloc_mem_err:
 257         bnxt_free_mem(bp, reconfig);
 258         return rc;
 259 }
 260
 261 static int bnxt_init_chip(struct bnxt *bp)
 262 {
 263         struct bnxt_rx_queue *rxq;
 264         struct rte_eth_link new;
 265         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(bp->eth_dev);
 266         struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
 267         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
 268         uint64_t rx_offloads = dev_conf->rxmode.offloads;
 269         uint32_t intr_vector = 0;
 270         uint32_t queue_id, base = BNXT_MISC_VEC_ID;
 271         uint32_t vec = BNXT_MISC_VEC_ID;
 272         unsigned int i, j;
 273         int rc;
 274
 275         if (bp->eth_dev->data->mtu > RTE_ETHER_MTU) {
 276                 bp->eth_dev->data->dev_conf.rxmode.offloads |=
 277                         DEV_RX_OFFLOAD_JUMBO_FRAME;
 278                 bp->flags |= BNXT_FLAG_JUMBO;
 279         } else {
 280                 bp->eth_dev->data->dev_conf.rxmode.offloads &=
 281                         ~DEV_RX_OFFLOAD_JUMBO_FRAME;
 282                 bp->flags &= ~BNXT_FLAG_JUMBO;
 283         }
 284
 285         /* THOR does not support ring groups.
 286          * But we will use the array to save RSS context IDs.
 287          */
 288         if (BNXT_CHIP_THOR(bp))
 289                 bp->max_ring_grps = BNXT_MAX_RSS_CTXTS_THOR;
 290
 291         rc = bnxt_alloc_all_hwrm_stat_ctxs(bp);
 292         if (rc) {
 293                 PMD_DRV_LOG(ERR, "HWRM stat ctx alloc failure rc: %x\n", rc);
 294                 goto err_out;
 295         }
 296
 297         rc = bnxt_alloc_hwrm_rings(bp);
 298         if (rc) {
 299                 PMD_DRV_LOG(ERR, "HWRM ring alloc failure rc: %x\n", rc);
 300                 goto err_out;
 301         }
 302
 303         rc = bnxt_alloc_all_hwrm_ring_grps(bp);
 304         if (rc) {
 305                 PMD_DRV_LOG(ERR, "HWRM ring grp alloc failure: %x\n", rc);
 306                 goto err_out;
 307         }
 308
 309         rc = bnxt_mq_rx_configure(bp);
 310         if (rc) {
 311                 PMD_DRV_LOG(ERR, "MQ mode configure failure rc: %x\n", rc);
 312                 goto err_out;
 313         }
 314
 315         /* VNIC configuration */
 316         for (i = 0; i < bp->nr_vnics; i++) {
 317                 struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
 318                 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
 319                 uint32_t size = sizeof(*vnic->fw_grp_ids) * bp->max_ring_grps;
 320
 321                 vnic->fw_grp_ids = rte_zmalloc("vnic_fw_grp_ids", size, 0);
 322                 if (!vnic->fw_grp_ids) {
 323                         PMD_DRV_LOG(ERR,
 324                                     "Failed to alloc %d bytes for group ids\n",
 325                                     size);
 326                         rc = -ENOMEM;
 327                         goto err_out;
 328                 }
 329                 memset(vnic->fw_grp_ids, -1, size);
 330
 331                 PMD_DRV_LOG(DEBUG, "vnic[%d] = %p vnic->fw_grp_ids = %p\n",
 332                             i, vnic, vnic->fw_grp_ids);
 333
 334                 rc = bnxt_hwrm_vnic_alloc(bp, vnic);
 335                 if (rc) {
 336                         PMD_DRV_LOG(ERR, "HWRM vnic %d alloc failure rc: %x\n",
 337                                 i, rc);
 338                         goto err_out;
 339                 }
 340
 341                 /* Alloc RSS context only if RSS mode is enabled */
 342                 if (dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS) {
 343                         int j, nr_ctxs = bnxt_rss_ctxts(bp);
 344
 345                         rc = 0;
 346                         for (j = 0; j < nr_ctxs; j++) {
 347                                 rc = bnxt_hwrm_vnic_ctx_alloc(bp, vnic, j);
 348                                 if (rc)
 349                                         break;
 350                         }
 351                         if (rc) {
 352                                 PMD_DRV_LOG(ERR,
 353                                   "HWRM vnic %d ctx %d alloc failure rc: %x\n",
 354                                   i, j, rc);
 355                                 goto err_out;
 356                         }
 357                         vnic->num_lb_ctxts = nr_ctxs;
 358                 }
 359
 360                 /*
 361                  * Firmware sets pf pair in default vnic cfg. If the VLAN strip
 362                  * setting is not available at this time, it will not be
 363                  * configured correctly in the CFA.
 364                  */
 365                 if (rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
 366                         vnic->vlan_strip = true;
 367                 else
 368                         vnic->vlan_strip = false;
 369
 370                 rc = bnxt_hwrm_vnic_cfg(bp, vnic);
 371                 if (rc) {
 372                         PMD_DRV_LOG(ERR, "HWRM vnic %d cfg failure rc: %x\n",
 373                                 i, rc);
 374                         goto err_out;
 375                 }
 376
 377                 rc = bnxt_set_hwrm_vnic_filters(bp, vnic);
 378                 if (rc) {
 379                         PMD_DRV_LOG(ERR,
 380                                 "HWRM vnic %d filter failure rc: %x\n",
 381                                 i, rc);
 382                         goto err_out;
 383                 }
 384
 385                 for (j = 0; j < bp->rx_nr_rings; j++) {
 386                         rxq = bp->eth_dev->data->rx_queues[j];
 387
 388                         PMD_DRV_LOG(DEBUG,
 389                                     "rxq[%d]->vnic=%p vnic->fw_grp_ids=%p\n",
 390                                     j, rxq->vnic, rxq->vnic->fw_grp_ids);
 391
 392                         if (BNXT_HAS_RING_GRPS(bp) && rxq->rx_deferred_start)
 393                                 rxq->vnic->fw_grp_ids[j] = INVALID_HW_RING_ID;
 394                 }
 395
 396                 rc = bnxt_vnic_rss_configure(bp, vnic);
 397                 if (rc) {
 398                         PMD_DRV_LOG(ERR,
 399                                     "HWRM vnic set RSS failure rc: %x\n", rc);
 400                         goto err_out;
 401                 }
 402
 403                 bnxt_hwrm_vnic_plcmode_cfg(bp, vnic);
 404
 405                 if (bp->eth_dev->data->dev_conf.rxmode.offloads &
 406                     DEV_RX_OFFLOAD_TCP_LRO)
 407                         bnxt_hwrm_vnic_tpa_cfg(bp, vnic, 1);
 408                 else
 409                         bnxt_hwrm_vnic_tpa_cfg(bp, vnic, 0);
 410         }
 411         rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, &bp->vnic_info[0], 0, NULL);
 412         if (rc) {
 413                 PMD_DRV_LOG(ERR,
 414                         "HWRM cfa l2 rx mask failure rc: %x\n", rc);
 415                 goto err_out;
 416         }
 417
 418         /* check and configure queue intr-vector mapping */
 419         if ((rte_intr_cap_multiple(intr_handle) ||
 420              !RTE_ETH_DEV_SRIOV(bp->eth_dev).active) &&
 421             bp->eth_dev->data->dev_conf.intr_conf.rxq != 0) {
 422                 intr_vector = bp->eth_dev->data->nb_rx_queues;
 423                 PMD_DRV_LOG(DEBUG, "intr_vector = %d\n", intr_vector);
 424                 if (intr_vector > bp->rx_cp_nr_rings) {
 425                         PMD_DRV_LOG(ERR, "At most %d intr queues supported",
 426                                         bp->rx_cp_nr_rings);
 427                         return -ENOTSUP;
 428                 }
 429                 rc = rte_intr_efd_enable(intr_handle, intr_vector);
 430                 if (rc)
 431                         return rc;
 432         }
 433
 434         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
 435                 intr_handle->intr_vec =
 436                         rte_zmalloc("intr_vec",
 437                                     bp->eth_dev->data->nb_rx_queues *
 438                                     sizeof(int), 0);
 439                 if (intr_handle->intr_vec == NULL) {
 440                         PMD_DRV_LOG(ERR, "Failed to allocate %d rx_queues"
 441                                 " intr_vec", bp->eth_dev->data->nb_rx_queues);
 442                         rc = -ENOMEM;
 443                         goto err_disable;
 444                 }
 445                 PMD_DRV_LOG(DEBUG, "intr_handle->intr_vec = %p "
 446                         "intr_handle->nb_efd = %d intr_handle->max_intr = %d\n",
 447                          intr_handle->intr_vec, intr_handle->nb_efd,
 448                         intr_handle->max_intr);
 449                 for (queue_id = 0; queue_id < bp->eth_dev->data->nb_rx_queues;
 450                      queue_id++) {
 451                         intr_handle->intr_vec[queue_id] =
 452                                                         vec + BNXT_RX_VEC_START;
 453                         if (vec < base + intr_handle->nb_efd - 1)
 454                                 vec++;
 455                 }
 456         }
 457
 458         /* enable uio/vfio intr/eventfd mapping */
 459         rc = rte_intr_enable(intr_handle);
 460         if (rc)
 461                 goto err_free;
 462
 463         rc = bnxt_get_hwrm_link_config(bp, &new);
 464         if (rc) {
 465                 PMD_DRV_LOG(ERR, "HWRM Get link config failure rc: %x\n", rc);
 466                 goto err_free;
 467         }
 468
 469         if (!bp->link_info.link_up) {
 470                 rc = bnxt_set_hwrm_link_config(bp, true);
 471                 if (rc) {
 472                         PMD_DRV_LOG(ERR,
 473                                 "HWRM link config failure rc: %x\n", rc);
 474                         goto err_free;
 475                 }
 476         }
 477         bnxt_print_link_info(bp->eth_dev);
 478
 479         return 0;
 480
 481 err_free:
 482         rte_free(intr_handle->intr_vec);
 483 err_disable:
 484         rte_intr_efd_disable(intr_handle);
 485 err_out:
 486         /* Some of the error status returned by FW may not be from errno.h */
 487         if (rc > 0)
 488                 rc = -EIO;
 489
 490         return rc;
 491 }
 492
 493 static int bnxt_shutdown_nic(struct bnxt *bp)
 494 {
 495         bnxt_free_all_hwrm_resources(bp);
 496         bnxt_free_all_filters(bp);
 497         bnxt_free_all_vnics(bp);
 498         return 0;
 499 }
 500
 501 static int bnxt_init_nic(struct bnxt *bp)
 502 {
 503         int rc;
 504
 505         if (BNXT_HAS_RING_GRPS(bp)) {
 506                 rc = bnxt_init_ring_grps(bp);
 507                 if (rc)
 508                         return rc;
 509         }
 510
 511         bnxt_init_vnics(bp);
 512         bnxt_init_filters(bp);
 513
 514         return 0;
 515 }
 516
 517 /*
 518  * Device configuration and status function
 519  */
 520
 521 static int bnxt_dev_info_get_op(struct rte_eth_dev *eth_dev,
 522                                 struct rte_eth_dev_info *dev_info)
 523 {
 524         struct bnxt *bp = eth_dev->data->dev_private;
 525         uint16_t max_vnics, i, j, vpool, vrxq;
 526         unsigned int max_rx_rings;
 527         int rc;
 528
 529         rc = is_bnxt_in_error(bp);
 530         if (rc)
 531                 return rc;
 532
 533         /* MAC Specifics */
 534         dev_info->max_mac_addrs = bp->max_l2_ctx;
 535         dev_info->max_hash_mac_addrs = 0;
 536
 537         /* PF/VF specifics */
 538         if (BNXT_PF(bp))
 539                 dev_info->max_vfs = bp->pdev->max_vfs;
 540         max_rx_rings = RTE_MIN(bp->max_rx_rings, bp->max_stat_ctx);
 541         /* For the sake of symmetry, max_rx_queues = max_tx_queues */
 542         dev_info->max_rx_queues = max_rx_rings;
 543         dev_info->max_tx_queues = max_rx_rings;
 544         dev_info->reta_size = bnxt_rss_hash_tbl_size(bp);
 545         dev_info->hash_key_size = 40;
 546         max_vnics = bp->max_vnics;
 547
 548         /* Fast path specifics */
 549         dev_info->min_rx_bufsize = 1;
 550         dev_info->max_rx_pktlen = BNXT_MAX_MTU + RTE_ETHER_HDR_LEN +
 551                 RTE_ETHER_CRC_LEN + VLAN_TAG_SIZE * 2;
 552
 553         dev_info->rx_offload_capa = BNXT_DEV_RX_OFFLOAD_SUPPORT;
 554         if (bp->flags & BNXT_FLAG_PTP_SUPPORTED)
 555                 dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_TIMESTAMP;
 556         dev_info->tx_offload_capa = BNXT_DEV_TX_OFFLOAD_SUPPORT;
 557         dev_info->flow_type_rss_offloads = BNXT_ETH_RSS_SUPPORT;
 558
 559         /* *INDENT-OFF* */
 560         dev_info->default_rxconf = (struct rte_eth_rxconf) {
 561                 .rx_thresh = {
 562                         .pthresh = 8,
 563                         .hthresh = 8,
 564                         .wthresh = 0,
 565                 },
 566                 .rx_free_thresh = 32,
 567                 /* If no descriptors available, pkts are dropped by default */
 568                 .rx_drop_en = 1,
 569         };
 570
 571         dev_info->default_txconf = (struct rte_eth_txconf) {
 572                 .tx_thresh = {
 573                         .pthresh = 32,
 574                         .hthresh = 0,
 575                         .wthresh = 0,
 576                 },
 577                 .tx_free_thresh = 32,
 578                 .tx_rs_thresh = 32,
 579         };
 580         eth_dev->data->dev_conf.intr_conf.lsc = 1;
 581
 582         eth_dev->data->dev_conf.intr_conf.rxq = 1;
 583         dev_info->rx_desc_lim.nb_min = BNXT_MIN_RING_DESC;
 584         dev_info->rx_desc_lim.nb_max = BNXT_MAX_RX_RING_DESC;
 585         dev_info->tx_desc_lim.nb_min = BNXT_MIN_RING_DESC;
 586         dev_info->tx_desc_lim.nb_max = BNXT_MAX_TX_RING_DESC;
 587
 588         /* *INDENT-ON* */
 589
 590         /*
 591          * TODO: default_rxconf, default_txconf, rx_desc_lim, and tx_desc_lim
 592          *       need further investigation.
 593          */
 594
 595         /* VMDq resources */
 596         vpool = 64; /* ETH_64_POOLS */
 597         vrxq = 128; /* ETH_VMDQ_DCB_NUM_QUEUES */
 598         for (i = 0; i < 4; vpool >>= 1, i++) {
 599                 if (max_vnics > vpool) {
 600                         for (j = 0; j < 5; vrxq >>= 1, j++) {
 601                                 if (dev_info->max_rx_queues > vrxq) {
 602                                         if (vpool > vrxq)
 603                                                 vpool = vrxq;
 604                                         goto found;
 605                                 }
 606                         }
 607                         /* Not enough resources to support VMDq */
 608                         break;
 609                 }
 610         }
 611         /* Not enough resources to support VMDq */
 612         vpool = 0;
 613         vrxq = 0;
 614 found:
 615         dev_info->max_vmdq_pools = vpool;
 616         dev_info->vmdq_queue_num = vrxq;
 617
 618         dev_info->vmdq_pool_base = 0;
 619         dev_info->vmdq_queue_base = 0;
 620
 621         return 0;
 622 }
 623
 624 /* Configure the device based on the configuration provided */
 625 static int bnxt_dev_configure_op(struct rte_eth_dev *eth_dev)
 626 {
 627         struct bnxt *bp = eth_dev->data->dev_private;
 628         uint64_t rx_offloads = eth_dev->data->dev_conf.rxmode.offloads;
 629         int rc;
 630
 631         bp->rx_queues = (void *)eth_dev->data->rx_queues;
 632         bp->tx_queues = (void *)eth_dev->data->tx_queues;
 633         bp->tx_nr_rings = eth_dev->data->nb_tx_queues;
 634         bp->rx_nr_rings = eth_dev->data->nb_rx_queues;
 635
 636         rc = is_bnxt_in_error(bp);
 637         if (rc)
 638                 return rc;
 639
 640         if (BNXT_VF(bp) && (bp->flags & BNXT_FLAG_NEW_RM)) {
 641                 rc = bnxt_hwrm_check_vf_rings(bp);
 642                 if (rc) {
 643                         PMD_DRV_LOG(ERR, "HWRM insufficient resources\n");
 644                         return -ENOSPC;
 645                 }
 646
 647                 rc = bnxt_hwrm_func_reserve_vf_resc(bp, false);
 648                 if (rc) {
 649                         PMD_DRV_LOG(ERR, "HWRM resource alloc fail:%x\n", rc);
 650                         return -ENOSPC;
 651                 }
 652         } else {
 653                 /* legacy driver needs to get updated values */
 654                 rc = bnxt_hwrm_func_qcaps(bp);
 655                 if (rc) {
 656                         PMD_DRV_LOG(ERR, "hwrm func qcaps fail:%d\n", rc);
 657                         return rc;
 658                 }
 659         }
 660
 661         /* Inherit new configurations */
 662         if (eth_dev->data->nb_rx_queues > bp->max_rx_rings ||
 663             eth_dev->data->nb_tx_queues > bp->max_tx_rings ||
 664             eth_dev->data->nb_rx_queues + eth_dev->data->nb_tx_queues
 665                 + BNXT_NUM_ASYNC_CPR(bp) > bp->max_cp_rings ||
 666             eth_dev->data->nb_rx_queues + eth_dev->data->nb_tx_queues >
 667             bp->max_stat_ctx)
 668                 goto resource_error;
 669
 670         if (BNXT_HAS_RING_GRPS(bp) &&
 671             (uint32_t)(eth_dev->data->nb_rx_queues) > bp->max_ring_grps)
 672                 goto resource_error;
 673
 674         if (!(eth_dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_RSS) &&
 675             bp->max_vnics < eth_dev->data->nb_rx_queues)
 676                 goto resource_error;
 677
 678         bp->rx_cp_nr_rings = bp->rx_nr_rings;
 679         bp->tx_cp_nr_rings = bp->tx_nr_rings;
 680
 681         if (rx_offloads & DEV_RX_OFFLOAD_JUMBO_FRAME) {
 682                 eth_dev->data->mtu =
 683                         eth_dev->data->dev_conf.rxmode.max_rx_pkt_len -
 684                         RTE_ETHER_HDR_LEN - RTE_ETHER_CRC_LEN - VLAN_TAG_SIZE *
 685                         BNXT_NUM_VLANS;
 686                 bnxt_mtu_set_op(eth_dev, eth_dev->data->mtu);
 687         }
 688         return 0;
 689
 690 resource_error:
 691         PMD_DRV_LOG(ERR,
 692                     "Insufficient resources to support requested config\n");
 693         PMD_DRV_LOG(ERR,
 694                     "Num Queues Requested: Tx %d, Rx %d\n",
 695                     eth_dev->data->nb_tx_queues,
 696                     eth_dev->data->nb_rx_queues);
 697         PMD_DRV_LOG(ERR,
 698                     "MAX: TxQ %d, RxQ %d, CQ %d Stat %d, Grp %d, Vnic %d\n",
 699                     bp->max_tx_rings, bp->max_rx_rings, bp->max_cp_rings,
 700                     bp->max_stat_ctx, bp->max_ring_grps, bp->max_vnics);
 701         return -ENOSPC;
 702 }
 703
 704 static void bnxt_print_link_info(struct rte_eth_dev *eth_dev)
 705 {
 706         struct rte_eth_link *link = &eth_dev->data->dev_link;
 707
 708         if (link->link_status)
 709                 PMD_DRV_LOG(INFO, "Port %d Link Up - speed %u Mbps - %s\n",
 710                         eth_dev->data->port_id,
 711                         (uint32_t)link->link_speed,
 712                         (link->link_duplex == ETH_LINK_FULL_DUPLEX) ?
 713                         ("full-duplex") : ("half-duplex\n"));
 714         else
 715                 PMD_DRV_LOG(INFO, "Port %d Link Down\n",
 716                         eth_dev->data->port_id);
 717 }
 718
 719 /*
 720  * Determine whether the current configuration requires support for scattered
 721  * receive; return 1 if scattered receive is required and 0 if not.
 722  */
 723 static int bnxt_scattered_rx(struct rte_eth_dev *eth_dev)
 724 {
 725         uint16_t buf_size;
 726         int i;
 727
 728         for (i = 0; i < eth_dev->data->nb_rx_queues; i++) {
 729                 struct bnxt_rx_queue *rxq = eth_dev->data->rx_queues[i];
 730
 731                 buf_size = (uint16_t)(rte_pktmbuf_data_room_size(rxq->mb_pool) -
 732                                       RTE_PKTMBUF_HEADROOM);
 733                 if (eth_dev->data->dev_conf.rxmode.max_rx_pkt_len > buf_size)
 734                         return 1;
 735         }
 736         return 0;
 737 }
 738
 739 static eth_rx_burst_t
 740 bnxt_receive_function(__rte_unused struct rte_eth_dev *eth_dev)
 741 {
 742 #ifdef RTE_ARCH_X86
 743 #ifndef RTE_LIBRTE_IEEE1588
 744         /*
 745          * Vector mode receive can be enabled only if scatter rx is not
 746          * in use and rx offloads are limited to VLAN stripping and
 747          * CRC stripping.
 748          */
 749         if (!eth_dev->data->scattered_rx &&
 750             !(eth_dev->data->dev_conf.rxmode.offloads &
 751               ~(DEV_RX_OFFLOAD_VLAN_STRIP |
 752                 DEV_RX_OFFLOAD_KEEP_CRC |
 753                 DEV_RX_OFFLOAD_JUMBO_FRAME |
 754                 DEV_RX_OFFLOAD_IPV4_CKSUM |
 755                 DEV_RX_OFFLOAD_UDP_CKSUM |
 756                 DEV_RX_OFFLOAD_TCP_CKSUM |
 757                 DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM |
 758                 DEV_RX_OFFLOAD_VLAN_FILTER))) {
 759                 PMD_DRV_LOG(INFO, "Using vector mode receive for port %d\n",
 760                             eth_dev->data->port_id);
 761                 return bnxt_recv_pkts_vec;
 762         }
 763         PMD_DRV_LOG(INFO, "Vector mode receive disabled for port %d\n",
 764                     eth_dev->data->port_id);
 765         PMD_DRV_LOG(INFO,
 766                     "Port %d scatter: %d rx offload: %" PRIX64 "\n",
 767                     eth_dev->data->port_id,
 768                     eth_dev->data->scattered_rx,
 769                     eth_dev->data->dev_conf.rxmode.offloads);
 770 #endif
 771 #endif
 772         return bnxt_recv_pkts;
 773 }
 774
 775 static eth_tx_burst_t
 776 bnxt_transmit_function(__rte_unused struct rte_eth_dev *eth_dev)
 777 {
 778 #ifdef RTE_ARCH_X86
 779 #ifndef RTE_LIBRTE_IEEE1588
 780         /*
 781          * Vector mode transmit can be enabled only if not using scatter rx
 782          * or tx offloads.
 783          */
 784         if (!eth_dev->data->scattered_rx &&
 785             !eth_dev->data->dev_conf.txmode.offloads) {
 786                 PMD_DRV_LOG(INFO, "Using vector mode transmit for port %d\n",
 787                             eth_dev->data->port_id);
 788                 return bnxt_xmit_pkts_vec;
 789         }
 790         PMD_DRV_LOG(INFO, "Vector mode transmit disabled for port %d\n",
 791                     eth_dev->data->port_id);
 792         PMD_DRV_LOG(INFO,
 793                     "Port %d scatter: %d tx offload: %" PRIX64 "\n",
 794                     eth_dev->data->port_id,
 795                     eth_dev->data->scattered_rx,
 796                     eth_dev->data->dev_conf.txmode.offloads);
 797 #endif
 798 #endif
 799         return bnxt_xmit_pkts;
 800 }
 801
 802 static int bnxt_handle_if_change_status(struct bnxt *bp)
 803 {
 804         int rc;
 805
 806         /* Since fw has undergone a reset and lost all contexts,
 807          * set fatal flag to not issue hwrm during cleanup
 808          */
 809         bp->flags |= BNXT_FLAG_FATAL_ERROR;
 810         bnxt_uninit_resources(bp, true);
 811
 812         /* clear fatal flag so that re-init happens */
 813         bp->flags &= ~BNXT_FLAG_FATAL_ERROR;
 814         rc = bnxt_init_resources(bp, true);
 815
 816         bp->flags &= ~BNXT_FLAG_IF_CHANGE_HOT_FW_RESET_DONE;
 817
 818         return rc;
 819 }
 820
 821 static int bnxt_dev_start_op(struct rte_eth_dev *eth_dev)
 822 {
 823         struct bnxt *bp = eth_dev->data->dev_private;
 824         uint64_t rx_offloads = eth_dev->data->dev_conf.rxmode.offloads;
 825         int vlan_mask = 0;
 826         int rc;
 827
 828         if (bp->rx_cp_nr_rings > RTE_ETHDEV_QUEUE_STAT_CNTRS) {
 829                 PMD_DRV_LOG(ERR,
 830                         "RxQ cnt %d > CONFIG_RTE_ETHDEV_QUEUE_STAT_CNTRS %d\n",
 831                         bp->rx_cp_nr_rings, RTE_ETHDEV_QUEUE_STAT_CNTRS);
 832         }
 833
 834         rc = bnxt_hwrm_if_change(bp, 1);
 835         if (!rc) {
 836                 if (bp->flags & BNXT_FLAG_IF_CHANGE_HOT_FW_RESET_DONE) {
 837                         rc = bnxt_handle_if_change_status(bp);
 838                         if (rc)
 839                                 return rc;
 840                 }
 841         }
 842
 843         rc = bnxt_init_chip(bp);
 844         if (rc)
 845                 goto error;
 846
 847         eth_dev->data->scattered_rx = bnxt_scattered_rx(eth_dev);
 848
 849         bnxt_link_update_op(eth_dev, 1);
 850
 851         if (rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER)
 852                 vlan_mask |= ETH_VLAN_FILTER_MASK;
 853         if (rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
 854                 vlan_mask |= ETH_VLAN_STRIP_MASK;
 855         rc = bnxt_vlan_offload_set_op(eth_dev, vlan_mask);
 856         if (rc)
 857                 goto error;
 858
 859         eth_dev->rx_pkt_burst = bnxt_receive_function(eth_dev);
 860         eth_dev->tx_pkt_burst = bnxt_transmit_function(eth_dev);
 861
 862         bnxt_enable_int(bp);
 863         bp->flags |= BNXT_FLAG_INIT_DONE;
 864         eth_dev->data->dev_started = 1;
 865         bp->dev_stopped = 0;
 866         bnxt_schedule_fw_health_check(bp);
 867         return 0;
 868
 869 error:
 870         bnxt_hwrm_if_change(bp, 0);
 871         bnxt_shutdown_nic(bp);
 872         bnxt_free_tx_mbufs(bp);
 873         bnxt_free_rx_mbufs(bp);
 874         return rc;
 875 }
 876
 877 static int bnxt_dev_set_link_up_op(struct rte_eth_dev *eth_dev)
 878 {
 879         struct bnxt *bp = eth_dev->data->dev_private;
 880         int rc = 0;
 881
 882         if (!bp->link_info.link_up)
 883                 rc = bnxt_set_hwrm_link_config(bp, true);
 884         if (!rc)
 885                 eth_dev->data->dev_link.link_status = 1;
 886
 887         bnxt_print_link_info(eth_dev);
 888         return 0;
 889 }
 890
 891 static int bnxt_dev_set_link_down_op(struct rte_eth_dev *eth_dev)
 892 {
 893         struct bnxt *bp = eth_dev->data->dev_private;
 894
 895         eth_dev->data->dev_link.link_status = 0;
 896         bnxt_set_hwrm_link_config(bp, false);
 897         bp->link_info.link_up = 0;
 898
 899         return 0;
 900 }
 901
 902 /* Unload the driver, release resources */
 903 static void bnxt_dev_stop_op(struct rte_eth_dev *eth_dev)
 904 {
 905         struct bnxt *bp = eth_dev->data->dev_private;
 906         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
 907         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
 908
 909         eth_dev->data->dev_started = 0;
 910         /* Prevent crashes when queues are still in use */
 911         eth_dev->rx_pkt_burst = &bnxt_dummy_recv_pkts;
 912         eth_dev->tx_pkt_burst = &bnxt_dummy_xmit_pkts;
 913
 914         bnxt_disable_int(bp);
 915
 916         /* disable uio/vfio intr/eventfd mapping */
 917         rte_intr_disable(intr_handle);
 918
 919         bnxt_cancel_fw_health_check(bp);
 920
 921         bp->flags &= ~BNXT_FLAG_INIT_DONE;
 922         if (bp->eth_dev->data->dev_started) {
 923                 /* TBD: STOP HW queues DMA */
 924                 eth_dev->data->dev_link.link_status = 0;
 925         }
 926         bnxt_set_hwrm_link_config(bp, false);
 927
 928         /* Clean queue intr-vector mapping */
 929         rte_intr_efd_disable(intr_handle);
 930         if (intr_handle->intr_vec != NULL) {
 931                 rte_free(intr_handle->intr_vec);
 932                 intr_handle->intr_vec = NULL;
 933         }
 934
 935         bnxt_hwrm_port_clr_stats(bp);
 936         bnxt_free_tx_mbufs(bp);
 937         bnxt_free_rx_mbufs(bp);
 938         bnxt_shutdown_nic(bp);
 939         bnxt_hwrm_if_change(bp, 0);
 940         bp->dev_stopped = 1;
 941 }
 942
 943 static void bnxt_dev_close_op(struct rte_eth_dev *eth_dev)
 944 {
 945         struct bnxt *bp = eth_dev->data->dev_private;
 946
 947         if (bp->dev_stopped == 0)
 948                 bnxt_dev_stop_op(eth_dev);
 949
 950         if (eth_dev->data->mac_addrs != NULL) {
 951                 rte_free(eth_dev->data->mac_addrs);
 952                 eth_dev->data->mac_addrs = NULL;
 953         }
 954         if (bp->grp_info != NULL) {
 955                 rte_free(bp->grp_info);
 956                 bp->grp_info = NULL;
 957         }
 958
 959         bnxt_dev_uninit(eth_dev);
 960 }
 961
 962 static void bnxt_mac_addr_remove_op(struct rte_eth_dev *eth_dev,
 963                                     uint32_t index)
 964 {
 965         struct bnxt *bp = eth_dev->data->dev_private;
 966         uint64_t pool_mask = eth_dev->data->mac_pool_sel[index];
 967         struct bnxt_vnic_info *vnic;
 968         struct bnxt_filter_info *filter, *temp_filter;
 969         uint32_t i;
 970
 971         if (is_bnxt_in_error(bp))
 972                 return;
 973
 974         /*
 975          * Loop through all VNICs from the specified filter flow pools to
 976          * remove the corresponding MAC addr filter
 977          */
 978         for (i = 0; i < bp->nr_vnics; i++) {
 979                 if (!(pool_mask & (1ULL << i)))
 980                         continue;
 981
 982                 vnic = &bp->vnic_info[i];
 983                 filter = STAILQ_FIRST(&vnic->filter);
 984                 while (filter) {
 985                         temp_filter = STAILQ_NEXT(filter, next);
 986                         if (filter->mac_index == index) {
 987                                 STAILQ_REMOVE(&vnic->filter, filter,
 988                                                 bnxt_filter_info, next);
 989                                 bnxt_hwrm_clear_l2_filter(bp, filter);
 990                                 filter->mac_index = INVALID_MAC_INDEX;
 991                                 memset(&filter->l2_addr, 0, RTE_ETHER_ADDR_LEN);
 992                                 STAILQ_INSERT_TAIL(&bp->free_filter_list,
 993                                                    filter, next);
 994                         }
 995                         filter = temp_filter;
 996                 }
 997         }
 998 }
 999
1000 static int bnxt_mac_addr_add_op(struct rte_eth_dev *eth_dev,
1001                                 struct rte_ether_addr *mac_addr,
1002                                 uint32_t index, uint32_t pool)
1003 {
1004         struct bnxt *bp = eth_dev->data->dev_private;
1005         struct bnxt_vnic_info *vnic = &bp->vnic_info[pool];
1006         struct bnxt_filter_info *filter;
1007         int rc = 0;
1008
1009         rc = is_bnxt_in_error(bp);
1010         if (rc)
1011                 return rc;
1012
1013         if (BNXT_VF(bp) & !BNXT_VF_IS_TRUSTED(bp)) {
1014                 PMD_DRV_LOG(ERR, "Cannot add MAC address to a VF interface\n");
1015                 return -ENOTSUP;
1016         }
1017
1018         if (!vnic) {
1019                 PMD_DRV_LOG(ERR, "VNIC not found for pool %d!\n", pool);
1020                 return -EINVAL;
1021         }
1022         /* Attach requested MAC address to the new l2_filter */
1023         STAILQ_FOREACH(filter, &vnic->filter, next) {
1024                 if (filter->mac_index == index) {
1025                         PMD_DRV_LOG(ERR,
1026                                 "MAC addr already existed for pool %d\n", pool);
1027                         return 0;
1028                 }
1029         }
1030         filter = bnxt_alloc_filter(bp);
1031         if (!filter) {
1032                 PMD_DRV_LOG(ERR, "L2 filter alloc failed\n");
1033                 return -ENODEV;
1034         }
1035
1036         filter->mac_index = index;
1037         memcpy(filter->l2_addr, mac_addr, RTE_ETHER_ADDR_LEN);
1038
1039         rc = bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id, filter);
1040         if (!rc) {
1041                 STAILQ_INSERT_TAIL(&vnic->filter, filter, next);
1042         } else {
1043                 filter->mac_index = INVALID_MAC_INDEX;
1044                 memset(&filter->l2_addr, 0, RTE_ETHER_ADDR_LEN);
1045                 bnxt_free_filter(bp, filter);
1046         }
1047
1048         return rc;
1049 }
1050
1051 int bnxt_link_update_op(struct rte_eth_dev *eth_dev, int wait_to_complete)
1052 {
1053         int rc = 0;
1054         struct bnxt *bp = eth_dev->data->dev_private;
1055         struct rte_eth_link new;
1056         unsigned int cnt = BNXT_LINK_WAIT_CNT;
1057
1058         rc = is_bnxt_in_error(bp);
1059         if (rc)
1060                 return rc;
1061
1062         memset(&new, 0, sizeof(new));
1063         do {
1064                 /* Retrieve link info from hardware */
1065                 rc = bnxt_get_hwrm_link_config(bp, &new);
1066                 if (rc) {
1067                         new.link_speed = ETH_LINK_SPEED_100M;
1068                         new.link_duplex = ETH_LINK_FULL_DUPLEX;
1069                         PMD_DRV_LOG(ERR,
1070                                 "Failed to retrieve link rc = 0x%x!\n", rc);
1071                         goto out;
1072                 }
1073
1074                 if (!wait_to_complete || new.link_status)
1075                         break;
1076
1077                 rte_delay_ms(BNXT_LINK_WAIT_INTERVAL);
1078         } while (cnt--);
1079
1080 out:
1081         /* Timed out or success */
1082         if (new.link_status != eth_dev->data->dev_link.link_status ||
1083         new.link_speed != eth_dev->data->dev_link.link_speed) {
1084                 memcpy(&eth_dev->data->dev_link, &new,
1085                         sizeof(struct rte_eth_link));
1086
1087                 _rte_eth_dev_callback_process(eth_dev,
1088                                               RTE_ETH_EVENT_INTR_LSC,
1089                                               NULL);
1090
1091                 bnxt_print_link_info(eth_dev);
1092         }
1093
1094         return rc;
1095 }
1096
1097 static int bnxt_promiscuous_enable_op(struct rte_eth_dev *eth_dev)
1098 {
1099         struct bnxt *bp = eth_dev->data->dev_private;
1100         struct bnxt_vnic_info *vnic;
1101         uint32_t old_flags;
1102         int rc;
1103
1104         rc = is_bnxt_in_error(bp);
1105         if (rc)
1106                 return rc;
1107
1108         if (bp->vnic_info == NULL)
1109                 return 0;
1110
1111         vnic = &bp->vnic_info[0];
1112
1113         old_flags = vnic->flags;
1114         vnic->flags |= BNXT_VNIC_INFO_PROMISC;
1115         rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1116         if (rc != 0)
1117                 vnic->flags = old_flags;
1118
1119         return rc;
1120 }
1121
1122 static int bnxt_promiscuous_disable_op(struct rte_eth_dev *eth_dev)
1123 {
1124         struct bnxt *bp = eth_dev->data->dev_private;
1125         struct bnxt_vnic_info *vnic;
1126         uint32_t old_flags;
1127         int rc;
1128
1129         rc = is_bnxt_in_error(bp);
1130         if (rc)
1131                 return rc;
1132
1133         if (bp->vnic_info == NULL)
1134                 return 0;
1135
1136         vnic = &bp->vnic_info[0];
1137
1138         old_flags = vnic->flags;
1139         vnic->flags &= ~BNXT_VNIC_INFO_PROMISC;
1140         rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1141         if (rc != 0)
1142                 vnic->flags = old_flags;
1143
1144         return rc;
1145 }
1146
1147 static int bnxt_allmulticast_enable_op(struct rte_eth_dev *eth_dev)
1148 {
1149         struct bnxt *bp = eth_dev->data->dev_private;
1150         struct bnxt_vnic_info *vnic;
1151         uint32_t old_flags;
1152         int rc;
1153
1154         rc = is_bnxt_in_error(bp);
1155         if (rc)
1156                 return rc;
1157
1158         if (bp->vnic_info == NULL)
1159                 return 0;
1160
1161         vnic = &bp->vnic_info[0];
1162
1163         old_flags = vnic->flags;
1164         vnic->flags |= BNXT_VNIC_INFO_ALLMULTI;
1165         rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1166         if (rc != 0)
1167                 vnic->flags = old_flags;
1168
1169         return rc;
1170 }
1171
1172 static int bnxt_allmulticast_disable_op(struct rte_eth_dev *eth_dev)
1173 {
1174         struct bnxt *bp = eth_dev->data->dev_private;
1175         struct bnxt_vnic_info *vnic;
1176         uint32_t old_flags;
1177         int rc;
1178
1179         rc = is_bnxt_in_error(bp);
1180         if (rc)
1181                 return rc;
1182
1183         if (bp->vnic_info == NULL)
1184                 return 0;
1185
1186         vnic = &bp->vnic_info[0];
1187
1188         old_flags = vnic->flags;
1189         vnic->flags &= ~BNXT_VNIC_INFO_ALLMULTI;
1190         rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1191         if (rc != 0)
1192                 vnic->flags = old_flags;
1193
1194         return rc;
1195 }
1196
1197 /* Return bnxt_rx_queue pointer corresponding to a given rxq. */
1198 static struct bnxt_rx_queue *bnxt_qid_to_rxq(struct bnxt *bp, uint16_t qid)
1199 {
1200         if (qid >= bp->rx_nr_rings)
1201                 return NULL;
1202
1203         return bp->eth_dev->data->rx_queues[qid];
1204 }
1205
1206 /* Return rxq corresponding to a given rss table ring/group ID. */
1207 static uint16_t bnxt_rss_to_qid(struct bnxt *bp, uint16_t fwr)
1208 {
1209         struct bnxt_rx_queue *rxq;
1210         unsigned int i;
1211
1212         if (!BNXT_HAS_RING_GRPS(bp)) {
1213                 for (i = 0; i < bp->rx_nr_rings; i++) {
1214                         rxq = bp->eth_dev->data->rx_queues[i];
1215                         if (rxq->rx_ring->rx_ring_struct->fw_ring_id == fwr)
1216                                 return rxq->index;
1217                 }
1218         } else {
1219                 for (i = 0; i < bp->rx_nr_rings; i++) {
1220                         if (bp->grp_info[i].fw_grp_id == fwr)
1221                                 return i;
1222                 }
1223         }
1224
1225         return INVALID_HW_RING_ID;
1226 }
1227
1228 static int bnxt_reta_update_op(struct rte_eth_dev *eth_dev,
1229                             struct rte_eth_rss_reta_entry64 *reta_conf,
1230                             uint16_t reta_size)
1231 {
1232         struct bnxt *bp = eth_dev->data->dev_private;
1233         struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
1234         struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
1235         uint16_t tbl_size = bnxt_rss_hash_tbl_size(bp);
1236         uint16_t idx, sft;
1237         int i, rc;
1238
1239         rc = is_bnxt_in_error(bp);
1240         if (rc)
1241                 return rc;
1242
1243         if (!vnic->rss_table)
1244                 return -EINVAL;
1245
1246         if (!(dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG))
1247                 return -EINVAL;
1248
1249         if (reta_size != tbl_size) {
1250                 PMD_DRV_LOG(ERR, "The configured hash table lookup size "
1251                         "(%d) must equal the size supported by the hardware "
1252                         "(%d)\n", reta_size, tbl_size);
1253                 return -EINVAL;
1254         }
1255
1256         for (i = 0; i < reta_size; i++) {
1257                 struct bnxt_rx_queue *rxq;
1258
1259                 idx = i / RTE_RETA_GROUP_SIZE;
1260                 sft = i % RTE_RETA_GROUP_SIZE;
1261
1262                 if (!(reta_conf[idx].mask & (1ULL << sft)))
1263                         continue;
1264
1265                 rxq = bnxt_qid_to_rxq(bp, reta_conf[idx].reta[sft]);
1266                 if (!rxq) {
1267                         PMD_DRV_LOG(ERR, "Invalid ring in reta_conf.\n");
1268                         return -EINVAL;
1269                 }
1270
1271                 if (BNXT_CHIP_THOR(bp)) {
1272                         vnic->rss_table[i * 2] =
1273                                 rxq->rx_ring->rx_ring_struct->fw_ring_id;
1274                         vnic->rss_table[i * 2 + 1] =
1275                                 rxq->cp_ring->cp_ring_struct->fw_ring_id;
1276                 } else {
1277                         vnic->rss_table[i] =
1278                             vnic->fw_grp_ids[reta_conf[idx].reta[sft]];
1279                 }
1280
1281                 vnic->rss_table[i] =
1282                     vnic->fw_grp_ids[reta_conf[idx].reta[sft]];
1283         }
1284
1285         bnxt_hwrm_vnic_rss_cfg(bp, vnic);
1286         return 0;
1287 }
1288
1289 static int bnxt_reta_query_op(struct rte_eth_dev *eth_dev,
1290                               struct rte_eth_rss_reta_entry64 *reta_conf,
1291                               uint16_t reta_size)
1292 {
1293         struct bnxt *bp = eth_dev->data->dev_private;
1294         struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
1295         uint16_t tbl_size = bnxt_rss_hash_tbl_size(bp);
1296         uint16_t idx, sft, i;
1297         int rc;
1298
1299         rc = is_bnxt_in_error(bp);
1300         if (rc)
1301                 return rc;
1302
1303         /* Retrieve from the default VNIC */
1304         if (!vnic)
1305                 return -EINVAL;
1306         if (!vnic->rss_table)
1307                 return -EINVAL;
1308
1309         if (reta_size != tbl_size) {
1310                 PMD_DRV_LOG(ERR, "The configured hash table lookup size "
1311                         "(%d) must equal the size supported by the hardware "
1312                         "(%d)\n", reta_size, tbl_size);
1313                 return -EINVAL;
1314         }
1315
1316         for (idx = 0, i = 0; i < reta_size; i++) {
1317                 idx = i / RTE_RETA_GROUP_SIZE;
1318                 sft = i % RTE_RETA_GROUP_SIZE;
1319
1320                 if (reta_conf[idx].mask & (1ULL << sft)) {
1321                         uint16_t qid;
1322
1323                         if (BNXT_CHIP_THOR(bp))
1324                                 qid = bnxt_rss_to_qid(bp,
1325                                                       vnic->rss_table[i * 2]);
1326                         else
1327                                 qid = bnxt_rss_to_qid(bp, vnic->rss_table[i]);
1328
1329                         if (qid == INVALID_HW_RING_ID) {
1330                                 PMD_DRV_LOG(ERR, "Inv. entry in rss table.\n");
1331                                 return -EINVAL;
1332                         }
1333                         reta_conf[idx].reta[sft] = qid;
1334                 }
1335         }
1336
1337         return 0;
1338 }
1339
1340 static int bnxt_rss_hash_update_op(struct rte_eth_dev *eth_dev,
1341                                    struct rte_eth_rss_conf *rss_conf)
1342 {
1343         struct bnxt *bp = eth_dev->data->dev_private;
1344         struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
1345         struct bnxt_vnic_info *vnic;
1346         uint16_t hash_type = 0;
1347         unsigned int i;
1348         int rc;
1349
1350         rc = is_bnxt_in_error(bp);
1351         if (rc)
1352                 return rc;
1353
1354         /*
1355          * If RSS enablement were different than dev_configure,
1356          * then return -EINVAL
1357          */
1358         if (dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG) {
1359                 if (!rss_conf->rss_hf)
1360                         PMD_DRV_LOG(ERR, "Hash type NONE\n");
1361         } else {
1362                 if (rss_conf->rss_hf & BNXT_ETH_RSS_SUPPORT)
1363                         return -EINVAL;
1364         }
1365
1366         bp->flags |= BNXT_FLAG_UPDATE_HASH;
1367         memcpy(&bp->rss_conf, rss_conf, sizeof(*rss_conf));
1368
1369         if (rss_conf->rss_hf & ETH_RSS_IPV4)
1370                 hash_type |= HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV4;
1371         if (rss_conf->rss_hf & ETH_RSS_NONFRAG_IPV4_TCP)
1372                 hash_type |= HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV4;
1373         if (rss_conf->rss_hf & ETH_RSS_NONFRAG_IPV4_UDP)
1374                 hash_type |= HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV4;
1375         if (rss_conf->rss_hf & ETH_RSS_IPV6)
1376                 hash_type |= HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6;
1377         if (rss_conf->rss_hf & ETH_RSS_NONFRAG_IPV6_TCP)
1378                 hash_type |= HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV6;
1379         if (rss_conf->rss_hf & ETH_RSS_NONFRAG_IPV6_UDP)
1380                 hash_type |= HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV6;
1381
1382         /* Update the RSS VNIC(s) */
1383         for (i = 0; i < bp->nr_vnics; i++) {
1384                 vnic = &bp->vnic_info[i];
1385                 vnic->hash_type = hash_type;
1386
1387                 /*
1388                  * Use the supplied key if the key length is
1389                  * acceptable and the rss_key is not NULL
1390                  */
1391                 if (rss_conf->rss_key &&
1392                     rss_conf->rss_key_len <= HW_HASH_KEY_SIZE)
1393                         memcpy(vnic->rss_hash_key, rss_conf->rss_key,
1394                                rss_conf->rss_key_len);
1395
1396                 bnxt_hwrm_vnic_rss_cfg(bp, vnic);
1397         }
1398         return 0;
1399 }
1400
1401 static int bnxt_rss_hash_conf_get_op(struct rte_eth_dev *eth_dev,
1402                                      struct rte_eth_rss_conf *rss_conf)
1403 {
1404         struct bnxt *bp = eth_dev->data->dev_private;
1405         struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
1406         int len, rc;
1407         uint32_t hash_types;
1408
1409         rc = is_bnxt_in_error(bp);
1410         if (rc)
1411                 return rc;
1412
1413         /* RSS configuration is the same for all VNICs */
1414         if (vnic && vnic->rss_hash_key) {
1415                 if (rss_conf->rss_key) {
1416                         len = rss_conf->rss_key_len <= HW_HASH_KEY_SIZE ?
1417                               rss_conf->rss_key_len : HW_HASH_KEY_SIZE;
1418                         memcpy(rss_conf->rss_key, vnic->rss_hash_key, len);
1419                 }
1420
1421                 hash_types = vnic->hash_type;
1422                 rss_conf->rss_hf = 0;
1423                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV4) {
1424                         rss_conf->rss_hf |= ETH_RSS_IPV4;
1425                         hash_types &= ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV4;
1426                 }
1427                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV4) {
1428                         rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP;
1429                         hash_types &=
1430                                 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV4;
1431                 }
1432                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV4) {
1433                         rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
1434                         hash_types &=
1435                                 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV4;
1436                 }
1437                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6) {
1438                         rss_conf->rss_hf |= ETH_RSS_IPV6;
1439                         hash_types &= ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6;
1440                 }
1441                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV6) {
1442                         rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV6_TCP;
1443                         hash_types &=
1444                                 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV6;
1445                 }
1446                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV6) {
1447                         rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;
1448                         hash_types &=
1449                                 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV6;
1450                 }
1451                 if (hash_types) {
1452                         PMD_DRV_LOG(ERR,
1453                                 "Unknwon RSS config from firmware (%08x), RSS disabled",
1454                                 vnic->hash_type);
1455                         return -ENOTSUP;
1456                 }
1457         } else {
1458                 rss_conf->rss_hf = 0;
1459         }
1460         return 0;
1461 }
1462
1463 static int bnxt_flow_ctrl_get_op(struct rte_eth_dev *dev,
1464                                struct rte_eth_fc_conf *fc_conf)
1465 {
1466         struct bnxt *bp = dev->data->dev_private;
1467         struct rte_eth_link link_info;
1468         int rc;
1469
1470         rc = is_bnxt_in_error(bp);
1471         if (rc)
1472                 return rc;
1473
1474         rc = bnxt_get_hwrm_link_config(bp, &link_info);
1475         if (rc)
1476                 return rc;
1477
1478         memset(fc_conf, 0, sizeof(*fc_conf));
1479         if (bp->link_info.auto_pause)
1480                 fc_conf->autoneg = 1;
1481         switch (bp->link_info.pause) {
1482         case 0:
1483                 fc_conf->mode = RTE_FC_NONE;
1484                 break;
1485         case HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_TX:
1486                 fc_conf->mode = RTE_FC_TX_PAUSE;
1487                 break;
1488         case HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_RX:
1489                 fc_conf->mode = RTE_FC_RX_PAUSE;
1490                 break;
1491         case (HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_TX |
1492                         HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_RX):
1493                 fc_conf->mode = RTE_FC_FULL;
1494                 break;
1495         }
1496         return 0;
1497 }
1498
1499 static int bnxt_flow_ctrl_set_op(struct rte_eth_dev *dev,
1500                                struct rte_eth_fc_conf *fc_conf)
1501 {
1502         struct bnxt *bp = dev->data->dev_private;
1503         int rc;
1504
1505         rc = is_bnxt_in_error(bp);
1506         if (rc)
1507                 return rc;
1508
1509         if (!BNXT_SINGLE_PF(bp) || BNXT_VF(bp)) {
1510                 PMD_DRV_LOG(ERR, "Flow Control Settings cannot be modified\n");
1511                 return -ENOTSUP;
1512         }
1513
1514         switch (fc_conf->mode) {
1515         case RTE_FC_NONE:
1516                 bp->link_info.auto_pause = 0;
1517                 bp->link_info.force_pause = 0;
1518                 break;
1519         case RTE_FC_RX_PAUSE:
1520                 if (fc_conf->autoneg) {
1521                         bp->link_info.auto_pause =
1522                                         HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_RX;
1523                         bp->link_info.force_pause = 0;
1524                 } else {
1525                         bp->link_info.auto_pause = 0;
1526                         bp->link_info.force_pause =
1527                                         HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_RX;
1528                 }
1529                 break;
1530         case RTE_FC_TX_PAUSE:
1531                 if (fc_conf->autoneg) {
1532                         bp->link_info.auto_pause =
1533                                         HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_TX;
1534                         bp->link_info.force_pause = 0;
1535                 } else {
1536                         bp->link_info.auto_pause = 0;
1537                         bp->link_info.force_pause =
1538                                         HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_TX;
1539                 }
1540                 break;
1541         case RTE_FC_FULL:
1542                 if (fc_conf->autoneg) {
1543                         bp->link_info.auto_pause =
1544                                         HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_TX |
1545                                         HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_RX;
1546                         bp->link_info.force_pause = 0;
1547                 } else {
1548                         bp->link_info.auto_pause = 0;
1549                         bp->link_info.force_pause =
1550                                         HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_TX |
1551                                         HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_RX;
1552                 }
1553                 break;
1554         }
1555         return bnxt_set_hwrm_link_config(bp, true);
1556 }
1557
1558 /* Add UDP tunneling port */
1559 static int
1560 bnxt_udp_tunnel_port_add_op(struct rte_eth_dev *eth_dev,
1561                          struct rte_eth_udp_tunnel *udp_tunnel)
1562 {
1563         struct bnxt *bp = eth_dev->data->dev_private;
1564         uint16_t tunnel_type = 0;
1565         int rc = 0;
1566
1567         rc = is_bnxt_in_error(bp);
1568         if (rc)
1569                 return rc;
1570
1571         switch (udp_tunnel->prot_type) {
1572         case RTE_TUNNEL_TYPE_VXLAN:
1573                 if (bp->vxlan_port_cnt) {
1574                         PMD_DRV_LOG(ERR, "Tunnel Port %d already programmed\n",
1575                                 udp_tunnel->udp_port);
1576                         if (bp->vxlan_port != udp_tunnel->udp_port) {
1577                                 PMD_DRV_LOG(ERR, "Only one port allowed\n");
1578                                 return -ENOSPC;
1579                         }
1580                         bp->vxlan_port_cnt++;
1581                         return 0;
1582                 }
1583                 tunnel_type =
1584                         HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_VXLAN;
1585                 bp->vxlan_port_cnt++;
1586                 break;
1587         case RTE_TUNNEL_TYPE_GENEVE:
1588                 if (bp->geneve_port_cnt) {
1589                         PMD_DRV_LOG(ERR, "Tunnel Port %d already programmed\n",
1590                                 udp_tunnel->udp_port);
1591                         if (bp->geneve_port != udp_tunnel->udp_port) {
1592                                 PMD_DRV_LOG(ERR, "Only one port allowed\n");
1593                                 return -ENOSPC;
1594                         }
1595                         bp->geneve_port_cnt++;
1596                         return 0;
1597                 }
1598                 tunnel_type =
1599                         HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_GENEVE;
1600                 bp->geneve_port_cnt++;
1601                 break;
1602         default:
1603                 PMD_DRV_LOG(ERR, "Tunnel type is not supported\n");
1604                 return -ENOTSUP;
1605         }
1606         rc = bnxt_hwrm_tunnel_dst_port_alloc(bp, udp_tunnel->udp_port,
1607                                              tunnel_type);
1608         return rc;
1609 }
1610
1611 static int
1612 bnxt_udp_tunnel_port_del_op(struct rte_eth_dev *eth_dev,
1613                          struct rte_eth_udp_tunnel *udp_tunnel)
1614 {
1615         struct bnxt *bp = eth_dev->data->dev_private;
1616         uint16_t tunnel_type = 0;
1617         uint16_t port = 0;
1618         int rc = 0;
1619
1620         rc = is_bnxt_in_error(bp);
1621         if (rc)
1622                 return rc;
1623
1624         switch (udp_tunnel->prot_type) {
1625         case RTE_TUNNEL_TYPE_VXLAN:
1626                 if (!bp->vxlan_port_cnt) {
1627                         PMD_DRV_LOG(ERR, "No Tunnel port configured yet\n");
1628                         return -EINVAL;
1629                 }
1630                 if (bp->vxlan_port != udp_tunnel->udp_port) {
1631                         PMD_DRV_LOG(ERR, "Req Port: %d. Configured port: %d\n",
1632                                 udp_tunnel->udp_port, bp->vxlan_port);
1633                         return -EINVAL;
1634                 }
1635                 if (--bp->vxlan_port_cnt)
1636                         return 0;
1637
1638                 tunnel_type =
1639                         HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN;
1640                 port = bp->vxlan_fw_dst_port_id;
1641                 break;
1642         case RTE_TUNNEL_TYPE_GENEVE:
1643                 if (!bp->geneve_port_cnt) {
1644                         PMD_DRV_LOG(ERR, "No Tunnel port configured yet\n");
1645                         return -EINVAL;
1646                 }
1647                 if (bp->geneve_port != udp_tunnel->udp_port) {
1648                         PMD_DRV_LOG(ERR, "Req Port: %d. Configured port: %d\n",
1649                                 udp_tunnel->udp_port, bp->geneve_port);
1650                         return -EINVAL;
1651                 }
1652                 if (--bp->geneve_port_cnt)
1653                         return 0;
1654
1655                 tunnel_type =
1656                         HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_GENEVE;
1657                 port = bp->geneve_fw_dst_port_id;
1658                 break;
1659         default:
1660                 PMD_DRV_LOG(ERR, "Tunnel type is not supported\n");
1661                 return -ENOTSUP;
1662         }
1663
1664         rc = bnxt_hwrm_tunnel_dst_port_free(bp, port, tunnel_type);
1665         if (!rc) {
1666                 if (tunnel_type ==
1667                     HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN)
1668                         bp->vxlan_port = 0;
1669                 if (tunnel_type ==
1670                     HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_GENEVE)
1671                         bp->geneve_port = 0;
1672         }
1673         return rc;
1674 }
1675
1676 static int bnxt_del_vlan_filter(struct bnxt *bp, uint16_t vlan_id)
1677 {
1678         struct bnxt_filter_info *filter;
1679         struct bnxt_vnic_info *vnic;
1680         int rc = 0;
1681         uint32_t chk = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN;
1682
1683         /* if VLAN exists && VLAN matches vlan_id
1684          *      remove the MAC+VLAN filter
1685          *      add a new MAC only filter
1686          * else
1687          *      VLAN filter doesn't exist, just skip and continue
1688          */
1689         vnic = BNXT_GET_DEFAULT_VNIC(bp);
1690         filter = STAILQ_FIRST(&vnic->filter);
1691         while (filter) {
1692                 /* Search for this matching MAC+VLAN filter */
1693                 if (filter->enables & chk && filter->l2_ivlan == vlan_id &&
1694                     !memcmp(filter->l2_addr,
1695                             bp->mac_addr,
1696                             RTE_ETHER_ADDR_LEN)) {
1697                         /* Delete the filter */
1698                         rc = bnxt_hwrm_clear_l2_filter(bp, filter);
1699                         if (rc)
1700                                 return rc;
1701                         STAILQ_REMOVE(&vnic->filter, filter,
1702                                       bnxt_filter_info, next);
1703                         STAILQ_INSERT_TAIL(&bp->free_filter_list, filter, next);
1704
1705                         PMD_DRV_LOG(INFO,
1706                                     "Del Vlan filter for %d\n",
1707                                     vlan_id);
1708                         return rc;
1709                 }
1710                 filter = STAILQ_NEXT(filter, next);
1711         }
1712         return -ENOENT;
1713 }
1714
1715 static int bnxt_add_vlan_filter(struct bnxt *bp, uint16_t vlan_id)
1716 {
1717         struct bnxt_filter_info *filter;
1718         struct bnxt_vnic_info *vnic;
1719         int rc = 0;
1720         uint32_t en = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN |
1721                 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN_MASK;
1722         uint32_t chk = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN;
1723
1724         /* Implementation notes on the use of VNIC in this command:
1725          *
1726          * By default, these filters belong to default vnic for the function.
1727          * Once these filters are set up, only destination VNIC can be modified.
1728          * If the destination VNIC is not specified in this command,
1729          * then the HWRM shall only create an l2 context id.
1730          */
1731
1732         vnic = BNXT_GET_DEFAULT_VNIC(bp);
1733         filter = STAILQ_FIRST(&vnic->filter);
1734         /* Check if the VLAN has already been added */
1735         while (filter) {
1736                 if (filter->enables & chk && filter->l2_ivlan == vlan_id &&
1737                     !memcmp(filter->l2_addr, bp->mac_addr, RTE_ETHER_ADDR_LEN))
1738                         return -EEXIST;
1739
1740                 filter = STAILQ_NEXT(filter, next);
1741         }
1742
1743         /* No match found. Alloc a fresh filter and issue the L2_FILTER_ALLOC
1744          * command to create MAC+VLAN filter with the right flags, enables set.
1745          */
1746         filter = bnxt_alloc_filter(bp);
1747         if (!filter) {
1748                 PMD_DRV_LOG(ERR,
1749                             "MAC/VLAN filter alloc failed\n");
1750                 return -ENOMEM;
1751         }
1752         /* MAC + VLAN ID filter */
1753         filter->l2_ivlan = vlan_id;
1754         filter->l2_ivlan_mask = 0x0FFF;
1755         filter->enables |= en;
1756         rc = bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id, filter);
1757         if (rc) {
1758                 /* Free the newly allocated filter as we were
1759                  * not able to create the filter in hardware.
1760                  */
1761                 filter->fw_l2_filter_id = UINT64_MAX;
1762                 STAILQ_INSERT_TAIL(&bp->free_filter_list, filter, next);
1763                 return rc;
1764         }
1765
1766         /* Add this new filter to the list */
1767         STAILQ_INSERT_TAIL(&vnic->filter, filter, next);
1768         PMD_DRV_LOG(INFO,
1769                     "Added Vlan filter for %d\n", vlan_id);
1770         return rc;
1771 }
1772
1773 static int bnxt_vlan_filter_set_op(struct rte_eth_dev *eth_dev,
1774                 uint16_t vlan_id, int on)
1775 {
1776         struct bnxt *bp = eth_dev->data->dev_private;
1777         int rc;
1778
1779         rc = is_bnxt_in_error(bp);
1780         if (rc)
1781                 return rc;
1782
1783         /* These operations apply to ALL existing MAC/VLAN filters */
1784         if (on)
1785                 return bnxt_add_vlan_filter(bp, vlan_id);
1786         else
1787                 return bnxt_del_vlan_filter(bp, vlan_id);
1788 }
1789
1790 static int
1791 bnxt_vlan_offload_set_op(struct rte_eth_dev *dev, int mask)
1792 {
1793         struct bnxt *bp = dev->data->dev_private;
1794         uint64_t rx_offloads = dev->data->dev_conf.rxmode.offloads;
1795         unsigned int i;
1796         int rc;
1797
1798         rc = is_bnxt_in_error(bp);
1799         if (rc)
1800                 return rc;
1801
1802         if (mask & ETH_VLAN_FILTER_MASK) {
1803                 if (!(rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER)) {
1804                         /* Remove any VLAN filters programmed */
1805                         for (i = 0; i < 4095; i++)
1806                                 bnxt_del_vlan_filter(bp, i);
1807                 }
1808                 PMD_DRV_LOG(DEBUG, "VLAN Filtering: %d\n",
1809                         !!(rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER));
1810         }
1811
1812         if (mask & ETH_VLAN_STRIP_MASK) {
1813                 /* Enable or disable VLAN stripping */
1814                 for (i = 0; i < bp->nr_vnics; i++) {
1815                         struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
1816                         if (rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
1817                                 vnic->vlan_strip = true;
1818                         else
1819                                 vnic->vlan_strip = false;
1820                         bnxt_hwrm_vnic_cfg(bp, vnic);
1821                 }
1822                 PMD_DRV_LOG(DEBUG, "VLAN Strip Offload: %d\n",
1823                         !!(rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP));
1824         }
1825
1826         if (mask & ETH_VLAN_EXTEND_MASK)
1827                 PMD_DRV_LOG(ERR, "Extend VLAN Not supported\n");
1828
1829         return 0;
1830 }
1831
1832 static int
1833 bnxt_set_default_mac_addr_op(struct rte_eth_dev *dev,
1834                         struct rte_ether_addr *addr)
1835 {
1836         struct bnxt *bp = dev->data->dev_private;
1837         /* Default Filter is tied to VNIC 0 */
1838         struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
1839         struct bnxt_filter_info *filter;
1840         int rc;
1841
1842         rc = is_bnxt_in_error(bp);
1843         if (rc)
1844                 return rc;
1845
1846         if (BNXT_VF(bp) && !BNXT_VF_IS_TRUSTED(bp))
1847                 return -EPERM;
1848
1849         if (rte_is_zero_ether_addr(addr))
1850                 return -EINVAL;
1851
1852         STAILQ_FOREACH(filter, &vnic->filter, next) {
1853                 /* Default Filter is at Index 0 */
1854                 if (filter->mac_index != 0)
1855                         continue;
1856
1857                 memcpy(filter->l2_addr, bp->mac_addr, RTE_ETHER_ADDR_LEN);
1858                 memset(filter->l2_addr_mask, 0xff, RTE_ETHER_ADDR_LEN);
1859                 filter->flags |= HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_PATH_RX;
1860                 filter->enables |=
1861                         HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR |
1862                         HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR_MASK;
1863
1864                 rc = bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id, filter);
1865                 if (rc)
1866                         return rc;
1867
1868                 memcpy(bp->mac_addr, addr, RTE_ETHER_ADDR_LEN);
1869                 PMD_DRV_LOG(DEBUG, "Set MAC addr\n");
1870                 return 0;
1871         }
1872
1873         return 0;
1874 }
1875
1876 static int
1877 bnxt_dev_set_mc_addr_list_op(struct rte_eth_dev *eth_dev,
1878                           struct rte_ether_addr *mc_addr_set,
1879                           uint32_t nb_mc_addr)
1880 {
1881         struct bnxt *bp = eth_dev->data->dev_private;
1882         char *mc_addr_list = (char *)mc_addr_set;
1883         struct bnxt_vnic_info *vnic;
1884         uint32_t off = 0, i = 0;
1885         int rc;
1886
1887         rc = is_bnxt_in_error(bp);
1888         if (rc)
1889                 return rc;
1890
1891         vnic = &bp->vnic_info[0];
1892
1893         if (nb_mc_addr > BNXT_MAX_MC_ADDRS) {
1894                 vnic->flags |= BNXT_VNIC_INFO_ALLMULTI;
1895                 goto allmulti;
1896         }
1897
1898         /* TODO Check for Duplicate mcast addresses */
1899         vnic->flags &= ~BNXT_VNIC_INFO_ALLMULTI;
1900         for (i = 0; i < nb_mc_addr; i++) {
1901                 memcpy(vnic->mc_list + off, &mc_addr_list[i],
1902                         RTE_ETHER_ADDR_LEN);
1903                 off += RTE_ETHER_ADDR_LEN;
1904         }
1905
1906         vnic->mc_addr_cnt = i;
1907
1908 allmulti:
1909         return bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1910 }
1911
1912 static int
1913 bnxt_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size)
1914 {
1915         struct bnxt *bp = dev->data->dev_private;
1916         uint8_t fw_major = (bp->fw_ver >> 24) & 0xff;
1917         uint8_t fw_minor = (bp->fw_ver >> 16) & 0xff;
1918         uint8_t fw_updt = (bp->fw_ver >> 8) & 0xff;
1919         int ret;
1920
1921         ret = snprintf(fw_version, fw_size, "%d.%d.%d",
1922                         fw_major, fw_minor, fw_updt);
1923
1924         ret += 1; /* add the size of '\0' */
1925         if (fw_size < (uint32_t)ret)
1926                 return ret;
1927         else
1928                 return 0;
1929 }
1930
1931 static void
1932 bnxt_rxq_info_get_op(struct rte_eth_dev *dev, uint16_t queue_id,
1933         struct rte_eth_rxq_info *qinfo)
1934 {
1935         struct bnxt_rx_queue *rxq;
1936
1937         rxq = dev->data->rx_queues[queue_id];
1938
1939         qinfo->mp = rxq->mb_pool;
1940         qinfo->scattered_rx = dev->data->scattered_rx;
1941         qinfo->nb_desc = rxq->nb_rx_desc;
1942
1943         qinfo->conf.rx_free_thresh = rxq->rx_free_thresh;
1944         qinfo->conf.rx_drop_en = 0;
1945         qinfo->conf.rx_deferred_start = 0;
1946 }
1947
1948 static void
1949 bnxt_txq_info_get_op(struct rte_eth_dev *dev, uint16_t queue_id,
1950         struct rte_eth_txq_info *qinfo)
1951 {
1952         struct bnxt_tx_queue *txq;
1953
1954         txq = dev->data->tx_queues[queue_id];
1955
1956         qinfo->nb_desc = txq->nb_tx_desc;
1957
1958         qinfo->conf.tx_thresh.pthresh = txq->pthresh;
1959         qinfo->conf.tx_thresh.hthresh = txq->hthresh;
1960         qinfo->conf.tx_thresh.wthresh = txq->wthresh;
1961
1962         qinfo->conf.tx_free_thresh = txq->tx_free_thresh;
1963         qinfo->conf.tx_rs_thresh = 0;
1964         qinfo->conf.tx_deferred_start = txq->tx_deferred_start;
1965 }
1966
1967 static int bnxt_mtu_set_op(struct rte_eth_dev *eth_dev, uint16_t new_mtu)
1968 {
1969         struct bnxt *bp = eth_dev->data->dev_private;
1970         struct rte_eth_dev_info dev_info;
1971         uint32_t new_pkt_size;
1972         uint32_t rc = 0;
1973         uint32_t i;
1974
1975         rc = is_bnxt_in_error(bp);
1976         if (rc)
1977                 return rc;
1978
1979         new_pkt_size = new_mtu + RTE_ETHER_HDR_LEN + RTE_ETHER_CRC_LEN +
1980                        VLAN_TAG_SIZE * BNXT_NUM_VLANS;
1981
1982         rc = bnxt_dev_info_get_op(eth_dev, &dev_info);
1983         if (rc != 0) {
1984                 PMD_DRV_LOG(ERR, "Error during getting ethernet device info\n");
1985                 return rc;
1986         }
1987
1988         if (new_mtu < RTE_ETHER_MIN_MTU || new_mtu > BNXT_MAX_MTU) {
1989                 PMD_DRV_LOG(ERR, "MTU requested must be within (%d, %d)\n",
1990                         RTE_ETHER_MIN_MTU, BNXT_MAX_MTU);
1991                 return -EINVAL;
1992         }
1993
1994 #ifdef RTE_ARCH_X86
1995         /*
1996          * If vector-mode tx/rx is active, disallow any MTU change that would
1997          * require scattered receive support.
1998          */
1999         if (eth_dev->data->dev_started &&
2000             (eth_dev->rx_pkt_burst == bnxt_recv_pkts_vec ||
2001              eth_dev->tx_pkt_burst == bnxt_xmit_pkts_vec) &&
2002             (new_pkt_size >
2003              eth_dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM)) {
2004                 PMD_DRV_LOG(ERR,
2005                             "MTU change would require scattered rx support. ");
2006                 PMD_DRV_LOG(ERR, "Stop port before changing MTU.\n");
2007                 return -EINVAL;
2008         }
2009 #endif
2010
2011         if (new_mtu > RTE_ETHER_MTU) {
2012                 bp->flags |= BNXT_FLAG_JUMBO;
2013                 bp->eth_dev->data->dev_conf.rxmode.offloads |=
2014                         DEV_RX_OFFLOAD_JUMBO_FRAME;
2015         } else {
2016                 bp->eth_dev->data->dev_conf.rxmode.offloads &=
2017                         ~DEV_RX_OFFLOAD_JUMBO_FRAME;
2018                 bp->flags &= ~BNXT_FLAG_JUMBO;
2019         }
2020
2021         eth_dev->data->dev_conf.rxmode.max_rx_pkt_len = new_pkt_size;
2022
2023         eth_dev->data->mtu = new_mtu;
2024         PMD_DRV_LOG(INFO, "New MTU is %d\n", eth_dev->data->mtu);
2025
2026         for (i = 0; i < bp->nr_vnics; i++) {
2027                 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
2028                 uint16_t size = 0;
2029
2030                 vnic->mru = bp->eth_dev->data->mtu + RTE_ETHER_HDR_LEN +
2031                                         RTE_ETHER_CRC_LEN + VLAN_TAG_SIZE * 2;
2032                 rc = bnxt_hwrm_vnic_cfg(bp, vnic);
2033                 if (rc)
2034                         break;
2035
2036                 size = rte_pktmbuf_data_room_size(bp->rx_queues[0]->mb_pool);
2037                 size -= RTE_PKTMBUF_HEADROOM;
2038
2039                 if (size < new_mtu) {
2040                         rc = bnxt_hwrm_vnic_plcmode_cfg(bp, vnic);
2041                         if (rc)
2042                                 return rc;
2043                 }
2044         }
2045
2046         return rc;
2047 }
2048
2049 static int
2050 bnxt_vlan_pvid_set_op(struct rte_eth_dev *dev, uint16_t pvid, int on)
2051 {
2052         struct bnxt *bp = dev->data->dev_private;
2053         uint16_t vlan = bp->vlan;
2054         int rc;
2055
2056         rc = is_bnxt_in_error(bp);
2057         if (rc)
2058                 return rc;
2059
2060         if (!BNXT_SINGLE_PF(bp) || BNXT_VF(bp)) {
2061                 PMD_DRV_LOG(ERR,
2062                         "PVID cannot be modified for this function\n");
2063                 return -ENOTSUP;
2064         }
2065         bp->vlan = on ? pvid : 0;
2066
2067         rc = bnxt_hwrm_set_default_vlan(bp, 0, 0);
2068         if (rc)
2069                 bp->vlan = vlan;
2070         return rc;
2071 }
2072
2073 static int
2074 bnxt_dev_led_on_op(struct rte_eth_dev *dev)
2075 {
2076         struct bnxt *bp = dev->data->dev_private;
2077         int rc;
2078
2079         rc = is_bnxt_in_error(bp);
2080         if (rc)
2081                 return rc;
2082
2083         return bnxt_hwrm_port_led_cfg(bp, true);
2084 }
2085
2086 static int
2087 bnxt_dev_led_off_op(struct rte_eth_dev *dev)
2088 {
2089         struct bnxt *bp = dev->data->dev_private;
2090         int rc;
2091
2092         rc = is_bnxt_in_error(bp);
2093         if (rc)
2094                 return rc;
2095
2096         return bnxt_hwrm_port_led_cfg(bp, false);
2097 }
2098
2099 static uint32_t
2100 bnxt_rx_queue_count_op(struct rte_eth_dev *dev, uint16_t rx_queue_id)
2101 {
2102         struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
2103         uint32_t desc = 0, raw_cons = 0, cons;
2104         struct bnxt_cp_ring_info *cpr;
2105         struct bnxt_rx_queue *rxq;
2106         struct rx_pkt_cmpl *rxcmp;
2107         uint16_t cmp_type;
2108         uint8_t cmp = 1;
2109         bool valid;
2110         int rc;
2111
2112         rc = is_bnxt_in_error(bp);
2113         if (rc)
2114                 return rc;
2115
2116         rxq = dev->data->rx_queues[rx_queue_id];
2117         cpr = rxq->cp_ring;
2118         valid = cpr->valid;
2119
2120         while (raw_cons < rxq->nb_rx_desc) {
2121                 cons = RING_CMP(cpr->cp_ring_struct, raw_cons);
2122                 rxcmp = (struct rx_pkt_cmpl *)&cpr->cp_desc_ring[cons];
2123
2124                 if (!CMPL_VALID(rxcmp, valid))
2125                         goto nothing_to_do;
2126                 valid = FLIP_VALID(cons, cpr->cp_ring_struct->ring_mask, valid);
2127                 cmp_type = CMP_TYPE(rxcmp);
2128                 if (cmp_type == RX_TPA_END_CMPL_TYPE_RX_TPA_END) {
2129                         cmp = (rte_le_to_cpu_32(
2130                                         ((struct rx_tpa_end_cmpl *)
2131                                          (rxcmp))->agg_bufs_v1) &
2132                                RX_TPA_END_CMPL_AGG_BUFS_MASK) >>
2133                                 RX_TPA_END_CMPL_AGG_BUFS_SFT;
2134                         desc++;
2135                 } else if (cmp_type == 0x11) {
2136                         desc++;
2137                         cmp = (rxcmp->agg_bufs_v1 &
2138                                    RX_PKT_CMPL_AGG_BUFS_MASK) >>
2139                                 RX_PKT_CMPL_AGG_BUFS_SFT;
2140                 } else {
2141                         cmp = 1;
2142                 }
2143 nothing_to_do:
2144                 raw_cons += cmp ? cmp : 2;
2145         }
2146
2147         return desc;
2148 }
2149
2150 static int
2151 bnxt_rx_descriptor_status_op(void *rx_queue, uint16_t offset)
2152 {
2153         struct bnxt_rx_queue *rxq = (struct bnxt_rx_queue *)rx_queue;
2154         struct bnxt_rx_ring_info *rxr;
2155         struct bnxt_cp_ring_info *cpr;
2156         struct bnxt_sw_rx_bd *rx_buf;
2157         struct rx_pkt_cmpl *rxcmp;
2158         uint32_t cons, cp_cons;
2159         int rc;
2160
2161         if (!rxq)
2162                 return -EINVAL;
2163
2164         rc = is_bnxt_in_error(rxq->bp);
2165         if (rc)
2166                 return rc;
2167
2168         cpr = rxq->cp_ring;
2169         rxr = rxq->rx_ring;
2170
2171         if (offset >= rxq->nb_rx_desc)
2172                 return -EINVAL;
2173
2174         cons = RING_CMP(cpr->cp_ring_struct, offset);
2175         cp_cons = cpr->cp_raw_cons;
2176         rxcmp = (struct rx_pkt_cmpl *)&cpr->cp_desc_ring[cons];
2177
2178         if (cons > cp_cons) {
2179                 if (CMPL_VALID(rxcmp, cpr->valid))
2180                         return RTE_ETH_RX_DESC_DONE;
2181         } else {
2182                 if (CMPL_VALID(rxcmp, !cpr->valid))
2183                         return RTE_ETH_RX_DESC_DONE;
2184         }
2185         rx_buf = &rxr->rx_buf_ring[cons];
2186         if (rx_buf->mbuf == NULL)
2187                 return RTE_ETH_RX_DESC_UNAVAIL;
2188
2189
2190         return RTE_ETH_RX_DESC_AVAIL;
2191 }
2192
2193 static int
2194 bnxt_tx_descriptor_status_op(void *tx_queue, uint16_t offset)
2195 {
2196         struct bnxt_tx_queue *txq = (struct bnxt_tx_queue *)tx_queue;
2197         struct bnxt_tx_ring_info *txr;
2198         struct bnxt_cp_ring_info *cpr;
2199         struct bnxt_sw_tx_bd *tx_buf;
2200         struct tx_pkt_cmpl *txcmp;
2201         uint32_t cons, cp_cons;
2202         int rc;
2203
2204         if (!txq)
2205                 return -EINVAL;
2206
2207         rc = is_bnxt_in_error(txq->bp);
2208         if (rc)
2209                 return rc;
2210
2211         cpr = txq->cp_ring;
2212         txr = txq->tx_ring;
2213
2214         if (offset >= txq->nb_tx_desc)
2215                 return -EINVAL;
2216
2217         cons = RING_CMP(cpr->cp_ring_struct, offset);
2218         txcmp = (struct tx_pkt_cmpl *)&cpr->cp_desc_ring[cons];
2219         cp_cons = cpr->cp_raw_cons;
2220
2221         if (cons > cp_cons) {
2222                 if (CMPL_VALID(txcmp, cpr->valid))
2223                         return RTE_ETH_TX_DESC_UNAVAIL;
2224         } else {
2225                 if (CMPL_VALID(txcmp, !cpr->valid))
2226                         return RTE_ETH_TX_DESC_UNAVAIL;
2227         }
2228         tx_buf = &txr->tx_buf_ring[cons];
2229         if (tx_buf->mbuf == NULL)
2230                 return RTE_ETH_TX_DESC_DONE;
2231
2232         return RTE_ETH_TX_DESC_FULL;
2233 }
2234
2235 static struct bnxt_filter_info *
2236 bnxt_match_and_validate_ether_filter(struct bnxt *bp,
2237                                 struct rte_eth_ethertype_filter *efilter,
2238                                 struct bnxt_vnic_info *vnic0,
2239                                 struct bnxt_vnic_info *vnic,
2240                                 int *ret)
2241 {
2242         struct bnxt_filter_info *mfilter = NULL;
2243         int match = 0;
2244         *ret = 0;
2245
2246         if (efilter->ether_type == RTE_ETHER_TYPE_IPV4 ||
2247                 efilter->ether_type == RTE_ETHER_TYPE_IPV6) {
2248                 PMD_DRV_LOG(ERR, "invalid ether_type(0x%04x) in"
2249                         " ethertype filter.", efilter->ether_type);
2250                 *ret = -EINVAL;
2251                 goto exit;
2252         }
2253         if (efilter->queue >= bp->rx_nr_rings) {
2254                 PMD_DRV_LOG(ERR, "Invalid queue %d\n", efilter->queue);
2255                 *ret = -EINVAL;
2256                 goto exit;
2257         }
2258
2259         vnic0 = &bp->vnic_info[0];
2260         vnic = &bp->vnic_info[efilter->queue];
2261         if (vnic == NULL) {
2262                 PMD_DRV_LOG(ERR, "Invalid queue %d\n", efilter->queue);
2263                 *ret = -EINVAL;
2264                 goto exit;
2265         }
2266
2267         if (efilter->flags & RTE_ETHTYPE_FLAGS_DROP) {
2268                 STAILQ_FOREACH(mfilter, &vnic0->filter, next) {
2269                         if ((!memcmp(efilter->mac_addr.addr_bytes,
2270                                      mfilter->l2_addr, RTE_ETHER_ADDR_LEN) &&
2271                              mfilter->flags ==
2272                              HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_DROP &&
2273                              mfilter->ethertype == efilter->ether_type)) {
2274                                 match = 1;
2275                                 break;
2276                         }
2277                 }
2278         } else {
2279                 STAILQ_FOREACH(mfilter, &vnic->filter, next)
2280                         if ((!memcmp(efilter->mac_addr.addr_bytes,
2281                                      mfilter->l2_addr, RTE_ETHER_ADDR_LEN) &&
2282                              mfilter->ethertype == efilter->ether_type &&
2283                              mfilter->flags ==
2284                              HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_PATH_RX)) {
2285                                 match = 1;
2286                                 break;
2287                         }
2288         }
2289
2290         if (match)
2291                 *ret = -EEXIST;
2292
2293 exit:
2294         return mfilter;
2295 }
2296
2297 static int
2298 bnxt_ethertype_filter(struct rte_eth_dev *dev,
2299                         enum rte_filter_op filter_op,
2300                         void *arg)
2301 {
2302         struct bnxt *bp = dev->data->dev_private;
2303         struct rte_eth_ethertype_filter *efilter =
2304                         (struct rte_eth_ethertype_filter *)arg;
2305         struct bnxt_filter_info *bfilter, *filter1;
2306         struct bnxt_vnic_info *vnic, *vnic0;
2307         int ret;
2308
2309         if (filter_op == RTE_ETH_FILTER_NOP)
2310                 return 0;
2311
2312         if (arg == NULL) {
2313                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
2314                             filter_op);
2315                 return -EINVAL;
2316         }
2317
2318         vnic0 = &bp->vnic_info[0];
2319         vnic = &bp->vnic_info[efilter->queue];
2320
2321         switch (filter_op) {
2322         case RTE_ETH_FILTER_ADD:
2323                 bnxt_match_and_validate_ether_filter(bp, efilter,
2324                                                         vnic0, vnic, &ret);
2325                 if (ret < 0)
2326                         return ret;
2327
2328                 bfilter = bnxt_get_unused_filter(bp);
2329                 if (bfilter == NULL) {
2330                         PMD_DRV_LOG(ERR,
2331                                 "Not enough resources for a new filter.\n");
2332                         return -ENOMEM;
2333                 }
2334                 bfilter->filter_type = HWRM_CFA_NTUPLE_FILTER;
2335                 memcpy(bfilter->l2_addr, efilter->mac_addr.addr_bytes,
2336                        RTE_ETHER_ADDR_LEN);
2337                 memcpy(bfilter->dst_macaddr, efilter->mac_addr.addr_bytes,
2338                        RTE_ETHER_ADDR_LEN);
2339                 bfilter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_MACADDR;
2340                 bfilter->ethertype = efilter->ether_type;
2341                 bfilter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2342
2343                 filter1 = bnxt_get_l2_filter(bp, bfilter, vnic0);
2344                 if (filter1 == NULL) {
2345                         ret = -EINVAL;
2346                         goto cleanup;
2347                 }
2348                 bfilter->enables |=
2349                         HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID;
2350                 bfilter->fw_l2_filter_id = filter1->fw_l2_filter_id;
2351
2352                 bfilter->dst_id = vnic->fw_vnic_id;
2353
2354                 if (efilter->flags & RTE_ETHTYPE_FLAGS_DROP) {
2355                         bfilter->flags =
2356                                 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_DROP;
2357                 }
2358
2359                 ret = bnxt_hwrm_set_ntuple_filter(bp, bfilter->dst_id, bfilter);
2360                 if (ret)
2361                         goto cleanup;
2362                 STAILQ_INSERT_TAIL(&vnic->filter, bfilter, next);
2363                 break;
2364         case RTE_ETH_FILTER_DELETE:
2365                 filter1 = bnxt_match_and_validate_ether_filter(bp, efilter,
2366                                                         vnic0, vnic, &ret);
2367                 if (ret == -EEXIST) {
2368                         ret = bnxt_hwrm_clear_ntuple_filter(bp, filter1);
2369
2370                         STAILQ_REMOVE(&vnic->filter, filter1, bnxt_filter_info,
2371                                       next);
2372                         bnxt_free_filter(bp, filter1);
2373                 } else if (ret == 0) {
2374                         PMD_DRV_LOG(ERR, "No matching filter found\n");
2375                 }
2376                 break;
2377         default:
2378                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
2379                 ret = -EINVAL;
2380                 goto error;
2381         }
2382         return ret;
2383 cleanup:
2384         bnxt_free_filter(bp, bfilter);
2385 error:
2386         return ret;
2387 }
2388
2389 static inline int
2390 parse_ntuple_filter(struct bnxt *bp,
2391                     struct rte_eth_ntuple_filter *nfilter,
2392                     struct bnxt_filter_info *bfilter)
2393 {
2394         uint32_t en = 0;
2395
2396         if (nfilter->queue >= bp->rx_nr_rings) {
2397                 PMD_DRV_LOG(ERR, "Invalid queue %d\n", nfilter->queue);
2398                 return -EINVAL;
2399         }
2400
2401         switch (nfilter->dst_port_mask) {
2402         case UINT16_MAX:
2403                 bfilter->dst_port_mask = -1;
2404                 bfilter->dst_port = nfilter->dst_port;
2405                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT |
2406                         NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
2407                 break;
2408         default:
2409                 PMD_DRV_LOG(ERR, "invalid dst_port mask.");
2410                 return -EINVAL;
2411         }
2412
2413         bfilter->ip_addr_type = NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4;
2414         en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2415
2416         switch (nfilter->proto_mask) {
2417         case UINT8_MAX:
2418                 if (nfilter->proto == 17) /* IPPROTO_UDP */
2419                         bfilter->ip_protocol = 17;
2420                 else if (nfilter->proto == 6) /* IPPROTO_TCP */
2421                         bfilter->ip_protocol = 6;
2422                 else
2423                         return -EINVAL;
2424                 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2425                 break;
2426         default:
2427                 PMD_DRV_LOG(ERR, "invalid protocol mask.");
2428                 return -EINVAL;
2429         }
2430
2431         switch (nfilter->dst_ip_mask) {
2432         case UINT32_MAX:
2433                 bfilter->dst_ipaddr_mask[0] = -1;
2434                 bfilter->dst_ipaddr[0] = nfilter->dst_ip;
2435                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR |
2436                         NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2437                 break;
2438         default:
2439                 PMD_DRV_LOG(ERR, "invalid dst_ip mask.");
2440                 return -EINVAL;
2441         }
2442
2443         switch (nfilter->src_ip_mask) {
2444         case UINT32_MAX:
2445                 bfilter->src_ipaddr_mask[0] = -1;
2446                 bfilter->src_ipaddr[0] = nfilter->src_ip;
2447                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR |
2448                         NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2449                 break;
2450         default:
2451                 PMD_DRV_LOG(ERR, "invalid src_ip mask.");
2452                 return -EINVAL;
2453         }
2454
2455         switch (nfilter->src_port_mask) {
2456         case UINT16_MAX:
2457                 bfilter->src_port_mask = -1;
2458                 bfilter->src_port = nfilter->src_port;
2459                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT |
2460                         NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
2461                 break;
2462         default:
2463                 PMD_DRV_LOG(ERR, "invalid src_port mask.");
2464                 return -EINVAL;
2465         }
2466
2467         //TODO Priority
2468         //nfilter->priority = (uint8_t)filter->priority;
2469
2470         bfilter->enables = en;
2471         return 0;
2472 }
2473
2474 static struct bnxt_filter_info*
2475 bnxt_match_ntuple_filter(struct bnxt *bp,
2476                          struct bnxt_filter_info *bfilter,
2477                          struct bnxt_vnic_info **mvnic)
2478 {
2479         struct bnxt_filter_info *mfilter = NULL;
2480         int i;
2481
2482         for (i = bp->nr_vnics - 1; i >= 0; i--) {
2483                 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
2484                 STAILQ_FOREACH(mfilter, &vnic->filter, next) {
2485                         if (bfilter->src_ipaddr[0] == mfilter->src_ipaddr[0] &&
2486                             bfilter->src_ipaddr_mask[0] ==
2487                             mfilter->src_ipaddr_mask[0] &&
2488                             bfilter->src_port == mfilter->src_port &&
2489                             bfilter->src_port_mask == mfilter->src_port_mask &&
2490                             bfilter->dst_ipaddr[0] == mfilter->dst_ipaddr[0] &&
2491                             bfilter->dst_ipaddr_mask[0] ==
2492                             mfilter->dst_ipaddr_mask[0] &&
2493                             bfilter->dst_port == mfilter->dst_port &&
2494                             bfilter->dst_port_mask == mfilter->dst_port_mask &&
2495                             bfilter->flags == mfilter->flags &&
2496                             bfilter->enables == mfilter->enables) {
2497                                 if (mvnic)
2498                                         *mvnic = vnic;
2499                                 return mfilter;
2500                         }
2501                 }
2502         }
2503         return NULL;
2504 }
2505
2506 static int
2507 bnxt_cfg_ntuple_filter(struct bnxt *bp,
2508                        struct rte_eth_ntuple_filter *nfilter,
2509                        enum rte_filter_op filter_op)
2510 {
2511         struct bnxt_filter_info *bfilter, *mfilter, *filter1;
2512         struct bnxt_vnic_info *vnic, *vnic0, *mvnic;
2513         int ret;
2514
2515         if (nfilter->flags != RTE_5TUPLE_FLAGS) {
2516                 PMD_DRV_LOG(ERR, "only 5tuple is supported.");
2517                 return -EINVAL;
2518         }
2519
2520         if (nfilter->flags & RTE_NTUPLE_FLAGS_TCP_FLAG) {
2521                 PMD_DRV_LOG(ERR, "Ntuple filter: TCP flags not supported\n");
2522                 return -EINVAL;
2523         }
2524
2525         bfilter = bnxt_get_unused_filter(bp);
2526         if (bfilter == NULL) {
2527                 PMD_DRV_LOG(ERR,
2528                         "Not enough resources for a new filter.\n");
2529                 return -ENOMEM;
2530         }
2531         ret = parse_ntuple_filter(bp, nfilter, bfilter);
2532         if (ret < 0)
2533                 goto free_filter;
2534
2535         vnic = &bp->vnic_info[nfilter->queue];
2536         vnic0 = &bp->vnic_info[0];
2537         filter1 = STAILQ_FIRST(&vnic0->filter);
2538         if (filter1 == NULL) {
2539                 ret = -EINVAL;
2540                 goto free_filter;
2541         }
2542
2543         bfilter->dst_id = vnic->fw_vnic_id;
2544         bfilter->fw_l2_filter_id = filter1->fw_l2_filter_id;
2545         bfilter->enables |=
2546                 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID;
2547         bfilter->ethertype = 0x800;
2548         bfilter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2549
2550         mfilter = bnxt_match_ntuple_filter(bp, bfilter, &mvnic);
2551
2552         if (mfilter != NULL && filter_op == RTE_ETH_FILTER_ADD &&
2553             bfilter->dst_id == mfilter->dst_id) {
2554                 PMD_DRV_LOG(ERR, "filter exists.\n");
2555                 ret = -EEXIST;
2556                 goto free_filter;
2557         } else if (mfilter != NULL && filter_op == RTE_ETH_FILTER_ADD &&
2558                    bfilter->dst_id != mfilter->dst_id) {
2559                 mfilter->dst_id = vnic->fw_vnic_id;
2560                 ret = bnxt_hwrm_set_ntuple_filter(bp, mfilter->dst_id, mfilter);
2561                 STAILQ_REMOVE(&mvnic->filter, mfilter, bnxt_filter_info, next);
2562                 STAILQ_INSERT_TAIL(&vnic->filter, mfilter, next);
2563                 PMD_DRV_LOG(ERR, "filter with matching pattern exists.\n");
2564                 PMD_DRV_LOG(ERR, " Updated it to the new destination queue\n");
2565                 goto free_filter;
2566         }
2567         if (mfilter == NULL && filter_op == RTE_ETH_FILTER_DELETE) {
2568                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
2569                 ret = -ENOENT;
2570                 goto free_filter;
2571         }
2572
2573         if (filter_op == RTE_ETH_FILTER_ADD) {
2574                 bfilter->filter_type = HWRM_CFA_NTUPLE_FILTER;
2575                 ret = bnxt_hwrm_set_ntuple_filter(bp, bfilter->dst_id, bfilter);
2576                 if (ret)
2577                         goto free_filter;
2578                 STAILQ_INSERT_TAIL(&vnic->filter, bfilter, next);
2579         } else {
2580                 if (mfilter == NULL) {
2581                         /* This should not happen. But for Coverity! */
2582                         ret = -ENOENT;
2583                         goto free_filter;
2584                 }
2585                 ret = bnxt_hwrm_clear_ntuple_filter(bp, mfilter);
2586
2587                 STAILQ_REMOVE(&vnic->filter, mfilter, bnxt_filter_info, next);
2588                 bnxt_free_filter(bp, mfilter);
2589                 mfilter->fw_l2_filter_id = -1;
2590                 bnxt_free_filter(bp, bfilter);
2591                 bfilter->fw_l2_filter_id = -1;
2592         }
2593
2594         return 0;
2595 free_filter:
2596         bfilter->fw_l2_filter_id = -1;
2597         bnxt_free_filter(bp, bfilter);
2598         return ret;
2599 }
2600
2601 static int
2602 bnxt_ntuple_filter(struct rte_eth_dev *dev,
2603                         enum rte_filter_op filter_op,
2604                         void *arg)
2605 {
2606         struct bnxt *bp = dev->data->dev_private;
2607         int ret;
2608
2609         if (filter_op == RTE_ETH_FILTER_NOP)
2610                 return 0;
2611
2612         if (arg == NULL) {
2613                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
2614                             filter_op);
2615                 return -EINVAL;
2616         }
2617
2618         switch (filter_op) {
2619         case RTE_ETH_FILTER_ADD:
2620                 ret = bnxt_cfg_ntuple_filter(bp,
2621                         (struct rte_eth_ntuple_filter *)arg,
2622                         filter_op);
2623                 break;
2624         case RTE_ETH_FILTER_DELETE:
2625                 ret = bnxt_cfg_ntuple_filter(bp,
2626                         (struct rte_eth_ntuple_filter *)arg,
2627                         filter_op);
2628                 break;
2629         default:
2630                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
2631                 ret = -EINVAL;
2632                 break;
2633         }
2634         return ret;
2635 }
2636
2637 static int
2638 bnxt_parse_fdir_filter(struct bnxt *bp,
2639                        struct rte_eth_fdir_filter *fdir,
2640                        struct bnxt_filter_info *filter)
2641 {
2642         enum rte_fdir_mode fdir_mode =
2643                 bp->eth_dev->data->dev_conf.fdir_conf.mode;
2644         struct bnxt_vnic_info *vnic0, *vnic;
2645         struct bnxt_filter_info *filter1;
2646         uint32_t en = 0;
2647         int i;
2648
2649         if (fdir_mode == RTE_FDIR_MODE_PERFECT_TUNNEL)
2650                 return -EINVAL;
2651
2652         filter->l2_ovlan = fdir->input.flow_ext.vlan_tci;
2653         en |= EM_FLOW_ALLOC_INPUT_EN_OVLAN_VID;
2654
2655         switch (fdir->input.flow_type) {
2656         case RTE_ETH_FLOW_IPV4:
2657         case RTE_ETH_FLOW_NONFRAG_IPV4_OTHER:
2658                 /* FALLTHROUGH */
2659                 filter->src_ipaddr[0] = fdir->input.flow.ip4_flow.src_ip;
2660                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
2661                 filter->dst_ipaddr[0] = fdir->input.flow.ip4_flow.dst_ip;
2662                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
2663                 filter->ip_protocol = fdir->input.flow.ip4_flow.proto;
2664                 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2665                 filter->ip_addr_type =
2666                         NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4;
2667                 filter->src_ipaddr_mask[0] = 0xffffffff;
2668                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2669                 filter->dst_ipaddr_mask[0] = 0xffffffff;
2670                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2671                 filter->ethertype = 0x800;
2672                 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2673                 break;
2674         case RTE_ETH_FLOW_NONFRAG_IPV4_TCP:
2675                 filter->src_port = fdir->input.flow.tcp4_flow.src_port;
2676                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT;
2677                 filter->dst_port = fdir->input.flow.tcp4_flow.dst_port;
2678                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT;
2679                 filter->dst_port_mask = 0xffff;
2680                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
2681                 filter->src_port_mask = 0xffff;
2682                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
2683                 filter->src_ipaddr[0] = fdir->input.flow.tcp4_flow.ip.src_ip;
2684                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
2685                 filter->dst_ipaddr[0] = fdir->input.flow.tcp4_flow.ip.dst_ip;
2686                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
2687                 filter->ip_protocol = 6;
2688                 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2689                 filter->ip_addr_type =
2690                         NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4;
2691                 filter->src_ipaddr_mask[0] = 0xffffffff;
2692                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2693                 filter->dst_ipaddr_mask[0] = 0xffffffff;
2694                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2695                 filter->ethertype = 0x800;
2696                 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2697                 break;
2698         case RTE_ETH_FLOW_NONFRAG_IPV4_UDP:
2699                 filter->src_port = fdir->input.flow.udp4_flow.src_port;
2700                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT;
2701                 filter->dst_port = fdir->input.flow.udp4_flow.dst_port;
2702                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT;
2703                 filter->dst_port_mask = 0xffff;
2704                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
2705                 filter->src_port_mask = 0xffff;
2706                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
2707                 filter->src_ipaddr[0] = fdir->input.flow.udp4_flow.ip.src_ip;
2708                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
2709                 filter->dst_ipaddr[0] = fdir->input.flow.udp4_flow.ip.dst_ip;
2710                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
2711                 filter->ip_protocol = 17;
2712                 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2713                 filter->ip_addr_type =
2714                         NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4;
2715                 filter->src_ipaddr_mask[0] = 0xffffffff;
2716                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2717                 filter->dst_ipaddr_mask[0] = 0xffffffff;
2718                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2719                 filter->ethertype = 0x800;
2720                 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2721                 break;
2722         case RTE_ETH_FLOW_IPV6:
2723         case RTE_ETH_FLOW_NONFRAG_IPV6_OTHER:
2724                 /* FALLTHROUGH */
2725                 filter->ip_addr_type =
2726                         NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV6;
2727                 filter->ip_protocol = fdir->input.flow.ipv6_flow.proto;
2728                 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2729                 rte_memcpy(filter->src_ipaddr,
2730                            fdir->input.flow.ipv6_flow.src_ip, 16);
2731                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
2732                 rte_memcpy(filter->dst_ipaddr,
2733                            fdir->input.flow.ipv6_flow.dst_ip, 16);
2734                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
2735                 memset(filter->dst_ipaddr_mask, 0xff, 16);
2736                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2737                 memset(filter->src_ipaddr_mask, 0xff, 16);
2738                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2739                 filter->ethertype = 0x86dd;
2740                 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2741                 break;
2742         case RTE_ETH_FLOW_NONFRAG_IPV6_TCP:
2743                 filter->src_port = fdir->input.flow.tcp6_flow.src_port;
2744                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT;
2745                 filter->dst_port = fdir->input.flow.tcp6_flow.dst_port;
2746                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT;
2747                 filter->dst_port_mask = 0xffff;
2748                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
2749                 filter->src_port_mask = 0xffff;
2750                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
2751                 filter->ip_addr_type =
2752                         NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV6;
2753                 filter->ip_protocol = fdir->input.flow.tcp6_flow.ip.proto;
2754                 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2755                 rte_memcpy(filter->src_ipaddr,
2756                            fdir->input.flow.tcp6_flow.ip.src_ip, 16);
2757                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
2758                 rte_memcpy(filter->dst_ipaddr,
2759                            fdir->input.flow.tcp6_flow.ip.dst_ip, 16);
2760                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
2761                 memset(filter->dst_ipaddr_mask, 0xff, 16);
2762                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2763                 memset(filter->src_ipaddr_mask, 0xff, 16);
2764                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2765                 filter->ethertype = 0x86dd;
2766                 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2767                 break;
2768         case RTE_ETH_FLOW_NONFRAG_IPV6_UDP:
2769                 filter->src_port = fdir->input.flow.udp6_flow.src_port;
2770                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT;
2771                 filter->dst_port = fdir->input.flow.udp6_flow.dst_port;
2772                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT;
2773                 filter->dst_port_mask = 0xffff;
2774                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
2775                 filter->src_port_mask = 0xffff;
2776                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
2777                 filter->ip_addr_type =
2778                         NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV6;
2779                 filter->ip_protocol = fdir->input.flow.udp6_flow.ip.proto;
2780                 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2781                 rte_memcpy(filter->src_ipaddr,
2782                            fdir->input.flow.udp6_flow.ip.src_ip, 16);
2783                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
2784                 rte_memcpy(filter->dst_ipaddr,
2785                            fdir->input.flow.udp6_flow.ip.dst_ip, 16);
2786                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
2787                 memset(filter->dst_ipaddr_mask, 0xff, 16);
2788                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2789                 memset(filter->src_ipaddr_mask, 0xff, 16);
2790                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2791                 filter->ethertype = 0x86dd;
2792                 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2793                 break;
2794         case RTE_ETH_FLOW_L2_PAYLOAD:
2795                 filter->ethertype = fdir->input.flow.l2_flow.ether_type;
2796                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2797                 break;
2798         case RTE_ETH_FLOW_VXLAN:
2799                 if (fdir->action.behavior == RTE_ETH_FDIR_REJECT)
2800                         return -EINVAL;
2801                 filter->vni = fdir->input.flow.tunnel_flow.tunnel_id;
2802                 filter->tunnel_type =
2803                         CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN;
2804                 en |= HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_TUNNEL_TYPE;
2805                 break;
2806         case RTE_ETH_FLOW_NVGRE:
2807                 if (fdir->action.behavior == RTE_ETH_FDIR_REJECT)
2808                         return -EINVAL;
2809                 filter->vni = fdir->input.flow.tunnel_flow.tunnel_id;
2810                 filter->tunnel_type =
2811                         CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_NVGRE;
2812                 en |= HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_TUNNEL_TYPE;
2813                 break;
2814         case RTE_ETH_FLOW_UNKNOWN:
2815         case RTE_ETH_FLOW_RAW:
2816         case RTE_ETH_FLOW_FRAG_IPV4:
2817         case RTE_ETH_FLOW_NONFRAG_IPV4_SCTP:
2818         case RTE_ETH_FLOW_FRAG_IPV6:
2819         case RTE_ETH_FLOW_NONFRAG_IPV6_SCTP:
2820         case RTE_ETH_FLOW_IPV6_EX:
2821         case RTE_ETH_FLOW_IPV6_TCP_EX:
2822         case RTE_ETH_FLOW_IPV6_UDP_EX:
2823         case RTE_ETH_FLOW_GENEVE:
2824                 /* FALLTHROUGH */
2825         default:
2826                 return -EINVAL;
2827         }
2828
2829         vnic0 = &bp->vnic_info[0];
2830         vnic = &bp->vnic_info[fdir->action.rx_queue];
2831         if (vnic == NULL) {
2832                 PMD_DRV_LOG(ERR, "Invalid queue %d\n", fdir->action.rx_queue);
2833                 return -EINVAL;
2834         }
2835
2836
2837         if (fdir_mode == RTE_FDIR_MODE_PERFECT_MAC_VLAN) {
2838                 rte_memcpy(filter->dst_macaddr,
2839                         fdir->input.flow.mac_vlan_flow.mac_addr.addr_bytes, 6);
2840                         en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_MACADDR;
2841         }
2842
2843         if (fdir->action.behavior == RTE_ETH_FDIR_REJECT) {
2844                 filter->flags = HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_DROP;
2845                 filter1 = STAILQ_FIRST(&vnic0->filter);
2846                 //filter1 = bnxt_get_l2_filter(bp, filter, vnic0);
2847         } else {
2848                 filter->dst_id = vnic->fw_vnic_id;
2849                 for (i = 0; i < RTE_ETHER_ADDR_LEN; i++)
2850                         if (filter->dst_macaddr[i] == 0x00)
2851                                 filter1 = STAILQ_FIRST(&vnic0->filter);
2852                         else
2853                                 filter1 = bnxt_get_l2_filter(bp, filter, vnic);
2854         }
2855
2856         if (filter1 == NULL)
2857                 return -EINVAL;
2858
2859         en |= HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID;
2860         filter->fw_l2_filter_id = filter1->fw_l2_filter_id;
2861
2862         filter->enables = en;
2863
2864         return 0;
2865 }
2866
2867 static struct bnxt_filter_info *
2868 bnxt_match_fdir(struct bnxt *bp, struct bnxt_filter_info *nf,
2869                 struct bnxt_vnic_info **mvnic)
2870 {
2871         struct bnxt_filter_info *mf = NULL;
2872         int i;
2873
2874         for (i = bp->nr_vnics - 1; i >= 0; i--) {
2875                 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
2876
2877                 STAILQ_FOREACH(mf, &vnic->filter, next) {
2878                         if (mf->filter_type == nf->filter_type &&
2879                             mf->flags == nf->flags &&
2880                             mf->src_port == nf->src_port &&
2881                             mf->src_port_mask == nf->src_port_mask &&
2882                             mf->dst_port == nf->dst_port &&
2883                             mf->dst_port_mask == nf->dst_port_mask &&
2884                             mf->ip_protocol == nf->ip_protocol &&
2885                             mf->ip_addr_type == nf->ip_addr_type &&
2886                             mf->ethertype == nf->ethertype &&
2887                             mf->vni == nf->vni &&
2888                             mf->tunnel_type == nf->tunnel_type &&
2889                             mf->l2_ovlan == nf->l2_ovlan &&
2890                             mf->l2_ovlan_mask == nf->l2_ovlan_mask &&
2891                             mf->l2_ivlan == nf->l2_ivlan &&
2892                             mf->l2_ivlan_mask == nf->l2_ivlan_mask &&
2893                             !memcmp(mf->l2_addr, nf->l2_addr,
2894                                     RTE_ETHER_ADDR_LEN) &&
2895                             !memcmp(mf->l2_addr_mask, nf->l2_addr_mask,
2896                                     RTE_ETHER_ADDR_LEN) &&
2897                             !memcmp(mf->src_macaddr, nf->src_macaddr,
2898                                     RTE_ETHER_ADDR_LEN) &&
2899                             !memcmp(mf->dst_macaddr, nf->dst_macaddr,
2900                                     RTE_ETHER_ADDR_LEN) &&
2901                             !memcmp(mf->src_ipaddr, nf->src_ipaddr,
2902                                     sizeof(nf->src_ipaddr)) &&
2903                             !memcmp(mf->src_ipaddr_mask, nf->src_ipaddr_mask,
2904                                     sizeof(nf->src_ipaddr_mask)) &&
2905                             !memcmp(mf->dst_ipaddr, nf->dst_ipaddr,
2906                                     sizeof(nf->dst_ipaddr)) &&
2907                             !memcmp(mf->dst_ipaddr_mask, nf->dst_ipaddr_mask,
2908                                     sizeof(nf->dst_ipaddr_mask))) {
2909                                 if (mvnic)
2910                                         *mvnic = vnic;
2911                                 return mf;
2912                         }
2913                 }
2914         }
2915         return NULL;
2916 }
2917
2918 static int
2919 bnxt_fdir_filter(struct rte_eth_dev *dev,
2920                  enum rte_filter_op filter_op,
2921                  void *arg)
2922 {
2923         struct bnxt *bp = dev->data->dev_private;
2924         struct rte_eth_fdir_filter *fdir  = (struct rte_eth_fdir_filter *)arg;
2925         struct bnxt_filter_info *filter, *match;
2926         struct bnxt_vnic_info *vnic, *mvnic;
2927         int ret = 0, i;
2928
2929         if (filter_op == RTE_ETH_FILTER_NOP)
2930                 return 0;
2931
2932         if (arg == NULL && filter_op != RTE_ETH_FILTER_FLUSH)
2933                 return -EINVAL;
2934
2935         switch (filter_op) {
2936         case RTE_ETH_FILTER_ADD:
2937         case RTE_ETH_FILTER_DELETE:
2938                 /* FALLTHROUGH */
2939                 filter = bnxt_get_unused_filter(bp);
2940                 if (filter == NULL) {
2941                         PMD_DRV_LOG(ERR,
2942                                 "Not enough resources for a new flow.\n");
2943                         return -ENOMEM;
2944                 }
2945
2946                 ret = bnxt_parse_fdir_filter(bp, fdir, filter);
2947                 if (ret != 0)
2948                         goto free_filter;
2949                 filter->filter_type = HWRM_CFA_NTUPLE_FILTER;
2950
2951                 if (fdir->action.behavior == RTE_ETH_FDIR_REJECT)
2952                         vnic = &bp->vnic_info[0];
2953                 else
2954                         vnic = &bp->vnic_info[fdir->action.rx_queue];
2955
2956                 match = bnxt_match_fdir(bp, filter, &mvnic);
2957                 if (match != NULL && filter_op == RTE_ETH_FILTER_ADD) {
2958                         if (match->dst_id == vnic->fw_vnic_id) {
2959                                 PMD_DRV_LOG(ERR, "Flow already exists.\n");
2960                                 ret = -EEXIST;
2961                                 goto free_filter;
2962                         } else {
2963                                 match->dst_id = vnic->fw_vnic_id;
2964                                 ret = bnxt_hwrm_set_ntuple_filter(bp,
2965                                                                   match->dst_id,
2966                                                                   match);
2967                                 STAILQ_REMOVE(&mvnic->filter, match,
2968                                               bnxt_filter_info, next);
2969                                 STAILQ_INSERT_TAIL(&vnic->filter, match, next);
2970                                 PMD_DRV_LOG(ERR,
2971                                         "Filter with matching pattern exist\n");
2972                                 PMD_DRV_LOG(ERR,
2973                                         "Updated it to new destination q\n");
2974                                 goto free_filter;
2975                         }
2976                 }
2977                 if (match == NULL && filter_op == RTE_ETH_FILTER_DELETE) {
2978                         PMD_DRV_LOG(ERR, "Flow does not exist.\n");
2979                         ret = -ENOENT;
2980                         goto free_filter;
2981                 }
2982
2983                 if (filter_op == RTE_ETH_FILTER_ADD) {
2984                         ret = bnxt_hwrm_set_ntuple_filter(bp,
2985                                                           filter->dst_id,
2986                                                           filter);
2987                         if (ret)
2988                                 goto free_filter;
2989                         STAILQ_INSERT_TAIL(&vnic->filter, filter, next);
2990                 } else {
2991                         ret = bnxt_hwrm_clear_ntuple_filter(bp, match);
2992                         STAILQ_REMOVE(&vnic->filter, match,
2993                                       bnxt_filter_info, next);
2994                         bnxt_free_filter(bp, match);
2995                         filter->fw_l2_filter_id = -1;
2996                         bnxt_free_filter(bp, filter);
2997                 }
2998                 break;
2999         case RTE_ETH_FILTER_FLUSH:
3000                 for (i = bp->nr_vnics - 1; i >= 0; i--) {
3001                         struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
3002
3003                         STAILQ_FOREACH(filter, &vnic->filter, next) {
3004                                 if (filter->filter_type ==
3005                                     HWRM_CFA_NTUPLE_FILTER) {
3006                                         ret =
3007                                         bnxt_hwrm_clear_ntuple_filter(bp,
3008                                                                       filter);
3009                                         STAILQ_REMOVE(&vnic->filter, filter,
3010                                                       bnxt_filter_info, next);
3011                                 }
3012                         }
3013                 }
3014                 return ret;
3015         case RTE_ETH_FILTER_UPDATE:
3016         case RTE_ETH_FILTER_STATS:
3017         case RTE_ETH_FILTER_INFO:
3018                 PMD_DRV_LOG(ERR, "operation %u not implemented", filter_op);
3019                 break;
3020         default:
3021                 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
3022                 ret = -EINVAL;
3023                 break;
3024         }
3025         return ret;
3026
3027 free_filter:
3028         filter->fw_l2_filter_id = -1;
3029         bnxt_free_filter(bp, filter);
3030         return ret;
3031 }
3032
3033 static int
3034 bnxt_filter_ctrl_op(struct rte_eth_dev *dev __rte_unused,
3035                     enum rte_filter_type filter_type,
3036                     enum rte_filter_op filter_op, void *arg)
3037 {
3038         int ret = 0;
3039
3040         ret = is_bnxt_in_error(dev->data->dev_private);
3041         if (ret)
3042                 return ret;
3043
3044         switch (filter_type) {
3045         case RTE_ETH_FILTER_TUNNEL:
3046                 PMD_DRV_LOG(ERR,
3047                         "filter type: %d: To be implemented\n", filter_type);
3048                 break;
3049         case RTE_ETH_FILTER_FDIR:
3050                 ret = bnxt_fdir_filter(dev, filter_op, arg);
3051                 break;
3052         case RTE_ETH_FILTER_NTUPLE:
3053                 ret = bnxt_ntuple_filter(dev, filter_op, arg);
3054                 break;
3055         case RTE_ETH_FILTER_ETHERTYPE:
3056                 ret = bnxt_ethertype_filter(dev, filter_op, arg);
3057                 break;
3058         case RTE_ETH_FILTER_GENERIC:
3059                 if (filter_op != RTE_ETH_FILTER_GET)
3060                         return -EINVAL;
3061                 *(const void **)arg = &bnxt_flow_ops;
3062                 break;
3063         default:
3064                 PMD_DRV_LOG(ERR,
3065                         "Filter type (%d) not supported", filter_type);
3066                 ret = -EINVAL;
3067                 break;
3068         }
3069         return ret;
3070 }
3071
3072 static const uint32_t *
3073 bnxt_dev_supported_ptypes_get_op(struct rte_eth_dev *dev)
3074 {
3075         static const uint32_t ptypes[] = {
3076                 RTE_PTYPE_L2_ETHER_VLAN,
3077                 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN,
3078                 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN,
3079                 RTE_PTYPE_L4_ICMP,
3080                 RTE_PTYPE_L4_TCP,
3081                 RTE_PTYPE_L4_UDP,
3082                 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN,
3083                 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN,
3084                 RTE_PTYPE_INNER_L4_ICMP,
3085                 RTE_PTYPE_INNER_L4_TCP,
3086                 RTE_PTYPE_INNER_L4_UDP,
3087                 RTE_PTYPE_UNKNOWN
3088         };
3089
3090         if (!dev->rx_pkt_burst)
3091                 return NULL;
3092
3093         return ptypes;
3094 }
3095
3096 static int bnxt_map_regs(struct bnxt *bp, uint32_t *reg_arr, int count,
3097                          int reg_win)
3098 {
3099         uint32_t reg_base = *reg_arr & 0xfffff000;
3100         uint32_t win_off;
3101         int i;
3102
3103         for (i = 0; i < count; i++) {
3104                 if ((reg_arr[i] & 0xfffff000) != reg_base)
3105                         return -ERANGE;
3106         }
3107         win_off = BNXT_GRCPF_REG_WINDOW_BASE_OUT + (reg_win - 1) * 4;
3108         rte_write32(reg_base, (uint8_t *)bp->bar0 + win_off);
3109         return 0;
3110 }
3111
3112 static int bnxt_map_ptp_regs(struct bnxt *bp)
3113 {
3114         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3115         uint32_t *reg_arr;
3116         int rc, i;
3117
3118         reg_arr = ptp->rx_regs;
3119         rc = bnxt_map_regs(bp, reg_arr, BNXT_PTP_RX_REGS, 5);
3120         if (rc)
3121                 return rc;
3122
3123         reg_arr = ptp->tx_regs;
3124         rc = bnxt_map_regs(bp, reg_arr, BNXT_PTP_TX_REGS, 6);
3125         if (rc)
3126                 return rc;
3127
3128         for (i = 0; i < BNXT_PTP_RX_REGS; i++)
3129                 ptp->rx_mapped_regs[i] = 0x5000 + (ptp->rx_regs[i] & 0xfff);
3130
3131         for (i = 0; i < BNXT_PTP_TX_REGS; i++)
3132                 ptp->tx_mapped_regs[i] = 0x6000 + (ptp->tx_regs[i] & 0xfff);
3133
3134         return 0;
3135 }
3136
3137 static void bnxt_unmap_ptp_regs(struct bnxt *bp)
3138 {
3139         rte_write32(0, (uint8_t *)bp->bar0 +
3140                          BNXT_GRCPF_REG_WINDOW_BASE_OUT + 16);
3141         rte_write32(0, (uint8_t *)bp->bar0 +
3142                          BNXT_GRCPF_REG_WINDOW_BASE_OUT + 20);
3143 }
3144
3145 static uint64_t bnxt_cc_read(struct bnxt *bp)
3146 {
3147         uint64_t ns;
3148
3149         ns = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3150                               BNXT_GRCPF_REG_SYNC_TIME));
3151         ns |= (uint64_t)(rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3152                                           BNXT_GRCPF_REG_SYNC_TIME + 4))) << 32;
3153         return ns;
3154 }
3155
3156 static int bnxt_get_tx_ts(struct bnxt *bp, uint64_t *ts)
3157 {
3158         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3159         uint32_t fifo;
3160
3161         fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3162                                 ptp->tx_mapped_regs[BNXT_PTP_TX_FIFO]));
3163         if (fifo & BNXT_PTP_TX_FIFO_EMPTY)
3164                 return -EAGAIN;
3165
3166         fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3167                                 ptp->tx_mapped_regs[BNXT_PTP_TX_FIFO]));
3168         *ts = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3169                                 ptp->tx_mapped_regs[BNXT_PTP_TX_TS_L]));
3170         *ts |= (uint64_t)rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3171                                 ptp->tx_mapped_regs[BNXT_PTP_TX_TS_H])) << 32;
3172
3173         return 0;
3174 }
3175
3176 static int bnxt_get_rx_ts(struct bnxt *bp, uint64_t *ts)
3177 {
3178         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3179         struct bnxt_pf_info *pf = &bp->pf;
3180         uint16_t port_id;
3181         uint32_t fifo;
3182
3183         if (!ptp)
3184                 return -ENODEV;
3185
3186         fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3187                                 ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO]));
3188         if (!(fifo & BNXT_PTP_RX_FIFO_PENDING))
3189                 return -EAGAIN;
3190
3191         port_id = pf->port_id;
3192         rte_write32(1 << port_id, (uint8_t *)bp->bar0 +
3193                ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO_ADV]);
3194
3195         fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3196                                    ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO]));
3197         if (fifo & BNXT_PTP_RX_FIFO_PENDING) {
3198 /*              bnxt_clr_rx_ts(bp);       TBD  */
3199                 return -EBUSY;
3200         }
3201
3202         *ts = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3203                                 ptp->rx_mapped_regs[BNXT_PTP_RX_TS_L]));
3204         *ts |= (uint64_t)rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3205                                 ptp->rx_mapped_regs[BNXT_PTP_RX_TS_H])) << 32;
3206
3207         return 0;
3208 }
3209
3210 static int
3211 bnxt_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
3212 {
3213         uint64_t ns;
3214         struct bnxt *bp = dev->data->dev_private;
3215         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3216
3217         if (!ptp)
3218                 return 0;
3219
3220         ns = rte_timespec_to_ns(ts);
3221         /* Set the timecounters to a new value. */
3222         ptp->tc.nsec = ns;
3223
3224         return 0;
3225 }
3226
3227 static int
3228 bnxt_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
3229 {
3230         struct bnxt *bp = dev->data->dev_private;
3231         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3232         uint64_t ns, systime_cycles = 0;
3233         int rc = 0;
3234
3235         if (!ptp)
3236                 return 0;
3237
3238         if (BNXT_CHIP_THOR(bp))
3239                 rc = bnxt_hwrm_port_ts_query(bp, BNXT_PTP_FLAGS_CURRENT_TIME,
3240                                              &systime_cycles);
3241         else
3242                 systime_cycles = bnxt_cc_read(bp);
3243
3244         ns = rte_timecounter_update(&ptp->tc, systime_cycles);
3245         *ts = rte_ns_to_timespec(ns);
3246
3247         return rc;
3248 }
3249 static int
3250 bnxt_timesync_enable(struct rte_eth_dev *dev)
3251 {
3252         struct bnxt *bp = dev->data->dev_private;
3253         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3254         uint32_t shift = 0;
3255         int rc;
3256
3257         if (!ptp)
3258                 return 0;
3259
3260         ptp->rx_filter = 1;
3261         ptp->tx_tstamp_en = 1;
3262         ptp->rxctl = BNXT_PTP_MSG_EVENTS;
3263
3264         rc = bnxt_hwrm_ptp_cfg(bp);
3265         if (rc)
3266                 return rc;
3267
3268         memset(&ptp->tc, 0, sizeof(struct rte_timecounter));
3269         memset(&ptp->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
3270         memset(&ptp->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
3271
3272         ptp->tc.cc_mask = BNXT_CYCLECOUNTER_MASK;
3273         ptp->tc.cc_shift = shift;
3274         ptp->tc.nsec_mask = (1ULL << shift) - 1;
3275
3276         ptp->rx_tstamp_tc.cc_mask = BNXT_CYCLECOUNTER_MASK;
3277         ptp->rx_tstamp_tc.cc_shift = shift;
3278         ptp->rx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
3279
3280         ptp->tx_tstamp_tc.cc_mask = BNXT_CYCLECOUNTER_MASK;
3281         ptp->tx_tstamp_tc.cc_shift = shift;
3282         ptp->tx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
3283
3284         if (!BNXT_CHIP_THOR(bp))
3285                 bnxt_map_ptp_regs(bp);
3286
3287         return 0;
3288 }
3289
3290 static int
3291 bnxt_timesync_disable(struct rte_eth_dev *dev)
3292 {
3293         struct bnxt *bp = dev->data->dev_private;
3294         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3295
3296         if (!ptp)
3297                 return 0;
3298
3299         ptp->rx_filter = 0;
3300         ptp->tx_tstamp_en = 0;
3301         ptp->rxctl = 0;
3302
3303         bnxt_hwrm_ptp_cfg(bp);
3304
3305         if (!BNXT_CHIP_THOR(bp))
3306                 bnxt_unmap_ptp_regs(bp);
3307
3308         return 0;
3309 }
3310
3311 static int
3312 bnxt_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
3313                                  struct timespec *timestamp,
3314                                  uint32_t flags __rte_unused)
3315 {
3316         struct bnxt *bp = dev->data->dev_private;
3317         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3318         uint64_t rx_tstamp_cycles = 0;
3319         uint64_t ns;
3320
3321         if (!ptp)
3322                 return 0;
3323
3324         if (BNXT_CHIP_THOR(bp))
3325                 rx_tstamp_cycles = ptp->rx_timestamp;
3326         else
3327                 bnxt_get_rx_ts(bp, &rx_tstamp_cycles);
3328
3329         ns = rte_timecounter_update(&ptp->rx_tstamp_tc, rx_tstamp_cycles);
3330         *timestamp = rte_ns_to_timespec(ns);
3331         return  0;
3332 }
3333
3334 static int
3335 bnxt_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
3336                                  struct timespec *timestamp)
3337 {
3338         struct bnxt *bp = dev->data->dev_private;
3339         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3340         uint64_t tx_tstamp_cycles = 0;
3341         uint64_t ns;
3342         int rc = 0;
3343
3344         if (!ptp)
3345                 return 0;
3346
3347         if (BNXT_CHIP_THOR(bp))
3348                 rc = bnxt_hwrm_port_ts_query(bp, BNXT_PTP_FLAGS_PATH_TX,
3349                                              &tx_tstamp_cycles);
3350         else
3351                 rc = bnxt_get_tx_ts(bp, &tx_tstamp_cycles);
3352
3353         ns = rte_timecounter_update(&ptp->tx_tstamp_tc, tx_tstamp_cycles);
3354         *timestamp = rte_ns_to_timespec(ns);
3355
3356         return rc;
3357 }
3358
3359 static int
3360 bnxt_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
3361 {
3362         struct bnxt *bp = dev->data->dev_private;
3363         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3364
3365         if (!ptp)
3366                 return 0;
3367
3368         ptp->tc.nsec += delta;
3369
3370         return 0;
3371 }
3372
3373 static int
3374 bnxt_get_eeprom_length_op(struct rte_eth_dev *dev)
3375 {
3376         struct bnxt *bp = dev->data->dev_private;
3377         int rc;
3378         uint32_t dir_entries;
3379         uint32_t entry_length;
3380
3381         rc = is_bnxt_in_error(bp);
3382         if (rc)
3383                 return rc;
3384
3385         PMD_DRV_LOG(INFO, "%04x:%02x:%02x:%02x\n",
3386                 bp->pdev->addr.domain, bp->pdev->addr.bus,
3387                 bp->pdev->addr.devid, bp->pdev->addr.function);
3388
3389         rc = bnxt_hwrm_nvm_get_dir_info(bp, &dir_entries, &entry_length);
3390         if (rc != 0)
3391                 return rc;
3392
3393         return dir_entries * entry_length;
3394 }
3395
3396 static int
3397 bnxt_get_eeprom_op(struct rte_eth_dev *dev,
3398                 struct rte_dev_eeprom_info *in_eeprom)
3399 {
3400         struct bnxt *bp = dev->data->dev_private;
3401         uint32_t index;
3402         uint32_t offset;
3403         int rc;
3404
3405         rc = is_bnxt_in_error(bp);
3406         if (rc)
3407                 return rc;
3408
3409         PMD_DRV_LOG(INFO, "%04x:%02x:%02x:%02x in_eeprom->offset = %d "
3410                 "len = %d\n", bp->pdev->addr.domain,
3411                 bp->pdev->addr.bus, bp->pdev->addr.devid,
3412                 bp->pdev->addr.function, in_eeprom->offset, in_eeprom->length);
3413
3414         if (in_eeprom->offset == 0) /* special offset value to get directory */
3415                 return bnxt_get_nvram_directory(bp, in_eeprom->length,
3416                                                 in_eeprom->data);
3417
3418         index = in_eeprom->offset >> 24;
3419         offset = in_eeprom->offset & 0xffffff;
3420
3421         if (index != 0)
3422                 return bnxt_hwrm_get_nvram_item(bp, index - 1, offset,
3423                                            in_eeprom->length, in_eeprom->data);
3424
3425         return 0;
3426 }
3427
3428 static bool bnxt_dir_type_is_ape_bin_format(uint16_t dir_type)
3429 {
3430         switch (dir_type) {
3431         case BNX_DIR_TYPE_CHIMP_PATCH:
3432         case BNX_DIR_TYPE_BOOTCODE:
3433         case BNX_DIR_TYPE_BOOTCODE_2:
3434         case BNX_DIR_TYPE_APE_FW:
3435         case BNX_DIR_TYPE_APE_PATCH:
3436         case BNX_DIR_TYPE_KONG_FW:
3437         case BNX_DIR_TYPE_KONG_PATCH:
3438         case BNX_DIR_TYPE_BONO_FW:
3439         case BNX_DIR_TYPE_BONO_PATCH:
3440                 /* FALLTHROUGH */
3441                 return true;
3442         }
3443
3444         return false;
3445 }
3446
3447 static bool bnxt_dir_type_is_other_exec_format(uint16_t dir_type)
3448 {
3449         switch (dir_type) {
3450         case BNX_DIR_TYPE_AVS:
3451         case BNX_DIR_TYPE_EXP_ROM_MBA:
3452         case BNX_DIR_TYPE_PCIE:
3453         case BNX_DIR_TYPE_TSCF_UCODE:
3454         case BNX_DIR_TYPE_EXT_PHY:
3455         case BNX_DIR_TYPE_CCM:
3456         case BNX_DIR_TYPE_ISCSI_BOOT:
3457         case BNX_DIR_TYPE_ISCSI_BOOT_IPV6:
3458         case BNX_DIR_TYPE_ISCSI_BOOT_IPV4N6:
3459                 /* FALLTHROUGH */
3460                 return true;
3461         }
3462
3463         return false;
3464 }
3465
3466 static bool bnxt_dir_type_is_executable(uint16_t dir_type)
3467 {
3468         return bnxt_dir_type_is_ape_bin_format(dir_type) ||
3469                 bnxt_dir_type_is_other_exec_format(dir_type);
3470 }
3471
3472 static int
3473 bnxt_set_eeprom_op(struct rte_eth_dev *dev,
3474                 struct rte_dev_eeprom_info *in_eeprom)
3475 {
3476         struct bnxt *bp = dev->data->dev_private;
3477         uint8_t index, dir_op;
3478         uint16_t type, ext, ordinal, attr;
3479         int rc;
3480
3481         rc = is_bnxt_in_error(bp);
3482         if (rc)
3483                 return rc;
3484
3485         PMD_DRV_LOG(INFO, "%04x:%02x:%02x:%02x in_eeprom->offset = %d "
3486                 "len = %d\n", bp->pdev->addr.domain,
3487                 bp->pdev->addr.bus, bp->pdev->addr.devid,
3488                 bp->pdev->addr.function, in_eeprom->offset, in_eeprom->length);
3489
3490         if (!BNXT_PF(bp)) {
3491                 PMD_DRV_LOG(ERR, "NVM write not supported from a VF\n");
3492                 return -EINVAL;
3493         }
3494
3495         type = in_eeprom->magic >> 16;
3496
3497         if (type == 0xffff) { /* special value for directory operations */
3498                 index = in_eeprom->magic & 0xff;
3499                 dir_op = in_eeprom->magic >> 8;
3500                 if (index == 0)
3501                         return -EINVAL;
3502                 switch (dir_op) {
3503                 case 0x0e: /* erase */
3504                         if (in_eeprom->offset != ~in_eeprom->magic)
3505                                 return -EINVAL;
3506                         return bnxt_hwrm_erase_nvram_directory(bp, index - 1);
3507                 default:
3508                         return -EINVAL;
3509                 }
3510         }
3511
3512         /* Create or re-write an NVM item: */
3513         if (bnxt_dir_type_is_executable(type) == true)
3514                 return -EOPNOTSUPP;
3515         ext = in_eeprom->magic & 0xffff;
3516         ordinal = in_eeprom->offset >> 16;
3517         attr = in_eeprom->offset & 0xffff;
3518
3519         return bnxt_hwrm_flash_nvram(bp, type, ordinal, ext, attr,
3520                                      in_eeprom->data, in_eeprom->length);
3521 }
3522
3523 /*
3524  * Initialization
3525  */
3526
3527 static const struct eth_dev_ops bnxt_dev_ops = {
3528         .dev_infos_get = bnxt_dev_info_get_op,
3529         .dev_close = bnxt_dev_close_op,
3530         .dev_configure = bnxt_dev_configure_op,
3531         .dev_start = bnxt_dev_start_op,
3532         .dev_stop = bnxt_dev_stop_op,
3533         .dev_set_link_up = bnxt_dev_set_link_up_op,
3534         .dev_set_link_down = bnxt_dev_set_link_down_op,
3535         .stats_get = bnxt_stats_get_op,
3536         .stats_reset = bnxt_stats_reset_op,
3537         .rx_queue_setup = bnxt_rx_queue_setup_op,
3538         .rx_queue_release = bnxt_rx_queue_release_op,
3539         .tx_queue_setup = bnxt_tx_queue_setup_op,
3540         .tx_queue_release = bnxt_tx_queue_release_op,
3541         .rx_queue_intr_enable = bnxt_rx_queue_intr_enable_op,
3542         .rx_queue_intr_disable = bnxt_rx_queue_intr_disable_op,
3543         .reta_update = bnxt_reta_update_op,
3544         .reta_query = bnxt_reta_query_op,
3545         .rss_hash_update = bnxt_rss_hash_update_op,
3546         .rss_hash_conf_get = bnxt_rss_hash_conf_get_op,
3547         .link_update = bnxt_link_update_op,
3548         .promiscuous_enable = bnxt_promiscuous_enable_op,
3549         .promiscuous_disable = bnxt_promiscuous_disable_op,
3550         .allmulticast_enable = bnxt_allmulticast_enable_op,
3551         .allmulticast_disable = bnxt_allmulticast_disable_op,
3552         .mac_addr_add = bnxt_mac_addr_add_op,
3553         .mac_addr_remove = bnxt_mac_addr_remove_op,
3554         .flow_ctrl_get = bnxt_flow_ctrl_get_op,
3555         .flow_ctrl_set = bnxt_flow_ctrl_set_op,
3556         .udp_tunnel_port_add  = bnxt_udp_tunnel_port_add_op,
3557         .udp_tunnel_port_del  = bnxt_udp_tunnel_port_del_op,
3558         .vlan_filter_set = bnxt_vlan_filter_set_op,
3559         .vlan_offload_set = bnxt_vlan_offload_set_op,
3560         .vlan_pvid_set = bnxt_vlan_pvid_set_op,
3561         .mtu_set = bnxt_mtu_set_op,
3562         .mac_addr_set = bnxt_set_default_mac_addr_op,
3563         .xstats_get = bnxt_dev_xstats_get_op,
3564         .xstats_get_names = bnxt_dev_xstats_get_names_op,
3565         .xstats_reset = bnxt_dev_xstats_reset_op,
3566         .fw_version_get = bnxt_fw_version_get,
3567         .set_mc_addr_list = bnxt_dev_set_mc_addr_list_op,
3568         .rxq_info_get = bnxt_rxq_info_get_op,
3569         .txq_info_get = bnxt_txq_info_get_op,
3570         .dev_led_on = bnxt_dev_led_on_op,
3571         .dev_led_off = bnxt_dev_led_off_op,
3572         .xstats_get_by_id = bnxt_dev_xstats_get_by_id_op,
3573         .xstats_get_names_by_id = bnxt_dev_xstats_get_names_by_id_op,
3574         .rx_queue_count = bnxt_rx_queue_count_op,
3575         .rx_descriptor_status = bnxt_rx_descriptor_status_op,
3576         .tx_descriptor_status = bnxt_tx_descriptor_status_op,
3577         .rx_queue_start = bnxt_rx_queue_start,
3578         .rx_queue_stop = bnxt_rx_queue_stop,
3579         .tx_queue_start = bnxt_tx_queue_start,
3580         .tx_queue_stop = bnxt_tx_queue_stop,
3581         .filter_ctrl = bnxt_filter_ctrl_op,
3582         .dev_supported_ptypes_get = bnxt_dev_supported_ptypes_get_op,
3583         .get_eeprom_length    = bnxt_get_eeprom_length_op,
3584         .get_eeprom           = bnxt_get_eeprom_op,
3585         .set_eeprom           = bnxt_set_eeprom_op,
3586         .timesync_enable      = bnxt_timesync_enable,
3587         .timesync_disable     = bnxt_timesync_disable,
3588         .timesync_read_time   = bnxt_timesync_read_time,
3589         .timesync_write_time   = bnxt_timesync_write_time,
3590         .timesync_adjust_time = bnxt_timesync_adjust_time,
3591         .timesync_read_rx_timestamp = bnxt_timesync_read_rx_timestamp,
3592         .timesync_read_tx_timestamp = bnxt_timesync_read_tx_timestamp,
3593 };
3594
3595 static uint32_t bnxt_map_reset_regs(struct bnxt *bp, uint32_t reg)
3596 {
3597         uint32_t offset;
3598
3599         /* Only pre-map the reset GRC registers using window 3 */
3600         rte_write32(reg & 0xfffff000, (uint8_t *)bp->bar0 +
3601                     BNXT_GRCPF_REG_WINDOW_BASE_OUT + 8);
3602
3603         offset = BNXT_GRCP_WINDOW_3_BASE + (reg & 0xffc);
3604
3605         return offset;
3606 }
3607
3608 int bnxt_map_fw_health_status_regs(struct bnxt *bp)
3609 {
3610         struct bnxt_error_recovery_info *info = bp->recovery_info;
3611         uint32_t reg_base = 0xffffffff;
3612         int i;
3613
3614         /* Only pre-map the monitoring GRC registers using window 2 */
3615         for (i = 0; i < BNXT_FW_STATUS_REG_CNT; i++) {
3616                 uint32_t reg = info->status_regs[i];
3617
3618                 if (BNXT_FW_STATUS_REG_TYPE(reg) != BNXT_FW_STATUS_REG_TYPE_GRC)
3619                         continue;
3620
3621                 if (reg_base == 0xffffffff)
3622                         reg_base = reg & 0xfffff000;
3623                 if ((reg & 0xfffff000) != reg_base)
3624                         return -ERANGE;
3625
3626                 /* Use mask 0xffc as the Lower 2 bits indicates
3627                  * address space location
3628                  */
3629                 info->mapped_status_regs[i] = BNXT_GRCP_WINDOW_2_BASE +
3630                                                 (reg & 0xffc);
3631         }
3632
3633         if (reg_base == 0xffffffff)
3634                 return 0;
3635
3636         rte_write32(reg_base, (uint8_t *)bp->bar0 +
3637                     BNXT_GRCPF_REG_WINDOW_BASE_OUT + 4);
3638
3639         return 0;
3640 }
3641
3642 static void bnxt_write_fw_reset_reg(struct bnxt *bp, uint32_t index)
3643 {
3644         struct bnxt_error_recovery_info *info = bp->recovery_info;
3645         uint32_t delay = info->delay_after_reset[index];
3646         uint32_t val = info->reset_reg_val[index];
3647         uint32_t reg = info->reset_reg[index];
3648         uint32_t type, offset;
3649
3650         type = BNXT_FW_STATUS_REG_TYPE(reg);
3651         offset = BNXT_FW_STATUS_REG_OFF(reg);
3652
3653         switch (type) {
3654         case BNXT_FW_STATUS_REG_TYPE_CFG:
3655                 rte_pci_write_config(bp->pdev, &val, sizeof(val), offset);
3656                 break;
3657         case BNXT_FW_STATUS_REG_TYPE_GRC:
3658                 offset = bnxt_map_reset_regs(bp, offset);
3659                 rte_write32(val, (uint8_t *)bp->bar0 + offset);
3660                 break;
3661         case BNXT_FW_STATUS_REG_TYPE_BAR0:
3662                 rte_write32(val, (uint8_t *)bp->bar0 + offset);
3663                 break;
3664         }
3665         /* wait on a specific interval of time until core reset is complete */
3666         if (delay)
3667                 rte_delay_ms(delay);
3668 }
3669
3670 static void bnxt_dev_cleanup(struct bnxt *bp)
3671 {
3672         bnxt_set_hwrm_link_config(bp, false);
3673         bp->link_info.link_up = 0;
3674         if (bp->dev_stopped == 0)
3675                 bnxt_dev_stop_op(bp->eth_dev);
3676
3677         bnxt_uninit_resources(bp, true);
3678 }
3679
3680 static int bnxt_restore_filters(struct bnxt *bp)
3681 {
3682         struct rte_eth_dev *dev = bp->eth_dev;
3683         int ret = 0;
3684
3685         if (dev->data->all_multicast)
3686                 ret = bnxt_allmulticast_enable_op(dev);
3687         if (dev->data->promiscuous)
3688                 ret = bnxt_promiscuous_enable_op(dev);
3689
3690         /* TODO restore other filters as well */
3691         return ret;
3692 }
3693
3694 static void bnxt_dev_recover(void *arg)
3695 {
3696         struct bnxt *bp = arg;
3697         int timeout = bp->fw_reset_max_msecs;
3698         int rc = 0;
3699
3700         /* Clear Error flag so that device re-init should happen */
3701         bp->flags &= ~BNXT_FLAG_FATAL_ERROR;
3702
3703         do {
3704                 rc = bnxt_hwrm_ver_get(bp);
3705                 if (rc == 0)
3706                         break;
3707                 rte_delay_ms(BNXT_FW_READY_WAIT_INTERVAL);
3708                 timeout -= BNXT_FW_READY_WAIT_INTERVAL;
3709         } while (rc && timeout);
3710
3711         if (rc) {
3712                 PMD_DRV_LOG(ERR, "FW is not Ready after reset\n");
3713                 goto err;
3714         }
3715
3716         rc = bnxt_init_resources(bp, true);
3717         if (rc) {
3718                 PMD_DRV_LOG(ERR,
3719                             "Failed to initialize resources after reset\n");
3720                 goto err;
3721         }
3722         /* clear reset flag as the device is initialized now */
3723         bp->flags &= ~BNXT_FLAG_FW_RESET;
3724
3725         rc = bnxt_dev_start_op(bp->eth_dev);
3726         if (rc) {
3727                 PMD_DRV_LOG(ERR, "Failed to start port after reset\n");
3728                 goto err;
3729         }
3730
3731         rc = bnxt_restore_filters(bp);
3732         if (rc)
3733                 goto err;
3734
3735         PMD_DRV_LOG(INFO, "Recovered from FW reset\n");
3736         return;
3737 err:
3738         bp->flags |= BNXT_FLAG_FATAL_ERROR;
3739         bnxt_uninit_resources(bp, false);
3740         PMD_DRV_LOG(ERR, "Failed to recover from FW reset\n");
3741 }
3742
3743 void bnxt_dev_reset_and_resume(void *arg)
3744 {
3745         struct bnxt *bp = arg;
3746         int rc;
3747
3748         bnxt_dev_cleanup(bp);
3749
3750         bnxt_wait_for_device_shutdown(bp);
3751
3752         rc = rte_eal_alarm_set(US_PER_MS * bp->fw_reset_min_msecs,
3753                                bnxt_dev_recover, (void *)bp);
3754         if (rc)
3755                 PMD_DRV_LOG(ERR, "Error setting recovery alarm");
3756 }
3757
3758 uint32_t bnxt_read_fw_status_reg(struct bnxt *bp, uint32_t index)
3759 {
3760         struct bnxt_error_recovery_info *info = bp->recovery_info;
3761         uint32_t reg = info->status_regs[index];
3762         uint32_t type, offset, val = 0;
3763
3764         type = BNXT_FW_STATUS_REG_TYPE(reg);
3765         offset = BNXT_FW_STATUS_REG_OFF(reg);
3766
3767         switch (type) {
3768         case BNXT_FW_STATUS_REG_TYPE_CFG:
3769                 rte_pci_read_config(bp->pdev, &val, sizeof(val), offset);
3770                 break;
3771         case BNXT_FW_STATUS_REG_TYPE_GRC:
3772                 offset = info->mapped_status_regs[index];
3773                 /* FALLTHROUGH */
3774         case BNXT_FW_STATUS_REG_TYPE_BAR0:
3775                 val = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3776                                        offset));
3777                 break;
3778         }
3779
3780         return val;
3781 }
3782
3783 static int bnxt_fw_reset_all(struct bnxt *bp)
3784 {
3785         struct bnxt_error_recovery_info *info = bp->recovery_info;
3786         uint32_t i;
3787         int rc = 0;
3788
3789         if (info->flags & BNXT_FLAG_ERROR_RECOVERY_HOST) {
3790                 /* Reset through master function driver */
3791                 for (i = 0; i < info->reg_array_cnt; i++)
3792                         bnxt_write_fw_reset_reg(bp, i);
3793                 /* Wait for time specified by FW after triggering reset */
3794                 rte_delay_ms(info->master_func_wait_period_after_reset);
3795         } else if (info->flags & BNXT_FLAG_ERROR_RECOVERY_CO_CPU) {
3796                 /* Reset with the help of Kong processor */
3797                 rc = bnxt_hwrm_fw_reset(bp);
3798                 if (rc)
3799                         PMD_DRV_LOG(ERR, "Failed to reset FW\n");
3800         }
3801
3802         return rc;
3803 }
3804
3805 static void bnxt_fw_reset_cb(void *arg)
3806 {
3807         struct bnxt *bp = arg;
3808         struct bnxt_error_recovery_info *info = bp->recovery_info;
3809         int rc = 0;
3810
3811         /* Only Master function can do FW reset */
3812         if (bnxt_is_master_func(bp) &&
3813             bnxt_is_recovery_enabled(bp)) {
3814                 rc = bnxt_fw_reset_all(bp);
3815                 if (rc) {
3816                         PMD_DRV_LOG(ERR, "Adapter recovery failed\n");
3817                         return;
3818                 }
3819         }
3820
3821         /* if recovery method is ERROR_RECOVERY_CO_CPU, KONG will send
3822          * EXCEPTION_FATAL_ASYNC event to all the functions
3823          * (including MASTER FUNC). After receiving this Async, all the active
3824          * drivers should treat this case as FW initiated recovery
3825          */
3826         if (info->flags & BNXT_FLAG_ERROR_RECOVERY_HOST) {
3827                 bp->fw_reset_min_msecs = BNXT_MIN_FW_READY_TIMEOUT;
3828                 bp->fw_reset_max_msecs = BNXT_MAX_FW_RESET_TIMEOUT;
3829
3830                 /* To recover from error */
3831                 rte_eal_alarm_set(US_PER_MS, bnxt_dev_reset_and_resume,
3832                                   (void *)bp);
3833         }
3834 }
3835
3836 /* Driver should poll FW heartbeat, reset_counter with the frequency
3837  * advertised by FW in HWRM_ERROR_RECOVERY_QCFG.
3838  * When the driver detects heartbeat stop or change in reset_counter,
3839  * it has to trigger a reset to recover from the error condition.
3840  * A “master PF” is the function who will have the privilege to
3841  * initiate the chimp reset. The master PF will be elected by the
3842  * firmware and will be notified through async message.
3843  */
3844 static void bnxt_check_fw_health(void *arg)
3845 {
3846         struct bnxt *bp = arg;
3847         struct bnxt_error_recovery_info *info = bp->recovery_info;
3848         uint32_t val = 0, wait_msec;
3849
3850         if (!info || !bnxt_is_recovery_enabled(bp) ||
3851             is_bnxt_in_error(bp))
3852                 return;
3853
3854         val = bnxt_read_fw_status_reg(bp, BNXT_FW_HEARTBEAT_CNT_REG);
3855         if (val == info->last_heart_beat)
3856                 goto reset;
3857
3858         info->last_heart_beat = val;
3859
3860         val = bnxt_read_fw_status_reg(bp, BNXT_FW_RECOVERY_CNT_REG);
3861         if (val != info->last_reset_counter)
3862                 goto reset;
3863
3864         info->last_reset_counter = val;
3865
3866         rte_eal_alarm_set(US_PER_MS * info->driver_polling_freq,
3867                           bnxt_check_fw_health, (void *)bp);
3868
3869         return;
3870 reset:
3871         /* Stop DMA to/from device */
3872         bp->flags |= BNXT_FLAG_FATAL_ERROR;
3873         bp->flags |= BNXT_FLAG_FW_RESET;
3874
3875         PMD_DRV_LOG(ERR, "Detected FW dead condition\n");
3876
3877         if (bnxt_is_master_func(bp))
3878                 wait_msec = info->master_func_wait_period;
3879         else
3880                 wait_msec = info->normal_func_wait_period;
3881
3882         rte_eal_alarm_set(US_PER_MS * wait_msec,
3883                           bnxt_fw_reset_cb, (void *)bp);
3884 }
3885
3886 void bnxt_schedule_fw_health_check(struct bnxt *bp)
3887 {
3888         uint32_t polling_freq;
3889
3890         if (!bnxt_is_recovery_enabled(bp))
3891                 return;
3892
3893         if (bp->flags & BNXT_FLAG_FW_HEALTH_CHECK_SCHEDULED)
3894                 return;
3895
3896         polling_freq = bp->recovery_info->driver_polling_freq;
3897
3898         rte_eal_alarm_set(US_PER_MS * polling_freq,
3899                           bnxt_check_fw_health, (void *)bp);
3900         bp->flags |= BNXT_FLAG_FW_HEALTH_CHECK_SCHEDULED;
3901 }
3902
3903 static void bnxt_cancel_fw_health_check(struct bnxt *bp)
3904 {
3905         if (!bnxt_is_recovery_enabled(bp))
3906                 return;
3907
3908         rte_eal_alarm_cancel(bnxt_check_fw_health, (void *)bp);
3909         bp->flags &= ~BNXT_FLAG_FW_HEALTH_CHECK_SCHEDULED;
3910 }
3911
3912 static bool bnxt_vf_pciid(uint16_t id)
3913 {
3914         if (id == BROADCOM_DEV_ID_57304_VF ||
3915             id == BROADCOM_DEV_ID_57406_VF ||
3916             id == BROADCOM_DEV_ID_5731X_VF ||
3917             id == BROADCOM_DEV_ID_5741X_VF ||
3918             id == BROADCOM_DEV_ID_57414_VF ||
3919             id == BROADCOM_DEV_ID_STRATUS_NIC_VF1 ||
3920             id == BROADCOM_DEV_ID_STRATUS_NIC_VF2 ||
3921             id == BROADCOM_DEV_ID_58802_VF ||
3922             id == BROADCOM_DEV_ID_57500_VF1 ||
3923             id == BROADCOM_DEV_ID_57500_VF2)
3924                 return true;
3925         return false;
3926 }
3927
3928 bool bnxt_stratus_device(struct bnxt *bp)
3929 {
3930         uint16_t id = bp->pdev->id.device_id;
3931
3932         if (id == BROADCOM_DEV_ID_STRATUS_NIC ||
3933             id == BROADCOM_DEV_ID_STRATUS_NIC_VF1 ||
3934             id == BROADCOM_DEV_ID_STRATUS_NIC_VF2)
3935                 return true;
3936         return false;
3937 }
3938
3939 static int bnxt_init_board(struct rte_eth_dev *eth_dev)
3940 {
3941         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
3942         struct bnxt *bp = eth_dev->data->dev_private;
3943
3944         /* enable device (incl. PCI PM wakeup), and bus-mastering */
3945         bp->bar0 = (void *)pci_dev->mem_resource[0].addr;
3946         bp->doorbell_base = (void *)pci_dev->mem_resource[2].addr;
3947         if (!bp->bar0 || !bp->doorbell_base) {
3948                 PMD_DRV_LOG(ERR, "Unable to access Hardware\n");
3949                 return -ENODEV;
3950         }
3951
3952         bp->eth_dev = eth_dev;
3953         bp->pdev = pci_dev;
3954
3955         return 0;
3956 }
3957
3958 static int bnxt_alloc_ctx_mem_blk(__rte_unused struct bnxt *bp,
3959                                   struct bnxt_ctx_pg_info *ctx_pg,
3960                                   uint32_t mem_size,
3961                                   const char *suffix,
3962                                   uint16_t idx)
3963 {
3964         struct bnxt_ring_mem_info *rmem = &ctx_pg->ring_mem;
3965         const struct rte_memzone *mz = NULL;
3966         char mz_name[RTE_MEMZONE_NAMESIZE];
3967         rte_iova_t mz_phys_addr;
3968         uint64_t valid_bits = 0;
3969         uint32_t sz;
3970         int i;
3971
3972         if (!mem_size)
3973                 return 0;
3974
3975         rmem->nr_pages = RTE_ALIGN_MUL_CEIL(mem_size, BNXT_PAGE_SIZE) /
3976                          BNXT_PAGE_SIZE;
3977         rmem->page_size = BNXT_PAGE_SIZE;
3978         rmem->pg_arr = ctx_pg->ctx_pg_arr;
3979         rmem->dma_arr = ctx_pg->ctx_dma_arr;
3980         rmem->flags = BNXT_RMEM_VALID_PTE_FLAG;
3981
3982         valid_bits = PTU_PTE_VALID;
3983
3984         if (rmem->nr_pages > 1) {
3985                 snprintf(mz_name, RTE_MEMZONE_NAMESIZE,
3986                          "bnxt_ctx_pg_tbl%s_%x_%d",
3987                          suffix, idx, bp->eth_dev->data->port_id);
3988                 mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0;
3989                 mz = rte_memzone_lookup(mz_name);
3990                 if (!mz) {
3991                         mz = rte_memzone_reserve_aligned(mz_name,
3992                                                 rmem->nr_pages * 8,
3993                                                 SOCKET_ID_ANY,
3994                                                 RTE_MEMZONE_2MB |
3995                                                 RTE_MEMZONE_SIZE_HINT_ONLY |
3996                                                 RTE_MEMZONE_IOVA_CONTIG,
3997                                                 BNXT_PAGE_SIZE);
3998                         if (mz == NULL)
3999                                 return -ENOMEM;
4000                 }
4001
4002                 memset(mz->addr, 0, mz->len);
4003                 mz_phys_addr = mz->iova;
4004                 if ((unsigned long)mz->addr == mz_phys_addr) {
4005                         PMD_DRV_LOG(DEBUG,
4006                                     "physical address same as virtual\n");
4007                         PMD_DRV_LOG(DEBUG, "Using rte_mem_virt2iova()\n");
4008                         mz_phys_addr = rte_mem_virt2iova(mz->addr);
4009                         if (mz_phys_addr == RTE_BAD_IOVA) {
4010                                 PMD_DRV_LOG(ERR,
4011                                         "unable to map addr to phys memory\n");
4012                                 return -ENOMEM;
4013                         }
4014                 }
4015                 rte_mem_lock_page(((char *)mz->addr));
4016
4017                 rmem->pg_tbl = mz->addr;
4018                 rmem->pg_tbl_map = mz_phys_addr;
4019                 rmem->pg_tbl_mz = mz;
4020         }
4021
4022         snprintf(mz_name, RTE_MEMZONE_NAMESIZE, "bnxt_ctx_%s_%x_%d",
4023                  suffix, idx, bp->eth_dev->data->port_id);
4024         mz = rte_memzone_lookup(mz_name);
4025         if (!mz) {
4026                 mz = rte_memzone_reserve_aligned(mz_name,
4027                                                  mem_size,
4028                                                  SOCKET_ID_ANY,
4029                                                  RTE_MEMZONE_1GB |
4030                                                  RTE_MEMZONE_SIZE_HINT_ONLY |
4031                                                  RTE_MEMZONE_IOVA_CONTIG,
4032                                                  BNXT_PAGE_SIZE);
4033                 if (mz == NULL)
4034                         return -ENOMEM;
4035         }
4036
4037         memset(mz->addr, 0, mz->len);
4038         mz_phys_addr = mz->iova;
4039         if ((unsigned long)mz->addr == mz_phys_addr) {
4040                 PMD_DRV_LOG(DEBUG,
4041                             "Memzone physical address same as virtual.\n");
4042                 PMD_DRV_LOG(DEBUG, "Using rte_mem_virt2iova()\n");
4043                 for (sz = 0; sz < mem_size; sz += BNXT_PAGE_SIZE)
4044                         rte_mem_lock_page(((char *)mz->addr) + sz);
4045                 mz_phys_addr = rte_mem_virt2iova(mz->addr);
4046                 if (mz_phys_addr == RTE_BAD_IOVA) {
4047                         PMD_DRV_LOG(ERR,
4048                                     "unable to map addr to phys memory\n");
4049                         return -ENOMEM;
4050                 }
4051         }
4052
4053         for (sz = 0, i = 0; sz < mem_size; sz += BNXT_PAGE_SIZE, i++) {
4054                 rte_mem_lock_page(((char *)mz->addr) + sz);
4055                 rmem->pg_arr[i] = ((char *)mz->addr) + sz;
4056                 rmem->dma_arr[i] = mz_phys_addr + sz;
4057
4058                 if (rmem->nr_pages > 1) {
4059                         if (i == rmem->nr_pages - 2 &&
4060                             (rmem->flags & BNXT_RMEM_RING_PTE_FLAG))
4061                                 valid_bits |= PTU_PTE_NEXT_TO_LAST;
4062                         else if (i == rmem->nr_pages - 1 &&
4063                                  (rmem->flags & BNXT_RMEM_RING_PTE_FLAG))
4064                                 valid_bits |= PTU_PTE_LAST;
4065
4066                         rmem->pg_tbl[i] = rte_cpu_to_le_64(rmem->dma_arr[i] |
4067                                                            valid_bits);
4068                 }
4069         }
4070
4071         rmem->mz = mz;
4072         if (rmem->vmem_size)
4073                 rmem->vmem = (void **)mz->addr;
4074         rmem->dma_arr[0] = mz_phys_addr;
4075         return 0;
4076 }
4077
4078 static void bnxt_free_ctx_mem(struct bnxt *bp)
4079 {
4080         int i;
4081
4082         if (!bp->ctx || !(bp->ctx->flags & BNXT_CTX_FLAG_INITED))
4083                 return;
4084
4085         bp->ctx->flags &= ~BNXT_CTX_FLAG_INITED;
4086         rte_memzone_free(bp->ctx->qp_mem.ring_mem.mz);
4087         rte_memzone_free(bp->ctx->srq_mem.ring_mem.mz);
4088         rte_memzone_free(bp->ctx->cq_mem.ring_mem.mz);
4089         rte_memzone_free(bp->ctx->vnic_mem.ring_mem.mz);
4090         rte_memzone_free(bp->ctx->stat_mem.ring_mem.mz);
4091         rte_memzone_free(bp->ctx->qp_mem.ring_mem.pg_tbl_mz);
4092         rte_memzone_free(bp->ctx->srq_mem.ring_mem.pg_tbl_mz);
4093         rte_memzone_free(bp->ctx->cq_mem.ring_mem.pg_tbl_mz);
4094         rte_memzone_free(bp->ctx->vnic_mem.ring_mem.pg_tbl_mz);
4095         rte_memzone_free(bp->ctx->stat_mem.ring_mem.pg_tbl_mz);
4096
4097         for (i = 0; i < BNXT_MAX_Q; i++) {
4098                 if (bp->ctx->tqm_mem[i])
4099                         rte_memzone_free(bp->ctx->tqm_mem[i]->ring_mem.mz);
4100         }
4101
4102         rte_free(bp->ctx);
4103         bp->ctx = NULL;
4104 }
4105
4106 #define bnxt_roundup(x, y)   ((((x) + ((y) - 1)) / (y)) * (y))
4107
4108 #define min_t(type, x, y) ({                    \
4109         type __min1 = (x);                      \
4110         type __min2 = (y);                      \
4111         __min1 < __min2 ? __min1 : __min2; })
4112
4113 #define max_t(type, x, y) ({                    \
4114         type __max1 = (x);                      \
4115         type __max2 = (y);                      \
4116         __max1 > __max2 ? __max1 : __max2; })
4117
4118 #define clamp_t(type, _x, min, max)     min_t(type, max_t(type, _x, min), max)
4119
4120 int bnxt_alloc_ctx_mem(struct bnxt *bp)
4121 {
4122         struct bnxt_ctx_pg_info *ctx_pg;
4123         struct bnxt_ctx_mem_info *ctx;
4124         uint32_t mem_size, ena, entries;
4125         int i, rc;
4126
4127         rc = bnxt_hwrm_func_backing_store_qcaps(bp);
4128         if (rc) {
4129                 PMD_DRV_LOG(ERR, "Query context mem capability failed\n");
4130                 return rc;
4131         }
4132         ctx = bp->ctx;
4133         if (!ctx || (ctx->flags & BNXT_CTX_FLAG_INITED))
4134                 return 0;
4135
4136         ctx_pg = &ctx->qp_mem;
4137         ctx_pg->entries = ctx->qp_min_qp1_entries + ctx->qp_max_l2_entries;
4138         mem_size = ctx->qp_entry_size * ctx_pg->entries;
4139         rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "qp_mem", 0);
4140         if (rc)
4141                 return rc;
4142
4143         ctx_pg = &ctx->srq_mem;
4144         ctx_pg->entries = ctx->srq_max_l2_entries;
4145         mem_size = ctx->srq_entry_size * ctx_pg->entries;
4146         rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "srq_mem", 0);
4147         if (rc)
4148                 return rc;
4149
4150         ctx_pg = &ctx->cq_mem;
4151         ctx_pg->entries = ctx->cq_max_l2_entries;
4152         mem_size = ctx->cq_entry_size * ctx_pg->entries;
4153         rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "cq_mem", 0);
4154         if (rc)
4155                 return rc;
4156
4157         ctx_pg = &ctx->vnic_mem;
4158         ctx_pg->entries = ctx->vnic_max_vnic_entries +
4159                 ctx->vnic_max_ring_table_entries;
4160         mem_size = ctx->vnic_entry_size * ctx_pg->entries;
4161         rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "vnic_mem", 0);
4162         if (rc)
4163                 return rc;
4164
4165         ctx_pg = &ctx->stat_mem;
4166         ctx_pg->entries = ctx->stat_max_entries;
4167         mem_size = ctx->stat_entry_size * ctx_pg->entries;
4168         rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "stat_mem", 0);
4169         if (rc)
4170                 return rc;
4171
4172         entries = ctx->qp_max_l2_entries;
4173         entries = bnxt_roundup(entries, ctx->tqm_entries_multiple);
4174         entries = clamp_t(uint32_t, entries, ctx->tqm_min_entries_per_ring,
4175                           ctx->tqm_max_entries_per_ring);
4176         for (i = 0, ena = 0; i < BNXT_MAX_Q; i++) {
4177                 ctx_pg = ctx->tqm_mem[i];
4178                 /* use min tqm entries for now. */
4179                 ctx_pg->entries = entries;
4180                 mem_size = ctx->tqm_entry_size * ctx_pg->entries;
4181                 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "tqm_mem", i);
4182                 if (rc)
4183                         return rc;
4184                 ena |= HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_SP << i;
4185         }
4186
4187         ena |= FUNC_BACKING_STORE_CFG_INPUT_DFLT_ENABLES;
4188         rc = bnxt_hwrm_func_backing_store_cfg(bp, ena);
4189         if (rc)
4190                 PMD_DRV_LOG(ERR,
4191                             "Failed to configure context mem: rc = %d\n", rc);
4192         else
4193                 ctx->flags |= BNXT_CTX_FLAG_INITED;
4194
4195         return rc;
4196 }
4197
4198 static int bnxt_alloc_stats_mem(struct bnxt *bp)
4199 {
4200         struct rte_pci_device *pci_dev = bp->pdev;
4201         char mz_name[RTE_MEMZONE_NAMESIZE];
4202         const struct rte_memzone *mz = NULL;
4203         uint32_t total_alloc_len;
4204         rte_iova_t mz_phys_addr;
4205
4206         if (pci_dev->id.device_id == BROADCOM_DEV_ID_NS2)
4207                 return 0;
4208
4209         snprintf(mz_name, RTE_MEMZONE_NAMESIZE,
4210                  "bnxt_" PCI_PRI_FMT "-%s", pci_dev->addr.domain,
4211                  pci_dev->addr.bus, pci_dev->addr.devid,
4212                  pci_dev->addr.function, "rx_port_stats");
4213         mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0;
4214         mz = rte_memzone_lookup(mz_name);
4215         total_alloc_len =
4216                 RTE_CACHE_LINE_ROUNDUP(sizeof(struct rx_port_stats) +
4217                                        sizeof(struct rx_port_stats_ext) + 512);
4218         if (!mz) {
4219                 mz = rte_memzone_reserve(mz_name, total_alloc_len,
4220                                          SOCKET_ID_ANY,
4221                                          RTE_MEMZONE_2MB |
4222                                          RTE_MEMZONE_SIZE_HINT_ONLY |
4223                                          RTE_MEMZONE_IOVA_CONTIG);
4224                 if (mz == NULL)
4225                         return -ENOMEM;
4226         }
4227         memset(mz->addr, 0, mz->len);
4228         mz_phys_addr = mz->iova;
4229         if ((unsigned long)mz->addr == mz_phys_addr) {
4230                 PMD_DRV_LOG(DEBUG,
4231                             "Memzone physical address same as virtual.\n");
4232                 PMD_DRV_LOG(DEBUG,
4233                             "Using rte_mem_virt2iova()\n");
4234                 mz_phys_addr = rte_mem_virt2iova(mz->addr);
4235                 if (mz_phys_addr == RTE_BAD_IOVA) {
4236                         PMD_DRV_LOG(ERR,
4237                                     "Can't map address to physical memory\n");
4238                         return -ENOMEM;
4239                 }
4240         }
4241
4242         bp->rx_mem_zone = (const void *)mz;
4243         bp->hw_rx_port_stats = mz->addr;
4244         bp->hw_rx_port_stats_map = mz_phys_addr;
4245
4246         snprintf(mz_name, RTE_MEMZONE_NAMESIZE,
4247                  "bnxt_" PCI_PRI_FMT "-%s", pci_dev->addr.domain,
4248                  pci_dev->addr.bus, pci_dev->addr.devid,
4249                  pci_dev->addr.function, "tx_port_stats");
4250         mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0;
4251         mz = rte_memzone_lookup(mz_name);
4252         total_alloc_len =
4253                 RTE_CACHE_LINE_ROUNDUP(sizeof(struct tx_port_stats) +
4254                                        sizeof(struct tx_port_stats_ext) + 512);
4255         if (!mz) {
4256                 mz = rte_memzone_reserve(mz_name,
4257                                          total_alloc_len,
4258                                          SOCKET_ID_ANY,
4259                                          RTE_MEMZONE_2MB |
4260                                          RTE_MEMZONE_SIZE_HINT_ONLY |
4261                                          RTE_MEMZONE_IOVA_CONTIG);
4262                 if (mz == NULL)
4263                         return -ENOMEM;
4264         }
4265         memset(mz->addr, 0, mz->len);
4266         mz_phys_addr = mz->iova;
4267         if ((unsigned long)mz->addr == mz_phys_addr) {
4268                 PMD_DRV_LOG(DEBUG,
4269                             "Memzone physical address same as virtual\n");
4270                 PMD_DRV_LOG(DEBUG, "Using rte_mem_virt2iova()\n");
4271                 mz_phys_addr = rte_mem_virt2iova(mz->addr);
4272                 if (mz_phys_addr == RTE_BAD_IOVA) {
4273                         PMD_DRV_LOG(ERR,
4274                                     "Can't map address to physical memory\n");
4275                         return -ENOMEM;
4276                 }
4277         }
4278
4279         bp->tx_mem_zone = (const void *)mz;
4280         bp->hw_tx_port_stats = mz->addr;
4281         bp->hw_tx_port_stats_map = mz_phys_addr;
4282         bp->flags |= BNXT_FLAG_PORT_STATS;
4283
4284         /* Display extended statistics if FW supports it */
4285         if (bp->hwrm_spec_code < HWRM_SPEC_CODE_1_8_4 ||
4286             bp->hwrm_spec_code == HWRM_SPEC_CODE_1_9_0 ||
4287             !(bp->flags & BNXT_FLAG_EXT_STATS_SUPPORTED))
4288                 return 0;
4289
4290         bp->hw_rx_port_stats_ext = (void *)
4291                 ((uint8_t *)bp->hw_rx_port_stats +
4292                  sizeof(struct rx_port_stats));
4293         bp->hw_rx_port_stats_ext_map = bp->hw_rx_port_stats_map +
4294                 sizeof(struct rx_port_stats);
4295         bp->flags |= BNXT_FLAG_EXT_RX_PORT_STATS;
4296
4297         if (bp->hwrm_spec_code < HWRM_SPEC_CODE_1_9_2 ||
4298             bp->flags & BNXT_FLAG_EXT_STATS_SUPPORTED) {
4299                 bp->hw_tx_port_stats_ext = (void *)
4300                         ((uint8_t *)bp->hw_tx_port_stats +
4301                          sizeof(struct tx_port_stats));
4302                 bp->hw_tx_port_stats_ext_map =
4303                         bp->hw_tx_port_stats_map +
4304                         sizeof(struct tx_port_stats);
4305                 bp->flags |= BNXT_FLAG_EXT_TX_PORT_STATS;
4306         }
4307
4308         return 0;
4309 }
4310
4311 static int bnxt_setup_mac_addr(struct rte_eth_dev *eth_dev)
4312 {
4313         struct bnxt *bp = eth_dev->data->dev_private;
4314         int rc = 0;
4315
4316         eth_dev->data->mac_addrs = rte_zmalloc("bnxt_mac_addr_tbl",
4317                                                RTE_ETHER_ADDR_LEN *
4318                                                bp->max_l2_ctx,
4319                                                0);
4320         if (eth_dev->data->mac_addrs == NULL) {
4321                 PMD_DRV_LOG(ERR, "Failed to alloc MAC addr tbl\n");
4322                 return -ENOMEM;
4323         }
4324
4325         if (bnxt_check_zero_bytes(bp->dflt_mac_addr, RTE_ETHER_ADDR_LEN)) {
4326                 if (BNXT_PF(bp))
4327                         return -EINVAL;
4328
4329                 /* Generate a random MAC address, if none was assigned by PF */
4330                 PMD_DRV_LOG(INFO, "VF MAC address not assigned by Host PF\n");
4331                 bnxt_eth_hw_addr_random(bp->mac_addr);
4332                 PMD_DRV_LOG(INFO,
4333                             "Assign random MAC:%02X:%02X:%02X:%02X:%02X:%02X\n",
4334                             bp->mac_addr[0], bp->mac_addr[1], bp->mac_addr[2],
4335                             bp->mac_addr[3], bp->mac_addr[4], bp->mac_addr[5]);
4336
4337                 rc = bnxt_hwrm_set_mac(bp);
4338                 if (!rc)
4339                         memcpy(&bp->eth_dev->data->mac_addrs[0], bp->mac_addr,
4340                                RTE_ETHER_ADDR_LEN);
4341                 return rc;
4342         }
4343
4344         /* Copy the permanent MAC from the FUNC_QCAPS response */
4345         memcpy(bp->mac_addr, bp->dflt_mac_addr, RTE_ETHER_ADDR_LEN);
4346         memcpy(&eth_dev->data->mac_addrs[0], bp->mac_addr, RTE_ETHER_ADDR_LEN);
4347
4348         return rc;
4349 }
4350
4351 static int bnxt_restore_dflt_mac(struct bnxt *bp)
4352 {
4353         int rc = 0;
4354
4355         /* MAC is already configured in FW */
4356         if (!bnxt_check_zero_bytes(bp->dflt_mac_addr, RTE_ETHER_ADDR_LEN))
4357                 return 0;
4358
4359         /* Restore the old MAC configured */
4360         rc = bnxt_hwrm_set_mac(bp);
4361         if (rc)
4362                 PMD_DRV_LOG(ERR, "Failed to restore MAC address\n");
4363
4364         return rc;
4365 }
4366
4367 static void bnxt_config_vf_req_fwd(struct bnxt *bp)
4368 {
4369         if (!BNXT_PF(bp))
4370                 return;
4371
4372 #define ALLOW_FUNC(x)   \
4373         { \
4374                 uint32_t arg = (x); \
4375                 bp->pf.vf_req_fwd[((arg) >> 5)] &= \
4376                 ~rte_cpu_to_le_32(1 << ((arg) & 0x1f)); \
4377         }
4378
4379         /* Forward all requests if firmware is new enough */
4380         if (((bp->fw_ver >= ((20 << 24) | (6 << 16) | (100 << 8))) &&
4381              (bp->fw_ver < ((20 << 24) | (7 << 16)))) ||
4382             ((bp->fw_ver >= ((20 << 24) | (8 << 16))))) {
4383                 memset(bp->pf.vf_req_fwd, 0xff, sizeof(bp->pf.vf_req_fwd));
4384         } else {
4385                 PMD_DRV_LOG(WARNING,
4386                             "Firmware too old for VF mailbox functionality\n");
4387                 memset(bp->pf.vf_req_fwd, 0, sizeof(bp->pf.vf_req_fwd));
4388         }
4389
4390         /*
4391          * The following are used for driver cleanup. If we disallow these,
4392          * VF drivers can't clean up cleanly.
4393          */
4394         ALLOW_FUNC(HWRM_FUNC_DRV_UNRGTR);
4395         ALLOW_FUNC(HWRM_VNIC_FREE);
4396         ALLOW_FUNC(HWRM_RING_FREE);
4397         ALLOW_FUNC(HWRM_RING_GRP_FREE);
4398         ALLOW_FUNC(HWRM_VNIC_RSS_COS_LB_CTX_FREE);
4399         ALLOW_FUNC(HWRM_CFA_L2_FILTER_FREE);
4400         ALLOW_FUNC(HWRM_STAT_CTX_FREE);
4401         ALLOW_FUNC(HWRM_PORT_PHY_QCFG);
4402         ALLOW_FUNC(HWRM_VNIC_TPA_CFG);
4403 }
4404
4405 static int bnxt_init_fw(struct bnxt *bp)
4406 {
4407         uint16_t mtu;
4408         int rc = 0;
4409
4410         rc = bnxt_hwrm_ver_get(bp);
4411         if (rc)
4412                 return rc;
4413
4414         rc = bnxt_hwrm_func_reset(bp);
4415         if (rc)
4416                 return -EIO;
4417
4418         rc = bnxt_hwrm_queue_qportcfg(bp);
4419         if (rc)
4420                 return rc;
4421
4422         /* Get the MAX capabilities for this function */
4423         rc = bnxt_hwrm_func_qcaps(bp);
4424         if (rc)
4425                 return rc;
4426
4427         rc = bnxt_hwrm_func_qcfg(bp, &mtu);
4428         if (rc)
4429                 return rc;
4430
4431         /* Get the adapter error recovery support info */
4432         rc = bnxt_hwrm_error_recovery_qcfg(bp);
4433         if (rc)
4434                 bp->flags &= ~BNXT_FLAG_FW_CAP_ERROR_RECOVERY;
4435
4436         if (mtu >= RTE_ETHER_MIN_MTU && mtu <= BNXT_MAX_MTU &&
4437             mtu != bp->eth_dev->data->mtu)
4438                 bp->eth_dev->data->mtu = mtu;
4439
4440         bnxt_hwrm_port_led_qcaps(bp);
4441
4442         return 0;
4443 }
4444
4445 static int bnxt_init_resources(struct bnxt *bp, bool reconfig_dev)
4446 {
4447         int rc;
4448
4449         rc = bnxt_init_fw(bp);
4450         if (rc)
4451                 return rc;
4452
4453         if (!reconfig_dev) {
4454                 rc = bnxt_setup_mac_addr(bp->eth_dev);
4455                 if (rc)
4456                         return rc;
4457         } else {
4458                 rc = bnxt_restore_dflt_mac(bp);
4459                 if (rc)
4460                         return rc;
4461         }
4462
4463         bnxt_config_vf_req_fwd(bp);
4464
4465         rc = bnxt_hwrm_func_driver_register(bp);
4466         if (rc) {
4467                 PMD_DRV_LOG(ERR, "Failed to register driver");
4468                 return -EBUSY;
4469         }
4470
4471         if (BNXT_PF(bp)) {
4472                 if (bp->pdev->max_vfs) {
4473                         rc = bnxt_hwrm_allocate_vfs(bp, bp->pdev->max_vfs);
4474                         if (rc) {
4475                                 PMD_DRV_LOG(ERR, "Failed to allocate VFs\n");
4476                                 return rc;
4477                         }
4478                 } else {
4479                         rc = bnxt_hwrm_allocate_pf_only(bp);
4480                         if (rc) {
4481                                 PMD_DRV_LOG(ERR,
4482                                             "Failed to allocate PF resources");
4483                                 return rc;
4484                         }
4485                 }
4486         }
4487
4488         rc = bnxt_alloc_mem(bp, reconfig_dev);
4489         if (rc)
4490                 return rc;
4491
4492         rc = bnxt_setup_int(bp);
4493         if (rc)
4494                 return rc;
4495
4496         bnxt_init_nic(bp);
4497
4498         rc = bnxt_request_int(bp);
4499         if (rc)
4500                 return rc;
4501
4502         return 0;
4503 }
4504
4505 static int
4506 bnxt_dev_init(struct rte_eth_dev *eth_dev)
4507 {
4508         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
4509         static int version_printed;
4510         struct bnxt *bp;
4511         int rc;
4512
4513         if (version_printed++ == 0)
4514                 PMD_DRV_LOG(INFO, "%s\n", bnxt_version);
4515
4516         rte_eth_copy_pci_info(eth_dev, pci_dev);
4517
4518         bp = eth_dev->data->dev_private;
4519
4520         bp->dev_stopped = 1;
4521
4522         eth_dev->dev_ops = &bnxt_dev_ops;
4523         eth_dev->rx_pkt_burst = &bnxt_recv_pkts;
4524         eth_dev->tx_pkt_burst = &bnxt_xmit_pkts;
4525
4526         /*
4527          * For secondary processes, we don't initialise any further
4528          * as primary has already done this work.
4529          */
4530         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
4531                 return 0;
4532
4533         if (bnxt_vf_pciid(pci_dev->id.device_id))
4534                 bp->flags |= BNXT_FLAG_VF;
4535
4536         if (pci_dev->id.device_id == BROADCOM_DEV_ID_57508 ||
4537             pci_dev->id.device_id == BROADCOM_DEV_ID_57504 ||
4538             pci_dev->id.device_id == BROADCOM_DEV_ID_57502 ||
4539             pci_dev->id.device_id == BROADCOM_DEV_ID_57500_VF1 ||
4540             pci_dev->id.device_id == BROADCOM_DEV_ID_57500_VF2)
4541                 bp->flags |= BNXT_FLAG_THOR_CHIP;
4542
4543         if (pci_dev->id.device_id == BROADCOM_DEV_ID_58802 ||
4544             pci_dev->id.device_id == BROADCOM_DEV_ID_58804 ||
4545             pci_dev->id.device_id == BROADCOM_DEV_ID_58808 ||
4546             pci_dev->id.device_id == BROADCOM_DEV_ID_58802_VF)
4547                 bp->flags |= BNXT_FLAG_STINGRAY;
4548
4549         rc = bnxt_init_board(eth_dev);
4550         if (rc) {
4551                 PMD_DRV_LOG(ERR,
4552                             "Failed to initialize board rc: %x\n", rc);
4553                 return rc;
4554         }
4555
4556         rc = bnxt_alloc_hwrm_resources(bp);
4557         if (rc) {
4558                 PMD_DRV_LOG(ERR,
4559                             "Failed to allocate hwrm resource rc: %x\n", rc);
4560                 goto error_free;
4561         }
4562         rc = bnxt_init_resources(bp, false);
4563         if (rc)
4564                 goto error_free;
4565
4566         rc = bnxt_alloc_stats_mem(bp);
4567         if (rc)
4568                 goto error_free;
4569
4570         PMD_DRV_LOG(INFO,
4571                     DRV_MODULE_NAME "found at mem %" PRIX64 ", node addr %pM\n",
4572                     pci_dev->mem_resource[0].phys_addr,
4573                     pci_dev->mem_resource[0].addr);
4574
4575         return 0;
4576
4577 error_free:
4578         bnxt_dev_uninit(eth_dev);
4579         return rc;
4580 }
4581
4582 static int
4583 bnxt_uninit_resources(struct bnxt *bp, bool reconfig_dev)
4584 {
4585         int rc;
4586
4587         bnxt_disable_int(bp);
4588         bnxt_free_int(bp);
4589         bnxt_free_mem(bp, reconfig_dev);
4590         bnxt_hwrm_func_buf_unrgtr(bp);
4591         rc = bnxt_hwrm_func_driver_unregister(bp, 0);
4592         bp->flags &= ~BNXT_FLAG_REGISTERED;
4593         bnxt_free_ctx_mem(bp);
4594         if (!reconfig_dev) {
4595                 bnxt_free_hwrm_resources(bp);
4596
4597                 if (bp->recovery_info != NULL) {
4598                         rte_free(bp->recovery_info);
4599                         bp->recovery_info = NULL;
4600                 }
4601         }
4602
4603         rte_free(bp->ptp_cfg);
4604         bp->ptp_cfg = NULL;
4605         return rc;
4606 }
4607
4608 static int
4609 bnxt_dev_uninit(struct rte_eth_dev *eth_dev)
4610 {
4611         struct bnxt *bp = eth_dev->data->dev_private;
4612         int rc;
4613
4614         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
4615                 return -EPERM;
4616
4617         PMD_DRV_LOG(DEBUG, "Calling Device uninit\n");
4618
4619         rc = bnxt_uninit_resources(bp, false);
4620
4621         if (bp->grp_info != NULL) {
4622                 rte_free(bp->grp_info);
4623                 bp->grp_info = NULL;
4624         }
4625
4626         if (bp->tx_mem_zone) {
4627                 rte_memzone_free((const struct rte_memzone *)bp->tx_mem_zone);
4628                 bp->tx_mem_zone = NULL;
4629         }
4630
4631         if (bp->rx_mem_zone) {
4632                 rte_memzone_free((const struct rte_memzone *)bp->rx_mem_zone);
4633                 bp->rx_mem_zone = NULL;
4634         }
4635
4636         if (bp->dev_stopped == 0)
4637                 bnxt_dev_close_op(eth_dev);
4638         if (bp->pf.vf_info)
4639                 rte_free(bp->pf.vf_info);
4640         eth_dev->dev_ops = NULL;
4641         eth_dev->rx_pkt_burst = NULL;
4642         eth_dev->tx_pkt_burst = NULL;
4643
4644         return rc;
4645 }
4646
4647 static int bnxt_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
4648         struct rte_pci_device *pci_dev)
4649 {
4650         return rte_eth_dev_pci_generic_probe(pci_dev, sizeof(struct bnxt),
4651                 bnxt_dev_init);
4652 }
4653
4654 static int bnxt_pci_remove(struct rte_pci_device *pci_dev)
4655 {
4656         if (rte_eal_process_type() == RTE_PROC_PRIMARY)
4657                 return rte_eth_dev_pci_generic_remove(pci_dev,
4658                                 bnxt_dev_uninit);
4659         else
4660                 return rte_eth_dev_pci_generic_remove(pci_dev, NULL);
4661 }
4662
4663 static struct rte_pci_driver bnxt_rte_pmd = {
4664         .id_table = bnxt_pci_id_map,
4665         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
4666         .probe = bnxt_pci_probe,
4667         .remove = bnxt_pci_remove,
4668 };
4669
4670 static bool
4671 is_device_supported(struct rte_eth_dev *dev, struct rte_pci_driver *drv)
4672 {
4673         if (strcmp(dev->device->driver->name, drv->driver.name))
4674                 return false;
4675
4676         return true;
4677 }
4678
4679 bool is_bnxt_supported(struct rte_eth_dev *dev)
4680 {
4681         return is_device_supported(dev, &bnxt_rte_pmd);
4682 }
4683
4684 RTE_INIT(bnxt_init_log)
4685 {
4686         bnxt_logtype_driver = rte_log_register("pmd.net.bnxt.driver");
4687         if (bnxt_logtype_driver >= 0)
4688                 rte_log_set_level(bnxt_logtype_driver, RTE_LOG_NOTICE);
4689 }
4690
4691 RTE_PMD_REGISTER_PCI(net_bnxt, bnxt_rte_pmd);
4692 RTE_PMD_REGISTER_PCI_TABLE(net_bnxt, bnxt_pci_id_map);
4693 RTE_PMD_REGISTER_KMOD_DEP(net_bnxt, "* igb_uio | uio_pci_generic | vfio-pci");