drivers/net/bnxt/bnxt_ethdev.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2014-2021 Broadcom
   3  * All rights reserved.
   4  */
   5
   6 #include <inttypes.h>
   7 #include <stdbool.h>
   8
   9 #include <rte_dev.h>
  10 #include <ethdev_driver.h>
  11 #include <ethdev_pci.h>
  12 #include <rte_malloc.h>
  13 #include <rte_cycles.h>
  14 #include <rte_alarm.h>
  15 #include <rte_kvargs.h>
  16 #include <rte_vect.h>
  17
  18 #include "bnxt.h"
  19 #include "bnxt_filter.h"
  20 #include "bnxt_hwrm.h"
  21 #include "bnxt_irq.h"
  22 #include "bnxt_reps.h"
  23 #include "bnxt_ring.h"
  24 #include "bnxt_rxq.h"
  25 #include "bnxt_rxr.h"
  26 #include "bnxt_stats.h"
  27 #include "bnxt_txq.h"
  28 #include "bnxt_txr.h"
  29 #include "bnxt_vnic.h"
  30 #include "hsi_struct_def_dpdk.h"
  31 #include "bnxt_nvm_defs.h"
  32 #include "bnxt_tf_common.h"
  33 #include "ulp_flow_db.h"
  34 #include "rte_pmd_bnxt.h"
  35
  36 #define DRV_MODULE_NAME         "bnxt"
  37 static const char bnxt_version[] =
  38         "Broadcom NetXtreme driver " DRV_MODULE_NAME;
  39
  40 /*
  41  * The set of PCI devices this driver supports
  42  */
  43 static const struct rte_pci_id bnxt_pci_id_map[] = {
  44         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM,
  45                          BROADCOM_DEV_ID_STRATUS_NIC_VF1) },
  46         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM,
  47                          BROADCOM_DEV_ID_STRATUS_NIC_VF2) },
  48         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_STRATUS_NIC) },
  49         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414_VF) },
  50         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57304_VF) },
  51         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_NS2) },
  52         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57406_VF) },
  53         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57407_MF) },
  54         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_5741X_VF) },
  55         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_5731X_VF) },
  56         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_MF) },
  57         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57412) },
  58         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414) },
  59         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_RJ45) },
  60         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_RJ45) },
  61         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57412_MF) },
  62         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57317_RJ45) },
  63         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_SFP) },
  64         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_SFP) },
  65         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57317_SFP) },
  66         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414_MF) },
  67         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_MF) },
  68         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58802) },
  69         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58804) },
  70         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58808) },
  71         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58802_VF) },
  72         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57508) },
  73         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57504) },
  74         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57502) },
  75         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57500_VF1) },
  76         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57500_VF2) },
  77         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57508_MF1) },
  78         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57504_MF1) },
  79         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57502_MF1) },
  80         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57508_MF2) },
  81         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57504_MF2) },
  82         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57502_MF2) },
  83         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58812) },
  84         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58814) },
  85         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58818) },
  86         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58818_VF) },
  87         { .vendor_id = 0, /* sentinel */ },
  88 };
  89
  90 #define BNXT_DEVARG_TRUFLOW     "host-based-truflow"
  91 #define BNXT_DEVARG_FLOW_XSTAT  "flow-xstat"
  92 #define BNXT_DEVARG_MAX_NUM_KFLOWS  "max-num-kflows"
  93 #define BNXT_DEVARG_REPRESENTOR "representor"
  94 #define BNXT_DEVARG_REP_BASED_PF  "rep-based-pf"
  95 #define BNXT_DEVARG_REP_IS_PF  "rep-is-pf"
  96 #define BNXT_DEVARG_REP_Q_R2F  "rep-q-r2f"
  97 #define BNXT_DEVARG_REP_Q_F2R  "rep-q-f2r"
  98 #define BNXT_DEVARG_REP_FC_R2F  "rep-fc-r2f"
  99 #define BNXT_DEVARG_REP_FC_F2R  "rep-fc-f2r"
 100
 101 static const char *const bnxt_dev_args[] = {
 102         BNXT_DEVARG_REPRESENTOR,
 103         BNXT_DEVARG_TRUFLOW,
 104         BNXT_DEVARG_FLOW_XSTAT,
 105         BNXT_DEVARG_MAX_NUM_KFLOWS,
 106         BNXT_DEVARG_REP_BASED_PF,
 107         BNXT_DEVARG_REP_IS_PF,
 108         BNXT_DEVARG_REP_Q_R2F,
 109         BNXT_DEVARG_REP_Q_F2R,
 110         BNXT_DEVARG_REP_FC_R2F,
 111         BNXT_DEVARG_REP_FC_F2R,
 112         NULL
 113 };
 114
 115 /*
 116  * truflow == false to disable the feature
 117  * truflow == true to enable the feature
 118  */
 119 #define BNXT_DEVARG_TRUFLOW_INVALID(truflow)    ((truflow) > 1)
 120
 121 /*
 122  * flow_xstat == false to disable the feature
 123  * flow_xstat == true to enable the feature
 124  */
 125 #define BNXT_DEVARG_FLOW_XSTAT_INVALID(flow_xstat)      ((flow_xstat) > 1)
 126
 127 /*
 128  * rep_is_pf == false to indicate VF representor
 129  * rep_is_pf == true to indicate PF representor
 130  */
 131 #define BNXT_DEVARG_REP_IS_PF_INVALID(rep_is_pf)        ((rep_is_pf) > 1)
 132
 133 /*
 134  * rep_based_pf == Physical index of the PF
 135  */
 136 #define BNXT_DEVARG_REP_BASED_PF_INVALID(rep_based_pf)  ((rep_based_pf) > 15)
 137 /*
 138  * rep_q_r2f == Logical COS Queue index for the rep to endpoint direction
 139  */
 140 #define BNXT_DEVARG_REP_Q_R2F_INVALID(rep_q_r2f)        ((rep_q_r2f) > 3)
 141
 142 /*
 143  * rep_q_f2r == Logical COS Queue index for the endpoint to rep direction
 144  */
 145 #define BNXT_DEVARG_REP_Q_F2R_INVALID(rep_q_f2r)        ((rep_q_f2r) > 3)
 146
 147 /*
 148  * rep_fc_r2f == Flow control for the representor to endpoint direction
 149  */
 150 #define BNXT_DEVARG_REP_FC_R2F_INVALID(rep_fc_r2f)      ((rep_fc_r2f) > 1)
 151
 152 /*
 153  * rep_fc_f2r == Flow control for the endpoint to representor direction
 154  */
 155 #define BNXT_DEVARG_REP_FC_F2R_INVALID(rep_fc_f2r)      ((rep_fc_f2r) > 1)
 156
 157 int bnxt_cfa_code_dynfield_offset = -1;
 158
 159 /*
 160  * max_num_kflows must be >= 32
 161  * and must be a power-of-2 supported value
 162  * return: 1 -> invalid
 163  *         0 -> valid
 164  */
 165 static int bnxt_devarg_max_num_kflow_invalid(uint16_t max_num_kflows)
 166 {
 167         if (max_num_kflows < 32 || !rte_is_power_of_2(max_num_kflows))
 168                 return 1;
 169         return 0;
 170 }
 171
 172 static int bnxt_vlan_offload_set_op(struct rte_eth_dev *dev, int mask);
 173 static int bnxt_dev_uninit(struct rte_eth_dev *eth_dev);
 174 static int bnxt_init_resources(struct bnxt *bp, bool reconfig_dev);
 175 static int bnxt_uninit_resources(struct bnxt *bp, bool reconfig_dev);
 176 static void bnxt_cancel_fw_health_check(struct bnxt *bp);
 177 static int bnxt_restore_vlan_filters(struct bnxt *bp);
 178 static void bnxt_dev_recover(void *arg);
 179 static void bnxt_free_error_recovery_info(struct bnxt *bp);
 180 static void bnxt_free_rep_info(struct bnxt *bp);
 181
 182 int is_bnxt_in_error(struct bnxt *bp)
 183 {
 184         if (bp->flags & BNXT_FLAG_FATAL_ERROR)
 185                 return -EIO;
 186         if (bp->flags & BNXT_FLAG_FW_RESET)
 187                 return -EBUSY;
 188
 189         return 0;
 190 }
 191
 192 /***********************/
 193
 194 /*
 195  * High level utility functions
 196  */
 197
 198 static uint16_t bnxt_rss_ctxts(const struct bnxt *bp)
 199 {
 200         unsigned int num_rss_rings = RTE_MIN(bp->rx_nr_rings,
 201                                              BNXT_RSS_TBL_SIZE_P5);
 202
 203         if (!BNXT_CHIP_P5(bp))
 204                 return 1;
 205
 206         return RTE_ALIGN_MUL_CEIL(num_rss_rings,
 207                                   BNXT_RSS_ENTRIES_PER_CTX_P5) /
 208                                   BNXT_RSS_ENTRIES_PER_CTX_P5;
 209 }
 210
 211 uint16_t bnxt_rss_hash_tbl_size(const struct bnxt *bp)
 212 {
 213         if (!BNXT_CHIP_P5(bp))
 214                 return HW_HASH_INDEX_SIZE;
 215
 216         return bnxt_rss_ctxts(bp) * BNXT_RSS_ENTRIES_PER_CTX_P5;
 217 }
 218
 219 static void bnxt_free_parent_info(struct bnxt *bp)
 220 {
 221         rte_free(bp->parent);
 222 }
 223
 224 static void bnxt_free_pf_info(struct bnxt *bp)
 225 {
 226         rte_free(bp->pf);
 227 }
 228
 229 static void bnxt_free_link_info(struct bnxt *bp)
 230 {
 231         rte_free(bp->link_info);
 232 }
 233
 234 static void bnxt_free_leds_info(struct bnxt *bp)
 235 {
 236         if (BNXT_VF(bp))
 237                 return;
 238
 239         rte_free(bp->leds);
 240         bp->leds = NULL;
 241 }
 242
 243 static void bnxt_free_flow_stats_info(struct bnxt *bp)
 244 {
 245         rte_free(bp->flow_stat);
 246         bp->flow_stat = NULL;
 247 }
 248
 249 static void bnxt_free_cos_queues(struct bnxt *bp)
 250 {
 251         rte_free(bp->rx_cos_queue);
 252         rte_free(bp->tx_cos_queue);
 253 }
 254
 255 static void bnxt_free_mem(struct bnxt *bp, bool reconfig)
 256 {
 257         bnxt_free_filter_mem(bp);
 258         bnxt_free_vnic_attributes(bp);
 259         bnxt_free_vnic_mem(bp);
 260
 261         /* tx/rx rings are configured as part of *_queue_setup callbacks.
 262          * If the number of rings change across fw update,
 263          * we don't have much choice except to warn the user.
 264          */
 265         if (!reconfig) {
 266                 bnxt_free_stats(bp);
 267                 bnxt_free_tx_rings(bp);
 268                 bnxt_free_rx_rings(bp);
 269         }
 270         bnxt_free_async_cp_ring(bp);
 271         bnxt_free_rxtx_nq_ring(bp);
 272
 273         rte_free(bp->grp_info);
 274         bp->grp_info = NULL;
 275 }
 276
 277 static int bnxt_alloc_parent_info(struct bnxt *bp)
 278 {
 279         bp->parent = rte_zmalloc("bnxt_parent_info",
 280                                  sizeof(struct bnxt_parent_info), 0);
 281         if (bp->parent == NULL)
 282                 return -ENOMEM;
 283
 284         return 0;
 285 }
 286
 287 static int bnxt_alloc_pf_info(struct bnxt *bp)
 288 {
 289         bp->pf = rte_zmalloc("bnxt_pf_info", sizeof(struct bnxt_pf_info), 0);
 290         if (bp->pf == NULL)
 291                 return -ENOMEM;
 292
 293         return 0;
 294 }
 295
 296 static int bnxt_alloc_link_info(struct bnxt *bp)
 297 {
 298         bp->link_info =
 299                 rte_zmalloc("bnxt_link_info", sizeof(struct bnxt_link_info), 0);
 300         if (bp->link_info == NULL)
 301                 return -ENOMEM;
 302
 303         return 0;
 304 }
 305
 306 static int bnxt_alloc_leds_info(struct bnxt *bp)
 307 {
 308         if (BNXT_VF(bp))
 309                 return 0;
 310
 311         bp->leds = rte_zmalloc("bnxt_leds",
 312                                BNXT_MAX_LED * sizeof(struct bnxt_led_info),
 313                                0);
 314         if (bp->leds == NULL)
 315                 return -ENOMEM;
 316
 317         return 0;
 318 }
 319
 320 static int bnxt_alloc_cos_queues(struct bnxt *bp)
 321 {
 322         bp->rx_cos_queue =
 323                 rte_zmalloc("bnxt_rx_cosq",
 324                             BNXT_COS_QUEUE_COUNT *
 325                             sizeof(struct bnxt_cos_queue_info),
 326                             0);
 327         if (bp->rx_cos_queue == NULL)
 328                 return -ENOMEM;
 329
 330         bp->tx_cos_queue =
 331                 rte_zmalloc("bnxt_tx_cosq",
 332                             BNXT_COS_QUEUE_COUNT *
 333                             sizeof(struct bnxt_cos_queue_info),
 334                             0);
 335         if (bp->tx_cos_queue == NULL)
 336                 return -ENOMEM;
 337
 338         return 0;
 339 }
 340
 341 static int bnxt_alloc_flow_stats_info(struct bnxt *bp)
 342 {
 343         bp->flow_stat = rte_zmalloc("bnxt_flow_xstat",
 344                                     sizeof(struct bnxt_flow_stat_info), 0);
 345         if (bp->flow_stat == NULL)
 346                 return -ENOMEM;
 347
 348         return 0;
 349 }
 350
 351 static int bnxt_alloc_mem(struct bnxt *bp, bool reconfig)
 352 {
 353         int rc;
 354
 355         rc = bnxt_alloc_ring_grps(bp);
 356         if (rc)
 357                 goto alloc_mem_err;
 358
 359         rc = bnxt_alloc_async_ring_struct(bp);
 360         if (rc)
 361                 goto alloc_mem_err;
 362
 363         rc = bnxt_alloc_vnic_mem(bp);
 364         if (rc)
 365                 goto alloc_mem_err;
 366
 367         rc = bnxt_alloc_vnic_attributes(bp);
 368         if (rc)
 369                 goto alloc_mem_err;
 370
 371         rc = bnxt_alloc_filter_mem(bp);
 372         if (rc)
 373                 goto alloc_mem_err;
 374
 375         rc = bnxt_alloc_async_cp_ring(bp);
 376         if (rc)
 377                 goto alloc_mem_err;
 378
 379         rc = bnxt_alloc_rxtx_nq_ring(bp);
 380         if (rc)
 381                 goto alloc_mem_err;
 382
 383         if (BNXT_FLOW_XSTATS_EN(bp)) {
 384                 rc = bnxt_alloc_flow_stats_info(bp);
 385                 if (rc)
 386                         goto alloc_mem_err;
 387         }
 388
 389         return 0;
 390
 391 alloc_mem_err:
 392         bnxt_free_mem(bp, reconfig);
 393         return rc;
 394 }
 395
 396 static int bnxt_setup_one_vnic(struct bnxt *bp, uint16_t vnic_id)
 397 {
 398         struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
 399         struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id];
 400         uint64_t rx_offloads = dev_conf->rxmode.offloads;
 401         struct bnxt_rx_queue *rxq;
 402         unsigned int j;
 403         int rc;
 404
 405         rc = bnxt_vnic_grp_alloc(bp, vnic);
 406         if (rc)
 407                 goto err_out;
 408
 409         PMD_DRV_LOG(DEBUG, "vnic[%d] = %p vnic->fw_grp_ids = %p\n",
 410                     vnic_id, vnic, vnic->fw_grp_ids);
 411
 412         rc = bnxt_hwrm_vnic_alloc(bp, vnic);
 413         if (rc)
 414                 goto err_out;
 415
 416         /* Alloc RSS context only if RSS mode is enabled */
 417         if (dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS) {
 418                 int j, nr_ctxs = bnxt_rss_ctxts(bp);
 419
 420                 if (bp->rx_nr_rings > BNXT_RSS_TBL_SIZE_P5) {
 421                         PMD_DRV_LOG(ERR, "RxQ cnt %d > reta_size %d\n",
 422                                     bp->rx_nr_rings, BNXT_RSS_TBL_SIZE_P5);
 423                         PMD_DRV_LOG(ERR,
 424                                     "Only queues 0-%d will be in RSS table\n",
 425                                     BNXT_RSS_TBL_SIZE_P5 - 1);
 426                 }
 427
 428                 rc = 0;
 429                 for (j = 0; j < nr_ctxs; j++) {
 430                         rc = bnxt_hwrm_vnic_ctx_alloc(bp, vnic, j);
 431                         if (rc)
 432                                 break;
 433                 }
 434                 if (rc) {
 435                         PMD_DRV_LOG(ERR,
 436                                     "HWRM vnic %d ctx %d alloc failure rc: %x\n",
 437                                     vnic_id, j, rc);
 438                         goto err_out;
 439                 }
 440                 vnic->num_lb_ctxts = nr_ctxs;
 441         }
 442
 443         /*
 444          * Firmware sets pf pair in default vnic cfg. If the VLAN strip
 445          * setting is not available at this time, it will not be
 446          * configured correctly in the CFA.
 447          */
 448         if (rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
 449                 vnic->vlan_strip = true;
 450         else
 451                 vnic->vlan_strip = false;
 452
 453         rc = bnxt_hwrm_vnic_cfg(bp, vnic);
 454         if (rc)
 455                 goto err_out;
 456
 457         rc = bnxt_set_hwrm_vnic_filters(bp, vnic);
 458         if (rc)
 459                 goto err_out;
 460
 461         for (j = 0; j < bp->rx_num_qs_per_vnic; j++) {
 462                 rxq = bp->eth_dev->data->rx_queues[j];
 463
 464                 PMD_DRV_LOG(DEBUG,
 465                             "rxq[%d]->vnic=%p vnic->fw_grp_ids=%p\n",
 466                             j, rxq->vnic, rxq->vnic->fw_grp_ids);
 467
 468                 if (BNXT_HAS_RING_GRPS(bp) && rxq->rx_deferred_start)
 469                         rxq->vnic->fw_grp_ids[j] = INVALID_HW_RING_ID;
 470                 else
 471                         vnic->rx_queue_cnt++;
 472         }
 473
 474         PMD_DRV_LOG(DEBUG, "vnic->rx_queue_cnt = %d\n", vnic->rx_queue_cnt);
 475
 476         rc = bnxt_vnic_rss_configure(bp, vnic);
 477         if (rc)
 478                 goto err_out;
 479
 480         bnxt_hwrm_vnic_plcmode_cfg(bp, vnic);
 481
 482         if (rx_offloads & DEV_RX_OFFLOAD_TCP_LRO)
 483                 bnxt_hwrm_vnic_tpa_cfg(bp, vnic, 1);
 484         else
 485                 bnxt_hwrm_vnic_tpa_cfg(bp, vnic, 0);
 486
 487         return 0;
 488 err_out:
 489         PMD_DRV_LOG(ERR, "HWRM vnic %d cfg failure rc: %x\n",
 490                     vnic_id, rc);
 491         return rc;
 492 }
 493
 494 static int bnxt_register_fc_ctx_mem(struct bnxt *bp)
 495 {
 496         int rc = 0;
 497
 498         rc = bnxt_hwrm_ctx_rgtr(bp, bp->flow_stat->rx_fc_in_tbl.dma,
 499                                 &bp->flow_stat->rx_fc_in_tbl.ctx_id);
 500         if (rc)
 501                 return rc;
 502
 503         PMD_DRV_LOG(DEBUG,
 504                     "rx_fc_in_tbl.va = %p rx_fc_in_tbl.dma = %p"
 505                     " rx_fc_in_tbl.ctx_id = %d\n",
 506                     bp->flow_stat->rx_fc_in_tbl.va,
 507                     (void *)((uintptr_t)bp->flow_stat->rx_fc_in_tbl.dma),
 508                     bp->flow_stat->rx_fc_in_tbl.ctx_id);
 509
 510         rc = bnxt_hwrm_ctx_rgtr(bp, bp->flow_stat->rx_fc_out_tbl.dma,
 511                                 &bp->flow_stat->rx_fc_out_tbl.ctx_id);
 512         if (rc)
 513                 return rc;
 514
 515         PMD_DRV_LOG(DEBUG,
 516                     "rx_fc_out_tbl.va = %p rx_fc_out_tbl.dma = %p"
 517                     " rx_fc_out_tbl.ctx_id = %d\n",
 518                     bp->flow_stat->rx_fc_out_tbl.va,
 519                     (void *)((uintptr_t)bp->flow_stat->rx_fc_out_tbl.dma),
 520                     bp->flow_stat->rx_fc_out_tbl.ctx_id);
 521
 522         rc = bnxt_hwrm_ctx_rgtr(bp, bp->flow_stat->tx_fc_in_tbl.dma,
 523                                 &bp->flow_stat->tx_fc_in_tbl.ctx_id);
 524         if (rc)
 525                 return rc;
 526
 527         PMD_DRV_LOG(DEBUG,
 528                     "tx_fc_in_tbl.va = %p tx_fc_in_tbl.dma = %p"
 529                     " tx_fc_in_tbl.ctx_id = %d\n",
 530                     bp->flow_stat->tx_fc_in_tbl.va,
 531                     (void *)((uintptr_t)bp->flow_stat->tx_fc_in_tbl.dma),
 532                     bp->flow_stat->tx_fc_in_tbl.ctx_id);
 533
 534         rc = bnxt_hwrm_ctx_rgtr(bp, bp->flow_stat->tx_fc_out_tbl.dma,
 535                                 &bp->flow_stat->tx_fc_out_tbl.ctx_id);
 536         if (rc)
 537                 return rc;
 538
 539         PMD_DRV_LOG(DEBUG,
 540                     "tx_fc_out_tbl.va = %p tx_fc_out_tbl.dma = %p"
 541                     " tx_fc_out_tbl.ctx_id = %d\n",
 542                     bp->flow_stat->tx_fc_out_tbl.va,
 543                     (void *)((uintptr_t)bp->flow_stat->tx_fc_out_tbl.dma),
 544                     bp->flow_stat->tx_fc_out_tbl.ctx_id);
 545
 546         memset(bp->flow_stat->rx_fc_out_tbl.va,
 547                0,
 548                bp->flow_stat->rx_fc_out_tbl.size);
 549         rc = bnxt_hwrm_cfa_counter_cfg(bp, BNXT_DIR_RX,
 550                                        CFA_COUNTER_CFG_IN_COUNTER_TYPE_FC,
 551                                        bp->flow_stat->rx_fc_out_tbl.ctx_id,
 552                                        bp->flow_stat->max_fc,
 553                                        true);
 554         if (rc)
 555                 return rc;
 556
 557         memset(bp->flow_stat->tx_fc_out_tbl.va,
 558                0,
 559                bp->flow_stat->tx_fc_out_tbl.size);
 560         rc = bnxt_hwrm_cfa_counter_cfg(bp, BNXT_DIR_TX,
 561                                        CFA_COUNTER_CFG_IN_COUNTER_TYPE_FC,
 562                                        bp->flow_stat->tx_fc_out_tbl.ctx_id,
 563                                        bp->flow_stat->max_fc,
 564                                        true);
 565
 566         return rc;
 567 }
 568
 569 static int bnxt_alloc_ctx_mem_buf(char *type, size_t size,
 570                                   struct bnxt_ctx_mem_buf_info *ctx)
 571 {
 572         if (!ctx)
 573                 return -EINVAL;
 574
 575         ctx->va = rte_zmalloc(type, size, 0);
 576         if (ctx->va == NULL)
 577                 return -ENOMEM;
 578         rte_mem_lock_page(ctx->va);
 579         ctx->size = size;
 580         ctx->dma = rte_mem_virt2iova(ctx->va);
 581         if (ctx->dma == RTE_BAD_IOVA)
 582                 return -ENOMEM;
 583
 584         return 0;
 585 }
 586
 587 static int bnxt_init_fc_ctx_mem(struct bnxt *bp)
 588 {
 589         struct rte_pci_device *pdev = bp->pdev;
 590         char type[RTE_MEMZONE_NAMESIZE];
 591         uint16_t max_fc;
 592         int rc = 0;
 593
 594         max_fc = bp->flow_stat->max_fc;
 595
 596         sprintf(type, "bnxt_rx_fc_in_" PCI_PRI_FMT, pdev->addr.domain,
 597                 pdev->addr.bus, pdev->addr.devid, pdev->addr.function);
 598         /* 4 bytes for each counter-id */
 599         rc = bnxt_alloc_ctx_mem_buf(type,
 600                                     max_fc * 4,
 601                                     &bp->flow_stat->rx_fc_in_tbl);
 602         if (rc)
 603                 return rc;
 604
 605         sprintf(type, "bnxt_rx_fc_out_" PCI_PRI_FMT, pdev->addr.domain,
 606                 pdev->addr.bus, pdev->addr.devid, pdev->addr.function);
 607         /* 16 bytes for each counter - 8 bytes pkt_count, 8 bytes byte_count */
 608         rc = bnxt_alloc_ctx_mem_buf(type,
 609                                     max_fc * 16,
 610                                     &bp->flow_stat->rx_fc_out_tbl);
 611         if (rc)
 612                 return rc;
 613
 614         sprintf(type, "bnxt_tx_fc_in_" PCI_PRI_FMT, pdev->addr.domain,
 615                 pdev->addr.bus, pdev->addr.devid, pdev->addr.function);
 616         /* 4 bytes for each counter-id */
 617         rc = bnxt_alloc_ctx_mem_buf(type,
 618                                     max_fc * 4,
 619                                     &bp->flow_stat->tx_fc_in_tbl);
 620         if (rc)
 621                 return rc;
 622
 623         sprintf(type, "bnxt_tx_fc_out_" PCI_PRI_FMT, pdev->addr.domain,
 624                 pdev->addr.bus, pdev->addr.devid, pdev->addr.function);
 625         /* 16 bytes for each counter - 8 bytes pkt_count, 8 bytes byte_count */
 626         rc = bnxt_alloc_ctx_mem_buf(type,
 627                                     max_fc * 16,
 628                                     &bp->flow_stat->tx_fc_out_tbl);
 629         if (rc)
 630                 return rc;
 631
 632         rc = bnxt_register_fc_ctx_mem(bp);
 633
 634         return rc;
 635 }
 636
 637 static int bnxt_init_ctx_mem(struct bnxt *bp)
 638 {
 639         int rc = 0;
 640
 641         if (!(bp->fw_cap & BNXT_FW_CAP_ADV_FLOW_COUNTERS) ||
 642             !(BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp)) ||
 643             !BNXT_FLOW_XSTATS_EN(bp))
 644                 return 0;
 645
 646         rc = bnxt_hwrm_cfa_counter_qcaps(bp, &bp->flow_stat->max_fc);
 647         if (rc)
 648                 return rc;
 649
 650         rc = bnxt_init_fc_ctx_mem(bp);
 651
 652         return rc;
 653 }
 654
 655 static int bnxt_update_phy_setting(struct bnxt *bp)
 656 {
 657         struct rte_eth_link new;
 658         int rc;
 659
 660         rc = bnxt_get_hwrm_link_config(bp, &new);
 661         if (rc) {
 662                 PMD_DRV_LOG(ERR, "Failed to get link settings\n");
 663                 return rc;
 664         }
 665
 666         /*
 667          * On BCM957508-N2100 adapters, FW will not allow any user other
 668          * than BMC to shutdown the port. bnxt_get_hwrm_link_config() call
 669          * always returns link up. Force phy update always in that case.
 670          */
 671         if (!new.link_status || IS_BNXT_DEV_957508_N2100(bp)) {
 672                 rc = bnxt_set_hwrm_link_config(bp, true);
 673                 if (rc) {
 674                         PMD_DRV_LOG(ERR, "Failed to update PHY settings\n");
 675                         return rc;
 676                 }
 677         }
 678
 679         return rc;
 680 }
 681
 682 static int bnxt_start_nic(struct bnxt *bp)
 683 {
 684         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(bp->eth_dev);
 685         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
 686         uint32_t intr_vector = 0;
 687         uint32_t queue_id, base = BNXT_MISC_VEC_ID;
 688         uint32_t vec = BNXT_MISC_VEC_ID;
 689         unsigned int i, j;
 690         int rc;
 691
 692         if (bp->eth_dev->data->mtu > RTE_ETHER_MTU) {
 693                 bp->eth_dev->data->dev_conf.rxmode.offloads |=
 694                         DEV_RX_OFFLOAD_JUMBO_FRAME;
 695                 bp->flags |= BNXT_FLAG_JUMBO;
 696         } else {
 697                 bp->eth_dev->data->dev_conf.rxmode.offloads &=
 698                         ~DEV_RX_OFFLOAD_JUMBO_FRAME;
 699                 bp->flags &= ~BNXT_FLAG_JUMBO;
 700         }
 701
 702         /* THOR does not support ring groups.
 703          * But we will use the array to save RSS context IDs.
 704          */
 705         if (BNXT_CHIP_P5(bp))
 706                 bp->max_ring_grps = BNXT_MAX_RSS_CTXTS_P5;
 707
 708         rc = bnxt_alloc_all_hwrm_stat_ctxs(bp);
 709         if (rc) {
 710                 PMD_DRV_LOG(ERR, "HWRM stat ctx alloc failure rc: %x\n", rc);
 711                 goto err_out;
 712         }
 713
 714         rc = bnxt_alloc_hwrm_rings(bp);
 715         if (rc) {
 716                 PMD_DRV_LOG(ERR, "HWRM ring alloc failure rc: %x\n", rc);
 717                 goto err_out;
 718         }
 719
 720         rc = bnxt_alloc_all_hwrm_ring_grps(bp);
 721         if (rc) {
 722                 PMD_DRV_LOG(ERR, "HWRM ring grp alloc failure: %x\n", rc);
 723                 goto err_out;
 724         }
 725
 726         if (!(bp->vnic_cap_flags & BNXT_VNIC_CAP_COS_CLASSIFY))
 727                 goto skip_cosq_cfg;
 728
 729         for (j = 0, i = 0; i < BNXT_COS_QUEUE_COUNT; i++) {
 730                 if (bp->rx_cos_queue[i].id != 0xff) {
 731                         struct bnxt_vnic_info *vnic = &bp->vnic_info[j++];
 732
 733                         if (!vnic) {
 734                                 PMD_DRV_LOG(ERR,
 735                                             "Num pools more than FW profile\n");
 736                                 rc = -EINVAL;
 737                                 goto err_out;
 738                         }
 739                         vnic->cos_queue_id = bp->rx_cos_queue[i].id;
 740                         bp->rx_cosq_cnt++;
 741                 }
 742         }
 743
 744 skip_cosq_cfg:
 745         rc = bnxt_mq_rx_configure(bp);
 746         if (rc) {
 747                 PMD_DRV_LOG(ERR, "MQ mode configure failure rc: %x\n", rc);
 748                 goto err_out;
 749         }
 750
 751         /* default vnic 0 */
 752         rc = bnxt_setup_one_vnic(bp, 0);
 753         if (rc)
 754                 goto err_out;
 755         /* VNIC configuration */
 756         if (BNXT_RFS_NEEDS_VNIC(bp)) {
 757                 for (i = 1; i < bp->nr_vnics; i++) {
 758                         rc = bnxt_setup_one_vnic(bp, i);
 759                         if (rc)
 760                                 goto err_out;
 761                 }
 762         }
 763
 764         rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, &bp->vnic_info[0], 0, NULL);
 765         if (rc) {
 766                 PMD_DRV_LOG(ERR,
 767                         "HWRM cfa l2 rx mask failure rc: %x\n", rc);
 768                 goto err_out;
 769         }
 770
 771         /* check and configure queue intr-vector mapping */
 772         if ((rte_intr_cap_multiple(intr_handle) ||
 773              !RTE_ETH_DEV_SRIOV(bp->eth_dev).active) &&
 774             bp->eth_dev->data->dev_conf.intr_conf.rxq != 0) {
 775                 intr_vector = bp->eth_dev->data->nb_rx_queues;
 776                 PMD_DRV_LOG(DEBUG, "intr_vector = %d\n", intr_vector);
 777                 if (intr_vector > bp->rx_cp_nr_rings) {
 778                         PMD_DRV_LOG(ERR, "At most %d intr queues supported",
 779                                         bp->rx_cp_nr_rings);
 780                         return -ENOTSUP;
 781                 }
 782                 rc = rte_intr_efd_enable(intr_handle, intr_vector);
 783                 if (rc)
 784                         return rc;
 785         }
 786
 787         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
 788                 intr_handle->intr_vec =
 789                         rte_zmalloc("intr_vec",
 790                                     bp->eth_dev->data->nb_rx_queues *
 791                                     sizeof(int), 0);
 792                 if (intr_handle->intr_vec == NULL) {
 793                         PMD_DRV_LOG(ERR, "Failed to allocate %d rx_queues"
 794                                 " intr_vec", bp->eth_dev->data->nb_rx_queues);
 795                         rc = -ENOMEM;
 796                         goto err_out;
 797                 }
 798                 PMD_DRV_LOG(DEBUG, "intr_handle->intr_vec = %p "
 799                         "intr_handle->nb_efd = %d intr_handle->max_intr = %d\n",
 800                          intr_handle->intr_vec, intr_handle->nb_efd,
 801                         intr_handle->max_intr);
 802                 for (queue_id = 0; queue_id < bp->eth_dev->data->nb_rx_queues;
 803                      queue_id++) {
 804                         intr_handle->intr_vec[queue_id] =
 805                                                         vec + BNXT_RX_VEC_START;
 806                         if (vec < base + intr_handle->nb_efd - 1)
 807                                 vec++;
 808                 }
 809         }
 810
 811         /* enable uio/vfio intr/eventfd mapping */
 812         rc = rte_intr_enable(intr_handle);
 813 #ifndef RTE_EXEC_ENV_FREEBSD
 814         /* In FreeBSD OS, nic_uio driver does not support interrupts */
 815         if (rc)
 816                 goto err_out;
 817 #endif
 818
 819         rc = bnxt_update_phy_setting(bp);
 820         if (rc)
 821                 goto err_out;
 822
 823         bp->mark_table = rte_zmalloc("bnxt_mark_table", BNXT_MARK_TABLE_SZ, 0);
 824         if (!bp->mark_table)
 825                 PMD_DRV_LOG(ERR, "Allocation of mark table failed\n");
 826
 827         return 0;
 828
 829 err_out:
 830         /* Some of the error status returned by FW may not be from errno.h */
 831         if (rc > 0)
 832                 rc = -EIO;
 833
 834         return rc;
 835 }
 836
 837 static int bnxt_shutdown_nic(struct bnxt *bp)
 838 {
 839         bnxt_free_all_hwrm_resources(bp);
 840         bnxt_free_all_filters(bp);
 841         bnxt_free_all_vnics(bp);
 842         return 0;
 843 }
 844
 845 /*
 846  * Device configuration and status function
 847  */
 848
 849 uint32_t bnxt_get_speed_capabilities(struct bnxt *bp)
 850 {
 851         uint32_t link_speed = bp->link_info->support_speeds;
 852         uint32_t speed_capa = 0;
 853
 854         /* If PAM4 is configured, use PAM4 supported speed */
 855         if (link_speed == 0 && bp->link_info->support_pam4_speeds > 0)
 856                 link_speed = bp->link_info->support_pam4_speeds;
 857
 858         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_100MB)
 859                 speed_capa |= ETH_LINK_SPEED_100M;
 860         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_100MBHD)
 861                 speed_capa |= ETH_LINK_SPEED_100M_HD;
 862         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_1GB)
 863                 speed_capa |= ETH_LINK_SPEED_1G;
 864         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_2_5GB)
 865                 speed_capa |= ETH_LINK_SPEED_2_5G;
 866         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_10GB)
 867                 speed_capa |= ETH_LINK_SPEED_10G;
 868         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_20GB)
 869                 speed_capa |= ETH_LINK_SPEED_20G;
 870         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_25GB)
 871                 speed_capa |= ETH_LINK_SPEED_25G;
 872         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_40GB)
 873                 speed_capa |= ETH_LINK_SPEED_40G;
 874         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_50GB)
 875                 speed_capa |= ETH_LINK_SPEED_50G;
 876         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_100GB)
 877                 speed_capa |= ETH_LINK_SPEED_100G;
 878         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_PAM4_SPEEDS_50G)
 879                 speed_capa |= ETH_LINK_SPEED_50G;
 880         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_PAM4_SPEEDS_100G)
 881                 speed_capa |= ETH_LINK_SPEED_100G;
 882         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_PAM4_SPEEDS_200G)
 883                 speed_capa |= ETH_LINK_SPEED_200G;
 884
 885         if (bp->link_info->auto_mode ==
 886             HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_MODE_NONE)
 887                 speed_capa |= ETH_LINK_SPEED_FIXED;
 888
 889         return speed_capa;
 890 }
 891
 892 static int bnxt_dev_info_get_op(struct rte_eth_dev *eth_dev,
 893                                 struct rte_eth_dev_info *dev_info)
 894 {
 895         struct rte_pci_device *pdev = RTE_DEV_TO_PCI(eth_dev->device);
 896         struct bnxt *bp = eth_dev->data->dev_private;
 897         uint16_t max_vnics, i, j, vpool, vrxq;
 898         unsigned int max_rx_rings;
 899         int rc;
 900
 901         rc = is_bnxt_in_error(bp);
 902         if (rc)
 903                 return rc;
 904
 905         /* MAC Specifics */
 906         dev_info->max_mac_addrs = bp->max_l2_ctx;
 907         dev_info->max_hash_mac_addrs = 0;
 908
 909         /* PF/VF specifics */
 910         if (BNXT_PF(bp))
 911                 dev_info->max_vfs = pdev->max_vfs;
 912
 913         max_rx_rings = bnxt_max_rings(bp);
 914         /* For the sake of symmetry, max_rx_queues = max_tx_queues */
 915         dev_info->max_rx_queues = max_rx_rings;
 916         dev_info->max_tx_queues = max_rx_rings;
 917         dev_info->reta_size = bnxt_rss_hash_tbl_size(bp);
 918         dev_info->hash_key_size = 40;
 919         max_vnics = bp->max_vnics;
 920
 921         /* MTU specifics */
 922         dev_info->min_mtu = RTE_ETHER_MIN_MTU;
 923         dev_info->max_mtu = BNXT_MAX_MTU;
 924
 925         /* Fast path specifics */
 926         dev_info->min_rx_bufsize = 1;
 927         dev_info->max_rx_pktlen = BNXT_MAX_PKT_LEN;
 928
 929         dev_info->rx_offload_capa = BNXT_DEV_RX_OFFLOAD_SUPPORT;
 930         if (bp->flags & BNXT_FLAG_PTP_SUPPORTED)
 931                 dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_TIMESTAMP;
 932         dev_info->tx_queue_offload_capa = DEV_TX_OFFLOAD_MBUF_FAST_FREE;
 933         dev_info->tx_offload_capa = BNXT_DEV_TX_OFFLOAD_SUPPORT |
 934                                     dev_info->tx_queue_offload_capa;
 935         dev_info->flow_type_rss_offloads = BNXT_ETH_RSS_SUPPORT;
 936
 937         dev_info->speed_capa = bnxt_get_speed_capabilities(bp);
 938
 939         /* *INDENT-OFF* */
 940         dev_info->default_rxconf = (struct rte_eth_rxconf) {
 941                 .rx_thresh = {
 942                         .pthresh = 8,
 943                         .hthresh = 8,
 944                         .wthresh = 0,
 945                 },
 946                 .rx_free_thresh = 32,
 947                 .rx_drop_en = BNXT_DEFAULT_RX_DROP_EN,
 948         };
 949
 950         dev_info->default_txconf = (struct rte_eth_txconf) {
 951                 .tx_thresh = {
 952                         .pthresh = 32,
 953                         .hthresh = 0,
 954                         .wthresh = 0,
 955                 },
 956                 .tx_free_thresh = 32,
 957                 .tx_rs_thresh = 32,
 958         };
 959         eth_dev->data->dev_conf.intr_conf.lsc = 1;
 960
 961         eth_dev->data->dev_conf.intr_conf.rxq = 1;
 962         dev_info->rx_desc_lim.nb_min = BNXT_MIN_RING_DESC;
 963         dev_info->rx_desc_lim.nb_max = BNXT_MAX_RX_RING_DESC;
 964         dev_info->tx_desc_lim.nb_min = BNXT_MIN_RING_DESC;
 965         dev_info->tx_desc_lim.nb_max = BNXT_MAX_TX_RING_DESC;
 966
 967         if (BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp)) {
 968                 dev_info->switch_info.name = eth_dev->device->name;
 969                 dev_info->switch_info.domain_id = bp->switch_domain_id;
 970                 dev_info->switch_info.port_id =
 971                                 BNXT_PF(bp) ? BNXT_SWITCH_PORT_ID_PF :
 972                                     BNXT_SWITCH_PORT_ID_TRUSTED_VF;
 973         }
 974
 975         /* *INDENT-ON* */
 976
 977         /*
 978          * TODO: default_rxconf, default_txconf, rx_desc_lim, and tx_desc_lim
 979          *       need further investigation.
 980          */
 981
 982         /* VMDq resources */
 983         vpool = 64; /* ETH_64_POOLS */
 984         vrxq = 128; /* ETH_VMDQ_DCB_NUM_QUEUES */
 985         for (i = 0; i < 4; vpool >>= 1, i++) {
 986                 if (max_vnics > vpool) {
 987                         for (j = 0; j < 5; vrxq >>= 1, j++) {
 988                                 if (dev_info->max_rx_queues > vrxq) {
 989                                         if (vpool > vrxq)
 990                                                 vpool = vrxq;
 991                                         goto found;
 992                                 }
 993                         }
 994                         /* Not enough resources to support VMDq */
 995                         break;
 996                 }
 997         }
 998         /* Not enough resources to support VMDq */
 999         vpool = 0;
1000         vrxq = 0;
1001 found:
1002         dev_info->max_vmdq_pools = vpool;
1003         dev_info->vmdq_queue_num = vrxq;
1004
1005         dev_info->vmdq_pool_base = 0;
1006         dev_info->vmdq_queue_base = 0;
1007
1008         return 0;
1009 }
1010
1011 /* Configure the device based on the configuration provided */
1012 static int bnxt_dev_configure_op(struct rte_eth_dev *eth_dev)
1013 {
1014         struct bnxt *bp = eth_dev->data->dev_private;
1015         uint64_t rx_offloads = eth_dev->data->dev_conf.rxmode.offloads;
1016         int rc;
1017
1018         bp->rx_queues = (void *)eth_dev->data->rx_queues;
1019         bp->tx_queues = (void *)eth_dev->data->tx_queues;
1020         bp->tx_nr_rings = eth_dev->data->nb_tx_queues;
1021         bp->rx_nr_rings = eth_dev->data->nb_rx_queues;
1022
1023         rc = is_bnxt_in_error(bp);
1024         if (rc)
1025                 return rc;
1026
1027         if (BNXT_VF(bp) && (bp->flags & BNXT_FLAG_NEW_RM)) {
1028                 rc = bnxt_hwrm_check_vf_rings(bp);
1029                 if (rc) {
1030                         PMD_DRV_LOG(ERR, "HWRM insufficient resources\n");
1031                         return -ENOSPC;
1032                 }
1033
1034                 /* If a resource has already been allocated - in this case
1035                  * it is the async completion ring, free it. Reallocate it after
1036                  * resource reservation. This will ensure the resource counts
1037                  * are calculated correctly.
1038                  */
1039
1040                 pthread_mutex_lock(&bp->def_cp_lock);
1041
1042                 if (!BNXT_HAS_NQ(bp) && bp->async_cp_ring) {
1043                         bnxt_disable_int(bp);
1044                         bnxt_free_cp_ring(bp, bp->async_cp_ring);
1045                 }
1046
1047                 rc = bnxt_hwrm_func_reserve_vf_resc(bp, false);
1048                 if (rc) {
1049                         PMD_DRV_LOG(ERR, "HWRM resource alloc fail:%x\n", rc);
1050                         pthread_mutex_unlock(&bp->def_cp_lock);
1051                         return -ENOSPC;
1052                 }
1053
1054                 if (!BNXT_HAS_NQ(bp) && bp->async_cp_ring) {
1055                         rc = bnxt_alloc_async_cp_ring(bp);
1056                         if (rc) {
1057                                 pthread_mutex_unlock(&bp->def_cp_lock);
1058                                 return rc;
1059                         }
1060                         bnxt_enable_int(bp);
1061                 }
1062
1063                 pthread_mutex_unlock(&bp->def_cp_lock);
1064         }
1065
1066         /* Inherit new configurations */
1067         if (eth_dev->data->nb_rx_queues > bp->max_rx_rings ||
1068             eth_dev->data->nb_tx_queues > bp->max_tx_rings ||
1069             eth_dev->data->nb_rx_queues + eth_dev->data->nb_tx_queues
1070                 + BNXT_NUM_ASYNC_CPR(bp) > bp->max_cp_rings ||
1071             eth_dev->data->nb_rx_queues + eth_dev->data->nb_tx_queues >
1072             bp->max_stat_ctx)
1073                 goto resource_error;
1074
1075         if (BNXT_HAS_RING_GRPS(bp) &&
1076             (uint32_t)(eth_dev->data->nb_rx_queues) > bp->max_ring_grps)
1077                 goto resource_error;
1078
1079         if (!(eth_dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_RSS) &&
1080             bp->max_vnics < eth_dev->data->nb_rx_queues)
1081                 goto resource_error;
1082
1083         bp->rx_cp_nr_rings = bp->rx_nr_rings;
1084         bp->tx_cp_nr_rings = bp->tx_nr_rings;
1085
1086         if (eth_dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG)
1087                 rx_offloads |= DEV_RX_OFFLOAD_RSS_HASH;
1088         eth_dev->data->dev_conf.rxmode.offloads = rx_offloads;
1089
1090         if (rx_offloads & DEV_RX_OFFLOAD_JUMBO_FRAME) {
1091                 eth_dev->data->mtu =
1092                         eth_dev->data->dev_conf.rxmode.max_rx_pkt_len -
1093                         RTE_ETHER_HDR_LEN - RTE_ETHER_CRC_LEN - VLAN_TAG_SIZE *
1094                         BNXT_NUM_VLANS;
1095                 bnxt_mtu_set_op(eth_dev, eth_dev->data->mtu);
1096         }
1097         return 0;
1098
1099 resource_error:
1100         PMD_DRV_LOG(ERR,
1101                     "Insufficient resources to support requested config\n");
1102         PMD_DRV_LOG(ERR,
1103                     "Num Queues Requested: Tx %d, Rx %d\n",
1104                     eth_dev->data->nb_tx_queues,
1105                     eth_dev->data->nb_rx_queues);
1106         PMD_DRV_LOG(ERR,
1107                     "MAX: TxQ %d, RxQ %d, CQ %d Stat %d, Grp %d, Vnic %d\n",
1108                     bp->max_tx_rings, bp->max_rx_rings, bp->max_cp_rings,
1109                     bp->max_stat_ctx, bp->max_ring_grps, bp->max_vnics);
1110         return -ENOSPC;
1111 }
1112
1113 void bnxt_print_link_info(struct rte_eth_dev *eth_dev)
1114 {
1115         struct rte_eth_link *link = &eth_dev->data->dev_link;
1116
1117         if (link->link_status)
1118                 PMD_DRV_LOG(INFO, "Port %d Link Up - speed %u Mbps - %s\n",
1119                         eth_dev->data->port_id,
1120                         (uint32_t)link->link_speed,
1121                         (link->link_duplex == ETH_LINK_FULL_DUPLEX) ?
1122                         ("full-duplex") : ("half-duplex\n"));
1123         else
1124                 PMD_DRV_LOG(INFO, "Port %d Link Down\n",
1125                         eth_dev->data->port_id);
1126 }
1127
1128 /*
1129  * Determine whether the current configuration requires support for scattered
1130  * receive; return 1 if scattered receive is required and 0 if not.
1131  */
1132 static int bnxt_scattered_rx(struct rte_eth_dev *eth_dev)
1133 {
1134         uint16_t buf_size;
1135         int i;
1136
1137         if (eth_dev->data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_SCATTER)
1138                 return 1;
1139
1140         if (eth_dev->data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_TCP_LRO)
1141                 return 1;
1142
1143         for (i = 0; i < eth_dev->data->nb_rx_queues; i++) {
1144                 struct bnxt_rx_queue *rxq = eth_dev->data->rx_queues[i];
1145
1146                 buf_size = (uint16_t)(rte_pktmbuf_data_room_size(rxq->mb_pool) -
1147                                       RTE_PKTMBUF_HEADROOM);
1148                 if (eth_dev->data->dev_conf.rxmode.max_rx_pkt_len > buf_size)
1149                         return 1;
1150         }
1151         return 0;
1152 }
1153
1154 static eth_rx_burst_t
1155 bnxt_receive_function(struct rte_eth_dev *eth_dev)
1156 {
1157         struct bnxt *bp = eth_dev->data->dev_private;
1158
1159         /* Disable vector mode RX for Stingray2 for now */
1160         if (BNXT_CHIP_SR2(bp)) {
1161                 bp->flags &= ~BNXT_FLAG_RX_VECTOR_PKT_MODE;
1162                 return bnxt_recv_pkts;
1163         }
1164
1165 #if defined(RTE_ARCH_X86) || defined(RTE_ARCH_ARM64)
1166 #ifndef RTE_LIBRTE_IEEE1588
1167         /*
1168          * Vector mode receive can be enabled only if scatter rx is not
1169          * in use and rx offloads are limited to VLAN stripping and
1170          * CRC stripping.
1171          */
1172         if (!eth_dev->data->scattered_rx &&
1173             !(eth_dev->data->dev_conf.rxmode.offloads &
1174               ~(DEV_RX_OFFLOAD_VLAN_STRIP |
1175                 DEV_RX_OFFLOAD_KEEP_CRC |
1176                 DEV_RX_OFFLOAD_JUMBO_FRAME |
1177                 DEV_RX_OFFLOAD_IPV4_CKSUM |
1178                 DEV_RX_OFFLOAD_UDP_CKSUM |
1179                 DEV_RX_OFFLOAD_TCP_CKSUM |
1180                 DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM |
1181                 DEV_RX_OFFLOAD_OUTER_UDP_CKSUM |
1182                 DEV_RX_OFFLOAD_RSS_HASH |
1183                 DEV_RX_OFFLOAD_VLAN_FILTER)) &&
1184             !BNXT_TRUFLOW_EN(bp) && BNXT_NUM_ASYNC_CPR(bp) &&
1185             rte_vect_get_max_simd_bitwidth() >= RTE_VECT_SIMD_128) {
1186                 PMD_DRV_LOG(INFO, "Using vector mode receive for port %d\n",
1187                             eth_dev->data->port_id);
1188                 bp->flags |= BNXT_FLAG_RX_VECTOR_PKT_MODE;
1189                 return bnxt_recv_pkts_vec;
1190         }
1191         PMD_DRV_LOG(INFO, "Vector mode receive disabled for port %d\n",
1192                     eth_dev->data->port_id);
1193         PMD_DRV_LOG(INFO,
1194                     "Port %d scatter: %d rx offload: %" PRIX64 "\n",
1195                     eth_dev->data->port_id,
1196                     eth_dev->data->scattered_rx,
1197                     eth_dev->data->dev_conf.rxmode.offloads);
1198 #endif
1199 #endif
1200         bp->flags &= ~BNXT_FLAG_RX_VECTOR_PKT_MODE;
1201         return bnxt_recv_pkts;
1202 }
1203
1204 static eth_tx_burst_t
1205 bnxt_transmit_function(struct rte_eth_dev *eth_dev)
1206 {
1207         struct bnxt *bp = eth_dev->data->dev_private;
1208
1209         /* Disable vector mode TX for Stingray2 for now */
1210         if (BNXT_CHIP_SR2(bp))
1211                 return bnxt_xmit_pkts;
1212
1213 #if defined(RTE_ARCH_X86) || defined(RTE_ARCH_ARM64)
1214 #ifndef RTE_LIBRTE_IEEE1588
1215         uint64_t offloads = eth_dev->data->dev_conf.txmode.offloads;
1216
1217         /*
1218          * Vector mode transmit can be enabled only if not using scatter rx
1219          * or tx offloads.
1220          */
1221         if (!eth_dev->data->scattered_rx &&
1222             !(offloads & ~DEV_TX_OFFLOAD_MBUF_FAST_FREE) &&
1223             !BNXT_TRUFLOW_EN(bp) &&
1224             rte_vect_get_max_simd_bitwidth() >= RTE_VECT_SIMD_128) {
1225                 PMD_DRV_LOG(INFO, "Using vector mode transmit for port %d\n",
1226                             eth_dev->data->port_id);
1227                 return bnxt_xmit_pkts_vec;
1228         }
1229         PMD_DRV_LOG(INFO, "Vector mode transmit disabled for port %d\n",
1230                     eth_dev->data->port_id);
1231         PMD_DRV_LOG(INFO,
1232                     "Port %d scatter: %d tx offload: %" PRIX64 "\n",
1233                     eth_dev->data->port_id,
1234                     eth_dev->data->scattered_rx,
1235                     offloads);
1236 #endif
1237 #endif
1238         return bnxt_xmit_pkts;
1239 }
1240
1241 static int bnxt_handle_if_change_status(struct bnxt *bp)
1242 {
1243         int rc;
1244
1245         /* Since fw has undergone a reset and lost all contexts,
1246          * set fatal flag to not issue hwrm during cleanup
1247          */
1248         bp->flags |= BNXT_FLAG_FATAL_ERROR;
1249         bnxt_uninit_resources(bp, true);
1250
1251         /* clear fatal flag so that re-init happens */
1252         bp->flags &= ~BNXT_FLAG_FATAL_ERROR;
1253         rc = bnxt_init_resources(bp, true);
1254
1255         bp->flags &= ~BNXT_FLAG_IF_CHANGE_HOT_FW_RESET_DONE;
1256
1257         return rc;
1258 }
1259
1260 static int bnxt_dev_set_link_up_op(struct rte_eth_dev *eth_dev)
1261 {
1262         struct bnxt *bp = eth_dev->data->dev_private;
1263         int rc = 0;
1264
1265         if (!BNXT_SINGLE_PF(bp))
1266                 return -ENOTSUP;
1267
1268         if (!bp->link_info->link_up)
1269                 rc = bnxt_set_hwrm_link_config(bp, true);
1270         if (!rc)
1271                 eth_dev->data->dev_link.link_status = 1;
1272
1273         bnxt_print_link_info(eth_dev);
1274         return rc;
1275 }
1276
1277 static int bnxt_dev_set_link_down_op(struct rte_eth_dev *eth_dev)
1278 {
1279         struct bnxt *bp = eth_dev->data->dev_private;
1280
1281         if (!BNXT_SINGLE_PF(bp))
1282                 return -ENOTSUP;
1283
1284         eth_dev->data->dev_link.link_status = 0;
1285         bnxt_set_hwrm_link_config(bp, false);
1286         bp->link_info->link_up = 0;
1287
1288         return 0;
1289 }
1290
1291 static void bnxt_free_switch_domain(struct bnxt *bp)
1292 {
1293         int rc = 0;
1294
1295         if (bp->switch_domain_id) {
1296                 rc = rte_eth_switch_domain_free(bp->switch_domain_id);
1297                 if (rc)
1298                         PMD_DRV_LOG(ERR, "free switch domain:%d fail: %d\n",
1299                                     bp->switch_domain_id, rc);
1300         }
1301 }
1302
1303 static void bnxt_ptp_get_current_time(void *arg)
1304 {
1305         struct bnxt *bp = arg;
1306         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
1307         int rc;
1308
1309         rc = is_bnxt_in_error(bp);
1310         if (rc)
1311                 return;
1312
1313         if (!ptp)
1314                 return;
1315
1316         bnxt_hwrm_port_ts_query(bp, BNXT_PTP_FLAGS_CURRENT_TIME,
1317                                 &ptp->current_time);
1318
1319         rc = rte_eal_alarm_set(US_PER_S, bnxt_ptp_get_current_time, (void *)bp);
1320         if (rc != 0) {
1321                 PMD_DRV_LOG(ERR, "Failed to re-schedule PTP alarm\n");
1322                 bp->flags2 &= ~BNXT_FLAGS2_PTP_ALARM_SCHEDULED;
1323         }
1324 }
1325
1326 static int bnxt_schedule_ptp_alarm(struct bnxt *bp)
1327 {
1328         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
1329         int rc;
1330
1331         if (bp->flags2 & BNXT_FLAGS2_PTP_ALARM_SCHEDULED)
1332                 return 0;
1333
1334         bnxt_hwrm_port_ts_query(bp, BNXT_PTP_FLAGS_CURRENT_TIME,
1335                                 &ptp->current_time);
1336
1337         rc = rte_eal_alarm_set(US_PER_S, bnxt_ptp_get_current_time, (void *)bp);
1338         return rc;
1339 }
1340
1341 static void bnxt_cancel_ptp_alarm(struct bnxt *bp)
1342 {
1343         if (bp->flags2 & BNXT_FLAGS2_PTP_ALARM_SCHEDULED) {
1344                 rte_eal_alarm_cancel(bnxt_ptp_get_current_time, (void *)bp);
1345                 bp->flags2 &= ~BNXT_FLAGS2_PTP_ALARM_SCHEDULED;
1346         }
1347 }
1348
1349 static void bnxt_ptp_stop(struct bnxt *bp)
1350 {
1351         bnxt_cancel_ptp_alarm(bp);
1352         bp->flags2 &= ~BNXT_FLAGS2_PTP_TIMESYNC_ENABLED;
1353 }
1354
1355 static int bnxt_ptp_start(struct bnxt *bp)
1356 {
1357         int rc;
1358
1359         rc = bnxt_schedule_ptp_alarm(bp);
1360         if (rc != 0) {
1361                 PMD_DRV_LOG(ERR, "Failed to schedule PTP alarm\n");
1362         } else {
1363                 bp->flags2 |= BNXT_FLAGS2_PTP_TIMESYNC_ENABLED;
1364                 bp->flags2 |= BNXT_FLAGS2_PTP_ALARM_SCHEDULED;
1365         }
1366
1367         return rc;
1368 }
1369
1370 static int bnxt_dev_stop(struct rte_eth_dev *eth_dev)
1371 {
1372         struct bnxt *bp = eth_dev->data->dev_private;
1373         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1374         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1375         struct rte_eth_link link;
1376         int ret;
1377
1378         eth_dev->data->dev_started = 0;
1379         eth_dev->data->scattered_rx = 0;
1380
1381         /* Prevent crashes when queues are still in use */
1382         eth_dev->rx_pkt_burst = &bnxt_dummy_recv_pkts;
1383         eth_dev->tx_pkt_burst = &bnxt_dummy_xmit_pkts;
1384
1385         bnxt_disable_int(bp);
1386
1387         /* disable uio/vfio intr/eventfd mapping */
1388         rte_intr_disable(intr_handle);
1389
1390         /* Stop the child representors for this device */
1391         ret = bnxt_rep_stop_all(bp);
1392         if (ret != 0)
1393                 return ret;
1394
1395         /* delete the bnxt ULP port details */
1396         bnxt_ulp_port_deinit(bp);
1397
1398         bnxt_cancel_fw_health_check(bp);
1399
1400         if (BNXT_P5_PTP_TIMESYNC_ENABLED(bp))
1401                 bnxt_cancel_ptp_alarm(bp);
1402
1403         /* Do not bring link down during reset recovery */
1404         if (!is_bnxt_in_error(bp)) {
1405                 bnxt_dev_set_link_down_op(eth_dev);
1406                 /* Wait for link to be reset */
1407                 if (BNXT_SINGLE_PF(bp))
1408                         rte_delay_ms(500);
1409                 /* clear the recorded link status */
1410                 memset(&link, 0, sizeof(link));
1411                 rte_eth_linkstatus_set(eth_dev, &link);
1412         }
1413
1414         /* Clean queue intr-vector mapping */
1415         rte_intr_efd_disable(intr_handle);
1416         if (intr_handle->intr_vec != NULL) {
1417                 rte_free(intr_handle->intr_vec);
1418                 intr_handle->intr_vec = NULL;
1419         }
1420
1421         bnxt_hwrm_port_clr_stats(bp);
1422         bnxt_free_tx_mbufs(bp);
1423         bnxt_free_rx_mbufs(bp);
1424         /* Process any remaining notifications in default completion queue */
1425         bnxt_int_handler(eth_dev);
1426         bnxt_shutdown_nic(bp);
1427         bnxt_hwrm_if_change(bp, false);
1428
1429         rte_free(bp->mark_table);
1430         bp->mark_table = NULL;
1431
1432         bp->flags &= ~BNXT_FLAG_RX_VECTOR_PKT_MODE;
1433         bp->rx_cosq_cnt = 0;
1434         /* All filters are deleted on a port stop. */
1435         if (BNXT_FLOW_XSTATS_EN(bp))
1436                 bp->flow_stat->flow_count = 0;
1437
1438         return 0;
1439 }
1440
1441 /* Unload the driver, release resources */
1442 static int bnxt_dev_stop_op(struct rte_eth_dev *eth_dev)
1443 {
1444         struct bnxt *bp = eth_dev->data->dev_private;
1445
1446         pthread_mutex_lock(&bp->err_recovery_lock);
1447         if (bp->flags & BNXT_FLAG_FW_RESET) {
1448                 PMD_DRV_LOG(ERR,
1449                             "Adapter recovering from error..Please retry\n");
1450                 pthread_mutex_unlock(&bp->err_recovery_lock);
1451                 return -EAGAIN;
1452         }
1453         pthread_mutex_unlock(&bp->err_recovery_lock);
1454
1455         return bnxt_dev_stop(eth_dev);
1456 }
1457
1458 static int bnxt_dev_start_op(struct rte_eth_dev *eth_dev)
1459 {
1460         struct bnxt *bp = eth_dev->data->dev_private;
1461         uint64_t rx_offloads = eth_dev->data->dev_conf.rxmode.offloads;
1462         int vlan_mask = 0;
1463         int rc, retry_cnt = BNXT_IF_CHANGE_RETRY_COUNT;
1464
1465         if (!eth_dev->data->nb_tx_queues || !eth_dev->data->nb_rx_queues) {
1466                 PMD_DRV_LOG(ERR, "Queues are not configured yet!\n");
1467                 return -EINVAL;
1468         }
1469
1470         if (bp->rx_cp_nr_rings > RTE_ETHDEV_QUEUE_STAT_CNTRS)
1471                 PMD_DRV_LOG(ERR,
1472                             "RxQ cnt %d > RTE_ETHDEV_QUEUE_STAT_CNTRS %d\n",
1473                             bp->rx_cp_nr_rings, RTE_ETHDEV_QUEUE_STAT_CNTRS);
1474
1475         do {
1476                 rc = bnxt_hwrm_if_change(bp, true);
1477                 if (rc == 0 || rc != -EAGAIN)
1478                         break;
1479
1480                 rte_delay_ms(BNXT_IF_CHANGE_RETRY_INTERVAL);
1481         } while (retry_cnt--);
1482
1483         if (rc)
1484                 return rc;
1485
1486         if (bp->flags & BNXT_FLAG_IF_CHANGE_HOT_FW_RESET_DONE) {
1487                 rc = bnxt_handle_if_change_status(bp);
1488                 if (rc)
1489                         return rc;
1490         }
1491
1492         bnxt_enable_int(bp);
1493
1494         eth_dev->data->scattered_rx = bnxt_scattered_rx(eth_dev);
1495
1496         rc = bnxt_start_nic(bp);
1497         if (rc)
1498                 goto error;
1499
1500         eth_dev->data->dev_started = 1;
1501
1502         bnxt_link_update_op(eth_dev, 1);
1503
1504         if (rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER)
1505                 vlan_mask |= ETH_VLAN_FILTER_MASK;
1506         if (rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
1507                 vlan_mask |= ETH_VLAN_STRIP_MASK;
1508         rc = bnxt_vlan_offload_set_op(eth_dev, vlan_mask);
1509         if (rc)
1510                 goto error;
1511
1512         /* Initialize bnxt ULP port details */
1513         rc = bnxt_ulp_port_init(bp);
1514         if (rc)
1515                 goto error;
1516
1517         eth_dev->rx_pkt_burst = bnxt_receive_function(eth_dev);
1518         eth_dev->tx_pkt_burst = bnxt_transmit_function(eth_dev);
1519
1520         bnxt_schedule_fw_health_check(bp);
1521
1522         if (BNXT_P5_PTP_TIMESYNC_ENABLED(bp))
1523                 bnxt_schedule_ptp_alarm(bp);
1524
1525         return 0;
1526
1527 error:
1528         bnxt_dev_stop(eth_dev);
1529         return rc;
1530 }
1531
1532 static void
1533 bnxt_uninit_locks(struct bnxt *bp)
1534 {
1535         pthread_mutex_destroy(&bp->flow_lock);
1536         pthread_mutex_destroy(&bp->def_cp_lock);
1537         pthread_mutex_destroy(&bp->health_check_lock);
1538         pthread_mutex_destroy(&bp->err_recovery_lock);
1539         if (bp->rep_info) {
1540                 pthread_mutex_destroy(&bp->rep_info->vfr_lock);
1541                 pthread_mutex_destroy(&bp->rep_info->vfr_start_lock);
1542         }
1543 }
1544
1545 static void bnxt_drv_uninit(struct bnxt *bp)
1546 {
1547         bnxt_free_switch_domain(bp);
1548         bnxt_free_leds_info(bp);
1549         bnxt_free_cos_queues(bp);
1550         bnxt_free_link_info(bp);
1551         bnxt_free_pf_info(bp);
1552         bnxt_free_parent_info(bp);
1553         bnxt_uninit_locks(bp);
1554
1555         rte_memzone_free((const struct rte_memzone *)bp->tx_mem_zone);
1556         bp->tx_mem_zone = NULL;
1557         rte_memzone_free((const struct rte_memzone *)bp->rx_mem_zone);
1558         bp->rx_mem_zone = NULL;
1559
1560         bnxt_free_vf_info(bp);
1561
1562         rte_free(bp->grp_info);
1563         bp->grp_info = NULL;
1564 }
1565
1566 static int bnxt_dev_close_op(struct rte_eth_dev *eth_dev)
1567 {
1568         struct bnxt *bp = eth_dev->data->dev_private;
1569         int ret = 0;
1570
1571         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1572                 return 0;
1573
1574         pthread_mutex_lock(&bp->err_recovery_lock);
1575         if (bp->flags & BNXT_FLAG_FW_RESET) {
1576                 PMD_DRV_LOG(ERR,
1577                             "Adapter recovering from error...Please retry\n");
1578                 pthread_mutex_unlock(&bp->err_recovery_lock);
1579                 return -EAGAIN;
1580         }
1581         pthread_mutex_unlock(&bp->err_recovery_lock);
1582
1583         /* cancel the recovery handler before remove dev */
1584         rte_eal_alarm_cancel(bnxt_dev_reset_and_resume, (void *)bp);
1585         rte_eal_alarm_cancel(bnxt_dev_recover, (void *)bp);
1586         bnxt_cancel_fc_thread(bp);
1587
1588         if (eth_dev->data->dev_started)
1589                 ret = bnxt_dev_stop(eth_dev);
1590
1591         bnxt_uninit_resources(bp, false);
1592
1593         bnxt_drv_uninit(bp);
1594
1595         return ret;
1596 }
1597
1598 static void bnxt_mac_addr_remove_op(struct rte_eth_dev *eth_dev,
1599                                     uint32_t index)
1600 {
1601         struct bnxt *bp = eth_dev->data->dev_private;
1602         uint64_t pool_mask = eth_dev->data->mac_pool_sel[index];
1603         struct bnxt_vnic_info *vnic;
1604         struct bnxt_filter_info *filter, *temp_filter;
1605         uint32_t i;
1606
1607         if (is_bnxt_in_error(bp))
1608                 return;
1609
1610         /*
1611          * Loop through all VNICs from the specified filter flow pools to
1612          * remove the corresponding MAC addr filter
1613          */
1614         for (i = 0; i < bp->nr_vnics; i++) {
1615                 if (!(pool_mask & (1ULL << i)))
1616                         continue;
1617
1618                 vnic = &bp->vnic_info[i];
1619                 filter = STAILQ_FIRST(&vnic->filter);
1620                 while (filter) {
1621                         temp_filter = STAILQ_NEXT(filter, next);
1622                         if (filter->mac_index == index) {
1623                                 STAILQ_REMOVE(&vnic->filter, filter,
1624                                                 bnxt_filter_info, next);
1625                                 bnxt_hwrm_clear_l2_filter(bp, filter);
1626                                 bnxt_free_filter(bp, filter);
1627                         }
1628                         filter = temp_filter;
1629                 }
1630         }
1631 }
1632
1633 static int bnxt_add_mac_filter(struct bnxt *bp, struct bnxt_vnic_info *vnic,
1634                                struct rte_ether_addr *mac_addr, uint32_t index,
1635                                uint32_t pool)
1636 {
1637         struct bnxt_filter_info *filter;
1638         int rc = 0;
1639
1640         /* Attach requested MAC address to the new l2_filter */
1641         STAILQ_FOREACH(filter, &vnic->filter, next) {
1642                 if (filter->mac_index == index) {
1643                         PMD_DRV_LOG(DEBUG,
1644                                     "MAC addr already existed for pool %d\n",
1645                                     pool);
1646                         return 0;
1647                 }
1648         }
1649
1650         filter = bnxt_alloc_filter(bp);
1651         if (!filter) {
1652                 PMD_DRV_LOG(ERR, "L2 filter alloc failed\n");
1653                 return -ENODEV;
1654         }
1655
1656         /* bnxt_alloc_filter copies default MAC to filter->l2_addr. So,
1657          * if the MAC that's been programmed now is a different one, then,
1658          * copy that addr to filter->l2_addr
1659          */
1660         if (mac_addr)
1661                 memcpy(filter->l2_addr, mac_addr, RTE_ETHER_ADDR_LEN);
1662         filter->flags |= HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_OUTERMOST;
1663
1664         rc = bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id, filter);
1665         if (!rc) {
1666                 filter->mac_index = index;
1667                 if (filter->mac_index == 0)
1668                         STAILQ_INSERT_HEAD(&vnic->filter, filter, next);
1669                 else
1670                         STAILQ_INSERT_TAIL(&vnic->filter, filter, next);
1671         } else {
1672                 bnxt_free_filter(bp, filter);
1673         }
1674
1675         return rc;
1676 }
1677
1678 static int bnxt_mac_addr_add_op(struct rte_eth_dev *eth_dev,
1679                                 struct rte_ether_addr *mac_addr,
1680                                 uint32_t index, uint32_t pool)
1681 {
1682         struct bnxt *bp = eth_dev->data->dev_private;
1683         struct bnxt_vnic_info *vnic = &bp->vnic_info[pool];
1684         int rc = 0;
1685
1686         rc = is_bnxt_in_error(bp);
1687         if (rc)
1688                 return rc;
1689
1690         if (BNXT_VF(bp) && !BNXT_VF_IS_TRUSTED(bp)) {
1691                 PMD_DRV_LOG(ERR, "Cannot add MAC address to a VF interface\n");
1692                 return -ENOTSUP;
1693         }
1694
1695         if (!vnic) {
1696                 PMD_DRV_LOG(ERR, "VNIC not found for pool %d!\n", pool);
1697                 return -EINVAL;
1698         }
1699
1700         /* Filter settings will get applied when port is started */
1701         if (!eth_dev->data->dev_started)
1702                 return 0;
1703
1704         rc = bnxt_add_mac_filter(bp, vnic, mac_addr, index, pool);
1705
1706         return rc;
1707 }
1708
1709 int bnxt_link_update_op(struct rte_eth_dev *eth_dev, int wait_to_complete)
1710 {
1711         int rc = 0;
1712         struct bnxt *bp = eth_dev->data->dev_private;
1713         struct rte_eth_link new;
1714         int cnt = wait_to_complete ? BNXT_MAX_LINK_WAIT_CNT :
1715                         BNXT_MIN_LINK_WAIT_CNT;
1716
1717         rc = is_bnxt_in_error(bp);
1718         if (rc)
1719                 return rc;
1720
1721         memset(&new, 0, sizeof(new));
1722         do {
1723                 /* Retrieve link info from hardware */
1724                 rc = bnxt_get_hwrm_link_config(bp, &new);
1725                 if (rc) {
1726                         new.link_speed = ETH_LINK_SPEED_100M;
1727                         new.link_duplex = ETH_LINK_FULL_DUPLEX;
1728                         PMD_DRV_LOG(ERR,
1729                                 "Failed to retrieve link rc = 0x%x!\n", rc);
1730                         goto out;
1731                 }
1732
1733                 if (!wait_to_complete || new.link_status)
1734                         break;
1735
1736                 rte_delay_ms(BNXT_LINK_WAIT_INTERVAL);
1737         } while (cnt--);
1738
1739         /* Only single function PF can bring phy down.
1740          * When port is stopped, report link down for VF/MH/NPAR functions.
1741          */
1742         if (!BNXT_SINGLE_PF(bp) && !eth_dev->data->dev_started)
1743                 memset(&new, 0, sizeof(new));
1744
1745 out:
1746         /* Timed out or success */
1747         if (new.link_status != eth_dev->data->dev_link.link_status ||
1748             new.link_speed != eth_dev->data->dev_link.link_speed) {
1749                 rte_eth_linkstatus_set(eth_dev, &new);
1750
1751                 rte_eth_dev_callback_process(eth_dev,
1752                                              RTE_ETH_EVENT_INTR_LSC,
1753                                              NULL);
1754
1755                 bnxt_print_link_info(eth_dev);
1756         }
1757
1758         return rc;
1759 }
1760
1761 static int bnxt_promiscuous_enable_op(struct rte_eth_dev *eth_dev)
1762 {
1763         struct bnxt *bp = eth_dev->data->dev_private;
1764         struct bnxt_vnic_info *vnic;
1765         uint32_t old_flags;
1766         int rc;
1767
1768         rc = is_bnxt_in_error(bp);
1769         if (rc)
1770                 return rc;
1771
1772         /* Filter settings will get applied when port is started */
1773         if (!eth_dev->data->dev_started)
1774                 return 0;
1775
1776         if (bp->vnic_info == NULL)
1777                 return 0;
1778
1779         vnic = BNXT_GET_DEFAULT_VNIC(bp);
1780
1781         old_flags = vnic->flags;
1782         vnic->flags |= BNXT_VNIC_INFO_PROMISC;
1783         rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1784         if (rc != 0)
1785                 vnic->flags = old_flags;
1786
1787         return rc;
1788 }
1789
1790 static int bnxt_promiscuous_disable_op(struct rte_eth_dev *eth_dev)
1791 {
1792         struct bnxt *bp = eth_dev->data->dev_private;
1793         struct bnxt_vnic_info *vnic;
1794         uint32_t old_flags;
1795         int rc;
1796
1797         rc = is_bnxt_in_error(bp);
1798         if (rc)
1799                 return rc;
1800
1801         /* Filter settings will get applied when port is started */
1802         if (!eth_dev->data->dev_started)
1803                 return 0;
1804
1805         if (bp->vnic_info == NULL)
1806                 return 0;
1807
1808         vnic = BNXT_GET_DEFAULT_VNIC(bp);
1809
1810         old_flags = vnic->flags;
1811         vnic->flags &= ~BNXT_VNIC_INFO_PROMISC;
1812         rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1813         if (rc != 0)
1814                 vnic->flags = old_flags;
1815
1816         return rc;
1817 }
1818
1819 static int bnxt_allmulticast_enable_op(struct rte_eth_dev *eth_dev)
1820 {
1821         struct bnxt *bp = eth_dev->data->dev_private;
1822         struct bnxt_vnic_info *vnic;
1823         uint32_t old_flags;
1824         int rc;
1825
1826         rc = is_bnxt_in_error(bp);
1827         if (rc)
1828                 return rc;
1829
1830         /* Filter settings will get applied when port is started */
1831         if (!eth_dev->data->dev_started)
1832                 return 0;
1833
1834         if (bp->vnic_info == NULL)
1835                 return 0;
1836
1837         vnic = BNXT_GET_DEFAULT_VNIC(bp);
1838
1839         old_flags = vnic->flags;
1840         vnic->flags |= BNXT_VNIC_INFO_ALLMULTI;
1841         rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1842         if (rc != 0)
1843                 vnic->flags = old_flags;
1844
1845         return rc;
1846 }
1847
1848 static int bnxt_allmulticast_disable_op(struct rte_eth_dev *eth_dev)
1849 {
1850         struct bnxt *bp = eth_dev->data->dev_private;
1851         struct bnxt_vnic_info *vnic;
1852         uint32_t old_flags;
1853         int rc;
1854
1855         rc = is_bnxt_in_error(bp);
1856         if (rc)
1857                 return rc;
1858
1859         /* Filter settings will get applied when port is started */
1860         if (!eth_dev->data->dev_started)
1861                 return 0;
1862
1863         if (bp->vnic_info == NULL)
1864                 return 0;
1865
1866         vnic = BNXT_GET_DEFAULT_VNIC(bp);
1867
1868         old_flags = vnic->flags;
1869         vnic->flags &= ~BNXT_VNIC_INFO_ALLMULTI;
1870         rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1871         if (rc != 0)
1872                 vnic->flags = old_flags;
1873
1874         return rc;
1875 }
1876
1877 /* Return bnxt_rx_queue pointer corresponding to a given rxq. */
1878 static struct bnxt_rx_queue *bnxt_qid_to_rxq(struct bnxt *bp, uint16_t qid)
1879 {
1880         if (qid >= bp->rx_nr_rings)
1881                 return NULL;
1882
1883         return bp->eth_dev->data->rx_queues[qid];
1884 }
1885
1886 /* Return rxq corresponding to a given rss table ring/group ID. */
1887 static uint16_t bnxt_rss_to_qid(struct bnxt *bp, uint16_t fwr)
1888 {
1889         struct bnxt_rx_queue *rxq;
1890         unsigned int i;
1891
1892         if (!BNXT_HAS_RING_GRPS(bp)) {
1893                 for (i = 0; i < bp->rx_nr_rings; i++) {
1894                         rxq = bp->eth_dev->data->rx_queues[i];
1895                         if (rxq->rx_ring->rx_ring_struct->fw_ring_id == fwr)
1896                                 return rxq->index;
1897                 }
1898         } else {
1899                 for (i = 0; i < bp->rx_nr_rings; i++) {
1900                         if (bp->grp_info[i].fw_grp_id == fwr)
1901                                 return i;
1902                 }
1903         }
1904
1905         return INVALID_HW_RING_ID;
1906 }
1907
1908 static int bnxt_reta_update_op(struct rte_eth_dev *eth_dev,
1909                             struct rte_eth_rss_reta_entry64 *reta_conf,
1910                             uint16_t reta_size)
1911 {
1912         struct bnxt *bp = eth_dev->data->dev_private;
1913         struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
1914         struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp);
1915         uint16_t tbl_size = bnxt_rss_hash_tbl_size(bp);
1916         uint16_t idx, sft;
1917         int i, rc;
1918
1919         rc = is_bnxt_in_error(bp);
1920         if (rc)
1921                 return rc;
1922
1923         if (!vnic->rss_table)
1924                 return -EINVAL;
1925
1926         if (!(dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG))
1927                 return -EINVAL;
1928
1929         if (reta_size != tbl_size) {
1930                 PMD_DRV_LOG(ERR, "The configured hash table lookup size "
1931                         "(%d) must equal the size supported by the hardware "
1932                         "(%d)\n", reta_size, tbl_size);
1933                 return -EINVAL;
1934         }
1935
1936         for (i = 0; i < reta_size; i++) {
1937                 struct bnxt_rx_queue *rxq;
1938
1939                 idx = i / RTE_RETA_GROUP_SIZE;
1940                 sft = i % RTE_RETA_GROUP_SIZE;
1941
1942                 if (!(reta_conf[idx].mask & (1ULL << sft)))
1943                         continue;
1944
1945                 rxq = bnxt_qid_to_rxq(bp, reta_conf[idx].reta[sft]);
1946                 if (!rxq) {
1947                         PMD_DRV_LOG(ERR, "Invalid ring in reta_conf.\n");
1948                         return -EINVAL;
1949                 }
1950
1951                 if (BNXT_CHIP_P5(bp)) {
1952                         vnic->rss_table[i * 2] =
1953                                 rxq->rx_ring->rx_ring_struct->fw_ring_id;
1954                         vnic->rss_table[i * 2 + 1] =
1955                                 rxq->cp_ring->cp_ring_struct->fw_ring_id;
1956                 } else {
1957                         vnic->rss_table[i] =
1958                             vnic->fw_grp_ids[reta_conf[idx].reta[sft]];
1959                 }
1960         }
1961
1962         rc = bnxt_hwrm_vnic_rss_cfg(bp, vnic);
1963         return rc;
1964 }
1965
1966 static int bnxt_reta_query_op(struct rte_eth_dev *eth_dev,
1967                               struct rte_eth_rss_reta_entry64 *reta_conf,
1968                               uint16_t reta_size)
1969 {
1970         struct bnxt *bp = eth_dev->data->dev_private;
1971         struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp);
1972         uint16_t tbl_size = bnxt_rss_hash_tbl_size(bp);
1973         uint16_t idx, sft, i;
1974         int rc;
1975
1976         rc = is_bnxt_in_error(bp);
1977         if (rc)
1978                 return rc;
1979
1980         /* Retrieve from the default VNIC */
1981         if (!vnic)
1982                 return -EINVAL;
1983         if (!vnic->rss_table)
1984                 return -EINVAL;
1985
1986         if (reta_size != tbl_size) {
1987                 PMD_DRV_LOG(ERR, "The configured hash table lookup size "
1988                         "(%d) must equal the size supported by the hardware "
1989                         "(%d)\n", reta_size, tbl_size);
1990                 return -EINVAL;
1991         }
1992
1993         for (idx = 0, i = 0; i < reta_size; i++) {
1994                 idx = i / RTE_RETA_GROUP_SIZE;
1995                 sft = i % RTE_RETA_GROUP_SIZE;
1996
1997                 if (reta_conf[idx].mask & (1ULL << sft)) {
1998                         uint16_t qid;
1999
2000                         if (BNXT_CHIP_P5(bp))
2001                                 qid = bnxt_rss_to_qid(bp,
2002                                                       vnic->rss_table[i * 2]);
2003                         else
2004                                 qid = bnxt_rss_to_qid(bp, vnic->rss_table[i]);
2005
2006                         if (qid == INVALID_HW_RING_ID) {
2007                                 PMD_DRV_LOG(ERR, "Inv. entry in rss table.\n");
2008                                 return -EINVAL;
2009                         }
2010                         reta_conf[idx].reta[sft] = qid;
2011                 }
2012         }
2013
2014         return 0;
2015 }
2016
2017 static int bnxt_rss_hash_update_op(struct rte_eth_dev *eth_dev,
2018                                    struct rte_eth_rss_conf *rss_conf)
2019 {
2020         struct bnxt *bp = eth_dev->data->dev_private;
2021         struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
2022         struct bnxt_vnic_info *vnic;
2023         int rc;
2024
2025         rc = is_bnxt_in_error(bp);
2026         if (rc)
2027                 return rc;
2028
2029         /*
2030          * If RSS enablement were different than dev_configure,
2031          * then return -EINVAL
2032          */
2033         if (dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG) {
2034                 if (!rss_conf->rss_hf)
2035                         PMD_DRV_LOG(ERR, "Hash type NONE\n");
2036         } else {
2037                 if (rss_conf->rss_hf & BNXT_ETH_RSS_SUPPORT)
2038                         return -EINVAL;
2039         }
2040
2041         bp->flags |= BNXT_FLAG_UPDATE_HASH;
2042         memcpy(&eth_dev->data->dev_conf.rx_adv_conf.rss_conf,
2043                rss_conf,
2044                sizeof(*rss_conf));
2045
2046         /* Update the default RSS VNIC(s) */
2047         vnic = BNXT_GET_DEFAULT_VNIC(bp);
2048         vnic->hash_type = bnxt_rte_to_hwrm_hash_types(rss_conf->rss_hf);
2049         vnic->hash_mode =
2050                 bnxt_rte_to_hwrm_hash_level(bp, rss_conf->rss_hf,
2051                                             ETH_RSS_LEVEL(rss_conf->rss_hf));
2052
2053         /*
2054          * If hashkey is not specified, use the previously configured
2055          * hashkey
2056          */
2057         if (!rss_conf->rss_key)
2058                 goto rss_config;
2059
2060         if (rss_conf->rss_key_len != HW_HASH_KEY_SIZE) {
2061                 PMD_DRV_LOG(ERR,
2062                             "Invalid hashkey length, should be 16 bytes\n");
2063                 return -EINVAL;
2064         }
2065         memcpy(vnic->rss_hash_key, rss_conf->rss_key, rss_conf->rss_key_len);
2066
2067 rss_config:
2068         rc = bnxt_hwrm_vnic_rss_cfg(bp, vnic);
2069         return rc;
2070 }
2071
2072 static int bnxt_rss_hash_conf_get_op(struct rte_eth_dev *eth_dev,
2073                                      struct rte_eth_rss_conf *rss_conf)
2074 {
2075         struct bnxt *bp = eth_dev->data->dev_private;
2076         struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp);
2077         int len, rc;
2078         uint32_t hash_types;
2079
2080         rc = is_bnxt_in_error(bp);
2081         if (rc)
2082                 return rc;
2083
2084         /* RSS configuration is the same for all VNICs */
2085         if (vnic && vnic->rss_hash_key) {
2086                 if (rss_conf->rss_key) {
2087                         len = rss_conf->rss_key_len <= HW_HASH_KEY_SIZE ?
2088                               rss_conf->rss_key_len : HW_HASH_KEY_SIZE;
2089                         memcpy(rss_conf->rss_key, vnic->rss_hash_key, len);
2090                 }
2091
2092                 hash_types = vnic->hash_type;
2093                 rss_conf->rss_hf = 0;
2094                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV4) {
2095                         rss_conf->rss_hf |= ETH_RSS_IPV4;
2096                         hash_types &= ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV4;
2097                 }
2098                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV4) {
2099                         rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP;
2100                         hash_types &=
2101                                 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV4;
2102                 }
2103                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV4) {
2104                         rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
2105                         hash_types &=
2106                                 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV4;
2107                 }
2108                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6) {
2109                         rss_conf->rss_hf |= ETH_RSS_IPV6;
2110                         hash_types &= ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6;
2111                 }
2112                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV6) {
2113                         rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV6_TCP;
2114                         hash_types &=
2115                                 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV6;
2116                 }
2117                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV6) {
2118                         rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;
2119                         hash_types &=
2120                                 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV6;
2121                 }
2122
2123                 rss_conf->rss_hf |=
2124                         bnxt_hwrm_to_rte_rss_level(bp, vnic->hash_mode);
2125
2126                 if (hash_types) {
2127                         PMD_DRV_LOG(ERR,
2128                                 "Unknown RSS config from firmware (%08x), RSS disabled",
2129                                 vnic->hash_type);
2130                         return -ENOTSUP;
2131                 }
2132         } else {
2133                 rss_conf->rss_hf = 0;
2134         }
2135         return 0;
2136 }
2137
2138 static int bnxt_flow_ctrl_get_op(struct rte_eth_dev *dev,
2139                                struct rte_eth_fc_conf *fc_conf)
2140 {
2141         struct bnxt *bp = dev->data->dev_private;
2142         struct rte_eth_link link_info;
2143         int rc;
2144
2145         rc = is_bnxt_in_error(bp);
2146         if (rc)
2147                 return rc;
2148
2149         rc = bnxt_get_hwrm_link_config(bp, &link_info);
2150         if (rc)
2151                 return rc;
2152
2153         memset(fc_conf, 0, sizeof(*fc_conf));
2154         if (bp->link_info->auto_pause)
2155                 fc_conf->autoneg = 1;
2156         switch (bp->link_info->pause) {
2157         case 0:
2158                 fc_conf->mode = RTE_FC_NONE;
2159                 break;
2160         case HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_TX:
2161                 fc_conf->mode = RTE_FC_TX_PAUSE;
2162                 break;
2163         case HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_RX:
2164                 fc_conf->mode = RTE_FC_RX_PAUSE;
2165                 break;
2166         case (HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_TX |
2167                         HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_RX):
2168                 fc_conf->mode = RTE_FC_FULL;
2169                 break;
2170         }
2171         return 0;
2172 }
2173
2174 static int bnxt_flow_ctrl_set_op(struct rte_eth_dev *dev,
2175                                struct rte_eth_fc_conf *fc_conf)
2176 {
2177         struct bnxt *bp = dev->data->dev_private;
2178         int rc;
2179
2180         rc = is_bnxt_in_error(bp);
2181         if (rc)
2182                 return rc;
2183
2184         if (!BNXT_SINGLE_PF(bp) || BNXT_VF(bp)) {
2185                 PMD_DRV_LOG(ERR, "Flow Control Settings cannot be modified\n");
2186                 return -ENOTSUP;
2187         }
2188
2189         switch (fc_conf->mode) {
2190         case RTE_FC_NONE:
2191                 bp->link_info->auto_pause = 0;
2192                 bp->link_info->force_pause = 0;
2193                 break;
2194         case RTE_FC_RX_PAUSE:
2195                 if (fc_conf->autoneg) {
2196                         bp->link_info->auto_pause =
2197                                         HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_RX;
2198                         bp->link_info->force_pause = 0;
2199                 } else {
2200                         bp->link_info->auto_pause = 0;
2201                         bp->link_info->force_pause =
2202                                         HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_RX;
2203                 }
2204                 break;
2205         case RTE_FC_TX_PAUSE:
2206                 if (fc_conf->autoneg) {
2207                         bp->link_info->auto_pause =
2208                                         HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_TX;
2209                         bp->link_info->force_pause = 0;
2210                 } else {
2211                         bp->link_info->auto_pause = 0;
2212                         bp->link_info->force_pause =
2213                                         HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_TX;
2214                 }
2215                 break;
2216         case RTE_FC_FULL:
2217                 if (fc_conf->autoneg) {
2218                         bp->link_info->auto_pause =
2219                                         HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_TX |
2220                                         HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_RX;
2221                         bp->link_info->force_pause = 0;
2222                 } else {
2223                         bp->link_info->auto_pause = 0;
2224                         bp->link_info->force_pause =
2225                                         HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_TX |
2226                                         HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_RX;
2227                 }
2228                 break;
2229         }
2230         return bnxt_set_hwrm_link_config(bp, true);
2231 }
2232
2233 /* Add UDP tunneling port */
2234 static int
2235 bnxt_udp_tunnel_port_add_op(struct rte_eth_dev *eth_dev,
2236                          struct rte_eth_udp_tunnel *udp_tunnel)
2237 {
2238         struct bnxt *bp = eth_dev->data->dev_private;
2239         uint16_t tunnel_type = 0;
2240         int rc = 0;
2241
2242         rc = is_bnxt_in_error(bp);
2243         if (rc)
2244                 return rc;
2245
2246         switch (udp_tunnel->prot_type) {
2247         case RTE_TUNNEL_TYPE_VXLAN:
2248                 if (bp->vxlan_port_cnt) {
2249                         PMD_DRV_LOG(ERR, "Tunnel Port %d already programmed\n",
2250                                 udp_tunnel->udp_port);
2251                         if (bp->vxlan_port != udp_tunnel->udp_port) {
2252                                 PMD_DRV_LOG(ERR, "Only one port allowed\n");
2253                                 return -ENOSPC;
2254                         }
2255                         bp->vxlan_port_cnt++;
2256                         return 0;
2257                 }
2258                 tunnel_type =
2259                         HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_VXLAN;
2260                 bp->vxlan_port_cnt++;
2261                 break;
2262         case RTE_TUNNEL_TYPE_GENEVE:
2263                 if (bp->geneve_port_cnt) {
2264                         PMD_DRV_LOG(ERR, "Tunnel Port %d already programmed\n",
2265                                 udp_tunnel->udp_port);
2266                         if (bp->geneve_port != udp_tunnel->udp_port) {
2267                                 PMD_DRV_LOG(ERR, "Only one port allowed\n");
2268                                 return -ENOSPC;
2269                         }
2270                         bp->geneve_port_cnt++;
2271                         return 0;
2272                 }
2273                 tunnel_type =
2274                         HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_GENEVE;
2275                 bp->geneve_port_cnt++;
2276                 break;
2277         default:
2278                 PMD_DRV_LOG(ERR, "Tunnel type is not supported\n");
2279                 return -ENOTSUP;
2280         }
2281         rc = bnxt_hwrm_tunnel_dst_port_alloc(bp, udp_tunnel->udp_port,
2282                                              tunnel_type);
2283         return rc;
2284 }
2285
2286 static int
2287 bnxt_udp_tunnel_port_del_op(struct rte_eth_dev *eth_dev,
2288                          struct rte_eth_udp_tunnel *udp_tunnel)
2289 {
2290         struct bnxt *bp = eth_dev->data->dev_private;
2291         uint16_t tunnel_type = 0;
2292         uint16_t port = 0;
2293         int rc = 0;
2294
2295         rc = is_bnxt_in_error(bp);
2296         if (rc)
2297                 return rc;
2298
2299         switch (udp_tunnel->prot_type) {
2300         case RTE_TUNNEL_TYPE_VXLAN:
2301                 if (!bp->vxlan_port_cnt) {
2302                         PMD_DRV_LOG(ERR, "No Tunnel port configured yet\n");
2303                         return -EINVAL;
2304                 }
2305                 if (bp->vxlan_port != udp_tunnel->udp_port) {
2306                         PMD_DRV_LOG(ERR, "Req Port: %d. Configured port: %d\n",
2307                                 udp_tunnel->udp_port, bp->vxlan_port);
2308                         return -EINVAL;
2309                 }
2310                 if (--bp->vxlan_port_cnt)
2311                         return 0;
2312
2313                 tunnel_type =
2314                         HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN;
2315                 port = bp->vxlan_fw_dst_port_id;
2316                 break;
2317         case RTE_TUNNEL_TYPE_GENEVE:
2318                 if (!bp->geneve_port_cnt) {
2319                         PMD_DRV_LOG(ERR, "No Tunnel port configured yet\n");
2320                         return -EINVAL;
2321                 }
2322                 if (bp->geneve_port != udp_tunnel->udp_port) {
2323                         PMD_DRV_LOG(ERR, "Req Port: %d. Configured port: %d\n",
2324                                 udp_tunnel->udp_port, bp->geneve_port);
2325                         return -EINVAL;
2326                 }
2327                 if (--bp->geneve_port_cnt)
2328                         return 0;
2329
2330                 tunnel_type =
2331                         HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_GENEVE;
2332                 port = bp->geneve_fw_dst_port_id;
2333                 break;
2334         default:
2335                 PMD_DRV_LOG(ERR, "Tunnel type is not supported\n");
2336                 return -ENOTSUP;
2337         }
2338
2339         rc = bnxt_hwrm_tunnel_dst_port_free(bp, port, tunnel_type);
2340         return rc;
2341 }
2342
2343 static int bnxt_del_vlan_filter(struct bnxt *bp, uint16_t vlan_id)
2344 {
2345         struct bnxt_filter_info *filter;
2346         struct bnxt_vnic_info *vnic;
2347         int rc = 0;
2348         uint32_t chk = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN;
2349
2350         vnic = BNXT_GET_DEFAULT_VNIC(bp);
2351         filter = STAILQ_FIRST(&vnic->filter);
2352         while (filter) {
2353                 /* Search for this matching MAC+VLAN filter */
2354                 if (bnxt_vlan_filter_exists(bp, filter, chk, vlan_id)) {
2355                         /* Delete the filter */
2356                         rc = bnxt_hwrm_clear_l2_filter(bp, filter);
2357                         if (rc)
2358                                 return rc;
2359                         STAILQ_REMOVE(&vnic->filter, filter,
2360                                       bnxt_filter_info, next);
2361                         bnxt_free_filter(bp, filter);
2362                         PMD_DRV_LOG(INFO,
2363                                     "Deleted vlan filter for %d\n",
2364                                     vlan_id);
2365                         return 0;
2366                 }
2367                 filter = STAILQ_NEXT(filter, next);
2368         }
2369         return -ENOENT;
2370 }
2371
2372 static int bnxt_add_vlan_filter(struct bnxt *bp, uint16_t vlan_id)
2373 {
2374         struct bnxt_filter_info *filter;
2375         struct bnxt_vnic_info *vnic;
2376         int rc = 0;
2377         uint32_t en = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN |
2378                 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN_MASK;
2379         uint32_t chk = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN;
2380
2381         /* Implementation notes on the use of VNIC in this command:
2382          *
2383          * By default, these filters belong to default vnic for the function.
2384          * Once these filters are set up, only destination VNIC can be modified.
2385          * If the destination VNIC is not specified in this command,
2386          * then the HWRM shall only create an l2 context id.
2387          */
2388
2389         vnic = BNXT_GET_DEFAULT_VNIC(bp);
2390         filter = STAILQ_FIRST(&vnic->filter);
2391         /* Check if the VLAN has already been added */
2392         while (filter) {
2393                 if (bnxt_vlan_filter_exists(bp, filter, chk, vlan_id))
2394                         return -EEXIST;
2395
2396                 filter = STAILQ_NEXT(filter, next);
2397         }
2398
2399         /* No match found. Alloc a fresh filter and issue the L2_FILTER_ALLOC
2400          * command to create MAC+VLAN filter with the right flags, enables set.
2401          */
2402         filter = bnxt_alloc_filter(bp);
2403         if (!filter) {
2404                 PMD_DRV_LOG(ERR,
2405                             "MAC/VLAN filter alloc failed\n");
2406                 return -ENOMEM;
2407         }
2408         /* MAC + VLAN ID filter */
2409         /* If l2_ivlan == 0 and l2_ivlan_mask != 0, only
2410          * untagged packets are received
2411          *
2412          * If l2_ivlan != 0 and l2_ivlan_mask != 0, untagged
2413          * packets and only the programmed vlan's packets are received
2414          */
2415         filter->l2_ivlan = vlan_id;
2416         filter->l2_ivlan_mask = 0x0FFF;
2417         filter->enables |= en;
2418         filter->flags |= HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_OUTERMOST;
2419
2420         rc = bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id, filter);
2421         if (rc) {
2422                 /* Free the newly allocated filter as we were
2423                  * not able to create the filter in hardware.
2424                  */
2425                 bnxt_free_filter(bp, filter);
2426                 return rc;
2427         }
2428
2429         filter->mac_index = 0;
2430         /* Add this new filter to the list */
2431         if (vlan_id == 0)
2432                 STAILQ_INSERT_HEAD(&vnic->filter, filter, next);
2433         else
2434                 STAILQ_INSERT_TAIL(&vnic->filter, filter, next);
2435
2436         PMD_DRV_LOG(INFO,
2437                     "Added Vlan filter for %d\n", vlan_id);
2438         return rc;
2439 }
2440
2441 static int bnxt_vlan_filter_set_op(struct rte_eth_dev *eth_dev,
2442                 uint16_t vlan_id, int on)
2443 {
2444         struct bnxt *bp = eth_dev->data->dev_private;
2445         int rc;
2446
2447         rc = is_bnxt_in_error(bp);
2448         if (rc)
2449                 return rc;
2450
2451         if (!eth_dev->data->dev_started) {
2452                 PMD_DRV_LOG(ERR, "port must be started before setting vlan\n");
2453                 return -EINVAL;
2454         }
2455
2456         /* These operations apply to ALL existing MAC/VLAN filters */
2457         if (on)
2458                 return bnxt_add_vlan_filter(bp, vlan_id);
2459         else
2460                 return bnxt_del_vlan_filter(bp, vlan_id);
2461 }
2462
2463 static int bnxt_del_dflt_mac_filter(struct bnxt *bp,
2464                                     struct bnxt_vnic_info *vnic)
2465 {
2466         struct bnxt_filter_info *filter;
2467         int rc;
2468
2469         filter = STAILQ_FIRST(&vnic->filter);
2470         while (filter) {
2471                 if (filter->mac_index == 0 &&
2472                     !memcmp(filter->l2_addr, bp->mac_addr,
2473                             RTE_ETHER_ADDR_LEN)) {
2474                         rc = bnxt_hwrm_clear_l2_filter(bp, filter);
2475                         if (!rc) {
2476                                 STAILQ_REMOVE(&vnic->filter, filter,
2477                                               bnxt_filter_info, next);
2478                                 bnxt_free_filter(bp, filter);
2479                         }
2480                         return rc;
2481                 }
2482                 filter = STAILQ_NEXT(filter, next);
2483         }
2484         return 0;
2485 }
2486
2487 static int
2488 bnxt_config_vlan_hw_filter(struct bnxt *bp, uint64_t rx_offloads)
2489 {
2490         struct bnxt_vnic_info *vnic;
2491         unsigned int i;
2492         int rc;
2493
2494         vnic = BNXT_GET_DEFAULT_VNIC(bp);
2495         if (!(rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER)) {
2496                 /* Remove any VLAN filters programmed */
2497                 for (i = 0; i < RTE_ETHER_MAX_VLAN_ID; i++)
2498                         bnxt_del_vlan_filter(bp, i);
2499
2500                 rc = bnxt_add_mac_filter(bp, vnic, NULL, 0, 0);
2501                 if (rc)
2502                         return rc;
2503         } else {
2504                 /* Default filter will allow packets that match the
2505                  * dest mac. So, it has to be deleted, otherwise, we
2506                  * will endup receiving vlan packets for which the
2507                  * filter is not programmed, when hw-vlan-filter
2508                  * configuration is ON
2509                  */
2510                 bnxt_del_dflt_mac_filter(bp, vnic);
2511                 /* This filter will allow only untagged packets */
2512                 bnxt_add_vlan_filter(bp, 0);
2513         }
2514         PMD_DRV_LOG(DEBUG, "VLAN Filtering: %d\n",
2515                     !!(rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER));
2516
2517         return 0;
2518 }
2519
2520 static int bnxt_free_one_vnic(struct bnxt *bp, uint16_t vnic_id)
2521 {
2522         struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id];
2523         unsigned int i;
2524         int rc;
2525
2526         /* Destroy vnic filters and vnic */
2527         if (bp->eth_dev->data->dev_conf.rxmode.offloads &
2528             DEV_RX_OFFLOAD_VLAN_FILTER) {
2529                 for (i = 0; i < RTE_ETHER_MAX_VLAN_ID; i++)
2530                         bnxt_del_vlan_filter(bp, i);
2531         }
2532         bnxt_del_dflt_mac_filter(bp, vnic);
2533
2534         rc = bnxt_hwrm_vnic_ctx_free(bp, vnic);
2535         if (rc)
2536                 return rc;
2537
2538         rc = bnxt_hwrm_vnic_free(bp, vnic);
2539         if (rc)
2540                 return rc;
2541
2542         rte_free(vnic->fw_grp_ids);
2543         vnic->fw_grp_ids = NULL;
2544
2545         vnic->rx_queue_cnt = 0;
2546
2547         return 0;
2548 }
2549
2550 static int
2551 bnxt_config_vlan_hw_stripping(struct bnxt *bp, uint64_t rx_offloads)
2552 {
2553         struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp);
2554         int rc;
2555
2556         /* Destroy, recreate and reconfigure the default vnic */
2557         rc = bnxt_free_one_vnic(bp, 0);
2558         if (rc)
2559                 return rc;
2560
2561         /* default vnic 0 */
2562         rc = bnxt_setup_one_vnic(bp, 0);
2563         if (rc)
2564                 return rc;
2565
2566         if (bp->eth_dev->data->dev_conf.rxmode.offloads &
2567             DEV_RX_OFFLOAD_VLAN_FILTER) {
2568                 rc = bnxt_add_vlan_filter(bp, 0);
2569                 if (rc)
2570                         return rc;
2571                 rc = bnxt_restore_vlan_filters(bp);
2572                 if (rc)
2573                         return rc;
2574         } else {
2575                 rc = bnxt_add_mac_filter(bp, vnic, NULL, 0, 0);
2576                 if (rc)
2577                         return rc;
2578         }
2579
2580         rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
2581         if (rc)
2582                 return rc;
2583
2584         PMD_DRV_LOG(DEBUG, "VLAN Strip Offload: %d\n",
2585                     !!(rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP));
2586
2587         return rc;
2588 }
2589
2590 static int
2591 bnxt_vlan_offload_set_op(struct rte_eth_dev *dev, int mask)
2592 {
2593         uint64_t rx_offloads = dev->data->dev_conf.rxmode.offloads;
2594         struct bnxt *bp = dev->data->dev_private;
2595         int rc;
2596
2597         rc = is_bnxt_in_error(bp);
2598         if (rc)
2599                 return rc;
2600
2601         /* Filter settings will get applied when port is started */
2602         if (!dev->data->dev_started)
2603                 return 0;
2604
2605         if (mask & ETH_VLAN_FILTER_MASK) {
2606                 /* Enable or disable VLAN filtering */
2607                 rc = bnxt_config_vlan_hw_filter(bp, rx_offloads);
2608                 if (rc)
2609                         return rc;
2610         }
2611
2612         if (mask & ETH_VLAN_STRIP_MASK) {
2613                 /* Enable or disable VLAN stripping */
2614                 rc = bnxt_config_vlan_hw_stripping(bp, rx_offloads);
2615                 if (rc)
2616                         return rc;
2617         }
2618
2619         if (mask & ETH_VLAN_EXTEND_MASK) {
2620                 if (rx_offloads & DEV_RX_OFFLOAD_VLAN_EXTEND)
2621                         PMD_DRV_LOG(DEBUG, "Extend VLAN supported\n");
2622                 else
2623                         PMD_DRV_LOG(INFO, "Extend VLAN unsupported\n");
2624         }
2625
2626         return 0;
2627 }
2628
2629 static int
2630 bnxt_vlan_tpid_set_op(struct rte_eth_dev *dev, enum rte_vlan_type vlan_type,
2631                       uint16_t tpid)
2632 {
2633         struct bnxt *bp = dev->data->dev_private;
2634         int qinq = dev->data->dev_conf.rxmode.offloads &
2635                    DEV_RX_OFFLOAD_VLAN_EXTEND;
2636
2637         if (vlan_type != ETH_VLAN_TYPE_INNER &&
2638             vlan_type != ETH_VLAN_TYPE_OUTER) {
2639                 PMD_DRV_LOG(ERR,
2640                             "Unsupported vlan type.");
2641                 return -EINVAL;
2642         }
2643         if (!qinq) {
2644                 PMD_DRV_LOG(ERR,
2645                             "QinQ not enabled. Needs to be ON as we can "
2646                             "accelerate only outer vlan\n");
2647                 return -EINVAL;
2648         }
2649
2650         if (vlan_type == ETH_VLAN_TYPE_OUTER) {
2651                 switch (tpid) {
2652                 case RTE_ETHER_TYPE_QINQ:
2653                         bp->outer_tpid_bd =
2654                                 TX_BD_LONG_CFA_META_VLAN_TPID_TPID88A8;
2655                                 break;
2656                 case RTE_ETHER_TYPE_VLAN:
2657                         bp->outer_tpid_bd =
2658                                 TX_BD_LONG_CFA_META_VLAN_TPID_TPID8100;
2659                                 break;
2660                 case RTE_ETHER_TYPE_QINQ1:
2661                         bp->outer_tpid_bd =
2662                                 TX_BD_LONG_CFA_META_VLAN_TPID_TPID9100;
2663                                 break;
2664                 case RTE_ETHER_TYPE_QINQ2:
2665                         bp->outer_tpid_bd =
2666                                 TX_BD_LONG_CFA_META_VLAN_TPID_TPID9200;
2667                                 break;
2668                 case RTE_ETHER_TYPE_QINQ3:
2669                         bp->outer_tpid_bd =
2670                                  TX_BD_LONG_CFA_META_VLAN_TPID_TPID9300;
2671                                 break;
2672                 default:
2673                         PMD_DRV_LOG(ERR, "Invalid TPID: %x\n", tpid);
2674                         return -EINVAL;
2675                 }
2676                 bp->outer_tpid_bd |= tpid;
2677                 PMD_DRV_LOG(INFO, "outer_tpid_bd = %x\n", bp->outer_tpid_bd);
2678         } else if (vlan_type == ETH_VLAN_TYPE_INNER) {
2679                 PMD_DRV_LOG(ERR,
2680                             "Can accelerate only outer vlan in QinQ\n");
2681                 return -EINVAL;
2682         }
2683
2684         return 0;
2685 }
2686
2687 static int
2688 bnxt_set_default_mac_addr_op(struct rte_eth_dev *dev,
2689                              struct rte_ether_addr *addr)
2690 {
2691         struct bnxt *bp = dev->data->dev_private;
2692         /* Default Filter is tied to VNIC 0 */
2693         struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp);
2694         int rc;
2695
2696         rc = is_bnxt_in_error(bp);
2697         if (rc)
2698                 return rc;
2699
2700         if (BNXT_VF(bp) && !BNXT_VF_IS_TRUSTED(bp))
2701                 return -EPERM;
2702
2703         if (rte_is_zero_ether_addr(addr))
2704                 return -EINVAL;
2705
2706         /* Filter settings will get applied when port is started */
2707         if (!dev->data->dev_started)
2708                 return 0;
2709
2710         /* Check if the requested MAC is already added */
2711         if (memcmp(addr, bp->mac_addr, RTE_ETHER_ADDR_LEN) == 0)
2712                 return 0;
2713
2714         /* Destroy filter and re-create it */
2715         bnxt_del_dflt_mac_filter(bp, vnic);
2716
2717         memcpy(bp->mac_addr, addr, RTE_ETHER_ADDR_LEN);
2718         if (dev->data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_VLAN_FILTER) {
2719                 /* This filter will allow only untagged packets */
2720                 rc = bnxt_add_vlan_filter(bp, 0);
2721         } else {
2722                 rc = bnxt_add_mac_filter(bp, vnic, addr, 0, 0);
2723         }
2724
2725         PMD_DRV_LOG(DEBUG, "Set MAC addr\n");
2726         return rc;
2727 }
2728
2729 static int
2730 bnxt_dev_set_mc_addr_list_op(struct rte_eth_dev *eth_dev,
2731                           struct rte_ether_addr *mc_addr_set,
2732                           uint32_t nb_mc_addr)
2733 {
2734         struct bnxt *bp = eth_dev->data->dev_private;
2735         char *mc_addr_list = (char *)mc_addr_set;
2736         struct bnxt_vnic_info *vnic;
2737         uint32_t off = 0, i = 0;
2738         int rc;
2739
2740         rc = is_bnxt_in_error(bp);
2741         if (rc)
2742                 return rc;
2743
2744         vnic = BNXT_GET_DEFAULT_VNIC(bp);
2745
2746         if (nb_mc_addr > BNXT_MAX_MC_ADDRS) {
2747                 vnic->flags |= BNXT_VNIC_INFO_ALLMULTI;
2748                 goto allmulti;
2749         }
2750
2751         /* TODO Check for Duplicate mcast addresses */
2752         vnic->flags &= ~BNXT_VNIC_INFO_ALLMULTI;
2753         for (i = 0; i < nb_mc_addr; i++) {
2754                 memcpy(vnic->mc_list + off, &mc_addr_list[i],
2755                         RTE_ETHER_ADDR_LEN);
2756                 off += RTE_ETHER_ADDR_LEN;
2757         }
2758
2759         vnic->mc_addr_cnt = i;
2760         if (vnic->mc_addr_cnt)
2761                 vnic->flags |= BNXT_VNIC_INFO_MCAST;
2762         else
2763                 vnic->flags &= ~BNXT_VNIC_INFO_MCAST;
2764
2765 allmulti:
2766         return bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
2767 }
2768
2769 static int
2770 bnxt_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size)
2771 {
2772         struct bnxt *bp = dev->data->dev_private;
2773         uint8_t fw_major = (bp->fw_ver >> 24) & 0xff;
2774         uint8_t fw_minor = (bp->fw_ver >> 16) & 0xff;
2775         uint8_t fw_updt = (bp->fw_ver >> 8) & 0xff;
2776         uint8_t fw_rsvd = bp->fw_ver & 0xff;
2777         int ret;
2778
2779         ret = snprintf(fw_version, fw_size, "%d.%d.%d.%d",
2780                         fw_major, fw_minor, fw_updt, fw_rsvd);
2781
2782         ret += 1; /* add the size of '\0' */
2783         if (fw_size < (uint32_t)ret)
2784                 return ret;
2785         else
2786                 return 0;
2787 }
2788
2789 static void
2790 bnxt_rxq_info_get_op(struct rte_eth_dev *dev, uint16_t queue_id,
2791         struct rte_eth_rxq_info *qinfo)
2792 {
2793         struct bnxt *bp = dev->data->dev_private;
2794         struct bnxt_rx_queue *rxq;
2795
2796         if (is_bnxt_in_error(bp))
2797                 return;
2798
2799         rxq = dev->data->rx_queues[queue_id];
2800
2801         qinfo->mp = rxq->mb_pool;
2802         qinfo->scattered_rx = dev->data->scattered_rx;
2803         qinfo->nb_desc = rxq->nb_rx_desc;
2804
2805         qinfo->conf.rx_free_thresh = rxq->rx_free_thresh;
2806         qinfo->conf.rx_drop_en = rxq->drop_en;
2807         qinfo->conf.rx_deferred_start = rxq->rx_deferred_start;
2808         qinfo->conf.offloads = dev->data->dev_conf.rxmode.offloads;
2809 }
2810
2811 static void
2812 bnxt_txq_info_get_op(struct rte_eth_dev *dev, uint16_t queue_id,
2813         struct rte_eth_txq_info *qinfo)
2814 {
2815         struct bnxt *bp = dev->data->dev_private;
2816         struct bnxt_tx_queue *txq;
2817
2818         if (is_bnxt_in_error(bp))
2819                 return;
2820
2821         txq = dev->data->tx_queues[queue_id];
2822
2823         qinfo->nb_desc = txq->nb_tx_desc;
2824
2825         qinfo->conf.tx_thresh.pthresh = txq->pthresh;
2826         qinfo->conf.tx_thresh.hthresh = txq->hthresh;
2827         qinfo->conf.tx_thresh.wthresh = txq->wthresh;
2828
2829         qinfo->conf.tx_free_thresh = txq->tx_free_thresh;
2830         qinfo->conf.tx_rs_thresh = 0;
2831         qinfo->conf.tx_deferred_start = txq->tx_deferred_start;
2832         qinfo->conf.offloads = txq->offloads;
2833 }
2834
2835 static const struct {
2836         eth_rx_burst_t pkt_burst;
2837         const char *info;
2838 } bnxt_rx_burst_info[] = {
2839         {bnxt_recv_pkts,        "Scalar"},
2840 #if defined(RTE_ARCH_X86)
2841         {bnxt_recv_pkts_vec,    "Vector SSE"},
2842 #elif defined(RTE_ARCH_ARM64)
2843         {bnxt_recv_pkts_vec,    "Vector Neon"},
2844 #endif
2845 };
2846
2847 static int
2848 bnxt_rx_burst_mode_get(struct rte_eth_dev *dev, __rte_unused uint16_t queue_id,
2849                        struct rte_eth_burst_mode *mode)
2850 {
2851         eth_rx_burst_t pkt_burst = dev->rx_pkt_burst;
2852         size_t i;
2853
2854         for (i = 0; i < RTE_DIM(bnxt_rx_burst_info); i++) {
2855                 if (pkt_burst == bnxt_rx_burst_info[i].pkt_burst) {
2856                         snprintf(mode->info, sizeof(mode->info), "%s",
2857                                  bnxt_rx_burst_info[i].info);
2858                         return 0;
2859                 }
2860         }
2861
2862         return -EINVAL;
2863 }
2864
2865 static const struct {
2866         eth_tx_burst_t pkt_burst;
2867         const char *info;
2868 } bnxt_tx_burst_info[] = {
2869         {bnxt_xmit_pkts,        "Scalar"},
2870 #if defined(RTE_ARCH_X86)
2871         {bnxt_xmit_pkts_vec,    "Vector SSE"},
2872 #elif defined(RTE_ARCH_ARM64)
2873         {bnxt_xmit_pkts_vec,    "Vector Neon"},
2874 #endif
2875 };
2876
2877 static int
2878 bnxt_tx_burst_mode_get(struct rte_eth_dev *dev, __rte_unused uint16_t queue_id,
2879                        struct rte_eth_burst_mode *mode)
2880 {
2881         eth_tx_burst_t pkt_burst = dev->tx_pkt_burst;
2882         size_t i;
2883
2884         for (i = 0; i < RTE_DIM(bnxt_tx_burst_info); i++) {
2885                 if (pkt_burst == bnxt_tx_burst_info[i].pkt_burst) {
2886                         snprintf(mode->info, sizeof(mode->info), "%s",
2887                                  bnxt_tx_burst_info[i].info);
2888                         return 0;
2889                 }
2890         }
2891
2892         return -EINVAL;
2893 }
2894
2895 int bnxt_mtu_set_op(struct rte_eth_dev *eth_dev, uint16_t new_mtu)
2896 {
2897         struct bnxt *bp = eth_dev->data->dev_private;
2898         uint32_t new_pkt_size;
2899         uint32_t rc = 0;
2900         uint32_t i;
2901
2902         rc = is_bnxt_in_error(bp);
2903         if (rc)
2904                 return rc;
2905
2906         /* Exit if receive queues are not configured yet */
2907         if (!eth_dev->data->nb_rx_queues)
2908                 return rc;
2909
2910         new_pkt_size = new_mtu + RTE_ETHER_HDR_LEN + RTE_ETHER_CRC_LEN +
2911                        VLAN_TAG_SIZE * BNXT_NUM_VLANS;
2912
2913         /*
2914          * Disallow any MTU change that would require scattered receive support
2915          * if it is not already enabled.
2916          */
2917         if (eth_dev->data->dev_started &&
2918             !eth_dev->data->scattered_rx &&
2919             (new_pkt_size >
2920              eth_dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM)) {
2921                 PMD_DRV_LOG(ERR,
2922                             "MTU change would require scattered rx support. ");
2923                 PMD_DRV_LOG(ERR, "Stop port before changing MTU.\n");
2924                 return -EINVAL;
2925         }
2926
2927         if (new_mtu > RTE_ETHER_MTU) {
2928                 bp->flags |= BNXT_FLAG_JUMBO;
2929                 bp->eth_dev->data->dev_conf.rxmode.offloads |=
2930                         DEV_RX_OFFLOAD_JUMBO_FRAME;
2931         } else {
2932                 bp->eth_dev->data->dev_conf.rxmode.offloads &=
2933                         ~DEV_RX_OFFLOAD_JUMBO_FRAME;
2934                 bp->flags &= ~BNXT_FLAG_JUMBO;
2935         }
2936
2937         /* Is there a change in mtu setting? */
2938         if (eth_dev->data->dev_conf.rxmode.max_rx_pkt_len == new_pkt_size)
2939                 return rc;
2940
2941         for (i = 0; i < bp->nr_vnics; i++) {
2942                 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
2943                 uint16_t size = 0;
2944
2945                 vnic->mru = BNXT_VNIC_MRU(new_mtu);
2946                 rc = bnxt_hwrm_vnic_cfg(bp, vnic);
2947                 if (rc)
2948                         break;
2949
2950                 size = rte_pktmbuf_data_room_size(bp->rx_queues[0]->mb_pool);
2951                 size -= RTE_PKTMBUF_HEADROOM;
2952
2953                 if (size < new_mtu) {
2954                         rc = bnxt_hwrm_vnic_plcmode_cfg(bp, vnic);
2955                         if (rc)
2956                                 return rc;
2957                 }
2958         }
2959
2960         if (!rc)
2961                 eth_dev->data->dev_conf.rxmode.max_rx_pkt_len = new_pkt_size;
2962
2963         PMD_DRV_LOG(INFO, "New MTU is %d\n", new_mtu);
2964
2965         return rc;
2966 }
2967
2968 static int
2969 bnxt_vlan_pvid_set_op(struct rte_eth_dev *dev, uint16_t pvid, int on)
2970 {
2971         struct bnxt *bp = dev->data->dev_private;
2972         uint16_t vlan = bp->vlan;
2973         int rc;
2974
2975         rc = is_bnxt_in_error(bp);
2976         if (rc)
2977                 return rc;
2978
2979         if (!BNXT_SINGLE_PF(bp) || BNXT_VF(bp)) {
2980                 PMD_DRV_LOG(ERR,
2981                         "PVID cannot be modified for this function\n");
2982                 return -ENOTSUP;
2983         }
2984         bp->vlan = on ? pvid : 0;
2985
2986         rc = bnxt_hwrm_set_default_vlan(bp, 0, 0);
2987         if (rc)
2988                 bp->vlan = vlan;
2989         return rc;
2990 }
2991
2992 static int
2993 bnxt_dev_led_on_op(struct rte_eth_dev *dev)
2994 {
2995         struct bnxt *bp = dev->data->dev_private;
2996         int rc;
2997
2998         rc = is_bnxt_in_error(bp);
2999         if (rc)
3000                 return rc;
3001
3002         return bnxt_hwrm_port_led_cfg(bp, true);
3003 }
3004
3005 static int
3006 bnxt_dev_led_off_op(struct rte_eth_dev *dev)
3007 {
3008         struct bnxt *bp = dev->data->dev_private;
3009         int rc;
3010
3011         rc = is_bnxt_in_error(bp);
3012         if (rc)
3013                 return rc;
3014
3015         return bnxt_hwrm_port_led_cfg(bp, false);
3016 }
3017
3018 static uint32_t
3019 bnxt_rx_queue_count_op(struct rte_eth_dev *dev, uint16_t rx_queue_id)
3020 {
3021         struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
3022         struct bnxt_cp_ring_info *cpr;
3023         uint32_t desc = 0, raw_cons;
3024         struct bnxt_rx_queue *rxq;
3025         struct rx_pkt_cmpl *rxcmp;
3026         int rc;
3027
3028         rc = is_bnxt_in_error(bp);
3029         if (rc)
3030                 return rc;
3031
3032         rxq = dev->data->rx_queues[rx_queue_id];
3033         cpr = rxq->cp_ring;
3034         raw_cons = cpr->cp_raw_cons;
3035
3036         while (1) {
3037                 uint32_t agg_cnt, cons, cmpl_type;
3038
3039                 cons = RING_CMP(cpr->cp_ring_struct, raw_cons);
3040                 rxcmp = (struct rx_pkt_cmpl *)&cpr->cp_desc_ring[cons];
3041
3042                 if (!CMP_VALID(rxcmp, raw_cons, cpr->cp_ring_struct))
3043                         break;
3044
3045                 cmpl_type = CMP_TYPE(rxcmp);
3046
3047                 switch (cmpl_type) {
3048                 case CMPL_BASE_TYPE_RX_L2:
3049                 case CMPL_BASE_TYPE_RX_L2_V2:
3050                         agg_cnt = BNXT_RX_L2_AGG_BUFS(rxcmp);
3051                         raw_cons = raw_cons + CMP_LEN(cmpl_type) + agg_cnt;
3052                         desc++;
3053                         break;
3054
3055                 case CMPL_BASE_TYPE_RX_TPA_END:
3056                         if (BNXT_CHIP_P5(rxq->bp)) {
3057                                 struct rx_tpa_v2_end_cmpl_hi *p5_tpa_end;
3058
3059                                 p5_tpa_end = (void *)rxcmp;
3060                                 agg_cnt = BNXT_TPA_END_AGG_BUFS_TH(p5_tpa_end);
3061                         } else {
3062                                 struct rx_tpa_end_cmpl *tpa_end;
3063
3064                                 tpa_end = (void *)rxcmp;
3065                                 agg_cnt = BNXT_TPA_END_AGG_BUFS(tpa_end);
3066                         }
3067
3068                         raw_cons = raw_cons + CMP_LEN(cmpl_type) + agg_cnt;
3069                         desc++;
3070                         break;
3071
3072                 default:
3073                         raw_cons += CMP_LEN(cmpl_type);
3074                 }
3075         }
3076
3077         return desc;
3078 }
3079
3080 static int
3081 bnxt_rx_descriptor_status_op(void *rx_queue, uint16_t offset)
3082 {
3083         struct bnxt_rx_queue *rxq = rx_queue;
3084         struct bnxt_cp_ring_info *cpr;
3085         struct bnxt_rx_ring_info *rxr;
3086         uint32_t desc, raw_cons;
3087         struct bnxt *bp = rxq->bp;
3088         struct rx_pkt_cmpl *rxcmp;
3089         int rc;
3090
3091         rc = is_bnxt_in_error(bp);
3092         if (rc)
3093                 return rc;
3094
3095         if (offset >= rxq->nb_rx_desc)
3096                 return -EINVAL;
3097
3098         rxr = rxq->rx_ring;
3099         cpr = rxq->cp_ring;
3100
3101         /*
3102          * For the vector receive case, the completion at the requested
3103          * offset can be indexed directly.
3104          */
3105 #if defined(RTE_ARCH_X86) || defined(RTE_ARCH_ARM64)
3106         if (bp->flags & BNXT_FLAG_RX_VECTOR_PKT_MODE) {
3107                 struct rx_pkt_cmpl *rxcmp;
3108                 uint32_t cons;
3109
3110                 /* Check status of completion descriptor. */
3111                 raw_cons = cpr->cp_raw_cons +
3112                            offset * CMP_LEN(CMPL_BASE_TYPE_RX_L2);
3113                 cons = RING_CMP(cpr->cp_ring_struct, raw_cons);
3114                 rxcmp = (struct rx_pkt_cmpl *)&cpr->cp_desc_ring[cons];
3115
3116                 if (CMP_VALID(rxcmp, raw_cons, cpr->cp_ring_struct))
3117                         return RTE_ETH_RX_DESC_DONE;
3118
3119                 /* Check whether rx desc has an mbuf attached. */
3120                 cons = RING_CMP(rxr->rx_ring_struct, raw_cons / 2);
3121                 if (cons >= rxq->rxrearm_start &&
3122                     cons < rxq->rxrearm_start + rxq->rxrearm_nb) {
3123                         return RTE_ETH_RX_DESC_UNAVAIL;
3124                 }
3125
3126                 return RTE_ETH_RX_DESC_AVAIL;
3127         }
3128 #endif
3129
3130         /*
3131          * For the non-vector receive case, scan the completion ring to
3132          * locate the completion descriptor for the requested offset.
3133          */
3134         raw_cons = cpr->cp_raw_cons;
3135         desc = 0;
3136         while (1) {
3137                 uint32_t agg_cnt, cons, cmpl_type;
3138
3139                 cons = RING_CMP(cpr->cp_ring_struct, raw_cons);
3140                 rxcmp = (struct rx_pkt_cmpl *)&cpr->cp_desc_ring[cons];
3141
3142                 if (!CMP_VALID(rxcmp, raw_cons, cpr->cp_ring_struct))
3143                         break;
3144
3145                 cmpl_type = CMP_TYPE(rxcmp);
3146
3147                 switch (cmpl_type) {
3148                 case CMPL_BASE_TYPE_RX_L2:
3149                 case CMPL_BASE_TYPE_RX_L2_V2:
3150                         if (desc == offset) {
3151                                 cons = rxcmp->opaque;
3152                                 if (rxr->rx_buf_ring[cons])
3153                                         return RTE_ETH_RX_DESC_DONE;
3154                                 else
3155                                         return RTE_ETH_RX_DESC_UNAVAIL;
3156                         }
3157                         agg_cnt = BNXT_RX_L2_AGG_BUFS(rxcmp);
3158                         raw_cons = raw_cons + CMP_LEN(cmpl_type) + agg_cnt;
3159                         desc++;
3160                         break;
3161
3162                 case CMPL_BASE_TYPE_RX_TPA_END:
3163                         if (desc == offset)
3164                                 return RTE_ETH_RX_DESC_DONE;
3165
3166                         if (BNXT_CHIP_P5(rxq->bp)) {
3167                                 struct rx_tpa_v2_end_cmpl_hi *p5_tpa_end;
3168
3169                                 p5_tpa_end = (void *)rxcmp;
3170                                 agg_cnt = BNXT_TPA_END_AGG_BUFS_TH(p5_tpa_end);
3171                         } else {
3172                                 struct rx_tpa_end_cmpl *tpa_end;
3173
3174                                 tpa_end = (void *)rxcmp;
3175                                 agg_cnt = BNXT_TPA_END_AGG_BUFS(tpa_end);
3176                         }
3177
3178                         raw_cons = raw_cons + CMP_LEN(cmpl_type) + agg_cnt;
3179                         desc++;
3180                         break;
3181
3182                 default:
3183                         raw_cons += CMP_LEN(cmpl_type);
3184                 }
3185         }
3186
3187         return RTE_ETH_RX_DESC_AVAIL;
3188 }
3189
3190 static int
3191 bnxt_tx_descriptor_status_op(void *tx_queue, uint16_t offset)
3192 {
3193         struct bnxt_tx_queue *txq = (struct bnxt_tx_queue *)tx_queue;
3194         struct bnxt_tx_ring_info *txr;
3195         struct bnxt_cp_ring_info *cpr;
3196         struct rte_mbuf **tx_buf;
3197         struct tx_pkt_cmpl *txcmp;
3198         uint32_t cons, cp_cons;
3199         int rc;
3200
3201         if (!txq)
3202                 return -EINVAL;
3203
3204         rc = is_bnxt_in_error(txq->bp);
3205         if (rc)
3206                 return rc;
3207
3208         cpr = txq->cp_ring;
3209         txr = txq->tx_ring;
3210
3211         if (offset >= txq->nb_tx_desc)
3212                 return -EINVAL;
3213
3214         cons = RING_CMP(cpr->cp_ring_struct, offset);
3215         txcmp = (struct tx_pkt_cmpl *)&cpr->cp_desc_ring[cons];
3216         cp_cons = cpr->cp_raw_cons;
3217
3218         if (cons > cp_cons) {
3219                 if (CMPL_VALID(txcmp, cpr->valid))
3220                         return RTE_ETH_TX_DESC_UNAVAIL;
3221         } else {
3222                 if (CMPL_VALID(txcmp, !cpr->valid))
3223                         return RTE_ETH_TX_DESC_UNAVAIL;
3224         }
3225         tx_buf = &txr->tx_buf_ring[cons];
3226         if (*tx_buf == NULL)
3227                 return RTE_ETH_TX_DESC_DONE;
3228
3229         return RTE_ETH_TX_DESC_FULL;
3230 }
3231
3232 int
3233 bnxt_flow_ops_get_op(struct rte_eth_dev *dev,
3234                      const struct rte_flow_ops **ops)
3235 {
3236         struct bnxt *bp = dev->data->dev_private;
3237         int ret = 0;
3238
3239         if (!bp)
3240                 return -EIO;
3241
3242         if (BNXT_ETH_DEV_IS_REPRESENTOR(dev)) {
3243                 struct bnxt_representor *vfr = dev->data->dev_private;
3244                 bp = vfr->parent_dev->data->dev_private;
3245                 /* parent is deleted while children are still valid */
3246                 if (!bp) {
3247                         PMD_DRV_LOG(DEBUG, "BNXT Port:%d VFR Error\n",
3248                                     dev->data->port_id);
3249                         return -EIO;
3250                 }
3251         }
3252
3253         ret = is_bnxt_in_error(bp);
3254         if (ret)
3255                 return ret;
3256
3257         /* PMD supports thread-safe flow operations.  rte_flow API
3258          * functions can avoid mutex for multi-thread safety.
3259          */
3260         dev->data->dev_flags |= RTE_ETH_DEV_FLOW_OPS_THREAD_SAFE;
3261
3262         if (BNXT_TRUFLOW_EN(bp))
3263                 *ops = &bnxt_ulp_rte_flow_ops;
3264         else
3265                 *ops = &bnxt_flow_ops;
3266
3267         return ret;
3268 }
3269
3270 static const uint32_t *
3271 bnxt_dev_supported_ptypes_get_op(struct rte_eth_dev *dev)
3272 {
3273         static const uint32_t ptypes[] = {
3274                 RTE_PTYPE_L2_ETHER_VLAN,
3275                 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN,
3276                 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN,
3277                 RTE_PTYPE_L4_ICMP,
3278                 RTE_PTYPE_L4_TCP,
3279                 RTE_PTYPE_L4_UDP,
3280                 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN,
3281                 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN,
3282                 RTE_PTYPE_INNER_L4_ICMP,
3283                 RTE_PTYPE_INNER_L4_TCP,
3284                 RTE_PTYPE_INNER_L4_UDP,
3285                 RTE_PTYPE_UNKNOWN
3286         };
3287
3288         if (!dev->rx_pkt_burst)
3289                 return NULL;
3290
3291         return ptypes;
3292 }
3293
3294 static int bnxt_map_regs(struct bnxt *bp, uint32_t *reg_arr, int count,
3295                          int reg_win)
3296 {
3297         uint32_t reg_base = *reg_arr & 0xfffff000;
3298         uint32_t win_off;
3299         int i;
3300
3301         for (i = 0; i < count; i++) {
3302                 if ((reg_arr[i] & 0xfffff000) != reg_base)
3303                         return -ERANGE;
3304         }
3305         win_off = BNXT_GRCPF_REG_WINDOW_BASE_OUT + (reg_win - 1) * 4;
3306         rte_write32(reg_base, (uint8_t *)bp->bar0 + win_off);
3307         return 0;
3308 }
3309
3310 static int bnxt_map_ptp_regs(struct bnxt *bp)
3311 {
3312         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3313         uint32_t *reg_arr;
3314         int rc, i;
3315
3316         reg_arr = ptp->rx_regs;
3317         rc = bnxt_map_regs(bp, reg_arr, BNXT_PTP_RX_REGS, 5);
3318         if (rc)
3319                 return rc;
3320
3321         reg_arr = ptp->tx_regs;
3322         rc = bnxt_map_regs(bp, reg_arr, BNXT_PTP_TX_REGS, 6);
3323         if (rc)
3324                 return rc;
3325
3326         for (i = 0; i < BNXT_PTP_RX_REGS; i++)
3327                 ptp->rx_mapped_regs[i] = 0x5000 + (ptp->rx_regs[i] & 0xfff);
3328
3329         for (i = 0; i < BNXT_PTP_TX_REGS; i++)
3330                 ptp->tx_mapped_regs[i] = 0x6000 + (ptp->tx_regs[i] & 0xfff);
3331
3332         return 0;
3333 }
3334
3335 static void bnxt_unmap_ptp_regs(struct bnxt *bp)
3336 {
3337         rte_write32(0, (uint8_t *)bp->bar0 +
3338                          BNXT_GRCPF_REG_WINDOW_BASE_OUT + 16);
3339         rte_write32(0, (uint8_t *)bp->bar0 +
3340                          BNXT_GRCPF_REG_WINDOW_BASE_OUT + 20);
3341 }
3342
3343 static uint64_t bnxt_cc_read(struct bnxt *bp)
3344 {
3345         uint64_t ns;
3346
3347         ns = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3348                               BNXT_GRCPF_REG_SYNC_TIME));
3349         ns |= (uint64_t)(rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3350                                           BNXT_GRCPF_REG_SYNC_TIME + 4))) << 32;
3351         return ns;
3352 }
3353
3354 static int bnxt_get_tx_ts(struct bnxt *bp, uint64_t *ts)
3355 {
3356         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3357         uint32_t fifo;
3358
3359         fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3360                                 ptp->tx_mapped_regs[BNXT_PTP_TX_FIFO]));
3361         if (fifo & BNXT_PTP_TX_FIFO_EMPTY)
3362                 return -EAGAIN;
3363
3364         fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3365                                 ptp->tx_mapped_regs[BNXT_PTP_TX_FIFO]));
3366         *ts = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3367                                 ptp->tx_mapped_regs[BNXT_PTP_TX_TS_L]));
3368         *ts |= (uint64_t)rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3369                                 ptp->tx_mapped_regs[BNXT_PTP_TX_TS_H])) << 32;
3370         rte_read32((uint8_t *)bp->bar0 + ptp->tx_mapped_regs[BNXT_PTP_TX_SEQ]);
3371
3372         return 0;
3373 }
3374
3375 static int bnxt_get_rx_ts(struct bnxt *bp, uint64_t *ts)
3376 {
3377         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3378         struct bnxt_pf_info *pf = bp->pf;
3379         uint16_t port_id;
3380         uint32_t fifo;
3381
3382         fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3383                                 ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO]));
3384         if (!(fifo & BNXT_PTP_RX_FIFO_PENDING))
3385                 return -EAGAIN;
3386
3387         port_id = pf->port_id;
3388         rte_write32(1 << port_id, (uint8_t *)bp->bar0 +
3389                ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO_ADV]);
3390
3391         fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3392                                    ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO]));
3393         if (fifo & BNXT_PTP_RX_FIFO_PENDING) {
3394 /*              bnxt_clr_rx_ts(bp);       TBD  */
3395                 return -EBUSY;
3396         }
3397
3398         *ts = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3399                                 ptp->rx_mapped_regs[BNXT_PTP_RX_TS_L]));
3400         *ts |= (uint64_t)rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3401                                 ptp->rx_mapped_regs[BNXT_PTP_RX_TS_H])) << 32;
3402
3403         return 0;
3404 }
3405
3406 static int
3407 bnxt_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
3408 {
3409         uint64_t ns;
3410         struct bnxt *bp = dev->data->dev_private;
3411         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3412
3413         if (!ptp)
3414                 return -ENOTSUP;
3415
3416         ns = rte_timespec_to_ns(ts);
3417         /* Set the timecounters to a new value. */
3418         ptp->tc.nsec = ns;
3419         ptp->tx_tstamp_tc.nsec = ns;
3420         ptp->rx_tstamp_tc.nsec = ns;
3421
3422         return 0;
3423 }
3424
3425 static int
3426 bnxt_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
3427 {
3428         struct bnxt *bp = dev->data->dev_private;
3429         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3430         uint64_t ns, systime_cycles = 0;
3431         int rc = 0;
3432
3433         if (!ptp)
3434                 return -ENOTSUP;
3435
3436         if (BNXT_CHIP_P5(bp))
3437                 rc = bnxt_hwrm_port_ts_query(bp, BNXT_PTP_FLAGS_CURRENT_TIME,
3438                                              &systime_cycles);
3439         else
3440                 systime_cycles = bnxt_cc_read(bp);
3441
3442         ns = rte_timecounter_update(&ptp->tc, systime_cycles);
3443         *ts = rte_ns_to_timespec(ns);
3444
3445         return rc;
3446 }
3447 static int
3448 bnxt_timesync_enable(struct rte_eth_dev *dev)
3449 {
3450         struct bnxt *bp = dev->data->dev_private;
3451         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3452         uint32_t shift = 0;
3453         int rc;
3454
3455         if (!ptp)
3456                 return -ENOTSUP;
3457
3458         ptp->rx_filter = 1;
3459         ptp->tx_tstamp_en = 1;
3460         ptp->rxctl = BNXT_PTP_MSG_EVENTS;
3461
3462         rc = bnxt_hwrm_ptp_cfg(bp);
3463         if (rc)
3464                 return rc;
3465
3466         memset(&ptp->tc, 0, sizeof(struct rte_timecounter));
3467         memset(&ptp->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
3468         memset(&ptp->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
3469
3470         ptp->tc.cc_mask = BNXT_CYCLECOUNTER_MASK;
3471         ptp->tc.cc_shift = shift;
3472         ptp->tc.nsec_mask = (1ULL << shift) - 1;
3473
3474         ptp->rx_tstamp_tc.cc_mask = BNXT_CYCLECOUNTER_MASK;
3475         ptp->rx_tstamp_tc.cc_shift = shift;
3476         ptp->rx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
3477
3478         ptp->tx_tstamp_tc.cc_mask = BNXT_CYCLECOUNTER_MASK;
3479         ptp->tx_tstamp_tc.cc_shift = shift;
3480         ptp->tx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
3481
3482         if (!BNXT_CHIP_P5(bp))
3483                 bnxt_map_ptp_regs(bp);
3484         else
3485                 rc = bnxt_ptp_start(bp);
3486
3487         return rc;
3488 }
3489
3490 static int
3491 bnxt_timesync_disable(struct rte_eth_dev *dev)
3492 {
3493         struct bnxt *bp = dev->data->dev_private;
3494         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3495
3496         if (!ptp)
3497                 return -ENOTSUP;
3498
3499         ptp->rx_filter = 0;
3500         ptp->tx_tstamp_en = 0;
3501         ptp->rxctl = 0;
3502
3503         bnxt_hwrm_ptp_cfg(bp);
3504
3505         if (!BNXT_CHIP_P5(bp))
3506                 bnxt_unmap_ptp_regs(bp);
3507         else
3508                 bnxt_ptp_stop(bp);
3509
3510         return 0;
3511 }
3512
3513 static int
3514 bnxt_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
3515                                  struct timespec *timestamp,
3516                                  uint32_t flags __rte_unused)
3517 {
3518         struct bnxt *bp = dev->data->dev_private;
3519         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3520         uint64_t rx_tstamp_cycles = 0;
3521         uint64_t ns;
3522
3523         if (!ptp)
3524                 return -ENOTSUP;
3525
3526         if (BNXT_CHIP_P5(bp))
3527                 rx_tstamp_cycles = ptp->rx_timestamp;
3528         else
3529                 bnxt_get_rx_ts(bp, &rx_tstamp_cycles);
3530
3531         ns = rte_timecounter_update(&ptp->rx_tstamp_tc, rx_tstamp_cycles);
3532         *timestamp = rte_ns_to_timespec(ns);
3533         return  0;
3534 }
3535
3536 static int
3537 bnxt_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
3538                                  struct timespec *timestamp)
3539 {
3540         struct bnxt *bp = dev->data->dev_private;
3541         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3542         uint64_t tx_tstamp_cycles = 0;
3543         uint64_t ns;
3544         int rc = 0;
3545
3546         if (!ptp)
3547                 return -ENOTSUP;
3548
3549         if (BNXT_CHIP_P5(bp))
3550                 rc = bnxt_hwrm_port_ts_query(bp, BNXT_PTP_FLAGS_PATH_TX,
3551                                              &tx_tstamp_cycles);
3552         else
3553                 rc = bnxt_get_tx_ts(bp, &tx_tstamp_cycles);
3554
3555         ns = rte_timecounter_update(&ptp->tx_tstamp_tc, tx_tstamp_cycles);
3556         *timestamp = rte_ns_to_timespec(ns);
3557
3558         return rc;
3559 }
3560
3561 static int
3562 bnxt_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
3563 {
3564         struct bnxt *bp = dev->data->dev_private;
3565         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3566
3567         if (!ptp)
3568                 return -ENOTSUP;
3569
3570         ptp->tc.nsec += delta;
3571         ptp->tx_tstamp_tc.nsec += delta;
3572         ptp->rx_tstamp_tc.nsec += delta;
3573
3574         return 0;
3575 }
3576
3577 static int
3578 bnxt_get_eeprom_length_op(struct rte_eth_dev *dev)
3579 {
3580         struct bnxt *bp = dev->data->dev_private;
3581         int rc;
3582         uint32_t dir_entries;
3583         uint32_t entry_length;
3584
3585         rc = is_bnxt_in_error(bp);
3586         if (rc)
3587                 return rc;
3588
3589         PMD_DRV_LOG(INFO, PCI_PRI_FMT "\n",
3590                     bp->pdev->addr.domain, bp->pdev->addr.bus,
3591                     bp->pdev->addr.devid, bp->pdev->addr.function);
3592
3593         rc = bnxt_hwrm_nvm_get_dir_info(bp, &dir_entries, &entry_length);
3594         if (rc != 0)
3595                 return rc;
3596
3597         return dir_entries * entry_length;
3598 }
3599
3600 static int
3601 bnxt_get_eeprom_op(struct rte_eth_dev *dev,
3602                 struct rte_dev_eeprom_info *in_eeprom)
3603 {
3604         struct bnxt *bp = dev->data->dev_private;
3605         uint32_t index;
3606         uint32_t offset;
3607         int rc;
3608
3609         rc = is_bnxt_in_error(bp);
3610         if (rc)
3611                 return rc;
3612
3613         PMD_DRV_LOG(INFO, PCI_PRI_FMT " in_eeprom->offset = %d len = %d\n",
3614                     bp->pdev->addr.domain, bp->pdev->addr.bus,
3615                     bp->pdev->addr.devid, bp->pdev->addr.function,
3616                     in_eeprom->offset, in_eeprom->length);
3617
3618         if (in_eeprom->offset == 0) /* special offset value to get directory */
3619                 return bnxt_get_nvram_directory(bp, in_eeprom->length,
3620                                                 in_eeprom->data);
3621
3622         index = in_eeprom->offset >> 24;
3623         offset = in_eeprom->offset & 0xffffff;
3624
3625         if (index != 0)
3626                 return bnxt_hwrm_get_nvram_item(bp, index - 1, offset,
3627                                            in_eeprom->length, in_eeprom->data);
3628
3629         return 0;
3630 }
3631
3632 static bool bnxt_dir_type_is_ape_bin_format(uint16_t dir_type)
3633 {
3634         switch (dir_type) {
3635         case BNX_DIR_TYPE_CHIMP_PATCH:
3636         case BNX_DIR_TYPE_BOOTCODE:
3637         case BNX_DIR_TYPE_BOOTCODE_2:
3638         case BNX_DIR_TYPE_APE_FW:
3639         case BNX_DIR_TYPE_APE_PATCH:
3640         case BNX_DIR_TYPE_KONG_FW:
3641         case BNX_DIR_TYPE_KONG_PATCH:
3642         case BNX_DIR_TYPE_BONO_FW:
3643         case BNX_DIR_TYPE_BONO_PATCH:
3644                 /* FALLTHROUGH */
3645                 return true;
3646         }
3647
3648         return false;
3649 }
3650
3651 static bool bnxt_dir_type_is_other_exec_format(uint16_t dir_type)
3652 {
3653         switch (dir_type) {
3654         case BNX_DIR_TYPE_AVS:
3655         case BNX_DIR_TYPE_EXP_ROM_MBA:
3656         case BNX_DIR_TYPE_PCIE:
3657         case BNX_DIR_TYPE_TSCF_UCODE:
3658         case BNX_DIR_TYPE_EXT_PHY:
3659         case BNX_DIR_TYPE_CCM:
3660         case BNX_DIR_TYPE_ISCSI_BOOT:
3661         case BNX_DIR_TYPE_ISCSI_BOOT_IPV6:
3662         case BNX_DIR_TYPE_ISCSI_BOOT_IPV4N6:
3663                 /* FALLTHROUGH */
3664                 return true;
3665         }
3666
3667         return false;
3668 }
3669
3670 static bool bnxt_dir_type_is_executable(uint16_t dir_type)
3671 {
3672         return bnxt_dir_type_is_ape_bin_format(dir_type) ||
3673                 bnxt_dir_type_is_other_exec_format(dir_type);
3674 }
3675
3676 static int
3677 bnxt_set_eeprom_op(struct rte_eth_dev *dev,
3678                 struct rte_dev_eeprom_info *in_eeprom)
3679 {
3680         struct bnxt *bp = dev->data->dev_private;
3681         uint8_t index, dir_op;
3682         uint16_t type, ext, ordinal, attr;
3683         int rc;
3684
3685         rc = is_bnxt_in_error(bp);
3686         if (rc)
3687                 return rc;
3688
3689         PMD_DRV_LOG(INFO, PCI_PRI_FMT " in_eeprom->offset = %d len = %d\n",
3690                     bp->pdev->addr.domain, bp->pdev->addr.bus,
3691                     bp->pdev->addr.devid, bp->pdev->addr.function,
3692                     in_eeprom->offset, in_eeprom->length);
3693
3694         if (!BNXT_PF(bp)) {
3695                 PMD_DRV_LOG(ERR, "NVM write not supported from a VF\n");
3696                 return -EINVAL;
3697         }
3698
3699         type = in_eeprom->magic >> 16;
3700
3701         if (type == 0xffff) { /* special value for directory operations */
3702                 index = in_eeprom->magic & 0xff;
3703                 dir_op = in_eeprom->magic >> 8;
3704                 if (index == 0)
3705                         return -EINVAL;
3706                 switch (dir_op) {
3707                 case 0x0e: /* erase */
3708                         if (in_eeprom->offset != ~in_eeprom->magic)
3709                                 return -EINVAL;
3710                         return bnxt_hwrm_erase_nvram_directory(bp, index - 1);
3711                 default:
3712                         return -EINVAL;
3713                 }
3714         }
3715
3716         /* Create or re-write an NVM item: */
3717         if (bnxt_dir_type_is_executable(type) == true)
3718                 return -EOPNOTSUPP;
3719         ext = in_eeprom->magic & 0xffff;
3720         ordinal = in_eeprom->offset >> 16;
3721         attr = in_eeprom->offset & 0xffff;
3722
3723         return bnxt_hwrm_flash_nvram(bp, type, ordinal, ext, attr,
3724                                      in_eeprom->data, in_eeprom->length);
3725 }
3726
3727 /*
3728  * Initialization
3729  */
3730
3731 static const struct eth_dev_ops bnxt_dev_ops = {
3732         .dev_infos_get = bnxt_dev_info_get_op,
3733         .dev_close = bnxt_dev_close_op,
3734         .dev_configure = bnxt_dev_configure_op,
3735         .dev_start = bnxt_dev_start_op,
3736         .dev_stop = bnxt_dev_stop_op,
3737         .dev_set_link_up = bnxt_dev_set_link_up_op,
3738         .dev_set_link_down = bnxt_dev_set_link_down_op,
3739         .stats_get = bnxt_stats_get_op,
3740         .stats_reset = bnxt_stats_reset_op,
3741         .rx_queue_setup = bnxt_rx_queue_setup_op,
3742         .rx_queue_release = bnxt_rx_queue_release_op,
3743         .tx_queue_setup = bnxt_tx_queue_setup_op,
3744         .tx_queue_release = bnxt_tx_queue_release_op,
3745         .rx_queue_intr_enable = bnxt_rx_queue_intr_enable_op,
3746         .rx_queue_intr_disable = bnxt_rx_queue_intr_disable_op,
3747         .reta_update = bnxt_reta_update_op,
3748         .reta_query = bnxt_reta_query_op,
3749         .rss_hash_update = bnxt_rss_hash_update_op,
3750         .rss_hash_conf_get = bnxt_rss_hash_conf_get_op,
3751         .link_update = bnxt_link_update_op,
3752         .promiscuous_enable = bnxt_promiscuous_enable_op,
3753         .promiscuous_disable = bnxt_promiscuous_disable_op,
3754         .allmulticast_enable = bnxt_allmulticast_enable_op,
3755         .allmulticast_disable = bnxt_allmulticast_disable_op,
3756         .mac_addr_add = bnxt_mac_addr_add_op,
3757         .mac_addr_remove = bnxt_mac_addr_remove_op,
3758         .flow_ctrl_get = bnxt_flow_ctrl_get_op,
3759         .flow_ctrl_set = bnxt_flow_ctrl_set_op,
3760         .udp_tunnel_port_add  = bnxt_udp_tunnel_port_add_op,
3761         .udp_tunnel_port_del  = bnxt_udp_tunnel_port_del_op,
3762         .vlan_filter_set = bnxt_vlan_filter_set_op,
3763         .vlan_offload_set = bnxt_vlan_offload_set_op,
3764         .vlan_tpid_set = bnxt_vlan_tpid_set_op,
3765         .vlan_pvid_set = bnxt_vlan_pvid_set_op,
3766         .mtu_set = bnxt_mtu_set_op,
3767         .mac_addr_set = bnxt_set_default_mac_addr_op,
3768         .xstats_get = bnxt_dev_xstats_get_op,
3769         .xstats_get_names = bnxt_dev_xstats_get_names_op,
3770         .xstats_reset = bnxt_dev_xstats_reset_op,
3771         .fw_version_get = bnxt_fw_version_get,
3772         .set_mc_addr_list = bnxt_dev_set_mc_addr_list_op,
3773         .rxq_info_get = bnxt_rxq_info_get_op,
3774         .txq_info_get = bnxt_txq_info_get_op,
3775         .rx_burst_mode_get = bnxt_rx_burst_mode_get,
3776         .tx_burst_mode_get = bnxt_tx_burst_mode_get,
3777         .dev_led_on = bnxt_dev_led_on_op,
3778         .dev_led_off = bnxt_dev_led_off_op,
3779         .rx_queue_start = bnxt_rx_queue_start,
3780         .rx_queue_stop = bnxt_rx_queue_stop,
3781         .tx_queue_start = bnxt_tx_queue_start,
3782         .tx_queue_stop = bnxt_tx_queue_stop,
3783         .flow_ops_get = bnxt_flow_ops_get_op,
3784         .dev_supported_ptypes_get = bnxt_dev_supported_ptypes_get_op,
3785         .get_eeprom_length    = bnxt_get_eeprom_length_op,
3786         .get_eeprom           = bnxt_get_eeprom_op,
3787         .set_eeprom           = bnxt_set_eeprom_op,
3788         .timesync_enable      = bnxt_timesync_enable,
3789         .timesync_disable     = bnxt_timesync_disable,
3790         .timesync_read_time   = bnxt_timesync_read_time,
3791         .timesync_write_time   = bnxt_timesync_write_time,
3792         .timesync_adjust_time = bnxt_timesync_adjust_time,
3793         .timesync_read_rx_timestamp = bnxt_timesync_read_rx_timestamp,
3794         .timesync_read_tx_timestamp = bnxt_timesync_read_tx_timestamp,
3795 };
3796
3797 static uint32_t bnxt_map_reset_regs(struct bnxt *bp, uint32_t reg)
3798 {
3799         uint32_t offset;
3800
3801         /* Only pre-map the reset GRC registers using window 3 */
3802         rte_write32(reg & 0xfffff000, (uint8_t *)bp->bar0 +
3803                     BNXT_GRCPF_REG_WINDOW_BASE_OUT + 8);
3804
3805         offset = BNXT_GRCP_WINDOW_3_BASE + (reg & 0xffc);
3806
3807         return offset;
3808 }
3809
3810 int bnxt_map_fw_health_status_regs(struct bnxt *bp)
3811 {
3812         struct bnxt_error_recovery_info *info = bp->recovery_info;
3813         uint32_t reg_base = 0xffffffff;
3814         int i;
3815
3816         /* Only pre-map the monitoring GRC registers using window 2 */
3817         for (i = 0; i < BNXT_FW_STATUS_REG_CNT; i++) {
3818                 uint32_t reg = info->status_regs[i];
3819
3820                 if (BNXT_FW_STATUS_REG_TYPE(reg) != BNXT_FW_STATUS_REG_TYPE_GRC)
3821                         continue;
3822
3823                 if (reg_base == 0xffffffff)
3824                         reg_base = reg & 0xfffff000;
3825                 if ((reg & 0xfffff000) != reg_base)
3826                         return -ERANGE;
3827
3828                 /* Use mask 0xffc as the Lower 2 bits indicates
3829                  * address space location
3830                  */
3831                 info->mapped_status_regs[i] = BNXT_GRCP_WINDOW_2_BASE +
3832                                                 (reg & 0xffc);
3833         }
3834
3835         if (reg_base == 0xffffffff)
3836                 return 0;
3837
3838         rte_write32(reg_base, (uint8_t *)bp->bar0 +
3839                     BNXT_GRCPF_REG_WINDOW_BASE_OUT + 4);
3840
3841         return 0;
3842 }
3843
3844 static void bnxt_write_fw_reset_reg(struct bnxt *bp, uint32_t index)
3845 {
3846         struct bnxt_error_recovery_info *info = bp->recovery_info;
3847         uint32_t delay = info->delay_after_reset[index];
3848         uint32_t val = info->reset_reg_val[index];
3849         uint32_t reg = info->reset_reg[index];
3850         uint32_t type, offset;
3851         int ret;
3852
3853         type = BNXT_FW_STATUS_REG_TYPE(reg);
3854         offset = BNXT_FW_STATUS_REG_OFF(reg);
3855
3856         switch (type) {
3857         case BNXT_FW_STATUS_REG_TYPE_CFG:
3858                 ret = rte_pci_write_config(bp->pdev, &val, sizeof(val), offset);
3859                 if (ret < 0) {
3860                         PMD_DRV_LOG(ERR, "Failed to write %#x at PCI offset %#x",
3861                                     val, offset);
3862                         return;
3863                 }
3864                 break;
3865         case BNXT_FW_STATUS_REG_TYPE_GRC:
3866                 offset = bnxt_map_reset_regs(bp, offset);
3867                 rte_write32(val, (uint8_t *)bp->bar0 + offset);
3868                 break;
3869         case BNXT_FW_STATUS_REG_TYPE_BAR0:
3870                 rte_write32(val, (uint8_t *)bp->bar0 + offset);
3871                 break;
3872         }
3873         /* wait on a specific interval of time until core reset is complete */
3874         if (delay)
3875                 rte_delay_ms(delay);
3876 }
3877
3878 static void bnxt_dev_cleanup(struct bnxt *bp)
3879 {
3880         bp->eth_dev->data->dev_link.link_status = 0;
3881         bp->link_info->link_up = 0;
3882         if (bp->eth_dev->data->dev_started)
3883                 bnxt_dev_stop(bp->eth_dev);
3884
3885         bnxt_uninit_resources(bp, true);
3886 }
3887
3888 static int
3889 bnxt_check_fw_reset_done(struct bnxt *bp)
3890 {
3891         int timeout = bp->fw_reset_max_msecs;
3892         uint16_t val = 0;
3893         int rc;
3894
3895         do {
3896                 rc = rte_pci_read_config(bp->pdev, &val, sizeof(val), PCI_SUBSYSTEM_ID_OFFSET);
3897                 if (rc < 0) {
3898                         PMD_DRV_LOG(ERR, "Failed to read PCI offset 0x%x", PCI_SUBSYSTEM_ID_OFFSET);
3899                         return rc;
3900                 }
3901                 if (val != 0xffff)
3902                         break;
3903                 rte_delay_ms(1);
3904         } while (timeout--);
3905
3906         if (val == 0xffff) {
3907                 PMD_DRV_LOG(ERR, "Firmware reset aborted, PCI config space invalid\n");
3908                 return -1;
3909         }
3910
3911         return 0;
3912 }
3913
3914 static int bnxt_restore_vlan_filters(struct bnxt *bp)
3915 {
3916         struct rte_eth_dev *dev = bp->eth_dev;
3917         struct rte_vlan_filter_conf *vfc;
3918         int vidx, vbit, rc;
3919         uint16_t vlan_id;
3920
3921         for (vlan_id = 1; vlan_id <= RTE_ETHER_MAX_VLAN_ID; vlan_id++) {
3922                 vfc = &dev->data->vlan_filter_conf;
3923                 vidx = vlan_id / 64;
3924                 vbit = vlan_id % 64;
3925
3926                 /* Each bit corresponds to a VLAN id */
3927                 if (vfc->ids[vidx] & (UINT64_C(1) << vbit)) {
3928                         rc = bnxt_add_vlan_filter(bp, vlan_id);
3929                         if (rc)
3930                                 return rc;
3931                 }
3932         }
3933
3934         return 0;
3935 }
3936
3937 static int bnxt_restore_mac_filters(struct bnxt *bp)
3938 {
3939         struct rte_eth_dev *dev = bp->eth_dev;
3940         struct rte_eth_dev_info dev_info;
3941         struct rte_ether_addr *addr;
3942         uint64_t pool_mask;
3943         uint32_t pool = 0;
3944         uint16_t i;
3945         int rc;
3946
3947         if (BNXT_VF(bp) && !BNXT_VF_IS_TRUSTED(bp))
3948                 return 0;
3949
3950         rc = bnxt_dev_info_get_op(dev, &dev_info);
3951         if (rc)
3952                 return rc;
3953
3954         /* replay MAC address configuration */
3955         for (i = 1; i < dev_info.max_mac_addrs; i++) {
3956                 addr = &dev->data->mac_addrs[i];
3957
3958                 /* skip zero address */
3959                 if (rte_is_zero_ether_addr(addr))
3960                         continue;
3961
3962                 pool = 0;
3963                 pool_mask = dev->data->mac_pool_sel[i];
3964
3965                 do {
3966                         if (pool_mask & 1ULL) {
3967                                 rc = bnxt_mac_addr_add_op(dev, addr, i, pool);
3968                                 if (rc)
3969                                         return rc;
3970                         }
3971                         pool_mask >>= 1;
3972                         pool++;
3973                 } while (pool_mask);
3974         }
3975
3976         return 0;
3977 }
3978
3979 static int bnxt_restore_filters(struct bnxt *bp)
3980 {
3981         struct rte_eth_dev *dev = bp->eth_dev;
3982         int ret = 0;
3983
3984         if (dev->data->all_multicast) {
3985                 ret = bnxt_allmulticast_enable_op(dev);
3986                 if (ret)
3987                         return ret;
3988         }
3989         if (dev->data->promiscuous) {
3990                 ret = bnxt_promiscuous_enable_op(dev);
3991                 if (ret)
3992                         return ret;
3993         }
3994
3995         ret = bnxt_restore_mac_filters(bp);
3996         if (ret)
3997                 return ret;
3998
3999         ret = bnxt_restore_vlan_filters(bp);
4000         /* TODO restore other filters as well */
4001         return ret;
4002 }
4003
4004 static int bnxt_check_fw_ready(struct bnxt *bp)
4005 {
4006         int timeout = bp->fw_reset_max_msecs;
4007         int rc = 0;
4008
4009         do {
4010                 rc = bnxt_hwrm_poll_ver_get(bp);
4011                 if (rc == 0)
4012                         break;
4013                 rte_delay_ms(BNXT_FW_READY_WAIT_INTERVAL);
4014                 timeout -= BNXT_FW_READY_WAIT_INTERVAL;
4015         } while (rc && timeout > 0);
4016
4017         if (rc)
4018                 PMD_DRV_LOG(ERR, "FW is not Ready after reset\n");
4019
4020         return rc;
4021 }
4022
4023 static void bnxt_dev_recover(void *arg)
4024 {
4025         struct bnxt *bp = arg;
4026         int rc = 0;
4027
4028         pthread_mutex_lock(&bp->err_recovery_lock);
4029
4030         if (!bp->fw_reset_min_msecs) {
4031                 rc = bnxt_check_fw_reset_done(bp);
4032                 if (rc)
4033                         goto err;
4034         }
4035
4036         /* Clear Error flag so that device re-init should happen */
4037         bp->flags &= ~BNXT_FLAG_FATAL_ERROR;
4038
4039         rc = bnxt_check_fw_ready(bp);
4040         if (rc)
4041                 goto err;
4042
4043         rc = bnxt_init_resources(bp, true);
4044         if (rc) {
4045                 PMD_DRV_LOG(ERR,
4046                             "Failed to initialize resources after reset\n");
4047                 goto err;
4048         }
4049         /* clear reset flag as the device is initialized now */
4050         bp->flags &= ~BNXT_FLAG_FW_RESET;
4051
4052         rc = bnxt_dev_start_op(bp->eth_dev);
4053         if (rc) {
4054                 PMD_DRV_LOG(ERR, "Failed to start port after reset\n");
4055                 goto err_start;
4056         }
4057
4058         rc = bnxt_restore_filters(bp);
4059         if (rc)
4060                 goto err_start;
4061
4062         PMD_DRV_LOG(INFO, "Recovered from FW reset\n");
4063         pthread_mutex_unlock(&bp->err_recovery_lock);
4064
4065         return;
4066 err_start:
4067         bnxt_dev_stop(bp->eth_dev);
4068 err:
4069         bp->flags |= BNXT_FLAG_FATAL_ERROR;
4070         bnxt_uninit_resources(bp, false);
4071         pthread_mutex_unlock(&bp->err_recovery_lock);
4072         PMD_DRV_LOG(ERR, "Failed to recover from FW reset\n");
4073 }
4074
4075 void bnxt_dev_reset_and_resume(void *arg)
4076 {
4077         struct bnxt *bp = arg;
4078         uint32_t us = US_PER_MS * bp->fw_reset_min_msecs;
4079         uint16_t val = 0;
4080         int rc;
4081
4082         bnxt_dev_cleanup(bp);
4083
4084         bnxt_wait_for_device_shutdown(bp);
4085
4086         /* During some fatal firmware error conditions, the PCI config space
4087          * register 0x2e which normally contains the subsystem ID will become
4088          * 0xffff. This register will revert back to the normal value after
4089          * the chip has completed core reset. If we detect this condition,
4090          * we can poll this config register immediately for the value to revert.
4091          */
4092         if (bp->flags & BNXT_FLAG_FATAL_ERROR) {
4093                 rc = rte_pci_read_config(bp->pdev, &val, sizeof(val), PCI_SUBSYSTEM_ID_OFFSET);
4094                 if (rc < 0) {
4095                         PMD_DRV_LOG(ERR, "Failed to read PCI offset 0x%x", PCI_SUBSYSTEM_ID_OFFSET);
4096                         return;
4097                 }
4098                 if (val == 0xffff) {
4099                         bp->fw_reset_min_msecs = 0;
4100                         us = 1;
4101                 }
4102         }
4103
4104         rc = rte_eal_alarm_set(us, bnxt_dev_recover, (void *)bp);
4105         if (rc)
4106                 PMD_DRV_LOG(ERR, "Error setting recovery alarm");
4107 }
4108
4109 uint32_t bnxt_read_fw_status_reg(struct bnxt *bp, uint32_t index)
4110 {
4111         struct bnxt_error_recovery_info *info = bp->recovery_info;
4112         uint32_t reg = info->status_regs[index];
4113         uint32_t type, offset, val = 0;
4114
4115         type = BNXT_FW_STATUS_REG_TYPE(reg);
4116         offset = BNXT_FW_STATUS_REG_OFF(reg);
4117
4118         switch (type) {
4119         case BNXT_FW_STATUS_REG_TYPE_CFG:
4120                 rte_pci_read_config(bp->pdev, &val, sizeof(val), offset);
4121                 break;
4122         case BNXT_FW_STATUS_REG_TYPE_GRC:
4123                 offset = info->mapped_status_regs[index];
4124                 /* FALLTHROUGH */
4125         case BNXT_FW_STATUS_REG_TYPE_BAR0:
4126                 val = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
4127                                        offset));
4128                 break;
4129         }
4130
4131         return val;
4132 }
4133
4134 static int bnxt_fw_reset_all(struct bnxt *bp)
4135 {
4136         struct bnxt_error_recovery_info *info = bp->recovery_info;
4137         uint32_t i;
4138         int rc = 0;
4139
4140         if (info->flags & BNXT_FLAG_ERROR_RECOVERY_HOST) {
4141                 /* Reset through master function driver */
4142                 for (i = 0; i < info->reg_array_cnt; i++)
4143                         bnxt_write_fw_reset_reg(bp, i);
4144                 /* Wait for time specified by FW after triggering reset */
4145                 rte_delay_ms(info->master_func_wait_period_after_reset);
4146         } else if (info->flags & BNXT_FLAG_ERROR_RECOVERY_CO_CPU) {
4147                 /* Reset with the help of Kong processor */
4148                 rc = bnxt_hwrm_fw_reset(bp);
4149                 if (rc)
4150                         PMD_DRV_LOG(ERR, "Failed to reset FW\n");
4151         }
4152
4153         return rc;
4154 }
4155
4156 static void bnxt_fw_reset_cb(void *arg)
4157 {
4158         struct bnxt *bp = arg;
4159         struct bnxt_error_recovery_info *info = bp->recovery_info;
4160         int rc = 0;
4161
4162         /* Only Master function can do FW reset */
4163         if (bnxt_is_master_func(bp) &&
4164             bnxt_is_recovery_enabled(bp)) {
4165                 rc = bnxt_fw_reset_all(bp);
4166                 if (rc) {
4167                         PMD_DRV_LOG(ERR, "Adapter recovery failed\n");
4168                         return;
4169                 }
4170         }
4171
4172         /* if recovery method is ERROR_RECOVERY_CO_CPU, KONG will send
4173          * EXCEPTION_FATAL_ASYNC event to all the functions
4174          * (including MASTER FUNC). After receiving this Async, all the active
4175          * drivers should treat this case as FW initiated recovery
4176          */
4177         if (info->flags & BNXT_FLAG_ERROR_RECOVERY_HOST) {
4178                 bp->fw_reset_min_msecs = BNXT_MIN_FW_READY_TIMEOUT;
4179                 bp->fw_reset_max_msecs = BNXT_MAX_FW_RESET_TIMEOUT;
4180
4181                 /* To recover from error */
4182                 rte_eal_alarm_set(US_PER_MS, bnxt_dev_reset_and_resume,
4183                                   (void *)bp);
4184         }
4185 }
4186
4187 /* Driver should poll FW heartbeat, reset_counter with the frequency
4188  * advertised by FW in HWRM_ERROR_RECOVERY_QCFG.
4189  * When the driver detects heartbeat stop or change in reset_counter,
4190  * it has to trigger a reset to recover from the error condition.
4191  * A “master PF” is the function who will have the privilege to
4192  * initiate the chimp reset. The master PF will be elected by the
4193  * firmware and will be notified through async message.
4194  */
4195 static void bnxt_check_fw_health(void *arg)
4196 {
4197         struct bnxt *bp = arg;
4198         struct bnxt_error_recovery_info *info = bp->recovery_info;
4199         uint32_t val = 0, wait_msec;
4200
4201         if (!info || !bnxt_is_recovery_enabled(bp) ||
4202             is_bnxt_in_error(bp))
4203                 return;
4204
4205         val = bnxt_read_fw_status_reg(bp, BNXT_FW_HEARTBEAT_CNT_REG);
4206         if (val == info->last_heart_beat)
4207                 goto reset;
4208
4209         info->last_heart_beat = val;
4210
4211         val = bnxt_read_fw_status_reg(bp, BNXT_FW_RECOVERY_CNT_REG);
4212         if (val != info->last_reset_counter)
4213                 goto reset;
4214
4215         info->last_reset_counter = val;
4216
4217         rte_eal_alarm_set(US_PER_MS * info->driver_polling_freq,
4218                           bnxt_check_fw_health, (void *)bp);
4219
4220         return;
4221 reset:
4222         /* Stop DMA to/from device */
4223         bp->flags |= BNXT_FLAG_FATAL_ERROR;
4224         bp->flags |= BNXT_FLAG_FW_RESET;
4225
4226         PMD_DRV_LOG(ERR, "Detected FW dead condition\n");
4227
4228         if (bnxt_is_master_func(bp))
4229                 wait_msec = info->master_func_wait_period;
4230         else
4231                 wait_msec = info->normal_func_wait_period;
4232
4233         rte_eal_alarm_set(US_PER_MS * wait_msec,
4234                           bnxt_fw_reset_cb, (void *)bp);
4235 }
4236
4237 void bnxt_schedule_fw_health_check(struct bnxt *bp)
4238 {
4239         uint32_t polling_freq;
4240
4241         pthread_mutex_lock(&bp->health_check_lock);
4242
4243         if (!bnxt_is_recovery_enabled(bp))
4244                 goto done;
4245
4246         if (bp->flags & BNXT_FLAG_FW_HEALTH_CHECK_SCHEDULED)
4247                 goto done;
4248
4249         polling_freq = bp->recovery_info->driver_polling_freq;
4250
4251         rte_eal_alarm_set(US_PER_MS * polling_freq,
4252                           bnxt_check_fw_health, (void *)bp);
4253         bp->flags |= BNXT_FLAG_FW_HEALTH_CHECK_SCHEDULED;
4254
4255 done:
4256         pthread_mutex_unlock(&bp->health_check_lock);
4257 }
4258
4259 static void bnxt_cancel_fw_health_check(struct bnxt *bp)
4260 {
4261         if (!bnxt_is_recovery_enabled(bp))
4262                 return;
4263
4264         rte_eal_alarm_cancel(bnxt_check_fw_health, (void *)bp);
4265         bp->flags &= ~BNXT_FLAG_FW_HEALTH_CHECK_SCHEDULED;
4266 }
4267
4268 static bool bnxt_vf_pciid(uint16_t device_id)
4269 {
4270         switch (device_id) {
4271         case BROADCOM_DEV_ID_57304_VF:
4272         case BROADCOM_DEV_ID_57406_VF:
4273         case BROADCOM_DEV_ID_5731X_VF:
4274         case BROADCOM_DEV_ID_5741X_VF:
4275         case BROADCOM_DEV_ID_57414_VF:
4276         case BROADCOM_DEV_ID_STRATUS_NIC_VF1:
4277         case BROADCOM_DEV_ID_STRATUS_NIC_VF2:
4278         case BROADCOM_DEV_ID_58802_VF:
4279         case BROADCOM_DEV_ID_57500_VF1:
4280         case BROADCOM_DEV_ID_57500_VF2:
4281         case BROADCOM_DEV_ID_58818_VF:
4282                 /* FALLTHROUGH */
4283                 return true;
4284         default:
4285                 return false;
4286         }
4287 }
4288
4289 /* Phase 5 device */
4290 static bool bnxt_p5_device(uint16_t device_id)
4291 {
4292         switch (device_id) {
4293         case BROADCOM_DEV_ID_57508:
4294         case BROADCOM_DEV_ID_57504:
4295         case BROADCOM_DEV_ID_57502:
4296         case BROADCOM_DEV_ID_57508_MF1:
4297         case BROADCOM_DEV_ID_57504_MF1:
4298         case BROADCOM_DEV_ID_57502_MF1:
4299         case BROADCOM_DEV_ID_57508_MF2:
4300         case BROADCOM_DEV_ID_57504_MF2:
4301         case BROADCOM_DEV_ID_57502_MF2:
4302         case BROADCOM_DEV_ID_57500_VF1:
4303         case BROADCOM_DEV_ID_57500_VF2:
4304         case BROADCOM_DEV_ID_58812:
4305         case BROADCOM_DEV_ID_58814:
4306         case BROADCOM_DEV_ID_58818:
4307         case BROADCOM_DEV_ID_58818_VF:
4308                 /* FALLTHROUGH */
4309                 return true;
4310         default:
4311                 return false;
4312         }
4313 }
4314
4315 bool bnxt_stratus_device(struct bnxt *bp)
4316 {
4317         uint16_t device_id = bp->pdev->id.device_id;
4318
4319         switch (device_id) {
4320         case BROADCOM_DEV_ID_STRATUS_NIC:
4321         case BROADCOM_DEV_ID_STRATUS_NIC_VF1:
4322         case BROADCOM_DEV_ID_STRATUS_NIC_VF2:
4323                 /* FALLTHROUGH */
4324                 return true;
4325         default:
4326                 return false;
4327         }
4328 }
4329
4330 static int bnxt_map_pci_bars(struct rte_eth_dev *eth_dev)
4331 {
4332         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
4333         struct bnxt *bp = eth_dev->data->dev_private;
4334
4335         /* enable device (incl. PCI PM wakeup), and bus-mastering */
4336         bp->bar0 = (void *)pci_dev->mem_resource[0].addr;
4337         bp->doorbell_base = (void *)pci_dev->mem_resource[2].addr;
4338         if (!bp->bar0 || !bp->doorbell_base) {
4339                 PMD_DRV_LOG(ERR, "Unable to access Hardware\n");
4340                 return -ENODEV;
4341         }
4342
4343         bp->eth_dev = eth_dev;
4344         bp->pdev = pci_dev;
4345
4346         return 0;
4347 }
4348
4349 static int bnxt_alloc_ctx_mem_blk(struct bnxt *bp,
4350                                   struct bnxt_ctx_pg_info *ctx_pg,
4351                                   uint32_t mem_size,
4352                                   const char *suffix,
4353                                   uint16_t idx)
4354 {
4355         struct bnxt_ring_mem_info *rmem = &ctx_pg->ring_mem;
4356         const struct rte_memzone *mz = NULL;
4357         char mz_name[RTE_MEMZONE_NAMESIZE];
4358         rte_iova_t mz_phys_addr;
4359         uint64_t valid_bits = 0;
4360         uint32_t sz;
4361         int i;
4362
4363         if (!mem_size)
4364                 return 0;
4365
4366         rmem->nr_pages = RTE_ALIGN_MUL_CEIL(mem_size, BNXT_PAGE_SIZE) /
4367                          BNXT_PAGE_SIZE;
4368         rmem->page_size = BNXT_PAGE_SIZE;
4369         rmem->pg_arr = ctx_pg->ctx_pg_arr;
4370         rmem->dma_arr = ctx_pg->ctx_dma_arr;
4371         rmem->flags = BNXT_RMEM_VALID_PTE_FLAG;
4372
4373         valid_bits = PTU_PTE_VALID;
4374
4375         if (rmem->nr_pages > 1) {
4376                 snprintf(mz_name, RTE_MEMZONE_NAMESIZE,
4377                          "bnxt_ctx_pg_tbl%s_%x_%d",
4378                          suffix, idx, bp->eth_dev->data->port_id);
4379                 mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0;
4380                 mz = rte_memzone_lookup(mz_name);
4381                 if (!mz) {
4382                         mz = rte_memzone_reserve_aligned(mz_name,
4383                                                 rmem->nr_pages * 8,
4384                                                 SOCKET_ID_ANY,
4385                                                 RTE_MEMZONE_2MB |
4386                                                 RTE_MEMZONE_SIZE_HINT_ONLY |
4387                                                 RTE_MEMZONE_IOVA_CONTIG,
4388                                                 BNXT_PAGE_SIZE);
4389                         if (mz == NULL)
4390                                 return -ENOMEM;
4391                 }
4392
4393                 memset(mz->addr, 0, mz->len);
4394                 mz_phys_addr = mz->iova;
4395
4396                 rmem->pg_tbl = mz->addr;
4397                 rmem->pg_tbl_map = mz_phys_addr;
4398                 rmem->pg_tbl_mz = mz;
4399         }
4400
4401         snprintf(mz_name, RTE_MEMZONE_NAMESIZE, "bnxt_ctx_%s_%x_%d",
4402                  suffix, idx, bp->eth_dev->data->port_id);
4403         mz = rte_memzone_lookup(mz_name);
4404         if (!mz) {
4405                 mz = rte_memzone_reserve_aligned(mz_name,
4406                                                  mem_size,
4407                                                  SOCKET_ID_ANY,
4408                                                  RTE_MEMZONE_1GB |
4409                                                  RTE_MEMZONE_SIZE_HINT_ONLY |
4410                                                  RTE_MEMZONE_IOVA_CONTIG,
4411                                                  BNXT_PAGE_SIZE);
4412                 if (mz == NULL)
4413                         return -ENOMEM;
4414         }
4415
4416         memset(mz->addr, 0, mz->len);
4417         mz_phys_addr = mz->iova;
4418
4419         for (sz = 0, i = 0; sz < mem_size; sz += BNXT_PAGE_SIZE, i++) {
4420                 rmem->pg_arr[i] = ((char *)mz->addr) + sz;
4421                 rmem->dma_arr[i] = mz_phys_addr + sz;
4422
4423                 if (rmem->nr_pages > 1) {
4424                         if (i == rmem->nr_pages - 2 &&
4425                             (rmem->flags & BNXT_RMEM_RING_PTE_FLAG))
4426                                 valid_bits |= PTU_PTE_NEXT_TO_LAST;
4427                         else if (i == rmem->nr_pages - 1 &&
4428                                  (rmem->flags & BNXT_RMEM_RING_PTE_FLAG))
4429                                 valid_bits |= PTU_PTE_LAST;
4430
4431                         rmem->pg_tbl[i] = rte_cpu_to_le_64(rmem->dma_arr[i] |
4432                                                            valid_bits);
4433                 }
4434         }
4435
4436         rmem->mz = mz;
4437         if (rmem->vmem_size)
4438                 rmem->vmem = (void **)mz->addr;
4439         rmem->dma_arr[0] = mz_phys_addr;
4440         return 0;
4441 }
4442
4443 static void bnxt_free_ctx_mem(struct bnxt *bp)
4444 {
4445         int i;
4446
4447         if (!bp->ctx || !(bp->ctx->flags & BNXT_CTX_FLAG_INITED))
4448                 return;
4449
4450         bp->ctx->flags &= ~BNXT_CTX_FLAG_INITED;
4451         rte_memzone_free(bp->ctx->qp_mem.ring_mem.mz);
4452         rte_memzone_free(bp->ctx->srq_mem.ring_mem.mz);
4453         rte_memzone_free(bp->ctx->cq_mem.ring_mem.mz);
4454         rte_memzone_free(bp->ctx->vnic_mem.ring_mem.mz);
4455         rte_memzone_free(bp->ctx->stat_mem.ring_mem.mz);
4456         rte_memzone_free(bp->ctx->qp_mem.ring_mem.pg_tbl_mz);
4457         rte_memzone_free(bp->ctx->srq_mem.ring_mem.pg_tbl_mz);
4458         rte_memzone_free(bp->ctx->cq_mem.ring_mem.pg_tbl_mz);
4459         rte_memzone_free(bp->ctx->vnic_mem.ring_mem.pg_tbl_mz);
4460         rte_memzone_free(bp->ctx->stat_mem.ring_mem.pg_tbl_mz);
4461
4462         for (i = 0; i < bp->ctx->tqm_fp_rings_count + 1; i++) {
4463                 if (bp->ctx->tqm_mem[i])
4464                         rte_memzone_free(bp->ctx->tqm_mem[i]->ring_mem.mz);
4465         }
4466
4467         rte_free(bp->ctx);
4468         bp->ctx = NULL;
4469 }
4470
4471 #define bnxt_roundup(x, y)   ((((x) + ((y) - 1)) / (y)) * (y))
4472
4473 #define min_t(type, x, y) ({                    \
4474         type __min1 = (x);                      \
4475         type __min2 = (y);                      \
4476         __min1 < __min2 ? __min1 : __min2; })
4477
4478 #define max_t(type, x, y) ({                    \
4479         type __max1 = (x);                      \
4480         type __max2 = (y);                      \
4481         __max1 > __max2 ? __max1 : __max2; })
4482
4483 #define clamp_t(type, _x, min, max)     min_t(type, max_t(type, _x, min), max)
4484
4485 int bnxt_alloc_ctx_mem(struct bnxt *bp)
4486 {
4487         struct bnxt_ctx_pg_info *ctx_pg;
4488         struct bnxt_ctx_mem_info *ctx;
4489         uint32_t mem_size, ena, entries;
4490         uint32_t entries_sp, min;
4491         int i, rc;
4492
4493         rc = bnxt_hwrm_func_backing_store_qcaps(bp);
4494         if (rc) {
4495                 PMD_DRV_LOG(ERR, "Query context mem capability failed\n");
4496                 return rc;
4497         }
4498         ctx = bp->ctx;
4499         if (!ctx || (ctx->flags & BNXT_CTX_FLAG_INITED))
4500                 return 0;
4501
4502         ctx_pg = &ctx->qp_mem;
4503         ctx_pg->entries = ctx->qp_min_qp1_entries + ctx->qp_max_l2_entries;
4504         if (ctx->qp_entry_size) {
4505                 mem_size = ctx->qp_entry_size * ctx_pg->entries;
4506                 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "qp_mem", 0);
4507                 if (rc)
4508                         return rc;
4509         }
4510
4511         ctx_pg = &ctx->srq_mem;
4512         ctx_pg->entries = ctx->srq_max_l2_entries;
4513         if (ctx->srq_entry_size) {
4514                 mem_size = ctx->srq_entry_size * ctx_pg->entries;
4515                 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "srq_mem", 0);
4516                 if (rc)
4517                         return rc;
4518         }
4519
4520         ctx_pg = &ctx->cq_mem;
4521         ctx_pg->entries = ctx->cq_max_l2_entries;
4522         if (ctx->cq_entry_size) {
4523                 mem_size = ctx->cq_entry_size * ctx_pg->entries;
4524                 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "cq_mem", 0);
4525                 if (rc)
4526                         return rc;
4527         }
4528
4529         ctx_pg = &ctx->vnic_mem;
4530         ctx_pg->entries = ctx->vnic_max_vnic_entries +
4531                 ctx->vnic_max_ring_table_entries;
4532         if (ctx->vnic_entry_size) {
4533                 mem_size = ctx->vnic_entry_size * ctx_pg->entries;
4534                 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "vnic_mem", 0);
4535                 if (rc)
4536                         return rc;
4537         }
4538
4539         ctx_pg = &ctx->stat_mem;
4540         ctx_pg->entries = ctx->stat_max_entries;
4541         if (ctx->stat_entry_size) {
4542                 mem_size = ctx->stat_entry_size * ctx_pg->entries;
4543                 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "stat_mem", 0);
4544                 if (rc)
4545                         return rc;
4546         }
4547
4548         min = ctx->tqm_min_entries_per_ring;
4549
4550         entries_sp = ctx->qp_max_l2_entries +
4551                      ctx->vnic_max_vnic_entries +
4552                      2 * ctx->qp_min_qp1_entries + min;
4553         entries_sp = bnxt_roundup(entries_sp, ctx->tqm_entries_multiple);
4554
4555         entries = ctx->qp_max_l2_entries + ctx->qp_min_qp1_entries;
4556         entries = bnxt_roundup(entries, ctx->tqm_entries_multiple);
4557         entries = clamp_t(uint32_t, entries, min,
4558                           ctx->tqm_max_entries_per_ring);
4559         for (i = 0, ena = 0; i < ctx->tqm_fp_rings_count + 1; i++) {
4560                 /* i=0 is for TQM_SP. i=1 to i=8 applies to RING0 to RING7.
4561                  * i > 8 is other ext rings.
4562                  */
4563                 ctx_pg = ctx->tqm_mem[i];
4564                 ctx_pg->entries = i ? entries : entries_sp;
4565                 if (ctx->tqm_entry_size) {
4566                         mem_size = ctx->tqm_entry_size * ctx_pg->entries;
4567                         rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size,
4568                                                     "tqm_mem", i);
4569                         if (rc)
4570                                 return rc;
4571                 }
4572                 if (i < BNXT_MAX_TQM_LEGACY_RINGS)
4573                         ena |= HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_SP << i;
4574                 else
4575                         ena |= HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_RING8;
4576         }
4577
4578         ena |= FUNC_BACKING_STORE_CFG_INPUT_DFLT_ENABLES;
4579         rc = bnxt_hwrm_func_backing_store_cfg(bp, ena);
4580         if (rc)
4581                 PMD_DRV_LOG(ERR,
4582                             "Failed to configure context mem: rc = %d\n", rc);
4583         else
4584                 ctx->flags |= BNXT_CTX_FLAG_INITED;
4585
4586         return rc;
4587 }
4588
4589 static int bnxt_alloc_stats_mem(struct bnxt *bp)
4590 {
4591         struct rte_pci_device *pci_dev = bp->pdev;
4592         char mz_name[RTE_MEMZONE_NAMESIZE];
4593         const struct rte_memzone *mz = NULL;
4594         uint32_t total_alloc_len;
4595         rte_iova_t mz_phys_addr;
4596
4597         if (pci_dev->id.device_id == BROADCOM_DEV_ID_NS2)
4598                 return 0;
4599
4600         snprintf(mz_name, RTE_MEMZONE_NAMESIZE,
4601                  "bnxt_" PCI_PRI_FMT "-%s", pci_dev->addr.domain,
4602                  pci_dev->addr.bus, pci_dev->addr.devid,
4603                  pci_dev->addr.function, "rx_port_stats");
4604         mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0;
4605         mz = rte_memzone_lookup(mz_name);
4606         total_alloc_len =
4607                 RTE_CACHE_LINE_ROUNDUP(sizeof(struct rx_port_stats) +
4608                                        sizeof(struct rx_port_stats_ext) + 512);
4609         if (!mz) {
4610                 mz = rte_memzone_reserve(mz_name, total_alloc_len,
4611                                          SOCKET_ID_ANY,
4612                                          RTE_MEMZONE_2MB |
4613                                          RTE_MEMZONE_SIZE_HINT_ONLY |
4614                                          RTE_MEMZONE_IOVA_CONTIG);
4615                 if (mz == NULL)
4616                         return -ENOMEM;
4617         }
4618         memset(mz->addr, 0, mz->len);
4619         mz_phys_addr = mz->iova;
4620
4621         bp->rx_mem_zone = (const void *)mz;
4622         bp->hw_rx_port_stats = mz->addr;
4623         bp->hw_rx_port_stats_map = mz_phys_addr;
4624
4625         snprintf(mz_name, RTE_MEMZONE_NAMESIZE,
4626                  "bnxt_" PCI_PRI_FMT "-%s", pci_dev->addr.domain,
4627                  pci_dev->addr.bus, pci_dev->addr.devid,
4628                  pci_dev->addr.function, "tx_port_stats");
4629         mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0;
4630         mz = rte_memzone_lookup(mz_name);
4631         total_alloc_len =
4632                 RTE_CACHE_LINE_ROUNDUP(sizeof(struct tx_port_stats) +
4633                                        sizeof(struct tx_port_stats_ext) + 512);
4634         if (!mz) {
4635                 mz = rte_memzone_reserve(mz_name,
4636                                          total_alloc_len,
4637                                          SOCKET_ID_ANY,
4638                                          RTE_MEMZONE_2MB |
4639                                          RTE_MEMZONE_SIZE_HINT_ONLY |
4640                                          RTE_MEMZONE_IOVA_CONTIG);
4641                 if (mz == NULL)
4642                         return -ENOMEM;
4643         }
4644         memset(mz->addr, 0, mz->len);
4645         mz_phys_addr = mz->iova;
4646
4647         bp->tx_mem_zone = (const void *)mz;
4648         bp->hw_tx_port_stats = mz->addr;
4649         bp->hw_tx_port_stats_map = mz_phys_addr;
4650         bp->flags |= BNXT_FLAG_PORT_STATS;
4651
4652         /* Display extended statistics if FW supports it */
4653         if (bp->hwrm_spec_code < HWRM_SPEC_CODE_1_8_4 ||
4654             bp->hwrm_spec_code == HWRM_SPEC_CODE_1_9_0 ||
4655             !(bp->flags & BNXT_FLAG_EXT_STATS_SUPPORTED))
4656                 return 0;
4657
4658         bp->hw_rx_port_stats_ext = (void *)
4659                 ((uint8_t *)bp->hw_rx_port_stats +
4660                  sizeof(struct rx_port_stats));
4661         bp->hw_rx_port_stats_ext_map = bp->hw_rx_port_stats_map +
4662                 sizeof(struct rx_port_stats);
4663         bp->flags |= BNXT_FLAG_EXT_RX_PORT_STATS;
4664
4665         if (bp->hwrm_spec_code < HWRM_SPEC_CODE_1_9_2 ||
4666             bp->flags & BNXT_FLAG_EXT_STATS_SUPPORTED) {
4667                 bp->hw_tx_port_stats_ext = (void *)
4668                         ((uint8_t *)bp->hw_tx_port_stats +
4669                          sizeof(struct tx_port_stats));
4670                 bp->hw_tx_port_stats_ext_map =
4671                         bp->hw_tx_port_stats_map +
4672                         sizeof(struct tx_port_stats);
4673                 bp->flags |= BNXT_FLAG_EXT_TX_PORT_STATS;
4674         }
4675
4676         return 0;
4677 }
4678
4679 static int bnxt_setup_mac_addr(struct rte_eth_dev *eth_dev)
4680 {
4681         struct bnxt *bp = eth_dev->data->dev_private;
4682         int rc = 0;
4683
4684         eth_dev->data->mac_addrs = rte_zmalloc("bnxt_mac_addr_tbl",
4685                                                RTE_ETHER_ADDR_LEN *
4686                                                bp->max_l2_ctx,
4687                                                0);
4688         if (eth_dev->data->mac_addrs == NULL) {
4689                 PMD_DRV_LOG(ERR, "Failed to alloc MAC addr tbl\n");
4690                 return -ENOMEM;
4691         }
4692
4693         if (!BNXT_HAS_DFLT_MAC_SET(bp)) {
4694                 if (BNXT_PF(bp))
4695                         return -EINVAL;
4696
4697                 /* Generate a random MAC address, if none was assigned by PF */
4698                 PMD_DRV_LOG(INFO, "VF MAC address not assigned by Host PF\n");
4699                 bnxt_eth_hw_addr_random(bp->mac_addr);
4700                 PMD_DRV_LOG(INFO,
4701                             "Assign random MAC:%02X:%02X:%02X:%02X:%02X:%02X\n",
4702                             bp->mac_addr[0], bp->mac_addr[1], bp->mac_addr[2],
4703                             bp->mac_addr[3], bp->mac_addr[4], bp->mac_addr[5]);
4704
4705                 rc = bnxt_hwrm_set_mac(bp);
4706                 if (rc)
4707                         return rc;
4708         }
4709
4710         /* Copy the permanent MAC from the FUNC_QCAPS response */
4711         memcpy(&eth_dev->data->mac_addrs[0], bp->mac_addr, RTE_ETHER_ADDR_LEN);
4712
4713         return rc;
4714 }
4715
4716 static int bnxt_restore_dflt_mac(struct bnxt *bp)
4717 {
4718         int rc = 0;
4719
4720         /* MAC is already configured in FW */
4721         if (BNXT_HAS_DFLT_MAC_SET(bp))
4722                 return 0;
4723
4724         /* Restore the old MAC configured */
4725         rc = bnxt_hwrm_set_mac(bp);
4726         if (rc)
4727                 PMD_DRV_LOG(ERR, "Failed to restore MAC address\n");
4728
4729         return rc;
4730 }
4731
4732 static void bnxt_config_vf_req_fwd(struct bnxt *bp)
4733 {
4734         if (!BNXT_PF(bp))
4735                 return;
4736
4737         memset(bp->pf->vf_req_fwd, 0, sizeof(bp->pf->vf_req_fwd));
4738
4739         if (!(bp->fw_cap & BNXT_FW_CAP_LINK_ADMIN))
4740                 BNXT_HWRM_CMD_TO_FORWARD(HWRM_PORT_PHY_QCFG);
4741         BNXT_HWRM_CMD_TO_FORWARD(HWRM_FUNC_CFG);
4742         BNXT_HWRM_CMD_TO_FORWARD(HWRM_FUNC_VF_CFG);
4743         BNXT_HWRM_CMD_TO_FORWARD(HWRM_CFA_L2_FILTER_ALLOC);
4744         BNXT_HWRM_CMD_TO_FORWARD(HWRM_OEM_CMD);
4745 }
4746
4747 uint16_t
4748 bnxt_get_svif(uint16_t port_id, bool func_svif,
4749               enum bnxt_ulp_intf_type type)
4750 {
4751         struct rte_eth_dev *eth_dev;
4752         struct bnxt *bp;
4753
4754         eth_dev = &rte_eth_devices[port_id];
4755         if (BNXT_ETH_DEV_IS_REPRESENTOR(eth_dev)) {
4756                 struct bnxt_representor *vfr = eth_dev->data->dev_private;
4757                 if (!vfr)
4758                         return 0;
4759
4760                 if (type == BNXT_ULP_INTF_TYPE_VF_REP)
4761                         return vfr->svif;
4762
4763                 eth_dev = vfr->parent_dev;
4764         }
4765
4766         bp = eth_dev->data->dev_private;
4767
4768         return func_svif ? bp->func_svif : bp->port_svif;
4769 }
4770
4771 uint16_t
4772 bnxt_get_vnic_id(uint16_t port, enum bnxt_ulp_intf_type type)
4773 {
4774         struct rte_eth_dev *eth_dev;
4775         struct bnxt_vnic_info *vnic;
4776         struct bnxt *bp;
4777
4778         eth_dev = &rte_eth_devices[port];
4779         if (BNXT_ETH_DEV_IS_REPRESENTOR(eth_dev)) {
4780                 struct bnxt_representor *vfr = eth_dev->data->dev_private;
4781                 if (!vfr)
4782                         return 0;
4783
4784                 if (type == BNXT_ULP_INTF_TYPE_VF_REP)
4785                         return vfr->dflt_vnic_id;
4786
4787                 eth_dev = vfr->parent_dev;
4788         }
4789
4790         bp = eth_dev->data->dev_private;
4791
4792         vnic = BNXT_GET_DEFAULT_VNIC(bp);
4793
4794         return vnic->fw_vnic_id;
4795 }
4796
4797 uint16_t
4798 bnxt_get_fw_func_id(uint16_t port, enum bnxt_ulp_intf_type type)
4799 {
4800         struct rte_eth_dev *eth_dev;
4801         struct bnxt *bp;
4802
4803         eth_dev = &rte_eth_devices[port];
4804         if (BNXT_ETH_DEV_IS_REPRESENTOR(eth_dev)) {
4805                 struct bnxt_representor *vfr = eth_dev->data->dev_private;
4806                 if (!vfr)
4807                         return 0;
4808
4809                 if (type == BNXT_ULP_INTF_TYPE_VF_REP)
4810                         return vfr->fw_fid;
4811
4812                 eth_dev = vfr->parent_dev;
4813         }
4814
4815         bp = eth_dev->data->dev_private;
4816
4817         return bp->fw_fid;
4818 }
4819
4820 enum bnxt_ulp_intf_type
4821 bnxt_get_interface_type(uint16_t port)
4822 {
4823         struct rte_eth_dev *eth_dev;
4824         struct bnxt *bp;
4825
4826         eth_dev = &rte_eth_devices[port];
4827         if (BNXT_ETH_DEV_IS_REPRESENTOR(eth_dev))
4828                 return BNXT_ULP_INTF_TYPE_VF_REP;
4829
4830         bp = eth_dev->data->dev_private;
4831         if (BNXT_PF(bp))
4832                 return BNXT_ULP_INTF_TYPE_PF;
4833         else if (BNXT_VF_IS_TRUSTED(bp))
4834                 return BNXT_ULP_INTF_TYPE_TRUSTED_VF;
4835         else if (BNXT_VF(bp))
4836                 return BNXT_ULP_INTF_TYPE_VF;
4837
4838         return BNXT_ULP_INTF_TYPE_INVALID;
4839 }
4840
4841 uint16_t
4842 bnxt_get_phy_port_id(uint16_t port_id)
4843 {
4844         struct bnxt_representor *vfr;
4845         struct rte_eth_dev *eth_dev;
4846         struct bnxt *bp;
4847
4848         eth_dev = &rte_eth_devices[port_id];
4849         if (BNXT_ETH_DEV_IS_REPRESENTOR(eth_dev)) {
4850                 vfr = eth_dev->data->dev_private;
4851                 if (!vfr)
4852                         return 0;
4853
4854                 eth_dev = vfr->parent_dev;
4855         }
4856
4857         bp = eth_dev->data->dev_private;
4858
4859         return BNXT_PF(bp) ? bp->pf->port_id : bp->parent->port_id;
4860 }
4861
4862 uint16_t
4863 bnxt_get_parif(uint16_t port_id, enum bnxt_ulp_intf_type type)
4864 {
4865         struct rte_eth_dev *eth_dev;
4866         struct bnxt *bp;
4867
4868         eth_dev = &rte_eth_devices[port_id];
4869         if (BNXT_ETH_DEV_IS_REPRESENTOR(eth_dev)) {
4870                 struct bnxt_representor *vfr = eth_dev->data->dev_private;
4871                 if (!vfr)
4872                         return 0;
4873
4874                 if (type == BNXT_ULP_INTF_TYPE_VF_REP)
4875                         return vfr->fw_fid - 1;
4876
4877                 eth_dev = vfr->parent_dev;
4878         }
4879
4880         bp = eth_dev->data->dev_private;
4881
4882         return BNXT_PF(bp) ? bp->fw_fid - 1 : bp->parent->fid - 1;
4883 }
4884
4885 uint16_t
4886 bnxt_get_vport(uint16_t port_id)
4887 {
4888         return (1 << bnxt_get_phy_port_id(port_id));
4889 }
4890
4891 static void bnxt_alloc_error_recovery_info(struct bnxt *bp)
4892 {
4893         struct bnxt_error_recovery_info *info = bp->recovery_info;
4894
4895         if (info) {
4896                 if (!(bp->fw_cap & BNXT_FW_CAP_HCOMM_FW_STATUS))
4897                         memset(info, 0, sizeof(*info));
4898                 return;
4899         }
4900
4901         if (!(bp->fw_cap & BNXT_FW_CAP_ERROR_RECOVERY))
4902                 return;
4903
4904         info = rte_zmalloc("bnxt_hwrm_error_recovery_qcfg",
4905                            sizeof(*info), 0);
4906         if (!info)
4907                 bp->fw_cap &= ~BNXT_FW_CAP_ERROR_RECOVERY;
4908
4909         bp->recovery_info = info;
4910 }
4911
4912 static void bnxt_check_fw_status(struct bnxt *bp)
4913 {
4914         uint32_t fw_status;
4915
4916         if (!(bp->recovery_info &&
4917               (bp->fw_cap & BNXT_FW_CAP_HCOMM_FW_STATUS)))
4918                 return;
4919
4920         fw_status = bnxt_read_fw_status_reg(bp, BNXT_FW_STATUS_REG);
4921         if (fw_status != BNXT_FW_STATUS_HEALTHY)
4922                 PMD_DRV_LOG(ERR, "Firmware not responding, status: %#x\n",
4923                             fw_status);
4924 }
4925
4926 static int bnxt_map_hcomm_fw_status_reg(struct bnxt *bp)
4927 {
4928         struct bnxt_error_recovery_info *info = bp->recovery_info;
4929         uint32_t status_loc;
4930         uint32_t sig_ver;
4931
4932         rte_write32(HCOMM_STATUS_STRUCT_LOC, (uint8_t *)bp->bar0 +
4933                     BNXT_GRCPF_REG_WINDOW_BASE_OUT + 4);
4934         sig_ver = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
4935                                    BNXT_GRCP_WINDOW_2_BASE +
4936                                    offsetof(struct hcomm_status,
4937                                             sig_ver)));
4938         /* If the signature is absent, then FW does not support this feature */
4939         if ((sig_ver & HCOMM_STATUS_SIGNATURE_MASK) !=
4940             HCOMM_STATUS_SIGNATURE_VAL)
4941                 return 0;
4942
4943         if (!info) {
4944                 info = rte_zmalloc("bnxt_hwrm_error_recovery_qcfg",
4945                                    sizeof(*info), 0);
4946                 if (!info)
4947                         return -ENOMEM;
4948                 bp->recovery_info = info;
4949         } else {
4950                 memset(info, 0, sizeof(*info));
4951         }
4952
4953         status_loc = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
4954                                       BNXT_GRCP_WINDOW_2_BASE +
4955                                       offsetof(struct hcomm_status,
4956                                                fw_status_loc)));
4957
4958         /* Only pre-map the FW health status GRC register */
4959         if (BNXT_FW_STATUS_REG_TYPE(status_loc) != BNXT_FW_STATUS_REG_TYPE_GRC)
4960                 return 0;
4961
4962         info->status_regs[BNXT_FW_STATUS_REG] = status_loc;
4963         info->mapped_status_regs[BNXT_FW_STATUS_REG] =
4964                 BNXT_GRCP_WINDOW_2_BASE + (status_loc & BNXT_GRCP_OFFSET_MASK);
4965
4966         rte_write32((status_loc & BNXT_GRCP_BASE_MASK), (uint8_t *)bp->bar0 +
4967                     BNXT_GRCPF_REG_WINDOW_BASE_OUT + 4);
4968
4969         bp->fw_cap |= BNXT_FW_CAP_HCOMM_FW_STATUS;
4970
4971         return 0;
4972 }
4973
4974 /* This function gets the FW version along with the
4975  * capabilities(MAX and current) of the function, vnic,
4976  * error recovery, phy and other chip related info
4977  */
4978 static int bnxt_get_config(struct bnxt *bp)
4979 {
4980         uint16_t mtu;
4981         int rc = 0;
4982
4983         bp->fw_cap = 0;
4984
4985         rc = bnxt_map_hcomm_fw_status_reg(bp);
4986         if (rc)
4987                 return rc;
4988
4989         rc = bnxt_hwrm_ver_get(bp, DFLT_HWRM_CMD_TIMEOUT);
4990         if (rc) {
4991                 bnxt_check_fw_status(bp);
4992                 return rc;
4993         }
4994
4995         rc = bnxt_hwrm_func_reset(bp);
4996         if (rc)
4997                 return -EIO;
4998
4999         rc = bnxt_hwrm_vnic_qcaps(bp);
5000         if (rc)
5001                 return rc;
5002
5003         rc = bnxt_hwrm_queue_qportcfg(bp);
5004         if (rc)
5005                 return rc;
5006
5007         /* Get the MAX capabilities for this function.
5008          * This function also allocates context memory for TQM rings and
5009          * informs the firmware about this allocated backing store memory.
5010          */
5011         rc = bnxt_hwrm_func_qcaps(bp);
5012         if (rc)
5013                 return rc;
5014
5015         rc = bnxt_hwrm_func_qcfg(bp, &mtu);
5016         if (rc)
5017                 return rc;
5018
5019         rc = bnxt_hwrm_cfa_adv_flow_mgmt_qcaps(bp);
5020         if (rc)
5021                 return rc;
5022
5023         bnxt_hwrm_port_mac_qcfg(bp);
5024
5025         bnxt_hwrm_parent_pf_qcfg(bp);
5026
5027         bnxt_hwrm_port_phy_qcaps(bp);
5028
5029         bnxt_alloc_error_recovery_info(bp);
5030         /* Get the adapter error recovery support info */
5031         rc = bnxt_hwrm_error_recovery_qcfg(bp);
5032         if (rc)
5033                 bp->fw_cap &= ~BNXT_FW_CAP_ERROR_RECOVERY;
5034
5035         bnxt_hwrm_port_led_qcaps(bp);
5036
5037         return 0;
5038 }
5039
5040 static int
5041 bnxt_init_locks(struct bnxt *bp)
5042 {
5043         int err;
5044
5045         err = pthread_mutex_init(&bp->flow_lock, NULL);
5046         if (err) {
5047                 PMD_DRV_LOG(ERR, "Unable to initialize flow_lock\n");
5048                 return err;
5049         }
5050
5051         err = pthread_mutex_init(&bp->def_cp_lock, NULL);
5052         if (err) {
5053                 PMD_DRV_LOG(ERR, "Unable to initialize def_cp_lock\n");
5054                 return err;
5055         }
5056
5057         err = pthread_mutex_init(&bp->health_check_lock, NULL);
5058         if (err) {
5059                 PMD_DRV_LOG(ERR, "Unable to initialize health_check_lock\n");
5060                 return err;
5061         }
5062
5063         err = pthread_mutex_init(&bp->err_recovery_lock, NULL);
5064         if (err)
5065                 PMD_DRV_LOG(ERR, "Unable to initialize err_recovery_lock\n");
5066
5067         return err;
5068 }
5069
5070 static int bnxt_init_resources(struct bnxt *bp, bool reconfig_dev)
5071 {
5072         int rc = 0;
5073
5074         rc = bnxt_get_config(bp);
5075         if (rc)
5076                 return rc;
5077
5078         if (!reconfig_dev) {
5079                 rc = bnxt_setup_mac_addr(bp->eth_dev);
5080                 if (rc)
5081                         return rc;
5082         } else {
5083                 rc = bnxt_restore_dflt_mac(bp);
5084                 if (rc)
5085                         return rc;
5086         }
5087
5088         bnxt_config_vf_req_fwd(bp);
5089
5090         rc = bnxt_hwrm_func_driver_register(bp);
5091         if (rc) {
5092                 PMD_DRV_LOG(ERR, "Failed to register driver");
5093                 return -EBUSY;
5094         }
5095
5096         if (BNXT_PF(bp)) {
5097                 if (bp->pdev->max_vfs) {
5098                         rc = bnxt_hwrm_allocate_vfs(bp, bp->pdev->max_vfs);
5099                         if (rc) {
5100                                 PMD_DRV_LOG(ERR, "Failed to allocate VFs\n");
5101                                 return rc;
5102                         }
5103                 } else {
5104                         rc = bnxt_hwrm_allocate_pf_only(bp);
5105                         if (rc) {
5106                                 PMD_DRV_LOG(ERR,
5107                                             "Failed to allocate PF resources");
5108                                 return rc;
5109                         }
5110                 }
5111         }
5112
5113         rc = bnxt_alloc_mem(bp, reconfig_dev);
5114         if (rc)
5115                 return rc;
5116
5117         rc = bnxt_setup_int(bp);
5118         if (rc)
5119                 return rc;
5120
5121         rc = bnxt_request_int(bp);
5122         if (rc)
5123                 return rc;
5124
5125         rc = bnxt_init_ctx_mem(bp);
5126         if (rc) {
5127                 PMD_DRV_LOG(ERR, "Failed to init adv_flow_counters\n");
5128                 return rc;
5129         }
5130
5131         return 0;
5132 }
5133
5134 static int
5135 bnxt_parse_devarg_truflow(__rte_unused const char *key,
5136                           const char *value, void *opaque_arg)
5137 {
5138         struct bnxt *bp = opaque_arg;
5139         unsigned long truflow;
5140         char *end = NULL;
5141
5142         if (!value || !opaque_arg) {
5143                 PMD_DRV_LOG(ERR,
5144                             "Invalid parameter passed to truflow devargs.\n");
5145                 return -EINVAL;
5146         }
5147
5148         truflow = strtoul(value, &end, 10);
5149         if (end == NULL || *end != '\0' ||
5150             (truflow == ULONG_MAX && errno == ERANGE)) {
5151                 PMD_DRV_LOG(ERR,
5152                             "Invalid parameter passed to truflow devargs.\n");
5153                 return -EINVAL;
5154         }
5155
5156         if (BNXT_DEVARG_TRUFLOW_INVALID(truflow)) {
5157                 PMD_DRV_LOG(ERR,
5158                             "Invalid value passed to truflow devargs.\n");
5159                 return -EINVAL;
5160         }
5161
5162         if (truflow) {
5163                 bp->flags |= BNXT_FLAG_TRUFLOW_EN;
5164                 PMD_DRV_LOG(INFO, "Host-based truflow feature enabled.\n");
5165         } else {
5166                 bp->flags &= ~BNXT_FLAG_TRUFLOW_EN;
5167                 PMD_DRV_LOG(INFO, "Host-based truflow feature disabled.\n");
5168         }
5169
5170         return 0;
5171 }
5172
5173 static int
5174 bnxt_parse_devarg_flow_xstat(__rte_unused const char *key,
5175                              const char *value, void *opaque_arg)
5176 {
5177         struct bnxt *bp = opaque_arg;
5178         unsigned long flow_xstat;
5179         char *end = NULL;
5180
5181         if (!value || !opaque_arg) {
5182                 PMD_DRV_LOG(ERR,
5183                             "Invalid parameter passed to flow_xstat devarg.\n");
5184                 return -EINVAL;
5185         }
5186
5187         flow_xstat = strtoul(value, &end, 10);
5188         if (end == NULL || *end != '\0' ||
5189             (flow_xstat == ULONG_MAX && errno == ERANGE)) {
5190                 PMD_DRV_LOG(ERR,
5191                             "Invalid parameter passed to flow_xstat devarg.\n");
5192                 return -EINVAL;
5193         }
5194
5195         if (BNXT_DEVARG_FLOW_XSTAT_INVALID(flow_xstat)) {
5196                 PMD_DRV_LOG(ERR,
5197                             "Invalid value passed to flow_xstat devarg.\n");
5198                 return -EINVAL;
5199         }
5200
5201         bp->flags |= BNXT_FLAG_FLOW_XSTATS_EN;
5202         if (BNXT_FLOW_XSTATS_EN(bp))
5203                 PMD_DRV_LOG(INFO, "flow_xstat feature enabled.\n");
5204
5205         return 0;
5206 }
5207
5208 static int
5209 bnxt_parse_devarg_max_num_kflows(__rte_unused const char *key,
5210                                         const char *value, void *opaque_arg)
5211 {
5212         struct bnxt *bp = opaque_arg;
5213         unsigned long max_num_kflows;
5214         char *end = NULL;
5215
5216         if (!value || !opaque_arg) {
5217                 PMD_DRV_LOG(ERR,
5218                         "Invalid parameter passed to max_num_kflows devarg.\n");
5219                 return -EINVAL;
5220         }
5221
5222         max_num_kflows = strtoul(value, &end, 10);
5223         if (end == NULL || *end != '\0' ||
5224                 (max_num_kflows == ULONG_MAX && errno == ERANGE)) {
5225                 PMD_DRV_LOG(ERR,
5226                         "Invalid parameter passed to max_num_kflows devarg.\n");
5227                 return -EINVAL;
5228         }
5229
5230         if (bnxt_devarg_max_num_kflow_invalid(max_num_kflows)) {
5231                 PMD_DRV_LOG(ERR,
5232                         "Invalid value passed to max_num_kflows devarg.\n");
5233                 return -EINVAL;
5234         }
5235
5236         bp->max_num_kflows = max_num_kflows;
5237         if (bp->max_num_kflows)
5238                 PMD_DRV_LOG(INFO, "max_num_kflows set as %ldK.\n",
5239                                 max_num_kflows);
5240
5241         return 0;
5242 }
5243
5244 static int
5245 bnxt_parse_devarg_rep_is_pf(__rte_unused const char *key,
5246                             const char *value, void *opaque_arg)
5247 {
5248         struct bnxt_representor *vfr_bp = opaque_arg;
5249         unsigned long rep_is_pf;
5250         char *end = NULL;
5251
5252         if (!value || !opaque_arg) {
5253                 PMD_DRV_LOG(ERR,
5254                             "Invalid parameter passed to rep_is_pf devargs.\n");
5255                 return -EINVAL;
5256         }
5257
5258         rep_is_pf = strtoul(value, &end, 10);
5259         if (end == NULL || *end != '\0' ||
5260             (rep_is_pf == ULONG_MAX && errno == ERANGE)) {
5261                 PMD_DRV_LOG(ERR,
5262                             "Invalid parameter passed to rep_is_pf devargs.\n");
5263                 return -EINVAL;
5264         }
5265
5266         if (BNXT_DEVARG_REP_IS_PF_INVALID(rep_is_pf)) {
5267                 PMD_DRV_LOG(ERR,
5268                             "Invalid value passed to rep_is_pf devargs.\n");
5269                 return -EINVAL;
5270         }
5271
5272         vfr_bp->flags |= rep_is_pf;
5273         if (BNXT_REP_PF(vfr_bp))
5274                 PMD_DRV_LOG(INFO, "PF representor\n");
5275         else
5276                 PMD_DRV_LOG(INFO, "VF representor\n");
5277
5278         return 0;
5279 }
5280
5281 static int
5282 bnxt_parse_devarg_rep_based_pf(__rte_unused const char *key,
5283                                const char *value, void *opaque_arg)
5284 {
5285         struct bnxt_representor *vfr_bp = opaque_arg;
5286         unsigned long rep_based_pf;
5287         char *end = NULL;
5288
5289         if (!value || !opaque_arg) {
5290                 PMD_DRV_LOG(ERR,
5291                             "Invalid parameter passed to rep_based_pf "
5292                             "devargs.\n");
5293                 return -EINVAL;
5294         }
5295
5296         rep_based_pf = strtoul(value, &end, 10);
5297         if (end == NULL || *end != '\0' ||
5298             (rep_based_pf == ULONG_MAX && errno == ERANGE)) {
5299                 PMD_DRV_LOG(ERR,
5300                             "Invalid parameter passed to rep_based_pf "
5301                             "devargs.\n");
5302                 return -EINVAL;
5303         }
5304
5305         if (BNXT_DEVARG_REP_BASED_PF_INVALID(rep_based_pf)) {
5306                 PMD_DRV_LOG(ERR,
5307                             "Invalid value passed to rep_based_pf devargs.\n");
5308                 return -EINVAL;
5309         }
5310
5311         vfr_bp->rep_based_pf = rep_based_pf;
5312         vfr_bp->flags |= BNXT_REP_BASED_PF_VALID;
5313
5314         PMD_DRV_LOG(INFO, "rep-based-pf = %d\n", vfr_bp->rep_based_pf);
5315
5316         return 0;
5317 }
5318
5319 static int
5320 bnxt_parse_devarg_rep_q_r2f(__rte_unused const char *key,
5321                             const char *value, void *opaque_arg)
5322 {
5323         struct bnxt_representor *vfr_bp = opaque_arg;
5324         unsigned long rep_q_r2f;
5325         char *end = NULL;
5326
5327         if (!value || !opaque_arg) {
5328                 PMD_DRV_LOG(ERR,
5329                             "Invalid parameter passed to rep_q_r2f "
5330                             "devargs.\n");
5331                 return -EINVAL;
5332         }
5333
5334         rep_q_r2f = strtoul(value, &end, 10);
5335         if (end == NULL || *end != '\0' ||
5336             (rep_q_r2f == ULONG_MAX && errno == ERANGE)) {
5337                 PMD_DRV_LOG(ERR,
5338                             "Invalid parameter passed to rep_q_r2f "
5339                             "devargs.\n");
5340                 return -EINVAL;
5341         }
5342
5343         if (BNXT_DEVARG_REP_Q_R2F_INVALID(rep_q_r2f)) {
5344                 PMD_DRV_LOG(ERR,
5345                             "Invalid value passed to rep_q_r2f devargs.\n");
5346                 return -EINVAL;
5347         }
5348
5349         vfr_bp->rep_q_r2f = rep_q_r2f;
5350         vfr_bp->flags |= BNXT_REP_Q_R2F_VALID;
5351         PMD_DRV_LOG(INFO, "rep-q-r2f = %d\n", vfr_bp->rep_q_r2f);
5352
5353         return 0;
5354 }
5355
5356 static int
5357 bnxt_parse_devarg_rep_q_f2r(__rte_unused const char *key,
5358                             const char *value, void *opaque_arg)
5359 {
5360         struct bnxt_representor *vfr_bp = opaque_arg;
5361         unsigned long rep_q_f2r;
5362         char *end = NULL;
5363
5364         if (!value || !opaque_arg) {
5365                 PMD_DRV_LOG(ERR,
5366                             "Invalid parameter passed to rep_q_f2r "
5367                             "devargs.\n");
5368                 return -EINVAL;
5369         }
5370
5371         rep_q_f2r = strtoul(value, &end, 10);
5372         if (end == NULL || *end != '\0' ||
5373             (rep_q_f2r == ULONG_MAX && errno == ERANGE)) {
5374                 PMD_DRV_LOG(ERR,
5375                             "Invalid parameter passed to rep_q_f2r "
5376                             "devargs.\n");
5377                 return -EINVAL;
5378         }
5379
5380         if (BNXT_DEVARG_REP_Q_F2R_INVALID(rep_q_f2r)) {
5381                 PMD_DRV_LOG(ERR,
5382                             "Invalid value passed to rep_q_f2r devargs.\n");
5383                 return -EINVAL;
5384         }
5385
5386         vfr_bp->rep_q_f2r = rep_q_f2r;
5387         vfr_bp->flags |= BNXT_REP_Q_F2R_VALID;
5388         PMD_DRV_LOG(INFO, "rep-q-f2r = %d\n", vfr_bp->rep_q_f2r);
5389
5390         return 0;
5391 }
5392
5393 static int
5394 bnxt_parse_devarg_rep_fc_r2f(__rte_unused const char *key,
5395                              const char *value, void *opaque_arg)
5396 {
5397         struct bnxt_representor *vfr_bp = opaque_arg;
5398         unsigned long rep_fc_r2f;
5399         char *end = NULL;
5400
5401         if (!value || !opaque_arg) {
5402                 PMD_DRV_LOG(ERR,
5403                             "Invalid parameter passed to rep_fc_r2f "
5404                             "devargs.\n");
5405                 return -EINVAL;
5406         }
5407
5408         rep_fc_r2f = strtoul(value, &end, 10);
5409         if (end == NULL || *end != '\0' ||
5410             (rep_fc_r2f == ULONG_MAX && errno == ERANGE)) {
5411                 PMD_DRV_LOG(ERR,
5412                             "Invalid parameter passed to rep_fc_r2f "
5413                             "devargs.\n");
5414                 return -EINVAL;
5415         }
5416
5417         if (BNXT_DEVARG_REP_FC_R2F_INVALID(rep_fc_r2f)) {
5418                 PMD_DRV_LOG(ERR,
5419                             "Invalid value passed to rep_fc_r2f devargs.\n");
5420                 return -EINVAL;
5421         }
5422
5423         vfr_bp->flags |= BNXT_REP_FC_R2F_VALID;
5424         vfr_bp->rep_fc_r2f = rep_fc_r2f;
5425         PMD_DRV_LOG(INFO, "rep-fc-r2f = %lu\n", rep_fc_r2f);
5426
5427         return 0;
5428 }
5429
5430 static int
5431 bnxt_parse_devarg_rep_fc_f2r(__rte_unused const char *key,
5432                              const char *value, void *opaque_arg)
5433 {
5434         struct bnxt_representor *vfr_bp = opaque_arg;
5435         unsigned long rep_fc_f2r;
5436         char *end = NULL;
5437
5438         if (!value || !opaque_arg) {
5439                 PMD_DRV_LOG(ERR,
5440                             "Invalid parameter passed to rep_fc_f2r "
5441                             "devargs.\n");
5442                 return -EINVAL;
5443         }
5444
5445         rep_fc_f2r = strtoul(value, &end, 10);
5446         if (end == NULL || *end != '\0' ||
5447             (rep_fc_f2r == ULONG_MAX && errno == ERANGE)) {
5448                 PMD_DRV_LOG(ERR,
5449                             "Invalid parameter passed to rep_fc_f2r "
5450                             "devargs.\n");
5451                 return -EINVAL;
5452         }
5453
5454         if (BNXT_DEVARG_REP_FC_F2R_INVALID(rep_fc_f2r)) {
5455                 PMD_DRV_LOG(ERR,
5456                             "Invalid value passed to rep_fc_f2r devargs.\n");
5457                 return -EINVAL;
5458         }
5459
5460         vfr_bp->flags |= BNXT_REP_FC_F2R_VALID;
5461         vfr_bp->rep_fc_f2r = rep_fc_f2r;
5462         PMD_DRV_LOG(INFO, "rep-fc-f2r = %lu\n", rep_fc_f2r);
5463
5464         return 0;
5465 }
5466
5467 static int
5468 bnxt_parse_dev_args(struct bnxt *bp, struct rte_devargs *devargs)
5469 {
5470         struct rte_kvargs *kvlist;
5471         int ret;
5472
5473         if (devargs == NULL)
5474                 return 0;
5475
5476         kvlist = rte_kvargs_parse(devargs->args, bnxt_dev_args);
5477         if (kvlist == NULL)
5478                 return -EINVAL;
5479
5480         /*
5481          * Handler for "truflow" devarg.
5482          * Invoked as for ex: "-a 0000:00:0d.0,host-based-truflow=1"
5483          */
5484         ret = rte_kvargs_process(kvlist, BNXT_DEVARG_TRUFLOW,
5485                                  bnxt_parse_devarg_truflow, bp);
5486         if (ret)
5487                 goto err;
5488
5489         /*
5490          * Handler for "flow_xstat" devarg.
5491          * Invoked as for ex: "-a 0000:00:0d.0,flow_xstat=1"
5492          */
5493         ret = rte_kvargs_process(kvlist, BNXT_DEVARG_FLOW_XSTAT,
5494                                  bnxt_parse_devarg_flow_xstat, bp);
5495         if (ret)
5496                 goto err;
5497
5498         /*
5499          * Handler for "max_num_kflows" devarg.
5500          * Invoked as for ex: "-a 000:00:0d.0,max_num_kflows=32"
5501          */
5502         ret = rte_kvargs_process(kvlist, BNXT_DEVARG_MAX_NUM_KFLOWS,
5503                                  bnxt_parse_devarg_max_num_kflows, bp);
5504         if (ret)
5505                 goto err;
5506
5507 err:
5508         rte_kvargs_free(kvlist);
5509         return ret;
5510 }
5511
5512 static int bnxt_alloc_switch_domain(struct bnxt *bp)
5513 {
5514         int rc = 0;
5515
5516         if (BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp)) {
5517                 rc = rte_eth_switch_domain_alloc(&bp->switch_domain_id);
5518                 if (rc)
5519                         PMD_DRV_LOG(ERR,
5520                                     "Failed to alloc switch domain: %d\n", rc);
5521                 else
5522                         PMD_DRV_LOG(INFO,
5523                                     "Switch domain allocated %d\n",
5524                                     bp->switch_domain_id);
5525         }
5526
5527         return rc;
5528 }
5529
5530 /* Allocate and initialize various fields in bnxt struct that
5531  * need to be allocated/destroyed only once in the lifetime of the driver
5532  */
5533 static int bnxt_drv_init(struct rte_eth_dev *eth_dev)
5534 {
5535         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
5536         struct bnxt *bp = eth_dev->data->dev_private;
5537         int rc = 0;
5538
5539         bp->flags &= ~BNXT_FLAG_RX_VECTOR_PKT_MODE;
5540
5541         if (bnxt_vf_pciid(pci_dev->id.device_id))
5542                 bp->flags |= BNXT_FLAG_VF;
5543
5544         if (bnxt_p5_device(pci_dev->id.device_id))
5545                 bp->flags |= BNXT_FLAG_CHIP_P5;
5546
5547         if (pci_dev->id.device_id == BROADCOM_DEV_ID_58802 ||
5548             pci_dev->id.device_id == BROADCOM_DEV_ID_58804 ||
5549             pci_dev->id.device_id == BROADCOM_DEV_ID_58808 ||
5550             pci_dev->id.device_id == BROADCOM_DEV_ID_58802_VF)
5551                 bp->flags |= BNXT_FLAG_STINGRAY;
5552
5553         if (BNXT_TRUFLOW_EN(bp)) {
5554                 /* extra mbuf field is required to store CFA code from mark */
5555                 static const struct rte_mbuf_dynfield bnxt_cfa_code_dynfield_desc = {
5556                         .name = RTE_PMD_BNXT_CFA_CODE_DYNFIELD_NAME,
5557                         .size = sizeof(bnxt_cfa_code_dynfield_t),
5558                         .align = __alignof__(bnxt_cfa_code_dynfield_t),
5559                 };
5560                 bnxt_cfa_code_dynfield_offset =
5561                         rte_mbuf_dynfield_register(&bnxt_cfa_code_dynfield_desc);
5562                 if (bnxt_cfa_code_dynfield_offset < 0) {
5563                         PMD_DRV_LOG(ERR,
5564                             "Failed to register mbuf field for TruFlow mark\n");
5565                         return -rte_errno;
5566                 }
5567         }
5568
5569         rc = bnxt_map_pci_bars(eth_dev);
5570         if (rc) {
5571                 PMD_DRV_LOG(ERR,
5572                             "Failed to initialize board rc: %x\n", rc);
5573                 return rc;
5574         }
5575
5576         rc = bnxt_alloc_pf_info(bp);
5577         if (rc)
5578                 return rc;
5579
5580         rc = bnxt_alloc_link_info(bp);
5581         if (rc)
5582                 return rc;
5583
5584         rc = bnxt_alloc_parent_info(bp);
5585         if (rc)
5586                 return rc;
5587
5588         rc = bnxt_alloc_hwrm_resources(bp);
5589         if (rc) {
5590                 PMD_DRV_LOG(ERR,
5591                             "Failed to allocate response buffer rc: %x\n", rc);
5592                 return rc;
5593         }
5594         rc = bnxt_alloc_leds_info(bp);
5595         if (rc)
5596                 return rc;
5597
5598         rc = bnxt_alloc_cos_queues(bp);
5599         if (rc)
5600                 return rc;
5601
5602         rc = bnxt_init_locks(bp);
5603         if (rc)
5604                 return rc;
5605
5606         rc = bnxt_alloc_switch_domain(bp);
5607         if (rc)
5608                 return rc;
5609
5610         return rc;
5611 }
5612
5613 static int
5614 bnxt_dev_init(struct rte_eth_dev *eth_dev, void *params __rte_unused)
5615 {
5616         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
5617         static int version_printed;
5618         struct bnxt *bp;
5619         int rc;
5620
5621         if (version_printed++ == 0)
5622                 PMD_DRV_LOG(INFO, "%s\n", bnxt_version);
5623
5624         eth_dev->dev_ops = &bnxt_dev_ops;
5625         eth_dev->rx_queue_count = bnxt_rx_queue_count_op;
5626         eth_dev->rx_descriptor_status = bnxt_rx_descriptor_status_op;
5627         eth_dev->tx_descriptor_status = bnxt_tx_descriptor_status_op;
5628         eth_dev->rx_pkt_burst = &bnxt_recv_pkts;
5629         eth_dev->tx_pkt_burst = &bnxt_xmit_pkts;
5630
5631         /*
5632          * For secondary processes, we don't initialise any further
5633          * as primary has already done this work.
5634          */
5635         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
5636                 return 0;
5637
5638         rte_eth_copy_pci_info(eth_dev, pci_dev);
5639         eth_dev->data->dev_flags |= RTE_ETH_DEV_AUTOFILL_QUEUE_XSTATS;
5640
5641         bp = eth_dev->data->dev_private;
5642
5643         /* Parse dev arguments passed on when starting the DPDK application. */
5644         rc = bnxt_parse_dev_args(bp, pci_dev->device.devargs);
5645         if (rc)
5646                 goto error_free;
5647
5648         rc = bnxt_drv_init(eth_dev);
5649         if (rc)
5650                 goto error_free;
5651
5652         rc = bnxt_init_resources(bp, false);
5653         if (rc)
5654                 goto error_free;
5655
5656         rc = bnxt_alloc_stats_mem(bp);
5657         if (rc)
5658                 goto error_free;
5659
5660         PMD_DRV_LOG(INFO,
5661                     DRV_MODULE_NAME "found at mem %" PRIX64 ", node addr %pM\n",
5662                     pci_dev->mem_resource[0].phys_addr,
5663                     pci_dev->mem_resource[0].addr);
5664
5665         return 0;
5666
5667 error_free:
5668         bnxt_dev_uninit(eth_dev);
5669         return rc;
5670 }
5671
5672
5673 static void bnxt_free_ctx_mem_buf(struct bnxt_ctx_mem_buf_info *ctx)
5674 {
5675         if (!ctx)
5676                 return;
5677
5678         if (ctx->va)
5679                 rte_free(ctx->va);
5680
5681         ctx->va = NULL;
5682         ctx->dma = RTE_BAD_IOVA;
5683         ctx->ctx_id = BNXT_CTX_VAL_INVAL;
5684 }
5685
5686 static void bnxt_unregister_fc_ctx_mem(struct bnxt *bp)
5687 {
5688         bnxt_hwrm_cfa_counter_cfg(bp, BNXT_DIR_RX,
5689                                   CFA_COUNTER_CFG_IN_COUNTER_TYPE_FC,
5690                                   bp->flow_stat->rx_fc_out_tbl.ctx_id,
5691                                   bp->flow_stat->max_fc,
5692                                   false);
5693
5694         bnxt_hwrm_cfa_counter_cfg(bp, BNXT_DIR_TX,
5695                                   CFA_COUNTER_CFG_IN_COUNTER_TYPE_FC,
5696                                   bp->flow_stat->tx_fc_out_tbl.ctx_id,
5697                                   bp->flow_stat->max_fc,
5698                                   false);
5699
5700         if (bp->flow_stat->rx_fc_in_tbl.ctx_id != BNXT_CTX_VAL_INVAL)
5701                 bnxt_hwrm_ctx_unrgtr(bp, bp->flow_stat->rx_fc_in_tbl.ctx_id);
5702         bp->flow_stat->rx_fc_in_tbl.ctx_id = BNXT_CTX_VAL_INVAL;
5703
5704         if (bp->flow_stat->rx_fc_out_tbl.ctx_id != BNXT_CTX_VAL_INVAL)
5705                 bnxt_hwrm_ctx_unrgtr(bp, bp->flow_stat->rx_fc_out_tbl.ctx_id);
5706         bp->flow_stat->rx_fc_out_tbl.ctx_id = BNXT_CTX_VAL_INVAL;
5707
5708         if (bp->flow_stat->tx_fc_in_tbl.ctx_id != BNXT_CTX_VAL_INVAL)
5709                 bnxt_hwrm_ctx_unrgtr(bp, bp->flow_stat->tx_fc_in_tbl.ctx_id);
5710         bp->flow_stat->tx_fc_in_tbl.ctx_id = BNXT_CTX_VAL_INVAL;
5711
5712         if (bp->flow_stat->tx_fc_out_tbl.ctx_id != BNXT_CTX_VAL_INVAL)
5713                 bnxt_hwrm_ctx_unrgtr(bp, bp->flow_stat->tx_fc_out_tbl.ctx_id);
5714         bp->flow_stat->tx_fc_out_tbl.ctx_id = BNXT_CTX_VAL_INVAL;
5715 }
5716
5717 static void bnxt_uninit_fc_ctx_mem(struct bnxt *bp)
5718 {
5719         bnxt_unregister_fc_ctx_mem(bp);
5720
5721         bnxt_free_ctx_mem_buf(&bp->flow_stat->rx_fc_in_tbl);
5722         bnxt_free_ctx_mem_buf(&bp->flow_stat->rx_fc_out_tbl);
5723         bnxt_free_ctx_mem_buf(&bp->flow_stat->tx_fc_in_tbl);
5724         bnxt_free_ctx_mem_buf(&bp->flow_stat->tx_fc_out_tbl);
5725 }
5726
5727 static void bnxt_uninit_ctx_mem(struct bnxt *bp)
5728 {
5729         if (BNXT_FLOW_XSTATS_EN(bp))
5730                 bnxt_uninit_fc_ctx_mem(bp);
5731 }
5732
5733 static void
5734 bnxt_free_error_recovery_info(struct bnxt *bp)
5735 {
5736         rte_free(bp->recovery_info);
5737         bp->recovery_info = NULL;
5738         bp->fw_cap &= ~BNXT_FW_CAP_ERROR_RECOVERY;
5739 }
5740
5741 static int
5742 bnxt_uninit_resources(struct bnxt *bp, bool reconfig_dev)
5743 {
5744         int rc;
5745
5746         bnxt_free_int(bp);
5747         bnxt_free_mem(bp, reconfig_dev);
5748
5749         bnxt_hwrm_func_buf_unrgtr(bp);
5750         rte_free(bp->pf->vf_req_buf);
5751
5752         rc = bnxt_hwrm_func_driver_unregister(bp, 0);
5753         bp->flags &= ~BNXT_FLAG_REGISTERED;
5754         bnxt_free_ctx_mem(bp);
5755         if (!reconfig_dev) {
5756                 bnxt_free_hwrm_resources(bp);
5757                 bnxt_free_error_recovery_info(bp);
5758         }
5759
5760         bnxt_uninit_ctx_mem(bp);
5761
5762         bnxt_free_flow_stats_info(bp);
5763         bnxt_free_rep_info(bp);
5764         rte_free(bp->ptp_cfg);
5765         bp->ptp_cfg = NULL;
5766         return rc;
5767 }
5768
5769 static int
5770 bnxt_dev_uninit(struct rte_eth_dev *eth_dev)
5771 {
5772         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
5773                 return -EPERM;
5774
5775         PMD_DRV_LOG(DEBUG, "Calling Device uninit\n");
5776
5777         if (eth_dev->state != RTE_ETH_DEV_UNUSED)
5778                 bnxt_dev_close_op(eth_dev);
5779
5780         return 0;
5781 }
5782
5783 static int bnxt_pci_remove_dev_with_reps(struct rte_eth_dev *eth_dev)
5784 {
5785         struct bnxt *bp = eth_dev->data->dev_private;
5786         struct rte_eth_dev *vf_rep_eth_dev;
5787         int ret = 0, i;
5788
5789         if (!bp)
5790                 return -EINVAL;
5791
5792         for (i = 0; i < bp->num_reps; i++) {
5793                 vf_rep_eth_dev = bp->rep_info[i].vfr_eth_dev;
5794                 if (!vf_rep_eth_dev)
5795                         continue;
5796                 PMD_DRV_LOG(DEBUG, "BNXT Port:%d VFR pci remove\n",
5797                             vf_rep_eth_dev->data->port_id);
5798                 rte_eth_dev_destroy(vf_rep_eth_dev, bnxt_representor_uninit);
5799         }
5800         PMD_DRV_LOG(DEBUG, "BNXT Port:%d pci remove\n",
5801                     eth_dev->data->port_id);
5802         ret = rte_eth_dev_destroy(eth_dev, bnxt_dev_uninit);
5803
5804         return ret;
5805 }
5806
5807 static void bnxt_free_rep_info(struct bnxt *bp)
5808 {
5809         rte_free(bp->rep_info);
5810         bp->rep_info = NULL;
5811         rte_free(bp->cfa_code_map);
5812         bp->cfa_code_map = NULL;
5813 }
5814
5815 static int bnxt_init_rep_info(struct bnxt *bp)
5816 {
5817         int i = 0, rc;
5818
5819         if (bp->rep_info)
5820                 return 0;
5821
5822         bp->rep_info = rte_zmalloc("bnxt_rep_info",
5823                                    sizeof(bp->rep_info[0]) * BNXT_MAX_VF_REPS,
5824                                    0);
5825         if (!bp->rep_info) {
5826                 PMD_DRV_LOG(ERR, "Failed to alloc memory for rep info\n");
5827                 return -ENOMEM;
5828         }
5829         bp->cfa_code_map = rte_zmalloc("bnxt_cfa_code_map",
5830                                        sizeof(*bp->cfa_code_map) *
5831                                        BNXT_MAX_CFA_CODE, 0);
5832         if (!bp->cfa_code_map) {
5833                 PMD_DRV_LOG(ERR, "Failed to alloc memory for cfa_code_map\n");
5834                 bnxt_free_rep_info(bp);
5835                 return -ENOMEM;
5836         }
5837
5838         for (i = 0; i < BNXT_MAX_CFA_CODE; i++)
5839                 bp->cfa_code_map[i] = BNXT_VF_IDX_INVALID;
5840
5841         rc = pthread_mutex_init(&bp->rep_info->vfr_lock, NULL);
5842         if (rc) {
5843                 PMD_DRV_LOG(ERR, "Unable to initialize vfr_lock\n");
5844                 bnxt_free_rep_info(bp);
5845                 return rc;
5846         }
5847
5848         rc = pthread_mutex_init(&bp->rep_info->vfr_start_lock, NULL);
5849         if (rc) {
5850                 PMD_DRV_LOG(ERR, "Unable to initialize vfr_start_lock\n");
5851                 bnxt_free_rep_info(bp);
5852                 return rc;
5853         }
5854
5855         return rc;
5856 }
5857
5858 static int bnxt_rep_port_probe(struct rte_pci_device *pci_dev,
5859                                struct rte_eth_devargs *eth_da,
5860                                struct rte_eth_dev *backing_eth_dev,
5861                                const char *dev_args)
5862 {
5863         struct rte_eth_dev *vf_rep_eth_dev;
5864         char name[RTE_ETH_NAME_MAX_LEN];
5865         struct bnxt *backing_bp;
5866         uint16_t num_rep;
5867         int i, ret = 0;
5868         struct rte_kvargs *kvlist = NULL;
5869
5870         if (eth_da->type == RTE_ETH_REPRESENTOR_NONE)
5871                 return 0;
5872         if (eth_da->type != RTE_ETH_REPRESENTOR_VF) {
5873                 PMD_DRV_LOG(ERR, "unsupported representor type %d\n",
5874                             eth_da->type);
5875                 return -ENOTSUP;
5876         }
5877         num_rep = eth_da->nb_representor_ports;
5878         if (num_rep > BNXT_MAX_VF_REPS) {
5879                 PMD_DRV_LOG(ERR, "nb_representor_ports = %d > %d MAX VF REPS\n",
5880                             num_rep, BNXT_MAX_VF_REPS);
5881                 return -EINVAL;
5882         }
5883
5884         if (num_rep >= RTE_MAX_ETHPORTS) {
5885                 PMD_DRV_LOG(ERR,
5886                             "nb_representor_ports = %d > %d MAX ETHPORTS\n",
5887                             num_rep, RTE_MAX_ETHPORTS);
5888                 return -EINVAL;
5889         }
5890
5891         backing_bp = backing_eth_dev->data->dev_private;
5892
5893         if (!(BNXT_PF(backing_bp) || BNXT_VF_IS_TRUSTED(backing_bp))) {
5894                 PMD_DRV_LOG(ERR,
5895                             "Not a PF or trusted VF. No Representor support\n");
5896                 /* Returning an error is not an option.
5897                  * Applications are not handling this correctly
5898                  */
5899                 return 0;
5900         }
5901
5902         if (bnxt_init_rep_info(backing_bp))
5903                 return 0;
5904
5905         for (i = 0; i < num_rep; i++) {
5906                 struct bnxt_representor representor = {
5907                         .vf_id = eth_da->representor_ports[i],
5908                         .switch_domain_id = backing_bp->switch_domain_id,
5909                         .parent_dev = backing_eth_dev
5910                 };
5911
5912                 if (representor.vf_id >= BNXT_MAX_VF_REPS) {
5913                         PMD_DRV_LOG(ERR, "VF-Rep id %d >= %d MAX VF ID\n",
5914                                     representor.vf_id, BNXT_MAX_VF_REPS);
5915                         continue;
5916                 }
5917
5918                 /* representor port net_bdf_port */
5919                 snprintf(name, sizeof(name), "net_%s_representor_%d",
5920                          pci_dev->device.name, eth_da->representor_ports[i]);
5921
5922                 kvlist = rte_kvargs_parse(dev_args, bnxt_dev_args);
5923                 if (kvlist) {
5924                         /*
5925                          * Handler for "rep_is_pf" devarg.
5926                          * Invoked as for ex: "-a 000:00:0d.0,
5927                          * rep-based-pf=<pf index> rep-is-pf=<VF=0 or PF=1>"
5928                          */
5929                         ret = rte_kvargs_process(kvlist, BNXT_DEVARG_REP_IS_PF,
5930                                                  bnxt_parse_devarg_rep_is_pf,
5931                                                  (void *)&representor);
5932                         if (ret) {
5933                                 ret = -EINVAL;
5934                                 goto err;
5935                         }
5936                         /*
5937                          * Handler for "rep_based_pf" devarg.
5938                          * Invoked as for ex: "-a 000:00:0d.0,
5939                          * rep-based-pf=<pf index> rep-is-pf=<VF=0 or PF=1>"
5940                          */
5941                         ret = rte_kvargs_process(kvlist,
5942                                                  BNXT_DEVARG_REP_BASED_PF,
5943                                                  bnxt_parse_devarg_rep_based_pf,
5944                                                  (void *)&representor);
5945                         if (ret) {
5946                                 ret = -EINVAL;
5947                                 goto err;
5948                         }
5949                         /*
5950                          * Handler for "rep_based_pf" devarg.
5951                          * Invoked as for ex: "-a 000:00:0d.0,
5952                          * rep-based-pf=<pf index> rep-is-pf=<VF=0 or PF=1>"
5953                          */
5954                         ret = rte_kvargs_process(kvlist, BNXT_DEVARG_REP_Q_R2F,
5955                                                  bnxt_parse_devarg_rep_q_r2f,
5956                                                  (void *)&representor);
5957                         if (ret) {
5958                                 ret = -EINVAL;
5959                                 goto err;
5960                         }
5961                         /*
5962                          * Handler for "rep_based_pf" devarg.
5963                          * Invoked as for ex: "-a 000:00:0d.0,
5964                          * rep-based-pf=<pf index> rep-is-pf=<VF=0 or PF=1>"
5965                          */
5966                         ret = rte_kvargs_process(kvlist, BNXT_DEVARG_REP_Q_F2R,
5967                                                  bnxt_parse_devarg_rep_q_f2r,
5968                                                  (void *)&representor);
5969                         if (ret) {
5970                                 ret = -EINVAL;
5971                                 goto err;
5972                         }
5973                         /*
5974                          * Handler for "rep_based_pf" devarg.
5975                          * Invoked as for ex: "-a 000:00:0d.0,
5976                          * rep-based-pf=<pf index> rep-is-pf=<VF=0 or PF=1>"
5977                          */
5978                         ret = rte_kvargs_process(kvlist, BNXT_DEVARG_REP_FC_R2F,
5979                                                  bnxt_parse_devarg_rep_fc_r2f,
5980                                                  (void *)&representor);
5981                         if (ret) {
5982                                 ret = -EINVAL;
5983                                 goto err;
5984                         }
5985                         /*
5986                          * Handler for "rep_based_pf" devarg.
5987                          * Invoked as for ex: "-a 000:00:0d.0,
5988                          * rep-based-pf=<pf index> rep-is-pf=<VF=0 or PF=1>"
5989                          */
5990                         ret = rte_kvargs_process(kvlist, BNXT_DEVARG_REP_FC_F2R,
5991                                                  bnxt_parse_devarg_rep_fc_f2r,
5992                                                  (void *)&representor);
5993                         if (ret) {
5994                                 ret = -EINVAL;
5995                                 goto err;
5996                         }
5997                 }
5998
5999                 ret = rte_eth_dev_create(&pci_dev->device, name,
6000                                          sizeof(struct bnxt_representor),
6001                                          NULL, NULL,
6002                                          bnxt_representor_init,
6003                                          &representor);
6004                 if (ret) {
6005                         PMD_DRV_LOG(ERR, "failed to create bnxt vf "
6006                                     "representor %s.", name);
6007                         goto err;
6008                 }
6009
6010                 vf_rep_eth_dev = rte_eth_dev_allocated(name);
6011                 if (!vf_rep_eth_dev) {
6012                         PMD_DRV_LOG(ERR, "Failed to find the eth_dev"
6013                                     " for VF-Rep: %s.", name);
6014                         ret = -ENODEV;
6015                         goto err;
6016                 }
6017
6018                 PMD_DRV_LOG(DEBUG, "BNXT Port:%d VFR pci probe\n",
6019                             backing_eth_dev->data->port_id);
6020                 backing_bp->rep_info[representor.vf_id].vfr_eth_dev =
6021                                                          vf_rep_eth_dev;
6022                 backing_bp->num_reps++;
6023
6024         }
6025
6026         rte_kvargs_free(kvlist);
6027         return 0;
6028
6029 err:
6030         /* If num_rep > 1, then rollback already created
6031          * ports, since we'll be failing the probe anyway
6032          */
6033         if (num_rep > 1)
6034                 bnxt_pci_remove_dev_with_reps(backing_eth_dev);
6035         rte_errno = -ret;
6036         rte_kvargs_free(kvlist);
6037
6038         return ret;
6039 }
6040
6041 static int bnxt_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
6042                           struct rte_pci_device *pci_dev)
6043 {
6044         struct rte_eth_devargs eth_da = { .nb_representor_ports = 0 };
6045         struct rte_eth_dev *backing_eth_dev;
6046         uint16_t num_rep;
6047         int ret = 0;
6048
6049         if (pci_dev->device.devargs) {
6050                 ret = rte_eth_devargs_parse(pci_dev->device.devargs->args,
6051                                             &eth_da);
6052                 if (ret)
6053                         return ret;
6054         }
6055
6056         num_rep = eth_da.nb_representor_ports;
6057         PMD_DRV_LOG(DEBUG, "nb_representor_ports = %d\n",
6058                     num_rep);
6059
6060         /* We could come here after first level of probe is already invoked
6061          * as part of an application bringup(OVS-DPDK vswitchd), so first check
6062          * for already allocated eth_dev for the backing device (PF/Trusted VF)
6063          */
6064         backing_eth_dev = rte_eth_dev_allocated(pci_dev->device.name);
6065         if (backing_eth_dev == NULL) {
6066                 ret = rte_eth_dev_create(&pci_dev->device, pci_dev->device.name,
6067                                          sizeof(struct bnxt),
6068                                          eth_dev_pci_specific_init, pci_dev,
6069                                          bnxt_dev_init, NULL);
6070
6071                 if (ret || !num_rep)
6072                         return ret;
6073
6074                 backing_eth_dev = rte_eth_dev_allocated(pci_dev->device.name);
6075         }
6076         PMD_DRV_LOG(DEBUG, "BNXT Port:%d pci probe\n",
6077                     backing_eth_dev->data->port_id);
6078
6079         if (!num_rep)
6080                 return ret;
6081
6082         /* probe representor ports now */
6083         ret = bnxt_rep_port_probe(pci_dev, &eth_da, backing_eth_dev,
6084                                   pci_dev->device.devargs->args);
6085
6086         return ret;
6087 }
6088
6089 static int bnxt_pci_remove(struct rte_pci_device *pci_dev)
6090 {
6091         struct rte_eth_dev *eth_dev;
6092
6093         eth_dev = rte_eth_dev_allocated(pci_dev->device.name);
6094         if (!eth_dev)
6095                 return 0; /* Invoked typically only by OVS-DPDK, by the
6096                            * time it comes here the eth_dev is already
6097                            * deleted by rte_eth_dev_close(), so returning
6098                            * +ve value will at least help in proper cleanup
6099                            */
6100
6101         PMD_DRV_LOG(DEBUG, "BNXT Port:%d pci remove\n", eth_dev->data->port_id);
6102         if (rte_eal_process_type() == RTE_PROC_PRIMARY) {
6103                 if (eth_dev->data->dev_flags & RTE_ETH_DEV_REPRESENTOR)
6104                         return rte_eth_dev_destroy(eth_dev,
6105                                                    bnxt_representor_uninit);
6106                 else
6107                         return rte_eth_dev_destroy(eth_dev,
6108                                                    bnxt_dev_uninit);
6109         } else {
6110                 return rte_eth_dev_pci_generic_remove(pci_dev, NULL);
6111         }
6112 }
6113
6114 static struct rte_pci_driver bnxt_rte_pmd = {
6115         .id_table = bnxt_pci_id_map,
6116         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC |
6117                         RTE_PCI_DRV_PROBE_AGAIN, /* Needed in case of VF-REPs
6118                                                   * and OVS-DPDK
6119                                                   */
6120         .probe = bnxt_pci_probe,
6121         .remove = bnxt_pci_remove,
6122 };
6123
6124 static bool
6125 is_device_supported(struct rte_eth_dev *dev, struct rte_pci_driver *drv)
6126 {
6127         if (strcmp(dev->device->driver->name, drv->driver.name))
6128                 return false;
6129
6130         return true;
6131 }
6132
6133 bool is_bnxt_supported(struct rte_eth_dev *dev)
6134 {
6135         return is_device_supported(dev, &bnxt_rte_pmd);
6136 }
6137
6138 RTE_LOG_REGISTER(bnxt_logtype_driver, pmd.net.bnxt.driver, NOTICE);
6139 RTE_PMD_REGISTER_PCI(net_bnxt, bnxt_rte_pmd);
6140 RTE_PMD_REGISTER_PCI_TABLE(net_bnxt, bnxt_pci_id_map);
6141 RTE_PMD_REGISTER_KMOD_DEP(net_bnxt, "* igb_uio | uio_pci_generic | vfio-pci");