drivers/net/bnxt/bnxt_ethdev.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2014-2018 Broadcom
   3  * All rights reserved.
   4  */
   5
   6 #include <inttypes.h>
   7 #include <stdbool.h>
   8
   9 #include <rte_dev.h>
  10 #include <rte_ethdev_driver.h>
  11 #include <rte_ethdev_pci.h>
  12 #include <rte_malloc.h>
  13 #include <rte_cycles.h>
  14 #include <rte_alarm.h>
  15 #include <rte_kvargs.h>
  16
  17 #include "bnxt.h"
  18 #include "bnxt_filter.h"
  19 #include "bnxt_hwrm.h"
  20 #include "bnxt_irq.h"
  21 #include "bnxt_reps.h"
  22 #include "bnxt_ring.h"
  23 #include "bnxt_rxq.h"
  24 #include "bnxt_rxr.h"
  25 #include "bnxt_stats.h"
  26 #include "bnxt_txq.h"
  27 #include "bnxt_txr.h"
  28 #include "bnxt_vnic.h"
  29 #include "hsi_struct_def_dpdk.h"
  30 #include "bnxt_nvm_defs.h"
  31
  32 #define DRV_MODULE_NAME         "bnxt"
  33 static const char bnxt_version[] =
  34         "Broadcom NetXtreme driver " DRV_MODULE_NAME;
  35
  36 /*
  37  * The set of PCI devices this driver supports
  38  */
  39 static const struct rte_pci_id bnxt_pci_id_map[] = {
  40         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM,
  41                          BROADCOM_DEV_ID_STRATUS_NIC_VF1) },
  42         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM,
  43                          BROADCOM_DEV_ID_STRATUS_NIC_VF2) },
  44         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_STRATUS_NIC) },
  45         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414_VF) },
  46         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57301) },
  47         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57302) },
  48         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57304_PF) },
  49         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57304_VF) },
  50         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_NS2) },
  51         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57402) },
  52         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57404) },
  53         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57406_PF) },
  54         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57406_VF) },
  55         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57402_MF) },
  56         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57407_RJ45) },
  57         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57404_MF) },
  58         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57406_MF) },
  59         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57407_SFP) },
  60         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57407_MF) },
  61         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_5741X_VF) },
  62         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_5731X_VF) },
  63         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57314) },
  64         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_MF) },
  65         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57311) },
  66         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57312) },
  67         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57412) },
  68         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414) },
  69         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_RJ45) },
  70         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_RJ45) },
  71         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57412_MF) },
  72         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57317_RJ45) },
  73         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_SFP) },
  74         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_SFP) },
  75         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57317_SFP) },
  76         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414_MF) },
  77         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_MF) },
  78         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58802) },
  79         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58804) },
  80         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58808) },
  81         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58802_VF) },
  82         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57508) },
  83         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57504) },
  84         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57502) },
  85         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57500_VF1) },
  86         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57500_VF2) },
  87         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57508_MF1) },
  88         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57504_MF1) },
  89         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57502_MF1) },
  90         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57508_MF2) },
  91         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57504_MF2) },
  92         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57502_MF2) },
  93         { .vendor_id = 0, /* sentinel */ },
  94 };
  95
  96 #define BNXT_DEVARG_TRUFLOW     "host-based-truflow"
  97 #define BNXT_DEVARG_FLOW_XSTAT  "flow-xstat"
  98 #define BNXT_DEVARG_MAX_NUM_KFLOWS  "max-num-kflows"
  99
 100 static const char *const bnxt_dev_args[] = {
 101         BNXT_DEVARG_TRUFLOW,
 102         BNXT_DEVARG_FLOW_XSTAT,
 103         BNXT_DEVARG_MAX_NUM_KFLOWS,
 104         NULL
 105 };
 106
 107 /*
 108  * truflow == false to disable the feature
 109  * truflow == true to enable the feature
 110  */
 111 #define BNXT_DEVARG_TRUFLOW_INVALID(truflow)    ((truflow) > 1)
 112
 113 /*
 114  * flow_xstat == false to disable the feature
 115  * flow_xstat == true to enable the feature
 116  */
 117 #define BNXT_DEVARG_FLOW_XSTAT_INVALID(flow_xstat)      ((flow_xstat) > 1)
 118
 119 /*
 120  * max_num_kflows must be >= 32
 121  * and must be a power-of-2 supported value
 122  * return: 1 -> invalid
 123  *         0 -> valid
 124  */
 125 static int bnxt_devarg_max_num_kflow_invalid(uint16_t max_num_kflows)
 126 {
 127         if (max_num_kflows < 32 || !rte_is_power_of_2(max_num_kflows))
 128                 return 1;
 129         return 0;
 130 }
 131
 132 static int bnxt_vlan_offload_set_op(struct rte_eth_dev *dev, int mask);
 133 static int bnxt_dev_uninit(struct rte_eth_dev *eth_dev);
 134 static int bnxt_init_resources(struct bnxt *bp, bool reconfig_dev);
 135 static int bnxt_uninit_resources(struct bnxt *bp, bool reconfig_dev);
 136 static void bnxt_cancel_fw_health_check(struct bnxt *bp);
 137 static int bnxt_restore_vlan_filters(struct bnxt *bp);
 138 static void bnxt_dev_recover(void *arg);
 139 static void bnxt_free_error_recovery_info(struct bnxt *bp);
 140 static void bnxt_free_rep_info(struct bnxt *bp);
 141
 142 int is_bnxt_in_error(struct bnxt *bp)
 143 {
 144         if (bp->flags & BNXT_FLAG_FATAL_ERROR)
 145                 return -EIO;
 146         if (bp->flags & BNXT_FLAG_FW_RESET)
 147                 return -EBUSY;
 148
 149         return 0;
 150 }
 151
 152 /***********************/
 153
 154 /*
 155  * High level utility functions
 156  */
 157
 158 static uint16_t bnxt_rss_ctxts(const struct bnxt *bp)
 159 {
 160         if (!BNXT_CHIP_THOR(bp))
 161                 return 1;
 162
 163         return RTE_ALIGN_MUL_CEIL(bp->rx_nr_rings,
 164                                   BNXT_RSS_ENTRIES_PER_CTX_THOR) /
 165                                     BNXT_RSS_ENTRIES_PER_CTX_THOR;
 166 }
 167
 168 uint16_t bnxt_rss_hash_tbl_size(const struct bnxt *bp)
 169 {
 170         if (!BNXT_CHIP_THOR(bp))
 171                 return HW_HASH_INDEX_SIZE;
 172
 173         return bnxt_rss_ctxts(bp) * BNXT_RSS_ENTRIES_PER_CTX_THOR;
 174 }
 175
 176 static void bnxt_free_parent_info(struct bnxt *bp)
 177 {
 178         rte_free(bp->parent);
 179 }
 180
 181 static void bnxt_free_pf_info(struct bnxt *bp)
 182 {
 183         rte_free(bp->pf);
 184 }
 185
 186 static void bnxt_free_link_info(struct bnxt *bp)
 187 {
 188         rte_free(bp->link_info);
 189 }
 190
 191 static void bnxt_free_leds_info(struct bnxt *bp)
 192 {
 193         rte_free(bp->leds);
 194         bp->leds = NULL;
 195 }
 196
 197 static void bnxt_free_flow_stats_info(struct bnxt *bp)
 198 {
 199         rte_free(bp->flow_stat);
 200         bp->flow_stat = NULL;
 201 }
 202
 203 static void bnxt_free_cos_queues(struct bnxt *bp)
 204 {
 205         rte_free(bp->rx_cos_queue);
 206         rte_free(bp->tx_cos_queue);
 207 }
 208
 209 static void bnxt_free_mem(struct bnxt *bp, bool reconfig)
 210 {
 211         bnxt_free_filter_mem(bp);
 212         bnxt_free_vnic_attributes(bp);
 213         bnxt_free_vnic_mem(bp);
 214
 215         /* tx/rx rings are configured as part of *_queue_setup callbacks.
 216          * If the number of rings change across fw update,
 217          * we don't have much choice except to warn the user.
 218          */
 219         if (!reconfig) {
 220                 bnxt_free_stats(bp);
 221                 bnxt_free_tx_rings(bp);
 222                 bnxt_free_rx_rings(bp);
 223         }
 224         bnxt_free_async_cp_ring(bp);
 225         bnxt_free_rxtx_nq_ring(bp);
 226
 227         rte_free(bp->grp_info);
 228         bp->grp_info = NULL;
 229 }
 230
 231 static int bnxt_alloc_parent_info(struct bnxt *bp)
 232 {
 233         bp->parent = rte_zmalloc("bnxt_parent_info",
 234                                  sizeof(struct bnxt_parent_info), 0);
 235         if (bp->parent == NULL)
 236                 return -ENOMEM;
 237
 238         return 0;
 239 }
 240
 241 static int bnxt_alloc_pf_info(struct bnxt *bp)
 242 {
 243         bp->pf = rte_zmalloc("bnxt_pf_info", sizeof(struct bnxt_pf_info), 0);
 244         if (bp->pf == NULL)
 245                 return -ENOMEM;
 246
 247         return 0;
 248 }
 249
 250 static int bnxt_alloc_link_info(struct bnxt *bp)
 251 {
 252         bp->link_info =
 253                 rte_zmalloc("bnxt_link_info", sizeof(struct bnxt_link_info), 0);
 254         if (bp->link_info == NULL)
 255                 return -ENOMEM;
 256
 257         return 0;
 258 }
 259
 260 static int bnxt_alloc_leds_info(struct bnxt *bp)
 261 {
 262         bp->leds = rte_zmalloc("bnxt_leds",
 263                                BNXT_MAX_LED * sizeof(struct bnxt_led_info),
 264                                0);
 265         if (bp->leds == NULL)
 266                 return -ENOMEM;
 267
 268         return 0;
 269 }
 270
 271 static int bnxt_alloc_cos_queues(struct bnxt *bp)
 272 {
 273         bp->rx_cos_queue =
 274                 rte_zmalloc("bnxt_rx_cosq",
 275                             BNXT_COS_QUEUE_COUNT *
 276                             sizeof(struct bnxt_cos_queue_info),
 277                             0);
 278         if (bp->rx_cos_queue == NULL)
 279                 return -ENOMEM;
 280
 281         bp->tx_cos_queue =
 282                 rte_zmalloc("bnxt_tx_cosq",
 283                             BNXT_COS_QUEUE_COUNT *
 284                             sizeof(struct bnxt_cos_queue_info),
 285                             0);
 286         if (bp->tx_cos_queue == NULL)
 287                 return -ENOMEM;
 288
 289         return 0;
 290 }
 291
 292 static int bnxt_alloc_flow_stats_info(struct bnxt *bp)
 293 {
 294         bp->flow_stat = rte_zmalloc("bnxt_flow_xstat",
 295                                     sizeof(struct bnxt_flow_stat_info), 0);
 296         if (bp->flow_stat == NULL)
 297                 return -ENOMEM;
 298
 299         return 0;
 300 }
 301
 302 static int bnxt_alloc_mem(struct bnxt *bp, bool reconfig)
 303 {
 304         int rc;
 305
 306         rc = bnxt_alloc_ring_grps(bp);
 307         if (rc)
 308                 goto alloc_mem_err;
 309
 310         rc = bnxt_alloc_async_ring_struct(bp);
 311         if (rc)
 312                 goto alloc_mem_err;
 313
 314         rc = bnxt_alloc_vnic_mem(bp);
 315         if (rc)
 316                 goto alloc_mem_err;
 317
 318         rc = bnxt_alloc_vnic_attributes(bp);
 319         if (rc)
 320                 goto alloc_mem_err;
 321
 322         rc = bnxt_alloc_filter_mem(bp);
 323         if (rc)
 324                 goto alloc_mem_err;
 325
 326         rc = bnxt_alloc_async_cp_ring(bp);
 327         if (rc)
 328                 goto alloc_mem_err;
 329
 330         rc = bnxt_alloc_rxtx_nq_ring(bp);
 331         if (rc)
 332                 goto alloc_mem_err;
 333
 334         if (BNXT_FLOW_XSTATS_EN(bp)) {
 335                 rc = bnxt_alloc_flow_stats_info(bp);
 336                 if (rc)
 337                         goto alloc_mem_err;
 338         }
 339
 340         return 0;
 341
 342 alloc_mem_err:
 343         bnxt_free_mem(bp, reconfig);
 344         return rc;
 345 }
 346
 347 static int bnxt_setup_one_vnic(struct bnxt *bp, uint16_t vnic_id)
 348 {
 349         struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
 350         struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id];
 351         uint64_t rx_offloads = dev_conf->rxmode.offloads;
 352         struct bnxt_rx_queue *rxq;
 353         unsigned int j;
 354         int rc;
 355
 356         rc = bnxt_vnic_grp_alloc(bp, vnic);
 357         if (rc)
 358                 goto err_out;
 359
 360         PMD_DRV_LOG(DEBUG, "vnic[%d] = %p vnic->fw_grp_ids = %p\n",
 361                     vnic_id, vnic, vnic->fw_grp_ids);
 362
 363         rc = bnxt_hwrm_vnic_alloc(bp, vnic);
 364         if (rc)
 365                 goto err_out;
 366
 367         /* Alloc RSS context only if RSS mode is enabled */
 368         if (dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS) {
 369                 int j, nr_ctxs = bnxt_rss_ctxts(bp);
 370
 371                 rc = 0;
 372                 for (j = 0; j < nr_ctxs; j++) {
 373                         rc = bnxt_hwrm_vnic_ctx_alloc(bp, vnic, j);
 374                         if (rc)
 375                                 break;
 376                 }
 377                 if (rc) {
 378                         PMD_DRV_LOG(ERR,
 379                                     "HWRM vnic %d ctx %d alloc failure rc: %x\n",
 380                                     vnic_id, j, rc);
 381                         goto err_out;
 382                 }
 383                 vnic->num_lb_ctxts = nr_ctxs;
 384         }
 385
 386         /*
 387          * Firmware sets pf pair in default vnic cfg. If the VLAN strip
 388          * setting is not available at this time, it will not be
 389          * configured correctly in the CFA.
 390          */
 391         if (rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
 392                 vnic->vlan_strip = true;
 393         else
 394                 vnic->vlan_strip = false;
 395
 396         rc = bnxt_hwrm_vnic_cfg(bp, vnic);
 397         if (rc)
 398                 goto err_out;
 399
 400         rc = bnxt_set_hwrm_vnic_filters(bp, vnic);
 401         if (rc)
 402                 goto err_out;
 403
 404         for (j = 0; j < bp->rx_num_qs_per_vnic; j++) {
 405                 rxq = bp->eth_dev->data->rx_queues[j];
 406
 407                 PMD_DRV_LOG(DEBUG,
 408                             "rxq[%d]->vnic=%p vnic->fw_grp_ids=%p\n",
 409                             j, rxq->vnic, rxq->vnic->fw_grp_ids);
 410
 411                 if (BNXT_HAS_RING_GRPS(bp) && rxq->rx_deferred_start)
 412                         rxq->vnic->fw_grp_ids[j] = INVALID_HW_RING_ID;
 413                 else
 414                         vnic->rx_queue_cnt++;
 415         }
 416
 417         PMD_DRV_LOG(DEBUG, "vnic->rx_queue_cnt = %d\n", vnic->rx_queue_cnt);
 418
 419         rc = bnxt_vnic_rss_configure(bp, vnic);
 420         if (rc)
 421                 goto err_out;
 422
 423         bnxt_hwrm_vnic_plcmode_cfg(bp, vnic);
 424
 425         if (rx_offloads & DEV_RX_OFFLOAD_TCP_LRO)
 426                 bnxt_hwrm_vnic_tpa_cfg(bp, vnic, 1);
 427         else
 428                 bnxt_hwrm_vnic_tpa_cfg(bp, vnic, 0);
 429
 430         return 0;
 431 err_out:
 432         PMD_DRV_LOG(ERR, "HWRM vnic %d cfg failure rc: %x\n",
 433                     vnic_id, rc);
 434         return rc;
 435 }
 436
 437 static int bnxt_register_fc_ctx_mem(struct bnxt *bp)
 438 {
 439         int rc = 0;
 440
 441         rc = bnxt_hwrm_ctx_rgtr(bp, bp->flow_stat->rx_fc_in_tbl.dma,
 442                                 &bp->flow_stat->rx_fc_in_tbl.ctx_id);
 443         if (rc)
 444                 return rc;
 445
 446         PMD_DRV_LOG(DEBUG,
 447                     "rx_fc_in_tbl.va = %p rx_fc_in_tbl.dma = %p"
 448                     " rx_fc_in_tbl.ctx_id = %d\n",
 449                     bp->flow_stat->rx_fc_in_tbl.va,
 450                     (void *)((uintptr_t)bp->flow_stat->rx_fc_in_tbl.dma),
 451                     bp->flow_stat->rx_fc_in_tbl.ctx_id);
 452
 453         rc = bnxt_hwrm_ctx_rgtr(bp, bp->flow_stat->rx_fc_out_tbl.dma,
 454                                 &bp->flow_stat->rx_fc_out_tbl.ctx_id);
 455         if (rc)
 456                 return rc;
 457
 458         PMD_DRV_LOG(DEBUG,
 459                     "rx_fc_out_tbl.va = %p rx_fc_out_tbl.dma = %p"
 460                     " rx_fc_out_tbl.ctx_id = %d\n",
 461                     bp->flow_stat->rx_fc_out_tbl.va,
 462                     (void *)((uintptr_t)bp->flow_stat->rx_fc_out_tbl.dma),
 463                     bp->flow_stat->rx_fc_out_tbl.ctx_id);
 464
 465         rc = bnxt_hwrm_ctx_rgtr(bp, bp->flow_stat->tx_fc_in_tbl.dma,
 466                                 &bp->flow_stat->tx_fc_in_tbl.ctx_id);
 467         if (rc)
 468                 return rc;
 469
 470         PMD_DRV_LOG(DEBUG,
 471                     "tx_fc_in_tbl.va = %p tx_fc_in_tbl.dma = %p"
 472                     " tx_fc_in_tbl.ctx_id = %d\n",
 473                     bp->flow_stat->tx_fc_in_tbl.va,
 474                     (void *)((uintptr_t)bp->flow_stat->tx_fc_in_tbl.dma),
 475                     bp->flow_stat->tx_fc_in_tbl.ctx_id);
 476
 477         rc = bnxt_hwrm_ctx_rgtr(bp, bp->flow_stat->tx_fc_out_tbl.dma,
 478                                 &bp->flow_stat->tx_fc_out_tbl.ctx_id);
 479         if (rc)
 480                 return rc;
 481
 482         PMD_DRV_LOG(DEBUG,
 483                     "tx_fc_out_tbl.va = %p tx_fc_out_tbl.dma = %p"
 484                     " tx_fc_out_tbl.ctx_id = %d\n",
 485                     bp->flow_stat->tx_fc_out_tbl.va,
 486                     (void *)((uintptr_t)bp->flow_stat->tx_fc_out_tbl.dma),
 487                     bp->flow_stat->tx_fc_out_tbl.ctx_id);
 488
 489         memset(bp->flow_stat->rx_fc_out_tbl.va,
 490                0,
 491                bp->flow_stat->rx_fc_out_tbl.size);
 492         rc = bnxt_hwrm_cfa_counter_cfg(bp, BNXT_DIR_RX,
 493                                        CFA_COUNTER_CFG_IN_COUNTER_TYPE_FC,
 494                                        bp->flow_stat->rx_fc_out_tbl.ctx_id,
 495                                        bp->flow_stat->max_fc,
 496                                        true);
 497         if (rc)
 498                 return rc;
 499
 500         memset(bp->flow_stat->tx_fc_out_tbl.va,
 501                0,
 502                bp->flow_stat->tx_fc_out_tbl.size);
 503         rc = bnxt_hwrm_cfa_counter_cfg(bp, BNXT_DIR_TX,
 504                                        CFA_COUNTER_CFG_IN_COUNTER_TYPE_FC,
 505                                        bp->flow_stat->tx_fc_out_tbl.ctx_id,
 506                                        bp->flow_stat->max_fc,
 507                                        true);
 508
 509         return rc;
 510 }
 511
 512 static int bnxt_alloc_ctx_mem_buf(char *type, size_t size,
 513                                   struct bnxt_ctx_mem_buf_info *ctx)
 514 {
 515         if (!ctx)
 516                 return -EINVAL;
 517
 518         ctx->va = rte_zmalloc(type, size, 0);
 519         if (ctx->va == NULL)
 520                 return -ENOMEM;
 521         rte_mem_lock_page(ctx->va);
 522         ctx->size = size;
 523         ctx->dma = rte_mem_virt2iova(ctx->va);
 524         if (ctx->dma == RTE_BAD_IOVA)
 525                 return -ENOMEM;
 526
 527         return 0;
 528 }
 529
 530 static int bnxt_init_fc_ctx_mem(struct bnxt *bp)
 531 {
 532         struct rte_pci_device *pdev = bp->pdev;
 533         char type[RTE_MEMZONE_NAMESIZE];
 534         uint16_t max_fc;
 535         int rc = 0;
 536
 537         max_fc = bp->flow_stat->max_fc;
 538
 539         sprintf(type, "bnxt_rx_fc_in_" PCI_PRI_FMT, pdev->addr.domain,
 540                 pdev->addr.bus, pdev->addr.devid, pdev->addr.function);
 541         /* 4 bytes for each counter-id */
 542         rc = bnxt_alloc_ctx_mem_buf(type,
 543                                     max_fc * 4,
 544                                     &bp->flow_stat->rx_fc_in_tbl);
 545         if (rc)
 546                 return rc;
 547
 548         sprintf(type, "bnxt_rx_fc_out_" PCI_PRI_FMT, pdev->addr.domain,
 549                 pdev->addr.bus, pdev->addr.devid, pdev->addr.function);
 550         /* 16 bytes for each counter - 8 bytes pkt_count, 8 bytes byte_count */
 551         rc = bnxt_alloc_ctx_mem_buf(type,
 552                                     max_fc * 16,
 553                                     &bp->flow_stat->rx_fc_out_tbl);
 554         if (rc)
 555                 return rc;
 556
 557         sprintf(type, "bnxt_tx_fc_in_" PCI_PRI_FMT, pdev->addr.domain,
 558                 pdev->addr.bus, pdev->addr.devid, pdev->addr.function);
 559         /* 4 bytes for each counter-id */
 560         rc = bnxt_alloc_ctx_mem_buf(type,
 561                                     max_fc * 4,
 562                                     &bp->flow_stat->tx_fc_in_tbl);
 563         if (rc)
 564                 return rc;
 565
 566         sprintf(type, "bnxt_tx_fc_out_" PCI_PRI_FMT, pdev->addr.domain,
 567                 pdev->addr.bus, pdev->addr.devid, pdev->addr.function);
 568         /* 16 bytes for each counter - 8 bytes pkt_count, 8 bytes byte_count */
 569         rc = bnxt_alloc_ctx_mem_buf(type,
 570                                     max_fc * 16,
 571                                     &bp->flow_stat->tx_fc_out_tbl);
 572         if (rc)
 573                 return rc;
 574
 575         rc = bnxt_register_fc_ctx_mem(bp);
 576
 577         return rc;
 578 }
 579
 580 static int bnxt_init_ctx_mem(struct bnxt *bp)
 581 {
 582         int rc = 0;
 583
 584         if (!(bp->fw_cap & BNXT_FW_CAP_ADV_FLOW_COUNTERS) ||
 585             !(BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp)) ||
 586             !BNXT_FLOW_XSTATS_EN(bp))
 587                 return 0;
 588
 589         rc = bnxt_hwrm_cfa_counter_qcaps(bp, &bp->flow_stat->max_fc);
 590         if (rc)
 591                 return rc;
 592
 593         rc = bnxt_init_fc_ctx_mem(bp);
 594
 595         return rc;
 596 }
 597
 598 static int bnxt_init_chip(struct bnxt *bp)
 599 {
 600         struct rte_eth_link new;
 601         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(bp->eth_dev);
 602         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
 603         uint32_t intr_vector = 0;
 604         uint32_t queue_id, base = BNXT_MISC_VEC_ID;
 605         uint32_t vec = BNXT_MISC_VEC_ID;
 606         unsigned int i, j;
 607         int rc;
 608
 609         if (bp->eth_dev->data->mtu > RTE_ETHER_MTU) {
 610                 bp->eth_dev->data->dev_conf.rxmode.offloads |=
 611                         DEV_RX_OFFLOAD_JUMBO_FRAME;
 612                 bp->flags |= BNXT_FLAG_JUMBO;
 613         } else {
 614                 bp->eth_dev->data->dev_conf.rxmode.offloads &=
 615                         ~DEV_RX_OFFLOAD_JUMBO_FRAME;
 616                 bp->flags &= ~BNXT_FLAG_JUMBO;
 617         }
 618
 619         /* THOR does not support ring groups.
 620          * But we will use the array to save RSS context IDs.
 621          */
 622         if (BNXT_CHIP_THOR(bp))
 623                 bp->max_ring_grps = BNXT_MAX_RSS_CTXTS_THOR;
 624
 625         rc = bnxt_alloc_all_hwrm_stat_ctxs(bp);
 626         if (rc) {
 627                 PMD_DRV_LOG(ERR, "HWRM stat ctx alloc failure rc: %x\n", rc);
 628                 goto err_out;
 629         }
 630
 631         rc = bnxt_alloc_hwrm_rings(bp);
 632         if (rc) {
 633                 PMD_DRV_LOG(ERR, "HWRM ring alloc failure rc: %x\n", rc);
 634                 goto err_out;
 635         }
 636
 637         rc = bnxt_alloc_all_hwrm_ring_grps(bp);
 638         if (rc) {
 639                 PMD_DRV_LOG(ERR, "HWRM ring grp alloc failure: %x\n", rc);
 640                 goto err_out;
 641         }
 642
 643         if (!(bp->vnic_cap_flags & BNXT_VNIC_CAP_COS_CLASSIFY))
 644                 goto skip_cosq_cfg;
 645
 646         for (j = 0, i = 0; i < BNXT_COS_QUEUE_COUNT; i++) {
 647                 if (bp->rx_cos_queue[i].id != 0xff) {
 648                         struct bnxt_vnic_info *vnic = &bp->vnic_info[j++];
 649
 650                         if (!vnic) {
 651                                 PMD_DRV_LOG(ERR,
 652                                             "Num pools more than FW profile\n");
 653                                 rc = -EINVAL;
 654                                 goto err_out;
 655                         }
 656                         vnic->cos_queue_id = bp->rx_cos_queue[i].id;
 657                         bp->rx_cosq_cnt++;
 658                 }
 659         }
 660
 661 skip_cosq_cfg:
 662         rc = bnxt_mq_rx_configure(bp);
 663         if (rc) {
 664                 PMD_DRV_LOG(ERR, "MQ mode configure failure rc: %x\n", rc);
 665                 goto err_out;
 666         }
 667
 668         /* VNIC configuration */
 669         for (i = 0; i < bp->nr_vnics; i++) {
 670                 rc = bnxt_setup_one_vnic(bp, i);
 671                 if (rc)
 672                         goto err_out;
 673         }
 674
 675         rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, &bp->vnic_info[0], 0, NULL);
 676         if (rc) {
 677                 PMD_DRV_LOG(ERR,
 678                         "HWRM cfa l2 rx mask failure rc: %x\n", rc);
 679                 goto err_out;
 680         }
 681
 682         /* check and configure queue intr-vector mapping */
 683         if ((rte_intr_cap_multiple(intr_handle) ||
 684              !RTE_ETH_DEV_SRIOV(bp->eth_dev).active) &&
 685             bp->eth_dev->data->dev_conf.intr_conf.rxq != 0) {
 686                 intr_vector = bp->eth_dev->data->nb_rx_queues;
 687                 PMD_DRV_LOG(DEBUG, "intr_vector = %d\n", intr_vector);
 688                 if (intr_vector > bp->rx_cp_nr_rings) {
 689                         PMD_DRV_LOG(ERR, "At most %d intr queues supported",
 690                                         bp->rx_cp_nr_rings);
 691                         return -ENOTSUP;
 692                 }
 693                 rc = rte_intr_efd_enable(intr_handle, intr_vector);
 694                 if (rc)
 695                         return rc;
 696         }
 697
 698         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
 699                 intr_handle->intr_vec =
 700                         rte_zmalloc("intr_vec",
 701                                     bp->eth_dev->data->nb_rx_queues *
 702                                     sizeof(int), 0);
 703                 if (intr_handle->intr_vec == NULL) {
 704                         PMD_DRV_LOG(ERR, "Failed to allocate %d rx_queues"
 705                                 " intr_vec", bp->eth_dev->data->nb_rx_queues);
 706                         rc = -ENOMEM;
 707                         goto err_disable;
 708                 }
 709                 PMD_DRV_LOG(DEBUG, "intr_handle->intr_vec = %p "
 710                         "intr_handle->nb_efd = %d intr_handle->max_intr = %d\n",
 711                          intr_handle->intr_vec, intr_handle->nb_efd,
 712                         intr_handle->max_intr);
 713                 for (queue_id = 0; queue_id < bp->eth_dev->data->nb_rx_queues;
 714                      queue_id++) {
 715                         intr_handle->intr_vec[queue_id] =
 716                                                         vec + BNXT_RX_VEC_START;
 717                         if (vec < base + intr_handle->nb_efd - 1)
 718                                 vec++;
 719                 }
 720         }
 721
 722         /* enable uio/vfio intr/eventfd mapping */
 723         rc = rte_intr_enable(intr_handle);
 724 #ifndef RTE_EXEC_ENV_FREEBSD
 725         /* In FreeBSD OS, nic_uio driver does not support interrupts */
 726         if (rc)
 727                 goto err_free;
 728 #endif
 729
 730         rc = bnxt_get_hwrm_link_config(bp, &new);
 731         if (rc) {
 732                 PMD_DRV_LOG(ERR, "HWRM Get link config failure rc: %x\n", rc);
 733                 goto err_free;
 734         }
 735
 736         if (!bp->link_info->link_up) {
 737                 rc = bnxt_set_hwrm_link_config(bp, true);
 738                 if (rc) {
 739                         PMD_DRV_LOG(ERR,
 740                                 "HWRM link config failure rc: %x\n", rc);
 741                         goto err_free;
 742                 }
 743         }
 744         bnxt_print_link_info(bp->eth_dev);
 745
 746         bp->mark_table = rte_zmalloc("bnxt_mark_table", BNXT_MARK_TABLE_SZ, 0);
 747         if (!bp->mark_table)
 748                 PMD_DRV_LOG(ERR, "Allocation of mark table failed\n");
 749
 750         return 0;
 751
 752 err_free:
 753         rte_free(intr_handle->intr_vec);
 754 err_disable:
 755         rte_intr_efd_disable(intr_handle);
 756 err_out:
 757         /* Some of the error status returned by FW may not be from errno.h */
 758         if (rc > 0)
 759                 rc = -EIO;
 760
 761         return rc;
 762 }
 763
 764 static int bnxt_shutdown_nic(struct bnxt *bp)
 765 {
 766         bnxt_free_all_hwrm_resources(bp);
 767         bnxt_free_all_filters(bp);
 768         bnxt_free_all_vnics(bp);
 769         return 0;
 770 }
 771
 772 /*
 773  * Device configuration and status function
 774  */
 775
 776 uint32_t bnxt_get_speed_capabilities(struct bnxt *bp)
 777 {
 778         uint32_t link_speed = bp->link_info->support_speeds;
 779         uint32_t speed_capa = 0;
 780
 781         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_100MB)
 782                 speed_capa |= ETH_LINK_SPEED_100M;
 783         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_100MBHD)
 784                 speed_capa |= ETH_LINK_SPEED_100M_HD;
 785         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_1GB)
 786                 speed_capa |= ETH_LINK_SPEED_1G;
 787         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_2_5GB)
 788                 speed_capa |= ETH_LINK_SPEED_2_5G;
 789         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_10GB)
 790                 speed_capa |= ETH_LINK_SPEED_10G;
 791         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_20GB)
 792                 speed_capa |= ETH_LINK_SPEED_20G;
 793         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_25GB)
 794                 speed_capa |= ETH_LINK_SPEED_25G;
 795         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_40GB)
 796                 speed_capa |= ETH_LINK_SPEED_40G;
 797         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_50GB)
 798                 speed_capa |= ETH_LINK_SPEED_50G;
 799         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_100GB)
 800                 speed_capa |= ETH_LINK_SPEED_100G;
 801         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_200GB)
 802                 speed_capa |= ETH_LINK_SPEED_200G;
 803
 804         if (bp->link_info->auto_mode ==
 805             HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_MODE_NONE)
 806                 speed_capa |= ETH_LINK_SPEED_FIXED;
 807         else
 808                 speed_capa |= ETH_LINK_SPEED_AUTONEG;
 809
 810         return speed_capa;
 811 }
 812
 813 static int bnxt_dev_info_get_op(struct rte_eth_dev *eth_dev,
 814                                 struct rte_eth_dev_info *dev_info)
 815 {
 816         struct rte_pci_device *pdev = RTE_DEV_TO_PCI(eth_dev->device);
 817         struct bnxt *bp = eth_dev->data->dev_private;
 818         uint16_t max_vnics, i, j, vpool, vrxq;
 819         unsigned int max_rx_rings;
 820         int rc;
 821
 822         rc = is_bnxt_in_error(bp);
 823         if (rc)
 824                 return rc;
 825
 826         /* MAC Specifics */
 827         dev_info->max_mac_addrs = bp->max_l2_ctx;
 828         dev_info->max_hash_mac_addrs = 0;
 829
 830         /* PF/VF specifics */
 831         if (BNXT_PF(bp))
 832                 dev_info->max_vfs = pdev->max_vfs;
 833
 834         max_rx_rings = BNXT_MAX_RINGS(bp);
 835         /* For the sake of symmetry, max_rx_queues = max_tx_queues */
 836         dev_info->max_rx_queues = max_rx_rings;
 837         dev_info->max_tx_queues = max_rx_rings;
 838         dev_info->reta_size = bnxt_rss_hash_tbl_size(bp);
 839         dev_info->hash_key_size = 40;
 840         max_vnics = bp->max_vnics;
 841
 842         /* MTU specifics */
 843         dev_info->min_mtu = RTE_ETHER_MIN_MTU;
 844         dev_info->max_mtu = BNXT_MAX_MTU;
 845
 846         /* Fast path specifics */
 847         dev_info->min_rx_bufsize = 1;
 848         dev_info->max_rx_pktlen = BNXT_MAX_PKT_LEN;
 849
 850         dev_info->rx_offload_capa = BNXT_DEV_RX_OFFLOAD_SUPPORT;
 851         if (bp->flags & BNXT_FLAG_PTP_SUPPORTED)
 852                 dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_TIMESTAMP;
 853         dev_info->tx_offload_capa = BNXT_DEV_TX_OFFLOAD_SUPPORT;
 854         dev_info->flow_type_rss_offloads = BNXT_ETH_RSS_SUPPORT;
 855
 856         dev_info->speed_capa = bnxt_get_speed_capabilities(bp);
 857
 858         /* *INDENT-OFF* */
 859         dev_info->default_rxconf = (struct rte_eth_rxconf) {
 860                 .rx_thresh = {
 861                         .pthresh = 8,
 862                         .hthresh = 8,
 863                         .wthresh = 0,
 864                 },
 865                 .rx_free_thresh = 32,
 866                 /* If no descriptors available, pkts are dropped by default */
 867                 .rx_drop_en = 1,
 868         };
 869
 870         dev_info->default_txconf = (struct rte_eth_txconf) {
 871                 .tx_thresh = {
 872                         .pthresh = 32,
 873                         .hthresh = 0,
 874                         .wthresh = 0,
 875                 },
 876                 .tx_free_thresh = 32,
 877                 .tx_rs_thresh = 32,
 878         };
 879         eth_dev->data->dev_conf.intr_conf.lsc = 1;
 880
 881         eth_dev->data->dev_conf.intr_conf.rxq = 1;
 882         dev_info->rx_desc_lim.nb_min = BNXT_MIN_RING_DESC;
 883         dev_info->rx_desc_lim.nb_max = BNXT_MAX_RX_RING_DESC;
 884         dev_info->tx_desc_lim.nb_min = BNXT_MIN_RING_DESC;
 885         dev_info->tx_desc_lim.nb_max = BNXT_MAX_TX_RING_DESC;
 886
 887         /* *INDENT-ON* */
 888
 889         /*
 890          * TODO: default_rxconf, default_txconf, rx_desc_lim, and tx_desc_lim
 891          *       need further investigation.
 892          */
 893
 894         /* VMDq resources */
 895         vpool = 64; /* ETH_64_POOLS */
 896         vrxq = 128; /* ETH_VMDQ_DCB_NUM_QUEUES */
 897         for (i = 0; i < 4; vpool >>= 1, i++) {
 898                 if (max_vnics > vpool) {
 899                         for (j = 0; j < 5; vrxq >>= 1, j++) {
 900                                 if (dev_info->max_rx_queues > vrxq) {
 901                                         if (vpool > vrxq)
 902                                                 vpool = vrxq;
 903                                         goto found;
 904                                 }
 905                         }
 906                         /* Not enough resources to support VMDq */
 907                         break;
 908                 }
 909         }
 910         /* Not enough resources to support VMDq */
 911         vpool = 0;
 912         vrxq = 0;
 913 found:
 914         dev_info->max_vmdq_pools = vpool;
 915         dev_info->vmdq_queue_num = vrxq;
 916
 917         dev_info->vmdq_pool_base = 0;
 918         dev_info->vmdq_queue_base = 0;
 919
 920         return 0;
 921 }
 922
 923 /* Configure the device based on the configuration provided */
 924 static int bnxt_dev_configure_op(struct rte_eth_dev *eth_dev)
 925 {
 926         struct bnxt *bp = eth_dev->data->dev_private;
 927         uint64_t rx_offloads = eth_dev->data->dev_conf.rxmode.offloads;
 928         int rc;
 929
 930         bp->rx_queues = (void *)eth_dev->data->rx_queues;
 931         bp->tx_queues = (void *)eth_dev->data->tx_queues;
 932         bp->tx_nr_rings = eth_dev->data->nb_tx_queues;
 933         bp->rx_nr_rings = eth_dev->data->nb_rx_queues;
 934
 935         rc = is_bnxt_in_error(bp);
 936         if (rc)
 937                 return rc;
 938
 939         if (BNXT_VF(bp) && (bp->flags & BNXT_FLAG_NEW_RM)) {
 940                 rc = bnxt_hwrm_check_vf_rings(bp);
 941                 if (rc) {
 942                         PMD_DRV_LOG(ERR, "HWRM insufficient resources\n");
 943                         return -ENOSPC;
 944                 }
 945
 946                 /* If a resource has already been allocated - in this case
 947                  * it is the async completion ring, free it. Reallocate it after
 948                  * resource reservation. This will ensure the resource counts
 949                  * are calculated correctly.
 950                  */
 951
 952                 pthread_mutex_lock(&bp->def_cp_lock);
 953
 954                 if (!BNXT_HAS_NQ(bp) && bp->async_cp_ring) {
 955                         bnxt_disable_int(bp);
 956                         bnxt_free_cp_ring(bp, bp->async_cp_ring);
 957                 }
 958
 959                 rc = bnxt_hwrm_func_reserve_vf_resc(bp, false);
 960                 if (rc) {
 961                         PMD_DRV_LOG(ERR, "HWRM resource alloc fail:%x\n", rc);
 962                         pthread_mutex_unlock(&bp->def_cp_lock);
 963                         return -ENOSPC;
 964                 }
 965
 966                 if (!BNXT_HAS_NQ(bp) && bp->async_cp_ring) {
 967                         rc = bnxt_alloc_async_cp_ring(bp);
 968                         if (rc) {
 969                                 pthread_mutex_unlock(&bp->def_cp_lock);
 970                                 return rc;
 971                         }
 972                         bnxt_enable_int(bp);
 973                 }
 974
 975                 pthread_mutex_unlock(&bp->def_cp_lock);
 976         } else {
 977                 /* legacy driver needs to get updated values */
 978                 rc = bnxt_hwrm_func_qcaps(bp);
 979                 if (rc) {
 980                         PMD_DRV_LOG(ERR, "hwrm func qcaps fail:%d\n", rc);
 981                         return rc;
 982                 }
 983         }
 984
 985         /* Inherit new configurations */
 986         if (eth_dev->data->nb_rx_queues > bp->max_rx_rings ||
 987             eth_dev->data->nb_tx_queues > bp->max_tx_rings ||
 988             eth_dev->data->nb_rx_queues + eth_dev->data->nb_tx_queues
 989                 + BNXT_NUM_ASYNC_CPR(bp) > bp->max_cp_rings ||
 990             eth_dev->data->nb_rx_queues + eth_dev->data->nb_tx_queues >
 991             bp->max_stat_ctx)
 992                 goto resource_error;
 993
 994         if (BNXT_HAS_RING_GRPS(bp) &&
 995             (uint32_t)(eth_dev->data->nb_rx_queues) > bp->max_ring_grps)
 996                 goto resource_error;
 997
 998         if (!(eth_dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_RSS) &&
 999             bp->max_vnics < eth_dev->data->nb_rx_queues)
1000                 goto resource_error;
1001
1002         bp->rx_cp_nr_rings = bp->rx_nr_rings;
1003         bp->tx_cp_nr_rings = bp->tx_nr_rings;
1004
1005         if (eth_dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG)
1006                 rx_offloads |= DEV_RX_OFFLOAD_RSS_HASH;
1007         eth_dev->data->dev_conf.rxmode.offloads = rx_offloads;
1008
1009         if (rx_offloads & DEV_RX_OFFLOAD_JUMBO_FRAME) {
1010                 eth_dev->data->mtu =
1011                         eth_dev->data->dev_conf.rxmode.max_rx_pkt_len -
1012                         RTE_ETHER_HDR_LEN - RTE_ETHER_CRC_LEN - VLAN_TAG_SIZE *
1013                         BNXT_NUM_VLANS;
1014                 bnxt_mtu_set_op(eth_dev, eth_dev->data->mtu);
1015         }
1016         return 0;
1017
1018 resource_error:
1019         PMD_DRV_LOG(ERR,
1020                     "Insufficient resources to support requested config\n");
1021         PMD_DRV_LOG(ERR,
1022                     "Num Queues Requested: Tx %d, Rx %d\n",
1023                     eth_dev->data->nb_tx_queues,
1024                     eth_dev->data->nb_rx_queues);
1025         PMD_DRV_LOG(ERR,
1026                     "MAX: TxQ %d, RxQ %d, CQ %d Stat %d, Grp %d, Vnic %d\n",
1027                     bp->max_tx_rings, bp->max_rx_rings, bp->max_cp_rings,
1028                     bp->max_stat_ctx, bp->max_ring_grps, bp->max_vnics);
1029         return -ENOSPC;
1030 }
1031
1032 void bnxt_print_link_info(struct rte_eth_dev *eth_dev)
1033 {
1034         struct rte_eth_link *link = &eth_dev->data->dev_link;
1035
1036         if (link->link_status)
1037                 PMD_DRV_LOG(INFO, "Port %d Link Up - speed %u Mbps - %s\n",
1038                         eth_dev->data->port_id,
1039                         (uint32_t)link->link_speed,
1040                         (link->link_duplex == ETH_LINK_FULL_DUPLEX) ?
1041                         ("full-duplex") : ("half-duplex\n"));
1042         else
1043                 PMD_DRV_LOG(INFO, "Port %d Link Down\n",
1044                         eth_dev->data->port_id);
1045 }
1046
1047 /*
1048  * Determine whether the current configuration requires support for scattered
1049  * receive; return 1 if scattered receive is required and 0 if not.
1050  */
1051 static int bnxt_scattered_rx(struct rte_eth_dev *eth_dev)
1052 {
1053         uint16_t buf_size;
1054         int i;
1055
1056         if (eth_dev->data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_SCATTER)
1057                 return 1;
1058
1059         for (i = 0; i < eth_dev->data->nb_rx_queues; i++) {
1060                 struct bnxt_rx_queue *rxq = eth_dev->data->rx_queues[i];
1061
1062                 buf_size = (uint16_t)(rte_pktmbuf_data_room_size(rxq->mb_pool) -
1063                                       RTE_PKTMBUF_HEADROOM);
1064                 if (eth_dev->data->dev_conf.rxmode.max_rx_pkt_len > buf_size)
1065                         return 1;
1066         }
1067         return 0;
1068 }
1069
1070 static eth_rx_burst_t
1071 bnxt_receive_function(struct rte_eth_dev *eth_dev)
1072 {
1073         struct bnxt *bp = eth_dev->data->dev_private;
1074
1075 #ifdef RTE_ARCH_X86
1076 #ifndef RTE_LIBRTE_IEEE1588
1077         /*
1078          * Vector mode receive can be enabled only if scatter rx is not
1079          * in use and rx offloads are limited to VLAN stripping and
1080          * CRC stripping.
1081          */
1082         if (!eth_dev->data->scattered_rx &&
1083             !(eth_dev->data->dev_conf.rxmode.offloads &
1084               ~(DEV_RX_OFFLOAD_VLAN_STRIP |
1085                 DEV_RX_OFFLOAD_KEEP_CRC |
1086                 DEV_RX_OFFLOAD_JUMBO_FRAME |
1087                 DEV_RX_OFFLOAD_IPV4_CKSUM |
1088                 DEV_RX_OFFLOAD_UDP_CKSUM |
1089                 DEV_RX_OFFLOAD_TCP_CKSUM |
1090                 DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM |
1091                 DEV_RX_OFFLOAD_RSS_HASH |
1092                 DEV_RX_OFFLOAD_VLAN_FILTER)) &&
1093             !BNXT_TRUFLOW_EN(bp)) {
1094                 PMD_DRV_LOG(INFO, "Using vector mode receive for port %d\n",
1095                             eth_dev->data->port_id);
1096                 bp->flags |= BNXT_FLAG_RX_VECTOR_PKT_MODE;
1097                 return bnxt_recv_pkts_vec;
1098         }
1099         PMD_DRV_LOG(INFO, "Vector mode receive disabled for port %d\n",
1100                     eth_dev->data->port_id);
1101         PMD_DRV_LOG(INFO,
1102                     "Port %d scatter: %d rx offload: %" PRIX64 "\n",
1103                     eth_dev->data->port_id,
1104                     eth_dev->data->scattered_rx,
1105                     eth_dev->data->dev_conf.rxmode.offloads);
1106 #endif
1107 #endif
1108         bp->flags &= ~BNXT_FLAG_RX_VECTOR_PKT_MODE;
1109         return bnxt_recv_pkts;
1110 }
1111
1112 static eth_tx_burst_t
1113 bnxt_transmit_function(__rte_unused struct rte_eth_dev *eth_dev)
1114 {
1115 #ifdef RTE_ARCH_X86
1116 #ifndef RTE_LIBRTE_IEEE1588
1117         /*
1118          * Vector mode transmit can be enabled only if not using scatter rx
1119          * or tx offloads.
1120          */
1121         if (!eth_dev->data->scattered_rx &&
1122             !eth_dev->data->dev_conf.txmode.offloads) {
1123                 PMD_DRV_LOG(INFO, "Using vector mode transmit for port %d\n",
1124                             eth_dev->data->port_id);
1125                 return bnxt_xmit_pkts_vec;
1126         }
1127         PMD_DRV_LOG(INFO, "Vector mode transmit disabled for port %d\n",
1128                     eth_dev->data->port_id);
1129         PMD_DRV_LOG(INFO,
1130                     "Port %d scatter: %d tx offload: %" PRIX64 "\n",
1131                     eth_dev->data->port_id,
1132                     eth_dev->data->scattered_rx,
1133                     eth_dev->data->dev_conf.txmode.offloads);
1134 #endif
1135 #endif
1136         return bnxt_xmit_pkts;
1137 }
1138
1139 static int bnxt_handle_if_change_status(struct bnxt *bp)
1140 {
1141         int rc;
1142
1143         /* Since fw has undergone a reset and lost all contexts,
1144          * set fatal flag to not issue hwrm during cleanup
1145          */
1146         bp->flags |= BNXT_FLAG_FATAL_ERROR;
1147         bnxt_uninit_resources(bp, true);
1148
1149         /* clear fatal flag so that re-init happens */
1150         bp->flags &= ~BNXT_FLAG_FATAL_ERROR;
1151         rc = bnxt_init_resources(bp, true);
1152
1153         bp->flags &= ~BNXT_FLAG_IF_CHANGE_HOT_FW_RESET_DONE;
1154
1155         return rc;
1156 }
1157
1158 static int bnxt_dev_start_op(struct rte_eth_dev *eth_dev)
1159 {
1160         struct bnxt *bp = eth_dev->data->dev_private;
1161         uint64_t rx_offloads = eth_dev->data->dev_conf.rxmode.offloads;
1162         int vlan_mask = 0;
1163         int rc, retry_cnt = BNXT_IF_CHANGE_RETRY_COUNT;
1164
1165         if (!eth_dev->data->nb_tx_queues || !eth_dev->data->nb_rx_queues) {
1166                 PMD_DRV_LOG(ERR, "Queues are not configured yet!\n");
1167                 return -EINVAL;
1168         }
1169
1170         if (bp->rx_cp_nr_rings > RTE_ETHDEV_QUEUE_STAT_CNTRS) {
1171                 PMD_DRV_LOG(ERR,
1172                         "RxQ cnt %d > CONFIG_RTE_ETHDEV_QUEUE_STAT_CNTRS %d\n",
1173                         bp->rx_cp_nr_rings, RTE_ETHDEV_QUEUE_STAT_CNTRS);
1174         }
1175
1176         do {
1177                 rc = bnxt_hwrm_if_change(bp, true);
1178                 if (rc == 0 || rc != -EAGAIN)
1179                         break;
1180
1181                 rte_delay_ms(BNXT_IF_CHANGE_RETRY_INTERVAL);
1182         } while (retry_cnt--);
1183
1184         if (rc)
1185                 return rc;
1186
1187         if (bp->flags & BNXT_FLAG_IF_CHANGE_HOT_FW_RESET_DONE) {
1188                 rc = bnxt_handle_if_change_status(bp);
1189                 if (rc)
1190                         return rc;
1191         }
1192
1193         bnxt_enable_int(bp);
1194
1195         rc = bnxt_init_chip(bp);
1196         if (rc)
1197                 goto error;
1198
1199         eth_dev->data->scattered_rx = bnxt_scattered_rx(eth_dev);
1200         eth_dev->data->dev_started = 1;
1201
1202         bnxt_link_update(eth_dev, 1, ETH_LINK_UP);
1203
1204         if (rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER)
1205                 vlan_mask |= ETH_VLAN_FILTER_MASK;
1206         if (rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
1207                 vlan_mask |= ETH_VLAN_STRIP_MASK;
1208         rc = bnxt_vlan_offload_set_op(eth_dev, vlan_mask);
1209         if (rc)
1210                 goto error;
1211
1212         eth_dev->rx_pkt_burst = bnxt_receive_function(eth_dev);
1213         eth_dev->tx_pkt_burst = bnxt_transmit_function(eth_dev);
1214
1215         pthread_mutex_lock(&bp->def_cp_lock);
1216         bnxt_schedule_fw_health_check(bp);
1217         pthread_mutex_unlock(&bp->def_cp_lock);
1218
1219         if (BNXT_TRUFLOW_EN(bp))
1220                 bnxt_ulp_init(bp);
1221
1222         return 0;
1223
1224 error:
1225         bnxt_shutdown_nic(bp);
1226         bnxt_free_tx_mbufs(bp);
1227         bnxt_free_rx_mbufs(bp);
1228         bnxt_hwrm_if_change(bp, false);
1229         eth_dev->data->dev_started = 0;
1230         return rc;
1231 }
1232
1233 static int bnxt_dev_set_link_up_op(struct rte_eth_dev *eth_dev)
1234 {
1235         struct bnxt *bp = eth_dev->data->dev_private;
1236         int rc = 0;
1237
1238         if (!bp->link_info->link_up)
1239                 rc = bnxt_set_hwrm_link_config(bp, true);
1240         if (!rc)
1241                 eth_dev->data->dev_link.link_status = 1;
1242
1243         bnxt_print_link_info(eth_dev);
1244         return rc;
1245 }
1246
1247 static int bnxt_dev_set_link_down_op(struct rte_eth_dev *eth_dev)
1248 {
1249         struct bnxt *bp = eth_dev->data->dev_private;
1250
1251         eth_dev->data->dev_link.link_status = 0;
1252         bnxt_set_hwrm_link_config(bp, false);
1253         bp->link_info->link_up = 0;
1254
1255         return 0;
1256 }
1257
1258 static void bnxt_free_switch_domain(struct bnxt *bp)
1259 {
1260         if (bp->switch_domain_id)
1261                 rte_eth_switch_domain_free(bp->switch_domain_id);
1262 }
1263
1264 /* Unload the driver, release resources */
1265 static void bnxt_dev_stop_op(struct rte_eth_dev *eth_dev)
1266 {
1267         struct bnxt *bp = eth_dev->data->dev_private;
1268         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1269         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1270
1271         if (BNXT_TRUFLOW_EN(bp))
1272                 bnxt_ulp_deinit(bp);
1273
1274         eth_dev->data->dev_started = 0;
1275         /* Prevent crashes when queues are still in use */
1276         eth_dev->rx_pkt_burst = &bnxt_dummy_recv_pkts;
1277         eth_dev->tx_pkt_burst = &bnxt_dummy_xmit_pkts;
1278
1279         bnxt_disable_int(bp);
1280
1281         /* disable uio/vfio intr/eventfd mapping */
1282         rte_intr_disable(intr_handle);
1283
1284         bnxt_cancel_fw_health_check(bp);
1285
1286         bnxt_dev_set_link_down_op(eth_dev);
1287
1288         /* Wait for link to be reset and the async notification to process.
1289          * During reset recovery, there is no need to wait and
1290          * VF/NPAR functions do not have privilege to change PHY config.
1291          */
1292         if (!is_bnxt_in_error(bp) && BNXT_SINGLE_PF(bp))
1293                 bnxt_link_update(eth_dev, 1, ETH_LINK_DOWN);
1294
1295         /* Clean queue intr-vector mapping */
1296         rte_intr_efd_disable(intr_handle);
1297         if (intr_handle->intr_vec != NULL) {
1298                 rte_free(intr_handle->intr_vec);
1299                 intr_handle->intr_vec = NULL;
1300         }
1301
1302         bnxt_hwrm_port_clr_stats(bp);
1303         bnxt_free_tx_mbufs(bp);
1304         bnxt_free_rx_mbufs(bp);
1305         /* Process any remaining notifications in default completion queue */
1306         bnxt_int_handler(eth_dev);
1307         bnxt_shutdown_nic(bp);
1308         bnxt_hwrm_if_change(bp, false);
1309
1310         rte_free(bp->mark_table);
1311         bp->mark_table = NULL;
1312
1313         bp->flags &= ~BNXT_FLAG_RX_VECTOR_PKT_MODE;
1314         bp->rx_cosq_cnt = 0;
1315         /* All filters are deleted on a port stop. */
1316         if (BNXT_FLOW_XSTATS_EN(bp))
1317                 bp->flow_stat->flow_count = 0;
1318 }
1319
1320 static void bnxt_dev_close_op(struct rte_eth_dev *eth_dev)
1321 {
1322         struct bnxt *bp = eth_dev->data->dev_private;
1323
1324         /* cancel the recovery handler before remove dev */
1325         rte_eal_alarm_cancel(bnxt_dev_reset_and_resume, (void *)bp);
1326         rte_eal_alarm_cancel(bnxt_dev_recover, (void *)bp);
1327         bnxt_cancel_fc_thread(bp);
1328
1329         if (eth_dev->data->dev_started)
1330                 bnxt_dev_stop_op(eth_dev);
1331
1332         bnxt_free_switch_domain(bp);
1333
1334         bnxt_uninit_resources(bp, false);
1335
1336         bnxt_free_leds_info(bp);
1337         bnxt_free_cos_queues(bp);
1338         bnxt_free_link_info(bp);
1339         bnxt_free_pf_info(bp);
1340         bnxt_free_parent_info(bp);
1341
1342         eth_dev->dev_ops = NULL;
1343         eth_dev->rx_pkt_burst = NULL;
1344         eth_dev->tx_pkt_burst = NULL;
1345
1346         rte_memzone_free((const struct rte_memzone *)bp->tx_mem_zone);
1347         bp->tx_mem_zone = NULL;
1348         rte_memzone_free((const struct rte_memzone *)bp->rx_mem_zone);
1349         bp->rx_mem_zone = NULL;
1350
1351         rte_free(bp->pf->vf_info);
1352         bp->pf->vf_info = NULL;
1353
1354         rte_free(bp->grp_info);
1355         bp->grp_info = NULL;
1356 }
1357
1358 static void bnxt_mac_addr_remove_op(struct rte_eth_dev *eth_dev,
1359                                     uint32_t index)
1360 {
1361         struct bnxt *bp = eth_dev->data->dev_private;
1362         uint64_t pool_mask = eth_dev->data->mac_pool_sel[index];
1363         struct bnxt_vnic_info *vnic;
1364         struct bnxt_filter_info *filter, *temp_filter;
1365         uint32_t i;
1366
1367         if (is_bnxt_in_error(bp))
1368                 return;
1369
1370         /*
1371          * Loop through all VNICs from the specified filter flow pools to
1372          * remove the corresponding MAC addr filter
1373          */
1374         for (i = 0; i < bp->nr_vnics; i++) {
1375                 if (!(pool_mask & (1ULL << i)))
1376                         continue;
1377
1378                 vnic = &bp->vnic_info[i];
1379                 filter = STAILQ_FIRST(&vnic->filter);
1380                 while (filter) {
1381                         temp_filter = STAILQ_NEXT(filter, next);
1382                         if (filter->mac_index == index) {
1383                                 STAILQ_REMOVE(&vnic->filter, filter,
1384                                                 bnxt_filter_info, next);
1385                                 bnxt_hwrm_clear_l2_filter(bp, filter);
1386                                 bnxt_free_filter(bp, filter);
1387                         }
1388                         filter = temp_filter;
1389                 }
1390         }
1391 }
1392
1393 static int bnxt_add_mac_filter(struct bnxt *bp, struct bnxt_vnic_info *vnic,
1394                                struct rte_ether_addr *mac_addr, uint32_t index,
1395                                uint32_t pool)
1396 {
1397         struct bnxt_filter_info *filter;
1398         int rc = 0;
1399
1400         /* Attach requested MAC address to the new l2_filter */
1401         STAILQ_FOREACH(filter, &vnic->filter, next) {
1402                 if (filter->mac_index == index) {
1403                         PMD_DRV_LOG(DEBUG,
1404                                     "MAC addr already existed for pool %d\n",
1405                                     pool);
1406                         return 0;
1407                 }
1408         }
1409
1410         filter = bnxt_alloc_filter(bp);
1411         if (!filter) {
1412                 PMD_DRV_LOG(ERR, "L2 filter alloc failed\n");
1413                 return -ENODEV;
1414         }
1415
1416         /* bnxt_alloc_filter copies default MAC to filter->l2_addr. So,
1417          * if the MAC that's been programmed now is a different one, then,
1418          * copy that addr to filter->l2_addr
1419          */
1420         if (mac_addr)
1421                 memcpy(filter->l2_addr, mac_addr, RTE_ETHER_ADDR_LEN);
1422         filter->flags |= HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_OUTERMOST;
1423
1424         rc = bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id, filter);
1425         if (!rc) {
1426                 filter->mac_index = index;
1427                 if (filter->mac_index == 0)
1428                         STAILQ_INSERT_HEAD(&vnic->filter, filter, next);
1429                 else
1430                         STAILQ_INSERT_TAIL(&vnic->filter, filter, next);
1431         } else {
1432                 bnxt_free_filter(bp, filter);
1433         }
1434
1435         return rc;
1436 }
1437
1438 static int bnxt_mac_addr_add_op(struct rte_eth_dev *eth_dev,
1439                                 struct rte_ether_addr *mac_addr,
1440                                 uint32_t index, uint32_t pool)
1441 {
1442         struct bnxt *bp = eth_dev->data->dev_private;
1443         struct bnxt_vnic_info *vnic = &bp->vnic_info[pool];
1444         int rc = 0;
1445
1446         rc = is_bnxt_in_error(bp);
1447         if (rc)
1448                 return rc;
1449
1450         if (BNXT_VF(bp) & !BNXT_VF_IS_TRUSTED(bp)) {
1451                 PMD_DRV_LOG(ERR, "Cannot add MAC address to a VF interface\n");
1452                 return -ENOTSUP;
1453         }
1454
1455         if (!vnic) {
1456                 PMD_DRV_LOG(ERR, "VNIC not found for pool %d!\n", pool);
1457                 return -EINVAL;
1458         }
1459
1460         /* Filter settings will get applied when port is started */
1461         if (!eth_dev->data->dev_started)
1462                 return 0;
1463
1464         rc = bnxt_add_mac_filter(bp, vnic, mac_addr, index, pool);
1465
1466         return rc;
1467 }
1468
1469 int bnxt_link_update(struct rte_eth_dev *eth_dev, int wait_to_complete,
1470                      bool exp_link_status)
1471 {
1472         int rc = 0;
1473         struct bnxt *bp = eth_dev->data->dev_private;
1474         struct rte_eth_link new;
1475         int cnt = exp_link_status ? BNXT_LINK_UP_WAIT_CNT :
1476                   BNXT_LINK_DOWN_WAIT_CNT;
1477
1478         rc = is_bnxt_in_error(bp);
1479         if (rc)
1480                 return rc;
1481
1482         memset(&new, 0, sizeof(new));
1483         do {
1484                 /* Retrieve link info from hardware */
1485                 rc = bnxt_get_hwrm_link_config(bp, &new);
1486                 if (rc) {
1487                         new.link_speed = ETH_LINK_SPEED_100M;
1488                         new.link_duplex = ETH_LINK_FULL_DUPLEX;
1489                         PMD_DRV_LOG(ERR,
1490                                 "Failed to retrieve link rc = 0x%x!\n", rc);
1491                         goto out;
1492                 }
1493
1494                 if (!wait_to_complete || new.link_status == exp_link_status)
1495                         break;
1496
1497                 rte_delay_ms(BNXT_LINK_WAIT_INTERVAL);
1498         } while (cnt--);
1499
1500 out:
1501         /* Timed out or success */
1502         if (new.link_status != eth_dev->data->dev_link.link_status ||
1503         new.link_speed != eth_dev->data->dev_link.link_speed) {
1504                 rte_eth_linkstatus_set(eth_dev, &new);
1505
1506                 _rte_eth_dev_callback_process(eth_dev,
1507                                               RTE_ETH_EVENT_INTR_LSC,
1508                                               NULL);
1509
1510                 bnxt_print_link_info(eth_dev);
1511         }
1512
1513         return rc;
1514 }
1515
1516 int bnxt_link_update_op(struct rte_eth_dev *eth_dev,
1517                         int wait_to_complete)
1518 {
1519         return bnxt_link_update(eth_dev, wait_to_complete, ETH_LINK_UP);
1520 }
1521
1522 static int bnxt_promiscuous_enable_op(struct rte_eth_dev *eth_dev)
1523 {
1524         struct bnxt *bp = eth_dev->data->dev_private;
1525         struct bnxt_vnic_info *vnic;
1526         uint32_t old_flags;
1527         int rc;
1528
1529         rc = is_bnxt_in_error(bp);
1530         if (rc)
1531                 return rc;
1532
1533         /* Filter settings will get applied when port is started */
1534         if (!eth_dev->data->dev_started)
1535                 return 0;
1536
1537         if (bp->vnic_info == NULL)
1538                 return 0;
1539
1540         vnic = BNXT_GET_DEFAULT_VNIC(bp);
1541
1542         old_flags = vnic->flags;
1543         vnic->flags |= BNXT_VNIC_INFO_PROMISC;
1544         rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1545         if (rc != 0)
1546                 vnic->flags = old_flags;
1547
1548         return rc;
1549 }
1550
1551 static int bnxt_promiscuous_disable_op(struct rte_eth_dev *eth_dev)
1552 {
1553         struct bnxt *bp = eth_dev->data->dev_private;
1554         struct bnxt_vnic_info *vnic;
1555         uint32_t old_flags;
1556         int rc;
1557
1558         rc = is_bnxt_in_error(bp);
1559         if (rc)
1560                 return rc;
1561
1562         /* Filter settings will get applied when port is started */
1563         if (!eth_dev->data->dev_started)
1564                 return 0;
1565
1566         if (bp->vnic_info == NULL)
1567                 return 0;
1568
1569         vnic = BNXT_GET_DEFAULT_VNIC(bp);
1570
1571         old_flags = vnic->flags;
1572         vnic->flags &= ~BNXT_VNIC_INFO_PROMISC;
1573         rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1574         if (rc != 0)
1575                 vnic->flags = old_flags;
1576
1577         return rc;
1578 }
1579
1580 static int bnxt_allmulticast_enable_op(struct rte_eth_dev *eth_dev)
1581 {
1582         struct bnxt *bp = eth_dev->data->dev_private;
1583         struct bnxt_vnic_info *vnic;
1584         uint32_t old_flags;
1585         int rc;
1586
1587         rc = is_bnxt_in_error(bp);
1588         if (rc)
1589                 return rc;
1590
1591         /* Filter settings will get applied when port is started */
1592         if (!eth_dev->data->dev_started)
1593                 return 0;
1594
1595         if (bp->vnic_info == NULL)
1596                 return 0;
1597
1598         vnic = BNXT_GET_DEFAULT_VNIC(bp);
1599
1600         old_flags = vnic->flags;
1601         vnic->flags |= BNXT_VNIC_INFO_ALLMULTI;
1602         rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1603         if (rc != 0)
1604                 vnic->flags = old_flags;
1605
1606         return rc;
1607 }
1608
1609 static int bnxt_allmulticast_disable_op(struct rte_eth_dev *eth_dev)
1610 {
1611         struct bnxt *bp = eth_dev->data->dev_private;
1612         struct bnxt_vnic_info *vnic;
1613         uint32_t old_flags;
1614         int rc;
1615
1616         rc = is_bnxt_in_error(bp);
1617         if (rc)
1618                 return rc;
1619
1620         /* Filter settings will get applied when port is started */
1621         if (!eth_dev->data->dev_started)
1622                 return 0;
1623
1624         if (bp->vnic_info == NULL)
1625                 return 0;
1626
1627         vnic = BNXT_GET_DEFAULT_VNIC(bp);
1628
1629         old_flags = vnic->flags;
1630         vnic->flags &= ~BNXT_VNIC_INFO_ALLMULTI;
1631         rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1632         if (rc != 0)
1633                 vnic->flags = old_flags;
1634
1635         return rc;
1636 }
1637
1638 /* Return bnxt_rx_queue pointer corresponding to a given rxq. */
1639 static struct bnxt_rx_queue *bnxt_qid_to_rxq(struct bnxt *bp, uint16_t qid)
1640 {
1641         if (qid >= bp->rx_nr_rings)
1642                 return NULL;
1643
1644         return bp->eth_dev->data->rx_queues[qid];
1645 }
1646
1647 /* Return rxq corresponding to a given rss table ring/group ID. */
1648 static uint16_t bnxt_rss_to_qid(struct bnxt *bp, uint16_t fwr)
1649 {
1650         struct bnxt_rx_queue *rxq;
1651         unsigned int i;
1652
1653         if (!BNXT_HAS_RING_GRPS(bp)) {
1654                 for (i = 0; i < bp->rx_nr_rings; i++) {
1655                         rxq = bp->eth_dev->data->rx_queues[i];
1656                         if (rxq->rx_ring->rx_ring_struct->fw_ring_id == fwr)
1657                                 return rxq->index;
1658                 }
1659         } else {
1660                 for (i = 0; i < bp->rx_nr_rings; i++) {
1661                         if (bp->grp_info[i].fw_grp_id == fwr)
1662                                 return i;
1663                 }
1664         }
1665
1666         return INVALID_HW_RING_ID;
1667 }
1668
1669 static int bnxt_reta_update_op(struct rte_eth_dev *eth_dev,
1670                             struct rte_eth_rss_reta_entry64 *reta_conf,
1671                             uint16_t reta_size)
1672 {
1673         struct bnxt *bp = eth_dev->data->dev_private;
1674         struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
1675         struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp);
1676         uint16_t tbl_size = bnxt_rss_hash_tbl_size(bp);
1677         uint16_t idx, sft;
1678         int i, rc;
1679
1680         rc = is_bnxt_in_error(bp);
1681         if (rc)
1682                 return rc;
1683
1684         if (!vnic->rss_table)
1685                 return -EINVAL;
1686
1687         if (!(dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG))
1688                 return -EINVAL;
1689
1690         if (reta_size != tbl_size) {
1691                 PMD_DRV_LOG(ERR, "The configured hash table lookup size "
1692                         "(%d) must equal the size supported by the hardware "
1693                         "(%d)\n", reta_size, tbl_size);
1694                 return -EINVAL;
1695         }
1696
1697         for (i = 0; i < reta_size; i++) {
1698                 struct bnxt_rx_queue *rxq;
1699
1700                 idx = i / RTE_RETA_GROUP_SIZE;
1701                 sft = i % RTE_RETA_GROUP_SIZE;
1702
1703                 if (!(reta_conf[idx].mask & (1ULL << sft)))
1704                         continue;
1705
1706                 rxq = bnxt_qid_to_rxq(bp, reta_conf[idx].reta[sft]);
1707                 if (!rxq) {
1708                         PMD_DRV_LOG(ERR, "Invalid ring in reta_conf.\n");
1709                         return -EINVAL;
1710                 }
1711
1712                 if (BNXT_CHIP_THOR(bp)) {
1713                         vnic->rss_table[i * 2] =
1714                                 rxq->rx_ring->rx_ring_struct->fw_ring_id;
1715                         vnic->rss_table[i * 2 + 1] =
1716                                 rxq->cp_ring->cp_ring_struct->fw_ring_id;
1717                 } else {
1718                         vnic->rss_table[i] =
1719                             vnic->fw_grp_ids[reta_conf[idx].reta[sft]];
1720                 }
1721         }
1722
1723         bnxt_hwrm_vnic_rss_cfg(bp, vnic);
1724         return 0;
1725 }
1726
1727 static int bnxt_reta_query_op(struct rte_eth_dev *eth_dev,
1728                               struct rte_eth_rss_reta_entry64 *reta_conf,
1729                               uint16_t reta_size)
1730 {
1731         struct bnxt *bp = eth_dev->data->dev_private;
1732         struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp);
1733         uint16_t tbl_size = bnxt_rss_hash_tbl_size(bp);
1734         uint16_t idx, sft, i;
1735         int rc;
1736
1737         rc = is_bnxt_in_error(bp);
1738         if (rc)
1739                 return rc;
1740
1741         /* Retrieve from the default VNIC */
1742         if (!vnic)
1743                 return -EINVAL;
1744         if (!vnic->rss_table)
1745                 return -EINVAL;
1746
1747         if (reta_size != tbl_size) {
1748                 PMD_DRV_LOG(ERR, "The configured hash table lookup size "
1749                         "(%d) must equal the size supported by the hardware "
1750                         "(%d)\n", reta_size, tbl_size);
1751                 return -EINVAL;
1752         }
1753
1754         for (idx = 0, i = 0; i < reta_size; i++) {
1755                 idx = i / RTE_RETA_GROUP_SIZE;
1756                 sft = i % RTE_RETA_GROUP_SIZE;
1757
1758                 if (reta_conf[idx].mask & (1ULL << sft)) {
1759                         uint16_t qid;
1760
1761                         if (BNXT_CHIP_THOR(bp))
1762                                 qid = bnxt_rss_to_qid(bp,
1763                                                       vnic->rss_table[i * 2]);
1764                         else
1765                                 qid = bnxt_rss_to_qid(bp, vnic->rss_table[i]);
1766
1767                         if (qid == INVALID_HW_RING_ID) {
1768                                 PMD_DRV_LOG(ERR, "Inv. entry in rss table.\n");
1769                                 return -EINVAL;
1770                         }
1771                         reta_conf[idx].reta[sft] = qid;
1772                 }
1773         }
1774
1775         return 0;
1776 }
1777
1778 static int bnxt_rss_hash_update_op(struct rte_eth_dev *eth_dev,
1779                                    struct rte_eth_rss_conf *rss_conf)
1780 {
1781         struct bnxt *bp = eth_dev->data->dev_private;
1782         struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
1783         struct bnxt_vnic_info *vnic;
1784         int rc;
1785
1786         rc = is_bnxt_in_error(bp);
1787         if (rc)
1788                 return rc;
1789
1790         /*
1791          * If RSS enablement were different than dev_configure,
1792          * then return -EINVAL
1793          */
1794         if (dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG) {
1795                 if (!rss_conf->rss_hf)
1796                         PMD_DRV_LOG(ERR, "Hash type NONE\n");
1797         } else {
1798                 if (rss_conf->rss_hf & BNXT_ETH_RSS_SUPPORT)
1799                         return -EINVAL;
1800         }
1801
1802         bp->flags |= BNXT_FLAG_UPDATE_HASH;
1803         memcpy(&eth_dev->data->dev_conf.rx_adv_conf.rss_conf,
1804                rss_conf,
1805                sizeof(*rss_conf));
1806
1807         /* Update the default RSS VNIC(s) */
1808         vnic = BNXT_GET_DEFAULT_VNIC(bp);
1809         vnic->hash_type = bnxt_rte_to_hwrm_hash_types(rss_conf->rss_hf);
1810
1811         /*
1812          * If hashkey is not specified, use the previously configured
1813          * hashkey
1814          */
1815         if (!rss_conf->rss_key)
1816                 goto rss_config;
1817
1818         if (rss_conf->rss_key_len != HW_HASH_KEY_SIZE) {
1819                 PMD_DRV_LOG(ERR,
1820                             "Invalid hashkey length, should be 16 bytes\n");
1821                 return -EINVAL;
1822         }
1823         memcpy(vnic->rss_hash_key, rss_conf->rss_key, rss_conf->rss_key_len);
1824
1825 rss_config:
1826         bnxt_hwrm_vnic_rss_cfg(bp, vnic);
1827         return 0;
1828 }
1829
1830 static int bnxt_rss_hash_conf_get_op(struct rte_eth_dev *eth_dev,
1831                                      struct rte_eth_rss_conf *rss_conf)
1832 {
1833         struct bnxt *bp = eth_dev->data->dev_private;
1834         struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp);
1835         int len, rc;
1836         uint32_t hash_types;
1837
1838         rc = is_bnxt_in_error(bp);
1839         if (rc)
1840                 return rc;
1841
1842         /* RSS configuration is the same for all VNICs */
1843         if (vnic && vnic->rss_hash_key) {
1844                 if (rss_conf->rss_key) {
1845                         len = rss_conf->rss_key_len <= HW_HASH_KEY_SIZE ?
1846                               rss_conf->rss_key_len : HW_HASH_KEY_SIZE;
1847                         memcpy(rss_conf->rss_key, vnic->rss_hash_key, len);
1848                 }
1849
1850                 hash_types = vnic->hash_type;
1851                 rss_conf->rss_hf = 0;
1852                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV4) {
1853                         rss_conf->rss_hf |= ETH_RSS_IPV4;
1854                         hash_types &= ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV4;
1855                 }
1856                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV4) {
1857                         rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP;
1858                         hash_types &=
1859                                 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV4;
1860                 }
1861                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV4) {
1862                         rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
1863                         hash_types &=
1864                                 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV4;
1865                 }
1866                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6) {
1867                         rss_conf->rss_hf |= ETH_RSS_IPV6;
1868                         hash_types &= ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6;
1869                 }
1870                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV6) {
1871                         rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV6_TCP;
1872                         hash_types &=
1873                                 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV6;
1874                 }
1875                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV6) {
1876                         rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;
1877                         hash_types &=
1878                                 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV6;
1879                 }
1880                 if (hash_types) {
1881                         PMD_DRV_LOG(ERR,
1882                                 "Unknown RSS config from firmware (%08x), RSS disabled",
1883                                 vnic->hash_type);
1884                         return -ENOTSUP;
1885                 }
1886         } else {
1887                 rss_conf->rss_hf = 0;
1888         }
1889         return 0;
1890 }
1891
1892 static int bnxt_flow_ctrl_get_op(struct rte_eth_dev *dev,
1893                                struct rte_eth_fc_conf *fc_conf)
1894 {
1895         struct bnxt *bp = dev->data->dev_private;
1896         struct rte_eth_link link_info;
1897         int rc;
1898
1899         rc = is_bnxt_in_error(bp);
1900         if (rc)
1901                 return rc;
1902
1903         rc = bnxt_get_hwrm_link_config(bp, &link_info);
1904         if (rc)
1905                 return rc;
1906
1907         memset(fc_conf, 0, sizeof(*fc_conf));
1908         if (bp->link_info->auto_pause)
1909                 fc_conf->autoneg = 1;
1910         switch (bp->link_info->pause) {
1911         case 0:
1912                 fc_conf->mode = RTE_FC_NONE;
1913                 break;
1914         case HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_TX:
1915                 fc_conf->mode = RTE_FC_TX_PAUSE;
1916                 break;
1917         case HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_RX:
1918                 fc_conf->mode = RTE_FC_RX_PAUSE;
1919                 break;
1920         case (HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_TX |
1921                         HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_RX):
1922                 fc_conf->mode = RTE_FC_FULL;
1923                 break;
1924         }
1925         return 0;
1926 }
1927
1928 static int bnxt_flow_ctrl_set_op(struct rte_eth_dev *dev,
1929                                struct rte_eth_fc_conf *fc_conf)
1930 {
1931         struct bnxt *bp = dev->data->dev_private;
1932         int rc;
1933
1934         rc = is_bnxt_in_error(bp);
1935         if (rc)
1936                 return rc;
1937
1938         if (!BNXT_SINGLE_PF(bp) || BNXT_VF(bp)) {
1939                 PMD_DRV_LOG(ERR, "Flow Control Settings cannot be modified\n");
1940                 return -ENOTSUP;
1941         }
1942
1943         switch (fc_conf->mode) {
1944         case RTE_FC_NONE:
1945                 bp->link_info->auto_pause = 0;
1946                 bp->link_info->force_pause = 0;
1947                 break;
1948         case RTE_FC_RX_PAUSE:
1949                 if (fc_conf->autoneg) {
1950                         bp->link_info->auto_pause =
1951                                         HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_RX;
1952                         bp->link_info->force_pause = 0;
1953                 } else {
1954                         bp->link_info->auto_pause = 0;
1955                         bp->link_info->force_pause =
1956                                         HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_RX;
1957                 }
1958                 break;
1959         case RTE_FC_TX_PAUSE:
1960                 if (fc_conf->autoneg) {
1961                         bp->link_info->auto_pause =
1962                                         HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_TX;
1963                         bp->link_info->force_pause = 0;
1964                 } else {
1965                         bp->link_info->auto_pause = 0;
1966                         bp->link_info->force_pause =
1967                                         HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_TX;
1968                 }
1969                 break;
1970         case RTE_FC_FULL:
1971                 if (fc_conf->autoneg) {
1972                         bp->link_info->auto_pause =
1973                                         HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_TX |
1974                                         HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_RX;
1975                         bp->link_info->force_pause = 0;
1976                 } else {
1977                         bp->link_info->auto_pause = 0;
1978                         bp->link_info->force_pause =
1979                                         HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_TX |
1980                                         HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_RX;
1981                 }
1982                 break;
1983         }
1984         return bnxt_set_hwrm_link_config(bp, true);
1985 }
1986
1987 /* Add UDP tunneling port */
1988 static int
1989 bnxt_udp_tunnel_port_add_op(struct rte_eth_dev *eth_dev,
1990                          struct rte_eth_udp_tunnel *udp_tunnel)
1991 {
1992         struct bnxt *bp = eth_dev->data->dev_private;
1993         uint16_t tunnel_type = 0;
1994         int rc = 0;
1995
1996         rc = is_bnxt_in_error(bp);
1997         if (rc)
1998                 return rc;
1999
2000         switch (udp_tunnel->prot_type) {
2001         case RTE_TUNNEL_TYPE_VXLAN:
2002                 if (bp->vxlan_port_cnt) {
2003                         PMD_DRV_LOG(ERR, "Tunnel Port %d already programmed\n",
2004                                 udp_tunnel->udp_port);
2005                         if (bp->vxlan_port != udp_tunnel->udp_port) {
2006                                 PMD_DRV_LOG(ERR, "Only one port allowed\n");
2007                                 return -ENOSPC;
2008                         }
2009                         bp->vxlan_port_cnt++;
2010                         return 0;
2011                 }
2012                 tunnel_type =
2013                         HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_VXLAN;
2014                 bp->vxlan_port_cnt++;
2015                 break;
2016         case RTE_TUNNEL_TYPE_GENEVE:
2017                 if (bp->geneve_port_cnt) {
2018                         PMD_DRV_LOG(ERR, "Tunnel Port %d already programmed\n",
2019                                 udp_tunnel->udp_port);
2020                         if (bp->geneve_port != udp_tunnel->udp_port) {
2021                                 PMD_DRV_LOG(ERR, "Only one port allowed\n");
2022                                 return -ENOSPC;
2023                         }
2024                         bp->geneve_port_cnt++;
2025                         return 0;
2026                 }
2027                 tunnel_type =
2028                         HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_GENEVE;
2029                 bp->geneve_port_cnt++;
2030                 break;
2031         default:
2032                 PMD_DRV_LOG(ERR, "Tunnel type is not supported\n");
2033                 return -ENOTSUP;
2034         }
2035         rc = bnxt_hwrm_tunnel_dst_port_alloc(bp, udp_tunnel->udp_port,
2036                                              tunnel_type);
2037         return rc;
2038 }
2039
2040 static int
2041 bnxt_udp_tunnel_port_del_op(struct rte_eth_dev *eth_dev,
2042                          struct rte_eth_udp_tunnel *udp_tunnel)
2043 {
2044         struct bnxt *bp = eth_dev->data->dev_private;
2045         uint16_t tunnel_type = 0;
2046         uint16_t port = 0;
2047         int rc = 0;
2048
2049         rc = is_bnxt_in_error(bp);
2050         if (rc)
2051                 return rc;
2052
2053         switch (udp_tunnel->prot_type) {
2054         case RTE_TUNNEL_TYPE_VXLAN:
2055                 if (!bp->vxlan_port_cnt) {
2056                         PMD_DRV_LOG(ERR, "No Tunnel port configured yet\n");
2057                         return -EINVAL;
2058                 }
2059                 if (bp->vxlan_port != udp_tunnel->udp_port) {
2060                         PMD_DRV_LOG(ERR, "Req Port: %d. Configured port: %d\n",
2061                                 udp_tunnel->udp_port, bp->vxlan_port);
2062                         return -EINVAL;
2063                 }
2064                 if (--bp->vxlan_port_cnt)
2065                         return 0;
2066
2067                 tunnel_type =
2068                         HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN;
2069                 port = bp->vxlan_fw_dst_port_id;
2070                 break;
2071         case RTE_TUNNEL_TYPE_GENEVE:
2072                 if (!bp->geneve_port_cnt) {
2073                         PMD_DRV_LOG(ERR, "No Tunnel port configured yet\n");
2074                         return -EINVAL;
2075                 }
2076                 if (bp->geneve_port != udp_tunnel->udp_port) {
2077                         PMD_DRV_LOG(ERR, "Req Port: %d. Configured port: %d\n",
2078                                 udp_tunnel->udp_port, bp->geneve_port);
2079                         return -EINVAL;
2080                 }
2081                 if (--bp->geneve_port_cnt)
2082                         return 0;
2083
2084                 tunnel_type =
2085                         HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_GENEVE;
2086                 port = bp->geneve_fw_dst_port_id;
2087                 break;
2088         default:
2089                 PMD_DRV_LOG(ERR, "Tunnel type is not supported\n");
2090                 return -ENOTSUP;
2091         }
2092
2093         rc = bnxt_hwrm_tunnel_dst_port_free(bp, port, tunnel_type);
2094         if (!rc) {
2095                 if (tunnel_type ==
2096                     HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN)
2097                         bp->vxlan_port = 0;
2098                 if (tunnel_type ==
2099                     HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_GENEVE)
2100                         bp->geneve_port = 0;
2101         }
2102         return rc;
2103 }
2104
2105 static int bnxt_del_vlan_filter(struct bnxt *bp, uint16_t vlan_id)
2106 {
2107         struct bnxt_filter_info *filter;
2108         struct bnxt_vnic_info *vnic;
2109         int rc = 0;
2110         uint32_t chk = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN;
2111
2112         vnic = BNXT_GET_DEFAULT_VNIC(bp);
2113         filter = STAILQ_FIRST(&vnic->filter);
2114         while (filter) {
2115                 /* Search for this matching MAC+VLAN filter */
2116                 if (bnxt_vlan_filter_exists(bp, filter, chk, vlan_id)) {
2117                         /* Delete the filter */
2118                         rc = bnxt_hwrm_clear_l2_filter(bp, filter);
2119                         if (rc)
2120                                 return rc;
2121                         STAILQ_REMOVE(&vnic->filter, filter,
2122                                       bnxt_filter_info, next);
2123                         bnxt_free_filter(bp, filter);
2124                         PMD_DRV_LOG(INFO,
2125                                     "Deleted vlan filter for %d\n",
2126                                     vlan_id);
2127                         return 0;
2128                 }
2129                 filter = STAILQ_NEXT(filter, next);
2130         }
2131         return -ENOENT;
2132 }
2133
2134 static int bnxt_add_vlan_filter(struct bnxt *bp, uint16_t vlan_id)
2135 {
2136         struct bnxt_filter_info *filter;
2137         struct bnxt_vnic_info *vnic;
2138         int rc = 0;
2139         uint32_t en = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN |
2140                 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN_MASK;
2141         uint32_t chk = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN;
2142
2143         /* Implementation notes on the use of VNIC in this command:
2144          *
2145          * By default, these filters belong to default vnic for the function.
2146          * Once these filters are set up, only destination VNIC can be modified.
2147          * If the destination VNIC is not specified in this command,
2148          * then the HWRM shall only create an l2 context id.
2149          */
2150
2151         vnic = BNXT_GET_DEFAULT_VNIC(bp);
2152         filter = STAILQ_FIRST(&vnic->filter);
2153         /* Check if the VLAN has already been added */
2154         while (filter) {
2155                 if (bnxt_vlan_filter_exists(bp, filter, chk, vlan_id))
2156                         return -EEXIST;
2157
2158                 filter = STAILQ_NEXT(filter, next);
2159         }
2160
2161         /* No match found. Alloc a fresh filter and issue the L2_FILTER_ALLOC
2162          * command to create MAC+VLAN filter with the right flags, enables set.
2163          */
2164         filter = bnxt_alloc_filter(bp);
2165         if (!filter) {
2166                 PMD_DRV_LOG(ERR,
2167                             "MAC/VLAN filter alloc failed\n");
2168                 return -ENOMEM;
2169         }
2170         /* MAC + VLAN ID filter */
2171         /* If l2_ivlan == 0 and l2_ivlan_mask != 0, only
2172          * untagged packets are received
2173          *
2174          * If l2_ivlan != 0 and l2_ivlan_mask != 0, untagged
2175          * packets and only the programmed vlan's packets are received
2176          */
2177         filter->l2_ivlan = vlan_id;
2178         filter->l2_ivlan_mask = 0x0FFF;
2179         filter->enables |= en;
2180         filter->flags |= HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_OUTERMOST;
2181
2182         rc = bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id, filter);
2183         if (rc) {
2184                 /* Free the newly allocated filter as we were
2185                  * not able to create the filter in hardware.
2186                  */
2187                 bnxt_free_filter(bp, filter);
2188                 return rc;
2189         }
2190
2191         filter->mac_index = 0;
2192         /* Add this new filter to the list */
2193         if (vlan_id == 0)
2194                 STAILQ_INSERT_HEAD(&vnic->filter, filter, next);
2195         else
2196                 STAILQ_INSERT_TAIL(&vnic->filter, filter, next);
2197
2198         PMD_DRV_LOG(INFO,
2199                     "Added Vlan filter for %d\n", vlan_id);
2200         return rc;
2201 }
2202
2203 static int bnxt_vlan_filter_set_op(struct rte_eth_dev *eth_dev,
2204                 uint16_t vlan_id, int on)
2205 {
2206         struct bnxt *bp = eth_dev->data->dev_private;
2207         int rc;
2208
2209         rc = is_bnxt_in_error(bp);
2210         if (rc)
2211                 return rc;
2212
2213         if (!eth_dev->data->dev_started) {
2214                 PMD_DRV_LOG(ERR, "port must be started before setting vlan\n");
2215                 return -EINVAL;
2216         }
2217
2218         /* These operations apply to ALL existing MAC/VLAN filters */
2219         if (on)
2220                 return bnxt_add_vlan_filter(bp, vlan_id);
2221         else
2222                 return bnxt_del_vlan_filter(bp, vlan_id);
2223 }
2224
2225 static int bnxt_del_dflt_mac_filter(struct bnxt *bp,
2226                                     struct bnxt_vnic_info *vnic)
2227 {
2228         struct bnxt_filter_info *filter;
2229         int rc;
2230
2231         filter = STAILQ_FIRST(&vnic->filter);
2232         while (filter) {
2233                 if (filter->mac_index == 0 &&
2234                     !memcmp(filter->l2_addr, bp->mac_addr,
2235                             RTE_ETHER_ADDR_LEN)) {
2236                         rc = bnxt_hwrm_clear_l2_filter(bp, filter);
2237                         if (!rc) {
2238                                 STAILQ_REMOVE(&vnic->filter, filter,
2239                                               bnxt_filter_info, next);
2240                                 bnxt_free_filter(bp, filter);
2241                         }
2242                         return rc;
2243                 }
2244                 filter = STAILQ_NEXT(filter, next);
2245         }
2246         return 0;
2247 }
2248
2249 static int
2250 bnxt_config_vlan_hw_filter(struct bnxt *bp, uint64_t rx_offloads)
2251 {
2252         struct bnxt_vnic_info *vnic;
2253         unsigned int i;
2254         int rc;
2255
2256         vnic = BNXT_GET_DEFAULT_VNIC(bp);
2257         if (!(rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER)) {
2258                 /* Remove any VLAN filters programmed */
2259                 for (i = 0; i < RTE_ETHER_MAX_VLAN_ID; i++)
2260                         bnxt_del_vlan_filter(bp, i);
2261
2262                 rc = bnxt_add_mac_filter(bp, vnic, NULL, 0, 0);
2263                 if (rc)
2264                         return rc;
2265         } else {
2266                 /* Default filter will allow packets that match the
2267                  * dest mac. So, it has to be deleted, otherwise, we
2268                  * will endup receiving vlan packets for which the
2269                  * filter is not programmed, when hw-vlan-filter
2270                  * configuration is ON
2271                  */
2272                 bnxt_del_dflt_mac_filter(bp, vnic);
2273                 /* This filter will allow only untagged packets */
2274                 bnxt_add_vlan_filter(bp, 0);
2275         }
2276         PMD_DRV_LOG(DEBUG, "VLAN Filtering: %d\n",
2277                     !!(rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER));
2278
2279         return 0;
2280 }
2281
2282 static int bnxt_free_one_vnic(struct bnxt *bp, uint16_t vnic_id)
2283 {
2284         struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id];
2285         unsigned int i;
2286         int rc;
2287
2288         /* Destroy vnic filters and vnic */
2289         if (bp->eth_dev->data->dev_conf.rxmode.offloads &
2290             DEV_RX_OFFLOAD_VLAN_FILTER) {
2291                 for (i = 0; i < RTE_ETHER_MAX_VLAN_ID; i++)
2292                         bnxt_del_vlan_filter(bp, i);
2293         }
2294         bnxt_del_dflt_mac_filter(bp, vnic);
2295
2296         rc = bnxt_hwrm_vnic_free(bp, vnic);
2297         if (rc)
2298                 return rc;
2299
2300         rte_free(vnic->fw_grp_ids);
2301         vnic->fw_grp_ids = NULL;
2302
2303         vnic->rx_queue_cnt = 0;
2304
2305         return 0;
2306 }
2307
2308 static int
2309 bnxt_config_vlan_hw_stripping(struct bnxt *bp, uint64_t rx_offloads)
2310 {
2311         struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp);
2312         int rc;
2313
2314         /* Destroy, recreate and reconfigure the default vnic */
2315         rc = bnxt_free_one_vnic(bp, 0);
2316         if (rc)
2317                 return rc;
2318
2319         /* default vnic 0 */
2320         rc = bnxt_setup_one_vnic(bp, 0);
2321         if (rc)
2322                 return rc;
2323
2324         if (bp->eth_dev->data->dev_conf.rxmode.offloads &
2325             DEV_RX_OFFLOAD_VLAN_FILTER) {
2326                 rc = bnxt_add_vlan_filter(bp, 0);
2327                 if (rc)
2328                         return rc;
2329                 rc = bnxt_restore_vlan_filters(bp);
2330                 if (rc)
2331                         return rc;
2332         } else {
2333                 rc = bnxt_add_mac_filter(bp, vnic, NULL, 0, 0);
2334                 if (rc)
2335                         return rc;
2336         }
2337
2338         rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
2339         if (rc)
2340                 return rc;
2341
2342         PMD_DRV_LOG(DEBUG, "VLAN Strip Offload: %d\n",
2343                     !!(rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP));
2344
2345         return rc;
2346 }
2347
2348 static int
2349 bnxt_vlan_offload_set_op(struct rte_eth_dev *dev, int mask)
2350 {
2351         uint64_t rx_offloads = dev->data->dev_conf.rxmode.offloads;
2352         struct bnxt *bp = dev->data->dev_private;
2353         int rc;
2354
2355         rc = is_bnxt_in_error(bp);
2356         if (rc)
2357                 return rc;
2358
2359         /* Filter settings will get applied when port is started */
2360         if (!dev->data->dev_started)
2361                 return 0;
2362
2363         if (mask & ETH_VLAN_FILTER_MASK) {
2364                 /* Enable or disable VLAN filtering */
2365                 rc = bnxt_config_vlan_hw_filter(bp, rx_offloads);
2366                 if (rc)
2367                         return rc;
2368         }
2369
2370         if (mask & ETH_VLAN_STRIP_MASK) {
2371                 /* Enable or disable VLAN stripping */
2372                 rc = bnxt_config_vlan_hw_stripping(bp, rx_offloads);
2373                 if (rc)
2374                         return rc;
2375         }
2376
2377         if (mask & ETH_VLAN_EXTEND_MASK) {
2378                 if (rx_offloads & DEV_RX_OFFLOAD_VLAN_EXTEND)
2379                         PMD_DRV_LOG(DEBUG, "Extend VLAN supported\n");
2380                 else
2381                         PMD_DRV_LOG(INFO, "Extend VLAN unsupported\n");
2382         }
2383
2384         return 0;
2385 }
2386
2387 static int
2388 bnxt_vlan_tpid_set_op(struct rte_eth_dev *dev, enum rte_vlan_type vlan_type,
2389                       uint16_t tpid)
2390 {
2391         struct bnxt *bp = dev->data->dev_private;
2392         int qinq = dev->data->dev_conf.rxmode.offloads &
2393                    DEV_RX_OFFLOAD_VLAN_EXTEND;
2394
2395         if (vlan_type != ETH_VLAN_TYPE_INNER &&
2396             vlan_type != ETH_VLAN_TYPE_OUTER) {
2397                 PMD_DRV_LOG(ERR,
2398                             "Unsupported vlan type.");
2399                 return -EINVAL;
2400         }
2401         if (!qinq) {
2402                 PMD_DRV_LOG(ERR,
2403                             "QinQ not enabled. Needs to be ON as we can "
2404                             "accelerate only outer vlan\n");
2405                 return -EINVAL;
2406         }
2407
2408         if (vlan_type == ETH_VLAN_TYPE_OUTER) {
2409                 switch (tpid) {
2410                 case RTE_ETHER_TYPE_QINQ:
2411                         bp->outer_tpid_bd =
2412                                 TX_BD_LONG_CFA_META_VLAN_TPID_TPID88A8;
2413                                 break;
2414                 case RTE_ETHER_TYPE_VLAN:
2415                         bp->outer_tpid_bd =
2416                                 TX_BD_LONG_CFA_META_VLAN_TPID_TPID8100;
2417                                 break;
2418                 case 0x9100:
2419                         bp->outer_tpid_bd =
2420                                 TX_BD_LONG_CFA_META_VLAN_TPID_TPID9100;
2421                                 break;
2422                 case 0x9200:
2423                         bp->outer_tpid_bd =
2424                                 TX_BD_LONG_CFA_META_VLAN_TPID_TPID9200;
2425                                 break;
2426                 case 0x9300:
2427                         bp->outer_tpid_bd =
2428                                  TX_BD_LONG_CFA_META_VLAN_TPID_TPID9300;
2429                                 break;
2430                 default:
2431                         PMD_DRV_LOG(ERR, "Invalid TPID: %x\n", tpid);
2432                         return -EINVAL;
2433                 }
2434                 bp->outer_tpid_bd |= tpid;
2435                 PMD_DRV_LOG(INFO, "outer_tpid_bd = %x\n", bp->outer_tpid_bd);
2436         } else if (vlan_type == ETH_VLAN_TYPE_INNER) {
2437                 PMD_DRV_LOG(ERR,
2438                             "Can accelerate only outer vlan in QinQ\n");
2439                 return -EINVAL;
2440         }
2441
2442         return 0;
2443 }
2444
2445 static int
2446 bnxt_set_default_mac_addr_op(struct rte_eth_dev *dev,
2447                              struct rte_ether_addr *addr)
2448 {
2449         struct bnxt *bp = dev->data->dev_private;
2450         /* Default Filter is tied to VNIC 0 */
2451         struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp);
2452         int rc;
2453
2454         rc = is_bnxt_in_error(bp);
2455         if (rc)
2456                 return rc;
2457
2458         if (BNXT_VF(bp) && !BNXT_VF_IS_TRUSTED(bp))
2459                 return -EPERM;
2460
2461         if (rte_is_zero_ether_addr(addr))
2462                 return -EINVAL;
2463
2464         /* Filter settings will get applied when port is started */
2465         if (!dev->data->dev_started)
2466                 return 0;
2467
2468         /* Check if the requested MAC is already added */
2469         if (memcmp(addr, bp->mac_addr, RTE_ETHER_ADDR_LEN) == 0)
2470                 return 0;
2471
2472         /* Destroy filter and re-create it */
2473         bnxt_del_dflt_mac_filter(bp, vnic);
2474
2475         memcpy(bp->mac_addr, addr, RTE_ETHER_ADDR_LEN);
2476         if (dev->data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_VLAN_FILTER) {
2477                 /* This filter will allow only untagged packets */
2478                 rc = bnxt_add_vlan_filter(bp, 0);
2479         } else {
2480                 rc = bnxt_add_mac_filter(bp, vnic, addr, 0, 0);
2481         }
2482
2483         PMD_DRV_LOG(DEBUG, "Set MAC addr\n");
2484         return rc;
2485 }
2486
2487 static int
2488 bnxt_dev_set_mc_addr_list_op(struct rte_eth_dev *eth_dev,
2489                           struct rte_ether_addr *mc_addr_set,
2490                           uint32_t nb_mc_addr)
2491 {
2492         struct bnxt *bp = eth_dev->data->dev_private;
2493         char *mc_addr_list = (char *)mc_addr_set;
2494         struct bnxt_vnic_info *vnic;
2495         uint32_t off = 0, i = 0;
2496         int rc;
2497
2498         rc = is_bnxt_in_error(bp);
2499         if (rc)
2500                 return rc;
2501
2502         vnic = BNXT_GET_DEFAULT_VNIC(bp);
2503
2504         if (nb_mc_addr > BNXT_MAX_MC_ADDRS) {
2505                 vnic->flags |= BNXT_VNIC_INFO_ALLMULTI;
2506                 goto allmulti;
2507         }
2508
2509         /* TODO Check for Duplicate mcast addresses */
2510         vnic->flags &= ~BNXT_VNIC_INFO_ALLMULTI;
2511         for (i = 0; i < nb_mc_addr; i++) {
2512                 memcpy(vnic->mc_list + off, &mc_addr_list[i],
2513                         RTE_ETHER_ADDR_LEN);
2514                 off += RTE_ETHER_ADDR_LEN;
2515         }
2516
2517         vnic->mc_addr_cnt = i;
2518         if (vnic->mc_addr_cnt)
2519                 vnic->flags |= BNXT_VNIC_INFO_MCAST;
2520         else
2521                 vnic->flags &= ~BNXT_VNIC_INFO_MCAST;
2522
2523 allmulti:
2524         return bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
2525 }
2526
2527 static int
2528 bnxt_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size)
2529 {
2530         struct bnxt *bp = dev->data->dev_private;
2531         uint8_t fw_major = (bp->fw_ver >> 24) & 0xff;
2532         uint8_t fw_minor = (bp->fw_ver >> 16) & 0xff;
2533         uint8_t fw_updt = (bp->fw_ver >> 8) & 0xff;
2534         uint8_t fw_rsvd = bp->fw_ver & 0xff;
2535         int ret;
2536
2537         ret = snprintf(fw_version, fw_size, "%d.%d.%d.%d",
2538                         fw_major, fw_minor, fw_updt, fw_rsvd);
2539
2540         ret += 1; /* add the size of '\0' */
2541         if (fw_size < (uint32_t)ret)
2542                 return ret;
2543         else
2544                 return 0;
2545 }
2546
2547 static void
2548 bnxt_rxq_info_get_op(struct rte_eth_dev *dev, uint16_t queue_id,
2549         struct rte_eth_rxq_info *qinfo)
2550 {
2551         struct bnxt *bp = dev->data->dev_private;
2552         struct bnxt_rx_queue *rxq;
2553
2554         if (is_bnxt_in_error(bp))
2555                 return;
2556
2557         rxq = dev->data->rx_queues[queue_id];
2558
2559         qinfo->mp = rxq->mb_pool;
2560         qinfo->scattered_rx = dev->data->scattered_rx;
2561         qinfo->nb_desc = rxq->nb_rx_desc;
2562
2563         qinfo->conf.rx_free_thresh = rxq->rx_free_thresh;
2564         qinfo->conf.rx_drop_en = 0;
2565         qinfo->conf.rx_deferred_start = rxq->rx_deferred_start;
2566 }
2567
2568 static void
2569 bnxt_txq_info_get_op(struct rte_eth_dev *dev, uint16_t queue_id,
2570         struct rte_eth_txq_info *qinfo)
2571 {
2572         struct bnxt *bp = dev->data->dev_private;
2573         struct bnxt_tx_queue *txq;
2574
2575         if (is_bnxt_in_error(bp))
2576                 return;
2577
2578         txq = dev->data->tx_queues[queue_id];
2579
2580         qinfo->nb_desc = txq->nb_tx_desc;
2581
2582         qinfo->conf.tx_thresh.pthresh = txq->pthresh;
2583         qinfo->conf.tx_thresh.hthresh = txq->hthresh;
2584         qinfo->conf.tx_thresh.wthresh = txq->wthresh;
2585
2586         qinfo->conf.tx_free_thresh = txq->tx_free_thresh;
2587         qinfo->conf.tx_rs_thresh = 0;
2588         qinfo->conf.tx_deferred_start = txq->tx_deferred_start;
2589 }
2590
2591 int bnxt_mtu_set_op(struct rte_eth_dev *eth_dev, uint16_t new_mtu)
2592 {
2593         struct bnxt *bp = eth_dev->data->dev_private;
2594         uint32_t new_pkt_size;
2595         uint32_t rc = 0;
2596         uint32_t i;
2597
2598         rc = is_bnxt_in_error(bp);
2599         if (rc)
2600                 return rc;
2601
2602         /* Exit if receive queues are not configured yet */
2603         if (!eth_dev->data->nb_rx_queues)
2604                 return rc;
2605
2606         new_pkt_size = new_mtu + RTE_ETHER_HDR_LEN + RTE_ETHER_CRC_LEN +
2607                        VLAN_TAG_SIZE * BNXT_NUM_VLANS;
2608
2609 #ifdef RTE_ARCH_X86
2610         /*
2611          * If vector-mode tx/rx is active, disallow any MTU change that would
2612          * require scattered receive support.
2613          */
2614         if (eth_dev->data->dev_started &&
2615             (eth_dev->rx_pkt_burst == bnxt_recv_pkts_vec ||
2616              eth_dev->tx_pkt_burst == bnxt_xmit_pkts_vec) &&
2617             (new_pkt_size >
2618              eth_dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM)) {
2619                 PMD_DRV_LOG(ERR,
2620                             "MTU change would require scattered rx support. ");
2621                 PMD_DRV_LOG(ERR, "Stop port before changing MTU.\n");
2622                 return -EINVAL;
2623         }
2624 #endif
2625
2626         if (new_mtu > RTE_ETHER_MTU) {
2627                 bp->flags |= BNXT_FLAG_JUMBO;
2628                 bp->eth_dev->data->dev_conf.rxmode.offloads |=
2629                         DEV_RX_OFFLOAD_JUMBO_FRAME;
2630         } else {
2631                 bp->eth_dev->data->dev_conf.rxmode.offloads &=
2632                         ~DEV_RX_OFFLOAD_JUMBO_FRAME;
2633                 bp->flags &= ~BNXT_FLAG_JUMBO;
2634         }
2635
2636         /* Is there a change in mtu setting? */
2637         if (eth_dev->data->dev_conf.rxmode.max_rx_pkt_len == new_pkt_size)
2638                 return rc;
2639
2640         for (i = 0; i < bp->nr_vnics; i++) {
2641                 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
2642                 uint16_t size = 0;
2643
2644                 vnic->mru = BNXT_VNIC_MRU(new_mtu);
2645                 rc = bnxt_hwrm_vnic_cfg(bp, vnic);
2646                 if (rc)
2647                         break;
2648
2649                 size = rte_pktmbuf_data_room_size(bp->rx_queues[0]->mb_pool);
2650                 size -= RTE_PKTMBUF_HEADROOM;
2651
2652                 if (size < new_mtu) {
2653                         rc = bnxt_hwrm_vnic_plcmode_cfg(bp, vnic);
2654                         if (rc)
2655                                 return rc;
2656                 }
2657         }
2658
2659         if (!rc)
2660                 eth_dev->data->dev_conf.rxmode.max_rx_pkt_len = new_pkt_size;
2661
2662         PMD_DRV_LOG(INFO, "New MTU is %d\n", new_mtu);
2663
2664         return rc;
2665 }
2666
2667 static int
2668 bnxt_vlan_pvid_set_op(struct rte_eth_dev *dev, uint16_t pvid, int on)
2669 {
2670         struct bnxt *bp = dev->data->dev_private;
2671         uint16_t vlan = bp->vlan;
2672         int rc;
2673
2674         rc = is_bnxt_in_error(bp);
2675         if (rc)
2676                 return rc;
2677
2678         if (!BNXT_SINGLE_PF(bp) || BNXT_VF(bp)) {
2679                 PMD_DRV_LOG(ERR,
2680                         "PVID cannot be modified for this function\n");
2681                 return -ENOTSUP;
2682         }
2683         bp->vlan = on ? pvid : 0;
2684
2685         rc = bnxt_hwrm_set_default_vlan(bp, 0, 0);
2686         if (rc)
2687                 bp->vlan = vlan;
2688         return rc;
2689 }
2690
2691 static int
2692 bnxt_dev_led_on_op(struct rte_eth_dev *dev)
2693 {
2694         struct bnxt *bp = dev->data->dev_private;
2695         int rc;
2696
2697         rc = is_bnxt_in_error(bp);
2698         if (rc)
2699                 return rc;
2700
2701         return bnxt_hwrm_port_led_cfg(bp, true);
2702 }
2703
2704 static int
2705 bnxt_dev_led_off_op(struct rte_eth_dev *dev)
2706 {
2707         struct bnxt *bp = dev->data->dev_private;
2708         int rc;
2709
2710         rc = is_bnxt_in_error(bp);
2711         if (rc)
2712                 return rc;
2713
2714         return bnxt_hwrm_port_led_cfg(bp, false);
2715 }
2716
2717 static uint32_t
2718 bnxt_rx_queue_count_op(struct rte_eth_dev *dev, uint16_t rx_queue_id)
2719 {
2720         struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
2721         uint32_t desc = 0, raw_cons = 0, cons;
2722         struct bnxt_cp_ring_info *cpr;
2723         struct bnxt_rx_queue *rxq;
2724         struct rx_pkt_cmpl *rxcmp;
2725         int rc;
2726
2727         rc = is_bnxt_in_error(bp);
2728         if (rc)
2729                 return rc;
2730
2731         rxq = dev->data->rx_queues[rx_queue_id];
2732         cpr = rxq->cp_ring;
2733         raw_cons = cpr->cp_raw_cons;
2734
2735         while (1) {
2736                 cons = RING_CMP(cpr->cp_ring_struct, raw_cons);
2737                 rte_prefetch0(&cpr->cp_desc_ring[cons]);
2738                 rxcmp = (struct rx_pkt_cmpl *)&cpr->cp_desc_ring[cons];
2739
2740                 if (!CMP_VALID(rxcmp, raw_cons, cpr->cp_ring_struct)) {
2741                         break;
2742                 } else {
2743                         raw_cons++;
2744                         desc++;
2745                 }
2746         }
2747
2748         return desc;
2749 }
2750
2751 static int
2752 bnxt_rx_descriptor_status_op(void *rx_queue, uint16_t offset)
2753 {
2754         struct bnxt_rx_queue *rxq = (struct bnxt_rx_queue *)rx_queue;
2755         struct bnxt_rx_ring_info *rxr;
2756         struct bnxt_cp_ring_info *cpr;
2757         struct bnxt_sw_rx_bd *rx_buf;
2758         struct rx_pkt_cmpl *rxcmp;
2759         uint32_t cons, cp_cons;
2760         int rc;
2761
2762         if (!rxq)
2763                 return -EINVAL;
2764
2765         rc = is_bnxt_in_error(rxq->bp);
2766         if (rc)
2767                 return rc;
2768
2769         cpr = rxq->cp_ring;
2770         rxr = rxq->rx_ring;
2771
2772         if (offset >= rxq->nb_rx_desc)
2773                 return -EINVAL;
2774
2775         cons = RING_CMP(cpr->cp_ring_struct, offset);
2776         cp_cons = cpr->cp_raw_cons;
2777         rxcmp = (struct rx_pkt_cmpl *)&cpr->cp_desc_ring[cons];
2778
2779         if (cons > cp_cons) {
2780                 if (CMPL_VALID(rxcmp, cpr->valid))
2781                         return RTE_ETH_RX_DESC_DONE;
2782         } else {
2783                 if (CMPL_VALID(rxcmp, !cpr->valid))
2784                         return RTE_ETH_RX_DESC_DONE;
2785         }
2786         rx_buf = &rxr->rx_buf_ring[cons];
2787         if (rx_buf->mbuf == NULL)
2788                 return RTE_ETH_RX_DESC_UNAVAIL;
2789
2790
2791         return RTE_ETH_RX_DESC_AVAIL;
2792 }
2793
2794 static int
2795 bnxt_tx_descriptor_status_op(void *tx_queue, uint16_t offset)
2796 {
2797         struct bnxt_tx_queue *txq = (struct bnxt_tx_queue *)tx_queue;
2798         struct bnxt_tx_ring_info *txr;
2799         struct bnxt_cp_ring_info *cpr;
2800         struct bnxt_sw_tx_bd *tx_buf;
2801         struct tx_pkt_cmpl *txcmp;
2802         uint32_t cons, cp_cons;
2803         int rc;
2804
2805         if (!txq)
2806                 return -EINVAL;
2807
2808         rc = is_bnxt_in_error(txq->bp);
2809         if (rc)
2810                 return rc;
2811
2812         cpr = txq->cp_ring;
2813         txr = txq->tx_ring;
2814
2815         if (offset >= txq->nb_tx_desc)
2816                 return -EINVAL;
2817
2818         cons = RING_CMP(cpr->cp_ring_struct, offset);
2819         txcmp = (struct tx_pkt_cmpl *)&cpr->cp_desc_ring[cons];
2820         cp_cons = cpr->cp_raw_cons;
2821
2822         if (cons > cp_cons) {
2823                 if (CMPL_VALID(txcmp, cpr->valid))
2824                         return RTE_ETH_TX_DESC_UNAVAIL;
2825         } else {
2826                 if (CMPL_VALID(txcmp, !cpr->valid))
2827                         return RTE_ETH_TX_DESC_UNAVAIL;
2828         }
2829         tx_buf = &txr->tx_buf_ring[cons];
2830         if (tx_buf->mbuf == NULL)
2831                 return RTE_ETH_TX_DESC_DONE;
2832
2833         return RTE_ETH_TX_DESC_FULL;
2834 }
2835
2836 static struct bnxt_filter_info *
2837 bnxt_match_and_validate_ether_filter(struct bnxt *bp,
2838                                 struct rte_eth_ethertype_filter *efilter,
2839                                 struct bnxt_vnic_info *vnic0,
2840                                 struct bnxt_vnic_info *vnic,
2841                                 int *ret)
2842 {
2843         struct bnxt_filter_info *mfilter = NULL;
2844         int match = 0;
2845         *ret = 0;
2846
2847         if (efilter->ether_type == RTE_ETHER_TYPE_IPV4 ||
2848                 efilter->ether_type == RTE_ETHER_TYPE_IPV6) {
2849                 PMD_DRV_LOG(ERR, "invalid ether_type(0x%04x) in"
2850                         " ethertype filter.", efilter->ether_type);
2851                 *ret = -EINVAL;
2852                 goto exit;
2853         }
2854         if (efilter->queue >= bp->rx_nr_rings) {
2855                 PMD_DRV_LOG(ERR, "Invalid queue %d\n", efilter->queue);
2856                 *ret = -EINVAL;
2857                 goto exit;
2858         }
2859
2860         vnic0 = BNXT_GET_DEFAULT_VNIC(bp);
2861         vnic = &bp->vnic_info[efilter->queue];
2862         if (vnic == NULL) {
2863                 PMD_DRV_LOG(ERR, "Invalid queue %d\n", efilter->queue);
2864                 *ret = -EINVAL;
2865                 goto exit;
2866         }
2867
2868         if (efilter->flags & RTE_ETHTYPE_FLAGS_DROP) {
2869                 STAILQ_FOREACH(mfilter, &vnic0->filter, next) {
2870                         if ((!memcmp(efilter->mac_addr.addr_bytes,
2871                                      mfilter->l2_addr, RTE_ETHER_ADDR_LEN) &&
2872                              mfilter->flags ==
2873                              HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_DROP &&
2874                              mfilter->ethertype == efilter->ether_type)) {
2875                                 match = 1;
2876                                 break;
2877                         }
2878                 }
2879         } else {
2880                 STAILQ_FOREACH(mfilter, &vnic->filter, next)
2881                         if ((!memcmp(efilter->mac_addr.addr_bytes,
2882                                      mfilter->l2_addr, RTE_ETHER_ADDR_LEN) &&
2883                              mfilter->ethertype == efilter->ether_type &&
2884                              mfilter->flags ==
2885                              HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_PATH_RX)) {
2886                                 match = 1;
2887                                 break;
2888                         }
2889         }
2890
2891         if (match)
2892                 *ret = -EEXIST;
2893
2894 exit:
2895         return mfilter;
2896 }
2897
2898 static int
2899 bnxt_ethertype_filter(struct rte_eth_dev *dev,
2900                         enum rte_filter_op filter_op,
2901                         void *arg)
2902 {
2903         struct bnxt *bp = dev->data->dev_private;
2904         struct rte_eth_ethertype_filter *efilter =
2905                         (struct rte_eth_ethertype_filter *)arg;
2906         struct bnxt_filter_info *bfilter, *filter1;
2907         struct bnxt_vnic_info *vnic, *vnic0;
2908         int ret;
2909
2910         if (filter_op == RTE_ETH_FILTER_NOP)
2911                 return 0;
2912
2913         if (arg == NULL) {
2914                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
2915                             filter_op);
2916                 return -EINVAL;
2917         }
2918
2919         vnic0 = BNXT_GET_DEFAULT_VNIC(bp);
2920         vnic = &bp->vnic_info[efilter->queue];
2921
2922         switch (filter_op) {
2923         case RTE_ETH_FILTER_ADD:
2924                 bnxt_match_and_validate_ether_filter(bp, efilter,
2925                                                         vnic0, vnic, &ret);
2926                 if (ret < 0)
2927                         return ret;
2928
2929                 bfilter = bnxt_get_unused_filter(bp);
2930                 if (bfilter == NULL) {
2931                         PMD_DRV_LOG(ERR,
2932                                 "Not enough resources for a new filter.\n");
2933                         return -ENOMEM;
2934                 }
2935                 bfilter->filter_type = HWRM_CFA_NTUPLE_FILTER;
2936                 memcpy(bfilter->l2_addr, efilter->mac_addr.addr_bytes,
2937                        RTE_ETHER_ADDR_LEN);
2938                 memcpy(bfilter->dst_macaddr, efilter->mac_addr.addr_bytes,
2939                        RTE_ETHER_ADDR_LEN);
2940                 bfilter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_MACADDR;
2941                 bfilter->ethertype = efilter->ether_type;
2942                 bfilter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2943
2944                 filter1 = bnxt_get_l2_filter(bp, bfilter, vnic0);
2945                 if (filter1 == NULL) {
2946                         ret = -EINVAL;
2947                         goto cleanup;
2948                 }
2949                 bfilter->enables |=
2950                         HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID;
2951                 bfilter->fw_l2_filter_id = filter1->fw_l2_filter_id;
2952
2953                 bfilter->dst_id = vnic->fw_vnic_id;
2954
2955                 if (efilter->flags & RTE_ETHTYPE_FLAGS_DROP) {
2956                         bfilter->flags =
2957                                 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_DROP;
2958                 }
2959
2960                 ret = bnxt_hwrm_set_ntuple_filter(bp, bfilter->dst_id, bfilter);
2961                 if (ret)
2962                         goto cleanup;
2963                 STAILQ_INSERT_TAIL(&vnic->filter, bfilter, next);
2964                 break;
2965         case RTE_ETH_FILTER_DELETE:
2966                 filter1 = bnxt_match_and_validate_ether_filter(bp, efilter,
2967                                                         vnic0, vnic, &ret);
2968                 if (ret == -EEXIST) {
2969                         ret = bnxt_hwrm_clear_ntuple_filter(bp, filter1);
2970
2971                         STAILQ_REMOVE(&vnic->filter, filter1, bnxt_filter_info,
2972                                       next);
2973                         bnxt_free_filter(bp, filter1);
2974                 } else if (ret == 0) {
2975                         PMD_DRV_LOG(ERR, "No matching filter found\n");
2976                 }
2977                 break;
2978         default:
2979                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
2980                 ret = -EINVAL;
2981                 goto error;
2982         }
2983         return ret;
2984 cleanup:
2985         bnxt_free_filter(bp, bfilter);
2986 error:
2987         return ret;
2988 }
2989
2990 static inline int
2991 parse_ntuple_filter(struct bnxt *bp,
2992                     struct rte_eth_ntuple_filter *nfilter,
2993                     struct bnxt_filter_info *bfilter)
2994 {
2995         uint32_t en = 0;
2996
2997         if (nfilter->queue >= bp->rx_nr_rings) {
2998                 PMD_DRV_LOG(ERR, "Invalid queue %d\n", nfilter->queue);
2999                 return -EINVAL;
3000         }
3001
3002         switch (nfilter->dst_port_mask) {
3003         case UINT16_MAX:
3004                 bfilter->dst_port_mask = -1;
3005                 bfilter->dst_port = nfilter->dst_port;
3006                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT |
3007                         NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
3008                 break;
3009         default:
3010                 PMD_DRV_LOG(ERR, "invalid dst_port mask.");
3011                 return -EINVAL;
3012         }
3013
3014         bfilter->ip_addr_type = NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4;
3015         en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
3016
3017         switch (nfilter->proto_mask) {
3018         case UINT8_MAX:
3019                 if (nfilter->proto == 17) /* IPPROTO_UDP */
3020                         bfilter->ip_protocol = 17;
3021                 else if (nfilter->proto == 6) /* IPPROTO_TCP */
3022                         bfilter->ip_protocol = 6;
3023                 else
3024                         return -EINVAL;
3025                 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
3026                 break;
3027         default:
3028                 PMD_DRV_LOG(ERR, "invalid protocol mask.");
3029                 return -EINVAL;
3030         }
3031
3032         switch (nfilter->dst_ip_mask) {
3033         case UINT32_MAX:
3034                 bfilter->dst_ipaddr_mask[0] = -1;
3035                 bfilter->dst_ipaddr[0] = nfilter->dst_ip;
3036                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR |
3037                         NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
3038                 break;
3039         default:
3040                 PMD_DRV_LOG(ERR, "invalid dst_ip mask.");
3041                 return -EINVAL;
3042         }
3043
3044         switch (nfilter->src_ip_mask) {
3045         case UINT32_MAX:
3046                 bfilter->src_ipaddr_mask[0] = -1;
3047                 bfilter->src_ipaddr[0] = nfilter->src_ip;
3048                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR |
3049                         NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
3050                 break;
3051         default:
3052                 PMD_DRV_LOG(ERR, "invalid src_ip mask.");
3053                 return -EINVAL;
3054         }
3055
3056         switch (nfilter->src_port_mask) {
3057         case UINT16_MAX:
3058                 bfilter->src_port_mask = -1;
3059                 bfilter->src_port = nfilter->src_port;
3060                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT |
3061                         NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
3062                 break;
3063         default:
3064                 PMD_DRV_LOG(ERR, "invalid src_port mask.");
3065                 return -EINVAL;
3066         }
3067
3068         bfilter->enables = en;
3069         return 0;
3070 }
3071
3072 static struct bnxt_filter_info*
3073 bnxt_match_ntuple_filter(struct bnxt *bp,
3074                          struct bnxt_filter_info *bfilter,
3075                          struct bnxt_vnic_info **mvnic)
3076 {
3077         struct bnxt_filter_info *mfilter = NULL;
3078         int i;
3079
3080         for (i = bp->nr_vnics - 1; i >= 0; i--) {
3081                 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
3082                 STAILQ_FOREACH(mfilter, &vnic->filter, next) {
3083                         if (bfilter->src_ipaddr[0] == mfilter->src_ipaddr[0] &&
3084                             bfilter->src_ipaddr_mask[0] ==
3085                             mfilter->src_ipaddr_mask[0] &&
3086                             bfilter->src_port == mfilter->src_port &&
3087                             bfilter->src_port_mask == mfilter->src_port_mask &&
3088                             bfilter->dst_ipaddr[0] == mfilter->dst_ipaddr[0] &&
3089                             bfilter->dst_ipaddr_mask[0] ==
3090                             mfilter->dst_ipaddr_mask[0] &&
3091                             bfilter->dst_port == mfilter->dst_port &&
3092                             bfilter->dst_port_mask == mfilter->dst_port_mask &&
3093                             bfilter->flags == mfilter->flags &&
3094                             bfilter->enables == mfilter->enables) {
3095                                 if (mvnic)
3096                                         *mvnic = vnic;
3097                                 return mfilter;
3098                         }
3099                 }
3100         }
3101         return NULL;
3102 }
3103
3104 static int
3105 bnxt_cfg_ntuple_filter(struct bnxt *bp,
3106                        struct rte_eth_ntuple_filter *nfilter,
3107                        enum rte_filter_op filter_op)
3108 {
3109         struct bnxt_filter_info *bfilter, *mfilter, *filter1;
3110         struct bnxt_vnic_info *vnic, *vnic0, *mvnic;
3111         int ret;
3112
3113         if (nfilter->flags != RTE_5TUPLE_FLAGS) {
3114                 PMD_DRV_LOG(ERR, "only 5tuple is supported.");
3115                 return -EINVAL;
3116         }
3117
3118         if (nfilter->flags & RTE_NTUPLE_FLAGS_TCP_FLAG) {
3119                 PMD_DRV_LOG(ERR, "Ntuple filter: TCP flags not supported\n");
3120                 return -EINVAL;
3121         }
3122
3123         bfilter = bnxt_get_unused_filter(bp);
3124         if (bfilter == NULL) {
3125                 PMD_DRV_LOG(ERR,
3126                         "Not enough resources for a new filter.\n");
3127                 return -ENOMEM;
3128         }
3129         ret = parse_ntuple_filter(bp, nfilter, bfilter);
3130         if (ret < 0)
3131                 goto free_filter;
3132
3133         vnic = &bp->vnic_info[nfilter->queue];
3134         vnic0 = BNXT_GET_DEFAULT_VNIC(bp);
3135         filter1 = STAILQ_FIRST(&vnic0->filter);
3136         if (filter1 == NULL) {
3137                 ret = -EINVAL;
3138                 goto free_filter;
3139         }
3140
3141         bfilter->dst_id = vnic->fw_vnic_id;
3142         bfilter->fw_l2_filter_id = filter1->fw_l2_filter_id;
3143         bfilter->enables |=
3144                 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID;
3145         bfilter->ethertype = 0x800;
3146         bfilter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
3147
3148         mfilter = bnxt_match_ntuple_filter(bp, bfilter, &mvnic);
3149
3150         if (mfilter != NULL && filter_op == RTE_ETH_FILTER_ADD &&
3151             bfilter->dst_id == mfilter->dst_id) {
3152                 PMD_DRV_LOG(ERR, "filter exists.\n");
3153                 ret = -EEXIST;
3154                 goto free_filter;
3155         } else if (mfilter != NULL && filter_op == RTE_ETH_FILTER_ADD &&
3156                    bfilter->dst_id != mfilter->dst_id) {
3157                 mfilter->dst_id = vnic->fw_vnic_id;
3158                 ret = bnxt_hwrm_set_ntuple_filter(bp, mfilter->dst_id, mfilter);
3159                 STAILQ_REMOVE(&mvnic->filter, mfilter, bnxt_filter_info, next);
3160                 STAILQ_INSERT_TAIL(&vnic->filter, mfilter, next);
3161                 PMD_DRV_LOG(ERR, "filter with matching pattern exists.\n");
3162                 PMD_DRV_LOG(ERR, " Updated it to the new destination queue\n");
3163                 goto free_filter;
3164         }
3165         if (mfilter == NULL && filter_op == RTE_ETH_FILTER_DELETE) {
3166                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
3167                 ret = -ENOENT;
3168                 goto free_filter;
3169         }
3170
3171         if (filter_op == RTE_ETH_FILTER_ADD) {
3172                 bfilter->filter_type = HWRM_CFA_NTUPLE_FILTER;
3173                 ret = bnxt_hwrm_set_ntuple_filter(bp, bfilter->dst_id, bfilter);
3174                 if (ret)
3175                         goto free_filter;
3176                 STAILQ_INSERT_TAIL(&vnic->filter, bfilter, next);
3177         } else {
3178                 if (mfilter == NULL) {
3179                         /* This should not happen. But for Coverity! */
3180                         ret = -ENOENT;
3181                         goto free_filter;
3182                 }
3183                 ret = bnxt_hwrm_clear_ntuple_filter(bp, mfilter);
3184
3185                 STAILQ_REMOVE(&vnic->filter, mfilter, bnxt_filter_info, next);
3186                 bnxt_free_filter(bp, mfilter);
3187                 bnxt_free_filter(bp, bfilter);
3188         }
3189
3190         return 0;
3191 free_filter:
3192         bnxt_free_filter(bp, bfilter);
3193         return ret;
3194 }
3195
3196 static int
3197 bnxt_ntuple_filter(struct rte_eth_dev *dev,
3198                         enum rte_filter_op filter_op,
3199                         void *arg)
3200 {
3201         struct bnxt *bp = dev->data->dev_private;
3202         int ret;
3203
3204         if (filter_op == RTE_ETH_FILTER_NOP)
3205                 return 0;
3206
3207         if (arg == NULL) {
3208                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
3209                             filter_op);
3210                 return -EINVAL;
3211         }
3212
3213         switch (filter_op) {
3214         case RTE_ETH_FILTER_ADD:
3215                 ret = bnxt_cfg_ntuple_filter(bp,
3216                         (struct rte_eth_ntuple_filter *)arg,
3217                         filter_op);
3218                 break;
3219         case RTE_ETH_FILTER_DELETE:
3220                 ret = bnxt_cfg_ntuple_filter(bp,
3221                         (struct rte_eth_ntuple_filter *)arg,
3222                         filter_op);
3223                 break;
3224         default:
3225                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
3226                 ret = -EINVAL;
3227                 break;
3228         }
3229         return ret;
3230 }
3231
3232 static int
3233 bnxt_parse_fdir_filter(struct bnxt *bp,
3234                        struct rte_eth_fdir_filter *fdir,
3235                        struct bnxt_filter_info *filter)
3236 {
3237         enum rte_fdir_mode fdir_mode =
3238                 bp->eth_dev->data->dev_conf.fdir_conf.mode;
3239         struct bnxt_vnic_info *vnic0, *vnic;
3240         struct bnxt_filter_info *filter1;
3241         uint32_t en = 0;
3242         int i;
3243
3244         if (fdir_mode == RTE_FDIR_MODE_PERFECT_TUNNEL)
3245                 return -EINVAL;
3246
3247         filter->l2_ovlan = fdir->input.flow_ext.vlan_tci;
3248         en |= EM_FLOW_ALLOC_INPUT_EN_OVLAN_VID;
3249
3250         switch (fdir->input.flow_type) {
3251         case RTE_ETH_FLOW_IPV4:
3252         case RTE_ETH_FLOW_NONFRAG_IPV4_OTHER:
3253                 /* FALLTHROUGH */
3254                 filter->src_ipaddr[0] = fdir->input.flow.ip4_flow.src_ip;
3255                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
3256                 filter->dst_ipaddr[0] = fdir->input.flow.ip4_flow.dst_ip;
3257                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
3258                 filter->ip_protocol = fdir->input.flow.ip4_flow.proto;
3259                 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
3260                 filter->ip_addr_type =
3261                         NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4;
3262                 filter->src_ipaddr_mask[0] = 0xffffffff;
3263                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
3264                 filter->dst_ipaddr_mask[0] = 0xffffffff;
3265                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
3266                 filter->ethertype = 0x800;
3267                 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
3268                 break;
3269         case RTE_ETH_FLOW_NONFRAG_IPV4_TCP:
3270                 filter->src_port = fdir->input.flow.tcp4_flow.src_port;
3271                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT;
3272                 filter->dst_port = fdir->input.flow.tcp4_flow.dst_port;
3273                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT;
3274                 filter->dst_port_mask = 0xffff;
3275                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
3276                 filter->src_port_mask = 0xffff;
3277                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
3278                 filter->src_ipaddr[0] = fdir->input.flow.tcp4_flow.ip.src_ip;
3279                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
3280                 filter->dst_ipaddr[0] = fdir->input.flow.tcp4_flow.ip.dst_ip;
3281                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
3282                 filter->ip_protocol = 6;
3283                 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
3284                 filter->ip_addr_type =
3285                         NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4;
3286                 filter->src_ipaddr_mask[0] = 0xffffffff;
3287                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
3288                 filter->dst_ipaddr_mask[0] = 0xffffffff;
3289                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
3290                 filter->ethertype = 0x800;
3291                 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
3292                 break;
3293         case RTE_ETH_FLOW_NONFRAG_IPV4_UDP:
3294                 filter->src_port = fdir->input.flow.udp4_flow.src_port;
3295                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT;
3296                 filter->dst_port = fdir->input.flow.udp4_flow.dst_port;
3297                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT;
3298                 filter->dst_port_mask = 0xffff;
3299                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
3300                 filter->src_port_mask = 0xffff;
3301                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
3302                 filter->src_ipaddr[0] = fdir->input.flow.udp4_flow.ip.src_ip;
3303                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
3304                 filter->dst_ipaddr[0] = fdir->input.flow.udp4_flow.ip.dst_ip;
3305                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
3306                 filter->ip_protocol = 17;
3307                 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
3308                 filter->ip_addr_type =
3309                         NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4;
3310                 filter->src_ipaddr_mask[0] = 0xffffffff;
3311                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
3312                 filter->dst_ipaddr_mask[0] = 0xffffffff;
3313                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
3314                 filter->ethertype = 0x800;
3315                 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
3316                 break;
3317         case RTE_ETH_FLOW_IPV6:
3318         case RTE_ETH_FLOW_NONFRAG_IPV6_OTHER:
3319                 /* FALLTHROUGH */
3320                 filter->ip_addr_type =
3321                         NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV6;
3322                 filter->ip_protocol = fdir->input.flow.ipv6_flow.proto;
3323                 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
3324                 rte_memcpy(filter->src_ipaddr,
3325                            fdir->input.flow.ipv6_flow.src_ip, 16);
3326                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
3327                 rte_memcpy(filter->dst_ipaddr,
3328                            fdir->input.flow.ipv6_flow.dst_ip, 16);
3329                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
3330                 memset(filter->dst_ipaddr_mask, 0xff, 16);
3331                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
3332                 memset(filter->src_ipaddr_mask, 0xff, 16);
3333                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
3334                 filter->ethertype = 0x86dd;
3335                 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
3336                 break;
3337         case RTE_ETH_FLOW_NONFRAG_IPV6_TCP:
3338                 filter->src_port = fdir->input.flow.tcp6_flow.src_port;
3339                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT;
3340                 filter->dst_port = fdir->input.flow.tcp6_flow.dst_port;
3341                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT;
3342                 filter->dst_port_mask = 0xffff;
3343                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
3344                 filter->src_port_mask = 0xffff;
3345                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
3346                 filter->ip_addr_type =
3347                         NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV6;
3348                 filter->ip_protocol = fdir->input.flow.tcp6_flow.ip.proto;
3349                 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
3350                 rte_memcpy(filter->src_ipaddr,
3351                            fdir->input.flow.tcp6_flow.ip.src_ip, 16);
3352                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
3353                 rte_memcpy(filter->dst_ipaddr,
3354                            fdir->input.flow.tcp6_flow.ip.dst_ip, 16);
3355                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
3356                 memset(filter->dst_ipaddr_mask, 0xff, 16);
3357                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
3358                 memset(filter->src_ipaddr_mask, 0xff, 16);
3359                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
3360                 filter->ethertype = 0x86dd;
3361                 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
3362                 break;
3363         case RTE_ETH_FLOW_NONFRAG_IPV6_UDP:
3364                 filter->src_port = fdir->input.flow.udp6_flow.src_port;
3365                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT;
3366                 filter->dst_port = fdir->input.flow.udp6_flow.dst_port;
3367                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT;
3368                 filter->dst_port_mask = 0xffff;
3369                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
3370                 filter->src_port_mask = 0xffff;
3371                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
3372                 filter->ip_addr_type =
3373                         NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV6;
3374                 filter->ip_protocol = fdir->input.flow.udp6_flow.ip.proto;
3375                 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
3376                 rte_memcpy(filter->src_ipaddr,
3377                            fdir->input.flow.udp6_flow.ip.src_ip, 16);
3378                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
3379                 rte_memcpy(filter->dst_ipaddr,
3380                            fdir->input.flow.udp6_flow.ip.dst_ip, 16);
3381                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
3382                 memset(filter->dst_ipaddr_mask, 0xff, 16);
3383                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
3384                 memset(filter->src_ipaddr_mask, 0xff, 16);
3385                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
3386                 filter->ethertype = 0x86dd;
3387                 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
3388                 break;
3389         case RTE_ETH_FLOW_L2_PAYLOAD:
3390                 filter->ethertype = fdir->input.flow.l2_flow.ether_type;
3391                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
3392                 break;
3393         case RTE_ETH_FLOW_VXLAN:
3394                 if (fdir->action.behavior == RTE_ETH_FDIR_REJECT)
3395                         return -EINVAL;
3396                 filter->vni = fdir->input.flow.tunnel_flow.tunnel_id;
3397                 filter->tunnel_type =
3398                         CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN;
3399                 en |= HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_TUNNEL_TYPE;
3400                 break;
3401         case RTE_ETH_FLOW_NVGRE:
3402                 if (fdir->action.behavior == RTE_ETH_FDIR_REJECT)
3403                         return -EINVAL;
3404                 filter->vni = fdir->input.flow.tunnel_flow.tunnel_id;
3405                 filter->tunnel_type =
3406                         CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_NVGRE;
3407                 en |= HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_TUNNEL_TYPE;
3408                 break;
3409         case RTE_ETH_FLOW_UNKNOWN:
3410         case RTE_ETH_FLOW_RAW:
3411         case RTE_ETH_FLOW_FRAG_IPV4:
3412         case RTE_ETH_FLOW_NONFRAG_IPV4_SCTP:
3413         case RTE_ETH_FLOW_FRAG_IPV6:
3414         case RTE_ETH_FLOW_NONFRAG_IPV6_SCTP:
3415         case RTE_ETH_FLOW_IPV6_EX:
3416         case RTE_ETH_FLOW_IPV6_TCP_EX:
3417         case RTE_ETH_FLOW_IPV6_UDP_EX:
3418         case RTE_ETH_FLOW_GENEVE:
3419                 /* FALLTHROUGH */
3420         default:
3421                 return -EINVAL;
3422         }
3423
3424         vnic0 = BNXT_GET_DEFAULT_VNIC(bp);
3425         vnic = &bp->vnic_info[fdir->action.rx_queue];
3426         if (vnic == NULL) {
3427                 PMD_DRV_LOG(ERR, "Invalid queue %d\n", fdir->action.rx_queue);
3428                 return -EINVAL;
3429         }
3430
3431         if (fdir_mode == RTE_FDIR_MODE_PERFECT_MAC_VLAN) {
3432                 rte_memcpy(filter->dst_macaddr,
3433                         fdir->input.flow.mac_vlan_flow.mac_addr.addr_bytes, 6);
3434                         en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_MACADDR;
3435         }
3436
3437         if (fdir->action.behavior == RTE_ETH_FDIR_REJECT) {
3438                 filter->flags = HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_DROP;
3439                 filter1 = STAILQ_FIRST(&vnic0->filter);
3440                 //filter1 = bnxt_get_l2_filter(bp, filter, vnic0);
3441         } else {
3442                 filter->dst_id = vnic->fw_vnic_id;
3443                 for (i = 0; i < RTE_ETHER_ADDR_LEN; i++)
3444                         if (filter->dst_macaddr[i] == 0x00)
3445                                 filter1 = STAILQ_FIRST(&vnic0->filter);
3446                         else
3447                                 filter1 = bnxt_get_l2_filter(bp, filter, vnic);
3448         }
3449
3450         if (filter1 == NULL)
3451                 return -EINVAL;
3452
3453         en |= HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID;
3454         filter->fw_l2_filter_id = filter1->fw_l2_filter_id;
3455
3456         filter->enables = en;
3457
3458         return 0;
3459 }
3460
3461 static struct bnxt_filter_info *
3462 bnxt_match_fdir(struct bnxt *bp, struct bnxt_filter_info *nf,
3463                 struct bnxt_vnic_info **mvnic)
3464 {
3465         struct bnxt_filter_info *mf = NULL;
3466         int i;
3467
3468         for (i = bp->nr_vnics - 1; i >= 0; i--) {
3469                 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
3470
3471                 STAILQ_FOREACH(mf, &vnic->filter, next) {
3472                         if (mf->filter_type == nf->filter_type &&
3473                             mf->flags == nf->flags &&
3474                             mf->src_port == nf->src_port &&
3475                             mf->src_port_mask == nf->src_port_mask &&
3476                             mf->dst_port == nf->dst_port &&
3477                             mf->dst_port_mask == nf->dst_port_mask &&
3478                             mf->ip_protocol == nf->ip_protocol &&
3479                             mf->ip_addr_type == nf->ip_addr_type &&
3480                             mf->ethertype == nf->ethertype &&
3481                             mf->vni == nf->vni &&
3482                             mf->tunnel_type == nf->tunnel_type &&
3483                             mf->l2_ovlan == nf->l2_ovlan &&
3484                             mf->l2_ovlan_mask == nf->l2_ovlan_mask &&
3485                             mf->l2_ivlan == nf->l2_ivlan &&
3486                             mf->l2_ivlan_mask == nf->l2_ivlan_mask &&
3487                             !memcmp(mf->l2_addr, nf->l2_addr,
3488                                     RTE_ETHER_ADDR_LEN) &&
3489                             !memcmp(mf->l2_addr_mask, nf->l2_addr_mask,
3490                                     RTE_ETHER_ADDR_LEN) &&
3491                             !memcmp(mf->src_macaddr, nf->src_macaddr,
3492                                     RTE_ETHER_ADDR_LEN) &&
3493                             !memcmp(mf->dst_macaddr, nf->dst_macaddr,
3494                                     RTE_ETHER_ADDR_LEN) &&
3495                             !memcmp(mf->src_ipaddr, nf->src_ipaddr,
3496                                     sizeof(nf->src_ipaddr)) &&
3497                             !memcmp(mf->src_ipaddr_mask, nf->src_ipaddr_mask,
3498                                     sizeof(nf->src_ipaddr_mask)) &&
3499                             !memcmp(mf->dst_ipaddr, nf->dst_ipaddr,
3500                                     sizeof(nf->dst_ipaddr)) &&
3501                             !memcmp(mf->dst_ipaddr_mask, nf->dst_ipaddr_mask,
3502                                     sizeof(nf->dst_ipaddr_mask))) {
3503                                 if (mvnic)
3504                                         *mvnic = vnic;
3505                                 return mf;
3506                         }
3507                 }
3508         }
3509         return NULL;
3510 }
3511
3512 static int
3513 bnxt_fdir_filter(struct rte_eth_dev *dev,
3514                  enum rte_filter_op filter_op,
3515                  void *arg)
3516 {
3517         struct bnxt *bp = dev->data->dev_private;
3518         struct rte_eth_fdir_filter *fdir  = (struct rte_eth_fdir_filter *)arg;
3519         struct bnxt_filter_info *filter, *match;
3520         struct bnxt_vnic_info *vnic, *mvnic;
3521         int ret = 0, i;
3522
3523         if (filter_op == RTE_ETH_FILTER_NOP)
3524                 return 0;
3525
3526         if (arg == NULL && filter_op != RTE_ETH_FILTER_FLUSH)
3527                 return -EINVAL;
3528
3529         switch (filter_op) {
3530         case RTE_ETH_FILTER_ADD:
3531         case RTE_ETH_FILTER_DELETE:
3532                 /* FALLTHROUGH */
3533                 filter = bnxt_get_unused_filter(bp);
3534                 if (filter == NULL) {
3535                         PMD_DRV_LOG(ERR,
3536                                 "Not enough resources for a new flow.\n");
3537                         return -ENOMEM;
3538                 }
3539
3540                 ret = bnxt_parse_fdir_filter(bp, fdir, filter);
3541                 if (ret != 0)
3542                         goto free_filter;
3543                 filter->filter_type = HWRM_CFA_NTUPLE_FILTER;
3544
3545                 if (fdir->action.behavior == RTE_ETH_FDIR_REJECT)
3546                         vnic = &bp->vnic_info[0];
3547                 else
3548                         vnic = &bp->vnic_info[fdir->action.rx_queue];
3549
3550                 match = bnxt_match_fdir(bp, filter, &mvnic);
3551                 if (match != NULL && filter_op == RTE_ETH_FILTER_ADD) {
3552                         if (match->dst_id == vnic->fw_vnic_id) {
3553                                 PMD_DRV_LOG(ERR, "Flow already exists.\n");
3554                                 ret = -EEXIST;
3555                                 goto free_filter;
3556                         } else {
3557                                 match->dst_id = vnic->fw_vnic_id;
3558                                 ret = bnxt_hwrm_set_ntuple_filter(bp,
3559                                                                   match->dst_id,
3560                                                                   match);
3561                                 STAILQ_REMOVE(&mvnic->filter, match,
3562                                               bnxt_filter_info, next);
3563                                 STAILQ_INSERT_TAIL(&vnic->filter, match, next);
3564                                 PMD_DRV_LOG(ERR,
3565                                         "Filter with matching pattern exist\n");
3566                                 PMD_DRV_LOG(ERR,
3567                                         "Updated it to new destination q\n");
3568                                 goto free_filter;
3569                         }
3570                 }
3571                 if (match == NULL && filter_op == RTE_ETH_FILTER_DELETE) {
3572                         PMD_DRV_LOG(ERR, "Flow does not exist.\n");
3573                         ret = -ENOENT;
3574                         goto free_filter;
3575                 }
3576
3577                 if (filter_op == RTE_ETH_FILTER_ADD) {
3578                         ret = bnxt_hwrm_set_ntuple_filter(bp,
3579                                                           filter->dst_id,
3580                                                           filter);
3581                         if (ret)
3582                                 goto free_filter;
3583                         STAILQ_INSERT_TAIL(&vnic->filter, filter, next);
3584                 } else {
3585                         ret = bnxt_hwrm_clear_ntuple_filter(bp, match);
3586                         STAILQ_REMOVE(&vnic->filter, match,
3587                                       bnxt_filter_info, next);
3588                         bnxt_free_filter(bp, match);
3589                         bnxt_free_filter(bp, filter);
3590                 }
3591                 break;
3592         case RTE_ETH_FILTER_FLUSH:
3593                 for (i = bp->nr_vnics - 1; i >= 0; i--) {
3594                         struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
3595
3596                         STAILQ_FOREACH(filter, &vnic->filter, next) {
3597                                 if (filter->filter_type ==
3598                                     HWRM_CFA_NTUPLE_FILTER) {
3599                                         ret =
3600                                         bnxt_hwrm_clear_ntuple_filter(bp,
3601                                                                       filter);
3602                                         STAILQ_REMOVE(&vnic->filter, filter,
3603                                                       bnxt_filter_info, next);
3604                                 }
3605                         }
3606                 }
3607                 return ret;
3608         case RTE_ETH_FILTER_UPDATE:
3609         case RTE_ETH_FILTER_STATS:
3610         case RTE_ETH_FILTER_INFO:
3611                 PMD_DRV_LOG(ERR, "operation %u not implemented", filter_op);
3612                 break;
3613         default:
3614                 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
3615                 ret = -EINVAL;
3616                 break;
3617         }
3618         return ret;
3619
3620 free_filter:
3621         bnxt_free_filter(bp, filter);
3622         return ret;
3623 }
3624
3625 static int
3626 bnxt_filter_ctrl_op(struct rte_eth_dev *dev,
3627                     enum rte_filter_type filter_type,
3628                     enum rte_filter_op filter_op, void *arg)
3629 {
3630         struct bnxt *bp = dev->data->dev_private;
3631         int ret = 0;
3632
3633         ret = is_bnxt_in_error(dev->data->dev_private);
3634         if (ret)
3635                 return ret;
3636
3637         switch (filter_type) {
3638         case RTE_ETH_FILTER_TUNNEL:
3639                 PMD_DRV_LOG(ERR,
3640                         "filter type: %d: To be implemented\n", filter_type);
3641                 break;
3642         case RTE_ETH_FILTER_FDIR:
3643                 ret = bnxt_fdir_filter(dev, filter_op, arg);
3644                 break;
3645         case RTE_ETH_FILTER_NTUPLE:
3646                 ret = bnxt_ntuple_filter(dev, filter_op, arg);
3647                 break;
3648         case RTE_ETH_FILTER_ETHERTYPE:
3649                 ret = bnxt_ethertype_filter(dev, filter_op, arg);
3650                 break;
3651         case RTE_ETH_FILTER_GENERIC:
3652                 if (filter_op != RTE_ETH_FILTER_GET)
3653                         return -EINVAL;
3654                 if (BNXT_TRUFLOW_EN(bp))
3655                         *(const void **)arg = &bnxt_ulp_rte_flow_ops;
3656                 else
3657                         *(const void **)arg = &bnxt_flow_ops;
3658                 break;
3659         default:
3660                 PMD_DRV_LOG(ERR,
3661                         "Filter type (%d) not supported", filter_type);
3662                 ret = -EINVAL;
3663                 break;
3664         }
3665         return ret;
3666 }
3667
3668 static const uint32_t *
3669 bnxt_dev_supported_ptypes_get_op(struct rte_eth_dev *dev)
3670 {
3671         static const uint32_t ptypes[] = {
3672                 RTE_PTYPE_L2_ETHER_VLAN,
3673                 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN,
3674                 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN,
3675                 RTE_PTYPE_L4_ICMP,
3676                 RTE_PTYPE_L4_TCP,
3677                 RTE_PTYPE_L4_UDP,
3678                 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN,
3679                 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN,
3680                 RTE_PTYPE_INNER_L4_ICMP,
3681                 RTE_PTYPE_INNER_L4_TCP,
3682                 RTE_PTYPE_INNER_L4_UDP,
3683                 RTE_PTYPE_UNKNOWN
3684         };
3685
3686         if (!dev->rx_pkt_burst)
3687                 return NULL;
3688
3689         return ptypes;
3690 }
3691
3692 static int bnxt_map_regs(struct bnxt *bp, uint32_t *reg_arr, int count,
3693                          int reg_win)
3694 {
3695         uint32_t reg_base = *reg_arr & 0xfffff000;
3696         uint32_t win_off;
3697         int i;
3698
3699         for (i = 0; i < count; i++) {
3700                 if ((reg_arr[i] & 0xfffff000) != reg_base)
3701                         return -ERANGE;
3702         }
3703         win_off = BNXT_GRCPF_REG_WINDOW_BASE_OUT + (reg_win - 1) * 4;
3704         rte_write32(reg_base, (uint8_t *)bp->bar0 + win_off);
3705         return 0;
3706 }
3707
3708 static int bnxt_map_ptp_regs(struct bnxt *bp)
3709 {
3710         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3711         uint32_t *reg_arr;
3712         int rc, i;
3713
3714         reg_arr = ptp->rx_regs;
3715         rc = bnxt_map_regs(bp, reg_arr, BNXT_PTP_RX_REGS, 5);
3716         if (rc)
3717                 return rc;
3718
3719         reg_arr = ptp->tx_regs;
3720         rc = bnxt_map_regs(bp, reg_arr, BNXT_PTP_TX_REGS, 6);
3721         if (rc)
3722                 return rc;
3723
3724         for (i = 0; i < BNXT_PTP_RX_REGS; i++)
3725                 ptp->rx_mapped_regs[i] = 0x5000 + (ptp->rx_regs[i] & 0xfff);
3726
3727         for (i = 0; i < BNXT_PTP_TX_REGS; i++)
3728                 ptp->tx_mapped_regs[i] = 0x6000 + (ptp->tx_regs[i] & 0xfff);
3729
3730         return 0;
3731 }
3732
3733 static void bnxt_unmap_ptp_regs(struct bnxt *bp)
3734 {
3735         rte_write32(0, (uint8_t *)bp->bar0 +
3736                          BNXT_GRCPF_REG_WINDOW_BASE_OUT + 16);
3737         rte_write32(0, (uint8_t *)bp->bar0 +
3738                          BNXT_GRCPF_REG_WINDOW_BASE_OUT + 20);
3739 }
3740
3741 static uint64_t bnxt_cc_read(struct bnxt *bp)
3742 {
3743         uint64_t ns;
3744
3745         ns = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3746                               BNXT_GRCPF_REG_SYNC_TIME));
3747         ns |= (uint64_t)(rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3748                                           BNXT_GRCPF_REG_SYNC_TIME + 4))) << 32;
3749         return ns;
3750 }
3751
3752 static int bnxt_get_tx_ts(struct bnxt *bp, uint64_t *ts)
3753 {
3754         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3755         uint32_t fifo;
3756
3757         fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3758                                 ptp->tx_mapped_regs[BNXT_PTP_TX_FIFO]));
3759         if (fifo & BNXT_PTP_TX_FIFO_EMPTY)
3760                 return -EAGAIN;
3761
3762         fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3763                                 ptp->tx_mapped_regs[BNXT_PTP_TX_FIFO]));
3764         *ts = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3765                                 ptp->tx_mapped_regs[BNXT_PTP_TX_TS_L]));
3766         *ts |= (uint64_t)rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3767                                 ptp->tx_mapped_regs[BNXT_PTP_TX_TS_H])) << 32;
3768
3769         return 0;
3770 }
3771
3772 static int bnxt_get_rx_ts(struct bnxt *bp, uint64_t *ts)
3773 {
3774         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3775         struct bnxt_pf_info *pf = bp->pf;
3776         uint16_t port_id;
3777         uint32_t fifo;
3778
3779         if (!ptp)
3780                 return -ENODEV;
3781
3782         fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3783                                 ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO]));
3784         if (!(fifo & BNXT_PTP_RX_FIFO_PENDING))
3785                 return -EAGAIN;
3786
3787         port_id = pf->port_id;
3788         rte_write32(1 << port_id, (uint8_t *)bp->bar0 +
3789                ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO_ADV]);
3790
3791         fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3792                                    ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO]));
3793         if (fifo & BNXT_PTP_RX_FIFO_PENDING) {
3794 /*              bnxt_clr_rx_ts(bp);       TBD  */
3795                 return -EBUSY;
3796         }
3797
3798         *ts = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3799                                 ptp->rx_mapped_regs[BNXT_PTP_RX_TS_L]));
3800         *ts |= (uint64_t)rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3801                                 ptp->rx_mapped_regs[BNXT_PTP_RX_TS_H])) << 32;
3802
3803         return 0;
3804 }
3805
3806 static int
3807 bnxt_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
3808 {
3809         uint64_t ns;
3810         struct bnxt *bp = dev->data->dev_private;
3811         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3812
3813         if (!ptp)
3814                 return 0;
3815
3816         ns = rte_timespec_to_ns(ts);
3817         /* Set the timecounters to a new value. */
3818         ptp->tc.nsec = ns;
3819
3820         return 0;
3821 }
3822
3823 static int
3824 bnxt_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
3825 {
3826         struct bnxt *bp = dev->data->dev_private;
3827         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3828         uint64_t ns, systime_cycles = 0;
3829         int rc = 0;
3830
3831         if (!ptp)
3832                 return 0;
3833
3834         if (BNXT_CHIP_THOR(bp))
3835                 rc = bnxt_hwrm_port_ts_query(bp, BNXT_PTP_FLAGS_CURRENT_TIME,
3836                                              &systime_cycles);
3837         else
3838                 systime_cycles = bnxt_cc_read(bp);
3839
3840         ns = rte_timecounter_update(&ptp->tc, systime_cycles);
3841         *ts = rte_ns_to_timespec(ns);
3842
3843         return rc;
3844 }
3845 static int
3846 bnxt_timesync_enable(struct rte_eth_dev *dev)
3847 {
3848         struct bnxt *bp = dev->data->dev_private;
3849         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3850         uint32_t shift = 0;
3851         int rc;
3852
3853         if (!ptp)
3854                 return 0;
3855
3856         ptp->rx_filter = 1;
3857         ptp->tx_tstamp_en = 1;
3858         ptp->rxctl = BNXT_PTP_MSG_EVENTS;
3859
3860         rc = bnxt_hwrm_ptp_cfg(bp);
3861         if (rc)
3862                 return rc;
3863
3864         memset(&ptp->tc, 0, sizeof(struct rte_timecounter));
3865         memset(&ptp->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
3866         memset(&ptp->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
3867
3868         ptp->tc.cc_mask = BNXT_CYCLECOUNTER_MASK;
3869         ptp->tc.cc_shift = shift;
3870         ptp->tc.nsec_mask = (1ULL << shift) - 1;
3871
3872         ptp->rx_tstamp_tc.cc_mask = BNXT_CYCLECOUNTER_MASK;
3873         ptp->rx_tstamp_tc.cc_shift = shift;
3874         ptp->rx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
3875
3876         ptp->tx_tstamp_tc.cc_mask = BNXT_CYCLECOUNTER_MASK;
3877         ptp->tx_tstamp_tc.cc_shift = shift;
3878         ptp->tx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
3879
3880         if (!BNXT_CHIP_THOR(bp))
3881                 bnxt_map_ptp_regs(bp);
3882
3883         return 0;
3884 }
3885
3886 static int
3887 bnxt_timesync_disable(struct rte_eth_dev *dev)
3888 {
3889         struct bnxt *bp = dev->data->dev_private;
3890         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3891
3892         if (!ptp)
3893                 return 0;
3894
3895         ptp->rx_filter = 0;
3896         ptp->tx_tstamp_en = 0;
3897         ptp->rxctl = 0;
3898
3899         bnxt_hwrm_ptp_cfg(bp);
3900
3901         if (!BNXT_CHIP_THOR(bp))
3902                 bnxt_unmap_ptp_regs(bp);
3903
3904         return 0;
3905 }
3906
3907 static int
3908 bnxt_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
3909                                  struct timespec *timestamp,
3910                                  uint32_t flags __rte_unused)
3911 {
3912         struct bnxt *bp = dev->data->dev_private;
3913         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3914         uint64_t rx_tstamp_cycles = 0;
3915         uint64_t ns;
3916
3917         if (!ptp)
3918                 return 0;
3919
3920         if (BNXT_CHIP_THOR(bp))
3921                 rx_tstamp_cycles = ptp->rx_timestamp;
3922         else
3923                 bnxt_get_rx_ts(bp, &rx_tstamp_cycles);
3924
3925         ns = rte_timecounter_update(&ptp->rx_tstamp_tc, rx_tstamp_cycles);
3926         *timestamp = rte_ns_to_timespec(ns);
3927         return  0;
3928 }
3929
3930 static int
3931 bnxt_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
3932                                  struct timespec *timestamp)
3933 {
3934         struct bnxt *bp = dev->data->dev_private;
3935         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3936         uint64_t tx_tstamp_cycles = 0;
3937         uint64_t ns;
3938         int rc = 0;
3939
3940         if (!ptp)
3941                 return 0;
3942
3943         if (BNXT_CHIP_THOR(bp))
3944                 rc = bnxt_hwrm_port_ts_query(bp, BNXT_PTP_FLAGS_PATH_TX,
3945                                              &tx_tstamp_cycles);
3946         else
3947                 rc = bnxt_get_tx_ts(bp, &tx_tstamp_cycles);
3948
3949         ns = rte_timecounter_update(&ptp->tx_tstamp_tc, tx_tstamp_cycles);
3950         *timestamp = rte_ns_to_timespec(ns);
3951
3952         return rc;
3953 }
3954
3955 static int
3956 bnxt_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
3957 {
3958         struct bnxt *bp = dev->data->dev_private;
3959         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3960
3961         if (!ptp)
3962                 return 0;
3963
3964         ptp->tc.nsec += delta;
3965
3966         return 0;
3967 }
3968
3969 static int
3970 bnxt_get_eeprom_length_op(struct rte_eth_dev *dev)
3971 {
3972         struct bnxt *bp = dev->data->dev_private;
3973         int rc;
3974         uint32_t dir_entries;
3975         uint32_t entry_length;
3976
3977         rc = is_bnxt_in_error(bp);
3978         if (rc)
3979                 return rc;
3980
3981         PMD_DRV_LOG(INFO, PCI_PRI_FMT "\n",
3982                     bp->pdev->addr.domain, bp->pdev->addr.bus,
3983                     bp->pdev->addr.devid, bp->pdev->addr.function);
3984
3985         rc = bnxt_hwrm_nvm_get_dir_info(bp, &dir_entries, &entry_length);
3986         if (rc != 0)
3987                 return rc;
3988
3989         return dir_entries * entry_length;
3990 }
3991
3992 static int
3993 bnxt_get_eeprom_op(struct rte_eth_dev *dev,
3994                 struct rte_dev_eeprom_info *in_eeprom)
3995 {
3996         struct bnxt *bp = dev->data->dev_private;
3997         uint32_t index;
3998         uint32_t offset;
3999         int rc;
4000
4001         rc = is_bnxt_in_error(bp);
4002         if (rc)
4003                 return rc;
4004
4005         PMD_DRV_LOG(INFO, PCI_PRI_FMT " in_eeprom->offset = %d len = %d\n",
4006                     bp->pdev->addr.domain, bp->pdev->addr.bus,
4007                     bp->pdev->addr.devid, bp->pdev->addr.function,
4008                     in_eeprom->offset, in_eeprom->length);
4009
4010         if (in_eeprom->offset == 0) /* special offset value to get directory */
4011                 return bnxt_get_nvram_directory(bp, in_eeprom->length,
4012                                                 in_eeprom->data);
4013
4014         index = in_eeprom->offset >> 24;
4015         offset = in_eeprom->offset & 0xffffff;
4016
4017         if (index != 0)
4018                 return bnxt_hwrm_get_nvram_item(bp, index - 1, offset,
4019                                            in_eeprom->length, in_eeprom->data);
4020
4021         return 0;
4022 }
4023
4024 static bool bnxt_dir_type_is_ape_bin_format(uint16_t dir_type)
4025 {
4026         switch (dir_type) {
4027         case BNX_DIR_TYPE_CHIMP_PATCH:
4028         case BNX_DIR_TYPE_BOOTCODE:
4029         case BNX_DIR_TYPE_BOOTCODE_2:
4030         case BNX_DIR_TYPE_APE_FW:
4031         case BNX_DIR_TYPE_APE_PATCH:
4032         case BNX_DIR_TYPE_KONG_FW:
4033         case BNX_DIR_TYPE_KONG_PATCH:
4034         case BNX_DIR_TYPE_BONO_FW:
4035         case BNX_DIR_TYPE_BONO_PATCH:
4036                 /* FALLTHROUGH */
4037                 return true;
4038         }
4039
4040         return false;
4041 }
4042
4043 static bool bnxt_dir_type_is_other_exec_format(uint16_t dir_type)
4044 {
4045         switch (dir_type) {
4046         case BNX_DIR_TYPE_AVS:
4047         case BNX_DIR_TYPE_EXP_ROM_MBA:
4048         case BNX_DIR_TYPE_PCIE:
4049         case BNX_DIR_TYPE_TSCF_UCODE:
4050         case BNX_DIR_TYPE_EXT_PHY:
4051         case BNX_DIR_TYPE_CCM:
4052         case BNX_DIR_TYPE_ISCSI_BOOT:
4053         case BNX_DIR_TYPE_ISCSI_BOOT_IPV6:
4054         case BNX_DIR_TYPE_ISCSI_BOOT_IPV4N6:
4055                 /* FALLTHROUGH */
4056                 return true;
4057         }
4058
4059         return false;
4060 }
4061
4062 static bool bnxt_dir_type_is_executable(uint16_t dir_type)
4063 {
4064         return bnxt_dir_type_is_ape_bin_format(dir_type) ||
4065                 bnxt_dir_type_is_other_exec_format(dir_type);
4066 }
4067
4068 static int
4069 bnxt_set_eeprom_op(struct rte_eth_dev *dev,
4070                 struct rte_dev_eeprom_info *in_eeprom)
4071 {
4072         struct bnxt *bp = dev->data->dev_private;
4073         uint8_t index, dir_op;
4074         uint16_t type, ext, ordinal, attr;
4075         int rc;
4076
4077         rc = is_bnxt_in_error(bp);
4078         if (rc)
4079                 return rc;
4080
4081         PMD_DRV_LOG(INFO, PCI_PRI_FMT " in_eeprom->offset = %d len = %d\n",
4082                     bp->pdev->addr.domain, bp->pdev->addr.bus,
4083                     bp->pdev->addr.devid, bp->pdev->addr.function,
4084                     in_eeprom->offset, in_eeprom->length);
4085
4086         if (!BNXT_PF(bp)) {
4087                 PMD_DRV_LOG(ERR, "NVM write not supported from a VF\n");
4088                 return -EINVAL;
4089         }
4090
4091         type = in_eeprom->magic >> 16;
4092
4093         if (type == 0xffff) { /* special value for directory operations */
4094                 index = in_eeprom->magic & 0xff;
4095                 dir_op = in_eeprom->magic >> 8;
4096                 if (index == 0)
4097                         return -EINVAL;
4098                 switch (dir_op) {
4099                 case 0x0e: /* erase */
4100                         if (in_eeprom->offset != ~in_eeprom->magic)
4101                                 return -EINVAL;
4102                         return bnxt_hwrm_erase_nvram_directory(bp, index - 1);
4103                 default:
4104                         return -EINVAL;
4105                 }
4106         }
4107
4108         /* Create or re-write an NVM item: */
4109         if (bnxt_dir_type_is_executable(type) == true)
4110                 return -EOPNOTSUPP;
4111         ext = in_eeprom->magic & 0xffff;
4112         ordinal = in_eeprom->offset >> 16;
4113         attr = in_eeprom->offset & 0xffff;
4114
4115         return bnxt_hwrm_flash_nvram(bp, type, ordinal, ext, attr,
4116                                      in_eeprom->data, in_eeprom->length);
4117 }
4118
4119 /*
4120  * Initialization
4121  */
4122
4123 static const struct eth_dev_ops bnxt_dev_ops = {
4124         .dev_infos_get = bnxt_dev_info_get_op,
4125         .dev_close = bnxt_dev_close_op,
4126         .dev_configure = bnxt_dev_configure_op,
4127         .dev_start = bnxt_dev_start_op,
4128         .dev_stop = bnxt_dev_stop_op,
4129         .dev_set_link_up = bnxt_dev_set_link_up_op,
4130         .dev_set_link_down = bnxt_dev_set_link_down_op,
4131         .stats_get = bnxt_stats_get_op,
4132         .stats_reset = bnxt_stats_reset_op,
4133         .rx_queue_setup = bnxt_rx_queue_setup_op,
4134         .rx_queue_release = bnxt_rx_queue_release_op,
4135         .tx_queue_setup = bnxt_tx_queue_setup_op,
4136         .tx_queue_release = bnxt_tx_queue_release_op,
4137         .rx_queue_intr_enable = bnxt_rx_queue_intr_enable_op,
4138         .rx_queue_intr_disable = bnxt_rx_queue_intr_disable_op,
4139         .reta_update = bnxt_reta_update_op,
4140         .reta_query = bnxt_reta_query_op,
4141         .rss_hash_update = bnxt_rss_hash_update_op,
4142         .rss_hash_conf_get = bnxt_rss_hash_conf_get_op,
4143         .link_update = bnxt_link_update_op,
4144         .promiscuous_enable = bnxt_promiscuous_enable_op,
4145         .promiscuous_disable = bnxt_promiscuous_disable_op,
4146         .allmulticast_enable = bnxt_allmulticast_enable_op,
4147         .allmulticast_disable = bnxt_allmulticast_disable_op,
4148         .mac_addr_add = bnxt_mac_addr_add_op,
4149         .mac_addr_remove = bnxt_mac_addr_remove_op,
4150         .flow_ctrl_get = bnxt_flow_ctrl_get_op,
4151         .flow_ctrl_set = bnxt_flow_ctrl_set_op,
4152         .udp_tunnel_port_add  = bnxt_udp_tunnel_port_add_op,
4153         .udp_tunnel_port_del  = bnxt_udp_tunnel_port_del_op,
4154         .vlan_filter_set = bnxt_vlan_filter_set_op,
4155         .vlan_offload_set = bnxt_vlan_offload_set_op,
4156         .vlan_tpid_set = bnxt_vlan_tpid_set_op,
4157         .vlan_pvid_set = bnxt_vlan_pvid_set_op,
4158         .mtu_set = bnxt_mtu_set_op,
4159         .mac_addr_set = bnxt_set_default_mac_addr_op,
4160         .xstats_get = bnxt_dev_xstats_get_op,
4161         .xstats_get_names = bnxt_dev_xstats_get_names_op,
4162         .xstats_reset = bnxt_dev_xstats_reset_op,
4163         .fw_version_get = bnxt_fw_version_get,
4164         .set_mc_addr_list = bnxt_dev_set_mc_addr_list_op,
4165         .rxq_info_get = bnxt_rxq_info_get_op,
4166         .txq_info_get = bnxt_txq_info_get_op,
4167         .dev_led_on = bnxt_dev_led_on_op,
4168         .dev_led_off = bnxt_dev_led_off_op,
4169         .xstats_get_by_id = bnxt_dev_xstats_get_by_id_op,
4170         .xstats_get_names_by_id = bnxt_dev_xstats_get_names_by_id_op,
4171         .rx_queue_count = bnxt_rx_queue_count_op,
4172         .rx_descriptor_status = bnxt_rx_descriptor_status_op,
4173         .tx_descriptor_status = bnxt_tx_descriptor_status_op,
4174         .rx_queue_start = bnxt_rx_queue_start,
4175         .rx_queue_stop = bnxt_rx_queue_stop,
4176         .tx_queue_start = bnxt_tx_queue_start,
4177         .tx_queue_stop = bnxt_tx_queue_stop,
4178         .filter_ctrl = bnxt_filter_ctrl_op,
4179         .dev_supported_ptypes_get = bnxt_dev_supported_ptypes_get_op,
4180         .get_eeprom_length    = bnxt_get_eeprom_length_op,
4181         .get_eeprom           = bnxt_get_eeprom_op,
4182         .set_eeprom           = bnxt_set_eeprom_op,
4183         .timesync_enable      = bnxt_timesync_enable,
4184         .timesync_disable     = bnxt_timesync_disable,
4185         .timesync_read_time   = bnxt_timesync_read_time,
4186         .timesync_write_time   = bnxt_timesync_write_time,
4187         .timesync_adjust_time = bnxt_timesync_adjust_time,
4188         .timesync_read_rx_timestamp = bnxt_timesync_read_rx_timestamp,
4189         .timesync_read_tx_timestamp = bnxt_timesync_read_tx_timestamp,
4190 };
4191
4192 static uint32_t bnxt_map_reset_regs(struct bnxt *bp, uint32_t reg)
4193 {
4194         uint32_t offset;
4195
4196         /* Only pre-map the reset GRC registers using window 3 */
4197         rte_write32(reg & 0xfffff000, (uint8_t *)bp->bar0 +
4198                     BNXT_GRCPF_REG_WINDOW_BASE_OUT + 8);
4199
4200         offset = BNXT_GRCP_WINDOW_3_BASE + (reg & 0xffc);
4201
4202         return offset;
4203 }
4204
4205 int bnxt_map_fw_health_status_regs(struct bnxt *bp)
4206 {
4207         struct bnxt_error_recovery_info *info = bp->recovery_info;
4208         uint32_t reg_base = 0xffffffff;
4209         int i;
4210
4211         /* Only pre-map the monitoring GRC registers using window 2 */
4212         for (i = 0; i < BNXT_FW_STATUS_REG_CNT; i++) {
4213                 uint32_t reg = info->status_regs[i];
4214
4215                 if (BNXT_FW_STATUS_REG_TYPE(reg) != BNXT_FW_STATUS_REG_TYPE_GRC)
4216                         continue;
4217
4218                 if (reg_base == 0xffffffff)
4219                         reg_base = reg & 0xfffff000;
4220                 if ((reg & 0xfffff000) != reg_base)
4221                         return -ERANGE;
4222
4223                 /* Use mask 0xffc as the Lower 2 bits indicates
4224                  * address space location
4225                  */
4226                 info->mapped_status_regs[i] = BNXT_GRCP_WINDOW_2_BASE +
4227                                                 (reg & 0xffc);
4228         }
4229
4230         if (reg_base == 0xffffffff)
4231                 return 0;
4232
4233         rte_write32(reg_base, (uint8_t *)bp->bar0 +
4234                     BNXT_GRCPF_REG_WINDOW_BASE_OUT + 4);
4235
4236         return 0;
4237 }
4238
4239 static void bnxt_write_fw_reset_reg(struct bnxt *bp, uint32_t index)
4240 {
4241         struct bnxt_error_recovery_info *info = bp->recovery_info;
4242         uint32_t delay = info->delay_after_reset[index];
4243         uint32_t val = info->reset_reg_val[index];
4244         uint32_t reg = info->reset_reg[index];
4245         uint32_t type, offset;
4246
4247         type = BNXT_FW_STATUS_REG_TYPE(reg);
4248         offset = BNXT_FW_STATUS_REG_OFF(reg);
4249
4250         switch (type) {
4251         case BNXT_FW_STATUS_REG_TYPE_CFG:
4252                 rte_pci_write_config(bp->pdev, &val, sizeof(val), offset);
4253                 break;
4254         case BNXT_FW_STATUS_REG_TYPE_GRC:
4255                 offset = bnxt_map_reset_regs(bp, offset);
4256                 rte_write32(val, (uint8_t *)bp->bar0 + offset);
4257                 break;
4258         case BNXT_FW_STATUS_REG_TYPE_BAR0:
4259                 rte_write32(val, (uint8_t *)bp->bar0 + offset);
4260                 break;
4261         }
4262         /* wait on a specific interval of time until core reset is complete */
4263         if (delay)
4264                 rte_delay_ms(delay);
4265 }
4266
4267 static void bnxt_dev_cleanup(struct bnxt *bp)
4268 {
4269         bnxt_set_hwrm_link_config(bp, false);
4270         bp->link_info->link_up = 0;
4271         if (bp->eth_dev->data->dev_started)
4272                 bnxt_dev_stop_op(bp->eth_dev);
4273
4274         bnxt_uninit_resources(bp, true);
4275 }
4276
4277 static int bnxt_restore_vlan_filters(struct bnxt *bp)
4278 {
4279         struct rte_eth_dev *dev = bp->eth_dev;
4280         struct rte_vlan_filter_conf *vfc;
4281         int vidx, vbit, rc;
4282         uint16_t vlan_id;
4283
4284         for (vlan_id = 1; vlan_id <= RTE_ETHER_MAX_VLAN_ID; vlan_id++) {
4285                 vfc = &dev->data->vlan_filter_conf;
4286                 vidx = vlan_id / 64;
4287                 vbit = vlan_id % 64;
4288
4289                 /* Each bit corresponds to a VLAN id */
4290                 if (vfc->ids[vidx] & (UINT64_C(1) << vbit)) {
4291                         rc = bnxt_add_vlan_filter(bp, vlan_id);
4292                         if (rc)
4293                                 return rc;
4294                 }
4295         }
4296
4297         return 0;
4298 }
4299
4300 static int bnxt_restore_mac_filters(struct bnxt *bp)
4301 {
4302         struct rte_eth_dev *dev = bp->eth_dev;
4303         struct rte_eth_dev_info dev_info;
4304         struct rte_ether_addr *addr;
4305         uint64_t pool_mask;
4306         uint32_t pool = 0;
4307         uint16_t i;
4308         int rc;
4309
4310         if (BNXT_VF(bp) & !BNXT_VF_IS_TRUSTED(bp))
4311                 return 0;
4312
4313         rc = bnxt_dev_info_get_op(dev, &dev_info);
4314         if (rc)
4315                 return rc;
4316
4317         /* replay MAC address configuration */
4318         for (i = 1; i < dev_info.max_mac_addrs; i++) {
4319                 addr = &dev->data->mac_addrs[i];
4320
4321                 /* skip zero address */
4322                 if (rte_is_zero_ether_addr(addr))
4323                         continue;
4324
4325                 pool = 0;
4326                 pool_mask = dev->data->mac_pool_sel[i];
4327
4328                 do {
4329                         if (pool_mask & 1ULL) {
4330                                 rc = bnxt_mac_addr_add_op(dev, addr, i, pool);
4331                                 if (rc)
4332                                         return rc;
4333                         }
4334                         pool_mask >>= 1;
4335                         pool++;
4336                 } while (pool_mask);
4337         }
4338
4339         return 0;
4340 }
4341
4342 static int bnxt_restore_filters(struct bnxt *bp)
4343 {
4344         struct rte_eth_dev *dev = bp->eth_dev;
4345         int ret = 0;
4346
4347         if (dev->data->all_multicast) {
4348                 ret = bnxt_allmulticast_enable_op(dev);
4349                 if (ret)
4350                         return ret;
4351         }
4352         if (dev->data->promiscuous) {
4353                 ret = bnxt_promiscuous_enable_op(dev);
4354                 if (ret)
4355                         return ret;
4356         }
4357
4358         ret = bnxt_restore_mac_filters(bp);
4359         if (ret)
4360                 return ret;
4361
4362         ret = bnxt_restore_vlan_filters(bp);
4363         /* TODO restore other filters as well */
4364         return ret;
4365 }
4366
4367 static void bnxt_dev_recover(void *arg)
4368 {
4369         struct bnxt *bp = arg;
4370         int timeout = bp->fw_reset_max_msecs;
4371         int rc = 0;
4372
4373         /* Clear Error flag so that device re-init should happen */
4374         bp->flags &= ~BNXT_FLAG_FATAL_ERROR;
4375
4376         do {
4377                 rc = bnxt_hwrm_ver_get(bp, SHORT_HWRM_CMD_TIMEOUT);
4378                 if (rc == 0)
4379                         break;
4380                 rte_delay_ms(BNXT_FW_READY_WAIT_INTERVAL);
4381                 timeout -= BNXT_FW_READY_WAIT_INTERVAL;
4382         } while (rc && timeout);
4383
4384         if (rc) {
4385                 PMD_DRV_LOG(ERR, "FW is not Ready after reset\n");
4386                 goto err;
4387         }
4388
4389         rc = bnxt_init_resources(bp, true);
4390         if (rc) {
4391                 PMD_DRV_LOG(ERR,
4392                             "Failed to initialize resources after reset\n");
4393                 goto err;
4394         }
4395         /* clear reset flag as the device is initialized now */
4396         bp->flags &= ~BNXT_FLAG_FW_RESET;
4397
4398         rc = bnxt_dev_start_op(bp->eth_dev);
4399         if (rc) {
4400                 PMD_DRV_LOG(ERR, "Failed to start port after reset\n");
4401                 goto err_start;
4402         }
4403
4404         rc = bnxt_restore_filters(bp);
4405         if (rc)
4406                 goto err_start;
4407
4408         PMD_DRV_LOG(INFO, "Recovered from FW reset\n");
4409         return;
4410 err_start:
4411         bnxt_dev_stop_op(bp->eth_dev);
4412 err:
4413         bp->flags |= BNXT_FLAG_FATAL_ERROR;
4414         bnxt_uninit_resources(bp, false);
4415         PMD_DRV_LOG(ERR, "Failed to recover from FW reset\n");
4416 }
4417
4418 void bnxt_dev_reset_and_resume(void *arg)
4419 {
4420         struct bnxt *bp = arg;
4421         int rc;
4422
4423         bnxt_dev_cleanup(bp);
4424
4425         bnxt_wait_for_device_shutdown(bp);
4426
4427         rc = rte_eal_alarm_set(US_PER_MS * bp->fw_reset_min_msecs,
4428                                bnxt_dev_recover, (void *)bp);
4429         if (rc)
4430                 PMD_DRV_LOG(ERR, "Error setting recovery alarm");
4431 }
4432
4433 uint32_t bnxt_read_fw_status_reg(struct bnxt *bp, uint32_t index)
4434 {
4435         struct bnxt_error_recovery_info *info = bp->recovery_info;
4436         uint32_t reg = info->status_regs[index];
4437         uint32_t type, offset, val = 0;
4438
4439         type = BNXT_FW_STATUS_REG_TYPE(reg);
4440         offset = BNXT_FW_STATUS_REG_OFF(reg);
4441
4442         switch (type) {
4443         case BNXT_FW_STATUS_REG_TYPE_CFG:
4444                 rte_pci_read_config(bp->pdev, &val, sizeof(val), offset);
4445                 break;
4446         case BNXT_FW_STATUS_REG_TYPE_GRC:
4447                 offset = info->mapped_status_regs[index];
4448                 /* FALLTHROUGH */
4449         case BNXT_FW_STATUS_REG_TYPE_BAR0:
4450                 val = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
4451                                        offset));
4452                 break;
4453         }
4454
4455         return val;
4456 }
4457
4458 static int bnxt_fw_reset_all(struct bnxt *bp)
4459 {
4460         struct bnxt_error_recovery_info *info = bp->recovery_info;
4461         uint32_t i;
4462         int rc = 0;
4463
4464         if (info->flags & BNXT_FLAG_ERROR_RECOVERY_HOST) {
4465                 /* Reset through master function driver */
4466                 for (i = 0; i < info->reg_array_cnt; i++)
4467                         bnxt_write_fw_reset_reg(bp, i);
4468                 /* Wait for time specified by FW after triggering reset */
4469                 rte_delay_ms(info->master_func_wait_period_after_reset);
4470         } else if (info->flags & BNXT_FLAG_ERROR_RECOVERY_CO_CPU) {
4471                 /* Reset with the help of Kong processor */
4472                 rc = bnxt_hwrm_fw_reset(bp);
4473                 if (rc)
4474                         PMD_DRV_LOG(ERR, "Failed to reset FW\n");
4475         }
4476
4477         return rc;
4478 }
4479
4480 static void bnxt_fw_reset_cb(void *arg)
4481 {
4482         struct bnxt *bp = arg;
4483         struct bnxt_error_recovery_info *info = bp->recovery_info;
4484         int rc = 0;
4485
4486         /* Only Master function can do FW reset */
4487         if (bnxt_is_master_func(bp) &&
4488             bnxt_is_recovery_enabled(bp)) {
4489                 rc = bnxt_fw_reset_all(bp);
4490                 if (rc) {
4491                         PMD_DRV_LOG(ERR, "Adapter recovery failed\n");
4492                         return;
4493                 }
4494         }
4495
4496         /* if recovery method is ERROR_RECOVERY_CO_CPU, KONG will send
4497          * EXCEPTION_FATAL_ASYNC event to all the functions
4498          * (including MASTER FUNC). After receiving this Async, all the active
4499          * drivers should treat this case as FW initiated recovery
4500          */
4501         if (info->flags & BNXT_FLAG_ERROR_RECOVERY_HOST) {
4502                 bp->fw_reset_min_msecs = BNXT_MIN_FW_READY_TIMEOUT;
4503                 bp->fw_reset_max_msecs = BNXT_MAX_FW_RESET_TIMEOUT;
4504
4505                 /* To recover from error */
4506                 rte_eal_alarm_set(US_PER_MS, bnxt_dev_reset_and_resume,
4507                                   (void *)bp);
4508         }
4509 }
4510
4511 /* Driver should poll FW heartbeat, reset_counter with the frequency
4512  * advertised by FW in HWRM_ERROR_RECOVERY_QCFG.
4513  * When the driver detects heartbeat stop or change in reset_counter,
4514  * it has to trigger a reset to recover from the error condition.
4515  * A “master PF” is the function who will have the privilege to
4516  * initiate the chimp reset. The master PF will be elected by the
4517  * firmware and will be notified through async message.
4518  */
4519 static void bnxt_check_fw_health(void *arg)
4520 {
4521         struct bnxt *bp = arg;
4522         struct bnxt_error_recovery_info *info = bp->recovery_info;
4523         uint32_t val = 0, wait_msec;
4524
4525         if (!info || !bnxt_is_recovery_enabled(bp) ||
4526             is_bnxt_in_error(bp))
4527                 return;
4528
4529         val = bnxt_read_fw_status_reg(bp, BNXT_FW_HEARTBEAT_CNT_REG);
4530         if (val == info->last_heart_beat)
4531                 goto reset;
4532
4533         info->last_heart_beat = val;
4534
4535         val = bnxt_read_fw_status_reg(bp, BNXT_FW_RECOVERY_CNT_REG);
4536         if (val != info->last_reset_counter)
4537                 goto reset;
4538
4539         info->last_reset_counter = val;
4540
4541         rte_eal_alarm_set(US_PER_MS * info->driver_polling_freq,
4542                           bnxt_check_fw_health, (void *)bp);
4543
4544         return;
4545 reset:
4546         /* Stop DMA to/from device */
4547         bp->flags |= BNXT_FLAG_FATAL_ERROR;
4548         bp->flags |= BNXT_FLAG_FW_RESET;
4549
4550         PMD_DRV_LOG(ERR, "Detected FW dead condition\n");
4551
4552         if (bnxt_is_master_func(bp))
4553                 wait_msec = info->master_func_wait_period;
4554         else
4555                 wait_msec = info->normal_func_wait_period;
4556
4557         rte_eal_alarm_set(US_PER_MS * wait_msec,
4558                           bnxt_fw_reset_cb, (void *)bp);
4559 }
4560
4561 void bnxt_schedule_fw_health_check(struct bnxt *bp)
4562 {
4563         uint32_t polling_freq;
4564
4565         if (!bnxt_is_recovery_enabled(bp))
4566                 return;
4567
4568         if (bp->flags & BNXT_FLAG_FW_HEALTH_CHECK_SCHEDULED)
4569                 return;
4570
4571         polling_freq = bp->recovery_info->driver_polling_freq;
4572
4573         rte_eal_alarm_set(US_PER_MS * polling_freq,
4574                           bnxt_check_fw_health, (void *)bp);
4575         bp->flags |= BNXT_FLAG_FW_HEALTH_CHECK_SCHEDULED;
4576 }
4577
4578 static void bnxt_cancel_fw_health_check(struct bnxt *bp)
4579 {
4580         if (!bnxt_is_recovery_enabled(bp))
4581                 return;
4582
4583         rte_eal_alarm_cancel(bnxt_check_fw_health, (void *)bp);
4584         bp->flags &= ~BNXT_FLAG_FW_HEALTH_CHECK_SCHEDULED;
4585 }
4586
4587 static bool bnxt_vf_pciid(uint16_t device_id)
4588 {
4589         switch (device_id) {
4590         case BROADCOM_DEV_ID_57304_VF:
4591         case BROADCOM_DEV_ID_57406_VF:
4592         case BROADCOM_DEV_ID_5731X_VF:
4593         case BROADCOM_DEV_ID_5741X_VF:
4594         case BROADCOM_DEV_ID_57414_VF:
4595         case BROADCOM_DEV_ID_STRATUS_NIC_VF1:
4596         case BROADCOM_DEV_ID_STRATUS_NIC_VF2:
4597         case BROADCOM_DEV_ID_58802_VF:
4598         case BROADCOM_DEV_ID_57500_VF1:
4599         case BROADCOM_DEV_ID_57500_VF2:
4600                 /* FALLTHROUGH */
4601                 return true;
4602         default:
4603                 return false;
4604         }
4605 }
4606
4607 static bool bnxt_thor_device(uint16_t device_id)
4608 {
4609         switch (device_id) {
4610         case BROADCOM_DEV_ID_57508:
4611         case BROADCOM_DEV_ID_57504:
4612         case BROADCOM_DEV_ID_57502:
4613         case BROADCOM_DEV_ID_57508_MF1:
4614         case BROADCOM_DEV_ID_57504_MF1:
4615         case BROADCOM_DEV_ID_57502_MF1:
4616         case BROADCOM_DEV_ID_57508_MF2:
4617         case BROADCOM_DEV_ID_57504_MF2:
4618         case BROADCOM_DEV_ID_57502_MF2:
4619         case BROADCOM_DEV_ID_57500_VF1:
4620         case BROADCOM_DEV_ID_57500_VF2:
4621                 /* FALLTHROUGH */
4622                 return true;
4623         default:
4624                 return false;
4625         }
4626 }
4627
4628 bool bnxt_stratus_device(struct bnxt *bp)
4629 {
4630         uint16_t device_id = bp->pdev->id.device_id;
4631
4632         switch (device_id) {
4633         case BROADCOM_DEV_ID_STRATUS_NIC:
4634         case BROADCOM_DEV_ID_STRATUS_NIC_VF1:
4635         case BROADCOM_DEV_ID_STRATUS_NIC_VF2:
4636                 /* FALLTHROUGH */
4637                 return true;
4638         default:
4639                 return false;
4640         }
4641 }
4642
4643 static int bnxt_init_board(struct rte_eth_dev *eth_dev)
4644 {
4645         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
4646         struct bnxt *bp = eth_dev->data->dev_private;
4647
4648         /* enable device (incl. PCI PM wakeup), and bus-mastering */
4649         bp->bar0 = (void *)pci_dev->mem_resource[0].addr;
4650         bp->doorbell_base = (void *)pci_dev->mem_resource[2].addr;
4651         if (!bp->bar0 || !bp->doorbell_base) {
4652                 PMD_DRV_LOG(ERR, "Unable to access Hardware\n");
4653                 return -ENODEV;
4654         }
4655
4656         bp->eth_dev = eth_dev;
4657         bp->pdev = pci_dev;
4658
4659         return 0;
4660 }
4661
4662 static int bnxt_alloc_ctx_mem_blk(struct bnxt *bp,
4663                                   struct bnxt_ctx_pg_info *ctx_pg,
4664                                   uint32_t mem_size,
4665                                   const char *suffix,
4666                                   uint16_t idx)
4667 {
4668         struct bnxt_ring_mem_info *rmem = &ctx_pg->ring_mem;
4669         const struct rte_memzone *mz = NULL;
4670         char mz_name[RTE_MEMZONE_NAMESIZE];
4671         rte_iova_t mz_phys_addr;
4672         uint64_t valid_bits = 0;
4673         uint32_t sz;
4674         int i;
4675
4676         if (!mem_size)
4677                 return 0;
4678
4679         rmem->nr_pages = RTE_ALIGN_MUL_CEIL(mem_size, BNXT_PAGE_SIZE) /
4680                          BNXT_PAGE_SIZE;
4681         rmem->page_size = BNXT_PAGE_SIZE;
4682         rmem->pg_arr = ctx_pg->ctx_pg_arr;
4683         rmem->dma_arr = ctx_pg->ctx_dma_arr;
4684         rmem->flags = BNXT_RMEM_VALID_PTE_FLAG;
4685
4686         valid_bits = PTU_PTE_VALID;
4687
4688         if (rmem->nr_pages > 1) {
4689                 snprintf(mz_name, RTE_MEMZONE_NAMESIZE,
4690                          "bnxt_ctx_pg_tbl%s_%x_%d",
4691                          suffix, idx, bp->eth_dev->data->port_id);
4692                 mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0;
4693                 mz = rte_memzone_lookup(mz_name);
4694                 if (!mz) {
4695                         mz = rte_memzone_reserve_aligned(mz_name,
4696                                                 rmem->nr_pages * 8,
4697                                                 SOCKET_ID_ANY,
4698                                                 RTE_MEMZONE_2MB |
4699                                                 RTE_MEMZONE_SIZE_HINT_ONLY |
4700                                                 RTE_MEMZONE_IOVA_CONTIG,
4701                                                 BNXT_PAGE_SIZE);
4702                         if (mz == NULL)
4703                                 return -ENOMEM;
4704                 }
4705
4706                 memset(mz->addr, 0, mz->len);
4707                 mz_phys_addr = mz->iova;
4708
4709                 rmem->pg_tbl = mz->addr;
4710                 rmem->pg_tbl_map = mz_phys_addr;
4711                 rmem->pg_tbl_mz = mz;
4712         }
4713
4714         snprintf(mz_name, RTE_MEMZONE_NAMESIZE, "bnxt_ctx_%s_%x_%d",
4715                  suffix, idx, bp->eth_dev->data->port_id);
4716         mz = rte_memzone_lookup(mz_name);
4717         if (!mz) {
4718                 mz = rte_memzone_reserve_aligned(mz_name,
4719                                                  mem_size,
4720                                                  SOCKET_ID_ANY,
4721                                                  RTE_MEMZONE_1GB |
4722                                                  RTE_MEMZONE_SIZE_HINT_ONLY |
4723                                                  RTE_MEMZONE_IOVA_CONTIG,
4724                                                  BNXT_PAGE_SIZE);
4725                 if (mz == NULL)
4726                         return -ENOMEM;
4727         }
4728
4729         memset(mz->addr, 0, mz->len);
4730         mz_phys_addr = mz->iova;
4731
4732         for (sz = 0, i = 0; sz < mem_size; sz += BNXT_PAGE_SIZE, i++) {
4733                 rmem->pg_arr[i] = ((char *)mz->addr) + sz;
4734                 rmem->dma_arr[i] = mz_phys_addr + sz;
4735
4736                 if (rmem->nr_pages > 1) {
4737                         if (i == rmem->nr_pages - 2 &&
4738                             (rmem->flags & BNXT_RMEM_RING_PTE_FLAG))
4739                                 valid_bits |= PTU_PTE_NEXT_TO_LAST;
4740                         else if (i == rmem->nr_pages - 1 &&
4741                                  (rmem->flags & BNXT_RMEM_RING_PTE_FLAG))
4742                                 valid_bits |= PTU_PTE_LAST;
4743
4744                         rmem->pg_tbl[i] = rte_cpu_to_le_64(rmem->dma_arr[i] |
4745                                                            valid_bits);
4746                 }
4747         }
4748
4749         rmem->mz = mz;
4750         if (rmem->vmem_size)
4751                 rmem->vmem = (void **)mz->addr;
4752         rmem->dma_arr[0] = mz_phys_addr;
4753         return 0;
4754 }
4755
4756 static void bnxt_free_ctx_mem(struct bnxt *bp)
4757 {
4758         int i;
4759
4760         if (!bp->ctx || !(bp->ctx->flags & BNXT_CTX_FLAG_INITED))
4761                 return;
4762
4763         bp->ctx->flags &= ~BNXT_CTX_FLAG_INITED;
4764         rte_memzone_free(bp->ctx->qp_mem.ring_mem.mz);
4765         rte_memzone_free(bp->ctx->srq_mem.ring_mem.mz);
4766         rte_memzone_free(bp->ctx->cq_mem.ring_mem.mz);
4767         rte_memzone_free(bp->ctx->vnic_mem.ring_mem.mz);
4768         rte_memzone_free(bp->ctx->stat_mem.ring_mem.mz);
4769         rte_memzone_free(bp->ctx->qp_mem.ring_mem.pg_tbl_mz);
4770         rte_memzone_free(bp->ctx->srq_mem.ring_mem.pg_tbl_mz);
4771         rte_memzone_free(bp->ctx->cq_mem.ring_mem.pg_tbl_mz);
4772         rte_memzone_free(bp->ctx->vnic_mem.ring_mem.pg_tbl_mz);
4773         rte_memzone_free(bp->ctx->stat_mem.ring_mem.pg_tbl_mz);
4774
4775         for (i = 0; i < bp->ctx->tqm_fp_rings_count + 1; i++) {
4776                 if (bp->ctx->tqm_mem[i])
4777                         rte_memzone_free(bp->ctx->tqm_mem[i]->ring_mem.mz);
4778         }
4779
4780         rte_free(bp->ctx);
4781         bp->ctx = NULL;
4782 }
4783
4784 #define bnxt_roundup(x, y)   ((((x) + ((y) - 1)) / (y)) * (y))
4785
4786 #define min_t(type, x, y) ({                    \
4787         type __min1 = (x);                      \
4788         type __min2 = (y);                      \
4789         __min1 < __min2 ? __min1 : __min2; })
4790
4791 #define max_t(type, x, y) ({                    \
4792         type __max1 = (x);                      \
4793         type __max2 = (y);                      \
4794         __max1 > __max2 ? __max1 : __max2; })
4795
4796 #define clamp_t(type, _x, min, max)     min_t(type, max_t(type, _x, min), max)
4797
4798 int bnxt_alloc_ctx_mem(struct bnxt *bp)
4799 {
4800         struct bnxt_ctx_pg_info *ctx_pg;
4801         struct bnxt_ctx_mem_info *ctx;
4802         uint32_t mem_size, ena, entries;
4803         uint32_t entries_sp, min;
4804         int i, rc;
4805
4806         rc = bnxt_hwrm_func_backing_store_qcaps(bp);
4807         if (rc) {
4808                 PMD_DRV_LOG(ERR, "Query context mem capability failed\n");
4809                 return rc;
4810         }
4811         ctx = bp->ctx;
4812         if (!ctx || (ctx->flags & BNXT_CTX_FLAG_INITED))
4813                 return 0;
4814
4815         ctx_pg = &ctx->qp_mem;
4816         ctx_pg->entries = ctx->qp_min_qp1_entries + ctx->qp_max_l2_entries;
4817         mem_size = ctx->qp_entry_size * ctx_pg->entries;
4818         rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "qp_mem", 0);
4819         if (rc)
4820                 return rc;
4821
4822         ctx_pg = &ctx->srq_mem;
4823         ctx_pg->entries = ctx->srq_max_l2_entries;
4824         mem_size = ctx->srq_entry_size * ctx_pg->entries;
4825         rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "srq_mem", 0);
4826         if (rc)
4827                 return rc;
4828
4829         ctx_pg = &ctx->cq_mem;
4830         ctx_pg->entries = ctx->cq_max_l2_entries;
4831         mem_size = ctx->cq_entry_size * ctx_pg->entries;
4832         rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "cq_mem", 0);
4833         if (rc)
4834                 return rc;
4835
4836         ctx_pg = &ctx->vnic_mem;
4837         ctx_pg->entries = ctx->vnic_max_vnic_entries +
4838                 ctx->vnic_max_ring_table_entries;
4839         mem_size = ctx->vnic_entry_size * ctx_pg->entries;
4840         rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "vnic_mem", 0);
4841         if (rc)
4842                 return rc;
4843
4844         ctx_pg = &ctx->stat_mem;
4845         ctx_pg->entries = ctx->stat_max_entries;
4846         mem_size = ctx->stat_entry_size * ctx_pg->entries;
4847         rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "stat_mem", 0);
4848         if (rc)
4849                 return rc;
4850
4851         min = ctx->tqm_min_entries_per_ring;
4852
4853         entries_sp = ctx->qp_max_l2_entries +
4854                      ctx->vnic_max_vnic_entries +
4855                      2 * ctx->qp_min_qp1_entries + min;
4856         entries_sp = bnxt_roundup(entries_sp, ctx->tqm_entries_multiple);
4857
4858         entries = ctx->qp_max_l2_entries + ctx->qp_min_qp1_entries;
4859         entries = bnxt_roundup(entries, ctx->tqm_entries_multiple);
4860         entries = clamp_t(uint32_t, entries, min,
4861                           ctx->tqm_max_entries_per_ring);
4862         for (i = 0, ena = 0; i < ctx->tqm_fp_rings_count + 1; i++) {
4863                 ctx_pg = ctx->tqm_mem[i];
4864                 ctx_pg->entries = i ? entries : entries_sp;
4865                 mem_size = ctx->tqm_entry_size * ctx_pg->entries;
4866                 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "tqm_mem", i);
4867                 if (rc)
4868                         return rc;
4869                 ena |= HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_SP << i;
4870         }
4871
4872         ena |= FUNC_BACKING_STORE_CFG_INPUT_DFLT_ENABLES;
4873         rc = bnxt_hwrm_func_backing_store_cfg(bp, ena);
4874         if (rc)
4875                 PMD_DRV_LOG(ERR,
4876                             "Failed to configure context mem: rc = %d\n", rc);
4877         else
4878                 ctx->flags |= BNXT_CTX_FLAG_INITED;
4879
4880         return rc;
4881 }
4882
4883 static int bnxt_alloc_stats_mem(struct bnxt *bp)
4884 {
4885         struct rte_pci_device *pci_dev = bp->pdev;
4886         char mz_name[RTE_MEMZONE_NAMESIZE];
4887         const struct rte_memzone *mz = NULL;
4888         uint32_t total_alloc_len;
4889         rte_iova_t mz_phys_addr;
4890
4891         if (pci_dev->id.device_id == BROADCOM_DEV_ID_NS2)
4892                 return 0;
4893
4894         snprintf(mz_name, RTE_MEMZONE_NAMESIZE,
4895                  "bnxt_" PCI_PRI_FMT "-%s", pci_dev->addr.domain,
4896                  pci_dev->addr.bus, pci_dev->addr.devid,
4897                  pci_dev->addr.function, "rx_port_stats");
4898         mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0;
4899         mz = rte_memzone_lookup(mz_name);
4900         total_alloc_len =
4901                 RTE_CACHE_LINE_ROUNDUP(sizeof(struct rx_port_stats) +
4902                                        sizeof(struct rx_port_stats_ext) + 512);
4903         if (!mz) {
4904                 mz = rte_memzone_reserve(mz_name, total_alloc_len,
4905                                          SOCKET_ID_ANY,
4906                                          RTE_MEMZONE_2MB |
4907                                          RTE_MEMZONE_SIZE_HINT_ONLY |
4908                                          RTE_MEMZONE_IOVA_CONTIG);
4909                 if (mz == NULL)
4910                         return -ENOMEM;
4911         }
4912         memset(mz->addr, 0, mz->len);
4913         mz_phys_addr = mz->iova;
4914
4915         bp->rx_mem_zone = (const void *)mz;
4916         bp->hw_rx_port_stats = mz->addr;
4917         bp->hw_rx_port_stats_map = mz_phys_addr;
4918
4919         snprintf(mz_name, RTE_MEMZONE_NAMESIZE,
4920                  "bnxt_" PCI_PRI_FMT "-%s", pci_dev->addr.domain,
4921                  pci_dev->addr.bus, pci_dev->addr.devid,
4922                  pci_dev->addr.function, "tx_port_stats");
4923         mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0;
4924         mz = rte_memzone_lookup(mz_name);
4925         total_alloc_len =
4926                 RTE_CACHE_LINE_ROUNDUP(sizeof(struct tx_port_stats) +
4927                                        sizeof(struct tx_port_stats_ext) + 512);
4928         if (!mz) {
4929                 mz = rte_memzone_reserve(mz_name,
4930                                          total_alloc_len,
4931                                          SOCKET_ID_ANY,
4932                                          RTE_MEMZONE_2MB |
4933                                          RTE_MEMZONE_SIZE_HINT_ONLY |
4934                                          RTE_MEMZONE_IOVA_CONTIG);
4935                 if (mz == NULL)
4936                         return -ENOMEM;
4937         }
4938         memset(mz->addr, 0, mz->len);
4939         mz_phys_addr = mz->iova;
4940
4941         bp->tx_mem_zone = (const void *)mz;
4942         bp->hw_tx_port_stats = mz->addr;
4943         bp->hw_tx_port_stats_map = mz_phys_addr;
4944         bp->flags |= BNXT_FLAG_PORT_STATS;
4945
4946         /* Display extended statistics if FW supports it */
4947         if (bp->hwrm_spec_code < HWRM_SPEC_CODE_1_8_4 ||
4948             bp->hwrm_spec_code == HWRM_SPEC_CODE_1_9_0 ||
4949             !(bp->flags & BNXT_FLAG_EXT_STATS_SUPPORTED))
4950                 return 0;
4951
4952         bp->hw_rx_port_stats_ext = (void *)
4953                 ((uint8_t *)bp->hw_rx_port_stats +
4954                  sizeof(struct rx_port_stats));
4955         bp->hw_rx_port_stats_ext_map = bp->hw_rx_port_stats_map +
4956                 sizeof(struct rx_port_stats);
4957         bp->flags |= BNXT_FLAG_EXT_RX_PORT_STATS;
4958
4959         if (bp->hwrm_spec_code < HWRM_SPEC_CODE_1_9_2 ||
4960             bp->flags & BNXT_FLAG_EXT_STATS_SUPPORTED) {
4961                 bp->hw_tx_port_stats_ext = (void *)
4962                         ((uint8_t *)bp->hw_tx_port_stats +
4963                          sizeof(struct tx_port_stats));
4964                 bp->hw_tx_port_stats_ext_map =
4965                         bp->hw_tx_port_stats_map +
4966                         sizeof(struct tx_port_stats);
4967                 bp->flags |= BNXT_FLAG_EXT_TX_PORT_STATS;
4968         }
4969
4970         return 0;
4971 }
4972
4973 static int bnxt_setup_mac_addr(struct rte_eth_dev *eth_dev)
4974 {
4975         struct bnxt *bp = eth_dev->data->dev_private;
4976         int rc = 0;
4977
4978         eth_dev->data->mac_addrs = rte_zmalloc("bnxt_mac_addr_tbl",
4979                                                RTE_ETHER_ADDR_LEN *
4980                                                bp->max_l2_ctx,
4981                                                0);
4982         if (eth_dev->data->mac_addrs == NULL) {
4983                 PMD_DRV_LOG(ERR, "Failed to alloc MAC addr tbl\n");
4984                 return -ENOMEM;
4985         }
4986
4987         if (!BNXT_HAS_DFLT_MAC_SET(bp)) {
4988                 if (BNXT_PF(bp))
4989                         return -EINVAL;
4990
4991                 /* Generate a random MAC address, if none was assigned by PF */
4992                 PMD_DRV_LOG(INFO, "VF MAC address not assigned by Host PF\n");
4993                 bnxt_eth_hw_addr_random(bp->mac_addr);
4994                 PMD_DRV_LOG(INFO,
4995                             "Assign random MAC:%02X:%02X:%02X:%02X:%02X:%02X\n",
4996                             bp->mac_addr[0], bp->mac_addr[1], bp->mac_addr[2],
4997                             bp->mac_addr[3], bp->mac_addr[4], bp->mac_addr[5]);
4998
4999                 rc = bnxt_hwrm_set_mac(bp);
5000                 if (rc)
5001                         return rc;
5002         }
5003
5004         /* Copy the permanent MAC from the FUNC_QCAPS response */
5005         memcpy(&eth_dev->data->mac_addrs[0], bp->mac_addr, RTE_ETHER_ADDR_LEN);
5006
5007         return rc;
5008 }
5009
5010 static int bnxt_restore_dflt_mac(struct bnxt *bp)
5011 {
5012         int rc = 0;
5013
5014         /* MAC is already configured in FW */
5015         if (BNXT_HAS_DFLT_MAC_SET(bp))
5016                 return 0;
5017
5018         /* Restore the old MAC configured */
5019         rc = bnxt_hwrm_set_mac(bp);
5020         if (rc)
5021                 PMD_DRV_LOG(ERR, "Failed to restore MAC address\n");
5022
5023         return rc;
5024 }
5025
5026 static void bnxt_config_vf_req_fwd(struct bnxt *bp)
5027 {
5028         if (!BNXT_PF(bp))
5029                 return;
5030
5031 #define ALLOW_FUNC(x)   \
5032         { \
5033                 uint32_t arg = (x); \
5034                 bp->pf->vf_req_fwd[((arg) >> 5)] &= \
5035                 ~rte_cpu_to_le_32(1 << ((arg) & 0x1f)); \
5036         }
5037
5038         /* Forward all requests if firmware is new enough */
5039         if (((bp->fw_ver >= ((20 << 24) | (6 << 16) | (100 << 8))) &&
5040              (bp->fw_ver < ((20 << 24) | (7 << 16)))) ||
5041             ((bp->fw_ver >= ((20 << 24) | (8 << 16))))) {
5042                 memset(bp->pf->vf_req_fwd, 0xff, sizeof(bp->pf->vf_req_fwd));
5043         } else {
5044                 PMD_DRV_LOG(WARNING,
5045                             "Firmware too old for VF mailbox functionality\n");
5046                 memset(bp->pf->vf_req_fwd, 0, sizeof(bp->pf->vf_req_fwd));
5047         }
5048
5049         /*
5050          * The following are used for driver cleanup. If we disallow these,
5051          * VF drivers can't clean up cleanly.
5052          */
5053         ALLOW_FUNC(HWRM_FUNC_DRV_UNRGTR);
5054         ALLOW_FUNC(HWRM_VNIC_FREE);
5055         ALLOW_FUNC(HWRM_RING_FREE);
5056         ALLOW_FUNC(HWRM_RING_GRP_FREE);
5057         ALLOW_FUNC(HWRM_VNIC_RSS_COS_LB_CTX_FREE);
5058         ALLOW_FUNC(HWRM_CFA_L2_FILTER_FREE);
5059         ALLOW_FUNC(HWRM_STAT_CTX_FREE);
5060         ALLOW_FUNC(HWRM_PORT_PHY_QCFG);
5061         ALLOW_FUNC(HWRM_VNIC_TPA_CFG);
5062 }
5063
5064 uint16_t
5065 bnxt_get_svif(uint16_t port_id, bool func_svif)
5066 {
5067         struct rte_eth_dev *eth_dev;
5068         struct bnxt *bp;
5069
5070         eth_dev = &rte_eth_devices[port_id];
5071         bp = eth_dev->data->dev_private;
5072
5073         return func_svif ? bp->func_svif : bp->port_svif;
5074 }
5075
5076 uint16_t
5077 bnxt_get_vnic_id(uint16_t port)
5078 {
5079         struct rte_eth_dev *eth_dev;
5080         struct bnxt_vnic_info *vnic;
5081         struct bnxt *bp;
5082
5083         eth_dev = &rte_eth_devices[port];
5084         bp = eth_dev->data->dev_private;
5085
5086         vnic = BNXT_GET_DEFAULT_VNIC(bp);
5087
5088         return vnic->fw_vnic_id;
5089 }
5090
5091 uint16_t
5092 bnxt_get_fw_func_id(uint16_t port)
5093 {
5094         struct rte_eth_dev *eth_dev;
5095         struct bnxt *bp;
5096
5097         eth_dev = &rte_eth_devices[port];
5098         bp = eth_dev->data->dev_private;
5099
5100         return bp->fw_fid;
5101 }
5102
5103 static void bnxt_alloc_error_recovery_info(struct bnxt *bp)
5104 {
5105         struct bnxt_error_recovery_info *info = bp->recovery_info;
5106
5107         if (info) {
5108                 if (!(bp->fw_cap & BNXT_FW_CAP_HCOMM_FW_STATUS))
5109                         memset(info, 0, sizeof(*info));
5110                 return;
5111         }
5112
5113         if (!(bp->fw_cap & BNXT_FW_CAP_ERROR_RECOVERY))
5114                 return;
5115
5116         info = rte_zmalloc("bnxt_hwrm_error_recovery_qcfg",
5117                            sizeof(*info), 0);
5118         if (!info)
5119                 bp->fw_cap &= ~BNXT_FW_CAP_ERROR_RECOVERY;
5120
5121         bp->recovery_info = info;
5122 }
5123
5124 static void bnxt_check_fw_status(struct bnxt *bp)
5125 {
5126         uint32_t fw_status;
5127
5128         if (!(bp->recovery_info &&
5129               (bp->fw_cap & BNXT_FW_CAP_HCOMM_FW_STATUS)))
5130                 return;
5131
5132         fw_status = bnxt_read_fw_status_reg(bp, BNXT_FW_STATUS_REG);
5133         if (fw_status != BNXT_FW_STATUS_HEALTHY)
5134                 PMD_DRV_LOG(ERR, "Firmware not responding, status: %#x\n",
5135                             fw_status);
5136 }
5137
5138 static int bnxt_map_hcomm_fw_status_reg(struct bnxt *bp)
5139 {
5140         struct bnxt_error_recovery_info *info = bp->recovery_info;
5141         uint32_t status_loc;
5142         uint32_t sig_ver;
5143
5144         rte_write32(HCOMM_STATUS_STRUCT_LOC, (uint8_t *)bp->bar0 +
5145                     BNXT_GRCPF_REG_WINDOW_BASE_OUT + 4);
5146         sig_ver = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
5147                                    BNXT_GRCP_WINDOW_2_BASE +
5148                                    offsetof(struct hcomm_status,
5149                                             sig_ver)));
5150         /* If the signature is absent, then FW does not support this feature */
5151         if ((sig_ver & HCOMM_STATUS_SIGNATURE_MASK) !=
5152             HCOMM_STATUS_SIGNATURE_VAL)
5153                 return 0;
5154
5155         if (!info) {
5156                 info = rte_zmalloc("bnxt_hwrm_error_recovery_qcfg",
5157                                    sizeof(*info), 0);
5158                 if (!info)
5159                         return -ENOMEM;
5160                 bp->recovery_info = info;
5161         } else {
5162                 memset(info, 0, sizeof(*info));
5163         }
5164
5165         status_loc = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
5166                                       BNXT_GRCP_WINDOW_2_BASE +
5167                                       offsetof(struct hcomm_status,
5168                                                fw_status_loc)));
5169
5170         /* Only pre-map the FW health status GRC register */
5171         if (BNXT_FW_STATUS_REG_TYPE(status_loc) != BNXT_FW_STATUS_REG_TYPE_GRC)
5172                 return 0;
5173
5174         info->status_regs[BNXT_FW_STATUS_REG] = status_loc;
5175         info->mapped_status_regs[BNXT_FW_STATUS_REG] =
5176                 BNXT_GRCP_WINDOW_2_BASE + (status_loc & BNXT_GRCP_OFFSET_MASK);
5177
5178         rte_write32((status_loc & BNXT_GRCP_BASE_MASK), (uint8_t *)bp->bar0 +
5179                     BNXT_GRCPF_REG_WINDOW_BASE_OUT + 4);
5180
5181         bp->fw_cap |= BNXT_FW_CAP_HCOMM_FW_STATUS;
5182
5183         return 0;
5184 }
5185
5186 static int bnxt_init_fw(struct bnxt *bp)
5187 {
5188         uint16_t mtu;
5189         int rc = 0;
5190
5191         bp->fw_cap = 0;
5192
5193         rc = bnxt_map_hcomm_fw_status_reg(bp);
5194         if (rc)
5195                 return rc;
5196
5197         rc = bnxt_hwrm_ver_get(bp, DFLT_HWRM_CMD_TIMEOUT);
5198         if (rc) {
5199                 bnxt_check_fw_status(bp);
5200                 return rc;
5201         }
5202
5203         rc = bnxt_hwrm_func_reset(bp);
5204         if (rc)
5205                 return -EIO;
5206
5207         rc = bnxt_hwrm_vnic_qcaps(bp);
5208         if (rc)
5209                 return rc;
5210
5211         rc = bnxt_hwrm_queue_qportcfg(bp);
5212         if (rc)
5213                 return rc;
5214
5215         /* Get the MAX capabilities for this function.
5216          * This function also allocates context memory for TQM rings and
5217          * informs the firmware about this allocated backing store memory.
5218          */
5219         rc = bnxt_hwrm_func_qcaps(bp);
5220         if (rc)
5221                 return rc;
5222
5223         rc = bnxt_hwrm_func_qcfg(bp, &mtu);
5224         if (rc)
5225                 return rc;
5226
5227         bnxt_hwrm_port_mac_qcfg(bp);
5228
5229         bnxt_hwrm_parent_pf_qcfg(bp);
5230
5231         rc = bnxt_hwrm_cfa_adv_flow_mgmt_qcaps(bp);
5232         if (rc)
5233                 return rc;
5234
5235         bnxt_alloc_error_recovery_info(bp);
5236         /* Get the adapter error recovery support info */
5237         rc = bnxt_hwrm_error_recovery_qcfg(bp);
5238         if (rc)
5239                 bp->fw_cap &= ~BNXT_FW_CAP_ERROR_RECOVERY;
5240
5241         bnxt_hwrm_port_led_qcaps(bp);
5242
5243         return 0;
5244 }
5245
5246 static int
5247 bnxt_init_locks(struct bnxt *bp)
5248 {
5249         int err;
5250
5251         err = pthread_mutex_init(&bp->flow_lock, NULL);
5252         if (err) {
5253                 PMD_DRV_LOG(ERR, "Unable to initialize flow_lock\n");
5254                 return err;
5255         }
5256
5257         err = pthread_mutex_init(&bp->def_cp_lock, NULL);
5258         if (err)
5259                 PMD_DRV_LOG(ERR, "Unable to initialize def_cp_lock\n");
5260         return err;
5261 }
5262
5263 static int bnxt_init_resources(struct bnxt *bp, bool reconfig_dev)
5264 {
5265         int rc = 0;
5266
5267         rc = bnxt_init_fw(bp);
5268         if (rc)
5269                 return rc;
5270
5271         if (!reconfig_dev) {
5272                 rc = bnxt_setup_mac_addr(bp->eth_dev);
5273                 if (rc)
5274                         return rc;
5275         } else {
5276                 rc = bnxt_restore_dflt_mac(bp);
5277                 if (rc)
5278                         return rc;
5279         }
5280
5281         bnxt_config_vf_req_fwd(bp);
5282
5283         rc = bnxt_hwrm_func_driver_register(bp);
5284         if (rc) {
5285                 PMD_DRV_LOG(ERR, "Failed to register driver");
5286                 return -EBUSY;
5287         }
5288
5289         if (BNXT_PF(bp)) {
5290                 if (bp->pdev->max_vfs) {
5291                         rc = bnxt_hwrm_allocate_vfs(bp, bp->pdev->max_vfs);
5292                         if (rc) {
5293                                 PMD_DRV_LOG(ERR, "Failed to allocate VFs\n");
5294                                 return rc;
5295                         }
5296                 } else {
5297                         rc = bnxt_hwrm_allocate_pf_only(bp);
5298                         if (rc) {
5299                                 PMD_DRV_LOG(ERR,
5300                                             "Failed to allocate PF resources");
5301                                 return rc;
5302                         }
5303                 }
5304         }
5305
5306         rc = bnxt_alloc_mem(bp, reconfig_dev);
5307         if (rc)
5308                 return rc;
5309
5310         rc = bnxt_setup_int(bp);
5311         if (rc)
5312                 return rc;
5313
5314         rc = bnxt_request_int(bp);
5315         if (rc)
5316                 return rc;
5317
5318         rc = bnxt_init_ctx_mem(bp);
5319         if (rc) {
5320                 PMD_DRV_LOG(ERR, "Failed to init adv_flow_counters\n");
5321                 return rc;
5322         }
5323
5324         rc = bnxt_init_locks(bp);
5325         if (rc)
5326                 return rc;
5327
5328         return 0;
5329 }
5330
5331 static int
5332 bnxt_parse_devarg_truflow(__rte_unused const char *key,
5333                           const char *value, void *opaque_arg)
5334 {
5335         struct bnxt *bp = opaque_arg;
5336         unsigned long truflow;
5337         char *end = NULL;
5338
5339         if (!value || !opaque_arg) {
5340                 PMD_DRV_LOG(ERR,
5341                             "Invalid parameter passed to truflow devargs.\n");
5342                 return -EINVAL;
5343         }
5344
5345         truflow = strtoul(value, &end, 10);
5346         if (end == NULL || *end != '\0' ||
5347             (truflow == ULONG_MAX && errno == ERANGE)) {
5348                 PMD_DRV_LOG(ERR,
5349                             "Invalid parameter passed to truflow devargs.\n");
5350                 return -EINVAL;
5351         }
5352
5353         if (BNXT_DEVARG_TRUFLOW_INVALID(truflow)) {
5354                 PMD_DRV_LOG(ERR,
5355                             "Invalid value passed to truflow devargs.\n");
5356                 return -EINVAL;
5357         }
5358
5359         bp->flags |= BNXT_FLAG_TRUFLOW_EN;
5360         if (BNXT_TRUFLOW_EN(bp))
5361                 PMD_DRV_LOG(INFO, "Host-based truflow feature enabled.\n");
5362
5363         return 0;
5364 }
5365
5366 static int
5367 bnxt_parse_devarg_flow_xstat(__rte_unused const char *key,
5368                              const char *value, void *opaque_arg)
5369 {
5370         struct bnxt *bp = opaque_arg;
5371         unsigned long flow_xstat;
5372         char *end = NULL;
5373
5374         if (!value || !opaque_arg) {
5375                 PMD_DRV_LOG(ERR,
5376                             "Invalid parameter passed to flow_xstat devarg.\n");
5377                 return -EINVAL;
5378         }
5379
5380         flow_xstat = strtoul(value, &end, 10);
5381         if (end == NULL || *end != '\0' ||
5382             (flow_xstat == ULONG_MAX && errno == ERANGE)) {
5383                 PMD_DRV_LOG(ERR,
5384                             "Invalid parameter passed to flow_xstat devarg.\n");
5385                 return -EINVAL;
5386         }
5387
5388         if (BNXT_DEVARG_FLOW_XSTAT_INVALID(flow_xstat)) {
5389                 PMD_DRV_LOG(ERR,
5390                             "Invalid value passed to flow_xstat devarg.\n");
5391                 return -EINVAL;
5392         }
5393
5394         bp->flags |= BNXT_FLAG_FLOW_XSTATS_EN;
5395         if (BNXT_FLOW_XSTATS_EN(bp))
5396                 PMD_DRV_LOG(INFO, "flow_xstat feature enabled.\n");
5397
5398         return 0;
5399 }
5400
5401 static int
5402 bnxt_parse_devarg_max_num_kflows(__rte_unused const char *key,
5403                                         const char *value, void *opaque_arg)
5404 {
5405         struct bnxt *bp = opaque_arg;
5406         unsigned long max_num_kflows;
5407         char *end = NULL;
5408
5409         if (!value || !opaque_arg) {
5410                 PMD_DRV_LOG(ERR,
5411                         "Invalid parameter passed to max_num_kflows devarg.\n");
5412                 return -EINVAL;
5413         }
5414
5415         max_num_kflows = strtoul(value, &end, 10);
5416         if (end == NULL || *end != '\0' ||
5417                 (max_num_kflows == ULONG_MAX && errno == ERANGE)) {
5418                 PMD_DRV_LOG(ERR,
5419                         "Invalid parameter passed to max_num_kflows devarg.\n");
5420                 return -EINVAL;
5421         }
5422
5423         if (bnxt_devarg_max_num_kflow_invalid(max_num_kflows)) {
5424                 PMD_DRV_LOG(ERR,
5425                         "Invalid value passed to max_num_kflows devarg.\n");
5426                 return -EINVAL;
5427         }
5428
5429         bp->max_num_kflows = max_num_kflows;
5430         if (bp->max_num_kflows)
5431                 PMD_DRV_LOG(INFO, "max_num_kflows set as %ldK.\n",
5432                                 max_num_kflows);
5433
5434         return 0;
5435 }
5436
5437 static void
5438 bnxt_parse_dev_args(struct bnxt *bp, struct rte_devargs *devargs)
5439 {
5440         struct rte_kvargs *kvlist;
5441
5442         if (devargs == NULL)
5443                 return;
5444
5445         kvlist = rte_kvargs_parse(devargs->args, bnxt_dev_args);
5446         if (kvlist == NULL)
5447                 return;
5448
5449         /*
5450          * Handler for "truflow" devarg.
5451          * Invoked as for ex: "-w 0000:00:0d.0,host-based-truflow=1"
5452          */
5453         rte_kvargs_process(kvlist, BNXT_DEVARG_TRUFLOW,
5454                            bnxt_parse_devarg_truflow, bp);
5455
5456         /*
5457          * Handler for "flow_xstat" devarg.
5458          * Invoked as for ex: "-w 0000:00:0d.0,flow_xstat=1"
5459          */
5460         rte_kvargs_process(kvlist, BNXT_DEVARG_FLOW_XSTAT,
5461                            bnxt_parse_devarg_flow_xstat, bp);
5462
5463         /*
5464          * Handler for "max_num_kflows" devarg.
5465          * Invoked as for ex: "-w 000:00:0d.0,max_num_kflows=32"
5466          */
5467         rte_kvargs_process(kvlist, BNXT_DEVARG_MAX_NUM_KFLOWS,
5468                            bnxt_parse_devarg_max_num_kflows, bp);
5469
5470         rte_kvargs_free(kvlist);
5471 }
5472
5473 static int bnxt_alloc_switch_domain(struct bnxt *bp)
5474 {
5475         int rc = 0;
5476
5477         if (BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp)) {
5478                 rc = rte_eth_switch_domain_alloc(&bp->switch_domain_id);
5479                 if (rc)
5480                         PMD_DRV_LOG(ERR,
5481                                     "Failed to alloc switch domain: %d\n", rc);
5482                 else
5483                         PMD_DRV_LOG(INFO,
5484                                     "Switch domain allocated %d\n",
5485                                     bp->switch_domain_id);
5486         }
5487
5488         return rc;
5489 }
5490
5491 static int
5492 bnxt_dev_init(struct rte_eth_dev *eth_dev, void *params __rte_unused)
5493 {
5494         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
5495         static int version_printed;
5496         struct bnxt *bp;
5497         int rc;
5498
5499         if (version_printed++ == 0)
5500                 PMD_DRV_LOG(INFO, "%s\n", bnxt_version);
5501
5502         eth_dev->dev_ops = &bnxt_dev_ops;
5503         eth_dev->rx_pkt_burst = &bnxt_recv_pkts;
5504         eth_dev->tx_pkt_burst = &bnxt_xmit_pkts;
5505
5506         /*
5507          * For secondary processes, we don't initialise any further
5508          * as primary has already done this work.
5509          */
5510         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
5511                 return 0;
5512
5513         rte_eth_copy_pci_info(eth_dev, pci_dev);
5514
5515         bp = eth_dev->data->dev_private;
5516
5517         /* Parse dev arguments passed on when starting the DPDK application. */
5518         bnxt_parse_dev_args(bp, pci_dev->device.devargs);
5519
5520         bp->flags &= ~BNXT_FLAG_RX_VECTOR_PKT_MODE;
5521
5522         if (bnxt_vf_pciid(pci_dev->id.device_id))
5523                 bp->flags |= BNXT_FLAG_VF;
5524
5525         if (bnxt_thor_device(pci_dev->id.device_id))
5526                 bp->flags |= BNXT_FLAG_THOR_CHIP;
5527
5528         if (pci_dev->id.device_id == BROADCOM_DEV_ID_58802 ||
5529             pci_dev->id.device_id == BROADCOM_DEV_ID_58804 ||
5530             pci_dev->id.device_id == BROADCOM_DEV_ID_58808 ||
5531             pci_dev->id.device_id == BROADCOM_DEV_ID_58802_VF)
5532                 bp->flags |= BNXT_FLAG_STINGRAY;
5533
5534         rc = bnxt_init_board(eth_dev);
5535         if (rc) {
5536                 PMD_DRV_LOG(ERR,
5537                             "Failed to initialize board rc: %x\n", rc);
5538                 return rc;
5539         }
5540
5541         rc = bnxt_alloc_pf_info(bp);
5542         if (rc)
5543                 goto error_free;
5544
5545         rc = bnxt_alloc_link_info(bp);
5546         if (rc)
5547                 goto error_free;
5548
5549         rc = bnxt_alloc_parent_info(bp);
5550         if (rc)
5551                 goto error_free;
5552
5553         rc = bnxt_alloc_hwrm_resources(bp);
5554         if (rc) {
5555                 PMD_DRV_LOG(ERR,
5556                             "Failed to allocate hwrm resource rc: %x\n", rc);
5557                 goto error_free;
5558         }
5559         rc = bnxt_alloc_leds_info(bp);
5560         if (rc)
5561                 goto error_free;
5562
5563         rc = bnxt_alloc_cos_queues(bp);
5564         if (rc)
5565                 goto error_free;
5566
5567         rc = bnxt_init_resources(bp, false);
5568         if (rc)
5569                 goto error_free;
5570
5571         rc = bnxt_alloc_stats_mem(bp);
5572         if (rc)
5573                 goto error_free;
5574
5575         bnxt_alloc_switch_domain(bp);
5576
5577         /* Pass the information to the rte_eth_dev_close() that it should also
5578          * release the private port resources.
5579          */
5580         eth_dev->data->dev_flags |= RTE_ETH_DEV_CLOSE_REMOVE;
5581
5582         PMD_DRV_LOG(INFO,
5583                     DRV_MODULE_NAME "found at mem %" PRIX64 ", node addr %pM\n",
5584                     pci_dev->mem_resource[0].phys_addr,
5585                     pci_dev->mem_resource[0].addr);
5586
5587         return 0;
5588
5589 error_free:
5590         bnxt_dev_uninit(eth_dev);
5591         return rc;
5592 }
5593
5594
5595 static void bnxt_free_ctx_mem_buf(struct bnxt_ctx_mem_buf_info *ctx)
5596 {
5597         if (!ctx)
5598                 return;
5599
5600         if (ctx->va)
5601                 rte_free(ctx->va);
5602
5603         ctx->va = NULL;
5604         ctx->dma = RTE_BAD_IOVA;
5605         ctx->ctx_id = BNXT_CTX_VAL_INVAL;
5606 }
5607
5608 static void bnxt_unregister_fc_ctx_mem(struct bnxt *bp)
5609 {
5610         bnxt_hwrm_cfa_counter_cfg(bp, BNXT_DIR_RX,
5611                                   CFA_COUNTER_CFG_IN_COUNTER_TYPE_FC,
5612                                   bp->flow_stat->rx_fc_out_tbl.ctx_id,
5613                                   bp->flow_stat->max_fc,
5614                                   false);
5615
5616         bnxt_hwrm_cfa_counter_cfg(bp, BNXT_DIR_TX,
5617                                   CFA_COUNTER_CFG_IN_COUNTER_TYPE_FC,
5618                                   bp->flow_stat->tx_fc_out_tbl.ctx_id,
5619                                   bp->flow_stat->max_fc,
5620                                   false);
5621
5622         if (bp->flow_stat->rx_fc_in_tbl.ctx_id != BNXT_CTX_VAL_INVAL)
5623                 bnxt_hwrm_ctx_unrgtr(bp, bp->flow_stat->rx_fc_in_tbl.ctx_id);
5624         bp->flow_stat->rx_fc_in_tbl.ctx_id = BNXT_CTX_VAL_INVAL;
5625
5626         if (bp->flow_stat->rx_fc_out_tbl.ctx_id != BNXT_CTX_VAL_INVAL)
5627                 bnxt_hwrm_ctx_unrgtr(bp, bp->flow_stat->rx_fc_out_tbl.ctx_id);
5628         bp->flow_stat->rx_fc_out_tbl.ctx_id = BNXT_CTX_VAL_INVAL;
5629
5630         if (bp->flow_stat->tx_fc_in_tbl.ctx_id != BNXT_CTX_VAL_INVAL)
5631                 bnxt_hwrm_ctx_unrgtr(bp, bp->flow_stat->tx_fc_in_tbl.ctx_id);
5632         bp->flow_stat->tx_fc_in_tbl.ctx_id = BNXT_CTX_VAL_INVAL;
5633
5634         if (bp->flow_stat->tx_fc_out_tbl.ctx_id != BNXT_CTX_VAL_INVAL)
5635                 bnxt_hwrm_ctx_unrgtr(bp, bp->flow_stat->tx_fc_out_tbl.ctx_id);
5636         bp->flow_stat->tx_fc_out_tbl.ctx_id = BNXT_CTX_VAL_INVAL;
5637 }
5638
5639 static void bnxt_uninit_fc_ctx_mem(struct bnxt *bp)
5640 {
5641         bnxt_unregister_fc_ctx_mem(bp);
5642
5643         bnxt_free_ctx_mem_buf(&bp->flow_stat->rx_fc_in_tbl);
5644         bnxt_free_ctx_mem_buf(&bp->flow_stat->rx_fc_out_tbl);
5645         bnxt_free_ctx_mem_buf(&bp->flow_stat->tx_fc_in_tbl);
5646         bnxt_free_ctx_mem_buf(&bp->flow_stat->tx_fc_out_tbl);
5647 }
5648
5649 static void bnxt_uninit_ctx_mem(struct bnxt *bp)
5650 {
5651         if (BNXT_FLOW_XSTATS_EN(bp))
5652                 bnxt_uninit_fc_ctx_mem(bp);
5653 }
5654
5655 static void
5656 bnxt_free_error_recovery_info(struct bnxt *bp)
5657 {
5658         rte_free(bp->recovery_info);
5659         bp->recovery_info = NULL;
5660         bp->fw_cap &= ~BNXT_FW_CAP_ERROR_RECOVERY;
5661 }
5662
5663 static void
5664 bnxt_uninit_locks(struct bnxt *bp)
5665 {
5666         pthread_mutex_destroy(&bp->flow_lock);
5667         pthread_mutex_destroy(&bp->def_cp_lock);
5668         if (bp->rep_info)
5669                 pthread_mutex_destroy(&bp->rep_info->vfr_lock);
5670 }
5671
5672 static int
5673 bnxt_uninit_resources(struct bnxt *bp, bool reconfig_dev)
5674 {
5675         int rc;
5676
5677         bnxt_free_int(bp);
5678         bnxt_free_mem(bp, reconfig_dev);
5679         bnxt_hwrm_func_buf_unrgtr(bp);
5680         rc = bnxt_hwrm_func_driver_unregister(bp, 0);
5681         bp->flags &= ~BNXT_FLAG_REGISTERED;
5682         bnxt_free_ctx_mem(bp);
5683         if (!reconfig_dev) {
5684                 bnxt_free_hwrm_resources(bp);
5685                 bnxt_free_error_recovery_info(bp);
5686         }
5687
5688         bnxt_uninit_ctx_mem(bp);
5689
5690         bnxt_uninit_locks(bp);
5691         bnxt_free_flow_stats_info(bp);
5692         bnxt_free_rep_info(bp);
5693         rte_free(bp->ptp_cfg);
5694         bp->ptp_cfg = NULL;
5695         return rc;
5696 }
5697
5698 static int
5699 bnxt_dev_uninit(struct rte_eth_dev *eth_dev)
5700 {
5701         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
5702                 return -EPERM;
5703
5704         PMD_DRV_LOG(DEBUG, "Calling Device uninit\n");
5705
5706         if (eth_dev->state != RTE_ETH_DEV_UNUSED)
5707                 bnxt_dev_close_op(eth_dev);
5708
5709         return 0;
5710 }
5711
5712 static int bnxt_pci_remove_dev_with_reps(struct rte_eth_dev *eth_dev)
5713 {
5714         struct bnxt *bp = eth_dev->data->dev_private;
5715         struct rte_eth_dev *vf_rep_eth_dev;
5716         int ret = 0, i;
5717
5718         if (!bp)
5719                 return -EINVAL;
5720
5721         for (i = 0; i < bp->num_reps; i++) {
5722                 vf_rep_eth_dev = bp->rep_info[i].vfr_eth_dev;
5723                 if (!vf_rep_eth_dev)
5724                         continue;
5725                 rte_eth_dev_destroy(vf_rep_eth_dev, bnxt_vf_representor_uninit);
5726         }
5727         ret = rte_eth_dev_destroy(eth_dev, bnxt_dev_uninit);
5728
5729         return ret;
5730 }
5731
5732 static void bnxt_free_rep_info(struct bnxt *bp)
5733 {
5734         rte_free(bp->rep_info);
5735         bp->rep_info = NULL;
5736         rte_free(bp->cfa_code_map);
5737         bp->cfa_code_map = NULL;
5738 }
5739
5740 static int bnxt_init_rep_info(struct bnxt *bp)
5741 {
5742         int i = 0, rc;
5743
5744         if (bp->rep_info)
5745                 return 0;
5746
5747         bp->rep_info = rte_zmalloc("bnxt_rep_info",
5748                                    sizeof(bp->rep_info[0]) * BNXT_MAX_VF_REPS,
5749                                    0);
5750         if (!bp->rep_info) {
5751                 PMD_DRV_LOG(ERR, "Failed to alloc memory for rep info\n");
5752                 return -ENOMEM;
5753         }
5754         bp->cfa_code_map = rte_zmalloc("bnxt_cfa_code_map",
5755                                        sizeof(*bp->cfa_code_map) *
5756                                        BNXT_MAX_CFA_CODE, 0);
5757         if (!bp->cfa_code_map) {
5758                 PMD_DRV_LOG(ERR, "Failed to alloc memory for cfa_code_map\n");
5759                 bnxt_free_rep_info(bp);
5760                 return -ENOMEM;
5761         }
5762
5763         for (i = 0; i < BNXT_MAX_CFA_CODE; i++)
5764                 bp->cfa_code_map[i] = BNXT_VF_IDX_INVALID;
5765
5766         rc = pthread_mutex_init(&bp->rep_info->vfr_lock, NULL);
5767         if (rc) {
5768                 PMD_DRV_LOG(ERR, "Unable to initialize vfr_lock\n");
5769                 bnxt_free_rep_info(bp);
5770                 return rc;
5771         }
5772         return rc;
5773 }
5774
5775 static int bnxt_rep_port_probe(struct rte_pci_device *pci_dev,
5776                                struct rte_eth_devargs eth_da,
5777                                struct rte_eth_dev *backing_eth_dev)
5778 {
5779         struct rte_eth_dev *vf_rep_eth_dev;
5780         char name[RTE_ETH_NAME_MAX_LEN];
5781         struct bnxt *backing_bp;
5782         uint16_t num_rep;
5783         int i, ret = 0;
5784
5785         num_rep = eth_da.nb_representor_ports;
5786         if (num_rep > BNXT_MAX_VF_REPS) {
5787                 PMD_DRV_LOG(ERR, "nb_representor_ports = %d > %d MAX VF REPS\n",
5788                             num_rep, BNXT_MAX_VF_REPS);
5789                 return -EINVAL;
5790         }
5791
5792         if (num_rep > RTE_MAX_ETHPORTS) {
5793                 PMD_DRV_LOG(ERR,
5794                             "nb_representor_ports = %d > %d MAX ETHPORTS\n",
5795                             num_rep, RTE_MAX_ETHPORTS);
5796                 return -EINVAL;
5797         }
5798
5799         backing_bp = backing_eth_dev->data->dev_private;
5800
5801         if (!(BNXT_PF(backing_bp) || BNXT_VF_IS_TRUSTED(backing_bp))) {
5802                 PMD_DRV_LOG(ERR,
5803                             "Not a PF or trusted VF. No Representor support\n");
5804                 /* Returning an error is not an option.
5805                  * Applications are not handling this correctly
5806                  */
5807                 return 0;
5808         }
5809
5810         if (bnxt_init_rep_info(backing_bp))
5811                 return 0;
5812
5813         for (i = 0; i < num_rep; i++) {
5814                 struct bnxt_vf_representor representor = {
5815                         .vf_id = eth_da.representor_ports[i],
5816                         .switch_domain_id = backing_bp->switch_domain_id,
5817                         .parent_dev = backing_eth_dev
5818                 };
5819
5820                 if (representor.vf_id >= BNXT_MAX_VF_REPS) {
5821                         PMD_DRV_LOG(ERR, "VF-Rep id %d >= %d MAX VF ID\n",
5822                                     representor.vf_id, BNXT_MAX_VF_REPS);
5823                         continue;
5824                 }
5825
5826                 /* representor port net_bdf_port */
5827                 snprintf(name, sizeof(name), "net_%s_representor_%d",
5828                          pci_dev->device.name, eth_da.representor_ports[i]);
5829
5830                 ret = rte_eth_dev_create(&pci_dev->device, name,
5831                                          sizeof(struct bnxt_vf_representor),
5832                                          NULL, NULL,
5833                                          bnxt_vf_representor_init,
5834                                          &representor);
5835
5836                 if (!ret) {
5837                         vf_rep_eth_dev = rte_eth_dev_allocated(name);
5838                         if (!vf_rep_eth_dev) {
5839                                 PMD_DRV_LOG(ERR, "Failed to find the eth_dev"
5840                                             " for VF-Rep: %s.", name);
5841                                 bnxt_pci_remove_dev_with_reps(backing_eth_dev);
5842                                 ret = -ENODEV;
5843                                 return ret;
5844                         }
5845                         backing_bp->rep_info[representor.vf_id].vfr_eth_dev =
5846                                 vf_rep_eth_dev;
5847                         backing_bp->num_reps++;
5848                 } else {
5849                         PMD_DRV_LOG(ERR, "failed to create bnxt vf "
5850                                     "representor %s.", name);
5851                         bnxt_pci_remove_dev_with_reps(backing_eth_dev);
5852                 }
5853         }
5854
5855         return ret;
5856 }
5857
5858 static int bnxt_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
5859                           struct rte_pci_device *pci_dev)
5860 {
5861         struct rte_eth_devargs eth_da = { .nb_representor_ports = 0 };
5862         struct rte_eth_dev *backing_eth_dev;
5863         uint16_t num_rep;
5864         int ret = 0;
5865
5866         if (pci_dev->device.devargs) {
5867                 ret = rte_eth_devargs_parse(pci_dev->device.devargs->args,
5868                                             &eth_da);
5869                 if (ret)
5870                         return ret;
5871         }
5872
5873         num_rep = eth_da.nb_representor_ports;
5874         PMD_DRV_LOG(DEBUG, "nb_representor_ports = %d\n",
5875                     num_rep);
5876
5877         /* We could come here after first level of probe is already invoked
5878          * as part of an application bringup(OVS-DPDK vswitchd), so first check
5879          * for already allocated eth_dev for the backing device (PF/Trusted VF)
5880          */
5881         backing_eth_dev = rte_eth_dev_allocated(pci_dev->device.name);
5882         if (backing_eth_dev == NULL) {
5883                 ret = rte_eth_dev_create(&pci_dev->device, pci_dev->device.name,
5884                                          sizeof(struct bnxt),
5885                                          eth_dev_pci_specific_init, pci_dev,
5886                                          bnxt_dev_init, NULL);
5887
5888                 if (ret || !num_rep)
5889                         return ret;
5890
5891                 backing_eth_dev = rte_eth_dev_allocated(pci_dev->device.name);
5892         }
5893
5894         /* probe representor ports now */
5895         ret = bnxt_rep_port_probe(pci_dev, eth_da, backing_eth_dev);
5896
5897         return ret;
5898 }
5899
5900 static int bnxt_pci_remove(struct rte_pci_device *pci_dev)
5901 {
5902         struct rte_eth_dev *eth_dev;
5903
5904         eth_dev = rte_eth_dev_allocated(pci_dev->device.name);
5905         if (!eth_dev)
5906                 return 0; /* Invoked typically only by OVS-DPDK, by the
5907                            * time it comes here the eth_dev is already
5908                            * deleted by rte_eth_dev_close(), so returning
5909                            * +ve value will at least help in proper cleanup
5910                            */
5911
5912         if (rte_eal_process_type() == RTE_PROC_PRIMARY) {
5913                 if (eth_dev->data->dev_flags & RTE_ETH_DEV_REPRESENTOR)
5914                         return rte_eth_dev_destroy(eth_dev,
5915                                                    bnxt_vf_representor_uninit);
5916                 else
5917                         return rte_eth_dev_destroy(eth_dev,
5918                                                    bnxt_dev_uninit);
5919         } else {
5920                 return rte_eth_dev_pci_generic_remove(pci_dev, NULL);
5921         }
5922 }
5923
5924 static struct rte_pci_driver bnxt_rte_pmd = {
5925         .id_table = bnxt_pci_id_map,
5926         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC |
5927                         RTE_PCI_DRV_PROBE_AGAIN, /* Needed in case of VF-REPs
5928                                                   * and OVS-DPDK
5929                                                   */
5930         .probe = bnxt_pci_probe,
5931         .remove = bnxt_pci_remove,
5932 };
5933
5934 static bool
5935 is_device_supported(struct rte_eth_dev *dev, struct rte_pci_driver *drv)
5936 {
5937         if (strcmp(dev->device->driver->name, drv->driver.name))
5938                 return false;
5939
5940         return true;
5941 }
5942
5943 bool is_bnxt_supported(struct rte_eth_dev *dev)
5944 {
5945         return is_device_supported(dev, &bnxt_rte_pmd);
5946 }
5947
5948 RTE_LOG_REGISTER(bnxt_logtype_driver, pmd.net.bnxt.driver, NOTICE);
5949 RTE_PMD_REGISTER_PCI(net_bnxt, bnxt_rte_pmd);
5950 RTE_PMD_REGISTER_PCI_TABLE(net_bnxt, bnxt_pci_id_map);
5951 RTE_PMD_REGISTER_KMOD_DEP(net_bnxt, "* igb_uio | uio_pci_generic | vfio-pci");