drivers/net/bnxt/bnxt_ethdev.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2014-2018 Broadcom
   3  * All rights reserved.
   4  */
   5
   6 #include <inttypes.h>
   7 #include <stdbool.h>
   8
   9 #include <rte_dev.h>
  10 #include <rte_ethdev_driver.h>
  11 #include <rte_ethdev_pci.h>
  12 #include <rte_malloc.h>
  13 #include <rte_cycles.h>
  14 #include <rte_alarm.h>
  15 #include <rte_kvargs.h>
  16
  17 #include "bnxt.h"
  18 #include "bnxt_filter.h"
  19 #include "bnxt_hwrm.h"
  20 #include "bnxt_irq.h"
  21 #include "bnxt_reps.h"
  22 #include "bnxt_ring.h"
  23 #include "bnxt_rxq.h"
  24 #include "bnxt_rxr.h"
  25 #include "bnxt_stats.h"
  26 #include "bnxt_txq.h"
  27 #include "bnxt_txr.h"
  28 #include "bnxt_vnic.h"
  29 #include "hsi_struct_def_dpdk.h"
  30 #include "bnxt_nvm_defs.h"
  31 #include "bnxt_tf_common.h"
  32 #include "ulp_flow_db.h"
  33
  34 #define DRV_MODULE_NAME         "bnxt"
  35 static const char bnxt_version[] =
  36         "Broadcom NetXtreme driver " DRV_MODULE_NAME;
  37
  38 /*
  39  * The set of PCI devices this driver supports
  40  */
  41 static const struct rte_pci_id bnxt_pci_id_map[] = {
  42         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM,
  43                          BROADCOM_DEV_ID_STRATUS_NIC_VF1) },
  44         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM,
  45                          BROADCOM_DEV_ID_STRATUS_NIC_VF2) },
  46         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_STRATUS_NIC) },
  47         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414_VF) },
  48         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57301) },
  49         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57302) },
  50         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57304_PF) },
  51         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57304_VF) },
  52         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_NS2) },
  53         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57402) },
  54         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57404) },
  55         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57406_PF) },
  56         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57406_VF) },
  57         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57402_MF) },
  58         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57407_RJ45) },
  59         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57404_MF) },
  60         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57406_MF) },
  61         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57407_SFP) },
  62         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57407_MF) },
  63         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_5741X_VF) },
  64         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_5731X_VF) },
  65         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57314) },
  66         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_MF) },
  67         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57311) },
  68         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57312) },
  69         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57412) },
  70         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414) },
  71         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_RJ45) },
  72         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_RJ45) },
  73         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57412_MF) },
  74         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57317_RJ45) },
  75         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_SFP) },
  76         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_SFP) },
  77         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57317_SFP) },
  78         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414_MF) },
  79         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_MF) },
  80         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58802) },
  81         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58804) },
  82         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58808) },
  83         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58802_VF) },
  84         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57508) },
  85         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57504) },
  86         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57502) },
  87         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57500_VF1) },
  88         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57500_VF2) },
  89         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57508_MF1) },
  90         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57504_MF1) },
  91         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57502_MF1) },
  92         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57508_MF2) },
  93         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57504_MF2) },
  94         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57502_MF2) },
  95         { .vendor_id = 0, /* sentinel */ },
  96 };
  97
  98 #define BNXT_DEVARG_TRUFLOW     "host-based-truflow"
  99 #define BNXT_DEVARG_FLOW_XSTAT  "flow-xstat"
 100 #define BNXT_DEVARG_MAX_NUM_KFLOWS  "max-num-kflows"
 101 #define BNXT_DEVARG_REPRESENTOR "representor"
 102
 103 static const char *const bnxt_dev_args[] = {
 104         BNXT_DEVARG_REPRESENTOR,
 105         BNXT_DEVARG_TRUFLOW,
 106         BNXT_DEVARG_FLOW_XSTAT,
 107         BNXT_DEVARG_MAX_NUM_KFLOWS,
 108         NULL
 109 };
 110
 111 /*
 112  * truflow == false to disable the feature
 113  * truflow == true to enable the feature
 114  */
 115 #define BNXT_DEVARG_TRUFLOW_INVALID(truflow)    ((truflow) > 1)
 116
 117 /*
 118  * flow_xstat == false to disable the feature
 119  * flow_xstat == true to enable the feature
 120  */
 121 #define BNXT_DEVARG_FLOW_XSTAT_INVALID(flow_xstat)      ((flow_xstat) > 1)
 122
 123 /*
 124  * max_num_kflows must be >= 32
 125  * and must be a power-of-2 supported value
 126  * return: 1 -> invalid
 127  *         0 -> valid
 128  */
 129 static int bnxt_devarg_max_num_kflow_invalid(uint16_t max_num_kflows)
 130 {
 131         if (max_num_kflows < 32 || !rte_is_power_of_2(max_num_kflows))
 132                 return 1;
 133         return 0;
 134 }
 135
 136 static int bnxt_vlan_offload_set_op(struct rte_eth_dev *dev, int mask);
 137 static int bnxt_dev_uninit(struct rte_eth_dev *eth_dev);
 138 static int bnxt_init_resources(struct bnxt *bp, bool reconfig_dev);
 139 static int bnxt_uninit_resources(struct bnxt *bp, bool reconfig_dev);
 140 static void bnxt_cancel_fw_health_check(struct bnxt *bp);
 141 static int bnxt_restore_vlan_filters(struct bnxt *bp);
 142 static void bnxt_dev_recover(void *arg);
 143 static void bnxt_free_error_recovery_info(struct bnxt *bp);
 144 static void bnxt_free_rep_info(struct bnxt *bp);
 145
 146 int is_bnxt_in_error(struct bnxt *bp)
 147 {
 148         if (bp->flags & BNXT_FLAG_FATAL_ERROR)
 149                 return -EIO;
 150         if (bp->flags & BNXT_FLAG_FW_RESET)
 151                 return -EBUSY;
 152
 153         return 0;
 154 }
 155
 156 /***********************/
 157
 158 /*
 159  * High level utility functions
 160  */
 161
 162 static uint16_t bnxt_rss_ctxts(const struct bnxt *bp)
 163 {
 164         if (!BNXT_CHIP_THOR(bp))
 165                 return 1;
 166
 167         return RTE_ALIGN_MUL_CEIL(bp->rx_nr_rings,
 168                                   BNXT_RSS_ENTRIES_PER_CTX_THOR) /
 169                                     BNXT_RSS_ENTRIES_PER_CTX_THOR;
 170 }
 171
 172 uint16_t bnxt_rss_hash_tbl_size(const struct bnxt *bp)
 173 {
 174         if (!BNXT_CHIP_THOR(bp))
 175                 return HW_HASH_INDEX_SIZE;
 176
 177         return bnxt_rss_ctxts(bp) * BNXT_RSS_ENTRIES_PER_CTX_THOR;
 178 }
 179
 180 static void bnxt_free_parent_info(struct bnxt *bp)
 181 {
 182         rte_free(bp->parent);
 183 }
 184
 185 static void bnxt_free_pf_info(struct bnxt *bp)
 186 {
 187         rte_free(bp->pf);
 188 }
 189
 190 static void bnxt_free_link_info(struct bnxt *bp)
 191 {
 192         rte_free(bp->link_info);
 193 }
 194
 195 static void bnxt_free_leds_info(struct bnxt *bp)
 196 {
 197         if (BNXT_VF(bp))
 198                 return;
 199
 200         rte_free(bp->leds);
 201         bp->leds = NULL;
 202 }
 203
 204 static void bnxt_free_flow_stats_info(struct bnxt *bp)
 205 {
 206         rte_free(bp->flow_stat);
 207         bp->flow_stat = NULL;
 208 }
 209
 210 static void bnxt_free_cos_queues(struct bnxt *bp)
 211 {
 212         rte_free(bp->rx_cos_queue);
 213         rte_free(bp->tx_cos_queue);
 214 }
 215
 216 static void bnxt_free_mem(struct bnxt *bp, bool reconfig)
 217 {
 218         bnxt_free_filter_mem(bp);
 219         bnxt_free_vnic_attributes(bp);
 220         bnxt_free_vnic_mem(bp);
 221
 222         /* tx/rx rings are configured as part of *_queue_setup callbacks.
 223          * If the number of rings change across fw update,
 224          * we don't have much choice except to warn the user.
 225          */
 226         if (!reconfig) {
 227                 bnxt_free_stats(bp);
 228                 bnxt_free_tx_rings(bp);
 229                 bnxt_free_rx_rings(bp);
 230         }
 231         bnxt_free_async_cp_ring(bp);
 232         bnxt_free_rxtx_nq_ring(bp);
 233
 234         rte_free(bp->grp_info);
 235         bp->grp_info = NULL;
 236 }
 237
 238 static int bnxt_alloc_parent_info(struct bnxt *bp)
 239 {
 240         bp->parent = rte_zmalloc("bnxt_parent_info",
 241                                  sizeof(struct bnxt_parent_info), 0);
 242         if (bp->parent == NULL)
 243                 return -ENOMEM;
 244
 245         return 0;
 246 }
 247
 248 static int bnxt_alloc_pf_info(struct bnxt *bp)
 249 {
 250         bp->pf = rte_zmalloc("bnxt_pf_info", sizeof(struct bnxt_pf_info), 0);
 251         if (bp->pf == NULL)
 252                 return -ENOMEM;
 253
 254         return 0;
 255 }
 256
 257 static int bnxt_alloc_link_info(struct bnxt *bp)
 258 {
 259         bp->link_info =
 260                 rte_zmalloc("bnxt_link_info", sizeof(struct bnxt_link_info), 0);
 261         if (bp->link_info == NULL)
 262                 return -ENOMEM;
 263
 264         return 0;
 265 }
 266
 267 static int bnxt_alloc_leds_info(struct bnxt *bp)
 268 {
 269         if (BNXT_VF(bp))
 270                 return 0;
 271
 272         bp->leds = rte_zmalloc("bnxt_leds",
 273                                BNXT_MAX_LED * sizeof(struct bnxt_led_info),
 274                                0);
 275         if (bp->leds == NULL)
 276                 return -ENOMEM;
 277
 278         return 0;
 279 }
 280
 281 static int bnxt_alloc_cos_queues(struct bnxt *bp)
 282 {
 283         bp->rx_cos_queue =
 284                 rte_zmalloc("bnxt_rx_cosq",
 285                             BNXT_COS_QUEUE_COUNT *
 286                             sizeof(struct bnxt_cos_queue_info),
 287                             0);
 288         if (bp->rx_cos_queue == NULL)
 289                 return -ENOMEM;
 290
 291         bp->tx_cos_queue =
 292                 rte_zmalloc("bnxt_tx_cosq",
 293                             BNXT_COS_QUEUE_COUNT *
 294                             sizeof(struct bnxt_cos_queue_info),
 295                             0);
 296         if (bp->tx_cos_queue == NULL)
 297                 return -ENOMEM;
 298
 299         return 0;
 300 }
 301
 302 static int bnxt_alloc_flow_stats_info(struct bnxt *bp)
 303 {
 304         bp->flow_stat = rte_zmalloc("bnxt_flow_xstat",
 305                                     sizeof(struct bnxt_flow_stat_info), 0);
 306         if (bp->flow_stat == NULL)
 307                 return -ENOMEM;
 308
 309         return 0;
 310 }
 311
 312 static int bnxt_alloc_mem(struct bnxt *bp, bool reconfig)
 313 {
 314         int rc;
 315
 316         rc = bnxt_alloc_ring_grps(bp);
 317         if (rc)
 318                 goto alloc_mem_err;
 319
 320         rc = bnxt_alloc_async_ring_struct(bp);
 321         if (rc)
 322                 goto alloc_mem_err;
 323
 324         rc = bnxt_alloc_vnic_mem(bp);
 325         if (rc)
 326                 goto alloc_mem_err;
 327
 328         rc = bnxt_alloc_vnic_attributes(bp);
 329         if (rc)
 330                 goto alloc_mem_err;
 331
 332         rc = bnxt_alloc_filter_mem(bp);
 333         if (rc)
 334                 goto alloc_mem_err;
 335
 336         rc = bnxt_alloc_async_cp_ring(bp);
 337         if (rc)
 338                 goto alloc_mem_err;
 339
 340         rc = bnxt_alloc_rxtx_nq_ring(bp);
 341         if (rc)
 342                 goto alloc_mem_err;
 343
 344         if (BNXT_FLOW_XSTATS_EN(bp)) {
 345                 rc = bnxt_alloc_flow_stats_info(bp);
 346                 if (rc)
 347                         goto alloc_mem_err;
 348         }
 349
 350         return 0;
 351
 352 alloc_mem_err:
 353         bnxt_free_mem(bp, reconfig);
 354         return rc;
 355 }
 356
 357 static int bnxt_setup_one_vnic(struct bnxt *bp, uint16_t vnic_id)
 358 {
 359         struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
 360         struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id];
 361         uint64_t rx_offloads = dev_conf->rxmode.offloads;
 362         struct bnxt_rx_queue *rxq;
 363         unsigned int j;
 364         int rc;
 365
 366         rc = bnxt_vnic_grp_alloc(bp, vnic);
 367         if (rc)
 368                 goto err_out;
 369
 370         PMD_DRV_LOG(DEBUG, "vnic[%d] = %p vnic->fw_grp_ids = %p\n",
 371                     vnic_id, vnic, vnic->fw_grp_ids);
 372
 373         rc = bnxt_hwrm_vnic_alloc(bp, vnic);
 374         if (rc)
 375                 goto err_out;
 376
 377         /* Alloc RSS context only if RSS mode is enabled */
 378         if (dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS) {
 379                 int j, nr_ctxs = bnxt_rss_ctxts(bp);
 380
 381                 rc = 0;
 382                 for (j = 0; j < nr_ctxs; j++) {
 383                         rc = bnxt_hwrm_vnic_ctx_alloc(bp, vnic, j);
 384                         if (rc)
 385                                 break;
 386                 }
 387                 if (rc) {
 388                         PMD_DRV_LOG(ERR,
 389                                     "HWRM vnic %d ctx %d alloc failure rc: %x\n",
 390                                     vnic_id, j, rc);
 391                         goto err_out;
 392                 }
 393                 vnic->num_lb_ctxts = nr_ctxs;
 394         }
 395
 396         /*
 397          * Firmware sets pf pair in default vnic cfg. If the VLAN strip
 398          * setting is not available at this time, it will not be
 399          * configured correctly in the CFA.
 400          */
 401         if (rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
 402                 vnic->vlan_strip = true;
 403         else
 404                 vnic->vlan_strip = false;
 405
 406         rc = bnxt_hwrm_vnic_cfg(bp, vnic);
 407         if (rc)
 408                 goto err_out;
 409
 410         rc = bnxt_set_hwrm_vnic_filters(bp, vnic);
 411         if (rc)
 412                 goto err_out;
 413
 414         for (j = 0; j < bp->rx_num_qs_per_vnic; j++) {
 415                 rxq = bp->eth_dev->data->rx_queues[j];
 416
 417                 PMD_DRV_LOG(DEBUG,
 418                             "rxq[%d]->vnic=%p vnic->fw_grp_ids=%p\n",
 419                             j, rxq->vnic, rxq->vnic->fw_grp_ids);
 420
 421                 if (BNXT_HAS_RING_GRPS(bp) && rxq->rx_deferred_start)
 422                         rxq->vnic->fw_grp_ids[j] = INVALID_HW_RING_ID;
 423                 else
 424                         vnic->rx_queue_cnt++;
 425         }
 426
 427         PMD_DRV_LOG(DEBUG, "vnic->rx_queue_cnt = %d\n", vnic->rx_queue_cnt);
 428
 429         rc = bnxt_vnic_rss_configure(bp, vnic);
 430         if (rc)
 431                 goto err_out;
 432
 433         bnxt_hwrm_vnic_plcmode_cfg(bp, vnic);
 434
 435         if (rx_offloads & DEV_RX_OFFLOAD_TCP_LRO)
 436                 bnxt_hwrm_vnic_tpa_cfg(bp, vnic, 1);
 437         else
 438                 bnxt_hwrm_vnic_tpa_cfg(bp, vnic, 0);
 439
 440         return 0;
 441 err_out:
 442         PMD_DRV_LOG(ERR, "HWRM vnic %d cfg failure rc: %x\n",
 443                     vnic_id, rc);
 444         return rc;
 445 }
 446
 447 static int bnxt_register_fc_ctx_mem(struct bnxt *bp)
 448 {
 449         int rc = 0;
 450
 451         rc = bnxt_hwrm_ctx_rgtr(bp, bp->flow_stat->rx_fc_in_tbl.dma,
 452                                 &bp->flow_stat->rx_fc_in_tbl.ctx_id);
 453         if (rc)
 454                 return rc;
 455
 456         PMD_DRV_LOG(DEBUG,
 457                     "rx_fc_in_tbl.va = %p rx_fc_in_tbl.dma = %p"
 458                     " rx_fc_in_tbl.ctx_id = %d\n",
 459                     bp->flow_stat->rx_fc_in_tbl.va,
 460                     (void *)((uintptr_t)bp->flow_stat->rx_fc_in_tbl.dma),
 461                     bp->flow_stat->rx_fc_in_tbl.ctx_id);
 462
 463         rc = bnxt_hwrm_ctx_rgtr(bp, bp->flow_stat->rx_fc_out_tbl.dma,
 464                                 &bp->flow_stat->rx_fc_out_tbl.ctx_id);
 465         if (rc)
 466                 return rc;
 467
 468         PMD_DRV_LOG(DEBUG,
 469                     "rx_fc_out_tbl.va = %p rx_fc_out_tbl.dma = %p"
 470                     " rx_fc_out_tbl.ctx_id = %d\n",
 471                     bp->flow_stat->rx_fc_out_tbl.va,
 472                     (void *)((uintptr_t)bp->flow_stat->rx_fc_out_tbl.dma),
 473                     bp->flow_stat->rx_fc_out_tbl.ctx_id);
 474
 475         rc = bnxt_hwrm_ctx_rgtr(bp, bp->flow_stat->tx_fc_in_tbl.dma,
 476                                 &bp->flow_stat->tx_fc_in_tbl.ctx_id);
 477         if (rc)
 478                 return rc;
 479
 480         PMD_DRV_LOG(DEBUG,
 481                     "tx_fc_in_tbl.va = %p tx_fc_in_tbl.dma = %p"
 482                     " tx_fc_in_tbl.ctx_id = %d\n",
 483                     bp->flow_stat->tx_fc_in_tbl.va,
 484                     (void *)((uintptr_t)bp->flow_stat->tx_fc_in_tbl.dma),
 485                     bp->flow_stat->tx_fc_in_tbl.ctx_id);
 486
 487         rc = bnxt_hwrm_ctx_rgtr(bp, bp->flow_stat->tx_fc_out_tbl.dma,
 488                                 &bp->flow_stat->tx_fc_out_tbl.ctx_id);
 489         if (rc)
 490                 return rc;
 491
 492         PMD_DRV_LOG(DEBUG,
 493                     "tx_fc_out_tbl.va = %p tx_fc_out_tbl.dma = %p"
 494                     " tx_fc_out_tbl.ctx_id = %d\n",
 495                     bp->flow_stat->tx_fc_out_tbl.va,
 496                     (void *)((uintptr_t)bp->flow_stat->tx_fc_out_tbl.dma),
 497                     bp->flow_stat->tx_fc_out_tbl.ctx_id);
 498
 499         memset(bp->flow_stat->rx_fc_out_tbl.va,
 500                0,
 501                bp->flow_stat->rx_fc_out_tbl.size);
 502         rc = bnxt_hwrm_cfa_counter_cfg(bp, BNXT_DIR_RX,
 503                                        CFA_COUNTER_CFG_IN_COUNTER_TYPE_FC,
 504                                        bp->flow_stat->rx_fc_out_tbl.ctx_id,
 505                                        bp->flow_stat->max_fc,
 506                                        true);
 507         if (rc)
 508                 return rc;
 509
 510         memset(bp->flow_stat->tx_fc_out_tbl.va,
 511                0,
 512                bp->flow_stat->tx_fc_out_tbl.size);
 513         rc = bnxt_hwrm_cfa_counter_cfg(bp, BNXT_DIR_TX,
 514                                        CFA_COUNTER_CFG_IN_COUNTER_TYPE_FC,
 515                                        bp->flow_stat->tx_fc_out_tbl.ctx_id,
 516                                        bp->flow_stat->max_fc,
 517                                        true);
 518
 519         return rc;
 520 }
 521
 522 static int bnxt_alloc_ctx_mem_buf(char *type, size_t size,
 523                                   struct bnxt_ctx_mem_buf_info *ctx)
 524 {
 525         if (!ctx)
 526                 return -EINVAL;
 527
 528         ctx->va = rte_zmalloc(type, size, 0);
 529         if (ctx->va == NULL)
 530                 return -ENOMEM;
 531         rte_mem_lock_page(ctx->va);
 532         ctx->size = size;
 533         ctx->dma = rte_mem_virt2iova(ctx->va);
 534         if (ctx->dma == RTE_BAD_IOVA)
 535                 return -ENOMEM;
 536
 537         return 0;
 538 }
 539
 540 static int bnxt_init_fc_ctx_mem(struct bnxt *bp)
 541 {
 542         struct rte_pci_device *pdev = bp->pdev;
 543         char type[RTE_MEMZONE_NAMESIZE];
 544         uint16_t max_fc;
 545         int rc = 0;
 546
 547         max_fc = bp->flow_stat->max_fc;
 548
 549         sprintf(type, "bnxt_rx_fc_in_" PCI_PRI_FMT, pdev->addr.domain,
 550                 pdev->addr.bus, pdev->addr.devid, pdev->addr.function);
 551         /* 4 bytes for each counter-id */
 552         rc = bnxt_alloc_ctx_mem_buf(type,
 553                                     max_fc * 4,
 554                                     &bp->flow_stat->rx_fc_in_tbl);
 555         if (rc)
 556                 return rc;
 557
 558         sprintf(type, "bnxt_rx_fc_out_" PCI_PRI_FMT, pdev->addr.domain,
 559                 pdev->addr.bus, pdev->addr.devid, pdev->addr.function);
 560         /* 16 bytes for each counter - 8 bytes pkt_count, 8 bytes byte_count */
 561         rc = bnxt_alloc_ctx_mem_buf(type,
 562                                     max_fc * 16,
 563                                     &bp->flow_stat->rx_fc_out_tbl);
 564         if (rc)
 565                 return rc;
 566
 567         sprintf(type, "bnxt_tx_fc_in_" PCI_PRI_FMT, pdev->addr.domain,
 568                 pdev->addr.bus, pdev->addr.devid, pdev->addr.function);
 569         /* 4 bytes for each counter-id */
 570         rc = bnxt_alloc_ctx_mem_buf(type,
 571                                     max_fc * 4,
 572                                     &bp->flow_stat->tx_fc_in_tbl);
 573         if (rc)
 574                 return rc;
 575
 576         sprintf(type, "bnxt_tx_fc_out_" PCI_PRI_FMT, pdev->addr.domain,
 577                 pdev->addr.bus, pdev->addr.devid, pdev->addr.function);
 578         /* 16 bytes for each counter - 8 bytes pkt_count, 8 bytes byte_count */
 579         rc = bnxt_alloc_ctx_mem_buf(type,
 580                                     max_fc * 16,
 581                                     &bp->flow_stat->tx_fc_out_tbl);
 582         if (rc)
 583                 return rc;
 584
 585         rc = bnxt_register_fc_ctx_mem(bp);
 586
 587         return rc;
 588 }
 589
 590 static int bnxt_init_ctx_mem(struct bnxt *bp)
 591 {
 592         int rc = 0;
 593
 594         if (!(bp->fw_cap & BNXT_FW_CAP_ADV_FLOW_COUNTERS) ||
 595             !(BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp)) ||
 596             !BNXT_FLOW_XSTATS_EN(bp))
 597                 return 0;
 598
 599         rc = bnxt_hwrm_cfa_counter_qcaps(bp, &bp->flow_stat->max_fc);
 600         if (rc)
 601                 return rc;
 602
 603         rc = bnxt_init_fc_ctx_mem(bp);
 604
 605         return rc;
 606 }
 607
 608 static int bnxt_init_chip(struct bnxt *bp)
 609 {
 610         struct rte_eth_link new;
 611         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(bp->eth_dev);
 612         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
 613         uint32_t intr_vector = 0;
 614         uint32_t queue_id, base = BNXT_MISC_VEC_ID;
 615         uint32_t vec = BNXT_MISC_VEC_ID;
 616         unsigned int i, j;
 617         int rc;
 618
 619         if (bp->eth_dev->data->mtu > RTE_ETHER_MTU) {
 620                 bp->eth_dev->data->dev_conf.rxmode.offloads |=
 621                         DEV_RX_OFFLOAD_JUMBO_FRAME;
 622                 bp->flags |= BNXT_FLAG_JUMBO;
 623         } else {
 624                 bp->eth_dev->data->dev_conf.rxmode.offloads &=
 625                         ~DEV_RX_OFFLOAD_JUMBO_FRAME;
 626                 bp->flags &= ~BNXT_FLAG_JUMBO;
 627         }
 628
 629         /* THOR does not support ring groups.
 630          * But we will use the array to save RSS context IDs.
 631          */
 632         if (BNXT_CHIP_THOR(bp))
 633                 bp->max_ring_grps = BNXT_MAX_RSS_CTXTS_THOR;
 634
 635         rc = bnxt_alloc_all_hwrm_stat_ctxs(bp);
 636         if (rc) {
 637                 PMD_DRV_LOG(ERR, "HWRM stat ctx alloc failure rc: %x\n", rc);
 638                 goto err_out;
 639         }
 640
 641         rc = bnxt_alloc_hwrm_rings(bp);
 642         if (rc) {
 643                 PMD_DRV_LOG(ERR, "HWRM ring alloc failure rc: %x\n", rc);
 644                 goto err_out;
 645         }
 646
 647         rc = bnxt_alloc_all_hwrm_ring_grps(bp);
 648         if (rc) {
 649                 PMD_DRV_LOG(ERR, "HWRM ring grp alloc failure: %x\n", rc);
 650                 goto err_out;
 651         }
 652
 653         if (!(bp->vnic_cap_flags & BNXT_VNIC_CAP_COS_CLASSIFY))
 654                 goto skip_cosq_cfg;
 655
 656         for (j = 0, i = 0; i < BNXT_COS_QUEUE_COUNT; i++) {
 657                 if (bp->rx_cos_queue[i].id != 0xff) {
 658                         struct bnxt_vnic_info *vnic = &bp->vnic_info[j++];
 659
 660                         if (!vnic) {
 661                                 PMD_DRV_LOG(ERR,
 662                                             "Num pools more than FW profile\n");
 663                                 rc = -EINVAL;
 664                                 goto err_out;
 665                         }
 666                         vnic->cos_queue_id = bp->rx_cos_queue[i].id;
 667                         bp->rx_cosq_cnt++;
 668                 }
 669         }
 670
 671 skip_cosq_cfg:
 672         rc = bnxt_mq_rx_configure(bp);
 673         if (rc) {
 674                 PMD_DRV_LOG(ERR, "MQ mode configure failure rc: %x\n", rc);
 675                 goto err_out;
 676         }
 677
 678         /* VNIC configuration */
 679         for (i = 0; i < bp->nr_vnics; i++) {
 680                 rc = bnxt_setup_one_vnic(bp, i);
 681                 if (rc)
 682                         goto err_out;
 683         }
 684
 685         rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, &bp->vnic_info[0], 0, NULL);
 686         if (rc) {
 687                 PMD_DRV_LOG(ERR,
 688                         "HWRM cfa l2 rx mask failure rc: %x\n", rc);
 689                 goto err_out;
 690         }
 691
 692         /* check and configure queue intr-vector mapping */
 693         if ((rte_intr_cap_multiple(intr_handle) ||
 694              !RTE_ETH_DEV_SRIOV(bp->eth_dev).active) &&
 695             bp->eth_dev->data->dev_conf.intr_conf.rxq != 0) {
 696                 intr_vector = bp->eth_dev->data->nb_rx_queues;
 697                 PMD_DRV_LOG(DEBUG, "intr_vector = %d\n", intr_vector);
 698                 if (intr_vector > bp->rx_cp_nr_rings) {
 699                         PMD_DRV_LOG(ERR, "At most %d intr queues supported",
 700                                         bp->rx_cp_nr_rings);
 701                         return -ENOTSUP;
 702                 }
 703                 rc = rte_intr_efd_enable(intr_handle, intr_vector);
 704                 if (rc)
 705                         return rc;
 706         }
 707
 708         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
 709                 intr_handle->intr_vec =
 710                         rte_zmalloc("intr_vec",
 711                                     bp->eth_dev->data->nb_rx_queues *
 712                                     sizeof(int), 0);
 713                 if (intr_handle->intr_vec == NULL) {
 714                         PMD_DRV_LOG(ERR, "Failed to allocate %d rx_queues"
 715                                 " intr_vec", bp->eth_dev->data->nb_rx_queues);
 716                         rc = -ENOMEM;
 717                         goto err_disable;
 718                 }
 719                 PMD_DRV_LOG(DEBUG, "intr_handle->intr_vec = %p "
 720                         "intr_handle->nb_efd = %d intr_handle->max_intr = %d\n",
 721                          intr_handle->intr_vec, intr_handle->nb_efd,
 722                         intr_handle->max_intr);
 723                 for (queue_id = 0; queue_id < bp->eth_dev->data->nb_rx_queues;
 724                      queue_id++) {
 725                         intr_handle->intr_vec[queue_id] =
 726                                                         vec + BNXT_RX_VEC_START;
 727                         if (vec < base + intr_handle->nb_efd - 1)
 728                                 vec++;
 729                 }
 730         }
 731
 732         /* enable uio/vfio intr/eventfd mapping */
 733         rc = rte_intr_enable(intr_handle);
 734 #ifndef RTE_EXEC_ENV_FREEBSD
 735         /* In FreeBSD OS, nic_uio driver does not support interrupts */
 736         if (rc)
 737                 goto err_free;
 738 #endif
 739
 740         rc = bnxt_get_hwrm_link_config(bp, &new);
 741         if (rc) {
 742                 PMD_DRV_LOG(ERR, "HWRM Get link config failure rc: %x\n", rc);
 743                 goto err_free;
 744         }
 745
 746         if (!bp->link_info->link_up) {
 747                 rc = bnxt_set_hwrm_link_config(bp, true);
 748                 if (rc) {
 749                         PMD_DRV_LOG(ERR,
 750                                 "HWRM link config failure rc: %x\n", rc);
 751                         goto err_free;
 752                 }
 753         }
 754         bnxt_print_link_info(bp->eth_dev);
 755
 756         bp->mark_table = rte_zmalloc("bnxt_mark_table", BNXT_MARK_TABLE_SZ, 0);
 757         if (!bp->mark_table)
 758                 PMD_DRV_LOG(ERR, "Allocation of mark table failed\n");
 759
 760         return 0;
 761
 762 err_free:
 763         rte_free(intr_handle->intr_vec);
 764 err_disable:
 765         rte_intr_efd_disable(intr_handle);
 766 err_out:
 767         /* Some of the error status returned by FW may not be from errno.h */
 768         if (rc > 0)
 769                 rc = -EIO;
 770
 771         return rc;
 772 }
 773
 774 static int bnxt_shutdown_nic(struct bnxt *bp)
 775 {
 776         bnxt_free_all_hwrm_resources(bp);
 777         bnxt_free_all_filters(bp);
 778         bnxt_free_all_vnics(bp);
 779         return 0;
 780 }
 781
 782 /*
 783  * Device configuration and status function
 784  */
 785
 786 uint32_t bnxt_get_speed_capabilities(struct bnxt *bp)
 787 {
 788         uint32_t link_speed = bp->link_info->support_speeds;
 789         uint32_t speed_capa = 0;
 790
 791         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_100MB)
 792                 speed_capa |= ETH_LINK_SPEED_100M;
 793         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_100MBHD)
 794                 speed_capa |= ETH_LINK_SPEED_100M_HD;
 795         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_1GB)
 796                 speed_capa |= ETH_LINK_SPEED_1G;
 797         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_2_5GB)
 798                 speed_capa |= ETH_LINK_SPEED_2_5G;
 799         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_10GB)
 800                 speed_capa |= ETH_LINK_SPEED_10G;
 801         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_20GB)
 802                 speed_capa |= ETH_LINK_SPEED_20G;
 803         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_25GB)
 804                 speed_capa |= ETH_LINK_SPEED_25G;
 805         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_40GB)
 806                 speed_capa |= ETH_LINK_SPEED_40G;
 807         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_50GB)
 808                 speed_capa |= ETH_LINK_SPEED_50G;
 809         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_100GB)
 810                 speed_capa |= ETH_LINK_SPEED_100G;
 811         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_200GB)
 812                 speed_capa |= ETH_LINK_SPEED_200G;
 813
 814         if (bp->link_info->auto_mode ==
 815             HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_MODE_NONE)
 816                 speed_capa |= ETH_LINK_SPEED_FIXED;
 817         else
 818                 speed_capa |= ETH_LINK_SPEED_AUTONEG;
 819
 820         return speed_capa;
 821 }
 822
 823 static int bnxt_dev_info_get_op(struct rte_eth_dev *eth_dev,
 824                                 struct rte_eth_dev_info *dev_info)
 825 {
 826         struct rte_pci_device *pdev = RTE_DEV_TO_PCI(eth_dev->device);
 827         struct bnxt *bp = eth_dev->data->dev_private;
 828         uint16_t max_vnics, i, j, vpool, vrxq;
 829         unsigned int max_rx_rings;
 830         int rc;
 831
 832         rc = is_bnxt_in_error(bp);
 833         if (rc)
 834                 return rc;
 835
 836         /* MAC Specifics */
 837         dev_info->max_mac_addrs = bp->max_l2_ctx;
 838         dev_info->max_hash_mac_addrs = 0;
 839
 840         /* PF/VF specifics */
 841         if (BNXT_PF(bp))
 842                 dev_info->max_vfs = pdev->max_vfs;
 843
 844         max_rx_rings = BNXT_MAX_RINGS(bp);
 845         /* For the sake of symmetry, max_rx_queues = max_tx_queues */
 846         dev_info->max_rx_queues = max_rx_rings;
 847         dev_info->max_tx_queues = max_rx_rings;
 848         dev_info->reta_size = bnxt_rss_hash_tbl_size(bp);
 849         dev_info->hash_key_size = 40;
 850         max_vnics = bp->max_vnics;
 851
 852         /* MTU specifics */
 853         dev_info->min_mtu = RTE_ETHER_MIN_MTU;
 854         dev_info->max_mtu = BNXT_MAX_MTU;
 855
 856         /* Fast path specifics */
 857         dev_info->min_rx_bufsize = 1;
 858         dev_info->max_rx_pktlen = BNXT_MAX_PKT_LEN;
 859
 860         dev_info->rx_offload_capa = BNXT_DEV_RX_OFFLOAD_SUPPORT;
 861         if (bp->flags & BNXT_FLAG_PTP_SUPPORTED)
 862                 dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_TIMESTAMP;
 863         dev_info->tx_offload_capa = BNXT_DEV_TX_OFFLOAD_SUPPORT;
 864         dev_info->flow_type_rss_offloads = BNXT_ETH_RSS_SUPPORT;
 865
 866         dev_info->speed_capa = bnxt_get_speed_capabilities(bp);
 867
 868         /* *INDENT-OFF* */
 869         dev_info->default_rxconf = (struct rte_eth_rxconf) {
 870                 .rx_thresh = {
 871                         .pthresh = 8,
 872                         .hthresh = 8,
 873                         .wthresh = 0,
 874                 },
 875                 .rx_free_thresh = 32,
 876                 /* If no descriptors available, pkts are dropped by default */
 877                 .rx_drop_en = 1,
 878         };
 879
 880         dev_info->default_txconf = (struct rte_eth_txconf) {
 881                 .tx_thresh = {
 882                         .pthresh = 32,
 883                         .hthresh = 0,
 884                         .wthresh = 0,
 885                 },
 886                 .tx_free_thresh = 32,
 887                 .tx_rs_thresh = 32,
 888         };
 889         eth_dev->data->dev_conf.intr_conf.lsc = 1;
 890
 891         eth_dev->data->dev_conf.intr_conf.rxq = 1;
 892         dev_info->rx_desc_lim.nb_min = BNXT_MIN_RING_DESC;
 893         dev_info->rx_desc_lim.nb_max = BNXT_MAX_RX_RING_DESC;
 894         dev_info->tx_desc_lim.nb_min = BNXT_MIN_RING_DESC;
 895         dev_info->tx_desc_lim.nb_max = BNXT_MAX_TX_RING_DESC;
 896
 897         /* *INDENT-ON* */
 898
 899         /*
 900          * TODO: default_rxconf, default_txconf, rx_desc_lim, and tx_desc_lim
 901          *       need further investigation.
 902          */
 903
 904         /* VMDq resources */
 905         vpool = 64; /* ETH_64_POOLS */
 906         vrxq = 128; /* ETH_VMDQ_DCB_NUM_QUEUES */
 907         for (i = 0; i < 4; vpool >>= 1, i++) {
 908                 if (max_vnics > vpool) {
 909                         for (j = 0; j < 5; vrxq >>= 1, j++) {
 910                                 if (dev_info->max_rx_queues > vrxq) {
 911                                         if (vpool > vrxq)
 912                                                 vpool = vrxq;
 913                                         goto found;
 914                                 }
 915                         }
 916                         /* Not enough resources to support VMDq */
 917                         break;
 918                 }
 919         }
 920         /* Not enough resources to support VMDq */
 921         vpool = 0;
 922         vrxq = 0;
 923 found:
 924         dev_info->max_vmdq_pools = vpool;
 925         dev_info->vmdq_queue_num = vrxq;
 926
 927         dev_info->vmdq_pool_base = 0;
 928         dev_info->vmdq_queue_base = 0;
 929
 930         return 0;
 931 }
 932
 933 /* Configure the device based on the configuration provided */
 934 static int bnxt_dev_configure_op(struct rte_eth_dev *eth_dev)
 935 {
 936         struct bnxt *bp = eth_dev->data->dev_private;
 937         uint64_t rx_offloads = eth_dev->data->dev_conf.rxmode.offloads;
 938         int rc;
 939
 940         bp->rx_queues = (void *)eth_dev->data->rx_queues;
 941         bp->tx_queues = (void *)eth_dev->data->tx_queues;
 942         bp->tx_nr_rings = eth_dev->data->nb_tx_queues;
 943         bp->rx_nr_rings = eth_dev->data->nb_rx_queues;
 944
 945         rc = is_bnxt_in_error(bp);
 946         if (rc)
 947                 return rc;
 948
 949         if (BNXT_VF(bp) && (bp->flags & BNXT_FLAG_NEW_RM)) {
 950                 rc = bnxt_hwrm_check_vf_rings(bp);
 951                 if (rc) {
 952                         PMD_DRV_LOG(ERR, "HWRM insufficient resources\n");
 953                         return -ENOSPC;
 954                 }
 955
 956                 /* If a resource has already been allocated - in this case
 957                  * it is the async completion ring, free it. Reallocate it after
 958                  * resource reservation. This will ensure the resource counts
 959                  * are calculated correctly.
 960                  */
 961
 962                 pthread_mutex_lock(&bp->def_cp_lock);
 963
 964                 if (!BNXT_HAS_NQ(bp) && bp->async_cp_ring) {
 965                         bnxt_disable_int(bp);
 966                         bnxt_free_cp_ring(bp, bp->async_cp_ring);
 967                 }
 968
 969                 rc = bnxt_hwrm_func_reserve_vf_resc(bp, false);
 970                 if (rc) {
 971                         PMD_DRV_LOG(ERR, "HWRM resource alloc fail:%x\n", rc);
 972                         pthread_mutex_unlock(&bp->def_cp_lock);
 973                         return -ENOSPC;
 974                 }
 975
 976                 if (!BNXT_HAS_NQ(bp) && bp->async_cp_ring) {
 977                         rc = bnxt_alloc_async_cp_ring(bp);
 978                         if (rc) {
 979                                 pthread_mutex_unlock(&bp->def_cp_lock);
 980                                 return rc;
 981                         }
 982                         bnxt_enable_int(bp);
 983                 }
 984
 985                 pthread_mutex_unlock(&bp->def_cp_lock);
 986         } else {
 987                 /* legacy driver needs to get updated values */
 988                 rc = bnxt_hwrm_func_qcaps(bp);
 989                 if (rc) {
 990                         PMD_DRV_LOG(ERR, "hwrm func qcaps fail:%d\n", rc);
 991                         return rc;
 992                 }
 993         }
 994
 995         /* Inherit new configurations */
 996         if (eth_dev->data->nb_rx_queues > bp->max_rx_rings ||
 997             eth_dev->data->nb_tx_queues > bp->max_tx_rings ||
 998             eth_dev->data->nb_rx_queues + eth_dev->data->nb_tx_queues
 999                 + BNXT_NUM_ASYNC_CPR(bp) > bp->max_cp_rings ||
1000             eth_dev->data->nb_rx_queues + eth_dev->data->nb_tx_queues >
1001             bp->max_stat_ctx)
1002                 goto resource_error;
1003
1004         if (BNXT_HAS_RING_GRPS(bp) &&
1005             (uint32_t)(eth_dev->data->nb_rx_queues) > bp->max_ring_grps)
1006                 goto resource_error;
1007
1008         if (!(eth_dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_RSS) &&
1009             bp->max_vnics < eth_dev->data->nb_rx_queues)
1010                 goto resource_error;
1011
1012         bp->rx_cp_nr_rings = bp->rx_nr_rings;
1013         bp->tx_cp_nr_rings = bp->tx_nr_rings;
1014
1015         if (eth_dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG)
1016                 rx_offloads |= DEV_RX_OFFLOAD_RSS_HASH;
1017         eth_dev->data->dev_conf.rxmode.offloads = rx_offloads;
1018
1019         if (rx_offloads & DEV_RX_OFFLOAD_JUMBO_FRAME) {
1020                 eth_dev->data->mtu =
1021                         eth_dev->data->dev_conf.rxmode.max_rx_pkt_len -
1022                         RTE_ETHER_HDR_LEN - RTE_ETHER_CRC_LEN - VLAN_TAG_SIZE *
1023                         BNXT_NUM_VLANS;
1024                 bnxt_mtu_set_op(eth_dev, eth_dev->data->mtu);
1025         }
1026         return 0;
1027
1028 resource_error:
1029         PMD_DRV_LOG(ERR,
1030                     "Insufficient resources to support requested config\n");
1031         PMD_DRV_LOG(ERR,
1032                     "Num Queues Requested: Tx %d, Rx %d\n",
1033                     eth_dev->data->nb_tx_queues,
1034                     eth_dev->data->nb_rx_queues);
1035         PMD_DRV_LOG(ERR,
1036                     "MAX: TxQ %d, RxQ %d, CQ %d Stat %d, Grp %d, Vnic %d\n",
1037                     bp->max_tx_rings, bp->max_rx_rings, bp->max_cp_rings,
1038                     bp->max_stat_ctx, bp->max_ring_grps, bp->max_vnics);
1039         return -ENOSPC;
1040 }
1041
1042 void bnxt_print_link_info(struct rte_eth_dev *eth_dev)
1043 {
1044         struct rte_eth_link *link = &eth_dev->data->dev_link;
1045
1046         if (link->link_status)
1047                 PMD_DRV_LOG(INFO, "Port %d Link Up - speed %u Mbps - %s\n",
1048                         eth_dev->data->port_id,
1049                         (uint32_t)link->link_speed,
1050                         (link->link_duplex == ETH_LINK_FULL_DUPLEX) ?
1051                         ("full-duplex") : ("half-duplex\n"));
1052         else
1053                 PMD_DRV_LOG(INFO, "Port %d Link Down\n",
1054                         eth_dev->data->port_id);
1055 }
1056
1057 /*
1058  * Determine whether the current configuration requires support for scattered
1059  * receive; return 1 if scattered receive is required and 0 if not.
1060  */
1061 static int bnxt_scattered_rx(struct rte_eth_dev *eth_dev)
1062 {
1063         uint16_t buf_size;
1064         int i;
1065
1066         if (eth_dev->data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_SCATTER)
1067                 return 1;
1068
1069         for (i = 0; i < eth_dev->data->nb_rx_queues; i++) {
1070                 struct bnxt_rx_queue *rxq = eth_dev->data->rx_queues[i];
1071
1072                 buf_size = (uint16_t)(rte_pktmbuf_data_room_size(rxq->mb_pool) -
1073                                       RTE_PKTMBUF_HEADROOM);
1074                 if (eth_dev->data->dev_conf.rxmode.max_rx_pkt_len > buf_size)
1075                         return 1;
1076         }
1077         return 0;
1078 }
1079
1080 static eth_rx_burst_t
1081 bnxt_receive_function(struct rte_eth_dev *eth_dev)
1082 {
1083         struct bnxt *bp = eth_dev->data->dev_private;
1084
1085 #if defined(RTE_ARCH_X86) || defined(RTE_ARCH_ARM64)
1086 #ifndef RTE_LIBRTE_IEEE1588
1087         /*
1088          * Vector mode receive can be enabled only if scatter rx is not
1089          * in use and rx offloads are limited to VLAN stripping and
1090          * CRC stripping.
1091          */
1092         if (!eth_dev->data->scattered_rx &&
1093             !(eth_dev->data->dev_conf.rxmode.offloads &
1094               ~(DEV_RX_OFFLOAD_VLAN_STRIP |
1095                 DEV_RX_OFFLOAD_KEEP_CRC |
1096                 DEV_RX_OFFLOAD_JUMBO_FRAME |
1097                 DEV_RX_OFFLOAD_IPV4_CKSUM |
1098                 DEV_RX_OFFLOAD_UDP_CKSUM |
1099                 DEV_RX_OFFLOAD_TCP_CKSUM |
1100                 DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM |
1101                 DEV_RX_OFFLOAD_RSS_HASH |
1102                 DEV_RX_OFFLOAD_VLAN_FILTER)) &&
1103             !BNXT_TRUFLOW_EN(bp)) {
1104                 PMD_DRV_LOG(INFO, "Using vector mode receive for port %d\n",
1105                             eth_dev->data->port_id);
1106                 bp->flags |= BNXT_FLAG_RX_VECTOR_PKT_MODE;
1107                 return bnxt_recv_pkts_vec;
1108         }
1109         PMD_DRV_LOG(INFO, "Vector mode receive disabled for port %d\n",
1110                     eth_dev->data->port_id);
1111         PMD_DRV_LOG(INFO,
1112                     "Port %d scatter: %d rx offload: %" PRIX64 "\n",
1113                     eth_dev->data->port_id,
1114                     eth_dev->data->scattered_rx,
1115                     eth_dev->data->dev_conf.rxmode.offloads);
1116 #endif
1117 #endif
1118         bp->flags &= ~BNXT_FLAG_RX_VECTOR_PKT_MODE;
1119         return bnxt_recv_pkts;
1120 }
1121
1122 static eth_tx_burst_t
1123 bnxt_transmit_function(__rte_unused struct rte_eth_dev *eth_dev)
1124 {
1125 #if defined(RTE_ARCH_X86) || defined(RTE_ARCH_ARM64)
1126 #ifndef RTE_LIBRTE_IEEE1588
1127         struct bnxt *bp = eth_dev->data->dev_private;
1128
1129         /*
1130          * Vector mode transmit can be enabled only if not using scatter rx
1131          * or tx offloads.
1132          */
1133         if (!eth_dev->data->scattered_rx &&
1134             !eth_dev->data->dev_conf.txmode.offloads &&
1135             !BNXT_TRUFLOW_EN(bp)) {
1136                 PMD_DRV_LOG(INFO, "Using vector mode transmit for port %d\n",
1137                             eth_dev->data->port_id);
1138                 return bnxt_xmit_pkts_vec;
1139         }
1140         PMD_DRV_LOG(INFO, "Vector mode transmit disabled for port %d\n",
1141                     eth_dev->data->port_id);
1142         PMD_DRV_LOG(INFO,
1143                     "Port %d scatter: %d tx offload: %" PRIX64 "\n",
1144                     eth_dev->data->port_id,
1145                     eth_dev->data->scattered_rx,
1146                     eth_dev->data->dev_conf.txmode.offloads);
1147 #endif
1148 #endif
1149         return bnxt_xmit_pkts;
1150 }
1151
1152 static int bnxt_handle_if_change_status(struct bnxt *bp)
1153 {
1154         int rc;
1155
1156         /* Since fw has undergone a reset and lost all contexts,
1157          * set fatal flag to not issue hwrm during cleanup
1158          */
1159         bp->flags |= BNXT_FLAG_FATAL_ERROR;
1160         bnxt_uninit_resources(bp, true);
1161
1162         /* clear fatal flag so that re-init happens */
1163         bp->flags &= ~BNXT_FLAG_FATAL_ERROR;
1164         rc = bnxt_init_resources(bp, true);
1165
1166         bp->flags &= ~BNXT_FLAG_IF_CHANGE_HOT_FW_RESET_DONE;
1167
1168         return rc;
1169 }
1170
1171 static int32_t
1172 bnxt_create_port_app_df_rule(struct bnxt *bp, uint8_t flow_type,
1173                              uint32_t *flow_id)
1174 {
1175         uint16_t port_id = bp->eth_dev->data->port_id;
1176         struct ulp_tlv_param param_list[] = {
1177                 {
1178                         .type = BNXT_ULP_DF_PARAM_TYPE_DEV_PORT_ID,
1179                         .length = 2,
1180                         .value = {(port_id >> 8) & 0xff, port_id & 0xff}
1181                 },
1182                 {
1183                         .type = BNXT_ULP_DF_PARAM_TYPE_LAST,
1184                         .length = 0,
1185                         .value = {0}
1186                 }
1187         };
1188
1189         return ulp_default_flow_create(bp->eth_dev, param_list, flow_type,
1190                                        flow_id);
1191 }
1192
1193 static int32_t
1194 bnxt_create_df_rules(struct bnxt *bp)
1195 {
1196         struct bnxt_ulp_data *cfg_data;
1197         int rc;
1198
1199         cfg_data = bp->ulp_ctx->cfg_data;
1200         rc = bnxt_create_port_app_df_rule(bp, BNXT_ULP_DF_TPL_PORT_TO_VS,
1201                                           &cfg_data->port_to_app_flow_id);
1202         if (rc) {
1203                 PMD_DRV_LOG(ERR,
1204                             "Failed to create port to app default rule\n");
1205                 return rc;
1206         }
1207
1208         BNXT_TF_DBG(DEBUG, "***** created port to app default rule ******\n");
1209         rc = bnxt_create_port_app_df_rule(bp, BNXT_ULP_DF_TPL_VS_TO_PORT,
1210                                           &cfg_data->app_to_port_flow_id);
1211         if (!rc) {
1212                 rc = ulp_default_flow_db_cfa_action_get(bp->ulp_ctx,
1213                                                         cfg_data->app_to_port_flow_id,
1214                                                         &cfg_data->tx_cfa_action);
1215                 if (rc)
1216                         goto err;
1217
1218                 BNXT_TF_DBG(DEBUG,
1219                             "***** created app to port default rule *****\n");
1220                 return 0;
1221         }
1222
1223 err:
1224         BNXT_TF_DBG(DEBUG, "Failed to create app to port default rule\n");
1225         return rc;
1226 }
1227
1228 static void
1229 bnxt_destroy_df_rules(struct bnxt *bp)
1230 {
1231         struct bnxt_ulp_data *cfg_data;
1232
1233         cfg_data = bp->ulp_ctx->cfg_data;
1234         ulp_default_flow_destroy(bp->eth_dev, cfg_data->port_to_app_flow_id);
1235         ulp_default_flow_destroy(bp->eth_dev, cfg_data->app_to_port_flow_id);
1236 }
1237
1238 static int bnxt_dev_start_op(struct rte_eth_dev *eth_dev)
1239 {
1240         struct bnxt *bp = eth_dev->data->dev_private;
1241         uint64_t rx_offloads = eth_dev->data->dev_conf.rxmode.offloads;
1242         int vlan_mask = 0;
1243         int rc, retry_cnt = BNXT_IF_CHANGE_RETRY_COUNT;
1244
1245         if (!eth_dev->data->nb_tx_queues || !eth_dev->data->nb_rx_queues) {
1246                 PMD_DRV_LOG(ERR, "Queues are not configured yet!\n");
1247                 return -EINVAL;
1248         }
1249
1250         if (bp->rx_cp_nr_rings > RTE_ETHDEV_QUEUE_STAT_CNTRS) {
1251                 PMD_DRV_LOG(ERR,
1252                         "RxQ cnt %d > CONFIG_RTE_ETHDEV_QUEUE_STAT_CNTRS %d\n",
1253                         bp->rx_cp_nr_rings, RTE_ETHDEV_QUEUE_STAT_CNTRS);
1254         }
1255
1256         do {
1257                 rc = bnxt_hwrm_if_change(bp, true);
1258                 if (rc == 0 || rc != -EAGAIN)
1259                         break;
1260
1261                 rte_delay_ms(BNXT_IF_CHANGE_RETRY_INTERVAL);
1262         } while (retry_cnt--);
1263
1264         if (rc)
1265                 return rc;
1266
1267         if (bp->flags & BNXT_FLAG_IF_CHANGE_HOT_FW_RESET_DONE) {
1268                 rc = bnxt_handle_if_change_status(bp);
1269                 if (rc)
1270                         return rc;
1271         }
1272
1273         bnxt_enable_int(bp);
1274
1275         rc = bnxt_init_chip(bp);
1276         if (rc)
1277                 goto error;
1278
1279         eth_dev->data->scattered_rx = bnxt_scattered_rx(eth_dev);
1280         eth_dev->data->dev_started = 1;
1281
1282         bnxt_link_update(eth_dev, 1, ETH_LINK_UP);
1283
1284         if (rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER)
1285                 vlan_mask |= ETH_VLAN_FILTER_MASK;
1286         if (rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
1287                 vlan_mask |= ETH_VLAN_STRIP_MASK;
1288         rc = bnxt_vlan_offload_set_op(eth_dev, vlan_mask);
1289         if (rc)
1290                 goto error;
1291
1292         eth_dev->rx_pkt_burst = bnxt_receive_function(eth_dev);
1293         eth_dev->tx_pkt_burst = bnxt_transmit_function(eth_dev);
1294
1295         pthread_mutex_lock(&bp->def_cp_lock);
1296         bnxt_schedule_fw_health_check(bp);
1297         pthread_mutex_unlock(&bp->def_cp_lock);
1298
1299         if (BNXT_TRUFLOW_EN(bp))
1300                 bnxt_ulp_init(bp);
1301
1302         return 0;
1303
1304 error:
1305         bnxt_shutdown_nic(bp);
1306         bnxt_free_tx_mbufs(bp);
1307         bnxt_free_rx_mbufs(bp);
1308         bnxt_hwrm_if_change(bp, false);
1309         eth_dev->data->dev_started = 0;
1310         return rc;
1311 }
1312
1313 static int bnxt_dev_set_link_up_op(struct rte_eth_dev *eth_dev)
1314 {
1315         struct bnxt *bp = eth_dev->data->dev_private;
1316         int rc = 0;
1317
1318         if (!bp->link_info->link_up)
1319                 rc = bnxt_set_hwrm_link_config(bp, true);
1320         if (!rc)
1321                 eth_dev->data->dev_link.link_status = 1;
1322
1323         bnxt_print_link_info(eth_dev);
1324         return rc;
1325 }
1326
1327 static int bnxt_dev_set_link_down_op(struct rte_eth_dev *eth_dev)
1328 {
1329         struct bnxt *bp = eth_dev->data->dev_private;
1330
1331         eth_dev->data->dev_link.link_status = 0;
1332         bnxt_set_hwrm_link_config(bp, false);
1333         bp->link_info->link_up = 0;
1334
1335         return 0;
1336 }
1337
1338 static void bnxt_free_switch_domain(struct bnxt *bp)
1339 {
1340         if (bp->switch_domain_id)
1341                 rte_eth_switch_domain_free(bp->switch_domain_id);
1342 }
1343
1344 /* Unload the driver, release resources */
1345 static void bnxt_dev_stop_op(struct rte_eth_dev *eth_dev)
1346 {
1347         struct bnxt *bp = eth_dev->data->dev_private;
1348         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1349         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1350
1351         eth_dev->data->dev_started = 0;
1352         /* Prevent crashes when queues are still in use */
1353         eth_dev->rx_pkt_burst = &bnxt_dummy_recv_pkts;
1354         eth_dev->tx_pkt_burst = &bnxt_dummy_xmit_pkts;
1355
1356         bnxt_disable_int(bp);
1357
1358         /* disable uio/vfio intr/eventfd mapping */
1359         rte_intr_disable(intr_handle);
1360
1361         bnxt_cancel_fw_health_check(bp);
1362
1363         bnxt_dev_set_link_down_op(eth_dev);
1364
1365         /* Wait for link to be reset and the async notification to process.
1366          * During reset recovery, there is no need to wait and
1367          * VF/NPAR functions do not have privilege to change PHY config.
1368          */
1369         if (!is_bnxt_in_error(bp) && BNXT_SINGLE_PF(bp))
1370                 bnxt_link_update(eth_dev, 1, ETH_LINK_DOWN);
1371
1372         /* Clean queue intr-vector mapping */
1373         rte_intr_efd_disable(intr_handle);
1374         if (intr_handle->intr_vec != NULL) {
1375                 rte_free(intr_handle->intr_vec);
1376                 intr_handle->intr_vec = NULL;
1377         }
1378
1379         bnxt_hwrm_port_clr_stats(bp);
1380         bnxt_free_tx_mbufs(bp);
1381         bnxt_free_rx_mbufs(bp);
1382         /* Process any remaining notifications in default completion queue */
1383         bnxt_int_handler(eth_dev);
1384         bnxt_shutdown_nic(bp);
1385         bnxt_hwrm_if_change(bp, false);
1386
1387         rte_free(bp->mark_table);
1388         bp->mark_table = NULL;
1389
1390         bp->flags &= ~BNXT_FLAG_RX_VECTOR_PKT_MODE;
1391         bp->rx_cosq_cnt = 0;
1392         /* All filters are deleted on a port stop. */
1393         if (BNXT_FLOW_XSTATS_EN(bp))
1394                 bp->flow_stat->flow_count = 0;
1395 }
1396
1397 static void bnxt_dev_close_op(struct rte_eth_dev *eth_dev)
1398 {
1399         struct bnxt *bp = eth_dev->data->dev_private;
1400
1401         /* cancel the recovery handler before remove dev */
1402         rte_eal_alarm_cancel(bnxt_dev_reset_and_resume, (void *)bp);
1403         rte_eal_alarm_cancel(bnxt_dev_recover, (void *)bp);
1404         bnxt_cancel_fc_thread(bp);
1405
1406         if (BNXT_TRUFLOW_EN(bp)) {
1407                 bnxt_destroy_df_rules(bp);
1408                 bnxt_ulp_deinit(bp);
1409         }
1410
1411         if (eth_dev->data->dev_started)
1412                 bnxt_dev_stop_op(eth_dev);
1413
1414         bnxt_free_switch_domain(bp);
1415
1416         bnxt_uninit_resources(bp, false);
1417
1418         bnxt_free_leds_info(bp);
1419         bnxt_free_cos_queues(bp);
1420         bnxt_free_link_info(bp);
1421         bnxt_free_pf_info(bp);
1422         bnxt_free_parent_info(bp);
1423
1424         eth_dev->dev_ops = NULL;
1425         eth_dev->rx_pkt_burst = NULL;
1426         eth_dev->tx_pkt_burst = NULL;
1427
1428         rte_memzone_free((const struct rte_memzone *)bp->tx_mem_zone);
1429         bp->tx_mem_zone = NULL;
1430         rte_memzone_free((const struct rte_memzone *)bp->rx_mem_zone);
1431         bp->rx_mem_zone = NULL;
1432
1433         rte_free(bp->pf->vf_info);
1434         bp->pf->vf_info = NULL;
1435
1436         rte_free(bp->grp_info);
1437         bp->grp_info = NULL;
1438 }
1439
1440 static void bnxt_mac_addr_remove_op(struct rte_eth_dev *eth_dev,
1441                                     uint32_t index)
1442 {
1443         struct bnxt *bp = eth_dev->data->dev_private;
1444         uint64_t pool_mask = eth_dev->data->mac_pool_sel[index];
1445         struct bnxt_vnic_info *vnic;
1446         struct bnxt_filter_info *filter, *temp_filter;
1447         uint32_t i;
1448
1449         if (is_bnxt_in_error(bp))
1450                 return;
1451
1452         /*
1453          * Loop through all VNICs from the specified filter flow pools to
1454          * remove the corresponding MAC addr filter
1455          */
1456         for (i = 0; i < bp->nr_vnics; i++) {
1457                 if (!(pool_mask & (1ULL << i)))
1458                         continue;
1459
1460                 vnic = &bp->vnic_info[i];
1461                 filter = STAILQ_FIRST(&vnic->filter);
1462                 while (filter) {
1463                         temp_filter = STAILQ_NEXT(filter, next);
1464                         if (filter->mac_index == index) {
1465                                 STAILQ_REMOVE(&vnic->filter, filter,
1466                                                 bnxt_filter_info, next);
1467                                 bnxt_hwrm_clear_l2_filter(bp, filter);
1468                                 bnxt_free_filter(bp, filter);
1469                         }
1470                         filter = temp_filter;
1471                 }
1472         }
1473 }
1474
1475 static int bnxt_add_mac_filter(struct bnxt *bp, struct bnxt_vnic_info *vnic,
1476                                struct rte_ether_addr *mac_addr, uint32_t index,
1477                                uint32_t pool)
1478 {
1479         struct bnxt_filter_info *filter;
1480         int rc = 0;
1481
1482         /* Attach requested MAC address to the new l2_filter */
1483         STAILQ_FOREACH(filter, &vnic->filter, next) {
1484                 if (filter->mac_index == index) {
1485                         PMD_DRV_LOG(DEBUG,
1486                                     "MAC addr already existed for pool %d\n",
1487                                     pool);
1488                         return 0;
1489                 }
1490         }
1491
1492         filter = bnxt_alloc_filter(bp);
1493         if (!filter) {
1494                 PMD_DRV_LOG(ERR, "L2 filter alloc failed\n");
1495                 return -ENODEV;
1496         }
1497
1498         /* bnxt_alloc_filter copies default MAC to filter->l2_addr. So,
1499          * if the MAC that's been programmed now is a different one, then,
1500          * copy that addr to filter->l2_addr
1501          */
1502         if (mac_addr)
1503                 memcpy(filter->l2_addr, mac_addr, RTE_ETHER_ADDR_LEN);
1504         filter->flags |= HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_OUTERMOST;
1505
1506         rc = bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id, filter);
1507         if (!rc) {
1508                 filter->mac_index = index;
1509                 if (filter->mac_index == 0)
1510                         STAILQ_INSERT_HEAD(&vnic->filter, filter, next);
1511                 else
1512                         STAILQ_INSERT_TAIL(&vnic->filter, filter, next);
1513         } else {
1514                 bnxt_free_filter(bp, filter);
1515         }
1516
1517         return rc;
1518 }
1519
1520 static int bnxt_mac_addr_add_op(struct rte_eth_dev *eth_dev,
1521                                 struct rte_ether_addr *mac_addr,
1522                                 uint32_t index, uint32_t pool)
1523 {
1524         struct bnxt *bp = eth_dev->data->dev_private;
1525         struct bnxt_vnic_info *vnic = &bp->vnic_info[pool];
1526         int rc = 0;
1527
1528         rc = is_bnxt_in_error(bp);
1529         if (rc)
1530                 return rc;
1531
1532         if (BNXT_VF(bp) & !BNXT_VF_IS_TRUSTED(bp)) {
1533                 PMD_DRV_LOG(ERR, "Cannot add MAC address to a VF interface\n");
1534                 return -ENOTSUP;
1535         }
1536
1537         if (!vnic) {
1538                 PMD_DRV_LOG(ERR, "VNIC not found for pool %d!\n", pool);
1539                 return -EINVAL;
1540         }
1541
1542         /* Filter settings will get applied when port is started */
1543         if (!eth_dev->data->dev_started)
1544                 return 0;
1545
1546         rc = bnxt_add_mac_filter(bp, vnic, mac_addr, index, pool);
1547
1548         return rc;
1549 }
1550
1551 int bnxt_link_update(struct rte_eth_dev *eth_dev, int wait_to_complete,
1552                      bool exp_link_status)
1553 {
1554         int rc = 0;
1555         struct bnxt *bp = eth_dev->data->dev_private;
1556         struct rte_eth_link new;
1557         int cnt = exp_link_status ? BNXT_LINK_UP_WAIT_CNT :
1558                   BNXT_LINK_DOWN_WAIT_CNT;
1559
1560         rc = is_bnxt_in_error(bp);
1561         if (rc)
1562                 return rc;
1563
1564         memset(&new, 0, sizeof(new));
1565         do {
1566                 /* Retrieve link info from hardware */
1567                 rc = bnxt_get_hwrm_link_config(bp, &new);
1568                 if (rc) {
1569                         new.link_speed = ETH_LINK_SPEED_100M;
1570                         new.link_duplex = ETH_LINK_FULL_DUPLEX;
1571                         PMD_DRV_LOG(ERR,
1572                                 "Failed to retrieve link rc = 0x%x!\n", rc);
1573                         goto out;
1574                 }
1575
1576                 if (!wait_to_complete || new.link_status == exp_link_status)
1577                         break;
1578
1579                 rte_delay_ms(BNXT_LINK_WAIT_INTERVAL);
1580         } while (cnt--);
1581
1582 out:
1583         /* Timed out or success */
1584         if (new.link_status != eth_dev->data->dev_link.link_status ||
1585         new.link_speed != eth_dev->data->dev_link.link_speed) {
1586                 rte_eth_linkstatus_set(eth_dev, &new);
1587
1588                 _rte_eth_dev_callback_process(eth_dev,
1589                                               RTE_ETH_EVENT_INTR_LSC,
1590                                               NULL);
1591
1592                 bnxt_print_link_info(eth_dev);
1593         }
1594
1595         return rc;
1596 }
1597
1598 int bnxt_link_update_op(struct rte_eth_dev *eth_dev,
1599                         int wait_to_complete)
1600 {
1601         return bnxt_link_update(eth_dev, wait_to_complete, ETH_LINK_UP);
1602 }
1603
1604 static int bnxt_promiscuous_enable_op(struct rte_eth_dev *eth_dev)
1605 {
1606         struct bnxt *bp = eth_dev->data->dev_private;
1607         struct bnxt_vnic_info *vnic;
1608         uint32_t old_flags;
1609         int rc;
1610
1611         rc = is_bnxt_in_error(bp);
1612         if (rc)
1613                 return rc;
1614
1615         /* Filter settings will get applied when port is started */
1616         if (!eth_dev->data->dev_started)
1617                 return 0;
1618
1619         if (bp->vnic_info == NULL)
1620                 return 0;
1621
1622         vnic = BNXT_GET_DEFAULT_VNIC(bp);
1623
1624         old_flags = vnic->flags;
1625         vnic->flags |= BNXT_VNIC_INFO_PROMISC;
1626         rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1627         if (rc != 0)
1628                 vnic->flags = old_flags;
1629
1630         return rc;
1631 }
1632
1633 static int bnxt_promiscuous_disable_op(struct rte_eth_dev *eth_dev)
1634 {
1635         struct bnxt *bp = eth_dev->data->dev_private;
1636         struct bnxt_vnic_info *vnic;
1637         uint32_t old_flags;
1638         int rc;
1639
1640         rc = is_bnxt_in_error(bp);
1641         if (rc)
1642                 return rc;
1643
1644         /* Filter settings will get applied when port is started */
1645         if (!eth_dev->data->dev_started)
1646                 return 0;
1647
1648         if (bp->vnic_info == NULL)
1649                 return 0;
1650
1651         vnic = BNXT_GET_DEFAULT_VNIC(bp);
1652
1653         old_flags = vnic->flags;
1654         vnic->flags &= ~BNXT_VNIC_INFO_PROMISC;
1655         rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1656         if (rc != 0)
1657                 vnic->flags = old_flags;
1658
1659         if (BNXT_TRUFLOW_EN(bp))
1660                 bnxt_create_df_rules(bp);
1661
1662         return rc;
1663 }
1664
1665 static int bnxt_allmulticast_enable_op(struct rte_eth_dev *eth_dev)
1666 {
1667         struct bnxt *bp = eth_dev->data->dev_private;
1668         struct bnxt_vnic_info *vnic;
1669         uint32_t old_flags;
1670         int rc;
1671
1672         rc = is_bnxt_in_error(bp);
1673         if (rc)
1674                 return rc;
1675
1676         /* Filter settings will get applied when port is started */
1677         if (!eth_dev->data->dev_started)
1678                 return 0;
1679
1680         if (bp->vnic_info == NULL)
1681                 return 0;
1682
1683         vnic = BNXT_GET_DEFAULT_VNIC(bp);
1684
1685         old_flags = vnic->flags;
1686         vnic->flags |= BNXT_VNIC_INFO_ALLMULTI;
1687         rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1688         if (rc != 0)
1689                 vnic->flags = old_flags;
1690
1691         return rc;
1692 }
1693
1694 static int bnxt_allmulticast_disable_op(struct rte_eth_dev *eth_dev)
1695 {
1696         struct bnxt *bp = eth_dev->data->dev_private;
1697         struct bnxt_vnic_info *vnic;
1698         uint32_t old_flags;
1699         int rc;
1700
1701         rc = is_bnxt_in_error(bp);
1702         if (rc)
1703                 return rc;
1704
1705         /* Filter settings will get applied when port is started */
1706         if (!eth_dev->data->dev_started)
1707                 return 0;
1708
1709         if (bp->vnic_info == NULL)
1710                 return 0;
1711
1712         vnic = BNXT_GET_DEFAULT_VNIC(bp);
1713
1714         old_flags = vnic->flags;
1715         vnic->flags &= ~BNXT_VNIC_INFO_ALLMULTI;
1716         rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1717         if (rc != 0)
1718                 vnic->flags = old_flags;
1719
1720         return rc;
1721 }
1722
1723 /* Return bnxt_rx_queue pointer corresponding to a given rxq. */
1724 static struct bnxt_rx_queue *bnxt_qid_to_rxq(struct bnxt *bp, uint16_t qid)
1725 {
1726         if (qid >= bp->rx_nr_rings)
1727                 return NULL;
1728
1729         return bp->eth_dev->data->rx_queues[qid];
1730 }
1731
1732 /* Return rxq corresponding to a given rss table ring/group ID. */
1733 static uint16_t bnxt_rss_to_qid(struct bnxt *bp, uint16_t fwr)
1734 {
1735         struct bnxt_rx_queue *rxq;
1736         unsigned int i;
1737
1738         if (!BNXT_HAS_RING_GRPS(bp)) {
1739                 for (i = 0; i < bp->rx_nr_rings; i++) {
1740                         rxq = bp->eth_dev->data->rx_queues[i];
1741                         if (rxq->rx_ring->rx_ring_struct->fw_ring_id == fwr)
1742                                 return rxq->index;
1743                 }
1744         } else {
1745                 for (i = 0; i < bp->rx_nr_rings; i++) {
1746                         if (bp->grp_info[i].fw_grp_id == fwr)
1747                                 return i;
1748                 }
1749         }
1750
1751         return INVALID_HW_RING_ID;
1752 }
1753
1754 static int bnxt_reta_update_op(struct rte_eth_dev *eth_dev,
1755                             struct rte_eth_rss_reta_entry64 *reta_conf,
1756                             uint16_t reta_size)
1757 {
1758         struct bnxt *bp = eth_dev->data->dev_private;
1759         struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
1760         struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp);
1761         uint16_t tbl_size = bnxt_rss_hash_tbl_size(bp);
1762         uint16_t idx, sft;
1763         int i, rc;
1764
1765         rc = is_bnxt_in_error(bp);
1766         if (rc)
1767                 return rc;
1768
1769         if (!vnic->rss_table)
1770                 return -EINVAL;
1771
1772         if (!(dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG))
1773                 return -EINVAL;
1774
1775         if (reta_size != tbl_size) {
1776                 PMD_DRV_LOG(ERR, "The configured hash table lookup size "
1777                         "(%d) must equal the size supported by the hardware "
1778                         "(%d)\n", reta_size, tbl_size);
1779                 return -EINVAL;
1780         }
1781
1782         for (i = 0; i < reta_size; i++) {
1783                 struct bnxt_rx_queue *rxq;
1784
1785                 idx = i / RTE_RETA_GROUP_SIZE;
1786                 sft = i % RTE_RETA_GROUP_SIZE;
1787
1788                 if (!(reta_conf[idx].mask & (1ULL << sft)))
1789                         continue;
1790
1791                 rxq = bnxt_qid_to_rxq(bp, reta_conf[idx].reta[sft]);
1792                 if (!rxq) {
1793                         PMD_DRV_LOG(ERR, "Invalid ring in reta_conf.\n");
1794                         return -EINVAL;
1795                 }
1796
1797                 if (BNXT_CHIP_THOR(bp)) {
1798                         vnic->rss_table[i * 2] =
1799                                 rxq->rx_ring->rx_ring_struct->fw_ring_id;
1800                         vnic->rss_table[i * 2 + 1] =
1801                                 rxq->cp_ring->cp_ring_struct->fw_ring_id;
1802                 } else {
1803                         vnic->rss_table[i] =
1804                             vnic->fw_grp_ids[reta_conf[idx].reta[sft]];
1805                 }
1806         }
1807
1808         bnxt_hwrm_vnic_rss_cfg(bp, vnic);
1809         return 0;
1810 }
1811
1812 static int bnxt_reta_query_op(struct rte_eth_dev *eth_dev,
1813                               struct rte_eth_rss_reta_entry64 *reta_conf,
1814                               uint16_t reta_size)
1815 {
1816         struct bnxt *bp = eth_dev->data->dev_private;
1817         struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp);
1818         uint16_t tbl_size = bnxt_rss_hash_tbl_size(bp);
1819         uint16_t idx, sft, i;
1820         int rc;
1821
1822         rc = is_bnxt_in_error(bp);
1823         if (rc)
1824                 return rc;
1825
1826         /* Retrieve from the default VNIC */
1827         if (!vnic)
1828                 return -EINVAL;
1829         if (!vnic->rss_table)
1830                 return -EINVAL;
1831
1832         if (reta_size != tbl_size) {
1833                 PMD_DRV_LOG(ERR, "The configured hash table lookup size "
1834                         "(%d) must equal the size supported by the hardware "
1835                         "(%d)\n", reta_size, tbl_size);
1836                 return -EINVAL;
1837         }
1838
1839         for (idx = 0, i = 0; i < reta_size; i++) {
1840                 idx = i / RTE_RETA_GROUP_SIZE;
1841                 sft = i % RTE_RETA_GROUP_SIZE;
1842
1843                 if (reta_conf[idx].mask & (1ULL << sft)) {
1844                         uint16_t qid;
1845
1846                         if (BNXT_CHIP_THOR(bp))
1847                                 qid = bnxt_rss_to_qid(bp,
1848                                                       vnic->rss_table[i * 2]);
1849                         else
1850                                 qid = bnxt_rss_to_qid(bp, vnic->rss_table[i]);
1851
1852                         if (qid == INVALID_HW_RING_ID) {
1853                                 PMD_DRV_LOG(ERR, "Inv. entry in rss table.\n");
1854                                 return -EINVAL;
1855                         }
1856                         reta_conf[idx].reta[sft] = qid;
1857                 }
1858         }
1859
1860         return 0;
1861 }
1862
1863 static int bnxt_rss_hash_update_op(struct rte_eth_dev *eth_dev,
1864                                    struct rte_eth_rss_conf *rss_conf)
1865 {
1866         struct bnxt *bp = eth_dev->data->dev_private;
1867         struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
1868         struct bnxt_vnic_info *vnic;
1869         int rc;
1870
1871         rc = is_bnxt_in_error(bp);
1872         if (rc)
1873                 return rc;
1874
1875         /*
1876          * If RSS enablement were different than dev_configure,
1877          * then return -EINVAL
1878          */
1879         if (dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG) {
1880                 if (!rss_conf->rss_hf)
1881                         PMD_DRV_LOG(ERR, "Hash type NONE\n");
1882         } else {
1883                 if (rss_conf->rss_hf & BNXT_ETH_RSS_SUPPORT)
1884                         return -EINVAL;
1885         }
1886
1887         bp->flags |= BNXT_FLAG_UPDATE_HASH;
1888         memcpy(&eth_dev->data->dev_conf.rx_adv_conf.rss_conf,
1889                rss_conf,
1890                sizeof(*rss_conf));
1891
1892         /* Update the default RSS VNIC(s) */
1893         vnic = BNXT_GET_DEFAULT_VNIC(bp);
1894         vnic->hash_type = bnxt_rte_to_hwrm_hash_types(rss_conf->rss_hf);
1895
1896         /*
1897          * If hashkey is not specified, use the previously configured
1898          * hashkey
1899          */
1900         if (!rss_conf->rss_key)
1901                 goto rss_config;
1902
1903         if (rss_conf->rss_key_len != HW_HASH_KEY_SIZE) {
1904                 PMD_DRV_LOG(ERR,
1905                             "Invalid hashkey length, should be 16 bytes\n");
1906                 return -EINVAL;
1907         }
1908         memcpy(vnic->rss_hash_key, rss_conf->rss_key, rss_conf->rss_key_len);
1909
1910 rss_config:
1911         bnxt_hwrm_vnic_rss_cfg(bp, vnic);
1912         return 0;
1913 }
1914
1915 static int bnxt_rss_hash_conf_get_op(struct rte_eth_dev *eth_dev,
1916                                      struct rte_eth_rss_conf *rss_conf)
1917 {
1918         struct bnxt *bp = eth_dev->data->dev_private;
1919         struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp);
1920         int len, rc;
1921         uint32_t hash_types;
1922
1923         rc = is_bnxt_in_error(bp);
1924         if (rc)
1925                 return rc;
1926
1927         /* RSS configuration is the same for all VNICs */
1928         if (vnic && vnic->rss_hash_key) {
1929                 if (rss_conf->rss_key) {
1930                         len = rss_conf->rss_key_len <= HW_HASH_KEY_SIZE ?
1931                               rss_conf->rss_key_len : HW_HASH_KEY_SIZE;
1932                         memcpy(rss_conf->rss_key, vnic->rss_hash_key, len);
1933                 }
1934
1935                 hash_types = vnic->hash_type;
1936                 rss_conf->rss_hf = 0;
1937                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV4) {
1938                         rss_conf->rss_hf |= ETH_RSS_IPV4;
1939                         hash_types &= ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV4;
1940                 }
1941                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV4) {
1942                         rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP;
1943                         hash_types &=
1944                                 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV4;
1945                 }
1946                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV4) {
1947                         rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
1948                         hash_types &=
1949                                 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV4;
1950                 }
1951                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6) {
1952                         rss_conf->rss_hf |= ETH_RSS_IPV6;
1953                         hash_types &= ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6;
1954                 }
1955                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV6) {
1956                         rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV6_TCP;
1957                         hash_types &=
1958                                 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV6;
1959                 }
1960                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV6) {
1961                         rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;
1962                         hash_types &=
1963                                 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV6;
1964                 }
1965                 if (hash_types) {
1966                         PMD_DRV_LOG(ERR,
1967                                 "Unknown RSS config from firmware (%08x), RSS disabled",
1968                                 vnic->hash_type);
1969                         return -ENOTSUP;
1970                 }
1971         } else {
1972                 rss_conf->rss_hf = 0;
1973         }
1974         return 0;
1975 }
1976
1977 static int bnxt_flow_ctrl_get_op(struct rte_eth_dev *dev,
1978                                struct rte_eth_fc_conf *fc_conf)
1979 {
1980         struct bnxt *bp = dev->data->dev_private;
1981         struct rte_eth_link link_info;
1982         int rc;
1983
1984         rc = is_bnxt_in_error(bp);
1985         if (rc)
1986                 return rc;
1987
1988         rc = bnxt_get_hwrm_link_config(bp, &link_info);
1989         if (rc)
1990                 return rc;
1991
1992         memset(fc_conf, 0, sizeof(*fc_conf));
1993         if (bp->link_info->auto_pause)
1994                 fc_conf->autoneg = 1;
1995         switch (bp->link_info->pause) {
1996         case 0:
1997                 fc_conf->mode = RTE_FC_NONE;
1998                 break;
1999         case HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_TX:
2000                 fc_conf->mode = RTE_FC_TX_PAUSE;
2001                 break;
2002         case HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_RX:
2003                 fc_conf->mode = RTE_FC_RX_PAUSE;
2004                 break;
2005         case (HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_TX |
2006                         HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_RX):
2007                 fc_conf->mode = RTE_FC_FULL;
2008                 break;
2009         }
2010         return 0;
2011 }
2012
2013 static int bnxt_flow_ctrl_set_op(struct rte_eth_dev *dev,
2014                                struct rte_eth_fc_conf *fc_conf)
2015 {
2016         struct bnxt *bp = dev->data->dev_private;
2017         int rc;
2018
2019         rc = is_bnxt_in_error(bp);
2020         if (rc)
2021                 return rc;
2022
2023         if (!BNXT_SINGLE_PF(bp) || BNXT_VF(bp)) {
2024                 PMD_DRV_LOG(ERR, "Flow Control Settings cannot be modified\n");
2025                 return -ENOTSUP;
2026         }
2027
2028         switch (fc_conf->mode) {
2029         case RTE_FC_NONE:
2030                 bp->link_info->auto_pause = 0;
2031                 bp->link_info->force_pause = 0;
2032                 break;
2033         case RTE_FC_RX_PAUSE:
2034                 if (fc_conf->autoneg) {
2035                         bp->link_info->auto_pause =
2036                                         HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_RX;
2037                         bp->link_info->force_pause = 0;
2038                 } else {
2039                         bp->link_info->auto_pause = 0;
2040                         bp->link_info->force_pause =
2041                                         HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_RX;
2042                 }
2043                 break;
2044         case RTE_FC_TX_PAUSE:
2045                 if (fc_conf->autoneg) {
2046                         bp->link_info->auto_pause =
2047                                         HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_TX;
2048                         bp->link_info->force_pause = 0;
2049                 } else {
2050                         bp->link_info->auto_pause = 0;
2051                         bp->link_info->force_pause =
2052                                         HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_TX;
2053                 }
2054                 break;
2055         case RTE_FC_FULL:
2056                 if (fc_conf->autoneg) {
2057                         bp->link_info->auto_pause =
2058                                         HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_TX |
2059                                         HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_RX;
2060                         bp->link_info->force_pause = 0;
2061                 } else {
2062                         bp->link_info->auto_pause = 0;
2063                         bp->link_info->force_pause =
2064                                         HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_TX |
2065                                         HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_RX;
2066                 }
2067                 break;
2068         }
2069         return bnxt_set_hwrm_link_config(bp, true);
2070 }
2071
2072 /* Add UDP tunneling port */
2073 static int
2074 bnxt_udp_tunnel_port_add_op(struct rte_eth_dev *eth_dev,
2075                          struct rte_eth_udp_tunnel *udp_tunnel)
2076 {
2077         struct bnxt *bp = eth_dev->data->dev_private;
2078         uint16_t tunnel_type = 0;
2079         int rc = 0;
2080
2081         rc = is_bnxt_in_error(bp);
2082         if (rc)
2083                 return rc;
2084
2085         switch (udp_tunnel->prot_type) {
2086         case RTE_TUNNEL_TYPE_VXLAN:
2087                 if (bp->vxlan_port_cnt) {
2088                         PMD_DRV_LOG(ERR, "Tunnel Port %d already programmed\n",
2089                                 udp_tunnel->udp_port);
2090                         if (bp->vxlan_port != udp_tunnel->udp_port) {
2091                                 PMD_DRV_LOG(ERR, "Only one port allowed\n");
2092                                 return -ENOSPC;
2093                         }
2094                         bp->vxlan_port_cnt++;
2095                         return 0;
2096                 }
2097                 tunnel_type =
2098                         HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_VXLAN;
2099                 bp->vxlan_port_cnt++;
2100                 break;
2101         case RTE_TUNNEL_TYPE_GENEVE:
2102                 if (bp->geneve_port_cnt) {
2103                         PMD_DRV_LOG(ERR, "Tunnel Port %d already programmed\n",
2104                                 udp_tunnel->udp_port);
2105                         if (bp->geneve_port != udp_tunnel->udp_port) {
2106                                 PMD_DRV_LOG(ERR, "Only one port allowed\n");
2107                                 return -ENOSPC;
2108                         }
2109                         bp->geneve_port_cnt++;
2110                         return 0;
2111                 }
2112                 tunnel_type =
2113                         HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_GENEVE;
2114                 bp->geneve_port_cnt++;
2115                 break;
2116         default:
2117                 PMD_DRV_LOG(ERR, "Tunnel type is not supported\n");
2118                 return -ENOTSUP;
2119         }
2120         rc = bnxt_hwrm_tunnel_dst_port_alloc(bp, udp_tunnel->udp_port,
2121                                              tunnel_type);
2122         return rc;
2123 }
2124
2125 static int
2126 bnxt_udp_tunnel_port_del_op(struct rte_eth_dev *eth_dev,
2127                          struct rte_eth_udp_tunnel *udp_tunnel)
2128 {
2129         struct bnxt *bp = eth_dev->data->dev_private;
2130         uint16_t tunnel_type = 0;
2131         uint16_t port = 0;
2132         int rc = 0;
2133
2134         rc = is_bnxt_in_error(bp);
2135         if (rc)
2136                 return rc;
2137
2138         switch (udp_tunnel->prot_type) {
2139         case RTE_TUNNEL_TYPE_VXLAN:
2140                 if (!bp->vxlan_port_cnt) {
2141                         PMD_DRV_LOG(ERR, "No Tunnel port configured yet\n");
2142                         return -EINVAL;
2143                 }
2144                 if (bp->vxlan_port != udp_tunnel->udp_port) {
2145                         PMD_DRV_LOG(ERR, "Req Port: %d. Configured port: %d\n",
2146                                 udp_tunnel->udp_port, bp->vxlan_port);
2147                         return -EINVAL;
2148                 }
2149                 if (--bp->vxlan_port_cnt)
2150                         return 0;
2151
2152                 tunnel_type =
2153                         HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN;
2154                 port = bp->vxlan_fw_dst_port_id;
2155                 break;
2156         case RTE_TUNNEL_TYPE_GENEVE:
2157                 if (!bp->geneve_port_cnt) {
2158                         PMD_DRV_LOG(ERR, "No Tunnel port configured yet\n");
2159                         return -EINVAL;
2160                 }
2161                 if (bp->geneve_port != udp_tunnel->udp_port) {
2162                         PMD_DRV_LOG(ERR, "Req Port: %d. Configured port: %d\n",
2163                                 udp_tunnel->udp_port, bp->geneve_port);
2164                         return -EINVAL;
2165                 }
2166                 if (--bp->geneve_port_cnt)
2167                         return 0;
2168
2169                 tunnel_type =
2170                         HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_GENEVE;
2171                 port = bp->geneve_fw_dst_port_id;
2172                 break;
2173         default:
2174                 PMD_DRV_LOG(ERR, "Tunnel type is not supported\n");
2175                 return -ENOTSUP;
2176         }
2177
2178         rc = bnxt_hwrm_tunnel_dst_port_free(bp, port, tunnel_type);
2179         if (!rc) {
2180                 if (tunnel_type ==
2181                     HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN)
2182                         bp->vxlan_port = 0;
2183                 if (tunnel_type ==
2184                     HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_GENEVE)
2185                         bp->geneve_port = 0;
2186         }
2187         return rc;
2188 }
2189
2190 static int bnxt_del_vlan_filter(struct bnxt *bp, uint16_t vlan_id)
2191 {
2192         struct bnxt_filter_info *filter;
2193         struct bnxt_vnic_info *vnic;
2194         int rc = 0;
2195         uint32_t chk = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN;
2196
2197         vnic = BNXT_GET_DEFAULT_VNIC(bp);
2198         filter = STAILQ_FIRST(&vnic->filter);
2199         while (filter) {
2200                 /* Search for this matching MAC+VLAN filter */
2201                 if (bnxt_vlan_filter_exists(bp, filter, chk, vlan_id)) {
2202                         /* Delete the filter */
2203                         rc = bnxt_hwrm_clear_l2_filter(bp, filter);
2204                         if (rc)
2205                                 return rc;
2206                         STAILQ_REMOVE(&vnic->filter, filter,
2207                                       bnxt_filter_info, next);
2208                         bnxt_free_filter(bp, filter);
2209                         PMD_DRV_LOG(INFO,
2210                                     "Deleted vlan filter for %d\n",
2211                                     vlan_id);
2212                         return 0;
2213                 }
2214                 filter = STAILQ_NEXT(filter, next);
2215         }
2216         return -ENOENT;
2217 }
2218
2219 static int bnxt_add_vlan_filter(struct bnxt *bp, uint16_t vlan_id)
2220 {
2221         struct bnxt_filter_info *filter;
2222         struct bnxt_vnic_info *vnic;
2223         int rc = 0;
2224         uint32_t en = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN |
2225                 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN_MASK;
2226         uint32_t chk = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN;
2227
2228         /* Implementation notes on the use of VNIC in this command:
2229          *
2230          * By default, these filters belong to default vnic for the function.
2231          * Once these filters are set up, only destination VNIC can be modified.
2232          * If the destination VNIC is not specified in this command,
2233          * then the HWRM shall only create an l2 context id.
2234          */
2235
2236         vnic = BNXT_GET_DEFAULT_VNIC(bp);
2237         filter = STAILQ_FIRST(&vnic->filter);
2238         /* Check if the VLAN has already been added */
2239         while (filter) {
2240                 if (bnxt_vlan_filter_exists(bp, filter, chk, vlan_id))
2241                         return -EEXIST;
2242
2243                 filter = STAILQ_NEXT(filter, next);
2244         }
2245
2246         /* No match found. Alloc a fresh filter and issue the L2_FILTER_ALLOC
2247          * command to create MAC+VLAN filter with the right flags, enables set.
2248          */
2249         filter = bnxt_alloc_filter(bp);
2250         if (!filter) {
2251                 PMD_DRV_LOG(ERR,
2252                             "MAC/VLAN filter alloc failed\n");
2253                 return -ENOMEM;
2254         }
2255         /* MAC + VLAN ID filter */
2256         /* If l2_ivlan == 0 and l2_ivlan_mask != 0, only
2257          * untagged packets are received
2258          *
2259          * If l2_ivlan != 0 and l2_ivlan_mask != 0, untagged
2260          * packets and only the programmed vlan's packets are received
2261          */
2262         filter->l2_ivlan = vlan_id;
2263         filter->l2_ivlan_mask = 0x0FFF;
2264         filter->enables |= en;
2265         filter->flags |= HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_OUTERMOST;
2266
2267         rc = bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id, filter);
2268         if (rc) {
2269                 /* Free the newly allocated filter as we were
2270                  * not able to create the filter in hardware.
2271                  */
2272                 bnxt_free_filter(bp, filter);
2273                 return rc;
2274         }
2275
2276         filter->mac_index = 0;
2277         /* Add this new filter to the list */
2278         if (vlan_id == 0)
2279                 STAILQ_INSERT_HEAD(&vnic->filter, filter, next);
2280         else
2281                 STAILQ_INSERT_TAIL(&vnic->filter, filter, next);
2282
2283         PMD_DRV_LOG(INFO,
2284                     "Added Vlan filter for %d\n", vlan_id);
2285         return rc;
2286 }
2287
2288 static int bnxt_vlan_filter_set_op(struct rte_eth_dev *eth_dev,
2289                 uint16_t vlan_id, int on)
2290 {
2291         struct bnxt *bp = eth_dev->data->dev_private;
2292         int rc;
2293
2294         rc = is_bnxt_in_error(bp);
2295         if (rc)
2296                 return rc;
2297
2298         if (!eth_dev->data->dev_started) {
2299                 PMD_DRV_LOG(ERR, "port must be started before setting vlan\n");
2300                 return -EINVAL;
2301         }
2302
2303         /* These operations apply to ALL existing MAC/VLAN filters */
2304         if (on)
2305                 return bnxt_add_vlan_filter(bp, vlan_id);
2306         else
2307                 return bnxt_del_vlan_filter(bp, vlan_id);
2308 }
2309
2310 static int bnxt_del_dflt_mac_filter(struct bnxt *bp,
2311                                     struct bnxt_vnic_info *vnic)
2312 {
2313         struct bnxt_filter_info *filter;
2314         int rc;
2315
2316         filter = STAILQ_FIRST(&vnic->filter);
2317         while (filter) {
2318                 if (filter->mac_index == 0 &&
2319                     !memcmp(filter->l2_addr, bp->mac_addr,
2320                             RTE_ETHER_ADDR_LEN)) {
2321                         rc = bnxt_hwrm_clear_l2_filter(bp, filter);
2322                         if (!rc) {
2323                                 STAILQ_REMOVE(&vnic->filter, filter,
2324                                               bnxt_filter_info, next);
2325                                 bnxt_free_filter(bp, filter);
2326                         }
2327                         return rc;
2328                 }
2329                 filter = STAILQ_NEXT(filter, next);
2330         }
2331         return 0;
2332 }
2333
2334 static int
2335 bnxt_config_vlan_hw_filter(struct bnxt *bp, uint64_t rx_offloads)
2336 {
2337         struct bnxt_vnic_info *vnic;
2338         unsigned int i;
2339         int rc;
2340
2341         vnic = BNXT_GET_DEFAULT_VNIC(bp);
2342         if (!(rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER)) {
2343                 /* Remove any VLAN filters programmed */
2344                 for (i = 0; i < RTE_ETHER_MAX_VLAN_ID; i++)
2345                         bnxt_del_vlan_filter(bp, i);
2346
2347                 rc = bnxt_add_mac_filter(bp, vnic, NULL, 0, 0);
2348                 if (rc)
2349                         return rc;
2350         } else {
2351                 /* Default filter will allow packets that match the
2352                  * dest mac. So, it has to be deleted, otherwise, we
2353                  * will endup receiving vlan packets for which the
2354                  * filter is not programmed, when hw-vlan-filter
2355                  * configuration is ON
2356                  */
2357                 bnxt_del_dflt_mac_filter(bp, vnic);
2358                 /* This filter will allow only untagged packets */
2359                 bnxt_add_vlan_filter(bp, 0);
2360         }
2361         PMD_DRV_LOG(DEBUG, "VLAN Filtering: %d\n",
2362                     !!(rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER));
2363
2364         return 0;
2365 }
2366
2367 static int bnxt_free_one_vnic(struct bnxt *bp, uint16_t vnic_id)
2368 {
2369         struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id];
2370         unsigned int i;
2371         int rc;
2372
2373         /* Destroy vnic filters and vnic */
2374         if (bp->eth_dev->data->dev_conf.rxmode.offloads &
2375             DEV_RX_OFFLOAD_VLAN_FILTER) {
2376                 for (i = 0; i < RTE_ETHER_MAX_VLAN_ID; i++)
2377                         bnxt_del_vlan_filter(bp, i);
2378         }
2379         bnxt_del_dflt_mac_filter(bp, vnic);
2380
2381         rc = bnxt_hwrm_vnic_free(bp, vnic);
2382         if (rc)
2383                 return rc;
2384
2385         rte_free(vnic->fw_grp_ids);
2386         vnic->fw_grp_ids = NULL;
2387
2388         vnic->rx_queue_cnt = 0;
2389
2390         return 0;
2391 }
2392
2393 static int
2394 bnxt_config_vlan_hw_stripping(struct bnxt *bp, uint64_t rx_offloads)
2395 {
2396         struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp);
2397         int rc;
2398
2399         /* Destroy, recreate and reconfigure the default vnic */
2400         rc = bnxt_free_one_vnic(bp, 0);
2401         if (rc)
2402                 return rc;
2403
2404         /* default vnic 0 */
2405         rc = bnxt_setup_one_vnic(bp, 0);
2406         if (rc)
2407                 return rc;
2408
2409         if (bp->eth_dev->data->dev_conf.rxmode.offloads &
2410             DEV_RX_OFFLOAD_VLAN_FILTER) {
2411                 rc = bnxt_add_vlan_filter(bp, 0);
2412                 if (rc)
2413                         return rc;
2414                 rc = bnxt_restore_vlan_filters(bp);
2415                 if (rc)
2416                         return rc;
2417         } else {
2418                 rc = bnxt_add_mac_filter(bp, vnic, NULL, 0, 0);
2419                 if (rc)
2420                         return rc;
2421         }
2422
2423         rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
2424         if (rc)
2425                 return rc;
2426
2427         PMD_DRV_LOG(DEBUG, "VLAN Strip Offload: %d\n",
2428                     !!(rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP));
2429
2430         return rc;
2431 }
2432
2433 static int
2434 bnxt_vlan_offload_set_op(struct rte_eth_dev *dev, int mask)
2435 {
2436         uint64_t rx_offloads = dev->data->dev_conf.rxmode.offloads;
2437         struct bnxt *bp = dev->data->dev_private;
2438         int rc;
2439
2440         rc = is_bnxt_in_error(bp);
2441         if (rc)
2442                 return rc;
2443
2444         /* Filter settings will get applied when port is started */
2445         if (!dev->data->dev_started)
2446                 return 0;
2447
2448         if (mask & ETH_VLAN_FILTER_MASK) {
2449                 /* Enable or disable VLAN filtering */
2450                 rc = bnxt_config_vlan_hw_filter(bp, rx_offloads);
2451                 if (rc)
2452                         return rc;
2453         }
2454
2455         if (mask & ETH_VLAN_STRIP_MASK) {
2456                 /* Enable or disable VLAN stripping */
2457                 rc = bnxt_config_vlan_hw_stripping(bp, rx_offloads);
2458                 if (rc)
2459                         return rc;
2460         }
2461
2462         if (mask & ETH_VLAN_EXTEND_MASK) {
2463                 if (rx_offloads & DEV_RX_OFFLOAD_VLAN_EXTEND)
2464                         PMD_DRV_LOG(DEBUG, "Extend VLAN supported\n");
2465                 else
2466                         PMD_DRV_LOG(INFO, "Extend VLAN unsupported\n");
2467         }
2468
2469         return 0;
2470 }
2471
2472 static int
2473 bnxt_vlan_tpid_set_op(struct rte_eth_dev *dev, enum rte_vlan_type vlan_type,
2474                       uint16_t tpid)
2475 {
2476         struct bnxt *bp = dev->data->dev_private;
2477         int qinq = dev->data->dev_conf.rxmode.offloads &
2478                    DEV_RX_OFFLOAD_VLAN_EXTEND;
2479
2480         if (vlan_type != ETH_VLAN_TYPE_INNER &&
2481             vlan_type != ETH_VLAN_TYPE_OUTER) {
2482                 PMD_DRV_LOG(ERR,
2483                             "Unsupported vlan type.");
2484                 return -EINVAL;
2485         }
2486         if (!qinq) {
2487                 PMD_DRV_LOG(ERR,
2488                             "QinQ not enabled. Needs to be ON as we can "
2489                             "accelerate only outer vlan\n");
2490                 return -EINVAL;
2491         }
2492
2493         if (vlan_type == ETH_VLAN_TYPE_OUTER) {
2494                 switch (tpid) {
2495                 case RTE_ETHER_TYPE_QINQ:
2496                         bp->outer_tpid_bd =
2497                                 TX_BD_LONG_CFA_META_VLAN_TPID_TPID88A8;
2498                                 break;
2499                 case RTE_ETHER_TYPE_VLAN:
2500                         bp->outer_tpid_bd =
2501                                 TX_BD_LONG_CFA_META_VLAN_TPID_TPID8100;
2502                                 break;
2503                 case RTE_ETHER_TYPE_QINQ1:
2504                         bp->outer_tpid_bd =
2505                                 TX_BD_LONG_CFA_META_VLAN_TPID_TPID9100;
2506                                 break;
2507                 case RTE_ETHER_TYPE_QINQ2:
2508                         bp->outer_tpid_bd =
2509                                 TX_BD_LONG_CFA_META_VLAN_TPID_TPID9200;
2510                                 break;
2511                 case RTE_ETHER_TYPE_QINQ3:
2512                         bp->outer_tpid_bd =
2513                                  TX_BD_LONG_CFA_META_VLAN_TPID_TPID9300;
2514                                 break;
2515                 default:
2516                         PMD_DRV_LOG(ERR, "Invalid TPID: %x\n", tpid);
2517                         return -EINVAL;
2518                 }
2519                 bp->outer_tpid_bd |= tpid;
2520                 PMD_DRV_LOG(INFO, "outer_tpid_bd = %x\n", bp->outer_tpid_bd);
2521         } else if (vlan_type == ETH_VLAN_TYPE_INNER) {
2522                 PMD_DRV_LOG(ERR,
2523                             "Can accelerate only outer vlan in QinQ\n");
2524                 return -EINVAL;
2525         }
2526
2527         return 0;
2528 }
2529
2530 static int
2531 bnxt_set_default_mac_addr_op(struct rte_eth_dev *dev,
2532                              struct rte_ether_addr *addr)
2533 {
2534         struct bnxt *bp = dev->data->dev_private;
2535         /* Default Filter is tied to VNIC 0 */
2536         struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp);
2537         int rc;
2538
2539         rc = is_bnxt_in_error(bp);
2540         if (rc)
2541                 return rc;
2542
2543         if (BNXT_VF(bp) && !BNXT_VF_IS_TRUSTED(bp))
2544                 return -EPERM;
2545
2546         if (rte_is_zero_ether_addr(addr))
2547                 return -EINVAL;
2548
2549         /* Filter settings will get applied when port is started */
2550         if (!dev->data->dev_started)
2551                 return 0;
2552
2553         /* Check if the requested MAC is already added */
2554         if (memcmp(addr, bp->mac_addr, RTE_ETHER_ADDR_LEN) == 0)
2555                 return 0;
2556
2557         /* Destroy filter and re-create it */
2558         bnxt_del_dflt_mac_filter(bp, vnic);
2559
2560         memcpy(bp->mac_addr, addr, RTE_ETHER_ADDR_LEN);
2561         if (dev->data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_VLAN_FILTER) {
2562                 /* This filter will allow only untagged packets */
2563                 rc = bnxt_add_vlan_filter(bp, 0);
2564         } else {
2565                 rc = bnxt_add_mac_filter(bp, vnic, addr, 0, 0);
2566         }
2567
2568         PMD_DRV_LOG(DEBUG, "Set MAC addr\n");
2569         return rc;
2570 }
2571
2572 static int
2573 bnxt_dev_set_mc_addr_list_op(struct rte_eth_dev *eth_dev,
2574                           struct rte_ether_addr *mc_addr_set,
2575                           uint32_t nb_mc_addr)
2576 {
2577         struct bnxt *bp = eth_dev->data->dev_private;
2578         char *mc_addr_list = (char *)mc_addr_set;
2579         struct bnxt_vnic_info *vnic;
2580         uint32_t off = 0, i = 0;
2581         int rc;
2582
2583         rc = is_bnxt_in_error(bp);
2584         if (rc)
2585                 return rc;
2586
2587         vnic = BNXT_GET_DEFAULT_VNIC(bp);
2588
2589         if (nb_mc_addr > BNXT_MAX_MC_ADDRS) {
2590                 vnic->flags |= BNXT_VNIC_INFO_ALLMULTI;
2591                 goto allmulti;
2592         }
2593
2594         /* TODO Check for Duplicate mcast addresses */
2595         vnic->flags &= ~BNXT_VNIC_INFO_ALLMULTI;
2596         for (i = 0; i < nb_mc_addr; i++) {
2597                 memcpy(vnic->mc_list + off, &mc_addr_list[i],
2598                         RTE_ETHER_ADDR_LEN);
2599                 off += RTE_ETHER_ADDR_LEN;
2600         }
2601
2602         vnic->mc_addr_cnt = i;
2603         if (vnic->mc_addr_cnt)
2604                 vnic->flags |= BNXT_VNIC_INFO_MCAST;
2605         else
2606                 vnic->flags &= ~BNXT_VNIC_INFO_MCAST;
2607
2608 allmulti:
2609         return bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
2610 }
2611
2612 static int
2613 bnxt_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size)
2614 {
2615         struct bnxt *bp = dev->data->dev_private;
2616         uint8_t fw_major = (bp->fw_ver >> 24) & 0xff;
2617         uint8_t fw_minor = (bp->fw_ver >> 16) & 0xff;
2618         uint8_t fw_updt = (bp->fw_ver >> 8) & 0xff;
2619         uint8_t fw_rsvd = bp->fw_ver & 0xff;
2620         int ret;
2621
2622         ret = snprintf(fw_version, fw_size, "%d.%d.%d.%d",
2623                         fw_major, fw_minor, fw_updt, fw_rsvd);
2624
2625         ret += 1; /* add the size of '\0' */
2626         if (fw_size < (uint32_t)ret)
2627                 return ret;
2628         else
2629                 return 0;
2630 }
2631
2632 static void
2633 bnxt_rxq_info_get_op(struct rte_eth_dev *dev, uint16_t queue_id,
2634         struct rte_eth_rxq_info *qinfo)
2635 {
2636         struct bnxt *bp = dev->data->dev_private;
2637         struct bnxt_rx_queue *rxq;
2638
2639         if (is_bnxt_in_error(bp))
2640                 return;
2641
2642         rxq = dev->data->rx_queues[queue_id];
2643
2644         qinfo->mp = rxq->mb_pool;
2645         qinfo->scattered_rx = dev->data->scattered_rx;
2646         qinfo->nb_desc = rxq->nb_rx_desc;
2647
2648         qinfo->conf.rx_free_thresh = rxq->rx_free_thresh;
2649         qinfo->conf.rx_drop_en = 0;
2650         qinfo->conf.rx_deferred_start = rxq->rx_deferred_start;
2651 }
2652
2653 static void
2654 bnxt_txq_info_get_op(struct rte_eth_dev *dev, uint16_t queue_id,
2655         struct rte_eth_txq_info *qinfo)
2656 {
2657         struct bnxt *bp = dev->data->dev_private;
2658         struct bnxt_tx_queue *txq;
2659
2660         if (is_bnxt_in_error(bp))
2661                 return;
2662
2663         txq = dev->data->tx_queues[queue_id];
2664
2665         qinfo->nb_desc = txq->nb_tx_desc;
2666
2667         qinfo->conf.tx_thresh.pthresh = txq->pthresh;
2668         qinfo->conf.tx_thresh.hthresh = txq->hthresh;
2669         qinfo->conf.tx_thresh.wthresh = txq->wthresh;
2670
2671         qinfo->conf.tx_free_thresh = txq->tx_free_thresh;
2672         qinfo->conf.tx_rs_thresh = 0;
2673         qinfo->conf.tx_deferred_start = txq->tx_deferred_start;
2674 }
2675
2676 static int
2677 bnxt_rx_burst_mode_get(struct rte_eth_dev *dev, __rte_unused uint16_t queue_id,
2678                        struct rte_eth_burst_mode *mode)
2679 {
2680         eth_rx_burst_t pkt_burst = dev->rx_pkt_burst;
2681
2682         if (pkt_burst == bnxt_recv_pkts) {
2683                 snprintf(mode->info, sizeof(mode->info), "%s",
2684                          "Scalar");
2685                 return 0;
2686         }
2687 #if defined(RTE_ARCH_X86) || defined(RTE_ARCH_ARM64)
2688         if (pkt_burst == bnxt_recv_pkts_vec) {
2689                 snprintf(mode->info, sizeof(mode->info), "%s",
2690                          "Vector SSE");
2691                 return 0;
2692         }
2693 #endif
2694
2695         return -EINVAL;
2696 }
2697
2698 static int
2699 bnxt_tx_burst_mode_get(struct rte_eth_dev *dev, __rte_unused uint16_t queue_id,
2700                        struct rte_eth_burst_mode *mode)
2701 {
2702         eth_tx_burst_t pkt_burst = dev->tx_pkt_burst;
2703
2704         if (pkt_burst == bnxt_xmit_pkts) {
2705                 snprintf(mode->info, sizeof(mode->info), "%s",
2706                          "Scalar");
2707                 return 0;
2708         }
2709 #if defined(RTE_ARCH_X86) || defined(RTE_ARCH_ARM64)
2710         if (pkt_burst == bnxt_xmit_pkts_vec) {
2711                 snprintf(mode->info, sizeof(mode->info), "%s",
2712                          "Vector SSE");
2713                 return 0;
2714         }
2715 #endif
2716
2717         return -EINVAL;
2718 }
2719
2720 int bnxt_mtu_set_op(struct rte_eth_dev *eth_dev, uint16_t new_mtu)
2721 {
2722         struct bnxt *bp = eth_dev->data->dev_private;
2723         uint32_t new_pkt_size;
2724         uint32_t rc = 0;
2725         uint32_t i;
2726
2727         rc = is_bnxt_in_error(bp);
2728         if (rc)
2729                 return rc;
2730
2731         /* Exit if receive queues are not configured yet */
2732         if (!eth_dev->data->nb_rx_queues)
2733                 return rc;
2734
2735         new_pkt_size = new_mtu + RTE_ETHER_HDR_LEN + RTE_ETHER_CRC_LEN +
2736                        VLAN_TAG_SIZE * BNXT_NUM_VLANS;
2737
2738 #if defined(RTE_ARCH_X86) || defined(RTE_ARCH_ARM64)
2739         /*
2740          * If vector-mode tx/rx is active, disallow any MTU change that would
2741          * require scattered receive support.
2742          */
2743         if (eth_dev->data->dev_started &&
2744             (eth_dev->rx_pkt_burst == bnxt_recv_pkts_vec ||
2745              eth_dev->tx_pkt_burst == bnxt_xmit_pkts_vec) &&
2746             (new_pkt_size >
2747              eth_dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM)) {
2748                 PMD_DRV_LOG(ERR,
2749                             "MTU change would require scattered rx support. ");
2750                 PMD_DRV_LOG(ERR, "Stop port before changing MTU.\n");
2751                 return -EINVAL;
2752         }
2753 #endif
2754
2755         if (new_mtu > RTE_ETHER_MTU) {
2756                 bp->flags |= BNXT_FLAG_JUMBO;
2757                 bp->eth_dev->data->dev_conf.rxmode.offloads |=
2758                         DEV_RX_OFFLOAD_JUMBO_FRAME;
2759         } else {
2760                 bp->eth_dev->data->dev_conf.rxmode.offloads &=
2761                         ~DEV_RX_OFFLOAD_JUMBO_FRAME;
2762                 bp->flags &= ~BNXT_FLAG_JUMBO;
2763         }
2764
2765         /* Is there a change in mtu setting? */
2766         if (eth_dev->data->dev_conf.rxmode.max_rx_pkt_len == new_pkt_size)
2767                 return rc;
2768
2769         for (i = 0; i < bp->nr_vnics; i++) {
2770                 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
2771                 uint16_t size = 0;
2772
2773                 vnic->mru = BNXT_VNIC_MRU(new_mtu);
2774                 rc = bnxt_hwrm_vnic_cfg(bp, vnic);
2775                 if (rc)
2776                         break;
2777
2778                 size = rte_pktmbuf_data_room_size(bp->rx_queues[0]->mb_pool);
2779                 size -= RTE_PKTMBUF_HEADROOM;
2780
2781                 if (size < new_mtu) {
2782                         rc = bnxt_hwrm_vnic_plcmode_cfg(bp, vnic);
2783                         if (rc)
2784                                 return rc;
2785                 }
2786         }
2787
2788         if (!rc)
2789                 eth_dev->data->dev_conf.rxmode.max_rx_pkt_len = new_pkt_size;
2790
2791         PMD_DRV_LOG(INFO, "New MTU is %d\n", new_mtu);
2792
2793         return rc;
2794 }
2795
2796 static int
2797 bnxt_vlan_pvid_set_op(struct rte_eth_dev *dev, uint16_t pvid, int on)
2798 {
2799         struct bnxt *bp = dev->data->dev_private;
2800         uint16_t vlan = bp->vlan;
2801         int rc;
2802
2803         rc = is_bnxt_in_error(bp);
2804         if (rc)
2805                 return rc;
2806
2807         if (!BNXT_SINGLE_PF(bp) || BNXT_VF(bp)) {
2808                 PMD_DRV_LOG(ERR,
2809                         "PVID cannot be modified for this function\n");
2810                 return -ENOTSUP;
2811         }
2812         bp->vlan = on ? pvid : 0;
2813
2814         rc = bnxt_hwrm_set_default_vlan(bp, 0, 0);
2815         if (rc)
2816                 bp->vlan = vlan;
2817         return rc;
2818 }
2819
2820 static int
2821 bnxt_dev_led_on_op(struct rte_eth_dev *dev)
2822 {
2823         struct bnxt *bp = dev->data->dev_private;
2824         int rc;
2825
2826         rc = is_bnxt_in_error(bp);
2827         if (rc)
2828                 return rc;
2829
2830         return bnxt_hwrm_port_led_cfg(bp, true);
2831 }
2832
2833 static int
2834 bnxt_dev_led_off_op(struct rte_eth_dev *dev)
2835 {
2836         struct bnxt *bp = dev->data->dev_private;
2837         int rc;
2838
2839         rc = is_bnxt_in_error(bp);
2840         if (rc)
2841                 return rc;
2842
2843         return bnxt_hwrm_port_led_cfg(bp, false);
2844 }
2845
2846 static uint32_t
2847 bnxt_rx_queue_count_op(struct rte_eth_dev *dev, uint16_t rx_queue_id)
2848 {
2849         struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
2850         uint32_t desc = 0, raw_cons = 0, cons;
2851         struct bnxt_cp_ring_info *cpr;
2852         struct bnxt_rx_queue *rxq;
2853         struct rx_pkt_cmpl *rxcmp;
2854         int rc;
2855
2856         rc = is_bnxt_in_error(bp);
2857         if (rc)
2858                 return rc;
2859
2860         rxq = dev->data->rx_queues[rx_queue_id];
2861         cpr = rxq->cp_ring;
2862         raw_cons = cpr->cp_raw_cons;
2863
2864         while (1) {
2865                 cons = RING_CMP(cpr->cp_ring_struct, raw_cons);
2866                 rte_prefetch0(&cpr->cp_desc_ring[cons]);
2867                 rxcmp = (struct rx_pkt_cmpl *)&cpr->cp_desc_ring[cons];
2868
2869                 if (!CMP_VALID(rxcmp, raw_cons, cpr->cp_ring_struct)) {
2870                         break;
2871                 } else {
2872                         raw_cons++;
2873                         desc++;
2874                 }
2875         }
2876
2877         return desc;
2878 }
2879
2880 static int
2881 bnxt_rx_descriptor_status_op(void *rx_queue, uint16_t offset)
2882 {
2883         struct bnxt_rx_queue *rxq = (struct bnxt_rx_queue *)rx_queue;
2884         struct bnxt_rx_ring_info *rxr;
2885         struct bnxt_cp_ring_info *cpr;
2886         struct bnxt_sw_rx_bd *rx_buf;
2887         struct rx_pkt_cmpl *rxcmp;
2888         uint32_t cons, cp_cons;
2889         int rc;
2890
2891         if (!rxq)
2892                 return -EINVAL;
2893
2894         rc = is_bnxt_in_error(rxq->bp);
2895         if (rc)
2896                 return rc;
2897
2898         cpr = rxq->cp_ring;
2899         rxr = rxq->rx_ring;
2900
2901         if (offset >= rxq->nb_rx_desc)
2902                 return -EINVAL;
2903
2904         cons = RING_CMP(cpr->cp_ring_struct, offset);
2905         cp_cons = cpr->cp_raw_cons;
2906         rxcmp = (struct rx_pkt_cmpl *)&cpr->cp_desc_ring[cons];
2907
2908         if (cons > cp_cons) {
2909                 if (CMPL_VALID(rxcmp, cpr->valid))
2910                         return RTE_ETH_RX_DESC_DONE;
2911         } else {
2912                 if (CMPL_VALID(rxcmp, !cpr->valid))
2913                         return RTE_ETH_RX_DESC_DONE;
2914         }
2915         rx_buf = &rxr->rx_buf_ring[cons];
2916         if (rx_buf->mbuf == NULL)
2917                 return RTE_ETH_RX_DESC_UNAVAIL;
2918
2919
2920         return RTE_ETH_RX_DESC_AVAIL;
2921 }
2922
2923 static int
2924 bnxt_tx_descriptor_status_op(void *tx_queue, uint16_t offset)
2925 {
2926         struct bnxt_tx_queue *txq = (struct bnxt_tx_queue *)tx_queue;
2927         struct bnxt_tx_ring_info *txr;
2928         struct bnxt_cp_ring_info *cpr;
2929         struct bnxt_sw_tx_bd *tx_buf;
2930         struct tx_pkt_cmpl *txcmp;
2931         uint32_t cons, cp_cons;
2932         int rc;
2933
2934         if (!txq)
2935                 return -EINVAL;
2936
2937         rc = is_bnxt_in_error(txq->bp);
2938         if (rc)
2939                 return rc;
2940
2941         cpr = txq->cp_ring;
2942         txr = txq->tx_ring;
2943
2944         if (offset >= txq->nb_tx_desc)
2945                 return -EINVAL;
2946
2947         cons = RING_CMP(cpr->cp_ring_struct, offset);
2948         txcmp = (struct tx_pkt_cmpl *)&cpr->cp_desc_ring[cons];
2949         cp_cons = cpr->cp_raw_cons;
2950
2951         if (cons > cp_cons) {
2952                 if (CMPL_VALID(txcmp, cpr->valid))
2953                         return RTE_ETH_TX_DESC_UNAVAIL;
2954         } else {
2955                 if (CMPL_VALID(txcmp, !cpr->valid))
2956                         return RTE_ETH_TX_DESC_UNAVAIL;
2957         }
2958         tx_buf = &txr->tx_buf_ring[cons];
2959         if (tx_buf->mbuf == NULL)
2960                 return RTE_ETH_TX_DESC_DONE;
2961
2962         return RTE_ETH_TX_DESC_FULL;
2963 }
2964
2965 static struct bnxt_filter_info *
2966 bnxt_match_and_validate_ether_filter(struct bnxt *bp,
2967                                 struct rte_eth_ethertype_filter *efilter,
2968                                 struct bnxt_vnic_info *vnic0,
2969                                 struct bnxt_vnic_info *vnic,
2970                                 int *ret)
2971 {
2972         struct bnxt_filter_info *mfilter = NULL;
2973         int match = 0;
2974         *ret = 0;
2975
2976         if (efilter->ether_type == RTE_ETHER_TYPE_IPV4 ||
2977                 efilter->ether_type == RTE_ETHER_TYPE_IPV6) {
2978                 PMD_DRV_LOG(ERR, "invalid ether_type(0x%04x) in"
2979                         " ethertype filter.", efilter->ether_type);
2980                 *ret = -EINVAL;
2981                 goto exit;
2982         }
2983         if (efilter->queue >= bp->rx_nr_rings) {
2984                 PMD_DRV_LOG(ERR, "Invalid queue %d\n", efilter->queue);
2985                 *ret = -EINVAL;
2986                 goto exit;
2987         }
2988
2989         vnic0 = BNXT_GET_DEFAULT_VNIC(bp);
2990         vnic = &bp->vnic_info[efilter->queue];
2991         if (vnic == NULL) {
2992                 PMD_DRV_LOG(ERR, "Invalid queue %d\n", efilter->queue);
2993                 *ret = -EINVAL;
2994                 goto exit;
2995         }
2996
2997         if (efilter->flags & RTE_ETHTYPE_FLAGS_DROP) {
2998                 STAILQ_FOREACH(mfilter, &vnic0->filter, next) {
2999                         if ((!memcmp(efilter->mac_addr.addr_bytes,
3000                                      mfilter->l2_addr, RTE_ETHER_ADDR_LEN) &&
3001                              mfilter->flags ==
3002                              HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_DROP &&
3003                              mfilter->ethertype == efilter->ether_type)) {
3004                                 match = 1;
3005                                 break;
3006                         }
3007                 }
3008         } else {
3009                 STAILQ_FOREACH(mfilter, &vnic->filter, next)
3010                         if ((!memcmp(efilter->mac_addr.addr_bytes,
3011                                      mfilter->l2_addr, RTE_ETHER_ADDR_LEN) &&
3012                              mfilter->ethertype == efilter->ether_type &&
3013                              mfilter->flags ==
3014                              HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_PATH_RX)) {
3015                                 match = 1;
3016                                 break;
3017                         }
3018         }
3019
3020         if (match)
3021                 *ret = -EEXIST;
3022
3023 exit:
3024         return mfilter;
3025 }
3026
3027 static int
3028 bnxt_ethertype_filter(struct rte_eth_dev *dev,
3029                         enum rte_filter_op filter_op,
3030                         void *arg)
3031 {
3032         struct bnxt *bp = dev->data->dev_private;
3033         struct rte_eth_ethertype_filter *efilter =
3034                         (struct rte_eth_ethertype_filter *)arg;
3035         struct bnxt_filter_info *bfilter, *filter1;
3036         struct bnxt_vnic_info *vnic, *vnic0;
3037         int ret;
3038
3039         if (filter_op == RTE_ETH_FILTER_NOP)
3040                 return 0;
3041
3042         if (arg == NULL) {
3043                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
3044                             filter_op);
3045                 return -EINVAL;
3046         }
3047
3048         vnic0 = BNXT_GET_DEFAULT_VNIC(bp);
3049         vnic = &bp->vnic_info[efilter->queue];
3050
3051         switch (filter_op) {
3052         case RTE_ETH_FILTER_ADD:
3053                 bnxt_match_and_validate_ether_filter(bp, efilter,
3054                                                         vnic0, vnic, &ret);
3055                 if (ret < 0)
3056                         return ret;
3057
3058                 bfilter = bnxt_get_unused_filter(bp);
3059                 if (bfilter == NULL) {
3060                         PMD_DRV_LOG(ERR,
3061                                 "Not enough resources for a new filter.\n");
3062                         return -ENOMEM;
3063                 }
3064                 bfilter->filter_type = HWRM_CFA_NTUPLE_FILTER;
3065                 memcpy(bfilter->l2_addr, efilter->mac_addr.addr_bytes,
3066                        RTE_ETHER_ADDR_LEN);
3067                 memcpy(bfilter->dst_macaddr, efilter->mac_addr.addr_bytes,
3068                        RTE_ETHER_ADDR_LEN);
3069                 bfilter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_MACADDR;
3070                 bfilter->ethertype = efilter->ether_type;
3071                 bfilter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
3072
3073                 filter1 = bnxt_get_l2_filter(bp, bfilter, vnic0);
3074                 if (filter1 == NULL) {
3075                         ret = -EINVAL;
3076                         goto cleanup;
3077                 }
3078                 bfilter->enables |=
3079                         HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID;
3080                 bfilter->fw_l2_filter_id = filter1->fw_l2_filter_id;
3081
3082                 bfilter->dst_id = vnic->fw_vnic_id;
3083
3084                 if (efilter->flags & RTE_ETHTYPE_FLAGS_DROP) {
3085                         bfilter->flags =
3086                                 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_DROP;
3087                 }
3088
3089                 ret = bnxt_hwrm_set_ntuple_filter(bp, bfilter->dst_id, bfilter);
3090                 if (ret)
3091                         goto cleanup;
3092                 STAILQ_INSERT_TAIL(&vnic->filter, bfilter, next);
3093                 break;
3094         case RTE_ETH_FILTER_DELETE:
3095                 filter1 = bnxt_match_and_validate_ether_filter(bp, efilter,
3096                                                         vnic0, vnic, &ret);
3097                 if (ret == -EEXIST) {
3098                         ret = bnxt_hwrm_clear_ntuple_filter(bp, filter1);
3099
3100                         STAILQ_REMOVE(&vnic->filter, filter1, bnxt_filter_info,
3101                                       next);
3102                         bnxt_free_filter(bp, filter1);
3103                 } else if (ret == 0) {
3104                         PMD_DRV_LOG(ERR, "No matching filter found\n");
3105                 }
3106                 break;
3107         default:
3108                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
3109                 ret = -EINVAL;
3110                 goto error;
3111         }
3112         return ret;
3113 cleanup:
3114         bnxt_free_filter(bp, bfilter);
3115 error:
3116         return ret;
3117 }
3118
3119 static inline int
3120 parse_ntuple_filter(struct bnxt *bp,
3121                     struct rte_eth_ntuple_filter *nfilter,
3122                     struct bnxt_filter_info *bfilter)
3123 {
3124         uint32_t en = 0;
3125
3126         if (nfilter->queue >= bp->rx_nr_rings) {
3127                 PMD_DRV_LOG(ERR, "Invalid queue %d\n", nfilter->queue);
3128                 return -EINVAL;
3129         }
3130
3131         switch (nfilter->dst_port_mask) {
3132         case UINT16_MAX:
3133                 bfilter->dst_port_mask = -1;
3134                 bfilter->dst_port = nfilter->dst_port;
3135                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT |
3136                         NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
3137                 break;
3138         default:
3139                 PMD_DRV_LOG(ERR, "invalid dst_port mask.");
3140                 return -EINVAL;
3141         }
3142
3143         bfilter->ip_addr_type = NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4;
3144         en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
3145
3146         switch (nfilter->proto_mask) {
3147         case UINT8_MAX:
3148                 if (nfilter->proto == 17) /* IPPROTO_UDP */
3149                         bfilter->ip_protocol = 17;
3150                 else if (nfilter->proto == 6) /* IPPROTO_TCP */
3151                         bfilter->ip_protocol = 6;
3152                 else
3153                         return -EINVAL;
3154                 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
3155                 break;
3156         default:
3157                 PMD_DRV_LOG(ERR, "invalid protocol mask.");
3158                 return -EINVAL;
3159         }
3160
3161         switch (nfilter->dst_ip_mask) {
3162         case UINT32_MAX:
3163                 bfilter->dst_ipaddr_mask[0] = -1;
3164                 bfilter->dst_ipaddr[0] = nfilter->dst_ip;
3165                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR |
3166                         NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
3167                 break;
3168         default:
3169                 PMD_DRV_LOG(ERR, "invalid dst_ip mask.");
3170                 return -EINVAL;
3171         }
3172
3173         switch (nfilter->src_ip_mask) {
3174         case UINT32_MAX:
3175                 bfilter->src_ipaddr_mask[0] = -1;
3176                 bfilter->src_ipaddr[0] = nfilter->src_ip;
3177                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR |
3178                         NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
3179                 break;
3180         default:
3181                 PMD_DRV_LOG(ERR, "invalid src_ip mask.");
3182                 return -EINVAL;
3183         }
3184
3185         switch (nfilter->src_port_mask) {
3186         case UINT16_MAX:
3187                 bfilter->src_port_mask = -1;
3188                 bfilter->src_port = nfilter->src_port;
3189                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT |
3190                         NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
3191                 break;
3192         default:
3193                 PMD_DRV_LOG(ERR, "invalid src_port mask.");
3194                 return -EINVAL;
3195         }
3196
3197         bfilter->enables = en;
3198         return 0;
3199 }
3200
3201 static struct bnxt_filter_info*
3202 bnxt_match_ntuple_filter(struct bnxt *bp,
3203                          struct bnxt_filter_info *bfilter,
3204                          struct bnxt_vnic_info **mvnic)
3205 {
3206         struct bnxt_filter_info *mfilter = NULL;
3207         int i;
3208
3209         for (i = bp->nr_vnics - 1; i >= 0; i--) {
3210                 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
3211                 STAILQ_FOREACH(mfilter, &vnic->filter, next) {
3212                         if (bfilter->src_ipaddr[0] == mfilter->src_ipaddr[0] &&
3213                             bfilter->src_ipaddr_mask[0] ==
3214                             mfilter->src_ipaddr_mask[0] &&
3215                             bfilter->src_port == mfilter->src_port &&
3216                             bfilter->src_port_mask == mfilter->src_port_mask &&
3217                             bfilter->dst_ipaddr[0] == mfilter->dst_ipaddr[0] &&
3218                             bfilter->dst_ipaddr_mask[0] ==
3219                             mfilter->dst_ipaddr_mask[0] &&
3220                             bfilter->dst_port == mfilter->dst_port &&
3221                             bfilter->dst_port_mask == mfilter->dst_port_mask &&
3222                             bfilter->flags == mfilter->flags &&
3223                             bfilter->enables == mfilter->enables) {
3224                                 if (mvnic)
3225                                         *mvnic = vnic;
3226                                 return mfilter;
3227                         }
3228                 }
3229         }
3230         return NULL;
3231 }
3232
3233 static int
3234 bnxt_cfg_ntuple_filter(struct bnxt *bp,
3235                        struct rte_eth_ntuple_filter *nfilter,
3236                        enum rte_filter_op filter_op)
3237 {
3238         struct bnxt_filter_info *bfilter, *mfilter, *filter1;
3239         struct bnxt_vnic_info *vnic, *vnic0, *mvnic;
3240         int ret;
3241
3242         if (nfilter->flags != RTE_5TUPLE_FLAGS) {
3243                 PMD_DRV_LOG(ERR, "only 5tuple is supported.");
3244                 return -EINVAL;
3245         }
3246
3247         if (nfilter->flags & RTE_NTUPLE_FLAGS_TCP_FLAG) {
3248                 PMD_DRV_LOG(ERR, "Ntuple filter: TCP flags not supported\n");
3249                 return -EINVAL;
3250         }
3251
3252         bfilter = bnxt_get_unused_filter(bp);
3253         if (bfilter == NULL) {
3254                 PMD_DRV_LOG(ERR,
3255                         "Not enough resources for a new filter.\n");
3256                 return -ENOMEM;
3257         }
3258         ret = parse_ntuple_filter(bp, nfilter, bfilter);
3259         if (ret < 0)
3260                 goto free_filter;
3261
3262         vnic = &bp->vnic_info[nfilter->queue];
3263         vnic0 = BNXT_GET_DEFAULT_VNIC(bp);
3264         filter1 = STAILQ_FIRST(&vnic0->filter);
3265         if (filter1 == NULL) {
3266                 ret = -EINVAL;
3267                 goto free_filter;
3268         }
3269
3270         bfilter->dst_id = vnic->fw_vnic_id;
3271         bfilter->fw_l2_filter_id = filter1->fw_l2_filter_id;
3272         bfilter->enables |=
3273                 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID;
3274         bfilter->ethertype = 0x800;
3275         bfilter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
3276
3277         mfilter = bnxt_match_ntuple_filter(bp, bfilter, &mvnic);
3278
3279         if (mfilter != NULL && filter_op == RTE_ETH_FILTER_ADD &&
3280             bfilter->dst_id == mfilter->dst_id) {
3281                 PMD_DRV_LOG(ERR, "filter exists.\n");
3282                 ret = -EEXIST;
3283                 goto free_filter;
3284         } else if (mfilter != NULL && filter_op == RTE_ETH_FILTER_ADD &&
3285                    bfilter->dst_id != mfilter->dst_id) {
3286                 mfilter->dst_id = vnic->fw_vnic_id;
3287                 ret = bnxt_hwrm_set_ntuple_filter(bp, mfilter->dst_id, mfilter);
3288                 STAILQ_REMOVE(&mvnic->filter, mfilter, bnxt_filter_info, next);
3289                 STAILQ_INSERT_TAIL(&vnic->filter, mfilter, next);
3290                 PMD_DRV_LOG(ERR, "filter with matching pattern exists.\n");
3291                 PMD_DRV_LOG(ERR, " Updated it to the new destination queue\n");
3292                 goto free_filter;
3293         }
3294         if (mfilter == NULL && filter_op == RTE_ETH_FILTER_DELETE) {
3295                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
3296                 ret = -ENOENT;
3297                 goto free_filter;
3298         }
3299
3300         if (filter_op == RTE_ETH_FILTER_ADD) {
3301                 bfilter->filter_type = HWRM_CFA_NTUPLE_FILTER;
3302                 ret = bnxt_hwrm_set_ntuple_filter(bp, bfilter->dst_id, bfilter);
3303                 if (ret)
3304                         goto free_filter;
3305                 STAILQ_INSERT_TAIL(&vnic->filter, bfilter, next);
3306         } else {
3307                 if (mfilter == NULL) {
3308                         /* This should not happen. But for Coverity! */
3309                         ret = -ENOENT;
3310                         goto free_filter;
3311                 }
3312                 ret = bnxt_hwrm_clear_ntuple_filter(bp, mfilter);
3313
3314                 STAILQ_REMOVE(&vnic->filter, mfilter, bnxt_filter_info, next);
3315                 bnxt_free_filter(bp, mfilter);
3316                 bnxt_free_filter(bp, bfilter);
3317         }
3318
3319         return 0;
3320 free_filter:
3321         bnxt_free_filter(bp, bfilter);
3322         return ret;
3323 }
3324
3325 static int
3326 bnxt_ntuple_filter(struct rte_eth_dev *dev,
3327                         enum rte_filter_op filter_op,
3328                         void *arg)
3329 {
3330         struct bnxt *bp = dev->data->dev_private;
3331         int ret;
3332
3333         if (filter_op == RTE_ETH_FILTER_NOP)
3334                 return 0;
3335
3336         if (arg == NULL) {
3337                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
3338                             filter_op);
3339                 return -EINVAL;
3340         }
3341
3342         switch (filter_op) {
3343         case RTE_ETH_FILTER_ADD:
3344                 ret = bnxt_cfg_ntuple_filter(bp,
3345                         (struct rte_eth_ntuple_filter *)arg,
3346                         filter_op);
3347                 break;
3348         case RTE_ETH_FILTER_DELETE:
3349                 ret = bnxt_cfg_ntuple_filter(bp,
3350                         (struct rte_eth_ntuple_filter *)arg,
3351                         filter_op);
3352                 break;
3353         default:
3354                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
3355                 ret = -EINVAL;
3356                 break;
3357         }
3358         return ret;
3359 }
3360
3361 static int
3362 bnxt_parse_fdir_filter(struct bnxt *bp,
3363                        struct rte_eth_fdir_filter *fdir,
3364                        struct bnxt_filter_info *filter)
3365 {
3366         enum rte_fdir_mode fdir_mode =
3367                 bp->eth_dev->data->dev_conf.fdir_conf.mode;
3368         struct bnxt_vnic_info *vnic0, *vnic;
3369         struct bnxt_filter_info *filter1;
3370         uint32_t en = 0;
3371         int i;
3372
3373         if (fdir_mode == RTE_FDIR_MODE_PERFECT_TUNNEL)
3374                 return -EINVAL;
3375
3376         filter->l2_ovlan = fdir->input.flow_ext.vlan_tci;
3377         en |= EM_FLOW_ALLOC_INPUT_EN_OVLAN_VID;
3378
3379         switch (fdir->input.flow_type) {
3380         case RTE_ETH_FLOW_IPV4:
3381         case RTE_ETH_FLOW_NONFRAG_IPV4_OTHER:
3382                 /* FALLTHROUGH */
3383                 filter->src_ipaddr[0] = fdir->input.flow.ip4_flow.src_ip;
3384                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
3385                 filter->dst_ipaddr[0] = fdir->input.flow.ip4_flow.dst_ip;
3386                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
3387                 filter->ip_protocol = fdir->input.flow.ip4_flow.proto;
3388                 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
3389                 filter->ip_addr_type =
3390                         NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4;
3391                 filter->src_ipaddr_mask[0] = 0xffffffff;
3392                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
3393                 filter->dst_ipaddr_mask[0] = 0xffffffff;
3394                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
3395                 filter->ethertype = 0x800;
3396                 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
3397                 break;
3398         case RTE_ETH_FLOW_NONFRAG_IPV4_TCP:
3399                 filter->src_port = fdir->input.flow.tcp4_flow.src_port;
3400                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT;
3401                 filter->dst_port = fdir->input.flow.tcp4_flow.dst_port;
3402                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT;
3403                 filter->dst_port_mask = 0xffff;
3404                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
3405                 filter->src_port_mask = 0xffff;
3406                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
3407                 filter->src_ipaddr[0] = fdir->input.flow.tcp4_flow.ip.src_ip;
3408                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
3409                 filter->dst_ipaddr[0] = fdir->input.flow.tcp4_flow.ip.dst_ip;
3410                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
3411                 filter->ip_protocol = 6;
3412                 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
3413                 filter->ip_addr_type =
3414                         NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4;
3415                 filter->src_ipaddr_mask[0] = 0xffffffff;
3416                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
3417                 filter->dst_ipaddr_mask[0] = 0xffffffff;
3418                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
3419                 filter->ethertype = 0x800;
3420                 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
3421                 break;
3422         case RTE_ETH_FLOW_NONFRAG_IPV4_UDP:
3423                 filter->src_port = fdir->input.flow.udp4_flow.src_port;
3424                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT;
3425                 filter->dst_port = fdir->input.flow.udp4_flow.dst_port;
3426                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT;
3427                 filter->dst_port_mask = 0xffff;
3428                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
3429                 filter->src_port_mask = 0xffff;
3430                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
3431                 filter->src_ipaddr[0] = fdir->input.flow.udp4_flow.ip.src_ip;
3432                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
3433                 filter->dst_ipaddr[0] = fdir->input.flow.udp4_flow.ip.dst_ip;
3434                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
3435                 filter->ip_protocol = 17;
3436                 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
3437                 filter->ip_addr_type =
3438                         NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4;
3439                 filter->src_ipaddr_mask[0] = 0xffffffff;
3440                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
3441                 filter->dst_ipaddr_mask[0] = 0xffffffff;
3442                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
3443                 filter->ethertype = 0x800;
3444                 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
3445                 break;
3446         case RTE_ETH_FLOW_IPV6:
3447         case RTE_ETH_FLOW_NONFRAG_IPV6_OTHER:
3448                 /* FALLTHROUGH */
3449                 filter->ip_addr_type =
3450                         NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV6;
3451                 filter->ip_protocol = fdir->input.flow.ipv6_flow.proto;
3452                 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
3453                 rte_memcpy(filter->src_ipaddr,
3454                            fdir->input.flow.ipv6_flow.src_ip, 16);
3455                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
3456                 rte_memcpy(filter->dst_ipaddr,
3457                            fdir->input.flow.ipv6_flow.dst_ip, 16);
3458                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
3459                 memset(filter->dst_ipaddr_mask, 0xff, 16);
3460                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
3461                 memset(filter->src_ipaddr_mask, 0xff, 16);
3462                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
3463                 filter->ethertype = 0x86dd;
3464                 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
3465                 break;
3466         case RTE_ETH_FLOW_NONFRAG_IPV6_TCP:
3467                 filter->src_port = fdir->input.flow.tcp6_flow.src_port;
3468                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT;
3469                 filter->dst_port = fdir->input.flow.tcp6_flow.dst_port;
3470                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT;
3471                 filter->dst_port_mask = 0xffff;
3472                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
3473                 filter->src_port_mask = 0xffff;
3474                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
3475                 filter->ip_addr_type =
3476                         NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV6;
3477                 filter->ip_protocol = fdir->input.flow.tcp6_flow.ip.proto;
3478                 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
3479                 rte_memcpy(filter->src_ipaddr,
3480                            fdir->input.flow.tcp6_flow.ip.src_ip, 16);
3481                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
3482                 rte_memcpy(filter->dst_ipaddr,
3483                            fdir->input.flow.tcp6_flow.ip.dst_ip, 16);
3484                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
3485                 memset(filter->dst_ipaddr_mask, 0xff, 16);
3486                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
3487                 memset(filter->src_ipaddr_mask, 0xff, 16);
3488                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
3489                 filter->ethertype = 0x86dd;
3490                 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
3491                 break;
3492         case RTE_ETH_FLOW_NONFRAG_IPV6_UDP:
3493                 filter->src_port = fdir->input.flow.udp6_flow.src_port;
3494                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT;
3495                 filter->dst_port = fdir->input.flow.udp6_flow.dst_port;
3496                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT;
3497                 filter->dst_port_mask = 0xffff;
3498                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
3499                 filter->src_port_mask = 0xffff;
3500                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
3501                 filter->ip_addr_type =
3502                         NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV6;
3503                 filter->ip_protocol = fdir->input.flow.udp6_flow.ip.proto;
3504                 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
3505                 rte_memcpy(filter->src_ipaddr,
3506                            fdir->input.flow.udp6_flow.ip.src_ip, 16);
3507                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
3508                 rte_memcpy(filter->dst_ipaddr,
3509                            fdir->input.flow.udp6_flow.ip.dst_ip, 16);
3510                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
3511                 memset(filter->dst_ipaddr_mask, 0xff, 16);
3512                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
3513                 memset(filter->src_ipaddr_mask, 0xff, 16);
3514                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
3515                 filter->ethertype = 0x86dd;
3516                 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
3517                 break;
3518         case RTE_ETH_FLOW_L2_PAYLOAD:
3519                 filter->ethertype = fdir->input.flow.l2_flow.ether_type;
3520                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
3521                 break;
3522         case RTE_ETH_FLOW_VXLAN:
3523                 if (fdir->action.behavior == RTE_ETH_FDIR_REJECT)
3524                         return -EINVAL;
3525                 filter->vni = fdir->input.flow.tunnel_flow.tunnel_id;
3526                 filter->tunnel_type =
3527                         CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN;
3528                 en |= HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_TUNNEL_TYPE;
3529                 break;
3530         case RTE_ETH_FLOW_NVGRE:
3531                 if (fdir->action.behavior == RTE_ETH_FDIR_REJECT)
3532                         return -EINVAL;
3533                 filter->vni = fdir->input.flow.tunnel_flow.tunnel_id;
3534                 filter->tunnel_type =
3535                         CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_NVGRE;
3536                 en |= HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_TUNNEL_TYPE;
3537                 break;
3538         case RTE_ETH_FLOW_UNKNOWN:
3539         case RTE_ETH_FLOW_RAW:
3540         case RTE_ETH_FLOW_FRAG_IPV4:
3541         case RTE_ETH_FLOW_NONFRAG_IPV4_SCTP:
3542         case RTE_ETH_FLOW_FRAG_IPV6:
3543         case RTE_ETH_FLOW_NONFRAG_IPV6_SCTP:
3544         case RTE_ETH_FLOW_IPV6_EX:
3545         case RTE_ETH_FLOW_IPV6_TCP_EX:
3546         case RTE_ETH_FLOW_IPV6_UDP_EX:
3547         case RTE_ETH_FLOW_GENEVE:
3548                 /* FALLTHROUGH */
3549         default:
3550                 return -EINVAL;
3551         }
3552
3553         vnic0 = BNXT_GET_DEFAULT_VNIC(bp);
3554         vnic = &bp->vnic_info[fdir->action.rx_queue];
3555         if (vnic == NULL) {
3556                 PMD_DRV_LOG(ERR, "Invalid queue %d\n", fdir->action.rx_queue);
3557                 return -EINVAL;
3558         }
3559
3560         if (fdir_mode == RTE_FDIR_MODE_PERFECT_MAC_VLAN) {
3561                 rte_memcpy(filter->dst_macaddr,
3562                         fdir->input.flow.mac_vlan_flow.mac_addr.addr_bytes, 6);
3563                         en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_MACADDR;
3564         }
3565
3566         if (fdir->action.behavior == RTE_ETH_FDIR_REJECT) {
3567                 filter->flags = HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_DROP;
3568                 filter1 = STAILQ_FIRST(&vnic0->filter);
3569                 //filter1 = bnxt_get_l2_filter(bp, filter, vnic0);
3570         } else {
3571                 filter->dst_id = vnic->fw_vnic_id;
3572                 for (i = 0; i < RTE_ETHER_ADDR_LEN; i++)
3573                         if (filter->dst_macaddr[i] == 0x00)
3574                                 filter1 = STAILQ_FIRST(&vnic0->filter);
3575                         else
3576                                 filter1 = bnxt_get_l2_filter(bp, filter, vnic);
3577         }
3578
3579         if (filter1 == NULL)
3580                 return -EINVAL;
3581
3582         en |= HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID;
3583         filter->fw_l2_filter_id = filter1->fw_l2_filter_id;
3584
3585         filter->enables = en;
3586
3587         return 0;
3588 }
3589
3590 static struct bnxt_filter_info *
3591 bnxt_match_fdir(struct bnxt *bp, struct bnxt_filter_info *nf,
3592                 struct bnxt_vnic_info **mvnic)
3593 {
3594         struct bnxt_filter_info *mf = NULL;
3595         int i;
3596
3597         for (i = bp->nr_vnics - 1; i >= 0; i--) {
3598                 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
3599
3600                 STAILQ_FOREACH(mf, &vnic->filter, next) {
3601                         if (mf->filter_type == nf->filter_type &&
3602                             mf->flags == nf->flags &&
3603                             mf->src_port == nf->src_port &&
3604                             mf->src_port_mask == nf->src_port_mask &&
3605                             mf->dst_port == nf->dst_port &&
3606                             mf->dst_port_mask == nf->dst_port_mask &&
3607                             mf->ip_protocol == nf->ip_protocol &&
3608                             mf->ip_addr_type == nf->ip_addr_type &&
3609                             mf->ethertype == nf->ethertype &&
3610                             mf->vni == nf->vni &&
3611                             mf->tunnel_type == nf->tunnel_type &&
3612                             mf->l2_ovlan == nf->l2_ovlan &&
3613                             mf->l2_ovlan_mask == nf->l2_ovlan_mask &&
3614                             mf->l2_ivlan == nf->l2_ivlan &&
3615                             mf->l2_ivlan_mask == nf->l2_ivlan_mask &&
3616                             !memcmp(mf->l2_addr, nf->l2_addr,
3617                                     RTE_ETHER_ADDR_LEN) &&
3618                             !memcmp(mf->l2_addr_mask, nf->l2_addr_mask,
3619                                     RTE_ETHER_ADDR_LEN) &&
3620                             !memcmp(mf->src_macaddr, nf->src_macaddr,
3621                                     RTE_ETHER_ADDR_LEN) &&
3622                             !memcmp(mf->dst_macaddr, nf->dst_macaddr,
3623                                     RTE_ETHER_ADDR_LEN) &&
3624                             !memcmp(mf->src_ipaddr, nf->src_ipaddr,
3625                                     sizeof(nf->src_ipaddr)) &&
3626                             !memcmp(mf->src_ipaddr_mask, nf->src_ipaddr_mask,
3627                                     sizeof(nf->src_ipaddr_mask)) &&
3628                             !memcmp(mf->dst_ipaddr, nf->dst_ipaddr,
3629                                     sizeof(nf->dst_ipaddr)) &&
3630                             !memcmp(mf->dst_ipaddr_mask, nf->dst_ipaddr_mask,
3631                                     sizeof(nf->dst_ipaddr_mask))) {
3632                                 if (mvnic)
3633                                         *mvnic = vnic;
3634                                 return mf;
3635                         }
3636                 }
3637         }
3638         return NULL;
3639 }
3640
3641 static int
3642 bnxt_fdir_filter(struct rte_eth_dev *dev,
3643                  enum rte_filter_op filter_op,
3644                  void *arg)
3645 {
3646         struct bnxt *bp = dev->data->dev_private;
3647         struct rte_eth_fdir_filter *fdir  = (struct rte_eth_fdir_filter *)arg;
3648         struct bnxt_filter_info *filter, *match;
3649         struct bnxt_vnic_info *vnic, *mvnic;
3650         int ret = 0, i;
3651
3652         if (filter_op == RTE_ETH_FILTER_NOP)
3653                 return 0;
3654
3655         if (arg == NULL && filter_op != RTE_ETH_FILTER_FLUSH)
3656                 return -EINVAL;
3657
3658         switch (filter_op) {
3659         case RTE_ETH_FILTER_ADD:
3660         case RTE_ETH_FILTER_DELETE:
3661                 /* FALLTHROUGH */
3662                 filter = bnxt_get_unused_filter(bp);
3663                 if (filter == NULL) {
3664                         PMD_DRV_LOG(ERR,
3665                                 "Not enough resources for a new flow.\n");
3666                         return -ENOMEM;
3667                 }
3668
3669                 ret = bnxt_parse_fdir_filter(bp, fdir, filter);
3670                 if (ret != 0)
3671                         goto free_filter;
3672                 filter->filter_type = HWRM_CFA_NTUPLE_FILTER;
3673
3674                 if (fdir->action.behavior == RTE_ETH_FDIR_REJECT)
3675                         vnic = &bp->vnic_info[0];
3676                 else
3677                         vnic = &bp->vnic_info[fdir->action.rx_queue];
3678
3679                 match = bnxt_match_fdir(bp, filter, &mvnic);
3680                 if (match != NULL && filter_op == RTE_ETH_FILTER_ADD) {
3681                         if (match->dst_id == vnic->fw_vnic_id) {
3682                                 PMD_DRV_LOG(ERR, "Flow already exists.\n");
3683                                 ret = -EEXIST;
3684                                 goto free_filter;
3685                         } else {
3686                                 match->dst_id = vnic->fw_vnic_id;
3687                                 ret = bnxt_hwrm_set_ntuple_filter(bp,
3688                                                                   match->dst_id,
3689                                                                   match);
3690                                 STAILQ_REMOVE(&mvnic->filter, match,
3691                                               bnxt_filter_info, next);
3692                                 STAILQ_INSERT_TAIL(&vnic->filter, match, next);
3693                                 PMD_DRV_LOG(ERR,
3694                                         "Filter with matching pattern exist\n");
3695                                 PMD_DRV_LOG(ERR,
3696                                         "Updated it to new destination q\n");
3697                                 goto free_filter;
3698                         }
3699                 }
3700                 if (match == NULL && filter_op == RTE_ETH_FILTER_DELETE) {
3701                         PMD_DRV_LOG(ERR, "Flow does not exist.\n");
3702                         ret = -ENOENT;
3703                         goto free_filter;
3704                 }
3705
3706                 if (filter_op == RTE_ETH_FILTER_ADD) {
3707                         ret = bnxt_hwrm_set_ntuple_filter(bp,
3708                                                           filter->dst_id,
3709                                                           filter);
3710                         if (ret)
3711                                 goto free_filter;
3712                         STAILQ_INSERT_TAIL(&vnic->filter, filter, next);
3713                 } else {
3714                         ret = bnxt_hwrm_clear_ntuple_filter(bp, match);
3715                         STAILQ_REMOVE(&vnic->filter, match,
3716                                       bnxt_filter_info, next);
3717                         bnxt_free_filter(bp, match);
3718                         bnxt_free_filter(bp, filter);
3719                 }
3720                 break;
3721         case RTE_ETH_FILTER_FLUSH:
3722                 for (i = bp->nr_vnics - 1; i >= 0; i--) {
3723                         struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
3724
3725                         STAILQ_FOREACH(filter, &vnic->filter, next) {
3726                                 if (filter->filter_type ==
3727                                     HWRM_CFA_NTUPLE_FILTER) {
3728                                         ret =
3729                                         bnxt_hwrm_clear_ntuple_filter(bp,
3730                                                                       filter);
3731                                         STAILQ_REMOVE(&vnic->filter, filter,
3732                                                       bnxt_filter_info, next);
3733                                 }
3734                         }
3735                 }
3736                 return ret;
3737         case RTE_ETH_FILTER_UPDATE:
3738         case RTE_ETH_FILTER_STATS:
3739         case RTE_ETH_FILTER_INFO:
3740                 PMD_DRV_LOG(ERR, "operation %u not implemented", filter_op);
3741                 break;
3742         default:
3743                 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
3744                 ret = -EINVAL;
3745                 break;
3746         }
3747         return ret;
3748
3749 free_filter:
3750         bnxt_free_filter(bp, filter);
3751         return ret;
3752 }
3753
3754 int
3755 bnxt_filter_ctrl_op(struct rte_eth_dev *dev,
3756                     enum rte_filter_type filter_type,
3757                     enum rte_filter_op filter_op, void *arg)
3758 {
3759         struct bnxt *bp = dev->data->dev_private;
3760         int ret = 0;
3761
3762         if (BNXT_ETH_DEV_IS_REPRESENTOR(dev)) {
3763                 struct bnxt_vf_representor *vfr = dev->data->dev_private;
3764                 bp = vfr->parent_dev->data->dev_private;
3765         }
3766
3767         ret = is_bnxt_in_error(bp);
3768         if (ret)
3769                 return ret;
3770
3771         switch (filter_type) {
3772         case RTE_ETH_FILTER_TUNNEL:
3773                 PMD_DRV_LOG(ERR,
3774                         "filter type: %d: To be implemented\n", filter_type);
3775                 break;
3776         case RTE_ETH_FILTER_FDIR:
3777                 ret = bnxt_fdir_filter(dev, filter_op, arg);
3778                 break;
3779         case RTE_ETH_FILTER_NTUPLE:
3780                 ret = bnxt_ntuple_filter(dev, filter_op, arg);
3781                 break;
3782         case RTE_ETH_FILTER_ETHERTYPE:
3783                 ret = bnxt_ethertype_filter(dev, filter_op, arg);
3784                 break;
3785         case RTE_ETH_FILTER_GENERIC:
3786                 if (filter_op != RTE_ETH_FILTER_GET)
3787                         return -EINVAL;
3788                 if (BNXT_TRUFLOW_EN(bp))
3789                         *(const void **)arg = &bnxt_ulp_rte_flow_ops;
3790                 else
3791                         *(const void **)arg = &bnxt_flow_ops;
3792                 break;
3793         default:
3794                 PMD_DRV_LOG(ERR,
3795                         "Filter type (%d) not supported", filter_type);
3796                 ret = -EINVAL;
3797                 break;
3798         }
3799         return ret;
3800 }
3801
3802 static const uint32_t *
3803 bnxt_dev_supported_ptypes_get_op(struct rte_eth_dev *dev)
3804 {
3805         static const uint32_t ptypes[] = {
3806                 RTE_PTYPE_L2_ETHER_VLAN,
3807                 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN,
3808                 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN,
3809                 RTE_PTYPE_L4_ICMP,
3810                 RTE_PTYPE_L4_TCP,
3811                 RTE_PTYPE_L4_UDP,
3812                 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN,
3813                 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN,
3814                 RTE_PTYPE_INNER_L4_ICMP,
3815                 RTE_PTYPE_INNER_L4_TCP,
3816                 RTE_PTYPE_INNER_L4_UDP,
3817                 RTE_PTYPE_UNKNOWN
3818         };
3819
3820         if (!dev->rx_pkt_burst)
3821                 return NULL;
3822
3823         return ptypes;
3824 }
3825
3826 static int bnxt_map_regs(struct bnxt *bp, uint32_t *reg_arr, int count,
3827                          int reg_win)
3828 {
3829         uint32_t reg_base = *reg_arr & 0xfffff000;
3830         uint32_t win_off;
3831         int i;
3832
3833         for (i = 0; i < count; i++) {
3834                 if ((reg_arr[i] & 0xfffff000) != reg_base)
3835                         return -ERANGE;
3836         }
3837         win_off = BNXT_GRCPF_REG_WINDOW_BASE_OUT + (reg_win - 1) * 4;
3838         rte_write32(reg_base, (uint8_t *)bp->bar0 + win_off);
3839         return 0;
3840 }
3841
3842 static int bnxt_map_ptp_regs(struct bnxt *bp)
3843 {
3844         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3845         uint32_t *reg_arr;
3846         int rc, i;
3847
3848         reg_arr = ptp->rx_regs;
3849         rc = bnxt_map_regs(bp, reg_arr, BNXT_PTP_RX_REGS, 5);
3850         if (rc)
3851                 return rc;
3852
3853         reg_arr = ptp->tx_regs;
3854         rc = bnxt_map_regs(bp, reg_arr, BNXT_PTP_TX_REGS, 6);
3855         if (rc)
3856                 return rc;
3857
3858         for (i = 0; i < BNXT_PTP_RX_REGS; i++)
3859                 ptp->rx_mapped_regs[i] = 0x5000 + (ptp->rx_regs[i] & 0xfff);
3860
3861         for (i = 0; i < BNXT_PTP_TX_REGS; i++)
3862                 ptp->tx_mapped_regs[i] = 0x6000 + (ptp->tx_regs[i] & 0xfff);
3863
3864         return 0;
3865 }
3866
3867 static void bnxt_unmap_ptp_regs(struct bnxt *bp)
3868 {
3869         rte_write32(0, (uint8_t *)bp->bar0 +
3870                          BNXT_GRCPF_REG_WINDOW_BASE_OUT + 16);
3871         rte_write32(0, (uint8_t *)bp->bar0 +
3872                          BNXT_GRCPF_REG_WINDOW_BASE_OUT + 20);
3873 }
3874
3875 static uint64_t bnxt_cc_read(struct bnxt *bp)
3876 {
3877         uint64_t ns;
3878
3879         ns = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3880                               BNXT_GRCPF_REG_SYNC_TIME));
3881         ns |= (uint64_t)(rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3882                                           BNXT_GRCPF_REG_SYNC_TIME + 4))) << 32;
3883         return ns;
3884 }
3885
3886 static int bnxt_get_tx_ts(struct bnxt *bp, uint64_t *ts)
3887 {
3888         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3889         uint32_t fifo;
3890
3891         fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3892                                 ptp->tx_mapped_regs[BNXT_PTP_TX_FIFO]));
3893         if (fifo & BNXT_PTP_TX_FIFO_EMPTY)
3894                 return -EAGAIN;
3895
3896         fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3897                                 ptp->tx_mapped_regs[BNXT_PTP_TX_FIFO]));
3898         *ts = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3899                                 ptp->tx_mapped_regs[BNXT_PTP_TX_TS_L]));
3900         *ts |= (uint64_t)rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3901                                 ptp->tx_mapped_regs[BNXT_PTP_TX_TS_H])) << 32;
3902
3903         return 0;
3904 }
3905
3906 static int bnxt_get_rx_ts(struct bnxt *bp, uint64_t *ts)
3907 {
3908         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3909         struct bnxt_pf_info *pf = bp->pf;
3910         uint16_t port_id;
3911         uint32_t fifo;
3912
3913         if (!ptp)
3914                 return -ENODEV;
3915
3916         fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3917                                 ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO]));
3918         if (!(fifo & BNXT_PTP_RX_FIFO_PENDING))
3919                 return -EAGAIN;
3920
3921         port_id = pf->port_id;
3922         rte_write32(1 << port_id, (uint8_t *)bp->bar0 +
3923                ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO_ADV]);
3924
3925         fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3926                                    ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO]));
3927         if (fifo & BNXT_PTP_RX_FIFO_PENDING) {
3928 /*              bnxt_clr_rx_ts(bp);       TBD  */
3929                 return -EBUSY;
3930         }
3931
3932         *ts = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3933                                 ptp->rx_mapped_regs[BNXT_PTP_RX_TS_L]));
3934         *ts |= (uint64_t)rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3935                                 ptp->rx_mapped_regs[BNXT_PTP_RX_TS_H])) << 32;
3936
3937         return 0;
3938 }
3939
3940 static int
3941 bnxt_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
3942 {
3943         uint64_t ns;
3944         struct bnxt *bp = dev->data->dev_private;
3945         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3946
3947         if (!ptp)
3948                 return 0;
3949
3950         ns = rte_timespec_to_ns(ts);
3951         /* Set the timecounters to a new value. */
3952         ptp->tc.nsec = ns;
3953
3954         return 0;
3955 }
3956
3957 static int
3958 bnxt_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
3959 {
3960         struct bnxt *bp = dev->data->dev_private;
3961         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3962         uint64_t ns, systime_cycles = 0;
3963         int rc = 0;
3964
3965         if (!ptp)
3966                 return 0;
3967
3968         if (BNXT_CHIP_THOR(bp))
3969                 rc = bnxt_hwrm_port_ts_query(bp, BNXT_PTP_FLAGS_CURRENT_TIME,
3970                                              &systime_cycles);
3971         else
3972                 systime_cycles = bnxt_cc_read(bp);
3973
3974         ns = rte_timecounter_update(&ptp->tc, systime_cycles);
3975         *ts = rte_ns_to_timespec(ns);
3976
3977         return rc;
3978 }
3979 static int
3980 bnxt_timesync_enable(struct rte_eth_dev *dev)
3981 {
3982         struct bnxt *bp = dev->data->dev_private;
3983         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3984         uint32_t shift = 0;
3985         int rc;
3986
3987         if (!ptp)
3988                 return 0;
3989
3990         ptp->rx_filter = 1;
3991         ptp->tx_tstamp_en = 1;
3992         ptp->rxctl = BNXT_PTP_MSG_EVENTS;
3993
3994         rc = bnxt_hwrm_ptp_cfg(bp);
3995         if (rc)
3996                 return rc;
3997
3998         memset(&ptp->tc, 0, sizeof(struct rte_timecounter));
3999         memset(&ptp->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
4000         memset(&ptp->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
4001
4002         ptp->tc.cc_mask = BNXT_CYCLECOUNTER_MASK;
4003         ptp->tc.cc_shift = shift;
4004         ptp->tc.nsec_mask = (1ULL << shift) - 1;
4005
4006         ptp->rx_tstamp_tc.cc_mask = BNXT_CYCLECOUNTER_MASK;
4007         ptp->rx_tstamp_tc.cc_shift = shift;
4008         ptp->rx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
4009
4010         ptp->tx_tstamp_tc.cc_mask = BNXT_CYCLECOUNTER_MASK;
4011         ptp->tx_tstamp_tc.cc_shift = shift;
4012         ptp->tx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
4013
4014         if (!BNXT_CHIP_THOR(bp))
4015                 bnxt_map_ptp_regs(bp);
4016
4017         return 0;
4018 }
4019
4020 static int
4021 bnxt_timesync_disable(struct rte_eth_dev *dev)
4022 {
4023         struct bnxt *bp = dev->data->dev_private;
4024         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
4025
4026         if (!ptp)
4027                 return 0;
4028
4029         ptp->rx_filter = 0;
4030         ptp->tx_tstamp_en = 0;
4031         ptp->rxctl = 0;
4032
4033         bnxt_hwrm_ptp_cfg(bp);
4034
4035         if (!BNXT_CHIP_THOR(bp))
4036                 bnxt_unmap_ptp_regs(bp);
4037
4038         return 0;
4039 }
4040
4041 static int
4042 bnxt_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
4043                                  struct timespec *timestamp,
4044                                  uint32_t flags __rte_unused)
4045 {
4046         struct bnxt *bp = dev->data->dev_private;
4047         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
4048         uint64_t rx_tstamp_cycles = 0;
4049         uint64_t ns;
4050
4051         if (!ptp)
4052                 return 0;
4053
4054         if (BNXT_CHIP_THOR(bp))
4055                 rx_tstamp_cycles = ptp->rx_timestamp;
4056         else
4057                 bnxt_get_rx_ts(bp, &rx_tstamp_cycles);
4058
4059         ns = rte_timecounter_update(&ptp->rx_tstamp_tc, rx_tstamp_cycles);
4060         *timestamp = rte_ns_to_timespec(ns);
4061         return  0;
4062 }
4063
4064 static int
4065 bnxt_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
4066                                  struct timespec *timestamp)
4067 {
4068         struct bnxt *bp = dev->data->dev_private;
4069         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
4070         uint64_t tx_tstamp_cycles = 0;
4071         uint64_t ns;
4072         int rc = 0;
4073
4074         if (!ptp)
4075                 return 0;
4076
4077         if (BNXT_CHIP_THOR(bp))
4078                 rc = bnxt_hwrm_port_ts_query(bp, BNXT_PTP_FLAGS_PATH_TX,
4079                                              &tx_tstamp_cycles);
4080         else
4081                 rc = bnxt_get_tx_ts(bp, &tx_tstamp_cycles);
4082
4083         ns = rte_timecounter_update(&ptp->tx_tstamp_tc, tx_tstamp_cycles);
4084         *timestamp = rte_ns_to_timespec(ns);
4085
4086         return rc;
4087 }
4088
4089 static int
4090 bnxt_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
4091 {
4092         struct bnxt *bp = dev->data->dev_private;
4093         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
4094
4095         if (!ptp)
4096                 return 0;
4097
4098         ptp->tc.nsec += delta;
4099
4100         return 0;
4101 }
4102
4103 static int
4104 bnxt_get_eeprom_length_op(struct rte_eth_dev *dev)
4105 {
4106         struct bnxt *bp = dev->data->dev_private;
4107         int rc;
4108         uint32_t dir_entries;
4109         uint32_t entry_length;
4110
4111         rc = is_bnxt_in_error(bp);
4112         if (rc)
4113                 return rc;
4114
4115         PMD_DRV_LOG(INFO, PCI_PRI_FMT "\n",
4116                     bp->pdev->addr.domain, bp->pdev->addr.bus,
4117                     bp->pdev->addr.devid, bp->pdev->addr.function);
4118
4119         rc = bnxt_hwrm_nvm_get_dir_info(bp, &dir_entries, &entry_length);
4120         if (rc != 0)
4121                 return rc;
4122
4123         return dir_entries * entry_length;
4124 }
4125
4126 static int
4127 bnxt_get_eeprom_op(struct rte_eth_dev *dev,
4128                 struct rte_dev_eeprom_info *in_eeprom)
4129 {
4130         struct bnxt *bp = dev->data->dev_private;
4131         uint32_t index;
4132         uint32_t offset;
4133         int rc;
4134
4135         rc = is_bnxt_in_error(bp);
4136         if (rc)
4137                 return rc;
4138
4139         PMD_DRV_LOG(INFO, PCI_PRI_FMT " in_eeprom->offset = %d len = %d\n",
4140                     bp->pdev->addr.domain, bp->pdev->addr.bus,
4141                     bp->pdev->addr.devid, bp->pdev->addr.function,
4142                     in_eeprom->offset, in_eeprom->length);
4143
4144         if (in_eeprom->offset == 0) /* special offset value to get directory */
4145                 return bnxt_get_nvram_directory(bp, in_eeprom->length,
4146                                                 in_eeprom->data);
4147
4148         index = in_eeprom->offset >> 24;
4149         offset = in_eeprom->offset & 0xffffff;
4150
4151         if (index != 0)
4152                 return bnxt_hwrm_get_nvram_item(bp, index - 1, offset,
4153                                            in_eeprom->length, in_eeprom->data);
4154
4155         return 0;
4156 }
4157
4158 static bool bnxt_dir_type_is_ape_bin_format(uint16_t dir_type)
4159 {
4160         switch (dir_type) {
4161         case BNX_DIR_TYPE_CHIMP_PATCH:
4162         case BNX_DIR_TYPE_BOOTCODE:
4163         case BNX_DIR_TYPE_BOOTCODE_2:
4164         case BNX_DIR_TYPE_APE_FW:
4165         case BNX_DIR_TYPE_APE_PATCH:
4166         case BNX_DIR_TYPE_KONG_FW:
4167         case BNX_DIR_TYPE_KONG_PATCH:
4168         case BNX_DIR_TYPE_BONO_FW:
4169         case BNX_DIR_TYPE_BONO_PATCH:
4170                 /* FALLTHROUGH */
4171                 return true;
4172         }
4173
4174         return false;
4175 }
4176
4177 static bool bnxt_dir_type_is_other_exec_format(uint16_t dir_type)
4178 {
4179         switch (dir_type) {
4180         case BNX_DIR_TYPE_AVS:
4181         case BNX_DIR_TYPE_EXP_ROM_MBA:
4182         case BNX_DIR_TYPE_PCIE:
4183         case BNX_DIR_TYPE_TSCF_UCODE:
4184         case BNX_DIR_TYPE_EXT_PHY:
4185         case BNX_DIR_TYPE_CCM:
4186         case BNX_DIR_TYPE_ISCSI_BOOT:
4187         case BNX_DIR_TYPE_ISCSI_BOOT_IPV6:
4188         case BNX_DIR_TYPE_ISCSI_BOOT_IPV4N6:
4189                 /* FALLTHROUGH */
4190                 return true;
4191         }
4192
4193         return false;
4194 }
4195
4196 static bool bnxt_dir_type_is_executable(uint16_t dir_type)
4197 {
4198         return bnxt_dir_type_is_ape_bin_format(dir_type) ||
4199                 bnxt_dir_type_is_other_exec_format(dir_type);
4200 }
4201
4202 static int
4203 bnxt_set_eeprom_op(struct rte_eth_dev *dev,
4204                 struct rte_dev_eeprom_info *in_eeprom)
4205 {
4206         struct bnxt *bp = dev->data->dev_private;
4207         uint8_t index, dir_op;
4208         uint16_t type, ext, ordinal, attr;
4209         int rc;
4210
4211         rc = is_bnxt_in_error(bp);
4212         if (rc)
4213                 return rc;
4214
4215         PMD_DRV_LOG(INFO, PCI_PRI_FMT " in_eeprom->offset = %d len = %d\n",
4216                     bp->pdev->addr.domain, bp->pdev->addr.bus,
4217                     bp->pdev->addr.devid, bp->pdev->addr.function,
4218                     in_eeprom->offset, in_eeprom->length);
4219
4220         if (!BNXT_PF(bp)) {
4221                 PMD_DRV_LOG(ERR, "NVM write not supported from a VF\n");
4222                 return -EINVAL;
4223         }
4224
4225         type = in_eeprom->magic >> 16;
4226
4227         if (type == 0xffff) { /* special value for directory operations */
4228                 index = in_eeprom->magic & 0xff;
4229                 dir_op = in_eeprom->magic >> 8;
4230                 if (index == 0)
4231                         return -EINVAL;
4232                 switch (dir_op) {
4233                 case 0x0e: /* erase */
4234                         if (in_eeprom->offset != ~in_eeprom->magic)
4235                                 return -EINVAL;
4236                         return bnxt_hwrm_erase_nvram_directory(bp, index - 1);
4237                 default:
4238                         return -EINVAL;
4239                 }
4240         }
4241
4242         /* Create or re-write an NVM item: */
4243         if (bnxt_dir_type_is_executable(type) == true)
4244                 return -EOPNOTSUPP;
4245         ext = in_eeprom->magic & 0xffff;
4246         ordinal = in_eeprom->offset >> 16;
4247         attr = in_eeprom->offset & 0xffff;
4248
4249         return bnxt_hwrm_flash_nvram(bp, type, ordinal, ext, attr,
4250                                      in_eeprom->data, in_eeprom->length);
4251 }
4252
4253 /*
4254  * Initialization
4255  */
4256
4257 static const struct eth_dev_ops bnxt_dev_ops = {
4258         .dev_infos_get = bnxt_dev_info_get_op,
4259         .dev_close = bnxt_dev_close_op,
4260         .dev_configure = bnxt_dev_configure_op,
4261         .dev_start = bnxt_dev_start_op,
4262         .dev_stop = bnxt_dev_stop_op,
4263         .dev_set_link_up = bnxt_dev_set_link_up_op,
4264         .dev_set_link_down = bnxt_dev_set_link_down_op,
4265         .stats_get = bnxt_stats_get_op,
4266         .stats_reset = bnxt_stats_reset_op,
4267         .rx_queue_setup = bnxt_rx_queue_setup_op,
4268         .rx_queue_release = bnxt_rx_queue_release_op,
4269         .tx_queue_setup = bnxt_tx_queue_setup_op,
4270         .tx_queue_release = bnxt_tx_queue_release_op,
4271         .rx_queue_intr_enable = bnxt_rx_queue_intr_enable_op,
4272         .rx_queue_intr_disable = bnxt_rx_queue_intr_disable_op,
4273         .reta_update = bnxt_reta_update_op,
4274         .reta_query = bnxt_reta_query_op,
4275         .rss_hash_update = bnxt_rss_hash_update_op,
4276         .rss_hash_conf_get = bnxt_rss_hash_conf_get_op,
4277         .link_update = bnxt_link_update_op,
4278         .promiscuous_enable = bnxt_promiscuous_enable_op,
4279         .promiscuous_disable = bnxt_promiscuous_disable_op,
4280         .allmulticast_enable = bnxt_allmulticast_enable_op,
4281         .allmulticast_disable = bnxt_allmulticast_disable_op,
4282         .mac_addr_add = bnxt_mac_addr_add_op,
4283         .mac_addr_remove = bnxt_mac_addr_remove_op,
4284         .flow_ctrl_get = bnxt_flow_ctrl_get_op,
4285         .flow_ctrl_set = bnxt_flow_ctrl_set_op,
4286         .udp_tunnel_port_add  = bnxt_udp_tunnel_port_add_op,
4287         .udp_tunnel_port_del  = bnxt_udp_tunnel_port_del_op,
4288         .vlan_filter_set = bnxt_vlan_filter_set_op,
4289         .vlan_offload_set = bnxt_vlan_offload_set_op,
4290         .vlan_tpid_set = bnxt_vlan_tpid_set_op,
4291         .vlan_pvid_set = bnxt_vlan_pvid_set_op,
4292         .mtu_set = bnxt_mtu_set_op,
4293         .mac_addr_set = bnxt_set_default_mac_addr_op,
4294         .xstats_get = bnxt_dev_xstats_get_op,
4295         .xstats_get_names = bnxt_dev_xstats_get_names_op,
4296         .xstats_reset = bnxt_dev_xstats_reset_op,
4297         .fw_version_get = bnxt_fw_version_get,
4298         .set_mc_addr_list = bnxt_dev_set_mc_addr_list_op,
4299         .rxq_info_get = bnxt_rxq_info_get_op,
4300         .txq_info_get = bnxt_txq_info_get_op,
4301         .rx_burst_mode_get = bnxt_rx_burst_mode_get,
4302         .tx_burst_mode_get = bnxt_tx_burst_mode_get,
4303         .dev_led_on = bnxt_dev_led_on_op,
4304         .dev_led_off = bnxt_dev_led_off_op,
4305         .xstats_get_by_id = bnxt_dev_xstats_get_by_id_op,
4306         .xstats_get_names_by_id = bnxt_dev_xstats_get_names_by_id_op,
4307         .rx_queue_count = bnxt_rx_queue_count_op,
4308         .rx_descriptor_status = bnxt_rx_descriptor_status_op,
4309         .tx_descriptor_status = bnxt_tx_descriptor_status_op,
4310         .rx_queue_start = bnxt_rx_queue_start,
4311         .rx_queue_stop = bnxt_rx_queue_stop,
4312         .tx_queue_start = bnxt_tx_queue_start,
4313         .tx_queue_stop = bnxt_tx_queue_stop,
4314         .filter_ctrl = bnxt_filter_ctrl_op,
4315         .dev_supported_ptypes_get = bnxt_dev_supported_ptypes_get_op,
4316         .get_eeprom_length    = bnxt_get_eeprom_length_op,
4317         .get_eeprom           = bnxt_get_eeprom_op,
4318         .set_eeprom           = bnxt_set_eeprom_op,
4319         .timesync_enable      = bnxt_timesync_enable,
4320         .timesync_disable     = bnxt_timesync_disable,
4321         .timesync_read_time   = bnxt_timesync_read_time,
4322         .timesync_write_time   = bnxt_timesync_write_time,
4323         .timesync_adjust_time = bnxt_timesync_adjust_time,
4324         .timesync_read_rx_timestamp = bnxt_timesync_read_rx_timestamp,
4325         .timesync_read_tx_timestamp = bnxt_timesync_read_tx_timestamp,
4326 };
4327
4328 static uint32_t bnxt_map_reset_regs(struct bnxt *bp, uint32_t reg)
4329 {
4330         uint32_t offset;
4331
4332         /* Only pre-map the reset GRC registers using window 3 */
4333         rte_write32(reg & 0xfffff000, (uint8_t *)bp->bar0 +
4334                     BNXT_GRCPF_REG_WINDOW_BASE_OUT + 8);
4335
4336         offset = BNXT_GRCP_WINDOW_3_BASE + (reg & 0xffc);
4337
4338         return offset;
4339 }
4340
4341 int bnxt_map_fw_health_status_regs(struct bnxt *bp)
4342 {
4343         struct bnxt_error_recovery_info *info = bp->recovery_info;
4344         uint32_t reg_base = 0xffffffff;
4345         int i;
4346
4347         /* Only pre-map the monitoring GRC registers using window 2 */
4348         for (i = 0; i < BNXT_FW_STATUS_REG_CNT; i++) {
4349                 uint32_t reg = info->status_regs[i];
4350
4351                 if (BNXT_FW_STATUS_REG_TYPE(reg) != BNXT_FW_STATUS_REG_TYPE_GRC)
4352                         continue;
4353
4354                 if (reg_base == 0xffffffff)
4355                         reg_base = reg & 0xfffff000;
4356                 if ((reg & 0xfffff000) != reg_base)
4357                         return -ERANGE;
4358
4359                 /* Use mask 0xffc as the Lower 2 bits indicates
4360                  * address space location
4361                  */
4362                 info->mapped_status_regs[i] = BNXT_GRCP_WINDOW_2_BASE +
4363                                                 (reg & 0xffc);
4364         }
4365
4366         if (reg_base == 0xffffffff)
4367                 return 0;
4368
4369         rte_write32(reg_base, (uint8_t *)bp->bar0 +
4370                     BNXT_GRCPF_REG_WINDOW_BASE_OUT + 4);
4371
4372         return 0;
4373 }
4374
4375 static void bnxt_write_fw_reset_reg(struct bnxt *bp, uint32_t index)
4376 {
4377         struct bnxt_error_recovery_info *info = bp->recovery_info;
4378         uint32_t delay = info->delay_after_reset[index];
4379         uint32_t val = info->reset_reg_val[index];
4380         uint32_t reg = info->reset_reg[index];
4381         uint32_t type, offset;
4382
4383         type = BNXT_FW_STATUS_REG_TYPE(reg);
4384         offset = BNXT_FW_STATUS_REG_OFF(reg);
4385
4386         switch (type) {
4387         case BNXT_FW_STATUS_REG_TYPE_CFG:
4388                 rte_pci_write_config(bp->pdev, &val, sizeof(val), offset);
4389                 break;
4390         case BNXT_FW_STATUS_REG_TYPE_GRC:
4391                 offset = bnxt_map_reset_regs(bp, offset);
4392                 rte_write32(val, (uint8_t *)bp->bar0 + offset);
4393                 break;
4394         case BNXT_FW_STATUS_REG_TYPE_BAR0:
4395                 rte_write32(val, (uint8_t *)bp->bar0 + offset);
4396                 break;
4397         }
4398         /* wait on a specific interval of time until core reset is complete */
4399         if (delay)
4400                 rte_delay_ms(delay);
4401 }
4402
4403 static void bnxt_dev_cleanup(struct bnxt *bp)
4404 {
4405         bnxt_set_hwrm_link_config(bp, false);
4406         bp->link_info->link_up = 0;
4407         if (bp->eth_dev->data->dev_started)
4408                 bnxt_dev_stop_op(bp->eth_dev);
4409
4410         bnxt_uninit_resources(bp, true);
4411 }
4412
4413 static int bnxt_restore_vlan_filters(struct bnxt *bp)
4414 {
4415         struct rte_eth_dev *dev = bp->eth_dev;
4416         struct rte_vlan_filter_conf *vfc;
4417         int vidx, vbit, rc;
4418         uint16_t vlan_id;
4419
4420         for (vlan_id = 1; vlan_id <= RTE_ETHER_MAX_VLAN_ID; vlan_id++) {
4421                 vfc = &dev->data->vlan_filter_conf;
4422                 vidx = vlan_id / 64;
4423                 vbit = vlan_id % 64;
4424
4425                 /* Each bit corresponds to a VLAN id */
4426                 if (vfc->ids[vidx] & (UINT64_C(1) << vbit)) {
4427                         rc = bnxt_add_vlan_filter(bp, vlan_id);
4428                         if (rc)
4429                                 return rc;
4430                 }
4431         }
4432
4433         return 0;
4434 }
4435
4436 static int bnxt_restore_mac_filters(struct bnxt *bp)
4437 {
4438         struct rte_eth_dev *dev = bp->eth_dev;
4439         struct rte_eth_dev_info dev_info;
4440         struct rte_ether_addr *addr;
4441         uint64_t pool_mask;
4442         uint32_t pool = 0;
4443         uint16_t i;
4444         int rc;
4445
4446         if (BNXT_VF(bp) & !BNXT_VF_IS_TRUSTED(bp))
4447                 return 0;
4448
4449         rc = bnxt_dev_info_get_op(dev, &dev_info);
4450         if (rc)
4451                 return rc;
4452
4453         /* replay MAC address configuration */
4454         for (i = 1; i < dev_info.max_mac_addrs; i++) {
4455                 addr = &dev->data->mac_addrs[i];
4456
4457                 /* skip zero address */
4458                 if (rte_is_zero_ether_addr(addr))
4459                         continue;
4460
4461                 pool = 0;
4462                 pool_mask = dev->data->mac_pool_sel[i];
4463
4464                 do {
4465                         if (pool_mask & 1ULL) {
4466                                 rc = bnxt_mac_addr_add_op(dev, addr, i, pool);
4467                                 if (rc)
4468                                         return rc;
4469                         }
4470                         pool_mask >>= 1;
4471                         pool++;
4472                 } while (pool_mask);
4473         }
4474
4475         return 0;
4476 }
4477
4478 static int bnxt_restore_filters(struct bnxt *bp)
4479 {
4480         struct rte_eth_dev *dev = bp->eth_dev;
4481         int ret = 0;
4482
4483         if (dev->data->all_multicast) {
4484                 ret = bnxt_allmulticast_enable_op(dev);
4485                 if (ret)
4486                         return ret;
4487         }
4488         if (dev->data->promiscuous) {
4489                 ret = bnxt_promiscuous_enable_op(dev);
4490                 if (ret)
4491                         return ret;
4492         }
4493
4494         ret = bnxt_restore_mac_filters(bp);
4495         if (ret)
4496                 return ret;
4497
4498         ret = bnxt_restore_vlan_filters(bp);
4499         /* TODO restore other filters as well */
4500         return ret;
4501 }
4502
4503 static void bnxt_dev_recover(void *arg)
4504 {
4505         struct bnxt *bp = arg;
4506         int timeout = bp->fw_reset_max_msecs;
4507         int rc = 0;
4508
4509         /* Clear Error flag so that device re-init should happen */
4510         bp->flags &= ~BNXT_FLAG_FATAL_ERROR;
4511
4512         do {
4513                 rc = bnxt_hwrm_ver_get(bp, SHORT_HWRM_CMD_TIMEOUT);
4514                 if (rc == 0)
4515                         break;
4516                 rte_delay_ms(BNXT_FW_READY_WAIT_INTERVAL);
4517                 timeout -= BNXT_FW_READY_WAIT_INTERVAL;
4518         } while (rc && timeout);
4519
4520         if (rc) {
4521                 PMD_DRV_LOG(ERR, "FW is not Ready after reset\n");
4522                 goto err;
4523         }
4524
4525         rc = bnxt_init_resources(bp, true);
4526         if (rc) {
4527                 PMD_DRV_LOG(ERR,
4528                             "Failed to initialize resources after reset\n");
4529                 goto err;
4530         }
4531         /* clear reset flag as the device is initialized now */
4532         bp->flags &= ~BNXT_FLAG_FW_RESET;
4533
4534         rc = bnxt_dev_start_op(bp->eth_dev);
4535         if (rc) {
4536                 PMD_DRV_LOG(ERR, "Failed to start port after reset\n");
4537                 goto err_start;
4538         }
4539
4540         rc = bnxt_restore_filters(bp);
4541         if (rc)
4542                 goto err_start;
4543
4544         PMD_DRV_LOG(INFO, "Recovered from FW reset\n");
4545         return;
4546 err_start:
4547         bnxt_dev_stop_op(bp->eth_dev);
4548 err:
4549         bp->flags |= BNXT_FLAG_FATAL_ERROR;
4550         bnxt_uninit_resources(bp, false);
4551         PMD_DRV_LOG(ERR, "Failed to recover from FW reset\n");
4552 }
4553
4554 void bnxt_dev_reset_and_resume(void *arg)
4555 {
4556         struct bnxt *bp = arg;
4557         int rc;
4558
4559         bnxt_dev_cleanup(bp);
4560
4561         bnxt_wait_for_device_shutdown(bp);
4562
4563         rc = rte_eal_alarm_set(US_PER_MS * bp->fw_reset_min_msecs,
4564                                bnxt_dev_recover, (void *)bp);
4565         if (rc)
4566                 PMD_DRV_LOG(ERR, "Error setting recovery alarm");
4567 }
4568
4569 uint32_t bnxt_read_fw_status_reg(struct bnxt *bp, uint32_t index)
4570 {
4571         struct bnxt_error_recovery_info *info = bp->recovery_info;
4572         uint32_t reg = info->status_regs[index];
4573         uint32_t type, offset, val = 0;
4574
4575         type = BNXT_FW_STATUS_REG_TYPE(reg);
4576         offset = BNXT_FW_STATUS_REG_OFF(reg);
4577
4578         switch (type) {
4579         case BNXT_FW_STATUS_REG_TYPE_CFG:
4580                 rte_pci_read_config(bp->pdev, &val, sizeof(val), offset);
4581                 break;
4582         case BNXT_FW_STATUS_REG_TYPE_GRC:
4583                 offset = info->mapped_status_regs[index];
4584                 /* FALLTHROUGH */
4585         case BNXT_FW_STATUS_REG_TYPE_BAR0:
4586                 val = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
4587                                        offset));
4588                 break;
4589         }
4590
4591         return val;
4592 }
4593
4594 static int bnxt_fw_reset_all(struct bnxt *bp)
4595 {
4596         struct bnxt_error_recovery_info *info = bp->recovery_info;
4597         uint32_t i;
4598         int rc = 0;
4599
4600         if (info->flags & BNXT_FLAG_ERROR_RECOVERY_HOST) {
4601                 /* Reset through master function driver */
4602                 for (i = 0; i < info->reg_array_cnt; i++)
4603                         bnxt_write_fw_reset_reg(bp, i);
4604                 /* Wait for time specified by FW after triggering reset */
4605                 rte_delay_ms(info->master_func_wait_period_after_reset);
4606         } else if (info->flags & BNXT_FLAG_ERROR_RECOVERY_CO_CPU) {
4607                 /* Reset with the help of Kong processor */
4608                 rc = bnxt_hwrm_fw_reset(bp);
4609                 if (rc)
4610                         PMD_DRV_LOG(ERR, "Failed to reset FW\n");
4611         }
4612
4613         return rc;
4614 }
4615
4616 static void bnxt_fw_reset_cb(void *arg)
4617 {
4618         struct bnxt *bp = arg;
4619         struct bnxt_error_recovery_info *info = bp->recovery_info;
4620         int rc = 0;
4621
4622         /* Only Master function can do FW reset */
4623         if (bnxt_is_master_func(bp) &&
4624             bnxt_is_recovery_enabled(bp)) {
4625                 rc = bnxt_fw_reset_all(bp);
4626                 if (rc) {
4627                         PMD_DRV_LOG(ERR, "Adapter recovery failed\n");
4628                         return;
4629                 }
4630         }
4631
4632         /* if recovery method is ERROR_RECOVERY_CO_CPU, KONG will send
4633          * EXCEPTION_FATAL_ASYNC event to all the functions
4634          * (including MASTER FUNC). After receiving this Async, all the active
4635          * drivers should treat this case as FW initiated recovery
4636          */
4637         if (info->flags & BNXT_FLAG_ERROR_RECOVERY_HOST) {
4638                 bp->fw_reset_min_msecs = BNXT_MIN_FW_READY_TIMEOUT;
4639                 bp->fw_reset_max_msecs = BNXT_MAX_FW_RESET_TIMEOUT;
4640
4641                 /* To recover from error */
4642                 rte_eal_alarm_set(US_PER_MS, bnxt_dev_reset_and_resume,
4643                                   (void *)bp);
4644         }
4645 }
4646
4647 /* Driver should poll FW heartbeat, reset_counter with the frequency
4648  * advertised by FW in HWRM_ERROR_RECOVERY_QCFG.
4649  * When the driver detects heartbeat stop or change in reset_counter,
4650  * it has to trigger a reset to recover from the error condition.
4651  * A “master PF” is the function who will have the privilege to
4652  * initiate the chimp reset. The master PF will be elected by the
4653  * firmware and will be notified through async message.
4654  */
4655 static void bnxt_check_fw_health(void *arg)
4656 {
4657         struct bnxt *bp = arg;
4658         struct bnxt_error_recovery_info *info = bp->recovery_info;
4659         uint32_t val = 0, wait_msec;
4660
4661         if (!info || !bnxt_is_recovery_enabled(bp) ||
4662             is_bnxt_in_error(bp))
4663                 return;
4664
4665         val = bnxt_read_fw_status_reg(bp, BNXT_FW_HEARTBEAT_CNT_REG);
4666         if (val == info->last_heart_beat)
4667                 goto reset;
4668
4669         info->last_heart_beat = val;
4670
4671         val = bnxt_read_fw_status_reg(bp, BNXT_FW_RECOVERY_CNT_REG);
4672         if (val != info->last_reset_counter)
4673                 goto reset;
4674
4675         info->last_reset_counter = val;
4676
4677         rte_eal_alarm_set(US_PER_MS * info->driver_polling_freq,
4678                           bnxt_check_fw_health, (void *)bp);
4679
4680         return;
4681 reset:
4682         /* Stop DMA to/from device */
4683         bp->flags |= BNXT_FLAG_FATAL_ERROR;
4684         bp->flags |= BNXT_FLAG_FW_RESET;
4685
4686         PMD_DRV_LOG(ERR, "Detected FW dead condition\n");
4687
4688         if (bnxt_is_master_func(bp))
4689                 wait_msec = info->master_func_wait_period;
4690         else
4691                 wait_msec = info->normal_func_wait_period;
4692
4693         rte_eal_alarm_set(US_PER_MS * wait_msec,
4694                           bnxt_fw_reset_cb, (void *)bp);
4695 }
4696
4697 void bnxt_schedule_fw_health_check(struct bnxt *bp)
4698 {
4699         uint32_t polling_freq;
4700
4701         if (!bnxt_is_recovery_enabled(bp))
4702                 return;
4703
4704         if (bp->flags & BNXT_FLAG_FW_HEALTH_CHECK_SCHEDULED)
4705                 return;
4706
4707         polling_freq = bp->recovery_info->driver_polling_freq;
4708
4709         rte_eal_alarm_set(US_PER_MS * polling_freq,
4710                           bnxt_check_fw_health, (void *)bp);
4711         bp->flags |= BNXT_FLAG_FW_HEALTH_CHECK_SCHEDULED;
4712 }
4713
4714 static void bnxt_cancel_fw_health_check(struct bnxt *bp)
4715 {
4716         if (!bnxt_is_recovery_enabled(bp))
4717                 return;
4718
4719         rte_eal_alarm_cancel(bnxt_check_fw_health, (void *)bp);
4720         bp->flags &= ~BNXT_FLAG_FW_HEALTH_CHECK_SCHEDULED;
4721 }
4722
4723 static bool bnxt_vf_pciid(uint16_t device_id)
4724 {
4725         switch (device_id) {
4726         case BROADCOM_DEV_ID_57304_VF:
4727         case BROADCOM_DEV_ID_57406_VF:
4728         case BROADCOM_DEV_ID_5731X_VF:
4729         case BROADCOM_DEV_ID_5741X_VF:
4730         case BROADCOM_DEV_ID_57414_VF:
4731         case BROADCOM_DEV_ID_STRATUS_NIC_VF1:
4732         case BROADCOM_DEV_ID_STRATUS_NIC_VF2:
4733         case BROADCOM_DEV_ID_58802_VF:
4734         case BROADCOM_DEV_ID_57500_VF1:
4735         case BROADCOM_DEV_ID_57500_VF2:
4736                 /* FALLTHROUGH */
4737                 return true;
4738         default:
4739                 return false;
4740         }
4741 }
4742
4743 static bool bnxt_thor_device(uint16_t device_id)
4744 {
4745         switch (device_id) {
4746         case BROADCOM_DEV_ID_57508:
4747         case BROADCOM_DEV_ID_57504:
4748         case BROADCOM_DEV_ID_57502:
4749         case BROADCOM_DEV_ID_57508_MF1:
4750         case BROADCOM_DEV_ID_57504_MF1:
4751         case BROADCOM_DEV_ID_57502_MF1:
4752         case BROADCOM_DEV_ID_57508_MF2:
4753         case BROADCOM_DEV_ID_57504_MF2:
4754         case BROADCOM_DEV_ID_57502_MF2:
4755         case BROADCOM_DEV_ID_57500_VF1:
4756         case BROADCOM_DEV_ID_57500_VF2:
4757                 /* FALLTHROUGH */
4758                 return true;
4759         default:
4760                 return false;
4761         }
4762 }
4763
4764 bool bnxt_stratus_device(struct bnxt *bp)
4765 {
4766         uint16_t device_id = bp->pdev->id.device_id;
4767
4768         switch (device_id) {
4769         case BROADCOM_DEV_ID_STRATUS_NIC:
4770         case BROADCOM_DEV_ID_STRATUS_NIC_VF1:
4771         case BROADCOM_DEV_ID_STRATUS_NIC_VF2:
4772                 /* FALLTHROUGH */
4773                 return true;
4774         default:
4775                 return false;
4776         }
4777 }
4778
4779 static int bnxt_init_board(struct rte_eth_dev *eth_dev)
4780 {
4781         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
4782         struct bnxt *bp = eth_dev->data->dev_private;
4783
4784         /* enable device (incl. PCI PM wakeup), and bus-mastering */
4785         bp->bar0 = (void *)pci_dev->mem_resource[0].addr;
4786         bp->doorbell_base = (void *)pci_dev->mem_resource[2].addr;
4787         if (!bp->bar0 || !bp->doorbell_base) {
4788                 PMD_DRV_LOG(ERR, "Unable to access Hardware\n");
4789                 return -ENODEV;
4790         }
4791
4792         bp->eth_dev = eth_dev;
4793         bp->pdev = pci_dev;
4794
4795         return 0;
4796 }
4797
4798 static int bnxt_alloc_ctx_mem_blk(struct bnxt *bp,
4799                                   struct bnxt_ctx_pg_info *ctx_pg,
4800                                   uint32_t mem_size,
4801                                   const char *suffix,
4802                                   uint16_t idx)
4803 {
4804         struct bnxt_ring_mem_info *rmem = &ctx_pg->ring_mem;
4805         const struct rte_memzone *mz = NULL;
4806         char mz_name[RTE_MEMZONE_NAMESIZE];
4807         rte_iova_t mz_phys_addr;
4808         uint64_t valid_bits = 0;
4809         uint32_t sz;
4810         int i;
4811
4812         if (!mem_size)
4813                 return 0;
4814
4815         rmem->nr_pages = RTE_ALIGN_MUL_CEIL(mem_size, BNXT_PAGE_SIZE) /
4816                          BNXT_PAGE_SIZE;
4817         rmem->page_size = BNXT_PAGE_SIZE;
4818         rmem->pg_arr = ctx_pg->ctx_pg_arr;
4819         rmem->dma_arr = ctx_pg->ctx_dma_arr;
4820         rmem->flags = BNXT_RMEM_VALID_PTE_FLAG;
4821
4822         valid_bits = PTU_PTE_VALID;
4823
4824         if (rmem->nr_pages > 1) {
4825                 snprintf(mz_name, RTE_MEMZONE_NAMESIZE,
4826                          "bnxt_ctx_pg_tbl%s_%x_%d",
4827                          suffix, idx, bp->eth_dev->data->port_id);
4828                 mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0;
4829                 mz = rte_memzone_lookup(mz_name);
4830                 if (!mz) {
4831                         mz = rte_memzone_reserve_aligned(mz_name,
4832                                                 rmem->nr_pages * 8,
4833                                                 SOCKET_ID_ANY,
4834                                                 RTE_MEMZONE_2MB |
4835                                                 RTE_MEMZONE_SIZE_HINT_ONLY |
4836                                                 RTE_MEMZONE_IOVA_CONTIG,
4837                                                 BNXT_PAGE_SIZE);
4838                         if (mz == NULL)
4839                                 return -ENOMEM;
4840                 }
4841
4842                 memset(mz->addr, 0, mz->len);
4843                 mz_phys_addr = mz->iova;
4844
4845                 rmem->pg_tbl = mz->addr;
4846                 rmem->pg_tbl_map = mz_phys_addr;
4847                 rmem->pg_tbl_mz = mz;
4848         }
4849
4850         snprintf(mz_name, RTE_MEMZONE_NAMESIZE, "bnxt_ctx_%s_%x_%d",
4851                  suffix, idx, bp->eth_dev->data->port_id);
4852         mz = rte_memzone_lookup(mz_name);
4853         if (!mz) {
4854                 mz = rte_memzone_reserve_aligned(mz_name,
4855                                                  mem_size,
4856                                                  SOCKET_ID_ANY,
4857                                                  RTE_MEMZONE_1GB |
4858                                                  RTE_MEMZONE_SIZE_HINT_ONLY |
4859                                                  RTE_MEMZONE_IOVA_CONTIG,
4860                                                  BNXT_PAGE_SIZE);
4861                 if (mz == NULL)
4862                         return -ENOMEM;
4863         }
4864
4865         memset(mz->addr, 0, mz->len);
4866         mz_phys_addr = mz->iova;
4867
4868         for (sz = 0, i = 0; sz < mem_size; sz += BNXT_PAGE_SIZE, i++) {
4869                 rmem->pg_arr[i] = ((char *)mz->addr) + sz;
4870                 rmem->dma_arr[i] = mz_phys_addr + sz;
4871
4872                 if (rmem->nr_pages > 1) {
4873                         if (i == rmem->nr_pages - 2 &&
4874                             (rmem->flags & BNXT_RMEM_RING_PTE_FLAG))
4875                                 valid_bits |= PTU_PTE_NEXT_TO_LAST;
4876                         else if (i == rmem->nr_pages - 1 &&
4877                                  (rmem->flags & BNXT_RMEM_RING_PTE_FLAG))
4878                                 valid_bits |= PTU_PTE_LAST;
4879
4880                         rmem->pg_tbl[i] = rte_cpu_to_le_64(rmem->dma_arr[i] |
4881                                                            valid_bits);
4882                 }
4883         }
4884
4885         rmem->mz = mz;
4886         if (rmem->vmem_size)
4887                 rmem->vmem = (void **)mz->addr;
4888         rmem->dma_arr[0] = mz_phys_addr;
4889         return 0;
4890 }
4891
4892 static void bnxt_free_ctx_mem(struct bnxt *bp)
4893 {
4894         int i;
4895
4896         if (!bp->ctx || !(bp->ctx->flags & BNXT_CTX_FLAG_INITED))
4897                 return;
4898
4899         bp->ctx->flags &= ~BNXT_CTX_FLAG_INITED;
4900         rte_memzone_free(bp->ctx->qp_mem.ring_mem.mz);
4901         rte_memzone_free(bp->ctx->srq_mem.ring_mem.mz);
4902         rte_memzone_free(bp->ctx->cq_mem.ring_mem.mz);
4903         rte_memzone_free(bp->ctx->vnic_mem.ring_mem.mz);
4904         rte_memzone_free(bp->ctx->stat_mem.ring_mem.mz);
4905         rte_memzone_free(bp->ctx->qp_mem.ring_mem.pg_tbl_mz);
4906         rte_memzone_free(bp->ctx->srq_mem.ring_mem.pg_tbl_mz);
4907         rte_memzone_free(bp->ctx->cq_mem.ring_mem.pg_tbl_mz);
4908         rte_memzone_free(bp->ctx->vnic_mem.ring_mem.pg_tbl_mz);
4909         rte_memzone_free(bp->ctx->stat_mem.ring_mem.pg_tbl_mz);
4910
4911         for (i = 0; i < bp->ctx->tqm_fp_rings_count + 1; i++) {
4912                 if (bp->ctx->tqm_mem[i])
4913                         rte_memzone_free(bp->ctx->tqm_mem[i]->ring_mem.mz);
4914         }
4915
4916         rte_free(bp->ctx);
4917         bp->ctx = NULL;
4918 }
4919
4920 #define bnxt_roundup(x, y)   ((((x) + ((y) - 1)) / (y)) * (y))
4921
4922 #define min_t(type, x, y) ({                    \
4923         type __min1 = (x);                      \
4924         type __min2 = (y);                      \
4925         __min1 < __min2 ? __min1 : __min2; })
4926
4927 #define max_t(type, x, y) ({                    \
4928         type __max1 = (x);                      \
4929         type __max2 = (y);                      \
4930         __max1 > __max2 ? __max1 : __max2; })
4931
4932 #define clamp_t(type, _x, min, max)     min_t(type, max_t(type, _x, min), max)
4933
4934 int bnxt_alloc_ctx_mem(struct bnxt *bp)
4935 {
4936         struct bnxt_ctx_pg_info *ctx_pg;
4937         struct bnxt_ctx_mem_info *ctx;
4938         uint32_t mem_size, ena, entries;
4939         uint32_t entries_sp, min;
4940         int i, rc;
4941
4942         rc = bnxt_hwrm_func_backing_store_qcaps(bp);
4943         if (rc) {
4944                 PMD_DRV_LOG(ERR, "Query context mem capability failed\n");
4945                 return rc;
4946         }
4947         ctx = bp->ctx;
4948         if (!ctx || (ctx->flags & BNXT_CTX_FLAG_INITED))
4949                 return 0;
4950
4951         ctx_pg = &ctx->qp_mem;
4952         ctx_pg->entries = ctx->qp_min_qp1_entries + ctx->qp_max_l2_entries;
4953         mem_size = ctx->qp_entry_size * ctx_pg->entries;
4954         rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "qp_mem", 0);
4955         if (rc)
4956                 return rc;
4957
4958         ctx_pg = &ctx->srq_mem;
4959         ctx_pg->entries = ctx->srq_max_l2_entries;
4960         mem_size = ctx->srq_entry_size * ctx_pg->entries;
4961         rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "srq_mem", 0);
4962         if (rc)
4963                 return rc;
4964
4965         ctx_pg = &ctx->cq_mem;
4966         ctx_pg->entries = ctx->cq_max_l2_entries;
4967         mem_size = ctx->cq_entry_size * ctx_pg->entries;
4968         rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "cq_mem", 0);
4969         if (rc)
4970                 return rc;
4971
4972         ctx_pg = &ctx->vnic_mem;
4973         ctx_pg->entries = ctx->vnic_max_vnic_entries +
4974                 ctx->vnic_max_ring_table_entries;
4975         mem_size = ctx->vnic_entry_size * ctx_pg->entries;
4976         rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "vnic_mem", 0);
4977         if (rc)
4978                 return rc;
4979
4980         ctx_pg = &ctx->stat_mem;
4981         ctx_pg->entries = ctx->stat_max_entries;
4982         mem_size = ctx->stat_entry_size * ctx_pg->entries;
4983         rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "stat_mem", 0);
4984         if (rc)
4985                 return rc;
4986
4987         min = ctx->tqm_min_entries_per_ring;
4988
4989         entries_sp = ctx->qp_max_l2_entries +
4990                      ctx->vnic_max_vnic_entries +
4991                      2 * ctx->qp_min_qp1_entries + min;
4992         entries_sp = bnxt_roundup(entries_sp, ctx->tqm_entries_multiple);
4993
4994         entries = ctx->qp_max_l2_entries + ctx->qp_min_qp1_entries;
4995         entries = bnxt_roundup(entries, ctx->tqm_entries_multiple);
4996         entries = clamp_t(uint32_t, entries, min,
4997                           ctx->tqm_max_entries_per_ring);
4998         for (i = 0, ena = 0; i < ctx->tqm_fp_rings_count + 1; i++) {
4999                 ctx_pg = ctx->tqm_mem[i];
5000                 ctx_pg->entries = i ? entries : entries_sp;
5001                 mem_size = ctx->tqm_entry_size * ctx_pg->entries;
5002                 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "tqm_mem", i);
5003                 if (rc)
5004                         return rc;
5005                 ena |= HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_SP << i;
5006         }
5007
5008         ena |= FUNC_BACKING_STORE_CFG_INPUT_DFLT_ENABLES;
5009         rc = bnxt_hwrm_func_backing_store_cfg(bp, ena);
5010         if (rc)
5011                 PMD_DRV_LOG(ERR,
5012                             "Failed to configure context mem: rc = %d\n", rc);
5013         else
5014                 ctx->flags |= BNXT_CTX_FLAG_INITED;
5015
5016         return rc;
5017 }
5018
5019 static int bnxt_alloc_stats_mem(struct bnxt *bp)
5020 {
5021         struct rte_pci_device *pci_dev = bp->pdev;
5022         char mz_name[RTE_MEMZONE_NAMESIZE];
5023         const struct rte_memzone *mz = NULL;
5024         uint32_t total_alloc_len;
5025         rte_iova_t mz_phys_addr;
5026
5027         if (pci_dev->id.device_id == BROADCOM_DEV_ID_NS2)
5028                 return 0;
5029
5030         snprintf(mz_name, RTE_MEMZONE_NAMESIZE,
5031                  "bnxt_" PCI_PRI_FMT "-%s", pci_dev->addr.domain,
5032                  pci_dev->addr.bus, pci_dev->addr.devid,
5033                  pci_dev->addr.function, "rx_port_stats");
5034         mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0;
5035         mz = rte_memzone_lookup(mz_name);
5036         total_alloc_len =
5037                 RTE_CACHE_LINE_ROUNDUP(sizeof(struct rx_port_stats) +
5038                                        sizeof(struct rx_port_stats_ext) + 512);
5039         if (!mz) {
5040                 mz = rte_memzone_reserve(mz_name, total_alloc_len,
5041                                          SOCKET_ID_ANY,
5042                                          RTE_MEMZONE_2MB |
5043                                          RTE_MEMZONE_SIZE_HINT_ONLY |
5044                                          RTE_MEMZONE_IOVA_CONTIG);
5045                 if (mz == NULL)
5046                         return -ENOMEM;
5047         }
5048         memset(mz->addr, 0, mz->len);
5049         mz_phys_addr = mz->iova;
5050
5051         bp->rx_mem_zone = (const void *)mz;
5052         bp->hw_rx_port_stats = mz->addr;
5053         bp->hw_rx_port_stats_map = mz_phys_addr;
5054
5055         snprintf(mz_name, RTE_MEMZONE_NAMESIZE,
5056                  "bnxt_" PCI_PRI_FMT "-%s", pci_dev->addr.domain,
5057                  pci_dev->addr.bus, pci_dev->addr.devid,
5058                  pci_dev->addr.function, "tx_port_stats");
5059         mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0;
5060         mz = rte_memzone_lookup(mz_name);
5061         total_alloc_len =
5062                 RTE_CACHE_LINE_ROUNDUP(sizeof(struct tx_port_stats) +
5063                                        sizeof(struct tx_port_stats_ext) + 512);
5064         if (!mz) {
5065                 mz = rte_memzone_reserve(mz_name,
5066                                          total_alloc_len,
5067                                          SOCKET_ID_ANY,
5068                                          RTE_MEMZONE_2MB |
5069                                          RTE_MEMZONE_SIZE_HINT_ONLY |
5070                                          RTE_MEMZONE_IOVA_CONTIG);
5071                 if (mz == NULL)
5072                         return -ENOMEM;
5073         }
5074         memset(mz->addr, 0, mz->len);
5075         mz_phys_addr = mz->iova;
5076
5077         bp->tx_mem_zone = (const void *)mz;
5078         bp->hw_tx_port_stats = mz->addr;
5079         bp->hw_tx_port_stats_map = mz_phys_addr;
5080         bp->flags |= BNXT_FLAG_PORT_STATS;
5081
5082         /* Display extended statistics if FW supports it */
5083         if (bp->hwrm_spec_code < HWRM_SPEC_CODE_1_8_4 ||
5084             bp->hwrm_spec_code == HWRM_SPEC_CODE_1_9_0 ||
5085             !(bp->flags & BNXT_FLAG_EXT_STATS_SUPPORTED))
5086                 return 0;
5087
5088         bp->hw_rx_port_stats_ext = (void *)
5089                 ((uint8_t *)bp->hw_rx_port_stats +
5090                  sizeof(struct rx_port_stats));
5091         bp->hw_rx_port_stats_ext_map = bp->hw_rx_port_stats_map +
5092                 sizeof(struct rx_port_stats);
5093         bp->flags |= BNXT_FLAG_EXT_RX_PORT_STATS;
5094
5095         if (bp->hwrm_spec_code < HWRM_SPEC_CODE_1_9_2 ||
5096             bp->flags & BNXT_FLAG_EXT_STATS_SUPPORTED) {
5097                 bp->hw_tx_port_stats_ext = (void *)
5098                         ((uint8_t *)bp->hw_tx_port_stats +
5099                          sizeof(struct tx_port_stats));
5100                 bp->hw_tx_port_stats_ext_map =
5101                         bp->hw_tx_port_stats_map +
5102                         sizeof(struct tx_port_stats);
5103                 bp->flags |= BNXT_FLAG_EXT_TX_PORT_STATS;
5104         }
5105
5106         return 0;
5107 }
5108
5109 static int bnxt_setup_mac_addr(struct rte_eth_dev *eth_dev)
5110 {
5111         struct bnxt *bp = eth_dev->data->dev_private;
5112         int rc = 0;
5113
5114         eth_dev->data->mac_addrs = rte_zmalloc("bnxt_mac_addr_tbl",
5115                                                RTE_ETHER_ADDR_LEN *
5116                                                bp->max_l2_ctx,
5117                                                0);
5118         if (eth_dev->data->mac_addrs == NULL) {
5119                 PMD_DRV_LOG(ERR, "Failed to alloc MAC addr tbl\n");
5120                 return -ENOMEM;
5121         }
5122
5123         if (!BNXT_HAS_DFLT_MAC_SET(bp)) {
5124                 if (BNXT_PF(bp))
5125                         return -EINVAL;
5126
5127                 /* Generate a random MAC address, if none was assigned by PF */
5128                 PMD_DRV_LOG(INFO, "VF MAC address not assigned by Host PF\n");
5129                 bnxt_eth_hw_addr_random(bp->mac_addr);
5130                 PMD_DRV_LOG(INFO,
5131                             "Assign random MAC:%02X:%02X:%02X:%02X:%02X:%02X\n",
5132                             bp->mac_addr[0], bp->mac_addr[1], bp->mac_addr[2],
5133                             bp->mac_addr[3], bp->mac_addr[4], bp->mac_addr[5]);
5134
5135                 rc = bnxt_hwrm_set_mac(bp);
5136                 if (rc)
5137                         return rc;
5138         }
5139
5140         /* Copy the permanent MAC from the FUNC_QCAPS response */
5141         memcpy(&eth_dev->data->mac_addrs[0], bp->mac_addr, RTE_ETHER_ADDR_LEN);
5142
5143         return rc;
5144 }
5145
5146 static int bnxt_restore_dflt_mac(struct bnxt *bp)
5147 {
5148         int rc = 0;
5149
5150         /* MAC is already configured in FW */
5151         if (BNXT_HAS_DFLT_MAC_SET(bp))
5152                 return 0;
5153
5154         /* Restore the old MAC configured */
5155         rc = bnxt_hwrm_set_mac(bp);
5156         if (rc)
5157                 PMD_DRV_LOG(ERR, "Failed to restore MAC address\n");
5158
5159         return rc;
5160 }
5161
5162 static void bnxt_config_vf_req_fwd(struct bnxt *bp)
5163 {
5164         if (!BNXT_PF(bp))
5165                 return;
5166
5167 #define ALLOW_FUNC(x)   \
5168         { \
5169                 uint32_t arg = (x); \
5170                 bp->pf->vf_req_fwd[((arg) >> 5)] &= \
5171                 ~rte_cpu_to_le_32(1 << ((arg) & 0x1f)); \
5172         }
5173
5174         /* Forward all requests if firmware is new enough */
5175         if (((bp->fw_ver >= ((20 << 24) | (6 << 16) | (100 << 8))) &&
5176              (bp->fw_ver < ((20 << 24) | (7 << 16)))) ||
5177             ((bp->fw_ver >= ((20 << 24) | (8 << 16))))) {
5178                 memset(bp->pf->vf_req_fwd, 0xff, sizeof(bp->pf->vf_req_fwd));
5179         } else {
5180                 PMD_DRV_LOG(WARNING,
5181                             "Firmware too old for VF mailbox functionality\n");
5182                 memset(bp->pf->vf_req_fwd, 0, sizeof(bp->pf->vf_req_fwd));
5183         }
5184
5185         /*
5186          * The following are used for driver cleanup. If we disallow these,
5187          * VF drivers can't clean up cleanly.
5188          */
5189         ALLOW_FUNC(HWRM_FUNC_DRV_UNRGTR);
5190         ALLOW_FUNC(HWRM_VNIC_FREE);
5191         ALLOW_FUNC(HWRM_RING_FREE);
5192         ALLOW_FUNC(HWRM_RING_GRP_FREE);
5193         ALLOW_FUNC(HWRM_VNIC_RSS_COS_LB_CTX_FREE);
5194         ALLOW_FUNC(HWRM_CFA_L2_FILTER_FREE);
5195         ALLOW_FUNC(HWRM_STAT_CTX_FREE);
5196         ALLOW_FUNC(HWRM_PORT_PHY_QCFG);
5197         ALLOW_FUNC(HWRM_VNIC_TPA_CFG);
5198 }
5199
5200 uint16_t
5201 bnxt_get_svif(uint16_t port_id, bool func_svif,
5202               enum bnxt_ulp_intf_type type)
5203 {
5204         struct rte_eth_dev *eth_dev;
5205         struct bnxt *bp;
5206
5207         eth_dev = &rte_eth_devices[port_id];
5208         if (BNXT_ETH_DEV_IS_REPRESENTOR(eth_dev)) {
5209                 struct bnxt_vf_representor *vfr = eth_dev->data->dev_private;
5210                 if (!vfr)
5211                         return 0;
5212
5213                 if (type == BNXT_ULP_INTF_TYPE_VF_REP)
5214                         return vfr->svif;
5215
5216                 eth_dev = vfr->parent_dev;
5217         }
5218
5219         bp = eth_dev->data->dev_private;
5220
5221         return func_svif ? bp->func_svif : bp->port_svif;
5222 }
5223
5224 uint16_t
5225 bnxt_get_vnic_id(uint16_t port, enum bnxt_ulp_intf_type type)
5226 {
5227         struct rte_eth_dev *eth_dev;
5228         struct bnxt_vnic_info *vnic;
5229         struct bnxt *bp;
5230
5231         eth_dev = &rte_eth_devices[port];
5232         if (BNXT_ETH_DEV_IS_REPRESENTOR(eth_dev)) {
5233                 struct bnxt_vf_representor *vfr = eth_dev->data->dev_private;
5234                 if (!vfr)
5235                         return 0;
5236
5237                 if (type == BNXT_ULP_INTF_TYPE_VF_REP)
5238                         return vfr->dflt_vnic_id;
5239
5240                 eth_dev = vfr->parent_dev;
5241         }
5242
5243         bp = eth_dev->data->dev_private;
5244
5245         vnic = BNXT_GET_DEFAULT_VNIC(bp);
5246
5247         return vnic->fw_vnic_id;
5248 }
5249
5250 uint16_t
5251 bnxt_get_fw_func_id(uint16_t port, enum bnxt_ulp_intf_type type)
5252 {
5253         struct rte_eth_dev *eth_dev;
5254         struct bnxt *bp;
5255
5256         eth_dev = &rte_eth_devices[port];
5257         if (BNXT_ETH_DEV_IS_REPRESENTOR(eth_dev)) {
5258                 struct bnxt_vf_representor *vfr = eth_dev->data->dev_private;
5259                 if (!vfr)
5260                         return 0;
5261
5262                 if (type == BNXT_ULP_INTF_TYPE_VF_REP)
5263                         return vfr->fw_fid;
5264
5265                 eth_dev = vfr->parent_dev;
5266         }
5267
5268         bp = eth_dev->data->dev_private;
5269
5270         return bp->fw_fid;
5271 }
5272
5273 enum bnxt_ulp_intf_type
5274 bnxt_get_interface_type(uint16_t port)
5275 {
5276         struct rte_eth_dev *eth_dev;
5277         struct bnxt *bp;
5278
5279         eth_dev = &rte_eth_devices[port];
5280         if (BNXT_ETH_DEV_IS_REPRESENTOR(eth_dev))
5281                 return BNXT_ULP_INTF_TYPE_VF_REP;
5282
5283         bp = eth_dev->data->dev_private;
5284         if (BNXT_PF(bp))
5285                 return BNXT_ULP_INTF_TYPE_PF;
5286         else if (BNXT_VF_IS_TRUSTED(bp))
5287                 return BNXT_ULP_INTF_TYPE_TRUSTED_VF;
5288         else if (BNXT_VF(bp))
5289                 return BNXT_ULP_INTF_TYPE_VF;
5290
5291         return BNXT_ULP_INTF_TYPE_INVALID;
5292 }
5293
5294 uint16_t
5295 bnxt_get_phy_port_id(uint16_t port_id)
5296 {
5297         struct bnxt_vf_representor *vfr;
5298         struct rte_eth_dev *eth_dev;
5299         struct bnxt *bp;
5300
5301         eth_dev = &rte_eth_devices[port_id];
5302         if (BNXT_ETH_DEV_IS_REPRESENTOR(eth_dev)) {
5303                 vfr = eth_dev->data->dev_private;
5304                 if (!vfr)
5305                         return 0;
5306
5307                 eth_dev = vfr->parent_dev;
5308         }
5309
5310         bp = eth_dev->data->dev_private;
5311
5312         return BNXT_PF(bp) ? bp->pf->port_id : bp->parent->port_id;
5313 }
5314
5315 uint16_t
5316 bnxt_get_parif(uint16_t port_id, enum bnxt_ulp_intf_type type)
5317 {
5318         struct rte_eth_dev *eth_dev;
5319         struct bnxt *bp;
5320
5321         eth_dev = &rte_eth_devices[port_id];
5322         if (BNXT_ETH_DEV_IS_REPRESENTOR(eth_dev)) {
5323                 struct bnxt_vf_representor *vfr = eth_dev->data->dev_private;
5324                 if (!vfr)
5325                         return 0;
5326
5327                 if (type == BNXT_ULP_INTF_TYPE_VF_REP)
5328                         return vfr->fw_fid - 1;
5329
5330                 eth_dev = vfr->parent_dev;
5331         }
5332
5333         bp = eth_dev->data->dev_private;
5334
5335         return BNXT_PF(bp) ? bp->fw_fid - 1 : bp->parent->fid - 1;
5336 }
5337
5338 uint16_t
5339 bnxt_get_vport(uint16_t port_id)
5340 {
5341         return (1 << bnxt_get_phy_port_id(port_id));
5342 }
5343
5344 static void bnxt_alloc_error_recovery_info(struct bnxt *bp)
5345 {
5346         struct bnxt_error_recovery_info *info = bp->recovery_info;
5347
5348         if (info) {
5349                 if (!(bp->fw_cap & BNXT_FW_CAP_HCOMM_FW_STATUS))
5350                         memset(info, 0, sizeof(*info));
5351                 return;
5352         }
5353
5354         if (!(bp->fw_cap & BNXT_FW_CAP_ERROR_RECOVERY))
5355                 return;
5356
5357         info = rte_zmalloc("bnxt_hwrm_error_recovery_qcfg",
5358                            sizeof(*info), 0);
5359         if (!info)
5360                 bp->fw_cap &= ~BNXT_FW_CAP_ERROR_RECOVERY;
5361
5362         bp->recovery_info = info;
5363 }
5364
5365 static void bnxt_check_fw_status(struct bnxt *bp)
5366 {
5367         uint32_t fw_status;
5368
5369         if (!(bp->recovery_info &&
5370               (bp->fw_cap & BNXT_FW_CAP_HCOMM_FW_STATUS)))
5371                 return;
5372
5373         fw_status = bnxt_read_fw_status_reg(bp, BNXT_FW_STATUS_REG);
5374         if (fw_status != BNXT_FW_STATUS_HEALTHY)
5375                 PMD_DRV_LOG(ERR, "Firmware not responding, status: %#x\n",
5376                             fw_status);
5377 }
5378
5379 static int bnxt_map_hcomm_fw_status_reg(struct bnxt *bp)
5380 {
5381         struct bnxt_error_recovery_info *info = bp->recovery_info;
5382         uint32_t status_loc;
5383         uint32_t sig_ver;
5384
5385         rte_write32(HCOMM_STATUS_STRUCT_LOC, (uint8_t *)bp->bar0 +
5386                     BNXT_GRCPF_REG_WINDOW_BASE_OUT + 4);
5387         sig_ver = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
5388                                    BNXT_GRCP_WINDOW_2_BASE +
5389                                    offsetof(struct hcomm_status,
5390                                             sig_ver)));
5391         /* If the signature is absent, then FW does not support this feature */
5392         if ((sig_ver & HCOMM_STATUS_SIGNATURE_MASK) !=
5393             HCOMM_STATUS_SIGNATURE_VAL)
5394                 return 0;
5395
5396         if (!info) {
5397                 info = rte_zmalloc("bnxt_hwrm_error_recovery_qcfg",
5398                                    sizeof(*info), 0);
5399                 if (!info)
5400                         return -ENOMEM;
5401                 bp->recovery_info = info;
5402         } else {
5403                 memset(info, 0, sizeof(*info));
5404         }
5405
5406         status_loc = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
5407                                       BNXT_GRCP_WINDOW_2_BASE +
5408                                       offsetof(struct hcomm_status,
5409                                                fw_status_loc)));
5410
5411         /* Only pre-map the FW health status GRC register */
5412         if (BNXT_FW_STATUS_REG_TYPE(status_loc) != BNXT_FW_STATUS_REG_TYPE_GRC)
5413                 return 0;
5414
5415         info->status_regs[BNXT_FW_STATUS_REG] = status_loc;
5416         info->mapped_status_regs[BNXT_FW_STATUS_REG] =
5417                 BNXT_GRCP_WINDOW_2_BASE + (status_loc & BNXT_GRCP_OFFSET_MASK);
5418
5419         rte_write32((status_loc & BNXT_GRCP_BASE_MASK), (uint8_t *)bp->bar0 +
5420                     BNXT_GRCPF_REG_WINDOW_BASE_OUT + 4);
5421
5422         bp->fw_cap |= BNXT_FW_CAP_HCOMM_FW_STATUS;
5423
5424         return 0;
5425 }
5426
5427 static int bnxt_init_fw(struct bnxt *bp)
5428 {
5429         uint16_t mtu;
5430         int rc = 0;
5431
5432         bp->fw_cap = 0;
5433
5434         rc = bnxt_map_hcomm_fw_status_reg(bp);
5435         if (rc)
5436                 return rc;
5437
5438         rc = bnxt_hwrm_ver_get(bp, DFLT_HWRM_CMD_TIMEOUT);
5439         if (rc) {
5440                 bnxt_check_fw_status(bp);
5441                 return rc;
5442         }
5443
5444         rc = bnxt_hwrm_func_reset(bp);
5445         if (rc)
5446                 return -EIO;
5447
5448         rc = bnxt_hwrm_vnic_qcaps(bp);
5449         if (rc)
5450                 return rc;
5451
5452         rc = bnxt_hwrm_queue_qportcfg(bp);
5453         if (rc)
5454                 return rc;
5455
5456         /* Get the MAX capabilities for this function.
5457          * This function also allocates context memory for TQM rings and
5458          * informs the firmware about this allocated backing store memory.
5459          */
5460         rc = bnxt_hwrm_func_qcaps(bp);
5461         if (rc)
5462                 return rc;
5463
5464         rc = bnxt_hwrm_func_qcfg(bp, &mtu);
5465         if (rc)
5466                 return rc;
5467
5468         bnxt_hwrm_port_mac_qcfg(bp);
5469
5470         bnxt_hwrm_parent_pf_qcfg(bp);
5471
5472         bnxt_hwrm_port_phy_qcaps(bp);
5473
5474         bnxt_alloc_error_recovery_info(bp);
5475         /* Get the adapter error recovery support info */
5476         rc = bnxt_hwrm_error_recovery_qcfg(bp);
5477         if (rc)
5478                 bp->fw_cap &= ~BNXT_FW_CAP_ERROR_RECOVERY;
5479
5480         bnxt_hwrm_port_led_qcaps(bp);
5481
5482         return 0;
5483 }
5484
5485 static int
5486 bnxt_init_locks(struct bnxt *bp)
5487 {
5488         int err;
5489
5490         err = pthread_mutex_init(&bp->flow_lock, NULL);
5491         if (err) {
5492                 PMD_DRV_LOG(ERR, "Unable to initialize flow_lock\n");
5493                 return err;
5494         }
5495
5496         err = pthread_mutex_init(&bp->def_cp_lock, NULL);
5497         if (err)
5498                 PMD_DRV_LOG(ERR, "Unable to initialize def_cp_lock\n");
5499         return err;
5500 }
5501
5502 static int bnxt_init_resources(struct bnxt *bp, bool reconfig_dev)
5503 {
5504         int rc = 0;
5505
5506         rc = bnxt_init_fw(bp);
5507         if (rc)
5508                 return rc;
5509
5510         if (!reconfig_dev) {
5511                 rc = bnxt_setup_mac_addr(bp->eth_dev);
5512                 if (rc)
5513                         return rc;
5514         } else {
5515                 rc = bnxt_restore_dflt_mac(bp);
5516                 if (rc)
5517                         return rc;
5518         }
5519
5520         bnxt_config_vf_req_fwd(bp);
5521
5522         rc = bnxt_hwrm_func_driver_register(bp);
5523         if (rc) {
5524                 PMD_DRV_LOG(ERR, "Failed to register driver");
5525                 return -EBUSY;
5526         }
5527
5528         if (BNXT_PF(bp)) {
5529                 if (bp->pdev->max_vfs) {
5530                         rc = bnxt_hwrm_allocate_vfs(bp, bp->pdev->max_vfs);
5531                         if (rc) {
5532                                 PMD_DRV_LOG(ERR, "Failed to allocate VFs\n");
5533                                 return rc;
5534                         }
5535                 } else {
5536                         rc = bnxt_hwrm_allocate_pf_only(bp);
5537                         if (rc) {
5538                                 PMD_DRV_LOG(ERR,
5539                                             "Failed to allocate PF resources");
5540                                 return rc;
5541                         }
5542                 }
5543         }
5544
5545         rc = bnxt_alloc_mem(bp, reconfig_dev);
5546         if (rc)
5547                 return rc;
5548
5549         rc = bnxt_setup_int(bp);
5550         if (rc)
5551                 return rc;
5552
5553         rc = bnxt_request_int(bp);
5554         if (rc)
5555                 return rc;
5556
5557         rc = bnxt_init_ctx_mem(bp);
5558         if (rc) {
5559                 PMD_DRV_LOG(ERR, "Failed to init adv_flow_counters\n");
5560                 return rc;
5561         }
5562
5563         rc = bnxt_init_locks(bp);
5564         if (rc)
5565                 return rc;
5566
5567         return 0;
5568 }
5569
5570 static int
5571 bnxt_parse_devarg_truflow(__rte_unused const char *key,
5572                           const char *value, void *opaque_arg)
5573 {
5574         struct bnxt *bp = opaque_arg;
5575         unsigned long truflow;
5576         char *end = NULL;
5577
5578         if (!value || !opaque_arg) {
5579                 PMD_DRV_LOG(ERR,
5580                             "Invalid parameter passed to truflow devargs.\n");
5581                 return -EINVAL;
5582         }
5583
5584         truflow = strtoul(value, &end, 10);
5585         if (end == NULL || *end != '\0' ||
5586             (truflow == ULONG_MAX && errno == ERANGE)) {
5587                 PMD_DRV_LOG(ERR,
5588                             "Invalid parameter passed to truflow devargs.\n");
5589                 return -EINVAL;
5590         }
5591
5592         if (BNXT_DEVARG_TRUFLOW_INVALID(truflow)) {
5593                 PMD_DRV_LOG(ERR,
5594                             "Invalid value passed to truflow devargs.\n");
5595                 return -EINVAL;
5596         }
5597
5598         bp->flags |= BNXT_FLAG_TRUFLOW_EN;
5599         if (BNXT_TRUFLOW_EN(bp))
5600                 PMD_DRV_LOG(INFO, "Host-based truflow feature enabled.\n");
5601
5602         return 0;
5603 }
5604
5605 static int
5606 bnxt_parse_devarg_flow_xstat(__rte_unused const char *key,
5607                              const char *value, void *opaque_arg)
5608 {
5609         struct bnxt *bp = opaque_arg;
5610         unsigned long flow_xstat;
5611         char *end = NULL;
5612
5613         if (!value || !opaque_arg) {
5614                 PMD_DRV_LOG(ERR,
5615                             "Invalid parameter passed to flow_xstat devarg.\n");
5616                 return -EINVAL;
5617         }
5618
5619         flow_xstat = strtoul(value, &end, 10);
5620         if (end == NULL || *end != '\0' ||
5621             (flow_xstat == ULONG_MAX && errno == ERANGE)) {
5622                 PMD_DRV_LOG(ERR,
5623                             "Invalid parameter passed to flow_xstat devarg.\n");
5624                 return -EINVAL;
5625         }
5626
5627         if (BNXT_DEVARG_FLOW_XSTAT_INVALID(flow_xstat)) {
5628                 PMD_DRV_LOG(ERR,
5629                             "Invalid value passed to flow_xstat devarg.\n");
5630                 return -EINVAL;
5631         }
5632
5633         bp->flags |= BNXT_FLAG_FLOW_XSTATS_EN;
5634         if (BNXT_FLOW_XSTATS_EN(bp))
5635                 PMD_DRV_LOG(INFO, "flow_xstat feature enabled.\n");
5636
5637         return 0;
5638 }
5639
5640 static int
5641 bnxt_parse_devarg_max_num_kflows(__rte_unused const char *key,
5642                                         const char *value, void *opaque_arg)
5643 {
5644         struct bnxt *bp = opaque_arg;
5645         unsigned long max_num_kflows;
5646         char *end = NULL;
5647
5648         if (!value || !opaque_arg) {
5649                 PMD_DRV_LOG(ERR,
5650                         "Invalid parameter passed to max_num_kflows devarg.\n");
5651                 return -EINVAL;
5652         }
5653
5654         max_num_kflows = strtoul(value, &end, 10);
5655         if (end == NULL || *end != '\0' ||
5656                 (max_num_kflows == ULONG_MAX && errno == ERANGE)) {
5657                 PMD_DRV_LOG(ERR,
5658                         "Invalid parameter passed to max_num_kflows devarg.\n");
5659                 return -EINVAL;
5660         }
5661
5662         if (bnxt_devarg_max_num_kflow_invalid(max_num_kflows)) {
5663                 PMD_DRV_LOG(ERR,
5664                         "Invalid value passed to max_num_kflows devarg.\n");
5665                 return -EINVAL;
5666         }
5667
5668         bp->max_num_kflows = max_num_kflows;
5669         if (bp->max_num_kflows)
5670                 PMD_DRV_LOG(INFO, "max_num_kflows set as %ldK.\n",
5671                                 max_num_kflows);
5672
5673         return 0;
5674 }
5675
5676 static void
5677 bnxt_parse_dev_args(struct bnxt *bp, struct rte_devargs *devargs)
5678 {
5679         struct rte_kvargs *kvlist;
5680
5681         if (devargs == NULL)
5682                 return;
5683
5684         kvlist = rte_kvargs_parse(devargs->args, bnxt_dev_args);
5685         if (kvlist == NULL)
5686                 return;
5687
5688         /*
5689          * Handler for "truflow" devarg.
5690          * Invoked as for ex: "-w 0000:00:0d.0,host-based-truflow=1"
5691          */
5692         rte_kvargs_process(kvlist, BNXT_DEVARG_TRUFLOW,
5693                            bnxt_parse_devarg_truflow, bp);
5694
5695         /*
5696          * Handler for "flow_xstat" devarg.
5697          * Invoked as for ex: "-w 0000:00:0d.0,flow_xstat=1"
5698          */
5699         rte_kvargs_process(kvlist, BNXT_DEVARG_FLOW_XSTAT,
5700                            bnxt_parse_devarg_flow_xstat, bp);
5701
5702         /*
5703          * Handler for "max_num_kflows" devarg.
5704          * Invoked as for ex: "-w 000:00:0d.0,max_num_kflows=32"
5705          */
5706         rte_kvargs_process(kvlist, BNXT_DEVARG_MAX_NUM_KFLOWS,
5707                            bnxt_parse_devarg_max_num_kflows, bp);
5708
5709         rte_kvargs_free(kvlist);
5710 }
5711
5712 static int bnxt_alloc_switch_domain(struct bnxt *bp)
5713 {
5714         int rc = 0;
5715
5716         if (BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp)) {
5717                 rc = rte_eth_switch_domain_alloc(&bp->switch_domain_id);
5718                 if (rc)
5719                         PMD_DRV_LOG(ERR,
5720                                     "Failed to alloc switch domain: %d\n", rc);
5721                 else
5722                         PMD_DRV_LOG(INFO,
5723                                     "Switch domain allocated %d\n",
5724                                     bp->switch_domain_id);
5725         }
5726
5727         return rc;
5728 }
5729
5730 static int
5731 bnxt_dev_init(struct rte_eth_dev *eth_dev, void *params __rte_unused)
5732 {
5733         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
5734         static int version_printed;
5735         struct bnxt *bp;
5736         int rc;
5737
5738         if (version_printed++ == 0)
5739                 PMD_DRV_LOG(INFO, "%s\n", bnxt_version);
5740
5741         eth_dev->dev_ops = &bnxt_dev_ops;
5742         eth_dev->rx_pkt_burst = &bnxt_recv_pkts;
5743         eth_dev->tx_pkt_burst = &bnxt_xmit_pkts;
5744
5745         /*
5746          * For secondary processes, we don't initialise any further
5747          * as primary has already done this work.
5748          */
5749         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
5750                 return 0;
5751
5752         rte_eth_copy_pci_info(eth_dev, pci_dev);
5753
5754         bp = eth_dev->data->dev_private;
5755
5756         /* Parse dev arguments passed on when starting the DPDK application. */
5757         bnxt_parse_dev_args(bp, pci_dev->device.devargs);
5758
5759         bp->flags &= ~BNXT_FLAG_RX_VECTOR_PKT_MODE;
5760
5761         if (bnxt_vf_pciid(pci_dev->id.device_id))
5762                 bp->flags |= BNXT_FLAG_VF;
5763
5764         if (bnxt_thor_device(pci_dev->id.device_id))
5765                 bp->flags |= BNXT_FLAG_THOR_CHIP;
5766
5767         if (pci_dev->id.device_id == BROADCOM_DEV_ID_58802 ||
5768             pci_dev->id.device_id == BROADCOM_DEV_ID_58804 ||
5769             pci_dev->id.device_id == BROADCOM_DEV_ID_58808 ||
5770             pci_dev->id.device_id == BROADCOM_DEV_ID_58802_VF)
5771                 bp->flags |= BNXT_FLAG_STINGRAY;
5772
5773         rc = bnxt_init_board(eth_dev);
5774         if (rc) {
5775                 PMD_DRV_LOG(ERR,
5776                             "Failed to initialize board rc: %x\n", rc);
5777                 return rc;
5778         }
5779
5780         rc = bnxt_alloc_pf_info(bp);
5781         if (rc)
5782                 goto error_free;
5783
5784         rc = bnxt_alloc_link_info(bp);
5785         if (rc)
5786                 goto error_free;
5787
5788         rc = bnxt_alloc_parent_info(bp);
5789         if (rc)
5790                 goto error_free;
5791
5792         rc = bnxt_alloc_hwrm_resources(bp);
5793         if (rc) {
5794                 PMD_DRV_LOG(ERR,
5795                             "Failed to allocate hwrm resource rc: %x\n", rc);
5796                 goto error_free;
5797         }
5798         rc = bnxt_alloc_leds_info(bp);
5799         if (rc)
5800                 goto error_free;
5801
5802         rc = bnxt_alloc_cos_queues(bp);
5803         if (rc)
5804                 goto error_free;
5805
5806         rc = bnxt_init_resources(bp, false);
5807         if (rc)
5808                 goto error_free;
5809
5810         rc = bnxt_alloc_stats_mem(bp);
5811         if (rc)
5812                 goto error_free;
5813
5814         bnxt_alloc_switch_domain(bp);
5815
5816         /* Pass the information to the rte_eth_dev_close() that it should also
5817          * release the private port resources.
5818          */
5819         eth_dev->data->dev_flags |= RTE_ETH_DEV_CLOSE_REMOVE;
5820
5821         PMD_DRV_LOG(INFO,
5822                     DRV_MODULE_NAME "found at mem %" PRIX64 ", node addr %pM\n",
5823                     pci_dev->mem_resource[0].phys_addr,
5824                     pci_dev->mem_resource[0].addr);
5825
5826         return 0;
5827
5828 error_free:
5829         bnxt_dev_uninit(eth_dev);
5830         return rc;
5831 }
5832
5833
5834 static void bnxt_free_ctx_mem_buf(struct bnxt_ctx_mem_buf_info *ctx)
5835 {
5836         if (!ctx)
5837                 return;
5838
5839         if (ctx->va)
5840                 rte_free(ctx->va);
5841
5842         ctx->va = NULL;
5843         ctx->dma = RTE_BAD_IOVA;
5844         ctx->ctx_id = BNXT_CTX_VAL_INVAL;
5845 }
5846
5847 static void bnxt_unregister_fc_ctx_mem(struct bnxt *bp)
5848 {
5849         bnxt_hwrm_cfa_counter_cfg(bp, BNXT_DIR_RX,
5850                                   CFA_COUNTER_CFG_IN_COUNTER_TYPE_FC,
5851                                   bp->flow_stat->rx_fc_out_tbl.ctx_id,
5852                                   bp->flow_stat->max_fc,
5853                                   false);
5854
5855         bnxt_hwrm_cfa_counter_cfg(bp, BNXT_DIR_TX,
5856                                   CFA_COUNTER_CFG_IN_COUNTER_TYPE_FC,
5857                                   bp->flow_stat->tx_fc_out_tbl.ctx_id,
5858                                   bp->flow_stat->max_fc,
5859                                   false);
5860
5861         if (bp->flow_stat->rx_fc_in_tbl.ctx_id != BNXT_CTX_VAL_INVAL)
5862                 bnxt_hwrm_ctx_unrgtr(bp, bp->flow_stat->rx_fc_in_tbl.ctx_id);
5863         bp->flow_stat->rx_fc_in_tbl.ctx_id = BNXT_CTX_VAL_INVAL;
5864
5865         if (bp->flow_stat->rx_fc_out_tbl.ctx_id != BNXT_CTX_VAL_INVAL)
5866                 bnxt_hwrm_ctx_unrgtr(bp, bp->flow_stat->rx_fc_out_tbl.ctx_id);
5867         bp->flow_stat->rx_fc_out_tbl.ctx_id = BNXT_CTX_VAL_INVAL;
5868
5869         if (bp->flow_stat->tx_fc_in_tbl.ctx_id != BNXT_CTX_VAL_INVAL)
5870                 bnxt_hwrm_ctx_unrgtr(bp, bp->flow_stat->tx_fc_in_tbl.ctx_id);
5871         bp->flow_stat->tx_fc_in_tbl.ctx_id = BNXT_CTX_VAL_INVAL;
5872
5873         if (bp->flow_stat->tx_fc_out_tbl.ctx_id != BNXT_CTX_VAL_INVAL)
5874                 bnxt_hwrm_ctx_unrgtr(bp, bp->flow_stat->tx_fc_out_tbl.ctx_id);
5875         bp->flow_stat->tx_fc_out_tbl.ctx_id = BNXT_CTX_VAL_INVAL;
5876 }
5877
5878 static void bnxt_uninit_fc_ctx_mem(struct bnxt *bp)
5879 {
5880         bnxt_unregister_fc_ctx_mem(bp);
5881
5882         bnxt_free_ctx_mem_buf(&bp->flow_stat->rx_fc_in_tbl);
5883         bnxt_free_ctx_mem_buf(&bp->flow_stat->rx_fc_out_tbl);
5884         bnxt_free_ctx_mem_buf(&bp->flow_stat->tx_fc_in_tbl);
5885         bnxt_free_ctx_mem_buf(&bp->flow_stat->tx_fc_out_tbl);
5886 }
5887
5888 static void bnxt_uninit_ctx_mem(struct bnxt *bp)
5889 {
5890         if (BNXT_FLOW_XSTATS_EN(bp))
5891                 bnxt_uninit_fc_ctx_mem(bp);
5892 }
5893
5894 static void
5895 bnxt_free_error_recovery_info(struct bnxt *bp)
5896 {
5897         rte_free(bp->recovery_info);
5898         bp->recovery_info = NULL;
5899         bp->fw_cap &= ~BNXT_FW_CAP_ERROR_RECOVERY;
5900 }
5901
5902 static void
5903 bnxt_uninit_locks(struct bnxt *bp)
5904 {
5905         pthread_mutex_destroy(&bp->flow_lock);
5906         pthread_mutex_destroy(&bp->def_cp_lock);
5907         if (bp->rep_info)
5908                 pthread_mutex_destroy(&bp->rep_info->vfr_lock);
5909 }
5910
5911 static int
5912 bnxt_uninit_resources(struct bnxt *bp, bool reconfig_dev)
5913 {
5914         int rc;
5915
5916         bnxt_free_int(bp);
5917         bnxt_free_mem(bp, reconfig_dev);
5918         bnxt_hwrm_func_buf_unrgtr(bp);
5919         rc = bnxt_hwrm_func_driver_unregister(bp, 0);
5920         bp->flags &= ~BNXT_FLAG_REGISTERED;
5921         bnxt_free_ctx_mem(bp);
5922         if (!reconfig_dev) {
5923                 bnxt_free_hwrm_resources(bp);
5924                 bnxt_free_error_recovery_info(bp);
5925         }
5926
5927         bnxt_uninit_ctx_mem(bp);
5928
5929         bnxt_uninit_locks(bp);
5930         bnxt_free_flow_stats_info(bp);
5931         bnxt_free_rep_info(bp);
5932         rte_free(bp->ptp_cfg);
5933         bp->ptp_cfg = NULL;
5934         return rc;
5935 }
5936
5937 static int
5938 bnxt_dev_uninit(struct rte_eth_dev *eth_dev)
5939 {
5940         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
5941                 return -EPERM;
5942
5943         PMD_DRV_LOG(DEBUG, "Calling Device uninit\n");
5944
5945         if (eth_dev->state != RTE_ETH_DEV_UNUSED)
5946                 bnxt_dev_close_op(eth_dev);
5947
5948         return 0;
5949 }
5950
5951 static int bnxt_pci_remove_dev_with_reps(struct rte_eth_dev *eth_dev)
5952 {
5953         struct bnxt *bp = eth_dev->data->dev_private;
5954         struct rte_eth_dev *vf_rep_eth_dev;
5955         int ret = 0, i;
5956
5957         if (!bp)
5958                 return -EINVAL;
5959
5960         for (i = 0; i < bp->num_reps; i++) {
5961                 vf_rep_eth_dev = bp->rep_info[i].vfr_eth_dev;
5962                 if (!vf_rep_eth_dev)
5963                         continue;
5964                 rte_eth_dev_destroy(vf_rep_eth_dev, bnxt_vf_representor_uninit);
5965         }
5966         ret = rte_eth_dev_destroy(eth_dev, bnxt_dev_uninit);
5967
5968         return ret;
5969 }
5970
5971 static void bnxt_free_rep_info(struct bnxt *bp)
5972 {
5973         rte_free(bp->rep_info);
5974         bp->rep_info = NULL;
5975         rte_free(bp->cfa_code_map);
5976         bp->cfa_code_map = NULL;
5977 }
5978
5979 static int bnxt_init_rep_info(struct bnxt *bp)
5980 {
5981         int i = 0, rc;
5982
5983         if (bp->rep_info)
5984                 return 0;
5985
5986         bp->rep_info = rte_zmalloc("bnxt_rep_info",
5987                                    sizeof(bp->rep_info[0]) * BNXT_MAX_VF_REPS,
5988                                    0);
5989         if (!bp->rep_info) {
5990                 PMD_DRV_LOG(ERR, "Failed to alloc memory for rep info\n");
5991                 return -ENOMEM;
5992         }
5993         bp->cfa_code_map = rte_zmalloc("bnxt_cfa_code_map",
5994                                        sizeof(*bp->cfa_code_map) *
5995                                        BNXT_MAX_CFA_CODE, 0);
5996         if (!bp->cfa_code_map) {
5997                 PMD_DRV_LOG(ERR, "Failed to alloc memory for cfa_code_map\n");
5998                 bnxt_free_rep_info(bp);
5999                 return -ENOMEM;
6000         }
6001
6002         for (i = 0; i < BNXT_MAX_CFA_CODE; i++)
6003                 bp->cfa_code_map[i] = BNXT_VF_IDX_INVALID;
6004
6005         rc = pthread_mutex_init(&bp->rep_info->vfr_lock, NULL);
6006         if (rc) {
6007                 PMD_DRV_LOG(ERR, "Unable to initialize vfr_lock\n");
6008                 bnxt_free_rep_info(bp);
6009                 return rc;
6010         }
6011         return rc;
6012 }
6013
6014 static int bnxt_rep_port_probe(struct rte_pci_device *pci_dev,
6015                                struct rte_eth_devargs eth_da,
6016                                struct rte_eth_dev *backing_eth_dev)
6017 {
6018         struct rte_eth_dev *vf_rep_eth_dev;
6019         char name[RTE_ETH_NAME_MAX_LEN];
6020         struct bnxt *backing_bp;
6021         uint16_t num_rep;
6022         int i, ret = 0;
6023
6024         num_rep = eth_da.nb_representor_ports;
6025         if (num_rep > BNXT_MAX_VF_REPS) {
6026                 PMD_DRV_LOG(ERR, "nb_representor_ports = %d > %d MAX VF REPS\n",
6027                             num_rep, BNXT_MAX_VF_REPS);
6028                 return -EINVAL;
6029         }
6030
6031         if (num_rep > RTE_MAX_ETHPORTS) {
6032                 PMD_DRV_LOG(ERR,
6033                             "nb_representor_ports = %d > %d MAX ETHPORTS\n",
6034                             num_rep, RTE_MAX_ETHPORTS);
6035                 return -EINVAL;
6036         }
6037
6038         backing_bp = backing_eth_dev->data->dev_private;
6039
6040         if (!(BNXT_PF(backing_bp) || BNXT_VF_IS_TRUSTED(backing_bp))) {
6041                 PMD_DRV_LOG(ERR,
6042                             "Not a PF or trusted VF. No Representor support\n");
6043                 /* Returning an error is not an option.
6044                  * Applications are not handling this correctly
6045                  */
6046                 return 0;
6047         }
6048
6049         if (bnxt_init_rep_info(backing_bp))
6050                 return 0;
6051
6052         for (i = 0; i < num_rep; i++) {
6053                 struct bnxt_vf_representor representor = {
6054                         .vf_id = eth_da.representor_ports[i],
6055                         .switch_domain_id = backing_bp->switch_domain_id,
6056                         .parent_dev = backing_eth_dev
6057                 };
6058
6059                 if (representor.vf_id >= BNXT_MAX_VF_REPS) {
6060                         PMD_DRV_LOG(ERR, "VF-Rep id %d >= %d MAX VF ID\n",
6061                                     representor.vf_id, BNXT_MAX_VF_REPS);
6062                         continue;
6063                 }
6064
6065                 /* representor port net_bdf_port */
6066                 snprintf(name, sizeof(name), "net_%s_representor_%d",
6067                          pci_dev->device.name, eth_da.representor_ports[i]);
6068
6069                 ret = rte_eth_dev_create(&pci_dev->device, name,
6070                                          sizeof(struct bnxt_vf_representor),
6071                                          NULL, NULL,
6072                                          bnxt_vf_representor_init,
6073                                          &representor);
6074
6075                 if (!ret) {
6076                         vf_rep_eth_dev = rte_eth_dev_allocated(name);
6077                         if (!vf_rep_eth_dev) {
6078                                 PMD_DRV_LOG(ERR, "Failed to find the eth_dev"
6079                                             " for VF-Rep: %s.", name);
6080                                 bnxt_pci_remove_dev_with_reps(backing_eth_dev);
6081                                 ret = -ENODEV;
6082                                 return ret;
6083                         }
6084                         backing_bp->rep_info[representor.vf_id].vfr_eth_dev =
6085                                 vf_rep_eth_dev;
6086                         backing_bp->num_reps++;
6087                 } else {
6088                         PMD_DRV_LOG(ERR, "failed to create bnxt vf "
6089                                     "representor %s.", name);
6090                         bnxt_pci_remove_dev_with_reps(backing_eth_dev);
6091                 }
6092         }
6093
6094         return ret;
6095 }
6096
6097 static int bnxt_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
6098                           struct rte_pci_device *pci_dev)
6099 {
6100         struct rte_eth_devargs eth_da = { .nb_representor_ports = 0 };
6101         struct rte_eth_dev *backing_eth_dev;
6102         uint16_t num_rep;
6103         int ret = 0;
6104
6105         if (pci_dev->device.devargs) {
6106                 ret = rte_eth_devargs_parse(pci_dev->device.devargs->args,
6107                                             &eth_da);
6108                 if (ret)
6109                         return ret;
6110         }
6111
6112         num_rep = eth_da.nb_representor_ports;
6113         PMD_DRV_LOG(DEBUG, "nb_representor_ports = %d\n",
6114                     num_rep);
6115
6116         /* We could come here after first level of probe is already invoked
6117          * as part of an application bringup(OVS-DPDK vswitchd), so first check
6118          * for already allocated eth_dev for the backing device (PF/Trusted VF)
6119          */
6120         backing_eth_dev = rte_eth_dev_allocated(pci_dev->device.name);
6121         if (backing_eth_dev == NULL) {
6122                 ret = rte_eth_dev_create(&pci_dev->device, pci_dev->device.name,
6123                                          sizeof(struct bnxt),
6124                                          eth_dev_pci_specific_init, pci_dev,
6125                                          bnxt_dev_init, NULL);
6126
6127                 if (ret || !num_rep)
6128                         return ret;
6129
6130                 backing_eth_dev = rte_eth_dev_allocated(pci_dev->device.name);
6131         }
6132
6133         /* probe representor ports now */
6134         ret = bnxt_rep_port_probe(pci_dev, eth_da, backing_eth_dev);
6135
6136         return ret;
6137 }
6138
6139 static int bnxt_pci_remove(struct rte_pci_device *pci_dev)
6140 {
6141         struct rte_eth_dev *eth_dev;
6142
6143         eth_dev = rte_eth_dev_allocated(pci_dev->device.name);
6144         if (!eth_dev)
6145                 return 0; /* Invoked typically only by OVS-DPDK, by the
6146                            * time it comes here the eth_dev is already
6147                            * deleted by rte_eth_dev_close(), so returning
6148                            * +ve value will at least help in proper cleanup
6149                            */
6150
6151         if (rte_eal_process_type() == RTE_PROC_PRIMARY) {
6152                 if (eth_dev->data->dev_flags & RTE_ETH_DEV_REPRESENTOR)
6153                         return rte_eth_dev_destroy(eth_dev,
6154                                                    bnxt_vf_representor_uninit);
6155                 else
6156                         return rte_eth_dev_destroy(eth_dev,
6157                                                    bnxt_dev_uninit);
6158         } else {
6159                 return rte_eth_dev_pci_generic_remove(pci_dev, NULL);
6160         }
6161 }
6162
6163 static struct rte_pci_driver bnxt_rte_pmd = {
6164         .id_table = bnxt_pci_id_map,
6165         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC |
6166                         RTE_PCI_DRV_PROBE_AGAIN, /* Needed in case of VF-REPs
6167                                                   * and OVS-DPDK
6168                                                   */
6169         .probe = bnxt_pci_probe,
6170         .remove = bnxt_pci_remove,
6171 };
6172
6173 static bool
6174 is_device_supported(struct rte_eth_dev *dev, struct rte_pci_driver *drv)
6175 {
6176         if (strcmp(dev->device->driver->name, drv->driver.name))
6177                 return false;
6178
6179         return true;
6180 }
6181
6182 bool is_bnxt_supported(struct rte_eth_dev *dev)
6183 {
6184         return is_device_supported(dev, &bnxt_rte_pmd);
6185 }
6186
6187 RTE_LOG_REGISTER(bnxt_logtype_driver, pmd.net.bnxt.driver, NOTICE);
6188 RTE_PMD_REGISTER_PCI(net_bnxt, bnxt_rte_pmd);
6189 RTE_PMD_REGISTER_PCI_TABLE(net_bnxt, bnxt_pci_id_map);
6190 RTE_PMD_REGISTER_KMOD_DEP(net_bnxt, "* igb_uio | uio_pci_generic | vfio-pci");