drivers/net/bnxt/bnxt_ethdev.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2014-2018 Broadcom
   3  * All rights reserved.
   4  */
   5
   6 #include <inttypes.h>
   7 #include <stdbool.h>
   8
   9 #include <rte_dev.h>
  10 #include <rte_ethdev_driver.h>
  11 #include <rte_ethdev_pci.h>
  12 #include <rte_malloc.h>
  13 #include <rte_cycles.h>
  14 #include <rte_alarm.h>
  15 #include <rte_kvargs.h>
  16
  17 #include "bnxt.h"
  18 #include "bnxt_filter.h"
  19 #include "bnxt_hwrm.h"
  20 #include "bnxt_irq.h"
  21 #include "bnxt_reps.h"
  22 #include "bnxt_ring.h"
  23 #include "bnxt_rxq.h"
  24 #include "bnxt_rxr.h"
  25 #include "bnxt_stats.h"
  26 #include "bnxt_txq.h"
  27 #include "bnxt_txr.h"
  28 #include "bnxt_vnic.h"
  29 #include "hsi_struct_def_dpdk.h"
  30 #include "bnxt_nvm_defs.h"
  31 #include "bnxt_tf_common.h"
  32 #include "ulp_flow_db.h"
  33
  34 #define DRV_MODULE_NAME         "bnxt"
  35 static const char bnxt_version[] =
  36         "Broadcom NetXtreme driver " DRV_MODULE_NAME;
  37
  38 /*
  39  * The set of PCI devices this driver supports
  40  */
  41 static const struct rte_pci_id bnxt_pci_id_map[] = {
  42         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM,
  43                          BROADCOM_DEV_ID_STRATUS_NIC_VF1) },
  44         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM,
  45                          BROADCOM_DEV_ID_STRATUS_NIC_VF2) },
  46         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_STRATUS_NIC) },
  47         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414_VF) },
  48         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57301) },
  49         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57302) },
  50         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57304_PF) },
  51         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57304_VF) },
  52         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_NS2) },
  53         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57402) },
  54         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57404) },
  55         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57406_PF) },
  56         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57406_VF) },
  57         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57402_MF) },
  58         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57407_RJ45) },
  59         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57404_MF) },
  60         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57406_MF) },
  61         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57407_SFP) },
  62         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57407_MF) },
  63         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_5741X_VF) },
  64         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_5731X_VF) },
  65         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57314) },
  66         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_MF) },
  67         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57311) },
  68         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57312) },
  69         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57412) },
  70         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414) },
  71         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_RJ45) },
  72         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_RJ45) },
  73         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57412_MF) },
  74         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57317_RJ45) },
  75         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_SFP) },
  76         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_SFP) },
  77         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57317_SFP) },
  78         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414_MF) },
  79         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_MF) },
  80         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58802) },
  81         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58804) },
  82         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58808) },
  83         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58802_VF) },
  84         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57508) },
  85         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57504) },
  86         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57502) },
  87         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57500_VF1) },
  88         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57500_VF2) },
  89         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57508_MF1) },
  90         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57504_MF1) },
  91         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57502_MF1) },
  92         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57508_MF2) },
  93         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57504_MF2) },
  94         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57502_MF2) },
  95         { .vendor_id = 0, /* sentinel */ },
  96 };
  97
  98 #define BNXT_DEVARG_TRUFLOW     "host-based-truflow"
  99 #define BNXT_DEVARG_FLOW_XSTAT  "flow-xstat"
 100 #define BNXT_DEVARG_MAX_NUM_KFLOWS  "max-num-kflows"
 101 #define BNXT_DEVARG_REPRESENTOR "representor"
 102 #define BNXT_DEVARG_REP_BASED_PF  "rep-based-pf"
 103 #define BNXT_DEVARG_REP_IS_PF  "rep-is-pf"
 104 #define BNXT_DEVARG_REP_Q_R2F  "rep-q-r2f"
 105 #define BNXT_DEVARG_REP_Q_F2R  "rep-q-f2r"
 106 #define BNXT_DEVARG_REP_FC_R2F  "rep-fc-r2f"
 107 #define BNXT_DEVARG_REP_FC_F2R  "rep-fc-f2r"
 108
 109 static const char *const bnxt_dev_args[] = {
 110         BNXT_DEVARG_REPRESENTOR,
 111         BNXT_DEVARG_TRUFLOW,
 112         BNXT_DEVARG_FLOW_XSTAT,
 113         BNXT_DEVARG_MAX_NUM_KFLOWS,
 114         BNXT_DEVARG_REP_BASED_PF,
 115         BNXT_DEVARG_REP_IS_PF,
 116         BNXT_DEVARG_REP_Q_R2F,
 117         BNXT_DEVARG_REP_Q_F2R,
 118         BNXT_DEVARG_REP_FC_R2F,
 119         BNXT_DEVARG_REP_FC_F2R,
 120         NULL
 121 };
 122
 123 /*
 124  * truflow == false to disable the feature
 125  * truflow == true to enable the feature
 126  */
 127 #define BNXT_DEVARG_TRUFLOW_INVALID(truflow)    ((truflow) > 1)
 128
 129 /*
 130  * flow_xstat == false to disable the feature
 131  * flow_xstat == true to enable the feature
 132  */
 133 #define BNXT_DEVARG_FLOW_XSTAT_INVALID(flow_xstat)      ((flow_xstat) > 1)
 134
 135 /*
 136  * rep_is_pf == false to indicate VF representor
 137  * rep_is_pf == true to indicate PF representor
 138  */
 139 #define BNXT_DEVARG_REP_IS_PF_INVALID(rep_is_pf)        ((rep_is_pf) > 1)
 140
 141 /*
 142  * rep_based_pf == Physical index of the PF
 143  */
 144 #define BNXT_DEVARG_REP_BASED_PF_INVALID(rep_based_pf)  ((rep_based_pf) > 15)
 145 /*
 146  * rep_q_r2f == Logical COS Queue index for the rep to endpoint direction
 147  */
 148 #define BNXT_DEVARG_REP_Q_R2F_INVALID(rep_q_r2f)        ((rep_q_r2f) > 3)
 149
 150 /*
 151  * rep_q_f2r == Logical COS Queue index for the endpoint to rep direction
 152  */
 153 #define BNXT_DEVARG_REP_Q_F2R_INVALID(rep_q_f2r)        ((rep_q_f2r) > 3)
 154
 155 /*
 156  * rep_fc_r2f == Flow control for the representor to endpoint direction
 157  */
 158 #define BNXT_DEVARG_REP_FC_R2F_INVALID(rep_fc_r2f)      ((rep_fc_r2f) > 1)
 159
 160 /*
 161  * rep_fc_f2r == Flow control for the endpoint to representor direction
 162  */
 163 #define BNXT_DEVARG_REP_FC_F2R_INVALID(rep_fc_f2r)      ((rep_fc_f2r) > 1)
 164
 165 /*
 166  * max_num_kflows must be >= 32
 167  * and must be a power-of-2 supported value
 168  * return: 1 -> invalid
 169  *         0 -> valid
 170  */
 171 static int bnxt_devarg_max_num_kflow_invalid(uint16_t max_num_kflows)
 172 {
 173         if (max_num_kflows < 32 || !rte_is_power_of_2(max_num_kflows))
 174                 return 1;
 175         return 0;
 176 }
 177
 178 static int bnxt_vlan_offload_set_op(struct rte_eth_dev *dev, int mask);
 179 static int bnxt_dev_uninit(struct rte_eth_dev *eth_dev);
 180 static int bnxt_init_resources(struct bnxt *bp, bool reconfig_dev);
 181 static int bnxt_uninit_resources(struct bnxt *bp, bool reconfig_dev);
 182 static void bnxt_cancel_fw_health_check(struct bnxt *bp);
 183 static int bnxt_restore_vlan_filters(struct bnxt *bp);
 184 static void bnxt_dev_recover(void *arg);
 185 static void bnxt_free_error_recovery_info(struct bnxt *bp);
 186 static void bnxt_free_rep_info(struct bnxt *bp);
 187
 188 int is_bnxt_in_error(struct bnxt *bp)
 189 {
 190         if (bp->flags & BNXT_FLAG_FATAL_ERROR)
 191                 return -EIO;
 192         if (bp->flags & BNXT_FLAG_FW_RESET)
 193                 return -EBUSY;
 194
 195         return 0;
 196 }
 197
 198 /***********************/
 199
 200 /*
 201  * High level utility functions
 202  */
 203
 204 static uint16_t bnxt_rss_ctxts(const struct bnxt *bp)
 205 {
 206         if (!BNXT_CHIP_THOR(bp))
 207                 return 1;
 208
 209         return RTE_ALIGN_MUL_CEIL(bp->rx_nr_rings,
 210                                   BNXT_RSS_ENTRIES_PER_CTX_THOR) /
 211                                     BNXT_RSS_ENTRIES_PER_CTX_THOR;
 212 }
 213
 214 uint16_t bnxt_rss_hash_tbl_size(const struct bnxt *bp)
 215 {
 216         if (!BNXT_CHIP_THOR(bp))
 217                 return HW_HASH_INDEX_SIZE;
 218
 219         return bnxt_rss_ctxts(bp) * BNXT_RSS_ENTRIES_PER_CTX_THOR;
 220 }
 221
 222 static void bnxt_free_parent_info(struct bnxt *bp)
 223 {
 224         rte_free(bp->parent);
 225 }
 226
 227 static void bnxt_free_pf_info(struct bnxt *bp)
 228 {
 229         rte_free(bp->pf);
 230 }
 231
 232 static void bnxt_free_link_info(struct bnxt *bp)
 233 {
 234         rte_free(bp->link_info);
 235 }
 236
 237 static void bnxt_free_leds_info(struct bnxt *bp)
 238 {
 239         if (BNXT_VF(bp))
 240                 return;
 241
 242         rte_free(bp->leds);
 243         bp->leds = NULL;
 244 }
 245
 246 static void bnxt_free_flow_stats_info(struct bnxt *bp)
 247 {
 248         rte_free(bp->flow_stat);
 249         bp->flow_stat = NULL;
 250 }
 251
 252 static void bnxt_free_cos_queues(struct bnxt *bp)
 253 {
 254         rte_free(bp->rx_cos_queue);
 255         rte_free(bp->tx_cos_queue);
 256 }
 257
 258 static void bnxt_free_mem(struct bnxt *bp, bool reconfig)
 259 {
 260         bnxt_free_filter_mem(bp);
 261         bnxt_free_vnic_attributes(bp);
 262         bnxt_free_vnic_mem(bp);
 263
 264         /* tx/rx rings are configured as part of *_queue_setup callbacks.
 265          * If the number of rings change across fw update,
 266          * we don't have much choice except to warn the user.
 267          */
 268         if (!reconfig) {
 269                 bnxt_free_stats(bp);
 270                 bnxt_free_tx_rings(bp);
 271                 bnxt_free_rx_rings(bp);
 272         }
 273         bnxt_free_async_cp_ring(bp);
 274         bnxt_free_rxtx_nq_ring(bp);
 275
 276         rte_free(bp->grp_info);
 277         bp->grp_info = NULL;
 278 }
 279
 280 static int bnxt_alloc_parent_info(struct bnxt *bp)
 281 {
 282         bp->parent = rte_zmalloc("bnxt_parent_info",
 283                                  sizeof(struct bnxt_parent_info), 0);
 284         if (bp->parent == NULL)
 285                 return -ENOMEM;
 286
 287         return 0;
 288 }
 289
 290 static int bnxt_alloc_pf_info(struct bnxt *bp)
 291 {
 292         bp->pf = rte_zmalloc("bnxt_pf_info", sizeof(struct bnxt_pf_info), 0);
 293         if (bp->pf == NULL)
 294                 return -ENOMEM;
 295
 296         return 0;
 297 }
 298
 299 static int bnxt_alloc_link_info(struct bnxt *bp)
 300 {
 301         bp->link_info =
 302                 rte_zmalloc("bnxt_link_info", sizeof(struct bnxt_link_info), 0);
 303         if (bp->link_info == NULL)
 304                 return -ENOMEM;
 305
 306         return 0;
 307 }
 308
 309 static int bnxt_alloc_leds_info(struct bnxt *bp)
 310 {
 311         if (BNXT_VF(bp))
 312                 return 0;
 313
 314         bp->leds = rte_zmalloc("bnxt_leds",
 315                                BNXT_MAX_LED * sizeof(struct bnxt_led_info),
 316                                0);
 317         if (bp->leds == NULL)
 318                 return -ENOMEM;
 319
 320         return 0;
 321 }
 322
 323 static int bnxt_alloc_cos_queues(struct bnxt *bp)
 324 {
 325         bp->rx_cos_queue =
 326                 rte_zmalloc("bnxt_rx_cosq",
 327                             BNXT_COS_QUEUE_COUNT *
 328                             sizeof(struct bnxt_cos_queue_info),
 329                             0);
 330         if (bp->rx_cos_queue == NULL)
 331                 return -ENOMEM;
 332
 333         bp->tx_cos_queue =
 334                 rte_zmalloc("bnxt_tx_cosq",
 335                             BNXT_COS_QUEUE_COUNT *
 336                             sizeof(struct bnxt_cos_queue_info),
 337                             0);
 338         if (bp->tx_cos_queue == NULL)
 339                 return -ENOMEM;
 340
 341         return 0;
 342 }
 343
 344 static int bnxt_alloc_flow_stats_info(struct bnxt *bp)
 345 {
 346         bp->flow_stat = rte_zmalloc("bnxt_flow_xstat",
 347                                     sizeof(struct bnxt_flow_stat_info), 0);
 348         if (bp->flow_stat == NULL)
 349                 return -ENOMEM;
 350
 351         return 0;
 352 }
 353
 354 static int bnxt_alloc_mem(struct bnxt *bp, bool reconfig)
 355 {
 356         int rc;
 357
 358         rc = bnxt_alloc_ring_grps(bp);
 359         if (rc)
 360                 goto alloc_mem_err;
 361
 362         rc = bnxt_alloc_async_ring_struct(bp);
 363         if (rc)
 364                 goto alloc_mem_err;
 365
 366         rc = bnxt_alloc_vnic_mem(bp);
 367         if (rc)
 368                 goto alloc_mem_err;
 369
 370         rc = bnxt_alloc_vnic_attributes(bp);
 371         if (rc)
 372                 goto alloc_mem_err;
 373
 374         rc = bnxt_alloc_filter_mem(bp);
 375         if (rc)
 376                 goto alloc_mem_err;
 377
 378         rc = bnxt_alloc_async_cp_ring(bp);
 379         if (rc)
 380                 goto alloc_mem_err;
 381
 382         rc = bnxt_alloc_rxtx_nq_ring(bp);
 383         if (rc)
 384                 goto alloc_mem_err;
 385
 386         if (BNXT_FLOW_XSTATS_EN(bp)) {
 387                 rc = bnxt_alloc_flow_stats_info(bp);
 388                 if (rc)
 389                         goto alloc_mem_err;
 390         }
 391
 392         return 0;
 393
 394 alloc_mem_err:
 395         bnxt_free_mem(bp, reconfig);
 396         return rc;
 397 }
 398
 399 static int bnxt_setup_one_vnic(struct bnxt *bp, uint16_t vnic_id)
 400 {
 401         struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
 402         struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id];
 403         uint64_t rx_offloads = dev_conf->rxmode.offloads;
 404         struct bnxt_rx_queue *rxq;
 405         unsigned int j;
 406         int rc;
 407
 408         rc = bnxt_vnic_grp_alloc(bp, vnic);
 409         if (rc)
 410                 goto err_out;
 411
 412         PMD_DRV_LOG(DEBUG, "vnic[%d] = %p vnic->fw_grp_ids = %p\n",
 413                     vnic_id, vnic, vnic->fw_grp_ids);
 414
 415         rc = bnxt_hwrm_vnic_alloc(bp, vnic);
 416         if (rc)
 417                 goto err_out;
 418
 419         /* Alloc RSS context only if RSS mode is enabled */
 420         if (dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS) {
 421                 int j, nr_ctxs = bnxt_rss_ctxts(bp);
 422
 423                 rc = 0;
 424                 for (j = 0; j < nr_ctxs; j++) {
 425                         rc = bnxt_hwrm_vnic_ctx_alloc(bp, vnic, j);
 426                         if (rc)
 427                                 break;
 428                 }
 429                 if (rc) {
 430                         PMD_DRV_LOG(ERR,
 431                                     "HWRM vnic %d ctx %d alloc failure rc: %x\n",
 432                                     vnic_id, j, rc);
 433                         goto err_out;
 434                 }
 435                 vnic->num_lb_ctxts = nr_ctxs;
 436         }
 437
 438         /*
 439          * Firmware sets pf pair in default vnic cfg. If the VLAN strip
 440          * setting is not available at this time, it will not be
 441          * configured correctly in the CFA.
 442          */
 443         if (rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
 444                 vnic->vlan_strip = true;
 445         else
 446                 vnic->vlan_strip = false;
 447
 448         rc = bnxt_hwrm_vnic_cfg(bp, vnic);
 449         if (rc)
 450                 goto err_out;
 451
 452         rc = bnxt_set_hwrm_vnic_filters(bp, vnic);
 453         if (rc)
 454                 goto err_out;
 455
 456         for (j = 0; j < bp->rx_num_qs_per_vnic; j++) {
 457                 rxq = bp->eth_dev->data->rx_queues[j];
 458
 459                 PMD_DRV_LOG(DEBUG,
 460                             "rxq[%d]->vnic=%p vnic->fw_grp_ids=%p\n",
 461                             j, rxq->vnic, rxq->vnic->fw_grp_ids);
 462
 463                 if (BNXT_HAS_RING_GRPS(bp) && rxq->rx_deferred_start)
 464                         rxq->vnic->fw_grp_ids[j] = INVALID_HW_RING_ID;
 465                 else
 466                         vnic->rx_queue_cnt++;
 467         }
 468
 469         PMD_DRV_LOG(DEBUG, "vnic->rx_queue_cnt = %d\n", vnic->rx_queue_cnt);
 470
 471         rc = bnxt_vnic_rss_configure(bp, vnic);
 472         if (rc)
 473                 goto err_out;
 474
 475         bnxt_hwrm_vnic_plcmode_cfg(bp, vnic);
 476
 477         if (rx_offloads & DEV_RX_OFFLOAD_TCP_LRO)
 478                 bnxt_hwrm_vnic_tpa_cfg(bp, vnic, 1);
 479         else
 480                 bnxt_hwrm_vnic_tpa_cfg(bp, vnic, 0);
 481
 482         return 0;
 483 err_out:
 484         PMD_DRV_LOG(ERR, "HWRM vnic %d cfg failure rc: %x\n",
 485                     vnic_id, rc);
 486         return rc;
 487 }
 488
 489 static int bnxt_register_fc_ctx_mem(struct bnxt *bp)
 490 {
 491         int rc = 0;
 492
 493         rc = bnxt_hwrm_ctx_rgtr(bp, bp->flow_stat->rx_fc_in_tbl.dma,
 494                                 &bp->flow_stat->rx_fc_in_tbl.ctx_id);
 495         if (rc)
 496                 return rc;
 497
 498         PMD_DRV_LOG(DEBUG,
 499                     "rx_fc_in_tbl.va = %p rx_fc_in_tbl.dma = %p"
 500                     " rx_fc_in_tbl.ctx_id = %d\n",
 501                     bp->flow_stat->rx_fc_in_tbl.va,
 502                     (void *)((uintptr_t)bp->flow_stat->rx_fc_in_tbl.dma),
 503                     bp->flow_stat->rx_fc_in_tbl.ctx_id);
 504
 505         rc = bnxt_hwrm_ctx_rgtr(bp, bp->flow_stat->rx_fc_out_tbl.dma,
 506                                 &bp->flow_stat->rx_fc_out_tbl.ctx_id);
 507         if (rc)
 508                 return rc;
 509
 510         PMD_DRV_LOG(DEBUG,
 511                     "rx_fc_out_tbl.va = %p rx_fc_out_tbl.dma = %p"
 512                     " rx_fc_out_tbl.ctx_id = %d\n",
 513                     bp->flow_stat->rx_fc_out_tbl.va,
 514                     (void *)((uintptr_t)bp->flow_stat->rx_fc_out_tbl.dma),
 515                     bp->flow_stat->rx_fc_out_tbl.ctx_id);
 516
 517         rc = bnxt_hwrm_ctx_rgtr(bp, bp->flow_stat->tx_fc_in_tbl.dma,
 518                                 &bp->flow_stat->tx_fc_in_tbl.ctx_id);
 519         if (rc)
 520                 return rc;
 521
 522         PMD_DRV_LOG(DEBUG,
 523                     "tx_fc_in_tbl.va = %p tx_fc_in_tbl.dma = %p"
 524                     " tx_fc_in_tbl.ctx_id = %d\n",
 525                     bp->flow_stat->tx_fc_in_tbl.va,
 526                     (void *)((uintptr_t)bp->flow_stat->tx_fc_in_tbl.dma),
 527                     bp->flow_stat->tx_fc_in_tbl.ctx_id);
 528
 529         rc = bnxt_hwrm_ctx_rgtr(bp, bp->flow_stat->tx_fc_out_tbl.dma,
 530                                 &bp->flow_stat->tx_fc_out_tbl.ctx_id);
 531         if (rc)
 532                 return rc;
 533
 534         PMD_DRV_LOG(DEBUG,
 535                     "tx_fc_out_tbl.va = %p tx_fc_out_tbl.dma = %p"
 536                     " tx_fc_out_tbl.ctx_id = %d\n",
 537                     bp->flow_stat->tx_fc_out_tbl.va,
 538                     (void *)((uintptr_t)bp->flow_stat->tx_fc_out_tbl.dma),
 539                     bp->flow_stat->tx_fc_out_tbl.ctx_id);
 540
 541         memset(bp->flow_stat->rx_fc_out_tbl.va,
 542                0,
 543                bp->flow_stat->rx_fc_out_tbl.size);
 544         rc = bnxt_hwrm_cfa_counter_cfg(bp, BNXT_DIR_RX,
 545                                        CFA_COUNTER_CFG_IN_COUNTER_TYPE_FC,
 546                                        bp->flow_stat->rx_fc_out_tbl.ctx_id,
 547                                        bp->flow_stat->max_fc,
 548                                        true);
 549         if (rc)
 550                 return rc;
 551
 552         memset(bp->flow_stat->tx_fc_out_tbl.va,
 553                0,
 554                bp->flow_stat->tx_fc_out_tbl.size);
 555         rc = bnxt_hwrm_cfa_counter_cfg(bp, BNXT_DIR_TX,
 556                                        CFA_COUNTER_CFG_IN_COUNTER_TYPE_FC,
 557                                        bp->flow_stat->tx_fc_out_tbl.ctx_id,
 558                                        bp->flow_stat->max_fc,
 559                                        true);
 560
 561         return rc;
 562 }
 563
 564 static int bnxt_alloc_ctx_mem_buf(char *type, size_t size,
 565                                   struct bnxt_ctx_mem_buf_info *ctx)
 566 {
 567         if (!ctx)
 568                 return -EINVAL;
 569
 570         ctx->va = rte_zmalloc(type, size, 0);
 571         if (ctx->va == NULL)
 572                 return -ENOMEM;
 573         rte_mem_lock_page(ctx->va);
 574         ctx->size = size;
 575         ctx->dma = rte_mem_virt2iova(ctx->va);
 576         if (ctx->dma == RTE_BAD_IOVA)
 577                 return -ENOMEM;
 578
 579         return 0;
 580 }
 581
 582 static int bnxt_init_fc_ctx_mem(struct bnxt *bp)
 583 {
 584         struct rte_pci_device *pdev = bp->pdev;
 585         char type[RTE_MEMZONE_NAMESIZE];
 586         uint16_t max_fc;
 587         int rc = 0;
 588
 589         max_fc = bp->flow_stat->max_fc;
 590
 591         sprintf(type, "bnxt_rx_fc_in_" PCI_PRI_FMT, pdev->addr.domain,
 592                 pdev->addr.bus, pdev->addr.devid, pdev->addr.function);
 593         /* 4 bytes for each counter-id */
 594         rc = bnxt_alloc_ctx_mem_buf(type,
 595                                     max_fc * 4,
 596                                     &bp->flow_stat->rx_fc_in_tbl);
 597         if (rc)
 598                 return rc;
 599
 600         sprintf(type, "bnxt_rx_fc_out_" PCI_PRI_FMT, pdev->addr.domain,
 601                 pdev->addr.bus, pdev->addr.devid, pdev->addr.function);
 602         /* 16 bytes for each counter - 8 bytes pkt_count, 8 bytes byte_count */
 603         rc = bnxt_alloc_ctx_mem_buf(type,
 604                                     max_fc * 16,
 605                                     &bp->flow_stat->rx_fc_out_tbl);
 606         if (rc)
 607                 return rc;
 608
 609         sprintf(type, "bnxt_tx_fc_in_" PCI_PRI_FMT, pdev->addr.domain,
 610                 pdev->addr.bus, pdev->addr.devid, pdev->addr.function);
 611         /* 4 bytes for each counter-id */
 612         rc = bnxt_alloc_ctx_mem_buf(type,
 613                                     max_fc * 4,
 614                                     &bp->flow_stat->tx_fc_in_tbl);
 615         if (rc)
 616                 return rc;
 617
 618         sprintf(type, "bnxt_tx_fc_out_" PCI_PRI_FMT, pdev->addr.domain,
 619                 pdev->addr.bus, pdev->addr.devid, pdev->addr.function);
 620         /* 16 bytes for each counter - 8 bytes pkt_count, 8 bytes byte_count */
 621         rc = bnxt_alloc_ctx_mem_buf(type,
 622                                     max_fc * 16,
 623                                     &bp->flow_stat->tx_fc_out_tbl);
 624         if (rc)
 625                 return rc;
 626
 627         rc = bnxt_register_fc_ctx_mem(bp);
 628
 629         return rc;
 630 }
 631
 632 static int bnxt_init_ctx_mem(struct bnxt *bp)
 633 {
 634         int rc = 0;
 635
 636         if (!(bp->fw_cap & BNXT_FW_CAP_ADV_FLOW_COUNTERS) ||
 637             !(BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp)) ||
 638             !BNXT_FLOW_XSTATS_EN(bp))
 639                 return 0;
 640
 641         rc = bnxt_hwrm_cfa_counter_qcaps(bp, &bp->flow_stat->max_fc);
 642         if (rc)
 643                 return rc;
 644
 645         rc = bnxt_init_fc_ctx_mem(bp);
 646
 647         return rc;
 648 }
 649
 650 static int bnxt_update_phy_setting(struct bnxt *bp)
 651 {
 652         struct rte_eth_link new;
 653         int rc;
 654
 655         rc = bnxt_get_hwrm_link_config(bp, &new);
 656         if (rc) {
 657                 PMD_DRV_LOG(ERR, "Failed to get link settings\n");
 658                 return rc;
 659         }
 660
 661         /*
 662          * On BCM957508-N2100 adapters, FW will not allow any user other
 663          * than BMC to shutdown the port. bnxt_get_hwrm_link_config() call
 664          * always returns link up. Force phy update always in that case.
 665          */
 666         if (!new.link_status || IS_BNXT_DEV_957508_N2100(bp)) {
 667                 rc = bnxt_set_hwrm_link_config(bp, true);
 668                 if (rc) {
 669                         PMD_DRV_LOG(ERR, "Failed to update PHY settings\n");
 670                         return rc;
 671                 }
 672         }
 673
 674         return rc;
 675 }
 676
 677 static int bnxt_init_chip(struct bnxt *bp)
 678 {
 679         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(bp->eth_dev);
 680         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
 681         uint32_t intr_vector = 0;
 682         uint32_t queue_id, base = BNXT_MISC_VEC_ID;
 683         uint32_t vec = BNXT_MISC_VEC_ID;
 684         unsigned int i, j;
 685         int rc;
 686
 687         if (bp->eth_dev->data->mtu > RTE_ETHER_MTU) {
 688                 bp->eth_dev->data->dev_conf.rxmode.offloads |=
 689                         DEV_RX_OFFLOAD_JUMBO_FRAME;
 690                 bp->flags |= BNXT_FLAG_JUMBO;
 691         } else {
 692                 bp->eth_dev->data->dev_conf.rxmode.offloads &=
 693                         ~DEV_RX_OFFLOAD_JUMBO_FRAME;
 694                 bp->flags &= ~BNXT_FLAG_JUMBO;
 695         }
 696
 697         /* THOR does not support ring groups.
 698          * But we will use the array to save RSS context IDs.
 699          */
 700         if (BNXT_CHIP_THOR(bp))
 701                 bp->max_ring_grps = BNXT_MAX_RSS_CTXTS_THOR;
 702
 703         rc = bnxt_alloc_all_hwrm_stat_ctxs(bp);
 704         if (rc) {
 705                 PMD_DRV_LOG(ERR, "HWRM stat ctx alloc failure rc: %x\n", rc);
 706                 goto err_out;
 707         }
 708
 709         rc = bnxt_alloc_hwrm_rings(bp);
 710         if (rc) {
 711                 PMD_DRV_LOG(ERR, "HWRM ring alloc failure rc: %x\n", rc);
 712                 goto err_out;
 713         }
 714
 715         rc = bnxt_alloc_all_hwrm_ring_grps(bp);
 716         if (rc) {
 717                 PMD_DRV_LOG(ERR, "HWRM ring grp alloc failure: %x\n", rc);
 718                 goto err_out;
 719         }
 720
 721         if (!(bp->vnic_cap_flags & BNXT_VNIC_CAP_COS_CLASSIFY))
 722                 goto skip_cosq_cfg;
 723
 724         for (j = 0, i = 0; i < BNXT_COS_QUEUE_COUNT; i++) {
 725                 if (bp->rx_cos_queue[i].id != 0xff) {
 726                         struct bnxt_vnic_info *vnic = &bp->vnic_info[j++];
 727
 728                         if (!vnic) {
 729                                 PMD_DRV_LOG(ERR,
 730                                             "Num pools more than FW profile\n");
 731                                 rc = -EINVAL;
 732                                 goto err_out;
 733                         }
 734                         vnic->cos_queue_id = bp->rx_cos_queue[i].id;
 735                         bp->rx_cosq_cnt++;
 736                 }
 737         }
 738
 739 skip_cosq_cfg:
 740         rc = bnxt_mq_rx_configure(bp);
 741         if (rc) {
 742                 PMD_DRV_LOG(ERR, "MQ mode configure failure rc: %x\n", rc);
 743                 goto err_out;
 744         }
 745
 746         /* VNIC configuration */
 747         for (i = 0; i < bp->nr_vnics; i++) {
 748                 rc = bnxt_setup_one_vnic(bp, i);
 749                 if (rc)
 750                         goto err_out;
 751         }
 752
 753         rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, &bp->vnic_info[0], 0, NULL);
 754         if (rc) {
 755                 PMD_DRV_LOG(ERR,
 756                         "HWRM cfa l2 rx mask failure rc: %x\n", rc);
 757                 goto err_out;
 758         }
 759
 760         /* check and configure queue intr-vector mapping */
 761         if ((rte_intr_cap_multiple(intr_handle) ||
 762              !RTE_ETH_DEV_SRIOV(bp->eth_dev).active) &&
 763             bp->eth_dev->data->dev_conf.intr_conf.rxq != 0) {
 764                 intr_vector = bp->eth_dev->data->nb_rx_queues;
 765                 PMD_DRV_LOG(DEBUG, "intr_vector = %d\n", intr_vector);
 766                 if (intr_vector > bp->rx_cp_nr_rings) {
 767                         PMD_DRV_LOG(ERR, "At most %d intr queues supported",
 768                                         bp->rx_cp_nr_rings);
 769                         return -ENOTSUP;
 770                 }
 771                 rc = rte_intr_efd_enable(intr_handle, intr_vector);
 772                 if (rc)
 773                         return rc;
 774         }
 775
 776         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
 777                 intr_handle->intr_vec =
 778                         rte_zmalloc("intr_vec",
 779                                     bp->eth_dev->data->nb_rx_queues *
 780                                     sizeof(int), 0);
 781                 if (intr_handle->intr_vec == NULL) {
 782                         PMD_DRV_LOG(ERR, "Failed to allocate %d rx_queues"
 783                                 " intr_vec", bp->eth_dev->data->nb_rx_queues);
 784                         rc = -ENOMEM;
 785                         goto err_disable;
 786                 }
 787                 PMD_DRV_LOG(DEBUG, "intr_handle->intr_vec = %p "
 788                         "intr_handle->nb_efd = %d intr_handle->max_intr = %d\n",
 789                          intr_handle->intr_vec, intr_handle->nb_efd,
 790                         intr_handle->max_intr);
 791                 for (queue_id = 0; queue_id < bp->eth_dev->data->nb_rx_queues;
 792                      queue_id++) {
 793                         intr_handle->intr_vec[queue_id] =
 794                                                         vec + BNXT_RX_VEC_START;
 795                         if (vec < base + intr_handle->nb_efd - 1)
 796                                 vec++;
 797                 }
 798         }
 799
 800         /* enable uio/vfio intr/eventfd mapping */
 801         rc = rte_intr_enable(intr_handle);
 802 #ifndef RTE_EXEC_ENV_FREEBSD
 803         /* In FreeBSD OS, nic_uio driver does not support interrupts */
 804         if (rc)
 805                 goto err_free;
 806 #endif
 807
 808         rc = bnxt_update_phy_setting(bp);
 809         if (rc)
 810                 goto err_free;
 811
 812         bp->mark_table = rte_zmalloc("bnxt_mark_table", BNXT_MARK_TABLE_SZ, 0);
 813         if (!bp->mark_table)
 814                 PMD_DRV_LOG(ERR, "Allocation of mark table failed\n");
 815
 816         return 0;
 817
 818 err_free:
 819         rte_free(intr_handle->intr_vec);
 820 err_disable:
 821         rte_intr_efd_disable(intr_handle);
 822 err_out:
 823         /* Some of the error status returned by FW may not be from errno.h */
 824         if (rc > 0)
 825                 rc = -EIO;
 826
 827         return rc;
 828 }
 829
 830 static int bnxt_shutdown_nic(struct bnxt *bp)
 831 {
 832         bnxt_free_all_hwrm_resources(bp);
 833         bnxt_free_all_filters(bp);
 834         bnxt_free_all_vnics(bp);
 835         return 0;
 836 }
 837
 838 /*
 839  * Device configuration and status function
 840  */
 841
 842 uint32_t bnxt_get_speed_capabilities(struct bnxt *bp)
 843 {
 844         uint32_t link_speed = bp->link_info->support_speeds;
 845         uint32_t speed_capa = 0;
 846
 847         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_100MB)
 848                 speed_capa |= ETH_LINK_SPEED_100M;
 849         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_100MBHD)
 850                 speed_capa |= ETH_LINK_SPEED_100M_HD;
 851         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_1GB)
 852                 speed_capa |= ETH_LINK_SPEED_1G;
 853         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_2_5GB)
 854                 speed_capa |= ETH_LINK_SPEED_2_5G;
 855         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_10GB)
 856                 speed_capa |= ETH_LINK_SPEED_10G;
 857         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_20GB)
 858                 speed_capa |= ETH_LINK_SPEED_20G;
 859         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_25GB)
 860                 speed_capa |= ETH_LINK_SPEED_25G;
 861         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_40GB)
 862                 speed_capa |= ETH_LINK_SPEED_40G;
 863         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_50GB)
 864                 speed_capa |= ETH_LINK_SPEED_50G;
 865         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_100GB)
 866                 speed_capa |= ETH_LINK_SPEED_100G;
 867         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_PAM4_SPEEDS_50G)
 868                 speed_capa |= ETH_LINK_SPEED_50G;
 869         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_PAM4_SPEEDS_100G)
 870                 speed_capa |= ETH_LINK_SPEED_100G;
 871         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_PAM4_SPEEDS_200G)
 872                 speed_capa |= ETH_LINK_SPEED_200G;
 873
 874         if (bp->link_info->auto_mode ==
 875             HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_MODE_NONE)
 876                 speed_capa |= ETH_LINK_SPEED_FIXED;
 877         else
 878                 speed_capa |= ETH_LINK_SPEED_AUTONEG;
 879
 880         return speed_capa;
 881 }
 882
 883 static int bnxt_dev_info_get_op(struct rte_eth_dev *eth_dev,
 884                                 struct rte_eth_dev_info *dev_info)
 885 {
 886         struct rte_pci_device *pdev = RTE_DEV_TO_PCI(eth_dev->device);
 887         struct bnxt *bp = eth_dev->data->dev_private;
 888         uint16_t max_vnics, i, j, vpool, vrxq;
 889         unsigned int max_rx_rings;
 890         int rc;
 891
 892         rc = is_bnxt_in_error(bp);
 893         if (rc)
 894                 return rc;
 895
 896         /* MAC Specifics */
 897         dev_info->max_mac_addrs = bp->max_l2_ctx;
 898         dev_info->max_hash_mac_addrs = 0;
 899
 900         /* PF/VF specifics */
 901         if (BNXT_PF(bp))
 902                 dev_info->max_vfs = pdev->max_vfs;
 903
 904         max_rx_rings = BNXT_MAX_RINGS(bp);
 905         /* For the sake of symmetry, max_rx_queues = max_tx_queues */
 906         dev_info->max_rx_queues = max_rx_rings;
 907         dev_info->max_tx_queues = max_rx_rings;
 908         dev_info->reta_size = bnxt_rss_hash_tbl_size(bp);
 909         dev_info->hash_key_size = 40;
 910         max_vnics = bp->max_vnics;
 911
 912         /* MTU specifics */
 913         dev_info->min_mtu = RTE_ETHER_MIN_MTU;
 914         dev_info->max_mtu = BNXT_MAX_MTU;
 915
 916         /* Fast path specifics */
 917         dev_info->min_rx_bufsize = 1;
 918         dev_info->max_rx_pktlen = BNXT_MAX_PKT_LEN;
 919
 920         dev_info->rx_offload_capa = BNXT_DEV_RX_OFFLOAD_SUPPORT;
 921         if (bp->flags & BNXT_FLAG_PTP_SUPPORTED)
 922                 dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_TIMESTAMP;
 923         dev_info->tx_offload_capa = BNXT_DEV_TX_OFFLOAD_SUPPORT;
 924         dev_info->flow_type_rss_offloads = BNXT_ETH_RSS_SUPPORT;
 925
 926         dev_info->speed_capa = bnxt_get_speed_capabilities(bp);
 927
 928         /* *INDENT-OFF* */
 929         dev_info->default_rxconf = (struct rte_eth_rxconf) {
 930                 .rx_thresh = {
 931                         .pthresh = 8,
 932                         .hthresh = 8,
 933                         .wthresh = 0,
 934                 },
 935                 .rx_free_thresh = 32,
 936                 .rx_drop_en = BNXT_DEFAULT_RX_DROP_EN,
 937         };
 938
 939         dev_info->default_txconf = (struct rte_eth_txconf) {
 940                 .tx_thresh = {
 941                         .pthresh = 32,
 942                         .hthresh = 0,
 943                         .wthresh = 0,
 944                 },
 945                 .tx_free_thresh = 32,
 946                 .tx_rs_thresh = 32,
 947         };
 948         eth_dev->data->dev_conf.intr_conf.lsc = 1;
 949
 950         eth_dev->data->dev_conf.intr_conf.rxq = 1;
 951         dev_info->rx_desc_lim.nb_min = BNXT_MIN_RING_DESC;
 952         dev_info->rx_desc_lim.nb_max = BNXT_MAX_RX_RING_DESC;
 953         dev_info->tx_desc_lim.nb_min = BNXT_MIN_RING_DESC;
 954         dev_info->tx_desc_lim.nb_max = BNXT_MAX_TX_RING_DESC;
 955
 956         if (BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp)) {
 957                 dev_info->switch_info.name = eth_dev->device->name;
 958                 dev_info->switch_info.domain_id = bp->switch_domain_id;
 959                 dev_info->switch_info.port_id =
 960                                 BNXT_PF(bp) ? BNXT_SWITCH_PORT_ID_PF :
 961                                     BNXT_SWITCH_PORT_ID_TRUSTED_VF;
 962         }
 963
 964         /* *INDENT-ON* */
 965
 966         /*
 967          * TODO: default_rxconf, default_txconf, rx_desc_lim, and tx_desc_lim
 968          *       need further investigation.
 969          */
 970
 971         /* VMDq resources */
 972         vpool = 64; /* ETH_64_POOLS */
 973         vrxq = 128; /* ETH_VMDQ_DCB_NUM_QUEUES */
 974         for (i = 0; i < 4; vpool >>= 1, i++) {
 975                 if (max_vnics > vpool) {
 976                         for (j = 0; j < 5; vrxq >>= 1, j++) {
 977                                 if (dev_info->max_rx_queues > vrxq) {
 978                                         if (vpool > vrxq)
 979                                                 vpool = vrxq;
 980                                         goto found;
 981                                 }
 982                         }
 983                         /* Not enough resources to support VMDq */
 984                         break;
 985                 }
 986         }
 987         /* Not enough resources to support VMDq */
 988         vpool = 0;
 989         vrxq = 0;
 990 found:
 991         dev_info->max_vmdq_pools = vpool;
 992         dev_info->vmdq_queue_num = vrxq;
 993
 994         dev_info->vmdq_pool_base = 0;
 995         dev_info->vmdq_queue_base = 0;
 996
 997         return 0;
 998 }
 999
1000 /* Configure the device based on the configuration provided */
1001 static int bnxt_dev_configure_op(struct rte_eth_dev *eth_dev)
1002 {
1003         struct bnxt *bp = eth_dev->data->dev_private;
1004         uint64_t rx_offloads = eth_dev->data->dev_conf.rxmode.offloads;
1005         int rc;
1006
1007         bp->rx_queues = (void *)eth_dev->data->rx_queues;
1008         bp->tx_queues = (void *)eth_dev->data->tx_queues;
1009         bp->tx_nr_rings = eth_dev->data->nb_tx_queues;
1010         bp->rx_nr_rings = eth_dev->data->nb_rx_queues;
1011
1012         rc = is_bnxt_in_error(bp);
1013         if (rc)
1014                 return rc;
1015
1016         if (BNXT_VF(bp) && (bp->flags & BNXT_FLAG_NEW_RM)) {
1017                 rc = bnxt_hwrm_check_vf_rings(bp);
1018                 if (rc) {
1019                         PMD_DRV_LOG(ERR, "HWRM insufficient resources\n");
1020                         return -ENOSPC;
1021                 }
1022
1023                 /* If a resource has already been allocated - in this case
1024                  * it is the async completion ring, free it. Reallocate it after
1025                  * resource reservation. This will ensure the resource counts
1026                  * are calculated correctly.
1027                  */
1028
1029                 pthread_mutex_lock(&bp->def_cp_lock);
1030
1031                 if (!BNXT_HAS_NQ(bp) && bp->async_cp_ring) {
1032                         bnxt_disable_int(bp);
1033                         bnxt_free_cp_ring(bp, bp->async_cp_ring);
1034                 }
1035
1036                 rc = bnxt_hwrm_func_reserve_vf_resc(bp, false);
1037                 if (rc) {
1038                         PMD_DRV_LOG(ERR, "HWRM resource alloc fail:%x\n", rc);
1039                         pthread_mutex_unlock(&bp->def_cp_lock);
1040                         return -ENOSPC;
1041                 }
1042
1043                 if (!BNXT_HAS_NQ(bp) && bp->async_cp_ring) {
1044                         rc = bnxt_alloc_async_cp_ring(bp);
1045                         if (rc) {
1046                                 pthread_mutex_unlock(&bp->def_cp_lock);
1047                                 return rc;
1048                         }
1049                         bnxt_enable_int(bp);
1050                 }
1051
1052                 pthread_mutex_unlock(&bp->def_cp_lock);
1053         } else {
1054                 /* legacy driver needs to get updated values */
1055                 rc = bnxt_hwrm_func_qcaps(bp);
1056                 if (rc) {
1057                         PMD_DRV_LOG(ERR, "hwrm func qcaps fail:%d\n", rc);
1058                         return rc;
1059                 }
1060         }
1061
1062         /* Inherit new configurations */
1063         if (eth_dev->data->nb_rx_queues > bp->max_rx_rings ||
1064             eth_dev->data->nb_tx_queues > bp->max_tx_rings ||
1065             eth_dev->data->nb_rx_queues + eth_dev->data->nb_tx_queues
1066                 + BNXT_NUM_ASYNC_CPR(bp) > bp->max_cp_rings ||
1067             eth_dev->data->nb_rx_queues + eth_dev->data->nb_tx_queues >
1068             bp->max_stat_ctx)
1069                 goto resource_error;
1070
1071         if (BNXT_HAS_RING_GRPS(bp) &&
1072             (uint32_t)(eth_dev->data->nb_rx_queues) > bp->max_ring_grps)
1073                 goto resource_error;
1074
1075         if (!(eth_dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_RSS) &&
1076             bp->max_vnics < eth_dev->data->nb_rx_queues)
1077                 goto resource_error;
1078
1079         bp->rx_cp_nr_rings = bp->rx_nr_rings;
1080         bp->tx_cp_nr_rings = bp->tx_nr_rings;
1081
1082         if (eth_dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG)
1083                 rx_offloads |= DEV_RX_OFFLOAD_RSS_HASH;
1084         eth_dev->data->dev_conf.rxmode.offloads = rx_offloads;
1085
1086         if (rx_offloads & DEV_RX_OFFLOAD_JUMBO_FRAME) {
1087                 eth_dev->data->mtu =
1088                         eth_dev->data->dev_conf.rxmode.max_rx_pkt_len -
1089                         RTE_ETHER_HDR_LEN - RTE_ETHER_CRC_LEN - VLAN_TAG_SIZE *
1090                         BNXT_NUM_VLANS;
1091                 bnxt_mtu_set_op(eth_dev, eth_dev->data->mtu);
1092         }
1093         return 0;
1094
1095 resource_error:
1096         PMD_DRV_LOG(ERR,
1097                     "Insufficient resources to support requested config\n");
1098         PMD_DRV_LOG(ERR,
1099                     "Num Queues Requested: Tx %d, Rx %d\n",
1100                     eth_dev->data->nb_tx_queues,
1101                     eth_dev->data->nb_rx_queues);
1102         PMD_DRV_LOG(ERR,
1103                     "MAX: TxQ %d, RxQ %d, CQ %d Stat %d, Grp %d, Vnic %d\n",
1104                     bp->max_tx_rings, bp->max_rx_rings, bp->max_cp_rings,
1105                     bp->max_stat_ctx, bp->max_ring_grps, bp->max_vnics);
1106         return -ENOSPC;
1107 }
1108
1109 void bnxt_print_link_info(struct rte_eth_dev *eth_dev)
1110 {
1111         struct rte_eth_link *link = &eth_dev->data->dev_link;
1112
1113         if (link->link_status)
1114                 PMD_DRV_LOG(INFO, "Port %d Link Up - speed %u Mbps - %s\n",
1115                         eth_dev->data->port_id,
1116                         (uint32_t)link->link_speed,
1117                         (link->link_duplex == ETH_LINK_FULL_DUPLEX) ?
1118                         ("full-duplex") : ("half-duplex\n"));
1119         else
1120                 PMD_DRV_LOG(INFO, "Port %d Link Down\n",
1121                         eth_dev->data->port_id);
1122 }
1123
1124 /*
1125  * Determine whether the current configuration requires support for scattered
1126  * receive; return 1 if scattered receive is required and 0 if not.
1127  */
1128 static int bnxt_scattered_rx(struct rte_eth_dev *eth_dev)
1129 {
1130         uint16_t buf_size;
1131         int i;
1132
1133         if (eth_dev->data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_SCATTER)
1134                 return 1;
1135
1136         for (i = 0; i < eth_dev->data->nb_rx_queues; i++) {
1137                 struct bnxt_rx_queue *rxq = eth_dev->data->rx_queues[i];
1138
1139                 buf_size = (uint16_t)(rte_pktmbuf_data_room_size(rxq->mb_pool) -
1140                                       RTE_PKTMBUF_HEADROOM);
1141                 if (eth_dev->data->dev_conf.rxmode.max_rx_pkt_len > buf_size)
1142                         return 1;
1143         }
1144         return 0;
1145 }
1146
1147 static eth_rx_burst_t
1148 bnxt_receive_function(struct rte_eth_dev *eth_dev)
1149 {
1150         struct bnxt *bp = eth_dev->data->dev_private;
1151
1152 #if defined(RTE_ARCH_X86) || defined(RTE_ARCH_ARM64)
1153 #ifndef RTE_LIBRTE_IEEE1588
1154         /*
1155          * Vector mode receive can be enabled only if scatter rx is not
1156          * in use and rx offloads are limited to VLAN stripping and
1157          * CRC stripping.
1158          */
1159         if (!eth_dev->data->scattered_rx &&
1160             !(eth_dev->data->dev_conf.rxmode.offloads &
1161               ~(DEV_RX_OFFLOAD_VLAN_STRIP |
1162                 DEV_RX_OFFLOAD_KEEP_CRC |
1163                 DEV_RX_OFFLOAD_JUMBO_FRAME |
1164                 DEV_RX_OFFLOAD_IPV4_CKSUM |
1165                 DEV_RX_OFFLOAD_UDP_CKSUM |
1166                 DEV_RX_OFFLOAD_TCP_CKSUM |
1167                 DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM |
1168                 DEV_RX_OFFLOAD_RSS_HASH |
1169                 DEV_RX_OFFLOAD_VLAN_FILTER)) &&
1170             !BNXT_TRUFLOW_EN(bp) && BNXT_NUM_ASYNC_CPR(bp)) {
1171                 PMD_DRV_LOG(INFO, "Using vector mode receive for port %d\n",
1172                             eth_dev->data->port_id);
1173                 bp->flags |= BNXT_FLAG_RX_VECTOR_PKT_MODE;
1174                 return bnxt_recv_pkts_vec;
1175         }
1176         PMD_DRV_LOG(INFO, "Vector mode receive disabled for port %d\n",
1177                     eth_dev->data->port_id);
1178         PMD_DRV_LOG(INFO,
1179                     "Port %d scatter: %d rx offload: %" PRIX64 "\n",
1180                     eth_dev->data->port_id,
1181                     eth_dev->data->scattered_rx,
1182                     eth_dev->data->dev_conf.rxmode.offloads);
1183 #endif
1184 #endif
1185         bp->flags &= ~BNXT_FLAG_RX_VECTOR_PKT_MODE;
1186         return bnxt_recv_pkts;
1187 }
1188
1189 static eth_tx_burst_t
1190 bnxt_transmit_function(__rte_unused struct rte_eth_dev *eth_dev)
1191 {
1192 #if defined(RTE_ARCH_X86) || defined(RTE_ARCH_ARM64)
1193 #ifndef RTE_LIBRTE_IEEE1588
1194         struct bnxt *bp = eth_dev->data->dev_private;
1195
1196         /*
1197          * Vector mode transmit can be enabled only if not using scatter rx
1198          * or tx offloads.
1199          */
1200         if (!eth_dev->data->scattered_rx &&
1201             !eth_dev->data->dev_conf.txmode.offloads &&
1202             !BNXT_TRUFLOW_EN(bp)) {
1203                 PMD_DRV_LOG(INFO, "Using vector mode transmit for port %d\n",
1204                             eth_dev->data->port_id);
1205                 return bnxt_xmit_pkts_vec;
1206         }
1207         PMD_DRV_LOG(INFO, "Vector mode transmit disabled for port %d\n",
1208                     eth_dev->data->port_id);
1209         PMD_DRV_LOG(INFO,
1210                     "Port %d scatter: %d tx offload: %" PRIX64 "\n",
1211                     eth_dev->data->port_id,
1212                     eth_dev->data->scattered_rx,
1213                     eth_dev->data->dev_conf.txmode.offloads);
1214 #endif
1215 #endif
1216         return bnxt_xmit_pkts;
1217 }
1218
1219 static int bnxt_handle_if_change_status(struct bnxt *bp)
1220 {
1221         int rc;
1222
1223         /* Since fw has undergone a reset and lost all contexts,
1224          * set fatal flag to not issue hwrm during cleanup
1225          */
1226         bp->flags |= BNXT_FLAG_FATAL_ERROR;
1227         bnxt_uninit_resources(bp, true);
1228
1229         /* clear fatal flag so that re-init happens */
1230         bp->flags &= ~BNXT_FLAG_FATAL_ERROR;
1231         rc = bnxt_init_resources(bp, true);
1232
1233         bp->flags &= ~BNXT_FLAG_IF_CHANGE_HOT_FW_RESET_DONE;
1234
1235         return rc;
1236 }
1237
1238 static int bnxt_dev_start_op(struct rte_eth_dev *eth_dev)
1239 {
1240         struct bnxt *bp = eth_dev->data->dev_private;
1241         uint64_t rx_offloads = eth_dev->data->dev_conf.rxmode.offloads;
1242         int vlan_mask = 0;
1243         int rc, retry_cnt = BNXT_IF_CHANGE_RETRY_COUNT;
1244
1245         if (!eth_dev->data->nb_tx_queues || !eth_dev->data->nb_rx_queues) {
1246                 PMD_DRV_LOG(ERR, "Queues are not configured yet!\n");
1247                 return -EINVAL;
1248         }
1249
1250         if (bp->rx_cp_nr_rings > RTE_ETHDEV_QUEUE_STAT_CNTRS) {
1251                 PMD_DRV_LOG(ERR,
1252                         "RxQ cnt %d > CONFIG_RTE_ETHDEV_QUEUE_STAT_CNTRS %d\n",
1253                         bp->rx_cp_nr_rings, RTE_ETHDEV_QUEUE_STAT_CNTRS);
1254         }
1255
1256         do {
1257                 rc = bnxt_hwrm_if_change(bp, true);
1258                 if (rc == 0 || rc != -EAGAIN)
1259                         break;
1260
1261                 rte_delay_ms(BNXT_IF_CHANGE_RETRY_INTERVAL);
1262         } while (retry_cnt--);
1263
1264         if (rc)
1265                 return rc;
1266
1267         if (bp->flags & BNXT_FLAG_IF_CHANGE_HOT_FW_RESET_DONE) {
1268                 rc = bnxt_handle_if_change_status(bp);
1269                 if (rc)
1270                         return rc;
1271         }
1272
1273         bnxt_enable_int(bp);
1274
1275         rc = bnxt_init_chip(bp);
1276         if (rc)
1277                 goto error;
1278
1279         eth_dev->data->scattered_rx = bnxt_scattered_rx(eth_dev);
1280         eth_dev->data->dev_started = 1;
1281
1282         bnxt_link_update(eth_dev, 1, ETH_LINK_UP);
1283
1284         if (rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER)
1285                 vlan_mask |= ETH_VLAN_FILTER_MASK;
1286         if (rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
1287                 vlan_mask |= ETH_VLAN_STRIP_MASK;
1288         rc = bnxt_vlan_offload_set_op(eth_dev, vlan_mask);
1289         if (rc)
1290                 goto error;
1291
1292         /* Initialize bnxt ULP port details */
1293         rc = bnxt_ulp_port_init(bp);
1294         if (rc)
1295                 goto error;
1296
1297         eth_dev->rx_pkt_burst = bnxt_receive_function(eth_dev);
1298         eth_dev->tx_pkt_burst = bnxt_transmit_function(eth_dev);
1299
1300         bnxt_schedule_fw_health_check(bp);
1301
1302         return 0;
1303
1304 error:
1305         bnxt_shutdown_nic(bp);
1306         bnxt_free_tx_mbufs(bp);
1307         bnxt_free_rx_mbufs(bp);
1308         bnxt_hwrm_if_change(bp, false);
1309         eth_dev->data->dev_started = 0;
1310         return rc;
1311 }
1312
1313 static int bnxt_dev_set_link_up_op(struct rte_eth_dev *eth_dev)
1314 {
1315         struct bnxt *bp = eth_dev->data->dev_private;
1316         int rc = 0;
1317
1318         if (!bp->link_info->link_up)
1319                 rc = bnxt_set_hwrm_link_config(bp, true);
1320         if (!rc)
1321                 eth_dev->data->dev_link.link_status = 1;
1322
1323         bnxt_print_link_info(eth_dev);
1324         return rc;
1325 }
1326
1327 static int bnxt_dev_set_link_down_op(struct rte_eth_dev *eth_dev)
1328 {
1329         struct bnxt *bp = eth_dev->data->dev_private;
1330
1331         eth_dev->data->dev_link.link_status = 0;
1332         bnxt_set_hwrm_link_config(bp, false);
1333         bp->link_info->link_up = 0;
1334
1335         return 0;
1336 }
1337
1338 static void bnxt_free_switch_domain(struct bnxt *bp)
1339 {
1340         if (bp->switch_domain_id)
1341                 rte_eth_switch_domain_free(bp->switch_domain_id);
1342 }
1343
1344 /* Unload the driver, release resources */
1345 static void bnxt_dev_stop_op(struct rte_eth_dev *eth_dev)
1346 {
1347         struct bnxt *bp = eth_dev->data->dev_private;
1348         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1349         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1350
1351         eth_dev->data->dev_started = 0;
1352         eth_dev->data->scattered_rx = 0;
1353
1354         /* Prevent crashes when queues are still in use */
1355         eth_dev->rx_pkt_burst = &bnxt_dummy_recv_pkts;
1356         eth_dev->tx_pkt_burst = &bnxt_dummy_xmit_pkts;
1357
1358         bnxt_disable_int(bp);
1359
1360         /* disable uio/vfio intr/eventfd mapping */
1361         rte_intr_disable(intr_handle);
1362
1363         /* Stop the child representors for this device */
1364         bnxt_rep_stop_all(bp);
1365
1366         /* delete the bnxt ULP port details */
1367         bnxt_ulp_port_deinit(bp);
1368
1369         bnxt_cancel_fw_health_check(bp);
1370
1371         /* Do not bring link down during reset recovery */
1372         if (!is_bnxt_in_error(bp))
1373                 bnxt_dev_set_link_down_op(eth_dev);
1374
1375         /* Wait for link to be reset and the async notification to process.
1376          * During reset recovery, there is no need to wait and
1377          * VF/NPAR functions do not have privilege to change PHY config.
1378          */
1379         if (!is_bnxt_in_error(bp) && BNXT_SINGLE_PF(bp))
1380                 bnxt_link_update(eth_dev, 1, ETH_LINK_DOWN);
1381
1382         /* Clean queue intr-vector mapping */
1383         rte_intr_efd_disable(intr_handle);
1384         if (intr_handle->intr_vec != NULL) {
1385                 rte_free(intr_handle->intr_vec);
1386                 intr_handle->intr_vec = NULL;
1387         }
1388
1389         bnxt_hwrm_port_clr_stats(bp);
1390         bnxt_free_tx_mbufs(bp);
1391         bnxt_free_rx_mbufs(bp);
1392         /* Process any remaining notifications in default completion queue */
1393         bnxt_int_handler(eth_dev);
1394         bnxt_shutdown_nic(bp);
1395         bnxt_hwrm_if_change(bp, false);
1396
1397         rte_free(bp->mark_table);
1398         bp->mark_table = NULL;
1399
1400         bp->flags &= ~BNXT_FLAG_RX_VECTOR_PKT_MODE;
1401         bp->rx_cosq_cnt = 0;
1402         /* All filters are deleted on a port stop. */
1403         if (BNXT_FLOW_XSTATS_EN(bp))
1404                 bp->flow_stat->flow_count = 0;
1405 }
1406
1407 static int bnxt_dev_close_op(struct rte_eth_dev *eth_dev)
1408 {
1409         struct bnxt *bp = eth_dev->data->dev_private;
1410
1411         /* cancel the recovery handler before remove dev */
1412         rte_eal_alarm_cancel(bnxt_dev_reset_and_resume, (void *)bp);
1413         rte_eal_alarm_cancel(bnxt_dev_recover, (void *)bp);
1414         bnxt_cancel_fc_thread(bp);
1415
1416         if (eth_dev->data->dev_started)
1417                 bnxt_dev_stop_op(eth_dev);
1418
1419         bnxt_free_switch_domain(bp);
1420
1421         bnxt_uninit_resources(bp, false);
1422
1423         bnxt_free_leds_info(bp);
1424         bnxt_free_cos_queues(bp);
1425         bnxt_free_link_info(bp);
1426         bnxt_free_pf_info(bp);
1427         bnxt_free_parent_info(bp);
1428
1429         eth_dev->dev_ops = NULL;
1430         eth_dev->rx_pkt_burst = NULL;
1431         eth_dev->tx_pkt_burst = NULL;
1432
1433         rte_memzone_free((const struct rte_memzone *)bp->tx_mem_zone);
1434         bp->tx_mem_zone = NULL;
1435         rte_memzone_free((const struct rte_memzone *)bp->rx_mem_zone);
1436         bp->rx_mem_zone = NULL;
1437
1438         bnxt_hwrm_free_vf_info(bp);
1439
1440         rte_free(bp->grp_info);
1441         bp->grp_info = NULL;
1442
1443         return 0;
1444 }
1445
1446 static void bnxt_mac_addr_remove_op(struct rte_eth_dev *eth_dev,
1447                                     uint32_t index)
1448 {
1449         struct bnxt *bp = eth_dev->data->dev_private;
1450         uint64_t pool_mask = eth_dev->data->mac_pool_sel[index];
1451         struct bnxt_vnic_info *vnic;
1452         struct bnxt_filter_info *filter, *temp_filter;
1453         uint32_t i;
1454
1455         if (is_bnxt_in_error(bp))
1456                 return;
1457
1458         /*
1459          * Loop through all VNICs from the specified filter flow pools to
1460          * remove the corresponding MAC addr filter
1461          */
1462         for (i = 0; i < bp->nr_vnics; i++) {
1463                 if (!(pool_mask & (1ULL << i)))
1464                         continue;
1465
1466                 vnic = &bp->vnic_info[i];
1467                 filter = STAILQ_FIRST(&vnic->filter);
1468                 while (filter) {
1469                         temp_filter = STAILQ_NEXT(filter, next);
1470                         if (filter->mac_index == index) {
1471                                 STAILQ_REMOVE(&vnic->filter, filter,
1472                                                 bnxt_filter_info, next);
1473                                 bnxt_hwrm_clear_l2_filter(bp, filter);
1474                                 bnxt_free_filter(bp, filter);
1475                         }
1476                         filter = temp_filter;
1477                 }
1478         }
1479 }
1480
1481 static int bnxt_add_mac_filter(struct bnxt *bp, struct bnxt_vnic_info *vnic,
1482                                struct rte_ether_addr *mac_addr, uint32_t index,
1483                                uint32_t pool)
1484 {
1485         struct bnxt_filter_info *filter;
1486         int rc = 0;
1487
1488         /* Attach requested MAC address to the new l2_filter */
1489         STAILQ_FOREACH(filter, &vnic->filter, next) {
1490                 if (filter->mac_index == index) {
1491                         PMD_DRV_LOG(DEBUG,
1492                                     "MAC addr already existed for pool %d\n",
1493                                     pool);
1494                         return 0;
1495                 }
1496         }
1497
1498         filter = bnxt_alloc_filter(bp);
1499         if (!filter) {
1500                 PMD_DRV_LOG(ERR, "L2 filter alloc failed\n");
1501                 return -ENODEV;
1502         }
1503
1504         /* bnxt_alloc_filter copies default MAC to filter->l2_addr. So,
1505          * if the MAC that's been programmed now is a different one, then,
1506          * copy that addr to filter->l2_addr
1507          */
1508         if (mac_addr)
1509                 memcpy(filter->l2_addr, mac_addr, RTE_ETHER_ADDR_LEN);
1510         filter->flags |= HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_OUTERMOST;
1511
1512         rc = bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id, filter);
1513         if (!rc) {
1514                 filter->mac_index = index;
1515                 if (filter->mac_index == 0)
1516                         STAILQ_INSERT_HEAD(&vnic->filter, filter, next);
1517                 else
1518                         STAILQ_INSERT_TAIL(&vnic->filter, filter, next);
1519         } else {
1520                 bnxt_free_filter(bp, filter);
1521         }
1522
1523         return rc;
1524 }
1525
1526 static int bnxt_mac_addr_add_op(struct rte_eth_dev *eth_dev,
1527                                 struct rte_ether_addr *mac_addr,
1528                                 uint32_t index, uint32_t pool)
1529 {
1530         struct bnxt *bp = eth_dev->data->dev_private;
1531         struct bnxt_vnic_info *vnic = &bp->vnic_info[pool];
1532         int rc = 0;
1533
1534         rc = is_bnxt_in_error(bp);
1535         if (rc)
1536                 return rc;
1537
1538         if (BNXT_VF(bp) & !BNXT_VF_IS_TRUSTED(bp)) {
1539                 PMD_DRV_LOG(ERR, "Cannot add MAC address to a VF interface\n");
1540                 return -ENOTSUP;
1541         }
1542
1543         if (!vnic) {
1544                 PMD_DRV_LOG(ERR, "VNIC not found for pool %d!\n", pool);
1545                 return -EINVAL;
1546         }
1547
1548         /* Filter settings will get applied when port is started */
1549         if (!eth_dev->data->dev_started)
1550                 return 0;
1551
1552         rc = bnxt_add_mac_filter(bp, vnic, mac_addr, index, pool);
1553
1554         return rc;
1555 }
1556
1557 int bnxt_link_update(struct rte_eth_dev *eth_dev, int wait_to_complete,
1558                      bool exp_link_status)
1559 {
1560         int rc = 0;
1561         struct bnxt *bp = eth_dev->data->dev_private;
1562         struct rte_eth_link new;
1563         int cnt = exp_link_status ? BNXT_LINK_UP_WAIT_CNT :
1564                   BNXT_LINK_DOWN_WAIT_CNT;
1565
1566         rc = is_bnxt_in_error(bp);
1567         if (rc)
1568                 return rc;
1569
1570         memset(&new, 0, sizeof(new));
1571         do {
1572                 /* Retrieve link info from hardware */
1573                 rc = bnxt_get_hwrm_link_config(bp, &new);
1574                 if (rc) {
1575                         new.link_speed = ETH_LINK_SPEED_100M;
1576                         new.link_duplex = ETH_LINK_FULL_DUPLEX;
1577                         PMD_DRV_LOG(ERR,
1578                                 "Failed to retrieve link rc = 0x%x!\n", rc);
1579                         goto out;
1580                 }
1581
1582                 if (!wait_to_complete || new.link_status == exp_link_status)
1583                         break;
1584
1585                 rte_delay_ms(BNXT_LINK_WAIT_INTERVAL);
1586         } while (cnt--);
1587
1588 out:
1589         /* Timed out or success */
1590         if (new.link_status != eth_dev->data->dev_link.link_status ||
1591         new.link_speed != eth_dev->data->dev_link.link_speed) {
1592                 rte_eth_linkstatus_set(eth_dev, &new);
1593
1594                 rte_eth_dev_callback_process(eth_dev,
1595                                              RTE_ETH_EVENT_INTR_LSC,
1596                                              NULL);
1597
1598                 bnxt_print_link_info(eth_dev);
1599         }
1600
1601         return rc;
1602 }
1603
1604 int bnxt_link_update_op(struct rte_eth_dev *eth_dev,
1605                         int wait_to_complete)
1606 {
1607         return bnxt_link_update(eth_dev, wait_to_complete, ETH_LINK_UP);
1608 }
1609
1610 static int bnxt_promiscuous_enable_op(struct rte_eth_dev *eth_dev)
1611 {
1612         struct bnxt *bp = eth_dev->data->dev_private;
1613         struct bnxt_vnic_info *vnic;
1614         uint32_t old_flags;
1615         int rc;
1616
1617         rc = is_bnxt_in_error(bp);
1618         if (rc)
1619                 return rc;
1620
1621         /* Filter settings will get applied when port is started */
1622         if (!eth_dev->data->dev_started)
1623                 return 0;
1624
1625         if (bp->vnic_info == NULL)
1626                 return 0;
1627
1628         vnic = BNXT_GET_DEFAULT_VNIC(bp);
1629
1630         old_flags = vnic->flags;
1631         vnic->flags |= BNXT_VNIC_INFO_PROMISC;
1632         rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1633         if (rc != 0)
1634                 vnic->flags = old_flags;
1635
1636         return rc;
1637 }
1638
1639 static int bnxt_promiscuous_disable_op(struct rte_eth_dev *eth_dev)
1640 {
1641         struct bnxt *bp = eth_dev->data->dev_private;
1642         struct bnxt_vnic_info *vnic;
1643         uint32_t old_flags;
1644         int rc;
1645
1646         rc = is_bnxt_in_error(bp);
1647         if (rc)
1648                 return rc;
1649
1650         /* Filter settings will get applied when port is started */
1651         if (!eth_dev->data->dev_started)
1652                 return 0;
1653
1654         if (bp->vnic_info == NULL)
1655                 return 0;
1656
1657         vnic = BNXT_GET_DEFAULT_VNIC(bp);
1658
1659         old_flags = vnic->flags;
1660         vnic->flags &= ~BNXT_VNIC_INFO_PROMISC;
1661         rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1662         if (rc != 0)
1663                 vnic->flags = old_flags;
1664
1665         return rc;
1666 }
1667
1668 static int bnxt_allmulticast_enable_op(struct rte_eth_dev *eth_dev)
1669 {
1670         struct bnxt *bp = eth_dev->data->dev_private;
1671         struct bnxt_vnic_info *vnic;
1672         uint32_t old_flags;
1673         int rc;
1674
1675         rc = is_bnxt_in_error(bp);
1676         if (rc)
1677                 return rc;
1678
1679         /* Filter settings will get applied when port is started */
1680         if (!eth_dev->data->dev_started)
1681                 return 0;
1682
1683         if (bp->vnic_info == NULL)
1684                 return 0;
1685
1686         vnic = BNXT_GET_DEFAULT_VNIC(bp);
1687
1688         old_flags = vnic->flags;
1689         vnic->flags |= BNXT_VNIC_INFO_ALLMULTI;
1690         rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1691         if (rc != 0)
1692                 vnic->flags = old_flags;
1693
1694         return rc;
1695 }
1696
1697 static int bnxt_allmulticast_disable_op(struct rte_eth_dev *eth_dev)
1698 {
1699         struct bnxt *bp = eth_dev->data->dev_private;
1700         struct bnxt_vnic_info *vnic;
1701         uint32_t old_flags;
1702         int rc;
1703
1704         rc = is_bnxt_in_error(bp);
1705         if (rc)
1706                 return rc;
1707
1708         /* Filter settings will get applied when port is started */
1709         if (!eth_dev->data->dev_started)
1710                 return 0;
1711
1712         if (bp->vnic_info == NULL)
1713                 return 0;
1714
1715         vnic = BNXT_GET_DEFAULT_VNIC(bp);
1716
1717         old_flags = vnic->flags;
1718         vnic->flags &= ~BNXT_VNIC_INFO_ALLMULTI;
1719         rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1720         if (rc != 0)
1721                 vnic->flags = old_flags;
1722
1723         return rc;
1724 }
1725
1726 /* Return bnxt_rx_queue pointer corresponding to a given rxq. */
1727 static struct bnxt_rx_queue *bnxt_qid_to_rxq(struct bnxt *bp, uint16_t qid)
1728 {
1729         if (qid >= bp->rx_nr_rings)
1730                 return NULL;
1731
1732         return bp->eth_dev->data->rx_queues[qid];
1733 }
1734
1735 /* Return rxq corresponding to a given rss table ring/group ID. */
1736 static uint16_t bnxt_rss_to_qid(struct bnxt *bp, uint16_t fwr)
1737 {
1738         struct bnxt_rx_queue *rxq;
1739         unsigned int i;
1740
1741         if (!BNXT_HAS_RING_GRPS(bp)) {
1742                 for (i = 0; i < bp->rx_nr_rings; i++) {
1743                         rxq = bp->eth_dev->data->rx_queues[i];
1744                         if (rxq->rx_ring->rx_ring_struct->fw_ring_id == fwr)
1745                                 return rxq->index;
1746                 }
1747         } else {
1748                 for (i = 0; i < bp->rx_nr_rings; i++) {
1749                         if (bp->grp_info[i].fw_grp_id == fwr)
1750                                 return i;
1751                 }
1752         }
1753
1754         return INVALID_HW_RING_ID;
1755 }
1756
1757 static int bnxt_reta_update_op(struct rte_eth_dev *eth_dev,
1758                             struct rte_eth_rss_reta_entry64 *reta_conf,
1759                             uint16_t reta_size)
1760 {
1761         struct bnxt *bp = eth_dev->data->dev_private;
1762         struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
1763         struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp);
1764         uint16_t tbl_size = bnxt_rss_hash_tbl_size(bp);
1765         uint16_t idx, sft;
1766         int i, rc;
1767
1768         rc = is_bnxt_in_error(bp);
1769         if (rc)
1770                 return rc;
1771
1772         if (!vnic->rss_table)
1773                 return -EINVAL;
1774
1775         if (!(dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG))
1776                 return -EINVAL;
1777
1778         if (reta_size != tbl_size) {
1779                 PMD_DRV_LOG(ERR, "The configured hash table lookup size "
1780                         "(%d) must equal the size supported by the hardware "
1781                         "(%d)\n", reta_size, tbl_size);
1782                 return -EINVAL;
1783         }
1784
1785         for (i = 0; i < reta_size; i++) {
1786                 struct bnxt_rx_queue *rxq;
1787
1788                 idx = i / RTE_RETA_GROUP_SIZE;
1789                 sft = i % RTE_RETA_GROUP_SIZE;
1790
1791                 if (!(reta_conf[idx].mask & (1ULL << sft)))
1792                         continue;
1793
1794                 rxq = bnxt_qid_to_rxq(bp, reta_conf[idx].reta[sft]);
1795                 if (!rxq) {
1796                         PMD_DRV_LOG(ERR, "Invalid ring in reta_conf.\n");
1797                         return -EINVAL;
1798                 }
1799
1800                 if (BNXT_CHIP_THOR(bp)) {
1801                         vnic->rss_table[i * 2] =
1802                                 rxq->rx_ring->rx_ring_struct->fw_ring_id;
1803                         vnic->rss_table[i * 2 + 1] =
1804                                 rxq->cp_ring->cp_ring_struct->fw_ring_id;
1805                 } else {
1806                         vnic->rss_table[i] =
1807                             vnic->fw_grp_ids[reta_conf[idx].reta[sft]];
1808                 }
1809         }
1810
1811         bnxt_hwrm_vnic_rss_cfg(bp, vnic);
1812         return 0;
1813 }
1814
1815 static int bnxt_reta_query_op(struct rte_eth_dev *eth_dev,
1816                               struct rte_eth_rss_reta_entry64 *reta_conf,
1817                               uint16_t reta_size)
1818 {
1819         struct bnxt *bp = eth_dev->data->dev_private;
1820         struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp);
1821         uint16_t tbl_size = bnxt_rss_hash_tbl_size(bp);
1822         uint16_t idx, sft, i;
1823         int rc;
1824
1825         rc = is_bnxt_in_error(bp);
1826         if (rc)
1827                 return rc;
1828
1829         /* Retrieve from the default VNIC */
1830         if (!vnic)
1831                 return -EINVAL;
1832         if (!vnic->rss_table)
1833                 return -EINVAL;
1834
1835         if (reta_size != tbl_size) {
1836                 PMD_DRV_LOG(ERR, "The configured hash table lookup size "
1837                         "(%d) must equal the size supported by the hardware "
1838                         "(%d)\n", reta_size, tbl_size);
1839                 return -EINVAL;
1840         }
1841
1842         for (idx = 0, i = 0; i < reta_size; i++) {
1843                 idx = i / RTE_RETA_GROUP_SIZE;
1844                 sft = i % RTE_RETA_GROUP_SIZE;
1845
1846                 if (reta_conf[idx].mask & (1ULL << sft)) {
1847                         uint16_t qid;
1848
1849                         if (BNXT_CHIP_THOR(bp))
1850                                 qid = bnxt_rss_to_qid(bp,
1851                                                       vnic->rss_table[i * 2]);
1852                         else
1853                                 qid = bnxt_rss_to_qid(bp, vnic->rss_table[i]);
1854
1855                         if (qid == INVALID_HW_RING_ID) {
1856                                 PMD_DRV_LOG(ERR, "Inv. entry in rss table.\n");
1857                                 return -EINVAL;
1858                         }
1859                         reta_conf[idx].reta[sft] = qid;
1860                 }
1861         }
1862
1863         return 0;
1864 }
1865
1866 static int bnxt_rss_hash_update_op(struct rte_eth_dev *eth_dev,
1867                                    struct rte_eth_rss_conf *rss_conf)
1868 {
1869         struct bnxt *bp = eth_dev->data->dev_private;
1870         struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
1871         struct bnxt_vnic_info *vnic;
1872         int rc;
1873
1874         rc = is_bnxt_in_error(bp);
1875         if (rc)
1876                 return rc;
1877
1878         /*
1879          * If RSS enablement were different than dev_configure,
1880          * then return -EINVAL
1881          */
1882         if (dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG) {
1883                 if (!rss_conf->rss_hf)
1884                         PMD_DRV_LOG(ERR, "Hash type NONE\n");
1885         } else {
1886                 if (rss_conf->rss_hf & BNXT_ETH_RSS_SUPPORT)
1887                         return -EINVAL;
1888         }
1889
1890         bp->flags |= BNXT_FLAG_UPDATE_HASH;
1891         memcpy(&eth_dev->data->dev_conf.rx_adv_conf.rss_conf,
1892                rss_conf,
1893                sizeof(*rss_conf));
1894
1895         /* Update the default RSS VNIC(s) */
1896         vnic = BNXT_GET_DEFAULT_VNIC(bp);
1897         vnic->hash_type = bnxt_rte_to_hwrm_hash_types(rss_conf->rss_hf);
1898
1899         /*
1900          * If hashkey is not specified, use the previously configured
1901          * hashkey
1902          */
1903         if (!rss_conf->rss_key)
1904                 goto rss_config;
1905
1906         if (rss_conf->rss_key_len != HW_HASH_KEY_SIZE) {
1907                 PMD_DRV_LOG(ERR,
1908                             "Invalid hashkey length, should be 16 bytes\n");
1909                 return -EINVAL;
1910         }
1911         memcpy(vnic->rss_hash_key, rss_conf->rss_key, rss_conf->rss_key_len);
1912
1913 rss_config:
1914         bnxt_hwrm_vnic_rss_cfg(bp, vnic);
1915         return 0;
1916 }
1917
1918 static int bnxt_rss_hash_conf_get_op(struct rte_eth_dev *eth_dev,
1919                                      struct rte_eth_rss_conf *rss_conf)
1920 {
1921         struct bnxt *bp = eth_dev->data->dev_private;
1922         struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp);
1923         int len, rc;
1924         uint32_t hash_types;
1925
1926         rc = is_bnxt_in_error(bp);
1927         if (rc)
1928                 return rc;
1929
1930         /* RSS configuration is the same for all VNICs */
1931         if (vnic && vnic->rss_hash_key) {
1932                 if (rss_conf->rss_key) {
1933                         len = rss_conf->rss_key_len <= HW_HASH_KEY_SIZE ?
1934                               rss_conf->rss_key_len : HW_HASH_KEY_SIZE;
1935                         memcpy(rss_conf->rss_key, vnic->rss_hash_key, len);
1936                 }
1937
1938                 hash_types = vnic->hash_type;
1939                 rss_conf->rss_hf = 0;
1940                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV4) {
1941                         rss_conf->rss_hf |= ETH_RSS_IPV4;
1942                         hash_types &= ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV4;
1943                 }
1944                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV4) {
1945                         rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP;
1946                         hash_types &=
1947                                 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV4;
1948                 }
1949                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV4) {
1950                         rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
1951                         hash_types &=
1952                                 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV4;
1953                 }
1954                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6) {
1955                         rss_conf->rss_hf |= ETH_RSS_IPV6;
1956                         hash_types &= ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6;
1957                 }
1958                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV6) {
1959                         rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV6_TCP;
1960                         hash_types &=
1961                                 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV6;
1962                 }
1963                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV6) {
1964                         rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;
1965                         hash_types &=
1966                                 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV6;
1967                 }
1968                 if (hash_types) {
1969                         PMD_DRV_LOG(ERR,
1970                                 "Unknown RSS config from firmware (%08x), RSS disabled",
1971                                 vnic->hash_type);
1972                         return -ENOTSUP;
1973                 }
1974         } else {
1975                 rss_conf->rss_hf = 0;
1976         }
1977         return 0;
1978 }
1979
1980 static int bnxt_flow_ctrl_get_op(struct rte_eth_dev *dev,
1981                                struct rte_eth_fc_conf *fc_conf)
1982 {
1983         struct bnxt *bp = dev->data->dev_private;
1984         struct rte_eth_link link_info;
1985         int rc;
1986
1987         rc = is_bnxt_in_error(bp);
1988         if (rc)
1989                 return rc;
1990
1991         rc = bnxt_get_hwrm_link_config(bp, &link_info);
1992         if (rc)
1993                 return rc;
1994
1995         memset(fc_conf, 0, sizeof(*fc_conf));
1996         if (bp->link_info->auto_pause)
1997                 fc_conf->autoneg = 1;
1998         switch (bp->link_info->pause) {
1999         case 0:
2000                 fc_conf->mode = RTE_FC_NONE;
2001                 break;
2002         case HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_TX:
2003                 fc_conf->mode = RTE_FC_TX_PAUSE;
2004                 break;
2005         case HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_RX:
2006                 fc_conf->mode = RTE_FC_RX_PAUSE;
2007                 break;
2008         case (HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_TX |
2009                         HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_RX):
2010                 fc_conf->mode = RTE_FC_FULL;
2011                 break;
2012         }
2013         return 0;
2014 }
2015
2016 static int bnxt_flow_ctrl_set_op(struct rte_eth_dev *dev,
2017                                struct rte_eth_fc_conf *fc_conf)
2018 {
2019         struct bnxt *bp = dev->data->dev_private;
2020         int rc;
2021
2022         rc = is_bnxt_in_error(bp);
2023         if (rc)
2024                 return rc;
2025
2026         if (!BNXT_SINGLE_PF(bp) || BNXT_VF(bp)) {
2027                 PMD_DRV_LOG(ERR, "Flow Control Settings cannot be modified\n");
2028                 return -ENOTSUP;
2029         }
2030
2031         switch (fc_conf->mode) {
2032         case RTE_FC_NONE:
2033                 bp->link_info->auto_pause = 0;
2034                 bp->link_info->force_pause = 0;
2035                 break;
2036         case RTE_FC_RX_PAUSE:
2037                 if (fc_conf->autoneg) {
2038                         bp->link_info->auto_pause =
2039                                         HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_RX;
2040                         bp->link_info->force_pause = 0;
2041                 } else {
2042                         bp->link_info->auto_pause = 0;
2043                         bp->link_info->force_pause =
2044                                         HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_RX;
2045                 }
2046                 break;
2047         case RTE_FC_TX_PAUSE:
2048                 if (fc_conf->autoneg) {
2049                         bp->link_info->auto_pause =
2050                                         HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_TX;
2051                         bp->link_info->force_pause = 0;
2052                 } else {
2053                         bp->link_info->auto_pause = 0;
2054                         bp->link_info->force_pause =
2055                                         HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_TX;
2056                 }
2057                 break;
2058         case RTE_FC_FULL:
2059                 if (fc_conf->autoneg) {
2060                         bp->link_info->auto_pause =
2061                                         HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_TX |
2062                                         HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_RX;
2063                         bp->link_info->force_pause = 0;
2064                 } else {
2065                         bp->link_info->auto_pause = 0;
2066                         bp->link_info->force_pause =
2067                                         HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_TX |
2068                                         HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_RX;
2069                 }
2070                 break;
2071         }
2072         return bnxt_set_hwrm_link_config(bp, true);
2073 }
2074
2075 /* Add UDP tunneling port */
2076 static int
2077 bnxt_udp_tunnel_port_add_op(struct rte_eth_dev *eth_dev,
2078                          struct rte_eth_udp_tunnel *udp_tunnel)
2079 {
2080         struct bnxt *bp = eth_dev->data->dev_private;
2081         uint16_t tunnel_type = 0;
2082         int rc = 0;
2083
2084         rc = is_bnxt_in_error(bp);
2085         if (rc)
2086                 return rc;
2087
2088         switch (udp_tunnel->prot_type) {
2089         case RTE_TUNNEL_TYPE_VXLAN:
2090                 if (bp->vxlan_port_cnt) {
2091                         PMD_DRV_LOG(ERR, "Tunnel Port %d already programmed\n",
2092                                 udp_tunnel->udp_port);
2093                         if (bp->vxlan_port != udp_tunnel->udp_port) {
2094                                 PMD_DRV_LOG(ERR, "Only one port allowed\n");
2095                                 return -ENOSPC;
2096                         }
2097                         bp->vxlan_port_cnt++;
2098                         return 0;
2099                 }
2100                 tunnel_type =
2101                         HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_VXLAN;
2102                 bp->vxlan_port_cnt++;
2103                 break;
2104         case RTE_TUNNEL_TYPE_GENEVE:
2105                 if (bp->geneve_port_cnt) {
2106                         PMD_DRV_LOG(ERR, "Tunnel Port %d already programmed\n",
2107                                 udp_tunnel->udp_port);
2108                         if (bp->geneve_port != udp_tunnel->udp_port) {
2109                                 PMD_DRV_LOG(ERR, "Only one port allowed\n");
2110                                 return -ENOSPC;
2111                         }
2112                         bp->geneve_port_cnt++;
2113                         return 0;
2114                 }
2115                 tunnel_type =
2116                         HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_GENEVE;
2117                 bp->geneve_port_cnt++;
2118                 break;
2119         default:
2120                 PMD_DRV_LOG(ERR, "Tunnel type is not supported\n");
2121                 return -ENOTSUP;
2122         }
2123         rc = bnxt_hwrm_tunnel_dst_port_alloc(bp, udp_tunnel->udp_port,
2124                                              tunnel_type);
2125         return rc;
2126 }
2127
2128 static int
2129 bnxt_udp_tunnel_port_del_op(struct rte_eth_dev *eth_dev,
2130                          struct rte_eth_udp_tunnel *udp_tunnel)
2131 {
2132         struct bnxt *bp = eth_dev->data->dev_private;
2133         uint16_t tunnel_type = 0;
2134         uint16_t port = 0;
2135         int rc = 0;
2136
2137         rc = is_bnxt_in_error(bp);
2138         if (rc)
2139                 return rc;
2140
2141         switch (udp_tunnel->prot_type) {
2142         case RTE_TUNNEL_TYPE_VXLAN:
2143                 if (!bp->vxlan_port_cnt) {
2144                         PMD_DRV_LOG(ERR, "No Tunnel port configured yet\n");
2145                         return -EINVAL;
2146                 }
2147                 if (bp->vxlan_port != udp_tunnel->udp_port) {
2148                         PMD_DRV_LOG(ERR, "Req Port: %d. Configured port: %d\n",
2149                                 udp_tunnel->udp_port, bp->vxlan_port);
2150                         return -EINVAL;
2151                 }
2152                 if (--bp->vxlan_port_cnt)
2153                         return 0;
2154
2155                 tunnel_type =
2156                         HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN;
2157                 port = bp->vxlan_fw_dst_port_id;
2158                 break;
2159         case RTE_TUNNEL_TYPE_GENEVE:
2160                 if (!bp->geneve_port_cnt) {
2161                         PMD_DRV_LOG(ERR, "No Tunnel port configured yet\n");
2162                         return -EINVAL;
2163                 }
2164                 if (bp->geneve_port != udp_tunnel->udp_port) {
2165                         PMD_DRV_LOG(ERR, "Req Port: %d. Configured port: %d\n",
2166                                 udp_tunnel->udp_port, bp->geneve_port);
2167                         return -EINVAL;
2168                 }
2169                 if (--bp->geneve_port_cnt)
2170                         return 0;
2171
2172                 tunnel_type =
2173                         HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_GENEVE;
2174                 port = bp->geneve_fw_dst_port_id;
2175                 break;
2176         default:
2177                 PMD_DRV_LOG(ERR, "Tunnel type is not supported\n");
2178                 return -ENOTSUP;
2179         }
2180
2181         rc = bnxt_hwrm_tunnel_dst_port_free(bp, port, tunnel_type);
2182         if (!rc) {
2183                 if (tunnel_type ==
2184                     HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN)
2185                         bp->vxlan_port = 0;
2186                 if (tunnel_type ==
2187                     HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_GENEVE)
2188                         bp->geneve_port = 0;
2189         }
2190         return rc;
2191 }
2192
2193 static int bnxt_del_vlan_filter(struct bnxt *bp, uint16_t vlan_id)
2194 {
2195         struct bnxt_filter_info *filter;
2196         struct bnxt_vnic_info *vnic;
2197         int rc = 0;
2198         uint32_t chk = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN;
2199
2200         vnic = BNXT_GET_DEFAULT_VNIC(bp);
2201         filter = STAILQ_FIRST(&vnic->filter);
2202         while (filter) {
2203                 /* Search for this matching MAC+VLAN filter */
2204                 if (bnxt_vlan_filter_exists(bp, filter, chk, vlan_id)) {
2205                         /* Delete the filter */
2206                         rc = bnxt_hwrm_clear_l2_filter(bp, filter);
2207                         if (rc)
2208                                 return rc;
2209                         STAILQ_REMOVE(&vnic->filter, filter,
2210                                       bnxt_filter_info, next);
2211                         bnxt_free_filter(bp, filter);
2212                         PMD_DRV_LOG(INFO,
2213                                     "Deleted vlan filter for %d\n",
2214                                     vlan_id);
2215                         return 0;
2216                 }
2217                 filter = STAILQ_NEXT(filter, next);
2218         }
2219         return -ENOENT;
2220 }
2221
2222 static int bnxt_add_vlan_filter(struct bnxt *bp, uint16_t vlan_id)
2223 {
2224         struct bnxt_filter_info *filter;
2225         struct bnxt_vnic_info *vnic;
2226         int rc = 0;
2227         uint32_t en = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN |
2228                 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN_MASK;
2229         uint32_t chk = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN;
2230
2231         /* Implementation notes on the use of VNIC in this command:
2232          *
2233          * By default, these filters belong to default vnic for the function.
2234          * Once these filters are set up, only destination VNIC can be modified.
2235          * If the destination VNIC is not specified in this command,
2236          * then the HWRM shall only create an l2 context id.
2237          */
2238
2239         vnic = BNXT_GET_DEFAULT_VNIC(bp);
2240         filter = STAILQ_FIRST(&vnic->filter);
2241         /* Check if the VLAN has already been added */
2242         while (filter) {
2243                 if (bnxt_vlan_filter_exists(bp, filter, chk, vlan_id))
2244                         return -EEXIST;
2245
2246                 filter = STAILQ_NEXT(filter, next);
2247         }
2248
2249         /* No match found. Alloc a fresh filter and issue the L2_FILTER_ALLOC
2250          * command to create MAC+VLAN filter with the right flags, enables set.
2251          */
2252         filter = bnxt_alloc_filter(bp);
2253         if (!filter) {
2254                 PMD_DRV_LOG(ERR,
2255                             "MAC/VLAN filter alloc failed\n");
2256                 return -ENOMEM;
2257         }
2258         /* MAC + VLAN ID filter */
2259         /* If l2_ivlan == 0 and l2_ivlan_mask != 0, only
2260          * untagged packets are received
2261          *
2262          * If l2_ivlan != 0 and l2_ivlan_mask != 0, untagged
2263          * packets and only the programmed vlan's packets are received
2264          */
2265         filter->l2_ivlan = vlan_id;
2266         filter->l2_ivlan_mask = 0x0FFF;
2267         filter->enables |= en;
2268         filter->flags |= HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_OUTERMOST;
2269
2270         rc = bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id, filter);
2271         if (rc) {
2272                 /* Free the newly allocated filter as we were
2273                  * not able to create the filter in hardware.
2274                  */
2275                 bnxt_free_filter(bp, filter);
2276                 return rc;
2277         }
2278
2279         filter->mac_index = 0;
2280         /* Add this new filter to the list */
2281         if (vlan_id == 0)
2282                 STAILQ_INSERT_HEAD(&vnic->filter, filter, next);
2283         else
2284                 STAILQ_INSERT_TAIL(&vnic->filter, filter, next);
2285
2286         PMD_DRV_LOG(INFO,
2287                     "Added Vlan filter for %d\n", vlan_id);
2288         return rc;
2289 }
2290
2291 static int bnxt_vlan_filter_set_op(struct rte_eth_dev *eth_dev,
2292                 uint16_t vlan_id, int on)
2293 {
2294         struct bnxt *bp = eth_dev->data->dev_private;
2295         int rc;
2296
2297         rc = is_bnxt_in_error(bp);
2298         if (rc)
2299                 return rc;
2300
2301         if (!eth_dev->data->dev_started) {
2302                 PMD_DRV_LOG(ERR, "port must be started before setting vlan\n");
2303                 return -EINVAL;
2304         }
2305
2306         /* These operations apply to ALL existing MAC/VLAN filters */
2307         if (on)
2308                 return bnxt_add_vlan_filter(bp, vlan_id);
2309         else
2310                 return bnxt_del_vlan_filter(bp, vlan_id);
2311 }
2312
2313 static int bnxt_del_dflt_mac_filter(struct bnxt *bp,
2314                                     struct bnxt_vnic_info *vnic)
2315 {
2316         struct bnxt_filter_info *filter;
2317         int rc;
2318
2319         filter = STAILQ_FIRST(&vnic->filter);
2320         while (filter) {
2321                 if (filter->mac_index == 0 &&
2322                     !memcmp(filter->l2_addr, bp->mac_addr,
2323                             RTE_ETHER_ADDR_LEN)) {
2324                         rc = bnxt_hwrm_clear_l2_filter(bp, filter);
2325                         if (!rc) {
2326                                 STAILQ_REMOVE(&vnic->filter, filter,
2327                                               bnxt_filter_info, next);
2328                                 bnxt_free_filter(bp, filter);
2329                         }
2330                         return rc;
2331                 }
2332                 filter = STAILQ_NEXT(filter, next);
2333         }
2334         return 0;
2335 }
2336
2337 static int
2338 bnxt_config_vlan_hw_filter(struct bnxt *bp, uint64_t rx_offloads)
2339 {
2340         struct bnxt_vnic_info *vnic;
2341         unsigned int i;
2342         int rc;
2343
2344         vnic = BNXT_GET_DEFAULT_VNIC(bp);
2345         if (!(rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER)) {
2346                 /* Remove any VLAN filters programmed */
2347                 for (i = 0; i < RTE_ETHER_MAX_VLAN_ID; i++)
2348                         bnxt_del_vlan_filter(bp, i);
2349
2350                 rc = bnxt_add_mac_filter(bp, vnic, NULL, 0, 0);
2351                 if (rc)
2352                         return rc;
2353         } else {
2354                 /* Default filter will allow packets that match the
2355                  * dest mac. So, it has to be deleted, otherwise, we
2356                  * will endup receiving vlan packets for which the
2357                  * filter is not programmed, when hw-vlan-filter
2358                  * configuration is ON
2359                  */
2360                 bnxt_del_dflt_mac_filter(bp, vnic);
2361                 /* This filter will allow only untagged packets */
2362                 bnxt_add_vlan_filter(bp, 0);
2363         }
2364         PMD_DRV_LOG(DEBUG, "VLAN Filtering: %d\n",
2365                     !!(rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER));
2366
2367         return 0;
2368 }
2369
2370 static int bnxt_free_one_vnic(struct bnxt *bp, uint16_t vnic_id)
2371 {
2372         struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id];
2373         unsigned int i;
2374         int rc;
2375
2376         /* Destroy vnic filters and vnic */
2377         if (bp->eth_dev->data->dev_conf.rxmode.offloads &
2378             DEV_RX_OFFLOAD_VLAN_FILTER) {
2379                 for (i = 0; i < RTE_ETHER_MAX_VLAN_ID; i++)
2380                         bnxt_del_vlan_filter(bp, i);
2381         }
2382         bnxt_del_dflt_mac_filter(bp, vnic);
2383
2384         rc = bnxt_hwrm_vnic_free(bp, vnic);
2385         if (rc)
2386                 return rc;
2387
2388         rte_free(vnic->fw_grp_ids);
2389         vnic->fw_grp_ids = NULL;
2390
2391         vnic->rx_queue_cnt = 0;
2392
2393         return 0;
2394 }
2395
2396 static int
2397 bnxt_config_vlan_hw_stripping(struct bnxt *bp, uint64_t rx_offloads)
2398 {
2399         struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp);
2400         int rc;
2401
2402         /* Destroy, recreate and reconfigure the default vnic */
2403         rc = bnxt_free_one_vnic(bp, 0);
2404         if (rc)
2405                 return rc;
2406
2407         /* default vnic 0 */
2408         rc = bnxt_setup_one_vnic(bp, 0);
2409         if (rc)
2410                 return rc;
2411
2412         if (bp->eth_dev->data->dev_conf.rxmode.offloads &
2413             DEV_RX_OFFLOAD_VLAN_FILTER) {
2414                 rc = bnxt_add_vlan_filter(bp, 0);
2415                 if (rc)
2416                         return rc;
2417                 rc = bnxt_restore_vlan_filters(bp);
2418                 if (rc)
2419                         return rc;
2420         } else {
2421                 rc = bnxt_add_mac_filter(bp, vnic, NULL, 0, 0);
2422                 if (rc)
2423                         return rc;
2424         }
2425
2426         rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
2427         if (rc)
2428                 return rc;
2429
2430         PMD_DRV_LOG(DEBUG, "VLAN Strip Offload: %d\n",
2431                     !!(rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP));
2432
2433         return rc;
2434 }
2435
2436 static int
2437 bnxt_vlan_offload_set_op(struct rte_eth_dev *dev, int mask)
2438 {
2439         uint64_t rx_offloads = dev->data->dev_conf.rxmode.offloads;
2440         struct bnxt *bp = dev->data->dev_private;
2441         int rc;
2442
2443         rc = is_bnxt_in_error(bp);
2444         if (rc)
2445                 return rc;
2446
2447         /* Filter settings will get applied when port is started */
2448         if (!dev->data->dev_started)
2449                 return 0;
2450
2451         if (mask & ETH_VLAN_FILTER_MASK) {
2452                 /* Enable or disable VLAN filtering */
2453                 rc = bnxt_config_vlan_hw_filter(bp, rx_offloads);
2454                 if (rc)
2455                         return rc;
2456         }
2457
2458         if (mask & ETH_VLAN_STRIP_MASK) {
2459                 /* Enable or disable VLAN stripping */
2460                 rc = bnxt_config_vlan_hw_stripping(bp, rx_offloads);
2461                 if (rc)
2462                         return rc;
2463         }
2464
2465         if (mask & ETH_VLAN_EXTEND_MASK) {
2466                 if (rx_offloads & DEV_RX_OFFLOAD_VLAN_EXTEND)
2467                         PMD_DRV_LOG(DEBUG, "Extend VLAN supported\n");
2468                 else
2469                         PMD_DRV_LOG(INFO, "Extend VLAN unsupported\n");
2470         }
2471
2472         return 0;
2473 }
2474
2475 static int
2476 bnxt_vlan_tpid_set_op(struct rte_eth_dev *dev, enum rte_vlan_type vlan_type,
2477                       uint16_t tpid)
2478 {
2479         struct bnxt *bp = dev->data->dev_private;
2480         int qinq = dev->data->dev_conf.rxmode.offloads &
2481                    DEV_RX_OFFLOAD_VLAN_EXTEND;
2482
2483         if (vlan_type != ETH_VLAN_TYPE_INNER &&
2484             vlan_type != ETH_VLAN_TYPE_OUTER) {
2485                 PMD_DRV_LOG(ERR,
2486                             "Unsupported vlan type.");
2487                 return -EINVAL;
2488         }
2489         if (!qinq) {
2490                 PMD_DRV_LOG(ERR,
2491                             "QinQ not enabled. Needs to be ON as we can "
2492                             "accelerate only outer vlan\n");
2493                 return -EINVAL;
2494         }
2495
2496         if (vlan_type == ETH_VLAN_TYPE_OUTER) {
2497                 switch (tpid) {
2498                 case RTE_ETHER_TYPE_QINQ:
2499                         bp->outer_tpid_bd =
2500                                 TX_BD_LONG_CFA_META_VLAN_TPID_TPID88A8;
2501                                 break;
2502                 case RTE_ETHER_TYPE_VLAN:
2503                         bp->outer_tpid_bd =
2504                                 TX_BD_LONG_CFA_META_VLAN_TPID_TPID8100;
2505                                 break;
2506                 case RTE_ETHER_TYPE_QINQ1:
2507                         bp->outer_tpid_bd =
2508                                 TX_BD_LONG_CFA_META_VLAN_TPID_TPID9100;
2509                                 break;
2510                 case RTE_ETHER_TYPE_QINQ2:
2511                         bp->outer_tpid_bd =
2512                                 TX_BD_LONG_CFA_META_VLAN_TPID_TPID9200;
2513                                 break;
2514                 case RTE_ETHER_TYPE_QINQ3:
2515                         bp->outer_tpid_bd =
2516                                  TX_BD_LONG_CFA_META_VLAN_TPID_TPID9300;
2517                                 break;
2518                 default:
2519                         PMD_DRV_LOG(ERR, "Invalid TPID: %x\n", tpid);
2520                         return -EINVAL;
2521                 }
2522                 bp->outer_tpid_bd |= tpid;
2523                 PMD_DRV_LOG(INFO, "outer_tpid_bd = %x\n", bp->outer_tpid_bd);
2524         } else if (vlan_type == ETH_VLAN_TYPE_INNER) {
2525                 PMD_DRV_LOG(ERR,
2526                             "Can accelerate only outer vlan in QinQ\n");
2527                 return -EINVAL;
2528         }
2529
2530         return 0;
2531 }
2532
2533 static int
2534 bnxt_set_default_mac_addr_op(struct rte_eth_dev *dev,
2535                              struct rte_ether_addr *addr)
2536 {
2537         struct bnxt *bp = dev->data->dev_private;
2538         /* Default Filter is tied to VNIC 0 */
2539         struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp);
2540         int rc;
2541
2542         rc = is_bnxt_in_error(bp);
2543         if (rc)
2544                 return rc;
2545
2546         if (BNXT_VF(bp) && !BNXT_VF_IS_TRUSTED(bp))
2547                 return -EPERM;
2548
2549         if (rte_is_zero_ether_addr(addr))
2550                 return -EINVAL;
2551
2552         /* Filter settings will get applied when port is started */
2553         if (!dev->data->dev_started)
2554                 return 0;
2555
2556         /* Check if the requested MAC is already added */
2557         if (memcmp(addr, bp->mac_addr, RTE_ETHER_ADDR_LEN) == 0)
2558                 return 0;
2559
2560         /* Destroy filter and re-create it */
2561         bnxt_del_dflt_mac_filter(bp, vnic);
2562
2563         memcpy(bp->mac_addr, addr, RTE_ETHER_ADDR_LEN);
2564         if (dev->data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_VLAN_FILTER) {
2565                 /* This filter will allow only untagged packets */
2566                 rc = bnxt_add_vlan_filter(bp, 0);
2567         } else {
2568                 rc = bnxt_add_mac_filter(bp, vnic, addr, 0, 0);
2569         }
2570
2571         PMD_DRV_LOG(DEBUG, "Set MAC addr\n");
2572         return rc;
2573 }
2574
2575 static int
2576 bnxt_dev_set_mc_addr_list_op(struct rte_eth_dev *eth_dev,
2577                           struct rte_ether_addr *mc_addr_set,
2578                           uint32_t nb_mc_addr)
2579 {
2580         struct bnxt *bp = eth_dev->data->dev_private;
2581         char *mc_addr_list = (char *)mc_addr_set;
2582         struct bnxt_vnic_info *vnic;
2583         uint32_t off = 0, i = 0;
2584         int rc;
2585
2586         rc = is_bnxt_in_error(bp);
2587         if (rc)
2588                 return rc;
2589
2590         vnic = BNXT_GET_DEFAULT_VNIC(bp);
2591
2592         if (nb_mc_addr > BNXT_MAX_MC_ADDRS) {
2593                 vnic->flags |= BNXT_VNIC_INFO_ALLMULTI;
2594                 goto allmulti;
2595         }
2596
2597         /* TODO Check for Duplicate mcast addresses */
2598         vnic->flags &= ~BNXT_VNIC_INFO_ALLMULTI;
2599         for (i = 0; i < nb_mc_addr; i++) {
2600                 memcpy(vnic->mc_list + off, &mc_addr_list[i],
2601                         RTE_ETHER_ADDR_LEN);
2602                 off += RTE_ETHER_ADDR_LEN;
2603         }
2604
2605         vnic->mc_addr_cnt = i;
2606         if (vnic->mc_addr_cnt)
2607                 vnic->flags |= BNXT_VNIC_INFO_MCAST;
2608         else
2609                 vnic->flags &= ~BNXT_VNIC_INFO_MCAST;
2610
2611 allmulti:
2612         return bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
2613 }
2614
2615 static int
2616 bnxt_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size)
2617 {
2618         struct bnxt *bp = dev->data->dev_private;
2619         uint8_t fw_major = (bp->fw_ver >> 24) & 0xff;
2620         uint8_t fw_minor = (bp->fw_ver >> 16) & 0xff;
2621         uint8_t fw_updt = (bp->fw_ver >> 8) & 0xff;
2622         uint8_t fw_rsvd = bp->fw_ver & 0xff;
2623         int ret;
2624
2625         ret = snprintf(fw_version, fw_size, "%d.%d.%d.%d",
2626                         fw_major, fw_minor, fw_updt, fw_rsvd);
2627
2628         ret += 1; /* add the size of '\0' */
2629         if (fw_size < (uint32_t)ret)
2630                 return ret;
2631         else
2632                 return 0;
2633 }
2634
2635 static void
2636 bnxt_rxq_info_get_op(struct rte_eth_dev *dev, uint16_t queue_id,
2637         struct rte_eth_rxq_info *qinfo)
2638 {
2639         struct bnxt *bp = dev->data->dev_private;
2640         struct bnxt_rx_queue *rxq;
2641
2642         if (is_bnxt_in_error(bp))
2643                 return;
2644
2645         rxq = dev->data->rx_queues[queue_id];
2646
2647         qinfo->mp = rxq->mb_pool;
2648         qinfo->scattered_rx = dev->data->scattered_rx;
2649         qinfo->nb_desc = rxq->nb_rx_desc;
2650
2651         qinfo->conf.rx_free_thresh = rxq->rx_free_thresh;
2652         qinfo->conf.rx_drop_en = rxq->drop_en;
2653         qinfo->conf.rx_deferred_start = rxq->rx_deferred_start;
2654         qinfo->conf.offloads = dev->data->dev_conf.rxmode.offloads;
2655 }
2656
2657 static void
2658 bnxt_txq_info_get_op(struct rte_eth_dev *dev, uint16_t queue_id,
2659         struct rte_eth_txq_info *qinfo)
2660 {
2661         struct bnxt *bp = dev->data->dev_private;
2662         struct bnxt_tx_queue *txq;
2663
2664         if (is_bnxt_in_error(bp))
2665                 return;
2666
2667         txq = dev->data->tx_queues[queue_id];
2668
2669         qinfo->nb_desc = txq->nb_tx_desc;
2670
2671         qinfo->conf.tx_thresh.pthresh = txq->pthresh;
2672         qinfo->conf.tx_thresh.hthresh = txq->hthresh;
2673         qinfo->conf.tx_thresh.wthresh = txq->wthresh;
2674
2675         qinfo->conf.tx_free_thresh = txq->tx_free_thresh;
2676         qinfo->conf.tx_rs_thresh = 0;
2677         qinfo->conf.tx_deferred_start = txq->tx_deferred_start;
2678         qinfo->conf.offloads = dev->data->dev_conf.txmode.offloads;
2679 }
2680
2681 static const struct {
2682         eth_rx_burst_t pkt_burst;
2683         const char *info;
2684 } bnxt_rx_burst_info[] = {
2685         {bnxt_recv_pkts,        "Scalar"},
2686 #if defined(RTE_ARCH_X86)
2687         {bnxt_recv_pkts_vec,    "Vector SSE"},
2688 #elif defined(RTE_ARCH_ARM64)
2689         {bnxt_recv_pkts_vec,    "Vector Neon"},
2690 #endif
2691 };
2692
2693 static int
2694 bnxt_rx_burst_mode_get(struct rte_eth_dev *dev, __rte_unused uint16_t queue_id,
2695                        struct rte_eth_burst_mode *mode)
2696 {
2697         eth_rx_burst_t pkt_burst = dev->rx_pkt_burst;
2698         size_t i;
2699
2700         for (i = 0; i < RTE_DIM(bnxt_rx_burst_info); i++) {
2701                 if (pkt_burst == bnxt_rx_burst_info[i].pkt_burst) {
2702                         snprintf(mode->info, sizeof(mode->info), "%s",
2703                                  bnxt_rx_burst_info[i].info);
2704                         return 0;
2705                 }
2706         }
2707
2708         return -EINVAL;
2709 }
2710
2711 static const struct {
2712         eth_tx_burst_t pkt_burst;
2713         const char *info;
2714 } bnxt_tx_burst_info[] = {
2715         {bnxt_xmit_pkts,        "Scalar"},
2716 #if defined(RTE_ARCH_X86)
2717         {bnxt_xmit_pkts_vec,    "Vector SSE"},
2718 #elif defined(RTE_ARCH_ARM64)
2719         {bnxt_xmit_pkts_vec,    "Vector Neon"},
2720 #endif
2721 };
2722
2723 static int
2724 bnxt_tx_burst_mode_get(struct rte_eth_dev *dev, __rte_unused uint16_t queue_id,
2725                        struct rte_eth_burst_mode *mode)
2726 {
2727         eth_tx_burst_t pkt_burst = dev->tx_pkt_burst;
2728         size_t i;
2729
2730         for (i = 0; i < RTE_DIM(bnxt_tx_burst_info); i++) {
2731                 if (pkt_burst == bnxt_tx_burst_info[i].pkt_burst) {
2732                         snprintf(mode->info, sizeof(mode->info), "%s",
2733                                  bnxt_tx_burst_info[i].info);
2734                         return 0;
2735                 }
2736         }
2737
2738         return -EINVAL;
2739 }
2740
2741 int bnxt_mtu_set_op(struct rte_eth_dev *eth_dev, uint16_t new_mtu)
2742 {
2743         struct bnxt *bp = eth_dev->data->dev_private;
2744         uint32_t new_pkt_size;
2745         uint32_t rc = 0;
2746         uint32_t i;
2747
2748         rc = is_bnxt_in_error(bp);
2749         if (rc)
2750                 return rc;
2751
2752         /* Exit if receive queues are not configured yet */
2753         if (!eth_dev->data->nb_rx_queues)
2754                 return rc;
2755
2756         new_pkt_size = new_mtu + RTE_ETHER_HDR_LEN + RTE_ETHER_CRC_LEN +
2757                        VLAN_TAG_SIZE * BNXT_NUM_VLANS;
2758
2759         /*
2760          * Disallow any MTU change that would require scattered receive support
2761          * if it is not already enabled.
2762          */
2763         if (eth_dev->data->dev_started &&
2764             !eth_dev->data->scattered_rx &&
2765             (new_pkt_size >
2766              eth_dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM)) {
2767                 PMD_DRV_LOG(ERR,
2768                             "MTU change would require scattered rx support. ");
2769                 PMD_DRV_LOG(ERR, "Stop port before changing MTU.\n");
2770                 return -EINVAL;
2771         }
2772
2773         if (new_mtu > RTE_ETHER_MTU) {
2774                 bp->flags |= BNXT_FLAG_JUMBO;
2775                 bp->eth_dev->data->dev_conf.rxmode.offloads |=
2776                         DEV_RX_OFFLOAD_JUMBO_FRAME;
2777         } else {
2778                 bp->eth_dev->data->dev_conf.rxmode.offloads &=
2779                         ~DEV_RX_OFFLOAD_JUMBO_FRAME;
2780                 bp->flags &= ~BNXT_FLAG_JUMBO;
2781         }
2782
2783         /* Is there a change in mtu setting? */
2784         if (eth_dev->data->dev_conf.rxmode.max_rx_pkt_len == new_pkt_size)
2785                 return rc;
2786
2787         for (i = 0; i < bp->nr_vnics; i++) {
2788                 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
2789                 uint16_t size = 0;
2790
2791                 vnic->mru = BNXT_VNIC_MRU(new_mtu);
2792                 rc = bnxt_hwrm_vnic_cfg(bp, vnic);
2793                 if (rc)
2794                         break;
2795
2796                 size = rte_pktmbuf_data_room_size(bp->rx_queues[0]->mb_pool);
2797                 size -= RTE_PKTMBUF_HEADROOM;
2798
2799                 if (size < new_mtu) {
2800                         rc = bnxt_hwrm_vnic_plcmode_cfg(bp, vnic);
2801                         if (rc)
2802                                 return rc;
2803                 }
2804         }
2805
2806         if (!rc)
2807                 eth_dev->data->dev_conf.rxmode.max_rx_pkt_len = new_pkt_size;
2808
2809         PMD_DRV_LOG(INFO, "New MTU is %d\n", new_mtu);
2810
2811         return rc;
2812 }
2813
2814 static int
2815 bnxt_vlan_pvid_set_op(struct rte_eth_dev *dev, uint16_t pvid, int on)
2816 {
2817         struct bnxt *bp = dev->data->dev_private;
2818         uint16_t vlan = bp->vlan;
2819         int rc;
2820
2821         rc = is_bnxt_in_error(bp);
2822         if (rc)
2823                 return rc;
2824
2825         if (!BNXT_SINGLE_PF(bp) || BNXT_VF(bp)) {
2826                 PMD_DRV_LOG(ERR,
2827                         "PVID cannot be modified for this function\n");
2828                 return -ENOTSUP;
2829         }
2830         bp->vlan = on ? pvid : 0;
2831
2832         rc = bnxt_hwrm_set_default_vlan(bp, 0, 0);
2833         if (rc)
2834                 bp->vlan = vlan;
2835         return rc;
2836 }
2837
2838 static int
2839 bnxt_dev_led_on_op(struct rte_eth_dev *dev)
2840 {
2841         struct bnxt *bp = dev->data->dev_private;
2842         int rc;
2843
2844         rc = is_bnxt_in_error(bp);
2845         if (rc)
2846                 return rc;
2847
2848         return bnxt_hwrm_port_led_cfg(bp, true);
2849 }
2850
2851 static int
2852 bnxt_dev_led_off_op(struct rte_eth_dev *dev)
2853 {
2854         struct bnxt *bp = dev->data->dev_private;
2855         int rc;
2856
2857         rc = is_bnxt_in_error(bp);
2858         if (rc)
2859                 return rc;
2860
2861         return bnxt_hwrm_port_led_cfg(bp, false);
2862 }
2863
2864 static uint32_t
2865 bnxt_rx_queue_count_op(struct rte_eth_dev *dev, uint16_t rx_queue_id)
2866 {
2867         struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
2868         uint32_t desc = 0, raw_cons = 0, cons;
2869         struct bnxt_cp_ring_info *cpr;
2870         struct bnxt_rx_queue *rxq;
2871         struct rx_pkt_cmpl *rxcmp;
2872         int rc;
2873
2874         rc = is_bnxt_in_error(bp);
2875         if (rc)
2876                 return rc;
2877
2878         rxq = dev->data->rx_queues[rx_queue_id];
2879         cpr = rxq->cp_ring;
2880         raw_cons = cpr->cp_raw_cons;
2881
2882         while (1) {
2883                 cons = RING_CMP(cpr->cp_ring_struct, raw_cons);
2884                 rte_prefetch0(&cpr->cp_desc_ring[cons]);
2885                 rxcmp = (struct rx_pkt_cmpl *)&cpr->cp_desc_ring[cons];
2886
2887                 if (!CMP_VALID(rxcmp, raw_cons, cpr->cp_ring_struct)) {
2888                         break;
2889                 } else {
2890                         raw_cons++;
2891                         desc++;
2892                 }
2893         }
2894
2895         return desc;
2896 }
2897
2898 static int
2899 bnxt_rx_descriptor_status_op(void *rx_queue, uint16_t offset)
2900 {
2901         struct bnxt_rx_queue *rxq = (struct bnxt_rx_queue *)rx_queue;
2902         struct bnxt_rx_ring_info *rxr;
2903         struct bnxt_cp_ring_info *cpr;
2904         struct rte_mbuf *rx_buf;
2905         struct rx_pkt_cmpl *rxcmp;
2906         uint32_t cons, cp_cons;
2907         int rc;
2908
2909         if (!rxq)
2910                 return -EINVAL;
2911
2912         rc = is_bnxt_in_error(rxq->bp);
2913         if (rc)
2914                 return rc;
2915
2916         cpr = rxq->cp_ring;
2917         rxr = rxq->rx_ring;
2918
2919         if (offset >= rxq->nb_rx_desc)
2920                 return -EINVAL;
2921
2922         cons = RING_CMP(cpr->cp_ring_struct, offset);
2923         cp_cons = cpr->cp_raw_cons;
2924         rxcmp = (struct rx_pkt_cmpl *)&cpr->cp_desc_ring[cons];
2925
2926         if (cons > cp_cons) {
2927                 if (CMPL_VALID(rxcmp, cpr->valid))
2928                         return RTE_ETH_RX_DESC_DONE;
2929         } else {
2930                 if (CMPL_VALID(rxcmp, !cpr->valid))
2931                         return RTE_ETH_RX_DESC_DONE;
2932         }
2933         rx_buf = rxr->rx_buf_ring[cons];
2934         if (rx_buf == NULL || rx_buf == &rxq->fake_mbuf)
2935                 return RTE_ETH_RX_DESC_UNAVAIL;
2936
2937
2938         return RTE_ETH_RX_DESC_AVAIL;
2939 }
2940
2941 static int
2942 bnxt_tx_descriptor_status_op(void *tx_queue, uint16_t offset)
2943 {
2944         struct bnxt_tx_queue *txq = (struct bnxt_tx_queue *)tx_queue;
2945         struct bnxt_tx_ring_info *txr;
2946         struct bnxt_cp_ring_info *cpr;
2947         struct bnxt_sw_tx_bd *tx_buf;
2948         struct tx_pkt_cmpl *txcmp;
2949         uint32_t cons, cp_cons;
2950         int rc;
2951
2952         if (!txq)
2953                 return -EINVAL;
2954
2955         rc = is_bnxt_in_error(txq->bp);
2956         if (rc)
2957                 return rc;
2958
2959         cpr = txq->cp_ring;
2960         txr = txq->tx_ring;
2961
2962         if (offset >= txq->nb_tx_desc)
2963                 return -EINVAL;
2964
2965         cons = RING_CMP(cpr->cp_ring_struct, offset);
2966         txcmp = (struct tx_pkt_cmpl *)&cpr->cp_desc_ring[cons];
2967         cp_cons = cpr->cp_raw_cons;
2968
2969         if (cons > cp_cons) {
2970                 if (CMPL_VALID(txcmp, cpr->valid))
2971                         return RTE_ETH_TX_DESC_UNAVAIL;
2972         } else {
2973                 if (CMPL_VALID(txcmp, !cpr->valid))
2974                         return RTE_ETH_TX_DESC_UNAVAIL;
2975         }
2976         tx_buf = &txr->tx_buf_ring[cons];
2977         if (tx_buf->mbuf == NULL)
2978                 return RTE_ETH_TX_DESC_DONE;
2979
2980         return RTE_ETH_TX_DESC_FULL;
2981 }
2982
2983 static struct bnxt_filter_info *
2984 bnxt_match_and_validate_ether_filter(struct bnxt *bp,
2985                                 struct rte_eth_ethertype_filter *efilter,
2986                                 struct bnxt_vnic_info *vnic0,
2987                                 struct bnxt_vnic_info *vnic,
2988                                 int *ret)
2989 {
2990         struct bnxt_filter_info *mfilter = NULL;
2991         int match = 0;
2992         *ret = 0;
2993
2994         if (efilter->ether_type == RTE_ETHER_TYPE_IPV4 ||
2995                 efilter->ether_type == RTE_ETHER_TYPE_IPV6) {
2996                 PMD_DRV_LOG(ERR, "invalid ether_type(0x%04x) in"
2997                         " ethertype filter.", efilter->ether_type);
2998                 *ret = -EINVAL;
2999                 goto exit;
3000         }
3001         if (efilter->queue >= bp->rx_nr_rings) {
3002                 PMD_DRV_LOG(ERR, "Invalid queue %d\n", efilter->queue);
3003                 *ret = -EINVAL;
3004                 goto exit;
3005         }
3006
3007         vnic0 = BNXT_GET_DEFAULT_VNIC(bp);
3008         vnic = &bp->vnic_info[efilter->queue];
3009         if (vnic == NULL) {
3010                 PMD_DRV_LOG(ERR, "Invalid queue %d\n", efilter->queue);
3011                 *ret = -EINVAL;
3012                 goto exit;
3013         }
3014
3015         if (efilter->flags & RTE_ETHTYPE_FLAGS_DROP) {
3016                 STAILQ_FOREACH(mfilter, &vnic0->filter, next) {
3017                         if ((!memcmp(efilter->mac_addr.addr_bytes,
3018                                      mfilter->l2_addr, RTE_ETHER_ADDR_LEN) &&
3019                              mfilter->flags ==
3020                              HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_DROP &&
3021                              mfilter->ethertype == efilter->ether_type)) {
3022                                 match = 1;
3023                                 break;
3024                         }
3025                 }
3026         } else {
3027                 STAILQ_FOREACH(mfilter, &vnic->filter, next)
3028                         if ((!memcmp(efilter->mac_addr.addr_bytes,
3029                                      mfilter->l2_addr, RTE_ETHER_ADDR_LEN) &&
3030                              mfilter->ethertype == efilter->ether_type &&
3031                              mfilter->flags ==
3032                              HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_PATH_RX)) {
3033                                 match = 1;
3034                                 break;
3035                         }
3036         }
3037
3038         if (match)
3039                 *ret = -EEXIST;
3040
3041 exit:
3042         return mfilter;
3043 }
3044
3045 static int
3046 bnxt_ethertype_filter(struct rte_eth_dev *dev,
3047                         enum rte_filter_op filter_op,
3048                         void *arg)
3049 {
3050         struct bnxt *bp = dev->data->dev_private;
3051         struct rte_eth_ethertype_filter *efilter =
3052                         (struct rte_eth_ethertype_filter *)arg;
3053         struct bnxt_filter_info *bfilter, *filter1;
3054         struct bnxt_vnic_info *vnic, *vnic0;
3055         int ret;
3056
3057         if (filter_op == RTE_ETH_FILTER_NOP)
3058                 return 0;
3059
3060         if (arg == NULL) {
3061                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
3062                             filter_op);
3063                 return -EINVAL;
3064         }
3065
3066         vnic0 = BNXT_GET_DEFAULT_VNIC(bp);
3067         vnic = &bp->vnic_info[efilter->queue];
3068
3069         switch (filter_op) {
3070         case RTE_ETH_FILTER_ADD:
3071                 bnxt_match_and_validate_ether_filter(bp, efilter,
3072                                                         vnic0, vnic, &ret);
3073                 if (ret < 0)
3074                         return ret;
3075
3076                 bfilter = bnxt_get_unused_filter(bp);
3077                 if (bfilter == NULL) {
3078                         PMD_DRV_LOG(ERR,
3079                                 "Not enough resources for a new filter.\n");
3080                         return -ENOMEM;
3081                 }
3082                 bfilter->filter_type = HWRM_CFA_NTUPLE_FILTER;
3083                 memcpy(bfilter->l2_addr, efilter->mac_addr.addr_bytes,
3084                        RTE_ETHER_ADDR_LEN);
3085                 memcpy(bfilter->dst_macaddr, efilter->mac_addr.addr_bytes,
3086                        RTE_ETHER_ADDR_LEN);
3087                 bfilter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_MACADDR;
3088                 bfilter->ethertype = efilter->ether_type;
3089                 bfilter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
3090
3091                 filter1 = bnxt_get_l2_filter(bp, bfilter, vnic0);
3092                 if (filter1 == NULL) {
3093                         ret = -EINVAL;
3094                         goto cleanup;
3095                 }
3096                 bfilter->enables |=
3097                         HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID;
3098                 bfilter->fw_l2_filter_id = filter1->fw_l2_filter_id;
3099
3100                 bfilter->dst_id = vnic->fw_vnic_id;
3101
3102                 if (efilter->flags & RTE_ETHTYPE_FLAGS_DROP) {
3103                         bfilter->flags =
3104                                 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_DROP;
3105                 }
3106
3107                 ret = bnxt_hwrm_set_ntuple_filter(bp, bfilter->dst_id, bfilter);
3108                 if (ret)
3109                         goto cleanup;
3110                 STAILQ_INSERT_TAIL(&vnic->filter, bfilter, next);
3111                 break;
3112         case RTE_ETH_FILTER_DELETE:
3113                 filter1 = bnxt_match_and_validate_ether_filter(bp, efilter,
3114                                                         vnic0, vnic, &ret);
3115                 if (ret == -EEXIST) {
3116                         ret = bnxt_hwrm_clear_ntuple_filter(bp, filter1);
3117
3118                         STAILQ_REMOVE(&vnic->filter, filter1, bnxt_filter_info,
3119                                       next);
3120                         bnxt_free_filter(bp, filter1);
3121                 } else if (ret == 0) {
3122                         PMD_DRV_LOG(ERR, "No matching filter found\n");
3123                 }
3124                 break;
3125         default:
3126                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
3127                 ret = -EINVAL;
3128                 goto error;
3129         }
3130         return ret;
3131 cleanup:
3132         bnxt_free_filter(bp, bfilter);
3133 error:
3134         return ret;
3135 }
3136
3137 static inline int
3138 parse_ntuple_filter(struct bnxt *bp,
3139                     struct rte_eth_ntuple_filter *nfilter,
3140                     struct bnxt_filter_info *bfilter)
3141 {
3142         uint32_t en = 0;
3143
3144         if (nfilter->queue >= bp->rx_nr_rings) {
3145                 PMD_DRV_LOG(ERR, "Invalid queue %d\n", nfilter->queue);
3146                 return -EINVAL;
3147         }
3148
3149         switch (nfilter->dst_port_mask) {
3150         case UINT16_MAX:
3151                 bfilter->dst_port_mask = -1;
3152                 bfilter->dst_port = nfilter->dst_port;
3153                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT |
3154                         NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
3155                 break;
3156         default:
3157                 PMD_DRV_LOG(ERR, "invalid dst_port mask.");
3158                 return -EINVAL;
3159         }
3160
3161         bfilter->ip_addr_type = NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4;
3162         en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
3163
3164         switch (nfilter->proto_mask) {
3165         case UINT8_MAX:
3166                 if (nfilter->proto == 17) /* IPPROTO_UDP */
3167                         bfilter->ip_protocol = 17;
3168                 else if (nfilter->proto == 6) /* IPPROTO_TCP */
3169                         bfilter->ip_protocol = 6;
3170                 else
3171                         return -EINVAL;
3172                 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
3173                 break;
3174         default:
3175                 PMD_DRV_LOG(ERR, "invalid protocol mask.");
3176                 return -EINVAL;
3177         }
3178
3179         switch (nfilter->dst_ip_mask) {
3180         case UINT32_MAX:
3181                 bfilter->dst_ipaddr_mask[0] = -1;
3182                 bfilter->dst_ipaddr[0] = nfilter->dst_ip;
3183                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR |
3184                         NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
3185                 break;
3186         default:
3187                 PMD_DRV_LOG(ERR, "invalid dst_ip mask.");
3188                 return -EINVAL;
3189         }
3190
3191         switch (nfilter->src_ip_mask) {
3192         case UINT32_MAX:
3193                 bfilter->src_ipaddr_mask[0] = -1;
3194                 bfilter->src_ipaddr[0] = nfilter->src_ip;
3195                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR |
3196                         NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
3197                 break;
3198         default:
3199                 PMD_DRV_LOG(ERR, "invalid src_ip mask.");
3200                 return -EINVAL;
3201         }
3202
3203         switch (nfilter->src_port_mask) {
3204         case UINT16_MAX:
3205                 bfilter->src_port_mask = -1;
3206                 bfilter->src_port = nfilter->src_port;
3207                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT |
3208                         NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
3209                 break;
3210         default:
3211                 PMD_DRV_LOG(ERR, "invalid src_port mask.");
3212                 return -EINVAL;
3213         }
3214
3215         bfilter->enables = en;
3216         return 0;
3217 }
3218
3219 static struct bnxt_filter_info*
3220 bnxt_match_ntuple_filter(struct bnxt *bp,
3221                          struct bnxt_filter_info *bfilter,
3222                          struct bnxt_vnic_info **mvnic)
3223 {
3224         struct bnxt_filter_info *mfilter = NULL;
3225         int i;
3226
3227         for (i = bp->nr_vnics - 1; i >= 0; i--) {
3228                 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
3229                 STAILQ_FOREACH(mfilter, &vnic->filter, next) {
3230                         if (bfilter->src_ipaddr[0] == mfilter->src_ipaddr[0] &&
3231                             bfilter->src_ipaddr_mask[0] ==
3232                             mfilter->src_ipaddr_mask[0] &&
3233                             bfilter->src_port == mfilter->src_port &&
3234                             bfilter->src_port_mask == mfilter->src_port_mask &&
3235                             bfilter->dst_ipaddr[0] == mfilter->dst_ipaddr[0] &&
3236                             bfilter->dst_ipaddr_mask[0] ==
3237                             mfilter->dst_ipaddr_mask[0] &&
3238                             bfilter->dst_port == mfilter->dst_port &&
3239                             bfilter->dst_port_mask == mfilter->dst_port_mask &&
3240                             bfilter->flags == mfilter->flags &&
3241                             bfilter->enables == mfilter->enables) {
3242                                 if (mvnic)
3243                                         *mvnic = vnic;
3244                                 return mfilter;
3245                         }
3246                 }
3247         }
3248         return NULL;
3249 }
3250
3251 static int
3252 bnxt_cfg_ntuple_filter(struct bnxt *bp,
3253                        struct rte_eth_ntuple_filter *nfilter,
3254                        enum rte_filter_op filter_op)
3255 {
3256         struct bnxt_filter_info *bfilter, *mfilter, *filter1;
3257         struct bnxt_vnic_info *vnic, *vnic0, *mvnic;
3258         int ret;
3259
3260         if (nfilter->flags != RTE_5TUPLE_FLAGS) {
3261                 PMD_DRV_LOG(ERR, "only 5tuple is supported.");
3262                 return -EINVAL;
3263         }
3264
3265         if (nfilter->flags & RTE_NTUPLE_FLAGS_TCP_FLAG) {
3266                 PMD_DRV_LOG(ERR, "Ntuple filter: TCP flags not supported\n");
3267                 return -EINVAL;
3268         }
3269
3270         bfilter = bnxt_get_unused_filter(bp);
3271         if (bfilter == NULL) {
3272                 PMD_DRV_LOG(ERR,
3273                         "Not enough resources for a new filter.\n");
3274                 return -ENOMEM;
3275         }
3276         ret = parse_ntuple_filter(bp, nfilter, bfilter);
3277         if (ret < 0)
3278                 goto free_filter;
3279
3280         vnic = &bp->vnic_info[nfilter->queue];
3281         vnic0 = BNXT_GET_DEFAULT_VNIC(bp);
3282         filter1 = STAILQ_FIRST(&vnic0->filter);
3283         if (filter1 == NULL) {
3284                 ret = -EINVAL;
3285                 goto free_filter;
3286         }
3287
3288         bfilter->dst_id = vnic->fw_vnic_id;
3289         bfilter->fw_l2_filter_id = filter1->fw_l2_filter_id;
3290         bfilter->enables |=
3291                 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID;
3292         bfilter->ethertype = 0x800;
3293         bfilter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
3294
3295         mfilter = bnxt_match_ntuple_filter(bp, bfilter, &mvnic);
3296
3297         if (mfilter != NULL && filter_op == RTE_ETH_FILTER_ADD &&
3298             bfilter->dst_id == mfilter->dst_id) {
3299                 PMD_DRV_LOG(ERR, "filter exists.\n");
3300                 ret = -EEXIST;
3301                 goto free_filter;
3302         } else if (mfilter != NULL && filter_op == RTE_ETH_FILTER_ADD &&
3303                    bfilter->dst_id != mfilter->dst_id) {
3304                 mfilter->dst_id = vnic->fw_vnic_id;
3305                 ret = bnxt_hwrm_set_ntuple_filter(bp, mfilter->dst_id, mfilter);
3306                 STAILQ_REMOVE(&mvnic->filter, mfilter, bnxt_filter_info, next);
3307                 STAILQ_INSERT_TAIL(&vnic->filter, mfilter, next);
3308                 PMD_DRV_LOG(ERR, "filter with matching pattern exists.\n");
3309                 PMD_DRV_LOG(ERR, " Updated it to the new destination queue\n");
3310                 goto free_filter;
3311         }
3312         if (mfilter == NULL && filter_op == RTE_ETH_FILTER_DELETE) {
3313                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
3314                 ret = -ENOENT;
3315                 goto free_filter;
3316         }
3317
3318         if (filter_op == RTE_ETH_FILTER_ADD) {
3319                 bfilter->filter_type = HWRM_CFA_NTUPLE_FILTER;
3320                 ret = bnxt_hwrm_set_ntuple_filter(bp, bfilter->dst_id, bfilter);
3321                 if (ret)
3322                         goto free_filter;
3323                 STAILQ_INSERT_TAIL(&vnic->filter, bfilter, next);
3324         } else {
3325                 if (mfilter == NULL) {
3326                         /* This should not happen. But for Coverity! */
3327                         ret = -ENOENT;
3328                         goto free_filter;
3329                 }
3330                 ret = bnxt_hwrm_clear_ntuple_filter(bp, mfilter);
3331
3332                 STAILQ_REMOVE(&vnic->filter, mfilter, bnxt_filter_info, next);
3333                 bnxt_free_filter(bp, mfilter);
3334                 bnxt_free_filter(bp, bfilter);
3335         }
3336
3337         return 0;
3338 free_filter:
3339         bnxt_free_filter(bp, bfilter);
3340         return ret;
3341 }
3342
3343 static int
3344 bnxt_ntuple_filter(struct rte_eth_dev *dev,
3345                         enum rte_filter_op filter_op,
3346                         void *arg)
3347 {
3348         struct bnxt *bp = dev->data->dev_private;
3349         int ret;
3350
3351         if (filter_op == RTE_ETH_FILTER_NOP)
3352                 return 0;
3353
3354         if (arg == NULL) {
3355                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
3356                             filter_op);
3357                 return -EINVAL;
3358         }
3359
3360         switch (filter_op) {
3361         case RTE_ETH_FILTER_ADD:
3362                 ret = bnxt_cfg_ntuple_filter(bp,
3363                         (struct rte_eth_ntuple_filter *)arg,
3364                         filter_op);
3365                 break;
3366         case RTE_ETH_FILTER_DELETE:
3367                 ret = bnxt_cfg_ntuple_filter(bp,
3368                         (struct rte_eth_ntuple_filter *)arg,
3369                         filter_op);
3370                 break;
3371         default:
3372                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
3373                 ret = -EINVAL;
3374                 break;
3375         }
3376         return ret;
3377 }
3378
3379 static int
3380 bnxt_parse_fdir_filter(struct bnxt *bp,
3381                        struct rte_eth_fdir_filter *fdir,
3382                        struct bnxt_filter_info *filter)
3383 {
3384         enum rte_fdir_mode fdir_mode =
3385                 bp->eth_dev->data->dev_conf.fdir_conf.mode;
3386         struct bnxt_vnic_info *vnic0, *vnic;
3387         struct bnxt_filter_info *filter1;
3388         uint32_t en = 0;
3389         int i;
3390
3391         if (fdir_mode == RTE_FDIR_MODE_PERFECT_TUNNEL)
3392                 return -EINVAL;
3393
3394         filter->l2_ovlan = fdir->input.flow_ext.vlan_tci;
3395         en |= EM_FLOW_ALLOC_INPUT_EN_OVLAN_VID;
3396
3397         switch (fdir->input.flow_type) {
3398         case RTE_ETH_FLOW_IPV4:
3399         case RTE_ETH_FLOW_NONFRAG_IPV4_OTHER:
3400                 /* FALLTHROUGH */
3401                 filter->src_ipaddr[0] = fdir->input.flow.ip4_flow.src_ip;
3402                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
3403                 filter->dst_ipaddr[0] = fdir->input.flow.ip4_flow.dst_ip;
3404                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
3405                 filter->ip_protocol = fdir->input.flow.ip4_flow.proto;
3406                 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
3407                 filter->ip_addr_type =
3408                         NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4;
3409                 filter->src_ipaddr_mask[0] = 0xffffffff;
3410                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
3411                 filter->dst_ipaddr_mask[0] = 0xffffffff;
3412                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
3413                 filter->ethertype = 0x800;
3414                 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
3415                 break;
3416         case RTE_ETH_FLOW_NONFRAG_IPV4_TCP:
3417                 filter->src_port = fdir->input.flow.tcp4_flow.src_port;
3418                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT;
3419                 filter->dst_port = fdir->input.flow.tcp4_flow.dst_port;
3420                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT;
3421                 filter->dst_port_mask = 0xffff;
3422                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
3423                 filter->src_port_mask = 0xffff;
3424                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
3425                 filter->src_ipaddr[0] = fdir->input.flow.tcp4_flow.ip.src_ip;
3426                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
3427                 filter->dst_ipaddr[0] = fdir->input.flow.tcp4_flow.ip.dst_ip;
3428                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
3429                 filter->ip_protocol = 6;
3430                 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
3431                 filter->ip_addr_type =
3432                         NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4;
3433                 filter->src_ipaddr_mask[0] = 0xffffffff;
3434                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
3435                 filter->dst_ipaddr_mask[0] = 0xffffffff;
3436                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
3437                 filter->ethertype = 0x800;
3438                 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
3439                 break;
3440         case RTE_ETH_FLOW_NONFRAG_IPV4_UDP:
3441                 filter->src_port = fdir->input.flow.udp4_flow.src_port;
3442                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT;
3443                 filter->dst_port = fdir->input.flow.udp4_flow.dst_port;
3444                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT;
3445                 filter->dst_port_mask = 0xffff;
3446                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
3447                 filter->src_port_mask = 0xffff;
3448                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
3449                 filter->src_ipaddr[0] = fdir->input.flow.udp4_flow.ip.src_ip;
3450                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
3451                 filter->dst_ipaddr[0] = fdir->input.flow.udp4_flow.ip.dst_ip;
3452                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
3453                 filter->ip_protocol = 17;
3454                 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
3455                 filter->ip_addr_type =
3456                         NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4;
3457                 filter->src_ipaddr_mask[0] = 0xffffffff;
3458                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
3459                 filter->dst_ipaddr_mask[0] = 0xffffffff;
3460                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
3461                 filter->ethertype = 0x800;
3462                 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
3463                 break;
3464         case RTE_ETH_FLOW_IPV6:
3465         case RTE_ETH_FLOW_NONFRAG_IPV6_OTHER:
3466                 /* FALLTHROUGH */
3467                 filter->ip_addr_type =
3468                         NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV6;
3469                 filter->ip_protocol = fdir->input.flow.ipv6_flow.proto;
3470                 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
3471                 rte_memcpy(filter->src_ipaddr,
3472                            fdir->input.flow.ipv6_flow.src_ip, 16);
3473                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
3474                 rte_memcpy(filter->dst_ipaddr,
3475                            fdir->input.flow.ipv6_flow.dst_ip, 16);
3476                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
3477                 memset(filter->dst_ipaddr_mask, 0xff, 16);
3478                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
3479                 memset(filter->src_ipaddr_mask, 0xff, 16);
3480                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
3481                 filter->ethertype = 0x86dd;
3482                 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
3483                 break;
3484         case RTE_ETH_FLOW_NONFRAG_IPV6_TCP:
3485                 filter->src_port = fdir->input.flow.tcp6_flow.src_port;
3486                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT;
3487                 filter->dst_port = fdir->input.flow.tcp6_flow.dst_port;
3488                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT;
3489                 filter->dst_port_mask = 0xffff;
3490                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
3491                 filter->src_port_mask = 0xffff;
3492                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
3493                 filter->ip_addr_type =
3494                         NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV6;
3495                 filter->ip_protocol = fdir->input.flow.tcp6_flow.ip.proto;
3496                 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
3497                 rte_memcpy(filter->src_ipaddr,
3498                            fdir->input.flow.tcp6_flow.ip.src_ip, 16);
3499                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
3500                 rte_memcpy(filter->dst_ipaddr,
3501                            fdir->input.flow.tcp6_flow.ip.dst_ip, 16);
3502                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
3503                 memset(filter->dst_ipaddr_mask, 0xff, 16);
3504                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
3505                 memset(filter->src_ipaddr_mask, 0xff, 16);
3506                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
3507                 filter->ethertype = 0x86dd;
3508                 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
3509                 break;
3510         case RTE_ETH_FLOW_NONFRAG_IPV6_UDP:
3511                 filter->src_port = fdir->input.flow.udp6_flow.src_port;
3512                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT;
3513                 filter->dst_port = fdir->input.flow.udp6_flow.dst_port;
3514                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT;
3515                 filter->dst_port_mask = 0xffff;
3516                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
3517                 filter->src_port_mask = 0xffff;
3518                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
3519                 filter->ip_addr_type =
3520                         NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV6;
3521                 filter->ip_protocol = fdir->input.flow.udp6_flow.ip.proto;
3522                 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
3523                 rte_memcpy(filter->src_ipaddr,
3524                            fdir->input.flow.udp6_flow.ip.src_ip, 16);
3525                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
3526                 rte_memcpy(filter->dst_ipaddr,
3527                            fdir->input.flow.udp6_flow.ip.dst_ip, 16);
3528                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
3529                 memset(filter->dst_ipaddr_mask, 0xff, 16);
3530                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
3531                 memset(filter->src_ipaddr_mask, 0xff, 16);
3532                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
3533                 filter->ethertype = 0x86dd;
3534                 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
3535                 break;
3536         case RTE_ETH_FLOW_L2_PAYLOAD:
3537                 filter->ethertype = fdir->input.flow.l2_flow.ether_type;
3538                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
3539                 break;
3540         case RTE_ETH_FLOW_VXLAN:
3541                 if (fdir->action.behavior == RTE_ETH_FDIR_REJECT)
3542                         return -EINVAL;
3543                 filter->vni = fdir->input.flow.tunnel_flow.tunnel_id;
3544                 filter->tunnel_type =
3545                         CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN;
3546                 en |= HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_TUNNEL_TYPE;
3547                 break;
3548         case RTE_ETH_FLOW_NVGRE:
3549                 if (fdir->action.behavior == RTE_ETH_FDIR_REJECT)
3550                         return -EINVAL;
3551                 filter->vni = fdir->input.flow.tunnel_flow.tunnel_id;
3552                 filter->tunnel_type =
3553                         CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_NVGRE;
3554                 en |= HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_TUNNEL_TYPE;
3555                 break;
3556         case RTE_ETH_FLOW_UNKNOWN:
3557         case RTE_ETH_FLOW_RAW:
3558         case RTE_ETH_FLOW_FRAG_IPV4:
3559         case RTE_ETH_FLOW_NONFRAG_IPV4_SCTP:
3560         case RTE_ETH_FLOW_FRAG_IPV6:
3561         case RTE_ETH_FLOW_NONFRAG_IPV6_SCTP:
3562         case RTE_ETH_FLOW_IPV6_EX:
3563         case RTE_ETH_FLOW_IPV6_TCP_EX:
3564         case RTE_ETH_FLOW_IPV6_UDP_EX:
3565         case RTE_ETH_FLOW_GENEVE:
3566                 /* FALLTHROUGH */
3567         default:
3568                 return -EINVAL;
3569         }
3570
3571         vnic0 = BNXT_GET_DEFAULT_VNIC(bp);
3572         vnic = &bp->vnic_info[fdir->action.rx_queue];
3573         if (vnic == NULL) {
3574                 PMD_DRV_LOG(ERR, "Invalid queue %d\n", fdir->action.rx_queue);
3575                 return -EINVAL;
3576         }
3577
3578         if (fdir_mode == RTE_FDIR_MODE_PERFECT_MAC_VLAN) {
3579                 rte_memcpy(filter->dst_macaddr,
3580                         fdir->input.flow.mac_vlan_flow.mac_addr.addr_bytes, 6);
3581                         en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_MACADDR;
3582         }
3583
3584         if (fdir->action.behavior == RTE_ETH_FDIR_REJECT) {
3585                 filter->flags = HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_DROP;
3586                 filter1 = STAILQ_FIRST(&vnic0->filter);
3587                 //filter1 = bnxt_get_l2_filter(bp, filter, vnic0);
3588         } else {
3589                 filter->dst_id = vnic->fw_vnic_id;
3590                 for (i = 0; i < RTE_ETHER_ADDR_LEN; i++)
3591                         if (filter->dst_macaddr[i] == 0x00)
3592                                 filter1 = STAILQ_FIRST(&vnic0->filter);
3593                         else
3594                                 filter1 = bnxt_get_l2_filter(bp, filter, vnic);
3595         }
3596
3597         if (filter1 == NULL)
3598                 return -EINVAL;
3599
3600         en |= HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID;
3601         filter->fw_l2_filter_id = filter1->fw_l2_filter_id;
3602
3603         filter->enables = en;
3604
3605         return 0;
3606 }
3607
3608 static struct bnxt_filter_info *
3609 bnxt_match_fdir(struct bnxt *bp, struct bnxt_filter_info *nf,
3610                 struct bnxt_vnic_info **mvnic)
3611 {
3612         struct bnxt_filter_info *mf = NULL;
3613         int i;
3614
3615         for (i = bp->nr_vnics - 1; i >= 0; i--) {
3616                 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
3617
3618                 STAILQ_FOREACH(mf, &vnic->filter, next) {
3619                         if (mf->filter_type == nf->filter_type &&
3620                             mf->flags == nf->flags &&
3621                             mf->src_port == nf->src_port &&
3622                             mf->src_port_mask == nf->src_port_mask &&
3623                             mf->dst_port == nf->dst_port &&
3624                             mf->dst_port_mask == nf->dst_port_mask &&
3625                             mf->ip_protocol == nf->ip_protocol &&
3626                             mf->ip_addr_type == nf->ip_addr_type &&
3627                             mf->ethertype == nf->ethertype &&
3628                             mf->vni == nf->vni &&
3629                             mf->tunnel_type == nf->tunnel_type &&
3630                             mf->l2_ovlan == nf->l2_ovlan &&
3631                             mf->l2_ovlan_mask == nf->l2_ovlan_mask &&
3632                             mf->l2_ivlan == nf->l2_ivlan &&
3633                             mf->l2_ivlan_mask == nf->l2_ivlan_mask &&
3634                             !memcmp(mf->l2_addr, nf->l2_addr,
3635                                     RTE_ETHER_ADDR_LEN) &&
3636                             !memcmp(mf->l2_addr_mask, nf->l2_addr_mask,
3637                                     RTE_ETHER_ADDR_LEN) &&
3638                             !memcmp(mf->src_macaddr, nf->src_macaddr,
3639                                     RTE_ETHER_ADDR_LEN) &&
3640                             !memcmp(mf->dst_macaddr, nf->dst_macaddr,
3641                                     RTE_ETHER_ADDR_LEN) &&
3642                             !memcmp(mf->src_ipaddr, nf->src_ipaddr,
3643                                     sizeof(nf->src_ipaddr)) &&
3644                             !memcmp(mf->src_ipaddr_mask, nf->src_ipaddr_mask,
3645                                     sizeof(nf->src_ipaddr_mask)) &&
3646                             !memcmp(mf->dst_ipaddr, nf->dst_ipaddr,
3647                                     sizeof(nf->dst_ipaddr)) &&
3648                             !memcmp(mf->dst_ipaddr_mask, nf->dst_ipaddr_mask,
3649                                     sizeof(nf->dst_ipaddr_mask))) {
3650                                 if (mvnic)
3651                                         *mvnic = vnic;
3652                                 return mf;
3653                         }
3654                 }
3655         }
3656         return NULL;
3657 }
3658
3659 static int
3660 bnxt_fdir_filter(struct rte_eth_dev *dev,
3661                  enum rte_filter_op filter_op,
3662                  void *arg)
3663 {
3664         struct bnxt *bp = dev->data->dev_private;
3665         struct rte_eth_fdir_filter *fdir  = (struct rte_eth_fdir_filter *)arg;
3666         struct bnxt_filter_info *filter, *match;
3667         struct bnxt_vnic_info *vnic, *mvnic;
3668         int ret = 0, i;
3669
3670         if (filter_op == RTE_ETH_FILTER_NOP)
3671                 return 0;
3672
3673         if (arg == NULL && filter_op != RTE_ETH_FILTER_FLUSH)
3674                 return -EINVAL;
3675
3676         switch (filter_op) {
3677         case RTE_ETH_FILTER_ADD:
3678         case RTE_ETH_FILTER_DELETE:
3679                 /* FALLTHROUGH */
3680                 filter = bnxt_get_unused_filter(bp);
3681                 if (filter == NULL) {
3682                         PMD_DRV_LOG(ERR,
3683                                 "Not enough resources for a new flow.\n");
3684                         return -ENOMEM;
3685                 }
3686
3687                 ret = bnxt_parse_fdir_filter(bp, fdir, filter);
3688                 if (ret != 0)
3689                         goto free_filter;
3690                 filter->filter_type = HWRM_CFA_NTUPLE_FILTER;
3691
3692                 if (fdir->action.behavior == RTE_ETH_FDIR_REJECT)
3693                         vnic = &bp->vnic_info[0];
3694                 else
3695                         vnic = &bp->vnic_info[fdir->action.rx_queue];
3696
3697                 match = bnxt_match_fdir(bp, filter, &mvnic);
3698                 if (match != NULL && filter_op == RTE_ETH_FILTER_ADD) {
3699                         if (match->dst_id == vnic->fw_vnic_id) {
3700                                 PMD_DRV_LOG(ERR, "Flow already exists.\n");
3701                                 ret = -EEXIST;
3702                                 goto free_filter;
3703                         } else {
3704                                 match->dst_id = vnic->fw_vnic_id;
3705                                 ret = bnxt_hwrm_set_ntuple_filter(bp,
3706                                                                   match->dst_id,
3707                                                                   match);
3708                                 STAILQ_REMOVE(&mvnic->filter, match,
3709                                               bnxt_filter_info, next);
3710                                 STAILQ_INSERT_TAIL(&vnic->filter, match, next);
3711                                 PMD_DRV_LOG(ERR,
3712                                         "Filter with matching pattern exist\n");
3713                                 PMD_DRV_LOG(ERR,
3714                                         "Updated it to new destination q\n");
3715                                 goto free_filter;
3716                         }
3717                 }
3718                 if (match == NULL && filter_op == RTE_ETH_FILTER_DELETE) {
3719                         PMD_DRV_LOG(ERR, "Flow does not exist.\n");
3720                         ret = -ENOENT;
3721                         goto free_filter;
3722                 }
3723
3724                 if (filter_op == RTE_ETH_FILTER_ADD) {
3725                         ret = bnxt_hwrm_set_ntuple_filter(bp,
3726                                                           filter->dst_id,
3727                                                           filter);
3728                         if (ret)
3729                                 goto free_filter;
3730                         STAILQ_INSERT_TAIL(&vnic->filter, filter, next);
3731                 } else {
3732                         ret = bnxt_hwrm_clear_ntuple_filter(bp, match);
3733                         STAILQ_REMOVE(&vnic->filter, match,
3734                                       bnxt_filter_info, next);
3735                         bnxt_free_filter(bp, match);
3736                         bnxt_free_filter(bp, filter);
3737                 }
3738                 break;
3739         case RTE_ETH_FILTER_FLUSH:
3740                 for (i = bp->nr_vnics - 1; i >= 0; i--) {
3741                         struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
3742
3743                         STAILQ_FOREACH(filter, &vnic->filter, next) {
3744                                 if (filter->filter_type ==
3745                                     HWRM_CFA_NTUPLE_FILTER) {
3746                                         ret =
3747                                         bnxt_hwrm_clear_ntuple_filter(bp,
3748                                                                       filter);
3749                                         STAILQ_REMOVE(&vnic->filter, filter,
3750                                                       bnxt_filter_info, next);
3751                                 }
3752                         }
3753                 }
3754                 return ret;
3755         case RTE_ETH_FILTER_UPDATE:
3756         case RTE_ETH_FILTER_STATS:
3757         case RTE_ETH_FILTER_INFO:
3758                 PMD_DRV_LOG(ERR, "operation %u not implemented", filter_op);
3759                 break;
3760         default:
3761                 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
3762                 ret = -EINVAL;
3763                 break;
3764         }
3765         return ret;
3766
3767 free_filter:
3768         bnxt_free_filter(bp, filter);
3769         return ret;
3770 }
3771
3772 int
3773 bnxt_filter_ctrl_op(struct rte_eth_dev *dev,
3774                     enum rte_filter_type filter_type,
3775                     enum rte_filter_op filter_op, void *arg)
3776 {
3777         struct bnxt *bp = dev->data->dev_private;
3778         int ret = 0;
3779
3780         if (!bp)
3781                 return -EIO;
3782
3783         if (BNXT_ETH_DEV_IS_REPRESENTOR(dev)) {
3784                 struct bnxt_representor *vfr = dev->data->dev_private;
3785                 bp = vfr->parent_dev->data->dev_private;
3786                 /* parent is deleted while children are still valid */
3787                 if (!bp) {
3788                         PMD_DRV_LOG(DEBUG, "BNXT Port:%d VFR Error %d:%d\n",
3789                                     dev->data->port_id,
3790                                     filter_type,
3791                                     filter_op);
3792                         return -EIO;
3793                 }
3794         }
3795
3796         ret = is_bnxt_in_error(bp);
3797         if (ret)
3798                 return ret;
3799
3800         switch (filter_type) {
3801         case RTE_ETH_FILTER_TUNNEL:
3802                 PMD_DRV_LOG(ERR,
3803                         "filter type: %d: To be implemented\n", filter_type);
3804                 break;
3805         case RTE_ETH_FILTER_FDIR:
3806                 ret = bnxt_fdir_filter(dev, filter_op, arg);
3807                 break;
3808         case RTE_ETH_FILTER_NTUPLE:
3809                 ret = bnxt_ntuple_filter(dev, filter_op, arg);
3810                 break;
3811         case RTE_ETH_FILTER_ETHERTYPE:
3812                 ret = bnxt_ethertype_filter(dev, filter_op, arg);
3813                 break;
3814         case RTE_ETH_FILTER_GENERIC:
3815                 if (filter_op != RTE_ETH_FILTER_GET)
3816                         return -EINVAL;
3817                 if (BNXT_TRUFLOW_EN(bp))
3818                         *(const void **)arg = &bnxt_ulp_rte_flow_ops;
3819                 else
3820                         *(const void **)arg = &bnxt_flow_ops;
3821                 break;
3822         default:
3823                 PMD_DRV_LOG(ERR,
3824                         "Filter type (%d) not supported", filter_type);
3825                 ret = -EINVAL;
3826                 break;
3827         }
3828         return ret;
3829 }
3830
3831 static const uint32_t *
3832 bnxt_dev_supported_ptypes_get_op(struct rte_eth_dev *dev)
3833 {
3834         static const uint32_t ptypes[] = {
3835                 RTE_PTYPE_L2_ETHER_VLAN,
3836                 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN,
3837                 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN,
3838                 RTE_PTYPE_L4_ICMP,
3839                 RTE_PTYPE_L4_TCP,
3840                 RTE_PTYPE_L4_UDP,
3841                 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN,
3842                 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN,
3843                 RTE_PTYPE_INNER_L4_ICMP,
3844                 RTE_PTYPE_INNER_L4_TCP,
3845                 RTE_PTYPE_INNER_L4_UDP,
3846                 RTE_PTYPE_UNKNOWN
3847         };
3848
3849         if (!dev->rx_pkt_burst)
3850                 return NULL;
3851
3852         return ptypes;
3853 }
3854
3855 static int bnxt_map_regs(struct bnxt *bp, uint32_t *reg_arr, int count,
3856                          int reg_win)
3857 {
3858         uint32_t reg_base = *reg_arr & 0xfffff000;
3859         uint32_t win_off;
3860         int i;
3861
3862         for (i = 0; i < count; i++) {
3863                 if ((reg_arr[i] & 0xfffff000) != reg_base)
3864                         return -ERANGE;
3865         }
3866         win_off = BNXT_GRCPF_REG_WINDOW_BASE_OUT + (reg_win - 1) * 4;
3867         rte_write32(reg_base, (uint8_t *)bp->bar0 + win_off);
3868         return 0;
3869 }
3870
3871 static int bnxt_map_ptp_regs(struct bnxt *bp)
3872 {
3873         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3874         uint32_t *reg_arr;
3875         int rc, i;
3876
3877         reg_arr = ptp->rx_regs;
3878         rc = bnxt_map_regs(bp, reg_arr, BNXT_PTP_RX_REGS, 5);
3879         if (rc)
3880                 return rc;
3881
3882         reg_arr = ptp->tx_regs;
3883         rc = bnxt_map_regs(bp, reg_arr, BNXT_PTP_TX_REGS, 6);
3884         if (rc)
3885                 return rc;
3886
3887         for (i = 0; i < BNXT_PTP_RX_REGS; i++)
3888                 ptp->rx_mapped_regs[i] = 0x5000 + (ptp->rx_regs[i] & 0xfff);
3889
3890         for (i = 0; i < BNXT_PTP_TX_REGS; i++)
3891                 ptp->tx_mapped_regs[i] = 0x6000 + (ptp->tx_regs[i] & 0xfff);
3892
3893         return 0;
3894 }
3895
3896 static void bnxt_unmap_ptp_regs(struct bnxt *bp)
3897 {
3898         rte_write32(0, (uint8_t *)bp->bar0 +
3899                          BNXT_GRCPF_REG_WINDOW_BASE_OUT + 16);
3900         rte_write32(0, (uint8_t *)bp->bar0 +
3901                          BNXT_GRCPF_REG_WINDOW_BASE_OUT + 20);
3902 }
3903
3904 static uint64_t bnxt_cc_read(struct bnxt *bp)
3905 {
3906         uint64_t ns;
3907
3908         ns = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3909                               BNXT_GRCPF_REG_SYNC_TIME));
3910         ns |= (uint64_t)(rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3911                                           BNXT_GRCPF_REG_SYNC_TIME + 4))) << 32;
3912         return ns;
3913 }
3914
3915 static int bnxt_get_tx_ts(struct bnxt *bp, uint64_t *ts)
3916 {
3917         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3918         uint32_t fifo;
3919
3920         fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3921                                 ptp->tx_mapped_regs[BNXT_PTP_TX_FIFO]));
3922         if (fifo & BNXT_PTP_TX_FIFO_EMPTY)
3923                 return -EAGAIN;
3924
3925         fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3926                                 ptp->tx_mapped_regs[BNXT_PTP_TX_FIFO]));
3927         *ts = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3928                                 ptp->tx_mapped_regs[BNXT_PTP_TX_TS_L]));
3929         *ts |= (uint64_t)rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3930                                 ptp->tx_mapped_regs[BNXT_PTP_TX_TS_H])) << 32;
3931
3932         return 0;
3933 }
3934
3935 static int bnxt_get_rx_ts(struct bnxt *bp, uint64_t *ts)
3936 {
3937         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3938         struct bnxt_pf_info *pf = bp->pf;
3939         uint16_t port_id;
3940         uint32_t fifo;
3941
3942         if (!ptp)
3943                 return -ENODEV;
3944
3945         fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3946                                 ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO]));
3947         if (!(fifo & BNXT_PTP_RX_FIFO_PENDING))
3948                 return -EAGAIN;
3949
3950         port_id = pf->port_id;
3951         rte_write32(1 << port_id, (uint8_t *)bp->bar0 +
3952                ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO_ADV]);
3953
3954         fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3955                                    ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO]));
3956         if (fifo & BNXT_PTP_RX_FIFO_PENDING) {
3957 /*              bnxt_clr_rx_ts(bp);       TBD  */
3958                 return -EBUSY;
3959         }
3960
3961         *ts = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3962                                 ptp->rx_mapped_regs[BNXT_PTP_RX_TS_L]));
3963         *ts |= (uint64_t)rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3964                                 ptp->rx_mapped_regs[BNXT_PTP_RX_TS_H])) << 32;
3965
3966         return 0;
3967 }
3968
3969 static int
3970 bnxt_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
3971 {
3972         uint64_t ns;
3973         struct bnxt *bp = dev->data->dev_private;
3974         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3975
3976         if (!ptp)
3977                 return 0;
3978
3979         ns = rte_timespec_to_ns(ts);
3980         /* Set the timecounters to a new value. */
3981         ptp->tc.nsec = ns;
3982
3983         return 0;
3984 }
3985
3986 static int
3987 bnxt_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
3988 {
3989         struct bnxt *bp = dev->data->dev_private;
3990         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3991         uint64_t ns, systime_cycles = 0;
3992         int rc = 0;
3993
3994         if (!ptp)
3995                 return 0;
3996
3997         if (BNXT_CHIP_THOR(bp))
3998                 rc = bnxt_hwrm_port_ts_query(bp, BNXT_PTP_FLAGS_CURRENT_TIME,
3999                                              &systime_cycles);
4000         else
4001                 systime_cycles = bnxt_cc_read(bp);
4002
4003         ns = rte_timecounter_update(&ptp->tc, systime_cycles);
4004         *ts = rte_ns_to_timespec(ns);
4005
4006         return rc;
4007 }
4008 static int
4009 bnxt_timesync_enable(struct rte_eth_dev *dev)
4010 {
4011         struct bnxt *bp = dev->data->dev_private;
4012         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
4013         uint32_t shift = 0;
4014         int rc;
4015
4016         if (!ptp)
4017                 return 0;
4018
4019         ptp->rx_filter = 1;
4020         ptp->tx_tstamp_en = 1;
4021         ptp->rxctl = BNXT_PTP_MSG_EVENTS;
4022
4023         rc = bnxt_hwrm_ptp_cfg(bp);
4024         if (rc)
4025                 return rc;
4026
4027         memset(&ptp->tc, 0, sizeof(struct rte_timecounter));
4028         memset(&ptp->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
4029         memset(&ptp->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
4030
4031         ptp->tc.cc_mask = BNXT_CYCLECOUNTER_MASK;
4032         ptp->tc.cc_shift = shift;
4033         ptp->tc.nsec_mask = (1ULL << shift) - 1;
4034
4035         ptp->rx_tstamp_tc.cc_mask = BNXT_CYCLECOUNTER_MASK;
4036         ptp->rx_tstamp_tc.cc_shift = shift;
4037         ptp->rx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
4038
4039         ptp->tx_tstamp_tc.cc_mask = BNXT_CYCLECOUNTER_MASK;
4040         ptp->tx_tstamp_tc.cc_shift = shift;
4041         ptp->tx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
4042
4043         if (!BNXT_CHIP_THOR(bp))
4044                 bnxt_map_ptp_regs(bp);
4045
4046         return 0;
4047 }
4048
4049 static int
4050 bnxt_timesync_disable(struct rte_eth_dev *dev)
4051 {
4052         struct bnxt *bp = dev->data->dev_private;
4053         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
4054
4055         if (!ptp)
4056                 return 0;
4057
4058         ptp->rx_filter = 0;
4059         ptp->tx_tstamp_en = 0;
4060         ptp->rxctl = 0;
4061
4062         bnxt_hwrm_ptp_cfg(bp);
4063
4064         if (!BNXT_CHIP_THOR(bp))
4065                 bnxt_unmap_ptp_regs(bp);
4066
4067         return 0;
4068 }
4069
4070 static int
4071 bnxt_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
4072                                  struct timespec *timestamp,
4073                                  uint32_t flags __rte_unused)
4074 {
4075         struct bnxt *bp = dev->data->dev_private;
4076         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
4077         uint64_t rx_tstamp_cycles = 0;
4078         uint64_t ns;
4079
4080         if (!ptp)
4081                 return 0;
4082
4083         if (BNXT_CHIP_THOR(bp))
4084                 rx_tstamp_cycles = ptp->rx_timestamp;
4085         else
4086                 bnxt_get_rx_ts(bp, &rx_tstamp_cycles);
4087
4088         ns = rte_timecounter_update(&ptp->rx_tstamp_tc, rx_tstamp_cycles);
4089         *timestamp = rte_ns_to_timespec(ns);
4090         return  0;
4091 }
4092
4093 static int
4094 bnxt_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
4095                                  struct timespec *timestamp)
4096 {
4097         struct bnxt *bp = dev->data->dev_private;
4098         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
4099         uint64_t tx_tstamp_cycles = 0;
4100         uint64_t ns;
4101         int rc = 0;
4102
4103         if (!ptp)
4104                 return 0;
4105
4106         if (BNXT_CHIP_THOR(bp))
4107                 rc = bnxt_hwrm_port_ts_query(bp, BNXT_PTP_FLAGS_PATH_TX,
4108                                              &tx_tstamp_cycles);
4109         else
4110                 rc = bnxt_get_tx_ts(bp, &tx_tstamp_cycles);
4111
4112         ns = rte_timecounter_update(&ptp->tx_tstamp_tc, tx_tstamp_cycles);
4113         *timestamp = rte_ns_to_timespec(ns);
4114
4115         return rc;
4116 }
4117
4118 static int
4119 bnxt_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
4120 {
4121         struct bnxt *bp = dev->data->dev_private;
4122         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
4123
4124         if (!ptp)
4125                 return 0;
4126
4127         ptp->tc.nsec += delta;
4128
4129         return 0;
4130 }
4131
4132 static int
4133 bnxt_get_eeprom_length_op(struct rte_eth_dev *dev)
4134 {
4135         struct bnxt *bp = dev->data->dev_private;
4136         int rc;
4137         uint32_t dir_entries;
4138         uint32_t entry_length;
4139
4140         rc = is_bnxt_in_error(bp);
4141         if (rc)
4142                 return rc;
4143
4144         PMD_DRV_LOG(INFO, PCI_PRI_FMT "\n",
4145                     bp->pdev->addr.domain, bp->pdev->addr.bus,
4146                     bp->pdev->addr.devid, bp->pdev->addr.function);
4147
4148         rc = bnxt_hwrm_nvm_get_dir_info(bp, &dir_entries, &entry_length);
4149         if (rc != 0)
4150                 return rc;
4151
4152         return dir_entries * entry_length;
4153 }
4154
4155 static int
4156 bnxt_get_eeprom_op(struct rte_eth_dev *dev,
4157                 struct rte_dev_eeprom_info *in_eeprom)
4158 {
4159         struct bnxt *bp = dev->data->dev_private;
4160         uint32_t index;
4161         uint32_t offset;
4162         int rc;
4163
4164         rc = is_bnxt_in_error(bp);
4165         if (rc)
4166                 return rc;
4167
4168         PMD_DRV_LOG(INFO, PCI_PRI_FMT " in_eeprom->offset = %d len = %d\n",
4169                     bp->pdev->addr.domain, bp->pdev->addr.bus,
4170                     bp->pdev->addr.devid, bp->pdev->addr.function,
4171                     in_eeprom->offset, in_eeprom->length);
4172
4173         if (in_eeprom->offset == 0) /* special offset value to get directory */
4174                 return bnxt_get_nvram_directory(bp, in_eeprom->length,
4175                                                 in_eeprom->data);
4176
4177         index = in_eeprom->offset >> 24;
4178         offset = in_eeprom->offset & 0xffffff;
4179
4180         if (index != 0)
4181                 return bnxt_hwrm_get_nvram_item(bp, index - 1, offset,
4182                                            in_eeprom->length, in_eeprom->data);
4183
4184         return 0;
4185 }
4186
4187 static bool bnxt_dir_type_is_ape_bin_format(uint16_t dir_type)
4188 {
4189         switch (dir_type) {
4190         case BNX_DIR_TYPE_CHIMP_PATCH:
4191         case BNX_DIR_TYPE_BOOTCODE:
4192         case BNX_DIR_TYPE_BOOTCODE_2:
4193         case BNX_DIR_TYPE_APE_FW:
4194         case BNX_DIR_TYPE_APE_PATCH:
4195         case BNX_DIR_TYPE_KONG_FW:
4196         case BNX_DIR_TYPE_KONG_PATCH:
4197         case BNX_DIR_TYPE_BONO_FW:
4198         case BNX_DIR_TYPE_BONO_PATCH:
4199                 /* FALLTHROUGH */
4200                 return true;
4201         }
4202
4203         return false;
4204 }
4205
4206 static bool bnxt_dir_type_is_other_exec_format(uint16_t dir_type)
4207 {
4208         switch (dir_type) {
4209         case BNX_DIR_TYPE_AVS:
4210         case BNX_DIR_TYPE_EXP_ROM_MBA:
4211         case BNX_DIR_TYPE_PCIE:
4212         case BNX_DIR_TYPE_TSCF_UCODE:
4213         case BNX_DIR_TYPE_EXT_PHY:
4214         case BNX_DIR_TYPE_CCM:
4215         case BNX_DIR_TYPE_ISCSI_BOOT:
4216         case BNX_DIR_TYPE_ISCSI_BOOT_IPV6:
4217         case BNX_DIR_TYPE_ISCSI_BOOT_IPV4N6:
4218                 /* FALLTHROUGH */
4219                 return true;
4220         }
4221
4222         return false;
4223 }
4224
4225 static bool bnxt_dir_type_is_executable(uint16_t dir_type)
4226 {
4227         return bnxt_dir_type_is_ape_bin_format(dir_type) ||
4228                 bnxt_dir_type_is_other_exec_format(dir_type);
4229 }
4230
4231 static int
4232 bnxt_set_eeprom_op(struct rte_eth_dev *dev,
4233                 struct rte_dev_eeprom_info *in_eeprom)
4234 {
4235         struct bnxt *bp = dev->data->dev_private;
4236         uint8_t index, dir_op;
4237         uint16_t type, ext, ordinal, attr;
4238         int rc;
4239
4240         rc = is_bnxt_in_error(bp);
4241         if (rc)
4242                 return rc;
4243
4244         PMD_DRV_LOG(INFO, PCI_PRI_FMT " in_eeprom->offset = %d len = %d\n",
4245                     bp->pdev->addr.domain, bp->pdev->addr.bus,
4246                     bp->pdev->addr.devid, bp->pdev->addr.function,
4247                     in_eeprom->offset, in_eeprom->length);
4248
4249         if (!BNXT_PF(bp)) {
4250                 PMD_DRV_LOG(ERR, "NVM write not supported from a VF\n");
4251                 return -EINVAL;
4252         }
4253
4254         type = in_eeprom->magic >> 16;
4255
4256         if (type == 0xffff) { /* special value for directory operations */
4257                 index = in_eeprom->magic & 0xff;
4258                 dir_op = in_eeprom->magic >> 8;
4259                 if (index == 0)
4260                         return -EINVAL;
4261                 switch (dir_op) {
4262                 case 0x0e: /* erase */
4263                         if (in_eeprom->offset != ~in_eeprom->magic)
4264                                 return -EINVAL;
4265                         return bnxt_hwrm_erase_nvram_directory(bp, index - 1);
4266                 default:
4267                         return -EINVAL;
4268                 }
4269         }
4270
4271         /* Create or re-write an NVM item: */
4272         if (bnxt_dir_type_is_executable(type) == true)
4273                 return -EOPNOTSUPP;
4274         ext = in_eeprom->magic & 0xffff;
4275         ordinal = in_eeprom->offset >> 16;
4276         attr = in_eeprom->offset & 0xffff;
4277
4278         return bnxt_hwrm_flash_nvram(bp, type, ordinal, ext, attr,
4279                                      in_eeprom->data, in_eeprom->length);
4280 }
4281
4282 /*
4283  * Initialization
4284  */
4285
4286 static const struct eth_dev_ops bnxt_dev_ops = {
4287         .dev_infos_get = bnxt_dev_info_get_op,
4288         .dev_close = bnxt_dev_close_op,
4289         .dev_configure = bnxt_dev_configure_op,
4290         .dev_start = bnxt_dev_start_op,
4291         .dev_stop = bnxt_dev_stop_op,
4292         .dev_set_link_up = bnxt_dev_set_link_up_op,
4293         .dev_set_link_down = bnxt_dev_set_link_down_op,
4294         .stats_get = bnxt_stats_get_op,
4295         .stats_reset = bnxt_stats_reset_op,
4296         .rx_queue_setup = bnxt_rx_queue_setup_op,
4297         .rx_queue_release = bnxt_rx_queue_release_op,
4298         .tx_queue_setup = bnxt_tx_queue_setup_op,
4299         .tx_queue_release = bnxt_tx_queue_release_op,
4300         .rx_queue_intr_enable = bnxt_rx_queue_intr_enable_op,
4301         .rx_queue_intr_disable = bnxt_rx_queue_intr_disable_op,
4302         .reta_update = bnxt_reta_update_op,
4303         .reta_query = bnxt_reta_query_op,
4304         .rss_hash_update = bnxt_rss_hash_update_op,
4305         .rss_hash_conf_get = bnxt_rss_hash_conf_get_op,
4306         .link_update = bnxt_link_update_op,
4307         .promiscuous_enable = bnxt_promiscuous_enable_op,
4308         .promiscuous_disable = bnxt_promiscuous_disable_op,
4309         .allmulticast_enable = bnxt_allmulticast_enable_op,
4310         .allmulticast_disable = bnxt_allmulticast_disable_op,
4311         .mac_addr_add = bnxt_mac_addr_add_op,
4312         .mac_addr_remove = bnxt_mac_addr_remove_op,
4313         .flow_ctrl_get = bnxt_flow_ctrl_get_op,
4314         .flow_ctrl_set = bnxt_flow_ctrl_set_op,
4315         .udp_tunnel_port_add  = bnxt_udp_tunnel_port_add_op,
4316         .udp_tunnel_port_del  = bnxt_udp_tunnel_port_del_op,
4317         .vlan_filter_set = bnxt_vlan_filter_set_op,
4318         .vlan_offload_set = bnxt_vlan_offload_set_op,
4319         .vlan_tpid_set = bnxt_vlan_tpid_set_op,
4320         .vlan_pvid_set = bnxt_vlan_pvid_set_op,
4321         .mtu_set = bnxt_mtu_set_op,
4322         .mac_addr_set = bnxt_set_default_mac_addr_op,
4323         .xstats_get = bnxt_dev_xstats_get_op,
4324         .xstats_get_names = bnxt_dev_xstats_get_names_op,
4325         .xstats_reset = bnxt_dev_xstats_reset_op,
4326         .fw_version_get = bnxt_fw_version_get,
4327         .set_mc_addr_list = bnxt_dev_set_mc_addr_list_op,
4328         .rxq_info_get = bnxt_rxq_info_get_op,
4329         .txq_info_get = bnxt_txq_info_get_op,
4330         .rx_burst_mode_get = bnxt_rx_burst_mode_get,
4331         .tx_burst_mode_get = bnxt_tx_burst_mode_get,
4332         .dev_led_on = bnxt_dev_led_on_op,
4333         .dev_led_off = bnxt_dev_led_off_op,
4334         .xstats_get_by_id = bnxt_dev_xstats_get_by_id_op,
4335         .xstats_get_names_by_id = bnxt_dev_xstats_get_names_by_id_op,
4336         .rx_queue_start = bnxt_rx_queue_start,
4337         .rx_queue_stop = bnxt_rx_queue_stop,
4338         .tx_queue_start = bnxt_tx_queue_start,
4339         .tx_queue_stop = bnxt_tx_queue_stop,
4340         .filter_ctrl = bnxt_filter_ctrl_op,
4341         .dev_supported_ptypes_get = bnxt_dev_supported_ptypes_get_op,
4342         .get_eeprom_length    = bnxt_get_eeprom_length_op,
4343         .get_eeprom           = bnxt_get_eeprom_op,
4344         .set_eeprom           = bnxt_set_eeprom_op,
4345         .timesync_enable      = bnxt_timesync_enable,
4346         .timesync_disable     = bnxt_timesync_disable,
4347         .timesync_read_time   = bnxt_timesync_read_time,
4348         .timesync_write_time   = bnxt_timesync_write_time,
4349         .timesync_adjust_time = bnxt_timesync_adjust_time,
4350         .timesync_read_rx_timestamp = bnxt_timesync_read_rx_timestamp,
4351         .timesync_read_tx_timestamp = bnxt_timesync_read_tx_timestamp,
4352 };
4353
4354 static uint32_t bnxt_map_reset_regs(struct bnxt *bp, uint32_t reg)
4355 {
4356         uint32_t offset;
4357
4358         /* Only pre-map the reset GRC registers using window 3 */
4359         rte_write32(reg & 0xfffff000, (uint8_t *)bp->bar0 +
4360                     BNXT_GRCPF_REG_WINDOW_BASE_OUT + 8);
4361
4362         offset = BNXT_GRCP_WINDOW_3_BASE + (reg & 0xffc);
4363
4364         return offset;
4365 }
4366
4367 int bnxt_map_fw_health_status_regs(struct bnxt *bp)
4368 {
4369         struct bnxt_error_recovery_info *info = bp->recovery_info;
4370         uint32_t reg_base = 0xffffffff;
4371         int i;
4372
4373         /* Only pre-map the monitoring GRC registers using window 2 */
4374         for (i = 0; i < BNXT_FW_STATUS_REG_CNT; i++) {
4375                 uint32_t reg = info->status_regs[i];
4376
4377                 if (BNXT_FW_STATUS_REG_TYPE(reg) != BNXT_FW_STATUS_REG_TYPE_GRC)
4378                         continue;
4379
4380                 if (reg_base == 0xffffffff)
4381                         reg_base = reg & 0xfffff000;
4382                 if ((reg & 0xfffff000) != reg_base)
4383                         return -ERANGE;
4384
4385                 /* Use mask 0xffc as the Lower 2 bits indicates
4386                  * address space location
4387                  */
4388                 info->mapped_status_regs[i] = BNXT_GRCP_WINDOW_2_BASE +
4389                                                 (reg & 0xffc);
4390         }
4391
4392         if (reg_base == 0xffffffff)
4393                 return 0;
4394
4395         rte_write32(reg_base, (uint8_t *)bp->bar0 +
4396                     BNXT_GRCPF_REG_WINDOW_BASE_OUT + 4);
4397
4398         return 0;
4399 }
4400
4401 static void bnxt_write_fw_reset_reg(struct bnxt *bp, uint32_t index)
4402 {
4403         struct bnxt_error_recovery_info *info = bp->recovery_info;
4404         uint32_t delay = info->delay_after_reset[index];
4405         uint32_t val = info->reset_reg_val[index];
4406         uint32_t reg = info->reset_reg[index];
4407         uint32_t type, offset;
4408
4409         type = BNXT_FW_STATUS_REG_TYPE(reg);
4410         offset = BNXT_FW_STATUS_REG_OFF(reg);
4411
4412         switch (type) {
4413         case BNXT_FW_STATUS_REG_TYPE_CFG:
4414                 rte_pci_write_config(bp->pdev, &val, sizeof(val), offset);
4415                 break;
4416         case BNXT_FW_STATUS_REG_TYPE_GRC:
4417                 offset = bnxt_map_reset_regs(bp, offset);
4418                 rte_write32(val, (uint8_t *)bp->bar0 + offset);
4419                 break;
4420         case BNXT_FW_STATUS_REG_TYPE_BAR0:
4421                 rte_write32(val, (uint8_t *)bp->bar0 + offset);
4422                 break;
4423         }
4424         /* wait on a specific interval of time until core reset is complete */
4425         if (delay)
4426                 rte_delay_ms(delay);
4427 }
4428
4429 static void bnxt_dev_cleanup(struct bnxt *bp)
4430 {
4431         bp->eth_dev->data->dev_link.link_status = 0;
4432         bp->link_info->link_up = 0;
4433         if (bp->eth_dev->data->dev_started)
4434                 bnxt_dev_stop_op(bp->eth_dev);
4435
4436         bnxt_uninit_resources(bp, true);
4437 }
4438
4439 static int bnxt_restore_vlan_filters(struct bnxt *bp)
4440 {
4441         struct rte_eth_dev *dev = bp->eth_dev;
4442         struct rte_vlan_filter_conf *vfc;
4443         int vidx, vbit, rc;
4444         uint16_t vlan_id;
4445
4446         for (vlan_id = 1; vlan_id <= RTE_ETHER_MAX_VLAN_ID; vlan_id++) {
4447                 vfc = &dev->data->vlan_filter_conf;
4448                 vidx = vlan_id / 64;
4449                 vbit = vlan_id % 64;
4450
4451                 /* Each bit corresponds to a VLAN id */
4452                 if (vfc->ids[vidx] & (UINT64_C(1) << vbit)) {
4453                         rc = bnxt_add_vlan_filter(bp, vlan_id);
4454                         if (rc)
4455                                 return rc;
4456                 }
4457         }
4458
4459         return 0;
4460 }
4461
4462 static int bnxt_restore_mac_filters(struct bnxt *bp)
4463 {
4464         struct rte_eth_dev *dev = bp->eth_dev;
4465         struct rte_eth_dev_info dev_info;
4466         struct rte_ether_addr *addr;
4467         uint64_t pool_mask;
4468         uint32_t pool = 0;
4469         uint16_t i;
4470         int rc;
4471
4472         if (BNXT_VF(bp) && !BNXT_VF_IS_TRUSTED(bp))
4473                 return 0;
4474
4475         rc = bnxt_dev_info_get_op(dev, &dev_info);
4476         if (rc)
4477                 return rc;
4478
4479         /* replay MAC address configuration */
4480         for (i = 1; i < dev_info.max_mac_addrs; i++) {
4481                 addr = &dev->data->mac_addrs[i];
4482
4483                 /* skip zero address */
4484                 if (rte_is_zero_ether_addr(addr))
4485                         continue;
4486
4487                 pool = 0;
4488                 pool_mask = dev->data->mac_pool_sel[i];
4489
4490                 do {
4491                         if (pool_mask & 1ULL) {
4492                                 rc = bnxt_mac_addr_add_op(dev, addr, i, pool);
4493                                 if (rc)
4494                                         return rc;
4495                         }
4496                         pool_mask >>= 1;
4497                         pool++;
4498                 } while (pool_mask);
4499         }
4500
4501         return 0;
4502 }
4503
4504 static int bnxt_restore_filters(struct bnxt *bp)
4505 {
4506         struct rte_eth_dev *dev = bp->eth_dev;
4507         int ret = 0;
4508
4509         if (dev->data->all_multicast) {
4510                 ret = bnxt_allmulticast_enable_op(dev);
4511                 if (ret)
4512                         return ret;
4513         }
4514         if (dev->data->promiscuous) {
4515                 ret = bnxt_promiscuous_enable_op(dev);
4516                 if (ret)
4517                         return ret;
4518         }
4519
4520         ret = bnxt_restore_mac_filters(bp);
4521         if (ret)
4522                 return ret;
4523
4524         ret = bnxt_restore_vlan_filters(bp);
4525         /* TODO restore other filters as well */
4526         return ret;
4527 }
4528
4529 static void bnxt_dev_recover(void *arg)
4530 {
4531         struct bnxt *bp = arg;
4532         int timeout = bp->fw_reset_max_msecs;
4533         int rc = 0;
4534
4535         /* Clear Error flag so that device re-init should happen */
4536         bp->flags &= ~BNXT_FLAG_FATAL_ERROR;
4537
4538         do {
4539                 rc = bnxt_hwrm_ver_get(bp, SHORT_HWRM_CMD_TIMEOUT);
4540                 if (rc == 0)
4541                         break;
4542                 rte_delay_ms(BNXT_FW_READY_WAIT_INTERVAL);
4543                 timeout -= BNXT_FW_READY_WAIT_INTERVAL;
4544         } while (rc && timeout);
4545
4546         if (rc) {
4547                 PMD_DRV_LOG(ERR, "FW is not Ready after reset\n");
4548                 goto err;
4549         }
4550
4551         rc = bnxt_init_resources(bp, true);
4552         if (rc) {
4553                 PMD_DRV_LOG(ERR,
4554                             "Failed to initialize resources after reset\n");
4555                 goto err;
4556         }
4557         /* clear reset flag as the device is initialized now */
4558         bp->flags &= ~BNXT_FLAG_FW_RESET;
4559
4560         rc = bnxt_dev_start_op(bp->eth_dev);
4561         if (rc) {
4562                 PMD_DRV_LOG(ERR, "Failed to start port after reset\n");
4563                 goto err_start;
4564         }
4565
4566         rc = bnxt_restore_filters(bp);
4567         if (rc)
4568                 goto err_start;
4569
4570         PMD_DRV_LOG(INFO, "Recovered from FW reset\n");
4571         return;
4572 err_start:
4573         bnxt_dev_stop_op(bp->eth_dev);
4574 err:
4575         bp->flags |= BNXT_FLAG_FATAL_ERROR;
4576         bnxt_uninit_resources(bp, false);
4577         PMD_DRV_LOG(ERR, "Failed to recover from FW reset\n");
4578 }
4579
4580 void bnxt_dev_reset_and_resume(void *arg)
4581 {
4582         struct bnxt *bp = arg;
4583         int rc;
4584
4585         bnxt_dev_cleanup(bp);
4586
4587         bnxt_wait_for_device_shutdown(bp);
4588
4589         rc = rte_eal_alarm_set(US_PER_MS * bp->fw_reset_min_msecs,
4590                                bnxt_dev_recover, (void *)bp);
4591         if (rc)
4592                 PMD_DRV_LOG(ERR, "Error setting recovery alarm");
4593 }
4594
4595 uint32_t bnxt_read_fw_status_reg(struct bnxt *bp, uint32_t index)
4596 {
4597         struct bnxt_error_recovery_info *info = bp->recovery_info;
4598         uint32_t reg = info->status_regs[index];
4599         uint32_t type, offset, val = 0;
4600
4601         type = BNXT_FW_STATUS_REG_TYPE(reg);
4602         offset = BNXT_FW_STATUS_REG_OFF(reg);
4603
4604         switch (type) {
4605         case BNXT_FW_STATUS_REG_TYPE_CFG:
4606                 rte_pci_read_config(bp->pdev, &val, sizeof(val), offset);
4607                 break;
4608         case BNXT_FW_STATUS_REG_TYPE_GRC:
4609                 offset = info->mapped_status_regs[index];
4610                 /* FALLTHROUGH */
4611         case BNXT_FW_STATUS_REG_TYPE_BAR0:
4612                 val = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
4613                                        offset));
4614                 break;
4615         }
4616
4617         return val;
4618 }
4619
4620 static int bnxt_fw_reset_all(struct bnxt *bp)
4621 {
4622         struct bnxt_error_recovery_info *info = bp->recovery_info;
4623         uint32_t i;
4624         int rc = 0;
4625
4626         if (info->flags & BNXT_FLAG_ERROR_RECOVERY_HOST) {
4627                 /* Reset through master function driver */
4628                 for (i = 0; i < info->reg_array_cnt; i++)
4629                         bnxt_write_fw_reset_reg(bp, i);
4630                 /* Wait for time specified by FW after triggering reset */
4631                 rte_delay_ms(info->master_func_wait_period_after_reset);
4632         } else if (info->flags & BNXT_FLAG_ERROR_RECOVERY_CO_CPU) {
4633                 /* Reset with the help of Kong processor */
4634                 rc = bnxt_hwrm_fw_reset(bp);
4635                 if (rc)
4636                         PMD_DRV_LOG(ERR, "Failed to reset FW\n");
4637         }
4638
4639         return rc;
4640 }
4641
4642 static void bnxt_fw_reset_cb(void *arg)
4643 {
4644         struct bnxt *bp = arg;
4645         struct bnxt_error_recovery_info *info = bp->recovery_info;
4646         int rc = 0;
4647
4648         /* Only Master function can do FW reset */
4649         if (bnxt_is_master_func(bp) &&
4650             bnxt_is_recovery_enabled(bp)) {
4651                 rc = bnxt_fw_reset_all(bp);
4652                 if (rc) {
4653                         PMD_DRV_LOG(ERR, "Adapter recovery failed\n");
4654                         return;
4655                 }
4656         }
4657
4658         /* if recovery method is ERROR_RECOVERY_CO_CPU, KONG will send
4659          * EXCEPTION_FATAL_ASYNC event to all the functions
4660          * (including MASTER FUNC). After receiving this Async, all the active
4661          * drivers should treat this case as FW initiated recovery
4662          */
4663         if (info->flags & BNXT_FLAG_ERROR_RECOVERY_HOST) {
4664                 bp->fw_reset_min_msecs = BNXT_MIN_FW_READY_TIMEOUT;
4665                 bp->fw_reset_max_msecs = BNXT_MAX_FW_RESET_TIMEOUT;
4666
4667                 /* To recover from error */
4668                 rte_eal_alarm_set(US_PER_MS, bnxt_dev_reset_and_resume,
4669                                   (void *)bp);
4670         }
4671 }
4672
4673 /* Driver should poll FW heartbeat, reset_counter with the frequency
4674  * advertised by FW in HWRM_ERROR_RECOVERY_QCFG.
4675  * When the driver detects heartbeat stop or change in reset_counter,
4676  * it has to trigger a reset to recover from the error condition.
4677  * A “master PF” is the function who will have the privilege to
4678  * initiate the chimp reset. The master PF will be elected by the
4679  * firmware and will be notified through async message.
4680  */
4681 static void bnxt_check_fw_health(void *arg)
4682 {
4683         struct bnxt *bp = arg;
4684         struct bnxt_error_recovery_info *info = bp->recovery_info;
4685         uint32_t val = 0, wait_msec;
4686
4687         if (!info || !bnxt_is_recovery_enabled(bp) ||
4688             is_bnxt_in_error(bp))
4689                 return;
4690
4691         val = bnxt_read_fw_status_reg(bp, BNXT_FW_HEARTBEAT_CNT_REG);
4692         if (val == info->last_heart_beat)
4693                 goto reset;
4694
4695         info->last_heart_beat = val;
4696
4697         val = bnxt_read_fw_status_reg(bp, BNXT_FW_RECOVERY_CNT_REG);
4698         if (val != info->last_reset_counter)
4699                 goto reset;
4700
4701         info->last_reset_counter = val;
4702
4703         rte_eal_alarm_set(US_PER_MS * info->driver_polling_freq,
4704                           bnxt_check_fw_health, (void *)bp);
4705
4706         return;
4707 reset:
4708         /* Stop DMA to/from device */
4709         bp->flags |= BNXT_FLAG_FATAL_ERROR;
4710         bp->flags |= BNXT_FLAG_FW_RESET;
4711
4712         PMD_DRV_LOG(ERR, "Detected FW dead condition\n");
4713
4714         if (bnxt_is_master_func(bp))
4715                 wait_msec = info->master_func_wait_period;
4716         else
4717                 wait_msec = info->normal_func_wait_period;
4718
4719         rte_eal_alarm_set(US_PER_MS * wait_msec,
4720                           bnxt_fw_reset_cb, (void *)bp);
4721 }
4722
4723 void bnxt_schedule_fw_health_check(struct bnxt *bp)
4724 {
4725         uint32_t polling_freq;
4726
4727         pthread_mutex_lock(&bp->health_check_lock);
4728
4729         if (!bnxt_is_recovery_enabled(bp))
4730                 goto done;
4731
4732         if (bp->flags & BNXT_FLAG_FW_HEALTH_CHECK_SCHEDULED)
4733                 goto done;
4734
4735         polling_freq = bp->recovery_info->driver_polling_freq;
4736
4737         rte_eal_alarm_set(US_PER_MS * polling_freq,
4738                           bnxt_check_fw_health, (void *)bp);
4739         bp->flags |= BNXT_FLAG_FW_HEALTH_CHECK_SCHEDULED;
4740
4741 done:
4742         pthread_mutex_unlock(&bp->health_check_lock);
4743 }
4744
4745 static void bnxt_cancel_fw_health_check(struct bnxt *bp)
4746 {
4747         if (!bnxt_is_recovery_enabled(bp))
4748                 return;
4749
4750         rte_eal_alarm_cancel(bnxt_check_fw_health, (void *)bp);
4751         bp->flags &= ~BNXT_FLAG_FW_HEALTH_CHECK_SCHEDULED;
4752 }
4753
4754 static bool bnxt_vf_pciid(uint16_t device_id)
4755 {
4756         switch (device_id) {
4757         case BROADCOM_DEV_ID_57304_VF:
4758         case BROADCOM_DEV_ID_57406_VF:
4759         case BROADCOM_DEV_ID_5731X_VF:
4760         case BROADCOM_DEV_ID_5741X_VF:
4761         case BROADCOM_DEV_ID_57414_VF:
4762         case BROADCOM_DEV_ID_STRATUS_NIC_VF1:
4763         case BROADCOM_DEV_ID_STRATUS_NIC_VF2:
4764         case BROADCOM_DEV_ID_58802_VF:
4765         case BROADCOM_DEV_ID_57500_VF1:
4766         case BROADCOM_DEV_ID_57500_VF2:
4767                 /* FALLTHROUGH */
4768                 return true;
4769         default:
4770                 return false;
4771         }
4772 }
4773
4774 static bool bnxt_thor_device(uint16_t device_id)
4775 {
4776         switch (device_id) {
4777         case BROADCOM_DEV_ID_57508:
4778         case BROADCOM_DEV_ID_57504:
4779         case BROADCOM_DEV_ID_57502:
4780         case BROADCOM_DEV_ID_57508_MF1:
4781         case BROADCOM_DEV_ID_57504_MF1:
4782         case BROADCOM_DEV_ID_57502_MF1:
4783         case BROADCOM_DEV_ID_57508_MF2:
4784         case BROADCOM_DEV_ID_57504_MF2:
4785         case BROADCOM_DEV_ID_57502_MF2:
4786         case BROADCOM_DEV_ID_57500_VF1:
4787         case BROADCOM_DEV_ID_57500_VF2:
4788                 /* FALLTHROUGH */
4789                 return true;
4790         default:
4791                 return false;
4792         }
4793 }
4794
4795 bool bnxt_stratus_device(struct bnxt *bp)
4796 {
4797         uint16_t device_id = bp->pdev->id.device_id;
4798
4799         switch (device_id) {
4800         case BROADCOM_DEV_ID_STRATUS_NIC:
4801         case BROADCOM_DEV_ID_STRATUS_NIC_VF1:
4802         case BROADCOM_DEV_ID_STRATUS_NIC_VF2:
4803                 /* FALLTHROUGH */
4804                 return true;
4805         default:
4806                 return false;
4807         }
4808 }
4809
4810 static int bnxt_init_board(struct rte_eth_dev *eth_dev)
4811 {
4812         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
4813         struct bnxt *bp = eth_dev->data->dev_private;
4814
4815         /* enable device (incl. PCI PM wakeup), and bus-mastering */
4816         bp->bar0 = (void *)pci_dev->mem_resource[0].addr;
4817         bp->doorbell_base = (void *)pci_dev->mem_resource[2].addr;
4818         if (!bp->bar0 || !bp->doorbell_base) {
4819                 PMD_DRV_LOG(ERR, "Unable to access Hardware\n");
4820                 return -ENODEV;
4821         }
4822
4823         bp->eth_dev = eth_dev;
4824         bp->pdev = pci_dev;
4825
4826         return 0;
4827 }
4828
4829 static int bnxt_alloc_ctx_mem_blk(struct bnxt *bp,
4830                                   struct bnxt_ctx_pg_info *ctx_pg,
4831                                   uint32_t mem_size,
4832                                   const char *suffix,
4833                                   uint16_t idx)
4834 {
4835         struct bnxt_ring_mem_info *rmem = &ctx_pg->ring_mem;
4836         const struct rte_memzone *mz = NULL;
4837         char mz_name[RTE_MEMZONE_NAMESIZE];
4838         rte_iova_t mz_phys_addr;
4839         uint64_t valid_bits = 0;
4840         uint32_t sz;
4841         int i;
4842
4843         if (!mem_size)
4844                 return 0;
4845
4846         rmem->nr_pages = RTE_ALIGN_MUL_CEIL(mem_size, BNXT_PAGE_SIZE) /
4847                          BNXT_PAGE_SIZE;
4848         rmem->page_size = BNXT_PAGE_SIZE;
4849         rmem->pg_arr = ctx_pg->ctx_pg_arr;
4850         rmem->dma_arr = ctx_pg->ctx_dma_arr;
4851         rmem->flags = BNXT_RMEM_VALID_PTE_FLAG;
4852
4853         valid_bits = PTU_PTE_VALID;
4854
4855         if (rmem->nr_pages > 1) {
4856                 snprintf(mz_name, RTE_MEMZONE_NAMESIZE,
4857                          "bnxt_ctx_pg_tbl%s_%x_%d",
4858                          suffix, idx, bp->eth_dev->data->port_id);
4859                 mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0;
4860                 mz = rte_memzone_lookup(mz_name);
4861                 if (!mz) {
4862                         mz = rte_memzone_reserve_aligned(mz_name,
4863                                                 rmem->nr_pages * 8,
4864                                                 SOCKET_ID_ANY,
4865                                                 RTE_MEMZONE_2MB |
4866                                                 RTE_MEMZONE_SIZE_HINT_ONLY |
4867                                                 RTE_MEMZONE_IOVA_CONTIG,
4868                                                 BNXT_PAGE_SIZE);
4869                         if (mz == NULL)
4870                                 return -ENOMEM;
4871                 }
4872
4873                 memset(mz->addr, 0, mz->len);
4874                 mz_phys_addr = mz->iova;
4875
4876                 rmem->pg_tbl = mz->addr;
4877                 rmem->pg_tbl_map = mz_phys_addr;
4878                 rmem->pg_tbl_mz = mz;
4879         }
4880
4881         snprintf(mz_name, RTE_MEMZONE_NAMESIZE, "bnxt_ctx_%s_%x_%d",
4882                  suffix, idx, bp->eth_dev->data->port_id);
4883         mz = rte_memzone_lookup(mz_name);
4884         if (!mz) {
4885                 mz = rte_memzone_reserve_aligned(mz_name,
4886                                                  mem_size,
4887                                                  SOCKET_ID_ANY,
4888                                                  RTE_MEMZONE_1GB |
4889                                                  RTE_MEMZONE_SIZE_HINT_ONLY |
4890                                                  RTE_MEMZONE_IOVA_CONTIG,
4891                                                  BNXT_PAGE_SIZE);
4892                 if (mz == NULL)
4893                         return -ENOMEM;
4894         }
4895
4896         memset(mz->addr, 0, mz->len);
4897         mz_phys_addr = mz->iova;
4898
4899         for (sz = 0, i = 0; sz < mem_size; sz += BNXT_PAGE_SIZE, i++) {
4900                 rmem->pg_arr[i] = ((char *)mz->addr) + sz;
4901                 rmem->dma_arr[i] = mz_phys_addr + sz;
4902
4903                 if (rmem->nr_pages > 1) {
4904                         if (i == rmem->nr_pages - 2 &&
4905                             (rmem->flags & BNXT_RMEM_RING_PTE_FLAG))
4906                                 valid_bits |= PTU_PTE_NEXT_TO_LAST;
4907                         else if (i == rmem->nr_pages - 1 &&
4908                                  (rmem->flags & BNXT_RMEM_RING_PTE_FLAG))
4909                                 valid_bits |= PTU_PTE_LAST;
4910
4911                         rmem->pg_tbl[i] = rte_cpu_to_le_64(rmem->dma_arr[i] |
4912                                                            valid_bits);
4913                 }
4914         }
4915
4916         rmem->mz = mz;
4917         if (rmem->vmem_size)
4918                 rmem->vmem = (void **)mz->addr;
4919         rmem->dma_arr[0] = mz_phys_addr;
4920         return 0;
4921 }
4922
4923 static void bnxt_free_ctx_mem(struct bnxt *bp)
4924 {
4925         int i;
4926
4927         if (!bp->ctx || !(bp->ctx->flags & BNXT_CTX_FLAG_INITED))
4928                 return;
4929
4930         bp->ctx->flags &= ~BNXT_CTX_FLAG_INITED;
4931         rte_memzone_free(bp->ctx->qp_mem.ring_mem.mz);
4932         rte_memzone_free(bp->ctx->srq_mem.ring_mem.mz);
4933         rte_memzone_free(bp->ctx->cq_mem.ring_mem.mz);
4934         rte_memzone_free(bp->ctx->vnic_mem.ring_mem.mz);
4935         rte_memzone_free(bp->ctx->stat_mem.ring_mem.mz);
4936         rte_memzone_free(bp->ctx->qp_mem.ring_mem.pg_tbl_mz);
4937         rte_memzone_free(bp->ctx->srq_mem.ring_mem.pg_tbl_mz);
4938         rte_memzone_free(bp->ctx->cq_mem.ring_mem.pg_tbl_mz);
4939         rte_memzone_free(bp->ctx->vnic_mem.ring_mem.pg_tbl_mz);
4940         rte_memzone_free(bp->ctx->stat_mem.ring_mem.pg_tbl_mz);
4941
4942         for (i = 0; i < bp->ctx->tqm_fp_rings_count + 1; i++) {
4943                 if (bp->ctx->tqm_mem[i])
4944                         rte_memzone_free(bp->ctx->tqm_mem[i]->ring_mem.mz);
4945         }
4946
4947         rte_free(bp->ctx);
4948         bp->ctx = NULL;
4949 }
4950
4951 #define bnxt_roundup(x, y)   ((((x) + ((y) - 1)) / (y)) * (y))
4952
4953 #define min_t(type, x, y) ({                    \
4954         type __min1 = (x);                      \
4955         type __min2 = (y);                      \
4956         __min1 < __min2 ? __min1 : __min2; })
4957
4958 #define max_t(type, x, y) ({                    \
4959         type __max1 = (x);                      \
4960         type __max2 = (y);                      \
4961         __max1 > __max2 ? __max1 : __max2; })
4962
4963 #define clamp_t(type, _x, min, max)     min_t(type, max_t(type, _x, min), max)
4964
4965 int bnxt_alloc_ctx_mem(struct bnxt *bp)
4966 {
4967         struct bnxt_ctx_pg_info *ctx_pg;
4968         struct bnxt_ctx_mem_info *ctx;
4969         uint32_t mem_size, ena, entries;
4970         uint32_t entries_sp, min;
4971         int i, rc;
4972
4973         rc = bnxt_hwrm_func_backing_store_qcaps(bp);
4974         if (rc) {
4975                 PMD_DRV_LOG(ERR, "Query context mem capability failed\n");
4976                 return rc;
4977         }
4978         ctx = bp->ctx;
4979         if (!ctx || (ctx->flags & BNXT_CTX_FLAG_INITED))
4980                 return 0;
4981
4982         ctx_pg = &ctx->qp_mem;
4983         ctx_pg->entries = ctx->qp_min_qp1_entries + ctx->qp_max_l2_entries;
4984         mem_size = ctx->qp_entry_size * ctx_pg->entries;
4985         rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "qp_mem", 0);
4986         if (rc)
4987                 return rc;
4988
4989         ctx_pg = &ctx->srq_mem;
4990         ctx_pg->entries = ctx->srq_max_l2_entries;
4991         mem_size = ctx->srq_entry_size * ctx_pg->entries;
4992         rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "srq_mem", 0);
4993         if (rc)
4994                 return rc;
4995
4996         ctx_pg = &ctx->cq_mem;
4997         ctx_pg->entries = ctx->cq_max_l2_entries;
4998         mem_size = ctx->cq_entry_size * ctx_pg->entries;
4999         rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "cq_mem", 0);
5000         if (rc)
5001                 return rc;
5002
5003         ctx_pg = &ctx->vnic_mem;
5004         ctx_pg->entries = ctx->vnic_max_vnic_entries +
5005                 ctx->vnic_max_ring_table_entries;
5006         mem_size = ctx->vnic_entry_size * ctx_pg->entries;
5007         rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "vnic_mem", 0);
5008         if (rc)
5009                 return rc;
5010
5011         ctx_pg = &ctx->stat_mem;
5012         ctx_pg->entries = ctx->stat_max_entries;
5013         mem_size = ctx->stat_entry_size * ctx_pg->entries;
5014         rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "stat_mem", 0);
5015         if (rc)
5016                 return rc;
5017
5018         min = ctx->tqm_min_entries_per_ring;
5019
5020         entries_sp = ctx->qp_max_l2_entries +
5021                      ctx->vnic_max_vnic_entries +
5022                      2 * ctx->qp_min_qp1_entries + min;
5023         entries_sp = bnxt_roundup(entries_sp, ctx->tqm_entries_multiple);
5024
5025         entries = ctx->qp_max_l2_entries + ctx->qp_min_qp1_entries;
5026         entries = bnxt_roundup(entries, ctx->tqm_entries_multiple);
5027         entries = clamp_t(uint32_t, entries, min,
5028                           ctx->tqm_max_entries_per_ring);
5029         for (i = 0, ena = 0; i < ctx->tqm_fp_rings_count + 1; i++) {
5030                 ctx_pg = ctx->tqm_mem[i];
5031                 ctx_pg->entries = i ? entries : entries_sp;
5032                 mem_size = ctx->tqm_entry_size * ctx_pg->entries;
5033                 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "tqm_mem", i);
5034                 if (rc)
5035                         return rc;
5036                 ena |= HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_SP << i;
5037         }
5038
5039         ena |= FUNC_BACKING_STORE_CFG_INPUT_DFLT_ENABLES;
5040         rc = bnxt_hwrm_func_backing_store_cfg(bp, ena);
5041         if (rc)
5042                 PMD_DRV_LOG(ERR,
5043                             "Failed to configure context mem: rc = %d\n", rc);
5044         else
5045                 ctx->flags |= BNXT_CTX_FLAG_INITED;
5046
5047         return rc;
5048 }
5049
5050 static int bnxt_alloc_stats_mem(struct bnxt *bp)
5051 {
5052         struct rte_pci_device *pci_dev = bp->pdev;
5053         char mz_name[RTE_MEMZONE_NAMESIZE];
5054         const struct rte_memzone *mz = NULL;
5055         uint32_t total_alloc_len;
5056         rte_iova_t mz_phys_addr;
5057
5058         if (pci_dev->id.device_id == BROADCOM_DEV_ID_NS2)
5059                 return 0;
5060
5061         snprintf(mz_name, RTE_MEMZONE_NAMESIZE,
5062                  "bnxt_" PCI_PRI_FMT "-%s", pci_dev->addr.domain,
5063                  pci_dev->addr.bus, pci_dev->addr.devid,
5064                  pci_dev->addr.function, "rx_port_stats");
5065         mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0;
5066         mz = rte_memzone_lookup(mz_name);
5067         total_alloc_len =
5068                 RTE_CACHE_LINE_ROUNDUP(sizeof(struct rx_port_stats) +
5069                                        sizeof(struct rx_port_stats_ext) + 512);
5070         if (!mz) {
5071                 mz = rte_memzone_reserve(mz_name, total_alloc_len,
5072                                          SOCKET_ID_ANY,
5073                                          RTE_MEMZONE_2MB |
5074                                          RTE_MEMZONE_SIZE_HINT_ONLY |
5075                                          RTE_MEMZONE_IOVA_CONTIG);
5076                 if (mz == NULL)
5077                         return -ENOMEM;
5078         }
5079         memset(mz->addr, 0, mz->len);
5080         mz_phys_addr = mz->iova;
5081
5082         bp->rx_mem_zone = (const void *)mz;
5083         bp->hw_rx_port_stats = mz->addr;
5084         bp->hw_rx_port_stats_map = mz_phys_addr;
5085
5086         snprintf(mz_name, RTE_MEMZONE_NAMESIZE,
5087                  "bnxt_" PCI_PRI_FMT "-%s", pci_dev->addr.domain,
5088                  pci_dev->addr.bus, pci_dev->addr.devid,
5089                  pci_dev->addr.function, "tx_port_stats");
5090         mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0;
5091         mz = rte_memzone_lookup(mz_name);
5092         total_alloc_len =
5093                 RTE_CACHE_LINE_ROUNDUP(sizeof(struct tx_port_stats) +
5094                                        sizeof(struct tx_port_stats_ext) + 512);
5095         if (!mz) {
5096                 mz = rte_memzone_reserve(mz_name,
5097                                          total_alloc_len,
5098                                          SOCKET_ID_ANY,
5099                                          RTE_MEMZONE_2MB |
5100                                          RTE_MEMZONE_SIZE_HINT_ONLY |
5101                                          RTE_MEMZONE_IOVA_CONTIG);
5102                 if (mz == NULL)
5103                         return -ENOMEM;
5104         }
5105         memset(mz->addr, 0, mz->len);
5106         mz_phys_addr = mz->iova;
5107
5108         bp->tx_mem_zone = (const void *)mz;
5109         bp->hw_tx_port_stats = mz->addr;
5110         bp->hw_tx_port_stats_map = mz_phys_addr;
5111         bp->flags |= BNXT_FLAG_PORT_STATS;
5112
5113         /* Display extended statistics if FW supports it */
5114         if (bp->hwrm_spec_code < HWRM_SPEC_CODE_1_8_4 ||
5115             bp->hwrm_spec_code == HWRM_SPEC_CODE_1_9_0 ||
5116             !(bp->flags & BNXT_FLAG_EXT_STATS_SUPPORTED))
5117                 return 0;
5118
5119         bp->hw_rx_port_stats_ext = (void *)
5120                 ((uint8_t *)bp->hw_rx_port_stats +
5121                  sizeof(struct rx_port_stats));
5122         bp->hw_rx_port_stats_ext_map = bp->hw_rx_port_stats_map +
5123                 sizeof(struct rx_port_stats);
5124         bp->flags |= BNXT_FLAG_EXT_RX_PORT_STATS;
5125
5126         if (bp->hwrm_spec_code < HWRM_SPEC_CODE_1_9_2 ||
5127             bp->flags & BNXT_FLAG_EXT_STATS_SUPPORTED) {
5128                 bp->hw_tx_port_stats_ext = (void *)
5129                         ((uint8_t *)bp->hw_tx_port_stats +
5130                          sizeof(struct tx_port_stats));
5131                 bp->hw_tx_port_stats_ext_map =
5132                         bp->hw_tx_port_stats_map +
5133                         sizeof(struct tx_port_stats);
5134                 bp->flags |= BNXT_FLAG_EXT_TX_PORT_STATS;
5135         }
5136
5137         return 0;
5138 }
5139
5140 static int bnxt_setup_mac_addr(struct rte_eth_dev *eth_dev)
5141 {
5142         struct bnxt *bp = eth_dev->data->dev_private;
5143         int rc = 0;
5144
5145         eth_dev->data->mac_addrs = rte_zmalloc("bnxt_mac_addr_tbl",
5146                                                RTE_ETHER_ADDR_LEN *
5147                                                bp->max_l2_ctx,
5148                                                0);
5149         if (eth_dev->data->mac_addrs == NULL) {
5150                 PMD_DRV_LOG(ERR, "Failed to alloc MAC addr tbl\n");
5151                 return -ENOMEM;
5152         }
5153
5154         if (!BNXT_HAS_DFLT_MAC_SET(bp)) {
5155                 if (BNXT_PF(bp))
5156                         return -EINVAL;
5157
5158                 /* Generate a random MAC address, if none was assigned by PF */
5159                 PMD_DRV_LOG(INFO, "VF MAC address not assigned by Host PF\n");
5160                 bnxt_eth_hw_addr_random(bp->mac_addr);
5161                 PMD_DRV_LOG(INFO,
5162                             "Assign random MAC:%02X:%02X:%02X:%02X:%02X:%02X\n",
5163                             bp->mac_addr[0], bp->mac_addr[1], bp->mac_addr[2],
5164                             bp->mac_addr[3], bp->mac_addr[4], bp->mac_addr[5]);
5165
5166                 rc = bnxt_hwrm_set_mac(bp);
5167                 if (rc)
5168                         return rc;
5169         }
5170
5171         /* Copy the permanent MAC from the FUNC_QCAPS response */
5172         memcpy(&eth_dev->data->mac_addrs[0], bp->mac_addr, RTE_ETHER_ADDR_LEN);
5173
5174         return rc;
5175 }
5176
5177 static int bnxt_restore_dflt_mac(struct bnxt *bp)
5178 {
5179         int rc = 0;
5180
5181         /* MAC is already configured in FW */
5182         if (BNXT_HAS_DFLT_MAC_SET(bp))
5183                 return 0;
5184
5185         /* Restore the old MAC configured */
5186         rc = bnxt_hwrm_set_mac(bp);
5187         if (rc)
5188                 PMD_DRV_LOG(ERR, "Failed to restore MAC address\n");
5189
5190         return rc;
5191 }
5192
5193 static void bnxt_config_vf_req_fwd(struct bnxt *bp)
5194 {
5195         if (!BNXT_PF(bp))
5196                 return;
5197
5198 #define ALLOW_FUNC(x)   \
5199         { \
5200                 uint32_t arg = (x); \
5201                 bp->pf->vf_req_fwd[((arg) >> 5)] &= \
5202                 ~rte_cpu_to_le_32(1 << ((arg) & 0x1f)); \
5203         }
5204
5205         /* Forward all requests if firmware is new enough */
5206         if (((bp->fw_ver >= ((20 << 24) | (6 << 16) | (100 << 8))) &&
5207              (bp->fw_ver < ((20 << 24) | (7 << 16)))) ||
5208             ((bp->fw_ver >= ((20 << 24) | (8 << 16))))) {
5209                 memset(bp->pf->vf_req_fwd, 0xff, sizeof(bp->pf->vf_req_fwd));
5210         } else {
5211                 PMD_DRV_LOG(WARNING,
5212                             "Firmware too old for VF mailbox functionality\n");
5213                 memset(bp->pf->vf_req_fwd, 0, sizeof(bp->pf->vf_req_fwd));
5214         }
5215
5216         /*
5217          * The following are used for driver cleanup. If we disallow these,
5218          * VF drivers can't clean up cleanly.
5219          */
5220         ALLOW_FUNC(HWRM_FUNC_DRV_UNRGTR);
5221         ALLOW_FUNC(HWRM_VNIC_FREE);
5222         ALLOW_FUNC(HWRM_RING_FREE);
5223         ALLOW_FUNC(HWRM_RING_GRP_FREE);
5224         ALLOW_FUNC(HWRM_VNIC_RSS_COS_LB_CTX_FREE);
5225         ALLOW_FUNC(HWRM_CFA_L2_FILTER_FREE);
5226         ALLOW_FUNC(HWRM_STAT_CTX_FREE);
5227         ALLOW_FUNC(HWRM_PORT_PHY_QCFG);
5228         ALLOW_FUNC(HWRM_VNIC_TPA_CFG);
5229 }
5230
5231 uint16_t
5232 bnxt_get_svif(uint16_t port_id, bool func_svif,
5233               enum bnxt_ulp_intf_type type)
5234 {
5235         struct rte_eth_dev *eth_dev;
5236         struct bnxt *bp;
5237
5238         eth_dev = &rte_eth_devices[port_id];
5239         if (BNXT_ETH_DEV_IS_REPRESENTOR(eth_dev)) {
5240                 struct bnxt_representor *vfr = eth_dev->data->dev_private;
5241                 if (!vfr)
5242                         return 0;
5243
5244                 if (type == BNXT_ULP_INTF_TYPE_VF_REP)
5245                         return vfr->svif;
5246
5247                 eth_dev = vfr->parent_dev;
5248         }
5249
5250         bp = eth_dev->data->dev_private;
5251
5252         return func_svif ? bp->func_svif : bp->port_svif;
5253 }
5254
5255 uint16_t
5256 bnxt_get_vnic_id(uint16_t port, enum bnxt_ulp_intf_type type)
5257 {
5258         struct rte_eth_dev *eth_dev;
5259         struct bnxt_vnic_info *vnic;
5260         struct bnxt *bp;
5261
5262         eth_dev = &rte_eth_devices[port];
5263         if (BNXT_ETH_DEV_IS_REPRESENTOR(eth_dev)) {
5264                 struct bnxt_representor *vfr = eth_dev->data->dev_private;
5265                 if (!vfr)
5266                         return 0;
5267
5268                 if (type == BNXT_ULP_INTF_TYPE_VF_REP)
5269                         return vfr->dflt_vnic_id;
5270
5271                 eth_dev = vfr->parent_dev;
5272         }
5273
5274         bp = eth_dev->data->dev_private;
5275
5276         vnic = BNXT_GET_DEFAULT_VNIC(bp);
5277
5278         return vnic->fw_vnic_id;
5279 }
5280
5281 uint16_t
5282 bnxt_get_fw_func_id(uint16_t port, enum bnxt_ulp_intf_type type)
5283 {
5284         struct rte_eth_dev *eth_dev;
5285         struct bnxt *bp;
5286
5287         eth_dev = &rte_eth_devices[port];
5288         if (BNXT_ETH_DEV_IS_REPRESENTOR(eth_dev)) {
5289                 struct bnxt_representor *vfr = eth_dev->data->dev_private;
5290                 if (!vfr)
5291                         return 0;
5292
5293                 if (type == BNXT_ULP_INTF_TYPE_VF_REP)
5294                         return vfr->fw_fid;
5295
5296                 eth_dev = vfr->parent_dev;
5297         }
5298
5299         bp = eth_dev->data->dev_private;
5300
5301         return bp->fw_fid;
5302 }
5303
5304 enum bnxt_ulp_intf_type
5305 bnxt_get_interface_type(uint16_t port)
5306 {
5307         struct rte_eth_dev *eth_dev;
5308         struct bnxt *bp;
5309
5310         eth_dev = &rte_eth_devices[port];
5311         if (BNXT_ETH_DEV_IS_REPRESENTOR(eth_dev))
5312                 return BNXT_ULP_INTF_TYPE_VF_REP;
5313
5314         bp = eth_dev->data->dev_private;
5315         if (BNXT_PF(bp))
5316                 return BNXT_ULP_INTF_TYPE_PF;
5317         else if (BNXT_VF_IS_TRUSTED(bp))
5318                 return BNXT_ULP_INTF_TYPE_TRUSTED_VF;
5319         else if (BNXT_VF(bp))
5320                 return BNXT_ULP_INTF_TYPE_VF;
5321
5322         return BNXT_ULP_INTF_TYPE_INVALID;
5323 }
5324
5325 uint16_t
5326 bnxt_get_phy_port_id(uint16_t port_id)
5327 {
5328         struct bnxt_representor *vfr;
5329         struct rte_eth_dev *eth_dev;
5330         struct bnxt *bp;
5331
5332         eth_dev = &rte_eth_devices[port_id];
5333         if (BNXT_ETH_DEV_IS_REPRESENTOR(eth_dev)) {
5334                 vfr = eth_dev->data->dev_private;
5335                 if (!vfr)
5336                         return 0;
5337
5338                 eth_dev = vfr->parent_dev;
5339         }
5340
5341         bp = eth_dev->data->dev_private;
5342
5343         return BNXT_PF(bp) ? bp->pf->port_id : bp->parent->port_id;
5344 }
5345
5346 uint16_t
5347 bnxt_get_parif(uint16_t port_id, enum bnxt_ulp_intf_type type)
5348 {
5349         struct rte_eth_dev *eth_dev;
5350         struct bnxt *bp;
5351
5352         eth_dev = &rte_eth_devices[port_id];
5353         if (BNXT_ETH_DEV_IS_REPRESENTOR(eth_dev)) {
5354                 struct bnxt_representor *vfr = eth_dev->data->dev_private;
5355                 if (!vfr)
5356                         return 0;
5357
5358                 if (type == BNXT_ULP_INTF_TYPE_VF_REP)
5359                         return vfr->fw_fid - 1;
5360
5361                 eth_dev = vfr->parent_dev;
5362         }
5363
5364         bp = eth_dev->data->dev_private;
5365
5366         return BNXT_PF(bp) ? bp->fw_fid - 1 : bp->parent->fid - 1;
5367 }
5368
5369 uint16_t
5370 bnxt_get_vport(uint16_t port_id)
5371 {
5372         return (1 << bnxt_get_phy_port_id(port_id));
5373 }
5374
5375 static void bnxt_alloc_error_recovery_info(struct bnxt *bp)
5376 {
5377         struct bnxt_error_recovery_info *info = bp->recovery_info;
5378
5379         if (info) {
5380                 if (!(bp->fw_cap & BNXT_FW_CAP_HCOMM_FW_STATUS))
5381                         memset(info, 0, sizeof(*info));
5382                 return;
5383         }
5384
5385         if (!(bp->fw_cap & BNXT_FW_CAP_ERROR_RECOVERY))
5386                 return;
5387
5388         info = rte_zmalloc("bnxt_hwrm_error_recovery_qcfg",
5389                            sizeof(*info), 0);
5390         if (!info)
5391                 bp->fw_cap &= ~BNXT_FW_CAP_ERROR_RECOVERY;
5392
5393         bp->recovery_info = info;
5394 }
5395
5396 static void bnxt_check_fw_status(struct bnxt *bp)
5397 {
5398         uint32_t fw_status;
5399
5400         if (!(bp->recovery_info &&
5401               (bp->fw_cap & BNXT_FW_CAP_HCOMM_FW_STATUS)))
5402                 return;
5403
5404         fw_status = bnxt_read_fw_status_reg(bp, BNXT_FW_STATUS_REG);
5405         if (fw_status != BNXT_FW_STATUS_HEALTHY)
5406                 PMD_DRV_LOG(ERR, "Firmware not responding, status: %#x\n",
5407                             fw_status);
5408 }
5409
5410 static int bnxt_map_hcomm_fw_status_reg(struct bnxt *bp)
5411 {
5412         struct bnxt_error_recovery_info *info = bp->recovery_info;
5413         uint32_t status_loc;
5414         uint32_t sig_ver;
5415
5416         rte_write32(HCOMM_STATUS_STRUCT_LOC, (uint8_t *)bp->bar0 +
5417                     BNXT_GRCPF_REG_WINDOW_BASE_OUT + 4);
5418         sig_ver = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
5419                                    BNXT_GRCP_WINDOW_2_BASE +
5420                                    offsetof(struct hcomm_status,
5421                                             sig_ver)));
5422         /* If the signature is absent, then FW does not support this feature */
5423         if ((sig_ver & HCOMM_STATUS_SIGNATURE_MASK) !=
5424             HCOMM_STATUS_SIGNATURE_VAL)
5425                 return 0;
5426
5427         if (!info) {
5428                 info = rte_zmalloc("bnxt_hwrm_error_recovery_qcfg",
5429                                    sizeof(*info), 0);
5430                 if (!info)
5431                         return -ENOMEM;
5432                 bp->recovery_info = info;
5433         } else {
5434                 memset(info, 0, sizeof(*info));
5435         }
5436
5437         status_loc = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
5438                                       BNXT_GRCP_WINDOW_2_BASE +
5439                                       offsetof(struct hcomm_status,
5440                                                fw_status_loc)));
5441
5442         /* Only pre-map the FW health status GRC register */
5443         if (BNXT_FW_STATUS_REG_TYPE(status_loc) != BNXT_FW_STATUS_REG_TYPE_GRC)
5444                 return 0;
5445
5446         info->status_regs[BNXT_FW_STATUS_REG] = status_loc;
5447         info->mapped_status_regs[BNXT_FW_STATUS_REG] =
5448                 BNXT_GRCP_WINDOW_2_BASE + (status_loc & BNXT_GRCP_OFFSET_MASK);
5449
5450         rte_write32((status_loc & BNXT_GRCP_BASE_MASK), (uint8_t *)bp->bar0 +
5451                     BNXT_GRCPF_REG_WINDOW_BASE_OUT + 4);
5452
5453         bp->fw_cap |= BNXT_FW_CAP_HCOMM_FW_STATUS;
5454
5455         return 0;
5456 }
5457
5458 static int bnxt_init_fw(struct bnxt *bp)
5459 {
5460         uint16_t mtu;
5461         int rc = 0;
5462
5463         bp->fw_cap = 0;
5464
5465         rc = bnxt_map_hcomm_fw_status_reg(bp);
5466         if (rc)
5467                 return rc;
5468
5469         rc = bnxt_hwrm_ver_get(bp, DFLT_HWRM_CMD_TIMEOUT);
5470         if (rc) {
5471                 bnxt_check_fw_status(bp);
5472                 return rc;
5473         }
5474
5475         rc = bnxt_hwrm_func_reset(bp);
5476         if (rc)
5477                 return -EIO;
5478
5479         rc = bnxt_hwrm_vnic_qcaps(bp);
5480         if (rc)
5481                 return rc;
5482
5483         rc = bnxt_hwrm_queue_qportcfg(bp);
5484         if (rc)
5485                 return rc;
5486
5487         /* Get the MAX capabilities for this function.
5488          * This function also allocates context memory for TQM rings and
5489          * informs the firmware about this allocated backing store memory.
5490          */
5491         rc = bnxt_hwrm_func_qcaps(bp);
5492         if (rc)
5493                 return rc;
5494
5495         rc = bnxt_hwrm_func_qcfg(bp, &mtu);
5496         if (rc)
5497                 return rc;
5498
5499         bnxt_hwrm_port_mac_qcfg(bp);
5500
5501         bnxt_hwrm_parent_pf_qcfg(bp);
5502
5503         bnxt_hwrm_port_phy_qcaps(bp);
5504
5505         bnxt_alloc_error_recovery_info(bp);
5506         /* Get the adapter error recovery support info */
5507         rc = bnxt_hwrm_error_recovery_qcfg(bp);
5508         if (rc)
5509                 bp->fw_cap &= ~BNXT_FW_CAP_ERROR_RECOVERY;
5510
5511         bnxt_hwrm_port_led_qcaps(bp);
5512
5513         return 0;
5514 }
5515
5516 static int
5517 bnxt_init_locks(struct bnxt *bp)
5518 {
5519         int err;
5520
5521         err = pthread_mutex_init(&bp->flow_lock, NULL);
5522         if (err) {
5523                 PMD_DRV_LOG(ERR, "Unable to initialize flow_lock\n");
5524                 return err;
5525         }
5526
5527         err = pthread_mutex_init(&bp->def_cp_lock, NULL);
5528         if (err)
5529                 PMD_DRV_LOG(ERR, "Unable to initialize def_cp_lock\n");
5530
5531         err = pthread_mutex_init(&bp->health_check_lock, NULL);
5532         if (err)
5533                 PMD_DRV_LOG(ERR, "Unable to initialize health_check_lock\n");
5534         return err;
5535 }
5536
5537 static int bnxt_init_resources(struct bnxt *bp, bool reconfig_dev)
5538 {
5539         int rc = 0;
5540
5541         rc = bnxt_init_fw(bp);
5542         if (rc)
5543                 return rc;
5544
5545         if (!reconfig_dev) {
5546                 rc = bnxt_setup_mac_addr(bp->eth_dev);
5547                 if (rc)
5548                         return rc;
5549         } else {
5550                 rc = bnxt_restore_dflt_mac(bp);
5551                 if (rc)
5552                         return rc;
5553         }
5554
5555         bnxt_config_vf_req_fwd(bp);
5556
5557         rc = bnxt_hwrm_func_driver_register(bp);
5558         if (rc) {
5559                 PMD_DRV_LOG(ERR, "Failed to register driver");
5560                 return -EBUSY;
5561         }
5562
5563         if (BNXT_PF(bp)) {
5564                 if (bp->pdev->max_vfs) {
5565                         rc = bnxt_hwrm_allocate_vfs(bp, bp->pdev->max_vfs);
5566                         if (rc) {
5567                                 PMD_DRV_LOG(ERR, "Failed to allocate VFs\n");
5568                                 return rc;
5569                         }
5570                 } else {
5571                         rc = bnxt_hwrm_allocate_pf_only(bp);
5572                         if (rc) {
5573                                 PMD_DRV_LOG(ERR,
5574                                             "Failed to allocate PF resources");
5575                                 return rc;
5576                         }
5577                 }
5578         }
5579
5580         rc = bnxt_alloc_mem(bp, reconfig_dev);
5581         if (rc)
5582                 return rc;
5583
5584         rc = bnxt_setup_int(bp);
5585         if (rc)
5586                 return rc;
5587
5588         rc = bnxt_request_int(bp);
5589         if (rc)
5590                 return rc;
5591
5592         rc = bnxt_init_ctx_mem(bp);
5593         if (rc) {
5594                 PMD_DRV_LOG(ERR, "Failed to init adv_flow_counters\n");
5595                 return rc;
5596         }
5597
5598         rc = bnxt_init_locks(bp);
5599         if (rc)
5600                 return rc;
5601
5602         return 0;
5603 }
5604
5605 static int
5606 bnxt_parse_devarg_truflow(__rte_unused const char *key,
5607                           const char *value, void *opaque_arg)
5608 {
5609         struct bnxt *bp = opaque_arg;
5610         unsigned long truflow;
5611         char *end = NULL;
5612
5613         if (!value || !opaque_arg) {
5614                 PMD_DRV_LOG(ERR,
5615                             "Invalid parameter passed to truflow devargs.\n");
5616                 return -EINVAL;
5617         }
5618
5619         truflow = strtoul(value, &end, 10);
5620         if (end == NULL || *end != '\0' ||
5621             (truflow == ULONG_MAX && errno == ERANGE)) {
5622                 PMD_DRV_LOG(ERR,
5623                             "Invalid parameter passed to truflow devargs.\n");
5624                 return -EINVAL;
5625         }
5626
5627         if (BNXT_DEVARG_TRUFLOW_INVALID(truflow)) {
5628                 PMD_DRV_LOG(ERR,
5629                             "Invalid value passed to truflow devargs.\n");
5630                 return -EINVAL;
5631         }
5632
5633         if (truflow) {
5634                 bp->flags |= BNXT_FLAG_TRUFLOW_EN;
5635                 PMD_DRV_LOG(INFO, "Host-based truflow feature enabled.\n");
5636         } else {
5637                 bp->flags &= ~BNXT_FLAG_TRUFLOW_EN;
5638                 PMD_DRV_LOG(INFO, "Host-based truflow feature disabled.\n");
5639         }
5640
5641         return 0;
5642 }
5643
5644 static int
5645 bnxt_parse_devarg_flow_xstat(__rte_unused const char *key,
5646                              const char *value, void *opaque_arg)
5647 {
5648         struct bnxt *bp = opaque_arg;
5649         unsigned long flow_xstat;
5650         char *end = NULL;
5651
5652         if (!value || !opaque_arg) {
5653                 PMD_DRV_LOG(ERR,
5654                             "Invalid parameter passed to flow_xstat devarg.\n");
5655                 return -EINVAL;
5656         }
5657
5658         flow_xstat = strtoul(value, &end, 10);
5659         if (end == NULL || *end != '\0' ||
5660             (flow_xstat == ULONG_MAX && errno == ERANGE)) {
5661                 PMD_DRV_LOG(ERR,
5662                             "Invalid parameter passed to flow_xstat devarg.\n");
5663                 return -EINVAL;
5664         }
5665
5666         if (BNXT_DEVARG_FLOW_XSTAT_INVALID(flow_xstat)) {
5667                 PMD_DRV_LOG(ERR,
5668                             "Invalid value passed to flow_xstat devarg.\n");
5669                 return -EINVAL;
5670         }
5671
5672         bp->flags |= BNXT_FLAG_FLOW_XSTATS_EN;
5673         if (BNXT_FLOW_XSTATS_EN(bp))
5674                 PMD_DRV_LOG(INFO, "flow_xstat feature enabled.\n");
5675
5676         return 0;
5677 }
5678
5679 static int
5680 bnxt_parse_devarg_max_num_kflows(__rte_unused const char *key,
5681                                         const char *value, void *opaque_arg)
5682 {
5683         struct bnxt *bp = opaque_arg;
5684         unsigned long max_num_kflows;
5685         char *end = NULL;
5686
5687         if (!value || !opaque_arg) {
5688                 PMD_DRV_LOG(ERR,
5689                         "Invalid parameter passed to max_num_kflows devarg.\n");
5690                 return -EINVAL;
5691         }
5692
5693         max_num_kflows = strtoul(value, &end, 10);
5694         if (end == NULL || *end != '\0' ||
5695                 (max_num_kflows == ULONG_MAX && errno == ERANGE)) {
5696                 PMD_DRV_LOG(ERR,
5697                         "Invalid parameter passed to max_num_kflows devarg.\n");
5698                 return -EINVAL;
5699         }
5700
5701         if (bnxt_devarg_max_num_kflow_invalid(max_num_kflows)) {
5702                 PMD_DRV_LOG(ERR,
5703                         "Invalid value passed to max_num_kflows devarg.\n");
5704                 return -EINVAL;
5705         }
5706
5707         bp->max_num_kflows = max_num_kflows;
5708         if (bp->max_num_kflows)
5709                 PMD_DRV_LOG(INFO, "max_num_kflows set as %ldK.\n",
5710                                 max_num_kflows);
5711
5712         return 0;
5713 }
5714
5715 static int
5716 bnxt_parse_devarg_rep_is_pf(__rte_unused const char *key,
5717                             const char *value, void *opaque_arg)
5718 {
5719         struct bnxt_representor *vfr_bp = opaque_arg;
5720         unsigned long rep_is_pf;
5721         char *end = NULL;
5722
5723         if (!value || !opaque_arg) {
5724                 PMD_DRV_LOG(ERR,
5725                             "Invalid parameter passed to rep_is_pf devargs.\n");
5726                 return -EINVAL;
5727         }
5728
5729         rep_is_pf = strtoul(value, &end, 10);
5730         if (end == NULL || *end != '\0' ||
5731             (rep_is_pf == ULONG_MAX && errno == ERANGE)) {
5732                 PMD_DRV_LOG(ERR,
5733                             "Invalid parameter passed to rep_is_pf devargs.\n");
5734                 return -EINVAL;
5735         }
5736
5737         if (BNXT_DEVARG_REP_IS_PF_INVALID(rep_is_pf)) {
5738                 PMD_DRV_LOG(ERR,
5739                             "Invalid value passed to rep_is_pf devargs.\n");
5740                 return -EINVAL;
5741         }
5742
5743         vfr_bp->flags |= rep_is_pf;
5744         if (BNXT_REP_PF(vfr_bp))
5745                 PMD_DRV_LOG(INFO, "PF representor\n");
5746         else
5747                 PMD_DRV_LOG(INFO, "VF representor\n");
5748
5749         return 0;
5750 }
5751
5752 static int
5753 bnxt_parse_devarg_rep_based_pf(__rte_unused const char *key,
5754                                const char *value, void *opaque_arg)
5755 {
5756         struct bnxt_representor *vfr_bp = opaque_arg;
5757         unsigned long rep_based_pf;
5758         char *end = NULL;
5759
5760         if (!value || !opaque_arg) {
5761                 PMD_DRV_LOG(ERR,
5762                             "Invalid parameter passed to rep_based_pf "
5763                             "devargs.\n");
5764                 return -EINVAL;
5765         }
5766
5767         rep_based_pf = strtoul(value, &end, 10);
5768         if (end == NULL || *end != '\0' ||
5769             (rep_based_pf == ULONG_MAX && errno == ERANGE)) {
5770                 PMD_DRV_LOG(ERR,
5771                             "Invalid parameter passed to rep_based_pf "
5772                             "devargs.\n");
5773                 return -EINVAL;
5774         }
5775
5776         if (BNXT_DEVARG_REP_BASED_PF_INVALID(rep_based_pf)) {
5777                 PMD_DRV_LOG(ERR,
5778                             "Invalid value passed to rep_based_pf devargs.\n");
5779                 return -EINVAL;
5780         }
5781
5782         vfr_bp->rep_based_pf = rep_based_pf;
5783         PMD_DRV_LOG(INFO, "rep-based-pf = %d\n", vfr_bp->rep_based_pf);
5784
5785         return 0;
5786 }
5787
5788 static int
5789 bnxt_parse_devarg_rep_q_r2f(__rte_unused const char *key,
5790                             const char *value, void *opaque_arg)
5791 {
5792         struct bnxt_representor *vfr_bp = opaque_arg;
5793         unsigned long rep_q_r2f;
5794         char *end = NULL;
5795
5796         if (!value || !opaque_arg) {
5797                 PMD_DRV_LOG(ERR,
5798                             "Invalid parameter passed to rep_q_r2f "
5799                             "devargs.\n");
5800                 return -EINVAL;
5801         }
5802
5803         rep_q_r2f = strtoul(value, &end, 10);
5804         if (end == NULL || *end != '\0' ||
5805             (rep_q_r2f == ULONG_MAX && errno == ERANGE)) {
5806                 PMD_DRV_LOG(ERR,
5807                             "Invalid parameter passed to rep_q_r2f "
5808                             "devargs.\n");
5809                 return -EINVAL;
5810         }
5811
5812         if (BNXT_DEVARG_REP_Q_R2F_INVALID(rep_q_r2f)) {
5813                 PMD_DRV_LOG(ERR,
5814                             "Invalid value passed to rep_q_r2f devargs.\n");
5815                 return -EINVAL;
5816         }
5817
5818         vfr_bp->rep_q_r2f = rep_q_r2f;
5819         vfr_bp->flags |= BNXT_REP_Q_R2F_VALID;
5820         PMD_DRV_LOG(INFO, "rep-q-r2f = %d\n", vfr_bp->rep_q_r2f);
5821
5822         return 0;
5823 }
5824
5825 static int
5826 bnxt_parse_devarg_rep_q_f2r(__rte_unused const char *key,
5827                             const char *value, void *opaque_arg)
5828 {
5829         struct bnxt_representor *vfr_bp = opaque_arg;
5830         unsigned long rep_q_f2r;
5831         char *end = NULL;
5832
5833         if (!value || !opaque_arg) {
5834                 PMD_DRV_LOG(ERR,
5835                             "Invalid parameter passed to rep_q_f2r "
5836                             "devargs.\n");
5837                 return -EINVAL;
5838         }
5839
5840         rep_q_f2r = strtoul(value, &end, 10);
5841         if (end == NULL || *end != '\0' ||
5842             (rep_q_f2r == ULONG_MAX && errno == ERANGE)) {
5843                 PMD_DRV_LOG(ERR,
5844                             "Invalid parameter passed to rep_q_f2r "
5845                             "devargs.\n");
5846                 return -EINVAL;
5847         }
5848
5849         if (BNXT_DEVARG_REP_Q_F2R_INVALID(rep_q_f2r)) {
5850                 PMD_DRV_LOG(ERR,
5851                             "Invalid value passed to rep_q_f2r devargs.\n");
5852                 return -EINVAL;
5853         }
5854
5855         vfr_bp->rep_q_f2r = rep_q_f2r;
5856         vfr_bp->flags |= BNXT_REP_Q_F2R_VALID;
5857         PMD_DRV_LOG(INFO, "rep-q-f2r = %d\n", vfr_bp->rep_q_f2r);
5858
5859         return 0;
5860 }
5861
5862 static int
5863 bnxt_parse_devarg_rep_fc_r2f(__rte_unused const char *key,
5864                              const char *value, void *opaque_arg)
5865 {
5866         struct bnxt_representor *vfr_bp = opaque_arg;
5867         unsigned long rep_fc_r2f;
5868         char *end = NULL;
5869
5870         if (!value || !opaque_arg) {
5871                 PMD_DRV_LOG(ERR,
5872                             "Invalid parameter passed to rep_fc_r2f "
5873                             "devargs.\n");
5874                 return -EINVAL;
5875         }
5876
5877         rep_fc_r2f = strtoul(value, &end, 10);
5878         if (end == NULL || *end != '\0' ||
5879             (rep_fc_r2f == ULONG_MAX && errno == ERANGE)) {
5880                 PMD_DRV_LOG(ERR,
5881                             "Invalid parameter passed to rep_fc_r2f "
5882                             "devargs.\n");
5883                 return -EINVAL;
5884         }
5885
5886         if (BNXT_DEVARG_REP_FC_R2F_INVALID(rep_fc_r2f)) {
5887                 PMD_DRV_LOG(ERR,
5888                             "Invalid value passed to rep_fc_r2f devargs.\n");
5889                 return -EINVAL;
5890         }
5891
5892         vfr_bp->flags |= BNXT_REP_FC_R2F_VALID;
5893         vfr_bp->rep_fc_r2f = rep_fc_r2f;
5894         PMD_DRV_LOG(INFO, "rep-fc-r2f = %lu\n", rep_fc_r2f);
5895
5896         return 0;
5897 }
5898
5899 static int
5900 bnxt_parse_devarg_rep_fc_f2r(__rte_unused const char *key,
5901                              const char *value, void *opaque_arg)
5902 {
5903         struct bnxt_representor *vfr_bp = opaque_arg;
5904         unsigned long rep_fc_f2r;
5905         char *end = NULL;
5906
5907         if (!value || !opaque_arg) {
5908                 PMD_DRV_LOG(ERR,
5909                             "Invalid parameter passed to rep_fc_f2r "
5910                             "devargs.\n");
5911                 return -EINVAL;
5912         }
5913
5914         rep_fc_f2r = strtoul(value, &end, 10);
5915         if (end == NULL || *end != '\0' ||
5916             (rep_fc_f2r == ULONG_MAX && errno == ERANGE)) {
5917                 PMD_DRV_LOG(ERR,
5918                             "Invalid parameter passed to rep_fc_f2r "
5919                             "devargs.\n");
5920                 return -EINVAL;
5921         }
5922
5923         if (BNXT_DEVARG_REP_FC_F2R_INVALID(rep_fc_f2r)) {
5924                 PMD_DRV_LOG(ERR,
5925                             "Invalid value passed to rep_fc_f2r devargs.\n");
5926                 return -EINVAL;
5927         }
5928
5929         vfr_bp->flags |= BNXT_REP_FC_F2R_VALID;
5930         vfr_bp->rep_fc_f2r = rep_fc_f2r;
5931         PMD_DRV_LOG(INFO, "rep-fc-f2r = %lu\n", rep_fc_f2r);
5932
5933         return 0;
5934 }
5935
5936 static void
5937 bnxt_parse_dev_args(struct bnxt *bp, struct rte_devargs *devargs)
5938 {
5939         struct rte_kvargs *kvlist;
5940
5941         if (devargs == NULL)
5942                 return;
5943
5944         kvlist = rte_kvargs_parse(devargs->args, bnxt_dev_args);
5945         if (kvlist == NULL)
5946                 return;
5947
5948         /*
5949          * Handler for "truflow" devarg.
5950          * Invoked as for ex: "-w 0000:00:0d.0,host-based-truflow=1"
5951          */
5952         rte_kvargs_process(kvlist, BNXT_DEVARG_TRUFLOW,
5953                            bnxt_parse_devarg_truflow, bp);
5954
5955         /*
5956          * Handler for "flow_xstat" devarg.
5957          * Invoked as for ex: "-w 0000:00:0d.0,flow_xstat=1"
5958          */
5959         rte_kvargs_process(kvlist, BNXT_DEVARG_FLOW_XSTAT,
5960                            bnxt_parse_devarg_flow_xstat, bp);
5961
5962         /*
5963          * Handler for "max_num_kflows" devarg.
5964          * Invoked as for ex: "-w 000:00:0d.0,max_num_kflows=32"
5965          */
5966         rte_kvargs_process(kvlist, BNXT_DEVARG_MAX_NUM_KFLOWS,
5967                            bnxt_parse_devarg_max_num_kflows, bp);
5968
5969         rte_kvargs_free(kvlist);
5970 }
5971
5972 static int bnxt_alloc_switch_domain(struct bnxt *bp)
5973 {
5974         int rc = 0;
5975
5976         if (BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp)) {
5977                 rc = rte_eth_switch_domain_alloc(&bp->switch_domain_id);
5978                 if (rc)
5979                         PMD_DRV_LOG(ERR,
5980                                     "Failed to alloc switch domain: %d\n", rc);
5981                 else
5982                         PMD_DRV_LOG(INFO,
5983                                     "Switch domain allocated %d\n",
5984                                     bp->switch_domain_id);
5985         }
5986
5987         return rc;
5988 }
5989
5990 static int
5991 bnxt_dev_init(struct rte_eth_dev *eth_dev, void *params __rte_unused)
5992 {
5993         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
5994         static int version_printed;
5995         struct bnxt *bp;
5996         int rc;
5997
5998         if (version_printed++ == 0)
5999                 PMD_DRV_LOG(INFO, "%s\n", bnxt_version);
6000
6001         eth_dev->dev_ops = &bnxt_dev_ops;
6002         eth_dev->rx_queue_count = bnxt_rx_queue_count_op;
6003         eth_dev->rx_descriptor_status = bnxt_rx_descriptor_status_op;
6004         eth_dev->tx_descriptor_status = bnxt_tx_descriptor_status_op;
6005         eth_dev->rx_pkt_burst = &bnxt_recv_pkts;
6006         eth_dev->tx_pkt_burst = &bnxt_xmit_pkts;
6007
6008         /*
6009          * For secondary processes, we don't initialise any further
6010          * as primary has already done this work.
6011          */
6012         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
6013                 return 0;
6014
6015         rte_eth_copy_pci_info(eth_dev, pci_dev);
6016
6017         bp = eth_dev->data->dev_private;
6018
6019         /* Parse dev arguments passed on when starting the DPDK application. */
6020         bnxt_parse_dev_args(bp, pci_dev->device.devargs);
6021
6022         bp->flags &= ~BNXT_FLAG_RX_VECTOR_PKT_MODE;
6023
6024         if (bnxt_vf_pciid(pci_dev->id.device_id))
6025                 bp->flags |= BNXT_FLAG_VF;
6026
6027         if (bnxt_thor_device(pci_dev->id.device_id))
6028                 bp->flags |= BNXT_FLAG_THOR_CHIP;
6029
6030         if (pci_dev->id.device_id == BROADCOM_DEV_ID_58802 ||
6031             pci_dev->id.device_id == BROADCOM_DEV_ID_58804 ||
6032             pci_dev->id.device_id == BROADCOM_DEV_ID_58808 ||
6033             pci_dev->id.device_id == BROADCOM_DEV_ID_58802_VF)
6034                 bp->flags |= BNXT_FLAG_STINGRAY;
6035
6036         rc = bnxt_init_board(eth_dev);
6037         if (rc) {
6038                 PMD_DRV_LOG(ERR,
6039                             "Failed to initialize board rc: %x\n", rc);
6040                 return rc;
6041         }
6042
6043         rc = bnxt_alloc_pf_info(bp);
6044         if (rc)
6045                 goto error_free;
6046
6047         rc = bnxt_alloc_link_info(bp);
6048         if (rc)
6049                 goto error_free;
6050
6051         rc = bnxt_alloc_parent_info(bp);
6052         if (rc)
6053                 goto error_free;
6054
6055         rc = bnxt_alloc_hwrm_resources(bp);
6056         if (rc) {
6057                 PMD_DRV_LOG(ERR,
6058                             "Failed to allocate hwrm resource rc: %x\n", rc);
6059                 goto error_free;
6060         }
6061         rc = bnxt_alloc_leds_info(bp);
6062         if (rc)
6063                 goto error_free;
6064
6065         rc = bnxt_alloc_cos_queues(bp);
6066         if (rc)
6067                 goto error_free;
6068
6069         rc = bnxt_init_resources(bp, false);
6070         if (rc)
6071                 goto error_free;
6072
6073         rc = bnxt_alloc_stats_mem(bp);
6074         if (rc)
6075                 goto error_free;
6076
6077         bnxt_alloc_switch_domain(bp);
6078
6079         /* Pass the information to the rte_eth_dev_close() that it should also
6080          * release the private port resources.
6081          */
6082         eth_dev->data->dev_flags |= RTE_ETH_DEV_CLOSE_REMOVE;
6083
6084         PMD_DRV_LOG(INFO,
6085                     DRV_MODULE_NAME "found at mem %" PRIX64 ", node addr %pM\n",
6086                     pci_dev->mem_resource[0].phys_addr,
6087                     pci_dev->mem_resource[0].addr);
6088
6089         return 0;
6090
6091 error_free:
6092         bnxt_dev_uninit(eth_dev);
6093         return rc;
6094 }
6095
6096
6097 static void bnxt_free_ctx_mem_buf(struct bnxt_ctx_mem_buf_info *ctx)
6098 {
6099         if (!ctx)
6100                 return;
6101
6102         if (ctx->va)
6103                 rte_free(ctx->va);
6104
6105         ctx->va = NULL;
6106         ctx->dma = RTE_BAD_IOVA;
6107         ctx->ctx_id = BNXT_CTX_VAL_INVAL;
6108 }
6109
6110 static void bnxt_unregister_fc_ctx_mem(struct bnxt *bp)
6111 {
6112         bnxt_hwrm_cfa_counter_cfg(bp, BNXT_DIR_RX,
6113                                   CFA_COUNTER_CFG_IN_COUNTER_TYPE_FC,
6114                                   bp->flow_stat->rx_fc_out_tbl.ctx_id,
6115                                   bp->flow_stat->max_fc,
6116                                   false);
6117
6118         bnxt_hwrm_cfa_counter_cfg(bp, BNXT_DIR_TX,
6119                                   CFA_COUNTER_CFG_IN_COUNTER_TYPE_FC,
6120                                   bp->flow_stat->tx_fc_out_tbl.ctx_id,
6121                                   bp->flow_stat->max_fc,
6122                                   false);
6123
6124         if (bp->flow_stat->rx_fc_in_tbl.ctx_id != BNXT_CTX_VAL_INVAL)
6125                 bnxt_hwrm_ctx_unrgtr(bp, bp->flow_stat->rx_fc_in_tbl.ctx_id);
6126         bp->flow_stat->rx_fc_in_tbl.ctx_id = BNXT_CTX_VAL_INVAL;
6127
6128         if (bp->flow_stat->rx_fc_out_tbl.ctx_id != BNXT_CTX_VAL_INVAL)
6129                 bnxt_hwrm_ctx_unrgtr(bp, bp->flow_stat->rx_fc_out_tbl.ctx_id);
6130         bp->flow_stat->rx_fc_out_tbl.ctx_id = BNXT_CTX_VAL_INVAL;
6131
6132         if (bp->flow_stat->tx_fc_in_tbl.ctx_id != BNXT_CTX_VAL_INVAL)
6133                 bnxt_hwrm_ctx_unrgtr(bp, bp->flow_stat->tx_fc_in_tbl.ctx_id);
6134         bp->flow_stat->tx_fc_in_tbl.ctx_id = BNXT_CTX_VAL_INVAL;
6135
6136         if (bp->flow_stat->tx_fc_out_tbl.ctx_id != BNXT_CTX_VAL_INVAL)
6137                 bnxt_hwrm_ctx_unrgtr(bp, bp->flow_stat->tx_fc_out_tbl.ctx_id);
6138         bp->flow_stat->tx_fc_out_tbl.ctx_id = BNXT_CTX_VAL_INVAL;
6139 }
6140
6141 static void bnxt_uninit_fc_ctx_mem(struct bnxt *bp)
6142 {
6143         bnxt_unregister_fc_ctx_mem(bp);
6144
6145         bnxt_free_ctx_mem_buf(&bp->flow_stat->rx_fc_in_tbl);
6146         bnxt_free_ctx_mem_buf(&bp->flow_stat->rx_fc_out_tbl);
6147         bnxt_free_ctx_mem_buf(&bp->flow_stat->tx_fc_in_tbl);
6148         bnxt_free_ctx_mem_buf(&bp->flow_stat->tx_fc_out_tbl);
6149 }
6150
6151 static void bnxt_uninit_ctx_mem(struct bnxt *bp)
6152 {
6153         if (BNXT_FLOW_XSTATS_EN(bp))
6154                 bnxt_uninit_fc_ctx_mem(bp);
6155 }
6156
6157 static void
6158 bnxt_free_error_recovery_info(struct bnxt *bp)
6159 {
6160         rte_free(bp->recovery_info);
6161         bp->recovery_info = NULL;
6162         bp->fw_cap &= ~BNXT_FW_CAP_ERROR_RECOVERY;
6163 }
6164
6165 static void
6166 bnxt_uninit_locks(struct bnxt *bp)
6167 {
6168         pthread_mutex_destroy(&bp->flow_lock);
6169         pthread_mutex_destroy(&bp->def_cp_lock);
6170         pthread_mutex_destroy(&bp->health_check_lock);
6171         if (bp->rep_info) {
6172                 pthread_mutex_destroy(&bp->rep_info->vfr_lock);
6173                 pthread_mutex_destroy(&bp->rep_info->vfr_start_lock);
6174         }
6175 }
6176
6177 static int
6178 bnxt_uninit_resources(struct bnxt *bp, bool reconfig_dev)
6179 {
6180         int rc;
6181
6182         bnxt_free_int(bp);
6183         bnxt_free_mem(bp, reconfig_dev);
6184         bnxt_hwrm_func_buf_unrgtr(bp);
6185         rc = bnxt_hwrm_func_driver_unregister(bp, 0);
6186         bp->flags &= ~BNXT_FLAG_REGISTERED;
6187         bnxt_free_ctx_mem(bp);
6188         if (!reconfig_dev) {
6189                 bnxt_free_hwrm_resources(bp);
6190                 bnxt_free_error_recovery_info(bp);
6191         }
6192
6193         bnxt_uninit_ctx_mem(bp);
6194
6195         bnxt_uninit_locks(bp);
6196         bnxt_free_flow_stats_info(bp);
6197         bnxt_free_rep_info(bp);
6198         rte_free(bp->ptp_cfg);
6199         bp->ptp_cfg = NULL;
6200         return rc;
6201 }
6202
6203 static int
6204 bnxt_dev_uninit(struct rte_eth_dev *eth_dev)
6205 {
6206         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
6207                 return -EPERM;
6208
6209         PMD_DRV_LOG(DEBUG, "Calling Device uninit\n");
6210
6211         if (eth_dev->state != RTE_ETH_DEV_UNUSED)
6212                 bnxt_dev_close_op(eth_dev);
6213
6214         return 0;
6215 }
6216
6217 static int bnxt_pci_remove_dev_with_reps(struct rte_eth_dev *eth_dev)
6218 {
6219         struct bnxt *bp = eth_dev->data->dev_private;
6220         struct rte_eth_dev *vf_rep_eth_dev;
6221         int ret = 0, i;
6222
6223         if (!bp)
6224                 return -EINVAL;
6225
6226         for (i = 0; i < bp->num_reps; i++) {
6227                 vf_rep_eth_dev = bp->rep_info[i].vfr_eth_dev;
6228                 if (!vf_rep_eth_dev)
6229                         continue;
6230                 PMD_DRV_LOG(DEBUG, "BNXT Port:%d VFR pci remove\n",
6231                             vf_rep_eth_dev->data->port_id);
6232                 rte_eth_dev_destroy(vf_rep_eth_dev, bnxt_representor_uninit);
6233         }
6234         PMD_DRV_LOG(DEBUG, "BNXT Port:%d pci remove\n",
6235                     eth_dev->data->port_id);
6236         ret = rte_eth_dev_destroy(eth_dev, bnxt_dev_uninit);
6237
6238         return ret;
6239 }
6240
6241 static void bnxt_free_rep_info(struct bnxt *bp)
6242 {
6243         rte_free(bp->rep_info);
6244         bp->rep_info = NULL;
6245         rte_free(bp->cfa_code_map);
6246         bp->cfa_code_map = NULL;
6247 }
6248
6249 static int bnxt_init_rep_info(struct bnxt *bp)
6250 {
6251         int i = 0, rc;
6252
6253         if (bp->rep_info)
6254                 return 0;
6255
6256         bp->rep_info = rte_zmalloc("bnxt_rep_info",
6257                                    sizeof(bp->rep_info[0]) * BNXT_MAX_VF_REPS,
6258                                    0);
6259         if (!bp->rep_info) {
6260                 PMD_DRV_LOG(ERR, "Failed to alloc memory for rep info\n");
6261                 return -ENOMEM;
6262         }
6263         bp->cfa_code_map = rte_zmalloc("bnxt_cfa_code_map",
6264                                        sizeof(*bp->cfa_code_map) *
6265                                        BNXT_MAX_CFA_CODE, 0);
6266         if (!bp->cfa_code_map) {
6267                 PMD_DRV_LOG(ERR, "Failed to alloc memory for cfa_code_map\n");
6268                 bnxt_free_rep_info(bp);
6269                 return -ENOMEM;
6270         }
6271
6272         for (i = 0; i < BNXT_MAX_CFA_CODE; i++)
6273                 bp->cfa_code_map[i] = BNXT_VF_IDX_INVALID;
6274
6275         rc = pthread_mutex_init(&bp->rep_info->vfr_lock, NULL);
6276         if (rc) {
6277                 PMD_DRV_LOG(ERR, "Unable to initialize vfr_lock\n");
6278                 bnxt_free_rep_info(bp);
6279                 return rc;
6280         }
6281
6282         rc = pthread_mutex_init(&bp->rep_info->vfr_start_lock, NULL);
6283         if (rc) {
6284                 PMD_DRV_LOG(ERR, "Unable to initialize vfr_start_lock\n");
6285                 bnxt_free_rep_info(bp);
6286                 return rc;
6287         }
6288
6289         return rc;
6290 }
6291
6292 static int bnxt_rep_port_probe(struct rte_pci_device *pci_dev,
6293                                struct rte_eth_devargs eth_da,
6294                                struct rte_eth_dev *backing_eth_dev,
6295                                const char *dev_args)
6296 {
6297         struct rte_eth_dev *vf_rep_eth_dev;
6298         char name[RTE_ETH_NAME_MAX_LEN];
6299         struct bnxt *backing_bp;
6300         uint16_t num_rep;
6301         int i, ret = 0;
6302         struct rte_kvargs *kvlist;
6303
6304         num_rep = eth_da.nb_representor_ports;
6305         if (num_rep > BNXT_MAX_VF_REPS) {
6306                 PMD_DRV_LOG(ERR, "nb_representor_ports = %d > %d MAX VF REPS\n",
6307                             num_rep, BNXT_MAX_VF_REPS);
6308                 return -EINVAL;
6309         }
6310
6311         if (num_rep >= RTE_MAX_ETHPORTS) {
6312                 PMD_DRV_LOG(ERR,
6313                             "nb_representor_ports = %d > %d MAX ETHPORTS\n",
6314                             num_rep, RTE_MAX_ETHPORTS);
6315                 return -EINVAL;
6316         }
6317
6318         backing_bp = backing_eth_dev->data->dev_private;
6319
6320         if (!(BNXT_PF(backing_bp) || BNXT_VF_IS_TRUSTED(backing_bp))) {
6321                 PMD_DRV_LOG(ERR,
6322                             "Not a PF or trusted VF. No Representor support\n");
6323                 /* Returning an error is not an option.
6324                  * Applications are not handling this correctly
6325                  */
6326                 return 0;
6327         }
6328
6329         if (bnxt_init_rep_info(backing_bp))
6330                 return 0;
6331
6332         for (i = 0; i < num_rep; i++) {
6333                 struct bnxt_representor representor = {
6334                         .vf_id = eth_da.representor_ports[i],
6335                         .switch_domain_id = backing_bp->switch_domain_id,
6336                         .parent_dev = backing_eth_dev
6337                 };
6338
6339                 if (representor.vf_id >= BNXT_MAX_VF_REPS) {
6340                         PMD_DRV_LOG(ERR, "VF-Rep id %d >= %d MAX VF ID\n",
6341                                     representor.vf_id, BNXT_MAX_VF_REPS);
6342                         continue;
6343                 }
6344
6345                 /* representor port net_bdf_port */
6346                 snprintf(name, sizeof(name), "net_%s_representor_%d",
6347                          pci_dev->device.name, eth_da.representor_ports[i]);
6348
6349                 kvlist = rte_kvargs_parse(dev_args, bnxt_dev_args);
6350                 if (kvlist) {
6351                         /*
6352                          * Handler for "rep_is_pf" devarg.
6353                          * Invoked as for ex: "-w 000:00:0d.0,
6354                          * rep-based-pf=<pf index> rep-is-pf=<VF=0 or PF=1>"
6355                          */
6356                         rte_kvargs_process(kvlist, BNXT_DEVARG_REP_IS_PF,
6357                                            bnxt_parse_devarg_rep_is_pf,
6358                                            (void *)&representor);
6359                         /*
6360                          * Handler for "rep_based_pf" devarg.
6361                          * Invoked as for ex: "-w 000:00:0d.0,
6362                          * rep-based-pf=<pf index> rep-is-pf=<VF=0 or PF=1>"
6363                          */
6364                         rte_kvargs_process(kvlist, BNXT_DEVARG_REP_BASED_PF,
6365                                            bnxt_parse_devarg_rep_based_pf,
6366                                            (void *)&representor);
6367                         /*
6368                          * Handler for "rep_based_pf" devarg.
6369                          * Invoked as for ex: "-w 000:00:0d.0,
6370                          * rep-based-pf=<pf index> rep-is-pf=<VF=0 or PF=1>"
6371                          */
6372                         rte_kvargs_process(kvlist, BNXT_DEVARG_REP_Q_R2F,
6373                                            bnxt_parse_devarg_rep_q_r2f,
6374                                            (void *)&representor);
6375                         /*
6376                          * Handler for "rep_based_pf" devarg.
6377                          * Invoked as for ex: "-w 000:00:0d.0,
6378                          * rep-based-pf=<pf index> rep-is-pf=<VF=0 or PF=1>"
6379                          */
6380                         rte_kvargs_process(kvlist, BNXT_DEVARG_REP_Q_F2R,
6381                                            bnxt_parse_devarg_rep_q_f2r,
6382                                            (void *)&representor);
6383                         /*
6384                          * Handler for "rep_based_pf" devarg.
6385                          * Invoked as for ex: "-w 000:00:0d.0,
6386                          * rep-based-pf=<pf index> rep-is-pf=<VF=0 or PF=1>"
6387                          */
6388                         rte_kvargs_process(kvlist, BNXT_DEVARG_REP_FC_R2F,
6389                                            bnxt_parse_devarg_rep_fc_r2f,
6390                                            (void *)&representor);
6391                         /*
6392                          * Handler for "rep_based_pf" devarg.
6393                          * Invoked as for ex: "-w 000:00:0d.0,
6394                          * rep-based-pf=<pf index> rep-is-pf=<VF=0 or PF=1>"
6395                          */
6396                         rte_kvargs_process(kvlist, BNXT_DEVARG_REP_FC_F2R,
6397                                            bnxt_parse_devarg_rep_fc_f2r,
6398                                            (void *)&representor);
6399                 }
6400
6401                 ret = rte_eth_dev_create(&pci_dev->device, name,
6402                                          sizeof(struct bnxt_representor),
6403                                          NULL, NULL,
6404                                          bnxt_representor_init,
6405                                          &representor);
6406                 if (ret) {
6407                         PMD_DRV_LOG(ERR, "failed to create bnxt vf "
6408                                     "representor %s.", name);
6409                         goto err;
6410                 }
6411
6412                 vf_rep_eth_dev = rte_eth_dev_allocated(name);
6413                 if (!vf_rep_eth_dev) {
6414                         PMD_DRV_LOG(ERR, "Failed to find the eth_dev"
6415                                     " for VF-Rep: %s.", name);
6416                         ret = -ENODEV;
6417                         goto err;
6418                 }
6419
6420                 PMD_DRV_LOG(DEBUG, "BNXT Port:%d VFR pci probe\n",
6421                             backing_eth_dev->data->port_id);
6422                 backing_bp->rep_info[representor.vf_id].vfr_eth_dev =
6423                                                          vf_rep_eth_dev;
6424                 backing_bp->num_reps++;
6425
6426         }
6427
6428         return 0;
6429
6430 err:
6431         /* If num_rep > 1, then rollback already created
6432          * ports, since we'll be failing the probe anyway
6433          */
6434         if (num_rep > 1)
6435                 bnxt_pci_remove_dev_with_reps(backing_eth_dev);
6436
6437         return ret;
6438 }
6439
6440 static int bnxt_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
6441                           struct rte_pci_device *pci_dev)
6442 {
6443         struct rte_eth_devargs eth_da = { .nb_representor_ports = 0 };
6444         struct rte_eth_dev *backing_eth_dev;
6445         uint16_t num_rep;
6446         int ret = 0;
6447
6448         if (pci_dev->device.devargs) {
6449                 ret = rte_eth_devargs_parse(pci_dev->device.devargs->args,
6450                                             &eth_da);
6451                 if (ret)
6452                         return ret;
6453         }
6454
6455         num_rep = eth_da.nb_representor_ports;
6456         PMD_DRV_LOG(DEBUG, "nb_representor_ports = %d\n",
6457                     num_rep);
6458
6459         /* We could come here after first level of probe is already invoked
6460          * as part of an application bringup(OVS-DPDK vswitchd), so first check
6461          * for already allocated eth_dev for the backing device (PF/Trusted VF)
6462          */
6463         backing_eth_dev = rte_eth_dev_allocated(pci_dev->device.name);
6464         if (backing_eth_dev == NULL) {
6465                 ret = rte_eth_dev_create(&pci_dev->device, pci_dev->device.name,
6466                                          sizeof(struct bnxt),
6467                                          eth_dev_pci_specific_init, pci_dev,
6468                                          bnxt_dev_init, NULL);
6469
6470                 if (ret || !num_rep)
6471                         return ret;
6472
6473                 backing_eth_dev = rte_eth_dev_allocated(pci_dev->device.name);
6474         }
6475         PMD_DRV_LOG(DEBUG, "BNXT Port:%d pci probe\n",
6476                     backing_eth_dev->data->port_id);
6477
6478         if (!num_rep)
6479                 return ret;
6480
6481         /* probe representor ports now */
6482         ret = bnxt_rep_port_probe(pci_dev, eth_da, backing_eth_dev,
6483                                   pci_dev->device.devargs->args);
6484
6485         return ret;
6486 }
6487
6488 static int bnxt_pci_remove(struct rte_pci_device *pci_dev)
6489 {
6490         struct rte_eth_dev *eth_dev;
6491
6492         eth_dev = rte_eth_dev_allocated(pci_dev->device.name);
6493         if (!eth_dev)
6494                 return 0; /* Invoked typically only by OVS-DPDK, by the
6495                            * time it comes here the eth_dev is already
6496                            * deleted by rte_eth_dev_close(), so returning
6497                            * +ve value will at least help in proper cleanup
6498                            */
6499
6500         PMD_DRV_LOG(DEBUG, "BNXT Port:%d pci remove\n", eth_dev->data->port_id);
6501         if (rte_eal_process_type() == RTE_PROC_PRIMARY) {
6502                 if (eth_dev->data->dev_flags & RTE_ETH_DEV_REPRESENTOR)
6503                         return rte_eth_dev_destroy(eth_dev,
6504                                                    bnxt_representor_uninit);
6505                 else
6506                         return rte_eth_dev_destroy(eth_dev,
6507                                                    bnxt_dev_uninit);
6508         } else {
6509                 return rte_eth_dev_pci_generic_remove(pci_dev, NULL);
6510         }
6511 }
6512
6513 static struct rte_pci_driver bnxt_rte_pmd = {
6514         .id_table = bnxt_pci_id_map,
6515         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC |
6516                         RTE_PCI_DRV_PROBE_AGAIN, /* Needed in case of VF-REPs
6517                                                   * and OVS-DPDK
6518                                                   */
6519         .probe = bnxt_pci_probe,
6520         .remove = bnxt_pci_remove,
6521 };
6522
6523 static bool
6524 is_device_supported(struct rte_eth_dev *dev, struct rte_pci_driver *drv)
6525 {
6526         if (strcmp(dev->device->driver->name, drv->driver.name))
6527                 return false;
6528
6529         return true;
6530 }
6531
6532 bool is_bnxt_supported(struct rte_eth_dev *dev)
6533 {
6534         return is_device_supported(dev, &bnxt_rte_pmd);
6535 }
6536
6537 RTE_LOG_REGISTER(bnxt_logtype_driver, pmd.net.bnxt.driver, NOTICE);
6538 RTE_PMD_REGISTER_PCI(net_bnxt, bnxt_rte_pmd);
6539 RTE_PMD_REGISTER_PCI_TABLE(net_bnxt, bnxt_pci_id_map);
6540 RTE_PMD_REGISTER_KMOD_DEP(net_bnxt, "* igb_uio | uio_pci_generic | vfio-pci");