drivers/net/bnxt/bnxt_ethdev.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2014-2018 Broadcom
   3  * All rights reserved.
   4  */
   5
   6 #include <inttypes.h>
   7 #include <stdbool.h>
   8
   9 #include <rte_dev.h>
  10 #include <rte_ethdev_driver.h>
  11 #include <rte_ethdev_pci.h>
  12 #include <rte_malloc.h>
  13 #include <rte_cycles.h>
  14 #include <rte_alarm.h>
  15 #include <rte_kvargs.h>
  16 #include <rte_vect.h>
  17
  18 #include "bnxt.h"
  19 #include "bnxt_filter.h"
  20 #include "bnxt_hwrm.h"
  21 #include "bnxt_irq.h"
  22 #include "bnxt_reps.h"
  23 #include "bnxt_ring.h"
  24 #include "bnxt_rxq.h"
  25 #include "bnxt_rxr.h"
  26 #include "bnxt_stats.h"
  27 #include "bnxt_txq.h"
  28 #include "bnxt_txr.h"
  29 #include "bnxt_vnic.h"
  30 #include "hsi_struct_def_dpdk.h"
  31 #include "bnxt_nvm_defs.h"
  32 #include "bnxt_tf_common.h"
  33 #include "ulp_flow_db.h"
  34 #include "rte_pmd_bnxt.h"
  35
  36 #define DRV_MODULE_NAME         "bnxt"
  37 static const char bnxt_version[] =
  38         "Broadcom NetXtreme driver " DRV_MODULE_NAME;
  39
  40 /*
  41  * The set of PCI devices this driver supports
  42  */
  43 static const struct rte_pci_id bnxt_pci_id_map[] = {
  44         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM,
  45                          BROADCOM_DEV_ID_STRATUS_NIC_VF1) },
  46         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM,
  47                          BROADCOM_DEV_ID_STRATUS_NIC_VF2) },
  48         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_STRATUS_NIC) },
  49         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414_VF) },
  50         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57301) },
  51         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57302) },
  52         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57304_PF) },
  53         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57304_VF) },
  54         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_NS2) },
  55         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57402) },
  56         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57404) },
  57         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57406_PF) },
  58         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57406_VF) },
  59         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57402_MF) },
  60         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57407_RJ45) },
  61         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57404_MF) },
  62         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57406_MF) },
  63         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57407_SFP) },
  64         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57407_MF) },
  65         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_5741X_VF) },
  66         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_5731X_VF) },
  67         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57314) },
  68         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_MF) },
  69         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57311) },
  70         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57312) },
  71         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57412) },
  72         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414) },
  73         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_RJ45) },
  74         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_RJ45) },
  75         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57412_MF) },
  76         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57317_RJ45) },
  77         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_SFP) },
  78         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_SFP) },
  79         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57317_SFP) },
  80         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414_MF) },
  81         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_MF) },
  82         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58802) },
  83         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58804) },
  84         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58808) },
  85         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58802_VF) },
  86         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57508) },
  87         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57504) },
  88         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57502) },
  89         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57500_VF1) },
  90         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57500_VF2) },
  91         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57508_MF1) },
  92         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57504_MF1) },
  93         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57502_MF1) },
  94         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57508_MF2) },
  95         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57504_MF2) },
  96         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57502_MF2) },
  97         { .vendor_id = 0, /* sentinel */ },
  98 };
  99
 100 #define BNXT_DEVARG_TRUFLOW     "host-based-truflow"
 101 #define BNXT_DEVARG_FLOW_XSTAT  "flow-xstat"
 102 #define BNXT_DEVARG_MAX_NUM_KFLOWS  "max-num-kflows"
 103 #define BNXT_DEVARG_REPRESENTOR "representor"
 104 #define BNXT_DEVARG_REP_BASED_PF  "rep-based-pf"
 105 #define BNXT_DEVARG_REP_IS_PF  "rep-is-pf"
 106 #define BNXT_DEVARG_REP_Q_R2F  "rep-q-r2f"
 107 #define BNXT_DEVARG_REP_Q_F2R  "rep-q-f2r"
 108 #define BNXT_DEVARG_REP_FC_R2F  "rep-fc-r2f"
 109 #define BNXT_DEVARG_REP_FC_F2R  "rep-fc-f2r"
 110
 111 static const char *const bnxt_dev_args[] = {
 112         BNXT_DEVARG_REPRESENTOR,
 113         BNXT_DEVARG_TRUFLOW,
 114         BNXT_DEVARG_FLOW_XSTAT,
 115         BNXT_DEVARG_MAX_NUM_KFLOWS,
 116         BNXT_DEVARG_REP_BASED_PF,
 117         BNXT_DEVARG_REP_IS_PF,
 118         BNXT_DEVARG_REP_Q_R2F,
 119         BNXT_DEVARG_REP_Q_F2R,
 120         BNXT_DEVARG_REP_FC_R2F,
 121         BNXT_DEVARG_REP_FC_F2R,
 122         NULL
 123 };
 124
 125 /*
 126  * truflow == false to disable the feature
 127  * truflow == true to enable the feature
 128  */
 129 #define BNXT_DEVARG_TRUFLOW_INVALID(truflow)    ((truflow) > 1)
 130
 131 /*
 132  * flow_xstat == false to disable the feature
 133  * flow_xstat == true to enable the feature
 134  */
 135 #define BNXT_DEVARG_FLOW_XSTAT_INVALID(flow_xstat)      ((flow_xstat) > 1)
 136
 137 /*
 138  * rep_is_pf == false to indicate VF representor
 139  * rep_is_pf == true to indicate PF representor
 140  */
 141 #define BNXT_DEVARG_REP_IS_PF_INVALID(rep_is_pf)        ((rep_is_pf) > 1)
 142
 143 /*
 144  * rep_based_pf == Physical index of the PF
 145  */
 146 #define BNXT_DEVARG_REP_BASED_PF_INVALID(rep_based_pf)  ((rep_based_pf) > 15)
 147 /*
 148  * rep_q_r2f == Logical COS Queue index for the rep to endpoint direction
 149  */
 150 #define BNXT_DEVARG_REP_Q_R2F_INVALID(rep_q_r2f)        ((rep_q_r2f) > 3)
 151
 152 /*
 153  * rep_q_f2r == Logical COS Queue index for the endpoint to rep direction
 154  */
 155 #define BNXT_DEVARG_REP_Q_F2R_INVALID(rep_q_f2r)        ((rep_q_f2r) > 3)
 156
 157 /*
 158  * rep_fc_r2f == Flow control for the representor to endpoint direction
 159  */
 160 #define BNXT_DEVARG_REP_FC_R2F_INVALID(rep_fc_r2f)      ((rep_fc_r2f) > 1)
 161
 162 /*
 163  * rep_fc_f2r == Flow control for the endpoint to representor direction
 164  */
 165 #define BNXT_DEVARG_REP_FC_F2R_INVALID(rep_fc_f2r)      ((rep_fc_f2r) > 1)
 166
 167 int bnxt_cfa_code_dynfield_offset = -1;
 168
 169 /*
 170  * max_num_kflows must be >= 32
 171  * and must be a power-of-2 supported value
 172  * return: 1 -> invalid
 173  *         0 -> valid
 174  */
 175 static int bnxt_devarg_max_num_kflow_invalid(uint16_t max_num_kflows)
 176 {
 177         if (max_num_kflows < 32 || !rte_is_power_of_2(max_num_kflows))
 178                 return 1;
 179         return 0;
 180 }
 181
 182 static int bnxt_vlan_offload_set_op(struct rte_eth_dev *dev, int mask);
 183 static int bnxt_dev_uninit(struct rte_eth_dev *eth_dev);
 184 static int bnxt_init_resources(struct bnxt *bp, bool reconfig_dev);
 185 static int bnxt_uninit_resources(struct bnxt *bp, bool reconfig_dev);
 186 static void bnxt_cancel_fw_health_check(struct bnxt *bp);
 187 static int bnxt_restore_vlan_filters(struct bnxt *bp);
 188 static void bnxt_dev_recover(void *arg);
 189 static void bnxt_free_error_recovery_info(struct bnxt *bp);
 190 static void bnxt_free_rep_info(struct bnxt *bp);
 191
 192 int is_bnxt_in_error(struct bnxt *bp)
 193 {
 194         if (bp->flags & BNXT_FLAG_FATAL_ERROR)
 195                 return -EIO;
 196         if (bp->flags & BNXT_FLAG_FW_RESET)
 197                 return -EBUSY;
 198
 199         return 0;
 200 }
 201
 202 /***********************/
 203
 204 /*
 205  * High level utility functions
 206  */
 207
 208 static uint16_t bnxt_rss_ctxts(const struct bnxt *bp)
 209 {
 210         if (!BNXT_CHIP_THOR(bp))
 211                 return 1;
 212
 213         return RTE_ALIGN_MUL_CEIL(bp->rx_nr_rings,
 214                                   BNXT_RSS_ENTRIES_PER_CTX_THOR) /
 215                                     BNXT_RSS_ENTRIES_PER_CTX_THOR;
 216 }
 217
 218 uint16_t bnxt_rss_hash_tbl_size(const struct bnxt *bp)
 219 {
 220         if (!BNXT_CHIP_THOR(bp))
 221                 return HW_HASH_INDEX_SIZE;
 222
 223         return bnxt_rss_ctxts(bp) * BNXT_RSS_ENTRIES_PER_CTX_THOR;
 224 }
 225
 226 static void bnxt_free_parent_info(struct bnxt *bp)
 227 {
 228         rte_free(bp->parent);
 229 }
 230
 231 static void bnxt_free_pf_info(struct bnxt *bp)
 232 {
 233         rte_free(bp->pf);
 234 }
 235
 236 static void bnxt_free_link_info(struct bnxt *bp)
 237 {
 238         rte_free(bp->link_info);
 239 }
 240
 241 static void bnxt_free_leds_info(struct bnxt *bp)
 242 {
 243         if (BNXT_VF(bp))
 244                 return;
 245
 246         rte_free(bp->leds);
 247         bp->leds = NULL;
 248 }
 249
 250 static void bnxt_free_flow_stats_info(struct bnxt *bp)
 251 {
 252         rte_free(bp->flow_stat);
 253         bp->flow_stat = NULL;
 254 }
 255
 256 static void bnxt_free_cos_queues(struct bnxt *bp)
 257 {
 258         rte_free(bp->rx_cos_queue);
 259         rte_free(bp->tx_cos_queue);
 260 }
 261
 262 static void bnxt_free_mem(struct bnxt *bp, bool reconfig)
 263 {
 264         bnxt_free_filter_mem(bp);
 265         bnxt_free_vnic_attributes(bp);
 266         bnxt_free_vnic_mem(bp);
 267
 268         /* tx/rx rings are configured as part of *_queue_setup callbacks.
 269          * If the number of rings change across fw update,
 270          * we don't have much choice except to warn the user.
 271          */
 272         if (!reconfig) {
 273                 bnxt_free_stats(bp);
 274                 bnxt_free_tx_rings(bp);
 275                 bnxt_free_rx_rings(bp);
 276         }
 277         bnxt_free_async_cp_ring(bp);
 278         bnxt_free_rxtx_nq_ring(bp);
 279
 280         rte_free(bp->grp_info);
 281         bp->grp_info = NULL;
 282 }
 283
 284 static int bnxt_alloc_parent_info(struct bnxt *bp)
 285 {
 286         bp->parent = rte_zmalloc("bnxt_parent_info",
 287                                  sizeof(struct bnxt_parent_info), 0);
 288         if (bp->parent == NULL)
 289                 return -ENOMEM;
 290
 291         return 0;
 292 }
 293
 294 static int bnxt_alloc_pf_info(struct bnxt *bp)
 295 {
 296         bp->pf = rte_zmalloc("bnxt_pf_info", sizeof(struct bnxt_pf_info), 0);
 297         if (bp->pf == NULL)
 298                 return -ENOMEM;
 299
 300         return 0;
 301 }
 302
 303 static int bnxt_alloc_link_info(struct bnxt *bp)
 304 {
 305         bp->link_info =
 306                 rte_zmalloc("bnxt_link_info", sizeof(struct bnxt_link_info), 0);
 307         if (bp->link_info == NULL)
 308                 return -ENOMEM;
 309
 310         return 0;
 311 }
 312
 313 static int bnxt_alloc_leds_info(struct bnxt *bp)
 314 {
 315         if (BNXT_VF(bp))
 316                 return 0;
 317
 318         bp->leds = rte_zmalloc("bnxt_leds",
 319                                BNXT_MAX_LED * sizeof(struct bnxt_led_info),
 320                                0);
 321         if (bp->leds == NULL)
 322                 return -ENOMEM;
 323
 324         return 0;
 325 }
 326
 327 static int bnxt_alloc_cos_queues(struct bnxt *bp)
 328 {
 329         bp->rx_cos_queue =
 330                 rte_zmalloc("bnxt_rx_cosq",
 331                             BNXT_COS_QUEUE_COUNT *
 332                             sizeof(struct bnxt_cos_queue_info),
 333                             0);
 334         if (bp->rx_cos_queue == NULL)
 335                 return -ENOMEM;
 336
 337         bp->tx_cos_queue =
 338                 rte_zmalloc("bnxt_tx_cosq",
 339                             BNXT_COS_QUEUE_COUNT *
 340                             sizeof(struct bnxt_cos_queue_info),
 341                             0);
 342         if (bp->tx_cos_queue == NULL)
 343                 return -ENOMEM;
 344
 345         return 0;
 346 }
 347
 348 static int bnxt_alloc_flow_stats_info(struct bnxt *bp)
 349 {
 350         bp->flow_stat = rte_zmalloc("bnxt_flow_xstat",
 351                                     sizeof(struct bnxt_flow_stat_info), 0);
 352         if (bp->flow_stat == NULL)
 353                 return -ENOMEM;
 354
 355         return 0;
 356 }
 357
 358 static int bnxt_alloc_mem(struct bnxt *bp, bool reconfig)
 359 {
 360         int rc;
 361
 362         rc = bnxt_alloc_ring_grps(bp);
 363         if (rc)
 364                 goto alloc_mem_err;
 365
 366         rc = bnxt_alloc_async_ring_struct(bp);
 367         if (rc)
 368                 goto alloc_mem_err;
 369
 370         rc = bnxt_alloc_vnic_mem(bp);
 371         if (rc)
 372                 goto alloc_mem_err;
 373
 374         rc = bnxt_alloc_vnic_attributes(bp);
 375         if (rc)
 376                 goto alloc_mem_err;
 377
 378         rc = bnxt_alloc_filter_mem(bp);
 379         if (rc)
 380                 goto alloc_mem_err;
 381
 382         rc = bnxt_alloc_async_cp_ring(bp);
 383         if (rc)
 384                 goto alloc_mem_err;
 385
 386         rc = bnxt_alloc_rxtx_nq_ring(bp);
 387         if (rc)
 388                 goto alloc_mem_err;
 389
 390         if (BNXT_FLOW_XSTATS_EN(bp)) {
 391                 rc = bnxt_alloc_flow_stats_info(bp);
 392                 if (rc)
 393                         goto alloc_mem_err;
 394         }
 395
 396         return 0;
 397
 398 alloc_mem_err:
 399         bnxt_free_mem(bp, reconfig);
 400         return rc;
 401 }
 402
 403 static int bnxt_setup_one_vnic(struct bnxt *bp, uint16_t vnic_id)
 404 {
 405         struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
 406         struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id];
 407         uint64_t rx_offloads = dev_conf->rxmode.offloads;
 408         struct bnxt_rx_queue *rxq;
 409         unsigned int j;
 410         int rc;
 411
 412         rc = bnxt_vnic_grp_alloc(bp, vnic);
 413         if (rc)
 414                 goto err_out;
 415
 416         PMD_DRV_LOG(DEBUG, "vnic[%d] = %p vnic->fw_grp_ids = %p\n",
 417                     vnic_id, vnic, vnic->fw_grp_ids);
 418
 419         rc = bnxt_hwrm_vnic_alloc(bp, vnic);
 420         if (rc)
 421                 goto err_out;
 422
 423         /* Alloc RSS context only if RSS mode is enabled */
 424         if (dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS) {
 425                 int j, nr_ctxs = bnxt_rss_ctxts(bp);
 426
 427                 rc = 0;
 428                 for (j = 0; j < nr_ctxs; j++) {
 429                         rc = bnxt_hwrm_vnic_ctx_alloc(bp, vnic, j);
 430                         if (rc)
 431                                 break;
 432                 }
 433                 if (rc) {
 434                         PMD_DRV_LOG(ERR,
 435                                     "HWRM vnic %d ctx %d alloc failure rc: %x\n",
 436                                     vnic_id, j, rc);
 437                         goto err_out;
 438                 }
 439                 vnic->num_lb_ctxts = nr_ctxs;
 440         }
 441
 442         /*
 443          * Firmware sets pf pair in default vnic cfg. If the VLAN strip
 444          * setting is not available at this time, it will not be
 445          * configured correctly in the CFA.
 446          */
 447         if (rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
 448                 vnic->vlan_strip = true;
 449         else
 450                 vnic->vlan_strip = false;
 451
 452         rc = bnxt_hwrm_vnic_cfg(bp, vnic);
 453         if (rc)
 454                 goto err_out;
 455
 456         rc = bnxt_set_hwrm_vnic_filters(bp, vnic);
 457         if (rc)
 458                 goto err_out;
 459
 460         for (j = 0; j < bp->rx_num_qs_per_vnic; j++) {
 461                 rxq = bp->eth_dev->data->rx_queues[j];
 462
 463                 PMD_DRV_LOG(DEBUG,
 464                             "rxq[%d]->vnic=%p vnic->fw_grp_ids=%p\n",
 465                             j, rxq->vnic, rxq->vnic->fw_grp_ids);
 466
 467                 if (BNXT_HAS_RING_GRPS(bp) && rxq->rx_deferred_start)
 468                         rxq->vnic->fw_grp_ids[j] = INVALID_HW_RING_ID;
 469                 else
 470                         vnic->rx_queue_cnt++;
 471         }
 472
 473         PMD_DRV_LOG(DEBUG, "vnic->rx_queue_cnt = %d\n", vnic->rx_queue_cnt);
 474
 475         rc = bnxt_vnic_rss_configure(bp, vnic);
 476         if (rc)
 477                 goto err_out;
 478
 479         bnxt_hwrm_vnic_plcmode_cfg(bp, vnic);
 480
 481         if (rx_offloads & DEV_RX_OFFLOAD_TCP_LRO)
 482                 bnxt_hwrm_vnic_tpa_cfg(bp, vnic, 1);
 483         else
 484                 bnxt_hwrm_vnic_tpa_cfg(bp, vnic, 0);
 485
 486         return 0;
 487 err_out:
 488         PMD_DRV_LOG(ERR, "HWRM vnic %d cfg failure rc: %x\n",
 489                     vnic_id, rc);
 490         return rc;
 491 }
 492
 493 static int bnxt_register_fc_ctx_mem(struct bnxt *bp)
 494 {
 495         int rc = 0;
 496
 497         rc = bnxt_hwrm_ctx_rgtr(bp, bp->flow_stat->rx_fc_in_tbl.dma,
 498                                 &bp->flow_stat->rx_fc_in_tbl.ctx_id);
 499         if (rc)
 500                 return rc;
 501
 502         PMD_DRV_LOG(DEBUG,
 503                     "rx_fc_in_tbl.va = %p rx_fc_in_tbl.dma = %p"
 504                     " rx_fc_in_tbl.ctx_id = %d\n",
 505                     bp->flow_stat->rx_fc_in_tbl.va,
 506                     (void *)((uintptr_t)bp->flow_stat->rx_fc_in_tbl.dma),
 507                     bp->flow_stat->rx_fc_in_tbl.ctx_id);
 508
 509         rc = bnxt_hwrm_ctx_rgtr(bp, bp->flow_stat->rx_fc_out_tbl.dma,
 510                                 &bp->flow_stat->rx_fc_out_tbl.ctx_id);
 511         if (rc)
 512                 return rc;
 513
 514         PMD_DRV_LOG(DEBUG,
 515                     "rx_fc_out_tbl.va = %p rx_fc_out_tbl.dma = %p"
 516                     " rx_fc_out_tbl.ctx_id = %d\n",
 517                     bp->flow_stat->rx_fc_out_tbl.va,
 518                     (void *)((uintptr_t)bp->flow_stat->rx_fc_out_tbl.dma),
 519                     bp->flow_stat->rx_fc_out_tbl.ctx_id);
 520
 521         rc = bnxt_hwrm_ctx_rgtr(bp, bp->flow_stat->tx_fc_in_tbl.dma,
 522                                 &bp->flow_stat->tx_fc_in_tbl.ctx_id);
 523         if (rc)
 524                 return rc;
 525
 526         PMD_DRV_LOG(DEBUG,
 527                     "tx_fc_in_tbl.va = %p tx_fc_in_tbl.dma = %p"
 528                     " tx_fc_in_tbl.ctx_id = %d\n",
 529                     bp->flow_stat->tx_fc_in_tbl.va,
 530                     (void *)((uintptr_t)bp->flow_stat->tx_fc_in_tbl.dma),
 531                     bp->flow_stat->tx_fc_in_tbl.ctx_id);
 532
 533         rc = bnxt_hwrm_ctx_rgtr(bp, bp->flow_stat->tx_fc_out_tbl.dma,
 534                                 &bp->flow_stat->tx_fc_out_tbl.ctx_id);
 535         if (rc)
 536                 return rc;
 537
 538         PMD_DRV_LOG(DEBUG,
 539                     "tx_fc_out_tbl.va = %p tx_fc_out_tbl.dma = %p"
 540                     " tx_fc_out_tbl.ctx_id = %d\n",
 541                     bp->flow_stat->tx_fc_out_tbl.va,
 542                     (void *)((uintptr_t)bp->flow_stat->tx_fc_out_tbl.dma),
 543                     bp->flow_stat->tx_fc_out_tbl.ctx_id);
 544
 545         memset(bp->flow_stat->rx_fc_out_tbl.va,
 546                0,
 547                bp->flow_stat->rx_fc_out_tbl.size);
 548         rc = bnxt_hwrm_cfa_counter_cfg(bp, BNXT_DIR_RX,
 549                                        CFA_COUNTER_CFG_IN_COUNTER_TYPE_FC,
 550                                        bp->flow_stat->rx_fc_out_tbl.ctx_id,
 551                                        bp->flow_stat->max_fc,
 552                                        true);
 553         if (rc)
 554                 return rc;
 555
 556         memset(bp->flow_stat->tx_fc_out_tbl.va,
 557                0,
 558                bp->flow_stat->tx_fc_out_tbl.size);
 559         rc = bnxt_hwrm_cfa_counter_cfg(bp, BNXT_DIR_TX,
 560                                        CFA_COUNTER_CFG_IN_COUNTER_TYPE_FC,
 561                                        bp->flow_stat->tx_fc_out_tbl.ctx_id,
 562                                        bp->flow_stat->max_fc,
 563                                        true);
 564
 565         return rc;
 566 }
 567
 568 static int bnxt_alloc_ctx_mem_buf(char *type, size_t size,
 569                                   struct bnxt_ctx_mem_buf_info *ctx)
 570 {
 571         if (!ctx)
 572                 return -EINVAL;
 573
 574         ctx->va = rte_zmalloc(type, size, 0);
 575         if (ctx->va == NULL)
 576                 return -ENOMEM;
 577         rte_mem_lock_page(ctx->va);
 578         ctx->size = size;
 579         ctx->dma = rte_mem_virt2iova(ctx->va);
 580         if (ctx->dma == RTE_BAD_IOVA)
 581                 return -ENOMEM;
 582
 583         return 0;
 584 }
 585
 586 static int bnxt_init_fc_ctx_mem(struct bnxt *bp)
 587 {
 588         struct rte_pci_device *pdev = bp->pdev;
 589         char type[RTE_MEMZONE_NAMESIZE];
 590         uint16_t max_fc;
 591         int rc = 0;
 592
 593         max_fc = bp->flow_stat->max_fc;
 594
 595         sprintf(type, "bnxt_rx_fc_in_" PCI_PRI_FMT, pdev->addr.domain,
 596                 pdev->addr.bus, pdev->addr.devid, pdev->addr.function);
 597         /* 4 bytes for each counter-id */
 598         rc = bnxt_alloc_ctx_mem_buf(type,
 599                                     max_fc * 4,
 600                                     &bp->flow_stat->rx_fc_in_tbl);
 601         if (rc)
 602                 return rc;
 603
 604         sprintf(type, "bnxt_rx_fc_out_" PCI_PRI_FMT, pdev->addr.domain,
 605                 pdev->addr.bus, pdev->addr.devid, pdev->addr.function);
 606         /* 16 bytes for each counter - 8 bytes pkt_count, 8 bytes byte_count */
 607         rc = bnxt_alloc_ctx_mem_buf(type,
 608                                     max_fc * 16,
 609                                     &bp->flow_stat->rx_fc_out_tbl);
 610         if (rc)
 611                 return rc;
 612
 613         sprintf(type, "bnxt_tx_fc_in_" PCI_PRI_FMT, pdev->addr.domain,
 614                 pdev->addr.bus, pdev->addr.devid, pdev->addr.function);
 615         /* 4 bytes for each counter-id */
 616         rc = bnxt_alloc_ctx_mem_buf(type,
 617                                     max_fc * 4,
 618                                     &bp->flow_stat->tx_fc_in_tbl);
 619         if (rc)
 620                 return rc;
 621
 622         sprintf(type, "bnxt_tx_fc_out_" PCI_PRI_FMT, pdev->addr.domain,
 623                 pdev->addr.bus, pdev->addr.devid, pdev->addr.function);
 624         /* 16 bytes for each counter - 8 bytes pkt_count, 8 bytes byte_count */
 625         rc = bnxt_alloc_ctx_mem_buf(type,
 626                                     max_fc * 16,
 627                                     &bp->flow_stat->tx_fc_out_tbl);
 628         if (rc)
 629                 return rc;
 630
 631         rc = bnxt_register_fc_ctx_mem(bp);
 632
 633         return rc;
 634 }
 635
 636 static int bnxt_init_ctx_mem(struct bnxt *bp)
 637 {
 638         int rc = 0;
 639
 640         if (!(bp->fw_cap & BNXT_FW_CAP_ADV_FLOW_COUNTERS) ||
 641             !(BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp)) ||
 642             !BNXT_FLOW_XSTATS_EN(bp))
 643                 return 0;
 644
 645         rc = bnxt_hwrm_cfa_counter_qcaps(bp, &bp->flow_stat->max_fc);
 646         if (rc)
 647                 return rc;
 648
 649         rc = bnxt_init_fc_ctx_mem(bp);
 650
 651         return rc;
 652 }
 653
 654 static int bnxt_update_phy_setting(struct bnxt *bp)
 655 {
 656         struct rte_eth_link new;
 657         int rc;
 658
 659         rc = bnxt_get_hwrm_link_config(bp, &new);
 660         if (rc) {
 661                 PMD_DRV_LOG(ERR, "Failed to get link settings\n");
 662                 return rc;
 663         }
 664
 665         /*
 666          * On BCM957508-N2100 adapters, FW will not allow any user other
 667          * than BMC to shutdown the port. bnxt_get_hwrm_link_config() call
 668          * always returns link up. Force phy update always in that case.
 669          */
 670         if (!new.link_status || IS_BNXT_DEV_957508_N2100(bp)) {
 671                 rc = bnxt_set_hwrm_link_config(bp, true);
 672                 if (rc) {
 673                         PMD_DRV_LOG(ERR, "Failed to update PHY settings\n");
 674                         return rc;
 675                 }
 676         }
 677
 678         return rc;
 679 }
 680
 681 static int bnxt_init_chip(struct bnxt *bp)
 682 {
 683         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(bp->eth_dev);
 684         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
 685         uint32_t intr_vector = 0;
 686         uint32_t queue_id, base = BNXT_MISC_VEC_ID;
 687         uint32_t vec = BNXT_MISC_VEC_ID;
 688         unsigned int i, j;
 689         int rc;
 690
 691         if (bp->eth_dev->data->mtu > RTE_ETHER_MTU) {
 692                 bp->eth_dev->data->dev_conf.rxmode.offloads |=
 693                         DEV_RX_OFFLOAD_JUMBO_FRAME;
 694                 bp->flags |= BNXT_FLAG_JUMBO;
 695         } else {
 696                 bp->eth_dev->data->dev_conf.rxmode.offloads &=
 697                         ~DEV_RX_OFFLOAD_JUMBO_FRAME;
 698                 bp->flags &= ~BNXT_FLAG_JUMBO;
 699         }
 700
 701         /* THOR does not support ring groups.
 702          * But we will use the array to save RSS context IDs.
 703          */
 704         if (BNXT_CHIP_THOR(bp))
 705                 bp->max_ring_grps = BNXT_MAX_RSS_CTXTS_THOR;
 706
 707         rc = bnxt_alloc_all_hwrm_stat_ctxs(bp);
 708         if (rc) {
 709                 PMD_DRV_LOG(ERR, "HWRM stat ctx alloc failure rc: %x\n", rc);
 710                 goto err_out;
 711         }
 712
 713         rc = bnxt_alloc_hwrm_rings(bp);
 714         if (rc) {
 715                 PMD_DRV_LOG(ERR, "HWRM ring alloc failure rc: %x\n", rc);
 716                 goto err_out;
 717         }
 718
 719         rc = bnxt_alloc_all_hwrm_ring_grps(bp);
 720         if (rc) {
 721                 PMD_DRV_LOG(ERR, "HWRM ring grp alloc failure: %x\n", rc);
 722                 goto err_out;
 723         }
 724
 725         if (!(bp->vnic_cap_flags & BNXT_VNIC_CAP_COS_CLASSIFY))
 726                 goto skip_cosq_cfg;
 727
 728         for (j = 0, i = 0; i < BNXT_COS_QUEUE_COUNT; i++) {
 729                 if (bp->rx_cos_queue[i].id != 0xff) {
 730                         struct bnxt_vnic_info *vnic = &bp->vnic_info[j++];
 731
 732                         if (!vnic) {
 733                                 PMD_DRV_LOG(ERR,
 734                                             "Num pools more than FW profile\n");
 735                                 rc = -EINVAL;
 736                                 goto err_out;
 737                         }
 738                         vnic->cos_queue_id = bp->rx_cos_queue[i].id;
 739                         bp->rx_cosq_cnt++;
 740                 }
 741         }
 742
 743 skip_cosq_cfg:
 744         rc = bnxt_mq_rx_configure(bp);
 745         if (rc) {
 746                 PMD_DRV_LOG(ERR, "MQ mode configure failure rc: %x\n", rc);
 747                 goto err_out;
 748         }
 749
 750         /* VNIC configuration */
 751         for (i = 0; i < bp->nr_vnics; i++) {
 752                 rc = bnxt_setup_one_vnic(bp, i);
 753                 if (rc)
 754                         goto err_out;
 755         }
 756
 757         rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, &bp->vnic_info[0], 0, NULL);
 758         if (rc) {
 759                 PMD_DRV_LOG(ERR,
 760                         "HWRM cfa l2 rx mask failure rc: %x\n", rc);
 761                 goto err_out;
 762         }
 763
 764         /* check and configure queue intr-vector mapping */
 765         if ((rte_intr_cap_multiple(intr_handle) ||
 766              !RTE_ETH_DEV_SRIOV(bp->eth_dev).active) &&
 767             bp->eth_dev->data->dev_conf.intr_conf.rxq != 0) {
 768                 intr_vector = bp->eth_dev->data->nb_rx_queues;
 769                 PMD_DRV_LOG(DEBUG, "intr_vector = %d\n", intr_vector);
 770                 if (intr_vector > bp->rx_cp_nr_rings) {
 771                         PMD_DRV_LOG(ERR, "At most %d intr queues supported",
 772                                         bp->rx_cp_nr_rings);
 773                         return -ENOTSUP;
 774                 }
 775                 rc = rte_intr_efd_enable(intr_handle, intr_vector);
 776                 if (rc)
 777                         return rc;
 778         }
 779
 780         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
 781                 intr_handle->intr_vec =
 782                         rte_zmalloc("intr_vec",
 783                                     bp->eth_dev->data->nb_rx_queues *
 784                                     sizeof(int), 0);
 785                 if (intr_handle->intr_vec == NULL) {
 786                         PMD_DRV_LOG(ERR, "Failed to allocate %d rx_queues"
 787                                 " intr_vec", bp->eth_dev->data->nb_rx_queues);
 788                         rc = -ENOMEM;
 789                         goto err_disable;
 790                 }
 791                 PMD_DRV_LOG(DEBUG, "intr_handle->intr_vec = %p "
 792                         "intr_handle->nb_efd = %d intr_handle->max_intr = %d\n",
 793                          intr_handle->intr_vec, intr_handle->nb_efd,
 794                         intr_handle->max_intr);
 795                 for (queue_id = 0; queue_id < bp->eth_dev->data->nb_rx_queues;
 796                      queue_id++) {
 797                         intr_handle->intr_vec[queue_id] =
 798                                                         vec + BNXT_RX_VEC_START;
 799                         if (vec < base + intr_handle->nb_efd - 1)
 800                                 vec++;
 801                 }
 802         }
 803
 804         /* enable uio/vfio intr/eventfd mapping */
 805         rc = rte_intr_enable(intr_handle);
 806 #ifndef RTE_EXEC_ENV_FREEBSD
 807         /* In FreeBSD OS, nic_uio driver does not support interrupts */
 808         if (rc)
 809                 goto err_free;
 810 #endif
 811
 812         rc = bnxt_update_phy_setting(bp);
 813         if (rc)
 814                 goto err_free;
 815
 816         bp->mark_table = rte_zmalloc("bnxt_mark_table", BNXT_MARK_TABLE_SZ, 0);
 817         if (!bp->mark_table)
 818                 PMD_DRV_LOG(ERR, "Allocation of mark table failed\n");
 819
 820         return 0;
 821
 822 err_free:
 823         rte_free(intr_handle->intr_vec);
 824 err_disable:
 825         rte_intr_efd_disable(intr_handle);
 826 err_out:
 827         /* Some of the error status returned by FW may not be from errno.h */
 828         if (rc > 0)
 829                 rc = -EIO;
 830
 831         return rc;
 832 }
 833
 834 static int bnxt_shutdown_nic(struct bnxt *bp)
 835 {
 836         bnxt_free_all_hwrm_resources(bp);
 837         bnxt_free_all_filters(bp);
 838         bnxt_free_all_vnics(bp);
 839         return 0;
 840 }
 841
 842 /*
 843  * Device configuration and status function
 844  */
 845
 846 uint32_t bnxt_get_speed_capabilities(struct bnxt *bp)
 847 {
 848         uint32_t link_speed = bp->link_info->support_speeds;
 849         uint32_t speed_capa = 0;
 850
 851         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_100MB)
 852                 speed_capa |= ETH_LINK_SPEED_100M;
 853         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_100MBHD)
 854                 speed_capa |= ETH_LINK_SPEED_100M_HD;
 855         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_1GB)
 856                 speed_capa |= ETH_LINK_SPEED_1G;
 857         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_2_5GB)
 858                 speed_capa |= ETH_LINK_SPEED_2_5G;
 859         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_10GB)
 860                 speed_capa |= ETH_LINK_SPEED_10G;
 861         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_20GB)
 862                 speed_capa |= ETH_LINK_SPEED_20G;
 863         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_25GB)
 864                 speed_capa |= ETH_LINK_SPEED_25G;
 865         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_40GB)
 866                 speed_capa |= ETH_LINK_SPEED_40G;
 867         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_50GB)
 868                 speed_capa |= ETH_LINK_SPEED_50G;
 869         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_100GB)
 870                 speed_capa |= ETH_LINK_SPEED_100G;
 871         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_PAM4_SPEEDS_50G)
 872                 speed_capa |= ETH_LINK_SPEED_50G;
 873         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_PAM4_SPEEDS_100G)
 874                 speed_capa |= ETH_LINK_SPEED_100G;
 875         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_PAM4_SPEEDS_200G)
 876                 speed_capa |= ETH_LINK_SPEED_200G;
 877
 878         if (bp->link_info->auto_mode ==
 879             HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_MODE_NONE)
 880                 speed_capa |= ETH_LINK_SPEED_FIXED;
 881         else
 882                 speed_capa |= ETH_LINK_SPEED_AUTONEG;
 883
 884         return speed_capa;
 885 }
 886
 887 static int bnxt_dev_info_get_op(struct rte_eth_dev *eth_dev,
 888                                 struct rte_eth_dev_info *dev_info)
 889 {
 890         struct rte_pci_device *pdev = RTE_DEV_TO_PCI(eth_dev->device);
 891         struct bnxt *bp = eth_dev->data->dev_private;
 892         uint16_t max_vnics, i, j, vpool, vrxq;
 893         unsigned int max_rx_rings;
 894         int rc;
 895
 896         rc = is_bnxt_in_error(bp);
 897         if (rc)
 898                 return rc;
 899
 900         /* MAC Specifics */
 901         dev_info->max_mac_addrs = bp->max_l2_ctx;
 902         dev_info->max_hash_mac_addrs = 0;
 903
 904         /* PF/VF specifics */
 905         if (BNXT_PF(bp))
 906                 dev_info->max_vfs = pdev->max_vfs;
 907
 908         max_rx_rings = BNXT_MAX_RINGS(bp);
 909         /* For the sake of symmetry, max_rx_queues = max_tx_queues */
 910         dev_info->max_rx_queues = max_rx_rings;
 911         dev_info->max_tx_queues = max_rx_rings;
 912         dev_info->reta_size = bnxt_rss_hash_tbl_size(bp);
 913         dev_info->hash_key_size = 40;
 914         max_vnics = bp->max_vnics;
 915
 916         /* MTU specifics */
 917         dev_info->min_mtu = RTE_ETHER_MIN_MTU;
 918         dev_info->max_mtu = BNXT_MAX_MTU;
 919
 920         /* Fast path specifics */
 921         dev_info->min_rx_bufsize = 1;
 922         dev_info->max_rx_pktlen = BNXT_MAX_PKT_LEN;
 923
 924         dev_info->rx_offload_capa = BNXT_DEV_RX_OFFLOAD_SUPPORT;
 925         if (bp->flags & BNXT_FLAG_PTP_SUPPORTED)
 926                 dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_TIMESTAMP;
 927         dev_info->tx_queue_offload_capa = DEV_TX_OFFLOAD_MBUF_FAST_FREE;
 928         dev_info->tx_offload_capa = BNXT_DEV_TX_OFFLOAD_SUPPORT |
 929                                     dev_info->tx_queue_offload_capa;
 930         dev_info->flow_type_rss_offloads = BNXT_ETH_RSS_SUPPORT;
 931
 932         dev_info->speed_capa = bnxt_get_speed_capabilities(bp);
 933
 934         /* *INDENT-OFF* */
 935         dev_info->default_rxconf = (struct rte_eth_rxconf) {
 936                 .rx_thresh = {
 937                         .pthresh = 8,
 938                         .hthresh = 8,
 939                         .wthresh = 0,
 940                 },
 941                 .rx_free_thresh = 32,
 942                 .rx_drop_en = BNXT_DEFAULT_RX_DROP_EN,
 943         };
 944
 945         dev_info->default_txconf = (struct rte_eth_txconf) {
 946                 .tx_thresh = {
 947                         .pthresh = 32,
 948                         .hthresh = 0,
 949                         .wthresh = 0,
 950                 },
 951                 .tx_free_thresh = 32,
 952                 .tx_rs_thresh = 32,
 953         };
 954         eth_dev->data->dev_conf.intr_conf.lsc = 1;
 955
 956         eth_dev->data->dev_conf.intr_conf.rxq = 1;
 957         dev_info->rx_desc_lim.nb_min = BNXT_MIN_RING_DESC;
 958         dev_info->rx_desc_lim.nb_max = BNXT_MAX_RX_RING_DESC;
 959         dev_info->tx_desc_lim.nb_min = BNXT_MIN_RING_DESC;
 960         dev_info->tx_desc_lim.nb_max = BNXT_MAX_TX_RING_DESC;
 961
 962         if (BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp)) {
 963                 dev_info->switch_info.name = eth_dev->device->name;
 964                 dev_info->switch_info.domain_id = bp->switch_domain_id;
 965                 dev_info->switch_info.port_id =
 966                                 BNXT_PF(bp) ? BNXT_SWITCH_PORT_ID_PF :
 967                                     BNXT_SWITCH_PORT_ID_TRUSTED_VF;
 968         }
 969
 970         /* *INDENT-ON* */
 971
 972         /*
 973          * TODO: default_rxconf, default_txconf, rx_desc_lim, and tx_desc_lim
 974          *       need further investigation.
 975          */
 976
 977         /* VMDq resources */
 978         vpool = 64; /* ETH_64_POOLS */
 979         vrxq = 128; /* ETH_VMDQ_DCB_NUM_QUEUES */
 980         for (i = 0; i < 4; vpool >>= 1, i++) {
 981                 if (max_vnics > vpool) {
 982                         for (j = 0; j < 5; vrxq >>= 1, j++) {
 983                                 if (dev_info->max_rx_queues > vrxq) {
 984                                         if (vpool > vrxq)
 985                                                 vpool = vrxq;
 986                                         goto found;
 987                                 }
 988                         }
 989                         /* Not enough resources to support VMDq */
 990                         break;
 991                 }
 992         }
 993         /* Not enough resources to support VMDq */
 994         vpool = 0;
 995         vrxq = 0;
 996 found:
 997         dev_info->max_vmdq_pools = vpool;
 998         dev_info->vmdq_queue_num = vrxq;
 999
1000         dev_info->vmdq_pool_base = 0;
1001         dev_info->vmdq_queue_base = 0;
1002
1003         return 0;
1004 }
1005
1006 /* Configure the device based on the configuration provided */
1007 static int bnxt_dev_configure_op(struct rte_eth_dev *eth_dev)
1008 {
1009         struct bnxt *bp = eth_dev->data->dev_private;
1010         uint64_t rx_offloads = eth_dev->data->dev_conf.rxmode.offloads;
1011         int rc;
1012
1013         bp->rx_queues = (void *)eth_dev->data->rx_queues;
1014         bp->tx_queues = (void *)eth_dev->data->tx_queues;
1015         bp->tx_nr_rings = eth_dev->data->nb_tx_queues;
1016         bp->rx_nr_rings = eth_dev->data->nb_rx_queues;
1017
1018         rc = is_bnxt_in_error(bp);
1019         if (rc)
1020                 return rc;
1021
1022         if (BNXT_VF(bp) && (bp->flags & BNXT_FLAG_NEW_RM)) {
1023                 rc = bnxt_hwrm_check_vf_rings(bp);
1024                 if (rc) {
1025                         PMD_DRV_LOG(ERR, "HWRM insufficient resources\n");
1026                         return -ENOSPC;
1027                 }
1028
1029                 /* If a resource has already been allocated - in this case
1030                  * it is the async completion ring, free it. Reallocate it after
1031                  * resource reservation. This will ensure the resource counts
1032                  * are calculated correctly.
1033                  */
1034
1035                 pthread_mutex_lock(&bp->def_cp_lock);
1036
1037                 if (!BNXT_HAS_NQ(bp) && bp->async_cp_ring) {
1038                         bnxt_disable_int(bp);
1039                         bnxt_free_cp_ring(bp, bp->async_cp_ring);
1040                 }
1041
1042                 rc = bnxt_hwrm_func_reserve_vf_resc(bp, false);
1043                 if (rc) {
1044                         PMD_DRV_LOG(ERR, "HWRM resource alloc fail:%x\n", rc);
1045                         pthread_mutex_unlock(&bp->def_cp_lock);
1046                         return -ENOSPC;
1047                 }
1048
1049                 if (!BNXT_HAS_NQ(bp) && bp->async_cp_ring) {
1050                         rc = bnxt_alloc_async_cp_ring(bp);
1051                         if (rc) {
1052                                 pthread_mutex_unlock(&bp->def_cp_lock);
1053                                 return rc;
1054                         }
1055                         bnxt_enable_int(bp);
1056                 }
1057
1058                 pthread_mutex_unlock(&bp->def_cp_lock);
1059         } else {
1060                 /* legacy driver needs to get updated values */
1061                 rc = bnxt_hwrm_func_qcaps(bp);
1062                 if (rc) {
1063                         PMD_DRV_LOG(ERR, "hwrm func qcaps fail:%d\n", rc);
1064                         return rc;
1065                 }
1066         }
1067
1068         /* Inherit new configurations */
1069         if (eth_dev->data->nb_rx_queues > bp->max_rx_rings ||
1070             eth_dev->data->nb_tx_queues > bp->max_tx_rings ||
1071             eth_dev->data->nb_rx_queues + eth_dev->data->nb_tx_queues
1072                 + BNXT_NUM_ASYNC_CPR(bp) > bp->max_cp_rings ||
1073             eth_dev->data->nb_rx_queues + eth_dev->data->nb_tx_queues >
1074             bp->max_stat_ctx)
1075                 goto resource_error;
1076
1077         if (BNXT_HAS_RING_GRPS(bp) &&
1078             (uint32_t)(eth_dev->data->nb_rx_queues) > bp->max_ring_grps)
1079                 goto resource_error;
1080
1081         if (!(eth_dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_RSS) &&
1082             bp->max_vnics < eth_dev->data->nb_rx_queues)
1083                 goto resource_error;
1084
1085         bp->rx_cp_nr_rings = bp->rx_nr_rings;
1086         bp->tx_cp_nr_rings = bp->tx_nr_rings;
1087
1088         if (eth_dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG)
1089                 rx_offloads |= DEV_RX_OFFLOAD_RSS_HASH;
1090         eth_dev->data->dev_conf.rxmode.offloads = rx_offloads;
1091
1092         if (rx_offloads & DEV_RX_OFFLOAD_JUMBO_FRAME) {
1093                 eth_dev->data->mtu =
1094                         eth_dev->data->dev_conf.rxmode.max_rx_pkt_len -
1095                         RTE_ETHER_HDR_LEN - RTE_ETHER_CRC_LEN - VLAN_TAG_SIZE *
1096                         BNXT_NUM_VLANS;
1097                 bnxt_mtu_set_op(eth_dev, eth_dev->data->mtu);
1098         }
1099         return 0;
1100
1101 resource_error:
1102         PMD_DRV_LOG(ERR,
1103                     "Insufficient resources to support requested config\n");
1104         PMD_DRV_LOG(ERR,
1105                     "Num Queues Requested: Tx %d, Rx %d\n",
1106                     eth_dev->data->nb_tx_queues,
1107                     eth_dev->data->nb_rx_queues);
1108         PMD_DRV_LOG(ERR,
1109                     "MAX: TxQ %d, RxQ %d, CQ %d Stat %d, Grp %d, Vnic %d\n",
1110                     bp->max_tx_rings, bp->max_rx_rings, bp->max_cp_rings,
1111                     bp->max_stat_ctx, bp->max_ring_grps, bp->max_vnics);
1112         return -ENOSPC;
1113 }
1114
1115 void bnxt_print_link_info(struct rte_eth_dev *eth_dev)
1116 {
1117         struct rte_eth_link *link = &eth_dev->data->dev_link;
1118
1119         if (link->link_status)
1120                 PMD_DRV_LOG(INFO, "Port %d Link Up - speed %u Mbps - %s\n",
1121                         eth_dev->data->port_id,
1122                         (uint32_t)link->link_speed,
1123                         (link->link_duplex == ETH_LINK_FULL_DUPLEX) ?
1124                         ("full-duplex") : ("half-duplex\n"));
1125         else
1126                 PMD_DRV_LOG(INFO, "Port %d Link Down\n",
1127                         eth_dev->data->port_id);
1128 }
1129
1130 /*
1131  * Determine whether the current configuration requires support for scattered
1132  * receive; return 1 if scattered receive is required and 0 if not.
1133  */
1134 static int bnxt_scattered_rx(struct rte_eth_dev *eth_dev)
1135 {
1136         uint16_t buf_size;
1137         int i;
1138
1139         if (eth_dev->data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_SCATTER)
1140                 return 1;
1141
1142         for (i = 0; i < eth_dev->data->nb_rx_queues; i++) {
1143                 struct bnxt_rx_queue *rxq = eth_dev->data->rx_queues[i];
1144
1145                 buf_size = (uint16_t)(rte_pktmbuf_data_room_size(rxq->mb_pool) -
1146                                       RTE_PKTMBUF_HEADROOM);
1147                 if (eth_dev->data->dev_conf.rxmode.max_rx_pkt_len > buf_size)
1148                         return 1;
1149         }
1150         return 0;
1151 }
1152
1153 static eth_rx_burst_t
1154 bnxt_receive_function(struct rte_eth_dev *eth_dev)
1155 {
1156         struct bnxt *bp = eth_dev->data->dev_private;
1157
1158 #if defined(RTE_ARCH_X86) || defined(RTE_ARCH_ARM64)
1159 #ifndef RTE_LIBRTE_IEEE1588
1160         /*
1161          * Vector mode receive can be enabled only if scatter rx is not
1162          * in use and rx offloads are limited to VLAN stripping and
1163          * CRC stripping.
1164          */
1165         if (!eth_dev->data->scattered_rx &&
1166             !(eth_dev->data->dev_conf.rxmode.offloads &
1167               ~(DEV_RX_OFFLOAD_VLAN_STRIP |
1168                 DEV_RX_OFFLOAD_KEEP_CRC |
1169                 DEV_RX_OFFLOAD_JUMBO_FRAME |
1170                 DEV_RX_OFFLOAD_IPV4_CKSUM |
1171                 DEV_RX_OFFLOAD_UDP_CKSUM |
1172                 DEV_RX_OFFLOAD_TCP_CKSUM |
1173                 DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM |
1174                 DEV_RX_OFFLOAD_RSS_HASH |
1175                 DEV_RX_OFFLOAD_VLAN_FILTER)) &&
1176             !BNXT_TRUFLOW_EN(bp) && BNXT_NUM_ASYNC_CPR(bp) &&
1177             rte_vect_get_max_simd_bitwidth() >= RTE_VECT_SIMD_128) {
1178                 PMD_DRV_LOG(INFO, "Using vector mode receive for port %d\n",
1179                             eth_dev->data->port_id);
1180                 bp->flags |= BNXT_FLAG_RX_VECTOR_PKT_MODE;
1181                 return bnxt_recv_pkts_vec;
1182         }
1183         PMD_DRV_LOG(INFO, "Vector mode receive disabled for port %d\n",
1184                     eth_dev->data->port_id);
1185         PMD_DRV_LOG(INFO,
1186                     "Port %d scatter: %d rx offload: %" PRIX64 "\n",
1187                     eth_dev->data->port_id,
1188                     eth_dev->data->scattered_rx,
1189                     eth_dev->data->dev_conf.rxmode.offloads);
1190 #endif
1191 #endif
1192         bp->flags &= ~BNXT_FLAG_RX_VECTOR_PKT_MODE;
1193         return bnxt_recv_pkts;
1194 }
1195
1196 static eth_tx_burst_t
1197 bnxt_transmit_function(__rte_unused struct rte_eth_dev *eth_dev)
1198 {
1199 #if defined(RTE_ARCH_X86) || defined(RTE_ARCH_ARM64)
1200 #ifndef RTE_LIBRTE_IEEE1588
1201         uint64_t offloads = eth_dev->data->dev_conf.txmode.offloads;
1202         struct bnxt *bp = eth_dev->data->dev_private;
1203
1204         /*
1205          * Vector mode transmit can be enabled only if not using scatter rx
1206          * or tx offloads.
1207          */
1208         if (!eth_dev->data->scattered_rx &&
1209             !(offloads & ~DEV_TX_OFFLOAD_MBUF_FAST_FREE) &&
1210             !BNXT_TRUFLOW_EN(bp) &&
1211             rte_vect_get_max_simd_bitwidth() >= RTE_VECT_SIMD_128) {
1212                 PMD_DRV_LOG(INFO, "Using vector mode transmit for port %d\n",
1213                             eth_dev->data->port_id);
1214                 return bnxt_xmit_pkts_vec;
1215         }
1216         PMD_DRV_LOG(INFO, "Vector mode transmit disabled for port %d\n",
1217                     eth_dev->data->port_id);
1218         PMD_DRV_LOG(INFO,
1219                     "Port %d scatter: %d tx offload: %" PRIX64 "\n",
1220                     eth_dev->data->port_id,
1221                     eth_dev->data->scattered_rx,
1222                     offloads);
1223 #endif
1224 #endif
1225         return bnxt_xmit_pkts;
1226 }
1227
1228 static int bnxt_handle_if_change_status(struct bnxt *bp)
1229 {
1230         int rc;
1231
1232         /* Since fw has undergone a reset and lost all contexts,
1233          * set fatal flag to not issue hwrm during cleanup
1234          */
1235         bp->flags |= BNXT_FLAG_FATAL_ERROR;
1236         bnxt_uninit_resources(bp, true);
1237
1238         /* clear fatal flag so that re-init happens */
1239         bp->flags &= ~BNXT_FLAG_FATAL_ERROR;
1240         rc = bnxt_init_resources(bp, true);
1241
1242         bp->flags &= ~BNXT_FLAG_IF_CHANGE_HOT_FW_RESET_DONE;
1243
1244         return rc;
1245 }
1246
1247 static int bnxt_dev_start_op(struct rte_eth_dev *eth_dev)
1248 {
1249         struct bnxt *bp = eth_dev->data->dev_private;
1250         uint64_t rx_offloads = eth_dev->data->dev_conf.rxmode.offloads;
1251         int vlan_mask = 0;
1252         int rc, retry_cnt = BNXT_IF_CHANGE_RETRY_COUNT;
1253
1254         if (!eth_dev->data->nb_tx_queues || !eth_dev->data->nb_rx_queues) {
1255                 PMD_DRV_LOG(ERR, "Queues are not configured yet!\n");
1256                 return -EINVAL;
1257         }
1258
1259         if (bp->rx_cp_nr_rings > RTE_ETHDEV_QUEUE_STAT_CNTRS) {
1260                 PMD_DRV_LOG(ERR,
1261                         "RxQ cnt %d > RTE_ETHDEV_QUEUE_STAT_CNTRS %d\n",
1262                         bp->rx_cp_nr_rings, RTE_ETHDEV_QUEUE_STAT_CNTRS);
1263         }
1264
1265         do {
1266                 rc = bnxt_hwrm_if_change(bp, true);
1267                 if (rc == 0 || rc != -EAGAIN)
1268                         break;
1269
1270                 rte_delay_ms(BNXT_IF_CHANGE_RETRY_INTERVAL);
1271         } while (retry_cnt--);
1272
1273         if (rc)
1274                 return rc;
1275
1276         if (bp->flags & BNXT_FLAG_IF_CHANGE_HOT_FW_RESET_DONE) {
1277                 rc = bnxt_handle_if_change_status(bp);
1278                 if (rc)
1279                         return rc;
1280         }
1281
1282         bnxt_enable_int(bp);
1283
1284         rc = bnxt_init_chip(bp);
1285         if (rc)
1286                 goto error;
1287
1288         eth_dev->data->scattered_rx = bnxt_scattered_rx(eth_dev);
1289         eth_dev->data->dev_started = 1;
1290
1291         bnxt_link_update_op(eth_dev, 1);
1292
1293         if (rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER)
1294                 vlan_mask |= ETH_VLAN_FILTER_MASK;
1295         if (rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
1296                 vlan_mask |= ETH_VLAN_STRIP_MASK;
1297         rc = bnxt_vlan_offload_set_op(eth_dev, vlan_mask);
1298         if (rc)
1299                 goto error;
1300
1301         /* Initialize bnxt ULP port details */
1302         rc = bnxt_ulp_port_init(bp);
1303         if (rc)
1304                 goto error;
1305
1306         eth_dev->rx_pkt_burst = bnxt_receive_function(eth_dev);
1307         eth_dev->tx_pkt_burst = bnxt_transmit_function(eth_dev);
1308
1309         bnxt_schedule_fw_health_check(bp);
1310
1311         return 0;
1312
1313 error:
1314         bnxt_shutdown_nic(bp);
1315         bnxt_free_tx_mbufs(bp);
1316         bnxt_free_rx_mbufs(bp);
1317         bnxt_hwrm_if_change(bp, false);
1318         eth_dev->data->dev_started = 0;
1319         return rc;
1320 }
1321
1322 static int bnxt_dev_set_link_up_op(struct rte_eth_dev *eth_dev)
1323 {
1324         struct bnxt *bp = eth_dev->data->dev_private;
1325         int rc = 0;
1326
1327         if (!bp->link_info->link_up)
1328                 rc = bnxt_set_hwrm_link_config(bp, true);
1329         if (!rc)
1330                 eth_dev->data->dev_link.link_status = 1;
1331
1332         bnxt_print_link_info(eth_dev);
1333         return rc;
1334 }
1335
1336 static int bnxt_dev_set_link_down_op(struct rte_eth_dev *eth_dev)
1337 {
1338         struct bnxt *bp = eth_dev->data->dev_private;
1339
1340         eth_dev->data->dev_link.link_status = 0;
1341         bnxt_set_hwrm_link_config(bp, false);
1342         bp->link_info->link_up = 0;
1343
1344         return 0;
1345 }
1346
1347 static void bnxt_free_switch_domain(struct bnxt *bp)
1348 {
1349         int rc = 0;
1350
1351         if (bp->switch_domain_id) {
1352                 rc = rte_eth_switch_domain_free(bp->switch_domain_id);
1353                 if (rc)
1354                         PMD_DRV_LOG(ERR, "free switch domain:%d fail: %d\n",
1355                                     bp->switch_domain_id, rc);
1356         }
1357 }
1358
1359 /* Unload the driver, release resources */
1360 static int bnxt_dev_stop_op(struct rte_eth_dev *eth_dev)
1361 {
1362         struct bnxt *bp = eth_dev->data->dev_private;
1363         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1364         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1365         struct rte_eth_link link;
1366         int ret;
1367
1368         eth_dev->data->dev_started = 0;
1369         eth_dev->data->scattered_rx = 0;
1370
1371         /* Prevent crashes when queues are still in use */
1372         eth_dev->rx_pkt_burst = &bnxt_dummy_recv_pkts;
1373         eth_dev->tx_pkt_burst = &bnxt_dummy_xmit_pkts;
1374
1375         bnxt_disable_int(bp);
1376
1377         /* disable uio/vfio intr/eventfd mapping */
1378         rte_intr_disable(intr_handle);
1379
1380         /* Stop the child representors for this device */
1381         ret = bnxt_rep_stop_all(bp);
1382         if (ret != 0)
1383                 return ret;
1384
1385         /* delete the bnxt ULP port details */
1386         bnxt_ulp_port_deinit(bp);
1387
1388         bnxt_cancel_fw_health_check(bp);
1389
1390         /* Do not bring link down during reset recovery */
1391         if (!is_bnxt_in_error(bp)) {
1392                 bnxt_dev_set_link_down_op(eth_dev);
1393                 /* Wait for link to be reset */
1394                 if (BNXT_SINGLE_PF(bp))
1395                         rte_delay_ms(500);
1396                 /* clear the recorded link status */
1397                 memset(&link, 0, sizeof(link));
1398                 rte_eth_linkstatus_set(eth_dev, &link);
1399         }
1400
1401         /* Clean queue intr-vector mapping */
1402         rte_intr_efd_disable(intr_handle);
1403         if (intr_handle->intr_vec != NULL) {
1404                 rte_free(intr_handle->intr_vec);
1405                 intr_handle->intr_vec = NULL;
1406         }
1407
1408         bnxt_hwrm_port_clr_stats(bp);
1409         bnxt_free_tx_mbufs(bp);
1410         bnxt_free_rx_mbufs(bp);
1411         /* Process any remaining notifications in default completion queue */
1412         bnxt_int_handler(eth_dev);
1413         bnxt_shutdown_nic(bp);
1414         bnxt_hwrm_if_change(bp, false);
1415
1416         rte_free(bp->mark_table);
1417         bp->mark_table = NULL;
1418
1419         bp->flags &= ~BNXT_FLAG_RX_VECTOR_PKT_MODE;
1420         bp->rx_cosq_cnt = 0;
1421         /* All filters are deleted on a port stop. */
1422         if (BNXT_FLOW_XSTATS_EN(bp))
1423                 bp->flow_stat->flow_count = 0;
1424
1425         return 0;
1426 }
1427
1428 static int bnxt_dev_close_op(struct rte_eth_dev *eth_dev)
1429 {
1430         struct bnxt *bp = eth_dev->data->dev_private;
1431         int ret = 0;
1432
1433         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1434                 return 0;
1435
1436         /* cancel the recovery handler before remove dev */
1437         rte_eal_alarm_cancel(bnxt_dev_reset_and_resume, (void *)bp);
1438         rte_eal_alarm_cancel(bnxt_dev_recover, (void *)bp);
1439         bnxt_cancel_fc_thread(bp);
1440
1441         if (eth_dev->data->dev_started)
1442                 ret = bnxt_dev_stop_op(eth_dev);
1443
1444         bnxt_free_switch_domain(bp);
1445
1446         bnxt_uninit_resources(bp, false);
1447
1448         bnxt_free_leds_info(bp);
1449         bnxt_free_cos_queues(bp);
1450         bnxt_free_link_info(bp);
1451         bnxt_free_pf_info(bp);
1452         bnxt_free_parent_info(bp);
1453
1454         rte_memzone_free((const struct rte_memzone *)bp->tx_mem_zone);
1455         bp->tx_mem_zone = NULL;
1456         rte_memzone_free((const struct rte_memzone *)bp->rx_mem_zone);
1457         bp->rx_mem_zone = NULL;
1458
1459         bnxt_hwrm_free_vf_info(bp);
1460
1461         rte_free(bp->grp_info);
1462         bp->grp_info = NULL;
1463
1464         return ret;
1465 }
1466
1467 static void bnxt_mac_addr_remove_op(struct rte_eth_dev *eth_dev,
1468                                     uint32_t index)
1469 {
1470         struct bnxt *bp = eth_dev->data->dev_private;
1471         uint64_t pool_mask = eth_dev->data->mac_pool_sel[index];
1472         struct bnxt_vnic_info *vnic;
1473         struct bnxt_filter_info *filter, *temp_filter;
1474         uint32_t i;
1475
1476         if (is_bnxt_in_error(bp))
1477                 return;
1478
1479         /*
1480          * Loop through all VNICs from the specified filter flow pools to
1481          * remove the corresponding MAC addr filter
1482          */
1483         for (i = 0; i < bp->nr_vnics; i++) {
1484                 if (!(pool_mask & (1ULL << i)))
1485                         continue;
1486
1487                 vnic = &bp->vnic_info[i];
1488                 filter = STAILQ_FIRST(&vnic->filter);
1489                 while (filter) {
1490                         temp_filter = STAILQ_NEXT(filter, next);
1491                         if (filter->mac_index == index) {
1492                                 STAILQ_REMOVE(&vnic->filter, filter,
1493                                                 bnxt_filter_info, next);
1494                                 bnxt_hwrm_clear_l2_filter(bp, filter);
1495                                 bnxt_free_filter(bp, filter);
1496                         }
1497                         filter = temp_filter;
1498                 }
1499         }
1500 }
1501
1502 static int bnxt_add_mac_filter(struct bnxt *bp, struct bnxt_vnic_info *vnic,
1503                                struct rte_ether_addr *mac_addr, uint32_t index,
1504                                uint32_t pool)
1505 {
1506         struct bnxt_filter_info *filter;
1507         int rc = 0;
1508
1509         /* Attach requested MAC address to the new l2_filter */
1510         STAILQ_FOREACH(filter, &vnic->filter, next) {
1511                 if (filter->mac_index == index) {
1512                         PMD_DRV_LOG(DEBUG,
1513                                     "MAC addr already existed for pool %d\n",
1514                                     pool);
1515                         return 0;
1516                 }
1517         }
1518
1519         filter = bnxt_alloc_filter(bp);
1520         if (!filter) {
1521                 PMD_DRV_LOG(ERR, "L2 filter alloc failed\n");
1522                 return -ENODEV;
1523         }
1524
1525         /* bnxt_alloc_filter copies default MAC to filter->l2_addr. So,
1526          * if the MAC that's been programmed now is a different one, then,
1527          * copy that addr to filter->l2_addr
1528          */
1529         if (mac_addr)
1530                 memcpy(filter->l2_addr, mac_addr, RTE_ETHER_ADDR_LEN);
1531         filter->flags |= HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_OUTERMOST;
1532
1533         rc = bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id, filter);
1534         if (!rc) {
1535                 filter->mac_index = index;
1536                 if (filter->mac_index == 0)
1537                         STAILQ_INSERT_HEAD(&vnic->filter, filter, next);
1538                 else
1539                         STAILQ_INSERT_TAIL(&vnic->filter, filter, next);
1540         } else {
1541                 bnxt_free_filter(bp, filter);
1542         }
1543
1544         return rc;
1545 }
1546
1547 static int bnxt_mac_addr_add_op(struct rte_eth_dev *eth_dev,
1548                                 struct rte_ether_addr *mac_addr,
1549                                 uint32_t index, uint32_t pool)
1550 {
1551         struct bnxt *bp = eth_dev->data->dev_private;
1552         struct bnxt_vnic_info *vnic = &bp->vnic_info[pool];
1553         int rc = 0;
1554
1555         rc = is_bnxt_in_error(bp);
1556         if (rc)
1557                 return rc;
1558
1559         if (BNXT_VF(bp) && !BNXT_VF_IS_TRUSTED(bp)) {
1560                 PMD_DRV_LOG(ERR, "Cannot add MAC address to a VF interface\n");
1561                 return -ENOTSUP;
1562         }
1563
1564         if (!vnic) {
1565                 PMD_DRV_LOG(ERR, "VNIC not found for pool %d!\n", pool);
1566                 return -EINVAL;
1567         }
1568
1569         /* Filter settings will get applied when port is started */
1570         if (!eth_dev->data->dev_started)
1571                 return 0;
1572
1573         rc = bnxt_add_mac_filter(bp, vnic, mac_addr, index, pool);
1574
1575         return rc;
1576 }
1577
1578 int bnxt_link_update_op(struct rte_eth_dev *eth_dev, int wait_to_complete)
1579 {
1580         int rc = 0;
1581         struct bnxt *bp = eth_dev->data->dev_private;
1582         struct rte_eth_link new;
1583         int cnt = wait_to_complete ? BNXT_MAX_LINK_WAIT_CNT :
1584                         BNXT_MIN_LINK_WAIT_CNT;
1585
1586         rc = is_bnxt_in_error(bp);
1587         if (rc)
1588                 return rc;
1589
1590         memset(&new, 0, sizeof(new));
1591         do {
1592                 /* Retrieve link info from hardware */
1593                 rc = bnxt_get_hwrm_link_config(bp, &new);
1594                 if (rc) {
1595                         new.link_speed = ETH_LINK_SPEED_100M;
1596                         new.link_duplex = ETH_LINK_FULL_DUPLEX;
1597                         PMD_DRV_LOG(ERR,
1598                                 "Failed to retrieve link rc = 0x%x!\n", rc);
1599                         goto out;
1600                 }
1601
1602                 if (!wait_to_complete || new.link_status)
1603                         break;
1604
1605                 rte_delay_ms(BNXT_LINK_WAIT_INTERVAL);
1606         } while (cnt--);
1607
1608         /* Only single function PF can bring phy down.
1609          * When port is stopped, report link down for VF/MH/NPAR functions.
1610          */
1611         if (!BNXT_SINGLE_PF(bp) && !eth_dev->data->dev_started)
1612                 memset(&new, 0, sizeof(new));
1613
1614 out:
1615         /* Timed out or success */
1616         if (new.link_status != eth_dev->data->dev_link.link_status ||
1617         new.link_speed != eth_dev->data->dev_link.link_speed) {
1618                 rte_eth_linkstatus_set(eth_dev, &new);
1619
1620                 rte_eth_dev_callback_process(eth_dev,
1621                                              RTE_ETH_EVENT_INTR_LSC,
1622                                              NULL);
1623
1624                 bnxt_print_link_info(eth_dev);
1625         }
1626
1627         return rc;
1628 }
1629
1630 static int bnxt_promiscuous_enable_op(struct rte_eth_dev *eth_dev)
1631 {
1632         struct bnxt *bp = eth_dev->data->dev_private;
1633         struct bnxt_vnic_info *vnic;
1634         uint32_t old_flags;
1635         int rc;
1636
1637         rc = is_bnxt_in_error(bp);
1638         if (rc)
1639                 return rc;
1640
1641         /* Filter settings will get applied when port is started */
1642         if (!eth_dev->data->dev_started)
1643                 return 0;
1644
1645         if (bp->vnic_info == NULL)
1646                 return 0;
1647
1648         vnic = BNXT_GET_DEFAULT_VNIC(bp);
1649
1650         old_flags = vnic->flags;
1651         vnic->flags |= BNXT_VNIC_INFO_PROMISC;
1652         rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1653         if (rc != 0)
1654                 vnic->flags = old_flags;
1655
1656         return rc;
1657 }
1658
1659 static int bnxt_promiscuous_disable_op(struct rte_eth_dev *eth_dev)
1660 {
1661         struct bnxt *bp = eth_dev->data->dev_private;
1662         struct bnxt_vnic_info *vnic;
1663         uint32_t old_flags;
1664         int rc;
1665
1666         rc = is_bnxt_in_error(bp);
1667         if (rc)
1668                 return rc;
1669
1670         /* Filter settings will get applied when port is started */
1671         if (!eth_dev->data->dev_started)
1672                 return 0;
1673
1674         if (bp->vnic_info == NULL)
1675                 return 0;
1676
1677         vnic = BNXT_GET_DEFAULT_VNIC(bp);
1678
1679         old_flags = vnic->flags;
1680         vnic->flags &= ~BNXT_VNIC_INFO_PROMISC;
1681         rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1682         if (rc != 0)
1683                 vnic->flags = old_flags;
1684
1685         return rc;
1686 }
1687
1688 static int bnxt_allmulticast_enable_op(struct rte_eth_dev *eth_dev)
1689 {
1690         struct bnxt *bp = eth_dev->data->dev_private;
1691         struct bnxt_vnic_info *vnic;
1692         uint32_t old_flags;
1693         int rc;
1694
1695         rc = is_bnxt_in_error(bp);
1696         if (rc)
1697                 return rc;
1698
1699         /* Filter settings will get applied when port is started */
1700         if (!eth_dev->data->dev_started)
1701                 return 0;
1702
1703         if (bp->vnic_info == NULL)
1704                 return 0;
1705
1706         vnic = BNXT_GET_DEFAULT_VNIC(bp);
1707
1708         old_flags = vnic->flags;
1709         vnic->flags |= BNXT_VNIC_INFO_ALLMULTI;
1710         rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1711         if (rc != 0)
1712                 vnic->flags = old_flags;
1713
1714         return rc;
1715 }
1716
1717 static int bnxt_allmulticast_disable_op(struct rte_eth_dev *eth_dev)
1718 {
1719         struct bnxt *bp = eth_dev->data->dev_private;
1720         struct bnxt_vnic_info *vnic;
1721         uint32_t old_flags;
1722         int rc;
1723
1724         rc = is_bnxt_in_error(bp);
1725         if (rc)
1726                 return rc;
1727
1728         /* Filter settings will get applied when port is started */
1729         if (!eth_dev->data->dev_started)
1730                 return 0;
1731
1732         if (bp->vnic_info == NULL)
1733                 return 0;
1734
1735         vnic = BNXT_GET_DEFAULT_VNIC(bp);
1736
1737         old_flags = vnic->flags;
1738         vnic->flags &= ~BNXT_VNIC_INFO_ALLMULTI;
1739         rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1740         if (rc != 0)
1741                 vnic->flags = old_flags;
1742
1743         return rc;
1744 }
1745
1746 /* Return bnxt_rx_queue pointer corresponding to a given rxq. */
1747 static struct bnxt_rx_queue *bnxt_qid_to_rxq(struct bnxt *bp, uint16_t qid)
1748 {
1749         if (qid >= bp->rx_nr_rings)
1750                 return NULL;
1751
1752         return bp->eth_dev->data->rx_queues[qid];
1753 }
1754
1755 /* Return rxq corresponding to a given rss table ring/group ID. */
1756 static uint16_t bnxt_rss_to_qid(struct bnxt *bp, uint16_t fwr)
1757 {
1758         struct bnxt_rx_queue *rxq;
1759         unsigned int i;
1760
1761         if (!BNXT_HAS_RING_GRPS(bp)) {
1762                 for (i = 0; i < bp->rx_nr_rings; i++) {
1763                         rxq = bp->eth_dev->data->rx_queues[i];
1764                         if (rxq->rx_ring->rx_ring_struct->fw_ring_id == fwr)
1765                                 return rxq->index;
1766                 }
1767         } else {
1768                 for (i = 0; i < bp->rx_nr_rings; i++) {
1769                         if (bp->grp_info[i].fw_grp_id == fwr)
1770                                 return i;
1771                 }
1772         }
1773
1774         return INVALID_HW_RING_ID;
1775 }
1776
1777 static int bnxt_reta_update_op(struct rte_eth_dev *eth_dev,
1778                             struct rte_eth_rss_reta_entry64 *reta_conf,
1779                             uint16_t reta_size)
1780 {
1781         struct bnxt *bp = eth_dev->data->dev_private;
1782         struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
1783         struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp);
1784         uint16_t tbl_size = bnxt_rss_hash_tbl_size(bp);
1785         uint16_t idx, sft;
1786         int i, rc;
1787
1788         rc = is_bnxt_in_error(bp);
1789         if (rc)
1790                 return rc;
1791
1792         if (!vnic->rss_table)
1793                 return -EINVAL;
1794
1795         if (!(dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG))
1796                 return -EINVAL;
1797
1798         if (reta_size != tbl_size) {
1799                 PMD_DRV_LOG(ERR, "The configured hash table lookup size "
1800                         "(%d) must equal the size supported by the hardware "
1801                         "(%d)\n", reta_size, tbl_size);
1802                 return -EINVAL;
1803         }
1804
1805         for (i = 0; i < reta_size; i++) {
1806                 struct bnxt_rx_queue *rxq;
1807
1808                 idx = i / RTE_RETA_GROUP_SIZE;
1809                 sft = i % RTE_RETA_GROUP_SIZE;
1810
1811                 if (!(reta_conf[idx].mask & (1ULL << sft)))
1812                         continue;
1813
1814                 rxq = bnxt_qid_to_rxq(bp, reta_conf[idx].reta[sft]);
1815                 if (!rxq) {
1816                         PMD_DRV_LOG(ERR, "Invalid ring in reta_conf.\n");
1817                         return -EINVAL;
1818                 }
1819
1820                 if (BNXT_CHIP_THOR(bp)) {
1821                         vnic->rss_table[i * 2] =
1822                                 rxq->rx_ring->rx_ring_struct->fw_ring_id;
1823                         vnic->rss_table[i * 2 + 1] =
1824                                 rxq->cp_ring->cp_ring_struct->fw_ring_id;
1825                 } else {
1826                         vnic->rss_table[i] =
1827                             vnic->fw_grp_ids[reta_conf[idx].reta[sft]];
1828                 }
1829         }
1830
1831         bnxt_hwrm_vnic_rss_cfg(bp, vnic);
1832         return 0;
1833 }
1834
1835 static int bnxt_reta_query_op(struct rte_eth_dev *eth_dev,
1836                               struct rte_eth_rss_reta_entry64 *reta_conf,
1837                               uint16_t reta_size)
1838 {
1839         struct bnxt *bp = eth_dev->data->dev_private;
1840         struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp);
1841         uint16_t tbl_size = bnxt_rss_hash_tbl_size(bp);
1842         uint16_t idx, sft, i;
1843         int rc;
1844
1845         rc = is_bnxt_in_error(bp);
1846         if (rc)
1847                 return rc;
1848
1849         /* Retrieve from the default VNIC */
1850         if (!vnic)
1851                 return -EINVAL;
1852         if (!vnic->rss_table)
1853                 return -EINVAL;
1854
1855         if (reta_size != tbl_size) {
1856                 PMD_DRV_LOG(ERR, "The configured hash table lookup size "
1857                         "(%d) must equal the size supported by the hardware "
1858                         "(%d)\n", reta_size, tbl_size);
1859                 return -EINVAL;
1860         }
1861
1862         for (idx = 0, i = 0; i < reta_size; i++) {
1863                 idx = i / RTE_RETA_GROUP_SIZE;
1864                 sft = i % RTE_RETA_GROUP_SIZE;
1865
1866                 if (reta_conf[idx].mask & (1ULL << sft)) {
1867                         uint16_t qid;
1868
1869                         if (BNXT_CHIP_THOR(bp))
1870                                 qid = bnxt_rss_to_qid(bp,
1871                                                       vnic->rss_table[i * 2]);
1872                         else
1873                                 qid = bnxt_rss_to_qid(bp, vnic->rss_table[i]);
1874
1875                         if (qid == INVALID_HW_RING_ID) {
1876                                 PMD_DRV_LOG(ERR, "Inv. entry in rss table.\n");
1877                                 return -EINVAL;
1878                         }
1879                         reta_conf[idx].reta[sft] = qid;
1880                 }
1881         }
1882
1883         return 0;
1884 }
1885
1886 static int bnxt_rss_hash_update_op(struct rte_eth_dev *eth_dev,
1887                                    struct rte_eth_rss_conf *rss_conf)
1888 {
1889         struct bnxt *bp = eth_dev->data->dev_private;
1890         struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
1891         struct bnxt_vnic_info *vnic;
1892         int rc;
1893
1894         rc = is_bnxt_in_error(bp);
1895         if (rc)
1896                 return rc;
1897
1898         /*
1899          * If RSS enablement were different than dev_configure,
1900          * then return -EINVAL
1901          */
1902         if (dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG) {
1903                 if (!rss_conf->rss_hf)
1904                         PMD_DRV_LOG(ERR, "Hash type NONE\n");
1905         } else {
1906                 if (rss_conf->rss_hf & BNXT_ETH_RSS_SUPPORT)
1907                         return -EINVAL;
1908         }
1909
1910         bp->flags |= BNXT_FLAG_UPDATE_HASH;
1911         memcpy(&eth_dev->data->dev_conf.rx_adv_conf.rss_conf,
1912                rss_conf,
1913                sizeof(*rss_conf));
1914
1915         /* Update the default RSS VNIC(s) */
1916         vnic = BNXT_GET_DEFAULT_VNIC(bp);
1917         vnic->hash_type = bnxt_rte_to_hwrm_hash_types(rss_conf->rss_hf);
1918         vnic->hash_mode =
1919                 bnxt_rte_to_hwrm_hash_level(bp, rss_conf->rss_hf,
1920                                             ETH_RSS_LEVEL(rss_conf->rss_hf));
1921
1922         /*
1923          * If hashkey is not specified, use the previously configured
1924          * hashkey
1925          */
1926         if (!rss_conf->rss_key)
1927                 goto rss_config;
1928
1929         if (rss_conf->rss_key_len != HW_HASH_KEY_SIZE) {
1930                 PMD_DRV_LOG(ERR,
1931                             "Invalid hashkey length, should be 16 bytes\n");
1932                 return -EINVAL;
1933         }
1934         memcpy(vnic->rss_hash_key, rss_conf->rss_key, rss_conf->rss_key_len);
1935
1936 rss_config:
1937         bnxt_hwrm_vnic_rss_cfg(bp, vnic);
1938         return 0;
1939 }
1940
1941 static int bnxt_rss_hash_conf_get_op(struct rte_eth_dev *eth_dev,
1942                                      struct rte_eth_rss_conf *rss_conf)
1943 {
1944         struct bnxt *bp = eth_dev->data->dev_private;
1945         struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp);
1946         int len, rc;
1947         uint32_t hash_types;
1948
1949         rc = is_bnxt_in_error(bp);
1950         if (rc)
1951                 return rc;
1952
1953         /* RSS configuration is the same for all VNICs */
1954         if (vnic && vnic->rss_hash_key) {
1955                 if (rss_conf->rss_key) {
1956                         len = rss_conf->rss_key_len <= HW_HASH_KEY_SIZE ?
1957                               rss_conf->rss_key_len : HW_HASH_KEY_SIZE;
1958                         memcpy(rss_conf->rss_key, vnic->rss_hash_key, len);
1959                 }
1960
1961                 hash_types = vnic->hash_type;
1962                 rss_conf->rss_hf = 0;
1963                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV4) {
1964                         rss_conf->rss_hf |= ETH_RSS_IPV4;
1965                         hash_types &= ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV4;
1966                 }
1967                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV4) {
1968                         rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP;
1969                         hash_types &=
1970                                 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV4;
1971                 }
1972                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV4) {
1973                         rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
1974                         hash_types &=
1975                                 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV4;
1976                 }
1977                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6) {
1978                         rss_conf->rss_hf |= ETH_RSS_IPV6;
1979                         hash_types &= ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6;
1980                 }
1981                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV6) {
1982                         rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV6_TCP;
1983                         hash_types &=
1984                                 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV6;
1985                 }
1986                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV6) {
1987                         rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;
1988                         hash_types &=
1989                                 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV6;
1990                 }
1991
1992                 rss_conf->rss_hf |=
1993                         bnxt_hwrm_to_rte_rss_level(bp, vnic->hash_mode);
1994
1995                 if (hash_types) {
1996                         PMD_DRV_LOG(ERR,
1997                                 "Unknown RSS config from firmware (%08x), RSS disabled",
1998                                 vnic->hash_type);
1999                         return -ENOTSUP;
2000                 }
2001         } else {
2002                 rss_conf->rss_hf = 0;
2003         }
2004         return 0;
2005 }
2006
2007 static int bnxt_flow_ctrl_get_op(struct rte_eth_dev *dev,
2008                                struct rte_eth_fc_conf *fc_conf)
2009 {
2010         struct bnxt *bp = dev->data->dev_private;
2011         struct rte_eth_link link_info;
2012         int rc;
2013
2014         rc = is_bnxt_in_error(bp);
2015         if (rc)
2016                 return rc;
2017
2018         rc = bnxt_get_hwrm_link_config(bp, &link_info);
2019         if (rc)
2020                 return rc;
2021
2022         memset(fc_conf, 0, sizeof(*fc_conf));
2023         if (bp->link_info->auto_pause)
2024                 fc_conf->autoneg = 1;
2025         switch (bp->link_info->pause) {
2026         case 0:
2027                 fc_conf->mode = RTE_FC_NONE;
2028                 break;
2029         case HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_TX:
2030                 fc_conf->mode = RTE_FC_TX_PAUSE;
2031                 break;
2032         case HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_RX:
2033                 fc_conf->mode = RTE_FC_RX_PAUSE;
2034                 break;
2035         case (HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_TX |
2036                         HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_RX):
2037                 fc_conf->mode = RTE_FC_FULL;
2038                 break;
2039         }
2040         return 0;
2041 }
2042
2043 static int bnxt_flow_ctrl_set_op(struct rte_eth_dev *dev,
2044                                struct rte_eth_fc_conf *fc_conf)
2045 {
2046         struct bnxt *bp = dev->data->dev_private;
2047         int rc;
2048
2049         rc = is_bnxt_in_error(bp);
2050         if (rc)
2051                 return rc;
2052
2053         if (!BNXT_SINGLE_PF(bp) || BNXT_VF(bp)) {
2054                 PMD_DRV_LOG(ERR, "Flow Control Settings cannot be modified\n");
2055                 return -ENOTSUP;
2056         }
2057
2058         switch (fc_conf->mode) {
2059         case RTE_FC_NONE:
2060                 bp->link_info->auto_pause = 0;
2061                 bp->link_info->force_pause = 0;
2062                 break;
2063         case RTE_FC_RX_PAUSE:
2064                 if (fc_conf->autoneg) {
2065                         bp->link_info->auto_pause =
2066                                         HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_RX;
2067                         bp->link_info->force_pause = 0;
2068                 } else {
2069                         bp->link_info->auto_pause = 0;
2070                         bp->link_info->force_pause =
2071                                         HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_RX;
2072                 }
2073                 break;
2074         case RTE_FC_TX_PAUSE:
2075                 if (fc_conf->autoneg) {
2076                         bp->link_info->auto_pause =
2077                                         HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_TX;
2078                         bp->link_info->force_pause = 0;
2079                 } else {
2080                         bp->link_info->auto_pause = 0;
2081                         bp->link_info->force_pause =
2082                                         HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_TX;
2083                 }
2084                 break;
2085         case RTE_FC_FULL:
2086                 if (fc_conf->autoneg) {
2087                         bp->link_info->auto_pause =
2088                                         HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_TX |
2089                                         HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_RX;
2090                         bp->link_info->force_pause = 0;
2091                 } else {
2092                         bp->link_info->auto_pause = 0;
2093                         bp->link_info->force_pause =
2094                                         HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_TX |
2095                                         HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_RX;
2096                 }
2097                 break;
2098         }
2099         return bnxt_set_hwrm_link_config(bp, true);
2100 }
2101
2102 /* Add UDP tunneling port */
2103 static int
2104 bnxt_udp_tunnel_port_add_op(struct rte_eth_dev *eth_dev,
2105                          struct rte_eth_udp_tunnel *udp_tunnel)
2106 {
2107         struct bnxt *bp = eth_dev->data->dev_private;
2108         uint16_t tunnel_type = 0;
2109         int rc = 0;
2110
2111         rc = is_bnxt_in_error(bp);
2112         if (rc)
2113                 return rc;
2114
2115         switch (udp_tunnel->prot_type) {
2116         case RTE_TUNNEL_TYPE_VXLAN:
2117                 if (bp->vxlan_port_cnt) {
2118                         PMD_DRV_LOG(ERR, "Tunnel Port %d already programmed\n",
2119                                 udp_tunnel->udp_port);
2120                         if (bp->vxlan_port != udp_tunnel->udp_port) {
2121                                 PMD_DRV_LOG(ERR, "Only one port allowed\n");
2122                                 return -ENOSPC;
2123                         }
2124                         bp->vxlan_port_cnt++;
2125                         return 0;
2126                 }
2127                 tunnel_type =
2128                         HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_VXLAN;
2129                 bp->vxlan_port_cnt++;
2130                 break;
2131         case RTE_TUNNEL_TYPE_GENEVE:
2132                 if (bp->geneve_port_cnt) {
2133                         PMD_DRV_LOG(ERR, "Tunnel Port %d already programmed\n",
2134                                 udp_tunnel->udp_port);
2135                         if (bp->geneve_port != udp_tunnel->udp_port) {
2136                                 PMD_DRV_LOG(ERR, "Only one port allowed\n");
2137                                 return -ENOSPC;
2138                         }
2139                         bp->geneve_port_cnt++;
2140                         return 0;
2141                 }
2142                 tunnel_type =
2143                         HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_GENEVE;
2144                 bp->geneve_port_cnt++;
2145                 break;
2146         default:
2147                 PMD_DRV_LOG(ERR, "Tunnel type is not supported\n");
2148                 return -ENOTSUP;
2149         }
2150         rc = bnxt_hwrm_tunnel_dst_port_alloc(bp, udp_tunnel->udp_port,
2151                                              tunnel_type);
2152         return rc;
2153 }
2154
2155 static int
2156 bnxt_udp_tunnel_port_del_op(struct rte_eth_dev *eth_dev,
2157                          struct rte_eth_udp_tunnel *udp_tunnel)
2158 {
2159         struct bnxt *bp = eth_dev->data->dev_private;
2160         uint16_t tunnel_type = 0;
2161         uint16_t port = 0;
2162         int rc = 0;
2163
2164         rc = is_bnxt_in_error(bp);
2165         if (rc)
2166                 return rc;
2167
2168         switch (udp_tunnel->prot_type) {
2169         case RTE_TUNNEL_TYPE_VXLAN:
2170                 if (!bp->vxlan_port_cnt) {
2171                         PMD_DRV_LOG(ERR, "No Tunnel port configured yet\n");
2172                         return -EINVAL;
2173                 }
2174                 if (bp->vxlan_port != udp_tunnel->udp_port) {
2175                         PMD_DRV_LOG(ERR, "Req Port: %d. Configured port: %d\n",
2176                                 udp_tunnel->udp_port, bp->vxlan_port);
2177                         return -EINVAL;
2178                 }
2179                 if (--bp->vxlan_port_cnt)
2180                         return 0;
2181
2182                 tunnel_type =
2183                         HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN;
2184                 port = bp->vxlan_fw_dst_port_id;
2185                 break;
2186         case RTE_TUNNEL_TYPE_GENEVE:
2187                 if (!bp->geneve_port_cnt) {
2188                         PMD_DRV_LOG(ERR, "No Tunnel port configured yet\n");
2189                         return -EINVAL;
2190                 }
2191                 if (bp->geneve_port != udp_tunnel->udp_port) {
2192                         PMD_DRV_LOG(ERR, "Req Port: %d. Configured port: %d\n",
2193                                 udp_tunnel->udp_port, bp->geneve_port);
2194                         return -EINVAL;
2195                 }
2196                 if (--bp->geneve_port_cnt)
2197                         return 0;
2198
2199                 tunnel_type =
2200                         HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_GENEVE;
2201                 port = bp->geneve_fw_dst_port_id;
2202                 break;
2203         default:
2204                 PMD_DRV_LOG(ERR, "Tunnel type is not supported\n");
2205                 return -ENOTSUP;
2206         }
2207
2208         rc = bnxt_hwrm_tunnel_dst_port_free(bp, port, tunnel_type);
2209         return rc;
2210 }
2211
2212 static int bnxt_del_vlan_filter(struct bnxt *bp, uint16_t vlan_id)
2213 {
2214         struct bnxt_filter_info *filter;
2215         struct bnxt_vnic_info *vnic;
2216         int rc = 0;
2217         uint32_t chk = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN;
2218
2219         vnic = BNXT_GET_DEFAULT_VNIC(bp);
2220         filter = STAILQ_FIRST(&vnic->filter);
2221         while (filter) {
2222                 /* Search for this matching MAC+VLAN filter */
2223                 if (bnxt_vlan_filter_exists(bp, filter, chk, vlan_id)) {
2224                         /* Delete the filter */
2225                         rc = bnxt_hwrm_clear_l2_filter(bp, filter);
2226                         if (rc)
2227                                 return rc;
2228                         STAILQ_REMOVE(&vnic->filter, filter,
2229                                       bnxt_filter_info, next);
2230                         bnxt_free_filter(bp, filter);
2231                         PMD_DRV_LOG(INFO,
2232                                     "Deleted vlan filter for %d\n",
2233                                     vlan_id);
2234                         return 0;
2235                 }
2236                 filter = STAILQ_NEXT(filter, next);
2237         }
2238         return -ENOENT;
2239 }
2240
2241 static int bnxt_add_vlan_filter(struct bnxt *bp, uint16_t vlan_id)
2242 {
2243         struct bnxt_filter_info *filter;
2244         struct bnxt_vnic_info *vnic;
2245         int rc = 0;
2246         uint32_t en = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN |
2247                 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN_MASK;
2248         uint32_t chk = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN;
2249
2250         /* Implementation notes on the use of VNIC in this command:
2251          *
2252          * By default, these filters belong to default vnic for the function.
2253          * Once these filters are set up, only destination VNIC can be modified.
2254          * If the destination VNIC is not specified in this command,
2255          * then the HWRM shall only create an l2 context id.
2256          */
2257
2258         vnic = BNXT_GET_DEFAULT_VNIC(bp);
2259         filter = STAILQ_FIRST(&vnic->filter);
2260         /* Check if the VLAN has already been added */
2261         while (filter) {
2262                 if (bnxt_vlan_filter_exists(bp, filter, chk, vlan_id))
2263                         return -EEXIST;
2264
2265                 filter = STAILQ_NEXT(filter, next);
2266         }
2267
2268         /* No match found. Alloc a fresh filter and issue the L2_FILTER_ALLOC
2269          * command to create MAC+VLAN filter with the right flags, enables set.
2270          */
2271         filter = bnxt_alloc_filter(bp);
2272         if (!filter) {
2273                 PMD_DRV_LOG(ERR,
2274                             "MAC/VLAN filter alloc failed\n");
2275                 return -ENOMEM;
2276         }
2277         /* MAC + VLAN ID filter */
2278         /* If l2_ivlan == 0 and l2_ivlan_mask != 0, only
2279          * untagged packets are received
2280          *
2281          * If l2_ivlan != 0 and l2_ivlan_mask != 0, untagged
2282          * packets and only the programmed vlan's packets are received
2283          */
2284         filter->l2_ivlan = vlan_id;
2285         filter->l2_ivlan_mask = 0x0FFF;
2286         filter->enables |= en;
2287         filter->flags |= HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_OUTERMOST;
2288
2289         rc = bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id, filter);
2290         if (rc) {
2291                 /* Free the newly allocated filter as we were
2292                  * not able to create the filter in hardware.
2293                  */
2294                 bnxt_free_filter(bp, filter);
2295                 return rc;
2296         }
2297
2298         filter->mac_index = 0;
2299         /* Add this new filter to the list */
2300         if (vlan_id == 0)
2301                 STAILQ_INSERT_HEAD(&vnic->filter, filter, next);
2302         else
2303                 STAILQ_INSERT_TAIL(&vnic->filter, filter, next);
2304
2305         PMD_DRV_LOG(INFO,
2306                     "Added Vlan filter for %d\n", vlan_id);
2307         return rc;
2308 }
2309
2310 static int bnxt_vlan_filter_set_op(struct rte_eth_dev *eth_dev,
2311                 uint16_t vlan_id, int on)
2312 {
2313         struct bnxt *bp = eth_dev->data->dev_private;
2314         int rc;
2315
2316         rc = is_bnxt_in_error(bp);
2317         if (rc)
2318                 return rc;
2319
2320         if (!eth_dev->data->dev_started) {
2321                 PMD_DRV_LOG(ERR, "port must be started before setting vlan\n");
2322                 return -EINVAL;
2323         }
2324
2325         /* These operations apply to ALL existing MAC/VLAN filters */
2326         if (on)
2327                 return bnxt_add_vlan_filter(bp, vlan_id);
2328         else
2329                 return bnxt_del_vlan_filter(bp, vlan_id);
2330 }
2331
2332 static int bnxt_del_dflt_mac_filter(struct bnxt *bp,
2333                                     struct bnxt_vnic_info *vnic)
2334 {
2335         struct bnxt_filter_info *filter;
2336         int rc;
2337
2338         filter = STAILQ_FIRST(&vnic->filter);
2339         while (filter) {
2340                 if (filter->mac_index == 0 &&
2341                     !memcmp(filter->l2_addr, bp->mac_addr,
2342                             RTE_ETHER_ADDR_LEN)) {
2343                         rc = bnxt_hwrm_clear_l2_filter(bp, filter);
2344                         if (!rc) {
2345                                 STAILQ_REMOVE(&vnic->filter, filter,
2346                                               bnxt_filter_info, next);
2347                                 bnxt_free_filter(bp, filter);
2348                         }
2349                         return rc;
2350                 }
2351                 filter = STAILQ_NEXT(filter, next);
2352         }
2353         return 0;
2354 }
2355
2356 static int
2357 bnxt_config_vlan_hw_filter(struct bnxt *bp, uint64_t rx_offloads)
2358 {
2359         struct bnxt_vnic_info *vnic;
2360         unsigned int i;
2361         int rc;
2362
2363         vnic = BNXT_GET_DEFAULT_VNIC(bp);
2364         if (!(rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER)) {
2365                 /* Remove any VLAN filters programmed */
2366                 for (i = 0; i < RTE_ETHER_MAX_VLAN_ID; i++)
2367                         bnxt_del_vlan_filter(bp, i);
2368
2369                 rc = bnxt_add_mac_filter(bp, vnic, NULL, 0, 0);
2370                 if (rc)
2371                         return rc;
2372         } else {
2373                 /* Default filter will allow packets that match the
2374                  * dest mac. So, it has to be deleted, otherwise, we
2375                  * will endup receiving vlan packets for which the
2376                  * filter is not programmed, when hw-vlan-filter
2377                  * configuration is ON
2378                  */
2379                 bnxt_del_dflt_mac_filter(bp, vnic);
2380                 /* This filter will allow only untagged packets */
2381                 bnxt_add_vlan_filter(bp, 0);
2382         }
2383         PMD_DRV_LOG(DEBUG, "VLAN Filtering: %d\n",
2384                     !!(rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER));
2385
2386         return 0;
2387 }
2388
2389 static int bnxt_free_one_vnic(struct bnxt *bp, uint16_t vnic_id)
2390 {
2391         struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id];
2392         unsigned int i;
2393         int rc;
2394
2395         /* Destroy vnic filters and vnic */
2396         if (bp->eth_dev->data->dev_conf.rxmode.offloads &
2397             DEV_RX_OFFLOAD_VLAN_FILTER) {
2398                 for (i = 0; i < RTE_ETHER_MAX_VLAN_ID; i++)
2399                         bnxt_del_vlan_filter(bp, i);
2400         }
2401         bnxt_del_dflt_mac_filter(bp, vnic);
2402
2403         rc = bnxt_hwrm_vnic_free(bp, vnic);
2404         if (rc)
2405                 return rc;
2406
2407         rte_free(vnic->fw_grp_ids);
2408         vnic->fw_grp_ids = NULL;
2409
2410         vnic->rx_queue_cnt = 0;
2411
2412         return 0;
2413 }
2414
2415 static int
2416 bnxt_config_vlan_hw_stripping(struct bnxt *bp, uint64_t rx_offloads)
2417 {
2418         struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp);
2419         int rc;
2420
2421         /* Destroy, recreate and reconfigure the default vnic */
2422         rc = bnxt_free_one_vnic(bp, 0);
2423         if (rc)
2424                 return rc;
2425
2426         /* default vnic 0 */
2427         rc = bnxt_setup_one_vnic(bp, 0);
2428         if (rc)
2429                 return rc;
2430
2431         if (bp->eth_dev->data->dev_conf.rxmode.offloads &
2432             DEV_RX_OFFLOAD_VLAN_FILTER) {
2433                 rc = bnxt_add_vlan_filter(bp, 0);
2434                 if (rc)
2435                         return rc;
2436                 rc = bnxt_restore_vlan_filters(bp);
2437                 if (rc)
2438                         return rc;
2439         } else {
2440                 rc = bnxt_add_mac_filter(bp, vnic, NULL, 0, 0);
2441                 if (rc)
2442                         return rc;
2443         }
2444
2445         rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
2446         if (rc)
2447                 return rc;
2448
2449         PMD_DRV_LOG(DEBUG, "VLAN Strip Offload: %d\n",
2450                     !!(rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP));
2451
2452         return rc;
2453 }
2454
2455 static int
2456 bnxt_vlan_offload_set_op(struct rte_eth_dev *dev, int mask)
2457 {
2458         uint64_t rx_offloads = dev->data->dev_conf.rxmode.offloads;
2459         struct bnxt *bp = dev->data->dev_private;
2460         int rc;
2461
2462         rc = is_bnxt_in_error(bp);
2463         if (rc)
2464                 return rc;
2465
2466         /* Filter settings will get applied when port is started */
2467         if (!dev->data->dev_started)
2468                 return 0;
2469
2470         if (mask & ETH_VLAN_FILTER_MASK) {
2471                 /* Enable or disable VLAN filtering */
2472                 rc = bnxt_config_vlan_hw_filter(bp, rx_offloads);
2473                 if (rc)
2474                         return rc;
2475         }
2476
2477         if (mask & ETH_VLAN_STRIP_MASK) {
2478                 /* Enable or disable VLAN stripping */
2479                 rc = bnxt_config_vlan_hw_stripping(bp, rx_offloads);
2480                 if (rc)
2481                         return rc;
2482         }
2483
2484         if (mask & ETH_VLAN_EXTEND_MASK) {
2485                 if (rx_offloads & DEV_RX_OFFLOAD_VLAN_EXTEND)
2486                         PMD_DRV_LOG(DEBUG, "Extend VLAN supported\n");
2487                 else
2488                         PMD_DRV_LOG(INFO, "Extend VLAN unsupported\n");
2489         }
2490
2491         return 0;
2492 }
2493
2494 static int
2495 bnxt_vlan_tpid_set_op(struct rte_eth_dev *dev, enum rte_vlan_type vlan_type,
2496                       uint16_t tpid)
2497 {
2498         struct bnxt *bp = dev->data->dev_private;
2499         int qinq = dev->data->dev_conf.rxmode.offloads &
2500                    DEV_RX_OFFLOAD_VLAN_EXTEND;
2501
2502         if (vlan_type != ETH_VLAN_TYPE_INNER &&
2503             vlan_type != ETH_VLAN_TYPE_OUTER) {
2504                 PMD_DRV_LOG(ERR,
2505                             "Unsupported vlan type.");
2506                 return -EINVAL;
2507         }
2508         if (!qinq) {
2509                 PMD_DRV_LOG(ERR,
2510                             "QinQ not enabled. Needs to be ON as we can "
2511                             "accelerate only outer vlan\n");
2512                 return -EINVAL;
2513         }
2514
2515         if (vlan_type == ETH_VLAN_TYPE_OUTER) {
2516                 switch (tpid) {
2517                 case RTE_ETHER_TYPE_QINQ:
2518                         bp->outer_tpid_bd =
2519                                 TX_BD_LONG_CFA_META_VLAN_TPID_TPID88A8;
2520                                 break;
2521                 case RTE_ETHER_TYPE_VLAN:
2522                         bp->outer_tpid_bd =
2523                                 TX_BD_LONG_CFA_META_VLAN_TPID_TPID8100;
2524                                 break;
2525                 case RTE_ETHER_TYPE_QINQ1:
2526                         bp->outer_tpid_bd =
2527                                 TX_BD_LONG_CFA_META_VLAN_TPID_TPID9100;
2528                                 break;
2529                 case RTE_ETHER_TYPE_QINQ2:
2530                         bp->outer_tpid_bd =
2531                                 TX_BD_LONG_CFA_META_VLAN_TPID_TPID9200;
2532                                 break;
2533                 case RTE_ETHER_TYPE_QINQ3:
2534                         bp->outer_tpid_bd =
2535                                  TX_BD_LONG_CFA_META_VLAN_TPID_TPID9300;
2536                                 break;
2537                 default:
2538                         PMD_DRV_LOG(ERR, "Invalid TPID: %x\n", tpid);
2539                         return -EINVAL;
2540                 }
2541                 bp->outer_tpid_bd |= tpid;
2542                 PMD_DRV_LOG(INFO, "outer_tpid_bd = %x\n", bp->outer_tpid_bd);
2543         } else if (vlan_type == ETH_VLAN_TYPE_INNER) {
2544                 PMD_DRV_LOG(ERR,
2545                             "Can accelerate only outer vlan in QinQ\n");
2546                 return -EINVAL;
2547         }
2548
2549         return 0;
2550 }
2551
2552 static int
2553 bnxt_set_default_mac_addr_op(struct rte_eth_dev *dev,
2554                              struct rte_ether_addr *addr)
2555 {
2556         struct bnxt *bp = dev->data->dev_private;
2557         /* Default Filter is tied to VNIC 0 */
2558         struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp);
2559         int rc;
2560
2561         rc = is_bnxt_in_error(bp);
2562         if (rc)
2563                 return rc;
2564
2565         if (BNXT_VF(bp) && !BNXT_VF_IS_TRUSTED(bp))
2566                 return -EPERM;
2567
2568         if (rte_is_zero_ether_addr(addr))
2569                 return -EINVAL;
2570
2571         /* Filter settings will get applied when port is started */
2572         if (!dev->data->dev_started)
2573                 return 0;
2574
2575         /* Check if the requested MAC is already added */
2576         if (memcmp(addr, bp->mac_addr, RTE_ETHER_ADDR_LEN) == 0)
2577                 return 0;
2578
2579         /* Destroy filter and re-create it */
2580         bnxt_del_dflt_mac_filter(bp, vnic);
2581
2582         memcpy(bp->mac_addr, addr, RTE_ETHER_ADDR_LEN);
2583         if (dev->data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_VLAN_FILTER) {
2584                 /* This filter will allow only untagged packets */
2585                 rc = bnxt_add_vlan_filter(bp, 0);
2586         } else {
2587                 rc = bnxt_add_mac_filter(bp, vnic, addr, 0, 0);
2588         }
2589
2590         PMD_DRV_LOG(DEBUG, "Set MAC addr\n");
2591         return rc;
2592 }
2593
2594 static int
2595 bnxt_dev_set_mc_addr_list_op(struct rte_eth_dev *eth_dev,
2596                           struct rte_ether_addr *mc_addr_set,
2597                           uint32_t nb_mc_addr)
2598 {
2599         struct bnxt *bp = eth_dev->data->dev_private;
2600         char *mc_addr_list = (char *)mc_addr_set;
2601         struct bnxt_vnic_info *vnic;
2602         uint32_t off = 0, i = 0;
2603         int rc;
2604
2605         rc = is_bnxt_in_error(bp);
2606         if (rc)
2607                 return rc;
2608
2609         vnic = BNXT_GET_DEFAULT_VNIC(bp);
2610
2611         if (nb_mc_addr > BNXT_MAX_MC_ADDRS) {
2612                 vnic->flags |= BNXT_VNIC_INFO_ALLMULTI;
2613                 goto allmulti;
2614         }
2615
2616         /* TODO Check for Duplicate mcast addresses */
2617         vnic->flags &= ~BNXT_VNIC_INFO_ALLMULTI;
2618         for (i = 0; i < nb_mc_addr; i++) {
2619                 memcpy(vnic->mc_list + off, &mc_addr_list[i],
2620                         RTE_ETHER_ADDR_LEN);
2621                 off += RTE_ETHER_ADDR_LEN;
2622         }
2623
2624         vnic->mc_addr_cnt = i;
2625         if (vnic->mc_addr_cnt)
2626                 vnic->flags |= BNXT_VNIC_INFO_MCAST;
2627         else
2628                 vnic->flags &= ~BNXT_VNIC_INFO_MCAST;
2629
2630 allmulti:
2631         return bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
2632 }
2633
2634 static int
2635 bnxt_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size)
2636 {
2637         struct bnxt *bp = dev->data->dev_private;
2638         uint8_t fw_major = (bp->fw_ver >> 24) & 0xff;
2639         uint8_t fw_minor = (bp->fw_ver >> 16) & 0xff;
2640         uint8_t fw_updt = (bp->fw_ver >> 8) & 0xff;
2641         uint8_t fw_rsvd = bp->fw_ver & 0xff;
2642         int ret;
2643
2644         ret = snprintf(fw_version, fw_size, "%d.%d.%d.%d",
2645                         fw_major, fw_minor, fw_updt, fw_rsvd);
2646
2647         ret += 1; /* add the size of '\0' */
2648         if (fw_size < (uint32_t)ret)
2649                 return ret;
2650         else
2651                 return 0;
2652 }
2653
2654 static void
2655 bnxt_rxq_info_get_op(struct rte_eth_dev *dev, uint16_t queue_id,
2656         struct rte_eth_rxq_info *qinfo)
2657 {
2658         struct bnxt *bp = dev->data->dev_private;
2659         struct bnxt_rx_queue *rxq;
2660
2661         if (is_bnxt_in_error(bp))
2662                 return;
2663
2664         rxq = dev->data->rx_queues[queue_id];
2665
2666         qinfo->mp = rxq->mb_pool;
2667         qinfo->scattered_rx = dev->data->scattered_rx;
2668         qinfo->nb_desc = rxq->nb_rx_desc;
2669
2670         qinfo->conf.rx_free_thresh = rxq->rx_free_thresh;
2671         qinfo->conf.rx_drop_en = rxq->drop_en;
2672         qinfo->conf.rx_deferred_start = rxq->rx_deferred_start;
2673         qinfo->conf.offloads = dev->data->dev_conf.rxmode.offloads;
2674 }
2675
2676 static void
2677 bnxt_txq_info_get_op(struct rte_eth_dev *dev, uint16_t queue_id,
2678         struct rte_eth_txq_info *qinfo)
2679 {
2680         struct bnxt *bp = dev->data->dev_private;
2681         struct bnxt_tx_queue *txq;
2682
2683         if (is_bnxt_in_error(bp))
2684                 return;
2685
2686         txq = dev->data->tx_queues[queue_id];
2687
2688         qinfo->nb_desc = txq->nb_tx_desc;
2689
2690         qinfo->conf.tx_thresh.pthresh = txq->pthresh;
2691         qinfo->conf.tx_thresh.hthresh = txq->hthresh;
2692         qinfo->conf.tx_thresh.wthresh = txq->wthresh;
2693
2694         qinfo->conf.tx_free_thresh = txq->tx_free_thresh;
2695         qinfo->conf.tx_rs_thresh = 0;
2696         qinfo->conf.tx_deferred_start = txq->tx_deferred_start;
2697         qinfo->conf.offloads = txq->offloads;
2698 }
2699
2700 static const struct {
2701         eth_rx_burst_t pkt_burst;
2702         const char *info;
2703 } bnxt_rx_burst_info[] = {
2704         {bnxt_recv_pkts,        "Scalar"},
2705 #if defined(RTE_ARCH_X86)
2706         {bnxt_recv_pkts_vec,    "Vector SSE"},
2707 #elif defined(RTE_ARCH_ARM64)
2708         {bnxt_recv_pkts_vec,    "Vector Neon"},
2709 #endif
2710 };
2711
2712 static int
2713 bnxt_rx_burst_mode_get(struct rte_eth_dev *dev, __rte_unused uint16_t queue_id,
2714                        struct rte_eth_burst_mode *mode)
2715 {
2716         eth_rx_burst_t pkt_burst = dev->rx_pkt_burst;
2717         size_t i;
2718
2719         for (i = 0; i < RTE_DIM(bnxt_rx_burst_info); i++) {
2720                 if (pkt_burst == bnxt_rx_burst_info[i].pkt_burst) {
2721                         snprintf(mode->info, sizeof(mode->info), "%s",
2722                                  bnxt_rx_burst_info[i].info);
2723                         return 0;
2724                 }
2725         }
2726
2727         return -EINVAL;
2728 }
2729
2730 static const struct {
2731         eth_tx_burst_t pkt_burst;
2732         const char *info;
2733 } bnxt_tx_burst_info[] = {
2734         {bnxt_xmit_pkts,        "Scalar"},
2735 #if defined(RTE_ARCH_X86)
2736         {bnxt_xmit_pkts_vec,    "Vector SSE"},
2737 #elif defined(RTE_ARCH_ARM64)
2738         {bnxt_xmit_pkts_vec,    "Vector Neon"},
2739 #endif
2740 };
2741
2742 static int
2743 bnxt_tx_burst_mode_get(struct rte_eth_dev *dev, __rte_unused uint16_t queue_id,
2744                        struct rte_eth_burst_mode *mode)
2745 {
2746         eth_tx_burst_t pkt_burst = dev->tx_pkt_burst;
2747         size_t i;
2748
2749         for (i = 0; i < RTE_DIM(bnxt_tx_burst_info); i++) {
2750                 if (pkt_burst == bnxt_tx_burst_info[i].pkt_burst) {
2751                         snprintf(mode->info, sizeof(mode->info), "%s",
2752                                  bnxt_tx_burst_info[i].info);
2753                         return 0;
2754                 }
2755         }
2756
2757         return -EINVAL;
2758 }
2759
2760 int bnxt_mtu_set_op(struct rte_eth_dev *eth_dev, uint16_t new_mtu)
2761 {
2762         struct bnxt *bp = eth_dev->data->dev_private;
2763         uint32_t new_pkt_size;
2764         uint32_t rc = 0;
2765         uint32_t i;
2766
2767         rc = is_bnxt_in_error(bp);
2768         if (rc)
2769                 return rc;
2770
2771         /* Exit if receive queues are not configured yet */
2772         if (!eth_dev->data->nb_rx_queues)
2773                 return rc;
2774
2775         new_pkt_size = new_mtu + RTE_ETHER_HDR_LEN + RTE_ETHER_CRC_LEN +
2776                        VLAN_TAG_SIZE * BNXT_NUM_VLANS;
2777
2778         /*
2779          * Disallow any MTU change that would require scattered receive support
2780          * if it is not already enabled.
2781          */
2782         if (eth_dev->data->dev_started &&
2783             !eth_dev->data->scattered_rx &&
2784             (new_pkt_size >
2785              eth_dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM)) {
2786                 PMD_DRV_LOG(ERR,
2787                             "MTU change would require scattered rx support. ");
2788                 PMD_DRV_LOG(ERR, "Stop port before changing MTU.\n");
2789                 return -EINVAL;
2790         }
2791
2792         if (new_mtu > RTE_ETHER_MTU) {
2793                 bp->flags |= BNXT_FLAG_JUMBO;
2794                 bp->eth_dev->data->dev_conf.rxmode.offloads |=
2795                         DEV_RX_OFFLOAD_JUMBO_FRAME;
2796         } else {
2797                 bp->eth_dev->data->dev_conf.rxmode.offloads &=
2798                         ~DEV_RX_OFFLOAD_JUMBO_FRAME;
2799                 bp->flags &= ~BNXT_FLAG_JUMBO;
2800         }
2801
2802         /* Is there a change in mtu setting? */
2803         if (eth_dev->data->dev_conf.rxmode.max_rx_pkt_len == new_pkt_size)
2804                 return rc;
2805
2806         for (i = 0; i < bp->nr_vnics; i++) {
2807                 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
2808                 uint16_t size = 0;
2809
2810                 vnic->mru = BNXT_VNIC_MRU(new_mtu);
2811                 rc = bnxt_hwrm_vnic_cfg(bp, vnic);
2812                 if (rc)
2813                         break;
2814
2815                 size = rte_pktmbuf_data_room_size(bp->rx_queues[0]->mb_pool);
2816                 size -= RTE_PKTMBUF_HEADROOM;
2817
2818                 if (size < new_mtu) {
2819                         rc = bnxt_hwrm_vnic_plcmode_cfg(bp, vnic);
2820                         if (rc)
2821                                 return rc;
2822                 }
2823         }
2824
2825         if (!rc)
2826                 eth_dev->data->dev_conf.rxmode.max_rx_pkt_len = new_pkt_size;
2827
2828         PMD_DRV_LOG(INFO, "New MTU is %d\n", new_mtu);
2829
2830         return rc;
2831 }
2832
2833 static int
2834 bnxt_vlan_pvid_set_op(struct rte_eth_dev *dev, uint16_t pvid, int on)
2835 {
2836         struct bnxt *bp = dev->data->dev_private;
2837         uint16_t vlan = bp->vlan;
2838         int rc;
2839
2840         rc = is_bnxt_in_error(bp);
2841         if (rc)
2842                 return rc;
2843
2844         if (!BNXT_SINGLE_PF(bp) || BNXT_VF(bp)) {
2845                 PMD_DRV_LOG(ERR,
2846                         "PVID cannot be modified for this function\n");
2847                 return -ENOTSUP;
2848         }
2849         bp->vlan = on ? pvid : 0;
2850
2851         rc = bnxt_hwrm_set_default_vlan(bp, 0, 0);
2852         if (rc)
2853                 bp->vlan = vlan;
2854         return rc;
2855 }
2856
2857 static int
2858 bnxt_dev_led_on_op(struct rte_eth_dev *dev)
2859 {
2860         struct bnxt *bp = dev->data->dev_private;
2861         int rc;
2862
2863         rc = is_bnxt_in_error(bp);
2864         if (rc)
2865                 return rc;
2866
2867         return bnxt_hwrm_port_led_cfg(bp, true);
2868 }
2869
2870 static int
2871 bnxt_dev_led_off_op(struct rte_eth_dev *dev)
2872 {
2873         struct bnxt *bp = dev->data->dev_private;
2874         int rc;
2875
2876         rc = is_bnxt_in_error(bp);
2877         if (rc)
2878                 return rc;
2879
2880         return bnxt_hwrm_port_led_cfg(bp, false);
2881 }
2882
2883 static uint32_t
2884 bnxt_rx_queue_count_op(struct rte_eth_dev *dev, uint16_t rx_queue_id)
2885 {
2886         struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
2887         uint32_t desc = 0, raw_cons = 0, cons;
2888         struct bnxt_cp_ring_info *cpr;
2889         struct bnxt_rx_queue *rxq;
2890         struct rx_pkt_cmpl *rxcmp;
2891         int rc;
2892
2893         rc = is_bnxt_in_error(bp);
2894         if (rc)
2895                 return rc;
2896
2897         rxq = dev->data->rx_queues[rx_queue_id];
2898         cpr = rxq->cp_ring;
2899         raw_cons = cpr->cp_raw_cons;
2900
2901         while (1) {
2902                 cons = RING_CMP(cpr->cp_ring_struct, raw_cons);
2903                 rte_prefetch0(&cpr->cp_desc_ring[cons]);
2904                 rxcmp = (struct rx_pkt_cmpl *)&cpr->cp_desc_ring[cons];
2905
2906                 if (!CMP_VALID(rxcmp, raw_cons, cpr->cp_ring_struct)) {
2907                         break;
2908                 } else {
2909                         raw_cons++;
2910                         desc++;
2911                 }
2912         }
2913
2914         return desc;
2915 }
2916
2917 static int
2918 bnxt_rx_descriptor_status_op(void *rx_queue, uint16_t offset)
2919 {
2920         struct bnxt_rx_queue *rxq = (struct bnxt_rx_queue *)rx_queue;
2921         struct bnxt_rx_ring_info *rxr;
2922         struct bnxt_cp_ring_info *cpr;
2923         struct rte_mbuf *rx_buf;
2924         struct rx_pkt_cmpl *rxcmp;
2925         uint32_t cons, cp_cons;
2926         int rc;
2927
2928         if (!rxq)
2929                 return -EINVAL;
2930
2931         rc = is_bnxt_in_error(rxq->bp);
2932         if (rc)
2933                 return rc;
2934
2935         cpr = rxq->cp_ring;
2936         rxr = rxq->rx_ring;
2937
2938         if (offset >= rxq->nb_rx_desc)
2939                 return -EINVAL;
2940
2941         cons = RING_CMP(cpr->cp_ring_struct, offset);
2942         cp_cons = cpr->cp_raw_cons;
2943         rxcmp = (struct rx_pkt_cmpl *)&cpr->cp_desc_ring[cons];
2944
2945         if (cons > cp_cons) {
2946                 if (CMPL_VALID(rxcmp, cpr->valid))
2947                         return RTE_ETH_RX_DESC_DONE;
2948         } else {
2949                 if (CMPL_VALID(rxcmp, !cpr->valid))
2950                         return RTE_ETH_RX_DESC_DONE;
2951         }
2952         rx_buf = rxr->rx_buf_ring[cons];
2953         if (rx_buf == NULL || rx_buf == &rxq->fake_mbuf)
2954                 return RTE_ETH_RX_DESC_UNAVAIL;
2955
2956
2957         return RTE_ETH_RX_DESC_AVAIL;
2958 }
2959
2960 static int
2961 bnxt_tx_descriptor_status_op(void *tx_queue, uint16_t offset)
2962 {
2963         struct bnxt_tx_queue *txq = (struct bnxt_tx_queue *)tx_queue;
2964         struct bnxt_tx_ring_info *txr;
2965         struct bnxt_cp_ring_info *cpr;
2966         struct bnxt_sw_tx_bd *tx_buf;
2967         struct tx_pkt_cmpl *txcmp;
2968         uint32_t cons, cp_cons;
2969         int rc;
2970
2971         if (!txq)
2972                 return -EINVAL;
2973
2974         rc = is_bnxt_in_error(txq->bp);
2975         if (rc)
2976                 return rc;
2977
2978         cpr = txq->cp_ring;
2979         txr = txq->tx_ring;
2980
2981         if (offset >= txq->nb_tx_desc)
2982                 return -EINVAL;
2983
2984         cons = RING_CMP(cpr->cp_ring_struct, offset);
2985         txcmp = (struct tx_pkt_cmpl *)&cpr->cp_desc_ring[cons];
2986         cp_cons = cpr->cp_raw_cons;
2987
2988         if (cons > cp_cons) {
2989                 if (CMPL_VALID(txcmp, cpr->valid))
2990                         return RTE_ETH_TX_DESC_UNAVAIL;
2991         } else {
2992                 if (CMPL_VALID(txcmp, !cpr->valid))
2993                         return RTE_ETH_TX_DESC_UNAVAIL;
2994         }
2995         tx_buf = &txr->tx_buf_ring[cons];
2996         if (tx_buf->mbuf == NULL)
2997                 return RTE_ETH_TX_DESC_DONE;
2998
2999         return RTE_ETH_TX_DESC_FULL;
3000 }
3001
3002 int
3003 bnxt_filter_ctrl_op(struct rte_eth_dev *dev,
3004                     enum rte_filter_type filter_type,
3005                     enum rte_filter_op filter_op, void *arg)
3006 {
3007         struct bnxt *bp = dev->data->dev_private;
3008         int ret = 0;
3009
3010         if (!bp)
3011                 return -EIO;
3012
3013         if (BNXT_ETH_DEV_IS_REPRESENTOR(dev)) {
3014                 struct bnxt_representor *vfr = dev->data->dev_private;
3015                 bp = vfr->parent_dev->data->dev_private;
3016                 /* parent is deleted while children are still valid */
3017                 if (!bp) {
3018                         PMD_DRV_LOG(DEBUG, "BNXT Port:%d VFR Error %d:%d\n",
3019                                     dev->data->port_id,
3020                                     filter_type,
3021                                     filter_op);
3022                         return -EIO;
3023                 }
3024         }
3025
3026         ret = is_bnxt_in_error(bp);
3027         if (ret)
3028                 return ret;
3029
3030         switch (filter_type) {
3031         case RTE_ETH_FILTER_GENERIC:
3032                 if (filter_op != RTE_ETH_FILTER_GET)
3033                         return -EINVAL;
3034
3035                 /* PMD supports thread-safe flow operations.  rte_flow API
3036                  * functions can avoid mutex for multi-thread safety.
3037                  */
3038                 dev->data->dev_flags |= RTE_ETH_DEV_FLOW_OPS_THREAD_SAFE;
3039
3040                 if (BNXT_TRUFLOW_EN(bp))
3041                         *(const void **)arg = &bnxt_ulp_rte_flow_ops;
3042                 else
3043                         *(const void **)arg = &bnxt_flow_ops;
3044                 break;
3045         default:
3046                 PMD_DRV_LOG(ERR,
3047                         "Filter type (%d) not supported", filter_type);
3048                 ret = -EINVAL;
3049                 break;
3050         }
3051         return ret;
3052 }
3053
3054 static const uint32_t *
3055 bnxt_dev_supported_ptypes_get_op(struct rte_eth_dev *dev)
3056 {
3057         static const uint32_t ptypes[] = {
3058                 RTE_PTYPE_L2_ETHER_VLAN,
3059                 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN,
3060                 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN,
3061                 RTE_PTYPE_L4_ICMP,
3062                 RTE_PTYPE_L4_TCP,
3063                 RTE_PTYPE_L4_UDP,
3064                 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN,
3065                 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN,
3066                 RTE_PTYPE_INNER_L4_ICMP,
3067                 RTE_PTYPE_INNER_L4_TCP,
3068                 RTE_PTYPE_INNER_L4_UDP,
3069                 RTE_PTYPE_UNKNOWN
3070         };
3071
3072         if (!dev->rx_pkt_burst)
3073                 return NULL;
3074
3075         return ptypes;
3076 }
3077
3078 static int bnxt_map_regs(struct bnxt *bp, uint32_t *reg_arr, int count,
3079                          int reg_win)
3080 {
3081         uint32_t reg_base = *reg_arr & 0xfffff000;
3082         uint32_t win_off;
3083         int i;
3084
3085         for (i = 0; i < count; i++) {
3086                 if ((reg_arr[i] & 0xfffff000) != reg_base)
3087                         return -ERANGE;
3088         }
3089         win_off = BNXT_GRCPF_REG_WINDOW_BASE_OUT + (reg_win - 1) * 4;
3090         rte_write32(reg_base, (uint8_t *)bp->bar0 + win_off);
3091         return 0;
3092 }
3093
3094 static int bnxt_map_ptp_regs(struct bnxt *bp)
3095 {
3096         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3097         uint32_t *reg_arr;
3098         int rc, i;
3099
3100         reg_arr = ptp->rx_regs;
3101         rc = bnxt_map_regs(bp, reg_arr, BNXT_PTP_RX_REGS, 5);
3102         if (rc)
3103                 return rc;
3104
3105         reg_arr = ptp->tx_regs;
3106         rc = bnxt_map_regs(bp, reg_arr, BNXT_PTP_TX_REGS, 6);
3107         if (rc)
3108                 return rc;
3109
3110         for (i = 0; i < BNXT_PTP_RX_REGS; i++)
3111                 ptp->rx_mapped_regs[i] = 0x5000 + (ptp->rx_regs[i] & 0xfff);
3112
3113         for (i = 0; i < BNXT_PTP_TX_REGS; i++)
3114                 ptp->tx_mapped_regs[i] = 0x6000 + (ptp->tx_regs[i] & 0xfff);
3115
3116         return 0;
3117 }
3118
3119 static void bnxt_unmap_ptp_regs(struct bnxt *bp)
3120 {
3121         rte_write32(0, (uint8_t *)bp->bar0 +
3122                          BNXT_GRCPF_REG_WINDOW_BASE_OUT + 16);
3123         rte_write32(0, (uint8_t *)bp->bar0 +
3124                          BNXT_GRCPF_REG_WINDOW_BASE_OUT + 20);
3125 }
3126
3127 static uint64_t bnxt_cc_read(struct bnxt *bp)
3128 {
3129         uint64_t ns;
3130
3131         ns = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3132                               BNXT_GRCPF_REG_SYNC_TIME));
3133         ns |= (uint64_t)(rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3134                                           BNXT_GRCPF_REG_SYNC_TIME + 4))) << 32;
3135         return ns;
3136 }
3137
3138 static int bnxt_get_tx_ts(struct bnxt *bp, uint64_t *ts)
3139 {
3140         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3141         uint32_t fifo;
3142
3143         fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3144                                 ptp->tx_mapped_regs[BNXT_PTP_TX_FIFO]));
3145         if (fifo & BNXT_PTP_TX_FIFO_EMPTY)
3146                 return -EAGAIN;
3147
3148         fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3149                                 ptp->tx_mapped_regs[BNXT_PTP_TX_FIFO]));
3150         *ts = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3151                                 ptp->tx_mapped_regs[BNXT_PTP_TX_TS_L]));
3152         *ts |= (uint64_t)rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3153                                 ptp->tx_mapped_regs[BNXT_PTP_TX_TS_H])) << 32;
3154
3155         return 0;
3156 }
3157
3158 static int bnxt_get_rx_ts(struct bnxt *bp, uint64_t *ts)
3159 {
3160         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3161         struct bnxt_pf_info *pf = bp->pf;
3162         uint16_t port_id;
3163         uint32_t fifo;
3164
3165         if (!ptp)
3166                 return -ENODEV;
3167
3168         fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3169                                 ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO]));
3170         if (!(fifo & BNXT_PTP_RX_FIFO_PENDING))
3171                 return -EAGAIN;
3172
3173         port_id = pf->port_id;
3174         rte_write32(1 << port_id, (uint8_t *)bp->bar0 +
3175                ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO_ADV]);
3176
3177         fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3178                                    ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO]));
3179         if (fifo & BNXT_PTP_RX_FIFO_PENDING) {
3180 /*              bnxt_clr_rx_ts(bp);       TBD  */
3181                 return -EBUSY;
3182         }
3183
3184         *ts = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3185                                 ptp->rx_mapped_regs[BNXT_PTP_RX_TS_L]));
3186         *ts |= (uint64_t)rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3187                                 ptp->rx_mapped_regs[BNXT_PTP_RX_TS_H])) << 32;
3188
3189         return 0;
3190 }
3191
3192 static int
3193 bnxt_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
3194 {
3195         uint64_t ns;
3196         struct bnxt *bp = dev->data->dev_private;
3197         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3198
3199         if (!ptp)
3200                 return 0;
3201
3202         ns = rte_timespec_to_ns(ts);
3203         /* Set the timecounters to a new value. */
3204         ptp->tc.nsec = ns;
3205
3206         return 0;
3207 }
3208
3209 static int
3210 bnxt_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
3211 {
3212         struct bnxt *bp = dev->data->dev_private;
3213         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3214         uint64_t ns, systime_cycles = 0;
3215         int rc = 0;
3216
3217         if (!ptp)
3218                 return 0;
3219
3220         if (BNXT_CHIP_THOR(bp))
3221                 rc = bnxt_hwrm_port_ts_query(bp, BNXT_PTP_FLAGS_CURRENT_TIME,
3222                                              &systime_cycles);
3223         else
3224                 systime_cycles = bnxt_cc_read(bp);
3225
3226         ns = rte_timecounter_update(&ptp->tc, systime_cycles);
3227         *ts = rte_ns_to_timespec(ns);
3228
3229         return rc;
3230 }
3231 static int
3232 bnxt_timesync_enable(struct rte_eth_dev *dev)
3233 {
3234         struct bnxt *bp = dev->data->dev_private;
3235         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3236         uint32_t shift = 0;
3237         int rc;
3238
3239         if (!ptp)
3240                 return 0;
3241
3242         ptp->rx_filter = 1;
3243         ptp->tx_tstamp_en = 1;
3244         ptp->rxctl = BNXT_PTP_MSG_EVENTS;
3245
3246         rc = bnxt_hwrm_ptp_cfg(bp);
3247         if (rc)
3248                 return rc;
3249
3250         memset(&ptp->tc, 0, sizeof(struct rte_timecounter));
3251         memset(&ptp->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
3252         memset(&ptp->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
3253
3254         ptp->tc.cc_mask = BNXT_CYCLECOUNTER_MASK;
3255         ptp->tc.cc_shift = shift;
3256         ptp->tc.nsec_mask = (1ULL << shift) - 1;
3257
3258         ptp->rx_tstamp_tc.cc_mask = BNXT_CYCLECOUNTER_MASK;
3259         ptp->rx_tstamp_tc.cc_shift = shift;
3260         ptp->rx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
3261
3262         ptp->tx_tstamp_tc.cc_mask = BNXT_CYCLECOUNTER_MASK;
3263         ptp->tx_tstamp_tc.cc_shift = shift;
3264         ptp->tx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
3265
3266         if (!BNXT_CHIP_THOR(bp))
3267                 bnxt_map_ptp_regs(bp);
3268
3269         return 0;
3270 }
3271
3272 static int
3273 bnxt_timesync_disable(struct rte_eth_dev *dev)
3274 {
3275         struct bnxt *bp = dev->data->dev_private;
3276         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3277
3278         if (!ptp)
3279                 return 0;
3280
3281         ptp->rx_filter = 0;
3282         ptp->tx_tstamp_en = 0;
3283         ptp->rxctl = 0;
3284
3285         bnxt_hwrm_ptp_cfg(bp);
3286
3287         if (!BNXT_CHIP_THOR(bp))
3288                 bnxt_unmap_ptp_regs(bp);
3289
3290         return 0;
3291 }
3292
3293 static int
3294 bnxt_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
3295                                  struct timespec *timestamp,
3296                                  uint32_t flags __rte_unused)
3297 {
3298         struct bnxt *bp = dev->data->dev_private;
3299         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3300         uint64_t rx_tstamp_cycles = 0;
3301         uint64_t ns;
3302
3303         if (!ptp)
3304                 return 0;
3305
3306         if (BNXT_CHIP_THOR(bp))
3307                 rx_tstamp_cycles = ptp->rx_timestamp;
3308         else
3309                 bnxt_get_rx_ts(bp, &rx_tstamp_cycles);
3310
3311         ns = rte_timecounter_update(&ptp->rx_tstamp_tc, rx_tstamp_cycles);
3312         *timestamp = rte_ns_to_timespec(ns);
3313         return  0;
3314 }
3315
3316 static int
3317 bnxt_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
3318                                  struct timespec *timestamp)
3319 {
3320         struct bnxt *bp = dev->data->dev_private;
3321         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3322         uint64_t tx_tstamp_cycles = 0;
3323         uint64_t ns;
3324         int rc = 0;
3325
3326         if (!ptp)
3327                 return 0;
3328
3329         if (BNXT_CHIP_THOR(bp))
3330                 rc = bnxt_hwrm_port_ts_query(bp, BNXT_PTP_FLAGS_PATH_TX,
3331                                              &tx_tstamp_cycles);
3332         else
3333                 rc = bnxt_get_tx_ts(bp, &tx_tstamp_cycles);
3334
3335         ns = rte_timecounter_update(&ptp->tx_tstamp_tc, tx_tstamp_cycles);
3336         *timestamp = rte_ns_to_timespec(ns);
3337
3338         return rc;
3339 }
3340
3341 static int
3342 bnxt_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
3343 {
3344         struct bnxt *bp = dev->data->dev_private;
3345         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3346
3347         if (!ptp)
3348                 return 0;
3349
3350         ptp->tc.nsec += delta;
3351
3352         return 0;
3353 }
3354
3355 static int
3356 bnxt_get_eeprom_length_op(struct rte_eth_dev *dev)
3357 {
3358         struct bnxt *bp = dev->data->dev_private;
3359         int rc;
3360         uint32_t dir_entries;
3361         uint32_t entry_length;
3362
3363         rc = is_bnxt_in_error(bp);
3364         if (rc)
3365                 return rc;
3366
3367         PMD_DRV_LOG(INFO, PCI_PRI_FMT "\n",
3368                     bp->pdev->addr.domain, bp->pdev->addr.bus,
3369                     bp->pdev->addr.devid, bp->pdev->addr.function);
3370
3371         rc = bnxt_hwrm_nvm_get_dir_info(bp, &dir_entries, &entry_length);
3372         if (rc != 0)
3373                 return rc;
3374
3375         return dir_entries * entry_length;
3376 }
3377
3378 static int
3379 bnxt_get_eeprom_op(struct rte_eth_dev *dev,
3380                 struct rte_dev_eeprom_info *in_eeprom)
3381 {
3382         struct bnxt *bp = dev->data->dev_private;
3383         uint32_t index;
3384         uint32_t offset;
3385         int rc;
3386
3387         rc = is_bnxt_in_error(bp);
3388         if (rc)
3389                 return rc;
3390
3391         PMD_DRV_LOG(INFO, PCI_PRI_FMT " in_eeprom->offset = %d len = %d\n",
3392                     bp->pdev->addr.domain, bp->pdev->addr.bus,
3393                     bp->pdev->addr.devid, bp->pdev->addr.function,
3394                     in_eeprom->offset, in_eeprom->length);
3395
3396         if (in_eeprom->offset == 0) /* special offset value to get directory */
3397                 return bnxt_get_nvram_directory(bp, in_eeprom->length,
3398                                                 in_eeprom->data);
3399
3400         index = in_eeprom->offset >> 24;
3401         offset = in_eeprom->offset & 0xffffff;
3402
3403         if (index != 0)
3404                 return bnxt_hwrm_get_nvram_item(bp, index - 1, offset,
3405                                            in_eeprom->length, in_eeprom->data);
3406
3407         return 0;
3408 }
3409
3410 static bool bnxt_dir_type_is_ape_bin_format(uint16_t dir_type)
3411 {
3412         switch (dir_type) {
3413         case BNX_DIR_TYPE_CHIMP_PATCH:
3414         case BNX_DIR_TYPE_BOOTCODE:
3415         case BNX_DIR_TYPE_BOOTCODE_2:
3416         case BNX_DIR_TYPE_APE_FW:
3417         case BNX_DIR_TYPE_APE_PATCH:
3418         case BNX_DIR_TYPE_KONG_FW:
3419         case BNX_DIR_TYPE_KONG_PATCH:
3420         case BNX_DIR_TYPE_BONO_FW:
3421         case BNX_DIR_TYPE_BONO_PATCH:
3422                 /* FALLTHROUGH */
3423                 return true;
3424         }
3425
3426         return false;
3427 }
3428
3429 static bool bnxt_dir_type_is_other_exec_format(uint16_t dir_type)
3430 {
3431         switch (dir_type) {
3432         case BNX_DIR_TYPE_AVS:
3433         case BNX_DIR_TYPE_EXP_ROM_MBA:
3434         case BNX_DIR_TYPE_PCIE:
3435         case BNX_DIR_TYPE_TSCF_UCODE:
3436         case BNX_DIR_TYPE_EXT_PHY:
3437         case BNX_DIR_TYPE_CCM:
3438         case BNX_DIR_TYPE_ISCSI_BOOT:
3439         case BNX_DIR_TYPE_ISCSI_BOOT_IPV6:
3440         case BNX_DIR_TYPE_ISCSI_BOOT_IPV4N6:
3441                 /* FALLTHROUGH */
3442                 return true;
3443         }
3444
3445         return false;
3446 }
3447
3448 static bool bnxt_dir_type_is_executable(uint16_t dir_type)
3449 {
3450         return bnxt_dir_type_is_ape_bin_format(dir_type) ||
3451                 bnxt_dir_type_is_other_exec_format(dir_type);
3452 }
3453
3454 static int
3455 bnxt_set_eeprom_op(struct rte_eth_dev *dev,
3456                 struct rte_dev_eeprom_info *in_eeprom)
3457 {
3458         struct bnxt *bp = dev->data->dev_private;
3459         uint8_t index, dir_op;
3460         uint16_t type, ext, ordinal, attr;
3461         int rc;
3462
3463         rc = is_bnxt_in_error(bp);
3464         if (rc)
3465                 return rc;
3466
3467         PMD_DRV_LOG(INFO, PCI_PRI_FMT " in_eeprom->offset = %d len = %d\n",
3468                     bp->pdev->addr.domain, bp->pdev->addr.bus,
3469                     bp->pdev->addr.devid, bp->pdev->addr.function,
3470                     in_eeprom->offset, in_eeprom->length);
3471
3472         if (!BNXT_PF(bp)) {
3473                 PMD_DRV_LOG(ERR, "NVM write not supported from a VF\n");
3474                 return -EINVAL;
3475         }
3476
3477         type = in_eeprom->magic >> 16;
3478
3479         if (type == 0xffff) { /* special value for directory operations */
3480                 index = in_eeprom->magic & 0xff;
3481                 dir_op = in_eeprom->magic >> 8;
3482                 if (index == 0)
3483                         return -EINVAL;
3484                 switch (dir_op) {
3485                 case 0x0e: /* erase */
3486                         if (in_eeprom->offset != ~in_eeprom->magic)
3487                                 return -EINVAL;
3488                         return bnxt_hwrm_erase_nvram_directory(bp, index - 1);
3489                 default:
3490                         return -EINVAL;
3491                 }
3492         }
3493
3494         /* Create or re-write an NVM item: */
3495         if (bnxt_dir_type_is_executable(type) == true)
3496                 return -EOPNOTSUPP;
3497         ext = in_eeprom->magic & 0xffff;
3498         ordinal = in_eeprom->offset >> 16;
3499         attr = in_eeprom->offset & 0xffff;
3500
3501         return bnxt_hwrm_flash_nvram(bp, type, ordinal, ext, attr,
3502                                      in_eeprom->data, in_eeprom->length);
3503 }
3504
3505 /*
3506  * Initialization
3507  */
3508
3509 static const struct eth_dev_ops bnxt_dev_ops = {
3510         .dev_infos_get = bnxt_dev_info_get_op,
3511         .dev_close = bnxt_dev_close_op,
3512         .dev_configure = bnxt_dev_configure_op,
3513         .dev_start = bnxt_dev_start_op,
3514         .dev_stop = bnxt_dev_stop_op,
3515         .dev_set_link_up = bnxt_dev_set_link_up_op,
3516         .dev_set_link_down = bnxt_dev_set_link_down_op,
3517         .stats_get = bnxt_stats_get_op,
3518         .stats_reset = bnxt_stats_reset_op,
3519         .rx_queue_setup = bnxt_rx_queue_setup_op,
3520         .rx_queue_release = bnxt_rx_queue_release_op,
3521         .tx_queue_setup = bnxt_tx_queue_setup_op,
3522         .tx_queue_release = bnxt_tx_queue_release_op,
3523         .rx_queue_intr_enable = bnxt_rx_queue_intr_enable_op,
3524         .rx_queue_intr_disable = bnxt_rx_queue_intr_disable_op,
3525         .reta_update = bnxt_reta_update_op,
3526         .reta_query = bnxt_reta_query_op,
3527         .rss_hash_update = bnxt_rss_hash_update_op,
3528         .rss_hash_conf_get = bnxt_rss_hash_conf_get_op,
3529         .link_update = bnxt_link_update_op,
3530         .promiscuous_enable = bnxt_promiscuous_enable_op,
3531         .promiscuous_disable = bnxt_promiscuous_disable_op,
3532         .allmulticast_enable = bnxt_allmulticast_enable_op,
3533         .allmulticast_disable = bnxt_allmulticast_disable_op,
3534         .mac_addr_add = bnxt_mac_addr_add_op,
3535         .mac_addr_remove = bnxt_mac_addr_remove_op,
3536         .flow_ctrl_get = bnxt_flow_ctrl_get_op,
3537         .flow_ctrl_set = bnxt_flow_ctrl_set_op,
3538         .udp_tunnel_port_add  = bnxt_udp_tunnel_port_add_op,
3539         .udp_tunnel_port_del  = bnxt_udp_tunnel_port_del_op,
3540         .vlan_filter_set = bnxt_vlan_filter_set_op,
3541         .vlan_offload_set = bnxt_vlan_offload_set_op,
3542         .vlan_tpid_set = bnxt_vlan_tpid_set_op,
3543         .vlan_pvid_set = bnxt_vlan_pvid_set_op,
3544         .mtu_set = bnxt_mtu_set_op,
3545         .mac_addr_set = bnxt_set_default_mac_addr_op,
3546         .xstats_get = bnxt_dev_xstats_get_op,
3547         .xstats_get_names = bnxt_dev_xstats_get_names_op,
3548         .xstats_reset = bnxt_dev_xstats_reset_op,
3549         .fw_version_get = bnxt_fw_version_get,
3550         .set_mc_addr_list = bnxt_dev_set_mc_addr_list_op,
3551         .rxq_info_get = bnxt_rxq_info_get_op,
3552         .txq_info_get = bnxt_txq_info_get_op,
3553         .rx_burst_mode_get = bnxt_rx_burst_mode_get,
3554         .tx_burst_mode_get = bnxt_tx_burst_mode_get,
3555         .dev_led_on = bnxt_dev_led_on_op,
3556         .dev_led_off = bnxt_dev_led_off_op,
3557         .rx_queue_start = bnxt_rx_queue_start,
3558         .rx_queue_stop = bnxt_rx_queue_stop,
3559         .tx_queue_start = bnxt_tx_queue_start,
3560         .tx_queue_stop = bnxt_tx_queue_stop,
3561         .filter_ctrl = bnxt_filter_ctrl_op,
3562         .dev_supported_ptypes_get = bnxt_dev_supported_ptypes_get_op,
3563         .get_eeprom_length    = bnxt_get_eeprom_length_op,
3564         .get_eeprom           = bnxt_get_eeprom_op,
3565         .set_eeprom           = bnxt_set_eeprom_op,
3566         .timesync_enable      = bnxt_timesync_enable,
3567         .timesync_disable     = bnxt_timesync_disable,
3568         .timesync_read_time   = bnxt_timesync_read_time,
3569         .timesync_write_time   = bnxt_timesync_write_time,
3570         .timesync_adjust_time = bnxt_timesync_adjust_time,
3571         .timesync_read_rx_timestamp = bnxt_timesync_read_rx_timestamp,
3572         .timesync_read_tx_timestamp = bnxt_timesync_read_tx_timestamp,
3573 };
3574
3575 static uint32_t bnxt_map_reset_regs(struct bnxt *bp, uint32_t reg)
3576 {
3577         uint32_t offset;
3578
3579         /* Only pre-map the reset GRC registers using window 3 */
3580         rte_write32(reg & 0xfffff000, (uint8_t *)bp->bar0 +
3581                     BNXT_GRCPF_REG_WINDOW_BASE_OUT + 8);
3582
3583         offset = BNXT_GRCP_WINDOW_3_BASE + (reg & 0xffc);
3584
3585         return offset;
3586 }
3587
3588 int bnxt_map_fw_health_status_regs(struct bnxt *bp)
3589 {
3590         struct bnxt_error_recovery_info *info = bp->recovery_info;
3591         uint32_t reg_base = 0xffffffff;
3592         int i;
3593
3594         /* Only pre-map the monitoring GRC registers using window 2 */
3595         for (i = 0; i < BNXT_FW_STATUS_REG_CNT; i++) {
3596                 uint32_t reg = info->status_regs[i];
3597
3598                 if (BNXT_FW_STATUS_REG_TYPE(reg) != BNXT_FW_STATUS_REG_TYPE_GRC)
3599                         continue;
3600
3601                 if (reg_base == 0xffffffff)
3602                         reg_base = reg & 0xfffff000;
3603                 if ((reg & 0xfffff000) != reg_base)
3604                         return -ERANGE;
3605
3606                 /* Use mask 0xffc as the Lower 2 bits indicates
3607                  * address space location
3608                  */
3609                 info->mapped_status_regs[i] = BNXT_GRCP_WINDOW_2_BASE +
3610                                                 (reg & 0xffc);
3611         }
3612
3613         if (reg_base == 0xffffffff)
3614                 return 0;
3615
3616         rte_write32(reg_base, (uint8_t *)bp->bar0 +
3617                     BNXT_GRCPF_REG_WINDOW_BASE_OUT + 4);
3618
3619         return 0;
3620 }
3621
3622 static void bnxt_write_fw_reset_reg(struct bnxt *bp, uint32_t index)
3623 {
3624         struct bnxt_error_recovery_info *info = bp->recovery_info;
3625         uint32_t delay = info->delay_after_reset[index];
3626         uint32_t val = info->reset_reg_val[index];
3627         uint32_t reg = info->reset_reg[index];
3628         uint32_t type, offset;
3629
3630         type = BNXT_FW_STATUS_REG_TYPE(reg);
3631         offset = BNXT_FW_STATUS_REG_OFF(reg);
3632
3633         switch (type) {
3634         case BNXT_FW_STATUS_REG_TYPE_CFG:
3635                 rte_pci_write_config(bp->pdev, &val, sizeof(val), offset);
3636                 break;
3637         case BNXT_FW_STATUS_REG_TYPE_GRC:
3638                 offset = bnxt_map_reset_regs(bp, offset);
3639                 rte_write32(val, (uint8_t *)bp->bar0 + offset);
3640                 break;
3641         case BNXT_FW_STATUS_REG_TYPE_BAR0:
3642                 rte_write32(val, (uint8_t *)bp->bar0 + offset);
3643                 break;
3644         }
3645         /* wait on a specific interval of time until core reset is complete */
3646         if (delay)
3647                 rte_delay_ms(delay);
3648 }
3649
3650 static void bnxt_dev_cleanup(struct bnxt *bp)
3651 {
3652         bp->eth_dev->data->dev_link.link_status = 0;
3653         bp->link_info->link_up = 0;
3654         if (bp->eth_dev->data->dev_started)
3655                 bnxt_dev_stop_op(bp->eth_dev);
3656
3657         bnxt_uninit_resources(bp, true);
3658 }
3659
3660 static int bnxt_restore_vlan_filters(struct bnxt *bp)
3661 {
3662         struct rte_eth_dev *dev = bp->eth_dev;
3663         struct rte_vlan_filter_conf *vfc;
3664         int vidx, vbit, rc;
3665         uint16_t vlan_id;
3666
3667         for (vlan_id = 1; vlan_id <= RTE_ETHER_MAX_VLAN_ID; vlan_id++) {
3668                 vfc = &dev->data->vlan_filter_conf;
3669                 vidx = vlan_id / 64;
3670                 vbit = vlan_id % 64;
3671
3672                 /* Each bit corresponds to a VLAN id */
3673                 if (vfc->ids[vidx] & (UINT64_C(1) << vbit)) {
3674                         rc = bnxt_add_vlan_filter(bp, vlan_id);
3675                         if (rc)
3676                                 return rc;
3677                 }
3678         }
3679
3680         return 0;
3681 }
3682
3683 static int bnxt_restore_mac_filters(struct bnxt *bp)
3684 {
3685         struct rte_eth_dev *dev = bp->eth_dev;
3686         struct rte_eth_dev_info dev_info;
3687         struct rte_ether_addr *addr;
3688         uint64_t pool_mask;
3689         uint32_t pool = 0;
3690         uint16_t i;
3691         int rc;
3692
3693         if (BNXT_VF(bp) && !BNXT_VF_IS_TRUSTED(bp))
3694                 return 0;
3695
3696         rc = bnxt_dev_info_get_op(dev, &dev_info);
3697         if (rc)
3698                 return rc;
3699
3700         /* replay MAC address configuration */
3701         for (i = 1; i < dev_info.max_mac_addrs; i++) {
3702                 addr = &dev->data->mac_addrs[i];
3703
3704                 /* skip zero address */
3705                 if (rte_is_zero_ether_addr(addr))
3706                         continue;
3707
3708                 pool = 0;
3709                 pool_mask = dev->data->mac_pool_sel[i];
3710
3711                 do {
3712                         if (pool_mask & 1ULL) {
3713                                 rc = bnxt_mac_addr_add_op(dev, addr, i, pool);
3714                                 if (rc)
3715                                         return rc;
3716                         }
3717                         pool_mask >>= 1;
3718                         pool++;
3719                 } while (pool_mask);
3720         }
3721
3722         return 0;
3723 }
3724
3725 static int bnxt_restore_filters(struct bnxt *bp)
3726 {
3727         struct rte_eth_dev *dev = bp->eth_dev;
3728         int ret = 0;
3729
3730         if (dev->data->all_multicast) {
3731                 ret = bnxt_allmulticast_enable_op(dev);
3732                 if (ret)
3733                         return ret;
3734         }
3735         if (dev->data->promiscuous) {
3736                 ret = bnxt_promiscuous_enable_op(dev);
3737                 if (ret)
3738                         return ret;
3739         }
3740
3741         ret = bnxt_restore_mac_filters(bp);
3742         if (ret)
3743                 return ret;
3744
3745         ret = bnxt_restore_vlan_filters(bp);
3746         /* TODO restore other filters as well */
3747         return ret;
3748 }
3749
3750 static void bnxt_dev_recover(void *arg)
3751 {
3752         struct bnxt *bp = arg;
3753         int timeout = bp->fw_reset_max_msecs;
3754         int rc = 0;
3755
3756         /* Clear Error flag so that device re-init should happen */
3757         bp->flags &= ~BNXT_FLAG_FATAL_ERROR;
3758
3759         do {
3760                 rc = bnxt_hwrm_ver_get(bp, SHORT_HWRM_CMD_TIMEOUT);
3761                 if (rc == 0)
3762                         break;
3763                 rte_delay_ms(BNXT_FW_READY_WAIT_INTERVAL);
3764                 timeout -= BNXT_FW_READY_WAIT_INTERVAL;
3765         } while (rc && timeout);
3766
3767         if (rc) {
3768                 PMD_DRV_LOG(ERR, "FW is not Ready after reset\n");
3769                 goto err;
3770         }
3771
3772         rc = bnxt_init_resources(bp, true);
3773         if (rc) {
3774                 PMD_DRV_LOG(ERR,
3775                             "Failed to initialize resources after reset\n");
3776                 goto err;
3777         }
3778         /* clear reset flag as the device is initialized now */
3779         bp->flags &= ~BNXT_FLAG_FW_RESET;
3780
3781         rc = bnxt_dev_start_op(bp->eth_dev);
3782         if (rc) {
3783                 PMD_DRV_LOG(ERR, "Failed to start port after reset\n");
3784                 goto err_start;
3785         }
3786
3787         rc = bnxt_restore_filters(bp);
3788         if (rc)
3789                 goto err_start;
3790
3791         PMD_DRV_LOG(INFO, "Recovered from FW reset\n");
3792         return;
3793 err_start:
3794         bnxt_dev_stop_op(bp->eth_dev);
3795 err:
3796         bp->flags |= BNXT_FLAG_FATAL_ERROR;
3797         bnxt_uninit_resources(bp, false);
3798         PMD_DRV_LOG(ERR, "Failed to recover from FW reset\n");
3799 }
3800
3801 void bnxt_dev_reset_and_resume(void *arg)
3802 {
3803         struct bnxt *bp = arg;
3804         int rc;
3805
3806         bnxt_dev_cleanup(bp);
3807
3808         bnxt_wait_for_device_shutdown(bp);
3809
3810         rc = rte_eal_alarm_set(US_PER_MS * bp->fw_reset_min_msecs,
3811                                bnxt_dev_recover, (void *)bp);
3812         if (rc)
3813                 PMD_DRV_LOG(ERR, "Error setting recovery alarm");
3814 }
3815
3816 uint32_t bnxt_read_fw_status_reg(struct bnxt *bp, uint32_t index)
3817 {
3818         struct bnxt_error_recovery_info *info = bp->recovery_info;
3819         uint32_t reg = info->status_regs[index];
3820         uint32_t type, offset, val = 0;
3821
3822         type = BNXT_FW_STATUS_REG_TYPE(reg);
3823         offset = BNXT_FW_STATUS_REG_OFF(reg);
3824
3825         switch (type) {
3826         case BNXT_FW_STATUS_REG_TYPE_CFG:
3827                 rte_pci_read_config(bp->pdev, &val, sizeof(val), offset);
3828                 break;
3829         case BNXT_FW_STATUS_REG_TYPE_GRC:
3830                 offset = info->mapped_status_regs[index];
3831                 /* FALLTHROUGH */
3832         case BNXT_FW_STATUS_REG_TYPE_BAR0:
3833                 val = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3834                                        offset));
3835                 break;
3836         }
3837
3838         return val;
3839 }
3840
3841 static int bnxt_fw_reset_all(struct bnxt *bp)
3842 {
3843         struct bnxt_error_recovery_info *info = bp->recovery_info;
3844         uint32_t i;
3845         int rc = 0;
3846
3847         if (info->flags & BNXT_FLAG_ERROR_RECOVERY_HOST) {
3848                 /* Reset through master function driver */
3849                 for (i = 0; i < info->reg_array_cnt; i++)
3850                         bnxt_write_fw_reset_reg(bp, i);
3851                 /* Wait for time specified by FW after triggering reset */
3852                 rte_delay_ms(info->master_func_wait_period_after_reset);
3853         } else if (info->flags & BNXT_FLAG_ERROR_RECOVERY_CO_CPU) {
3854                 /* Reset with the help of Kong processor */
3855                 rc = bnxt_hwrm_fw_reset(bp);
3856                 if (rc)
3857                         PMD_DRV_LOG(ERR, "Failed to reset FW\n");
3858         }
3859
3860         return rc;
3861 }
3862
3863 static void bnxt_fw_reset_cb(void *arg)
3864 {
3865         struct bnxt *bp = arg;
3866         struct bnxt_error_recovery_info *info = bp->recovery_info;
3867         int rc = 0;
3868
3869         /* Only Master function can do FW reset */
3870         if (bnxt_is_master_func(bp) &&
3871             bnxt_is_recovery_enabled(bp)) {
3872                 rc = bnxt_fw_reset_all(bp);
3873                 if (rc) {
3874                         PMD_DRV_LOG(ERR, "Adapter recovery failed\n");
3875                         return;
3876                 }
3877         }
3878
3879         /* if recovery method is ERROR_RECOVERY_CO_CPU, KONG will send
3880          * EXCEPTION_FATAL_ASYNC event to all the functions
3881          * (including MASTER FUNC). After receiving this Async, all the active
3882          * drivers should treat this case as FW initiated recovery
3883          */
3884         if (info->flags & BNXT_FLAG_ERROR_RECOVERY_HOST) {
3885                 bp->fw_reset_min_msecs = BNXT_MIN_FW_READY_TIMEOUT;
3886                 bp->fw_reset_max_msecs = BNXT_MAX_FW_RESET_TIMEOUT;
3887
3888                 /* To recover from error */
3889                 rte_eal_alarm_set(US_PER_MS, bnxt_dev_reset_and_resume,
3890                                   (void *)bp);
3891         }
3892 }
3893
3894 /* Driver should poll FW heartbeat, reset_counter with the frequency
3895  * advertised by FW in HWRM_ERROR_RECOVERY_QCFG.
3896  * When the driver detects heartbeat stop or change in reset_counter,
3897  * it has to trigger a reset to recover from the error condition.
3898  * A “master PF” is the function who will have the privilege to
3899  * initiate the chimp reset. The master PF will be elected by the
3900  * firmware and will be notified through async message.
3901  */
3902 static void bnxt_check_fw_health(void *arg)
3903 {
3904         struct bnxt *bp = arg;
3905         struct bnxt_error_recovery_info *info = bp->recovery_info;
3906         uint32_t val = 0, wait_msec;
3907
3908         if (!info || !bnxt_is_recovery_enabled(bp) ||
3909             is_bnxt_in_error(bp))
3910                 return;
3911
3912         val = bnxt_read_fw_status_reg(bp, BNXT_FW_HEARTBEAT_CNT_REG);
3913         if (val == info->last_heart_beat)
3914                 goto reset;
3915
3916         info->last_heart_beat = val;
3917
3918         val = bnxt_read_fw_status_reg(bp, BNXT_FW_RECOVERY_CNT_REG);
3919         if (val != info->last_reset_counter)
3920                 goto reset;
3921
3922         info->last_reset_counter = val;
3923
3924         rte_eal_alarm_set(US_PER_MS * info->driver_polling_freq,
3925                           bnxt_check_fw_health, (void *)bp);
3926
3927         return;
3928 reset:
3929         /* Stop DMA to/from device */
3930         bp->flags |= BNXT_FLAG_FATAL_ERROR;
3931         bp->flags |= BNXT_FLAG_FW_RESET;
3932
3933         PMD_DRV_LOG(ERR, "Detected FW dead condition\n");
3934
3935         if (bnxt_is_master_func(bp))
3936                 wait_msec = info->master_func_wait_period;
3937         else
3938                 wait_msec = info->normal_func_wait_period;
3939
3940         rte_eal_alarm_set(US_PER_MS * wait_msec,
3941                           bnxt_fw_reset_cb, (void *)bp);
3942 }
3943
3944 void bnxt_schedule_fw_health_check(struct bnxt *bp)
3945 {
3946         uint32_t polling_freq;
3947
3948         pthread_mutex_lock(&bp->health_check_lock);
3949
3950         if (!bnxt_is_recovery_enabled(bp))
3951                 goto done;
3952
3953         if (bp->flags & BNXT_FLAG_FW_HEALTH_CHECK_SCHEDULED)
3954                 goto done;
3955
3956         polling_freq = bp->recovery_info->driver_polling_freq;
3957
3958         rte_eal_alarm_set(US_PER_MS * polling_freq,
3959                           bnxt_check_fw_health, (void *)bp);
3960         bp->flags |= BNXT_FLAG_FW_HEALTH_CHECK_SCHEDULED;
3961
3962 done:
3963         pthread_mutex_unlock(&bp->health_check_lock);
3964 }
3965
3966 static void bnxt_cancel_fw_health_check(struct bnxt *bp)
3967 {
3968         if (!bnxt_is_recovery_enabled(bp))
3969                 return;
3970
3971         rte_eal_alarm_cancel(bnxt_check_fw_health, (void *)bp);
3972         bp->flags &= ~BNXT_FLAG_FW_HEALTH_CHECK_SCHEDULED;
3973 }
3974
3975 static bool bnxt_vf_pciid(uint16_t device_id)
3976 {
3977         switch (device_id) {
3978         case BROADCOM_DEV_ID_57304_VF:
3979         case BROADCOM_DEV_ID_57406_VF:
3980         case BROADCOM_DEV_ID_5731X_VF:
3981         case BROADCOM_DEV_ID_5741X_VF:
3982         case BROADCOM_DEV_ID_57414_VF:
3983         case BROADCOM_DEV_ID_STRATUS_NIC_VF1:
3984         case BROADCOM_DEV_ID_STRATUS_NIC_VF2:
3985         case BROADCOM_DEV_ID_58802_VF:
3986         case BROADCOM_DEV_ID_57500_VF1:
3987         case BROADCOM_DEV_ID_57500_VF2:
3988                 /* FALLTHROUGH */
3989                 return true;
3990         default:
3991                 return false;
3992         }
3993 }
3994
3995 static bool bnxt_thor_device(uint16_t device_id)
3996 {
3997         switch (device_id) {
3998         case BROADCOM_DEV_ID_57508:
3999         case BROADCOM_DEV_ID_57504:
4000         case BROADCOM_DEV_ID_57502:
4001         case BROADCOM_DEV_ID_57508_MF1:
4002         case BROADCOM_DEV_ID_57504_MF1:
4003         case BROADCOM_DEV_ID_57502_MF1:
4004         case BROADCOM_DEV_ID_57508_MF2:
4005         case BROADCOM_DEV_ID_57504_MF2:
4006         case BROADCOM_DEV_ID_57502_MF2:
4007         case BROADCOM_DEV_ID_57500_VF1:
4008         case BROADCOM_DEV_ID_57500_VF2:
4009                 /* FALLTHROUGH */
4010                 return true;
4011         default:
4012                 return false;
4013         }
4014 }
4015
4016 bool bnxt_stratus_device(struct bnxt *bp)
4017 {
4018         uint16_t device_id = bp->pdev->id.device_id;
4019
4020         switch (device_id) {
4021         case BROADCOM_DEV_ID_STRATUS_NIC:
4022         case BROADCOM_DEV_ID_STRATUS_NIC_VF1:
4023         case BROADCOM_DEV_ID_STRATUS_NIC_VF2:
4024                 /* FALLTHROUGH */
4025                 return true;
4026         default:
4027                 return false;
4028         }
4029 }
4030
4031 static int bnxt_init_board(struct rte_eth_dev *eth_dev)
4032 {
4033         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
4034         struct bnxt *bp = eth_dev->data->dev_private;
4035
4036         /* enable device (incl. PCI PM wakeup), and bus-mastering */
4037         bp->bar0 = (void *)pci_dev->mem_resource[0].addr;
4038         bp->doorbell_base = (void *)pci_dev->mem_resource[2].addr;
4039         if (!bp->bar0 || !bp->doorbell_base) {
4040                 PMD_DRV_LOG(ERR, "Unable to access Hardware\n");
4041                 return -ENODEV;
4042         }
4043
4044         bp->eth_dev = eth_dev;
4045         bp->pdev = pci_dev;
4046
4047         return 0;
4048 }
4049
4050 static int bnxt_alloc_ctx_mem_blk(struct bnxt *bp,
4051                                   struct bnxt_ctx_pg_info *ctx_pg,
4052                                   uint32_t mem_size,
4053                                   const char *suffix,
4054                                   uint16_t idx)
4055 {
4056         struct bnxt_ring_mem_info *rmem = &ctx_pg->ring_mem;
4057         const struct rte_memzone *mz = NULL;
4058         char mz_name[RTE_MEMZONE_NAMESIZE];
4059         rte_iova_t mz_phys_addr;
4060         uint64_t valid_bits = 0;
4061         uint32_t sz;
4062         int i;
4063
4064         if (!mem_size)
4065                 return 0;
4066
4067         rmem->nr_pages = RTE_ALIGN_MUL_CEIL(mem_size, BNXT_PAGE_SIZE) /
4068                          BNXT_PAGE_SIZE;
4069         rmem->page_size = BNXT_PAGE_SIZE;
4070         rmem->pg_arr = ctx_pg->ctx_pg_arr;
4071         rmem->dma_arr = ctx_pg->ctx_dma_arr;
4072         rmem->flags = BNXT_RMEM_VALID_PTE_FLAG;
4073
4074         valid_bits = PTU_PTE_VALID;
4075
4076         if (rmem->nr_pages > 1) {
4077                 snprintf(mz_name, RTE_MEMZONE_NAMESIZE,
4078                          "bnxt_ctx_pg_tbl%s_%x_%d",
4079                          suffix, idx, bp->eth_dev->data->port_id);
4080                 mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0;
4081                 mz = rte_memzone_lookup(mz_name);
4082                 if (!mz) {
4083                         mz = rte_memzone_reserve_aligned(mz_name,
4084                                                 rmem->nr_pages * 8,
4085                                                 SOCKET_ID_ANY,
4086                                                 RTE_MEMZONE_2MB |
4087                                                 RTE_MEMZONE_SIZE_HINT_ONLY |
4088                                                 RTE_MEMZONE_IOVA_CONTIG,
4089                                                 BNXT_PAGE_SIZE);
4090                         if (mz == NULL)
4091                                 return -ENOMEM;
4092                 }
4093
4094                 memset(mz->addr, 0, mz->len);
4095                 mz_phys_addr = mz->iova;
4096
4097                 rmem->pg_tbl = mz->addr;
4098                 rmem->pg_tbl_map = mz_phys_addr;
4099                 rmem->pg_tbl_mz = mz;
4100         }
4101
4102         snprintf(mz_name, RTE_MEMZONE_NAMESIZE, "bnxt_ctx_%s_%x_%d",
4103                  suffix, idx, bp->eth_dev->data->port_id);
4104         mz = rte_memzone_lookup(mz_name);
4105         if (!mz) {
4106                 mz = rte_memzone_reserve_aligned(mz_name,
4107                                                  mem_size,
4108                                                  SOCKET_ID_ANY,
4109                                                  RTE_MEMZONE_1GB |
4110                                                  RTE_MEMZONE_SIZE_HINT_ONLY |
4111                                                  RTE_MEMZONE_IOVA_CONTIG,
4112                                                  BNXT_PAGE_SIZE);
4113                 if (mz == NULL)
4114                         return -ENOMEM;
4115         }
4116
4117         memset(mz->addr, 0, mz->len);
4118         mz_phys_addr = mz->iova;
4119
4120         for (sz = 0, i = 0; sz < mem_size; sz += BNXT_PAGE_SIZE, i++) {
4121                 rmem->pg_arr[i] = ((char *)mz->addr) + sz;
4122                 rmem->dma_arr[i] = mz_phys_addr + sz;
4123
4124                 if (rmem->nr_pages > 1) {
4125                         if (i == rmem->nr_pages - 2 &&
4126                             (rmem->flags & BNXT_RMEM_RING_PTE_FLAG))
4127                                 valid_bits |= PTU_PTE_NEXT_TO_LAST;
4128                         else if (i == rmem->nr_pages - 1 &&
4129                                  (rmem->flags & BNXT_RMEM_RING_PTE_FLAG))
4130                                 valid_bits |= PTU_PTE_LAST;
4131
4132                         rmem->pg_tbl[i] = rte_cpu_to_le_64(rmem->dma_arr[i] |
4133                                                            valid_bits);
4134                 }
4135         }
4136
4137         rmem->mz = mz;
4138         if (rmem->vmem_size)
4139                 rmem->vmem = (void **)mz->addr;
4140         rmem->dma_arr[0] = mz_phys_addr;
4141         return 0;
4142 }
4143
4144 static void bnxt_free_ctx_mem(struct bnxt *bp)
4145 {
4146         int i;
4147
4148         if (!bp->ctx || !(bp->ctx->flags & BNXT_CTX_FLAG_INITED))
4149                 return;
4150
4151         bp->ctx->flags &= ~BNXT_CTX_FLAG_INITED;
4152         rte_memzone_free(bp->ctx->qp_mem.ring_mem.mz);
4153         rte_memzone_free(bp->ctx->srq_mem.ring_mem.mz);
4154         rte_memzone_free(bp->ctx->cq_mem.ring_mem.mz);
4155         rte_memzone_free(bp->ctx->vnic_mem.ring_mem.mz);
4156         rte_memzone_free(bp->ctx->stat_mem.ring_mem.mz);
4157         rte_memzone_free(bp->ctx->qp_mem.ring_mem.pg_tbl_mz);
4158         rte_memzone_free(bp->ctx->srq_mem.ring_mem.pg_tbl_mz);
4159         rte_memzone_free(bp->ctx->cq_mem.ring_mem.pg_tbl_mz);
4160         rte_memzone_free(bp->ctx->vnic_mem.ring_mem.pg_tbl_mz);
4161         rte_memzone_free(bp->ctx->stat_mem.ring_mem.pg_tbl_mz);
4162
4163         for (i = 0; i < bp->ctx->tqm_fp_rings_count + 1; i++) {
4164                 if (bp->ctx->tqm_mem[i])
4165                         rte_memzone_free(bp->ctx->tqm_mem[i]->ring_mem.mz);
4166         }
4167
4168         rte_free(bp->ctx);
4169         bp->ctx = NULL;
4170 }
4171
4172 #define bnxt_roundup(x, y)   ((((x) + ((y) - 1)) / (y)) * (y))
4173
4174 #define min_t(type, x, y) ({                    \
4175         type __min1 = (x);                      \
4176         type __min2 = (y);                      \
4177         __min1 < __min2 ? __min1 : __min2; })
4178
4179 #define max_t(type, x, y) ({                    \
4180         type __max1 = (x);                      \
4181         type __max2 = (y);                      \
4182         __max1 > __max2 ? __max1 : __max2; })
4183
4184 #define clamp_t(type, _x, min, max)     min_t(type, max_t(type, _x, min), max)
4185
4186 int bnxt_alloc_ctx_mem(struct bnxt *bp)
4187 {
4188         struct bnxt_ctx_pg_info *ctx_pg;
4189         struct bnxt_ctx_mem_info *ctx;
4190         uint32_t mem_size, ena, entries;
4191         uint32_t entries_sp, min;
4192         int i, rc;
4193
4194         rc = bnxt_hwrm_func_backing_store_qcaps(bp);
4195         if (rc) {
4196                 PMD_DRV_LOG(ERR, "Query context mem capability failed\n");
4197                 return rc;
4198         }
4199         ctx = bp->ctx;
4200         if (!ctx || (ctx->flags & BNXT_CTX_FLAG_INITED))
4201                 return 0;
4202
4203         ctx_pg = &ctx->qp_mem;
4204         ctx_pg->entries = ctx->qp_min_qp1_entries + ctx->qp_max_l2_entries;
4205         mem_size = ctx->qp_entry_size * ctx_pg->entries;
4206         rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "qp_mem", 0);
4207         if (rc)
4208                 return rc;
4209
4210         ctx_pg = &ctx->srq_mem;
4211         ctx_pg->entries = ctx->srq_max_l2_entries;
4212         mem_size = ctx->srq_entry_size * ctx_pg->entries;
4213         rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "srq_mem", 0);
4214         if (rc)
4215                 return rc;
4216
4217         ctx_pg = &ctx->cq_mem;
4218         ctx_pg->entries = ctx->cq_max_l2_entries;
4219         mem_size = ctx->cq_entry_size * ctx_pg->entries;
4220         rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "cq_mem", 0);
4221         if (rc)
4222                 return rc;
4223
4224         ctx_pg = &ctx->vnic_mem;
4225         ctx_pg->entries = ctx->vnic_max_vnic_entries +
4226                 ctx->vnic_max_ring_table_entries;
4227         mem_size = ctx->vnic_entry_size * ctx_pg->entries;
4228         rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "vnic_mem", 0);
4229         if (rc)
4230                 return rc;
4231
4232         ctx_pg = &ctx->stat_mem;
4233         ctx_pg->entries = ctx->stat_max_entries;
4234         mem_size = ctx->stat_entry_size * ctx_pg->entries;
4235         rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "stat_mem", 0);
4236         if (rc)
4237                 return rc;
4238
4239         min = ctx->tqm_min_entries_per_ring;
4240
4241         entries_sp = ctx->qp_max_l2_entries +
4242                      ctx->vnic_max_vnic_entries +
4243                      2 * ctx->qp_min_qp1_entries + min;
4244         entries_sp = bnxt_roundup(entries_sp, ctx->tqm_entries_multiple);
4245
4246         entries = ctx->qp_max_l2_entries + ctx->qp_min_qp1_entries;
4247         entries = bnxt_roundup(entries, ctx->tqm_entries_multiple);
4248         entries = clamp_t(uint32_t, entries, min,
4249                           ctx->tqm_max_entries_per_ring);
4250         for (i = 0, ena = 0; i < ctx->tqm_fp_rings_count + 1; i++) {
4251                 ctx_pg = ctx->tqm_mem[i];
4252                 ctx_pg->entries = i ? entries : entries_sp;
4253                 mem_size = ctx->tqm_entry_size * ctx_pg->entries;
4254                 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "tqm_mem", i);
4255                 if (rc)
4256                         return rc;
4257                 ena |= HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_SP << i;
4258         }
4259
4260         ena |= FUNC_BACKING_STORE_CFG_INPUT_DFLT_ENABLES;
4261         rc = bnxt_hwrm_func_backing_store_cfg(bp, ena);
4262         if (rc)
4263                 PMD_DRV_LOG(ERR,
4264                             "Failed to configure context mem: rc = %d\n", rc);
4265         else
4266                 ctx->flags |= BNXT_CTX_FLAG_INITED;
4267
4268         return rc;
4269 }
4270
4271 static int bnxt_alloc_stats_mem(struct bnxt *bp)
4272 {
4273         struct rte_pci_device *pci_dev = bp->pdev;
4274         char mz_name[RTE_MEMZONE_NAMESIZE];
4275         const struct rte_memzone *mz = NULL;
4276         uint32_t total_alloc_len;
4277         rte_iova_t mz_phys_addr;
4278
4279         if (pci_dev->id.device_id == BROADCOM_DEV_ID_NS2)
4280                 return 0;
4281
4282         snprintf(mz_name, RTE_MEMZONE_NAMESIZE,
4283                  "bnxt_" PCI_PRI_FMT "-%s", pci_dev->addr.domain,
4284                  pci_dev->addr.bus, pci_dev->addr.devid,
4285                  pci_dev->addr.function, "rx_port_stats");
4286         mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0;
4287         mz = rte_memzone_lookup(mz_name);
4288         total_alloc_len =
4289                 RTE_CACHE_LINE_ROUNDUP(sizeof(struct rx_port_stats) +
4290                                        sizeof(struct rx_port_stats_ext) + 512);
4291         if (!mz) {
4292                 mz = rte_memzone_reserve(mz_name, total_alloc_len,
4293                                          SOCKET_ID_ANY,
4294                                          RTE_MEMZONE_2MB |
4295                                          RTE_MEMZONE_SIZE_HINT_ONLY |
4296                                          RTE_MEMZONE_IOVA_CONTIG);
4297                 if (mz == NULL)
4298                         return -ENOMEM;
4299         }
4300         memset(mz->addr, 0, mz->len);
4301         mz_phys_addr = mz->iova;
4302
4303         bp->rx_mem_zone = (const void *)mz;
4304         bp->hw_rx_port_stats = mz->addr;
4305         bp->hw_rx_port_stats_map = mz_phys_addr;
4306
4307         snprintf(mz_name, RTE_MEMZONE_NAMESIZE,
4308                  "bnxt_" PCI_PRI_FMT "-%s", pci_dev->addr.domain,
4309                  pci_dev->addr.bus, pci_dev->addr.devid,
4310                  pci_dev->addr.function, "tx_port_stats");
4311         mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0;
4312         mz = rte_memzone_lookup(mz_name);
4313         total_alloc_len =
4314                 RTE_CACHE_LINE_ROUNDUP(sizeof(struct tx_port_stats) +
4315                                        sizeof(struct tx_port_stats_ext) + 512);
4316         if (!mz) {
4317                 mz = rte_memzone_reserve(mz_name,
4318                                          total_alloc_len,
4319                                          SOCKET_ID_ANY,
4320                                          RTE_MEMZONE_2MB |
4321                                          RTE_MEMZONE_SIZE_HINT_ONLY |
4322                                          RTE_MEMZONE_IOVA_CONTIG);
4323                 if (mz == NULL)
4324                         return -ENOMEM;
4325         }
4326         memset(mz->addr, 0, mz->len);
4327         mz_phys_addr = mz->iova;
4328
4329         bp->tx_mem_zone = (const void *)mz;
4330         bp->hw_tx_port_stats = mz->addr;
4331         bp->hw_tx_port_stats_map = mz_phys_addr;
4332         bp->flags |= BNXT_FLAG_PORT_STATS;
4333
4334         /* Display extended statistics if FW supports it */
4335         if (bp->hwrm_spec_code < HWRM_SPEC_CODE_1_8_4 ||
4336             bp->hwrm_spec_code == HWRM_SPEC_CODE_1_9_0 ||
4337             !(bp->flags & BNXT_FLAG_EXT_STATS_SUPPORTED))
4338                 return 0;
4339
4340         bp->hw_rx_port_stats_ext = (void *)
4341                 ((uint8_t *)bp->hw_rx_port_stats +
4342                  sizeof(struct rx_port_stats));
4343         bp->hw_rx_port_stats_ext_map = bp->hw_rx_port_stats_map +
4344                 sizeof(struct rx_port_stats);
4345         bp->flags |= BNXT_FLAG_EXT_RX_PORT_STATS;
4346
4347         if (bp->hwrm_spec_code < HWRM_SPEC_CODE_1_9_2 ||
4348             bp->flags & BNXT_FLAG_EXT_STATS_SUPPORTED) {
4349                 bp->hw_tx_port_stats_ext = (void *)
4350                         ((uint8_t *)bp->hw_tx_port_stats +
4351                          sizeof(struct tx_port_stats));
4352                 bp->hw_tx_port_stats_ext_map =
4353                         bp->hw_tx_port_stats_map +
4354                         sizeof(struct tx_port_stats);
4355                 bp->flags |= BNXT_FLAG_EXT_TX_PORT_STATS;
4356         }
4357
4358         return 0;
4359 }
4360
4361 static int bnxt_setup_mac_addr(struct rte_eth_dev *eth_dev)
4362 {
4363         struct bnxt *bp = eth_dev->data->dev_private;
4364         int rc = 0;
4365
4366         eth_dev->data->mac_addrs = rte_zmalloc("bnxt_mac_addr_tbl",
4367                                                RTE_ETHER_ADDR_LEN *
4368                                                bp->max_l2_ctx,
4369                                                0);
4370         if (eth_dev->data->mac_addrs == NULL) {
4371                 PMD_DRV_LOG(ERR, "Failed to alloc MAC addr tbl\n");
4372                 return -ENOMEM;
4373         }
4374
4375         if (!BNXT_HAS_DFLT_MAC_SET(bp)) {
4376                 if (BNXT_PF(bp))
4377                         return -EINVAL;
4378
4379                 /* Generate a random MAC address, if none was assigned by PF */
4380                 PMD_DRV_LOG(INFO, "VF MAC address not assigned by Host PF\n");
4381                 bnxt_eth_hw_addr_random(bp->mac_addr);
4382                 PMD_DRV_LOG(INFO,
4383                             "Assign random MAC:%02X:%02X:%02X:%02X:%02X:%02X\n",
4384                             bp->mac_addr[0], bp->mac_addr[1], bp->mac_addr[2],
4385                             bp->mac_addr[3], bp->mac_addr[4], bp->mac_addr[5]);
4386
4387                 rc = bnxt_hwrm_set_mac(bp);
4388                 if (rc)
4389                         return rc;
4390         }
4391
4392         /* Copy the permanent MAC from the FUNC_QCAPS response */
4393         memcpy(&eth_dev->data->mac_addrs[0], bp->mac_addr, RTE_ETHER_ADDR_LEN);
4394
4395         return rc;
4396 }
4397
4398 static int bnxt_restore_dflt_mac(struct bnxt *bp)
4399 {
4400         int rc = 0;
4401
4402         /* MAC is already configured in FW */
4403         if (BNXT_HAS_DFLT_MAC_SET(bp))
4404                 return 0;
4405
4406         /* Restore the old MAC configured */
4407         rc = bnxt_hwrm_set_mac(bp);
4408         if (rc)
4409                 PMD_DRV_LOG(ERR, "Failed to restore MAC address\n");
4410
4411         return rc;
4412 }
4413
4414 static void bnxt_config_vf_req_fwd(struct bnxt *bp)
4415 {
4416         if (!BNXT_PF(bp))
4417                 return;
4418
4419         memset(bp->pf->vf_req_fwd, 0, sizeof(bp->pf->vf_req_fwd));
4420
4421         if (!(bp->fw_cap & BNXT_FW_CAP_LINK_ADMIN))
4422                 BNXT_HWRM_CMD_TO_FORWARD(HWRM_PORT_PHY_QCFG);
4423         BNXT_HWRM_CMD_TO_FORWARD(HWRM_FUNC_CFG);
4424         BNXT_HWRM_CMD_TO_FORWARD(HWRM_FUNC_VF_CFG);
4425         BNXT_HWRM_CMD_TO_FORWARD(HWRM_CFA_L2_FILTER_ALLOC);
4426         BNXT_HWRM_CMD_TO_FORWARD(HWRM_OEM_CMD);
4427 }
4428
4429 uint16_t
4430 bnxt_get_svif(uint16_t port_id, bool func_svif,
4431               enum bnxt_ulp_intf_type type)
4432 {
4433         struct rte_eth_dev *eth_dev;
4434         struct bnxt *bp;
4435
4436         eth_dev = &rte_eth_devices[port_id];
4437         if (BNXT_ETH_DEV_IS_REPRESENTOR(eth_dev)) {
4438                 struct bnxt_representor *vfr = eth_dev->data->dev_private;
4439                 if (!vfr)
4440                         return 0;
4441
4442                 if (type == BNXT_ULP_INTF_TYPE_VF_REP)
4443                         return vfr->svif;
4444
4445                 eth_dev = vfr->parent_dev;
4446         }
4447
4448         bp = eth_dev->data->dev_private;
4449
4450         return func_svif ? bp->func_svif : bp->port_svif;
4451 }
4452
4453 uint16_t
4454 bnxt_get_vnic_id(uint16_t port, enum bnxt_ulp_intf_type type)
4455 {
4456         struct rte_eth_dev *eth_dev;
4457         struct bnxt_vnic_info *vnic;
4458         struct bnxt *bp;
4459
4460         eth_dev = &rte_eth_devices[port];
4461         if (BNXT_ETH_DEV_IS_REPRESENTOR(eth_dev)) {
4462                 struct bnxt_representor *vfr = eth_dev->data->dev_private;
4463                 if (!vfr)
4464                         return 0;
4465
4466                 if (type == BNXT_ULP_INTF_TYPE_VF_REP)
4467                         return vfr->dflt_vnic_id;
4468
4469                 eth_dev = vfr->parent_dev;
4470         }
4471
4472         bp = eth_dev->data->dev_private;
4473
4474         vnic = BNXT_GET_DEFAULT_VNIC(bp);
4475
4476         return vnic->fw_vnic_id;
4477 }
4478
4479 uint16_t
4480 bnxt_get_fw_func_id(uint16_t port, enum bnxt_ulp_intf_type type)
4481 {
4482         struct rte_eth_dev *eth_dev;
4483         struct bnxt *bp;
4484
4485         eth_dev = &rte_eth_devices[port];
4486         if (BNXT_ETH_DEV_IS_REPRESENTOR(eth_dev)) {
4487                 struct bnxt_representor *vfr = eth_dev->data->dev_private;
4488                 if (!vfr)
4489                         return 0;
4490
4491                 if (type == BNXT_ULP_INTF_TYPE_VF_REP)
4492                         return vfr->fw_fid;
4493
4494                 eth_dev = vfr->parent_dev;
4495         }
4496
4497         bp = eth_dev->data->dev_private;
4498
4499         return bp->fw_fid;
4500 }
4501
4502 enum bnxt_ulp_intf_type
4503 bnxt_get_interface_type(uint16_t port)
4504 {
4505         struct rte_eth_dev *eth_dev;
4506         struct bnxt *bp;
4507
4508         eth_dev = &rte_eth_devices[port];
4509         if (BNXT_ETH_DEV_IS_REPRESENTOR(eth_dev))
4510                 return BNXT_ULP_INTF_TYPE_VF_REP;
4511
4512         bp = eth_dev->data->dev_private;
4513         if (BNXT_PF(bp))
4514                 return BNXT_ULP_INTF_TYPE_PF;
4515         else if (BNXT_VF_IS_TRUSTED(bp))
4516                 return BNXT_ULP_INTF_TYPE_TRUSTED_VF;
4517         else if (BNXT_VF(bp))
4518                 return BNXT_ULP_INTF_TYPE_VF;
4519
4520         return BNXT_ULP_INTF_TYPE_INVALID;
4521 }
4522
4523 uint16_t
4524 bnxt_get_phy_port_id(uint16_t port_id)
4525 {
4526         struct bnxt_representor *vfr;
4527         struct rte_eth_dev *eth_dev;
4528         struct bnxt *bp;
4529
4530         eth_dev = &rte_eth_devices[port_id];
4531         if (BNXT_ETH_DEV_IS_REPRESENTOR(eth_dev)) {
4532                 vfr = eth_dev->data->dev_private;
4533                 if (!vfr)
4534                         return 0;
4535
4536                 eth_dev = vfr->parent_dev;
4537         }
4538
4539         bp = eth_dev->data->dev_private;
4540
4541         return BNXT_PF(bp) ? bp->pf->port_id : bp->parent->port_id;
4542 }
4543
4544 uint16_t
4545 bnxt_get_parif(uint16_t port_id, enum bnxt_ulp_intf_type type)
4546 {
4547         struct rte_eth_dev *eth_dev;
4548         struct bnxt *bp;
4549
4550         eth_dev = &rte_eth_devices[port_id];
4551         if (BNXT_ETH_DEV_IS_REPRESENTOR(eth_dev)) {
4552                 struct bnxt_representor *vfr = eth_dev->data->dev_private;
4553                 if (!vfr)
4554                         return 0;
4555
4556                 if (type == BNXT_ULP_INTF_TYPE_VF_REP)
4557                         return vfr->fw_fid - 1;
4558
4559                 eth_dev = vfr->parent_dev;
4560         }
4561
4562         bp = eth_dev->data->dev_private;
4563
4564         return BNXT_PF(bp) ? bp->fw_fid - 1 : bp->parent->fid - 1;
4565 }
4566
4567 uint16_t
4568 bnxt_get_vport(uint16_t port_id)
4569 {
4570         return (1 << bnxt_get_phy_port_id(port_id));
4571 }
4572
4573 static void bnxt_alloc_error_recovery_info(struct bnxt *bp)
4574 {
4575         struct bnxt_error_recovery_info *info = bp->recovery_info;
4576
4577         if (info) {
4578                 if (!(bp->fw_cap & BNXT_FW_CAP_HCOMM_FW_STATUS))
4579                         memset(info, 0, sizeof(*info));
4580                 return;
4581         }
4582
4583         if (!(bp->fw_cap & BNXT_FW_CAP_ERROR_RECOVERY))
4584                 return;
4585
4586         info = rte_zmalloc("bnxt_hwrm_error_recovery_qcfg",
4587                            sizeof(*info), 0);
4588         if (!info)
4589                 bp->fw_cap &= ~BNXT_FW_CAP_ERROR_RECOVERY;
4590
4591         bp->recovery_info = info;
4592 }
4593
4594 static void bnxt_check_fw_status(struct bnxt *bp)
4595 {
4596         uint32_t fw_status;
4597
4598         if (!(bp->recovery_info &&
4599               (bp->fw_cap & BNXT_FW_CAP_HCOMM_FW_STATUS)))
4600                 return;
4601
4602         fw_status = bnxt_read_fw_status_reg(bp, BNXT_FW_STATUS_REG);
4603         if (fw_status != BNXT_FW_STATUS_HEALTHY)
4604                 PMD_DRV_LOG(ERR, "Firmware not responding, status: %#x\n",
4605                             fw_status);
4606 }
4607
4608 static int bnxt_map_hcomm_fw_status_reg(struct bnxt *bp)
4609 {
4610         struct bnxt_error_recovery_info *info = bp->recovery_info;
4611         uint32_t status_loc;
4612         uint32_t sig_ver;
4613
4614         rte_write32(HCOMM_STATUS_STRUCT_LOC, (uint8_t *)bp->bar0 +
4615                     BNXT_GRCPF_REG_WINDOW_BASE_OUT + 4);
4616         sig_ver = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
4617                                    BNXT_GRCP_WINDOW_2_BASE +
4618                                    offsetof(struct hcomm_status,
4619                                             sig_ver)));
4620         /* If the signature is absent, then FW does not support this feature */
4621         if ((sig_ver & HCOMM_STATUS_SIGNATURE_MASK) !=
4622             HCOMM_STATUS_SIGNATURE_VAL)
4623                 return 0;
4624
4625         if (!info) {
4626                 info = rte_zmalloc("bnxt_hwrm_error_recovery_qcfg",
4627                                    sizeof(*info), 0);
4628                 if (!info)
4629                         return -ENOMEM;
4630                 bp->recovery_info = info;
4631         } else {
4632                 memset(info, 0, sizeof(*info));
4633         }
4634
4635         status_loc = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
4636                                       BNXT_GRCP_WINDOW_2_BASE +
4637                                       offsetof(struct hcomm_status,
4638                                                fw_status_loc)));
4639
4640         /* Only pre-map the FW health status GRC register */
4641         if (BNXT_FW_STATUS_REG_TYPE(status_loc) != BNXT_FW_STATUS_REG_TYPE_GRC)
4642                 return 0;
4643
4644         info->status_regs[BNXT_FW_STATUS_REG] = status_loc;
4645         info->mapped_status_regs[BNXT_FW_STATUS_REG] =
4646                 BNXT_GRCP_WINDOW_2_BASE + (status_loc & BNXT_GRCP_OFFSET_MASK);
4647
4648         rte_write32((status_loc & BNXT_GRCP_BASE_MASK), (uint8_t *)bp->bar0 +
4649                     BNXT_GRCPF_REG_WINDOW_BASE_OUT + 4);
4650
4651         bp->fw_cap |= BNXT_FW_CAP_HCOMM_FW_STATUS;
4652
4653         return 0;
4654 }
4655
4656 static int bnxt_init_fw(struct bnxt *bp)
4657 {
4658         uint16_t mtu;
4659         int rc = 0;
4660
4661         bp->fw_cap = 0;
4662
4663         rc = bnxt_map_hcomm_fw_status_reg(bp);
4664         if (rc)
4665                 return rc;
4666
4667         rc = bnxt_hwrm_ver_get(bp, DFLT_HWRM_CMD_TIMEOUT);
4668         if (rc) {
4669                 bnxt_check_fw_status(bp);
4670                 return rc;
4671         }
4672
4673         rc = bnxt_hwrm_func_reset(bp);
4674         if (rc)
4675                 return -EIO;
4676
4677         rc = bnxt_hwrm_vnic_qcaps(bp);
4678         if (rc)
4679                 return rc;
4680
4681         rc = bnxt_hwrm_queue_qportcfg(bp);
4682         if (rc)
4683                 return rc;
4684
4685         /* Get the MAX capabilities for this function.
4686          * This function also allocates context memory for TQM rings and
4687          * informs the firmware about this allocated backing store memory.
4688          */
4689         rc = bnxt_hwrm_func_qcaps(bp);
4690         if (rc)
4691                 return rc;
4692
4693         rc = bnxt_hwrm_func_qcfg(bp, &mtu);
4694         if (rc)
4695                 return rc;
4696
4697         bnxt_hwrm_port_mac_qcfg(bp);
4698
4699         bnxt_hwrm_parent_pf_qcfg(bp);
4700
4701         bnxt_hwrm_port_phy_qcaps(bp);
4702
4703         bnxt_alloc_error_recovery_info(bp);
4704         /* Get the adapter error recovery support info */
4705         rc = bnxt_hwrm_error_recovery_qcfg(bp);
4706         if (rc)
4707                 bp->fw_cap &= ~BNXT_FW_CAP_ERROR_RECOVERY;
4708
4709         bnxt_hwrm_port_led_qcaps(bp);
4710
4711         return 0;
4712 }
4713
4714 static int
4715 bnxt_init_locks(struct bnxt *bp)
4716 {
4717         int err;
4718
4719         err = pthread_mutex_init(&bp->flow_lock, NULL);
4720         if (err) {
4721                 PMD_DRV_LOG(ERR, "Unable to initialize flow_lock\n");
4722                 return err;
4723         }
4724
4725         err = pthread_mutex_init(&bp->def_cp_lock, NULL);
4726         if (err)
4727                 PMD_DRV_LOG(ERR, "Unable to initialize def_cp_lock\n");
4728
4729         err = pthread_mutex_init(&bp->health_check_lock, NULL);
4730         if (err)
4731                 PMD_DRV_LOG(ERR, "Unable to initialize health_check_lock\n");
4732         return err;
4733 }
4734
4735 static int bnxt_init_resources(struct bnxt *bp, bool reconfig_dev)
4736 {
4737         int rc = 0;
4738
4739         rc = bnxt_init_fw(bp);
4740         if (rc)
4741                 return rc;
4742
4743         if (!reconfig_dev) {
4744                 rc = bnxt_setup_mac_addr(bp->eth_dev);
4745                 if (rc)
4746                         return rc;
4747         } else {
4748                 rc = bnxt_restore_dflt_mac(bp);
4749                 if (rc)
4750                         return rc;
4751         }
4752
4753         bnxt_config_vf_req_fwd(bp);
4754
4755         rc = bnxt_hwrm_func_driver_register(bp);
4756         if (rc) {
4757                 PMD_DRV_LOG(ERR, "Failed to register driver");
4758                 return -EBUSY;
4759         }
4760
4761         if (BNXT_PF(bp)) {
4762                 if (bp->pdev->max_vfs) {
4763                         rc = bnxt_hwrm_allocate_vfs(bp, bp->pdev->max_vfs);
4764                         if (rc) {
4765                                 PMD_DRV_LOG(ERR, "Failed to allocate VFs\n");
4766                                 return rc;
4767                         }
4768                 } else {
4769                         rc = bnxt_hwrm_allocate_pf_only(bp);
4770                         if (rc) {
4771                                 PMD_DRV_LOG(ERR,
4772                                             "Failed to allocate PF resources");
4773                                 return rc;
4774                         }
4775                 }
4776         }
4777
4778         rc = bnxt_alloc_mem(bp, reconfig_dev);
4779         if (rc)
4780                 return rc;
4781
4782         rc = bnxt_setup_int(bp);
4783         if (rc)
4784                 return rc;
4785
4786         rc = bnxt_request_int(bp);
4787         if (rc)
4788                 return rc;
4789
4790         rc = bnxt_init_ctx_mem(bp);
4791         if (rc) {
4792                 PMD_DRV_LOG(ERR, "Failed to init adv_flow_counters\n");
4793                 return rc;
4794         }
4795
4796         rc = bnxt_init_locks(bp);
4797         if (rc)
4798                 return rc;
4799
4800         return 0;
4801 }
4802
4803 static int
4804 bnxt_parse_devarg_truflow(__rte_unused const char *key,
4805                           const char *value, void *opaque_arg)
4806 {
4807         struct bnxt *bp = opaque_arg;
4808         unsigned long truflow;
4809         char *end = NULL;
4810
4811         if (!value || !opaque_arg) {
4812                 PMD_DRV_LOG(ERR,
4813                             "Invalid parameter passed to truflow devargs.\n");
4814                 return -EINVAL;
4815         }
4816
4817         truflow = strtoul(value, &end, 10);
4818         if (end == NULL || *end != '\0' ||
4819             (truflow == ULONG_MAX && errno == ERANGE)) {
4820                 PMD_DRV_LOG(ERR,
4821                             "Invalid parameter passed to truflow devargs.\n");
4822                 return -EINVAL;
4823         }
4824
4825         if (BNXT_DEVARG_TRUFLOW_INVALID(truflow)) {
4826                 PMD_DRV_LOG(ERR,
4827                             "Invalid value passed to truflow devargs.\n");
4828                 return -EINVAL;
4829         }
4830
4831         if (truflow) {
4832                 bp->flags |= BNXT_FLAG_TRUFLOW_EN;
4833                 PMD_DRV_LOG(INFO, "Host-based truflow feature enabled.\n");
4834         } else {
4835                 bp->flags &= ~BNXT_FLAG_TRUFLOW_EN;
4836                 PMD_DRV_LOG(INFO, "Host-based truflow feature disabled.\n");
4837         }
4838
4839         return 0;
4840 }
4841
4842 static int
4843 bnxt_parse_devarg_flow_xstat(__rte_unused const char *key,
4844                              const char *value, void *opaque_arg)
4845 {
4846         struct bnxt *bp = opaque_arg;
4847         unsigned long flow_xstat;
4848         char *end = NULL;
4849
4850         if (!value || !opaque_arg) {
4851                 PMD_DRV_LOG(ERR,
4852                             "Invalid parameter passed to flow_xstat devarg.\n");
4853                 return -EINVAL;
4854         }
4855
4856         flow_xstat = strtoul(value, &end, 10);
4857         if (end == NULL || *end != '\0' ||
4858             (flow_xstat == ULONG_MAX && errno == ERANGE)) {
4859                 PMD_DRV_LOG(ERR,
4860                             "Invalid parameter passed to flow_xstat devarg.\n");
4861                 return -EINVAL;
4862         }
4863
4864         if (BNXT_DEVARG_FLOW_XSTAT_INVALID(flow_xstat)) {
4865                 PMD_DRV_LOG(ERR,
4866                             "Invalid value passed to flow_xstat devarg.\n");
4867                 return -EINVAL;
4868         }
4869
4870         bp->flags |= BNXT_FLAG_FLOW_XSTATS_EN;
4871         if (BNXT_FLOW_XSTATS_EN(bp))
4872                 PMD_DRV_LOG(INFO, "flow_xstat feature enabled.\n");
4873
4874         return 0;
4875 }
4876
4877 static int
4878 bnxt_parse_devarg_max_num_kflows(__rte_unused const char *key,
4879                                         const char *value, void *opaque_arg)
4880 {
4881         struct bnxt *bp = opaque_arg;
4882         unsigned long max_num_kflows;
4883         char *end = NULL;
4884
4885         if (!value || !opaque_arg) {
4886                 PMD_DRV_LOG(ERR,
4887                         "Invalid parameter passed to max_num_kflows devarg.\n");
4888                 return -EINVAL;
4889         }
4890
4891         max_num_kflows = strtoul(value, &end, 10);
4892         if (end == NULL || *end != '\0' ||
4893                 (max_num_kflows == ULONG_MAX && errno == ERANGE)) {
4894                 PMD_DRV_LOG(ERR,
4895                         "Invalid parameter passed to max_num_kflows devarg.\n");
4896                 return -EINVAL;
4897         }
4898
4899         if (bnxt_devarg_max_num_kflow_invalid(max_num_kflows)) {
4900                 PMD_DRV_LOG(ERR,
4901                         "Invalid value passed to max_num_kflows devarg.\n");
4902                 return -EINVAL;
4903         }
4904
4905         bp->max_num_kflows = max_num_kflows;
4906         if (bp->max_num_kflows)
4907                 PMD_DRV_LOG(INFO, "max_num_kflows set as %ldK.\n",
4908                                 max_num_kflows);
4909
4910         return 0;
4911 }
4912
4913 static int
4914 bnxt_parse_devarg_rep_is_pf(__rte_unused const char *key,
4915                             const char *value, void *opaque_arg)
4916 {
4917         struct bnxt_representor *vfr_bp = opaque_arg;
4918         unsigned long rep_is_pf;
4919         char *end = NULL;
4920
4921         if (!value || !opaque_arg) {
4922                 PMD_DRV_LOG(ERR,
4923                             "Invalid parameter passed to rep_is_pf devargs.\n");
4924                 return -EINVAL;
4925         }
4926
4927         rep_is_pf = strtoul(value, &end, 10);
4928         if (end == NULL || *end != '\0' ||
4929             (rep_is_pf == ULONG_MAX && errno == ERANGE)) {
4930                 PMD_DRV_LOG(ERR,
4931                             "Invalid parameter passed to rep_is_pf devargs.\n");
4932                 return -EINVAL;
4933         }
4934
4935         if (BNXT_DEVARG_REP_IS_PF_INVALID(rep_is_pf)) {
4936                 PMD_DRV_LOG(ERR,
4937                             "Invalid value passed to rep_is_pf devargs.\n");
4938                 return -EINVAL;
4939         }
4940
4941         vfr_bp->flags |= rep_is_pf;
4942         if (BNXT_REP_PF(vfr_bp))
4943                 PMD_DRV_LOG(INFO, "PF representor\n");
4944         else
4945                 PMD_DRV_LOG(INFO, "VF representor\n");
4946
4947         return 0;
4948 }
4949
4950 static int
4951 bnxt_parse_devarg_rep_based_pf(__rte_unused const char *key,
4952                                const char *value, void *opaque_arg)
4953 {
4954         struct bnxt_representor *vfr_bp = opaque_arg;
4955         unsigned long rep_based_pf;
4956         char *end = NULL;
4957
4958         if (!value || !opaque_arg) {
4959                 PMD_DRV_LOG(ERR,
4960                             "Invalid parameter passed to rep_based_pf "
4961                             "devargs.\n");
4962                 return -EINVAL;
4963         }
4964
4965         rep_based_pf = strtoul(value, &end, 10);
4966         if (end == NULL || *end != '\0' ||
4967             (rep_based_pf == ULONG_MAX && errno == ERANGE)) {
4968                 PMD_DRV_LOG(ERR,
4969                             "Invalid parameter passed to rep_based_pf "
4970                             "devargs.\n");
4971                 return -EINVAL;
4972         }
4973
4974         if (BNXT_DEVARG_REP_BASED_PF_INVALID(rep_based_pf)) {
4975                 PMD_DRV_LOG(ERR,
4976                             "Invalid value passed to rep_based_pf devargs.\n");
4977                 return -EINVAL;
4978         }
4979
4980         vfr_bp->rep_based_pf = rep_based_pf;
4981         vfr_bp->flags |= BNXT_REP_BASED_PF_VALID;
4982
4983         PMD_DRV_LOG(INFO, "rep-based-pf = %d\n", vfr_bp->rep_based_pf);
4984
4985         return 0;
4986 }
4987
4988 static int
4989 bnxt_parse_devarg_rep_q_r2f(__rte_unused const char *key,
4990                             const char *value, void *opaque_arg)
4991 {
4992         struct bnxt_representor *vfr_bp = opaque_arg;
4993         unsigned long rep_q_r2f;
4994         char *end = NULL;
4995
4996         if (!value || !opaque_arg) {
4997                 PMD_DRV_LOG(ERR,
4998                             "Invalid parameter passed to rep_q_r2f "
4999                             "devargs.\n");
5000                 return -EINVAL;
5001         }
5002
5003         rep_q_r2f = strtoul(value, &end, 10);
5004         if (end == NULL || *end != '\0' ||
5005             (rep_q_r2f == ULONG_MAX && errno == ERANGE)) {
5006                 PMD_DRV_LOG(ERR,
5007                             "Invalid parameter passed to rep_q_r2f "
5008                             "devargs.\n");
5009                 return -EINVAL;
5010         }
5011
5012         if (BNXT_DEVARG_REP_Q_R2F_INVALID(rep_q_r2f)) {
5013                 PMD_DRV_LOG(ERR,
5014                             "Invalid value passed to rep_q_r2f devargs.\n");
5015                 return -EINVAL;
5016         }
5017
5018         vfr_bp->rep_q_r2f = rep_q_r2f;
5019         vfr_bp->flags |= BNXT_REP_Q_R2F_VALID;
5020         PMD_DRV_LOG(INFO, "rep-q-r2f = %d\n", vfr_bp->rep_q_r2f);
5021
5022         return 0;
5023 }
5024
5025 static int
5026 bnxt_parse_devarg_rep_q_f2r(__rte_unused const char *key,
5027                             const char *value, void *opaque_arg)
5028 {
5029         struct bnxt_representor *vfr_bp = opaque_arg;
5030         unsigned long rep_q_f2r;
5031         char *end = NULL;
5032
5033         if (!value || !opaque_arg) {
5034                 PMD_DRV_LOG(ERR,
5035                             "Invalid parameter passed to rep_q_f2r "
5036                             "devargs.\n");
5037                 return -EINVAL;
5038         }
5039
5040         rep_q_f2r = strtoul(value, &end, 10);
5041         if (end == NULL || *end != '\0' ||
5042             (rep_q_f2r == ULONG_MAX && errno == ERANGE)) {
5043                 PMD_DRV_LOG(ERR,
5044                             "Invalid parameter passed to rep_q_f2r "
5045                             "devargs.\n");
5046                 return -EINVAL;
5047         }
5048
5049         if (BNXT_DEVARG_REP_Q_F2R_INVALID(rep_q_f2r)) {
5050                 PMD_DRV_LOG(ERR,
5051                             "Invalid value passed to rep_q_f2r devargs.\n");
5052                 return -EINVAL;
5053         }
5054
5055         vfr_bp->rep_q_f2r = rep_q_f2r;
5056         vfr_bp->flags |= BNXT_REP_Q_F2R_VALID;
5057         PMD_DRV_LOG(INFO, "rep-q-f2r = %d\n", vfr_bp->rep_q_f2r);
5058
5059         return 0;
5060 }
5061
5062 static int
5063 bnxt_parse_devarg_rep_fc_r2f(__rte_unused const char *key,
5064                              const char *value, void *opaque_arg)
5065 {
5066         struct bnxt_representor *vfr_bp = opaque_arg;
5067         unsigned long rep_fc_r2f;
5068         char *end = NULL;
5069
5070         if (!value || !opaque_arg) {
5071                 PMD_DRV_LOG(ERR,
5072                             "Invalid parameter passed to rep_fc_r2f "
5073                             "devargs.\n");
5074                 return -EINVAL;
5075         }
5076
5077         rep_fc_r2f = strtoul(value, &end, 10);
5078         if (end == NULL || *end != '\0' ||
5079             (rep_fc_r2f == ULONG_MAX && errno == ERANGE)) {
5080                 PMD_DRV_LOG(ERR,
5081                             "Invalid parameter passed to rep_fc_r2f "
5082                             "devargs.\n");
5083                 return -EINVAL;
5084         }
5085
5086         if (BNXT_DEVARG_REP_FC_R2F_INVALID(rep_fc_r2f)) {
5087                 PMD_DRV_LOG(ERR,
5088                             "Invalid value passed to rep_fc_r2f devargs.\n");
5089                 return -EINVAL;
5090         }
5091
5092         vfr_bp->flags |= BNXT_REP_FC_R2F_VALID;
5093         vfr_bp->rep_fc_r2f = rep_fc_r2f;
5094         PMD_DRV_LOG(INFO, "rep-fc-r2f = %lu\n", rep_fc_r2f);
5095
5096         return 0;
5097 }
5098
5099 static int
5100 bnxt_parse_devarg_rep_fc_f2r(__rte_unused const char *key,
5101                              const char *value, void *opaque_arg)
5102 {
5103         struct bnxt_representor *vfr_bp = opaque_arg;
5104         unsigned long rep_fc_f2r;
5105         char *end = NULL;
5106
5107         if (!value || !opaque_arg) {
5108                 PMD_DRV_LOG(ERR,
5109                             "Invalid parameter passed to rep_fc_f2r "
5110                             "devargs.\n");
5111                 return -EINVAL;
5112         }
5113
5114         rep_fc_f2r = strtoul(value, &end, 10);
5115         if (end == NULL || *end != '\0' ||
5116             (rep_fc_f2r == ULONG_MAX && errno == ERANGE)) {
5117                 PMD_DRV_LOG(ERR,
5118                             "Invalid parameter passed to rep_fc_f2r "
5119                             "devargs.\n");
5120                 return -EINVAL;
5121         }
5122
5123         if (BNXT_DEVARG_REP_FC_F2R_INVALID(rep_fc_f2r)) {
5124                 PMD_DRV_LOG(ERR,
5125                             "Invalid value passed to rep_fc_f2r devargs.\n");
5126                 return -EINVAL;
5127         }
5128
5129         vfr_bp->flags |= BNXT_REP_FC_F2R_VALID;
5130         vfr_bp->rep_fc_f2r = rep_fc_f2r;
5131         PMD_DRV_LOG(INFO, "rep-fc-f2r = %lu\n", rep_fc_f2r);
5132
5133         return 0;
5134 }
5135
5136 static void
5137 bnxt_parse_dev_args(struct bnxt *bp, struct rte_devargs *devargs)
5138 {
5139         struct rte_kvargs *kvlist;
5140
5141         if (devargs == NULL)
5142                 return;
5143
5144         kvlist = rte_kvargs_parse(devargs->args, bnxt_dev_args);
5145         if (kvlist == NULL)
5146                 return;
5147
5148         /*
5149          * Handler for "truflow" devarg.
5150          * Invoked as for ex: "-w 0000:00:0d.0,host-based-truflow=1"
5151          */
5152         rte_kvargs_process(kvlist, BNXT_DEVARG_TRUFLOW,
5153                            bnxt_parse_devarg_truflow, bp);
5154
5155         /*
5156          * Handler for "flow_xstat" devarg.
5157          * Invoked as for ex: "-w 0000:00:0d.0,flow_xstat=1"
5158          */
5159         rte_kvargs_process(kvlist, BNXT_DEVARG_FLOW_XSTAT,
5160                            bnxt_parse_devarg_flow_xstat, bp);
5161
5162         /*
5163          * Handler for "max_num_kflows" devarg.
5164          * Invoked as for ex: "-w 000:00:0d.0,max_num_kflows=32"
5165          */
5166         rte_kvargs_process(kvlist, BNXT_DEVARG_MAX_NUM_KFLOWS,
5167                            bnxt_parse_devarg_max_num_kflows, bp);
5168
5169         rte_kvargs_free(kvlist);
5170 }
5171
5172 static int bnxt_alloc_switch_domain(struct bnxt *bp)
5173 {
5174         int rc = 0;
5175
5176         if (BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp)) {
5177                 rc = rte_eth_switch_domain_alloc(&bp->switch_domain_id);
5178                 if (rc)
5179                         PMD_DRV_LOG(ERR,
5180                                     "Failed to alloc switch domain: %d\n", rc);
5181                 else
5182                         PMD_DRV_LOG(INFO,
5183                                     "Switch domain allocated %d\n",
5184                                     bp->switch_domain_id);
5185         }
5186
5187         return rc;
5188 }
5189
5190 static int
5191 bnxt_dev_init(struct rte_eth_dev *eth_dev, void *params __rte_unused)
5192 {
5193         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
5194         static int version_printed;
5195         struct bnxt *bp;
5196         int rc;
5197
5198         if (version_printed++ == 0)
5199                 PMD_DRV_LOG(INFO, "%s\n", bnxt_version);
5200
5201         eth_dev->dev_ops = &bnxt_dev_ops;
5202         eth_dev->rx_queue_count = bnxt_rx_queue_count_op;
5203         eth_dev->rx_descriptor_status = bnxt_rx_descriptor_status_op;
5204         eth_dev->tx_descriptor_status = bnxt_tx_descriptor_status_op;
5205         eth_dev->rx_pkt_burst = &bnxt_recv_pkts;
5206         eth_dev->tx_pkt_burst = &bnxt_xmit_pkts;
5207
5208         /*
5209          * For secondary processes, we don't initialise any further
5210          * as primary has already done this work.
5211          */
5212         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
5213                 return 0;
5214
5215         rte_eth_copy_pci_info(eth_dev, pci_dev);
5216         eth_dev->data->dev_flags |= RTE_ETH_DEV_AUTOFILL_QUEUE_XSTATS;
5217
5218         bp = eth_dev->data->dev_private;
5219
5220         /* Parse dev arguments passed on when starting the DPDK application. */
5221         bnxt_parse_dev_args(bp, pci_dev->device.devargs);
5222
5223         bp->flags &= ~BNXT_FLAG_RX_VECTOR_PKT_MODE;
5224
5225         if (bnxt_vf_pciid(pci_dev->id.device_id))
5226                 bp->flags |= BNXT_FLAG_VF;
5227
5228         if (bnxt_thor_device(pci_dev->id.device_id))
5229                 bp->flags |= BNXT_FLAG_THOR_CHIP;
5230
5231         if (pci_dev->id.device_id == BROADCOM_DEV_ID_58802 ||
5232             pci_dev->id.device_id == BROADCOM_DEV_ID_58804 ||
5233             pci_dev->id.device_id == BROADCOM_DEV_ID_58808 ||
5234             pci_dev->id.device_id == BROADCOM_DEV_ID_58802_VF)
5235                 bp->flags |= BNXT_FLAG_STINGRAY;
5236
5237         if (BNXT_TRUFLOW_EN(bp)) {
5238                 /* extra mbuf field is required to store CFA code from mark */
5239                 static const struct rte_mbuf_dynfield bnxt_cfa_code_dynfield_desc = {
5240                         .name = RTE_PMD_BNXT_CFA_CODE_DYNFIELD_NAME,
5241                         .size = sizeof(bnxt_cfa_code_dynfield_t),
5242                         .align = __alignof__(bnxt_cfa_code_dynfield_t),
5243                 };
5244                 bnxt_cfa_code_dynfield_offset =
5245                         rte_mbuf_dynfield_register(&bnxt_cfa_code_dynfield_desc);
5246                 if (bnxt_cfa_code_dynfield_offset < 0) {
5247                         PMD_DRV_LOG(ERR,
5248                             "Failed to register mbuf field for TruFlow mark\n");
5249                         return -rte_errno;
5250                 }
5251         }
5252
5253         rc = bnxt_init_board(eth_dev);
5254         if (rc) {
5255                 PMD_DRV_LOG(ERR,
5256                             "Failed to initialize board rc: %x\n", rc);
5257                 return rc;
5258         }
5259
5260         rc = bnxt_alloc_pf_info(bp);
5261         if (rc)
5262                 goto error_free;
5263
5264         rc = bnxt_alloc_link_info(bp);
5265         if (rc)
5266                 goto error_free;
5267
5268         rc = bnxt_alloc_parent_info(bp);
5269         if (rc)
5270                 goto error_free;
5271
5272         rc = bnxt_alloc_hwrm_resources(bp);
5273         if (rc) {
5274                 PMD_DRV_LOG(ERR,
5275                             "Failed to allocate hwrm resource rc: %x\n", rc);
5276                 goto error_free;
5277         }
5278         rc = bnxt_alloc_leds_info(bp);
5279         if (rc)
5280                 goto error_free;
5281
5282         rc = bnxt_alloc_cos_queues(bp);
5283         if (rc)
5284                 goto error_free;
5285
5286         rc = bnxt_init_resources(bp, false);
5287         if (rc)
5288                 goto error_free;
5289
5290         rc = bnxt_alloc_stats_mem(bp);
5291         if (rc)
5292                 goto error_free;
5293
5294         bnxt_alloc_switch_domain(bp);
5295
5296         PMD_DRV_LOG(INFO,
5297                     DRV_MODULE_NAME "found at mem %" PRIX64 ", node addr %pM\n",
5298                     pci_dev->mem_resource[0].phys_addr,
5299                     pci_dev->mem_resource[0].addr);
5300
5301         return 0;
5302
5303 error_free:
5304         bnxt_dev_uninit(eth_dev);
5305         return rc;
5306 }
5307
5308
5309 static void bnxt_free_ctx_mem_buf(struct bnxt_ctx_mem_buf_info *ctx)
5310 {
5311         if (!ctx)
5312                 return;
5313
5314         if (ctx->va)
5315                 rte_free(ctx->va);
5316
5317         ctx->va = NULL;
5318         ctx->dma = RTE_BAD_IOVA;
5319         ctx->ctx_id = BNXT_CTX_VAL_INVAL;
5320 }
5321
5322 static void bnxt_unregister_fc_ctx_mem(struct bnxt *bp)
5323 {
5324         bnxt_hwrm_cfa_counter_cfg(bp, BNXT_DIR_RX,
5325                                   CFA_COUNTER_CFG_IN_COUNTER_TYPE_FC,
5326                                   bp->flow_stat->rx_fc_out_tbl.ctx_id,
5327                                   bp->flow_stat->max_fc,
5328                                   false);
5329
5330         bnxt_hwrm_cfa_counter_cfg(bp, BNXT_DIR_TX,
5331                                   CFA_COUNTER_CFG_IN_COUNTER_TYPE_FC,
5332                                   bp->flow_stat->tx_fc_out_tbl.ctx_id,
5333                                   bp->flow_stat->max_fc,
5334                                   false);
5335
5336         if (bp->flow_stat->rx_fc_in_tbl.ctx_id != BNXT_CTX_VAL_INVAL)
5337                 bnxt_hwrm_ctx_unrgtr(bp, bp->flow_stat->rx_fc_in_tbl.ctx_id);
5338         bp->flow_stat->rx_fc_in_tbl.ctx_id = BNXT_CTX_VAL_INVAL;
5339
5340         if (bp->flow_stat->rx_fc_out_tbl.ctx_id != BNXT_CTX_VAL_INVAL)
5341                 bnxt_hwrm_ctx_unrgtr(bp, bp->flow_stat->rx_fc_out_tbl.ctx_id);
5342         bp->flow_stat->rx_fc_out_tbl.ctx_id = BNXT_CTX_VAL_INVAL;
5343
5344         if (bp->flow_stat->tx_fc_in_tbl.ctx_id != BNXT_CTX_VAL_INVAL)
5345                 bnxt_hwrm_ctx_unrgtr(bp, bp->flow_stat->tx_fc_in_tbl.ctx_id);
5346         bp->flow_stat->tx_fc_in_tbl.ctx_id = BNXT_CTX_VAL_INVAL;
5347
5348         if (bp->flow_stat->tx_fc_out_tbl.ctx_id != BNXT_CTX_VAL_INVAL)
5349                 bnxt_hwrm_ctx_unrgtr(bp, bp->flow_stat->tx_fc_out_tbl.ctx_id);
5350         bp->flow_stat->tx_fc_out_tbl.ctx_id = BNXT_CTX_VAL_INVAL;
5351 }
5352
5353 static void bnxt_uninit_fc_ctx_mem(struct bnxt *bp)
5354 {
5355         bnxt_unregister_fc_ctx_mem(bp);
5356
5357         bnxt_free_ctx_mem_buf(&bp->flow_stat->rx_fc_in_tbl);
5358         bnxt_free_ctx_mem_buf(&bp->flow_stat->rx_fc_out_tbl);
5359         bnxt_free_ctx_mem_buf(&bp->flow_stat->tx_fc_in_tbl);
5360         bnxt_free_ctx_mem_buf(&bp->flow_stat->tx_fc_out_tbl);
5361 }
5362
5363 static void bnxt_uninit_ctx_mem(struct bnxt *bp)
5364 {
5365         if (BNXT_FLOW_XSTATS_EN(bp))
5366                 bnxt_uninit_fc_ctx_mem(bp);
5367 }
5368
5369 static void
5370 bnxt_free_error_recovery_info(struct bnxt *bp)
5371 {
5372         rte_free(bp->recovery_info);
5373         bp->recovery_info = NULL;
5374         bp->fw_cap &= ~BNXT_FW_CAP_ERROR_RECOVERY;
5375 }
5376
5377 static void
5378 bnxt_uninit_locks(struct bnxt *bp)
5379 {
5380         pthread_mutex_destroy(&bp->flow_lock);
5381         pthread_mutex_destroy(&bp->def_cp_lock);
5382         pthread_mutex_destroy(&bp->health_check_lock);
5383         if (bp->rep_info) {
5384                 pthread_mutex_destroy(&bp->rep_info->vfr_lock);
5385                 pthread_mutex_destroy(&bp->rep_info->vfr_start_lock);
5386         }
5387 }
5388
5389 static int
5390 bnxt_uninit_resources(struct bnxt *bp, bool reconfig_dev)
5391 {
5392         int rc;
5393
5394         bnxt_free_int(bp);
5395         bnxt_free_mem(bp, reconfig_dev);
5396
5397         bnxt_hwrm_func_buf_unrgtr(bp);
5398         rte_free(bp->pf->vf_req_buf);
5399
5400         rc = bnxt_hwrm_func_driver_unregister(bp, 0);
5401         bp->flags &= ~BNXT_FLAG_REGISTERED;
5402         bnxt_free_ctx_mem(bp);
5403         if (!reconfig_dev) {
5404                 bnxt_free_hwrm_resources(bp);
5405                 bnxt_free_error_recovery_info(bp);
5406         }
5407
5408         bnxt_uninit_ctx_mem(bp);
5409
5410         bnxt_uninit_locks(bp);
5411         bnxt_free_flow_stats_info(bp);
5412         bnxt_free_rep_info(bp);
5413         rte_free(bp->ptp_cfg);
5414         bp->ptp_cfg = NULL;
5415         return rc;
5416 }
5417
5418 static int
5419 bnxt_dev_uninit(struct rte_eth_dev *eth_dev)
5420 {
5421         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
5422                 return -EPERM;
5423
5424         PMD_DRV_LOG(DEBUG, "Calling Device uninit\n");
5425
5426         if (eth_dev->state != RTE_ETH_DEV_UNUSED)
5427                 bnxt_dev_close_op(eth_dev);
5428
5429         return 0;
5430 }
5431
5432 static int bnxt_pci_remove_dev_with_reps(struct rte_eth_dev *eth_dev)
5433 {
5434         struct bnxt *bp = eth_dev->data->dev_private;
5435         struct rte_eth_dev *vf_rep_eth_dev;
5436         int ret = 0, i;
5437
5438         if (!bp)
5439                 return -EINVAL;
5440
5441         for (i = 0; i < bp->num_reps; i++) {
5442                 vf_rep_eth_dev = bp->rep_info[i].vfr_eth_dev;
5443                 if (!vf_rep_eth_dev)
5444                         continue;
5445                 PMD_DRV_LOG(DEBUG, "BNXT Port:%d VFR pci remove\n",
5446                             vf_rep_eth_dev->data->port_id);
5447                 rte_eth_dev_destroy(vf_rep_eth_dev, bnxt_representor_uninit);
5448         }
5449         PMD_DRV_LOG(DEBUG, "BNXT Port:%d pci remove\n",
5450                     eth_dev->data->port_id);
5451         ret = rte_eth_dev_destroy(eth_dev, bnxt_dev_uninit);
5452
5453         return ret;
5454 }
5455
5456 static void bnxt_free_rep_info(struct bnxt *bp)
5457 {
5458         rte_free(bp->rep_info);
5459         bp->rep_info = NULL;
5460         rte_free(bp->cfa_code_map);
5461         bp->cfa_code_map = NULL;
5462 }
5463
5464 static int bnxt_init_rep_info(struct bnxt *bp)
5465 {
5466         int i = 0, rc;
5467
5468         if (bp->rep_info)
5469                 return 0;
5470
5471         bp->rep_info = rte_zmalloc("bnxt_rep_info",
5472                                    sizeof(bp->rep_info[0]) * BNXT_MAX_VF_REPS,
5473                                    0);
5474         if (!bp->rep_info) {
5475                 PMD_DRV_LOG(ERR, "Failed to alloc memory for rep info\n");
5476                 return -ENOMEM;
5477         }
5478         bp->cfa_code_map = rte_zmalloc("bnxt_cfa_code_map",
5479                                        sizeof(*bp->cfa_code_map) *
5480                                        BNXT_MAX_CFA_CODE, 0);
5481         if (!bp->cfa_code_map) {
5482                 PMD_DRV_LOG(ERR, "Failed to alloc memory for cfa_code_map\n");
5483                 bnxt_free_rep_info(bp);
5484                 return -ENOMEM;
5485         }
5486
5487         for (i = 0; i < BNXT_MAX_CFA_CODE; i++)
5488                 bp->cfa_code_map[i] = BNXT_VF_IDX_INVALID;
5489
5490         rc = pthread_mutex_init(&bp->rep_info->vfr_lock, NULL);
5491         if (rc) {
5492                 PMD_DRV_LOG(ERR, "Unable to initialize vfr_lock\n");
5493                 bnxt_free_rep_info(bp);
5494                 return rc;
5495         }
5496
5497         rc = pthread_mutex_init(&bp->rep_info->vfr_start_lock, NULL);
5498         if (rc) {
5499                 PMD_DRV_LOG(ERR, "Unable to initialize vfr_start_lock\n");
5500                 bnxt_free_rep_info(bp);
5501                 return rc;
5502         }
5503
5504         return rc;
5505 }
5506
5507 static int bnxt_rep_port_probe(struct rte_pci_device *pci_dev,
5508                                struct rte_eth_devargs *eth_da,
5509                                struct rte_eth_dev *backing_eth_dev,
5510                                const char *dev_args)
5511 {
5512         struct rte_eth_dev *vf_rep_eth_dev;
5513         char name[RTE_ETH_NAME_MAX_LEN];
5514         struct bnxt *backing_bp;
5515         uint16_t num_rep;
5516         int i, ret = 0;
5517         struct rte_kvargs *kvlist = NULL;
5518
5519         num_rep = eth_da->nb_representor_ports;
5520         if (num_rep > BNXT_MAX_VF_REPS) {
5521                 PMD_DRV_LOG(ERR, "nb_representor_ports = %d > %d MAX VF REPS\n",
5522                             num_rep, BNXT_MAX_VF_REPS);
5523                 return -EINVAL;
5524         }
5525
5526         if (num_rep >= RTE_MAX_ETHPORTS) {
5527                 PMD_DRV_LOG(ERR,
5528                             "nb_representor_ports = %d > %d MAX ETHPORTS\n",
5529                             num_rep, RTE_MAX_ETHPORTS);
5530                 return -EINVAL;
5531         }
5532
5533         backing_bp = backing_eth_dev->data->dev_private;
5534
5535         if (!(BNXT_PF(backing_bp) || BNXT_VF_IS_TRUSTED(backing_bp))) {
5536                 PMD_DRV_LOG(ERR,
5537                             "Not a PF or trusted VF. No Representor support\n");
5538                 /* Returning an error is not an option.
5539                  * Applications are not handling this correctly
5540                  */
5541                 return 0;
5542         }
5543
5544         if (bnxt_init_rep_info(backing_bp))
5545                 return 0;
5546
5547         for (i = 0; i < num_rep; i++) {
5548                 struct bnxt_representor representor = {
5549                         .vf_id = eth_da->representor_ports[i],
5550                         .switch_domain_id = backing_bp->switch_domain_id,
5551                         .parent_dev = backing_eth_dev
5552                 };
5553
5554                 if (representor.vf_id >= BNXT_MAX_VF_REPS) {
5555                         PMD_DRV_LOG(ERR, "VF-Rep id %d >= %d MAX VF ID\n",
5556                                     representor.vf_id, BNXT_MAX_VF_REPS);
5557                         continue;
5558                 }
5559
5560                 /* representor port net_bdf_port */
5561                 snprintf(name, sizeof(name), "net_%s_representor_%d",
5562                          pci_dev->device.name, eth_da->representor_ports[i]);
5563
5564                 kvlist = rte_kvargs_parse(dev_args, bnxt_dev_args);
5565                 if (kvlist) {
5566                         /*
5567                          * Handler for "rep_is_pf" devarg.
5568                          * Invoked as for ex: "-w 000:00:0d.0,
5569                          * rep-based-pf=<pf index> rep-is-pf=<VF=0 or PF=1>"
5570                          */
5571                         ret = rte_kvargs_process(kvlist, BNXT_DEVARG_REP_IS_PF,
5572                                                  bnxt_parse_devarg_rep_is_pf,
5573                                                  (void *)&representor);
5574                         if (ret) {
5575                                 ret = -EINVAL;
5576                                 goto err;
5577                         }
5578                         /*
5579                          * Handler for "rep_based_pf" devarg.
5580                          * Invoked as for ex: "-w 000:00:0d.0,
5581                          * rep-based-pf=<pf index> rep-is-pf=<VF=0 or PF=1>"
5582                          */
5583                         ret = rte_kvargs_process(kvlist,
5584                                                  BNXT_DEVARG_REP_BASED_PF,
5585                                                  bnxt_parse_devarg_rep_based_pf,
5586                                                  (void *)&representor);
5587                         if (ret) {
5588                                 ret = -EINVAL;
5589                                 goto err;
5590                         }
5591                         /*
5592                          * Handler for "rep_based_pf" devarg.
5593                          * Invoked as for ex: "-w 000:00:0d.0,
5594                          * rep-based-pf=<pf index> rep-is-pf=<VF=0 or PF=1>"
5595                          */
5596                         ret = rte_kvargs_process(kvlist, BNXT_DEVARG_REP_Q_R2F,
5597                                                  bnxt_parse_devarg_rep_q_r2f,
5598                                                  (void *)&representor);
5599                         if (ret) {
5600                                 ret = -EINVAL;
5601                                 goto err;
5602                         }
5603                         /*
5604                          * Handler for "rep_based_pf" devarg.
5605                          * Invoked as for ex: "-w 000:00:0d.0,
5606                          * rep-based-pf=<pf index> rep-is-pf=<VF=0 or PF=1>"
5607                          */
5608                         ret = rte_kvargs_process(kvlist, BNXT_DEVARG_REP_Q_F2R,
5609                                                  bnxt_parse_devarg_rep_q_f2r,
5610                                                  (void *)&representor);
5611                         if (ret) {
5612                                 ret = -EINVAL;
5613                                 goto err;
5614                         }
5615                         /*
5616                          * Handler for "rep_based_pf" devarg.
5617                          * Invoked as for ex: "-w 000:00:0d.0,
5618                          * rep-based-pf=<pf index> rep-is-pf=<VF=0 or PF=1>"
5619                          */
5620                         ret = rte_kvargs_process(kvlist, BNXT_DEVARG_REP_FC_R2F,
5621                                                  bnxt_parse_devarg_rep_fc_r2f,
5622                                                  (void *)&representor);
5623                         if (ret) {
5624                                 ret = -EINVAL;
5625                                 goto err;
5626                         }
5627                         /*
5628                          * Handler for "rep_based_pf" devarg.
5629                          * Invoked as for ex: "-w 000:00:0d.0,
5630                          * rep-based-pf=<pf index> rep-is-pf=<VF=0 or PF=1>"
5631                          */
5632                         ret = rte_kvargs_process(kvlist, BNXT_DEVARG_REP_FC_F2R,
5633                                                  bnxt_parse_devarg_rep_fc_f2r,
5634                                                  (void *)&representor);
5635                         if (ret) {
5636                                 ret = -EINVAL;
5637                                 goto err;
5638                         }
5639                 }
5640
5641                 ret = rte_eth_dev_create(&pci_dev->device, name,
5642                                          sizeof(struct bnxt_representor),
5643                                          NULL, NULL,
5644                                          bnxt_representor_init,
5645                                          &representor);
5646                 if (ret) {
5647                         PMD_DRV_LOG(ERR, "failed to create bnxt vf "
5648                                     "representor %s.", name);
5649                         goto err;
5650                 }
5651
5652                 vf_rep_eth_dev = rte_eth_dev_allocated(name);
5653                 if (!vf_rep_eth_dev) {
5654                         PMD_DRV_LOG(ERR, "Failed to find the eth_dev"
5655                                     " for VF-Rep: %s.", name);
5656                         ret = -ENODEV;
5657                         goto err;
5658                 }
5659
5660                 PMD_DRV_LOG(DEBUG, "BNXT Port:%d VFR pci probe\n",
5661                             backing_eth_dev->data->port_id);
5662                 backing_bp->rep_info[representor.vf_id].vfr_eth_dev =
5663                                                          vf_rep_eth_dev;
5664                 backing_bp->num_reps++;
5665
5666         }
5667
5668         rte_kvargs_free(kvlist);
5669         return 0;
5670
5671 err:
5672         /* If num_rep > 1, then rollback already created
5673          * ports, since we'll be failing the probe anyway
5674          */
5675         if (num_rep > 1)
5676                 bnxt_pci_remove_dev_with_reps(backing_eth_dev);
5677         rte_errno = -ret;
5678         rte_kvargs_free(kvlist);
5679
5680         return ret;
5681 }
5682
5683 static int bnxt_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
5684                           struct rte_pci_device *pci_dev)
5685 {
5686         struct rte_eth_devargs eth_da = { .nb_representor_ports = 0 };
5687         struct rte_eth_dev *backing_eth_dev;
5688         uint16_t num_rep;
5689         int ret = 0;
5690
5691         if (pci_dev->device.devargs) {
5692                 ret = rte_eth_devargs_parse(pci_dev->device.devargs->args,
5693                                             &eth_da);
5694                 if (ret)
5695                         return ret;
5696         }
5697
5698         num_rep = eth_da.nb_representor_ports;
5699         PMD_DRV_LOG(DEBUG, "nb_representor_ports = %d\n",
5700                     num_rep);
5701
5702         /* We could come here after first level of probe is already invoked
5703          * as part of an application bringup(OVS-DPDK vswitchd), so first check
5704          * for already allocated eth_dev for the backing device (PF/Trusted VF)
5705          */
5706         backing_eth_dev = rte_eth_dev_allocated(pci_dev->device.name);
5707         if (backing_eth_dev == NULL) {
5708                 ret = rte_eth_dev_create(&pci_dev->device, pci_dev->device.name,
5709                                          sizeof(struct bnxt),
5710                                          eth_dev_pci_specific_init, pci_dev,
5711                                          bnxt_dev_init, NULL);
5712
5713                 if (ret || !num_rep)
5714                         return ret;
5715
5716                 backing_eth_dev = rte_eth_dev_allocated(pci_dev->device.name);
5717         }
5718         PMD_DRV_LOG(DEBUG, "BNXT Port:%d pci probe\n",
5719                     backing_eth_dev->data->port_id);
5720
5721         if (!num_rep)
5722                 return ret;
5723
5724         /* probe representor ports now */
5725         ret = bnxt_rep_port_probe(pci_dev, &eth_da, backing_eth_dev,
5726                                   pci_dev->device.devargs->args);
5727
5728         return ret;
5729 }
5730
5731 static int bnxt_pci_remove(struct rte_pci_device *pci_dev)
5732 {
5733         struct rte_eth_dev *eth_dev;
5734
5735         eth_dev = rte_eth_dev_allocated(pci_dev->device.name);
5736         if (!eth_dev)
5737                 return 0; /* Invoked typically only by OVS-DPDK, by the
5738                            * time it comes here the eth_dev is already
5739                            * deleted by rte_eth_dev_close(), so returning
5740                            * +ve value will at least help in proper cleanup
5741                            */
5742
5743         PMD_DRV_LOG(DEBUG, "BNXT Port:%d pci remove\n", eth_dev->data->port_id);
5744         if (rte_eal_process_type() == RTE_PROC_PRIMARY) {
5745                 if (eth_dev->data->dev_flags & RTE_ETH_DEV_REPRESENTOR)
5746                         return rte_eth_dev_destroy(eth_dev,
5747                                                    bnxt_representor_uninit);
5748                 else
5749                         return rte_eth_dev_destroy(eth_dev,
5750                                                    bnxt_dev_uninit);
5751         } else {
5752                 return rte_eth_dev_pci_generic_remove(pci_dev, NULL);
5753         }
5754 }
5755
5756 static struct rte_pci_driver bnxt_rte_pmd = {
5757         .id_table = bnxt_pci_id_map,
5758         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC |
5759                         RTE_PCI_DRV_PROBE_AGAIN, /* Needed in case of VF-REPs
5760                                                   * and OVS-DPDK
5761                                                   */
5762         .probe = bnxt_pci_probe,
5763         .remove = bnxt_pci_remove,
5764 };
5765
5766 static bool
5767 is_device_supported(struct rte_eth_dev *dev, struct rte_pci_driver *drv)
5768 {
5769         if (strcmp(dev->device->driver->name, drv->driver.name))
5770                 return false;
5771
5772         return true;
5773 }
5774
5775 bool is_bnxt_supported(struct rte_eth_dev *dev)
5776 {
5777         return is_device_supported(dev, &bnxt_rte_pmd);
5778 }
5779
5780 RTE_LOG_REGISTER(bnxt_logtype_driver, pmd.net.bnxt.driver, NOTICE);
5781 RTE_PMD_REGISTER_PCI(net_bnxt, bnxt_rte_pmd);
5782 RTE_PMD_REGISTER_PCI_TABLE(net_bnxt, bnxt_pci_id_map);
5783 RTE_PMD_REGISTER_KMOD_DEP(net_bnxt, "* igb_uio | uio_pci_generic | vfio-pci");