1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2014-2021 Broadcom
10 #include <ethdev_driver.h>
11 #include <ethdev_pci.h>
12 #include <rte_malloc.h>
13 #include <rte_cycles.h>
14 #include <rte_alarm.h>
15 #include <rte_kvargs.h>
19 #include "bnxt_filter.h"
20 #include "bnxt_hwrm.h"
22 #include "bnxt_reps.h"
23 #include "bnxt_ring.h"
26 #include "bnxt_stats.h"
29 #include "bnxt_vnic.h"
30 #include "hsi_struct_def_dpdk.h"
31 #include "bnxt_nvm_defs.h"
32 #include "bnxt_tf_common.h"
33 #include "ulp_flow_db.h"
34 #include "rte_pmd_bnxt.h"
36 #define DRV_MODULE_NAME "bnxt"
37 static const char bnxt_version[] =
38 "Broadcom NetXtreme driver " DRV_MODULE_NAME;
41 * The set of PCI devices this driver supports
43 static const struct rte_pci_id bnxt_pci_id_map[] = {
44 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM,
45 BROADCOM_DEV_ID_STRATUS_NIC_VF1) },
46 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM,
47 BROADCOM_DEV_ID_STRATUS_NIC_VF2) },
48 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_STRATUS_NIC) },
49 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414_VF) },
50 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57304_VF) },
51 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_NS2) },
52 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57406_VF) },
53 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57407_MF) },
54 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_5741X_VF) },
55 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_5731X_VF) },
56 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_MF) },
57 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57412) },
58 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414) },
59 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_RJ45) },
60 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_RJ45) },
61 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57412_MF) },
62 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57317_RJ45) },
63 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_SFP) },
64 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_SFP) },
65 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57317_SFP) },
66 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414_MF) },
67 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_MF) },
68 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58802) },
69 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58804) },
70 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58808) },
71 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58802_VF) },
72 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57508) },
73 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57504) },
74 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57502) },
75 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57500_VF1) },
76 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57500_VF2) },
77 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57508_MF1) },
78 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57504_MF1) },
79 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57502_MF1) },
80 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57508_MF2) },
81 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57504_MF2) },
82 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57502_MF2) },
83 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58812) },
84 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58814) },
85 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58818) },
86 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58818_VF) },
87 { .vendor_id = 0, /* sentinel */ },
90 #define BNXT_DEVARG_ACCUM_STATS "accum-stats"
91 #define BNXT_DEVARG_FLOW_XSTAT "flow-xstat"
92 #define BNXT_DEVARG_MAX_NUM_KFLOWS "max-num-kflows"
93 #define BNXT_DEVARG_REPRESENTOR "representor"
94 #define BNXT_DEVARG_REP_BASED_PF "rep-based-pf"
95 #define BNXT_DEVARG_REP_IS_PF "rep-is-pf"
96 #define BNXT_DEVARG_REP_Q_R2F "rep-q-r2f"
97 #define BNXT_DEVARG_REP_Q_F2R "rep-q-f2r"
98 #define BNXT_DEVARG_REP_FC_R2F "rep-fc-r2f"
99 #define BNXT_DEVARG_REP_FC_F2R "rep-fc-f2r"
100 #define BNXT_DEVARG_APP_ID "app-id"
102 static const char *const bnxt_dev_args[] = {
103 BNXT_DEVARG_REPRESENTOR,
104 BNXT_DEVARG_ACCUM_STATS,
105 BNXT_DEVARG_FLOW_XSTAT,
106 BNXT_DEVARG_MAX_NUM_KFLOWS,
107 BNXT_DEVARG_REP_BASED_PF,
108 BNXT_DEVARG_REP_IS_PF,
109 BNXT_DEVARG_REP_Q_R2F,
110 BNXT_DEVARG_REP_Q_F2R,
111 BNXT_DEVARG_REP_FC_R2F,
112 BNXT_DEVARG_REP_FC_F2R,
118 * accum-stats == false to disable flow counter accumulation
119 * accum-stats == true to enable flow counter accumulation
121 #define BNXT_DEVARG_ACCUM_STATS_INVALID(accum_stats) ((accum_stats) > 1)
124 * app-id = an non-negative 8-bit number
126 #define BNXT_DEVARG_APP_ID_INVALID(val) ((val) > 255)
129 * flow_xstat == false to disable the feature
130 * flow_xstat == true to enable the feature
132 #define BNXT_DEVARG_FLOW_XSTAT_INVALID(flow_xstat) ((flow_xstat) > 1)
135 * rep_is_pf == false to indicate VF representor
136 * rep_is_pf == true to indicate PF representor
138 #define BNXT_DEVARG_REP_IS_PF_INVALID(rep_is_pf) ((rep_is_pf) > 1)
141 * rep_based_pf == Physical index of the PF
143 #define BNXT_DEVARG_REP_BASED_PF_INVALID(rep_based_pf) ((rep_based_pf) > 15)
145 * rep_q_r2f == Logical COS Queue index for the rep to endpoint direction
147 #define BNXT_DEVARG_REP_Q_R2F_INVALID(rep_q_r2f) ((rep_q_r2f) > 3)
150 * rep_q_f2r == Logical COS Queue index for the endpoint to rep direction
152 #define BNXT_DEVARG_REP_Q_F2R_INVALID(rep_q_f2r) ((rep_q_f2r) > 3)
155 * rep_fc_r2f == Flow control for the representor to endpoint direction
157 #define BNXT_DEVARG_REP_FC_R2F_INVALID(rep_fc_r2f) ((rep_fc_r2f) > 1)
160 * rep_fc_f2r == Flow control for the endpoint to representor direction
162 #define BNXT_DEVARG_REP_FC_F2R_INVALID(rep_fc_f2r) ((rep_fc_f2r) > 1)
164 int bnxt_cfa_code_dynfield_offset = -1;
167 * max_num_kflows must be >= 32
168 * and must be a power-of-2 supported value
169 * return: 1 -> invalid
172 static int bnxt_devarg_max_num_kflow_invalid(uint16_t max_num_kflows)
174 if (max_num_kflows < 32 || !rte_is_power_of_2(max_num_kflows))
179 static int bnxt_vlan_offload_set_op(struct rte_eth_dev *dev, int mask);
180 static int bnxt_dev_uninit(struct rte_eth_dev *eth_dev);
181 static int bnxt_init_resources(struct bnxt *bp, bool reconfig_dev);
182 static int bnxt_uninit_resources(struct bnxt *bp, bool reconfig_dev);
183 static void bnxt_cancel_fw_health_check(struct bnxt *bp);
184 static int bnxt_restore_vlan_filters(struct bnxt *bp);
185 static void bnxt_dev_recover(void *arg);
186 static void bnxt_free_error_recovery_info(struct bnxt *bp);
187 static void bnxt_free_rep_info(struct bnxt *bp);
189 int is_bnxt_in_error(struct bnxt *bp)
191 if (bp->flags & BNXT_FLAG_FATAL_ERROR)
193 if (bp->flags & BNXT_FLAG_FW_RESET)
199 /***********************/
202 * High level utility functions
205 static uint16_t bnxt_rss_ctxts(const struct bnxt *bp)
207 unsigned int num_rss_rings = RTE_MIN(bp->rx_nr_rings,
208 BNXT_RSS_TBL_SIZE_P5);
210 if (!BNXT_CHIP_P5(bp))
213 return RTE_ALIGN_MUL_CEIL(num_rss_rings,
214 BNXT_RSS_ENTRIES_PER_CTX_P5) /
215 BNXT_RSS_ENTRIES_PER_CTX_P5;
218 uint16_t bnxt_rss_hash_tbl_size(const struct bnxt *bp)
220 if (!BNXT_CHIP_P5(bp))
221 return HW_HASH_INDEX_SIZE;
223 return bnxt_rss_ctxts(bp) * BNXT_RSS_ENTRIES_PER_CTX_P5;
226 static void bnxt_free_parent_info(struct bnxt *bp)
228 rte_free(bp->parent);
232 static void bnxt_free_pf_info(struct bnxt *bp)
238 static void bnxt_free_link_info(struct bnxt *bp)
240 rte_free(bp->link_info);
241 bp->link_info = NULL;
244 static void bnxt_free_leds_info(struct bnxt *bp)
253 static void bnxt_free_flow_stats_info(struct bnxt *bp)
255 rte_free(bp->flow_stat);
256 bp->flow_stat = NULL;
259 static void bnxt_free_cos_queues(struct bnxt *bp)
261 rte_free(bp->rx_cos_queue);
262 bp->rx_cos_queue = NULL;
263 rte_free(bp->tx_cos_queue);
264 bp->tx_cos_queue = NULL;
267 static void bnxt_free_mem(struct bnxt *bp, bool reconfig)
269 bnxt_free_filter_mem(bp);
270 bnxt_free_vnic_attributes(bp);
271 bnxt_free_vnic_mem(bp);
273 /* tx/rx rings are configured as part of *_queue_setup callbacks.
274 * If the number of rings change across fw update,
275 * we don't have much choice except to warn the user.
279 bnxt_free_tx_rings(bp);
280 bnxt_free_rx_rings(bp);
282 bnxt_free_async_cp_ring(bp);
283 bnxt_free_rxtx_nq_ring(bp);
285 rte_free(bp->grp_info);
289 static int bnxt_alloc_parent_info(struct bnxt *bp)
291 bp->parent = rte_zmalloc("bnxt_parent_info",
292 sizeof(struct bnxt_parent_info), 0);
293 if (bp->parent == NULL)
299 static int bnxt_alloc_pf_info(struct bnxt *bp)
301 bp->pf = rte_zmalloc("bnxt_pf_info", sizeof(struct bnxt_pf_info), 0);
308 static int bnxt_alloc_link_info(struct bnxt *bp)
311 rte_zmalloc("bnxt_link_info", sizeof(struct bnxt_link_info), 0);
312 if (bp->link_info == NULL)
318 static int bnxt_alloc_leds_info(struct bnxt *bp)
323 bp->leds = rte_zmalloc("bnxt_leds",
324 BNXT_MAX_LED * sizeof(struct bnxt_led_info),
326 if (bp->leds == NULL)
332 static int bnxt_alloc_cos_queues(struct bnxt *bp)
335 rte_zmalloc("bnxt_rx_cosq",
336 BNXT_COS_QUEUE_COUNT *
337 sizeof(struct bnxt_cos_queue_info),
339 if (bp->rx_cos_queue == NULL)
343 rte_zmalloc("bnxt_tx_cosq",
344 BNXT_COS_QUEUE_COUNT *
345 sizeof(struct bnxt_cos_queue_info),
347 if (bp->tx_cos_queue == NULL)
353 static int bnxt_alloc_flow_stats_info(struct bnxt *bp)
355 bp->flow_stat = rte_zmalloc("bnxt_flow_xstat",
356 sizeof(struct bnxt_flow_stat_info), 0);
357 if (bp->flow_stat == NULL)
363 static int bnxt_alloc_mem(struct bnxt *bp, bool reconfig)
367 rc = bnxt_alloc_ring_grps(bp);
371 rc = bnxt_alloc_async_ring_struct(bp);
375 rc = bnxt_alloc_vnic_mem(bp);
379 rc = bnxt_alloc_vnic_attributes(bp);
383 rc = bnxt_alloc_filter_mem(bp);
387 rc = bnxt_alloc_async_cp_ring(bp);
391 rc = bnxt_alloc_rxtx_nq_ring(bp);
395 if (BNXT_FLOW_XSTATS_EN(bp)) {
396 rc = bnxt_alloc_flow_stats_info(bp);
404 bnxt_free_mem(bp, reconfig);
408 static int bnxt_setup_one_vnic(struct bnxt *bp, uint16_t vnic_id)
410 struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
411 struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id];
412 uint64_t rx_offloads = dev_conf->rxmode.offloads;
413 struct bnxt_rx_queue *rxq;
417 rc = bnxt_vnic_grp_alloc(bp, vnic);
421 PMD_DRV_LOG(DEBUG, "vnic[%d] = %p vnic->fw_grp_ids = %p\n",
422 vnic_id, vnic, vnic->fw_grp_ids);
424 rc = bnxt_hwrm_vnic_alloc(bp, vnic);
428 /* Alloc RSS context only if RSS mode is enabled */
429 if (dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS) {
430 int j, nr_ctxs = bnxt_rss_ctxts(bp);
432 /* RSS table size in Thor is 512.
433 * Cap max Rx rings to same value
435 if (bp->rx_nr_rings > BNXT_RSS_TBL_SIZE_P5) {
436 PMD_DRV_LOG(ERR, "RxQ cnt %d > reta_size %d\n",
437 bp->rx_nr_rings, BNXT_RSS_TBL_SIZE_P5);
442 for (j = 0; j < nr_ctxs; j++) {
443 rc = bnxt_hwrm_vnic_ctx_alloc(bp, vnic, j);
449 "HWRM vnic %d ctx %d alloc failure rc: %x\n",
453 vnic->num_lb_ctxts = nr_ctxs;
457 * Firmware sets pf pair in default vnic cfg. If the VLAN strip
458 * setting is not available at this time, it will not be
459 * configured correctly in the CFA.
461 if (rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
462 vnic->vlan_strip = true;
464 vnic->vlan_strip = false;
466 rc = bnxt_hwrm_vnic_cfg(bp, vnic);
470 rc = bnxt_set_hwrm_vnic_filters(bp, vnic);
474 for (j = 0; j < bp->rx_num_qs_per_vnic; j++) {
475 rxq = bp->eth_dev->data->rx_queues[j];
478 "rxq[%d]->vnic=%p vnic->fw_grp_ids=%p\n",
479 j, rxq->vnic, rxq->vnic->fw_grp_ids);
481 if (BNXT_HAS_RING_GRPS(bp) && rxq->rx_deferred_start)
482 rxq->vnic->fw_grp_ids[j] = INVALID_HW_RING_ID;
484 vnic->rx_queue_cnt++;
487 PMD_DRV_LOG(DEBUG, "vnic->rx_queue_cnt = %d\n", vnic->rx_queue_cnt);
489 rc = bnxt_vnic_rss_configure(bp, vnic);
493 bnxt_hwrm_vnic_plcmode_cfg(bp, vnic);
495 rc = bnxt_hwrm_vnic_tpa_cfg(bp, vnic,
496 (rx_offloads & DEV_RX_OFFLOAD_TCP_LRO) ?
503 PMD_DRV_LOG(ERR, "HWRM vnic %d cfg failure rc: %x\n",
508 static int bnxt_register_fc_ctx_mem(struct bnxt *bp)
512 rc = bnxt_hwrm_ctx_rgtr(bp, bp->flow_stat->rx_fc_in_tbl.dma,
513 &bp->flow_stat->rx_fc_in_tbl.ctx_id);
518 "rx_fc_in_tbl.va = %p rx_fc_in_tbl.dma = %p"
519 " rx_fc_in_tbl.ctx_id = %d\n",
520 bp->flow_stat->rx_fc_in_tbl.va,
521 (void *)((uintptr_t)bp->flow_stat->rx_fc_in_tbl.dma),
522 bp->flow_stat->rx_fc_in_tbl.ctx_id);
524 rc = bnxt_hwrm_ctx_rgtr(bp, bp->flow_stat->rx_fc_out_tbl.dma,
525 &bp->flow_stat->rx_fc_out_tbl.ctx_id);
530 "rx_fc_out_tbl.va = %p rx_fc_out_tbl.dma = %p"
531 " rx_fc_out_tbl.ctx_id = %d\n",
532 bp->flow_stat->rx_fc_out_tbl.va,
533 (void *)((uintptr_t)bp->flow_stat->rx_fc_out_tbl.dma),
534 bp->flow_stat->rx_fc_out_tbl.ctx_id);
536 rc = bnxt_hwrm_ctx_rgtr(bp, bp->flow_stat->tx_fc_in_tbl.dma,
537 &bp->flow_stat->tx_fc_in_tbl.ctx_id);
542 "tx_fc_in_tbl.va = %p tx_fc_in_tbl.dma = %p"
543 " tx_fc_in_tbl.ctx_id = %d\n",
544 bp->flow_stat->tx_fc_in_tbl.va,
545 (void *)((uintptr_t)bp->flow_stat->tx_fc_in_tbl.dma),
546 bp->flow_stat->tx_fc_in_tbl.ctx_id);
548 rc = bnxt_hwrm_ctx_rgtr(bp, bp->flow_stat->tx_fc_out_tbl.dma,
549 &bp->flow_stat->tx_fc_out_tbl.ctx_id);
554 "tx_fc_out_tbl.va = %p tx_fc_out_tbl.dma = %p"
555 " tx_fc_out_tbl.ctx_id = %d\n",
556 bp->flow_stat->tx_fc_out_tbl.va,
557 (void *)((uintptr_t)bp->flow_stat->tx_fc_out_tbl.dma),
558 bp->flow_stat->tx_fc_out_tbl.ctx_id);
560 memset(bp->flow_stat->rx_fc_out_tbl.va,
562 bp->flow_stat->rx_fc_out_tbl.size);
563 rc = bnxt_hwrm_cfa_counter_cfg(bp, BNXT_DIR_RX,
564 CFA_COUNTER_CFG_IN_COUNTER_TYPE_FC,
565 bp->flow_stat->rx_fc_out_tbl.ctx_id,
566 bp->flow_stat->max_fc,
571 memset(bp->flow_stat->tx_fc_out_tbl.va,
573 bp->flow_stat->tx_fc_out_tbl.size);
574 rc = bnxt_hwrm_cfa_counter_cfg(bp, BNXT_DIR_TX,
575 CFA_COUNTER_CFG_IN_COUNTER_TYPE_FC,
576 bp->flow_stat->tx_fc_out_tbl.ctx_id,
577 bp->flow_stat->max_fc,
583 static int bnxt_alloc_ctx_mem_buf(struct bnxt *bp, char *type, size_t size,
584 struct bnxt_ctx_mem_buf_info *ctx)
589 ctx->va = rte_zmalloc_socket(type, size, 0,
590 bp->eth_dev->device->numa_node);
593 rte_mem_lock_page(ctx->va);
595 ctx->dma = rte_mem_virt2iova(ctx->va);
596 if (ctx->dma == RTE_BAD_IOVA)
602 static int bnxt_init_fc_ctx_mem(struct bnxt *bp)
604 struct rte_pci_device *pdev = bp->pdev;
605 char type[RTE_MEMZONE_NAMESIZE];
609 max_fc = bp->flow_stat->max_fc;
611 sprintf(type, "bnxt_rx_fc_in_" PCI_PRI_FMT, pdev->addr.domain,
612 pdev->addr.bus, pdev->addr.devid, pdev->addr.function);
613 /* 4 bytes for each counter-id */
614 rc = bnxt_alloc_ctx_mem_buf(bp, type,
616 &bp->flow_stat->rx_fc_in_tbl);
620 sprintf(type, "bnxt_rx_fc_out_" PCI_PRI_FMT, pdev->addr.domain,
621 pdev->addr.bus, pdev->addr.devid, pdev->addr.function);
622 /* 16 bytes for each counter - 8 bytes pkt_count, 8 bytes byte_count */
623 rc = bnxt_alloc_ctx_mem_buf(bp, type,
625 &bp->flow_stat->rx_fc_out_tbl);
629 sprintf(type, "bnxt_tx_fc_in_" PCI_PRI_FMT, pdev->addr.domain,
630 pdev->addr.bus, pdev->addr.devid, pdev->addr.function);
631 /* 4 bytes for each counter-id */
632 rc = bnxt_alloc_ctx_mem_buf(bp, type,
634 &bp->flow_stat->tx_fc_in_tbl);
638 sprintf(type, "bnxt_tx_fc_out_" PCI_PRI_FMT, pdev->addr.domain,
639 pdev->addr.bus, pdev->addr.devid, pdev->addr.function);
640 /* 16 bytes for each counter - 8 bytes pkt_count, 8 bytes byte_count */
641 rc = bnxt_alloc_ctx_mem_buf(bp, type,
643 &bp->flow_stat->tx_fc_out_tbl);
647 rc = bnxt_register_fc_ctx_mem(bp);
652 static int bnxt_init_ctx_mem(struct bnxt *bp)
656 if (!(bp->fw_cap & BNXT_FW_CAP_ADV_FLOW_COUNTERS) ||
657 !(BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp)) ||
658 !BNXT_FLOW_XSTATS_EN(bp))
661 rc = bnxt_hwrm_cfa_counter_qcaps(bp, &bp->flow_stat->max_fc);
665 rc = bnxt_init_fc_ctx_mem(bp);
670 static int bnxt_update_phy_setting(struct bnxt *bp)
672 struct rte_eth_link new;
675 rc = bnxt_get_hwrm_link_config(bp, &new);
677 PMD_DRV_LOG(ERR, "Failed to get link settings\n");
682 * On BCM957508-N2100 adapters, FW will not allow any user other
683 * than BMC to shutdown the port. bnxt_get_hwrm_link_config() call
684 * always returns link up. Force phy update always in that case.
686 if (!new.link_status || IS_BNXT_DEV_957508_N2100(bp)) {
687 rc = bnxt_set_hwrm_link_config(bp, true);
689 PMD_DRV_LOG(ERR, "Failed to update PHY settings\n");
697 static void bnxt_free_prev_ring_stats(struct bnxt *bp)
699 rte_free(bp->prev_rx_ring_stats);
700 rte_free(bp->prev_tx_ring_stats);
702 bp->prev_rx_ring_stats = NULL;
703 bp->prev_tx_ring_stats = NULL;
706 static int bnxt_alloc_prev_ring_stats(struct bnxt *bp)
708 bp->prev_rx_ring_stats = rte_zmalloc("bnxt_prev_rx_ring_stats",
709 sizeof(struct bnxt_ring_stats) *
712 if (bp->prev_rx_ring_stats == NULL)
715 bp->prev_tx_ring_stats = rte_zmalloc("bnxt_prev_tx_ring_stats",
716 sizeof(struct bnxt_ring_stats) *
719 if (bp->prev_tx_ring_stats == NULL)
725 bnxt_free_prev_ring_stats(bp);
729 static int bnxt_start_nic(struct bnxt *bp)
731 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(bp->eth_dev);
732 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
733 uint32_t intr_vector = 0;
734 uint32_t queue_id, base = BNXT_MISC_VEC_ID;
735 uint32_t vec = BNXT_MISC_VEC_ID;
739 if (bp->eth_dev->data->mtu > RTE_ETHER_MTU) {
740 bp->eth_dev->data->dev_conf.rxmode.offloads |=
741 DEV_RX_OFFLOAD_JUMBO_FRAME;
742 bp->flags |= BNXT_FLAG_JUMBO;
744 bp->eth_dev->data->dev_conf.rxmode.offloads &=
745 ~DEV_RX_OFFLOAD_JUMBO_FRAME;
746 bp->flags &= ~BNXT_FLAG_JUMBO;
749 /* THOR does not support ring groups.
750 * But we will use the array to save RSS context IDs.
752 if (BNXT_CHIP_P5(bp))
753 bp->max_ring_grps = BNXT_MAX_RSS_CTXTS_P5;
755 rc = bnxt_alloc_all_hwrm_stat_ctxs(bp);
757 PMD_DRV_LOG(ERR, "HWRM stat ctx alloc failure rc: %x\n", rc);
761 rc = bnxt_alloc_hwrm_rings(bp);
763 PMD_DRV_LOG(ERR, "HWRM ring alloc failure rc: %x\n", rc);
767 rc = bnxt_alloc_all_hwrm_ring_grps(bp);
769 PMD_DRV_LOG(ERR, "HWRM ring grp alloc failure: %x\n", rc);
773 if (!(bp->vnic_cap_flags & BNXT_VNIC_CAP_COS_CLASSIFY))
776 for (j = 0, i = 0; i < BNXT_COS_QUEUE_COUNT; i++) {
777 if (bp->rx_cos_queue[i].id != 0xff) {
778 struct bnxt_vnic_info *vnic = &bp->vnic_info[j++];
782 "Num pools more than FW profile\n");
786 vnic->cos_queue_id = bp->rx_cos_queue[i].id;
792 rc = bnxt_mq_rx_configure(bp);
794 PMD_DRV_LOG(ERR, "MQ mode configure failure rc: %x\n", rc);
799 rc = bnxt_setup_one_vnic(bp, 0);
802 /* VNIC configuration */
803 if (BNXT_RFS_NEEDS_VNIC(bp)) {
804 for (i = 1; i < bp->nr_vnics; i++) {
805 rc = bnxt_setup_one_vnic(bp, i);
811 rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, &bp->vnic_info[0], 0, NULL);
814 "HWRM cfa l2 rx mask failure rc: %x\n", rc);
818 /* check and configure queue intr-vector mapping */
819 if ((rte_intr_cap_multiple(intr_handle) ||
820 !RTE_ETH_DEV_SRIOV(bp->eth_dev).active) &&
821 bp->eth_dev->data->dev_conf.intr_conf.rxq != 0) {
822 intr_vector = bp->eth_dev->data->nb_rx_queues;
823 PMD_DRV_LOG(DEBUG, "intr_vector = %d\n", intr_vector);
824 if (intr_vector > bp->rx_cp_nr_rings) {
825 PMD_DRV_LOG(ERR, "At most %d intr queues supported",
829 rc = rte_intr_efd_enable(intr_handle, intr_vector);
834 if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
835 intr_handle->intr_vec =
836 rte_zmalloc("intr_vec",
837 bp->eth_dev->data->nb_rx_queues *
839 if (intr_handle->intr_vec == NULL) {
840 PMD_DRV_LOG(ERR, "Failed to allocate %d rx_queues"
841 " intr_vec", bp->eth_dev->data->nb_rx_queues);
845 PMD_DRV_LOG(DEBUG, "intr_handle->intr_vec = %p "
846 "intr_handle->nb_efd = %d intr_handle->max_intr = %d\n",
847 intr_handle->intr_vec, intr_handle->nb_efd,
848 intr_handle->max_intr);
849 for (queue_id = 0; queue_id < bp->eth_dev->data->nb_rx_queues;
851 intr_handle->intr_vec[queue_id] =
852 vec + BNXT_RX_VEC_START;
853 if (vec < base + intr_handle->nb_efd - 1)
858 /* enable uio/vfio intr/eventfd mapping */
859 rc = rte_intr_enable(intr_handle);
860 #ifndef RTE_EXEC_ENV_FREEBSD
861 /* In FreeBSD OS, nic_uio driver does not support interrupts */
866 rc = bnxt_update_phy_setting(bp);
870 bp->mark_table = rte_zmalloc("bnxt_mark_table", BNXT_MARK_TABLE_SZ, 0);
872 PMD_DRV_LOG(ERR, "Allocation of mark table failed\n");
877 /* Some of the error status returned by FW may not be from errno.h */
884 static int bnxt_shutdown_nic(struct bnxt *bp)
886 bnxt_free_all_hwrm_resources(bp);
887 bnxt_free_all_filters(bp);
888 bnxt_free_all_vnics(bp);
893 * Device configuration and status function
896 uint32_t bnxt_get_speed_capabilities(struct bnxt *bp)
898 uint32_t link_speed = 0;
899 uint32_t speed_capa = 0;
901 if (bp->link_info == NULL)
904 link_speed = bp->link_info->support_speeds;
906 /* If PAM4 is configured, use PAM4 supported speed */
907 if (link_speed == 0 && bp->link_info->support_pam4_speeds > 0)
908 link_speed = bp->link_info->support_pam4_speeds;
910 if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_100MB)
911 speed_capa |= ETH_LINK_SPEED_100M;
912 if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_100MBHD)
913 speed_capa |= ETH_LINK_SPEED_100M_HD;
914 if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_1GB)
915 speed_capa |= ETH_LINK_SPEED_1G;
916 if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_2_5GB)
917 speed_capa |= ETH_LINK_SPEED_2_5G;
918 if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_10GB)
919 speed_capa |= ETH_LINK_SPEED_10G;
920 if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_20GB)
921 speed_capa |= ETH_LINK_SPEED_20G;
922 if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_25GB)
923 speed_capa |= ETH_LINK_SPEED_25G;
924 if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_40GB)
925 speed_capa |= ETH_LINK_SPEED_40G;
926 if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_50GB)
927 speed_capa |= ETH_LINK_SPEED_50G;
928 if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_100GB)
929 speed_capa |= ETH_LINK_SPEED_100G;
930 if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_PAM4_SPEEDS_50G)
931 speed_capa |= ETH_LINK_SPEED_50G;
932 if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_PAM4_SPEEDS_100G)
933 speed_capa |= ETH_LINK_SPEED_100G;
934 if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_PAM4_SPEEDS_200G)
935 speed_capa |= ETH_LINK_SPEED_200G;
937 if (bp->link_info->auto_mode ==
938 HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_MODE_NONE)
939 speed_capa |= ETH_LINK_SPEED_FIXED;
944 static int bnxt_dev_info_get_op(struct rte_eth_dev *eth_dev,
945 struct rte_eth_dev_info *dev_info)
947 struct rte_pci_device *pdev = RTE_DEV_TO_PCI(eth_dev->device);
948 struct bnxt *bp = eth_dev->data->dev_private;
949 uint16_t max_vnics, i, j, vpool, vrxq;
950 unsigned int max_rx_rings;
953 rc = is_bnxt_in_error(bp);
958 dev_info->max_mac_addrs = bp->max_l2_ctx;
959 dev_info->max_hash_mac_addrs = 0;
961 /* PF/VF specifics */
963 dev_info->max_vfs = pdev->max_vfs;
965 max_rx_rings = bnxt_max_rings(bp);
966 /* For the sake of symmetry, max_rx_queues = max_tx_queues */
967 dev_info->max_rx_queues = max_rx_rings;
968 dev_info->max_tx_queues = max_rx_rings;
969 dev_info->reta_size = bnxt_rss_hash_tbl_size(bp);
970 dev_info->hash_key_size = HW_HASH_KEY_SIZE;
971 max_vnics = bp->max_vnics;
974 dev_info->min_mtu = RTE_ETHER_MIN_MTU;
975 dev_info->max_mtu = BNXT_MAX_MTU;
977 /* Fast path specifics */
978 dev_info->min_rx_bufsize = 1;
979 dev_info->max_rx_pktlen = BNXT_MAX_PKT_LEN;
981 dev_info->rx_offload_capa = BNXT_DEV_RX_OFFLOAD_SUPPORT;
982 if (bp->flags & BNXT_FLAG_PTP_SUPPORTED)
983 dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_TIMESTAMP;
984 dev_info->tx_queue_offload_capa = DEV_TX_OFFLOAD_MBUF_FAST_FREE;
985 dev_info->tx_offload_capa = BNXT_DEV_TX_OFFLOAD_SUPPORT |
986 dev_info->tx_queue_offload_capa;
987 dev_info->flow_type_rss_offloads = BNXT_ETH_RSS_SUPPORT;
989 dev_info->speed_capa = bnxt_get_speed_capabilities(bp);
990 dev_info->dev_capa = RTE_ETH_DEV_CAPA_RUNTIME_RX_QUEUE_SETUP |
991 RTE_ETH_DEV_CAPA_RUNTIME_TX_QUEUE_SETUP;
993 dev_info->default_rxconf = (struct rte_eth_rxconf) {
999 .rx_free_thresh = 32,
1000 .rx_drop_en = BNXT_DEFAULT_RX_DROP_EN,
1003 dev_info->default_txconf = (struct rte_eth_txconf) {
1009 .tx_free_thresh = 32,
1012 eth_dev->data->dev_conf.intr_conf.lsc = 1;
1014 dev_info->rx_desc_lim.nb_min = BNXT_MIN_RING_DESC;
1015 dev_info->rx_desc_lim.nb_max = BNXT_MAX_RX_RING_DESC;
1016 dev_info->tx_desc_lim.nb_min = BNXT_MIN_RING_DESC;
1017 dev_info->tx_desc_lim.nb_max = BNXT_MAX_TX_RING_DESC;
1019 if (BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp)) {
1020 dev_info->switch_info.name = eth_dev->device->name;
1021 dev_info->switch_info.domain_id = bp->switch_domain_id;
1022 dev_info->switch_info.port_id =
1023 BNXT_PF(bp) ? BNXT_SWITCH_PORT_ID_PF :
1024 BNXT_SWITCH_PORT_ID_TRUSTED_VF;
1028 * TODO: default_rxconf, default_txconf, rx_desc_lim, and tx_desc_lim
1029 * need further investigation.
1032 /* VMDq resources */
1033 vpool = 64; /* ETH_64_POOLS */
1034 vrxq = 128; /* ETH_VMDQ_DCB_NUM_QUEUES */
1035 for (i = 0; i < 4; vpool >>= 1, i++) {
1036 if (max_vnics > vpool) {
1037 for (j = 0; j < 5; vrxq >>= 1, j++) {
1038 if (dev_info->max_rx_queues > vrxq) {
1044 /* Not enough resources to support VMDq */
1048 /* Not enough resources to support VMDq */
1052 dev_info->max_vmdq_pools = vpool;
1053 dev_info->vmdq_queue_num = vrxq;
1055 dev_info->vmdq_pool_base = 0;
1056 dev_info->vmdq_queue_base = 0;
1061 /* Configure the device based on the configuration provided */
1062 static int bnxt_dev_configure_op(struct rte_eth_dev *eth_dev)
1064 struct bnxt *bp = eth_dev->data->dev_private;
1065 uint64_t rx_offloads = eth_dev->data->dev_conf.rxmode.offloads;
1068 bp->rx_queues = (void *)eth_dev->data->rx_queues;
1069 bp->tx_queues = (void *)eth_dev->data->tx_queues;
1070 bp->tx_nr_rings = eth_dev->data->nb_tx_queues;
1071 bp->rx_nr_rings = eth_dev->data->nb_rx_queues;
1073 rc = is_bnxt_in_error(bp);
1077 if (BNXT_VF(bp) && (bp->flags & BNXT_FLAG_NEW_RM)) {
1078 rc = bnxt_hwrm_check_vf_rings(bp);
1080 PMD_DRV_LOG(ERR, "HWRM insufficient resources\n");
1084 /* If a resource has already been allocated - in this case
1085 * it is the async completion ring, free it. Reallocate it after
1086 * resource reservation. This will ensure the resource counts
1087 * are calculated correctly.
1090 pthread_mutex_lock(&bp->def_cp_lock);
1092 if (!BNXT_HAS_NQ(bp) && bp->async_cp_ring) {
1093 bnxt_disable_int(bp);
1094 bnxt_free_cp_ring(bp, bp->async_cp_ring);
1097 rc = bnxt_hwrm_func_reserve_vf_resc(bp, false);
1099 PMD_DRV_LOG(ERR, "HWRM resource alloc fail:%x\n", rc);
1100 pthread_mutex_unlock(&bp->def_cp_lock);
1104 if (!BNXT_HAS_NQ(bp) && bp->async_cp_ring) {
1105 rc = bnxt_alloc_async_cp_ring(bp);
1107 pthread_mutex_unlock(&bp->def_cp_lock);
1110 bnxt_enable_int(bp);
1113 pthread_mutex_unlock(&bp->def_cp_lock);
1116 /* Inherit new configurations */
1117 if (eth_dev->data->nb_rx_queues > bp->max_rx_rings ||
1118 eth_dev->data->nb_tx_queues > bp->max_tx_rings ||
1119 eth_dev->data->nb_rx_queues + eth_dev->data->nb_tx_queues
1120 + BNXT_NUM_ASYNC_CPR(bp) > bp->max_cp_rings ||
1121 eth_dev->data->nb_rx_queues + eth_dev->data->nb_tx_queues >
1123 goto resource_error;
1125 if (BNXT_HAS_RING_GRPS(bp) &&
1126 (uint32_t)(eth_dev->data->nb_rx_queues) > bp->max_ring_grps)
1127 goto resource_error;
1129 if (!(eth_dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_RSS) &&
1130 bp->max_vnics < eth_dev->data->nb_rx_queues)
1131 goto resource_error;
1133 bp->rx_cp_nr_rings = bp->rx_nr_rings;
1134 bp->tx_cp_nr_rings = bp->tx_nr_rings;
1136 if (eth_dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG)
1137 rx_offloads |= DEV_RX_OFFLOAD_RSS_HASH;
1138 eth_dev->data->dev_conf.rxmode.offloads = rx_offloads;
1140 if (rx_offloads & DEV_RX_OFFLOAD_JUMBO_FRAME) {
1141 eth_dev->data->mtu =
1142 eth_dev->data->dev_conf.rxmode.max_rx_pkt_len -
1143 RTE_ETHER_HDR_LEN - RTE_ETHER_CRC_LEN - VLAN_TAG_SIZE *
1145 bnxt_mtu_set_op(eth_dev, eth_dev->data->mtu);
1151 "Insufficient resources to support requested config\n");
1153 "Num Queues Requested: Tx %d, Rx %d\n",
1154 eth_dev->data->nb_tx_queues,
1155 eth_dev->data->nb_rx_queues);
1157 "MAX: TxQ %d, RxQ %d, CQ %d Stat %d, Grp %d, Vnic %d\n",
1158 bp->max_tx_rings, bp->max_rx_rings, bp->max_cp_rings,
1159 bp->max_stat_ctx, bp->max_ring_grps, bp->max_vnics);
1163 void bnxt_print_link_info(struct rte_eth_dev *eth_dev)
1165 struct rte_eth_link *link = ð_dev->data->dev_link;
1167 if (link->link_status)
1168 PMD_DRV_LOG(INFO, "Port %d Link Up - speed %u Mbps - %s\n",
1169 eth_dev->data->port_id,
1170 (uint32_t)link->link_speed,
1171 (link->link_duplex == ETH_LINK_FULL_DUPLEX) ?
1172 ("full-duplex") : ("half-duplex\n"));
1174 PMD_DRV_LOG(INFO, "Port %d Link Down\n",
1175 eth_dev->data->port_id);
1179 * Determine whether the current configuration requires support for scattered
1180 * receive; return 1 if scattered receive is required and 0 if not.
1182 static int bnxt_scattered_rx(struct rte_eth_dev *eth_dev)
1187 if (eth_dev->data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_SCATTER)
1190 if (eth_dev->data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_TCP_LRO)
1193 for (i = 0; i < eth_dev->data->nb_rx_queues; i++) {
1194 struct bnxt_rx_queue *rxq = eth_dev->data->rx_queues[i];
1196 buf_size = (uint16_t)(rte_pktmbuf_data_room_size(rxq->mb_pool) -
1197 RTE_PKTMBUF_HEADROOM);
1198 if (eth_dev->data->dev_conf.rxmode.max_rx_pkt_len > buf_size)
1204 static eth_rx_burst_t
1205 bnxt_receive_function(struct rte_eth_dev *eth_dev)
1207 struct bnxt *bp = eth_dev->data->dev_private;
1209 /* Disable vector mode RX for Stingray2 for now */
1210 if (BNXT_CHIP_SR2(bp)) {
1211 bp->flags &= ~BNXT_FLAG_RX_VECTOR_PKT_MODE;
1212 return bnxt_recv_pkts;
1215 #if (defined(RTE_ARCH_X86) || defined(RTE_ARCH_ARM64)) && \
1216 !defined(RTE_LIBRTE_IEEE1588)
1218 /* Vector mode receive cannot be enabled if scattered rx is in use. */
1219 if (eth_dev->data->scattered_rx)
1223 * Vector mode receive cannot be enabled if Truflow is enabled or if
1224 * asynchronous completions and receive completions can be placed in
1225 * the same completion ring.
1227 if (BNXT_TRUFLOW_EN(bp) || !BNXT_NUM_ASYNC_CPR(bp))
1231 * Vector mode receive cannot be enabled if any receive offloads outside
1232 * a limited subset have been enabled.
1234 if (eth_dev->data->dev_conf.rxmode.offloads &
1235 ~(DEV_RX_OFFLOAD_VLAN_STRIP |
1236 DEV_RX_OFFLOAD_KEEP_CRC |
1237 DEV_RX_OFFLOAD_JUMBO_FRAME |
1238 DEV_RX_OFFLOAD_IPV4_CKSUM |
1239 DEV_RX_OFFLOAD_UDP_CKSUM |
1240 DEV_RX_OFFLOAD_TCP_CKSUM |
1241 DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM |
1242 DEV_RX_OFFLOAD_OUTER_UDP_CKSUM |
1243 DEV_RX_OFFLOAD_RSS_HASH |
1244 DEV_RX_OFFLOAD_VLAN_FILTER))
1247 #if defined(RTE_ARCH_X86) && defined(CC_AVX2_SUPPORT)
1248 if (rte_vect_get_max_simd_bitwidth() >= RTE_VECT_SIMD_256 &&
1249 rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX2) == 1) {
1251 "Using AVX2 vector mode receive for port %d\n",
1252 eth_dev->data->port_id);
1253 bp->flags |= BNXT_FLAG_RX_VECTOR_PKT_MODE;
1254 return bnxt_recv_pkts_vec_avx2;
1257 if (rte_vect_get_max_simd_bitwidth() >= RTE_VECT_SIMD_128) {
1259 "Using SSE vector mode receive for port %d\n",
1260 eth_dev->data->port_id);
1261 bp->flags |= BNXT_FLAG_RX_VECTOR_PKT_MODE;
1262 return bnxt_recv_pkts_vec;
1266 PMD_DRV_LOG(INFO, "Vector mode receive disabled for port %d\n",
1267 eth_dev->data->port_id);
1269 "Port %d scatter: %d rx offload: %" PRIX64 "\n",
1270 eth_dev->data->port_id,
1271 eth_dev->data->scattered_rx,
1272 eth_dev->data->dev_conf.rxmode.offloads);
1274 bp->flags &= ~BNXT_FLAG_RX_VECTOR_PKT_MODE;
1275 return bnxt_recv_pkts;
1278 static eth_tx_burst_t
1279 bnxt_transmit_function(struct rte_eth_dev *eth_dev)
1281 struct bnxt *bp = eth_dev->data->dev_private;
1283 /* Disable vector mode TX for Stingray2 for now */
1284 if (BNXT_CHIP_SR2(bp))
1285 return bnxt_xmit_pkts;
1287 #if defined(RTE_ARCH_X86) || defined(RTE_ARCH_ARM64) && \
1288 !defined(RTE_LIBRTE_IEEE1588)
1289 uint64_t offloads = eth_dev->data->dev_conf.txmode.offloads;
1292 * Vector mode transmit can be enabled only if not using scatter rx
1295 if (eth_dev->data->scattered_rx ||
1296 (offloads & ~DEV_TX_OFFLOAD_MBUF_FAST_FREE) ||
1297 BNXT_TRUFLOW_EN(bp))
1300 #if defined(RTE_ARCH_X86) && defined(CC_AVX2_SUPPORT)
1301 if (rte_vect_get_max_simd_bitwidth() >= RTE_VECT_SIMD_256 &&
1302 rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX2) == 1) {
1304 "Using AVX2 vector mode transmit for port %d\n",
1305 eth_dev->data->port_id);
1306 return bnxt_xmit_pkts_vec_avx2;
1309 if (rte_vect_get_max_simd_bitwidth() >= RTE_VECT_SIMD_128) {
1311 "Using SSE vector mode transmit for port %d\n",
1312 eth_dev->data->port_id);
1313 return bnxt_xmit_pkts_vec;
1317 PMD_DRV_LOG(INFO, "Vector mode transmit disabled for port %d\n",
1318 eth_dev->data->port_id);
1320 "Port %d scatter: %d tx offload: %" PRIX64 "\n",
1321 eth_dev->data->port_id,
1322 eth_dev->data->scattered_rx,
1325 return bnxt_xmit_pkts;
1328 static int bnxt_handle_if_change_status(struct bnxt *bp)
1332 /* Since fw has undergone a reset and lost all contexts,
1333 * set fatal flag to not issue hwrm during cleanup
1335 bp->flags |= BNXT_FLAG_FATAL_ERROR;
1336 bnxt_uninit_resources(bp, true);
1338 /* clear fatal flag so that re-init happens */
1339 bp->flags &= ~BNXT_FLAG_FATAL_ERROR;
1340 rc = bnxt_init_resources(bp, true);
1342 bp->flags &= ~BNXT_FLAG_IF_CHANGE_HOT_FW_RESET_DONE;
1347 static int bnxt_dev_set_link_up_op(struct rte_eth_dev *eth_dev)
1349 struct bnxt *bp = eth_dev->data->dev_private;
1352 if (!BNXT_SINGLE_PF(bp))
1355 if (!bp->link_info->link_up)
1356 rc = bnxt_set_hwrm_link_config(bp, true);
1358 eth_dev->data->dev_link.link_status = 1;
1360 bnxt_print_link_info(eth_dev);
1364 static int bnxt_dev_set_link_down_op(struct rte_eth_dev *eth_dev)
1366 struct bnxt *bp = eth_dev->data->dev_private;
1368 if (!BNXT_SINGLE_PF(bp))
1371 eth_dev->data->dev_link.link_status = 0;
1372 bnxt_set_hwrm_link_config(bp, false);
1373 bp->link_info->link_up = 0;
1378 static void bnxt_free_switch_domain(struct bnxt *bp)
1382 if (!(BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp)))
1385 rc = rte_eth_switch_domain_free(bp->switch_domain_id);
1387 PMD_DRV_LOG(ERR, "free switch domain:%d fail: %d\n",
1388 bp->switch_domain_id, rc);
1391 static void bnxt_ptp_get_current_time(void *arg)
1393 struct bnxt *bp = arg;
1394 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
1397 rc = is_bnxt_in_error(bp);
1404 bnxt_hwrm_port_ts_query(bp, BNXT_PTP_FLAGS_CURRENT_TIME,
1405 &ptp->current_time);
1407 rc = rte_eal_alarm_set(US_PER_S, bnxt_ptp_get_current_time, (void *)bp);
1409 PMD_DRV_LOG(ERR, "Failed to re-schedule PTP alarm\n");
1410 bp->flags2 &= ~BNXT_FLAGS2_PTP_ALARM_SCHEDULED;
1414 static int bnxt_schedule_ptp_alarm(struct bnxt *bp)
1416 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
1419 if (bp->flags2 & BNXT_FLAGS2_PTP_ALARM_SCHEDULED)
1422 bnxt_hwrm_port_ts_query(bp, BNXT_PTP_FLAGS_CURRENT_TIME,
1423 &ptp->current_time);
1425 rc = rte_eal_alarm_set(US_PER_S, bnxt_ptp_get_current_time, (void *)bp);
1429 static void bnxt_cancel_ptp_alarm(struct bnxt *bp)
1431 if (bp->flags2 & BNXT_FLAGS2_PTP_ALARM_SCHEDULED) {
1432 rte_eal_alarm_cancel(bnxt_ptp_get_current_time, (void *)bp);
1433 bp->flags2 &= ~BNXT_FLAGS2_PTP_ALARM_SCHEDULED;
1437 static void bnxt_ptp_stop(struct bnxt *bp)
1439 bnxt_cancel_ptp_alarm(bp);
1440 bp->flags2 &= ~BNXT_FLAGS2_PTP_TIMESYNC_ENABLED;
1443 static int bnxt_ptp_start(struct bnxt *bp)
1447 rc = bnxt_schedule_ptp_alarm(bp);
1449 PMD_DRV_LOG(ERR, "Failed to schedule PTP alarm\n");
1451 bp->flags2 |= BNXT_FLAGS2_PTP_TIMESYNC_ENABLED;
1452 bp->flags2 |= BNXT_FLAGS2_PTP_ALARM_SCHEDULED;
1458 static int bnxt_dev_stop(struct rte_eth_dev *eth_dev)
1460 struct bnxt *bp = eth_dev->data->dev_private;
1461 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1462 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1463 struct rte_eth_link link;
1466 eth_dev->data->dev_started = 0;
1467 eth_dev->data->scattered_rx = 0;
1469 /* Prevent crashes when queues are still in use */
1470 eth_dev->rx_pkt_burst = &bnxt_dummy_recv_pkts;
1471 eth_dev->tx_pkt_burst = &bnxt_dummy_xmit_pkts;
1473 bnxt_disable_int(bp);
1475 /* disable uio/vfio intr/eventfd mapping */
1476 rte_intr_disable(intr_handle);
1478 /* Stop the child representors for this device */
1479 ret = bnxt_rep_stop_all(bp);
1483 /* delete the bnxt ULP port details */
1484 bnxt_ulp_port_deinit(bp);
1486 bnxt_cancel_fw_health_check(bp);
1488 if (BNXT_P5_PTP_TIMESYNC_ENABLED(bp))
1489 bnxt_cancel_ptp_alarm(bp);
1491 /* Do not bring link down during reset recovery */
1492 if (!is_bnxt_in_error(bp)) {
1493 bnxt_dev_set_link_down_op(eth_dev);
1494 /* Wait for link to be reset */
1495 if (BNXT_SINGLE_PF(bp))
1497 /* clear the recorded link status */
1498 memset(&link, 0, sizeof(link));
1499 rte_eth_linkstatus_set(eth_dev, &link);
1502 /* Clean queue intr-vector mapping */
1503 rte_intr_efd_disable(intr_handle);
1504 if (intr_handle->intr_vec != NULL) {
1505 rte_free(intr_handle->intr_vec);
1506 intr_handle->intr_vec = NULL;
1509 bnxt_hwrm_port_clr_stats(bp);
1510 bnxt_free_tx_mbufs(bp);
1511 bnxt_free_rx_mbufs(bp);
1512 /* Process any remaining notifications in default completion queue */
1513 bnxt_int_handler(eth_dev);
1514 bnxt_shutdown_nic(bp);
1515 bnxt_hwrm_if_change(bp, false);
1517 bnxt_free_prev_ring_stats(bp);
1518 rte_free(bp->mark_table);
1519 bp->mark_table = NULL;
1521 bp->flags &= ~BNXT_FLAG_RX_VECTOR_PKT_MODE;
1522 bp->rx_cosq_cnt = 0;
1523 /* All filters are deleted on a port stop. */
1524 if (BNXT_FLOW_XSTATS_EN(bp))
1525 bp->flow_stat->flow_count = 0;
1530 /* Unload the driver, release resources */
1531 static int bnxt_dev_stop_op(struct rte_eth_dev *eth_dev)
1533 struct bnxt *bp = eth_dev->data->dev_private;
1535 pthread_mutex_lock(&bp->err_recovery_lock);
1536 if (bp->flags & BNXT_FLAG_FW_RESET) {
1538 "Adapter recovering from error..Please retry\n");
1539 pthread_mutex_unlock(&bp->err_recovery_lock);
1542 pthread_mutex_unlock(&bp->err_recovery_lock);
1544 return bnxt_dev_stop(eth_dev);
1547 static int bnxt_dev_start_op(struct rte_eth_dev *eth_dev)
1549 struct bnxt *bp = eth_dev->data->dev_private;
1550 uint64_t rx_offloads = eth_dev->data->dev_conf.rxmode.offloads;
1552 int rc, retry_cnt = BNXT_IF_CHANGE_RETRY_COUNT;
1554 if (!eth_dev->data->nb_tx_queues || !eth_dev->data->nb_rx_queues) {
1555 PMD_DRV_LOG(ERR, "Queues are not configured yet!\n");
1559 if (bp->rx_cp_nr_rings > RTE_ETHDEV_QUEUE_STAT_CNTRS)
1561 "RxQ cnt %d > RTE_ETHDEV_QUEUE_STAT_CNTRS %d\n",
1562 bp->rx_cp_nr_rings, RTE_ETHDEV_QUEUE_STAT_CNTRS);
1565 rc = bnxt_hwrm_if_change(bp, true);
1566 if (rc == 0 || rc != -EAGAIN)
1569 rte_delay_ms(BNXT_IF_CHANGE_RETRY_INTERVAL);
1570 } while (retry_cnt--);
1575 if (bp->flags & BNXT_FLAG_IF_CHANGE_HOT_FW_RESET_DONE) {
1576 rc = bnxt_handle_if_change_status(bp);
1581 bnxt_enable_int(bp);
1583 eth_dev->data->scattered_rx = bnxt_scattered_rx(eth_dev);
1585 rc = bnxt_start_nic(bp);
1589 rc = bnxt_alloc_prev_ring_stats(bp);
1593 eth_dev->data->dev_started = 1;
1595 bnxt_link_update_op(eth_dev, 1);
1597 if (rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER)
1598 vlan_mask |= ETH_VLAN_FILTER_MASK;
1599 if (rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
1600 vlan_mask |= ETH_VLAN_STRIP_MASK;
1601 rc = bnxt_vlan_offload_set_op(eth_dev, vlan_mask);
1605 /* Initialize bnxt ULP port details */
1606 rc = bnxt_ulp_port_init(bp);
1610 eth_dev->rx_pkt_burst = bnxt_receive_function(eth_dev);
1611 eth_dev->tx_pkt_burst = bnxt_transmit_function(eth_dev);
1613 bnxt_schedule_fw_health_check(bp);
1615 if (BNXT_P5_PTP_TIMESYNC_ENABLED(bp))
1616 bnxt_schedule_ptp_alarm(bp);
1621 bnxt_dev_stop(eth_dev);
1626 bnxt_uninit_locks(struct bnxt *bp)
1628 pthread_mutex_destroy(&bp->flow_lock);
1629 pthread_mutex_destroy(&bp->def_cp_lock);
1630 pthread_mutex_destroy(&bp->health_check_lock);
1631 pthread_mutex_destroy(&bp->err_recovery_lock);
1633 pthread_mutex_destroy(&bp->rep_info->vfr_lock);
1634 pthread_mutex_destroy(&bp->rep_info->vfr_start_lock);
1638 static void bnxt_drv_uninit(struct bnxt *bp)
1640 bnxt_free_leds_info(bp);
1641 bnxt_free_cos_queues(bp);
1642 bnxt_free_link_info(bp);
1643 bnxt_free_parent_info(bp);
1644 bnxt_uninit_locks(bp);
1646 rte_memzone_free((const struct rte_memzone *)bp->tx_mem_zone);
1647 bp->tx_mem_zone = NULL;
1648 rte_memzone_free((const struct rte_memzone *)bp->rx_mem_zone);
1649 bp->rx_mem_zone = NULL;
1651 bnxt_free_vf_info(bp);
1652 bnxt_free_pf_info(bp);
1654 rte_free(bp->grp_info);
1655 bp->grp_info = NULL;
1658 static int bnxt_dev_close_op(struct rte_eth_dev *eth_dev)
1660 struct bnxt *bp = eth_dev->data->dev_private;
1663 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1666 pthread_mutex_lock(&bp->err_recovery_lock);
1667 if (bp->flags & BNXT_FLAG_FW_RESET) {
1669 "Adapter recovering from error...Please retry\n");
1670 pthread_mutex_unlock(&bp->err_recovery_lock);
1673 pthread_mutex_unlock(&bp->err_recovery_lock);
1675 /* cancel the recovery handler before remove dev */
1676 rte_eal_alarm_cancel(bnxt_dev_reset_and_resume, (void *)bp);
1677 rte_eal_alarm_cancel(bnxt_dev_recover, (void *)bp);
1678 bnxt_cancel_fc_thread(bp);
1680 if (eth_dev->data->dev_started)
1681 ret = bnxt_dev_stop(eth_dev);
1683 bnxt_uninit_resources(bp, false);
1685 bnxt_drv_uninit(bp);
1690 static void bnxt_mac_addr_remove_op(struct rte_eth_dev *eth_dev,
1693 struct bnxt *bp = eth_dev->data->dev_private;
1694 uint64_t pool_mask = eth_dev->data->mac_pool_sel[index];
1695 struct bnxt_vnic_info *vnic;
1696 struct bnxt_filter_info *filter, *temp_filter;
1699 if (is_bnxt_in_error(bp))
1703 * Loop through all VNICs from the specified filter flow pools to
1704 * remove the corresponding MAC addr filter
1706 for (i = 0; i < bp->nr_vnics; i++) {
1707 if (!(pool_mask & (1ULL << i)))
1710 vnic = &bp->vnic_info[i];
1711 filter = STAILQ_FIRST(&vnic->filter);
1713 temp_filter = STAILQ_NEXT(filter, next);
1714 if (filter->mac_index == index) {
1715 STAILQ_REMOVE(&vnic->filter, filter,
1716 bnxt_filter_info, next);
1717 bnxt_hwrm_clear_l2_filter(bp, filter);
1718 bnxt_free_filter(bp, filter);
1720 filter = temp_filter;
1725 static int bnxt_add_mac_filter(struct bnxt *bp, struct bnxt_vnic_info *vnic,
1726 struct rte_ether_addr *mac_addr, uint32_t index,
1729 struct bnxt_filter_info *filter;
1732 /* Attach requested MAC address to the new l2_filter */
1733 STAILQ_FOREACH(filter, &vnic->filter, next) {
1734 if (filter->mac_index == index) {
1736 "MAC addr already existed for pool %d\n",
1742 filter = bnxt_alloc_filter(bp);
1744 PMD_DRV_LOG(ERR, "L2 filter alloc failed\n");
1748 /* bnxt_alloc_filter copies default MAC to filter->l2_addr. So,
1749 * if the MAC that's been programmed now is a different one, then,
1750 * copy that addr to filter->l2_addr
1753 memcpy(filter->l2_addr, mac_addr, RTE_ETHER_ADDR_LEN);
1754 filter->flags |= HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_OUTERMOST;
1756 rc = bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id, filter);
1758 filter->mac_index = index;
1759 if (filter->mac_index == 0)
1760 STAILQ_INSERT_HEAD(&vnic->filter, filter, next);
1762 STAILQ_INSERT_TAIL(&vnic->filter, filter, next);
1764 bnxt_free_filter(bp, filter);
1770 static int bnxt_mac_addr_add_op(struct rte_eth_dev *eth_dev,
1771 struct rte_ether_addr *mac_addr,
1772 uint32_t index, uint32_t pool)
1774 struct bnxt *bp = eth_dev->data->dev_private;
1775 struct bnxt_vnic_info *vnic = &bp->vnic_info[pool];
1778 rc = is_bnxt_in_error(bp);
1782 if (BNXT_VF(bp) && !BNXT_VF_IS_TRUSTED(bp)) {
1783 PMD_DRV_LOG(ERR, "Cannot add MAC address to a VF interface\n");
1788 PMD_DRV_LOG(ERR, "VNIC not found for pool %d!\n", pool);
1792 /* Filter settings will get applied when port is started */
1793 if (!eth_dev->data->dev_started)
1796 rc = bnxt_add_mac_filter(bp, vnic, mac_addr, index, pool);
1801 int bnxt_link_update_op(struct rte_eth_dev *eth_dev, int wait_to_complete)
1804 struct bnxt *bp = eth_dev->data->dev_private;
1805 struct rte_eth_link new;
1806 int cnt = wait_to_complete ? BNXT_MAX_LINK_WAIT_CNT :
1807 BNXT_MIN_LINK_WAIT_CNT;
1809 rc = is_bnxt_in_error(bp);
1813 memset(&new, 0, sizeof(new));
1815 if (bp->link_info == NULL)
1819 /* Retrieve link info from hardware */
1820 rc = bnxt_get_hwrm_link_config(bp, &new);
1822 new.link_speed = ETH_LINK_SPEED_100M;
1823 new.link_duplex = ETH_LINK_FULL_DUPLEX;
1825 "Failed to retrieve link rc = 0x%x!\n", rc);
1829 if (!wait_to_complete || new.link_status)
1832 rte_delay_ms(BNXT_LINK_WAIT_INTERVAL);
1835 /* Only single function PF can bring phy down.
1836 * When port is stopped, report link down for VF/MH/NPAR functions.
1838 if (!BNXT_SINGLE_PF(bp) && !eth_dev->data->dev_started)
1839 memset(&new, 0, sizeof(new));
1842 /* Timed out or success */
1843 if (new.link_status != eth_dev->data->dev_link.link_status ||
1844 new.link_speed != eth_dev->data->dev_link.link_speed) {
1845 rte_eth_linkstatus_set(eth_dev, &new);
1846 bnxt_print_link_info(eth_dev);
1852 static int bnxt_promiscuous_enable_op(struct rte_eth_dev *eth_dev)
1854 struct bnxt *bp = eth_dev->data->dev_private;
1855 struct bnxt_vnic_info *vnic;
1859 rc = is_bnxt_in_error(bp);
1863 /* Filter settings will get applied when port is started */
1864 if (!eth_dev->data->dev_started)
1867 if (bp->vnic_info == NULL)
1870 vnic = BNXT_GET_DEFAULT_VNIC(bp);
1872 old_flags = vnic->flags;
1873 vnic->flags |= BNXT_VNIC_INFO_PROMISC;
1874 rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1876 vnic->flags = old_flags;
1881 static int bnxt_promiscuous_disable_op(struct rte_eth_dev *eth_dev)
1883 struct bnxt *bp = eth_dev->data->dev_private;
1884 struct bnxt_vnic_info *vnic;
1888 rc = is_bnxt_in_error(bp);
1892 /* Filter settings will get applied when port is started */
1893 if (!eth_dev->data->dev_started)
1896 if (bp->vnic_info == NULL)
1899 vnic = BNXT_GET_DEFAULT_VNIC(bp);
1901 old_flags = vnic->flags;
1902 vnic->flags &= ~BNXT_VNIC_INFO_PROMISC;
1903 rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1905 vnic->flags = old_flags;
1910 static int bnxt_allmulticast_enable_op(struct rte_eth_dev *eth_dev)
1912 struct bnxt *bp = eth_dev->data->dev_private;
1913 struct bnxt_vnic_info *vnic;
1917 rc = is_bnxt_in_error(bp);
1921 /* Filter settings will get applied when port is started */
1922 if (!eth_dev->data->dev_started)
1925 if (bp->vnic_info == NULL)
1928 vnic = BNXT_GET_DEFAULT_VNIC(bp);
1930 old_flags = vnic->flags;
1931 vnic->flags |= BNXT_VNIC_INFO_ALLMULTI;
1932 rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1934 vnic->flags = old_flags;
1939 static int bnxt_allmulticast_disable_op(struct rte_eth_dev *eth_dev)
1941 struct bnxt *bp = eth_dev->data->dev_private;
1942 struct bnxt_vnic_info *vnic;
1946 rc = is_bnxt_in_error(bp);
1950 /* Filter settings will get applied when port is started */
1951 if (!eth_dev->data->dev_started)
1954 if (bp->vnic_info == NULL)
1957 vnic = BNXT_GET_DEFAULT_VNIC(bp);
1959 old_flags = vnic->flags;
1960 vnic->flags &= ~BNXT_VNIC_INFO_ALLMULTI;
1961 rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1963 vnic->flags = old_flags;
1968 /* Return bnxt_rx_queue pointer corresponding to a given rxq. */
1969 static struct bnxt_rx_queue *bnxt_qid_to_rxq(struct bnxt *bp, uint16_t qid)
1971 if (qid >= bp->rx_nr_rings)
1974 return bp->eth_dev->data->rx_queues[qid];
1977 /* Return rxq corresponding to a given rss table ring/group ID. */
1978 static uint16_t bnxt_rss_to_qid(struct bnxt *bp, uint16_t fwr)
1980 struct bnxt_rx_queue *rxq;
1983 if (!BNXT_HAS_RING_GRPS(bp)) {
1984 for (i = 0; i < bp->rx_nr_rings; i++) {
1985 rxq = bp->eth_dev->data->rx_queues[i];
1986 if (rxq->rx_ring->rx_ring_struct->fw_ring_id == fwr)
1990 for (i = 0; i < bp->rx_nr_rings; i++) {
1991 if (bp->grp_info[i].fw_grp_id == fwr)
1996 return INVALID_HW_RING_ID;
1999 static int bnxt_reta_update_op(struct rte_eth_dev *eth_dev,
2000 struct rte_eth_rss_reta_entry64 *reta_conf,
2003 struct bnxt *bp = eth_dev->data->dev_private;
2004 struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
2005 struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp);
2006 uint16_t tbl_size = bnxt_rss_hash_tbl_size(bp);
2010 rc = is_bnxt_in_error(bp);
2014 if (!vnic->rss_table)
2017 if (!(dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG))
2020 if (reta_size != tbl_size) {
2021 PMD_DRV_LOG(ERR, "The configured hash table lookup size "
2022 "(%d) must equal the size supported by the hardware "
2023 "(%d)\n", reta_size, tbl_size);
2027 for (i = 0; i < reta_size; i++) {
2028 struct bnxt_rx_queue *rxq;
2030 idx = i / RTE_RETA_GROUP_SIZE;
2031 sft = i % RTE_RETA_GROUP_SIZE;
2033 if (!(reta_conf[idx].mask & (1ULL << sft)))
2036 rxq = bnxt_qid_to_rxq(bp, reta_conf[idx].reta[sft]);
2038 PMD_DRV_LOG(ERR, "Invalid ring in reta_conf.\n");
2042 if (BNXT_CHIP_P5(bp)) {
2043 vnic->rss_table[i * 2] =
2044 rxq->rx_ring->rx_ring_struct->fw_ring_id;
2045 vnic->rss_table[i * 2 + 1] =
2046 rxq->cp_ring->cp_ring_struct->fw_ring_id;
2048 vnic->rss_table[i] =
2049 vnic->fw_grp_ids[reta_conf[idx].reta[sft]];
2053 rc = bnxt_hwrm_vnic_rss_cfg(bp, vnic);
2057 static int bnxt_reta_query_op(struct rte_eth_dev *eth_dev,
2058 struct rte_eth_rss_reta_entry64 *reta_conf,
2061 struct bnxt *bp = eth_dev->data->dev_private;
2062 struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp);
2063 uint16_t tbl_size = bnxt_rss_hash_tbl_size(bp);
2064 uint16_t idx, sft, i;
2067 rc = is_bnxt_in_error(bp);
2073 if (!vnic->rss_table)
2076 if (reta_size != tbl_size) {
2077 PMD_DRV_LOG(ERR, "The configured hash table lookup size "
2078 "(%d) must equal the size supported by the hardware "
2079 "(%d)\n", reta_size, tbl_size);
2083 for (idx = 0, i = 0; i < reta_size; i++) {
2084 idx = i / RTE_RETA_GROUP_SIZE;
2085 sft = i % RTE_RETA_GROUP_SIZE;
2087 if (reta_conf[idx].mask & (1ULL << sft)) {
2090 if (BNXT_CHIP_P5(bp))
2091 qid = bnxt_rss_to_qid(bp,
2092 vnic->rss_table[i * 2]);
2094 qid = bnxt_rss_to_qid(bp, vnic->rss_table[i]);
2096 if (qid == INVALID_HW_RING_ID) {
2097 PMD_DRV_LOG(ERR, "Inv. entry in rss table.\n");
2100 reta_conf[idx].reta[sft] = qid;
2107 static int bnxt_rss_hash_update_op(struct rte_eth_dev *eth_dev,
2108 struct rte_eth_rss_conf *rss_conf)
2110 struct bnxt *bp = eth_dev->data->dev_private;
2111 struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
2112 struct bnxt_vnic_info *vnic;
2115 rc = is_bnxt_in_error(bp);
2120 * If RSS enablement were different than dev_configure,
2121 * then return -EINVAL
2123 if (dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG) {
2124 if (!rss_conf->rss_hf)
2125 PMD_DRV_LOG(ERR, "Hash type NONE\n");
2127 if (rss_conf->rss_hf & BNXT_ETH_RSS_SUPPORT)
2131 bp->flags |= BNXT_FLAG_UPDATE_HASH;
2132 memcpy(ð_dev->data->dev_conf.rx_adv_conf.rss_conf,
2136 /* Update the default RSS VNIC(s) */
2137 vnic = BNXT_GET_DEFAULT_VNIC(bp);
2138 vnic->hash_type = bnxt_rte_to_hwrm_hash_types(rss_conf->rss_hf);
2140 bnxt_rte_to_hwrm_hash_level(bp, rss_conf->rss_hf,
2141 ETH_RSS_LEVEL(rss_conf->rss_hf));
2144 * If hashkey is not specified, use the previously configured
2147 if (!rss_conf->rss_key)
2150 if (rss_conf->rss_key_len != HW_HASH_KEY_SIZE) {
2152 "Invalid hashkey length, should be %d bytes\n",
2156 memcpy(vnic->rss_hash_key, rss_conf->rss_key, rss_conf->rss_key_len);
2159 rc = bnxt_hwrm_vnic_rss_cfg(bp, vnic);
2163 static int bnxt_rss_hash_conf_get_op(struct rte_eth_dev *eth_dev,
2164 struct rte_eth_rss_conf *rss_conf)
2166 struct bnxt *bp = eth_dev->data->dev_private;
2167 struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp);
2169 uint32_t hash_types;
2171 rc = is_bnxt_in_error(bp);
2175 /* RSS configuration is the same for all VNICs */
2176 if (vnic && vnic->rss_hash_key) {
2177 if (rss_conf->rss_key) {
2178 len = rss_conf->rss_key_len <= HW_HASH_KEY_SIZE ?
2179 rss_conf->rss_key_len : HW_HASH_KEY_SIZE;
2180 memcpy(rss_conf->rss_key, vnic->rss_hash_key, len);
2183 hash_types = vnic->hash_type;
2184 rss_conf->rss_hf = 0;
2185 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV4) {
2186 rss_conf->rss_hf |= ETH_RSS_IPV4;
2187 hash_types &= ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV4;
2189 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV4) {
2190 rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP;
2192 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV4;
2194 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV4) {
2195 rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
2197 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV4;
2199 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6) {
2200 rss_conf->rss_hf |= ETH_RSS_IPV6;
2201 hash_types &= ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6;
2203 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV6) {
2204 rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV6_TCP;
2206 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV6;
2208 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV6) {
2209 rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;
2211 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV6;
2215 bnxt_hwrm_to_rte_rss_level(bp, vnic->hash_mode);
2219 "Unknown RSS config from firmware (%08x), RSS disabled",
2224 rss_conf->rss_hf = 0;
2229 static int bnxt_flow_ctrl_get_op(struct rte_eth_dev *dev,
2230 struct rte_eth_fc_conf *fc_conf)
2232 struct bnxt *bp = dev->data->dev_private;
2233 struct rte_eth_link link_info;
2236 rc = is_bnxt_in_error(bp);
2240 rc = bnxt_get_hwrm_link_config(bp, &link_info);
2244 memset(fc_conf, 0, sizeof(*fc_conf));
2245 if (bp->link_info->auto_pause)
2246 fc_conf->autoneg = 1;
2247 switch (bp->link_info->pause) {
2249 fc_conf->mode = RTE_FC_NONE;
2251 case HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_TX:
2252 fc_conf->mode = RTE_FC_TX_PAUSE;
2254 case HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_RX:
2255 fc_conf->mode = RTE_FC_RX_PAUSE;
2257 case (HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_TX |
2258 HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_RX):
2259 fc_conf->mode = RTE_FC_FULL;
2265 static int bnxt_flow_ctrl_set_op(struct rte_eth_dev *dev,
2266 struct rte_eth_fc_conf *fc_conf)
2268 struct bnxt *bp = dev->data->dev_private;
2271 rc = is_bnxt_in_error(bp);
2275 if (!BNXT_SINGLE_PF(bp)) {
2277 "Flow Control Settings cannot be modified on VF or on shared PF\n");
2281 switch (fc_conf->mode) {
2283 bp->link_info->auto_pause = 0;
2284 bp->link_info->force_pause = 0;
2286 case RTE_FC_RX_PAUSE:
2287 if (fc_conf->autoneg) {
2288 bp->link_info->auto_pause =
2289 HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_RX;
2290 bp->link_info->force_pause = 0;
2292 bp->link_info->auto_pause = 0;
2293 bp->link_info->force_pause =
2294 HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_RX;
2297 case RTE_FC_TX_PAUSE:
2298 if (fc_conf->autoneg) {
2299 bp->link_info->auto_pause =
2300 HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_TX;
2301 bp->link_info->force_pause = 0;
2303 bp->link_info->auto_pause = 0;
2304 bp->link_info->force_pause =
2305 HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_TX;
2309 if (fc_conf->autoneg) {
2310 bp->link_info->auto_pause =
2311 HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_TX |
2312 HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_RX;
2313 bp->link_info->force_pause = 0;
2315 bp->link_info->auto_pause = 0;
2316 bp->link_info->force_pause =
2317 HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_TX |
2318 HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_RX;
2322 return bnxt_set_hwrm_link_config(bp, true);
2325 /* Add UDP tunneling port */
2327 bnxt_udp_tunnel_port_add_op(struct rte_eth_dev *eth_dev,
2328 struct rte_eth_udp_tunnel *udp_tunnel)
2330 struct bnxt *bp = eth_dev->data->dev_private;
2331 uint16_t tunnel_type = 0;
2334 rc = is_bnxt_in_error(bp);
2338 switch (udp_tunnel->prot_type) {
2339 case RTE_TUNNEL_TYPE_VXLAN:
2340 if (bp->vxlan_port_cnt) {
2341 PMD_DRV_LOG(ERR, "Tunnel Port %d already programmed\n",
2342 udp_tunnel->udp_port);
2343 if (bp->vxlan_port != udp_tunnel->udp_port) {
2344 PMD_DRV_LOG(ERR, "Only one port allowed\n");
2347 bp->vxlan_port_cnt++;
2351 HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_VXLAN;
2352 bp->vxlan_port_cnt++;
2354 case RTE_TUNNEL_TYPE_GENEVE:
2355 if (bp->geneve_port_cnt) {
2356 PMD_DRV_LOG(ERR, "Tunnel Port %d already programmed\n",
2357 udp_tunnel->udp_port);
2358 if (bp->geneve_port != udp_tunnel->udp_port) {
2359 PMD_DRV_LOG(ERR, "Only one port allowed\n");
2362 bp->geneve_port_cnt++;
2366 HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_GENEVE;
2367 bp->geneve_port_cnt++;
2370 PMD_DRV_LOG(ERR, "Tunnel type is not supported\n");
2373 rc = bnxt_hwrm_tunnel_dst_port_alloc(bp, udp_tunnel->udp_port,
2379 bnxt_udp_tunnel_port_del_op(struct rte_eth_dev *eth_dev,
2380 struct rte_eth_udp_tunnel *udp_tunnel)
2382 struct bnxt *bp = eth_dev->data->dev_private;
2383 uint16_t tunnel_type = 0;
2387 rc = is_bnxt_in_error(bp);
2391 switch (udp_tunnel->prot_type) {
2392 case RTE_TUNNEL_TYPE_VXLAN:
2393 if (!bp->vxlan_port_cnt) {
2394 PMD_DRV_LOG(ERR, "No Tunnel port configured yet\n");
2397 if (bp->vxlan_port != udp_tunnel->udp_port) {
2398 PMD_DRV_LOG(ERR, "Req Port: %d. Configured port: %d\n",
2399 udp_tunnel->udp_port, bp->vxlan_port);
2402 if (--bp->vxlan_port_cnt)
2406 HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN;
2407 port = bp->vxlan_fw_dst_port_id;
2409 case RTE_TUNNEL_TYPE_GENEVE:
2410 if (!bp->geneve_port_cnt) {
2411 PMD_DRV_LOG(ERR, "No Tunnel port configured yet\n");
2414 if (bp->geneve_port != udp_tunnel->udp_port) {
2415 PMD_DRV_LOG(ERR, "Req Port: %d. Configured port: %d\n",
2416 udp_tunnel->udp_port, bp->geneve_port);
2419 if (--bp->geneve_port_cnt)
2423 HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_GENEVE;
2424 port = bp->geneve_fw_dst_port_id;
2427 PMD_DRV_LOG(ERR, "Tunnel type is not supported\n");
2431 rc = bnxt_hwrm_tunnel_dst_port_free(bp, port, tunnel_type);
2435 static int bnxt_del_vlan_filter(struct bnxt *bp, uint16_t vlan_id)
2437 struct bnxt_filter_info *filter;
2438 struct bnxt_vnic_info *vnic;
2440 uint32_t chk = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN;
2442 vnic = BNXT_GET_DEFAULT_VNIC(bp);
2443 filter = STAILQ_FIRST(&vnic->filter);
2445 /* Search for this matching MAC+VLAN filter */
2446 if (bnxt_vlan_filter_exists(bp, filter, chk, vlan_id)) {
2447 /* Delete the filter */
2448 rc = bnxt_hwrm_clear_l2_filter(bp, filter);
2451 STAILQ_REMOVE(&vnic->filter, filter,
2452 bnxt_filter_info, next);
2453 bnxt_free_filter(bp, filter);
2455 "Deleted vlan filter for %d\n",
2459 filter = STAILQ_NEXT(filter, next);
2464 static int bnxt_add_vlan_filter(struct bnxt *bp, uint16_t vlan_id)
2466 struct bnxt_filter_info *filter;
2467 struct bnxt_vnic_info *vnic;
2469 uint32_t en = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN |
2470 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN_MASK;
2471 uint32_t chk = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN;
2473 /* Implementation notes on the use of VNIC in this command:
2475 * By default, these filters belong to default vnic for the function.
2476 * Once these filters are set up, only destination VNIC can be modified.
2477 * If the destination VNIC is not specified in this command,
2478 * then the HWRM shall only create an l2 context id.
2481 vnic = BNXT_GET_DEFAULT_VNIC(bp);
2482 filter = STAILQ_FIRST(&vnic->filter);
2483 /* Check if the VLAN has already been added */
2485 if (bnxt_vlan_filter_exists(bp, filter, chk, vlan_id))
2488 filter = STAILQ_NEXT(filter, next);
2491 /* No match found. Alloc a fresh filter and issue the L2_FILTER_ALLOC
2492 * command to create MAC+VLAN filter with the right flags, enables set.
2494 filter = bnxt_alloc_filter(bp);
2497 "MAC/VLAN filter alloc failed\n");
2500 /* MAC + VLAN ID filter */
2501 /* If l2_ivlan == 0 and l2_ivlan_mask != 0, only
2502 * untagged packets are received
2504 * If l2_ivlan != 0 and l2_ivlan_mask != 0, untagged
2505 * packets and only the programmed vlan's packets are received
2507 filter->l2_ivlan = vlan_id;
2508 filter->l2_ivlan_mask = 0x0FFF;
2509 filter->enables |= en;
2510 filter->flags |= HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_OUTERMOST;
2512 rc = bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id, filter);
2514 /* Free the newly allocated filter as we were
2515 * not able to create the filter in hardware.
2517 bnxt_free_filter(bp, filter);
2521 filter->mac_index = 0;
2522 /* Add this new filter to the list */
2524 STAILQ_INSERT_HEAD(&vnic->filter, filter, next);
2526 STAILQ_INSERT_TAIL(&vnic->filter, filter, next);
2529 "Added Vlan filter for %d\n", vlan_id);
2533 static int bnxt_vlan_filter_set_op(struct rte_eth_dev *eth_dev,
2534 uint16_t vlan_id, int on)
2536 struct bnxt *bp = eth_dev->data->dev_private;
2539 rc = is_bnxt_in_error(bp);
2543 if (!eth_dev->data->dev_started) {
2544 PMD_DRV_LOG(ERR, "port must be started before setting vlan\n");
2548 /* These operations apply to ALL existing MAC/VLAN filters */
2550 return bnxt_add_vlan_filter(bp, vlan_id);
2552 return bnxt_del_vlan_filter(bp, vlan_id);
2555 static int bnxt_del_dflt_mac_filter(struct bnxt *bp,
2556 struct bnxt_vnic_info *vnic)
2558 struct bnxt_filter_info *filter;
2561 filter = STAILQ_FIRST(&vnic->filter);
2563 if (filter->mac_index == 0 &&
2564 !memcmp(filter->l2_addr, bp->mac_addr,
2565 RTE_ETHER_ADDR_LEN)) {
2566 rc = bnxt_hwrm_clear_l2_filter(bp, filter);
2568 STAILQ_REMOVE(&vnic->filter, filter,
2569 bnxt_filter_info, next);
2570 bnxt_free_filter(bp, filter);
2574 filter = STAILQ_NEXT(filter, next);
2580 bnxt_config_vlan_hw_filter(struct bnxt *bp, uint64_t rx_offloads)
2582 struct bnxt_vnic_info *vnic;
2586 vnic = BNXT_GET_DEFAULT_VNIC(bp);
2587 if (!(rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER)) {
2588 /* Remove any VLAN filters programmed */
2589 for (i = 0; i < RTE_ETHER_MAX_VLAN_ID; i++)
2590 bnxt_del_vlan_filter(bp, i);
2592 rc = bnxt_add_mac_filter(bp, vnic, NULL, 0, 0);
2596 /* Default filter will allow packets that match the
2597 * dest mac. So, it has to be deleted, otherwise, we
2598 * will endup receiving vlan packets for which the
2599 * filter is not programmed, when hw-vlan-filter
2600 * configuration is ON
2602 bnxt_del_dflt_mac_filter(bp, vnic);
2603 /* This filter will allow only untagged packets */
2604 bnxt_add_vlan_filter(bp, 0);
2606 PMD_DRV_LOG(DEBUG, "VLAN Filtering: %d\n",
2607 !!(rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER));
2612 static int bnxt_free_one_vnic(struct bnxt *bp, uint16_t vnic_id)
2614 struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id];
2618 /* Destroy vnic filters and vnic */
2619 if (bp->eth_dev->data->dev_conf.rxmode.offloads &
2620 DEV_RX_OFFLOAD_VLAN_FILTER) {
2621 for (i = 0; i < RTE_ETHER_MAX_VLAN_ID; i++)
2622 bnxt_del_vlan_filter(bp, i);
2624 bnxt_del_dflt_mac_filter(bp, vnic);
2626 rc = bnxt_hwrm_vnic_ctx_free(bp, vnic);
2630 rc = bnxt_hwrm_vnic_free(bp, vnic);
2634 rte_free(vnic->fw_grp_ids);
2635 vnic->fw_grp_ids = NULL;
2637 vnic->rx_queue_cnt = 0;
2643 bnxt_config_vlan_hw_stripping(struct bnxt *bp, uint64_t rx_offloads)
2645 struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp);
2648 /* Destroy, recreate and reconfigure the default vnic */
2649 rc = bnxt_free_one_vnic(bp, 0);
2653 /* default vnic 0 */
2654 rc = bnxt_setup_one_vnic(bp, 0);
2658 if (bp->eth_dev->data->dev_conf.rxmode.offloads &
2659 DEV_RX_OFFLOAD_VLAN_FILTER) {
2660 rc = bnxt_add_vlan_filter(bp, 0);
2663 rc = bnxt_restore_vlan_filters(bp);
2667 rc = bnxt_add_mac_filter(bp, vnic, NULL, 0, 0);
2672 rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
2676 PMD_DRV_LOG(DEBUG, "VLAN Strip Offload: %d\n",
2677 !!(rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP));
2683 bnxt_vlan_offload_set_op(struct rte_eth_dev *dev, int mask)
2685 uint64_t rx_offloads = dev->data->dev_conf.rxmode.offloads;
2686 struct bnxt *bp = dev->data->dev_private;
2689 rc = is_bnxt_in_error(bp);
2693 /* Filter settings will get applied when port is started */
2694 if (!dev->data->dev_started)
2697 if (mask & ETH_VLAN_FILTER_MASK) {
2698 /* Enable or disable VLAN filtering */
2699 rc = bnxt_config_vlan_hw_filter(bp, rx_offloads);
2704 if (mask & ETH_VLAN_STRIP_MASK) {
2705 /* Enable or disable VLAN stripping */
2706 rc = bnxt_config_vlan_hw_stripping(bp, rx_offloads);
2711 if (mask & ETH_VLAN_EXTEND_MASK) {
2712 if (rx_offloads & DEV_RX_OFFLOAD_VLAN_EXTEND)
2713 PMD_DRV_LOG(DEBUG, "Extend VLAN supported\n");
2715 PMD_DRV_LOG(INFO, "Extend VLAN unsupported\n");
2722 bnxt_vlan_tpid_set_op(struct rte_eth_dev *dev, enum rte_vlan_type vlan_type,
2725 struct bnxt *bp = dev->data->dev_private;
2726 int qinq = dev->data->dev_conf.rxmode.offloads &
2727 DEV_RX_OFFLOAD_VLAN_EXTEND;
2729 if (vlan_type != ETH_VLAN_TYPE_INNER &&
2730 vlan_type != ETH_VLAN_TYPE_OUTER) {
2732 "Unsupported vlan type.");
2737 "QinQ not enabled. Needs to be ON as we can "
2738 "accelerate only outer vlan\n");
2742 if (vlan_type == ETH_VLAN_TYPE_OUTER) {
2744 case RTE_ETHER_TYPE_QINQ:
2746 TX_BD_LONG_CFA_META_VLAN_TPID_TPID88A8;
2748 case RTE_ETHER_TYPE_VLAN:
2750 TX_BD_LONG_CFA_META_VLAN_TPID_TPID8100;
2752 case RTE_ETHER_TYPE_QINQ1:
2754 TX_BD_LONG_CFA_META_VLAN_TPID_TPID9100;
2756 case RTE_ETHER_TYPE_QINQ2:
2758 TX_BD_LONG_CFA_META_VLAN_TPID_TPID9200;
2760 case RTE_ETHER_TYPE_QINQ3:
2762 TX_BD_LONG_CFA_META_VLAN_TPID_TPID9300;
2765 PMD_DRV_LOG(ERR, "Invalid TPID: %x\n", tpid);
2768 bp->outer_tpid_bd |= tpid;
2769 PMD_DRV_LOG(INFO, "outer_tpid_bd = %x\n", bp->outer_tpid_bd);
2770 } else if (vlan_type == ETH_VLAN_TYPE_INNER) {
2772 "Can accelerate only outer vlan in QinQ\n");
2780 bnxt_set_default_mac_addr_op(struct rte_eth_dev *dev,
2781 struct rte_ether_addr *addr)
2783 struct bnxt *bp = dev->data->dev_private;
2784 /* Default Filter is tied to VNIC 0 */
2785 struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp);
2788 rc = is_bnxt_in_error(bp);
2792 if (BNXT_VF(bp) && !BNXT_VF_IS_TRUSTED(bp))
2795 if (rte_is_zero_ether_addr(addr))
2798 /* Filter settings will get applied when port is started */
2799 if (!dev->data->dev_started)
2802 /* Check if the requested MAC is already added */
2803 if (memcmp(addr, bp->mac_addr, RTE_ETHER_ADDR_LEN) == 0)
2806 /* Destroy filter and re-create it */
2807 bnxt_del_dflt_mac_filter(bp, vnic);
2809 memcpy(bp->mac_addr, addr, RTE_ETHER_ADDR_LEN);
2810 if (dev->data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_VLAN_FILTER) {
2811 /* This filter will allow only untagged packets */
2812 rc = bnxt_add_vlan_filter(bp, 0);
2814 rc = bnxt_add_mac_filter(bp, vnic, addr, 0, 0);
2817 PMD_DRV_LOG(DEBUG, "Set MAC addr\n");
2822 bnxt_dev_set_mc_addr_list_op(struct rte_eth_dev *eth_dev,
2823 struct rte_ether_addr *mc_addr_set,
2824 uint32_t nb_mc_addr)
2826 struct bnxt *bp = eth_dev->data->dev_private;
2827 char *mc_addr_list = (char *)mc_addr_set;
2828 struct bnxt_vnic_info *vnic;
2829 uint32_t off = 0, i = 0;
2832 rc = is_bnxt_in_error(bp);
2836 vnic = BNXT_GET_DEFAULT_VNIC(bp);
2838 if (nb_mc_addr > BNXT_MAX_MC_ADDRS) {
2839 vnic->flags |= BNXT_VNIC_INFO_ALLMULTI;
2843 /* TODO Check for Duplicate mcast addresses */
2844 vnic->flags &= ~BNXT_VNIC_INFO_ALLMULTI;
2845 for (i = 0; i < nb_mc_addr; i++) {
2846 memcpy(vnic->mc_list + off, &mc_addr_list[i],
2847 RTE_ETHER_ADDR_LEN);
2848 off += RTE_ETHER_ADDR_LEN;
2851 vnic->mc_addr_cnt = i;
2852 if (vnic->mc_addr_cnt)
2853 vnic->flags |= BNXT_VNIC_INFO_MCAST;
2855 vnic->flags &= ~BNXT_VNIC_INFO_MCAST;
2858 return bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
2862 bnxt_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size)
2864 struct bnxt *bp = dev->data->dev_private;
2865 uint8_t fw_major = (bp->fw_ver >> 24) & 0xff;
2866 uint8_t fw_minor = (bp->fw_ver >> 16) & 0xff;
2867 uint8_t fw_updt = (bp->fw_ver >> 8) & 0xff;
2868 uint8_t fw_rsvd = bp->fw_ver & 0xff;
2871 ret = snprintf(fw_version, fw_size, "%d.%d.%d.%d",
2872 fw_major, fw_minor, fw_updt, fw_rsvd);
2876 ret += 1; /* add the size of '\0' */
2877 if (fw_size < (size_t)ret)
2884 bnxt_rxq_info_get_op(struct rte_eth_dev *dev, uint16_t queue_id,
2885 struct rte_eth_rxq_info *qinfo)
2887 struct bnxt *bp = dev->data->dev_private;
2888 struct bnxt_rx_queue *rxq;
2890 if (is_bnxt_in_error(bp))
2893 rxq = dev->data->rx_queues[queue_id];
2895 qinfo->mp = rxq->mb_pool;
2896 qinfo->scattered_rx = dev->data->scattered_rx;
2897 qinfo->nb_desc = rxq->nb_rx_desc;
2899 qinfo->conf.rx_free_thresh = rxq->rx_free_thresh;
2900 qinfo->conf.rx_drop_en = rxq->drop_en;
2901 qinfo->conf.rx_deferred_start = rxq->rx_deferred_start;
2902 qinfo->conf.offloads = dev->data->dev_conf.rxmode.offloads;
2906 bnxt_txq_info_get_op(struct rte_eth_dev *dev, uint16_t queue_id,
2907 struct rte_eth_txq_info *qinfo)
2909 struct bnxt *bp = dev->data->dev_private;
2910 struct bnxt_tx_queue *txq;
2912 if (is_bnxt_in_error(bp))
2915 txq = dev->data->tx_queues[queue_id];
2917 qinfo->nb_desc = txq->nb_tx_desc;
2919 qinfo->conf.tx_thresh.pthresh = txq->pthresh;
2920 qinfo->conf.tx_thresh.hthresh = txq->hthresh;
2921 qinfo->conf.tx_thresh.wthresh = txq->wthresh;
2923 qinfo->conf.tx_free_thresh = txq->tx_free_thresh;
2924 qinfo->conf.tx_rs_thresh = 0;
2925 qinfo->conf.tx_deferred_start = txq->tx_deferred_start;
2926 qinfo->conf.offloads = txq->offloads;
2929 static const struct {
2930 eth_rx_burst_t pkt_burst;
2932 } bnxt_rx_burst_info[] = {
2933 {bnxt_recv_pkts, "Scalar"},
2934 #if defined(RTE_ARCH_X86)
2935 {bnxt_recv_pkts_vec, "Vector SSE"},
2937 #if defined(RTE_ARCH_X86) && defined(CC_AVX2_SUPPORT)
2938 {bnxt_recv_pkts_vec_avx2, "Vector AVX2"},
2940 #if defined(RTE_ARCH_ARM64)
2941 {bnxt_recv_pkts_vec, "Vector Neon"},
2946 bnxt_rx_burst_mode_get(struct rte_eth_dev *dev, __rte_unused uint16_t queue_id,
2947 struct rte_eth_burst_mode *mode)
2949 eth_rx_burst_t pkt_burst = dev->rx_pkt_burst;
2952 for (i = 0; i < RTE_DIM(bnxt_rx_burst_info); i++) {
2953 if (pkt_burst == bnxt_rx_burst_info[i].pkt_burst) {
2954 snprintf(mode->info, sizeof(mode->info), "%s",
2955 bnxt_rx_burst_info[i].info);
2963 static const struct {
2964 eth_tx_burst_t pkt_burst;
2966 } bnxt_tx_burst_info[] = {
2967 {bnxt_xmit_pkts, "Scalar"},
2968 #if defined(RTE_ARCH_X86)
2969 {bnxt_xmit_pkts_vec, "Vector SSE"},
2971 #if defined(RTE_ARCH_X86) && defined(CC_AVX2_SUPPORT)
2972 {bnxt_xmit_pkts_vec_avx2, "Vector AVX2"},
2974 #if defined(RTE_ARCH_ARM64)
2975 {bnxt_xmit_pkts_vec, "Vector Neon"},
2980 bnxt_tx_burst_mode_get(struct rte_eth_dev *dev, __rte_unused uint16_t queue_id,
2981 struct rte_eth_burst_mode *mode)
2983 eth_tx_burst_t pkt_burst = dev->tx_pkt_burst;
2986 for (i = 0; i < RTE_DIM(bnxt_tx_burst_info); i++) {
2987 if (pkt_burst == bnxt_tx_burst_info[i].pkt_burst) {
2988 snprintf(mode->info, sizeof(mode->info), "%s",
2989 bnxt_tx_burst_info[i].info);
2997 int bnxt_mtu_set_op(struct rte_eth_dev *eth_dev, uint16_t new_mtu)
2999 struct bnxt *bp = eth_dev->data->dev_private;
3000 uint32_t new_pkt_size;
3004 rc = is_bnxt_in_error(bp);
3008 /* Exit if receive queues are not configured yet */
3009 if (!eth_dev->data->nb_rx_queues)
3012 new_pkt_size = new_mtu + RTE_ETHER_HDR_LEN + RTE_ETHER_CRC_LEN +
3013 VLAN_TAG_SIZE * BNXT_NUM_VLANS;
3016 * Disallow any MTU change that would require scattered receive support
3017 * if it is not already enabled.
3019 if (eth_dev->data->dev_started &&
3020 !eth_dev->data->scattered_rx &&
3022 eth_dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM)) {
3024 "MTU change would require scattered rx support. ");
3025 PMD_DRV_LOG(ERR, "Stop port before changing MTU.\n");
3029 if (new_mtu > RTE_ETHER_MTU) {
3030 bp->flags |= BNXT_FLAG_JUMBO;
3031 bp->eth_dev->data->dev_conf.rxmode.offloads |=
3032 DEV_RX_OFFLOAD_JUMBO_FRAME;
3034 bp->eth_dev->data->dev_conf.rxmode.offloads &=
3035 ~DEV_RX_OFFLOAD_JUMBO_FRAME;
3036 bp->flags &= ~BNXT_FLAG_JUMBO;
3039 /* Is there a change in mtu setting? */
3040 if (eth_dev->data->dev_conf.rxmode.max_rx_pkt_len == new_pkt_size)
3043 for (i = 0; i < bp->nr_vnics; i++) {
3044 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
3047 vnic->mru = BNXT_VNIC_MRU(new_mtu);
3048 rc = bnxt_hwrm_vnic_cfg(bp, vnic);
3052 size = rte_pktmbuf_data_room_size(bp->rx_queues[0]->mb_pool);
3053 size -= RTE_PKTMBUF_HEADROOM;
3055 if (size < new_mtu) {
3056 rc = bnxt_hwrm_vnic_plcmode_cfg(bp, vnic);
3063 eth_dev->data->dev_conf.rxmode.max_rx_pkt_len = new_pkt_size;
3065 PMD_DRV_LOG(INFO, "New MTU is %d\n", new_mtu);
3071 bnxt_vlan_pvid_set_op(struct rte_eth_dev *dev, uint16_t pvid, int on)
3073 struct bnxt *bp = dev->data->dev_private;
3074 uint16_t vlan = bp->vlan;
3077 rc = is_bnxt_in_error(bp);
3081 if (!BNXT_SINGLE_PF(bp)) {
3082 PMD_DRV_LOG(ERR, "PVID cannot be modified on VF or on shared PF\n");
3085 bp->vlan = on ? pvid : 0;
3087 rc = bnxt_hwrm_set_default_vlan(bp, 0, 0);
3094 bnxt_dev_led_on_op(struct rte_eth_dev *dev)
3096 struct bnxt *bp = dev->data->dev_private;
3099 rc = is_bnxt_in_error(bp);
3103 return bnxt_hwrm_port_led_cfg(bp, true);
3107 bnxt_dev_led_off_op(struct rte_eth_dev *dev)
3109 struct bnxt *bp = dev->data->dev_private;
3112 rc = is_bnxt_in_error(bp);
3116 return bnxt_hwrm_port_led_cfg(bp, false);
3120 bnxt_rx_queue_count_op(struct rte_eth_dev *dev, uint16_t rx_queue_id)
3122 struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
3123 struct bnxt_cp_ring_info *cpr;
3124 uint32_t desc = 0, raw_cons, cp_ring_size;
3125 struct bnxt_rx_queue *rxq;
3126 struct rx_pkt_cmpl *rxcmp;
3129 rc = is_bnxt_in_error(bp);
3133 rxq = dev->data->rx_queues[rx_queue_id];
3135 raw_cons = cpr->cp_raw_cons;
3136 cp_ring_size = cpr->cp_ring_struct->ring_size;
3139 uint32_t agg_cnt, cons, cmpl_type;
3141 cons = RING_CMP(cpr->cp_ring_struct, raw_cons);
3142 rxcmp = (struct rx_pkt_cmpl *)&cpr->cp_desc_ring[cons];
3144 if (!bnxt_cpr_cmp_valid(rxcmp, raw_cons, cp_ring_size))
3147 cmpl_type = CMP_TYPE(rxcmp);
3149 switch (cmpl_type) {
3150 case CMPL_BASE_TYPE_RX_L2:
3151 case CMPL_BASE_TYPE_RX_L2_V2:
3152 agg_cnt = BNXT_RX_L2_AGG_BUFS(rxcmp);
3153 raw_cons = raw_cons + CMP_LEN(cmpl_type) + agg_cnt;
3157 case CMPL_BASE_TYPE_RX_TPA_END:
3158 if (BNXT_CHIP_P5(rxq->bp)) {
3159 struct rx_tpa_v2_end_cmpl_hi *p5_tpa_end;
3161 p5_tpa_end = (void *)rxcmp;
3162 agg_cnt = BNXT_TPA_END_AGG_BUFS_TH(p5_tpa_end);
3164 struct rx_tpa_end_cmpl *tpa_end;
3166 tpa_end = (void *)rxcmp;
3167 agg_cnt = BNXT_TPA_END_AGG_BUFS(tpa_end);
3170 raw_cons = raw_cons + CMP_LEN(cmpl_type) + agg_cnt;
3175 raw_cons += CMP_LEN(cmpl_type);
3183 bnxt_rx_descriptor_status_op(void *rx_queue, uint16_t offset)
3185 struct bnxt_rx_queue *rxq = rx_queue;
3186 struct bnxt_cp_ring_info *cpr;
3187 struct bnxt_rx_ring_info *rxr;
3188 uint32_t desc, raw_cons, cp_ring_size;
3189 struct bnxt *bp = rxq->bp;
3190 struct rx_pkt_cmpl *rxcmp;
3193 rc = is_bnxt_in_error(bp);
3197 if (offset >= rxq->nb_rx_desc)
3202 cp_ring_size = cpr->cp_ring_struct->ring_size;
3205 * For the vector receive case, the completion at the requested
3206 * offset can be indexed directly.
3208 #if defined(RTE_ARCH_X86) || defined(RTE_ARCH_ARM64)
3209 if (bp->flags & BNXT_FLAG_RX_VECTOR_PKT_MODE) {
3210 struct rx_pkt_cmpl *rxcmp;
3213 /* Check status of completion descriptor. */
3214 raw_cons = cpr->cp_raw_cons +
3215 offset * CMP_LEN(CMPL_BASE_TYPE_RX_L2);
3216 cons = RING_CMP(cpr->cp_ring_struct, raw_cons);
3217 rxcmp = (struct rx_pkt_cmpl *)&cpr->cp_desc_ring[cons];
3219 if (bnxt_cpr_cmp_valid(rxcmp, raw_cons, cp_ring_size))
3220 return RTE_ETH_RX_DESC_DONE;
3222 /* Check whether rx desc has an mbuf attached. */
3223 cons = RING_CMP(rxr->rx_ring_struct, raw_cons / 2);
3224 if (cons >= rxq->rxrearm_start &&
3225 cons < rxq->rxrearm_start + rxq->rxrearm_nb) {
3226 return RTE_ETH_RX_DESC_UNAVAIL;
3229 return RTE_ETH_RX_DESC_AVAIL;
3234 * For the non-vector receive case, scan the completion ring to
3235 * locate the completion descriptor for the requested offset.
3237 raw_cons = cpr->cp_raw_cons;
3240 uint32_t agg_cnt, cons, cmpl_type;
3242 cons = RING_CMP(cpr->cp_ring_struct, raw_cons);
3243 rxcmp = (struct rx_pkt_cmpl *)&cpr->cp_desc_ring[cons];
3245 if (!bnxt_cpr_cmp_valid(rxcmp, raw_cons, cp_ring_size))
3248 cmpl_type = CMP_TYPE(rxcmp);
3250 switch (cmpl_type) {
3251 case CMPL_BASE_TYPE_RX_L2:
3252 case CMPL_BASE_TYPE_RX_L2_V2:
3253 if (desc == offset) {
3254 cons = rxcmp->opaque;
3255 if (rxr->rx_buf_ring[cons])
3256 return RTE_ETH_RX_DESC_DONE;
3258 return RTE_ETH_RX_DESC_UNAVAIL;
3260 agg_cnt = BNXT_RX_L2_AGG_BUFS(rxcmp);
3261 raw_cons = raw_cons + CMP_LEN(cmpl_type) + agg_cnt;
3265 case CMPL_BASE_TYPE_RX_TPA_END:
3267 return RTE_ETH_RX_DESC_DONE;
3269 if (BNXT_CHIP_P5(rxq->bp)) {
3270 struct rx_tpa_v2_end_cmpl_hi *p5_tpa_end;
3272 p5_tpa_end = (void *)rxcmp;
3273 agg_cnt = BNXT_TPA_END_AGG_BUFS_TH(p5_tpa_end);
3275 struct rx_tpa_end_cmpl *tpa_end;
3277 tpa_end = (void *)rxcmp;
3278 agg_cnt = BNXT_TPA_END_AGG_BUFS(tpa_end);
3281 raw_cons = raw_cons + CMP_LEN(cmpl_type) + agg_cnt;
3286 raw_cons += CMP_LEN(cmpl_type);
3290 return RTE_ETH_RX_DESC_AVAIL;
3294 bnxt_tx_descriptor_status_op(void *tx_queue, uint16_t offset)
3296 struct bnxt_tx_queue *txq = (struct bnxt_tx_queue *)tx_queue;
3297 struct bnxt_cp_ring_info *cpr = txq->cp_ring;
3298 uint32_t ring_mask, raw_cons, nb_tx_pkts = 0;
3299 struct cmpl_base *cp_desc_ring;
3302 rc = is_bnxt_in_error(txq->bp);
3306 if (offset >= txq->nb_tx_desc)
3309 /* Return "desc done" if descriptor is available for use. */
3310 if (bnxt_tx_bds_in_hw(txq) <= offset)
3311 return RTE_ETH_TX_DESC_DONE;
3313 raw_cons = cpr->cp_raw_cons;
3314 cp_desc_ring = cpr->cp_desc_ring;
3315 ring_mask = cpr->cp_ring_struct->ring_mask;
3317 /* Check to see if hw has posted a completion for the descriptor. */
3319 struct tx_cmpl *txcmp;
3322 cons = RING_CMPL(ring_mask, raw_cons);
3323 txcmp = (struct tx_cmpl *)&cp_desc_ring[cons];
3325 if (!bnxt_cpr_cmp_valid(txcmp, raw_cons, ring_mask + 1))
3328 if (CMP_TYPE(txcmp) == TX_CMPL_TYPE_TX_L2)
3329 nb_tx_pkts += rte_le_to_cpu_32(txcmp->opaque);
3331 if (nb_tx_pkts > offset)
3332 return RTE_ETH_TX_DESC_DONE;
3334 raw_cons = NEXT_RAW_CMP(raw_cons);
3337 /* Descriptor is pending transmit, not yet completed by hardware. */
3338 return RTE_ETH_TX_DESC_FULL;
3342 bnxt_flow_ops_get_op(struct rte_eth_dev *dev,
3343 const struct rte_flow_ops **ops)
3345 struct bnxt *bp = dev->data->dev_private;
3351 if (BNXT_ETH_DEV_IS_REPRESENTOR(dev)) {
3352 struct bnxt_representor *vfr = dev->data->dev_private;
3353 bp = vfr->parent_dev->data->dev_private;
3354 /* parent is deleted while children are still valid */
3356 PMD_DRV_LOG(DEBUG, "BNXT Port:%d VFR Error\n",
3357 dev->data->port_id);
3362 ret = is_bnxt_in_error(bp);
3366 /* PMD supports thread-safe flow operations. rte_flow API
3367 * functions can avoid mutex for multi-thread safety.
3369 dev->data->dev_flags |= RTE_ETH_DEV_FLOW_OPS_THREAD_SAFE;
3371 if (BNXT_TRUFLOW_EN(bp))
3372 *ops = &bnxt_ulp_rte_flow_ops;
3374 *ops = &bnxt_flow_ops;
3379 static const uint32_t *
3380 bnxt_dev_supported_ptypes_get_op(struct rte_eth_dev *dev)
3382 static const uint32_t ptypes[] = {
3383 RTE_PTYPE_L2_ETHER_VLAN,
3384 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN,
3385 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN,
3389 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN,
3390 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN,
3391 RTE_PTYPE_INNER_L4_ICMP,
3392 RTE_PTYPE_INNER_L4_TCP,
3393 RTE_PTYPE_INNER_L4_UDP,
3397 if (!dev->rx_pkt_burst)
3403 static int bnxt_map_regs(struct bnxt *bp, uint32_t *reg_arr, int count,
3406 uint32_t reg_base = *reg_arr & 0xfffff000;
3410 for (i = 0; i < count; i++) {
3411 if ((reg_arr[i] & 0xfffff000) != reg_base)
3414 win_off = BNXT_GRCPF_REG_WINDOW_BASE_OUT + (reg_win - 1) * 4;
3415 rte_write32(reg_base, (uint8_t *)bp->bar0 + win_off);
3419 static int bnxt_map_ptp_regs(struct bnxt *bp)
3421 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3425 reg_arr = ptp->rx_regs;
3426 rc = bnxt_map_regs(bp, reg_arr, BNXT_PTP_RX_REGS, 5);
3430 reg_arr = ptp->tx_regs;
3431 rc = bnxt_map_regs(bp, reg_arr, BNXT_PTP_TX_REGS, 6);
3435 for (i = 0; i < BNXT_PTP_RX_REGS; i++)
3436 ptp->rx_mapped_regs[i] = 0x5000 + (ptp->rx_regs[i] & 0xfff);
3438 for (i = 0; i < BNXT_PTP_TX_REGS; i++)
3439 ptp->tx_mapped_regs[i] = 0x6000 + (ptp->tx_regs[i] & 0xfff);
3444 static void bnxt_unmap_ptp_regs(struct bnxt *bp)
3446 rte_write32(0, (uint8_t *)bp->bar0 +
3447 BNXT_GRCPF_REG_WINDOW_BASE_OUT + 16);
3448 rte_write32(0, (uint8_t *)bp->bar0 +
3449 BNXT_GRCPF_REG_WINDOW_BASE_OUT + 20);
3452 static uint64_t bnxt_cc_read(struct bnxt *bp)
3456 ns = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3457 BNXT_GRCPF_REG_SYNC_TIME));
3458 ns |= (uint64_t)(rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3459 BNXT_GRCPF_REG_SYNC_TIME + 4))) << 32;
3463 static int bnxt_get_tx_ts(struct bnxt *bp, uint64_t *ts)
3465 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3468 fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3469 ptp->tx_mapped_regs[BNXT_PTP_TX_FIFO]));
3470 if (fifo & BNXT_PTP_TX_FIFO_EMPTY)
3473 fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3474 ptp->tx_mapped_regs[BNXT_PTP_TX_FIFO]));
3475 *ts = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3476 ptp->tx_mapped_regs[BNXT_PTP_TX_TS_L]));
3477 *ts |= (uint64_t)rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3478 ptp->tx_mapped_regs[BNXT_PTP_TX_TS_H])) << 32;
3479 rte_read32((uint8_t *)bp->bar0 + ptp->tx_mapped_regs[BNXT_PTP_TX_SEQ]);
3484 static int bnxt_clr_rx_ts(struct bnxt *bp, uint64_t *last_ts)
3486 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3487 struct bnxt_pf_info *pf = bp->pf;
3492 if (!ptp || (bp->flags & BNXT_FLAG_CHIP_P5))
3495 port_id = pf->port_id;
3496 fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3497 ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO]));
3498 while ((fifo & BNXT_PTP_RX_FIFO_PENDING) && (i < BNXT_PTP_RX_PND_CNT)) {
3499 rte_write32(1 << port_id, (uint8_t *)bp->bar0 +
3500 ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO_ADV]);
3501 fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3502 ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO]));
3503 *last_ts = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3504 ptp->rx_mapped_regs[BNXT_PTP_RX_TS_L]));
3505 *last_ts |= (uint64_t)rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3506 ptp->rx_mapped_regs[BNXT_PTP_RX_TS_H])) << 32;
3510 if (i >= BNXT_PTP_RX_PND_CNT)
3516 static int bnxt_get_rx_ts(struct bnxt *bp, uint64_t *ts)
3518 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3519 struct bnxt_pf_info *pf = bp->pf;
3523 fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3524 ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO]));
3525 if (!(fifo & BNXT_PTP_RX_FIFO_PENDING))
3528 port_id = pf->port_id;
3529 rte_write32(1 << port_id, (uint8_t *)bp->bar0 +
3530 ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO_ADV]);
3532 fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3533 ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO]));
3534 if (fifo & BNXT_PTP_RX_FIFO_PENDING)
3535 return bnxt_clr_rx_ts(bp, ts);
3537 *ts = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3538 ptp->rx_mapped_regs[BNXT_PTP_RX_TS_L]));
3539 *ts |= (uint64_t)rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3540 ptp->rx_mapped_regs[BNXT_PTP_RX_TS_H])) << 32;
3546 bnxt_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
3549 struct bnxt *bp = dev->data->dev_private;
3550 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3555 ns = rte_timespec_to_ns(ts);
3556 /* Set the timecounters to a new value. */
3558 ptp->tx_tstamp_tc.nsec = ns;
3559 ptp->rx_tstamp_tc.nsec = ns;
3565 bnxt_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
3567 struct bnxt *bp = dev->data->dev_private;
3568 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3569 uint64_t ns, systime_cycles = 0;
3575 if (BNXT_CHIP_P5(bp))
3576 rc = bnxt_hwrm_port_ts_query(bp, BNXT_PTP_FLAGS_CURRENT_TIME,
3579 systime_cycles = bnxt_cc_read(bp);
3581 ns = rte_timecounter_update(&ptp->tc, systime_cycles);
3582 *ts = rte_ns_to_timespec(ns);
3587 bnxt_timesync_enable(struct rte_eth_dev *dev)
3589 struct bnxt *bp = dev->data->dev_private;
3590 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3598 ptp->tx_tstamp_en = 1;
3599 ptp->rxctl = BNXT_PTP_MSG_EVENTS;
3601 rc = bnxt_hwrm_ptp_cfg(bp);
3605 memset(&ptp->tc, 0, sizeof(struct rte_timecounter));
3606 memset(&ptp->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
3607 memset(&ptp->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
3609 ptp->tc.cc_mask = BNXT_CYCLECOUNTER_MASK;
3610 ptp->tc.cc_shift = shift;
3611 ptp->tc.nsec_mask = (1ULL << shift) - 1;
3613 ptp->rx_tstamp_tc.cc_mask = BNXT_CYCLECOUNTER_MASK;
3614 ptp->rx_tstamp_tc.cc_shift = shift;
3615 ptp->rx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
3617 ptp->tx_tstamp_tc.cc_mask = BNXT_CYCLECOUNTER_MASK;
3618 ptp->tx_tstamp_tc.cc_shift = shift;
3619 ptp->tx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
3621 if (!BNXT_CHIP_P5(bp))
3622 bnxt_map_ptp_regs(bp);
3624 rc = bnxt_ptp_start(bp);
3630 bnxt_timesync_disable(struct rte_eth_dev *dev)
3632 struct bnxt *bp = dev->data->dev_private;
3633 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3639 ptp->tx_tstamp_en = 0;
3642 bnxt_hwrm_ptp_cfg(bp);
3644 if (!BNXT_CHIP_P5(bp))
3645 bnxt_unmap_ptp_regs(bp);
3653 bnxt_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
3654 struct timespec *timestamp,
3655 uint32_t flags __rte_unused)
3657 struct bnxt *bp = dev->data->dev_private;
3658 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3659 uint64_t rx_tstamp_cycles = 0;
3665 if (BNXT_CHIP_P5(bp))
3666 rx_tstamp_cycles = ptp->rx_timestamp;
3668 bnxt_get_rx_ts(bp, &rx_tstamp_cycles);
3670 ns = rte_timecounter_update(&ptp->rx_tstamp_tc, rx_tstamp_cycles);
3671 *timestamp = rte_ns_to_timespec(ns);
3676 bnxt_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
3677 struct timespec *timestamp)
3679 struct bnxt *bp = dev->data->dev_private;
3680 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3681 uint64_t tx_tstamp_cycles = 0;
3688 if (BNXT_CHIP_P5(bp))
3689 rc = bnxt_hwrm_port_ts_query(bp, BNXT_PTP_FLAGS_PATH_TX,
3692 rc = bnxt_get_tx_ts(bp, &tx_tstamp_cycles);
3694 ns = rte_timecounter_update(&ptp->tx_tstamp_tc, tx_tstamp_cycles);
3695 *timestamp = rte_ns_to_timespec(ns);
3701 bnxt_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
3703 struct bnxt *bp = dev->data->dev_private;
3704 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3709 ptp->tc.nsec += delta;
3710 ptp->tx_tstamp_tc.nsec += delta;
3711 ptp->rx_tstamp_tc.nsec += delta;
3717 bnxt_get_eeprom_length_op(struct rte_eth_dev *dev)
3719 struct bnxt *bp = dev->data->dev_private;
3721 uint32_t dir_entries;
3722 uint32_t entry_length;
3724 rc = is_bnxt_in_error(bp);
3728 PMD_DRV_LOG(INFO, PCI_PRI_FMT "\n",
3729 bp->pdev->addr.domain, bp->pdev->addr.bus,
3730 bp->pdev->addr.devid, bp->pdev->addr.function);
3732 rc = bnxt_hwrm_nvm_get_dir_info(bp, &dir_entries, &entry_length);
3736 return dir_entries * entry_length;
3740 bnxt_get_eeprom_op(struct rte_eth_dev *dev,
3741 struct rte_dev_eeprom_info *in_eeprom)
3743 struct bnxt *bp = dev->data->dev_private;
3748 rc = is_bnxt_in_error(bp);
3752 PMD_DRV_LOG(INFO, PCI_PRI_FMT " in_eeprom->offset = %d len = %d\n",
3753 bp->pdev->addr.domain, bp->pdev->addr.bus,
3754 bp->pdev->addr.devid, bp->pdev->addr.function,
3755 in_eeprom->offset, in_eeprom->length);
3757 if (in_eeprom->offset == 0) /* special offset value to get directory */
3758 return bnxt_get_nvram_directory(bp, in_eeprom->length,
3761 index = in_eeprom->offset >> 24;
3762 offset = in_eeprom->offset & 0xffffff;
3765 return bnxt_hwrm_get_nvram_item(bp, index - 1, offset,
3766 in_eeprom->length, in_eeprom->data);
3771 static bool bnxt_dir_type_is_ape_bin_format(uint16_t dir_type)
3774 case BNX_DIR_TYPE_CHIMP_PATCH:
3775 case BNX_DIR_TYPE_BOOTCODE:
3776 case BNX_DIR_TYPE_BOOTCODE_2:
3777 case BNX_DIR_TYPE_APE_FW:
3778 case BNX_DIR_TYPE_APE_PATCH:
3779 case BNX_DIR_TYPE_KONG_FW:
3780 case BNX_DIR_TYPE_KONG_PATCH:
3781 case BNX_DIR_TYPE_BONO_FW:
3782 case BNX_DIR_TYPE_BONO_PATCH:
3790 static bool bnxt_dir_type_is_other_exec_format(uint16_t dir_type)
3793 case BNX_DIR_TYPE_AVS:
3794 case BNX_DIR_TYPE_EXP_ROM_MBA:
3795 case BNX_DIR_TYPE_PCIE:
3796 case BNX_DIR_TYPE_TSCF_UCODE:
3797 case BNX_DIR_TYPE_EXT_PHY:
3798 case BNX_DIR_TYPE_CCM:
3799 case BNX_DIR_TYPE_ISCSI_BOOT:
3800 case BNX_DIR_TYPE_ISCSI_BOOT_IPV6:
3801 case BNX_DIR_TYPE_ISCSI_BOOT_IPV4N6:
3809 static bool bnxt_dir_type_is_executable(uint16_t dir_type)
3811 return bnxt_dir_type_is_ape_bin_format(dir_type) ||
3812 bnxt_dir_type_is_other_exec_format(dir_type);
3816 bnxt_set_eeprom_op(struct rte_eth_dev *dev,
3817 struct rte_dev_eeprom_info *in_eeprom)
3819 struct bnxt *bp = dev->data->dev_private;
3820 uint8_t index, dir_op;
3821 uint16_t type, ext, ordinal, attr;
3824 rc = is_bnxt_in_error(bp);
3828 PMD_DRV_LOG(INFO, PCI_PRI_FMT " in_eeprom->offset = %d len = %d\n",
3829 bp->pdev->addr.domain, bp->pdev->addr.bus,
3830 bp->pdev->addr.devid, bp->pdev->addr.function,
3831 in_eeprom->offset, in_eeprom->length);
3834 PMD_DRV_LOG(ERR, "NVM write not supported from a VF\n");
3838 type = in_eeprom->magic >> 16;
3840 if (type == 0xffff) { /* special value for directory operations */
3841 index = in_eeprom->magic & 0xff;
3842 dir_op = in_eeprom->magic >> 8;
3846 case 0x0e: /* erase */
3847 if (in_eeprom->offset != ~in_eeprom->magic)
3849 return bnxt_hwrm_erase_nvram_directory(bp, index - 1);
3855 /* Create or re-write an NVM item: */
3856 if (bnxt_dir_type_is_executable(type) == true)
3858 ext = in_eeprom->magic & 0xffff;
3859 ordinal = in_eeprom->offset >> 16;
3860 attr = in_eeprom->offset & 0xffff;
3862 return bnxt_hwrm_flash_nvram(bp, type, ordinal, ext, attr,
3863 in_eeprom->data, in_eeprom->length);
3866 static int bnxt_get_module_info(struct rte_eth_dev *dev,
3867 struct rte_eth_dev_module_info *modinfo)
3869 uint8_t module_info[SFF_DIAG_SUPPORT_OFFSET + 1];
3870 struct bnxt *bp = dev->data->dev_private;
3873 /* No point in going further if phy status indicates
3874 * module is not inserted or if it is powered down or
3875 * if it is of type 10GBase-T
3877 if (bp->link_info->module_status >
3878 HWRM_PORT_PHY_QCFG_OUTPUT_MODULE_STATUS_WARNINGMSG) {
3879 PMD_DRV_LOG(NOTICE, "Port %u : Module is not inserted or is powered down\n",
3880 dev->data->port_id);
3884 /* This feature is not supported in older firmware versions */
3885 if (bp->hwrm_spec_code < 0x10202) {
3886 PMD_DRV_LOG(NOTICE, "Port %u : Feature is not supported in older firmware\n",
3887 dev->data->port_id);
3891 rc = bnxt_hwrm_read_sfp_module_eeprom_info(bp, I2C_DEV_ADDR_A0, 0, 0,
3892 SFF_DIAG_SUPPORT_OFFSET + 1,
3898 switch (module_info[0]) {
3899 case SFF_MODULE_ID_SFP:
3900 modinfo->type = RTE_ETH_MODULE_SFF_8472;
3901 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8472_LEN;
3902 if (module_info[SFF_DIAG_SUPPORT_OFFSET] == 0)
3903 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8436_LEN;
3905 case SFF_MODULE_ID_QSFP:
3906 case SFF_MODULE_ID_QSFP_PLUS:
3907 modinfo->type = RTE_ETH_MODULE_SFF_8436;
3908 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8436_LEN;
3910 case SFF_MODULE_ID_QSFP28:
3911 modinfo->type = RTE_ETH_MODULE_SFF_8636;
3912 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8636_MAX_LEN;
3913 if (module_info[SFF8636_FLATMEM_OFFSET] & SFF8636_FLATMEM_MASK)
3914 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8636_LEN;
3917 PMD_DRV_LOG(NOTICE, "Port %u : Unsupported module\n", dev->data->port_id);
3921 PMD_DRV_LOG(INFO, "Port %u : modinfo->type = %d modinfo->eeprom_len = %d\n",
3922 dev->data->port_id, modinfo->type, modinfo->eeprom_len);
3927 static int bnxt_get_module_eeprom(struct rte_eth_dev *dev,
3928 struct rte_dev_eeprom_info *info)
3930 uint8_t pg_addr[5] = { I2C_DEV_ADDR_A0, I2C_DEV_ADDR_A0 };
3931 uint32_t offset = info->offset, length = info->length;
3932 uint8_t module_info[SFF_DIAG_SUPPORT_OFFSET + 1];
3933 struct bnxt *bp = dev->data->dev_private;
3934 uint8_t *data = info->data;
3935 uint8_t page = offset >> 7;
3936 uint8_t max_pages = 2;
3940 rc = bnxt_hwrm_read_sfp_module_eeprom_info(bp, I2C_DEV_ADDR_A0, 0, 0,
3941 SFF_DIAG_SUPPORT_OFFSET + 1,
3946 switch (module_info[0]) {
3947 case SFF_MODULE_ID_SFP:
3948 module_info[SFF_DIAG_SUPPORT_OFFSET] = 0;
3949 if (module_info[SFF_DIAG_SUPPORT_OFFSET]) {
3950 pg_addr[2] = I2C_DEV_ADDR_A2;
3951 pg_addr[3] = I2C_DEV_ADDR_A2;
3955 case SFF_MODULE_ID_QSFP28:
3956 rc = bnxt_hwrm_read_sfp_module_eeprom_info(bp, I2C_DEV_ADDR_A0, 0,
3957 SFF8636_OPT_PAGES_OFFSET,
3962 if (opt_pages & SFF8636_PAGE1_MASK) {
3963 pg_addr[2] = I2C_DEV_ADDR_A0;
3966 if (opt_pages & SFF8636_PAGE2_MASK) {
3967 pg_addr[3] = I2C_DEV_ADDR_A0;
3970 if (~module_info[SFF8636_FLATMEM_OFFSET] & SFF8636_FLATMEM_MASK) {
3971 pg_addr[4] = I2C_DEV_ADDR_A0;
3979 memset(data, 0, length);
3982 while (length && page < max_pages) {
3983 uint8_t raw_page = page ? page - 1 : 0;
3986 if (pg_addr[page] == I2C_DEV_ADDR_A2)
3990 chunk = RTE_MIN(length, 256 - offset);
3992 if (pg_addr[page]) {
3993 rc = bnxt_hwrm_read_sfp_module_eeprom_info(bp, pg_addr[page],
4003 page += 1 + (chunk > 128);
4006 return length ? -EINVAL : 0;
4013 static const struct eth_dev_ops bnxt_dev_ops = {
4014 .dev_infos_get = bnxt_dev_info_get_op,
4015 .dev_close = bnxt_dev_close_op,
4016 .dev_configure = bnxt_dev_configure_op,
4017 .dev_start = bnxt_dev_start_op,
4018 .dev_stop = bnxt_dev_stop_op,
4019 .dev_set_link_up = bnxt_dev_set_link_up_op,
4020 .dev_set_link_down = bnxt_dev_set_link_down_op,
4021 .stats_get = bnxt_stats_get_op,
4022 .stats_reset = bnxt_stats_reset_op,
4023 .rx_queue_setup = bnxt_rx_queue_setup_op,
4024 .rx_queue_release = bnxt_rx_queue_release_op,
4025 .tx_queue_setup = bnxt_tx_queue_setup_op,
4026 .tx_queue_release = bnxt_tx_queue_release_op,
4027 .rx_queue_intr_enable = bnxt_rx_queue_intr_enable_op,
4028 .rx_queue_intr_disable = bnxt_rx_queue_intr_disable_op,
4029 .reta_update = bnxt_reta_update_op,
4030 .reta_query = bnxt_reta_query_op,
4031 .rss_hash_update = bnxt_rss_hash_update_op,
4032 .rss_hash_conf_get = bnxt_rss_hash_conf_get_op,
4033 .link_update = bnxt_link_update_op,
4034 .promiscuous_enable = bnxt_promiscuous_enable_op,
4035 .promiscuous_disable = bnxt_promiscuous_disable_op,
4036 .allmulticast_enable = bnxt_allmulticast_enable_op,
4037 .allmulticast_disable = bnxt_allmulticast_disable_op,
4038 .mac_addr_add = bnxt_mac_addr_add_op,
4039 .mac_addr_remove = bnxt_mac_addr_remove_op,
4040 .flow_ctrl_get = bnxt_flow_ctrl_get_op,
4041 .flow_ctrl_set = bnxt_flow_ctrl_set_op,
4042 .udp_tunnel_port_add = bnxt_udp_tunnel_port_add_op,
4043 .udp_tunnel_port_del = bnxt_udp_tunnel_port_del_op,
4044 .vlan_filter_set = bnxt_vlan_filter_set_op,
4045 .vlan_offload_set = bnxt_vlan_offload_set_op,
4046 .vlan_tpid_set = bnxt_vlan_tpid_set_op,
4047 .vlan_pvid_set = bnxt_vlan_pvid_set_op,
4048 .mtu_set = bnxt_mtu_set_op,
4049 .mac_addr_set = bnxt_set_default_mac_addr_op,
4050 .xstats_get = bnxt_dev_xstats_get_op,
4051 .xstats_get_names = bnxt_dev_xstats_get_names_op,
4052 .xstats_reset = bnxt_dev_xstats_reset_op,
4053 .fw_version_get = bnxt_fw_version_get,
4054 .set_mc_addr_list = bnxt_dev_set_mc_addr_list_op,
4055 .rxq_info_get = bnxt_rxq_info_get_op,
4056 .txq_info_get = bnxt_txq_info_get_op,
4057 .rx_burst_mode_get = bnxt_rx_burst_mode_get,
4058 .tx_burst_mode_get = bnxt_tx_burst_mode_get,
4059 .dev_led_on = bnxt_dev_led_on_op,
4060 .dev_led_off = bnxt_dev_led_off_op,
4061 .rx_queue_start = bnxt_rx_queue_start,
4062 .rx_queue_stop = bnxt_rx_queue_stop,
4063 .tx_queue_start = bnxt_tx_queue_start,
4064 .tx_queue_stop = bnxt_tx_queue_stop,
4065 .flow_ops_get = bnxt_flow_ops_get_op,
4066 .dev_supported_ptypes_get = bnxt_dev_supported_ptypes_get_op,
4067 .get_eeprom_length = bnxt_get_eeprom_length_op,
4068 .get_eeprom = bnxt_get_eeprom_op,
4069 .set_eeprom = bnxt_set_eeprom_op,
4070 .get_module_info = bnxt_get_module_info,
4071 .get_module_eeprom = bnxt_get_module_eeprom,
4072 .timesync_enable = bnxt_timesync_enable,
4073 .timesync_disable = bnxt_timesync_disable,
4074 .timesync_read_time = bnxt_timesync_read_time,
4075 .timesync_write_time = bnxt_timesync_write_time,
4076 .timesync_adjust_time = bnxt_timesync_adjust_time,
4077 .timesync_read_rx_timestamp = bnxt_timesync_read_rx_timestamp,
4078 .timesync_read_tx_timestamp = bnxt_timesync_read_tx_timestamp,
4081 static uint32_t bnxt_map_reset_regs(struct bnxt *bp, uint32_t reg)
4085 /* Only pre-map the reset GRC registers using window 3 */
4086 rte_write32(reg & 0xfffff000, (uint8_t *)bp->bar0 +
4087 BNXT_GRCPF_REG_WINDOW_BASE_OUT + 8);
4089 offset = BNXT_GRCP_WINDOW_3_BASE + (reg & 0xffc);
4094 int bnxt_map_fw_health_status_regs(struct bnxt *bp)
4096 struct bnxt_error_recovery_info *info = bp->recovery_info;
4097 uint32_t reg_base = 0xffffffff;
4100 /* Only pre-map the monitoring GRC registers using window 2 */
4101 for (i = 0; i < BNXT_FW_STATUS_REG_CNT; i++) {
4102 uint32_t reg = info->status_regs[i];
4104 if (BNXT_FW_STATUS_REG_TYPE(reg) != BNXT_FW_STATUS_REG_TYPE_GRC)
4107 if (reg_base == 0xffffffff)
4108 reg_base = reg & 0xfffff000;
4109 if ((reg & 0xfffff000) != reg_base)
4112 /* Use mask 0xffc as the Lower 2 bits indicates
4113 * address space location
4115 info->mapped_status_regs[i] = BNXT_GRCP_WINDOW_2_BASE +
4119 if (reg_base == 0xffffffff)
4122 rte_write32(reg_base, (uint8_t *)bp->bar0 +
4123 BNXT_GRCPF_REG_WINDOW_BASE_OUT + 4);
4128 static void bnxt_write_fw_reset_reg(struct bnxt *bp, uint32_t index)
4130 struct bnxt_error_recovery_info *info = bp->recovery_info;
4131 uint32_t delay = info->delay_after_reset[index];
4132 uint32_t val = info->reset_reg_val[index];
4133 uint32_t reg = info->reset_reg[index];
4134 uint32_t type, offset;
4137 type = BNXT_FW_STATUS_REG_TYPE(reg);
4138 offset = BNXT_FW_STATUS_REG_OFF(reg);
4141 case BNXT_FW_STATUS_REG_TYPE_CFG:
4142 ret = rte_pci_write_config(bp->pdev, &val, sizeof(val), offset);
4144 PMD_DRV_LOG(ERR, "Failed to write %#x at PCI offset %#x",
4149 case BNXT_FW_STATUS_REG_TYPE_GRC:
4150 offset = bnxt_map_reset_regs(bp, offset);
4151 rte_write32(val, (uint8_t *)bp->bar0 + offset);
4153 case BNXT_FW_STATUS_REG_TYPE_BAR0:
4154 rte_write32(val, (uint8_t *)bp->bar0 + offset);
4157 /* wait on a specific interval of time until core reset is complete */
4159 rte_delay_ms(delay);
4162 static void bnxt_dev_cleanup(struct bnxt *bp)
4164 bp->eth_dev->data->dev_link.link_status = 0;
4165 bp->link_info->link_up = 0;
4166 if (bp->eth_dev->data->dev_started)
4167 bnxt_dev_stop(bp->eth_dev);
4169 bnxt_uninit_resources(bp, true);
4173 bnxt_check_fw_reset_done(struct bnxt *bp)
4175 int timeout = bp->fw_reset_max_msecs;
4180 rc = rte_pci_read_config(bp->pdev, &val, sizeof(val), PCI_SUBSYSTEM_ID_OFFSET);
4182 PMD_DRV_LOG(ERR, "Failed to read PCI offset 0x%x", PCI_SUBSYSTEM_ID_OFFSET);
4188 } while (timeout--);
4190 if (val == 0xffff) {
4191 PMD_DRV_LOG(ERR, "Firmware reset aborted, PCI config space invalid\n");
4198 static int bnxt_restore_vlan_filters(struct bnxt *bp)
4200 struct rte_eth_dev *dev = bp->eth_dev;
4201 struct rte_vlan_filter_conf *vfc;
4205 for (vlan_id = 1; vlan_id <= RTE_ETHER_MAX_VLAN_ID; vlan_id++) {
4206 vfc = &dev->data->vlan_filter_conf;
4207 vidx = vlan_id / 64;
4208 vbit = vlan_id % 64;
4210 /* Each bit corresponds to a VLAN id */
4211 if (vfc->ids[vidx] & (UINT64_C(1) << vbit)) {
4212 rc = bnxt_add_vlan_filter(bp, vlan_id);
4221 static int bnxt_restore_mac_filters(struct bnxt *bp)
4223 struct rte_eth_dev *dev = bp->eth_dev;
4224 struct rte_eth_dev_info dev_info;
4225 struct rte_ether_addr *addr;
4231 if (BNXT_VF(bp) && !BNXT_VF_IS_TRUSTED(bp))
4234 rc = bnxt_dev_info_get_op(dev, &dev_info);
4238 /* replay MAC address configuration */
4239 for (i = 1; i < dev_info.max_mac_addrs; i++) {
4240 addr = &dev->data->mac_addrs[i];
4242 /* skip zero address */
4243 if (rte_is_zero_ether_addr(addr))
4247 pool_mask = dev->data->mac_pool_sel[i];
4250 if (pool_mask & 1ULL) {
4251 rc = bnxt_mac_addr_add_op(dev, addr, i, pool);
4257 } while (pool_mask);
4263 static int bnxt_restore_filters(struct bnxt *bp)
4265 struct rte_eth_dev *dev = bp->eth_dev;
4268 if (dev->data->all_multicast) {
4269 ret = bnxt_allmulticast_enable_op(dev);
4273 if (dev->data->promiscuous) {
4274 ret = bnxt_promiscuous_enable_op(dev);
4279 ret = bnxt_restore_mac_filters(bp);
4283 ret = bnxt_restore_vlan_filters(bp);
4284 /* TODO restore other filters as well */
4288 static int bnxt_check_fw_ready(struct bnxt *bp)
4290 int timeout = bp->fw_reset_max_msecs;
4294 rc = bnxt_hwrm_poll_ver_get(bp);
4297 rte_delay_ms(BNXT_FW_READY_WAIT_INTERVAL);
4298 timeout -= BNXT_FW_READY_WAIT_INTERVAL;
4299 } while (rc && timeout > 0);
4302 PMD_DRV_LOG(ERR, "FW is not Ready after reset\n");
4307 static void bnxt_dev_recover(void *arg)
4309 struct bnxt *bp = arg;
4312 pthread_mutex_lock(&bp->err_recovery_lock);
4314 if (!bp->fw_reset_min_msecs) {
4315 rc = bnxt_check_fw_reset_done(bp);
4320 /* Clear Error flag so that device re-init should happen */
4321 bp->flags &= ~BNXT_FLAG_FATAL_ERROR;
4323 rc = bnxt_check_fw_ready(bp);
4327 rc = bnxt_init_resources(bp, true);
4330 "Failed to initialize resources after reset\n");
4333 /* clear reset flag as the device is initialized now */
4334 bp->flags &= ~BNXT_FLAG_FW_RESET;
4336 rc = bnxt_dev_start_op(bp->eth_dev);
4338 PMD_DRV_LOG(ERR, "Failed to start port after reset\n");
4342 rc = bnxt_restore_filters(bp);
4346 PMD_DRV_LOG(INFO, "Recovered from FW reset\n");
4347 pthread_mutex_unlock(&bp->err_recovery_lock);
4351 bnxt_dev_stop(bp->eth_dev);
4353 bp->flags |= BNXT_FLAG_FATAL_ERROR;
4354 bnxt_uninit_resources(bp, false);
4355 if (bp->eth_dev->data->dev_conf.intr_conf.rmv)
4356 rte_eth_dev_callback_process(bp->eth_dev,
4357 RTE_ETH_EVENT_INTR_RMV,
4359 pthread_mutex_unlock(&bp->err_recovery_lock);
4360 PMD_DRV_LOG(ERR, "Failed to recover from FW reset\n");
4363 void bnxt_dev_reset_and_resume(void *arg)
4365 struct bnxt *bp = arg;
4366 uint32_t us = US_PER_MS * bp->fw_reset_min_msecs;
4370 bnxt_dev_cleanup(bp);
4372 bnxt_wait_for_device_shutdown(bp);
4374 /* During some fatal firmware error conditions, the PCI config space
4375 * register 0x2e which normally contains the subsystem ID will become
4376 * 0xffff. This register will revert back to the normal value after
4377 * the chip has completed core reset. If we detect this condition,
4378 * we can poll this config register immediately for the value to revert.
4380 if (bp->flags & BNXT_FLAG_FATAL_ERROR) {
4381 rc = rte_pci_read_config(bp->pdev, &val, sizeof(val), PCI_SUBSYSTEM_ID_OFFSET);
4383 PMD_DRV_LOG(ERR, "Failed to read PCI offset 0x%x", PCI_SUBSYSTEM_ID_OFFSET);
4386 if (val == 0xffff) {
4387 bp->fw_reset_min_msecs = 0;
4392 rc = rte_eal_alarm_set(us, bnxt_dev_recover, (void *)bp);
4394 PMD_DRV_LOG(ERR, "Error setting recovery alarm");
4397 uint32_t bnxt_read_fw_status_reg(struct bnxt *bp, uint32_t index)
4399 struct bnxt_error_recovery_info *info = bp->recovery_info;
4400 uint32_t reg = info->status_regs[index];
4401 uint32_t type, offset, val = 0;
4404 type = BNXT_FW_STATUS_REG_TYPE(reg);
4405 offset = BNXT_FW_STATUS_REG_OFF(reg);
4408 case BNXT_FW_STATUS_REG_TYPE_CFG:
4409 ret = rte_pci_read_config(bp->pdev, &val, sizeof(val), offset);
4411 PMD_DRV_LOG(ERR, "Failed to read PCI offset %#x",
4414 case BNXT_FW_STATUS_REG_TYPE_GRC:
4415 offset = info->mapped_status_regs[index];
4417 case BNXT_FW_STATUS_REG_TYPE_BAR0:
4418 val = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
4426 static int bnxt_fw_reset_all(struct bnxt *bp)
4428 struct bnxt_error_recovery_info *info = bp->recovery_info;
4432 if (info->flags & BNXT_FLAG_ERROR_RECOVERY_HOST) {
4433 /* Reset through master function driver */
4434 for (i = 0; i < info->reg_array_cnt; i++)
4435 bnxt_write_fw_reset_reg(bp, i);
4436 /* Wait for time specified by FW after triggering reset */
4437 rte_delay_ms(info->master_func_wait_period_after_reset);
4438 } else if (info->flags & BNXT_FLAG_ERROR_RECOVERY_CO_CPU) {
4439 /* Reset with the help of Kong processor */
4440 rc = bnxt_hwrm_fw_reset(bp);
4442 PMD_DRV_LOG(ERR, "Failed to reset FW\n");
4448 static void bnxt_fw_reset_cb(void *arg)
4450 struct bnxt *bp = arg;
4451 struct bnxt_error_recovery_info *info = bp->recovery_info;
4454 /* Only Master function can do FW reset */
4455 if (bnxt_is_master_func(bp) &&
4456 bnxt_is_recovery_enabled(bp)) {
4457 rc = bnxt_fw_reset_all(bp);
4459 PMD_DRV_LOG(ERR, "Adapter recovery failed\n");
4464 /* if recovery method is ERROR_RECOVERY_CO_CPU, KONG will send
4465 * EXCEPTION_FATAL_ASYNC event to all the functions
4466 * (including MASTER FUNC). After receiving this Async, all the active
4467 * drivers should treat this case as FW initiated recovery
4469 if (info->flags & BNXT_FLAG_ERROR_RECOVERY_HOST) {
4470 bp->fw_reset_min_msecs = BNXT_MIN_FW_READY_TIMEOUT;
4471 bp->fw_reset_max_msecs = BNXT_MAX_FW_RESET_TIMEOUT;
4473 /* To recover from error */
4474 rte_eal_alarm_set(US_PER_MS, bnxt_dev_reset_and_resume,
4479 /* Driver should poll FW heartbeat, reset_counter with the frequency
4480 * advertised by FW in HWRM_ERROR_RECOVERY_QCFG.
4481 * When the driver detects heartbeat stop or change in reset_counter,
4482 * it has to trigger a reset to recover from the error condition.
4483 * A “master PF” is the function who will have the privilege to
4484 * initiate the chimp reset. The master PF will be elected by the
4485 * firmware and will be notified through async message.
4487 static void bnxt_check_fw_health(void *arg)
4489 struct bnxt *bp = arg;
4490 struct bnxt_error_recovery_info *info = bp->recovery_info;
4491 uint32_t val = 0, wait_msec;
4493 if (!info || !bnxt_is_recovery_enabled(bp) ||
4494 is_bnxt_in_error(bp))
4497 val = bnxt_read_fw_status_reg(bp, BNXT_FW_HEARTBEAT_CNT_REG);
4498 if (val == info->last_heart_beat)
4501 info->last_heart_beat = val;
4503 val = bnxt_read_fw_status_reg(bp, BNXT_FW_RECOVERY_CNT_REG);
4504 if (val != info->last_reset_counter)
4507 info->last_reset_counter = val;
4509 rte_eal_alarm_set(US_PER_MS * info->driver_polling_freq,
4510 bnxt_check_fw_health, (void *)bp);
4514 /* Stop DMA to/from device */
4515 bp->flags |= BNXT_FLAG_FATAL_ERROR;
4516 bp->flags |= BNXT_FLAG_FW_RESET;
4520 PMD_DRV_LOG(ERR, "Detected FW dead condition\n");
4522 if (bnxt_is_master_func(bp))
4523 wait_msec = info->master_func_wait_period;
4525 wait_msec = info->normal_func_wait_period;
4527 rte_eal_alarm_set(US_PER_MS * wait_msec,
4528 bnxt_fw_reset_cb, (void *)bp);
4531 void bnxt_schedule_fw_health_check(struct bnxt *bp)
4533 uint32_t polling_freq;
4535 pthread_mutex_lock(&bp->health_check_lock);
4537 if (!bnxt_is_recovery_enabled(bp))
4540 if (bp->flags & BNXT_FLAG_FW_HEALTH_CHECK_SCHEDULED)
4543 polling_freq = bp->recovery_info->driver_polling_freq;
4545 rte_eal_alarm_set(US_PER_MS * polling_freq,
4546 bnxt_check_fw_health, (void *)bp);
4547 bp->flags |= BNXT_FLAG_FW_HEALTH_CHECK_SCHEDULED;
4550 pthread_mutex_unlock(&bp->health_check_lock);
4553 static void bnxt_cancel_fw_health_check(struct bnxt *bp)
4555 rte_eal_alarm_cancel(bnxt_check_fw_health, (void *)bp);
4556 bp->flags &= ~BNXT_FLAG_FW_HEALTH_CHECK_SCHEDULED;
4559 static bool bnxt_vf_pciid(uint16_t device_id)
4561 switch (device_id) {
4562 case BROADCOM_DEV_ID_57304_VF:
4563 case BROADCOM_DEV_ID_57406_VF:
4564 case BROADCOM_DEV_ID_5731X_VF:
4565 case BROADCOM_DEV_ID_5741X_VF:
4566 case BROADCOM_DEV_ID_57414_VF:
4567 case BROADCOM_DEV_ID_STRATUS_NIC_VF1:
4568 case BROADCOM_DEV_ID_STRATUS_NIC_VF2:
4569 case BROADCOM_DEV_ID_58802_VF:
4570 case BROADCOM_DEV_ID_57500_VF1:
4571 case BROADCOM_DEV_ID_57500_VF2:
4572 case BROADCOM_DEV_ID_58818_VF:
4580 /* Phase 5 device */
4581 static bool bnxt_p5_device(uint16_t device_id)
4583 switch (device_id) {
4584 case BROADCOM_DEV_ID_57508:
4585 case BROADCOM_DEV_ID_57504:
4586 case BROADCOM_DEV_ID_57502:
4587 case BROADCOM_DEV_ID_57508_MF1:
4588 case BROADCOM_DEV_ID_57504_MF1:
4589 case BROADCOM_DEV_ID_57502_MF1:
4590 case BROADCOM_DEV_ID_57508_MF2:
4591 case BROADCOM_DEV_ID_57504_MF2:
4592 case BROADCOM_DEV_ID_57502_MF2:
4593 case BROADCOM_DEV_ID_57500_VF1:
4594 case BROADCOM_DEV_ID_57500_VF2:
4595 case BROADCOM_DEV_ID_58812:
4596 case BROADCOM_DEV_ID_58814:
4597 case BROADCOM_DEV_ID_58818:
4598 case BROADCOM_DEV_ID_58818_VF:
4606 bool bnxt_stratus_device(struct bnxt *bp)
4608 uint16_t device_id = bp->pdev->id.device_id;
4610 switch (device_id) {
4611 case BROADCOM_DEV_ID_STRATUS_NIC:
4612 case BROADCOM_DEV_ID_STRATUS_NIC_VF1:
4613 case BROADCOM_DEV_ID_STRATUS_NIC_VF2:
4621 static int bnxt_map_pci_bars(struct rte_eth_dev *eth_dev)
4623 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
4624 struct bnxt *bp = eth_dev->data->dev_private;
4626 /* enable device (incl. PCI PM wakeup), and bus-mastering */
4627 bp->bar0 = (void *)pci_dev->mem_resource[0].addr;
4628 bp->doorbell_base = (void *)pci_dev->mem_resource[2].addr;
4629 if (!bp->bar0 || !bp->doorbell_base) {
4630 PMD_DRV_LOG(ERR, "Unable to access Hardware\n");
4634 bp->eth_dev = eth_dev;
4640 static int bnxt_alloc_ctx_mem_blk(struct bnxt *bp,
4641 struct bnxt_ctx_pg_info *ctx_pg,
4646 struct bnxt_ring_mem_info *rmem = &ctx_pg->ring_mem;
4647 const struct rte_memzone *mz = NULL;
4648 char mz_name[RTE_MEMZONE_NAMESIZE];
4649 rte_iova_t mz_phys_addr;
4650 uint64_t valid_bits = 0;
4657 rmem->nr_pages = RTE_ALIGN_MUL_CEIL(mem_size, BNXT_PAGE_SIZE) /
4659 rmem->page_size = BNXT_PAGE_SIZE;
4660 rmem->pg_arr = ctx_pg->ctx_pg_arr;
4661 rmem->dma_arr = ctx_pg->ctx_dma_arr;
4662 rmem->flags = BNXT_RMEM_VALID_PTE_FLAG;
4664 valid_bits = PTU_PTE_VALID;
4666 if (rmem->nr_pages > 1) {
4667 snprintf(mz_name, RTE_MEMZONE_NAMESIZE,
4668 "bnxt_ctx_pg_tbl%s_%x_%d",
4669 suffix, idx, bp->eth_dev->data->port_id);
4670 mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0;
4671 mz = rte_memzone_lookup(mz_name);
4673 mz = rte_memzone_reserve_aligned(mz_name,
4675 bp->eth_dev->device->numa_node,
4677 RTE_MEMZONE_SIZE_HINT_ONLY |
4678 RTE_MEMZONE_IOVA_CONTIG,
4684 memset(mz->addr, 0, mz->len);
4685 mz_phys_addr = mz->iova;
4687 rmem->pg_tbl = mz->addr;
4688 rmem->pg_tbl_map = mz_phys_addr;
4689 rmem->pg_tbl_mz = mz;
4692 snprintf(mz_name, RTE_MEMZONE_NAMESIZE, "bnxt_ctx_%s_%x_%d",
4693 suffix, idx, bp->eth_dev->data->port_id);
4694 mz = rte_memzone_lookup(mz_name);
4696 mz = rte_memzone_reserve_aligned(mz_name,
4698 bp->eth_dev->device->numa_node,
4700 RTE_MEMZONE_SIZE_HINT_ONLY |
4701 RTE_MEMZONE_IOVA_CONTIG,
4707 memset(mz->addr, 0, mz->len);
4708 mz_phys_addr = mz->iova;
4710 for (sz = 0, i = 0; sz < mem_size; sz += BNXT_PAGE_SIZE, i++) {
4711 rmem->pg_arr[i] = ((char *)mz->addr) + sz;
4712 rmem->dma_arr[i] = mz_phys_addr + sz;
4714 if (rmem->nr_pages > 1) {
4715 if (i == rmem->nr_pages - 2 &&
4716 (rmem->flags & BNXT_RMEM_RING_PTE_FLAG))
4717 valid_bits |= PTU_PTE_NEXT_TO_LAST;
4718 else if (i == rmem->nr_pages - 1 &&
4719 (rmem->flags & BNXT_RMEM_RING_PTE_FLAG))
4720 valid_bits |= PTU_PTE_LAST;
4722 rmem->pg_tbl[i] = rte_cpu_to_le_64(rmem->dma_arr[i] |
4728 if (rmem->vmem_size)
4729 rmem->vmem = (void **)mz->addr;
4730 rmem->dma_arr[0] = mz_phys_addr;
4734 static void bnxt_free_ctx_mem(struct bnxt *bp)
4738 if (!bp->ctx || !(bp->ctx->flags & BNXT_CTX_FLAG_INITED))
4741 bp->ctx->flags &= ~BNXT_CTX_FLAG_INITED;
4742 rte_memzone_free(bp->ctx->qp_mem.ring_mem.mz);
4743 rte_memzone_free(bp->ctx->srq_mem.ring_mem.mz);
4744 rte_memzone_free(bp->ctx->cq_mem.ring_mem.mz);
4745 rte_memzone_free(bp->ctx->vnic_mem.ring_mem.mz);
4746 rte_memzone_free(bp->ctx->stat_mem.ring_mem.mz);
4747 rte_memzone_free(bp->ctx->qp_mem.ring_mem.pg_tbl_mz);
4748 rte_memzone_free(bp->ctx->srq_mem.ring_mem.pg_tbl_mz);
4749 rte_memzone_free(bp->ctx->cq_mem.ring_mem.pg_tbl_mz);
4750 rte_memzone_free(bp->ctx->vnic_mem.ring_mem.pg_tbl_mz);
4751 rte_memzone_free(bp->ctx->stat_mem.ring_mem.pg_tbl_mz);
4753 for (i = 0; i < bp->ctx->tqm_fp_rings_count + 1; i++) {
4754 if (bp->ctx->tqm_mem[i])
4755 rte_memzone_free(bp->ctx->tqm_mem[i]->ring_mem.mz);
4762 #define bnxt_roundup(x, y) ((((x) + ((y) - 1)) / (y)) * (y))
4764 #define min_t(type, x, y) ({ \
4765 type __min1 = (x); \
4766 type __min2 = (y); \
4767 __min1 < __min2 ? __min1 : __min2; })
4769 #define max_t(type, x, y) ({ \
4770 type __max1 = (x); \
4771 type __max2 = (y); \
4772 __max1 > __max2 ? __max1 : __max2; })
4774 #define clamp_t(type, _x, min, max) min_t(type, max_t(type, _x, min), max)
4776 int bnxt_alloc_ctx_mem(struct bnxt *bp)
4778 struct bnxt_ctx_pg_info *ctx_pg;
4779 struct bnxt_ctx_mem_info *ctx;
4780 uint32_t mem_size, ena, entries;
4781 uint32_t entries_sp, min;
4784 rc = bnxt_hwrm_func_backing_store_qcaps(bp);
4786 PMD_DRV_LOG(ERR, "Query context mem capability failed\n");
4790 if (!ctx || (ctx->flags & BNXT_CTX_FLAG_INITED))
4793 ctx_pg = &ctx->qp_mem;
4794 ctx_pg->entries = ctx->qp_min_qp1_entries + ctx->qp_max_l2_entries;
4795 if (ctx->qp_entry_size) {
4796 mem_size = ctx->qp_entry_size * ctx_pg->entries;
4797 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "qp_mem", 0);
4802 ctx_pg = &ctx->srq_mem;
4803 ctx_pg->entries = ctx->srq_max_l2_entries;
4804 if (ctx->srq_entry_size) {
4805 mem_size = ctx->srq_entry_size * ctx_pg->entries;
4806 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "srq_mem", 0);
4811 ctx_pg = &ctx->cq_mem;
4812 ctx_pg->entries = ctx->cq_max_l2_entries;
4813 if (ctx->cq_entry_size) {
4814 mem_size = ctx->cq_entry_size * ctx_pg->entries;
4815 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "cq_mem", 0);
4820 ctx_pg = &ctx->vnic_mem;
4821 ctx_pg->entries = ctx->vnic_max_vnic_entries +
4822 ctx->vnic_max_ring_table_entries;
4823 if (ctx->vnic_entry_size) {
4824 mem_size = ctx->vnic_entry_size * ctx_pg->entries;
4825 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "vnic_mem", 0);
4830 ctx_pg = &ctx->stat_mem;
4831 ctx_pg->entries = ctx->stat_max_entries;
4832 if (ctx->stat_entry_size) {
4833 mem_size = ctx->stat_entry_size * ctx_pg->entries;
4834 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "stat_mem", 0);
4839 min = ctx->tqm_min_entries_per_ring;
4841 entries_sp = ctx->qp_max_l2_entries +
4842 ctx->vnic_max_vnic_entries +
4843 2 * ctx->qp_min_qp1_entries + min;
4844 entries_sp = bnxt_roundup(entries_sp, ctx->tqm_entries_multiple);
4846 entries = ctx->qp_max_l2_entries + ctx->qp_min_qp1_entries;
4847 entries = bnxt_roundup(entries, ctx->tqm_entries_multiple);
4848 entries = clamp_t(uint32_t, entries, min,
4849 ctx->tqm_max_entries_per_ring);
4850 for (i = 0, ena = 0; i < ctx->tqm_fp_rings_count + 1; i++) {
4851 /* i=0 is for TQM_SP. i=1 to i=8 applies to RING0 to RING7.
4852 * i > 8 is other ext rings.
4854 ctx_pg = ctx->tqm_mem[i];
4855 ctx_pg->entries = i ? entries : entries_sp;
4856 if (ctx->tqm_entry_size) {
4857 mem_size = ctx->tqm_entry_size * ctx_pg->entries;
4858 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size,
4863 if (i < BNXT_MAX_TQM_LEGACY_RINGS)
4864 ena |= HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_SP << i;
4866 ena |= HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_RING8;
4869 ena |= FUNC_BACKING_STORE_CFG_INPUT_DFLT_ENABLES;
4870 rc = bnxt_hwrm_func_backing_store_cfg(bp, ena);
4873 "Failed to configure context mem: rc = %d\n", rc);
4875 ctx->flags |= BNXT_CTX_FLAG_INITED;
4880 static int bnxt_alloc_stats_mem(struct bnxt *bp)
4882 struct rte_pci_device *pci_dev = bp->pdev;
4883 char mz_name[RTE_MEMZONE_NAMESIZE];
4884 const struct rte_memzone *mz = NULL;
4885 uint32_t total_alloc_len;
4886 rte_iova_t mz_phys_addr;
4888 if (pci_dev->id.device_id == BROADCOM_DEV_ID_NS2)
4891 snprintf(mz_name, RTE_MEMZONE_NAMESIZE,
4892 "bnxt_" PCI_PRI_FMT "-%s", pci_dev->addr.domain,
4893 pci_dev->addr.bus, pci_dev->addr.devid,
4894 pci_dev->addr.function, "rx_port_stats");
4895 mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0;
4896 mz = rte_memzone_lookup(mz_name);
4898 RTE_CACHE_LINE_ROUNDUP(sizeof(struct rx_port_stats) +
4899 sizeof(struct rx_port_stats_ext) + 512);
4901 mz = rte_memzone_reserve(mz_name, total_alloc_len,
4904 RTE_MEMZONE_SIZE_HINT_ONLY |
4905 RTE_MEMZONE_IOVA_CONTIG);
4909 memset(mz->addr, 0, mz->len);
4910 mz_phys_addr = mz->iova;
4912 bp->rx_mem_zone = (const void *)mz;
4913 bp->hw_rx_port_stats = mz->addr;
4914 bp->hw_rx_port_stats_map = mz_phys_addr;
4916 snprintf(mz_name, RTE_MEMZONE_NAMESIZE,
4917 "bnxt_" PCI_PRI_FMT "-%s", pci_dev->addr.domain,
4918 pci_dev->addr.bus, pci_dev->addr.devid,
4919 pci_dev->addr.function, "tx_port_stats");
4920 mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0;
4921 mz = rte_memzone_lookup(mz_name);
4923 RTE_CACHE_LINE_ROUNDUP(sizeof(struct tx_port_stats) +
4924 sizeof(struct tx_port_stats_ext) + 512);
4926 mz = rte_memzone_reserve(mz_name,
4930 RTE_MEMZONE_SIZE_HINT_ONLY |
4931 RTE_MEMZONE_IOVA_CONTIG);
4935 memset(mz->addr, 0, mz->len);
4936 mz_phys_addr = mz->iova;
4938 bp->tx_mem_zone = (const void *)mz;
4939 bp->hw_tx_port_stats = mz->addr;
4940 bp->hw_tx_port_stats_map = mz_phys_addr;
4941 bp->flags |= BNXT_FLAG_PORT_STATS;
4943 /* Display extended statistics if FW supports it */
4944 if (bp->hwrm_spec_code < HWRM_SPEC_CODE_1_8_4 ||
4945 bp->hwrm_spec_code == HWRM_SPEC_CODE_1_9_0 ||
4946 !(bp->flags & BNXT_FLAG_EXT_STATS_SUPPORTED))
4949 bp->hw_rx_port_stats_ext = (void *)
4950 ((uint8_t *)bp->hw_rx_port_stats +
4951 sizeof(struct rx_port_stats));
4952 bp->hw_rx_port_stats_ext_map = bp->hw_rx_port_stats_map +
4953 sizeof(struct rx_port_stats);
4954 bp->flags |= BNXT_FLAG_EXT_RX_PORT_STATS;
4956 if (bp->hwrm_spec_code < HWRM_SPEC_CODE_1_9_2 ||
4957 bp->flags & BNXT_FLAG_EXT_STATS_SUPPORTED) {
4958 bp->hw_tx_port_stats_ext = (void *)
4959 ((uint8_t *)bp->hw_tx_port_stats +
4960 sizeof(struct tx_port_stats));
4961 bp->hw_tx_port_stats_ext_map =
4962 bp->hw_tx_port_stats_map +
4963 sizeof(struct tx_port_stats);
4964 bp->flags |= BNXT_FLAG_EXT_TX_PORT_STATS;
4970 static int bnxt_setup_mac_addr(struct rte_eth_dev *eth_dev)
4972 struct bnxt *bp = eth_dev->data->dev_private;
4975 eth_dev->data->mac_addrs = rte_zmalloc("bnxt_mac_addr_tbl",
4976 RTE_ETHER_ADDR_LEN *
4979 if (eth_dev->data->mac_addrs == NULL) {
4980 PMD_DRV_LOG(ERR, "Failed to alloc MAC addr tbl\n");
4984 if (!BNXT_HAS_DFLT_MAC_SET(bp)) {
4988 /* Generate a random MAC address, if none was assigned by PF */
4989 PMD_DRV_LOG(INFO, "VF MAC address not assigned by Host PF\n");
4990 bnxt_eth_hw_addr_random(bp->mac_addr);
4992 "Assign random MAC:%02X:%02X:%02X:%02X:%02X:%02X\n",
4993 bp->mac_addr[0], bp->mac_addr[1], bp->mac_addr[2],
4994 bp->mac_addr[3], bp->mac_addr[4], bp->mac_addr[5]);
4996 rc = bnxt_hwrm_set_mac(bp);
5001 /* Copy the permanent MAC from the FUNC_QCAPS response */
5002 memcpy(ð_dev->data->mac_addrs[0], bp->mac_addr, RTE_ETHER_ADDR_LEN);
5007 static int bnxt_restore_dflt_mac(struct bnxt *bp)
5011 /* MAC is already configured in FW */
5012 if (BNXT_HAS_DFLT_MAC_SET(bp))
5015 /* Restore the old MAC configured */
5016 rc = bnxt_hwrm_set_mac(bp);
5018 PMD_DRV_LOG(ERR, "Failed to restore MAC address\n");
5023 static void bnxt_config_vf_req_fwd(struct bnxt *bp)
5028 memset(bp->pf->vf_req_fwd, 0, sizeof(bp->pf->vf_req_fwd));
5030 if (!(bp->fw_cap & BNXT_FW_CAP_LINK_ADMIN))
5031 BNXT_HWRM_CMD_TO_FORWARD(HWRM_PORT_PHY_QCFG);
5032 BNXT_HWRM_CMD_TO_FORWARD(HWRM_FUNC_CFG);
5033 BNXT_HWRM_CMD_TO_FORWARD(HWRM_FUNC_VF_CFG);
5034 BNXT_HWRM_CMD_TO_FORWARD(HWRM_CFA_L2_FILTER_ALLOC);
5035 BNXT_HWRM_CMD_TO_FORWARD(HWRM_OEM_CMD);
5039 bnxt_get_bp(uint16_t port)
5042 struct rte_eth_dev *dev;
5044 if (!rte_eth_dev_is_valid_port(port)) {
5045 PMD_DRV_LOG(ERR, "Invalid port %d\n", port);
5049 dev = &rte_eth_devices[port];
5050 if (!is_bnxt_supported(dev)) {
5051 PMD_DRV_LOG(ERR, "Device %d not supported\n", port);
5055 bp = (struct bnxt *)dev->data->dev_private;
5056 if (!BNXT_TRUFLOW_EN(bp)) {
5057 PMD_DRV_LOG(ERR, "TRUFLOW not enabled\n");
5065 bnxt_get_svif(uint16_t port_id, bool func_svif,
5066 enum bnxt_ulp_intf_type type)
5068 struct rte_eth_dev *eth_dev;
5071 eth_dev = &rte_eth_devices[port_id];
5072 if (BNXT_ETH_DEV_IS_REPRESENTOR(eth_dev)) {
5073 struct bnxt_representor *vfr = eth_dev->data->dev_private;
5077 if (type == BNXT_ULP_INTF_TYPE_VF_REP)
5080 eth_dev = vfr->parent_dev;
5083 bp = eth_dev->data->dev_private;
5085 return func_svif ? bp->func_svif : bp->port_svif;
5089 bnxt_get_iface_mac(uint16_t port, enum bnxt_ulp_intf_type type,
5090 uint8_t *mac, uint8_t *parent_mac)
5092 struct rte_eth_dev *eth_dev;
5095 if (type != BNXT_ULP_INTF_TYPE_TRUSTED_VF &&
5096 type != BNXT_ULP_INTF_TYPE_PF)
5099 eth_dev = &rte_eth_devices[port];
5100 bp = eth_dev->data->dev_private;
5101 memcpy(mac, bp->mac_addr, RTE_ETHER_ADDR_LEN);
5103 if (type == BNXT_ULP_INTF_TYPE_TRUSTED_VF)
5104 memcpy(parent_mac, bp->parent->mac_addr, RTE_ETHER_ADDR_LEN);
5108 bnxt_get_parent_vnic_id(uint16_t port, enum bnxt_ulp_intf_type type)
5110 struct rte_eth_dev *eth_dev;
5113 if (type != BNXT_ULP_INTF_TYPE_TRUSTED_VF)
5116 eth_dev = &rte_eth_devices[port];
5117 bp = eth_dev->data->dev_private;
5119 return bp->parent->vnic;
5122 bnxt_get_vnic_id(uint16_t port, enum bnxt_ulp_intf_type type)
5124 struct rte_eth_dev *eth_dev;
5125 struct bnxt_vnic_info *vnic;
5128 eth_dev = &rte_eth_devices[port];
5129 if (BNXT_ETH_DEV_IS_REPRESENTOR(eth_dev)) {
5130 struct bnxt_representor *vfr = eth_dev->data->dev_private;
5134 if (type == BNXT_ULP_INTF_TYPE_VF_REP)
5135 return vfr->dflt_vnic_id;
5137 eth_dev = vfr->parent_dev;
5140 bp = eth_dev->data->dev_private;
5142 vnic = BNXT_GET_DEFAULT_VNIC(bp);
5144 return vnic->fw_vnic_id;
5148 bnxt_get_fw_func_id(uint16_t port, enum bnxt_ulp_intf_type type)
5150 struct rte_eth_dev *eth_dev;
5153 eth_dev = &rte_eth_devices[port];
5154 if (BNXT_ETH_DEV_IS_REPRESENTOR(eth_dev)) {
5155 struct bnxt_representor *vfr = eth_dev->data->dev_private;
5159 if (type == BNXT_ULP_INTF_TYPE_VF_REP)
5162 eth_dev = vfr->parent_dev;
5165 bp = eth_dev->data->dev_private;
5170 enum bnxt_ulp_intf_type
5171 bnxt_get_interface_type(uint16_t port)
5173 struct rte_eth_dev *eth_dev;
5176 eth_dev = &rte_eth_devices[port];
5177 if (BNXT_ETH_DEV_IS_REPRESENTOR(eth_dev))
5178 return BNXT_ULP_INTF_TYPE_VF_REP;
5180 bp = eth_dev->data->dev_private;
5182 return BNXT_ULP_INTF_TYPE_PF;
5183 else if (BNXT_VF_IS_TRUSTED(bp))
5184 return BNXT_ULP_INTF_TYPE_TRUSTED_VF;
5185 else if (BNXT_VF(bp))
5186 return BNXT_ULP_INTF_TYPE_VF;
5188 return BNXT_ULP_INTF_TYPE_INVALID;
5192 bnxt_get_phy_port_id(uint16_t port_id)
5194 struct bnxt_representor *vfr;
5195 struct rte_eth_dev *eth_dev;
5198 eth_dev = &rte_eth_devices[port_id];
5199 if (BNXT_ETH_DEV_IS_REPRESENTOR(eth_dev)) {
5200 vfr = eth_dev->data->dev_private;
5204 eth_dev = vfr->parent_dev;
5207 bp = eth_dev->data->dev_private;
5209 return BNXT_PF(bp) ? bp->pf->port_id : bp->parent->port_id;
5213 bnxt_get_parif(uint16_t port_id, enum bnxt_ulp_intf_type type)
5215 struct rte_eth_dev *eth_dev;
5218 eth_dev = &rte_eth_devices[port_id];
5219 if (BNXT_ETH_DEV_IS_REPRESENTOR(eth_dev)) {
5220 struct bnxt_representor *vfr = eth_dev->data->dev_private;
5224 if (type == BNXT_ULP_INTF_TYPE_VF_REP)
5225 return vfr->fw_fid - 1;
5227 eth_dev = vfr->parent_dev;
5230 bp = eth_dev->data->dev_private;
5232 return BNXT_PF(bp) ? bp->fw_fid - 1 : bp->parent->fid - 1;
5236 bnxt_get_vport(uint16_t port_id)
5238 return (1 << bnxt_get_phy_port_id(port_id));
5241 static void bnxt_alloc_error_recovery_info(struct bnxt *bp)
5243 struct bnxt_error_recovery_info *info = bp->recovery_info;
5246 if (!(bp->fw_cap & BNXT_FW_CAP_HCOMM_FW_STATUS))
5247 memset(info, 0, sizeof(*info));
5251 if (!(bp->fw_cap & BNXT_FW_CAP_ERROR_RECOVERY))
5254 info = rte_zmalloc("bnxt_hwrm_error_recovery_qcfg",
5257 bp->fw_cap &= ~BNXT_FW_CAP_ERROR_RECOVERY;
5259 bp->recovery_info = info;
5262 static void bnxt_check_fw_status(struct bnxt *bp)
5266 if (!(bp->recovery_info &&
5267 (bp->fw_cap & BNXT_FW_CAP_HCOMM_FW_STATUS)))
5270 fw_status = bnxt_read_fw_status_reg(bp, BNXT_FW_STATUS_REG);
5271 if (fw_status != BNXT_FW_STATUS_HEALTHY)
5272 PMD_DRV_LOG(ERR, "Firmware not responding, status: %#x\n",
5276 static int bnxt_map_hcomm_fw_status_reg(struct bnxt *bp)
5278 struct bnxt_error_recovery_info *info = bp->recovery_info;
5279 uint32_t status_loc;
5282 rte_write32(HCOMM_STATUS_STRUCT_LOC, (uint8_t *)bp->bar0 +
5283 BNXT_GRCPF_REG_WINDOW_BASE_OUT + 4);
5284 sig_ver = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
5285 BNXT_GRCP_WINDOW_2_BASE +
5286 offsetof(struct hcomm_status,
5288 /* If the signature is absent, then FW does not support this feature */
5289 if ((sig_ver & HCOMM_STATUS_SIGNATURE_MASK) !=
5290 HCOMM_STATUS_SIGNATURE_VAL)
5294 info = rte_zmalloc("bnxt_hwrm_error_recovery_qcfg",
5298 bp->recovery_info = info;
5300 memset(info, 0, sizeof(*info));
5303 status_loc = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
5304 BNXT_GRCP_WINDOW_2_BASE +
5305 offsetof(struct hcomm_status,
5308 /* Only pre-map the FW health status GRC register */
5309 if (BNXT_FW_STATUS_REG_TYPE(status_loc) != BNXT_FW_STATUS_REG_TYPE_GRC)
5312 info->status_regs[BNXT_FW_STATUS_REG] = status_loc;
5313 info->mapped_status_regs[BNXT_FW_STATUS_REG] =
5314 BNXT_GRCP_WINDOW_2_BASE + (status_loc & BNXT_GRCP_OFFSET_MASK);
5316 rte_write32((status_loc & BNXT_GRCP_BASE_MASK), (uint8_t *)bp->bar0 +
5317 BNXT_GRCPF_REG_WINDOW_BASE_OUT + 4);
5319 bp->fw_cap |= BNXT_FW_CAP_HCOMM_FW_STATUS;
5324 /* This function gets the FW version along with the
5325 * capabilities(MAX and current) of the function, vnic,
5326 * error recovery, phy and other chip related info
5328 static int bnxt_get_config(struct bnxt *bp)
5335 rc = bnxt_map_hcomm_fw_status_reg(bp);
5339 rc = bnxt_hwrm_ver_get(bp, DFLT_HWRM_CMD_TIMEOUT);
5341 bnxt_check_fw_status(bp);
5345 rc = bnxt_hwrm_func_reset(bp);
5349 rc = bnxt_hwrm_vnic_qcaps(bp);
5353 rc = bnxt_hwrm_queue_qportcfg(bp);
5357 /* Get the MAX capabilities for this function.
5358 * This function also allocates context memory for TQM rings and
5359 * informs the firmware about this allocated backing store memory.
5361 rc = bnxt_hwrm_func_qcaps(bp);
5365 rc = bnxt_hwrm_func_qcfg(bp, &mtu);
5369 rc = bnxt_hwrm_cfa_adv_flow_mgmt_qcaps(bp);
5373 bnxt_hwrm_port_mac_qcfg(bp);
5375 bnxt_hwrm_parent_pf_qcfg(bp);
5377 bnxt_hwrm_port_phy_qcaps(bp);
5379 bnxt_alloc_error_recovery_info(bp);
5380 /* Get the adapter error recovery support info */
5381 rc = bnxt_hwrm_error_recovery_qcfg(bp);
5383 bp->fw_cap &= ~BNXT_FW_CAP_ERROR_RECOVERY;
5385 bnxt_hwrm_port_led_qcaps(bp);
5391 bnxt_init_locks(struct bnxt *bp)
5395 err = pthread_mutex_init(&bp->flow_lock, NULL);
5397 PMD_DRV_LOG(ERR, "Unable to initialize flow_lock\n");
5401 err = pthread_mutex_init(&bp->def_cp_lock, NULL);
5403 PMD_DRV_LOG(ERR, "Unable to initialize def_cp_lock\n");
5407 err = pthread_mutex_init(&bp->health_check_lock, NULL);
5409 PMD_DRV_LOG(ERR, "Unable to initialize health_check_lock\n");
5413 err = pthread_mutex_init(&bp->err_recovery_lock, NULL);
5415 PMD_DRV_LOG(ERR, "Unable to initialize err_recovery_lock\n");
5420 static int bnxt_init_resources(struct bnxt *bp, bool reconfig_dev)
5424 rc = bnxt_get_config(bp);
5428 if (!reconfig_dev) {
5429 rc = bnxt_setup_mac_addr(bp->eth_dev);
5433 rc = bnxt_restore_dflt_mac(bp);
5438 bnxt_config_vf_req_fwd(bp);
5440 rc = bnxt_hwrm_func_driver_register(bp);
5442 PMD_DRV_LOG(ERR, "Failed to register driver");
5447 if (bp->pdev->max_vfs) {
5448 rc = bnxt_hwrm_allocate_vfs(bp, bp->pdev->max_vfs);
5450 PMD_DRV_LOG(ERR, "Failed to allocate VFs\n");
5454 rc = bnxt_hwrm_allocate_pf_only(bp);
5457 "Failed to allocate PF resources");
5463 rc = bnxt_alloc_mem(bp, reconfig_dev);
5467 rc = bnxt_setup_int(bp);
5471 rc = bnxt_request_int(bp);
5475 rc = bnxt_init_ctx_mem(bp);
5477 PMD_DRV_LOG(ERR, "Failed to init adv_flow_counters\n");
5485 bnxt_parse_devarg_accum_stats(__rte_unused const char *key,
5486 const char *value, void *opaque_arg)
5488 struct bnxt *bp = opaque_arg;
5489 unsigned long accum_stats;
5492 if (!value || !opaque_arg) {
5494 "Invalid parameter passed to accum-stats devargs.\n");
5498 accum_stats = strtoul(value, &end, 10);
5499 if (end == NULL || *end != '\0' ||
5500 (accum_stats == ULONG_MAX && errno == ERANGE)) {
5502 "Invalid parameter passed to accum-stats devargs.\n");
5506 if (BNXT_DEVARG_ACCUM_STATS_INVALID(accum_stats)) {
5508 "Invalid value passed to accum-stats devargs.\n");
5513 bp->flags2 |= BNXT_FLAGS2_ACCUM_STATS_EN;
5514 PMD_DRV_LOG(INFO, "Host-based accum-stats feature enabled.\n");
5516 bp->flags2 &= ~BNXT_FLAGS2_ACCUM_STATS_EN;
5517 PMD_DRV_LOG(INFO, "Host-based accum-stats feature disabled.\n");
5524 bnxt_parse_devarg_flow_xstat(__rte_unused const char *key,
5525 const char *value, void *opaque_arg)
5527 struct bnxt *bp = opaque_arg;
5528 unsigned long flow_xstat;
5531 if (!value || !opaque_arg) {
5533 "Invalid parameter passed to flow_xstat devarg.\n");
5537 flow_xstat = strtoul(value, &end, 10);
5538 if (end == NULL || *end != '\0' ||
5539 (flow_xstat == ULONG_MAX && errno == ERANGE)) {
5541 "Invalid parameter passed to flow_xstat devarg.\n");
5545 if (BNXT_DEVARG_FLOW_XSTAT_INVALID(flow_xstat)) {
5547 "Invalid value passed to flow_xstat devarg.\n");
5551 bp->flags |= BNXT_FLAG_FLOW_XSTATS_EN;
5552 if (BNXT_FLOW_XSTATS_EN(bp))
5553 PMD_DRV_LOG(INFO, "flow_xstat feature enabled.\n");
5559 bnxt_parse_devarg_max_num_kflows(__rte_unused const char *key,
5560 const char *value, void *opaque_arg)
5562 struct bnxt *bp = opaque_arg;
5563 unsigned long max_num_kflows;
5566 if (!value || !opaque_arg) {
5568 "Invalid parameter passed to max_num_kflows devarg.\n");
5572 max_num_kflows = strtoul(value, &end, 10);
5573 if (end == NULL || *end != '\0' ||
5574 (max_num_kflows == ULONG_MAX && errno == ERANGE)) {
5576 "Invalid parameter passed to max_num_kflows devarg.\n");
5580 if (bnxt_devarg_max_num_kflow_invalid(max_num_kflows)) {
5582 "Invalid value passed to max_num_kflows devarg.\n");
5586 bp->max_num_kflows = max_num_kflows;
5587 if (bp->max_num_kflows)
5588 PMD_DRV_LOG(INFO, "max_num_kflows set as %ldK.\n",
5595 bnxt_parse_devarg_app_id(__rte_unused const char *key,
5596 const char *value, void *opaque_arg)
5598 struct bnxt *bp = opaque_arg;
5599 unsigned long app_id;
5602 if (!value || !opaque_arg) {
5604 "Invalid parameter passed to app-id "
5609 app_id = strtoul(value, &end, 10);
5610 if (end == NULL || *end != '\0' ||
5611 (app_id == ULONG_MAX && errno == ERANGE)) {
5613 "Invalid parameter passed to app_id "
5618 if (BNXT_DEVARG_APP_ID_INVALID(app_id)) {
5619 PMD_DRV_LOG(ERR, "Invalid app-id(%d) devargs.\n",
5624 bp->app_id = app_id;
5625 PMD_DRV_LOG(INFO, "app-id=%d feature enabled.\n", (uint16_t)app_id);
5631 bnxt_parse_devarg_rep_is_pf(__rte_unused const char *key,
5632 const char *value, void *opaque_arg)
5634 struct bnxt_representor *vfr_bp = opaque_arg;
5635 unsigned long rep_is_pf;
5638 if (!value || !opaque_arg) {
5640 "Invalid parameter passed to rep_is_pf devargs.\n");
5644 rep_is_pf = strtoul(value, &end, 10);
5645 if (end == NULL || *end != '\0' ||
5646 (rep_is_pf == ULONG_MAX && errno == ERANGE)) {
5648 "Invalid parameter passed to rep_is_pf devargs.\n");
5652 if (BNXT_DEVARG_REP_IS_PF_INVALID(rep_is_pf)) {
5654 "Invalid value passed to rep_is_pf devargs.\n");
5658 vfr_bp->flags |= rep_is_pf;
5659 if (BNXT_REP_PF(vfr_bp))
5660 PMD_DRV_LOG(INFO, "PF representor\n");
5662 PMD_DRV_LOG(INFO, "VF representor\n");
5668 bnxt_parse_devarg_rep_based_pf(__rte_unused const char *key,
5669 const char *value, void *opaque_arg)
5671 struct bnxt_representor *vfr_bp = opaque_arg;
5672 unsigned long rep_based_pf;
5675 if (!value || !opaque_arg) {
5677 "Invalid parameter passed to rep_based_pf "
5682 rep_based_pf = strtoul(value, &end, 10);
5683 if (end == NULL || *end != '\0' ||
5684 (rep_based_pf == ULONG_MAX && errno == ERANGE)) {
5686 "Invalid parameter passed to rep_based_pf "
5691 if (BNXT_DEVARG_REP_BASED_PF_INVALID(rep_based_pf)) {
5693 "Invalid value passed to rep_based_pf devargs.\n");
5697 vfr_bp->rep_based_pf = rep_based_pf;
5698 vfr_bp->flags |= BNXT_REP_BASED_PF_VALID;
5700 PMD_DRV_LOG(INFO, "rep-based-pf = %d\n", vfr_bp->rep_based_pf);
5706 bnxt_parse_devarg_rep_q_r2f(__rte_unused const char *key,
5707 const char *value, void *opaque_arg)
5709 struct bnxt_representor *vfr_bp = opaque_arg;
5710 unsigned long rep_q_r2f;
5713 if (!value || !opaque_arg) {
5715 "Invalid parameter passed to rep_q_r2f "
5720 rep_q_r2f = strtoul(value, &end, 10);
5721 if (end == NULL || *end != '\0' ||
5722 (rep_q_r2f == ULONG_MAX && errno == ERANGE)) {
5724 "Invalid parameter passed to rep_q_r2f "
5729 if (BNXT_DEVARG_REP_Q_R2F_INVALID(rep_q_r2f)) {
5731 "Invalid value passed to rep_q_r2f devargs.\n");
5735 vfr_bp->rep_q_r2f = rep_q_r2f;
5736 vfr_bp->flags |= BNXT_REP_Q_R2F_VALID;
5737 PMD_DRV_LOG(INFO, "rep-q-r2f = %d\n", vfr_bp->rep_q_r2f);
5743 bnxt_parse_devarg_rep_q_f2r(__rte_unused const char *key,
5744 const char *value, void *opaque_arg)
5746 struct bnxt_representor *vfr_bp = opaque_arg;
5747 unsigned long rep_q_f2r;
5750 if (!value || !opaque_arg) {
5752 "Invalid parameter passed to rep_q_f2r "
5757 rep_q_f2r = strtoul(value, &end, 10);
5758 if (end == NULL || *end != '\0' ||
5759 (rep_q_f2r == ULONG_MAX && errno == ERANGE)) {
5761 "Invalid parameter passed to rep_q_f2r "
5766 if (BNXT_DEVARG_REP_Q_F2R_INVALID(rep_q_f2r)) {
5768 "Invalid value passed to rep_q_f2r devargs.\n");
5772 vfr_bp->rep_q_f2r = rep_q_f2r;
5773 vfr_bp->flags |= BNXT_REP_Q_F2R_VALID;
5774 PMD_DRV_LOG(INFO, "rep-q-f2r = %d\n", vfr_bp->rep_q_f2r);
5780 bnxt_parse_devarg_rep_fc_r2f(__rte_unused const char *key,
5781 const char *value, void *opaque_arg)
5783 struct bnxt_representor *vfr_bp = opaque_arg;
5784 unsigned long rep_fc_r2f;
5787 if (!value || !opaque_arg) {
5789 "Invalid parameter passed to rep_fc_r2f "
5794 rep_fc_r2f = strtoul(value, &end, 10);
5795 if (end == NULL || *end != '\0' ||
5796 (rep_fc_r2f == ULONG_MAX && errno == ERANGE)) {
5798 "Invalid parameter passed to rep_fc_r2f "
5803 if (BNXT_DEVARG_REP_FC_R2F_INVALID(rep_fc_r2f)) {
5805 "Invalid value passed to rep_fc_r2f devargs.\n");
5809 vfr_bp->flags |= BNXT_REP_FC_R2F_VALID;
5810 vfr_bp->rep_fc_r2f = rep_fc_r2f;
5811 PMD_DRV_LOG(INFO, "rep-fc-r2f = %lu\n", rep_fc_r2f);
5817 bnxt_parse_devarg_rep_fc_f2r(__rte_unused const char *key,
5818 const char *value, void *opaque_arg)
5820 struct bnxt_representor *vfr_bp = opaque_arg;
5821 unsigned long rep_fc_f2r;
5824 if (!value || !opaque_arg) {
5826 "Invalid parameter passed to rep_fc_f2r "
5831 rep_fc_f2r = strtoul(value, &end, 10);
5832 if (end == NULL || *end != '\0' ||
5833 (rep_fc_f2r == ULONG_MAX && errno == ERANGE)) {
5835 "Invalid parameter passed to rep_fc_f2r "
5840 if (BNXT_DEVARG_REP_FC_F2R_INVALID(rep_fc_f2r)) {
5842 "Invalid value passed to rep_fc_f2r devargs.\n");
5846 vfr_bp->flags |= BNXT_REP_FC_F2R_VALID;
5847 vfr_bp->rep_fc_f2r = rep_fc_f2r;
5848 PMD_DRV_LOG(INFO, "rep-fc-f2r = %lu\n", rep_fc_f2r);
5854 bnxt_parse_dev_args(struct bnxt *bp, struct rte_devargs *devargs)
5856 struct rte_kvargs *kvlist;
5859 if (devargs == NULL)
5862 kvlist = rte_kvargs_parse(devargs->args, bnxt_dev_args);
5867 * Handler for "flow_xstat" devarg.
5868 * Invoked as for ex: "-a 0000:00:0d.0,flow_xstat=1"
5870 ret = rte_kvargs_process(kvlist, BNXT_DEVARG_FLOW_XSTAT,
5871 bnxt_parse_devarg_flow_xstat, bp);
5876 * Handler for "accum-stats" devarg.
5877 * Invoked as for ex: "-a 0000:00:0d.0,accum-stats=1"
5879 rte_kvargs_process(kvlist, BNXT_DEVARG_ACCUM_STATS,
5880 bnxt_parse_devarg_accum_stats, bp);
5882 * Handler for "max_num_kflows" devarg.
5883 * Invoked as for ex: "-a 000:00:0d.0,max_num_kflows=32"
5885 ret = rte_kvargs_process(kvlist, BNXT_DEVARG_MAX_NUM_KFLOWS,
5886 bnxt_parse_devarg_max_num_kflows, bp);
5892 * Handler for "app-id" devarg.
5893 * Invoked as for ex: "-a 000:00:0d.0,app-id=1"
5895 rte_kvargs_process(kvlist, BNXT_DEVARG_APP_ID,
5896 bnxt_parse_devarg_app_id, bp);
5898 rte_kvargs_free(kvlist);
5902 static int bnxt_alloc_switch_domain(struct bnxt *bp)
5906 if (BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp)) {
5907 rc = rte_eth_switch_domain_alloc(&bp->switch_domain_id);
5910 "Failed to alloc switch domain: %d\n", rc);
5913 "Switch domain allocated %d\n",
5914 bp->switch_domain_id);
5920 /* Allocate and initialize various fields in bnxt struct that
5921 * need to be allocated/destroyed only once in the lifetime of the driver
5923 static int bnxt_drv_init(struct rte_eth_dev *eth_dev)
5925 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
5926 struct bnxt *bp = eth_dev->data->dev_private;
5929 bp->flags &= ~BNXT_FLAG_RX_VECTOR_PKT_MODE;
5931 if (bnxt_vf_pciid(pci_dev->id.device_id))
5932 bp->flags |= BNXT_FLAG_VF;
5934 if (bnxt_p5_device(pci_dev->id.device_id))
5935 bp->flags |= BNXT_FLAG_CHIP_P5;
5937 if (pci_dev->id.device_id == BROADCOM_DEV_ID_58802 ||
5938 pci_dev->id.device_id == BROADCOM_DEV_ID_58804 ||
5939 pci_dev->id.device_id == BROADCOM_DEV_ID_58808 ||
5940 pci_dev->id.device_id == BROADCOM_DEV_ID_58802_VF)
5941 bp->flags |= BNXT_FLAG_STINGRAY;
5943 if (BNXT_TRUFLOW_EN(bp)) {
5944 /* extra mbuf field is required to store CFA code from mark */
5945 static const struct rte_mbuf_dynfield bnxt_cfa_code_dynfield_desc = {
5946 .name = RTE_PMD_BNXT_CFA_CODE_DYNFIELD_NAME,
5947 .size = sizeof(bnxt_cfa_code_dynfield_t),
5948 .align = __alignof__(bnxt_cfa_code_dynfield_t),
5950 bnxt_cfa_code_dynfield_offset =
5951 rte_mbuf_dynfield_register(&bnxt_cfa_code_dynfield_desc);
5952 if (bnxt_cfa_code_dynfield_offset < 0) {
5954 "Failed to register mbuf field for TruFlow mark\n");
5959 rc = bnxt_map_pci_bars(eth_dev);
5962 "Failed to initialize board rc: %x\n", rc);
5966 rc = bnxt_alloc_pf_info(bp);
5970 rc = bnxt_alloc_link_info(bp);
5974 rc = bnxt_alloc_parent_info(bp);
5978 rc = bnxt_alloc_hwrm_resources(bp);
5981 "Failed to allocate response buffer rc: %x\n", rc);
5984 rc = bnxt_alloc_leds_info(bp);
5988 rc = bnxt_alloc_cos_queues(bp);
5992 rc = bnxt_init_locks(bp);
5996 rc = bnxt_alloc_switch_domain(bp);
6004 bnxt_dev_init(struct rte_eth_dev *eth_dev, void *params __rte_unused)
6006 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
6007 static int version_printed;
6011 if (version_printed++ == 0)
6012 PMD_DRV_LOG(INFO, "%s\n", bnxt_version);
6014 eth_dev->dev_ops = &bnxt_dev_ops;
6015 eth_dev->rx_queue_count = bnxt_rx_queue_count_op;
6016 eth_dev->rx_descriptor_status = bnxt_rx_descriptor_status_op;
6017 eth_dev->tx_descriptor_status = bnxt_tx_descriptor_status_op;
6018 eth_dev->rx_pkt_burst = &bnxt_recv_pkts;
6019 eth_dev->tx_pkt_burst = &bnxt_xmit_pkts;
6022 * For secondary processes, we don't initialise any further
6023 * as primary has already done this work.
6025 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
6028 rte_eth_copy_pci_info(eth_dev, pci_dev);
6029 eth_dev->data->dev_flags |= RTE_ETH_DEV_AUTOFILL_QUEUE_XSTATS;
6031 bp = eth_dev->data->dev_private;
6033 /* Parse dev arguments passed on when starting the DPDK application. */
6034 rc = bnxt_parse_dev_args(bp, pci_dev->device.devargs);
6038 rc = bnxt_drv_init(eth_dev);
6042 rc = bnxt_init_resources(bp, false);
6046 rc = bnxt_alloc_stats_mem(bp);
6051 "Found %s device at mem %" PRIX64 ", node addr %pM\n",
6053 pci_dev->mem_resource[0].phys_addr,
6054 pci_dev->mem_resource[0].addr);
6059 bnxt_dev_uninit(eth_dev);
6064 static void bnxt_free_ctx_mem_buf(struct bnxt_ctx_mem_buf_info *ctx)
6073 ctx->dma = RTE_BAD_IOVA;
6074 ctx->ctx_id = BNXT_CTX_VAL_INVAL;
6077 static void bnxt_unregister_fc_ctx_mem(struct bnxt *bp)
6079 bnxt_hwrm_cfa_counter_cfg(bp, BNXT_DIR_RX,
6080 CFA_COUNTER_CFG_IN_COUNTER_TYPE_FC,
6081 bp->flow_stat->rx_fc_out_tbl.ctx_id,
6082 bp->flow_stat->max_fc,
6085 bnxt_hwrm_cfa_counter_cfg(bp, BNXT_DIR_TX,
6086 CFA_COUNTER_CFG_IN_COUNTER_TYPE_FC,
6087 bp->flow_stat->tx_fc_out_tbl.ctx_id,
6088 bp->flow_stat->max_fc,
6091 if (bp->flow_stat->rx_fc_in_tbl.ctx_id != BNXT_CTX_VAL_INVAL)
6092 bnxt_hwrm_ctx_unrgtr(bp, bp->flow_stat->rx_fc_in_tbl.ctx_id);
6093 bp->flow_stat->rx_fc_in_tbl.ctx_id = BNXT_CTX_VAL_INVAL;
6095 if (bp->flow_stat->rx_fc_out_tbl.ctx_id != BNXT_CTX_VAL_INVAL)
6096 bnxt_hwrm_ctx_unrgtr(bp, bp->flow_stat->rx_fc_out_tbl.ctx_id);
6097 bp->flow_stat->rx_fc_out_tbl.ctx_id = BNXT_CTX_VAL_INVAL;
6099 if (bp->flow_stat->tx_fc_in_tbl.ctx_id != BNXT_CTX_VAL_INVAL)
6100 bnxt_hwrm_ctx_unrgtr(bp, bp->flow_stat->tx_fc_in_tbl.ctx_id);
6101 bp->flow_stat->tx_fc_in_tbl.ctx_id = BNXT_CTX_VAL_INVAL;
6103 if (bp->flow_stat->tx_fc_out_tbl.ctx_id != BNXT_CTX_VAL_INVAL)
6104 bnxt_hwrm_ctx_unrgtr(bp, bp->flow_stat->tx_fc_out_tbl.ctx_id);
6105 bp->flow_stat->tx_fc_out_tbl.ctx_id = BNXT_CTX_VAL_INVAL;
6108 static void bnxt_uninit_fc_ctx_mem(struct bnxt *bp)
6110 bnxt_unregister_fc_ctx_mem(bp);
6112 bnxt_free_ctx_mem_buf(&bp->flow_stat->rx_fc_in_tbl);
6113 bnxt_free_ctx_mem_buf(&bp->flow_stat->rx_fc_out_tbl);
6114 bnxt_free_ctx_mem_buf(&bp->flow_stat->tx_fc_in_tbl);
6115 bnxt_free_ctx_mem_buf(&bp->flow_stat->tx_fc_out_tbl);
6118 static void bnxt_uninit_ctx_mem(struct bnxt *bp)
6120 if (BNXT_FLOW_XSTATS_EN(bp))
6121 bnxt_uninit_fc_ctx_mem(bp);
6125 bnxt_free_error_recovery_info(struct bnxt *bp)
6127 rte_free(bp->recovery_info);
6128 bp->recovery_info = NULL;
6129 bp->fw_cap &= ~BNXT_FW_CAP_ERROR_RECOVERY;
6133 bnxt_uninit_resources(struct bnxt *bp, bool reconfig_dev)
6138 bnxt_free_mem(bp, reconfig_dev);
6140 bnxt_hwrm_func_buf_unrgtr(bp);
6141 if (bp->pf != NULL) {
6142 rte_free(bp->pf->vf_req_buf);
6143 bp->pf->vf_req_buf = NULL;
6146 rc = bnxt_hwrm_func_driver_unregister(bp, 0);
6147 bp->flags &= ~BNXT_FLAG_REGISTERED;
6148 bnxt_free_ctx_mem(bp);
6149 if (!reconfig_dev) {
6150 bnxt_free_hwrm_resources(bp);
6151 bnxt_free_error_recovery_info(bp);
6154 bnxt_uninit_ctx_mem(bp);
6156 bnxt_free_flow_stats_info(bp);
6157 if (bp->rep_info != NULL)
6158 bnxt_free_switch_domain(bp);
6159 bnxt_free_rep_info(bp);
6160 rte_free(bp->ptp_cfg);
6166 bnxt_dev_uninit(struct rte_eth_dev *eth_dev)
6168 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
6171 PMD_DRV_LOG(DEBUG, "Calling Device uninit\n");
6173 if (eth_dev->state != RTE_ETH_DEV_UNUSED)
6174 bnxt_dev_close_op(eth_dev);
6179 static int bnxt_pci_remove_dev_with_reps(struct rte_eth_dev *eth_dev)
6181 struct bnxt *bp = eth_dev->data->dev_private;
6182 struct rte_eth_dev *vf_rep_eth_dev;
6188 for (i = 0; i < bp->num_reps; i++) {
6189 vf_rep_eth_dev = bp->rep_info[i].vfr_eth_dev;
6190 if (!vf_rep_eth_dev)
6192 PMD_DRV_LOG(DEBUG, "BNXT Port:%d VFR pci remove\n",
6193 vf_rep_eth_dev->data->port_id);
6194 rte_eth_dev_destroy(vf_rep_eth_dev, bnxt_representor_uninit);
6196 PMD_DRV_LOG(DEBUG, "BNXT Port:%d pci remove\n",
6197 eth_dev->data->port_id);
6198 ret = rte_eth_dev_destroy(eth_dev, bnxt_dev_uninit);
6203 static void bnxt_free_rep_info(struct bnxt *bp)
6205 rte_free(bp->rep_info);
6206 bp->rep_info = NULL;
6207 rte_free(bp->cfa_code_map);
6208 bp->cfa_code_map = NULL;
6211 static int bnxt_init_rep_info(struct bnxt *bp)
6218 bp->rep_info = rte_zmalloc("bnxt_rep_info",
6219 sizeof(bp->rep_info[0]) * BNXT_MAX_VF_REPS,
6221 if (!bp->rep_info) {
6222 PMD_DRV_LOG(ERR, "Failed to alloc memory for rep info\n");
6225 bp->cfa_code_map = rte_zmalloc("bnxt_cfa_code_map",
6226 sizeof(*bp->cfa_code_map) *
6227 BNXT_MAX_CFA_CODE, 0);
6228 if (!bp->cfa_code_map) {
6229 PMD_DRV_LOG(ERR, "Failed to alloc memory for cfa_code_map\n");
6230 bnxt_free_rep_info(bp);
6234 for (i = 0; i < BNXT_MAX_CFA_CODE; i++)
6235 bp->cfa_code_map[i] = BNXT_VF_IDX_INVALID;
6237 rc = pthread_mutex_init(&bp->rep_info->vfr_lock, NULL);
6239 PMD_DRV_LOG(ERR, "Unable to initialize vfr_lock\n");
6240 bnxt_free_rep_info(bp);
6244 rc = pthread_mutex_init(&bp->rep_info->vfr_start_lock, NULL);
6246 PMD_DRV_LOG(ERR, "Unable to initialize vfr_start_lock\n");
6247 bnxt_free_rep_info(bp);
6254 static int bnxt_rep_port_probe(struct rte_pci_device *pci_dev,
6255 struct rte_eth_devargs *eth_da,
6256 struct rte_eth_dev *backing_eth_dev,
6257 const char *dev_args)
6259 struct rte_eth_dev *vf_rep_eth_dev;
6260 char name[RTE_ETH_NAME_MAX_LEN];
6261 struct bnxt *backing_bp;
6264 struct rte_kvargs *kvlist = NULL;
6266 if (eth_da->type == RTE_ETH_REPRESENTOR_NONE)
6268 if (eth_da->type != RTE_ETH_REPRESENTOR_VF) {
6269 PMD_DRV_LOG(ERR, "unsupported representor type %d\n",
6273 num_rep = eth_da->nb_representor_ports;
6274 if (num_rep > BNXT_MAX_VF_REPS) {
6275 PMD_DRV_LOG(ERR, "nb_representor_ports = %d > %d MAX VF REPS\n",
6276 num_rep, BNXT_MAX_VF_REPS);
6280 if (num_rep >= RTE_MAX_ETHPORTS) {
6282 "nb_representor_ports = %d > %d MAX ETHPORTS\n",
6283 num_rep, RTE_MAX_ETHPORTS);
6287 backing_bp = backing_eth_dev->data->dev_private;
6289 if (!(BNXT_PF(backing_bp) || BNXT_VF_IS_TRUSTED(backing_bp))) {
6291 "Not a PF or trusted VF. No Representor support\n");
6292 /* Returning an error is not an option.
6293 * Applications are not handling this correctly
6298 if (bnxt_init_rep_info(backing_bp))
6301 for (i = 0; i < num_rep; i++) {
6302 struct bnxt_representor representor = {
6303 .vf_id = eth_da->representor_ports[i],
6304 .switch_domain_id = backing_bp->switch_domain_id,
6305 .parent_dev = backing_eth_dev
6308 if (representor.vf_id >= BNXT_MAX_VF_REPS) {
6309 PMD_DRV_LOG(ERR, "VF-Rep id %d >= %d MAX VF ID\n",
6310 representor.vf_id, BNXT_MAX_VF_REPS);
6314 /* representor port net_bdf_port */
6315 snprintf(name, sizeof(name), "net_%s_representor_%d",
6316 pci_dev->device.name, eth_da->representor_ports[i]);
6318 kvlist = rte_kvargs_parse(dev_args, bnxt_dev_args);
6321 * Handler for "rep_is_pf" devarg.
6322 * Invoked as for ex: "-a 000:00:0d.0,
6323 * rep-based-pf=<pf index> rep-is-pf=<VF=0 or PF=1>"
6325 ret = rte_kvargs_process(kvlist, BNXT_DEVARG_REP_IS_PF,
6326 bnxt_parse_devarg_rep_is_pf,
6327 (void *)&representor);
6333 * Handler for "rep_based_pf" devarg.
6334 * Invoked as for ex: "-a 000:00:0d.0,
6335 * rep-based-pf=<pf index> rep-is-pf=<VF=0 or PF=1>"
6337 ret = rte_kvargs_process(kvlist,
6338 BNXT_DEVARG_REP_BASED_PF,
6339 bnxt_parse_devarg_rep_based_pf,
6340 (void *)&representor);
6346 * Handler for "rep_based_pf" devarg.
6347 * Invoked as for ex: "-a 000:00:0d.0,
6348 * rep-based-pf=<pf index> rep-is-pf=<VF=0 or PF=1>"
6350 ret = rte_kvargs_process(kvlist, BNXT_DEVARG_REP_Q_R2F,
6351 bnxt_parse_devarg_rep_q_r2f,
6352 (void *)&representor);
6358 * Handler for "rep_based_pf" devarg.
6359 * Invoked as for ex: "-a 000:00:0d.0,
6360 * rep-based-pf=<pf index> rep-is-pf=<VF=0 or PF=1>"
6362 ret = rte_kvargs_process(kvlist, BNXT_DEVARG_REP_Q_F2R,
6363 bnxt_parse_devarg_rep_q_f2r,
6364 (void *)&representor);
6370 * Handler for "rep_based_pf" devarg.
6371 * Invoked as for ex: "-a 000:00:0d.0,
6372 * rep-based-pf=<pf index> rep-is-pf=<VF=0 or PF=1>"
6374 ret = rte_kvargs_process(kvlist, BNXT_DEVARG_REP_FC_R2F,
6375 bnxt_parse_devarg_rep_fc_r2f,
6376 (void *)&representor);
6382 * Handler for "rep_based_pf" devarg.
6383 * Invoked as for ex: "-a 000:00:0d.0,
6384 * rep-based-pf=<pf index> rep-is-pf=<VF=0 or PF=1>"
6386 ret = rte_kvargs_process(kvlist, BNXT_DEVARG_REP_FC_F2R,
6387 bnxt_parse_devarg_rep_fc_f2r,
6388 (void *)&representor);
6395 ret = rte_eth_dev_create(&pci_dev->device, name,
6396 sizeof(struct bnxt_representor),
6398 bnxt_representor_init,
6401 PMD_DRV_LOG(ERR, "failed to create bnxt vf "
6402 "representor %s.", name);
6406 vf_rep_eth_dev = rte_eth_dev_allocated(name);
6407 if (!vf_rep_eth_dev) {
6408 PMD_DRV_LOG(ERR, "Failed to find the eth_dev"
6409 " for VF-Rep: %s.", name);
6414 PMD_DRV_LOG(DEBUG, "BNXT Port:%d VFR pci probe\n",
6415 backing_eth_dev->data->port_id);
6416 backing_bp->rep_info[representor.vf_id].vfr_eth_dev =
6418 backing_bp->num_reps++;
6422 rte_kvargs_free(kvlist);
6426 /* If num_rep > 1, then rollback already created
6427 * ports, since we'll be failing the probe anyway
6430 bnxt_pci_remove_dev_with_reps(backing_eth_dev);
6432 rte_kvargs_free(kvlist);
6437 static int bnxt_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
6438 struct rte_pci_device *pci_dev)
6440 struct rte_eth_devargs eth_da = { .nb_representor_ports = 0 };
6441 struct rte_eth_dev *backing_eth_dev;
6445 if (pci_dev->device.devargs) {
6446 ret = rte_eth_devargs_parse(pci_dev->device.devargs->args,
6452 num_rep = eth_da.nb_representor_ports;
6453 PMD_DRV_LOG(DEBUG, "nb_representor_ports = %d\n",
6456 /* We could come here after first level of probe is already invoked
6457 * as part of an application bringup(OVS-DPDK vswitchd), so first check
6458 * for already allocated eth_dev for the backing device (PF/Trusted VF)
6460 backing_eth_dev = rte_eth_dev_allocated(pci_dev->device.name);
6461 if (backing_eth_dev == NULL) {
6462 ret = rte_eth_dev_create(&pci_dev->device, pci_dev->device.name,
6463 sizeof(struct bnxt),
6464 eth_dev_pci_specific_init, pci_dev,
6465 bnxt_dev_init, NULL);
6467 if (ret || !num_rep)
6470 backing_eth_dev = rte_eth_dev_allocated(pci_dev->device.name);
6472 PMD_DRV_LOG(DEBUG, "BNXT Port:%d pci probe\n",
6473 backing_eth_dev->data->port_id);
6478 /* probe representor ports now */
6479 ret = bnxt_rep_port_probe(pci_dev, ð_da, backing_eth_dev,
6480 pci_dev->device.devargs->args);
6485 static int bnxt_pci_remove(struct rte_pci_device *pci_dev)
6487 struct rte_eth_dev *eth_dev;
6489 eth_dev = rte_eth_dev_allocated(pci_dev->device.name);
6491 return 0; /* Invoked typically only by OVS-DPDK, by the
6492 * time it comes here the eth_dev is already
6493 * deleted by rte_eth_dev_close(), so returning
6494 * +ve value will at least help in proper cleanup
6497 PMD_DRV_LOG(DEBUG, "BNXT Port:%d pci remove\n", eth_dev->data->port_id);
6498 if (rte_eal_process_type() == RTE_PROC_PRIMARY) {
6499 if (eth_dev->data->dev_flags & RTE_ETH_DEV_REPRESENTOR)
6500 return rte_eth_dev_destroy(eth_dev,
6501 bnxt_representor_uninit);
6503 return rte_eth_dev_destroy(eth_dev,
6506 return rte_eth_dev_pci_generic_remove(pci_dev, NULL);
6510 static struct rte_pci_driver bnxt_rte_pmd = {
6511 .id_table = bnxt_pci_id_map,
6512 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC |
6513 RTE_PCI_DRV_INTR_RMV |
6514 RTE_PCI_DRV_PROBE_AGAIN, /* Needed in case of VF-REPs
6517 .probe = bnxt_pci_probe,
6518 .remove = bnxt_pci_remove,
6522 is_device_supported(struct rte_eth_dev *dev, struct rte_pci_driver *drv)
6524 if (strcmp(dev->device->driver->name, drv->driver.name))
6530 bool is_bnxt_supported(struct rte_eth_dev *dev)
6532 return is_device_supported(dev, &bnxt_rte_pmd);
6535 RTE_LOG_REGISTER_SUFFIX(bnxt_logtype_driver, driver, NOTICE);
6536 RTE_PMD_REGISTER_PCI(net_bnxt, bnxt_rte_pmd);
6537 RTE_PMD_REGISTER_PCI_TABLE(net_bnxt, bnxt_pci_id_map);
6538 RTE_PMD_REGISTER_KMOD_DEP(net_bnxt, "* igb_uio | uio_pci_generic | vfio-pci");