drivers/net/bnxt/bnxt_ethdev.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2014-2018 Broadcom
   3  * All rights reserved.
   4  */
   5
   6 #include <inttypes.h>
   7 #include <stdbool.h>
   8
   9 #include <rte_dev.h>
  10 #include <rte_ethdev_driver.h>
  11 #include <rte_ethdev_pci.h>
  12 #include <rte_malloc.h>
  13 #include <rte_cycles.h>
  14 #include <rte_alarm.h>
  15 #include <rte_kvargs.h>
  16
  17 #include "bnxt.h"
  18 #include "bnxt_filter.h"
  19 #include "bnxt_hwrm.h"
  20 #include "bnxt_irq.h"
  21 #include "bnxt_reps.h"
  22 #include "bnxt_ring.h"
  23 #include "bnxt_rxq.h"
  24 #include "bnxt_rxr.h"
  25 #include "bnxt_stats.h"
  26 #include "bnxt_txq.h"
  27 #include "bnxt_txr.h"
  28 #include "bnxt_vnic.h"
  29 #include "hsi_struct_def_dpdk.h"
  30 #include "bnxt_nvm_defs.h"
  31 #include "bnxt_tf_common.h"
  32 #include "ulp_flow_db.h"
  33
  34 #define DRV_MODULE_NAME         "bnxt"
  35 static const char bnxt_version[] =
  36         "Broadcom NetXtreme driver " DRV_MODULE_NAME;
  37
  38 /*
  39  * The set of PCI devices this driver supports
  40  */
  41 static const struct rte_pci_id bnxt_pci_id_map[] = {
  42         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM,
  43                          BROADCOM_DEV_ID_STRATUS_NIC_VF1) },
  44         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM,
  45                          BROADCOM_DEV_ID_STRATUS_NIC_VF2) },
  46         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_STRATUS_NIC) },
  47         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414_VF) },
  48         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57301) },
  49         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57302) },
  50         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57304_PF) },
  51         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57304_VF) },
  52         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_NS2) },
  53         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57402) },
  54         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57404) },
  55         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57406_PF) },
  56         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57406_VF) },
  57         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57402_MF) },
  58         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57407_RJ45) },
  59         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57404_MF) },
  60         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57406_MF) },
  61         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57407_SFP) },
  62         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57407_MF) },
  63         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_5741X_VF) },
  64         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_5731X_VF) },
  65         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57314) },
  66         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_MF) },
  67         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57311) },
  68         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57312) },
  69         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57412) },
  70         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414) },
  71         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_RJ45) },
  72         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_RJ45) },
  73         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57412_MF) },
  74         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57317_RJ45) },
  75         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_SFP) },
  76         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_SFP) },
  77         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57317_SFP) },
  78         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414_MF) },
  79         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_MF) },
  80         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58802) },
  81         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58804) },
  82         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58808) },
  83         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58802_VF) },
  84         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57508) },
  85         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57504) },
  86         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57502) },
  87         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57500_VF1) },
  88         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57500_VF2) },
  89         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57508_MF1) },
  90         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57504_MF1) },
  91         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57502_MF1) },
  92         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57508_MF2) },
  93         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57504_MF2) },
  94         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57502_MF2) },
  95         { .vendor_id = 0, /* sentinel */ },
  96 };
  97
  98 #define BNXT_DEVARG_TRUFLOW     "host-based-truflow"
  99 #define BNXT_DEVARG_FLOW_XSTAT  "flow-xstat"
 100 #define BNXT_DEVARG_MAX_NUM_KFLOWS  "max-num-kflows"
 101 #define BNXT_DEVARG_REPRESENTOR "representor"
 102
 103 static const char *const bnxt_dev_args[] = {
 104         BNXT_DEVARG_REPRESENTOR,
 105         BNXT_DEVARG_TRUFLOW,
 106         BNXT_DEVARG_FLOW_XSTAT,
 107         BNXT_DEVARG_MAX_NUM_KFLOWS,
 108         NULL
 109 };
 110
 111 /*
 112  * truflow == false to disable the feature
 113  * truflow == true to enable the feature
 114  */
 115 #define BNXT_DEVARG_TRUFLOW_INVALID(truflow)    ((truflow) > 1)
 116
 117 /*
 118  * flow_xstat == false to disable the feature
 119  * flow_xstat == true to enable the feature
 120  */
 121 #define BNXT_DEVARG_FLOW_XSTAT_INVALID(flow_xstat)      ((flow_xstat) > 1)
 122
 123 /*
 124  * max_num_kflows must be >= 32
 125  * and must be a power-of-2 supported value
 126  * return: 1 -> invalid
 127  *         0 -> valid
 128  */
 129 static int bnxt_devarg_max_num_kflow_invalid(uint16_t max_num_kflows)
 130 {
 131         if (max_num_kflows < 32 || !rte_is_power_of_2(max_num_kflows))
 132                 return 1;
 133         return 0;
 134 }
 135
 136 static int bnxt_vlan_offload_set_op(struct rte_eth_dev *dev, int mask);
 137 static int bnxt_dev_uninit(struct rte_eth_dev *eth_dev);
 138 static int bnxt_init_resources(struct bnxt *bp, bool reconfig_dev);
 139 static int bnxt_uninit_resources(struct bnxt *bp, bool reconfig_dev);
 140 static void bnxt_cancel_fw_health_check(struct bnxt *bp);
 141 static int bnxt_restore_vlan_filters(struct bnxt *bp);
 142 static void bnxt_dev_recover(void *arg);
 143 static void bnxt_free_error_recovery_info(struct bnxt *bp);
 144 static void bnxt_free_rep_info(struct bnxt *bp);
 145
 146 int is_bnxt_in_error(struct bnxt *bp)
 147 {
 148         if (bp->flags & BNXT_FLAG_FATAL_ERROR)
 149                 return -EIO;
 150         if (bp->flags & BNXT_FLAG_FW_RESET)
 151                 return -EBUSY;
 152
 153         return 0;
 154 }
 155
 156 /***********************/
 157
 158 /*
 159  * High level utility functions
 160  */
 161
 162 static uint16_t bnxt_rss_ctxts(const struct bnxt *bp)
 163 {
 164         if (!BNXT_CHIP_THOR(bp))
 165                 return 1;
 166
 167         return RTE_ALIGN_MUL_CEIL(bp->rx_nr_rings,
 168                                   BNXT_RSS_ENTRIES_PER_CTX_THOR) /
 169                                     BNXT_RSS_ENTRIES_PER_CTX_THOR;
 170 }
 171
 172 uint16_t bnxt_rss_hash_tbl_size(const struct bnxt *bp)
 173 {
 174         if (!BNXT_CHIP_THOR(bp))
 175                 return HW_HASH_INDEX_SIZE;
 176
 177         return bnxt_rss_ctxts(bp) * BNXT_RSS_ENTRIES_PER_CTX_THOR;
 178 }
 179
 180 static void bnxt_free_parent_info(struct bnxt *bp)
 181 {
 182         rte_free(bp->parent);
 183 }
 184
 185 static void bnxt_free_pf_info(struct bnxt *bp)
 186 {
 187         rte_free(bp->pf);
 188 }
 189
 190 static void bnxt_free_link_info(struct bnxt *bp)
 191 {
 192         rte_free(bp->link_info);
 193 }
 194
 195 static void bnxt_free_leds_info(struct bnxt *bp)
 196 {
 197         if (BNXT_VF(bp))
 198                 return;
 199
 200         rte_free(bp->leds);
 201         bp->leds = NULL;
 202 }
 203
 204 static void bnxt_free_flow_stats_info(struct bnxt *bp)
 205 {
 206         rte_free(bp->flow_stat);
 207         bp->flow_stat = NULL;
 208 }
 209
 210 static void bnxt_free_cos_queues(struct bnxt *bp)
 211 {
 212         rte_free(bp->rx_cos_queue);
 213         rte_free(bp->tx_cos_queue);
 214 }
 215
 216 static void bnxt_free_mem(struct bnxt *bp, bool reconfig)
 217 {
 218         bnxt_free_filter_mem(bp);
 219         bnxt_free_vnic_attributes(bp);
 220         bnxt_free_vnic_mem(bp);
 221
 222         /* tx/rx rings are configured as part of *_queue_setup callbacks.
 223          * If the number of rings change across fw update,
 224          * we don't have much choice except to warn the user.
 225          */
 226         if (!reconfig) {
 227                 bnxt_free_stats(bp);
 228                 bnxt_free_tx_rings(bp);
 229                 bnxt_free_rx_rings(bp);
 230         }
 231         bnxt_free_async_cp_ring(bp);
 232         bnxt_free_rxtx_nq_ring(bp);
 233
 234         rte_free(bp->grp_info);
 235         bp->grp_info = NULL;
 236 }
 237
 238 static int bnxt_alloc_parent_info(struct bnxt *bp)
 239 {
 240         bp->parent = rte_zmalloc("bnxt_parent_info",
 241                                  sizeof(struct bnxt_parent_info), 0);
 242         if (bp->parent == NULL)
 243                 return -ENOMEM;
 244
 245         return 0;
 246 }
 247
 248 static int bnxt_alloc_pf_info(struct bnxt *bp)
 249 {
 250         bp->pf = rte_zmalloc("bnxt_pf_info", sizeof(struct bnxt_pf_info), 0);
 251         if (bp->pf == NULL)
 252                 return -ENOMEM;
 253
 254         return 0;
 255 }
 256
 257 static int bnxt_alloc_link_info(struct bnxt *bp)
 258 {
 259         bp->link_info =
 260                 rte_zmalloc("bnxt_link_info", sizeof(struct bnxt_link_info), 0);
 261         if (bp->link_info == NULL)
 262                 return -ENOMEM;
 263
 264         return 0;
 265 }
 266
 267 static int bnxt_alloc_leds_info(struct bnxt *bp)
 268 {
 269         if (BNXT_VF(bp))
 270                 return 0;
 271
 272         bp->leds = rte_zmalloc("bnxt_leds",
 273                                BNXT_MAX_LED * sizeof(struct bnxt_led_info),
 274                                0);
 275         if (bp->leds == NULL)
 276                 return -ENOMEM;
 277
 278         return 0;
 279 }
 280
 281 static int bnxt_alloc_cos_queues(struct bnxt *bp)
 282 {
 283         bp->rx_cos_queue =
 284                 rte_zmalloc("bnxt_rx_cosq",
 285                             BNXT_COS_QUEUE_COUNT *
 286                             sizeof(struct bnxt_cos_queue_info),
 287                             0);
 288         if (bp->rx_cos_queue == NULL)
 289                 return -ENOMEM;
 290
 291         bp->tx_cos_queue =
 292                 rte_zmalloc("bnxt_tx_cosq",
 293                             BNXT_COS_QUEUE_COUNT *
 294                             sizeof(struct bnxt_cos_queue_info),
 295                             0);
 296         if (bp->tx_cos_queue == NULL)
 297                 return -ENOMEM;
 298
 299         return 0;
 300 }
 301
 302 static int bnxt_alloc_flow_stats_info(struct bnxt *bp)
 303 {
 304         bp->flow_stat = rte_zmalloc("bnxt_flow_xstat",
 305                                     sizeof(struct bnxt_flow_stat_info), 0);
 306         if (bp->flow_stat == NULL)
 307                 return -ENOMEM;
 308
 309         return 0;
 310 }
 311
 312 static int bnxt_alloc_mem(struct bnxt *bp, bool reconfig)
 313 {
 314         int rc;
 315
 316         rc = bnxt_alloc_ring_grps(bp);
 317         if (rc)
 318                 goto alloc_mem_err;
 319
 320         rc = bnxt_alloc_async_ring_struct(bp);
 321         if (rc)
 322                 goto alloc_mem_err;
 323
 324         rc = bnxt_alloc_vnic_mem(bp);
 325         if (rc)
 326                 goto alloc_mem_err;
 327
 328         rc = bnxt_alloc_vnic_attributes(bp);
 329         if (rc)
 330                 goto alloc_mem_err;
 331
 332         rc = bnxt_alloc_filter_mem(bp);
 333         if (rc)
 334                 goto alloc_mem_err;
 335
 336         rc = bnxt_alloc_async_cp_ring(bp);
 337         if (rc)
 338                 goto alloc_mem_err;
 339
 340         rc = bnxt_alloc_rxtx_nq_ring(bp);
 341         if (rc)
 342                 goto alloc_mem_err;
 343
 344         if (BNXT_FLOW_XSTATS_EN(bp)) {
 345                 rc = bnxt_alloc_flow_stats_info(bp);
 346                 if (rc)
 347                         goto alloc_mem_err;
 348         }
 349
 350         return 0;
 351
 352 alloc_mem_err:
 353         bnxt_free_mem(bp, reconfig);
 354         return rc;
 355 }
 356
 357 static int bnxt_setup_one_vnic(struct bnxt *bp, uint16_t vnic_id)
 358 {
 359         struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
 360         struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id];
 361         uint64_t rx_offloads = dev_conf->rxmode.offloads;
 362         struct bnxt_rx_queue *rxq;
 363         unsigned int j;
 364         int rc;
 365
 366         rc = bnxt_vnic_grp_alloc(bp, vnic);
 367         if (rc)
 368                 goto err_out;
 369
 370         PMD_DRV_LOG(DEBUG, "vnic[%d] = %p vnic->fw_grp_ids = %p\n",
 371                     vnic_id, vnic, vnic->fw_grp_ids);
 372
 373         rc = bnxt_hwrm_vnic_alloc(bp, vnic);
 374         if (rc)
 375                 goto err_out;
 376
 377         /* Alloc RSS context only if RSS mode is enabled */
 378         if (dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS) {
 379                 int j, nr_ctxs = bnxt_rss_ctxts(bp);
 380
 381                 rc = 0;
 382                 for (j = 0; j < nr_ctxs; j++) {
 383                         rc = bnxt_hwrm_vnic_ctx_alloc(bp, vnic, j);
 384                         if (rc)
 385                                 break;
 386                 }
 387                 if (rc) {
 388                         PMD_DRV_LOG(ERR,
 389                                     "HWRM vnic %d ctx %d alloc failure rc: %x\n",
 390                                     vnic_id, j, rc);
 391                         goto err_out;
 392                 }
 393                 vnic->num_lb_ctxts = nr_ctxs;
 394         }
 395
 396         /*
 397          * Firmware sets pf pair in default vnic cfg. If the VLAN strip
 398          * setting is not available at this time, it will not be
 399          * configured correctly in the CFA.
 400          */
 401         if (rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
 402                 vnic->vlan_strip = true;
 403         else
 404                 vnic->vlan_strip = false;
 405
 406         rc = bnxt_hwrm_vnic_cfg(bp, vnic);
 407         if (rc)
 408                 goto err_out;
 409
 410         rc = bnxt_set_hwrm_vnic_filters(bp, vnic);
 411         if (rc)
 412                 goto err_out;
 413
 414         for (j = 0; j < bp->rx_num_qs_per_vnic; j++) {
 415                 rxq = bp->eth_dev->data->rx_queues[j];
 416
 417                 PMD_DRV_LOG(DEBUG,
 418                             "rxq[%d]->vnic=%p vnic->fw_grp_ids=%p\n",
 419                             j, rxq->vnic, rxq->vnic->fw_grp_ids);
 420
 421                 if (BNXT_HAS_RING_GRPS(bp) && rxq->rx_deferred_start)
 422                         rxq->vnic->fw_grp_ids[j] = INVALID_HW_RING_ID;
 423                 else
 424                         vnic->rx_queue_cnt++;
 425         }
 426
 427         PMD_DRV_LOG(DEBUG, "vnic->rx_queue_cnt = %d\n", vnic->rx_queue_cnt);
 428
 429         rc = bnxt_vnic_rss_configure(bp, vnic);
 430         if (rc)
 431                 goto err_out;
 432
 433         bnxt_hwrm_vnic_plcmode_cfg(bp, vnic);
 434
 435         if (rx_offloads & DEV_RX_OFFLOAD_TCP_LRO)
 436                 bnxt_hwrm_vnic_tpa_cfg(bp, vnic, 1);
 437         else
 438                 bnxt_hwrm_vnic_tpa_cfg(bp, vnic, 0);
 439
 440         return 0;
 441 err_out:
 442         PMD_DRV_LOG(ERR, "HWRM vnic %d cfg failure rc: %x\n",
 443                     vnic_id, rc);
 444         return rc;
 445 }
 446
 447 static int bnxt_register_fc_ctx_mem(struct bnxt *bp)
 448 {
 449         int rc = 0;
 450
 451         rc = bnxt_hwrm_ctx_rgtr(bp, bp->flow_stat->rx_fc_in_tbl.dma,
 452                                 &bp->flow_stat->rx_fc_in_tbl.ctx_id);
 453         if (rc)
 454                 return rc;
 455
 456         PMD_DRV_LOG(DEBUG,
 457                     "rx_fc_in_tbl.va = %p rx_fc_in_tbl.dma = %p"
 458                     " rx_fc_in_tbl.ctx_id = %d\n",
 459                     bp->flow_stat->rx_fc_in_tbl.va,
 460                     (void *)((uintptr_t)bp->flow_stat->rx_fc_in_tbl.dma),
 461                     bp->flow_stat->rx_fc_in_tbl.ctx_id);
 462
 463         rc = bnxt_hwrm_ctx_rgtr(bp, bp->flow_stat->rx_fc_out_tbl.dma,
 464                                 &bp->flow_stat->rx_fc_out_tbl.ctx_id);
 465         if (rc)
 466                 return rc;
 467
 468         PMD_DRV_LOG(DEBUG,
 469                     "rx_fc_out_tbl.va = %p rx_fc_out_tbl.dma = %p"
 470                     " rx_fc_out_tbl.ctx_id = %d\n",
 471                     bp->flow_stat->rx_fc_out_tbl.va,
 472                     (void *)((uintptr_t)bp->flow_stat->rx_fc_out_tbl.dma),
 473                     bp->flow_stat->rx_fc_out_tbl.ctx_id);
 474
 475         rc = bnxt_hwrm_ctx_rgtr(bp, bp->flow_stat->tx_fc_in_tbl.dma,
 476                                 &bp->flow_stat->tx_fc_in_tbl.ctx_id);
 477         if (rc)
 478                 return rc;
 479
 480         PMD_DRV_LOG(DEBUG,
 481                     "tx_fc_in_tbl.va = %p tx_fc_in_tbl.dma = %p"
 482                     " tx_fc_in_tbl.ctx_id = %d\n",
 483                     bp->flow_stat->tx_fc_in_tbl.va,
 484                     (void *)((uintptr_t)bp->flow_stat->tx_fc_in_tbl.dma),
 485                     bp->flow_stat->tx_fc_in_tbl.ctx_id);
 486
 487         rc = bnxt_hwrm_ctx_rgtr(bp, bp->flow_stat->tx_fc_out_tbl.dma,
 488                                 &bp->flow_stat->tx_fc_out_tbl.ctx_id);
 489         if (rc)
 490                 return rc;
 491
 492         PMD_DRV_LOG(DEBUG,
 493                     "tx_fc_out_tbl.va = %p tx_fc_out_tbl.dma = %p"
 494                     " tx_fc_out_tbl.ctx_id = %d\n",
 495                     bp->flow_stat->tx_fc_out_tbl.va,
 496                     (void *)((uintptr_t)bp->flow_stat->tx_fc_out_tbl.dma),
 497                     bp->flow_stat->tx_fc_out_tbl.ctx_id);
 498
 499         memset(bp->flow_stat->rx_fc_out_tbl.va,
 500                0,
 501                bp->flow_stat->rx_fc_out_tbl.size);
 502         rc = bnxt_hwrm_cfa_counter_cfg(bp, BNXT_DIR_RX,
 503                                        CFA_COUNTER_CFG_IN_COUNTER_TYPE_FC,
 504                                        bp->flow_stat->rx_fc_out_tbl.ctx_id,
 505                                        bp->flow_stat->max_fc,
 506                                        true);
 507         if (rc)
 508                 return rc;
 509
 510         memset(bp->flow_stat->tx_fc_out_tbl.va,
 511                0,
 512                bp->flow_stat->tx_fc_out_tbl.size);
 513         rc = bnxt_hwrm_cfa_counter_cfg(bp, BNXT_DIR_TX,
 514                                        CFA_COUNTER_CFG_IN_COUNTER_TYPE_FC,
 515                                        bp->flow_stat->tx_fc_out_tbl.ctx_id,
 516                                        bp->flow_stat->max_fc,
 517                                        true);
 518
 519         return rc;
 520 }
 521
 522 static int bnxt_alloc_ctx_mem_buf(char *type, size_t size,
 523                                   struct bnxt_ctx_mem_buf_info *ctx)
 524 {
 525         if (!ctx)
 526                 return -EINVAL;
 527
 528         ctx->va = rte_zmalloc(type, size, 0);
 529         if (ctx->va == NULL)
 530                 return -ENOMEM;
 531         rte_mem_lock_page(ctx->va);
 532         ctx->size = size;
 533         ctx->dma = rte_mem_virt2iova(ctx->va);
 534         if (ctx->dma == RTE_BAD_IOVA)
 535                 return -ENOMEM;
 536
 537         return 0;
 538 }
 539
 540 static int bnxt_init_fc_ctx_mem(struct bnxt *bp)
 541 {
 542         struct rte_pci_device *pdev = bp->pdev;
 543         char type[RTE_MEMZONE_NAMESIZE];
 544         uint16_t max_fc;
 545         int rc = 0;
 546
 547         max_fc = bp->flow_stat->max_fc;
 548
 549         sprintf(type, "bnxt_rx_fc_in_" PCI_PRI_FMT, pdev->addr.domain,
 550                 pdev->addr.bus, pdev->addr.devid, pdev->addr.function);
 551         /* 4 bytes for each counter-id */
 552         rc = bnxt_alloc_ctx_mem_buf(type,
 553                                     max_fc * 4,
 554                                     &bp->flow_stat->rx_fc_in_tbl);
 555         if (rc)
 556                 return rc;
 557
 558         sprintf(type, "bnxt_rx_fc_out_" PCI_PRI_FMT, pdev->addr.domain,
 559                 pdev->addr.bus, pdev->addr.devid, pdev->addr.function);
 560         /* 16 bytes for each counter - 8 bytes pkt_count, 8 bytes byte_count */
 561         rc = bnxt_alloc_ctx_mem_buf(type,
 562                                     max_fc * 16,
 563                                     &bp->flow_stat->rx_fc_out_tbl);
 564         if (rc)
 565                 return rc;
 566
 567         sprintf(type, "bnxt_tx_fc_in_" PCI_PRI_FMT, pdev->addr.domain,
 568                 pdev->addr.bus, pdev->addr.devid, pdev->addr.function);
 569         /* 4 bytes for each counter-id */
 570         rc = bnxt_alloc_ctx_mem_buf(type,
 571                                     max_fc * 4,
 572                                     &bp->flow_stat->tx_fc_in_tbl);
 573         if (rc)
 574                 return rc;
 575
 576         sprintf(type, "bnxt_tx_fc_out_" PCI_PRI_FMT, pdev->addr.domain,
 577                 pdev->addr.bus, pdev->addr.devid, pdev->addr.function);
 578         /* 16 bytes for each counter - 8 bytes pkt_count, 8 bytes byte_count */
 579         rc = bnxt_alloc_ctx_mem_buf(type,
 580                                     max_fc * 16,
 581                                     &bp->flow_stat->tx_fc_out_tbl);
 582         if (rc)
 583                 return rc;
 584
 585         rc = bnxt_register_fc_ctx_mem(bp);
 586
 587         return rc;
 588 }
 589
 590 static int bnxt_init_ctx_mem(struct bnxt *bp)
 591 {
 592         int rc = 0;
 593
 594         if (!(bp->fw_cap & BNXT_FW_CAP_ADV_FLOW_COUNTERS) ||
 595             !(BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp)) ||
 596             !BNXT_FLOW_XSTATS_EN(bp))
 597                 return 0;
 598
 599         rc = bnxt_hwrm_cfa_counter_qcaps(bp, &bp->flow_stat->max_fc);
 600         if (rc)
 601                 return rc;
 602
 603         rc = bnxt_init_fc_ctx_mem(bp);
 604
 605         return rc;
 606 }
 607
 608 static int bnxt_update_phy_setting(struct bnxt *bp)
 609 {
 610         struct rte_eth_link new;
 611         int rc;
 612
 613         rc = bnxt_get_hwrm_link_config(bp, &new);
 614         if (rc) {
 615                 PMD_DRV_LOG(ERR, "Failed to get link settings\n");
 616                 return rc;
 617         }
 618
 619         /*
 620          * On BCM957508-N2100 adapters, FW will not allow any user other
 621          * than BMC to shutdown the port. bnxt_get_hwrm_link_config() call
 622          * always returns link up. Force phy update always in that case.
 623          */
 624         if (!new.link_status || IS_BNXT_DEV_957508_N2100(bp)) {
 625                 rc = bnxt_set_hwrm_link_config(bp, true);
 626                 if (rc) {
 627                         PMD_DRV_LOG(ERR, "Failed to update PHY settings\n");
 628                         return rc;
 629                 }
 630         }
 631
 632         return rc;
 633 }
 634
 635 static int bnxt_init_chip(struct bnxt *bp)
 636 {
 637         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(bp->eth_dev);
 638         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
 639         uint32_t intr_vector = 0;
 640         uint32_t queue_id, base = BNXT_MISC_VEC_ID;
 641         uint32_t vec = BNXT_MISC_VEC_ID;
 642         unsigned int i, j;
 643         int rc;
 644
 645         if (bp->eth_dev->data->mtu > RTE_ETHER_MTU) {
 646                 bp->eth_dev->data->dev_conf.rxmode.offloads |=
 647                         DEV_RX_OFFLOAD_JUMBO_FRAME;
 648                 bp->flags |= BNXT_FLAG_JUMBO;
 649         } else {
 650                 bp->eth_dev->data->dev_conf.rxmode.offloads &=
 651                         ~DEV_RX_OFFLOAD_JUMBO_FRAME;
 652                 bp->flags &= ~BNXT_FLAG_JUMBO;
 653         }
 654
 655         /* THOR does not support ring groups.
 656          * But we will use the array to save RSS context IDs.
 657          */
 658         if (BNXT_CHIP_THOR(bp))
 659                 bp->max_ring_grps = BNXT_MAX_RSS_CTXTS_THOR;
 660
 661         rc = bnxt_alloc_all_hwrm_stat_ctxs(bp);
 662         if (rc) {
 663                 PMD_DRV_LOG(ERR, "HWRM stat ctx alloc failure rc: %x\n", rc);
 664                 goto err_out;
 665         }
 666
 667         rc = bnxt_alloc_hwrm_rings(bp);
 668         if (rc) {
 669                 PMD_DRV_LOG(ERR, "HWRM ring alloc failure rc: %x\n", rc);
 670                 goto err_out;
 671         }
 672
 673         rc = bnxt_alloc_all_hwrm_ring_grps(bp);
 674         if (rc) {
 675                 PMD_DRV_LOG(ERR, "HWRM ring grp alloc failure: %x\n", rc);
 676                 goto err_out;
 677         }
 678
 679         if (!(bp->vnic_cap_flags & BNXT_VNIC_CAP_COS_CLASSIFY))
 680                 goto skip_cosq_cfg;
 681
 682         for (j = 0, i = 0; i < BNXT_COS_QUEUE_COUNT; i++) {
 683                 if (bp->rx_cos_queue[i].id != 0xff) {
 684                         struct bnxt_vnic_info *vnic = &bp->vnic_info[j++];
 685
 686                         if (!vnic) {
 687                                 PMD_DRV_LOG(ERR,
 688                                             "Num pools more than FW profile\n");
 689                                 rc = -EINVAL;
 690                                 goto err_out;
 691                         }
 692                         vnic->cos_queue_id = bp->rx_cos_queue[i].id;
 693                         bp->rx_cosq_cnt++;
 694                 }
 695         }
 696
 697 skip_cosq_cfg:
 698         rc = bnxt_mq_rx_configure(bp);
 699         if (rc) {
 700                 PMD_DRV_LOG(ERR, "MQ mode configure failure rc: %x\n", rc);
 701                 goto err_out;
 702         }
 703
 704         /* VNIC configuration */
 705         for (i = 0; i < bp->nr_vnics; i++) {
 706                 rc = bnxt_setup_one_vnic(bp, i);
 707                 if (rc)
 708                         goto err_out;
 709         }
 710
 711         rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, &bp->vnic_info[0], 0, NULL);
 712         if (rc) {
 713                 PMD_DRV_LOG(ERR,
 714                         "HWRM cfa l2 rx mask failure rc: %x\n", rc);
 715                 goto err_out;
 716         }
 717
 718         /* check and configure queue intr-vector mapping */
 719         if ((rte_intr_cap_multiple(intr_handle) ||
 720              !RTE_ETH_DEV_SRIOV(bp->eth_dev).active) &&
 721             bp->eth_dev->data->dev_conf.intr_conf.rxq != 0) {
 722                 intr_vector = bp->eth_dev->data->nb_rx_queues;
 723                 PMD_DRV_LOG(DEBUG, "intr_vector = %d\n", intr_vector);
 724                 if (intr_vector > bp->rx_cp_nr_rings) {
 725                         PMD_DRV_LOG(ERR, "At most %d intr queues supported",
 726                                         bp->rx_cp_nr_rings);
 727                         return -ENOTSUP;
 728                 }
 729                 rc = rte_intr_efd_enable(intr_handle, intr_vector);
 730                 if (rc)
 731                         return rc;
 732         }
 733
 734         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
 735                 intr_handle->intr_vec =
 736                         rte_zmalloc("intr_vec",
 737                                     bp->eth_dev->data->nb_rx_queues *
 738                                     sizeof(int), 0);
 739                 if (intr_handle->intr_vec == NULL) {
 740                         PMD_DRV_LOG(ERR, "Failed to allocate %d rx_queues"
 741                                 " intr_vec", bp->eth_dev->data->nb_rx_queues);
 742                         rc = -ENOMEM;
 743                         goto err_disable;
 744                 }
 745                 PMD_DRV_LOG(DEBUG, "intr_handle->intr_vec = %p "
 746                         "intr_handle->nb_efd = %d intr_handle->max_intr = %d\n",
 747                          intr_handle->intr_vec, intr_handle->nb_efd,
 748                         intr_handle->max_intr);
 749                 for (queue_id = 0; queue_id < bp->eth_dev->data->nb_rx_queues;
 750                      queue_id++) {
 751                         intr_handle->intr_vec[queue_id] =
 752                                                         vec + BNXT_RX_VEC_START;
 753                         if (vec < base + intr_handle->nb_efd - 1)
 754                                 vec++;
 755                 }
 756         }
 757
 758         /* enable uio/vfio intr/eventfd mapping */
 759         rc = rte_intr_enable(intr_handle);
 760 #ifndef RTE_EXEC_ENV_FREEBSD
 761         /* In FreeBSD OS, nic_uio driver does not support interrupts */
 762         if (rc)
 763                 goto err_free;
 764 #endif
 765
 766         rc = bnxt_update_phy_setting(bp);
 767         if (rc)
 768                 goto err_free;
 769
 770         bp->mark_table = rte_zmalloc("bnxt_mark_table", BNXT_MARK_TABLE_SZ, 0);
 771         if (!bp->mark_table)
 772                 PMD_DRV_LOG(ERR, "Allocation of mark table failed\n");
 773
 774         return 0;
 775
 776 err_free:
 777         rte_free(intr_handle->intr_vec);
 778 err_disable:
 779         rte_intr_efd_disable(intr_handle);
 780 err_out:
 781         /* Some of the error status returned by FW may not be from errno.h */
 782         if (rc > 0)
 783                 rc = -EIO;
 784
 785         return rc;
 786 }
 787
 788 static int bnxt_shutdown_nic(struct bnxt *bp)
 789 {
 790         bnxt_free_all_hwrm_resources(bp);
 791         bnxt_free_all_filters(bp);
 792         bnxt_free_all_vnics(bp);
 793         return 0;
 794 }
 795
 796 /*
 797  * Device configuration and status function
 798  */
 799
 800 uint32_t bnxt_get_speed_capabilities(struct bnxt *bp)
 801 {
 802         uint32_t link_speed = bp->link_info->support_speeds;
 803         uint32_t speed_capa = 0;
 804
 805         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_100MB)
 806                 speed_capa |= ETH_LINK_SPEED_100M;
 807         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_100MBHD)
 808                 speed_capa |= ETH_LINK_SPEED_100M_HD;
 809         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_1GB)
 810                 speed_capa |= ETH_LINK_SPEED_1G;
 811         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_2_5GB)
 812                 speed_capa |= ETH_LINK_SPEED_2_5G;
 813         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_10GB)
 814                 speed_capa |= ETH_LINK_SPEED_10G;
 815         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_20GB)
 816                 speed_capa |= ETH_LINK_SPEED_20G;
 817         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_25GB)
 818                 speed_capa |= ETH_LINK_SPEED_25G;
 819         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_40GB)
 820                 speed_capa |= ETH_LINK_SPEED_40G;
 821         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_50GB)
 822                 speed_capa |= ETH_LINK_SPEED_50G;
 823         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_100GB)
 824                 speed_capa |= ETH_LINK_SPEED_100G;
 825         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_200GB)
 826                 speed_capa |= ETH_LINK_SPEED_200G;
 827
 828         if (bp->link_info->auto_mode ==
 829             HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_MODE_NONE)
 830                 speed_capa |= ETH_LINK_SPEED_FIXED;
 831         else
 832                 speed_capa |= ETH_LINK_SPEED_AUTONEG;
 833
 834         return speed_capa;
 835 }
 836
 837 static int bnxt_dev_info_get_op(struct rte_eth_dev *eth_dev,
 838                                 struct rte_eth_dev_info *dev_info)
 839 {
 840         struct rte_pci_device *pdev = RTE_DEV_TO_PCI(eth_dev->device);
 841         struct bnxt *bp = eth_dev->data->dev_private;
 842         uint16_t max_vnics, i, j, vpool, vrxq;
 843         unsigned int max_rx_rings;
 844         int rc;
 845
 846         rc = is_bnxt_in_error(bp);
 847         if (rc)
 848                 return rc;
 849
 850         /* MAC Specifics */
 851         dev_info->max_mac_addrs = bp->max_l2_ctx;
 852         dev_info->max_hash_mac_addrs = 0;
 853
 854         /* PF/VF specifics */
 855         if (BNXT_PF(bp))
 856                 dev_info->max_vfs = pdev->max_vfs;
 857
 858         max_rx_rings = BNXT_MAX_RINGS(bp);
 859         /* For the sake of symmetry, max_rx_queues = max_tx_queues */
 860         dev_info->max_rx_queues = max_rx_rings;
 861         dev_info->max_tx_queues = max_rx_rings;
 862         dev_info->reta_size = bnxt_rss_hash_tbl_size(bp);
 863         dev_info->hash_key_size = 40;
 864         max_vnics = bp->max_vnics;
 865
 866         /* MTU specifics */
 867         dev_info->min_mtu = RTE_ETHER_MIN_MTU;
 868         dev_info->max_mtu = BNXT_MAX_MTU;
 869
 870         /* Fast path specifics */
 871         dev_info->min_rx_bufsize = 1;
 872         dev_info->max_rx_pktlen = BNXT_MAX_PKT_LEN;
 873
 874         dev_info->rx_offload_capa = BNXT_DEV_RX_OFFLOAD_SUPPORT;
 875         if (bp->flags & BNXT_FLAG_PTP_SUPPORTED)
 876                 dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_TIMESTAMP;
 877         dev_info->tx_offload_capa = BNXT_DEV_TX_OFFLOAD_SUPPORT;
 878         dev_info->flow_type_rss_offloads = BNXT_ETH_RSS_SUPPORT;
 879
 880         dev_info->speed_capa = bnxt_get_speed_capabilities(bp);
 881
 882         /* *INDENT-OFF* */
 883         dev_info->default_rxconf = (struct rte_eth_rxconf) {
 884                 .rx_thresh = {
 885                         .pthresh = 8,
 886                         .hthresh = 8,
 887                         .wthresh = 0,
 888                 },
 889                 .rx_free_thresh = 32,
 890                 /* If no descriptors available, pkts are dropped by default */
 891                 .rx_drop_en = 1,
 892         };
 893
 894         dev_info->default_txconf = (struct rte_eth_txconf) {
 895                 .tx_thresh = {
 896                         .pthresh = 32,
 897                         .hthresh = 0,
 898                         .wthresh = 0,
 899                 },
 900                 .tx_free_thresh = 32,
 901                 .tx_rs_thresh = 32,
 902         };
 903         eth_dev->data->dev_conf.intr_conf.lsc = 1;
 904
 905         eth_dev->data->dev_conf.intr_conf.rxq = 1;
 906         dev_info->rx_desc_lim.nb_min = BNXT_MIN_RING_DESC;
 907         dev_info->rx_desc_lim.nb_max = BNXT_MAX_RX_RING_DESC;
 908         dev_info->tx_desc_lim.nb_min = BNXT_MIN_RING_DESC;
 909         dev_info->tx_desc_lim.nb_max = BNXT_MAX_TX_RING_DESC;
 910
 911         /* *INDENT-ON* */
 912
 913         /*
 914          * TODO: default_rxconf, default_txconf, rx_desc_lim, and tx_desc_lim
 915          *       need further investigation.
 916          */
 917
 918         /* VMDq resources */
 919         vpool = 64; /* ETH_64_POOLS */
 920         vrxq = 128; /* ETH_VMDQ_DCB_NUM_QUEUES */
 921         for (i = 0; i < 4; vpool >>= 1, i++) {
 922                 if (max_vnics > vpool) {
 923                         for (j = 0; j < 5; vrxq >>= 1, j++) {
 924                                 if (dev_info->max_rx_queues > vrxq) {
 925                                         if (vpool > vrxq)
 926                                                 vpool = vrxq;
 927                                         goto found;
 928                                 }
 929                         }
 930                         /* Not enough resources to support VMDq */
 931                         break;
 932                 }
 933         }
 934         /* Not enough resources to support VMDq */
 935         vpool = 0;
 936         vrxq = 0;
 937 found:
 938         dev_info->max_vmdq_pools = vpool;
 939         dev_info->vmdq_queue_num = vrxq;
 940
 941         dev_info->vmdq_pool_base = 0;
 942         dev_info->vmdq_queue_base = 0;
 943
 944         return 0;
 945 }
 946
 947 /* Configure the device based on the configuration provided */
 948 static int bnxt_dev_configure_op(struct rte_eth_dev *eth_dev)
 949 {
 950         struct bnxt *bp = eth_dev->data->dev_private;
 951         uint64_t rx_offloads = eth_dev->data->dev_conf.rxmode.offloads;
 952         int rc;
 953
 954         bp->rx_queues = (void *)eth_dev->data->rx_queues;
 955         bp->tx_queues = (void *)eth_dev->data->tx_queues;
 956         bp->tx_nr_rings = eth_dev->data->nb_tx_queues;
 957         bp->rx_nr_rings = eth_dev->data->nb_rx_queues;
 958
 959         rc = is_bnxt_in_error(bp);
 960         if (rc)
 961                 return rc;
 962
 963         if (BNXT_VF(bp) && (bp->flags & BNXT_FLAG_NEW_RM)) {
 964                 rc = bnxt_hwrm_check_vf_rings(bp);
 965                 if (rc) {
 966                         PMD_DRV_LOG(ERR, "HWRM insufficient resources\n");
 967                         return -ENOSPC;
 968                 }
 969
 970                 /* If a resource has already been allocated - in this case
 971                  * it is the async completion ring, free it. Reallocate it after
 972                  * resource reservation. This will ensure the resource counts
 973                  * are calculated correctly.
 974                  */
 975
 976                 pthread_mutex_lock(&bp->def_cp_lock);
 977
 978                 if (!BNXT_HAS_NQ(bp) && bp->async_cp_ring) {
 979                         bnxt_disable_int(bp);
 980                         bnxt_free_cp_ring(bp, bp->async_cp_ring);
 981                 }
 982
 983                 rc = bnxt_hwrm_func_reserve_vf_resc(bp, false);
 984                 if (rc) {
 985                         PMD_DRV_LOG(ERR, "HWRM resource alloc fail:%x\n", rc);
 986                         pthread_mutex_unlock(&bp->def_cp_lock);
 987                         return -ENOSPC;
 988                 }
 989
 990                 if (!BNXT_HAS_NQ(bp) && bp->async_cp_ring) {
 991                         rc = bnxt_alloc_async_cp_ring(bp);
 992                         if (rc) {
 993                                 pthread_mutex_unlock(&bp->def_cp_lock);
 994                                 return rc;
 995                         }
 996                         bnxt_enable_int(bp);
 997                 }
 998
 999                 pthread_mutex_unlock(&bp->def_cp_lock);
1000         } else {
1001                 /* legacy driver needs to get updated values */
1002                 rc = bnxt_hwrm_func_qcaps(bp);
1003                 if (rc) {
1004                         PMD_DRV_LOG(ERR, "hwrm func qcaps fail:%d\n", rc);
1005                         return rc;
1006                 }
1007         }
1008
1009         /* Inherit new configurations */
1010         if (eth_dev->data->nb_rx_queues > bp->max_rx_rings ||
1011             eth_dev->data->nb_tx_queues > bp->max_tx_rings ||
1012             eth_dev->data->nb_rx_queues + eth_dev->data->nb_tx_queues
1013                 + BNXT_NUM_ASYNC_CPR(bp) > bp->max_cp_rings ||
1014             eth_dev->data->nb_rx_queues + eth_dev->data->nb_tx_queues >
1015             bp->max_stat_ctx)
1016                 goto resource_error;
1017
1018         if (BNXT_HAS_RING_GRPS(bp) &&
1019             (uint32_t)(eth_dev->data->nb_rx_queues) > bp->max_ring_grps)
1020                 goto resource_error;
1021
1022         if (!(eth_dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_RSS) &&
1023             bp->max_vnics < eth_dev->data->nb_rx_queues)
1024                 goto resource_error;
1025
1026         bp->rx_cp_nr_rings = bp->rx_nr_rings;
1027         bp->tx_cp_nr_rings = bp->tx_nr_rings;
1028
1029         if (eth_dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG)
1030                 rx_offloads |= DEV_RX_OFFLOAD_RSS_HASH;
1031         eth_dev->data->dev_conf.rxmode.offloads = rx_offloads;
1032
1033         if (rx_offloads & DEV_RX_OFFLOAD_JUMBO_FRAME) {
1034                 eth_dev->data->mtu =
1035                         eth_dev->data->dev_conf.rxmode.max_rx_pkt_len -
1036                         RTE_ETHER_HDR_LEN - RTE_ETHER_CRC_LEN - VLAN_TAG_SIZE *
1037                         BNXT_NUM_VLANS;
1038                 bnxt_mtu_set_op(eth_dev, eth_dev->data->mtu);
1039         }
1040         return 0;
1041
1042 resource_error:
1043         PMD_DRV_LOG(ERR,
1044                     "Insufficient resources to support requested config\n");
1045         PMD_DRV_LOG(ERR,
1046                     "Num Queues Requested: Tx %d, Rx %d\n",
1047                     eth_dev->data->nb_tx_queues,
1048                     eth_dev->data->nb_rx_queues);
1049         PMD_DRV_LOG(ERR,
1050                     "MAX: TxQ %d, RxQ %d, CQ %d Stat %d, Grp %d, Vnic %d\n",
1051                     bp->max_tx_rings, bp->max_rx_rings, bp->max_cp_rings,
1052                     bp->max_stat_ctx, bp->max_ring_grps, bp->max_vnics);
1053         return -ENOSPC;
1054 }
1055
1056 void bnxt_print_link_info(struct rte_eth_dev *eth_dev)
1057 {
1058         struct rte_eth_link *link = &eth_dev->data->dev_link;
1059
1060         if (link->link_status)
1061                 PMD_DRV_LOG(INFO, "Port %d Link Up - speed %u Mbps - %s\n",
1062                         eth_dev->data->port_id,
1063                         (uint32_t)link->link_speed,
1064                         (link->link_duplex == ETH_LINK_FULL_DUPLEX) ?
1065                         ("full-duplex") : ("half-duplex\n"));
1066         else
1067                 PMD_DRV_LOG(INFO, "Port %d Link Down\n",
1068                         eth_dev->data->port_id);
1069 }
1070
1071 /*
1072  * Determine whether the current configuration requires support for scattered
1073  * receive; return 1 if scattered receive is required and 0 if not.
1074  */
1075 static int bnxt_scattered_rx(struct rte_eth_dev *eth_dev)
1076 {
1077         uint16_t buf_size;
1078         int i;
1079
1080         if (eth_dev->data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_SCATTER)
1081                 return 1;
1082
1083         for (i = 0; i < eth_dev->data->nb_rx_queues; i++) {
1084                 struct bnxt_rx_queue *rxq = eth_dev->data->rx_queues[i];
1085
1086                 buf_size = (uint16_t)(rte_pktmbuf_data_room_size(rxq->mb_pool) -
1087                                       RTE_PKTMBUF_HEADROOM);
1088                 if (eth_dev->data->dev_conf.rxmode.max_rx_pkt_len > buf_size)
1089                         return 1;
1090         }
1091         return 0;
1092 }
1093
1094 static eth_rx_burst_t
1095 bnxt_receive_function(struct rte_eth_dev *eth_dev)
1096 {
1097         struct bnxt *bp = eth_dev->data->dev_private;
1098
1099 #if defined(RTE_ARCH_X86) || defined(RTE_ARCH_ARM64)
1100 #ifndef RTE_LIBRTE_IEEE1588
1101         /*
1102          * Vector mode receive can be enabled only if scatter rx is not
1103          * in use and rx offloads are limited to VLAN stripping and
1104          * CRC stripping.
1105          */
1106         if (!eth_dev->data->scattered_rx &&
1107             !(eth_dev->data->dev_conf.rxmode.offloads &
1108               ~(DEV_RX_OFFLOAD_VLAN_STRIP |
1109                 DEV_RX_OFFLOAD_KEEP_CRC |
1110                 DEV_RX_OFFLOAD_JUMBO_FRAME |
1111                 DEV_RX_OFFLOAD_IPV4_CKSUM |
1112                 DEV_RX_OFFLOAD_UDP_CKSUM |
1113                 DEV_RX_OFFLOAD_TCP_CKSUM |
1114                 DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM |
1115                 DEV_RX_OFFLOAD_RSS_HASH |
1116                 DEV_RX_OFFLOAD_VLAN_FILTER)) &&
1117             !BNXT_TRUFLOW_EN(bp) && BNXT_NUM_ASYNC_CPR(bp)) {
1118                 PMD_DRV_LOG(INFO, "Using vector mode receive for port %d\n",
1119                             eth_dev->data->port_id);
1120                 bp->flags |= BNXT_FLAG_RX_VECTOR_PKT_MODE;
1121                 return bnxt_recv_pkts_vec;
1122         }
1123         PMD_DRV_LOG(INFO, "Vector mode receive disabled for port %d\n",
1124                     eth_dev->data->port_id);
1125         PMD_DRV_LOG(INFO,
1126                     "Port %d scatter: %d rx offload: %" PRIX64 "\n",
1127                     eth_dev->data->port_id,
1128                     eth_dev->data->scattered_rx,
1129                     eth_dev->data->dev_conf.rxmode.offloads);
1130 #endif
1131 #endif
1132         bp->flags &= ~BNXT_FLAG_RX_VECTOR_PKT_MODE;
1133         return bnxt_recv_pkts;
1134 }
1135
1136 static eth_tx_burst_t
1137 bnxt_transmit_function(__rte_unused struct rte_eth_dev *eth_dev)
1138 {
1139 #if defined(RTE_ARCH_X86) || defined(RTE_ARCH_ARM64)
1140 #ifndef RTE_LIBRTE_IEEE1588
1141         struct bnxt *bp = eth_dev->data->dev_private;
1142
1143         /*
1144          * Vector mode transmit can be enabled only if not using scatter rx
1145          * or tx offloads.
1146          */
1147         if (!eth_dev->data->scattered_rx &&
1148             !eth_dev->data->dev_conf.txmode.offloads &&
1149             !BNXT_TRUFLOW_EN(bp)) {
1150                 PMD_DRV_LOG(INFO, "Using vector mode transmit for port %d\n",
1151                             eth_dev->data->port_id);
1152                 return bnxt_xmit_pkts_vec;
1153         }
1154         PMD_DRV_LOG(INFO, "Vector mode transmit disabled for port %d\n",
1155                     eth_dev->data->port_id);
1156         PMD_DRV_LOG(INFO,
1157                     "Port %d scatter: %d tx offload: %" PRIX64 "\n",
1158                     eth_dev->data->port_id,
1159                     eth_dev->data->scattered_rx,
1160                     eth_dev->data->dev_conf.txmode.offloads);
1161 #endif
1162 #endif
1163         return bnxt_xmit_pkts;
1164 }
1165
1166 static int bnxt_handle_if_change_status(struct bnxt *bp)
1167 {
1168         int rc;
1169
1170         /* Since fw has undergone a reset and lost all contexts,
1171          * set fatal flag to not issue hwrm during cleanup
1172          */
1173         bp->flags |= BNXT_FLAG_FATAL_ERROR;
1174         bnxt_uninit_resources(bp, true);
1175
1176         /* clear fatal flag so that re-init happens */
1177         bp->flags &= ~BNXT_FLAG_FATAL_ERROR;
1178         rc = bnxt_init_resources(bp, true);
1179
1180         bp->flags &= ~BNXT_FLAG_IF_CHANGE_HOT_FW_RESET_DONE;
1181
1182         return rc;
1183 }
1184
1185 static int bnxt_dev_start_op(struct rte_eth_dev *eth_dev)
1186 {
1187         struct bnxt *bp = eth_dev->data->dev_private;
1188         uint64_t rx_offloads = eth_dev->data->dev_conf.rxmode.offloads;
1189         int vlan_mask = 0;
1190         int rc, retry_cnt = BNXT_IF_CHANGE_RETRY_COUNT;
1191
1192         if (!eth_dev->data->nb_tx_queues || !eth_dev->data->nb_rx_queues) {
1193                 PMD_DRV_LOG(ERR, "Queues are not configured yet!\n");
1194                 return -EINVAL;
1195         }
1196
1197         if (bp->rx_cp_nr_rings > RTE_ETHDEV_QUEUE_STAT_CNTRS) {
1198                 PMD_DRV_LOG(ERR,
1199                         "RxQ cnt %d > CONFIG_RTE_ETHDEV_QUEUE_STAT_CNTRS %d\n",
1200                         bp->rx_cp_nr_rings, RTE_ETHDEV_QUEUE_STAT_CNTRS);
1201         }
1202
1203         do {
1204                 rc = bnxt_hwrm_if_change(bp, true);
1205                 if (rc == 0 || rc != -EAGAIN)
1206                         break;
1207
1208                 rte_delay_ms(BNXT_IF_CHANGE_RETRY_INTERVAL);
1209         } while (retry_cnt--);
1210
1211         if (rc)
1212                 return rc;
1213
1214         if (bp->flags & BNXT_FLAG_IF_CHANGE_HOT_FW_RESET_DONE) {
1215                 rc = bnxt_handle_if_change_status(bp);
1216                 if (rc)
1217                         return rc;
1218         }
1219
1220         bnxt_enable_int(bp);
1221
1222         rc = bnxt_init_chip(bp);
1223         if (rc)
1224                 goto error;
1225
1226         eth_dev->data->scattered_rx = bnxt_scattered_rx(eth_dev);
1227         eth_dev->data->dev_started = 1;
1228
1229         bnxt_link_update(eth_dev, 1, ETH_LINK_UP);
1230
1231         if (rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER)
1232                 vlan_mask |= ETH_VLAN_FILTER_MASK;
1233         if (rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
1234                 vlan_mask |= ETH_VLAN_STRIP_MASK;
1235         rc = bnxt_vlan_offload_set_op(eth_dev, vlan_mask);
1236         if (rc)
1237                 goto error;
1238
1239         /* Initialize bnxt ULP port details */
1240         rc = bnxt_ulp_port_init(bp);
1241         if (rc)
1242                 goto error;
1243
1244         eth_dev->rx_pkt_burst = bnxt_receive_function(eth_dev);
1245         eth_dev->tx_pkt_burst = bnxt_transmit_function(eth_dev);
1246
1247         pthread_mutex_lock(&bp->def_cp_lock);
1248         bnxt_schedule_fw_health_check(bp);
1249         pthread_mutex_unlock(&bp->def_cp_lock);
1250
1251         return 0;
1252
1253 error:
1254         bnxt_shutdown_nic(bp);
1255         bnxt_free_tx_mbufs(bp);
1256         bnxt_free_rx_mbufs(bp);
1257         bnxt_hwrm_if_change(bp, false);
1258         eth_dev->data->dev_started = 0;
1259         return rc;
1260 }
1261
1262 static int bnxt_dev_set_link_up_op(struct rte_eth_dev *eth_dev)
1263 {
1264         struct bnxt *bp = eth_dev->data->dev_private;
1265         int rc = 0;
1266
1267         if (!bp->link_info->link_up)
1268                 rc = bnxt_set_hwrm_link_config(bp, true);
1269         if (!rc)
1270                 eth_dev->data->dev_link.link_status = 1;
1271
1272         bnxt_print_link_info(eth_dev);
1273         return rc;
1274 }
1275
1276 static int bnxt_dev_set_link_down_op(struct rte_eth_dev *eth_dev)
1277 {
1278         struct bnxt *bp = eth_dev->data->dev_private;
1279
1280         eth_dev->data->dev_link.link_status = 0;
1281         bnxt_set_hwrm_link_config(bp, false);
1282         bp->link_info->link_up = 0;
1283
1284         return 0;
1285 }
1286
1287 static void bnxt_free_switch_domain(struct bnxt *bp)
1288 {
1289         if (bp->switch_domain_id)
1290                 rte_eth_switch_domain_free(bp->switch_domain_id);
1291 }
1292
1293 /* Unload the driver, release resources */
1294 static void bnxt_dev_stop_op(struct rte_eth_dev *eth_dev)
1295 {
1296         struct bnxt *bp = eth_dev->data->dev_private;
1297         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1298         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1299
1300         eth_dev->data->dev_started = 0;
1301         eth_dev->data->scattered_rx = 0;
1302
1303         /* Prevent crashes when queues are still in use */
1304         eth_dev->rx_pkt_burst = &bnxt_dummy_recv_pkts;
1305         eth_dev->tx_pkt_burst = &bnxt_dummy_xmit_pkts;
1306
1307         bnxt_disable_int(bp);
1308
1309         /* disable uio/vfio intr/eventfd mapping */
1310         rte_intr_disable(intr_handle);
1311
1312         /* delete the bnxt ULP port details */
1313         bnxt_ulp_port_deinit(bp);
1314
1315         bnxt_cancel_fw_health_check(bp);
1316
1317         bnxt_dev_set_link_down_op(eth_dev);
1318
1319         /* Wait for link to be reset and the async notification to process.
1320          * During reset recovery, there is no need to wait and
1321          * VF/NPAR functions do not have privilege to change PHY config.
1322          */
1323         if (!is_bnxt_in_error(bp) && BNXT_SINGLE_PF(bp))
1324                 bnxt_link_update(eth_dev, 1, ETH_LINK_DOWN);
1325
1326         /* Clean queue intr-vector mapping */
1327         rte_intr_efd_disable(intr_handle);
1328         if (intr_handle->intr_vec != NULL) {
1329                 rte_free(intr_handle->intr_vec);
1330                 intr_handle->intr_vec = NULL;
1331         }
1332
1333         bnxt_hwrm_port_clr_stats(bp);
1334         bnxt_free_tx_mbufs(bp);
1335         bnxt_free_rx_mbufs(bp);
1336         /* Process any remaining notifications in default completion queue */
1337         bnxt_int_handler(eth_dev);
1338         bnxt_shutdown_nic(bp);
1339         bnxt_hwrm_if_change(bp, false);
1340
1341         rte_free(bp->mark_table);
1342         bp->mark_table = NULL;
1343
1344         bp->flags &= ~BNXT_FLAG_RX_VECTOR_PKT_MODE;
1345         bp->rx_cosq_cnt = 0;
1346         /* All filters are deleted on a port stop. */
1347         if (BNXT_FLOW_XSTATS_EN(bp))
1348                 bp->flow_stat->flow_count = 0;
1349 }
1350
1351 static void bnxt_dev_close_op(struct rte_eth_dev *eth_dev)
1352 {
1353         struct bnxt *bp = eth_dev->data->dev_private;
1354
1355         /* cancel the recovery handler before remove dev */
1356         rte_eal_alarm_cancel(bnxt_dev_reset_and_resume, (void *)bp);
1357         rte_eal_alarm_cancel(bnxt_dev_recover, (void *)bp);
1358         bnxt_cancel_fc_thread(bp);
1359
1360         if (eth_dev->data->dev_started)
1361                 bnxt_dev_stop_op(eth_dev);
1362
1363         bnxt_free_switch_domain(bp);
1364
1365         bnxt_uninit_resources(bp, false);
1366
1367         bnxt_free_leds_info(bp);
1368         bnxt_free_cos_queues(bp);
1369         bnxt_free_link_info(bp);
1370         bnxt_free_pf_info(bp);
1371         bnxt_free_parent_info(bp);
1372
1373         eth_dev->dev_ops = NULL;
1374         eth_dev->rx_pkt_burst = NULL;
1375         eth_dev->tx_pkt_burst = NULL;
1376
1377         rte_memzone_free((const struct rte_memzone *)bp->tx_mem_zone);
1378         bp->tx_mem_zone = NULL;
1379         rte_memzone_free((const struct rte_memzone *)bp->rx_mem_zone);
1380         bp->rx_mem_zone = NULL;
1381
1382         bnxt_hwrm_free_vf_info(bp);
1383
1384         rte_free(bp->grp_info);
1385         bp->grp_info = NULL;
1386 }
1387
1388 static void bnxt_mac_addr_remove_op(struct rte_eth_dev *eth_dev,
1389                                     uint32_t index)
1390 {
1391         struct bnxt *bp = eth_dev->data->dev_private;
1392         uint64_t pool_mask = eth_dev->data->mac_pool_sel[index];
1393         struct bnxt_vnic_info *vnic;
1394         struct bnxt_filter_info *filter, *temp_filter;
1395         uint32_t i;
1396
1397         if (is_bnxt_in_error(bp))
1398                 return;
1399
1400         /*
1401          * Loop through all VNICs from the specified filter flow pools to
1402          * remove the corresponding MAC addr filter
1403          */
1404         for (i = 0; i < bp->nr_vnics; i++) {
1405                 if (!(pool_mask & (1ULL << i)))
1406                         continue;
1407
1408                 vnic = &bp->vnic_info[i];
1409                 filter = STAILQ_FIRST(&vnic->filter);
1410                 while (filter) {
1411                         temp_filter = STAILQ_NEXT(filter, next);
1412                         if (filter->mac_index == index) {
1413                                 STAILQ_REMOVE(&vnic->filter, filter,
1414                                                 bnxt_filter_info, next);
1415                                 bnxt_hwrm_clear_l2_filter(bp, filter);
1416                                 bnxt_free_filter(bp, filter);
1417                         }
1418                         filter = temp_filter;
1419                 }
1420         }
1421 }
1422
1423 static int bnxt_add_mac_filter(struct bnxt *bp, struct bnxt_vnic_info *vnic,
1424                                struct rte_ether_addr *mac_addr, uint32_t index,
1425                                uint32_t pool)
1426 {
1427         struct bnxt_filter_info *filter;
1428         int rc = 0;
1429
1430         /* Attach requested MAC address to the new l2_filter */
1431         STAILQ_FOREACH(filter, &vnic->filter, next) {
1432                 if (filter->mac_index == index) {
1433                         PMD_DRV_LOG(DEBUG,
1434                                     "MAC addr already existed for pool %d\n",
1435                                     pool);
1436                         return 0;
1437                 }
1438         }
1439
1440         filter = bnxt_alloc_filter(bp);
1441         if (!filter) {
1442                 PMD_DRV_LOG(ERR, "L2 filter alloc failed\n");
1443                 return -ENODEV;
1444         }
1445
1446         /* bnxt_alloc_filter copies default MAC to filter->l2_addr. So,
1447          * if the MAC that's been programmed now is a different one, then,
1448          * copy that addr to filter->l2_addr
1449          */
1450         if (mac_addr)
1451                 memcpy(filter->l2_addr, mac_addr, RTE_ETHER_ADDR_LEN);
1452         filter->flags |= HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_OUTERMOST;
1453
1454         rc = bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id, filter);
1455         if (!rc) {
1456                 filter->mac_index = index;
1457                 if (filter->mac_index == 0)
1458                         STAILQ_INSERT_HEAD(&vnic->filter, filter, next);
1459                 else
1460                         STAILQ_INSERT_TAIL(&vnic->filter, filter, next);
1461         } else {
1462                 bnxt_free_filter(bp, filter);
1463         }
1464
1465         return rc;
1466 }
1467
1468 static int bnxt_mac_addr_add_op(struct rte_eth_dev *eth_dev,
1469                                 struct rte_ether_addr *mac_addr,
1470                                 uint32_t index, uint32_t pool)
1471 {
1472         struct bnxt *bp = eth_dev->data->dev_private;
1473         struct bnxt_vnic_info *vnic = &bp->vnic_info[pool];
1474         int rc = 0;
1475
1476         rc = is_bnxt_in_error(bp);
1477         if (rc)
1478                 return rc;
1479
1480         if (BNXT_VF(bp) & !BNXT_VF_IS_TRUSTED(bp)) {
1481                 PMD_DRV_LOG(ERR, "Cannot add MAC address to a VF interface\n");
1482                 return -ENOTSUP;
1483         }
1484
1485         if (!vnic) {
1486                 PMD_DRV_LOG(ERR, "VNIC not found for pool %d!\n", pool);
1487                 return -EINVAL;
1488         }
1489
1490         /* Filter settings will get applied when port is started */
1491         if (!eth_dev->data->dev_started)
1492                 return 0;
1493
1494         rc = bnxt_add_mac_filter(bp, vnic, mac_addr, index, pool);
1495
1496         return rc;
1497 }
1498
1499 int bnxt_link_update(struct rte_eth_dev *eth_dev, int wait_to_complete,
1500                      bool exp_link_status)
1501 {
1502         int rc = 0;
1503         struct bnxt *bp = eth_dev->data->dev_private;
1504         struct rte_eth_link new;
1505         int cnt = exp_link_status ? BNXT_LINK_UP_WAIT_CNT :
1506                   BNXT_LINK_DOWN_WAIT_CNT;
1507
1508         rc = is_bnxt_in_error(bp);
1509         if (rc)
1510                 return rc;
1511
1512         memset(&new, 0, sizeof(new));
1513         do {
1514                 /* Retrieve link info from hardware */
1515                 rc = bnxt_get_hwrm_link_config(bp, &new);
1516                 if (rc) {
1517                         new.link_speed = ETH_LINK_SPEED_100M;
1518                         new.link_duplex = ETH_LINK_FULL_DUPLEX;
1519                         PMD_DRV_LOG(ERR,
1520                                 "Failed to retrieve link rc = 0x%x!\n", rc);
1521                         goto out;
1522                 }
1523
1524                 if (!wait_to_complete || new.link_status == exp_link_status)
1525                         break;
1526
1527                 rte_delay_ms(BNXT_LINK_WAIT_INTERVAL);
1528         } while (cnt--);
1529
1530 out:
1531         /* Timed out or success */
1532         if (new.link_status != eth_dev->data->dev_link.link_status ||
1533         new.link_speed != eth_dev->data->dev_link.link_speed) {
1534                 rte_eth_linkstatus_set(eth_dev, &new);
1535
1536                 rte_eth_dev_callback_process(eth_dev,
1537                                              RTE_ETH_EVENT_INTR_LSC,
1538                                              NULL);
1539
1540                 bnxt_print_link_info(eth_dev);
1541         }
1542
1543         return rc;
1544 }
1545
1546 int bnxt_link_update_op(struct rte_eth_dev *eth_dev,
1547                         int wait_to_complete)
1548 {
1549         return bnxt_link_update(eth_dev, wait_to_complete, ETH_LINK_UP);
1550 }
1551
1552 static int bnxt_promiscuous_enable_op(struct rte_eth_dev *eth_dev)
1553 {
1554         struct bnxt *bp = eth_dev->data->dev_private;
1555         struct bnxt_vnic_info *vnic;
1556         uint32_t old_flags;
1557         int rc;
1558
1559         rc = is_bnxt_in_error(bp);
1560         if (rc)
1561                 return rc;
1562
1563         /* Filter settings will get applied when port is started */
1564         if (!eth_dev->data->dev_started)
1565                 return 0;
1566
1567         if (bp->vnic_info == NULL)
1568                 return 0;
1569
1570         vnic = BNXT_GET_DEFAULT_VNIC(bp);
1571
1572         old_flags = vnic->flags;
1573         vnic->flags |= BNXT_VNIC_INFO_PROMISC;
1574         rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1575         if (rc != 0)
1576                 vnic->flags = old_flags;
1577
1578         return rc;
1579 }
1580
1581 static int bnxt_promiscuous_disable_op(struct rte_eth_dev *eth_dev)
1582 {
1583         struct bnxt *bp = eth_dev->data->dev_private;
1584         struct bnxt_vnic_info *vnic;
1585         uint32_t old_flags;
1586         int rc;
1587
1588         rc = is_bnxt_in_error(bp);
1589         if (rc)
1590                 return rc;
1591
1592         /* Filter settings will get applied when port is started */
1593         if (!eth_dev->data->dev_started)
1594                 return 0;
1595
1596         if (bp->vnic_info == NULL)
1597                 return 0;
1598
1599         vnic = BNXT_GET_DEFAULT_VNIC(bp);
1600
1601         old_flags = vnic->flags;
1602         vnic->flags &= ~BNXT_VNIC_INFO_PROMISC;
1603         rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1604         if (rc != 0)
1605                 vnic->flags = old_flags;
1606
1607         return rc;
1608 }
1609
1610 static int bnxt_allmulticast_enable_op(struct rte_eth_dev *eth_dev)
1611 {
1612         struct bnxt *bp = eth_dev->data->dev_private;
1613         struct bnxt_vnic_info *vnic;
1614         uint32_t old_flags;
1615         int rc;
1616
1617         rc = is_bnxt_in_error(bp);
1618         if (rc)
1619                 return rc;
1620
1621         /* Filter settings will get applied when port is started */
1622         if (!eth_dev->data->dev_started)
1623                 return 0;
1624
1625         if (bp->vnic_info == NULL)
1626                 return 0;
1627
1628         vnic = BNXT_GET_DEFAULT_VNIC(bp);
1629
1630         old_flags = vnic->flags;
1631         vnic->flags |= BNXT_VNIC_INFO_ALLMULTI;
1632         rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1633         if (rc != 0)
1634                 vnic->flags = old_flags;
1635
1636         return rc;
1637 }
1638
1639 static int bnxt_allmulticast_disable_op(struct rte_eth_dev *eth_dev)
1640 {
1641         struct bnxt *bp = eth_dev->data->dev_private;
1642         struct bnxt_vnic_info *vnic;
1643         uint32_t old_flags;
1644         int rc;
1645
1646         rc = is_bnxt_in_error(bp);
1647         if (rc)
1648                 return rc;
1649
1650         /* Filter settings will get applied when port is started */
1651         if (!eth_dev->data->dev_started)
1652                 return 0;
1653
1654         if (bp->vnic_info == NULL)
1655                 return 0;
1656
1657         vnic = BNXT_GET_DEFAULT_VNIC(bp);
1658
1659         old_flags = vnic->flags;
1660         vnic->flags &= ~BNXT_VNIC_INFO_ALLMULTI;
1661         rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1662         if (rc != 0)
1663                 vnic->flags = old_flags;
1664
1665         return rc;
1666 }
1667
1668 /* Return bnxt_rx_queue pointer corresponding to a given rxq. */
1669 static struct bnxt_rx_queue *bnxt_qid_to_rxq(struct bnxt *bp, uint16_t qid)
1670 {
1671         if (qid >= bp->rx_nr_rings)
1672                 return NULL;
1673
1674         return bp->eth_dev->data->rx_queues[qid];
1675 }
1676
1677 /* Return rxq corresponding to a given rss table ring/group ID. */
1678 static uint16_t bnxt_rss_to_qid(struct bnxt *bp, uint16_t fwr)
1679 {
1680         struct bnxt_rx_queue *rxq;
1681         unsigned int i;
1682
1683         if (!BNXT_HAS_RING_GRPS(bp)) {
1684                 for (i = 0; i < bp->rx_nr_rings; i++) {
1685                         rxq = bp->eth_dev->data->rx_queues[i];
1686                         if (rxq->rx_ring->rx_ring_struct->fw_ring_id == fwr)
1687                                 return rxq->index;
1688                 }
1689         } else {
1690                 for (i = 0; i < bp->rx_nr_rings; i++) {
1691                         if (bp->grp_info[i].fw_grp_id == fwr)
1692                                 return i;
1693                 }
1694         }
1695
1696         return INVALID_HW_RING_ID;
1697 }
1698
1699 static int bnxt_reta_update_op(struct rte_eth_dev *eth_dev,
1700                             struct rte_eth_rss_reta_entry64 *reta_conf,
1701                             uint16_t reta_size)
1702 {
1703         struct bnxt *bp = eth_dev->data->dev_private;
1704         struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
1705         struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp);
1706         uint16_t tbl_size = bnxt_rss_hash_tbl_size(bp);
1707         uint16_t idx, sft;
1708         int i, rc;
1709
1710         rc = is_bnxt_in_error(bp);
1711         if (rc)
1712                 return rc;
1713
1714         if (!vnic->rss_table)
1715                 return -EINVAL;
1716
1717         if (!(dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG))
1718                 return -EINVAL;
1719
1720         if (reta_size != tbl_size) {
1721                 PMD_DRV_LOG(ERR, "The configured hash table lookup size "
1722                         "(%d) must equal the size supported by the hardware "
1723                         "(%d)\n", reta_size, tbl_size);
1724                 return -EINVAL;
1725         }
1726
1727         for (i = 0; i < reta_size; i++) {
1728                 struct bnxt_rx_queue *rxq;
1729
1730                 idx = i / RTE_RETA_GROUP_SIZE;
1731                 sft = i % RTE_RETA_GROUP_SIZE;
1732
1733                 if (!(reta_conf[idx].mask & (1ULL << sft)))
1734                         continue;
1735
1736                 rxq = bnxt_qid_to_rxq(bp, reta_conf[idx].reta[sft]);
1737                 if (!rxq) {
1738                         PMD_DRV_LOG(ERR, "Invalid ring in reta_conf.\n");
1739                         return -EINVAL;
1740                 }
1741
1742                 if (BNXT_CHIP_THOR(bp)) {
1743                         vnic->rss_table[i * 2] =
1744                                 rxq->rx_ring->rx_ring_struct->fw_ring_id;
1745                         vnic->rss_table[i * 2 + 1] =
1746                                 rxq->cp_ring->cp_ring_struct->fw_ring_id;
1747                 } else {
1748                         vnic->rss_table[i] =
1749                             vnic->fw_grp_ids[reta_conf[idx].reta[sft]];
1750                 }
1751         }
1752
1753         bnxt_hwrm_vnic_rss_cfg(bp, vnic);
1754         return 0;
1755 }
1756
1757 static int bnxt_reta_query_op(struct rte_eth_dev *eth_dev,
1758                               struct rte_eth_rss_reta_entry64 *reta_conf,
1759                               uint16_t reta_size)
1760 {
1761         struct bnxt *bp = eth_dev->data->dev_private;
1762         struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp);
1763         uint16_t tbl_size = bnxt_rss_hash_tbl_size(bp);
1764         uint16_t idx, sft, i;
1765         int rc;
1766
1767         rc = is_bnxt_in_error(bp);
1768         if (rc)
1769                 return rc;
1770
1771         /* Retrieve from the default VNIC */
1772         if (!vnic)
1773                 return -EINVAL;
1774         if (!vnic->rss_table)
1775                 return -EINVAL;
1776
1777         if (reta_size != tbl_size) {
1778                 PMD_DRV_LOG(ERR, "The configured hash table lookup size "
1779                         "(%d) must equal the size supported by the hardware "
1780                         "(%d)\n", reta_size, tbl_size);
1781                 return -EINVAL;
1782         }
1783
1784         for (idx = 0, i = 0; i < reta_size; i++) {
1785                 idx = i / RTE_RETA_GROUP_SIZE;
1786                 sft = i % RTE_RETA_GROUP_SIZE;
1787
1788                 if (reta_conf[idx].mask & (1ULL << sft)) {
1789                         uint16_t qid;
1790
1791                         if (BNXT_CHIP_THOR(bp))
1792                                 qid = bnxt_rss_to_qid(bp,
1793                                                       vnic->rss_table[i * 2]);
1794                         else
1795                                 qid = bnxt_rss_to_qid(bp, vnic->rss_table[i]);
1796
1797                         if (qid == INVALID_HW_RING_ID) {
1798                                 PMD_DRV_LOG(ERR, "Inv. entry in rss table.\n");
1799                                 return -EINVAL;
1800                         }
1801                         reta_conf[idx].reta[sft] = qid;
1802                 }
1803         }
1804
1805         return 0;
1806 }
1807
1808 static int bnxt_rss_hash_update_op(struct rte_eth_dev *eth_dev,
1809                                    struct rte_eth_rss_conf *rss_conf)
1810 {
1811         struct bnxt *bp = eth_dev->data->dev_private;
1812         struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
1813         struct bnxt_vnic_info *vnic;
1814         int rc;
1815
1816         rc = is_bnxt_in_error(bp);
1817         if (rc)
1818                 return rc;
1819
1820         /*
1821          * If RSS enablement were different than dev_configure,
1822          * then return -EINVAL
1823          */
1824         if (dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG) {
1825                 if (!rss_conf->rss_hf)
1826                         PMD_DRV_LOG(ERR, "Hash type NONE\n");
1827         } else {
1828                 if (rss_conf->rss_hf & BNXT_ETH_RSS_SUPPORT)
1829                         return -EINVAL;
1830         }
1831
1832         bp->flags |= BNXT_FLAG_UPDATE_HASH;
1833         memcpy(&eth_dev->data->dev_conf.rx_adv_conf.rss_conf,
1834                rss_conf,
1835                sizeof(*rss_conf));
1836
1837         /* Update the default RSS VNIC(s) */
1838         vnic = BNXT_GET_DEFAULT_VNIC(bp);
1839         vnic->hash_type = bnxt_rte_to_hwrm_hash_types(rss_conf->rss_hf);
1840
1841         /*
1842          * If hashkey is not specified, use the previously configured
1843          * hashkey
1844          */
1845         if (!rss_conf->rss_key)
1846                 goto rss_config;
1847
1848         if (rss_conf->rss_key_len != HW_HASH_KEY_SIZE) {
1849                 PMD_DRV_LOG(ERR,
1850                             "Invalid hashkey length, should be 16 bytes\n");
1851                 return -EINVAL;
1852         }
1853         memcpy(vnic->rss_hash_key, rss_conf->rss_key, rss_conf->rss_key_len);
1854
1855 rss_config:
1856         bnxt_hwrm_vnic_rss_cfg(bp, vnic);
1857         return 0;
1858 }
1859
1860 static int bnxt_rss_hash_conf_get_op(struct rte_eth_dev *eth_dev,
1861                                      struct rte_eth_rss_conf *rss_conf)
1862 {
1863         struct bnxt *bp = eth_dev->data->dev_private;
1864         struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp);
1865         int len, rc;
1866         uint32_t hash_types;
1867
1868         rc = is_bnxt_in_error(bp);
1869         if (rc)
1870                 return rc;
1871
1872         /* RSS configuration is the same for all VNICs */
1873         if (vnic && vnic->rss_hash_key) {
1874                 if (rss_conf->rss_key) {
1875                         len = rss_conf->rss_key_len <= HW_HASH_KEY_SIZE ?
1876                               rss_conf->rss_key_len : HW_HASH_KEY_SIZE;
1877                         memcpy(rss_conf->rss_key, vnic->rss_hash_key, len);
1878                 }
1879
1880                 hash_types = vnic->hash_type;
1881                 rss_conf->rss_hf = 0;
1882                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV4) {
1883                         rss_conf->rss_hf |= ETH_RSS_IPV4;
1884                         hash_types &= ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV4;
1885                 }
1886                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV4) {
1887                         rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP;
1888                         hash_types &=
1889                                 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV4;
1890                 }
1891                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV4) {
1892                         rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
1893                         hash_types &=
1894                                 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV4;
1895                 }
1896                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6) {
1897                         rss_conf->rss_hf |= ETH_RSS_IPV6;
1898                         hash_types &= ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6;
1899                 }
1900                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV6) {
1901                         rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV6_TCP;
1902                         hash_types &=
1903                                 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV6;
1904                 }
1905                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV6) {
1906                         rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;
1907                         hash_types &=
1908                                 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV6;
1909                 }
1910                 if (hash_types) {
1911                         PMD_DRV_LOG(ERR,
1912                                 "Unknown RSS config from firmware (%08x), RSS disabled",
1913                                 vnic->hash_type);
1914                         return -ENOTSUP;
1915                 }
1916         } else {
1917                 rss_conf->rss_hf = 0;
1918         }
1919         return 0;
1920 }
1921
1922 static int bnxt_flow_ctrl_get_op(struct rte_eth_dev *dev,
1923                                struct rte_eth_fc_conf *fc_conf)
1924 {
1925         struct bnxt *bp = dev->data->dev_private;
1926         struct rte_eth_link link_info;
1927         int rc;
1928
1929         rc = is_bnxt_in_error(bp);
1930         if (rc)
1931                 return rc;
1932
1933         rc = bnxt_get_hwrm_link_config(bp, &link_info);
1934         if (rc)
1935                 return rc;
1936
1937         memset(fc_conf, 0, sizeof(*fc_conf));
1938         if (bp->link_info->auto_pause)
1939                 fc_conf->autoneg = 1;
1940         switch (bp->link_info->pause) {
1941         case 0:
1942                 fc_conf->mode = RTE_FC_NONE;
1943                 break;
1944         case HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_TX:
1945                 fc_conf->mode = RTE_FC_TX_PAUSE;
1946                 break;
1947         case HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_RX:
1948                 fc_conf->mode = RTE_FC_RX_PAUSE;
1949                 break;
1950         case (HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_TX |
1951                         HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_RX):
1952                 fc_conf->mode = RTE_FC_FULL;
1953                 break;
1954         }
1955         return 0;
1956 }
1957
1958 static int bnxt_flow_ctrl_set_op(struct rte_eth_dev *dev,
1959                                struct rte_eth_fc_conf *fc_conf)
1960 {
1961         struct bnxt *bp = dev->data->dev_private;
1962         int rc;
1963
1964         rc = is_bnxt_in_error(bp);
1965         if (rc)
1966                 return rc;
1967
1968         if (!BNXT_SINGLE_PF(bp) || BNXT_VF(bp)) {
1969                 PMD_DRV_LOG(ERR, "Flow Control Settings cannot be modified\n");
1970                 return -ENOTSUP;
1971         }
1972
1973         switch (fc_conf->mode) {
1974         case RTE_FC_NONE:
1975                 bp->link_info->auto_pause = 0;
1976                 bp->link_info->force_pause = 0;
1977                 break;
1978         case RTE_FC_RX_PAUSE:
1979                 if (fc_conf->autoneg) {
1980                         bp->link_info->auto_pause =
1981                                         HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_RX;
1982                         bp->link_info->force_pause = 0;
1983                 } else {
1984                         bp->link_info->auto_pause = 0;
1985                         bp->link_info->force_pause =
1986                                         HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_RX;
1987                 }
1988                 break;
1989         case RTE_FC_TX_PAUSE:
1990                 if (fc_conf->autoneg) {
1991                         bp->link_info->auto_pause =
1992                                         HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_TX;
1993                         bp->link_info->force_pause = 0;
1994                 } else {
1995                         bp->link_info->auto_pause = 0;
1996                         bp->link_info->force_pause =
1997                                         HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_TX;
1998                 }
1999                 break;
2000         case RTE_FC_FULL:
2001                 if (fc_conf->autoneg) {
2002                         bp->link_info->auto_pause =
2003                                         HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_TX |
2004                                         HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_RX;
2005                         bp->link_info->force_pause = 0;
2006                 } else {
2007                         bp->link_info->auto_pause = 0;
2008                         bp->link_info->force_pause =
2009                                         HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_TX |
2010                                         HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_RX;
2011                 }
2012                 break;
2013         }
2014         return bnxt_set_hwrm_link_config(bp, true);
2015 }
2016
2017 /* Add UDP tunneling port */
2018 static int
2019 bnxt_udp_tunnel_port_add_op(struct rte_eth_dev *eth_dev,
2020                          struct rte_eth_udp_tunnel *udp_tunnel)
2021 {
2022         struct bnxt *bp = eth_dev->data->dev_private;
2023         uint16_t tunnel_type = 0;
2024         int rc = 0;
2025
2026         rc = is_bnxt_in_error(bp);
2027         if (rc)
2028                 return rc;
2029
2030         switch (udp_tunnel->prot_type) {
2031         case RTE_TUNNEL_TYPE_VXLAN:
2032                 if (bp->vxlan_port_cnt) {
2033                         PMD_DRV_LOG(ERR, "Tunnel Port %d already programmed\n",
2034                                 udp_tunnel->udp_port);
2035                         if (bp->vxlan_port != udp_tunnel->udp_port) {
2036                                 PMD_DRV_LOG(ERR, "Only one port allowed\n");
2037                                 return -ENOSPC;
2038                         }
2039                         bp->vxlan_port_cnt++;
2040                         return 0;
2041                 }
2042                 tunnel_type =
2043                         HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_VXLAN;
2044                 bp->vxlan_port_cnt++;
2045                 break;
2046         case RTE_TUNNEL_TYPE_GENEVE:
2047                 if (bp->geneve_port_cnt) {
2048                         PMD_DRV_LOG(ERR, "Tunnel Port %d already programmed\n",
2049                                 udp_tunnel->udp_port);
2050                         if (bp->geneve_port != udp_tunnel->udp_port) {
2051                                 PMD_DRV_LOG(ERR, "Only one port allowed\n");
2052                                 return -ENOSPC;
2053                         }
2054                         bp->geneve_port_cnt++;
2055                         return 0;
2056                 }
2057                 tunnel_type =
2058                         HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_GENEVE;
2059                 bp->geneve_port_cnt++;
2060                 break;
2061         default:
2062                 PMD_DRV_LOG(ERR, "Tunnel type is not supported\n");
2063                 return -ENOTSUP;
2064         }
2065         rc = bnxt_hwrm_tunnel_dst_port_alloc(bp, udp_tunnel->udp_port,
2066                                              tunnel_type);
2067         return rc;
2068 }
2069
2070 static int
2071 bnxt_udp_tunnel_port_del_op(struct rte_eth_dev *eth_dev,
2072                          struct rte_eth_udp_tunnel *udp_tunnel)
2073 {
2074         struct bnxt *bp = eth_dev->data->dev_private;
2075         uint16_t tunnel_type = 0;
2076         uint16_t port = 0;
2077         int rc = 0;
2078
2079         rc = is_bnxt_in_error(bp);
2080         if (rc)
2081                 return rc;
2082
2083         switch (udp_tunnel->prot_type) {
2084         case RTE_TUNNEL_TYPE_VXLAN:
2085                 if (!bp->vxlan_port_cnt) {
2086                         PMD_DRV_LOG(ERR, "No Tunnel port configured yet\n");
2087                         return -EINVAL;
2088                 }
2089                 if (bp->vxlan_port != udp_tunnel->udp_port) {
2090                         PMD_DRV_LOG(ERR, "Req Port: %d. Configured port: %d\n",
2091                                 udp_tunnel->udp_port, bp->vxlan_port);
2092                         return -EINVAL;
2093                 }
2094                 if (--bp->vxlan_port_cnt)
2095                         return 0;
2096
2097                 tunnel_type =
2098                         HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN;
2099                 port = bp->vxlan_fw_dst_port_id;
2100                 break;
2101         case RTE_TUNNEL_TYPE_GENEVE:
2102                 if (!bp->geneve_port_cnt) {
2103                         PMD_DRV_LOG(ERR, "No Tunnel port configured yet\n");
2104                         return -EINVAL;
2105                 }
2106                 if (bp->geneve_port != udp_tunnel->udp_port) {
2107                         PMD_DRV_LOG(ERR, "Req Port: %d. Configured port: %d\n",
2108                                 udp_tunnel->udp_port, bp->geneve_port);
2109                         return -EINVAL;
2110                 }
2111                 if (--bp->geneve_port_cnt)
2112                         return 0;
2113
2114                 tunnel_type =
2115                         HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_GENEVE;
2116                 port = bp->geneve_fw_dst_port_id;
2117                 break;
2118         default:
2119                 PMD_DRV_LOG(ERR, "Tunnel type is not supported\n");
2120                 return -ENOTSUP;
2121         }
2122
2123         rc = bnxt_hwrm_tunnel_dst_port_free(bp, port, tunnel_type);
2124         if (!rc) {
2125                 if (tunnel_type ==
2126                     HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN)
2127                         bp->vxlan_port = 0;
2128                 if (tunnel_type ==
2129                     HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_GENEVE)
2130                         bp->geneve_port = 0;
2131         }
2132         return rc;
2133 }
2134
2135 static int bnxt_del_vlan_filter(struct bnxt *bp, uint16_t vlan_id)
2136 {
2137         struct bnxt_filter_info *filter;
2138         struct bnxt_vnic_info *vnic;
2139         int rc = 0;
2140         uint32_t chk = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN;
2141
2142         vnic = BNXT_GET_DEFAULT_VNIC(bp);
2143         filter = STAILQ_FIRST(&vnic->filter);
2144         while (filter) {
2145                 /* Search for this matching MAC+VLAN filter */
2146                 if (bnxt_vlan_filter_exists(bp, filter, chk, vlan_id)) {
2147                         /* Delete the filter */
2148                         rc = bnxt_hwrm_clear_l2_filter(bp, filter);
2149                         if (rc)
2150                                 return rc;
2151                         STAILQ_REMOVE(&vnic->filter, filter,
2152                                       bnxt_filter_info, next);
2153                         bnxt_free_filter(bp, filter);
2154                         PMD_DRV_LOG(INFO,
2155                                     "Deleted vlan filter for %d\n",
2156                                     vlan_id);
2157                         return 0;
2158                 }
2159                 filter = STAILQ_NEXT(filter, next);
2160         }
2161         return -ENOENT;
2162 }
2163
2164 static int bnxt_add_vlan_filter(struct bnxt *bp, uint16_t vlan_id)
2165 {
2166         struct bnxt_filter_info *filter;
2167         struct bnxt_vnic_info *vnic;
2168         int rc = 0;
2169         uint32_t en = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN |
2170                 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN_MASK;
2171         uint32_t chk = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN;
2172
2173         /* Implementation notes on the use of VNIC in this command:
2174          *
2175          * By default, these filters belong to default vnic for the function.
2176          * Once these filters are set up, only destination VNIC can be modified.
2177          * If the destination VNIC is not specified in this command,
2178          * then the HWRM shall only create an l2 context id.
2179          */
2180
2181         vnic = BNXT_GET_DEFAULT_VNIC(bp);
2182         filter = STAILQ_FIRST(&vnic->filter);
2183         /* Check if the VLAN has already been added */
2184         while (filter) {
2185                 if (bnxt_vlan_filter_exists(bp, filter, chk, vlan_id))
2186                         return -EEXIST;
2187
2188                 filter = STAILQ_NEXT(filter, next);
2189         }
2190
2191         /* No match found. Alloc a fresh filter and issue the L2_FILTER_ALLOC
2192          * command to create MAC+VLAN filter with the right flags, enables set.
2193          */
2194         filter = bnxt_alloc_filter(bp);
2195         if (!filter) {
2196                 PMD_DRV_LOG(ERR,
2197                             "MAC/VLAN filter alloc failed\n");
2198                 return -ENOMEM;
2199         }
2200         /* MAC + VLAN ID filter */
2201         /* If l2_ivlan == 0 and l2_ivlan_mask != 0, only
2202          * untagged packets are received
2203          *
2204          * If l2_ivlan != 0 and l2_ivlan_mask != 0, untagged
2205          * packets and only the programmed vlan's packets are received
2206          */
2207         filter->l2_ivlan = vlan_id;
2208         filter->l2_ivlan_mask = 0x0FFF;
2209         filter->enables |= en;
2210         filter->flags |= HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_OUTERMOST;
2211
2212         rc = bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id, filter);
2213         if (rc) {
2214                 /* Free the newly allocated filter as we were
2215                  * not able to create the filter in hardware.
2216                  */
2217                 bnxt_free_filter(bp, filter);
2218                 return rc;
2219         }
2220
2221         filter->mac_index = 0;
2222         /* Add this new filter to the list */
2223         if (vlan_id == 0)
2224                 STAILQ_INSERT_HEAD(&vnic->filter, filter, next);
2225         else
2226                 STAILQ_INSERT_TAIL(&vnic->filter, filter, next);
2227
2228         PMD_DRV_LOG(INFO,
2229                     "Added Vlan filter for %d\n", vlan_id);
2230         return rc;
2231 }
2232
2233 static int bnxt_vlan_filter_set_op(struct rte_eth_dev *eth_dev,
2234                 uint16_t vlan_id, int on)
2235 {
2236         struct bnxt *bp = eth_dev->data->dev_private;
2237         int rc;
2238
2239         rc = is_bnxt_in_error(bp);
2240         if (rc)
2241                 return rc;
2242
2243         if (!eth_dev->data->dev_started) {
2244                 PMD_DRV_LOG(ERR, "port must be started before setting vlan\n");
2245                 return -EINVAL;
2246         }
2247
2248         /* These operations apply to ALL existing MAC/VLAN filters */
2249         if (on)
2250                 return bnxt_add_vlan_filter(bp, vlan_id);
2251         else
2252                 return bnxt_del_vlan_filter(bp, vlan_id);
2253 }
2254
2255 static int bnxt_del_dflt_mac_filter(struct bnxt *bp,
2256                                     struct bnxt_vnic_info *vnic)
2257 {
2258         struct bnxt_filter_info *filter;
2259         int rc;
2260
2261         filter = STAILQ_FIRST(&vnic->filter);
2262         while (filter) {
2263                 if (filter->mac_index == 0 &&
2264                     !memcmp(filter->l2_addr, bp->mac_addr,
2265                             RTE_ETHER_ADDR_LEN)) {
2266                         rc = bnxt_hwrm_clear_l2_filter(bp, filter);
2267                         if (!rc) {
2268                                 STAILQ_REMOVE(&vnic->filter, filter,
2269                                               bnxt_filter_info, next);
2270                                 bnxt_free_filter(bp, filter);
2271                         }
2272                         return rc;
2273                 }
2274                 filter = STAILQ_NEXT(filter, next);
2275         }
2276         return 0;
2277 }
2278
2279 static int
2280 bnxt_config_vlan_hw_filter(struct bnxt *bp, uint64_t rx_offloads)
2281 {
2282         struct bnxt_vnic_info *vnic;
2283         unsigned int i;
2284         int rc;
2285
2286         vnic = BNXT_GET_DEFAULT_VNIC(bp);
2287         if (!(rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER)) {
2288                 /* Remove any VLAN filters programmed */
2289                 for (i = 0; i < RTE_ETHER_MAX_VLAN_ID; i++)
2290                         bnxt_del_vlan_filter(bp, i);
2291
2292                 rc = bnxt_add_mac_filter(bp, vnic, NULL, 0, 0);
2293                 if (rc)
2294                         return rc;
2295         } else {
2296                 /* Default filter will allow packets that match the
2297                  * dest mac. So, it has to be deleted, otherwise, we
2298                  * will endup receiving vlan packets for which the
2299                  * filter is not programmed, when hw-vlan-filter
2300                  * configuration is ON
2301                  */
2302                 bnxt_del_dflt_mac_filter(bp, vnic);
2303                 /* This filter will allow only untagged packets */
2304                 bnxt_add_vlan_filter(bp, 0);
2305         }
2306         PMD_DRV_LOG(DEBUG, "VLAN Filtering: %d\n",
2307                     !!(rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER));
2308
2309         return 0;
2310 }
2311
2312 static int bnxt_free_one_vnic(struct bnxt *bp, uint16_t vnic_id)
2313 {
2314         struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id];
2315         unsigned int i;
2316         int rc;
2317
2318         /* Destroy vnic filters and vnic */
2319         if (bp->eth_dev->data->dev_conf.rxmode.offloads &
2320             DEV_RX_OFFLOAD_VLAN_FILTER) {
2321                 for (i = 0; i < RTE_ETHER_MAX_VLAN_ID; i++)
2322                         bnxt_del_vlan_filter(bp, i);
2323         }
2324         bnxt_del_dflt_mac_filter(bp, vnic);
2325
2326         rc = bnxt_hwrm_vnic_free(bp, vnic);
2327         if (rc)
2328                 return rc;
2329
2330         rte_free(vnic->fw_grp_ids);
2331         vnic->fw_grp_ids = NULL;
2332
2333         vnic->rx_queue_cnt = 0;
2334
2335         return 0;
2336 }
2337
2338 static int
2339 bnxt_config_vlan_hw_stripping(struct bnxt *bp, uint64_t rx_offloads)
2340 {
2341         struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp);
2342         int rc;
2343
2344         /* Destroy, recreate and reconfigure the default vnic */
2345         rc = bnxt_free_one_vnic(bp, 0);
2346         if (rc)
2347                 return rc;
2348
2349         /* default vnic 0 */
2350         rc = bnxt_setup_one_vnic(bp, 0);
2351         if (rc)
2352                 return rc;
2353
2354         if (bp->eth_dev->data->dev_conf.rxmode.offloads &
2355             DEV_RX_OFFLOAD_VLAN_FILTER) {
2356                 rc = bnxt_add_vlan_filter(bp, 0);
2357                 if (rc)
2358                         return rc;
2359                 rc = bnxt_restore_vlan_filters(bp);
2360                 if (rc)
2361                         return rc;
2362         } else {
2363                 rc = bnxt_add_mac_filter(bp, vnic, NULL, 0, 0);
2364                 if (rc)
2365                         return rc;
2366         }
2367
2368         rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
2369         if (rc)
2370                 return rc;
2371
2372         PMD_DRV_LOG(DEBUG, "VLAN Strip Offload: %d\n",
2373                     !!(rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP));
2374
2375         return rc;
2376 }
2377
2378 static int
2379 bnxt_vlan_offload_set_op(struct rte_eth_dev *dev, int mask)
2380 {
2381         uint64_t rx_offloads = dev->data->dev_conf.rxmode.offloads;
2382         struct bnxt *bp = dev->data->dev_private;
2383         int rc;
2384
2385         rc = is_bnxt_in_error(bp);
2386         if (rc)
2387                 return rc;
2388
2389         /* Filter settings will get applied when port is started */
2390         if (!dev->data->dev_started)
2391                 return 0;
2392
2393         if (mask & ETH_VLAN_FILTER_MASK) {
2394                 /* Enable or disable VLAN filtering */
2395                 rc = bnxt_config_vlan_hw_filter(bp, rx_offloads);
2396                 if (rc)
2397                         return rc;
2398         }
2399
2400         if (mask & ETH_VLAN_STRIP_MASK) {
2401                 /* Enable or disable VLAN stripping */
2402                 rc = bnxt_config_vlan_hw_stripping(bp, rx_offloads);
2403                 if (rc)
2404                         return rc;
2405         }
2406
2407         if (mask & ETH_VLAN_EXTEND_MASK) {
2408                 if (rx_offloads & DEV_RX_OFFLOAD_VLAN_EXTEND)
2409                         PMD_DRV_LOG(DEBUG, "Extend VLAN supported\n");
2410                 else
2411                         PMD_DRV_LOG(INFO, "Extend VLAN unsupported\n");
2412         }
2413
2414         return 0;
2415 }
2416
2417 static int
2418 bnxt_vlan_tpid_set_op(struct rte_eth_dev *dev, enum rte_vlan_type vlan_type,
2419                       uint16_t tpid)
2420 {
2421         struct bnxt *bp = dev->data->dev_private;
2422         int qinq = dev->data->dev_conf.rxmode.offloads &
2423                    DEV_RX_OFFLOAD_VLAN_EXTEND;
2424
2425         if (vlan_type != ETH_VLAN_TYPE_INNER &&
2426             vlan_type != ETH_VLAN_TYPE_OUTER) {
2427                 PMD_DRV_LOG(ERR,
2428                             "Unsupported vlan type.");
2429                 return -EINVAL;
2430         }
2431         if (!qinq) {
2432                 PMD_DRV_LOG(ERR,
2433                             "QinQ not enabled. Needs to be ON as we can "
2434                             "accelerate only outer vlan\n");
2435                 return -EINVAL;
2436         }
2437
2438         if (vlan_type == ETH_VLAN_TYPE_OUTER) {
2439                 switch (tpid) {
2440                 case RTE_ETHER_TYPE_QINQ:
2441                         bp->outer_tpid_bd =
2442                                 TX_BD_LONG_CFA_META_VLAN_TPID_TPID88A8;
2443                                 break;
2444                 case RTE_ETHER_TYPE_VLAN:
2445                         bp->outer_tpid_bd =
2446                                 TX_BD_LONG_CFA_META_VLAN_TPID_TPID8100;
2447                                 break;
2448                 case RTE_ETHER_TYPE_QINQ1:
2449                         bp->outer_tpid_bd =
2450                                 TX_BD_LONG_CFA_META_VLAN_TPID_TPID9100;
2451                                 break;
2452                 case RTE_ETHER_TYPE_QINQ2:
2453                         bp->outer_tpid_bd =
2454                                 TX_BD_LONG_CFA_META_VLAN_TPID_TPID9200;
2455                                 break;
2456                 case RTE_ETHER_TYPE_QINQ3:
2457                         bp->outer_tpid_bd =
2458                                  TX_BD_LONG_CFA_META_VLAN_TPID_TPID9300;
2459                                 break;
2460                 default:
2461                         PMD_DRV_LOG(ERR, "Invalid TPID: %x\n", tpid);
2462                         return -EINVAL;
2463                 }
2464                 bp->outer_tpid_bd |= tpid;
2465                 PMD_DRV_LOG(INFO, "outer_tpid_bd = %x\n", bp->outer_tpid_bd);
2466         } else if (vlan_type == ETH_VLAN_TYPE_INNER) {
2467                 PMD_DRV_LOG(ERR,
2468                             "Can accelerate only outer vlan in QinQ\n");
2469                 return -EINVAL;
2470         }
2471
2472         return 0;
2473 }
2474
2475 static int
2476 bnxt_set_default_mac_addr_op(struct rte_eth_dev *dev,
2477                              struct rte_ether_addr *addr)
2478 {
2479         struct bnxt *bp = dev->data->dev_private;
2480         /* Default Filter is tied to VNIC 0 */
2481         struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp);
2482         int rc;
2483
2484         rc = is_bnxt_in_error(bp);
2485         if (rc)
2486                 return rc;
2487
2488         if (BNXT_VF(bp) && !BNXT_VF_IS_TRUSTED(bp))
2489                 return -EPERM;
2490
2491         if (rte_is_zero_ether_addr(addr))
2492                 return -EINVAL;
2493
2494         /* Filter settings will get applied when port is started */
2495         if (!dev->data->dev_started)
2496                 return 0;
2497
2498         /* Check if the requested MAC is already added */
2499         if (memcmp(addr, bp->mac_addr, RTE_ETHER_ADDR_LEN) == 0)
2500                 return 0;
2501
2502         /* Destroy filter and re-create it */
2503         bnxt_del_dflt_mac_filter(bp, vnic);
2504
2505         memcpy(bp->mac_addr, addr, RTE_ETHER_ADDR_LEN);
2506         if (dev->data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_VLAN_FILTER) {
2507                 /* This filter will allow only untagged packets */
2508                 rc = bnxt_add_vlan_filter(bp, 0);
2509         } else {
2510                 rc = bnxt_add_mac_filter(bp, vnic, addr, 0, 0);
2511         }
2512
2513         PMD_DRV_LOG(DEBUG, "Set MAC addr\n");
2514         return rc;
2515 }
2516
2517 static int
2518 bnxt_dev_set_mc_addr_list_op(struct rte_eth_dev *eth_dev,
2519                           struct rte_ether_addr *mc_addr_set,
2520                           uint32_t nb_mc_addr)
2521 {
2522         struct bnxt *bp = eth_dev->data->dev_private;
2523         char *mc_addr_list = (char *)mc_addr_set;
2524         struct bnxt_vnic_info *vnic;
2525         uint32_t off = 0, i = 0;
2526         int rc;
2527
2528         rc = is_bnxt_in_error(bp);
2529         if (rc)
2530                 return rc;
2531
2532         vnic = BNXT_GET_DEFAULT_VNIC(bp);
2533
2534         if (nb_mc_addr > BNXT_MAX_MC_ADDRS) {
2535                 vnic->flags |= BNXT_VNIC_INFO_ALLMULTI;
2536                 goto allmulti;
2537         }
2538
2539         /* TODO Check for Duplicate mcast addresses */
2540         vnic->flags &= ~BNXT_VNIC_INFO_ALLMULTI;
2541         for (i = 0; i < nb_mc_addr; i++) {
2542                 memcpy(vnic->mc_list + off, &mc_addr_list[i],
2543                         RTE_ETHER_ADDR_LEN);
2544                 off += RTE_ETHER_ADDR_LEN;
2545         }
2546
2547         vnic->mc_addr_cnt = i;
2548         if (vnic->mc_addr_cnt)
2549                 vnic->flags |= BNXT_VNIC_INFO_MCAST;
2550         else
2551                 vnic->flags &= ~BNXT_VNIC_INFO_MCAST;
2552
2553 allmulti:
2554         return bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
2555 }
2556
2557 static int
2558 bnxt_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size)
2559 {
2560         struct bnxt *bp = dev->data->dev_private;
2561         uint8_t fw_major = (bp->fw_ver >> 24) & 0xff;
2562         uint8_t fw_minor = (bp->fw_ver >> 16) & 0xff;
2563         uint8_t fw_updt = (bp->fw_ver >> 8) & 0xff;
2564         uint8_t fw_rsvd = bp->fw_ver & 0xff;
2565         int ret;
2566
2567         ret = snprintf(fw_version, fw_size, "%d.%d.%d.%d",
2568                         fw_major, fw_minor, fw_updt, fw_rsvd);
2569
2570         ret += 1; /* add the size of '\0' */
2571         if (fw_size < (uint32_t)ret)
2572                 return ret;
2573         else
2574                 return 0;
2575 }
2576
2577 static void
2578 bnxt_rxq_info_get_op(struct rte_eth_dev *dev, uint16_t queue_id,
2579         struct rte_eth_rxq_info *qinfo)
2580 {
2581         struct bnxt *bp = dev->data->dev_private;
2582         struct bnxt_rx_queue *rxq;
2583
2584         if (is_bnxt_in_error(bp))
2585                 return;
2586
2587         rxq = dev->data->rx_queues[queue_id];
2588
2589         qinfo->mp = rxq->mb_pool;
2590         qinfo->scattered_rx = dev->data->scattered_rx;
2591         qinfo->nb_desc = rxq->nb_rx_desc;
2592
2593         qinfo->conf.rx_free_thresh = rxq->rx_free_thresh;
2594         qinfo->conf.rx_drop_en = 0;
2595         qinfo->conf.rx_deferred_start = rxq->rx_deferred_start;
2596 }
2597
2598 static void
2599 bnxt_txq_info_get_op(struct rte_eth_dev *dev, uint16_t queue_id,
2600         struct rte_eth_txq_info *qinfo)
2601 {
2602         struct bnxt *bp = dev->data->dev_private;
2603         struct bnxt_tx_queue *txq;
2604
2605         if (is_bnxt_in_error(bp))
2606                 return;
2607
2608         txq = dev->data->tx_queues[queue_id];
2609
2610         qinfo->nb_desc = txq->nb_tx_desc;
2611
2612         qinfo->conf.tx_thresh.pthresh = txq->pthresh;
2613         qinfo->conf.tx_thresh.hthresh = txq->hthresh;
2614         qinfo->conf.tx_thresh.wthresh = txq->wthresh;
2615
2616         qinfo->conf.tx_free_thresh = txq->tx_free_thresh;
2617         qinfo->conf.tx_rs_thresh = 0;
2618         qinfo->conf.tx_deferred_start = txq->tx_deferred_start;
2619 }
2620
2621 static const struct {
2622         eth_rx_burst_t pkt_burst;
2623         const char *info;
2624 } bnxt_rx_burst_info[] = {
2625         {bnxt_recv_pkts,        "Scalar"},
2626 #if defined(RTE_ARCH_X86)
2627         {bnxt_recv_pkts_vec,    "Vector SSE"},
2628 #elif defined(RTE_ARCH_ARM64)
2629         {bnxt_recv_pkts_vec,    "Vector Neon"},
2630 #endif
2631 };
2632
2633 static int
2634 bnxt_rx_burst_mode_get(struct rte_eth_dev *dev, __rte_unused uint16_t queue_id,
2635                        struct rte_eth_burst_mode *mode)
2636 {
2637         eth_rx_burst_t pkt_burst = dev->rx_pkt_burst;
2638         size_t i;
2639
2640         for (i = 0; i < RTE_DIM(bnxt_rx_burst_info); i++) {
2641                 if (pkt_burst == bnxt_rx_burst_info[i].pkt_burst) {
2642                         snprintf(mode->info, sizeof(mode->info), "%s",
2643                                  bnxt_rx_burst_info[i].info);
2644                         return 0;
2645                 }
2646         }
2647
2648         return -EINVAL;
2649 }
2650
2651 static const struct {
2652         eth_tx_burst_t pkt_burst;
2653         const char *info;
2654 } bnxt_tx_burst_info[] = {
2655         {bnxt_xmit_pkts,        "Scalar"},
2656 #if defined(RTE_ARCH_X86)
2657         {bnxt_xmit_pkts_vec,    "Vector SSE"},
2658 #elif defined(RTE_ARCH_ARM64)
2659         {bnxt_xmit_pkts_vec,    "Vector Neon"},
2660 #endif
2661 };
2662
2663 static int
2664 bnxt_tx_burst_mode_get(struct rte_eth_dev *dev, __rte_unused uint16_t queue_id,
2665                        struct rte_eth_burst_mode *mode)
2666 {
2667         eth_tx_burst_t pkt_burst = dev->tx_pkt_burst;
2668         size_t i;
2669
2670         for (i = 0; i < RTE_DIM(bnxt_tx_burst_info); i++) {
2671                 if (pkt_burst == bnxt_tx_burst_info[i].pkt_burst) {
2672                         snprintf(mode->info, sizeof(mode->info), "%s",
2673                                  bnxt_tx_burst_info[i].info);
2674                         return 0;
2675                 }
2676         }
2677
2678         return -EINVAL;
2679 }
2680
2681 int bnxt_mtu_set_op(struct rte_eth_dev *eth_dev, uint16_t new_mtu)
2682 {
2683         struct bnxt *bp = eth_dev->data->dev_private;
2684         uint32_t new_pkt_size;
2685         uint32_t rc = 0;
2686         uint32_t i;
2687
2688         rc = is_bnxt_in_error(bp);
2689         if (rc)
2690                 return rc;
2691
2692         /* Exit if receive queues are not configured yet */
2693         if (!eth_dev->data->nb_rx_queues)
2694                 return rc;
2695
2696         new_pkt_size = new_mtu + RTE_ETHER_HDR_LEN + RTE_ETHER_CRC_LEN +
2697                        VLAN_TAG_SIZE * BNXT_NUM_VLANS;
2698
2699         /*
2700          * Disallow any MTU change that would require scattered receive support
2701          * if it is not already enabled.
2702          */
2703         if (eth_dev->data->dev_started &&
2704             !eth_dev->data->scattered_rx &&
2705             (new_pkt_size >
2706              eth_dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM)) {
2707                 PMD_DRV_LOG(ERR,
2708                             "MTU change would require scattered rx support. ");
2709                 PMD_DRV_LOG(ERR, "Stop port before changing MTU.\n");
2710                 return -EINVAL;
2711         }
2712
2713         if (new_mtu > RTE_ETHER_MTU) {
2714                 bp->flags |= BNXT_FLAG_JUMBO;
2715                 bp->eth_dev->data->dev_conf.rxmode.offloads |=
2716                         DEV_RX_OFFLOAD_JUMBO_FRAME;
2717         } else {
2718                 bp->eth_dev->data->dev_conf.rxmode.offloads &=
2719                         ~DEV_RX_OFFLOAD_JUMBO_FRAME;
2720                 bp->flags &= ~BNXT_FLAG_JUMBO;
2721         }
2722
2723         /* Is there a change in mtu setting? */
2724         if (eth_dev->data->dev_conf.rxmode.max_rx_pkt_len == new_pkt_size)
2725                 return rc;
2726
2727         for (i = 0; i < bp->nr_vnics; i++) {
2728                 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
2729                 uint16_t size = 0;
2730
2731                 vnic->mru = BNXT_VNIC_MRU(new_mtu);
2732                 rc = bnxt_hwrm_vnic_cfg(bp, vnic);
2733                 if (rc)
2734                         break;
2735
2736                 size = rte_pktmbuf_data_room_size(bp->rx_queues[0]->mb_pool);
2737                 size -= RTE_PKTMBUF_HEADROOM;
2738
2739                 if (size < new_mtu) {
2740                         rc = bnxt_hwrm_vnic_plcmode_cfg(bp, vnic);
2741                         if (rc)
2742                                 return rc;
2743                 }
2744         }
2745
2746         if (!rc)
2747                 eth_dev->data->dev_conf.rxmode.max_rx_pkt_len = new_pkt_size;
2748
2749         PMD_DRV_LOG(INFO, "New MTU is %d\n", new_mtu);
2750
2751         return rc;
2752 }
2753
2754 static int
2755 bnxt_vlan_pvid_set_op(struct rte_eth_dev *dev, uint16_t pvid, int on)
2756 {
2757         struct bnxt *bp = dev->data->dev_private;
2758         uint16_t vlan = bp->vlan;
2759         int rc;
2760
2761         rc = is_bnxt_in_error(bp);
2762         if (rc)
2763                 return rc;
2764
2765         if (!BNXT_SINGLE_PF(bp) || BNXT_VF(bp)) {
2766                 PMD_DRV_LOG(ERR,
2767                         "PVID cannot be modified for this function\n");
2768                 return -ENOTSUP;
2769         }
2770         bp->vlan = on ? pvid : 0;
2771
2772         rc = bnxt_hwrm_set_default_vlan(bp, 0, 0);
2773         if (rc)
2774                 bp->vlan = vlan;
2775         return rc;
2776 }
2777
2778 static int
2779 bnxt_dev_led_on_op(struct rte_eth_dev *dev)
2780 {
2781         struct bnxt *bp = dev->data->dev_private;
2782         int rc;
2783
2784         rc = is_bnxt_in_error(bp);
2785         if (rc)
2786                 return rc;
2787
2788         return bnxt_hwrm_port_led_cfg(bp, true);
2789 }
2790
2791 static int
2792 bnxt_dev_led_off_op(struct rte_eth_dev *dev)
2793 {
2794         struct bnxt *bp = dev->data->dev_private;
2795         int rc;
2796
2797         rc = is_bnxt_in_error(bp);
2798         if (rc)
2799                 return rc;
2800
2801         return bnxt_hwrm_port_led_cfg(bp, false);
2802 }
2803
2804 static uint32_t
2805 bnxt_rx_queue_count_op(struct rte_eth_dev *dev, uint16_t rx_queue_id)
2806 {
2807         struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
2808         uint32_t desc = 0, raw_cons = 0, cons;
2809         struct bnxt_cp_ring_info *cpr;
2810         struct bnxt_rx_queue *rxq;
2811         struct rx_pkt_cmpl *rxcmp;
2812         int rc;
2813
2814         rc = is_bnxt_in_error(bp);
2815         if (rc)
2816                 return rc;
2817
2818         rxq = dev->data->rx_queues[rx_queue_id];
2819         cpr = rxq->cp_ring;
2820         raw_cons = cpr->cp_raw_cons;
2821
2822         while (1) {
2823                 cons = RING_CMP(cpr->cp_ring_struct, raw_cons);
2824                 rte_prefetch0(&cpr->cp_desc_ring[cons]);
2825                 rxcmp = (struct rx_pkt_cmpl *)&cpr->cp_desc_ring[cons];
2826
2827                 if (!CMP_VALID(rxcmp, raw_cons, cpr->cp_ring_struct)) {
2828                         break;
2829                 } else {
2830                         raw_cons++;
2831                         desc++;
2832                 }
2833         }
2834
2835         return desc;
2836 }
2837
2838 static int
2839 bnxt_rx_descriptor_status_op(void *rx_queue, uint16_t offset)
2840 {
2841         struct bnxt_rx_queue *rxq = (struct bnxt_rx_queue *)rx_queue;
2842         struct bnxt_rx_ring_info *rxr;
2843         struct bnxt_cp_ring_info *cpr;
2844         struct rte_mbuf *rx_buf;
2845         struct rx_pkt_cmpl *rxcmp;
2846         uint32_t cons, cp_cons;
2847         int rc;
2848
2849         if (!rxq)
2850                 return -EINVAL;
2851
2852         rc = is_bnxt_in_error(rxq->bp);
2853         if (rc)
2854                 return rc;
2855
2856         cpr = rxq->cp_ring;
2857         rxr = rxq->rx_ring;
2858
2859         if (offset >= rxq->nb_rx_desc)
2860                 return -EINVAL;
2861
2862         cons = RING_CMP(cpr->cp_ring_struct, offset);
2863         cp_cons = cpr->cp_raw_cons;
2864         rxcmp = (struct rx_pkt_cmpl *)&cpr->cp_desc_ring[cons];
2865
2866         if (cons > cp_cons) {
2867                 if (CMPL_VALID(rxcmp, cpr->valid))
2868                         return RTE_ETH_RX_DESC_DONE;
2869         } else {
2870                 if (CMPL_VALID(rxcmp, !cpr->valid))
2871                         return RTE_ETH_RX_DESC_DONE;
2872         }
2873         rx_buf = rxr->rx_buf_ring[cons];
2874         if (rx_buf == NULL || rx_buf == &rxq->fake_mbuf)
2875                 return RTE_ETH_RX_DESC_UNAVAIL;
2876
2877
2878         return RTE_ETH_RX_DESC_AVAIL;
2879 }
2880
2881 static int
2882 bnxt_tx_descriptor_status_op(void *tx_queue, uint16_t offset)
2883 {
2884         struct bnxt_tx_queue *txq = (struct bnxt_tx_queue *)tx_queue;
2885         struct bnxt_tx_ring_info *txr;
2886         struct bnxt_cp_ring_info *cpr;
2887         struct bnxt_sw_tx_bd *tx_buf;
2888         struct tx_pkt_cmpl *txcmp;
2889         uint32_t cons, cp_cons;
2890         int rc;
2891
2892         if (!txq)
2893                 return -EINVAL;
2894
2895         rc = is_bnxt_in_error(txq->bp);
2896         if (rc)
2897                 return rc;
2898
2899         cpr = txq->cp_ring;
2900         txr = txq->tx_ring;
2901
2902         if (offset >= txq->nb_tx_desc)
2903                 return -EINVAL;
2904
2905         cons = RING_CMP(cpr->cp_ring_struct, offset);
2906         txcmp = (struct tx_pkt_cmpl *)&cpr->cp_desc_ring[cons];
2907         cp_cons = cpr->cp_raw_cons;
2908
2909         if (cons > cp_cons) {
2910                 if (CMPL_VALID(txcmp, cpr->valid))
2911                         return RTE_ETH_TX_DESC_UNAVAIL;
2912         } else {
2913                 if (CMPL_VALID(txcmp, !cpr->valid))
2914                         return RTE_ETH_TX_DESC_UNAVAIL;
2915         }
2916         tx_buf = &txr->tx_buf_ring[cons];
2917         if (tx_buf->mbuf == NULL)
2918                 return RTE_ETH_TX_DESC_DONE;
2919
2920         return RTE_ETH_TX_DESC_FULL;
2921 }
2922
2923 static struct bnxt_filter_info *
2924 bnxt_match_and_validate_ether_filter(struct bnxt *bp,
2925                                 struct rte_eth_ethertype_filter *efilter,
2926                                 struct bnxt_vnic_info *vnic0,
2927                                 struct bnxt_vnic_info *vnic,
2928                                 int *ret)
2929 {
2930         struct bnxt_filter_info *mfilter = NULL;
2931         int match = 0;
2932         *ret = 0;
2933
2934         if (efilter->ether_type == RTE_ETHER_TYPE_IPV4 ||
2935                 efilter->ether_type == RTE_ETHER_TYPE_IPV6) {
2936                 PMD_DRV_LOG(ERR, "invalid ether_type(0x%04x) in"
2937                         " ethertype filter.", efilter->ether_type);
2938                 *ret = -EINVAL;
2939                 goto exit;
2940         }
2941         if (efilter->queue >= bp->rx_nr_rings) {
2942                 PMD_DRV_LOG(ERR, "Invalid queue %d\n", efilter->queue);
2943                 *ret = -EINVAL;
2944                 goto exit;
2945         }
2946
2947         vnic0 = BNXT_GET_DEFAULT_VNIC(bp);
2948         vnic = &bp->vnic_info[efilter->queue];
2949         if (vnic == NULL) {
2950                 PMD_DRV_LOG(ERR, "Invalid queue %d\n", efilter->queue);
2951                 *ret = -EINVAL;
2952                 goto exit;
2953         }
2954
2955         if (efilter->flags & RTE_ETHTYPE_FLAGS_DROP) {
2956                 STAILQ_FOREACH(mfilter, &vnic0->filter, next) {
2957                         if ((!memcmp(efilter->mac_addr.addr_bytes,
2958                                      mfilter->l2_addr, RTE_ETHER_ADDR_LEN) &&
2959                              mfilter->flags ==
2960                              HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_DROP &&
2961                              mfilter->ethertype == efilter->ether_type)) {
2962                                 match = 1;
2963                                 break;
2964                         }
2965                 }
2966         } else {
2967                 STAILQ_FOREACH(mfilter, &vnic->filter, next)
2968                         if ((!memcmp(efilter->mac_addr.addr_bytes,
2969                                      mfilter->l2_addr, RTE_ETHER_ADDR_LEN) &&
2970                              mfilter->ethertype == efilter->ether_type &&
2971                              mfilter->flags ==
2972                              HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_PATH_RX)) {
2973                                 match = 1;
2974                                 break;
2975                         }
2976         }
2977
2978         if (match)
2979                 *ret = -EEXIST;
2980
2981 exit:
2982         return mfilter;
2983 }
2984
2985 static int
2986 bnxt_ethertype_filter(struct rte_eth_dev *dev,
2987                         enum rte_filter_op filter_op,
2988                         void *arg)
2989 {
2990         struct bnxt *bp = dev->data->dev_private;
2991         struct rte_eth_ethertype_filter *efilter =
2992                         (struct rte_eth_ethertype_filter *)arg;
2993         struct bnxt_filter_info *bfilter, *filter1;
2994         struct bnxt_vnic_info *vnic, *vnic0;
2995         int ret;
2996
2997         if (filter_op == RTE_ETH_FILTER_NOP)
2998                 return 0;
2999
3000         if (arg == NULL) {
3001                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
3002                             filter_op);
3003                 return -EINVAL;
3004         }
3005
3006         vnic0 = BNXT_GET_DEFAULT_VNIC(bp);
3007         vnic = &bp->vnic_info[efilter->queue];
3008
3009         switch (filter_op) {
3010         case RTE_ETH_FILTER_ADD:
3011                 bnxt_match_and_validate_ether_filter(bp, efilter,
3012                                                         vnic0, vnic, &ret);
3013                 if (ret < 0)
3014                         return ret;
3015
3016                 bfilter = bnxt_get_unused_filter(bp);
3017                 if (bfilter == NULL) {
3018                         PMD_DRV_LOG(ERR,
3019                                 "Not enough resources for a new filter.\n");
3020                         return -ENOMEM;
3021                 }
3022                 bfilter->filter_type = HWRM_CFA_NTUPLE_FILTER;
3023                 memcpy(bfilter->l2_addr, efilter->mac_addr.addr_bytes,
3024                        RTE_ETHER_ADDR_LEN);
3025                 memcpy(bfilter->dst_macaddr, efilter->mac_addr.addr_bytes,
3026                        RTE_ETHER_ADDR_LEN);
3027                 bfilter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_MACADDR;
3028                 bfilter->ethertype = efilter->ether_type;
3029                 bfilter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
3030
3031                 filter1 = bnxt_get_l2_filter(bp, bfilter, vnic0);
3032                 if (filter1 == NULL) {
3033                         ret = -EINVAL;
3034                         goto cleanup;
3035                 }
3036                 bfilter->enables |=
3037                         HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID;
3038                 bfilter->fw_l2_filter_id = filter1->fw_l2_filter_id;
3039
3040                 bfilter->dst_id = vnic->fw_vnic_id;
3041
3042                 if (efilter->flags & RTE_ETHTYPE_FLAGS_DROP) {
3043                         bfilter->flags =
3044                                 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_DROP;
3045                 }
3046
3047                 ret = bnxt_hwrm_set_ntuple_filter(bp, bfilter->dst_id, bfilter);
3048                 if (ret)
3049                         goto cleanup;
3050                 STAILQ_INSERT_TAIL(&vnic->filter, bfilter, next);
3051                 break;
3052         case RTE_ETH_FILTER_DELETE:
3053                 filter1 = bnxt_match_and_validate_ether_filter(bp, efilter,
3054                                                         vnic0, vnic, &ret);
3055                 if (ret == -EEXIST) {
3056                         ret = bnxt_hwrm_clear_ntuple_filter(bp, filter1);
3057
3058                         STAILQ_REMOVE(&vnic->filter, filter1, bnxt_filter_info,
3059                                       next);
3060                         bnxt_free_filter(bp, filter1);
3061                 } else if (ret == 0) {
3062                         PMD_DRV_LOG(ERR, "No matching filter found\n");
3063                 }
3064                 break;
3065         default:
3066                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
3067                 ret = -EINVAL;
3068                 goto error;
3069         }
3070         return ret;
3071 cleanup:
3072         bnxt_free_filter(bp, bfilter);
3073 error:
3074         return ret;
3075 }
3076
3077 static inline int
3078 parse_ntuple_filter(struct bnxt *bp,
3079                     struct rte_eth_ntuple_filter *nfilter,
3080                     struct bnxt_filter_info *bfilter)
3081 {
3082         uint32_t en = 0;
3083
3084         if (nfilter->queue >= bp->rx_nr_rings) {
3085                 PMD_DRV_LOG(ERR, "Invalid queue %d\n", nfilter->queue);
3086                 return -EINVAL;
3087         }
3088
3089         switch (nfilter->dst_port_mask) {
3090         case UINT16_MAX:
3091                 bfilter->dst_port_mask = -1;
3092                 bfilter->dst_port = nfilter->dst_port;
3093                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT |
3094                         NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
3095                 break;
3096         default:
3097                 PMD_DRV_LOG(ERR, "invalid dst_port mask.");
3098                 return -EINVAL;
3099         }
3100
3101         bfilter->ip_addr_type = NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4;
3102         en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
3103
3104         switch (nfilter->proto_mask) {
3105         case UINT8_MAX:
3106                 if (nfilter->proto == 17) /* IPPROTO_UDP */
3107                         bfilter->ip_protocol = 17;
3108                 else if (nfilter->proto == 6) /* IPPROTO_TCP */
3109                         bfilter->ip_protocol = 6;
3110                 else
3111                         return -EINVAL;
3112                 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
3113                 break;
3114         default:
3115                 PMD_DRV_LOG(ERR, "invalid protocol mask.");
3116                 return -EINVAL;
3117         }
3118
3119         switch (nfilter->dst_ip_mask) {
3120         case UINT32_MAX:
3121                 bfilter->dst_ipaddr_mask[0] = -1;
3122                 bfilter->dst_ipaddr[0] = nfilter->dst_ip;
3123                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR |
3124                         NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
3125                 break;
3126         default:
3127                 PMD_DRV_LOG(ERR, "invalid dst_ip mask.");
3128                 return -EINVAL;
3129         }
3130
3131         switch (nfilter->src_ip_mask) {
3132         case UINT32_MAX:
3133                 bfilter->src_ipaddr_mask[0] = -1;
3134                 bfilter->src_ipaddr[0] = nfilter->src_ip;
3135                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR |
3136                         NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
3137                 break;
3138         default:
3139                 PMD_DRV_LOG(ERR, "invalid src_ip mask.");
3140                 return -EINVAL;
3141         }
3142
3143         switch (nfilter->src_port_mask) {
3144         case UINT16_MAX:
3145                 bfilter->src_port_mask = -1;
3146                 bfilter->src_port = nfilter->src_port;
3147                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT |
3148                         NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
3149                 break;
3150         default:
3151                 PMD_DRV_LOG(ERR, "invalid src_port mask.");
3152                 return -EINVAL;
3153         }
3154
3155         bfilter->enables = en;
3156         return 0;
3157 }
3158
3159 static struct bnxt_filter_info*
3160 bnxt_match_ntuple_filter(struct bnxt *bp,
3161                          struct bnxt_filter_info *bfilter,
3162                          struct bnxt_vnic_info **mvnic)
3163 {
3164         struct bnxt_filter_info *mfilter = NULL;
3165         int i;
3166
3167         for (i = bp->nr_vnics - 1; i >= 0; i--) {
3168                 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
3169                 STAILQ_FOREACH(mfilter, &vnic->filter, next) {
3170                         if (bfilter->src_ipaddr[0] == mfilter->src_ipaddr[0] &&
3171                             bfilter->src_ipaddr_mask[0] ==
3172                             mfilter->src_ipaddr_mask[0] &&
3173                             bfilter->src_port == mfilter->src_port &&
3174                             bfilter->src_port_mask == mfilter->src_port_mask &&
3175                             bfilter->dst_ipaddr[0] == mfilter->dst_ipaddr[0] &&
3176                             bfilter->dst_ipaddr_mask[0] ==
3177                             mfilter->dst_ipaddr_mask[0] &&
3178                             bfilter->dst_port == mfilter->dst_port &&
3179                             bfilter->dst_port_mask == mfilter->dst_port_mask &&
3180                             bfilter->flags == mfilter->flags &&
3181                             bfilter->enables == mfilter->enables) {
3182                                 if (mvnic)
3183                                         *mvnic = vnic;
3184                                 return mfilter;
3185                         }
3186                 }
3187         }
3188         return NULL;
3189 }
3190
3191 static int
3192 bnxt_cfg_ntuple_filter(struct bnxt *bp,
3193                        struct rte_eth_ntuple_filter *nfilter,
3194                        enum rte_filter_op filter_op)
3195 {
3196         struct bnxt_filter_info *bfilter, *mfilter, *filter1;
3197         struct bnxt_vnic_info *vnic, *vnic0, *mvnic;
3198         int ret;
3199
3200         if (nfilter->flags != RTE_5TUPLE_FLAGS) {
3201                 PMD_DRV_LOG(ERR, "only 5tuple is supported.");
3202                 return -EINVAL;
3203         }
3204
3205         if (nfilter->flags & RTE_NTUPLE_FLAGS_TCP_FLAG) {
3206                 PMD_DRV_LOG(ERR, "Ntuple filter: TCP flags not supported\n");
3207                 return -EINVAL;
3208         }
3209
3210         bfilter = bnxt_get_unused_filter(bp);
3211         if (bfilter == NULL) {
3212                 PMD_DRV_LOG(ERR,
3213                         "Not enough resources for a new filter.\n");
3214                 return -ENOMEM;
3215         }
3216         ret = parse_ntuple_filter(bp, nfilter, bfilter);
3217         if (ret < 0)
3218                 goto free_filter;
3219
3220         vnic = &bp->vnic_info[nfilter->queue];
3221         vnic0 = BNXT_GET_DEFAULT_VNIC(bp);
3222         filter1 = STAILQ_FIRST(&vnic0->filter);
3223         if (filter1 == NULL) {
3224                 ret = -EINVAL;
3225                 goto free_filter;
3226         }
3227
3228         bfilter->dst_id = vnic->fw_vnic_id;
3229         bfilter->fw_l2_filter_id = filter1->fw_l2_filter_id;
3230         bfilter->enables |=
3231                 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID;
3232         bfilter->ethertype = 0x800;
3233         bfilter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
3234
3235         mfilter = bnxt_match_ntuple_filter(bp, bfilter, &mvnic);
3236
3237         if (mfilter != NULL && filter_op == RTE_ETH_FILTER_ADD &&
3238             bfilter->dst_id == mfilter->dst_id) {
3239                 PMD_DRV_LOG(ERR, "filter exists.\n");
3240                 ret = -EEXIST;
3241                 goto free_filter;
3242         } else if (mfilter != NULL && filter_op == RTE_ETH_FILTER_ADD &&
3243                    bfilter->dst_id != mfilter->dst_id) {
3244                 mfilter->dst_id = vnic->fw_vnic_id;
3245                 ret = bnxt_hwrm_set_ntuple_filter(bp, mfilter->dst_id, mfilter);
3246                 STAILQ_REMOVE(&mvnic->filter, mfilter, bnxt_filter_info, next);
3247                 STAILQ_INSERT_TAIL(&vnic->filter, mfilter, next);
3248                 PMD_DRV_LOG(ERR, "filter with matching pattern exists.\n");
3249                 PMD_DRV_LOG(ERR, " Updated it to the new destination queue\n");
3250                 goto free_filter;
3251         }
3252         if (mfilter == NULL && filter_op == RTE_ETH_FILTER_DELETE) {
3253                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
3254                 ret = -ENOENT;
3255                 goto free_filter;
3256         }
3257
3258         if (filter_op == RTE_ETH_FILTER_ADD) {
3259                 bfilter->filter_type = HWRM_CFA_NTUPLE_FILTER;
3260                 ret = bnxt_hwrm_set_ntuple_filter(bp, bfilter->dst_id, bfilter);
3261                 if (ret)
3262                         goto free_filter;
3263                 STAILQ_INSERT_TAIL(&vnic->filter, bfilter, next);
3264         } else {
3265                 if (mfilter == NULL) {
3266                         /* This should not happen. But for Coverity! */
3267                         ret = -ENOENT;
3268                         goto free_filter;
3269                 }
3270                 ret = bnxt_hwrm_clear_ntuple_filter(bp, mfilter);
3271
3272                 STAILQ_REMOVE(&vnic->filter, mfilter, bnxt_filter_info, next);
3273                 bnxt_free_filter(bp, mfilter);
3274                 bnxt_free_filter(bp, bfilter);
3275         }
3276
3277         return 0;
3278 free_filter:
3279         bnxt_free_filter(bp, bfilter);
3280         return ret;
3281 }
3282
3283 static int
3284 bnxt_ntuple_filter(struct rte_eth_dev *dev,
3285                         enum rte_filter_op filter_op,
3286                         void *arg)
3287 {
3288         struct bnxt *bp = dev->data->dev_private;
3289         int ret;
3290
3291         if (filter_op == RTE_ETH_FILTER_NOP)
3292                 return 0;
3293
3294         if (arg == NULL) {
3295                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
3296                             filter_op);
3297                 return -EINVAL;
3298         }
3299
3300         switch (filter_op) {
3301         case RTE_ETH_FILTER_ADD:
3302                 ret = bnxt_cfg_ntuple_filter(bp,
3303                         (struct rte_eth_ntuple_filter *)arg,
3304                         filter_op);
3305                 break;
3306         case RTE_ETH_FILTER_DELETE:
3307                 ret = bnxt_cfg_ntuple_filter(bp,
3308                         (struct rte_eth_ntuple_filter *)arg,
3309                         filter_op);
3310                 break;
3311         default:
3312                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
3313                 ret = -EINVAL;
3314                 break;
3315         }
3316         return ret;
3317 }
3318
3319 static int
3320 bnxt_parse_fdir_filter(struct bnxt *bp,
3321                        struct rte_eth_fdir_filter *fdir,
3322                        struct bnxt_filter_info *filter)
3323 {
3324         enum rte_fdir_mode fdir_mode =
3325                 bp->eth_dev->data->dev_conf.fdir_conf.mode;
3326         struct bnxt_vnic_info *vnic0, *vnic;
3327         struct bnxt_filter_info *filter1;
3328         uint32_t en = 0;
3329         int i;
3330
3331         if (fdir_mode == RTE_FDIR_MODE_PERFECT_TUNNEL)
3332                 return -EINVAL;
3333
3334         filter->l2_ovlan = fdir->input.flow_ext.vlan_tci;
3335         en |= EM_FLOW_ALLOC_INPUT_EN_OVLAN_VID;
3336
3337         switch (fdir->input.flow_type) {
3338         case RTE_ETH_FLOW_IPV4:
3339         case RTE_ETH_FLOW_NONFRAG_IPV4_OTHER:
3340                 /* FALLTHROUGH */
3341                 filter->src_ipaddr[0] = fdir->input.flow.ip4_flow.src_ip;
3342                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
3343                 filter->dst_ipaddr[0] = fdir->input.flow.ip4_flow.dst_ip;
3344                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
3345                 filter->ip_protocol = fdir->input.flow.ip4_flow.proto;
3346                 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
3347                 filter->ip_addr_type =
3348                         NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4;
3349                 filter->src_ipaddr_mask[0] = 0xffffffff;
3350                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
3351                 filter->dst_ipaddr_mask[0] = 0xffffffff;
3352                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
3353                 filter->ethertype = 0x800;
3354                 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
3355                 break;
3356         case RTE_ETH_FLOW_NONFRAG_IPV4_TCP:
3357                 filter->src_port = fdir->input.flow.tcp4_flow.src_port;
3358                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT;
3359                 filter->dst_port = fdir->input.flow.tcp4_flow.dst_port;
3360                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT;
3361                 filter->dst_port_mask = 0xffff;
3362                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
3363                 filter->src_port_mask = 0xffff;
3364                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
3365                 filter->src_ipaddr[0] = fdir->input.flow.tcp4_flow.ip.src_ip;
3366                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
3367                 filter->dst_ipaddr[0] = fdir->input.flow.tcp4_flow.ip.dst_ip;
3368                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
3369                 filter->ip_protocol = 6;
3370                 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
3371                 filter->ip_addr_type =
3372                         NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4;
3373                 filter->src_ipaddr_mask[0] = 0xffffffff;
3374                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
3375                 filter->dst_ipaddr_mask[0] = 0xffffffff;
3376                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
3377                 filter->ethertype = 0x800;
3378                 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
3379                 break;
3380         case RTE_ETH_FLOW_NONFRAG_IPV4_UDP:
3381                 filter->src_port = fdir->input.flow.udp4_flow.src_port;
3382                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT;
3383                 filter->dst_port = fdir->input.flow.udp4_flow.dst_port;
3384                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT;
3385                 filter->dst_port_mask = 0xffff;
3386                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
3387                 filter->src_port_mask = 0xffff;
3388                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
3389                 filter->src_ipaddr[0] = fdir->input.flow.udp4_flow.ip.src_ip;
3390                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
3391                 filter->dst_ipaddr[0] = fdir->input.flow.udp4_flow.ip.dst_ip;
3392                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
3393                 filter->ip_protocol = 17;
3394                 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
3395                 filter->ip_addr_type =
3396                         NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4;
3397                 filter->src_ipaddr_mask[0] = 0xffffffff;
3398                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
3399                 filter->dst_ipaddr_mask[0] = 0xffffffff;
3400                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
3401                 filter->ethertype = 0x800;
3402                 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
3403                 break;
3404         case RTE_ETH_FLOW_IPV6:
3405         case RTE_ETH_FLOW_NONFRAG_IPV6_OTHER:
3406                 /* FALLTHROUGH */
3407                 filter->ip_addr_type =
3408                         NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV6;
3409                 filter->ip_protocol = fdir->input.flow.ipv6_flow.proto;
3410                 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
3411                 rte_memcpy(filter->src_ipaddr,
3412                            fdir->input.flow.ipv6_flow.src_ip, 16);
3413                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
3414                 rte_memcpy(filter->dst_ipaddr,
3415                            fdir->input.flow.ipv6_flow.dst_ip, 16);
3416                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
3417                 memset(filter->dst_ipaddr_mask, 0xff, 16);
3418                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
3419                 memset(filter->src_ipaddr_mask, 0xff, 16);
3420                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
3421                 filter->ethertype = 0x86dd;
3422                 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
3423                 break;
3424         case RTE_ETH_FLOW_NONFRAG_IPV6_TCP:
3425                 filter->src_port = fdir->input.flow.tcp6_flow.src_port;
3426                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT;
3427                 filter->dst_port = fdir->input.flow.tcp6_flow.dst_port;
3428                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT;
3429                 filter->dst_port_mask = 0xffff;
3430                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
3431                 filter->src_port_mask = 0xffff;
3432                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
3433                 filter->ip_addr_type =
3434                         NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV6;
3435                 filter->ip_protocol = fdir->input.flow.tcp6_flow.ip.proto;
3436                 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
3437                 rte_memcpy(filter->src_ipaddr,
3438                            fdir->input.flow.tcp6_flow.ip.src_ip, 16);
3439                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
3440                 rte_memcpy(filter->dst_ipaddr,
3441                            fdir->input.flow.tcp6_flow.ip.dst_ip, 16);
3442                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
3443                 memset(filter->dst_ipaddr_mask, 0xff, 16);
3444                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
3445                 memset(filter->src_ipaddr_mask, 0xff, 16);
3446                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
3447                 filter->ethertype = 0x86dd;
3448                 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
3449                 break;
3450         case RTE_ETH_FLOW_NONFRAG_IPV6_UDP:
3451                 filter->src_port = fdir->input.flow.udp6_flow.src_port;
3452                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT;
3453                 filter->dst_port = fdir->input.flow.udp6_flow.dst_port;
3454                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT;
3455                 filter->dst_port_mask = 0xffff;
3456                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
3457                 filter->src_port_mask = 0xffff;
3458                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
3459                 filter->ip_addr_type =
3460                         NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV6;
3461                 filter->ip_protocol = fdir->input.flow.udp6_flow.ip.proto;
3462                 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
3463                 rte_memcpy(filter->src_ipaddr,
3464                            fdir->input.flow.udp6_flow.ip.src_ip, 16);
3465                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
3466                 rte_memcpy(filter->dst_ipaddr,
3467                            fdir->input.flow.udp6_flow.ip.dst_ip, 16);
3468                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
3469                 memset(filter->dst_ipaddr_mask, 0xff, 16);
3470                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
3471                 memset(filter->src_ipaddr_mask, 0xff, 16);
3472                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
3473                 filter->ethertype = 0x86dd;
3474                 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
3475                 break;
3476         case RTE_ETH_FLOW_L2_PAYLOAD:
3477                 filter->ethertype = fdir->input.flow.l2_flow.ether_type;
3478                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
3479                 break;
3480         case RTE_ETH_FLOW_VXLAN:
3481                 if (fdir->action.behavior == RTE_ETH_FDIR_REJECT)
3482                         return -EINVAL;
3483                 filter->vni = fdir->input.flow.tunnel_flow.tunnel_id;
3484                 filter->tunnel_type =
3485                         CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN;
3486                 en |= HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_TUNNEL_TYPE;
3487                 break;
3488         case RTE_ETH_FLOW_NVGRE:
3489                 if (fdir->action.behavior == RTE_ETH_FDIR_REJECT)
3490                         return -EINVAL;
3491                 filter->vni = fdir->input.flow.tunnel_flow.tunnel_id;
3492                 filter->tunnel_type =
3493                         CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_NVGRE;
3494                 en |= HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_TUNNEL_TYPE;
3495                 break;
3496         case RTE_ETH_FLOW_UNKNOWN:
3497         case RTE_ETH_FLOW_RAW:
3498         case RTE_ETH_FLOW_FRAG_IPV4:
3499         case RTE_ETH_FLOW_NONFRAG_IPV4_SCTP:
3500         case RTE_ETH_FLOW_FRAG_IPV6:
3501         case RTE_ETH_FLOW_NONFRAG_IPV6_SCTP:
3502         case RTE_ETH_FLOW_IPV6_EX:
3503         case RTE_ETH_FLOW_IPV6_TCP_EX:
3504         case RTE_ETH_FLOW_IPV6_UDP_EX:
3505         case RTE_ETH_FLOW_GENEVE:
3506                 /* FALLTHROUGH */
3507         default:
3508                 return -EINVAL;
3509         }
3510
3511         vnic0 = BNXT_GET_DEFAULT_VNIC(bp);
3512         vnic = &bp->vnic_info[fdir->action.rx_queue];
3513         if (vnic == NULL) {
3514                 PMD_DRV_LOG(ERR, "Invalid queue %d\n", fdir->action.rx_queue);
3515                 return -EINVAL;
3516         }
3517
3518         if (fdir_mode == RTE_FDIR_MODE_PERFECT_MAC_VLAN) {
3519                 rte_memcpy(filter->dst_macaddr,
3520                         fdir->input.flow.mac_vlan_flow.mac_addr.addr_bytes, 6);
3521                         en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_MACADDR;
3522         }
3523
3524         if (fdir->action.behavior == RTE_ETH_FDIR_REJECT) {
3525                 filter->flags = HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_DROP;
3526                 filter1 = STAILQ_FIRST(&vnic0->filter);
3527                 //filter1 = bnxt_get_l2_filter(bp, filter, vnic0);
3528         } else {
3529                 filter->dst_id = vnic->fw_vnic_id;
3530                 for (i = 0; i < RTE_ETHER_ADDR_LEN; i++)
3531                         if (filter->dst_macaddr[i] == 0x00)
3532                                 filter1 = STAILQ_FIRST(&vnic0->filter);
3533                         else
3534                                 filter1 = bnxt_get_l2_filter(bp, filter, vnic);
3535         }
3536
3537         if (filter1 == NULL)
3538                 return -EINVAL;
3539
3540         en |= HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID;
3541         filter->fw_l2_filter_id = filter1->fw_l2_filter_id;
3542
3543         filter->enables = en;
3544
3545         return 0;
3546 }
3547
3548 static struct bnxt_filter_info *
3549 bnxt_match_fdir(struct bnxt *bp, struct bnxt_filter_info *nf,
3550                 struct bnxt_vnic_info **mvnic)
3551 {
3552         struct bnxt_filter_info *mf = NULL;
3553         int i;
3554
3555         for (i = bp->nr_vnics - 1; i >= 0; i--) {
3556                 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
3557
3558                 STAILQ_FOREACH(mf, &vnic->filter, next) {
3559                         if (mf->filter_type == nf->filter_type &&
3560                             mf->flags == nf->flags &&
3561                             mf->src_port == nf->src_port &&
3562                             mf->src_port_mask == nf->src_port_mask &&
3563                             mf->dst_port == nf->dst_port &&
3564                             mf->dst_port_mask == nf->dst_port_mask &&
3565                             mf->ip_protocol == nf->ip_protocol &&
3566                             mf->ip_addr_type == nf->ip_addr_type &&
3567                             mf->ethertype == nf->ethertype &&
3568                             mf->vni == nf->vni &&
3569                             mf->tunnel_type == nf->tunnel_type &&
3570                             mf->l2_ovlan == nf->l2_ovlan &&
3571                             mf->l2_ovlan_mask == nf->l2_ovlan_mask &&
3572                             mf->l2_ivlan == nf->l2_ivlan &&
3573                             mf->l2_ivlan_mask == nf->l2_ivlan_mask &&
3574                             !memcmp(mf->l2_addr, nf->l2_addr,
3575                                     RTE_ETHER_ADDR_LEN) &&
3576                             !memcmp(mf->l2_addr_mask, nf->l2_addr_mask,
3577                                     RTE_ETHER_ADDR_LEN) &&
3578                             !memcmp(mf->src_macaddr, nf->src_macaddr,
3579                                     RTE_ETHER_ADDR_LEN) &&
3580                             !memcmp(mf->dst_macaddr, nf->dst_macaddr,
3581                                     RTE_ETHER_ADDR_LEN) &&
3582                             !memcmp(mf->src_ipaddr, nf->src_ipaddr,
3583                                     sizeof(nf->src_ipaddr)) &&
3584                             !memcmp(mf->src_ipaddr_mask, nf->src_ipaddr_mask,
3585                                     sizeof(nf->src_ipaddr_mask)) &&
3586                             !memcmp(mf->dst_ipaddr, nf->dst_ipaddr,
3587                                     sizeof(nf->dst_ipaddr)) &&
3588                             !memcmp(mf->dst_ipaddr_mask, nf->dst_ipaddr_mask,
3589                                     sizeof(nf->dst_ipaddr_mask))) {
3590                                 if (mvnic)
3591                                         *mvnic = vnic;
3592                                 return mf;
3593                         }
3594                 }
3595         }
3596         return NULL;
3597 }
3598
3599 static int
3600 bnxt_fdir_filter(struct rte_eth_dev *dev,
3601                  enum rte_filter_op filter_op,
3602                  void *arg)
3603 {
3604         struct bnxt *bp = dev->data->dev_private;
3605         struct rte_eth_fdir_filter *fdir  = (struct rte_eth_fdir_filter *)arg;
3606         struct bnxt_filter_info *filter, *match;
3607         struct bnxt_vnic_info *vnic, *mvnic;
3608         int ret = 0, i;
3609
3610         if (filter_op == RTE_ETH_FILTER_NOP)
3611                 return 0;
3612
3613         if (arg == NULL && filter_op != RTE_ETH_FILTER_FLUSH)
3614                 return -EINVAL;
3615
3616         switch (filter_op) {
3617         case RTE_ETH_FILTER_ADD:
3618         case RTE_ETH_FILTER_DELETE:
3619                 /* FALLTHROUGH */
3620                 filter = bnxt_get_unused_filter(bp);
3621                 if (filter == NULL) {
3622                         PMD_DRV_LOG(ERR,
3623                                 "Not enough resources for a new flow.\n");
3624                         return -ENOMEM;
3625                 }
3626
3627                 ret = bnxt_parse_fdir_filter(bp, fdir, filter);
3628                 if (ret != 0)
3629                         goto free_filter;
3630                 filter->filter_type = HWRM_CFA_NTUPLE_FILTER;
3631
3632                 if (fdir->action.behavior == RTE_ETH_FDIR_REJECT)
3633                         vnic = &bp->vnic_info[0];
3634                 else
3635                         vnic = &bp->vnic_info[fdir->action.rx_queue];
3636
3637                 match = bnxt_match_fdir(bp, filter, &mvnic);
3638                 if (match != NULL && filter_op == RTE_ETH_FILTER_ADD) {
3639                         if (match->dst_id == vnic->fw_vnic_id) {
3640                                 PMD_DRV_LOG(ERR, "Flow already exists.\n");
3641                                 ret = -EEXIST;
3642                                 goto free_filter;
3643                         } else {
3644                                 match->dst_id = vnic->fw_vnic_id;
3645                                 ret = bnxt_hwrm_set_ntuple_filter(bp,
3646                                                                   match->dst_id,
3647                                                                   match);
3648                                 STAILQ_REMOVE(&mvnic->filter, match,
3649                                               bnxt_filter_info, next);
3650                                 STAILQ_INSERT_TAIL(&vnic->filter, match, next);
3651                                 PMD_DRV_LOG(ERR,
3652                                         "Filter with matching pattern exist\n");
3653                                 PMD_DRV_LOG(ERR,
3654                                         "Updated it to new destination q\n");
3655                                 goto free_filter;
3656                         }
3657                 }
3658                 if (match == NULL && filter_op == RTE_ETH_FILTER_DELETE) {
3659                         PMD_DRV_LOG(ERR, "Flow does not exist.\n");
3660                         ret = -ENOENT;
3661                         goto free_filter;
3662                 }
3663
3664                 if (filter_op == RTE_ETH_FILTER_ADD) {
3665                         ret = bnxt_hwrm_set_ntuple_filter(bp,
3666                                                           filter->dst_id,
3667                                                           filter);
3668                         if (ret)
3669                                 goto free_filter;
3670                         STAILQ_INSERT_TAIL(&vnic->filter, filter, next);
3671                 } else {
3672                         ret = bnxt_hwrm_clear_ntuple_filter(bp, match);
3673                         STAILQ_REMOVE(&vnic->filter, match,
3674                                       bnxt_filter_info, next);
3675                         bnxt_free_filter(bp, match);
3676                         bnxt_free_filter(bp, filter);
3677                 }
3678                 break;
3679         case RTE_ETH_FILTER_FLUSH:
3680                 for (i = bp->nr_vnics - 1; i >= 0; i--) {
3681                         struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
3682
3683                         STAILQ_FOREACH(filter, &vnic->filter, next) {
3684                                 if (filter->filter_type ==
3685                                     HWRM_CFA_NTUPLE_FILTER) {
3686                                         ret =
3687                                         bnxt_hwrm_clear_ntuple_filter(bp,
3688                                                                       filter);
3689                                         STAILQ_REMOVE(&vnic->filter, filter,
3690                                                       bnxt_filter_info, next);
3691                                 }
3692                         }
3693                 }
3694                 return ret;
3695         case RTE_ETH_FILTER_UPDATE:
3696         case RTE_ETH_FILTER_STATS:
3697         case RTE_ETH_FILTER_INFO:
3698                 PMD_DRV_LOG(ERR, "operation %u not implemented", filter_op);
3699                 break;
3700         default:
3701                 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
3702                 ret = -EINVAL;
3703                 break;
3704         }
3705         return ret;
3706
3707 free_filter:
3708         bnxt_free_filter(bp, filter);
3709         return ret;
3710 }
3711
3712 int
3713 bnxt_filter_ctrl_op(struct rte_eth_dev *dev,
3714                     enum rte_filter_type filter_type,
3715                     enum rte_filter_op filter_op, void *arg)
3716 {
3717         struct bnxt *bp = dev->data->dev_private;
3718         int ret = 0;
3719
3720         if (!bp)
3721                 return -EIO;
3722
3723         if (BNXT_ETH_DEV_IS_REPRESENTOR(dev)) {
3724                 struct bnxt_vf_representor *vfr = dev->data->dev_private;
3725                 bp = vfr->parent_dev->data->dev_private;
3726                 /* parent is deleted while children are still valid */
3727                 if (!bp)
3728                         return -EIO;
3729         }
3730
3731         ret = is_bnxt_in_error(bp);
3732         if (ret)
3733                 return ret;
3734
3735         switch (filter_type) {
3736         case RTE_ETH_FILTER_TUNNEL:
3737                 PMD_DRV_LOG(ERR,
3738                         "filter type: %d: To be implemented\n", filter_type);
3739                 break;
3740         case RTE_ETH_FILTER_FDIR:
3741                 ret = bnxt_fdir_filter(dev, filter_op, arg);
3742                 break;
3743         case RTE_ETH_FILTER_NTUPLE:
3744                 ret = bnxt_ntuple_filter(dev, filter_op, arg);
3745                 break;
3746         case RTE_ETH_FILTER_ETHERTYPE:
3747                 ret = bnxt_ethertype_filter(dev, filter_op, arg);
3748                 break;
3749         case RTE_ETH_FILTER_GENERIC:
3750                 if (filter_op != RTE_ETH_FILTER_GET)
3751                         return -EINVAL;
3752                 if (BNXT_TRUFLOW_EN(bp))
3753                         *(const void **)arg = &bnxt_ulp_rte_flow_ops;
3754                 else
3755                         *(const void **)arg = &bnxt_flow_ops;
3756                 break;
3757         default:
3758                 PMD_DRV_LOG(ERR,
3759                         "Filter type (%d) not supported", filter_type);
3760                 ret = -EINVAL;
3761                 break;
3762         }
3763         return ret;
3764 }
3765
3766 static const uint32_t *
3767 bnxt_dev_supported_ptypes_get_op(struct rte_eth_dev *dev)
3768 {
3769         static const uint32_t ptypes[] = {
3770                 RTE_PTYPE_L2_ETHER_VLAN,
3771                 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN,
3772                 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN,
3773                 RTE_PTYPE_L4_ICMP,
3774                 RTE_PTYPE_L4_TCP,
3775                 RTE_PTYPE_L4_UDP,
3776                 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN,
3777                 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN,
3778                 RTE_PTYPE_INNER_L4_ICMP,
3779                 RTE_PTYPE_INNER_L4_TCP,
3780                 RTE_PTYPE_INNER_L4_UDP,
3781                 RTE_PTYPE_UNKNOWN
3782         };
3783
3784         if (!dev->rx_pkt_burst)
3785                 return NULL;
3786
3787         return ptypes;
3788 }
3789
3790 static int bnxt_map_regs(struct bnxt *bp, uint32_t *reg_arr, int count,
3791                          int reg_win)
3792 {
3793         uint32_t reg_base = *reg_arr & 0xfffff000;
3794         uint32_t win_off;
3795         int i;
3796
3797         for (i = 0; i < count; i++) {
3798                 if ((reg_arr[i] & 0xfffff000) != reg_base)
3799                         return -ERANGE;
3800         }
3801         win_off = BNXT_GRCPF_REG_WINDOW_BASE_OUT + (reg_win - 1) * 4;
3802         rte_write32(reg_base, (uint8_t *)bp->bar0 + win_off);
3803         return 0;
3804 }
3805
3806 static int bnxt_map_ptp_regs(struct bnxt *bp)
3807 {
3808         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3809         uint32_t *reg_arr;
3810         int rc, i;
3811
3812         reg_arr = ptp->rx_regs;
3813         rc = bnxt_map_regs(bp, reg_arr, BNXT_PTP_RX_REGS, 5);
3814         if (rc)
3815                 return rc;
3816
3817         reg_arr = ptp->tx_regs;
3818         rc = bnxt_map_regs(bp, reg_arr, BNXT_PTP_TX_REGS, 6);
3819         if (rc)
3820                 return rc;
3821
3822         for (i = 0; i < BNXT_PTP_RX_REGS; i++)
3823                 ptp->rx_mapped_regs[i] = 0x5000 + (ptp->rx_regs[i] & 0xfff);
3824
3825         for (i = 0; i < BNXT_PTP_TX_REGS; i++)
3826                 ptp->tx_mapped_regs[i] = 0x6000 + (ptp->tx_regs[i] & 0xfff);
3827
3828         return 0;
3829 }
3830
3831 static void bnxt_unmap_ptp_regs(struct bnxt *bp)
3832 {
3833         rte_write32(0, (uint8_t *)bp->bar0 +
3834                          BNXT_GRCPF_REG_WINDOW_BASE_OUT + 16);
3835         rte_write32(0, (uint8_t *)bp->bar0 +
3836                          BNXT_GRCPF_REG_WINDOW_BASE_OUT + 20);
3837 }
3838
3839 static uint64_t bnxt_cc_read(struct bnxt *bp)
3840 {
3841         uint64_t ns;
3842
3843         ns = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3844                               BNXT_GRCPF_REG_SYNC_TIME));
3845         ns |= (uint64_t)(rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3846                                           BNXT_GRCPF_REG_SYNC_TIME + 4))) << 32;
3847         return ns;
3848 }
3849
3850 static int bnxt_get_tx_ts(struct bnxt *bp, uint64_t *ts)
3851 {
3852         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3853         uint32_t fifo;
3854
3855         fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3856                                 ptp->tx_mapped_regs[BNXT_PTP_TX_FIFO]));
3857         if (fifo & BNXT_PTP_TX_FIFO_EMPTY)
3858                 return -EAGAIN;
3859
3860         fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3861                                 ptp->tx_mapped_regs[BNXT_PTP_TX_FIFO]));
3862         *ts = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3863                                 ptp->tx_mapped_regs[BNXT_PTP_TX_TS_L]));
3864         *ts |= (uint64_t)rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3865                                 ptp->tx_mapped_regs[BNXT_PTP_TX_TS_H])) << 32;
3866
3867         return 0;
3868 }
3869
3870 static int bnxt_get_rx_ts(struct bnxt *bp, uint64_t *ts)
3871 {
3872         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3873         struct bnxt_pf_info *pf = bp->pf;
3874         uint16_t port_id;
3875         uint32_t fifo;
3876
3877         if (!ptp)
3878                 return -ENODEV;
3879
3880         fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3881                                 ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO]));
3882         if (!(fifo & BNXT_PTP_RX_FIFO_PENDING))
3883                 return -EAGAIN;
3884
3885         port_id = pf->port_id;
3886         rte_write32(1 << port_id, (uint8_t *)bp->bar0 +
3887                ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO_ADV]);
3888
3889         fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3890                                    ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO]));
3891         if (fifo & BNXT_PTP_RX_FIFO_PENDING) {
3892 /*              bnxt_clr_rx_ts(bp);       TBD  */
3893                 return -EBUSY;
3894         }
3895
3896         *ts = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3897                                 ptp->rx_mapped_regs[BNXT_PTP_RX_TS_L]));
3898         *ts |= (uint64_t)rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3899                                 ptp->rx_mapped_regs[BNXT_PTP_RX_TS_H])) << 32;
3900
3901         return 0;
3902 }
3903
3904 static int
3905 bnxt_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
3906 {
3907         uint64_t ns;
3908         struct bnxt *bp = dev->data->dev_private;
3909         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3910
3911         if (!ptp)
3912                 return 0;
3913
3914         ns = rte_timespec_to_ns(ts);
3915         /* Set the timecounters to a new value. */
3916         ptp->tc.nsec = ns;
3917
3918         return 0;
3919 }
3920
3921 static int
3922 bnxt_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
3923 {
3924         struct bnxt *bp = dev->data->dev_private;
3925         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3926         uint64_t ns, systime_cycles = 0;
3927         int rc = 0;
3928
3929         if (!ptp)
3930                 return 0;
3931
3932         if (BNXT_CHIP_THOR(bp))
3933                 rc = bnxt_hwrm_port_ts_query(bp, BNXT_PTP_FLAGS_CURRENT_TIME,
3934                                              &systime_cycles);
3935         else
3936                 systime_cycles = bnxt_cc_read(bp);
3937
3938         ns = rte_timecounter_update(&ptp->tc, systime_cycles);
3939         *ts = rte_ns_to_timespec(ns);
3940
3941         return rc;
3942 }
3943 static int
3944 bnxt_timesync_enable(struct rte_eth_dev *dev)
3945 {
3946         struct bnxt *bp = dev->data->dev_private;
3947         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3948         uint32_t shift = 0;
3949         int rc;
3950
3951         if (!ptp)
3952                 return 0;
3953
3954         ptp->rx_filter = 1;
3955         ptp->tx_tstamp_en = 1;
3956         ptp->rxctl = BNXT_PTP_MSG_EVENTS;
3957
3958         rc = bnxt_hwrm_ptp_cfg(bp);
3959         if (rc)
3960                 return rc;
3961
3962         memset(&ptp->tc, 0, sizeof(struct rte_timecounter));
3963         memset(&ptp->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
3964         memset(&ptp->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
3965
3966         ptp->tc.cc_mask = BNXT_CYCLECOUNTER_MASK;
3967         ptp->tc.cc_shift = shift;
3968         ptp->tc.nsec_mask = (1ULL << shift) - 1;
3969
3970         ptp->rx_tstamp_tc.cc_mask = BNXT_CYCLECOUNTER_MASK;
3971         ptp->rx_tstamp_tc.cc_shift = shift;
3972         ptp->rx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
3973
3974         ptp->tx_tstamp_tc.cc_mask = BNXT_CYCLECOUNTER_MASK;
3975         ptp->tx_tstamp_tc.cc_shift = shift;
3976         ptp->tx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
3977
3978         if (!BNXT_CHIP_THOR(bp))
3979                 bnxt_map_ptp_regs(bp);
3980
3981         return 0;
3982 }
3983
3984 static int
3985 bnxt_timesync_disable(struct rte_eth_dev *dev)
3986 {
3987         struct bnxt *bp = dev->data->dev_private;
3988         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3989
3990         if (!ptp)
3991                 return 0;
3992
3993         ptp->rx_filter = 0;
3994         ptp->tx_tstamp_en = 0;
3995         ptp->rxctl = 0;
3996
3997         bnxt_hwrm_ptp_cfg(bp);
3998
3999         if (!BNXT_CHIP_THOR(bp))
4000                 bnxt_unmap_ptp_regs(bp);
4001
4002         return 0;
4003 }
4004
4005 static int
4006 bnxt_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
4007                                  struct timespec *timestamp,
4008                                  uint32_t flags __rte_unused)
4009 {
4010         struct bnxt *bp = dev->data->dev_private;
4011         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
4012         uint64_t rx_tstamp_cycles = 0;
4013         uint64_t ns;
4014
4015         if (!ptp)
4016                 return 0;
4017
4018         if (BNXT_CHIP_THOR(bp))
4019                 rx_tstamp_cycles = ptp->rx_timestamp;
4020         else
4021                 bnxt_get_rx_ts(bp, &rx_tstamp_cycles);
4022
4023         ns = rte_timecounter_update(&ptp->rx_tstamp_tc, rx_tstamp_cycles);
4024         *timestamp = rte_ns_to_timespec(ns);
4025         return  0;
4026 }
4027
4028 static int
4029 bnxt_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
4030                                  struct timespec *timestamp)
4031 {
4032         struct bnxt *bp = dev->data->dev_private;
4033         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
4034         uint64_t tx_tstamp_cycles = 0;
4035         uint64_t ns;
4036         int rc = 0;
4037
4038         if (!ptp)
4039                 return 0;
4040
4041         if (BNXT_CHIP_THOR(bp))
4042                 rc = bnxt_hwrm_port_ts_query(bp, BNXT_PTP_FLAGS_PATH_TX,
4043                                              &tx_tstamp_cycles);
4044         else
4045                 rc = bnxt_get_tx_ts(bp, &tx_tstamp_cycles);
4046
4047         ns = rte_timecounter_update(&ptp->tx_tstamp_tc, tx_tstamp_cycles);
4048         *timestamp = rte_ns_to_timespec(ns);
4049
4050         return rc;
4051 }
4052
4053 static int
4054 bnxt_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
4055 {
4056         struct bnxt *bp = dev->data->dev_private;
4057         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
4058
4059         if (!ptp)
4060                 return 0;
4061
4062         ptp->tc.nsec += delta;
4063
4064         return 0;
4065 }
4066
4067 static int
4068 bnxt_get_eeprom_length_op(struct rte_eth_dev *dev)
4069 {
4070         struct bnxt *bp = dev->data->dev_private;
4071         int rc;
4072         uint32_t dir_entries;
4073         uint32_t entry_length;
4074
4075         rc = is_bnxt_in_error(bp);
4076         if (rc)
4077                 return rc;
4078
4079         PMD_DRV_LOG(INFO, PCI_PRI_FMT "\n",
4080                     bp->pdev->addr.domain, bp->pdev->addr.bus,
4081                     bp->pdev->addr.devid, bp->pdev->addr.function);
4082
4083         rc = bnxt_hwrm_nvm_get_dir_info(bp, &dir_entries, &entry_length);
4084         if (rc != 0)
4085                 return rc;
4086
4087         return dir_entries * entry_length;
4088 }
4089
4090 static int
4091 bnxt_get_eeprom_op(struct rte_eth_dev *dev,
4092                 struct rte_dev_eeprom_info *in_eeprom)
4093 {
4094         struct bnxt *bp = dev->data->dev_private;
4095         uint32_t index;
4096         uint32_t offset;
4097         int rc;
4098
4099         rc = is_bnxt_in_error(bp);
4100         if (rc)
4101                 return rc;
4102
4103         PMD_DRV_LOG(INFO, PCI_PRI_FMT " in_eeprom->offset = %d len = %d\n",
4104                     bp->pdev->addr.domain, bp->pdev->addr.bus,
4105                     bp->pdev->addr.devid, bp->pdev->addr.function,
4106                     in_eeprom->offset, in_eeprom->length);
4107
4108         if (in_eeprom->offset == 0) /* special offset value to get directory */
4109                 return bnxt_get_nvram_directory(bp, in_eeprom->length,
4110                                                 in_eeprom->data);
4111
4112         index = in_eeprom->offset >> 24;
4113         offset = in_eeprom->offset & 0xffffff;
4114
4115         if (index != 0)
4116                 return bnxt_hwrm_get_nvram_item(bp, index - 1, offset,
4117                                            in_eeprom->length, in_eeprom->data);
4118
4119         return 0;
4120 }
4121
4122 static bool bnxt_dir_type_is_ape_bin_format(uint16_t dir_type)
4123 {
4124         switch (dir_type) {
4125         case BNX_DIR_TYPE_CHIMP_PATCH:
4126         case BNX_DIR_TYPE_BOOTCODE:
4127         case BNX_DIR_TYPE_BOOTCODE_2:
4128         case BNX_DIR_TYPE_APE_FW:
4129         case BNX_DIR_TYPE_APE_PATCH:
4130         case BNX_DIR_TYPE_KONG_FW:
4131         case BNX_DIR_TYPE_KONG_PATCH:
4132         case BNX_DIR_TYPE_BONO_FW:
4133         case BNX_DIR_TYPE_BONO_PATCH:
4134                 /* FALLTHROUGH */
4135                 return true;
4136         }
4137
4138         return false;
4139 }
4140
4141 static bool bnxt_dir_type_is_other_exec_format(uint16_t dir_type)
4142 {
4143         switch (dir_type) {
4144         case BNX_DIR_TYPE_AVS:
4145         case BNX_DIR_TYPE_EXP_ROM_MBA:
4146         case BNX_DIR_TYPE_PCIE:
4147         case BNX_DIR_TYPE_TSCF_UCODE:
4148         case BNX_DIR_TYPE_EXT_PHY:
4149         case BNX_DIR_TYPE_CCM:
4150         case BNX_DIR_TYPE_ISCSI_BOOT:
4151         case BNX_DIR_TYPE_ISCSI_BOOT_IPV6:
4152         case BNX_DIR_TYPE_ISCSI_BOOT_IPV4N6:
4153                 /* FALLTHROUGH */
4154                 return true;
4155         }
4156
4157         return false;
4158 }
4159
4160 static bool bnxt_dir_type_is_executable(uint16_t dir_type)
4161 {
4162         return bnxt_dir_type_is_ape_bin_format(dir_type) ||
4163                 bnxt_dir_type_is_other_exec_format(dir_type);
4164 }
4165
4166 static int
4167 bnxt_set_eeprom_op(struct rte_eth_dev *dev,
4168                 struct rte_dev_eeprom_info *in_eeprom)
4169 {
4170         struct bnxt *bp = dev->data->dev_private;
4171         uint8_t index, dir_op;
4172         uint16_t type, ext, ordinal, attr;
4173         int rc;
4174
4175         rc = is_bnxt_in_error(bp);
4176         if (rc)
4177                 return rc;
4178
4179         PMD_DRV_LOG(INFO, PCI_PRI_FMT " in_eeprom->offset = %d len = %d\n",
4180                     bp->pdev->addr.domain, bp->pdev->addr.bus,
4181                     bp->pdev->addr.devid, bp->pdev->addr.function,
4182                     in_eeprom->offset, in_eeprom->length);
4183
4184         if (!BNXT_PF(bp)) {
4185                 PMD_DRV_LOG(ERR, "NVM write not supported from a VF\n");
4186                 return -EINVAL;
4187         }
4188
4189         type = in_eeprom->magic >> 16;
4190
4191         if (type == 0xffff) { /* special value for directory operations */
4192                 index = in_eeprom->magic & 0xff;
4193                 dir_op = in_eeprom->magic >> 8;
4194                 if (index == 0)
4195                         return -EINVAL;
4196                 switch (dir_op) {
4197                 case 0x0e: /* erase */
4198                         if (in_eeprom->offset != ~in_eeprom->magic)
4199                                 return -EINVAL;
4200                         return bnxt_hwrm_erase_nvram_directory(bp, index - 1);
4201                 default:
4202                         return -EINVAL;
4203                 }
4204         }
4205
4206         /* Create or re-write an NVM item: */
4207         if (bnxt_dir_type_is_executable(type) == true)
4208                 return -EOPNOTSUPP;
4209         ext = in_eeprom->magic & 0xffff;
4210         ordinal = in_eeprom->offset >> 16;
4211         attr = in_eeprom->offset & 0xffff;
4212
4213         return bnxt_hwrm_flash_nvram(bp, type, ordinal, ext, attr,
4214                                      in_eeprom->data, in_eeprom->length);
4215 }
4216
4217 /*
4218  * Initialization
4219  */
4220
4221 static const struct eth_dev_ops bnxt_dev_ops = {
4222         .dev_infos_get = bnxt_dev_info_get_op,
4223         .dev_close = bnxt_dev_close_op,
4224         .dev_configure = bnxt_dev_configure_op,
4225         .dev_start = bnxt_dev_start_op,
4226         .dev_stop = bnxt_dev_stop_op,
4227         .dev_set_link_up = bnxt_dev_set_link_up_op,
4228         .dev_set_link_down = bnxt_dev_set_link_down_op,
4229         .stats_get = bnxt_stats_get_op,
4230         .stats_reset = bnxt_stats_reset_op,
4231         .rx_queue_setup = bnxt_rx_queue_setup_op,
4232         .rx_queue_release = bnxt_rx_queue_release_op,
4233         .tx_queue_setup = bnxt_tx_queue_setup_op,
4234         .tx_queue_release = bnxt_tx_queue_release_op,
4235         .rx_queue_intr_enable = bnxt_rx_queue_intr_enable_op,
4236         .rx_queue_intr_disable = bnxt_rx_queue_intr_disable_op,
4237         .reta_update = bnxt_reta_update_op,
4238         .reta_query = bnxt_reta_query_op,
4239         .rss_hash_update = bnxt_rss_hash_update_op,
4240         .rss_hash_conf_get = bnxt_rss_hash_conf_get_op,
4241         .link_update = bnxt_link_update_op,
4242         .promiscuous_enable = bnxt_promiscuous_enable_op,
4243         .promiscuous_disable = bnxt_promiscuous_disable_op,
4244         .allmulticast_enable = bnxt_allmulticast_enable_op,
4245         .allmulticast_disable = bnxt_allmulticast_disable_op,
4246         .mac_addr_add = bnxt_mac_addr_add_op,
4247         .mac_addr_remove = bnxt_mac_addr_remove_op,
4248         .flow_ctrl_get = bnxt_flow_ctrl_get_op,
4249         .flow_ctrl_set = bnxt_flow_ctrl_set_op,
4250         .udp_tunnel_port_add  = bnxt_udp_tunnel_port_add_op,
4251         .udp_tunnel_port_del  = bnxt_udp_tunnel_port_del_op,
4252         .vlan_filter_set = bnxt_vlan_filter_set_op,
4253         .vlan_offload_set = bnxt_vlan_offload_set_op,
4254         .vlan_tpid_set = bnxt_vlan_tpid_set_op,
4255         .vlan_pvid_set = bnxt_vlan_pvid_set_op,
4256         .mtu_set = bnxt_mtu_set_op,
4257         .mac_addr_set = bnxt_set_default_mac_addr_op,
4258         .xstats_get = bnxt_dev_xstats_get_op,
4259         .xstats_get_names = bnxt_dev_xstats_get_names_op,
4260         .xstats_reset = bnxt_dev_xstats_reset_op,
4261         .fw_version_get = bnxt_fw_version_get,
4262         .set_mc_addr_list = bnxt_dev_set_mc_addr_list_op,
4263         .rxq_info_get = bnxt_rxq_info_get_op,
4264         .txq_info_get = bnxt_txq_info_get_op,
4265         .rx_burst_mode_get = bnxt_rx_burst_mode_get,
4266         .tx_burst_mode_get = bnxt_tx_burst_mode_get,
4267         .dev_led_on = bnxt_dev_led_on_op,
4268         .dev_led_off = bnxt_dev_led_off_op,
4269         .xstats_get_by_id = bnxt_dev_xstats_get_by_id_op,
4270         .xstats_get_names_by_id = bnxt_dev_xstats_get_names_by_id_op,
4271         .rx_queue_start = bnxt_rx_queue_start,
4272         .rx_queue_stop = bnxt_rx_queue_stop,
4273         .tx_queue_start = bnxt_tx_queue_start,
4274         .tx_queue_stop = bnxt_tx_queue_stop,
4275         .filter_ctrl = bnxt_filter_ctrl_op,
4276         .dev_supported_ptypes_get = bnxt_dev_supported_ptypes_get_op,
4277         .get_eeprom_length    = bnxt_get_eeprom_length_op,
4278         .get_eeprom           = bnxt_get_eeprom_op,
4279         .set_eeprom           = bnxt_set_eeprom_op,
4280         .timesync_enable      = bnxt_timesync_enable,
4281         .timesync_disable     = bnxt_timesync_disable,
4282         .timesync_read_time   = bnxt_timesync_read_time,
4283         .timesync_write_time   = bnxt_timesync_write_time,
4284         .timesync_adjust_time = bnxt_timesync_adjust_time,
4285         .timesync_read_rx_timestamp = bnxt_timesync_read_rx_timestamp,
4286         .timesync_read_tx_timestamp = bnxt_timesync_read_tx_timestamp,
4287 };
4288
4289 static uint32_t bnxt_map_reset_regs(struct bnxt *bp, uint32_t reg)
4290 {
4291         uint32_t offset;
4292
4293         /* Only pre-map the reset GRC registers using window 3 */
4294         rte_write32(reg & 0xfffff000, (uint8_t *)bp->bar0 +
4295                     BNXT_GRCPF_REG_WINDOW_BASE_OUT + 8);
4296
4297         offset = BNXT_GRCP_WINDOW_3_BASE + (reg & 0xffc);
4298
4299         return offset;
4300 }
4301
4302 int bnxt_map_fw_health_status_regs(struct bnxt *bp)
4303 {
4304         struct bnxt_error_recovery_info *info = bp->recovery_info;
4305         uint32_t reg_base = 0xffffffff;
4306         int i;
4307
4308         /* Only pre-map the monitoring GRC registers using window 2 */
4309         for (i = 0; i < BNXT_FW_STATUS_REG_CNT; i++) {
4310                 uint32_t reg = info->status_regs[i];
4311
4312                 if (BNXT_FW_STATUS_REG_TYPE(reg) != BNXT_FW_STATUS_REG_TYPE_GRC)
4313                         continue;
4314
4315                 if (reg_base == 0xffffffff)
4316                         reg_base = reg & 0xfffff000;
4317                 if ((reg & 0xfffff000) != reg_base)
4318                         return -ERANGE;
4319
4320                 /* Use mask 0xffc as the Lower 2 bits indicates
4321                  * address space location
4322                  */
4323                 info->mapped_status_regs[i] = BNXT_GRCP_WINDOW_2_BASE +
4324                                                 (reg & 0xffc);
4325         }
4326
4327         if (reg_base == 0xffffffff)
4328                 return 0;
4329
4330         rte_write32(reg_base, (uint8_t *)bp->bar0 +
4331                     BNXT_GRCPF_REG_WINDOW_BASE_OUT + 4);
4332
4333         return 0;
4334 }
4335
4336 static void bnxt_write_fw_reset_reg(struct bnxt *bp, uint32_t index)
4337 {
4338         struct bnxt_error_recovery_info *info = bp->recovery_info;
4339         uint32_t delay = info->delay_after_reset[index];
4340         uint32_t val = info->reset_reg_val[index];
4341         uint32_t reg = info->reset_reg[index];
4342         uint32_t type, offset;
4343
4344         type = BNXT_FW_STATUS_REG_TYPE(reg);
4345         offset = BNXT_FW_STATUS_REG_OFF(reg);
4346
4347         switch (type) {
4348         case BNXT_FW_STATUS_REG_TYPE_CFG:
4349                 rte_pci_write_config(bp->pdev, &val, sizeof(val), offset);
4350                 break;
4351         case BNXT_FW_STATUS_REG_TYPE_GRC:
4352                 offset = bnxt_map_reset_regs(bp, offset);
4353                 rte_write32(val, (uint8_t *)bp->bar0 + offset);
4354                 break;
4355         case BNXT_FW_STATUS_REG_TYPE_BAR0:
4356                 rte_write32(val, (uint8_t *)bp->bar0 + offset);
4357                 break;
4358         }
4359         /* wait on a specific interval of time until core reset is complete */
4360         if (delay)
4361                 rte_delay_ms(delay);
4362 }
4363
4364 static void bnxt_dev_cleanup(struct bnxt *bp)
4365 {
4366         bnxt_set_hwrm_link_config(bp, false);
4367         bp->link_info->link_up = 0;
4368         if (bp->eth_dev->data->dev_started)
4369                 bnxt_dev_stop_op(bp->eth_dev);
4370
4371         bnxt_uninit_resources(bp, true);
4372 }
4373
4374 static int bnxt_restore_vlan_filters(struct bnxt *bp)
4375 {
4376         struct rte_eth_dev *dev = bp->eth_dev;
4377         struct rte_vlan_filter_conf *vfc;
4378         int vidx, vbit, rc;
4379         uint16_t vlan_id;
4380
4381         for (vlan_id = 1; vlan_id <= RTE_ETHER_MAX_VLAN_ID; vlan_id++) {
4382                 vfc = &dev->data->vlan_filter_conf;
4383                 vidx = vlan_id / 64;
4384                 vbit = vlan_id % 64;
4385
4386                 /* Each bit corresponds to a VLAN id */
4387                 if (vfc->ids[vidx] & (UINT64_C(1) << vbit)) {
4388                         rc = bnxt_add_vlan_filter(bp, vlan_id);
4389                         if (rc)
4390                                 return rc;
4391                 }
4392         }
4393
4394         return 0;
4395 }
4396
4397 static int bnxt_restore_mac_filters(struct bnxt *bp)
4398 {
4399         struct rte_eth_dev *dev = bp->eth_dev;
4400         struct rte_eth_dev_info dev_info;
4401         struct rte_ether_addr *addr;
4402         uint64_t pool_mask;
4403         uint32_t pool = 0;
4404         uint16_t i;
4405         int rc;
4406
4407         if (BNXT_VF(bp) && !BNXT_VF_IS_TRUSTED(bp))
4408                 return 0;
4409
4410         rc = bnxt_dev_info_get_op(dev, &dev_info);
4411         if (rc)
4412                 return rc;
4413
4414         /* replay MAC address configuration */
4415         for (i = 1; i < dev_info.max_mac_addrs; i++) {
4416                 addr = &dev->data->mac_addrs[i];
4417
4418                 /* skip zero address */
4419                 if (rte_is_zero_ether_addr(addr))
4420                         continue;
4421
4422                 pool = 0;
4423                 pool_mask = dev->data->mac_pool_sel[i];
4424
4425                 do {
4426                         if (pool_mask & 1ULL) {
4427                                 rc = bnxt_mac_addr_add_op(dev, addr, i, pool);
4428                                 if (rc)
4429                                         return rc;
4430                         }
4431                         pool_mask >>= 1;
4432                         pool++;
4433                 } while (pool_mask);
4434         }
4435
4436         return 0;
4437 }
4438
4439 static int bnxt_restore_filters(struct bnxt *bp)
4440 {
4441         struct rte_eth_dev *dev = bp->eth_dev;
4442         int ret = 0;
4443
4444         if (dev->data->all_multicast) {
4445                 ret = bnxt_allmulticast_enable_op(dev);
4446                 if (ret)
4447                         return ret;
4448         }
4449         if (dev->data->promiscuous) {
4450                 ret = bnxt_promiscuous_enable_op(dev);
4451                 if (ret)
4452                         return ret;
4453         }
4454
4455         ret = bnxt_restore_mac_filters(bp);
4456         if (ret)
4457                 return ret;
4458
4459         ret = bnxt_restore_vlan_filters(bp);
4460         /* TODO restore other filters as well */
4461         return ret;
4462 }
4463
4464 static void bnxt_dev_recover(void *arg)
4465 {
4466         struct bnxt *bp = arg;
4467         int timeout = bp->fw_reset_max_msecs;
4468         int rc = 0;
4469
4470         /* Clear Error flag so that device re-init should happen */
4471         bp->flags &= ~BNXT_FLAG_FATAL_ERROR;
4472
4473         do {
4474                 rc = bnxt_hwrm_ver_get(bp, SHORT_HWRM_CMD_TIMEOUT);
4475                 if (rc == 0)
4476                         break;
4477                 rte_delay_ms(BNXT_FW_READY_WAIT_INTERVAL);
4478                 timeout -= BNXT_FW_READY_WAIT_INTERVAL;
4479         } while (rc && timeout);
4480
4481         if (rc) {
4482                 PMD_DRV_LOG(ERR, "FW is not Ready after reset\n");
4483                 goto err;
4484         }
4485
4486         rc = bnxt_init_resources(bp, true);
4487         if (rc) {
4488                 PMD_DRV_LOG(ERR,
4489                             "Failed to initialize resources after reset\n");
4490                 goto err;
4491         }
4492         /* clear reset flag as the device is initialized now */
4493         bp->flags &= ~BNXT_FLAG_FW_RESET;
4494
4495         rc = bnxt_dev_start_op(bp->eth_dev);
4496         if (rc) {
4497                 PMD_DRV_LOG(ERR, "Failed to start port after reset\n");
4498                 goto err_start;
4499         }
4500
4501         rc = bnxt_restore_filters(bp);
4502         if (rc)
4503                 goto err_start;
4504
4505         PMD_DRV_LOG(INFO, "Recovered from FW reset\n");
4506         return;
4507 err_start:
4508         bnxt_dev_stop_op(bp->eth_dev);
4509 err:
4510         bp->flags |= BNXT_FLAG_FATAL_ERROR;
4511         bnxt_uninit_resources(bp, false);
4512         PMD_DRV_LOG(ERR, "Failed to recover from FW reset\n");
4513 }
4514
4515 void bnxt_dev_reset_and_resume(void *arg)
4516 {
4517         struct bnxt *bp = arg;
4518         int rc;
4519
4520         bnxt_dev_cleanup(bp);
4521
4522         bnxt_wait_for_device_shutdown(bp);
4523
4524         rc = rte_eal_alarm_set(US_PER_MS * bp->fw_reset_min_msecs,
4525                                bnxt_dev_recover, (void *)bp);
4526         if (rc)
4527                 PMD_DRV_LOG(ERR, "Error setting recovery alarm");
4528 }
4529
4530 uint32_t bnxt_read_fw_status_reg(struct bnxt *bp, uint32_t index)
4531 {
4532         struct bnxt_error_recovery_info *info = bp->recovery_info;
4533         uint32_t reg = info->status_regs[index];
4534         uint32_t type, offset, val = 0;
4535
4536         type = BNXT_FW_STATUS_REG_TYPE(reg);
4537         offset = BNXT_FW_STATUS_REG_OFF(reg);
4538
4539         switch (type) {
4540         case BNXT_FW_STATUS_REG_TYPE_CFG:
4541                 rte_pci_read_config(bp->pdev, &val, sizeof(val), offset);
4542                 break;
4543         case BNXT_FW_STATUS_REG_TYPE_GRC:
4544                 offset = info->mapped_status_regs[index];
4545                 /* FALLTHROUGH */
4546         case BNXT_FW_STATUS_REG_TYPE_BAR0:
4547                 val = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
4548                                        offset));
4549                 break;
4550         }
4551
4552         return val;
4553 }
4554
4555 static int bnxt_fw_reset_all(struct bnxt *bp)
4556 {
4557         struct bnxt_error_recovery_info *info = bp->recovery_info;
4558         uint32_t i;
4559         int rc = 0;
4560
4561         if (info->flags & BNXT_FLAG_ERROR_RECOVERY_HOST) {
4562                 /* Reset through master function driver */
4563                 for (i = 0; i < info->reg_array_cnt; i++)
4564                         bnxt_write_fw_reset_reg(bp, i);
4565                 /* Wait for time specified by FW after triggering reset */
4566                 rte_delay_ms(info->master_func_wait_period_after_reset);
4567         } else if (info->flags & BNXT_FLAG_ERROR_RECOVERY_CO_CPU) {
4568                 /* Reset with the help of Kong processor */
4569                 rc = bnxt_hwrm_fw_reset(bp);
4570                 if (rc)
4571                         PMD_DRV_LOG(ERR, "Failed to reset FW\n");
4572         }
4573
4574         return rc;
4575 }
4576
4577 static void bnxt_fw_reset_cb(void *arg)
4578 {
4579         struct bnxt *bp = arg;
4580         struct bnxt_error_recovery_info *info = bp->recovery_info;
4581         int rc = 0;
4582
4583         /* Only Master function can do FW reset */
4584         if (bnxt_is_master_func(bp) &&
4585             bnxt_is_recovery_enabled(bp)) {
4586                 rc = bnxt_fw_reset_all(bp);
4587                 if (rc) {
4588                         PMD_DRV_LOG(ERR, "Adapter recovery failed\n");
4589                         return;
4590                 }
4591         }
4592
4593         /* if recovery method is ERROR_RECOVERY_CO_CPU, KONG will send
4594          * EXCEPTION_FATAL_ASYNC event to all the functions
4595          * (including MASTER FUNC). After receiving this Async, all the active
4596          * drivers should treat this case as FW initiated recovery
4597          */
4598         if (info->flags & BNXT_FLAG_ERROR_RECOVERY_HOST) {
4599                 bp->fw_reset_min_msecs = BNXT_MIN_FW_READY_TIMEOUT;
4600                 bp->fw_reset_max_msecs = BNXT_MAX_FW_RESET_TIMEOUT;
4601
4602                 /* To recover from error */
4603                 rte_eal_alarm_set(US_PER_MS, bnxt_dev_reset_and_resume,
4604                                   (void *)bp);
4605         }
4606 }
4607
4608 /* Driver should poll FW heartbeat, reset_counter with the frequency
4609  * advertised by FW in HWRM_ERROR_RECOVERY_QCFG.
4610  * When the driver detects heartbeat stop or change in reset_counter,
4611  * it has to trigger a reset to recover from the error condition.
4612  * A “master PF” is the function who will have the privilege to
4613  * initiate the chimp reset. The master PF will be elected by the
4614  * firmware and will be notified through async message.
4615  */
4616 static void bnxt_check_fw_health(void *arg)
4617 {
4618         struct bnxt *bp = arg;
4619         struct bnxt_error_recovery_info *info = bp->recovery_info;
4620         uint32_t val = 0, wait_msec;
4621
4622         if (!info || !bnxt_is_recovery_enabled(bp) ||
4623             is_bnxt_in_error(bp))
4624                 return;
4625
4626         val = bnxt_read_fw_status_reg(bp, BNXT_FW_HEARTBEAT_CNT_REG);
4627         if (val == info->last_heart_beat)
4628                 goto reset;
4629
4630         info->last_heart_beat = val;
4631
4632         val = bnxt_read_fw_status_reg(bp, BNXT_FW_RECOVERY_CNT_REG);
4633         if (val != info->last_reset_counter)
4634                 goto reset;
4635
4636         info->last_reset_counter = val;
4637
4638         rte_eal_alarm_set(US_PER_MS * info->driver_polling_freq,
4639                           bnxt_check_fw_health, (void *)bp);
4640
4641         return;
4642 reset:
4643         /* Stop DMA to/from device */
4644         bp->flags |= BNXT_FLAG_FATAL_ERROR;
4645         bp->flags |= BNXT_FLAG_FW_RESET;
4646
4647         PMD_DRV_LOG(ERR, "Detected FW dead condition\n");
4648
4649         if (bnxt_is_master_func(bp))
4650                 wait_msec = info->master_func_wait_period;
4651         else
4652                 wait_msec = info->normal_func_wait_period;
4653
4654         rte_eal_alarm_set(US_PER_MS * wait_msec,
4655                           bnxt_fw_reset_cb, (void *)bp);
4656 }
4657
4658 void bnxt_schedule_fw_health_check(struct bnxt *bp)
4659 {
4660         uint32_t polling_freq;
4661
4662         if (!bnxt_is_recovery_enabled(bp))
4663                 return;
4664
4665         if (bp->flags & BNXT_FLAG_FW_HEALTH_CHECK_SCHEDULED)
4666                 return;
4667
4668         polling_freq = bp->recovery_info->driver_polling_freq;
4669
4670         rte_eal_alarm_set(US_PER_MS * polling_freq,
4671                           bnxt_check_fw_health, (void *)bp);
4672         bp->flags |= BNXT_FLAG_FW_HEALTH_CHECK_SCHEDULED;
4673 }
4674
4675 static void bnxt_cancel_fw_health_check(struct bnxt *bp)
4676 {
4677         if (!bnxt_is_recovery_enabled(bp))
4678                 return;
4679
4680         rte_eal_alarm_cancel(bnxt_check_fw_health, (void *)bp);
4681         bp->flags &= ~BNXT_FLAG_FW_HEALTH_CHECK_SCHEDULED;
4682 }
4683
4684 static bool bnxt_vf_pciid(uint16_t device_id)
4685 {
4686         switch (device_id) {
4687         case BROADCOM_DEV_ID_57304_VF:
4688         case BROADCOM_DEV_ID_57406_VF:
4689         case BROADCOM_DEV_ID_5731X_VF:
4690         case BROADCOM_DEV_ID_5741X_VF:
4691         case BROADCOM_DEV_ID_57414_VF:
4692         case BROADCOM_DEV_ID_STRATUS_NIC_VF1:
4693         case BROADCOM_DEV_ID_STRATUS_NIC_VF2:
4694         case BROADCOM_DEV_ID_58802_VF:
4695         case BROADCOM_DEV_ID_57500_VF1:
4696         case BROADCOM_DEV_ID_57500_VF2:
4697                 /* FALLTHROUGH */
4698                 return true;
4699         default:
4700                 return false;
4701         }
4702 }
4703
4704 static bool bnxt_thor_device(uint16_t device_id)
4705 {
4706         switch (device_id) {
4707         case BROADCOM_DEV_ID_57508:
4708         case BROADCOM_DEV_ID_57504:
4709         case BROADCOM_DEV_ID_57502:
4710         case BROADCOM_DEV_ID_57508_MF1:
4711         case BROADCOM_DEV_ID_57504_MF1:
4712         case BROADCOM_DEV_ID_57502_MF1:
4713         case BROADCOM_DEV_ID_57508_MF2:
4714         case BROADCOM_DEV_ID_57504_MF2:
4715         case BROADCOM_DEV_ID_57502_MF2:
4716         case BROADCOM_DEV_ID_57500_VF1:
4717         case BROADCOM_DEV_ID_57500_VF2:
4718                 /* FALLTHROUGH */
4719                 return true;
4720         default:
4721                 return false;
4722         }
4723 }
4724
4725 bool bnxt_stratus_device(struct bnxt *bp)
4726 {
4727         uint16_t device_id = bp->pdev->id.device_id;
4728
4729         switch (device_id) {
4730         case BROADCOM_DEV_ID_STRATUS_NIC:
4731         case BROADCOM_DEV_ID_STRATUS_NIC_VF1:
4732         case BROADCOM_DEV_ID_STRATUS_NIC_VF2:
4733                 /* FALLTHROUGH */
4734                 return true;
4735         default:
4736                 return false;
4737         }
4738 }
4739
4740 static int bnxt_init_board(struct rte_eth_dev *eth_dev)
4741 {
4742         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
4743         struct bnxt *bp = eth_dev->data->dev_private;
4744
4745         /* enable device (incl. PCI PM wakeup), and bus-mastering */
4746         bp->bar0 = (void *)pci_dev->mem_resource[0].addr;
4747         bp->doorbell_base = (void *)pci_dev->mem_resource[2].addr;
4748         if (!bp->bar0 || !bp->doorbell_base) {
4749                 PMD_DRV_LOG(ERR, "Unable to access Hardware\n");
4750                 return -ENODEV;
4751         }
4752
4753         bp->eth_dev = eth_dev;
4754         bp->pdev = pci_dev;
4755
4756         return 0;
4757 }
4758
4759 static int bnxt_alloc_ctx_mem_blk(struct bnxt *bp,
4760                                   struct bnxt_ctx_pg_info *ctx_pg,
4761                                   uint32_t mem_size,
4762                                   const char *suffix,
4763                                   uint16_t idx)
4764 {
4765         struct bnxt_ring_mem_info *rmem = &ctx_pg->ring_mem;
4766         const struct rte_memzone *mz = NULL;
4767         char mz_name[RTE_MEMZONE_NAMESIZE];
4768         rte_iova_t mz_phys_addr;
4769         uint64_t valid_bits = 0;
4770         uint32_t sz;
4771         int i;
4772
4773         if (!mem_size)
4774                 return 0;
4775
4776         rmem->nr_pages = RTE_ALIGN_MUL_CEIL(mem_size, BNXT_PAGE_SIZE) /
4777                          BNXT_PAGE_SIZE;
4778         rmem->page_size = BNXT_PAGE_SIZE;
4779         rmem->pg_arr = ctx_pg->ctx_pg_arr;
4780         rmem->dma_arr = ctx_pg->ctx_dma_arr;
4781         rmem->flags = BNXT_RMEM_VALID_PTE_FLAG;
4782
4783         valid_bits = PTU_PTE_VALID;
4784
4785         if (rmem->nr_pages > 1) {
4786                 snprintf(mz_name, RTE_MEMZONE_NAMESIZE,
4787                          "bnxt_ctx_pg_tbl%s_%x_%d",
4788                          suffix, idx, bp->eth_dev->data->port_id);
4789                 mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0;
4790                 mz = rte_memzone_lookup(mz_name);
4791                 if (!mz) {
4792                         mz = rte_memzone_reserve_aligned(mz_name,
4793                                                 rmem->nr_pages * 8,
4794                                                 SOCKET_ID_ANY,
4795                                                 RTE_MEMZONE_2MB |
4796                                                 RTE_MEMZONE_SIZE_HINT_ONLY |
4797                                                 RTE_MEMZONE_IOVA_CONTIG,
4798                                                 BNXT_PAGE_SIZE);
4799                         if (mz == NULL)
4800                                 return -ENOMEM;
4801                 }
4802
4803                 memset(mz->addr, 0, mz->len);
4804                 mz_phys_addr = mz->iova;
4805
4806                 rmem->pg_tbl = mz->addr;
4807                 rmem->pg_tbl_map = mz_phys_addr;
4808                 rmem->pg_tbl_mz = mz;
4809         }
4810
4811         snprintf(mz_name, RTE_MEMZONE_NAMESIZE, "bnxt_ctx_%s_%x_%d",
4812                  suffix, idx, bp->eth_dev->data->port_id);
4813         mz = rte_memzone_lookup(mz_name);
4814         if (!mz) {
4815                 mz = rte_memzone_reserve_aligned(mz_name,
4816                                                  mem_size,
4817                                                  SOCKET_ID_ANY,
4818                                                  RTE_MEMZONE_1GB |
4819                                                  RTE_MEMZONE_SIZE_HINT_ONLY |
4820                                                  RTE_MEMZONE_IOVA_CONTIG,
4821                                                  BNXT_PAGE_SIZE);
4822                 if (mz == NULL)
4823                         return -ENOMEM;
4824         }
4825
4826         memset(mz->addr, 0, mz->len);
4827         mz_phys_addr = mz->iova;
4828
4829         for (sz = 0, i = 0; sz < mem_size; sz += BNXT_PAGE_SIZE, i++) {
4830                 rmem->pg_arr[i] = ((char *)mz->addr) + sz;
4831                 rmem->dma_arr[i] = mz_phys_addr + sz;
4832
4833                 if (rmem->nr_pages > 1) {
4834                         if (i == rmem->nr_pages - 2 &&
4835                             (rmem->flags & BNXT_RMEM_RING_PTE_FLAG))
4836                                 valid_bits |= PTU_PTE_NEXT_TO_LAST;
4837                         else if (i == rmem->nr_pages - 1 &&
4838                                  (rmem->flags & BNXT_RMEM_RING_PTE_FLAG))
4839                                 valid_bits |= PTU_PTE_LAST;
4840
4841                         rmem->pg_tbl[i] = rte_cpu_to_le_64(rmem->dma_arr[i] |
4842                                                            valid_bits);
4843                 }
4844         }
4845
4846         rmem->mz = mz;
4847         if (rmem->vmem_size)
4848                 rmem->vmem = (void **)mz->addr;
4849         rmem->dma_arr[0] = mz_phys_addr;
4850         return 0;
4851 }
4852
4853 static void bnxt_free_ctx_mem(struct bnxt *bp)
4854 {
4855         int i;
4856
4857         if (!bp->ctx || !(bp->ctx->flags & BNXT_CTX_FLAG_INITED))
4858                 return;
4859
4860         bp->ctx->flags &= ~BNXT_CTX_FLAG_INITED;
4861         rte_memzone_free(bp->ctx->qp_mem.ring_mem.mz);
4862         rte_memzone_free(bp->ctx->srq_mem.ring_mem.mz);
4863         rte_memzone_free(bp->ctx->cq_mem.ring_mem.mz);
4864         rte_memzone_free(bp->ctx->vnic_mem.ring_mem.mz);
4865         rte_memzone_free(bp->ctx->stat_mem.ring_mem.mz);
4866         rte_memzone_free(bp->ctx->qp_mem.ring_mem.pg_tbl_mz);
4867         rte_memzone_free(bp->ctx->srq_mem.ring_mem.pg_tbl_mz);
4868         rte_memzone_free(bp->ctx->cq_mem.ring_mem.pg_tbl_mz);
4869         rte_memzone_free(bp->ctx->vnic_mem.ring_mem.pg_tbl_mz);
4870         rte_memzone_free(bp->ctx->stat_mem.ring_mem.pg_tbl_mz);
4871
4872         for (i = 0; i < bp->ctx->tqm_fp_rings_count + 1; i++) {
4873                 if (bp->ctx->tqm_mem[i])
4874                         rte_memzone_free(bp->ctx->tqm_mem[i]->ring_mem.mz);
4875         }
4876
4877         rte_free(bp->ctx);
4878         bp->ctx = NULL;
4879 }
4880
4881 #define bnxt_roundup(x, y)   ((((x) + ((y) - 1)) / (y)) * (y))
4882
4883 #define min_t(type, x, y) ({                    \
4884         type __min1 = (x);                      \
4885         type __min2 = (y);                      \
4886         __min1 < __min2 ? __min1 : __min2; })
4887
4888 #define max_t(type, x, y) ({                    \
4889         type __max1 = (x);                      \
4890         type __max2 = (y);                      \
4891         __max1 > __max2 ? __max1 : __max2; })
4892
4893 #define clamp_t(type, _x, min, max)     min_t(type, max_t(type, _x, min), max)
4894
4895 int bnxt_alloc_ctx_mem(struct bnxt *bp)
4896 {
4897         struct bnxt_ctx_pg_info *ctx_pg;
4898         struct bnxt_ctx_mem_info *ctx;
4899         uint32_t mem_size, ena, entries;
4900         uint32_t entries_sp, min;
4901         int i, rc;
4902
4903         rc = bnxt_hwrm_func_backing_store_qcaps(bp);
4904         if (rc) {
4905                 PMD_DRV_LOG(ERR, "Query context mem capability failed\n");
4906                 return rc;
4907         }
4908         ctx = bp->ctx;
4909         if (!ctx || (ctx->flags & BNXT_CTX_FLAG_INITED))
4910                 return 0;
4911
4912         ctx_pg = &ctx->qp_mem;
4913         ctx_pg->entries = ctx->qp_min_qp1_entries + ctx->qp_max_l2_entries;
4914         mem_size = ctx->qp_entry_size * ctx_pg->entries;
4915         rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "qp_mem", 0);
4916         if (rc)
4917                 return rc;
4918
4919         ctx_pg = &ctx->srq_mem;
4920         ctx_pg->entries = ctx->srq_max_l2_entries;
4921         mem_size = ctx->srq_entry_size * ctx_pg->entries;
4922         rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "srq_mem", 0);
4923         if (rc)
4924                 return rc;
4925
4926         ctx_pg = &ctx->cq_mem;
4927         ctx_pg->entries = ctx->cq_max_l2_entries;
4928         mem_size = ctx->cq_entry_size * ctx_pg->entries;
4929         rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "cq_mem", 0);
4930         if (rc)
4931                 return rc;
4932
4933         ctx_pg = &ctx->vnic_mem;
4934         ctx_pg->entries = ctx->vnic_max_vnic_entries +
4935                 ctx->vnic_max_ring_table_entries;
4936         mem_size = ctx->vnic_entry_size * ctx_pg->entries;
4937         rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "vnic_mem", 0);
4938         if (rc)
4939                 return rc;
4940
4941         ctx_pg = &ctx->stat_mem;
4942         ctx_pg->entries = ctx->stat_max_entries;
4943         mem_size = ctx->stat_entry_size * ctx_pg->entries;
4944         rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "stat_mem", 0);
4945         if (rc)
4946                 return rc;
4947
4948         min = ctx->tqm_min_entries_per_ring;
4949
4950         entries_sp = ctx->qp_max_l2_entries +
4951                      ctx->vnic_max_vnic_entries +
4952                      2 * ctx->qp_min_qp1_entries + min;
4953         entries_sp = bnxt_roundup(entries_sp, ctx->tqm_entries_multiple);
4954
4955         entries = ctx->qp_max_l2_entries + ctx->qp_min_qp1_entries;
4956         entries = bnxt_roundup(entries, ctx->tqm_entries_multiple);
4957         entries = clamp_t(uint32_t, entries, min,
4958                           ctx->tqm_max_entries_per_ring);
4959         for (i = 0, ena = 0; i < ctx->tqm_fp_rings_count + 1; i++) {
4960                 ctx_pg = ctx->tqm_mem[i];
4961                 ctx_pg->entries = i ? entries : entries_sp;
4962                 mem_size = ctx->tqm_entry_size * ctx_pg->entries;
4963                 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "tqm_mem", i);
4964                 if (rc)
4965                         return rc;
4966                 ena |= HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_SP << i;
4967         }
4968
4969         ena |= FUNC_BACKING_STORE_CFG_INPUT_DFLT_ENABLES;
4970         rc = bnxt_hwrm_func_backing_store_cfg(bp, ena);
4971         if (rc)
4972                 PMD_DRV_LOG(ERR,
4973                             "Failed to configure context mem: rc = %d\n", rc);
4974         else
4975                 ctx->flags |= BNXT_CTX_FLAG_INITED;
4976
4977         return rc;
4978 }
4979
4980 static int bnxt_alloc_stats_mem(struct bnxt *bp)
4981 {
4982         struct rte_pci_device *pci_dev = bp->pdev;
4983         char mz_name[RTE_MEMZONE_NAMESIZE];
4984         const struct rte_memzone *mz = NULL;
4985         uint32_t total_alloc_len;
4986         rte_iova_t mz_phys_addr;
4987
4988         if (pci_dev->id.device_id == BROADCOM_DEV_ID_NS2)
4989                 return 0;
4990
4991         snprintf(mz_name, RTE_MEMZONE_NAMESIZE,
4992                  "bnxt_" PCI_PRI_FMT "-%s", pci_dev->addr.domain,
4993                  pci_dev->addr.bus, pci_dev->addr.devid,
4994                  pci_dev->addr.function, "rx_port_stats");
4995         mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0;
4996         mz = rte_memzone_lookup(mz_name);
4997         total_alloc_len =
4998                 RTE_CACHE_LINE_ROUNDUP(sizeof(struct rx_port_stats) +
4999                                        sizeof(struct rx_port_stats_ext) + 512);
5000         if (!mz) {
5001                 mz = rte_memzone_reserve(mz_name, total_alloc_len,
5002                                          SOCKET_ID_ANY,
5003                                          RTE_MEMZONE_2MB |
5004                                          RTE_MEMZONE_SIZE_HINT_ONLY |
5005                                          RTE_MEMZONE_IOVA_CONTIG);
5006                 if (mz == NULL)
5007                         return -ENOMEM;
5008         }
5009         memset(mz->addr, 0, mz->len);
5010         mz_phys_addr = mz->iova;
5011
5012         bp->rx_mem_zone = (const void *)mz;
5013         bp->hw_rx_port_stats = mz->addr;
5014         bp->hw_rx_port_stats_map = mz_phys_addr;
5015
5016         snprintf(mz_name, RTE_MEMZONE_NAMESIZE,
5017                  "bnxt_" PCI_PRI_FMT "-%s", pci_dev->addr.domain,
5018                  pci_dev->addr.bus, pci_dev->addr.devid,
5019                  pci_dev->addr.function, "tx_port_stats");
5020         mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0;
5021         mz = rte_memzone_lookup(mz_name);
5022         total_alloc_len =
5023                 RTE_CACHE_LINE_ROUNDUP(sizeof(struct tx_port_stats) +
5024                                        sizeof(struct tx_port_stats_ext) + 512);
5025         if (!mz) {
5026                 mz = rte_memzone_reserve(mz_name,
5027                                          total_alloc_len,
5028                                          SOCKET_ID_ANY,
5029                                          RTE_MEMZONE_2MB |
5030                                          RTE_MEMZONE_SIZE_HINT_ONLY |
5031                                          RTE_MEMZONE_IOVA_CONTIG);
5032                 if (mz == NULL)
5033                         return -ENOMEM;
5034         }
5035         memset(mz->addr, 0, mz->len);
5036         mz_phys_addr = mz->iova;
5037
5038         bp->tx_mem_zone = (const void *)mz;
5039         bp->hw_tx_port_stats = mz->addr;
5040         bp->hw_tx_port_stats_map = mz_phys_addr;
5041         bp->flags |= BNXT_FLAG_PORT_STATS;
5042
5043         /* Display extended statistics if FW supports it */
5044         if (bp->hwrm_spec_code < HWRM_SPEC_CODE_1_8_4 ||
5045             bp->hwrm_spec_code == HWRM_SPEC_CODE_1_9_0 ||
5046             !(bp->flags & BNXT_FLAG_EXT_STATS_SUPPORTED))
5047                 return 0;
5048
5049         bp->hw_rx_port_stats_ext = (void *)
5050                 ((uint8_t *)bp->hw_rx_port_stats +
5051                  sizeof(struct rx_port_stats));
5052         bp->hw_rx_port_stats_ext_map = bp->hw_rx_port_stats_map +
5053                 sizeof(struct rx_port_stats);
5054         bp->flags |= BNXT_FLAG_EXT_RX_PORT_STATS;
5055
5056         if (bp->hwrm_spec_code < HWRM_SPEC_CODE_1_9_2 ||
5057             bp->flags & BNXT_FLAG_EXT_STATS_SUPPORTED) {
5058                 bp->hw_tx_port_stats_ext = (void *)
5059                         ((uint8_t *)bp->hw_tx_port_stats +
5060                          sizeof(struct tx_port_stats));
5061                 bp->hw_tx_port_stats_ext_map =
5062                         bp->hw_tx_port_stats_map +
5063                         sizeof(struct tx_port_stats);
5064                 bp->flags |= BNXT_FLAG_EXT_TX_PORT_STATS;
5065         }
5066
5067         return 0;
5068 }
5069
5070 static int bnxt_setup_mac_addr(struct rte_eth_dev *eth_dev)
5071 {
5072         struct bnxt *bp = eth_dev->data->dev_private;
5073         int rc = 0;
5074
5075         eth_dev->data->mac_addrs = rte_zmalloc("bnxt_mac_addr_tbl",
5076                                                RTE_ETHER_ADDR_LEN *
5077                                                bp->max_l2_ctx,
5078                                                0);
5079         if (eth_dev->data->mac_addrs == NULL) {
5080                 PMD_DRV_LOG(ERR, "Failed to alloc MAC addr tbl\n");
5081                 return -ENOMEM;
5082         }
5083
5084         if (!BNXT_HAS_DFLT_MAC_SET(bp)) {
5085                 if (BNXT_PF(bp))
5086                         return -EINVAL;
5087
5088                 /* Generate a random MAC address, if none was assigned by PF */
5089                 PMD_DRV_LOG(INFO, "VF MAC address not assigned by Host PF\n");
5090                 bnxt_eth_hw_addr_random(bp->mac_addr);
5091                 PMD_DRV_LOG(INFO,
5092                             "Assign random MAC:%02X:%02X:%02X:%02X:%02X:%02X\n",
5093                             bp->mac_addr[0], bp->mac_addr[1], bp->mac_addr[2],
5094                             bp->mac_addr[3], bp->mac_addr[4], bp->mac_addr[5]);
5095
5096                 rc = bnxt_hwrm_set_mac(bp);
5097                 if (rc)
5098                         return rc;
5099         }
5100
5101         /* Copy the permanent MAC from the FUNC_QCAPS response */
5102         memcpy(&eth_dev->data->mac_addrs[0], bp->mac_addr, RTE_ETHER_ADDR_LEN);
5103
5104         return rc;
5105 }
5106
5107 static int bnxt_restore_dflt_mac(struct bnxt *bp)
5108 {
5109         int rc = 0;
5110
5111         /* MAC is already configured in FW */
5112         if (BNXT_HAS_DFLT_MAC_SET(bp))
5113                 return 0;
5114
5115         /* Restore the old MAC configured */
5116         rc = bnxt_hwrm_set_mac(bp);
5117         if (rc)
5118                 PMD_DRV_LOG(ERR, "Failed to restore MAC address\n");
5119
5120         return rc;
5121 }
5122
5123 static void bnxt_config_vf_req_fwd(struct bnxt *bp)
5124 {
5125         if (!BNXT_PF(bp))
5126                 return;
5127
5128 #define ALLOW_FUNC(x)   \
5129         { \
5130                 uint32_t arg = (x); \
5131                 bp->pf->vf_req_fwd[((arg) >> 5)] &= \
5132                 ~rte_cpu_to_le_32(1 << ((arg) & 0x1f)); \
5133         }
5134
5135         /* Forward all requests if firmware is new enough */
5136         if (((bp->fw_ver >= ((20 << 24) | (6 << 16) | (100 << 8))) &&
5137              (bp->fw_ver < ((20 << 24) | (7 << 16)))) ||
5138             ((bp->fw_ver >= ((20 << 24) | (8 << 16))))) {
5139                 memset(bp->pf->vf_req_fwd, 0xff, sizeof(bp->pf->vf_req_fwd));
5140         } else {
5141                 PMD_DRV_LOG(WARNING,
5142                             "Firmware too old for VF mailbox functionality\n");
5143                 memset(bp->pf->vf_req_fwd, 0, sizeof(bp->pf->vf_req_fwd));
5144         }
5145
5146         /*
5147          * The following are used for driver cleanup. If we disallow these,
5148          * VF drivers can't clean up cleanly.
5149          */
5150         ALLOW_FUNC(HWRM_FUNC_DRV_UNRGTR);
5151         ALLOW_FUNC(HWRM_VNIC_FREE);
5152         ALLOW_FUNC(HWRM_RING_FREE);
5153         ALLOW_FUNC(HWRM_RING_GRP_FREE);
5154         ALLOW_FUNC(HWRM_VNIC_RSS_COS_LB_CTX_FREE);
5155         ALLOW_FUNC(HWRM_CFA_L2_FILTER_FREE);
5156         ALLOW_FUNC(HWRM_STAT_CTX_FREE);
5157         ALLOW_FUNC(HWRM_PORT_PHY_QCFG);
5158         ALLOW_FUNC(HWRM_VNIC_TPA_CFG);
5159 }
5160
5161 uint16_t
5162 bnxt_get_svif(uint16_t port_id, bool func_svif,
5163               enum bnxt_ulp_intf_type type)
5164 {
5165         struct rte_eth_dev *eth_dev;
5166         struct bnxt *bp;
5167
5168         eth_dev = &rte_eth_devices[port_id];
5169         if (BNXT_ETH_DEV_IS_REPRESENTOR(eth_dev)) {
5170                 struct bnxt_vf_representor *vfr = eth_dev->data->dev_private;
5171                 if (!vfr)
5172                         return 0;
5173
5174                 if (type == BNXT_ULP_INTF_TYPE_VF_REP)
5175                         return vfr->svif;
5176
5177                 eth_dev = vfr->parent_dev;
5178         }
5179
5180         bp = eth_dev->data->dev_private;
5181
5182         return func_svif ? bp->func_svif : bp->port_svif;
5183 }
5184
5185 uint16_t
5186 bnxt_get_vnic_id(uint16_t port, enum bnxt_ulp_intf_type type)
5187 {
5188         struct rte_eth_dev *eth_dev;
5189         struct bnxt_vnic_info *vnic;
5190         struct bnxt *bp;
5191
5192         eth_dev = &rte_eth_devices[port];
5193         if (BNXT_ETH_DEV_IS_REPRESENTOR(eth_dev)) {
5194                 struct bnxt_vf_representor *vfr = eth_dev->data->dev_private;
5195                 if (!vfr)
5196                         return 0;
5197
5198                 if (type == BNXT_ULP_INTF_TYPE_VF_REP)
5199                         return vfr->dflt_vnic_id;
5200
5201                 eth_dev = vfr->parent_dev;
5202         }
5203
5204         bp = eth_dev->data->dev_private;
5205
5206         vnic = BNXT_GET_DEFAULT_VNIC(bp);
5207
5208         return vnic->fw_vnic_id;
5209 }
5210
5211 uint16_t
5212 bnxt_get_fw_func_id(uint16_t port, enum bnxt_ulp_intf_type type)
5213 {
5214         struct rte_eth_dev *eth_dev;
5215         struct bnxt *bp;
5216
5217         eth_dev = &rte_eth_devices[port];
5218         if (BNXT_ETH_DEV_IS_REPRESENTOR(eth_dev)) {
5219                 struct bnxt_vf_representor *vfr = eth_dev->data->dev_private;
5220                 if (!vfr)
5221                         return 0;
5222
5223                 if (type == BNXT_ULP_INTF_TYPE_VF_REP)
5224                         return vfr->fw_fid;
5225
5226                 eth_dev = vfr->parent_dev;
5227         }
5228
5229         bp = eth_dev->data->dev_private;
5230
5231         return bp->fw_fid;
5232 }
5233
5234 enum bnxt_ulp_intf_type
5235 bnxt_get_interface_type(uint16_t port)
5236 {
5237         struct rte_eth_dev *eth_dev;
5238         struct bnxt *bp;
5239
5240         eth_dev = &rte_eth_devices[port];
5241         if (BNXT_ETH_DEV_IS_REPRESENTOR(eth_dev))
5242                 return BNXT_ULP_INTF_TYPE_VF_REP;
5243
5244         bp = eth_dev->data->dev_private;
5245         if (BNXT_PF(bp))
5246                 return BNXT_ULP_INTF_TYPE_PF;
5247         else if (BNXT_VF_IS_TRUSTED(bp))
5248                 return BNXT_ULP_INTF_TYPE_TRUSTED_VF;
5249         else if (BNXT_VF(bp))
5250                 return BNXT_ULP_INTF_TYPE_VF;
5251
5252         return BNXT_ULP_INTF_TYPE_INVALID;
5253 }
5254
5255 uint16_t
5256 bnxt_get_phy_port_id(uint16_t port_id)
5257 {
5258         struct bnxt_vf_representor *vfr;
5259         struct rte_eth_dev *eth_dev;
5260         struct bnxt *bp;
5261
5262         eth_dev = &rte_eth_devices[port_id];
5263         if (BNXT_ETH_DEV_IS_REPRESENTOR(eth_dev)) {
5264                 vfr = eth_dev->data->dev_private;
5265                 if (!vfr)
5266                         return 0;
5267
5268                 eth_dev = vfr->parent_dev;
5269         }
5270
5271         bp = eth_dev->data->dev_private;
5272
5273         return BNXT_PF(bp) ? bp->pf->port_id : bp->parent->port_id;
5274 }
5275
5276 uint16_t
5277 bnxt_get_parif(uint16_t port_id, enum bnxt_ulp_intf_type type)
5278 {
5279         struct rte_eth_dev *eth_dev;
5280         struct bnxt *bp;
5281
5282         eth_dev = &rte_eth_devices[port_id];
5283         if (BNXT_ETH_DEV_IS_REPRESENTOR(eth_dev)) {
5284                 struct bnxt_vf_representor *vfr = eth_dev->data->dev_private;
5285                 if (!vfr)
5286                         return 0;
5287
5288                 if (type == BNXT_ULP_INTF_TYPE_VF_REP)
5289                         return vfr->fw_fid - 1;
5290
5291                 eth_dev = vfr->parent_dev;
5292         }
5293
5294         bp = eth_dev->data->dev_private;
5295
5296         return BNXT_PF(bp) ? bp->fw_fid - 1 : bp->parent->fid - 1;
5297 }
5298
5299 uint16_t
5300 bnxt_get_vport(uint16_t port_id)
5301 {
5302         return (1 << bnxt_get_phy_port_id(port_id));
5303 }
5304
5305 static void bnxt_alloc_error_recovery_info(struct bnxt *bp)
5306 {
5307         struct bnxt_error_recovery_info *info = bp->recovery_info;
5308
5309         if (info) {
5310                 if (!(bp->fw_cap & BNXT_FW_CAP_HCOMM_FW_STATUS))
5311                         memset(info, 0, sizeof(*info));
5312                 return;
5313         }
5314
5315         if (!(bp->fw_cap & BNXT_FW_CAP_ERROR_RECOVERY))
5316                 return;
5317
5318         info = rte_zmalloc("bnxt_hwrm_error_recovery_qcfg",
5319                            sizeof(*info), 0);
5320         if (!info)
5321                 bp->fw_cap &= ~BNXT_FW_CAP_ERROR_RECOVERY;
5322
5323         bp->recovery_info = info;
5324 }
5325
5326 static void bnxt_check_fw_status(struct bnxt *bp)
5327 {
5328         uint32_t fw_status;
5329
5330         if (!(bp->recovery_info &&
5331               (bp->fw_cap & BNXT_FW_CAP_HCOMM_FW_STATUS)))
5332                 return;
5333
5334         fw_status = bnxt_read_fw_status_reg(bp, BNXT_FW_STATUS_REG);
5335         if (fw_status != BNXT_FW_STATUS_HEALTHY)
5336                 PMD_DRV_LOG(ERR, "Firmware not responding, status: %#x\n",
5337                             fw_status);
5338 }
5339
5340 static int bnxt_map_hcomm_fw_status_reg(struct bnxt *bp)
5341 {
5342         struct bnxt_error_recovery_info *info = bp->recovery_info;
5343         uint32_t status_loc;
5344         uint32_t sig_ver;
5345
5346         rte_write32(HCOMM_STATUS_STRUCT_LOC, (uint8_t *)bp->bar0 +
5347                     BNXT_GRCPF_REG_WINDOW_BASE_OUT + 4);
5348         sig_ver = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
5349                                    BNXT_GRCP_WINDOW_2_BASE +
5350                                    offsetof(struct hcomm_status,
5351                                             sig_ver)));
5352         /* If the signature is absent, then FW does not support this feature */
5353         if ((sig_ver & HCOMM_STATUS_SIGNATURE_MASK) !=
5354             HCOMM_STATUS_SIGNATURE_VAL)
5355                 return 0;
5356
5357         if (!info) {
5358                 info = rte_zmalloc("bnxt_hwrm_error_recovery_qcfg",
5359                                    sizeof(*info), 0);
5360                 if (!info)
5361                         return -ENOMEM;
5362                 bp->recovery_info = info;
5363         } else {
5364                 memset(info, 0, sizeof(*info));
5365         }
5366
5367         status_loc = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
5368                                       BNXT_GRCP_WINDOW_2_BASE +
5369                                       offsetof(struct hcomm_status,
5370                                                fw_status_loc)));
5371
5372         /* Only pre-map the FW health status GRC register */
5373         if (BNXT_FW_STATUS_REG_TYPE(status_loc) != BNXT_FW_STATUS_REG_TYPE_GRC)
5374                 return 0;
5375
5376         info->status_regs[BNXT_FW_STATUS_REG] = status_loc;
5377         info->mapped_status_regs[BNXT_FW_STATUS_REG] =
5378                 BNXT_GRCP_WINDOW_2_BASE + (status_loc & BNXT_GRCP_OFFSET_MASK);
5379
5380         rte_write32((status_loc & BNXT_GRCP_BASE_MASK), (uint8_t *)bp->bar0 +
5381                     BNXT_GRCPF_REG_WINDOW_BASE_OUT + 4);
5382
5383         bp->fw_cap |= BNXT_FW_CAP_HCOMM_FW_STATUS;
5384
5385         return 0;
5386 }
5387
5388 static int bnxt_init_fw(struct bnxt *bp)
5389 {
5390         uint16_t mtu;
5391         int rc = 0;
5392
5393         bp->fw_cap = 0;
5394
5395         rc = bnxt_map_hcomm_fw_status_reg(bp);
5396         if (rc)
5397                 return rc;
5398
5399         rc = bnxt_hwrm_ver_get(bp, DFLT_HWRM_CMD_TIMEOUT);
5400         if (rc) {
5401                 bnxt_check_fw_status(bp);
5402                 return rc;
5403         }
5404
5405         rc = bnxt_hwrm_func_reset(bp);
5406         if (rc)
5407                 return -EIO;
5408
5409         rc = bnxt_hwrm_vnic_qcaps(bp);
5410         if (rc)
5411                 return rc;
5412
5413         rc = bnxt_hwrm_queue_qportcfg(bp);
5414         if (rc)
5415                 return rc;
5416
5417         /* Get the MAX capabilities for this function.
5418          * This function also allocates context memory for TQM rings and
5419          * informs the firmware about this allocated backing store memory.
5420          */
5421         rc = bnxt_hwrm_func_qcaps(bp);
5422         if (rc)
5423                 return rc;
5424
5425         rc = bnxt_hwrm_func_qcfg(bp, &mtu);
5426         if (rc)
5427                 return rc;
5428
5429         bnxt_hwrm_port_mac_qcfg(bp);
5430
5431         bnxt_hwrm_parent_pf_qcfg(bp);
5432
5433         bnxt_hwrm_port_phy_qcaps(bp);
5434
5435         bnxt_alloc_error_recovery_info(bp);
5436         /* Get the adapter error recovery support info */
5437         rc = bnxt_hwrm_error_recovery_qcfg(bp);
5438         if (rc)
5439                 bp->fw_cap &= ~BNXT_FW_CAP_ERROR_RECOVERY;
5440
5441         bnxt_hwrm_port_led_qcaps(bp);
5442
5443         return 0;
5444 }
5445
5446 static int
5447 bnxt_init_locks(struct bnxt *bp)
5448 {
5449         int err;
5450
5451         err = pthread_mutex_init(&bp->flow_lock, NULL);
5452         if (err) {
5453                 PMD_DRV_LOG(ERR, "Unable to initialize flow_lock\n");
5454                 return err;
5455         }
5456
5457         err = pthread_mutex_init(&bp->def_cp_lock, NULL);
5458         if (err)
5459                 PMD_DRV_LOG(ERR, "Unable to initialize def_cp_lock\n");
5460         return err;
5461 }
5462
5463 static int bnxt_init_resources(struct bnxt *bp, bool reconfig_dev)
5464 {
5465         int rc = 0;
5466
5467         rc = bnxt_init_fw(bp);
5468         if (rc)
5469                 return rc;
5470
5471         if (!reconfig_dev) {
5472                 rc = bnxt_setup_mac_addr(bp->eth_dev);
5473                 if (rc)
5474                         return rc;
5475         } else {
5476                 rc = bnxt_restore_dflt_mac(bp);
5477                 if (rc)
5478                         return rc;
5479         }
5480
5481         bnxt_config_vf_req_fwd(bp);
5482
5483         rc = bnxt_hwrm_func_driver_register(bp);
5484         if (rc) {
5485                 PMD_DRV_LOG(ERR, "Failed to register driver");
5486                 return -EBUSY;
5487         }
5488
5489         if (BNXT_PF(bp)) {
5490                 if (bp->pdev->max_vfs) {
5491                         rc = bnxt_hwrm_allocate_vfs(bp, bp->pdev->max_vfs);
5492                         if (rc) {
5493                                 PMD_DRV_LOG(ERR, "Failed to allocate VFs\n");
5494                                 return rc;
5495                         }
5496                 } else {
5497                         rc = bnxt_hwrm_allocate_pf_only(bp);
5498                         if (rc) {
5499                                 PMD_DRV_LOG(ERR,
5500                                             "Failed to allocate PF resources");
5501                                 return rc;
5502                         }
5503                 }
5504         }
5505
5506         rc = bnxt_alloc_mem(bp, reconfig_dev);
5507         if (rc)
5508                 return rc;
5509
5510         rc = bnxt_setup_int(bp);
5511         if (rc)
5512                 return rc;
5513
5514         rc = bnxt_request_int(bp);
5515         if (rc)
5516                 return rc;
5517
5518         rc = bnxt_init_ctx_mem(bp);
5519         if (rc) {
5520                 PMD_DRV_LOG(ERR, "Failed to init adv_flow_counters\n");
5521                 return rc;
5522         }
5523
5524         rc = bnxt_init_locks(bp);
5525         if (rc)
5526                 return rc;
5527
5528         return 0;
5529 }
5530
5531 static int
5532 bnxt_parse_devarg_truflow(__rte_unused const char *key,
5533                           const char *value, void *opaque_arg)
5534 {
5535         struct bnxt *bp = opaque_arg;
5536         unsigned long truflow;
5537         char *end = NULL;
5538
5539         if (!value || !opaque_arg) {
5540                 PMD_DRV_LOG(ERR,
5541                             "Invalid parameter passed to truflow devargs.\n");
5542                 return -EINVAL;
5543         }
5544
5545         truflow = strtoul(value, &end, 10);
5546         if (end == NULL || *end != '\0' ||
5547             (truflow == ULONG_MAX && errno == ERANGE)) {
5548                 PMD_DRV_LOG(ERR,
5549                             "Invalid parameter passed to truflow devargs.\n");
5550                 return -EINVAL;
5551         }
5552
5553         if (BNXT_DEVARG_TRUFLOW_INVALID(truflow)) {
5554                 PMD_DRV_LOG(ERR,
5555                             "Invalid value passed to truflow devargs.\n");
5556                 return -EINVAL;
5557         }
5558
5559         bp->flags |= BNXT_FLAG_TRUFLOW_EN;
5560         if (BNXT_TRUFLOW_EN(bp))
5561                 PMD_DRV_LOG(INFO, "Host-based truflow feature enabled.\n");
5562
5563         return 0;
5564 }
5565
5566 static int
5567 bnxt_parse_devarg_flow_xstat(__rte_unused const char *key,
5568                              const char *value, void *opaque_arg)
5569 {
5570         struct bnxt *bp = opaque_arg;
5571         unsigned long flow_xstat;
5572         char *end = NULL;
5573
5574         if (!value || !opaque_arg) {
5575                 PMD_DRV_LOG(ERR,
5576                             "Invalid parameter passed to flow_xstat devarg.\n");
5577                 return -EINVAL;
5578         }
5579
5580         flow_xstat = strtoul(value, &end, 10);
5581         if (end == NULL || *end != '\0' ||
5582             (flow_xstat == ULONG_MAX && errno == ERANGE)) {
5583                 PMD_DRV_LOG(ERR,
5584                             "Invalid parameter passed to flow_xstat devarg.\n");
5585                 return -EINVAL;
5586         }
5587
5588         if (BNXT_DEVARG_FLOW_XSTAT_INVALID(flow_xstat)) {
5589                 PMD_DRV_LOG(ERR,
5590                             "Invalid value passed to flow_xstat devarg.\n");
5591                 return -EINVAL;
5592         }
5593
5594         bp->flags |= BNXT_FLAG_FLOW_XSTATS_EN;
5595         if (BNXT_FLOW_XSTATS_EN(bp))
5596                 PMD_DRV_LOG(INFO, "flow_xstat feature enabled.\n");
5597
5598         return 0;
5599 }
5600
5601 static int
5602 bnxt_parse_devarg_max_num_kflows(__rte_unused const char *key,
5603                                         const char *value, void *opaque_arg)
5604 {
5605         struct bnxt *bp = opaque_arg;
5606         unsigned long max_num_kflows;
5607         char *end = NULL;
5608
5609         if (!value || !opaque_arg) {
5610                 PMD_DRV_LOG(ERR,
5611                         "Invalid parameter passed to max_num_kflows devarg.\n");
5612                 return -EINVAL;
5613         }
5614
5615         max_num_kflows = strtoul(value, &end, 10);
5616         if (end == NULL || *end != '\0' ||
5617                 (max_num_kflows == ULONG_MAX && errno == ERANGE)) {
5618                 PMD_DRV_LOG(ERR,
5619                         "Invalid parameter passed to max_num_kflows devarg.\n");
5620                 return -EINVAL;
5621         }
5622
5623         if (bnxt_devarg_max_num_kflow_invalid(max_num_kflows)) {
5624                 PMD_DRV_LOG(ERR,
5625                         "Invalid value passed to max_num_kflows devarg.\n");
5626                 return -EINVAL;
5627         }
5628
5629         bp->max_num_kflows = max_num_kflows;
5630         if (bp->max_num_kflows)
5631                 PMD_DRV_LOG(INFO, "max_num_kflows set as %ldK.\n",
5632                                 max_num_kflows);
5633
5634         return 0;
5635 }
5636
5637 static void
5638 bnxt_parse_dev_args(struct bnxt *bp, struct rte_devargs *devargs)
5639 {
5640         struct rte_kvargs *kvlist;
5641
5642         if (devargs == NULL)
5643                 return;
5644
5645         kvlist = rte_kvargs_parse(devargs->args, bnxt_dev_args);
5646         if (kvlist == NULL)
5647                 return;
5648
5649         /*
5650          * Handler for "truflow" devarg.
5651          * Invoked as for ex: "-w 0000:00:0d.0,host-based-truflow=1"
5652          */
5653         rte_kvargs_process(kvlist, BNXT_DEVARG_TRUFLOW,
5654                            bnxt_parse_devarg_truflow, bp);
5655
5656         /*
5657          * Handler for "flow_xstat" devarg.
5658          * Invoked as for ex: "-w 0000:00:0d.0,flow_xstat=1"
5659          */
5660         rte_kvargs_process(kvlist, BNXT_DEVARG_FLOW_XSTAT,
5661                            bnxt_parse_devarg_flow_xstat, bp);
5662
5663         /*
5664          * Handler for "max_num_kflows" devarg.
5665          * Invoked as for ex: "-w 000:00:0d.0,max_num_kflows=32"
5666          */
5667         rte_kvargs_process(kvlist, BNXT_DEVARG_MAX_NUM_KFLOWS,
5668                            bnxt_parse_devarg_max_num_kflows, bp);
5669
5670         rte_kvargs_free(kvlist);
5671 }
5672
5673 static int bnxt_alloc_switch_domain(struct bnxt *bp)
5674 {
5675         int rc = 0;
5676
5677         if (BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp)) {
5678                 rc = rte_eth_switch_domain_alloc(&bp->switch_domain_id);
5679                 if (rc)
5680                         PMD_DRV_LOG(ERR,
5681                                     "Failed to alloc switch domain: %d\n", rc);
5682                 else
5683                         PMD_DRV_LOG(INFO,
5684                                     "Switch domain allocated %d\n",
5685                                     bp->switch_domain_id);
5686         }
5687
5688         return rc;
5689 }
5690
5691 static int
5692 bnxt_dev_init(struct rte_eth_dev *eth_dev, void *params __rte_unused)
5693 {
5694         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
5695         static int version_printed;
5696         struct bnxt *bp;
5697         int rc;
5698
5699         if (version_printed++ == 0)
5700                 PMD_DRV_LOG(INFO, "%s\n", bnxt_version);
5701
5702         eth_dev->dev_ops = &bnxt_dev_ops;
5703         eth_dev->rx_queue_count = bnxt_rx_queue_count_op;
5704         eth_dev->rx_descriptor_status = bnxt_rx_descriptor_status_op;
5705         eth_dev->tx_descriptor_status = bnxt_tx_descriptor_status_op;
5706         eth_dev->rx_pkt_burst = &bnxt_recv_pkts;
5707         eth_dev->tx_pkt_burst = &bnxt_xmit_pkts;
5708
5709         /*
5710          * For secondary processes, we don't initialise any further
5711          * as primary has already done this work.
5712          */
5713         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
5714                 return 0;
5715
5716         rte_eth_copy_pci_info(eth_dev, pci_dev);
5717
5718         bp = eth_dev->data->dev_private;
5719
5720         /* Parse dev arguments passed on when starting the DPDK application. */
5721         bnxt_parse_dev_args(bp, pci_dev->device.devargs);
5722
5723         bp->flags &= ~BNXT_FLAG_RX_VECTOR_PKT_MODE;
5724
5725         if (bnxt_vf_pciid(pci_dev->id.device_id))
5726                 bp->flags |= BNXT_FLAG_VF;
5727
5728         if (bnxt_thor_device(pci_dev->id.device_id))
5729                 bp->flags |= BNXT_FLAG_THOR_CHIP;
5730
5731         if (pci_dev->id.device_id == BROADCOM_DEV_ID_58802 ||
5732             pci_dev->id.device_id == BROADCOM_DEV_ID_58804 ||
5733             pci_dev->id.device_id == BROADCOM_DEV_ID_58808 ||
5734             pci_dev->id.device_id == BROADCOM_DEV_ID_58802_VF)
5735                 bp->flags |= BNXT_FLAG_STINGRAY;
5736
5737         rc = bnxt_init_board(eth_dev);
5738         if (rc) {
5739                 PMD_DRV_LOG(ERR,
5740                             "Failed to initialize board rc: %x\n", rc);
5741                 return rc;
5742         }
5743
5744         rc = bnxt_alloc_pf_info(bp);
5745         if (rc)
5746                 goto error_free;
5747
5748         rc = bnxt_alloc_link_info(bp);
5749         if (rc)
5750                 goto error_free;
5751
5752         rc = bnxt_alloc_parent_info(bp);
5753         if (rc)
5754                 goto error_free;
5755
5756         rc = bnxt_alloc_hwrm_resources(bp);
5757         if (rc) {
5758                 PMD_DRV_LOG(ERR,
5759                             "Failed to allocate hwrm resource rc: %x\n", rc);
5760                 goto error_free;
5761         }
5762         rc = bnxt_alloc_leds_info(bp);
5763         if (rc)
5764                 goto error_free;
5765
5766         rc = bnxt_alloc_cos_queues(bp);
5767         if (rc)
5768                 goto error_free;
5769
5770         rc = bnxt_init_resources(bp, false);
5771         if (rc)
5772                 goto error_free;
5773
5774         rc = bnxt_alloc_stats_mem(bp);
5775         if (rc)
5776                 goto error_free;
5777
5778         bnxt_alloc_switch_domain(bp);
5779
5780         /* Pass the information to the rte_eth_dev_close() that it should also
5781          * release the private port resources.
5782          */
5783         eth_dev->data->dev_flags |= RTE_ETH_DEV_CLOSE_REMOVE;
5784
5785         PMD_DRV_LOG(INFO,
5786                     DRV_MODULE_NAME "found at mem %" PRIX64 ", node addr %pM\n",
5787                     pci_dev->mem_resource[0].phys_addr,
5788                     pci_dev->mem_resource[0].addr);
5789
5790         return 0;
5791
5792 error_free:
5793         bnxt_dev_uninit(eth_dev);
5794         return rc;
5795 }
5796
5797
5798 static void bnxt_free_ctx_mem_buf(struct bnxt_ctx_mem_buf_info *ctx)
5799 {
5800         if (!ctx)
5801                 return;
5802
5803         if (ctx->va)
5804                 rte_free(ctx->va);
5805
5806         ctx->va = NULL;
5807         ctx->dma = RTE_BAD_IOVA;
5808         ctx->ctx_id = BNXT_CTX_VAL_INVAL;
5809 }
5810
5811 static void bnxt_unregister_fc_ctx_mem(struct bnxt *bp)
5812 {
5813         bnxt_hwrm_cfa_counter_cfg(bp, BNXT_DIR_RX,
5814                                   CFA_COUNTER_CFG_IN_COUNTER_TYPE_FC,
5815                                   bp->flow_stat->rx_fc_out_tbl.ctx_id,
5816                                   bp->flow_stat->max_fc,
5817                                   false);
5818
5819         bnxt_hwrm_cfa_counter_cfg(bp, BNXT_DIR_TX,
5820                                   CFA_COUNTER_CFG_IN_COUNTER_TYPE_FC,
5821                                   bp->flow_stat->tx_fc_out_tbl.ctx_id,
5822                                   bp->flow_stat->max_fc,
5823                                   false);
5824
5825         if (bp->flow_stat->rx_fc_in_tbl.ctx_id != BNXT_CTX_VAL_INVAL)
5826                 bnxt_hwrm_ctx_unrgtr(bp, bp->flow_stat->rx_fc_in_tbl.ctx_id);
5827         bp->flow_stat->rx_fc_in_tbl.ctx_id = BNXT_CTX_VAL_INVAL;
5828
5829         if (bp->flow_stat->rx_fc_out_tbl.ctx_id != BNXT_CTX_VAL_INVAL)
5830                 bnxt_hwrm_ctx_unrgtr(bp, bp->flow_stat->rx_fc_out_tbl.ctx_id);
5831         bp->flow_stat->rx_fc_out_tbl.ctx_id = BNXT_CTX_VAL_INVAL;
5832
5833         if (bp->flow_stat->tx_fc_in_tbl.ctx_id != BNXT_CTX_VAL_INVAL)
5834                 bnxt_hwrm_ctx_unrgtr(bp, bp->flow_stat->tx_fc_in_tbl.ctx_id);
5835         bp->flow_stat->tx_fc_in_tbl.ctx_id = BNXT_CTX_VAL_INVAL;
5836
5837         if (bp->flow_stat->tx_fc_out_tbl.ctx_id != BNXT_CTX_VAL_INVAL)
5838                 bnxt_hwrm_ctx_unrgtr(bp, bp->flow_stat->tx_fc_out_tbl.ctx_id);
5839         bp->flow_stat->tx_fc_out_tbl.ctx_id = BNXT_CTX_VAL_INVAL;
5840 }
5841
5842 static void bnxt_uninit_fc_ctx_mem(struct bnxt *bp)
5843 {
5844         bnxt_unregister_fc_ctx_mem(bp);
5845
5846         bnxt_free_ctx_mem_buf(&bp->flow_stat->rx_fc_in_tbl);
5847         bnxt_free_ctx_mem_buf(&bp->flow_stat->rx_fc_out_tbl);
5848         bnxt_free_ctx_mem_buf(&bp->flow_stat->tx_fc_in_tbl);
5849         bnxt_free_ctx_mem_buf(&bp->flow_stat->tx_fc_out_tbl);
5850 }
5851
5852 static void bnxt_uninit_ctx_mem(struct bnxt *bp)
5853 {
5854         if (BNXT_FLOW_XSTATS_EN(bp))
5855                 bnxt_uninit_fc_ctx_mem(bp);
5856 }
5857
5858 static void
5859 bnxt_free_error_recovery_info(struct bnxt *bp)
5860 {
5861         rte_free(bp->recovery_info);
5862         bp->recovery_info = NULL;
5863         bp->fw_cap &= ~BNXT_FW_CAP_ERROR_RECOVERY;
5864 }
5865
5866 static void
5867 bnxt_uninit_locks(struct bnxt *bp)
5868 {
5869         pthread_mutex_destroy(&bp->flow_lock);
5870         pthread_mutex_destroy(&bp->def_cp_lock);
5871         if (bp->rep_info) {
5872                 pthread_mutex_destroy(&bp->rep_info->vfr_lock);
5873                 pthread_mutex_destroy(&bp->rep_info->vfr_start_lock);
5874         }
5875 }
5876
5877 static int
5878 bnxt_uninit_resources(struct bnxt *bp, bool reconfig_dev)
5879 {
5880         int rc;
5881
5882         bnxt_free_int(bp);
5883         bnxt_free_mem(bp, reconfig_dev);
5884         bnxt_hwrm_func_buf_unrgtr(bp);
5885         rc = bnxt_hwrm_func_driver_unregister(bp, 0);
5886         bp->flags &= ~BNXT_FLAG_REGISTERED;
5887         bnxt_free_ctx_mem(bp);
5888         if (!reconfig_dev) {
5889                 bnxt_free_hwrm_resources(bp);
5890                 bnxt_free_error_recovery_info(bp);
5891         }
5892
5893         bnxt_uninit_ctx_mem(bp);
5894
5895         bnxt_uninit_locks(bp);
5896         bnxt_free_flow_stats_info(bp);
5897         bnxt_free_rep_info(bp);
5898         rte_free(bp->ptp_cfg);
5899         bp->ptp_cfg = NULL;
5900         return rc;
5901 }
5902
5903 static int
5904 bnxt_dev_uninit(struct rte_eth_dev *eth_dev)
5905 {
5906         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
5907                 return -EPERM;
5908
5909         PMD_DRV_LOG(DEBUG, "Calling Device uninit\n");
5910
5911         if (eth_dev->state != RTE_ETH_DEV_UNUSED)
5912                 bnxt_dev_close_op(eth_dev);
5913
5914         return 0;
5915 }
5916
5917 static int bnxt_pci_remove_dev_with_reps(struct rte_eth_dev *eth_dev)
5918 {
5919         struct bnxt *bp = eth_dev->data->dev_private;
5920         struct rte_eth_dev *vf_rep_eth_dev;
5921         int ret = 0, i;
5922
5923         if (!bp)
5924                 return -EINVAL;
5925
5926         for (i = 0; i < bp->num_reps; i++) {
5927                 vf_rep_eth_dev = bp->rep_info[i].vfr_eth_dev;
5928                 if (!vf_rep_eth_dev)
5929                         continue;
5930                 rte_eth_dev_destroy(vf_rep_eth_dev, bnxt_vf_representor_uninit);
5931         }
5932         ret = rte_eth_dev_destroy(eth_dev, bnxt_dev_uninit);
5933
5934         return ret;
5935 }
5936
5937 static void bnxt_free_rep_info(struct bnxt *bp)
5938 {
5939         rte_free(bp->rep_info);
5940         bp->rep_info = NULL;
5941         rte_free(bp->cfa_code_map);
5942         bp->cfa_code_map = NULL;
5943 }
5944
5945 static int bnxt_init_rep_info(struct bnxt *bp)
5946 {
5947         int i = 0, rc;
5948
5949         if (bp->rep_info)
5950                 return 0;
5951
5952         bp->rep_info = rte_zmalloc("bnxt_rep_info",
5953                                    sizeof(bp->rep_info[0]) * BNXT_MAX_VF_REPS,
5954                                    0);
5955         if (!bp->rep_info) {
5956                 PMD_DRV_LOG(ERR, "Failed to alloc memory for rep info\n");
5957                 return -ENOMEM;
5958         }
5959         bp->cfa_code_map = rte_zmalloc("bnxt_cfa_code_map",
5960                                        sizeof(*bp->cfa_code_map) *
5961                                        BNXT_MAX_CFA_CODE, 0);
5962         if (!bp->cfa_code_map) {
5963                 PMD_DRV_LOG(ERR, "Failed to alloc memory for cfa_code_map\n");
5964                 bnxt_free_rep_info(bp);
5965                 return -ENOMEM;
5966         }
5967
5968         for (i = 0; i < BNXT_MAX_CFA_CODE; i++)
5969                 bp->cfa_code_map[i] = BNXT_VF_IDX_INVALID;
5970
5971         rc = pthread_mutex_init(&bp->rep_info->vfr_lock, NULL);
5972         if (rc) {
5973                 PMD_DRV_LOG(ERR, "Unable to initialize vfr_lock\n");
5974                 bnxt_free_rep_info(bp);
5975                 return rc;
5976         }
5977
5978         rc = pthread_mutex_init(&bp->rep_info->vfr_start_lock, NULL);
5979         if (rc) {
5980                 PMD_DRV_LOG(ERR, "Unable to initialize vfr_start_lock\n");
5981                 bnxt_free_rep_info(bp);
5982                 return rc;
5983         }
5984
5985         return rc;
5986 }
5987
5988 static int bnxt_rep_port_probe(struct rte_pci_device *pci_dev,
5989                                struct rte_eth_devargs eth_da,
5990                                struct rte_eth_dev *backing_eth_dev)
5991 {
5992         struct rte_eth_dev *vf_rep_eth_dev;
5993         char name[RTE_ETH_NAME_MAX_LEN];
5994         struct bnxt *backing_bp;
5995         uint16_t num_rep;
5996         int i, ret = 0;
5997
5998         num_rep = eth_da.nb_representor_ports;
5999         if (num_rep > BNXT_MAX_VF_REPS) {
6000                 PMD_DRV_LOG(ERR, "nb_representor_ports = %d > %d MAX VF REPS\n",
6001                             num_rep, BNXT_MAX_VF_REPS);
6002                 return -EINVAL;
6003         }
6004
6005         if (num_rep > RTE_MAX_ETHPORTS) {
6006                 PMD_DRV_LOG(ERR,
6007                             "nb_representor_ports = %d > %d MAX ETHPORTS\n",
6008                             num_rep, RTE_MAX_ETHPORTS);
6009                 return -EINVAL;
6010         }
6011
6012         backing_bp = backing_eth_dev->data->dev_private;
6013
6014         if (!(BNXT_PF(backing_bp) || BNXT_VF_IS_TRUSTED(backing_bp))) {
6015                 PMD_DRV_LOG(ERR,
6016                             "Not a PF or trusted VF. No Representor support\n");
6017                 /* Returning an error is not an option.
6018                  * Applications are not handling this correctly
6019                  */
6020                 return 0;
6021         }
6022
6023         if (bnxt_init_rep_info(backing_bp))
6024                 return 0;
6025
6026         for (i = 0; i < num_rep; i++) {
6027                 struct bnxt_vf_representor representor = {
6028                         .vf_id = eth_da.representor_ports[i],
6029                         .switch_domain_id = backing_bp->switch_domain_id,
6030                         .parent_dev = backing_eth_dev
6031                 };
6032
6033                 if (representor.vf_id >= BNXT_MAX_VF_REPS) {
6034                         PMD_DRV_LOG(ERR, "VF-Rep id %d >= %d MAX VF ID\n",
6035                                     representor.vf_id, BNXT_MAX_VF_REPS);
6036                         continue;
6037                 }
6038
6039                 /* representor port net_bdf_port */
6040                 snprintf(name, sizeof(name), "net_%s_representor_%d",
6041                          pci_dev->device.name, eth_da.representor_ports[i]);
6042
6043                 ret = rte_eth_dev_create(&pci_dev->device, name,
6044                                          sizeof(struct bnxt_vf_representor),
6045                                          NULL, NULL,
6046                                          bnxt_vf_representor_init,
6047                                          &representor);
6048
6049                 if (!ret) {
6050                         vf_rep_eth_dev = rte_eth_dev_allocated(name);
6051                         if (!vf_rep_eth_dev) {
6052                                 PMD_DRV_LOG(ERR, "Failed to find the eth_dev"
6053                                             " for VF-Rep: %s.", name);
6054                                 bnxt_pci_remove_dev_with_reps(backing_eth_dev);
6055                                 ret = -ENODEV;
6056                                 return ret;
6057                         }
6058                         backing_bp->rep_info[representor.vf_id].vfr_eth_dev =
6059                                 vf_rep_eth_dev;
6060                         backing_bp->num_reps++;
6061                 } else {
6062                         PMD_DRV_LOG(ERR, "failed to create bnxt vf "
6063                                     "representor %s.", name);
6064                         bnxt_pci_remove_dev_with_reps(backing_eth_dev);
6065                 }
6066         }
6067
6068         return ret;
6069 }
6070
6071 static int bnxt_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
6072                           struct rte_pci_device *pci_dev)
6073 {
6074         struct rte_eth_devargs eth_da = { .nb_representor_ports = 0 };
6075         struct rte_eth_dev *backing_eth_dev;
6076         uint16_t num_rep;
6077         int ret = 0;
6078
6079         if (pci_dev->device.devargs) {
6080                 ret = rte_eth_devargs_parse(pci_dev->device.devargs->args,
6081                                             &eth_da);
6082                 if (ret)
6083                         return ret;
6084         }
6085
6086         num_rep = eth_da.nb_representor_ports;
6087         PMD_DRV_LOG(DEBUG, "nb_representor_ports = %d\n",
6088                     num_rep);
6089
6090         /* We could come here after first level of probe is already invoked
6091          * as part of an application bringup(OVS-DPDK vswitchd), so first check
6092          * for already allocated eth_dev for the backing device (PF/Trusted VF)
6093          */
6094         backing_eth_dev = rte_eth_dev_allocated(pci_dev->device.name);
6095         if (backing_eth_dev == NULL) {
6096                 ret = rte_eth_dev_create(&pci_dev->device, pci_dev->device.name,
6097                                          sizeof(struct bnxt),
6098                                          eth_dev_pci_specific_init, pci_dev,
6099                                          bnxt_dev_init, NULL);
6100
6101                 if (ret || !num_rep)
6102                         return ret;
6103
6104                 backing_eth_dev = rte_eth_dev_allocated(pci_dev->device.name);
6105         }
6106
6107         /* probe representor ports now */
6108         ret = bnxt_rep_port_probe(pci_dev, eth_da, backing_eth_dev);
6109
6110         return ret;
6111 }
6112
6113 static int bnxt_pci_remove(struct rte_pci_device *pci_dev)
6114 {
6115         struct rte_eth_dev *eth_dev;
6116
6117         eth_dev = rte_eth_dev_allocated(pci_dev->device.name);
6118         if (!eth_dev)
6119                 return 0; /* Invoked typically only by OVS-DPDK, by the
6120                            * time it comes here the eth_dev is already
6121                            * deleted by rte_eth_dev_close(), so returning
6122                            * +ve value will at least help in proper cleanup
6123                            */
6124
6125         if (rte_eal_process_type() == RTE_PROC_PRIMARY) {
6126                 if (eth_dev->data->dev_flags & RTE_ETH_DEV_REPRESENTOR)
6127                         return rte_eth_dev_destroy(eth_dev,
6128                                                    bnxt_vf_representor_uninit);
6129                 else
6130                         return rte_eth_dev_destroy(eth_dev,
6131                                                    bnxt_dev_uninit);
6132         } else {
6133                 return rte_eth_dev_pci_generic_remove(pci_dev, NULL);
6134         }
6135 }
6136
6137 static struct rte_pci_driver bnxt_rte_pmd = {
6138         .id_table = bnxt_pci_id_map,
6139         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC |
6140                         RTE_PCI_DRV_PROBE_AGAIN, /* Needed in case of VF-REPs
6141                                                   * and OVS-DPDK
6142                                                   */
6143         .probe = bnxt_pci_probe,
6144         .remove = bnxt_pci_remove,
6145 };
6146
6147 static bool
6148 is_device_supported(struct rte_eth_dev *dev, struct rte_pci_driver *drv)
6149 {
6150         if (strcmp(dev->device->driver->name, drv->driver.name))
6151                 return false;
6152
6153         return true;
6154 }
6155
6156 bool is_bnxt_supported(struct rte_eth_dev *dev)
6157 {
6158         return is_device_supported(dev, &bnxt_rte_pmd);
6159 }
6160
6161 RTE_LOG_REGISTER(bnxt_logtype_driver, pmd.net.bnxt.driver, NOTICE);
6162 RTE_PMD_REGISTER_PCI(net_bnxt, bnxt_rte_pmd);
6163 RTE_PMD_REGISTER_PCI_TABLE(net_bnxt, bnxt_pci_id_map);
6164 RTE_PMD_REGISTER_KMOD_DEP(net_bnxt, "* igb_uio | uio_pci_generic | vfio-pci");