drivers/net/bnxt/bnxt_ethdev.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2014-2018 Broadcom
   3  * All rights reserved.
   4  */
   5
   6 #include <inttypes.h>
   7 #include <stdbool.h>
   8
   9 #include <rte_dev.h>
  10 #include <rte_ethdev_driver.h>
  11 #include <rte_ethdev_pci.h>
  12 #include <rte_malloc.h>
  13 #include <rte_cycles.h>
  14 #include <rte_alarm.h>
  15 #include <rte_kvargs.h>
  16
  17 #include "bnxt.h"
  18 #include "bnxt_filter.h"
  19 #include "bnxt_hwrm.h"
  20 #include "bnxt_irq.h"
  21 #include "bnxt_reps.h"
  22 #include "bnxt_ring.h"
  23 #include "bnxt_rxq.h"
  24 #include "bnxt_rxr.h"
  25 #include "bnxt_stats.h"
  26 #include "bnxt_txq.h"
  27 #include "bnxt_txr.h"
  28 #include "bnxt_vnic.h"
  29 #include "hsi_struct_def_dpdk.h"
  30 #include "bnxt_nvm_defs.h"
  31 #include "bnxt_tf_common.h"
  32 #include "ulp_flow_db.h"
  33
  34 #define DRV_MODULE_NAME         "bnxt"
  35 static const char bnxt_version[] =
  36         "Broadcom NetXtreme driver " DRV_MODULE_NAME;
  37
  38 /*
  39  * The set of PCI devices this driver supports
  40  */
  41 static const struct rte_pci_id bnxt_pci_id_map[] = {
  42         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM,
  43                          BROADCOM_DEV_ID_STRATUS_NIC_VF1) },
  44         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM,
  45                          BROADCOM_DEV_ID_STRATUS_NIC_VF2) },
  46         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_STRATUS_NIC) },
  47         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414_VF) },
  48         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57301) },
  49         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57302) },
  50         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57304_PF) },
  51         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57304_VF) },
  52         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_NS2) },
  53         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57402) },
  54         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57404) },
  55         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57406_PF) },
  56         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57406_VF) },
  57         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57402_MF) },
  58         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57407_RJ45) },
  59         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57404_MF) },
  60         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57406_MF) },
  61         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57407_SFP) },
  62         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57407_MF) },
  63         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_5741X_VF) },
  64         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_5731X_VF) },
  65         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57314) },
  66         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_MF) },
  67         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57311) },
  68         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57312) },
  69         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57412) },
  70         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414) },
  71         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_RJ45) },
  72         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_RJ45) },
  73         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57412_MF) },
  74         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57317_RJ45) },
  75         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_SFP) },
  76         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_SFP) },
  77         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57317_SFP) },
  78         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414_MF) },
  79         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_MF) },
  80         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58802) },
  81         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58804) },
  82         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58808) },
  83         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58802_VF) },
  84         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57508) },
  85         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57504) },
  86         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57502) },
  87         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57500_VF1) },
  88         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57500_VF2) },
  89         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57508_MF1) },
  90         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57504_MF1) },
  91         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57502_MF1) },
  92         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57508_MF2) },
  93         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57504_MF2) },
  94         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57502_MF2) },
  95         { .vendor_id = 0, /* sentinel */ },
  96 };
  97
  98 #define BNXT_DEVARG_TRUFLOW     "host-based-truflow"
  99 #define BNXT_DEVARG_FLOW_XSTAT  "flow-xstat"
 100 #define BNXT_DEVARG_MAX_NUM_KFLOWS  "max-num-kflows"
 101 #define BNXT_DEVARG_REPRESENTOR "representor"
 102 #define BNXT_DEVARG_REP_BASED_PF  "rep-based-pf"
 103 #define BNXT_DEVARG_REP_IS_PF  "rep-is-pf"
 104 #define BNXT_DEVARG_REP_Q_R2F  "rep-q-r2f"
 105 #define BNXT_DEVARG_REP_Q_F2R  "rep-q-f2r"
 106 #define BNXT_DEVARG_REP_FC_R2F  "rep-fc-r2f"
 107 #define BNXT_DEVARG_REP_FC_F2R  "rep-fc-f2r"
 108
 109 static const char *const bnxt_dev_args[] = {
 110         BNXT_DEVARG_REPRESENTOR,
 111         BNXT_DEVARG_TRUFLOW,
 112         BNXT_DEVARG_FLOW_XSTAT,
 113         BNXT_DEVARG_MAX_NUM_KFLOWS,
 114         BNXT_DEVARG_REP_BASED_PF,
 115         BNXT_DEVARG_REP_IS_PF,
 116         BNXT_DEVARG_REP_Q_R2F,
 117         BNXT_DEVARG_REP_Q_F2R,
 118         BNXT_DEVARG_REP_FC_R2F,
 119         BNXT_DEVARG_REP_FC_F2R,
 120         NULL
 121 };
 122
 123 /*
 124  * truflow == false to disable the feature
 125  * truflow == true to enable the feature
 126  */
 127 #define BNXT_DEVARG_TRUFLOW_INVALID(truflow)    ((truflow) > 1)
 128
 129 /*
 130  * flow_xstat == false to disable the feature
 131  * flow_xstat == true to enable the feature
 132  */
 133 #define BNXT_DEVARG_FLOW_XSTAT_INVALID(flow_xstat)      ((flow_xstat) > 1)
 134
 135 /*
 136  * rep_is_pf == false to indicate VF representor
 137  * rep_is_pf == true to indicate PF representor
 138  */
 139 #define BNXT_DEVARG_REP_IS_PF_INVALID(rep_is_pf)        ((rep_is_pf) > 1)
 140
 141 /*
 142  * rep_based_pf == Physical index of the PF
 143  */
 144 #define BNXT_DEVARG_REP_BASED_PF_INVALID(rep_based_pf)  ((rep_based_pf) > 15)
 145 /*
 146  * rep_q_r2f == Logical COS Queue index for the rep to endpoint direction
 147  */
 148 #define BNXT_DEVARG_REP_Q_R2F_INVALID(rep_q_r2f)        ((rep_q_r2f) > 3)
 149
 150 /*
 151  * rep_q_f2r == Logical COS Queue index for the endpoint to rep direction
 152  */
 153 #define BNXT_DEVARG_REP_Q_F2R_INVALID(rep_q_f2r)        ((rep_q_f2r) > 3)
 154
 155 /*
 156  * rep_fc_r2f == Flow control for the representor to endpoint direction
 157  */
 158 #define BNXT_DEVARG_REP_FC_R2F_INVALID(rep_fc_r2f)      ((rep_fc_r2f) > 1)
 159
 160 /*
 161  * rep_fc_f2r == Flow control for the endpoint to representor direction
 162  */
 163 #define BNXT_DEVARG_REP_FC_F2R_INVALID(rep_fc_f2r)      ((rep_fc_f2r) > 1)
 164
 165 /*
 166  * max_num_kflows must be >= 32
 167  * and must be a power-of-2 supported value
 168  * return: 1 -> invalid
 169  *         0 -> valid
 170  */
 171 static int bnxt_devarg_max_num_kflow_invalid(uint16_t max_num_kflows)
 172 {
 173         if (max_num_kflows < 32 || !rte_is_power_of_2(max_num_kflows))
 174                 return 1;
 175         return 0;
 176 }
 177
 178 static int bnxt_vlan_offload_set_op(struct rte_eth_dev *dev, int mask);
 179 static int bnxt_dev_uninit(struct rte_eth_dev *eth_dev);
 180 static int bnxt_init_resources(struct bnxt *bp, bool reconfig_dev);
 181 static int bnxt_uninit_resources(struct bnxt *bp, bool reconfig_dev);
 182 static void bnxt_cancel_fw_health_check(struct bnxt *bp);
 183 static int bnxt_restore_vlan_filters(struct bnxt *bp);
 184 static void bnxt_dev_recover(void *arg);
 185 static void bnxt_free_error_recovery_info(struct bnxt *bp);
 186 static void bnxt_free_rep_info(struct bnxt *bp);
 187
 188 int is_bnxt_in_error(struct bnxt *bp)
 189 {
 190         if (bp->flags & BNXT_FLAG_FATAL_ERROR)
 191                 return -EIO;
 192         if (bp->flags & BNXT_FLAG_FW_RESET)
 193                 return -EBUSY;
 194
 195         return 0;
 196 }
 197
 198 /***********************/
 199
 200 /*
 201  * High level utility functions
 202  */
 203
 204 static uint16_t bnxt_rss_ctxts(const struct bnxt *bp)
 205 {
 206         if (!BNXT_CHIP_THOR(bp))
 207                 return 1;
 208
 209         return RTE_ALIGN_MUL_CEIL(bp->rx_nr_rings,
 210                                   BNXT_RSS_ENTRIES_PER_CTX_THOR) /
 211                                     BNXT_RSS_ENTRIES_PER_CTX_THOR;
 212 }
 213
 214 uint16_t bnxt_rss_hash_tbl_size(const struct bnxt *bp)
 215 {
 216         if (!BNXT_CHIP_THOR(bp))
 217                 return HW_HASH_INDEX_SIZE;
 218
 219         return bnxt_rss_ctxts(bp) * BNXT_RSS_ENTRIES_PER_CTX_THOR;
 220 }
 221
 222 static void bnxt_free_parent_info(struct bnxt *bp)
 223 {
 224         rte_free(bp->parent);
 225 }
 226
 227 static void bnxt_free_pf_info(struct bnxt *bp)
 228 {
 229         rte_free(bp->pf);
 230 }
 231
 232 static void bnxt_free_link_info(struct bnxt *bp)
 233 {
 234         rte_free(bp->link_info);
 235 }
 236
 237 static void bnxt_free_leds_info(struct bnxt *bp)
 238 {
 239         if (BNXT_VF(bp))
 240                 return;
 241
 242         rte_free(bp->leds);
 243         bp->leds = NULL;
 244 }
 245
 246 static void bnxt_free_flow_stats_info(struct bnxt *bp)
 247 {
 248         rte_free(bp->flow_stat);
 249         bp->flow_stat = NULL;
 250 }
 251
 252 static void bnxt_free_cos_queues(struct bnxt *bp)
 253 {
 254         rte_free(bp->rx_cos_queue);
 255         rte_free(bp->tx_cos_queue);
 256 }
 257
 258 static void bnxt_free_mem(struct bnxt *bp, bool reconfig)
 259 {
 260         bnxt_free_filter_mem(bp);
 261         bnxt_free_vnic_attributes(bp);
 262         bnxt_free_vnic_mem(bp);
 263
 264         /* tx/rx rings are configured as part of *_queue_setup callbacks.
 265          * If the number of rings change across fw update,
 266          * we don't have much choice except to warn the user.
 267          */
 268         if (!reconfig) {
 269                 bnxt_free_stats(bp);
 270                 bnxt_free_tx_rings(bp);
 271                 bnxt_free_rx_rings(bp);
 272         }
 273         bnxt_free_async_cp_ring(bp);
 274         bnxt_free_rxtx_nq_ring(bp);
 275
 276         rte_free(bp->grp_info);
 277         bp->grp_info = NULL;
 278 }
 279
 280 static int bnxt_alloc_parent_info(struct bnxt *bp)
 281 {
 282         bp->parent = rte_zmalloc("bnxt_parent_info",
 283                                  sizeof(struct bnxt_parent_info), 0);
 284         if (bp->parent == NULL)
 285                 return -ENOMEM;
 286
 287         return 0;
 288 }
 289
 290 static int bnxt_alloc_pf_info(struct bnxt *bp)
 291 {
 292         bp->pf = rte_zmalloc("bnxt_pf_info", sizeof(struct bnxt_pf_info), 0);
 293         if (bp->pf == NULL)
 294                 return -ENOMEM;
 295
 296         return 0;
 297 }
 298
 299 static int bnxt_alloc_link_info(struct bnxt *bp)
 300 {
 301         bp->link_info =
 302                 rte_zmalloc("bnxt_link_info", sizeof(struct bnxt_link_info), 0);
 303         if (bp->link_info == NULL)
 304                 return -ENOMEM;
 305
 306         return 0;
 307 }
 308
 309 static int bnxt_alloc_leds_info(struct bnxt *bp)
 310 {
 311         if (BNXT_VF(bp))
 312                 return 0;
 313
 314         bp->leds = rte_zmalloc("bnxt_leds",
 315                                BNXT_MAX_LED * sizeof(struct bnxt_led_info),
 316                                0);
 317         if (bp->leds == NULL)
 318                 return -ENOMEM;
 319
 320         return 0;
 321 }
 322
 323 static int bnxt_alloc_cos_queues(struct bnxt *bp)
 324 {
 325         bp->rx_cos_queue =
 326                 rte_zmalloc("bnxt_rx_cosq",
 327                             BNXT_COS_QUEUE_COUNT *
 328                             sizeof(struct bnxt_cos_queue_info),
 329                             0);
 330         if (bp->rx_cos_queue == NULL)
 331                 return -ENOMEM;
 332
 333         bp->tx_cos_queue =
 334                 rte_zmalloc("bnxt_tx_cosq",
 335                             BNXT_COS_QUEUE_COUNT *
 336                             sizeof(struct bnxt_cos_queue_info),
 337                             0);
 338         if (bp->tx_cos_queue == NULL)
 339                 return -ENOMEM;
 340
 341         return 0;
 342 }
 343
 344 static int bnxt_alloc_flow_stats_info(struct bnxt *bp)
 345 {
 346         bp->flow_stat = rte_zmalloc("bnxt_flow_xstat",
 347                                     sizeof(struct bnxt_flow_stat_info), 0);
 348         if (bp->flow_stat == NULL)
 349                 return -ENOMEM;
 350
 351         return 0;
 352 }
 353
 354 static int bnxt_alloc_mem(struct bnxt *bp, bool reconfig)
 355 {
 356         int rc;
 357
 358         rc = bnxt_alloc_ring_grps(bp);
 359         if (rc)
 360                 goto alloc_mem_err;
 361
 362         rc = bnxt_alloc_async_ring_struct(bp);
 363         if (rc)
 364                 goto alloc_mem_err;
 365
 366         rc = bnxt_alloc_vnic_mem(bp);
 367         if (rc)
 368                 goto alloc_mem_err;
 369
 370         rc = bnxt_alloc_vnic_attributes(bp);
 371         if (rc)
 372                 goto alloc_mem_err;
 373
 374         rc = bnxt_alloc_filter_mem(bp);
 375         if (rc)
 376                 goto alloc_mem_err;
 377
 378         rc = bnxt_alloc_async_cp_ring(bp);
 379         if (rc)
 380                 goto alloc_mem_err;
 381
 382         rc = bnxt_alloc_rxtx_nq_ring(bp);
 383         if (rc)
 384                 goto alloc_mem_err;
 385
 386         if (BNXT_FLOW_XSTATS_EN(bp)) {
 387                 rc = bnxt_alloc_flow_stats_info(bp);
 388                 if (rc)
 389                         goto alloc_mem_err;
 390         }
 391
 392         return 0;
 393
 394 alloc_mem_err:
 395         bnxt_free_mem(bp, reconfig);
 396         return rc;
 397 }
 398
 399 static int bnxt_setup_one_vnic(struct bnxt *bp, uint16_t vnic_id)
 400 {
 401         struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
 402         struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id];
 403         uint64_t rx_offloads = dev_conf->rxmode.offloads;
 404         struct bnxt_rx_queue *rxq;
 405         unsigned int j;
 406         int rc;
 407
 408         rc = bnxt_vnic_grp_alloc(bp, vnic);
 409         if (rc)
 410                 goto err_out;
 411
 412         PMD_DRV_LOG(DEBUG, "vnic[%d] = %p vnic->fw_grp_ids = %p\n",
 413                     vnic_id, vnic, vnic->fw_grp_ids);
 414
 415         rc = bnxt_hwrm_vnic_alloc(bp, vnic);
 416         if (rc)
 417                 goto err_out;
 418
 419         /* Alloc RSS context only if RSS mode is enabled */
 420         if (dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS) {
 421                 int j, nr_ctxs = bnxt_rss_ctxts(bp);
 422
 423                 rc = 0;
 424                 for (j = 0; j < nr_ctxs; j++) {
 425                         rc = bnxt_hwrm_vnic_ctx_alloc(bp, vnic, j);
 426                         if (rc)
 427                                 break;
 428                 }
 429                 if (rc) {
 430                         PMD_DRV_LOG(ERR,
 431                                     "HWRM vnic %d ctx %d alloc failure rc: %x\n",
 432                                     vnic_id, j, rc);
 433                         goto err_out;
 434                 }
 435                 vnic->num_lb_ctxts = nr_ctxs;
 436         }
 437
 438         /*
 439          * Firmware sets pf pair in default vnic cfg. If the VLAN strip
 440          * setting is not available at this time, it will not be
 441          * configured correctly in the CFA.
 442          */
 443         if (rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
 444                 vnic->vlan_strip = true;
 445         else
 446                 vnic->vlan_strip = false;
 447
 448         rc = bnxt_hwrm_vnic_cfg(bp, vnic);
 449         if (rc)
 450                 goto err_out;
 451
 452         rc = bnxt_set_hwrm_vnic_filters(bp, vnic);
 453         if (rc)
 454                 goto err_out;
 455
 456         for (j = 0; j < bp->rx_num_qs_per_vnic; j++) {
 457                 rxq = bp->eth_dev->data->rx_queues[j];
 458
 459                 PMD_DRV_LOG(DEBUG,
 460                             "rxq[%d]->vnic=%p vnic->fw_grp_ids=%p\n",
 461                             j, rxq->vnic, rxq->vnic->fw_grp_ids);
 462
 463                 if (BNXT_HAS_RING_GRPS(bp) && rxq->rx_deferred_start)
 464                         rxq->vnic->fw_grp_ids[j] = INVALID_HW_RING_ID;
 465                 else
 466                         vnic->rx_queue_cnt++;
 467         }
 468
 469         PMD_DRV_LOG(DEBUG, "vnic->rx_queue_cnt = %d\n", vnic->rx_queue_cnt);
 470
 471         rc = bnxt_vnic_rss_configure(bp, vnic);
 472         if (rc)
 473                 goto err_out;
 474
 475         bnxt_hwrm_vnic_plcmode_cfg(bp, vnic);
 476
 477         if (rx_offloads & DEV_RX_OFFLOAD_TCP_LRO)
 478                 bnxt_hwrm_vnic_tpa_cfg(bp, vnic, 1);
 479         else
 480                 bnxt_hwrm_vnic_tpa_cfg(bp, vnic, 0);
 481
 482         return 0;
 483 err_out:
 484         PMD_DRV_LOG(ERR, "HWRM vnic %d cfg failure rc: %x\n",
 485                     vnic_id, rc);
 486         return rc;
 487 }
 488
 489 static int bnxt_register_fc_ctx_mem(struct bnxt *bp)
 490 {
 491         int rc = 0;
 492
 493         rc = bnxt_hwrm_ctx_rgtr(bp, bp->flow_stat->rx_fc_in_tbl.dma,
 494                                 &bp->flow_stat->rx_fc_in_tbl.ctx_id);
 495         if (rc)
 496                 return rc;
 497
 498         PMD_DRV_LOG(DEBUG,
 499                     "rx_fc_in_tbl.va = %p rx_fc_in_tbl.dma = %p"
 500                     " rx_fc_in_tbl.ctx_id = %d\n",
 501                     bp->flow_stat->rx_fc_in_tbl.va,
 502                     (void *)((uintptr_t)bp->flow_stat->rx_fc_in_tbl.dma),
 503                     bp->flow_stat->rx_fc_in_tbl.ctx_id);
 504
 505         rc = bnxt_hwrm_ctx_rgtr(bp, bp->flow_stat->rx_fc_out_tbl.dma,
 506                                 &bp->flow_stat->rx_fc_out_tbl.ctx_id);
 507         if (rc)
 508                 return rc;
 509
 510         PMD_DRV_LOG(DEBUG,
 511                     "rx_fc_out_tbl.va = %p rx_fc_out_tbl.dma = %p"
 512                     " rx_fc_out_tbl.ctx_id = %d\n",
 513                     bp->flow_stat->rx_fc_out_tbl.va,
 514                     (void *)((uintptr_t)bp->flow_stat->rx_fc_out_tbl.dma),
 515                     bp->flow_stat->rx_fc_out_tbl.ctx_id);
 516
 517         rc = bnxt_hwrm_ctx_rgtr(bp, bp->flow_stat->tx_fc_in_tbl.dma,
 518                                 &bp->flow_stat->tx_fc_in_tbl.ctx_id);
 519         if (rc)
 520                 return rc;
 521
 522         PMD_DRV_LOG(DEBUG,
 523                     "tx_fc_in_tbl.va = %p tx_fc_in_tbl.dma = %p"
 524                     " tx_fc_in_tbl.ctx_id = %d\n",
 525                     bp->flow_stat->tx_fc_in_tbl.va,
 526                     (void *)((uintptr_t)bp->flow_stat->tx_fc_in_tbl.dma),
 527                     bp->flow_stat->tx_fc_in_tbl.ctx_id);
 528
 529         rc = bnxt_hwrm_ctx_rgtr(bp, bp->flow_stat->tx_fc_out_tbl.dma,
 530                                 &bp->flow_stat->tx_fc_out_tbl.ctx_id);
 531         if (rc)
 532                 return rc;
 533
 534         PMD_DRV_LOG(DEBUG,
 535                     "tx_fc_out_tbl.va = %p tx_fc_out_tbl.dma = %p"
 536                     " tx_fc_out_tbl.ctx_id = %d\n",
 537                     bp->flow_stat->tx_fc_out_tbl.va,
 538                     (void *)((uintptr_t)bp->flow_stat->tx_fc_out_tbl.dma),
 539                     bp->flow_stat->tx_fc_out_tbl.ctx_id);
 540
 541         memset(bp->flow_stat->rx_fc_out_tbl.va,
 542                0,
 543                bp->flow_stat->rx_fc_out_tbl.size);
 544         rc = bnxt_hwrm_cfa_counter_cfg(bp, BNXT_DIR_RX,
 545                                        CFA_COUNTER_CFG_IN_COUNTER_TYPE_FC,
 546                                        bp->flow_stat->rx_fc_out_tbl.ctx_id,
 547                                        bp->flow_stat->max_fc,
 548                                        true);
 549         if (rc)
 550                 return rc;
 551
 552         memset(bp->flow_stat->tx_fc_out_tbl.va,
 553                0,
 554                bp->flow_stat->tx_fc_out_tbl.size);
 555         rc = bnxt_hwrm_cfa_counter_cfg(bp, BNXT_DIR_TX,
 556                                        CFA_COUNTER_CFG_IN_COUNTER_TYPE_FC,
 557                                        bp->flow_stat->tx_fc_out_tbl.ctx_id,
 558                                        bp->flow_stat->max_fc,
 559                                        true);
 560
 561         return rc;
 562 }
 563
 564 static int bnxt_alloc_ctx_mem_buf(char *type, size_t size,
 565                                   struct bnxt_ctx_mem_buf_info *ctx)
 566 {
 567         if (!ctx)
 568                 return -EINVAL;
 569
 570         ctx->va = rte_zmalloc(type, size, 0);
 571         if (ctx->va == NULL)
 572                 return -ENOMEM;
 573         rte_mem_lock_page(ctx->va);
 574         ctx->size = size;
 575         ctx->dma = rte_mem_virt2iova(ctx->va);
 576         if (ctx->dma == RTE_BAD_IOVA)
 577                 return -ENOMEM;
 578
 579         return 0;
 580 }
 581
 582 static int bnxt_init_fc_ctx_mem(struct bnxt *bp)
 583 {
 584         struct rte_pci_device *pdev = bp->pdev;
 585         char type[RTE_MEMZONE_NAMESIZE];
 586         uint16_t max_fc;
 587         int rc = 0;
 588
 589         max_fc = bp->flow_stat->max_fc;
 590
 591         sprintf(type, "bnxt_rx_fc_in_" PCI_PRI_FMT, pdev->addr.domain,
 592                 pdev->addr.bus, pdev->addr.devid, pdev->addr.function);
 593         /* 4 bytes for each counter-id */
 594         rc = bnxt_alloc_ctx_mem_buf(type,
 595                                     max_fc * 4,
 596                                     &bp->flow_stat->rx_fc_in_tbl);
 597         if (rc)
 598                 return rc;
 599
 600         sprintf(type, "bnxt_rx_fc_out_" PCI_PRI_FMT, pdev->addr.domain,
 601                 pdev->addr.bus, pdev->addr.devid, pdev->addr.function);
 602         /* 16 bytes for each counter - 8 bytes pkt_count, 8 bytes byte_count */
 603         rc = bnxt_alloc_ctx_mem_buf(type,
 604                                     max_fc * 16,
 605                                     &bp->flow_stat->rx_fc_out_tbl);
 606         if (rc)
 607                 return rc;
 608
 609         sprintf(type, "bnxt_tx_fc_in_" PCI_PRI_FMT, pdev->addr.domain,
 610                 pdev->addr.bus, pdev->addr.devid, pdev->addr.function);
 611         /* 4 bytes for each counter-id */
 612         rc = bnxt_alloc_ctx_mem_buf(type,
 613                                     max_fc * 4,
 614                                     &bp->flow_stat->tx_fc_in_tbl);
 615         if (rc)
 616                 return rc;
 617
 618         sprintf(type, "bnxt_tx_fc_out_" PCI_PRI_FMT, pdev->addr.domain,
 619                 pdev->addr.bus, pdev->addr.devid, pdev->addr.function);
 620         /* 16 bytes for each counter - 8 bytes pkt_count, 8 bytes byte_count */
 621         rc = bnxt_alloc_ctx_mem_buf(type,
 622                                     max_fc * 16,
 623                                     &bp->flow_stat->tx_fc_out_tbl);
 624         if (rc)
 625                 return rc;
 626
 627         rc = bnxt_register_fc_ctx_mem(bp);
 628
 629         return rc;
 630 }
 631
 632 static int bnxt_init_ctx_mem(struct bnxt *bp)
 633 {
 634         int rc = 0;
 635
 636         if (!(bp->fw_cap & BNXT_FW_CAP_ADV_FLOW_COUNTERS) ||
 637             !(BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp)) ||
 638             !BNXT_FLOW_XSTATS_EN(bp))
 639                 return 0;
 640
 641         rc = bnxt_hwrm_cfa_counter_qcaps(bp, &bp->flow_stat->max_fc);
 642         if (rc)
 643                 return rc;
 644
 645         rc = bnxt_init_fc_ctx_mem(bp);
 646
 647         return rc;
 648 }
 649
 650 static int bnxt_update_phy_setting(struct bnxt *bp)
 651 {
 652         struct rte_eth_link new;
 653         int rc;
 654
 655         rc = bnxt_get_hwrm_link_config(bp, &new);
 656         if (rc) {
 657                 PMD_DRV_LOG(ERR, "Failed to get link settings\n");
 658                 return rc;
 659         }
 660
 661         /*
 662          * On BCM957508-N2100 adapters, FW will not allow any user other
 663          * than BMC to shutdown the port. bnxt_get_hwrm_link_config() call
 664          * always returns link up. Force phy update always in that case.
 665          */
 666         if (!new.link_status || IS_BNXT_DEV_957508_N2100(bp)) {
 667                 rc = bnxt_set_hwrm_link_config(bp, true);
 668                 if (rc) {
 669                         PMD_DRV_LOG(ERR, "Failed to update PHY settings\n");
 670                         return rc;
 671                 }
 672         }
 673
 674         return rc;
 675 }
 676
 677 static int bnxt_init_chip(struct bnxt *bp)
 678 {
 679         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(bp->eth_dev);
 680         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
 681         uint32_t intr_vector = 0;
 682         uint32_t queue_id, base = BNXT_MISC_VEC_ID;
 683         uint32_t vec = BNXT_MISC_VEC_ID;
 684         unsigned int i, j;
 685         int rc;
 686
 687         if (bp->eth_dev->data->mtu > RTE_ETHER_MTU) {
 688                 bp->eth_dev->data->dev_conf.rxmode.offloads |=
 689                         DEV_RX_OFFLOAD_JUMBO_FRAME;
 690                 bp->flags |= BNXT_FLAG_JUMBO;
 691         } else {
 692                 bp->eth_dev->data->dev_conf.rxmode.offloads &=
 693                         ~DEV_RX_OFFLOAD_JUMBO_FRAME;
 694                 bp->flags &= ~BNXT_FLAG_JUMBO;
 695         }
 696
 697         /* THOR does not support ring groups.
 698          * But we will use the array to save RSS context IDs.
 699          */
 700         if (BNXT_CHIP_THOR(bp))
 701                 bp->max_ring_grps = BNXT_MAX_RSS_CTXTS_THOR;
 702
 703         rc = bnxt_alloc_all_hwrm_stat_ctxs(bp);
 704         if (rc) {
 705                 PMD_DRV_LOG(ERR, "HWRM stat ctx alloc failure rc: %x\n", rc);
 706                 goto err_out;
 707         }
 708
 709         rc = bnxt_alloc_hwrm_rings(bp);
 710         if (rc) {
 711                 PMD_DRV_LOG(ERR, "HWRM ring alloc failure rc: %x\n", rc);
 712                 goto err_out;
 713         }
 714
 715         rc = bnxt_alloc_all_hwrm_ring_grps(bp);
 716         if (rc) {
 717                 PMD_DRV_LOG(ERR, "HWRM ring grp alloc failure: %x\n", rc);
 718                 goto err_out;
 719         }
 720
 721         if (!(bp->vnic_cap_flags & BNXT_VNIC_CAP_COS_CLASSIFY))
 722                 goto skip_cosq_cfg;
 723
 724         for (j = 0, i = 0; i < BNXT_COS_QUEUE_COUNT; i++) {
 725                 if (bp->rx_cos_queue[i].id != 0xff) {
 726                         struct bnxt_vnic_info *vnic = &bp->vnic_info[j++];
 727
 728                         if (!vnic) {
 729                                 PMD_DRV_LOG(ERR,
 730                                             "Num pools more than FW profile\n");
 731                                 rc = -EINVAL;
 732                                 goto err_out;
 733                         }
 734                         vnic->cos_queue_id = bp->rx_cos_queue[i].id;
 735                         bp->rx_cosq_cnt++;
 736                 }
 737         }
 738
 739 skip_cosq_cfg:
 740         rc = bnxt_mq_rx_configure(bp);
 741         if (rc) {
 742                 PMD_DRV_LOG(ERR, "MQ mode configure failure rc: %x\n", rc);
 743                 goto err_out;
 744         }
 745
 746         /* VNIC configuration */
 747         for (i = 0; i < bp->nr_vnics; i++) {
 748                 rc = bnxt_setup_one_vnic(bp, i);
 749                 if (rc)
 750                         goto err_out;
 751         }
 752
 753         rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, &bp->vnic_info[0], 0, NULL);
 754         if (rc) {
 755                 PMD_DRV_LOG(ERR,
 756                         "HWRM cfa l2 rx mask failure rc: %x\n", rc);
 757                 goto err_out;
 758         }
 759
 760         /* check and configure queue intr-vector mapping */
 761         if ((rte_intr_cap_multiple(intr_handle) ||
 762              !RTE_ETH_DEV_SRIOV(bp->eth_dev).active) &&
 763             bp->eth_dev->data->dev_conf.intr_conf.rxq != 0) {
 764                 intr_vector = bp->eth_dev->data->nb_rx_queues;
 765                 PMD_DRV_LOG(DEBUG, "intr_vector = %d\n", intr_vector);
 766                 if (intr_vector > bp->rx_cp_nr_rings) {
 767                         PMD_DRV_LOG(ERR, "At most %d intr queues supported",
 768                                         bp->rx_cp_nr_rings);
 769                         return -ENOTSUP;
 770                 }
 771                 rc = rte_intr_efd_enable(intr_handle, intr_vector);
 772                 if (rc)
 773                         return rc;
 774         }
 775
 776         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
 777                 intr_handle->intr_vec =
 778                         rte_zmalloc("intr_vec",
 779                                     bp->eth_dev->data->nb_rx_queues *
 780                                     sizeof(int), 0);
 781                 if (intr_handle->intr_vec == NULL) {
 782                         PMD_DRV_LOG(ERR, "Failed to allocate %d rx_queues"
 783                                 " intr_vec", bp->eth_dev->data->nb_rx_queues);
 784                         rc = -ENOMEM;
 785                         goto err_disable;
 786                 }
 787                 PMD_DRV_LOG(DEBUG, "intr_handle->intr_vec = %p "
 788                         "intr_handle->nb_efd = %d intr_handle->max_intr = %d\n",
 789                          intr_handle->intr_vec, intr_handle->nb_efd,
 790                         intr_handle->max_intr);
 791                 for (queue_id = 0; queue_id < bp->eth_dev->data->nb_rx_queues;
 792                      queue_id++) {
 793                         intr_handle->intr_vec[queue_id] =
 794                                                         vec + BNXT_RX_VEC_START;
 795                         if (vec < base + intr_handle->nb_efd - 1)
 796                                 vec++;
 797                 }
 798         }
 799
 800         /* enable uio/vfio intr/eventfd mapping */
 801         rc = rte_intr_enable(intr_handle);
 802 #ifndef RTE_EXEC_ENV_FREEBSD
 803         /* In FreeBSD OS, nic_uio driver does not support interrupts */
 804         if (rc)
 805                 goto err_free;
 806 #endif
 807
 808         rc = bnxt_update_phy_setting(bp);
 809         if (rc)
 810                 goto err_free;
 811
 812         bp->mark_table = rte_zmalloc("bnxt_mark_table", BNXT_MARK_TABLE_SZ, 0);
 813         if (!bp->mark_table)
 814                 PMD_DRV_LOG(ERR, "Allocation of mark table failed\n");
 815
 816         return 0;
 817
 818 err_free:
 819         rte_free(intr_handle->intr_vec);
 820 err_disable:
 821         rte_intr_efd_disable(intr_handle);
 822 err_out:
 823         /* Some of the error status returned by FW may not be from errno.h */
 824         if (rc > 0)
 825                 rc = -EIO;
 826
 827         return rc;
 828 }
 829
 830 static int bnxt_shutdown_nic(struct bnxt *bp)
 831 {
 832         bnxt_free_all_hwrm_resources(bp);
 833         bnxt_free_all_filters(bp);
 834         bnxt_free_all_vnics(bp);
 835         return 0;
 836 }
 837
 838 /*
 839  * Device configuration and status function
 840  */
 841
 842 uint32_t bnxt_get_speed_capabilities(struct bnxt *bp)
 843 {
 844         uint32_t link_speed = bp->link_info->support_speeds;
 845         uint32_t speed_capa = 0;
 846
 847         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_100MB)
 848                 speed_capa |= ETH_LINK_SPEED_100M;
 849         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_100MBHD)
 850                 speed_capa |= ETH_LINK_SPEED_100M_HD;
 851         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_1GB)
 852                 speed_capa |= ETH_LINK_SPEED_1G;
 853         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_2_5GB)
 854                 speed_capa |= ETH_LINK_SPEED_2_5G;
 855         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_10GB)
 856                 speed_capa |= ETH_LINK_SPEED_10G;
 857         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_20GB)
 858                 speed_capa |= ETH_LINK_SPEED_20G;
 859         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_25GB)
 860                 speed_capa |= ETH_LINK_SPEED_25G;
 861         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_40GB)
 862                 speed_capa |= ETH_LINK_SPEED_40G;
 863         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_50GB)
 864                 speed_capa |= ETH_LINK_SPEED_50G;
 865         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_100GB)
 866                 speed_capa |= ETH_LINK_SPEED_100G;
 867         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_200GB)
 868                 speed_capa |= ETH_LINK_SPEED_200G;
 869
 870         if (bp->link_info->auto_mode ==
 871             HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_MODE_NONE)
 872                 speed_capa |= ETH_LINK_SPEED_FIXED;
 873         else
 874                 speed_capa |= ETH_LINK_SPEED_AUTONEG;
 875
 876         return speed_capa;
 877 }
 878
 879 static int bnxt_dev_info_get_op(struct rte_eth_dev *eth_dev,
 880                                 struct rte_eth_dev_info *dev_info)
 881 {
 882         struct rte_pci_device *pdev = RTE_DEV_TO_PCI(eth_dev->device);
 883         struct bnxt *bp = eth_dev->data->dev_private;
 884         uint16_t max_vnics, i, j, vpool, vrxq;
 885         unsigned int max_rx_rings;
 886         int rc;
 887
 888         rc = is_bnxt_in_error(bp);
 889         if (rc)
 890                 return rc;
 891
 892         /* MAC Specifics */
 893         dev_info->max_mac_addrs = bp->max_l2_ctx;
 894         dev_info->max_hash_mac_addrs = 0;
 895
 896         /* PF/VF specifics */
 897         if (BNXT_PF(bp))
 898                 dev_info->max_vfs = pdev->max_vfs;
 899
 900         max_rx_rings = BNXT_MAX_RINGS(bp);
 901         /* For the sake of symmetry, max_rx_queues = max_tx_queues */
 902         dev_info->max_rx_queues = max_rx_rings;
 903         dev_info->max_tx_queues = max_rx_rings;
 904         dev_info->reta_size = bnxt_rss_hash_tbl_size(bp);
 905         dev_info->hash_key_size = 40;
 906         max_vnics = bp->max_vnics;
 907
 908         /* MTU specifics */
 909         dev_info->min_mtu = RTE_ETHER_MIN_MTU;
 910         dev_info->max_mtu = BNXT_MAX_MTU;
 911
 912         /* Fast path specifics */
 913         dev_info->min_rx_bufsize = 1;
 914         dev_info->max_rx_pktlen = BNXT_MAX_PKT_LEN;
 915
 916         dev_info->rx_offload_capa = BNXT_DEV_RX_OFFLOAD_SUPPORT;
 917         if (bp->flags & BNXT_FLAG_PTP_SUPPORTED)
 918                 dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_TIMESTAMP;
 919         dev_info->tx_offload_capa = BNXT_DEV_TX_OFFLOAD_SUPPORT;
 920         dev_info->flow_type_rss_offloads = BNXT_ETH_RSS_SUPPORT;
 921
 922         dev_info->speed_capa = bnxt_get_speed_capabilities(bp);
 923
 924         /* *INDENT-OFF* */
 925         dev_info->default_rxconf = (struct rte_eth_rxconf) {
 926                 .rx_thresh = {
 927                         .pthresh = 8,
 928                         .hthresh = 8,
 929                         .wthresh = 0,
 930                 },
 931                 .rx_free_thresh = 32,
 932                 /* If no descriptors available, pkts are dropped by default */
 933                 .rx_drop_en = 1,
 934         };
 935
 936         dev_info->default_txconf = (struct rte_eth_txconf) {
 937                 .tx_thresh = {
 938                         .pthresh = 32,
 939                         .hthresh = 0,
 940                         .wthresh = 0,
 941                 },
 942                 .tx_free_thresh = 32,
 943                 .tx_rs_thresh = 32,
 944         };
 945         eth_dev->data->dev_conf.intr_conf.lsc = 1;
 946
 947         eth_dev->data->dev_conf.intr_conf.rxq = 1;
 948         dev_info->rx_desc_lim.nb_min = BNXT_MIN_RING_DESC;
 949         dev_info->rx_desc_lim.nb_max = BNXT_MAX_RX_RING_DESC;
 950         dev_info->tx_desc_lim.nb_min = BNXT_MIN_RING_DESC;
 951         dev_info->tx_desc_lim.nb_max = BNXT_MAX_TX_RING_DESC;
 952
 953         if (BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp)) {
 954                 dev_info->switch_info.name = eth_dev->device->name;
 955                 dev_info->switch_info.domain_id = bp->switch_domain_id;
 956                 dev_info->switch_info.port_id =
 957                                 BNXT_PF(bp) ? BNXT_SWITCH_PORT_ID_PF :
 958                                     BNXT_SWITCH_PORT_ID_TRUSTED_VF;
 959         }
 960
 961         /* *INDENT-ON* */
 962
 963         /*
 964          * TODO: default_rxconf, default_txconf, rx_desc_lim, and tx_desc_lim
 965          *       need further investigation.
 966          */
 967
 968         /* VMDq resources */
 969         vpool = 64; /* ETH_64_POOLS */
 970         vrxq = 128; /* ETH_VMDQ_DCB_NUM_QUEUES */
 971         for (i = 0; i < 4; vpool >>= 1, i++) {
 972                 if (max_vnics > vpool) {
 973                         for (j = 0; j < 5; vrxq >>= 1, j++) {
 974                                 if (dev_info->max_rx_queues > vrxq) {
 975                                         if (vpool > vrxq)
 976                                                 vpool = vrxq;
 977                                         goto found;
 978                                 }
 979                         }
 980                         /* Not enough resources to support VMDq */
 981                         break;
 982                 }
 983         }
 984         /* Not enough resources to support VMDq */
 985         vpool = 0;
 986         vrxq = 0;
 987 found:
 988         dev_info->max_vmdq_pools = vpool;
 989         dev_info->vmdq_queue_num = vrxq;
 990
 991         dev_info->vmdq_pool_base = 0;
 992         dev_info->vmdq_queue_base = 0;
 993
 994         return 0;
 995 }
 996
 997 /* Configure the device based on the configuration provided */
 998 static int bnxt_dev_configure_op(struct rte_eth_dev *eth_dev)
 999 {
1000         struct bnxt *bp = eth_dev->data->dev_private;
1001         uint64_t rx_offloads = eth_dev->data->dev_conf.rxmode.offloads;
1002         int rc;
1003
1004         bp->rx_queues = (void *)eth_dev->data->rx_queues;
1005         bp->tx_queues = (void *)eth_dev->data->tx_queues;
1006         bp->tx_nr_rings = eth_dev->data->nb_tx_queues;
1007         bp->rx_nr_rings = eth_dev->data->nb_rx_queues;
1008
1009         rc = is_bnxt_in_error(bp);
1010         if (rc)
1011                 return rc;
1012
1013         if (BNXT_VF(bp) && (bp->flags & BNXT_FLAG_NEW_RM)) {
1014                 rc = bnxt_hwrm_check_vf_rings(bp);
1015                 if (rc) {
1016                         PMD_DRV_LOG(ERR, "HWRM insufficient resources\n");
1017                         return -ENOSPC;
1018                 }
1019
1020                 /* If a resource has already been allocated - in this case
1021                  * it is the async completion ring, free it. Reallocate it after
1022                  * resource reservation. This will ensure the resource counts
1023                  * are calculated correctly.
1024                  */
1025
1026                 pthread_mutex_lock(&bp->def_cp_lock);
1027
1028                 if (!BNXT_HAS_NQ(bp) && bp->async_cp_ring) {
1029                         bnxt_disable_int(bp);
1030                         bnxt_free_cp_ring(bp, bp->async_cp_ring);
1031                 }
1032
1033                 rc = bnxt_hwrm_func_reserve_vf_resc(bp, false);
1034                 if (rc) {
1035                         PMD_DRV_LOG(ERR, "HWRM resource alloc fail:%x\n", rc);
1036                         pthread_mutex_unlock(&bp->def_cp_lock);
1037                         return -ENOSPC;
1038                 }
1039
1040                 if (!BNXT_HAS_NQ(bp) && bp->async_cp_ring) {
1041                         rc = bnxt_alloc_async_cp_ring(bp);
1042                         if (rc) {
1043                                 pthread_mutex_unlock(&bp->def_cp_lock);
1044                                 return rc;
1045                         }
1046                         bnxt_enable_int(bp);
1047                 }
1048
1049                 pthread_mutex_unlock(&bp->def_cp_lock);
1050         } else {
1051                 /* legacy driver needs to get updated values */
1052                 rc = bnxt_hwrm_func_qcaps(bp);
1053                 if (rc) {
1054                         PMD_DRV_LOG(ERR, "hwrm func qcaps fail:%d\n", rc);
1055                         return rc;
1056                 }
1057         }
1058
1059         /* Inherit new configurations */
1060         if (eth_dev->data->nb_rx_queues > bp->max_rx_rings ||
1061             eth_dev->data->nb_tx_queues > bp->max_tx_rings ||
1062             eth_dev->data->nb_rx_queues + eth_dev->data->nb_tx_queues
1063                 + BNXT_NUM_ASYNC_CPR(bp) > bp->max_cp_rings ||
1064             eth_dev->data->nb_rx_queues + eth_dev->data->nb_tx_queues >
1065             bp->max_stat_ctx)
1066                 goto resource_error;
1067
1068         if (BNXT_HAS_RING_GRPS(bp) &&
1069             (uint32_t)(eth_dev->data->nb_rx_queues) > bp->max_ring_grps)
1070                 goto resource_error;
1071
1072         if (!(eth_dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_RSS) &&
1073             bp->max_vnics < eth_dev->data->nb_rx_queues)
1074                 goto resource_error;
1075
1076         bp->rx_cp_nr_rings = bp->rx_nr_rings;
1077         bp->tx_cp_nr_rings = bp->tx_nr_rings;
1078
1079         if (eth_dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG)
1080                 rx_offloads |= DEV_RX_OFFLOAD_RSS_HASH;
1081         eth_dev->data->dev_conf.rxmode.offloads = rx_offloads;
1082
1083         if (rx_offloads & DEV_RX_OFFLOAD_JUMBO_FRAME) {
1084                 eth_dev->data->mtu =
1085                         eth_dev->data->dev_conf.rxmode.max_rx_pkt_len -
1086                         RTE_ETHER_HDR_LEN - RTE_ETHER_CRC_LEN - VLAN_TAG_SIZE *
1087                         BNXT_NUM_VLANS;
1088                 bnxt_mtu_set_op(eth_dev, eth_dev->data->mtu);
1089         }
1090         return 0;
1091
1092 resource_error:
1093         PMD_DRV_LOG(ERR,
1094                     "Insufficient resources to support requested config\n");
1095         PMD_DRV_LOG(ERR,
1096                     "Num Queues Requested: Tx %d, Rx %d\n",
1097                     eth_dev->data->nb_tx_queues,
1098                     eth_dev->data->nb_rx_queues);
1099         PMD_DRV_LOG(ERR,
1100                     "MAX: TxQ %d, RxQ %d, CQ %d Stat %d, Grp %d, Vnic %d\n",
1101                     bp->max_tx_rings, bp->max_rx_rings, bp->max_cp_rings,
1102                     bp->max_stat_ctx, bp->max_ring_grps, bp->max_vnics);
1103         return -ENOSPC;
1104 }
1105
1106 void bnxt_print_link_info(struct rte_eth_dev *eth_dev)
1107 {
1108         struct rte_eth_link *link = &eth_dev->data->dev_link;
1109
1110         if (link->link_status)
1111                 PMD_DRV_LOG(INFO, "Port %d Link Up - speed %u Mbps - %s\n",
1112                         eth_dev->data->port_id,
1113                         (uint32_t)link->link_speed,
1114                         (link->link_duplex == ETH_LINK_FULL_DUPLEX) ?
1115                         ("full-duplex") : ("half-duplex\n"));
1116         else
1117                 PMD_DRV_LOG(INFO, "Port %d Link Down\n",
1118                         eth_dev->data->port_id);
1119 }
1120
1121 /*
1122  * Determine whether the current configuration requires support for scattered
1123  * receive; return 1 if scattered receive is required and 0 if not.
1124  */
1125 static int bnxt_scattered_rx(struct rte_eth_dev *eth_dev)
1126 {
1127         uint16_t buf_size;
1128         int i;
1129
1130         if (eth_dev->data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_SCATTER)
1131                 return 1;
1132
1133         for (i = 0; i < eth_dev->data->nb_rx_queues; i++) {
1134                 struct bnxt_rx_queue *rxq = eth_dev->data->rx_queues[i];
1135
1136                 buf_size = (uint16_t)(rte_pktmbuf_data_room_size(rxq->mb_pool) -
1137                                       RTE_PKTMBUF_HEADROOM);
1138                 if (eth_dev->data->dev_conf.rxmode.max_rx_pkt_len > buf_size)
1139                         return 1;
1140         }
1141         return 0;
1142 }
1143
1144 static eth_rx_burst_t
1145 bnxt_receive_function(struct rte_eth_dev *eth_dev)
1146 {
1147         struct bnxt *bp = eth_dev->data->dev_private;
1148
1149 #if defined(RTE_ARCH_X86) || defined(RTE_ARCH_ARM64)
1150 #ifndef RTE_LIBRTE_IEEE1588
1151         /*
1152          * Vector mode receive can be enabled only if scatter rx is not
1153          * in use and rx offloads are limited to VLAN stripping and
1154          * CRC stripping.
1155          */
1156         if (!eth_dev->data->scattered_rx &&
1157             !(eth_dev->data->dev_conf.rxmode.offloads &
1158               ~(DEV_RX_OFFLOAD_VLAN_STRIP |
1159                 DEV_RX_OFFLOAD_KEEP_CRC |
1160                 DEV_RX_OFFLOAD_JUMBO_FRAME |
1161                 DEV_RX_OFFLOAD_IPV4_CKSUM |
1162                 DEV_RX_OFFLOAD_UDP_CKSUM |
1163                 DEV_RX_OFFLOAD_TCP_CKSUM |
1164                 DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM |
1165                 DEV_RX_OFFLOAD_RSS_HASH |
1166                 DEV_RX_OFFLOAD_VLAN_FILTER)) &&
1167             !BNXT_TRUFLOW_EN(bp) && BNXT_NUM_ASYNC_CPR(bp)) {
1168                 PMD_DRV_LOG(INFO, "Using vector mode receive for port %d\n",
1169                             eth_dev->data->port_id);
1170                 bp->flags |= BNXT_FLAG_RX_VECTOR_PKT_MODE;
1171                 return bnxt_recv_pkts_vec;
1172         }
1173         PMD_DRV_LOG(INFO, "Vector mode receive disabled for port %d\n",
1174                     eth_dev->data->port_id);
1175         PMD_DRV_LOG(INFO,
1176                     "Port %d scatter: %d rx offload: %" PRIX64 "\n",
1177                     eth_dev->data->port_id,
1178                     eth_dev->data->scattered_rx,
1179                     eth_dev->data->dev_conf.rxmode.offloads);
1180 #endif
1181 #endif
1182         bp->flags &= ~BNXT_FLAG_RX_VECTOR_PKT_MODE;
1183         return bnxt_recv_pkts;
1184 }
1185
1186 static eth_tx_burst_t
1187 bnxt_transmit_function(__rte_unused struct rte_eth_dev *eth_dev)
1188 {
1189 #if defined(RTE_ARCH_X86) || defined(RTE_ARCH_ARM64)
1190 #ifndef RTE_LIBRTE_IEEE1588
1191         struct bnxt *bp = eth_dev->data->dev_private;
1192
1193         /*
1194          * Vector mode transmit can be enabled only if not using scatter rx
1195          * or tx offloads.
1196          */
1197         if (!eth_dev->data->scattered_rx &&
1198             !eth_dev->data->dev_conf.txmode.offloads &&
1199             !BNXT_TRUFLOW_EN(bp)) {
1200                 PMD_DRV_LOG(INFO, "Using vector mode transmit for port %d\n",
1201                             eth_dev->data->port_id);
1202                 return bnxt_xmit_pkts_vec;
1203         }
1204         PMD_DRV_LOG(INFO, "Vector mode transmit disabled for port %d\n",
1205                     eth_dev->data->port_id);
1206         PMD_DRV_LOG(INFO,
1207                     "Port %d scatter: %d tx offload: %" PRIX64 "\n",
1208                     eth_dev->data->port_id,
1209                     eth_dev->data->scattered_rx,
1210                     eth_dev->data->dev_conf.txmode.offloads);
1211 #endif
1212 #endif
1213         return bnxt_xmit_pkts;
1214 }
1215
1216 static int bnxt_handle_if_change_status(struct bnxt *bp)
1217 {
1218         int rc;
1219
1220         /* Since fw has undergone a reset and lost all contexts,
1221          * set fatal flag to not issue hwrm during cleanup
1222          */
1223         bp->flags |= BNXT_FLAG_FATAL_ERROR;
1224         bnxt_uninit_resources(bp, true);
1225
1226         /* clear fatal flag so that re-init happens */
1227         bp->flags &= ~BNXT_FLAG_FATAL_ERROR;
1228         rc = bnxt_init_resources(bp, true);
1229
1230         bp->flags &= ~BNXT_FLAG_IF_CHANGE_HOT_FW_RESET_DONE;
1231
1232         return rc;
1233 }
1234
1235 static int bnxt_dev_start_op(struct rte_eth_dev *eth_dev)
1236 {
1237         struct bnxt *bp = eth_dev->data->dev_private;
1238         uint64_t rx_offloads = eth_dev->data->dev_conf.rxmode.offloads;
1239         int vlan_mask = 0;
1240         int rc, retry_cnt = BNXT_IF_CHANGE_RETRY_COUNT;
1241
1242         if (!eth_dev->data->nb_tx_queues || !eth_dev->data->nb_rx_queues) {
1243                 PMD_DRV_LOG(ERR, "Queues are not configured yet!\n");
1244                 return -EINVAL;
1245         }
1246
1247         if (bp->rx_cp_nr_rings > RTE_ETHDEV_QUEUE_STAT_CNTRS) {
1248                 PMD_DRV_LOG(ERR,
1249                         "RxQ cnt %d > CONFIG_RTE_ETHDEV_QUEUE_STAT_CNTRS %d\n",
1250                         bp->rx_cp_nr_rings, RTE_ETHDEV_QUEUE_STAT_CNTRS);
1251         }
1252
1253         do {
1254                 rc = bnxt_hwrm_if_change(bp, true);
1255                 if (rc == 0 || rc != -EAGAIN)
1256                         break;
1257
1258                 rte_delay_ms(BNXT_IF_CHANGE_RETRY_INTERVAL);
1259         } while (retry_cnt--);
1260
1261         if (rc)
1262                 return rc;
1263
1264         if (bp->flags & BNXT_FLAG_IF_CHANGE_HOT_FW_RESET_DONE) {
1265                 rc = bnxt_handle_if_change_status(bp);
1266                 if (rc)
1267                         return rc;
1268         }
1269
1270         bnxt_enable_int(bp);
1271
1272         rc = bnxt_init_chip(bp);
1273         if (rc)
1274                 goto error;
1275
1276         eth_dev->data->scattered_rx = bnxt_scattered_rx(eth_dev);
1277         eth_dev->data->dev_started = 1;
1278
1279         bnxt_link_update(eth_dev, 1, ETH_LINK_UP);
1280
1281         if (rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER)
1282                 vlan_mask |= ETH_VLAN_FILTER_MASK;
1283         if (rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
1284                 vlan_mask |= ETH_VLAN_STRIP_MASK;
1285         rc = bnxt_vlan_offload_set_op(eth_dev, vlan_mask);
1286         if (rc)
1287                 goto error;
1288
1289         /* Initialize bnxt ULP port details */
1290         rc = bnxt_ulp_port_init(bp);
1291         if (rc)
1292                 goto error;
1293
1294         eth_dev->rx_pkt_burst = bnxt_receive_function(eth_dev);
1295         eth_dev->tx_pkt_burst = bnxt_transmit_function(eth_dev);
1296
1297         bnxt_schedule_fw_health_check(bp);
1298
1299         return 0;
1300
1301 error:
1302         bnxt_shutdown_nic(bp);
1303         bnxt_free_tx_mbufs(bp);
1304         bnxt_free_rx_mbufs(bp);
1305         bnxt_hwrm_if_change(bp, false);
1306         eth_dev->data->dev_started = 0;
1307         return rc;
1308 }
1309
1310 static int bnxt_dev_set_link_up_op(struct rte_eth_dev *eth_dev)
1311 {
1312         struct bnxt *bp = eth_dev->data->dev_private;
1313         int rc = 0;
1314
1315         if (!bp->link_info->link_up)
1316                 rc = bnxt_set_hwrm_link_config(bp, true);
1317         if (!rc)
1318                 eth_dev->data->dev_link.link_status = 1;
1319
1320         bnxt_print_link_info(eth_dev);
1321         return rc;
1322 }
1323
1324 static int bnxt_dev_set_link_down_op(struct rte_eth_dev *eth_dev)
1325 {
1326         struct bnxt *bp = eth_dev->data->dev_private;
1327
1328         eth_dev->data->dev_link.link_status = 0;
1329         bnxt_set_hwrm_link_config(bp, false);
1330         bp->link_info->link_up = 0;
1331
1332         return 0;
1333 }
1334
1335 static void bnxt_free_switch_domain(struct bnxt *bp)
1336 {
1337         if (bp->switch_domain_id)
1338                 rte_eth_switch_domain_free(bp->switch_domain_id);
1339 }
1340
1341 /* Unload the driver, release resources */
1342 static void bnxt_dev_stop_op(struct rte_eth_dev *eth_dev)
1343 {
1344         struct bnxt *bp = eth_dev->data->dev_private;
1345         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1346         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1347
1348         eth_dev->data->dev_started = 0;
1349         eth_dev->data->scattered_rx = 0;
1350
1351         /* Prevent crashes when queues are still in use */
1352         eth_dev->rx_pkt_burst = &bnxt_dummy_recv_pkts;
1353         eth_dev->tx_pkt_burst = &bnxt_dummy_xmit_pkts;
1354
1355         bnxt_disable_int(bp);
1356
1357         /* disable uio/vfio intr/eventfd mapping */
1358         rte_intr_disable(intr_handle);
1359
1360         /* Stop the child representors for this device */
1361         bnxt_rep_stop_all(bp);
1362
1363         /* delete the bnxt ULP port details */
1364         bnxt_ulp_port_deinit(bp);
1365
1366         bnxt_cancel_fw_health_check(bp);
1367
1368         /* Do not bring link down during reset recovery */
1369         if (!is_bnxt_in_error(bp))
1370                 bnxt_dev_set_link_down_op(eth_dev);
1371
1372         /* Wait for link to be reset and the async notification to process.
1373          * During reset recovery, there is no need to wait and
1374          * VF/NPAR functions do not have privilege to change PHY config.
1375          */
1376         if (!is_bnxt_in_error(bp) && BNXT_SINGLE_PF(bp))
1377                 bnxt_link_update(eth_dev, 1, ETH_LINK_DOWN);
1378
1379         /* Clean queue intr-vector mapping */
1380         rte_intr_efd_disable(intr_handle);
1381         if (intr_handle->intr_vec != NULL) {
1382                 rte_free(intr_handle->intr_vec);
1383                 intr_handle->intr_vec = NULL;
1384         }
1385
1386         bnxt_hwrm_port_clr_stats(bp);
1387         bnxt_free_tx_mbufs(bp);
1388         bnxt_free_rx_mbufs(bp);
1389         /* Process any remaining notifications in default completion queue */
1390         bnxt_int_handler(eth_dev);
1391         bnxt_shutdown_nic(bp);
1392         bnxt_hwrm_if_change(bp, false);
1393
1394         rte_free(bp->mark_table);
1395         bp->mark_table = NULL;
1396
1397         bp->flags &= ~BNXT_FLAG_RX_VECTOR_PKT_MODE;
1398         bp->rx_cosq_cnt = 0;
1399         /* All filters are deleted on a port stop. */
1400         if (BNXT_FLOW_XSTATS_EN(bp))
1401                 bp->flow_stat->flow_count = 0;
1402 }
1403
1404 static void bnxt_dev_close_op(struct rte_eth_dev *eth_dev)
1405 {
1406         struct bnxt *bp = eth_dev->data->dev_private;
1407
1408         /* cancel the recovery handler before remove dev */
1409         rte_eal_alarm_cancel(bnxt_dev_reset_and_resume, (void *)bp);
1410         rte_eal_alarm_cancel(bnxt_dev_recover, (void *)bp);
1411         bnxt_cancel_fc_thread(bp);
1412
1413         if (eth_dev->data->dev_started)
1414                 bnxt_dev_stop_op(eth_dev);
1415
1416         bnxt_free_switch_domain(bp);
1417
1418         bnxt_uninit_resources(bp, false);
1419
1420         bnxt_free_leds_info(bp);
1421         bnxt_free_cos_queues(bp);
1422         bnxt_free_link_info(bp);
1423         bnxt_free_pf_info(bp);
1424         bnxt_free_parent_info(bp);
1425
1426         eth_dev->dev_ops = NULL;
1427         eth_dev->rx_pkt_burst = NULL;
1428         eth_dev->tx_pkt_burst = NULL;
1429
1430         rte_memzone_free((const struct rte_memzone *)bp->tx_mem_zone);
1431         bp->tx_mem_zone = NULL;
1432         rte_memzone_free((const struct rte_memzone *)bp->rx_mem_zone);
1433         bp->rx_mem_zone = NULL;
1434
1435         bnxt_hwrm_free_vf_info(bp);
1436
1437         rte_free(bp->grp_info);
1438         bp->grp_info = NULL;
1439 }
1440
1441 static void bnxt_mac_addr_remove_op(struct rte_eth_dev *eth_dev,
1442                                     uint32_t index)
1443 {
1444         struct bnxt *bp = eth_dev->data->dev_private;
1445         uint64_t pool_mask = eth_dev->data->mac_pool_sel[index];
1446         struct bnxt_vnic_info *vnic;
1447         struct bnxt_filter_info *filter, *temp_filter;
1448         uint32_t i;
1449
1450         if (is_bnxt_in_error(bp))
1451                 return;
1452
1453         /*
1454          * Loop through all VNICs from the specified filter flow pools to
1455          * remove the corresponding MAC addr filter
1456          */
1457         for (i = 0; i < bp->nr_vnics; i++) {
1458                 if (!(pool_mask & (1ULL << i)))
1459                         continue;
1460
1461                 vnic = &bp->vnic_info[i];
1462                 filter = STAILQ_FIRST(&vnic->filter);
1463                 while (filter) {
1464                         temp_filter = STAILQ_NEXT(filter, next);
1465                         if (filter->mac_index == index) {
1466                                 STAILQ_REMOVE(&vnic->filter, filter,
1467                                                 bnxt_filter_info, next);
1468                                 bnxt_hwrm_clear_l2_filter(bp, filter);
1469                                 bnxt_free_filter(bp, filter);
1470                         }
1471                         filter = temp_filter;
1472                 }
1473         }
1474 }
1475
1476 static int bnxt_add_mac_filter(struct bnxt *bp, struct bnxt_vnic_info *vnic,
1477                                struct rte_ether_addr *mac_addr, uint32_t index,
1478                                uint32_t pool)
1479 {
1480         struct bnxt_filter_info *filter;
1481         int rc = 0;
1482
1483         /* Attach requested MAC address to the new l2_filter */
1484         STAILQ_FOREACH(filter, &vnic->filter, next) {
1485                 if (filter->mac_index == index) {
1486                         PMD_DRV_LOG(DEBUG,
1487                                     "MAC addr already existed for pool %d\n",
1488                                     pool);
1489                         return 0;
1490                 }
1491         }
1492
1493         filter = bnxt_alloc_filter(bp);
1494         if (!filter) {
1495                 PMD_DRV_LOG(ERR, "L2 filter alloc failed\n");
1496                 return -ENODEV;
1497         }
1498
1499         /* bnxt_alloc_filter copies default MAC to filter->l2_addr. So,
1500          * if the MAC that's been programmed now is a different one, then,
1501          * copy that addr to filter->l2_addr
1502          */
1503         if (mac_addr)
1504                 memcpy(filter->l2_addr, mac_addr, RTE_ETHER_ADDR_LEN);
1505         filter->flags |= HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_OUTERMOST;
1506
1507         rc = bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id, filter);
1508         if (!rc) {
1509                 filter->mac_index = index;
1510                 if (filter->mac_index == 0)
1511                         STAILQ_INSERT_HEAD(&vnic->filter, filter, next);
1512                 else
1513                         STAILQ_INSERT_TAIL(&vnic->filter, filter, next);
1514         } else {
1515                 bnxt_free_filter(bp, filter);
1516         }
1517
1518         return rc;
1519 }
1520
1521 static int bnxt_mac_addr_add_op(struct rte_eth_dev *eth_dev,
1522                                 struct rte_ether_addr *mac_addr,
1523                                 uint32_t index, uint32_t pool)
1524 {
1525         struct bnxt *bp = eth_dev->data->dev_private;
1526         struct bnxt_vnic_info *vnic = &bp->vnic_info[pool];
1527         int rc = 0;
1528
1529         rc = is_bnxt_in_error(bp);
1530         if (rc)
1531                 return rc;
1532
1533         if (BNXT_VF(bp) & !BNXT_VF_IS_TRUSTED(bp)) {
1534                 PMD_DRV_LOG(ERR, "Cannot add MAC address to a VF interface\n");
1535                 return -ENOTSUP;
1536         }
1537
1538         if (!vnic) {
1539                 PMD_DRV_LOG(ERR, "VNIC not found for pool %d!\n", pool);
1540                 return -EINVAL;
1541         }
1542
1543         /* Filter settings will get applied when port is started */
1544         if (!eth_dev->data->dev_started)
1545                 return 0;
1546
1547         rc = bnxt_add_mac_filter(bp, vnic, mac_addr, index, pool);
1548
1549         return rc;
1550 }
1551
1552 int bnxt_link_update(struct rte_eth_dev *eth_dev, int wait_to_complete,
1553                      bool exp_link_status)
1554 {
1555         int rc = 0;
1556         struct bnxt *bp = eth_dev->data->dev_private;
1557         struct rte_eth_link new;
1558         int cnt = exp_link_status ? BNXT_LINK_UP_WAIT_CNT :
1559                   BNXT_LINK_DOWN_WAIT_CNT;
1560
1561         rc = is_bnxt_in_error(bp);
1562         if (rc)
1563                 return rc;
1564
1565         memset(&new, 0, sizeof(new));
1566         do {
1567                 /* Retrieve link info from hardware */
1568                 rc = bnxt_get_hwrm_link_config(bp, &new);
1569                 if (rc) {
1570                         new.link_speed = ETH_LINK_SPEED_100M;
1571                         new.link_duplex = ETH_LINK_FULL_DUPLEX;
1572                         PMD_DRV_LOG(ERR,
1573                                 "Failed to retrieve link rc = 0x%x!\n", rc);
1574                         goto out;
1575                 }
1576
1577                 if (!wait_to_complete || new.link_status == exp_link_status)
1578                         break;
1579
1580                 rte_delay_ms(BNXT_LINK_WAIT_INTERVAL);
1581         } while (cnt--);
1582
1583 out:
1584         /* Timed out or success */
1585         if (new.link_status != eth_dev->data->dev_link.link_status ||
1586         new.link_speed != eth_dev->data->dev_link.link_speed) {
1587                 rte_eth_linkstatus_set(eth_dev, &new);
1588
1589                 rte_eth_dev_callback_process(eth_dev,
1590                                              RTE_ETH_EVENT_INTR_LSC,
1591                                              NULL);
1592
1593                 bnxt_print_link_info(eth_dev);
1594         }
1595
1596         return rc;
1597 }
1598
1599 int bnxt_link_update_op(struct rte_eth_dev *eth_dev,
1600                         int wait_to_complete)
1601 {
1602         return bnxt_link_update(eth_dev, wait_to_complete, ETH_LINK_UP);
1603 }
1604
1605 static int bnxt_promiscuous_enable_op(struct rte_eth_dev *eth_dev)
1606 {
1607         struct bnxt *bp = eth_dev->data->dev_private;
1608         struct bnxt_vnic_info *vnic;
1609         uint32_t old_flags;
1610         int rc;
1611
1612         rc = is_bnxt_in_error(bp);
1613         if (rc)
1614                 return rc;
1615
1616         /* Filter settings will get applied when port is started */
1617         if (!eth_dev->data->dev_started)
1618                 return 0;
1619
1620         if (bp->vnic_info == NULL)
1621                 return 0;
1622
1623         vnic = BNXT_GET_DEFAULT_VNIC(bp);
1624
1625         old_flags = vnic->flags;
1626         vnic->flags |= BNXT_VNIC_INFO_PROMISC;
1627         rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1628         if (rc != 0)
1629                 vnic->flags = old_flags;
1630
1631         return rc;
1632 }
1633
1634 static int bnxt_promiscuous_disable_op(struct rte_eth_dev *eth_dev)
1635 {
1636         struct bnxt *bp = eth_dev->data->dev_private;
1637         struct bnxt_vnic_info *vnic;
1638         uint32_t old_flags;
1639         int rc;
1640
1641         rc = is_bnxt_in_error(bp);
1642         if (rc)
1643                 return rc;
1644
1645         /* Filter settings will get applied when port is started */
1646         if (!eth_dev->data->dev_started)
1647                 return 0;
1648
1649         if (bp->vnic_info == NULL)
1650                 return 0;
1651
1652         vnic = BNXT_GET_DEFAULT_VNIC(bp);
1653
1654         old_flags = vnic->flags;
1655         vnic->flags &= ~BNXT_VNIC_INFO_PROMISC;
1656         rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1657         if (rc != 0)
1658                 vnic->flags = old_flags;
1659
1660         return rc;
1661 }
1662
1663 static int bnxt_allmulticast_enable_op(struct rte_eth_dev *eth_dev)
1664 {
1665         struct bnxt *bp = eth_dev->data->dev_private;
1666         struct bnxt_vnic_info *vnic;
1667         uint32_t old_flags;
1668         int rc;
1669
1670         rc = is_bnxt_in_error(bp);
1671         if (rc)
1672                 return rc;
1673
1674         /* Filter settings will get applied when port is started */
1675         if (!eth_dev->data->dev_started)
1676                 return 0;
1677
1678         if (bp->vnic_info == NULL)
1679                 return 0;
1680
1681         vnic = BNXT_GET_DEFAULT_VNIC(bp);
1682
1683         old_flags = vnic->flags;
1684         vnic->flags |= BNXT_VNIC_INFO_ALLMULTI;
1685         rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1686         if (rc != 0)
1687                 vnic->flags = old_flags;
1688
1689         return rc;
1690 }
1691
1692 static int bnxt_allmulticast_disable_op(struct rte_eth_dev *eth_dev)
1693 {
1694         struct bnxt *bp = eth_dev->data->dev_private;
1695         struct bnxt_vnic_info *vnic;
1696         uint32_t old_flags;
1697         int rc;
1698
1699         rc = is_bnxt_in_error(bp);
1700         if (rc)
1701                 return rc;
1702
1703         /* Filter settings will get applied when port is started */
1704         if (!eth_dev->data->dev_started)
1705                 return 0;
1706
1707         if (bp->vnic_info == NULL)
1708                 return 0;
1709
1710         vnic = BNXT_GET_DEFAULT_VNIC(bp);
1711
1712         old_flags = vnic->flags;
1713         vnic->flags &= ~BNXT_VNIC_INFO_ALLMULTI;
1714         rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1715         if (rc != 0)
1716                 vnic->flags = old_flags;
1717
1718         return rc;
1719 }
1720
1721 /* Return bnxt_rx_queue pointer corresponding to a given rxq. */
1722 static struct bnxt_rx_queue *bnxt_qid_to_rxq(struct bnxt *bp, uint16_t qid)
1723 {
1724         if (qid >= bp->rx_nr_rings)
1725                 return NULL;
1726
1727         return bp->eth_dev->data->rx_queues[qid];
1728 }
1729
1730 /* Return rxq corresponding to a given rss table ring/group ID. */
1731 static uint16_t bnxt_rss_to_qid(struct bnxt *bp, uint16_t fwr)
1732 {
1733         struct bnxt_rx_queue *rxq;
1734         unsigned int i;
1735
1736         if (!BNXT_HAS_RING_GRPS(bp)) {
1737                 for (i = 0; i < bp->rx_nr_rings; i++) {
1738                         rxq = bp->eth_dev->data->rx_queues[i];
1739                         if (rxq->rx_ring->rx_ring_struct->fw_ring_id == fwr)
1740                                 return rxq->index;
1741                 }
1742         } else {
1743                 for (i = 0; i < bp->rx_nr_rings; i++) {
1744                         if (bp->grp_info[i].fw_grp_id == fwr)
1745                                 return i;
1746                 }
1747         }
1748
1749         return INVALID_HW_RING_ID;
1750 }
1751
1752 static int bnxt_reta_update_op(struct rte_eth_dev *eth_dev,
1753                             struct rte_eth_rss_reta_entry64 *reta_conf,
1754                             uint16_t reta_size)
1755 {
1756         struct bnxt *bp = eth_dev->data->dev_private;
1757         struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
1758         struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp);
1759         uint16_t tbl_size = bnxt_rss_hash_tbl_size(bp);
1760         uint16_t idx, sft;
1761         int i, rc;
1762
1763         rc = is_bnxt_in_error(bp);
1764         if (rc)
1765                 return rc;
1766
1767         if (!vnic->rss_table)
1768                 return -EINVAL;
1769
1770         if (!(dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG))
1771                 return -EINVAL;
1772
1773         if (reta_size != tbl_size) {
1774                 PMD_DRV_LOG(ERR, "The configured hash table lookup size "
1775                         "(%d) must equal the size supported by the hardware "
1776                         "(%d)\n", reta_size, tbl_size);
1777                 return -EINVAL;
1778         }
1779
1780         for (i = 0; i < reta_size; i++) {
1781                 struct bnxt_rx_queue *rxq;
1782
1783                 idx = i / RTE_RETA_GROUP_SIZE;
1784                 sft = i % RTE_RETA_GROUP_SIZE;
1785
1786                 if (!(reta_conf[idx].mask & (1ULL << sft)))
1787                         continue;
1788
1789                 rxq = bnxt_qid_to_rxq(bp, reta_conf[idx].reta[sft]);
1790                 if (!rxq) {
1791                         PMD_DRV_LOG(ERR, "Invalid ring in reta_conf.\n");
1792                         return -EINVAL;
1793                 }
1794
1795                 if (BNXT_CHIP_THOR(bp)) {
1796                         vnic->rss_table[i * 2] =
1797                                 rxq->rx_ring->rx_ring_struct->fw_ring_id;
1798                         vnic->rss_table[i * 2 + 1] =
1799                                 rxq->cp_ring->cp_ring_struct->fw_ring_id;
1800                 } else {
1801                         vnic->rss_table[i] =
1802                             vnic->fw_grp_ids[reta_conf[idx].reta[sft]];
1803                 }
1804         }
1805
1806         bnxt_hwrm_vnic_rss_cfg(bp, vnic);
1807         return 0;
1808 }
1809
1810 static int bnxt_reta_query_op(struct rte_eth_dev *eth_dev,
1811                               struct rte_eth_rss_reta_entry64 *reta_conf,
1812                               uint16_t reta_size)
1813 {
1814         struct bnxt *bp = eth_dev->data->dev_private;
1815         struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp);
1816         uint16_t tbl_size = bnxt_rss_hash_tbl_size(bp);
1817         uint16_t idx, sft, i;
1818         int rc;
1819
1820         rc = is_bnxt_in_error(bp);
1821         if (rc)
1822                 return rc;
1823
1824         /* Retrieve from the default VNIC */
1825         if (!vnic)
1826                 return -EINVAL;
1827         if (!vnic->rss_table)
1828                 return -EINVAL;
1829
1830         if (reta_size != tbl_size) {
1831                 PMD_DRV_LOG(ERR, "The configured hash table lookup size "
1832                         "(%d) must equal the size supported by the hardware "
1833                         "(%d)\n", reta_size, tbl_size);
1834                 return -EINVAL;
1835         }
1836
1837         for (idx = 0, i = 0; i < reta_size; i++) {
1838                 idx = i / RTE_RETA_GROUP_SIZE;
1839                 sft = i % RTE_RETA_GROUP_SIZE;
1840
1841                 if (reta_conf[idx].mask & (1ULL << sft)) {
1842                         uint16_t qid;
1843
1844                         if (BNXT_CHIP_THOR(bp))
1845                                 qid = bnxt_rss_to_qid(bp,
1846                                                       vnic->rss_table[i * 2]);
1847                         else
1848                                 qid = bnxt_rss_to_qid(bp, vnic->rss_table[i]);
1849
1850                         if (qid == INVALID_HW_RING_ID) {
1851                                 PMD_DRV_LOG(ERR, "Inv. entry in rss table.\n");
1852                                 return -EINVAL;
1853                         }
1854                         reta_conf[idx].reta[sft] = qid;
1855                 }
1856         }
1857
1858         return 0;
1859 }
1860
1861 static int bnxt_rss_hash_update_op(struct rte_eth_dev *eth_dev,
1862                                    struct rte_eth_rss_conf *rss_conf)
1863 {
1864         struct bnxt *bp = eth_dev->data->dev_private;
1865         struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
1866         struct bnxt_vnic_info *vnic;
1867         int rc;
1868
1869         rc = is_bnxt_in_error(bp);
1870         if (rc)
1871                 return rc;
1872
1873         /*
1874          * If RSS enablement were different than dev_configure,
1875          * then return -EINVAL
1876          */
1877         if (dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG) {
1878                 if (!rss_conf->rss_hf)
1879                         PMD_DRV_LOG(ERR, "Hash type NONE\n");
1880         } else {
1881                 if (rss_conf->rss_hf & BNXT_ETH_RSS_SUPPORT)
1882                         return -EINVAL;
1883         }
1884
1885         bp->flags |= BNXT_FLAG_UPDATE_HASH;
1886         memcpy(&eth_dev->data->dev_conf.rx_adv_conf.rss_conf,
1887                rss_conf,
1888                sizeof(*rss_conf));
1889
1890         /* Update the default RSS VNIC(s) */
1891         vnic = BNXT_GET_DEFAULT_VNIC(bp);
1892         vnic->hash_type = bnxt_rte_to_hwrm_hash_types(rss_conf->rss_hf);
1893
1894         /*
1895          * If hashkey is not specified, use the previously configured
1896          * hashkey
1897          */
1898         if (!rss_conf->rss_key)
1899                 goto rss_config;
1900
1901         if (rss_conf->rss_key_len != HW_HASH_KEY_SIZE) {
1902                 PMD_DRV_LOG(ERR,
1903                             "Invalid hashkey length, should be 16 bytes\n");
1904                 return -EINVAL;
1905         }
1906         memcpy(vnic->rss_hash_key, rss_conf->rss_key, rss_conf->rss_key_len);
1907
1908 rss_config:
1909         bnxt_hwrm_vnic_rss_cfg(bp, vnic);
1910         return 0;
1911 }
1912
1913 static int bnxt_rss_hash_conf_get_op(struct rte_eth_dev *eth_dev,
1914                                      struct rte_eth_rss_conf *rss_conf)
1915 {
1916         struct bnxt *bp = eth_dev->data->dev_private;
1917         struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp);
1918         int len, rc;
1919         uint32_t hash_types;
1920
1921         rc = is_bnxt_in_error(bp);
1922         if (rc)
1923                 return rc;
1924
1925         /* RSS configuration is the same for all VNICs */
1926         if (vnic && vnic->rss_hash_key) {
1927                 if (rss_conf->rss_key) {
1928                         len = rss_conf->rss_key_len <= HW_HASH_KEY_SIZE ?
1929                               rss_conf->rss_key_len : HW_HASH_KEY_SIZE;
1930                         memcpy(rss_conf->rss_key, vnic->rss_hash_key, len);
1931                 }
1932
1933                 hash_types = vnic->hash_type;
1934                 rss_conf->rss_hf = 0;
1935                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV4) {
1936                         rss_conf->rss_hf |= ETH_RSS_IPV4;
1937                         hash_types &= ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV4;
1938                 }
1939                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV4) {
1940                         rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP;
1941                         hash_types &=
1942                                 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV4;
1943                 }
1944                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV4) {
1945                         rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
1946                         hash_types &=
1947                                 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV4;
1948                 }
1949                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6) {
1950                         rss_conf->rss_hf |= ETH_RSS_IPV6;
1951                         hash_types &= ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6;
1952                 }
1953                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV6) {
1954                         rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV6_TCP;
1955                         hash_types &=
1956                                 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV6;
1957                 }
1958                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV6) {
1959                         rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;
1960                         hash_types &=
1961                                 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV6;
1962                 }
1963                 if (hash_types) {
1964                         PMD_DRV_LOG(ERR,
1965                                 "Unknown RSS config from firmware (%08x), RSS disabled",
1966                                 vnic->hash_type);
1967                         return -ENOTSUP;
1968                 }
1969         } else {
1970                 rss_conf->rss_hf = 0;
1971         }
1972         return 0;
1973 }
1974
1975 static int bnxt_flow_ctrl_get_op(struct rte_eth_dev *dev,
1976                                struct rte_eth_fc_conf *fc_conf)
1977 {
1978         struct bnxt *bp = dev->data->dev_private;
1979         struct rte_eth_link link_info;
1980         int rc;
1981
1982         rc = is_bnxt_in_error(bp);
1983         if (rc)
1984                 return rc;
1985
1986         rc = bnxt_get_hwrm_link_config(bp, &link_info);
1987         if (rc)
1988                 return rc;
1989
1990         memset(fc_conf, 0, sizeof(*fc_conf));
1991         if (bp->link_info->auto_pause)
1992                 fc_conf->autoneg = 1;
1993         switch (bp->link_info->pause) {
1994         case 0:
1995                 fc_conf->mode = RTE_FC_NONE;
1996                 break;
1997         case HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_TX:
1998                 fc_conf->mode = RTE_FC_TX_PAUSE;
1999                 break;
2000         case HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_RX:
2001                 fc_conf->mode = RTE_FC_RX_PAUSE;
2002                 break;
2003         case (HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_TX |
2004                         HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_RX):
2005                 fc_conf->mode = RTE_FC_FULL;
2006                 break;
2007         }
2008         return 0;
2009 }
2010
2011 static int bnxt_flow_ctrl_set_op(struct rte_eth_dev *dev,
2012                                struct rte_eth_fc_conf *fc_conf)
2013 {
2014         struct bnxt *bp = dev->data->dev_private;
2015         int rc;
2016
2017         rc = is_bnxt_in_error(bp);
2018         if (rc)
2019                 return rc;
2020
2021         if (!BNXT_SINGLE_PF(bp) || BNXT_VF(bp)) {
2022                 PMD_DRV_LOG(ERR, "Flow Control Settings cannot be modified\n");
2023                 return -ENOTSUP;
2024         }
2025
2026         switch (fc_conf->mode) {
2027         case RTE_FC_NONE:
2028                 bp->link_info->auto_pause = 0;
2029                 bp->link_info->force_pause = 0;
2030                 break;
2031         case RTE_FC_RX_PAUSE:
2032                 if (fc_conf->autoneg) {
2033                         bp->link_info->auto_pause =
2034                                         HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_RX;
2035                         bp->link_info->force_pause = 0;
2036                 } else {
2037                         bp->link_info->auto_pause = 0;
2038                         bp->link_info->force_pause =
2039                                         HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_RX;
2040                 }
2041                 break;
2042         case RTE_FC_TX_PAUSE:
2043                 if (fc_conf->autoneg) {
2044                         bp->link_info->auto_pause =
2045                                         HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_TX;
2046                         bp->link_info->force_pause = 0;
2047                 } else {
2048                         bp->link_info->auto_pause = 0;
2049                         bp->link_info->force_pause =
2050                                         HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_TX;
2051                 }
2052                 break;
2053         case RTE_FC_FULL:
2054                 if (fc_conf->autoneg) {
2055                         bp->link_info->auto_pause =
2056                                         HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_TX |
2057                                         HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_RX;
2058                         bp->link_info->force_pause = 0;
2059                 } else {
2060                         bp->link_info->auto_pause = 0;
2061                         bp->link_info->force_pause =
2062                                         HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_TX |
2063                                         HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_RX;
2064                 }
2065                 break;
2066         }
2067         return bnxt_set_hwrm_link_config(bp, true);
2068 }
2069
2070 /* Add UDP tunneling port */
2071 static int
2072 bnxt_udp_tunnel_port_add_op(struct rte_eth_dev *eth_dev,
2073                          struct rte_eth_udp_tunnel *udp_tunnel)
2074 {
2075         struct bnxt *bp = eth_dev->data->dev_private;
2076         uint16_t tunnel_type = 0;
2077         int rc = 0;
2078
2079         rc = is_bnxt_in_error(bp);
2080         if (rc)
2081                 return rc;
2082
2083         switch (udp_tunnel->prot_type) {
2084         case RTE_TUNNEL_TYPE_VXLAN:
2085                 if (bp->vxlan_port_cnt) {
2086                         PMD_DRV_LOG(ERR, "Tunnel Port %d already programmed\n",
2087                                 udp_tunnel->udp_port);
2088                         if (bp->vxlan_port != udp_tunnel->udp_port) {
2089                                 PMD_DRV_LOG(ERR, "Only one port allowed\n");
2090                                 return -ENOSPC;
2091                         }
2092                         bp->vxlan_port_cnt++;
2093                         return 0;
2094                 }
2095                 tunnel_type =
2096                         HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_VXLAN;
2097                 bp->vxlan_port_cnt++;
2098                 break;
2099         case RTE_TUNNEL_TYPE_GENEVE:
2100                 if (bp->geneve_port_cnt) {
2101                         PMD_DRV_LOG(ERR, "Tunnel Port %d already programmed\n",
2102                                 udp_tunnel->udp_port);
2103                         if (bp->geneve_port != udp_tunnel->udp_port) {
2104                                 PMD_DRV_LOG(ERR, "Only one port allowed\n");
2105                                 return -ENOSPC;
2106                         }
2107                         bp->geneve_port_cnt++;
2108                         return 0;
2109                 }
2110                 tunnel_type =
2111                         HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_GENEVE;
2112                 bp->geneve_port_cnt++;
2113                 break;
2114         default:
2115                 PMD_DRV_LOG(ERR, "Tunnel type is not supported\n");
2116                 return -ENOTSUP;
2117         }
2118         rc = bnxt_hwrm_tunnel_dst_port_alloc(bp, udp_tunnel->udp_port,
2119                                              tunnel_type);
2120         return rc;
2121 }
2122
2123 static int
2124 bnxt_udp_tunnel_port_del_op(struct rte_eth_dev *eth_dev,
2125                          struct rte_eth_udp_tunnel *udp_tunnel)
2126 {
2127         struct bnxt *bp = eth_dev->data->dev_private;
2128         uint16_t tunnel_type = 0;
2129         uint16_t port = 0;
2130         int rc = 0;
2131
2132         rc = is_bnxt_in_error(bp);
2133         if (rc)
2134                 return rc;
2135
2136         switch (udp_tunnel->prot_type) {
2137         case RTE_TUNNEL_TYPE_VXLAN:
2138                 if (!bp->vxlan_port_cnt) {
2139                         PMD_DRV_LOG(ERR, "No Tunnel port configured yet\n");
2140                         return -EINVAL;
2141                 }
2142                 if (bp->vxlan_port != udp_tunnel->udp_port) {
2143                         PMD_DRV_LOG(ERR, "Req Port: %d. Configured port: %d\n",
2144                                 udp_tunnel->udp_port, bp->vxlan_port);
2145                         return -EINVAL;
2146                 }
2147                 if (--bp->vxlan_port_cnt)
2148                         return 0;
2149
2150                 tunnel_type =
2151                         HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN;
2152                 port = bp->vxlan_fw_dst_port_id;
2153                 break;
2154         case RTE_TUNNEL_TYPE_GENEVE:
2155                 if (!bp->geneve_port_cnt) {
2156                         PMD_DRV_LOG(ERR, "No Tunnel port configured yet\n");
2157                         return -EINVAL;
2158                 }
2159                 if (bp->geneve_port != udp_tunnel->udp_port) {
2160                         PMD_DRV_LOG(ERR, "Req Port: %d. Configured port: %d\n",
2161                                 udp_tunnel->udp_port, bp->geneve_port);
2162                         return -EINVAL;
2163                 }
2164                 if (--bp->geneve_port_cnt)
2165                         return 0;
2166
2167                 tunnel_type =
2168                         HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_GENEVE;
2169                 port = bp->geneve_fw_dst_port_id;
2170                 break;
2171         default:
2172                 PMD_DRV_LOG(ERR, "Tunnel type is not supported\n");
2173                 return -ENOTSUP;
2174         }
2175
2176         rc = bnxt_hwrm_tunnel_dst_port_free(bp, port, tunnel_type);
2177         if (!rc) {
2178                 if (tunnel_type ==
2179                     HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN)
2180                         bp->vxlan_port = 0;
2181                 if (tunnel_type ==
2182                     HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_GENEVE)
2183                         bp->geneve_port = 0;
2184         }
2185         return rc;
2186 }
2187
2188 static int bnxt_del_vlan_filter(struct bnxt *bp, uint16_t vlan_id)
2189 {
2190         struct bnxt_filter_info *filter;
2191         struct bnxt_vnic_info *vnic;
2192         int rc = 0;
2193         uint32_t chk = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN;
2194
2195         vnic = BNXT_GET_DEFAULT_VNIC(bp);
2196         filter = STAILQ_FIRST(&vnic->filter);
2197         while (filter) {
2198                 /* Search for this matching MAC+VLAN filter */
2199                 if (bnxt_vlan_filter_exists(bp, filter, chk, vlan_id)) {
2200                         /* Delete the filter */
2201                         rc = bnxt_hwrm_clear_l2_filter(bp, filter);
2202                         if (rc)
2203                                 return rc;
2204                         STAILQ_REMOVE(&vnic->filter, filter,
2205                                       bnxt_filter_info, next);
2206                         bnxt_free_filter(bp, filter);
2207                         PMD_DRV_LOG(INFO,
2208                                     "Deleted vlan filter for %d\n",
2209                                     vlan_id);
2210                         return 0;
2211                 }
2212                 filter = STAILQ_NEXT(filter, next);
2213         }
2214         return -ENOENT;
2215 }
2216
2217 static int bnxt_add_vlan_filter(struct bnxt *bp, uint16_t vlan_id)
2218 {
2219         struct bnxt_filter_info *filter;
2220         struct bnxt_vnic_info *vnic;
2221         int rc = 0;
2222         uint32_t en = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN |
2223                 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN_MASK;
2224         uint32_t chk = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN;
2225
2226         /* Implementation notes on the use of VNIC in this command:
2227          *
2228          * By default, these filters belong to default vnic for the function.
2229          * Once these filters are set up, only destination VNIC can be modified.
2230          * If the destination VNIC is not specified in this command,
2231          * then the HWRM shall only create an l2 context id.
2232          */
2233
2234         vnic = BNXT_GET_DEFAULT_VNIC(bp);
2235         filter = STAILQ_FIRST(&vnic->filter);
2236         /* Check if the VLAN has already been added */
2237         while (filter) {
2238                 if (bnxt_vlan_filter_exists(bp, filter, chk, vlan_id))
2239                         return -EEXIST;
2240
2241                 filter = STAILQ_NEXT(filter, next);
2242         }
2243
2244         /* No match found. Alloc a fresh filter and issue the L2_FILTER_ALLOC
2245          * command to create MAC+VLAN filter with the right flags, enables set.
2246          */
2247         filter = bnxt_alloc_filter(bp);
2248         if (!filter) {
2249                 PMD_DRV_LOG(ERR,
2250                             "MAC/VLAN filter alloc failed\n");
2251                 return -ENOMEM;
2252         }
2253         /* MAC + VLAN ID filter */
2254         /* If l2_ivlan == 0 and l2_ivlan_mask != 0, only
2255          * untagged packets are received
2256          *
2257          * If l2_ivlan != 0 and l2_ivlan_mask != 0, untagged
2258          * packets and only the programmed vlan's packets are received
2259          */
2260         filter->l2_ivlan = vlan_id;
2261         filter->l2_ivlan_mask = 0x0FFF;
2262         filter->enables |= en;
2263         filter->flags |= HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_OUTERMOST;
2264
2265         rc = bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id, filter);
2266         if (rc) {
2267                 /* Free the newly allocated filter as we were
2268                  * not able to create the filter in hardware.
2269                  */
2270                 bnxt_free_filter(bp, filter);
2271                 return rc;
2272         }
2273
2274         filter->mac_index = 0;
2275         /* Add this new filter to the list */
2276         if (vlan_id == 0)
2277                 STAILQ_INSERT_HEAD(&vnic->filter, filter, next);
2278         else
2279                 STAILQ_INSERT_TAIL(&vnic->filter, filter, next);
2280
2281         PMD_DRV_LOG(INFO,
2282                     "Added Vlan filter for %d\n", vlan_id);
2283         return rc;
2284 }
2285
2286 static int bnxt_vlan_filter_set_op(struct rte_eth_dev *eth_dev,
2287                 uint16_t vlan_id, int on)
2288 {
2289         struct bnxt *bp = eth_dev->data->dev_private;
2290         int rc;
2291
2292         rc = is_bnxt_in_error(bp);
2293         if (rc)
2294                 return rc;
2295
2296         if (!eth_dev->data->dev_started) {
2297                 PMD_DRV_LOG(ERR, "port must be started before setting vlan\n");
2298                 return -EINVAL;
2299         }
2300
2301         /* These operations apply to ALL existing MAC/VLAN filters */
2302         if (on)
2303                 return bnxt_add_vlan_filter(bp, vlan_id);
2304         else
2305                 return bnxt_del_vlan_filter(bp, vlan_id);
2306 }
2307
2308 static int bnxt_del_dflt_mac_filter(struct bnxt *bp,
2309                                     struct bnxt_vnic_info *vnic)
2310 {
2311         struct bnxt_filter_info *filter;
2312         int rc;
2313
2314         filter = STAILQ_FIRST(&vnic->filter);
2315         while (filter) {
2316                 if (filter->mac_index == 0 &&
2317                     !memcmp(filter->l2_addr, bp->mac_addr,
2318                             RTE_ETHER_ADDR_LEN)) {
2319                         rc = bnxt_hwrm_clear_l2_filter(bp, filter);
2320                         if (!rc) {
2321                                 STAILQ_REMOVE(&vnic->filter, filter,
2322                                               bnxt_filter_info, next);
2323                                 bnxt_free_filter(bp, filter);
2324                         }
2325                         return rc;
2326                 }
2327                 filter = STAILQ_NEXT(filter, next);
2328         }
2329         return 0;
2330 }
2331
2332 static int
2333 bnxt_config_vlan_hw_filter(struct bnxt *bp, uint64_t rx_offloads)
2334 {
2335         struct bnxt_vnic_info *vnic;
2336         unsigned int i;
2337         int rc;
2338
2339         vnic = BNXT_GET_DEFAULT_VNIC(bp);
2340         if (!(rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER)) {
2341                 /* Remove any VLAN filters programmed */
2342                 for (i = 0; i < RTE_ETHER_MAX_VLAN_ID; i++)
2343                         bnxt_del_vlan_filter(bp, i);
2344
2345                 rc = bnxt_add_mac_filter(bp, vnic, NULL, 0, 0);
2346                 if (rc)
2347                         return rc;
2348         } else {
2349                 /* Default filter will allow packets that match the
2350                  * dest mac. So, it has to be deleted, otherwise, we
2351                  * will endup receiving vlan packets for which the
2352                  * filter is not programmed, when hw-vlan-filter
2353                  * configuration is ON
2354                  */
2355                 bnxt_del_dflt_mac_filter(bp, vnic);
2356                 /* This filter will allow only untagged packets */
2357                 bnxt_add_vlan_filter(bp, 0);
2358         }
2359         PMD_DRV_LOG(DEBUG, "VLAN Filtering: %d\n",
2360                     !!(rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER));
2361
2362         return 0;
2363 }
2364
2365 static int bnxt_free_one_vnic(struct bnxt *bp, uint16_t vnic_id)
2366 {
2367         struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id];
2368         unsigned int i;
2369         int rc;
2370
2371         /* Destroy vnic filters and vnic */
2372         if (bp->eth_dev->data->dev_conf.rxmode.offloads &
2373             DEV_RX_OFFLOAD_VLAN_FILTER) {
2374                 for (i = 0; i < RTE_ETHER_MAX_VLAN_ID; i++)
2375                         bnxt_del_vlan_filter(bp, i);
2376         }
2377         bnxt_del_dflt_mac_filter(bp, vnic);
2378
2379         rc = bnxt_hwrm_vnic_free(bp, vnic);
2380         if (rc)
2381                 return rc;
2382
2383         rte_free(vnic->fw_grp_ids);
2384         vnic->fw_grp_ids = NULL;
2385
2386         vnic->rx_queue_cnt = 0;
2387
2388         return 0;
2389 }
2390
2391 static int
2392 bnxt_config_vlan_hw_stripping(struct bnxt *bp, uint64_t rx_offloads)
2393 {
2394         struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp);
2395         int rc;
2396
2397         /* Destroy, recreate and reconfigure the default vnic */
2398         rc = bnxt_free_one_vnic(bp, 0);
2399         if (rc)
2400                 return rc;
2401
2402         /* default vnic 0 */
2403         rc = bnxt_setup_one_vnic(bp, 0);
2404         if (rc)
2405                 return rc;
2406
2407         if (bp->eth_dev->data->dev_conf.rxmode.offloads &
2408             DEV_RX_OFFLOAD_VLAN_FILTER) {
2409                 rc = bnxt_add_vlan_filter(bp, 0);
2410                 if (rc)
2411                         return rc;
2412                 rc = bnxt_restore_vlan_filters(bp);
2413                 if (rc)
2414                         return rc;
2415         } else {
2416                 rc = bnxt_add_mac_filter(bp, vnic, NULL, 0, 0);
2417                 if (rc)
2418                         return rc;
2419         }
2420
2421         rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
2422         if (rc)
2423                 return rc;
2424
2425         PMD_DRV_LOG(DEBUG, "VLAN Strip Offload: %d\n",
2426                     !!(rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP));
2427
2428         return rc;
2429 }
2430
2431 static int
2432 bnxt_vlan_offload_set_op(struct rte_eth_dev *dev, int mask)
2433 {
2434         uint64_t rx_offloads = dev->data->dev_conf.rxmode.offloads;
2435         struct bnxt *bp = dev->data->dev_private;
2436         int rc;
2437
2438         rc = is_bnxt_in_error(bp);
2439         if (rc)
2440                 return rc;
2441
2442         /* Filter settings will get applied when port is started */
2443         if (!dev->data->dev_started)
2444                 return 0;
2445
2446         if (mask & ETH_VLAN_FILTER_MASK) {
2447                 /* Enable or disable VLAN filtering */
2448                 rc = bnxt_config_vlan_hw_filter(bp, rx_offloads);
2449                 if (rc)
2450                         return rc;
2451         }
2452
2453         if (mask & ETH_VLAN_STRIP_MASK) {
2454                 /* Enable or disable VLAN stripping */
2455                 rc = bnxt_config_vlan_hw_stripping(bp, rx_offloads);
2456                 if (rc)
2457                         return rc;
2458         }
2459
2460         if (mask & ETH_VLAN_EXTEND_MASK) {
2461                 if (rx_offloads & DEV_RX_OFFLOAD_VLAN_EXTEND)
2462                         PMD_DRV_LOG(DEBUG, "Extend VLAN supported\n");
2463                 else
2464                         PMD_DRV_LOG(INFO, "Extend VLAN unsupported\n");
2465         }
2466
2467         return 0;
2468 }
2469
2470 static int
2471 bnxt_vlan_tpid_set_op(struct rte_eth_dev *dev, enum rte_vlan_type vlan_type,
2472                       uint16_t tpid)
2473 {
2474         struct bnxt *bp = dev->data->dev_private;
2475         int qinq = dev->data->dev_conf.rxmode.offloads &
2476                    DEV_RX_OFFLOAD_VLAN_EXTEND;
2477
2478         if (vlan_type != ETH_VLAN_TYPE_INNER &&
2479             vlan_type != ETH_VLAN_TYPE_OUTER) {
2480                 PMD_DRV_LOG(ERR,
2481                             "Unsupported vlan type.");
2482                 return -EINVAL;
2483         }
2484         if (!qinq) {
2485                 PMD_DRV_LOG(ERR,
2486                             "QinQ not enabled. Needs to be ON as we can "
2487                             "accelerate only outer vlan\n");
2488                 return -EINVAL;
2489         }
2490
2491         if (vlan_type == ETH_VLAN_TYPE_OUTER) {
2492                 switch (tpid) {
2493                 case RTE_ETHER_TYPE_QINQ:
2494                         bp->outer_tpid_bd =
2495                                 TX_BD_LONG_CFA_META_VLAN_TPID_TPID88A8;
2496                                 break;
2497                 case RTE_ETHER_TYPE_VLAN:
2498                         bp->outer_tpid_bd =
2499                                 TX_BD_LONG_CFA_META_VLAN_TPID_TPID8100;
2500                                 break;
2501                 case RTE_ETHER_TYPE_QINQ1:
2502                         bp->outer_tpid_bd =
2503                                 TX_BD_LONG_CFA_META_VLAN_TPID_TPID9100;
2504                                 break;
2505                 case RTE_ETHER_TYPE_QINQ2:
2506                         bp->outer_tpid_bd =
2507                                 TX_BD_LONG_CFA_META_VLAN_TPID_TPID9200;
2508                                 break;
2509                 case RTE_ETHER_TYPE_QINQ3:
2510                         bp->outer_tpid_bd =
2511                                  TX_BD_LONG_CFA_META_VLAN_TPID_TPID9300;
2512                                 break;
2513                 default:
2514                         PMD_DRV_LOG(ERR, "Invalid TPID: %x\n", tpid);
2515                         return -EINVAL;
2516                 }
2517                 bp->outer_tpid_bd |= tpid;
2518                 PMD_DRV_LOG(INFO, "outer_tpid_bd = %x\n", bp->outer_tpid_bd);
2519         } else if (vlan_type == ETH_VLAN_TYPE_INNER) {
2520                 PMD_DRV_LOG(ERR,
2521                             "Can accelerate only outer vlan in QinQ\n");
2522                 return -EINVAL;
2523         }
2524
2525         return 0;
2526 }
2527
2528 static int
2529 bnxt_set_default_mac_addr_op(struct rte_eth_dev *dev,
2530                              struct rte_ether_addr *addr)
2531 {
2532         struct bnxt *bp = dev->data->dev_private;
2533         /* Default Filter is tied to VNIC 0 */
2534         struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp);
2535         int rc;
2536
2537         rc = is_bnxt_in_error(bp);
2538         if (rc)
2539                 return rc;
2540
2541         if (BNXT_VF(bp) && !BNXT_VF_IS_TRUSTED(bp))
2542                 return -EPERM;
2543
2544         if (rte_is_zero_ether_addr(addr))
2545                 return -EINVAL;
2546
2547         /* Filter settings will get applied when port is started */
2548         if (!dev->data->dev_started)
2549                 return 0;
2550
2551         /* Check if the requested MAC is already added */
2552         if (memcmp(addr, bp->mac_addr, RTE_ETHER_ADDR_LEN) == 0)
2553                 return 0;
2554
2555         /* Destroy filter and re-create it */
2556         bnxt_del_dflt_mac_filter(bp, vnic);
2557
2558         memcpy(bp->mac_addr, addr, RTE_ETHER_ADDR_LEN);
2559         if (dev->data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_VLAN_FILTER) {
2560                 /* This filter will allow only untagged packets */
2561                 rc = bnxt_add_vlan_filter(bp, 0);
2562         } else {
2563                 rc = bnxt_add_mac_filter(bp, vnic, addr, 0, 0);
2564         }
2565
2566         PMD_DRV_LOG(DEBUG, "Set MAC addr\n");
2567         return rc;
2568 }
2569
2570 static int
2571 bnxt_dev_set_mc_addr_list_op(struct rte_eth_dev *eth_dev,
2572                           struct rte_ether_addr *mc_addr_set,
2573                           uint32_t nb_mc_addr)
2574 {
2575         struct bnxt *bp = eth_dev->data->dev_private;
2576         char *mc_addr_list = (char *)mc_addr_set;
2577         struct bnxt_vnic_info *vnic;
2578         uint32_t off = 0, i = 0;
2579         int rc;
2580
2581         rc = is_bnxt_in_error(bp);
2582         if (rc)
2583                 return rc;
2584
2585         vnic = BNXT_GET_DEFAULT_VNIC(bp);
2586
2587         if (nb_mc_addr > BNXT_MAX_MC_ADDRS) {
2588                 vnic->flags |= BNXT_VNIC_INFO_ALLMULTI;
2589                 goto allmulti;
2590         }
2591
2592         /* TODO Check for Duplicate mcast addresses */
2593         vnic->flags &= ~BNXT_VNIC_INFO_ALLMULTI;
2594         for (i = 0; i < nb_mc_addr; i++) {
2595                 memcpy(vnic->mc_list + off, &mc_addr_list[i],
2596                         RTE_ETHER_ADDR_LEN);
2597                 off += RTE_ETHER_ADDR_LEN;
2598         }
2599
2600         vnic->mc_addr_cnt = i;
2601         if (vnic->mc_addr_cnt)
2602                 vnic->flags |= BNXT_VNIC_INFO_MCAST;
2603         else
2604                 vnic->flags &= ~BNXT_VNIC_INFO_MCAST;
2605
2606 allmulti:
2607         return bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
2608 }
2609
2610 static int
2611 bnxt_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size)
2612 {
2613         struct bnxt *bp = dev->data->dev_private;
2614         uint8_t fw_major = (bp->fw_ver >> 24) & 0xff;
2615         uint8_t fw_minor = (bp->fw_ver >> 16) & 0xff;
2616         uint8_t fw_updt = (bp->fw_ver >> 8) & 0xff;
2617         uint8_t fw_rsvd = bp->fw_ver & 0xff;
2618         int ret;
2619
2620         ret = snprintf(fw_version, fw_size, "%d.%d.%d.%d",
2621                         fw_major, fw_minor, fw_updt, fw_rsvd);
2622
2623         ret += 1; /* add the size of '\0' */
2624         if (fw_size < (uint32_t)ret)
2625                 return ret;
2626         else
2627                 return 0;
2628 }
2629
2630 static void
2631 bnxt_rxq_info_get_op(struct rte_eth_dev *dev, uint16_t queue_id,
2632         struct rte_eth_rxq_info *qinfo)
2633 {
2634         struct bnxt *bp = dev->data->dev_private;
2635         struct bnxt_rx_queue *rxq;
2636
2637         if (is_bnxt_in_error(bp))
2638                 return;
2639
2640         rxq = dev->data->rx_queues[queue_id];
2641
2642         qinfo->mp = rxq->mb_pool;
2643         qinfo->scattered_rx = dev->data->scattered_rx;
2644         qinfo->nb_desc = rxq->nb_rx_desc;
2645
2646         qinfo->conf.rx_free_thresh = rxq->rx_free_thresh;
2647         qinfo->conf.rx_drop_en = 0;
2648         qinfo->conf.rx_deferred_start = rxq->rx_deferred_start;
2649 }
2650
2651 static void
2652 bnxt_txq_info_get_op(struct rte_eth_dev *dev, uint16_t queue_id,
2653         struct rte_eth_txq_info *qinfo)
2654 {
2655         struct bnxt *bp = dev->data->dev_private;
2656         struct bnxt_tx_queue *txq;
2657
2658         if (is_bnxt_in_error(bp))
2659                 return;
2660
2661         txq = dev->data->tx_queues[queue_id];
2662
2663         qinfo->nb_desc = txq->nb_tx_desc;
2664
2665         qinfo->conf.tx_thresh.pthresh = txq->pthresh;
2666         qinfo->conf.tx_thresh.hthresh = txq->hthresh;
2667         qinfo->conf.tx_thresh.wthresh = txq->wthresh;
2668
2669         qinfo->conf.tx_free_thresh = txq->tx_free_thresh;
2670         qinfo->conf.tx_rs_thresh = 0;
2671         qinfo->conf.tx_deferred_start = txq->tx_deferred_start;
2672 }
2673
2674 static const struct {
2675         eth_rx_burst_t pkt_burst;
2676         const char *info;
2677 } bnxt_rx_burst_info[] = {
2678         {bnxt_recv_pkts,        "Scalar"},
2679 #if defined(RTE_ARCH_X86)
2680         {bnxt_recv_pkts_vec,    "Vector SSE"},
2681 #elif defined(RTE_ARCH_ARM64)
2682         {bnxt_recv_pkts_vec,    "Vector Neon"},
2683 #endif
2684 };
2685
2686 static int
2687 bnxt_rx_burst_mode_get(struct rte_eth_dev *dev, __rte_unused uint16_t queue_id,
2688                        struct rte_eth_burst_mode *mode)
2689 {
2690         eth_rx_burst_t pkt_burst = dev->rx_pkt_burst;
2691         size_t i;
2692
2693         for (i = 0; i < RTE_DIM(bnxt_rx_burst_info); i++) {
2694                 if (pkt_burst == bnxt_rx_burst_info[i].pkt_burst) {
2695                         snprintf(mode->info, sizeof(mode->info), "%s",
2696                                  bnxt_rx_burst_info[i].info);
2697                         return 0;
2698                 }
2699         }
2700
2701         return -EINVAL;
2702 }
2703
2704 static const struct {
2705         eth_tx_burst_t pkt_burst;
2706         const char *info;
2707 } bnxt_tx_burst_info[] = {
2708         {bnxt_xmit_pkts,        "Scalar"},
2709 #if defined(RTE_ARCH_X86)
2710         {bnxt_xmit_pkts_vec,    "Vector SSE"},
2711 #elif defined(RTE_ARCH_ARM64)
2712         {bnxt_xmit_pkts_vec,    "Vector Neon"},
2713 #endif
2714 };
2715
2716 static int
2717 bnxt_tx_burst_mode_get(struct rte_eth_dev *dev, __rte_unused uint16_t queue_id,
2718                        struct rte_eth_burst_mode *mode)
2719 {
2720         eth_tx_burst_t pkt_burst = dev->tx_pkt_burst;
2721         size_t i;
2722
2723         for (i = 0; i < RTE_DIM(bnxt_tx_burst_info); i++) {
2724                 if (pkt_burst == bnxt_tx_burst_info[i].pkt_burst) {
2725                         snprintf(mode->info, sizeof(mode->info), "%s",
2726                                  bnxt_tx_burst_info[i].info);
2727                         return 0;
2728                 }
2729         }
2730
2731         return -EINVAL;
2732 }
2733
2734 int bnxt_mtu_set_op(struct rte_eth_dev *eth_dev, uint16_t new_mtu)
2735 {
2736         struct bnxt *bp = eth_dev->data->dev_private;
2737         uint32_t new_pkt_size;
2738         uint32_t rc = 0;
2739         uint32_t i;
2740
2741         rc = is_bnxt_in_error(bp);
2742         if (rc)
2743                 return rc;
2744
2745         /* Exit if receive queues are not configured yet */
2746         if (!eth_dev->data->nb_rx_queues)
2747                 return rc;
2748
2749         new_pkt_size = new_mtu + RTE_ETHER_HDR_LEN + RTE_ETHER_CRC_LEN +
2750                        VLAN_TAG_SIZE * BNXT_NUM_VLANS;
2751
2752         /*
2753          * Disallow any MTU change that would require scattered receive support
2754          * if it is not already enabled.
2755          */
2756         if (eth_dev->data->dev_started &&
2757             !eth_dev->data->scattered_rx &&
2758             (new_pkt_size >
2759              eth_dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM)) {
2760                 PMD_DRV_LOG(ERR,
2761                             "MTU change would require scattered rx support. ");
2762                 PMD_DRV_LOG(ERR, "Stop port before changing MTU.\n");
2763                 return -EINVAL;
2764         }
2765
2766         if (new_mtu > RTE_ETHER_MTU) {
2767                 bp->flags |= BNXT_FLAG_JUMBO;
2768                 bp->eth_dev->data->dev_conf.rxmode.offloads |=
2769                         DEV_RX_OFFLOAD_JUMBO_FRAME;
2770         } else {
2771                 bp->eth_dev->data->dev_conf.rxmode.offloads &=
2772                         ~DEV_RX_OFFLOAD_JUMBO_FRAME;
2773                 bp->flags &= ~BNXT_FLAG_JUMBO;
2774         }
2775
2776         /* Is there a change in mtu setting? */
2777         if (eth_dev->data->dev_conf.rxmode.max_rx_pkt_len == new_pkt_size)
2778                 return rc;
2779
2780         for (i = 0; i < bp->nr_vnics; i++) {
2781                 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
2782                 uint16_t size = 0;
2783
2784                 vnic->mru = BNXT_VNIC_MRU(new_mtu);
2785                 rc = bnxt_hwrm_vnic_cfg(bp, vnic);
2786                 if (rc)
2787                         break;
2788
2789                 size = rte_pktmbuf_data_room_size(bp->rx_queues[0]->mb_pool);
2790                 size -= RTE_PKTMBUF_HEADROOM;
2791
2792                 if (size < new_mtu) {
2793                         rc = bnxt_hwrm_vnic_plcmode_cfg(bp, vnic);
2794                         if (rc)
2795                                 return rc;
2796                 }
2797         }
2798
2799         if (!rc)
2800                 eth_dev->data->dev_conf.rxmode.max_rx_pkt_len = new_pkt_size;
2801
2802         PMD_DRV_LOG(INFO, "New MTU is %d\n", new_mtu);
2803
2804         return rc;
2805 }
2806
2807 static int
2808 bnxt_vlan_pvid_set_op(struct rte_eth_dev *dev, uint16_t pvid, int on)
2809 {
2810         struct bnxt *bp = dev->data->dev_private;
2811         uint16_t vlan = bp->vlan;
2812         int rc;
2813
2814         rc = is_bnxt_in_error(bp);
2815         if (rc)
2816                 return rc;
2817
2818         if (!BNXT_SINGLE_PF(bp) || BNXT_VF(bp)) {
2819                 PMD_DRV_LOG(ERR,
2820                         "PVID cannot be modified for this function\n");
2821                 return -ENOTSUP;
2822         }
2823         bp->vlan = on ? pvid : 0;
2824
2825         rc = bnxt_hwrm_set_default_vlan(bp, 0, 0);
2826         if (rc)
2827                 bp->vlan = vlan;
2828         return rc;
2829 }
2830
2831 static int
2832 bnxt_dev_led_on_op(struct rte_eth_dev *dev)
2833 {
2834         struct bnxt *bp = dev->data->dev_private;
2835         int rc;
2836
2837         rc = is_bnxt_in_error(bp);
2838         if (rc)
2839                 return rc;
2840
2841         return bnxt_hwrm_port_led_cfg(bp, true);
2842 }
2843
2844 static int
2845 bnxt_dev_led_off_op(struct rte_eth_dev *dev)
2846 {
2847         struct bnxt *bp = dev->data->dev_private;
2848         int rc;
2849
2850         rc = is_bnxt_in_error(bp);
2851         if (rc)
2852                 return rc;
2853
2854         return bnxt_hwrm_port_led_cfg(bp, false);
2855 }
2856
2857 static uint32_t
2858 bnxt_rx_queue_count_op(struct rte_eth_dev *dev, uint16_t rx_queue_id)
2859 {
2860         struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
2861         uint32_t desc = 0, raw_cons = 0, cons;
2862         struct bnxt_cp_ring_info *cpr;
2863         struct bnxt_rx_queue *rxq;
2864         struct rx_pkt_cmpl *rxcmp;
2865         int rc;
2866
2867         rc = is_bnxt_in_error(bp);
2868         if (rc)
2869                 return rc;
2870
2871         rxq = dev->data->rx_queues[rx_queue_id];
2872         cpr = rxq->cp_ring;
2873         raw_cons = cpr->cp_raw_cons;
2874
2875         while (1) {
2876                 cons = RING_CMP(cpr->cp_ring_struct, raw_cons);
2877                 rte_prefetch0(&cpr->cp_desc_ring[cons]);
2878                 rxcmp = (struct rx_pkt_cmpl *)&cpr->cp_desc_ring[cons];
2879
2880                 if (!CMP_VALID(rxcmp, raw_cons, cpr->cp_ring_struct)) {
2881                         break;
2882                 } else {
2883                         raw_cons++;
2884                         desc++;
2885                 }
2886         }
2887
2888         return desc;
2889 }
2890
2891 static int
2892 bnxt_rx_descriptor_status_op(void *rx_queue, uint16_t offset)
2893 {
2894         struct bnxt_rx_queue *rxq = (struct bnxt_rx_queue *)rx_queue;
2895         struct bnxt_rx_ring_info *rxr;
2896         struct bnxt_cp_ring_info *cpr;
2897         struct rte_mbuf *rx_buf;
2898         struct rx_pkt_cmpl *rxcmp;
2899         uint32_t cons, cp_cons;
2900         int rc;
2901
2902         if (!rxq)
2903                 return -EINVAL;
2904
2905         rc = is_bnxt_in_error(rxq->bp);
2906         if (rc)
2907                 return rc;
2908
2909         cpr = rxq->cp_ring;
2910         rxr = rxq->rx_ring;
2911
2912         if (offset >= rxq->nb_rx_desc)
2913                 return -EINVAL;
2914
2915         cons = RING_CMP(cpr->cp_ring_struct, offset);
2916         cp_cons = cpr->cp_raw_cons;
2917         rxcmp = (struct rx_pkt_cmpl *)&cpr->cp_desc_ring[cons];
2918
2919         if (cons > cp_cons) {
2920                 if (CMPL_VALID(rxcmp, cpr->valid))
2921                         return RTE_ETH_RX_DESC_DONE;
2922         } else {
2923                 if (CMPL_VALID(rxcmp, !cpr->valid))
2924                         return RTE_ETH_RX_DESC_DONE;
2925         }
2926         rx_buf = rxr->rx_buf_ring[cons];
2927         if (rx_buf == NULL || rx_buf == &rxq->fake_mbuf)
2928                 return RTE_ETH_RX_DESC_UNAVAIL;
2929
2930
2931         return RTE_ETH_RX_DESC_AVAIL;
2932 }
2933
2934 static int
2935 bnxt_tx_descriptor_status_op(void *tx_queue, uint16_t offset)
2936 {
2937         struct bnxt_tx_queue *txq = (struct bnxt_tx_queue *)tx_queue;
2938         struct bnxt_tx_ring_info *txr;
2939         struct bnxt_cp_ring_info *cpr;
2940         struct bnxt_sw_tx_bd *tx_buf;
2941         struct tx_pkt_cmpl *txcmp;
2942         uint32_t cons, cp_cons;
2943         int rc;
2944
2945         if (!txq)
2946                 return -EINVAL;
2947
2948         rc = is_bnxt_in_error(txq->bp);
2949         if (rc)
2950                 return rc;
2951
2952         cpr = txq->cp_ring;
2953         txr = txq->tx_ring;
2954
2955         if (offset >= txq->nb_tx_desc)
2956                 return -EINVAL;
2957
2958         cons = RING_CMP(cpr->cp_ring_struct, offset);
2959         txcmp = (struct tx_pkt_cmpl *)&cpr->cp_desc_ring[cons];
2960         cp_cons = cpr->cp_raw_cons;
2961
2962         if (cons > cp_cons) {
2963                 if (CMPL_VALID(txcmp, cpr->valid))
2964                         return RTE_ETH_TX_DESC_UNAVAIL;
2965         } else {
2966                 if (CMPL_VALID(txcmp, !cpr->valid))
2967                         return RTE_ETH_TX_DESC_UNAVAIL;
2968         }
2969         tx_buf = &txr->tx_buf_ring[cons];
2970         if (tx_buf->mbuf == NULL)
2971                 return RTE_ETH_TX_DESC_DONE;
2972
2973         return RTE_ETH_TX_DESC_FULL;
2974 }
2975
2976 static struct bnxt_filter_info *
2977 bnxt_match_and_validate_ether_filter(struct bnxt *bp,
2978                                 struct rte_eth_ethertype_filter *efilter,
2979                                 struct bnxt_vnic_info *vnic0,
2980                                 struct bnxt_vnic_info *vnic,
2981                                 int *ret)
2982 {
2983         struct bnxt_filter_info *mfilter = NULL;
2984         int match = 0;
2985         *ret = 0;
2986
2987         if (efilter->ether_type == RTE_ETHER_TYPE_IPV4 ||
2988                 efilter->ether_type == RTE_ETHER_TYPE_IPV6) {
2989                 PMD_DRV_LOG(ERR, "invalid ether_type(0x%04x) in"
2990                         " ethertype filter.", efilter->ether_type);
2991                 *ret = -EINVAL;
2992                 goto exit;
2993         }
2994         if (efilter->queue >= bp->rx_nr_rings) {
2995                 PMD_DRV_LOG(ERR, "Invalid queue %d\n", efilter->queue);
2996                 *ret = -EINVAL;
2997                 goto exit;
2998         }
2999
3000         vnic0 = BNXT_GET_DEFAULT_VNIC(bp);
3001         vnic = &bp->vnic_info[efilter->queue];
3002         if (vnic == NULL) {
3003                 PMD_DRV_LOG(ERR, "Invalid queue %d\n", efilter->queue);
3004                 *ret = -EINVAL;
3005                 goto exit;
3006         }
3007
3008         if (efilter->flags & RTE_ETHTYPE_FLAGS_DROP) {
3009                 STAILQ_FOREACH(mfilter, &vnic0->filter, next) {
3010                         if ((!memcmp(efilter->mac_addr.addr_bytes,
3011                                      mfilter->l2_addr, RTE_ETHER_ADDR_LEN) &&
3012                              mfilter->flags ==
3013                              HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_DROP &&
3014                              mfilter->ethertype == efilter->ether_type)) {
3015                                 match = 1;
3016                                 break;
3017                         }
3018                 }
3019         } else {
3020                 STAILQ_FOREACH(mfilter, &vnic->filter, next)
3021                         if ((!memcmp(efilter->mac_addr.addr_bytes,
3022                                      mfilter->l2_addr, RTE_ETHER_ADDR_LEN) &&
3023                              mfilter->ethertype == efilter->ether_type &&
3024                              mfilter->flags ==
3025                              HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_PATH_RX)) {
3026                                 match = 1;
3027                                 break;
3028                         }
3029         }
3030
3031         if (match)
3032                 *ret = -EEXIST;
3033
3034 exit:
3035         return mfilter;
3036 }
3037
3038 static int
3039 bnxt_ethertype_filter(struct rte_eth_dev *dev,
3040                         enum rte_filter_op filter_op,
3041                         void *arg)
3042 {
3043         struct bnxt *bp = dev->data->dev_private;
3044         struct rte_eth_ethertype_filter *efilter =
3045                         (struct rte_eth_ethertype_filter *)arg;
3046         struct bnxt_filter_info *bfilter, *filter1;
3047         struct bnxt_vnic_info *vnic, *vnic0;
3048         int ret;
3049
3050         if (filter_op == RTE_ETH_FILTER_NOP)
3051                 return 0;
3052
3053         if (arg == NULL) {
3054                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
3055                             filter_op);
3056                 return -EINVAL;
3057         }
3058
3059         vnic0 = BNXT_GET_DEFAULT_VNIC(bp);
3060         vnic = &bp->vnic_info[efilter->queue];
3061
3062         switch (filter_op) {
3063         case RTE_ETH_FILTER_ADD:
3064                 bnxt_match_and_validate_ether_filter(bp, efilter,
3065                                                         vnic0, vnic, &ret);
3066                 if (ret < 0)
3067                         return ret;
3068
3069                 bfilter = bnxt_get_unused_filter(bp);
3070                 if (bfilter == NULL) {
3071                         PMD_DRV_LOG(ERR,
3072                                 "Not enough resources for a new filter.\n");
3073                         return -ENOMEM;
3074                 }
3075                 bfilter->filter_type = HWRM_CFA_NTUPLE_FILTER;
3076                 memcpy(bfilter->l2_addr, efilter->mac_addr.addr_bytes,
3077                        RTE_ETHER_ADDR_LEN);
3078                 memcpy(bfilter->dst_macaddr, efilter->mac_addr.addr_bytes,
3079                        RTE_ETHER_ADDR_LEN);
3080                 bfilter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_MACADDR;
3081                 bfilter->ethertype = efilter->ether_type;
3082                 bfilter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
3083
3084                 filter1 = bnxt_get_l2_filter(bp, bfilter, vnic0);
3085                 if (filter1 == NULL) {
3086                         ret = -EINVAL;
3087                         goto cleanup;
3088                 }
3089                 bfilter->enables |=
3090                         HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID;
3091                 bfilter->fw_l2_filter_id = filter1->fw_l2_filter_id;
3092
3093                 bfilter->dst_id = vnic->fw_vnic_id;
3094
3095                 if (efilter->flags & RTE_ETHTYPE_FLAGS_DROP) {
3096                         bfilter->flags =
3097                                 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_DROP;
3098                 }
3099
3100                 ret = bnxt_hwrm_set_ntuple_filter(bp, bfilter->dst_id, bfilter);
3101                 if (ret)
3102                         goto cleanup;
3103                 STAILQ_INSERT_TAIL(&vnic->filter, bfilter, next);
3104                 break;
3105         case RTE_ETH_FILTER_DELETE:
3106                 filter1 = bnxt_match_and_validate_ether_filter(bp, efilter,
3107                                                         vnic0, vnic, &ret);
3108                 if (ret == -EEXIST) {
3109                         ret = bnxt_hwrm_clear_ntuple_filter(bp, filter1);
3110
3111                         STAILQ_REMOVE(&vnic->filter, filter1, bnxt_filter_info,
3112                                       next);
3113                         bnxt_free_filter(bp, filter1);
3114                 } else if (ret == 0) {
3115                         PMD_DRV_LOG(ERR, "No matching filter found\n");
3116                 }
3117                 break;
3118         default:
3119                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
3120                 ret = -EINVAL;
3121                 goto error;
3122         }
3123         return ret;
3124 cleanup:
3125         bnxt_free_filter(bp, bfilter);
3126 error:
3127         return ret;
3128 }
3129
3130 static inline int
3131 parse_ntuple_filter(struct bnxt *bp,
3132                     struct rte_eth_ntuple_filter *nfilter,
3133                     struct bnxt_filter_info *bfilter)
3134 {
3135         uint32_t en = 0;
3136
3137         if (nfilter->queue >= bp->rx_nr_rings) {
3138                 PMD_DRV_LOG(ERR, "Invalid queue %d\n", nfilter->queue);
3139                 return -EINVAL;
3140         }
3141
3142         switch (nfilter->dst_port_mask) {
3143         case UINT16_MAX:
3144                 bfilter->dst_port_mask = -1;
3145                 bfilter->dst_port = nfilter->dst_port;
3146                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT |
3147                         NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
3148                 break;
3149         default:
3150                 PMD_DRV_LOG(ERR, "invalid dst_port mask.");
3151                 return -EINVAL;
3152         }
3153
3154         bfilter->ip_addr_type = NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4;
3155         en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
3156
3157         switch (nfilter->proto_mask) {
3158         case UINT8_MAX:
3159                 if (nfilter->proto == 17) /* IPPROTO_UDP */
3160                         bfilter->ip_protocol = 17;
3161                 else if (nfilter->proto == 6) /* IPPROTO_TCP */
3162                         bfilter->ip_protocol = 6;
3163                 else
3164                         return -EINVAL;
3165                 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
3166                 break;
3167         default:
3168                 PMD_DRV_LOG(ERR, "invalid protocol mask.");
3169                 return -EINVAL;
3170         }
3171
3172         switch (nfilter->dst_ip_mask) {
3173         case UINT32_MAX:
3174                 bfilter->dst_ipaddr_mask[0] = -1;
3175                 bfilter->dst_ipaddr[0] = nfilter->dst_ip;
3176                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR |
3177                         NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
3178                 break;
3179         default:
3180                 PMD_DRV_LOG(ERR, "invalid dst_ip mask.");
3181                 return -EINVAL;
3182         }
3183
3184         switch (nfilter->src_ip_mask) {
3185         case UINT32_MAX:
3186                 bfilter->src_ipaddr_mask[0] = -1;
3187                 bfilter->src_ipaddr[0] = nfilter->src_ip;
3188                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR |
3189                         NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
3190                 break;
3191         default:
3192                 PMD_DRV_LOG(ERR, "invalid src_ip mask.");
3193                 return -EINVAL;
3194         }
3195
3196         switch (nfilter->src_port_mask) {
3197         case UINT16_MAX:
3198                 bfilter->src_port_mask = -1;
3199                 bfilter->src_port = nfilter->src_port;
3200                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT |
3201                         NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
3202                 break;
3203         default:
3204                 PMD_DRV_LOG(ERR, "invalid src_port mask.");
3205                 return -EINVAL;
3206         }
3207
3208         bfilter->enables = en;
3209         return 0;
3210 }
3211
3212 static struct bnxt_filter_info*
3213 bnxt_match_ntuple_filter(struct bnxt *bp,
3214                          struct bnxt_filter_info *bfilter,
3215                          struct bnxt_vnic_info **mvnic)
3216 {
3217         struct bnxt_filter_info *mfilter = NULL;
3218         int i;
3219
3220         for (i = bp->nr_vnics - 1; i >= 0; i--) {
3221                 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
3222                 STAILQ_FOREACH(mfilter, &vnic->filter, next) {
3223                         if (bfilter->src_ipaddr[0] == mfilter->src_ipaddr[0] &&
3224                             bfilter->src_ipaddr_mask[0] ==
3225                             mfilter->src_ipaddr_mask[0] &&
3226                             bfilter->src_port == mfilter->src_port &&
3227                             bfilter->src_port_mask == mfilter->src_port_mask &&
3228                             bfilter->dst_ipaddr[0] == mfilter->dst_ipaddr[0] &&
3229                             bfilter->dst_ipaddr_mask[0] ==
3230                             mfilter->dst_ipaddr_mask[0] &&
3231                             bfilter->dst_port == mfilter->dst_port &&
3232                             bfilter->dst_port_mask == mfilter->dst_port_mask &&
3233                             bfilter->flags == mfilter->flags &&
3234                             bfilter->enables == mfilter->enables) {
3235                                 if (mvnic)
3236                                         *mvnic = vnic;
3237                                 return mfilter;
3238                         }
3239                 }
3240         }
3241         return NULL;
3242 }
3243
3244 static int
3245 bnxt_cfg_ntuple_filter(struct bnxt *bp,
3246                        struct rte_eth_ntuple_filter *nfilter,
3247                        enum rte_filter_op filter_op)
3248 {
3249         struct bnxt_filter_info *bfilter, *mfilter, *filter1;
3250         struct bnxt_vnic_info *vnic, *vnic0, *mvnic;
3251         int ret;
3252
3253         if (nfilter->flags != RTE_5TUPLE_FLAGS) {
3254                 PMD_DRV_LOG(ERR, "only 5tuple is supported.");
3255                 return -EINVAL;
3256         }
3257
3258         if (nfilter->flags & RTE_NTUPLE_FLAGS_TCP_FLAG) {
3259                 PMD_DRV_LOG(ERR, "Ntuple filter: TCP flags not supported\n");
3260                 return -EINVAL;
3261         }
3262
3263         bfilter = bnxt_get_unused_filter(bp);
3264         if (bfilter == NULL) {
3265                 PMD_DRV_LOG(ERR,
3266                         "Not enough resources for a new filter.\n");
3267                 return -ENOMEM;
3268         }
3269         ret = parse_ntuple_filter(bp, nfilter, bfilter);
3270         if (ret < 0)
3271                 goto free_filter;
3272
3273         vnic = &bp->vnic_info[nfilter->queue];
3274         vnic0 = BNXT_GET_DEFAULT_VNIC(bp);
3275         filter1 = STAILQ_FIRST(&vnic0->filter);
3276         if (filter1 == NULL) {
3277                 ret = -EINVAL;
3278                 goto free_filter;
3279         }
3280
3281         bfilter->dst_id = vnic->fw_vnic_id;
3282         bfilter->fw_l2_filter_id = filter1->fw_l2_filter_id;
3283         bfilter->enables |=
3284                 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID;
3285         bfilter->ethertype = 0x800;
3286         bfilter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
3287
3288         mfilter = bnxt_match_ntuple_filter(bp, bfilter, &mvnic);
3289
3290         if (mfilter != NULL && filter_op == RTE_ETH_FILTER_ADD &&
3291             bfilter->dst_id == mfilter->dst_id) {
3292                 PMD_DRV_LOG(ERR, "filter exists.\n");
3293                 ret = -EEXIST;
3294                 goto free_filter;
3295         } else if (mfilter != NULL && filter_op == RTE_ETH_FILTER_ADD &&
3296                    bfilter->dst_id != mfilter->dst_id) {
3297                 mfilter->dst_id = vnic->fw_vnic_id;
3298                 ret = bnxt_hwrm_set_ntuple_filter(bp, mfilter->dst_id, mfilter);
3299                 STAILQ_REMOVE(&mvnic->filter, mfilter, bnxt_filter_info, next);
3300                 STAILQ_INSERT_TAIL(&vnic->filter, mfilter, next);
3301                 PMD_DRV_LOG(ERR, "filter with matching pattern exists.\n");
3302                 PMD_DRV_LOG(ERR, " Updated it to the new destination queue\n");
3303                 goto free_filter;
3304         }
3305         if (mfilter == NULL && filter_op == RTE_ETH_FILTER_DELETE) {
3306                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
3307                 ret = -ENOENT;
3308                 goto free_filter;
3309         }
3310
3311         if (filter_op == RTE_ETH_FILTER_ADD) {
3312                 bfilter->filter_type = HWRM_CFA_NTUPLE_FILTER;
3313                 ret = bnxt_hwrm_set_ntuple_filter(bp, bfilter->dst_id, bfilter);
3314                 if (ret)
3315                         goto free_filter;
3316                 STAILQ_INSERT_TAIL(&vnic->filter, bfilter, next);
3317         } else {
3318                 if (mfilter == NULL) {
3319                         /* This should not happen. But for Coverity! */
3320                         ret = -ENOENT;
3321                         goto free_filter;
3322                 }
3323                 ret = bnxt_hwrm_clear_ntuple_filter(bp, mfilter);
3324
3325                 STAILQ_REMOVE(&vnic->filter, mfilter, bnxt_filter_info, next);
3326                 bnxt_free_filter(bp, mfilter);
3327                 bnxt_free_filter(bp, bfilter);
3328         }
3329
3330         return 0;
3331 free_filter:
3332         bnxt_free_filter(bp, bfilter);
3333         return ret;
3334 }
3335
3336 static int
3337 bnxt_ntuple_filter(struct rte_eth_dev *dev,
3338                         enum rte_filter_op filter_op,
3339                         void *arg)
3340 {
3341         struct bnxt *bp = dev->data->dev_private;
3342         int ret;
3343
3344         if (filter_op == RTE_ETH_FILTER_NOP)
3345                 return 0;
3346
3347         if (arg == NULL) {
3348                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
3349                             filter_op);
3350                 return -EINVAL;
3351         }
3352
3353         switch (filter_op) {
3354         case RTE_ETH_FILTER_ADD:
3355                 ret = bnxt_cfg_ntuple_filter(bp,
3356                         (struct rte_eth_ntuple_filter *)arg,
3357                         filter_op);
3358                 break;
3359         case RTE_ETH_FILTER_DELETE:
3360                 ret = bnxt_cfg_ntuple_filter(bp,
3361                         (struct rte_eth_ntuple_filter *)arg,
3362                         filter_op);
3363                 break;
3364         default:
3365                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
3366                 ret = -EINVAL;
3367                 break;
3368         }
3369         return ret;
3370 }
3371
3372 static int
3373 bnxt_parse_fdir_filter(struct bnxt *bp,
3374                        struct rte_eth_fdir_filter *fdir,
3375                        struct bnxt_filter_info *filter)
3376 {
3377         enum rte_fdir_mode fdir_mode =
3378                 bp->eth_dev->data->dev_conf.fdir_conf.mode;
3379         struct bnxt_vnic_info *vnic0, *vnic;
3380         struct bnxt_filter_info *filter1;
3381         uint32_t en = 0;
3382         int i;
3383
3384         if (fdir_mode == RTE_FDIR_MODE_PERFECT_TUNNEL)
3385                 return -EINVAL;
3386
3387         filter->l2_ovlan = fdir->input.flow_ext.vlan_tci;
3388         en |= EM_FLOW_ALLOC_INPUT_EN_OVLAN_VID;
3389
3390         switch (fdir->input.flow_type) {
3391         case RTE_ETH_FLOW_IPV4:
3392         case RTE_ETH_FLOW_NONFRAG_IPV4_OTHER:
3393                 /* FALLTHROUGH */
3394                 filter->src_ipaddr[0] = fdir->input.flow.ip4_flow.src_ip;
3395                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
3396                 filter->dst_ipaddr[0] = fdir->input.flow.ip4_flow.dst_ip;
3397                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
3398                 filter->ip_protocol = fdir->input.flow.ip4_flow.proto;
3399                 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
3400                 filter->ip_addr_type =
3401                         NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4;
3402                 filter->src_ipaddr_mask[0] = 0xffffffff;
3403                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
3404                 filter->dst_ipaddr_mask[0] = 0xffffffff;
3405                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
3406                 filter->ethertype = 0x800;
3407                 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
3408                 break;
3409         case RTE_ETH_FLOW_NONFRAG_IPV4_TCP:
3410                 filter->src_port = fdir->input.flow.tcp4_flow.src_port;
3411                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT;
3412                 filter->dst_port = fdir->input.flow.tcp4_flow.dst_port;
3413                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT;
3414                 filter->dst_port_mask = 0xffff;
3415                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
3416                 filter->src_port_mask = 0xffff;
3417                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
3418                 filter->src_ipaddr[0] = fdir->input.flow.tcp4_flow.ip.src_ip;
3419                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
3420                 filter->dst_ipaddr[0] = fdir->input.flow.tcp4_flow.ip.dst_ip;
3421                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
3422                 filter->ip_protocol = 6;
3423                 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
3424                 filter->ip_addr_type =
3425                         NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4;
3426                 filter->src_ipaddr_mask[0] = 0xffffffff;
3427                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
3428                 filter->dst_ipaddr_mask[0] = 0xffffffff;
3429                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
3430                 filter->ethertype = 0x800;
3431                 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
3432                 break;
3433         case RTE_ETH_FLOW_NONFRAG_IPV4_UDP:
3434                 filter->src_port = fdir->input.flow.udp4_flow.src_port;
3435                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT;
3436                 filter->dst_port = fdir->input.flow.udp4_flow.dst_port;
3437                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT;
3438                 filter->dst_port_mask = 0xffff;
3439                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
3440                 filter->src_port_mask = 0xffff;
3441                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
3442                 filter->src_ipaddr[0] = fdir->input.flow.udp4_flow.ip.src_ip;
3443                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
3444                 filter->dst_ipaddr[0] = fdir->input.flow.udp4_flow.ip.dst_ip;
3445                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
3446                 filter->ip_protocol = 17;
3447                 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
3448                 filter->ip_addr_type =
3449                         NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4;
3450                 filter->src_ipaddr_mask[0] = 0xffffffff;
3451                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
3452                 filter->dst_ipaddr_mask[0] = 0xffffffff;
3453                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
3454                 filter->ethertype = 0x800;
3455                 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
3456                 break;
3457         case RTE_ETH_FLOW_IPV6:
3458         case RTE_ETH_FLOW_NONFRAG_IPV6_OTHER:
3459                 /* FALLTHROUGH */
3460                 filter->ip_addr_type =
3461                         NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV6;
3462                 filter->ip_protocol = fdir->input.flow.ipv6_flow.proto;
3463                 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
3464                 rte_memcpy(filter->src_ipaddr,
3465                            fdir->input.flow.ipv6_flow.src_ip, 16);
3466                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
3467                 rte_memcpy(filter->dst_ipaddr,
3468                            fdir->input.flow.ipv6_flow.dst_ip, 16);
3469                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
3470                 memset(filter->dst_ipaddr_mask, 0xff, 16);
3471                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
3472                 memset(filter->src_ipaddr_mask, 0xff, 16);
3473                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
3474                 filter->ethertype = 0x86dd;
3475                 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
3476                 break;
3477         case RTE_ETH_FLOW_NONFRAG_IPV6_TCP:
3478                 filter->src_port = fdir->input.flow.tcp6_flow.src_port;
3479                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT;
3480                 filter->dst_port = fdir->input.flow.tcp6_flow.dst_port;
3481                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT;
3482                 filter->dst_port_mask = 0xffff;
3483                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
3484                 filter->src_port_mask = 0xffff;
3485                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
3486                 filter->ip_addr_type =
3487                         NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV6;
3488                 filter->ip_protocol = fdir->input.flow.tcp6_flow.ip.proto;
3489                 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
3490                 rte_memcpy(filter->src_ipaddr,
3491                            fdir->input.flow.tcp6_flow.ip.src_ip, 16);
3492                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
3493                 rte_memcpy(filter->dst_ipaddr,
3494                            fdir->input.flow.tcp6_flow.ip.dst_ip, 16);
3495                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
3496                 memset(filter->dst_ipaddr_mask, 0xff, 16);
3497                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
3498                 memset(filter->src_ipaddr_mask, 0xff, 16);
3499                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
3500                 filter->ethertype = 0x86dd;
3501                 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
3502                 break;
3503         case RTE_ETH_FLOW_NONFRAG_IPV6_UDP:
3504                 filter->src_port = fdir->input.flow.udp6_flow.src_port;
3505                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT;
3506                 filter->dst_port = fdir->input.flow.udp6_flow.dst_port;
3507                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT;
3508                 filter->dst_port_mask = 0xffff;
3509                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
3510                 filter->src_port_mask = 0xffff;
3511                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
3512                 filter->ip_addr_type =
3513                         NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV6;
3514                 filter->ip_protocol = fdir->input.flow.udp6_flow.ip.proto;
3515                 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
3516                 rte_memcpy(filter->src_ipaddr,
3517                            fdir->input.flow.udp6_flow.ip.src_ip, 16);
3518                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
3519                 rte_memcpy(filter->dst_ipaddr,
3520                            fdir->input.flow.udp6_flow.ip.dst_ip, 16);
3521                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
3522                 memset(filter->dst_ipaddr_mask, 0xff, 16);
3523                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
3524                 memset(filter->src_ipaddr_mask, 0xff, 16);
3525                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
3526                 filter->ethertype = 0x86dd;
3527                 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
3528                 break;
3529         case RTE_ETH_FLOW_L2_PAYLOAD:
3530                 filter->ethertype = fdir->input.flow.l2_flow.ether_type;
3531                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
3532                 break;
3533         case RTE_ETH_FLOW_VXLAN:
3534                 if (fdir->action.behavior == RTE_ETH_FDIR_REJECT)
3535                         return -EINVAL;
3536                 filter->vni = fdir->input.flow.tunnel_flow.tunnel_id;
3537                 filter->tunnel_type =
3538                         CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN;
3539                 en |= HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_TUNNEL_TYPE;
3540                 break;
3541         case RTE_ETH_FLOW_NVGRE:
3542                 if (fdir->action.behavior == RTE_ETH_FDIR_REJECT)
3543                         return -EINVAL;
3544                 filter->vni = fdir->input.flow.tunnel_flow.tunnel_id;
3545                 filter->tunnel_type =
3546                         CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_NVGRE;
3547                 en |= HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_TUNNEL_TYPE;
3548                 break;
3549         case RTE_ETH_FLOW_UNKNOWN:
3550         case RTE_ETH_FLOW_RAW:
3551         case RTE_ETH_FLOW_FRAG_IPV4:
3552         case RTE_ETH_FLOW_NONFRAG_IPV4_SCTP:
3553         case RTE_ETH_FLOW_FRAG_IPV6:
3554         case RTE_ETH_FLOW_NONFRAG_IPV6_SCTP:
3555         case RTE_ETH_FLOW_IPV6_EX:
3556         case RTE_ETH_FLOW_IPV6_TCP_EX:
3557         case RTE_ETH_FLOW_IPV6_UDP_EX:
3558         case RTE_ETH_FLOW_GENEVE:
3559                 /* FALLTHROUGH */
3560         default:
3561                 return -EINVAL;
3562         }
3563
3564         vnic0 = BNXT_GET_DEFAULT_VNIC(bp);
3565         vnic = &bp->vnic_info[fdir->action.rx_queue];
3566         if (vnic == NULL) {
3567                 PMD_DRV_LOG(ERR, "Invalid queue %d\n", fdir->action.rx_queue);
3568                 return -EINVAL;
3569         }
3570
3571         if (fdir_mode == RTE_FDIR_MODE_PERFECT_MAC_VLAN) {
3572                 rte_memcpy(filter->dst_macaddr,
3573                         fdir->input.flow.mac_vlan_flow.mac_addr.addr_bytes, 6);
3574                         en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_MACADDR;
3575         }
3576
3577         if (fdir->action.behavior == RTE_ETH_FDIR_REJECT) {
3578                 filter->flags = HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_DROP;
3579                 filter1 = STAILQ_FIRST(&vnic0->filter);
3580                 //filter1 = bnxt_get_l2_filter(bp, filter, vnic0);
3581         } else {
3582                 filter->dst_id = vnic->fw_vnic_id;
3583                 for (i = 0; i < RTE_ETHER_ADDR_LEN; i++)
3584                         if (filter->dst_macaddr[i] == 0x00)
3585                                 filter1 = STAILQ_FIRST(&vnic0->filter);
3586                         else
3587                                 filter1 = bnxt_get_l2_filter(bp, filter, vnic);
3588         }
3589
3590         if (filter1 == NULL)
3591                 return -EINVAL;
3592
3593         en |= HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID;
3594         filter->fw_l2_filter_id = filter1->fw_l2_filter_id;
3595
3596         filter->enables = en;
3597
3598         return 0;
3599 }
3600
3601 static struct bnxt_filter_info *
3602 bnxt_match_fdir(struct bnxt *bp, struct bnxt_filter_info *nf,
3603                 struct bnxt_vnic_info **mvnic)
3604 {
3605         struct bnxt_filter_info *mf = NULL;
3606         int i;
3607
3608         for (i = bp->nr_vnics - 1; i >= 0; i--) {
3609                 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
3610
3611                 STAILQ_FOREACH(mf, &vnic->filter, next) {
3612                         if (mf->filter_type == nf->filter_type &&
3613                             mf->flags == nf->flags &&
3614                             mf->src_port == nf->src_port &&
3615                             mf->src_port_mask == nf->src_port_mask &&
3616                             mf->dst_port == nf->dst_port &&
3617                             mf->dst_port_mask == nf->dst_port_mask &&
3618                             mf->ip_protocol == nf->ip_protocol &&
3619                             mf->ip_addr_type == nf->ip_addr_type &&
3620                             mf->ethertype == nf->ethertype &&
3621                             mf->vni == nf->vni &&
3622                             mf->tunnel_type == nf->tunnel_type &&
3623                             mf->l2_ovlan == nf->l2_ovlan &&
3624                             mf->l2_ovlan_mask == nf->l2_ovlan_mask &&
3625                             mf->l2_ivlan == nf->l2_ivlan &&
3626                             mf->l2_ivlan_mask == nf->l2_ivlan_mask &&
3627                             !memcmp(mf->l2_addr, nf->l2_addr,
3628                                     RTE_ETHER_ADDR_LEN) &&
3629                             !memcmp(mf->l2_addr_mask, nf->l2_addr_mask,
3630                                     RTE_ETHER_ADDR_LEN) &&
3631                             !memcmp(mf->src_macaddr, nf->src_macaddr,
3632                                     RTE_ETHER_ADDR_LEN) &&
3633                             !memcmp(mf->dst_macaddr, nf->dst_macaddr,
3634                                     RTE_ETHER_ADDR_LEN) &&
3635                             !memcmp(mf->src_ipaddr, nf->src_ipaddr,
3636                                     sizeof(nf->src_ipaddr)) &&
3637                             !memcmp(mf->src_ipaddr_mask, nf->src_ipaddr_mask,
3638                                     sizeof(nf->src_ipaddr_mask)) &&
3639                             !memcmp(mf->dst_ipaddr, nf->dst_ipaddr,
3640                                     sizeof(nf->dst_ipaddr)) &&
3641                             !memcmp(mf->dst_ipaddr_mask, nf->dst_ipaddr_mask,
3642                                     sizeof(nf->dst_ipaddr_mask))) {
3643                                 if (mvnic)
3644                                         *mvnic = vnic;
3645                                 return mf;
3646                         }
3647                 }
3648         }
3649         return NULL;
3650 }
3651
3652 static int
3653 bnxt_fdir_filter(struct rte_eth_dev *dev,
3654                  enum rte_filter_op filter_op,
3655                  void *arg)
3656 {
3657         struct bnxt *bp = dev->data->dev_private;
3658         struct rte_eth_fdir_filter *fdir  = (struct rte_eth_fdir_filter *)arg;
3659         struct bnxt_filter_info *filter, *match;
3660         struct bnxt_vnic_info *vnic, *mvnic;
3661         int ret = 0, i;
3662
3663         if (filter_op == RTE_ETH_FILTER_NOP)
3664                 return 0;
3665
3666         if (arg == NULL && filter_op != RTE_ETH_FILTER_FLUSH)
3667                 return -EINVAL;
3668
3669         switch (filter_op) {
3670         case RTE_ETH_FILTER_ADD:
3671         case RTE_ETH_FILTER_DELETE:
3672                 /* FALLTHROUGH */
3673                 filter = bnxt_get_unused_filter(bp);
3674                 if (filter == NULL) {
3675                         PMD_DRV_LOG(ERR,
3676                                 "Not enough resources for a new flow.\n");
3677                         return -ENOMEM;
3678                 }
3679
3680                 ret = bnxt_parse_fdir_filter(bp, fdir, filter);
3681                 if (ret != 0)
3682                         goto free_filter;
3683                 filter->filter_type = HWRM_CFA_NTUPLE_FILTER;
3684
3685                 if (fdir->action.behavior == RTE_ETH_FDIR_REJECT)
3686                         vnic = &bp->vnic_info[0];
3687                 else
3688                         vnic = &bp->vnic_info[fdir->action.rx_queue];
3689
3690                 match = bnxt_match_fdir(bp, filter, &mvnic);
3691                 if (match != NULL && filter_op == RTE_ETH_FILTER_ADD) {
3692                         if (match->dst_id == vnic->fw_vnic_id) {
3693                                 PMD_DRV_LOG(ERR, "Flow already exists.\n");
3694                                 ret = -EEXIST;
3695                                 goto free_filter;
3696                         } else {
3697                                 match->dst_id = vnic->fw_vnic_id;
3698                                 ret = bnxt_hwrm_set_ntuple_filter(bp,
3699                                                                   match->dst_id,
3700                                                                   match);
3701                                 STAILQ_REMOVE(&mvnic->filter, match,
3702                                               bnxt_filter_info, next);
3703                                 STAILQ_INSERT_TAIL(&vnic->filter, match, next);
3704                                 PMD_DRV_LOG(ERR,
3705                                         "Filter with matching pattern exist\n");
3706                                 PMD_DRV_LOG(ERR,
3707                                         "Updated it to new destination q\n");
3708                                 goto free_filter;
3709                         }
3710                 }
3711                 if (match == NULL && filter_op == RTE_ETH_FILTER_DELETE) {
3712                         PMD_DRV_LOG(ERR, "Flow does not exist.\n");
3713                         ret = -ENOENT;
3714                         goto free_filter;
3715                 }
3716
3717                 if (filter_op == RTE_ETH_FILTER_ADD) {
3718                         ret = bnxt_hwrm_set_ntuple_filter(bp,
3719                                                           filter->dst_id,
3720                                                           filter);
3721                         if (ret)
3722                                 goto free_filter;
3723                         STAILQ_INSERT_TAIL(&vnic->filter, filter, next);
3724                 } else {
3725                         ret = bnxt_hwrm_clear_ntuple_filter(bp, match);
3726                         STAILQ_REMOVE(&vnic->filter, match,
3727                                       bnxt_filter_info, next);
3728                         bnxt_free_filter(bp, match);
3729                         bnxt_free_filter(bp, filter);
3730                 }
3731                 break;
3732         case RTE_ETH_FILTER_FLUSH:
3733                 for (i = bp->nr_vnics - 1; i >= 0; i--) {
3734                         struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
3735
3736                         STAILQ_FOREACH(filter, &vnic->filter, next) {
3737                                 if (filter->filter_type ==
3738                                     HWRM_CFA_NTUPLE_FILTER) {
3739                                         ret =
3740                                         bnxt_hwrm_clear_ntuple_filter(bp,
3741                                                                       filter);
3742                                         STAILQ_REMOVE(&vnic->filter, filter,
3743                                                       bnxt_filter_info, next);
3744                                 }
3745                         }
3746                 }
3747                 return ret;
3748         case RTE_ETH_FILTER_UPDATE:
3749         case RTE_ETH_FILTER_STATS:
3750         case RTE_ETH_FILTER_INFO:
3751                 PMD_DRV_LOG(ERR, "operation %u not implemented", filter_op);
3752                 break;
3753         default:
3754                 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
3755                 ret = -EINVAL;
3756                 break;
3757         }
3758         return ret;
3759
3760 free_filter:
3761         bnxt_free_filter(bp, filter);
3762         return ret;
3763 }
3764
3765 int
3766 bnxt_filter_ctrl_op(struct rte_eth_dev *dev,
3767                     enum rte_filter_type filter_type,
3768                     enum rte_filter_op filter_op, void *arg)
3769 {
3770         struct bnxt *bp = dev->data->dev_private;
3771         int ret = 0;
3772
3773         if (!bp)
3774                 return -EIO;
3775
3776         if (BNXT_ETH_DEV_IS_REPRESENTOR(dev)) {
3777                 struct bnxt_representor *vfr = dev->data->dev_private;
3778                 bp = vfr->parent_dev->data->dev_private;
3779                 /* parent is deleted while children are still valid */
3780                 if (!bp) {
3781                         PMD_DRV_LOG(DEBUG, "BNXT Port:%d VFR Error %d:%d\n",
3782                                     dev->data->port_id,
3783                                     filter_type,
3784                                     filter_op);
3785                         return -EIO;
3786                 }
3787         }
3788
3789         ret = is_bnxt_in_error(bp);
3790         if (ret)
3791                 return ret;
3792
3793         switch (filter_type) {
3794         case RTE_ETH_FILTER_TUNNEL:
3795                 PMD_DRV_LOG(ERR,
3796                         "filter type: %d: To be implemented\n", filter_type);
3797                 break;
3798         case RTE_ETH_FILTER_FDIR:
3799                 ret = bnxt_fdir_filter(dev, filter_op, arg);
3800                 break;
3801         case RTE_ETH_FILTER_NTUPLE:
3802                 ret = bnxt_ntuple_filter(dev, filter_op, arg);
3803                 break;
3804         case RTE_ETH_FILTER_ETHERTYPE:
3805                 ret = bnxt_ethertype_filter(dev, filter_op, arg);
3806                 break;
3807         case RTE_ETH_FILTER_GENERIC:
3808                 if (filter_op != RTE_ETH_FILTER_GET)
3809                         return -EINVAL;
3810                 if (BNXT_TRUFLOW_EN(bp))
3811                         *(const void **)arg = &bnxt_ulp_rte_flow_ops;
3812                 else
3813                         *(const void **)arg = &bnxt_flow_ops;
3814                 break;
3815         default:
3816                 PMD_DRV_LOG(ERR,
3817                         "Filter type (%d) not supported", filter_type);
3818                 ret = -EINVAL;
3819                 break;
3820         }
3821         return ret;
3822 }
3823
3824 static const uint32_t *
3825 bnxt_dev_supported_ptypes_get_op(struct rte_eth_dev *dev)
3826 {
3827         static const uint32_t ptypes[] = {
3828                 RTE_PTYPE_L2_ETHER_VLAN,
3829                 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN,
3830                 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN,
3831                 RTE_PTYPE_L4_ICMP,
3832                 RTE_PTYPE_L4_TCP,
3833                 RTE_PTYPE_L4_UDP,
3834                 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN,
3835                 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN,
3836                 RTE_PTYPE_INNER_L4_ICMP,
3837                 RTE_PTYPE_INNER_L4_TCP,
3838                 RTE_PTYPE_INNER_L4_UDP,
3839                 RTE_PTYPE_UNKNOWN
3840         };
3841
3842         if (!dev->rx_pkt_burst)
3843                 return NULL;
3844
3845         return ptypes;
3846 }
3847
3848 static int bnxt_map_regs(struct bnxt *bp, uint32_t *reg_arr, int count,
3849                          int reg_win)
3850 {
3851         uint32_t reg_base = *reg_arr & 0xfffff000;
3852         uint32_t win_off;
3853         int i;
3854
3855         for (i = 0; i < count; i++) {
3856                 if ((reg_arr[i] & 0xfffff000) != reg_base)
3857                         return -ERANGE;
3858         }
3859         win_off = BNXT_GRCPF_REG_WINDOW_BASE_OUT + (reg_win - 1) * 4;
3860         rte_write32(reg_base, (uint8_t *)bp->bar0 + win_off);
3861         return 0;
3862 }
3863
3864 static int bnxt_map_ptp_regs(struct bnxt *bp)
3865 {
3866         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3867         uint32_t *reg_arr;
3868         int rc, i;
3869
3870         reg_arr = ptp->rx_regs;
3871         rc = bnxt_map_regs(bp, reg_arr, BNXT_PTP_RX_REGS, 5);
3872         if (rc)
3873                 return rc;
3874
3875         reg_arr = ptp->tx_regs;
3876         rc = bnxt_map_regs(bp, reg_arr, BNXT_PTP_TX_REGS, 6);
3877         if (rc)
3878                 return rc;
3879
3880         for (i = 0; i < BNXT_PTP_RX_REGS; i++)
3881                 ptp->rx_mapped_regs[i] = 0x5000 + (ptp->rx_regs[i] & 0xfff);
3882
3883         for (i = 0; i < BNXT_PTP_TX_REGS; i++)
3884                 ptp->tx_mapped_regs[i] = 0x6000 + (ptp->tx_regs[i] & 0xfff);
3885
3886         return 0;
3887 }
3888
3889 static void bnxt_unmap_ptp_regs(struct bnxt *bp)
3890 {
3891         rte_write32(0, (uint8_t *)bp->bar0 +
3892                          BNXT_GRCPF_REG_WINDOW_BASE_OUT + 16);
3893         rte_write32(0, (uint8_t *)bp->bar0 +
3894                          BNXT_GRCPF_REG_WINDOW_BASE_OUT + 20);
3895 }
3896
3897 static uint64_t bnxt_cc_read(struct bnxt *bp)
3898 {
3899         uint64_t ns;
3900
3901         ns = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3902                               BNXT_GRCPF_REG_SYNC_TIME));
3903         ns |= (uint64_t)(rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3904                                           BNXT_GRCPF_REG_SYNC_TIME + 4))) << 32;
3905         return ns;
3906 }
3907
3908 static int bnxt_get_tx_ts(struct bnxt *bp, uint64_t *ts)
3909 {
3910         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3911         uint32_t fifo;
3912
3913         fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3914                                 ptp->tx_mapped_regs[BNXT_PTP_TX_FIFO]));
3915         if (fifo & BNXT_PTP_TX_FIFO_EMPTY)
3916                 return -EAGAIN;
3917
3918         fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3919                                 ptp->tx_mapped_regs[BNXT_PTP_TX_FIFO]));
3920         *ts = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3921                                 ptp->tx_mapped_regs[BNXT_PTP_TX_TS_L]));
3922         *ts |= (uint64_t)rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3923                                 ptp->tx_mapped_regs[BNXT_PTP_TX_TS_H])) << 32;
3924
3925         return 0;
3926 }
3927
3928 static int bnxt_get_rx_ts(struct bnxt *bp, uint64_t *ts)
3929 {
3930         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3931         struct bnxt_pf_info *pf = bp->pf;
3932         uint16_t port_id;
3933         uint32_t fifo;
3934
3935         if (!ptp)
3936                 return -ENODEV;
3937
3938         fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3939                                 ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO]));
3940         if (!(fifo & BNXT_PTP_RX_FIFO_PENDING))
3941                 return -EAGAIN;
3942
3943         port_id = pf->port_id;
3944         rte_write32(1 << port_id, (uint8_t *)bp->bar0 +
3945                ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO_ADV]);
3946
3947         fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3948                                    ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO]));
3949         if (fifo & BNXT_PTP_RX_FIFO_PENDING) {
3950 /*              bnxt_clr_rx_ts(bp);       TBD  */
3951                 return -EBUSY;
3952         }
3953
3954         *ts = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3955                                 ptp->rx_mapped_regs[BNXT_PTP_RX_TS_L]));
3956         *ts |= (uint64_t)rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3957                                 ptp->rx_mapped_regs[BNXT_PTP_RX_TS_H])) << 32;
3958
3959         return 0;
3960 }
3961
3962 static int
3963 bnxt_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
3964 {
3965         uint64_t ns;
3966         struct bnxt *bp = dev->data->dev_private;
3967         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3968
3969         if (!ptp)
3970                 return 0;
3971
3972         ns = rte_timespec_to_ns(ts);
3973         /* Set the timecounters to a new value. */
3974         ptp->tc.nsec = ns;
3975
3976         return 0;
3977 }
3978
3979 static int
3980 bnxt_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
3981 {
3982         struct bnxt *bp = dev->data->dev_private;
3983         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3984         uint64_t ns, systime_cycles = 0;
3985         int rc = 0;
3986
3987         if (!ptp)
3988                 return 0;
3989
3990         if (BNXT_CHIP_THOR(bp))
3991                 rc = bnxt_hwrm_port_ts_query(bp, BNXT_PTP_FLAGS_CURRENT_TIME,
3992                                              &systime_cycles);
3993         else
3994                 systime_cycles = bnxt_cc_read(bp);
3995
3996         ns = rte_timecounter_update(&ptp->tc, systime_cycles);
3997         *ts = rte_ns_to_timespec(ns);
3998
3999         return rc;
4000 }
4001 static int
4002 bnxt_timesync_enable(struct rte_eth_dev *dev)
4003 {
4004         struct bnxt *bp = dev->data->dev_private;
4005         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
4006         uint32_t shift = 0;
4007         int rc;
4008
4009         if (!ptp)
4010                 return 0;
4011
4012         ptp->rx_filter = 1;
4013         ptp->tx_tstamp_en = 1;
4014         ptp->rxctl = BNXT_PTP_MSG_EVENTS;
4015
4016         rc = bnxt_hwrm_ptp_cfg(bp);
4017         if (rc)
4018                 return rc;
4019
4020         memset(&ptp->tc, 0, sizeof(struct rte_timecounter));
4021         memset(&ptp->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
4022         memset(&ptp->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
4023
4024         ptp->tc.cc_mask = BNXT_CYCLECOUNTER_MASK;
4025         ptp->tc.cc_shift = shift;
4026         ptp->tc.nsec_mask = (1ULL << shift) - 1;
4027
4028         ptp->rx_tstamp_tc.cc_mask = BNXT_CYCLECOUNTER_MASK;
4029         ptp->rx_tstamp_tc.cc_shift = shift;
4030         ptp->rx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
4031
4032         ptp->tx_tstamp_tc.cc_mask = BNXT_CYCLECOUNTER_MASK;
4033         ptp->tx_tstamp_tc.cc_shift = shift;
4034         ptp->tx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
4035
4036         if (!BNXT_CHIP_THOR(bp))
4037                 bnxt_map_ptp_regs(bp);
4038
4039         return 0;
4040 }
4041
4042 static int
4043 bnxt_timesync_disable(struct rte_eth_dev *dev)
4044 {
4045         struct bnxt *bp = dev->data->dev_private;
4046         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
4047
4048         if (!ptp)
4049                 return 0;
4050
4051         ptp->rx_filter = 0;
4052         ptp->tx_tstamp_en = 0;
4053         ptp->rxctl = 0;
4054
4055         bnxt_hwrm_ptp_cfg(bp);
4056
4057         if (!BNXT_CHIP_THOR(bp))
4058                 bnxt_unmap_ptp_regs(bp);
4059
4060         return 0;
4061 }
4062
4063 static int
4064 bnxt_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
4065                                  struct timespec *timestamp,
4066                                  uint32_t flags __rte_unused)
4067 {
4068         struct bnxt *bp = dev->data->dev_private;
4069         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
4070         uint64_t rx_tstamp_cycles = 0;
4071         uint64_t ns;
4072
4073         if (!ptp)
4074                 return 0;
4075
4076         if (BNXT_CHIP_THOR(bp))
4077                 rx_tstamp_cycles = ptp->rx_timestamp;
4078         else
4079                 bnxt_get_rx_ts(bp, &rx_tstamp_cycles);
4080
4081         ns = rte_timecounter_update(&ptp->rx_tstamp_tc, rx_tstamp_cycles);
4082         *timestamp = rte_ns_to_timespec(ns);
4083         return  0;
4084 }
4085
4086 static int
4087 bnxt_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
4088                                  struct timespec *timestamp)
4089 {
4090         struct bnxt *bp = dev->data->dev_private;
4091         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
4092         uint64_t tx_tstamp_cycles = 0;
4093         uint64_t ns;
4094         int rc = 0;
4095
4096         if (!ptp)
4097                 return 0;
4098
4099         if (BNXT_CHIP_THOR(bp))
4100                 rc = bnxt_hwrm_port_ts_query(bp, BNXT_PTP_FLAGS_PATH_TX,
4101                                              &tx_tstamp_cycles);
4102         else
4103                 rc = bnxt_get_tx_ts(bp, &tx_tstamp_cycles);
4104
4105         ns = rte_timecounter_update(&ptp->tx_tstamp_tc, tx_tstamp_cycles);
4106         *timestamp = rte_ns_to_timespec(ns);
4107
4108         return rc;
4109 }
4110
4111 static int
4112 bnxt_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
4113 {
4114         struct bnxt *bp = dev->data->dev_private;
4115         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
4116
4117         if (!ptp)
4118                 return 0;
4119
4120         ptp->tc.nsec += delta;
4121
4122         return 0;
4123 }
4124
4125 static int
4126 bnxt_get_eeprom_length_op(struct rte_eth_dev *dev)
4127 {
4128         struct bnxt *bp = dev->data->dev_private;
4129         int rc;
4130         uint32_t dir_entries;
4131         uint32_t entry_length;
4132
4133         rc = is_bnxt_in_error(bp);
4134         if (rc)
4135                 return rc;
4136
4137         PMD_DRV_LOG(INFO, PCI_PRI_FMT "\n",
4138                     bp->pdev->addr.domain, bp->pdev->addr.bus,
4139                     bp->pdev->addr.devid, bp->pdev->addr.function);
4140
4141         rc = bnxt_hwrm_nvm_get_dir_info(bp, &dir_entries, &entry_length);
4142         if (rc != 0)
4143                 return rc;
4144
4145         return dir_entries * entry_length;
4146 }
4147
4148 static int
4149 bnxt_get_eeprom_op(struct rte_eth_dev *dev,
4150                 struct rte_dev_eeprom_info *in_eeprom)
4151 {
4152         struct bnxt *bp = dev->data->dev_private;
4153         uint32_t index;
4154         uint32_t offset;
4155         int rc;
4156
4157         rc = is_bnxt_in_error(bp);
4158         if (rc)
4159                 return rc;
4160
4161         PMD_DRV_LOG(INFO, PCI_PRI_FMT " in_eeprom->offset = %d len = %d\n",
4162                     bp->pdev->addr.domain, bp->pdev->addr.bus,
4163                     bp->pdev->addr.devid, bp->pdev->addr.function,
4164                     in_eeprom->offset, in_eeprom->length);
4165
4166         if (in_eeprom->offset == 0) /* special offset value to get directory */
4167                 return bnxt_get_nvram_directory(bp, in_eeprom->length,
4168                                                 in_eeprom->data);
4169
4170         index = in_eeprom->offset >> 24;
4171         offset = in_eeprom->offset & 0xffffff;
4172
4173         if (index != 0)
4174                 return bnxt_hwrm_get_nvram_item(bp, index - 1, offset,
4175                                            in_eeprom->length, in_eeprom->data);
4176
4177         return 0;
4178 }
4179
4180 static bool bnxt_dir_type_is_ape_bin_format(uint16_t dir_type)
4181 {
4182         switch (dir_type) {
4183         case BNX_DIR_TYPE_CHIMP_PATCH:
4184         case BNX_DIR_TYPE_BOOTCODE:
4185         case BNX_DIR_TYPE_BOOTCODE_2:
4186         case BNX_DIR_TYPE_APE_FW:
4187         case BNX_DIR_TYPE_APE_PATCH:
4188         case BNX_DIR_TYPE_KONG_FW:
4189         case BNX_DIR_TYPE_KONG_PATCH:
4190         case BNX_DIR_TYPE_BONO_FW:
4191         case BNX_DIR_TYPE_BONO_PATCH:
4192                 /* FALLTHROUGH */
4193                 return true;
4194         }
4195
4196         return false;
4197 }
4198
4199 static bool bnxt_dir_type_is_other_exec_format(uint16_t dir_type)
4200 {
4201         switch (dir_type) {
4202         case BNX_DIR_TYPE_AVS:
4203         case BNX_DIR_TYPE_EXP_ROM_MBA:
4204         case BNX_DIR_TYPE_PCIE:
4205         case BNX_DIR_TYPE_TSCF_UCODE:
4206         case BNX_DIR_TYPE_EXT_PHY:
4207         case BNX_DIR_TYPE_CCM:
4208         case BNX_DIR_TYPE_ISCSI_BOOT:
4209         case BNX_DIR_TYPE_ISCSI_BOOT_IPV6:
4210         case BNX_DIR_TYPE_ISCSI_BOOT_IPV4N6:
4211                 /* FALLTHROUGH */
4212                 return true;
4213         }
4214
4215         return false;
4216 }
4217
4218 static bool bnxt_dir_type_is_executable(uint16_t dir_type)
4219 {
4220         return bnxt_dir_type_is_ape_bin_format(dir_type) ||
4221                 bnxt_dir_type_is_other_exec_format(dir_type);
4222 }
4223
4224 static int
4225 bnxt_set_eeprom_op(struct rte_eth_dev *dev,
4226                 struct rte_dev_eeprom_info *in_eeprom)
4227 {
4228         struct bnxt *bp = dev->data->dev_private;
4229         uint8_t index, dir_op;
4230         uint16_t type, ext, ordinal, attr;
4231         int rc;
4232
4233         rc = is_bnxt_in_error(bp);
4234         if (rc)
4235                 return rc;
4236
4237         PMD_DRV_LOG(INFO, PCI_PRI_FMT " in_eeprom->offset = %d len = %d\n",
4238                     bp->pdev->addr.domain, bp->pdev->addr.bus,
4239                     bp->pdev->addr.devid, bp->pdev->addr.function,
4240                     in_eeprom->offset, in_eeprom->length);
4241
4242         if (!BNXT_PF(bp)) {
4243                 PMD_DRV_LOG(ERR, "NVM write not supported from a VF\n");
4244                 return -EINVAL;
4245         }
4246
4247         type = in_eeprom->magic >> 16;
4248
4249         if (type == 0xffff) { /* special value for directory operations */
4250                 index = in_eeprom->magic & 0xff;
4251                 dir_op = in_eeprom->magic >> 8;
4252                 if (index == 0)
4253                         return -EINVAL;
4254                 switch (dir_op) {
4255                 case 0x0e: /* erase */
4256                         if (in_eeprom->offset != ~in_eeprom->magic)
4257                                 return -EINVAL;
4258                         return bnxt_hwrm_erase_nvram_directory(bp, index - 1);
4259                 default:
4260                         return -EINVAL;
4261                 }
4262         }
4263
4264         /* Create or re-write an NVM item: */
4265         if (bnxt_dir_type_is_executable(type) == true)
4266                 return -EOPNOTSUPP;
4267         ext = in_eeprom->magic & 0xffff;
4268         ordinal = in_eeprom->offset >> 16;
4269         attr = in_eeprom->offset & 0xffff;
4270
4271         return bnxt_hwrm_flash_nvram(bp, type, ordinal, ext, attr,
4272                                      in_eeprom->data, in_eeprom->length);
4273 }
4274
4275 /*
4276  * Initialization
4277  */
4278
4279 static const struct eth_dev_ops bnxt_dev_ops = {
4280         .dev_infos_get = bnxt_dev_info_get_op,
4281         .dev_close = bnxt_dev_close_op,
4282         .dev_configure = bnxt_dev_configure_op,
4283         .dev_start = bnxt_dev_start_op,
4284         .dev_stop = bnxt_dev_stop_op,
4285         .dev_set_link_up = bnxt_dev_set_link_up_op,
4286         .dev_set_link_down = bnxt_dev_set_link_down_op,
4287         .stats_get = bnxt_stats_get_op,
4288         .stats_reset = bnxt_stats_reset_op,
4289         .rx_queue_setup = bnxt_rx_queue_setup_op,
4290         .rx_queue_release = bnxt_rx_queue_release_op,
4291         .tx_queue_setup = bnxt_tx_queue_setup_op,
4292         .tx_queue_release = bnxt_tx_queue_release_op,
4293         .rx_queue_intr_enable = bnxt_rx_queue_intr_enable_op,
4294         .rx_queue_intr_disable = bnxt_rx_queue_intr_disable_op,
4295         .reta_update = bnxt_reta_update_op,
4296         .reta_query = bnxt_reta_query_op,
4297         .rss_hash_update = bnxt_rss_hash_update_op,
4298         .rss_hash_conf_get = bnxt_rss_hash_conf_get_op,
4299         .link_update = bnxt_link_update_op,
4300         .promiscuous_enable = bnxt_promiscuous_enable_op,
4301         .promiscuous_disable = bnxt_promiscuous_disable_op,
4302         .allmulticast_enable = bnxt_allmulticast_enable_op,
4303         .allmulticast_disable = bnxt_allmulticast_disable_op,
4304         .mac_addr_add = bnxt_mac_addr_add_op,
4305         .mac_addr_remove = bnxt_mac_addr_remove_op,
4306         .flow_ctrl_get = bnxt_flow_ctrl_get_op,
4307         .flow_ctrl_set = bnxt_flow_ctrl_set_op,
4308         .udp_tunnel_port_add  = bnxt_udp_tunnel_port_add_op,
4309         .udp_tunnel_port_del  = bnxt_udp_tunnel_port_del_op,
4310         .vlan_filter_set = bnxt_vlan_filter_set_op,
4311         .vlan_offload_set = bnxt_vlan_offload_set_op,
4312         .vlan_tpid_set = bnxt_vlan_tpid_set_op,
4313         .vlan_pvid_set = bnxt_vlan_pvid_set_op,
4314         .mtu_set = bnxt_mtu_set_op,
4315         .mac_addr_set = bnxt_set_default_mac_addr_op,
4316         .xstats_get = bnxt_dev_xstats_get_op,
4317         .xstats_get_names = bnxt_dev_xstats_get_names_op,
4318         .xstats_reset = bnxt_dev_xstats_reset_op,
4319         .fw_version_get = bnxt_fw_version_get,
4320         .set_mc_addr_list = bnxt_dev_set_mc_addr_list_op,
4321         .rxq_info_get = bnxt_rxq_info_get_op,
4322         .txq_info_get = bnxt_txq_info_get_op,
4323         .rx_burst_mode_get = bnxt_rx_burst_mode_get,
4324         .tx_burst_mode_get = bnxt_tx_burst_mode_get,
4325         .dev_led_on = bnxt_dev_led_on_op,
4326         .dev_led_off = bnxt_dev_led_off_op,
4327         .xstats_get_by_id = bnxt_dev_xstats_get_by_id_op,
4328         .xstats_get_names_by_id = bnxt_dev_xstats_get_names_by_id_op,
4329         .rx_queue_start = bnxt_rx_queue_start,
4330         .rx_queue_stop = bnxt_rx_queue_stop,
4331         .tx_queue_start = bnxt_tx_queue_start,
4332         .tx_queue_stop = bnxt_tx_queue_stop,
4333         .filter_ctrl = bnxt_filter_ctrl_op,
4334         .dev_supported_ptypes_get = bnxt_dev_supported_ptypes_get_op,
4335         .get_eeprom_length    = bnxt_get_eeprom_length_op,
4336         .get_eeprom           = bnxt_get_eeprom_op,
4337         .set_eeprom           = bnxt_set_eeprom_op,
4338         .timesync_enable      = bnxt_timesync_enable,
4339         .timesync_disable     = bnxt_timesync_disable,
4340         .timesync_read_time   = bnxt_timesync_read_time,
4341         .timesync_write_time   = bnxt_timesync_write_time,
4342         .timesync_adjust_time = bnxt_timesync_adjust_time,
4343         .timesync_read_rx_timestamp = bnxt_timesync_read_rx_timestamp,
4344         .timesync_read_tx_timestamp = bnxt_timesync_read_tx_timestamp,
4345 };
4346
4347 static uint32_t bnxt_map_reset_regs(struct bnxt *bp, uint32_t reg)
4348 {
4349         uint32_t offset;
4350
4351         /* Only pre-map the reset GRC registers using window 3 */
4352         rte_write32(reg & 0xfffff000, (uint8_t *)bp->bar0 +
4353                     BNXT_GRCPF_REG_WINDOW_BASE_OUT + 8);
4354
4355         offset = BNXT_GRCP_WINDOW_3_BASE + (reg & 0xffc);
4356
4357         return offset;
4358 }
4359
4360 int bnxt_map_fw_health_status_regs(struct bnxt *bp)
4361 {
4362         struct bnxt_error_recovery_info *info = bp->recovery_info;
4363         uint32_t reg_base = 0xffffffff;
4364         int i;
4365
4366         /* Only pre-map the monitoring GRC registers using window 2 */
4367         for (i = 0; i < BNXT_FW_STATUS_REG_CNT; i++) {
4368                 uint32_t reg = info->status_regs[i];
4369
4370                 if (BNXT_FW_STATUS_REG_TYPE(reg) != BNXT_FW_STATUS_REG_TYPE_GRC)
4371                         continue;
4372
4373                 if (reg_base == 0xffffffff)
4374                         reg_base = reg & 0xfffff000;
4375                 if ((reg & 0xfffff000) != reg_base)
4376                         return -ERANGE;
4377
4378                 /* Use mask 0xffc as the Lower 2 bits indicates
4379                  * address space location
4380                  */
4381                 info->mapped_status_regs[i] = BNXT_GRCP_WINDOW_2_BASE +
4382                                                 (reg & 0xffc);
4383         }
4384
4385         if (reg_base == 0xffffffff)
4386                 return 0;
4387
4388         rte_write32(reg_base, (uint8_t *)bp->bar0 +
4389                     BNXT_GRCPF_REG_WINDOW_BASE_OUT + 4);
4390
4391         return 0;
4392 }
4393
4394 static void bnxt_write_fw_reset_reg(struct bnxt *bp, uint32_t index)
4395 {
4396         struct bnxt_error_recovery_info *info = bp->recovery_info;
4397         uint32_t delay = info->delay_after_reset[index];
4398         uint32_t val = info->reset_reg_val[index];
4399         uint32_t reg = info->reset_reg[index];
4400         uint32_t type, offset;
4401
4402         type = BNXT_FW_STATUS_REG_TYPE(reg);
4403         offset = BNXT_FW_STATUS_REG_OFF(reg);
4404
4405         switch (type) {
4406         case BNXT_FW_STATUS_REG_TYPE_CFG:
4407                 rte_pci_write_config(bp->pdev, &val, sizeof(val), offset);
4408                 break;
4409         case BNXT_FW_STATUS_REG_TYPE_GRC:
4410                 offset = bnxt_map_reset_regs(bp, offset);
4411                 rte_write32(val, (uint8_t *)bp->bar0 + offset);
4412                 break;
4413         case BNXT_FW_STATUS_REG_TYPE_BAR0:
4414                 rte_write32(val, (uint8_t *)bp->bar0 + offset);
4415                 break;
4416         }
4417         /* wait on a specific interval of time until core reset is complete */
4418         if (delay)
4419                 rte_delay_ms(delay);
4420 }
4421
4422 static void bnxt_dev_cleanup(struct bnxt *bp)
4423 {
4424         bp->eth_dev->data->dev_link.link_status = 0;
4425         bp->link_info->link_up = 0;
4426         if (bp->eth_dev->data->dev_started)
4427                 bnxt_dev_stop_op(bp->eth_dev);
4428
4429         bnxt_uninit_resources(bp, true);
4430 }
4431
4432 static int bnxt_restore_vlan_filters(struct bnxt *bp)
4433 {
4434         struct rte_eth_dev *dev = bp->eth_dev;
4435         struct rte_vlan_filter_conf *vfc;
4436         int vidx, vbit, rc;
4437         uint16_t vlan_id;
4438
4439         for (vlan_id = 1; vlan_id <= RTE_ETHER_MAX_VLAN_ID; vlan_id++) {
4440                 vfc = &dev->data->vlan_filter_conf;
4441                 vidx = vlan_id / 64;
4442                 vbit = vlan_id % 64;
4443
4444                 /* Each bit corresponds to a VLAN id */
4445                 if (vfc->ids[vidx] & (UINT64_C(1) << vbit)) {
4446                         rc = bnxt_add_vlan_filter(bp, vlan_id);
4447                         if (rc)
4448                                 return rc;
4449                 }
4450         }
4451
4452         return 0;
4453 }
4454
4455 static int bnxt_restore_mac_filters(struct bnxt *bp)
4456 {
4457         struct rte_eth_dev *dev = bp->eth_dev;
4458         struct rte_eth_dev_info dev_info;
4459         struct rte_ether_addr *addr;
4460         uint64_t pool_mask;
4461         uint32_t pool = 0;
4462         uint16_t i;
4463         int rc;
4464
4465         if (BNXT_VF(bp) && !BNXT_VF_IS_TRUSTED(bp))
4466                 return 0;
4467
4468         rc = bnxt_dev_info_get_op(dev, &dev_info);
4469         if (rc)
4470                 return rc;
4471
4472         /* replay MAC address configuration */
4473         for (i = 1; i < dev_info.max_mac_addrs; i++) {
4474                 addr = &dev->data->mac_addrs[i];
4475
4476                 /* skip zero address */
4477                 if (rte_is_zero_ether_addr(addr))
4478                         continue;
4479
4480                 pool = 0;
4481                 pool_mask = dev->data->mac_pool_sel[i];
4482
4483                 do {
4484                         if (pool_mask & 1ULL) {
4485                                 rc = bnxt_mac_addr_add_op(dev, addr, i, pool);
4486                                 if (rc)
4487                                         return rc;
4488                         }
4489                         pool_mask >>= 1;
4490                         pool++;
4491                 } while (pool_mask);
4492         }
4493
4494         return 0;
4495 }
4496
4497 static int bnxt_restore_filters(struct bnxt *bp)
4498 {
4499         struct rte_eth_dev *dev = bp->eth_dev;
4500         int ret = 0;
4501
4502         if (dev->data->all_multicast) {
4503                 ret = bnxt_allmulticast_enable_op(dev);
4504                 if (ret)
4505                         return ret;
4506         }
4507         if (dev->data->promiscuous) {
4508                 ret = bnxt_promiscuous_enable_op(dev);
4509                 if (ret)
4510                         return ret;
4511         }
4512
4513         ret = bnxt_restore_mac_filters(bp);
4514         if (ret)
4515                 return ret;
4516
4517         ret = bnxt_restore_vlan_filters(bp);
4518         /* TODO restore other filters as well */
4519         return ret;
4520 }
4521
4522 static void bnxt_dev_recover(void *arg)
4523 {
4524         struct bnxt *bp = arg;
4525         int timeout = bp->fw_reset_max_msecs;
4526         int rc = 0;
4527
4528         /* Clear Error flag so that device re-init should happen */
4529         bp->flags &= ~BNXT_FLAG_FATAL_ERROR;
4530
4531         do {
4532                 rc = bnxt_hwrm_ver_get(bp, SHORT_HWRM_CMD_TIMEOUT);
4533                 if (rc == 0)
4534                         break;
4535                 rte_delay_ms(BNXT_FW_READY_WAIT_INTERVAL);
4536                 timeout -= BNXT_FW_READY_WAIT_INTERVAL;
4537         } while (rc && timeout);
4538
4539         if (rc) {
4540                 PMD_DRV_LOG(ERR, "FW is not Ready after reset\n");
4541                 goto err;
4542         }
4543
4544         rc = bnxt_init_resources(bp, true);
4545         if (rc) {
4546                 PMD_DRV_LOG(ERR,
4547                             "Failed to initialize resources after reset\n");
4548                 goto err;
4549         }
4550         /* clear reset flag as the device is initialized now */
4551         bp->flags &= ~BNXT_FLAG_FW_RESET;
4552
4553         rc = bnxt_dev_start_op(bp->eth_dev);
4554         if (rc) {
4555                 PMD_DRV_LOG(ERR, "Failed to start port after reset\n");
4556                 goto err_start;
4557         }
4558
4559         rc = bnxt_restore_filters(bp);
4560         if (rc)
4561                 goto err_start;
4562
4563         PMD_DRV_LOG(INFO, "Recovered from FW reset\n");
4564         return;
4565 err_start:
4566         bnxt_dev_stop_op(bp->eth_dev);
4567 err:
4568         bp->flags |= BNXT_FLAG_FATAL_ERROR;
4569         bnxt_uninit_resources(bp, false);
4570         PMD_DRV_LOG(ERR, "Failed to recover from FW reset\n");
4571 }
4572
4573 void bnxt_dev_reset_and_resume(void *arg)
4574 {
4575         struct bnxt *bp = arg;
4576         int rc;
4577
4578         bnxt_dev_cleanup(bp);
4579
4580         bnxt_wait_for_device_shutdown(bp);
4581
4582         rc = rte_eal_alarm_set(US_PER_MS * bp->fw_reset_min_msecs,
4583                                bnxt_dev_recover, (void *)bp);
4584         if (rc)
4585                 PMD_DRV_LOG(ERR, "Error setting recovery alarm");
4586 }
4587
4588 uint32_t bnxt_read_fw_status_reg(struct bnxt *bp, uint32_t index)
4589 {
4590         struct bnxt_error_recovery_info *info = bp->recovery_info;
4591         uint32_t reg = info->status_regs[index];
4592         uint32_t type, offset, val = 0;
4593
4594         type = BNXT_FW_STATUS_REG_TYPE(reg);
4595         offset = BNXT_FW_STATUS_REG_OFF(reg);
4596
4597         switch (type) {
4598         case BNXT_FW_STATUS_REG_TYPE_CFG:
4599                 rte_pci_read_config(bp->pdev, &val, sizeof(val), offset);
4600                 break;
4601         case BNXT_FW_STATUS_REG_TYPE_GRC:
4602                 offset = info->mapped_status_regs[index];
4603                 /* FALLTHROUGH */
4604         case BNXT_FW_STATUS_REG_TYPE_BAR0:
4605                 val = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
4606                                        offset));
4607                 break;
4608         }
4609
4610         return val;
4611 }
4612
4613 static int bnxt_fw_reset_all(struct bnxt *bp)
4614 {
4615         struct bnxt_error_recovery_info *info = bp->recovery_info;
4616         uint32_t i;
4617         int rc = 0;
4618
4619         if (info->flags & BNXT_FLAG_ERROR_RECOVERY_HOST) {
4620                 /* Reset through master function driver */
4621                 for (i = 0; i < info->reg_array_cnt; i++)
4622                         bnxt_write_fw_reset_reg(bp, i);
4623                 /* Wait for time specified by FW after triggering reset */
4624                 rte_delay_ms(info->master_func_wait_period_after_reset);
4625         } else if (info->flags & BNXT_FLAG_ERROR_RECOVERY_CO_CPU) {
4626                 /* Reset with the help of Kong processor */
4627                 rc = bnxt_hwrm_fw_reset(bp);
4628                 if (rc)
4629                         PMD_DRV_LOG(ERR, "Failed to reset FW\n");
4630         }
4631
4632         return rc;
4633 }
4634
4635 static void bnxt_fw_reset_cb(void *arg)
4636 {
4637         struct bnxt *bp = arg;
4638         struct bnxt_error_recovery_info *info = bp->recovery_info;
4639         int rc = 0;
4640
4641         /* Only Master function can do FW reset */
4642         if (bnxt_is_master_func(bp) &&
4643             bnxt_is_recovery_enabled(bp)) {
4644                 rc = bnxt_fw_reset_all(bp);
4645                 if (rc) {
4646                         PMD_DRV_LOG(ERR, "Adapter recovery failed\n");
4647                         return;
4648                 }
4649         }
4650
4651         /* if recovery method is ERROR_RECOVERY_CO_CPU, KONG will send
4652          * EXCEPTION_FATAL_ASYNC event to all the functions
4653          * (including MASTER FUNC). After receiving this Async, all the active
4654          * drivers should treat this case as FW initiated recovery
4655          */
4656         if (info->flags & BNXT_FLAG_ERROR_RECOVERY_HOST) {
4657                 bp->fw_reset_min_msecs = BNXT_MIN_FW_READY_TIMEOUT;
4658                 bp->fw_reset_max_msecs = BNXT_MAX_FW_RESET_TIMEOUT;
4659
4660                 /* To recover from error */
4661                 rte_eal_alarm_set(US_PER_MS, bnxt_dev_reset_and_resume,
4662                                   (void *)bp);
4663         }
4664 }
4665
4666 /* Driver should poll FW heartbeat, reset_counter with the frequency
4667  * advertised by FW in HWRM_ERROR_RECOVERY_QCFG.
4668  * When the driver detects heartbeat stop or change in reset_counter,
4669  * it has to trigger a reset to recover from the error condition.
4670  * A “master PF” is the function who will have the privilege to
4671  * initiate the chimp reset. The master PF will be elected by the
4672  * firmware and will be notified through async message.
4673  */
4674 static void bnxt_check_fw_health(void *arg)
4675 {
4676         struct bnxt *bp = arg;
4677         struct bnxt_error_recovery_info *info = bp->recovery_info;
4678         uint32_t val = 0, wait_msec;
4679
4680         if (!info || !bnxt_is_recovery_enabled(bp) ||
4681             is_bnxt_in_error(bp))
4682                 return;
4683
4684         val = bnxt_read_fw_status_reg(bp, BNXT_FW_HEARTBEAT_CNT_REG);
4685         if (val == info->last_heart_beat)
4686                 goto reset;
4687
4688         info->last_heart_beat = val;
4689
4690         val = bnxt_read_fw_status_reg(bp, BNXT_FW_RECOVERY_CNT_REG);
4691         if (val != info->last_reset_counter)
4692                 goto reset;
4693
4694         info->last_reset_counter = val;
4695
4696         rte_eal_alarm_set(US_PER_MS * info->driver_polling_freq,
4697                           bnxt_check_fw_health, (void *)bp);
4698
4699         return;
4700 reset:
4701         /* Stop DMA to/from device */
4702         bp->flags |= BNXT_FLAG_FATAL_ERROR;
4703         bp->flags |= BNXT_FLAG_FW_RESET;
4704
4705         PMD_DRV_LOG(ERR, "Detected FW dead condition\n");
4706
4707         if (bnxt_is_master_func(bp))
4708                 wait_msec = info->master_func_wait_period;
4709         else
4710                 wait_msec = info->normal_func_wait_period;
4711
4712         rte_eal_alarm_set(US_PER_MS * wait_msec,
4713                           bnxt_fw_reset_cb, (void *)bp);
4714 }
4715
4716 void bnxt_schedule_fw_health_check(struct bnxt *bp)
4717 {
4718         uint32_t polling_freq;
4719
4720         pthread_mutex_lock(&bp->health_check_lock);
4721
4722         if (!bnxt_is_recovery_enabled(bp))
4723                 goto done;
4724
4725         if (bp->flags & BNXT_FLAG_FW_HEALTH_CHECK_SCHEDULED)
4726                 goto done;
4727
4728         polling_freq = bp->recovery_info->driver_polling_freq;
4729
4730         rte_eal_alarm_set(US_PER_MS * polling_freq,
4731                           bnxt_check_fw_health, (void *)bp);
4732         bp->flags |= BNXT_FLAG_FW_HEALTH_CHECK_SCHEDULED;
4733
4734 done:
4735         pthread_mutex_unlock(&bp->health_check_lock);
4736 }
4737
4738 static void bnxt_cancel_fw_health_check(struct bnxt *bp)
4739 {
4740         if (!bnxt_is_recovery_enabled(bp))
4741                 return;
4742
4743         rte_eal_alarm_cancel(bnxt_check_fw_health, (void *)bp);
4744         bp->flags &= ~BNXT_FLAG_FW_HEALTH_CHECK_SCHEDULED;
4745 }
4746
4747 static bool bnxt_vf_pciid(uint16_t device_id)
4748 {
4749         switch (device_id) {
4750         case BROADCOM_DEV_ID_57304_VF:
4751         case BROADCOM_DEV_ID_57406_VF:
4752         case BROADCOM_DEV_ID_5731X_VF:
4753         case BROADCOM_DEV_ID_5741X_VF:
4754         case BROADCOM_DEV_ID_57414_VF:
4755         case BROADCOM_DEV_ID_STRATUS_NIC_VF1:
4756         case BROADCOM_DEV_ID_STRATUS_NIC_VF2:
4757         case BROADCOM_DEV_ID_58802_VF:
4758         case BROADCOM_DEV_ID_57500_VF1:
4759         case BROADCOM_DEV_ID_57500_VF2:
4760                 /* FALLTHROUGH */
4761                 return true;
4762         default:
4763                 return false;
4764         }
4765 }
4766
4767 static bool bnxt_thor_device(uint16_t device_id)
4768 {
4769         switch (device_id) {
4770         case BROADCOM_DEV_ID_57508:
4771         case BROADCOM_DEV_ID_57504:
4772         case BROADCOM_DEV_ID_57502:
4773         case BROADCOM_DEV_ID_57508_MF1:
4774         case BROADCOM_DEV_ID_57504_MF1:
4775         case BROADCOM_DEV_ID_57502_MF1:
4776         case BROADCOM_DEV_ID_57508_MF2:
4777         case BROADCOM_DEV_ID_57504_MF2:
4778         case BROADCOM_DEV_ID_57502_MF2:
4779         case BROADCOM_DEV_ID_57500_VF1:
4780         case BROADCOM_DEV_ID_57500_VF2:
4781                 /* FALLTHROUGH */
4782                 return true;
4783         default:
4784                 return false;
4785         }
4786 }
4787
4788 bool bnxt_stratus_device(struct bnxt *bp)
4789 {
4790         uint16_t device_id = bp->pdev->id.device_id;
4791
4792         switch (device_id) {
4793         case BROADCOM_DEV_ID_STRATUS_NIC:
4794         case BROADCOM_DEV_ID_STRATUS_NIC_VF1:
4795         case BROADCOM_DEV_ID_STRATUS_NIC_VF2:
4796                 /* FALLTHROUGH */
4797                 return true;
4798         default:
4799                 return false;
4800         }
4801 }
4802
4803 static int bnxt_init_board(struct rte_eth_dev *eth_dev)
4804 {
4805         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
4806         struct bnxt *bp = eth_dev->data->dev_private;
4807
4808         /* enable device (incl. PCI PM wakeup), and bus-mastering */
4809         bp->bar0 = (void *)pci_dev->mem_resource[0].addr;
4810         bp->doorbell_base = (void *)pci_dev->mem_resource[2].addr;
4811         if (!bp->bar0 || !bp->doorbell_base) {
4812                 PMD_DRV_LOG(ERR, "Unable to access Hardware\n");
4813                 return -ENODEV;
4814         }
4815
4816         bp->eth_dev = eth_dev;
4817         bp->pdev = pci_dev;
4818
4819         return 0;
4820 }
4821
4822 static int bnxt_alloc_ctx_mem_blk(struct bnxt *bp,
4823                                   struct bnxt_ctx_pg_info *ctx_pg,
4824                                   uint32_t mem_size,
4825                                   const char *suffix,
4826                                   uint16_t idx)
4827 {
4828         struct bnxt_ring_mem_info *rmem = &ctx_pg->ring_mem;
4829         const struct rte_memzone *mz = NULL;
4830         char mz_name[RTE_MEMZONE_NAMESIZE];
4831         rte_iova_t mz_phys_addr;
4832         uint64_t valid_bits = 0;
4833         uint32_t sz;
4834         int i;
4835
4836         if (!mem_size)
4837                 return 0;
4838
4839         rmem->nr_pages = RTE_ALIGN_MUL_CEIL(mem_size, BNXT_PAGE_SIZE) /
4840                          BNXT_PAGE_SIZE;
4841         rmem->page_size = BNXT_PAGE_SIZE;
4842         rmem->pg_arr = ctx_pg->ctx_pg_arr;
4843         rmem->dma_arr = ctx_pg->ctx_dma_arr;
4844         rmem->flags = BNXT_RMEM_VALID_PTE_FLAG;
4845
4846         valid_bits = PTU_PTE_VALID;
4847
4848         if (rmem->nr_pages > 1) {
4849                 snprintf(mz_name, RTE_MEMZONE_NAMESIZE,
4850                          "bnxt_ctx_pg_tbl%s_%x_%d",
4851                          suffix, idx, bp->eth_dev->data->port_id);
4852                 mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0;
4853                 mz = rte_memzone_lookup(mz_name);
4854                 if (!mz) {
4855                         mz = rte_memzone_reserve_aligned(mz_name,
4856                                                 rmem->nr_pages * 8,
4857                                                 SOCKET_ID_ANY,
4858                                                 RTE_MEMZONE_2MB |
4859                                                 RTE_MEMZONE_SIZE_HINT_ONLY |
4860                                                 RTE_MEMZONE_IOVA_CONTIG,
4861                                                 BNXT_PAGE_SIZE);
4862                         if (mz == NULL)
4863                                 return -ENOMEM;
4864                 }
4865
4866                 memset(mz->addr, 0, mz->len);
4867                 mz_phys_addr = mz->iova;
4868
4869                 rmem->pg_tbl = mz->addr;
4870                 rmem->pg_tbl_map = mz_phys_addr;
4871                 rmem->pg_tbl_mz = mz;
4872         }
4873
4874         snprintf(mz_name, RTE_MEMZONE_NAMESIZE, "bnxt_ctx_%s_%x_%d",
4875                  suffix, idx, bp->eth_dev->data->port_id);
4876         mz = rte_memzone_lookup(mz_name);
4877         if (!mz) {
4878                 mz = rte_memzone_reserve_aligned(mz_name,
4879                                                  mem_size,
4880                                                  SOCKET_ID_ANY,
4881                                                  RTE_MEMZONE_1GB |
4882                                                  RTE_MEMZONE_SIZE_HINT_ONLY |
4883                                                  RTE_MEMZONE_IOVA_CONTIG,
4884                                                  BNXT_PAGE_SIZE);
4885                 if (mz == NULL)
4886                         return -ENOMEM;
4887         }
4888
4889         memset(mz->addr, 0, mz->len);
4890         mz_phys_addr = mz->iova;
4891
4892         for (sz = 0, i = 0; sz < mem_size; sz += BNXT_PAGE_SIZE, i++) {
4893                 rmem->pg_arr[i] = ((char *)mz->addr) + sz;
4894                 rmem->dma_arr[i] = mz_phys_addr + sz;
4895
4896                 if (rmem->nr_pages > 1) {
4897                         if (i == rmem->nr_pages - 2 &&
4898                             (rmem->flags & BNXT_RMEM_RING_PTE_FLAG))
4899                                 valid_bits |= PTU_PTE_NEXT_TO_LAST;
4900                         else if (i == rmem->nr_pages - 1 &&
4901                                  (rmem->flags & BNXT_RMEM_RING_PTE_FLAG))
4902                                 valid_bits |= PTU_PTE_LAST;
4903
4904                         rmem->pg_tbl[i] = rte_cpu_to_le_64(rmem->dma_arr[i] |
4905                                                            valid_bits);
4906                 }
4907         }
4908
4909         rmem->mz = mz;
4910         if (rmem->vmem_size)
4911                 rmem->vmem = (void **)mz->addr;
4912         rmem->dma_arr[0] = mz_phys_addr;
4913         return 0;
4914 }
4915
4916 static void bnxt_free_ctx_mem(struct bnxt *bp)
4917 {
4918         int i;
4919
4920         if (!bp->ctx || !(bp->ctx->flags & BNXT_CTX_FLAG_INITED))
4921                 return;
4922
4923         bp->ctx->flags &= ~BNXT_CTX_FLAG_INITED;
4924         rte_memzone_free(bp->ctx->qp_mem.ring_mem.mz);
4925         rte_memzone_free(bp->ctx->srq_mem.ring_mem.mz);
4926         rte_memzone_free(bp->ctx->cq_mem.ring_mem.mz);
4927         rte_memzone_free(bp->ctx->vnic_mem.ring_mem.mz);
4928         rte_memzone_free(bp->ctx->stat_mem.ring_mem.mz);
4929         rte_memzone_free(bp->ctx->qp_mem.ring_mem.pg_tbl_mz);
4930         rte_memzone_free(bp->ctx->srq_mem.ring_mem.pg_tbl_mz);
4931         rte_memzone_free(bp->ctx->cq_mem.ring_mem.pg_tbl_mz);
4932         rte_memzone_free(bp->ctx->vnic_mem.ring_mem.pg_tbl_mz);
4933         rte_memzone_free(bp->ctx->stat_mem.ring_mem.pg_tbl_mz);
4934
4935         for (i = 0; i < bp->ctx->tqm_fp_rings_count + 1; i++) {
4936                 if (bp->ctx->tqm_mem[i])
4937                         rte_memzone_free(bp->ctx->tqm_mem[i]->ring_mem.mz);
4938         }
4939
4940         rte_free(bp->ctx);
4941         bp->ctx = NULL;
4942 }
4943
4944 #define bnxt_roundup(x, y)   ((((x) + ((y) - 1)) / (y)) * (y))
4945
4946 #define min_t(type, x, y) ({                    \
4947         type __min1 = (x);                      \
4948         type __min2 = (y);                      \
4949         __min1 < __min2 ? __min1 : __min2; })
4950
4951 #define max_t(type, x, y) ({                    \
4952         type __max1 = (x);                      \
4953         type __max2 = (y);                      \
4954         __max1 > __max2 ? __max1 : __max2; })
4955
4956 #define clamp_t(type, _x, min, max)     min_t(type, max_t(type, _x, min), max)
4957
4958 int bnxt_alloc_ctx_mem(struct bnxt *bp)
4959 {
4960         struct bnxt_ctx_pg_info *ctx_pg;
4961         struct bnxt_ctx_mem_info *ctx;
4962         uint32_t mem_size, ena, entries;
4963         uint32_t entries_sp, min;
4964         int i, rc;
4965
4966         rc = bnxt_hwrm_func_backing_store_qcaps(bp);
4967         if (rc) {
4968                 PMD_DRV_LOG(ERR, "Query context mem capability failed\n");
4969                 return rc;
4970         }
4971         ctx = bp->ctx;
4972         if (!ctx || (ctx->flags & BNXT_CTX_FLAG_INITED))
4973                 return 0;
4974
4975         ctx_pg = &ctx->qp_mem;
4976         ctx_pg->entries = ctx->qp_min_qp1_entries + ctx->qp_max_l2_entries;
4977         mem_size = ctx->qp_entry_size * ctx_pg->entries;
4978         rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "qp_mem", 0);
4979         if (rc)
4980                 return rc;
4981
4982         ctx_pg = &ctx->srq_mem;
4983         ctx_pg->entries = ctx->srq_max_l2_entries;
4984         mem_size = ctx->srq_entry_size * ctx_pg->entries;
4985         rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "srq_mem", 0);
4986         if (rc)
4987                 return rc;
4988
4989         ctx_pg = &ctx->cq_mem;
4990         ctx_pg->entries = ctx->cq_max_l2_entries;
4991         mem_size = ctx->cq_entry_size * ctx_pg->entries;
4992         rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "cq_mem", 0);
4993         if (rc)
4994                 return rc;
4995
4996         ctx_pg = &ctx->vnic_mem;
4997         ctx_pg->entries = ctx->vnic_max_vnic_entries +
4998                 ctx->vnic_max_ring_table_entries;
4999         mem_size = ctx->vnic_entry_size * ctx_pg->entries;
5000         rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "vnic_mem", 0);
5001         if (rc)
5002                 return rc;
5003
5004         ctx_pg = &ctx->stat_mem;
5005         ctx_pg->entries = ctx->stat_max_entries;
5006         mem_size = ctx->stat_entry_size * ctx_pg->entries;
5007         rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "stat_mem", 0);
5008         if (rc)
5009                 return rc;
5010
5011         min = ctx->tqm_min_entries_per_ring;
5012
5013         entries_sp = ctx->qp_max_l2_entries +
5014                      ctx->vnic_max_vnic_entries +
5015                      2 * ctx->qp_min_qp1_entries + min;
5016         entries_sp = bnxt_roundup(entries_sp, ctx->tqm_entries_multiple);
5017
5018         entries = ctx->qp_max_l2_entries + ctx->qp_min_qp1_entries;
5019         entries = bnxt_roundup(entries, ctx->tqm_entries_multiple);
5020         entries = clamp_t(uint32_t, entries, min,
5021                           ctx->tqm_max_entries_per_ring);
5022         for (i = 0, ena = 0; i < ctx->tqm_fp_rings_count + 1; i++) {
5023                 ctx_pg = ctx->tqm_mem[i];
5024                 ctx_pg->entries = i ? entries : entries_sp;
5025                 mem_size = ctx->tqm_entry_size * ctx_pg->entries;
5026                 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "tqm_mem", i);
5027                 if (rc)
5028                         return rc;
5029                 ena |= HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_SP << i;
5030         }
5031
5032         ena |= FUNC_BACKING_STORE_CFG_INPUT_DFLT_ENABLES;
5033         rc = bnxt_hwrm_func_backing_store_cfg(bp, ena);
5034         if (rc)
5035                 PMD_DRV_LOG(ERR,
5036                             "Failed to configure context mem: rc = %d\n", rc);
5037         else
5038                 ctx->flags |= BNXT_CTX_FLAG_INITED;
5039
5040         return rc;
5041 }
5042
5043 static int bnxt_alloc_stats_mem(struct bnxt *bp)
5044 {
5045         struct rte_pci_device *pci_dev = bp->pdev;
5046         char mz_name[RTE_MEMZONE_NAMESIZE];
5047         const struct rte_memzone *mz = NULL;
5048         uint32_t total_alloc_len;
5049         rte_iova_t mz_phys_addr;
5050
5051         if (pci_dev->id.device_id == BROADCOM_DEV_ID_NS2)
5052                 return 0;
5053
5054         snprintf(mz_name, RTE_MEMZONE_NAMESIZE,
5055                  "bnxt_" PCI_PRI_FMT "-%s", pci_dev->addr.domain,
5056                  pci_dev->addr.bus, pci_dev->addr.devid,
5057                  pci_dev->addr.function, "rx_port_stats");
5058         mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0;
5059         mz = rte_memzone_lookup(mz_name);
5060         total_alloc_len =
5061                 RTE_CACHE_LINE_ROUNDUP(sizeof(struct rx_port_stats) +
5062                                        sizeof(struct rx_port_stats_ext) + 512);
5063         if (!mz) {
5064                 mz = rte_memzone_reserve(mz_name, total_alloc_len,
5065                                          SOCKET_ID_ANY,
5066                                          RTE_MEMZONE_2MB |
5067                                          RTE_MEMZONE_SIZE_HINT_ONLY |
5068                                          RTE_MEMZONE_IOVA_CONTIG);
5069                 if (mz == NULL)
5070                         return -ENOMEM;
5071         }
5072         memset(mz->addr, 0, mz->len);
5073         mz_phys_addr = mz->iova;
5074
5075         bp->rx_mem_zone = (const void *)mz;
5076         bp->hw_rx_port_stats = mz->addr;
5077         bp->hw_rx_port_stats_map = mz_phys_addr;
5078
5079         snprintf(mz_name, RTE_MEMZONE_NAMESIZE,
5080                  "bnxt_" PCI_PRI_FMT "-%s", pci_dev->addr.domain,
5081                  pci_dev->addr.bus, pci_dev->addr.devid,
5082                  pci_dev->addr.function, "tx_port_stats");
5083         mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0;
5084         mz = rte_memzone_lookup(mz_name);
5085         total_alloc_len =
5086                 RTE_CACHE_LINE_ROUNDUP(sizeof(struct tx_port_stats) +
5087                                        sizeof(struct tx_port_stats_ext) + 512);
5088         if (!mz) {
5089                 mz = rte_memzone_reserve(mz_name,
5090                                          total_alloc_len,
5091                                          SOCKET_ID_ANY,
5092                                          RTE_MEMZONE_2MB |
5093                                          RTE_MEMZONE_SIZE_HINT_ONLY |
5094                                          RTE_MEMZONE_IOVA_CONTIG);
5095                 if (mz == NULL)
5096                         return -ENOMEM;
5097         }
5098         memset(mz->addr, 0, mz->len);
5099         mz_phys_addr = mz->iova;
5100
5101         bp->tx_mem_zone = (const void *)mz;
5102         bp->hw_tx_port_stats = mz->addr;
5103         bp->hw_tx_port_stats_map = mz_phys_addr;
5104         bp->flags |= BNXT_FLAG_PORT_STATS;
5105
5106         /* Display extended statistics if FW supports it */
5107         if (bp->hwrm_spec_code < HWRM_SPEC_CODE_1_8_4 ||
5108             bp->hwrm_spec_code == HWRM_SPEC_CODE_1_9_0 ||
5109             !(bp->flags & BNXT_FLAG_EXT_STATS_SUPPORTED))
5110                 return 0;
5111
5112         bp->hw_rx_port_stats_ext = (void *)
5113                 ((uint8_t *)bp->hw_rx_port_stats +
5114                  sizeof(struct rx_port_stats));
5115         bp->hw_rx_port_stats_ext_map = bp->hw_rx_port_stats_map +
5116                 sizeof(struct rx_port_stats);
5117         bp->flags |= BNXT_FLAG_EXT_RX_PORT_STATS;
5118
5119         if (bp->hwrm_spec_code < HWRM_SPEC_CODE_1_9_2 ||
5120             bp->flags & BNXT_FLAG_EXT_STATS_SUPPORTED) {
5121                 bp->hw_tx_port_stats_ext = (void *)
5122                         ((uint8_t *)bp->hw_tx_port_stats +
5123                          sizeof(struct tx_port_stats));
5124                 bp->hw_tx_port_stats_ext_map =
5125                         bp->hw_tx_port_stats_map +
5126                         sizeof(struct tx_port_stats);
5127                 bp->flags |= BNXT_FLAG_EXT_TX_PORT_STATS;
5128         }
5129
5130         return 0;
5131 }
5132
5133 static int bnxt_setup_mac_addr(struct rte_eth_dev *eth_dev)
5134 {
5135         struct bnxt *bp = eth_dev->data->dev_private;
5136         int rc = 0;
5137
5138         eth_dev->data->mac_addrs = rte_zmalloc("bnxt_mac_addr_tbl",
5139                                                RTE_ETHER_ADDR_LEN *
5140                                                bp->max_l2_ctx,
5141                                                0);
5142         if (eth_dev->data->mac_addrs == NULL) {
5143                 PMD_DRV_LOG(ERR, "Failed to alloc MAC addr tbl\n");
5144                 return -ENOMEM;
5145         }
5146
5147         if (!BNXT_HAS_DFLT_MAC_SET(bp)) {
5148                 if (BNXT_PF(bp))
5149                         return -EINVAL;
5150
5151                 /* Generate a random MAC address, if none was assigned by PF */
5152                 PMD_DRV_LOG(INFO, "VF MAC address not assigned by Host PF\n");
5153                 bnxt_eth_hw_addr_random(bp->mac_addr);
5154                 PMD_DRV_LOG(INFO,
5155                             "Assign random MAC:%02X:%02X:%02X:%02X:%02X:%02X\n",
5156                             bp->mac_addr[0], bp->mac_addr[1], bp->mac_addr[2],
5157                             bp->mac_addr[3], bp->mac_addr[4], bp->mac_addr[5]);
5158
5159                 rc = bnxt_hwrm_set_mac(bp);
5160                 if (rc)
5161                         return rc;
5162         }
5163
5164         /* Copy the permanent MAC from the FUNC_QCAPS response */
5165         memcpy(&eth_dev->data->mac_addrs[0], bp->mac_addr, RTE_ETHER_ADDR_LEN);
5166
5167         return rc;
5168 }
5169
5170 static int bnxt_restore_dflt_mac(struct bnxt *bp)
5171 {
5172         int rc = 0;
5173
5174         /* MAC is already configured in FW */
5175         if (BNXT_HAS_DFLT_MAC_SET(bp))
5176                 return 0;
5177
5178         /* Restore the old MAC configured */
5179         rc = bnxt_hwrm_set_mac(bp);
5180         if (rc)
5181                 PMD_DRV_LOG(ERR, "Failed to restore MAC address\n");
5182
5183         return rc;
5184 }
5185
5186 static void bnxt_config_vf_req_fwd(struct bnxt *bp)
5187 {
5188         if (!BNXT_PF(bp))
5189                 return;
5190
5191 #define ALLOW_FUNC(x)   \
5192         { \
5193                 uint32_t arg = (x); \
5194                 bp->pf->vf_req_fwd[((arg) >> 5)] &= \
5195                 ~rte_cpu_to_le_32(1 << ((arg) & 0x1f)); \
5196         }
5197
5198         /* Forward all requests if firmware is new enough */
5199         if (((bp->fw_ver >= ((20 << 24) | (6 << 16) | (100 << 8))) &&
5200              (bp->fw_ver < ((20 << 24) | (7 << 16)))) ||
5201             ((bp->fw_ver >= ((20 << 24) | (8 << 16))))) {
5202                 memset(bp->pf->vf_req_fwd, 0xff, sizeof(bp->pf->vf_req_fwd));
5203         } else {
5204                 PMD_DRV_LOG(WARNING,
5205                             "Firmware too old for VF mailbox functionality\n");
5206                 memset(bp->pf->vf_req_fwd, 0, sizeof(bp->pf->vf_req_fwd));
5207         }
5208
5209         /*
5210          * The following are used for driver cleanup. If we disallow these,
5211          * VF drivers can't clean up cleanly.
5212          */
5213         ALLOW_FUNC(HWRM_FUNC_DRV_UNRGTR);
5214         ALLOW_FUNC(HWRM_VNIC_FREE);
5215         ALLOW_FUNC(HWRM_RING_FREE);
5216         ALLOW_FUNC(HWRM_RING_GRP_FREE);
5217         ALLOW_FUNC(HWRM_VNIC_RSS_COS_LB_CTX_FREE);
5218         ALLOW_FUNC(HWRM_CFA_L2_FILTER_FREE);
5219         ALLOW_FUNC(HWRM_STAT_CTX_FREE);
5220         ALLOW_FUNC(HWRM_PORT_PHY_QCFG);
5221         ALLOW_FUNC(HWRM_VNIC_TPA_CFG);
5222 }
5223
5224 uint16_t
5225 bnxt_get_svif(uint16_t port_id, bool func_svif,
5226               enum bnxt_ulp_intf_type type)
5227 {
5228         struct rte_eth_dev *eth_dev;
5229         struct bnxt *bp;
5230
5231         eth_dev = &rte_eth_devices[port_id];
5232         if (BNXT_ETH_DEV_IS_REPRESENTOR(eth_dev)) {
5233                 struct bnxt_representor *vfr = eth_dev->data->dev_private;
5234                 if (!vfr)
5235                         return 0;
5236
5237                 if (type == BNXT_ULP_INTF_TYPE_VF_REP)
5238                         return vfr->svif;
5239
5240                 eth_dev = vfr->parent_dev;
5241         }
5242
5243         bp = eth_dev->data->dev_private;
5244
5245         return func_svif ? bp->func_svif : bp->port_svif;
5246 }
5247
5248 uint16_t
5249 bnxt_get_vnic_id(uint16_t port, enum bnxt_ulp_intf_type type)
5250 {
5251         struct rte_eth_dev *eth_dev;
5252         struct bnxt_vnic_info *vnic;
5253         struct bnxt *bp;
5254
5255         eth_dev = &rte_eth_devices[port];
5256         if (BNXT_ETH_DEV_IS_REPRESENTOR(eth_dev)) {
5257                 struct bnxt_representor *vfr = eth_dev->data->dev_private;
5258                 if (!vfr)
5259                         return 0;
5260
5261                 if (type == BNXT_ULP_INTF_TYPE_VF_REP)
5262                         return vfr->dflt_vnic_id;
5263
5264                 eth_dev = vfr->parent_dev;
5265         }
5266
5267         bp = eth_dev->data->dev_private;
5268
5269         vnic = BNXT_GET_DEFAULT_VNIC(bp);
5270
5271         return vnic->fw_vnic_id;
5272 }
5273
5274 uint16_t
5275 bnxt_get_fw_func_id(uint16_t port, enum bnxt_ulp_intf_type type)
5276 {
5277         struct rte_eth_dev *eth_dev;
5278         struct bnxt *bp;
5279
5280         eth_dev = &rte_eth_devices[port];
5281         if (BNXT_ETH_DEV_IS_REPRESENTOR(eth_dev)) {
5282                 struct bnxt_representor *vfr = eth_dev->data->dev_private;
5283                 if (!vfr)
5284                         return 0;
5285
5286                 if (type == BNXT_ULP_INTF_TYPE_VF_REP)
5287                         return vfr->fw_fid;
5288
5289                 eth_dev = vfr->parent_dev;
5290         }
5291
5292         bp = eth_dev->data->dev_private;
5293
5294         return bp->fw_fid;
5295 }
5296
5297 enum bnxt_ulp_intf_type
5298 bnxt_get_interface_type(uint16_t port)
5299 {
5300         struct rte_eth_dev *eth_dev;
5301         struct bnxt *bp;
5302
5303         eth_dev = &rte_eth_devices[port];
5304         if (BNXT_ETH_DEV_IS_REPRESENTOR(eth_dev))
5305                 return BNXT_ULP_INTF_TYPE_VF_REP;
5306
5307         bp = eth_dev->data->dev_private;
5308         if (BNXT_PF(bp))
5309                 return BNXT_ULP_INTF_TYPE_PF;
5310         else if (BNXT_VF_IS_TRUSTED(bp))
5311                 return BNXT_ULP_INTF_TYPE_TRUSTED_VF;
5312         else if (BNXT_VF(bp))
5313                 return BNXT_ULP_INTF_TYPE_VF;
5314
5315         return BNXT_ULP_INTF_TYPE_INVALID;
5316 }
5317
5318 uint16_t
5319 bnxt_get_phy_port_id(uint16_t port_id)
5320 {
5321         struct bnxt_representor *vfr;
5322         struct rte_eth_dev *eth_dev;
5323         struct bnxt *bp;
5324
5325         eth_dev = &rte_eth_devices[port_id];
5326         if (BNXT_ETH_DEV_IS_REPRESENTOR(eth_dev)) {
5327                 vfr = eth_dev->data->dev_private;
5328                 if (!vfr)
5329                         return 0;
5330
5331                 eth_dev = vfr->parent_dev;
5332         }
5333
5334         bp = eth_dev->data->dev_private;
5335
5336         return BNXT_PF(bp) ? bp->pf->port_id : bp->parent->port_id;
5337 }
5338
5339 uint16_t
5340 bnxt_get_parif(uint16_t port_id, enum bnxt_ulp_intf_type type)
5341 {
5342         struct rte_eth_dev *eth_dev;
5343         struct bnxt *bp;
5344
5345         eth_dev = &rte_eth_devices[port_id];
5346         if (BNXT_ETH_DEV_IS_REPRESENTOR(eth_dev)) {
5347                 struct bnxt_representor *vfr = eth_dev->data->dev_private;
5348                 if (!vfr)
5349                         return 0;
5350
5351                 if (type == BNXT_ULP_INTF_TYPE_VF_REP)
5352                         return vfr->fw_fid - 1;
5353
5354                 eth_dev = vfr->parent_dev;
5355         }
5356
5357         bp = eth_dev->data->dev_private;
5358
5359         return BNXT_PF(bp) ? bp->fw_fid - 1 : bp->parent->fid - 1;
5360 }
5361
5362 uint16_t
5363 bnxt_get_vport(uint16_t port_id)
5364 {
5365         return (1 << bnxt_get_phy_port_id(port_id));
5366 }
5367
5368 static void bnxt_alloc_error_recovery_info(struct bnxt *bp)
5369 {
5370         struct bnxt_error_recovery_info *info = bp->recovery_info;
5371
5372         if (info) {
5373                 if (!(bp->fw_cap & BNXT_FW_CAP_HCOMM_FW_STATUS))
5374                         memset(info, 0, sizeof(*info));
5375                 return;
5376         }
5377
5378         if (!(bp->fw_cap & BNXT_FW_CAP_ERROR_RECOVERY))
5379                 return;
5380
5381         info = rte_zmalloc("bnxt_hwrm_error_recovery_qcfg",
5382                            sizeof(*info), 0);
5383         if (!info)
5384                 bp->fw_cap &= ~BNXT_FW_CAP_ERROR_RECOVERY;
5385
5386         bp->recovery_info = info;
5387 }
5388
5389 static void bnxt_check_fw_status(struct bnxt *bp)
5390 {
5391         uint32_t fw_status;
5392
5393         if (!(bp->recovery_info &&
5394               (bp->fw_cap & BNXT_FW_CAP_HCOMM_FW_STATUS)))
5395                 return;
5396
5397         fw_status = bnxt_read_fw_status_reg(bp, BNXT_FW_STATUS_REG);
5398         if (fw_status != BNXT_FW_STATUS_HEALTHY)
5399                 PMD_DRV_LOG(ERR, "Firmware not responding, status: %#x\n",
5400                             fw_status);
5401 }
5402
5403 static int bnxt_map_hcomm_fw_status_reg(struct bnxt *bp)
5404 {
5405         struct bnxt_error_recovery_info *info = bp->recovery_info;
5406         uint32_t status_loc;
5407         uint32_t sig_ver;
5408
5409         rte_write32(HCOMM_STATUS_STRUCT_LOC, (uint8_t *)bp->bar0 +
5410                     BNXT_GRCPF_REG_WINDOW_BASE_OUT + 4);
5411         sig_ver = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
5412                                    BNXT_GRCP_WINDOW_2_BASE +
5413                                    offsetof(struct hcomm_status,
5414                                             sig_ver)));
5415         /* If the signature is absent, then FW does not support this feature */
5416         if ((sig_ver & HCOMM_STATUS_SIGNATURE_MASK) !=
5417             HCOMM_STATUS_SIGNATURE_VAL)
5418                 return 0;
5419
5420         if (!info) {
5421                 info = rte_zmalloc("bnxt_hwrm_error_recovery_qcfg",
5422                                    sizeof(*info), 0);
5423                 if (!info)
5424                         return -ENOMEM;
5425                 bp->recovery_info = info;
5426         } else {
5427                 memset(info, 0, sizeof(*info));
5428         }
5429
5430         status_loc = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
5431                                       BNXT_GRCP_WINDOW_2_BASE +
5432                                       offsetof(struct hcomm_status,
5433                                                fw_status_loc)));
5434
5435         /* Only pre-map the FW health status GRC register */
5436         if (BNXT_FW_STATUS_REG_TYPE(status_loc) != BNXT_FW_STATUS_REG_TYPE_GRC)
5437                 return 0;
5438
5439         info->status_regs[BNXT_FW_STATUS_REG] = status_loc;
5440         info->mapped_status_regs[BNXT_FW_STATUS_REG] =
5441                 BNXT_GRCP_WINDOW_2_BASE + (status_loc & BNXT_GRCP_OFFSET_MASK);
5442
5443         rte_write32((status_loc & BNXT_GRCP_BASE_MASK), (uint8_t *)bp->bar0 +
5444                     BNXT_GRCPF_REG_WINDOW_BASE_OUT + 4);
5445
5446         bp->fw_cap |= BNXT_FW_CAP_HCOMM_FW_STATUS;
5447
5448         return 0;
5449 }
5450
5451 static int bnxt_init_fw(struct bnxt *bp)
5452 {
5453         uint16_t mtu;
5454         int rc = 0;
5455
5456         bp->fw_cap = 0;
5457
5458         rc = bnxt_map_hcomm_fw_status_reg(bp);
5459         if (rc)
5460                 return rc;
5461
5462         rc = bnxt_hwrm_ver_get(bp, DFLT_HWRM_CMD_TIMEOUT);
5463         if (rc) {
5464                 bnxt_check_fw_status(bp);
5465                 return rc;
5466         }
5467
5468         rc = bnxt_hwrm_func_reset(bp);
5469         if (rc)
5470                 return -EIO;
5471
5472         rc = bnxt_hwrm_vnic_qcaps(bp);
5473         if (rc)
5474                 return rc;
5475
5476         rc = bnxt_hwrm_queue_qportcfg(bp);
5477         if (rc)
5478                 return rc;
5479
5480         /* Get the MAX capabilities for this function.
5481          * This function also allocates context memory for TQM rings and
5482          * informs the firmware about this allocated backing store memory.
5483          */
5484         rc = bnxt_hwrm_func_qcaps(bp);
5485         if (rc)
5486                 return rc;
5487
5488         rc = bnxt_hwrm_func_qcfg(bp, &mtu);
5489         if (rc)
5490                 return rc;
5491
5492         bnxt_hwrm_port_mac_qcfg(bp);
5493
5494         bnxt_hwrm_parent_pf_qcfg(bp);
5495
5496         bnxt_hwrm_port_phy_qcaps(bp);
5497
5498         bnxt_alloc_error_recovery_info(bp);
5499         /* Get the adapter error recovery support info */
5500         rc = bnxt_hwrm_error_recovery_qcfg(bp);
5501         if (rc)
5502                 bp->fw_cap &= ~BNXT_FW_CAP_ERROR_RECOVERY;
5503
5504         bnxt_hwrm_port_led_qcaps(bp);
5505
5506         return 0;
5507 }
5508
5509 static int
5510 bnxt_init_locks(struct bnxt *bp)
5511 {
5512         int err;
5513
5514         err = pthread_mutex_init(&bp->flow_lock, NULL);
5515         if (err) {
5516                 PMD_DRV_LOG(ERR, "Unable to initialize flow_lock\n");
5517                 return err;
5518         }
5519
5520         err = pthread_mutex_init(&bp->def_cp_lock, NULL);
5521         if (err)
5522                 PMD_DRV_LOG(ERR, "Unable to initialize def_cp_lock\n");
5523
5524         err = pthread_mutex_init(&bp->health_check_lock, NULL);
5525         if (err)
5526                 PMD_DRV_LOG(ERR, "Unable to initialize health_check_lock\n");
5527         return err;
5528 }
5529
5530 static int bnxt_init_resources(struct bnxt *bp, bool reconfig_dev)
5531 {
5532         int rc = 0;
5533
5534         rc = bnxt_init_fw(bp);
5535         if (rc)
5536                 return rc;
5537
5538         if (!reconfig_dev) {
5539                 rc = bnxt_setup_mac_addr(bp->eth_dev);
5540                 if (rc)
5541                         return rc;
5542         } else {
5543                 rc = bnxt_restore_dflt_mac(bp);
5544                 if (rc)
5545                         return rc;
5546         }
5547
5548         bnxt_config_vf_req_fwd(bp);
5549
5550         rc = bnxt_hwrm_func_driver_register(bp);
5551         if (rc) {
5552                 PMD_DRV_LOG(ERR, "Failed to register driver");
5553                 return -EBUSY;
5554         }
5555
5556         if (BNXT_PF(bp)) {
5557                 if (bp->pdev->max_vfs) {
5558                         rc = bnxt_hwrm_allocate_vfs(bp, bp->pdev->max_vfs);
5559                         if (rc) {
5560                                 PMD_DRV_LOG(ERR, "Failed to allocate VFs\n");
5561                                 return rc;
5562                         }
5563                 } else {
5564                         rc = bnxt_hwrm_allocate_pf_only(bp);
5565                         if (rc) {
5566                                 PMD_DRV_LOG(ERR,
5567                                             "Failed to allocate PF resources");
5568                                 return rc;
5569                         }
5570                 }
5571         }
5572
5573         rc = bnxt_alloc_mem(bp, reconfig_dev);
5574         if (rc)
5575                 return rc;
5576
5577         rc = bnxt_setup_int(bp);
5578         if (rc)
5579                 return rc;
5580
5581         rc = bnxt_request_int(bp);
5582         if (rc)
5583                 return rc;
5584
5585         rc = bnxt_init_ctx_mem(bp);
5586         if (rc) {
5587                 PMD_DRV_LOG(ERR, "Failed to init adv_flow_counters\n");
5588                 return rc;
5589         }
5590
5591         rc = bnxt_init_locks(bp);
5592         if (rc)
5593                 return rc;
5594
5595         return 0;
5596 }
5597
5598 static int
5599 bnxt_parse_devarg_truflow(__rte_unused const char *key,
5600                           const char *value, void *opaque_arg)
5601 {
5602         struct bnxt *bp = opaque_arg;
5603         unsigned long truflow;
5604         char *end = NULL;
5605
5606         if (!value || !opaque_arg) {
5607                 PMD_DRV_LOG(ERR,
5608                             "Invalid parameter passed to truflow devargs.\n");
5609                 return -EINVAL;
5610         }
5611
5612         truflow = strtoul(value, &end, 10);
5613         if (end == NULL || *end != '\0' ||
5614             (truflow == ULONG_MAX && errno == ERANGE)) {
5615                 PMD_DRV_LOG(ERR,
5616                             "Invalid parameter passed to truflow devargs.\n");
5617                 return -EINVAL;
5618         }
5619
5620         if (BNXT_DEVARG_TRUFLOW_INVALID(truflow)) {
5621                 PMD_DRV_LOG(ERR,
5622                             "Invalid value passed to truflow devargs.\n");
5623                 return -EINVAL;
5624         }
5625
5626         if (truflow) {
5627                 bp->flags |= BNXT_FLAG_TRUFLOW_EN;
5628                 PMD_DRV_LOG(INFO, "Host-based truflow feature enabled.\n");
5629         } else {
5630                 bp->flags &= ~BNXT_FLAG_TRUFLOW_EN;
5631                 PMD_DRV_LOG(INFO, "Host-based truflow feature disabled.\n");
5632         }
5633
5634         return 0;
5635 }
5636
5637 static int
5638 bnxt_parse_devarg_flow_xstat(__rte_unused const char *key,
5639                              const char *value, void *opaque_arg)
5640 {
5641         struct bnxt *bp = opaque_arg;
5642         unsigned long flow_xstat;
5643         char *end = NULL;
5644
5645         if (!value || !opaque_arg) {
5646                 PMD_DRV_LOG(ERR,
5647                             "Invalid parameter passed to flow_xstat devarg.\n");
5648                 return -EINVAL;
5649         }
5650
5651         flow_xstat = strtoul(value, &end, 10);
5652         if (end == NULL || *end != '\0' ||
5653             (flow_xstat == ULONG_MAX && errno == ERANGE)) {
5654                 PMD_DRV_LOG(ERR,
5655                             "Invalid parameter passed to flow_xstat devarg.\n");
5656                 return -EINVAL;
5657         }
5658
5659         if (BNXT_DEVARG_FLOW_XSTAT_INVALID(flow_xstat)) {
5660                 PMD_DRV_LOG(ERR,
5661                             "Invalid value passed to flow_xstat devarg.\n");
5662                 return -EINVAL;
5663         }
5664
5665         bp->flags |= BNXT_FLAG_FLOW_XSTATS_EN;
5666         if (BNXT_FLOW_XSTATS_EN(bp))
5667                 PMD_DRV_LOG(INFO, "flow_xstat feature enabled.\n");
5668
5669         return 0;
5670 }
5671
5672 static int
5673 bnxt_parse_devarg_max_num_kflows(__rte_unused const char *key,
5674                                         const char *value, void *opaque_arg)
5675 {
5676         struct bnxt *bp = opaque_arg;
5677         unsigned long max_num_kflows;
5678         char *end = NULL;
5679
5680         if (!value || !opaque_arg) {
5681                 PMD_DRV_LOG(ERR,
5682                         "Invalid parameter passed to max_num_kflows devarg.\n");
5683                 return -EINVAL;
5684         }
5685
5686         max_num_kflows = strtoul(value, &end, 10);
5687         if (end == NULL || *end != '\0' ||
5688                 (max_num_kflows == ULONG_MAX && errno == ERANGE)) {
5689                 PMD_DRV_LOG(ERR,
5690                         "Invalid parameter passed to max_num_kflows devarg.\n");
5691                 return -EINVAL;
5692         }
5693
5694         if (bnxt_devarg_max_num_kflow_invalid(max_num_kflows)) {
5695                 PMD_DRV_LOG(ERR,
5696                         "Invalid value passed to max_num_kflows devarg.\n");
5697                 return -EINVAL;
5698         }
5699
5700         bp->max_num_kflows = max_num_kflows;
5701         if (bp->max_num_kflows)
5702                 PMD_DRV_LOG(INFO, "max_num_kflows set as %ldK.\n",
5703                                 max_num_kflows);
5704
5705         return 0;
5706 }
5707
5708 static int
5709 bnxt_parse_devarg_rep_is_pf(__rte_unused const char *key,
5710                             const char *value, void *opaque_arg)
5711 {
5712         struct bnxt_representor *vfr_bp = opaque_arg;
5713         unsigned long rep_is_pf;
5714         char *end = NULL;
5715
5716         if (!value || !opaque_arg) {
5717                 PMD_DRV_LOG(ERR,
5718                             "Invalid parameter passed to rep_is_pf devargs.\n");
5719                 return -EINVAL;
5720         }
5721
5722         rep_is_pf = strtoul(value, &end, 10);
5723         if (end == NULL || *end != '\0' ||
5724             (rep_is_pf == ULONG_MAX && errno == ERANGE)) {
5725                 PMD_DRV_LOG(ERR,
5726                             "Invalid parameter passed to rep_is_pf devargs.\n");
5727                 return -EINVAL;
5728         }
5729
5730         if (BNXT_DEVARG_REP_IS_PF_INVALID(rep_is_pf)) {
5731                 PMD_DRV_LOG(ERR,
5732                             "Invalid value passed to rep_is_pf devargs.\n");
5733                 return -EINVAL;
5734         }
5735
5736         vfr_bp->flags |= rep_is_pf;
5737         if (BNXT_REP_PF(vfr_bp))
5738                 PMD_DRV_LOG(INFO, "PF representor\n");
5739         else
5740                 PMD_DRV_LOG(INFO, "VF representor\n");
5741
5742         return 0;
5743 }
5744
5745 static int
5746 bnxt_parse_devarg_rep_based_pf(__rte_unused const char *key,
5747                                const char *value, void *opaque_arg)
5748 {
5749         struct bnxt_representor *vfr_bp = opaque_arg;
5750         unsigned long rep_based_pf;
5751         char *end = NULL;
5752
5753         if (!value || !opaque_arg) {
5754                 PMD_DRV_LOG(ERR,
5755                             "Invalid parameter passed to rep_based_pf "
5756                             "devargs.\n");
5757                 return -EINVAL;
5758         }
5759
5760         rep_based_pf = strtoul(value, &end, 10);
5761         if (end == NULL || *end != '\0' ||
5762             (rep_based_pf == ULONG_MAX && errno == ERANGE)) {
5763                 PMD_DRV_LOG(ERR,
5764                             "Invalid parameter passed to rep_based_pf "
5765                             "devargs.\n");
5766                 return -EINVAL;
5767         }
5768
5769         if (BNXT_DEVARG_REP_BASED_PF_INVALID(rep_based_pf)) {
5770                 PMD_DRV_LOG(ERR,
5771                             "Invalid value passed to rep_based_pf devargs.\n");
5772                 return -EINVAL;
5773         }
5774
5775         vfr_bp->rep_based_pf = rep_based_pf;
5776         PMD_DRV_LOG(INFO, "rep-based-pf = %d\n", vfr_bp->rep_based_pf);
5777
5778         return 0;
5779 }
5780
5781 static int
5782 bnxt_parse_devarg_rep_q_r2f(__rte_unused const char *key,
5783                             const char *value, void *opaque_arg)
5784 {
5785         struct bnxt_representor *vfr_bp = opaque_arg;
5786         unsigned long rep_q_r2f;
5787         char *end = NULL;
5788
5789         if (!value || !opaque_arg) {
5790                 PMD_DRV_LOG(ERR,
5791                             "Invalid parameter passed to rep_q_r2f "
5792                             "devargs.\n");
5793                 return -EINVAL;
5794         }
5795
5796         rep_q_r2f = strtoul(value, &end, 10);
5797         if (end == NULL || *end != '\0' ||
5798             (rep_q_r2f == ULONG_MAX && errno == ERANGE)) {
5799                 PMD_DRV_LOG(ERR,
5800                             "Invalid parameter passed to rep_q_r2f "
5801                             "devargs.\n");
5802                 return -EINVAL;
5803         }
5804
5805         if (BNXT_DEVARG_REP_Q_R2F_INVALID(rep_q_r2f)) {
5806                 PMD_DRV_LOG(ERR,
5807                             "Invalid value passed to rep_q_r2f devargs.\n");
5808                 return -EINVAL;
5809         }
5810
5811         vfr_bp->rep_q_r2f = rep_q_r2f;
5812         vfr_bp->flags |= BNXT_REP_Q_R2F_VALID;
5813         PMD_DRV_LOG(INFO, "rep-q-r2f = %d\n", vfr_bp->rep_q_r2f);
5814
5815         return 0;
5816 }
5817
5818 static int
5819 bnxt_parse_devarg_rep_q_f2r(__rte_unused const char *key,
5820                             const char *value, void *opaque_arg)
5821 {
5822         struct bnxt_representor *vfr_bp = opaque_arg;
5823         unsigned long rep_q_f2r;
5824         char *end = NULL;
5825
5826         if (!value || !opaque_arg) {
5827                 PMD_DRV_LOG(ERR,
5828                             "Invalid parameter passed to rep_q_f2r "
5829                             "devargs.\n");
5830                 return -EINVAL;
5831         }
5832
5833         rep_q_f2r = strtoul(value, &end, 10);
5834         if (end == NULL || *end != '\0' ||
5835             (rep_q_f2r == ULONG_MAX && errno == ERANGE)) {
5836                 PMD_DRV_LOG(ERR,
5837                             "Invalid parameter passed to rep_q_f2r "
5838                             "devargs.\n");
5839                 return -EINVAL;
5840         }
5841
5842         if (BNXT_DEVARG_REP_Q_F2R_INVALID(rep_q_f2r)) {
5843                 PMD_DRV_LOG(ERR,
5844                             "Invalid value passed to rep_q_f2r devargs.\n");
5845                 return -EINVAL;
5846         }
5847
5848         vfr_bp->rep_q_f2r = rep_q_f2r;
5849         vfr_bp->flags |= BNXT_REP_Q_F2R_VALID;
5850         PMD_DRV_LOG(INFO, "rep-q-f2r = %d\n", vfr_bp->rep_q_f2r);
5851
5852         return 0;
5853 }
5854
5855 static int
5856 bnxt_parse_devarg_rep_fc_r2f(__rte_unused const char *key,
5857                              const char *value, void *opaque_arg)
5858 {
5859         struct bnxt_representor *vfr_bp = opaque_arg;
5860         unsigned long rep_fc_r2f;
5861         char *end = NULL;
5862
5863         if (!value || !opaque_arg) {
5864                 PMD_DRV_LOG(ERR,
5865                             "Invalid parameter passed to rep_fc_r2f "
5866                             "devargs.\n");
5867                 return -EINVAL;
5868         }
5869
5870         rep_fc_r2f = strtoul(value, &end, 10);
5871         if (end == NULL || *end != '\0' ||
5872             (rep_fc_r2f == ULONG_MAX && errno == ERANGE)) {
5873                 PMD_DRV_LOG(ERR,
5874                             "Invalid parameter passed to rep_fc_r2f "
5875                             "devargs.\n");
5876                 return -EINVAL;
5877         }
5878
5879         if (BNXT_DEVARG_REP_FC_R2F_INVALID(rep_fc_r2f)) {
5880                 PMD_DRV_LOG(ERR,
5881                             "Invalid value passed to rep_fc_r2f devargs.\n");
5882                 return -EINVAL;
5883         }
5884
5885         vfr_bp->flags |= BNXT_REP_FC_R2F_VALID;
5886         vfr_bp->rep_fc_r2f = rep_fc_r2f;
5887         PMD_DRV_LOG(INFO, "rep-fc-r2f = %lu\n", rep_fc_r2f);
5888
5889         return 0;
5890 }
5891
5892 static int
5893 bnxt_parse_devarg_rep_fc_f2r(__rte_unused const char *key,
5894                              const char *value, void *opaque_arg)
5895 {
5896         struct bnxt_representor *vfr_bp = opaque_arg;
5897         unsigned long rep_fc_f2r;
5898         char *end = NULL;
5899
5900         if (!value || !opaque_arg) {
5901                 PMD_DRV_LOG(ERR,
5902                             "Invalid parameter passed to rep_fc_f2r "
5903                             "devargs.\n");
5904                 return -EINVAL;
5905         }
5906
5907         rep_fc_f2r = strtoul(value, &end, 10);
5908         if (end == NULL || *end != '\0' ||
5909             (rep_fc_f2r == ULONG_MAX && errno == ERANGE)) {
5910                 PMD_DRV_LOG(ERR,
5911                             "Invalid parameter passed to rep_fc_f2r "
5912                             "devargs.\n");
5913                 return -EINVAL;
5914         }
5915
5916         if (BNXT_DEVARG_REP_FC_F2R_INVALID(rep_fc_f2r)) {
5917                 PMD_DRV_LOG(ERR,
5918                             "Invalid value passed to rep_fc_f2r devargs.\n");
5919                 return -EINVAL;
5920         }
5921
5922         vfr_bp->flags |= BNXT_REP_FC_F2R_VALID;
5923         vfr_bp->rep_fc_f2r = rep_fc_f2r;
5924         PMD_DRV_LOG(INFO, "rep-fc-f2r = %lu\n", rep_fc_f2r);
5925
5926         return 0;
5927 }
5928
5929 static void
5930 bnxt_parse_dev_args(struct bnxt *bp, struct rte_devargs *devargs)
5931 {
5932         struct rte_kvargs *kvlist;
5933
5934         if (devargs == NULL)
5935                 return;
5936
5937         kvlist = rte_kvargs_parse(devargs->args, bnxt_dev_args);
5938         if (kvlist == NULL)
5939                 return;
5940
5941         /*
5942          * Handler for "truflow" devarg.
5943          * Invoked as for ex: "-w 0000:00:0d.0,host-based-truflow=1"
5944          */
5945         rte_kvargs_process(kvlist, BNXT_DEVARG_TRUFLOW,
5946                            bnxt_parse_devarg_truflow, bp);
5947
5948         /*
5949          * Handler for "flow_xstat" devarg.
5950          * Invoked as for ex: "-w 0000:00:0d.0,flow_xstat=1"
5951          */
5952         rte_kvargs_process(kvlist, BNXT_DEVARG_FLOW_XSTAT,
5953                            bnxt_parse_devarg_flow_xstat, bp);
5954
5955         /*
5956          * Handler for "max_num_kflows" devarg.
5957          * Invoked as for ex: "-w 000:00:0d.0,max_num_kflows=32"
5958          */
5959         rte_kvargs_process(kvlist, BNXT_DEVARG_MAX_NUM_KFLOWS,
5960                            bnxt_parse_devarg_max_num_kflows, bp);
5961
5962         rte_kvargs_free(kvlist);
5963 }
5964
5965 static int bnxt_alloc_switch_domain(struct bnxt *bp)
5966 {
5967         int rc = 0;
5968
5969         if (BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp)) {
5970                 rc = rte_eth_switch_domain_alloc(&bp->switch_domain_id);
5971                 if (rc)
5972                         PMD_DRV_LOG(ERR,
5973                                     "Failed to alloc switch domain: %d\n", rc);
5974                 else
5975                         PMD_DRV_LOG(INFO,
5976                                     "Switch domain allocated %d\n",
5977                                     bp->switch_domain_id);
5978         }
5979
5980         return rc;
5981 }
5982
5983 static int
5984 bnxt_dev_init(struct rte_eth_dev *eth_dev, void *params __rte_unused)
5985 {
5986         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
5987         static int version_printed;
5988         struct bnxt *bp;
5989         int rc;
5990
5991         if (version_printed++ == 0)
5992                 PMD_DRV_LOG(INFO, "%s\n", bnxt_version);
5993
5994         eth_dev->dev_ops = &bnxt_dev_ops;
5995         eth_dev->rx_queue_count = bnxt_rx_queue_count_op;
5996         eth_dev->rx_descriptor_status = bnxt_rx_descriptor_status_op;
5997         eth_dev->tx_descriptor_status = bnxt_tx_descriptor_status_op;
5998         eth_dev->rx_pkt_burst = &bnxt_recv_pkts;
5999         eth_dev->tx_pkt_burst = &bnxt_xmit_pkts;
6000
6001         /*
6002          * For secondary processes, we don't initialise any further
6003          * as primary has already done this work.
6004          */
6005         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
6006                 return 0;
6007
6008         rte_eth_copy_pci_info(eth_dev, pci_dev);
6009
6010         bp = eth_dev->data->dev_private;
6011
6012         /* Parse dev arguments passed on when starting the DPDK application. */
6013         bnxt_parse_dev_args(bp, pci_dev->device.devargs);
6014
6015         bp->flags &= ~BNXT_FLAG_RX_VECTOR_PKT_MODE;
6016
6017         if (bnxt_vf_pciid(pci_dev->id.device_id))
6018                 bp->flags |= BNXT_FLAG_VF;
6019
6020         if (bnxt_thor_device(pci_dev->id.device_id))
6021                 bp->flags |= BNXT_FLAG_THOR_CHIP;
6022
6023         if (pci_dev->id.device_id == BROADCOM_DEV_ID_58802 ||
6024             pci_dev->id.device_id == BROADCOM_DEV_ID_58804 ||
6025             pci_dev->id.device_id == BROADCOM_DEV_ID_58808 ||
6026             pci_dev->id.device_id == BROADCOM_DEV_ID_58802_VF)
6027                 bp->flags |= BNXT_FLAG_STINGRAY;
6028
6029         rc = bnxt_init_board(eth_dev);
6030         if (rc) {
6031                 PMD_DRV_LOG(ERR,
6032                             "Failed to initialize board rc: %x\n", rc);
6033                 return rc;
6034         }
6035
6036         rc = bnxt_alloc_pf_info(bp);
6037         if (rc)
6038                 goto error_free;
6039
6040         rc = bnxt_alloc_link_info(bp);
6041         if (rc)
6042                 goto error_free;
6043
6044         rc = bnxt_alloc_parent_info(bp);
6045         if (rc)
6046                 goto error_free;
6047
6048         rc = bnxt_alloc_hwrm_resources(bp);
6049         if (rc) {
6050                 PMD_DRV_LOG(ERR,
6051                             "Failed to allocate hwrm resource rc: %x\n", rc);
6052                 goto error_free;
6053         }
6054         rc = bnxt_alloc_leds_info(bp);
6055         if (rc)
6056                 goto error_free;
6057
6058         rc = bnxt_alloc_cos_queues(bp);
6059         if (rc)
6060                 goto error_free;
6061
6062         rc = bnxt_init_resources(bp, false);
6063         if (rc)
6064                 goto error_free;
6065
6066         rc = bnxt_alloc_stats_mem(bp);
6067         if (rc)
6068                 goto error_free;
6069
6070         bnxt_alloc_switch_domain(bp);
6071
6072         /* Pass the information to the rte_eth_dev_close() that it should also
6073          * release the private port resources.
6074          */
6075         eth_dev->data->dev_flags |= RTE_ETH_DEV_CLOSE_REMOVE;
6076
6077         PMD_DRV_LOG(INFO,
6078                     DRV_MODULE_NAME "found at mem %" PRIX64 ", node addr %pM\n",
6079                     pci_dev->mem_resource[0].phys_addr,
6080                     pci_dev->mem_resource[0].addr);
6081
6082         return 0;
6083
6084 error_free:
6085         bnxt_dev_uninit(eth_dev);
6086         return rc;
6087 }
6088
6089
6090 static void bnxt_free_ctx_mem_buf(struct bnxt_ctx_mem_buf_info *ctx)
6091 {
6092         if (!ctx)
6093                 return;
6094
6095         if (ctx->va)
6096                 rte_free(ctx->va);
6097
6098         ctx->va = NULL;
6099         ctx->dma = RTE_BAD_IOVA;
6100         ctx->ctx_id = BNXT_CTX_VAL_INVAL;
6101 }
6102
6103 static void bnxt_unregister_fc_ctx_mem(struct bnxt *bp)
6104 {
6105         bnxt_hwrm_cfa_counter_cfg(bp, BNXT_DIR_RX,
6106                                   CFA_COUNTER_CFG_IN_COUNTER_TYPE_FC,
6107                                   bp->flow_stat->rx_fc_out_tbl.ctx_id,
6108                                   bp->flow_stat->max_fc,
6109                                   false);
6110
6111         bnxt_hwrm_cfa_counter_cfg(bp, BNXT_DIR_TX,
6112                                   CFA_COUNTER_CFG_IN_COUNTER_TYPE_FC,
6113                                   bp->flow_stat->tx_fc_out_tbl.ctx_id,
6114                                   bp->flow_stat->max_fc,
6115                                   false);
6116
6117         if (bp->flow_stat->rx_fc_in_tbl.ctx_id != BNXT_CTX_VAL_INVAL)
6118                 bnxt_hwrm_ctx_unrgtr(bp, bp->flow_stat->rx_fc_in_tbl.ctx_id);
6119         bp->flow_stat->rx_fc_in_tbl.ctx_id = BNXT_CTX_VAL_INVAL;
6120
6121         if (bp->flow_stat->rx_fc_out_tbl.ctx_id != BNXT_CTX_VAL_INVAL)
6122                 bnxt_hwrm_ctx_unrgtr(bp, bp->flow_stat->rx_fc_out_tbl.ctx_id);
6123         bp->flow_stat->rx_fc_out_tbl.ctx_id = BNXT_CTX_VAL_INVAL;
6124
6125         if (bp->flow_stat->tx_fc_in_tbl.ctx_id != BNXT_CTX_VAL_INVAL)
6126                 bnxt_hwrm_ctx_unrgtr(bp, bp->flow_stat->tx_fc_in_tbl.ctx_id);
6127         bp->flow_stat->tx_fc_in_tbl.ctx_id = BNXT_CTX_VAL_INVAL;
6128
6129         if (bp->flow_stat->tx_fc_out_tbl.ctx_id != BNXT_CTX_VAL_INVAL)
6130                 bnxt_hwrm_ctx_unrgtr(bp, bp->flow_stat->tx_fc_out_tbl.ctx_id);
6131         bp->flow_stat->tx_fc_out_tbl.ctx_id = BNXT_CTX_VAL_INVAL;
6132 }
6133
6134 static void bnxt_uninit_fc_ctx_mem(struct bnxt *bp)
6135 {
6136         bnxt_unregister_fc_ctx_mem(bp);
6137
6138         bnxt_free_ctx_mem_buf(&bp->flow_stat->rx_fc_in_tbl);
6139         bnxt_free_ctx_mem_buf(&bp->flow_stat->rx_fc_out_tbl);
6140         bnxt_free_ctx_mem_buf(&bp->flow_stat->tx_fc_in_tbl);
6141         bnxt_free_ctx_mem_buf(&bp->flow_stat->tx_fc_out_tbl);
6142 }
6143
6144 static void bnxt_uninit_ctx_mem(struct bnxt *bp)
6145 {
6146         if (BNXT_FLOW_XSTATS_EN(bp))
6147                 bnxt_uninit_fc_ctx_mem(bp);
6148 }
6149
6150 static void
6151 bnxt_free_error_recovery_info(struct bnxt *bp)
6152 {
6153         rte_free(bp->recovery_info);
6154         bp->recovery_info = NULL;
6155         bp->fw_cap &= ~BNXT_FW_CAP_ERROR_RECOVERY;
6156 }
6157
6158 static void
6159 bnxt_uninit_locks(struct bnxt *bp)
6160 {
6161         pthread_mutex_destroy(&bp->flow_lock);
6162         pthread_mutex_destroy(&bp->def_cp_lock);
6163         pthread_mutex_destroy(&bp->health_check_lock);
6164         if (bp->rep_info) {
6165                 pthread_mutex_destroy(&bp->rep_info->vfr_lock);
6166                 pthread_mutex_destroy(&bp->rep_info->vfr_start_lock);
6167         }
6168 }
6169
6170 static int
6171 bnxt_uninit_resources(struct bnxt *bp, bool reconfig_dev)
6172 {
6173         int rc;
6174
6175         bnxt_free_int(bp);
6176         bnxt_free_mem(bp, reconfig_dev);
6177         bnxt_hwrm_func_buf_unrgtr(bp);
6178         rc = bnxt_hwrm_func_driver_unregister(bp, 0);
6179         bp->flags &= ~BNXT_FLAG_REGISTERED;
6180         bnxt_free_ctx_mem(bp);
6181         if (!reconfig_dev) {
6182                 bnxt_free_hwrm_resources(bp);
6183                 bnxt_free_error_recovery_info(bp);
6184         }
6185
6186         bnxt_uninit_ctx_mem(bp);
6187
6188         bnxt_uninit_locks(bp);
6189         bnxt_free_flow_stats_info(bp);
6190         bnxt_free_rep_info(bp);
6191         rte_free(bp->ptp_cfg);
6192         bp->ptp_cfg = NULL;
6193         return rc;
6194 }
6195
6196 static int
6197 bnxt_dev_uninit(struct rte_eth_dev *eth_dev)
6198 {
6199         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
6200                 return -EPERM;
6201
6202         PMD_DRV_LOG(DEBUG, "Calling Device uninit\n");
6203
6204         if (eth_dev->state != RTE_ETH_DEV_UNUSED)
6205                 bnxt_dev_close_op(eth_dev);
6206
6207         return 0;
6208 }
6209
6210 static int bnxt_pci_remove_dev_with_reps(struct rte_eth_dev *eth_dev)
6211 {
6212         struct bnxt *bp = eth_dev->data->dev_private;
6213         struct rte_eth_dev *vf_rep_eth_dev;
6214         int ret = 0, i;
6215
6216         if (!bp)
6217                 return -EINVAL;
6218
6219         for (i = 0; i < bp->num_reps; i++) {
6220                 vf_rep_eth_dev = bp->rep_info[i].vfr_eth_dev;
6221                 if (!vf_rep_eth_dev)
6222                         continue;
6223                 PMD_DRV_LOG(DEBUG, "BNXT Port:%d VFR pci remove\n",
6224                             vf_rep_eth_dev->data->port_id);
6225                 rte_eth_dev_destroy(vf_rep_eth_dev, bnxt_representor_uninit);
6226         }
6227         PMD_DRV_LOG(DEBUG, "BNXT Port:%d pci remove\n",
6228                     eth_dev->data->port_id);
6229         ret = rte_eth_dev_destroy(eth_dev, bnxt_dev_uninit);
6230
6231         return ret;
6232 }
6233
6234 static void bnxt_free_rep_info(struct bnxt *bp)
6235 {
6236         rte_free(bp->rep_info);
6237         bp->rep_info = NULL;
6238         rte_free(bp->cfa_code_map);
6239         bp->cfa_code_map = NULL;
6240 }
6241
6242 static int bnxt_init_rep_info(struct bnxt *bp)
6243 {
6244         int i = 0, rc;
6245
6246         if (bp->rep_info)
6247                 return 0;
6248
6249         bp->rep_info = rte_zmalloc("bnxt_rep_info",
6250                                    sizeof(bp->rep_info[0]) * BNXT_MAX_VF_REPS,
6251                                    0);
6252         if (!bp->rep_info) {
6253                 PMD_DRV_LOG(ERR, "Failed to alloc memory for rep info\n");
6254                 return -ENOMEM;
6255         }
6256         bp->cfa_code_map = rte_zmalloc("bnxt_cfa_code_map",
6257                                        sizeof(*bp->cfa_code_map) *
6258                                        BNXT_MAX_CFA_CODE, 0);
6259         if (!bp->cfa_code_map) {
6260                 PMD_DRV_LOG(ERR, "Failed to alloc memory for cfa_code_map\n");
6261                 bnxt_free_rep_info(bp);
6262                 return -ENOMEM;
6263         }
6264
6265         for (i = 0; i < BNXT_MAX_CFA_CODE; i++)
6266                 bp->cfa_code_map[i] = BNXT_VF_IDX_INVALID;
6267
6268         rc = pthread_mutex_init(&bp->rep_info->vfr_lock, NULL);
6269         if (rc) {
6270                 PMD_DRV_LOG(ERR, "Unable to initialize vfr_lock\n");
6271                 bnxt_free_rep_info(bp);
6272                 return rc;
6273         }
6274
6275         rc = pthread_mutex_init(&bp->rep_info->vfr_start_lock, NULL);
6276         if (rc) {
6277                 PMD_DRV_LOG(ERR, "Unable to initialize vfr_start_lock\n");
6278                 bnxt_free_rep_info(bp);
6279                 return rc;
6280         }
6281
6282         return rc;
6283 }
6284
6285 static int bnxt_rep_port_probe(struct rte_pci_device *pci_dev,
6286                                struct rte_eth_devargs eth_da,
6287                                struct rte_eth_dev *backing_eth_dev,
6288                                const char *dev_args)
6289 {
6290         struct rte_eth_dev *vf_rep_eth_dev;
6291         char name[RTE_ETH_NAME_MAX_LEN];
6292         struct bnxt *backing_bp;
6293         uint16_t num_rep;
6294         int i, ret = 0;
6295         struct rte_kvargs *kvlist;
6296
6297         num_rep = eth_da.nb_representor_ports;
6298         if (num_rep > BNXT_MAX_VF_REPS) {
6299                 PMD_DRV_LOG(ERR, "nb_representor_ports = %d > %d MAX VF REPS\n",
6300                             num_rep, BNXT_MAX_VF_REPS);
6301                 return -EINVAL;
6302         }
6303
6304         if (num_rep >= RTE_MAX_ETHPORTS) {
6305                 PMD_DRV_LOG(ERR,
6306                             "nb_representor_ports = %d > %d MAX ETHPORTS\n",
6307                             num_rep, RTE_MAX_ETHPORTS);
6308                 return -EINVAL;
6309         }
6310
6311         backing_bp = backing_eth_dev->data->dev_private;
6312
6313         if (!(BNXT_PF(backing_bp) || BNXT_VF_IS_TRUSTED(backing_bp))) {
6314                 PMD_DRV_LOG(ERR,
6315                             "Not a PF or trusted VF. No Representor support\n");
6316                 /* Returning an error is not an option.
6317                  * Applications are not handling this correctly
6318                  */
6319                 return 0;
6320         }
6321
6322         if (bnxt_init_rep_info(backing_bp))
6323                 return 0;
6324
6325         for (i = 0; i < num_rep; i++) {
6326                 struct bnxt_representor representor = {
6327                         .vf_id = eth_da.representor_ports[i],
6328                         .switch_domain_id = backing_bp->switch_domain_id,
6329                         .parent_dev = backing_eth_dev
6330                 };
6331
6332                 if (representor.vf_id >= BNXT_MAX_VF_REPS) {
6333                         PMD_DRV_LOG(ERR, "VF-Rep id %d >= %d MAX VF ID\n",
6334                                     representor.vf_id, BNXT_MAX_VF_REPS);
6335                         continue;
6336                 }
6337
6338                 /* representor port net_bdf_port */
6339                 snprintf(name, sizeof(name), "net_%s_representor_%d",
6340                          pci_dev->device.name, eth_da.representor_ports[i]);
6341
6342                 kvlist = rte_kvargs_parse(dev_args, bnxt_dev_args);
6343                 if (kvlist) {
6344                         /*
6345                          * Handler for "rep_is_pf" devarg.
6346                          * Invoked as for ex: "-w 000:00:0d.0,
6347                          * rep-based-pf=<pf index> rep-is-pf=<VF=0 or PF=1>"
6348                          */
6349                         rte_kvargs_process(kvlist, BNXT_DEVARG_REP_IS_PF,
6350                                            bnxt_parse_devarg_rep_is_pf,
6351                                            (void *)&representor);
6352                         /*
6353                          * Handler for "rep_based_pf" devarg.
6354                          * Invoked as for ex: "-w 000:00:0d.0,
6355                          * rep-based-pf=<pf index> rep-is-pf=<VF=0 or PF=1>"
6356                          */
6357                         rte_kvargs_process(kvlist, BNXT_DEVARG_REP_BASED_PF,
6358                                            bnxt_parse_devarg_rep_based_pf,
6359                                            (void *)&representor);
6360                         /*
6361                          * Handler for "rep_based_pf" devarg.
6362                          * Invoked as for ex: "-w 000:00:0d.0,
6363                          * rep-based-pf=<pf index> rep-is-pf=<VF=0 or PF=1>"
6364                          */
6365                         rte_kvargs_process(kvlist, BNXT_DEVARG_REP_Q_R2F,
6366                                            bnxt_parse_devarg_rep_q_r2f,
6367                                            (void *)&representor);
6368                         /*
6369                          * Handler for "rep_based_pf" devarg.
6370                          * Invoked as for ex: "-w 000:00:0d.0,
6371                          * rep-based-pf=<pf index> rep-is-pf=<VF=0 or PF=1>"
6372                          */
6373                         rte_kvargs_process(kvlist, BNXT_DEVARG_REP_Q_F2R,
6374                                            bnxt_parse_devarg_rep_q_f2r,
6375                                            (void *)&representor);
6376                         /*
6377                          * Handler for "rep_based_pf" devarg.
6378                          * Invoked as for ex: "-w 000:00:0d.0,
6379                          * rep-based-pf=<pf index> rep-is-pf=<VF=0 or PF=1>"
6380                          */
6381                         rte_kvargs_process(kvlist, BNXT_DEVARG_REP_FC_R2F,
6382                                            bnxt_parse_devarg_rep_fc_r2f,
6383                                            (void *)&representor);
6384                         /*
6385                          * Handler for "rep_based_pf" devarg.
6386                          * Invoked as for ex: "-w 000:00:0d.0,
6387                          * rep-based-pf=<pf index> rep-is-pf=<VF=0 or PF=1>"
6388                          */
6389                         rte_kvargs_process(kvlist, BNXT_DEVARG_REP_FC_F2R,
6390                                            bnxt_parse_devarg_rep_fc_f2r,
6391                                            (void *)&representor);
6392                 }
6393
6394                 ret = rte_eth_dev_create(&pci_dev->device, name,
6395                                          sizeof(struct bnxt_representor),
6396                                          NULL, NULL,
6397                                          bnxt_representor_init,
6398                                          &representor);
6399                 if (ret) {
6400                         PMD_DRV_LOG(ERR, "failed to create bnxt vf "
6401                                     "representor %s.", name);
6402                         goto err;
6403                 }
6404
6405                 vf_rep_eth_dev = rte_eth_dev_allocated(name);
6406                 if (!vf_rep_eth_dev) {
6407                         PMD_DRV_LOG(ERR, "Failed to find the eth_dev"
6408                                     " for VF-Rep: %s.", name);
6409                         ret = -ENODEV;
6410                         goto err;
6411                 }
6412
6413                 PMD_DRV_LOG(DEBUG, "BNXT Port:%d VFR pci probe\n",
6414                             backing_eth_dev->data->port_id);
6415                 backing_bp->rep_info[representor.vf_id].vfr_eth_dev =
6416                                                          vf_rep_eth_dev;
6417                 backing_bp->num_reps++;
6418
6419         }
6420
6421         return 0;
6422
6423 err:
6424         /* If num_rep > 1, then rollback already created
6425          * ports, since we'll be failing the probe anyway
6426          */
6427         if (num_rep > 1)
6428                 bnxt_pci_remove_dev_with_reps(backing_eth_dev);
6429
6430         return ret;
6431 }
6432
6433 static int bnxt_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
6434                           struct rte_pci_device *pci_dev)
6435 {
6436         struct rte_eth_devargs eth_da = { .nb_representor_ports = 0 };
6437         struct rte_eth_dev *backing_eth_dev;
6438         uint16_t num_rep;
6439         int ret = 0;
6440
6441         if (pci_dev->device.devargs) {
6442                 ret = rte_eth_devargs_parse(pci_dev->device.devargs->args,
6443                                             &eth_da);
6444                 if (ret)
6445                         return ret;
6446         }
6447
6448         num_rep = eth_da.nb_representor_ports;
6449         PMD_DRV_LOG(DEBUG, "nb_representor_ports = %d\n",
6450                     num_rep);
6451
6452         /* We could come here after first level of probe is already invoked
6453          * as part of an application bringup(OVS-DPDK vswitchd), so first check
6454          * for already allocated eth_dev for the backing device (PF/Trusted VF)
6455          */
6456         backing_eth_dev = rte_eth_dev_allocated(pci_dev->device.name);
6457         if (backing_eth_dev == NULL) {
6458                 ret = rte_eth_dev_create(&pci_dev->device, pci_dev->device.name,
6459                                          sizeof(struct bnxt),
6460                                          eth_dev_pci_specific_init, pci_dev,
6461                                          bnxt_dev_init, NULL);
6462
6463                 if (ret || !num_rep)
6464                         return ret;
6465
6466                 backing_eth_dev = rte_eth_dev_allocated(pci_dev->device.name);
6467         }
6468         PMD_DRV_LOG(DEBUG, "BNXT Port:%d pci probe\n",
6469                     backing_eth_dev->data->port_id);
6470         /* probe representor ports now */
6471         ret = bnxt_rep_port_probe(pci_dev, eth_da, backing_eth_dev,
6472                                   pci_dev->device.devargs->args);
6473
6474         return ret;
6475 }
6476
6477 static int bnxt_pci_remove(struct rte_pci_device *pci_dev)
6478 {
6479         struct rte_eth_dev *eth_dev;
6480
6481         eth_dev = rte_eth_dev_allocated(pci_dev->device.name);
6482         if (!eth_dev)
6483                 return 0; /* Invoked typically only by OVS-DPDK, by the
6484                            * time it comes here the eth_dev is already
6485                            * deleted by rte_eth_dev_close(), so returning
6486                            * +ve value will at least help in proper cleanup
6487                            */
6488
6489         PMD_DRV_LOG(DEBUG, "BNXT Port:%d pci remove\n", eth_dev->data->port_id);
6490         if (rte_eal_process_type() == RTE_PROC_PRIMARY) {
6491                 if (eth_dev->data->dev_flags & RTE_ETH_DEV_REPRESENTOR)
6492                         return rte_eth_dev_destroy(eth_dev,
6493                                                    bnxt_representor_uninit);
6494                 else
6495                         return rte_eth_dev_destroy(eth_dev,
6496                                                    bnxt_dev_uninit);
6497         } else {
6498                 return rte_eth_dev_pci_generic_remove(pci_dev, NULL);
6499         }
6500 }
6501
6502 static struct rte_pci_driver bnxt_rte_pmd = {
6503         .id_table = bnxt_pci_id_map,
6504         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC |
6505                         RTE_PCI_DRV_PROBE_AGAIN, /* Needed in case of VF-REPs
6506                                                   * and OVS-DPDK
6507                                                   */
6508         .probe = bnxt_pci_probe,
6509         .remove = bnxt_pci_remove,
6510 };
6511
6512 static bool
6513 is_device_supported(struct rte_eth_dev *dev, struct rte_pci_driver *drv)
6514 {
6515         if (strcmp(dev->device->driver->name, drv->driver.name))
6516                 return false;
6517
6518         return true;
6519 }
6520
6521 bool is_bnxt_supported(struct rte_eth_dev *dev)
6522 {
6523         return is_device_supported(dev, &bnxt_rte_pmd);
6524 }
6525
6526 RTE_LOG_REGISTER(bnxt_logtype_driver, pmd.net.bnxt.driver, NOTICE);
6527 RTE_PMD_REGISTER_PCI(net_bnxt, bnxt_rte_pmd);
6528 RTE_PMD_REGISTER_PCI_TABLE(net_bnxt, bnxt_pci_id_map);
6529 RTE_PMD_REGISTER_KMOD_DEP(net_bnxt, "* igb_uio | uio_pci_generic | vfio-pci");