drivers/net/bnxt/bnxt_ethdev.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2014-2018 Broadcom
   3  * All rights reserved.
   4  */
   5
   6 #include <inttypes.h>
   7 #include <stdbool.h>
   8
   9 #include <rte_dev.h>
  10 #include <rte_ethdev_driver.h>
  11 #include <rte_ethdev_pci.h>
  12 #include <rte_malloc.h>
  13 #include <rte_cycles.h>
  14 #include <rte_alarm.h>
  15 #include <rte_kvargs.h>
  16
  17 #include "bnxt.h"
  18 #include "bnxt_filter.h"
  19 #include "bnxt_hwrm.h"
  20 #include "bnxt_irq.h"
  21 #include "bnxt_reps.h"
  22 #include "bnxt_ring.h"
  23 #include "bnxt_rxq.h"
  24 #include "bnxt_rxr.h"
  25 #include "bnxt_stats.h"
  26 #include "bnxt_txq.h"
  27 #include "bnxt_txr.h"
  28 #include "bnxt_vnic.h"
  29 #include "hsi_struct_def_dpdk.h"
  30 #include "bnxt_nvm_defs.h"
  31 #include "bnxt_tf_common.h"
  32 #include "ulp_flow_db.h"
  33
  34 #define DRV_MODULE_NAME         "bnxt"
  35 static const char bnxt_version[] =
  36         "Broadcom NetXtreme driver " DRV_MODULE_NAME;
  37
  38 /*
  39  * The set of PCI devices this driver supports
  40  */
  41 static const struct rte_pci_id bnxt_pci_id_map[] = {
  42         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM,
  43                          BROADCOM_DEV_ID_STRATUS_NIC_VF1) },
  44         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM,
  45                          BROADCOM_DEV_ID_STRATUS_NIC_VF2) },
  46         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_STRATUS_NIC) },
  47         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414_VF) },
  48         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57301) },
  49         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57302) },
  50         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57304_PF) },
  51         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57304_VF) },
  52         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_NS2) },
  53         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57402) },
  54         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57404) },
  55         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57406_PF) },
  56         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57406_VF) },
  57         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57402_MF) },
  58         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57407_RJ45) },
  59         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57404_MF) },
  60         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57406_MF) },
  61         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57407_SFP) },
  62         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57407_MF) },
  63         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_5741X_VF) },
  64         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_5731X_VF) },
  65         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57314) },
  66         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_MF) },
  67         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57311) },
  68         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57312) },
  69         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57412) },
  70         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414) },
  71         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_RJ45) },
  72         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_RJ45) },
  73         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57412_MF) },
  74         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57317_RJ45) },
  75         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_SFP) },
  76         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_SFP) },
  77         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57317_SFP) },
  78         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414_MF) },
  79         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_MF) },
  80         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58802) },
  81         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58804) },
  82         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58808) },
  83         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58802_VF) },
  84         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57508) },
  85         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57504) },
  86         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57502) },
  87         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57500_VF1) },
  88         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57500_VF2) },
  89         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57508_MF1) },
  90         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57504_MF1) },
  91         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57502_MF1) },
  92         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57508_MF2) },
  93         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57504_MF2) },
  94         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57502_MF2) },
  95         { .vendor_id = 0, /* sentinel */ },
  96 };
  97
  98 #define BNXT_DEVARG_TRUFLOW     "host-based-truflow"
  99 #define BNXT_DEVARG_FLOW_XSTAT  "flow-xstat"
 100 #define BNXT_DEVARG_MAX_NUM_KFLOWS  "max-num-kflows"
 101 #define BNXT_DEVARG_REPRESENTOR "representor"
 102 #define BNXT_DEVARG_REP_BASED_PF  "rep-based-pf"
 103 #define BNXT_DEVARG_REP_IS_PF  "rep-is-pf"
 104 #define BNXT_DEVARG_REP_Q_R2F  "rep-q-r2f"
 105 #define BNXT_DEVARG_REP_Q_F2R  "rep-q-f2r"
 106 #define BNXT_DEVARG_REP_FC_R2F  "rep-fc-r2f"
 107 #define BNXT_DEVARG_REP_FC_F2R  "rep-fc-f2r"
 108
 109 static const char *const bnxt_dev_args[] = {
 110         BNXT_DEVARG_REPRESENTOR,
 111         BNXT_DEVARG_TRUFLOW,
 112         BNXT_DEVARG_FLOW_XSTAT,
 113         BNXT_DEVARG_MAX_NUM_KFLOWS,
 114         BNXT_DEVARG_REP_BASED_PF,
 115         BNXT_DEVARG_REP_IS_PF,
 116         BNXT_DEVARG_REP_Q_R2F,
 117         BNXT_DEVARG_REP_Q_F2R,
 118         BNXT_DEVARG_REP_FC_R2F,
 119         BNXT_DEVARG_REP_FC_F2R,
 120         NULL
 121 };
 122
 123 /*
 124  * truflow == false to disable the feature
 125  * truflow == true to enable the feature
 126  */
 127 #define BNXT_DEVARG_TRUFLOW_INVALID(truflow)    ((truflow) > 1)
 128
 129 /*
 130  * flow_xstat == false to disable the feature
 131  * flow_xstat == true to enable the feature
 132  */
 133 #define BNXT_DEVARG_FLOW_XSTAT_INVALID(flow_xstat)      ((flow_xstat) > 1)
 134
 135 /*
 136  * rep_is_pf == false to indicate VF representor
 137  * rep_is_pf == true to indicate PF representor
 138  */
 139 #define BNXT_DEVARG_REP_IS_PF_INVALID(rep_is_pf)        ((rep_is_pf) > 1)
 140
 141 /*
 142  * rep_based_pf == Physical index of the PF
 143  */
 144 #define BNXT_DEVARG_REP_BASED_PF_INVALID(rep_based_pf)  ((rep_based_pf) > 15)
 145 /*
 146  * rep_q_r2f == Logical COS Queue index for the rep to endpoint direction
 147  */
 148 #define BNXT_DEVARG_REP_Q_R2F_INVALID(rep_q_r2f)        ((rep_q_r2f) > 3)
 149
 150 /*
 151  * rep_q_f2r == Logical COS Queue index for the endpoint to rep direction
 152  */
 153 #define BNXT_DEVARG_REP_Q_F2R_INVALID(rep_q_f2r)        ((rep_q_f2r) > 3)
 154
 155 /*
 156  * rep_fc_r2f == Flow control for the representor to endpoint direction
 157  */
 158 #define BNXT_DEVARG_REP_FC_R2F_INVALID(rep_fc_r2f)      ((rep_fc_r2f) > 1)
 159
 160 /*
 161  * rep_fc_f2r == Flow control for the endpoint to representor direction
 162  */
 163 #define BNXT_DEVARG_REP_FC_F2R_INVALID(rep_fc_f2r)      ((rep_fc_f2r) > 1)
 164
 165 /*
 166  * max_num_kflows must be >= 32
 167  * and must be a power-of-2 supported value
 168  * return: 1 -> invalid
 169  *         0 -> valid
 170  */
 171 static int bnxt_devarg_max_num_kflow_invalid(uint16_t max_num_kflows)
 172 {
 173         if (max_num_kflows < 32 || !rte_is_power_of_2(max_num_kflows))
 174                 return 1;
 175         return 0;
 176 }
 177
 178 static int bnxt_vlan_offload_set_op(struct rte_eth_dev *dev, int mask);
 179 static int bnxt_dev_uninit(struct rte_eth_dev *eth_dev);
 180 static int bnxt_init_resources(struct bnxt *bp, bool reconfig_dev);
 181 static int bnxt_uninit_resources(struct bnxt *bp, bool reconfig_dev);
 182 static void bnxt_cancel_fw_health_check(struct bnxt *bp);
 183 static int bnxt_restore_vlan_filters(struct bnxt *bp);
 184 static void bnxt_dev_recover(void *arg);
 185 static void bnxt_free_error_recovery_info(struct bnxt *bp);
 186 static void bnxt_free_rep_info(struct bnxt *bp);
 187
 188 int is_bnxt_in_error(struct bnxt *bp)
 189 {
 190         if (bp->flags & BNXT_FLAG_FATAL_ERROR)
 191                 return -EIO;
 192         if (bp->flags & BNXT_FLAG_FW_RESET)
 193                 return -EBUSY;
 194
 195         return 0;
 196 }
 197
 198 /***********************/
 199
 200 /*
 201  * High level utility functions
 202  */
 203
 204 static uint16_t bnxt_rss_ctxts(const struct bnxt *bp)
 205 {
 206         if (!BNXT_CHIP_THOR(bp))
 207                 return 1;
 208
 209         return RTE_ALIGN_MUL_CEIL(bp->rx_nr_rings,
 210                                   BNXT_RSS_ENTRIES_PER_CTX_THOR) /
 211                                     BNXT_RSS_ENTRIES_PER_CTX_THOR;
 212 }
 213
 214 uint16_t bnxt_rss_hash_tbl_size(const struct bnxt *bp)
 215 {
 216         if (!BNXT_CHIP_THOR(bp))
 217                 return HW_HASH_INDEX_SIZE;
 218
 219         return bnxt_rss_ctxts(bp) * BNXT_RSS_ENTRIES_PER_CTX_THOR;
 220 }
 221
 222 static void bnxt_free_parent_info(struct bnxt *bp)
 223 {
 224         rte_free(bp->parent);
 225 }
 226
 227 static void bnxt_free_pf_info(struct bnxt *bp)
 228 {
 229         rte_free(bp->pf);
 230 }
 231
 232 static void bnxt_free_link_info(struct bnxt *bp)
 233 {
 234         rte_free(bp->link_info);
 235 }
 236
 237 static void bnxt_free_leds_info(struct bnxt *bp)
 238 {
 239         if (BNXT_VF(bp))
 240                 return;
 241
 242         rte_free(bp->leds);
 243         bp->leds = NULL;
 244 }
 245
 246 static void bnxt_free_flow_stats_info(struct bnxt *bp)
 247 {
 248         rte_free(bp->flow_stat);
 249         bp->flow_stat = NULL;
 250 }
 251
 252 static void bnxt_free_cos_queues(struct bnxt *bp)
 253 {
 254         rte_free(bp->rx_cos_queue);
 255         rte_free(bp->tx_cos_queue);
 256 }
 257
 258 static void bnxt_free_mem(struct bnxt *bp, bool reconfig)
 259 {
 260         bnxt_free_filter_mem(bp);
 261         bnxt_free_vnic_attributes(bp);
 262         bnxt_free_vnic_mem(bp);
 263
 264         /* tx/rx rings are configured as part of *_queue_setup callbacks.
 265          * If the number of rings change across fw update,
 266          * we don't have much choice except to warn the user.
 267          */
 268         if (!reconfig) {
 269                 bnxt_free_stats(bp);
 270                 bnxt_free_tx_rings(bp);
 271                 bnxt_free_rx_rings(bp);
 272         }
 273         bnxt_free_async_cp_ring(bp);
 274         bnxt_free_rxtx_nq_ring(bp);
 275
 276         rte_free(bp->grp_info);
 277         bp->grp_info = NULL;
 278 }
 279
 280 static int bnxt_alloc_parent_info(struct bnxt *bp)
 281 {
 282         bp->parent = rte_zmalloc("bnxt_parent_info",
 283                                  sizeof(struct bnxt_parent_info), 0);
 284         if (bp->parent == NULL)
 285                 return -ENOMEM;
 286
 287         return 0;
 288 }
 289
 290 static int bnxt_alloc_pf_info(struct bnxt *bp)
 291 {
 292         bp->pf = rte_zmalloc("bnxt_pf_info", sizeof(struct bnxt_pf_info), 0);
 293         if (bp->pf == NULL)
 294                 return -ENOMEM;
 295
 296         return 0;
 297 }
 298
 299 static int bnxt_alloc_link_info(struct bnxt *bp)
 300 {
 301         bp->link_info =
 302                 rte_zmalloc("bnxt_link_info", sizeof(struct bnxt_link_info), 0);
 303         if (bp->link_info == NULL)
 304                 return -ENOMEM;
 305
 306         return 0;
 307 }
 308
 309 static int bnxt_alloc_leds_info(struct bnxt *bp)
 310 {
 311         if (BNXT_VF(bp))
 312                 return 0;
 313
 314         bp->leds = rte_zmalloc("bnxt_leds",
 315                                BNXT_MAX_LED * sizeof(struct bnxt_led_info),
 316                                0);
 317         if (bp->leds == NULL)
 318                 return -ENOMEM;
 319
 320         return 0;
 321 }
 322
 323 static int bnxt_alloc_cos_queues(struct bnxt *bp)
 324 {
 325         bp->rx_cos_queue =
 326                 rte_zmalloc("bnxt_rx_cosq",
 327                             BNXT_COS_QUEUE_COUNT *
 328                             sizeof(struct bnxt_cos_queue_info),
 329                             0);
 330         if (bp->rx_cos_queue == NULL)
 331                 return -ENOMEM;
 332
 333         bp->tx_cos_queue =
 334                 rte_zmalloc("bnxt_tx_cosq",
 335                             BNXT_COS_QUEUE_COUNT *
 336                             sizeof(struct bnxt_cos_queue_info),
 337                             0);
 338         if (bp->tx_cos_queue == NULL)
 339                 return -ENOMEM;
 340
 341         return 0;
 342 }
 343
 344 static int bnxt_alloc_flow_stats_info(struct bnxt *bp)
 345 {
 346         bp->flow_stat = rte_zmalloc("bnxt_flow_xstat",
 347                                     sizeof(struct bnxt_flow_stat_info), 0);
 348         if (bp->flow_stat == NULL)
 349                 return -ENOMEM;
 350
 351         return 0;
 352 }
 353
 354 static int bnxt_alloc_mem(struct bnxt *bp, bool reconfig)
 355 {
 356         int rc;
 357
 358         rc = bnxt_alloc_ring_grps(bp);
 359         if (rc)
 360                 goto alloc_mem_err;
 361
 362         rc = bnxt_alloc_async_ring_struct(bp);
 363         if (rc)
 364                 goto alloc_mem_err;
 365
 366         rc = bnxt_alloc_vnic_mem(bp);
 367         if (rc)
 368                 goto alloc_mem_err;
 369
 370         rc = bnxt_alloc_vnic_attributes(bp);
 371         if (rc)
 372                 goto alloc_mem_err;
 373
 374         rc = bnxt_alloc_filter_mem(bp);
 375         if (rc)
 376                 goto alloc_mem_err;
 377
 378         rc = bnxt_alloc_async_cp_ring(bp);
 379         if (rc)
 380                 goto alloc_mem_err;
 381
 382         rc = bnxt_alloc_rxtx_nq_ring(bp);
 383         if (rc)
 384                 goto alloc_mem_err;
 385
 386         if (BNXT_FLOW_XSTATS_EN(bp)) {
 387                 rc = bnxt_alloc_flow_stats_info(bp);
 388                 if (rc)
 389                         goto alloc_mem_err;
 390         }
 391
 392         return 0;
 393
 394 alloc_mem_err:
 395         bnxt_free_mem(bp, reconfig);
 396         return rc;
 397 }
 398
 399 static int bnxt_setup_one_vnic(struct bnxt *bp, uint16_t vnic_id)
 400 {
 401         struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
 402         struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id];
 403         uint64_t rx_offloads = dev_conf->rxmode.offloads;
 404         struct bnxt_rx_queue *rxq;
 405         unsigned int j;
 406         int rc;
 407
 408         rc = bnxt_vnic_grp_alloc(bp, vnic);
 409         if (rc)
 410                 goto err_out;
 411
 412         PMD_DRV_LOG(DEBUG, "vnic[%d] = %p vnic->fw_grp_ids = %p\n",
 413                     vnic_id, vnic, vnic->fw_grp_ids);
 414
 415         rc = bnxt_hwrm_vnic_alloc(bp, vnic);
 416         if (rc)
 417                 goto err_out;
 418
 419         /* Alloc RSS context only if RSS mode is enabled */
 420         if (dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS) {
 421                 int j, nr_ctxs = bnxt_rss_ctxts(bp);
 422
 423                 rc = 0;
 424                 for (j = 0; j < nr_ctxs; j++) {
 425                         rc = bnxt_hwrm_vnic_ctx_alloc(bp, vnic, j);
 426                         if (rc)
 427                                 break;
 428                 }
 429                 if (rc) {
 430                         PMD_DRV_LOG(ERR,
 431                                     "HWRM vnic %d ctx %d alloc failure rc: %x\n",
 432                                     vnic_id, j, rc);
 433                         goto err_out;
 434                 }
 435                 vnic->num_lb_ctxts = nr_ctxs;
 436         }
 437
 438         /*
 439          * Firmware sets pf pair in default vnic cfg. If the VLAN strip
 440          * setting is not available at this time, it will not be
 441          * configured correctly in the CFA.
 442          */
 443         if (rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
 444                 vnic->vlan_strip = true;
 445         else
 446                 vnic->vlan_strip = false;
 447
 448         rc = bnxt_hwrm_vnic_cfg(bp, vnic);
 449         if (rc)
 450                 goto err_out;
 451
 452         rc = bnxt_set_hwrm_vnic_filters(bp, vnic);
 453         if (rc)
 454                 goto err_out;
 455
 456         for (j = 0; j < bp->rx_num_qs_per_vnic; j++) {
 457                 rxq = bp->eth_dev->data->rx_queues[j];
 458
 459                 PMD_DRV_LOG(DEBUG,
 460                             "rxq[%d]->vnic=%p vnic->fw_grp_ids=%p\n",
 461                             j, rxq->vnic, rxq->vnic->fw_grp_ids);
 462
 463                 if (BNXT_HAS_RING_GRPS(bp) && rxq->rx_deferred_start)
 464                         rxq->vnic->fw_grp_ids[j] = INVALID_HW_RING_ID;
 465                 else
 466                         vnic->rx_queue_cnt++;
 467         }
 468
 469         PMD_DRV_LOG(DEBUG, "vnic->rx_queue_cnt = %d\n", vnic->rx_queue_cnt);
 470
 471         rc = bnxt_vnic_rss_configure(bp, vnic);
 472         if (rc)
 473                 goto err_out;
 474
 475         bnxt_hwrm_vnic_plcmode_cfg(bp, vnic);
 476
 477         if (rx_offloads & DEV_RX_OFFLOAD_TCP_LRO)
 478                 bnxt_hwrm_vnic_tpa_cfg(bp, vnic, 1);
 479         else
 480                 bnxt_hwrm_vnic_tpa_cfg(bp, vnic, 0);
 481
 482         return 0;
 483 err_out:
 484         PMD_DRV_LOG(ERR, "HWRM vnic %d cfg failure rc: %x\n",
 485                     vnic_id, rc);
 486         return rc;
 487 }
 488
 489 static int bnxt_register_fc_ctx_mem(struct bnxt *bp)
 490 {
 491         int rc = 0;
 492
 493         rc = bnxt_hwrm_ctx_rgtr(bp, bp->flow_stat->rx_fc_in_tbl.dma,
 494                                 &bp->flow_stat->rx_fc_in_tbl.ctx_id);
 495         if (rc)
 496                 return rc;
 497
 498         PMD_DRV_LOG(DEBUG,
 499                     "rx_fc_in_tbl.va = %p rx_fc_in_tbl.dma = %p"
 500                     " rx_fc_in_tbl.ctx_id = %d\n",
 501                     bp->flow_stat->rx_fc_in_tbl.va,
 502                     (void *)((uintptr_t)bp->flow_stat->rx_fc_in_tbl.dma),
 503                     bp->flow_stat->rx_fc_in_tbl.ctx_id);
 504
 505         rc = bnxt_hwrm_ctx_rgtr(bp, bp->flow_stat->rx_fc_out_tbl.dma,
 506                                 &bp->flow_stat->rx_fc_out_tbl.ctx_id);
 507         if (rc)
 508                 return rc;
 509
 510         PMD_DRV_LOG(DEBUG,
 511                     "rx_fc_out_tbl.va = %p rx_fc_out_tbl.dma = %p"
 512                     " rx_fc_out_tbl.ctx_id = %d\n",
 513                     bp->flow_stat->rx_fc_out_tbl.va,
 514                     (void *)((uintptr_t)bp->flow_stat->rx_fc_out_tbl.dma),
 515                     bp->flow_stat->rx_fc_out_tbl.ctx_id);
 516
 517         rc = bnxt_hwrm_ctx_rgtr(bp, bp->flow_stat->tx_fc_in_tbl.dma,
 518                                 &bp->flow_stat->tx_fc_in_tbl.ctx_id);
 519         if (rc)
 520                 return rc;
 521
 522         PMD_DRV_LOG(DEBUG,
 523                     "tx_fc_in_tbl.va = %p tx_fc_in_tbl.dma = %p"
 524                     " tx_fc_in_tbl.ctx_id = %d\n",
 525                     bp->flow_stat->tx_fc_in_tbl.va,
 526                     (void *)((uintptr_t)bp->flow_stat->tx_fc_in_tbl.dma),
 527                     bp->flow_stat->tx_fc_in_tbl.ctx_id);
 528
 529         rc = bnxt_hwrm_ctx_rgtr(bp, bp->flow_stat->tx_fc_out_tbl.dma,
 530                                 &bp->flow_stat->tx_fc_out_tbl.ctx_id);
 531         if (rc)
 532                 return rc;
 533
 534         PMD_DRV_LOG(DEBUG,
 535                     "tx_fc_out_tbl.va = %p tx_fc_out_tbl.dma = %p"
 536                     " tx_fc_out_tbl.ctx_id = %d\n",
 537                     bp->flow_stat->tx_fc_out_tbl.va,
 538                     (void *)((uintptr_t)bp->flow_stat->tx_fc_out_tbl.dma),
 539                     bp->flow_stat->tx_fc_out_tbl.ctx_id);
 540
 541         memset(bp->flow_stat->rx_fc_out_tbl.va,
 542                0,
 543                bp->flow_stat->rx_fc_out_tbl.size);
 544         rc = bnxt_hwrm_cfa_counter_cfg(bp, BNXT_DIR_RX,
 545                                        CFA_COUNTER_CFG_IN_COUNTER_TYPE_FC,
 546                                        bp->flow_stat->rx_fc_out_tbl.ctx_id,
 547                                        bp->flow_stat->max_fc,
 548                                        true);
 549         if (rc)
 550                 return rc;
 551
 552         memset(bp->flow_stat->tx_fc_out_tbl.va,
 553                0,
 554                bp->flow_stat->tx_fc_out_tbl.size);
 555         rc = bnxt_hwrm_cfa_counter_cfg(bp, BNXT_DIR_TX,
 556                                        CFA_COUNTER_CFG_IN_COUNTER_TYPE_FC,
 557                                        bp->flow_stat->tx_fc_out_tbl.ctx_id,
 558                                        bp->flow_stat->max_fc,
 559                                        true);
 560
 561         return rc;
 562 }
 563
 564 static int bnxt_alloc_ctx_mem_buf(char *type, size_t size,
 565                                   struct bnxt_ctx_mem_buf_info *ctx)
 566 {
 567         if (!ctx)
 568                 return -EINVAL;
 569
 570         ctx->va = rte_zmalloc(type, size, 0);
 571         if (ctx->va == NULL)
 572                 return -ENOMEM;
 573         rte_mem_lock_page(ctx->va);
 574         ctx->size = size;
 575         ctx->dma = rte_mem_virt2iova(ctx->va);
 576         if (ctx->dma == RTE_BAD_IOVA)
 577                 return -ENOMEM;
 578
 579         return 0;
 580 }
 581
 582 static int bnxt_init_fc_ctx_mem(struct bnxt *bp)
 583 {
 584         struct rte_pci_device *pdev = bp->pdev;
 585         char type[RTE_MEMZONE_NAMESIZE];
 586         uint16_t max_fc;
 587         int rc = 0;
 588
 589         max_fc = bp->flow_stat->max_fc;
 590
 591         sprintf(type, "bnxt_rx_fc_in_" PCI_PRI_FMT, pdev->addr.domain,
 592                 pdev->addr.bus, pdev->addr.devid, pdev->addr.function);
 593         /* 4 bytes for each counter-id */
 594         rc = bnxt_alloc_ctx_mem_buf(type,
 595                                     max_fc * 4,
 596                                     &bp->flow_stat->rx_fc_in_tbl);
 597         if (rc)
 598                 return rc;
 599
 600         sprintf(type, "bnxt_rx_fc_out_" PCI_PRI_FMT, pdev->addr.domain,
 601                 pdev->addr.bus, pdev->addr.devid, pdev->addr.function);
 602         /* 16 bytes for each counter - 8 bytes pkt_count, 8 bytes byte_count */
 603         rc = bnxt_alloc_ctx_mem_buf(type,
 604                                     max_fc * 16,
 605                                     &bp->flow_stat->rx_fc_out_tbl);
 606         if (rc)
 607                 return rc;
 608
 609         sprintf(type, "bnxt_tx_fc_in_" PCI_PRI_FMT, pdev->addr.domain,
 610                 pdev->addr.bus, pdev->addr.devid, pdev->addr.function);
 611         /* 4 bytes for each counter-id */
 612         rc = bnxt_alloc_ctx_mem_buf(type,
 613                                     max_fc * 4,
 614                                     &bp->flow_stat->tx_fc_in_tbl);
 615         if (rc)
 616                 return rc;
 617
 618         sprintf(type, "bnxt_tx_fc_out_" PCI_PRI_FMT, pdev->addr.domain,
 619                 pdev->addr.bus, pdev->addr.devid, pdev->addr.function);
 620         /* 16 bytes for each counter - 8 bytes pkt_count, 8 bytes byte_count */
 621         rc = bnxt_alloc_ctx_mem_buf(type,
 622                                     max_fc * 16,
 623                                     &bp->flow_stat->tx_fc_out_tbl);
 624         if (rc)
 625                 return rc;
 626
 627         rc = bnxt_register_fc_ctx_mem(bp);
 628
 629         return rc;
 630 }
 631
 632 static int bnxt_init_ctx_mem(struct bnxt *bp)
 633 {
 634         int rc = 0;
 635
 636         if (!(bp->fw_cap & BNXT_FW_CAP_ADV_FLOW_COUNTERS) ||
 637             !(BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp)) ||
 638             !BNXT_FLOW_XSTATS_EN(bp))
 639                 return 0;
 640
 641         rc = bnxt_hwrm_cfa_counter_qcaps(bp, &bp->flow_stat->max_fc);
 642         if (rc)
 643                 return rc;
 644
 645         rc = bnxt_init_fc_ctx_mem(bp);
 646
 647         return rc;
 648 }
 649
 650 static int bnxt_update_phy_setting(struct bnxt *bp)
 651 {
 652         struct rte_eth_link new;
 653         int rc;
 654
 655         rc = bnxt_get_hwrm_link_config(bp, &new);
 656         if (rc) {
 657                 PMD_DRV_LOG(ERR, "Failed to get link settings\n");
 658                 return rc;
 659         }
 660
 661         /*
 662          * On BCM957508-N2100 adapters, FW will not allow any user other
 663          * than BMC to shutdown the port. bnxt_get_hwrm_link_config() call
 664          * always returns link up. Force phy update always in that case.
 665          */
 666         if (!new.link_status || IS_BNXT_DEV_957508_N2100(bp)) {
 667                 rc = bnxt_set_hwrm_link_config(bp, true);
 668                 if (rc) {
 669                         PMD_DRV_LOG(ERR, "Failed to update PHY settings\n");
 670                         return rc;
 671                 }
 672         }
 673
 674         return rc;
 675 }
 676
 677 static int bnxt_init_chip(struct bnxt *bp)
 678 {
 679         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(bp->eth_dev);
 680         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
 681         uint32_t intr_vector = 0;
 682         uint32_t queue_id, base = BNXT_MISC_VEC_ID;
 683         uint32_t vec = BNXT_MISC_VEC_ID;
 684         unsigned int i, j;
 685         int rc;
 686
 687         if (bp->eth_dev->data->mtu > RTE_ETHER_MTU) {
 688                 bp->eth_dev->data->dev_conf.rxmode.offloads |=
 689                         DEV_RX_OFFLOAD_JUMBO_FRAME;
 690                 bp->flags |= BNXT_FLAG_JUMBO;
 691         } else {
 692                 bp->eth_dev->data->dev_conf.rxmode.offloads &=
 693                         ~DEV_RX_OFFLOAD_JUMBO_FRAME;
 694                 bp->flags &= ~BNXT_FLAG_JUMBO;
 695         }
 696
 697         /* THOR does not support ring groups.
 698          * But we will use the array to save RSS context IDs.
 699          */
 700         if (BNXT_CHIP_THOR(bp))
 701                 bp->max_ring_grps = BNXT_MAX_RSS_CTXTS_THOR;
 702
 703         rc = bnxt_alloc_all_hwrm_stat_ctxs(bp);
 704         if (rc) {
 705                 PMD_DRV_LOG(ERR, "HWRM stat ctx alloc failure rc: %x\n", rc);
 706                 goto err_out;
 707         }
 708
 709         rc = bnxt_alloc_hwrm_rings(bp);
 710         if (rc) {
 711                 PMD_DRV_LOG(ERR, "HWRM ring alloc failure rc: %x\n", rc);
 712                 goto err_out;
 713         }
 714
 715         rc = bnxt_alloc_all_hwrm_ring_grps(bp);
 716         if (rc) {
 717                 PMD_DRV_LOG(ERR, "HWRM ring grp alloc failure: %x\n", rc);
 718                 goto err_out;
 719         }
 720
 721         if (!(bp->vnic_cap_flags & BNXT_VNIC_CAP_COS_CLASSIFY))
 722                 goto skip_cosq_cfg;
 723
 724         for (j = 0, i = 0; i < BNXT_COS_QUEUE_COUNT; i++) {
 725                 if (bp->rx_cos_queue[i].id != 0xff) {
 726                         struct bnxt_vnic_info *vnic = &bp->vnic_info[j++];
 727
 728                         if (!vnic) {
 729                                 PMD_DRV_LOG(ERR,
 730                                             "Num pools more than FW profile\n");
 731                                 rc = -EINVAL;
 732                                 goto err_out;
 733                         }
 734                         vnic->cos_queue_id = bp->rx_cos_queue[i].id;
 735                         bp->rx_cosq_cnt++;
 736                 }
 737         }
 738
 739 skip_cosq_cfg:
 740         rc = bnxt_mq_rx_configure(bp);
 741         if (rc) {
 742                 PMD_DRV_LOG(ERR, "MQ mode configure failure rc: %x\n", rc);
 743                 goto err_out;
 744         }
 745
 746         /* VNIC configuration */
 747         for (i = 0; i < bp->nr_vnics; i++) {
 748                 rc = bnxt_setup_one_vnic(bp, i);
 749                 if (rc)
 750                         goto err_out;
 751         }
 752
 753         rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, &bp->vnic_info[0], 0, NULL);
 754         if (rc) {
 755                 PMD_DRV_LOG(ERR,
 756                         "HWRM cfa l2 rx mask failure rc: %x\n", rc);
 757                 goto err_out;
 758         }
 759
 760         /* check and configure queue intr-vector mapping */
 761         if ((rte_intr_cap_multiple(intr_handle) ||
 762              !RTE_ETH_DEV_SRIOV(bp->eth_dev).active) &&
 763             bp->eth_dev->data->dev_conf.intr_conf.rxq != 0) {
 764                 intr_vector = bp->eth_dev->data->nb_rx_queues;
 765                 PMD_DRV_LOG(DEBUG, "intr_vector = %d\n", intr_vector);
 766                 if (intr_vector > bp->rx_cp_nr_rings) {
 767                         PMD_DRV_LOG(ERR, "At most %d intr queues supported",
 768                                         bp->rx_cp_nr_rings);
 769                         return -ENOTSUP;
 770                 }
 771                 rc = rte_intr_efd_enable(intr_handle, intr_vector);
 772                 if (rc)
 773                         return rc;
 774         }
 775
 776         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
 777                 intr_handle->intr_vec =
 778                         rte_zmalloc("intr_vec",
 779                                     bp->eth_dev->data->nb_rx_queues *
 780                                     sizeof(int), 0);
 781                 if (intr_handle->intr_vec == NULL) {
 782                         PMD_DRV_LOG(ERR, "Failed to allocate %d rx_queues"
 783                                 " intr_vec", bp->eth_dev->data->nb_rx_queues);
 784                         rc = -ENOMEM;
 785                         goto err_disable;
 786                 }
 787                 PMD_DRV_LOG(DEBUG, "intr_handle->intr_vec = %p "
 788                         "intr_handle->nb_efd = %d intr_handle->max_intr = %d\n",
 789                          intr_handle->intr_vec, intr_handle->nb_efd,
 790                         intr_handle->max_intr);
 791                 for (queue_id = 0; queue_id < bp->eth_dev->data->nb_rx_queues;
 792                      queue_id++) {
 793                         intr_handle->intr_vec[queue_id] =
 794                                                         vec + BNXT_RX_VEC_START;
 795                         if (vec < base + intr_handle->nb_efd - 1)
 796                                 vec++;
 797                 }
 798         }
 799
 800         /* enable uio/vfio intr/eventfd mapping */
 801         rc = rte_intr_enable(intr_handle);
 802 #ifndef RTE_EXEC_ENV_FREEBSD
 803         /* In FreeBSD OS, nic_uio driver does not support interrupts */
 804         if (rc)
 805                 goto err_free;
 806 #endif
 807
 808         rc = bnxt_update_phy_setting(bp);
 809         if (rc)
 810                 goto err_free;
 811
 812         bp->mark_table = rte_zmalloc("bnxt_mark_table", BNXT_MARK_TABLE_SZ, 0);
 813         if (!bp->mark_table)
 814                 PMD_DRV_LOG(ERR, "Allocation of mark table failed\n");
 815
 816         return 0;
 817
 818 err_free:
 819         rte_free(intr_handle->intr_vec);
 820 err_disable:
 821         rte_intr_efd_disable(intr_handle);
 822 err_out:
 823         /* Some of the error status returned by FW may not be from errno.h */
 824         if (rc > 0)
 825                 rc = -EIO;
 826
 827         return rc;
 828 }
 829
 830 static int bnxt_shutdown_nic(struct bnxt *bp)
 831 {
 832         bnxt_free_all_hwrm_resources(bp);
 833         bnxt_free_all_filters(bp);
 834         bnxt_free_all_vnics(bp);
 835         return 0;
 836 }
 837
 838 /*
 839  * Device configuration and status function
 840  */
 841
 842 uint32_t bnxt_get_speed_capabilities(struct bnxt *bp)
 843 {
 844         uint32_t link_speed = bp->link_info->support_speeds;
 845         uint32_t speed_capa = 0;
 846
 847         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_100MB)
 848                 speed_capa |= ETH_LINK_SPEED_100M;
 849         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_100MBHD)
 850                 speed_capa |= ETH_LINK_SPEED_100M_HD;
 851         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_1GB)
 852                 speed_capa |= ETH_LINK_SPEED_1G;
 853         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_2_5GB)
 854                 speed_capa |= ETH_LINK_SPEED_2_5G;
 855         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_10GB)
 856                 speed_capa |= ETH_LINK_SPEED_10G;
 857         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_20GB)
 858                 speed_capa |= ETH_LINK_SPEED_20G;
 859         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_25GB)
 860                 speed_capa |= ETH_LINK_SPEED_25G;
 861         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_40GB)
 862                 speed_capa |= ETH_LINK_SPEED_40G;
 863         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_50GB)
 864                 speed_capa |= ETH_LINK_SPEED_50G;
 865         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_100GB)
 866                 speed_capa |= ETH_LINK_SPEED_100G;
 867         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_PAM4_SPEEDS_50G)
 868                 speed_capa |= ETH_LINK_SPEED_50G;
 869         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_PAM4_SPEEDS_100G)
 870                 speed_capa |= ETH_LINK_SPEED_100G;
 871         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_PAM4_SPEEDS_200G)
 872                 speed_capa |= ETH_LINK_SPEED_200G;
 873
 874         if (bp->link_info->auto_mode ==
 875             HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_MODE_NONE)
 876                 speed_capa |= ETH_LINK_SPEED_FIXED;
 877         else
 878                 speed_capa |= ETH_LINK_SPEED_AUTONEG;
 879
 880         return speed_capa;
 881 }
 882
 883 static int bnxt_dev_info_get_op(struct rte_eth_dev *eth_dev,
 884                                 struct rte_eth_dev_info *dev_info)
 885 {
 886         struct rte_pci_device *pdev = RTE_DEV_TO_PCI(eth_dev->device);
 887         struct bnxt *bp = eth_dev->data->dev_private;
 888         uint16_t max_vnics, i, j, vpool, vrxq;
 889         unsigned int max_rx_rings;
 890         int rc;
 891
 892         rc = is_bnxt_in_error(bp);
 893         if (rc)
 894                 return rc;
 895
 896         /* MAC Specifics */
 897         dev_info->max_mac_addrs = bp->max_l2_ctx;
 898         dev_info->max_hash_mac_addrs = 0;
 899
 900         /* PF/VF specifics */
 901         if (BNXT_PF(bp))
 902                 dev_info->max_vfs = pdev->max_vfs;
 903
 904         max_rx_rings = BNXT_MAX_RINGS(bp);
 905         /* For the sake of symmetry, max_rx_queues = max_tx_queues */
 906         dev_info->max_rx_queues = max_rx_rings;
 907         dev_info->max_tx_queues = max_rx_rings;
 908         dev_info->reta_size = bnxt_rss_hash_tbl_size(bp);
 909         dev_info->hash_key_size = 40;
 910         max_vnics = bp->max_vnics;
 911
 912         /* MTU specifics */
 913         dev_info->min_mtu = RTE_ETHER_MIN_MTU;
 914         dev_info->max_mtu = BNXT_MAX_MTU;
 915
 916         /* Fast path specifics */
 917         dev_info->min_rx_bufsize = 1;
 918         dev_info->max_rx_pktlen = BNXT_MAX_PKT_LEN;
 919
 920         dev_info->rx_offload_capa = BNXT_DEV_RX_OFFLOAD_SUPPORT;
 921         if (bp->flags & BNXT_FLAG_PTP_SUPPORTED)
 922                 dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_TIMESTAMP;
 923         dev_info->tx_queue_offload_capa = DEV_TX_OFFLOAD_MBUF_FAST_FREE;
 924         dev_info->tx_offload_capa = BNXT_DEV_TX_OFFLOAD_SUPPORT |
 925                                     dev_info->tx_queue_offload_capa;
 926         dev_info->flow_type_rss_offloads = BNXT_ETH_RSS_SUPPORT;
 927
 928         dev_info->speed_capa = bnxt_get_speed_capabilities(bp);
 929
 930         /* *INDENT-OFF* */
 931         dev_info->default_rxconf = (struct rte_eth_rxconf) {
 932                 .rx_thresh = {
 933                         .pthresh = 8,
 934                         .hthresh = 8,
 935                         .wthresh = 0,
 936                 },
 937                 .rx_free_thresh = 32,
 938                 .rx_drop_en = BNXT_DEFAULT_RX_DROP_EN,
 939         };
 940
 941         dev_info->default_txconf = (struct rte_eth_txconf) {
 942                 .tx_thresh = {
 943                         .pthresh = 32,
 944                         .hthresh = 0,
 945                         .wthresh = 0,
 946                 },
 947                 .tx_free_thresh = 32,
 948                 .tx_rs_thresh = 32,
 949         };
 950         eth_dev->data->dev_conf.intr_conf.lsc = 1;
 951
 952         eth_dev->data->dev_conf.intr_conf.rxq = 1;
 953         dev_info->rx_desc_lim.nb_min = BNXT_MIN_RING_DESC;
 954         dev_info->rx_desc_lim.nb_max = BNXT_MAX_RX_RING_DESC;
 955         dev_info->tx_desc_lim.nb_min = BNXT_MIN_RING_DESC;
 956         dev_info->tx_desc_lim.nb_max = BNXT_MAX_TX_RING_DESC;
 957
 958         if (BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp)) {
 959                 dev_info->switch_info.name = eth_dev->device->name;
 960                 dev_info->switch_info.domain_id = bp->switch_domain_id;
 961                 dev_info->switch_info.port_id =
 962                                 BNXT_PF(bp) ? BNXT_SWITCH_PORT_ID_PF :
 963                                     BNXT_SWITCH_PORT_ID_TRUSTED_VF;
 964         }
 965
 966         /* *INDENT-ON* */
 967
 968         /*
 969          * TODO: default_rxconf, default_txconf, rx_desc_lim, and tx_desc_lim
 970          *       need further investigation.
 971          */
 972
 973         /* VMDq resources */
 974         vpool = 64; /* ETH_64_POOLS */
 975         vrxq = 128; /* ETH_VMDQ_DCB_NUM_QUEUES */
 976         for (i = 0; i < 4; vpool >>= 1, i++) {
 977                 if (max_vnics > vpool) {
 978                         for (j = 0; j < 5; vrxq >>= 1, j++) {
 979                                 if (dev_info->max_rx_queues > vrxq) {
 980                                         if (vpool > vrxq)
 981                                                 vpool = vrxq;
 982                                         goto found;
 983                                 }
 984                         }
 985                         /* Not enough resources to support VMDq */
 986                         break;
 987                 }
 988         }
 989         /* Not enough resources to support VMDq */
 990         vpool = 0;
 991         vrxq = 0;
 992 found:
 993         dev_info->max_vmdq_pools = vpool;
 994         dev_info->vmdq_queue_num = vrxq;
 995
 996         dev_info->vmdq_pool_base = 0;
 997         dev_info->vmdq_queue_base = 0;
 998
 999         return 0;
1000 }
1001
1002 /* Configure the device based on the configuration provided */
1003 static int bnxt_dev_configure_op(struct rte_eth_dev *eth_dev)
1004 {
1005         struct bnxt *bp = eth_dev->data->dev_private;
1006         uint64_t rx_offloads = eth_dev->data->dev_conf.rxmode.offloads;
1007         int rc;
1008
1009         bp->rx_queues = (void *)eth_dev->data->rx_queues;
1010         bp->tx_queues = (void *)eth_dev->data->tx_queues;
1011         bp->tx_nr_rings = eth_dev->data->nb_tx_queues;
1012         bp->rx_nr_rings = eth_dev->data->nb_rx_queues;
1013
1014         rc = is_bnxt_in_error(bp);
1015         if (rc)
1016                 return rc;
1017
1018         if (BNXT_VF(bp) && (bp->flags & BNXT_FLAG_NEW_RM)) {
1019                 rc = bnxt_hwrm_check_vf_rings(bp);
1020                 if (rc) {
1021                         PMD_DRV_LOG(ERR, "HWRM insufficient resources\n");
1022                         return -ENOSPC;
1023                 }
1024
1025                 /* If a resource has already been allocated - in this case
1026                  * it is the async completion ring, free it. Reallocate it after
1027                  * resource reservation. This will ensure the resource counts
1028                  * are calculated correctly.
1029                  */
1030
1031                 pthread_mutex_lock(&bp->def_cp_lock);
1032
1033                 if (!BNXT_HAS_NQ(bp) && bp->async_cp_ring) {
1034                         bnxt_disable_int(bp);
1035                         bnxt_free_cp_ring(bp, bp->async_cp_ring);
1036                 }
1037
1038                 rc = bnxt_hwrm_func_reserve_vf_resc(bp, false);
1039                 if (rc) {
1040                         PMD_DRV_LOG(ERR, "HWRM resource alloc fail:%x\n", rc);
1041                         pthread_mutex_unlock(&bp->def_cp_lock);
1042                         return -ENOSPC;
1043                 }
1044
1045                 if (!BNXT_HAS_NQ(bp) && bp->async_cp_ring) {
1046                         rc = bnxt_alloc_async_cp_ring(bp);
1047                         if (rc) {
1048                                 pthread_mutex_unlock(&bp->def_cp_lock);
1049                                 return rc;
1050                         }
1051                         bnxt_enable_int(bp);
1052                 }
1053
1054                 pthread_mutex_unlock(&bp->def_cp_lock);
1055         } else {
1056                 /* legacy driver needs to get updated values */
1057                 rc = bnxt_hwrm_func_qcaps(bp);
1058                 if (rc) {
1059                         PMD_DRV_LOG(ERR, "hwrm func qcaps fail:%d\n", rc);
1060                         return rc;
1061                 }
1062         }
1063
1064         /* Inherit new configurations */
1065         if (eth_dev->data->nb_rx_queues > bp->max_rx_rings ||
1066             eth_dev->data->nb_tx_queues > bp->max_tx_rings ||
1067             eth_dev->data->nb_rx_queues + eth_dev->data->nb_tx_queues
1068                 + BNXT_NUM_ASYNC_CPR(bp) > bp->max_cp_rings ||
1069             eth_dev->data->nb_rx_queues + eth_dev->data->nb_tx_queues >
1070             bp->max_stat_ctx)
1071                 goto resource_error;
1072
1073         if (BNXT_HAS_RING_GRPS(bp) &&
1074             (uint32_t)(eth_dev->data->nb_rx_queues) > bp->max_ring_grps)
1075                 goto resource_error;
1076
1077         if (!(eth_dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_RSS) &&
1078             bp->max_vnics < eth_dev->data->nb_rx_queues)
1079                 goto resource_error;
1080
1081         bp->rx_cp_nr_rings = bp->rx_nr_rings;
1082         bp->tx_cp_nr_rings = bp->tx_nr_rings;
1083
1084         if (eth_dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG)
1085                 rx_offloads |= DEV_RX_OFFLOAD_RSS_HASH;
1086         eth_dev->data->dev_conf.rxmode.offloads = rx_offloads;
1087
1088         if (rx_offloads & DEV_RX_OFFLOAD_JUMBO_FRAME) {
1089                 eth_dev->data->mtu =
1090                         eth_dev->data->dev_conf.rxmode.max_rx_pkt_len -
1091                         RTE_ETHER_HDR_LEN - RTE_ETHER_CRC_LEN - VLAN_TAG_SIZE *
1092                         BNXT_NUM_VLANS;
1093                 bnxt_mtu_set_op(eth_dev, eth_dev->data->mtu);
1094         }
1095         return 0;
1096
1097 resource_error:
1098         PMD_DRV_LOG(ERR,
1099                     "Insufficient resources to support requested config\n");
1100         PMD_DRV_LOG(ERR,
1101                     "Num Queues Requested: Tx %d, Rx %d\n",
1102                     eth_dev->data->nb_tx_queues,
1103                     eth_dev->data->nb_rx_queues);
1104         PMD_DRV_LOG(ERR,
1105                     "MAX: TxQ %d, RxQ %d, CQ %d Stat %d, Grp %d, Vnic %d\n",
1106                     bp->max_tx_rings, bp->max_rx_rings, bp->max_cp_rings,
1107                     bp->max_stat_ctx, bp->max_ring_grps, bp->max_vnics);
1108         return -ENOSPC;
1109 }
1110
1111 void bnxt_print_link_info(struct rte_eth_dev *eth_dev)
1112 {
1113         struct rte_eth_link *link = &eth_dev->data->dev_link;
1114
1115         if (link->link_status)
1116                 PMD_DRV_LOG(INFO, "Port %d Link Up - speed %u Mbps - %s\n",
1117                         eth_dev->data->port_id,
1118                         (uint32_t)link->link_speed,
1119                         (link->link_duplex == ETH_LINK_FULL_DUPLEX) ?
1120                         ("full-duplex") : ("half-duplex\n"));
1121         else
1122                 PMD_DRV_LOG(INFO, "Port %d Link Down\n",
1123                         eth_dev->data->port_id);
1124 }
1125
1126 /*
1127  * Determine whether the current configuration requires support for scattered
1128  * receive; return 1 if scattered receive is required and 0 if not.
1129  */
1130 static int bnxt_scattered_rx(struct rte_eth_dev *eth_dev)
1131 {
1132         uint16_t buf_size;
1133         int i;
1134
1135         if (eth_dev->data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_SCATTER)
1136                 return 1;
1137
1138         for (i = 0; i < eth_dev->data->nb_rx_queues; i++) {
1139                 struct bnxt_rx_queue *rxq = eth_dev->data->rx_queues[i];
1140
1141                 buf_size = (uint16_t)(rte_pktmbuf_data_room_size(rxq->mb_pool) -
1142                                       RTE_PKTMBUF_HEADROOM);
1143                 if (eth_dev->data->dev_conf.rxmode.max_rx_pkt_len > buf_size)
1144                         return 1;
1145         }
1146         return 0;
1147 }
1148
1149 static eth_rx_burst_t
1150 bnxt_receive_function(struct rte_eth_dev *eth_dev)
1151 {
1152         struct bnxt *bp = eth_dev->data->dev_private;
1153
1154 #if defined(RTE_ARCH_X86) || defined(RTE_ARCH_ARM64)
1155 #ifndef RTE_LIBRTE_IEEE1588
1156         /*
1157          * Vector mode receive can be enabled only if scatter rx is not
1158          * in use and rx offloads are limited to VLAN stripping and
1159          * CRC stripping.
1160          */
1161         if (!eth_dev->data->scattered_rx &&
1162             !(eth_dev->data->dev_conf.rxmode.offloads &
1163               ~(DEV_RX_OFFLOAD_VLAN_STRIP |
1164                 DEV_RX_OFFLOAD_KEEP_CRC |
1165                 DEV_RX_OFFLOAD_JUMBO_FRAME |
1166                 DEV_RX_OFFLOAD_IPV4_CKSUM |
1167                 DEV_RX_OFFLOAD_UDP_CKSUM |
1168                 DEV_RX_OFFLOAD_TCP_CKSUM |
1169                 DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM |
1170                 DEV_RX_OFFLOAD_RSS_HASH |
1171                 DEV_RX_OFFLOAD_VLAN_FILTER)) &&
1172             !BNXT_TRUFLOW_EN(bp) && BNXT_NUM_ASYNC_CPR(bp)) {
1173                 PMD_DRV_LOG(INFO, "Using vector mode receive for port %d\n",
1174                             eth_dev->data->port_id);
1175                 bp->flags |= BNXT_FLAG_RX_VECTOR_PKT_MODE;
1176                 return bnxt_recv_pkts_vec;
1177         }
1178         PMD_DRV_LOG(INFO, "Vector mode receive disabled for port %d\n",
1179                     eth_dev->data->port_id);
1180         PMD_DRV_LOG(INFO,
1181                     "Port %d scatter: %d rx offload: %" PRIX64 "\n",
1182                     eth_dev->data->port_id,
1183                     eth_dev->data->scattered_rx,
1184                     eth_dev->data->dev_conf.rxmode.offloads);
1185 #endif
1186 #endif
1187         bp->flags &= ~BNXT_FLAG_RX_VECTOR_PKT_MODE;
1188         return bnxt_recv_pkts;
1189 }
1190
1191 static eth_tx_burst_t
1192 bnxt_transmit_function(__rte_unused struct rte_eth_dev *eth_dev)
1193 {
1194 #if defined(RTE_ARCH_X86) || defined(RTE_ARCH_ARM64)
1195 #ifndef RTE_LIBRTE_IEEE1588
1196         uint64_t offloads = eth_dev->data->dev_conf.txmode.offloads;
1197         struct bnxt *bp = eth_dev->data->dev_private;
1198
1199         /*
1200          * Vector mode transmit can be enabled only if not using scatter rx
1201          * or tx offloads.
1202          */
1203         if (!eth_dev->data->scattered_rx &&
1204             !(offloads & ~DEV_TX_OFFLOAD_MBUF_FAST_FREE) &&
1205             !BNXT_TRUFLOW_EN(bp)) {
1206                 PMD_DRV_LOG(INFO, "Using vector mode transmit for port %d\n",
1207                             eth_dev->data->port_id);
1208                 return bnxt_xmit_pkts_vec;
1209         }
1210         PMD_DRV_LOG(INFO, "Vector mode transmit disabled for port %d\n",
1211                     eth_dev->data->port_id);
1212         PMD_DRV_LOG(INFO,
1213                     "Port %d scatter: %d tx offload: %" PRIX64 "\n",
1214                     eth_dev->data->port_id,
1215                     eth_dev->data->scattered_rx,
1216                     offloads);
1217 #endif
1218 #endif
1219         return bnxt_xmit_pkts;
1220 }
1221
1222 static int bnxt_handle_if_change_status(struct bnxt *bp)
1223 {
1224         int rc;
1225
1226         /* Since fw has undergone a reset and lost all contexts,
1227          * set fatal flag to not issue hwrm during cleanup
1228          */
1229         bp->flags |= BNXT_FLAG_FATAL_ERROR;
1230         bnxt_uninit_resources(bp, true);
1231
1232         /* clear fatal flag so that re-init happens */
1233         bp->flags &= ~BNXT_FLAG_FATAL_ERROR;
1234         rc = bnxt_init_resources(bp, true);
1235
1236         bp->flags &= ~BNXT_FLAG_IF_CHANGE_HOT_FW_RESET_DONE;
1237
1238         return rc;
1239 }
1240
1241 static int bnxt_dev_start_op(struct rte_eth_dev *eth_dev)
1242 {
1243         struct bnxt *bp = eth_dev->data->dev_private;
1244         uint64_t rx_offloads = eth_dev->data->dev_conf.rxmode.offloads;
1245         int vlan_mask = 0;
1246         int rc, retry_cnt = BNXT_IF_CHANGE_RETRY_COUNT;
1247
1248         if (!eth_dev->data->nb_tx_queues || !eth_dev->data->nb_rx_queues) {
1249                 PMD_DRV_LOG(ERR, "Queues are not configured yet!\n");
1250                 return -EINVAL;
1251         }
1252
1253         if (bp->rx_cp_nr_rings > RTE_ETHDEV_QUEUE_STAT_CNTRS) {
1254                 PMD_DRV_LOG(ERR,
1255                         "RxQ cnt %d > CONFIG_RTE_ETHDEV_QUEUE_STAT_CNTRS %d\n",
1256                         bp->rx_cp_nr_rings, RTE_ETHDEV_QUEUE_STAT_CNTRS);
1257         }
1258
1259         do {
1260                 rc = bnxt_hwrm_if_change(bp, true);
1261                 if (rc == 0 || rc != -EAGAIN)
1262                         break;
1263
1264                 rte_delay_ms(BNXT_IF_CHANGE_RETRY_INTERVAL);
1265         } while (retry_cnt--);
1266
1267         if (rc)
1268                 return rc;
1269
1270         if (bp->flags & BNXT_FLAG_IF_CHANGE_HOT_FW_RESET_DONE) {
1271                 rc = bnxt_handle_if_change_status(bp);
1272                 if (rc)
1273                         return rc;
1274         }
1275
1276         bnxt_enable_int(bp);
1277
1278         rc = bnxt_init_chip(bp);
1279         if (rc)
1280                 goto error;
1281
1282         eth_dev->data->scattered_rx = bnxt_scattered_rx(eth_dev);
1283         eth_dev->data->dev_started = 1;
1284
1285         bnxt_link_update_op(eth_dev, 1);
1286
1287         if (rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER)
1288                 vlan_mask |= ETH_VLAN_FILTER_MASK;
1289         if (rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
1290                 vlan_mask |= ETH_VLAN_STRIP_MASK;
1291         rc = bnxt_vlan_offload_set_op(eth_dev, vlan_mask);
1292         if (rc)
1293                 goto error;
1294
1295         /* Initialize bnxt ULP port details */
1296         rc = bnxt_ulp_port_init(bp);
1297         if (rc)
1298                 goto error;
1299
1300         eth_dev->rx_pkt_burst = bnxt_receive_function(eth_dev);
1301         eth_dev->tx_pkt_burst = bnxt_transmit_function(eth_dev);
1302
1303         bnxt_schedule_fw_health_check(bp);
1304
1305         return 0;
1306
1307 error:
1308         bnxt_shutdown_nic(bp);
1309         bnxt_free_tx_mbufs(bp);
1310         bnxt_free_rx_mbufs(bp);
1311         bnxt_hwrm_if_change(bp, false);
1312         eth_dev->data->dev_started = 0;
1313         return rc;
1314 }
1315
1316 static int bnxt_dev_set_link_up_op(struct rte_eth_dev *eth_dev)
1317 {
1318         struct bnxt *bp = eth_dev->data->dev_private;
1319         int rc = 0;
1320
1321         if (!bp->link_info->link_up)
1322                 rc = bnxt_set_hwrm_link_config(bp, true);
1323         if (!rc)
1324                 eth_dev->data->dev_link.link_status = 1;
1325
1326         bnxt_print_link_info(eth_dev);
1327         return rc;
1328 }
1329
1330 static int bnxt_dev_set_link_down_op(struct rte_eth_dev *eth_dev)
1331 {
1332         struct bnxt *bp = eth_dev->data->dev_private;
1333
1334         eth_dev->data->dev_link.link_status = 0;
1335         bnxt_set_hwrm_link_config(bp, false);
1336         bp->link_info->link_up = 0;
1337
1338         return 0;
1339 }
1340
1341 static void bnxt_free_switch_domain(struct bnxt *bp)
1342 {
1343         if (bp->switch_domain_id)
1344                 rte_eth_switch_domain_free(bp->switch_domain_id);
1345 }
1346
1347 /* Unload the driver, release resources */
1348 static void bnxt_dev_stop_op(struct rte_eth_dev *eth_dev)
1349 {
1350         struct bnxt *bp = eth_dev->data->dev_private;
1351         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1352         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1353         struct rte_eth_link link;
1354
1355         eth_dev->data->dev_started = 0;
1356         eth_dev->data->scattered_rx = 0;
1357
1358         /* Prevent crashes when queues are still in use */
1359         eth_dev->rx_pkt_burst = &bnxt_dummy_recv_pkts;
1360         eth_dev->tx_pkt_burst = &bnxt_dummy_xmit_pkts;
1361
1362         bnxt_disable_int(bp);
1363
1364         /* disable uio/vfio intr/eventfd mapping */
1365         rte_intr_disable(intr_handle);
1366
1367         /* Stop the child representors for this device */
1368         bnxt_rep_stop_all(bp);
1369
1370         /* delete the bnxt ULP port details */
1371         bnxt_ulp_port_deinit(bp);
1372
1373         bnxt_cancel_fw_health_check(bp);
1374
1375         /* Do not bring link down during reset recovery */
1376         if (!is_bnxt_in_error(bp)) {
1377                 bnxt_dev_set_link_down_op(eth_dev);
1378                 /* Wait for link to be reset */
1379                 if (BNXT_SINGLE_PF(bp))
1380                         rte_delay_ms(500);
1381                 /* clear the recorded link status */
1382                 memset(&link, 0, sizeof(link));
1383                 rte_eth_linkstatus_set(eth_dev, &link);
1384         }
1385
1386         /* Clean queue intr-vector mapping */
1387         rte_intr_efd_disable(intr_handle);
1388         if (intr_handle->intr_vec != NULL) {
1389                 rte_free(intr_handle->intr_vec);
1390                 intr_handle->intr_vec = NULL;
1391         }
1392
1393         bnxt_hwrm_port_clr_stats(bp);
1394         bnxt_free_tx_mbufs(bp);
1395         bnxt_free_rx_mbufs(bp);
1396         /* Process any remaining notifications in default completion queue */
1397         bnxt_int_handler(eth_dev);
1398         bnxt_shutdown_nic(bp);
1399         bnxt_hwrm_if_change(bp, false);
1400
1401         rte_free(bp->mark_table);
1402         bp->mark_table = NULL;
1403
1404         bp->flags &= ~BNXT_FLAG_RX_VECTOR_PKT_MODE;
1405         bp->rx_cosq_cnt = 0;
1406         /* All filters are deleted on a port stop. */
1407         if (BNXT_FLOW_XSTATS_EN(bp))
1408                 bp->flow_stat->flow_count = 0;
1409 }
1410
1411 static int bnxt_dev_close_op(struct rte_eth_dev *eth_dev)
1412 {
1413         struct bnxt *bp = eth_dev->data->dev_private;
1414
1415         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1416                 return 0;
1417
1418         /* cancel the recovery handler before remove dev */
1419         rte_eal_alarm_cancel(bnxt_dev_reset_and_resume, (void *)bp);
1420         rte_eal_alarm_cancel(bnxt_dev_recover, (void *)bp);
1421         bnxt_cancel_fc_thread(bp);
1422
1423         if (eth_dev->data->dev_started)
1424                 bnxt_dev_stop_op(eth_dev);
1425
1426         bnxt_free_switch_domain(bp);
1427
1428         bnxt_uninit_resources(bp, false);
1429
1430         bnxt_free_leds_info(bp);
1431         bnxt_free_cos_queues(bp);
1432         bnxt_free_link_info(bp);
1433         bnxt_free_pf_info(bp);
1434         bnxt_free_parent_info(bp);
1435
1436         rte_memzone_free((const struct rte_memzone *)bp->tx_mem_zone);
1437         bp->tx_mem_zone = NULL;
1438         rte_memzone_free((const struct rte_memzone *)bp->rx_mem_zone);
1439         bp->rx_mem_zone = NULL;
1440
1441         bnxt_hwrm_free_vf_info(bp);
1442
1443         rte_free(bp->grp_info);
1444         bp->grp_info = NULL;
1445
1446         return 0;
1447 }
1448
1449 static void bnxt_mac_addr_remove_op(struct rte_eth_dev *eth_dev,
1450                                     uint32_t index)
1451 {
1452         struct bnxt *bp = eth_dev->data->dev_private;
1453         uint64_t pool_mask = eth_dev->data->mac_pool_sel[index];
1454         struct bnxt_vnic_info *vnic;
1455         struct bnxt_filter_info *filter, *temp_filter;
1456         uint32_t i;
1457
1458         if (is_bnxt_in_error(bp))
1459                 return;
1460
1461         /*
1462          * Loop through all VNICs from the specified filter flow pools to
1463          * remove the corresponding MAC addr filter
1464          */
1465         for (i = 0; i < bp->nr_vnics; i++) {
1466                 if (!(pool_mask & (1ULL << i)))
1467                         continue;
1468
1469                 vnic = &bp->vnic_info[i];
1470                 filter = STAILQ_FIRST(&vnic->filter);
1471                 while (filter) {
1472                         temp_filter = STAILQ_NEXT(filter, next);
1473                         if (filter->mac_index == index) {
1474                                 STAILQ_REMOVE(&vnic->filter, filter,
1475                                                 bnxt_filter_info, next);
1476                                 bnxt_hwrm_clear_l2_filter(bp, filter);
1477                                 bnxt_free_filter(bp, filter);
1478                         }
1479                         filter = temp_filter;
1480                 }
1481         }
1482 }
1483
1484 static int bnxt_add_mac_filter(struct bnxt *bp, struct bnxt_vnic_info *vnic,
1485                                struct rte_ether_addr *mac_addr, uint32_t index,
1486                                uint32_t pool)
1487 {
1488         struct bnxt_filter_info *filter;
1489         int rc = 0;
1490
1491         /* Attach requested MAC address to the new l2_filter */
1492         STAILQ_FOREACH(filter, &vnic->filter, next) {
1493                 if (filter->mac_index == index) {
1494                         PMD_DRV_LOG(DEBUG,
1495                                     "MAC addr already existed for pool %d\n",
1496                                     pool);
1497                         return 0;
1498                 }
1499         }
1500
1501         filter = bnxt_alloc_filter(bp);
1502         if (!filter) {
1503                 PMD_DRV_LOG(ERR, "L2 filter alloc failed\n");
1504                 return -ENODEV;
1505         }
1506
1507         /* bnxt_alloc_filter copies default MAC to filter->l2_addr. So,
1508          * if the MAC that's been programmed now is a different one, then,
1509          * copy that addr to filter->l2_addr
1510          */
1511         if (mac_addr)
1512                 memcpy(filter->l2_addr, mac_addr, RTE_ETHER_ADDR_LEN);
1513         filter->flags |= HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_OUTERMOST;
1514
1515         rc = bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id, filter);
1516         if (!rc) {
1517                 filter->mac_index = index;
1518                 if (filter->mac_index == 0)
1519                         STAILQ_INSERT_HEAD(&vnic->filter, filter, next);
1520                 else
1521                         STAILQ_INSERT_TAIL(&vnic->filter, filter, next);
1522         } else {
1523                 bnxt_free_filter(bp, filter);
1524         }
1525
1526         return rc;
1527 }
1528
1529 static int bnxt_mac_addr_add_op(struct rte_eth_dev *eth_dev,
1530                                 struct rte_ether_addr *mac_addr,
1531                                 uint32_t index, uint32_t pool)
1532 {
1533         struct bnxt *bp = eth_dev->data->dev_private;
1534         struct bnxt_vnic_info *vnic = &bp->vnic_info[pool];
1535         int rc = 0;
1536
1537         rc = is_bnxt_in_error(bp);
1538         if (rc)
1539                 return rc;
1540
1541         if (BNXT_VF(bp) & !BNXT_VF_IS_TRUSTED(bp)) {
1542                 PMD_DRV_LOG(ERR, "Cannot add MAC address to a VF interface\n");
1543                 return -ENOTSUP;
1544         }
1545
1546         if (!vnic) {
1547                 PMD_DRV_LOG(ERR, "VNIC not found for pool %d!\n", pool);
1548                 return -EINVAL;
1549         }
1550
1551         /* Filter settings will get applied when port is started */
1552         if (!eth_dev->data->dev_started)
1553                 return 0;
1554
1555         rc = bnxt_add_mac_filter(bp, vnic, mac_addr, index, pool);
1556
1557         return rc;
1558 }
1559
1560 int bnxt_link_update_op(struct rte_eth_dev *eth_dev, int wait_to_complete)
1561 {
1562         int rc = 0;
1563         struct bnxt *bp = eth_dev->data->dev_private;
1564         struct rte_eth_link new;
1565         int cnt = wait_to_complete ? BNXT_MAX_LINK_WAIT_CNT :
1566                         BNXT_MIN_LINK_WAIT_CNT;
1567
1568         rc = is_bnxt_in_error(bp);
1569         if (rc)
1570                 return rc;
1571
1572         memset(&new, 0, sizeof(new));
1573         do {
1574                 /* Retrieve link info from hardware */
1575                 rc = bnxt_get_hwrm_link_config(bp, &new);
1576                 if (rc) {
1577                         new.link_speed = ETH_LINK_SPEED_100M;
1578                         new.link_duplex = ETH_LINK_FULL_DUPLEX;
1579                         PMD_DRV_LOG(ERR,
1580                                 "Failed to retrieve link rc = 0x%x!\n", rc);
1581                         goto out;
1582                 }
1583
1584                 if (!wait_to_complete || new.link_status)
1585                         break;
1586
1587                 rte_delay_ms(BNXT_LINK_WAIT_INTERVAL);
1588         } while (cnt--);
1589
1590         /* Only single function PF can bring phy down.
1591          * When port is stopped, report link down for VF/MH/NPAR functions.
1592          */
1593         if (!BNXT_SINGLE_PF(bp) && !eth_dev->data->dev_started)
1594                 memset(&new, 0, sizeof(new));
1595
1596 out:
1597         /* Timed out or success */
1598         if (new.link_status != eth_dev->data->dev_link.link_status ||
1599         new.link_speed != eth_dev->data->dev_link.link_speed) {
1600                 rte_eth_linkstatus_set(eth_dev, &new);
1601
1602                 rte_eth_dev_callback_process(eth_dev,
1603                                              RTE_ETH_EVENT_INTR_LSC,
1604                                              NULL);
1605
1606                 bnxt_print_link_info(eth_dev);
1607         }
1608
1609         return rc;
1610 }
1611
1612 static int bnxt_promiscuous_enable_op(struct rte_eth_dev *eth_dev)
1613 {
1614         struct bnxt *bp = eth_dev->data->dev_private;
1615         struct bnxt_vnic_info *vnic;
1616         uint32_t old_flags;
1617         int rc;
1618
1619         rc = is_bnxt_in_error(bp);
1620         if (rc)
1621                 return rc;
1622
1623         /* Filter settings will get applied when port is started */
1624         if (!eth_dev->data->dev_started)
1625                 return 0;
1626
1627         if (bp->vnic_info == NULL)
1628                 return 0;
1629
1630         vnic = BNXT_GET_DEFAULT_VNIC(bp);
1631
1632         old_flags = vnic->flags;
1633         vnic->flags |= BNXT_VNIC_INFO_PROMISC;
1634         rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1635         if (rc != 0)
1636                 vnic->flags = old_flags;
1637
1638         return rc;
1639 }
1640
1641 static int bnxt_promiscuous_disable_op(struct rte_eth_dev *eth_dev)
1642 {
1643         struct bnxt *bp = eth_dev->data->dev_private;
1644         struct bnxt_vnic_info *vnic;
1645         uint32_t old_flags;
1646         int rc;
1647
1648         rc = is_bnxt_in_error(bp);
1649         if (rc)
1650                 return rc;
1651
1652         /* Filter settings will get applied when port is started */
1653         if (!eth_dev->data->dev_started)
1654                 return 0;
1655
1656         if (bp->vnic_info == NULL)
1657                 return 0;
1658
1659         vnic = BNXT_GET_DEFAULT_VNIC(bp);
1660
1661         old_flags = vnic->flags;
1662         vnic->flags &= ~BNXT_VNIC_INFO_PROMISC;
1663         rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1664         if (rc != 0)
1665                 vnic->flags = old_flags;
1666
1667         return rc;
1668 }
1669
1670 static int bnxt_allmulticast_enable_op(struct rte_eth_dev *eth_dev)
1671 {
1672         struct bnxt *bp = eth_dev->data->dev_private;
1673         struct bnxt_vnic_info *vnic;
1674         uint32_t old_flags;
1675         int rc;
1676
1677         rc = is_bnxt_in_error(bp);
1678         if (rc)
1679                 return rc;
1680
1681         /* Filter settings will get applied when port is started */
1682         if (!eth_dev->data->dev_started)
1683                 return 0;
1684
1685         if (bp->vnic_info == NULL)
1686                 return 0;
1687
1688         vnic = BNXT_GET_DEFAULT_VNIC(bp);
1689
1690         old_flags = vnic->flags;
1691         vnic->flags |= BNXT_VNIC_INFO_ALLMULTI;
1692         rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1693         if (rc != 0)
1694                 vnic->flags = old_flags;
1695
1696         return rc;
1697 }
1698
1699 static int bnxt_allmulticast_disable_op(struct rte_eth_dev *eth_dev)
1700 {
1701         struct bnxt *bp = eth_dev->data->dev_private;
1702         struct bnxt_vnic_info *vnic;
1703         uint32_t old_flags;
1704         int rc;
1705
1706         rc = is_bnxt_in_error(bp);
1707         if (rc)
1708                 return rc;
1709
1710         /* Filter settings will get applied when port is started */
1711         if (!eth_dev->data->dev_started)
1712                 return 0;
1713
1714         if (bp->vnic_info == NULL)
1715                 return 0;
1716
1717         vnic = BNXT_GET_DEFAULT_VNIC(bp);
1718
1719         old_flags = vnic->flags;
1720         vnic->flags &= ~BNXT_VNIC_INFO_ALLMULTI;
1721         rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1722         if (rc != 0)
1723                 vnic->flags = old_flags;
1724
1725         return rc;
1726 }
1727
1728 /* Return bnxt_rx_queue pointer corresponding to a given rxq. */
1729 static struct bnxt_rx_queue *bnxt_qid_to_rxq(struct bnxt *bp, uint16_t qid)
1730 {
1731         if (qid >= bp->rx_nr_rings)
1732                 return NULL;
1733
1734         return bp->eth_dev->data->rx_queues[qid];
1735 }
1736
1737 /* Return rxq corresponding to a given rss table ring/group ID. */
1738 static uint16_t bnxt_rss_to_qid(struct bnxt *bp, uint16_t fwr)
1739 {
1740         struct bnxt_rx_queue *rxq;
1741         unsigned int i;
1742
1743         if (!BNXT_HAS_RING_GRPS(bp)) {
1744                 for (i = 0; i < bp->rx_nr_rings; i++) {
1745                         rxq = bp->eth_dev->data->rx_queues[i];
1746                         if (rxq->rx_ring->rx_ring_struct->fw_ring_id == fwr)
1747                                 return rxq->index;
1748                 }
1749         } else {
1750                 for (i = 0; i < bp->rx_nr_rings; i++) {
1751                         if (bp->grp_info[i].fw_grp_id == fwr)
1752                                 return i;
1753                 }
1754         }
1755
1756         return INVALID_HW_RING_ID;
1757 }
1758
1759 static int bnxt_reta_update_op(struct rte_eth_dev *eth_dev,
1760                             struct rte_eth_rss_reta_entry64 *reta_conf,
1761                             uint16_t reta_size)
1762 {
1763         struct bnxt *bp = eth_dev->data->dev_private;
1764         struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
1765         struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp);
1766         uint16_t tbl_size = bnxt_rss_hash_tbl_size(bp);
1767         uint16_t idx, sft;
1768         int i, rc;
1769
1770         rc = is_bnxt_in_error(bp);
1771         if (rc)
1772                 return rc;
1773
1774         if (!vnic->rss_table)
1775                 return -EINVAL;
1776
1777         if (!(dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG))
1778                 return -EINVAL;
1779
1780         if (reta_size != tbl_size) {
1781                 PMD_DRV_LOG(ERR, "The configured hash table lookup size "
1782                         "(%d) must equal the size supported by the hardware "
1783                         "(%d)\n", reta_size, tbl_size);
1784                 return -EINVAL;
1785         }
1786
1787         for (i = 0; i < reta_size; i++) {
1788                 struct bnxt_rx_queue *rxq;
1789
1790                 idx = i / RTE_RETA_GROUP_SIZE;
1791                 sft = i % RTE_RETA_GROUP_SIZE;
1792
1793                 if (!(reta_conf[idx].mask & (1ULL << sft)))
1794                         continue;
1795
1796                 rxq = bnxt_qid_to_rxq(bp, reta_conf[idx].reta[sft]);
1797                 if (!rxq) {
1798                         PMD_DRV_LOG(ERR, "Invalid ring in reta_conf.\n");
1799                         return -EINVAL;
1800                 }
1801
1802                 if (BNXT_CHIP_THOR(bp)) {
1803                         vnic->rss_table[i * 2] =
1804                                 rxq->rx_ring->rx_ring_struct->fw_ring_id;
1805                         vnic->rss_table[i * 2 + 1] =
1806                                 rxq->cp_ring->cp_ring_struct->fw_ring_id;
1807                 } else {
1808                         vnic->rss_table[i] =
1809                             vnic->fw_grp_ids[reta_conf[idx].reta[sft]];
1810                 }
1811         }
1812
1813         bnxt_hwrm_vnic_rss_cfg(bp, vnic);
1814         return 0;
1815 }
1816
1817 static int bnxt_reta_query_op(struct rte_eth_dev *eth_dev,
1818                               struct rte_eth_rss_reta_entry64 *reta_conf,
1819                               uint16_t reta_size)
1820 {
1821         struct bnxt *bp = eth_dev->data->dev_private;
1822         struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp);
1823         uint16_t tbl_size = bnxt_rss_hash_tbl_size(bp);
1824         uint16_t idx, sft, i;
1825         int rc;
1826
1827         rc = is_bnxt_in_error(bp);
1828         if (rc)
1829                 return rc;
1830
1831         /* Retrieve from the default VNIC */
1832         if (!vnic)
1833                 return -EINVAL;
1834         if (!vnic->rss_table)
1835                 return -EINVAL;
1836
1837         if (reta_size != tbl_size) {
1838                 PMD_DRV_LOG(ERR, "The configured hash table lookup size "
1839                         "(%d) must equal the size supported by the hardware "
1840                         "(%d)\n", reta_size, tbl_size);
1841                 return -EINVAL;
1842         }
1843
1844         for (idx = 0, i = 0; i < reta_size; i++) {
1845                 idx = i / RTE_RETA_GROUP_SIZE;
1846                 sft = i % RTE_RETA_GROUP_SIZE;
1847
1848                 if (reta_conf[idx].mask & (1ULL << sft)) {
1849                         uint16_t qid;
1850
1851                         if (BNXT_CHIP_THOR(bp))
1852                                 qid = bnxt_rss_to_qid(bp,
1853                                                       vnic->rss_table[i * 2]);
1854                         else
1855                                 qid = bnxt_rss_to_qid(bp, vnic->rss_table[i]);
1856
1857                         if (qid == INVALID_HW_RING_ID) {
1858                                 PMD_DRV_LOG(ERR, "Inv. entry in rss table.\n");
1859                                 return -EINVAL;
1860                         }
1861                         reta_conf[idx].reta[sft] = qid;
1862                 }
1863         }
1864
1865         return 0;
1866 }
1867
1868 static int bnxt_rss_hash_update_op(struct rte_eth_dev *eth_dev,
1869                                    struct rte_eth_rss_conf *rss_conf)
1870 {
1871         struct bnxt *bp = eth_dev->data->dev_private;
1872         struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
1873         struct bnxt_vnic_info *vnic;
1874         int rc;
1875
1876         rc = is_bnxt_in_error(bp);
1877         if (rc)
1878                 return rc;
1879
1880         /*
1881          * If RSS enablement were different than dev_configure,
1882          * then return -EINVAL
1883          */
1884         if (dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG) {
1885                 if (!rss_conf->rss_hf)
1886                         PMD_DRV_LOG(ERR, "Hash type NONE\n");
1887         } else {
1888                 if (rss_conf->rss_hf & BNXT_ETH_RSS_SUPPORT)
1889                         return -EINVAL;
1890         }
1891
1892         bp->flags |= BNXT_FLAG_UPDATE_HASH;
1893         memcpy(&eth_dev->data->dev_conf.rx_adv_conf.rss_conf,
1894                rss_conf,
1895                sizeof(*rss_conf));
1896
1897         /* Update the default RSS VNIC(s) */
1898         vnic = BNXT_GET_DEFAULT_VNIC(bp);
1899         vnic->hash_type = bnxt_rte_to_hwrm_hash_types(rss_conf->rss_hf);
1900         vnic->hash_mode =
1901                 bnxt_rte_to_hwrm_hash_level(bp, rss_conf->rss_hf,
1902                                             ETH_RSS_LEVEL(rss_conf->rss_hf));
1903
1904         /*
1905          * If hashkey is not specified, use the previously configured
1906          * hashkey
1907          */
1908         if (!rss_conf->rss_key)
1909                 goto rss_config;
1910
1911         if (rss_conf->rss_key_len != HW_HASH_KEY_SIZE) {
1912                 PMD_DRV_LOG(ERR,
1913                             "Invalid hashkey length, should be 16 bytes\n");
1914                 return -EINVAL;
1915         }
1916         memcpy(vnic->rss_hash_key, rss_conf->rss_key, rss_conf->rss_key_len);
1917
1918 rss_config:
1919         bnxt_hwrm_vnic_rss_cfg(bp, vnic);
1920         return 0;
1921 }
1922
1923 static int bnxt_rss_hash_conf_get_op(struct rte_eth_dev *eth_dev,
1924                                      struct rte_eth_rss_conf *rss_conf)
1925 {
1926         struct bnxt *bp = eth_dev->data->dev_private;
1927         struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp);
1928         int len, rc;
1929         uint32_t hash_types;
1930
1931         rc = is_bnxt_in_error(bp);
1932         if (rc)
1933                 return rc;
1934
1935         /* RSS configuration is the same for all VNICs */
1936         if (vnic && vnic->rss_hash_key) {
1937                 if (rss_conf->rss_key) {
1938                         len = rss_conf->rss_key_len <= HW_HASH_KEY_SIZE ?
1939                               rss_conf->rss_key_len : HW_HASH_KEY_SIZE;
1940                         memcpy(rss_conf->rss_key, vnic->rss_hash_key, len);
1941                 }
1942
1943                 hash_types = vnic->hash_type;
1944                 rss_conf->rss_hf = 0;
1945                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV4) {
1946                         rss_conf->rss_hf |= ETH_RSS_IPV4;
1947                         hash_types &= ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV4;
1948                 }
1949                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV4) {
1950                         rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP;
1951                         hash_types &=
1952                                 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV4;
1953                 }
1954                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV4) {
1955                         rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
1956                         hash_types &=
1957                                 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV4;
1958                 }
1959                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6) {
1960                         rss_conf->rss_hf |= ETH_RSS_IPV6;
1961                         hash_types &= ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6;
1962                 }
1963                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV6) {
1964                         rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV6_TCP;
1965                         hash_types &=
1966                                 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV6;
1967                 }
1968                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV6) {
1969                         rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;
1970                         hash_types &=
1971                                 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV6;
1972                 }
1973
1974                 rss_conf->rss_hf |=
1975                         bnxt_hwrm_to_rte_rss_level(bp, vnic->hash_mode);
1976
1977                 if (hash_types) {
1978                         PMD_DRV_LOG(ERR,
1979                                 "Unknown RSS config from firmware (%08x), RSS disabled",
1980                                 vnic->hash_type);
1981                         return -ENOTSUP;
1982                 }
1983         } else {
1984                 rss_conf->rss_hf = 0;
1985         }
1986         return 0;
1987 }
1988
1989 static int bnxt_flow_ctrl_get_op(struct rte_eth_dev *dev,
1990                                struct rte_eth_fc_conf *fc_conf)
1991 {
1992         struct bnxt *bp = dev->data->dev_private;
1993         struct rte_eth_link link_info;
1994         int rc;
1995
1996         rc = is_bnxt_in_error(bp);
1997         if (rc)
1998                 return rc;
1999
2000         rc = bnxt_get_hwrm_link_config(bp, &link_info);
2001         if (rc)
2002                 return rc;
2003
2004         memset(fc_conf, 0, sizeof(*fc_conf));
2005         if (bp->link_info->auto_pause)
2006                 fc_conf->autoneg = 1;
2007         switch (bp->link_info->pause) {
2008         case 0:
2009                 fc_conf->mode = RTE_FC_NONE;
2010                 break;
2011         case HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_TX:
2012                 fc_conf->mode = RTE_FC_TX_PAUSE;
2013                 break;
2014         case HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_RX:
2015                 fc_conf->mode = RTE_FC_RX_PAUSE;
2016                 break;
2017         case (HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_TX |
2018                         HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_RX):
2019                 fc_conf->mode = RTE_FC_FULL;
2020                 break;
2021         }
2022         return 0;
2023 }
2024
2025 static int bnxt_flow_ctrl_set_op(struct rte_eth_dev *dev,
2026                                struct rte_eth_fc_conf *fc_conf)
2027 {
2028         struct bnxt *bp = dev->data->dev_private;
2029         int rc;
2030
2031         rc = is_bnxt_in_error(bp);
2032         if (rc)
2033                 return rc;
2034
2035         if (!BNXT_SINGLE_PF(bp) || BNXT_VF(bp)) {
2036                 PMD_DRV_LOG(ERR, "Flow Control Settings cannot be modified\n");
2037                 return -ENOTSUP;
2038         }
2039
2040         switch (fc_conf->mode) {
2041         case RTE_FC_NONE:
2042                 bp->link_info->auto_pause = 0;
2043                 bp->link_info->force_pause = 0;
2044                 break;
2045         case RTE_FC_RX_PAUSE:
2046                 if (fc_conf->autoneg) {
2047                         bp->link_info->auto_pause =
2048                                         HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_RX;
2049                         bp->link_info->force_pause = 0;
2050                 } else {
2051                         bp->link_info->auto_pause = 0;
2052                         bp->link_info->force_pause =
2053                                         HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_RX;
2054                 }
2055                 break;
2056         case RTE_FC_TX_PAUSE:
2057                 if (fc_conf->autoneg) {
2058                         bp->link_info->auto_pause =
2059                                         HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_TX;
2060                         bp->link_info->force_pause = 0;
2061                 } else {
2062                         bp->link_info->auto_pause = 0;
2063                         bp->link_info->force_pause =
2064                                         HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_TX;
2065                 }
2066                 break;
2067         case RTE_FC_FULL:
2068                 if (fc_conf->autoneg) {
2069                         bp->link_info->auto_pause =
2070                                         HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_TX |
2071                                         HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_RX;
2072                         bp->link_info->force_pause = 0;
2073                 } else {
2074                         bp->link_info->auto_pause = 0;
2075                         bp->link_info->force_pause =
2076                                         HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_TX |
2077                                         HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_RX;
2078                 }
2079                 break;
2080         }
2081         return bnxt_set_hwrm_link_config(bp, true);
2082 }
2083
2084 /* Add UDP tunneling port */
2085 static int
2086 bnxt_udp_tunnel_port_add_op(struct rte_eth_dev *eth_dev,
2087                          struct rte_eth_udp_tunnel *udp_tunnel)
2088 {
2089         struct bnxt *bp = eth_dev->data->dev_private;
2090         uint16_t tunnel_type = 0;
2091         int rc = 0;
2092
2093         rc = is_bnxt_in_error(bp);
2094         if (rc)
2095                 return rc;
2096
2097         switch (udp_tunnel->prot_type) {
2098         case RTE_TUNNEL_TYPE_VXLAN:
2099                 if (bp->vxlan_port_cnt) {
2100                         PMD_DRV_LOG(ERR, "Tunnel Port %d already programmed\n",
2101                                 udp_tunnel->udp_port);
2102                         if (bp->vxlan_port != udp_tunnel->udp_port) {
2103                                 PMD_DRV_LOG(ERR, "Only one port allowed\n");
2104                                 return -ENOSPC;
2105                         }
2106                         bp->vxlan_port_cnt++;
2107                         return 0;
2108                 }
2109                 tunnel_type =
2110                         HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_VXLAN;
2111                 bp->vxlan_port_cnt++;
2112                 break;
2113         case RTE_TUNNEL_TYPE_GENEVE:
2114                 if (bp->geneve_port_cnt) {
2115                         PMD_DRV_LOG(ERR, "Tunnel Port %d already programmed\n",
2116                                 udp_tunnel->udp_port);
2117                         if (bp->geneve_port != udp_tunnel->udp_port) {
2118                                 PMD_DRV_LOG(ERR, "Only one port allowed\n");
2119                                 return -ENOSPC;
2120                         }
2121                         bp->geneve_port_cnt++;
2122                         return 0;
2123                 }
2124                 tunnel_type =
2125                         HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_GENEVE;
2126                 bp->geneve_port_cnt++;
2127                 break;
2128         default:
2129                 PMD_DRV_LOG(ERR, "Tunnel type is not supported\n");
2130                 return -ENOTSUP;
2131         }
2132         rc = bnxt_hwrm_tunnel_dst_port_alloc(bp, udp_tunnel->udp_port,
2133                                              tunnel_type);
2134         return rc;
2135 }
2136
2137 static int
2138 bnxt_udp_tunnel_port_del_op(struct rte_eth_dev *eth_dev,
2139                          struct rte_eth_udp_tunnel *udp_tunnel)
2140 {
2141         struct bnxt *bp = eth_dev->data->dev_private;
2142         uint16_t tunnel_type = 0;
2143         uint16_t port = 0;
2144         int rc = 0;
2145
2146         rc = is_bnxt_in_error(bp);
2147         if (rc)
2148                 return rc;
2149
2150         switch (udp_tunnel->prot_type) {
2151         case RTE_TUNNEL_TYPE_VXLAN:
2152                 if (!bp->vxlan_port_cnt) {
2153                         PMD_DRV_LOG(ERR, "No Tunnel port configured yet\n");
2154                         return -EINVAL;
2155                 }
2156                 if (bp->vxlan_port != udp_tunnel->udp_port) {
2157                         PMD_DRV_LOG(ERR, "Req Port: %d. Configured port: %d\n",
2158                                 udp_tunnel->udp_port, bp->vxlan_port);
2159                         return -EINVAL;
2160                 }
2161                 if (--bp->vxlan_port_cnt)
2162                         return 0;
2163
2164                 tunnel_type =
2165                         HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN;
2166                 port = bp->vxlan_fw_dst_port_id;
2167                 break;
2168         case RTE_TUNNEL_TYPE_GENEVE:
2169                 if (!bp->geneve_port_cnt) {
2170                         PMD_DRV_LOG(ERR, "No Tunnel port configured yet\n");
2171                         return -EINVAL;
2172                 }
2173                 if (bp->geneve_port != udp_tunnel->udp_port) {
2174                         PMD_DRV_LOG(ERR, "Req Port: %d. Configured port: %d\n",
2175                                 udp_tunnel->udp_port, bp->geneve_port);
2176                         return -EINVAL;
2177                 }
2178                 if (--bp->geneve_port_cnt)
2179                         return 0;
2180
2181                 tunnel_type =
2182                         HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_GENEVE;
2183                 port = bp->geneve_fw_dst_port_id;
2184                 break;
2185         default:
2186                 PMD_DRV_LOG(ERR, "Tunnel type is not supported\n");
2187                 return -ENOTSUP;
2188         }
2189
2190         rc = bnxt_hwrm_tunnel_dst_port_free(bp, port, tunnel_type);
2191         return rc;
2192 }
2193
2194 static int bnxt_del_vlan_filter(struct bnxt *bp, uint16_t vlan_id)
2195 {
2196         struct bnxt_filter_info *filter;
2197         struct bnxt_vnic_info *vnic;
2198         int rc = 0;
2199         uint32_t chk = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN;
2200
2201         vnic = BNXT_GET_DEFAULT_VNIC(bp);
2202         filter = STAILQ_FIRST(&vnic->filter);
2203         while (filter) {
2204                 /* Search for this matching MAC+VLAN filter */
2205                 if (bnxt_vlan_filter_exists(bp, filter, chk, vlan_id)) {
2206                         /* Delete the filter */
2207                         rc = bnxt_hwrm_clear_l2_filter(bp, filter);
2208                         if (rc)
2209                                 return rc;
2210                         STAILQ_REMOVE(&vnic->filter, filter,
2211                                       bnxt_filter_info, next);
2212                         bnxt_free_filter(bp, filter);
2213                         PMD_DRV_LOG(INFO,
2214                                     "Deleted vlan filter for %d\n",
2215                                     vlan_id);
2216                         return 0;
2217                 }
2218                 filter = STAILQ_NEXT(filter, next);
2219         }
2220         return -ENOENT;
2221 }
2222
2223 static int bnxt_add_vlan_filter(struct bnxt *bp, uint16_t vlan_id)
2224 {
2225         struct bnxt_filter_info *filter;
2226         struct bnxt_vnic_info *vnic;
2227         int rc = 0;
2228         uint32_t en = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN |
2229                 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN_MASK;
2230         uint32_t chk = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN;
2231
2232         /* Implementation notes on the use of VNIC in this command:
2233          *
2234          * By default, these filters belong to default vnic for the function.
2235          * Once these filters are set up, only destination VNIC can be modified.
2236          * If the destination VNIC is not specified in this command,
2237          * then the HWRM shall only create an l2 context id.
2238          */
2239
2240         vnic = BNXT_GET_DEFAULT_VNIC(bp);
2241         filter = STAILQ_FIRST(&vnic->filter);
2242         /* Check if the VLAN has already been added */
2243         while (filter) {
2244                 if (bnxt_vlan_filter_exists(bp, filter, chk, vlan_id))
2245                         return -EEXIST;
2246
2247                 filter = STAILQ_NEXT(filter, next);
2248         }
2249
2250         /* No match found. Alloc a fresh filter and issue the L2_FILTER_ALLOC
2251          * command to create MAC+VLAN filter with the right flags, enables set.
2252          */
2253         filter = bnxt_alloc_filter(bp);
2254         if (!filter) {
2255                 PMD_DRV_LOG(ERR,
2256                             "MAC/VLAN filter alloc failed\n");
2257                 return -ENOMEM;
2258         }
2259         /* MAC + VLAN ID filter */
2260         /* If l2_ivlan == 0 and l2_ivlan_mask != 0, only
2261          * untagged packets are received
2262          *
2263          * If l2_ivlan != 0 and l2_ivlan_mask != 0, untagged
2264          * packets and only the programmed vlan's packets are received
2265          */
2266         filter->l2_ivlan = vlan_id;
2267         filter->l2_ivlan_mask = 0x0FFF;
2268         filter->enables |= en;
2269         filter->flags |= HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_OUTERMOST;
2270
2271         rc = bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id, filter);
2272         if (rc) {
2273                 /* Free the newly allocated filter as we were
2274                  * not able to create the filter in hardware.
2275                  */
2276                 bnxt_free_filter(bp, filter);
2277                 return rc;
2278         }
2279
2280         filter->mac_index = 0;
2281         /* Add this new filter to the list */
2282         if (vlan_id == 0)
2283                 STAILQ_INSERT_HEAD(&vnic->filter, filter, next);
2284         else
2285                 STAILQ_INSERT_TAIL(&vnic->filter, filter, next);
2286
2287         PMD_DRV_LOG(INFO,
2288                     "Added Vlan filter for %d\n", vlan_id);
2289         return rc;
2290 }
2291
2292 static int bnxt_vlan_filter_set_op(struct rte_eth_dev *eth_dev,
2293                 uint16_t vlan_id, int on)
2294 {
2295         struct bnxt *bp = eth_dev->data->dev_private;
2296         int rc;
2297
2298         rc = is_bnxt_in_error(bp);
2299         if (rc)
2300                 return rc;
2301
2302         if (!eth_dev->data->dev_started) {
2303                 PMD_DRV_LOG(ERR, "port must be started before setting vlan\n");
2304                 return -EINVAL;
2305         }
2306
2307         /* These operations apply to ALL existing MAC/VLAN filters */
2308         if (on)
2309                 return bnxt_add_vlan_filter(bp, vlan_id);
2310         else
2311                 return bnxt_del_vlan_filter(bp, vlan_id);
2312 }
2313
2314 static int bnxt_del_dflt_mac_filter(struct bnxt *bp,
2315                                     struct bnxt_vnic_info *vnic)
2316 {
2317         struct bnxt_filter_info *filter;
2318         int rc;
2319
2320         filter = STAILQ_FIRST(&vnic->filter);
2321         while (filter) {
2322                 if (filter->mac_index == 0 &&
2323                     !memcmp(filter->l2_addr, bp->mac_addr,
2324                             RTE_ETHER_ADDR_LEN)) {
2325                         rc = bnxt_hwrm_clear_l2_filter(bp, filter);
2326                         if (!rc) {
2327                                 STAILQ_REMOVE(&vnic->filter, filter,
2328                                               bnxt_filter_info, next);
2329                                 bnxt_free_filter(bp, filter);
2330                         }
2331                         return rc;
2332                 }
2333                 filter = STAILQ_NEXT(filter, next);
2334         }
2335         return 0;
2336 }
2337
2338 static int
2339 bnxt_config_vlan_hw_filter(struct bnxt *bp, uint64_t rx_offloads)
2340 {
2341         struct bnxt_vnic_info *vnic;
2342         unsigned int i;
2343         int rc;
2344
2345         vnic = BNXT_GET_DEFAULT_VNIC(bp);
2346         if (!(rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER)) {
2347                 /* Remove any VLAN filters programmed */
2348                 for (i = 0; i < RTE_ETHER_MAX_VLAN_ID; i++)
2349                         bnxt_del_vlan_filter(bp, i);
2350
2351                 rc = bnxt_add_mac_filter(bp, vnic, NULL, 0, 0);
2352                 if (rc)
2353                         return rc;
2354         } else {
2355                 /* Default filter will allow packets that match the
2356                  * dest mac. So, it has to be deleted, otherwise, we
2357                  * will endup receiving vlan packets for which the
2358                  * filter is not programmed, when hw-vlan-filter
2359                  * configuration is ON
2360                  */
2361                 bnxt_del_dflt_mac_filter(bp, vnic);
2362                 /* This filter will allow only untagged packets */
2363                 bnxt_add_vlan_filter(bp, 0);
2364         }
2365         PMD_DRV_LOG(DEBUG, "VLAN Filtering: %d\n",
2366                     !!(rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER));
2367
2368         return 0;
2369 }
2370
2371 static int bnxt_free_one_vnic(struct bnxt *bp, uint16_t vnic_id)
2372 {
2373         struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id];
2374         unsigned int i;
2375         int rc;
2376
2377         /* Destroy vnic filters and vnic */
2378         if (bp->eth_dev->data->dev_conf.rxmode.offloads &
2379             DEV_RX_OFFLOAD_VLAN_FILTER) {
2380                 for (i = 0; i < RTE_ETHER_MAX_VLAN_ID; i++)
2381                         bnxt_del_vlan_filter(bp, i);
2382         }
2383         bnxt_del_dflt_mac_filter(bp, vnic);
2384
2385         rc = bnxt_hwrm_vnic_free(bp, vnic);
2386         if (rc)
2387                 return rc;
2388
2389         rte_free(vnic->fw_grp_ids);
2390         vnic->fw_grp_ids = NULL;
2391
2392         vnic->rx_queue_cnt = 0;
2393
2394         return 0;
2395 }
2396
2397 static int
2398 bnxt_config_vlan_hw_stripping(struct bnxt *bp, uint64_t rx_offloads)
2399 {
2400         struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp);
2401         int rc;
2402
2403         /* Destroy, recreate and reconfigure the default vnic */
2404         rc = bnxt_free_one_vnic(bp, 0);
2405         if (rc)
2406                 return rc;
2407
2408         /* default vnic 0 */
2409         rc = bnxt_setup_one_vnic(bp, 0);
2410         if (rc)
2411                 return rc;
2412
2413         if (bp->eth_dev->data->dev_conf.rxmode.offloads &
2414             DEV_RX_OFFLOAD_VLAN_FILTER) {
2415                 rc = bnxt_add_vlan_filter(bp, 0);
2416                 if (rc)
2417                         return rc;
2418                 rc = bnxt_restore_vlan_filters(bp);
2419                 if (rc)
2420                         return rc;
2421         } else {
2422                 rc = bnxt_add_mac_filter(bp, vnic, NULL, 0, 0);
2423                 if (rc)
2424                         return rc;
2425         }
2426
2427         rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
2428         if (rc)
2429                 return rc;
2430
2431         PMD_DRV_LOG(DEBUG, "VLAN Strip Offload: %d\n",
2432                     !!(rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP));
2433
2434         return rc;
2435 }
2436
2437 static int
2438 bnxt_vlan_offload_set_op(struct rte_eth_dev *dev, int mask)
2439 {
2440         uint64_t rx_offloads = dev->data->dev_conf.rxmode.offloads;
2441         struct bnxt *bp = dev->data->dev_private;
2442         int rc;
2443
2444         rc = is_bnxt_in_error(bp);
2445         if (rc)
2446                 return rc;
2447
2448         /* Filter settings will get applied when port is started */
2449         if (!dev->data->dev_started)
2450                 return 0;
2451
2452         if (mask & ETH_VLAN_FILTER_MASK) {
2453                 /* Enable or disable VLAN filtering */
2454                 rc = bnxt_config_vlan_hw_filter(bp, rx_offloads);
2455                 if (rc)
2456                         return rc;
2457         }
2458
2459         if (mask & ETH_VLAN_STRIP_MASK) {
2460                 /* Enable or disable VLAN stripping */
2461                 rc = bnxt_config_vlan_hw_stripping(bp, rx_offloads);
2462                 if (rc)
2463                         return rc;
2464         }
2465
2466         if (mask & ETH_VLAN_EXTEND_MASK) {
2467                 if (rx_offloads & DEV_RX_OFFLOAD_VLAN_EXTEND)
2468                         PMD_DRV_LOG(DEBUG, "Extend VLAN supported\n");
2469                 else
2470                         PMD_DRV_LOG(INFO, "Extend VLAN unsupported\n");
2471         }
2472
2473         return 0;
2474 }
2475
2476 static int
2477 bnxt_vlan_tpid_set_op(struct rte_eth_dev *dev, enum rte_vlan_type vlan_type,
2478                       uint16_t tpid)
2479 {
2480         struct bnxt *bp = dev->data->dev_private;
2481         int qinq = dev->data->dev_conf.rxmode.offloads &
2482                    DEV_RX_OFFLOAD_VLAN_EXTEND;
2483
2484         if (vlan_type != ETH_VLAN_TYPE_INNER &&
2485             vlan_type != ETH_VLAN_TYPE_OUTER) {
2486                 PMD_DRV_LOG(ERR,
2487                             "Unsupported vlan type.");
2488                 return -EINVAL;
2489         }
2490         if (!qinq) {
2491                 PMD_DRV_LOG(ERR,
2492                             "QinQ not enabled. Needs to be ON as we can "
2493                             "accelerate only outer vlan\n");
2494                 return -EINVAL;
2495         }
2496
2497         if (vlan_type == ETH_VLAN_TYPE_OUTER) {
2498                 switch (tpid) {
2499                 case RTE_ETHER_TYPE_QINQ:
2500                         bp->outer_tpid_bd =
2501                                 TX_BD_LONG_CFA_META_VLAN_TPID_TPID88A8;
2502                                 break;
2503                 case RTE_ETHER_TYPE_VLAN:
2504                         bp->outer_tpid_bd =
2505                                 TX_BD_LONG_CFA_META_VLAN_TPID_TPID8100;
2506                                 break;
2507                 case RTE_ETHER_TYPE_QINQ1:
2508                         bp->outer_tpid_bd =
2509                                 TX_BD_LONG_CFA_META_VLAN_TPID_TPID9100;
2510                                 break;
2511                 case RTE_ETHER_TYPE_QINQ2:
2512                         bp->outer_tpid_bd =
2513                                 TX_BD_LONG_CFA_META_VLAN_TPID_TPID9200;
2514                                 break;
2515                 case RTE_ETHER_TYPE_QINQ3:
2516                         bp->outer_tpid_bd =
2517                                  TX_BD_LONG_CFA_META_VLAN_TPID_TPID9300;
2518                                 break;
2519                 default:
2520                         PMD_DRV_LOG(ERR, "Invalid TPID: %x\n", tpid);
2521                         return -EINVAL;
2522                 }
2523                 bp->outer_tpid_bd |= tpid;
2524                 PMD_DRV_LOG(INFO, "outer_tpid_bd = %x\n", bp->outer_tpid_bd);
2525         } else if (vlan_type == ETH_VLAN_TYPE_INNER) {
2526                 PMD_DRV_LOG(ERR,
2527                             "Can accelerate only outer vlan in QinQ\n");
2528                 return -EINVAL;
2529         }
2530
2531         return 0;
2532 }
2533
2534 static int
2535 bnxt_set_default_mac_addr_op(struct rte_eth_dev *dev,
2536                              struct rte_ether_addr *addr)
2537 {
2538         struct bnxt *bp = dev->data->dev_private;
2539         /* Default Filter is tied to VNIC 0 */
2540         struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp);
2541         int rc;
2542
2543         rc = is_bnxt_in_error(bp);
2544         if (rc)
2545                 return rc;
2546
2547         if (BNXT_VF(bp) && !BNXT_VF_IS_TRUSTED(bp))
2548                 return -EPERM;
2549
2550         if (rte_is_zero_ether_addr(addr))
2551                 return -EINVAL;
2552
2553         /* Filter settings will get applied when port is started */
2554         if (!dev->data->dev_started)
2555                 return 0;
2556
2557         /* Check if the requested MAC is already added */
2558         if (memcmp(addr, bp->mac_addr, RTE_ETHER_ADDR_LEN) == 0)
2559                 return 0;
2560
2561         /* Destroy filter and re-create it */
2562         bnxt_del_dflt_mac_filter(bp, vnic);
2563
2564         memcpy(bp->mac_addr, addr, RTE_ETHER_ADDR_LEN);
2565         if (dev->data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_VLAN_FILTER) {
2566                 /* This filter will allow only untagged packets */
2567                 rc = bnxt_add_vlan_filter(bp, 0);
2568         } else {
2569                 rc = bnxt_add_mac_filter(bp, vnic, addr, 0, 0);
2570         }
2571
2572         PMD_DRV_LOG(DEBUG, "Set MAC addr\n");
2573         return rc;
2574 }
2575
2576 static int
2577 bnxt_dev_set_mc_addr_list_op(struct rte_eth_dev *eth_dev,
2578                           struct rte_ether_addr *mc_addr_set,
2579                           uint32_t nb_mc_addr)
2580 {
2581         struct bnxt *bp = eth_dev->data->dev_private;
2582         char *mc_addr_list = (char *)mc_addr_set;
2583         struct bnxt_vnic_info *vnic;
2584         uint32_t off = 0, i = 0;
2585         int rc;
2586
2587         rc = is_bnxt_in_error(bp);
2588         if (rc)
2589                 return rc;
2590
2591         vnic = BNXT_GET_DEFAULT_VNIC(bp);
2592
2593         if (nb_mc_addr > BNXT_MAX_MC_ADDRS) {
2594                 vnic->flags |= BNXT_VNIC_INFO_ALLMULTI;
2595                 goto allmulti;
2596         }
2597
2598         /* TODO Check for Duplicate mcast addresses */
2599         vnic->flags &= ~BNXT_VNIC_INFO_ALLMULTI;
2600         for (i = 0; i < nb_mc_addr; i++) {
2601                 memcpy(vnic->mc_list + off, &mc_addr_list[i],
2602                         RTE_ETHER_ADDR_LEN);
2603                 off += RTE_ETHER_ADDR_LEN;
2604         }
2605
2606         vnic->mc_addr_cnt = i;
2607         if (vnic->mc_addr_cnt)
2608                 vnic->flags |= BNXT_VNIC_INFO_MCAST;
2609         else
2610                 vnic->flags &= ~BNXT_VNIC_INFO_MCAST;
2611
2612 allmulti:
2613         return bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
2614 }
2615
2616 static int
2617 bnxt_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size)
2618 {
2619         struct bnxt *bp = dev->data->dev_private;
2620         uint8_t fw_major = (bp->fw_ver >> 24) & 0xff;
2621         uint8_t fw_minor = (bp->fw_ver >> 16) & 0xff;
2622         uint8_t fw_updt = (bp->fw_ver >> 8) & 0xff;
2623         uint8_t fw_rsvd = bp->fw_ver & 0xff;
2624         int ret;
2625
2626         ret = snprintf(fw_version, fw_size, "%d.%d.%d.%d",
2627                         fw_major, fw_minor, fw_updt, fw_rsvd);
2628
2629         ret += 1; /* add the size of '\0' */
2630         if (fw_size < (uint32_t)ret)
2631                 return ret;
2632         else
2633                 return 0;
2634 }
2635
2636 static void
2637 bnxt_rxq_info_get_op(struct rte_eth_dev *dev, uint16_t queue_id,
2638         struct rte_eth_rxq_info *qinfo)
2639 {
2640         struct bnxt *bp = dev->data->dev_private;
2641         struct bnxt_rx_queue *rxq;
2642
2643         if (is_bnxt_in_error(bp))
2644                 return;
2645
2646         rxq = dev->data->rx_queues[queue_id];
2647
2648         qinfo->mp = rxq->mb_pool;
2649         qinfo->scattered_rx = dev->data->scattered_rx;
2650         qinfo->nb_desc = rxq->nb_rx_desc;
2651
2652         qinfo->conf.rx_free_thresh = rxq->rx_free_thresh;
2653         qinfo->conf.rx_drop_en = rxq->drop_en;
2654         qinfo->conf.rx_deferred_start = rxq->rx_deferred_start;
2655         qinfo->conf.offloads = dev->data->dev_conf.rxmode.offloads;
2656 }
2657
2658 static void
2659 bnxt_txq_info_get_op(struct rte_eth_dev *dev, uint16_t queue_id,
2660         struct rte_eth_txq_info *qinfo)
2661 {
2662         struct bnxt *bp = dev->data->dev_private;
2663         struct bnxt_tx_queue *txq;
2664
2665         if (is_bnxt_in_error(bp))
2666                 return;
2667
2668         txq = dev->data->tx_queues[queue_id];
2669
2670         qinfo->nb_desc = txq->nb_tx_desc;
2671
2672         qinfo->conf.tx_thresh.pthresh = txq->pthresh;
2673         qinfo->conf.tx_thresh.hthresh = txq->hthresh;
2674         qinfo->conf.tx_thresh.wthresh = txq->wthresh;
2675
2676         qinfo->conf.tx_free_thresh = txq->tx_free_thresh;
2677         qinfo->conf.tx_rs_thresh = 0;
2678         qinfo->conf.tx_deferred_start = txq->tx_deferred_start;
2679         qinfo->conf.offloads = txq->offloads;
2680 }
2681
2682 static const struct {
2683         eth_rx_burst_t pkt_burst;
2684         const char *info;
2685 } bnxt_rx_burst_info[] = {
2686         {bnxt_recv_pkts,        "Scalar"},
2687 #if defined(RTE_ARCH_X86)
2688         {bnxt_recv_pkts_vec,    "Vector SSE"},
2689 #elif defined(RTE_ARCH_ARM64)
2690         {bnxt_recv_pkts_vec,    "Vector Neon"},
2691 #endif
2692 };
2693
2694 static int
2695 bnxt_rx_burst_mode_get(struct rte_eth_dev *dev, __rte_unused uint16_t queue_id,
2696                        struct rte_eth_burst_mode *mode)
2697 {
2698         eth_rx_burst_t pkt_burst = dev->rx_pkt_burst;
2699         size_t i;
2700
2701         for (i = 0; i < RTE_DIM(bnxt_rx_burst_info); i++) {
2702                 if (pkt_burst == bnxt_rx_burst_info[i].pkt_burst) {
2703                         snprintf(mode->info, sizeof(mode->info), "%s",
2704                                  bnxt_rx_burst_info[i].info);
2705                         return 0;
2706                 }
2707         }
2708
2709         return -EINVAL;
2710 }
2711
2712 static const struct {
2713         eth_tx_burst_t pkt_burst;
2714         const char *info;
2715 } bnxt_tx_burst_info[] = {
2716         {bnxt_xmit_pkts,        "Scalar"},
2717 #if defined(RTE_ARCH_X86)
2718         {bnxt_xmit_pkts_vec,    "Vector SSE"},
2719 #elif defined(RTE_ARCH_ARM64)
2720         {bnxt_xmit_pkts_vec,    "Vector Neon"},
2721 #endif
2722 };
2723
2724 static int
2725 bnxt_tx_burst_mode_get(struct rte_eth_dev *dev, __rte_unused uint16_t queue_id,
2726                        struct rte_eth_burst_mode *mode)
2727 {
2728         eth_tx_burst_t pkt_burst = dev->tx_pkt_burst;
2729         size_t i;
2730
2731         for (i = 0; i < RTE_DIM(bnxt_tx_burst_info); i++) {
2732                 if (pkt_burst == bnxt_tx_burst_info[i].pkt_burst) {
2733                         snprintf(mode->info, sizeof(mode->info), "%s",
2734                                  bnxt_tx_burst_info[i].info);
2735                         return 0;
2736                 }
2737         }
2738
2739         return -EINVAL;
2740 }
2741
2742 int bnxt_mtu_set_op(struct rte_eth_dev *eth_dev, uint16_t new_mtu)
2743 {
2744         struct bnxt *bp = eth_dev->data->dev_private;
2745         uint32_t new_pkt_size;
2746         uint32_t rc = 0;
2747         uint32_t i;
2748
2749         rc = is_bnxt_in_error(bp);
2750         if (rc)
2751                 return rc;
2752
2753         /* Exit if receive queues are not configured yet */
2754         if (!eth_dev->data->nb_rx_queues)
2755                 return rc;
2756
2757         new_pkt_size = new_mtu + RTE_ETHER_HDR_LEN + RTE_ETHER_CRC_LEN +
2758                        VLAN_TAG_SIZE * BNXT_NUM_VLANS;
2759
2760         /*
2761          * Disallow any MTU change that would require scattered receive support
2762          * if it is not already enabled.
2763          */
2764         if (eth_dev->data->dev_started &&
2765             !eth_dev->data->scattered_rx &&
2766             (new_pkt_size >
2767              eth_dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM)) {
2768                 PMD_DRV_LOG(ERR,
2769                             "MTU change would require scattered rx support. ");
2770                 PMD_DRV_LOG(ERR, "Stop port before changing MTU.\n");
2771                 return -EINVAL;
2772         }
2773
2774         if (new_mtu > RTE_ETHER_MTU) {
2775                 bp->flags |= BNXT_FLAG_JUMBO;
2776                 bp->eth_dev->data->dev_conf.rxmode.offloads |=
2777                         DEV_RX_OFFLOAD_JUMBO_FRAME;
2778         } else {
2779                 bp->eth_dev->data->dev_conf.rxmode.offloads &=
2780                         ~DEV_RX_OFFLOAD_JUMBO_FRAME;
2781                 bp->flags &= ~BNXT_FLAG_JUMBO;
2782         }
2783
2784         /* Is there a change in mtu setting? */
2785         if (eth_dev->data->dev_conf.rxmode.max_rx_pkt_len == new_pkt_size)
2786                 return rc;
2787
2788         for (i = 0; i < bp->nr_vnics; i++) {
2789                 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
2790                 uint16_t size = 0;
2791
2792                 vnic->mru = BNXT_VNIC_MRU(new_mtu);
2793                 rc = bnxt_hwrm_vnic_cfg(bp, vnic);
2794                 if (rc)
2795                         break;
2796
2797                 size = rte_pktmbuf_data_room_size(bp->rx_queues[0]->mb_pool);
2798                 size -= RTE_PKTMBUF_HEADROOM;
2799
2800                 if (size < new_mtu) {
2801                         rc = bnxt_hwrm_vnic_plcmode_cfg(bp, vnic);
2802                         if (rc)
2803                                 return rc;
2804                 }
2805         }
2806
2807         if (!rc)
2808                 eth_dev->data->dev_conf.rxmode.max_rx_pkt_len = new_pkt_size;
2809
2810         PMD_DRV_LOG(INFO, "New MTU is %d\n", new_mtu);
2811
2812         return rc;
2813 }
2814
2815 static int
2816 bnxt_vlan_pvid_set_op(struct rte_eth_dev *dev, uint16_t pvid, int on)
2817 {
2818         struct bnxt *bp = dev->data->dev_private;
2819         uint16_t vlan = bp->vlan;
2820         int rc;
2821
2822         rc = is_bnxt_in_error(bp);
2823         if (rc)
2824                 return rc;
2825
2826         if (!BNXT_SINGLE_PF(bp) || BNXT_VF(bp)) {
2827                 PMD_DRV_LOG(ERR,
2828                         "PVID cannot be modified for this function\n");
2829                 return -ENOTSUP;
2830         }
2831         bp->vlan = on ? pvid : 0;
2832
2833         rc = bnxt_hwrm_set_default_vlan(bp, 0, 0);
2834         if (rc)
2835                 bp->vlan = vlan;
2836         return rc;
2837 }
2838
2839 static int
2840 bnxt_dev_led_on_op(struct rte_eth_dev *dev)
2841 {
2842         struct bnxt *bp = dev->data->dev_private;
2843         int rc;
2844
2845         rc = is_bnxt_in_error(bp);
2846         if (rc)
2847                 return rc;
2848
2849         return bnxt_hwrm_port_led_cfg(bp, true);
2850 }
2851
2852 static int
2853 bnxt_dev_led_off_op(struct rte_eth_dev *dev)
2854 {
2855         struct bnxt *bp = dev->data->dev_private;
2856         int rc;
2857
2858         rc = is_bnxt_in_error(bp);
2859         if (rc)
2860                 return rc;
2861
2862         return bnxt_hwrm_port_led_cfg(bp, false);
2863 }
2864
2865 static uint32_t
2866 bnxt_rx_queue_count_op(struct rte_eth_dev *dev, uint16_t rx_queue_id)
2867 {
2868         struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
2869         uint32_t desc = 0, raw_cons = 0, cons;
2870         struct bnxt_cp_ring_info *cpr;
2871         struct bnxt_rx_queue *rxq;
2872         struct rx_pkt_cmpl *rxcmp;
2873         int rc;
2874
2875         rc = is_bnxt_in_error(bp);
2876         if (rc)
2877                 return rc;
2878
2879         rxq = dev->data->rx_queues[rx_queue_id];
2880         cpr = rxq->cp_ring;
2881         raw_cons = cpr->cp_raw_cons;
2882
2883         while (1) {
2884                 cons = RING_CMP(cpr->cp_ring_struct, raw_cons);
2885                 rte_prefetch0(&cpr->cp_desc_ring[cons]);
2886                 rxcmp = (struct rx_pkt_cmpl *)&cpr->cp_desc_ring[cons];
2887
2888                 if (!CMP_VALID(rxcmp, raw_cons, cpr->cp_ring_struct)) {
2889                         break;
2890                 } else {
2891                         raw_cons++;
2892                         desc++;
2893                 }
2894         }
2895
2896         return desc;
2897 }
2898
2899 static int
2900 bnxt_rx_descriptor_status_op(void *rx_queue, uint16_t offset)
2901 {
2902         struct bnxt_rx_queue *rxq = (struct bnxt_rx_queue *)rx_queue;
2903         struct bnxt_rx_ring_info *rxr;
2904         struct bnxt_cp_ring_info *cpr;
2905         struct rte_mbuf *rx_buf;
2906         struct rx_pkt_cmpl *rxcmp;
2907         uint32_t cons, cp_cons;
2908         int rc;
2909
2910         if (!rxq)
2911                 return -EINVAL;
2912
2913         rc = is_bnxt_in_error(rxq->bp);
2914         if (rc)
2915                 return rc;
2916
2917         cpr = rxq->cp_ring;
2918         rxr = rxq->rx_ring;
2919
2920         if (offset >= rxq->nb_rx_desc)
2921                 return -EINVAL;
2922
2923         cons = RING_CMP(cpr->cp_ring_struct, offset);
2924         cp_cons = cpr->cp_raw_cons;
2925         rxcmp = (struct rx_pkt_cmpl *)&cpr->cp_desc_ring[cons];
2926
2927         if (cons > cp_cons) {
2928                 if (CMPL_VALID(rxcmp, cpr->valid))
2929                         return RTE_ETH_RX_DESC_DONE;
2930         } else {
2931                 if (CMPL_VALID(rxcmp, !cpr->valid))
2932                         return RTE_ETH_RX_DESC_DONE;
2933         }
2934         rx_buf = rxr->rx_buf_ring[cons];
2935         if (rx_buf == NULL || rx_buf == &rxq->fake_mbuf)
2936                 return RTE_ETH_RX_DESC_UNAVAIL;
2937
2938
2939         return RTE_ETH_RX_DESC_AVAIL;
2940 }
2941
2942 static int
2943 bnxt_tx_descriptor_status_op(void *tx_queue, uint16_t offset)
2944 {
2945         struct bnxt_tx_queue *txq = (struct bnxt_tx_queue *)tx_queue;
2946         struct bnxt_tx_ring_info *txr;
2947         struct bnxt_cp_ring_info *cpr;
2948         struct bnxt_sw_tx_bd *tx_buf;
2949         struct tx_pkt_cmpl *txcmp;
2950         uint32_t cons, cp_cons;
2951         int rc;
2952
2953         if (!txq)
2954                 return -EINVAL;
2955
2956         rc = is_bnxt_in_error(txq->bp);
2957         if (rc)
2958                 return rc;
2959
2960         cpr = txq->cp_ring;
2961         txr = txq->tx_ring;
2962
2963         if (offset >= txq->nb_tx_desc)
2964                 return -EINVAL;
2965
2966         cons = RING_CMP(cpr->cp_ring_struct, offset);
2967         txcmp = (struct tx_pkt_cmpl *)&cpr->cp_desc_ring[cons];
2968         cp_cons = cpr->cp_raw_cons;
2969
2970         if (cons > cp_cons) {
2971                 if (CMPL_VALID(txcmp, cpr->valid))
2972                         return RTE_ETH_TX_DESC_UNAVAIL;
2973         } else {
2974                 if (CMPL_VALID(txcmp, !cpr->valid))
2975                         return RTE_ETH_TX_DESC_UNAVAIL;
2976         }
2977         tx_buf = &txr->tx_buf_ring[cons];
2978         if (tx_buf->mbuf == NULL)
2979                 return RTE_ETH_TX_DESC_DONE;
2980
2981         return RTE_ETH_TX_DESC_FULL;
2982 }
2983
2984 static struct bnxt_filter_info *
2985 bnxt_match_and_validate_ether_filter(struct bnxt *bp,
2986                                 struct rte_eth_ethertype_filter *efilter,
2987                                 struct bnxt_vnic_info *vnic0,
2988                                 struct bnxt_vnic_info *vnic,
2989                                 int *ret)
2990 {
2991         struct bnxt_filter_info *mfilter = NULL;
2992         int match = 0;
2993         *ret = 0;
2994
2995         if (efilter->ether_type == RTE_ETHER_TYPE_IPV4 ||
2996                 efilter->ether_type == RTE_ETHER_TYPE_IPV6) {
2997                 PMD_DRV_LOG(ERR, "invalid ether_type(0x%04x) in"
2998                         " ethertype filter.", efilter->ether_type);
2999                 *ret = -EINVAL;
3000                 goto exit;
3001         }
3002         if (efilter->queue >= bp->rx_nr_rings) {
3003                 PMD_DRV_LOG(ERR, "Invalid queue %d\n", efilter->queue);
3004                 *ret = -EINVAL;
3005                 goto exit;
3006         }
3007
3008         vnic0 = BNXT_GET_DEFAULT_VNIC(bp);
3009         vnic = &bp->vnic_info[efilter->queue];
3010         if (vnic == NULL) {
3011                 PMD_DRV_LOG(ERR, "Invalid queue %d\n", efilter->queue);
3012                 *ret = -EINVAL;
3013                 goto exit;
3014         }
3015
3016         if (efilter->flags & RTE_ETHTYPE_FLAGS_DROP) {
3017                 STAILQ_FOREACH(mfilter, &vnic0->filter, next) {
3018                         if ((!memcmp(efilter->mac_addr.addr_bytes,
3019                                      mfilter->l2_addr, RTE_ETHER_ADDR_LEN) &&
3020                              mfilter->flags ==
3021                              HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_DROP &&
3022                              mfilter->ethertype == efilter->ether_type)) {
3023                                 match = 1;
3024                                 break;
3025                         }
3026                 }
3027         } else {
3028                 STAILQ_FOREACH(mfilter, &vnic->filter, next)
3029                         if ((!memcmp(efilter->mac_addr.addr_bytes,
3030                                      mfilter->l2_addr, RTE_ETHER_ADDR_LEN) &&
3031                              mfilter->ethertype == efilter->ether_type &&
3032                              mfilter->flags ==
3033                              HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_PATH_RX)) {
3034                                 match = 1;
3035                                 break;
3036                         }
3037         }
3038
3039         if (match)
3040                 *ret = -EEXIST;
3041
3042 exit:
3043         return mfilter;
3044 }
3045
3046 static int
3047 bnxt_ethertype_filter(struct rte_eth_dev *dev,
3048                         enum rte_filter_op filter_op,
3049                         void *arg)
3050 {
3051         struct bnxt *bp = dev->data->dev_private;
3052         struct rte_eth_ethertype_filter *efilter =
3053                         (struct rte_eth_ethertype_filter *)arg;
3054         struct bnxt_filter_info *bfilter, *filter1;
3055         struct bnxt_vnic_info *vnic, *vnic0;
3056         int ret;
3057
3058         if (filter_op == RTE_ETH_FILTER_NOP)
3059                 return 0;
3060
3061         if (arg == NULL) {
3062                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
3063                             filter_op);
3064                 return -EINVAL;
3065         }
3066
3067         vnic0 = BNXT_GET_DEFAULT_VNIC(bp);
3068         vnic = &bp->vnic_info[efilter->queue];
3069
3070         switch (filter_op) {
3071         case RTE_ETH_FILTER_ADD:
3072                 bnxt_match_and_validate_ether_filter(bp, efilter,
3073                                                         vnic0, vnic, &ret);
3074                 if (ret < 0)
3075                         return ret;
3076
3077                 bfilter = bnxt_get_unused_filter(bp);
3078                 if (bfilter == NULL) {
3079                         PMD_DRV_LOG(ERR,
3080                                 "Not enough resources for a new filter.\n");
3081                         return -ENOMEM;
3082                 }
3083                 bfilter->filter_type = HWRM_CFA_NTUPLE_FILTER;
3084                 memcpy(bfilter->l2_addr, efilter->mac_addr.addr_bytes,
3085                        RTE_ETHER_ADDR_LEN);
3086                 memcpy(bfilter->dst_macaddr, efilter->mac_addr.addr_bytes,
3087                        RTE_ETHER_ADDR_LEN);
3088                 bfilter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_MACADDR;
3089                 bfilter->ethertype = efilter->ether_type;
3090                 bfilter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
3091
3092                 filter1 = bnxt_get_l2_filter(bp, bfilter, vnic0);
3093                 if (filter1 == NULL) {
3094                         ret = -EINVAL;
3095                         goto cleanup;
3096                 }
3097                 bfilter->enables |=
3098                         HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID;
3099                 bfilter->fw_l2_filter_id = filter1->fw_l2_filter_id;
3100
3101                 bfilter->dst_id = vnic->fw_vnic_id;
3102
3103                 if (efilter->flags & RTE_ETHTYPE_FLAGS_DROP) {
3104                         bfilter->flags =
3105                                 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_DROP;
3106                 }
3107
3108                 ret = bnxt_hwrm_set_ntuple_filter(bp, bfilter->dst_id, bfilter);
3109                 if (ret)
3110                         goto cleanup;
3111                 STAILQ_INSERT_TAIL(&vnic->filter, bfilter, next);
3112                 break;
3113         case RTE_ETH_FILTER_DELETE:
3114                 filter1 = bnxt_match_and_validate_ether_filter(bp, efilter,
3115                                                         vnic0, vnic, &ret);
3116                 if (ret == -EEXIST) {
3117                         ret = bnxt_hwrm_clear_ntuple_filter(bp, filter1);
3118
3119                         STAILQ_REMOVE(&vnic->filter, filter1, bnxt_filter_info,
3120                                       next);
3121                         bnxt_free_filter(bp, filter1);
3122                 } else if (ret == 0) {
3123                         PMD_DRV_LOG(ERR, "No matching filter found\n");
3124                 }
3125                 break;
3126         default:
3127                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
3128                 ret = -EINVAL;
3129                 goto error;
3130         }
3131         return ret;
3132 cleanup:
3133         bnxt_free_filter(bp, bfilter);
3134 error:
3135         return ret;
3136 }
3137
3138 static inline int
3139 parse_ntuple_filter(struct bnxt *bp,
3140                     struct rte_eth_ntuple_filter *nfilter,
3141                     struct bnxt_filter_info *bfilter)
3142 {
3143         uint32_t en = 0;
3144
3145         if (nfilter->queue >= bp->rx_nr_rings) {
3146                 PMD_DRV_LOG(ERR, "Invalid queue %d\n", nfilter->queue);
3147                 return -EINVAL;
3148         }
3149
3150         switch (nfilter->dst_port_mask) {
3151         case UINT16_MAX:
3152                 bfilter->dst_port_mask = -1;
3153                 bfilter->dst_port = nfilter->dst_port;
3154                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT |
3155                         NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
3156                 break;
3157         default:
3158                 PMD_DRV_LOG(ERR, "invalid dst_port mask.");
3159                 return -EINVAL;
3160         }
3161
3162         bfilter->ip_addr_type = NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4;
3163         en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
3164
3165         switch (nfilter->proto_mask) {
3166         case UINT8_MAX:
3167                 if (nfilter->proto == 17) /* IPPROTO_UDP */
3168                         bfilter->ip_protocol = 17;
3169                 else if (nfilter->proto == 6) /* IPPROTO_TCP */
3170                         bfilter->ip_protocol = 6;
3171                 else
3172                         return -EINVAL;
3173                 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
3174                 break;
3175         default:
3176                 PMD_DRV_LOG(ERR, "invalid protocol mask.");
3177                 return -EINVAL;
3178         }
3179
3180         switch (nfilter->dst_ip_mask) {
3181         case UINT32_MAX:
3182                 bfilter->dst_ipaddr_mask[0] = -1;
3183                 bfilter->dst_ipaddr[0] = nfilter->dst_ip;
3184                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR |
3185                         NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
3186                 break;
3187         default:
3188                 PMD_DRV_LOG(ERR, "invalid dst_ip mask.");
3189                 return -EINVAL;
3190         }
3191
3192         switch (nfilter->src_ip_mask) {
3193         case UINT32_MAX:
3194                 bfilter->src_ipaddr_mask[0] = -1;
3195                 bfilter->src_ipaddr[0] = nfilter->src_ip;
3196                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR |
3197                         NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
3198                 break;
3199         default:
3200                 PMD_DRV_LOG(ERR, "invalid src_ip mask.");
3201                 return -EINVAL;
3202         }
3203
3204         switch (nfilter->src_port_mask) {
3205         case UINT16_MAX:
3206                 bfilter->src_port_mask = -1;
3207                 bfilter->src_port = nfilter->src_port;
3208                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT |
3209                         NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
3210                 break;
3211         default:
3212                 PMD_DRV_LOG(ERR, "invalid src_port mask.");
3213                 return -EINVAL;
3214         }
3215
3216         bfilter->enables = en;
3217         return 0;
3218 }
3219
3220 static struct bnxt_filter_info*
3221 bnxt_match_ntuple_filter(struct bnxt *bp,
3222                          struct bnxt_filter_info *bfilter,
3223                          struct bnxt_vnic_info **mvnic)
3224 {
3225         struct bnxt_filter_info *mfilter = NULL;
3226         int i;
3227
3228         for (i = bp->nr_vnics - 1; i >= 0; i--) {
3229                 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
3230                 STAILQ_FOREACH(mfilter, &vnic->filter, next) {
3231                         if (bfilter->src_ipaddr[0] == mfilter->src_ipaddr[0] &&
3232                             bfilter->src_ipaddr_mask[0] ==
3233                             mfilter->src_ipaddr_mask[0] &&
3234                             bfilter->src_port == mfilter->src_port &&
3235                             bfilter->src_port_mask == mfilter->src_port_mask &&
3236                             bfilter->dst_ipaddr[0] == mfilter->dst_ipaddr[0] &&
3237                             bfilter->dst_ipaddr_mask[0] ==
3238                             mfilter->dst_ipaddr_mask[0] &&
3239                             bfilter->dst_port == mfilter->dst_port &&
3240                             bfilter->dst_port_mask == mfilter->dst_port_mask &&
3241                             bfilter->flags == mfilter->flags &&
3242                             bfilter->enables == mfilter->enables) {
3243                                 if (mvnic)
3244                                         *mvnic = vnic;
3245                                 return mfilter;
3246                         }
3247                 }
3248         }
3249         return NULL;
3250 }
3251
3252 static int
3253 bnxt_cfg_ntuple_filter(struct bnxt *bp,
3254                        struct rte_eth_ntuple_filter *nfilter,
3255                        enum rte_filter_op filter_op)
3256 {
3257         struct bnxt_filter_info *bfilter, *mfilter, *filter1;
3258         struct bnxt_vnic_info *vnic, *vnic0, *mvnic;
3259         int ret;
3260
3261         if (nfilter->flags != RTE_5TUPLE_FLAGS) {
3262                 PMD_DRV_LOG(ERR, "only 5tuple is supported.");
3263                 return -EINVAL;
3264         }
3265
3266         if (nfilter->flags & RTE_NTUPLE_FLAGS_TCP_FLAG) {
3267                 PMD_DRV_LOG(ERR, "Ntuple filter: TCP flags not supported\n");
3268                 return -EINVAL;
3269         }
3270
3271         bfilter = bnxt_get_unused_filter(bp);
3272         if (bfilter == NULL) {
3273                 PMD_DRV_LOG(ERR,
3274                         "Not enough resources for a new filter.\n");
3275                 return -ENOMEM;
3276         }
3277         ret = parse_ntuple_filter(bp, nfilter, bfilter);
3278         if (ret < 0)
3279                 goto free_filter;
3280
3281         vnic = &bp->vnic_info[nfilter->queue];
3282         vnic0 = BNXT_GET_DEFAULT_VNIC(bp);
3283         filter1 = STAILQ_FIRST(&vnic0->filter);
3284         if (filter1 == NULL) {
3285                 ret = -EINVAL;
3286                 goto free_filter;
3287         }
3288
3289         bfilter->dst_id = vnic->fw_vnic_id;
3290         bfilter->fw_l2_filter_id = filter1->fw_l2_filter_id;
3291         bfilter->enables |=
3292                 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID;
3293         bfilter->ethertype = 0x800;
3294         bfilter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
3295
3296         mfilter = bnxt_match_ntuple_filter(bp, bfilter, &mvnic);
3297
3298         if (mfilter != NULL && filter_op == RTE_ETH_FILTER_ADD &&
3299             bfilter->dst_id == mfilter->dst_id) {
3300                 PMD_DRV_LOG(ERR, "filter exists.\n");
3301                 ret = -EEXIST;
3302                 goto free_filter;
3303         } else if (mfilter != NULL && filter_op == RTE_ETH_FILTER_ADD &&
3304                    bfilter->dst_id != mfilter->dst_id) {
3305                 mfilter->dst_id = vnic->fw_vnic_id;
3306                 ret = bnxt_hwrm_set_ntuple_filter(bp, mfilter->dst_id, mfilter);
3307                 STAILQ_REMOVE(&mvnic->filter, mfilter, bnxt_filter_info, next);
3308                 STAILQ_INSERT_TAIL(&vnic->filter, mfilter, next);
3309                 PMD_DRV_LOG(ERR, "filter with matching pattern exists.\n");
3310                 PMD_DRV_LOG(ERR, " Updated it to the new destination queue\n");
3311                 goto free_filter;
3312         }
3313         if (mfilter == NULL && filter_op == RTE_ETH_FILTER_DELETE) {
3314                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
3315                 ret = -ENOENT;
3316                 goto free_filter;
3317         }
3318
3319         if (filter_op == RTE_ETH_FILTER_ADD) {
3320                 bfilter->filter_type = HWRM_CFA_NTUPLE_FILTER;
3321                 ret = bnxt_hwrm_set_ntuple_filter(bp, bfilter->dst_id, bfilter);
3322                 if (ret)
3323                         goto free_filter;
3324                 STAILQ_INSERT_TAIL(&vnic->filter, bfilter, next);
3325         } else {
3326                 if (mfilter == NULL) {
3327                         /* This should not happen. But for Coverity! */
3328                         ret = -ENOENT;
3329                         goto free_filter;
3330                 }
3331                 ret = bnxt_hwrm_clear_ntuple_filter(bp, mfilter);
3332
3333                 STAILQ_REMOVE(&vnic->filter, mfilter, bnxt_filter_info, next);
3334                 bnxt_free_filter(bp, mfilter);
3335                 bnxt_free_filter(bp, bfilter);
3336         }
3337
3338         return 0;
3339 free_filter:
3340         bnxt_free_filter(bp, bfilter);
3341         return ret;
3342 }
3343
3344 static int
3345 bnxt_ntuple_filter(struct rte_eth_dev *dev,
3346                         enum rte_filter_op filter_op,
3347                         void *arg)
3348 {
3349         struct bnxt *bp = dev->data->dev_private;
3350         int ret;
3351
3352         if (filter_op == RTE_ETH_FILTER_NOP)
3353                 return 0;
3354
3355         if (arg == NULL) {
3356                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
3357                             filter_op);
3358                 return -EINVAL;
3359         }
3360
3361         switch (filter_op) {
3362         case RTE_ETH_FILTER_ADD:
3363                 ret = bnxt_cfg_ntuple_filter(bp,
3364                         (struct rte_eth_ntuple_filter *)arg,
3365                         filter_op);
3366                 break;
3367         case RTE_ETH_FILTER_DELETE:
3368                 ret = bnxt_cfg_ntuple_filter(bp,
3369                         (struct rte_eth_ntuple_filter *)arg,
3370                         filter_op);
3371                 break;
3372         default:
3373                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
3374                 ret = -EINVAL;
3375                 break;
3376         }
3377         return ret;
3378 }
3379
3380 static int
3381 bnxt_parse_fdir_filter(struct bnxt *bp,
3382                        struct rte_eth_fdir_filter *fdir,
3383                        struct bnxt_filter_info *filter)
3384 {
3385         enum rte_fdir_mode fdir_mode =
3386                 bp->eth_dev->data->dev_conf.fdir_conf.mode;
3387         struct bnxt_vnic_info *vnic0, *vnic;
3388         struct bnxt_filter_info *filter1;
3389         uint32_t en = 0;
3390         int i;
3391
3392         if (fdir_mode == RTE_FDIR_MODE_PERFECT_TUNNEL)
3393                 return -EINVAL;
3394
3395         filter->l2_ovlan = fdir->input.flow_ext.vlan_tci;
3396         en |= EM_FLOW_ALLOC_INPUT_EN_OVLAN_VID;
3397
3398         switch (fdir->input.flow_type) {
3399         case RTE_ETH_FLOW_IPV4:
3400         case RTE_ETH_FLOW_NONFRAG_IPV4_OTHER:
3401                 /* FALLTHROUGH */
3402                 filter->src_ipaddr[0] = fdir->input.flow.ip4_flow.src_ip;
3403                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
3404                 filter->dst_ipaddr[0] = fdir->input.flow.ip4_flow.dst_ip;
3405                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
3406                 filter->ip_protocol = fdir->input.flow.ip4_flow.proto;
3407                 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
3408                 filter->ip_addr_type =
3409                         NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4;
3410                 filter->src_ipaddr_mask[0] = 0xffffffff;
3411                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
3412                 filter->dst_ipaddr_mask[0] = 0xffffffff;
3413                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
3414                 filter->ethertype = 0x800;
3415                 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
3416                 break;
3417         case RTE_ETH_FLOW_NONFRAG_IPV4_TCP:
3418                 filter->src_port = fdir->input.flow.tcp4_flow.src_port;
3419                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT;
3420                 filter->dst_port = fdir->input.flow.tcp4_flow.dst_port;
3421                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT;
3422                 filter->dst_port_mask = 0xffff;
3423                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
3424                 filter->src_port_mask = 0xffff;
3425                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
3426                 filter->src_ipaddr[0] = fdir->input.flow.tcp4_flow.ip.src_ip;
3427                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
3428                 filter->dst_ipaddr[0] = fdir->input.flow.tcp4_flow.ip.dst_ip;
3429                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
3430                 filter->ip_protocol = 6;
3431                 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
3432                 filter->ip_addr_type =
3433                         NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4;
3434                 filter->src_ipaddr_mask[0] = 0xffffffff;
3435                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
3436                 filter->dst_ipaddr_mask[0] = 0xffffffff;
3437                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
3438                 filter->ethertype = 0x800;
3439                 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
3440                 break;
3441         case RTE_ETH_FLOW_NONFRAG_IPV4_UDP:
3442                 filter->src_port = fdir->input.flow.udp4_flow.src_port;
3443                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT;
3444                 filter->dst_port = fdir->input.flow.udp4_flow.dst_port;
3445                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT;
3446                 filter->dst_port_mask = 0xffff;
3447                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
3448                 filter->src_port_mask = 0xffff;
3449                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
3450                 filter->src_ipaddr[0] = fdir->input.flow.udp4_flow.ip.src_ip;
3451                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
3452                 filter->dst_ipaddr[0] = fdir->input.flow.udp4_flow.ip.dst_ip;
3453                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
3454                 filter->ip_protocol = 17;
3455                 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
3456                 filter->ip_addr_type =
3457                         NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4;
3458                 filter->src_ipaddr_mask[0] = 0xffffffff;
3459                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
3460                 filter->dst_ipaddr_mask[0] = 0xffffffff;
3461                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
3462                 filter->ethertype = 0x800;
3463                 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
3464                 break;
3465         case RTE_ETH_FLOW_IPV6:
3466         case RTE_ETH_FLOW_NONFRAG_IPV6_OTHER:
3467                 /* FALLTHROUGH */
3468                 filter->ip_addr_type =
3469                         NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV6;
3470                 filter->ip_protocol = fdir->input.flow.ipv6_flow.proto;
3471                 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
3472                 rte_memcpy(filter->src_ipaddr,
3473                            fdir->input.flow.ipv6_flow.src_ip, 16);
3474                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
3475                 rte_memcpy(filter->dst_ipaddr,
3476                            fdir->input.flow.ipv6_flow.dst_ip, 16);
3477                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
3478                 memset(filter->dst_ipaddr_mask, 0xff, 16);
3479                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
3480                 memset(filter->src_ipaddr_mask, 0xff, 16);
3481                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
3482                 filter->ethertype = 0x86dd;
3483                 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
3484                 break;
3485         case RTE_ETH_FLOW_NONFRAG_IPV6_TCP:
3486                 filter->src_port = fdir->input.flow.tcp6_flow.src_port;
3487                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT;
3488                 filter->dst_port = fdir->input.flow.tcp6_flow.dst_port;
3489                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT;
3490                 filter->dst_port_mask = 0xffff;
3491                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
3492                 filter->src_port_mask = 0xffff;
3493                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
3494                 filter->ip_addr_type =
3495                         NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV6;
3496                 filter->ip_protocol = fdir->input.flow.tcp6_flow.ip.proto;
3497                 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
3498                 rte_memcpy(filter->src_ipaddr,
3499                            fdir->input.flow.tcp6_flow.ip.src_ip, 16);
3500                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
3501                 rte_memcpy(filter->dst_ipaddr,
3502                            fdir->input.flow.tcp6_flow.ip.dst_ip, 16);
3503                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
3504                 memset(filter->dst_ipaddr_mask, 0xff, 16);
3505                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
3506                 memset(filter->src_ipaddr_mask, 0xff, 16);
3507                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
3508                 filter->ethertype = 0x86dd;
3509                 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
3510                 break;
3511         case RTE_ETH_FLOW_NONFRAG_IPV6_UDP:
3512                 filter->src_port = fdir->input.flow.udp6_flow.src_port;
3513                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT;
3514                 filter->dst_port = fdir->input.flow.udp6_flow.dst_port;
3515                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT;
3516                 filter->dst_port_mask = 0xffff;
3517                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
3518                 filter->src_port_mask = 0xffff;
3519                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
3520                 filter->ip_addr_type =
3521                         NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV6;
3522                 filter->ip_protocol = fdir->input.flow.udp6_flow.ip.proto;
3523                 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
3524                 rte_memcpy(filter->src_ipaddr,
3525                            fdir->input.flow.udp6_flow.ip.src_ip, 16);
3526                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
3527                 rte_memcpy(filter->dst_ipaddr,
3528                            fdir->input.flow.udp6_flow.ip.dst_ip, 16);
3529                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
3530                 memset(filter->dst_ipaddr_mask, 0xff, 16);
3531                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
3532                 memset(filter->src_ipaddr_mask, 0xff, 16);
3533                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
3534                 filter->ethertype = 0x86dd;
3535                 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
3536                 break;
3537         case RTE_ETH_FLOW_L2_PAYLOAD:
3538                 filter->ethertype = fdir->input.flow.l2_flow.ether_type;
3539                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
3540                 break;
3541         case RTE_ETH_FLOW_VXLAN:
3542                 if (fdir->action.behavior == RTE_ETH_FDIR_REJECT)
3543                         return -EINVAL;
3544                 filter->vni = fdir->input.flow.tunnel_flow.tunnel_id;
3545                 filter->tunnel_type =
3546                         CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN;
3547                 en |= HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_TUNNEL_TYPE;
3548                 break;
3549         case RTE_ETH_FLOW_NVGRE:
3550                 if (fdir->action.behavior == RTE_ETH_FDIR_REJECT)
3551                         return -EINVAL;
3552                 filter->vni = fdir->input.flow.tunnel_flow.tunnel_id;
3553                 filter->tunnel_type =
3554                         CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_NVGRE;
3555                 en |= HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_TUNNEL_TYPE;
3556                 break;
3557         case RTE_ETH_FLOW_UNKNOWN:
3558         case RTE_ETH_FLOW_RAW:
3559         case RTE_ETH_FLOW_FRAG_IPV4:
3560         case RTE_ETH_FLOW_NONFRAG_IPV4_SCTP:
3561         case RTE_ETH_FLOW_FRAG_IPV6:
3562         case RTE_ETH_FLOW_NONFRAG_IPV6_SCTP:
3563         case RTE_ETH_FLOW_IPV6_EX:
3564         case RTE_ETH_FLOW_IPV6_TCP_EX:
3565         case RTE_ETH_FLOW_IPV6_UDP_EX:
3566         case RTE_ETH_FLOW_GENEVE:
3567                 /* FALLTHROUGH */
3568         default:
3569                 return -EINVAL;
3570         }
3571
3572         vnic0 = BNXT_GET_DEFAULT_VNIC(bp);
3573         vnic = &bp->vnic_info[fdir->action.rx_queue];
3574         if (vnic == NULL) {
3575                 PMD_DRV_LOG(ERR, "Invalid queue %d\n", fdir->action.rx_queue);
3576                 return -EINVAL;
3577         }
3578
3579         if (fdir_mode == RTE_FDIR_MODE_PERFECT_MAC_VLAN) {
3580                 rte_memcpy(filter->dst_macaddr,
3581                         fdir->input.flow.mac_vlan_flow.mac_addr.addr_bytes, 6);
3582                         en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_MACADDR;
3583         }
3584
3585         if (fdir->action.behavior == RTE_ETH_FDIR_REJECT) {
3586                 filter->flags = HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_DROP;
3587                 filter1 = STAILQ_FIRST(&vnic0->filter);
3588                 //filter1 = bnxt_get_l2_filter(bp, filter, vnic0);
3589         } else {
3590                 filter->dst_id = vnic->fw_vnic_id;
3591                 for (i = 0; i < RTE_ETHER_ADDR_LEN; i++)
3592                         if (filter->dst_macaddr[i] == 0x00)
3593                                 filter1 = STAILQ_FIRST(&vnic0->filter);
3594                         else
3595                                 filter1 = bnxt_get_l2_filter(bp, filter, vnic);
3596         }
3597
3598         if (filter1 == NULL)
3599                 return -EINVAL;
3600
3601         en |= HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID;
3602         filter->fw_l2_filter_id = filter1->fw_l2_filter_id;
3603
3604         filter->enables = en;
3605
3606         return 0;
3607 }
3608
3609 static struct bnxt_filter_info *
3610 bnxt_match_fdir(struct bnxt *bp, struct bnxt_filter_info *nf,
3611                 struct bnxt_vnic_info **mvnic)
3612 {
3613         struct bnxt_filter_info *mf = NULL;
3614         int i;
3615
3616         for (i = bp->nr_vnics - 1; i >= 0; i--) {
3617                 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
3618
3619                 STAILQ_FOREACH(mf, &vnic->filter, next) {
3620                         if (mf->filter_type == nf->filter_type &&
3621                             mf->flags == nf->flags &&
3622                             mf->src_port == nf->src_port &&
3623                             mf->src_port_mask == nf->src_port_mask &&
3624                             mf->dst_port == nf->dst_port &&
3625                             mf->dst_port_mask == nf->dst_port_mask &&
3626                             mf->ip_protocol == nf->ip_protocol &&
3627                             mf->ip_addr_type == nf->ip_addr_type &&
3628                             mf->ethertype == nf->ethertype &&
3629                             mf->vni == nf->vni &&
3630                             mf->tunnel_type == nf->tunnel_type &&
3631                             mf->l2_ovlan == nf->l2_ovlan &&
3632                             mf->l2_ovlan_mask == nf->l2_ovlan_mask &&
3633                             mf->l2_ivlan == nf->l2_ivlan &&
3634                             mf->l2_ivlan_mask == nf->l2_ivlan_mask &&
3635                             !memcmp(mf->l2_addr, nf->l2_addr,
3636                                     RTE_ETHER_ADDR_LEN) &&
3637                             !memcmp(mf->l2_addr_mask, nf->l2_addr_mask,
3638                                     RTE_ETHER_ADDR_LEN) &&
3639                             !memcmp(mf->src_macaddr, nf->src_macaddr,
3640                                     RTE_ETHER_ADDR_LEN) &&
3641                             !memcmp(mf->dst_macaddr, nf->dst_macaddr,
3642                                     RTE_ETHER_ADDR_LEN) &&
3643                             !memcmp(mf->src_ipaddr, nf->src_ipaddr,
3644                                     sizeof(nf->src_ipaddr)) &&
3645                             !memcmp(mf->src_ipaddr_mask, nf->src_ipaddr_mask,
3646                                     sizeof(nf->src_ipaddr_mask)) &&
3647                             !memcmp(mf->dst_ipaddr, nf->dst_ipaddr,
3648                                     sizeof(nf->dst_ipaddr)) &&
3649                             !memcmp(mf->dst_ipaddr_mask, nf->dst_ipaddr_mask,
3650                                     sizeof(nf->dst_ipaddr_mask))) {
3651                                 if (mvnic)
3652                                         *mvnic = vnic;
3653                                 return mf;
3654                         }
3655                 }
3656         }
3657         return NULL;
3658 }
3659
3660 static int
3661 bnxt_fdir_filter(struct rte_eth_dev *dev,
3662                  enum rte_filter_op filter_op,
3663                  void *arg)
3664 {
3665         struct bnxt *bp = dev->data->dev_private;
3666         struct rte_eth_fdir_filter *fdir  = (struct rte_eth_fdir_filter *)arg;
3667         struct bnxt_filter_info *filter, *match;
3668         struct bnxt_vnic_info *vnic, *mvnic;
3669         int ret = 0, i;
3670
3671         if (filter_op == RTE_ETH_FILTER_NOP)
3672                 return 0;
3673
3674         if (arg == NULL && filter_op != RTE_ETH_FILTER_FLUSH)
3675                 return -EINVAL;
3676
3677         switch (filter_op) {
3678         case RTE_ETH_FILTER_ADD:
3679         case RTE_ETH_FILTER_DELETE:
3680                 /* FALLTHROUGH */
3681                 filter = bnxt_get_unused_filter(bp);
3682                 if (filter == NULL) {
3683                         PMD_DRV_LOG(ERR,
3684                                 "Not enough resources for a new flow.\n");
3685                         return -ENOMEM;
3686                 }
3687
3688                 ret = bnxt_parse_fdir_filter(bp, fdir, filter);
3689                 if (ret != 0)
3690                         goto free_filter;
3691                 filter->filter_type = HWRM_CFA_NTUPLE_FILTER;
3692
3693                 if (fdir->action.behavior == RTE_ETH_FDIR_REJECT)
3694                         vnic = &bp->vnic_info[0];
3695                 else
3696                         vnic = &bp->vnic_info[fdir->action.rx_queue];
3697
3698                 match = bnxt_match_fdir(bp, filter, &mvnic);
3699                 if (match != NULL && filter_op == RTE_ETH_FILTER_ADD) {
3700                         if (match->dst_id == vnic->fw_vnic_id) {
3701                                 PMD_DRV_LOG(ERR, "Flow already exists.\n");
3702                                 ret = -EEXIST;
3703                                 goto free_filter;
3704                         } else {
3705                                 match->dst_id = vnic->fw_vnic_id;
3706                                 ret = bnxt_hwrm_set_ntuple_filter(bp,
3707                                                                   match->dst_id,
3708                                                                   match);
3709                                 STAILQ_REMOVE(&mvnic->filter, match,
3710                                               bnxt_filter_info, next);
3711                                 STAILQ_INSERT_TAIL(&vnic->filter, match, next);
3712                                 PMD_DRV_LOG(ERR,
3713                                         "Filter with matching pattern exist\n");
3714                                 PMD_DRV_LOG(ERR,
3715                                         "Updated it to new destination q\n");
3716                                 goto free_filter;
3717                         }
3718                 }
3719                 if (match == NULL && filter_op == RTE_ETH_FILTER_DELETE) {
3720                         PMD_DRV_LOG(ERR, "Flow does not exist.\n");
3721                         ret = -ENOENT;
3722                         goto free_filter;
3723                 }
3724
3725                 if (filter_op == RTE_ETH_FILTER_ADD) {
3726                         ret = bnxt_hwrm_set_ntuple_filter(bp,
3727                                                           filter->dst_id,
3728                                                           filter);
3729                         if (ret)
3730                                 goto free_filter;
3731                         STAILQ_INSERT_TAIL(&vnic->filter, filter, next);
3732                 } else {
3733                         ret = bnxt_hwrm_clear_ntuple_filter(bp, match);
3734                         STAILQ_REMOVE(&vnic->filter, match,
3735                                       bnxt_filter_info, next);
3736                         bnxt_free_filter(bp, match);
3737                         bnxt_free_filter(bp, filter);
3738                 }
3739                 break;
3740         case RTE_ETH_FILTER_FLUSH:
3741                 for (i = bp->nr_vnics - 1; i >= 0; i--) {
3742                         struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
3743
3744                         STAILQ_FOREACH(filter, &vnic->filter, next) {
3745                                 if (filter->filter_type ==
3746                                     HWRM_CFA_NTUPLE_FILTER) {
3747                                         ret =
3748                                         bnxt_hwrm_clear_ntuple_filter(bp,
3749                                                                       filter);
3750                                         STAILQ_REMOVE(&vnic->filter, filter,
3751                                                       bnxt_filter_info, next);
3752                                 }
3753                         }
3754                 }
3755                 return ret;
3756         case RTE_ETH_FILTER_UPDATE:
3757         case RTE_ETH_FILTER_STATS:
3758         case RTE_ETH_FILTER_INFO:
3759                 PMD_DRV_LOG(ERR, "operation %u not implemented", filter_op);
3760                 break;
3761         default:
3762                 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
3763                 ret = -EINVAL;
3764                 break;
3765         }
3766         return ret;
3767
3768 free_filter:
3769         bnxt_free_filter(bp, filter);
3770         return ret;
3771 }
3772
3773 int
3774 bnxt_filter_ctrl_op(struct rte_eth_dev *dev,
3775                     enum rte_filter_type filter_type,
3776                     enum rte_filter_op filter_op, void *arg)
3777 {
3778         struct bnxt *bp = dev->data->dev_private;
3779         int ret = 0;
3780
3781         if (!bp)
3782                 return -EIO;
3783
3784         if (BNXT_ETH_DEV_IS_REPRESENTOR(dev)) {
3785                 struct bnxt_representor *vfr = dev->data->dev_private;
3786                 bp = vfr->parent_dev->data->dev_private;
3787                 /* parent is deleted while children are still valid */
3788                 if (!bp) {
3789                         PMD_DRV_LOG(DEBUG, "BNXT Port:%d VFR Error %d:%d\n",
3790                                     dev->data->port_id,
3791                                     filter_type,
3792                                     filter_op);
3793                         return -EIO;
3794                 }
3795         }
3796
3797         ret = is_bnxt_in_error(bp);
3798         if (ret)
3799                 return ret;
3800
3801         switch (filter_type) {
3802         case RTE_ETH_FILTER_TUNNEL:
3803                 PMD_DRV_LOG(ERR,
3804                         "filter type: %d: To be implemented\n", filter_type);
3805                 break;
3806         case RTE_ETH_FILTER_FDIR:
3807                 ret = bnxt_fdir_filter(dev, filter_op, arg);
3808                 break;
3809         case RTE_ETH_FILTER_NTUPLE:
3810                 ret = bnxt_ntuple_filter(dev, filter_op, arg);
3811                 break;
3812         case RTE_ETH_FILTER_ETHERTYPE:
3813                 ret = bnxt_ethertype_filter(dev, filter_op, arg);
3814                 break;
3815         case RTE_ETH_FILTER_GENERIC:
3816                 if (filter_op != RTE_ETH_FILTER_GET)
3817                         return -EINVAL;
3818                 if (BNXT_TRUFLOW_EN(bp))
3819                         *(const void **)arg = &bnxt_ulp_rte_flow_ops;
3820                 else
3821                         *(const void **)arg = &bnxt_flow_ops;
3822                 break;
3823         default:
3824                 PMD_DRV_LOG(ERR,
3825                         "Filter type (%d) not supported", filter_type);
3826                 ret = -EINVAL;
3827                 break;
3828         }
3829         return ret;
3830 }
3831
3832 static const uint32_t *
3833 bnxt_dev_supported_ptypes_get_op(struct rte_eth_dev *dev)
3834 {
3835         static const uint32_t ptypes[] = {
3836                 RTE_PTYPE_L2_ETHER_VLAN,
3837                 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN,
3838                 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN,
3839                 RTE_PTYPE_L4_ICMP,
3840                 RTE_PTYPE_L4_TCP,
3841                 RTE_PTYPE_L4_UDP,
3842                 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN,
3843                 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN,
3844                 RTE_PTYPE_INNER_L4_ICMP,
3845                 RTE_PTYPE_INNER_L4_TCP,
3846                 RTE_PTYPE_INNER_L4_UDP,
3847                 RTE_PTYPE_UNKNOWN
3848         };
3849
3850         if (!dev->rx_pkt_burst)
3851                 return NULL;
3852
3853         return ptypes;
3854 }
3855
3856 static int bnxt_map_regs(struct bnxt *bp, uint32_t *reg_arr, int count,
3857                          int reg_win)
3858 {
3859         uint32_t reg_base = *reg_arr & 0xfffff000;
3860         uint32_t win_off;
3861         int i;
3862
3863         for (i = 0; i < count; i++) {
3864                 if ((reg_arr[i] & 0xfffff000) != reg_base)
3865                         return -ERANGE;
3866         }
3867         win_off = BNXT_GRCPF_REG_WINDOW_BASE_OUT + (reg_win - 1) * 4;
3868         rte_write32(reg_base, (uint8_t *)bp->bar0 + win_off);
3869         return 0;
3870 }
3871
3872 static int bnxt_map_ptp_regs(struct bnxt *bp)
3873 {
3874         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3875         uint32_t *reg_arr;
3876         int rc, i;
3877
3878         reg_arr = ptp->rx_regs;
3879         rc = bnxt_map_regs(bp, reg_arr, BNXT_PTP_RX_REGS, 5);
3880         if (rc)
3881                 return rc;
3882
3883         reg_arr = ptp->tx_regs;
3884         rc = bnxt_map_regs(bp, reg_arr, BNXT_PTP_TX_REGS, 6);
3885         if (rc)
3886                 return rc;
3887
3888         for (i = 0; i < BNXT_PTP_RX_REGS; i++)
3889                 ptp->rx_mapped_regs[i] = 0x5000 + (ptp->rx_regs[i] & 0xfff);
3890
3891         for (i = 0; i < BNXT_PTP_TX_REGS; i++)
3892                 ptp->tx_mapped_regs[i] = 0x6000 + (ptp->tx_regs[i] & 0xfff);
3893
3894         return 0;
3895 }
3896
3897 static void bnxt_unmap_ptp_regs(struct bnxt *bp)
3898 {
3899         rte_write32(0, (uint8_t *)bp->bar0 +
3900                          BNXT_GRCPF_REG_WINDOW_BASE_OUT + 16);
3901         rte_write32(0, (uint8_t *)bp->bar0 +
3902                          BNXT_GRCPF_REG_WINDOW_BASE_OUT + 20);
3903 }
3904
3905 static uint64_t bnxt_cc_read(struct bnxt *bp)
3906 {
3907         uint64_t ns;
3908
3909         ns = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3910                               BNXT_GRCPF_REG_SYNC_TIME));
3911         ns |= (uint64_t)(rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3912                                           BNXT_GRCPF_REG_SYNC_TIME + 4))) << 32;
3913         return ns;
3914 }
3915
3916 static int bnxt_get_tx_ts(struct bnxt *bp, uint64_t *ts)
3917 {
3918         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3919         uint32_t fifo;
3920
3921         fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3922                                 ptp->tx_mapped_regs[BNXT_PTP_TX_FIFO]));
3923         if (fifo & BNXT_PTP_TX_FIFO_EMPTY)
3924                 return -EAGAIN;
3925
3926         fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3927                                 ptp->tx_mapped_regs[BNXT_PTP_TX_FIFO]));
3928         *ts = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3929                                 ptp->tx_mapped_regs[BNXT_PTP_TX_TS_L]));
3930         *ts |= (uint64_t)rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3931                                 ptp->tx_mapped_regs[BNXT_PTP_TX_TS_H])) << 32;
3932
3933         return 0;
3934 }
3935
3936 static int bnxt_get_rx_ts(struct bnxt *bp, uint64_t *ts)
3937 {
3938         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3939         struct bnxt_pf_info *pf = bp->pf;
3940         uint16_t port_id;
3941         uint32_t fifo;
3942
3943         if (!ptp)
3944                 return -ENODEV;
3945
3946         fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3947                                 ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO]));
3948         if (!(fifo & BNXT_PTP_RX_FIFO_PENDING))
3949                 return -EAGAIN;
3950
3951         port_id = pf->port_id;
3952         rte_write32(1 << port_id, (uint8_t *)bp->bar0 +
3953                ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO_ADV]);
3954
3955         fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3956                                    ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO]));
3957         if (fifo & BNXT_PTP_RX_FIFO_PENDING) {
3958 /*              bnxt_clr_rx_ts(bp);       TBD  */
3959                 return -EBUSY;
3960         }
3961
3962         *ts = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3963                                 ptp->rx_mapped_regs[BNXT_PTP_RX_TS_L]));
3964         *ts |= (uint64_t)rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3965                                 ptp->rx_mapped_regs[BNXT_PTP_RX_TS_H])) << 32;
3966
3967         return 0;
3968 }
3969
3970 static int
3971 bnxt_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
3972 {
3973         uint64_t ns;
3974         struct bnxt *bp = dev->data->dev_private;
3975         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3976
3977         if (!ptp)
3978                 return 0;
3979
3980         ns = rte_timespec_to_ns(ts);
3981         /* Set the timecounters to a new value. */
3982         ptp->tc.nsec = ns;
3983
3984         return 0;
3985 }
3986
3987 static int
3988 bnxt_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
3989 {
3990         struct bnxt *bp = dev->data->dev_private;
3991         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3992         uint64_t ns, systime_cycles = 0;
3993         int rc = 0;
3994
3995         if (!ptp)
3996                 return 0;
3997
3998         if (BNXT_CHIP_THOR(bp))
3999                 rc = bnxt_hwrm_port_ts_query(bp, BNXT_PTP_FLAGS_CURRENT_TIME,
4000                                              &systime_cycles);
4001         else
4002                 systime_cycles = bnxt_cc_read(bp);
4003
4004         ns = rte_timecounter_update(&ptp->tc, systime_cycles);
4005         *ts = rte_ns_to_timespec(ns);
4006
4007         return rc;
4008 }
4009 static int
4010 bnxt_timesync_enable(struct rte_eth_dev *dev)
4011 {
4012         struct bnxt *bp = dev->data->dev_private;
4013         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
4014         uint32_t shift = 0;
4015         int rc;
4016
4017         if (!ptp)
4018                 return 0;
4019
4020         ptp->rx_filter = 1;
4021         ptp->tx_tstamp_en = 1;
4022         ptp->rxctl = BNXT_PTP_MSG_EVENTS;
4023
4024         rc = bnxt_hwrm_ptp_cfg(bp);
4025         if (rc)
4026                 return rc;
4027
4028         memset(&ptp->tc, 0, sizeof(struct rte_timecounter));
4029         memset(&ptp->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
4030         memset(&ptp->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
4031
4032         ptp->tc.cc_mask = BNXT_CYCLECOUNTER_MASK;
4033         ptp->tc.cc_shift = shift;
4034         ptp->tc.nsec_mask = (1ULL << shift) - 1;
4035
4036         ptp->rx_tstamp_tc.cc_mask = BNXT_CYCLECOUNTER_MASK;
4037         ptp->rx_tstamp_tc.cc_shift = shift;
4038         ptp->rx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
4039
4040         ptp->tx_tstamp_tc.cc_mask = BNXT_CYCLECOUNTER_MASK;
4041         ptp->tx_tstamp_tc.cc_shift = shift;
4042         ptp->tx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
4043
4044         if (!BNXT_CHIP_THOR(bp))
4045                 bnxt_map_ptp_regs(bp);
4046
4047         return 0;
4048 }
4049
4050 static int
4051 bnxt_timesync_disable(struct rte_eth_dev *dev)
4052 {
4053         struct bnxt *bp = dev->data->dev_private;
4054         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
4055
4056         if (!ptp)
4057                 return 0;
4058
4059         ptp->rx_filter = 0;
4060         ptp->tx_tstamp_en = 0;
4061         ptp->rxctl = 0;
4062
4063         bnxt_hwrm_ptp_cfg(bp);
4064
4065         if (!BNXT_CHIP_THOR(bp))
4066                 bnxt_unmap_ptp_regs(bp);
4067
4068         return 0;
4069 }
4070
4071 static int
4072 bnxt_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
4073                                  struct timespec *timestamp,
4074                                  uint32_t flags __rte_unused)
4075 {
4076         struct bnxt *bp = dev->data->dev_private;
4077         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
4078         uint64_t rx_tstamp_cycles = 0;
4079         uint64_t ns;
4080
4081         if (!ptp)
4082                 return 0;
4083
4084         if (BNXT_CHIP_THOR(bp))
4085                 rx_tstamp_cycles = ptp->rx_timestamp;
4086         else
4087                 bnxt_get_rx_ts(bp, &rx_tstamp_cycles);
4088
4089         ns = rte_timecounter_update(&ptp->rx_tstamp_tc, rx_tstamp_cycles);
4090         *timestamp = rte_ns_to_timespec(ns);
4091         return  0;
4092 }
4093
4094 static int
4095 bnxt_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
4096                                  struct timespec *timestamp)
4097 {
4098         struct bnxt *bp = dev->data->dev_private;
4099         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
4100         uint64_t tx_tstamp_cycles = 0;
4101         uint64_t ns;
4102         int rc = 0;
4103
4104         if (!ptp)
4105                 return 0;
4106
4107         if (BNXT_CHIP_THOR(bp))
4108                 rc = bnxt_hwrm_port_ts_query(bp, BNXT_PTP_FLAGS_PATH_TX,
4109                                              &tx_tstamp_cycles);
4110         else
4111                 rc = bnxt_get_tx_ts(bp, &tx_tstamp_cycles);
4112
4113         ns = rte_timecounter_update(&ptp->tx_tstamp_tc, tx_tstamp_cycles);
4114         *timestamp = rte_ns_to_timespec(ns);
4115
4116         return rc;
4117 }
4118
4119 static int
4120 bnxt_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
4121 {
4122         struct bnxt *bp = dev->data->dev_private;
4123         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
4124
4125         if (!ptp)
4126                 return 0;
4127
4128         ptp->tc.nsec += delta;
4129
4130         return 0;
4131 }
4132
4133 static int
4134 bnxt_get_eeprom_length_op(struct rte_eth_dev *dev)
4135 {
4136         struct bnxt *bp = dev->data->dev_private;
4137         int rc;
4138         uint32_t dir_entries;
4139         uint32_t entry_length;
4140
4141         rc = is_bnxt_in_error(bp);
4142         if (rc)
4143                 return rc;
4144
4145         PMD_DRV_LOG(INFO, PCI_PRI_FMT "\n",
4146                     bp->pdev->addr.domain, bp->pdev->addr.bus,
4147                     bp->pdev->addr.devid, bp->pdev->addr.function);
4148
4149         rc = bnxt_hwrm_nvm_get_dir_info(bp, &dir_entries, &entry_length);
4150         if (rc != 0)
4151                 return rc;
4152
4153         return dir_entries * entry_length;
4154 }
4155
4156 static int
4157 bnxt_get_eeprom_op(struct rte_eth_dev *dev,
4158                 struct rte_dev_eeprom_info *in_eeprom)
4159 {
4160         struct bnxt *bp = dev->data->dev_private;
4161         uint32_t index;
4162         uint32_t offset;
4163         int rc;
4164
4165         rc = is_bnxt_in_error(bp);
4166         if (rc)
4167                 return rc;
4168
4169         PMD_DRV_LOG(INFO, PCI_PRI_FMT " in_eeprom->offset = %d len = %d\n",
4170                     bp->pdev->addr.domain, bp->pdev->addr.bus,
4171                     bp->pdev->addr.devid, bp->pdev->addr.function,
4172                     in_eeprom->offset, in_eeprom->length);
4173
4174         if (in_eeprom->offset == 0) /* special offset value to get directory */
4175                 return bnxt_get_nvram_directory(bp, in_eeprom->length,
4176                                                 in_eeprom->data);
4177
4178         index = in_eeprom->offset >> 24;
4179         offset = in_eeprom->offset & 0xffffff;
4180
4181         if (index != 0)
4182                 return bnxt_hwrm_get_nvram_item(bp, index - 1, offset,
4183                                            in_eeprom->length, in_eeprom->data);
4184
4185         return 0;
4186 }
4187
4188 static bool bnxt_dir_type_is_ape_bin_format(uint16_t dir_type)
4189 {
4190         switch (dir_type) {
4191         case BNX_DIR_TYPE_CHIMP_PATCH:
4192         case BNX_DIR_TYPE_BOOTCODE:
4193         case BNX_DIR_TYPE_BOOTCODE_2:
4194         case BNX_DIR_TYPE_APE_FW:
4195         case BNX_DIR_TYPE_APE_PATCH:
4196         case BNX_DIR_TYPE_KONG_FW:
4197         case BNX_DIR_TYPE_KONG_PATCH:
4198         case BNX_DIR_TYPE_BONO_FW:
4199         case BNX_DIR_TYPE_BONO_PATCH:
4200                 /* FALLTHROUGH */
4201                 return true;
4202         }
4203
4204         return false;
4205 }
4206
4207 static bool bnxt_dir_type_is_other_exec_format(uint16_t dir_type)
4208 {
4209         switch (dir_type) {
4210         case BNX_DIR_TYPE_AVS:
4211         case BNX_DIR_TYPE_EXP_ROM_MBA:
4212         case BNX_DIR_TYPE_PCIE:
4213         case BNX_DIR_TYPE_TSCF_UCODE:
4214         case BNX_DIR_TYPE_EXT_PHY:
4215         case BNX_DIR_TYPE_CCM:
4216         case BNX_DIR_TYPE_ISCSI_BOOT:
4217         case BNX_DIR_TYPE_ISCSI_BOOT_IPV6:
4218         case BNX_DIR_TYPE_ISCSI_BOOT_IPV4N6:
4219                 /* FALLTHROUGH */
4220                 return true;
4221         }
4222
4223         return false;
4224 }
4225
4226 static bool bnxt_dir_type_is_executable(uint16_t dir_type)
4227 {
4228         return bnxt_dir_type_is_ape_bin_format(dir_type) ||
4229                 bnxt_dir_type_is_other_exec_format(dir_type);
4230 }
4231
4232 static int
4233 bnxt_set_eeprom_op(struct rte_eth_dev *dev,
4234                 struct rte_dev_eeprom_info *in_eeprom)
4235 {
4236         struct bnxt *bp = dev->data->dev_private;
4237         uint8_t index, dir_op;
4238         uint16_t type, ext, ordinal, attr;
4239         int rc;
4240
4241         rc = is_bnxt_in_error(bp);
4242         if (rc)
4243                 return rc;
4244
4245         PMD_DRV_LOG(INFO, PCI_PRI_FMT " in_eeprom->offset = %d len = %d\n",
4246                     bp->pdev->addr.domain, bp->pdev->addr.bus,
4247                     bp->pdev->addr.devid, bp->pdev->addr.function,
4248                     in_eeprom->offset, in_eeprom->length);
4249
4250         if (!BNXT_PF(bp)) {
4251                 PMD_DRV_LOG(ERR, "NVM write not supported from a VF\n");
4252                 return -EINVAL;
4253         }
4254
4255         type = in_eeprom->magic >> 16;
4256
4257         if (type == 0xffff) { /* special value for directory operations */
4258                 index = in_eeprom->magic & 0xff;
4259                 dir_op = in_eeprom->magic >> 8;
4260                 if (index == 0)
4261                         return -EINVAL;
4262                 switch (dir_op) {
4263                 case 0x0e: /* erase */
4264                         if (in_eeprom->offset != ~in_eeprom->magic)
4265                                 return -EINVAL;
4266                         return bnxt_hwrm_erase_nvram_directory(bp, index - 1);
4267                 default:
4268                         return -EINVAL;
4269                 }
4270         }
4271
4272         /* Create or re-write an NVM item: */
4273         if (bnxt_dir_type_is_executable(type) == true)
4274                 return -EOPNOTSUPP;
4275         ext = in_eeprom->magic & 0xffff;
4276         ordinal = in_eeprom->offset >> 16;
4277         attr = in_eeprom->offset & 0xffff;
4278
4279         return bnxt_hwrm_flash_nvram(bp, type, ordinal, ext, attr,
4280                                      in_eeprom->data, in_eeprom->length);
4281 }
4282
4283 /*
4284  * Initialization
4285  */
4286
4287 static const struct eth_dev_ops bnxt_dev_ops = {
4288         .dev_infos_get = bnxt_dev_info_get_op,
4289         .dev_close = bnxt_dev_close_op,
4290         .dev_configure = bnxt_dev_configure_op,
4291         .dev_start = bnxt_dev_start_op,
4292         .dev_stop = bnxt_dev_stop_op,
4293         .dev_set_link_up = bnxt_dev_set_link_up_op,
4294         .dev_set_link_down = bnxt_dev_set_link_down_op,
4295         .stats_get = bnxt_stats_get_op,
4296         .stats_reset = bnxt_stats_reset_op,
4297         .rx_queue_setup = bnxt_rx_queue_setup_op,
4298         .rx_queue_release = bnxt_rx_queue_release_op,
4299         .tx_queue_setup = bnxt_tx_queue_setup_op,
4300         .tx_queue_release = bnxt_tx_queue_release_op,
4301         .rx_queue_intr_enable = bnxt_rx_queue_intr_enable_op,
4302         .rx_queue_intr_disable = bnxt_rx_queue_intr_disable_op,
4303         .reta_update = bnxt_reta_update_op,
4304         .reta_query = bnxt_reta_query_op,
4305         .rss_hash_update = bnxt_rss_hash_update_op,
4306         .rss_hash_conf_get = bnxt_rss_hash_conf_get_op,
4307         .link_update = bnxt_link_update_op,
4308         .promiscuous_enable = bnxt_promiscuous_enable_op,
4309         .promiscuous_disable = bnxt_promiscuous_disable_op,
4310         .allmulticast_enable = bnxt_allmulticast_enable_op,
4311         .allmulticast_disable = bnxt_allmulticast_disable_op,
4312         .mac_addr_add = bnxt_mac_addr_add_op,
4313         .mac_addr_remove = bnxt_mac_addr_remove_op,
4314         .flow_ctrl_get = bnxt_flow_ctrl_get_op,
4315         .flow_ctrl_set = bnxt_flow_ctrl_set_op,
4316         .udp_tunnel_port_add  = bnxt_udp_tunnel_port_add_op,
4317         .udp_tunnel_port_del  = bnxt_udp_tunnel_port_del_op,
4318         .vlan_filter_set = bnxt_vlan_filter_set_op,
4319         .vlan_offload_set = bnxt_vlan_offload_set_op,
4320         .vlan_tpid_set = bnxt_vlan_tpid_set_op,
4321         .vlan_pvid_set = bnxt_vlan_pvid_set_op,
4322         .mtu_set = bnxt_mtu_set_op,
4323         .mac_addr_set = bnxt_set_default_mac_addr_op,
4324         .xstats_get = bnxt_dev_xstats_get_op,
4325         .xstats_get_names = bnxt_dev_xstats_get_names_op,
4326         .xstats_reset = bnxt_dev_xstats_reset_op,
4327         .fw_version_get = bnxt_fw_version_get,
4328         .set_mc_addr_list = bnxt_dev_set_mc_addr_list_op,
4329         .rxq_info_get = bnxt_rxq_info_get_op,
4330         .txq_info_get = bnxt_txq_info_get_op,
4331         .rx_burst_mode_get = bnxt_rx_burst_mode_get,
4332         .tx_burst_mode_get = bnxt_tx_burst_mode_get,
4333         .dev_led_on = bnxt_dev_led_on_op,
4334         .dev_led_off = bnxt_dev_led_off_op,
4335         .xstats_get_by_id = bnxt_dev_xstats_get_by_id_op,
4336         .xstats_get_names_by_id = bnxt_dev_xstats_get_names_by_id_op,
4337         .rx_queue_start = bnxt_rx_queue_start,
4338         .rx_queue_stop = bnxt_rx_queue_stop,
4339         .tx_queue_start = bnxt_tx_queue_start,
4340         .tx_queue_stop = bnxt_tx_queue_stop,
4341         .filter_ctrl = bnxt_filter_ctrl_op,
4342         .dev_supported_ptypes_get = bnxt_dev_supported_ptypes_get_op,
4343         .get_eeprom_length    = bnxt_get_eeprom_length_op,
4344         .get_eeprom           = bnxt_get_eeprom_op,
4345         .set_eeprom           = bnxt_set_eeprom_op,
4346         .timesync_enable      = bnxt_timesync_enable,
4347         .timesync_disable     = bnxt_timesync_disable,
4348         .timesync_read_time   = bnxt_timesync_read_time,
4349         .timesync_write_time   = bnxt_timesync_write_time,
4350         .timesync_adjust_time = bnxt_timesync_adjust_time,
4351         .timesync_read_rx_timestamp = bnxt_timesync_read_rx_timestamp,
4352         .timesync_read_tx_timestamp = bnxt_timesync_read_tx_timestamp,
4353 };
4354
4355 static uint32_t bnxt_map_reset_regs(struct bnxt *bp, uint32_t reg)
4356 {
4357         uint32_t offset;
4358
4359         /* Only pre-map the reset GRC registers using window 3 */
4360         rte_write32(reg & 0xfffff000, (uint8_t *)bp->bar0 +
4361                     BNXT_GRCPF_REG_WINDOW_BASE_OUT + 8);
4362
4363         offset = BNXT_GRCP_WINDOW_3_BASE + (reg & 0xffc);
4364
4365         return offset;
4366 }
4367
4368 int bnxt_map_fw_health_status_regs(struct bnxt *bp)
4369 {
4370         struct bnxt_error_recovery_info *info = bp->recovery_info;
4371         uint32_t reg_base = 0xffffffff;
4372         int i;
4373
4374         /* Only pre-map the monitoring GRC registers using window 2 */
4375         for (i = 0; i < BNXT_FW_STATUS_REG_CNT; i++) {
4376                 uint32_t reg = info->status_regs[i];
4377
4378                 if (BNXT_FW_STATUS_REG_TYPE(reg) != BNXT_FW_STATUS_REG_TYPE_GRC)
4379                         continue;
4380
4381                 if (reg_base == 0xffffffff)
4382                         reg_base = reg & 0xfffff000;
4383                 if ((reg & 0xfffff000) != reg_base)
4384                         return -ERANGE;
4385
4386                 /* Use mask 0xffc as the Lower 2 bits indicates
4387                  * address space location
4388                  */
4389                 info->mapped_status_regs[i] = BNXT_GRCP_WINDOW_2_BASE +
4390                                                 (reg & 0xffc);
4391         }
4392
4393         if (reg_base == 0xffffffff)
4394                 return 0;
4395
4396         rte_write32(reg_base, (uint8_t *)bp->bar0 +
4397                     BNXT_GRCPF_REG_WINDOW_BASE_OUT + 4);
4398
4399         return 0;
4400 }
4401
4402 static void bnxt_write_fw_reset_reg(struct bnxt *bp, uint32_t index)
4403 {
4404         struct bnxt_error_recovery_info *info = bp->recovery_info;
4405         uint32_t delay = info->delay_after_reset[index];
4406         uint32_t val = info->reset_reg_val[index];
4407         uint32_t reg = info->reset_reg[index];
4408         uint32_t type, offset;
4409
4410         type = BNXT_FW_STATUS_REG_TYPE(reg);
4411         offset = BNXT_FW_STATUS_REG_OFF(reg);
4412
4413         switch (type) {
4414         case BNXT_FW_STATUS_REG_TYPE_CFG:
4415                 rte_pci_write_config(bp->pdev, &val, sizeof(val), offset);
4416                 break;
4417         case BNXT_FW_STATUS_REG_TYPE_GRC:
4418                 offset = bnxt_map_reset_regs(bp, offset);
4419                 rte_write32(val, (uint8_t *)bp->bar0 + offset);
4420                 break;
4421         case BNXT_FW_STATUS_REG_TYPE_BAR0:
4422                 rte_write32(val, (uint8_t *)bp->bar0 + offset);
4423                 break;
4424         }
4425         /* wait on a specific interval of time until core reset is complete */
4426         if (delay)
4427                 rte_delay_ms(delay);
4428 }
4429
4430 static void bnxt_dev_cleanup(struct bnxt *bp)
4431 {
4432         bp->eth_dev->data->dev_link.link_status = 0;
4433         bp->link_info->link_up = 0;
4434         if (bp->eth_dev->data->dev_started)
4435                 bnxt_dev_stop_op(bp->eth_dev);
4436
4437         bnxt_uninit_resources(bp, true);
4438 }
4439
4440 static int bnxt_restore_vlan_filters(struct bnxt *bp)
4441 {
4442         struct rte_eth_dev *dev = bp->eth_dev;
4443         struct rte_vlan_filter_conf *vfc;
4444         int vidx, vbit, rc;
4445         uint16_t vlan_id;
4446
4447         for (vlan_id = 1; vlan_id <= RTE_ETHER_MAX_VLAN_ID; vlan_id++) {
4448                 vfc = &dev->data->vlan_filter_conf;
4449                 vidx = vlan_id / 64;
4450                 vbit = vlan_id % 64;
4451
4452                 /* Each bit corresponds to a VLAN id */
4453                 if (vfc->ids[vidx] & (UINT64_C(1) << vbit)) {
4454                         rc = bnxt_add_vlan_filter(bp, vlan_id);
4455                         if (rc)
4456                                 return rc;
4457                 }
4458         }
4459
4460         return 0;
4461 }
4462
4463 static int bnxt_restore_mac_filters(struct bnxt *bp)
4464 {
4465         struct rte_eth_dev *dev = bp->eth_dev;
4466         struct rte_eth_dev_info dev_info;
4467         struct rte_ether_addr *addr;
4468         uint64_t pool_mask;
4469         uint32_t pool = 0;
4470         uint16_t i;
4471         int rc;
4472
4473         if (BNXT_VF(bp) && !BNXT_VF_IS_TRUSTED(bp))
4474                 return 0;
4475
4476         rc = bnxt_dev_info_get_op(dev, &dev_info);
4477         if (rc)
4478                 return rc;
4479
4480         /* replay MAC address configuration */
4481         for (i = 1; i < dev_info.max_mac_addrs; i++) {
4482                 addr = &dev->data->mac_addrs[i];
4483
4484                 /* skip zero address */
4485                 if (rte_is_zero_ether_addr(addr))
4486                         continue;
4487
4488                 pool = 0;
4489                 pool_mask = dev->data->mac_pool_sel[i];
4490
4491                 do {
4492                         if (pool_mask & 1ULL) {
4493                                 rc = bnxt_mac_addr_add_op(dev, addr, i, pool);
4494                                 if (rc)
4495                                         return rc;
4496                         }
4497                         pool_mask >>= 1;
4498                         pool++;
4499                 } while (pool_mask);
4500         }
4501
4502         return 0;
4503 }
4504
4505 static int bnxt_restore_filters(struct bnxt *bp)
4506 {
4507         struct rte_eth_dev *dev = bp->eth_dev;
4508         int ret = 0;
4509
4510         if (dev->data->all_multicast) {
4511                 ret = bnxt_allmulticast_enable_op(dev);
4512                 if (ret)
4513                         return ret;
4514         }
4515         if (dev->data->promiscuous) {
4516                 ret = bnxt_promiscuous_enable_op(dev);
4517                 if (ret)
4518                         return ret;
4519         }
4520
4521         ret = bnxt_restore_mac_filters(bp);
4522         if (ret)
4523                 return ret;
4524
4525         ret = bnxt_restore_vlan_filters(bp);
4526         /* TODO restore other filters as well */
4527         return ret;
4528 }
4529
4530 static void bnxt_dev_recover(void *arg)
4531 {
4532         struct bnxt *bp = arg;
4533         int timeout = bp->fw_reset_max_msecs;
4534         int rc = 0;
4535
4536         /* Clear Error flag so that device re-init should happen */
4537         bp->flags &= ~BNXT_FLAG_FATAL_ERROR;
4538
4539         do {
4540                 rc = bnxt_hwrm_ver_get(bp, SHORT_HWRM_CMD_TIMEOUT);
4541                 if (rc == 0)
4542                         break;
4543                 rte_delay_ms(BNXT_FW_READY_WAIT_INTERVAL);
4544                 timeout -= BNXT_FW_READY_WAIT_INTERVAL;
4545         } while (rc && timeout);
4546
4547         if (rc) {
4548                 PMD_DRV_LOG(ERR, "FW is not Ready after reset\n");
4549                 goto err;
4550         }
4551
4552         rc = bnxt_init_resources(bp, true);
4553         if (rc) {
4554                 PMD_DRV_LOG(ERR,
4555                             "Failed to initialize resources after reset\n");
4556                 goto err;
4557         }
4558         /* clear reset flag as the device is initialized now */
4559         bp->flags &= ~BNXT_FLAG_FW_RESET;
4560
4561         rc = bnxt_dev_start_op(bp->eth_dev);
4562         if (rc) {
4563                 PMD_DRV_LOG(ERR, "Failed to start port after reset\n");
4564                 goto err_start;
4565         }
4566
4567         rc = bnxt_restore_filters(bp);
4568         if (rc)
4569                 goto err_start;
4570
4571         PMD_DRV_LOG(INFO, "Recovered from FW reset\n");
4572         return;
4573 err_start:
4574         bnxt_dev_stop_op(bp->eth_dev);
4575 err:
4576         bp->flags |= BNXT_FLAG_FATAL_ERROR;
4577         bnxt_uninit_resources(bp, false);
4578         PMD_DRV_LOG(ERR, "Failed to recover from FW reset\n");
4579 }
4580
4581 void bnxt_dev_reset_and_resume(void *arg)
4582 {
4583         struct bnxt *bp = arg;
4584         int rc;
4585
4586         bnxt_dev_cleanup(bp);
4587
4588         bnxt_wait_for_device_shutdown(bp);
4589
4590         rc = rte_eal_alarm_set(US_PER_MS * bp->fw_reset_min_msecs,
4591                                bnxt_dev_recover, (void *)bp);
4592         if (rc)
4593                 PMD_DRV_LOG(ERR, "Error setting recovery alarm");
4594 }
4595
4596 uint32_t bnxt_read_fw_status_reg(struct bnxt *bp, uint32_t index)
4597 {
4598         struct bnxt_error_recovery_info *info = bp->recovery_info;
4599         uint32_t reg = info->status_regs[index];
4600         uint32_t type, offset, val = 0;
4601
4602         type = BNXT_FW_STATUS_REG_TYPE(reg);
4603         offset = BNXT_FW_STATUS_REG_OFF(reg);
4604
4605         switch (type) {
4606         case BNXT_FW_STATUS_REG_TYPE_CFG:
4607                 rte_pci_read_config(bp->pdev, &val, sizeof(val), offset);
4608                 break;
4609         case BNXT_FW_STATUS_REG_TYPE_GRC:
4610                 offset = info->mapped_status_regs[index];
4611                 /* FALLTHROUGH */
4612         case BNXT_FW_STATUS_REG_TYPE_BAR0:
4613                 val = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
4614                                        offset));
4615                 break;
4616         }
4617
4618         return val;
4619 }
4620
4621 static int bnxt_fw_reset_all(struct bnxt *bp)
4622 {
4623         struct bnxt_error_recovery_info *info = bp->recovery_info;
4624         uint32_t i;
4625         int rc = 0;
4626
4627         if (info->flags & BNXT_FLAG_ERROR_RECOVERY_HOST) {
4628                 /* Reset through master function driver */
4629                 for (i = 0; i < info->reg_array_cnt; i++)
4630                         bnxt_write_fw_reset_reg(bp, i);
4631                 /* Wait for time specified by FW after triggering reset */
4632                 rte_delay_ms(info->master_func_wait_period_after_reset);
4633         } else if (info->flags & BNXT_FLAG_ERROR_RECOVERY_CO_CPU) {
4634                 /* Reset with the help of Kong processor */
4635                 rc = bnxt_hwrm_fw_reset(bp);
4636                 if (rc)
4637                         PMD_DRV_LOG(ERR, "Failed to reset FW\n");
4638         }
4639
4640         return rc;
4641 }
4642
4643 static void bnxt_fw_reset_cb(void *arg)
4644 {
4645         struct bnxt *bp = arg;
4646         struct bnxt_error_recovery_info *info = bp->recovery_info;
4647         int rc = 0;
4648
4649         /* Only Master function can do FW reset */
4650         if (bnxt_is_master_func(bp) &&
4651             bnxt_is_recovery_enabled(bp)) {
4652                 rc = bnxt_fw_reset_all(bp);
4653                 if (rc) {
4654                         PMD_DRV_LOG(ERR, "Adapter recovery failed\n");
4655                         return;
4656                 }
4657         }
4658
4659         /* if recovery method is ERROR_RECOVERY_CO_CPU, KONG will send
4660          * EXCEPTION_FATAL_ASYNC event to all the functions
4661          * (including MASTER FUNC). After receiving this Async, all the active
4662          * drivers should treat this case as FW initiated recovery
4663          */
4664         if (info->flags & BNXT_FLAG_ERROR_RECOVERY_HOST) {
4665                 bp->fw_reset_min_msecs = BNXT_MIN_FW_READY_TIMEOUT;
4666                 bp->fw_reset_max_msecs = BNXT_MAX_FW_RESET_TIMEOUT;
4667
4668                 /* To recover from error */
4669                 rte_eal_alarm_set(US_PER_MS, bnxt_dev_reset_and_resume,
4670                                   (void *)bp);
4671         }
4672 }
4673
4674 /* Driver should poll FW heartbeat, reset_counter with the frequency
4675  * advertised by FW in HWRM_ERROR_RECOVERY_QCFG.
4676  * When the driver detects heartbeat stop or change in reset_counter,
4677  * it has to trigger a reset to recover from the error condition.
4678  * A “master PF” is the function who will have the privilege to
4679  * initiate the chimp reset. The master PF will be elected by the
4680  * firmware and will be notified through async message.
4681  */
4682 static void bnxt_check_fw_health(void *arg)
4683 {
4684         struct bnxt *bp = arg;
4685         struct bnxt_error_recovery_info *info = bp->recovery_info;
4686         uint32_t val = 0, wait_msec;
4687
4688         if (!info || !bnxt_is_recovery_enabled(bp) ||
4689             is_bnxt_in_error(bp))
4690                 return;
4691
4692         val = bnxt_read_fw_status_reg(bp, BNXT_FW_HEARTBEAT_CNT_REG);
4693         if (val == info->last_heart_beat)
4694                 goto reset;
4695
4696         info->last_heart_beat = val;
4697
4698         val = bnxt_read_fw_status_reg(bp, BNXT_FW_RECOVERY_CNT_REG);
4699         if (val != info->last_reset_counter)
4700                 goto reset;
4701
4702         info->last_reset_counter = val;
4703
4704         rte_eal_alarm_set(US_PER_MS * info->driver_polling_freq,
4705                           bnxt_check_fw_health, (void *)bp);
4706
4707         return;
4708 reset:
4709         /* Stop DMA to/from device */
4710         bp->flags |= BNXT_FLAG_FATAL_ERROR;
4711         bp->flags |= BNXT_FLAG_FW_RESET;
4712
4713         PMD_DRV_LOG(ERR, "Detected FW dead condition\n");
4714
4715         if (bnxt_is_master_func(bp))
4716                 wait_msec = info->master_func_wait_period;
4717         else
4718                 wait_msec = info->normal_func_wait_period;
4719
4720         rte_eal_alarm_set(US_PER_MS * wait_msec,
4721                           bnxt_fw_reset_cb, (void *)bp);
4722 }
4723
4724 void bnxt_schedule_fw_health_check(struct bnxt *bp)
4725 {
4726         uint32_t polling_freq;
4727
4728         pthread_mutex_lock(&bp->health_check_lock);
4729
4730         if (!bnxt_is_recovery_enabled(bp))
4731                 goto done;
4732
4733         if (bp->flags & BNXT_FLAG_FW_HEALTH_CHECK_SCHEDULED)
4734                 goto done;
4735
4736         polling_freq = bp->recovery_info->driver_polling_freq;
4737
4738         rte_eal_alarm_set(US_PER_MS * polling_freq,
4739                           bnxt_check_fw_health, (void *)bp);
4740         bp->flags |= BNXT_FLAG_FW_HEALTH_CHECK_SCHEDULED;
4741
4742 done:
4743         pthread_mutex_unlock(&bp->health_check_lock);
4744 }
4745
4746 static void bnxt_cancel_fw_health_check(struct bnxt *bp)
4747 {
4748         if (!bnxt_is_recovery_enabled(bp))
4749                 return;
4750
4751         rte_eal_alarm_cancel(bnxt_check_fw_health, (void *)bp);
4752         bp->flags &= ~BNXT_FLAG_FW_HEALTH_CHECK_SCHEDULED;
4753 }
4754
4755 static bool bnxt_vf_pciid(uint16_t device_id)
4756 {
4757         switch (device_id) {
4758         case BROADCOM_DEV_ID_57304_VF:
4759         case BROADCOM_DEV_ID_57406_VF:
4760         case BROADCOM_DEV_ID_5731X_VF:
4761         case BROADCOM_DEV_ID_5741X_VF:
4762         case BROADCOM_DEV_ID_57414_VF:
4763         case BROADCOM_DEV_ID_STRATUS_NIC_VF1:
4764         case BROADCOM_DEV_ID_STRATUS_NIC_VF2:
4765         case BROADCOM_DEV_ID_58802_VF:
4766         case BROADCOM_DEV_ID_57500_VF1:
4767         case BROADCOM_DEV_ID_57500_VF2:
4768                 /* FALLTHROUGH */
4769                 return true;
4770         default:
4771                 return false;
4772         }
4773 }
4774
4775 static bool bnxt_thor_device(uint16_t device_id)
4776 {
4777         switch (device_id) {
4778         case BROADCOM_DEV_ID_57508:
4779         case BROADCOM_DEV_ID_57504:
4780         case BROADCOM_DEV_ID_57502:
4781         case BROADCOM_DEV_ID_57508_MF1:
4782         case BROADCOM_DEV_ID_57504_MF1:
4783         case BROADCOM_DEV_ID_57502_MF1:
4784         case BROADCOM_DEV_ID_57508_MF2:
4785         case BROADCOM_DEV_ID_57504_MF2:
4786         case BROADCOM_DEV_ID_57502_MF2:
4787         case BROADCOM_DEV_ID_57500_VF1:
4788         case BROADCOM_DEV_ID_57500_VF2:
4789                 /* FALLTHROUGH */
4790                 return true;
4791         default:
4792                 return false;
4793         }
4794 }
4795
4796 bool bnxt_stratus_device(struct bnxt *bp)
4797 {
4798         uint16_t device_id = bp->pdev->id.device_id;
4799
4800         switch (device_id) {
4801         case BROADCOM_DEV_ID_STRATUS_NIC:
4802         case BROADCOM_DEV_ID_STRATUS_NIC_VF1:
4803         case BROADCOM_DEV_ID_STRATUS_NIC_VF2:
4804                 /* FALLTHROUGH */
4805                 return true;
4806         default:
4807                 return false;
4808         }
4809 }
4810
4811 static int bnxt_init_board(struct rte_eth_dev *eth_dev)
4812 {
4813         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
4814         struct bnxt *bp = eth_dev->data->dev_private;
4815
4816         /* enable device (incl. PCI PM wakeup), and bus-mastering */
4817         bp->bar0 = (void *)pci_dev->mem_resource[0].addr;
4818         bp->doorbell_base = (void *)pci_dev->mem_resource[2].addr;
4819         if (!bp->bar0 || !bp->doorbell_base) {
4820                 PMD_DRV_LOG(ERR, "Unable to access Hardware\n");
4821                 return -ENODEV;
4822         }
4823
4824         bp->eth_dev = eth_dev;
4825         bp->pdev = pci_dev;
4826
4827         return 0;
4828 }
4829
4830 static int bnxt_alloc_ctx_mem_blk(struct bnxt *bp,
4831                                   struct bnxt_ctx_pg_info *ctx_pg,
4832                                   uint32_t mem_size,
4833                                   const char *suffix,
4834                                   uint16_t idx)
4835 {
4836         struct bnxt_ring_mem_info *rmem = &ctx_pg->ring_mem;
4837         const struct rte_memzone *mz = NULL;
4838         char mz_name[RTE_MEMZONE_NAMESIZE];
4839         rte_iova_t mz_phys_addr;
4840         uint64_t valid_bits = 0;
4841         uint32_t sz;
4842         int i;
4843
4844         if (!mem_size)
4845                 return 0;
4846
4847         rmem->nr_pages = RTE_ALIGN_MUL_CEIL(mem_size, BNXT_PAGE_SIZE) /
4848                          BNXT_PAGE_SIZE;
4849         rmem->page_size = BNXT_PAGE_SIZE;
4850         rmem->pg_arr = ctx_pg->ctx_pg_arr;
4851         rmem->dma_arr = ctx_pg->ctx_dma_arr;
4852         rmem->flags = BNXT_RMEM_VALID_PTE_FLAG;
4853
4854         valid_bits = PTU_PTE_VALID;
4855
4856         if (rmem->nr_pages > 1) {
4857                 snprintf(mz_name, RTE_MEMZONE_NAMESIZE,
4858                          "bnxt_ctx_pg_tbl%s_%x_%d",
4859                          suffix, idx, bp->eth_dev->data->port_id);
4860                 mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0;
4861                 mz = rte_memzone_lookup(mz_name);
4862                 if (!mz) {
4863                         mz = rte_memzone_reserve_aligned(mz_name,
4864                                                 rmem->nr_pages * 8,
4865                                                 SOCKET_ID_ANY,
4866                                                 RTE_MEMZONE_2MB |
4867                                                 RTE_MEMZONE_SIZE_HINT_ONLY |
4868                                                 RTE_MEMZONE_IOVA_CONTIG,
4869                                                 BNXT_PAGE_SIZE);
4870                         if (mz == NULL)
4871                                 return -ENOMEM;
4872                 }
4873
4874                 memset(mz->addr, 0, mz->len);
4875                 mz_phys_addr = mz->iova;
4876
4877                 rmem->pg_tbl = mz->addr;
4878                 rmem->pg_tbl_map = mz_phys_addr;
4879                 rmem->pg_tbl_mz = mz;
4880         }
4881
4882         snprintf(mz_name, RTE_MEMZONE_NAMESIZE, "bnxt_ctx_%s_%x_%d",
4883                  suffix, idx, bp->eth_dev->data->port_id);
4884         mz = rte_memzone_lookup(mz_name);
4885         if (!mz) {
4886                 mz = rte_memzone_reserve_aligned(mz_name,
4887                                                  mem_size,
4888                                                  SOCKET_ID_ANY,
4889                                                  RTE_MEMZONE_1GB |
4890                                                  RTE_MEMZONE_SIZE_HINT_ONLY |
4891                                                  RTE_MEMZONE_IOVA_CONTIG,
4892                                                  BNXT_PAGE_SIZE);
4893                 if (mz == NULL)
4894                         return -ENOMEM;
4895         }
4896
4897         memset(mz->addr, 0, mz->len);
4898         mz_phys_addr = mz->iova;
4899
4900         for (sz = 0, i = 0; sz < mem_size; sz += BNXT_PAGE_SIZE, i++) {
4901                 rmem->pg_arr[i] = ((char *)mz->addr) + sz;
4902                 rmem->dma_arr[i] = mz_phys_addr + sz;
4903
4904                 if (rmem->nr_pages > 1) {
4905                         if (i == rmem->nr_pages - 2 &&
4906                             (rmem->flags & BNXT_RMEM_RING_PTE_FLAG))
4907                                 valid_bits |= PTU_PTE_NEXT_TO_LAST;
4908                         else if (i == rmem->nr_pages - 1 &&
4909                                  (rmem->flags & BNXT_RMEM_RING_PTE_FLAG))
4910                                 valid_bits |= PTU_PTE_LAST;
4911
4912                         rmem->pg_tbl[i] = rte_cpu_to_le_64(rmem->dma_arr[i] |
4913                                                            valid_bits);
4914                 }
4915         }
4916
4917         rmem->mz = mz;
4918         if (rmem->vmem_size)
4919                 rmem->vmem = (void **)mz->addr;
4920         rmem->dma_arr[0] = mz_phys_addr;
4921         return 0;
4922 }
4923
4924 static void bnxt_free_ctx_mem(struct bnxt *bp)
4925 {
4926         int i;
4927
4928         if (!bp->ctx || !(bp->ctx->flags & BNXT_CTX_FLAG_INITED))
4929                 return;
4930
4931         bp->ctx->flags &= ~BNXT_CTX_FLAG_INITED;
4932         rte_memzone_free(bp->ctx->qp_mem.ring_mem.mz);
4933         rte_memzone_free(bp->ctx->srq_mem.ring_mem.mz);
4934         rte_memzone_free(bp->ctx->cq_mem.ring_mem.mz);
4935         rte_memzone_free(bp->ctx->vnic_mem.ring_mem.mz);
4936         rte_memzone_free(bp->ctx->stat_mem.ring_mem.mz);
4937         rte_memzone_free(bp->ctx->qp_mem.ring_mem.pg_tbl_mz);
4938         rte_memzone_free(bp->ctx->srq_mem.ring_mem.pg_tbl_mz);
4939         rte_memzone_free(bp->ctx->cq_mem.ring_mem.pg_tbl_mz);
4940         rte_memzone_free(bp->ctx->vnic_mem.ring_mem.pg_tbl_mz);
4941         rte_memzone_free(bp->ctx->stat_mem.ring_mem.pg_tbl_mz);
4942
4943         for (i = 0; i < bp->ctx->tqm_fp_rings_count + 1; i++) {
4944                 if (bp->ctx->tqm_mem[i])
4945                         rte_memzone_free(bp->ctx->tqm_mem[i]->ring_mem.mz);
4946         }
4947
4948         rte_free(bp->ctx);
4949         bp->ctx = NULL;
4950 }
4951
4952 #define bnxt_roundup(x, y)   ((((x) + ((y) - 1)) / (y)) * (y))
4953
4954 #define min_t(type, x, y) ({                    \
4955         type __min1 = (x);                      \
4956         type __min2 = (y);                      \
4957         __min1 < __min2 ? __min1 : __min2; })
4958
4959 #define max_t(type, x, y) ({                    \
4960         type __max1 = (x);                      \
4961         type __max2 = (y);                      \
4962         __max1 > __max2 ? __max1 : __max2; })
4963
4964 #define clamp_t(type, _x, min, max)     min_t(type, max_t(type, _x, min), max)
4965
4966 int bnxt_alloc_ctx_mem(struct bnxt *bp)
4967 {
4968         struct bnxt_ctx_pg_info *ctx_pg;
4969         struct bnxt_ctx_mem_info *ctx;
4970         uint32_t mem_size, ena, entries;
4971         uint32_t entries_sp, min;
4972         int i, rc;
4973
4974         rc = bnxt_hwrm_func_backing_store_qcaps(bp);
4975         if (rc) {
4976                 PMD_DRV_LOG(ERR, "Query context mem capability failed\n");
4977                 return rc;
4978         }
4979         ctx = bp->ctx;
4980         if (!ctx || (ctx->flags & BNXT_CTX_FLAG_INITED))
4981                 return 0;
4982
4983         ctx_pg = &ctx->qp_mem;
4984         ctx_pg->entries = ctx->qp_min_qp1_entries + ctx->qp_max_l2_entries;
4985         mem_size = ctx->qp_entry_size * ctx_pg->entries;
4986         rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "qp_mem", 0);
4987         if (rc)
4988                 return rc;
4989
4990         ctx_pg = &ctx->srq_mem;
4991         ctx_pg->entries = ctx->srq_max_l2_entries;
4992         mem_size = ctx->srq_entry_size * ctx_pg->entries;
4993         rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "srq_mem", 0);
4994         if (rc)
4995                 return rc;
4996
4997         ctx_pg = &ctx->cq_mem;
4998         ctx_pg->entries = ctx->cq_max_l2_entries;
4999         mem_size = ctx->cq_entry_size * ctx_pg->entries;
5000         rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "cq_mem", 0);
5001         if (rc)
5002                 return rc;
5003
5004         ctx_pg = &ctx->vnic_mem;
5005         ctx_pg->entries = ctx->vnic_max_vnic_entries +
5006                 ctx->vnic_max_ring_table_entries;
5007         mem_size = ctx->vnic_entry_size * ctx_pg->entries;
5008         rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "vnic_mem", 0);
5009         if (rc)
5010                 return rc;
5011
5012         ctx_pg = &ctx->stat_mem;
5013         ctx_pg->entries = ctx->stat_max_entries;
5014         mem_size = ctx->stat_entry_size * ctx_pg->entries;
5015         rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "stat_mem", 0);
5016         if (rc)
5017                 return rc;
5018
5019         min = ctx->tqm_min_entries_per_ring;
5020
5021         entries_sp = ctx->qp_max_l2_entries +
5022                      ctx->vnic_max_vnic_entries +
5023                      2 * ctx->qp_min_qp1_entries + min;
5024         entries_sp = bnxt_roundup(entries_sp, ctx->tqm_entries_multiple);
5025
5026         entries = ctx->qp_max_l2_entries + ctx->qp_min_qp1_entries;
5027         entries = bnxt_roundup(entries, ctx->tqm_entries_multiple);
5028         entries = clamp_t(uint32_t, entries, min,
5029                           ctx->tqm_max_entries_per_ring);
5030         for (i = 0, ena = 0; i < ctx->tqm_fp_rings_count + 1; i++) {
5031                 ctx_pg = ctx->tqm_mem[i];
5032                 ctx_pg->entries = i ? entries : entries_sp;
5033                 mem_size = ctx->tqm_entry_size * ctx_pg->entries;
5034                 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "tqm_mem", i);
5035                 if (rc)
5036                         return rc;
5037                 ena |= HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_SP << i;
5038         }
5039
5040         ena |= FUNC_BACKING_STORE_CFG_INPUT_DFLT_ENABLES;
5041         rc = bnxt_hwrm_func_backing_store_cfg(bp, ena);
5042         if (rc)
5043                 PMD_DRV_LOG(ERR,
5044                             "Failed to configure context mem: rc = %d\n", rc);
5045         else
5046                 ctx->flags |= BNXT_CTX_FLAG_INITED;
5047
5048         return rc;
5049 }
5050
5051 static int bnxt_alloc_stats_mem(struct bnxt *bp)
5052 {
5053         struct rte_pci_device *pci_dev = bp->pdev;
5054         char mz_name[RTE_MEMZONE_NAMESIZE];
5055         const struct rte_memzone *mz = NULL;
5056         uint32_t total_alloc_len;
5057         rte_iova_t mz_phys_addr;
5058
5059         if (pci_dev->id.device_id == BROADCOM_DEV_ID_NS2)
5060                 return 0;
5061
5062         snprintf(mz_name, RTE_MEMZONE_NAMESIZE,
5063                  "bnxt_" PCI_PRI_FMT "-%s", pci_dev->addr.domain,
5064                  pci_dev->addr.bus, pci_dev->addr.devid,
5065                  pci_dev->addr.function, "rx_port_stats");
5066         mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0;
5067         mz = rte_memzone_lookup(mz_name);
5068         total_alloc_len =
5069                 RTE_CACHE_LINE_ROUNDUP(sizeof(struct rx_port_stats) +
5070                                        sizeof(struct rx_port_stats_ext) + 512);
5071         if (!mz) {
5072                 mz = rte_memzone_reserve(mz_name, total_alloc_len,
5073                                          SOCKET_ID_ANY,
5074                                          RTE_MEMZONE_2MB |
5075                                          RTE_MEMZONE_SIZE_HINT_ONLY |
5076                                          RTE_MEMZONE_IOVA_CONTIG);
5077                 if (mz == NULL)
5078                         return -ENOMEM;
5079         }
5080         memset(mz->addr, 0, mz->len);
5081         mz_phys_addr = mz->iova;
5082
5083         bp->rx_mem_zone = (const void *)mz;
5084         bp->hw_rx_port_stats = mz->addr;
5085         bp->hw_rx_port_stats_map = mz_phys_addr;
5086
5087         snprintf(mz_name, RTE_MEMZONE_NAMESIZE,
5088                  "bnxt_" PCI_PRI_FMT "-%s", pci_dev->addr.domain,
5089                  pci_dev->addr.bus, pci_dev->addr.devid,
5090                  pci_dev->addr.function, "tx_port_stats");
5091         mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0;
5092         mz = rte_memzone_lookup(mz_name);
5093         total_alloc_len =
5094                 RTE_CACHE_LINE_ROUNDUP(sizeof(struct tx_port_stats) +
5095                                        sizeof(struct tx_port_stats_ext) + 512);
5096         if (!mz) {
5097                 mz = rte_memzone_reserve(mz_name,
5098                                          total_alloc_len,
5099                                          SOCKET_ID_ANY,
5100                                          RTE_MEMZONE_2MB |
5101                                          RTE_MEMZONE_SIZE_HINT_ONLY |
5102                                          RTE_MEMZONE_IOVA_CONTIG);
5103                 if (mz == NULL)
5104                         return -ENOMEM;
5105         }
5106         memset(mz->addr, 0, mz->len);
5107         mz_phys_addr = mz->iova;
5108
5109         bp->tx_mem_zone = (const void *)mz;
5110         bp->hw_tx_port_stats = mz->addr;
5111         bp->hw_tx_port_stats_map = mz_phys_addr;
5112         bp->flags |= BNXT_FLAG_PORT_STATS;
5113
5114         /* Display extended statistics if FW supports it */
5115         if (bp->hwrm_spec_code < HWRM_SPEC_CODE_1_8_4 ||
5116             bp->hwrm_spec_code == HWRM_SPEC_CODE_1_9_0 ||
5117             !(bp->flags & BNXT_FLAG_EXT_STATS_SUPPORTED))
5118                 return 0;
5119
5120         bp->hw_rx_port_stats_ext = (void *)
5121                 ((uint8_t *)bp->hw_rx_port_stats +
5122                  sizeof(struct rx_port_stats));
5123         bp->hw_rx_port_stats_ext_map = bp->hw_rx_port_stats_map +
5124                 sizeof(struct rx_port_stats);
5125         bp->flags |= BNXT_FLAG_EXT_RX_PORT_STATS;
5126
5127         if (bp->hwrm_spec_code < HWRM_SPEC_CODE_1_9_2 ||
5128             bp->flags & BNXT_FLAG_EXT_STATS_SUPPORTED) {
5129                 bp->hw_tx_port_stats_ext = (void *)
5130                         ((uint8_t *)bp->hw_tx_port_stats +
5131                          sizeof(struct tx_port_stats));
5132                 bp->hw_tx_port_stats_ext_map =
5133                         bp->hw_tx_port_stats_map +
5134                         sizeof(struct tx_port_stats);
5135                 bp->flags |= BNXT_FLAG_EXT_TX_PORT_STATS;
5136         }
5137
5138         return 0;
5139 }
5140
5141 static int bnxt_setup_mac_addr(struct rte_eth_dev *eth_dev)
5142 {
5143         struct bnxt *bp = eth_dev->data->dev_private;
5144         int rc = 0;
5145
5146         eth_dev->data->mac_addrs = rte_zmalloc("bnxt_mac_addr_tbl",
5147                                                RTE_ETHER_ADDR_LEN *
5148                                                bp->max_l2_ctx,
5149                                                0);
5150         if (eth_dev->data->mac_addrs == NULL) {
5151                 PMD_DRV_LOG(ERR, "Failed to alloc MAC addr tbl\n");
5152                 return -ENOMEM;
5153         }
5154
5155         if (!BNXT_HAS_DFLT_MAC_SET(bp)) {
5156                 if (BNXT_PF(bp))
5157                         return -EINVAL;
5158
5159                 /* Generate a random MAC address, if none was assigned by PF */
5160                 PMD_DRV_LOG(INFO, "VF MAC address not assigned by Host PF\n");
5161                 bnxt_eth_hw_addr_random(bp->mac_addr);
5162                 PMD_DRV_LOG(INFO,
5163                             "Assign random MAC:%02X:%02X:%02X:%02X:%02X:%02X\n",
5164                             bp->mac_addr[0], bp->mac_addr[1], bp->mac_addr[2],
5165                             bp->mac_addr[3], bp->mac_addr[4], bp->mac_addr[5]);
5166
5167                 rc = bnxt_hwrm_set_mac(bp);
5168                 if (rc)
5169                         return rc;
5170         }
5171
5172         /* Copy the permanent MAC from the FUNC_QCAPS response */
5173         memcpy(&eth_dev->data->mac_addrs[0], bp->mac_addr, RTE_ETHER_ADDR_LEN);
5174
5175         return rc;
5176 }
5177
5178 static int bnxt_restore_dflt_mac(struct bnxt *bp)
5179 {
5180         int rc = 0;
5181
5182         /* MAC is already configured in FW */
5183         if (BNXT_HAS_DFLT_MAC_SET(bp))
5184                 return 0;
5185
5186         /* Restore the old MAC configured */
5187         rc = bnxt_hwrm_set_mac(bp);
5188         if (rc)
5189                 PMD_DRV_LOG(ERR, "Failed to restore MAC address\n");
5190
5191         return rc;
5192 }
5193
5194 static void bnxt_config_vf_req_fwd(struct bnxt *bp)
5195 {
5196         if (!BNXT_PF(bp))
5197                 return;
5198
5199         memset(bp->pf->vf_req_fwd, 0, sizeof(bp->pf->vf_req_fwd));
5200
5201         if (!(bp->fw_cap & BNXT_FW_CAP_LINK_ADMIN))
5202                 BNXT_HWRM_CMD_TO_FORWARD(HWRM_PORT_PHY_QCFG);
5203         BNXT_HWRM_CMD_TO_FORWARD(HWRM_FUNC_CFG);
5204         BNXT_HWRM_CMD_TO_FORWARD(HWRM_FUNC_VF_CFG);
5205         BNXT_HWRM_CMD_TO_FORWARD(HWRM_CFA_L2_FILTER_ALLOC);
5206         BNXT_HWRM_CMD_TO_FORWARD(HWRM_OEM_CMD);
5207 }
5208
5209 uint16_t
5210 bnxt_get_svif(uint16_t port_id, bool func_svif,
5211               enum bnxt_ulp_intf_type type)
5212 {
5213         struct rte_eth_dev *eth_dev;
5214         struct bnxt *bp;
5215
5216         eth_dev = &rte_eth_devices[port_id];
5217         if (BNXT_ETH_DEV_IS_REPRESENTOR(eth_dev)) {
5218                 struct bnxt_representor *vfr = eth_dev->data->dev_private;
5219                 if (!vfr)
5220                         return 0;
5221
5222                 if (type == BNXT_ULP_INTF_TYPE_VF_REP)
5223                         return vfr->svif;
5224
5225                 eth_dev = vfr->parent_dev;
5226         }
5227
5228         bp = eth_dev->data->dev_private;
5229
5230         return func_svif ? bp->func_svif : bp->port_svif;
5231 }
5232
5233 uint16_t
5234 bnxt_get_vnic_id(uint16_t port, enum bnxt_ulp_intf_type type)
5235 {
5236         struct rte_eth_dev *eth_dev;
5237         struct bnxt_vnic_info *vnic;
5238         struct bnxt *bp;
5239
5240         eth_dev = &rte_eth_devices[port];
5241         if (BNXT_ETH_DEV_IS_REPRESENTOR(eth_dev)) {
5242                 struct bnxt_representor *vfr = eth_dev->data->dev_private;
5243                 if (!vfr)
5244                         return 0;
5245
5246                 if (type == BNXT_ULP_INTF_TYPE_VF_REP)
5247                         return vfr->dflt_vnic_id;
5248
5249                 eth_dev = vfr->parent_dev;
5250         }
5251
5252         bp = eth_dev->data->dev_private;
5253
5254         vnic = BNXT_GET_DEFAULT_VNIC(bp);
5255
5256         return vnic->fw_vnic_id;
5257 }
5258
5259 uint16_t
5260 bnxt_get_fw_func_id(uint16_t port, enum bnxt_ulp_intf_type type)
5261 {
5262         struct rte_eth_dev *eth_dev;
5263         struct bnxt *bp;
5264
5265         eth_dev = &rte_eth_devices[port];
5266         if (BNXT_ETH_DEV_IS_REPRESENTOR(eth_dev)) {
5267                 struct bnxt_representor *vfr = eth_dev->data->dev_private;
5268                 if (!vfr)
5269                         return 0;
5270
5271                 if (type == BNXT_ULP_INTF_TYPE_VF_REP)
5272                         return vfr->fw_fid;
5273
5274                 eth_dev = vfr->parent_dev;
5275         }
5276
5277         bp = eth_dev->data->dev_private;
5278
5279         return bp->fw_fid;
5280 }
5281
5282 enum bnxt_ulp_intf_type
5283 bnxt_get_interface_type(uint16_t port)
5284 {
5285         struct rte_eth_dev *eth_dev;
5286         struct bnxt *bp;
5287
5288         eth_dev = &rte_eth_devices[port];
5289         if (BNXT_ETH_DEV_IS_REPRESENTOR(eth_dev))
5290                 return BNXT_ULP_INTF_TYPE_VF_REP;
5291
5292         bp = eth_dev->data->dev_private;
5293         if (BNXT_PF(bp))
5294                 return BNXT_ULP_INTF_TYPE_PF;
5295         else if (BNXT_VF_IS_TRUSTED(bp))
5296                 return BNXT_ULP_INTF_TYPE_TRUSTED_VF;
5297         else if (BNXT_VF(bp))
5298                 return BNXT_ULP_INTF_TYPE_VF;
5299
5300         return BNXT_ULP_INTF_TYPE_INVALID;
5301 }
5302
5303 uint16_t
5304 bnxt_get_phy_port_id(uint16_t port_id)
5305 {
5306         struct bnxt_representor *vfr;
5307         struct rte_eth_dev *eth_dev;
5308         struct bnxt *bp;
5309
5310         eth_dev = &rte_eth_devices[port_id];
5311         if (BNXT_ETH_DEV_IS_REPRESENTOR(eth_dev)) {
5312                 vfr = eth_dev->data->dev_private;
5313                 if (!vfr)
5314                         return 0;
5315
5316                 eth_dev = vfr->parent_dev;
5317         }
5318
5319         bp = eth_dev->data->dev_private;
5320
5321         return BNXT_PF(bp) ? bp->pf->port_id : bp->parent->port_id;
5322 }
5323
5324 uint16_t
5325 bnxt_get_parif(uint16_t port_id, enum bnxt_ulp_intf_type type)
5326 {
5327         struct rte_eth_dev *eth_dev;
5328         struct bnxt *bp;
5329
5330         eth_dev = &rte_eth_devices[port_id];
5331         if (BNXT_ETH_DEV_IS_REPRESENTOR(eth_dev)) {
5332                 struct bnxt_representor *vfr = eth_dev->data->dev_private;
5333                 if (!vfr)
5334                         return 0;
5335
5336                 if (type == BNXT_ULP_INTF_TYPE_VF_REP)
5337                         return vfr->fw_fid - 1;
5338
5339                 eth_dev = vfr->parent_dev;
5340         }
5341
5342         bp = eth_dev->data->dev_private;
5343
5344         return BNXT_PF(bp) ? bp->fw_fid - 1 : bp->parent->fid - 1;
5345 }
5346
5347 uint16_t
5348 bnxt_get_vport(uint16_t port_id)
5349 {
5350         return (1 << bnxt_get_phy_port_id(port_id));
5351 }
5352
5353 static void bnxt_alloc_error_recovery_info(struct bnxt *bp)
5354 {
5355         struct bnxt_error_recovery_info *info = bp->recovery_info;
5356
5357         if (info) {
5358                 if (!(bp->fw_cap & BNXT_FW_CAP_HCOMM_FW_STATUS))
5359                         memset(info, 0, sizeof(*info));
5360                 return;
5361         }
5362
5363         if (!(bp->fw_cap & BNXT_FW_CAP_ERROR_RECOVERY))
5364                 return;
5365
5366         info = rte_zmalloc("bnxt_hwrm_error_recovery_qcfg",
5367                            sizeof(*info), 0);
5368         if (!info)
5369                 bp->fw_cap &= ~BNXT_FW_CAP_ERROR_RECOVERY;
5370
5371         bp->recovery_info = info;
5372 }
5373
5374 static void bnxt_check_fw_status(struct bnxt *bp)
5375 {
5376         uint32_t fw_status;
5377
5378         if (!(bp->recovery_info &&
5379               (bp->fw_cap & BNXT_FW_CAP_HCOMM_FW_STATUS)))
5380                 return;
5381
5382         fw_status = bnxt_read_fw_status_reg(bp, BNXT_FW_STATUS_REG);
5383         if (fw_status != BNXT_FW_STATUS_HEALTHY)
5384                 PMD_DRV_LOG(ERR, "Firmware not responding, status: %#x\n",
5385                             fw_status);
5386 }
5387
5388 static int bnxt_map_hcomm_fw_status_reg(struct bnxt *bp)
5389 {
5390         struct bnxt_error_recovery_info *info = bp->recovery_info;
5391         uint32_t status_loc;
5392         uint32_t sig_ver;
5393
5394         rte_write32(HCOMM_STATUS_STRUCT_LOC, (uint8_t *)bp->bar0 +
5395                     BNXT_GRCPF_REG_WINDOW_BASE_OUT + 4);
5396         sig_ver = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
5397                                    BNXT_GRCP_WINDOW_2_BASE +
5398                                    offsetof(struct hcomm_status,
5399                                             sig_ver)));
5400         /* If the signature is absent, then FW does not support this feature */
5401         if ((sig_ver & HCOMM_STATUS_SIGNATURE_MASK) !=
5402             HCOMM_STATUS_SIGNATURE_VAL)
5403                 return 0;
5404
5405         if (!info) {
5406                 info = rte_zmalloc("bnxt_hwrm_error_recovery_qcfg",
5407                                    sizeof(*info), 0);
5408                 if (!info)
5409                         return -ENOMEM;
5410                 bp->recovery_info = info;
5411         } else {
5412                 memset(info, 0, sizeof(*info));
5413         }
5414
5415         status_loc = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
5416                                       BNXT_GRCP_WINDOW_2_BASE +
5417                                       offsetof(struct hcomm_status,
5418                                                fw_status_loc)));
5419
5420         /* Only pre-map the FW health status GRC register */
5421         if (BNXT_FW_STATUS_REG_TYPE(status_loc) != BNXT_FW_STATUS_REG_TYPE_GRC)
5422                 return 0;
5423
5424         info->status_regs[BNXT_FW_STATUS_REG] = status_loc;
5425         info->mapped_status_regs[BNXT_FW_STATUS_REG] =
5426                 BNXT_GRCP_WINDOW_2_BASE + (status_loc & BNXT_GRCP_OFFSET_MASK);
5427
5428         rte_write32((status_loc & BNXT_GRCP_BASE_MASK), (uint8_t *)bp->bar0 +
5429                     BNXT_GRCPF_REG_WINDOW_BASE_OUT + 4);
5430
5431         bp->fw_cap |= BNXT_FW_CAP_HCOMM_FW_STATUS;
5432
5433         return 0;
5434 }
5435
5436 static int bnxt_init_fw(struct bnxt *bp)
5437 {
5438         uint16_t mtu;
5439         int rc = 0;
5440
5441         bp->fw_cap = 0;
5442
5443         rc = bnxt_map_hcomm_fw_status_reg(bp);
5444         if (rc)
5445                 return rc;
5446
5447         rc = bnxt_hwrm_ver_get(bp, DFLT_HWRM_CMD_TIMEOUT);
5448         if (rc) {
5449                 bnxt_check_fw_status(bp);
5450                 return rc;
5451         }
5452
5453         rc = bnxt_hwrm_func_reset(bp);
5454         if (rc)
5455                 return -EIO;
5456
5457         rc = bnxt_hwrm_vnic_qcaps(bp);
5458         if (rc)
5459                 return rc;
5460
5461         rc = bnxt_hwrm_queue_qportcfg(bp);
5462         if (rc)
5463                 return rc;
5464
5465         /* Get the MAX capabilities for this function.
5466          * This function also allocates context memory for TQM rings and
5467          * informs the firmware about this allocated backing store memory.
5468          */
5469         rc = bnxt_hwrm_func_qcaps(bp);
5470         if (rc)
5471                 return rc;
5472
5473         rc = bnxt_hwrm_func_qcfg(bp, &mtu);
5474         if (rc)
5475                 return rc;
5476
5477         bnxt_hwrm_port_mac_qcfg(bp);
5478
5479         bnxt_hwrm_parent_pf_qcfg(bp);
5480
5481         bnxt_hwrm_port_phy_qcaps(bp);
5482
5483         bnxt_alloc_error_recovery_info(bp);
5484         /* Get the adapter error recovery support info */
5485         rc = bnxt_hwrm_error_recovery_qcfg(bp);
5486         if (rc)
5487                 bp->fw_cap &= ~BNXT_FW_CAP_ERROR_RECOVERY;
5488
5489         bnxt_hwrm_port_led_qcaps(bp);
5490
5491         return 0;
5492 }
5493
5494 static int
5495 bnxt_init_locks(struct bnxt *bp)
5496 {
5497         int err;
5498
5499         err = pthread_mutex_init(&bp->flow_lock, NULL);
5500         if (err) {
5501                 PMD_DRV_LOG(ERR, "Unable to initialize flow_lock\n");
5502                 return err;
5503         }
5504
5505         err = pthread_mutex_init(&bp->def_cp_lock, NULL);
5506         if (err)
5507                 PMD_DRV_LOG(ERR, "Unable to initialize def_cp_lock\n");
5508
5509         err = pthread_mutex_init(&bp->health_check_lock, NULL);
5510         if (err)
5511                 PMD_DRV_LOG(ERR, "Unable to initialize health_check_lock\n");
5512         return err;
5513 }
5514
5515 static int bnxt_init_resources(struct bnxt *bp, bool reconfig_dev)
5516 {
5517         int rc = 0;
5518
5519         rc = bnxt_init_fw(bp);
5520         if (rc)
5521                 return rc;
5522
5523         if (!reconfig_dev) {
5524                 rc = bnxt_setup_mac_addr(bp->eth_dev);
5525                 if (rc)
5526                         return rc;
5527         } else {
5528                 rc = bnxt_restore_dflt_mac(bp);
5529                 if (rc)
5530                         return rc;
5531         }
5532
5533         bnxt_config_vf_req_fwd(bp);
5534
5535         rc = bnxt_hwrm_func_driver_register(bp);
5536         if (rc) {
5537                 PMD_DRV_LOG(ERR, "Failed to register driver");
5538                 return -EBUSY;
5539         }
5540
5541         if (BNXT_PF(bp)) {
5542                 if (bp->pdev->max_vfs) {
5543                         rc = bnxt_hwrm_allocate_vfs(bp, bp->pdev->max_vfs);
5544                         if (rc) {
5545                                 PMD_DRV_LOG(ERR, "Failed to allocate VFs\n");
5546                                 return rc;
5547                         }
5548                 } else {
5549                         rc = bnxt_hwrm_allocate_pf_only(bp);
5550                         if (rc) {
5551                                 PMD_DRV_LOG(ERR,
5552                                             "Failed to allocate PF resources");
5553                                 return rc;
5554                         }
5555                 }
5556         }
5557
5558         rc = bnxt_alloc_mem(bp, reconfig_dev);
5559         if (rc)
5560                 return rc;
5561
5562         rc = bnxt_setup_int(bp);
5563         if (rc)
5564                 return rc;
5565
5566         rc = bnxt_request_int(bp);
5567         if (rc)
5568                 return rc;
5569
5570         rc = bnxt_init_ctx_mem(bp);
5571         if (rc) {
5572                 PMD_DRV_LOG(ERR, "Failed to init adv_flow_counters\n");
5573                 return rc;
5574         }
5575
5576         rc = bnxt_init_locks(bp);
5577         if (rc)
5578                 return rc;
5579
5580         return 0;
5581 }
5582
5583 static int
5584 bnxt_parse_devarg_truflow(__rte_unused const char *key,
5585                           const char *value, void *opaque_arg)
5586 {
5587         struct bnxt *bp = opaque_arg;
5588         unsigned long truflow;
5589         char *end = NULL;
5590
5591         if (!value || !opaque_arg) {
5592                 PMD_DRV_LOG(ERR,
5593                             "Invalid parameter passed to truflow devargs.\n");
5594                 return -EINVAL;
5595         }
5596
5597         truflow = strtoul(value, &end, 10);
5598         if (end == NULL || *end != '\0' ||
5599             (truflow == ULONG_MAX && errno == ERANGE)) {
5600                 PMD_DRV_LOG(ERR,
5601                             "Invalid parameter passed to truflow devargs.\n");
5602                 return -EINVAL;
5603         }
5604
5605         if (BNXT_DEVARG_TRUFLOW_INVALID(truflow)) {
5606                 PMD_DRV_LOG(ERR,
5607                             "Invalid value passed to truflow devargs.\n");
5608                 return -EINVAL;
5609         }
5610
5611         if (truflow) {
5612                 bp->flags |= BNXT_FLAG_TRUFLOW_EN;
5613                 PMD_DRV_LOG(INFO, "Host-based truflow feature enabled.\n");
5614         } else {
5615                 bp->flags &= ~BNXT_FLAG_TRUFLOW_EN;
5616                 PMD_DRV_LOG(INFO, "Host-based truflow feature disabled.\n");
5617         }
5618
5619         return 0;
5620 }
5621
5622 static int
5623 bnxt_parse_devarg_flow_xstat(__rte_unused const char *key,
5624                              const char *value, void *opaque_arg)
5625 {
5626         struct bnxt *bp = opaque_arg;
5627         unsigned long flow_xstat;
5628         char *end = NULL;
5629
5630         if (!value || !opaque_arg) {
5631                 PMD_DRV_LOG(ERR,
5632                             "Invalid parameter passed to flow_xstat devarg.\n");
5633                 return -EINVAL;
5634         }
5635
5636         flow_xstat = strtoul(value, &end, 10);
5637         if (end == NULL || *end != '\0' ||
5638             (flow_xstat == ULONG_MAX && errno == ERANGE)) {
5639                 PMD_DRV_LOG(ERR,
5640                             "Invalid parameter passed to flow_xstat devarg.\n");
5641                 return -EINVAL;
5642         }
5643
5644         if (BNXT_DEVARG_FLOW_XSTAT_INVALID(flow_xstat)) {
5645                 PMD_DRV_LOG(ERR,
5646                             "Invalid value passed to flow_xstat devarg.\n");
5647                 return -EINVAL;
5648         }
5649
5650         bp->flags |= BNXT_FLAG_FLOW_XSTATS_EN;
5651         if (BNXT_FLOW_XSTATS_EN(bp))
5652                 PMD_DRV_LOG(INFO, "flow_xstat feature enabled.\n");
5653
5654         return 0;
5655 }
5656
5657 static int
5658 bnxt_parse_devarg_max_num_kflows(__rte_unused const char *key,
5659                                         const char *value, void *opaque_arg)
5660 {
5661         struct bnxt *bp = opaque_arg;
5662         unsigned long max_num_kflows;
5663         char *end = NULL;
5664
5665         if (!value || !opaque_arg) {
5666                 PMD_DRV_LOG(ERR,
5667                         "Invalid parameter passed to max_num_kflows devarg.\n");
5668                 return -EINVAL;
5669         }
5670
5671         max_num_kflows = strtoul(value, &end, 10);
5672         if (end == NULL || *end != '\0' ||
5673                 (max_num_kflows == ULONG_MAX && errno == ERANGE)) {
5674                 PMD_DRV_LOG(ERR,
5675                         "Invalid parameter passed to max_num_kflows devarg.\n");
5676                 return -EINVAL;
5677         }
5678
5679         if (bnxt_devarg_max_num_kflow_invalid(max_num_kflows)) {
5680                 PMD_DRV_LOG(ERR,
5681                         "Invalid value passed to max_num_kflows devarg.\n");
5682                 return -EINVAL;
5683         }
5684
5685         bp->max_num_kflows = max_num_kflows;
5686         if (bp->max_num_kflows)
5687                 PMD_DRV_LOG(INFO, "max_num_kflows set as %ldK.\n",
5688                                 max_num_kflows);
5689
5690         return 0;
5691 }
5692
5693 static int
5694 bnxt_parse_devarg_rep_is_pf(__rte_unused const char *key,
5695                             const char *value, void *opaque_arg)
5696 {
5697         struct bnxt_representor *vfr_bp = opaque_arg;
5698         unsigned long rep_is_pf;
5699         char *end = NULL;
5700
5701         if (!value || !opaque_arg) {
5702                 PMD_DRV_LOG(ERR,
5703                             "Invalid parameter passed to rep_is_pf devargs.\n");
5704                 return -EINVAL;
5705         }
5706
5707         rep_is_pf = strtoul(value, &end, 10);
5708         if (end == NULL || *end != '\0' ||
5709             (rep_is_pf == ULONG_MAX && errno == ERANGE)) {
5710                 PMD_DRV_LOG(ERR,
5711                             "Invalid parameter passed to rep_is_pf devargs.\n");
5712                 return -EINVAL;
5713         }
5714
5715         if (BNXT_DEVARG_REP_IS_PF_INVALID(rep_is_pf)) {
5716                 PMD_DRV_LOG(ERR,
5717                             "Invalid value passed to rep_is_pf devargs.\n");
5718                 return -EINVAL;
5719         }
5720
5721         vfr_bp->flags |= rep_is_pf;
5722         if (BNXT_REP_PF(vfr_bp))
5723                 PMD_DRV_LOG(INFO, "PF representor\n");
5724         else
5725                 PMD_DRV_LOG(INFO, "VF representor\n");
5726
5727         return 0;
5728 }
5729
5730 static int
5731 bnxt_parse_devarg_rep_based_pf(__rte_unused const char *key,
5732                                const char *value, void *opaque_arg)
5733 {
5734         struct bnxt_representor *vfr_bp = opaque_arg;
5735         unsigned long rep_based_pf;
5736         char *end = NULL;
5737
5738         if (!value || !opaque_arg) {
5739                 PMD_DRV_LOG(ERR,
5740                             "Invalid parameter passed to rep_based_pf "
5741                             "devargs.\n");
5742                 return -EINVAL;
5743         }
5744
5745         rep_based_pf = strtoul(value, &end, 10);
5746         if (end == NULL || *end != '\0' ||
5747             (rep_based_pf == ULONG_MAX && errno == ERANGE)) {
5748                 PMD_DRV_LOG(ERR,
5749                             "Invalid parameter passed to rep_based_pf "
5750                             "devargs.\n");
5751                 return -EINVAL;
5752         }
5753
5754         if (BNXT_DEVARG_REP_BASED_PF_INVALID(rep_based_pf)) {
5755                 PMD_DRV_LOG(ERR,
5756                             "Invalid value passed to rep_based_pf devargs.\n");
5757                 return -EINVAL;
5758         }
5759
5760         vfr_bp->rep_based_pf = rep_based_pf;
5761         PMD_DRV_LOG(INFO, "rep-based-pf = %d\n", vfr_bp->rep_based_pf);
5762
5763         return 0;
5764 }
5765
5766 static int
5767 bnxt_parse_devarg_rep_q_r2f(__rte_unused const char *key,
5768                             const char *value, void *opaque_arg)
5769 {
5770         struct bnxt_representor *vfr_bp = opaque_arg;
5771         unsigned long rep_q_r2f;
5772         char *end = NULL;
5773
5774         if (!value || !opaque_arg) {
5775                 PMD_DRV_LOG(ERR,
5776                             "Invalid parameter passed to rep_q_r2f "
5777                             "devargs.\n");
5778                 return -EINVAL;
5779         }
5780
5781         rep_q_r2f = strtoul(value, &end, 10);
5782         if (end == NULL || *end != '\0' ||
5783             (rep_q_r2f == ULONG_MAX && errno == ERANGE)) {
5784                 PMD_DRV_LOG(ERR,
5785                             "Invalid parameter passed to rep_q_r2f "
5786                             "devargs.\n");
5787                 return -EINVAL;
5788         }
5789
5790         if (BNXT_DEVARG_REP_Q_R2F_INVALID(rep_q_r2f)) {
5791                 PMD_DRV_LOG(ERR,
5792                             "Invalid value passed to rep_q_r2f devargs.\n");
5793                 return -EINVAL;
5794         }
5795
5796         vfr_bp->rep_q_r2f = rep_q_r2f;
5797         vfr_bp->flags |= BNXT_REP_Q_R2F_VALID;
5798         PMD_DRV_LOG(INFO, "rep-q-r2f = %d\n", vfr_bp->rep_q_r2f);
5799
5800         return 0;
5801 }
5802
5803 static int
5804 bnxt_parse_devarg_rep_q_f2r(__rte_unused const char *key,
5805                             const char *value, void *opaque_arg)
5806 {
5807         struct bnxt_representor *vfr_bp = opaque_arg;
5808         unsigned long rep_q_f2r;
5809         char *end = NULL;
5810
5811         if (!value || !opaque_arg) {
5812                 PMD_DRV_LOG(ERR,
5813                             "Invalid parameter passed to rep_q_f2r "
5814                             "devargs.\n");
5815                 return -EINVAL;
5816         }
5817
5818         rep_q_f2r = strtoul(value, &end, 10);
5819         if (end == NULL || *end != '\0' ||
5820             (rep_q_f2r == ULONG_MAX && errno == ERANGE)) {
5821                 PMD_DRV_LOG(ERR,
5822                             "Invalid parameter passed to rep_q_f2r "
5823                             "devargs.\n");
5824                 return -EINVAL;
5825         }
5826
5827         if (BNXT_DEVARG_REP_Q_F2R_INVALID(rep_q_f2r)) {
5828                 PMD_DRV_LOG(ERR,
5829                             "Invalid value passed to rep_q_f2r devargs.\n");
5830                 return -EINVAL;
5831         }
5832
5833         vfr_bp->rep_q_f2r = rep_q_f2r;
5834         vfr_bp->flags |= BNXT_REP_Q_F2R_VALID;
5835         PMD_DRV_LOG(INFO, "rep-q-f2r = %d\n", vfr_bp->rep_q_f2r);
5836
5837         return 0;
5838 }
5839
5840 static int
5841 bnxt_parse_devarg_rep_fc_r2f(__rte_unused const char *key,
5842                              const char *value, void *opaque_arg)
5843 {
5844         struct bnxt_representor *vfr_bp = opaque_arg;
5845         unsigned long rep_fc_r2f;
5846         char *end = NULL;
5847
5848         if (!value || !opaque_arg) {
5849                 PMD_DRV_LOG(ERR,
5850                             "Invalid parameter passed to rep_fc_r2f "
5851                             "devargs.\n");
5852                 return -EINVAL;
5853         }
5854
5855         rep_fc_r2f = strtoul(value, &end, 10);
5856         if (end == NULL || *end != '\0' ||
5857             (rep_fc_r2f == ULONG_MAX && errno == ERANGE)) {
5858                 PMD_DRV_LOG(ERR,
5859                             "Invalid parameter passed to rep_fc_r2f "
5860                             "devargs.\n");
5861                 return -EINVAL;
5862         }
5863
5864         if (BNXT_DEVARG_REP_FC_R2F_INVALID(rep_fc_r2f)) {
5865                 PMD_DRV_LOG(ERR,
5866                             "Invalid value passed to rep_fc_r2f devargs.\n");
5867                 return -EINVAL;
5868         }
5869
5870         vfr_bp->flags |= BNXT_REP_FC_R2F_VALID;
5871         vfr_bp->rep_fc_r2f = rep_fc_r2f;
5872         PMD_DRV_LOG(INFO, "rep-fc-r2f = %lu\n", rep_fc_r2f);
5873
5874         return 0;
5875 }
5876
5877 static int
5878 bnxt_parse_devarg_rep_fc_f2r(__rte_unused const char *key,
5879                              const char *value, void *opaque_arg)
5880 {
5881         struct bnxt_representor *vfr_bp = opaque_arg;
5882         unsigned long rep_fc_f2r;
5883         char *end = NULL;
5884
5885         if (!value || !opaque_arg) {
5886                 PMD_DRV_LOG(ERR,
5887                             "Invalid parameter passed to rep_fc_f2r "
5888                             "devargs.\n");
5889                 return -EINVAL;
5890         }
5891
5892         rep_fc_f2r = strtoul(value, &end, 10);
5893         if (end == NULL || *end != '\0' ||
5894             (rep_fc_f2r == ULONG_MAX && errno == ERANGE)) {
5895                 PMD_DRV_LOG(ERR,
5896                             "Invalid parameter passed to rep_fc_f2r "
5897                             "devargs.\n");
5898                 return -EINVAL;
5899         }
5900
5901         if (BNXT_DEVARG_REP_FC_F2R_INVALID(rep_fc_f2r)) {
5902                 PMD_DRV_LOG(ERR,
5903                             "Invalid value passed to rep_fc_f2r devargs.\n");
5904                 return -EINVAL;
5905         }
5906
5907         vfr_bp->flags |= BNXT_REP_FC_F2R_VALID;
5908         vfr_bp->rep_fc_f2r = rep_fc_f2r;
5909         PMD_DRV_LOG(INFO, "rep-fc-f2r = %lu\n", rep_fc_f2r);
5910
5911         return 0;
5912 }
5913
5914 static void
5915 bnxt_parse_dev_args(struct bnxt *bp, struct rte_devargs *devargs)
5916 {
5917         struct rte_kvargs *kvlist;
5918
5919         if (devargs == NULL)
5920                 return;
5921
5922         kvlist = rte_kvargs_parse(devargs->args, bnxt_dev_args);
5923         if (kvlist == NULL)
5924                 return;
5925
5926         /*
5927          * Handler for "truflow" devarg.
5928          * Invoked as for ex: "-w 0000:00:0d.0,host-based-truflow=1"
5929          */
5930         rte_kvargs_process(kvlist, BNXT_DEVARG_TRUFLOW,
5931                            bnxt_parse_devarg_truflow, bp);
5932
5933         /*
5934          * Handler for "flow_xstat" devarg.
5935          * Invoked as for ex: "-w 0000:00:0d.0,flow_xstat=1"
5936          */
5937         rte_kvargs_process(kvlist, BNXT_DEVARG_FLOW_XSTAT,
5938                            bnxt_parse_devarg_flow_xstat, bp);
5939
5940         /*
5941          * Handler for "max_num_kflows" devarg.
5942          * Invoked as for ex: "-w 000:00:0d.0,max_num_kflows=32"
5943          */
5944         rte_kvargs_process(kvlist, BNXT_DEVARG_MAX_NUM_KFLOWS,
5945                            bnxt_parse_devarg_max_num_kflows, bp);
5946
5947         rte_kvargs_free(kvlist);
5948 }
5949
5950 static int bnxt_alloc_switch_domain(struct bnxt *bp)
5951 {
5952         int rc = 0;
5953
5954         if (BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp)) {
5955                 rc = rte_eth_switch_domain_alloc(&bp->switch_domain_id);
5956                 if (rc)
5957                         PMD_DRV_LOG(ERR,
5958                                     "Failed to alloc switch domain: %d\n", rc);
5959                 else
5960                         PMD_DRV_LOG(INFO,
5961                                     "Switch domain allocated %d\n",
5962                                     bp->switch_domain_id);
5963         }
5964
5965         return rc;
5966 }
5967
5968 static int
5969 bnxt_dev_init(struct rte_eth_dev *eth_dev, void *params __rte_unused)
5970 {
5971         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
5972         static int version_printed;
5973         struct bnxt *bp;
5974         int rc;
5975
5976         if (version_printed++ == 0)
5977                 PMD_DRV_LOG(INFO, "%s\n", bnxt_version);
5978
5979         eth_dev->dev_ops = &bnxt_dev_ops;
5980         eth_dev->rx_queue_count = bnxt_rx_queue_count_op;
5981         eth_dev->rx_descriptor_status = bnxt_rx_descriptor_status_op;
5982         eth_dev->tx_descriptor_status = bnxt_tx_descriptor_status_op;
5983         eth_dev->rx_pkt_burst = &bnxt_recv_pkts;
5984         eth_dev->tx_pkt_burst = &bnxt_xmit_pkts;
5985
5986         /*
5987          * For secondary processes, we don't initialise any further
5988          * as primary has already done this work.
5989          */
5990         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
5991                 return 0;
5992
5993         rte_eth_copy_pci_info(eth_dev, pci_dev);
5994
5995         bp = eth_dev->data->dev_private;
5996
5997         /* Parse dev arguments passed on when starting the DPDK application. */
5998         bnxt_parse_dev_args(bp, pci_dev->device.devargs);
5999
6000         bp->flags &= ~BNXT_FLAG_RX_VECTOR_PKT_MODE;
6001
6002         if (bnxt_vf_pciid(pci_dev->id.device_id))
6003                 bp->flags |= BNXT_FLAG_VF;
6004
6005         if (bnxt_thor_device(pci_dev->id.device_id))
6006                 bp->flags |= BNXT_FLAG_THOR_CHIP;
6007
6008         if (pci_dev->id.device_id == BROADCOM_DEV_ID_58802 ||
6009             pci_dev->id.device_id == BROADCOM_DEV_ID_58804 ||
6010             pci_dev->id.device_id == BROADCOM_DEV_ID_58808 ||
6011             pci_dev->id.device_id == BROADCOM_DEV_ID_58802_VF)
6012                 bp->flags |= BNXT_FLAG_STINGRAY;
6013
6014         rc = bnxt_init_board(eth_dev);
6015         if (rc) {
6016                 PMD_DRV_LOG(ERR,
6017                             "Failed to initialize board rc: %x\n", rc);
6018                 return rc;
6019         }
6020
6021         rc = bnxt_alloc_pf_info(bp);
6022         if (rc)
6023                 goto error_free;
6024
6025         rc = bnxt_alloc_link_info(bp);
6026         if (rc)
6027                 goto error_free;
6028
6029         rc = bnxt_alloc_parent_info(bp);
6030         if (rc)
6031                 goto error_free;
6032
6033         rc = bnxt_alloc_hwrm_resources(bp);
6034         if (rc) {
6035                 PMD_DRV_LOG(ERR,
6036                             "Failed to allocate hwrm resource rc: %x\n", rc);
6037                 goto error_free;
6038         }
6039         rc = bnxt_alloc_leds_info(bp);
6040         if (rc)
6041                 goto error_free;
6042
6043         rc = bnxt_alloc_cos_queues(bp);
6044         if (rc)
6045                 goto error_free;
6046
6047         rc = bnxt_init_resources(bp, false);
6048         if (rc)
6049                 goto error_free;
6050
6051         rc = bnxt_alloc_stats_mem(bp);
6052         if (rc)
6053                 goto error_free;
6054
6055         bnxt_alloc_switch_domain(bp);
6056
6057         PMD_DRV_LOG(INFO,
6058                     DRV_MODULE_NAME "found at mem %" PRIX64 ", node addr %pM\n",
6059                     pci_dev->mem_resource[0].phys_addr,
6060                     pci_dev->mem_resource[0].addr);
6061
6062         return 0;
6063
6064 error_free:
6065         bnxt_dev_uninit(eth_dev);
6066         return rc;
6067 }
6068
6069
6070 static void bnxt_free_ctx_mem_buf(struct bnxt_ctx_mem_buf_info *ctx)
6071 {
6072         if (!ctx)
6073                 return;
6074
6075         if (ctx->va)
6076                 rte_free(ctx->va);
6077
6078         ctx->va = NULL;
6079         ctx->dma = RTE_BAD_IOVA;
6080         ctx->ctx_id = BNXT_CTX_VAL_INVAL;
6081 }
6082
6083 static void bnxt_unregister_fc_ctx_mem(struct bnxt *bp)
6084 {
6085         bnxt_hwrm_cfa_counter_cfg(bp, BNXT_DIR_RX,
6086                                   CFA_COUNTER_CFG_IN_COUNTER_TYPE_FC,
6087                                   bp->flow_stat->rx_fc_out_tbl.ctx_id,
6088                                   bp->flow_stat->max_fc,
6089                                   false);
6090
6091         bnxt_hwrm_cfa_counter_cfg(bp, BNXT_DIR_TX,
6092                                   CFA_COUNTER_CFG_IN_COUNTER_TYPE_FC,
6093                                   bp->flow_stat->tx_fc_out_tbl.ctx_id,
6094                                   bp->flow_stat->max_fc,
6095                                   false);
6096
6097         if (bp->flow_stat->rx_fc_in_tbl.ctx_id != BNXT_CTX_VAL_INVAL)
6098                 bnxt_hwrm_ctx_unrgtr(bp, bp->flow_stat->rx_fc_in_tbl.ctx_id);
6099         bp->flow_stat->rx_fc_in_tbl.ctx_id = BNXT_CTX_VAL_INVAL;
6100
6101         if (bp->flow_stat->rx_fc_out_tbl.ctx_id != BNXT_CTX_VAL_INVAL)
6102                 bnxt_hwrm_ctx_unrgtr(bp, bp->flow_stat->rx_fc_out_tbl.ctx_id);
6103         bp->flow_stat->rx_fc_out_tbl.ctx_id = BNXT_CTX_VAL_INVAL;
6104
6105         if (bp->flow_stat->tx_fc_in_tbl.ctx_id != BNXT_CTX_VAL_INVAL)
6106                 bnxt_hwrm_ctx_unrgtr(bp, bp->flow_stat->tx_fc_in_tbl.ctx_id);
6107         bp->flow_stat->tx_fc_in_tbl.ctx_id = BNXT_CTX_VAL_INVAL;
6108
6109         if (bp->flow_stat->tx_fc_out_tbl.ctx_id != BNXT_CTX_VAL_INVAL)
6110                 bnxt_hwrm_ctx_unrgtr(bp, bp->flow_stat->tx_fc_out_tbl.ctx_id);
6111         bp->flow_stat->tx_fc_out_tbl.ctx_id = BNXT_CTX_VAL_INVAL;
6112 }
6113
6114 static void bnxt_uninit_fc_ctx_mem(struct bnxt *bp)
6115 {
6116         bnxt_unregister_fc_ctx_mem(bp);
6117
6118         bnxt_free_ctx_mem_buf(&bp->flow_stat->rx_fc_in_tbl);
6119         bnxt_free_ctx_mem_buf(&bp->flow_stat->rx_fc_out_tbl);
6120         bnxt_free_ctx_mem_buf(&bp->flow_stat->tx_fc_in_tbl);
6121         bnxt_free_ctx_mem_buf(&bp->flow_stat->tx_fc_out_tbl);
6122 }
6123
6124 static void bnxt_uninit_ctx_mem(struct bnxt *bp)
6125 {
6126         if (BNXT_FLOW_XSTATS_EN(bp))
6127                 bnxt_uninit_fc_ctx_mem(bp);
6128 }
6129
6130 static void
6131 bnxt_free_error_recovery_info(struct bnxt *bp)
6132 {
6133         rte_free(bp->recovery_info);
6134         bp->recovery_info = NULL;
6135         bp->fw_cap &= ~BNXT_FW_CAP_ERROR_RECOVERY;
6136 }
6137
6138 static void
6139 bnxt_uninit_locks(struct bnxt *bp)
6140 {
6141         pthread_mutex_destroy(&bp->flow_lock);
6142         pthread_mutex_destroy(&bp->def_cp_lock);
6143         pthread_mutex_destroy(&bp->health_check_lock);
6144         if (bp->rep_info) {
6145                 pthread_mutex_destroy(&bp->rep_info->vfr_lock);
6146                 pthread_mutex_destroy(&bp->rep_info->vfr_start_lock);
6147         }
6148 }
6149
6150 static int
6151 bnxt_uninit_resources(struct bnxt *bp, bool reconfig_dev)
6152 {
6153         int rc;
6154
6155         bnxt_free_int(bp);
6156         bnxt_free_mem(bp, reconfig_dev);
6157
6158         bnxt_hwrm_func_buf_unrgtr(bp);
6159         rte_free(bp->pf->vf_req_buf);
6160
6161         rc = bnxt_hwrm_func_driver_unregister(bp, 0);
6162         bp->flags &= ~BNXT_FLAG_REGISTERED;
6163         bnxt_free_ctx_mem(bp);
6164         if (!reconfig_dev) {
6165                 bnxt_free_hwrm_resources(bp);
6166                 bnxt_free_error_recovery_info(bp);
6167         }
6168
6169         bnxt_uninit_ctx_mem(bp);
6170
6171         bnxt_uninit_locks(bp);
6172         bnxt_free_flow_stats_info(bp);
6173         bnxt_free_rep_info(bp);
6174         rte_free(bp->ptp_cfg);
6175         bp->ptp_cfg = NULL;
6176         return rc;
6177 }
6178
6179 static int
6180 bnxt_dev_uninit(struct rte_eth_dev *eth_dev)
6181 {
6182         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
6183                 return -EPERM;
6184
6185         PMD_DRV_LOG(DEBUG, "Calling Device uninit\n");
6186
6187         if (eth_dev->state != RTE_ETH_DEV_UNUSED)
6188                 bnxt_dev_close_op(eth_dev);
6189
6190         return 0;
6191 }
6192
6193 static int bnxt_pci_remove_dev_with_reps(struct rte_eth_dev *eth_dev)
6194 {
6195         struct bnxt *bp = eth_dev->data->dev_private;
6196         struct rte_eth_dev *vf_rep_eth_dev;
6197         int ret = 0, i;
6198
6199         if (!bp)
6200                 return -EINVAL;
6201
6202         for (i = 0; i < bp->num_reps; i++) {
6203                 vf_rep_eth_dev = bp->rep_info[i].vfr_eth_dev;
6204                 if (!vf_rep_eth_dev)
6205                         continue;
6206                 PMD_DRV_LOG(DEBUG, "BNXT Port:%d VFR pci remove\n",
6207                             vf_rep_eth_dev->data->port_id);
6208                 rte_eth_dev_destroy(vf_rep_eth_dev, bnxt_representor_uninit);
6209         }
6210         PMD_DRV_LOG(DEBUG, "BNXT Port:%d pci remove\n",
6211                     eth_dev->data->port_id);
6212         ret = rte_eth_dev_destroy(eth_dev, bnxt_dev_uninit);
6213
6214         return ret;
6215 }
6216
6217 static void bnxt_free_rep_info(struct bnxt *bp)
6218 {
6219         rte_free(bp->rep_info);
6220         bp->rep_info = NULL;
6221         rte_free(bp->cfa_code_map);
6222         bp->cfa_code_map = NULL;
6223 }
6224
6225 static int bnxt_init_rep_info(struct bnxt *bp)
6226 {
6227         int i = 0, rc;
6228
6229         if (bp->rep_info)
6230                 return 0;
6231
6232         bp->rep_info = rte_zmalloc("bnxt_rep_info",
6233                                    sizeof(bp->rep_info[0]) * BNXT_MAX_VF_REPS,
6234                                    0);
6235         if (!bp->rep_info) {
6236                 PMD_DRV_LOG(ERR, "Failed to alloc memory for rep info\n");
6237                 return -ENOMEM;
6238         }
6239         bp->cfa_code_map = rte_zmalloc("bnxt_cfa_code_map",
6240                                        sizeof(*bp->cfa_code_map) *
6241                                        BNXT_MAX_CFA_CODE, 0);
6242         if (!bp->cfa_code_map) {
6243                 PMD_DRV_LOG(ERR, "Failed to alloc memory for cfa_code_map\n");
6244                 bnxt_free_rep_info(bp);
6245                 return -ENOMEM;
6246         }
6247
6248         for (i = 0; i < BNXT_MAX_CFA_CODE; i++)
6249                 bp->cfa_code_map[i] = BNXT_VF_IDX_INVALID;
6250
6251         rc = pthread_mutex_init(&bp->rep_info->vfr_lock, NULL);
6252         if (rc) {
6253                 PMD_DRV_LOG(ERR, "Unable to initialize vfr_lock\n");
6254                 bnxt_free_rep_info(bp);
6255                 return rc;
6256         }
6257
6258         rc = pthread_mutex_init(&bp->rep_info->vfr_start_lock, NULL);
6259         if (rc) {
6260                 PMD_DRV_LOG(ERR, "Unable to initialize vfr_start_lock\n");
6261                 bnxt_free_rep_info(bp);
6262                 return rc;
6263         }
6264
6265         return rc;
6266 }
6267
6268 static int bnxt_rep_port_probe(struct rte_pci_device *pci_dev,
6269                                struct rte_eth_devargs eth_da,
6270                                struct rte_eth_dev *backing_eth_dev,
6271                                const char *dev_args)
6272 {
6273         struct rte_eth_dev *vf_rep_eth_dev;
6274         char name[RTE_ETH_NAME_MAX_LEN];
6275         struct bnxt *backing_bp;
6276         uint16_t num_rep;
6277         int i, ret = 0;
6278         struct rte_kvargs *kvlist;
6279
6280         num_rep = eth_da.nb_representor_ports;
6281         if (num_rep > BNXT_MAX_VF_REPS) {
6282                 PMD_DRV_LOG(ERR, "nb_representor_ports = %d > %d MAX VF REPS\n",
6283                             num_rep, BNXT_MAX_VF_REPS);
6284                 return -EINVAL;
6285         }
6286
6287         if (num_rep >= RTE_MAX_ETHPORTS) {
6288                 PMD_DRV_LOG(ERR,
6289                             "nb_representor_ports = %d > %d MAX ETHPORTS\n",
6290                             num_rep, RTE_MAX_ETHPORTS);
6291                 return -EINVAL;
6292         }
6293
6294         backing_bp = backing_eth_dev->data->dev_private;
6295
6296         if (!(BNXT_PF(backing_bp) || BNXT_VF_IS_TRUSTED(backing_bp))) {
6297                 PMD_DRV_LOG(ERR,
6298                             "Not a PF or trusted VF. No Representor support\n");
6299                 /* Returning an error is not an option.
6300                  * Applications are not handling this correctly
6301                  */
6302                 return 0;
6303         }
6304
6305         if (bnxt_init_rep_info(backing_bp))
6306                 return 0;
6307
6308         for (i = 0; i < num_rep; i++) {
6309                 struct bnxt_representor representor = {
6310                         .vf_id = eth_da.representor_ports[i],
6311                         .switch_domain_id = backing_bp->switch_domain_id,
6312                         .parent_dev = backing_eth_dev
6313                 };
6314
6315                 if (representor.vf_id >= BNXT_MAX_VF_REPS) {
6316                         PMD_DRV_LOG(ERR, "VF-Rep id %d >= %d MAX VF ID\n",
6317                                     representor.vf_id, BNXT_MAX_VF_REPS);
6318                         continue;
6319                 }
6320
6321                 /* representor port net_bdf_port */
6322                 snprintf(name, sizeof(name), "net_%s_representor_%d",
6323                          pci_dev->device.name, eth_da.representor_ports[i]);
6324
6325                 kvlist = rte_kvargs_parse(dev_args, bnxt_dev_args);
6326                 if (kvlist) {
6327                         /*
6328                          * Handler for "rep_is_pf" devarg.
6329                          * Invoked as for ex: "-w 000:00:0d.0,
6330                          * rep-based-pf=<pf index> rep-is-pf=<VF=0 or PF=1>"
6331                          */
6332                         rte_kvargs_process(kvlist, BNXT_DEVARG_REP_IS_PF,
6333                                            bnxt_parse_devarg_rep_is_pf,
6334                                            (void *)&representor);
6335                         /*
6336                          * Handler for "rep_based_pf" devarg.
6337                          * Invoked as for ex: "-w 000:00:0d.0,
6338                          * rep-based-pf=<pf index> rep-is-pf=<VF=0 or PF=1>"
6339                          */
6340                         rte_kvargs_process(kvlist, BNXT_DEVARG_REP_BASED_PF,
6341                                            bnxt_parse_devarg_rep_based_pf,
6342                                            (void *)&representor);
6343                         /*
6344                          * Handler for "rep_based_pf" devarg.
6345                          * Invoked as for ex: "-w 000:00:0d.0,
6346                          * rep-based-pf=<pf index> rep-is-pf=<VF=0 or PF=1>"
6347                          */
6348                         rte_kvargs_process(kvlist, BNXT_DEVARG_REP_Q_R2F,
6349                                            bnxt_parse_devarg_rep_q_r2f,
6350                                            (void *)&representor);
6351                         /*
6352                          * Handler for "rep_based_pf" devarg.
6353                          * Invoked as for ex: "-w 000:00:0d.0,
6354                          * rep-based-pf=<pf index> rep-is-pf=<VF=0 or PF=1>"
6355                          */
6356                         rte_kvargs_process(kvlist, BNXT_DEVARG_REP_Q_F2R,
6357                                            bnxt_parse_devarg_rep_q_f2r,
6358                                            (void *)&representor);
6359                         /*
6360                          * Handler for "rep_based_pf" devarg.
6361                          * Invoked as for ex: "-w 000:00:0d.0,
6362                          * rep-based-pf=<pf index> rep-is-pf=<VF=0 or PF=1>"
6363                          */
6364                         rte_kvargs_process(kvlist, BNXT_DEVARG_REP_FC_R2F,
6365                                            bnxt_parse_devarg_rep_fc_r2f,
6366                                            (void *)&representor);
6367                         /*
6368                          * Handler for "rep_based_pf" devarg.
6369                          * Invoked as for ex: "-w 000:00:0d.0,
6370                          * rep-based-pf=<pf index> rep-is-pf=<VF=0 or PF=1>"
6371                          */
6372                         rte_kvargs_process(kvlist, BNXT_DEVARG_REP_FC_F2R,
6373                                            bnxt_parse_devarg_rep_fc_f2r,
6374                                            (void *)&representor);
6375                 }
6376
6377                 ret = rte_eth_dev_create(&pci_dev->device, name,
6378                                          sizeof(struct bnxt_representor),
6379                                          NULL, NULL,
6380                                          bnxt_representor_init,
6381                                          &representor);
6382                 if (ret) {
6383                         PMD_DRV_LOG(ERR, "failed to create bnxt vf "
6384                                     "representor %s.", name);
6385                         goto err;
6386                 }
6387
6388                 vf_rep_eth_dev = rte_eth_dev_allocated(name);
6389                 if (!vf_rep_eth_dev) {
6390                         PMD_DRV_LOG(ERR, "Failed to find the eth_dev"
6391                                     " for VF-Rep: %s.", name);
6392                         ret = -ENODEV;
6393                         goto err;
6394                 }
6395
6396                 PMD_DRV_LOG(DEBUG, "BNXT Port:%d VFR pci probe\n",
6397                             backing_eth_dev->data->port_id);
6398                 backing_bp->rep_info[representor.vf_id].vfr_eth_dev =
6399                                                          vf_rep_eth_dev;
6400                 backing_bp->num_reps++;
6401
6402         }
6403
6404         return 0;
6405
6406 err:
6407         /* If num_rep > 1, then rollback already created
6408          * ports, since we'll be failing the probe anyway
6409          */
6410         if (num_rep > 1)
6411                 bnxt_pci_remove_dev_with_reps(backing_eth_dev);
6412
6413         return ret;
6414 }
6415
6416 static int bnxt_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
6417                           struct rte_pci_device *pci_dev)
6418 {
6419         struct rte_eth_devargs eth_da = { .nb_representor_ports = 0 };
6420         struct rte_eth_dev *backing_eth_dev;
6421         uint16_t num_rep;
6422         int ret = 0;
6423
6424         if (pci_dev->device.devargs) {
6425                 ret = rte_eth_devargs_parse(pci_dev->device.devargs->args,
6426                                             &eth_da);
6427                 if (ret)
6428                         return ret;
6429         }
6430
6431         num_rep = eth_da.nb_representor_ports;
6432         PMD_DRV_LOG(DEBUG, "nb_representor_ports = %d\n",
6433                     num_rep);
6434
6435         /* We could come here after first level of probe is already invoked
6436          * as part of an application bringup(OVS-DPDK vswitchd), so first check
6437          * for already allocated eth_dev for the backing device (PF/Trusted VF)
6438          */
6439         backing_eth_dev = rte_eth_dev_allocated(pci_dev->device.name);
6440         if (backing_eth_dev == NULL) {
6441                 ret = rte_eth_dev_create(&pci_dev->device, pci_dev->device.name,
6442                                          sizeof(struct bnxt),
6443                                          eth_dev_pci_specific_init, pci_dev,
6444                                          bnxt_dev_init, NULL);
6445
6446                 if (ret || !num_rep)
6447                         return ret;
6448
6449                 backing_eth_dev = rte_eth_dev_allocated(pci_dev->device.name);
6450         }
6451         PMD_DRV_LOG(DEBUG, "BNXT Port:%d pci probe\n",
6452                     backing_eth_dev->data->port_id);
6453
6454         if (!num_rep)
6455                 return ret;
6456
6457         /* probe representor ports now */
6458         ret = bnxt_rep_port_probe(pci_dev, eth_da, backing_eth_dev,
6459                                   pci_dev->device.devargs->args);
6460
6461         return ret;
6462 }
6463
6464 static int bnxt_pci_remove(struct rte_pci_device *pci_dev)
6465 {
6466         struct rte_eth_dev *eth_dev;
6467
6468         eth_dev = rte_eth_dev_allocated(pci_dev->device.name);
6469         if (!eth_dev)
6470                 return 0; /* Invoked typically only by OVS-DPDK, by the
6471                            * time it comes here the eth_dev is already
6472                            * deleted by rte_eth_dev_close(), so returning
6473                            * +ve value will at least help in proper cleanup
6474                            */
6475
6476         PMD_DRV_LOG(DEBUG, "BNXT Port:%d pci remove\n", eth_dev->data->port_id);
6477         if (rte_eal_process_type() == RTE_PROC_PRIMARY) {
6478                 if (eth_dev->data->dev_flags & RTE_ETH_DEV_REPRESENTOR)
6479                         return rte_eth_dev_destroy(eth_dev,
6480                                                    bnxt_representor_uninit);
6481                 else
6482                         return rte_eth_dev_destroy(eth_dev,
6483                                                    bnxt_dev_uninit);
6484         } else {
6485                 return rte_eth_dev_pci_generic_remove(pci_dev, NULL);
6486         }
6487 }
6488
6489 static struct rte_pci_driver bnxt_rte_pmd = {
6490         .id_table = bnxt_pci_id_map,
6491         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC |
6492                         RTE_PCI_DRV_PROBE_AGAIN, /* Needed in case of VF-REPs
6493                                                   * and OVS-DPDK
6494                                                   */
6495         .probe = bnxt_pci_probe,
6496         .remove = bnxt_pci_remove,
6497 };
6498
6499 static bool
6500 is_device_supported(struct rte_eth_dev *dev, struct rte_pci_driver *drv)
6501 {
6502         if (strcmp(dev->device->driver->name, drv->driver.name))
6503                 return false;
6504
6505         return true;
6506 }
6507
6508 bool is_bnxt_supported(struct rte_eth_dev *dev)
6509 {
6510         return is_device_supported(dev, &bnxt_rte_pmd);
6511 }
6512
6513 RTE_LOG_REGISTER(bnxt_logtype_driver, pmd.net.bnxt.driver, NOTICE);
6514 RTE_PMD_REGISTER_PCI(net_bnxt, bnxt_rte_pmd);
6515 RTE_PMD_REGISTER_PCI_TABLE(net_bnxt, bnxt_pci_id_map);
6516 RTE_PMD_REGISTER_KMOD_DEP(net_bnxt, "* igb_uio | uio_pci_generic | vfio-pci");