drivers/net/bnxt/bnxt_ethdev.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2014-2018 Broadcom
   3  * All rights reserved.
   4  */
   5
   6 #include <inttypes.h>
   7 #include <stdbool.h>
   8
   9 #include <rte_dev.h>
  10 #include <rte_ethdev_driver.h>
  11 #include <rte_ethdev_pci.h>
  12 #include <rte_malloc.h>
  13 #include <rte_cycles.h>
  14 #include <rte_alarm.h>
  15 #include <rte_kvargs.h>
  16
  17 #include "bnxt.h"
  18 #include "bnxt_filter.h"
  19 #include "bnxt_hwrm.h"
  20 #include "bnxt_irq.h"
  21 #include "bnxt_reps.h"
  22 #include "bnxt_ring.h"
  23 #include "bnxt_rxq.h"
  24 #include "bnxt_rxr.h"
  25 #include "bnxt_stats.h"
  26 #include "bnxt_txq.h"
  27 #include "bnxt_txr.h"
  28 #include "bnxt_vnic.h"
  29 #include "hsi_struct_def_dpdk.h"
  30 #include "bnxt_nvm_defs.h"
  31 #include "bnxt_tf_common.h"
  32 #include "ulp_flow_db.h"
  33
  34 #define DRV_MODULE_NAME         "bnxt"
  35 static const char bnxt_version[] =
  36         "Broadcom NetXtreme driver " DRV_MODULE_NAME;
  37
  38 /*
  39  * The set of PCI devices this driver supports
  40  */
  41 static const struct rte_pci_id bnxt_pci_id_map[] = {
  42         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM,
  43                          BROADCOM_DEV_ID_STRATUS_NIC_VF1) },
  44         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM,
  45                          BROADCOM_DEV_ID_STRATUS_NIC_VF2) },
  46         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_STRATUS_NIC) },
  47         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414_VF) },
  48         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57301) },
  49         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57302) },
  50         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57304_PF) },
  51         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57304_VF) },
  52         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_NS2) },
  53         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57402) },
  54         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57404) },
  55         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57406_PF) },
  56         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57406_VF) },
  57         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57402_MF) },
  58         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57407_RJ45) },
  59         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57404_MF) },
  60         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57406_MF) },
  61         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57407_SFP) },
  62         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57407_MF) },
  63         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_5741X_VF) },
  64         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_5731X_VF) },
  65         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57314) },
  66         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_MF) },
  67         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57311) },
  68         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57312) },
  69         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57412) },
  70         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414) },
  71         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_RJ45) },
  72         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_RJ45) },
  73         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57412_MF) },
  74         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57317_RJ45) },
  75         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_SFP) },
  76         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_SFP) },
  77         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57317_SFP) },
  78         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414_MF) },
  79         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_MF) },
  80         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58802) },
  81         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58804) },
  82         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58808) },
  83         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58802_VF) },
  84         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57508) },
  85         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57504) },
  86         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57502) },
  87         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57500_VF1) },
  88         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57500_VF2) },
  89         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57508_MF1) },
  90         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57504_MF1) },
  91         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57502_MF1) },
  92         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57508_MF2) },
  93         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57504_MF2) },
  94         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57502_MF2) },
  95         { .vendor_id = 0, /* sentinel */ },
  96 };
  97
  98 #define BNXT_DEVARG_TRUFLOW     "host-based-truflow"
  99 #define BNXT_DEVARG_FLOW_XSTAT  "flow-xstat"
 100 #define BNXT_DEVARG_MAX_NUM_KFLOWS  "max-num-kflows"
 101 #define BNXT_DEVARG_REPRESENTOR "representor"
 102
 103 static const char *const bnxt_dev_args[] = {
 104         BNXT_DEVARG_REPRESENTOR,
 105         BNXT_DEVARG_TRUFLOW,
 106         BNXT_DEVARG_FLOW_XSTAT,
 107         BNXT_DEVARG_MAX_NUM_KFLOWS,
 108         NULL
 109 };
 110
 111 /*
 112  * truflow == false to disable the feature
 113  * truflow == true to enable the feature
 114  */
 115 #define BNXT_DEVARG_TRUFLOW_INVALID(truflow)    ((truflow) > 1)
 116
 117 /*
 118  * flow_xstat == false to disable the feature
 119  * flow_xstat == true to enable the feature
 120  */
 121 #define BNXT_DEVARG_FLOW_XSTAT_INVALID(flow_xstat)      ((flow_xstat) > 1)
 122
 123 /*
 124  * max_num_kflows must be >= 32
 125  * and must be a power-of-2 supported value
 126  * return: 1 -> invalid
 127  *         0 -> valid
 128  */
 129 static int bnxt_devarg_max_num_kflow_invalid(uint16_t max_num_kflows)
 130 {
 131         if (max_num_kflows < 32 || !rte_is_power_of_2(max_num_kflows))
 132                 return 1;
 133         return 0;
 134 }
 135
 136 static int bnxt_vlan_offload_set_op(struct rte_eth_dev *dev, int mask);
 137 static int bnxt_dev_uninit(struct rte_eth_dev *eth_dev);
 138 static int bnxt_init_resources(struct bnxt *bp, bool reconfig_dev);
 139 static int bnxt_uninit_resources(struct bnxt *bp, bool reconfig_dev);
 140 static void bnxt_cancel_fw_health_check(struct bnxt *bp);
 141 static int bnxt_restore_vlan_filters(struct bnxt *bp);
 142 static void bnxt_dev_recover(void *arg);
 143 static void bnxt_free_error_recovery_info(struct bnxt *bp);
 144 static void bnxt_free_rep_info(struct bnxt *bp);
 145
 146 int is_bnxt_in_error(struct bnxt *bp)
 147 {
 148         if (bp->flags & BNXT_FLAG_FATAL_ERROR)
 149                 return -EIO;
 150         if (bp->flags & BNXT_FLAG_FW_RESET)
 151                 return -EBUSY;
 152
 153         return 0;
 154 }
 155
 156 /***********************/
 157
 158 /*
 159  * High level utility functions
 160  */
 161
 162 static uint16_t bnxt_rss_ctxts(const struct bnxt *bp)
 163 {
 164         if (!BNXT_CHIP_THOR(bp))
 165                 return 1;
 166
 167         return RTE_ALIGN_MUL_CEIL(bp->rx_nr_rings,
 168                                   BNXT_RSS_ENTRIES_PER_CTX_THOR) /
 169                                     BNXT_RSS_ENTRIES_PER_CTX_THOR;
 170 }
 171
 172 uint16_t bnxt_rss_hash_tbl_size(const struct bnxt *bp)
 173 {
 174         if (!BNXT_CHIP_THOR(bp))
 175                 return HW_HASH_INDEX_SIZE;
 176
 177         return bnxt_rss_ctxts(bp) * BNXT_RSS_ENTRIES_PER_CTX_THOR;
 178 }
 179
 180 static void bnxt_free_parent_info(struct bnxt *bp)
 181 {
 182         rte_free(bp->parent);
 183 }
 184
 185 static void bnxt_free_pf_info(struct bnxt *bp)
 186 {
 187         rte_free(bp->pf);
 188 }
 189
 190 static void bnxt_free_link_info(struct bnxt *bp)
 191 {
 192         rte_free(bp->link_info);
 193 }
 194
 195 static void bnxt_free_leds_info(struct bnxt *bp)
 196 {
 197         if (BNXT_VF(bp))
 198                 return;
 199
 200         rte_free(bp->leds);
 201         bp->leds = NULL;
 202 }
 203
 204 static void bnxt_free_flow_stats_info(struct bnxt *bp)
 205 {
 206         rte_free(bp->flow_stat);
 207         bp->flow_stat = NULL;
 208 }
 209
 210 static void bnxt_free_cos_queues(struct bnxt *bp)
 211 {
 212         rte_free(bp->rx_cos_queue);
 213         rte_free(bp->tx_cos_queue);
 214 }
 215
 216 static void bnxt_free_mem(struct bnxt *bp, bool reconfig)
 217 {
 218         bnxt_free_filter_mem(bp);
 219         bnxt_free_vnic_attributes(bp);
 220         bnxt_free_vnic_mem(bp);
 221
 222         /* tx/rx rings are configured as part of *_queue_setup callbacks.
 223          * If the number of rings change across fw update,
 224          * we don't have much choice except to warn the user.
 225          */
 226         if (!reconfig) {
 227                 bnxt_free_stats(bp);
 228                 bnxt_free_tx_rings(bp);
 229                 bnxt_free_rx_rings(bp);
 230         }
 231         bnxt_free_async_cp_ring(bp);
 232         bnxt_free_rxtx_nq_ring(bp);
 233
 234         rte_free(bp->grp_info);
 235         bp->grp_info = NULL;
 236 }
 237
 238 static int bnxt_alloc_parent_info(struct bnxt *bp)
 239 {
 240         bp->parent = rte_zmalloc("bnxt_parent_info",
 241                                  sizeof(struct bnxt_parent_info), 0);
 242         if (bp->parent == NULL)
 243                 return -ENOMEM;
 244
 245         return 0;
 246 }
 247
 248 static int bnxt_alloc_pf_info(struct bnxt *bp)
 249 {
 250         bp->pf = rte_zmalloc("bnxt_pf_info", sizeof(struct bnxt_pf_info), 0);
 251         if (bp->pf == NULL)
 252                 return -ENOMEM;
 253
 254         return 0;
 255 }
 256
 257 static int bnxt_alloc_link_info(struct bnxt *bp)
 258 {
 259         bp->link_info =
 260                 rte_zmalloc("bnxt_link_info", sizeof(struct bnxt_link_info), 0);
 261         if (bp->link_info == NULL)
 262                 return -ENOMEM;
 263
 264         return 0;
 265 }
 266
 267 static int bnxt_alloc_leds_info(struct bnxt *bp)
 268 {
 269         if (BNXT_VF(bp))
 270                 return 0;
 271
 272         bp->leds = rte_zmalloc("bnxt_leds",
 273                                BNXT_MAX_LED * sizeof(struct bnxt_led_info),
 274                                0);
 275         if (bp->leds == NULL)
 276                 return -ENOMEM;
 277
 278         return 0;
 279 }
 280
 281 static int bnxt_alloc_cos_queues(struct bnxt *bp)
 282 {
 283         bp->rx_cos_queue =
 284                 rte_zmalloc("bnxt_rx_cosq",
 285                             BNXT_COS_QUEUE_COUNT *
 286                             sizeof(struct bnxt_cos_queue_info),
 287                             0);
 288         if (bp->rx_cos_queue == NULL)
 289                 return -ENOMEM;
 290
 291         bp->tx_cos_queue =
 292                 rte_zmalloc("bnxt_tx_cosq",
 293                             BNXT_COS_QUEUE_COUNT *
 294                             sizeof(struct bnxt_cos_queue_info),
 295                             0);
 296         if (bp->tx_cos_queue == NULL)
 297                 return -ENOMEM;
 298
 299         return 0;
 300 }
 301
 302 static int bnxt_alloc_flow_stats_info(struct bnxt *bp)
 303 {
 304         bp->flow_stat = rte_zmalloc("bnxt_flow_xstat",
 305                                     sizeof(struct bnxt_flow_stat_info), 0);
 306         if (bp->flow_stat == NULL)
 307                 return -ENOMEM;
 308
 309         return 0;
 310 }
 311
 312 static int bnxt_alloc_mem(struct bnxt *bp, bool reconfig)
 313 {
 314         int rc;
 315
 316         rc = bnxt_alloc_ring_grps(bp);
 317         if (rc)
 318                 goto alloc_mem_err;
 319
 320         rc = bnxt_alloc_async_ring_struct(bp);
 321         if (rc)
 322                 goto alloc_mem_err;
 323
 324         rc = bnxt_alloc_vnic_mem(bp);
 325         if (rc)
 326                 goto alloc_mem_err;
 327
 328         rc = bnxt_alloc_vnic_attributes(bp);
 329         if (rc)
 330                 goto alloc_mem_err;
 331
 332         rc = bnxt_alloc_filter_mem(bp);
 333         if (rc)
 334                 goto alloc_mem_err;
 335
 336         rc = bnxt_alloc_async_cp_ring(bp);
 337         if (rc)
 338                 goto alloc_mem_err;
 339
 340         rc = bnxt_alloc_rxtx_nq_ring(bp);
 341         if (rc)
 342                 goto alloc_mem_err;
 343
 344         if (BNXT_FLOW_XSTATS_EN(bp)) {
 345                 rc = bnxt_alloc_flow_stats_info(bp);
 346                 if (rc)
 347                         goto alloc_mem_err;
 348         }
 349
 350         return 0;
 351
 352 alloc_mem_err:
 353         bnxt_free_mem(bp, reconfig);
 354         return rc;
 355 }
 356
 357 static int bnxt_setup_one_vnic(struct bnxt *bp, uint16_t vnic_id)
 358 {
 359         struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
 360         struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id];
 361         uint64_t rx_offloads = dev_conf->rxmode.offloads;
 362         struct bnxt_rx_queue *rxq;
 363         unsigned int j;
 364         int rc;
 365
 366         rc = bnxt_vnic_grp_alloc(bp, vnic);
 367         if (rc)
 368                 goto err_out;
 369
 370         PMD_DRV_LOG(DEBUG, "vnic[%d] = %p vnic->fw_grp_ids = %p\n",
 371                     vnic_id, vnic, vnic->fw_grp_ids);
 372
 373         rc = bnxt_hwrm_vnic_alloc(bp, vnic);
 374         if (rc)
 375                 goto err_out;
 376
 377         /* Alloc RSS context only if RSS mode is enabled */
 378         if (dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS) {
 379                 int j, nr_ctxs = bnxt_rss_ctxts(bp);
 380
 381                 rc = 0;
 382                 for (j = 0; j < nr_ctxs; j++) {
 383                         rc = bnxt_hwrm_vnic_ctx_alloc(bp, vnic, j);
 384                         if (rc)
 385                                 break;
 386                 }
 387                 if (rc) {
 388                         PMD_DRV_LOG(ERR,
 389                                     "HWRM vnic %d ctx %d alloc failure rc: %x\n",
 390                                     vnic_id, j, rc);
 391                         goto err_out;
 392                 }
 393                 vnic->num_lb_ctxts = nr_ctxs;
 394         }
 395
 396         /*
 397          * Firmware sets pf pair in default vnic cfg. If the VLAN strip
 398          * setting is not available at this time, it will not be
 399          * configured correctly in the CFA.
 400          */
 401         if (rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
 402                 vnic->vlan_strip = true;
 403         else
 404                 vnic->vlan_strip = false;
 405
 406         rc = bnxt_hwrm_vnic_cfg(bp, vnic);
 407         if (rc)
 408                 goto err_out;
 409
 410         rc = bnxt_set_hwrm_vnic_filters(bp, vnic);
 411         if (rc)
 412                 goto err_out;
 413
 414         for (j = 0; j < bp->rx_num_qs_per_vnic; j++) {
 415                 rxq = bp->eth_dev->data->rx_queues[j];
 416
 417                 PMD_DRV_LOG(DEBUG,
 418                             "rxq[%d]->vnic=%p vnic->fw_grp_ids=%p\n",
 419                             j, rxq->vnic, rxq->vnic->fw_grp_ids);
 420
 421                 if (BNXT_HAS_RING_GRPS(bp) && rxq->rx_deferred_start)
 422                         rxq->vnic->fw_grp_ids[j] = INVALID_HW_RING_ID;
 423                 else
 424                         vnic->rx_queue_cnt++;
 425         }
 426
 427         PMD_DRV_LOG(DEBUG, "vnic->rx_queue_cnt = %d\n", vnic->rx_queue_cnt);
 428
 429         rc = bnxt_vnic_rss_configure(bp, vnic);
 430         if (rc)
 431                 goto err_out;
 432
 433         bnxt_hwrm_vnic_plcmode_cfg(bp, vnic);
 434
 435         if (rx_offloads & DEV_RX_OFFLOAD_TCP_LRO)
 436                 bnxt_hwrm_vnic_tpa_cfg(bp, vnic, 1);
 437         else
 438                 bnxt_hwrm_vnic_tpa_cfg(bp, vnic, 0);
 439
 440         return 0;
 441 err_out:
 442         PMD_DRV_LOG(ERR, "HWRM vnic %d cfg failure rc: %x\n",
 443                     vnic_id, rc);
 444         return rc;
 445 }
 446
 447 static int bnxt_register_fc_ctx_mem(struct bnxt *bp)
 448 {
 449         int rc = 0;
 450
 451         rc = bnxt_hwrm_ctx_rgtr(bp, bp->flow_stat->rx_fc_in_tbl.dma,
 452                                 &bp->flow_stat->rx_fc_in_tbl.ctx_id);
 453         if (rc)
 454                 return rc;
 455
 456         PMD_DRV_LOG(DEBUG,
 457                     "rx_fc_in_tbl.va = %p rx_fc_in_tbl.dma = %p"
 458                     " rx_fc_in_tbl.ctx_id = %d\n",
 459                     bp->flow_stat->rx_fc_in_tbl.va,
 460                     (void *)((uintptr_t)bp->flow_stat->rx_fc_in_tbl.dma),
 461                     bp->flow_stat->rx_fc_in_tbl.ctx_id);
 462
 463         rc = bnxt_hwrm_ctx_rgtr(bp, bp->flow_stat->rx_fc_out_tbl.dma,
 464                                 &bp->flow_stat->rx_fc_out_tbl.ctx_id);
 465         if (rc)
 466                 return rc;
 467
 468         PMD_DRV_LOG(DEBUG,
 469                     "rx_fc_out_tbl.va = %p rx_fc_out_tbl.dma = %p"
 470                     " rx_fc_out_tbl.ctx_id = %d\n",
 471                     bp->flow_stat->rx_fc_out_tbl.va,
 472                     (void *)((uintptr_t)bp->flow_stat->rx_fc_out_tbl.dma),
 473                     bp->flow_stat->rx_fc_out_tbl.ctx_id);
 474
 475         rc = bnxt_hwrm_ctx_rgtr(bp, bp->flow_stat->tx_fc_in_tbl.dma,
 476                                 &bp->flow_stat->tx_fc_in_tbl.ctx_id);
 477         if (rc)
 478                 return rc;
 479
 480         PMD_DRV_LOG(DEBUG,
 481                     "tx_fc_in_tbl.va = %p tx_fc_in_tbl.dma = %p"
 482                     " tx_fc_in_tbl.ctx_id = %d\n",
 483                     bp->flow_stat->tx_fc_in_tbl.va,
 484                     (void *)((uintptr_t)bp->flow_stat->tx_fc_in_tbl.dma),
 485                     bp->flow_stat->tx_fc_in_tbl.ctx_id);
 486
 487         rc = bnxt_hwrm_ctx_rgtr(bp, bp->flow_stat->tx_fc_out_tbl.dma,
 488                                 &bp->flow_stat->tx_fc_out_tbl.ctx_id);
 489         if (rc)
 490                 return rc;
 491
 492         PMD_DRV_LOG(DEBUG,
 493                     "tx_fc_out_tbl.va = %p tx_fc_out_tbl.dma = %p"
 494                     " tx_fc_out_tbl.ctx_id = %d\n",
 495                     bp->flow_stat->tx_fc_out_tbl.va,
 496                     (void *)((uintptr_t)bp->flow_stat->tx_fc_out_tbl.dma),
 497                     bp->flow_stat->tx_fc_out_tbl.ctx_id);
 498
 499         memset(bp->flow_stat->rx_fc_out_tbl.va,
 500                0,
 501                bp->flow_stat->rx_fc_out_tbl.size);
 502         rc = bnxt_hwrm_cfa_counter_cfg(bp, BNXT_DIR_RX,
 503                                        CFA_COUNTER_CFG_IN_COUNTER_TYPE_FC,
 504                                        bp->flow_stat->rx_fc_out_tbl.ctx_id,
 505                                        bp->flow_stat->max_fc,
 506                                        true);
 507         if (rc)
 508                 return rc;
 509
 510         memset(bp->flow_stat->tx_fc_out_tbl.va,
 511                0,
 512                bp->flow_stat->tx_fc_out_tbl.size);
 513         rc = bnxt_hwrm_cfa_counter_cfg(bp, BNXT_DIR_TX,
 514                                        CFA_COUNTER_CFG_IN_COUNTER_TYPE_FC,
 515                                        bp->flow_stat->tx_fc_out_tbl.ctx_id,
 516                                        bp->flow_stat->max_fc,
 517                                        true);
 518
 519         return rc;
 520 }
 521
 522 static int bnxt_alloc_ctx_mem_buf(char *type, size_t size,
 523                                   struct bnxt_ctx_mem_buf_info *ctx)
 524 {
 525         if (!ctx)
 526                 return -EINVAL;
 527
 528         ctx->va = rte_zmalloc(type, size, 0);
 529         if (ctx->va == NULL)
 530                 return -ENOMEM;
 531         rte_mem_lock_page(ctx->va);
 532         ctx->size = size;
 533         ctx->dma = rte_mem_virt2iova(ctx->va);
 534         if (ctx->dma == RTE_BAD_IOVA)
 535                 return -ENOMEM;
 536
 537         return 0;
 538 }
 539
 540 static int bnxt_init_fc_ctx_mem(struct bnxt *bp)
 541 {
 542         struct rte_pci_device *pdev = bp->pdev;
 543         char type[RTE_MEMZONE_NAMESIZE];
 544         uint16_t max_fc;
 545         int rc = 0;
 546
 547         max_fc = bp->flow_stat->max_fc;
 548
 549         sprintf(type, "bnxt_rx_fc_in_" PCI_PRI_FMT, pdev->addr.domain,
 550                 pdev->addr.bus, pdev->addr.devid, pdev->addr.function);
 551         /* 4 bytes for each counter-id */
 552         rc = bnxt_alloc_ctx_mem_buf(type,
 553                                     max_fc * 4,
 554                                     &bp->flow_stat->rx_fc_in_tbl);
 555         if (rc)
 556                 return rc;
 557
 558         sprintf(type, "bnxt_rx_fc_out_" PCI_PRI_FMT, pdev->addr.domain,
 559                 pdev->addr.bus, pdev->addr.devid, pdev->addr.function);
 560         /* 16 bytes for each counter - 8 bytes pkt_count, 8 bytes byte_count */
 561         rc = bnxt_alloc_ctx_mem_buf(type,
 562                                     max_fc * 16,
 563                                     &bp->flow_stat->rx_fc_out_tbl);
 564         if (rc)
 565                 return rc;
 566
 567         sprintf(type, "bnxt_tx_fc_in_" PCI_PRI_FMT, pdev->addr.domain,
 568                 pdev->addr.bus, pdev->addr.devid, pdev->addr.function);
 569         /* 4 bytes for each counter-id */
 570         rc = bnxt_alloc_ctx_mem_buf(type,
 571                                     max_fc * 4,
 572                                     &bp->flow_stat->tx_fc_in_tbl);
 573         if (rc)
 574                 return rc;
 575
 576         sprintf(type, "bnxt_tx_fc_out_" PCI_PRI_FMT, pdev->addr.domain,
 577                 pdev->addr.bus, pdev->addr.devid, pdev->addr.function);
 578         /* 16 bytes for each counter - 8 bytes pkt_count, 8 bytes byte_count */
 579         rc = bnxt_alloc_ctx_mem_buf(type,
 580                                     max_fc * 16,
 581                                     &bp->flow_stat->tx_fc_out_tbl);
 582         if (rc)
 583                 return rc;
 584
 585         rc = bnxt_register_fc_ctx_mem(bp);
 586
 587         return rc;
 588 }
 589
 590 static int bnxt_init_ctx_mem(struct bnxt *bp)
 591 {
 592         int rc = 0;
 593
 594         if (!(bp->fw_cap & BNXT_FW_CAP_ADV_FLOW_COUNTERS) ||
 595             !(BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp)) ||
 596             !BNXT_FLOW_XSTATS_EN(bp))
 597                 return 0;
 598
 599         rc = bnxt_hwrm_cfa_counter_qcaps(bp, &bp->flow_stat->max_fc);
 600         if (rc)
 601                 return rc;
 602
 603         rc = bnxt_init_fc_ctx_mem(bp);
 604
 605         return rc;
 606 }
 607
 608 static int bnxt_update_phy_setting(struct bnxt *bp)
 609 {
 610         struct rte_eth_link new;
 611         int rc;
 612
 613         rc = bnxt_get_hwrm_link_config(bp, &new);
 614         if (rc) {
 615                 PMD_DRV_LOG(ERR, "Failed to get link settings\n");
 616                 return rc;
 617         }
 618
 619         /*
 620          * On BCM957508-N2100 adapters, FW will not allow any user other
 621          * than BMC to shutdown the port. bnxt_get_hwrm_link_config() call
 622          * always returns link up. Force phy update always in that case.
 623          */
 624         if (!new.link_status || IS_BNXT_DEV_957508_N2100(bp)) {
 625                 rc = bnxt_set_hwrm_link_config(bp, true);
 626                 if (rc) {
 627                         PMD_DRV_LOG(ERR, "Failed to update PHY settings\n");
 628                         return rc;
 629                 }
 630         }
 631
 632         return rc;
 633 }
 634
 635 static int bnxt_init_chip(struct bnxt *bp)
 636 {
 637         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(bp->eth_dev);
 638         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
 639         uint32_t intr_vector = 0;
 640         uint32_t queue_id, base = BNXT_MISC_VEC_ID;
 641         uint32_t vec = BNXT_MISC_VEC_ID;
 642         unsigned int i, j;
 643         int rc;
 644
 645         if (bp->eth_dev->data->mtu > RTE_ETHER_MTU) {
 646                 bp->eth_dev->data->dev_conf.rxmode.offloads |=
 647                         DEV_RX_OFFLOAD_JUMBO_FRAME;
 648                 bp->flags |= BNXT_FLAG_JUMBO;
 649         } else {
 650                 bp->eth_dev->data->dev_conf.rxmode.offloads &=
 651                         ~DEV_RX_OFFLOAD_JUMBO_FRAME;
 652                 bp->flags &= ~BNXT_FLAG_JUMBO;
 653         }
 654
 655         /* THOR does not support ring groups.
 656          * But we will use the array to save RSS context IDs.
 657          */
 658         if (BNXT_CHIP_THOR(bp))
 659                 bp->max_ring_grps = BNXT_MAX_RSS_CTXTS_THOR;
 660
 661         rc = bnxt_alloc_all_hwrm_stat_ctxs(bp);
 662         if (rc) {
 663                 PMD_DRV_LOG(ERR, "HWRM stat ctx alloc failure rc: %x\n", rc);
 664                 goto err_out;
 665         }
 666
 667         rc = bnxt_alloc_hwrm_rings(bp);
 668         if (rc) {
 669                 PMD_DRV_LOG(ERR, "HWRM ring alloc failure rc: %x\n", rc);
 670                 goto err_out;
 671         }
 672
 673         rc = bnxt_alloc_all_hwrm_ring_grps(bp);
 674         if (rc) {
 675                 PMD_DRV_LOG(ERR, "HWRM ring grp alloc failure: %x\n", rc);
 676                 goto err_out;
 677         }
 678
 679         if (!(bp->vnic_cap_flags & BNXT_VNIC_CAP_COS_CLASSIFY))
 680                 goto skip_cosq_cfg;
 681
 682         for (j = 0, i = 0; i < BNXT_COS_QUEUE_COUNT; i++) {
 683                 if (bp->rx_cos_queue[i].id != 0xff) {
 684                         struct bnxt_vnic_info *vnic = &bp->vnic_info[j++];
 685
 686                         if (!vnic) {
 687                                 PMD_DRV_LOG(ERR,
 688                                             "Num pools more than FW profile\n");
 689                                 rc = -EINVAL;
 690                                 goto err_out;
 691                         }
 692                         vnic->cos_queue_id = bp->rx_cos_queue[i].id;
 693                         bp->rx_cosq_cnt++;
 694                 }
 695         }
 696
 697 skip_cosq_cfg:
 698         rc = bnxt_mq_rx_configure(bp);
 699         if (rc) {
 700                 PMD_DRV_LOG(ERR, "MQ mode configure failure rc: %x\n", rc);
 701                 goto err_out;
 702         }
 703
 704         /* VNIC configuration */
 705         for (i = 0; i < bp->nr_vnics; i++) {
 706                 rc = bnxt_setup_one_vnic(bp, i);
 707                 if (rc)
 708                         goto err_out;
 709         }
 710
 711         rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, &bp->vnic_info[0], 0, NULL);
 712         if (rc) {
 713                 PMD_DRV_LOG(ERR,
 714                         "HWRM cfa l2 rx mask failure rc: %x\n", rc);
 715                 goto err_out;
 716         }
 717
 718         /* check and configure queue intr-vector mapping */
 719         if ((rte_intr_cap_multiple(intr_handle) ||
 720              !RTE_ETH_DEV_SRIOV(bp->eth_dev).active) &&
 721             bp->eth_dev->data->dev_conf.intr_conf.rxq != 0) {
 722                 intr_vector = bp->eth_dev->data->nb_rx_queues;
 723                 PMD_DRV_LOG(DEBUG, "intr_vector = %d\n", intr_vector);
 724                 if (intr_vector > bp->rx_cp_nr_rings) {
 725                         PMD_DRV_LOG(ERR, "At most %d intr queues supported",
 726                                         bp->rx_cp_nr_rings);
 727                         return -ENOTSUP;
 728                 }
 729                 rc = rte_intr_efd_enable(intr_handle, intr_vector);
 730                 if (rc)
 731                         return rc;
 732         }
 733
 734         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
 735                 intr_handle->intr_vec =
 736                         rte_zmalloc("intr_vec",
 737                                     bp->eth_dev->data->nb_rx_queues *
 738                                     sizeof(int), 0);
 739                 if (intr_handle->intr_vec == NULL) {
 740                         PMD_DRV_LOG(ERR, "Failed to allocate %d rx_queues"
 741                                 " intr_vec", bp->eth_dev->data->nb_rx_queues);
 742                         rc = -ENOMEM;
 743                         goto err_disable;
 744                 }
 745                 PMD_DRV_LOG(DEBUG, "intr_handle->intr_vec = %p "
 746                         "intr_handle->nb_efd = %d intr_handle->max_intr = %d\n",
 747                          intr_handle->intr_vec, intr_handle->nb_efd,
 748                         intr_handle->max_intr);
 749                 for (queue_id = 0; queue_id < bp->eth_dev->data->nb_rx_queues;
 750                      queue_id++) {
 751                         intr_handle->intr_vec[queue_id] =
 752                                                         vec + BNXT_RX_VEC_START;
 753                         if (vec < base + intr_handle->nb_efd - 1)
 754                                 vec++;
 755                 }
 756         }
 757
 758         /* enable uio/vfio intr/eventfd mapping */
 759         rc = rte_intr_enable(intr_handle);
 760 #ifndef RTE_EXEC_ENV_FREEBSD
 761         /* In FreeBSD OS, nic_uio driver does not support interrupts */
 762         if (rc)
 763                 goto err_free;
 764 #endif
 765
 766         rc = bnxt_update_phy_setting(bp);
 767         if (rc)
 768                 goto err_free;
 769
 770         bp->mark_table = rte_zmalloc("bnxt_mark_table", BNXT_MARK_TABLE_SZ, 0);
 771         if (!bp->mark_table)
 772                 PMD_DRV_LOG(ERR, "Allocation of mark table failed\n");
 773
 774         return 0;
 775
 776 err_free:
 777         rte_free(intr_handle->intr_vec);
 778 err_disable:
 779         rte_intr_efd_disable(intr_handle);
 780 err_out:
 781         /* Some of the error status returned by FW may not be from errno.h */
 782         if (rc > 0)
 783                 rc = -EIO;
 784
 785         return rc;
 786 }
 787
 788 static int bnxt_shutdown_nic(struct bnxt *bp)
 789 {
 790         bnxt_free_all_hwrm_resources(bp);
 791         bnxt_free_all_filters(bp);
 792         bnxt_free_all_vnics(bp);
 793         return 0;
 794 }
 795
 796 /*
 797  * Device configuration and status function
 798  */
 799
 800 uint32_t bnxt_get_speed_capabilities(struct bnxt *bp)
 801 {
 802         uint32_t link_speed = bp->link_info->support_speeds;
 803         uint32_t speed_capa = 0;
 804
 805         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_100MB)
 806                 speed_capa |= ETH_LINK_SPEED_100M;
 807         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_100MBHD)
 808                 speed_capa |= ETH_LINK_SPEED_100M_HD;
 809         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_1GB)
 810                 speed_capa |= ETH_LINK_SPEED_1G;
 811         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_2_5GB)
 812                 speed_capa |= ETH_LINK_SPEED_2_5G;
 813         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_10GB)
 814                 speed_capa |= ETH_LINK_SPEED_10G;
 815         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_20GB)
 816                 speed_capa |= ETH_LINK_SPEED_20G;
 817         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_25GB)
 818                 speed_capa |= ETH_LINK_SPEED_25G;
 819         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_40GB)
 820                 speed_capa |= ETH_LINK_SPEED_40G;
 821         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_50GB)
 822                 speed_capa |= ETH_LINK_SPEED_50G;
 823         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_100GB)
 824                 speed_capa |= ETH_LINK_SPEED_100G;
 825         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_200GB)
 826                 speed_capa |= ETH_LINK_SPEED_200G;
 827
 828         if (bp->link_info->auto_mode ==
 829             HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_MODE_NONE)
 830                 speed_capa |= ETH_LINK_SPEED_FIXED;
 831         else
 832                 speed_capa |= ETH_LINK_SPEED_AUTONEG;
 833
 834         return speed_capa;
 835 }
 836
 837 static int bnxt_dev_info_get_op(struct rte_eth_dev *eth_dev,
 838                                 struct rte_eth_dev_info *dev_info)
 839 {
 840         struct rte_pci_device *pdev = RTE_DEV_TO_PCI(eth_dev->device);
 841         struct bnxt *bp = eth_dev->data->dev_private;
 842         uint16_t max_vnics, i, j, vpool, vrxq;
 843         unsigned int max_rx_rings;
 844         int rc;
 845
 846         rc = is_bnxt_in_error(bp);
 847         if (rc)
 848                 return rc;
 849
 850         /* MAC Specifics */
 851         dev_info->max_mac_addrs = bp->max_l2_ctx;
 852         dev_info->max_hash_mac_addrs = 0;
 853
 854         /* PF/VF specifics */
 855         if (BNXT_PF(bp))
 856                 dev_info->max_vfs = pdev->max_vfs;
 857
 858         max_rx_rings = BNXT_MAX_RINGS(bp);
 859         /* For the sake of symmetry, max_rx_queues = max_tx_queues */
 860         dev_info->max_rx_queues = max_rx_rings;
 861         dev_info->max_tx_queues = max_rx_rings;
 862         dev_info->reta_size = bnxt_rss_hash_tbl_size(bp);
 863         dev_info->hash_key_size = 40;
 864         max_vnics = bp->max_vnics;
 865
 866         /* MTU specifics */
 867         dev_info->min_mtu = RTE_ETHER_MIN_MTU;
 868         dev_info->max_mtu = BNXT_MAX_MTU;
 869
 870         /* Fast path specifics */
 871         dev_info->min_rx_bufsize = 1;
 872         dev_info->max_rx_pktlen = BNXT_MAX_PKT_LEN;
 873
 874         dev_info->rx_offload_capa = BNXT_DEV_RX_OFFLOAD_SUPPORT;
 875         if (bp->flags & BNXT_FLAG_PTP_SUPPORTED)
 876                 dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_TIMESTAMP;
 877         dev_info->tx_offload_capa = BNXT_DEV_TX_OFFLOAD_SUPPORT;
 878         dev_info->flow_type_rss_offloads = BNXT_ETH_RSS_SUPPORT;
 879
 880         dev_info->speed_capa = bnxt_get_speed_capabilities(bp);
 881
 882         /* *INDENT-OFF* */
 883         dev_info->default_rxconf = (struct rte_eth_rxconf) {
 884                 .rx_thresh = {
 885                         .pthresh = 8,
 886                         .hthresh = 8,
 887                         .wthresh = 0,
 888                 },
 889                 .rx_free_thresh = 32,
 890                 /* If no descriptors available, pkts are dropped by default */
 891                 .rx_drop_en = 1,
 892         };
 893
 894         dev_info->default_txconf = (struct rte_eth_txconf) {
 895                 .tx_thresh = {
 896                         .pthresh = 32,
 897                         .hthresh = 0,
 898                         .wthresh = 0,
 899                 },
 900                 .tx_free_thresh = 32,
 901                 .tx_rs_thresh = 32,
 902         };
 903         eth_dev->data->dev_conf.intr_conf.lsc = 1;
 904
 905         eth_dev->data->dev_conf.intr_conf.rxq = 1;
 906         dev_info->rx_desc_lim.nb_min = BNXT_MIN_RING_DESC;
 907         dev_info->rx_desc_lim.nb_max = BNXT_MAX_RX_RING_DESC;
 908         dev_info->tx_desc_lim.nb_min = BNXT_MIN_RING_DESC;
 909         dev_info->tx_desc_lim.nb_max = BNXT_MAX_TX_RING_DESC;
 910
 911         /* *INDENT-ON* */
 912
 913         /*
 914          * TODO: default_rxconf, default_txconf, rx_desc_lim, and tx_desc_lim
 915          *       need further investigation.
 916          */
 917
 918         /* VMDq resources */
 919         vpool = 64; /* ETH_64_POOLS */
 920         vrxq = 128; /* ETH_VMDQ_DCB_NUM_QUEUES */
 921         for (i = 0; i < 4; vpool >>= 1, i++) {
 922                 if (max_vnics > vpool) {
 923                         for (j = 0; j < 5; vrxq >>= 1, j++) {
 924                                 if (dev_info->max_rx_queues > vrxq) {
 925                                         if (vpool > vrxq)
 926                                                 vpool = vrxq;
 927                                         goto found;
 928                                 }
 929                         }
 930                         /* Not enough resources to support VMDq */
 931                         break;
 932                 }
 933         }
 934         /* Not enough resources to support VMDq */
 935         vpool = 0;
 936         vrxq = 0;
 937 found:
 938         dev_info->max_vmdq_pools = vpool;
 939         dev_info->vmdq_queue_num = vrxq;
 940
 941         dev_info->vmdq_pool_base = 0;
 942         dev_info->vmdq_queue_base = 0;
 943
 944         return 0;
 945 }
 946
 947 /* Configure the device based on the configuration provided */
 948 static int bnxt_dev_configure_op(struct rte_eth_dev *eth_dev)
 949 {
 950         struct bnxt *bp = eth_dev->data->dev_private;
 951         uint64_t rx_offloads = eth_dev->data->dev_conf.rxmode.offloads;
 952         int rc;
 953
 954         bp->rx_queues = (void *)eth_dev->data->rx_queues;
 955         bp->tx_queues = (void *)eth_dev->data->tx_queues;
 956         bp->tx_nr_rings = eth_dev->data->nb_tx_queues;
 957         bp->rx_nr_rings = eth_dev->data->nb_rx_queues;
 958
 959         rc = is_bnxt_in_error(bp);
 960         if (rc)
 961                 return rc;
 962
 963         if (BNXT_VF(bp) && (bp->flags & BNXT_FLAG_NEW_RM)) {
 964                 rc = bnxt_hwrm_check_vf_rings(bp);
 965                 if (rc) {
 966                         PMD_DRV_LOG(ERR, "HWRM insufficient resources\n");
 967                         return -ENOSPC;
 968                 }
 969
 970                 /* If a resource has already been allocated - in this case
 971                  * it is the async completion ring, free it. Reallocate it after
 972                  * resource reservation. This will ensure the resource counts
 973                  * are calculated correctly.
 974                  */
 975
 976                 pthread_mutex_lock(&bp->def_cp_lock);
 977
 978                 if (!BNXT_HAS_NQ(bp) && bp->async_cp_ring) {
 979                         bnxt_disable_int(bp);
 980                         bnxt_free_cp_ring(bp, bp->async_cp_ring);
 981                 }
 982
 983                 rc = bnxt_hwrm_func_reserve_vf_resc(bp, false);
 984                 if (rc) {
 985                         PMD_DRV_LOG(ERR, "HWRM resource alloc fail:%x\n", rc);
 986                         pthread_mutex_unlock(&bp->def_cp_lock);
 987                         return -ENOSPC;
 988                 }
 989
 990                 if (!BNXT_HAS_NQ(bp) && bp->async_cp_ring) {
 991                         rc = bnxt_alloc_async_cp_ring(bp);
 992                         if (rc) {
 993                                 pthread_mutex_unlock(&bp->def_cp_lock);
 994                                 return rc;
 995                         }
 996                         bnxt_enable_int(bp);
 997                 }
 998
 999                 pthread_mutex_unlock(&bp->def_cp_lock);
1000         } else {
1001                 /* legacy driver needs to get updated values */
1002                 rc = bnxt_hwrm_func_qcaps(bp);
1003                 if (rc) {
1004                         PMD_DRV_LOG(ERR, "hwrm func qcaps fail:%d\n", rc);
1005                         return rc;
1006                 }
1007         }
1008
1009         /* Inherit new configurations */
1010         if (eth_dev->data->nb_rx_queues > bp->max_rx_rings ||
1011             eth_dev->data->nb_tx_queues > bp->max_tx_rings ||
1012             eth_dev->data->nb_rx_queues + eth_dev->data->nb_tx_queues
1013                 + BNXT_NUM_ASYNC_CPR(bp) > bp->max_cp_rings ||
1014             eth_dev->data->nb_rx_queues + eth_dev->data->nb_tx_queues >
1015             bp->max_stat_ctx)
1016                 goto resource_error;
1017
1018         if (BNXT_HAS_RING_GRPS(bp) &&
1019             (uint32_t)(eth_dev->data->nb_rx_queues) > bp->max_ring_grps)
1020                 goto resource_error;
1021
1022         if (!(eth_dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_RSS) &&
1023             bp->max_vnics < eth_dev->data->nb_rx_queues)
1024                 goto resource_error;
1025
1026         bp->rx_cp_nr_rings = bp->rx_nr_rings;
1027         bp->tx_cp_nr_rings = bp->tx_nr_rings;
1028
1029         if (eth_dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG)
1030                 rx_offloads |= DEV_RX_OFFLOAD_RSS_HASH;
1031         eth_dev->data->dev_conf.rxmode.offloads = rx_offloads;
1032
1033         if (rx_offloads & DEV_RX_OFFLOAD_JUMBO_FRAME) {
1034                 eth_dev->data->mtu =
1035                         eth_dev->data->dev_conf.rxmode.max_rx_pkt_len -
1036                         RTE_ETHER_HDR_LEN - RTE_ETHER_CRC_LEN - VLAN_TAG_SIZE *
1037                         BNXT_NUM_VLANS;
1038                 bnxt_mtu_set_op(eth_dev, eth_dev->data->mtu);
1039         }
1040         return 0;
1041
1042 resource_error:
1043         PMD_DRV_LOG(ERR,
1044                     "Insufficient resources to support requested config\n");
1045         PMD_DRV_LOG(ERR,
1046                     "Num Queues Requested: Tx %d, Rx %d\n",
1047                     eth_dev->data->nb_tx_queues,
1048                     eth_dev->data->nb_rx_queues);
1049         PMD_DRV_LOG(ERR,
1050                     "MAX: TxQ %d, RxQ %d, CQ %d Stat %d, Grp %d, Vnic %d\n",
1051                     bp->max_tx_rings, bp->max_rx_rings, bp->max_cp_rings,
1052                     bp->max_stat_ctx, bp->max_ring_grps, bp->max_vnics);
1053         return -ENOSPC;
1054 }
1055
1056 void bnxt_print_link_info(struct rte_eth_dev *eth_dev)
1057 {
1058         struct rte_eth_link *link = &eth_dev->data->dev_link;
1059
1060         if (link->link_status)
1061                 PMD_DRV_LOG(INFO, "Port %d Link Up - speed %u Mbps - %s\n",
1062                         eth_dev->data->port_id,
1063                         (uint32_t)link->link_speed,
1064                         (link->link_duplex == ETH_LINK_FULL_DUPLEX) ?
1065                         ("full-duplex") : ("half-duplex\n"));
1066         else
1067                 PMD_DRV_LOG(INFO, "Port %d Link Down\n",
1068                         eth_dev->data->port_id);
1069 }
1070
1071 /*
1072  * Determine whether the current configuration requires support for scattered
1073  * receive; return 1 if scattered receive is required and 0 if not.
1074  */
1075 static int bnxt_scattered_rx(struct rte_eth_dev *eth_dev)
1076 {
1077         uint16_t buf_size;
1078         int i;
1079
1080         if (eth_dev->data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_SCATTER)
1081                 return 1;
1082
1083         for (i = 0; i < eth_dev->data->nb_rx_queues; i++) {
1084                 struct bnxt_rx_queue *rxq = eth_dev->data->rx_queues[i];
1085
1086                 buf_size = (uint16_t)(rte_pktmbuf_data_room_size(rxq->mb_pool) -
1087                                       RTE_PKTMBUF_HEADROOM);
1088                 if (eth_dev->data->dev_conf.rxmode.max_rx_pkt_len > buf_size)
1089                         return 1;
1090         }
1091         return 0;
1092 }
1093
1094 static eth_rx_burst_t
1095 bnxt_receive_function(struct rte_eth_dev *eth_dev)
1096 {
1097         struct bnxt *bp = eth_dev->data->dev_private;
1098
1099 #if defined(RTE_ARCH_X86) || defined(RTE_ARCH_ARM64)
1100 #ifndef RTE_LIBRTE_IEEE1588
1101         /*
1102          * Vector mode receive can be enabled only if scatter rx is not
1103          * in use and rx offloads are limited to VLAN stripping and
1104          * CRC stripping.
1105          */
1106         if (!eth_dev->data->scattered_rx &&
1107             !(eth_dev->data->dev_conf.rxmode.offloads &
1108               ~(DEV_RX_OFFLOAD_VLAN_STRIP |
1109                 DEV_RX_OFFLOAD_KEEP_CRC |
1110                 DEV_RX_OFFLOAD_JUMBO_FRAME |
1111                 DEV_RX_OFFLOAD_IPV4_CKSUM |
1112                 DEV_RX_OFFLOAD_UDP_CKSUM |
1113                 DEV_RX_OFFLOAD_TCP_CKSUM |
1114                 DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM |
1115                 DEV_RX_OFFLOAD_RSS_HASH |
1116                 DEV_RX_OFFLOAD_VLAN_FILTER)) &&
1117             !BNXT_TRUFLOW_EN(bp)) {
1118                 PMD_DRV_LOG(INFO, "Using vector mode receive for port %d\n",
1119                             eth_dev->data->port_id);
1120                 bp->flags |= BNXT_FLAG_RX_VECTOR_PKT_MODE;
1121                 return bnxt_recv_pkts_vec;
1122         }
1123         PMD_DRV_LOG(INFO, "Vector mode receive disabled for port %d\n",
1124                     eth_dev->data->port_id);
1125         PMD_DRV_LOG(INFO,
1126                     "Port %d scatter: %d rx offload: %" PRIX64 "\n",
1127                     eth_dev->data->port_id,
1128                     eth_dev->data->scattered_rx,
1129                     eth_dev->data->dev_conf.rxmode.offloads);
1130 #endif
1131 #endif
1132         bp->flags &= ~BNXT_FLAG_RX_VECTOR_PKT_MODE;
1133         return bnxt_recv_pkts;
1134 }
1135
1136 static eth_tx_burst_t
1137 bnxt_transmit_function(__rte_unused struct rte_eth_dev *eth_dev)
1138 {
1139 #if defined(RTE_ARCH_X86) || defined(RTE_ARCH_ARM64)
1140 #ifndef RTE_LIBRTE_IEEE1588
1141         struct bnxt *bp = eth_dev->data->dev_private;
1142
1143         /*
1144          * Vector mode transmit can be enabled only if not using scatter rx
1145          * or tx offloads.
1146          */
1147         if (!eth_dev->data->scattered_rx &&
1148             !eth_dev->data->dev_conf.txmode.offloads &&
1149             !BNXT_TRUFLOW_EN(bp)) {
1150                 PMD_DRV_LOG(INFO, "Using vector mode transmit for port %d\n",
1151                             eth_dev->data->port_id);
1152                 return bnxt_xmit_pkts_vec;
1153         }
1154         PMD_DRV_LOG(INFO, "Vector mode transmit disabled for port %d\n",
1155                     eth_dev->data->port_id);
1156         PMD_DRV_LOG(INFO,
1157                     "Port %d scatter: %d tx offload: %" PRIX64 "\n",
1158                     eth_dev->data->port_id,
1159                     eth_dev->data->scattered_rx,
1160                     eth_dev->data->dev_conf.txmode.offloads);
1161 #endif
1162 #endif
1163         return bnxt_xmit_pkts;
1164 }
1165
1166 static int bnxt_handle_if_change_status(struct bnxt *bp)
1167 {
1168         int rc;
1169
1170         /* Since fw has undergone a reset and lost all contexts,
1171          * set fatal flag to not issue hwrm during cleanup
1172          */
1173         bp->flags |= BNXT_FLAG_FATAL_ERROR;
1174         bnxt_uninit_resources(bp, true);
1175
1176         /* clear fatal flag so that re-init happens */
1177         bp->flags &= ~BNXT_FLAG_FATAL_ERROR;
1178         rc = bnxt_init_resources(bp, true);
1179
1180         bp->flags &= ~BNXT_FLAG_IF_CHANGE_HOT_FW_RESET_DONE;
1181
1182         return rc;
1183 }
1184
1185 static int bnxt_dev_start_op(struct rte_eth_dev *eth_dev)
1186 {
1187         struct bnxt *bp = eth_dev->data->dev_private;
1188         uint64_t rx_offloads = eth_dev->data->dev_conf.rxmode.offloads;
1189         int vlan_mask = 0;
1190         int rc, retry_cnt = BNXT_IF_CHANGE_RETRY_COUNT;
1191
1192         if (!eth_dev->data->nb_tx_queues || !eth_dev->data->nb_rx_queues) {
1193                 PMD_DRV_LOG(ERR, "Queues are not configured yet!\n");
1194                 return -EINVAL;
1195         }
1196
1197         if (bp->rx_cp_nr_rings > RTE_ETHDEV_QUEUE_STAT_CNTRS) {
1198                 PMD_DRV_LOG(ERR,
1199                         "RxQ cnt %d > CONFIG_RTE_ETHDEV_QUEUE_STAT_CNTRS %d\n",
1200                         bp->rx_cp_nr_rings, RTE_ETHDEV_QUEUE_STAT_CNTRS);
1201         }
1202
1203         do {
1204                 rc = bnxt_hwrm_if_change(bp, true);
1205                 if (rc == 0 || rc != -EAGAIN)
1206                         break;
1207
1208                 rte_delay_ms(BNXT_IF_CHANGE_RETRY_INTERVAL);
1209         } while (retry_cnt--);
1210
1211         if (rc)
1212                 return rc;
1213
1214         if (bp->flags & BNXT_FLAG_IF_CHANGE_HOT_FW_RESET_DONE) {
1215                 rc = bnxt_handle_if_change_status(bp);
1216                 if (rc)
1217                         return rc;
1218         }
1219
1220         bnxt_enable_int(bp);
1221
1222         rc = bnxt_init_chip(bp);
1223         if (rc)
1224                 goto error;
1225
1226         eth_dev->data->scattered_rx = bnxt_scattered_rx(eth_dev);
1227         eth_dev->data->dev_started = 1;
1228
1229         bnxt_link_update(eth_dev, 1, ETH_LINK_UP);
1230
1231         if (rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER)
1232                 vlan_mask |= ETH_VLAN_FILTER_MASK;
1233         if (rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
1234                 vlan_mask |= ETH_VLAN_STRIP_MASK;
1235         rc = bnxt_vlan_offload_set_op(eth_dev, vlan_mask);
1236         if (rc)
1237                 goto error;
1238
1239         eth_dev->rx_pkt_burst = bnxt_receive_function(eth_dev);
1240         eth_dev->tx_pkt_burst = bnxt_transmit_function(eth_dev);
1241
1242         pthread_mutex_lock(&bp->def_cp_lock);
1243         bnxt_schedule_fw_health_check(bp);
1244         pthread_mutex_unlock(&bp->def_cp_lock);
1245
1246         bnxt_ulp_init(bp);
1247
1248         return 0;
1249
1250 error:
1251         bnxt_shutdown_nic(bp);
1252         bnxt_free_tx_mbufs(bp);
1253         bnxt_free_rx_mbufs(bp);
1254         bnxt_hwrm_if_change(bp, false);
1255         eth_dev->data->dev_started = 0;
1256         return rc;
1257 }
1258
1259 static int bnxt_dev_set_link_up_op(struct rte_eth_dev *eth_dev)
1260 {
1261         struct bnxt *bp = eth_dev->data->dev_private;
1262         int rc = 0;
1263
1264         if (!bp->link_info->link_up)
1265                 rc = bnxt_set_hwrm_link_config(bp, true);
1266         if (!rc)
1267                 eth_dev->data->dev_link.link_status = 1;
1268
1269         bnxt_print_link_info(eth_dev);
1270         return rc;
1271 }
1272
1273 static int bnxt_dev_set_link_down_op(struct rte_eth_dev *eth_dev)
1274 {
1275         struct bnxt *bp = eth_dev->data->dev_private;
1276
1277         eth_dev->data->dev_link.link_status = 0;
1278         bnxt_set_hwrm_link_config(bp, false);
1279         bp->link_info->link_up = 0;
1280
1281         return 0;
1282 }
1283
1284 static void bnxt_free_switch_domain(struct bnxt *bp)
1285 {
1286         if (bp->switch_domain_id)
1287                 rte_eth_switch_domain_free(bp->switch_domain_id);
1288 }
1289
1290 /* Unload the driver, release resources */
1291 static void bnxt_dev_stop_op(struct rte_eth_dev *eth_dev)
1292 {
1293         struct bnxt *bp = eth_dev->data->dev_private;
1294         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1295         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1296
1297         eth_dev->data->dev_started = 0;
1298         /* Prevent crashes when queues are still in use */
1299         eth_dev->rx_pkt_burst = &bnxt_dummy_recv_pkts;
1300         eth_dev->tx_pkt_burst = &bnxt_dummy_xmit_pkts;
1301
1302         bnxt_disable_int(bp);
1303
1304         /* disable uio/vfio intr/eventfd mapping */
1305         rte_intr_disable(intr_handle);
1306
1307         bnxt_ulp_destroy_df_rules(bp, false);
1308         bnxt_ulp_deinit(bp);
1309
1310         bnxt_cancel_fw_health_check(bp);
1311
1312         bnxt_dev_set_link_down_op(eth_dev);
1313
1314         /* Wait for link to be reset and the async notification to process.
1315          * During reset recovery, there is no need to wait and
1316          * VF/NPAR functions do not have privilege to change PHY config.
1317          */
1318         if (!is_bnxt_in_error(bp) && BNXT_SINGLE_PF(bp))
1319                 bnxt_link_update(eth_dev, 1, ETH_LINK_DOWN);
1320
1321         /* Clean queue intr-vector mapping */
1322         rte_intr_efd_disable(intr_handle);
1323         if (intr_handle->intr_vec != NULL) {
1324                 rte_free(intr_handle->intr_vec);
1325                 intr_handle->intr_vec = NULL;
1326         }
1327
1328         bnxt_hwrm_port_clr_stats(bp);
1329         bnxt_free_tx_mbufs(bp);
1330         bnxt_free_rx_mbufs(bp);
1331         /* Process any remaining notifications in default completion queue */
1332         bnxt_int_handler(eth_dev);
1333         bnxt_shutdown_nic(bp);
1334         bnxt_hwrm_if_change(bp, false);
1335
1336         rte_free(bp->mark_table);
1337         bp->mark_table = NULL;
1338
1339         bp->flags &= ~BNXT_FLAG_RX_VECTOR_PKT_MODE;
1340         bp->rx_cosq_cnt = 0;
1341         /* All filters are deleted on a port stop. */
1342         if (BNXT_FLOW_XSTATS_EN(bp))
1343                 bp->flow_stat->flow_count = 0;
1344 }
1345
1346 static void bnxt_dev_close_op(struct rte_eth_dev *eth_dev)
1347 {
1348         struct bnxt *bp = eth_dev->data->dev_private;
1349
1350         /* cancel the recovery handler before remove dev */
1351         rte_eal_alarm_cancel(bnxt_dev_reset_and_resume, (void *)bp);
1352         rte_eal_alarm_cancel(bnxt_dev_recover, (void *)bp);
1353         bnxt_cancel_fc_thread(bp);
1354
1355         if (eth_dev->data->dev_started)
1356                 bnxt_dev_stop_op(eth_dev);
1357
1358         bnxt_free_switch_domain(bp);
1359
1360         bnxt_uninit_resources(bp, false);
1361
1362         bnxt_free_leds_info(bp);
1363         bnxt_free_cos_queues(bp);
1364         bnxt_free_link_info(bp);
1365         bnxt_free_pf_info(bp);
1366         bnxt_free_parent_info(bp);
1367
1368         eth_dev->dev_ops = NULL;
1369         eth_dev->rx_pkt_burst = NULL;
1370         eth_dev->tx_pkt_burst = NULL;
1371
1372         rte_memzone_free((const struct rte_memzone *)bp->tx_mem_zone);
1373         bp->tx_mem_zone = NULL;
1374         rte_memzone_free((const struct rte_memzone *)bp->rx_mem_zone);
1375         bp->rx_mem_zone = NULL;
1376
1377         bnxt_hwrm_free_vf_info(bp);
1378
1379         rte_free(bp->grp_info);
1380         bp->grp_info = NULL;
1381 }
1382
1383 static void bnxt_mac_addr_remove_op(struct rte_eth_dev *eth_dev,
1384                                     uint32_t index)
1385 {
1386         struct bnxt *bp = eth_dev->data->dev_private;
1387         uint64_t pool_mask = eth_dev->data->mac_pool_sel[index];
1388         struct bnxt_vnic_info *vnic;
1389         struct bnxt_filter_info *filter, *temp_filter;
1390         uint32_t i;
1391
1392         if (is_bnxt_in_error(bp))
1393                 return;
1394
1395         /*
1396          * Loop through all VNICs from the specified filter flow pools to
1397          * remove the corresponding MAC addr filter
1398          */
1399         for (i = 0; i < bp->nr_vnics; i++) {
1400                 if (!(pool_mask & (1ULL << i)))
1401                         continue;
1402
1403                 vnic = &bp->vnic_info[i];
1404                 filter = STAILQ_FIRST(&vnic->filter);
1405                 while (filter) {
1406                         temp_filter = STAILQ_NEXT(filter, next);
1407                         if (filter->mac_index == index) {
1408                                 STAILQ_REMOVE(&vnic->filter, filter,
1409                                                 bnxt_filter_info, next);
1410                                 bnxt_hwrm_clear_l2_filter(bp, filter);
1411                                 bnxt_free_filter(bp, filter);
1412                         }
1413                         filter = temp_filter;
1414                 }
1415         }
1416 }
1417
1418 static int bnxt_add_mac_filter(struct bnxt *bp, struct bnxt_vnic_info *vnic,
1419                                struct rte_ether_addr *mac_addr, uint32_t index,
1420                                uint32_t pool)
1421 {
1422         struct bnxt_filter_info *filter;
1423         int rc = 0;
1424
1425         /* Attach requested MAC address to the new l2_filter */
1426         STAILQ_FOREACH(filter, &vnic->filter, next) {
1427                 if (filter->mac_index == index) {
1428                         PMD_DRV_LOG(DEBUG,
1429                                     "MAC addr already existed for pool %d\n",
1430                                     pool);
1431                         return 0;
1432                 }
1433         }
1434
1435         filter = bnxt_alloc_filter(bp);
1436         if (!filter) {
1437                 PMD_DRV_LOG(ERR, "L2 filter alloc failed\n");
1438                 return -ENODEV;
1439         }
1440
1441         /* bnxt_alloc_filter copies default MAC to filter->l2_addr. So,
1442          * if the MAC that's been programmed now is a different one, then,
1443          * copy that addr to filter->l2_addr
1444          */
1445         if (mac_addr)
1446                 memcpy(filter->l2_addr, mac_addr, RTE_ETHER_ADDR_LEN);
1447         filter->flags |= HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_OUTERMOST;
1448
1449         rc = bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id, filter);
1450         if (!rc) {
1451                 filter->mac_index = index;
1452                 if (filter->mac_index == 0)
1453                         STAILQ_INSERT_HEAD(&vnic->filter, filter, next);
1454                 else
1455                         STAILQ_INSERT_TAIL(&vnic->filter, filter, next);
1456         } else {
1457                 bnxt_free_filter(bp, filter);
1458         }
1459
1460         return rc;
1461 }
1462
1463 static int bnxt_mac_addr_add_op(struct rte_eth_dev *eth_dev,
1464                                 struct rte_ether_addr *mac_addr,
1465                                 uint32_t index, uint32_t pool)
1466 {
1467         struct bnxt *bp = eth_dev->data->dev_private;
1468         struct bnxt_vnic_info *vnic = &bp->vnic_info[pool];
1469         int rc = 0;
1470
1471         rc = is_bnxt_in_error(bp);
1472         if (rc)
1473                 return rc;
1474
1475         if (BNXT_VF(bp) & !BNXT_VF_IS_TRUSTED(bp)) {
1476                 PMD_DRV_LOG(ERR, "Cannot add MAC address to a VF interface\n");
1477                 return -ENOTSUP;
1478         }
1479
1480         if (!vnic) {
1481                 PMD_DRV_LOG(ERR, "VNIC not found for pool %d!\n", pool);
1482                 return -EINVAL;
1483         }
1484
1485         /* Filter settings will get applied when port is started */
1486         if (!eth_dev->data->dev_started)
1487                 return 0;
1488
1489         rc = bnxt_add_mac_filter(bp, vnic, mac_addr, index, pool);
1490
1491         return rc;
1492 }
1493
1494 int bnxt_link_update(struct rte_eth_dev *eth_dev, int wait_to_complete,
1495                      bool exp_link_status)
1496 {
1497         int rc = 0;
1498         struct bnxt *bp = eth_dev->data->dev_private;
1499         struct rte_eth_link new;
1500         int cnt = exp_link_status ? BNXT_LINK_UP_WAIT_CNT :
1501                   BNXT_LINK_DOWN_WAIT_CNT;
1502
1503         rc = is_bnxt_in_error(bp);
1504         if (rc)
1505                 return rc;
1506
1507         memset(&new, 0, sizeof(new));
1508         do {
1509                 /* Retrieve link info from hardware */
1510                 rc = bnxt_get_hwrm_link_config(bp, &new);
1511                 if (rc) {
1512                         new.link_speed = ETH_LINK_SPEED_100M;
1513                         new.link_duplex = ETH_LINK_FULL_DUPLEX;
1514                         PMD_DRV_LOG(ERR,
1515                                 "Failed to retrieve link rc = 0x%x!\n", rc);
1516                         goto out;
1517                 }
1518
1519                 if (!wait_to_complete || new.link_status == exp_link_status)
1520                         break;
1521
1522                 rte_delay_ms(BNXT_LINK_WAIT_INTERVAL);
1523         } while (cnt--);
1524
1525 out:
1526         /* Timed out or success */
1527         if (new.link_status != eth_dev->data->dev_link.link_status ||
1528         new.link_speed != eth_dev->data->dev_link.link_speed) {
1529                 rte_eth_linkstatus_set(eth_dev, &new);
1530
1531                 rte_eth_dev_callback_process(eth_dev,
1532                                              RTE_ETH_EVENT_INTR_LSC,
1533                                              NULL);
1534
1535                 bnxt_print_link_info(eth_dev);
1536         }
1537
1538         return rc;
1539 }
1540
1541 int bnxt_link_update_op(struct rte_eth_dev *eth_dev,
1542                         int wait_to_complete)
1543 {
1544         return bnxt_link_update(eth_dev, wait_to_complete, ETH_LINK_UP);
1545 }
1546
1547 static int bnxt_promiscuous_enable_op(struct rte_eth_dev *eth_dev)
1548 {
1549         struct bnxt *bp = eth_dev->data->dev_private;
1550         struct bnxt_vnic_info *vnic;
1551         uint32_t old_flags;
1552         int rc;
1553
1554         rc = is_bnxt_in_error(bp);
1555         if (rc)
1556                 return rc;
1557
1558         /* Filter settings will get applied when port is started */
1559         if (!eth_dev->data->dev_started)
1560                 return 0;
1561
1562         if (bp->vnic_info == NULL)
1563                 return 0;
1564
1565         vnic = BNXT_GET_DEFAULT_VNIC(bp);
1566
1567         old_flags = vnic->flags;
1568         vnic->flags |= BNXT_VNIC_INFO_PROMISC;
1569         rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1570         if (rc != 0)
1571                 vnic->flags = old_flags;
1572
1573         return rc;
1574 }
1575
1576 static int bnxt_promiscuous_disable_op(struct rte_eth_dev *eth_dev)
1577 {
1578         struct bnxt *bp = eth_dev->data->dev_private;
1579         struct bnxt_vnic_info *vnic;
1580         uint32_t old_flags;
1581         int rc;
1582
1583         rc = is_bnxt_in_error(bp);
1584         if (rc)
1585                 return rc;
1586
1587         /* Filter settings will get applied when port is started */
1588         if (!eth_dev->data->dev_started)
1589                 return 0;
1590
1591         if (bp->vnic_info == NULL)
1592                 return 0;
1593
1594         vnic = BNXT_GET_DEFAULT_VNIC(bp);
1595
1596         old_flags = vnic->flags;
1597         vnic->flags &= ~BNXT_VNIC_INFO_PROMISC;
1598         rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1599         if (rc != 0)
1600                 vnic->flags = old_flags;
1601
1602         bnxt_ulp_create_df_rules(bp);
1603
1604         return rc;
1605 }
1606
1607 static int bnxt_allmulticast_enable_op(struct rte_eth_dev *eth_dev)
1608 {
1609         struct bnxt *bp = eth_dev->data->dev_private;
1610         struct bnxt_vnic_info *vnic;
1611         uint32_t old_flags;
1612         int rc;
1613
1614         rc = is_bnxt_in_error(bp);
1615         if (rc)
1616                 return rc;
1617
1618         /* Filter settings will get applied when port is started */
1619         if (!eth_dev->data->dev_started)
1620                 return 0;
1621
1622         if (bp->vnic_info == NULL)
1623                 return 0;
1624
1625         vnic = BNXT_GET_DEFAULT_VNIC(bp);
1626
1627         old_flags = vnic->flags;
1628         vnic->flags |= BNXT_VNIC_INFO_ALLMULTI;
1629         rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1630         if (rc != 0)
1631                 vnic->flags = old_flags;
1632
1633         return rc;
1634 }
1635
1636 static int bnxt_allmulticast_disable_op(struct rte_eth_dev *eth_dev)
1637 {
1638         struct bnxt *bp = eth_dev->data->dev_private;
1639         struct bnxt_vnic_info *vnic;
1640         uint32_t old_flags;
1641         int rc;
1642
1643         rc = is_bnxt_in_error(bp);
1644         if (rc)
1645                 return rc;
1646
1647         /* Filter settings will get applied when port is started */
1648         if (!eth_dev->data->dev_started)
1649                 return 0;
1650
1651         if (bp->vnic_info == NULL)
1652                 return 0;
1653
1654         vnic = BNXT_GET_DEFAULT_VNIC(bp);
1655
1656         old_flags = vnic->flags;
1657         vnic->flags &= ~BNXT_VNIC_INFO_ALLMULTI;
1658         rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1659         if (rc != 0)
1660                 vnic->flags = old_flags;
1661
1662         return rc;
1663 }
1664
1665 /* Return bnxt_rx_queue pointer corresponding to a given rxq. */
1666 static struct bnxt_rx_queue *bnxt_qid_to_rxq(struct bnxt *bp, uint16_t qid)
1667 {
1668         if (qid >= bp->rx_nr_rings)
1669                 return NULL;
1670
1671         return bp->eth_dev->data->rx_queues[qid];
1672 }
1673
1674 /* Return rxq corresponding to a given rss table ring/group ID. */
1675 static uint16_t bnxt_rss_to_qid(struct bnxt *bp, uint16_t fwr)
1676 {
1677         struct bnxt_rx_queue *rxq;
1678         unsigned int i;
1679
1680         if (!BNXT_HAS_RING_GRPS(bp)) {
1681                 for (i = 0; i < bp->rx_nr_rings; i++) {
1682                         rxq = bp->eth_dev->data->rx_queues[i];
1683                         if (rxq->rx_ring->rx_ring_struct->fw_ring_id == fwr)
1684                                 return rxq->index;
1685                 }
1686         } else {
1687                 for (i = 0; i < bp->rx_nr_rings; i++) {
1688                         if (bp->grp_info[i].fw_grp_id == fwr)
1689                                 return i;
1690                 }
1691         }
1692
1693         return INVALID_HW_RING_ID;
1694 }
1695
1696 static int bnxt_reta_update_op(struct rte_eth_dev *eth_dev,
1697                             struct rte_eth_rss_reta_entry64 *reta_conf,
1698                             uint16_t reta_size)
1699 {
1700         struct bnxt *bp = eth_dev->data->dev_private;
1701         struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
1702         struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp);
1703         uint16_t tbl_size = bnxt_rss_hash_tbl_size(bp);
1704         uint16_t idx, sft;
1705         int i, rc;
1706
1707         rc = is_bnxt_in_error(bp);
1708         if (rc)
1709                 return rc;
1710
1711         if (!vnic->rss_table)
1712                 return -EINVAL;
1713
1714         if (!(dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG))
1715                 return -EINVAL;
1716
1717         if (reta_size != tbl_size) {
1718                 PMD_DRV_LOG(ERR, "The configured hash table lookup size "
1719                         "(%d) must equal the size supported by the hardware "
1720                         "(%d)\n", reta_size, tbl_size);
1721                 return -EINVAL;
1722         }
1723
1724         for (i = 0; i < reta_size; i++) {
1725                 struct bnxt_rx_queue *rxq;
1726
1727                 idx = i / RTE_RETA_GROUP_SIZE;
1728                 sft = i % RTE_RETA_GROUP_SIZE;
1729
1730                 if (!(reta_conf[idx].mask & (1ULL << sft)))
1731                         continue;
1732
1733                 rxq = bnxt_qid_to_rxq(bp, reta_conf[idx].reta[sft]);
1734                 if (!rxq) {
1735                         PMD_DRV_LOG(ERR, "Invalid ring in reta_conf.\n");
1736                         return -EINVAL;
1737                 }
1738
1739                 if (BNXT_CHIP_THOR(bp)) {
1740                         vnic->rss_table[i * 2] =
1741                                 rxq->rx_ring->rx_ring_struct->fw_ring_id;
1742                         vnic->rss_table[i * 2 + 1] =
1743                                 rxq->cp_ring->cp_ring_struct->fw_ring_id;
1744                 } else {
1745                         vnic->rss_table[i] =
1746                             vnic->fw_grp_ids[reta_conf[idx].reta[sft]];
1747                 }
1748         }
1749
1750         bnxt_hwrm_vnic_rss_cfg(bp, vnic);
1751         return 0;
1752 }
1753
1754 static int bnxt_reta_query_op(struct rte_eth_dev *eth_dev,
1755                               struct rte_eth_rss_reta_entry64 *reta_conf,
1756                               uint16_t reta_size)
1757 {
1758         struct bnxt *bp = eth_dev->data->dev_private;
1759         struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp);
1760         uint16_t tbl_size = bnxt_rss_hash_tbl_size(bp);
1761         uint16_t idx, sft, i;
1762         int rc;
1763
1764         rc = is_bnxt_in_error(bp);
1765         if (rc)
1766                 return rc;
1767
1768         /* Retrieve from the default VNIC */
1769         if (!vnic)
1770                 return -EINVAL;
1771         if (!vnic->rss_table)
1772                 return -EINVAL;
1773
1774         if (reta_size != tbl_size) {
1775                 PMD_DRV_LOG(ERR, "The configured hash table lookup size "
1776                         "(%d) must equal the size supported by the hardware "
1777                         "(%d)\n", reta_size, tbl_size);
1778                 return -EINVAL;
1779         }
1780
1781         for (idx = 0, i = 0; i < reta_size; i++) {
1782                 idx = i / RTE_RETA_GROUP_SIZE;
1783                 sft = i % RTE_RETA_GROUP_SIZE;
1784
1785                 if (reta_conf[idx].mask & (1ULL << sft)) {
1786                         uint16_t qid;
1787
1788                         if (BNXT_CHIP_THOR(bp))
1789                                 qid = bnxt_rss_to_qid(bp,
1790                                                       vnic->rss_table[i * 2]);
1791                         else
1792                                 qid = bnxt_rss_to_qid(bp, vnic->rss_table[i]);
1793
1794                         if (qid == INVALID_HW_RING_ID) {
1795                                 PMD_DRV_LOG(ERR, "Inv. entry in rss table.\n");
1796                                 return -EINVAL;
1797                         }
1798                         reta_conf[idx].reta[sft] = qid;
1799                 }
1800         }
1801
1802         return 0;
1803 }
1804
1805 static int bnxt_rss_hash_update_op(struct rte_eth_dev *eth_dev,
1806                                    struct rte_eth_rss_conf *rss_conf)
1807 {
1808         struct bnxt *bp = eth_dev->data->dev_private;
1809         struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
1810         struct bnxt_vnic_info *vnic;
1811         int rc;
1812
1813         rc = is_bnxt_in_error(bp);
1814         if (rc)
1815                 return rc;
1816
1817         /*
1818          * If RSS enablement were different than dev_configure,
1819          * then return -EINVAL
1820          */
1821         if (dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG) {
1822                 if (!rss_conf->rss_hf)
1823                         PMD_DRV_LOG(ERR, "Hash type NONE\n");
1824         } else {
1825                 if (rss_conf->rss_hf & BNXT_ETH_RSS_SUPPORT)
1826                         return -EINVAL;
1827         }
1828
1829         bp->flags |= BNXT_FLAG_UPDATE_HASH;
1830         memcpy(&eth_dev->data->dev_conf.rx_adv_conf.rss_conf,
1831                rss_conf,
1832                sizeof(*rss_conf));
1833
1834         /* Update the default RSS VNIC(s) */
1835         vnic = BNXT_GET_DEFAULT_VNIC(bp);
1836         vnic->hash_type = bnxt_rte_to_hwrm_hash_types(rss_conf->rss_hf);
1837
1838         /*
1839          * If hashkey is not specified, use the previously configured
1840          * hashkey
1841          */
1842         if (!rss_conf->rss_key)
1843                 goto rss_config;
1844
1845         if (rss_conf->rss_key_len != HW_HASH_KEY_SIZE) {
1846                 PMD_DRV_LOG(ERR,
1847                             "Invalid hashkey length, should be 16 bytes\n");
1848                 return -EINVAL;
1849         }
1850         memcpy(vnic->rss_hash_key, rss_conf->rss_key, rss_conf->rss_key_len);
1851
1852 rss_config:
1853         bnxt_hwrm_vnic_rss_cfg(bp, vnic);
1854         return 0;
1855 }
1856
1857 static int bnxt_rss_hash_conf_get_op(struct rte_eth_dev *eth_dev,
1858                                      struct rte_eth_rss_conf *rss_conf)
1859 {
1860         struct bnxt *bp = eth_dev->data->dev_private;
1861         struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp);
1862         int len, rc;
1863         uint32_t hash_types;
1864
1865         rc = is_bnxt_in_error(bp);
1866         if (rc)
1867                 return rc;
1868
1869         /* RSS configuration is the same for all VNICs */
1870         if (vnic && vnic->rss_hash_key) {
1871                 if (rss_conf->rss_key) {
1872                         len = rss_conf->rss_key_len <= HW_HASH_KEY_SIZE ?
1873                               rss_conf->rss_key_len : HW_HASH_KEY_SIZE;
1874                         memcpy(rss_conf->rss_key, vnic->rss_hash_key, len);
1875                 }
1876
1877                 hash_types = vnic->hash_type;
1878                 rss_conf->rss_hf = 0;
1879                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV4) {
1880                         rss_conf->rss_hf |= ETH_RSS_IPV4;
1881                         hash_types &= ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV4;
1882                 }
1883                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV4) {
1884                         rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP;
1885                         hash_types &=
1886                                 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV4;
1887                 }
1888                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV4) {
1889                         rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
1890                         hash_types &=
1891                                 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV4;
1892                 }
1893                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6) {
1894                         rss_conf->rss_hf |= ETH_RSS_IPV6;
1895                         hash_types &= ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6;
1896                 }
1897                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV6) {
1898                         rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV6_TCP;
1899                         hash_types &=
1900                                 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV6;
1901                 }
1902                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV6) {
1903                         rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;
1904                         hash_types &=
1905                                 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV6;
1906                 }
1907                 if (hash_types) {
1908                         PMD_DRV_LOG(ERR,
1909                                 "Unknown RSS config from firmware (%08x), RSS disabled",
1910                                 vnic->hash_type);
1911                         return -ENOTSUP;
1912                 }
1913         } else {
1914                 rss_conf->rss_hf = 0;
1915         }
1916         return 0;
1917 }
1918
1919 static int bnxt_flow_ctrl_get_op(struct rte_eth_dev *dev,
1920                                struct rte_eth_fc_conf *fc_conf)
1921 {
1922         struct bnxt *bp = dev->data->dev_private;
1923         struct rte_eth_link link_info;
1924         int rc;
1925
1926         rc = is_bnxt_in_error(bp);
1927         if (rc)
1928                 return rc;
1929
1930         rc = bnxt_get_hwrm_link_config(bp, &link_info);
1931         if (rc)
1932                 return rc;
1933
1934         memset(fc_conf, 0, sizeof(*fc_conf));
1935         if (bp->link_info->auto_pause)
1936                 fc_conf->autoneg = 1;
1937         switch (bp->link_info->pause) {
1938         case 0:
1939                 fc_conf->mode = RTE_FC_NONE;
1940                 break;
1941         case HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_TX:
1942                 fc_conf->mode = RTE_FC_TX_PAUSE;
1943                 break;
1944         case HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_RX:
1945                 fc_conf->mode = RTE_FC_RX_PAUSE;
1946                 break;
1947         case (HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_TX |
1948                         HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_RX):
1949                 fc_conf->mode = RTE_FC_FULL;
1950                 break;
1951         }
1952         return 0;
1953 }
1954
1955 static int bnxt_flow_ctrl_set_op(struct rte_eth_dev *dev,
1956                                struct rte_eth_fc_conf *fc_conf)
1957 {
1958         struct bnxt *bp = dev->data->dev_private;
1959         int rc;
1960
1961         rc = is_bnxt_in_error(bp);
1962         if (rc)
1963                 return rc;
1964
1965         if (!BNXT_SINGLE_PF(bp) || BNXT_VF(bp)) {
1966                 PMD_DRV_LOG(ERR, "Flow Control Settings cannot be modified\n");
1967                 return -ENOTSUP;
1968         }
1969
1970         switch (fc_conf->mode) {
1971         case RTE_FC_NONE:
1972                 bp->link_info->auto_pause = 0;
1973                 bp->link_info->force_pause = 0;
1974                 break;
1975         case RTE_FC_RX_PAUSE:
1976                 if (fc_conf->autoneg) {
1977                         bp->link_info->auto_pause =
1978                                         HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_RX;
1979                         bp->link_info->force_pause = 0;
1980                 } else {
1981                         bp->link_info->auto_pause = 0;
1982                         bp->link_info->force_pause =
1983                                         HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_RX;
1984                 }
1985                 break;
1986         case RTE_FC_TX_PAUSE:
1987                 if (fc_conf->autoneg) {
1988                         bp->link_info->auto_pause =
1989                                         HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_TX;
1990                         bp->link_info->force_pause = 0;
1991                 } else {
1992                         bp->link_info->auto_pause = 0;
1993                         bp->link_info->force_pause =
1994                                         HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_TX;
1995                 }
1996                 break;
1997         case RTE_FC_FULL:
1998                 if (fc_conf->autoneg) {
1999                         bp->link_info->auto_pause =
2000                                         HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_TX |
2001                                         HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_RX;
2002                         bp->link_info->force_pause = 0;
2003                 } else {
2004                         bp->link_info->auto_pause = 0;
2005                         bp->link_info->force_pause =
2006                                         HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_TX |
2007                                         HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_RX;
2008                 }
2009                 break;
2010         }
2011         return bnxt_set_hwrm_link_config(bp, true);
2012 }
2013
2014 /* Add UDP tunneling port */
2015 static int
2016 bnxt_udp_tunnel_port_add_op(struct rte_eth_dev *eth_dev,
2017                          struct rte_eth_udp_tunnel *udp_tunnel)
2018 {
2019         struct bnxt *bp = eth_dev->data->dev_private;
2020         uint16_t tunnel_type = 0;
2021         int rc = 0;
2022
2023         rc = is_bnxt_in_error(bp);
2024         if (rc)
2025                 return rc;
2026
2027         switch (udp_tunnel->prot_type) {
2028         case RTE_TUNNEL_TYPE_VXLAN:
2029                 if (bp->vxlan_port_cnt) {
2030                         PMD_DRV_LOG(ERR, "Tunnel Port %d already programmed\n",
2031                                 udp_tunnel->udp_port);
2032                         if (bp->vxlan_port != udp_tunnel->udp_port) {
2033                                 PMD_DRV_LOG(ERR, "Only one port allowed\n");
2034                                 return -ENOSPC;
2035                         }
2036                         bp->vxlan_port_cnt++;
2037                         return 0;
2038                 }
2039                 tunnel_type =
2040                         HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_VXLAN;
2041                 bp->vxlan_port_cnt++;
2042                 break;
2043         case RTE_TUNNEL_TYPE_GENEVE:
2044                 if (bp->geneve_port_cnt) {
2045                         PMD_DRV_LOG(ERR, "Tunnel Port %d already programmed\n",
2046                                 udp_tunnel->udp_port);
2047                         if (bp->geneve_port != udp_tunnel->udp_port) {
2048                                 PMD_DRV_LOG(ERR, "Only one port allowed\n");
2049                                 return -ENOSPC;
2050                         }
2051                         bp->geneve_port_cnt++;
2052                         return 0;
2053                 }
2054                 tunnel_type =
2055                         HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_GENEVE;
2056                 bp->geneve_port_cnt++;
2057                 break;
2058         default:
2059                 PMD_DRV_LOG(ERR, "Tunnel type is not supported\n");
2060                 return -ENOTSUP;
2061         }
2062         rc = bnxt_hwrm_tunnel_dst_port_alloc(bp, udp_tunnel->udp_port,
2063                                              tunnel_type);
2064         return rc;
2065 }
2066
2067 static int
2068 bnxt_udp_tunnel_port_del_op(struct rte_eth_dev *eth_dev,
2069                          struct rte_eth_udp_tunnel *udp_tunnel)
2070 {
2071         struct bnxt *bp = eth_dev->data->dev_private;
2072         uint16_t tunnel_type = 0;
2073         uint16_t port = 0;
2074         int rc = 0;
2075
2076         rc = is_bnxt_in_error(bp);
2077         if (rc)
2078                 return rc;
2079
2080         switch (udp_tunnel->prot_type) {
2081         case RTE_TUNNEL_TYPE_VXLAN:
2082                 if (!bp->vxlan_port_cnt) {
2083                         PMD_DRV_LOG(ERR, "No Tunnel port configured yet\n");
2084                         return -EINVAL;
2085                 }
2086                 if (bp->vxlan_port != udp_tunnel->udp_port) {
2087                         PMD_DRV_LOG(ERR, "Req Port: %d. Configured port: %d\n",
2088                                 udp_tunnel->udp_port, bp->vxlan_port);
2089                         return -EINVAL;
2090                 }
2091                 if (--bp->vxlan_port_cnt)
2092                         return 0;
2093
2094                 tunnel_type =
2095                         HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN;
2096                 port = bp->vxlan_fw_dst_port_id;
2097                 break;
2098         case RTE_TUNNEL_TYPE_GENEVE:
2099                 if (!bp->geneve_port_cnt) {
2100                         PMD_DRV_LOG(ERR, "No Tunnel port configured yet\n");
2101                         return -EINVAL;
2102                 }
2103                 if (bp->geneve_port != udp_tunnel->udp_port) {
2104                         PMD_DRV_LOG(ERR, "Req Port: %d. Configured port: %d\n",
2105                                 udp_tunnel->udp_port, bp->geneve_port);
2106                         return -EINVAL;
2107                 }
2108                 if (--bp->geneve_port_cnt)
2109                         return 0;
2110
2111                 tunnel_type =
2112                         HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_GENEVE;
2113                 port = bp->geneve_fw_dst_port_id;
2114                 break;
2115         default:
2116                 PMD_DRV_LOG(ERR, "Tunnel type is not supported\n");
2117                 return -ENOTSUP;
2118         }
2119
2120         rc = bnxt_hwrm_tunnel_dst_port_free(bp, port, tunnel_type);
2121         if (!rc) {
2122                 if (tunnel_type ==
2123                     HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN)
2124                         bp->vxlan_port = 0;
2125                 if (tunnel_type ==
2126                     HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_GENEVE)
2127                         bp->geneve_port = 0;
2128         }
2129         return rc;
2130 }
2131
2132 static int bnxt_del_vlan_filter(struct bnxt *bp, uint16_t vlan_id)
2133 {
2134         struct bnxt_filter_info *filter;
2135         struct bnxt_vnic_info *vnic;
2136         int rc = 0;
2137         uint32_t chk = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN;
2138
2139         vnic = BNXT_GET_DEFAULT_VNIC(bp);
2140         filter = STAILQ_FIRST(&vnic->filter);
2141         while (filter) {
2142                 /* Search for this matching MAC+VLAN filter */
2143                 if (bnxt_vlan_filter_exists(bp, filter, chk, vlan_id)) {
2144                         /* Delete the filter */
2145                         rc = bnxt_hwrm_clear_l2_filter(bp, filter);
2146                         if (rc)
2147                                 return rc;
2148                         STAILQ_REMOVE(&vnic->filter, filter,
2149                                       bnxt_filter_info, next);
2150                         bnxt_free_filter(bp, filter);
2151                         PMD_DRV_LOG(INFO,
2152                                     "Deleted vlan filter for %d\n",
2153                                     vlan_id);
2154                         return 0;
2155                 }
2156                 filter = STAILQ_NEXT(filter, next);
2157         }
2158         return -ENOENT;
2159 }
2160
2161 static int bnxt_add_vlan_filter(struct bnxt *bp, uint16_t vlan_id)
2162 {
2163         struct bnxt_filter_info *filter;
2164         struct bnxt_vnic_info *vnic;
2165         int rc = 0;
2166         uint32_t en = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN |
2167                 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN_MASK;
2168         uint32_t chk = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN;
2169
2170         /* Implementation notes on the use of VNIC in this command:
2171          *
2172          * By default, these filters belong to default vnic for the function.
2173          * Once these filters are set up, only destination VNIC can be modified.
2174          * If the destination VNIC is not specified in this command,
2175          * then the HWRM shall only create an l2 context id.
2176          */
2177
2178         vnic = BNXT_GET_DEFAULT_VNIC(bp);
2179         filter = STAILQ_FIRST(&vnic->filter);
2180         /* Check if the VLAN has already been added */
2181         while (filter) {
2182                 if (bnxt_vlan_filter_exists(bp, filter, chk, vlan_id))
2183                         return -EEXIST;
2184
2185                 filter = STAILQ_NEXT(filter, next);
2186         }
2187
2188         /* No match found. Alloc a fresh filter and issue the L2_FILTER_ALLOC
2189          * command to create MAC+VLAN filter with the right flags, enables set.
2190          */
2191         filter = bnxt_alloc_filter(bp);
2192         if (!filter) {
2193                 PMD_DRV_LOG(ERR,
2194                             "MAC/VLAN filter alloc failed\n");
2195                 return -ENOMEM;
2196         }
2197         /* MAC + VLAN ID filter */
2198         /* If l2_ivlan == 0 and l2_ivlan_mask != 0, only
2199          * untagged packets are received
2200          *
2201          * If l2_ivlan != 0 and l2_ivlan_mask != 0, untagged
2202          * packets and only the programmed vlan's packets are received
2203          */
2204         filter->l2_ivlan = vlan_id;
2205         filter->l2_ivlan_mask = 0x0FFF;
2206         filter->enables |= en;
2207         filter->flags |= HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_OUTERMOST;
2208
2209         rc = bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id, filter);
2210         if (rc) {
2211                 /* Free the newly allocated filter as we were
2212                  * not able to create the filter in hardware.
2213                  */
2214                 bnxt_free_filter(bp, filter);
2215                 return rc;
2216         }
2217
2218         filter->mac_index = 0;
2219         /* Add this new filter to the list */
2220         if (vlan_id == 0)
2221                 STAILQ_INSERT_HEAD(&vnic->filter, filter, next);
2222         else
2223                 STAILQ_INSERT_TAIL(&vnic->filter, filter, next);
2224
2225         PMD_DRV_LOG(INFO,
2226                     "Added Vlan filter for %d\n", vlan_id);
2227         return rc;
2228 }
2229
2230 static int bnxt_vlan_filter_set_op(struct rte_eth_dev *eth_dev,
2231                 uint16_t vlan_id, int on)
2232 {
2233         struct bnxt *bp = eth_dev->data->dev_private;
2234         int rc;
2235
2236         rc = is_bnxt_in_error(bp);
2237         if (rc)
2238                 return rc;
2239
2240         if (!eth_dev->data->dev_started) {
2241                 PMD_DRV_LOG(ERR, "port must be started before setting vlan\n");
2242                 return -EINVAL;
2243         }
2244
2245         /* These operations apply to ALL existing MAC/VLAN filters */
2246         if (on)
2247                 return bnxt_add_vlan_filter(bp, vlan_id);
2248         else
2249                 return bnxt_del_vlan_filter(bp, vlan_id);
2250 }
2251
2252 static int bnxt_del_dflt_mac_filter(struct bnxt *bp,
2253                                     struct bnxt_vnic_info *vnic)
2254 {
2255         struct bnxt_filter_info *filter;
2256         int rc;
2257
2258         filter = STAILQ_FIRST(&vnic->filter);
2259         while (filter) {
2260                 if (filter->mac_index == 0 &&
2261                     !memcmp(filter->l2_addr, bp->mac_addr,
2262                             RTE_ETHER_ADDR_LEN)) {
2263                         rc = bnxt_hwrm_clear_l2_filter(bp, filter);
2264                         if (!rc) {
2265                                 STAILQ_REMOVE(&vnic->filter, filter,
2266                                               bnxt_filter_info, next);
2267                                 bnxt_free_filter(bp, filter);
2268                         }
2269                         return rc;
2270                 }
2271                 filter = STAILQ_NEXT(filter, next);
2272         }
2273         return 0;
2274 }
2275
2276 static int
2277 bnxt_config_vlan_hw_filter(struct bnxt *bp, uint64_t rx_offloads)
2278 {
2279         struct bnxt_vnic_info *vnic;
2280         unsigned int i;
2281         int rc;
2282
2283         vnic = BNXT_GET_DEFAULT_VNIC(bp);
2284         if (!(rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER)) {
2285                 /* Remove any VLAN filters programmed */
2286                 for (i = 0; i < RTE_ETHER_MAX_VLAN_ID; i++)
2287                         bnxt_del_vlan_filter(bp, i);
2288
2289                 rc = bnxt_add_mac_filter(bp, vnic, NULL, 0, 0);
2290                 if (rc)
2291                         return rc;
2292         } else {
2293                 /* Default filter will allow packets that match the
2294                  * dest mac. So, it has to be deleted, otherwise, we
2295                  * will endup receiving vlan packets for which the
2296                  * filter is not programmed, when hw-vlan-filter
2297                  * configuration is ON
2298                  */
2299                 bnxt_del_dflt_mac_filter(bp, vnic);
2300                 /* This filter will allow only untagged packets */
2301                 bnxt_add_vlan_filter(bp, 0);
2302         }
2303         PMD_DRV_LOG(DEBUG, "VLAN Filtering: %d\n",
2304                     !!(rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER));
2305
2306         return 0;
2307 }
2308
2309 static int bnxt_free_one_vnic(struct bnxt *bp, uint16_t vnic_id)
2310 {
2311         struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id];
2312         unsigned int i;
2313         int rc;
2314
2315         /* Destroy vnic filters and vnic */
2316         if (bp->eth_dev->data->dev_conf.rxmode.offloads &
2317             DEV_RX_OFFLOAD_VLAN_FILTER) {
2318                 for (i = 0; i < RTE_ETHER_MAX_VLAN_ID; i++)
2319                         bnxt_del_vlan_filter(bp, i);
2320         }
2321         bnxt_del_dflt_mac_filter(bp, vnic);
2322
2323         rc = bnxt_hwrm_vnic_free(bp, vnic);
2324         if (rc)
2325                 return rc;
2326
2327         rte_free(vnic->fw_grp_ids);
2328         vnic->fw_grp_ids = NULL;
2329
2330         vnic->rx_queue_cnt = 0;
2331
2332         return 0;
2333 }
2334
2335 static int
2336 bnxt_config_vlan_hw_stripping(struct bnxt *bp, uint64_t rx_offloads)
2337 {
2338         struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp);
2339         int rc;
2340
2341         /* Destroy, recreate and reconfigure the default vnic */
2342         rc = bnxt_free_one_vnic(bp, 0);
2343         if (rc)
2344                 return rc;
2345
2346         /* default vnic 0 */
2347         rc = bnxt_setup_one_vnic(bp, 0);
2348         if (rc)
2349                 return rc;
2350
2351         if (bp->eth_dev->data->dev_conf.rxmode.offloads &
2352             DEV_RX_OFFLOAD_VLAN_FILTER) {
2353                 rc = bnxt_add_vlan_filter(bp, 0);
2354                 if (rc)
2355                         return rc;
2356                 rc = bnxt_restore_vlan_filters(bp);
2357                 if (rc)
2358                         return rc;
2359         } else {
2360                 rc = bnxt_add_mac_filter(bp, vnic, NULL, 0, 0);
2361                 if (rc)
2362                         return rc;
2363         }
2364
2365         rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
2366         if (rc)
2367                 return rc;
2368
2369         PMD_DRV_LOG(DEBUG, "VLAN Strip Offload: %d\n",
2370                     !!(rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP));
2371
2372         return rc;
2373 }
2374
2375 static int
2376 bnxt_vlan_offload_set_op(struct rte_eth_dev *dev, int mask)
2377 {
2378         uint64_t rx_offloads = dev->data->dev_conf.rxmode.offloads;
2379         struct bnxt *bp = dev->data->dev_private;
2380         int rc;
2381
2382         rc = is_bnxt_in_error(bp);
2383         if (rc)
2384                 return rc;
2385
2386         /* Filter settings will get applied when port is started */
2387         if (!dev->data->dev_started)
2388                 return 0;
2389
2390         if (mask & ETH_VLAN_FILTER_MASK) {
2391                 /* Enable or disable VLAN filtering */
2392                 rc = bnxt_config_vlan_hw_filter(bp, rx_offloads);
2393                 if (rc)
2394                         return rc;
2395         }
2396
2397         if (mask & ETH_VLAN_STRIP_MASK) {
2398                 /* Enable or disable VLAN stripping */
2399                 rc = bnxt_config_vlan_hw_stripping(bp, rx_offloads);
2400                 if (rc)
2401                         return rc;
2402         }
2403
2404         if (mask & ETH_VLAN_EXTEND_MASK) {
2405                 if (rx_offloads & DEV_RX_OFFLOAD_VLAN_EXTEND)
2406                         PMD_DRV_LOG(DEBUG, "Extend VLAN supported\n");
2407                 else
2408                         PMD_DRV_LOG(INFO, "Extend VLAN unsupported\n");
2409         }
2410
2411         return 0;
2412 }
2413
2414 static int
2415 bnxt_vlan_tpid_set_op(struct rte_eth_dev *dev, enum rte_vlan_type vlan_type,
2416                       uint16_t tpid)
2417 {
2418         struct bnxt *bp = dev->data->dev_private;
2419         int qinq = dev->data->dev_conf.rxmode.offloads &
2420                    DEV_RX_OFFLOAD_VLAN_EXTEND;
2421
2422         if (vlan_type != ETH_VLAN_TYPE_INNER &&
2423             vlan_type != ETH_VLAN_TYPE_OUTER) {
2424                 PMD_DRV_LOG(ERR,
2425                             "Unsupported vlan type.");
2426                 return -EINVAL;
2427         }
2428         if (!qinq) {
2429                 PMD_DRV_LOG(ERR,
2430                             "QinQ not enabled. Needs to be ON as we can "
2431                             "accelerate only outer vlan\n");
2432                 return -EINVAL;
2433         }
2434
2435         if (vlan_type == ETH_VLAN_TYPE_OUTER) {
2436                 switch (tpid) {
2437                 case RTE_ETHER_TYPE_QINQ:
2438                         bp->outer_tpid_bd =
2439                                 TX_BD_LONG_CFA_META_VLAN_TPID_TPID88A8;
2440                                 break;
2441                 case RTE_ETHER_TYPE_VLAN:
2442                         bp->outer_tpid_bd =
2443                                 TX_BD_LONG_CFA_META_VLAN_TPID_TPID8100;
2444                                 break;
2445                 case RTE_ETHER_TYPE_QINQ1:
2446                         bp->outer_tpid_bd =
2447                                 TX_BD_LONG_CFA_META_VLAN_TPID_TPID9100;
2448                                 break;
2449                 case RTE_ETHER_TYPE_QINQ2:
2450                         bp->outer_tpid_bd =
2451                                 TX_BD_LONG_CFA_META_VLAN_TPID_TPID9200;
2452                                 break;
2453                 case RTE_ETHER_TYPE_QINQ3:
2454                         bp->outer_tpid_bd =
2455                                  TX_BD_LONG_CFA_META_VLAN_TPID_TPID9300;
2456                                 break;
2457                 default:
2458                         PMD_DRV_LOG(ERR, "Invalid TPID: %x\n", tpid);
2459                         return -EINVAL;
2460                 }
2461                 bp->outer_tpid_bd |= tpid;
2462                 PMD_DRV_LOG(INFO, "outer_tpid_bd = %x\n", bp->outer_tpid_bd);
2463         } else if (vlan_type == ETH_VLAN_TYPE_INNER) {
2464                 PMD_DRV_LOG(ERR,
2465                             "Can accelerate only outer vlan in QinQ\n");
2466                 return -EINVAL;
2467         }
2468
2469         return 0;
2470 }
2471
2472 static int
2473 bnxt_set_default_mac_addr_op(struct rte_eth_dev *dev,
2474                              struct rte_ether_addr *addr)
2475 {
2476         struct bnxt *bp = dev->data->dev_private;
2477         /* Default Filter is tied to VNIC 0 */
2478         struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp);
2479         int rc;
2480
2481         rc = is_bnxt_in_error(bp);
2482         if (rc)
2483                 return rc;
2484
2485         if (BNXT_VF(bp) && !BNXT_VF_IS_TRUSTED(bp))
2486                 return -EPERM;
2487
2488         if (rte_is_zero_ether_addr(addr))
2489                 return -EINVAL;
2490
2491         /* Filter settings will get applied when port is started */
2492         if (!dev->data->dev_started)
2493                 return 0;
2494
2495         /* Check if the requested MAC is already added */
2496         if (memcmp(addr, bp->mac_addr, RTE_ETHER_ADDR_LEN) == 0)
2497                 return 0;
2498
2499         /* Destroy filter and re-create it */
2500         bnxt_del_dflt_mac_filter(bp, vnic);
2501
2502         memcpy(bp->mac_addr, addr, RTE_ETHER_ADDR_LEN);
2503         if (dev->data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_VLAN_FILTER) {
2504                 /* This filter will allow only untagged packets */
2505                 rc = bnxt_add_vlan_filter(bp, 0);
2506         } else {
2507                 rc = bnxt_add_mac_filter(bp, vnic, addr, 0, 0);
2508         }
2509
2510         PMD_DRV_LOG(DEBUG, "Set MAC addr\n");
2511         return rc;
2512 }
2513
2514 static int
2515 bnxt_dev_set_mc_addr_list_op(struct rte_eth_dev *eth_dev,
2516                           struct rte_ether_addr *mc_addr_set,
2517                           uint32_t nb_mc_addr)
2518 {
2519         struct bnxt *bp = eth_dev->data->dev_private;
2520         char *mc_addr_list = (char *)mc_addr_set;
2521         struct bnxt_vnic_info *vnic;
2522         uint32_t off = 0, i = 0;
2523         int rc;
2524
2525         rc = is_bnxt_in_error(bp);
2526         if (rc)
2527                 return rc;
2528
2529         vnic = BNXT_GET_DEFAULT_VNIC(bp);
2530
2531         if (nb_mc_addr > BNXT_MAX_MC_ADDRS) {
2532                 vnic->flags |= BNXT_VNIC_INFO_ALLMULTI;
2533                 goto allmulti;
2534         }
2535
2536         /* TODO Check for Duplicate mcast addresses */
2537         vnic->flags &= ~BNXT_VNIC_INFO_ALLMULTI;
2538         for (i = 0; i < nb_mc_addr; i++) {
2539                 memcpy(vnic->mc_list + off, &mc_addr_list[i],
2540                         RTE_ETHER_ADDR_LEN);
2541                 off += RTE_ETHER_ADDR_LEN;
2542         }
2543
2544         vnic->mc_addr_cnt = i;
2545         if (vnic->mc_addr_cnt)
2546                 vnic->flags |= BNXT_VNIC_INFO_MCAST;
2547         else
2548                 vnic->flags &= ~BNXT_VNIC_INFO_MCAST;
2549
2550 allmulti:
2551         return bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
2552 }
2553
2554 static int
2555 bnxt_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size)
2556 {
2557         struct bnxt *bp = dev->data->dev_private;
2558         uint8_t fw_major = (bp->fw_ver >> 24) & 0xff;
2559         uint8_t fw_minor = (bp->fw_ver >> 16) & 0xff;
2560         uint8_t fw_updt = (bp->fw_ver >> 8) & 0xff;
2561         uint8_t fw_rsvd = bp->fw_ver & 0xff;
2562         int ret;
2563
2564         ret = snprintf(fw_version, fw_size, "%d.%d.%d.%d",
2565                         fw_major, fw_minor, fw_updt, fw_rsvd);
2566
2567         ret += 1; /* add the size of '\0' */
2568         if (fw_size < (uint32_t)ret)
2569                 return ret;
2570         else
2571                 return 0;
2572 }
2573
2574 static void
2575 bnxt_rxq_info_get_op(struct rte_eth_dev *dev, uint16_t queue_id,
2576         struct rte_eth_rxq_info *qinfo)
2577 {
2578         struct bnxt *bp = dev->data->dev_private;
2579         struct bnxt_rx_queue *rxq;
2580
2581         if (is_bnxt_in_error(bp))
2582                 return;
2583
2584         rxq = dev->data->rx_queues[queue_id];
2585
2586         qinfo->mp = rxq->mb_pool;
2587         qinfo->scattered_rx = dev->data->scattered_rx;
2588         qinfo->nb_desc = rxq->nb_rx_desc;
2589
2590         qinfo->conf.rx_free_thresh = rxq->rx_free_thresh;
2591         qinfo->conf.rx_drop_en = 0;
2592         qinfo->conf.rx_deferred_start = rxq->rx_deferred_start;
2593 }
2594
2595 static void
2596 bnxt_txq_info_get_op(struct rte_eth_dev *dev, uint16_t queue_id,
2597         struct rte_eth_txq_info *qinfo)
2598 {
2599         struct bnxt *bp = dev->data->dev_private;
2600         struct bnxt_tx_queue *txq;
2601
2602         if (is_bnxt_in_error(bp))
2603                 return;
2604
2605         txq = dev->data->tx_queues[queue_id];
2606
2607         qinfo->nb_desc = txq->nb_tx_desc;
2608
2609         qinfo->conf.tx_thresh.pthresh = txq->pthresh;
2610         qinfo->conf.tx_thresh.hthresh = txq->hthresh;
2611         qinfo->conf.tx_thresh.wthresh = txq->wthresh;
2612
2613         qinfo->conf.tx_free_thresh = txq->tx_free_thresh;
2614         qinfo->conf.tx_rs_thresh = 0;
2615         qinfo->conf.tx_deferred_start = txq->tx_deferred_start;
2616 }
2617
2618 static const struct {
2619         eth_rx_burst_t pkt_burst;
2620         const char *info;
2621 } bnxt_rx_burst_info[] = {
2622         {bnxt_recv_pkts,        "Scalar"},
2623 #if defined(RTE_ARCH_X86)
2624         {bnxt_recv_pkts_vec,    "Vector SSE"},
2625 #elif defined(RTE_ARCH_ARM64)
2626         {bnxt_recv_pkts_vec,    "Vector Neon"},
2627 #endif
2628 };
2629
2630 static int
2631 bnxt_rx_burst_mode_get(struct rte_eth_dev *dev, __rte_unused uint16_t queue_id,
2632                        struct rte_eth_burst_mode *mode)
2633 {
2634         eth_rx_burst_t pkt_burst = dev->rx_pkt_burst;
2635         size_t i;
2636
2637         for (i = 0; i < RTE_DIM(bnxt_rx_burst_info); i++) {
2638                 if (pkt_burst == bnxt_rx_burst_info[i].pkt_burst) {
2639                         snprintf(mode->info, sizeof(mode->info), "%s",
2640                                  bnxt_rx_burst_info[i].info);
2641                         return 0;
2642                 }
2643         }
2644
2645         return -EINVAL;
2646 }
2647
2648 static const struct {
2649         eth_tx_burst_t pkt_burst;
2650         const char *info;
2651 } bnxt_tx_burst_info[] = {
2652         {bnxt_xmit_pkts,        "Scalar"},
2653 #if defined(RTE_ARCH_X86)
2654         {bnxt_xmit_pkts_vec,    "Vector SSE"},
2655 #elif defined(RTE_ARCH_ARM64)
2656         {bnxt_xmit_pkts_vec,    "Vector Neon"},
2657 #endif
2658 };
2659
2660 static int
2661 bnxt_tx_burst_mode_get(struct rte_eth_dev *dev, __rte_unused uint16_t queue_id,
2662                        struct rte_eth_burst_mode *mode)
2663 {
2664         eth_tx_burst_t pkt_burst = dev->tx_pkt_burst;
2665         size_t i;
2666
2667         for (i = 0; i < RTE_DIM(bnxt_tx_burst_info); i++) {
2668                 if (pkt_burst == bnxt_tx_burst_info[i].pkt_burst) {
2669                         snprintf(mode->info, sizeof(mode->info), "%s",
2670                                  bnxt_tx_burst_info[i].info);
2671                         return 0;
2672                 }
2673         }
2674
2675         return -EINVAL;
2676 }
2677
2678 int bnxt_mtu_set_op(struct rte_eth_dev *eth_dev, uint16_t new_mtu)
2679 {
2680         struct bnxt *bp = eth_dev->data->dev_private;
2681         uint32_t new_pkt_size;
2682         uint32_t rc = 0;
2683         uint32_t i;
2684
2685         rc = is_bnxt_in_error(bp);
2686         if (rc)
2687                 return rc;
2688
2689         /* Exit if receive queues are not configured yet */
2690         if (!eth_dev->data->nb_rx_queues)
2691                 return rc;
2692
2693         new_pkt_size = new_mtu + RTE_ETHER_HDR_LEN + RTE_ETHER_CRC_LEN +
2694                        VLAN_TAG_SIZE * BNXT_NUM_VLANS;
2695
2696 #if defined(RTE_ARCH_X86) || defined(RTE_ARCH_ARM64)
2697         /*
2698          * If vector-mode tx/rx is active, disallow any MTU change that would
2699          * require scattered receive support.
2700          */
2701         if (eth_dev->data->dev_started &&
2702             (eth_dev->rx_pkt_burst == bnxt_recv_pkts_vec ||
2703              eth_dev->tx_pkt_burst == bnxt_xmit_pkts_vec) &&
2704             (new_pkt_size >
2705              eth_dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM)) {
2706                 PMD_DRV_LOG(ERR,
2707                             "MTU change would require scattered rx support. ");
2708                 PMD_DRV_LOG(ERR, "Stop port before changing MTU.\n");
2709                 return -EINVAL;
2710         }
2711 #endif
2712
2713         if (new_mtu > RTE_ETHER_MTU) {
2714                 bp->flags |= BNXT_FLAG_JUMBO;
2715                 bp->eth_dev->data->dev_conf.rxmode.offloads |=
2716                         DEV_RX_OFFLOAD_JUMBO_FRAME;
2717         } else {
2718                 bp->eth_dev->data->dev_conf.rxmode.offloads &=
2719                         ~DEV_RX_OFFLOAD_JUMBO_FRAME;
2720                 bp->flags &= ~BNXT_FLAG_JUMBO;
2721         }
2722
2723         /* Is there a change in mtu setting? */
2724         if (eth_dev->data->dev_conf.rxmode.max_rx_pkt_len == new_pkt_size)
2725                 return rc;
2726
2727         for (i = 0; i < bp->nr_vnics; i++) {
2728                 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
2729                 uint16_t size = 0;
2730
2731                 vnic->mru = BNXT_VNIC_MRU(new_mtu);
2732                 rc = bnxt_hwrm_vnic_cfg(bp, vnic);
2733                 if (rc)
2734                         break;
2735
2736                 size = rte_pktmbuf_data_room_size(bp->rx_queues[0]->mb_pool);
2737                 size -= RTE_PKTMBUF_HEADROOM;
2738
2739                 if (size < new_mtu) {
2740                         rc = bnxt_hwrm_vnic_plcmode_cfg(bp, vnic);
2741                         if (rc)
2742                                 return rc;
2743                 }
2744         }
2745
2746         if (!rc)
2747                 eth_dev->data->dev_conf.rxmode.max_rx_pkt_len = new_pkt_size;
2748
2749         PMD_DRV_LOG(INFO, "New MTU is %d\n", new_mtu);
2750
2751         return rc;
2752 }
2753
2754 static int
2755 bnxt_vlan_pvid_set_op(struct rte_eth_dev *dev, uint16_t pvid, int on)
2756 {
2757         struct bnxt *bp = dev->data->dev_private;
2758         uint16_t vlan = bp->vlan;
2759         int rc;
2760
2761         rc = is_bnxt_in_error(bp);
2762         if (rc)
2763                 return rc;
2764
2765         if (!BNXT_SINGLE_PF(bp) || BNXT_VF(bp)) {
2766                 PMD_DRV_LOG(ERR,
2767                         "PVID cannot be modified for this function\n");
2768                 return -ENOTSUP;
2769         }
2770         bp->vlan = on ? pvid : 0;
2771
2772         rc = bnxt_hwrm_set_default_vlan(bp, 0, 0);
2773         if (rc)
2774                 bp->vlan = vlan;
2775         return rc;
2776 }
2777
2778 static int
2779 bnxt_dev_led_on_op(struct rte_eth_dev *dev)
2780 {
2781         struct bnxt *bp = dev->data->dev_private;
2782         int rc;
2783
2784         rc = is_bnxt_in_error(bp);
2785         if (rc)
2786                 return rc;
2787
2788         return bnxt_hwrm_port_led_cfg(bp, true);
2789 }
2790
2791 static int
2792 bnxt_dev_led_off_op(struct rte_eth_dev *dev)
2793 {
2794         struct bnxt *bp = dev->data->dev_private;
2795         int rc;
2796
2797         rc = is_bnxt_in_error(bp);
2798         if (rc)
2799                 return rc;
2800
2801         return bnxt_hwrm_port_led_cfg(bp, false);
2802 }
2803
2804 static uint32_t
2805 bnxt_rx_queue_count_op(struct rte_eth_dev *dev, uint16_t rx_queue_id)
2806 {
2807         struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
2808         uint32_t desc = 0, raw_cons = 0, cons;
2809         struct bnxt_cp_ring_info *cpr;
2810         struct bnxt_rx_queue *rxq;
2811         struct rx_pkt_cmpl *rxcmp;
2812         int rc;
2813
2814         rc = is_bnxt_in_error(bp);
2815         if (rc)
2816                 return rc;
2817
2818         rxq = dev->data->rx_queues[rx_queue_id];
2819         cpr = rxq->cp_ring;
2820         raw_cons = cpr->cp_raw_cons;
2821
2822         while (1) {
2823                 cons = RING_CMP(cpr->cp_ring_struct, raw_cons);
2824                 rte_prefetch0(&cpr->cp_desc_ring[cons]);
2825                 rxcmp = (struct rx_pkt_cmpl *)&cpr->cp_desc_ring[cons];
2826
2827                 if (!CMP_VALID(rxcmp, raw_cons, cpr->cp_ring_struct)) {
2828                         break;
2829                 } else {
2830                         raw_cons++;
2831                         desc++;
2832                 }
2833         }
2834
2835         return desc;
2836 }
2837
2838 static int
2839 bnxt_rx_descriptor_status_op(void *rx_queue, uint16_t offset)
2840 {
2841         struct bnxt_rx_queue *rxq = (struct bnxt_rx_queue *)rx_queue;
2842         struct bnxt_rx_ring_info *rxr;
2843         struct bnxt_cp_ring_info *cpr;
2844         struct bnxt_sw_rx_bd *rx_buf;
2845         struct rx_pkt_cmpl *rxcmp;
2846         uint32_t cons, cp_cons;
2847         int rc;
2848
2849         if (!rxq)
2850                 return -EINVAL;
2851
2852         rc = is_bnxt_in_error(rxq->bp);
2853         if (rc)
2854                 return rc;
2855
2856         cpr = rxq->cp_ring;
2857         rxr = rxq->rx_ring;
2858
2859         if (offset >= rxq->nb_rx_desc)
2860                 return -EINVAL;
2861
2862         cons = RING_CMP(cpr->cp_ring_struct, offset);
2863         cp_cons = cpr->cp_raw_cons;
2864         rxcmp = (struct rx_pkt_cmpl *)&cpr->cp_desc_ring[cons];
2865
2866         if (cons > cp_cons) {
2867                 if (CMPL_VALID(rxcmp, cpr->valid))
2868                         return RTE_ETH_RX_DESC_DONE;
2869         } else {
2870                 if (CMPL_VALID(rxcmp, !cpr->valid))
2871                         return RTE_ETH_RX_DESC_DONE;
2872         }
2873         rx_buf = &rxr->rx_buf_ring[cons];
2874         if (rx_buf->mbuf == NULL)
2875                 return RTE_ETH_RX_DESC_UNAVAIL;
2876
2877
2878         return RTE_ETH_RX_DESC_AVAIL;
2879 }
2880
2881 static int
2882 bnxt_tx_descriptor_status_op(void *tx_queue, uint16_t offset)
2883 {
2884         struct bnxt_tx_queue *txq = (struct bnxt_tx_queue *)tx_queue;
2885         struct bnxt_tx_ring_info *txr;
2886         struct bnxt_cp_ring_info *cpr;
2887         struct bnxt_sw_tx_bd *tx_buf;
2888         struct tx_pkt_cmpl *txcmp;
2889         uint32_t cons, cp_cons;
2890         int rc;
2891
2892         if (!txq)
2893                 return -EINVAL;
2894
2895         rc = is_bnxt_in_error(txq->bp);
2896         if (rc)
2897                 return rc;
2898
2899         cpr = txq->cp_ring;
2900         txr = txq->tx_ring;
2901
2902         if (offset >= txq->nb_tx_desc)
2903                 return -EINVAL;
2904
2905         cons = RING_CMP(cpr->cp_ring_struct, offset);
2906         txcmp = (struct tx_pkt_cmpl *)&cpr->cp_desc_ring[cons];
2907         cp_cons = cpr->cp_raw_cons;
2908
2909         if (cons > cp_cons) {
2910                 if (CMPL_VALID(txcmp, cpr->valid))
2911                         return RTE_ETH_TX_DESC_UNAVAIL;
2912         } else {
2913                 if (CMPL_VALID(txcmp, !cpr->valid))
2914                         return RTE_ETH_TX_DESC_UNAVAIL;
2915         }
2916         tx_buf = &txr->tx_buf_ring[cons];
2917         if (tx_buf->mbuf == NULL)
2918                 return RTE_ETH_TX_DESC_DONE;
2919
2920         return RTE_ETH_TX_DESC_FULL;
2921 }
2922
2923 static struct bnxt_filter_info *
2924 bnxt_match_and_validate_ether_filter(struct bnxt *bp,
2925                                 struct rte_eth_ethertype_filter *efilter,
2926                                 struct bnxt_vnic_info *vnic0,
2927                                 struct bnxt_vnic_info *vnic,
2928                                 int *ret)
2929 {
2930         struct bnxt_filter_info *mfilter = NULL;
2931         int match = 0;
2932         *ret = 0;
2933
2934         if (efilter->ether_type == RTE_ETHER_TYPE_IPV4 ||
2935                 efilter->ether_type == RTE_ETHER_TYPE_IPV6) {
2936                 PMD_DRV_LOG(ERR, "invalid ether_type(0x%04x) in"
2937                         " ethertype filter.", efilter->ether_type);
2938                 *ret = -EINVAL;
2939                 goto exit;
2940         }
2941         if (efilter->queue >= bp->rx_nr_rings) {
2942                 PMD_DRV_LOG(ERR, "Invalid queue %d\n", efilter->queue);
2943                 *ret = -EINVAL;
2944                 goto exit;
2945         }
2946
2947         vnic0 = BNXT_GET_DEFAULT_VNIC(bp);
2948         vnic = &bp->vnic_info[efilter->queue];
2949         if (vnic == NULL) {
2950                 PMD_DRV_LOG(ERR, "Invalid queue %d\n", efilter->queue);
2951                 *ret = -EINVAL;
2952                 goto exit;
2953         }
2954
2955         if (efilter->flags & RTE_ETHTYPE_FLAGS_DROP) {
2956                 STAILQ_FOREACH(mfilter, &vnic0->filter, next) {
2957                         if ((!memcmp(efilter->mac_addr.addr_bytes,
2958                                      mfilter->l2_addr, RTE_ETHER_ADDR_LEN) &&
2959                              mfilter->flags ==
2960                              HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_DROP &&
2961                              mfilter->ethertype == efilter->ether_type)) {
2962                                 match = 1;
2963                                 break;
2964                         }
2965                 }
2966         } else {
2967                 STAILQ_FOREACH(mfilter, &vnic->filter, next)
2968                         if ((!memcmp(efilter->mac_addr.addr_bytes,
2969                                      mfilter->l2_addr, RTE_ETHER_ADDR_LEN) &&
2970                              mfilter->ethertype == efilter->ether_type &&
2971                              mfilter->flags ==
2972                              HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_PATH_RX)) {
2973                                 match = 1;
2974                                 break;
2975                         }
2976         }
2977
2978         if (match)
2979                 *ret = -EEXIST;
2980
2981 exit:
2982         return mfilter;
2983 }
2984
2985 static int
2986 bnxt_ethertype_filter(struct rte_eth_dev *dev,
2987                         enum rte_filter_op filter_op,
2988                         void *arg)
2989 {
2990         struct bnxt *bp = dev->data->dev_private;
2991         struct rte_eth_ethertype_filter *efilter =
2992                         (struct rte_eth_ethertype_filter *)arg;
2993         struct bnxt_filter_info *bfilter, *filter1;
2994         struct bnxt_vnic_info *vnic, *vnic0;
2995         int ret;
2996
2997         if (filter_op == RTE_ETH_FILTER_NOP)
2998                 return 0;
2999
3000         if (arg == NULL) {
3001                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
3002                             filter_op);
3003                 return -EINVAL;
3004         }
3005
3006         vnic0 = BNXT_GET_DEFAULT_VNIC(bp);
3007         vnic = &bp->vnic_info[efilter->queue];
3008
3009         switch (filter_op) {
3010         case RTE_ETH_FILTER_ADD:
3011                 bnxt_match_and_validate_ether_filter(bp, efilter,
3012                                                         vnic0, vnic, &ret);
3013                 if (ret < 0)
3014                         return ret;
3015
3016                 bfilter = bnxt_get_unused_filter(bp);
3017                 if (bfilter == NULL) {
3018                         PMD_DRV_LOG(ERR,
3019                                 "Not enough resources for a new filter.\n");
3020                         return -ENOMEM;
3021                 }
3022                 bfilter->filter_type = HWRM_CFA_NTUPLE_FILTER;
3023                 memcpy(bfilter->l2_addr, efilter->mac_addr.addr_bytes,
3024                        RTE_ETHER_ADDR_LEN);
3025                 memcpy(bfilter->dst_macaddr, efilter->mac_addr.addr_bytes,
3026                        RTE_ETHER_ADDR_LEN);
3027                 bfilter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_MACADDR;
3028                 bfilter->ethertype = efilter->ether_type;
3029                 bfilter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
3030
3031                 filter1 = bnxt_get_l2_filter(bp, bfilter, vnic0);
3032                 if (filter1 == NULL) {
3033                         ret = -EINVAL;
3034                         goto cleanup;
3035                 }
3036                 bfilter->enables |=
3037                         HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID;
3038                 bfilter->fw_l2_filter_id = filter1->fw_l2_filter_id;
3039
3040                 bfilter->dst_id = vnic->fw_vnic_id;
3041
3042                 if (efilter->flags & RTE_ETHTYPE_FLAGS_DROP) {
3043                         bfilter->flags =
3044                                 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_DROP;
3045                 }
3046
3047                 ret = bnxt_hwrm_set_ntuple_filter(bp, bfilter->dst_id, bfilter);
3048                 if (ret)
3049                         goto cleanup;
3050                 STAILQ_INSERT_TAIL(&vnic->filter, bfilter, next);
3051                 break;
3052         case RTE_ETH_FILTER_DELETE:
3053                 filter1 = bnxt_match_and_validate_ether_filter(bp, efilter,
3054                                                         vnic0, vnic, &ret);
3055                 if (ret == -EEXIST) {
3056                         ret = bnxt_hwrm_clear_ntuple_filter(bp, filter1);
3057
3058                         STAILQ_REMOVE(&vnic->filter, filter1, bnxt_filter_info,
3059                                       next);
3060                         bnxt_free_filter(bp, filter1);
3061                 } else if (ret == 0) {
3062                         PMD_DRV_LOG(ERR, "No matching filter found\n");
3063                 }
3064                 break;
3065         default:
3066                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
3067                 ret = -EINVAL;
3068                 goto error;
3069         }
3070         return ret;
3071 cleanup:
3072         bnxt_free_filter(bp, bfilter);
3073 error:
3074         return ret;
3075 }
3076
3077 static inline int
3078 parse_ntuple_filter(struct bnxt *bp,
3079                     struct rte_eth_ntuple_filter *nfilter,
3080                     struct bnxt_filter_info *bfilter)
3081 {
3082         uint32_t en = 0;
3083
3084         if (nfilter->queue >= bp->rx_nr_rings) {
3085                 PMD_DRV_LOG(ERR, "Invalid queue %d\n", nfilter->queue);
3086                 return -EINVAL;
3087         }
3088
3089         switch (nfilter->dst_port_mask) {
3090         case UINT16_MAX:
3091                 bfilter->dst_port_mask = -1;
3092                 bfilter->dst_port = nfilter->dst_port;
3093                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT |
3094                         NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
3095                 break;
3096         default:
3097                 PMD_DRV_LOG(ERR, "invalid dst_port mask.");
3098                 return -EINVAL;
3099         }
3100
3101         bfilter->ip_addr_type = NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4;
3102         en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
3103
3104         switch (nfilter->proto_mask) {
3105         case UINT8_MAX:
3106                 if (nfilter->proto == 17) /* IPPROTO_UDP */
3107                         bfilter->ip_protocol = 17;
3108                 else if (nfilter->proto == 6) /* IPPROTO_TCP */
3109                         bfilter->ip_protocol = 6;
3110                 else
3111                         return -EINVAL;
3112                 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
3113                 break;
3114         default:
3115                 PMD_DRV_LOG(ERR, "invalid protocol mask.");
3116                 return -EINVAL;
3117         }
3118
3119         switch (nfilter->dst_ip_mask) {
3120         case UINT32_MAX:
3121                 bfilter->dst_ipaddr_mask[0] = -1;
3122                 bfilter->dst_ipaddr[0] = nfilter->dst_ip;
3123                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR |
3124                         NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
3125                 break;
3126         default:
3127                 PMD_DRV_LOG(ERR, "invalid dst_ip mask.");
3128                 return -EINVAL;
3129         }
3130
3131         switch (nfilter->src_ip_mask) {
3132         case UINT32_MAX:
3133                 bfilter->src_ipaddr_mask[0] = -1;
3134                 bfilter->src_ipaddr[0] = nfilter->src_ip;
3135                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR |
3136                         NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
3137                 break;
3138         default:
3139                 PMD_DRV_LOG(ERR, "invalid src_ip mask.");
3140                 return -EINVAL;
3141         }
3142
3143         switch (nfilter->src_port_mask) {
3144         case UINT16_MAX:
3145                 bfilter->src_port_mask = -1;
3146                 bfilter->src_port = nfilter->src_port;
3147                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT |
3148                         NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
3149                 break;
3150         default:
3151                 PMD_DRV_LOG(ERR, "invalid src_port mask.");
3152                 return -EINVAL;
3153         }
3154
3155         bfilter->enables = en;
3156         return 0;
3157 }
3158
3159 static struct bnxt_filter_info*
3160 bnxt_match_ntuple_filter(struct bnxt *bp,
3161                          struct bnxt_filter_info *bfilter,
3162                          struct bnxt_vnic_info **mvnic)
3163 {
3164         struct bnxt_filter_info *mfilter = NULL;
3165         int i;
3166
3167         for (i = bp->nr_vnics - 1; i >= 0; i--) {
3168                 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
3169                 STAILQ_FOREACH(mfilter, &vnic->filter, next) {
3170                         if (bfilter->src_ipaddr[0] == mfilter->src_ipaddr[0] &&
3171                             bfilter->src_ipaddr_mask[0] ==
3172                             mfilter->src_ipaddr_mask[0] &&
3173                             bfilter->src_port == mfilter->src_port &&
3174                             bfilter->src_port_mask == mfilter->src_port_mask &&
3175                             bfilter->dst_ipaddr[0] == mfilter->dst_ipaddr[0] &&
3176                             bfilter->dst_ipaddr_mask[0] ==
3177                             mfilter->dst_ipaddr_mask[0] &&
3178                             bfilter->dst_port == mfilter->dst_port &&
3179                             bfilter->dst_port_mask == mfilter->dst_port_mask &&
3180                             bfilter->flags == mfilter->flags &&
3181                             bfilter->enables == mfilter->enables) {
3182                                 if (mvnic)
3183                                         *mvnic = vnic;
3184                                 return mfilter;
3185                         }
3186                 }
3187         }
3188         return NULL;
3189 }
3190
3191 static int
3192 bnxt_cfg_ntuple_filter(struct bnxt *bp,
3193                        struct rte_eth_ntuple_filter *nfilter,
3194                        enum rte_filter_op filter_op)
3195 {
3196         struct bnxt_filter_info *bfilter, *mfilter, *filter1;
3197         struct bnxt_vnic_info *vnic, *vnic0, *mvnic;
3198         int ret;
3199
3200         if (nfilter->flags != RTE_5TUPLE_FLAGS) {
3201                 PMD_DRV_LOG(ERR, "only 5tuple is supported.");
3202                 return -EINVAL;
3203         }
3204
3205         if (nfilter->flags & RTE_NTUPLE_FLAGS_TCP_FLAG) {
3206                 PMD_DRV_LOG(ERR, "Ntuple filter: TCP flags not supported\n");
3207                 return -EINVAL;
3208         }
3209
3210         bfilter = bnxt_get_unused_filter(bp);
3211         if (bfilter == NULL) {
3212                 PMD_DRV_LOG(ERR,
3213                         "Not enough resources for a new filter.\n");
3214                 return -ENOMEM;
3215         }
3216         ret = parse_ntuple_filter(bp, nfilter, bfilter);
3217         if (ret < 0)
3218                 goto free_filter;
3219
3220         vnic = &bp->vnic_info[nfilter->queue];
3221         vnic0 = BNXT_GET_DEFAULT_VNIC(bp);
3222         filter1 = STAILQ_FIRST(&vnic0->filter);
3223         if (filter1 == NULL) {
3224                 ret = -EINVAL;
3225                 goto free_filter;
3226         }
3227
3228         bfilter->dst_id = vnic->fw_vnic_id;
3229         bfilter->fw_l2_filter_id = filter1->fw_l2_filter_id;
3230         bfilter->enables |=
3231                 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID;
3232         bfilter->ethertype = 0x800;
3233         bfilter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
3234
3235         mfilter = bnxt_match_ntuple_filter(bp, bfilter, &mvnic);
3236
3237         if (mfilter != NULL && filter_op == RTE_ETH_FILTER_ADD &&
3238             bfilter->dst_id == mfilter->dst_id) {
3239                 PMD_DRV_LOG(ERR, "filter exists.\n");
3240                 ret = -EEXIST;
3241                 goto free_filter;
3242         } else if (mfilter != NULL && filter_op == RTE_ETH_FILTER_ADD &&
3243                    bfilter->dst_id != mfilter->dst_id) {
3244                 mfilter->dst_id = vnic->fw_vnic_id;
3245                 ret = bnxt_hwrm_set_ntuple_filter(bp, mfilter->dst_id, mfilter);
3246                 STAILQ_REMOVE(&mvnic->filter, mfilter, bnxt_filter_info, next);
3247                 STAILQ_INSERT_TAIL(&vnic->filter, mfilter, next);
3248                 PMD_DRV_LOG(ERR, "filter with matching pattern exists.\n");
3249                 PMD_DRV_LOG(ERR, " Updated it to the new destination queue\n");
3250                 goto free_filter;
3251         }
3252         if (mfilter == NULL && filter_op == RTE_ETH_FILTER_DELETE) {
3253                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
3254                 ret = -ENOENT;
3255                 goto free_filter;
3256         }
3257
3258         if (filter_op == RTE_ETH_FILTER_ADD) {
3259                 bfilter->filter_type = HWRM_CFA_NTUPLE_FILTER;
3260                 ret = bnxt_hwrm_set_ntuple_filter(bp, bfilter->dst_id, bfilter);
3261                 if (ret)
3262                         goto free_filter;
3263                 STAILQ_INSERT_TAIL(&vnic->filter, bfilter, next);
3264         } else {
3265                 if (mfilter == NULL) {
3266                         /* This should not happen. But for Coverity! */
3267                         ret = -ENOENT;
3268                         goto free_filter;
3269                 }
3270                 ret = bnxt_hwrm_clear_ntuple_filter(bp, mfilter);
3271
3272                 STAILQ_REMOVE(&vnic->filter, mfilter, bnxt_filter_info, next);
3273                 bnxt_free_filter(bp, mfilter);
3274                 bnxt_free_filter(bp, bfilter);
3275         }
3276
3277         return 0;
3278 free_filter:
3279         bnxt_free_filter(bp, bfilter);
3280         return ret;
3281 }
3282
3283 static int
3284 bnxt_ntuple_filter(struct rte_eth_dev *dev,
3285                         enum rte_filter_op filter_op,
3286                         void *arg)
3287 {
3288         struct bnxt *bp = dev->data->dev_private;
3289         int ret;
3290
3291         if (filter_op == RTE_ETH_FILTER_NOP)
3292                 return 0;
3293
3294         if (arg == NULL) {
3295                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
3296                             filter_op);
3297                 return -EINVAL;
3298         }
3299
3300         switch (filter_op) {
3301         case RTE_ETH_FILTER_ADD:
3302                 ret = bnxt_cfg_ntuple_filter(bp,
3303                         (struct rte_eth_ntuple_filter *)arg,
3304                         filter_op);
3305                 break;
3306         case RTE_ETH_FILTER_DELETE:
3307                 ret = bnxt_cfg_ntuple_filter(bp,
3308                         (struct rte_eth_ntuple_filter *)arg,
3309                         filter_op);
3310                 break;
3311         default:
3312                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
3313                 ret = -EINVAL;
3314                 break;
3315         }
3316         return ret;
3317 }
3318
3319 static int
3320 bnxt_parse_fdir_filter(struct bnxt *bp,
3321                        struct rte_eth_fdir_filter *fdir,
3322                        struct bnxt_filter_info *filter)
3323 {
3324         enum rte_fdir_mode fdir_mode =
3325                 bp->eth_dev->data->dev_conf.fdir_conf.mode;
3326         struct bnxt_vnic_info *vnic0, *vnic;
3327         struct bnxt_filter_info *filter1;
3328         uint32_t en = 0;
3329         int i;
3330
3331         if (fdir_mode == RTE_FDIR_MODE_PERFECT_TUNNEL)
3332                 return -EINVAL;
3333
3334         filter->l2_ovlan = fdir->input.flow_ext.vlan_tci;
3335         en |= EM_FLOW_ALLOC_INPUT_EN_OVLAN_VID;
3336
3337         switch (fdir->input.flow_type) {
3338         case RTE_ETH_FLOW_IPV4:
3339         case RTE_ETH_FLOW_NONFRAG_IPV4_OTHER:
3340                 /* FALLTHROUGH */
3341                 filter->src_ipaddr[0] = fdir->input.flow.ip4_flow.src_ip;
3342                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
3343                 filter->dst_ipaddr[0] = fdir->input.flow.ip4_flow.dst_ip;
3344                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
3345                 filter->ip_protocol = fdir->input.flow.ip4_flow.proto;
3346                 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
3347                 filter->ip_addr_type =
3348                         NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4;
3349                 filter->src_ipaddr_mask[0] = 0xffffffff;
3350                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
3351                 filter->dst_ipaddr_mask[0] = 0xffffffff;
3352                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
3353                 filter->ethertype = 0x800;
3354                 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
3355                 break;
3356         case RTE_ETH_FLOW_NONFRAG_IPV4_TCP:
3357                 filter->src_port = fdir->input.flow.tcp4_flow.src_port;
3358                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT;
3359                 filter->dst_port = fdir->input.flow.tcp4_flow.dst_port;
3360                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT;
3361                 filter->dst_port_mask = 0xffff;
3362                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
3363                 filter->src_port_mask = 0xffff;
3364                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
3365                 filter->src_ipaddr[0] = fdir->input.flow.tcp4_flow.ip.src_ip;
3366                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
3367                 filter->dst_ipaddr[0] = fdir->input.flow.tcp4_flow.ip.dst_ip;
3368                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
3369                 filter->ip_protocol = 6;
3370                 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
3371                 filter->ip_addr_type =
3372                         NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4;
3373                 filter->src_ipaddr_mask[0] = 0xffffffff;
3374                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
3375                 filter->dst_ipaddr_mask[0] = 0xffffffff;
3376                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
3377                 filter->ethertype = 0x800;
3378                 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
3379                 break;
3380         case RTE_ETH_FLOW_NONFRAG_IPV4_UDP:
3381                 filter->src_port = fdir->input.flow.udp4_flow.src_port;
3382                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT;
3383                 filter->dst_port = fdir->input.flow.udp4_flow.dst_port;
3384                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT;
3385                 filter->dst_port_mask = 0xffff;
3386                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
3387                 filter->src_port_mask = 0xffff;
3388                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
3389                 filter->src_ipaddr[0] = fdir->input.flow.udp4_flow.ip.src_ip;
3390                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
3391                 filter->dst_ipaddr[0] = fdir->input.flow.udp4_flow.ip.dst_ip;
3392                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
3393                 filter->ip_protocol = 17;
3394                 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
3395                 filter->ip_addr_type =
3396                         NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4;
3397                 filter->src_ipaddr_mask[0] = 0xffffffff;
3398                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
3399                 filter->dst_ipaddr_mask[0] = 0xffffffff;
3400                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
3401                 filter->ethertype = 0x800;
3402                 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
3403                 break;
3404         case RTE_ETH_FLOW_IPV6:
3405         case RTE_ETH_FLOW_NONFRAG_IPV6_OTHER:
3406                 /* FALLTHROUGH */
3407                 filter->ip_addr_type =
3408                         NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV6;
3409                 filter->ip_protocol = fdir->input.flow.ipv6_flow.proto;
3410                 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
3411                 rte_memcpy(filter->src_ipaddr,
3412                            fdir->input.flow.ipv6_flow.src_ip, 16);
3413                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
3414                 rte_memcpy(filter->dst_ipaddr,
3415                            fdir->input.flow.ipv6_flow.dst_ip, 16);
3416                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
3417                 memset(filter->dst_ipaddr_mask, 0xff, 16);
3418                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
3419                 memset(filter->src_ipaddr_mask, 0xff, 16);
3420                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
3421                 filter->ethertype = 0x86dd;
3422                 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
3423                 break;
3424         case RTE_ETH_FLOW_NONFRAG_IPV6_TCP:
3425                 filter->src_port = fdir->input.flow.tcp6_flow.src_port;
3426                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT;
3427                 filter->dst_port = fdir->input.flow.tcp6_flow.dst_port;
3428                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT;
3429                 filter->dst_port_mask = 0xffff;
3430                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
3431                 filter->src_port_mask = 0xffff;
3432                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
3433                 filter->ip_addr_type =
3434                         NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV6;
3435                 filter->ip_protocol = fdir->input.flow.tcp6_flow.ip.proto;
3436                 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
3437                 rte_memcpy(filter->src_ipaddr,
3438                            fdir->input.flow.tcp6_flow.ip.src_ip, 16);
3439                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
3440                 rte_memcpy(filter->dst_ipaddr,
3441                            fdir->input.flow.tcp6_flow.ip.dst_ip, 16);
3442                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
3443                 memset(filter->dst_ipaddr_mask, 0xff, 16);
3444                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
3445                 memset(filter->src_ipaddr_mask, 0xff, 16);
3446                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
3447                 filter->ethertype = 0x86dd;
3448                 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
3449                 break;
3450         case RTE_ETH_FLOW_NONFRAG_IPV6_UDP:
3451                 filter->src_port = fdir->input.flow.udp6_flow.src_port;
3452                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT;
3453                 filter->dst_port = fdir->input.flow.udp6_flow.dst_port;
3454                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT;
3455                 filter->dst_port_mask = 0xffff;
3456                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
3457                 filter->src_port_mask = 0xffff;
3458                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
3459                 filter->ip_addr_type =
3460                         NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV6;
3461                 filter->ip_protocol = fdir->input.flow.udp6_flow.ip.proto;
3462                 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
3463                 rte_memcpy(filter->src_ipaddr,
3464                            fdir->input.flow.udp6_flow.ip.src_ip, 16);
3465                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
3466                 rte_memcpy(filter->dst_ipaddr,
3467                            fdir->input.flow.udp6_flow.ip.dst_ip, 16);
3468                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
3469                 memset(filter->dst_ipaddr_mask, 0xff, 16);
3470                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
3471                 memset(filter->src_ipaddr_mask, 0xff, 16);
3472                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
3473                 filter->ethertype = 0x86dd;
3474                 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
3475                 break;
3476         case RTE_ETH_FLOW_L2_PAYLOAD:
3477                 filter->ethertype = fdir->input.flow.l2_flow.ether_type;
3478                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
3479                 break;
3480         case RTE_ETH_FLOW_VXLAN:
3481                 if (fdir->action.behavior == RTE_ETH_FDIR_REJECT)
3482                         return -EINVAL;
3483                 filter->vni = fdir->input.flow.tunnel_flow.tunnel_id;
3484                 filter->tunnel_type =
3485                         CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN;
3486                 en |= HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_TUNNEL_TYPE;
3487                 break;
3488         case RTE_ETH_FLOW_NVGRE:
3489                 if (fdir->action.behavior == RTE_ETH_FDIR_REJECT)
3490                         return -EINVAL;
3491                 filter->vni = fdir->input.flow.tunnel_flow.tunnel_id;
3492                 filter->tunnel_type =
3493                         CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_NVGRE;
3494                 en |= HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_TUNNEL_TYPE;
3495                 break;
3496         case RTE_ETH_FLOW_UNKNOWN:
3497         case RTE_ETH_FLOW_RAW:
3498         case RTE_ETH_FLOW_FRAG_IPV4:
3499         case RTE_ETH_FLOW_NONFRAG_IPV4_SCTP:
3500         case RTE_ETH_FLOW_FRAG_IPV6:
3501         case RTE_ETH_FLOW_NONFRAG_IPV6_SCTP:
3502         case RTE_ETH_FLOW_IPV6_EX:
3503         case RTE_ETH_FLOW_IPV6_TCP_EX:
3504         case RTE_ETH_FLOW_IPV6_UDP_EX:
3505         case RTE_ETH_FLOW_GENEVE:
3506                 /* FALLTHROUGH */
3507         default:
3508                 return -EINVAL;
3509         }
3510
3511         vnic0 = BNXT_GET_DEFAULT_VNIC(bp);
3512         vnic = &bp->vnic_info[fdir->action.rx_queue];
3513         if (vnic == NULL) {
3514                 PMD_DRV_LOG(ERR, "Invalid queue %d\n", fdir->action.rx_queue);
3515                 return -EINVAL;
3516         }
3517
3518         if (fdir_mode == RTE_FDIR_MODE_PERFECT_MAC_VLAN) {
3519                 rte_memcpy(filter->dst_macaddr,
3520                         fdir->input.flow.mac_vlan_flow.mac_addr.addr_bytes, 6);
3521                         en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_MACADDR;
3522         }
3523
3524         if (fdir->action.behavior == RTE_ETH_FDIR_REJECT) {
3525                 filter->flags = HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_DROP;
3526                 filter1 = STAILQ_FIRST(&vnic0->filter);
3527                 //filter1 = bnxt_get_l2_filter(bp, filter, vnic0);
3528         } else {
3529                 filter->dst_id = vnic->fw_vnic_id;
3530                 for (i = 0; i < RTE_ETHER_ADDR_LEN; i++)
3531                         if (filter->dst_macaddr[i] == 0x00)
3532                                 filter1 = STAILQ_FIRST(&vnic0->filter);
3533                         else
3534                                 filter1 = bnxt_get_l2_filter(bp, filter, vnic);
3535         }
3536
3537         if (filter1 == NULL)
3538                 return -EINVAL;
3539
3540         en |= HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID;
3541         filter->fw_l2_filter_id = filter1->fw_l2_filter_id;
3542
3543         filter->enables = en;
3544
3545         return 0;
3546 }
3547
3548 static struct bnxt_filter_info *
3549 bnxt_match_fdir(struct bnxt *bp, struct bnxt_filter_info *nf,
3550                 struct bnxt_vnic_info **mvnic)
3551 {
3552         struct bnxt_filter_info *mf = NULL;
3553         int i;
3554
3555         for (i = bp->nr_vnics - 1; i >= 0; i--) {
3556                 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
3557
3558                 STAILQ_FOREACH(mf, &vnic->filter, next) {
3559                         if (mf->filter_type == nf->filter_type &&
3560                             mf->flags == nf->flags &&
3561                             mf->src_port == nf->src_port &&
3562                             mf->src_port_mask == nf->src_port_mask &&
3563                             mf->dst_port == nf->dst_port &&
3564                             mf->dst_port_mask == nf->dst_port_mask &&
3565                             mf->ip_protocol == nf->ip_protocol &&
3566                             mf->ip_addr_type == nf->ip_addr_type &&
3567                             mf->ethertype == nf->ethertype &&
3568                             mf->vni == nf->vni &&
3569                             mf->tunnel_type == nf->tunnel_type &&
3570                             mf->l2_ovlan == nf->l2_ovlan &&
3571                             mf->l2_ovlan_mask == nf->l2_ovlan_mask &&
3572                             mf->l2_ivlan == nf->l2_ivlan &&
3573                             mf->l2_ivlan_mask == nf->l2_ivlan_mask &&
3574                             !memcmp(mf->l2_addr, nf->l2_addr,
3575                                     RTE_ETHER_ADDR_LEN) &&
3576                             !memcmp(mf->l2_addr_mask, nf->l2_addr_mask,
3577                                     RTE_ETHER_ADDR_LEN) &&
3578                             !memcmp(mf->src_macaddr, nf->src_macaddr,
3579                                     RTE_ETHER_ADDR_LEN) &&
3580                             !memcmp(mf->dst_macaddr, nf->dst_macaddr,
3581                                     RTE_ETHER_ADDR_LEN) &&
3582                             !memcmp(mf->src_ipaddr, nf->src_ipaddr,
3583                                     sizeof(nf->src_ipaddr)) &&
3584                             !memcmp(mf->src_ipaddr_mask, nf->src_ipaddr_mask,
3585                                     sizeof(nf->src_ipaddr_mask)) &&
3586                             !memcmp(mf->dst_ipaddr, nf->dst_ipaddr,
3587                                     sizeof(nf->dst_ipaddr)) &&
3588                             !memcmp(mf->dst_ipaddr_mask, nf->dst_ipaddr_mask,
3589                                     sizeof(nf->dst_ipaddr_mask))) {
3590                                 if (mvnic)
3591                                         *mvnic = vnic;
3592                                 return mf;
3593                         }
3594                 }
3595         }
3596         return NULL;
3597 }
3598
3599 static int
3600 bnxt_fdir_filter(struct rte_eth_dev *dev,
3601                  enum rte_filter_op filter_op,
3602                  void *arg)
3603 {
3604         struct bnxt *bp = dev->data->dev_private;
3605         struct rte_eth_fdir_filter *fdir  = (struct rte_eth_fdir_filter *)arg;
3606         struct bnxt_filter_info *filter, *match;
3607         struct bnxt_vnic_info *vnic, *mvnic;
3608         int ret = 0, i;
3609
3610         if (filter_op == RTE_ETH_FILTER_NOP)
3611                 return 0;
3612
3613         if (arg == NULL && filter_op != RTE_ETH_FILTER_FLUSH)
3614                 return -EINVAL;
3615
3616         switch (filter_op) {
3617         case RTE_ETH_FILTER_ADD:
3618         case RTE_ETH_FILTER_DELETE:
3619                 /* FALLTHROUGH */
3620                 filter = bnxt_get_unused_filter(bp);
3621                 if (filter == NULL) {
3622                         PMD_DRV_LOG(ERR,
3623                                 "Not enough resources for a new flow.\n");
3624                         return -ENOMEM;
3625                 }
3626
3627                 ret = bnxt_parse_fdir_filter(bp, fdir, filter);
3628                 if (ret != 0)
3629                         goto free_filter;
3630                 filter->filter_type = HWRM_CFA_NTUPLE_FILTER;
3631
3632                 if (fdir->action.behavior == RTE_ETH_FDIR_REJECT)
3633                         vnic = &bp->vnic_info[0];
3634                 else
3635                         vnic = &bp->vnic_info[fdir->action.rx_queue];
3636
3637                 match = bnxt_match_fdir(bp, filter, &mvnic);
3638                 if (match != NULL && filter_op == RTE_ETH_FILTER_ADD) {
3639                         if (match->dst_id == vnic->fw_vnic_id) {
3640                                 PMD_DRV_LOG(ERR, "Flow already exists.\n");
3641                                 ret = -EEXIST;
3642                                 goto free_filter;
3643                         } else {
3644                                 match->dst_id = vnic->fw_vnic_id;
3645                                 ret = bnxt_hwrm_set_ntuple_filter(bp,
3646                                                                   match->dst_id,
3647                                                                   match);
3648                                 STAILQ_REMOVE(&mvnic->filter, match,
3649                                               bnxt_filter_info, next);
3650                                 STAILQ_INSERT_TAIL(&vnic->filter, match, next);
3651                                 PMD_DRV_LOG(ERR,
3652                                         "Filter with matching pattern exist\n");
3653                                 PMD_DRV_LOG(ERR,
3654                                         "Updated it to new destination q\n");
3655                                 goto free_filter;
3656                         }
3657                 }
3658                 if (match == NULL && filter_op == RTE_ETH_FILTER_DELETE) {
3659                         PMD_DRV_LOG(ERR, "Flow does not exist.\n");
3660                         ret = -ENOENT;
3661                         goto free_filter;
3662                 }
3663
3664                 if (filter_op == RTE_ETH_FILTER_ADD) {
3665                         ret = bnxt_hwrm_set_ntuple_filter(bp,
3666                                                           filter->dst_id,
3667                                                           filter);
3668                         if (ret)
3669                                 goto free_filter;
3670                         STAILQ_INSERT_TAIL(&vnic->filter, filter, next);
3671                 } else {
3672                         ret = bnxt_hwrm_clear_ntuple_filter(bp, match);
3673                         STAILQ_REMOVE(&vnic->filter, match,
3674                                       bnxt_filter_info, next);
3675                         bnxt_free_filter(bp, match);
3676                         bnxt_free_filter(bp, filter);
3677                 }
3678                 break;
3679         case RTE_ETH_FILTER_FLUSH:
3680                 for (i = bp->nr_vnics - 1; i >= 0; i--) {
3681                         struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
3682
3683                         STAILQ_FOREACH(filter, &vnic->filter, next) {
3684                                 if (filter->filter_type ==
3685                                     HWRM_CFA_NTUPLE_FILTER) {
3686                                         ret =
3687                                         bnxt_hwrm_clear_ntuple_filter(bp,
3688                                                                       filter);
3689                                         STAILQ_REMOVE(&vnic->filter, filter,
3690                                                       bnxt_filter_info, next);
3691                                 }
3692                         }
3693                 }
3694                 return ret;
3695         case RTE_ETH_FILTER_UPDATE:
3696         case RTE_ETH_FILTER_STATS:
3697         case RTE_ETH_FILTER_INFO:
3698                 PMD_DRV_LOG(ERR, "operation %u not implemented", filter_op);
3699                 break;
3700         default:
3701                 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
3702                 ret = -EINVAL;
3703                 break;
3704         }
3705         return ret;
3706
3707 free_filter:
3708         bnxt_free_filter(bp, filter);
3709         return ret;
3710 }
3711
3712 int
3713 bnxt_filter_ctrl_op(struct rte_eth_dev *dev,
3714                     enum rte_filter_type filter_type,
3715                     enum rte_filter_op filter_op, void *arg)
3716 {
3717         struct bnxt *bp = dev->data->dev_private;
3718         int ret = 0;
3719
3720         if (BNXT_ETH_DEV_IS_REPRESENTOR(dev)) {
3721                 struct bnxt_vf_representor *vfr = dev->data->dev_private;
3722                 bp = vfr->parent_dev->data->dev_private;
3723         }
3724
3725         ret = is_bnxt_in_error(bp);
3726         if (ret)
3727                 return ret;
3728
3729         switch (filter_type) {
3730         case RTE_ETH_FILTER_TUNNEL:
3731                 PMD_DRV_LOG(ERR,
3732                         "filter type: %d: To be implemented\n", filter_type);
3733                 break;
3734         case RTE_ETH_FILTER_FDIR:
3735                 ret = bnxt_fdir_filter(dev, filter_op, arg);
3736                 break;
3737         case RTE_ETH_FILTER_NTUPLE:
3738                 ret = bnxt_ntuple_filter(dev, filter_op, arg);
3739                 break;
3740         case RTE_ETH_FILTER_ETHERTYPE:
3741                 ret = bnxt_ethertype_filter(dev, filter_op, arg);
3742                 break;
3743         case RTE_ETH_FILTER_GENERIC:
3744                 if (filter_op != RTE_ETH_FILTER_GET)
3745                         return -EINVAL;
3746                 if (BNXT_TRUFLOW_EN(bp))
3747                         *(const void **)arg = &bnxt_ulp_rte_flow_ops;
3748                 else
3749                         *(const void **)arg = &bnxt_flow_ops;
3750                 break;
3751         default:
3752                 PMD_DRV_LOG(ERR,
3753                         "Filter type (%d) not supported", filter_type);
3754                 ret = -EINVAL;
3755                 break;
3756         }
3757         return ret;
3758 }
3759
3760 static const uint32_t *
3761 bnxt_dev_supported_ptypes_get_op(struct rte_eth_dev *dev)
3762 {
3763         static const uint32_t ptypes[] = {
3764                 RTE_PTYPE_L2_ETHER_VLAN,
3765                 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN,
3766                 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN,
3767                 RTE_PTYPE_L4_ICMP,
3768                 RTE_PTYPE_L4_TCP,
3769                 RTE_PTYPE_L4_UDP,
3770                 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN,
3771                 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN,
3772                 RTE_PTYPE_INNER_L4_ICMP,
3773                 RTE_PTYPE_INNER_L4_TCP,
3774                 RTE_PTYPE_INNER_L4_UDP,
3775                 RTE_PTYPE_UNKNOWN
3776         };
3777
3778         if (!dev->rx_pkt_burst)
3779                 return NULL;
3780
3781         return ptypes;
3782 }
3783
3784 static int bnxt_map_regs(struct bnxt *bp, uint32_t *reg_arr, int count,
3785                          int reg_win)
3786 {
3787         uint32_t reg_base = *reg_arr & 0xfffff000;
3788         uint32_t win_off;
3789         int i;
3790
3791         for (i = 0; i < count; i++) {
3792                 if ((reg_arr[i] & 0xfffff000) != reg_base)
3793                         return -ERANGE;
3794         }
3795         win_off = BNXT_GRCPF_REG_WINDOW_BASE_OUT + (reg_win - 1) * 4;
3796         rte_write32(reg_base, (uint8_t *)bp->bar0 + win_off);
3797         return 0;
3798 }
3799
3800 static int bnxt_map_ptp_regs(struct bnxt *bp)
3801 {
3802         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3803         uint32_t *reg_arr;
3804         int rc, i;
3805
3806         reg_arr = ptp->rx_regs;
3807         rc = bnxt_map_regs(bp, reg_arr, BNXT_PTP_RX_REGS, 5);
3808         if (rc)
3809                 return rc;
3810
3811         reg_arr = ptp->tx_regs;
3812         rc = bnxt_map_regs(bp, reg_arr, BNXT_PTP_TX_REGS, 6);
3813         if (rc)
3814                 return rc;
3815
3816         for (i = 0; i < BNXT_PTP_RX_REGS; i++)
3817                 ptp->rx_mapped_regs[i] = 0x5000 + (ptp->rx_regs[i] & 0xfff);
3818
3819         for (i = 0; i < BNXT_PTP_TX_REGS; i++)
3820                 ptp->tx_mapped_regs[i] = 0x6000 + (ptp->tx_regs[i] & 0xfff);
3821
3822         return 0;
3823 }
3824
3825 static void bnxt_unmap_ptp_regs(struct bnxt *bp)
3826 {
3827         rte_write32(0, (uint8_t *)bp->bar0 +
3828                          BNXT_GRCPF_REG_WINDOW_BASE_OUT + 16);
3829         rte_write32(0, (uint8_t *)bp->bar0 +
3830                          BNXT_GRCPF_REG_WINDOW_BASE_OUT + 20);
3831 }
3832
3833 static uint64_t bnxt_cc_read(struct bnxt *bp)
3834 {
3835         uint64_t ns;
3836
3837         ns = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3838                               BNXT_GRCPF_REG_SYNC_TIME));
3839         ns |= (uint64_t)(rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3840                                           BNXT_GRCPF_REG_SYNC_TIME + 4))) << 32;
3841         return ns;
3842 }
3843
3844 static int bnxt_get_tx_ts(struct bnxt *bp, uint64_t *ts)
3845 {
3846         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3847         uint32_t fifo;
3848
3849         fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3850                                 ptp->tx_mapped_regs[BNXT_PTP_TX_FIFO]));
3851         if (fifo & BNXT_PTP_TX_FIFO_EMPTY)
3852                 return -EAGAIN;
3853
3854         fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3855                                 ptp->tx_mapped_regs[BNXT_PTP_TX_FIFO]));
3856         *ts = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3857                                 ptp->tx_mapped_regs[BNXT_PTP_TX_TS_L]));
3858         *ts |= (uint64_t)rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3859                                 ptp->tx_mapped_regs[BNXT_PTP_TX_TS_H])) << 32;
3860
3861         return 0;
3862 }
3863
3864 static int bnxt_get_rx_ts(struct bnxt *bp, uint64_t *ts)
3865 {
3866         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3867         struct bnxt_pf_info *pf = bp->pf;
3868         uint16_t port_id;
3869         uint32_t fifo;
3870
3871         if (!ptp)
3872                 return -ENODEV;
3873
3874         fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3875                                 ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO]));
3876         if (!(fifo & BNXT_PTP_RX_FIFO_PENDING))
3877                 return -EAGAIN;
3878
3879         port_id = pf->port_id;
3880         rte_write32(1 << port_id, (uint8_t *)bp->bar0 +
3881                ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO_ADV]);
3882
3883         fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3884                                    ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO]));
3885         if (fifo & BNXT_PTP_RX_FIFO_PENDING) {
3886 /*              bnxt_clr_rx_ts(bp);       TBD  */
3887                 return -EBUSY;
3888         }
3889
3890         *ts = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3891                                 ptp->rx_mapped_regs[BNXT_PTP_RX_TS_L]));
3892         *ts |= (uint64_t)rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3893                                 ptp->rx_mapped_regs[BNXT_PTP_RX_TS_H])) << 32;
3894
3895         return 0;
3896 }
3897
3898 static int
3899 bnxt_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
3900 {
3901         uint64_t ns;
3902         struct bnxt *bp = dev->data->dev_private;
3903         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3904
3905         if (!ptp)
3906                 return 0;
3907
3908         ns = rte_timespec_to_ns(ts);
3909         /* Set the timecounters to a new value. */
3910         ptp->tc.nsec = ns;
3911
3912         return 0;
3913 }
3914
3915 static int
3916 bnxt_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
3917 {
3918         struct bnxt *bp = dev->data->dev_private;
3919         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3920         uint64_t ns, systime_cycles = 0;
3921         int rc = 0;
3922
3923         if (!ptp)
3924                 return 0;
3925
3926         if (BNXT_CHIP_THOR(bp))
3927                 rc = bnxt_hwrm_port_ts_query(bp, BNXT_PTP_FLAGS_CURRENT_TIME,
3928                                              &systime_cycles);
3929         else
3930                 systime_cycles = bnxt_cc_read(bp);
3931
3932         ns = rte_timecounter_update(&ptp->tc, systime_cycles);
3933         *ts = rte_ns_to_timespec(ns);
3934
3935         return rc;
3936 }
3937 static int
3938 bnxt_timesync_enable(struct rte_eth_dev *dev)
3939 {
3940         struct bnxt *bp = dev->data->dev_private;
3941         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3942         uint32_t shift = 0;
3943         int rc;
3944
3945         if (!ptp)
3946                 return 0;
3947
3948         ptp->rx_filter = 1;
3949         ptp->tx_tstamp_en = 1;
3950         ptp->rxctl = BNXT_PTP_MSG_EVENTS;
3951
3952         rc = bnxt_hwrm_ptp_cfg(bp);
3953         if (rc)
3954                 return rc;
3955
3956         memset(&ptp->tc, 0, sizeof(struct rte_timecounter));
3957         memset(&ptp->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
3958         memset(&ptp->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
3959
3960         ptp->tc.cc_mask = BNXT_CYCLECOUNTER_MASK;
3961         ptp->tc.cc_shift = shift;
3962         ptp->tc.nsec_mask = (1ULL << shift) - 1;
3963
3964         ptp->rx_tstamp_tc.cc_mask = BNXT_CYCLECOUNTER_MASK;
3965         ptp->rx_tstamp_tc.cc_shift = shift;
3966         ptp->rx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
3967
3968         ptp->tx_tstamp_tc.cc_mask = BNXT_CYCLECOUNTER_MASK;
3969         ptp->tx_tstamp_tc.cc_shift = shift;
3970         ptp->tx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
3971
3972         if (!BNXT_CHIP_THOR(bp))
3973                 bnxt_map_ptp_regs(bp);
3974
3975         return 0;
3976 }
3977
3978 static int
3979 bnxt_timesync_disable(struct rte_eth_dev *dev)
3980 {
3981         struct bnxt *bp = dev->data->dev_private;
3982         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3983
3984         if (!ptp)
3985                 return 0;
3986
3987         ptp->rx_filter = 0;
3988         ptp->tx_tstamp_en = 0;
3989         ptp->rxctl = 0;
3990
3991         bnxt_hwrm_ptp_cfg(bp);
3992
3993         if (!BNXT_CHIP_THOR(bp))
3994                 bnxt_unmap_ptp_regs(bp);
3995
3996         return 0;
3997 }
3998
3999 static int
4000 bnxt_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
4001                                  struct timespec *timestamp,
4002                                  uint32_t flags __rte_unused)
4003 {
4004         struct bnxt *bp = dev->data->dev_private;
4005         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
4006         uint64_t rx_tstamp_cycles = 0;
4007         uint64_t ns;
4008
4009         if (!ptp)
4010                 return 0;
4011
4012         if (BNXT_CHIP_THOR(bp))
4013                 rx_tstamp_cycles = ptp->rx_timestamp;
4014         else
4015                 bnxt_get_rx_ts(bp, &rx_tstamp_cycles);
4016
4017         ns = rte_timecounter_update(&ptp->rx_tstamp_tc, rx_tstamp_cycles);
4018         *timestamp = rte_ns_to_timespec(ns);
4019         return  0;
4020 }
4021
4022 static int
4023 bnxt_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
4024                                  struct timespec *timestamp)
4025 {
4026         struct bnxt *bp = dev->data->dev_private;
4027         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
4028         uint64_t tx_tstamp_cycles = 0;
4029         uint64_t ns;
4030         int rc = 0;
4031
4032         if (!ptp)
4033                 return 0;
4034
4035         if (BNXT_CHIP_THOR(bp))
4036                 rc = bnxt_hwrm_port_ts_query(bp, BNXT_PTP_FLAGS_PATH_TX,
4037                                              &tx_tstamp_cycles);
4038         else
4039                 rc = bnxt_get_tx_ts(bp, &tx_tstamp_cycles);
4040
4041         ns = rte_timecounter_update(&ptp->tx_tstamp_tc, tx_tstamp_cycles);
4042         *timestamp = rte_ns_to_timespec(ns);
4043
4044         return rc;
4045 }
4046
4047 static int
4048 bnxt_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
4049 {
4050         struct bnxt *bp = dev->data->dev_private;
4051         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
4052
4053         if (!ptp)
4054                 return 0;
4055
4056         ptp->tc.nsec += delta;
4057
4058         return 0;
4059 }
4060
4061 static int
4062 bnxt_get_eeprom_length_op(struct rte_eth_dev *dev)
4063 {
4064         struct bnxt *bp = dev->data->dev_private;
4065         int rc;
4066         uint32_t dir_entries;
4067         uint32_t entry_length;
4068
4069         rc = is_bnxt_in_error(bp);
4070         if (rc)
4071                 return rc;
4072
4073         PMD_DRV_LOG(INFO, PCI_PRI_FMT "\n",
4074                     bp->pdev->addr.domain, bp->pdev->addr.bus,
4075                     bp->pdev->addr.devid, bp->pdev->addr.function);
4076
4077         rc = bnxt_hwrm_nvm_get_dir_info(bp, &dir_entries, &entry_length);
4078         if (rc != 0)
4079                 return rc;
4080
4081         return dir_entries * entry_length;
4082 }
4083
4084 static int
4085 bnxt_get_eeprom_op(struct rte_eth_dev *dev,
4086                 struct rte_dev_eeprom_info *in_eeprom)
4087 {
4088         struct bnxt *bp = dev->data->dev_private;
4089         uint32_t index;
4090         uint32_t offset;
4091         int rc;
4092
4093         rc = is_bnxt_in_error(bp);
4094         if (rc)
4095                 return rc;
4096
4097         PMD_DRV_LOG(INFO, PCI_PRI_FMT " in_eeprom->offset = %d len = %d\n",
4098                     bp->pdev->addr.domain, bp->pdev->addr.bus,
4099                     bp->pdev->addr.devid, bp->pdev->addr.function,
4100                     in_eeprom->offset, in_eeprom->length);
4101
4102         if (in_eeprom->offset == 0) /* special offset value to get directory */
4103                 return bnxt_get_nvram_directory(bp, in_eeprom->length,
4104                                                 in_eeprom->data);
4105
4106         index = in_eeprom->offset >> 24;
4107         offset = in_eeprom->offset & 0xffffff;
4108
4109         if (index != 0)
4110                 return bnxt_hwrm_get_nvram_item(bp, index - 1, offset,
4111                                            in_eeprom->length, in_eeprom->data);
4112
4113         return 0;
4114 }
4115
4116 static bool bnxt_dir_type_is_ape_bin_format(uint16_t dir_type)
4117 {
4118         switch (dir_type) {
4119         case BNX_DIR_TYPE_CHIMP_PATCH:
4120         case BNX_DIR_TYPE_BOOTCODE:
4121         case BNX_DIR_TYPE_BOOTCODE_2:
4122         case BNX_DIR_TYPE_APE_FW:
4123         case BNX_DIR_TYPE_APE_PATCH:
4124         case BNX_DIR_TYPE_KONG_FW:
4125         case BNX_DIR_TYPE_KONG_PATCH:
4126         case BNX_DIR_TYPE_BONO_FW:
4127         case BNX_DIR_TYPE_BONO_PATCH:
4128                 /* FALLTHROUGH */
4129                 return true;
4130         }
4131
4132         return false;
4133 }
4134
4135 static bool bnxt_dir_type_is_other_exec_format(uint16_t dir_type)
4136 {
4137         switch (dir_type) {
4138         case BNX_DIR_TYPE_AVS:
4139         case BNX_DIR_TYPE_EXP_ROM_MBA:
4140         case BNX_DIR_TYPE_PCIE:
4141         case BNX_DIR_TYPE_TSCF_UCODE:
4142         case BNX_DIR_TYPE_EXT_PHY:
4143         case BNX_DIR_TYPE_CCM:
4144         case BNX_DIR_TYPE_ISCSI_BOOT:
4145         case BNX_DIR_TYPE_ISCSI_BOOT_IPV6:
4146         case BNX_DIR_TYPE_ISCSI_BOOT_IPV4N6:
4147                 /* FALLTHROUGH */
4148                 return true;
4149         }
4150
4151         return false;
4152 }
4153
4154 static bool bnxt_dir_type_is_executable(uint16_t dir_type)
4155 {
4156         return bnxt_dir_type_is_ape_bin_format(dir_type) ||
4157                 bnxt_dir_type_is_other_exec_format(dir_type);
4158 }
4159
4160 static int
4161 bnxt_set_eeprom_op(struct rte_eth_dev *dev,
4162                 struct rte_dev_eeprom_info *in_eeprom)
4163 {
4164         struct bnxt *bp = dev->data->dev_private;
4165         uint8_t index, dir_op;
4166         uint16_t type, ext, ordinal, attr;
4167         int rc;
4168
4169         rc = is_bnxt_in_error(bp);
4170         if (rc)
4171                 return rc;
4172
4173         PMD_DRV_LOG(INFO, PCI_PRI_FMT " in_eeprom->offset = %d len = %d\n",
4174                     bp->pdev->addr.domain, bp->pdev->addr.bus,
4175                     bp->pdev->addr.devid, bp->pdev->addr.function,
4176                     in_eeprom->offset, in_eeprom->length);
4177
4178         if (!BNXT_PF(bp)) {
4179                 PMD_DRV_LOG(ERR, "NVM write not supported from a VF\n");
4180                 return -EINVAL;
4181         }
4182
4183         type = in_eeprom->magic >> 16;
4184
4185         if (type == 0xffff) { /* special value for directory operations */
4186                 index = in_eeprom->magic & 0xff;
4187                 dir_op = in_eeprom->magic >> 8;
4188                 if (index == 0)
4189                         return -EINVAL;
4190                 switch (dir_op) {
4191                 case 0x0e: /* erase */
4192                         if (in_eeprom->offset != ~in_eeprom->magic)
4193                                 return -EINVAL;
4194                         return bnxt_hwrm_erase_nvram_directory(bp, index - 1);
4195                 default:
4196                         return -EINVAL;
4197                 }
4198         }
4199
4200         /* Create or re-write an NVM item: */
4201         if (bnxt_dir_type_is_executable(type) == true)
4202                 return -EOPNOTSUPP;
4203         ext = in_eeprom->magic & 0xffff;
4204         ordinal = in_eeprom->offset >> 16;
4205         attr = in_eeprom->offset & 0xffff;
4206
4207         return bnxt_hwrm_flash_nvram(bp, type, ordinal, ext, attr,
4208                                      in_eeprom->data, in_eeprom->length);
4209 }
4210
4211 /*
4212  * Initialization
4213  */
4214
4215 static const struct eth_dev_ops bnxt_dev_ops = {
4216         .dev_infos_get = bnxt_dev_info_get_op,
4217         .dev_close = bnxt_dev_close_op,
4218         .dev_configure = bnxt_dev_configure_op,
4219         .dev_start = bnxt_dev_start_op,
4220         .dev_stop = bnxt_dev_stop_op,
4221         .dev_set_link_up = bnxt_dev_set_link_up_op,
4222         .dev_set_link_down = bnxt_dev_set_link_down_op,
4223         .stats_get = bnxt_stats_get_op,
4224         .stats_reset = bnxt_stats_reset_op,
4225         .rx_queue_setup = bnxt_rx_queue_setup_op,
4226         .rx_queue_release = bnxt_rx_queue_release_op,
4227         .tx_queue_setup = bnxt_tx_queue_setup_op,
4228         .tx_queue_release = bnxt_tx_queue_release_op,
4229         .rx_queue_intr_enable = bnxt_rx_queue_intr_enable_op,
4230         .rx_queue_intr_disable = bnxt_rx_queue_intr_disable_op,
4231         .reta_update = bnxt_reta_update_op,
4232         .reta_query = bnxt_reta_query_op,
4233         .rss_hash_update = bnxt_rss_hash_update_op,
4234         .rss_hash_conf_get = bnxt_rss_hash_conf_get_op,
4235         .link_update = bnxt_link_update_op,
4236         .promiscuous_enable = bnxt_promiscuous_enable_op,
4237         .promiscuous_disable = bnxt_promiscuous_disable_op,
4238         .allmulticast_enable = bnxt_allmulticast_enable_op,
4239         .allmulticast_disable = bnxt_allmulticast_disable_op,
4240         .mac_addr_add = bnxt_mac_addr_add_op,
4241         .mac_addr_remove = bnxt_mac_addr_remove_op,
4242         .flow_ctrl_get = bnxt_flow_ctrl_get_op,
4243         .flow_ctrl_set = bnxt_flow_ctrl_set_op,
4244         .udp_tunnel_port_add  = bnxt_udp_tunnel_port_add_op,
4245         .udp_tunnel_port_del  = bnxt_udp_tunnel_port_del_op,
4246         .vlan_filter_set = bnxt_vlan_filter_set_op,
4247         .vlan_offload_set = bnxt_vlan_offload_set_op,
4248         .vlan_tpid_set = bnxt_vlan_tpid_set_op,
4249         .vlan_pvid_set = bnxt_vlan_pvid_set_op,
4250         .mtu_set = bnxt_mtu_set_op,
4251         .mac_addr_set = bnxt_set_default_mac_addr_op,
4252         .xstats_get = bnxt_dev_xstats_get_op,
4253         .xstats_get_names = bnxt_dev_xstats_get_names_op,
4254         .xstats_reset = bnxt_dev_xstats_reset_op,
4255         .fw_version_get = bnxt_fw_version_get,
4256         .set_mc_addr_list = bnxt_dev_set_mc_addr_list_op,
4257         .rxq_info_get = bnxt_rxq_info_get_op,
4258         .txq_info_get = bnxt_txq_info_get_op,
4259         .rx_burst_mode_get = bnxt_rx_burst_mode_get,
4260         .tx_burst_mode_get = bnxt_tx_burst_mode_get,
4261         .dev_led_on = bnxt_dev_led_on_op,
4262         .dev_led_off = bnxt_dev_led_off_op,
4263         .xstats_get_by_id = bnxt_dev_xstats_get_by_id_op,
4264         .xstats_get_names_by_id = bnxt_dev_xstats_get_names_by_id_op,
4265         .rx_queue_start = bnxt_rx_queue_start,
4266         .rx_queue_stop = bnxt_rx_queue_stop,
4267         .tx_queue_start = bnxt_tx_queue_start,
4268         .tx_queue_stop = bnxt_tx_queue_stop,
4269         .filter_ctrl = bnxt_filter_ctrl_op,
4270         .dev_supported_ptypes_get = bnxt_dev_supported_ptypes_get_op,
4271         .get_eeprom_length    = bnxt_get_eeprom_length_op,
4272         .get_eeprom           = bnxt_get_eeprom_op,
4273         .set_eeprom           = bnxt_set_eeprom_op,
4274         .timesync_enable      = bnxt_timesync_enable,
4275         .timesync_disable     = bnxt_timesync_disable,
4276         .timesync_read_time   = bnxt_timesync_read_time,
4277         .timesync_write_time   = bnxt_timesync_write_time,
4278         .timesync_adjust_time = bnxt_timesync_adjust_time,
4279         .timesync_read_rx_timestamp = bnxt_timesync_read_rx_timestamp,
4280         .timesync_read_tx_timestamp = bnxt_timesync_read_tx_timestamp,
4281 };
4282
4283 static uint32_t bnxt_map_reset_regs(struct bnxt *bp, uint32_t reg)
4284 {
4285         uint32_t offset;
4286
4287         /* Only pre-map the reset GRC registers using window 3 */
4288         rte_write32(reg & 0xfffff000, (uint8_t *)bp->bar0 +
4289                     BNXT_GRCPF_REG_WINDOW_BASE_OUT + 8);
4290
4291         offset = BNXT_GRCP_WINDOW_3_BASE + (reg & 0xffc);
4292
4293         return offset;
4294 }
4295
4296 int bnxt_map_fw_health_status_regs(struct bnxt *bp)
4297 {
4298         struct bnxt_error_recovery_info *info = bp->recovery_info;
4299         uint32_t reg_base = 0xffffffff;
4300         int i;
4301
4302         /* Only pre-map the monitoring GRC registers using window 2 */
4303         for (i = 0; i < BNXT_FW_STATUS_REG_CNT; i++) {
4304                 uint32_t reg = info->status_regs[i];
4305
4306                 if (BNXT_FW_STATUS_REG_TYPE(reg) != BNXT_FW_STATUS_REG_TYPE_GRC)
4307                         continue;
4308
4309                 if (reg_base == 0xffffffff)
4310                         reg_base = reg & 0xfffff000;
4311                 if ((reg & 0xfffff000) != reg_base)
4312                         return -ERANGE;
4313
4314                 /* Use mask 0xffc as the Lower 2 bits indicates
4315                  * address space location
4316                  */
4317                 info->mapped_status_regs[i] = BNXT_GRCP_WINDOW_2_BASE +
4318                                                 (reg & 0xffc);
4319         }
4320
4321         if (reg_base == 0xffffffff)
4322                 return 0;
4323
4324         rte_write32(reg_base, (uint8_t *)bp->bar0 +
4325                     BNXT_GRCPF_REG_WINDOW_BASE_OUT + 4);
4326
4327         return 0;
4328 }
4329
4330 static void bnxt_write_fw_reset_reg(struct bnxt *bp, uint32_t index)
4331 {
4332         struct bnxt_error_recovery_info *info = bp->recovery_info;
4333         uint32_t delay = info->delay_after_reset[index];
4334         uint32_t val = info->reset_reg_val[index];
4335         uint32_t reg = info->reset_reg[index];
4336         uint32_t type, offset;
4337
4338         type = BNXT_FW_STATUS_REG_TYPE(reg);
4339         offset = BNXT_FW_STATUS_REG_OFF(reg);
4340
4341         switch (type) {
4342         case BNXT_FW_STATUS_REG_TYPE_CFG:
4343                 rte_pci_write_config(bp->pdev, &val, sizeof(val), offset);
4344                 break;
4345         case BNXT_FW_STATUS_REG_TYPE_GRC:
4346                 offset = bnxt_map_reset_regs(bp, offset);
4347                 rte_write32(val, (uint8_t *)bp->bar0 + offset);
4348                 break;
4349         case BNXT_FW_STATUS_REG_TYPE_BAR0:
4350                 rte_write32(val, (uint8_t *)bp->bar0 + offset);
4351                 break;
4352         }
4353         /* wait on a specific interval of time until core reset is complete */
4354         if (delay)
4355                 rte_delay_ms(delay);
4356 }
4357
4358 static void bnxt_dev_cleanup(struct bnxt *bp)
4359 {
4360         bnxt_set_hwrm_link_config(bp, false);
4361         bp->link_info->link_up = 0;
4362         if (bp->eth_dev->data->dev_started)
4363                 bnxt_dev_stop_op(bp->eth_dev);
4364
4365         bnxt_uninit_resources(bp, true);
4366 }
4367
4368 static int bnxt_restore_vlan_filters(struct bnxt *bp)
4369 {
4370         struct rte_eth_dev *dev = bp->eth_dev;
4371         struct rte_vlan_filter_conf *vfc;
4372         int vidx, vbit, rc;
4373         uint16_t vlan_id;
4374
4375         for (vlan_id = 1; vlan_id <= RTE_ETHER_MAX_VLAN_ID; vlan_id++) {
4376                 vfc = &dev->data->vlan_filter_conf;
4377                 vidx = vlan_id / 64;
4378                 vbit = vlan_id % 64;
4379
4380                 /* Each bit corresponds to a VLAN id */
4381                 if (vfc->ids[vidx] & (UINT64_C(1) << vbit)) {
4382                         rc = bnxt_add_vlan_filter(bp, vlan_id);
4383                         if (rc)
4384                                 return rc;
4385                 }
4386         }
4387
4388         return 0;
4389 }
4390
4391 static int bnxt_restore_mac_filters(struct bnxt *bp)
4392 {
4393         struct rte_eth_dev *dev = bp->eth_dev;
4394         struct rte_eth_dev_info dev_info;
4395         struct rte_ether_addr *addr;
4396         uint64_t pool_mask;
4397         uint32_t pool = 0;
4398         uint16_t i;
4399         int rc;
4400
4401         if (BNXT_VF(bp) && !BNXT_VF_IS_TRUSTED(bp))
4402                 return 0;
4403
4404         rc = bnxt_dev_info_get_op(dev, &dev_info);
4405         if (rc)
4406                 return rc;
4407
4408         /* replay MAC address configuration */
4409         for (i = 1; i < dev_info.max_mac_addrs; i++) {
4410                 addr = &dev->data->mac_addrs[i];
4411
4412                 /* skip zero address */
4413                 if (rte_is_zero_ether_addr(addr))
4414                         continue;
4415
4416                 pool = 0;
4417                 pool_mask = dev->data->mac_pool_sel[i];
4418
4419                 do {
4420                         if (pool_mask & 1ULL) {
4421                                 rc = bnxt_mac_addr_add_op(dev, addr, i, pool);
4422                                 if (rc)
4423                                         return rc;
4424                         }
4425                         pool_mask >>= 1;
4426                         pool++;
4427                 } while (pool_mask);
4428         }
4429
4430         return 0;
4431 }
4432
4433 static int bnxt_restore_filters(struct bnxt *bp)
4434 {
4435         struct rte_eth_dev *dev = bp->eth_dev;
4436         int ret = 0;
4437
4438         if (dev->data->all_multicast) {
4439                 ret = bnxt_allmulticast_enable_op(dev);
4440                 if (ret)
4441                         return ret;
4442         }
4443         if (dev->data->promiscuous) {
4444                 ret = bnxt_promiscuous_enable_op(dev);
4445                 if (ret)
4446                         return ret;
4447         }
4448
4449         ret = bnxt_restore_mac_filters(bp);
4450         if (ret)
4451                 return ret;
4452
4453         ret = bnxt_restore_vlan_filters(bp);
4454         /* TODO restore other filters as well */
4455         return ret;
4456 }
4457
4458 static void bnxt_dev_recover(void *arg)
4459 {
4460         struct bnxt *bp = arg;
4461         int timeout = bp->fw_reset_max_msecs;
4462         int rc = 0;
4463
4464         /* Clear Error flag so that device re-init should happen */
4465         bp->flags &= ~BNXT_FLAG_FATAL_ERROR;
4466
4467         do {
4468                 rc = bnxt_hwrm_ver_get(bp, SHORT_HWRM_CMD_TIMEOUT);
4469                 if (rc == 0)
4470                         break;
4471                 rte_delay_ms(BNXT_FW_READY_WAIT_INTERVAL);
4472                 timeout -= BNXT_FW_READY_WAIT_INTERVAL;
4473         } while (rc && timeout);
4474
4475         if (rc) {
4476                 PMD_DRV_LOG(ERR, "FW is not Ready after reset\n");
4477                 goto err;
4478         }
4479
4480         rc = bnxt_init_resources(bp, true);
4481         if (rc) {
4482                 PMD_DRV_LOG(ERR,
4483                             "Failed to initialize resources after reset\n");
4484                 goto err;
4485         }
4486         /* clear reset flag as the device is initialized now */
4487         bp->flags &= ~BNXT_FLAG_FW_RESET;
4488
4489         rc = bnxt_dev_start_op(bp->eth_dev);
4490         if (rc) {
4491                 PMD_DRV_LOG(ERR, "Failed to start port after reset\n");
4492                 goto err_start;
4493         }
4494
4495         rc = bnxt_restore_filters(bp);
4496         if (rc)
4497                 goto err_start;
4498
4499         PMD_DRV_LOG(INFO, "Recovered from FW reset\n");
4500         return;
4501 err_start:
4502         bnxt_dev_stop_op(bp->eth_dev);
4503 err:
4504         bp->flags |= BNXT_FLAG_FATAL_ERROR;
4505         bnxt_uninit_resources(bp, false);
4506         PMD_DRV_LOG(ERR, "Failed to recover from FW reset\n");
4507 }
4508
4509 void bnxt_dev_reset_and_resume(void *arg)
4510 {
4511         struct bnxt *bp = arg;
4512         int rc;
4513
4514         bnxt_dev_cleanup(bp);
4515
4516         bnxt_wait_for_device_shutdown(bp);
4517
4518         rc = rte_eal_alarm_set(US_PER_MS * bp->fw_reset_min_msecs,
4519                                bnxt_dev_recover, (void *)bp);
4520         if (rc)
4521                 PMD_DRV_LOG(ERR, "Error setting recovery alarm");
4522 }
4523
4524 uint32_t bnxt_read_fw_status_reg(struct bnxt *bp, uint32_t index)
4525 {
4526         struct bnxt_error_recovery_info *info = bp->recovery_info;
4527         uint32_t reg = info->status_regs[index];
4528         uint32_t type, offset, val = 0;
4529
4530         type = BNXT_FW_STATUS_REG_TYPE(reg);
4531         offset = BNXT_FW_STATUS_REG_OFF(reg);
4532
4533         switch (type) {
4534         case BNXT_FW_STATUS_REG_TYPE_CFG:
4535                 rte_pci_read_config(bp->pdev, &val, sizeof(val), offset);
4536                 break;
4537         case BNXT_FW_STATUS_REG_TYPE_GRC:
4538                 offset = info->mapped_status_regs[index];
4539                 /* FALLTHROUGH */
4540         case BNXT_FW_STATUS_REG_TYPE_BAR0:
4541                 val = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
4542                                        offset));
4543                 break;
4544         }
4545
4546         return val;
4547 }
4548
4549 static int bnxt_fw_reset_all(struct bnxt *bp)
4550 {
4551         struct bnxt_error_recovery_info *info = bp->recovery_info;
4552         uint32_t i;
4553         int rc = 0;
4554
4555         if (info->flags & BNXT_FLAG_ERROR_RECOVERY_HOST) {
4556                 /* Reset through master function driver */
4557                 for (i = 0; i < info->reg_array_cnt; i++)
4558                         bnxt_write_fw_reset_reg(bp, i);
4559                 /* Wait for time specified by FW after triggering reset */
4560                 rte_delay_ms(info->master_func_wait_period_after_reset);
4561         } else if (info->flags & BNXT_FLAG_ERROR_RECOVERY_CO_CPU) {
4562                 /* Reset with the help of Kong processor */
4563                 rc = bnxt_hwrm_fw_reset(bp);
4564                 if (rc)
4565                         PMD_DRV_LOG(ERR, "Failed to reset FW\n");
4566         }
4567
4568         return rc;
4569 }
4570
4571 static void bnxt_fw_reset_cb(void *arg)
4572 {
4573         struct bnxt *bp = arg;
4574         struct bnxt_error_recovery_info *info = bp->recovery_info;
4575         int rc = 0;
4576
4577         /* Only Master function can do FW reset */
4578         if (bnxt_is_master_func(bp) &&
4579             bnxt_is_recovery_enabled(bp)) {
4580                 rc = bnxt_fw_reset_all(bp);
4581                 if (rc) {
4582                         PMD_DRV_LOG(ERR, "Adapter recovery failed\n");
4583                         return;
4584                 }
4585         }
4586
4587         /* if recovery method is ERROR_RECOVERY_CO_CPU, KONG will send
4588          * EXCEPTION_FATAL_ASYNC event to all the functions
4589          * (including MASTER FUNC). After receiving this Async, all the active
4590          * drivers should treat this case as FW initiated recovery
4591          */
4592         if (info->flags & BNXT_FLAG_ERROR_RECOVERY_HOST) {
4593                 bp->fw_reset_min_msecs = BNXT_MIN_FW_READY_TIMEOUT;
4594                 bp->fw_reset_max_msecs = BNXT_MAX_FW_RESET_TIMEOUT;
4595
4596                 /* To recover from error */
4597                 rte_eal_alarm_set(US_PER_MS, bnxt_dev_reset_and_resume,
4598                                   (void *)bp);
4599         }
4600 }
4601
4602 /* Driver should poll FW heartbeat, reset_counter with the frequency
4603  * advertised by FW in HWRM_ERROR_RECOVERY_QCFG.
4604  * When the driver detects heartbeat stop or change in reset_counter,
4605  * it has to trigger a reset to recover from the error condition.
4606  * A “master PF” is the function who will have the privilege to
4607  * initiate the chimp reset. The master PF will be elected by the
4608  * firmware and will be notified through async message.
4609  */
4610 static void bnxt_check_fw_health(void *arg)
4611 {
4612         struct bnxt *bp = arg;
4613         struct bnxt_error_recovery_info *info = bp->recovery_info;
4614         uint32_t val = 0, wait_msec;
4615
4616         if (!info || !bnxt_is_recovery_enabled(bp) ||
4617             is_bnxt_in_error(bp))
4618                 return;
4619
4620         val = bnxt_read_fw_status_reg(bp, BNXT_FW_HEARTBEAT_CNT_REG);
4621         if (val == info->last_heart_beat)
4622                 goto reset;
4623
4624         info->last_heart_beat = val;
4625
4626         val = bnxt_read_fw_status_reg(bp, BNXT_FW_RECOVERY_CNT_REG);
4627         if (val != info->last_reset_counter)
4628                 goto reset;
4629
4630         info->last_reset_counter = val;
4631
4632         rte_eal_alarm_set(US_PER_MS * info->driver_polling_freq,
4633                           bnxt_check_fw_health, (void *)bp);
4634
4635         return;
4636 reset:
4637         /* Stop DMA to/from device */
4638         bp->flags |= BNXT_FLAG_FATAL_ERROR;
4639         bp->flags |= BNXT_FLAG_FW_RESET;
4640
4641         PMD_DRV_LOG(ERR, "Detected FW dead condition\n");
4642
4643         if (bnxt_is_master_func(bp))
4644                 wait_msec = info->master_func_wait_period;
4645         else
4646                 wait_msec = info->normal_func_wait_period;
4647
4648         rte_eal_alarm_set(US_PER_MS * wait_msec,
4649                           bnxt_fw_reset_cb, (void *)bp);
4650 }
4651
4652 void bnxt_schedule_fw_health_check(struct bnxt *bp)
4653 {
4654         uint32_t polling_freq;
4655
4656         if (!bnxt_is_recovery_enabled(bp))
4657                 return;
4658
4659         if (bp->flags & BNXT_FLAG_FW_HEALTH_CHECK_SCHEDULED)
4660                 return;
4661
4662         polling_freq = bp->recovery_info->driver_polling_freq;
4663
4664         rte_eal_alarm_set(US_PER_MS * polling_freq,
4665                           bnxt_check_fw_health, (void *)bp);
4666         bp->flags |= BNXT_FLAG_FW_HEALTH_CHECK_SCHEDULED;
4667 }
4668
4669 static void bnxt_cancel_fw_health_check(struct bnxt *bp)
4670 {
4671         if (!bnxt_is_recovery_enabled(bp))
4672                 return;
4673
4674         rte_eal_alarm_cancel(bnxt_check_fw_health, (void *)bp);
4675         bp->flags &= ~BNXT_FLAG_FW_HEALTH_CHECK_SCHEDULED;
4676 }
4677
4678 static bool bnxt_vf_pciid(uint16_t device_id)
4679 {
4680         switch (device_id) {
4681         case BROADCOM_DEV_ID_57304_VF:
4682         case BROADCOM_DEV_ID_57406_VF:
4683         case BROADCOM_DEV_ID_5731X_VF:
4684         case BROADCOM_DEV_ID_5741X_VF:
4685         case BROADCOM_DEV_ID_57414_VF:
4686         case BROADCOM_DEV_ID_STRATUS_NIC_VF1:
4687         case BROADCOM_DEV_ID_STRATUS_NIC_VF2:
4688         case BROADCOM_DEV_ID_58802_VF:
4689         case BROADCOM_DEV_ID_57500_VF1:
4690         case BROADCOM_DEV_ID_57500_VF2:
4691                 /* FALLTHROUGH */
4692                 return true;
4693         default:
4694                 return false;
4695         }
4696 }
4697
4698 static bool bnxt_thor_device(uint16_t device_id)
4699 {
4700         switch (device_id) {
4701         case BROADCOM_DEV_ID_57508:
4702         case BROADCOM_DEV_ID_57504:
4703         case BROADCOM_DEV_ID_57502:
4704         case BROADCOM_DEV_ID_57508_MF1:
4705         case BROADCOM_DEV_ID_57504_MF1:
4706         case BROADCOM_DEV_ID_57502_MF1:
4707         case BROADCOM_DEV_ID_57508_MF2:
4708         case BROADCOM_DEV_ID_57504_MF2:
4709         case BROADCOM_DEV_ID_57502_MF2:
4710         case BROADCOM_DEV_ID_57500_VF1:
4711         case BROADCOM_DEV_ID_57500_VF2:
4712                 /* FALLTHROUGH */
4713                 return true;
4714         default:
4715                 return false;
4716         }
4717 }
4718
4719 bool bnxt_stratus_device(struct bnxt *bp)
4720 {
4721         uint16_t device_id = bp->pdev->id.device_id;
4722
4723         switch (device_id) {
4724         case BROADCOM_DEV_ID_STRATUS_NIC:
4725         case BROADCOM_DEV_ID_STRATUS_NIC_VF1:
4726         case BROADCOM_DEV_ID_STRATUS_NIC_VF2:
4727                 /* FALLTHROUGH */
4728                 return true;
4729         default:
4730                 return false;
4731         }
4732 }
4733
4734 static int bnxt_init_board(struct rte_eth_dev *eth_dev)
4735 {
4736         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
4737         struct bnxt *bp = eth_dev->data->dev_private;
4738
4739         /* enable device (incl. PCI PM wakeup), and bus-mastering */
4740         bp->bar0 = (void *)pci_dev->mem_resource[0].addr;
4741         bp->doorbell_base = (void *)pci_dev->mem_resource[2].addr;
4742         if (!bp->bar0 || !bp->doorbell_base) {
4743                 PMD_DRV_LOG(ERR, "Unable to access Hardware\n");
4744                 return -ENODEV;
4745         }
4746
4747         bp->eth_dev = eth_dev;
4748         bp->pdev = pci_dev;
4749
4750         return 0;
4751 }
4752
4753 static int bnxt_alloc_ctx_mem_blk(struct bnxt *bp,
4754                                   struct bnxt_ctx_pg_info *ctx_pg,
4755                                   uint32_t mem_size,
4756                                   const char *suffix,
4757                                   uint16_t idx)
4758 {
4759         struct bnxt_ring_mem_info *rmem = &ctx_pg->ring_mem;
4760         const struct rte_memzone *mz = NULL;
4761         char mz_name[RTE_MEMZONE_NAMESIZE];
4762         rte_iova_t mz_phys_addr;
4763         uint64_t valid_bits = 0;
4764         uint32_t sz;
4765         int i;
4766
4767         if (!mem_size)
4768                 return 0;
4769
4770         rmem->nr_pages = RTE_ALIGN_MUL_CEIL(mem_size, BNXT_PAGE_SIZE) /
4771                          BNXT_PAGE_SIZE;
4772         rmem->page_size = BNXT_PAGE_SIZE;
4773         rmem->pg_arr = ctx_pg->ctx_pg_arr;
4774         rmem->dma_arr = ctx_pg->ctx_dma_arr;
4775         rmem->flags = BNXT_RMEM_VALID_PTE_FLAG;
4776
4777         valid_bits = PTU_PTE_VALID;
4778
4779         if (rmem->nr_pages > 1) {
4780                 snprintf(mz_name, RTE_MEMZONE_NAMESIZE,
4781                          "bnxt_ctx_pg_tbl%s_%x_%d",
4782                          suffix, idx, bp->eth_dev->data->port_id);
4783                 mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0;
4784                 mz = rte_memzone_lookup(mz_name);
4785                 if (!mz) {
4786                         mz = rte_memzone_reserve_aligned(mz_name,
4787                                                 rmem->nr_pages * 8,
4788                                                 SOCKET_ID_ANY,
4789                                                 RTE_MEMZONE_2MB |
4790                                                 RTE_MEMZONE_SIZE_HINT_ONLY |
4791                                                 RTE_MEMZONE_IOVA_CONTIG,
4792                                                 BNXT_PAGE_SIZE);
4793                         if (mz == NULL)
4794                                 return -ENOMEM;
4795                 }
4796
4797                 memset(mz->addr, 0, mz->len);
4798                 mz_phys_addr = mz->iova;
4799
4800                 rmem->pg_tbl = mz->addr;
4801                 rmem->pg_tbl_map = mz_phys_addr;
4802                 rmem->pg_tbl_mz = mz;
4803         }
4804
4805         snprintf(mz_name, RTE_MEMZONE_NAMESIZE, "bnxt_ctx_%s_%x_%d",
4806                  suffix, idx, bp->eth_dev->data->port_id);
4807         mz = rte_memzone_lookup(mz_name);
4808         if (!mz) {
4809                 mz = rte_memzone_reserve_aligned(mz_name,
4810                                                  mem_size,
4811                                                  SOCKET_ID_ANY,
4812                                                  RTE_MEMZONE_1GB |
4813                                                  RTE_MEMZONE_SIZE_HINT_ONLY |
4814                                                  RTE_MEMZONE_IOVA_CONTIG,
4815                                                  BNXT_PAGE_SIZE);
4816                 if (mz == NULL)
4817                         return -ENOMEM;
4818         }
4819
4820         memset(mz->addr, 0, mz->len);
4821         mz_phys_addr = mz->iova;
4822
4823         for (sz = 0, i = 0; sz < mem_size; sz += BNXT_PAGE_SIZE, i++) {
4824                 rmem->pg_arr[i] = ((char *)mz->addr) + sz;
4825                 rmem->dma_arr[i] = mz_phys_addr + sz;
4826
4827                 if (rmem->nr_pages > 1) {
4828                         if (i == rmem->nr_pages - 2 &&
4829                             (rmem->flags & BNXT_RMEM_RING_PTE_FLAG))
4830                                 valid_bits |= PTU_PTE_NEXT_TO_LAST;
4831                         else if (i == rmem->nr_pages - 1 &&
4832                                  (rmem->flags & BNXT_RMEM_RING_PTE_FLAG))
4833                                 valid_bits |= PTU_PTE_LAST;
4834
4835                         rmem->pg_tbl[i] = rte_cpu_to_le_64(rmem->dma_arr[i] |
4836                                                            valid_bits);
4837                 }
4838         }
4839
4840         rmem->mz = mz;
4841         if (rmem->vmem_size)
4842                 rmem->vmem = (void **)mz->addr;
4843         rmem->dma_arr[0] = mz_phys_addr;
4844         return 0;
4845 }
4846
4847 static void bnxt_free_ctx_mem(struct bnxt *bp)
4848 {
4849         int i;
4850
4851         if (!bp->ctx || !(bp->ctx->flags & BNXT_CTX_FLAG_INITED))
4852                 return;
4853
4854         bp->ctx->flags &= ~BNXT_CTX_FLAG_INITED;
4855         rte_memzone_free(bp->ctx->qp_mem.ring_mem.mz);
4856         rte_memzone_free(bp->ctx->srq_mem.ring_mem.mz);
4857         rte_memzone_free(bp->ctx->cq_mem.ring_mem.mz);
4858         rte_memzone_free(bp->ctx->vnic_mem.ring_mem.mz);
4859         rte_memzone_free(bp->ctx->stat_mem.ring_mem.mz);
4860         rte_memzone_free(bp->ctx->qp_mem.ring_mem.pg_tbl_mz);
4861         rte_memzone_free(bp->ctx->srq_mem.ring_mem.pg_tbl_mz);
4862         rte_memzone_free(bp->ctx->cq_mem.ring_mem.pg_tbl_mz);
4863         rte_memzone_free(bp->ctx->vnic_mem.ring_mem.pg_tbl_mz);
4864         rte_memzone_free(bp->ctx->stat_mem.ring_mem.pg_tbl_mz);
4865
4866         for (i = 0; i < bp->ctx->tqm_fp_rings_count + 1; i++) {
4867                 if (bp->ctx->tqm_mem[i])
4868                         rte_memzone_free(bp->ctx->tqm_mem[i]->ring_mem.mz);
4869         }
4870
4871         rte_free(bp->ctx);
4872         bp->ctx = NULL;
4873 }
4874
4875 #define bnxt_roundup(x, y)   ((((x) + ((y) - 1)) / (y)) * (y))
4876
4877 #define min_t(type, x, y) ({                    \
4878         type __min1 = (x);                      \
4879         type __min2 = (y);                      \
4880         __min1 < __min2 ? __min1 : __min2; })
4881
4882 #define max_t(type, x, y) ({                    \
4883         type __max1 = (x);                      \
4884         type __max2 = (y);                      \
4885         __max1 > __max2 ? __max1 : __max2; })
4886
4887 #define clamp_t(type, _x, min, max)     min_t(type, max_t(type, _x, min), max)
4888
4889 int bnxt_alloc_ctx_mem(struct bnxt *bp)
4890 {
4891         struct bnxt_ctx_pg_info *ctx_pg;
4892         struct bnxt_ctx_mem_info *ctx;
4893         uint32_t mem_size, ena, entries;
4894         uint32_t entries_sp, min;
4895         int i, rc;
4896
4897         rc = bnxt_hwrm_func_backing_store_qcaps(bp);
4898         if (rc) {
4899                 PMD_DRV_LOG(ERR, "Query context mem capability failed\n");
4900                 return rc;
4901         }
4902         ctx = bp->ctx;
4903         if (!ctx || (ctx->flags & BNXT_CTX_FLAG_INITED))
4904                 return 0;
4905
4906         ctx_pg = &ctx->qp_mem;
4907         ctx_pg->entries = ctx->qp_min_qp1_entries + ctx->qp_max_l2_entries;
4908         mem_size = ctx->qp_entry_size * ctx_pg->entries;
4909         rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "qp_mem", 0);
4910         if (rc)
4911                 return rc;
4912
4913         ctx_pg = &ctx->srq_mem;
4914         ctx_pg->entries = ctx->srq_max_l2_entries;
4915         mem_size = ctx->srq_entry_size * ctx_pg->entries;
4916         rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "srq_mem", 0);
4917         if (rc)
4918                 return rc;
4919
4920         ctx_pg = &ctx->cq_mem;
4921         ctx_pg->entries = ctx->cq_max_l2_entries;
4922         mem_size = ctx->cq_entry_size * ctx_pg->entries;
4923         rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "cq_mem", 0);
4924         if (rc)
4925                 return rc;
4926
4927         ctx_pg = &ctx->vnic_mem;
4928         ctx_pg->entries = ctx->vnic_max_vnic_entries +
4929                 ctx->vnic_max_ring_table_entries;
4930         mem_size = ctx->vnic_entry_size * ctx_pg->entries;
4931         rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "vnic_mem", 0);
4932         if (rc)
4933                 return rc;
4934
4935         ctx_pg = &ctx->stat_mem;
4936         ctx_pg->entries = ctx->stat_max_entries;
4937         mem_size = ctx->stat_entry_size * ctx_pg->entries;
4938         rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "stat_mem", 0);
4939         if (rc)
4940                 return rc;
4941
4942         min = ctx->tqm_min_entries_per_ring;
4943
4944         entries_sp = ctx->qp_max_l2_entries +
4945                      ctx->vnic_max_vnic_entries +
4946                      2 * ctx->qp_min_qp1_entries + min;
4947         entries_sp = bnxt_roundup(entries_sp, ctx->tqm_entries_multiple);
4948
4949         entries = ctx->qp_max_l2_entries + ctx->qp_min_qp1_entries;
4950         entries = bnxt_roundup(entries, ctx->tqm_entries_multiple);
4951         entries = clamp_t(uint32_t, entries, min,
4952                           ctx->tqm_max_entries_per_ring);
4953         for (i = 0, ena = 0; i < ctx->tqm_fp_rings_count + 1; i++) {
4954                 ctx_pg = ctx->tqm_mem[i];
4955                 ctx_pg->entries = i ? entries : entries_sp;
4956                 mem_size = ctx->tqm_entry_size * ctx_pg->entries;
4957                 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "tqm_mem", i);
4958                 if (rc)
4959                         return rc;
4960                 ena |= HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_SP << i;
4961         }
4962
4963         ena |= FUNC_BACKING_STORE_CFG_INPUT_DFLT_ENABLES;
4964         rc = bnxt_hwrm_func_backing_store_cfg(bp, ena);
4965         if (rc)
4966                 PMD_DRV_LOG(ERR,
4967                             "Failed to configure context mem: rc = %d\n", rc);
4968         else
4969                 ctx->flags |= BNXT_CTX_FLAG_INITED;
4970
4971         return rc;
4972 }
4973
4974 static int bnxt_alloc_stats_mem(struct bnxt *bp)
4975 {
4976         struct rte_pci_device *pci_dev = bp->pdev;
4977         char mz_name[RTE_MEMZONE_NAMESIZE];
4978         const struct rte_memzone *mz = NULL;
4979         uint32_t total_alloc_len;
4980         rte_iova_t mz_phys_addr;
4981
4982         if (pci_dev->id.device_id == BROADCOM_DEV_ID_NS2)
4983                 return 0;
4984
4985         snprintf(mz_name, RTE_MEMZONE_NAMESIZE,
4986                  "bnxt_" PCI_PRI_FMT "-%s", pci_dev->addr.domain,
4987                  pci_dev->addr.bus, pci_dev->addr.devid,
4988                  pci_dev->addr.function, "rx_port_stats");
4989         mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0;
4990         mz = rte_memzone_lookup(mz_name);
4991         total_alloc_len =
4992                 RTE_CACHE_LINE_ROUNDUP(sizeof(struct rx_port_stats) +
4993                                        sizeof(struct rx_port_stats_ext) + 512);
4994         if (!mz) {
4995                 mz = rte_memzone_reserve(mz_name, total_alloc_len,
4996                                          SOCKET_ID_ANY,
4997                                          RTE_MEMZONE_2MB |
4998                                          RTE_MEMZONE_SIZE_HINT_ONLY |
4999                                          RTE_MEMZONE_IOVA_CONTIG);
5000                 if (mz == NULL)
5001                         return -ENOMEM;
5002         }
5003         memset(mz->addr, 0, mz->len);
5004         mz_phys_addr = mz->iova;
5005
5006         bp->rx_mem_zone = (const void *)mz;
5007         bp->hw_rx_port_stats = mz->addr;
5008         bp->hw_rx_port_stats_map = mz_phys_addr;
5009
5010         snprintf(mz_name, RTE_MEMZONE_NAMESIZE,
5011                  "bnxt_" PCI_PRI_FMT "-%s", pci_dev->addr.domain,
5012                  pci_dev->addr.bus, pci_dev->addr.devid,
5013                  pci_dev->addr.function, "tx_port_stats");
5014         mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0;
5015         mz = rte_memzone_lookup(mz_name);
5016         total_alloc_len =
5017                 RTE_CACHE_LINE_ROUNDUP(sizeof(struct tx_port_stats) +
5018                                        sizeof(struct tx_port_stats_ext) + 512);
5019         if (!mz) {
5020                 mz = rte_memzone_reserve(mz_name,
5021                                          total_alloc_len,
5022                                          SOCKET_ID_ANY,
5023                                          RTE_MEMZONE_2MB |
5024                                          RTE_MEMZONE_SIZE_HINT_ONLY |
5025                                          RTE_MEMZONE_IOVA_CONTIG);
5026                 if (mz == NULL)
5027                         return -ENOMEM;
5028         }
5029         memset(mz->addr, 0, mz->len);
5030         mz_phys_addr = mz->iova;
5031
5032         bp->tx_mem_zone = (const void *)mz;
5033         bp->hw_tx_port_stats = mz->addr;
5034         bp->hw_tx_port_stats_map = mz_phys_addr;
5035         bp->flags |= BNXT_FLAG_PORT_STATS;
5036
5037         /* Display extended statistics if FW supports it */
5038         if (bp->hwrm_spec_code < HWRM_SPEC_CODE_1_8_4 ||
5039             bp->hwrm_spec_code == HWRM_SPEC_CODE_1_9_0 ||
5040             !(bp->flags & BNXT_FLAG_EXT_STATS_SUPPORTED))
5041                 return 0;
5042
5043         bp->hw_rx_port_stats_ext = (void *)
5044                 ((uint8_t *)bp->hw_rx_port_stats +
5045                  sizeof(struct rx_port_stats));
5046         bp->hw_rx_port_stats_ext_map = bp->hw_rx_port_stats_map +
5047                 sizeof(struct rx_port_stats);
5048         bp->flags |= BNXT_FLAG_EXT_RX_PORT_STATS;
5049
5050         if (bp->hwrm_spec_code < HWRM_SPEC_CODE_1_9_2 ||
5051             bp->flags & BNXT_FLAG_EXT_STATS_SUPPORTED) {
5052                 bp->hw_tx_port_stats_ext = (void *)
5053                         ((uint8_t *)bp->hw_tx_port_stats +
5054                          sizeof(struct tx_port_stats));
5055                 bp->hw_tx_port_stats_ext_map =
5056                         bp->hw_tx_port_stats_map +
5057                         sizeof(struct tx_port_stats);
5058                 bp->flags |= BNXT_FLAG_EXT_TX_PORT_STATS;
5059         }
5060
5061         return 0;
5062 }
5063
5064 static int bnxt_setup_mac_addr(struct rte_eth_dev *eth_dev)
5065 {
5066         struct bnxt *bp = eth_dev->data->dev_private;
5067         int rc = 0;
5068
5069         eth_dev->data->mac_addrs = rte_zmalloc("bnxt_mac_addr_tbl",
5070                                                RTE_ETHER_ADDR_LEN *
5071                                                bp->max_l2_ctx,
5072                                                0);
5073         if (eth_dev->data->mac_addrs == NULL) {
5074                 PMD_DRV_LOG(ERR, "Failed to alloc MAC addr tbl\n");
5075                 return -ENOMEM;
5076         }
5077
5078         if (!BNXT_HAS_DFLT_MAC_SET(bp)) {
5079                 if (BNXT_PF(bp))
5080                         return -EINVAL;
5081
5082                 /* Generate a random MAC address, if none was assigned by PF */
5083                 PMD_DRV_LOG(INFO, "VF MAC address not assigned by Host PF\n");
5084                 bnxt_eth_hw_addr_random(bp->mac_addr);
5085                 PMD_DRV_LOG(INFO,
5086                             "Assign random MAC:%02X:%02X:%02X:%02X:%02X:%02X\n",
5087                             bp->mac_addr[0], bp->mac_addr[1], bp->mac_addr[2],
5088                             bp->mac_addr[3], bp->mac_addr[4], bp->mac_addr[5]);
5089
5090                 rc = bnxt_hwrm_set_mac(bp);
5091                 if (rc)
5092                         return rc;
5093         }
5094
5095         /* Copy the permanent MAC from the FUNC_QCAPS response */
5096         memcpy(&eth_dev->data->mac_addrs[0], bp->mac_addr, RTE_ETHER_ADDR_LEN);
5097
5098         return rc;
5099 }
5100
5101 static int bnxt_restore_dflt_mac(struct bnxt *bp)
5102 {
5103         int rc = 0;
5104
5105         /* MAC is already configured in FW */
5106         if (BNXT_HAS_DFLT_MAC_SET(bp))
5107                 return 0;
5108
5109         /* Restore the old MAC configured */
5110         rc = bnxt_hwrm_set_mac(bp);
5111         if (rc)
5112                 PMD_DRV_LOG(ERR, "Failed to restore MAC address\n");
5113
5114         return rc;
5115 }
5116
5117 static void bnxt_config_vf_req_fwd(struct bnxt *bp)
5118 {
5119         if (!BNXT_PF(bp))
5120                 return;
5121
5122 #define ALLOW_FUNC(x)   \
5123         { \
5124                 uint32_t arg = (x); \
5125                 bp->pf->vf_req_fwd[((arg) >> 5)] &= \
5126                 ~rte_cpu_to_le_32(1 << ((arg) & 0x1f)); \
5127         }
5128
5129         /* Forward all requests if firmware is new enough */
5130         if (((bp->fw_ver >= ((20 << 24) | (6 << 16) | (100 << 8))) &&
5131              (bp->fw_ver < ((20 << 24) | (7 << 16)))) ||
5132             ((bp->fw_ver >= ((20 << 24) | (8 << 16))))) {
5133                 memset(bp->pf->vf_req_fwd, 0xff, sizeof(bp->pf->vf_req_fwd));
5134         } else {
5135                 PMD_DRV_LOG(WARNING,
5136                             "Firmware too old for VF mailbox functionality\n");
5137                 memset(bp->pf->vf_req_fwd, 0, sizeof(bp->pf->vf_req_fwd));
5138         }
5139
5140         /*
5141          * The following are used for driver cleanup. If we disallow these,
5142          * VF drivers can't clean up cleanly.
5143          */
5144         ALLOW_FUNC(HWRM_FUNC_DRV_UNRGTR);
5145         ALLOW_FUNC(HWRM_VNIC_FREE);
5146         ALLOW_FUNC(HWRM_RING_FREE);
5147         ALLOW_FUNC(HWRM_RING_GRP_FREE);
5148         ALLOW_FUNC(HWRM_VNIC_RSS_COS_LB_CTX_FREE);
5149         ALLOW_FUNC(HWRM_CFA_L2_FILTER_FREE);
5150         ALLOW_FUNC(HWRM_STAT_CTX_FREE);
5151         ALLOW_FUNC(HWRM_PORT_PHY_QCFG);
5152         ALLOW_FUNC(HWRM_VNIC_TPA_CFG);
5153 }
5154
5155 uint16_t
5156 bnxt_get_svif(uint16_t port_id, bool func_svif,
5157               enum bnxt_ulp_intf_type type)
5158 {
5159         struct rte_eth_dev *eth_dev;
5160         struct bnxt *bp;
5161
5162         eth_dev = &rte_eth_devices[port_id];
5163         if (BNXT_ETH_DEV_IS_REPRESENTOR(eth_dev)) {
5164                 struct bnxt_vf_representor *vfr = eth_dev->data->dev_private;
5165                 if (!vfr)
5166                         return 0;
5167
5168                 if (type == BNXT_ULP_INTF_TYPE_VF_REP)
5169                         return vfr->svif;
5170
5171                 eth_dev = vfr->parent_dev;
5172         }
5173
5174         bp = eth_dev->data->dev_private;
5175
5176         return func_svif ? bp->func_svif : bp->port_svif;
5177 }
5178
5179 uint16_t
5180 bnxt_get_vnic_id(uint16_t port, enum bnxt_ulp_intf_type type)
5181 {
5182         struct rte_eth_dev *eth_dev;
5183         struct bnxt_vnic_info *vnic;
5184         struct bnxt *bp;
5185
5186         eth_dev = &rte_eth_devices[port];
5187         if (BNXT_ETH_DEV_IS_REPRESENTOR(eth_dev)) {
5188                 struct bnxt_vf_representor *vfr = eth_dev->data->dev_private;
5189                 if (!vfr)
5190                         return 0;
5191
5192                 if (type == BNXT_ULP_INTF_TYPE_VF_REP)
5193                         return vfr->dflt_vnic_id;
5194
5195                 eth_dev = vfr->parent_dev;
5196         }
5197
5198         bp = eth_dev->data->dev_private;
5199
5200         vnic = BNXT_GET_DEFAULT_VNIC(bp);
5201
5202         return vnic->fw_vnic_id;
5203 }
5204
5205 uint16_t
5206 bnxt_get_fw_func_id(uint16_t port, enum bnxt_ulp_intf_type type)
5207 {
5208         struct rte_eth_dev *eth_dev;
5209         struct bnxt *bp;
5210
5211         eth_dev = &rte_eth_devices[port];
5212         if (BNXT_ETH_DEV_IS_REPRESENTOR(eth_dev)) {
5213                 struct bnxt_vf_representor *vfr = eth_dev->data->dev_private;
5214                 if (!vfr)
5215                         return 0;
5216
5217                 if (type == BNXT_ULP_INTF_TYPE_VF_REP)
5218                         return vfr->fw_fid;
5219
5220                 eth_dev = vfr->parent_dev;
5221         }
5222
5223         bp = eth_dev->data->dev_private;
5224
5225         return bp->fw_fid;
5226 }
5227
5228 enum bnxt_ulp_intf_type
5229 bnxt_get_interface_type(uint16_t port)
5230 {
5231         struct rte_eth_dev *eth_dev;
5232         struct bnxt *bp;
5233
5234         eth_dev = &rte_eth_devices[port];
5235         if (BNXT_ETH_DEV_IS_REPRESENTOR(eth_dev))
5236                 return BNXT_ULP_INTF_TYPE_VF_REP;
5237
5238         bp = eth_dev->data->dev_private;
5239         if (BNXT_PF(bp))
5240                 return BNXT_ULP_INTF_TYPE_PF;
5241         else if (BNXT_VF_IS_TRUSTED(bp))
5242                 return BNXT_ULP_INTF_TYPE_TRUSTED_VF;
5243         else if (BNXT_VF(bp))
5244                 return BNXT_ULP_INTF_TYPE_VF;
5245
5246         return BNXT_ULP_INTF_TYPE_INVALID;
5247 }
5248
5249 uint16_t
5250 bnxt_get_phy_port_id(uint16_t port_id)
5251 {
5252         struct bnxt_vf_representor *vfr;
5253         struct rte_eth_dev *eth_dev;
5254         struct bnxt *bp;
5255
5256         eth_dev = &rte_eth_devices[port_id];
5257         if (BNXT_ETH_DEV_IS_REPRESENTOR(eth_dev)) {
5258                 vfr = eth_dev->data->dev_private;
5259                 if (!vfr)
5260                         return 0;
5261
5262                 eth_dev = vfr->parent_dev;
5263         }
5264
5265         bp = eth_dev->data->dev_private;
5266
5267         return BNXT_PF(bp) ? bp->pf->port_id : bp->parent->port_id;
5268 }
5269
5270 uint16_t
5271 bnxt_get_parif(uint16_t port_id, enum bnxt_ulp_intf_type type)
5272 {
5273         struct rte_eth_dev *eth_dev;
5274         struct bnxt *bp;
5275
5276         eth_dev = &rte_eth_devices[port_id];
5277         if (BNXT_ETH_DEV_IS_REPRESENTOR(eth_dev)) {
5278                 struct bnxt_vf_representor *vfr = eth_dev->data->dev_private;
5279                 if (!vfr)
5280                         return 0;
5281
5282                 if (type == BNXT_ULP_INTF_TYPE_VF_REP)
5283                         return vfr->fw_fid - 1;
5284
5285                 eth_dev = vfr->parent_dev;
5286         }
5287
5288         bp = eth_dev->data->dev_private;
5289
5290         return BNXT_PF(bp) ? bp->fw_fid - 1 : bp->parent->fid - 1;
5291 }
5292
5293 uint16_t
5294 bnxt_get_vport(uint16_t port_id)
5295 {
5296         return (1 << bnxt_get_phy_port_id(port_id));
5297 }
5298
5299 static void bnxt_alloc_error_recovery_info(struct bnxt *bp)
5300 {
5301         struct bnxt_error_recovery_info *info = bp->recovery_info;
5302
5303         if (info) {
5304                 if (!(bp->fw_cap & BNXT_FW_CAP_HCOMM_FW_STATUS))
5305                         memset(info, 0, sizeof(*info));
5306                 return;
5307         }
5308
5309         if (!(bp->fw_cap & BNXT_FW_CAP_ERROR_RECOVERY))
5310                 return;
5311
5312         info = rte_zmalloc("bnxt_hwrm_error_recovery_qcfg",
5313                            sizeof(*info), 0);
5314         if (!info)
5315                 bp->fw_cap &= ~BNXT_FW_CAP_ERROR_RECOVERY;
5316
5317         bp->recovery_info = info;
5318 }
5319
5320 static void bnxt_check_fw_status(struct bnxt *bp)
5321 {
5322         uint32_t fw_status;
5323
5324         if (!(bp->recovery_info &&
5325               (bp->fw_cap & BNXT_FW_CAP_HCOMM_FW_STATUS)))
5326                 return;
5327
5328         fw_status = bnxt_read_fw_status_reg(bp, BNXT_FW_STATUS_REG);
5329         if (fw_status != BNXT_FW_STATUS_HEALTHY)
5330                 PMD_DRV_LOG(ERR, "Firmware not responding, status: %#x\n",
5331                             fw_status);
5332 }
5333
5334 static int bnxt_map_hcomm_fw_status_reg(struct bnxt *bp)
5335 {
5336         struct bnxt_error_recovery_info *info = bp->recovery_info;
5337         uint32_t status_loc;
5338         uint32_t sig_ver;
5339
5340         rte_write32(HCOMM_STATUS_STRUCT_LOC, (uint8_t *)bp->bar0 +
5341                     BNXT_GRCPF_REG_WINDOW_BASE_OUT + 4);
5342         sig_ver = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
5343                                    BNXT_GRCP_WINDOW_2_BASE +
5344                                    offsetof(struct hcomm_status,
5345                                             sig_ver)));
5346         /* If the signature is absent, then FW does not support this feature */
5347         if ((sig_ver & HCOMM_STATUS_SIGNATURE_MASK) !=
5348             HCOMM_STATUS_SIGNATURE_VAL)
5349                 return 0;
5350
5351         if (!info) {
5352                 info = rte_zmalloc("bnxt_hwrm_error_recovery_qcfg",
5353                                    sizeof(*info), 0);
5354                 if (!info)
5355                         return -ENOMEM;
5356                 bp->recovery_info = info;
5357         } else {
5358                 memset(info, 0, sizeof(*info));
5359         }
5360
5361         status_loc = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
5362                                       BNXT_GRCP_WINDOW_2_BASE +
5363                                       offsetof(struct hcomm_status,
5364                                                fw_status_loc)));
5365
5366         /* Only pre-map the FW health status GRC register */
5367         if (BNXT_FW_STATUS_REG_TYPE(status_loc) != BNXT_FW_STATUS_REG_TYPE_GRC)
5368                 return 0;
5369
5370         info->status_regs[BNXT_FW_STATUS_REG] = status_loc;
5371         info->mapped_status_regs[BNXT_FW_STATUS_REG] =
5372                 BNXT_GRCP_WINDOW_2_BASE + (status_loc & BNXT_GRCP_OFFSET_MASK);
5373
5374         rte_write32((status_loc & BNXT_GRCP_BASE_MASK), (uint8_t *)bp->bar0 +
5375                     BNXT_GRCPF_REG_WINDOW_BASE_OUT + 4);
5376
5377         bp->fw_cap |= BNXT_FW_CAP_HCOMM_FW_STATUS;
5378
5379         return 0;
5380 }
5381
5382 static int bnxt_init_fw(struct bnxt *bp)
5383 {
5384         uint16_t mtu;
5385         int rc = 0;
5386
5387         bp->fw_cap = 0;
5388
5389         rc = bnxt_map_hcomm_fw_status_reg(bp);
5390         if (rc)
5391                 return rc;
5392
5393         rc = bnxt_hwrm_ver_get(bp, DFLT_HWRM_CMD_TIMEOUT);
5394         if (rc) {
5395                 bnxt_check_fw_status(bp);
5396                 return rc;
5397         }
5398
5399         rc = bnxt_hwrm_func_reset(bp);
5400         if (rc)
5401                 return -EIO;
5402
5403         rc = bnxt_hwrm_vnic_qcaps(bp);
5404         if (rc)
5405                 return rc;
5406
5407         rc = bnxt_hwrm_queue_qportcfg(bp);
5408         if (rc)
5409                 return rc;
5410
5411         /* Get the MAX capabilities for this function.
5412          * This function also allocates context memory for TQM rings and
5413          * informs the firmware about this allocated backing store memory.
5414          */
5415         rc = bnxt_hwrm_func_qcaps(bp);
5416         if (rc)
5417                 return rc;
5418
5419         rc = bnxt_hwrm_func_qcfg(bp, &mtu);
5420         if (rc)
5421                 return rc;
5422
5423         bnxt_hwrm_port_mac_qcfg(bp);
5424
5425         bnxt_hwrm_parent_pf_qcfg(bp);
5426
5427         bnxt_hwrm_port_phy_qcaps(bp);
5428
5429         bnxt_alloc_error_recovery_info(bp);
5430         /* Get the adapter error recovery support info */
5431         rc = bnxt_hwrm_error_recovery_qcfg(bp);
5432         if (rc)
5433                 bp->fw_cap &= ~BNXT_FW_CAP_ERROR_RECOVERY;
5434
5435         bnxt_hwrm_port_led_qcaps(bp);
5436
5437         return 0;
5438 }
5439
5440 static int
5441 bnxt_init_locks(struct bnxt *bp)
5442 {
5443         int err;
5444
5445         err = pthread_mutex_init(&bp->flow_lock, NULL);
5446         if (err) {
5447                 PMD_DRV_LOG(ERR, "Unable to initialize flow_lock\n");
5448                 return err;
5449         }
5450
5451         err = pthread_mutex_init(&bp->def_cp_lock, NULL);
5452         if (err)
5453                 PMD_DRV_LOG(ERR, "Unable to initialize def_cp_lock\n");
5454         return err;
5455 }
5456
5457 static int bnxt_init_resources(struct bnxt *bp, bool reconfig_dev)
5458 {
5459         int rc = 0;
5460
5461         rc = bnxt_init_fw(bp);
5462         if (rc)
5463                 return rc;
5464
5465         if (!reconfig_dev) {
5466                 rc = bnxt_setup_mac_addr(bp->eth_dev);
5467                 if (rc)
5468                         return rc;
5469         } else {
5470                 rc = bnxt_restore_dflt_mac(bp);
5471                 if (rc)
5472                         return rc;
5473         }
5474
5475         bnxt_config_vf_req_fwd(bp);
5476
5477         rc = bnxt_hwrm_func_driver_register(bp);
5478         if (rc) {
5479                 PMD_DRV_LOG(ERR, "Failed to register driver");
5480                 return -EBUSY;
5481         }
5482
5483         if (BNXT_PF(bp)) {
5484                 if (bp->pdev->max_vfs) {
5485                         rc = bnxt_hwrm_allocate_vfs(bp, bp->pdev->max_vfs);
5486                         if (rc) {
5487                                 PMD_DRV_LOG(ERR, "Failed to allocate VFs\n");
5488                                 return rc;
5489                         }
5490                 } else {
5491                         rc = bnxt_hwrm_allocate_pf_only(bp);
5492                         if (rc) {
5493                                 PMD_DRV_LOG(ERR,
5494                                             "Failed to allocate PF resources");
5495                                 return rc;
5496                         }
5497                 }
5498         }
5499
5500         rc = bnxt_alloc_mem(bp, reconfig_dev);
5501         if (rc)
5502                 return rc;
5503
5504         rc = bnxt_setup_int(bp);
5505         if (rc)
5506                 return rc;
5507
5508         rc = bnxt_request_int(bp);
5509         if (rc)
5510                 return rc;
5511
5512         rc = bnxt_init_ctx_mem(bp);
5513         if (rc) {
5514                 PMD_DRV_LOG(ERR, "Failed to init adv_flow_counters\n");
5515                 return rc;
5516         }
5517
5518         rc = bnxt_init_locks(bp);
5519         if (rc)
5520                 return rc;
5521
5522         return 0;
5523 }
5524
5525 static int
5526 bnxt_parse_devarg_truflow(__rte_unused const char *key,
5527                           const char *value, void *opaque_arg)
5528 {
5529         struct bnxt *bp = opaque_arg;
5530         unsigned long truflow;
5531         char *end = NULL;
5532
5533         if (!value || !opaque_arg) {
5534                 PMD_DRV_LOG(ERR,
5535                             "Invalid parameter passed to truflow devargs.\n");
5536                 return -EINVAL;
5537         }
5538
5539         truflow = strtoul(value, &end, 10);
5540         if (end == NULL || *end != '\0' ||
5541             (truflow == ULONG_MAX && errno == ERANGE)) {
5542                 PMD_DRV_LOG(ERR,
5543                             "Invalid parameter passed to truflow devargs.\n");
5544                 return -EINVAL;
5545         }
5546
5547         if (BNXT_DEVARG_TRUFLOW_INVALID(truflow)) {
5548                 PMD_DRV_LOG(ERR,
5549                             "Invalid value passed to truflow devargs.\n");
5550                 return -EINVAL;
5551         }
5552
5553         bp->flags |= BNXT_FLAG_TRUFLOW_EN;
5554         if (BNXT_TRUFLOW_EN(bp))
5555                 PMD_DRV_LOG(INFO, "Host-based truflow feature enabled.\n");
5556
5557         return 0;
5558 }
5559
5560 static int
5561 bnxt_parse_devarg_flow_xstat(__rte_unused const char *key,
5562                              const char *value, void *opaque_arg)
5563 {
5564         struct bnxt *bp = opaque_arg;
5565         unsigned long flow_xstat;
5566         char *end = NULL;
5567
5568         if (!value || !opaque_arg) {
5569                 PMD_DRV_LOG(ERR,
5570                             "Invalid parameter passed to flow_xstat devarg.\n");
5571                 return -EINVAL;
5572         }
5573
5574         flow_xstat = strtoul(value, &end, 10);
5575         if (end == NULL || *end != '\0' ||
5576             (flow_xstat == ULONG_MAX && errno == ERANGE)) {
5577                 PMD_DRV_LOG(ERR,
5578                             "Invalid parameter passed to flow_xstat devarg.\n");
5579                 return -EINVAL;
5580         }
5581
5582         if (BNXT_DEVARG_FLOW_XSTAT_INVALID(flow_xstat)) {
5583                 PMD_DRV_LOG(ERR,
5584                             "Invalid value passed to flow_xstat devarg.\n");
5585                 return -EINVAL;
5586         }
5587
5588         bp->flags |= BNXT_FLAG_FLOW_XSTATS_EN;
5589         if (BNXT_FLOW_XSTATS_EN(bp))
5590                 PMD_DRV_LOG(INFO, "flow_xstat feature enabled.\n");
5591
5592         return 0;
5593 }
5594
5595 static int
5596 bnxt_parse_devarg_max_num_kflows(__rte_unused const char *key,
5597                                         const char *value, void *opaque_arg)
5598 {
5599         struct bnxt *bp = opaque_arg;
5600         unsigned long max_num_kflows;
5601         char *end = NULL;
5602
5603         if (!value || !opaque_arg) {
5604                 PMD_DRV_LOG(ERR,
5605                         "Invalid parameter passed to max_num_kflows devarg.\n");
5606                 return -EINVAL;
5607         }
5608
5609         max_num_kflows = strtoul(value, &end, 10);
5610         if (end == NULL || *end != '\0' ||
5611                 (max_num_kflows == ULONG_MAX && errno == ERANGE)) {
5612                 PMD_DRV_LOG(ERR,
5613                         "Invalid parameter passed to max_num_kflows devarg.\n");
5614                 return -EINVAL;
5615         }
5616
5617         if (bnxt_devarg_max_num_kflow_invalid(max_num_kflows)) {
5618                 PMD_DRV_LOG(ERR,
5619                         "Invalid value passed to max_num_kflows devarg.\n");
5620                 return -EINVAL;
5621         }
5622
5623         bp->max_num_kflows = max_num_kflows;
5624         if (bp->max_num_kflows)
5625                 PMD_DRV_LOG(INFO, "max_num_kflows set as %ldK.\n",
5626                                 max_num_kflows);
5627
5628         return 0;
5629 }
5630
5631 static void
5632 bnxt_parse_dev_args(struct bnxt *bp, struct rte_devargs *devargs)
5633 {
5634         struct rte_kvargs *kvlist;
5635
5636         if (devargs == NULL)
5637                 return;
5638
5639         kvlist = rte_kvargs_parse(devargs->args, bnxt_dev_args);
5640         if (kvlist == NULL)
5641                 return;
5642
5643         /*
5644          * Handler for "truflow" devarg.
5645          * Invoked as for ex: "-w 0000:00:0d.0,host-based-truflow=1"
5646          */
5647         rte_kvargs_process(kvlist, BNXT_DEVARG_TRUFLOW,
5648                            bnxt_parse_devarg_truflow, bp);
5649
5650         /*
5651          * Handler for "flow_xstat" devarg.
5652          * Invoked as for ex: "-w 0000:00:0d.0,flow_xstat=1"
5653          */
5654         rte_kvargs_process(kvlist, BNXT_DEVARG_FLOW_XSTAT,
5655                            bnxt_parse_devarg_flow_xstat, bp);
5656
5657         /*
5658          * Handler for "max_num_kflows" devarg.
5659          * Invoked as for ex: "-w 000:00:0d.0,max_num_kflows=32"
5660          */
5661         rte_kvargs_process(kvlist, BNXT_DEVARG_MAX_NUM_KFLOWS,
5662                            bnxt_parse_devarg_max_num_kflows, bp);
5663
5664         rte_kvargs_free(kvlist);
5665 }
5666
5667 static int bnxt_alloc_switch_domain(struct bnxt *bp)
5668 {
5669         int rc = 0;
5670
5671         if (BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp)) {
5672                 rc = rte_eth_switch_domain_alloc(&bp->switch_domain_id);
5673                 if (rc)
5674                         PMD_DRV_LOG(ERR,
5675                                     "Failed to alloc switch domain: %d\n", rc);
5676                 else
5677                         PMD_DRV_LOG(INFO,
5678                                     "Switch domain allocated %d\n",
5679                                     bp->switch_domain_id);
5680         }
5681
5682         return rc;
5683 }
5684
5685 static int
5686 bnxt_dev_init(struct rte_eth_dev *eth_dev, void *params __rte_unused)
5687 {
5688         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
5689         static int version_printed;
5690         struct bnxt *bp;
5691         int rc;
5692
5693         if (version_printed++ == 0)
5694                 PMD_DRV_LOG(INFO, "%s\n", bnxt_version);
5695
5696         eth_dev->dev_ops = &bnxt_dev_ops;
5697         eth_dev->rx_queue_count = bnxt_rx_queue_count_op;
5698         eth_dev->rx_descriptor_status = bnxt_rx_descriptor_status_op;
5699         eth_dev->tx_descriptor_status = bnxt_tx_descriptor_status_op;
5700         eth_dev->rx_pkt_burst = &bnxt_recv_pkts;
5701         eth_dev->tx_pkt_burst = &bnxt_xmit_pkts;
5702
5703         /*
5704          * For secondary processes, we don't initialise any further
5705          * as primary has already done this work.
5706          */
5707         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
5708                 return 0;
5709
5710         rte_eth_copy_pci_info(eth_dev, pci_dev);
5711
5712         bp = eth_dev->data->dev_private;
5713
5714         /* Parse dev arguments passed on when starting the DPDK application. */
5715         bnxt_parse_dev_args(bp, pci_dev->device.devargs);
5716
5717         bp->flags &= ~BNXT_FLAG_RX_VECTOR_PKT_MODE;
5718
5719         if (bnxt_vf_pciid(pci_dev->id.device_id))
5720                 bp->flags |= BNXT_FLAG_VF;
5721
5722         if (bnxt_thor_device(pci_dev->id.device_id))
5723                 bp->flags |= BNXT_FLAG_THOR_CHIP;
5724
5725         if (pci_dev->id.device_id == BROADCOM_DEV_ID_58802 ||
5726             pci_dev->id.device_id == BROADCOM_DEV_ID_58804 ||
5727             pci_dev->id.device_id == BROADCOM_DEV_ID_58808 ||
5728             pci_dev->id.device_id == BROADCOM_DEV_ID_58802_VF)
5729                 bp->flags |= BNXT_FLAG_STINGRAY;
5730
5731         rc = bnxt_init_board(eth_dev);
5732         if (rc) {
5733                 PMD_DRV_LOG(ERR,
5734                             "Failed to initialize board rc: %x\n", rc);
5735                 return rc;
5736         }
5737
5738         rc = bnxt_alloc_pf_info(bp);
5739         if (rc)
5740                 goto error_free;
5741
5742         rc = bnxt_alloc_link_info(bp);
5743         if (rc)
5744                 goto error_free;
5745
5746         rc = bnxt_alloc_parent_info(bp);
5747         if (rc)
5748                 goto error_free;
5749
5750         rc = bnxt_alloc_hwrm_resources(bp);
5751         if (rc) {
5752                 PMD_DRV_LOG(ERR,
5753                             "Failed to allocate hwrm resource rc: %x\n", rc);
5754                 goto error_free;
5755         }
5756         rc = bnxt_alloc_leds_info(bp);
5757         if (rc)
5758                 goto error_free;
5759
5760         rc = bnxt_alloc_cos_queues(bp);
5761         if (rc)
5762                 goto error_free;
5763
5764         rc = bnxt_init_resources(bp, false);
5765         if (rc)
5766                 goto error_free;
5767
5768         rc = bnxt_alloc_stats_mem(bp);
5769         if (rc)
5770                 goto error_free;
5771
5772         bnxt_alloc_switch_domain(bp);
5773
5774         /* Pass the information to the rte_eth_dev_close() that it should also
5775          * release the private port resources.
5776          */
5777         eth_dev->data->dev_flags |= RTE_ETH_DEV_CLOSE_REMOVE;
5778
5779         PMD_DRV_LOG(INFO,
5780                     DRV_MODULE_NAME "found at mem %" PRIX64 ", node addr %pM\n",
5781                     pci_dev->mem_resource[0].phys_addr,
5782                     pci_dev->mem_resource[0].addr);
5783
5784         return 0;
5785
5786 error_free:
5787         bnxt_dev_uninit(eth_dev);
5788         return rc;
5789 }
5790
5791
5792 static void bnxt_free_ctx_mem_buf(struct bnxt_ctx_mem_buf_info *ctx)
5793 {
5794         if (!ctx)
5795                 return;
5796
5797         if (ctx->va)
5798                 rte_free(ctx->va);
5799
5800         ctx->va = NULL;
5801         ctx->dma = RTE_BAD_IOVA;
5802         ctx->ctx_id = BNXT_CTX_VAL_INVAL;
5803 }
5804
5805 static void bnxt_unregister_fc_ctx_mem(struct bnxt *bp)
5806 {
5807         bnxt_hwrm_cfa_counter_cfg(bp, BNXT_DIR_RX,
5808                                   CFA_COUNTER_CFG_IN_COUNTER_TYPE_FC,
5809                                   bp->flow_stat->rx_fc_out_tbl.ctx_id,
5810                                   bp->flow_stat->max_fc,
5811                                   false);
5812
5813         bnxt_hwrm_cfa_counter_cfg(bp, BNXT_DIR_TX,
5814                                   CFA_COUNTER_CFG_IN_COUNTER_TYPE_FC,
5815                                   bp->flow_stat->tx_fc_out_tbl.ctx_id,
5816                                   bp->flow_stat->max_fc,
5817                                   false);
5818
5819         if (bp->flow_stat->rx_fc_in_tbl.ctx_id != BNXT_CTX_VAL_INVAL)
5820                 bnxt_hwrm_ctx_unrgtr(bp, bp->flow_stat->rx_fc_in_tbl.ctx_id);
5821         bp->flow_stat->rx_fc_in_tbl.ctx_id = BNXT_CTX_VAL_INVAL;
5822
5823         if (bp->flow_stat->rx_fc_out_tbl.ctx_id != BNXT_CTX_VAL_INVAL)
5824                 bnxt_hwrm_ctx_unrgtr(bp, bp->flow_stat->rx_fc_out_tbl.ctx_id);
5825         bp->flow_stat->rx_fc_out_tbl.ctx_id = BNXT_CTX_VAL_INVAL;
5826
5827         if (bp->flow_stat->tx_fc_in_tbl.ctx_id != BNXT_CTX_VAL_INVAL)
5828                 bnxt_hwrm_ctx_unrgtr(bp, bp->flow_stat->tx_fc_in_tbl.ctx_id);
5829         bp->flow_stat->tx_fc_in_tbl.ctx_id = BNXT_CTX_VAL_INVAL;
5830
5831         if (bp->flow_stat->tx_fc_out_tbl.ctx_id != BNXT_CTX_VAL_INVAL)
5832                 bnxt_hwrm_ctx_unrgtr(bp, bp->flow_stat->tx_fc_out_tbl.ctx_id);
5833         bp->flow_stat->tx_fc_out_tbl.ctx_id = BNXT_CTX_VAL_INVAL;
5834 }
5835
5836 static void bnxt_uninit_fc_ctx_mem(struct bnxt *bp)
5837 {
5838         bnxt_unregister_fc_ctx_mem(bp);
5839
5840         bnxt_free_ctx_mem_buf(&bp->flow_stat->rx_fc_in_tbl);
5841         bnxt_free_ctx_mem_buf(&bp->flow_stat->rx_fc_out_tbl);
5842         bnxt_free_ctx_mem_buf(&bp->flow_stat->tx_fc_in_tbl);
5843         bnxt_free_ctx_mem_buf(&bp->flow_stat->tx_fc_out_tbl);
5844 }
5845
5846 static void bnxt_uninit_ctx_mem(struct bnxt *bp)
5847 {
5848         if (BNXT_FLOW_XSTATS_EN(bp))
5849                 bnxt_uninit_fc_ctx_mem(bp);
5850 }
5851
5852 static void
5853 bnxt_free_error_recovery_info(struct bnxt *bp)
5854 {
5855         rte_free(bp->recovery_info);
5856         bp->recovery_info = NULL;
5857         bp->fw_cap &= ~BNXT_FW_CAP_ERROR_RECOVERY;
5858 }
5859
5860 static void
5861 bnxt_uninit_locks(struct bnxt *bp)
5862 {
5863         pthread_mutex_destroy(&bp->flow_lock);
5864         pthread_mutex_destroy(&bp->def_cp_lock);
5865         if (bp->rep_info) {
5866                 pthread_mutex_destroy(&bp->rep_info->vfr_lock);
5867                 pthread_mutex_destroy(&bp->rep_info->vfr_start_lock);
5868         }
5869 }
5870
5871 static int
5872 bnxt_uninit_resources(struct bnxt *bp, bool reconfig_dev)
5873 {
5874         int rc;
5875
5876         bnxt_free_int(bp);
5877         bnxt_free_mem(bp, reconfig_dev);
5878         bnxt_hwrm_func_buf_unrgtr(bp);
5879         rc = bnxt_hwrm_func_driver_unregister(bp, 0);
5880         bp->flags &= ~BNXT_FLAG_REGISTERED;
5881         bnxt_free_ctx_mem(bp);
5882         if (!reconfig_dev) {
5883                 bnxt_free_hwrm_resources(bp);
5884                 bnxt_free_error_recovery_info(bp);
5885         }
5886
5887         bnxt_uninit_ctx_mem(bp);
5888
5889         bnxt_uninit_locks(bp);
5890         bnxt_free_flow_stats_info(bp);
5891         bnxt_free_rep_info(bp);
5892         rte_free(bp->ptp_cfg);
5893         bp->ptp_cfg = NULL;
5894         return rc;
5895 }
5896
5897 static int
5898 bnxt_dev_uninit(struct rte_eth_dev *eth_dev)
5899 {
5900         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
5901                 return -EPERM;
5902
5903         PMD_DRV_LOG(DEBUG, "Calling Device uninit\n");
5904
5905         if (eth_dev->state != RTE_ETH_DEV_UNUSED)
5906                 bnxt_dev_close_op(eth_dev);
5907
5908         return 0;
5909 }
5910
5911 static int bnxt_pci_remove_dev_with_reps(struct rte_eth_dev *eth_dev)
5912 {
5913         struct bnxt *bp = eth_dev->data->dev_private;
5914         struct rte_eth_dev *vf_rep_eth_dev;
5915         int ret = 0, i;
5916
5917         if (!bp)
5918                 return -EINVAL;
5919
5920         for (i = 0; i < bp->num_reps; i++) {
5921                 vf_rep_eth_dev = bp->rep_info[i].vfr_eth_dev;
5922                 if (!vf_rep_eth_dev)
5923                         continue;
5924                 rte_eth_dev_destroy(vf_rep_eth_dev, bnxt_vf_representor_uninit);
5925         }
5926         ret = rte_eth_dev_destroy(eth_dev, bnxt_dev_uninit);
5927
5928         return ret;
5929 }
5930
5931 static void bnxt_free_rep_info(struct bnxt *bp)
5932 {
5933         rte_free(bp->rep_info);
5934         bp->rep_info = NULL;
5935         rte_free(bp->cfa_code_map);
5936         bp->cfa_code_map = NULL;
5937 }
5938
5939 static int bnxt_init_rep_info(struct bnxt *bp)
5940 {
5941         int i = 0, rc;
5942
5943         if (bp->rep_info)
5944                 return 0;
5945
5946         bp->rep_info = rte_zmalloc("bnxt_rep_info",
5947                                    sizeof(bp->rep_info[0]) * BNXT_MAX_VF_REPS,
5948                                    0);
5949         if (!bp->rep_info) {
5950                 PMD_DRV_LOG(ERR, "Failed to alloc memory for rep info\n");
5951                 return -ENOMEM;
5952         }
5953         bp->cfa_code_map = rte_zmalloc("bnxt_cfa_code_map",
5954                                        sizeof(*bp->cfa_code_map) *
5955                                        BNXT_MAX_CFA_CODE, 0);
5956         if (!bp->cfa_code_map) {
5957                 PMD_DRV_LOG(ERR, "Failed to alloc memory for cfa_code_map\n");
5958                 bnxt_free_rep_info(bp);
5959                 return -ENOMEM;
5960         }
5961
5962         for (i = 0; i < BNXT_MAX_CFA_CODE; i++)
5963                 bp->cfa_code_map[i] = BNXT_VF_IDX_INVALID;
5964
5965         rc = pthread_mutex_init(&bp->rep_info->vfr_lock, NULL);
5966         if (rc) {
5967                 PMD_DRV_LOG(ERR, "Unable to initialize vfr_lock\n");
5968                 bnxt_free_rep_info(bp);
5969                 return rc;
5970         }
5971
5972         rc = pthread_mutex_init(&bp->rep_info->vfr_start_lock, NULL);
5973         if (rc) {
5974                 PMD_DRV_LOG(ERR, "Unable to initialize vfr_start_lock\n");
5975                 bnxt_free_rep_info(bp);
5976                 return rc;
5977         }
5978
5979         return rc;
5980 }
5981
5982 static int bnxt_rep_port_probe(struct rte_pci_device *pci_dev,
5983                                struct rte_eth_devargs eth_da,
5984                                struct rte_eth_dev *backing_eth_dev)
5985 {
5986         struct rte_eth_dev *vf_rep_eth_dev;
5987         char name[RTE_ETH_NAME_MAX_LEN];
5988         struct bnxt *backing_bp;
5989         uint16_t num_rep;
5990         int i, ret = 0;
5991
5992         num_rep = eth_da.nb_representor_ports;
5993         if (num_rep > BNXT_MAX_VF_REPS) {
5994                 PMD_DRV_LOG(ERR, "nb_representor_ports = %d > %d MAX VF REPS\n",
5995                             num_rep, BNXT_MAX_VF_REPS);
5996                 return -EINVAL;
5997         }
5998
5999         if (num_rep > RTE_MAX_ETHPORTS) {
6000                 PMD_DRV_LOG(ERR,
6001                             "nb_representor_ports = %d > %d MAX ETHPORTS\n",
6002                             num_rep, RTE_MAX_ETHPORTS);
6003                 return -EINVAL;
6004         }
6005
6006         backing_bp = backing_eth_dev->data->dev_private;
6007
6008         if (!(BNXT_PF(backing_bp) || BNXT_VF_IS_TRUSTED(backing_bp))) {
6009                 PMD_DRV_LOG(ERR,
6010                             "Not a PF or trusted VF. No Representor support\n");
6011                 /* Returning an error is not an option.
6012                  * Applications are not handling this correctly
6013                  */
6014                 return 0;
6015         }
6016
6017         if (bnxt_init_rep_info(backing_bp))
6018                 return 0;
6019
6020         for (i = 0; i < num_rep; i++) {
6021                 struct bnxt_vf_representor representor = {
6022                         .vf_id = eth_da.representor_ports[i],
6023                         .switch_domain_id = backing_bp->switch_domain_id,
6024                         .parent_dev = backing_eth_dev
6025                 };
6026
6027                 if (representor.vf_id >= BNXT_MAX_VF_REPS) {
6028                         PMD_DRV_LOG(ERR, "VF-Rep id %d >= %d MAX VF ID\n",
6029                                     representor.vf_id, BNXT_MAX_VF_REPS);
6030                         continue;
6031                 }
6032
6033                 /* representor port net_bdf_port */
6034                 snprintf(name, sizeof(name), "net_%s_representor_%d",
6035                          pci_dev->device.name, eth_da.representor_ports[i]);
6036
6037                 ret = rte_eth_dev_create(&pci_dev->device, name,
6038                                          sizeof(struct bnxt_vf_representor),
6039                                          NULL, NULL,
6040                                          bnxt_vf_representor_init,
6041                                          &representor);
6042
6043                 if (!ret) {
6044                         vf_rep_eth_dev = rte_eth_dev_allocated(name);
6045                         if (!vf_rep_eth_dev) {
6046                                 PMD_DRV_LOG(ERR, "Failed to find the eth_dev"
6047                                             " for VF-Rep: %s.", name);
6048                                 bnxt_pci_remove_dev_with_reps(backing_eth_dev);
6049                                 ret = -ENODEV;
6050                                 return ret;
6051                         }
6052                         backing_bp->rep_info[representor.vf_id].vfr_eth_dev =
6053                                 vf_rep_eth_dev;
6054                         backing_bp->num_reps++;
6055                 } else {
6056                         PMD_DRV_LOG(ERR, "failed to create bnxt vf "
6057                                     "representor %s.", name);
6058                         bnxt_pci_remove_dev_with_reps(backing_eth_dev);
6059                 }
6060         }
6061
6062         return ret;
6063 }
6064
6065 static int bnxt_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
6066                           struct rte_pci_device *pci_dev)
6067 {
6068         struct rte_eth_devargs eth_da = { .nb_representor_ports = 0 };
6069         struct rte_eth_dev *backing_eth_dev;
6070         uint16_t num_rep;
6071         int ret = 0;
6072
6073         if (pci_dev->device.devargs) {
6074                 ret = rte_eth_devargs_parse(pci_dev->device.devargs->args,
6075                                             &eth_da);
6076                 if (ret)
6077                         return ret;
6078         }
6079
6080         num_rep = eth_da.nb_representor_ports;
6081         PMD_DRV_LOG(DEBUG, "nb_representor_ports = %d\n",
6082                     num_rep);
6083
6084         /* We could come here after first level of probe is already invoked
6085          * as part of an application bringup(OVS-DPDK vswitchd), so first check
6086          * for already allocated eth_dev for the backing device (PF/Trusted VF)
6087          */
6088         backing_eth_dev = rte_eth_dev_allocated(pci_dev->device.name);
6089         if (backing_eth_dev == NULL) {
6090                 ret = rte_eth_dev_create(&pci_dev->device, pci_dev->device.name,
6091                                          sizeof(struct bnxt),
6092                                          eth_dev_pci_specific_init, pci_dev,
6093                                          bnxt_dev_init, NULL);
6094
6095                 if (ret || !num_rep)
6096                         return ret;
6097
6098                 backing_eth_dev = rte_eth_dev_allocated(pci_dev->device.name);
6099         }
6100
6101         /* probe representor ports now */
6102         ret = bnxt_rep_port_probe(pci_dev, eth_da, backing_eth_dev);
6103
6104         return ret;
6105 }
6106
6107 static int bnxt_pci_remove(struct rte_pci_device *pci_dev)
6108 {
6109         struct rte_eth_dev *eth_dev;
6110
6111         eth_dev = rte_eth_dev_allocated(pci_dev->device.name);
6112         if (!eth_dev)
6113                 return 0; /* Invoked typically only by OVS-DPDK, by the
6114                            * time it comes here the eth_dev is already
6115                            * deleted by rte_eth_dev_close(), so returning
6116                            * +ve value will at least help in proper cleanup
6117                            */
6118
6119         if (rte_eal_process_type() == RTE_PROC_PRIMARY) {
6120                 if (eth_dev->data->dev_flags & RTE_ETH_DEV_REPRESENTOR)
6121                         return rte_eth_dev_destroy(eth_dev,
6122                                                    bnxt_vf_representor_uninit);
6123                 else
6124                         return rte_eth_dev_destroy(eth_dev,
6125                                                    bnxt_dev_uninit);
6126         } else {
6127                 return rte_eth_dev_pci_generic_remove(pci_dev, NULL);
6128         }
6129 }
6130
6131 static struct rte_pci_driver bnxt_rte_pmd = {
6132         .id_table = bnxt_pci_id_map,
6133         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC |
6134                         RTE_PCI_DRV_PROBE_AGAIN, /* Needed in case of VF-REPs
6135                                                   * and OVS-DPDK
6136                                                   */
6137         .probe = bnxt_pci_probe,
6138         .remove = bnxt_pci_remove,
6139 };
6140
6141 static bool
6142 is_device_supported(struct rte_eth_dev *dev, struct rte_pci_driver *drv)
6143 {
6144         if (strcmp(dev->device->driver->name, drv->driver.name))
6145                 return false;
6146
6147         return true;
6148 }
6149
6150 bool is_bnxt_supported(struct rte_eth_dev *dev)
6151 {
6152         return is_device_supported(dev, &bnxt_rte_pmd);
6153 }
6154
6155 RTE_LOG_REGISTER(bnxt_logtype_driver, pmd.net.bnxt.driver, NOTICE);
6156 RTE_PMD_REGISTER_PCI(net_bnxt, bnxt_rte_pmd);
6157 RTE_PMD_REGISTER_PCI_TABLE(net_bnxt, bnxt_pci_id_map);
6158 RTE_PMD_REGISTER_KMOD_DEP(net_bnxt, "* igb_uio | uio_pci_generic | vfio-pci");