drivers/net/bnxt/bnxt_ethdev.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2014-2021 Broadcom
   3  * All rights reserved.
   4  */
   5
   6 #include <inttypes.h>
   7 #include <stdbool.h>
   8
   9 #include <rte_dev.h>
  10 #include <ethdev_driver.h>
  11 #include <ethdev_pci.h>
  12 #include <rte_malloc.h>
  13 #include <rte_cycles.h>
  14 #include <rte_alarm.h>
  15 #include <rte_kvargs.h>
  16 #include <rte_vect.h>
  17
  18 #include "bnxt.h"
  19 #include "bnxt_filter.h"
  20 #include "bnxt_hwrm.h"
  21 #include "bnxt_irq.h"
  22 #include "bnxt_reps.h"
  23 #include "bnxt_ring.h"
  24 #include "bnxt_rxq.h"
  25 #include "bnxt_rxr.h"
  26 #include "bnxt_stats.h"
  27 #include "bnxt_txq.h"
  28 #include "bnxt_txr.h"
  29 #include "bnxt_vnic.h"
  30 #include "hsi_struct_def_dpdk.h"
  31 #include "bnxt_nvm_defs.h"
  32 #include "bnxt_tf_common.h"
  33 #include "ulp_flow_db.h"
  34 #include "rte_pmd_bnxt.h"
  35
  36 #define DRV_MODULE_NAME         "bnxt"
  37 static const char bnxt_version[] =
  38         "Broadcom NetXtreme driver " DRV_MODULE_NAME;
  39
  40 /*
  41  * The set of PCI devices this driver supports
  42  */
  43 static const struct rte_pci_id bnxt_pci_id_map[] = {
  44         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM,
  45                          BROADCOM_DEV_ID_STRATUS_NIC_VF1) },
  46         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM,
  47                          BROADCOM_DEV_ID_STRATUS_NIC_VF2) },
  48         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_STRATUS_NIC) },
  49         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414_VF) },
  50         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57304_VF) },
  51         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_NS2) },
  52         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57406_VF) },
  53         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57407_MF) },
  54         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_5741X_VF) },
  55         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_5731X_VF) },
  56         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_MF) },
  57         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57412) },
  58         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414) },
  59         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_RJ45) },
  60         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_RJ45) },
  61         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57412_MF) },
  62         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57317_RJ45) },
  63         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_SFP) },
  64         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_SFP) },
  65         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57317_SFP) },
  66         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414_MF) },
  67         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_MF) },
  68         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58802) },
  69         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58804) },
  70         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58808) },
  71         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58802_VF) },
  72         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57508) },
  73         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57504) },
  74         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57502) },
  75         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57500_VF1) },
  76         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57500_VF2) },
  77         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57508_MF1) },
  78         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57504_MF1) },
  79         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57502_MF1) },
  80         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57508_MF2) },
  81         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57504_MF2) },
  82         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57502_MF2) },
  83         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58812) },
  84         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58814) },
  85         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58818) },
  86         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58818_VF) },
  87         { .vendor_id = 0, /* sentinel */ },
  88 };
  89
  90 #define BNXT_DEVARG_ACCUM_STATS "accum-stats"
  91 #define BNXT_DEVARG_FLOW_XSTAT  "flow-xstat"
  92 #define BNXT_DEVARG_MAX_NUM_KFLOWS  "max-num-kflows"
  93 #define BNXT_DEVARG_REPRESENTOR "representor"
  94 #define BNXT_DEVARG_REP_BASED_PF  "rep-based-pf"
  95 #define BNXT_DEVARG_REP_IS_PF  "rep-is-pf"
  96 #define BNXT_DEVARG_REP_Q_R2F  "rep-q-r2f"
  97 #define BNXT_DEVARG_REP_Q_F2R  "rep-q-f2r"
  98 #define BNXT_DEVARG_REP_FC_R2F  "rep-fc-r2f"
  99 #define BNXT_DEVARG_REP_FC_F2R  "rep-fc-f2r"
 100 #define BNXT_DEVARG_APP_ID      "app-id"
 101
 102 static const char *const bnxt_dev_args[] = {
 103         BNXT_DEVARG_REPRESENTOR,
 104         BNXT_DEVARG_ACCUM_STATS,
 105         BNXT_DEVARG_FLOW_XSTAT,
 106         BNXT_DEVARG_MAX_NUM_KFLOWS,
 107         BNXT_DEVARG_REP_BASED_PF,
 108         BNXT_DEVARG_REP_IS_PF,
 109         BNXT_DEVARG_REP_Q_R2F,
 110         BNXT_DEVARG_REP_Q_F2R,
 111         BNXT_DEVARG_REP_FC_R2F,
 112         BNXT_DEVARG_REP_FC_F2R,
 113         BNXT_DEVARG_APP_ID,
 114         NULL
 115 };
 116
 117 /*
 118  * accum-stats == false to disable flow counter accumulation
 119  * accum-stats == true to enable flow counter accumulation
 120  */
 121 #define BNXT_DEVARG_ACCUM_STATS_INVALID(accum_stats)    ((accum_stats) > 1)
 122
 123 /*
 124  * app-id = an non-negative 8-bit number
 125  */
 126 #define BNXT_DEVARG_APP_ID_INVALID(val)                 ((val) > 255)
 127
 128 /*
 129  * flow_xstat == false to disable the feature
 130  * flow_xstat == true to enable the feature
 131  */
 132 #define BNXT_DEVARG_FLOW_XSTAT_INVALID(flow_xstat)      ((flow_xstat) > 1)
 133
 134 /*
 135  * rep_is_pf == false to indicate VF representor
 136  * rep_is_pf == true to indicate PF representor
 137  */
 138 #define BNXT_DEVARG_REP_IS_PF_INVALID(rep_is_pf)        ((rep_is_pf) > 1)
 139
 140 /*
 141  * rep_based_pf == Physical index of the PF
 142  */
 143 #define BNXT_DEVARG_REP_BASED_PF_INVALID(rep_based_pf)  ((rep_based_pf) > 15)
 144 /*
 145  * rep_q_r2f == Logical COS Queue index for the rep to endpoint direction
 146  */
 147 #define BNXT_DEVARG_REP_Q_R2F_INVALID(rep_q_r2f)        ((rep_q_r2f) > 3)
 148
 149 /*
 150  * rep_q_f2r == Logical COS Queue index for the endpoint to rep direction
 151  */
 152 #define BNXT_DEVARG_REP_Q_F2R_INVALID(rep_q_f2r)        ((rep_q_f2r) > 3)
 153
 154 /*
 155  * rep_fc_r2f == Flow control for the representor to endpoint direction
 156  */
 157 #define BNXT_DEVARG_REP_FC_R2F_INVALID(rep_fc_r2f)      ((rep_fc_r2f) > 1)
 158
 159 /*
 160  * rep_fc_f2r == Flow control for the endpoint to representor direction
 161  */
 162 #define BNXT_DEVARG_REP_FC_F2R_INVALID(rep_fc_f2r)      ((rep_fc_f2r) > 1)
 163
 164 int bnxt_cfa_code_dynfield_offset = -1;
 165
 166 /*
 167  * max_num_kflows must be >= 32
 168  * and must be a power-of-2 supported value
 169  * return: 1 -> invalid
 170  *         0 -> valid
 171  */
 172 static int bnxt_devarg_max_num_kflow_invalid(uint16_t max_num_kflows)
 173 {
 174         if (max_num_kflows < 32 || !rte_is_power_of_2(max_num_kflows))
 175                 return 1;
 176         return 0;
 177 }
 178
 179 static int bnxt_vlan_offload_set_op(struct rte_eth_dev *dev, int mask);
 180 static int bnxt_dev_uninit(struct rte_eth_dev *eth_dev);
 181 static int bnxt_init_resources(struct bnxt *bp, bool reconfig_dev);
 182 static int bnxt_uninit_resources(struct bnxt *bp, bool reconfig_dev);
 183 static void bnxt_cancel_fw_health_check(struct bnxt *bp);
 184 static int bnxt_restore_vlan_filters(struct bnxt *bp);
 185 static void bnxt_dev_recover(void *arg);
 186 static void bnxt_free_error_recovery_info(struct bnxt *bp);
 187 static void bnxt_free_rep_info(struct bnxt *bp);
 188
 189 int is_bnxt_in_error(struct bnxt *bp)
 190 {
 191         if (bp->flags & BNXT_FLAG_FATAL_ERROR)
 192                 return -EIO;
 193         if (bp->flags & BNXT_FLAG_FW_RESET)
 194                 return -EBUSY;
 195
 196         return 0;
 197 }
 198
 199 /***********************/
 200
 201 /*
 202  * High level utility functions
 203  */
 204
 205 static uint16_t bnxt_rss_ctxts(const struct bnxt *bp)
 206 {
 207         unsigned int num_rss_rings = RTE_MIN(bp->rx_nr_rings,
 208                                              BNXT_RSS_TBL_SIZE_P5);
 209
 210         if (!BNXT_CHIP_P5(bp))
 211                 return 1;
 212
 213         return RTE_ALIGN_MUL_CEIL(num_rss_rings,
 214                                   BNXT_RSS_ENTRIES_PER_CTX_P5) /
 215                                   BNXT_RSS_ENTRIES_PER_CTX_P5;
 216 }
 217
 218 uint16_t bnxt_rss_hash_tbl_size(const struct bnxt *bp)
 219 {
 220         if (!BNXT_CHIP_P5(bp))
 221                 return HW_HASH_INDEX_SIZE;
 222
 223         return bnxt_rss_ctxts(bp) * BNXT_RSS_ENTRIES_PER_CTX_P5;
 224 }
 225
 226 static void bnxt_free_parent_info(struct bnxt *bp)
 227 {
 228         rte_free(bp->parent);
 229         bp->parent = NULL;
 230 }
 231
 232 static void bnxt_free_pf_info(struct bnxt *bp)
 233 {
 234         rte_free(bp->pf);
 235         bp->pf = NULL;
 236 }
 237
 238 static void bnxt_free_link_info(struct bnxt *bp)
 239 {
 240         rte_free(bp->link_info);
 241         bp->link_info = NULL;
 242 }
 243
 244 static void bnxt_free_leds_info(struct bnxt *bp)
 245 {
 246         if (BNXT_VF(bp))
 247                 return;
 248
 249         rte_free(bp->leds);
 250         bp->leds = NULL;
 251 }
 252
 253 static void bnxt_free_flow_stats_info(struct bnxt *bp)
 254 {
 255         rte_free(bp->flow_stat);
 256         bp->flow_stat = NULL;
 257 }
 258
 259 static void bnxt_free_cos_queues(struct bnxt *bp)
 260 {
 261         rte_free(bp->rx_cos_queue);
 262         bp->rx_cos_queue = NULL;
 263         rte_free(bp->tx_cos_queue);
 264         bp->tx_cos_queue = NULL;
 265 }
 266
 267 static void bnxt_free_mem(struct bnxt *bp, bool reconfig)
 268 {
 269         bnxt_free_filter_mem(bp);
 270         bnxt_free_vnic_attributes(bp);
 271         bnxt_free_vnic_mem(bp);
 272
 273         /* tx/rx rings are configured as part of *_queue_setup callbacks.
 274          * If the number of rings change across fw update,
 275          * we don't have much choice except to warn the user.
 276          */
 277         if (!reconfig) {
 278                 bnxt_free_stats(bp);
 279                 bnxt_free_tx_rings(bp);
 280                 bnxt_free_rx_rings(bp);
 281         }
 282         bnxt_free_async_cp_ring(bp);
 283         bnxt_free_rxtx_nq_ring(bp);
 284
 285         rte_free(bp->grp_info);
 286         bp->grp_info = NULL;
 287 }
 288
 289 static int bnxt_alloc_parent_info(struct bnxt *bp)
 290 {
 291         bp->parent = rte_zmalloc("bnxt_parent_info",
 292                                  sizeof(struct bnxt_parent_info), 0);
 293         if (bp->parent == NULL)
 294                 return -ENOMEM;
 295
 296         return 0;
 297 }
 298
 299 static int bnxt_alloc_pf_info(struct bnxt *bp)
 300 {
 301         bp->pf = rte_zmalloc("bnxt_pf_info", sizeof(struct bnxt_pf_info), 0);
 302         if (bp->pf == NULL)
 303                 return -ENOMEM;
 304
 305         return 0;
 306 }
 307
 308 static int bnxt_alloc_link_info(struct bnxt *bp)
 309 {
 310         bp->link_info =
 311                 rte_zmalloc("bnxt_link_info", sizeof(struct bnxt_link_info), 0);
 312         if (bp->link_info == NULL)
 313                 return -ENOMEM;
 314
 315         return 0;
 316 }
 317
 318 static int bnxt_alloc_leds_info(struct bnxt *bp)
 319 {
 320         if (BNXT_VF(bp))
 321                 return 0;
 322
 323         bp->leds = rte_zmalloc("bnxt_leds",
 324                                BNXT_MAX_LED * sizeof(struct bnxt_led_info),
 325                                0);
 326         if (bp->leds == NULL)
 327                 return -ENOMEM;
 328
 329         return 0;
 330 }
 331
 332 static int bnxt_alloc_cos_queues(struct bnxt *bp)
 333 {
 334         bp->rx_cos_queue =
 335                 rte_zmalloc("bnxt_rx_cosq",
 336                             BNXT_COS_QUEUE_COUNT *
 337                             sizeof(struct bnxt_cos_queue_info),
 338                             0);
 339         if (bp->rx_cos_queue == NULL)
 340                 return -ENOMEM;
 341
 342         bp->tx_cos_queue =
 343                 rte_zmalloc("bnxt_tx_cosq",
 344                             BNXT_COS_QUEUE_COUNT *
 345                             sizeof(struct bnxt_cos_queue_info),
 346                             0);
 347         if (bp->tx_cos_queue == NULL)
 348                 return -ENOMEM;
 349
 350         return 0;
 351 }
 352
 353 static int bnxt_alloc_flow_stats_info(struct bnxt *bp)
 354 {
 355         bp->flow_stat = rte_zmalloc("bnxt_flow_xstat",
 356                                     sizeof(struct bnxt_flow_stat_info), 0);
 357         if (bp->flow_stat == NULL)
 358                 return -ENOMEM;
 359
 360         return 0;
 361 }
 362
 363 static int bnxt_alloc_mem(struct bnxt *bp, bool reconfig)
 364 {
 365         int rc;
 366
 367         rc = bnxt_alloc_ring_grps(bp);
 368         if (rc)
 369                 goto alloc_mem_err;
 370
 371         rc = bnxt_alloc_async_ring_struct(bp);
 372         if (rc)
 373                 goto alloc_mem_err;
 374
 375         rc = bnxt_alloc_vnic_mem(bp);
 376         if (rc)
 377                 goto alloc_mem_err;
 378
 379         rc = bnxt_alloc_vnic_attributes(bp);
 380         if (rc)
 381                 goto alloc_mem_err;
 382
 383         rc = bnxt_alloc_filter_mem(bp);
 384         if (rc)
 385                 goto alloc_mem_err;
 386
 387         rc = bnxt_alloc_async_cp_ring(bp);
 388         if (rc)
 389                 goto alloc_mem_err;
 390
 391         rc = bnxt_alloc_rxtx_nq_ring(bp);
 392         if (rc)
 393                 goto alloc_mem_err;
 394
 395         if (BNXT_FLOW_XSTATS_EN(bp)) {
 396                 rc = bnxt_alloc_flow_stats_info(bp);
 397                 if (rc)
 398                         goto alloc_mem_err;
 399         }
 400
 401         return 0;
 402
 403 alloc_mem_err:
 404         bnxt_free_mem(bp, reconfig);
 405         return rc;
 406 }
 407
 408 static int bnxt_setup_one_vnic(struct bnxt *bp, uint16_t vnic_id)
 409 {
 410         struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
 411         struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id];
 412         uint64_t rx_offloads = dev_conf->rxmode.offloads;
 413         struct bnxt_rx_queue *rxq;
 414         unsigned int j;
 415         int rc;
 416
 417         rc = bnxt_vnic_grp_alloc(bp, vnic);
 418         if (rc)
 419                 goto err_out;
 420
 421         PMD_DRV_LOG(DEBUG, "vnic[%d] = %p vnic->fw_grp_ids = %p\n",
 422                     vnic_id, vnic, vnic->fw_grp_ids);
 423
 424         rc = bnxt_hwrm_vnic_alloc(bp, vnic);
 425         if (rc)
 426                 goto err_out;
 427
 428         /* Alloc RSS context only if RSS mode is enabled */
 429         if (dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS) {
 430                 int j, nr_ctxs = bnxt_rss_ctxts(bp);
 431
 432                 /* RSS table size in Thor is 512.
 433                  * Cap max Rx rings to same value
 434                  */
 435                 if (bp->rx_nr_rings > BNXT_RSS_TBL_SIZE_P5) {
 436                         PMD_DRV_LOG(ERR, "RxQ cnt %d > reta_size %d\n",
 437                                     bp->rx_nr_rings, BNXT_RSS_TBL_SIZE_P5);
 438                         goto err_out;
 439                 }
 440
 441                 rc = 0;
 442                 for (j = 0; j < nr_ctxs; j++) {
 443                         rc = bnxt_hwrm_vnic_ctx_alloc(bp, vnic, j);
 444                         if (rc)
 445                                 break;
 446                 }
 447                 if (rc) {
 448                         PMD_DRV_LOG(ERR,
 449                                     "HWRM vnic %d ctx %d alloc failure rc: %x\n",
 450                                     vnic_id, j, rc);
 451                         goto err_out;
 452                 }
 453                 vnic->num_lb_ctxts = nr_ctxs;
 454         }
 455
 456         /*
 457          * Firmware sets pf pair in default vnic cfg. If the VLAN strip
 458          * setting is not available at this time, it will not be
 459          * configured correctly in the CFA.
 460          */
 461         if (rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
 462                 vnic->vlan_strip = true;
 463         else
 464                 vnic->vlan_strip = false;
 465
 466         rc = bnxt_hwrm_vnic_cfg(bp, vnic);
 467         if (rc)
 468                 goto err_out;
 469
 470         rc = bnxt_set_hwrm_vnic_filters(bp, vnic);
 471         if (rc)
 472                 goto err_out;
 473
 474         for (j = 0; j < bp->rx_num_qs_per_vnic; j++) {
 475                 rxq = bp->eth_dev->data->rx_queues[j];
 476
 477                 PMD_DRV_LOG(DEBUG,
 478                             "rxq[%d]->vnic=%p vnic->fw_grp_ids=%p\n",
 479                             j, rxq->vnic, rxq->vnic->fw_grp_ids);
 480
 481                 if (BNXT_HAS_RING_GRPS(bp) && rxq->rx_deferred_start)
 482                         rxq->vnic->fw_grp_ids[j] = INVALID_HW_RING_ID;
 483                 else
 484                         vnic->rx_queue_cnt++;
 485         }
 486
 487         PMD_DRV_LOG(DEBUG, "vnic->rx_queue_cnt = %d\n", vnic->rx_queue_cnt);
 488
 489         rc = bnxt_vnic_rss_configure(bp, vnic);
 490         if (rc)
 491                 goto err_out;
 492
 493         bnxt_hwrm_vnic_plcmode_cfg(bp, vnic);
 494
 495         rc = bnxt_hwrm_vnic_tpa_cfg(bp, vnic,
 496                                     (rx_offloads & DEV_RX_OFFLOAD_TCP_LRO) ?
 497                                     true : false);
 498         if (rc)
 499                 goto err_out;
 500
 501         return 0;
 502 err_out:
 503         PMD_DRV_LOG(ERR, "HWRM vnic %d cfg failure rc: %x\n",
 504                     vnic_id, rc);
 505         return rc;
 506 }
 507
 508 static int bnxt_register_fc_ctx_mem(struct bnxt *bp)
 509 {
 510         int rc = 0;
 511
 512         rc = bnxt_hwrm_ctx_rgtr(bp, bp->flow_stat->rx_fc_in_tbl.dma,
 513                                 &bp->flow_stat->rx_fc_in_tbl.ctx_id);
 514         if (rc)
 515                 return rc;
 516
 517         PMD_DRV_LOG(DEBUG,
 518                     "rx_fc_in_tbl.va = %p rx_fc_in_tbl.dma = %p"
 519                     " rx_fc_in_tbl.ctx_id = %d\n",
 520                     bp->flow_stat->rx_fc_in_tbl.va,
 521                     (void *)((uintptr_t)bp->flow_stat->rx_fc_in_tbl.dma),
 522                     bp->flow_stat->rx_fc_in_tbl.ctx_id);
 523
 524         rc = bnxt_hwrm_ctx_rgtr(bp, bp->flow_stat->rx_fc_out_tbl.dma,
 525                                 &bp->flow_stat->rx_fc_out_tbl.ctx_id);
 526         if (rc)
 527                 return rc;
 528
 529         PMD_DRV_LOG(DEBUG,
 530                     "rx_fc_out_tbl.va = %p rx_fc_out_tbl.dma = %p"
 531                     " rx_fc_out_tbl.ctx_id = %d\n",
 532                     bp->flow_stat->rx_fc_out_tbl.va,
 533                     (void *)((uintptr_t)bp->flow_stat->rx_fc_out_tbl.dma),
 534                     bp->flow_stat->rx_fc_out_tbl.ctx_id);
 535
 536         rc = bnxt_hwrm_ctx_rgtr(bp, bp->flow_stat->tx_fc_in_tbl.dma,
 537                                 &bp->flow_stat->tx_fc_in_tbl.ctx_id);
 538         if (rc)
 539                 return rc;
 540
 541         PMD_DRV_LOG(DEBUG,
 542                     "tx_fc_in_tbl.va = %p tx_fc_in_tbl.dma = %p"
 543                     " tx_fc_in_tbl.ctx_id = %d\n",
 544                     bp->flow_stat->tx_fc_in_tbl.va,
 545                     (void *)((uintptr_t)bp->flow_stat->tx_fc_in_tbl.dma),
 546                     bp->flow_stat->tx_fc_in_tbl.ctx_id);
 547
 548         rc = bnxt_hwrm_ctx_rgtr(bp, bp->flow_stat->tx_fc_out_tbl.dma,
 549                                 &bp->flow_stat->tx_fc_out_tbl.ctx_id);
 550         if (rc)
 551                 return rc;
 552
 553         PMD_DRV_LOG(DEBUG,
 554                     "tx_fc_out_tbl.va = %p tx_fc_out_tbl.dma = %p"
 555                     " tx_fc_out_tbl.ctx_id = %d\n",
 556                     bp->flow_stat->tx_fc_out_tbl.va,
 557                     (void *)((uintptr_t)bp->flow_stat->tx_fc_out_tbl.dma),
 558                     bp->flow_stat->tx_fc_out_tbl.ctx_id);
 559
 560         memset(bp->flow_stat->rx_fc_out_tbl.va,
 561                0,
 562                bp->flow_stat->rx_fc_out_tbl.size);
 563         rc = bnxt_hwrm_cfa_counter_cfg(bp, BNXT_DIR_RX,
 564                                        CFA_COUNTER_CFG_IN_COUNTER_TYPE_FC,
 565                                        bp->flow_stat->rx_fc_out_tbl.ctx_id,
 566                                        bp->flow_stat->max_fc,
 567                                        true);
 568         if (rc)
 569                 return rc;
 570
 571         memset(bp->flow_stat->tx_fc_out_tbl.va,
 572                0,
 573                bp->flow_stat->tx_fc_out_tbl.size);
 574         rc = bnxt_hwrm_cfa_counter_cfg(bp, BNXT_DIR_TX,
 575                                        CFA_COUNTER_CFG_IN_COUNTER_TYPE_FC,
 576                                        bp->flow_stat->tx_fc_out_tbl.ctx_id,
 577                                        bp->flow_stat->max_fc,
 578                                        true);
 579
 580         return rc;
 581 }
 582
 583 static int bnxt_alloc_ctx_mem_buf(struct bnxt *bp, char *type, size_t size,
 584                                   struct bnxt_ctx_mem_buf_info *ctx)
 585 {
 586         if (!ctx)
 587                 return -EINVAL;
 588
 589         ctx->va = rte_zmalloc_socket(type, size, 0,
 590                                      bp->eth_dev->device->numa_node);
 591         if (ctx->va == NULL)
 592                 return -ENOMEM;
 593         rte_mem_lock_page(ctx->va);
 594         ctx->size = size;
 595         ctx->dma = rte_mem_virt2iova(ctx->va);
 596         if (ctx->dma == RTE_BAD_IOVA)
 597                 return -ENOMEM;
 598
 599         return 0;
 600 }
 601
 602 static int bnxt_init_fc_ctx_mem(struct bnxt *bp)
 603 {
 604         struct rte_pci_device *pdev = bp->pdev;
 605         char type[RTE_MEMZONE_NAMESIZE];
 606         uint16_t max_fc;
 607         int rc = 0;
 608
 609         max_fc = bp->flow_stat->max_fc;
 610
 611         sprintf(type, "bnxt_rx_fc_in_" PCI_PRI_FMT, pdev->addr.domain,
 612                 pdev->addr.bus, pdev->addr.devid, pdev->addr.function);
 613         /* 4 bytes for each counter-id */
 614         rc = bnxt_alloc_ctx_mem_buf(bp, type,
 615                                     max_fc * 4,
 616                                     &bp->flow_stat->rx_fc_in_tbl);
 617         if (rc)
 618                 return rc;
 619
 620         sprintf(type, "bnxt_rx_fc_out_" PCI_PRI_FMT, pdev->addr.domain,
 621                 pdev->addr.bus, pdev->addr.devid, pdev->addr.function);
 622         /* 16 bytes for each counter - 8 bytes pkt_count, 8 bytes byte_count */
 623         rc = bnxt_alloc_ctx_mem_buf(bp, type,
 624                                     max_fc * 16,
 625                                     &bp->flow_stat->rx_fc_out_tbl);
 626         if (rc)
 627                 return rc;
 628
 629         sprintf(type, "bnxt_tx_fc_in_" PCI_PRI_FMT, pdev->addr.domain,
 630                 pdev->addr.bus, pdev->addr.devid, pdev->addr.function);
 631         /* 4 bytes for each counter-id */
 632         rc = bnxt_alloc_ctx_mem_buf(bp, type,
 633                                     max_fc * 4,
 634                                     &bp->flow_stat->tx_fc_in_tbl);
 635         if (rc)
 636                 return rc;
 637
 638         sprintf(type, "bnxt_tx_fc_out_" PCI_PRI_FMT, pdev->addr.domain,
 639                 pdev->addr.bus, pdev->addr.devid, pdev->addr.function);
 640         /* 16 bytes for each counter - 8 bytes pkt_count, 8 bytes byte_count */
 641         rc = bnxt_alloc_ctx_mem_buf(bp, type,
 642                                     max_fc * 16,
 643                                     &bp->flow_stat->tx_fc_out_tbl);
 644         if (rc)
 645                 return rc;
 646
 647         rc = bnxt_register_fc_ctx_mem(bp);
 648
 649         return rc;
 650 }
 651
 652 static int bnxt_init_ctx_mem(struct bnxt *bp)
 653 {
 654         int rc = 0;
 655
 656         if (!(bp->fw_cap & BNXT_FW_CAP_ADV_FLOW_COUNTERS) ||
 657             !(BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp)) ||
 658             !BNXT_FLOW_XSTATS_EN(bp))
 659                 return 0;
 660
 661         rc = bnxt_hwrm_cfa_counter_qcaps(bp, &bp->flow_stat->max_fc);
 662         if (rc)
 663                 return rc;
 664
 665         rc = bnxt_init_fc_ctx_mem(bp);
 666
 667         return rc;
 668 }
 669
 670 static int bnxt_update_phy_setting(struct bnxt *bp)
 671 {
 672         struct rte_eth_link new;
 673         int rc;
 674
 675         rc = bnxt_get_hwrm_link_config(bp, &new);
 676         if (rc) {
 677                 PMD_DRV_LOG(ERR, "Failed to get link settings\n");
 678                 return rc;
 679         }
 680
 681         /*
 682          * On BCM957508-N2100 adapters, FW will not allow any user other
 683          * than BMC to shutdown the port. bnxt_get_hwrm_link_config() call
 684          * always returns link up. Force phy update always in that case.
 685          */
 686         if (!new.link_status || IS_BNXT_DEV_957508_N2100(bp)) {
 687                 rc = bnxt_set_hwrm_link_config(bp, true);
 688                 if (rc) {
 689                         PMD_DRV_LOG(ERR, "Failed to update PHY settings\n");
 690                         return rc;
 691                 }
 692         }
 693
 694         return rc;
 695 }
 696
 697 static void bnxt_free_prev_ring_stats(struct bnxt *bp)
 698 {
 699         rte_free(bp->prev_rx_ring_stats);
 700         rte_free(bp->prev_tx_ring_stats);
 701
 702         bp->prev_rx_ring_stats = NULL;
 703         bp->prev_tx_ring_stats = NULL;
 704 }
 705
 706 static int bnxt_alloc_prev_ring_stats(struct bnxt *bp)
 707 {
 708         bp->prev_rx_ring_stats =  rte_zmalloc("bnxt_prev_rx_ring_stats",
 709                                               sizeof(struct bnxt_ring_stats) *
 710                                               bp->rx_cp_nr_rings,
 711                                               0);
 712         if (bp->prev_rx_ring_stats == NULL)
 713                 return -ENOMEM;
 714
 715         bp->prev_tx_ring_stats = rte_zmalloc("bnxt_prev_tx_ring_stats",
 716                                              sizeof(struct bnxt_ring_stats) *
 717                                              bp->tx_cp_nr_rings,
 718                                              0);
 719         if (bp->prev_tx_ring_stats == NULL)
 720                 goto error;
 721
 722         return 0;
 723
 724 error:
 725         bnxt_free_prev_ring_stats(bp);
 726         return -ENOMEM;
 727 }
 728
 729 static int bnxt_start_nic(struct bnxt *bp)
 730 {
 731         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(bp->eth_dev);
 732         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
 733         uint32_t intr_vector = 0;
 734         uint32_t queue_id, base = BNXT_MISC_VEC_ID;
 735         uint32_t vec = BNXT_MISC_VEC_ID;
 736         unsigned int i, j;
 737         int rc;
 738
 739         if (bp->eth_dev->data->mtu > RTE_ETHER_MTU) {
 740                 bp->eth_dev->data->dev_conf.rxmode.offloads |=
 741                         DEV_RX_OFFLOAD_JUMBO_FRAME;
 742                 bp->flags |= BNXT_FLAG_JUMBO;
 743         } else {
 744                 bp->eth_dev->data->dev_conf.rxmode.offloads &=
 745                         ~DEV_RX_OFFLOAD_JUMBO_FRAME;
 746                 bp->flags &= ~BNXT_FLAG_JUMBO;
 747         }
 748
 749         /* THOR does not support ring groups.
 750          * But we will use the array to save RSS context IDs.
 751          */
 752         if (BNXT_CHIP_P5(bp))
 753                 bp->max_ring_grps = BNXT_MAX_RSS_CTXTS_P5;
 754
 755         rc = bnxt_alloc_all_hwrm_stat_ctxs(bp);
 756         if (rc) {
 757                 PMD_DRV_LOG(ERR, "HWRM stat ctx alloc failure rc: %x\n", rc);
 758                 goto err_out;
 759         }
 760
 761         rc = bnxt_alloc_hwrm_rings(bp);
 762         if (rc) {
 763                 PMD_DRV_LOG(ERR, "HWRM ring alloc failure rc: %x\n", rc);
 764                 goto err_out;
 765         }
 766
 767         rc = bnxt_alloc_all_hwrm_ring_grps(bp);
 768         if (rc) {
 769                 PMD_DRV_LOG(ERR, "HWRM ring grp alloc failure: %x\n", rc);
 770                 goto err_out;
 771         }
 772
 773         if (!(bp->vnic_cap_flags & BNXT_VNIC_CAP_COS_CLASSIFY))
 774                 goto skip_cosq_cfg;
 775
 776         for (j = 0, i = 0; i < BNXT_COS_QUEUE_COUNT; i++) {
 777                 if (bp->rx_cos_queue[i].id != 0xff) {
 778                         struct bnxt_vnic_info *vnic = &bp->vnic_info[j++];
 779
 780                         if (!vnic) {
 781                                 PMD_DRV_LOG(ERR,
 782                                             "Num pools more than FW profile\n");
 783                                 rc = -EINVAL;
 784                                 goto err_out;
 785                         }
 786                         vnic->cos_queue_id = bp->rx_cos_queue[i].id;
 787                         bp->rx_cosq_cnt++;
 788                 }
 789         }
 790
 791 skip_cosq_cfg:
 792         rc = bnxt_mq_rx_configure(bp);
 793         if (rc) {
 794                 PMD_DRV_LOG(ERR, "MQ mode configure failure rc: %x\n", rc);
 795                 goto err_out;
 796         }
 797
 798         /* default vnic 0 */
 799         rc = bnxt_setup_one_vnic(bp, 0);
 800         if (rc)
 801                 goto err_out;
 802         /* VNIC configuration */
 803         if (BNXT_RFS_NEEDS_VNIC(bp)) {
 804                 for (i = 1; i < bp->nr_vnics; i++) {
 805                         rc = bnxt_setup_one_vnic(bp, i);
 806                         if (rc)
 807                                 goto err_out;
 808                 }
 809         }
 810
 811         for (j = 0; j < bp->tx_nr_rings; j++) {
 812                 struct bnxt_tx_queue *txq = bp->tx_queues[j];
 813
 814                 if (!txq->tx_deferred_start) {
 815                         bp->eth_dev->data->tx_queue_state[j] =
 816                                 RTE_ETH_QUEUE_STATE_STARTED;
 817                         txq->tx_started = true;
 818                 }
 819         }
 820
 821         for (j = 0; j < bp->rx_nr_rings; j++) {
 822                 struct bnxt_rx_queue *rxq = bp->rx_queues[j];
 823
 824                 if (!rxq->rx_deferred_start) {
 825                         bp->eth_dev->data->rx_queue_state[j] =
 826                                 RTE_ETH_QUEUE_STATE_STARTED;
 827                         rxq->rx_started = true;
 828                 }
 829         }
 830
 831         rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, &bp->vnic_info[0], 0, NULL);
 832         if (rc) {
 833                 PMD_DRV_LOG(ERR,
 834                         "HWRM cfa l2 rx mask failure rc: %x\n", rc);
 835                 goto err_out;
 836         }
 837
 838         /* check and configure queue intr-vector mapping */
 839         if ((rte_intr_cap_multiple(intr_handle) ||
 840              !RTE_ETH_DEV_SRIOV(bp->eth_dev).active) &&
 841             bp->eth_dev->data->dev_conf.intr_conf.rxq != 0) {
 842                 intr_vector = bp->eth_dev->data->nb_rx_queues;
 843                 PMD_DRV_LOG(DEBUG, "intr_vector = %d\n", intr_vector);
 844                 if (intr_vector > bp->rx_cp_nr_rings) {
 845                         PMD_DRV_LOG(ERR, "At most %d intr queues supported",
 846                                         bp->rx_cp_nr_rings);
 847                         return -ENOTSUP;
 848                 }
 849                 rc = rte_intr_efd_enable(intr_handle, intr_vector);
 850                 if (rc)
 851                         return rc;
 852         }
 853
 854         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
 855                 intr_handle->intr_vec =
 856                         rte_zmalloc("intr_vec",
 857                                     bp->eth_dev->data->nb_rx_queues *
 858                                     sizeof(int), 0);
 859                 if (intr_handle->intr_vec == NULL) {
 860                         PMD_DRV_LOG(ERR, "Failed to allocate %d rx_queues"
 861                                 " intr_vec", bp->eth_dev->data->nb_rx_queues);
 862                         rc = -ENOMEM;
 863                         goto err_out;
 864                 }
 865                 PMD_DRV_LOG(DEBUG, "intr_handle->intr_vec = %p "
 866                         "intr_handle->nb_efd = %d intr_handle->max_intr = %d\n",
 867                          intr_handle->intr_vec, intr_handle->nb_efd,
 868                         intr_handle->max_intr);
 869                 for (queue_id = 0; queue_id < bp->eth_dev->data->nb_rx_queues;
 870                      queue_id++) {
 871                         intr_handle->intr_vec[queue_id] =
 872                                                         vec + BNXT_RX_VEC_START;
 873                         if (vec < base + intr_handle->nb_efd - 1)
 874                                 vec++;
 875                 }
 876         }
 877
 878         /* enable uio/vfio intr/eventfd mapping */
 879         rc = rte_intr_enable(intr_handle);
 880 #ifndef RTE_EXEC_ENV_FREEBSD
 881         /* In FreeBSD OS, nic_uio driver does not support interrupts */
 882         if (rc)
 883                 goto err_out;
 884 #endif
 885
 886         rc = bnxt_update_phy_setting(bp);
 887         if (rc)
 888                 goto err_out;
 889
 890         bp->mark_table = rte_zmalloc("bnxt_mark_table", BNXT_MARK_TABLE_SZ, 0);
 891         if (!bp->mark_table)
 892                 PMD_DRV_LOG(ERR, "Allocation of mark table failed\n");
 893
 894         return 0;
 895
 896 err_out:
 897         /* Some of the error status returned by FW may not be from errno.h */
 898         if (rc > 0)
 899                 rc = -EIO;
 900
 901         return rc;
 902 }
 903
 904 static int bnxt_shutdown_nic(struct bnxt *bp)
 905 {
 906         bnxt_free_all_hwrm_resources(bp);
 907         bnxt_free_all_filters(bp);
 908         bnxt_free_all_vnics(bp);
 909         return 0;
 910 }
 911
 912 /*
 913  * Device configuration and status function
 914  */
 915
 916 uint32_t bnxt_get_speed_capabilities(struct bnxt *bp)
 917 {
 918         uint32_t link_speed = 0;
 919         uint32_t speed_capa = 0;
 920
 921         if (bp->link_info == NULL)
 922                 return 0;
 923
 924         link_speed = bp->link_info->support_speeds;
 925
 926         /* If PAM4 is configured, use PAM4 supported speed */
 927         if (link_speed == 0 && bp->link_info->support_pam4_speeds > 0)
 928                 link_speed = bp->link_info->support_pam4_speeds;
 929
 930         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_100MB)
 931                 speed_capa |= ETH_LINK_SPEED_100M;
 932         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_100MBHD)
 933                 speed_capa |= ETH_LINK_SPEED_100M_HD;
 934         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_1GB)
 935                 speed_capa |= ETH_LINK_SPEED_1G;
 936         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_2_5GB)
 937                 speed_capa |= ETH_LINK_SPEED_2_5G;
 938         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_10GB)
 939                 speed_capa |= ETH_LINK_SPEED_10G;
 940         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_20GB)
 941                 speed_capa |= ETH_LINK_SPEED_20G;
 942         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_25GB)
 943                 speed_capa |= ETH_LINK_SPEED_25G;
 944         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_40GB)
 945                 speed_capa |= ETH_LINK_SPEED_40G;
 946         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_50GB)
 947                 speed_capa |= ETH_LINK_SPEED_50G;
 948         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_100GB)
 949                 speed_capa |= ETH_LINK_SPEED_100G;
 950         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_PAM4_SPEEDS_50G)
 951                 speed_capa |= ETH_LINK_SPEED_50G;
 952         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_PAM4_SPEEDS_100G)
 953                 speed_capa |= ETH_LINK_SPEED_100G;
 954         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_PAM4_SPEEDS_200G)
 955                 speed_capa |= ETH_LINK_SPEED_200G;
 956
 957         if (bp->link_info->auto_mode ==
 958             HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_MODE_NONE)
 959                 speed_capa |= ETH_LINK_SPEED_FIXED;
 960
 961         return speed_capa;
 962 }
 963
 964 static int bnxt_dev_info_get_op(struct rte_eth_dev *eth_dev,
 965                                 struct rte_eth_dev_info *dev_info)
 966 {
 967         struct rte_pci_device *pdev = RTE_DEV_TO_PCI(eth_dev->device);
 968         struct bnxt *bp = eth_dev->data->dev_private;
 969         uint16_t max_vnics, i, j, vpool, vrxq;
 970         unsigned int max_rx_rings;
 971         int rc;
 972
 973         rc = is_bnxt_in_error(bp);
 974         if (rc)
 975                 return rc;
 976
 977         /* MAC Specifics */
 978         dev_info->max_mac_addrs = bp->max_l2_ctx;
 979         dev_info->max_hash_mac_addrs = 0;
 980
 981         /* PF/VF specifics */
 982         if (BNXT_PF(bp))
 983                 dev_info->max_vfs = pdev->max_vfs;
 984
 985         max_rx_rings = bnxt_max_rings(bp);
 986         /* For the sake of symmetry, max_rx_queues = max_tx_queues */
 987         dev_info->max_rx_queues = max_rx_rings;
 988         dev_info->max_tx_queues = max_rx_rings;
 989         dev_info->reta_size = bnxt_rss_hash_tbl_size(bp);
 990         dev_info->hash_key_size = HW_HASH_KEY_SIZE;
 991         max_vnics = bp->max_vnics;
 992
 993         /* MTU specifics */
 994         dev_info->min_mtu = RTE_ETHER_MIN_MTU;
 995         dev_info->max_mtu = BNXT_MAX_MTU;
 996
 997         /* Fast path specifics */
 998         dev_info->min_rx_bufsize = 1;
 999         dev_info->max_rx_pktlen = BNXT_MAX_PKT_LEN;
1000
1001         dev_info->rx_offload_capa = BNXT_DEV_RX_OFFLOAD_SUPPORT;
1002         if (bp->flags & BNXT_FLAG_PTP_SUPPORTED)
1003                 dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_TIMESTAMP;
1004         if (bp->vnic_cap_flags & BNXT_VNIC_CAP_VLAN_RX_STRIP)
1005                 dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_VLAN_STRIP;
1006         dev_info->tx_queue_offload_capa = DEV_TX_OFFLOAD_MBUF_FAST_FREE;
1007         dev_info->tx_offload_capa = BNXT_DEV_TX_OFFLOAD_SUPPORT |
1008                                     dev_info->tx_queue_offload_capa;
1009         if (bp->fw_cap & BNXT_FW_CAP_VLAN_TX_INSERT)
1010                 dev_info->tx_offload_capa |= DEV_TX_OFFLOAD_VLAN_INSERT;
1011         dev_info->flow_type_rss_offloads = BNXT_ETH_RSS_SUPPORT;
1012
1013         dev_info->speed_capa = bnxt_get_speed_capabilities(bp);
1014         dev_info->dev_capa = RTE_ETH_DEV_CAPA_RUNTIME_RX_QUEUE_SETUP |
1015                              RTE_ETH_DEV_CAPA_RUNTIME_TX_QUEUE_SETUP;
1016
1017         dev_info->default_rxconf = (struct rte_eth_rxconf) {
1018                 .rx_thresh = {
1019                         .pthresh = 8,
1020                         .hthresh = 8,
1021                         .wthresh = 0,
1022                 },
1023                 .rx_free_thresh = 32,
1024                 .rx_drop_en = BNXT_DEFAULT_RX_DROP_EN,
1025         };
1026
1027         dev_info->default_txconf = (struct rte_eth_txconf) {
1028                 .tx_thresh = {
1029                         .pthresh = 32,
1030                         .hthresh = 0,
1031                         .wthresh = 0,
1032                 },
1033                 .tx_free_thresh = 32,
1034                 .tx_rs_thresh = 32,
1035         };
1036         eth_dev->data->dev_conf.intr_conf.lsc = 1;
1037
1038         dev_info->rx_desc_lim.nb_min = BNXT_MIN_RING_DESC;
1039         dev_info->rx_desc_lim.nb_max = BNXT_MAX_RX_RING_DESC;
1040         dev_info->tx_desc_lim.nb_min = BNXT_MIN_RING_DESC;
1041         dev_info->tx_desc_lim.nb_max = BNXT_MAX_TX_RING_DESC;
1042
1043         if (BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp)) {
1044                 dev_info->switch_info.name = eth_dev->device->name;
1045                 dev_info->switch_info.domain_id = bp->switch_domain_id;
1046                 dev_info->switch_info.port_id =
1047                                 BNXT_PF(bp) ? BNXT_SWITCH_PORT_ID_PF :
1048                                     BNXT_SWITCH_PORT_ID_TRUSTED_VF;
1049         }
1050
1051         /*
1052          * TODO: default_rxconf, default_txconf, rx_desc_lim, and tx_desc_lim
1053          *       need further investigation.
1054          */
1055
1056         /* VMDq resources */
1057         vpool = 64; /* ETH_64_POOLS */
1058         vrxq = 128; /* ETH_VMDQ_DCB_NUM_QUEUES */
1059         for (i = 0; i < 4; vpool >>= 1, i++) {
1060                 if (max_vnics > vpool) {
1061                         for (j = 0; j < 5; vrxq >>= 1, j++) {
1062                                 if (dev_info->max_rx_queues > vrxq) {
1063                                         if (vpool > vrxq)
1064                                                 vpool = vrxq;
1065                                         goto found;
1066                                 }
1067                         }
1068                         /* Not enough resources to support VMDq */
1069                         break;
1070                 }
1071         }
1072         /* Not enough resources to support VMDq */
1073         vpool = 0;
1074         vrxq = 0;
1075 found:
1076         dev_info->max_vmdq_pools = vpool;
1077         dev_info->vmdq_queue_num = vrxq;
1078
1079         dev_info->vmdq_pool_base = 0;
1080         dev_info->vmdq_queue_base = 0;
1081
1082         return 0;
1083 }
1084
1085 /* Configure the device based on the configuration provided */
1086 static int bnxt_dev_configure_op(struct rte_eth_dev *eth_dev)
1087 {
1088         struct bnxt *bp = eth_dev->data->dev_private;
1089         uint64_t rx_offloads = eth_dev->data->dev_conf.rxmode.offloads;
1090         int rc;
1091
1092         bp->rx_queues = (void *)eth_dev->data->rx_queues;
1093         bp->tx_queues = (void *)eth_dev->data->tx_queues;
1094         bp->tx_nr_rings = eth_dev->data->nb_tx_queues;
1095         bp->rx_nr_rings = eth_dev->data->nb_rx_queues;
1096
1097         rc = is_bnxt_in_error(bp);
1098         if (rc)
1099                 return rc;
1100
1101         if (BNXT_VF(bp) && (bp->flags & BNXT_FLAG_NEW_RM)) {
1102                 rc = bnxt_hwrm_check_vf_rings(bp);
1103                 if (rc) {
1104                         PMD_DRV_LOG(ERR, "HWRM insufficient resources\n");
1105                         return -ENOSPC;
1106                 }
1107
1108                 /* If a resource has already been allocated - in this case
1109                  * it is the async completion ring, free it. Reallocate it after
1110                  * resource reservation. This will ensure the resource counts
1111                  * are calculated correctly.
1112                  */
1113
1114                 pthread_mutex_lock(&bp->def_cp_lock);
1115
1116                 if (!BNXT_HAS_NQ(bp) && bp->async_cp_ring) {
1117                         bnxt_disable_int(bp);
1118                         bnxt_free_cp_ring(bp, bp->async_cp_ring);
1119                 }
1120
1121                 rc = bnxt_hwrm_func_reserve_vf_resc(bp, false);
1122                 if (rc) {
1123                         PMD_DRV_LOG(ERR, "HWRM resource alloc fail:%x\n", rc);
1124                         pthread_mutex_unlock(&bp->def_cp_lock);
1125                         return -ENOSPC;
1126                 }
1127
1128                 if (!BNXT_HAS_NQ(bp) && bp->async_cp_ring) {
1129                         rc = bnxt_alloc_async_cp_ring(bp);
1130                         if (rc) {
1131                                 pthread_mutex_unlock(&bp->def_cp_lock);
1132                                 return rc;
1133                         }
1134                         bnxt_enable_int(bp);
1135                 }
1136
1137                 pthread_mutex_unlock(&bp->def_cp_lock);
1138         }
1139
1140         /* Inherit new configurations */
1141         if (eth_dev->data->nb_rx_queues > bp->max_rx_rings ||
1142             eth_dev->data->nb_tx_queues > bp->max_tx_rings ||
1143             eth_dev->data->nb_rx_queues + eth_dev->data->nb_tx_queues
1144                 + BNXT_NUM_ASYNC_CPR(bp) > bp->max_cp_rings ||
1145             eth_dev->data->nb_rx_queues + eth_dev->data->nb_tx_queues >
1146             bp->max_stat_ctx)
1147                 goto resource_error;
1148
1149         if (BNXT_HAS_RING_GRPS(bp) &&
1150             (uint32_t)(eth_dev->data->nb_rx_queues) > bp->max_ring_grps)
1151                 goto resource_error;
1152
1153         if (!(eth_dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_RSS) &&
1154             bp->max_vnics < eth_dev->data->nb_rx_queues)
1155                 goto resource_error;
1156
1157         bp->rx_cp_nr_rings = bp->rx_nr_rings;
1158         bp->tx_cp_nr_rings = bp->tx_nr_rings;
1159
1160         if (eth_dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG)
1161                 rx_offloads |= DEV_RX_OFFLOAD_RSS_HASH;
1162         eth_dev->data->dev_conf.rxmode.offloads = rx_offloads;
1163
1164         bnxt_mtu_set_op(eth_dev, eth_dev->data->mtu);
1165
1166         return 0;
1167
1168 resource_error:
1169         PMD_DRV_LOG(ERR,
1170                     "Insufficient resources to support requested config\n");
1171         PMD_DRV_LOG(ERR,
1172                     "Num Queues Requested: Tx %d, Rx %d\n",
1173                     eth_dev->data->nb_tx_queues,
1174                     eth_dev->data->nb_rx_queues);
1175         PMD_DRV_LOG(ERR,
1176                     "MAX: TxQ %d, RxQ %d, CQ %d Stat %d, Grp %d, Vnic %d\n",
1177                     bp->max_tx_rings, bp->max_rx_rings, bp->max_cp_rings,
1178                     bp->max_stat_ctx, bp->max_ring_grps, bp->max_vnics);
1179         return -ENOSPC;
1180 }
1181
1182 void bnxt_print_link_info(struct rte_eth_dev *eth_dev)
1183 {
1184         struct rte_eth_link *link = &eth_dev->data->dev_link;
1185
1186         if (link->link_status)
1187                 PMD_DRV_LOG(INFO, "Port %d Link Up - speed %u Mbps - %s\n",
1188                         eth_dev->data->port_id,
1189                         (uint32_t)link->link_speed,
1190                         (link->link_duplex == ETH_LINK_FULL_DUPLEX) ?
1191                         ("full-duplex") : ("half-duplex\n"));
1192         else
1193                 PMD_DRV_LOG(INFO, "Port %d Link Down\n",
1194                         eth_dev->data->port_id);
1195 }
1196
1197 /*
1198  * Determine whether the current configuration requires support for scattered
1199  * receive; return 1 if scattered receive is required and 0 if not.
1200  */
1201 static int bnxt_scattered_rx(struct rte_eth_dev *eth_dev)
1202 {
1203         uint32_t overhead = BNXT_MAX_PKT_LEN - BNXT_MAX_MTU;
1204         uint16_t buf_size;
1205         int i;
1206
1207         if (eth_dev->data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_SCATTER)
1208                 return 1;
1209
1210         if (eth_dev->data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_TCP_LRO)
1211                 return 1;
1212
1213         for (i = 0; i < eth_dev->data->nb_rx_queues; i++) {
1214                 struct bnxt_rx_queue *rxq = eth_dev->data->rx_queues[i];
1215
1216                 buf_size = (uint16_t)(rte_pktmbuf_data_room_size(rxq->mb_pool) -
1217                                       RTE_PKTMBUF_HEADROOM);
1218                 if (eth_dev->data->mtu + overhead > buf_size)
1219                         return 1;
1220         }
1221         return 0;
1222 }
1223
1224 static eth_rx_burst_t
1225 bnxt_receive_function(struct rte_eth_dev *eth_dev)
1226 {
1227         struct bnxt *bp = eth_dev->data->dev_private;
1228
1229         /* Disable vector mode RX for Stingray2 for now */
1230         if (BNXT_CHIP_SR2(bp)) {
1231                 bp->flags &= ~BNXT_FLAG_RX_VECTOR_PKT_MODE;
1232                 return bnxt_recv_pkts;
1233         }
1234
1235 #if (defined(RTE_ARCH_X86) || defined(RTE_ARCH_ARM64)) && \
1236         !defined(RTE_LIBRTE_IEEE1588)
1237
1238         /* Vector mode receive cannot be enabled if scattered rx is in use. */
1239         if (eth_dev->data->scattered_rx)
1240                 goto use_scalar_rx;
1241
1242         /*
1243          * Vector mode receive cannot be enabled if Truflow is enabled or if
1244          * asynchronous completions and receive completions can be placed in
1245          * the same completion ring.
1246          */
1247         if (BNXT_TRUFLOW_EN(bp) || !BNXT_NUM_ASYNC_CPR(bp))
1248                 goto use_scalar_rx;
1249
1250         /*
1251          * Vector mode receive cannot be enabled if any receive offloads outside
1252          * a limited subset have been enabled.
1253          */
1254         if (eth_dev->data->dev_conf.rxmode.offloads &
1255                 ~(DEV_RX_OFFLOAD_VLAN_STRIP |
1256                   DEV_RX_OFFLOAD_KEEP_CRC |
1257                   DEV_RX_OFFLOAD_JUMBO_FRAME |
1258                   DEV_RX_OFFLOAD_IPV4_CKSUM |
1259                   DEV_RX_OFFLOAD_UDP_CKSUM |
1260                   DEV_RX_OFFLOAD_TCP_CKSUM |
1261                   DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM |
1262                   DEV_RX_OFFLOAD_OUTER_UDP_CKSUM |
1263                   DEV_RX_OFFLOAD_RSS_HASH |
1264                   DEV_RX_OFFLOAD_VLAN_FILTER))
1265                 goto use_scalar_rx;
1266
1267 #if defined(RTE_ARCH_X86) && defined(CC_AVX2_SUPPORT)
1268         if (rte_vect_get_max_simd_bitwidth() >= RTE_VECT_SIMD_256 &&
1269             rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX2) == 1) {
1270                 PMD_DRV_LOG(INFO,
1271                             "Using AVX2 vector mode receive for port %d\n",
1272                             eth_dev->data->port_id);
1273                 bp->flags |= BNXT_FLAG_RX_VECTOR_PKT_MODE;
1274                 return bnxt_recv_pkts_vec_avx2;
1275         }
1276  #endif
1277         if (rte_vect_get_max_simd_bitwidth() >= RTE_VECT_SIMD_128) {
1278                 PMD_DRV_LOG(INFO,
1279                             "Using SSE vector mode receive for port %d\n",
1280                             eth_dev->data->port_id);
1281                 bp->flags |= BNXT_FLAG_RX_VECTOR_PKT_MODE;
1282                 return bnxt_recv_pkts_vec;
1283         }
1284
1285 use_scalar_rx:
1286         PMD_DRV_LOG(INFO, "Vector mode receive disabled for port %d\n",
1287                     eth_dev->data->port_id);
1288         PMD_DRV_LOG(INFO,
1289                     "Port %d scatter: %d rx offload: %" PRIX64 "\n",
1290                     eth_dev->data->port_id,
1291                     eth_dev->data->scattered_rx,
1292                     eth_dev->data->dev_conf.rxmode.offloads);
1293 #endif
1294         bp->flags &= ~BNXT_FLAG_RX_VECTOR_PKT_MODE;
1295         return bnxt_recv_pkts;
1296 }
1297
1298 static eth_tx_burst_t
1299 bnxt_transmit_function(struct rte_eth_dev *eth_dev)
1300 {
1301         struct bnxt *bp = eth_dev->data->dev_private;
1302
1303         /* Disable vector mode TX for Stingray2 for now */
1304         if (BNXT_CHIP_SR2(bp))
1305                 return bnxt_xmit_pkts;
1306
1307 #if defined(RTE_ARCH_X86) || defined(RTE_ARCH_ARM64) && \
1308         !defined(RTE_LIBRTE_IEEE1588)
1309         uint64_t offloads = eth_dev->data->dev_conf.txmode.offloads;
1310
1311         /*
1312          * Vector mode transmit can be enabled only if not using scatter rx
1313          * or tx offloads.
1314          */
1315         if (eth_dev->data->scattered_rx ||
1316             (offloads & ~DEV_TX_OFFLOAD_MBUF_FAST_FREE) ||
1317             BNXT_TRUFLOW_EN(bp))
1318                 goto use_scalar_tx;
1319
1320 #if defined(RTE_ARCH_X86) && defined(CC_AVX2_SUPPORT)
1321         if (rte_vect_get_max_simd_bitwidth() >= RTE_VECT_SIMD_256 &&
1322             rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX2) == 1) {
1323                 PMD_DRV_LOG(INFO,
1324                             "Using AVX2 vector mode transmit for port %d\n",
1325                             eth_dev->data->port_id);
1326                 return bnxt_xmit_pkts_vec_avx2;
1327         }
1328 #endif
1329         if (rte_vect_get_max_simd_bitwidth() >= RTE_VECT_SIMD_128) {
1330                 PMD_DRV_LOG(INFO,
1331                             "Using SSE vector mode transmit for port %d\n",
1332                             eth_dev->data->port_id);
1333                 return bnxt_xmit_pkts_vec;
1334         }
1335
1336 use_scalar_tx:
1337         PMD_DRV_LOG(INFO, "Vector mode transmit disabled for port %d\n",
1338                     eth_dev->data->port_id);
1339         PMD_DRV_LOG(INFO,
1340                     "Port %d scatter: %d tx offload: %" PRIX64 "\n",
1341                     eth_dev->data->port_id,
1342                     eth_dev->data->scattered_rx,
1343                     offloads);
1344 #endif
1345         return bnxt_xmit_pkts;
1346 }
1347
1348 static int bnxt_handle_if_change_status(struct bnxt *bp)
1349 {
1350         int rc;
1351
1352         /* Since fw has undergone a reset and lost all contexts,
1353          * set fatal flag to not issue hwrm during cleanup
1354          */
1355         bp->flags |= BNXT_FLAG_FATAL_ERROR;
1356         bnxt_uninit_resources(bp, true);
1357
1358         /* clear fatal flag so that re-init happens */
1359         bp->flags &= ~BNXT_FLAG_FATAL_ERROR;
1360         rc = bnxt_init_resources(bp, true);
1361
1362         bp->flags &= ~BNXT_FLAG_IF_CHANGE_HOT_FW_RESET_DONE;
1363
1364         return rc;
1365 }
1366
1367 static int bnxt_dev_set_link_up_op(struct rte_eth_dev *eth_dev)
1368 {
1369         struct bnxt *bp = eth_dev->data->dev_private;
1370         int rc = 0;
1371
1372         if (!BNXT_SINGLE_PF(bp))
1373                 return -ENOTSUP;
1374
1375         if (!bp->link_info->link_up)
1376                 rc = bnxt_set_hwrm_link_config(bp, true);
1377         if (!rc)
1378                 eth_dev->data->dev_link.link_status = 1;
1379
1380         bnxt_print_link_info(eth_dev);
1381         return rc;
1382 }
1383
1384 static int bnxt_dev_set_link_down_op(struct rte_eth_dev *eth_dev)
1385 {
1386         struct bnxt *bp = eth_dev->data->dev_private;
1387
1388         if (!BNXT_SINGLE_PF(bp))
1389                 return -ENOTSUP;
1390
1391         eth_dev->data->dev_link.link_status = 0;
1392         bnxt_set_hwrm_link_config(bp, false);
1393         bp->link_info->link_up = 0;
1394
1395         return 0;
1396 }
1397
1398 static void bnxt_free_switch_domain(struct bnxt *bp)
1399 {
1400         int rc = 0;
1401
1402         if (!(BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp)))
1403                 return;
1404
1405         rc = rte_eth_switch_domain_free(bp->switch_domain_id);
1406         if (rc)
1407                 PMD_DRV_LOG(ERR, "free switch domain:%d fail: %d\n",
1408                             bp->switch_domain_id, rc);
1409 }
1410
1411 static void bnxt_ptp_get_current_time(void *arg)
1412 {
1413         struct bnxt *bp = arg;
1414         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
1415         int rc;
1416
1417         rc = is_bnxt_in_error(bp);
1418         if (rc)
1419                 return;
1420
1421         if (!ptp)
1422                 return;
1423
1424         bnxt_hwrm_port_ts_query(bp, BNXT_PTP_FLAGS_CURRENT_TIME,
1425                                 &ptp->current_time);
1426
1427         rc = rte_eal_alarm_set(US_PER_S, bnxt_ptp_get_current_time, (void *)bp);
1428         if (rc != 0) {
1429                 PMD_DRV_LOG(ERR, "Failed to re-schedule PTP alarm\n");
1430                 bp->flags2 &= ~BNXT_FLAGS2_PTP_ALARM_SCHEDULED;
1431         }
1432 }
1433
1434 static int bnxt_schedule_ptp_alarm(struct bnxt *bp)
1435 {
1436         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
1437         int rc;
1438
1439         if (bp->flags2 & BNXT_FLAGS2_PTP_ALARM_SCHEDULED)
1440                 return 0;
1441
1442         bnxt_hwrm_port_ts_query(bp, BNXT_PTP_FLAGS_CURRENT_TIME,
1443                                 &ptp->current_time);
1444
1445         rc = rte_eal_alarm_set(US_PER_S, bnxt_ptp_get_current_time, (void *)bp);
1446         return rc;
1447 }
1448
1449 static void bnxt_cancel_ptp_alarm(struct bnxt *bp)
1450 {
1451         if (bp->flags2 & BNXT_FLAGS2_PTP_ALARM_SCHEDULED) {
1452                 rte_eal_alarm_cancel(bnxt_ptp_get_current_time, (void *)bp);
1453                 bp->flags2 &= ~BNXT_FLAGS2_PTP_ALARM_SCHEDULED;
1454         }
1455 }
1456
1457 static void bnxt_ptp_stop(struct bnxt *bp)
1458 {
1459         bnxt_cancel_ptp_alarm(bp);
1460         bp->flags2 &= ~BNXT_FLAGS2_PTP_TIMESYNC_ENABLED;
1461 }
1462
1463 static int bnxt_ptp_start(struct bnxt *bp)
1464 {
1465         int rc;
1466
1467         rc = bnxt_schedule_ptp_alarm(bp);
1468         if (rc != 0) {
1469                 PMD_DRV_LOG(ERR, "Failed to schedule PTP alarm\n");
1470         } else {
1471                 bp->flags2 |= BNXT_FLAGS2_PTP_TIMESYNC_ENABLED;
1472                 bp->flags2 |= BNXT_FLAGS2_PTP_ALARM_SCHEDULED;
1473         }
1474
1475         return rc;
1476 }
1477
1478 static int bnxt_dev_stop(struct rte_eth_dev *eth_dev)
1479 {
1480         struct bnxt *bp = eth_dev->data->dev_private;
1481         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1482         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1483         struct rte_eth_link link;
1484         int ret;
1485
1486         eth_dev->data->dev_started = 0;
1487         eth_dev->data->scattered_rx = 0;
1488
1489         /* Prevent crashes when queues are still in use */
1490         eth_dev->rx_pkt_burst = &bnxt_dummy_recv_pkts;
1491         eth_dev->tx_pkt_burst = &bnxt_dummy_xmit_pkts;
1492
1493         bnxt_disable_int(bp);
1494
1495         /* disable uio/vfio intr/eventfd mapping */
1496         rte_intr_disable(intr_handle);
1497
1498         /* Stop the child representors for this device */
1499         ret = bnxt_rep_stop_all(bp);
1500         if (ret != 0)
1501                 return ret;
1502
1503         /* delete the bnxt ULP port details */
1504         bnxt_ulp_port_deinit(bp);
1505
1506         bnxt_cancel_fw_health_check(bp);
1507
1508         if (BNXT_P5_PTP_TIMESYNC_ENABLED(bp))
1509                 bnxt_cancel_ptp_alarm(bp);
1510
1511         /* Do not bring link down during reset recovery */
1512         if (!is_bnxt_in_error(bp)) {
1513                 bnxt_dev_set_link_down_op(eth_dev);
1514                 /* Wait for link to be reset */
1515                 if (BNXT_SINGLE_PF(bp))
1516                         rte_delay_ms(500);
1517                 /* clear the recorded link status */
1518                 memset(&link, 0, sizeof(link));
1519                 rte_eth_linkstatus_set(eth_dev, &link);
1520         }
1521
1522         /* Clean queue intr-vector mapping */
1523         rte_intr_efd_disable(intr_handle);
1524         if (intr_handle->intr_vec != NULL) {
1525                 rte_free(intr_handle->intr_vec);
1526                 intr_handle->intr_vec = NULL;
1527         }
1528
1529         bnxt_hwrm_port_clr_stats(bp);
1530         bnxt_free_tx_mbufs(bp);
1531         bnxt_free_rx_mbufs(bp);
1532         /* Process any remaining notifications in default completion queue */
1533         bnxt_int_handler(eth_dev);
1534         bnxt_shutdown_nic(bp);
1535         bnxt_hwrm_if_change(bp, false);
1536
1537         bnxt_free_prev_ring_stats(bp);
1538         rte_free(bp->mark_table);
1539         bp->mark_table = NULL;
1540
1541         bp->flags &= ~BNXT_FLAG_RX_VECTOR_PKT_MODE;
1542         bp->rx_cosq_cnt = 0;
1543         /* All filters are deleted on a port stop. */
1544         if (BNXT_FLOW_XSTATS_EN(bp))
1545                 bp->flow_stat->flow_count = 0;
1546
1547         return 0;
1548 }
1549
1550 /* Unload the driver, release resources */
1551 static int bnxt_dev_stop_op(struct rte_eth_dev *eth_dev)
1552 {
1553         struct bnxt *bp = eth_dev->data->dev_private;
1554
1555         pthread_mutex_lock(&bp->err_recovery_lock);
1556         if (bp->flags & BNXT_FLAG_FW_RESET) {
1557                 PMD_DRV_LOG(ERR,
1558                             "Adapter recovering from error..Please retry\n");
1559                 pthread_mutex_unlock(&bp->err_recovery_lock);
1560                 return -EAGAIN;
1561         }
1562         pthread_mutex_unlock(&bp->err_recovery_lock);
1563
1564         return bnxt_dev_stop(eth_dev);
1565 }
1566
1567 static int bnxt_dev_start_op(struct rte_eth_dev *eth_dev)
1568 {
1569         struct bnxt *bp = eth_dev->data->dev_private;
1570         uint64_t rx_offloads = eth_dev->data->dev_conf.rxmode.offloads;
1571         int vlan_mask = 0;
1572         int rc, retry_cnt = BNXT_IF_CHANGE_RETRY_COUNT;
1573
1574         if (!eth_dev->data->nb_tx_queues || !eth_dev->data->nb_rx_queues) {
1575                 PMD_DRV_LOG(ERR, "Queues are not configured yet!\n");
1576                 return -EINVAL;
1577         }
1578
1579         if (bp->rx_cp_nr_rings > RTE_ETHDEV_QUEUE_STAT_CNTRS)
1580                 PMD_DRV_LOG(ERR,
1581                             "RxQ cnt %d > RTE_ETHDEV_QUEUE_STAT_CNTRS %d\n",
1582                             bp->rx_cp_nr_rings, RTE_ETHDEV_QUEUE_STAT_CNTRS);
1583
1584         do {
1585                 rc = bnxt_hwrm_if_change(bp, true);
1586                 if (rc == 0 || rc != -EAGAIN)
1587                         break;
1588
1589                 rte_delay_ms(BNXT_IF_CHANGE_RETRY_INTERVAL);
1590         } while (retry_cnt--);
1591
1592         if (rc)
1593                 return rc;
1594
1595         if (bp->flags & BNXT_FLAG_IF_CHANGE_HOT_FW_RESET_DONE) {
1596                 rc = bnxt_handle_if_change_status(bp);
1597                 if (rc)
1598                         return rc;
1599         }
1600
1601         bnxt_enable_int(bp);
1602
1603         eth_dev->data->scattered_rx = bnxt_scattered_rx(eth_dev);
1604
1605         rc = bnxt_start_nic(bp);
1606         if (rc)
1607                 goto error;
1608
1609         rc = bnxt_alloc_prev_ring_stats(bp);
1610         if (rc)
1611                 goto error;
1612
1613         eth_dev->data->dev_started = 1;
1614
1615         bnxt_link_update_op(eth_dev, 1);
1616
1617         if (rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER)
1618                 vlan_mask |= ETH_VLAN_FILTER_MASK;
1619         if (rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
1620                 vlan_mask |= ETH_VLAN_STRIP_MASK;
1621         rc = bnxt_vlan_offload_set_op(eth_dev, vlan_mask);
1622         if (rc)
1623                 goto error;
1624
1625         /* Initialize bnxt ULP port details */
1626         rc = bnxt_ulp_port_init(bp);
1627         if (rc)
1628                 goto error;
1629
1630         eth_dev->rx_pkt_burst = bnxt_receive_function(eth_dev);
1631         eth_dev->tx_pkt_burst = bnxt_transmit_function(eth_dev);
1632
1633         bnxt_schedule_fw_health_check(bp);
1634
1635         if (BNXT_P5_PTP_TIMESYNC_ENABLED(bp))
1636                 bnxt_schedule_ptp_alarm(bp);
1637
1638         return 0;
1639
1640 error:
1641         bnxt_dev_stop(eth_dev);
1642         return rc;
1643 }
1644
1645 static void
1646 bnxt_uninit_locks(struct bnxt *bp)
1647 {
1648         pthread_mutex_destroy(&bp->flow_lock);
1649         pthread_mutex_destroy(&bp->def_cp_lock);
1650         pthread_mutex_destroy(&bp->health_check_lock);
1651         pthread_mutex_destroy(&bp->err_recovery_lock);
1652         if (bp->rep_info) {
1653                 pthread_mutex_destroy(&bp->rep_info->vfr_lock);
1654                 pthread_mutex_destroy(&bp->rep_info->vfr_start_lock);
1655         }
1656 }
1657
1658 static void bnxt_drv_uninit(struct bnxt *bp)
1659 {
1660         bnxt_free_leds_info(bp);
1661         bnxt_free_cos_queues(bp);
1662         bnxt_free_link_info(bp);
1663         bnxt_free_parent_info(bp);
1664         bnxt_uninit_locks(bp);
1665
1666         rte_memzone_free((const struct rte_memzone *)bp->tx_mem_zone);
1667         bp->tx_mem_zone = NULL;
1668         rte_memzone_free((const struct rte_memzone *)bp->rx_mem_zone);
1669         bp->rx_mem_zone = NULL;
1670
1671         bnxt_free_vf_info(bp);
1672         bnxt_free_pf_info(bp);
1673
1674         rte_free(bp->grp_info);
1675         bp->grp_info = NULL;
1676 }
1677
1678 static int bnxt_dev_close_op(struct rte_eth_dev *eth_dev)
1679 {
1680         struct bnxt *bp = eth_dev->data->dev_private;
1681         int ret = 0;
1682
1683         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1684                 return 0;
1685
1686         pthread_mutex_lock(&bp->err_recovery_lock);
1687         if (bp->flags & BNXT_FLAG_FW_RESET) {
1688                 PMD_DRV_LOG(ERR,
1689                             "Adapter recovering from error...Please retry\n");
1690                 pthread_mutex_unlock(&bp->err_recovery_lock);
1691                 return -EAGAIN;
1692         }
1693         pthread_mutex_unlock(&bp->err_recovery_lock);
1694
1695         /* cancel the recovery handler before remove dev */
1696         rte_eal_alarm_cancel(bnxt_dev_reset_and_resume, (void *)bp);
1697         rte_eal_alarm_cancel(bnxt_dev_recover, (void *)bp);
1698         bnxt_cancel_fc_thread(bp);
1699
1700         if (eth_dev->data->dev_started)
1701                 ret = bnxt_dev_stop(eth_dev);
1702
1703         bnxt_uninit_resources(bp, false);
1704
1705         bnxt_drv_uninit(bp);
1706
1707         return ret;
1708 }
1709
1710 static void bnxt_mac_addr_remove_op(struct rte_eth_dev *eth_dev,
1711                                     uint32_t index)
1712 {
1713         struct bnxt *bp = eth_dev->data->dev_private;
1714         uint64_t pool_mask = eth_dev->data->mac_pool_sel[index];
1715         struct bnxt_vnic_info *vnic;
1716         struct bnxt_filter_info *filter, *temp_filter;
1717         uint32_t i;
1718
1719         if (is_bnxt_in_error(bp))
1720                 return;
1721
1722         /*
1723          * Loop through all VNICs from the specified filter flow pools to
1724          * remove the corresponding MAC addr filter
1725          */
1726         for (i = 0; i < bp->nr_vnics; i++) {
1727                 if (!(pool_mask & (1ULL << i)))
1728                         continue;
1729
1730                 vnic = &bp->vnic_info[i];
1731                 filter = STAILQ_FIRST(&vnic->filter);
1732                 while (filter) {
1733                         temp_filter = STAILQ_NEXT(filter, next);
1734                         if (filter->mac_index == index) {
1735                                 STAILQ_REMOVE(&vnic->filter, filter,
1736                                                 bnxt_filter_info, next);
1737                                 bnxt_hwrm_clear_l2_filter(bp, filter);
1738                                 bnxt_free_filter(bp, filter);
1739                         }
1740                         filter = temp_filter;
1741                 }
1742         }
1743 }
1744
1745 static int bnxt_add_mac_filter(struct bnxt *bp, struct bnxt_vnic_info *vnic,
1746                                struct rte_ether_addr *mac_addr, uint32_t index,
1747                                uint32_t pool)
1748 {
1749         struct bnxt_filter_info *filter;
1750         int rc = 0;
1751
1752         /* Attach requested MAC address to the new l2_filter */
1753         STAILQ_FOREACH(filter, &vnic->filter, next) {
1754                 if (filter->mac_index == index) {
1755                         PMD_DRV_LOG(DEBUG,
1756                                     "MAC addr already existed for pool %d\n",
1757                                     pool);
1758                         return 0;
1759                 }
1760         }
1761
1762         filter = bnxt_alloc_filter(bp);
1763         if (!filter) {
1764                 PMD_DRV_LOG(ERR, "L2 filter alloc failed\n");
1765                 return -ENODEV;
1766         }
1767
1768         /* bnxt_alloc_filter copies default MAC to filter->l2_addr. So,
1769          * if the MAC that's been programmed now is a different one, then,
1770          * copy that addr to filter->l2_addr
1771          */
1772         if (mac_addr)
1773                 memcpy(filter->l2_addr, mac_addr, RTE_ETHER_ADDR_LEN);
1774         filter->flags |= HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_OUTERMOST;
1775
1776         rc = bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id, filter);
1777         if (!rc) {
1778                 filter->mac_index = index;
1779                 if (filter->mac_index == 0)
1780                         STAILQ_INSERT_HEAD(&vnic->filter, filter, next);
1781                 else
1782                         STAILQ_INSERT_TAIL(&vnic->filter, filter, next);
1783         } else {
1784                 bnxt_free_filter(bp, filter);
1785         }
1786
1787         return rc;
1788 }
1789
1790 static int bnxt_mac_addr_add_op(struct rte_eth_dev *eth_dev,
1791                                 struct rte_ether_addr *mac_addr,
1792                                 uint32_t index, uint32_t pool)
1793 {
1794         struct bnxt *bp = eth_dev->data->dev_private;
1795         struct bnxt_vnic_info *vnic = &bp->vnic_info[pool];
1796         int rc = 0;
1797
1798         rc = is_bnxt_in_error(bp);
1799         if (rc)
1800                 return rc;
1801
1802         if (BNXT_VF(bp) && !BNXT_VF_IS_TRUSTED(bp)) {
1803                 PMD_DRV_LOG(ERR, "Cannot add MAC address to a VF interface\n");
1804                 return -ENOTSUP;
1805         }
1806
1807         if (!vnic) {
1808                 PMD_DRV_LOG(ERR, "VNIC not found for pool %d!\n", pool);
1809                 return -EINVAL;
1810         }
1811
1812         /* Filter settings will get applied when port is started */
1813         if (!eth_dev->data->dev_started)
1814                 return 0;
1815
1816         rc = bnxt_add_mac_filter(bp, vnic, mac_addr, index, pool);
1817
1818         return rc;
1819 }
1820
1821 int bnxt_link_update_op(struct rte_eth_dev *eth_dev, int wait_to_complete)
1822 {
1823         int rc = 0;
1824         struct bnxt *bp = eth_dev->data->dev_private;
1825         struct rte_eth_link new;
1826         int cnt = wait_to_complete ? BNXT_MAX_LINK_WAIT_CNT :
1827                         BNXT_MIN_LINK_WAIT_CNT;
1828
1829         rc = is_bnxt_in_error(bp);
1830         if (rc)
1831                 return rc;
1832
1833         memset(&new, 0, sizeof(new));
1834
1835         if (bp->link_info == NULL)
1836                 goto out;
1837
1838         do {
1839                 /* Retrieve link info from hardware */
1840                 rc = bnxt_get_hwrm_link_config(bp, &new);
1841                 if (rc) {
1842                         new.link_speed = ETH_LINK_SPEED_100M;
1843                         new.link_duplex = ETH_LINK_FULL_DUPLEX;
1844                         PMD_DRV_LOG(ERR,
1845                                 "Failed to retrieve link rc = 0x%x!\n", rc);
1846                         goto out;
1847                 }
1848
1849                 if (!wait_to_complete || new.link_status)
1850                         break;
1851
1852                 rte_delay_ms(BNXT_LINK_WAIT_INTERVAL);
1853         } while (cnt--);
1854
1855         /* Only single function PF can bring phy down.
1856          * When port is stopped, report link down for VF/MH/NPAR functions.
1857          */
1858         if (!BNXT_SINGLE_PF(bp) && !eth_dev->data->dev_started)
1859                 memset(&new, 0, sizeof(new));
1860
1861 out:
1862         /* Timed out or success */
1863         if (new.link_status != eth_dev->data->dev_link.link_status ||
1864             new.link_speed != eth_dev->data->dev_link.link_speed) {
1865                 rte_eth_linkstatus_set(eth_dev, &new);
1866                 bnxt_print_link_info(eth_dev);
1867         }
1868
1869         return rc;
1870 }
1871
1872 static int bnxt_promiscuous_enable_op(struct rte_eth_dev *eth_dev)
1873 {
1874         struct bnxt *bp = eth_dev->data->dev_private;
1875         struct bnxt_vnic_info *vnic;
1876         uint32_t old_flags;
1877         int rc;
1878
1879         rc = is_bnxt_in_error(bp);
1880         if (rc)
1881                 return rc;
1882
1883         /* Filter settings will get applied when port is started */
1884         if (!eth_dev->data->dev_started)
1885                 return 0;
1886
1887         if (bp->vnic_info == NULL)
1888                 return 0;
1889
1890         vnic = BNXT_GET_DEFAULT_VNIC(bp);
1891
1892         old_flags = vnic->flags;
1893         vnic->flags |= BNXT_VNIC_INFO_PROMISC;
1894         rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1895         if (rc != 0)
1896                 vnic->flags = old_flags;
1897
1898         return rc;
1899 }
1900
1901 static int bnxt_promiscuous_disable_op(struct rte_eth_dev *eth_dev)
1902 {
1903         struct bnxt *bp = eth_dev->data->dev_private;
1904         struct bnxt_vnic_info *vnic;
1905         uint32_t old_flags;
1906         int rc;
1907
1908         rc = is_bnxt_in_error(bp);
1909         if (rc)
1910                 return rc;
1911
1912         /* Filter settings will get applied when port is started */
1913         if (!eth_dev->data->dev_started)
1914                 return 0;
1915
1916         if (bp->vnic_info == NULL)
1917                 return 0;
1918
1919         vnic = BNXT_GET_DEFAULT_VNIC(bp);
1920
1921         old_flags = vnic->flags;
1922         vnic->flags &= ~BNXT_VNIC_INFO_PROMISC;
1923         rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1924         if (rc != 0)
1925                 vnic->flags = old_flags;
1926
1927         return rc;
1928 }
1929
1930 static int bnxt_allmulticast_enable_op(struct rte_eth_dev *eth_dev)
1931 {
1932         struct bnxt *bp = eth_dev->data->dev_private;
1933         struct bnxt_vnic_info *vnic;
1934         uint32_t old_flags;
1935         int rc;
1936
1937         rc = is_bnxt_in_error(bp);
1938         if (rc)
1939                 return rc;
1940
1941         /* Filter settings will get applied when port is started */
1942         if (!eth_dev->data->dev_started)
1943                 return 0;
1944
1945         if (bp->vnic_info == NULL)
1946                 return 0;
1947
1948         vnic = BNXT_GET_DEFAULT_VNIC(bp);
1949
1950         old_flags = vnic->flags;
1951         vnic->flags |= BNXT_VNIC_INFO_ALLMULTI;
1952         rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1953         if (rc != 0)
1954                 vnic->flags = old_flags;
1955
1956         return rc;
1957 }
1958
1959 static int bnxt_allmulticast_disable_op(struct rte_eth_dev *eth_dev)
1960 {
1961         struct bnxt *bp = eth_dev->data->dev_private;
1962         struct bnxt_vnic_info *vnic;
1963         uint32_t old_flags;
1964         int rc;
1965
1966         rc = is_bnxt_in_error(bp);
1967         if (rc)
1968                 return rc;
1969
1970         /* Filter settings will get applied when port is started */
1971         if (!eth_dev->data->dev_started)
1972                 return 0;
1973
1974         if (bp->vnic_info == NULL)
1975                 return 0;
1976
1977         vnic = BNXT_GET_DEFAULT_VNIC(bp);
1978
1979         old_flags = vnic->flags;
1980         vnic->flags &= ~BNXT_VNIC_INFO_ALLMULTI;
1981         rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1982         if (rc != 0)
1983                 vnic->flags = old_flags;
1984
1985         return rc;
1986 }
1987
1988 /* Return bnxt_rx_queue pointer corresponding to a given rxq. */
1989 static struct bnxt_rx_queue *bnxt_qid_to_rxq(struct bnxt *bp, uint16_t qid)
1990 {
1991         if (qid >= bp->rx_nr_rings)
1992                 return NULL;
1993
1994         return bp->eth_dev->data->rx_queues[qid];
1995 }
1996
1997 /* Return rxq corresponding to a given rss table ring/group ID. */
1998 static uint16_t bnxt_rss_to_qid(struct bnxt *bp, uint16_t fwr)
1999 {
2000         struct bnxt_rx_queue *rxq;
2001         unsigned int i;
2002
2003         if (!BNXT_HAS_RING_GRPS(bp)) {
2004                 for (i = 0; i < bp->rx_nr_rings; i++) {
2005                         rxq = bp->eth_dev->data->rx_queues[i];
2006                         if (rxq->rx_ring->rx_ring_struct->fw_ring_id == fwr)
2007                                 return rxq->index;
2008                 }
2009         } else {
2010                 for (i = 0; i < bp->rx_nr_rings; i++) {
2011                         if (bp->grp_info[i].fw_grp_id == fwr)
2012                                 return i;
2013                 }
2014         }
2015
2016         return INVALID_HW_RING_ID;
2017 }
2018
2019 static int bnxt_reta_update_op(struct rte_eth_dev *eth_dev,
2020                             struct rte_eth_rss_reta_entry64 *reta_conf,
2021                             uint16_t reta_size)
2022 {
2023         struct bnxt *bp = eth_dev->data->dev_private;
2024         struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
2025         struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp);
2026         uint16_t tbl_size = bnxt_rss_hash_tbl_size(bp);
2027         uint16_t idx, sft;
2028         int i, rc;
2029
2030         rc = is_bnxt_in_error(bp);
2031         if (rc)
2032                 return rc;
2033
2034         if (!vnic->rss_table)
2035                 return -EINVAL;
2036
2037         if (!(dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG))
2038                 return -EINVAL;
2039
2040         if (reta_size != tbl_size) {
2041                 PMD_DRV_LOG(ERR, "The configured hash table lookup size "
2042                         "(%d) must equal the size supported by the hardware "
2043                         "(%d)\n", reta_size, tbl_size);
2044                 return -EINVAL;
2045         }
2046
2047         for (i = 0; i < reta_size; i++) {
2048                 struct bnxt_rx_queue *rxq;
2049
2050                 idx = i / RTE_RETA_GROUP_SIZE;
2051                 sft = i % RTE_RETA_GROUP_SIZE;
2052
2053                 if (!(reta_conf[idx].mask & (1ULL << sft)))
2054                         continue;
2055
2056                 rxq = bnxt_qid_to_rxq(bp, reta_conf[idx].reta[sft]);
2057                 if (!rxq) {
2058                         PMD_DRV_LOG(ERR, "Invalid ring in reta_conf.\n");
2059                         return -EINVAL;
2060                 }
2061
2062                 if (BNXT_CHIP_P5(bp)) {
2063                         vnic->rss_table[i * 2] =
2064                                 rxq->rx_ring->rx_ring_struct->fw_ring_id;
2065                         vnic->rss_table[i * 2 + 1] =
2066                                 rxq->cp_ring->cp_ring_struct->fw_ring_id;
2067                 } else {
2068                         vnic->rss_table[i] =
2069                             vnic->fw_grp_ids[reta_conf[idx].reta[sft]];
2070                 }
2071         }
2072
2073         rc = bnxt_hwrm_vnic_rss_cfg(bp, vnic);
2074         return rc;
2075 }
2076
2077 static int bnxt_reta_query_op(struct rte_eth_dev *eth_dev,
2078                               struct rte_eth_rss_reta_entry64 *reta_conf,
2079                               uint16_t reta_size)
2080 {
2081         struct bnxt *bp = eth_dev->data->dev_private;
2082         struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp);
2083         uint16_t tbl_size = bnxt_rss_hash_tbl_size(bp);
2084         uint16_t idx, sft, i;
2085         int rc;
2086
2087         rc = is_bnxt_in_error(bp);
2088         if (rc)
2089                 return rc;
2090
2091         if (!vnic)
2092                 return -EINVAL;
2093         if (!vnic->rss_table)
2094                 return -EINVAL;
2095
2096         if (reta_size != tbl_size) {
2097                 PMD_DRV_LOG(ERR, "The configured hash table lookup size "
2098                         "(%d) must equal the size supported by the hardware "
2099                         "(%d)\n", reta_size, tbl_size);
2100                 return -EINVAL;
2101         }
2102
2103         for (idx = 0, i = 0; i < reta_size; i++) {
2104                 idx = i / RTE_RETA_GROUP_SIZE;
2105                 sft = i % RTE_RETA_GROUP_SIZE;
2106
2107                 if (reta_conf[idx].mask & (1ULL << sft)) {
2108                         uint16_t qid;
2109
2110                         if (BNXT_CHIP_P5(bp))
2111                                 qid = bnxt_rss_to_qid(bp,
2112                                                       vnic->rss_table[i * 2]);
2113                         else
2114                                 qid = bnxt_rss_to_qid(bp, vnic->rss_table[i]);
2115
2116                         if (qid == INVALID_HW_RING_ID) {
2117                                 PMD_DRV_LOG(ERR, "Inv. entry in rss table.\n");
2118                                 return -EINVAL;
2119                         }
2120                         reta_conf[idx].reta[sft] = qid;
2121                 }
2122         }
2123
2124         return 0;
2125 }
2126
2127 static int bnxt_rss_hash_update_op(struct rte_eth_dev *eth_dev,
2128                                    struct rte_eth_rss_conf *rss_conf)
2129 {
2130         struct bnxt *bp = eth_dev->data->dev_private;
2131         struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
2132         struct bnxt_vnic_info *vnic;
2133         int rc;
2134
2135         rc = is_bnxt_in_error(bp);
2136         if (rc)
2137                 return rc;
2138
2139         /*
2140          * If RSS enablement were different than dev_configure,
2141          * then return -EINVAL
2142          */
2143         if (dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG) {
2144                 if (!rss_conf->rss_hf)
2145                         PMD_DRV_LOG(ERR, "Hash type NONE\n");
2146         } else {
2147                 if (rss_conf->rss_hf & BNXT_ETH_RSS_SUPPORT)
2148                         return -EINVAL;
2149         }
2150
2151         bp->flags |= BNXT_FLAG_UPDATE_HASH;
2152         memcpy(&eth_dev->data->dev_conf.rx_adv_conf.rss_conf,
2153                rss_conf,
2154                sizeof(*rss_conf));
2155
2156         /* Update the default RSS VNIC(s) */
2157         vnic = BNXT_GET_DEFAULT_VNIC(bp);
2158         vnic->hash_type = bnxt_rte_to_hwrm_hash_types(rss_conf->rss_hf);
2159         vnic->hash_mode =
2160                 bnxt_rte_to_hwrm_hash_level(bp, rss_conf->rss_hf,
2161                                             ETH_RSS_LEVEL(rss_conf->rss_hf));
2162
2163         /*
2164          * If hashkey is not specified, use the previously configured
2165          * hashkey
2166          */
2167         if (!rss_conf->rss_key)
2168                 goto rss_config;
2169
2170         if (rss_conf->rss_key_len != HW_HASH_KEY_SIZE) {
2171                 PMD_DRV_LOG(ERR,
2172                             "Invalid hashkey length, should be %d bytes\n",
2173                             HW_HASH_KEY_SIZE);
2174                 return -EINVAL;
2175         }
2176         memcpy(vnic->rss_hash_key, rss_conf->rss_key, rss_conf->rss_key_len);
2177
2178 rss_config:
2179         rc = bnxt_hwrm_vnic_rss_cfg(bp, vnic);
2180         return rc;
2181 }
2182
2183 static int bnxt_rss_hash_conf_get_op(struct rte_eth_dev *eth_dev,
2184                                      struct rte_eth_rss_conf *rss_conf)
2185 {
2186         struct bnxt *bp = eth_dev->data->dev_private;
2187         struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp);
2188         int len, rc;
2189         uint32_t hash_types;
2190
2191         rc = is_bnxt_in_error(bp);
2192         if (rc)
2193                 return rc;
2194
2195         /* RSS configuration is the same for all VNICs */
2196         if (vnic && vnic->rss_hash_key) {
2197                 if (rss_conf->rss_key) {
2198                         len = rss_conf->rss_key_len <= HW_HASH_KEY_SIZE ?
2199                               rss_conf->rss_key_len : HW_HASH_KEY_SIZE;
2200                         memcpy(rss_conf->rss_key, vnic->rss_hash_key, len);
2201                 }
2202
2203                 hash_types = vnic->hash_type;
2204                 rss_conf->rss_hf = 0;
2205                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV4) {
2206                         rss_conf->rss_hf |= ETH_RSS_IPV4;
2207                         hash_types &= ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV4;
2208                 }
2209                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV4) {
2210                         rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP;
2211                         hash_types &=
2212                                 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV4;
2213                 }
2214                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV4) {
2215                         rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
2216                         hash_types &=
2217                                 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV4;
2218                 }
2219                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6) {
2220                         rss_conf->rss_hf |= ETH_RSS_IPV6;
2221                         hash_types &= ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6;
2222                 }
2223                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV6) {
2224                         rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV6_TCP;
2225                         hash_types &=
2226                                 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV6;
2227                 }
2228                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV6) {
2229                         rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;
2230                         hash_types &=
2231                                 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV6;
2232                 }
2233
2234                 rss_conf->rss_hf |=
2235                         bnxt_hwrm_to_rte_rss_level(bp, vnic->hash_mode);
2236
2237                 if (hash_types) {
2238                         PMD_DRV_LOG(ERR,
2239                                 "Unknown RSS config from firmware (%08x), RSS disabled",
2240                                 vnic->hash_type);
2241                         return -ENOTSUP;
2242                 }
2243         } else {
2244                 rss_conf->rss_hf = 0;
2245         }
2246         return 0;
2247 }
2248
2249 static int bnxt_flow_ctrl_get_op(struct rte_eth_dev *dev,
2250                                struct rte_eth_fc_conf *fc_conf)
2251 {
2252         struct bnxt *bp = dev->data->dev_private;
2253         struct rte_eth_link link_info;
2254         int rc;
2255
2256         rc = is_bnxt_in_error(bp);
2257         if (rc)
2258                 return rc;
2259
2260         rc = bnxt_get_hwrm_link_config(bp, &link_info);
2261         if (rc)
2262                 return rc;
2263
2264         memset(fc_conf, 0, sizeof(*fc_conf));
2265         if (bp->link_info->auto_pause)
2266                 fc_conf->autoneg = 1;
2267         switch (bp->link_info->pause) {
2268         case 0:
2269                 fc_conf->mode = RTE_FC_NONE;
2270                 break;
2271         case HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_TX:
2272                 fc_conf->mode = RTE_FC_TX_PAUSE;
2273                 break;
2274         case HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_RX:
2275                 fc_conf->mode = RTE_FC_RX_PAUSE;
2276                 break;
2277         case (HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_TX |
2278                         HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_RX):
2279                 fc_conf->mode = RTE_FC_FULL;
2280                 break;
2281         }
2282         return 0;
2283 }
2284
2285 static int bnxt_flow_ctrl_set_op(struct rte_eth_dev *dev,
2286                                struct rte_eth_fc_conf *fc_conf)
2287 {
2288         struct bnxt *bp = dev->data->dev_private;
2289         int rc;
2290
2291         rc = is_bnxt_in_error(bp);
2292         if (rc)
2293                 return rc;
2294
2295         if (!BNXT_SINGLE_PF(bp)) {
2296                 PMD_DRV_LOG(ERR,
2297                             "Flow Control Settings cannot be modified on VF or on shared PF\n");
2298                 return -ENOTSUP;
2299         }
2300
2301         switch (fc_conf->mode) {
2302         case RTE_FC_NONE:
2303                 bp->link_info->auto_pause = 0;
2304                 bp->link_info->force_pause = 0;
2305                 break;
2306         case RTE_FC_RX_PAUSE:
2307                 if (fc_conf->autoneg) {
2308                         bp->link_info->auto_pause =
2309                                         HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_RX;
2310                         bp->link_info->force_pause = 0;
2311                 } else {
2312                         bp->link_info->auto_pause = 0;
2313                         bp->link_info->force_pause =
2314                                         HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_RX;
2315                 }
2316                 break;
2317         case RTE_FC_TX_PAUSE:
2318                 if (fc_conf->autoneg) {
2319                         bp->link_info->auto_pause =
2320                                         HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_TX;
2321                         bp->link_info->force_pause = 0;
2322                 } else {
2323                         bp->link_info->auto_pause = 0;
2324                         bp->link_info->force_pause =
2325                                         HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_TX;
2326                 }
2327                 break;
2328         case RTE_FC_FULL:
2329                 if (fc_conf->autoneg) {
2330                         bp->link_info->auto_pause =
2331                                         HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_TX |
2332                                         HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_RX;
2333                         bp->link_info->force_pause = 0;
2334                 } else {
2335                         bp->link_info->auto_pause = 0;
2336                         bp->link_info->force_pause =
2337                                         HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_TX |
2338                                         HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_RX;
2339                 }
2340                 break;
2341         }
2342         return bnxt_set_hwrm_link_config(bp, true);
2343 }
2344
2345 /* Add UDP tunneling port */
2346 static int
2347 bnxt_udp_tunnel_port_add_op(struct rte_eth_dev *eth_dev,
2348                          struct rte_eth_udp_tunnel *udp_tunnel)
2349 {
2350         struct bnxt *bp = eth_dev->data->dev_private;
2351         uint16_t tunnel_type = 0;
2352         int rc = 0;
2353
2354         rc = is_bnxt_in_error(bp);
2355         if (rc)
2356                 return rc;
2357
2358         switch (udp_tunnel->prot_type) {
2359         case RTE_TUNNEL_TYPE_VXLAN:
2360                 if (bp->vxlan_port_cnt) {
2361                         PMD_DRV_LOG(ERR, "Tunnel Port %d already programmed\n",
2362                                 udp_tunnel->udp_port);
2363                         if (bp->vxlan_port != udp_tunnel->udp_port) {
2364                                 PMD_DRV_LOG(ERR, "Only one port allowed\n");
2365                                 return -ENOSPC;
2366                         }
2367                         bp->vxlan_port_cnt++;
2368                         return 0;
2369                 }
2370                 tunnel_type =
2371                         HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_VXLAN;
2372                 break;
2373         case RTE_TUNNEL_TYPE_GENEVE:
2374                 if (bp->geneve_port_cnt) {
2375                         PMD_DRV_LOG(ERR, "Tunnel Port %d already programmed\n",
2376                                 udp_tunnel->udp_port);
2377                         if (bp->geneve_port != udp_tunnel->udp_port) {
2378                                 PMD_DRV_LOG(ERR, "Only one port allowed\n");
2379                                 return -ENOSPC;
2380                         }
2381                         bp->geneve_port_cnt++;
2382                         return 0;
2383                 }
2384                 tunnel_type =
2385                         HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_GENEVE;
2386                 break;
2387         default:
2388                 PMD_DRV_LOG(ERR, "Tunnel type is not supported\n");
2389                 return -ENOTSUP;
2390         }
2391         rc = bnxt_hwrm_tunnel_dst_port_alloc(bp, udp_tunnel->udp_port,
2392                                              tunnel_type);
2393
2394         if (rc != 0)
2395                 return rc;
2396
2397         if (tunnel_type ==
2398             HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_VXLAN)
2399                 bp->vxlan_port_cnt++;
2400
2401         if (tunnel_type ==
2402             HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_GENEVE)
2403                 bp->geneve_port_cnt++;
2404
2405         return rc;
2406 }
2407
2408 static int
2409 bnxt_udp_tunnel_port_del_op(struct rte_eth_dev *eth_dev,
2410                          struct rte_eth_udp_tunnel *udp_tunnel)
2411 {
2412         struct bnxt *bp = eth_dev->data->dev_private;
2413         uint16_t tunnel_type = 0;
2414         uint16_t port = 0;
2415         int rc = 0;
2416
2417         rc = is_bnxt_in_error(bp);
2418         if (rc)
2419                 return rc;
2420
2421         switch (udp_tunnel->prot_type) {
2422         case RTE_TUNNEL_TYPE_VXLAN:
2423                 if (!bp->vxlan_port_cnt) {
2424                         PMD_DRV_LOG(ERR, "No Tunnel port configured yet\n");
2425                         return -EINVAL;
2426                 }
2427                 if (bp->vxlan_port != udp_tunnel->udp_port) {
2428                         PMD_DRV_LOG(ERR, "Req Port: %d. Configured port: %d\n",
2429                                 udp_tunnel->udp_port, bp->vxlan_port);
2430                         return -EINVAL;
2431                 }
2432                 if (--bp->vxlan_port_cnt)
2433                         return 0;
2434
2435                 tunnel_type =
2436                         HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN;
2437                 port = bp->vxlan_fw_dst_port_id;
2438                 break;
2439         case RTE_TUNNEL_TYPE_GENEVE:
2440                 if (!bp->geneve_port_cnt) {
2441                         PMD_DRV_LOG(ERR, "No Tunnel port configured yet\n");
2442                         return -EINVAL;
2443                 }
2444                 if (bp->geneve_port != udp_tunnel->udp_port) {
2445                         PMD_DRV_LOG(ERR, "Req Port: %d. Configured port: %d\n",
2446                                 udp_tunnel->udp_port, bp->geneve_port);
2447                         return -EINVAL;
2448                 }
2449                 if (--bp->geneve_port_cnt)
2450                         return 0;
2451
2452                 tunnel_type =
2453                         HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_GENEVE;
2454                 port = bp->geneve_fw_dst_port_id;
2455                 break;
2456         default:
2457                 PMD_DRV_LOG(ERR, "Tunnel type is not supported\n");
2458                 return -ENOTSUP;
2459         }
2460
2461         rc = bnxt_hwrm_tunnel_dst_port_free(bp, port, tunnel_type);
2462         return rc;
2463 }
2464
2465 static int bnxt_del_vlan_filter(struct bnxt *bp, uint16_t vlan_id)
2466 {
2467         struct bnxt_filter_info *filter;
2468         struct bnxt_vnic_info *vnic;
2469         int rc = 0;
2470         uint32_t chk = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN;
2471
2472         vnic = BNXT_GET_DEFAULT_VNIC(bp);
2473         filter = STAILQ_FIRST(&vnic->filter);
2474         while (filter) {
2475                 /* Search for this matching MAC+VLAN filter */
2476                 if (bnxt_vlan_filter_exists(bp, filter, chk, vlan_id)) {
2477                         /* Delete the filter */
2478                         rc = bnxt_hwrm_clear_l2_filter(bp, filter);
2479                         if (rc)
2480                                 return rc;
2481                         STAILQ_REMOVE(&vnic->filter, filter,
2482                                       bnxt_filter_info, next);
2483                         bnxt_free_filter(bp, filter);
2484                         PMD_DRV_LOG(INFO,
2485                                     "Deleted vlan filter for %d\n",
2486                                     vlan_id);
2487                         return 0;
2488                 }
2489                 filter = STAILQ_NEXT(filter, next);
2490         }
2491         return -ENOENT;
2492 }
2493
2494 static int bnxt_add_vlan_filter(struct bnxt *bp, uint16_t vlan_id)
2495 {
2496         struct bnxt_filter_info *filter;
2497         struct bnxt_vnic_info *vnic;
2498         int rc = 0;
2499         uint32_t en = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN |
2500                 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN_MASK;
2501         uint32_t chk = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN;
2502
2503         /* Implementation notes on the use of VNIC in this command:
2504          *
2505          * By default, these filters belong to default vnic for the function.
2506          * Once these filters are set up, only destination VNIC can be modified.
2507          * If the destination VNIC is not specified in this command,
2508          * then the HWRM shall only create an l2 context id.
2509          */
2510
2511         vnic = BNXT_GET_DEFAULT_VNIC(bp);
2512         filter = STAILQ_FIRST(&vnic->filter);
2513         /* Check if the VLAN has already been added */
2514         while (filter) {
2515                 if (bnxt_vlan_filter_exists(bp, filter, chk, vlan_id))
2516                         return -EEXIST;
2517
2518                 filter = STAILQ_NEXT(filter, next);
2519         }
2520
2521         /* No match found. Alloc a fresh filter and issue the L2_FILTER_ALLOC
2522          * command to create MAC+VLAN filter with the right flags, enables set.
2523          */
2524         filter = bnxt_alloc_filter(bp);
2525         if (!filter) {
2526                 PMD_DRV_LOG(ERR,
2527                             "MAC/VLAN filter alloc failed\n");
2528                 return -ENOMEM;
2529         }
2530         /* MAC + VLAN ID filter */
2531         /* If l2_ivlan == 0 and l2_ivlan_mask != 0, only
2532          * untagged packets are received
2533          *
2534          * If l2_ivlan != 0 and l2_ivlan_mask != 0, untagged
2535          * packets and only the programmed vlan's packets are received
2536          */
2537         filter->l2_ivlan = vlan_id;
2538         filter->l2_ivlan_mask = 0x0FFF;
2539         filter->enables |= en;
2540         filter->flags |= HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_OUTERMOST;
2541
2542         rc = bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id, filter);
2543         if (rc) {
2544                 /* Free the newly allocated filter as we were
2545                  * not able to create the filter in hardware.
2546                  */
2547                 bnxt_free_filter(bp, filter);
2548                 return rc;
2549         }
2550
2551         filter->mac_index = 0;
2552         /* Add this new filter to the list */
2553         if (vlan_id == 0)
2554                 STAILQ_INSERT_HEAD(&vnic->filter, filter, next);
2555         else
2556                 STAILQ_INSERT_TAIL(&vnic->filter, filter, next);
2557
2558         PMD_DRV_LOG(INFO,
2559                     "Added Vlan filter for %d\n", vlan_id);
2560         return rc;
2561 }
2562
2563 static int bnxt_vlan_filter_set_op(struct rte_eth_dev *eth_dev,
2564                 uint16_t vlan_id, int on)
2565 {
2566         struct bnxt *bp = eth_dev->data->dev_private;
2567         int rc;
2568
2569         rc = is_bnxt_in_error(bp);
2570         if (rc)
2571                 return rc;
2572
2573         if (!eth_dev->data->dev_started) {
2574                 PMD_DRV_LOG(ERR, "port must be started before setting vlan\n");
2575                 return -EINVAL;
2576         }
2577
2578         /* These operations apply to ALL existing MAC/VLAN filters */
2579         if (on)
2580                 return bnxt_add_vlan_filter(bp, vlan_id);
2581         else
2582                 return bnxt_del_vlan_filter(bp, vlan_id);
2583 }
2584
2585 static int bnxt_del_dflt_mac_filter(struct bnxt *bp,
2586                                     struct bnxt_vnic_info *vnic)
2587 {
2588         struct bnxt_filter_info *filter;
2589         int rc;
2590
2591         filter = STAILQ_FIRST(&vnic->filter);
2592         while (filter) {
2593                 if (filter->mac_index == 0 &&
2594                     !memcmp(filter->l2_addr, bp->mac_addr,
2595                             RTE_ETHER_ADDR_LEN)) {
2596                         rc = bnxt_hwrm_clear_l2_filter(bp, filter);
2597                         if (!rc) {
2598                                 STAILQ_REMOVE(&vnic->filter, filter,
2599                                               bnxt_filter_info, next);
2600                                 bnxt_free_filter(bp, filter);
2601                         }
2602                         return rc;
2603                 }
2604                 filter = STAILQ_NEXT(filter, next);
2605         }
2606         return 0;
2607 }
2608
2609 static int
2610 bnxt_config_vlan_hw_filter(struct bnxt *bp, uint64_t rx_offloads)
2611 {
2612         struct bnxt_vnic_info *vnic;
2613         unsigned int i;
2614         int rc;
2615
2616         vnic = BNXT_GET_DEFAULT_VNIC(bp);
2617         if (!(rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER)) {
2618                 /* Remove any VLAN filters programmed */
2619                 for (i = 0; i < RTE_ETHER_MAX_VLAN_ID; i++)
2620                         bnxt_del_vlan_filter(bp, i);
2621
2622                 rc = bnxt_add_mac_filter(bp, vnic, NULL, 0, 0);
2623                 if (rc)
2624                         return rc;
2625         } else {
2626                 /* Default filter will allow packets that match the
2627                  * dest mac. So, it has to be deleted, otherwise, we
2628                  * will endup receiving vlan packets for which the
2629                  * filter is not programmed, when hw-vlan-filter
2630                  * configuration is ON
2631                  */
2632                 bnxt_del_dflt_mac_filter(bp, vnic);
2633                 /* This filter will allow only untagged packets */
2634                 bnxt_add_vlan_filter(bp, 0);
2635         }
2636         PMD_DRV_LOG(DEBUG, "VLAN Filtering: %d\n",
2637                     !!(rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER));
2638
2639         return 0;
2640 }
2641
2642 static int bnxt_free_one_vnic(struct bnxt *bp, uint16_t vnic_id)
2643 {
2644         struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id];
2645         unsigned int i;
2646         int rc;
2647
2648         /* Destroy vnic filters and vnic */
2649         if (bp->eth_dev->data->dev_conf.rxmode.offloads &
2650             DEV_RX_OFFLOAD_VLAN_FILTER) {
2651                 for (i = 0; i < RTE_ETHER_MAX_VLAN_ID; i++)
2652                         bnxt_del_vlan_filter(bp, i);
2653         }
2654         bnxt_del_dflt_mac_filter(bp, vnic);
2655
2656         rc = bnxt_hwrm_vnic_ctx_free(bp, vnic);
2657         if (rc)
2658                 return rc;
2659
2660         rc = bnxt_hwrm_vnic_free(bp, vnic);
2661         if (rc)
2662                 return rc;
2663
2664         rte_free(vnic->fw_grp_ids);
2665         vnic->fw_grp_ids = NULL;
2666
2667         vnic->rx_queue_cnt = 0;
2668
2669         return 0;
2670 }
2671
2672 static int
2673 bnxt_config_vlan_hw_stripping(struct bnxt *bp, uint64_t rx_offloads)
2674 {
2675         struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp);
2676         int rc;
2677
2678         /* Destroy, recreate and reconfigure the default vnic */
2679         rc = bnxt_free_one_vnic(bp, 0);
2680         if (rc)
2681                 return rc;
2682
2683         /* default vnic 0 */
2684         rc = bnxt_setup_one_vnic(bp, 0);
2685         if (rc)
2686                 return rc;
2687
2688         if (bp->eth_dev->data->dev_conf.rxmode.offloads &
2689             DEV_RX_OFFLOAD_VLAN_FILTER) {
2690                 rc = bnxt_add_vlan_filter(bp, 0);
2691                 if (rc)
2692                         return rc;
2693                 rc = bnxt_restore_vlan_filters(bp);
2694                 if (rc)
2695                         return rc;
2696         } else {
2697                 rc = bnxt_add_mac_filter(bp, vnic, NULL, 0, 0);
2698                 if (rc)
2699                         return rc;
2700         }
2701
2702         rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
2703         if (rc)
2704                 return rc;
2705
2706         PMD_DRV_LOG(DEBUG, "VLAN Strip Offload: %d\n",
2707                     !!(rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP));
2708
2709         return rc;
2710 }
2711
2712 static int
2713 bnxt_vlan_offload_set_op(struct rte_eth_dev *dev, int mask)
2714 {
2715         uint64_t rx_offloads = dev->data->dev_conf.rxmode.offloads;
2716         struct bnxt *bp = dev->data->dev_private;
2717         int rc;
2718
2719         rc = is_bnxt_in_error(bp);
2720         if (rc)
2721                 return rc;
2722
2723         /* Filter settings will get applied when port is started */
2724         if (!dev->data->dev_started)
2725                 return 0;
2726
2727         if (mask & ETH_VLAN_FILTER_MASK) {
2728                 /* Enable or disable VLAN filtering */
2729                 rc = bnxt_config_vlan_hw_filter(bp, rx_offloads);
2730                 if (rc)
2731                         return rc;
2732         }
2733
2734         if (mask & ETH_VLAN_STRIP_MASK) {
2735                 /* Enable or disable VLAN stripping */
2736                 rc = bnxt_config_vlan_hw_stripping(bp, rx_offloads);
2737                 if (rc)
2738                         return rc;
2739         }
2740
2741         if (mask & ETH_VLAN_EXTEND_MASK) {
2742                 if (rx_offloads & DEV_RX_OFFLOAD_VLAN_EXTEND)
2743                         PMD_DRV_LOG(DEBUG, "Extend VLAN supported\n");
2744                 else
2745                         PMD_DRV_LOG(INFO, "Extend VLAN unsupported\n");
2746         }
2747
2748         return 0;
2749 }
2750
2751 static int
2752 bnxt_vlan_tpid_set_op(struct rte_eth_dev *dev, enum rte_vlan_type vlan_type,
2753                       uint16_t tpid)
2754 {
2755         struct bnxt *bp = dev->data->dev_private;
2756         int qinq = dev->data->dev_conf.rxmode.offloads &
2757                    DEV_RX_OFFLOAD_VLAN_EXTEND;
2758
2759         if (vlan_type != ETH_VLAN_TYPE_INNER &&
2760             vlan_type != ETH_VLAN_TYPE_OUTER) {
2761                 PMD_DRV_LOG(ERR,
2762                             "Unsupported vlan type.");
2763                 return -EINVAL;
2764         }
2765         if (!qinq) {
2766                 PMD_DRV_LOG(ERR,
2767                             "QinQ not enabled. Needs to be ON as we can "
2768                             "accelerate only outer vlan\n");
2769                 return -EINVAL;
2770         }
2771
2772         if (vlan_type == ETH_VLAN_TYPE_OUTER) {
2773                 switch (tpid) {
2774                 case RTE_ETHER_TYPE_QINQ:
2775                         bp->outer_tpid_bd =
2776                                 TX_BD_LONG_CFA_META_VLAN_TPID_TPID88A8;
2777                                 break;
2778                 case RTE_ETHER_TYPE_VLAN:
2779                         bp->outer_tpid_bd =
2780                                 TX_BD_LONG_CFA_META_VLAN_TPID_TPID8100;
2781                                 break;
2782                 case RTE_ETHER_TYPE_QINQ1:
2783                         bp->outer_tpid_bd =
2784                                 TX_BD_LONG_CFA_META_VLAN_TPID_TPID9100;
2785                                 break;
2786                 case RTE_ETHER_TYPE_QINQ2:
2787                         bp->outer_tpid_bd =
2788                                 TX_BD_LONG_CFA_META_VLAN_TPID_TPID9200;
2789                                 break;
2790                 case RTE_ETHER_TYPE_QINQ3:
2791                         bp->outer_tpid_bd =
2792                                  TX_BD_LONG_CFA_META_VLAN_TPID_TPID9300;
2793                                 break;
2794                 default:
2795                         PMD_DRV_LOG(ERR, "Invalid TPID: %x\n", tpid);
2796                         return -EINVAL;
2797                 }
2798                 bp->outer_tpid_bd |= tpid;
2799                 PMD_DRV_LOG(INFO, "outer_tpid_bd = %x\n", bp->outer_tpid_bd);
2800         } else if (vlan_type == ETH_VLAN_TYPE_INNER) {
2801                 PMD_DRV_LOG(ERR,
2802                             "Can accelerate only outer vlan in QinQ\n");
2803                 return -EINVAL;
2804         }
2805
2806         return 0;
2807 }
2808
2809 static int
2810 bnxt_set_default_mac_addr_op(struct rte_eth_dev *dev,
2811                              struct rte_ether_addr *addr)
2812 {
2813         struct bnxt *bp = dev->data->dev_private;
2814         /* Default Filter is tied to VNIC 0 */
2815         struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp);
2816         int rc;
2817
2818         rc = is_bnxt_in_error(bp);
2819         if (rc)
2820                 return rc;
2821
2822         if (BNXT_VF(bp) && !BNXT_VF_IS_TRUSTED(bp))
2823                 return -EPERM;
2824
2825         if (rte_is_zero_ether_addr(addr))
2826                 return -EINVAL;
2827
2828         /* Filter settings will get applied when port is started */
2829         if (!dev->data->dev_started)
2830                 return 0;
2831
2832         /* Check if the requested MAC is already added */
2833         if (memcmp(addr, bp->mac_addr, RTE_ETHER_ADDR_LEN) == 0)
2834                 return 0;
2835
2836         /* Destroy filter and re-create it */
2837         bnxt_del_dflt_mac_filter(bp, vnic);
2838
2839         memcpy(bp->mac_addr, addr, RTE_ETHER_ADDR_LEN);
2840         if (dev->data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_VLAN_FILTER) {
2841                 /* This filter will allow only untagged packets */
2842                 rc = bnxt_add_vlan_filter(bp, 0);
2843         } else {
2844                 rc = bnxt_add_mac_filter(bp, vnic, addr, 0, 0);
2845         }
2846
2847         PMD_DRV_LOG(DEBUG, "Set MAC addr\n");
2848         return rc;
2849 }
2850
2851 static int
2852 bnxt_dev_set_mc_addr_list_op(struct rte_eth_dev *eth_dev,
2853                           struct rte_ether_addr *mc_addr_set,
2854                           uint32_t nb_mc_addr)
2855 {
2856         struct bnxt *bp = eth_dev->data->dev_private;
2857         char *mc_addr_list = (char *)mc_addr_set;
2858         struct bnxt_vnic_info *vnic;
2859         uint32_t off = 0, i = 0;
2860         int rc;
2861
2862         rc = is_bnxt_in_error(bp);
2863         if (rc)
2864                 return rc;
2865
2866         vnic = BNXT_GET_DEFAULT_VNIC(bp);
2867
2868         if (nb_mc_addr > BNXT_MAX_MC_ADDRS) {
2869                 vnic->flags |= BNXT_VNIC_INFO_ALLMULTI;
2870                 goto allmulti;
2871         }
2872
2873         /* TODO Check for Duplicate mcast addresses */
2874         vnic->flags &= ~BNXT_VNIC_INFO_ALLMULTI;
2875         for (i = 0; i < nb_mc_addr; i++) {
2876                 memcpy(vnic->mc_list + off, &mc_addr_list[i],
2877                         RTE_ETHER_ADDR_LEN);
2878                 off += RTE_ETHER_ADDR_LEN;
2879         }
2880
2881         vnic->mc_addr_cnt = i;
2882         if (vnic->mc_addr_cnt)
2883                 vnic->flags |= BNXT_VNIC_INFO_MCAST;
2884         else
2885                 vnic->flags &= ~BNXT_VNIC_INFO_MCAST;
2886
2887 allmulti:
2888         return bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
2889 }
2890
2891 static int
2892 bnxt_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size)
2893 {
2894         struct bnxt *bp = dev->data->dev_private;
2895         uint8_t fw_major = (bp->fw_ver >> 24) & 0xff;
2896         uint8_t fw_minor = (bp->fw_ver >> 16) & 0xff;
2897         uint8_t fw_updt = (bp->fw_ver >> 8) & 0xff;
2898         uint8_t fw_rsvd = bp->fw_ver & 0xff;
2899         int ret;
2900
2901         ret = snprintf(fw_version, fw_size, "%d.%d.%d.%d",
2902                         fw_major, fw_minor, fw_updt, fw_rsvd);
2903         if (ret < 0)
2904                 return -EINVAL;
2905
2906         ret += 1; /* add the size of '\0' */
2907         if (fw_size < (size_t)ret)
2908                 return ret;
2909         else
2910                 return 0;
2911 }
2912
2913 static void
2914 bnxt_rxq_info_get_op(struct rte_eth_dev *dev, uint16_t queue_id,
2915         struct rte_eth_rxq_info *qinfo)
2916 {
2917         struct bnxt *bp = dev->data->dev_private;
2918         struct bnxt_rx_queue *rxq;
2919
2920         if (is_bnxt_in_error(bp))
2921                 return;
2922
2923         rxq = dev->data->rx_queues[queue_id];
2924
2925         qinfo->mp = rxq->mb_pool;
2926         qinfo->scattered_rx = dev->data->scattered_rx;
2927         qinfo->nb_desc = rxq->nb_rx_desc;
2928
2929         qinfo->conf.rx_free_thresh = rxq->rx_free_thresh;
2930         qinfo->conf.rx_drop_en = rxq->drop_en;
2931         qinfo->conf.rx_deferred_start = rxq->rx_deferred_start;
2932         qinfo->conf.offloads = dev->data->dev_conf.rxmode.offloads;
2933 }
2934
2935 static void
2936 bnxt_txq_info_get_op(struct rte_eth_dev *dev, uint16_t queue_id,
2937         struct rte_eth_txq_info *qinfo)
2938 {
2939         struct bnxt *bp = dev->data->dev_private;
2940         struct bnxt_tx_queue *txq;
2941
2942         if (is_bnxt_in_error(bp))
2943                 return;
2944
2945         txq = dev->data->tx_queues[queue_id];
2946
2947         qinfo->nb_desc = txq->nb_tx_desc;
2948
2949         qinfo->conf.tx_thresh.pthresh = txq->pthresh;
2950         qinfo->conf.tx_thresh.hthresh = txq->hthresh;
2951         qinfo->conf.tx_thresh.wthresh = txq->wthresh;
2952
2953         qinfo->conf.tx_free_thresh = txq->tx_free_thresh;
2954         qinfo->conf.tx_rs_thresh = 0;
2955         qinfo->conf.tx_deferred_start = txq->tx_deferred_start;
2956         qinfo->conf.offloads = txq->offloads;
2957 }
2958
2959 static const struct {
2960         eth_rx_burst_t pkt_burst;
2961         const char *info;
2962 } bnxt_rx_burst_info[] = {
2963         {bnxt_recv_pkts,                "Scalar"},
2964 #if defined(RTE_ARCH_X86)
2965         {bnxt_recv_pkts_vec,            "Vector SSE"},
2966 #endif
2967 #if defined(RTE_ARCH_X86) && defined(CC_AVX2_SUPPORT)
2968         {bnxt_recv_pkts_vec_avx2,       "Vector AVX2"},
2969 #endif
2970 #if defined(RTE_ARCH_ARM64)
2971         {bnxt_recv_pkts_vec,            "Vector Neon"},
2972 #endif
2973 };
2974
2975 static int
2976 bnxt_rx_burst_mode_get(struct rte_eth_dev *dev, __rte_unused uint16_t queue_id,
2977                        struct rte_eth_burst_mode *mode)
2978 {
2979         eth_rx_burst_t pkt_burst = dev->rx_pkt_burst;
2980         size_t i;
2981
2982         for (i = 0; i < RTE_DIM(bnxt_rx_burst_info); i++) {
2983                 if (pkt_burst == bnxt_rx_burst_info[i].pkt_burst) {
2984                         snprintf(mode->info, sizeof(mode->info), "%s",
2985                                  bnxt_rx_burst_info[i].info);
2986                         return 0;
2987                 }
2988         }
2989
2990         return -EINVAL;
2991 }
2992
2993 static const struct {
2994         eth_tx_burst_t pkt_burst;
2995         const char *info;
2996 } bnxt_tx_burst_info[] = {
2997         {bnxt_xmit_pkts,                "Scalar"},
2998 #if defined(RTE_ARCH_X86)
2999         {bnxt_xmit_pkts_vec,            "Vector SSE"},
3000 #endif
3001 #if defined(RTE_ARCH_X86) && defined(CC_AVX2_SUPPORT)
3002         {bnxt_xmit_pkts_vec_avx2,       "Vector AVX2"},
3003 #endif
3004 #if defined(RTE_ARCH_ARM64)
3005         {bnxt_xmit_pkts_vec,            "Vector Neon"},
3006 #endif
3007 };
3008
3009 static int
3010 bnxt_tx_burst_mode_get(struct rte_eth_dev *dev, __rte_unused uint16_t queue_id,
3011                        struct rte_eth_burst_mode *mode)
3012 {
3013         eth_tx_burst_t pkt_burst = dev->tx_pkt_burst;
3014         size_t i;
3015
3016         for (i = 0; i < RTE_DIM(bnxt_tx_burst_info); i++) {
3017                 if (pkt_burst == bnxt_tx_burst_info[i].pkt_burst) {
3018                         snprintf(mode->info, sizeof(mode->info), "%s",
3019                                  bnxt_tx_burst_info[i].info);
3020                         return 0;
3021                 }
3022         }
3023
3024         return -EINVAL;
3025 }
3026
3027 int bnxt_mtu_set_op(struct rte_eth_dev *eth_dev, uint16_t new_mtu)
3028 {
3029         uint32_t overhead = BNXT_MAX_PKT_LEN - BNXT_MAX_MTU;
3030         struct bnxt *bp = eth_dev->data->dev_private;
3031         uint32_t new_pkt_size;
3032         uint32_t rc = 0;
3033         uint32_t i;
3034
3035         rc = is_bnxt_in_error(bp);
3036         if (rc)
3037                 return rc;
3038
3039         /* Exit if receive queues are not configured yet */
3040         if (!eth_dev->data->nb_rx_queues)
3041                 return rc;
3042
3043         new_pkt_size = new_mtu + overhead;
3044
3045         /*
3046          * Disallow any MTU change that would require scattered receive support
3047          * if it is not already enabled.
3048          */
3049         if (eth_dev->data->dev_started &&
3050             !eth_dev->data->scattered_rx &&
3051             (new_pkt_size >
3052              eth_dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM)) {
3053                 PMD_DRV_LOG(ERR,
3054                             "MTU change would require scattered rx support. ");
3055                 PMD_DRV_LOG(ERR, "Stop port before changing MTU.\n");
3056                 return -EINVAL;
3057         }
3058
3059         if (new_mtu > RTE_ETHER_MTU) {
3060                 bp->flags |= BNXT_FLAG_JUMBO;
3061                 bp->eth_dev->data->dev_conf.rxmode.offloads |=
3062                         DEV_RX_OFFLOAD_JUMBO_FRAME;
3063         } else {
3064                 bp->eth_dev->data->dev_conf.rxmode.offloads &=
3065                         ~DEV_RX_OFFLOAD_JUMBO_FRAME;
3066                 bp->flags &= ~BNXT_FLAG_JUMBO;
3067         }
3068
3069         /* Is there a change in mtu setting? */
3070         if (eth_dev->data->mtu == new_mtu)
3071                 return rc;
3072
3073         for (i = 0; i < bp->nr_vnics; i++) {
3074                 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
3075                 uint16_t size = 0;
3076
3077                 vnic->mru = BNXT_VNIC_MRU(new_mtu);
3078                 rc = bnxt_hwrm_vnic_cfg(bp, vnic);
3079                 if (rc)
3080                         break;
3081
3082                 size = rte_pktmbuf_data_room_size(bp->rx_queues[0]->mb_pool);
3083                 size -= RTE_PKTMBUF_HEADROOM;
3084
3085                 if (size < new_mtu) {
3086                         rc = bnxt_hwrm_vnic_plcmode_cfg(bp, vnic);
3087                         if (rc)
3088                                 return rc;
3089                 }
3090         }
3091
3092         if (bnxt_hwrm_config_host_mtu(bp))
3093                 PMD_DRV_LOG(WARNING, "Failed to configure host MTU\n");
3094
3095         PMD_DRV_LOG(INFO, "New MTU is %d\n", new_mtu);
3096
3097         return rc;
3098 }
3099
3100 static int
3101 bnxt_vlan_pvid_set_op(struct rte_eth_dev *dev, uint16_t pvid, int on)
3102 {
3103         struct bnxt *bp = dev->data->dev_private;
3104         uint16_t vlan = bp->vlan;
3105         int rc;
3106
3107         rc = is_bnxt_in_error(bp);
3108         if (rc)
3109                 return rc;
3110
3111         if (!BNXT_SINGLE_PF(bp)) {
3112                 PMD_DRV_LOG(ERR, "PVID cannot be modified on VF or on shared PF\n");
3113                 return -ENOTSUP;
3114         }
3115         bp->vlan = on ? pvid : 0;
3116
3117         rc = bnxt_hwrm_set_default_vlan(bp, 0, 0);
3118         if (rc)
3119                 bp->vlan = vlan;
3120         return rc;
3121 }
3122
3123 static int
3124 bnxt_dev_led_on_op(struct rte_eth_dev *dev)
3125 {
3126         struct bnxt *bp = dev->data->dev_private;
3127         int rc;
3128
3129         rc = is_bnxt_in_error(bp);
3130         if (rc)
3131                 return rc;
3132
3133         return bnxt_hwrm_port_led_cfg(bp, true);
3134 }
3135
3136 static int
3137 bnxt_dev_led_off_op(struct rte_eth_dev *dev)
3138 {
3139         struct bnxt *bp = dev->data->dev_private;
3140         int rc;
3141
3142         rc = is_bnxt_in_error(bp);
3143         if (rc)
3144                 return rc;
3145
3146         return bnxt_hwrm_port_led_cfg(bp, false);
3147 }
3148
3149 static uint32_t
3150 bnxt_rx_queue_count_op(void *rx_queue)
3151 {
3152         struct bnxt *bp;
3153         struct bnxt_cp_ring_info *cpr;
3154         uint32_t desc = 0, raw_cons, cp_ring_size;
3155         struct bnxt_rx_queue *rxq;
3156         struct rx_pkt_cmpl *rxcmp;
3157         int rc;
3158
3159         rxq = rx_queue;
3160         bp = rxq->bp;
3161
3162         rc = is_bnxt_in_error(bp);
3163         if (rc)
3164                 return rc;
3165
3166         cpr = rxq->cp_ring;
3167         raw_cons = cpr->cp_raw_cons;
3168         cp_ring_size = cpr->cp_ring_struct->ring_size;
3169
3170         while (1) {
3171                 uint32_t agg_cnt, cons, cmpl_type;
3172
3173                 cons = RING_CMP(cpr->cp_ring_struct, raw_cons);
3174                 rxcmp = (struct rx_pkt_cmpl *)&cpr->cp_desc_ring[cons];
3175
3176                 if (!bnxt_cpr_cmp_valid(rxcmp, raw_cons, cp_ring_size))
3177                         break;
3178
3179                 cmpl_type = CMP_TYPE(rxcmp);
3180
3181                 switch (cmpl_type) {
3182                 case CMPL_BASE_TYPE_RX_L2:
3183                 case CMPL_BASE_TYPE_RX_L2_V2:
3184                         agg_cnt = BNXT_RX_L2_AGG_BUFS(rxcmp);
3185                         raw_cons = raw_cons + CMP_LEN(cmpl_type) + agg_cnt;
3186                         desc++;
3187                         break;
3188
3189                 case CMPL_BASE_TYPE_RX_TPA_END:
3190                         if (BNXT_CHIP_P5(rxq->bp)) {
3191                                 struct rx_tpa_v2_end_cmpl_hi *p5_tpa_end;
3192
3193                                 p5_tpa_end = (void *)rxcmp;
3194                                 agg_cnt = BNXT_TPA_END_AGG_BUFS_TH(p5_tpa_end);
3195                         } else {
3196                                 struct rx_tpa_end_cmpl *tpa_end;
3197
3198                                 tpa_end = (void *)rxcmp;
3199                                 agg_cnt = BNXT_TPA_END_AGG_BUFS(tpa_end);
3200                         }
3201
3202                         raw_cons = raw_cons + CMP_LEN(cmpl_type) + agg_cnt;
3203                         desc++;
3204                         break;
3205
3206                 default:
3207                         raw_cons += CMP_LEN(cmpl_type);
3208                 }
3209         }
3210
3211         return desc;
3212 }
3213
3214 static int
3215 bnxt_rx_descriptor_status_op(void *rx_queue, uint16_t offset)
3216 {
3217         struct bnxt_rx_queue *rxq = rx_queue;
3218         struct bnxt_cp_ring_info *cpr;
3219         struct bnxt_rx_ring_info *rxr;
3220         uint32_t desc, raw_cons, cp_ring_size;
3221         struct bnxt *bp = rxq->bp;
3222         struct rx_pkt_cmpl *rxcmp;
3223         int rc;
3224
3225         rc = is_bnxt_in_error(bp);
3226         if (rc)
3227                 return rc;
3228
3229         if (offset >= rxq->nb_rx_desc)
3230                 return -EINVAL;
3231
3232         rxr = rxq->rx_ring;
3233         cpr = rxq->cp_ring;
3234         cp_ring_size = cpr->cp_ring_struct->ring_size;
3235
3236         /*
3237          * For the vector receive case, the completion at the requested
3238          * offset can be indexed directly.
3239          */
3240 #if defined(RTE_ARCH_X86) || defined(RTE_ARCH_ARM64)
3241         if (bp->flags & BNXT_FLAG_RX_VECTOR_PKT_MODE) {
3242                 struct rx_pkt_cmpl *rxcmp;
3243                 uint32_t cons;
3244
3245                 /* Check status of completion descriptor. */
3246                 raw_cons = cpr->cp_raw_cons +
3247                            offset * CMP_LEN(CMPL_BASE_TYPE_RX_L2);
3248                 cons = RING_CMP(cpr->cp_ring_struct, raw_cons);
3249                 rxcmp = (struct rx_pkt_cmpl *)&cpr->cp_desc_ring[cons];
3250
3251                 if (bnxt_cpr_cmp_valid(rxcmp, raw_cons, cp_ring_size))
3252                         return RTE_ETH_RX_DESC_DONE;
3253
3254                 /* Check whether rx desc has an mbuf attached. */
3255                 cons = RING_CMP(rxr->rx_ring_struct, raw_cons / 2);
3256                 if (cons >= rxq->rxrearm_start &&
3257                     cons < rxq->rxrearm_start + rxq->rxrearm_nb) {
3258                         return RTE_ETH_RX_DESC_UNAVAIL;
3259                 }
3260
3261                 return RTE_ETH_RX_DESC_AVAIL;
3262         }
3263 #endif
3264
3265         /*
3266          * For the non-vector receive case, scan the completion ring to
3267          * locate the completion descriptor for the requested offset.
3268          */
3269         raw_cons = cpr->cp_raw_cons;
3270         desc = 0;
3271         while (1) {
3272                 uint32_t agg_cnt, cons, cmpl_type;
3273
3274                 cons = RING_CMP(cpr->cp_ring_struct, raw_cons);
3275                 rxcmp = (struct rx_pkt_cmpl *)&cpr->cp_desc_ring[cons];
3276
3277                 if (!bnxt_cpr_cmp_valid(rxcmp, raw_cons, cp_ring_size))
3278                         break;
3279
3280                 cmpl_type = CMP_TYPE(rxcmp);
3281
3282                 switch (cmpl_type) {
3283                 case CMPL_BASE_TYPE_RX_L2:
3284                 case CMPL_BASE_TYPE_RX_L2_V2:
3285                         if (desc == offset) {
3286                                 cons = rxcmp->opaque;
3287                                 if (rxr->rx_buf_ring[cons])
3288                                         return RTE_ETH_RX_DESC_DONE;
3289                                 else
3290                                         return RTE_ETH_RX_DESC_UNAVAIL;
3291                         }
3292                         agg_cnt = BNXT_RX_L2_AGG_BUFS(rxcmp);
3293                         raw_cons = raw_cons + CMP_LEN(cmpl_type) + agg_cnt;
3294                         desc++;
3295                         break;
3296
3297                 case CMPL_BASE_TYPE_RX_TPA_END:
3298                         if (desc == offset)
3299                                 return RTE_ETH_RX_DESC_DONE;
3300
3301                         if (BNXT_CHIP_P5(rxq->bp)) {
3302                                 struct rx_tpa_v2_end_cmpl_hi *p5_tpa_end;
3303
3304                                 p5_tpa_end = (void *)rxcmp;
3305                                 agg_cnt = BNXT_TPA_END_AGG_BUFS_TH(p5_tpa_end);
3306                         } else {
3307                                 struct rx_tpa_end_cmpl *tpa_end;
3308
3309                                 tpa_end = (void *)rxcmp;
3310                                 agg_cnt = BNXT_TPA_END_AGG_BUFS(tpa_end);
3311                         }
3312
3313                         raw_cons = raw_cons + CMP_LEN(cmpl_type) + agg_cnt;
3314                         desc++;
3315                         break;
3316
3317                 default:
3318                         raw_cons += CMP_LEN(cmpl_type);
3319                 }
3320         }
3321
3322         return RTE_ETH_RX_DESC_AVAIL;
3323 }
3324
3325 static int
3326 bnxt_tx_descriptor_status_op(void *tx_queue, uint16_t offset)
3327 {
3328         struct bnxt_tx_queue *txq = (struct bnxt_tx_queue *)tx_queue;
3329         struct bnxt_cp_ring_info *cpr = txq->cp_ring;
3330         uint32_t ring_mask, raw_cons, nb_tx_pkts = 0;
3331         struct cmpl_base *cp_desc_ring;
3332         int rc;
3333
3334         rc = is_bnxt_in_error(txq->bp);
3335         if (rc)
3336                 return rc;
3337
3338         if (offset >= txq->nb_tx_desc)
3339                 return -EINVAL;
3340
3341         /* Return "desc done" if descriptor is available for use. */
3342         if (bnxt_tx_bds_in_hw(txq) <= offset)
3343                 return RTE_ETH_TX_DESC_DONE;
3344
3345         raw_cons = cpr->cp_raw_cons;
3346         cp_desc_ring = cpr->cp_desc_ring;
3347         ring_mask = cpr->cp_ring_struct->ring_mask;
3348
3349         /* Check to see if hw has posted a completion for the descriptor. */
3350         while (1) {
3351                 struct tx_cmpl *txcmp;
3352                 uint32_t cons;
3353
3354                 cons = RING_CMPL(ring_mask, raw_cons);
3355                 txcmp = (struct tx_cmpl *)&cp_desc_ring[cons];
3356
3357                 if (!bnxt_cpr_cmp_valid(txcmp, raw_cons, ring_mask + 1))
3358                         break;
3359
3360                 if (CMP_TYPE(txcmp) == TX_CMPL_TYPE_TX_L2)
3361                         nb_tx_pkts += rte_le_to_cpu_32(txcmp->opaque);
3362
3363                 if (nb_tx_pkts > offset)
3364                         return RTE_ETH_TX_DESC_DONE;
3365
3366                 raw_cons = NEXT_RAW_CMP(raw_cons);
3367         }
3368
3369         /* Descriptor is pending transmit, not yet completed by hardware. */
3370         return RTE_ETH_TX_DESC_FULL;
3371 }
3372
3373 int
3374 bnxt_flow_ops_get_op(struct rte_eth_dev *dev,
3375                      const struct rte_flow_ops **ops)
3376 {
3377         struct bnxt *bp = dev->data->dev_private;
3378         int ret = 0;
3379
3380         if (!bp)
3381                 return -EIO;
3382
3383         if (BNXT_ETH_DEV_IS_REPRESENTOR(dev)) {
3384                 struct bnxt_representor *vfr = dev->data->dev_private;
3385                 bp = vfr->parent_dev->data->dev_private;
3386                 /* parent is deleted while children are still valid */
3387                 if (!bp) {
3388                         PMD_DRV_LOG(DEBUG, "BNXT Port:%d VFR Error\n",
3389                                     dev->data->port_id);
3390                         return -EIO;
3391                 }
3392         }
3393
3394         ret = is_bnxt_in_error(bp);
3395         if (ret)
3396                 return ret;
3397
3398         /* PMD supports thread-safe flow operations.  rte_flow API
3399          * functions can avoid mutex for multi-thread safety.
3400          */
3401         dev->data->dev_flags |= RTE_ETH_DEV_FLOW_OPS_THREAD_SAFE;
3402
3403         if (BNXT_TRUFLOW_EN(bp))
3404                 *ops = &bnxt_ulp_rte_flow_ops;
3405         else
3406                 *ops = &bnxt_flow_ops;
3407
3408         return ret;
3409 }
3410
3411 static const uint32_t *
3412 bnxt_dev_supported_ptypes_get_op(struct rte_eth_dev *dev)
3413 {
3414         static const uint32_t ptypes[] = {
3415                 RTE_PTYPE_L2_ETHER_VLAN,
3416                 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN,
3417                 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN,
3418                 RTE_PTYPE_L4_ICMP,
3419                 RTE_PTYPE_L4_TCP,
3420                 RTE_PTYPE_L4_UDP,
3421                 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN,
3422                 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN,
3423                 RTE_PTYPE_INNER_L4_ICMP,
3424                 RTE_PTYPE_INNER_L4_TCP,
3425                 RTE_PTYPE_INNER_L4_UDP,
3426                 RTE_PTYPE_UNKNOWN
3427         };
3428
3429         if (!dev->rx_pkt_burst)
3430                 return NULL;
3431
3432         return ptypes;
3433 }
3434
3435 static int bnxt_map_regs(struct bnxt *bp, uint32_t *reg_arr, int count,
3436                          int reg_win)
3437 {
3438         uint32_t reg_base = *reg_arr & 0xfffff000;
3439         uint32_t win_off;
3440         int i;
3441
3442         for (i = 0; i < count; i++) {
3443                 if ((reg_arr[i] & 0xfffff000) != reg_base)
3444                         return -ERANGE;
3445         }
3446         win_off = BNXT_GRCPF_REG_WINDOW_BASE_OUT + (reg_win - 1) * 4;
3447         rte_write32(reg_base, (uint8_t *)bp->bar0 + win_off);
3448         return 0;
3449 }
3450
3451 static int bnxt_map_ptp_regs(struct bnxt *bp)
3452 {
3453         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3454         uint32_t *reg_arr;
3455         int rc, i;
3456
3457         reg_arr = ptp->rx_regs;
3458         rc = bnxt_map_regs(bp, reg_arr, BNXT_PTP_RX_REGS, 5);
3459         if (rc)
3460                 return rc;
3461
3462         reg_arr = ptp->tx_regs;
3463         rc = bnxt_map_regs(bp, reg_arr, BNXT_PTP_TX_REGS, 6);
3464         if (rc)
3465                 return rc;
3466
3467         for (i = 0; i < BNXT_PTP_RX_REGS; i++)
3468                 ptp->rx_mapped_regs[i] = 0x5000 + (ptp->rx_regs[i] & 0xfff);
3469
3470         for (i = 0; i < BNXT_PTP_TX_REGS; i++)
3471                 ptp->tx_mapped_regs[i] = 0x6000 + (ptp->tx_regs[i] & 0xfff);
3472
3473         return 0;
3474 }
3475
3476 static void bnxt_unmap_ptp_regs(struct bnxt *bp)
3477 {
3478         rte_write32(0, (uint8_t *)bp->bar0 +
3479                          BNXT_GRCPF_REG_WINDOW_BASE_OUT + 16);
3480         rte_write32(0, (uint8_t *)bp->bar0 +
3481                          BNXT_GRCPF_REG_WINDOW_BASE_OUT + 20);
3482 }
3483
3484 static uint64_t bnxt_cc_read(struct bnxt *bp)
3485 {
3486         uint64_t ns;
3487
3488         ns = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3489                               BNXT_GRCPF_REG_SYNC_TIME));
3490         ns |= (uint64_t)(rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3491                                           BNXT_GRCPF_REG_SYNC_TIME + 4))) << 32;
3492         return ns;
3493 }
3494
3495 static int bnxt_get_tx_ts(struct bnxt *bp, uint64_t *ts)
3496 {
3497         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3498         uint32_t fifo;
3499
3500         fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3501                                 ptp->tx_mapped_regs[BNXT_PTP_TX_FIFO]));
3502         if (fifo & BNXT_PTP_TX_FIFO_EMPTY)
3503                 return -EAGAIN;
3504
3505         fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3506                                 ptp->tx_mapped_regs[BNXT_PTP_TX_FIFO]));
3507         *ts = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3508                                 ptp->tx_mapped_regs[BNXT_PTP_TX_TS_L]));
3509         *ts |= (uint64_t)rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3510                                 ptp->tx_mapped_regs[BNXT_PTP_TX_TS_H])) << 32;
3511         rte_read32((uint8_t *)bp->bar0 + ptp->tx_mapped_regs[BNXT_PTP_TX_SEQ]);
3512
3513         return 0;
3514 }
3515
3516 static int bnxt_clr_rx_ts(struct bnxt *bp, uint64_t *last_ts)
3517 {
3518         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3519         struct bnxt_pf_info *pf = bp->pf;
3520         uint16_t port_id;
3521         int i = 0;
3522         uint32_t fifo;
3523
3524         if (!ptp || (bp->flags & BNXT_FLAG_CHIP_P5))
3525                 return -EINVAL;
3526
3527         port_id = pf->port_id;
3528         fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3529                                 ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO]));
3530         while ((fifo & BNXT_PTP_RX_FIFO_PENDING) && (i < BNXT_PTP_RX_PND_CNT)) {
3531                 rte_write32(1 << port_id, (uint8_t *)bp->bar0 +
3532                             ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO_ADV]);
3533                 fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3534                                         ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO]));
3535                 *last_ts = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3536                                         ptp->rx_mapped_regs[BNXT_PTP_RX_TS_L]));
3537                 *last_ts |= (uint64_t)rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3538                                         ptp->rx_mapped_regs[BNXT_PTP_RX_TS_H])) << 32;
3539                 i++;
3540         }
3541
3542         if (i >= BNXT_PTP_RX_PND_CNT)
3543                 return -EBUSY;
3544
3545         return 0;
3546 }
3547
3548 static int bnxt_get_rx_ts(struct bnxt *bp, uint64_t *ts)
3549 {
3550         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3551         struct bnxt_pf_info *pf = bp->pf;
3552         uint16_t port_id;
3553         uint32_t fifo;
3554
3555         fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3556                                 ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO]));
3557         if (!(fifo & BNXT_PTP_RX_FIFO_PENDING))
3558                 return -EAGAIN;
3559
3560         port_id = pf->port_id;
3561         rte_write32(1 << port_id, (uint8_t *)bp->bar0 +
3562                ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO_ADV]);
3563
3564         fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3565                                    ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO]));
3566         if (fifo & BNXT_PTP_RX_FIFO_PENDING)
3567                 return bnxt_clr_rx_ts(bp, ts);
3568
3569         *ts = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3570                                 ptp->rx_mapped_regs[BNXT_PTP_RX_TS_L]));
3571         *ts |= (uint64_t)rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3572                                 ptp->rx_mapped_regs[BNXT_PTP_RX_TS_H])) << 32;
3573
3574         return 0;
3575 }
3576
3577 static int
3578 bnxt_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
3579 {
3580         uint64_t ns;
3581         struct bnxt *bp = dev->data->dev_private;
3582         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3583
3584         if (!ptp)
3585                 return -ENOTSUP;
3586
3587         ns = rte_timespec_to_ns(ts);
3588         /* Set the timecounters to a new value. */
3589         ptp->tc.nsec = ns;
3590         ptp->tx_tstamp_tc.nsec = ns;
3591         ptp->rx_tstamp_tc.nsec = ns;
3592
3593         return 0;
3594 }
3595
3596 static int
3597 bnxt_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
3598 {
3599         struct bnxt *bp = dev->data->dev_private;
3600         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3601         uint64_t ns, systime_cycles = 0;
3602         int rc = 0;
3603
3604         if (!ptp)
3605                 return -ENOTSUP;
3606
3607         if (BNXT_CHIP_P5(bp))
3608                 rc = bnxt_hwrm_port_ts_query(bp, BNXT_PTP_FLAGS_CURRENT_TIME,
3609                                              &systime_cycles);
3610         else
3611                 systime_cycles = bnxt_cc_read(bp);
3612
3613         ns = rte_timecounter_update(&ptp->tc, systime_cycles);
3614         *ts = rte_ns_to_timespec(ns);
3615
3616         return rc;
3617 }
3618 static int
3619 bnxt_timesync_enable(struct rte_eth_dev *dev)
3620 {
3621         struct bnxt *bp = dev->data->dev_private;
3622         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3623         uint32_t shift = 0;
3624         int rc;
3625
3626         if (!ptp)
3627                 return -ENOTSUP;
3628
3629         ptp->rx_filter = 1;
3630         ptp->tx_tstamp_en = 1;
3631         ptp->rxctl = BNXT_PTP_MSG_EVENTS;
3632
3633         rc = bnxt_hwrm_ptp_cfg(bp);
3634         if (rc)
3635                 return rc;
3636
3637         memset(&ptp->tc, 0, sizeof(struct rte_timecounter));
3638         memset(&ptp->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
3639         memset(&ptp->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
3640
3641         ptp->tc.cc_mask = BNXT_CYCLECOUNTER_MASK;
3642         ptp->tc.cc_shift = shift;
3643         ptp->tc.nsec_mask = (1ULL << shift) - 1;
3644
3645         ptp->rx_tstamp_tc.cc_mask = BNXT_CYCLECOUNTER_MASK;
3646         ptp->rx_tstamp_tc.cc_shift = shift;
3647         ptp->rx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
3648
3649         ptp->tx_tstamp_tc.cc_mask = BNXT_CYCLECOUNTER_MASK;
3650         ptp->tx_tstamp_tc.cc_shift = shift;
3651         ptp->tx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
3652
3653         if (!BNXT_CHIP_P5(bp))
3654                 bnxt_map_ptp_regs(bp);
3655         else
3656                 rc = bnxt_ptp_start(bp);
3657
3658         return rc;
3659 }
3660
3661 static int
3662 bnxt_timesync_disable(struct rte_eth_dev *dev)
3663 {
3664         struct bnxt *bp = dev->data->dev_private;
3665         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3666
3667         if (!ptp)
3668                 return -ENOTSUP;
3669
3670         ptp->rx_filter = 0;
3671         ptp->tx_tstamp_en = 0;
3672         ptp->rxctl = 0;
3673
3674         bnxt_hwrm_ptp_cfg(bp);
3675
3676         if (!BNXT_CHIP_P5(bp))
3677                 bnxt_unmap_ptp_regs(bp);
3678         else
3679                 bnxt_ptp_stop(bp);
3680
3681         return 0;
3682 }
3683
3684 static int
3685 bnxt_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
3686                                  struct timespec *timestamp,
3687                                  uint32_t flags __rte_unused)
3688 {
3689         struct bnxt *bp = dev->data->dev_private;
3690         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3691         uint64_t rx_tstamp_cycles = 0;
3692         uint64_t ns;
3693
3694         if (!ptp)
3695                 return -ENOTSUP;
3696
3697         if (BNXT_CHIP_P5(bp))
3698                 rx_tstamp_cycles = ptp->rx_timestamp;
3699         else
3700                 bnxt_get_rx_ts(bp, &rx_tstamp_cycles);
3701
3702         ns = rte_timecounter_update(&ptp->rx_tstamp_tc, rx_tstamp_cycles);
3703         *timestamp = rte_ns_to_timespec(ns);
3704         return  0;
3705 }
3706
3707 static int
3708 bnxt_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
3709                                  struct timespec *timestamp)
3710 {
3711         struct bnxt *bp = dev->data->dev_private;
3712         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3713         uint64_t tx_tstamp_cycles = 0;
3714         uint64_t ns;
3715         int rc = 0;
3716
3717         if (!ptp)
3718                 return -ENOTSUP;
3719
3720         if (BNXT_CHIP_P5(bp))
3721                 rc = bnxt_hwrm_port_ts_query(bp, BNXT_PTP_FLAGS_PATH_TX,
3722                                              &tx_tstamp_cycles);
3723         else
3724                 rc = bnxt_get_tx_ts(bp, &tx_tstamp_cycles);
3725
3726         ns = rte_timecounter_update(&ptp->tx_tstamp_tc, tx_tstamp_cycles);
3727         *timestamp = rte_ns_to_timespec(ns);
3728
3729         return rc;
3730 }
3731
3732 static int
3733 bnxt_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
3734 {
3735         struct bnxt *bp = dev->data->dev_private;
3736         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3737
3738         if (!ptp)
3739                 return -ENOTSUP;
3740
3741         ptp->tc.nsec += delta;
3742         ptp->tx_tstamp_tc.nsec += delta;
3743         ptp->rx_tstamp_tc.nsec += delta;
3744
3745         return 0;
3746 }
3747
3748 static int
3749 bnxt_get_eeprom_length_op(struct rte_eth_dev *dev)
3750 {
3751         struct bnxt *bp = dev->data->dev_private;
3752         int rc;
3753         uint32_t dir_entries;
3754         uint32_t entry_length;
3755
3756         rc = is_bnxt_in_error(bp);
3757         if (rc)
3758                 return rc;
3759
3760         PMD_DRV_LOG(INFO, PCI_PRI_FMT "\n",
3761                     bp->pdev->addr.domain, bp->pdev->addr.bus,
3762                     bp->pdev->addr.devid, bp->pdev->addr.function);
3763
3764         rc = bnxt_hwrm_nvm_get_dir_info(bp, &dir_entries, &entry_length);
3765         if (rc != 0)
3766                 return rc;
3767
3768         return dir_entries * entry_length;
3769 }
3770
3771 static int
3772 bnxt_get_eeprom_op(struct rte_eth_dev *dev,
3773                 struct rte_dev_eeprom_info *in_eeprom)
3774 {
3775         struct bnxt *bp = dev->data->dev_private;
3776         uint32_t index;
3777         uint32_t offset;
3778         int rc;
3779
3780         rc = is_bnxt_in_error(bp);
3781         if (rc)
3782                 return rc;
3783
3784         PMD_DRV_LOG(INFO, PCI_PRI_FMT " in_eeprom->offset = %d len = %d\n",
3785                     bp->pdev->addr.domain, bp->pdev->addr.bus,
3786                     bp->pdev->addr.devid, bp->pdev->addr.function,
3787                     in_eeprom->offset, in_eeprom->length);
3788
3789         if (in_eeprom->offset == 0) /* special offset value to get directory */
3790                 return bnxt_get_nvram_directory(bp, in_eeprom->length,
3791                                                 in_eeprom->data);
3792
3793         index = in_eeprom->offset >> 24;
3794         offset = in_eeprom->offset & 0xffffff;
3795
3796         if (index != 0)
3797                 return bnxt_hwrm_get_nvram_item(bp, index - 1, offset,
3798                                            in_eeprom->length, in_eeprom->data);
3799
3800         return 0;
3801 }
3802
3803 static bool bnxt_dir_type_is_ape_bin_format(uint16_t dir_type)
3804 {
3805         switch (dir_type) {
3806         case BNX_DIR_TYPE_CHIMP_PATCH:
3807         case BNX_DIR_TYPE_BOOTCODE:
3808         case BNX_DIR_TYPE_BOOTCODE_2:
3809         case BNX_DIR_TYPE_APE_FW:
3810         case BNX_DIR_TYPE_APE_PATCH:
3811         case BNX_DIR_TYPE_KONG_FW:
3812         case BNX_DIR_TYPE_KONG_PATCH:
3813         case BNX_DIR_TYPE_BONO_FW:
3814         case BNX_DIR_TYPE_BONO_PATCH:
3815                 /* FALLTHROUGH */
3816                 return true;
3817         }
3818
3819         return false;
3820 }
3821
3822 static bool bnxt_dir_type_is_other_exec_format(uint16_t dir_type)
3823 {
3824         switch (dir_type) {
3825         case BNX_DIR_TYPE_AVS:
3826         case BNX_DIR_TYPE_EXP_ROM_MBA:
3827         case BNX_DIR_TYPE_PCIE:
3828         case BNX_DIR_TYPE_TSCF_UCODE:
3829         case BNX_DIR_TYPE_EXT_PHY:
3830         case BNX_DIR_TYPE_CCM:
3831         case BNX_DIR_TYPE_ISCSI_BOOT:
3832         case BNX_DIR_TYPE_ISCSI_BOOT_IPV6:
3833         case BNX_DIR_TYPE_ISCSI_BOOT_IPV4N6:
3834                 /* FALLTHROUGH */
3835                 return true;
3836         }
3837
3838         return false;
3839 }
3840
3841 static bool bnxt_dir_type_is_executable(uint16_t dir_type)
3842 {
3843         return bnxt_dir_type_is_ape_bin_format(dir_type) ||
3844                 bnxt_dir_type_is_other_exec_format(dir_type);
3845 }
3846
3847 static int
3848 bnxt_set_eeprom_op(struct rte_eth_dev *dev,
3849                 struct rte_dev_eeprom_info *in_eeprom)
3850 {
3851         struct bnxt *bp = dev->data->dev_private;
3852         uint8_t index, dir_op;
3853         uint16_t type, ext, ordinal, attr;
3854         int rc;
3855
3856         rc = is_bnxt_in_error(bp);
3857         if (rc)
3858                 return rc;
3859
3860         PMD_DRV_LOG(INFO, PCI_PRI_FMT " in_eeprom->offset = %d len = %d\n",
3861                     bp->pdev->addr.domain, bp->pdev->addr.bus,
3862                     bp->pdev->addr.devid, bp->pdev->addr.function,
3863                     in_eeprom->offset, in_eeprom->length);
3864
3865         if (!BNXT_PF(bp)) {
3866                 PMD_DRV_LOG(ERR, "NVM write not supported from a VF\n");
3867                 return -EINVAL;
3868         }
3869
3870         type = in_eeprom->magic >> 16;
3871
3872         if (type == 0xffff) { /* special value for directory operations */
3873                 index = in_eeprom->magic & 0xff;
3874                 dir_op = in_eeprom->magic >> 8;
3875                 if (index == 0)
3876                         return -EINVAL;
3877                 switch (dir_op) {
3878                 case 0x0e: /* erase */
3879                         if (in_eeprom->offset != ~in_eeprom->magic)
3880                                 return -EINVAL;
3881                         return bnxt_hwrm_erase_nvram_directory(bp, index - 1);
3882                 default:
3883                         return -EINVAL;
3884                 }
3885         }
3886
3887         /* Create or re-write an NVM item: */
3888         if (bnxt_dir_type_is_executable(type) == true)
3889                 return -EOPNOTSUPP;
3890         ext = in_eeprom->magic & 0xffff;
3891         ordinal = in_eeprom->offset >> 16;
3892         attr = in_eeprom->offset & 0xffff;
3893
3894         return bnxt_hwrm_flash_nvram(bp, type, ordinal, ext, attr,
3895                                      in_eeprom->data, in_eeprom->length);
3896 }
3897
3898 static int bnxt_get_module_info(struct rte_eth_dev *dev,
3899                                 struct rte_eth_dev_module_info *modinfo)
3900 {
3901         uint8_t module_info[SFF_DIAG_SUPPORT_OFFSET + 1];
3902         struct bnxt *bp = dev->data->dev_private;
3903         int rc;
3904
3905         /* No point in going further if phy status indicates
3906          * module is not inserted or if it is powered down or
3907          * if it is of type 10GBase-T
3908          */
3909         if (bp->link_info->module_status >
3910             HWRM_PORT_PHY_QCFG_OUTPUT_MODULE_STATUS_WARNINGMSG) {
3911                 PMD_DRV_LOG(NOTICE, "Port %u : Module is not inserted or is powered down\n",
3912                             dev->data->port_id);
3913                 return -ENOTSUP;
3914         }
3915
3916         /* This feature is not supported in older firmware versions */
3917         if (bp->hwrm_spec_code < 0x10202) {
3918                 PMD_DRV_LOG(NOTICE, "Port %u : Feature is not supported in older firmware\n",
3919                             dev->data->port_id);
3920                 return -ENOTSUP;
3921         }
3922
3923         rc = bnxt_hwrm_read_sfp_module_eeprom_info(bp, I2C_DEV_ADDR_A0, 0, 0,
3924                                                    SFF_DIAG_SUPPORT_OFFSET + 1,
3925                                                    module_info);
3926
3927         if (rc)
3928                 return rc;
3929
3930         switch (module_info[0]) {
3931         case SFF_MODULE_ID_SFP:
3932                 modinfo->type = RTE_ETH_MODULE_SFF_8472;
3933                 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8472_LEN;
3934                 if (module_info[SFF_DIAG_SUPPORT_OFFSET] == 0)
3935                         modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8436_LEN;
3936                 break;
3937         case SFF_MODULE_ID_QSFP:
3938         case SFF_MODULE_ID_QSFP_PLUS:
3939                 modinfo->type = RTE_ETH_MODULE_SFF_8436;
3940                 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8436_LEN;
3941                 break;
3942         case SFF_MODULE_ID_QSFP28:
3943                 modinfo->type = RTE_ETH_MODULE_SFF_8636;
3944                 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8636_MAX_LEN;
3945                 if (module_info[SFF8636_FLATMEM_OFFSET] & SFF8636_FLATMEM_MASK)
3946                         modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8636_LEN;
3947                 break;
3948         default:
3949                 PMD_DRV_LOG(NOTICE, "Port %u : Unsupported module\n", dev->data->port_id);
3950                 return -ENOTSUP;
3951         }
3952
3953         PMD_DRV_LOG(INFO, "Port %u : modinfo->type = %d modinfo->eeprom_len = %d\n",
3954                     dev->data->port_id, modinfo->type, modinfo->eeprom_len);
3955
3956         return 0;
3957 }
3958
3959 static int bnxt_get_module_eeprom(struct rte_eth_dev *dev,
3960                                   struct rte_dev_eeprom_info *info)
3961 {
3962         uint8_t pg_addr[5] = { I2C_DEV_ADDR_A0, I2C_DEV_ADDR_A0 };
3963         uint32_t offset = info->offset, length = info->length;
3964         uint8_t module_info[SFF_DIAG_SUPPORT_OFFSET + 1];
3965         struct bnxt *bp = dev->data->dev_private;
3966         uint8_t *data = info->data;
3967         uint8_t page = offset >> 7;
3968         uint8_t max_pages = 2;
3969         uint8_t opt_pages;
3970         int rc;
3971
3972         rc = bnxt_hwrm_read_sfp_module_eeprom_info(bp, I2C_DEV_ADDR_A0, 0, 0,
3973                                                    SFF_DIAG_SUPPORT_OFFSET + 1,
3974                                                    module_info);
3975         if (rc)
3976                 return rc;
3977
3978         switch (module_info[0]) {
3979         case SFF_MODULE_ID_SFP:
3980                 module_info[SFF_DIAG_SUPPORT_OFFSET] = 0;
3981                 if (module_info[SFF_DIAG_SUPPORT_OFFSET]) {
3982                         pg_addr[2] = I2C_DEV_ADDR_A2;
3983                         pg_addr[3] = I2C_DEV_ADDR_A2;
3984                         max_pages = 4;
3985                 }
3986                 break;
3987         case SFF_MODULE_ID_QSFP28:
3988                 rc = bnxt_hwrm_read_sfp_module_eeprom_info(bp, I2C_DEV_ADDR_A0, 0,
3989                                                            SFF8636_OPT_PAGES_OFFSET,
3990                                                            1, &opt_pages);
3991                 if (rc)
3992                         return rc;
3993
3994                 if (opt_pages & SFF8636_PAGE1_MASK) {
3995                         pg_addr[2] = I2C_DEV_ADDR_A0;
3996                         max_pages = 3;
3997                 }
3998                 if (opt_pages & SFF8636_PAGE2_MASK) {
3999                         pg_addr[3] = I2C_DEV_ADDR_A0;
4000                         max_pages = 4;
4001                 }
4002                 if (~module_info[SFF8636_FLATMEM_OFFSET] & SFF8636_FLATMEM_MASK) {
4003                         pg_addr[4] = I2C_DEV_ADDR_A0;
4004                         max_pages = 5;
4005                 }
4006                 break;
4007         default:
4008                 break;
4009         }
4010
4011         memset(data, 0, length);
4012
4013         offset &= 0xff;
4014         while (length && page < max_pages) {
4015                 uint8_t raw_page = page ? page - 1 : 0;
4016                 uint16_t chunk;
4017
4018                 if (pg_addr[page] == I2C_DEV_ADDR_A2)
4019                         raw_page = 0;
4020                 else if (page)
4021                         offset |= 0x80;
4022                 chunk = RTE_MIN(length, 256 - offset);
4023
4024                 if (pg_addr[page]) {
4025                         rc = bnxt_hwrm_read_sfp_module_eeprom_info(bp, pg_addr[page],
4026                                                                    raw_page, offset,
4027                                                                    chunk, data);
4028                         if (rc)
4029                                 return rc;
4030                 }
4031
4032                 data += chunk;
4033                 length -= chunk;
4034                 offset = 0;
4035                 page += 1 + (chunk > 128);
4036         }
4037
4038         return length ? -EINVAL : 0;
4039 }
4040
4041 /*
4042  * Initialization
4043  */
4044
4045 static const struct eth_dev_ops bnxt_dev_ops = {
4046         .dev_infos_get = bnxt_dev_info_get_op,
4047         .dev_close = bnxt_dev_close_op,
4048         .dev_configure = bnxt_dev_configure_op,
4049         .dev_start = bnxt_dev_start_op,
4050         .dev_stop = bnxt_dev_stop_op,
4051         .dev_set_link_up = bnxt_dev_set_link_up_op,
4052         .dev_set_link_down = bnxt_dev_set_link_down_op,
4053         .stats_get = bnxt_stats_get_op,
4054         .stats_reset = bnxt_stats_reset_op,
4055         .rx_queue_setup = bnxt_rx_queue_setup_op,
4056         .rx_queue_release = bnxt_rx_queue_release_op,
4057         .tx_queue_setup = bnxt_tx_queue_setup_op,
4058         .tx_queue_release = bnxt_tx_queue_release_op,
4059         .rx_queue_intr_enable = bnxt_rx_queue_intr_enable_op,
4060         .rx_queue_intr_disable = bnxt_rx_queue_intr_disable_op,
4061         .reta_update = bnxt_reta_update_op,
4062         .reta_query = bnxt_reta_query_op,
4063         .rss_hash_update = bnxt_rss_hash_update_op,
4064         .rss_hash_conf_get = bnxt_rss_hash_conf_get_op,
4065         .link_update = bnxt_link_update_op,
4066         .promiscuous_enable = bnxt_promiscuous_enable_op,
4067         .promiscuous_disable = bnxt_promiscuous_disable_op,
4068         .allmulticast_enable = bnxt_allmulticast_enable_op,
4069         .allmulticast_disable = bnxt_allmulticast_disable_op,
4070         .mac_addr_add = bnxt_mac_addr_add_op,
4071         .mac_addr_remove = bnxt_mac_addr_remove_op,
4072         .flow_ctrl_get = bnxt_flow_ctrl_get_op,
4073         .flow_ctrl_set = bnxt_flow_ctrl_set_op,
4074         .udp_tunnel_port_add  = bnxt_udp_tunnel_port_add_op,
4075         .udp_tunnel_port_del  = bnxt_udp_tunnel_port_del_op,
4076         .vlan_filter_set = bnxt_vlan_filter_set_op,
4077         .vlan_offload_set = bnxt_vlan_offload_set_op,
4078         .vlan_tpid_set = bnxt_vlan_tpid_set_op,
4079         .vlan_pvid_set = bnxt_vlan_pvid_set_op,
4080         .mtu_set = bnxt_mtu_set_op,
4081         .mac_addr_set = bnxt_set_default_mac_addr_op,
4082         .xstats_get = bnxt_dev_xstats_get_op,
4083         .xstats_get_names = bnxt_dev_xstats_get_names_op,
4084         .xstats_reset = bnxt_dev_xstats_reset_op,
4085         .fw_version_get = bnxt_fw_version_get,
4086         .set_mc_addr_list = bnxt_dev_set_mc_addr_list_op,
4087         .rxq_info_get = bnxt_rxq_info_get_op,
4088         .txq_info_get = bnxt_txq_info_get_op,
4089         .rx_burst_mode_get = bnxt_rx_burst_mode_get,
4090         .tx_burst_mode_get = bnxt_tx_burst_mode_get,
4091         .dev_led_on = bnxt_dev_led_on_op,
4092         .dev_led_off = bnxt_dev_led_off_op,
4093         .rx_queue_start = bnxt_rx_queue_start,
4094         .rx_queue_stop = bnxt_rx_queue_stop,
4095         .tx_queue_start = bnxt_tx_queue_start,
4096         .tx_queue_stop = bnxt_tx_queue_stop,
4097         .flow_ops_get = bnxt_flow_ops_get_op,
4098         .dev_supported_ptypes_get = bnxt_dev_supported_ptypes_get_op,
4099         .get_eeprom_length    = bnxt_get_eeprom_length_op,
4100         .get_eeprom           = bnxt_get_eeprom_op,
4101         .set_eeprom           = bnxt_set_eeprom_op,
4102         .get_module_info = bnxt_get_module_info,
4103         .get_module_eeprom = bnxt_get_module_eeprom,
4104         .timesync_enable      = bnxt_timesync_enable,
4105         .timesync_disable     = bnxt_timesync_disable,
4106         .timesync_read_time   = bnxt_timesync_read_time,
4107         .timesync_write_time   = bnxt_timesync_write_time,
4108         .timesync_adjust_time = bnxt_timesync_adjust_time,
4109         .timesync_read_rx_timestamp = bnxt_timesync_read_rx_timestamp,
4110         .timesync_read_tx_timestamp = bnxt_timesync_read_tx_timestamp,
4111 };
4112
4113 static uint32_t bnxt_map_reset_regs(struct bnxt *bp, uint32_t reg)
4114 {
4115         uint32_t offset;
4116
4117         /* Only pre-map the reset GRC registers using window 3 */
4118         rte_write32(reg & 0xfffff000, (uint8_t *)bp->bar0 +
4119                     BNXT_GRCPF_REG_WINDOW_BASE_OUT + 8);
4120
4121         offset = BNXT_GRCP_WINDOW_3_BASE + (reg & 0xffc);
4122
4123         return offset;
4124 }
4125
4126 int bnxt_map_fw_health_status_regs(struct bnxt *bp)
4127 {
4128         struct bnxt_error_recovery_info *info = bp->recovery_info;
4129         uint32_t reg_base = 0xffffffff;
4130         int i;
4131
4132         /* Only pre-map the monitoring GRC registers using window 2 */
4133         for (i = 0; i < BNXT_FW_STATUS_REG_CNT; i++) {
4134                 uint32_t reg = info->status_regs[i];
4135
4136                 if (BNXT_FW_STATUS_REG_TYPE(reg) != BNXT_FW_STATUS_REG_TYPE_GRC)
4137                         continue;
4138
4139                 if (reg_base == 0xffffffff)
4140                         reg_base = reg & 0xfffff000;
4141                 if ((reg & 0xfffff000) != reg_base)
4142                         return -ERANGE;
4143
4144                 /* Use mask 0xffc as the Lower 2 bits indicates
4145                  * address space location
4146                  */
4147                 info->mapped_status_regs[i] = BNXT_GRCP_WINDOW_2_BASE +
4148                                                 (reg & 0xffc);
4149         }
4150
4151         if (reg_base == 0xffffffff)
4152                 return 0;
4153
4154         rte_write32(reg_base, (uint8_t *)bp->bar0 +
4155                     BNXT_GRCPF_REG_WINDOW_BASE_OUT + 4);
4156
4157         return 0;
4158 }
4159
4160 static void bnxt_write_fw_reset_reg(struct bnxt *bp, uint32_t index)
4161 {
4162         struct bnxt_error_recovery_info *info = bp->recovery_info;
4163         uint32_t delay = info->delay_after_reset[index];
4164         uint32_t val = info->reset_reg_val[index];
4165         uint32_t reg = info->reset_reg[index];
4166         uint32_t type, offset;
4167         int ret;
4168
4169         type = BNXT_FW_STATUS_REG_TYPE(reg);
4170         offset = BNXT_FW_STATUS_REG_OFF(reg);
4171
4172         switch (type) {
4173         case BNXT_FW_STATUS_REG_TYPE_CFG:
4174                 ret = rte_pci_write_config(bp->pdev, &val, sizeof(val), offset);
4175                 if (ret < 0) {
4176                         PMD_DRV_LOG(ERR, "Failed to write %#x at PCI offset %#x",
4177                                     val, offset);
4178                         return;
4179                 }
4180                 break;
4181         case BNXT_FW_STATUS_REG_TYPE_GRC:
4182                 offset = bnxt_map_reset_regs(bp, offset);
4183                 rte_write32(val, (uint8_t *)bp->bar0 + offset);
4184                 break;
4185         case BNXT_FW_STATUS_REG_TYPE_BAR0:
4186                 rte_write32(val, (uint8_t *)bp->bar0 + offset);
4187                 break;
4188         }
4189         /* wait on a specific interval of time until core reset is complete */
4190         if (delay)
4191                 rte_delay_ms(delay);
4192 }
4193
4194 static void bnxt_dev_cleanup(struct bnxt *bp)
4195 {
4196         bp->eth_dev->data->dev_link.link_status = 0;
4197         bp->link_info->link_up = 0;
4198         if (bp->eth_dev->data->dev_started)
4199                 bnxt_dev_stop(bp->eth_dev);
4200
4201         bnxt_uninit_resources(bp, true);
4202 }
4203
4204 static int
4205 bnxt_check_fw_reset_done(struct bnxt *bp)
4206 {
4207         int timeout = bp->fw_reset_max_msecs;
4208         uint16_t val = 0;
4209         int rc;
4210
4211         do {
4212                 rc = rte_pci_read_config(bp->pdev, &val, sizeof(val), PCI_SUBSYSTEM_ID_OFFSET);
4213                 if (rc < 0) {
4214                         PMD_DRV_LOG(ERR, "Failed to read PCI offset 0x%x", PCI_SUBSYSTEM_ID_OFFSET);
4215                         return rc;
4216                 }
4217                 if (val != 0xffff)
4218                         break;
4219                 rte_delay_ms(1);
4220         } while (timeout--);
4221
4222         if (val == 0xffff) {
4223                 PMD_DRV_LOG(ERR, "Firmware reset aborted, PCI config space invalid\n");
4224                 return -1;
4225         }
4226
4227         return 0;
4228 }
4229
4230 static int bnxt_restore_vlan_filters(struct bnxt *bp)
4231 {
4232         struct rte_eth_dev *dev = bp->eth_dev;
4233         struct rte_vlan_filter_conf *vfc;
4234         int vidx, vbit, rc;
4235         uint16_t vlan_id;
4236
4237         for (vlan_id = 1; vlan_id <= RTE_ETHER_MAX_VLAN_ID; vlan_id++) {
4238                 vfc = &dev->data->vlan_filter_conf;
4239                 vidx = vlan_id / 64;
4240                 vbit = vlan_id % 64;
4241
4242                 /* Each bit corresponds to a VLAN id */
4243                 if (vfc->ids[vidx] & (UINT64_C(1) << vbit)) {
4244                         rc = bnxt_add_vlan_filter(bp, vlan_id);
4245                         if (rc)
4246                                 return rc;
4247                 }
4248         }
4249
4250         return 0;
4251 }
4252
4253 static int bnxt_restore_mac_filters(struct bnxt *bp)
4254 {
4255         struct rte_eth_dev *dev = bp->eth_dev;
4256         struct rte_eth_dev_info dev_info;
4257         struct rte_ether_addr *addr;
4258         uint64_t pool_mask;
4259         uint32_t pool = 0;
4260         uint32_t i;
4261         int rc;
4262
4263         if (BNXT_VF(bp) && !BNXT_VF_IS_TRUSTED(bp))
4264                 return 0;
4265
4266         rc = bnxt_dev_info_get_op(dev, &dev_info);
4267         if (rc)
4268                 return rc;
4269
4270         /* replay MAC address configuration */
4271         for (i = 1; i < dev_info.max_mac_addrs; i++) {
4272                 addr = &dev->data->mac_addrs[i];
4273
4274                 /* skip zero address */
4275                 if (rte_is_zero_ether_addr(addr))
4276                         continue;
4277
4278                 pool = 0;
4279                 pool_mask = dev->data->mac_pool_sel[i];
4280
4281                 do {
4282                         if (pool_mask & 1ULL) {
4283                                 rc = bnxt_mac_addr_add_op(dev, addr, i, pool);
4284                                 if (rc)
4285                                         return rc;
4286                         }
4287                         pool_mask >>= 1;
4288                         pool++;
4289                 } while (pool_mask);
4290         }
4291
4292         return 0;
4293 }
4294
4295 static int bnxt_restore_filters(struct bnxt *bp)
4296 {
4297         struct rte_eth_dev *dev = bp->eth_dev;
4298         int ret = 0;
4299
4300         if (dev->data->all_multicast) {
4301                 ret = bnxt_allmulticast_enable_op(dev);
4302                 if (ret)
4303                         return ret;
4304         }
4305         if (dev->data->promiscuous) {
4306                 ret = bnxt_promiscuous_enable_op(dev);
4307                 if (ret)
4308                         return ret;
4309         }
4310
4311         ret = bnxt_restore_mac_filters(bp);
4312         if (ret)
4313                 return ret;
4314
4315         ret = bnxt_restore_vlan_filters(bp);
4316         /* TODO restore other filters as well */
4317         return ret;
4318 }
4319
4320 static int bnxt_check_fw_ready(struct bnxt *bp)
4321 {
4322         int timeout = bp->fw_reset_max_msecs;
4323         int rc = 0;
4324
4325         do {
4326                 rc = bnxt_hwrm_poll_ver_get(bp);
4327                 if (rc == 0)
4328                         break;
4329                 rte_delay_ms(BNXT_FW_READY_WAIT_INTERVAL);
4330                 timeout -= BNXT_FW_READY_WAIT_INTERVAL;
4331         } while (rc && timeout > 0);
4332
4333         if (rc)
4334                 PMD_DRV_LOG(ERR, "FW is not Ready after reset\n");
4335
4336         return rc;
4337 }
4338
4339 static void bnxt_dev_recover(void *arg)
4340 {
4341         struct bnxt *bp = arg;
4342         int rc = 0;
4343
4344         pthread_mutex_lock(&bp->err_recovery_lock);
4345
4346         if (!bp->fw_reset_min_msecs) {
4347                 rc = bnxt_check_fw_reset_done(bp);
4348                 if (rc)
4349                         goto err;
4350         }
4351
4352         /* Clear Error flag so that device re-init should happen */
4353         bp->flags &= ~BNXT_FLAG_FATAL_ERROR;
4354
4355         rc = bnxt_check_fw_ready(bp);
4356         if (rc)
4357                 goto err;
4358
4359         rc = bnxt_init_resources(bp, true);
4360         if (rc) {
4361                 PMD_DRV_LOG(ERR,
4362                             "Failed to initialize resources after reset\n");
4363                 goto err;
4364         }
4365         /* clear reset flag as the device is initialized now */
4366         bp->flags &= ~BNXT_FLAG_FW_RESET;
4367
4368         rc = bnxt_dev_start_op(bp->eth_dev);
4369         if (rc) {
4370                 PMD_DRV_LOG(ERR, "Failed to start port after reset\n");
4371                 goto err_start;
4372         }
4373
4374         rc = bnxt_restore_filters(bp);
4375         if (rc)
4376                 goto err_start;
4377
4378         PMD_DRV_LOG(INFO, "Recovered from FW reset\n");
4379         pthread_mutex_unlock(&bp->err_recovery_lock);
4380
4381         return;
4382 err_start:
4383         bnxt_dev_stop(bp->eth_dev);
4384 err:
4385         bp->flags |= BNXT_FLAG_FATAL_ERROR;
4386         bnxt_uninit_resources(bp, false);
4387         if (bp->eth_dev->data->dev_conf.intr_conf.rmv)
4388                 rte_eth_dev_callback_process(bp->eth_dev,
4389                                              RTE_ETH_EVENT_INTR_RMV,
4390                                              NULL);
4391         pthread_mutex_unlock(&bp->err_recovery_lock);
4392         PMD_DRV_LOG(ERR, "Failed to recover from FW reset\n");
4393 }
4394
4395 void bnxt_dev_reset_and_resume(void *arg)
4396 {
4397         struct bnxt *bp = arg;
4398         uint32_t us = US_PER_MS * bp->fw_reset_min_msecs;
4399         uint16_t val = 0;
4400         int rc;
4401
4402         bnxt_dev_cleanup(bp);
4403
4404         bnxt_wait_for_device_shutdown(bp);
4405
4406         /* During some fatal firmware error conditions, the PCI config space
4407          * register 0x2e which normally contains the subsystem ID will become
4408          * 0xffff. This register will revert back to the normal value after
4409          * the chip has completed core reset. If we detect this condition,
4410          * we can poll this config register immediately for the value to revert.
4411          */
4412         if (bp->flags & BNXT_FLAG_FATAL_ERROR) {
4413                 rc = rte_pci_read_config(bp->pdev, &val, sizeof(val), PCI_SUBSYSTEM_ID_OFFSET);
4414                 if (rc < 0) {
4415                         PMD_DRV_LOG(ERR, "Failed to read PCI offset 0x%x", PCI_SUBSYSTEM_ID_OFFSET);
4416                         return;
4417                 }
4418                 if (val == 0xffff) {
4419                         bp->fw_reset_min_msecs = 0;
4420                         us = 1;
4421                 }
4422         }
4423
4424         rc = rte_eal_alarm_set(us, bnxt_dev_recover, (void *)bp);
4425         if (rc)
4426                 PMD_DRV_LOG(ERR, "Error setting recovery alarm");
4427 }
4428
4429 uint32_t bnxt_read_fw_status_reg(struct bnxt *bp, uint32_t index)
4430 {
4431         struct bnxt_error_recovery_info *info = bp->recovery_info;
4432         uint32_t reg = info->status_regs[index];
4433         uint32_t type, offset, val = 0;
4434         int ret = 0;
4435
4436         type = BNXT_FW_STATUS_REG_TYPE(reg);
4437         offset = BNXT_FW_STATUS_REG_OFF(reg);
4438
4439         switch (type) {
4440         case BNXT_FW_STATUS_REG_TYPE_CFG:
4441                 ret = rte_pci_read_config(bp->pdev, &val, sizeof(val), offset);
4442                 if (ret < 0)
4443                         PMD_DRV_LOG(ERR, "Failed to read PCI offset %#x",
4444                                     offset);
4445                 break;
4446         case BNXT_FW_STATUS_REG_TYPE_GRC:
4447                 offset = info->mapped_status_regs[index];
4448                 /* FALLTHROUGH */
4449         case BNXT_FW_STATUS_REG_TYPE_BAR0:
4450                 val = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
4451                                        offset));
4452                 break;
4453         }
4454
4455         return val;
4456 }
4457
4458 static int bnxt_fw_reset_all(struct bnxt *bp)
4459 {
4460         struct bnxt_error_recovery_info *info = bp->recovery_info;
4461         uint32_t i;
4462         int rc = 0;
4463
4464         if (info->flags & BNXT_FLAG_ERROR_RECOVERY_HOST) {
4465                 /* Reset through primary function driver */
4466                 for (i = 0; i < info->reg_array_cnt; i++)
4467                         bnxt_write_fw_reset_reg(bp, i);
4468                 /* Wait for time specified by FW after triggering reset */
4469                 rte_delay_ms(info->primary_func_wait_period_after_reset);
4470         } else if (info->flags & BNXT_FLAG_ERROR_RECOVERY_CO_CPU) {
4471                 /* Reset with the help of Kong processor */
4472                 rc = bnxt_hwrm_fw_reset(bp);
4473                 if (rc)
4474                         PMD_DRV_LOG(ERR, "Failed to reset FW\n");
4475         }
4476
4477         return rc;
4478 }
4479
4480 static void bnxt_fw_reset_cb(void *arg)
4481 {
4482         struct bnxt *bp = arg;
4483         struct bnxt_error_recovery_info *info = bp->recovery_info;
4484         int rc = 0;
4485
4486         /* Only Primary function can do FW reset */
4487         if (bnxt_is_primary_func(bp) &&
4488             bnxt_is_recovery_enabled(bp)) {
4489                 rc = bnxt_fw_reset_all(bp);
4490                 if (rc) {
4491                         PMD_DRV_LOG(ERR, "Adapter recovery failed\n");
4492                         return;
4493                 }
4494         }
4495
4496         /* if recovery method is ERROR_RECOVERY_CO_CPU, KONG will send
4497          * EXCEPTION_FATAL_ASYNC event to all the functions
4498          * (including MASTER FUNC). After receiving this Async, all the active
4499          * drivers should treat this case as FW initiated recovery
4500          */
4501         if (info->flags & BNXT_FLAG_ERROR_RECOVERY_HOST) {
4502                 bp->fw_reset_min_msecs = BNXT_MIN_FW_READY_TIMEOUT;
4503                 bp->fw_reset_max_msecs = BNXT_MAX_FW_RESET_TIMEOUT;
4504
4505                 /* To recover from error */
4506                 rte_eal_alarm_set(US_PER_MS, bnxt_dev_reset_and_resume,
4507                                   (void *)bp);
4508         }
4509 }
4510
4511 /* Driver should poll FW heartbeat, reset_counter with the frequency
4512  * advertised by FW in HWRM_ERROR_RECOVERY_QCFG.
4513  * When the driver detects heartbeat stop or change in reset_counter,
4514  * it has to trigger a reset to recover from the error condition.
4515  * A “primary function” is the function who will have the privilege to
4516  * initiate the chimp reset. The primary function will be elected by the
4517  * firmware and will be notified through async message.
4518  */
4519 static void bnxt_check_fw_health(void *arg)
4520 {
4521         struct bnxt *bp = arg;
4522         struct bnxt_error_recovery_info *info = bp->recovery_info;
4523         uint32_t val = 0, wait_msec;
4524
4525         if (!info || !bnxt_is_recovery_enabled(bp) ||
4526             is_bnxt_in_error(bp))
4527                 return;
4528
4529         val = bnxt_read_fw_status_reg(bp, BNXT_FW_HEARTBEAT_CNT_REG);
4530         if (val == info->last_heart_beat)
4531                 goto reset;
4532
4533         info->last_heart_beat = val;
4534
4535         val = bnxt_read_fw_status_reg(bp, BNXT_FW_RECOVERY_CNT_REG);
4536         if (val != info->last_reset_counter)
4537                 goto reset;
4538
4539         info->last_reset_counter = val;
4540
4541         rte_eal_alarm_set(US_PER_MS * info->driver_polling_freq,
4542                           bnxt_check_fw_health, (void *)bp);
4543
4544         return;
4545 reset:
4546         /* Stop DMA to/from device */
4547         bp->flags |= BNXT_FLAG_FATAL_ERROR;
4548         bp->flags |= BNXT_FLAG_FW_RESET;
4549
4550         bnxt_stop_rxtx(bp);
4551
4552         PMD_DRV_LOG(ERR, "Detected FW dead condition\n");
4553
4554         if (bnxt_is_primary_func(bp))
4555                 wait_msec = info->primary_func_wait_period;
4556         else
4557                 wait_msec = info->normal_func_wait_period;
4558
4559         rte_eal_alarm_set(US_PER_MS * wait_msec,
4560                           bnxt_fw_reset_cb, (void *)bp);
4561 }
4562
4563 void bnxt_schedule_fw_health_check(struct bnxt *bp)
4564 {
4565         uint32_t polling_freq;
4566
4567         pthread_mutex_lock(&bp->health_check_lock);
4568
4569         if (!bnxt_is_recovery_enabled(bp))
4570                 goto done;
4571
4572         if (bp->flags & BNXT_FLAG_FW_HEALTH_CHECK_SCHEDULED)
4573                 goto done;
4574
4575         polling_freq = bp->recovery_info->driver_polling_freq;
4576
4577         rte_eal_alarm_set(US_PER_MS * polling_freq,
4578                           bnxt_check_fw_health, (void *)bp);
4579         bp->flags |= BNXT_FLAG_FW_HEALTH_CHECK_SCHEDULED;
4580
4581 done:
4582         pthread_mutex_unlock(&bp->health_check_lock);
4583 }
4584
4585 static void bnxt_cancel_fw_health_check(struct bnxt *bp)
4586 {
4587         rte_eal_alarm_cancel(bnxt_check_fw_health, (void *)bp);
4588         bp->flags &= ~BNXT_FLAG_FW_HEALTH_CHECK_SCHEDULED;
4589 }
4590
4591 static bool bnxt_vf_pciid(uint16_t device_id)
4592 {
4593         switch (device_id) {
4594         case BROADCOM_DEV_ID_57304_VF:
4595         case BROADCOM_DEV_ID_57406_VF:
4596         case BROADCOM_DEV_ID_5731X_VF:
4597         case BROADCOM_DEV_ID_5741X_VF:
4598         case BROADCOM_DEV_ID_57414_VF:
4599         case BROADCOM_DEV_ID_STRATUS_NIC_VF1:
4600         case BROADCOM_DEV_ID_STRATUS_NIC_VF2:
4601         case BROADCOM_DEV_ID_58802_VF:
4602         case BROADCOM_DEV_ID_57500_VF1:
4603         case BROADCOM_DEV_ID_57500_VF2:
4604         case BROADCOM_DEV_ID_58818_VF:
4605                 /* FALLTHROUGH */
4606                 return true;
4607         default:
4608                 return false;
4609         }
4610 }
4611
4612 /* Phase 5 device */
4613 static bool bnxt_p5_device(uint16_t device_id)
4614 {
4615         switch (device_id) {
4616         case BROADCOM_DEV_ID_57508:
4617         case BROADCOM_DEV_ID_57504:
4618         case BROADCOM_DEV_ID_57502:
4619         case BROADCOM_DEV_ID_57508_MF1:
4620         case BROADCOM_DEV_ID_57504_MF1:
4621         case BROADCOM_DEV_ID_57502_MF1:
4622         case BROADCOM_DEV_ID_57508_MF2:
4623         case BROADCOM_DEV_ID_57504_MF2:
4624         case BROADCOM_DEV_ID_57502_MF2:
4625         case BROADCOM_DEV_ID_57500_VF1:
4626         case BROADCOM_DEV_ID_57500_VF2:
4627         case BROADCOM_DEV_ID_58812:
4628         case BROADCOM_DEV_ID_58814:
4629         case BROADCOM_DEV_ID_58818:
4630         case BROADCOM_DEV_ID_58818_VF:
4631                 /* FALLTHROUGH */
4632                 return true;
4633         default:
4634                 return false;
4635         }
4636 }
4637
4638 bool bnxt_stratus_device(struct bnxt *bp)
4639 {
4640         uint16_t device_id = bp->pdev->id.device_id;
4641
4642         switch (device_id) {
4643         case BROADCOM_DEV_ID_STRATUS_NIC:
4644         case BROADCOM_DEV_ID_STRATUS_NIC_VF1:
4645         case BROADCOM_DEV_ID_STRATUS_NIC_VF2:
4646                 /* FALLTHROUGH */
4647                 return true;
4648         default:
4649                 return false;
4650         }
4651 }
4652
4653 static int bnxt_map_pci_bars(struct rte_eth_dev *eth_dev)
4654 {
4655         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
4656         struct bnxt *bp = eth_dev->data->dev_private;
4657
4658         /* enable device (incl. PCI PM wakeup), and bus-mastering */
4659         bp->bar0 = (void *)pci_dev->mem_resource[0].addr;
4660         bp->doorbell_base = (void *)pci_dev->mem_resource[2].addr;
4661         if (!bp->bar0 || !bp->doorbell_base) {
4662                 PMD_DRV_LOG(ERR, "Unable to access Hardware\n");
4663                 return -ENODEV;
4664         }
4665
4666         bp->eth_dev = eth_dev;
4667         bp->pdev = pci_dev;
4668
4669         return 0;
4670 }
4671
4672 static int bnxt_alloc_ctx_mem_blk(struct bnxt *bp,
4673                                   struct bnxt_ctx_pg_info *ctx_pg,
4674                                   uint32_t mem_size,
4675                                   const char *suffix,
4676                                   uint16_t idx)
4677 {
4678         struct bnxt_ring_mem_info *rmem = &ctx_pg->ring_mem;
4679         const struct rte_memzone *mz = NULL;
4680         char mz_name[RTE_MEMZONE_NAMESIZE];
4681         rte_iova_t mz_phys_addr;
4682         uint64_t valid_bits = 0;
4683         uint32_t sz;
4684         int i;
4685
4686         if (!mem_size)
4687                 return 0;
4688
4689         rmem->nr_pages = RTE_ALIGN_MUL_CEIL(mem_size, BNXT_PAGE_SIZE) /
4690                          BNXT_PAGE_SIZE;
4691         rmem->page_size = BNXT_PAGE_SIZE;
4692         rmem->pg_arr = ctx_pg->ctx_pg_arr;
4693         rmem->dma_arr = ctx_pg->ctx_dma_arr;
4694         rmem->flags = BNXT_RMEM_VALID_PTE_FLAG;
4695
4696         valid_bits = PTU_PTE_VALID;
4697
4698         if (rmem->nr_pages > 1) {
4699                 snprintf(mz_name, RTE_MEMZONE_NAMESIZE,
4700                          "bnxt_ctx_pg_tbl%s_%x_%d",
4701                          suffix, idx, bp->eth_dev->data->port_id);
4702                 mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0;
4703                 mz = rte_memzone_lookup(mz_name);
4704                 if (!mz) {
4705                         mz = rte_memzone_reserve_aligned(mz_name,
4706                                                 rmem->nr_pages * 8,
4707                                                 bp->eth_dev->device->numa_node,
4708                                                 RTE_MEMZONE_2MB |
4709                                                 RTE_MEMZONE_SIZE_HINT_ONLY |
4710                                                 RTE_MEMZONE_IOVA_CONTIG,
4711                                                 BNXT_PAGE_SIZE);
4712                         if (mz == NULL)
4713                                 return -ENOMEM;
4714                 }
4715
4716                 memset(mz->addr, 0, mz->len);
4717                 mz_phys_addr = mz->iova;
4718
4719                 rmem->pg_tbl = mz->addr;
4720                 rmem->pg_tbl_map = mz_phys_addr;
4721                 rmem->pg_tbl_mz = mz;
4722         }
4723
4724         snprintf(mz_name, RTE_MEMZONE_NAMESIZE, "bnxt_ctx_%s_%x_%d",
4725                  suffix, idx, bp->eth_dev->data->port_id);
4726         mz = rte_memzone_lookup(mz_name);
4727         if (!mz) {
4728                 mz = rte_memzone_reserve_aligned(mz_name,
4729                                                  mem_size,
4730                                                  bp->eth_dev->device->numa_node,
4731                                                  RTE_MEMZONE_1GB |
4732                                                  RTE_MEMZONE_SIZE_HINT_ONLY |
4733                                                  RTE_MEMZONE_IOVA_CONTIG,
4734                                                  BNXT_PAGE_SIZE);
4735                 if (mz == NULL)
4736                         return -ENOMEM;
4737         }
4738
4739         memset(mz->addr, 0, mz->len);
4740         mz_phys_addr = mz->iova;
4741
4742         for (sz = 0, i = 0; sz < mem_size; sz += BNXT_PAGE_SIZE, i++) {
4743                 rmem->pg_arr[i] = ((char *)mz->addr) + sz;
4744                 rmem->dma_arr[i] = mz_phys_addr + sz;
4745
4746                 if (rmem->nr_pages > 1) {
4747                         if (i == rmem->nr_pages - 2 &&
4748                             (rmem->flags & BNXT_RMEM_RING_PTE_FLAG))
4749                                 valid_bits |= PTU_PTE_NEXT_TO_LAST;
4750                         else if (i == rmem->nr_pages - 1 &&
4751                                  (rmem->flags & BNXT_RMEM_RING_PTE_FLAG))
4752                                 valid_bits |= PTU_PTE_LAST;
4753
4754                         rmem->pg_tbl[i] = rte_cpu_to_le_64(rmem->dma_arr[i] |
4755                                                            valid_bits);
4756                 }
4757         }
4758
4759         rmem->mz = mz;
4760         if (rmem->vmem_size)
4761                 rmem->vmem = (void **)mz->addr;
4762         rmem->dma_arr[0] = mz_phys_addr;
4763         return 0;
4764 }
4765
4766 static void bnxt_free_ctx_mem(struct bnxt *bp)
4767 {
4768         int i;
4769
4770         if (!bp->ctx || !(bp->ctx->flags & BNXT_CTX_FLAG_INITED))
4771                 return;
4772
4773         bp->ctx->flags &= ~BNXT_CTX_FLAG_INITED;
4774         rte_memzone_free(bp->ctx->qp_mem.ring_mem.mz);
4775         rte_memzone_free(bp->ctx->srq_mem.ring_mem.mz);
4776         rte_memzone_free(bp->ctx->cq_mem.ring_mem.mz);
4777         rte_memzone_free(bp->ctx->vnic_mem.ring_mem.mz);
4778         rte_memzone_free(bp->ctx->stat_mem.ring_mem.mz);
4779         rte_memzone_free(bp->ctx->qp_mem.ring_mem.pg_tbl_mz);
4780         rte_memzone_free(bp->ctx->srq_mem.ring_mem.pg_tbl_mz);
4781         rte_memzone_free(bp->ctx->cq_mem.ring_mem.pg_tbl_mz);
4782         rte_memzone_free(bp->ctx->vnic_mem.ring_mem.pg_tbl_mz);
4783         rte_memzone_free(bp->ctx->stat_mem.ring_mem.pg_tbl_mz);
4784
4785         for (i = 0; i < bp->ctx->tqm_fp_rings_count + 1; i++) {
4786                 if (bp->ctx->tqm_mem[i])
4787                         rte_memzone_free(bp->ctx->tqm_mem[i]->ring_mem.mz);
4788         }
4789
4790         rte_free(bp->ctx);
4791         bp->ctx = NULL;
4792 }
4793
4794 #define bnxt_roundup(x, y)   ((((x) + ((y) - 1)) / (y)) * (y))
4795
4796 #define min_t(type, x, y) ({                    \
4797         type __min1 = (x);                      \
4798         type __min2 = (y);                      \
4799         __min1 < __min2 ? __min1 : __min2; })
4800
4801 #define max_t(type, x, y) ({                    \
4802         type __max1 = (x);                      \
4803         type __max2 = (y);                      \
4804         __max1 > __max2 ? __max1 : __max2; })
4805
4806 #define clamp_t(type, _x, min, max)     min_t(type, max_t(type, _x, min), max)
4807
4808 int bnxt_alloc_ctx_mem(struct bnxt *bp)
4809 {
4810         struct bnxt_ctx_pg_info *ctx_pg;
4811         struct bnxt_ctx_mem_info *ctx;
4812         uint32_t mem_size, ena, entries;
4813         uint32_t entries_sp, min;
4814         int i, rc;
4815
4816         rc = bnxt_hwrm_func_backing_store_qcaps(bp);
4817         if (rc) {
4818                 PMD_DRV_LOG(ERR, "Query context mem capability failed\n");
4819                 return rc;
4820         }
4821         ctx = bp->ctx;
4822         if (!ctx || (ctx->flags & BNXT_CTX_FLAG_INITED))
4823                 return 0;
4824
4825         ctx_pg = &ctx->qp_mem;
4826         ctx_pg->entries = ctx->qp_min_qp1_entries + ctx->qp_max_l2_entries;
4827         if (ctx->qp_entry_size) {
4828                 mem_size = ctx->qp_entry_size * ctx_pg->entries;
4829                 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "qp_mem", 0);
4830                 if (rc)
4831                         return rc;
4832         }
4833
4834         ctx_pg = &ctx->srq_mem;
4835         ctx_pg->entries = ctx->srq_max_l2_entries;
4836         if (ctx->srq_entry_size) {
4837                 mem_size = ctx->srq_entry_size * ctx_pg->entries;
4838                 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "srq_mem", 0);
4839                 if (rc)
4840                         return rc;
4841         }
4842
4843         ctx_pg = &ctx->cq_mem;
4844         ctx_pg->entries = ctx->cq_max_l2_entries;
4845         if (ctx->cq_entry_size) {
4846                 mem_size = ctx->cq_entry_size * ctx_pg->entries;
4847                 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "cq_mem", 0);
4848                 if (rc)
4849                         return rc;
4850         }
4851
4852         ctx_pg = &ctx->vnic_mem;
4853         ctx_pg->entries = ctx->vnic_max_vnic_entries +
4854                 ctx->vnic_max_ring_table_entries;
4855         if (ctx->vnic_entry_size) {
4856                 mem_size = ctx->vnic_entry_size * ctx_pg->entries;
4857                 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "vnic_mem", 0);
4858                 if (rc)
4859                         return rc;
4860         }
4861
4862         ctx_pg = &ctx->stat_mem;
4863         ctx_pg->entries = ctx->stat_max_entries;
4864         if (ctx->stat_entry_size) {
4865                 mem_size = ctx->stat_entry_size * ctx_pg->entries;
4866                 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "stat_mem", 0);
4867                 if (rc)
4868                         return rc;
4869         }
4870
4871         min = ctx->tqm_min_entries_per_ring;
4872
4873         entries_sp = ctx->qp_max_l2_entries +
4874                      ctx->vnic_max_vnic_entries +
4875                      2 * ctx->qp_min_qp1_entries + min;
4876         entries_sp = bnxt_roundup(entries_sp, ctx->tqm_entries_multiple);
4877
4878         entries = ctx->qp_max_l2_entries + ctx->qp_min_qp1_entries;
4879         entries = bnxt_roundup(entries, ctx->tqm_entries_multiple);
4880         entries = clamp_t(uint32_t, entries, min,
4881                           ctx->tqm_max_entries_per_ring);
4882         for (i = 0, ena = 0; i < ctx->tqm_fp_rings_count + 1; i++) {
4883                 /* i=0 is for TQM_SP. i=1 to i=8 applies to RING0 to RING7.
4884                  * i > 8 is other ext rings.
4885                  */
4886                 ctx_pg = ctx->tqm_mem[i];
4887                 ctx_pg->entries = i ? entries : entries_sp;
4888                 if (ctx->tqm_entry_size) {
4889                         mem_size = ctx->tqm_entry_size * ctx_pg->entries;
4890                         rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size,
4891                                                     "tqm_mem", i);
4892                         if (rc)
4893                                 return rc;
4894                 }
4895                 if (i < BNXT_MAX_TQM_LEGACY_RINGS)
4896                         ena |= HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_SP << i;
4897                 else
4898                         ena |= HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_RING8;
4899         }
4900
4901         ena |= FUNC_BACKING_STORE_CFG_INPUT_DFLT_ENABLES;
4902         rc = bnxt_hwrm_func_backing_store_cfg(bp, ena);
4903         if (rc)
4904                 PMD_DRV_LOG(ERR,
4905                             "Failed to configure context mem: rc = %d\n", rc);
4906         else
4907                 ctx->flags |= BNXT_CTX_FLAG_INITED;
4908
4909         return rc;
4910 }
4911
4912 static int bnxt_alloc_stats_mem(struct bnxt *bp)
4913 {
4914         struct rte_pci_device *pci_dev = bp->pdev;
4915         char mz_name[RTE_MEMZONE_NAMESIZE];
4916         const struct rte_memzone *mz = NULL;
4917         uint32_t total_alloc_len;
4918         rte_iova_t mz_phys_addr;
4919
4920         if (pci_dev->id.device_id == BROADCOM_DEV_ID_NS2)
4921                 return 0;
4922
4923         snprintf(mz_name, RTE_MEMZONE_NAMESIZE,
4924                  "bnxt_" PCI_PRI_FMT "-%s", pci_dev->addr.domain,
4925                  pci_dev->addr.bus, pci_dev->addr.devid,
4926                  pci_dev->addr.function, "rx_port_stats");
4927         mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0;
4928         mz = rte_memzone_lookup(mz_name);
4929         total_alloc_len =
4930                 RTE_CACHE_LINE_ROUNDUP(sizeof(struct rx_port_stats) +
4931                                        sizeof(struct rx_port_stats_ext) + 512);
4932         if (!mz) {
4933                 mz = rte_memzone_reserve(mz_name, total_alloc_len,
4934                                          SOCKET_ID_ANY,
4935                                          RTE_MEMZONE_2MB |
4936                                          RTE_MEMZONE_SIZE_HINT_ONLY |
4937                                          RTE_MEMZONE_IOVA_CONTIG);
4938                 if (mz == NULL)
4939                         return -ENOMEM;
4940         }
4941         memset(mz->addr, 0, mz->len);
4942         mz_phys_addr = mz->iova;
4943
4944         bp->rx_mem_zone = (const void *)mz;
4945         bp->hw_rx_port_stats = mz->addr;
4946         bp->hw_rx_port_stats_map = mz_phys_addr;
4947
4948         snprintf(mz_name, RTE_MEMZONE_NAMESIZE,
4949                  "bnxt_" PCI_PRI_FMT "-%s", pci_dev->addr.domain,
4950                  pci_dev->addr.bus, pci_dev->addr.devid,
4951                  pci_dev->addr.function, "tx_port_stats");
4952         mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0;
4953         mz = rte_memzone_lookup(mz_name);
4954         total_alloc_len =
4955                 RTE_CACHE_LINE_ROUNDUP(sizeof(struct tx_port_stats) +
4956                                        sizeof(struct tx_port_stats_ext) + 512);
4957         if (!mz) {
4958                 mz = rte_memzone_reserve(mz_name,
4959                                          total_alloc_len,
4960                                          SOCKET_ID_ANY,
4961                                          RTE_MEMZONE_2MB |
4962                                          RTE_MEMZONE_SIZE_HINT_ONLY |
4963                                          RTE_MEMZONE_IOVA_CONTIG);
4964                 if (mz == NULL)
4965                         return -ENOMEM;
4966         }
4967         memset(mz->addr, 0, mz->len);
4968         mz_phys_addr = mz->iova;
4969
4970         bp->tx_mem_zone = (const void *)mz;
4971         bp->hw_tx_port_stats = mz->addr;
4972         bp->hw_tx_port_stats_map = mz_phys_addr;
4973         bp->flags |= BNXT_FLAG_PORT_STATS;
4974
4975         /* Display extended statistics if FW supports it */
4976         if (bp->hwrm_spec_code < HWRM_SPEC_CODE_1_8_4 ||
4977             bp->hwrm_spec_code == HWRM_SPEC_CODE_1_9_0 ||
4978             !(bp->flags & BNXT_FLAG_EXT_STATS_SUPPORTED))
4979                 return 0;
4980
4981         bp->hw_rx_port_stats_ext = (void *)
4982                 ((uint8_t *)bp->hw_rx_port_stats +
4983                  sizeof(struct rx_port_stats));
4984         bp->hw_rx_port_stats_ext_map = bp->hw_rx_port_stats_map +
4985                 sizeof(struct rx_port_stats);
4986         bp->flags |= BNXT_FLAG_EXT_RX_PORT_STATS;
4987
4988         if (bp->hwrm_spec_code < HWRM_SPEC_CODE_1_9_2 ||
4989             bp->flags & BNXT_FLAG_EXT_STATS_SUPPORTED) {
4990                 bp->hw_tx_port_stats_ext = (void *)
4991                         ((uint8_t *)bp->hw_tx_port_stats +
4992                          sizeof(struct tx_port_stats));
4993                 bp->hw_tx_port_stats_ext_map =
4994                         bp->hw_tx_port_stats_map +
4995                         sizeof(struct tx_port_stats);
4996                 bp->flags |= BNXT_FLAG_EXT_TX_PORT_STATS;
4997         }
4998
4999         return 0;
5000 }
5001
5002 static int bnxt_setup_mac_addr(struct rte_eth_dev *eth_dev)
5003 {
5004         struct bnxt *bp = eth_dev->data->dev_private;
5005         int rc = 0;
5006
5007         eth_dev->data->mac_addrs = rte_zmalloc("bnxt_mac_addr_tbl",
5008                                                RTE_ETHER_ADDR_LEN *
5009                                                bp->max_l2_ctx,
5010                                                0);
5011         if (eth_dev->data->mac_addrs == NULL) {
5012                 PMD_DRV_LOG(ERR, "Failed to alloc MAC addr tbl\n");
5013                 return -ENOMEM;
5014         }
5015
5016         if (!BNXT_HAS_DFLT_MAC_SET(bp)) {
5017                 if (BNXT_PF(bp))
5018                         return -EINVAL;
5019
5020                 /* Generate a random MAC address, if none was assigned by PF */
5021                 PMD_DRV_LOG(INFO, "VF MAC address not assigned by Host PF\n");
5022                 bnxt_eth_hw_addr_random(bp->mac_addr);
5023                 PMD_DRV_LOG(INFO,
5024                             "Assign random MAC:" RTE_ETHER_ADDR_PRT_FMT "\n",
5025                             bp->mac_addr[0], bp->mac_addr[1], bp->mac_addr[2],
5026                             bp->mac_addr[3], bp->mac_addr[4], bp->mac_addr[5]);
5027
5028                 rc = bnxt_hwrm_set_mac(bp);
5029                 if (rc)
5030                         return rc;
5031         }
5032
5033         /* Copy the permanent MAC from the FUNC_QCAPS response */
5034         memcpy(&eth_dev->data->mac_addrs[0], bp->mac_addr, RTE_ETHER_ADDR_LEN);
5035
5036         return rc;
5037 }
5038
5039 static int bnxt_restore_dflt_mac(struct bnxt *bp)
5040 {
5041         int rc = 0;
5042
5043         /* MAC is already configured in FW */
5044         if (BNXT_HAS_DFLT_MAC_SET(bp))
5045                 return 0;
5046
5047         /* Restore the old MAC configured */
5048         rc = bnxt_hwrm_set_mac(bp);
5049         if (rc)
5050                 PMD_DRV_LOG(ERR, "Failed to restore MAC address\n");
5051
5052         return rc;
5053 }
5054
5055 static void bnxt_config_vf_req_fwd(struct bnxt *bp)
5056 {
5057         if (!BNXT_PF(bp))
5058                 return;
5059
5060         memset(bp->pf->vf_req_fwd, 0, sizeof(bp->pf->vf_req_fwd));
5061
5062         if (!(bp->fw_cap & BNXT_FW_CAP_LINK_ADMIN))
5063                 BNXT_HWRM_CMD_TO_FORWARD(HWRM_PORT_PHY_QCFG);
5064         BNXT_HWRM_CMD_TO_FORWARD(HWRM_FUNC_CFG);
5065         BNXT_HWRM_CMD_TO_FORWARD(HWRM_FUNC_VF_CFG);
5066         BNXT_HWRM_CMD_TO_FORWARD(HWRM_CFA_L2_FILTER_ALLOC);
5067         BNXT_HWRM_CMD_TO_FORWARD(HWRM_OEM_CMD);
5068 }
5069
5070 struct bnxt *
5071 bnxt_get_bp(uint16_t port)
5072 {
5073         struct bnxt *bp;
5074         struct rte_eth_dev *dev;
5075
5076         if (!rte_eth_dev_is_valid_port(port)) {
5077                 PMD_DRV_LOG(ERR, "Invalid port %d\n", port);
5078                 return NULL;
5079         }
5080
5081         dev = &rte_eth_devices[port];
5082         if (!is_bnxt_supported(dev)) {
5083                 PMD_DRV_LOG(ERR, "Device %d not supported\n", port);
5084                 return NULL;
5085         }
5086
5087         bp = (struct bnxt *)dev->data->dev_private;
5088         if (!BNXT_TRUFLOW_EN(bp)) {
5089                 PMD_DRV_LOG(ERR, "TRUFLOW not enabled\n");
5090                 return NULL;
5091         }
5092
5093         return bp;
5094 }
5095
5096 uint16_t
5097 bnxt_get_svif(uint16_t port_id, bool func_svif,
5098               enum bnxt_ulp_intf_type type)
5099 {
5100         struct rte_eth_dev *eth_dev;
5101         struct bnxt *bp;
5102
5103         eth_dev = &rte_eth_devices[port_id];
5104         if (BNXT_ETH_DEV_IS_REPRESENTOR(eth_dev)) {
5105                 struct bnxt_representor *vfr = eth_dev->data->dev_private;
5106                 if (!vfr)
5107                         return 0;
5108
5109                 if (type == BNXT_ULP_INTF_TYPE_VF_REP)
5110                         return vfr->svif;
5111
5112                 eth_dev = vfr->parent_dev;
5113         }
5114
5115         bp = eth_dev->data->dev_private;
5116
5117         return func_svif ? bp->func_svif : bp->port_svif;
5118 }
5119
5120 void
5121 bnxt_get_iface_mac(uint16_t port, enum bnxt_ulp_intf_type type,
5122                    uint8_t *mac, uint8_t *parent_mac)
5123 {
5124         struct rte_eth_dev *eth_dev;
5125         struct bnxt *bp;
5126
5127         if (type != BNXT_ULP_INTF_TYPE_TRUSTED_VF &&
5128             type != BNXT_ULP_INTF_TYPE_PF)
5129                 return;
5130
5131         eth_dev = &rte_eth_devices[port];
5132         bp = eth_dev->data->dev_private;
5133         memcpy(mac, bp->mac_addr, RTE_ETHER_ADDR_LEN);
5134
5135         if (type == BNXT_ULP_INTF_TYPE_TRUSTED_VF)
5136                 memcpy(parent_mac, bp->parent->mac_addr, RTE_ETHER_ADDR_LEN);
5137 }
5138
5139 uint16_t
5140 bnxt_get_parent_vnic_id(uint16_t port, enum bnxt_ulp_intf_type type)
5141 {
5142         struct rte_eth_dev *eth_dev;
5143         struct bnxt *bp;
5144
5145         if (type != BNXT_ULP_INTF_TYPE_TRUSTED_VF)
5146                 return 0;
5147
5148         eth_dev = &rte_eth_devices[port];
5149         bp = eth_dev->data->dev_private;
5150
5151         return bp->parent->vnic;
5152 }
5153 uint16_t
5154 bnxt_get_vnic_id(uint16_t port, enum bnxt_ulp_intf_type type)
5155 {
5156         struct rte_eth_dev *eth_dev;
5157         struct bnxt_vnic_info *vnic;
5158         struct bnxt *bp;
5159
5160         eth_dev = &rte_eth_devices[port];
5161         if (BNXT_ETH_DEV_IS_REPRESENTOR(eth_dev)) {
5162                 struct bnxt_representor *vfr = eth_dev->data->dev_private;
5163                 if (!vfr)
5164                         return 0;
5165
5166                 if (type == BNXT_ULP_INTF_TYPE_VF_REP)
5167                         return vfr->dflt_vnic_id;
5168
5169                 eth_dev = vfr->parent_dev;
5170         }
5171
5172         bp = eth_dev->data->dev_private;
5173
5174         vnic = BNXT_GET_DEFAULT_VNIC(bp);
5175
5176         return vnic->fw_vnic_id;
5177 }
5178
5179 uint16_t
5180 bnxt_get_fw_func_id(uint16_t port, enum bnxt_ulp_intf_type type)
5181 {
5182         struct rte_eth_dev *eth_dev;
5183         struct bnxt *bp;
5184
5185         eth_dev = &rte_eth_devices[port];
5186         if (BNXT_ETH_DEV_IS_REPRESENTOR(eth_dev)) {
5187                 struct bnxt_representor *vfr = eth_dev->data->dev_private;
5188                 if (!vfr)
5189                         return 0;
5190
5191                 if (type == BNXT_ULP_INTF_TYPE_VF_REP)
5192                         return vfr->fw_fid;
5193
5194                 eth_dev = vfr->parent_dev;
5195         }
5196
5197         bp = eth_dev->data->dev_private;
5198
5199         return bp->fw_fid;
5200 }
5201
5202 enum bnxt_ulp_intf_type
5203 bnxt_get_interface_type(uint16_t port)
5204 {
5205         struct rte_eth_dev *eth_dev;
5206         struct bnxt *bp;
5207
5208         eth_dev = &rte_eth_devices[port];
5209         if (BNXT_ETH_DEV_IS_REPRESENTOR(eth_dev))
5210                 return BNXT_ULP_INTF_TYPE_VF_REP;
5211
5212         bp = eth_dev->data->dev_private;
5213         if (BNXT_PF(bp))
5214                 return BNXT_ULP_INTF_TYPE_PF;
5215         else if (BNXT_VF_IS_TRUSTED(bp))
5216                 return BNXT_ULP_INTF_TYPE_TRUSTED_VF;
5217         else if (BNXT_VF(bp))
5218                 return BNXT_ULP_INTF_TYPE_VF;
5219
5220         return BNXT_ULP_INTF_TYPE_INVALID;
5221 }
5222
5223 uint16_t
5224 bnxt_get_phy_port_id(uint16_t port_id)
5225 {
5226         struct bnxt_representor *vfr;
5227         struct rte_eth_dev *eth_dev;
5228         struct bnxt *bp;
5229
5230         eth_dev = &rte_eth_devices[port_id];
5231         if (BNXT_ETH_DEV_IS_REPRESENTOR(eth_dev)) {
5232                 vfr = eth_dev->data->dev_private;
5233                 if (!vfr)
5234                         return 0;
5235
5236                 eth_dev = vfr->parent_dev;
5237         }
5238
5239         bp = eth_dev->data->dev_private;
5240
5241         return BNXT_PF(bp) ? bp->pf->port_id : bp->parent->port_id;
5242 }
5243
5244 uint16_t
5245 bnxt_get_parif(uint16_t port_id, enum bnxt_ulp_intf_type type)
5246 {
5247         struct rte_eth_dev *eth_dev;
5248         struct bnxt *bp;
5249
5250         eth_dev = &rte_eth_devices[port_id];
5251         if (BNXT_ETH_DEV_IS_REPRESENTOR(eth_dev)) {
5252                 struct bnxt_representor *vfr = eth_dev->data->dev_private;
5253                 if (!vfr)
5254                         return 0;
5255
5256                 if (type == BNXT_ULP_INTF_TYPE_VF_REP)
5257                         return vfr->fw_fid - 1;
5258
5259                 eth_dev = vfr->parent_dev;
5260         }
5261
5262         bp = eth_dev->data->dev_private;
5263
5264         return BNXT_PF(bp) ? bp->fw_fid - 1 : bp->parent->fid - 1;
5265 }
5266
5267 uint16_t
5268 bnxt_get_vport(uint16_t port_id)
5269 {
5270         return (1 << bnxt_get_phy_port_id(port_id));
5271 }
5272
5273 static void bnxt_alloc_error_recovery_info(struct bnxt *bp)
5274 {
5275         struct bnxt_error_recovery_info *info = bp->recovery_info;
5276
5277         if (info) {
5278                 if (!(bp->fw_cap & BNXT_FW_CAP_HCOMM_FW_STATUS))
5279                         memset(info, 0, sizeof(*info));
5280                 return;
5281         }
5282
5283         if (!(bp->fw_cap & BNXT_FW_CAP_ERROR_RECOVERY))
5284                 return;
5285
5286         info = rte_zmalloc("bnxt_hwrm_error_recovery_qcfg",
5287                            sizeof(*info), 0);
5288         if (!info)
5289                 bp->fw_cap &= ~BNXT_FW_CAP_ERROR_RECOVERY;
5290
5291         bp->recovery_info = info;
5292 }
5293
5294 static void bnxt_check_fw_status(struct bnxt *bp)
5295 {
5296         uint32_t fw_status;
5297
5298         if (!(bp->recovery_info &&
5299               (bp->fw_cap & BNXT_FW_CAP_HCOMM_FW_STATUS)))
5300                 return;
5301
5302         fw_status = bnxt_read_fw_status_reg(bp, BNXT_FW_STATUS_REG);
5303         if (fw_status != BNXT_FW_STATUS_HEALTHY)
5304                 PMD_DRV_LOG(ERR, "Firmware not responding, status: %#x\n",
5305                             fw_status);
5306 }
5307
5308 static int bnxt_map_hcomm_fw_status_reg(struct bnxt *bp)
5309 {
5310         struct bnxt_error_recovery_info *info = bp->recovery_info;
5311         uint32_t status_loc;
5312         uint32_t sig_ver;
5313
5314         rte_write32(HCOMM_STATUS_STRUCT_LOC, (uint8_t *)bp->bar0 +
5315                     BNXT_GRCPF_REG_WINDOW_BASE_OUT + 4);
5316         sig_ver = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
5317                                    BNXT_GRCP_WINDOW_2_BASE +
5318                                    offsetof(struct hcomm_status,
5319                                             sig_ver)));
5320         /* If the signature is absent, then FW does not support this feature */
5321         if ((sig_ver & HCOMM_STATUS_SIGNATURE_MASK) !=
5322             HCOMM_STATUS_SIGNATURE_VAL)
5323                 return 0;
5324
5325         if (!info) {
5326                 info = rte_zmalloc("bnxt_hwrm_error_recovery_qcfg",
5327                                    sizeof(*info), 0);
5328                 if (!info)
5329                         return -ENOMEM;
5330                 bp->recovery_info = info;
5331         } else {
5332                 memset(info, 0, sizeof(*info));
5333         }
5334
5335         status_loc = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
5336                                       BNXT_GRCP_WINDOW_2_BASE +
5337                                       offsetof(struct hcomm_status,
5338                                                fw_status_loc)));
5339
5340         /* Only pre-map the FW health status GRC register */
5341         if (BNXT_FW_STATUS_REG_TYPE(status_loc) != BNXT_FW_STATUS_REG_TYPE_GRC)
5342                 return 0;
5343
5344         info->status_regs[BNXT_FW_STATUS_REG] = status_loc;
5345         info->mapped_status_regs[BNXT_FW_STATUS_REG] =
5346                 BNXT_GRCP_WINDOW_2_BASE + (status_loc & BNXT_GRCP_OFFSET_MASK);
5347
5348         rte_write32((status_loc & BNXT_GRCP_BASE_MASK), (uint8_t *)bp->bar0 +
5349                     BNXT_GRCPF_REG_WINDOW_BASE_OUT + 4);
5350
5351         bp->fw_cap |= BNXT_FW_CAP_HCOMM_FW_STATUS;
5352
5353         return 0;
5354 }
5355
5356 /* This function gets the FW version along with the
5357  * capabilities(MAX and current) of the function, vnic,
5358  * error recovery, phy and other chip related info
5359  */
5360 static int bnxt_get_config(struct bnxt *bp)
5361 {
5362         uint16_t mtu;
5363         int rc = 0;
5364
5365         bp->fw_cap = 0;
5366
5367         rc = bnxt_map_hcomm_fw_status_reg(bp);
5368         if (rc)
5369                 return rc;
5370
5371         rc = bnxt_hwrm_ver_get(bp, DFLT_HWRM_CMD_TIMEOUT);
5372         if (rc) {
5373                 bnxt_check_fw_status(bp);
5374                 return rc;
5375         }
5376
5377         rc = bnxt_hwrm_func_reset(bp);
5378         if (rc)
5379                 return -EIO;
5380
5381         rc = bnxt_hwrm_vnic_qcaps(bp);
5382         if (rc)
5383                 return rc;
5384
5385         rc = bnxt_hwrm_queue_qportcfg(bp);
5386         if (rc)
5387                 return rc;
5388
5389         /* Get the MAX capabilities for this function.
5390          * This function also allocates context memory for TQM rings and
5391          * informs the firmware about this allocated backing store memory.
5392          */
5393         rc = bnxt_hwrm_func_qcaps(bp);
5394         if (rc)
5395                 return rc;
5396
5397         rc = bnxt_hwrm_func_qcfg(bp, &mtu);
5398         if (rc)
5399                 return rc;
5400
5401         rc = bnxt_hwrm_cfa_adv_flow_mgmt_qcaps(bp);
5402         if (rc)
5403                 return rc;
5404
5405         bnxt_hwrm_port_mac_qcfg(bp);
5406
5407         bnxt_hwrm_parent_pf_qcfg(bp);
5408
5409         bnxt_hwrm_port_phy_qcaps(bp);
5410
5411         bnxt_alloc_error_recovery_info(bp);
5412         /* Get the adapter error recovery support info */
5413         rc = bnxt_hwrm_error_recovery_qcfg(bp);
5414         if (rc)
5415                 bp->fw_cap &= ~BNXT_FW_CAP_ERROR_RECOVERY;
5416
5417         bnxt_hwrm_port_led_qcaps(bp);
5418
5419         return 0;
5420 }
5421
5422 static int
5423 bnxt_init_locks(struct bnxt *bp)
5424 {
5425         int err;
5426
5427         err = pthread_mutex_init(&bp->flow_lock, NULL);
5428         if (err) {
5429                 PMD_DRV_LOG(ERR, "Unable to initialize flow_lock\n");
5430                 return err;
5431         }
5432
5433         err = pthread_mutex_init(&bp->def_cp_lock, NULL);
5434         if (err) {
5435                 PMD_DRV_LOG(ERR, "Unable to initialize def_cp_lock\n");
5436                 return err;
5437         }
5438
5439         err = pthread_mutex_init(&bp->health_check_lock, NULL);
5440         if (err) {
5441                 PMD_DRV_LOG(ERR, "Unable to initialize health_check_lock\n");
5442                 return err;
5443         }
5444
5445         err = pthread_mutex_init(&bp->err_recovery_lock, NULL);
5446         if (err)
5447                 PMD_DRV_LOG(ERR, "Unable to initialize err_recovery_lock\n");
5448
5449         return err;
5450 }
5451
5452 static int bnxt_init_resources(struct bnxt *bp, bool reconfig_dev)
5453 {
5454         int rc = 0;
5455
5456         rc = bnxt_get_config(bp);
5457         if (rc)
5458                 return rc;
5459
5460         if (!reconfig_dev) {
5461                 rc = bnxt_setup_mac_addr(bp->eth_dev);
5462                 if (rc)
5463                         return rc;
5464         } else {
5465                 rc = bnxt_restore_dflt_mac(bp);
5466                 if (rc)
5467                         return rc;
5468         }
5469
5470         bnxt_config_vf_req_fwd(bp);
5471
5472         rc = bnxt_hwrm_func_driver_register(bp);
5473         if (rc) {
5474                 PMD_DRV_LOG(ERR, "Failed to register driver");
5475                 return -EBUSY;
5476         }
5477
5478         if (BNXT_PF(bp)) {
5479                 if (bp->pdev->max_vfs) {
5480                         rc = bnxt_hwrm_allocate_vfs(bp, bp->pdev->max_vfs);
5481                         if (rc) {
5482                                 PMD_DRV_LOG(ERR, "Failed to allocate VFs\n");
5483                                 return rc;
5484                         }
5485                 } else {
5486                         rc = bnxt_hwrm_allocate_pf_only(bp);
5487                         if (rc) {
5488                                 PMD_DRV_LOG(ERR,
5489                                             "Failed to allocate PF resources");
5490                                 return rc;
5491                         }
5492                 }
5493         }
5494
5495         rc = bnxt_alloc_mem(bp, reconfig_dev);
5496         if (rc)
5497                 return rc;
5498
5499         rc = bnxt_setup_int(bp);
5500         if (rc)
5501                 return rc;
5502
5503         rc = bnxt_request_int(bp);
5504         if (rc)
5505                 return rc;
5506
5507         rc = bnxt_init_ctx_mem(bp);
5508         if (rc) {
5509                 PMD_DRV_LOG(ERR, "Failed to init adv_flow_counters\n");
5510                 return rc;
5511         }
5512
5513         return 0;
5514 }
5515
5516 static int
5517 bnxt_parse_devarg_accum_stats(__rte_unused const char *key,
5518                               const char *value, void *opaque_arg)
5519 {
5520         struct bnxt *bp = opaque_arg;
5521         unsigned long accum_stats;
5522         char *end = NULL;
5523
5524         if (!value || !opaque_arg) {
5525                 PMD_DRV_LOG(ERR,
5526                             "Invalid parameter passed to accum-stats devargs.\n");
5527                 return -EINVAL;
5528         }
5529
5530         accum_stats = strtoul(value, &end, 10);
5531         if (end == NULL || *end != '\0' ||
5532             (accum_stats == ULONG_MAX && errno == ERANGE)) {
5533                 PMD_DRV_LOG(ERR,
5534                             "Invalid parameter passed to accum-stats devargs.\n");
5535                 return -EINVAL;
5536         }
5537
5538         if (BNXT_DEVARG_ACCUM_STATS_INVALID(accum_stats)) {
5539                 PMD_DRV_LOG(ERR,
5540                             "Invalid value passed to accum-stats devargs.\n");
5541                 return -EINVAL;
5542         }
5543
5544         if (accum_stats) {
5545                 bp->flags2 |= BNXT_FLAGS2_ACCUM_STATS_EN;
5546                 PMD_DRV_LOG(INFO, "Host-based accum-stats feature enabled.\n");
5547         } else {
5548                 bp->flags2 &= ~BNXT_FLAGS2_ACCUM_STATS_EN;
5549                 PMD_DRV_LOG(INFO, "Host-based accum-stats feature disabled.\n");
5550         }
5551
5552         return 0;
5553 }
5554
5555 static int
5556 bnxt_parse_devarg_flow_xstat(__rte_unused const char *key,
5557                              const char *value, void *opaque_arg)
5558 {
5559         struct bnxt *bp = opaque_arg;
5560         unsigned long flow_xstat;
5561         char *end = NULL;
5562
5563         if (!value || !opaque_arg) {
5564                 PMD_DRV_LOG(ERR,
5565                             "Invalid parameter passed to flow_xstat devarg.\n");
5566                 return -EINVAL;
5567         }
5568
5569         flow_xstat = strtoul(value, &end, 10);
5570         if (end == NULL || *end != '\0' ||
5571             (flow_xstat == ULONG_MAX && errno == ERANGE)) {
5572                 PMD_DRV_LOG(ERR,
5573                             "Invalid parameter passed to flow_xstat devarg.\n");
5574                 return -EINVAL;
5575         }
5576
5577         if (BNXT_DEVARG_FLOW_XSTAT_INVALID(flow_xstat)) {
5578                 PMD_DRV_LOG(ERR,
5579                             "Invalid value passed to flow_xstat devarg.\n");
5580                 return -EINVAL;
5581         }
5582
5583         bp->flags |= BNXT_FLAG_FLOW_XSTATS_EN;
5584         if (BNXT_FLOW_XSTATS_EN(bp))
5585                 PMD_DRV_LOG(INFO, "flow_xstat feature enabled.\n");
5586
5587         return 0;
5588 }
5589
5590 static int
5591 bnxt_parse_devarg_max_num_kflows(__rte_unused const char *key,
5592                                         const char *value, void *opaque_arg)
5593 {
5594         struct bnxt *bp = opaque_arg;
5595         unsigned long max_num_kflows;
5596         char *end = NULL;
5597
5598         if (!value || !opaque_arg) {
5599                 PMD_DRV_LOG(ERR,
5600                         "Invalid parameter passed to max_num_kflows devarg.\n");
5601                 return -EINVAL;
5602         }
5603
5604         max_num_kflows = strtoul(value, &end, 10);
5605         if (end == NULL || *end != '\0' ||
5606                 (max_num_kflows == ULONG_MAX && errno == ERANGE)) {
5607                 PMD_DRV_LOG(ERR,
5608                         "Invalid parameter passed to max_num_kflows devarg.\n");
5609                 return -EINVAL;
5610         }
5611
5612         if (bnxt_devarg_max_num_kflow_invalid(max_num_kflows)) {
5613                 PMD_DRV_LOG(ERR,
5614                         "Invalid value passed to max_num_kflows devarg.\n");
5615                 return -EINVAL;
5616         }
5617
5618         bp->max_num_kflows = max_num_kflows;
5619         if (bp->max_num_kflows)
5620                 PMD_DRV_LOG(INFO, "max_num_kflows set as %ldK.\n",
5621                                 max_num_kflows);
5622
5623         return 0;
5624 }
5625
5626 static int
5627 bnxt_parse_devarg_app_id(__rte_unused const char *key,
5628                                  const char *value, void *opaque_arg)
5629 {
5630         struct bnxt *bp = opaque_arg;
5631         unsigned long app_id;
5632         char *end = NULL;
5633
5634         if (!value || !opaque_arg) {
5635                 PMD_DRV_LOG(ERR,
5636                             "Invalid parameter passed to app-id "
5637                             "devargs.\n");
5638                 return -EINVAL;
5639         }
5640
5641         app_id = strtoul(value, &end, 10);
5642         if (end == NULL || *end != '\0' ||
5643             (app_id == ULONG_MAX && errno == ERANGE)) {
5644                 PMD_DRV_LOG(ERR,
5645                             "Invalid parameter passed to app_id "
5646                             "devargs.\n");
5647                 return -EINVAL;
5648         }
5649
5650         if (BNXT_DEVARG_APP_ID_INVALID(app_id)) {
5651                 PMD_DRV_LOG(ERR, "Invalid app-id(%d) devargs.\n",
5652                             (uint16_t)app_id);
5653                 return -EINVAL;
5654         }
5655
5656         bp->app_id = app_id;
5657         PMD_DRV_LOG(INFO, "app-id=%d feature enabled.\n", (uint16_t)app_id);
5658
5659         return 0;
5660 }
5661
5662 static int
5663 bnxt_parse_devarg_rep_is_pf(__rte_unused const char *key,
5664                             const char *value, void *opaque_arg)
5665 {
5666         struct bnxt_representor *vfr_bp = opaque_arg;
5667         unsigned long rep_is_pf;
5668         char *end = NULL;
5669
5670         if (!value || !opaque_arg) {
5671                 PMD_DRV_LOG(ERR,
5672                             "Invalid parameter passed to rep_is_pf devargs.\n");
5673                 return -EINVAL;
5674         }
5675
5676         rep_is_pf = strtoul(value, &end, 10);
5677         if (end == NULL || *end != '\0' ||
5678             (rep_is_pf == ULONG_MAX && errno == ERANGE)) {
5679                 PMD_DRV_LOG(ERR,
5680                             "Invalid parameter passed to rep_is_pf devargs.\n");
5681                 return -EINVAL;
5682         }
5683
5684         if (BNXT_DEVARG_REP_IS_PF_INVALID(rep_is_pf)) {
5685                 PMD_DRV_LOG(ERR,
5686                             "Invalid value passed to rep_is_pf devargs.\n");
5687                 return -EINVAL;
5688         }
5689
5690         vfr_bp->flags |= rep_is_pf;
5691         if (BNXT_REP_PF(vfr_bp))
5692                 PMD_DRV_LOG(INFO, "PF representor\n");
5693         else
5694                 PMD_DRV_LOG(INFO, "VF representor\n");
5695
5696         return 0;
5697 }
5698
5699 static int
5700 bnxt_parse_devarg_rep_based_pf(__rte_unused const char *key,
5701                                const char *value, void *opaque_arg)
5702 {
5703         struct bnxt_representor *vfr_bp = opaque_arg;
5704         unsigned long rep_based_pf;
5705         char *end = NULL;
5706
5707         if (!value || !opaque_arg) {
5708                 PMD_DRV_LOG(ERR,
5709                             "Invalid parameter passed to rep_based_pf "
5710                             "devargs.\n");
5711                 return -EINVAL;
5712         }
5713
5714         rep_based_pf = strtoul(value, &end, 10);
5715         if (end == NULL || *end != '\0' ||
5716             (rep_based_pf == ULONG_MAX && errno == ERANGE)) {
5717                 PMD_DRV_LOG(ERR,
5718                             "Invalid parameter passed to rep_based_pf "
5719                             "devargs.\n");
5720                 return -EINVAL;
5721         }
5722
5723         if (BNXT_DEVARG_REP_BASED_PF_INVALID(rep_based_pf)) {
5724                 PMD_DRV_LOG(ERR,
5725                             "Invalid value passed to rep_based_pf devargs.\n");
5726                 return -EINVAL;
5727         }
5728
5729         vfr_bp->rep_based_pf = rep_based_pf;
5730         vfr_bp->flags |= BNXT_REP_BASED_PF_VALID;
5731
5732         PMD_DRV_LOG(INFO, "rep-based-pf = %d\n", vfr_bp->rep_based_pf);
5733
5734         return 0;
5735 }
5736
5737 static int
5738 bnxt_parse_devarg_rep_q_r2f(__rte_unused const char *key,
5739                             const char *value, void *opaque_arg)
5740 {
5741         struct bnxt_representor *vfr_bp = opaque_arg;
5742         unsigned long rep_q_r2f;
5743         char *end = NULL;
5744
5745         if (!value || !opaque_arg) {
5746                 PMD_DRV_LOG(ERR,
5747                             "Invalid parameter passed to rep_q_r2f "
5748                             "devargs.\n");
5749                 return -EINVAL;
5750         }
5751
5752         rep_q_r2f = strtoul(value, &end, 10);
5753         if (end == NULL || *end != '\0' ||
5754             (rep_q_r2f == ULONG_MAX && errno == ERANGE)) {
5755                 PMD_DRV_LOG(ERR,
5756                             "Invalid parameter passed to rep_q_r2f "
5757                             "devargs.\n");
5758                 return -EINVAL;
5759         }
5760
5761         if (BNXT_DEVARG_REP_Q_R2F_INVALID(rep_q_r2f)) {
5762                 PMD_DRV_LOG(ERR,
5763                             "Invalid value passed to rep_q_r2f devargs.\n");
5764                 return -EINVAL;
5765         }
5766
5767         vfr_bp->rep_q_r2f = rep_q_r2f;
5768         vfr_bp->flags |= BNXT_REP_Q_R2F_VALID;
5769         PMD_DRV_LOG(INFO, "rep-q-r2f = %d\n", vfr_bp->rep_q_r2f);
5770
5771         return 0;
5772 }
5773
5774 static int
5775 bnxt_parse_devarg_rep_q_f2r(__rte_unused const char *key,
5776                             const char *value, void *opaque_arg)
5777 {
5778         struct bnxt_representor *vfr_bp = opaque_arg;
5779         unsigned long rep_q_f2r;
5780         char *end = NULL;
5781
5782         if (!value || !opaque_arg) {
5783                 PMD_DRV_LOG(ERR,
5784                             "Invalid parameter passed to rep_q_f2r "
5785                             "devargs.\n");
5786                 return -EINVAL;
5787         }
5788
5789         rep_q_f2r = strtoul(value, &end, 10);
5790         if (end == NULL || *end != '\0' ||
5791             (rep_q_f2r == ULONG_MAX && errno == ERANGE)) {
5792                 PMD_DRV_LOG(ERR,
5793                             "Invalid parameter passed to rep_q_f2r "
5794                             "devargs.\n");
5795                 return -EINVAL;
5796         }
5797
5798         if (BNXT_DEVARG_REP_Q_F2R_INVALID(rep_q_f2r)) {
5799                 PMD_DRV_LOG(ERR,
5800                             "Invalid value passed to rep_q_f2r devargs.\n");
5801                 return -EINVAL;
5802         }
5803
5804         vfr_bp->rep_q_f2r = rep_q_f2r;
5805         vfr_bp->flags |= BNXT_REP_Q_F2R_VALID;
5806         PMD_DRV_LOG(INFO, "rep-q-f2r = %d\n", vfr_bp->rep_q_f2r);
5807
5808         return 0;
5809 }
5810
5811 static int
5812 bnxt_parse_devarg_rep_fc_r2f(__rte_unused const char *key,
5813                              const char *value, void *opaque_arg)
5814 {
5815         struct bnxt_representor *vfr_bp = opaque_arg;
5816         unsigned long rep_fc_r2f;
5817         char *end = NULL;
5818
5819         if (!value || !opaque_arg) {
5820                 PMD_DRV_LOG(ERR,
5821                             "Invalid parameter passed to rep_fc_r2f "
5822                             "devargs.\n");
5823                 return -EINVAL;
5824         }
5825
5826         rep_fc_r2f = strtoul(value, &end, 10);
5827         if (end == NULL || *end != '\0' ||
5828             (rep_fc_r2f == ULONG_MAX && errno == ERANGE)) {
5829                 PMD_DRV_LOG(ERR,
5830                             "Invalid parameter passed to rep_fc_r2f "
5831                             "devargs.\n");
5832                 return -EINVAL;
5833         }
5834
5835         if (BNXT_DEVARG_REP_FC_R2F_INVALID(rep_fc_r2f)) {
5836                 PMD_DRV_LOG(ERR,
5837                             "Invalid value passed to rep_fc_r2f devargs.\n");
5838                 return -EINVAL;
5839         }
5840
5841         vfr_bp->flags |= BNXT_REP_FC_R2F_VALID;
5842         vfr_bp->rep_fc_r2f = rep_fc_r2f;
5843         PMD_DRV_LOG(INFO, "rep-fc-r2f = %lu\n", rep_fc_r2f);
5844
5845         return 0;
5846 }
5847
5848 static int
5849 bnxt_parse_devarg_rep_fc_f2r(__rte_unused const char *key,
5850                              const char *value, void *opaque_arg)
5851 {
5852         struct bnxt_representor *vfr_bp = opaque_arg;
5853         unsigned long rep_fc_f2r;
5854         char *end = NULL;
5855
5856         if (!value || !opaque_arg) {
5857                 PMD_DRV_LOG(ERR,
5858                             "Invalid parameter passed to rep_fc_f2r "
5859                             "devargs.\n");
5860                 return -EINVAL;
5861         }
5862
5863         rep_fc_f2r = strtoul(value, &end, 10);
5864         if (end == NULL || *end != '\0' ||
5865             (rep_fc_f2r == ULONG_MAX && errno == ERANGE)) {
5866                 PMD_DRV_LOG(ERR,
5867                             "Invalid parameter passed to rep_fc_f2r "
5868                             "devargs.\n");
5869                 return -EINVAL;
5870         }
5871
5872         if (BNXT_DEVARG_REP_FC_F2R_INVALID(rep_fc_f2r)) {
5873                 PMD_DRV_LOG(ERR,
5874                             "Invalid value passed to rep_fc_f2r devargs.\n");
5875                 return -EINVAL;
5876         }
5877
5878         vfr_bp->flags |= BNXT_REP_FC_F2R_VALID;
5879         vfr_bp->rep_fc_f2r = rep_fc_f2r;
5880         PMD_DRV_LOG(INFO, "rep-fc-f2r = %lu\n", rep_fc_f2r);
5881
5882         return 0;
5883 }
5884
5885 static int
5886 bnxt_parse_dev_args(struct bnxt *bp, struct rte_devargs *devargs)
5887 {
5888         struct rte_kvargs *kvlist;
5889         int ret;
5890
5891         if (devargs == NULL)
5892                 return 0;
5893
5894         kvlist = rte_kvargs_parse(devargs->args, bnxt_dev_args);
5895         if (kvlist == NULL)
5896                 return -EINVAL;
5897
5898         /*
5899          * Handler for "flow_xstat" devarg.
5900          * Invoked as for ex: "-a 0000:00:0d.0,flow_xstat=1"
5901          */
5902         ret = rte_kvargs_process(kvlist, BNXT_DEVARG_FLOW_XSTAT,
5903                                  bnxt_parse_devarg_flow_xstat, bp);
5904         if (ret)
5905                 goto err;
5906
5907         /*
5908          * Handler for "accum-stats" devarg.
5909          * Invoked as for ex: "-a 0000:00:0d.0,accum-stats=1"
5910          */
5911         rte_kvargs_process(kvlist, BNXT_DEVARG_ACCUM_STATS,
5912                            bnxt_parse_devarg_accum_stats, bp);
5913         /*
5914          * Handler for "max_num_kflows" devarg.
5915          * Invoked as for ex: "-a 000:00:0d.0,max_num_kflows=32"
5916          */
5917         ret = rte_kvargs_process(kvlist, BNXT_DEVARG_MAX_NUM_KFLOWS,
5918                                  bnxt_parse_devarg_max_num_kflows, bp);
5919         if (ret)
5920                 goto err;
5921
5922 err:
5923         /*
5924          * Handler for "app-id" devarg.
5925          * Invoked as for ex: "-a 000:00:0d.0,app-id=1"
5926          */
5927         rte_kvargs_process(kvlist, BNXT_DEVARG_APP_ID,
5928                            bnxt_parse_devarg_app_id, bp);
5929
5930         rte_kvargs_free(kvlist);
5931         return ret;
5932 }
5933
5934 static int bnxt_alloc_switch_domain(struct bnxt *bp)
5935 {
5936         int rc = 0;
5937
5938         if (BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp)) {
5939                 rc = rte_eth_switch_domain_alloc(&bp->switch_domain_id);
5940                 if (rc)
5941                         PMD_DRV_LOG(ERR,
5942                                     "Failed to alloc switch domain: %d\n", rc);
5943                 else
5944                         PMD_DRV_LOG(INFO,
5945                                     "Switch domain allocated %d\n",
5946                                     bp->switch_domain_id);
5947         }
5948
5949         return rc;
5950 }
5951
5952 /* Allocate and initialize various fields in bnxt struct that
5953  * need to be allocated/destroyed only once in the lifetime of the driver
5954  */
5955 static int bnxt_drv_init(struct rte_eth_dev *eth_dev)
5956 {
5957         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
5958         struct bnxt *bp = eth_dev->data->dev_private;
5959         int rc = 0;
5960
5961         bp->flags &= ~BNXT_FLAG_RX_VECTOR_PKT_MODE;
5962
5963         if (bnxt_vf_pciid(pci_dev->id.device_id))
5964                 bp->flags |= BNXT_FLAG_VF;
5965
5966         if (bnxt_p5_device(pci_dev->id.device_id))
5967                 bp->flags |= BNXT_FLAG_CHIP_P5;
5968
5969         if (pci_dev->id.device_id == BROADCOM_DEV_ID_58802 ||
5970             pci_dev->id.device_id == BROADCOM_DEV_ID_58804 ||
5971             pci_dev->id.device_id == BROADCOM_DEV_ID_58808 ||
5972             pci_dev->id.device_id == BROADCOM_DEV_ID_58802_VF)
5973                 bp->flags |= BNXT_FLAG_STINGRAY;
5974
5975         if (BNXT_TRUFLOW_EN(bp)) {
5976                 /* extra mbuf field is required to store CFA code from mark */
5977                 static const struct rte_mbuf_dynfield bnxt_cfa_code_dynfield_desc = {
5978                         .name = RTE_PMD_BNXT_CFA_CODE_DYNFIELD_NAME,
5979                         .size = sizeof(bnxt_cfa_code_dynfield_t),
5980                         .align = __alignof__(bnxt_cfa_code_dynfield_t),
5981                 };
5982                 bnxt_cfa_code_dynfield_offset =
5983                         rte_mbuf_dynfield_register(&bnxt_cfa_code_dynfield_desc);
5984                 if (bnxt_cfa_code_dynfield_offset < 0) {
5985                         PMD_DRV_LOG(ERR,
5986                             "Failed to register mbuf field for TruFlow mark\n");
5987                         return -rte_errno;
5988                 }
5989         }
5990
5991         rc = bnxt_map_pci_bars(eth_dev);
5992         if (rc) {
5993                 PMD_DRV_LOG(ERR,
5994                             "Failed to initialize board rc: %x\n", rc);
5995                 return rc;
5996         }
5997
5998         rc = bnxt_alloc_pf_info(bp);
5999         if (rc)
6000                 return rc;
6001
6002         rc = bnxt_alloc_link_info(bp);
6003         if (rc)
6004                 return rc;
6005
6006         rc = bnxt_alloc_parent_info(bp);
6007         if (rc)
6008                 return rc;
6009
6010         rc = bnxt_alloc_hwrm_resources(bp);
6011         if (rc) {
6012                 PMD_DRV_LOG(ERR,
6013                             "Failed to allocate response buffer rc: %x\n", rc);
6014                 return rc;
6015         }
6016         rc = bnxt_alloc_leds_info(bp);
6017         if (rc)
6018                 return rc;
6019
6020         rc = bnxt_alloc_cos_queues(bp);
6021         if (rc)
6022                 return rc;
6023
6024         rc = bnxt_init_locks(bp);
6025         if (rc)
6026                 return rc;
6027
6028         rc = bnxt_alloc_switch_domain(bp);
6029         if (rc)
6030                 return rc;
6031
6032         return rc;
6033 }
6034
6035 static int
6036 bnxt_dev_init(struct rte_eth_dev *eth_dev, void *params __rte_unused)
6037 {
6038         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
6039         static int version_printed;
6040         struct bnxt *bp;
6041         int rc;
6042
6043         if (version_printed++ == 0)
6044                 PMD_DRV_LOG(INFO, "%s\n", bnxt_version);
6045
6046         eth_dev->dev_ops = &bnxt_dev_ops;
6047         eth_dev->rx_queue_count = bnxt_rx_queue_count_op;
6048         eth_dev->rx_descriptor_status = bnxt_rx_descriptor_status_op;
6049         eth_dev->tx_descriptor_status = bnxt_tx_descriptor_status_op;
6050         eth_dev->rx_pkt_burst = &bnxt_recv_pkts;
6051         eth_dev->tx_pkt_burst = &bnxt_xmit_pkts;
6052
6053         /*
6054          * For secondary processes, we don't initialise any further
6055          * as primary has already done this work.
6056          */
6057         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
6058                 return 0;
6059
6060         rte_eth_copy_pci_info(eth_dev, pci_dev);
6061         eth_dev->data->dev_flags |= RTE_ETH_DEV_AUTOFILL_QUEUE_XSTATS;
6062
6063         bp = eth_dev->data->dev_private;
6064
6065         /* Parse dev arguments passed on when starting the DPDK application. */
6066         rc = bnxt_parse_dev_args(bp, pci_dev->device.devargs);
6067         if (rc)
6068                 goto error_free;
6069
6070         rc = bnxt_drv_init(eth_dev);
6071         if (rc)
6072                 goto error_free;
6073
6074         rc = bnxt_init_resources(bp, false);
6075         if (rc)
6076                 goto error_free;
6077
6078         rc = bnxt_alloc_stats_mem(bp);
6079         if (rc)
6080                 goto error_free;
6081
6082         PMD_DRV_LOG(INFO,
6083                     "Found %s device at mem %" PRIX64 ", node addr %pM\n",
6084                     DRV_MODULE_NAME,
6085                     pci_dev->mem_resource[0].phys_addr,
6086                     pci_dev->mem_resource[0].addr);
6087
6088         return 0;
6089
6090 error_free:
6091         bnxt_dev_uninit(eth_dev);
6092         return rc;
6093 }
6094
6095
6096 static void bnxt_free_ctx_mem_buf(struct bnxt_ctx_mem_buf_info *ctx)
6097 {
6098         if (!ctx)
6099                 return;
6100
6101         if (ctx->va)
6102                 rte_free(ctx->va);
6103
6104         ctx->va = NULL;
6105         ctx->dma = RTE_BAD_IOVA;
6106         ctx->ctx_id = BNXT_CTX_VAL_INVAL;
6107 }
6108
6109 static void bnxt_unregister_fc_ctx_mem(struct bnxt *bp)
6110 {
6111         bnxt_hwrm_cfa_counter_cfg(bp, BNXT_DIR_RX,
6112                                   CFA_COUNTER_CFG_IN_COUNTER_TYPE_FC,
6113                                   bp->flow_stat->rx_fc_out_tbl.ctx_id,
6114                                   bp->flow_stat->max_fc,
6115                                   false);
6116
6117         bnxt_hwrm_cfa_counter_cfg(bp, BNXT_DIR_TX,
6118                                   CFA_COUNTER_CFG_IN_COUNTER_TYPE_FC,
6119                                   bp->flow_stat->tx_fc_out_tbl.ctx_id,
6120                                   bp->flow_stat->max_fc,
6121                                   false);
6122
6123         if (bp->flow_stat->rx_fc_in_tbl.ctx_id != BNXT_CTX_VAL_INVAL)
6124                 bnxt_hwrm_ctx_unrgtr(bp, bp->flow_stat->rx_fc_in_tbl.ctx_id);
6125         bp->flow_stat->rx_fc_in_tbl.ctx_id = BNXT_CTX_VAL_INVAL;
6126
6127         if (bp->flow_stat->rx_fc_out_tbl.ctx_id != BNXT_CTX_VAL_INVAL)
6128                 bnxt_hwrm_ctx_unrgtr(bp, bp->flow_stat->rx_fc_out_tbl.ctx_id);
6129         bp->flow_stat->rx_fc_out_tbl.ctx_id = BNXT_CTX_VAL_INVAL;
6130
6131         if (bp->flow_stat->tx_fc_in_tbl.ctx_id != BNXT_CTX_VAL_INVAL)
6132                 bnxt_hwrm_ctx_unrgtr(bp, bp->flow_stat->tx_fc_in_tbl.ctx_id);
6133         bp->flow_stat->tx_fc_in_tbl.ctx_id = BNXT_CTX_VAL_INVAL;
6134
6135         if (bp->flow_stat->tx_fc_out_tbl.ctx_id != BNXT_CTX_VAL_INVAL)
6136                 bnxt_hwrm_ctx_unrgtr(bp, bp->flow_stat->tx_fc_out_tbl.ctx_id);
6137         bp->flow_stat->tx_fc_out_tbl.ctx_id = BNXT_CTX_VAL_INVAL;
6138 }
6139
6140 static void bnxt_uninit_fc_ctx_mem(struct bnxt *bp)
6141 {
6142         bnxt_unregister_fc_ctx_mem(bp);
6143
6144         bnxt_free_ctx_mem_buf(&bp->flow_stat->rx_fc_in_tbl);
6145         bnxt_free_ctx_mem_buf(&bp->flow_stat->rx_fc_out_tbl);
6146         bnxt_free_ctx_mem_buf(&bp->flow_stat->tx_fc_in_tbl);
6147         bnxt_free_ctx_mem_buf(&bp->flow_stat->tx_fc_out_tbl);
6148 }
6149
6150 static void bnxt_uninit_ctx_mem(struct bnxt *bp)
6151 {
6152         if (BNXT_FLOW_XSTATS_EN(bp))
6153                 bnxt_uninit_fc_ctx_mem(bp);
6154 }
6155
6156 static void
6157 bnxt_free_error_recovery_info(struct bnxt *bp)
6158 {
6159         rte_free(bp->recovery_info);
6160         bp->recovery_info = NULL;
6161         bp->fw_cap &= ~BNXT_FW_CAP_ERROR_RECOVERY;
6162 }
6163
6164 static int
6165 bnxt_uninit_resources(struct bnxt *bp, bool reconfig_dev)
6166 {
6167         int rc;
6168
6169         bnxt_free_int(bp);
6170         bnxt_free_mem(bp, reconfig_dev);
6171
6172         bnxt_hwrm_func_buf_unrgtr(bp);
6173         if (bp->pf != NULL) {
6174                 rte_free(bp->pf->vf_req_buf);
6175                 bp->pf->vf_req_buf = NULL;
6176         }
6177
6178         rc = bnxt_hwrm_func_driver_unregister(bp);
6179         bp->flags &= ~BNXT_FLAG_REGISTERED;
6180         bnxt_free_ctx_mem(bp);
6181         if (!reconfig_dev) {
6182                 bnxt_free_hwrm_resources(bp);
6183                 bnxt_free_error_recovery_info(bp);
6184         }
6185
6186         bnxt_uninit_ctx_mem(bp);
6187
6188         bnxt_free_flow_stats_info(bp);
6189         if (bp->rep_info != NULL)
6190                 bnxt_free_switch_domain(bp);
6191         bnxt_free_rep_info(bp);
6192         rte_free(bp->ptp_cfg);
6193         bp->ptp_cfg = NULL;
6194         return rc;
6195 }
6196
6197 static int
6198 bnxt_dev_uninit(struct rte_eth_dev *eth_dev)
6199 {
6200         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
6201                 return -EPERM;
6202
6203         PMD_DRV_LOG(DEBUG, "Calling Device uninit\n");
6204
6205         if (eth_dev->state != RTE_ETH_DEV_UNUSED)
6206                 bnxt_dev_close_op(eth_dev);
6207
6208         return 0;
6209 }
6210
6211 static int bnxt_pci_remove_dev_with_reps(struct rte_eth_dev *eth_dev)
6212 {
6213         struct bnxt *bp = eth_dev->data->dev_private;
6214         struct rte_eth_dev *vf_rep_eth_dev;
6215         int ret = 0, i;
6216
6217         if (!bp)
6218                 return -EINVAL;
6219
6220         for (i = 0; i < bp->num_reps; i++) {
6221                 vf_rep_eth_dev = bp->rep_info[i].vfr_eth_dev;
6222                 if (!vf_rep_eth_dev)
6223                         continue;
6224                 PMD_DRV_LOG(DEBUG, "BNXT Port:%d VFR pci remove\n",
6225                             vf_rep_eth_dev->data->port_id);
6226                 rte_eth_dev_destroy(vf_rep_eth_dev, bnxt_representor_uninit);
6227         }
6228         PMD_DRV_LOG(DEBUG, "BNXT Port:%d pci remove\n",
6229                     eth_dev->data->port_id);
6230         ret = rte_eth_dev_destroy(eth_dev, bnxt_dev_uninit);
6231
6232         return ret;
6233 }
6234
6235 static void bnxt_free_rep_info(struct bnxt *bp)
6236 {
6237         rte_free(bp->rep_info);
6238         bp->rep_info = NULL;
6239         rte_free(bp->cfa_code_map);
6240         bp->cfa_code_map = NULL;
6241 }
6242
6243 static int bnxt_init_rep_info(struct bnxt *bp)
6244 {
6245         int i = 0, rc;
6246
6247         if (bp->rep_info)
6248                 return 0;
6249
6250         bp->rep_info = rte_zmalloc("bnxt_rep_info",
6251                                    sizeof(bp->rep_info[0]) * BNXT_MAX_VF_REPS,
6252                                    0);
6253         if (!bp->rep_info) {
6254                 PMD_DRV_LOG(ERR, "Failed to alloc memory for rep info\n");
6255                 return -ENOMEM;
6256         }
6257         bp->cfa_code_map = rte_zmalloc("bnxt_cfa_code_map",
6258                                        sizeof(*bp->cfa_code_map) *
6259                                        BNXT_MAX_CFA_CODE, 0);
6260         if (!bp->cfa_code_map) {
6261                 PMD_DRV_LOG(ERR, "Failed to alloc memory for cfa_code_map\n");
6262                 bnxt_free_rep_info(bp);
6263                 return -ENOMEM;
6264         }
6265
6266         for (i = 0; i < BNXT_MAX_CFA_CODE; i++)
6267                 bp->cfa_code_map[i] = BNXT_VF_IDX_INVALID;
6268
6269         rc = pthread_mutex_init(&bp->rep_info->vfr_lock, NULL);
6270         if (rc) {
6271                 PMD_DRV_LOG(ERR, "Unable to initialize vfr_lock\n");
6272                 bnxt_free_rep_info(bp);
6273                 return rc;
6274         }
6275
6276         rc = pthread_mutex_init(&bp->rep_info->vfr_start_lock, NULL);
6277         if (rc) {
6278                 PMD_DRV_LOG(ERR, "Unable to initialize vfr_start_lock\n");
6279                 bnxt_free_rep_info(bp);
6280                 return rc;
6281         }
6282
6283         return rc;
6284 }
6285
6286 static int bnxt_rep_port_probe(struct rte_pci_device *pci_dev,
6287                                struct rte_eth_devargs *eth_da,
6288                                struct rte_eth_dev *backing_eth_dev,
6289                                const char *dev_args)
6290 {
6291         struct rte_eth_dev *vf_rep_eth_dev;
6292         char name[RTE_ETH_NAME_MAX_LEN];
6293         struct bnxt *backing_bp;
6294         uint16_t num_rep;
6295         int i, ret = 0;
6296         struct rte_kvargs *kvlist = NULL;
6297
6298         if (eth_da->type == RTE_ETH_REPRESENTOR_NONE)
6299                 return 0;
6300         if (eth_da->type != RTE_ETH_REPRESENTOR_VF) {
6301                 PMD_DRV_LOG(ERR, "unsupported representor type %d\n",
6302                             eth_da->type);
6303                 return -ENOTSUP;
6304         }
6305         num_rep = eth_da->nb_representor_ports;
6306         if (num_rep > BNXT_MAX_VF_REPS) {
6307                 PMD_DRV_LOG(ERR, "nb_representor_ports = %d > %d MAX VF REPS\n",
6308                             num_rep, BNXT_MAX_VF_REPS);
6309                 return -EINVAL;
6310         }
6311
6312         if (num_rep >= RTE_MAX_ETHPORTS) {
6313                 PMD_DRV_LOG(ERR,
6314                             "nb_representor_ports = %d > %d MAX ETHPORTS\n",
6315                             num_rep, RTE_MAX_ETHPORTS);
6316                 return -EINVAL;
6317         }
6318
6319         backing_bp = backing_eth_dev->data->dev_private;
6320
6321         if (!(BNXT_PF(backing_bp) || BNXT_VF_IS_TRUSTED(backing_bp))) {
6322                 PMD_DRV_LOG(ERR,
6323                             "Not a PF or trusted VF. No Representor support\n");
6324                 /* Returning an error is not an option.
6325                  * Applications are not handling this correctly
6326                  */
6327                 return 0;
6328         }
6329
6330         if (bnxt_init_rep_info(backing_bp))
6331                 return 0;
6332
6333         for (i = 0; i < num_rep; i++) {
6334                 struct bnxt_representor representor = {
6335                         .vf_id = eth_da->representor_ports[i],
6336                         .switch_domain_id = backing_bp->switch_domain_id,
6337                         .parent_dev = backing_eth_dev
6338                 };
6339
6340                 if (representor.vf_id >= BNXT_MAX_VF_REPS) {
6341                         PMD_DRV_LOG(ERR, "VF-Rep id %d >= %d MAX VF ID\n",
6342                                     representor.vf_id, BNXT_MAX_VF_REPS);
6343                         continue;
6344                 }
6345
6346                 /* representor port net_bdf_port */
6347                 snprintf(name, sizeof(name), "net_%s_representor_%d",
6348                          pci_dev->device.name, eth_da->representor_ports[i]);
6349
6350                 kvlist = rte_kvargs_parse(dev_args, bnxt_dev_args);
6351                 if (kvlist) {
6352                         /*
6353                          * Handler for "rep_is_pf" devarg.
6354                          * Invoked as for ex: "-a 000:00:0d.0,
6355                          * rep-based-pf=<pf index> rep-is-pf=<VF=0 or PF=1>"
6356                          */
6357                         ret = rte_kvargs_process(kvlist, BNXT_DEVARG_REP_IS_PF,
6358                                                  bnxt_parse_devarg_rep_is_pf,
6359                                                  (void *)&representor);
6360                         if (ret) {
6361                                 ret = -EINVAL;
6362                                 goto err;
6363                         }
6364                         /*
6365                          * Handler for "rep_based_pf" devarg.
6366                          * Invoked as for ex: "-a 000:00:0d.0,
6367                          * rep-based-pf=<pf index> rep-is-pf=<VF=0 or PF=1>"
6368                          */
6369                         ret = rte_kvargs_process(kvlist,
6370                                                  BNXT_DEVARG_REP_BASED_PF,
6371                                                  bnxt_parse_devarg_rep_based_pf,
6372                                                  (void *)&representor);
6373                         if (ret) {
6374                                 ret = -EINVAL;
6375                                 goto err;
6376                         }
6377                         /*
6378                          * Handler for "rep_based_pf" devarg.
6379                          * Invoked as for ex: "-a 000:00:0d.0,
6380                          * rep-based-pf=<pf index> rep-is-pf=<VF=0 or PF=1>"
6381                          */
6382                         ret = rte_kvargs_process(kvlist, BNXT_DEVARG_REP_Q_R2F,
6383                                                  bnxt_parse_devarg_rep_q_r2f,
6384                                                  (void *)&representor);
6385                         if (ret) {
6386                                 ret = -EINVAL;
6387                                 goto err;
6388                         }
6389                         /*
6390                          * Handler for "rep_based_pf" devarg.
6391                          * Invoked as for ex: "-a 000:00:0d.0,
6392                          * rep-based-pf=<pf index> rep-is-pf=<VF=0 or PF=1>"
6393                          */
6394                         ret = rte_kvargs_process(kvlist, BNXT_DEVARG_REP_Q_F2R,
6395                                                  bnxt_parse_devarg_rep_q_f2r,
6396                                                  (void *)&representor);
6397                         if (ret) {
6398                                 ret = -EINVAL;
6399                                 goto err;
6400                         }
6401                         /*
6402                          * Handler for "rep_based_pf" devarg.
6403                          * Invoked as for ex: "-a 000:00:0d.0,
6404                          * rep-based-pf=<pf index> rep-is-pf=<VF=0 or PF=1>"
6405                          */
6406                         ret = rte_kvargs_process(kvlist, BNXT_DEVARG_REP_FC_R2F,
6407                                                  bnxt_parse_devarg_rep_fc_r2f,
6408                                                  (void *)&representor);
6409                         if (ret) {
6410                                 ret = -EINVAL;
6411                                 goto err;
6412                         }
6413                         /*
6414                          * Handler for "rep_based_pf" devarg.
6415                          * Invoked as for ex: "-a 000:00:0d.0,
6416                          * rep-based-pf=<pf index> rep-is-pf=<VF=0 or PF=1>"
6417                          */
6418                         ret = rte_kvargs_process(kvlist, BNXT_DEVARG_REP_FC_F2R,
6419                                                  bnxt_parse_devarg_rep_fc_f2r,
6420                                                  (void *)&representor);
6421                         if (ret) {
6422                                 ret = -EINVAL;
6423                                 goto err;
6424                         }
6425                 }
6426
6427                 ret = rte_eth_dev_create(&pci_dev->device, name,
6428                                          sizeof(struct bnxt_representor),
6429                                          NULL, NULL,
6430                                          bnxt_representor_init,
6431                                          &representor);
6432                 if (ret) {
6433                         PMD_DRV_LOG(ERR, "failed to create bnxt vf "
6434                                     "representor %s.", name);
6435                         goto err;
6436                 }
6437
6438                 vf_rep_eth_dev = rte_eth_dev_allocated(name);
6439                 if (!vf_rep_eth_dev) {
6440                         PMD_DRV_LOG(ERR, "Failed to find the eth_dev"
6441                                     " for VF-Rep: %s.", name);
6442                         ret = -ENODEV;
6443                         goto err;
6444                 }
6445
6446                 PMD_DRV_LOG(DEBUG, "BNXT Port:%d VFR pci probe\n",
6447                             backing_eth_dev->data->port_id);
6448                 backing_bp->rep_info[representor.vf_id].vfr_eth_dev =
6449                                                          vf_rep_eth_dev;
6450                 backing_bp->num_reps++;
6451
6452         }
6453
6454         rte_kvargs_free(kvlist);
6455         return 0;
6456
6457 err:
6458         /* If num_rep > 1, then rollback already created
6459          * ports, since we'll be failing the probe anyway
6460          */
6461         if (num_rep > 1)
6462                 bnxt_pci_remove_dev_with_reps(backing_eth_dev);
6463         rte_errno = -ret;
6464         rte_kvargs_free(kvlist);
6465
6466         return ret;
6467 }
6468
6469 static int bnxt_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
6470                           struct rte_pci_device *pci_dev)
6471 {
6472         struct rte_eth_devargs eth_da = { .nb_representor_ports = 0 };
6473         struct rte_eth_dev *backing_eth_dev;
6474         uint16_t num_rep;
6475         int ret = 0;
6476
6477         if (pci_dev->device.devargs) {
6478                 ret = rte_eth_devargs_parse(pci_dev->device.devargs->args,
6479                                             &eth_da);
6480                 if (ret)
6481                         return ret;
6482         }
6483
6484         num_rep = eth_da.nb_representor_ports;
6485         PMD_DRV_LOG(DEBUG, "nb_representor_ports = %d\n",
6486                     num_rep);
6487
6488         /* We could come here after first level of probe is already invoked
6489          * as part of an application bringup(OVS-DPDK vswitchd), so first check
6490          * for already allocated eth_dev for the backing device (PF/Trusted VF)
6491          */
6492         backing_eth_dev = rte_eth_dev_allocated(pci_dev->device.name);
6493         if (backing_eth_dev == NULL) {
6494                 ret = rte_eth_dev_create(&pci_dev->device, pci_dev->device.name,
6495                                          sizeof(struct bnxt),
6496                                          eth_dev_pci_specific_init, pci_dev,
6497                                          bnxt_dev_init, NULL);
6498
6499                 if (ret || !num_rep)
6500                         return ret;
6501
6502                 backing_eth_dev = rte_eth_dev_allocated(pci_dev->device.name);
6503         }
6504         PMD_DRV_LOG(DEBUG, "BNXT Port:%d pci probe\n",
6505                     backing_eth_dev->data->port_id);
6506
6507         if (!num_rep)
6508                 return ret;
6509
6510         /* probe representor ports now */
6511         ret = bnxt_rep_port_probe(pci_dev, &eth_da, backing_eth_dev,
6512                                   pci_dev->device.devargs->args);
6513
6514         return ret;
6515 }
6516
6517 static int bnxt_pci_remove(struct rte_pci_device *pci_dev)
6518 {
6519         struct rte_eth_dev *eth_dev;
6520
6521         eth_dev = rte_eth_dev_allocated(pci_dev->device.name);
6522         if (!eth_dev)
6523                 return 0; /* Invoked typically only by OVS-DPDK, by the
6524                            * time it comes here the eth_dev is already
6525                            * deleted by rte_eth_dev_close(), so returning
6526                            * +ve value will at least help in proper cleanup
6527                            */
6528
6529         PMD_DRV_LOG(DEBUG, "BNXT Port:%d pci remove\n", eth_dev->data->port_id);
6530         if (rte_eal_process_type() == RTE_PROC_PRIMARY) {
6531                 if (eth_dev->data->dev_flags & RTE_ETH_DEV_REPRESENTOR)
6532                         return rte_eth_dev_destroy(eth_dev,
6533                                                    bnxt_representor_uninit);
6534                 else
6535                         return rte_eth_dev_destroy(eth_dev,
6536                                                    bnxt_dev_uninit);
6537         } else {
6538                 return rte_eth_dev_pci_generic_remove(pci_dev, NULL);
6539         }
6540 }
6541
6542 static struct rte_pci_driver bnxt_rte_pmd = {
6543         .id_table = bnxt_pci_id_map,
6544         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC |
6545                         RTE_PCI_DRV_INTR_RMV |
6546                         RTE_PCI_DRV_PROBE_AGAIN, /* Needed in case of VF-REPs
6547                                                   * and OVS-DPDK
6548                                                   */
6549         .probe = bnxt_pci_probe,
6550         .remove = bnxt_pci_remove,
6551 };
6552
6553 static bool
6554 is_device_supported(struct rte_eth_dev *dev, struct rte_pci_driver *drv)
6555 {
6556         if (strcmp(dev->device->driver->name, drv->driver.name))
6557                 return false;
6558
6559         return true;
6560 }
6561
6562 bool is_bnxt_supported(struct rte_eth_dev *dev)
6563 {
6564         return is_device_supported(dev, &bnxt_rte_pmd);
6565 }
6566
6567 RTE_LOG_REGISTER_SUFFIX(bnxt_logtype_driver, driver, NOTICE);
6568 RTE_PMD_REGISTER_PCI(net_bnxt, bnxt_rte_pmd);
6569 RTE_PMD_REGISTER_PCI_TABLE(net_bnxt, bnxt_pci_id_map);
6570 RTE_PMD_REGISTER_KMOD_DEP(net_bnxt, "* igb_uio | uio_pci_generic | vfio-pci");