drivers/net/bnxt/bnxt_ethdev.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2014-2018 Broadcom
   3  * All rights reserved.
   4  */
   5
   6 #include <inttypes.h>
   7 #include <stdbool.h>
   8
   9 #include <rte_dev.h>
  10 #include <rte_ethdev_driver.h>
  11 #include <rte_ethdev_pci.h>
  12 #include <rte_malloc.h>
  13 #include <rte_cycles.h>
  14
  15 #include "bnxt.h"
  16 #include "bnxt_cpr.h"
  17 #include "bnxt_filter.h"
  18 #include "bnxt_hwrm.h"
  19 #include "bnxt_irq.h"
  20 #include "bnxt_ring.h"
  21 #include "bnxt_rxq.h"
  22 #include "bnxt_rxr.h"
  23 #include "bnxt_stats.h"
  24 #include "bnxt_txq.h"
  25 #include "bnxt_txr.h"
  26 #include "bnxt_vnic.h"
  27 #include "hsi_struct_def_dpdk.h"
  28 #include "bnxt_nvm_defs.h"
  29 #include "bnxt_util.h"
  30
  31 #define DRV_MODULE_NAME         "bnxt"
  32 static const char bnxt_version[] =
  33         "Broadcom NetXtreme driver " DRV_MODULE_NAME;
  34 int bnxt_logtype_driver;
  35
  36 #define PCI_VENDOR_ID_BROADCOM 0x14E4
  37
  38 #define BROADCOM_DEV_ID_STRATUS_NIC_VF1 0x1606
  39 #define BROADCOM_DEV_ID_STRATUS_NIC_VF2 0x1609
  40 #define BROADCOM_DEV_ID_STRATUS_NIC 0x1614
  41 #define BROADCOM_DEV_ID_57414_VF 0x16c1
  42 #define BROADCOM_DEV_ID_57301 0x16c8
  43 #define BROADCOM_DEV_ID_57302 0x16c9
  44 #define BROADCOM_DEV_ID_57304_PF 0x16ca
  45 #define BROADCOM_DEV_ID_57304_VF 0x16cb
  46 #define BROADCOM_DEV_ID_57417_MF 0x16cc
  47 #define BROADCOM_DEV_ID_NS2 0x16cd
  48 #define BROADCOM_DEV_ID_57311 0x16ce
  49 #define BROADCOM_DEV_ID_57312 0x16cf
  50 #define BROADCOM_DEV_ID_57402 0x16d0
  51 #define BROADCOM_DEV_ID_57404 0x16d1
  52 #define BROADCOM_DEV_ID_57406_PF 0x16d2
  53 #define BROADCOM_DEV_ID_57406_VF 0x16d3
  54 #define BROADCOM_DEV_ID_57402_MF 0x16d4
  55 #define BROADCOM_DEV_ID_57407_RJ45 0x16d5
  56 #define BROADCOM_DEV_ID_57412 0x16d6
  57 #define BROADCOM_DEV_ID_57414 0x16d7
  58 #define BROADCOM_DEV_ID_57416_RJ45 0x16d8
  59 #define BROADCOM_DEV_ID_57417_RJ45 0x16d9
  60 #define BROADCOM_DEV_ID_5741X_VF 0x16dc
  61 #define BROADCOM_DEV_ID_57412_MF 0x16de
  62 #define BROADCOM_DEV_ID_57314 0x16df
  63 #define BROADCOM_DEV_ID_57317_RJ45 0x16e0
  64 #define BROADCOM_DEV_ID_5731X_VF 0x16e1
  65 #define BROADCOM_DEV_ID_57417_SFP 0x16e2
  66 #define BROADCOM_DEV_ID_57416_SFP 0x16e3
  67 #define BROADCOM_DEV_ID_57317_SFP 0x16e4
  68 #define BROADCOM_DEV_ID_57404_MF 0x16e7
  69 #define BROADCOM_DEV_ID_57406_MF 0x16e8
  70 #define BROADCOM_DEV_ID_57407_SFP 0x16e9
  71 #define BROADCOM_DEV_ID_57407_MF 0x16ea
  72 #define BROADCOM_DEV_ID_57414_MF 0x16ec
  73 #define BROADCOM_DEV_ID_57416_MF 0x16ee
  74 #define BROADCOM_DEV_ID_57508 0x1750
  75 #define BROADCOM_DEV_ID_57504 0x1751
  76 #define BROADCOM_DEV_ID_57502 0x1752
  77 #define BROADCOM_DEV_ID_57500_VF1 0x1806
  78 #define BROADCOM_DEV_ID_57500_VF2 0x1807
  79 #define BROADCOM_DEV_ID_58802 0xd802
  80 #define BROADCOM_DEV_ID_58804 0xd804
  81 #define BROADCOM_DEV_ID_58808 0x16f0
  82 #define BROADCOM_DEV_ID_58802_VF 0xd800
  83
  84 static const struct rte_pci_id bnxt_pci_id_map[] = {
  85         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM,
  86                          BROADCOM_DEV_ID_STRATUS_NIC_VF1) },
  87         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM,
  88                          BROADCOM_DEV_ID_STRATUS_NIC_VF2) },
  89         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_STRATUS_NIC) },
  90         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414_VF) },
  91         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57301) },
  92         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57302) },
  93         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57304_PF) },
  94         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57304_VF) },
  95         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_NS2) },
  96         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57402) },
  97         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57404) },
  98         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57406_PF) },
  99         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57406_VF) },
 100         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57402_MF) },
 101         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57407_RJ45) },
 102         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57404_MF) },
 103         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57406_MF) },
 104         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57407_SFP) },
 105         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57407_MF) },
 106         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_5741X_VF) },
 107         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_5731X_VF) },
 108         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57314) },
 109         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_MF) },
 110         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57311) },
 111         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57312) },
 112         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57412) },
 113         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414) },
 114         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_RJ45) },
 115         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_RJ45) },
 116         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57412_MF) },
 117         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57317_RJ45) },
 118         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_SFP) },
 119         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_SFP) },
 120         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57317_SFP) },
 121         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414_MF) },
 122         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_MF) },
 123         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58802) },
 124         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58804) },
 125         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58808) },
 126         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58802_VF) },
 127         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57508) },
 128         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57504) },
 129         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57502) },
 130         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57500_VF1) },
 131         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57500_VF2) },
 132         { .vendor_id = 0, /* sentinel */ },
 133 };
 134
 135 #define BNXT_ETH_RSS_SUPPORT (  \
 136         ETH_RSS_IPV4 |          \
 137         ETH_RSS_NONFRAG_IPV4_TCP |      \
 138         ETH_RSS_NONFRAG_IPV4_UDP |      \
 139         ETH_RSS_IPV6 |          \
 140         ETH_RSS_NONFRAG_IPV6_TCP |      \
 141         ETH_RSS_NONFRAG_IPV6_UDP)
 142
 143 #define BNXT_DEV_TX_OFFLOAD_SUPPORT (DEV_TX_OFFLOAD_VLAN_INSERT | \
 144                                      DEV_TX_OFFLOAD_IPV4_CKSUM | \
 145                                      DEV_TX_OFFLOAD_TCP_CKSUM | \
 146                                      DEV_TX_OFFLOAD_UDP_CKSUM | \
 147                                      DEV_TX_OFFLOAD_TCP_TSO | \
 148                                      DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM | \
 149                                      DEV_TX_OFFLOAD_VXLAN_TNL_TSO | \
 150                                      DEV_TX_OFFLOAD_GRE_TNL_TSO | \
 151                                      DEV_TX_OFFLOAD_IPIP_TNL_TSO | \
 152                                      DEV_TX_OFFLOAD_GENEVE_TNL_TSO | \
 153                                      DEV_TX_OFFLOAD_MULTI_SEGS)
 154
 155 #define BNXT_DEV_RX_OFFLOAD_SUPPORT (DEV_RX_OFFLOAD_VLAN_FILTER | \
 156                                      DEV_RX_OFFLOAD_VLAN_STRIP | \
 157                                      DEV_RX_OFFLOAD_IPV4_CKSUM | \
 158                                      DEV_RX_OFFLOAD_UDP_CKSUM | \
 159                                      DEV_RX_OFFLOAD_TCP_CKSUM | \
 160                                      DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM | \
 161                                      DEV_RX_OFFLOAD_JUMBO_FRAME | \
 162                                      DEV_RX_OFFLOAD_KEEP_CRC | \
 163                                      DEV_RX_OFFLOAD_TCP_LRO)
 164
 165 static int bnxt_vlan_offload_set_op(struct rte_eth_dev *dev, int mask);
 166 static void bnxt_print_link_info(struct rte_eth_dev *eth_dev);
 167 static int bnxt_mtu_set_op(struct rte_eth_dev *eth_dev, uint16_t new_mtu);
 168 static int bnxt_dev_uninit(struct rte_eth_dev *eth_dev);
 169
 170 /***********************/
 171
 172 /*
 173  * High level utility functions
 174  */
 175
 176 static uint16_t bnxt_rss_ctxts(const struct bnxt *bp)
 177 {
 178         if (!BNXT_CHIP_THOR(bp))
 179                 return 1;
 180
 181         return RTE_ALIGN_MUL_CEIL(bp->rx_nr_rings,
 182                                   BNXT_RSS_ENTRIES_PER_CTX_THOR) /
 183                                     BNXT_RSS_ENTRIES_PER_CTX_THOR;
 184 }
 185
 186 static uint16_t  bnxt_rss_hash_tbl_size(const struct bnxt *bp)
 187 {
 188         if (!BNXT_CHIP_THOR(bp))
 189                 return HW_HASH_INDEX_SIZE;
 190
 191         return bnxt_rss_ctxts(bp) * BNXT_RSS_ENTRIES_PER_CTX_THOR;
 192 }
 193
 194 static void bnxt_free_mem(struct bnxt *bp)
 195 {
 196         bnxt_free_filter_mem(bp);
 197         bnxt_free_vnic_attributes(bp);
 198         bnxt_free_vnic_mem(bp);
 199
 200         bnxt_free_stats(bp);
 201         bnxt_free_tx_rings(bp);
 202         bnxt_free_rx_rings(bp);
 203         bnxt_free_async_cp_ring(bp);
 204 }
 205
 206 static int bnxt_alloc_mem(struct bnxt *bp)
 207 {
 208         int rc;
 209
 210         rc = bnxt_alloc_async_ring_struct(bp);
 211         if (rc)
 212                 goto alloc_mem_err;
 213
 214         rc = bnxt_alloc_vnic_mem(bp);
 215         if (rc)
 216                 goto alloc_mem_err;
 217
 218         rc = bnxt_alloc_vnic_attributes(bp);
 219         if (rc)
 220                 goto alloc_mem_err;
 221
 222         rc = bnxt_alloc_filter_mem(bp);
 223         if (rc)
 224                 goto alloc_mem_err;
 225
 226         rc = bnxt_alloc_async_cp_ring(bp);
 227         if (rc)
 228                 goto alloc_mem_err;
 229
 230         return 0;
 231
 232 alloc_mem_err:
 233         bnxt_free_mem(bp);
 234         return rc;
 235 }
 236
 237 static int bnxt_init_chip(struct bnxt *bp)
 238 {
 239         struct bnxt_rx_queue *rxq;
 240         struct rte_eth_link new;
 241         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(bp->eth_dev);
 242         struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
 243         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
 244         uint64_t rx_offloads = dev_conf->rxmode.offloads;
 245         uint32_t intr_vector = 0;
 246         uint32_t queue_id, base = BNXT_MISC_VEC_ID;
 247         uint32_t vec = BNXT_MISC_VEC_ID;
 248         unsigned int i, j;
 249         int rc;
 250
 251         if (bp->eth_dev->data->mtu > RTE_ETHER_MTU) {
 252                 bp->eth_dev->data->dev_conf.rxmode.offloads |=
 253                         DEV_RX_OFFLOAD_JUMBO_FRAME;
 254                 bp->flags |= BNXT_FLAG_JUMBO;
 255         } else {
 256                 bp->eth_dev->data->dev_conf.rxmode.offloads &=
 257                         ~DEV_RX_OFFLOAD_JUMBO_FRAME;
 258                 bp->flags &= ~BNXT_FLAG_JUMBO;
 259         }
 260
 261         /* THOR does not support ring groups.
 262          * But we will use the array to save RSS context IDs.
 263          */
 264         if (BNXT_CHIP_THOR(bp))
 265                 bp->max_ring_grps = BNXT_MAX_RSS_CTXTS_THOR;
 266
 267         rc = bnxt_alloc_all_hwrm_stat_ctxs(bp);
 268         if (rc) {
 269                 PMD_DRV_LOG(ERR, "HWRM stat ctx alloc failure rc: %x\n", rc);
 270                 goto err_out;
 271         }
 272
 273         rc = bnxt_alloc_hwrm_rings(bp);
 274         if (rc) {
 275                 PMD_DRV_LOG(ERR, "HWRM ring alloc failure rc: %x\n", rc);
 276                 goto err_out;
 277         }
 278
 279         rc = bnxt_alloc_all_hwrm_ring_grps(bp);
 280         if (rc) {
 281                 PMD_DRV_LOG(ERR, "HWRM ring grp alloc failure: %x\n", rc);
 282                 goto err_out;
 283         }
 284
 285         rc = bnxt_mq_rx_configure(bp);
 286         if (rc) {
 287                 PMD_DRV_LOG(ERR, "MQ mode configure failure rc: %x\n", rc);
 288                 goto err_out;
 289         }
 290
 291         /* VNIC configuration */
 292         for (i = 0; i < bp->nr_vnics; i++) {
 293                 struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
 294                 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
 295                 uint32_t size = sizeof(*vnic->fw_grp_ids) * bp->max_ring_grps;
 296
 297                 vnic->fw_grp_ids = rte_zmalloc("vnic_fw_grp_ids", size, 0);
 298                 if (!vnic->fw_grp_ids) {
 299                         PMD_DRV_LOG(ERR,
 300                                     "Failed to alloc %d bytes for group ids\n",
 301                                     size);
 302                         rc = -ENOMEM;
 303                         goto err_out;
 304                 }
 305                 memset(vnic->fw_grp_ids, -1, size);
 306
 307                 PMD_DRV_LOG(DEBUG, "vnic[%d] = %p vnic->fw_grp_ids = %p\n",
 308                             i, vnic, vnic->fw_grp_ids);
 309
 310                 rc = bnxt_hwrm_vnic_alloc(bp, vnic);
 311                 if (rc) {
 312                         PMD_DRV_LOG(ERR, "HWRM vnic %d alloc failure rc: %x\n",
 313                                 i, rc);
 314                         goto err_out;
 315                 }
 316
 317                 /* Alloc RSS context only if RSS mode is enabled */
 318                 if (dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS) {
 319                         int j, nr_ctxs = bnxt_rss_ctxts(bp);
 320
 321                         rc = 0;
 322                         for (j = 0; j < nr_ctxs; j++) {
 323                                 rc = bnxt_hwrm_vnic_ctx_alloc(bp, vnic, j);
 324                                 if (rc)
 325                                         break;
 326                         }
 327                         if (rc) {
 328                                 PMD_DRV_LOG(ERR,
 329                                   "HWRM vnic %d ctx %d alloc failure rc: %x\n",
 330                                   i, j, rc);
 331                                 goto err_out;
 332                         }
 333                         vnic->num_lb_ctxts = nr_ctxs;
 334                 }
 335
 336                 /*
 337                  * Firmware sets pf pair in default vnic cfg. If the VLAN strip
 338                  * setting is not available at this time, it will not be
 339                  * configured correctly in the CFA.
 340                  */
 341                 if (rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
 342                         vnic->vlan_strip = true;
 343                 else
 344                         vnic->vlan_strip = false;
 345
 346                 rc = bnxt_hwrm_vnic_cfg(bp, vnic);
 347                 if (rc) {
 348                         PMD_DRV_LOG(ERR, "HWRM vnic %d cfg failure rc: %x\n",
 349                                 i, rc);
 350                         goto err_out;
 351                 }
 352
 353                 rc = bnxt_set_hwrm_vnic_filters(bp, vnic);
 354                 if (rc) {
 355                         PMD_DRV_LOG(ERR,
 356                                 "HWRM vnic %d filter failure rc: %x\n",
 357                                 i, rc);
 358                         goto err_out;
 359                 }
 360
 361                 for (j = 0; j < bp->rx_nr_rings; j++) {
 362                         rxq = bp->eth_dev->data->rx_queues[j];
 363
 364                         PMD_DRV_LOG(DEBUG,
 365                                     "rxq[%d]->vnic=%p vnic->fw_grp_ids=%p\n",
 366                                     j, rxq->vnic, rxq->vnic->fw_grp_ids);
 367
 368                         if (BNXT_HAS_RING_GRPS(bp) && rxq->rx_deferred_start)
 369                                 rxq->vnic->fw_grp_ids[j] = INVALID_HW_RING_ID;
 370                 }
 371
 372                 rc = bnxt_vnic_rss_configure(bp, vnic);
 373                 if (rc) {
 374                         PMD_DRV_LOG(ERR,
 375                                     "HWRM vnic set RSS failure rc: %x\n", rc);
 376                         goto err_out;
 377                 }
 378
 379                 bnxt_hwrm_vnic_plcmode_cfg(bp, vnic);
 380
 381                 if (bp->eth_dev->data->dev_conf.rxmode.offloads &
 382                     DEV_RX_OFFLOAD_TCP_LRO)
 383                         bnxt_hwrm_vnic_tpa_cfg(bp, vnic, 1);
 384                 else
 385                         bnxt_hwrm_vnic_tpa_cfg(bp, vnic, 0);
 386         }
 387         rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, &bp->vnic_info[0], 0, NULL);
 388         if (rc) {
 389                 PMD_DRV_LOG(ERR,
 390                         "HWRM cfa l2 rx mask failure rc: %x\n", rc);
 391                 goto err_out;
 392         }
 393
 394         /* check and configure queue intr-vector mapping */
 395         if ((rte_intr_cap_multiple(intr_handle) ||
 396              !RTE_ETH_DEV_SRIOV(bp->eth_dev).active) &&
 397             bp->eth_dev->data->dev_conf.intr_conf.rxq != 0) {
 398                 intr_vector = bp->eth_dev->data->nb_rx_queues;
 399                 PMD_DRV_LOG(DEBUG, "intr_vector = %d\n", intr_vector);
 400                 if (intr_vector > bp->rx_cp_nr_rings) {
 401                         PMD_DRV_LOG(ERR, "At most %d intr queues supported",
 402                                         bp->rx_cp_nr_rings);
 403                         return -ENOTSUP;
 404                 }
 405                 rc = rte_intr_efd_enable(intr_handle, intr_vector);
 406                 if (rc)
 407                         return rc;
 408         }
 409
 410         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
 411                 intr_handle->intr_vec =
 412                         rte_zmalloc("intr_vec",
 413                                     bp->eth_dev->data->nb_rx_queues *
 414                                     sizeof(int), 0);
 415                 if (intr_handle->intr_vec == NULL) {
 416                         PMD_DRV_LOG(ERR, "Failed to allocate %d rx_queues"
 417                                 " intr_vec", bp->eth_dev->data->nb_rx_queues);
 418                         rc = -ENOMEM;
 419                         goto err_disable;
 420                 }
 421                 PMD_DRV_LOG(DEBUG, "intr_handle->intr_vec = %p "
 422                         "intr_handle->nb_efd = %d intr_handle->max_intr = %d\n",
 423                          intr_handle->intr_vec, intr_handle->nb_efd,
 424                         intr_handle->max_intr);
 425                 for (queue_id = 0; queue_id < bp->eth_dev->data->nb_rx_queues;
 426                      queue_id++) {
 427                         intr_handle->intr_vec[queue_id] =
 428                                                         vec + BNXT_RX_VEC_START;
 429                         if (vec < base + intr_handle->nb_efd - 1)
 430                                 vec++;
 431                 }
 432         }
 433
 434         /* enable uio/vfio intr/eventfd mapping */
 435         rc = rte_intr_enable(intr_handle);
 436         if (rc)
 437                 goto err_free;
 438
 439         rc = bnxt_get_hwrm_link_config(bp, &new);
 440         if (rc) {
 441                 PMD_DRV_LOG(ERR, "HWRM Get link config failure rc: %x\n", rc);
 442                 goto err_free;
 443         }
 444
 445         if (!bp->link_info.link_up) {
 446                 rc = bnxt_set_hwrm_link_config(bp, true);
 447                 if (rc) {
 448                         PMD_DRV_LOG(ERR,
 449                                 "HWRM link config failure rc: %x\n", rc);
 450                         goto err_free;
 451                 }
 452         }
 453         bnxt_print_link_info(bp->eth_dev);
 454
 455         return 0;
 456
 457 err_free:
 458         rte_free(intr_handle->intr_vec);
 459 err_disable:
 460         rte_intr_efd_disable(intr_handle);
 461 err_out:
 462         /* Some of the error status returned by FW may not be from errno.h */
 463         if (rc > 0)
 464                 rc = -EIO;
 465
 466         return rc;
 467 }
 468
 469 static int bnxt_shutdown_nic(struct bnxt *bp)
 470 {
 471         bnxt_free_all_hwrm_resources(bp);
 472         bnxt_free_all_filters(bp);
 473         bnxt_free_all_vnics(bp);
 474         return 0;
 475 }
 476
 477 static int bnxt_init_nic(struct bnxt *bp)
 478 {
 479         int rc;
 480
 481         if (BNXT_HAS_RING_GRPS(bp)) {
 482                 rc = bnxt_init_ring_grps(bp);
 483                 if (rc)
 484                         return rc;
 485         }
 486
 487         bnxt_init_vnics(bp);
 488         bnxt_init_filters(bp);
 489
 490         return 0;
 491 }
 492
 493 /*
 494  * Device configuration and status function
 495  */
 496
 497 static int bnxt_dev_info_get_op(struct rte_eth_dev *eth_dev,
 498                                 struct rte_eth_dev_info *dev_info)
 499 {
 500         struct bnxt *bp = eth_dev->data->dev_private;
 501         uint16_t max_vnics, i, j, vpool, vrxq;
 502         unsigned int max_rx_rings;
 503
 504         /* MAC Specifics */
 505         dev_info->max_mac_addrs = bp->max_l2_ctx;
 506         dev_info->max_hash_mac_addrs = 0;
 507
 508         /* PF/VF specifics */
 509         if (BNXT_PF(bp))
 510                 dev_info->max_vfs = bp->pdev->max_vfs;
 511         max_rx_rings = RTE_MIN(bp->max_rx_rings, bp->max_stat_ctx);
 512         /* For the sake of symmetry, max_rx_queues = max_tx_queues */
 513         dev_info->max_rx_queues = max_rx_rings;
 514         dev_info->max_tx_queues = max_rx_rings;
 515         dev_info->reta_size = bnxt_rss_hash_tbl_size(bp);
 516         dev_info->hash_key_size = 40;
 517         max_vnics = bp->max_vnics;
 518
 519         /* Fast path specifics */
 520         dev_info->min_rx_bufsize = 1;
 521         dev_info->max_rx_pktlen = BNXT_MAX_MTU + RTE_ETHER_HDR_LEN +
 522                 RTE_ETHER_CRC_LEN + VLAN_TAG_SIZE * 2;
 523
 524         dev_info->rx_offload_capa = BNXT_DEV_RX_OFFLOAD_SUPPORT;
 525         if (bp->flags & BNXT_FLAG_PTP_SUPPORTED)
 526                 dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_TIMESTAMP;
 527         dev_info->tx_offload_capa = BNXT_DEV_TX_OFFLOAD_SUPPORT;
 528         dev_info->flow_type_rss_offloads = BNXT_ETH_RSS_SUPPORT;
 529
 530         /* *INDENT-OFF* */
 531         dev_info->default_rxconf = (struct rte_eth_rxconf) {
 532                 .rx_thresh = {
 533                         .pthresh = 8,
 534                         .hthresh = 8,
 535                         .wthresh = 0,
 536                 },
 537                 .rx_free_thresh = 32,
 538                 /* If no descriptors available, pkts are dropped by default */
 539                 .rx_drop_en = 1,
 540         };
 541
 542         dev_info->default_txconf = (struct rte_eth_txconf) {
 543                 .tx_thresh = {
 544                         .pthresh = 32,
 545                         .hthresh = 0,
 546                         .wthresh = 0,
 547                 },
 548                 .tx_free_thresh = 32,
 549                 .tx_rs_thresh = 32,
 550         };
 551         eth_dev->data->dev_conf.intr_conf.lsc = 1;
 552
 553         eth_dev->data->dev_conf.intr_conf.rxq = 1;
 554         dev_info->rx_desc_lim.nb_min = BNXT_MIN_RING_DESC;
 555         dev_info->rx_desc_lim.nb_max = BNXT_MAX_RX_RING_DESC;
 556         dev_info->tx_desc_lim.nb_min = BNXT_MIN_RING_DESC;
 557         dev_info->tx_desc_lim.nb_max = BNXT_MAX_TX_RING_DESC;
 558
 559         /* *INDENT-ON* */
 560
 561         /*
 562          * TODO: default_rxconf, default_txconf, rx_desc_lim, and tx_desc_lim
 563          *       need further investigation.
 564          */
 565
 566         /* VMDq resources */
 567         vpool = 64; /* ETH_64_POOLS */
 568         vrxq = 128; /* ETH_VMDQ_DCB_NUM_QUEUES */
 569         for (i = 0; i < 4; vpool >>= 1, i++) {
 570                 if (max_vnics > vpool) {
 571                         for (j = 0; j < 5; vrxq >>= 1, j++) {
 572                                 if (dev_info->max_rx_queues > vrxq) {
 573                                         if (vpool > vrxq)
 574                                                 vpool = vrxq;
 575                                         goto found;
 576                                 }
 577                         }
 578                         /* Not enough resources to support VMDq */
 579                         break;
 580                 }
 581         }
 582         /* Not enough resources to support VMDq */
 583         vpool = 0;
 584         vrxq = 0;
 585 found:
 586         dev_info->max_vmdq_pools = vpool;
 587         dev_info->vmdq_queue_num = vrxq;
 588
 589         dev_info->vmdq_pool_base = 0;
 590         dev_info->vmdq_queue_base = 0;
 591
 592         return 0;
 593 }
 594
 595 /* Configure the device based on the configuration provided */
 596 static int bnxt_dev_configure_op(struct rte_eth_dev *eth_dev)
 597 {
 598         struct bnxt *bp = eth_dev->data->dev_private;
 599         uint64_t rx_offloads = eth_dev->data->dev_conf.rxmode.offloads;
 600         int rc;
 601
 602         bp->rx_queues = (void *)eth_dev->data->rx_queues;
 603         bp->tx_queues = (void *)eth_dev->data->tx_queues;
 604         bp->tx_nr_rings = eth_dev->data->nb_tx_queues;
 605         bp->rx_nr_rings = eth_dev->data->nb_rx_queues;
 606
 607         if (BNXT_VF(bp) && (bp->flags & BNXT_FLAG_NEW_RM)) {
 608                 rc = bnxt_hwrm_check_vf_rings(bp);
 609                 if (rc) {
 610                         PMD_DRV_LOG(ERR, "HWRM insufficient resources\n");
 611                         return -ENOSPC;
 612                 }
 613
 614                 rc = bnxt_hwrm_func_reserve_vf_resc(bp, false);
 615                 if (rc) {
 616                         PMD_DRV_LOG(ERR, "HWRM resource alloc fail:%x\n", rc);
 617                         return -ENOSPC;
 618                 }
 619         } else {
 620                 /* legacy driver needs to get updated values */
 621                 rc = bnxt_hwrm_func_qcaps(bp);
 622                 if (rc) {
 623                         PMD_DRV_LOG(ERR, "hwrm func qcaps fail:%d\n", rc);
 624                         return rc;
 625                 }
 626         }
 627
 628         /* Inherit new configurations */
 629         if (eth_dev->data->nb_rx_queues > bp->max_rx_rings ||
 630             eth_dev->data->nb_tx_queues > bp->max_tx_rings ||
 631             eth_dev->data->nb_rx_queues + eth_dev->data->nb_tx_queues
 632                 + BNXT_NUM_ASYNC_CPR(bp) > bp->max_cp_rings ||
 633             eth_dev->data->nb_rx_queues + eth_dev->data->nb_tx_queues >
 634             bp->max_stat_ctx)
 635                 goto resource_error;
 636
 637         if (BNXT_HAS_RING_GRPS(bp) &&
 638             (uint32_t)(eth_dev->data->nb_rx_queues) > bp->max_ring_grps)
 639                 goto resource_error;
 640
 641         if (!(eth_dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_RSS) &&
 642             bp->max_vnics < eth_dev->data->nb_rx_queues)
 643                 goto resource_error;
 644
 645         bp->rx_cp_nr_rings = bp->rx_nr_rings;
 646         bp->tx_cp_nr_rings = bp->tx_nr_rings;
 647
 648         if (rx_offloads & DEV_RX_OFFLOAD_JUMBO_FRAME) {
 649                 eth_dev->data->mtu =
 650                         eth_dev->data->dev_conf.rxmode.max_rx_pkt_len -
 651                         RTE_ETHER_HDR_LEN - RTE_ETHER_CRC_LEN - VLAN_TAG_SIZE *
 652                         BNXT_NUM_VLANS;
 653                 bnxt_mtu_set_op(eth_dev, eth_dev->data->mtu);
 654         }
 655         return 0;
 656
 657 resource_error:
 658         PMD_DRV_LOG(ERR,
 659                     "Insufficient resources to support requested config\n");
 660         PMD_DRV_LOG(ERR,
 661                     "Num Queues Requested: Tx %d, Rx %d\n",
 662                     eth_dev->data->nb_tx_queues,
 663                     eth_dev->data->nb_rx_queues);
 664         PMD_DRV_LOG(ERR,
 665                     "MAX: TxQ %d, RxQ %d, CQ %d Stat %d, Grp %d, Vnic %d\n",
 666                     bp->max_tx_rings, bp->max_rx_rings, bp->max_cp_rings,
 667                     bp->max_stat_ctx, bp->max_ring_grps, bp->max_vnics);
 668         return -ENOSPC;
 669 }
 670
 671 static void bnxt_print_link_info(struct rte_eth_dev *eth_dev)
 672 {
 673         struct rte_eth_link *link = &eth_dev->data->dev_link;
 674
 675         if (link->link_status)
 676                 PMD_DRV_LOG(INFO, "Port %d Link Up - speed %u Mbps - %s\n",
 677                         eth_dev->data->port_id,
 678                         (uint32_t)link->link_speed,
 679                         (link->link_duplex == ETH_LINK_FULL_DUPLEX) ?
 680                         ("full-duplex") : ("half-duplex\n"));
 681         else
 682                 PMD_DRV_LOG(INFO, "Port %d Link Down\n",
 683                         eth_dev->data->port_id);
 684 }
 685
 686 /*
 687  * Determine whether the current configuration requires support for scattered
 688  * receive; return 1 if scattered receive is required and 0 if not.
 689  */
 690 static int bnxt_scattered_rx(struct rte_eth_dev *eth_dev)
 691 {
 692         uint16_t buf_size;
 693         int i;
 694
 695         for (i = 0; i < eth_dev->data->nb_rx_queues; i++) {
 696                 struct bnxt_rx_queue *rxq = eth_dev->data->rx_queues[i];
 697
 698                 buf_size = (uint16_t)(rte_pktmbuf_data_room_size(rxq->mb_pool) -
 699                                       RTE_PKTMBUF_HEADROOM);
 700                 if (eth_dev->data->dev_conf.rxmode.max_rx_pkt_len > buf_size)
 701                         return 1;
 702         }
 703         return 0;
 704 }
 705
 706 static eth_rx_burst_t
 707 bnxt_receive_function(__rte_unused struct rte_eth_dev *eth_dev)
 708 {
 709 #ifdef RTE_ARCH_X86
 710         /*
 711          * Vector mode receive can be enabled only if scatter rx is not
 712          * in use and rx offloads are limited to VLAN stripping and
 713          * CRC stripping.
 714          */
 715         if (!eth_dev->data->scattered_rx &&
 716             !(eth_dev->data->dev_conf.rxmode.offloads &
 717               ~(DEV_RX_OFFLOAD_VLAN_STRIP |
 718                 DEV_RX_OFFLOAD_KEEP_CRC |
 719                 DEV_RX_OFFLOAD_JUMBO_FRAME |
 720                 DEV_RX_OFFLOAD_IPV4_CKSUM |
 721                 DEV_RX_OFFLOAD_UDP_CKSUM |
 722                 DEV_RX_OFFLOAD_TCP_CKSUM |
 723                 DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM |
 724                 DEV_RX_OFFLOAD_VLAN_FILTER))) {
 725                 PMD_DRV_LOG(INFO, "Using vector mode receive for port %d\n",
 726                             eth_dev->data->port_id);
 727                 return bnxt_recv_pkts_vec;
 728         }
 729         PMD_DRV_LOG(INFO, "Vector mode receive disabled for port %d\n",
 730                     eth_dev->data->port_id);
 731         PMD_DRV_LOG(INFO,
 732                     "Port %d scatter: %d rx offload: %" PRIX64 "\n",
 733                     eth_dev->data->port_id,
 734                     eth_dev->data->scattered_rx,
 735                     eth_dev->data->dev_conf.rxmode.offloads);
 736 #endif
 737         return bnxt_recv_pkts;
 738 }
 739
 740 static eth_tx_burst_t
 741 bnxt_transmit_function(__rte_unused struct rte_eth_dev *eth_dev)
 742 {
 743 #ifdef RTE_ARCH_X86
 744         /*
 745          * Vector mode transmit can be enabled only if not using scatter rx
 746          * or tx offloads.
 747          */
 748         if (!eth_dev->data->scattered_rx &&
 749             !eth_dev->data->dev_conf.txmode.offloads) {
 750                 PMD_DRV_LOG(INFO, "Using vector mode transmit for port %d\n",
 751                             eth_dev->data->port_id);
 752                 return bnxt_xmit_pkts_vec;
 753         }
 754         PMD_DRV_LOG(INFO, "Vector mode transmit disabled for port %d\n",
 755                     eth_dev->data->port_id);
 756         PMD_DRV_LOG(INFO,
 757                     "Port %d scatter: %d tx offload: %" PRIX64 "\n",
 758                     eth_dev->data->port_id,
 759                     eth_dev->data->scattered_rx,
 760                     eth_dev->data->dev_conf.txmode.offloads);
 761 #endif
 762         return bnxt_xmit_pkts;
 763 }
 764
 765 static int bnxt_dev_start_op(struct rte_eth_dev *eth_dev)
 766 {
 767         struct bnxt *bp = eth_dev->data->dev_private;
 768         uint64_t rx_offloads = eth_dev->data->dev_conf.rxmode.offloads;
 769         int vlan_mask = 0;
 770         int rc;
 771
 772         if (bp->rx_cp_nr_rings > RTE_ETHDEV_QUEUE_STAT_CNTRS) {
 773                 PMD_DRV_LOG(ERR,
 774                         "RxQ cnt %d > CONFIG_RTE_ETHDEV_QUEUE_STAT_CNTRS %d\n",
 775                         bp->rx_cp_nr_rings, RTE_ETHDEV_QUEUE_STAT_CNTRS);
 776         }
 777
 778         rc = bnxt_init_chip(bp);
 779         if (rc)
 780                 goto error;
 781
 782         eth_dev->data->scattered_rx = bnxt_scattered_rx(eth_dev);
 783
 784         bnxt_link_update_op(eth_dev, 1);
 785
 786         if (rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER)
 787                 vlan_mask |= ETH_VLAN_FILTER_MASK;
 788         if (rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
 789                 vlan_mask |= ETH_VLAN_STRIP_MASK;
 790         rc = bnxt_vlan_offload_set_op(eth_dev, vlan_mask);
 791         if (rc)
 792                 goto error;
 793
 794         eth_dev->rx_pkt_burst = bnxt_receive_function(eth_dev);
 795         eth_dev->tx_pkt_burst = bnxt_transmit_function(eth_dev);
 796         bnxt_enable_int(bp);
 797         bp->flags |= BNXT_FLAG_INIT_DONE;
 798         bp->dev_stopped = 0;
 799         return 0;
 800
 801 error:
 802         bnxt_shutdown_nic(bp);
 803         bnxt_free_tx_mbufs(bp);
 804         bnxt_free_rx_mbufs(bp);
 805         return rc;
 806 }
 807
 808 static int bnxt_dev_set_link_up_op(struct rte_eth_dev *eth_dev)
 809 {
 810         struct bnxt *bp = eth_dev->data->dev_private;
 811         int rc = 0;
 812
 813         if (!bp->link_info.link_up)
 814                 rc = bnxt_set_hwrm_link_config(bp, true);
 815         if (!rc)
 816                 eth_dev->data->dev_link.link_status = 1;
 817
 818         bnxt_print_link_info(eth_dev);
 819         return 0;
 820 }
 821
 822 static int bnxt_dev_set_link_down_op(struct rte_eth_dev *eth_dev)
 823 {
 824         struct bnxt *bp = eth_dev->data->dev_private;
 825
 826         eth_dev->data->dev_link.link_status = 0;
 827         bnxt_set_hwrm_link_config(bp, false);
 828         bp->link_info.link_up = 0;
 829
 830         return 0;
 831 }
 832
 833 /* Unload the driver, release resources */
 834 static void bnxt_dev_stop_op(struct rte_eth_dev *eth_dev)
 835 {
 836         struct bnxt *bp = eth_dev->data->dev_private;
 837         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
 838         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
 839
 840         bnxt_disable_int(bp);
 841
 842         /* disable uio/vfio intr/eventfd mapping */
 843         rte_intr_disable(intr_handle);
 844
 845         bp->flags &= ~BNXT_FLAG_INIT_DONE;
 846         if (bp->eth_dev->data->dev_started) {
 847                 /* TBD: STOP HW queues DMA */
 848                 eth_dev->data->dev_link.link_status = 0;
 849         }
 850         bnxt_set_hwrm_link_config(bp, false);
 851
 852         /* Clean queue intr-vector mapping */
 853         rte_intr_efd_disable(intr_handle);
 854         if (intr_handle->intr_vec != NULL) {
 855                 rte_free(intr_handle->intr_vec);
 856                 intr_handle->intr_vec = NULL;
 857         }
 858
 859         bnxt_hwrm_port_clr_stats(bp);
 860         bnxt_free_tx_mbufs(bp);
 861         bnxt_free_rx_mbufs(bp);
 862         bnxt_shutdown_nic(bp);
 863         bp->dev_stopped = 1;
 864 }
 865
 866 static void bnxt_dev_close_op(struct rte_eth_dev *eth_dev)
 867 {
 868         struct bnxt *bp = eth_dev->data->dev_private;
 869
 870         if (bp->dev_stopped == 0)
 871                 bnxt_dev_stop_op(eth_dev);
 872
 873         if (eth_dev->data->mac_addrs != NULL) {
 874                 rte_free(eth_dev->data->mac_addrs);
 875                 eth_dev->data->mac_addrs = NULL;
 876         }
 877         if (bp->grp_info != NULL) {
 878                 rte_free(bp->grp_info);
 879                 bp->grp_info = NULL;
 880         }
 881
 882         bnxt_dev_uninit(eth_dev);
 883 }
 884
 885 static void bnxt_mac_addr_remove_op(struct rte_eth_dev *eth_dev,
 886                                     uint32_t index)
 887 {
 888         struct bnxt *bp = eth_dev->data->dev_private;
 889         uint64_t pool_mask = eth_dev->data->mac_pool_sel[index];
 890         struct bnxt_vnic_info *vnic;
 891         struct bnxt_filter_info *filter, *temp_filter;
 892         uint32_t i;
 893
 894         /*
 895          * Loop through all VNICs from the specified filter flow pools to
 896          * remove the corresponding MAC addr filter
 897          */
 898         for (i = 0; i < bp->nr_vnics; i++) {
 899                 if (!(pool_mask & (1ULL << i)))
 900                         continue;
 901
 902                 vnic = &bp->vnic_info[i];
 903                 filter = STAILQ_FIRST(&vnic->filter);
 904                 while (filter) {
 905                         temp_filter = STAILQ_NEXT(filter, next);
 906                         if (filter->mac_index == index) {
 907                                 STAILQ_REMOVE(&vnic->filter, filter,
 908                                                 bnxt_filter_info, next);
 909                                 bnxt_hwrm_clear_l2_filter(bp, filter);
 910                                 filter->mac_index = INVALID_MAC_INDEX;
 911                                 memset(&filter->l2_addr, 0, RTE_ETHER_ADDR_LEN);
 912                                 STAILQ_INSERT_TAIL(&bp->free_filter_list,
 913                                                    filter, next);
 914                         }
 915                         filter = temp_filter;
 916                 }
 917         }
 918 }
 919
 920 static int bnxt_mac_addr_add_op(struct rte_eth_dev *eth_dev,
 921                                 struct rte_ether_addr *mac_addr,
 922                                 uint32_t index, uint32_t pool)
 923 {
 924         struct bnxt *bp = eth_dev->data->dev_private;
 925         struct bnxt_vnic_info *vnic = &bp->vnic_info[pool];
 926         struct bnxt_filter_info *filter;
 927         int rc = 0;
 928
 929         if (BNXT_VF(bp) & !BNXT_VF_IS_TRUSTED(bp)) {
 930                 PMD_DRV_LOG(ERR, "Cannot add MAC address to a VF interface\n");
 931                 return -ENOTSUP;
 932         }
 933
 934         if (!vnic) {
 935                 PMD_DRV_LOG(ERR, "VNIC not found for pool %d!\n", pool);
 936                 return -EINVAL;
 937         }
 938         /* Attach requested MAC address to the new l2_filter */
 939         STAILQ_FOREACH(filter, &vnic->filter, next) {
 940                 if (filter->mac_index == index) {
 941                         PMD_DRV_LOG(ERR,
 942                                 "MAC addr already existed for pool %d\n", pool);
 943                         return 0;
 944                 }
 945         }
 946         filter = bnxt_alloc_filter(bp);
 947         if (!filter) {
 948                 PMD_DRV_LOG(ERR, "L2 filter alloc failed\n");
 949                 return -ENODEV;
 950         }
 951
 952         filter->mac_index = index;
 953         memcpy(filter->l2_addr, mac_addr, RTE_ETHER_ADDR_LEN);
 954
 955         rc = bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id, filter);
 956         if (!rc) {
 957                 STAILQ_INSERT_TAIL(&vnic->filter, filter, next);
 958         } else {
 959                 filter->mac_index = INVALID_MAC_INDEX;
 960                 memset(&filter->l2_addr, 0, RTE_ETHER_ADDR_LEN);
 961                 bnxt_free_filter(bp, filter);
 962         }
 963
 964         return rc;
 965 }
 966
 967 int bnxt_link_update_op(struct rte_eth_dev *eth_dev, int wait_to_complete)
 968 {
 969         int rc = 0;
 970         struct bnxt *bp = eth_dev->data->dev_private;
 971         struct rte_eth_link new;
 972         unsigned int cnt = BNXT_LINK_WAIT_CNT;
 973
 974         memset(&new, 0, sizeof(new));
 975         do {
 976                 /* Retrieve link info from hardware */
 977                 rc = bnxt_get_hwrm_link_config(bp, &new);
 978                 if (rc) {
 979                         new.link_speed = ETH_LINK_SPEED_100M;
 980                         new.link_duplex = ETH_LINK_FULL_DUPLEX;
 981                         PMD_DRV_LOG(ERR,
 982                                 "Failed to retrieve link rc = 0x%x!\n", rc);
 983                         goto out;
 984                 }
 985
 986                 if (!wait_to_complete || new.link_status)
 987                         break;
 988
 989                 rte_delay_ms(BNXT_LINK_WAIT_INTERVAL);
 990         } while (cnt--);
 991
 992 out:
 993         /* Timed out or success */
 994         if (new.link_status != eth_dev->data->dev_link.link_status ||
 995         new.link_speed != eth_dev->data->dev_link.link_speed) {
 996                 memcpy(&eth_dev->data->dev_link, &new,
 997                         sizeof(struct rte_eth_link));
 998
 999                 _rte_eth_dev_callback_process(eth_dev,
1000                                               RTE_ETH_EVENT_INTR_LSC,
1001                                               NULL);
1002
1003                 bnxt_print_link_info(eth_dev);
1004         }
1005
1006         return rc;
1007 }
1008
1009 static void bnxt_promiscuous_enable_op(struct rte_eth_dev *eth_dev)
1010 {
1011         struct bnxt *bp = eth_dev->data->dev_private;
1012         struct bnxt_vnic_info *vnic;
1013
1014         if (bp->vnic_info == NULL)
1015                 return;
1016
1017         vnic = &bp->vnic_info[0];
1018
1019         vnic->flags |= BNXT_VNIC_INFO_PROMISC;
1020         bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1021 }
1022
1023 static void bnxt_promiscuous_disable_op(struct rte_eth_dev *eth_dev)
1024 {
1025         struct bnxt *bp = eth_dev->data->dev_private;
1026         struct bnxt_vnic_info *vnic;
1027
1028         if (bp->vnic_info == NULL)
1029                 return;
1030
1031         vnic = &bp->vnic_info[0];
1032
1033         vnic->flags &= ~BNXT_VNIC_INFO_PROMISC;
1034         bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1035 }
1036
1037 static void bnxt_allmulticast_enable_op(struct rte_eth_dev *eth_dev)
1038 {
1039         struct bnxt *bp = eth_dev->data->dev_private;
1040         struct bnxt_vnic_info *vnic;
1041
1042         if (bp->vnic_info == NULL)
1043                 return;
1044
1045         vnic = &bp->vnic_info[0];
1046
1047         vnic->flags |= BNXT_VNIC_INFO_ALLMULTI;
1048         bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1049 }
1050
1051 static void bnxt_allmulticast_disable_op(struct rte_eth_dev *eth_dev)
1052 {
1053         struct bnxt *bp = eth_dev->data->dev_private;
1054         struct bnxt_vnic_info *vnic;
1055
1056         if (bp->vnic_info == NULL)
1057                 return;
1058
1059         vnic = &bp->vnic_info[0];
1060
1061         vnic->flags &= ~BNXT_VNIC_INFO_ALLMULTI;
1062         bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1063 }
1064
1065 /* Return bnxt_rx_queue pointer corresponding to a given rxq. */
1066 static struct bnxt_rx_queue *bnxt_qid_to_rxq(struct bnxt *bp, uint16_t qid)
1067 {
1068         if (qid >= bp->rx_nr_rings)
1069                 return NULL;
1070
1071         return bp->eth_dev->data->rx_queues[qid];
1072 }
1073
1074 /* Return rxq corresponding to a given rss table ring/group ID. */
1075 static uint16_t bnxt_rss_to_qid(struct bnxt *bp, uint16_t fwr)
1076 {
1077         struct bnxt_rx_queue *rxq;
1078         unsigned int i;
1079
1080         if (!BNXT_HAS_RING_GRPS(bp)) {
1081                 for (i = 0; i < bp->rx_nr_rings; i++) {
1082                         rxq = bp->eth_dev->data->rx_queues[i];
1083                         if (rxq->rx_ring->rx_ring_struct->fw_ring_id == fwr)
1084                                 return rxq->index;
1085                 }
1086         } else {
1087                 for (i = 0; i < bp->rx_nr_rings; i++) {
1088                         if (bp->grp_info[i].fw_grp_id == fwr)
1089                                 return i;
1090                 }
1091         }
1092
1093         return INVALID_HW_RING_ID;
1094 }
1095
1096 static int bnxt_reta_update_op(struct rte_eth_dev *eth_dev,
1097                             struct rte_eth_rss_reta_entry64 *reta_conf,
1098                             uint16_t reta_size)
1099 {
1100         struct bnxt *bp = eth_dev->data->dev_private;
1101         struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
1102         struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
1103         uint16_t tbl_size = bnxt_rss_hash_tbl_size(bp);
1104         uint16_t idx, sft;
1105         int i;
1106
1107         if (!vnic->rss_table)
1108                 return -EINVAL;
1109
1110         if (!(dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG))
1111                 return -EINVAL;
1112
1113         if (reta_size != tbl_size) {
1114                 PMD_DRV_LOG(ERR, "The configured hash table lookup size "
1115                         "(%d) must equal the size supported by the hardware "
1116                         "(%d)\n", reta_size, tbl_size);
1117                 return -EINVAL;
1118         }
1119
1120         for (i = 0; i < reta_size; i++) {
1121                 struct bnxt_rx_queue *rxq;
1122
1123                 idx = i / RTE_RETA_GROUP_SIZE;
1124                 sft = i % RTE_RETA_GROUP_SIZE;
1125
1126                 if (!(reta_conf[idx].mask & (1ULL << sft)))
1127                         continue;
1128
1129                 rxq = bnxt_qid_to_rxq(bp, reta_conf[idx].reta[sft]);
1130                 if (!rxq) {
1131                         PMD_DRV_LOG(ERR, "Invalid ring in reta_conf.\n");
1132                         return -EINVAL;
1133                 }
1134
1135                 if (BNXT_CHIP_THOR(bp)) {
1136                         vnic->rss_table[i * 2] =
1137                                 rxq->rx_ring->rx_ring_struct->fw_ring_id;
1138                         vnic->rss_table[i * 2 + 1] =
1139                                 rxq->cp_ring->cp_ring_struct->fw_ring_id;
1140                 } else {
1141                         vnic->rss_table[i] =
1142                             vnic->fw_grp_ids[reta_conf[idx].reta[sft]];
1143                 }
1144
1145                 vnic->rss_table[i] =
1146                     vnic->fw_grp_ids[reta_conf[idx].reta[sft]];
1147         }
1148
1149         bnxt_hwrm_vnic_rss_cfg(bp, vnic);
1150         return 0;
1151 }
1152
1153 static int bnxt_reta_query_op(struct rte_eth_dev *eth_dev,
1154                               struct rte_eth_rss_reta_entry64 *reta_conf,
1155                               uint16_t reta_size)
1156 {
1157         struct bnxt *bp = eth_dev->data->dev_private;
1158         struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
1159         uint16_t tbl_size = bnxt_rss_hash_tbl_size(bp);
1160         uint16_t idx, sft, i;
1161
1162         /* Retrieve from the default VNIC */
1163         if (!vnic)
1164                 return -EINVAL;
1165         if (!vnic->rss_table)
1166                 return -EINVAL;
1167
1168         if (reta_size != tbl_size) {
1169                 PMD_DRV_LOG(ERR, "The configured hash table lookup size "
1170                         "(%d) must equal the size supported by the hardware "
1171                         "(%d)\n", reta_size, tbl_size);
1172                 return -EINVAL;
1173         }
1174
1175         for (idx = 0, i = 0; i < reta_size; i++) {
1176                 idx = i / RTE_RETA_GROUP_SIZE;
1177                 sft = i % RTE_RETA_GROUP_SIZE;
1178
1179                 if (reta_conf[idx].mask & (1ULL << sft)) {
1180                         uint16_t qid;
1181
1182                         if (BNXT_CHIP_THOR(bp))
1183                                 qid = bnxt_rss_to_qid(bp,
1184                                                       vnic->rss_table[i * 2]);
1185                         else
1186                                 qid = bnxt_rss_to_qid(bp, vnic->rss_table[i]);
1187
1188                         if (qid == INVALID_HW_RING_ID) {
1189                                 PMD_DRV_LOG(ERR, "Inv. entry in rss table.\n");
1190                                 return -EINVAL;
1191                         }
1192                         reta_conf[idx].reta[sft] = qid;
1193                 }
1194         }
1195
1196         return 0;
1197 }
1198
1199 static int bnxt_rss_hash_update_op(struct rte_eth_dev *eth_dev,
1200                                    struct rte_eth_rss_conf *rss_conf)
1201 {
1202         struct bnxt *bp = eth_dev->data->dev_private;
1203         struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
1204         struct bnxt_vnic_info *vnic;
1205         uint16_t hash_type = 0;
1206         unsigned int i;
1207
1208         /*
1209          * If RSS enablement were different than dev_configure,
1210          * then return -EINVAL
1211          */
1212         if (dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG) {
1213                 if (!rss_conf->rss_hf)
1214                         PMD_DRV_LOG(ERR, "Hash type NONE\n");
1215         } else {
1216                 if (rss_conf->rss_hf & BNXT_ETH_RSS_SUPPORT)
1217                         return -EINVAL;
1218         }
1219
1220         bp->flags |= BNXT_FLAG_UPDATE_HASH;
1221         memcpy(&bp->rss_conf, rss_conf, sizeof(*rss_conf));
1222
1223         if (rss_conf->rss_hf & ETH_RSS_IPV4)
1224                 hash_type |= HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV4;
1225         if (rss_conf->rss_hf & ETH_RSS_NONFRAG_IPV4_TCP)
1226                 hash_type |= HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV4;
1227         if (rss_conf->rss_hf & ETH_RSS_NONFRAG_IPV4_UDP)
1228                 hash_type |= HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV4;
1229         if (rss_conf->rss_hf & ETH_RSS_IPV6)
1230                 hash_type |= HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6;
1231         if (rss_conf->rss_hf & ETH_RSS_NONFRAG_IPV6_TCP)
1232                 hash_type |= HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV6;
1233         if (rss_conf->rss_hf & ETH_RSS_NONFRAG_IPV6_UDP)
1234                 hash_type |= HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV6;
1235
1236         /* Update the RSS VNIC(s) */
1237         for (i = 0; i < bp->nr_vnics; i++) {
1238                 vnic = &bp->vnic_info[i];
1239                 vnic->hash_type = hash_type;
1240
1241                 /*
1242                  * Use the supplied key if the key length is
1243                  * acceptable and the rss_key is not NULL
1244                  */
1245                 if (rss_conf->rss_key &&
1246                     rss_conf->rss_key_len <= HW_HASH_KEY_SIZE)
1247                         memcpy(vnic->rss_hash_key, rss_conf->rss_key,
1248                                rss_conf->rss_key_len);
1249
1250                 bnxt_hwrm_vnic_rss_cfg(bp, vnic);
1251         }
1252         return 0;
1253 }
1254
1255 static int bnxt_rss_hash_conf_get_op(struct rte_eth_dev *eth_dev,
1256                                      struct rte_eth_rss_conf *rss_conf)
1257 {
1258         struct bnxt *bp = eth_dev->data->dev_private;
1259         struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
1260         int len;
1261         uint32_t hash_types;
1262
1263         /* RSS configuration is the same for all VNICs */
1264         if (vnic && vnic->rss_hash_key) {
1265                 if (rss_conf->rss_key) {
1266                         len = rss_conf->rss_key_len <= HW_HASH_KEY_SIZE ?
1267                               rss_conf->rss_key_len : HW_HASH_KEY_SIZE;
1268                         memcpy(rss_conf->rss_key, vnic->rss_hash_key, len);
1269                 }
1270
1271                 hash_types = vnic->hash_type;
1272                 rss_conf->rss_hf = 0;
1273                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV4) {
1274                         rss_conf->rss_hf |= ETH_RSS_IPV4;
1275                         hash_types &= ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV4;
1276                 }
1277                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV4) {
1278                         rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP;
1279                         hash_types &=
1280                                 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV4;
1281                 }
1282                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV4) {
1283                         rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
1284                         hash_types &=
1285                                 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV4;
1286                 }
1287                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6) {
1288                         rss_conf->rss_hf |= ETH_RSS_IPV6;
1289                         hash_types &= ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6;
1290                 }
1291                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV6) {
1292                         rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV6_TCP;
1293                         hash_types &=
1294                                 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV6;
1295                 }
1296                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV6) {
1297                         rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;
1298                         hash_types &=
1299                                 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV6;
1300                 }
1301                 if (hash_types) {
1302                         PMD_DRV_LOG(ERR,
1303                                 "Unknwon RSS config from firmware (%08x), RSS disabled",
1304                                 vnic->hash_type);
1305                         return -ENOTSUP;
1306                 }
1307         } else {
1308                 rss_conf->rss_hf = 0;
1309         }
1310         return 0;
1311 }
1312
1313 static int bnxt_flow_ctrl_get_op(struct rte_eth_dev *dev,
1314                                struct rte_eth_fc_conf *fc_conf)
1315 {
1316         struct bnxt *bp = dev->data->dev_private;
1317         struct rte_eth_link link_info;
1318         int rc;
1319
1320         rc = bnxt_get_hwrm_link_config(bp, &link_info);
1321         if (rc)
1322                 return rc;
1323
1324         memset(fc_conf, 0, sizeof(*fc_conf));
1325         if (bp->link_info.auto_pause)
1326                 fc_conf->autoneg = 1;
1327         switch (bp->link_info.pause) {
1328         case 0:
1329                 fc_conf->mode = RTE_FC_NONE;
1330                 break;
1331         case HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_TX:
1332                 fc_conf->mode = RTE_FC_TX_PAUSE;
1333                 break;
1334         case HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_RX:
1335                 fc_conf->mode = RTE_FC_RX_PAUSE;
1336                 break;
1337         case (HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_TX |
1338                         HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_RX):
1339                 fc_conf->mode = RTE_FC_FULL;
1340                 break;
1341         }
1342         return 0;
1343 }
1344
1345 static int bnxt_flow_ctrl_set_op(struct rte_eth_dev *dev,
1346                                struct rte_eth_fc_conf *fc_conf)
1347 {
1348         struct bnxt *bp = dev->data->dev_private;
1349
1350         if (!BNXT_SINGLE_PF(bp) || BNXT_VF(bp)) {
1351                 PMD_DRV_LOG(ERR, "Flow Control Settings cannot be modified\n");
1352                 return -ENOTSUP;
1353         }
1354
1355         switch (fc_conf->mode) {
1356         case RTE_FC_NONE:
1357                 bp->link_info.auto_pause = 0;
1358                 bp->link_info.force_pause = 0;
1359                 break;
1360         case RTE_FC_RX_PAUSE:
1361                 if (fc_conf->autoneg) {
1362                         bp->link_info.auto_pause =
1363                                         HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_RX;
1364                         bp->link_info.force_pause = 0;
1365                 } else {
1366                         bp->link_info.auto_pause = 0;
1367                         bp->link_info.force_pause =
1368                                         HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_RX;
1369                 }
1370                 break;
1371         case RTE_FC_TX_PAUSE:
1372                 if (fc_conf->autoneg) {
1373                         bp->link_info.auto_pause =
1374                                         HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_TX;
1375                         bp->link_info.force_pause = 0;
1376                 } else {
1377                         bp->link_info.auto_pause = 0;
1378                         bp->link_info.force_pause =
1379                                         HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_TX;
1380                 }
1381                 break;
1382         case RTE_FC_FULL:
1383                 if (fc_conf->autoneg) {
1384                         bp->link_info.auto_pause =
1385                                         HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_TX |
1386                                         HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_RX;
1387                         bp->link_info.force_pause = 0;
1388                 } else {
1389                         bp->link_info.auto_pause = 0;
1390                         bp->link_info.force_pause =
1391                                         HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_TX |
1392                                         HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_RX;
1393                 }
1394                 break;
1395         }
1396         return bnxt_set_hwrm_link_config(bp, true);
1397 }
1398
1399 /* Add UDP tunneling port */
1400 static int
1401 bnxt_udp_tunnel_port_add_op(struct rte_eth_dev *eth_dev,
1402                          struct rte_eth_udp_tunnel *udp_tunnel)
1403 {
1404         struct bnxt *bp = eth_dev->data->dev_private;
1405         uint16_t tunnel_type = 0;
1406         int rc = 0;
1407
1408         switch (udp_tunnel->prot_type) {
1409         case RTE_TUNNEL_TYPE_VXLAN:
1410                 if (bp->vxlan_port_cnt) {
1411                         PMD_DRV_LOG(ERR, "Tunnel Port %d already programmed\n",
1412                                 udp_tunnel->udp_port);
1413                         if (bp->vxlan_port != udp_tunnel->udp_port) {
1414                                 PMD_DRV_LOG(ERR, "Only one port allowed\n");
1415                                 return -ENOSPC;
1416                         }
1417                         bp->vxlan_port_cnt++;
1418                         return 0;
1419                 }
1420                 tunnel_type =
1421                         HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_VXLAN;
1422                 bp->vxlan_port_cnt++;
1423                 break;
1424         case RTE_TUNNEL_TYPE_GENEVE:
1425                 if (bp->geneve_port_cnt) {
1426                         PMD_DRV_LOG(ERR, "Tunnel Port %d already programmed\n",
1427                                 udp_tunnel->udp_port);
1428                         if (bp->geneve_port != udp_tunnel->udp_port) {
1429                                 PMD_DRV_LOG(ERR, "Only one port allowed\n");
1430                                 return -ENOSPC;
1431                         }
1432                         bp->geneve_port_cnt++;
1433                         return 0;
1434                 }
1435                 tunnel_type =
1436                         HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_GENEVE;
1437                 bp->geneve_port_cnt++;
1438                 break;
1439         default:
1440                 PMD_DRV_LOG(ERR, "Tunnel type is not supported\n");
1441                 return -ENOTSUP;
1442         }
1443         rc = bnxt_hwrm_tunnel_dst_port_alloc(bp, udp_tunnel->udp_port,
1444                                              tunnel_type);
1445         return rc;
1446 }
1447
1448 static int
1449 bnxt_udp_tunnel_port_del_op(struct rte_eth_dev *eth_dev,
1450                          struct rte_eth_udp_tunnel *udp_tunnel)
1451 {
1452         struct bnxt *bp = eth_dev->data->dev_private;
1453         uint16_t tunnel_type = 0;
1454         uint16_t port = 0;
1455         int rc = 0;
1456
1457         switch (udp_tunnel->prot_type) {
1458         case RTE_TUNNEL_TYPE_VXLAN:
1459                 if (!bp->vxlan_port_cnt) {
1460                         PMD_DRV_LOG(ERR, "No Tunnel port configured yet\n");
1461                         return -EINVAL;
1462                 }
1463                 if (bp->vxlan_port != udp_tunnel->udp_port) {
1464                         PMD_DRV_LOG(ERR, "Req Port: %d. Configured port: %d\n",
1465                                 udp_tunnel->udp_port, bp->vxlan_port);
1466                         return -EINVAL;
1467                 }
1468                 if (--bp->vxlan_port_cnt)
1469                         return 0;
1470
1471                 tunnel_type =
1472                         HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN;
1473                 port = bp->vxlan_fw_dst_port_id;
1474                 break;
1475         case RTE_TUNNEL_TYPE_GENEVE:
1476                 if (!bp->geneve_port_cnt) {
1477                         PMD_DRV_LOG(ERR, "No Tunnel port configured yet\n");
1478                         return -EINVAL;
1479                 }
1480                 if (bp->geneve_port != udp_tunnel->udp_port) {
1481                         PMD_DRV_LOG(ERR, "Req Port: %d. Configured port: %d\n",
1482                                 udp_tunnel->udp_port, bp->geneve_port);
1483                         return -EINVAL;
1484                 }
1485                 if (--bp->geneve_port_cnt)
1486                         return 0;
1487
1488                 tunnel_type =
1489                         HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_GENEVE;
1490                 port = bp->geneve_fw_dst_port_id;
1491                 break;
1492         default:
1493                 PMD_DRV_LOG(ERR, "Tunnel type is not supported\n");
1494                 return -ENOTSUP;
1495         }
1496
1497         rc = bnxt_hwrm_tunnel_dst_port_free(bp, port, tunnel_type);
1498         if (!rc) {
1499                 if (tunnel_type ==
1500                     HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN)
1501                         bp->vxlan_port = 0;
1502                 if (tunnel_type ==
1503                     HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_GENEVE)
1504                         bp->geneve_port = 0;
1505         }
1506         return rc;
1507 }
1508
1509 static int bnxt_del_vlan_filter(struct bnxt *bp, uint16_t vlan_id)
1510 {
1511         struct bnxt_filter_info *filter;
1512         struct bnxt_vnic_info *vnic;
1513         int rc = 0;
1514         uint32_t chk = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN;
1515
1516         /* if VLAN exists && VLAN matches vlan_id
1517          *      remove the MAC+VLAN filter
1518          *      add a new MAC only filter
1519          * else
1520          *      VLAN filter doesn't exist, just skip and continue
1521          */
1522         vnic = BNXT_GET_DEFAULT_VNIC(bp);
1523         filter = STAILQ_FIRST(&vnic->filter);
1524         while (filter) {
1525                 /* Search for this matching MAC+VLAN filter */
1526                 if (filter->enables & chk && filter->l2_ivlan == vlan_id &&
1527                     !memcmp(filter->l2_addr,
1528                             bp->mac_addr,
1529                             RTE_ETHER_ADDR_LEN)) {
1530                         /* Delete the filter */
1531                         rc = bnxt_hwrm_clear_l2_filter(bp, filter);
1532                         if (rc)
1533                                 return rc;
1534                         STAILQ_REMOVE(&vnic->filter, filter,
1535                                       bnxt_filter_info, next);
1536                         STAILQ_INSERT_TAIL(&bp->free_filter_list, filter, next);
1537
1538                         PMD_DRV_LOG(INFO,
1539                                     "Del Vlan filter for %d\n",
1540                                     vlan_id);
1541                         return rc;
1542                 }
1543                 filter = STAILQ_NEXT(filter, next);
1544         }
1545         return -ENOENT;
1546 }
1547
1548 static int bnxt_add_vlan_filter(struct bnxt *bp, uint16_t vlan_id)
1549 {
1550         struct bnxt_filter_info *filter;
1551         struct bnxt_vnic_info *vnic;
1552         int rc = 0;
1553         uint32_t en = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN |
1554                 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN_MASK;
1555         uint32_t chk = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN;
1556
1557         /* Implementation notes on the use of VNIC in this command:
1558          *
1559          * By default, these filters belong to default vnic for the function.
1560          * Once these filters are set up, only destination VNIC can be modified.
1561          * If the destination VNIC is not specified in this command,
1562          * then the HWRM shall only create an l2 context id.
1563          */
1564
1565         vnic = BNXT_GET_DEFAULT_VNIC(bp);
1566         filter = STAILQ_FIRST(&vnic->filter);
1567         /* Check if the VLAN has already been added */
1568         while (filter) {
1569                 if (filter->enables & chk && filter->l2_ivlan == vlan_id &&
1570                     !memcmp(filter->l2_addr, bp->mac_addr, RTE_ETHER_ADDR_LEN))
1571                         return -EEXIST;
1572
1573                 filter = STAILQ_NEXT(filter, next);
1574         }
1575
1576         /* No match found. Alloc a fresh filter and issue the L2_FILTER_ALLOC
1577          * command to create MAC+VLAN filter with the right flags, enables set.
1578          */
1579         filter = bnxt_alloc_filter(bp);
1580         if (!filter) {
1581                 PMD_DRV_LOG(ERR,
1582                             "MAC/VLAN filter alloc failed\n");
1583                 return -ENOMEM;
1584         }
1585         /* MAC + VLAN ID filter */
1586         filter->l2_ivlan = vlan_id;
1587         filter->l2_ivlan_mask = 0x0FFF;
1588         filter->enables |= en;
1589         rc = bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id, filter);
1590         if (rc) {
1591                 /* Free the newly allocated filter as we were
1592                  * not able to create the filter in hardware.
1593                  */
1594                 filter->fw_l2_filter_id = UINT64_MAX;
1595                 STAILQ_INSERT_TAIL(&bp->free_filter_list, filter, next);
1596                 return rc;
1597         }
1598
1599         /* Add this new filter to the list */
1600         STAILQ_INSERT_TAIL(&vnic->filter, filter, next);
1601         PMD_DRV_LOG(INFO,
1602                     "Added Vlan filter for %d\n", vlan_id);
1603         return rc;
1604 }
1605
1606 static int bnxt_vlan_filter_set_op(struct rte_eth_dev *eth_dev,
1607                 uint16_t vlan_id, int on)
1608 {
1609         struct bnxt *bp = eth_dev->data->dev_private;
1610
1611         /* These operations apply to ALL existing MAC/VLAN filters */
1612         if (on)
1613                 return bnxt_add_vlan_filter(bp, vlan_id);
1614         else
1615                 return bnxt_del_vlan_filter(bp, vlan_id);
1616 }
1617
1618 static int
1619 bnxt_vlan_offload_set_op(struct rte_eth_dev *dev, int mask)
1620 {
1621         struct bnxt *bp = dev->data->dev_private;
1622         uint64_t rx_offloads = dev->data->dev_conf.rxmode.offloads;
1623         unsigned int i;
1624
1625         if (mask & ETH_VLAN_FILTER_MASK) {
1626                 if (!(rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER)) {
1627                         /* Remove any VLAN filters programmed */
1628                         for (i = 0; i < 4095; i++)
1629                                 bnxt_del_vlan_filter(bp, i);
1630                 }
1631                 PMD_DRV_LOG(DEBUG, "VLAN Filtering: %d\n",
1632                         !!(rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER));
1633         }
1634
1635         if (mask & ETH_VLAN_STRIP_MASK) {
1636                 /* Enable or disable VLAN stripping */
1637                 for (i = 0; i < bp->nr_vnics; i++) {
1638                         struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
1639                         if (rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
1640                                 vnic->vlan_strip = true;
1641                         else
1642                                 vnic->vlan_strip = false;
1643                         bnxt_hwrm_vnic_cfg(bp, vnic);
1644                 }
1645                 PMD_DRV_LOG(DEBUG, "VLAN Strip Offload: %d\n",
1646                         !!(rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP));
1647         }
1648
1649         if (mask & ETH_VLAN_EXTEND_MASK)
1650                 PMD_DRV_LOG(ERR, "Extend VLAN Not supported\n");
1651
1652         return 0;
1653 }
1654
1655 static int
1656 bnxt_set_default_mac_addr_op(struct rte_eth_dev *dev,
1657                         struct rte_ether_addr *addr)
1658 {
1659         struct bnxt *bp = dev->data->dev_private;
1660         /* Default Filter is tied to VNIC 0 */
1661         struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
1662         struct bnxt_filter_info *filter;
1663         int rc;
1664
1665         if (BNXT_VF(bp) && !BNXT_VF_IS_TRUSTED(bp))
1666                 return -EPERM;
1667
1668         if (rte_is_zero_ether_addr(addr))
1669                 return -EINVAL;
1670
1671         STAILQ_FOREACH(filter, &vnic->filter, next) {
1672                 /* Default Filter is at Index 0 */
1673                 if (filter->mac_index != 0)
1674                         continue;
1675
1676                 memcpy(filter->l2_addr, bp->mac_addr, RTE_ETHER_ADDR_LEN);
1677                 memset(filter->l2_addr_mask, 0xff, RTE_ETHER_ADDR_LEN);
1678                 filter->flags |= HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_PATH_RX;
1679                 filter->enables |=
1680                         HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR |
1681                         HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR_MASK;
1682
1683                 rc = bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id, filter);
1684                 if (rc)
1685                         return rc;
1686
1687                 memcpy(bp->mac_addr, addr, RTE_ETHER_ADDR_LEN);
1688                 PMD_DRV_LOG(DEBUG, "Set MAC addr\n");
1689                 return 0;
1690         }
1691
1692         return 0;
1693 }
1694
1695 static int
1696 bnxt_dev_set_mc_addr_list_op(struct rte_eth_dev *eth_dev,
1697                           struct rte_ether_addr *mc_addr_set,
1698                           uint32_t nb_mc_addr)
1699 {
1700         struct bnxt *bp = eth_dev->data->dev_private;
1701         char *mc_addr_list = (char *)mc_addr_set;
1702         struct bnxt_vnic_info *vnic;
1703         uint32_t off = 0, i = 0;
1704
1705         vnic = &bp->vnic_info[0];
1706
1707         if (nb_mc_addr > BNXT_MAX_MC_ADDRS) {
1708                 vnic->flags |= BNXT_VNIC_INFO_ALLMULTI;
1709                 goto allmulti;
1710         }
1711
1712         /* TODO Check for Duplicate mcast addresses */
1713         vnic->flags &= ~BNXT_VNIC_INFO_ALLMULTI;
1714         for (i = 0; i < nb_mc_addr; i++) {
1715                 memcpy(vnic->mc_list + off, &mc_addr_list[i],
1716                         RTE_ETHER_ADDR_LEN);
1717                 off += RTE_ETHER_ADDR_LEN;
1718         }
1719
1720         vnic->mc_addr_cnt = i;
1721
1722 allmulti:
1723         return bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1724 }
1725
1726 static int
1727 bnxt_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size)
1728 {
1729         struct bnxt *bp = dev->data->dev_private;
1730         uint8_t fw_major = (bp->fw_ver >> 24) & 0xff;
1731         uint8_t fw_minor = (bp->fw_ver >> 16) & 0xff;
1732         uint8_t fw_updt = (bp->fw_ver >> 8) & 0xff;
1733         int ret;
1734
1735         ret = snprintf(fw_version, fw_size, "%d.%d.%d",
1736                         fw_major, fw_minor, fw_updt);
1737
1738         ret += 1; /* add the size of '\0' */
1739         if (fw_size < (uint32_t)ret)
1740                 return ret;
1741         else
1742                 return 0;
1743 }
1744
1745 static void
1746 bnxt_rxq_info_get_op(struct rte_eth_dev *dev, uint16_t queue_id,
1747         struct rte_eth_rxq_info *qinfo)
1748 {
1749         struct bnxt_rx_queue *rxq;
1750
1751         rxq = dev->data->rx_queues[queue_id];
1752
1753         qinfo->mp = rxq->mb_pool;
1754         qinfo->scattered_rx = dev->data->scattered_rx;
1755         qinfo->nb_desc = rxq->nb_rx_desc;
1756
1757         qinfo->conf.rx_free_thresh = rxq->rx_free_thresh;
1758         qinfo->conf.rx_drop_en = 0;
1759         qinfo->conf.rx_deferred_start = 0;
1760 }
1761
1762 static void
1763 bnxt_txq_info_get_op(struct rte_eth_dev *dev, uint16_t queue_id,
1764         struct rte_eth_txq_info *qinfo)
1765 {
1766         struct bnxt_tx_queue *txq;
1767
1768         txq = dev->data->tx_queues[queue_id];
1769
1770         qinfo->nb_desc = txq->nb_tx_desc;
1771
1772         qinfo->conf.tx_thresh.pthresh = txq->pthresh;
1773         qinfo->conf.tx_thresh.hthresh = txq->hthresh;
1774         qinfo->conf.tx_thresh.wthresh = txq->wthresh;
1775
1776         qinfo->conf.tx_free_thresh = txq->tx_free_thresh;
1777         qinfo->conf.tx_rs_thresh = 0;
1778         qinfo->conf.tx_deferred_start = txq->tx_deferred_start;
1779 }
1780
1781 static int bnxt_mtu_set_op(struct rte_eth_dev *eth_dev, uint16_t new_mtu)
1782 {
1783         struct bnxt *bp = eth_dev->data->dev_private;
1784         struct rte_eth_dev_info dev_info;
1785         uint32_t new_pkt_size;
1786         uint32_t rc = 0;
1787         uint32_t i;
1788
1789         new_pkt_size = new_mtu + RTE_ETHER_HDR_LEN + RTE_ETHER_CRC_LEN +
1790                        VLAN_TAG_SIZE * BNXT_NUM_VLANS;
1791
1792         rc = bnxt_dev_info_get_op(eth_dev, &dev_info);
1793         if (rc != 0) {
1794                 PMD_DRV_LOG(ERR, "Error during getting ethernet device info\n");
1795                 return rc;
1796         }
1797
1798         if (new_mtu < RTE_ETHER_MIN_MTU || new_mtu > BNXT_MAX_MTU) {
1799                 PMD_DRV_LOG(ERR, "MTU requested must be within (%d, %d)\n",
1800                         RTE_ETHER_MIN_MTU, BNXT_MAX_MTU);
1801                 return -EINVAL;
1802         }
1803
1804 #ifdef RTE_ARCH_X86
1805         /*
1806          * If vector-mode tx/rx is active, disallow any MTU change that would
1807          * require scattered receive support.
1808          */
1809         if (eth_dev->data->dev_started &&
1810             (eth_dev->rx_pkt_burst == bnxt_recv_pkts_vec ||
1811              eth_dev->tx_pkt_burst == bnxt_xmit_pkts_vec) &&
1812             (new_pkt_size >
1813              eth_dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM)) {
1814                 PMD_DRV_LOG(ERR,
1815                             "MTU change would require scattered rx support. ");
1816                 PMD_DRV_LOG(ERR, "Stop port before changing MTU.\n");
1817                 return -EINVAL;
1818         }
1819 #endif
1820
1821         if (new_mtu > RTE_ETHER_MTU) {
1822                 bp->flags |= BNXT_FLAG_JUMBO;
1823                 bp->eth_dev->data->dev_conf.rxmode.offloads |=
1824                         DEV_RX_OFFLOAD_JUMBO_FRAME;
1825         } else {
1826                 bp->eth_dev->data->dev_conf.rxmode.offloads &=
1827                         ~DEV_RX_OFFLOAD_JUMBO_FRAME;
1828                 bp->flags &= ~BNXT_FLAG_JUMBO;
1829         }
1830
1831         eth_dev->data->dev_conf.rxmode.max_rx_pkt_len = new_pkt_size;
1832
1833         eth_dev->data->mtu = new_mtu;
1834         PMD_DRV_LOG(INFO, "New MTU is %d\n", eth_dev->data->mtu);
1835
1836         for (i = 0; i < bp->nr_vnics; i++) {
1837                 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
1838                 uint16_t size = 0;
1839
1840                 vnic->mru = bp->eth_dev->data->mtu + RTE_ETHER_HDR_LEN +
1841                                         RTE_ETHER_CRC_LEN + VLAN_TAG_SIZE * 2;
1842                 rc = bnxt_hwrm_vnic_cfg(bp, vnic);
1843                 if (rc)
1844                         break;
1845
1846                 size = rte_pktmbuf_data_room_size(bp->rx_queues[0]->mb_pool);
1847                 size -= RTE_PKTMBUF_HEADROOM;
1848
1849                 if (size < new_mtu) {
1850                         rc = bnxt_hwrm_vnic_plcmode_cfg(bp, vnic);
1851                         if (rc)
1852                                 return rc;
1853                 }
1854         }
1855
1856         return rc;
1857 }
1858
1859 static int
1860 bnxt_vlan_pvid_set_op(struct rte_eth_dev *dev, uint16_t pvid, int on)
1861 {
1862         struct bnxt *bp = dev->data->dev_private;
1863         uint16_t vlan = bp->vlan;
1864         int rc;
1865
1866         if (!BNXT_SINGLE_PF(bp) || BNXT_VF(bp)) {
1867                 PMD_DRV_LOG(ERR,
1868                         "PVID cannot be modified for this function\n");
1869                 return -ENOTSUP;
1870         }
1871         bp->vlan = on ? pvid : 0;
1872
1873         rc = bnxt_hwrm_set_default_vlan(bp, 0, 0);
1874         if (rc)
1875                 bp->vlan = vlan;
1876         return rc;
1877 }
1878
1879 static int
1880 bnxt_dev_led_on_op(struct rte_eth_dev *dev)
1881 {
1882         struct bnxt *bp = dev->data->dev_private;
1883
1884         return bnxt_hwrm_port_led_cfg(bp, true);
1885 }
1886
1887 static int
1888 bnxt_dev_led_off_op(struct rte_eth_dev *dev)
1889 {
1890         struct bnxt *bp = dev->data->dev_private;
1891
1892         return bnxt_hwrm_port_led_cfg(bp, false);
1893 }
1894
1895 static uint32_t
1896 bnxt_rx_queue_count_op(struct rte_eth_dev *dev, uint16_t rx_queue_id)
1897 {
1898         uint32_t desc = 0, raw_cons = 0, cons;
1899         struct bnxt_cp_ring_info *cpr;
1900         struct bnxt_rx_queue *rxq;
1901         struct rx_pkt_cmpl *rxcmp;
1902         uint16_t cmp_type;
1903         uint8_t cmp = 1;
1904         bool valid;
1905
1906         rxq = dev->data->rx_queues[rx_queue_id];
1907         cpr = rxq->cp_ring;
1908         valid = cpr->valid;
1909
1910         while (raw_cons < rxq->nb_rx_desc) {
1911                 cons = RING_CMP(cpr->cp_ring_struct, raw_cons);
1912                 rxcmp = (struct rx_pkt_cmpl *)&cpr->cp_desc_ring[cons];
1913
1914                 if (!CMPL_VALID(rxcmp, valid))
1915                         goto nothing_to_do;
1916                 valid = FLIP_VALID(cons, cpr->cp_ring_struct->ring_mask, valid);
1917                 cmp_type = CMP_TYPE(rxcmp);
1918                 if (cmp_type == RX_TPA_END_CMPL_TYPE_RX_TPA_END) {
1919                         cmp = (rte_le_to_cpu_32(
1920                                         ((struct rx_tpa_end_cmpl *)
1921                                          (rxcmp))->agg_bufs_v1) &
1922                                RX_TPA_END_CMPL_AGG_BUFS_MASK) >>
1923                                 RX_TPA_END_CMPL_AGG_BUFS_SFT;
1924                         desc++;
1925                 } else if (cmp_type == 0x11) {
1926                         desc++;
1927                         cmp = (rxcmp->agg_bufs_v1 &
1928                                    RX_PKT_CMPL_AGG_BUFS_MASK) >>
1929                                 RX_PKT_CMPL_AGG_BUFS_SFT;
1930                 } else {
1931                         cmp = 1;
1932                 }
1933 nothing_to_do:
1934                 raw_cons += cmp ? cmp : 2;
1935         }
1936
1937         return desc;
1938 }
1939
1940 static int
1941 bnxt_rx_descriptor_status_op(void *rx_queue, uint16_t offset)
1942 {
1943         struct bnxt_rx_queue *rxq = (struct bnxt_rx_queue *)rx_queue;
1944         struct bnxt_rx_ring_info *rxr;
1945         struct bnxt_cp_ring_info *cpr;
1946         struct bnxt_sw_rx_bd *rx_buf;
1947         struct rx_pkt_cmpl *rxcmp;
1948         uint32_t cons, cp_cons;
1949
1950         if (!rxq)
1951                 return -EINVAL;
1952
1953         cpr = rxq->cp_ring;
1954         rxr = rxq->rx_ring;
1955
1956         if (offset >= rxq->nb_rx_desc)
1957                 return -EINVAL;
1958
1959         cons = RING_CMP(cpr->cp_ring_struct, offset);
1960         cp_cons = cpr->cp_raw_cons;
1961         rxcmp = (struct rx_pkt_cmpl *)&cpr->cp_desc_ring[cons];
1962
1963         if (cons > cp_cons) {
1964                 if (CMPL_VALID(rxcmp, cpr->valid))
1965                         return RTE_ETH_RX_DESC_DONE;
1966         } else {
1967                 if (CMPL_VALID(rxcmp, !cpr->valid))
1968                         return RTE_ETH_RX_DESC_DONE;
1969         }
1970         rx_buf = &rxr->rx_buf_ring[cons];
1971         if (rx_buf->mbuf == NULL)
1972                 return RTE_ETH_RX_DESC_UNAVAIL;
1973
1974
1975         return RTE_ETH_RX_DESC_AVAIL;
1976 }
1977
1978 static int
1979 bnxt_tx_descriptor_status_op(void *tx_queue, uint16_t offset)
1980 {
1981         struct bnxt_tx_queue *txq = (struct bnxt_tx_queue *)tx_queue;
1982         struct bnxt_tx_ring_info *txr;
1983         struct bnxt_cp_ring_info *cpr;
1984         struct bnxt_sw_tx_bd *tx_buf;
1985         struct tx_pkt_cmpl *txcmp;
1986         uint32_t cons, cp_cons;
1987
1988         if (!txq)
1989                 return -EINVAL;
1990
1991         cpr = txq->cp_ring;
1992         txr = txq->tx_ring;
1993
1994         if (offset >= txq->nb_tx_desc)
1995                 return -EINVAL;
1996
1997         cons = RING_CMP(cpr->cp_ring_struct, offset);
1998         txcmp = (struct tx_pkt_cmpl *)&cpr->cp_desc_ring[cons];
1999         cp_cons = cpr->cp_raw_cons;
2000
2001         if (cons > cp_cons) {
2002                 if (CMPL_VALID(txcmp, cpr->valid))
2003                         return RTE_ETH_TX_DESC_UNAVAIL;
2004         } else {
2005                 if (CMPL_VALID(txcmp, !cpr->valid))
2006                         return RTE_ETH_TX_DESC_UNAVAIL;
2007         }
2008         tx_buf = &txr->tx_buf_ring[cons];
2009         if (tx_buf->mbuf == NULL)
2010                 return RTE_ETH_TX_DESC_DONE;
2011
2012         return RTE_ETH_TX_DESC_FULL;
2013 }
2014
2015 static struct bnxt_filter_info *
2016 bnxt_match_and_validate_ether_filter(struct bnxt *bp,
2017                                 struct rte_eth_ethertype_filter *efilter,
2018                                 struct bnxt_vnic_info *vnic0,
2019                                 struct bnxt_vnic_info *vnic,
2020                                 int *ret)
2021 {
2022         struct bnxt_filter_info *mfilter = NULL;
2023         int match = 0;
2024         *ret = 0;
2025
2026         if (efilter->ether_type == RTE_ETHER_TYPE_IPV4 ||
2027                 efilter->ether_type == RTE_ETHER_TYPE_IPV6) {
2028                 PMD_DRV_LOG(ERR, "invalid ether_type(0x%04x) in"
2029                         " ethertype filter.", efilter->ether_type);
2030                 *ret = -EINVAL;
2031                 goto exit;
2032         }
2033         if (efilter->queue >= bp->rx_nr_rings) {
2034                 PMD_DRV_LOG(ERR, "Invalid queue %d\n", efilter->queue);
2035                 *ret = -EINVAL;
2036                 goto exit;
2037         }
2038
2039         vnic0 = &bp->vnic_info[0];
2040         vnic = &bp->vnic_info[efilter->queue];
2041         if (vnic == NULL) {
2042                 PMD_DRV_LOG(ERR, "Invalid queue %d\n", efilter->queue);
2043                 *ret = -EINVAL;
2044                 goto exit;
2045         }
2046
2047         if (efilter->flags & RTE_ETHTYPE_FLAGS_DROP) {
2048                 STAILQ_FOREACH(mfilter, &vnic0->filter, next) {
2049                         if ((!memcmp(efilter->mac_addr.addr_bytes,
2050                                      mfilter->l2_addr, RTE_ETHER_ADDR_LEN) &&
2051                              mfilter->flags ==
2052                              HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_DROP &&
2053                              mfilter->ethertype == efilter->ether_type)) {
2054                                 match = 1;
2055                                 break;
2056                         }
2057                 }
2058         } else {
2059                 STAILQ_FOREACH(mfilter, &vnic->filter, next)
2060                         if ((!memcmp(efilter->mac_addr.addr_bytes,
2061                                      mfilter->l2_addr, RTE_ETHER_ADDR_LEN) &&
2062                              mfilter->ethertype == efilter->ether_type &&
2063                              mfilter->flags ==
2064                              HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_PATH_RX)) {
2065                                 match = 1;
2066                                 break;
2067                         }
2068         }
2069
2070         if (match)
2071                 *ret = -EEXIST;
2072
2073 exit:
2074         return mfilter;
2075 }
2076
2077 static int
2078 bnxt_ethertype_filter(struct rte_eth_dev *dev,
2079                         enum rte_filter_op filter_op,
2080                         void *arg)
2081 {
2082         struct bnxt *bp = dev->data->dev_private;
2083         struct rte_eth_ethertype_filter *efilter =
2084                         (struct rte_eth_ethertype_filter *)arg;
2085         struct bnxt_filter_info *bfilter, *filter1;
2086         struct bnxt_vnic_info *vnic, *vnic0;
2087         int ret;
2088
2089         if (filter_op == RTE_ETH_FILTER_NOP)
2090                 return 0;
2091
2092         if (arg == NULL) {
2093                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
2094                             filter_op);
2095                 return -EINVAL;
2096         }
2097
2098         vnic0 = &bp->vnic_info[0];
2099         vnic = &bp->vnic_info[efilter->queue];
2100
2101         switch (filter_op) {
2102         case RTE_ETH_FILTER_ADD:
2103                 bnxt_match_and_validate_ether_filter(bp, efilter,
2104                                                         vnic0, vnic, &ret);
2105                 if (ret < 0)
2106                         return ret;
2107
2108                 bfilter = bnxt_get_unused_filter(bp);
2109                 if (bfilter == NULL) {
2110                         PMD_DRV_LOG(ERR,
2111                                 "Not enough resources for a new filter.\n");
2112                         return -ENOMEM;
2113                 }
2114                 bfilter->filter_type = HWRM_CFA_NTUPLE_FILTER;
2115                 memcpy(bfilter->l2_addr, efilter->mac_addr.addr_bytes,
2116                        RTE_ETHER_ADDR_LEN);
2117                 memcpy(bfilter->dst_macaddr, efilter->mac_addr.addr_bytes,
2118                        RTE_ETHER_ADDR_LEN);
2119                 bfilter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_MACADDR;
2120                 bfilter->ethertype = efilter->ether_type;
2121                 bfilter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2122
2123                 filter1 = bnxt_get_l2_filter(bp, bfilter, vnic0);
2124                 if (filter1 == NULL) {
2125                         ret = -EINVAL;
2126                         goto cleanup;
2127                 }
2128                 bfilter->enables |=
2129                         HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID;
2130                 bfilter->fw_l2_filter_id = filter1->fw_l2_filter_id;
2131
2132                 bfilter->dst_id = vnic->fw_vnic_id;
2133
2134                 if (efilter->flags & RTE_ETHTYPE_FLAGS_DROP) {
2135                         bfilter->flags =
2136                                 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_DROP;
2137                 }
2138
2139                 ret = bnxt_hwrm_set_ntuple_filter(bp, bfilter->dst_id, bfilter);
2140                 if (ret)
2141                         goto cleanup;
2142                 STAILQ_INSERT_TAIL(&vnic->filter, bfilter, next);
2143                 break;
2144         case RTE_ETH_FILTER_DELETE:
2145                 filter1 = bnxt_match_and_validate_ether_filter(bp, efilter,
2146                                                         vnic0, vnic, &ret);
2147                 if (ret == -EEXIST) {
2148                         ret = bnxt_hwrm_clear_ntuple_filter(bp, filter1);
2149
2150                         STAILQ_REMOVE(&vnic->filter, filter1, bnxt_filter_info,
2151                                       next);
2152                         bnxt_free_filter(bp, filter1);
2153                 } else if (ret == 0) {
2154                         PMD_DRV_LOG(ERR, "No matching filter found\n");
2155                 }
2156                 break;
2157         default:
2158                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
2159                 ret = -EINVAL;
2160                 goto error;
2161         }
2162         return ret;
2163 cleanup:
2164         bnxt_free_filter(bp, bfilter);
2165 error:
2166         return ret;
2167 }
2168
2169 static inline int
2170 parse_ntuple_filter(struct bnxt *bp,
2171                     struct rte_eth_ntuple_filter *nfilter,
2172                     struct bnxt_filter_info *bfilter)
2173 {
2174         uint32_t en = 0;
2175
2176         if (nfilter->queue >= bp->rx_nr_rings) {
2177                 PMD_DRV_LOG(ERR, "Invalid queue %d\n", nfilter->queue);
2178                 return -EINVAL;
2179         }
2180
2181         switch (nfilter->dst_port_mask) {
2182         case UINT16_MAX:
2183                 bfilter->dst_port_mask = -1;
2184                 bfilter->dst_port = nfilter->dst_port;
2185                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT |
2186                         NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
2187                 break;
2188         default:
2189                 PMD_DRV_LOG(ERR, "invalid dst_port mask.");
2190                 return -EINVAL;
2191         }
2192
2193         bfilter->ip_addr_type = NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4;
2194         en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2195
2196         switch (nfilter->proto_mask) {
2197         case UINT8_MAX:
2198                 if (nfilter->proto == 17) /* IPPROTO_UDP */
2199                         bfilter->ip_protocol = 17;
2200                 else if (nfilter->proto == 6) /* IPPROTO_TCP */
2201                         bfilter->ip_protocol = 6;
2202                 else
2203                         return -EINVAL;
2204                 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2205                 break;
2206         default:
2207                 PMD_DRV_LOG(ERR, "invalid protocol mask.");
2208                 return -EINVAL;
2209         }
2210
2211         switch (nfilter->dst_ip_mask) {
2212         case UINT32_MAX:
2213                 bfilter->dst_ipaddr_mask[0] = -1;
2214                 bfilter->dst_ipaddr[0] = nfilter->dst_ip;
2215                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR |
2216                         NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2217                 break;
2218         default:
2219                 PMD_DRV_LOG(ERR, "invalid dst_ip mask.");
2220                 return -EINVAL;
2221         }
2222
2223         switch (nfilter->src_ip_mask) {
2224         case UINT32_MAX:
2225                 bfilter->src_ipaddr_mask[0] = -1;
2226                 bfilter->src_ipaddr[0] = nfilter->src_ip;
2227                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR |
2228                         NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2229                 break;
2230         default:
2231                 PMD_DRV_LOG(ERR, "invalid src_ip mask.");
2232                 return -EINVAL;
2233         }
2234
2235         switch (nfilter->src_port_mask) {
2236         case UINT16_MAX:
2237                 bfilter->src_port_mask = -1;
2238                 bfilter->src_port = nfilter->src_port;
2239                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT |
2240                         NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
2241                 break;
2242         default:
2243                 PMD_DRV_LOG(ERR, "invalid src_port mask.");
2244                 return -EINVAL;
2245         }
2246
2247         //TODO Priority
2248         //nfilter->priority = (uint8_t)filter->priority;
2249
2250         bfilter->enables = en;
2251         return 0;
2252 }
2253
2254 static struct bnxt_filter_info*
2255 bnxt_match_ntuple_filter(struct bnxt *bp,
2256                          struct bnxt_filter_info *bfilter,
2257                          struct bnxt_vnic_info **mvnic)
2258 {
2259         struct bnxt_filter_info *mfilter = NULL;
2260         int i;
2261
2262         for (i = bp->nr_vnics - 1; i >= 0; i--) {
2263                 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
2264                 STAILQ_FOREACH(mfilter, &vnic->filter, next) {
2265                         if (bfilter->src_ipaddr[0] == mfilter->src_ipaddr[0] &&
2266                             bfilter->src_ipaddr_mask[0] ==
2267                             mfilter->src_ipaddr_mask[0] &&
2268                             bfilter->src_port == mfilter->src_port &&
2269                             bfilter->src_port_mask == mfilter->src_port_mask &&
2270                             bfilter->dst_ipaddr[0] == mfilter->dst_ipaddr[0] &&
2271                             bfilter->dst_ipaddr_mask[0] ==
2272                             mfilter->dst_ipaddr_mask[0] &&
2273                             bfilter->dst_port == mfilter->dst_port &&
2274                             bfilter->dst_port_mask == mfilter->dst_port_mask &&
2275                             bfilter->flags == mfilter->flags &&
2276                             bfilter->enables == mfilter->enables) {
2277                                 if (mvnic)
2278                                         *mvnic = vnic;
2279                                 return mfilter;
2280                         }
2281                 }
2282         }
2283         return NULL;
2284 }
2285
2286 static int
2287 bnxt_cfg_ntuple_filter(struct bnxt *bp,
2288                        struct rte_eth_ntuple_filter *nfilter,
2289                        enum rte_filter_op filter_op)
2290 {
2291         struct bnxt_filter_info *bfilter, *mfilter, *filter1;
2292         struct bnxt_vnic_info *vnic, *vnic0, *mvnic;
2293         int ret;
2294
2295         if (nfilter->flags != RTE_5TUPLE_FLAGS) {
2296                 PMD_DRV_LOG(ERR, "only 5tuple is supported.");
2297                 return -EINVAL;
2298         }
2299
2300         if (nfilter->flags & RTE_NTUPLE_FLAGS_TCP_FLAG) {
2301                 PMD_DRV_LOG(ERR, "Ntuple filter: TCP flags not supported\n");
2302                 return -EINVAL;
2303         }
2304
2305         bfilter = bnxt_get_unused_filter(bp);
2306         if (bfilter == NULL) {
2307                 PMD_DRV_LOG(ERR,
2308                         "Not enough resources for a new filter.\n");
2309                 return -ENOMEM;
2310         }
2311         ret = parse_ntuple_filter(bp, nfilter, bfilter);
2312         if (ret < 0)
2313                 goto free_filter;
2314
2315         vnic = &bp->vnic_info[nfilter->queue];
2316         vnic0 = &bp->vnic_info[0];
2317         filter1 = STAILQ_FIRST(&vnic0->filter);
2318         if (filter1 == NULL) {
2319                 ret = -EINVAL;
2320                 goto free_filter;
2321         }
2322
2323         bfilter->dst_id = vnic->fw_vnic_id;
2324         bfilter->fw_l2_filter_id = filter1->fw_l2_filter_id;
2325         bfilter->enables |=
2326                 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID;
2327         bfilter->ethertype = 0x800;
2328         bfilter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2329
2330         mfilter = bnxt_match_ntuple_filter(bp, bfilter, &mvnic);
2331
2332         if (mfilter != NULL && filter_op == RTE_ETH_FILTER_ADD &&
2333             bfilter->dst_id == mfilter->dst_id) {
2334                 PMD_DRV_LOG(ERR, "filter exists.\n");
2335                 ret = -EEXIST;
2336                 goto free_filter;
2337         } else if (mfilter != NULL && filter_op == RTE_ETH_FILTER_ADD &&
2338                    bfilter->dst_id != mfilter->dst_id) {
2339                 mfilter->dst_id = vnic->fw_vnic_id;
2340                 ret = bnxt_hwrm_set_ntuple_filter(bp, mfilter->dst_id, mfilter);
2341                 STAILQ_REMOVE(&mvnic->filter, mfilter, bnxt_filter_info, next);
2342                 STAILQ_INSERT_TAIL(&vnic->filter, mfilter, next);
2343                 PMD_DRV_LOG(ERR, "filter with matching pattern exists.\n");
2344                 PMD_DRV_LOG(ERR, " Updated it to the new destination queue\n");
2345                 goto free_filter;
2346         }
2347         if (mfilter == NULL && filter_op == RTE_ETH_FILTER_DELETE) {
2348                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
2349                 ret = -ENOENT;
2350                 goto free_filter;
2351         }
2352
2353         if (filter_op == RTE_ETH_FILTER_ADD) {
2354                 bfilter->filter_type = HWRM_CFA_NTUPLE_FILTER;
2355                 ret = bnxt_hwrm_set_ntuple_filter(bp, bfilter->dst_id, bfilter);
2356                 if (ret)
2357                         goto free_filter;
2358                 STAILQ_INSERT_TAIL(&vnic->filter, bfilter, next);
2359         } else {
2360                 if (mfilter == NULL) {
2361                         /* This should not happen. But for Coverity! */
2362                         ret = -ENOENT;
2363                         goto free_filter;
2364                 }
2365                 ret = bnxt_hwrm_clear_ntuple_filter(bp, mfilter);
2366
2367                 STAILQ_REMOVE(&vnic->filter, mfilter, bnxt_filter_info, next);
2368                 bnxt_free_filter(bp, mfilter);
2369                 mfilter->fw_l2_filter_id = -1;
2370                 bnxt_free_filter(bp, bfilter);
2371                 bfilter->fw_l2_filter_id = -1;
2372         }
2373
2374         return 0;
2375 free_filter:
2376         bfilter->fw_l2_filter_id = -1;
2377         bnxt_free_filter(bp, bfilter);
2378         return ret;
2379 }
2380
2381 static int
2382 bnxt_ntuple_filter(struct rte_eth_dev *dev,
2383                         enum rte_filter_op filter_op,
2384                         void *arg)
2385 {
2386         struct bnxt *bp = dev->data->dev_private;
2387         int ret;
2388
2389         if (filter_op == RTE_ETH_FILTER_NOP)
2390                 return 0;
2391
2392         if (arg == NULL) {
2393                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
2394                             filter_op);
2395                 return -EINVAL;
2396         }
2397
2398         switch (filter_op) {
2399         case RTE_ETH_FILTER_ADD:
2400                 ret = bnxt_cfg_ntuple_filter(bp,
2401                         (struct rte_eth_ntuple_filter *)arg,
2402                         filter_op);
2403                 break;
2404         case RTE_ETH_FILTER_DELETE:
2405                 ret = bnxt_cfg_ntuple_filter(bp,
2406                         (struct rte_eth_ntuple_filter *)arg,
2407                         filter_op);
2408                 break;
2409         default:
2410                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
2411                 ret = -EINVAL;
2412                 break;
2413         }
2414         return ret;
2415 }
2416
2417 static int
2418 bnxt_parse_fdir_filter(struct bnxt *bp,
2419                        struct rte_eth_fdir_filter *fdir,
2420                        struct bnxt_filter_info *filter)
2421 {
2422         enum rte_fdir_mode fdir_mode =
2423                 bp->eth_dev->data->dev_conf.fdir_conf.mode;
2424         struct bnxt_vnic_info *vnic0, *vnic;
2425         struct bnxt_filter_info *filter1;
2426         uint32_t en = 0;
2427         int i;
2428
2429         if (fdir_mode == RTE_FDIR_MODE_PERFECT_TUNNEL)
2430                 return -EINVAL;
2431
2432         filter->l2_ovlan = fdir->input.flow_ext.vlan_tci;
2433         en |= EM_FLOW_ALLOC_INPUT_EN_OVLAN_VID;
2434
2435         switch (fdir->input.flow_type) {
2436         case RTE_ETH_FLOW_IPV4:
2437         case RTE_ETH_FLOW_NONFRAG_IPV4_OTHER:
2438                 /* FALLTHROUGH */
2439                 filter->src_ipaddr[0] = fdir->input.flow.ip4_flow.src_ip;
2440                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
2441                 filter->dst_ipaddr[0] = fdir->input.flow.ip4_flow.dst_ip;
2442                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
2443                 filter->ip_protocol = fdir->input.flow.ip4_flow.proto;
2444                 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2445                 filter->ip_addr_type =
2446                         NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4;
2447                 filter->src_ipaddr_mask[0] = 0xffffffff;
2448                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2449                 filter->dst_ipaddr_mask[0] = 0xffffffff;
2450                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2451                 filter->ethertype = 0x800;
2452                 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2453                 break;
2454         case RTE_ETH_FLOW_NONFRAG_IPV4_TCP:
2455                 filter->src_port = fdir->input.flow.tcp4_flow.src_port;
2456                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT;
2457                 filter->dst_port = fdir->input.flow.tcp4_flow.dst_port;
2458                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT;
2459                 filter->dst_port_mask = 0xffff;
2460                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
2461                 filter->src_port_mask = 0xffff;
2462                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
2463                 filter->src_ipaddr[0] = fdir->input.flow.tcp4_flow.ip.src_ip;
2464                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
2465                 filter->dst_ipaddr[0] = fdir->input.flow.tcp4_flow.ip.dst_ip;
2466                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
2467                 filter->ip_protocol = 6;
2468                 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2469                 filter->ip_addr_type =
2470                         NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4;
2471                 filter->src_ipaddr_mask[0] = 0xffffffff;
2472                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2473                 filter->dst_ipaddr_mask[0] = 0xffffffff;
2474                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2475                 filter->ethertype = 0x800;
2476                 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2477                 break;
2478         case RTE_ETH_FLOW_NONFRAG_IPV4_UDP:
2479                 filter->src_port = fdir->input.flow.udp4_flow.src_port;
2480                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT;
2481                 filter->dst_port = fdir->input.flow.udp4_flow.dst_port;
2482                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT;
2483                 filter->dst_port_mask = 0xffff;
2484                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
2485                 filter->src_port_mask = 0xffff;
2486                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
2487                 filter->src_ipaddr[0] = fdir->input.flow.udp4_flow.ip.src_ip;
2488                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
2489                 filter->dst_ipaddr[0] = fdir->input.flow.udp4_flow.ip.dst_ip;
2490                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
2491                 filter->ip_protocol = 17;
2492                 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2493                 filter->ip_addr_type =
2494                         NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4;
2495                 filter->src_ipaddr_mask[0] = 0xffffffff;
2496                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2497                 filter->dst_ipaddr_mask[0] = 0xffffffff;
2498                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2499                 filter->ethertype = 0x800;
2500                 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2501                 break;
2502         case RTE_ETH_FLOW_IPV6:
2503         case RTE_ETH_FLOW_NONFRAG_IPV6_OTHER:
2504                 /* FALLTHROUGH */
2505                 filter->ip_addr_type =
2506                         NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV6;
2507                 filter->ip_protocol = fdir->input.flow.ipv6_flow.proto;
2508                 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2509                 rte_memcpy(filter->src_ipaddr,
2510                            fdir->input.flow.ipv6_flow.src_ip, 16);
2511                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
2512                 rte_memcpy(filter->dst_ipaddr,
2513                            fdir->input.flow.ipv6_flow.dst_ip, 16);
2514                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
2515                 memset(filter->dst_ipaddr_mask, 0xff, 16);
2516                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2517                 memset(filter->src_ipaddr_mask, 0xff, 16);
2518                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2519                 filter->ethertype = 0x86dd;
2520                 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2521                 break;
2522         case RTE_ETH_FLOW_NONFRAG_IPV6_TCP:
2523                 filter->src_port = fdir->input.flow.tcp6_flow.src_port;
2524                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT;
2525                 filter->dst_port = fdir->input.flow.tcp6_flow.dst_port;
2526                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT;
2527                 filter->dst_port_mask = 0xffff;
2528                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
2529                 filter->src_port_mask = 0xffff;
2530                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
2531                 filter->ip_addr_type =
2532                         NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV6;
2533                 filter->ip_protocol = fdir->input.flow.tcp6_flow.ip.proto;
2534                 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2535                 rte_memcpy(filter->src_ipaddr,
2536                            fdir->input.flow.tcp6_flow.ip.src_ip, 16);
2537                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
2538                 rte_memcpy(filter->dst_ipaddr,
2539                            fdir->input.flow.tcp6_flow.ip.dst_ip, 16);
2540                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
2541                 memset(filter->dst_ipaddr_mask, 0xff, 16);
2542                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2543                 memset(filter->src_ipaddr_mask, 0xff, 16);
2544                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2545                 filter->ethertype = 0x86dd;
2546                 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2547                 break;
2548         case RTE_ETH_FLOW_NONFRAG_IPV6_UDP:
2549                 filter->src_port = fdir->input.flow.udp6_flow.src_port;
2550                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT;
2551                 filter->dst_port = fdir->input.flow.udp6_flow.dst_port;
2552                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT;
2553                 filter->dst_port_mask = 0xffff;
2554                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
2555                 filter->src_port_mask = 0xffff;
2556                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
2557                 filter->ip_addr_type =
2558                         NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV6;
2559                 filter->ip_protocol = fdir->input.flow.udp6_flow.ip.proto;
2560                 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2561                 rte_memcpy(filter->src_ipaddr,
2562                            fdir->input.flow.udp6_flow.ip.src_ip, 16);
2563                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
2564                 rte_memcpy(filter->dst_ipaddr,
2565                            fdir->input.flow.udp6_flow.ip.dst_ip, 16);
2566                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
2567                 memset(filter->dst_ipaddr_mask, 0xff, 16);
2568                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2569                 memset(filter->src_ipaddr_mask, 0xff, 16);
2570                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2571                 filter->ethertype = 0x86dd;
2572                 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2573                 break;
2574         case RTE_ETH_FLOW_L2_PAYLOAD:
2575                 filter->ethertype = fdir->input.flow.l2_flow.ether_type;
2576                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2577                 break;
2578         case RTE_ETH_FLOW_VXLAN:
2579                 if (fdir->action.behavior == RTE_ETH_FDIR_REJECT)
2580                         return -EINVAL;
2581                 filter->vni = fdir->input.flow.tunnel_flow.tunnel_id;
2582                 filter->tunnel_type =
2583                         CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN;
2584                 en |= HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_TUNNEL_TYPE;
2585                 break;
2586         case RTE_ETH_FLOW_NVGRE:
2587                 if (fdir->action.behavior == RTE_ETH_FDIR_REJECT)
2588                         return -EINVAL;
2589                 filter->vni = fdir->input.flow.tunnel_flow.tunnel_id;
2590                 filter->tunnel_type =
2591                         CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_NVGRE;
2592                 en |= HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_TUNNEL_TYPE;
2593                 break;
2594         case RTE_ETH_FLOW_UNKNOWN:
2595         case RTE_ETH_FLOW_RAW:
2596         case RTE_ETH_FLOW_FRAG_IPV4:
2597         case RTE_ETH_FLOW_NONFRAG_IPV4_SCTP:
2598         case RTE_ETH_FLOW_FRAG_IPV6:
2599         case RTE_ETH_FLOW_NONFRAG_IPV6_SCTP:
2600         case RTE_ETH_FLOW_IPV6_EX:
2601         case RTE_ETH_FLOW_IPV6_TCP_EX:
2602         case RTE_ETH_FLOW_IPV6_UDP_EX:
2603         case RTE_ETH_FLOW_GENEVE:
2604                 /* FALLTHROUGH */
2605         default:
2606                 return -EINVAL;
2607         }
2608
2609         vnic0 = &bp->vnic_info[0];
2610         vnic = &bp->vnic_info[fdir->action.rx_queue];
2611         if (vnic == NULL) {
2612                 PMD_DRV_LOG(ERR, "Invalid queue %d\n", fdir->action.rx_queue);
2613                 return -EINVAL;
2614         }
2615
2616
2617         if (fdir_mode == RTE_FDIR_MODE_PERFECT_MAC_VLAN) {
2618                 rte_memcpy(filter->dst_macaddr,
2619                         fdir->input.flow.mac_vlan_flow.mac_addr.addr_bytes, 6);
2620                         en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_MACADDR;
2621         }
2622
2623         if (fdir->action.behavior == RTE_ETH_FDIR_REJECT) {
2624                 filter->flags = HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_DROP;
2625                 filter1 = STAILQ_FIRST(&vnic0->filter);
2626                 //filter1 = bnxt_get_l2_filter(bp, filter, vnic0);
2627         } else {
2628                 filter->dst_id = vnic->fw_vnic_id;
2629                 for (i = 0; i < RTE_ETHER_ADDR_LEN; i++)
2630                         if (filter->dst_macaddr[i] == 0x00)
2631                                 filter1 = STAILQ_FIRST(&vnic0->filter);
2632                         else
2633                                 filter1 = bnxt_get_l2_filter(bp, filter, vnic);
2634         }
2635
2636         if (filter1 == NULL)
2637                 return -EINVAL;
2638
2639         en |= HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID;
2640         filter->fw_l2_filter_id = filter1->fw_l2_filter_id;
2641
2642         filter->enables = en;
2643
2644         return 0;
2645 }
2646
2647 static struct bnxt_filter_info *
2648 bnxt_match_fdir(struct bnxt *bp, struct bnxt_filter_info *nf,
2649                 struct bnxt_vnic_info **mvnic)
2650 {
2651         struct bnxt_filter_info *mf = NULL;
2652         int i;
2653
2654         for (i = bp->nr_vnics - 1; i >= 0; i--) {
2655                 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
2656
2657                 STAILQ_FOREACH(mf, &vnic->filter, next) {
2658                         if (mf->filter_type == nf->filter_type &&
2659                             mf->flags == nf->flags &&
2660                             mf->src_port == nf->src_port &&
2661                             mf->src_port_mask == nf->src_port_mask &&
2662                             mf->dst_port == nf->dst_port &&
2663                             mf->dst_port_mask == nf->dst_port_mask &&
2664                             mf->ip_protocol == nf->ip_protocol &&
2665                             mf->ip_addr_type == nf->ip_addr_type &&
2666                             mf->ethertype == nf->ethertype &&
2667                             mf->vni == nf->vni &&
2668                             mf->tunnel_type == nf->tunnel_type &&
2669                             mf->l2_ovlan == nf->l2_ovlan &&
2670                             mf->l2_ovlan_mask == nf->l2_ovlan_mask &&
2671                             mf->l2_ivlan == nf->l2_ivlan &&
2672                             mf->l2_ivlan_mask == nf->l2_ivlan_mask &&
2673                             !memcmp(mf->l2_addr, nf->l2_addr,
2674                                     RTE_ETHER_ADDR_LEN) &&
2675                             !memcmp(mf->l2_addr_mask, nf->l2_addr_mask,
2676                                     RTE_ETHER_ADDR_LEN) &&
2677                             !memcmp(mf->src_macaddr, nf->src_macaddr,
2678                                     RTE_ETHER_ADDR_LEN) &&
2679                             !memcmp(mf->dst_macaddr, nf->dst_macaddr,
2680                                     RTE_ETHER_ADDR_LEN) &&
2681                             !memcmp(mf->src_ipaddr, nf->src_ipaddr,
2682                                     sizeof(nf->src_ipaddr)) &&
2683                             !memcmp(mf->src_ipaddr_mask, nf->src_ipaddr_mask,
2684                                     sizeof(nf->src_ipaddr_mask)) &&
2685                             !memcmp(mf->dst_ipaddr, nf->dst_ipaddr,
2686                                     sizeof(nf->dst_ipaddr)) &&
2687                             !memcmp(mf->dst_ipaddr_mask, nf->dst_ipaddr_mask,
2688                                     sizeof(nf->dst_ipaddr_mask))) {
2689                                 if (mvnic)
2690                                         *mvnic = vnic;
2691                                 return mf;
2692                         }
2693                 }
2694         }
2695         return NULL;
2696 }
2697
2698 static int
2699 bnxt_fdir_filter(struct rte_eth_dev *dev,
2700                  enum rte_filter_op filter_op,
2701                  void *arg)
2702 {
2703         struct bnxt *bp = dev->data->dev_private;
2704         struct rte_eth_fdir_filter *fdir  = (struct rte_eth_fdir_filter *)arg;
2705         struct bnxt_filter_info *filter, *match;
2706         struct bnxt_vnic_info *vnic, *mvnic;
2707         int ret = 0, i;
2708
2709         if (filter_op == RTE_ETH_FILTER_NOP)
2710                 return 0;
2711
2712         if (arg == NULL && filter_op != RTE_ETH_FILTER_FLUSH)
2713                 return -EINVAL;
2714
2715         switch (filter_op) {
2716         case RTE_ETH_FILTER_ADD:
2717         case RTE_ETH_FILTER_DELETE:
2718                 /* FALLTHROUGH */
2719                 filter = bnxt_get_unused_filter(bp);
2720                 if (filter == NULL) {
2721                         PMD_DRV_LOG(ERR,
2722                                 "Not enough resources for a new flow.\n");
2723                         return -ENOMEM;
2724                 }
2725
2726                 ret = bnxt_parse_fdir_filter(bp, fdir, filter);
2727                 if (ret != 0)
2728                         goto free_filter;
2729                 filter->filter_type = HWRM_CFA_NTUPLE_FILTER;
2730
2731                 if (fdir->action.behavior == RTE_ETH_FDIR_REJECT)
2732                         vnic = &bp->vnic_info[0];
2733                 else
2734                         vnic = &bp->vnic_info[fdir->action.rx_queue];
2735
2736                 match = bnxt_match_fdir(bp, filter, &mvnic);
2737                 if (match != NULL && filter_op == RTE_ETH_FILTER_ADD) {
2738                         if (match->dst_id == vnic->fw_vnic_id) {
2739                                 PMD_DRV_LOG(ERR, "Flow already exists.\n");
2740                                 ret = -EEXIST;
2741                                 goto free_filter;
2742                         } else {
2743                                 match->dst_id = vnic->fw_vnic_id;
2744                                 ret = bnxt_hwrm_set_ntuple_filter(bp,
2745                                                                   match->dst_id,
2746                                                                   match);
2747                                 STAILQ_REMOVE(&mvnic->filter, match,
2748                                               bnxt_filter_info, next);
2749                                 STAILQ_INSERT_TAIL(&vnic->filter, match, next);
2750                                 PMD_DRV_LOG(ERR,
2751                                         "Filter with matching pattern exist\n");
2752                                 PMD_DRV_LOG(ERR,
2753                                         "Updated it to new destination q\n");
2754                                 goto free_filter;
2755                         }
2756                 }
2757                 if (match == NULL && filter_op == RTE_ETH_FILTER_DELETE) {
2758                         PMD_DRV_LOG(ERR, "Flow does not exist.\n");
2759                         ret = -ENOENT;
2760                         goto free_filter;
2761                 }
2762
2763                 if (filter_op == RTE_ETH_FILTER_ADD) {
2764                         ret = bnxt_hwrm_set_ntuple_filter(bp,
2765                                                           filter->dst_id,
2766                                                           filter);
2767                         if (ret)
2768                                 goto free_filter;
2769                         STAILQ_INSERT_TAIL(&vnic->filter, filter, next);
2770                 } else {
2771                         ret = bnxt_hwrm_clear_ntuple_filter(bp, match);
2772                         STAILQ_REMOVE(&vnic->filter, match,
2773                                       bnxt_filter_info, next);
2774                         bnxt_free_filter(bp, match);
2775                         filter->fw_l2_filter_id = -1;
2776                         bnxt_free_filter(bp, filter);
2777                 }
2778                 break;
2779         case RTE_ETH_FILTER_FLUSH:
2780                 for (i = bp->nr_vnics - 1; i >= 0; i--) {
2781                         struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
2782
2783                         STAILQ_FOREACH(filter, &vnic->filter, next) {
2784                                 if (filter->filter_type ==
2785                                     HWRM_CFA_NTUPLE_FILTER) {
2786                                         ret =
2787                                         bnxt_hwrm_clear_ntuple_filter(bp,
2788                                                                       filter);
2789                                         STAILQ_REMOVE(&vnic->filter, filter,
2790                                                       bnxt_filter_info, next);
2791                                 }
2792                         }
2793                 }
2794                 return ret;
2795         case RTE_ETH_FILTER_UPDATE:
2796         case RTE_ETH_FILTER_STATS:
2797         case RTE_ETH_FILTER_INFO:
2798                 PMD_DRV_LOG(ERR, "operation %u not implemented", filter_op);
2799                 break;
2800         default:
2801                 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
2802                 ret = -EINVAL;
2803                 break;
2804         }
2805         return ret;
2806
2807 free_filter:
2808         filter->fw_l2_filter_id = -1;
2809         bnxt_free_filter(bp, filter);
2810         return ret;
2811 }
2812
2813 static int
2814 bnxt_filter_ctrl_op(struct rte_eth_dev *dev __rte_unused,
2815                     enum rte_filter_type filter_type,
2816                     enum rte_filter_op filter_op, void *arg)
2817 {
2818         int ret = 0;
2819
2820         switch (filter_type) {
2821         case RTE_ETH_FILTER_TUNNEL:
2822                 PMD_DRV_LOG(ERR,
2823                         "filter type: %d: To be implemented\n", filter_type);
2824                 break;
2825         case RTE_ETH_FILTER_FDIR:
2826                 ret = bnxt_fdir_filter(dev, filter_op, arg);
2827                 break;
2828         case RTE_ETH_FILTER_NTUPLE:
2829                 ret = bnxt_ntuple_filter(dev, filter_op, arg);
2830                 break;
2831         case RTE_ETH_FILTER_ETHERTYPE:
2832                 ret = bnxt_ethertype_filter(dev, filter_op, arg);
2833                 break;
2834         case RTE_ETH_FILTER_GENERIC:
2835                 if (filter_op != RTE_ETH_FILTER_GET)
2836                         return -EINVAL;
2837                 *(const void **)arg = &bnxt_flow_ops;
2838                 break;
2839         default:
2840                 PMD_DRV_LOG(ERR,
2841                         "Filter type (%d) not supported", filter_type);
2842                 ret = -EINVAL;
2843                 break;
2844         }
2845         return ret;
2846 }
2847
2848 static const uint32_t *
2849 bnxt_dev_supported_ptypes_get_op(struct rte_eth_dev *dev)
2850 {
2851         static const uint32_t ptypes[] = {
2852                 RTE_PTYPE_L2_ETHER_VLAN,
2853                 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN,
2854                 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN,
2855                 RTE_PTYPE_L4_ICMP,
2856                 RTE_PTYPE_L4_TCP,
2857                 RTE_PTYPE_L4_UDP,
2858                 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN,
2859                 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN,
2860                 RTE_PTYPE_INNER_L4_ICMP,
2861                 RTE_PTYPE_INNER_L4_TCP,
2862                 RTE_PTYPE_INNER_L4_UDP,
2863                 RTE_PTYPE_UNKNOWN
2864         };
2865
2866         if (!dev->rx_pkt_burst)
2867                 return NULL;
2868
2869         return ptypes;
2870 }
2871
2872 static int bnxt_map_regs(struct bnxt *bp, uint32_t *reg_arr, int count,
2873                          int reg_win)
2874 {
2875         uint32_t reg_base = *reg_arr & 0xfffff000;
2876         uint32_t win_off;
2877         int i;
2878
2879         for (i = 0; i < count; i++) {
2880                 if ((reg_arr[i] & 0xfffff000) != reg_base)
2881                         return -ERANGE;
2882         }
2883         win_off = BNXT_GRCPF_REG_WINDOW_BASE_OUT + (reg_win - 1) * 4;
2884         rte_write32(reg_base, (uint8_t *)bp->bar0 + win_off);
2885         return 0;
2886 }
2887
2888 static int bnxt_map_ptp_regs(struct bnxt *bp)
2889 {
2890         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
2891         uint32_t *reg_arr;
2892         int rc, i;
2893
2894         reg_arr = ptp->rx_regs;
2895         rc = bnxt_map_regs(bp, reg_arr, BNXT_PTP_RX_REGS, 5);
2896         if (rc)
2897                 return rc;
2898
2899         reg_arr = ptp->tx_regs;
2900         rc = bnxt_map_regs(bp, reg_arr, BNXT_PTP_TX_REGS, 6);
2901         if (rc)
2902                 return rc;
2903
2904         for (i = 0; i < BNXT_PTP_RX_REGS; i++)
2905                 ptp->rx_mapped_regs[i] = 0x5000 + (ptp->rx_regs[i] & 0xfff);
2906
2907         for (i = 0; i < BNXT_PTP_TX_REGS; i++)
2908                 ptp->tx_mapped_regs[i] = 0x6000 + (ptp->tx_regs[i] & 0xfff);
2909
2910         return 0;
2911 }
2912
2913 static void bnxt_unmap_ptp_regs(struct bnxt *bp)
2914 {
2915         rte_write32(0, (uint8_t *)bp->bar0 +
2916                          BNXT_GRCPF_REG_WINDOW_BASE_OUT + 16);
2917         rte_write32(0, (uint8_t *)bp->bar0 +
2918                          BNXT_GRCPF_REG_WINDOW_BASE_OUT + 20);
2919 }
2920
2921 static uint64_t bnxt_cc_read(struct bnxt *bp)
2922 {
2923         uint64_t ns;
2924
2925         ns = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
2926                               BNXT_GRCPF_REG_SYNC_TIME));
2927         ns |= (uint64_t)(rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
2928                                           BNXT_GRCPF_REG_SYNC_TIME + 4))) << 32;
2929         return ns;
2930 }
2931
2932 static int bnxt_get_tx_ts(struct bnxt *bp, uint64_t *ts)
2933 {
2934         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
2935         uint32_t fifo;
2936
2937         fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
2938                                 ptp->tx_mapped_regs[BNXT_PTP_TX_FIFO]));
2939         if (fifo & BNXT_PTP_TX_FIFO_EMPTY)
2940                 return -EAGAIN;
2941
2942         fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
2943                                 ptp->tx_mapped_regs[BNXT_PTP_TX_FIFO]));
2944         *ts = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
2945                                 ptp->tx_mapped_regs[BNXT_PTP_TX_TS_L]));
2946         *ts |= (uint64_t)rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
2947                                 ptp->tx_mapped_regs[BNXT_PTP_TX_TS_H])) << 32;
2948
2949         return 0;
2950 }
2951
2952 static int bnxt_get_rx_ts(struct bnxt *bp, uint64_t *ts)
2953 {
2954         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
2955         struct bnxt_pf_info *pf = &bp->pf;
2956         uint16_t port_id;
2957         uint32_t fifo;
2958
2959         if (!ptp)
2960                 return -ENODEV;
2961
2962         fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
2963                                 ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO]));
2964         if (!(fifo & BNXT_PTP_RX_FIFO_PENDING))
2965                 return -EAGAIN;
2966
2967         port_id = pf->port_id;
2968         rte_write32(1 << port_id, (uint8_t *)bp->bar0 +
2969                ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO_ADV]);
2970
2971         fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
2972                                    ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO]));
2973         if (fifo & BNXT_PTP_RX_FIFO_PENDING) {
2974 /*              bnxt_clr_rx_ts(bp);       TBD  */
2975                 return -EBUSY;
2976         }
2977
2978         *ts = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
2979                                 ptp->rx_mapped_regs[BNXT_PTP_RX_TS_L]));
2980         *ts |= (uint64_t)rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
2981                                 ptp->rx_mapped_regs[BNXT_PTP_RX_TS_H])) << 32;
2982
2983         return 0;
2984 }
2985
2986 static int
2987 bnxt_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
2988 {
2989         uint64_t ns;
2990         struct bnxt *bp = dev->data->dev_private;
2991         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
2992
2993         if (!ptp)
2994                 return 0;
2995
2996         ns = rte_timespec_to_ns(ts);
2997         /* Set the timecounters to a new value. */
2998         ptp->tc.nsec = ns;
2999
3000         return 0;
3001 }
3002
3003 static int
3004 bnxt_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
3005 {
3006         uint64_t ns, systime_cycles;
3007         struct bnxt *bp = dev->data->dev_private;
3008         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3009
3010         if (!ptp)
3011                 return 0;
3012
3013         systime_cycles = bnxt_cc_read(bp);
3014         ns = rte_timecounter_update(&ptp->tc, systime_cycles);
3015         *ts = rte_ns_to_timespec(ns);
3016
3017         return 0;
3018 }
3019 static int
3020 bnxt_timesync_enable(struct rte_eth_dev *dev)
3021 {
3022         struct bnxt *bp = dev->data->dev_private;
3023         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3024         uint32_t shift = 0;
3025
3026         if (!ptp)
3027                 return 0;
3028
3029         ptp->rx_filter = 1;
3030         ptp->tx_tstamp_en = 1;
3031         ptp->rxctl = BNXT_PTP_MSG_EVENTS;
3032
3033         if (!bnxt_hwrm_ptp_cfg(bp))
3034                 bnxt_map_ptp_regs(bp);
3035
3036         memset(&ptp->tc, 0, sizeof(struct rte_timecounter));
3037         memset(&ptp->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
3038         memset(&ptp->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
3039
3040         ptp->tc.cc_mask = BNXT_CYCLECOUNTER_MASK;
3041         ptp->tc.cc_shift = shift;
3042         ptp->tc.nsec_mask = (1ULL << shift) - 1;
3043
3044         ptp->rx_tstamp_tc.cc_mask = BNXT_CYCLECOUNTER_MASK;
3045         ptp->rx_tstamp_tc.cc_shift = shift;
3046         ptp->rx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
3047
3048         ptp->tx_tstamp_tc.cc_mask = BNXT_CYCLECOUNTER_MASK;
3049         ptp->tx_tstamp_tc.cc_shift = shift;
3050         ptp->tx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
3051
3052         return 0;
3053 }
3054
3055 static int
3056 bnxt_timesync_disable(struct rte_eth_dev *dev)
3057 {
3058         struct bnxt *bp = dev->data->dev_private;
3059         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3060
3061         if (!ptp)
3062                 return 0;
3063
3064         ptp->rx_filter = 0;
3065         ptp->tx_tstamp_en = 0;
3066         ptp->rxctl = 0;
3067
3068         bnxt_hwrm_ptp_cfg(bp);
3069
3070         bnxt_unmap_ptp_regs(bp);
3071
3072         return 0;
3073 }
3074
3075 static int
3076 bnxt_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
3077                                  struct timespec *timestamp,
3078                                  uint32_t flags __rte_unused)
3079 {
3080         struct bnxt *bp = dev->data->dev_private;
3081         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3082         uint64_t rx_tstamp_cycles = 0;
3083         uint64_t ns;
3084
3085         if (!ptp)
3086                 return 0;
3087
3088         bnxt_get_rx_ts(bp, &rx_tstamp_cycles);
3089         ns = rte_timecounter_update(&ptp->rx_tstamp_tc, rx_tstamp_cycles);
3090         *timestamp = rte_ns_to_timespec(ns);
3091         return  0;
3092 }
3093
3094 static int
3095 bnxt_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
3096                                  struct timespec *timestamp)
3097 {
3098         struct bnxt *bp = dev->data->dev_private;
3099         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3100         uint64_t tx_tstamp_cycles = 0;
3101         uint64_t ns;
3102
3103         if (!ptp)
3104                 return 0;
3105
3106         bnxt_get_tx_ts(bp, &tx_tstamp_cycles);
3107         ns = rte_timecounter_update(&ptp->tx_tstamp_tc, tx_tstamp_cycles);
3108         *timestamp = rte_ns_to_timespec(ns);
3109
3110         return 0;
3111 }
3112
3113 static int
3114 bnxt_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
3115 {
3116         struct bnxt *bp = dev->data->dev_private;
3117         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3118
3119         if (!ptp)
3120                 return 0;
3121
3122         ptp->tc.nsec += delta;
3123
3124         return 0;
3125 }
3126
3127 static int
3128 bnxt_get_eeprom_length_op(struct rte_eth_dev *dev)
3129 {
3130         struct bnxt *bp = dev->data->dev_private;
3131         int rc;
3132         uint32_t dir_entries;
3133         uint32_t entry_length;
3134
3135         PMD_DRV_LOG(INFO, "%04x:%02x:%02x:%02x\n",
3136                 bp->pdev->addr.domain, bp->pdev->addr.bus,
3137                 bp->pdev->addr.devid, bp->pdev->addr.function);
3138
3139         rc = bnxt_hwrm_nvm_get_dir_info(bp, &dir_entries, &entry_length);
3140         if (rc != 0)
3141                 return rc;
3142
3143         return dir_entries * entry_length;
3144 }
3145
3146 static int
3147 bnxt_get_eeprom_op(struct rte_eth_dev *dev,
3148                 struct rte_dev_eeprom_info *in_eeprom)
3149 {
3150         struct bnxt *bp = dev->data->dev_private;
3151         uint32_t index;
3152         uint32_t offset;
3153
3154         PMD_DRV_LOG(INFO, "%04x:%02x:%02x:%02x in_eeprom->offset = %d "
3155                 "len = %d\n", bp->pdev->addr.domain,
3156                 bp->pdev->addr.bus, bp->pdev->addr.devid,
3157                 bp->pdev->addr.function, in_eeprom->offset, in_eeprom->length);
3158
3159         if (in_eeprom->offset == 0) /* special offset value to get directory */
3160                 return bnxt_get_nvram_directory(bp, in_eeprom->length,
3161                                                 in_eeprom->data);
3162
3163         index = in_eeprom->offset >> 24;
3164         offset = in_eeprom->offset & 0xffffff;
3165
3166         if (index != 0)
3167                 return bnxt_hwrm_get_nvram_item(bp, index - 1, offset,
3168                                            in_eeprom->length, in_eeprom->data);
3169
3170         return 0;
3171 }
3172
3173 static bool bnxt_dir_type_is_ape_bin_format(uint16_t dir_type)
3174 {
3175         switch (dir_type) {
3176         case BNX_DIR_TYPE_CHIMP_PATCH:
3177         case BNX_DIR_TYPE_BOOTCODE:
3178         case BNX_DIR_TYPE_BOOTCODE_2:
3179         case BNX_DIR_TYPE_APE_FW:
3180         case BNX_DIR_TYPE_APE_PATCH:
3181         case BNX_DIR_TYPE_KONG_FW:
3182         case BNX_DIR_TYPE_KONG_PATCH:
3183         case BNX_DIR_TYPE_BONO_FW:
3184         case BNX_DIR_TYPE_BONO_PATCH:
3185                 /* FALLTHROUGH */
3186                 return true;
3187         }
3188
3189         return false;
3190 }
3191
3192 static bool bnxt_dir_type_is_other_exec_format(uint16_t dir_type)
3193 {
3194         switch (dir_type) {
3195         case BNX_DIR_TYPE_AVS:
3196         case BNX_DIR_TYPE_EXP_ROM_MBA:
3197         case BNX_DIR_TYPE_PCIE:
3198         case BNX_DIR_TYPE_TSCF_UCODE:
3199         case BNX_DIR_TYPE_EXT_PHY:
3200         case BNX_DIR_TYPE_CCM:
3201         case BNX_DIR_TYPE_ISCSI_BOOT:
3202         case BNX_DIR_TYPE_ISCSI_BOOT_IPV6:
3203         case BNX_DIR_TYPE_ISCSI_BOOT_IPV4N6:
3204                 /* FALLTHROUGH */
3205                 return true;
3206         }
3207
3208         return false;
3209 }
3210
3211 static bool bnxt_dir_type_is_executable(uint16_t dir_type)
3212 {
3213         return bnxt_dir_type_is_ape_bin_format(dir_type) ||
3214                 bnxt_dir_type_is_other_exec_format(dir_type);
3215 }
3216
3217 static int
3218 bnxt_set_eeprom_op(struct rte_eth_dev *dev,
3219                 struct rte_dev_eeprom_info *in_eeprom)
3220 {
3221         struct bnxt *bp = dev->data->dev_private;
3222         uint8_t index, dir_op;
3223         uint16_t type, ext, ordinal, attr;
3224
3225         PMD_DRV_LOG(INFO, "%04x:%02x:%02x:%02x in_eeprom->offset = %d "
3226                 "len = %d\n", bp->pdev->addr.domain,
3227                 bp->pdev->addr.bus, bp->pdev->addr.devid,
3228                 bp->pdev->addr.function, in_eeprom->offset, in_eeprom->length);
3229
3230         if (!BNXT_PF(bp)) {
3231                 PMD_DRV_LOG(ERR, "NVM write not supported from a VF\n");
3232                 return -EINVAL;
3233         }
3234
3235         type = in_eeprom->magic >> 16;
3236
3237         if (type == 0xffff) { /* special value for directory operations */
3238                 index = in_eeprom->magic & 0xff;
3239                 dir_op = in_eeprom->magic >> 8;
3240                 if (index == 0)
3241                         return -EINVAL;
3242                 switch (dir_op) {
3243                 case 0x0e: /* erase */
3244                         if (in_eeprom->offset != ~in_eeprom->magic)
3245                                 return -EINVAL;
3246                         return bnxt_hwrm_erase_nvram_directory(bp, index - 1);
3247                 default:
3248                         return -EINVAL;
3249                 }
3250         }
3251
3252         /* Create or re-write an NVM item: */
3253         if (bnxt_dir_type_is_executable(type) == true)
3254                 return -EOPNOTSUPP;
3255         ext = in_eeprom->magic & 0xffff;
3256         ordinal = in_eeprom->offset >> 16;
3257         attr = in_eeprom->offset & 0xffff;
3258
3259         return bnxt_hwrm_flash_nvram(bp, type, ordinal, ext, attr,
3260                                      in_eeprom->data, in_eeprom->length);
3261 }
3262
3263 /*
3264  * Initialization
3265  */
3266
3267 static const struct eth_dev_ops bnxt_dev_ops = {
3268         .dev_infos_get = bnxt_dev_info_get_op,
3269         .dev_close = bnxt_dev_close_op,
3270         .dev_configure = bnxt_dev_configure_op,
3271         .dev_start = bnxt_dev_start_op,
3272         .dev_stop = bnxt_dev_stop_op,
3273         .dev_set_link_up = bnxt_dev_set_link_up_op,
3274         .dev_set_link_down = bnxt_dev_set_link_down_op,
3275         .stats_get = bnxt_stats_get_op,
3276         .stats_reset = bnxt_stats_reset_op,
3277         .rx_queue_setup = bnxt_rx_queue_setup_op,
3278         .rx_queue_release = bnxt_rx_queue_release_op,
3279         .tx_queue_setup = bnxt_tx_queue_setup_op,
3280         .tx_queue_release = bnxt_tx_queue_release_op,
3281         .rx_queue_intr_enable = bnxt_rx_queue_intr_enable_op,
3282         .rx_queue_intr_disable = bnxt_rx_queue_intr_disable_op,
3283         .reta_update = bnxt_reta_update_op,
3284         .reta_query = bnxt_reta_query_op,
3285         .rss_hash_update = bnxt_rss_hash_update_op,
3286         .rss_hash_conf_get = bnxt_rss_hash_conf_get_op,
3287         .link_update = bnxt_link_update_op,
3288         .promiscuous_enable = bnxt_promiscuous_enable_op,
3289         .promiscuous_disable = bnxt_promiscuous_disable_op,
3290         .allmulticast_enable = bnxt_allmulticast_enable_op,
3291         .allmulticast_disable = bnxt_allmulticast_disable_op,
3292         .mac_addr_add = bnxt_mac_addr_add_op,
3293         .mac_addr_remove = bnxt_mac_addr_remove_op,
3294         .flow_ctrl_get = bnxt_flow_ctrl_get_op,
3295         .flow_ctrl_set = bnxt_flow_ctrl_set_op,
3296         .udp_tunnel_port_add  = bnxt_udp_tunnel_port_add_op,
3297         .udp_tunnel_port_del  = bnxt_udp_tunnel_port_del_op,
3298         .vlan_filter_set = bnxt_vlan_filter_set_op,
3299         .vlan_offload_set = bnxt_vlan_offload_set_op,
3300         .vlan_pvid_set = bnxt_vlan_pvid_set_op,
3301         .mtu_set = bnxt_mtu_set_op,
3302         .mac_addr_set = bnxt_set_default_mac_addr_op,
3303         .xstats_get = bnxt_dev_xstats_get_op,
3304         .xstats_get_names = bnxt_dev_xstats_get_names_op,
3305         .xstats_reset = bnxt_dev_xstats_reset_op,
3306         .fw_version_get = bnxt_fw_version_get,
3307         .set_mc_addr_list = bnxt_dev_set_mc_addr_list_op,
3308         .rxq_info_get = bnxt_rxq_info_get_op,
3309         .txq_info_get = bnxt_txq_info_get_op,
3310         .dev_led_on = bnxt_dev_led_on_op,
3311         .dev_led_off = bnxt_dev_led_off_op,
3312         .xstats_get_by_id = bnxt_dev_xstats_get_by_id_op,
3313         .xstats_get_names_by_id = bnxt_dev_xstats_get_names_by_id_op,
3314         .rx_queue_count = bnxt_rx_queue_count_op,
3315         .rx_descriptor_status = bnxt_rx_descriptor_status_op,
3316         .tx_descriptor_status = bnxt_tx_descriptor_status_op,
3317         .rx_queue_start = bnxt_rx_queue_start,
3318         .rx_queue_stop = bnxt_rx_queue_stop,
3319         .tx_queue_start = bnxt_tx_queue_start,
3320         .tx_queue_stop = bnxt_tx_queue_stop,
3321         .filter_ctrl = bnxt_filter_ctrl_op,
3322         .dev_supported_ptypes_get = bnxt_dev_supported_ptypes_get_op,
3323         .get_eeprom_length    = bnxt_get_eeprom_length_op,
3324         .get_eeprom           = bnxt_get_eeprom_op,
3325         .set_eeprom           = bnxt_set_eeprom_op,
3326         .timesync_enable      = bnxt_timesync_enable,
3327         .timesync_disable     = bnxt_timesync_disable,
3328         .timesync_read_time   = bnxt_timesync_read_time,
3329         .timesync_write_time   = bnxt_timesync_write_time,
3330         .timesync_adjust_time = bnxt_timesync_adjust_time,
3331         .timesync_read_rx_timestamp = bnxt_timesync_read_rx_timestamp,
3332         .timesync_read_tx_timestamp = bnxt_timesync_read_tx_timestamp,
3333 };
3334
3335 static bool bnxt_vf_pciid(uint16_t id)
3336 {
3337         if (id == BROADCOM_DEV_ID_57304_VF ||
3338             id == BROADCOM_DEV_ID_57406_VF ||
3339             id == BROADCOM_DEV_ID_5731X_VF ||
3340             id == BROADCOM_DEV_ID_5741X_VF ||
3341             id == BROADCOM_DEV_ID_57414_VF ||
3342             id == BROADCOM_DEV_ID_STRATUS_NIC_VF1 ||
3343             id == BROADCOM_DEV_ID_STRATUS_NIC_VF2 ||
3344             id == BROADCOM_DEV_ID_58802_VF ||
3345             id == BROADCOM_DEV_ID_57500_VF1 ||
3346             id == BROADCOM_DEV_ID_57500_VF2)
3347                 return true;
3348         return false;
3349 }
3350
3351 bool bnxt_stratus_device(struct bnxt *bp)
3352 {
3353         uint16_t id = bp->pdev->id.device_id;
3354
3355         if (id == BROADCOM_DEV_ID_STRATUS_NIC ||
3356             id == BROADCOM_DEV_ID_STRATUS_NIC_VF1 ||
3357             id == BROADCOM_DEV_ID_STRATUS_NIC_VF2)
3358                 return true;
3359         return false;
3360 }
3361
3362 static int bnxt_init_board(struct rte_eth_dev *eth_dev)
3363 {
3364         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
3365         struct bnxt *bp = eth_dev->data->dev_private;
3366
3367         /* enable device (incl. PCI PM wakeup), and bus-mastering */
3368         bp->bar0 = (void *)pci_dev->mem_resource[0].addr;
3369         bp->doorbell_base = (void *)pci_dev->mem_resource[2].addr;
3370         if (!bp->bar0 || !bp->doorbell_base) {
3371                 PMD_DRV_LOG(ERR, "Unable to access Hardware\n");
3372                 return -ENODEV;
3373         }
3374
3375         bp->eth_dev = eth_dev;
3376         bp->pdev = pci_dev;
3377
3378         return 0;
3379 }
3380
3381 static int bnxt_alloc_ctx_mem_blk(__rte_unused struct bnxt *bp,
3382                                   struct bnxt_ctx_pg_info *ctx_pg,
3383                                   uint32_t mem_size,
3384                                   const char *suffix,
3385                                   uint16_t idx)
3386 {
3387         struct bnxt_ring_mem_info *rmem = &ctx_pg->ring_mem;
3388         const struct rte_memzone *mz = NULL;
3389         char mz_name[RTE_MEMZONE_NAMESIZE];
3390         rte_iova_t mz_phys_addr;
3391         uint64_t valid_bits = 0;
3392         uint32_t sz;
3393         int i;
3394
3395         if (!mem_size)
3396                 return 0;
3397
3398         rmem->nr_pages = RTE_ALIGN_MUL_CEIL(mem_size, BNXT_PAGE_SIZE) /
3399                          BNXT_PAGE_SIZE;
3400         rmem->page_size = BNXT_PAGE_SIZE;
3401         rmem->pg_arr = ctx_pg->ctx_pg_arr;
3402         rmem->dma_arr = ctx_pg->ctx_dma_arr;
3403         rmem->flags = BNXT_RMEM_VALID_PTE_FLAG;
3404
3405         valid_bits = PTU_PTE_VALID;
3406
3407         if (rmem->nr_pages > 1) {
3408                 snprintf(mz_name, RTE_MEMZONE_NAMESIZE,
3409                          "bnxt_ctx_pg_tbl%s_%x_%d",
3410                          suffix, idx, bp->eth_dev->data->port_id);
3411                 mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0;
3412                 mz = rte_memzone_lookup(mz_name);
3413                 if (!mz) {
3414                         mz = rte_memzone_reserve_aligned(mz_name,
3415                                                 rmem->nr_pages * 8,
3416                                                 SOCKET_ID_ANY,
3417                                                 RTE_MEMZONE_2MB |
3418                                                 RTE_MEMZONE_SIZE_HINT_ONLY |
3419                                                 RTE_MEMZONE_IOVA_CONTIG,
3420                                                 BNXT_PAGE_SIZE);
3421                         if (mz == NULL)
3422                                 return -ENOMEM;
3423                 }
3424
3425                 memset(mz->addr, 0, mz->len);
3426                 mz_phys_addr = mz->iova;
3427                 if ((unsigned long)mz->addr == mz_phys_addr) {
3428                         PMD_DRV_LOG(WARNING,
3429                                 "Memzone physical address same as virtual.\n");
3430                         PMD_DRV_LOG(WARNING,
3431                                     "Using rte_mem_virt2iova()\n");
3432                         mz_phys_addr = rte_mem_virt2iova(mz->addr);
3433                         if (mz_phys_addr == RTE_BAD_IOVA) {
3434                                 PMD_DRV_LOG(ERR,
3435                                         "unable to map addr to phys memory\n");
3436                                 return -ENOMEM;
3437                         }
3438                 }
3439                 rte_mem_lock_page(((char *)mz->addr));
3440
3441                 rmem->pg_tbl = mz->addr;
3442                 rmem->pg_tbl_map = mz_phys_addr;
3443                 rmem->pg_tbl_mz = mz;
3444         }
3445
3446         snprintf(mz_name, RTE_MEMZONE_NAMESIZE, "bnxt_ctx_%s_%x_%d",
3447                  suffix, idx, bp->eth_dev->data->port_id);
3448         mz = rte_memzone_lookup(mz_name);
3449         if (!mz) {
3450                 mz = rte_memzone_reserve_aligned(mz_name,
3451                                                  mem_size,
3452                                                  SOCKET_ID_ANY,
3453                                                  RTE_MEMZONE_1GB |
3454                                                  RTE_MEMZONE_SIZE_HINT_ONLY |
3455                                                  RTE_MEMZONE_IOVA_CONTIG,
3456                                                  BNXT_PAGE_SIZE);
3457                 if (mz == NULL)
3458                         return -ENOMEM;
3459         }
3460
3461         memset(mz->addr, 0, mz->len);
3462         mz_phys_addr = mz->iova;
3463         if ((unsigned long)mz->addr == mz_phys_addr) {
3464                 PMD_DRV_LOG(WARNING,
3465                             "Memzone physical address same as virtual.\n");
3466                 PMD_DRV_LOG(WARNING,
3467                             "Using rte_mem_virt2iova()\n");
3468                 for (sz = 0; sz < mem_size; sz += BNXT_PAGE_SIZE)
3469                         rte_mem_lock_page(((char *)mz->addr) + sz);
3470                 mz_phys_addr = rte_mem_virt2iova(mz->addr);
3471                 if (mz_phys_addr == RTE_BAD_IOVA) {
3472                         PMD_DRV_LOG(ERR,
3473                                     "unable to map addr to phys memory\n");
3474                         return -ENOMEM;
3475                 }
3476         }
3477
3478         for (sz = 0, i = 0; sz < mem_size; sz += BNXT_PAGE_SIZE, i++) {
3479                 rte_mem_lock_page(((char *)mz->addr) + sz);
3480                 rmem->pg_arr[i] = ((char *)mz->addr) + sz;
3481                 rmem->dma_arr[i] = mz_phys_addr + sz;
3482
3483                 if (rmem->nr_pages > 1) {
3484                         if (i == rmem->nr_pages - 2 &&
3485                             (rmem->flags & BNXT_RMEM_RING_PTE_FLAG))
3486                                 valid_bits |= PTU_PTE_NEXT_TO_LAST;
3487                         else if (i == rmem->nr_pages - 1 &&
3488                                  (rmem->flags & BNXT_RMEM_RING_PTE_FLAG))
3489                                 valid_bits |= PTU_PTE_LAST;
3490
3491                         rmem->pg_tbl[i] = rte_cpu_to_le_64(rmem->dma_arr[i] |
3492                                                            valid_bits);
3493                 }
3494         }
3495
3496         rmem->mz = mz;
3497         if (rmem->vmem_size)
3498                 rmem->vmem = (void **)mz->addr;
3499         rmem->dma_arr[0] = mz_phys_addr;
3500         return 0;
3501 }
3502
3503 static void bnxt_free_ctx_mem(struct bnxt *bp)
3504 {
3505         int i;
3506
3507         if (!bp->ctx || !(bp->ctx->flags & BNXT_CTX_FLAG_INITED))
3508                 return;
3509
3510         bp->ctx->flags &= ~BNXT_CTX_FLAG_INITED;
3511         rte_memzone_free(bp->ctx->qp_mem.ring_mem.mz);
3512         rte_memzone_free(bp->ctx->srq_mem.ring_mem.mz);
3513         rte_memzone_free(bp->ctx->cq_mem.ring_mem.mz);
3514         rte_memzone_free(bp->ctx->vnic_mem.ring_mem.mz);
3515         rte_memzone_free(bp->ctx->stat_mem.ring_mem.mz);
3516         rte_memzone_free(bp->ctx->qp_mem.ring_mem.pg_tbl_mz);
3517         rte_memzone_free(bp->ctx->srq_mem.ring_mem.pg_tbl_mz);
3518         rte_memzone_free(bp->ctx->cq_mem.ring_mem.pg_tbl_mz);
3519         rte_memzone_free(bp->ctx->vnic_mem.ring_mem.pg_tbl_mz);
3520         rte_memzone_free(bp->ctx->stat_mem.ring_mem.pg_tbl_mz);
3521
3522         for (i = 0; i < BNXT_MAX_Q; i++) {
3523                 if (bp->ctx->tqm_mem[i])
3524                         rte_memzone_free(bp->ctx->tqm_mem[i]->ring_mem.mz);
3525         }
3526
3527         rte_free(bp->ctx);
3528         bp->ctx = NULL;
3529 }
3530
3531 #define bnxt_roundup(x, y)   ((((x) + ((y) - 1)) / (y)) * (y))
3532
3533 #define min_t(type, x, y) ({                    \
3534         type __min1 = (x);                      \
3535         type __min2 = (y);                      \
3536         __min1 < __min2 ? __min1 : __min2; })
3537
3538 #define max_t(type, x, y) ({                    \
3539         type __max1 = (x);                      \
3540         type __max2 = (y);                      \
3541         __max1 > __max2 ? __max1 : __max2; })
3542
3543 #define clamp_t(type, _x, min, max)     min_t(type, max_t(type, _x, min), max)
3544
3545 int bnxt_alloc_ctx_mem(struct bnxt *bp)
3546 {
3547         struct bnxt_ctx_pg_info *ctx_pg;
3548         struct bnxt_ctx_mem_info *ctx;
3549         uint32_t mem_size, ena, entries;
3550         int i, rc;
3551
3552         rc = bnxt_hwrm_func_backing_store_qcaps(bp);
3553         if (rc) {
3554                 PMD_DRV_LOG(ERR, "Query context mem capability failed\n");
3555                 return rc;
3556         }
3557         ctx = bp->ctx;
3558         if (!ctx || (ctx->flags & BNXT_CTX_FLAG_INITED))
3559                 return 0;
3560
3561         ctx_pg = &ctx->qp_mem;
3562         ctx_pg->entries = ctx->qp_min_qp1_entries + ctx->qp_max_l2_entries;
3563         mem_size = ctx->qp_entry_size * ctx_pg->entries;
3564         rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "qp_mem", 0);
3565         if (rc)
3566                 return rc;
3567
3568         ctx_pg = &ctx->srq_mem;
3569         ctx_pg->entries = ctx->srq_max_l2_entries;
3570         mem_size = ctx->srq_entry_size * ctx_pg->entries;
3571         rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "srq_mem", 0);
3572         if (rc)
3573                 return rc;
3574
3575         ctx_pg = &ctx->cq_mem;
3576         ctx_pg->entries = ctx->cq_max_l2_entries;
3577         mem_size = ctx->cq_entry_size * ctx_pg->entries;
3578         rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "cq_mem", 0);
3579         if (rc)
3580                 return rc;
3581
3582         ctx_pg = &ctx->vnic_mem;
3583         ctx_pg->entries = ctx->vnic_max_vnic_entries +
3584                 ctx->vnic_max_ring_table_entries;
3585         mem_size = ctx->vnic_entry_size * ctx_pg->entries;
3586         rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "vnic_mem", 0);
3587         if (rc)
3588                 return rc;
3589
3590         ctx_pg = &ctx->stat_mem;
3591         ctx_pg->entries = ctx->stat_max_entries;
3592         mem_size = ctx->stat_entry_size * ctx_pg->entries;
3593         rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "stat_mem", 0);
3594         if (rc)
3595                 return rc;
3596
3597         entries = ctx->qp_max_l2_entries;
3598         entries = bnxt_roundup(entries, ctx->tqm_entries_multiple);
3599         entries = clamp_t(uint32_t, entries, ctx->tqm_min_entries_per_ring,
3600                           ctx->tqm_max_entries_per_ring);
3601         for (i = 0, ena = 0; i < BNXT_MAX_Q; i++) {
3602                 ctx_pg = ctx->tqm_mem[i];
3603                 /* use min tqm entries for now. */
3604                 ctx_pg->entries = entries;
3605                 mem_size = ctx->tqm_entry_size * ctx_pg->entries;
3606                 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "tqm_mem", i);
3607                 if (rc)
3608                         return rc;
3609                 ena |= HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_SP << i;
3610         }
3611
3612         ena |= FUNC_BACKING_STORE_CFG_INPUT_DFLT_ENABLES;
3613         rc = bnxt_hwrm_func_backing_store_cfg(bp, ena);
3614         if (rc)
3615                 PMD_DRV_LOG(ERR,
3616                             "Failed to configure context mem: rc = %d\n", rc);
3617         else
3618                 ctx->flags |= BNXT_CTX_FLAG_INITED;
3619
3620         return rc;
3621 }
3622
3623 static int bnxt_alloc_stats_mem(struct bnxt *bp)
3624 {
3625         struct rte_pci_device *pci_dev = bp->pdev;
3626         char mz_name[RTE_MEMZONE_NAMESIZE];
3627         const struct rte_memzone *mz = NULL;
3628         uint32_t total_alloc_len;
3629         rte_iova_t mz_phys_addr;
3630
3631         if (pci_dev->id.device_id == BROADCOM_DEV_ID_NS2)
3632                 return 0;
3633
3634         snprintf(mz_name, RTE_MEMZONE_NAMESIZE,
3635                  "bnxt_" PCI_PRI_FMT "-%s", pci_dev->addr.domain,
3636                  pci_dev->addr.bus, pci_dev->addr.devid,
3637                  pci_dev->addr.function, "rx_port_stats");
3638         mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0;
3639         mz = rte_memzone_lookup(mz_name);
3640         total_alloc_len =
3641                 RTE_CACHE_LINE_ROUNDUP(sizeof(struct rx_port_stats) +
3642                                        sizeof(struct rx_port_stats_ext) + 512);
3643         if (!mz) {
3644                 mz = rte_memzone_reserve(mz_name, total_alloc_len,
3645                                          SOCKET_ID_ANY,
3646                                          RTE_MEMZONE_2MB |
3647                                          RTE_MEMZONE_SIZE_HINT_ONLY |
3648                                          RTE_MEMZONE_IOVA_CONTIG);
3649                 if (mz == NULL)
3650                         return -ENOMEM;
3651         }
3652         memset(mz->addr, 0, mz->len);
3653         mz_phys_addr = mz->iova;
3654         if ((unsigned long)mz->addr == mz_phys_addr) {
3655                 PMD_DRV_LOG(WARNING,
3656                             "Memzone physical address same as virtual.\n");
3657                 PMD_DRV_LOG(WARNING,
3658                             "Using rte_mem_virt2iova()\n");
3659                 mz_phys_addr = rte_mem_virt2iova(mz->addr);
3660                 if (mz_phys_addr == RTE_BAD_IOVA) {
3661                         PMD_DRV_LOG(ERR,
3662                                     "Can't map address to physical memory\n");
3663                         return -ENOMEM;
3664                 }
3665         }
3666
3667         bp->rx_mem_zone = (const void *)mz;
3668         bp->hw_rx_port_stats = mz->addr;
3669         bp->hw_rx_port_stats_map = mz_phys_addr;
3670
3671         snprintf(mz_name, RTE_MEMZONE_NAMESIZE,
3672                  "bnxt_" PCI_PRI_FMT "-%s", pci_dev->addr.domain,
3673                  pci_dev->addr.bus, pci_dev->addr.devid,
3674                  pci_dev->addr.function, "tx_port_stats");
3675         mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0;
3676         mz = rte_memzone_lookup(mz_name);
3677         total_alloc_len =
3678                 RTE_CACHE_LINE_ROUNDUP(sizeof(struct tx_port_stats) +
3679                                        sizeof(struct tx_port_stats_ext) + 512);
3680         if (!mz) {
3681                 mz = rte_memzone_reserve(mz_name,
3682                                          total_alloc_len,
3683                                          SOCKET_ID_ANY,
3684                                          RTE_MEMZONE_2MB |
3685                                          RTE_MEMZONE_SIZE_HINT_ONLY |
3686                                          RTE_MEMZONE_IOVA_CONTIG);
3687                 if (mz == NULL)
3688                         return -ENOMEM;
3689         }
3690         memset(mz->addr, 0, mz->len);
3691         mz_phys_addr = mz->iova;
3692         if ((unsigned long)mz->addr == mz_phys_addr) {
3693                 PMD_DRV_LOG(WARNING,
3694                             "Memzone physical address same as virtual\n");
3695                 PMD_DRV_LOG(WARNING,
3696                             "Using rte_mem_virt2iova()\n");
3697                 mz_phys_addr = rte_mem_virt2iova(mz->addr);
3698                 if (mz_phys_addr == RTE_BAD_IOVA) {
3699                         PMD_DRV_LOG(ERR,
3700                                     "Can't map address to physical memory\n");
3701                         return -ENOMEM;
3702                 }
3703         }
3704
3705         bp->tx_mem_zone = (const void *)mz;
3706         bp->hw_tx_port_stats = mz->addr;
3707         bp->hw_tx_port_stats_map = mz_phys_addr;
3708         bp->flags |= BNXT_FLAG_PORT_STATS;
3709
3710         /* Display extended statistics if FW supports it */
3711         if (bp->hwrm_spec_code < HWRM_SPEC_CODE_1_8_4 ||
3712             bp->hwrm_spec_code == HWRM_SPEC_CODE_1_9_0 ||
3713             !(bp->flags & BNXT_FLAG_EXT_STATS_SUPPORTED))
3714                 return 0;
3715
3716         bp->hw_rx_port_stats_ext = (void *)
3717                 ((uint8_t *)bp->hw_rx_port_stats +
3718                  sizeof(struct rx_port_stats));
3719         bp->hw_rx_port_stats_ext_map = bp->hw_rx_port_stats_map +
3720                 sizeof(struct rx_port_stats);
3721         bp->flags |= BNXT_FLAG_EXT_RX_PORT_STATS;
3722
3723         if (bp->hwrm_spec_code < HWRM_SPEC_CODE_1_9_2 ||
3724             bp->flags & BNXT_FLAG_EXT_STATS_SUPPORTED) {
3725                 bp->hw_tx_port_stats_ext = (void *)
3726                         ((uint8_t *)bp->hw_tx_port_stats +
3727                          sizeof(struct tx_port_stats));
3728                 bp->hw_tx_port_stats_ext_map =
3729                         bp->hw_tx_port_stats_map +
3730                         sizeof(struct tx_port_stats);
3731                 bp->flags |= BNXT_FLAG_EXT_TX_PORT_STATS;
3732         }
3733
3734         return 0;
3735 }
3736
3737 static int bnxt_setup_mac_addr(struct rte_eth_dev *eth_dev)
3738 {
3739         struct bnxt *bp = eth_dev->data->dev_private;
3740         int rc = 0;
3741
3742         eth_dev->data->mac_addrs = rte_zmalloc("bnxt_mac_addr_tbl",
3743                                                RTE_ETHER_ADDR_LEN *
3744                                                bp->max_l2_ctx,
3745                                                0);
3746         if (eth_dev->data->mac_addrs == NULL) {
3747                 PMD_DRV_LOG(ERR, "Failed to alloc MAC addr tbl\n");
3748                 return -ENOMEM;
3749         }
3750
3751         if (bnxt_check_zero_bytes(bp->dflt_mac_addr, RTE_ETHER_ADDR_LEN)) {
3752                 if (BNXT_PF(bp))
3753                         return -EINVAL;
3754
3755                 /* Generate a random MAC address, if none was assigned by PF */
3756                 PMD_DRV_LOG(INFO, "VF MAC address not assigned by Host PF\n");
3757                 bnxt_eth_hw_addr_random(bp->mac_addr);
3758                 PMD_DRV_LOG(INFO,
3759                             "Assign random MAC:%02X:%02X:%02X:%02X:%02X:%02X\n",
3760                             bp->mac_addr[0], bp->mac_addr[1], bp->mac_addr[2],
3761                             bp->mac_addr[3], bp->mac_addr[4], bp->mac_addr[5]);
3762
3763                 rc = bnxt_hwrm_set_mac(bp);
3764                 if (!rc)
3765                         memcpy(&bp->eth_dev->data->mac_addrs[0], bp->mac_addr,
3766                                RTE_ETHER_ADDR_LEN);
3767                 return rc;
3768         }
3769
3770         /* Copy the permanent MAC from the FUNC_QCAPS response */
3771         memcpy(bp->mac_addr, bp->dflt_mac_addr, RTE_ETHER_ADDR_LEN);
3772         memcpy(&eth_dev->data->mac_addrs[0], bp->mac_addr, RTE_ETHER_ADDR_LEN);
3773
3774         return rc;
3775 }
3776
3777 #define ALLOW_FUNC(x)   \
3778         { \
3779                 uint32_t arg = (x); \
3780                 bp->pf.vf_req_fwd[((arg) >> 5)] &= \
3781                 ~rte_cpu_to_le_32(1 << ((arg) & 0x1f)); \
3782         }
3783 static int
3784 bnxt_dev_init(struct rte_eth_dev *eth_dev)
3785 {
3786         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
3787         static int version_printed;
3788         struct bnxt *bp;
3789         uint16_t mtu;
3790         int rc;
3791
3792         if (version_printed++ == 0)
3793                 PMD_DRV_LOG(INFO, "%s\n", bnxt_version);
3794
3795         rte_eth_copy_pci_info(eth_dev, pci_dev);
3796
3797         bp = eth_dev->data->dev_private;
3798
3799         bp->dev_stopped = 1;
3800
3801         eth_dev->dev_ops = &bnxt_dev_ops;
3802         eth_dev->rx_pkt_burst = &bnxt_recv_pkts;
3803         eth_dev->tx_pkt_burst = &bnxt_xmit_pkts;
3804
3805         /*
3806          * For secondary processes, we don't initialise any further
3807          * as primary has already done this work.
3808          */
3809         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
3810                 return 0;
3811
3812         if (bnxt_vf_pciid(pci_dev->id.device_id))
3813                 bp->flags |= BNXT_FLAG_VF;
3814
3815         if (pci_dev->id.device_id == BROADCOM_DEV_ID_57508 ||
3816             pci_dev->id.device_id == BROADCOM_DEV_ID_57504 ||
3817             pci_dev->id.device_id == BROADCOM_DEV_ID_57502 ||
3818             pci_dev->id.device_id == BROADCOM_DEV_ID_57500_VF1 ||
3819             pci_dev->id.device_id == BROADCOM_DEV_ID_57500_VF2)
3820                 bp->flags |= BNXT_FLAG_THOR_CHIP;
3821
3822         if (pci_dev->id.device_id == BROADCOM_DEV_ID_58802 ||
3823             pci_dev->id.device_id == BROADCOM_DEV_ID_58804 ||
3824             pci_dev->id.device_id == BROADCOM_DEV_ID_58808 ||
3825             pci_dev->id.device_id == BROADCOM_DEV_ID_58802_VF)
3826                 bp->flags |= BNXT_FLAG_STINGRAY;
3827
3828         rc = bnxt_init_board(eth_dev);
3829         if (rc) {
3830                 PMD_DRV_LOG(ERR,
3831                         "Board initialization failed rc: %x\n", rc);
3832                 goto error;
3833         }
3834
3835         rc = bnxt_alloc_hwrm_resources(bp);
3836         if (rc) {
3837                 PMD_DRV_LOG(ERR,
3838                         "hwrm resource allocation failure rc: %x\n", rc);
3839                 goto error_free;
3840         }
3841         rc = bnxt_hwrm_ver_get(bp);
3842         if (rc)
3843                 goto error_free;
3844
3845         rc = bnxt_hwrm_func_reset(bp);
3846         if (rc) {
3847                 PMD_DRV_LOG(ERR, "hwrm chip reset failure rc: %x\n", rc);
3848                 rc = -EIO;
3849                 goto error_free;
3850         }
3851
3852         rc = bnxt_hwrm_queue_qportcfg(bp);
3853         if (rc) {
3854                 PMD_DRV_LOG(ERR, "hwrm queue qportcfg failed\n");
3855                 goto error_free;
3856         }
3857         /* Get the MAX capabilities for this function */
3858         rc = bnxt_hwrm_func_qcaps(bp);
3859         if (rc) {
3860                 PMD_DRV_LOG(ERR, "hwrm query capability failure rc: %x\n", rc);
3861                 goto error_free;
3862         }
3863
3864         rc = bnxt_alloc_stats_mem(bp);
3865         if (rc)
3866                 goto error_free;
3867
3868         if (bp->max_tx_rings == 0) {
3869                 PMD_DRV_LOG(ERR, "No TX rings available!\n");
3870                 rc = -EBUSY;
3871                 goto error_free;
3872         }
3873
3874         rc = bnxt_setup_mac_addr(eth_dev);
3875         if (rc)
3876                 goto error_free;
3877
3878         /* THOR does not support ring groups.
3879          * But we will use the array to save RSS context IDs.
3880          */
3881         if (BNXT_CHIP_THOR(bp)) {
3882                 bp->max_ring_grps = BNXT_MAX_RSS_CTXTS_THOR;
3883         } else if (bp->max_ring_grps < bp->rx_cp_nr_rings) {
3884                 /* 1 ring is for default completion ring */
3885                 PMD_DRV_LOG(ERR, "Insufficient resource: Ring Group\n");
3886                 rc = -ENOSPC;
3887                 goto error_free;
3888         }
3889
3890         if (BNXT_HAS_RING_GRPS(bp)) {
3891                 bp->grp_info = rte_zmalloc("bnxt_grp_info",
3892                                         sizeof(*bp->grp_info) *
3893                                                 bp->max_ring_grps, 0);
3894                 if (!bp->grp_info) {
3895                         PMD_DRV_LOG(ERR,
3896                                 "Failed to alloc %zu bytes for grp info tbl.\n",
3897                                 sizeof(*bp->grp_info) * bp->max_ring_grps);
3898                         rc = -ENOMEM;
3899                         goto error_free;
3900                 }
3901         }
3902
3903         /* Forward all requests if firmware is new enough */
3904         if (((bp->fw_ver >= ((20 << 24) | (6 << 16) | (100 << 8))) &&
3905             (bp->fw_ver < ((20 << 24) | (7 << 16)))) ||
3906             ((bp->fw_ver >= ((20 << 24) | (8 << 16))))) {
3907                 memset(bp->pf.vf_req_fwd, 0xff, sizeof(bp->pf.vf_req_fwd));
3908         } else {
3909                 PMD_DRV_LOG(WARNING,
3910                         "Firmware too old for VF mailbox functionality\n");
3911                 memset(bp->pf.vf_req_fwd, 0, sizeof(bp->pf.vf_req_fwd));
3912         }
3913
3914         /*
3915          * The following are used for driver cleanup.  If we disallow these,
3916          * VF drivers can't clean up cleanly.
3917          */
3918         ALLOW_FUNC(HWRM_FUNC_DRV_UNRGTR);
3919         ALLOW_FUNC(HWRM_VNIC_FREE);
3920         ALLOW_FUNC(HWRM_RING_FREE);
3921         ALLOW_FUNC(HWRM_RING_GRP_FREE);
3922         ALLOW_FUNC(HWRM_VNIC_RSS_COS_LB_CTX_FREE);
3923         ALLOW_FUNC(HWRM_CFA_L2_FILTER_FREE);
3924         ALLOW_FUNC(HWRM_STAT_CTX_FREE);
3925         ALLOW_FUNC(HWRM_PORT_PHY_QCFG);
3926         ALLOW_FUNC(HWRM_VNIC_TPA_CFG);
3927         rc = bnxt_hwrm_func_driver_register(bp);
3928         if (rc) {
3929                 PMD_DRV_LOG(ERR,
3930                         "Failed to register driver");
3931                 rc = -EBUSY;
3932                 goto error_free;
3933         }
3934
3935         PMD_DRV_LOG(INFO,
3936                 DRV_MODULE_NAME " found at mem %" PRIx64 ", node addr %pM\n",
3937                 pci_dev->mem_resource[0].phys_addr,
3938                 pci_dev->mem_resource[0].addr);
3939
3940         rc = bnxt_hwrm_func_qcfg(bp, &mtu);
3941         if (rc) {
3942                 PMD_DRV_LOG(ERR, "hwrm func qcfg failed\n");
3943                 goto error_free;
3944         }
3945
3946         if (mtu >= RTE_ETHER_MIN_MTU && mtu <= BNXT_MAX_MTU &&
3947             mtu != eth_dev->data->mtu)
3948                 eth_dev->data->mtu = mtu;
3949
3950         if (BNXT_PF(bp)) {
3951                 //if (bp->pf.active_vfs) {
3952                         // TODO: Deallocate VF resources?
3953                 //}
3954                 if (bp->pdev->max_vfs) {
3955                         rc = bnxt_hwrm_allocate_vfs(bp, bp->pdev->max_vfs);
3956                         if (rc) {
3957                                 PMD_DRV_LOG(ERR, "Failed to allocate VFs\n");
3958                                 goto error_free;
3959                         }
3960                 } else {
3961                         rc = bnxt_hwrm_allocate_pf_only(bp);
3962                         if (rc) {
3963                                 PMD_DRV_LOG(ERR,
3964                                         "Failed to allocate PF resources\n");
3965                                 goto error_free;
3966                         }
3967                 }
3968         }
3969
3970         bnxt_hwrm_port_led_qcaps(bp);
3971
3972         rc = bnxt_setup_int(bp);
3973         if (rc)
3974                 goto error_free;
3975
3976         rc = bnxt_alloc_mem(bp);
3977         if (rc)
3978                 goto error_free;
3979
3980         bnxt_init_nic(bp);
3981
3982         rc = bnxt_request_int(bp);
3983         if (rc)
3984                 goto error_free;
3985
3986         return 0;
3987
3988 error_free:
3989         bnxt_dev_uninit(eth_dev);
3990 error:
3991         return rc;
3992 }
3993
3994 static int
3995 bnxt_dev_uninit(struct rte_eth_dev *eth_dev)
3996 {
3997         struct bnxt *bp = eth_dev->data->dev_private;
3998         int rc;
3999
4000         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
4001                 return -EPERM;
4002
4003         PMD_DRV_LOG(DEBUG, "Calling Device uninit\n");
4004         bnxt_disable_int(bp);
4005         bnxt_free_int(bp);
4006         bnxt_free_mem(bp);
4007
4008         bnxt_hwrm_func_buf_unrgtr(bp);
4009
4010         if (bp->grp_info != NULL) {
4011                 rte_free(bp->grp_info);
4012                 bp->grp_info = NULL;
4013         }
4014         rc = bnxt_hwrm_func_driver_unregister(bp, 0);
4015         bnxt_free_hwrm_resources(bp);
4016
4017         if (bp->tx_mem_zone) {
4018                 rte_memzone_free((const struct rte_memzone *)bp->tx_mem_zone);
4019                 bp->tx_mem_zone = NULL;
4020         }
4021
4022         if (bp->rx_mem_zone) {
4023                 rte_memzone_free((const struct rte_memzone *)bp->rx_mem_zone);
4024                 bp->rx_mem_zone = NULL;
4025         }
4026
4027         if (bp->dev_stopped == 0)
4028                 bnxt_dev_close_op(eth_dev);
4029         if (bp->pf.vf_info)
4030                 rte_free(bp->pf.vf_info);
4031         bnxt_free_ctx_mem(bp);
4032         eth_dev->dev_ops = NULL;
4033         eth_dev->rx_pkt_burst = NULL;
4034         eth_dev->tx_pkt_burst = NULL;
4035
4036         return rc;
4037 }
4038
4039 static int bnxt_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
4040         struct rte_pci_device *pci_dev)
4041 {
4042         return rte_eth_dev_pci_generic_probe(pci_dev, sizeof(struct bnxt),
4043                 bnxt_dev_init);
4044 }
4045
4046 static int bnxt_pci_remove(struct rte_pci_device *pci_dev)
4047 {
4048         if (rte_eal_process_type() == RTE_PROC_PRIMARY)
4049                 return rte_eth_dev_pci_generic_remove(pci_dev,
4050                                 bnxt_dev_uninit);
4051         else
4052                 return rte_eth_dev_pci_generic_remove(pci_dev, NULL);
4053 }
4054
4055 static struct rte_pci_driver bnxt_rte_pmd = {
4056         .id_table = bnxt_pci_id_map,
4057         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
4058         .probe = bnxt_pci_probe,
4059         .remove = bnxt_pci_remove,
4060 };
4061
4062 static bool
4063 is_device_supported(struct rte_eth_dev *dev, struct rte_pci_driver *drv)
4064 {
4065         if (strcmp(dev->device->driver->name, drv->driver.name))
4066                 return false;
4067
4068         return true;
4069 }
4070
4071 bool is_bnxt_supported(struct rte_eth_dev *dev)
4072 {
4073         return is_device_supported(dev, &bnxt_rte_pmd);
4074 }
4075
4076 RTE_INIT(bnxt_init_log)
4077 {
4078         bnxt_logtype_driver = rte_log_register("pmd.net.bnxt.driver");
4079         if (bnxt_logtype_driver >= 0)
4080                 rte_log_set_level(bnxt_logtype_driver, RTE_LOG_NOTICE);
4081 }
4082
4083 RTE_PMD_REGISTER_PCI(net_bnxt, bnxt_rte_pmd);
4084 RTE_PMD_REGISTER_PCI_TABLE(net_bnxt, bnxt_pci_id_map);
4085 RTE_PMD_REGISTER_KMOD_DEP(net_bnxt, "* igb_uio | uio_pci_generic | vfio-pci");