drivers/net/bnxt/bnxt_ethdev.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2014-2018 Broadcom
   3  * All rights reserved.
   4  */
   5
   6 #include <inttypes.h>
   7 #include <stdbool.h>
   8
   9 #include <rte_dev.h>
  10 #include <rte_ethdev_driver.h>
  11 #include <rte_ethdev_pci.h>
  12 #include <rte_malloc.h>
  13 #include <rte_cycles.h>
  14 #include <rte_alarm.h>
  15 #include <rte_kvargs.h>
  16
  17 #include "bnxt.h"
  18 #include "bnxt_filter.h"
  19 #include "bnxt_hwrm.h"
  20 #include "bnxt_irq.h"
  21 #include "bnxt_ring.h"
  22 #include "bnxt_rxq.h"
  23 #include "bnxt_rxr.h"
  24 #include "bnxt_stats.h"
  25 #include "bnxt_txq.h"
  26 #include "bnxt_txr.h"
  27 #include "bnxt_vnic.h"
  28 #include "hsi_struct_def_dpdk.h"
  29 #include "bnxt_nvm_defs.h"
  30
  31 #define DRV_MODULE_NAME         "bnxt"
  32 static const char bnxt_version[] =
  33         "Broadcom NetXtreme driver " DRV_MODULE_NAME;
  34 int bnxt_logtype_driver;
  35
  36 /*
  37  * The set of PCI devices this driver supports
  38  */
  39 static const struct rte_pci_id bnxt_pci_id_map[] = {
  40         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM,
  41                          BROADCOM_DEV_ID_STRATUS_NIC_VF1) },
  42         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM,
  43                          BROADCOM_DEV_ID_STRATUS_NIC_VF2) },
  44         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_STRATUS_NIC) },
  45         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414_VF) },
  46         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57301) },
  47         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57302) },
  48         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57304_PF) },
  49         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57304_VF) },
  50         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_NS2) },
  51         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57402) },
  52         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57404) },
  53         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57406_PF) },
  54         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57406_VF) },
  55         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57402_MF) },
  56         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57407_RJ45) },
  57         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57404_MF) },
  58         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57406_MF) },
  59         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57407_SFP) },
  60         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57407_MF) },
  61         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_5741X_VF) },
  62         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_5731X_VF) },
  63         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57314) },
  64         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_MF) },
  65         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57311) },
  66         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57312) },
  67         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57412) },
  68         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414) },
  69         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_RJ45) },
  70         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_RJ45) },
  71         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57412_MF) },
  72         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57317_RJ45) },
  73         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_SFP) },
  74         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_SFP) },
  75         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57317_SFP) },
  76         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414_MF) },
  77         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_MF) },
  78         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58802) },
  79         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58804) },
  80         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58808) },
  81         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58802_VF) },
  82         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57508) },
  83         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57504) },
  84         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57502) },
  85         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57500_VF1) },
  86         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57500_VF2) },
  87         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57508_MF1) },
  88         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57504_MF1) },
  89         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57502_MF1) },
  90         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57508_MF2) },
  91         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57504_MF2) },
  92         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57502_MF2) },
  93         { .vendor_id = 0, /* sentinel */ },
  94 };
  95
  96 #define BNXT_ETH_RSS_SUPPORT (  \
  97         ETH_RSS_IPV4 |          \
  98         ETH_RSS_NONFRAG_IPV4_TCP |      \
  99         ETH_RSS_NONFRAG_IPV4_UDP |      \
 100         ETH_RSS_IPV6 |          \
 101         ETH_RSS_NONFRAG_IPV6_TCP |      \
 102         ETH_RSS_NONFRAG_IPV6_UDP)
 103
 104 #define BNXT_DEV_TX_OFFLOAD_SUPPORT (DEV_TX_OFFLOAD_VLAN_INSERT | \
 105                                      DEV_TX_OFFLOAD_IPV4_CKSUM | \
 106                                      DEV_TX_OFFLOAD_TCP_CKSUM | \
 107                                      DEV_TX_OFFLOAD_UDP_CKSUM | \
 108                                      DEV_TX_OFFLOAD_TCP_TSO | \
 109                                      DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM | \
 110                                      DEV_TX_OFFLOAD_VXLAN_TNL_TSO | \
 111                                      DEV_TX_OFFLOAD_GRE_TNL_TSO | \
 112                                      DEV_TX_OFFLOAD_IPIP_TNL_TSO | \
 113                                      DEV_TX_OFFLOAD_GENEVE_TNL_TSO | \
 114                                      DEV_TX_OFFLOAD_QINQ_INSERT | \
 115                                      DEV_TX_OFFLOAD_MULTI_SEGS)
 116
 117 #define BNXT_DEV_RX_OFFLOAD_SUPPORT (DEV_RX_OFFLOAD_VLAN_FILTER | \
 118                                      DEV_RX_OFFLOAD_VLAN_STRIP | \
 119                                      DEV_RX_OFFLOAD_IPV4_CKSUM | \
 120                                      DEV_RX_OFFLOAD_UDP_CKSUM | \
 121                                      DEV_RX_OFFLOAD_TCP_CKSUM | \
 122                                      DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM | \
 123                                      DEV_RX_OFFLOAD_JUMBO_FRAME | \
 124                                      DEV_RX_OFFLOAD_KEEP_CRC | \
 125                                      DEV_RX_OFFLOAD_VLAN_EXTEND | \
 126                                      DEV_RX_OFFLOAD_TCP_LRO | \
 127                                      DEV_RX_OFFLOAD_SCATTER | \
 128                                      DEV_RX_OFFLOAD_RSS_HASH)
 129
 130 #define BNXT_DEVARG_TRUFLOW     "host-based-truflow"
 131 static const char *const bnxt_dev_args[] = {
 132         BNXT_DEVARG_TRUFLOW,
 133         NULL
 134 };
 135
 136 /*
 137  * truflow == false to disable the feature
 138  * truflow == true to enable the feature
 139  */
 140 #define BNXT_DEVARG_TRUFLOW_INVALID(truflow)    ((truflow) > 1)
 141
 142 static int bnxt_vlan_offload_set_op(struct rte_eth_dev *dev, int mask);
 143 static void bnxt_print_link_info(struct rte_eth_dev *eth_dev);
 144 static int bnxt_dev_uninit(struct rte_eth_dev *eth_dev);
 145 static int bnxt_init_resources(struct bnxt *bp, bool reconfig_dev);
 146 static int bnxt_uninit_resources(struct bnxt *bp, bool reconfig_dev);
 147 static void bnxt_cancel_fw_health_check(struct bnxt *bp);
 148 static int bnxt_restore_vlan_filters(struct bnxt *bp);
 149 static void bnxt_dev_recover(void *arg);
 150
 151 int is_bnxt_in_error(struct bnxt *bp)
 152 {
 153         if (bp->flags & BNXT_FLAG_FATAL_ERROR)
 154                 return -EIO;
 155         if (bp->flags & BNXT_FLAG_FW_RESET)
 156                 return -EBUSY;
 157
 158         return 0;
 159 }
 160
 161 /***********************/
 162
 163 /*
 164  * High level utility functions
 165  */
 166
 167 static uint16_t bnxt_rss_ctxts(const struct bnxt *bp)
 168 {
 169         if (!BNXT_CHIP_THOR(bp))
 170                 return 1;
 171
 172         return RTE_ALIGN_MUL_CEIL(bp->rx_nr_rings,
 173                                   BNXT_RSS_ENTRIES_PER_CTX_THOR) /
 174                                     BNXT_RSS_ENTRIES_PER_CTX_THOR;
 175 }
 176
 177 static uint16_t  bnxt_rss_hash_tbl_size(const struct bnxt *bp)
 178 {
 179         if (!BNXT_CHIP_THOR(bp))
 180                 return HW_HASH_INDEX_SIZE;
 181
 182         return bnxt_rss_ctxts(bp) * BNXT_RSS_ENTRIES_PER_CTX_THOR;
 183 }
 184
 185 static void bnxt_free_mem(struct bnxt *bp, bool reconfig)
 186 {
 187         bnxt_free_filter_mem(bp);
 188         bnxt_free_vnic_attributes(bp);
 189         bnxt_free_vnic_mem(bp);
 190
 191         /* tx/rx rings are configured as part of *_queue_setup callbacks.
 192          * If the number of rings change across fw update,
 193          * we don't have much choice except to warn the user.
 194          */
 195         if (!reconfig) {
 196                 bnxt_free_stats(bp);
 197                 bnxt_free_tx_rings(bp);
 198                 bnxt_free_rx_rings(bp);
 199         }
 200         bnxt_free_async_cp_ring(bp);
 201         bnxt_free_rxtx_nq_ring(bp);
 202
 203         rte_free(bp->grp_info);
 204         bp->grp_info = NULL;
 205 }
 206
 207 static int bnxt_alloc_mem(struct bnxt *bp, bool reconfig)
 208 {
 209         int rc;
 210
 211         rc = bnxt_alloc_ring_grps(bp);
 212         if (rc)
 213                 goto alloc_mem_err;
 214
 215         rc = bnxt_alloc_async_ring_struct(bp);
 216         if (rc)
 217                 goto alloc_mem_err;
 218
 219         rc = bnxt_alloc_vnic_mem(bp);
 220         if (rc)
 221                 goto alloc_mem_err;
 222
 223         rc = bnxt_alloc_vnic_attributes(bp);
 224         if (rc)
 225                 goto alloc_mem_err;
 226
 227         rc = bnxt_alloc_filter_mem(bp);
 228         if (rc)
 229                 goto alloc_mem_err;
 230
 231         rc = bnxt_alloc_async_cp_ring(bp);
 232         if (rc)
 233                 goto alloc_mem_err;
 234
 235         rc = bnxt_alloc_rxtx_nq_ring(bp);
 236         if (rc)
 237                 goto alloc_mem_err;
 238
 239         return 0;
 240
 241 alloc_mem_err:
 242         bnxt_free_mem(bp, reconfig);
 243         return rc;
 244 }
 245
 246 static int bnxt_setup_one_vnic(struct bnxt *bp, uint16_t vnic_id)
 247 {
 248         struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
 249         struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id];
 250         uint64_t rx_offloads = dev_conf->rxmode.offloads;
 251         struct bnxt_rx_queue *rxq;
 252         unsigned int j;
 253         int rc;
 254
 255         rc = bnxt_vnic_grp_alloc(bp, vnic);
 256         if (rc)
 257                 goto err_out;
 258
 259         PMD_DRV_LOG(DEBUG, "vnic[%d] = %p vnic->fw_grp_ids = %p\n",
 260                     vnic_id, vnic, vnic->fw_grp_ids);
 261
 262         rc = bnxt_hwrm_vnic_alloc(bp, vnic);
 263         if (rc)
 264                 goto err_out;
 265
 266         /* Alloc RSS context only if RSS mode is enabled */
 267         if (dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS) {
 268                 int j, nr_ctxs = bnxt_rss_ctxts(bp);
 269
 270                 rc = 0;
 271                 for (j = 0; j < nr_ctxs; j++) {
 272                         rc = bnxt_hwrm_vnic_ctx_alloc(bp, vnic, j);
 273                         if (rc)
 274                                 break;
 275                 }
 276                 if (rc) {
 277                         PMD_DRV_LOG(ERR,
 278                                     "HWRM vnic %d ctx %d alloc failure rc: %x\n",
 279                                     vnic_id, j, rc);
 280                         goto err_out;
 281                 }
 282                 vnic->num_lb_ctxts = nr_ctxs;
 283         }
 284
 285         /*
 286          * Firmware sets pf pair in default vnic cfg. If the VLAN strip
 287          * setting is not available at this time, it will not be
 288          * configured correctly in the CFA.
 289          */
 290         if (rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
 291                 vnic->vlan_strip = true;
 292         else
 293                 vnic->vlan_strip = false;
 294
 295         rc = bnxt_hwrm_vnic_cfg(bp, vnic);
 296         if (rc)
 297                 goto err_out;
 298
 299         rc = bnxt_set_hwrm_vnic_filters(bp, vnic);
 300         if (rc)
 301                 goto err_out;
 302
 303         for (j = 0; j < bp->rx_num_qs_per_vnic; j++) {
 304                 rxq = bp->eth_dev->data->rx_queues[j];
 305
 306                 PMD_DRV_LOG(DEBUG,
 307                             "rxq[%d]->vnic=%p vnic->fw_grp_ids=%p\n",
 308                             j, rxq->vnic, rxq->vnic->fw_grp_ids);
 309
 310                 if (BNXT_HAS_RING_GRPS(bp) && rxq->rx_deferred_start)
 311                         rxq->vnic->fw_grp_ids[j] = INVALID_HW_RING_ID;
 312                 else
 313                         vnic->rx_queue_cnt++;
 314         }
 315
 316         PMD_DRV_LOG(DEBUG, "vnic->rx_queue_cnt = %d\n", vnic->rx_queue_cnt);
 317
 318         rc = bnxt_vnic_rss_configure(bp, vnic);
 319         if (rc)
 320                 goto err_out;
 321
 322         bnxt_hwrm_vnic_plcmode_cfg(bp, vnic);
 323
 324         if (rx_offloads & DEV_RX_OFFLOAD_TCP_LRO)
 325                 bnxt_hwrm_vnic_tpa_cfg(bp, vnic, 1);
 326         else
 327                 bnxt_hwrm_vnic_tpa_cfg(bp, vnic, 0);
 328
 329         return 0;
 330 err_out:
 331         PMD_DRV_LOG(ERR, "HWRM vnic %d cfg failure rc: %x\n",
 332                     vnic_id, rc);
 333         return rc;
 334 }
 335
 336 static int bnxt_init_chip(struct bnxt *bp)
 337 {
 338         struct rte_eth_link new;
 339         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(bp->eth_dev);
 340         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
 341         uint32_t intr_vector = 0;
 342         uint32_t queue_id, base = BNXT_MISC_VEC_ID;
 343         uint32_t vec = BNXT_MISC_VEC_ID;
 344         unsigned int i, j;
 345         int rc;
 346
 347         if (bp->eth_dev->data->mtu > RTE_ETHER_MTU) {
 348                 bp->eth_dev->data->dev_conf.rxmode.offloads |=
 349                         DEV_RX_OFFLOAD_JUMBO_FRAME;
 350                 bp->flags |= BNXT_FLAG_JUMBO;
 351         } else {
 352                 bp->eth_dev->data->dev_conf.rxmode.offloads &=
 353                         ~DEV_RX_OFFLOAD_JUMBO_FRAME;
 354                 bp->flags &= ~BNXT_FLAG_JUMBO;
 355         }
 356
 357         /* THOR does not support ring groups.
 358          * But we will use the array to save RSS context IDs.
 359          */
 360         if (BNXT_CHIP_THOR(bp))
 361                 bp->max_ring_grps = BNXT_MAX_RSS_CTXTS_THOR;
 362
 363         rc = bnxt_alloc_all_hwrm_stat_ctxs(bp);
 364         if (rc) {
 365                 PMD_DRV_LOG(ERR, "HWRM stat ctx alloc failure rc: %x\n", rc);
 366                 goto err_out;
 367         }
 368
 369         rc = bnxt_alloc_hwrm_rings(bp);
 370         if (rc) {
 371                 PMD_DRV_LOG(ERR, "HWRM ring alloc failure rc: %x\n", rc);
 372                 goto err_out;
 373         }
 374
 375         rc = bnxt_alloc_all_hwrm_ring_grps(bp);
 376         if (rc) {
 377                 PMD_DRV_LOG(ERR, "HWRM ring grp alloc failure: %x\n", rc);
 378                 goto err_out;
 379         }
 380
 381         if (!(bp->vnic_cap_flags & BNXT_VNIC_CAP_COS_CLASSIFY))
 382                 goto skip_cosq_cfg;
 383
 384         for (j = 0, i = 0; i < BNXT_COS_QUEUE_COUNT; i++) {
 385                 if (bp->rx_cos_queue[i].id != 0xff) {
 386                         struct bnxt_vnic_info *vnic = &bp->vnic_info[j++];
 387
 388                         if (!vnic) {
 389                                 PMD_DRV_LOG(ERR,
 390                                             "Num pools more than FW profile\n");
 391                                 rc = -EINVAL;
 392                                 goto err_out;
 393                         }
 394                         vnic->cos_queue_id = bp->rx_cos_queue[i].id;
 395                         bp->rx_cosq_cnt++;
 396                 }
 397         }
 398
 399 skip_cosq_cfg:
 400         rc = bnxt_mq_rx_configure(bp);
 401         if (rc) {
 402                 PMD_DRV_LOG(ERR, "MQ mode configure failure rc: %x\n", rc);
 403                 goto err_out;
 404         }
 405
 406         /* VNIC configuration */
 407         for (i = 0; i < bp->nr_vnics; i++) {
 408                 rc = bnxt_setup_one_vnic(bp, i);
 409                 if (rc)
 410                         goto err_out;
 411         }
 412
 413         rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, &bp->vnic_info[0], 0, NULL);
 414         if (rc) {
 415                 PMD_DRV_LOG(ERR,
 416                         "HWRM cfa l2 rx mask failure rc: %x\n", rc);
 417                 goto err_out;
 418         }
 419
 420         /* check and configure queue intr-vector mapping */
 421         if ((rte_intr_cap_multiple(intr_handle) ||
 422              !RTE_ETH_DEV_SRIOV(bp->eth_dev).active) &&
 423             bp->eth_dev->data->dev_conf.intr_conf.rxq != 0) {
 424                 intr_vector = bp->eth_dev->data->nb_rx_queues;
 425                 PMD_DRV_LOG(DEBUG, "intr_vector = %d\n", intr_vector);
 426                 if (intr_vector > bp->rx_cp_nr_rings) {
 427                         PMD_DRV_LOG(ERR, "At most %d intr queues supported",
 428                                         bp->rx_cp_nr_rings);
 429                         return -ENOTSUP;
 430                 }
 431                 rc = rte_intr_efd_enable(intr_handle, intr_vector);
 432                 if (rc)
 433                         return rc;
 434         }
 435
 436         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
 437                 intr_handle->intr_vec =
 438                         rte_zmalloc("intr_vec",
 439                                     bp->eth_dev->data->nb_rx_queues *
 440                                     sizeof(int), 0);
 441                 if (intr_handle->intr_vec == NULL) {
 442                         PMD_DRV_LOG(ERR, "Failed to allocate %d rx_queues"
 443                                 " intr_vec", bp->eth_dev->data->nb_rx_queues);
 444                         rc = -ENOMEM;
 445                         goto err_disable;
 446                 }
 447                 PMD_DRV_LOG(DEBUG, "intr_handle->intr_vec = %p "
 448                         "intr_handle->nb_efd = %d intr_handle->max_intr = %d\n",
 449                          intr_handle->intr_vec, intr_handle->nb_efd,
 450                         intr_handle->max_intr);
 451                 for (queue_id = 0; queue_id < bp->eth_dev->data->nb_rx_queues;
 452                      queue_id++) {
 453                         intr_handle->intr_vec[queue_id] =
 454                                                         vec + BNXT_RX_VEC_START;
 455                         if (vec < base + intr_handle->nb_efd - 1)
 456                                 vec++;
 457                 }
 458         }
 459
 460         /* enable uio/vfio intr/eventfd mapping */
 461         rc = rte_intr_enable(intr_handle);
 462 #ifndef RTE_EXEC_ENV_FREEBSD
 463         /* In FreeBSD OS, nic_uio driver does not support interrupts */
 464         if (rc)
 465                 goto err_free;
 466 #endif
 467
 468         rc = bnxt_get_hwrm_link_config(bp, &new);
 469         if (rc) {
 470                 PMD_DRV_LOG(ERR, "HWRM Get link config failure rc: %x\n", rc);
 471                 goto err_free;
 472         }
 473
 474         if (!bp->link_info.link_up) {
 475                 rc = bnxt_set_hwrm_link_config(bp, true);
 476                 if (rc) {
 477                         PMD_DRV_LOG(ERR,
 478                                 "HWRM link config failure rc: %x\n", rc);
 479                         goto err_free;
 480                 }
 481         }
 482         bnxt_print_link_info(bp->eth_dev);
 483
 484         bp->mark_table = rte_zmalloc("bnxt_mark_table", BNXT_MARK_TABLE_SZ, 0);
 485         if (!bp->mark_table)
 486                 PMD_DRV_LOG(ERR, "Allocation of mark table failed\n");
 487
 488         return 0;
 489
 490 err_free:
 491         rte_free(intr_handle->intr_vec);
 492 err_disable:
 493         rte_intr_efd_disable(intr_handle);
 494 err_out:
 495         /* Some of the error status returned by FW may not be from errno.h */
 496         if (rc > 0)
 497                 rc = -EIO;
 498
 499         return rc;
 500 }
 501
 502 static int bnxt_shutdown_nic(struct bnxt *bp)
 503 {
 504         bnxt_free_all_hwrm_resources(bp);
 505         bnxt_free_all_filters(bp);
 506         bnxt_free_all_vnics(bp);
 507         return 0;
 508 }
 509
 510 /*
 511  * Device configuration and status function
 512  */
 513
 514 static int bnxt_dev_info_get_op(struct rte_eth_dev *eth_dev,
 515                                 struct rte_eth_dev_info *dev_info)
 516 {
 517         struct rte_pci_device *pdev = RTE_DEV_TO_PCI(eth_dev->device);
 518         struct bnxt *bp = eth_dev->data->dev_private;
 519         uint16_t max_vnics, i, j, vpool, vrxq;
 520         unsigned int max_rx_rings;
 521         int rc;
 522
 523         rc = is_bnxt_in_error(bp);
 524         if (rc)
 525                 return rc;
 526
 527         /* MAC Specifics */
 528         dev_info->max_mac_addrs = bp->max_l2_ctx;
 529         dev_info->max_hash_mac_addrs = 0;
 530
 531         /* PF/VF specifics */
 532         if (BNXT_PF(bp))
 533                 dev_info->max_vfs = pdev->max_vfs;
 534
 535         max_rx_rings = BNXT_MAX_RINGS(bp);
 536         /* For the sake of symmetry, max_rx_queues = max_tx_queues */
 537         dev_info->max_rx_queues = max_rx_rings;
 538         dev_info->max_tx_queues = max_rx_rings;
 539         dev_info->reta_size = bnxt_rss_hash_tbl_size(bp);
 540         dev_info->hash_key_size = 40;
 541         max_vnics = bp->max_vnics;
 542
 543         /* MTU specifics */
 544         dev_info->min_mtu = RTE_ETHER_MIN_MTU;
 545         dev_info->max_mtu = BNXT_MAX_MTU;
 546
 547         /* Fast path specifics */
 548         dev_info->min_rx_bufsize = 1;
 549         dev_info->max_rx_pktlen = BNXT_MAX_PKT_LEN;
 550
 551         dev_info->rx_offload_capa = BNXT_DEV_RX_OFFLOAD_SUPPORT;
 552         if (bp->flags & BNXT_FLAG_PTP_SUPPORTED)
 553                 dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_TIMESTAMP;
 554         dev_info->tx_offload_capa = BNXT_DEV_TX_OFFLOAD_SUPPORT;
 555         dev_info->flow_type_rss_offloads = BNXT_ETH_RSS_SUPPORT;
 556
 557         /* *INDENT-OFF* */
 558         dev_info->default_rxconf = (struct rte_eth_rxconf) {
 559                 .rx_thresh = {
 560                         .pthresh = 8,
 561                         .hthresh = 8,
 562                         .wthresh = 0,
 563                 },
 564                 .rx_free_thresh = 32,
 565                 /* If no descriptors available, pkts are dropped by default */
 566                 .rx_drop_en = 1,
 567         };
 568
 569         dev_info->default_txconf = (struct rte_eth_txconf) {
 570                 .tx_thresh = {
 571                         .pthresh = 32,
 572                         .hthresh = 0,
 573                         .wthresh = 0,
 574                 },
 575                 .tx_free_thresh = 32,
 576                 .tx_rs_thresh = 32,
 577         };
 578         eth_dev->data->dev_conf.intr_conf.lsc = 1;
 579
 580         eth_dev->data->dev_conf.intr_conf.rxq = 1;
 581         dev_info->rx_desc_lim.nb_min = BNXT_MIN_RING_DESC;
 582         dev_info->rx_desc_lim.nb_max = BNXT_MAX_RX_RING_DESC;
 583         dev_info->tx_desc_lim.nb_min = BNXT_MIN_RING_DESC;
 584         dev_info->tx_desc_lim.nb_max = BNXT_MAX_TX_RING_DESC;
 585
 586         /* *INDENT-ON* */
 587
 588         /*
 589          * TODO: default_rxconf, default_txconf, rx_desc_lim, and tx_desc_lim
 590          *       need further investigation.
 591          */
 592
 593         /* VMDq resources */
 594         vpool = 64; /* ETH_64_POOLS */
 595         vrxq = 128; /* ETH_VMDQ_DCB_NUM_QUEUES */
 596         for (i = 0; i < 4; vpool >>= 1, i++) {
 597                 if (max_vnics > vpool) {
 598                         for (j = 0; j < 5; vrxq >>= 1, j++) {
 599                                 if (dev_info->max_rx_queues > vrxq) {
 600                                         if (vpool > vrxq)
 601                                                 vpool = vrxq;
 602                                         goto found;
 603                                 }
 604                         }
 605                         /* Not enough resources to support VMDq */
 606                         break;
 607                 }
 608         }
 609         /* Not enough resources to support VMDq */
 610         vpool = 0;
 611         vrxq = 0;
 612 found:
 613         dev_info->max_vmdq_pools = vpool;
 614         dev_info->vmdq_queue_num = vrxq;
 615
 616         dev_info->vmdq_pool_base = 0;
 617         dev_info->vmdq_queue_base = 0;
 618
 619         return 0;
 620 }
 621
 622 /* Configure the device based on the configuration provided */
 623 static int bnxt_dev_configure_op(struct rte_eth_dev *eth_dev)
 624 {
 625         struct bnxt *bp = eth_dev->data->dev_private;
 626         uint64_t rx_offloads = eth_dev->data->dev_conf.rxmode.offloads;
 627         int rc;
 628
 629         bp->rx_queues = (void *)eth_dev->data->rx_queues;
 630         bp->tx_queues = (void *)eth_dev->data->tx_queues;
 631         bp->tx_nr_rings = eth_dev->data->nb_tx_queues;
 632         bp->rx_nr_rings = eth_dev->data->nb_rx_queues;
 633
 634         rc = is_bnxt_in_error(bp);
 635         if (rc)
 636                 return rc;
 637
 638         if (BNXT_VF(bp) && (bp->flags & BNXT_FLAG_NEW_RM)) {
 639                 rc = bnxt_hwrm_check_vf_rings(bp);
 640                 if (rc) {
 641                         PMD_DRV_LOG(ERR, "HWRM insufficient resources\n");
 642                         return -ENOSPC;
 643                 }
 644
 645                 /* If a resource has already been allocated - in this case
 646                  * it is the async completion ring, free it. Reallocate it after
 647                  * resource reservation. This will ensure the resource counts
 648                  * are calculated correctly.
 649                  */
 650
 651                 pthread_mutex_lock(&bp->def_cp_lock);
 652
 653                 if (!BNXT_HAS_NQ(bp) && bp->async_cp_ring) {
 654                         bnxt_disable_int(bp);
 655                         bnxt_free_cp_ring(bp, bp->async_cp_ring);
 656                 }
 657
 658                 rc = bnxt_hwrm_func_reserve_vf_resc(bp, false);
 659                 if (rc) {
 660                         PMD_DRV_LOG(ERR, "HWRM resource alloc fail:%x\n", rc);
 661                         pthread_mutex_unlock(&bp->def_cp_lock);
 662                         return -ENOSPC;
 663                 }
 664
 665                 if (!BNXT_HAS_NQ(bp) && bp->async_cp_ring) {
 666                         rc = bnxt_alloc_async_cp_ring(bp);
 667                         if (rc) {
 668                                 pthread_mutex_unlock(&bp->def_cp_lock);
 669                                 return rc;
 670                         }
 671                         bnxt_enable_int(bp);
 672                 }
 673
 674                 pthread_mutex_unlock(&bp->def_cp_lock);
 675         } else {
 676                 /* legacy driver needs to get updated values */
 677                 rc = bnxt_hwrm_func_qcaps(bp);
 678                 if (rc) {
 679                         PMD_DRV_LOG(ERR, "hwrm func qcaps fail:%d\n", rc);
 680                         return rc;
 681                 }
 682         }
 683
 684         /* Inherit new configurations */
 685         if (eth_dev->data->nb_rx_queues > bp->max_rx_rings ||
 686             eth_dev->data->nb_tx_queues > bp->max_tx_rings ||
 687             eth_dev->data->nb_rx_queues + eth_dev->data->nb_tx_queues
 688                 + BNXT_NUM_ASYNC_CPR(bp) > bp->max_cp_rings ||
 689             eth_dev->data->nb_rx_queues + eth_dev->data->nb_tx_queues >
 690             bp->max_stat_ctx)
 691                 goto resource_error;
 692
 693         if (BNXT_HAS_RING_GRPS(bp) &&
 694             (uint32_t)(eth_dev->data->nb_rx_queues) > bp->max_ring_grps)
 695                 goto resource_error;
 696
 697         if (!(eth_dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_RSS) &&
 698             bp->max_vnics < eth_dev->data->nb_rx_queues)
 699                 goto resource_error;
 700
 701         bp->rx_cp_nr_rings = bp->rx_nr_rings;
 702         bp->tx_cp_nr_rings = bp->tx_nr_rings;
 703
 704         if (eth_dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG)
 705                 rx_offloads |= DEV_RX_OFFLOAD_RSS_HASH;
 706         eth_dev->data->dev_conf.rxmode.offloads = rx_offloads;
 707
 708         if (rx_offloads & DEV_RX_OFFLOAD_JUMBO_FRAME) {
 709                 eth_dev->data->mtu =
 710                         eth_dev->data->dev_conf.rxmode.max_rx_pkt_len -
 711                         RTE_ETHER_HDR_LEN - RTE_ETHER_CRC_LEN - VLAN_TAG_SIZE *
 712                         BNXT_NUM_VLANS;
 713                 bnxt_mtu_set_op(eth_dev, eth_dev->data->mtu);
 714         }
 715         return 0;
 716
 717 resource_error:
 718         PMD_DRV_LOG(ERR,
 719                     "Insufficient resources to support requested config\n");
 720         PMD_DRV_LOG(ERR,
 721                     "Num Queues Requested: Tx %d, Rx %d\n",
 722                     eth_dev->data->nb_tx_queues,
 723                     eth_dev->data->nb_rx_queues);
 724         PMD_DRV_LOG(ERR,
 725                     "MAX: TxQ %d, RxQ %d, CQ %d Stat %d, Grp %d, Vnic %d\n",
 726                     bp->max_tx_rings, bp->max_rx_rings, bp->max_cp_rings,
 727                     bp->max_stat_ctx, bp->max_ring_grps, bp->max_vnics);
 728         return -ENOSPC;
 729 }
 730
 731 static void bnxt_print_link_info(struct rte_eth_dev *eth_dev)
 732 {
 733         struct rte_eth_link *link = &eth_dev->data->dev_link;
 734
 735         if (link->link_status)
 736                 PMD_DRV_LOG(INFO, "Port %d Link Up - speed %u Mbps - %s\n",
 737                         eth_dev->data->port_id,
 738                         (uint32_t)link->link_speed,
 739                         (link->link_duplex == ETH_LINK_FULL_DUPLEX) ?
 740                         ("full-duplex") : ("half-duplex\n"));
 741         else
 742                 PMD_DRV_LOG(INFO, "Port %d Link Down\n",
 743                         eth_dev->data->port_id);
 744 }
 745
 746 /*
 747  * Determine whether the current configuration requires support for scattered
 748  * receive; return 1 if scattered receive is required and 0 if not.
 749  */
 750 static int bnxt_scattered_rx(struct rte_eth_dev *eth_dev)
 751 {
 752         uint16_t buf_size;
 753         int i;
 754
 755         if (eth_dev->data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_SCATTER)
 756                 return 1;
 757
 758         for (i = 0; i < eth_dev->data->nb_rx_queues; i++) {
 759                 struct bnxt_rx_queue *rxq = eth_dev->data->rx_queues[i];
 760
 761                 buf_size = (uint16_t)(rte_pktmbuf_data_room_size(rxq->mb_pool) -
 762                                       RTE_PKTMBUF_HEADROOM);
 763                 if (eth_dev->data->dev_conf.rxmode.max_rx_pkt_len > buf_size)
 764                         return 1;
 765         }
 766         return 0;
 767 }
 768
 769 static eth_rx_burst_t
 770 bnxt_receive_function(struct rte_eth_dev *eth_dev)
 771 {
 772         struct bnxt *bp = eth_dev->data->dev_private;
 773
 774 #ifdef RTE_ARCH_X86
 775 #ifndef RTE_LIBRTE_IEEE1588
 776         /*
 777          * Vector mode receive can be enabled only if scatter rx is not
 778          * in use and rx offloads are limited to VLAN stripping and
 779          * CRC stripping.
 780          */
 781         if (!eth_dev->data->scattered_rx &&
 782             !(eth_dev->data->dev_conf.rxmode.offloads &
 783               ~(DEV_RX_OFFLOAD_VLAN_STRIP |
 784                 DEV_RX_OFFLOAD_KEEP_CRC |
 785                 DEV_RX_OFFLOAD_JUMBO_FRAME |
 786                 DEV_RX_OFFLOAD_IPV4_CKSUM |
 787                 DEV_RX_OFFLOAD_UDP_CKSUM |
 788                 DEV_RX_OFFLOAD_TCP_CKSUM |
 789                 DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM |
 790                 DEV_RX_OFFLOAD_RSS_HASH |
 791                 DEV_RX_OFFLOAD_VLAN_FILTER))) {
 792                 PMD_DRV_LOG(INFO, "Using vector mode receive for port %d\n",
 793                             eth_dev->data->port_id);
 794                 bp->flags |= BNXT_FLAG_RX_VECTOR_PKT_MODE;
 795                 return bnxt_recv_pkts_vec;
 796         }
 797         PMD_DRV_LOG(INFO, "Vector mode receive disabled for port %d\n",
 798                     eth_dev->data->port_id);
 799         PMD_DRV_LOG(INFO,
 800                     "Port %d scatter: %d rx offload: %" PRIX64 "\n",
 801                     eth_dev->data->port_id,
 802                     eth_dev->data->scattered_rx,
 803                     eth_dev->data->dev_conf.rxmode.offloads);
 804 #endif
 805 #endif
 806         bp->flags &= ~BNXT_FLAG_RX_VECTOR_PKT_MODE;
 807         return bnxt_recv_pkts;
 808 }
 809
 810 static eth_tx_burst_t
 811 bnxt_transmit_function(__rte_unused struct rte_eth_dev *eth_dev)
 812 {
 813 #ifdef RTE_ARCH_X86
 814 #ifndef RTE_LIBRTE_IEEE1588
 815         /*
 816          * Vector mode transmit can be enabled only if not using scatter rx
 817          * or tx offloads.
 818          */
 819         if (!eth_dev->data->scattered_rx &&
 820             !eth_dev->data->dev_conf.txmode.offloads) {
 821                 PMD_DRV_LOG(INFO, "Using vector mode transmit for port %d\n",
 822                             eth_dev->data->port_id);
 823                 return bnxt_xmit_pkts_vec;
 824         }
 825         PMD_DRV_LOG(INFO, "Vector mode transmit disabled for port %d\n",
 826                     eth_dev->data->port_id);
 827         PMD_DRV_LOG(INFO,
 828                     "Port %d scatter: %d tx offload: %" PRIX64 "\n",
 829                     eth_dev->data->port_id,
 830                     eth_dev->data->scattered_rx,
 831                     eth_dev->data->dev_conf.txmode.offloads);
 832 #endif
 833 #endif
 834         return bnxt_xmit_pkts;
 835 }
 836
 837 static int bnxt_handle_if_change_status(struct bnxt *bp)
 838 {
 839         int rc;
 840
 841         /* Since fw has undergone a reset and lost all contexts,
 842          * set fatal flag to not issue hwrm during cleanup
 843          */
 844         bp->flags |= BNXT_FLAG_FATAL_ERROR;
 845         bnxt_uninit_resources(bp, true);
 846
 847         /* clear fatal flag so that re-init happens */
 848         bp->flags &= ~BNXT_FLAG_FATAL_ERROR;
 849         rc = bnxt_init_resources(bp, true);
 850
 851         bp->flags &= ~BNXT_FLAG_IF_CHANGE_HOT_FW_RESET_DONE;
 852
 853         return rc;
 854 }
 855
 856 static int bnxt_dev_start_op(struct rte_eth_dev *eth_dev)
 857 {
 858         struct bnxt *bp = eth_dev->data->dev_private;
 859         uint64_t rx_offloads = eth_dev->data->dev_conf.rxmode.offloads;
 860         int vlan_mask = 0;
 861         int rc;
 862
 863         if (!eth_dev->data->nb_tx_queues || !eth_dev->data->nb_rx_queues) {
 864                 PMD_DRV_LOG(ERR, "Queues are not configured yet!\n");
 865                 return -EINVAL;
 866         }
 867
 868         if (bp->rx_cp_nr_rings > RTE_ETHDEV_QUEUE_STAT_CNTRS) {
 869                 PMD_DRV_LOG(ERR,
 870                         "RxQ cnt %d > CONFIG_RTE_ETHDEV_QUEUE_STAT_CNTRS %d\n",
 871                         bp->rx_cp_nr_rings, RTE_ETHDEV_QUEUE_STAT_CNTRS);
 872         }
 873
 874         rc = bnxt_hwrm_if_change(bp, 1);
 875         if (!rc) {
 876                 if (bp->flags & BNXT_FLAG_IF_CHANGE_HOT_FW_RESET_DONE) {
 877                         rc = bnxt_handle_if_change_status(bp);
 878                         if (rc)
 879                                 return rc;
 880                 }
 881         }
 882         bnxt_enable_int(bp);
 883
 884         rc = bnxt_init_chip(bp);
 885         if (rc)
 886                 goto error;
 887
 888         eth_dev->data->scattered_rx = bnxt_scattered_rx(eth_dev);
 889         eth_dev->data->dev_started = 1;
 890
 891         bnxt_link_update(eth_dev, 1, ETH_LINK_UP);
 892
 893         if (rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER)
 894                 vlan_mask |= ETH_VLAN_FILTER_MASK;
 895         if (rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
 896                 vlan_mask |= ETH_VLAN_STRIP_MASK;
 897         rc = bnxt_vlan_offload_set_op(eth_dev, vlan_mask);
 898         if (rc)
 899                 goto error;
 900
 901         eth_dev->rx_pkt_burst = bnxt_receive_function(eth_dev);
 902         eth_dev->tx_pkt_burst = bnxt_transmit_function(eth_dev);
 903
 904         pthread_mutex_lock(&bp->def_cp_lock);
 905         bnxt_schedule_fw_health_check(bp);
 906         pthread_mutex_unlock(&bp->def_cp_lock);
 907         return 0;
 908
 909 error:
 910         bnxt_hwrm_if_change(bp, 0);
 911         bnxt_shutdown_nic(bp);
 912         bnxt_free_tx_mbufs(bp);
 913         bnxt_free_rx_mbufs(bp);
 914         eth_dev->data->dev_started = 0;
 915         return rc;
 916 }
 917
 918 static int bnxt_dev_set_link_up_op(struct rte_eth_dev *eth_dev)
 919 {
 920         struct bnxt *bp = eth_dev->data->dev_private;
 921         int rc = 0;
 922
 923         if (!bp->link_info.link_up)
 924                 rc = bnxt_set_hwrm_link_config(bp, true);
 925         if (!rc)
 926                 eth_dev->data->dev_link.link_status = 1;
 927
 928         bnxt_print_link_info(eth_dev);
 929         return rc;
 930 }
 931
 932 static int bnxt_dev_set_link_down_op(struct rte_eth_dev *eth_dev)
 933 {
 934         struct bnxt *bp = eth_dev->data->dev_private;
 935
 936         eth_dev->data->dev_link.link_status = 0;
 937         bnxt_set_hwrm_link_config(bp, false);
 938         bp->link_info.link_up = 0;
 939
 940         return 0;
 941 }
 942
 943 /* Unload the driver, release resources */
 944 static void bnxt_dev_stop_op(struct rte_eth_dev *eth_dev)
 945 {
 946         struct bnxt *bp = eth_dev->data->dev_private;
 947         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
 948         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
 949
 950         eth_dev->data->dev_started = 0;
 951         /* Prevent crashes when queues are still in use */
 952         eth_dev->rx_pkt_burst = &bnxt_dummy_recv_pkts;
 953         eth_dev->tx_pkt_burst = &bnxt_dummy_xmit_pkts;
 954
 955         bnxt_disable_int(bp);
 956
 957         /* disable uio/vfio intr/eventfd mapping */
 958         rte_intr_disable(intr_handle);
 959
 960         bnxt_cancel_fw_health_check(bp);
 961
 962         bnxt_dev_set_link_down_op(eth_dev);
 963
 964         /* Wait for link to be reset and the async notification to process.
 965          * During reset recovery, there is no need to wait and
 966          * VF/NPAR functions do not have privilege to change PHY config.
 967          */
 968         if (!is_bnxt_in_error(bp) && BNXT_SINGLE_PF(bp))
 969                 bnxt_link_update(eth_dev, 1, ETH_LINK_DOWN);
 970
 971         /* Clean queue intr-vector mapping */
 972         rte_intr_efd_disable(intr_handle);
 973         if (intr_handle->intr_vec != NULL) {
 974                 rte_free(intr_handle->intr_vec);
 975                 intr_handle->intr_vec = NULL;
 976         }
 977
 978         bnxt_hwrm_port_clr_stats(bp);
 979         bnxt_free_tx_mbufs(bp);
 980         bnxt_free_rx_mbufs(bp);
 981         /* Process any remaining notifications in default completion queue */
 982         bnxt_int_handler(eth_dev);
 983         bnxt_shutdown_nic(bp);
 984         bnxt_hwrm_if_change(bp, 0);
 985
 986         rte_free(bp->mark_table);
 987         bp->mark_table = NULL;
 988
 989         bp->flags &= ~BNXT_FLAG_RX_VECTOR_PKT_MODE;
 990         bp->rx_cosq_cnt = 0;
 991 }
 992
 993 static void bnxt_dev_close_op(struct rte_eth_dev *eth_dev)
 994 {
 995         struct bnxt *bp = eth_dev->data->dev_private;
 996
 997         /* cancel the recovery handler before remove dev */
 998         rte_eal_alarm_cancel(bnxt_dev_reset_and_resume, (void *)bp);
 999         rte_eal_alarm_cancel(bnxt_dev_recover, (void *)bp);
1000
1001         if (eth_dev->data->dev_started)
1002                 bnxt_dev_stop_op(eth_dev);
1003
1004         bnxt_uninit_resources(bp, false);
1005
1006         eth_dev->dev_ops = NULL;
1007         eth_dev->rx_pkt_burst = NULL;
1008         eth_dev->tx_pkt_burst = NULL;
1009
1010         rte_memzone_free((const struct rte_memzone *)bp->tx_mem_zone);
1011         bp->tx_mem_zone = NULL;
1012         rte_memzone_free((const struct rte_memzone *)bp->rx_mem_zone);
1013         bp->rx_mem_zone = NULL;
1014
1015         rte_free(bp->pf.vf_info);
1016         bp->pf.vf_info = NULL;
1017
1018         rte_free(bp->grp_info);
1019         bp->grp_info = NULL;
1020 }
1021
1022 static void bnxt_mac_addr_remove_op(struct rte_eth_dev *eth_dev,
1023                                     uint32_t index)
1024 {
1025         struct bnxt *bp = eth_dev->data->dev_private;
1026         uint64_t pool_mask = eth_dev->data->mac_pool_sel[index];
1027         struct bnxt_vnic_info *vnic;
1028         struct bnxt_filter_info *filter, *temp_filter;
1029         uint32_t i;
1030
1031         if (is_bnxt_in_error(bp))
1032                 return;
1033
1034         /*
1035          * Loop through all VNICs from the specified filter flow pools to
1036          * remove the corresponding MAC addr filter
1037          */
1038         for (i = 0; i < bp->nr_vnics; i++) {
1039                 if (!(pool_mask & (1ULL << i)))
1040                         continue;
1041
1042                 vnic = &bp->vnic_info[i];
1043                 filter = STAILQ_FIRST(&vnic->filter);
1044                 while (filter) {
1045                         temp_filter = STAILQ_NEXT(filter, next);
1046                         if (filter->mac_index == index) {
1047                                 STAILQ_REMOVE(&vnic->filter, filter,
1048                                                 bnxt_filter_info, next);
1049                                 bnxt_hwrm_clear_l2_filter(bp, filter);
1050                                 bnxt_free_filter(bp, filter);
1051                         }
1052                         filter = temp_filter;
1053                 }
1054         }
1055 }
1056
1057 static int bnxt_add_mac_filter(struct bnxt *bp, struct bnxt_vnic_info *vnic,
1058                                struct rte_ether_addr *mac_addr, uint32_t index,
1059                                uint32_t pool)
1060 {
1061         struct bnxt_filter_info *filter;
1062         int rc = 0;
1063
1064         /* Attach requested MAC address to the new l2_filter */
1065         STAILQ_FOREACH(filter, &vnic->filter, next) {
1066                 if (filter->mac_index == index) {
1067                         PMD_DRV_LOG(DEBUG,
1068                                     "MAC addr already existed for pool %d\n",
1069                                     pool);
1070                         return 0;
1071                 }
1072         }
1073
1074         filter = bnxt_alloc_filter(bp);
1075         if (!filter) {
1076                 PMD_DRV_LOG(ERR, "L2 filter alloc failed\n");
1077                 return -ENODEV;
1078         }
1079
1080         /* bnxt_alloc_filter copies default MAC to filter->l2_addr. So,
1081          * if the MAC that's been programmed now is a different one, then,
1082          * copy that addr to filter->l2_addr
1083          */
1084         if (mac_addr)
1085                 memcpy(filter->l2_addr, mac_addr, RTE_ETHER_ADDR_LEN);
1086         filter->flags |= HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_OUTERMOST;
1087
1088         rc = bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id, filter);
1089         if (!rc) {
1090                 filter->mac_index = index;
1091                 if (filter->mac_index == 0)
1092                         STAILQ_INSERT_HEAD(&vnic->filter, filter, next);
1093                 else
1094                         STAILQ_INSERT_TAIL(&vnic->filter, filter, next);
1095         } else {
1096                 bnxt_free_filter(bp, filter);
1097         }
1098
1099         return rc;
1100 }
1101
1102 static int bnxt_mac_addr_add_op(struct rte_eth_dev *eth_dev,
1103                                 struct rte_ether_addr *mac_addr,
1104                                 uint32_t index, uint32_t pool)
1105 {
1106         struct bnxt *bp = eth_dev->data->dev_private;
1107         struct bnxt_vnic_info *vnic = &bp->vnic_info[pool];
1108         int rc = 0;
1109
1110         rc = is_bnxt_in_error(bp);
1111         if (rc)
1112                 return rc;
1113
1114         if (BNXT_VF(bp) & !BNXT_VF_IS_TRUSTED(bp)) {
1115                 PMD_DRV_LOG(ERR, "Cannot add MAC address to a VF interface\n");
1116                 return -ENOTSUP;
1117         }
1118
1119         if (!vnic) {
1120                 PMD_DRV_LOG(ERR, "VNIC not found for pool %d!\n", pool);
1121                 return -EINVAL;
1122         }
1123
1124         /* Filter settings will get applied when port is started */
1125         if (!eth_dev->data->dev_started)
1126                 return 0;
1127
1128         rc = bnxt_add_mac_filter(bp, vnic, mac_addr, index, pool);
1129
1130         return rc;
1131 }
1132
1133 int bnxt_link_update(struct rte_eth_dev *eth_dev, int wait_to_complete,
1134                      bool exp_link_status)
1135 {
1136         int rc = 0;
1137         struct bnxt *bp = eth_dev->data->dev_private;
1138         struct rte_eth_link new;
1139         int cnt = exp_link_status ? BNXT_LINK_UP_WAIT_CNT :
1140                   BNXT_LINK_DOWN_WAIT_CNT;
1141
1142         rc = is_bnxt_in_error(bp);
1143         if (rc)
1144                 return rc;
1145
1146         memset(&new, 0, sizeof(new));
1147         do {
1148                 /* Retrieve link info from hardware */
1149                 rc = bnxt_get_hwrm_link_config(bp, &new);
1150                 if (rc) {
1151                         new.link_speed = ETH_LINK_SPEED_100M;
1152                         new.link_duplex = ETH_LINK_FULL_DUPLEX;
1153                         PMD_DRV_LOG(ERR,
1154                                 "Failed to retrieve link rc = 0x%x!\n", rc);
1155                         goto out;
1156                 }
1157
1158                 if (!wait_to_complete || new.link_status == exp_link_status)
1159                         break;
1160
1161                 rte_delay_ms(BNXT_LINK_WAIT_INTERVAL);
1162         } while (cnt--);
1163
1164 out:
1165         /* Timed out or success */
1166         if (new.link_status != eth_dev->data->dev_link.link_status ||
1167         new.link_speed != eth_dev->data->dev_link.link_speed) {
1168                 rte_eth_linkstatus_set(eth_dev, &new);
1169
1170                 _rte_eth_dev_callback_process(eth_dev,
1171                                               RTE_ETH_EVENT_INTR_LSC,
1172                                               NULL);
1173
1174                 bnxt_print_link_info(eth_dev);
1175         }
1176
1177         return rc;
1178 }
1179
1180 static int bnxt_link_update_op(struct rte_eth_dev *eth_dev,
1181                                int wait_to_complete)
1182 {
1183         return bnxt_link_update(eth_dev, wait_to_complete, ETH_LINK_UP);
1184 }
1185
1186 static int bnxt_promiscuous_enable_op(struct rte_eth_dev *eth_dev)
1187 {
1188         struct bnxt *bp = eth_dev->data->dev_private;
1189         struct bnxt_vnic_info *vnic;
1190         uint32_t old_flags;
1191         int rc;
1192
1193         rc = is_bnxt_in_error(bp);
1194         if (rc)
1195                 return rc;
1196
1197         /* Filter settings will get applied when port is started */
1198         if (!eth_dev->data->dev_started)
1199                 return 0;
1200
1201         if (bp->vnic_info == NULL)
1202                 return 0;
1203
1204         vnic = BNXT_GET_DEFAULT_VNIC(bp);
1205
1206         old_flags = vnic->flags;
1207         vnic->flags |= BNXT_VNIC_INFO_PROMISC;
1208         rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1209         if (rc != 0)
1210                 vnic->flags = old_flags;
1211
1212         return rc;
1213 }
1214
1215 static int bnxt_promiscuous_disable_op(struct rte_eth_dev *eth_dev)
1216 {
1217         struct bnxt *bp = eth_dev->data->dev_private;
1218         struct bnxt_vnic_info *vnic;
1219         uint32_t old_flags;
1220         int rc;
1221
1222         rc = is_bnxt_in_error(bp);
1223         if (rc)
1224                 return rc;
1225
1226         /* Filter settings will get applied when port is started */
1227         if (!eth_dev->data->dev_started)
1228                 return 0;
1229
1230         if (bp->vnic_info == NULL)
1231                 return 0;
1232
1233         vnic = BNXT_GET_DEFAULT_VNIC(bp);
1234
1235         old_flags = vnic->flags;
1236         vnic->flags &= ~BNXT_VNIC_INFO_PROMISC;
1237         rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1238         if (rc != 0)
1239                 vnic->flags = old_flags;
1240
1241         return rc;
1242 }
1243
1244 static int bnxt_allmulticast_enable_op(struct rte_eth_dev *eth_dev)
1245 {
1246         struct bnxt *bp = eth_dev->data->dev_private;
1247         struct bnxt_vnic_info *vnic;
1248         uint32_t old_flags;
1249         int rc;
1250
1251         rc = is_bnxt_in_error(bp);
1252         if (rc)
1253                 return rc;
1254
1255         /* Filter settings will get applied when port is started */
1256         if (!eth_dev->data->dev_started)
1257                 return 0;
1258
1259         if (bp->vnic_info == NULL)
1260                 return 0;
1261
1262         vnic = BNXT_GET_DEFAULT_VNIC(bp);
1263
1264         old_flags = vnic->flags;
1265         vnic->flags |= BNXT_VNIC_INFO_ALLMULTI;
1266         rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1267         if (rc != 0)
1268                 vnic->flags = old_flags;
1269
1270         return rc;
1271 }
1272
1273 static int bnxt_allmulticast_disable_op(struct rte_eth_dev *eth_dev)
1274 {
1275         struct bnxt *bp = eth_dev->data->dev_private;
1276         struct bnxt_vnic_info *vnic;
1277         uint32_t old_flags;
1278         int rc;
1279
1280         rc = is_bnxt_in_error(bp);
1281         if (rc)
1282                 return rc;
1283
1284         /* Filter settings will get applied when port is started */
1285         if (!eth_dev->data->dev_started)
1286                 return 0;
1287
1288         if (bp->vnic_info == NULL)
1289                 return 0;
1290
1291         vnic = BNXT_GET_DEFAULT_VNIC(bp);
1292
1293         old_flags = vnic->flags;
1294         vnic->flags &= ~BNXT_VNIC_INFO_ALLMULTI;
1295         rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1296         if (rc != 0)
1297                 vnic->flags = old_flags;
1298
1299         return rc;
1300 }
1301
1302 /* Return bnxt_rx_queue pointer corresponding to a given rxq. */
1303 static struct bnxt_rx_queue *bnxt_qid_to_rxq(struct bnxt *bp, uint16_t qid)
1304 {
1305         if (qid >= bp->rx_nr_rings)
1306                 return NULL;
1307
1308         return bp->eth_dev->data->rx_queues[qid];
1309 }
1310
1311 /* Return rxq corresponding to a given rss table ring/group ID. */
1312 static uint16_t bnxt_rss_to_qid(struct bnxt *bp, uint16_t fwr)
1313 {
1314         struct bnxt_rx_queue *rxq;
1315         unsigned int i;
1316
1317         if (!BNXT_HAS_RING_GRPS(bp)) {
1318                 for (i = 0; i < bp->rx_nr_rings; i++) {
1319                         rxq = bp->eth_dev->data->rx_queues[i];
1320                         if (rxq->rx_ring->rx_ring_struct->fw_ring_id == fwr)
1321                                 return rxq->index;
1322                 }
1323         } else {
1324                 for (i = 0; i < bp->rx_nr_rings; i++) {
1325                         if (bp->grp_info[i].fw_grp_id == fwr)
1326                                 return i;
1327                 }
1328         }
1329
1330         return INVALID_HW_RING_ID;
1331 }
1332
1333 static int bnxt_reta_update_op(struct rte_eth_dev *eth_dev,
1334                             struct rte_eth_rss_reta_entry64 *reta_conf,
1335                             uint16_t reta_size)
1336 {
1337         struct bnxt *bp = eth_dev->data->dev_private;
1338         struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
1339         struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp);
1340         uint16_t tbl_size = bnxt_rss_hash_tbl_size(bp);
1341         uint16_t idx, sft;
1342         int i, rc;
1343
1344         rc = is_bnxt_in_error(bp);
1345         if (rc)
1346                 return rc;
1347
1348         if (!vnic->rss_table)
1349                 return -EINVAL;
1350
1351         if (!(dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG))
1352                 return -EINVAL;
1353
1354         if (reta_size != tbl_size) {
1355                 PMD_DRV_LOG(ERR, "The configured hash table lookup size "
1356                         "(%d) must equal the size supported by the hardware "
1357                         "(%d)\n", reta_size, tbl_size);
1358                 return -EINVAL;
1359         }
1360
1361         for (i = 0; i < reta_size; i++) {
1362                 struct bnxt_rx_queue *rxq;
1363
1364                 idx = i / RTE_RETA_GROUP_SIZE;
1365                 sft = i % RTE_RETA_GROUP_SIZE;
1366
1367                 if (!(reta_conf[idx].mask & (1ULL << sft)))
1368                         continue;
1369
1370                 rxq = bnxt_qid_to_rxq(bp, reta_conf[idx].reta[sft]);
1371                 if (!rxq) {
1372                         PMD_DRV_LOG(ERR, "Invalid ring in reta_conf.\n");
1373                         return -EINVAL;
1374                 }
1375
1376                 if (BNXT_CHIP_THOR(bp)) {
1377                         vnic->rss_table[i * 2] =
1378                                 rxq->rx_ring->rx_ring_struct->fw_ring_id;
1379                         vnic->rss_table[i * 2 + 1] =
1380                                 rxq->cp_ring->cp_ring_struct->fw_ring_id;
1381                 } else {
1382                         vnic->rss_table[i] =
1383                             vnic->fw_grp_ids[reta_conf[idx].reta[sft]];
1384                 }
1385         }
1386
1387         bnxt_hwrm_vnic_rss_cfg(bp, vnic);
1388         return 0;
1389 }
1390
1391 static int bnxt_reta_query_op(struct rte_eth_dev *eth_dev,
1392                               struct rte_eth_rss_reta_entry64 *reta_conf,
1393                               uint16_t reta_size)
1394 {
1395         struct bnxt *bp = eth_dev->data->dev_private;
1396         struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp);
1397         uint16_t tbl_size = bnxt_rss_hash_tbl_size(bp);
1398         uint16_t idx, sft, i;
1399         int rc;
1400
1401         rc = is_bnxt_in_error(bp);
1402         if (rc)
1403                 return rc;
1404
1405         /* Retrieve from the default VNIC */
1406         if (!vnic)
1407                 return -EINVAL;
1408         if (!vnic->rss_table)
1409                 return -EINVAL;
1410
1411         if (reta_size != tbl_size) {
1412                 PMD_DRV_LOG(ERR, "The configured hash table lookup size "
1413                         "(%d) must equal the size supported by the hardware "
1414                         "(%d)\n", reta_size, tbl_size);
1415                 return -EINVAL;
1416         }
1417
1418         for (idx = 0, i = 0; i < reta_size; i++) {
1419                 idx = i / RTE_RETA_GROUP_SIZE;
1420                 sft = i % RTE_RETA_GROUP_SIZE;
1421
1422                 if (reta_conf[idx].mask & (1ULL << sft)) {
1423                         uint16_t qid;
1424
1425                         if (BNXT_CHIP_THOR(bp))
1426                                 qid = bnxt_rss_to_qid(bp,
1427                                                       vnic->rss_table[i * 2]);
1428                         else
1429                                 qid = bnxt_rss_to_qid(bp, vnic->rss_table[i]);
1430
1431                         if (qid == INVALID_HW_RING_ID) {
1432                                 PMD_DRV_LOG(ERR, "Inv. entry in rss table.\n");
1433                                 return -EINVAL;
1434                         }
1435                         reta_conf[idx].reta[sft] = qid;
1436                 }
1437         }
1438
1439         return 0;
1440 }
1441
1442 static int bnxt_rss_hash_update_op(struct rte_eth_dev *eth_dev,
1443                                    struct rte_eth_rss_conf *rss_conf)
1444 {
1445         struct bnxt *bp = eth_dev->data->dev_private;
1446         struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
1447         struct bnxt_vnic_info *vnic;
1448         int rc;
1449
1450         rc = is_bnxt_in_error(bp);
1451         if (rc)
1452                 return rc;
1453
1454         /*
1455          * If RSS enablement were different than dev_configure,
1456          * then return -EINVAL
1457          */
1458         if (dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG) {
1459                 if (!rss_conf->rss_hf)
1460                         PMD_DRV_LOG(ERR, "Hash type NONE\n");
1461         } else {
1462                 if (rss_conf->rss_hf & BNXT_ETH_RSS_SUPPORT)
1463                         return -EINVAL;
1464         }
1465
1466         bp->flags |= BNXT_FLAG_UPDATE_HASH;
1467         memcpy(&bp->rss_conf, rss_conf, sizeof(*rss_conf));
1468
1469         /* Update the default RSS VNIC(s) */
1470         vnic = BNXT_GET_DEFAULT_VNIC(bp);
1471         vnic->hash_type = bnxt_rte_to_hwrm_hash_types(rss_conf->rss_hf);
1472
1473         /*
1474          * If hashkey is not specified, use the previously configured
1475          * hashkey
1476          */
1477         if (!rss_conf->rss_key)
1478                 goto rss_config;
1479
1480         if (rss_conf->rss_key_len != HW_HASH_KEY_SIZE) {
1481                 PMD_DRV_LOG(ERR,
1482                             "Invalid hashkey length, should be 16 bytes\n");
1483                 return -EINVAL;
1484         }
1485         memcpy(vnic->rss_hash_key, rss_conf->rss_key, rss_conf->rss_key_len);
1486
1487 rss_config:
1488         bnxt_hwrm_vnic_rss_cfg(bp, vnic);
1489         return 0;
1490 }
1491
1492 static int bnxt_rss_hash_conf_get_op(struct rte_eth_dev *eth_dev,
1493                                      struct rte_eth_rss_conf *rss_conf)
1494 {
1495         struct bnxt *bp = eth_dev->data->dev_private;
1496         struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp);
1497         int len, rc;
1498         uint32_t hash_types;
1499
1500         rc = is_bnxt_in_error(bp);
1501         if (rc)
1502                 return rc;
1503
1504         /* RSS configuration is the same for all VNICs */
1505         if (vnic && vnic->rss_hash_key) {
1506                 if (rss_conf->rss_key) {
1507                         len = rss_conf->rss_key_len <= HW_HASH_KEY_SIZE ?
1508                               rss_conf->rss_key_len : HW_HASH_KEY_SIZE;
1509                         memcpy(rss_conf->rss_key, vnic->rss_hash_key, len);
1510                 }
1511
1512                 hash_types = vnic->hash_type;
1513                 rss_conf->rss_hf = 0;
1514                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV4) {
1515                         rss_conf->rss_hf |= ETH_RSS_IPV4;
1516                         hash_types &= ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV4;
1517                 }
1518                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV4) {
1519                         rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP;
1520                         hash_types &=
1521                                 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV4;
1522                 }
1523                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV4) {
1524                         rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
1525                         hash_types &=
1526                                 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV4;
1527                 }
1528                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6) {
1529                         rss_conf->rss_hf |= ETH_RSS_IPV6;
1530                         hash_types &= ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6;
1531                 }
1532                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV6) {
1533                         rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV6_TCP;
1534                         hash_types &=
1535                                 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV6;
1536                 }
1537                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV6) {
1538                         rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;
1539                         hash_types &=
1540                                 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV6;
1541                 }
1542                 if (hash_types) {
1543                         PMD_DRV_LOG(ERR,
1544                                 "Unknwon RSS config from firmware (%08x), RSS disabled",
1545                                 vnic->hash_type);
1546                         return -ENOTSUP;
1547                 }
1548         } else {
1549                 rss_conf->rss_hf = 0;
1550         }
1551         return 0;
1552 }
1553
1554 static int bnxt_flow_ctrl_get_op(struct rte_eth_dev *dev,
1555                                struct rte_eth_fc_conf *fc_conf)
1556 {
1557         struct bnxt *bp = dev->data->dev_private;
1558         struct rte_eth_link link_info;
1559         int rc;
1560
1561         rc = is_bnxt_in_error(bp);
1562         if (rc)
1563                 return rc;
1564
1565         rc = bnxt_get_hwrm_link_config(bp, &link_info);
1566         if (rc)
1567                 return rc;
1568
1569         memset(fc_conf, 0, sizeof(*fc_conf));
1570         if (bp->link_info.auto_pause)
1571                 fc_conf->autoneg = 1;
1572         switch (bp->link_info.pause) {
1573         case 0:
1574                 fc_conf->mode = RTE_FC_NONE;
1575                 break;
1576         case HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_TX:
1577                 fc_conf->mode = RTE_FC_TX_PAUSE;
1578                 break;
1579         case HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_RX:
1580                 fc_conf->mode = RTE_FC_RX_PAUSE;
1581                 break;
1582         case (HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_TX |
1583                         HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_RX):
1584                 fc_conf->mode = RTE_FC_FULL;
1585                 break;
1586         }
1587         return 0;
1588 }
1589
1590 static int bnxt_flow_ctrl_set_op(struct rte_eth_dev *dev,
1591                                struct rte_eth_fc_conf *fc_conf)
1592 {
1593         struct bnxt *bp = dev->data->dev_private;
1594         int rc;
1595
1596         rc = is_bnxt_in_error(bp);
1597         if (rc)
1598                 return rc;
1599
1600         if (!BNXT_SINGLE_PF(bp) || BNXT_VF(bp)) {
1601                 PMD_DRV_LOG(ERR, "Flow Control Settings cannot be modified\n");
1602                 return -ENOTSUP;
1603         }
1604
1605         switch (fc_conf->mode) {
1606         case RTE_FC_NONE:
1607                 bp->link_info.auto_pause = 0;
1608                 bp->link_info.force_pause = 0;
1609                 break;
1610         case RTE_FC_RX_PAUSE:
1611                 if (fc_conf->autoneg) {
1612                         bp->link_info.auto_pause =
1613                                         HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_RX;
1614                         bp->link_info.force_pause = 0;
1615                 } else {
1616                         bp->link_info.auto_pause = 0;
1617                         bp->link_info.force_pause =
1618                                         HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_RX;
1619                 }
1620                 break;
1621         case RTE_FC_TX_PAUSE:
1622                 if (fc_conf->autoneg) {
1623                         bp->link_info.auto_pause =
1624                                         HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_TX;
1625                         bp->link_info.force_pause = 0;
1626                 } else {
1627                         bp->link_info.auto_pause = 0;
1628                         bp->link_info.force_pause =
1629                                         HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_TX;
1630                 }
1631                 break;
1632         case RTE_FC_FULL:
1633                 if (fc_conf->autoneg) {
1634                         bp->link_info.auto_pause =
1635                                         HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_TX |
1636                                         HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_RX;
1637                         bp->link_info.force_pause = 0;
1638                 } else {
1639                         bp->link_info.auto_pause = 0;
1640                         bp->link_info.force_pause =
1641                                         HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_TX |
1642                                         HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_RX;
1643                 }
1644                 break;
1645         }
1646         return bnxt_set_hwrm_link_config(bp, true);
1647 }
1648
1649 /* Add UDP tunneling port */
1650 static int
1651 bnxt_udp_tunnel_port_add_op(struct rte_eth_dev *eth_dev,
1652                          struct rte_eth_udp_tunnel *udp_tunnel)
1653 {
1654         struct bnxt *bp = eth_dev->data->dev_private;
1655         uint16_t tunnel_type = 0;
1656         int rc = 0;
1657
1658         rc = is_bnxt_in_error(bp);
1659         if (rc)
1660                 return rc;
1661
1662         switch (udp_tunnel->prot_type) {
1663         case RTE_TUNNEL_TYPE_VXLAN:
1664                 if (bp->vxlan_port_cnt) {
1665                         PMD_DRV_LOG(ERR, "Tunnel Port %d already programmed\n",
1666                                 udp_tunnel->udp_port);
1667                         if (bp->vxlan_port != udp_tunnel->udp_port) {
1668                                 PMD_DRV_LOG(ERR, "Only one port allowed\n");
1669                                 return -ENOSPC;
1670                         }
1671                         bp->vxlan_port_cnt++;
1672                         return 0;
1673                 }
1674                 tunnel_type =
1675                         HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_VXLAN;
1676                 bp->vxlan_port_cnt++;
1677                 break;
1678         case RTE_TUNNEL_TYPE_GENEVE:
1679                 if (bp->geneve_port_cnt) {
1680                         PMD_DRV_LOG(ERR, "Tunnel Port %d already programmed\n",
1681                                 udp_tunnel->udp_port);
1682                         if (bp->geneve_port != udp_tunnel->udp_port) {
1683                                 PMD_DRV_LOG(ERR, "Only one port allowed\n");
1684                                 return -ENOSPC;
1685                         }
1686                         bp->geneve_port_cnt++;
1687                         return 0;
1688                 }
1689                 tunnel_type =
1690                         HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_GENEVE;
1691                 bp->geneve_port_cnt++;
1692                 break;
1693         default:
1694                 PMD_DRV_LOG(ERR, "Tunnel type is not supported\n");
1695                 return -ENOTSUP;
1696         }
1697         rc = bnxt_hwrm_tunnel_dst_port_alloc(bp, udp_tunnel->udp_port,
1698                                              tunnel_type);
1699         return rc;
1700 }
1701
1702 static int
1703 bnxt_udp_tunnel_port_del_op(struct rte_eth_dev *eth_dev,
1704                          struct rte_eth_udp_tunnel *udp_tunnel)
1705 {
1706         struct bnxt *bp = eth_dev->data->dev_private;
1707         uint16_t tunnel_type = 0;
1708         uint16_t port = 0;
1709         int rc = 0;
1710
1711         rc = is_bnxt_in_error(bp);
1712         if (rc)
1713                 return rc;
1714
1715         switch (udp_tunnel->prot_type) {
1716         case RTE_TUNNEL_TYPE_VXLAN:
1717                 if (!bp->vxlan_port_cnt) {
1718                         PMD_DRV_LOG(ERR, "No Tunnel port configured yet\n");
1719                         return -EINVAL;
1720                 }
1721                 if (bp->vxlan_port != udp_tunnel->udp_port) {
1722                         PMD_DRV_LOG(ERR, "Req Port: %d. Configured port: %d\n",
1723                                 udp_tunnel->udp_port, bp->vxlan_port);
1724                         return -EINVAL;
1725                 }
1726                 if (--bp->vxlan_port_cnt)
1727                         return 0;
1728
1729                 tunnel_type =
1730                         HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN;
1731                 port = bp->vxlan_fw_dst_port_id;
1732                 break;
1733         case RTE_TUNNEL_TYPE_GENEVE:
1734                 if (!bp->geneve_port_cnt) {
1735                         PMD_DRV_LOG(ERR, "No Tunnel port configured yet\n");
1736                         return -EINVAL;
1737                 }
1738                 if (bp->geneve_port != udp_tunnel->udp_port) {
1739                         PMD_DRV_LOG(ERR, "Req Port: %d. Configured port: %d\n",
1740                                 udp_tunnel->udp_port, bp->geneve_port);
1741                         return -EINVAL;
1742                 }
1743                 if (--bp->geneve_port_cnt)
1744                         return 0;
1745
1746                 tunnel_type =
1747                         HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_GENEVE;
1748                 port = bp->geneve_fw_dst_port_id;
1749                 break;
1750         default:
1751                 PMD_DRV_LOG(ERR, "Tunnel type is not supported\n");
1752                 return -ENOTSUP;
1753         }
1754
1755         rc = bnxt_hwrm_tunnel_dst_port_free(bp, port, tunnel_type);
1756         if (!rc) {
1757                 if (tunnel_type ==
1758                     HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN)
1759                         bp->vxlan_port = 0;
1760                 if (tunnel_type ==
1761                     HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_GENEVE)
1762                         bp->geneve_port = 0;
1763         }
1764         return rc;
1765 }
1766
1767 static int bnxt_del_vlan_filter(struct bnxt *bp, uint16_t vlan_id)
1768 {
1769         struct bnxt_filter_info *filter;
1770         struct bnxt_vnic_info *vnic;
1771         int rc = 0;
1772         uint32_t chk = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN;
1773
1774         vnic = BNXT_GET_DEFAULT_VNIC(bp);
1775         filter = STAILQ_FIRST(&vnic->filter);
1776         while (filter) {
1777                 /* Search for this matching MAC+VLAN filter */
1778                 if (bnxt_vlan_filter_exists(bp, filter, chk, vlan_id)) {
1779                         /* Delete the filter */
1780                         rc = bnxt_hwrm_clear_l2_filter(bp, filter);
1781                         if (rc)
1782                                 return rc;
1783                         STAILQ_REMOVE(&vnic->filter, filter,
1784                                       bnxt_filter_info, next);
1785                         bnxt_free_filter(bp, filter);
1786                         PMD_DRV_LOG(INFO,
1787                                     "Deleted vlan filter for %d\n",
1788                                     vlan_id);
1789                         return 0;
1790                 }
1791                 filter = STAILQ_NEXT(filter, next);
1792         }
1793         return -ENOENT;
1794 }
1795
1796 static int bnxt_add_vlan_filter(struct bnxt *bp, uint16_t vlan_id)
1797 {
1798         struct bnxt_filter_info *filter;
1799         struct bnxt_vnic_info *vnic;
1800         int rc = 0;
1801         uint32_t en = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN |
1802                 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN_MASK;
1803         uint32_t chk = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN;
1804
1805         /* Implementation notes on the use of VNIC in this command:
1806          *
1807          * By default, these filters belong to default vnic for the function.
1808          * Once these filters are set up, only destination VNIC can be modified.
1809          * If the destination VNIC is not specified in this command,
1810          * then the HWRM shall only create an l2 context id.
1811          */
1812
1813         vnic = BNXT_GET_DEFAULT_VNIC(bp);
1814         filter = STAILQ_FIRST(&vnic->filter);
1815         /* Check if the VLAN has already been added */
1816         while (filter) {
1817                 if (bnxt_vlan_filter_exists(bp, filter, chk, vlan_id))
1818                         return -EEXIST;
1819
1820                 filter = STAILQ_NEXT(filter, next);
1821         }
1822
1823         /* No match found. Alloc a fresh filter and issue the L2_FILTER_ALLOC
1824          * command to create MAC+VLAN filter with the right flags, enables set.
1825          */
1826         filter = bnxt_alloc_filter(bp);
1827         if (!filter) {
1828                 PMD_DRV_LOG(ERR,
1829                             "MAC/VLAN filter alloc failed\n");
1830                 return -ENOMEM;
1831         }
1832         /* MAC + VLAN ID filter */
1833         /* If l2_ivlan == 0 and l2_ivlan_mask != 0, only
1834          * untagged packets are received
1835          *
1836          * If l2_ivlan != 0 and l2_ivlan_mask != 0, untagged
1837          * packets and only the programmed vlan's packets are received
1838          */
1839         filter->l2_ivlan = vlan_id;
1840         filter->l2_ivlan_mask = 0x0FFF;
1841         filter->enables |= en;
1842         filter->flags |= HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_OUTERMOST;
1843
1844         rc = bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id, filter);
1845         if (rc) {
1846                 /* Free the newly allocated filter as we were
1847                  * not able to create the filter in hardware.
1848                  */
1849                 bnxt_free_filter(bp, filter);
1850                 return rc;
1851         }
1852
1853         filter->mac_index = 0;
1854         /* Add this new filter to the list */
1855         if (vlan_id == 0)
1856                 STAILQ_INSERT_HEAD(&vnic->filter, filter, next);
1857         else
1858                 STAILQ_INSERT_TAIL(&vnic->filter, filter, next);
1859
1860         PMD_DRV_LOG(INFO,
1861                     "Added Vlan filter for %d\n", vlan_id);
1862         return rc;
1863 }
1864
1865 static int bnxt_vlan_filter_set_op(struct rte_eth_dev *eth_dev,
1866                 uint16_t vlan_id, int on)
1867 {
1868         struct bnxt *bp = eth_dev->data->dev_private;
1869         int rc;
1870
1871         rc = is_bnxt_in_error(bp);
1872         if (rc)
1873                 return rc;
1874
1875         /* These operations apply to ALL existing MAC/VLAN filters */
1876         if (on)
1877                 return bnxt_add_vlan_filter(bp, vlan_id);
1878         else
1879                 return bnxt_del_vlan_filter(bp, vlan_id);
1880 }
1881
1882 static int bnxt_del_dflt_mac_filter(struct bnxt *bp,
1883                                     struct bnxt_vnic_info *vnic)
1884 {
1885         struct bnxt_filter_info *filter;
1886         int rc;
1887
1888         filter = STAILQ_FIRST(&vnic->filter);
1889         while (filter) {
1890                 if (filter->mac_index == 0 &&
1891                     !memcmp(filter->l2_addr, bp->mac_addr,
1892                             RTE_ETHER_ADDR_LEN)) {
1893                         rc = bnxt_hwrm_clear_l2_filter(bp, filter);
1894                         if (!rc) {
1895                                 STAILQ_REMOVE(&vnic->filter, filter,
1896                                               bnxt_filter_info, next);
1897                                 bnxt_free_filter(bp, filter);
1898                         }
1899                         return rc;
1900                 }
1901                 filter = STAILQ_NEXT(filter, next);
1902         }
1903         return 0;
1904 }
1905
1906 static int
1907 bnxt_config_vlan_hw_filter(struct bnxt *bp, uint64_t rx_offloads)
1908 {
1909         struct bnxt_vnic_info *vnic;
1910         unsigned int i;
1911         int rc;
1912
1913         vnic = BNXT_GET_DEFAULT_VNIC(bp);
1914         if (!(rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER)) {
1915                 /* Remove any VLAN filters programmed */
1916                 for (i = 0; i < RTE_ETHER_MAX_VLAN_ID; i++)
1917                         bnxt_del_vlan_filter(bp, i);
1918
1919                 rc = bnxt_add_mac_filter(bp, vnic, NULL, 0, 0);
1920                 if (rc)
1921                         return rc;
1922         } else {
1923                 /* Default filter will allow packets that match the
1924                  * dest mac. So, it has to be deleted, otherwise, we
1925                  * will endup receiving vlan packets for which the
1926                  * filter is not programmed, when hw-vlan-filter
1927                  * configuration is ON
1928                  */
1929                 bnxt_del_dflt_mac_filter(bp, vnic);
1930                 /* This filter will allow only untagged packets */
1931                 bnxt_add_vlan_filter(bp, 0);
1932         }
1933         PMD_DRV_LOG(DEBUG, "VLAN Filtering: %d\n",
1934                     !!(rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER));
1935
1936         return 0;
1937 }
1938
1939 static int bnxt_free_one_vnic(struct bnxt *bp, uint16_t vnic_id)
1940 {
1941         struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id];
1942         unsigned int i;
1943         int rc;
1944
1945         /* Destroy vnic filters and vnic */
1946         if (bp->eth_dev->data->dev_conf.rxmode.offloads &
1947             DEV_RX_OFFLOAD_VLAN_FILTER) {
1948                 for (i = 0; i < RTE_ETHER_MAX_VLAN_ID; i++)
1949                         bnxt_del_vlan_filter(bp, i);
1950         }
1951         bnxt_del_dflt_mac_filter(bp, vnic);
1952
1953         rc = bnxt_hwrm_vnic_free(bp, vnic);
1954         if (rc)
1955                 return rc;
1956
1957         rte_free(vnic->fw_grp_ids);
1958         vnic->fw_grp_ids = NULL;
1959
1960         return 0;
1961 }
1962
1963 static int
1964 bnxt_config_vlan_hw_stripping(struct bnxt *bp, uint64_t rx_offloads)
1965 {
1966         struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp);
1967         int rc;
1968
1969         /* Destroy, recreate and reconfigure the default vnic */
1970         rc = bnxt_free_one_vnic(bp, 0);
1971         if (rc)
1972                 return rc;
1973
1974         /* default vnic 0 */
1975         rc = bnxt_setup_one_vnic(bp, 0);
1976         if (rc)
1977                 return rc;
1978
1979         if (bp->eth_dev->data->dev_conf.rxmode.offloads &
1980             DEV_RX_OFFLOAD_VLAN_FILTER) {
1981                 rc = bnxt_add_vlan_filter(bp, 0);
1982                 if (rc)
1983                         return rc;
1984                 rc = bnxt_restore_vlan_filters(bp);
1985                 if (rc)
1986                         return rc;
1987         } else {
1988                 rc = bnxt_add_mac_filter(bp, vnic, NULL, 0, 0);
1989                 if (rc)
1990                         return rc;
1991         }
1992
1993         rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1994         if (rc)
1995                 return rc;
1996
1997         PMD_DRV_LOG(DEBUG, "VLAN Strip Offload: %d\n",
1998                     !!(rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP));
1999
2000         return rc;
2001 }
2002
2003 static int
2004 bnxt_vlan_offload_set_op(struct rte_eth_dev *dev, int mask)
2005 {
2006         uint64_t rx_offloads = dev->data->dev_conf.rxmode.offloads;
2007         struct bnxt *bp = dev->data->dev_private;
2008         int rc;
2009
2010         rc = is_bnxt_in_error(bp);
2011         if (rc)
2012                 return rc;
2013
2014         /* Filter settings will get applied when port is started */
2015         if (!dev->data->dev_started)
2016                 return 0;
2017
2018         if (mask & ETH_VLAN_FILTER_MASK) {
2019                 /* Enable or disable VLAN filtering */
2020                 rc = bnxt_config_vlan_hw_filter(bp, rx_offloads);
2021                 if (rc)
2022                         return rc;
2023         }
2024
2025         if (mask & ETH_VLAN_STRIP_MASK) {
2026                 /* Enable or disable VLAN stripping */
2027                 rc = bnxt_config_vlan_hw_stripping(bp, rx_offloads);
2028                 if (rc)
2029                         return rc;
2030         }
2031
2032         if (mask & ETH_VLAN_EXTEND_MASK) {
2033                 if (rx_offloads & DEV_RX_OFFLOAD_VLAN_EXTEND)
2034                         PMD_DRV_LOG(DEBUG, "Extend VLAN supported\n");
2035                 else
2036                         PMD_DRV_LOG(INFO, "Extend VLAN unsupported\n");
2037         }
2038
2039         return 0;
2040 }
2041
2042 static int
2043 bnxt_vlan_tpid_set_op(struct rte_eth_dev *dev, enum rte_vlan_type vlan_type,
2044                       uint16_t tpid)
2045 {
2046         struct bnxt *bp = dev->data->dev_private;
2047         int qinq = dev->data->dev_conf.rxmode.offloads &
2048                    DEV_RX_OFFLOAD_VLAN_EXTEND;
2049
2050         if (vlan_type != ETH_VLAN_TYPE_INNER &&
2051             vlan_type != ETH_VLAN_TYPE_OUTER) {
2052                 PMD_DRV_LOG(ERR,
2053                             "Unsupported vlan type.");
2054                 return -EINVAL;
2055         }
2056         if (!qinq) {
2057                 PMD_DRV_LOG(ERR,
2058                             "QinQ not enabled. Needs to be ON as we can "
2059                             "accelerate only outer vlan\n");
2060                 return -EINVAL;
2061         }
2062
2063         if (vlan_type == ETH_VLAN_TYPE_OUTER) {
2064                 switch (tpid) {
2065                 case RTE_ETHER_TYPE_QINQ:
2066                         bp->outer_tpid_bd =
2067                                 TX_BD_LONG_CFA_META_VLAN_TPID_TPID88A8;
2068                                 break;
2069                 case RTE_ETHER_TYPE_VLAN:
2070                         bp->outer_tpid_bd =
2071                                 TX_BD_LONG_CFA_META_VLAN_TPID_TPID8100;
2072                                 break;
2073                 case 0x9100:
2074                         bp->outer_tpid_bd =
2075                                 TX_BD_LONG_CFA_META_VLAN_TPID_TPID9100;
2076                                 break;
2077                 case 0x9200:
2078                         bp->outer_tpid_bd =
2079                                 TX_BD_LONG_CFA_META_VLAN_TPID_TPID9200;
2080                                 break;
2081                 case 0x9300:
2082                         bp->outer_tpid_bd =
2083                                  TX_BD_LONG_CFA_META_VLAN_TPID_TPID9300;
2084                                 break;
2085                 default:
2086                         PMD_DRV_LOG(ERR, "Invalid TPID: %x\n", tpid);
2087                         return -EINVAL;
2088                 }
2089                 bp->outer_tpid_bd |= tpid;
2090                 PMD_DRV_LOG(INFO, "outer_tpid_bd = %x\n", bp->outer_tpid_bd);
2091         } else if (vlan_type == ETH_VLAN_TYPE_INNER) {
2092                 PMD_DRV_LOG(ERR,
2093                             "Can accelerate only outer vlan in QinQ\n");
2094                 return -EINVAL;
2095         }
2096
2097         return 0;
2098 }
2099
2100 static int
2101 bnxt_set_default_mac_addr_op(struct rte_eth_dev *dev,
2102                              struct rte_ether_addr *addr)
2103 {
2104         struct bnxt *bp = dev->data->dev_private;
2105         /* Default Filter is tied to VNIC 0 */
2106         struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp);
2107         int rc;
2108
2109         rc = is_bnxt_in_error(bp);
2110         if (rc)
2111                 return rc;
2112
2113         if (BNXT_VF(bp) && !BNXT_VF_IS_TRUSTED(bp))
2114                 return -EPERM;
2115
2116         if (rte_is_zero_ether_addr(addr))
2117                 return -EINVAL;
2118
2119         /* Filter settings will get applied when port is started */
2120         if (!dev->data->dev_started)
2121                 return 0;
2122
2123         /* Check if the requested MAC is already added */
2124         if (memcmp(addr, bp->mac_addr, RTE_ETHER_ADDR_LEN) == 0)
2125                 return 0;
2126
2127         /* Destroy filter and re-create it */
2128         bnxt_del_dflt_mac_filter(bp, vnic);
2129
2130         memcpy(bp->mac_addr, addr, RTE_ETHER_ADDR_LEN);
2131         if (dev->data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_VLAN_FILTER) {
2132                 /* This filter will allow only untagged packets */
2133                 rc = bnxt_add_vlan_filter(bp, 0);
2134         } else {
2135                 rc = bnxt_add_mac_filter(bp, vnic, addr, 0, 0);
2136         }
2137
2138         PMD_DRV_LOG(DEBUG, "Set MAC addr\n");
2139         return rc;
2140 }
2141
2142 static int
2143 bnxt_dev_set_mc_addr_list_op(struct rte_eth_dev *eth_dev,
2144                           struct rte_ether_addr *mc_addr_set,
2145                           uint32_t nb_mc_addr)
2146 {
2147         struct bnxt *bp = eth_dev->data->dev_private;
2148         char *mc_addr_list = (char *)mc_addr_set;
2149         struct bnxt_vnic_info *vnic;
2150         uint32_t off = 0, i = 0;
2151         int rc;
2152
2153         rc = is_bnxt_in_error(bp);
2154         if (rc)
2155                 return rc;
2156
2157         vnic = BNXT_GET_DEFAULT_VNIC(bp);
2158
2159         if (nb_mc_addr > BNXT_MAX_MC_ADDRS) {
2160                 vnic->flags |= BNXT_VNIC_INFO_ALLMULTI;
2161                 goto allmulti;
2162         }
2163
2164         /* TODO Check for Duplicate mcast addresses */
2165         vnic->flags &= ~BNXT_VNIC_INFO_ALLMULTI;
2166         for (i = 0; i < nb_mc_addr; i++) {
2167                 memcpy(vnic->mc_list + off, &mc_addr_list[i],
2168                         RTE_ETHER_ADDR_LEN);
2169                 off += RTE_ETHER_ADDR_LEN;
2170         }
2171
2172         vnic->mc_addr_cnt = i;
2173         if (vnic->mc_addr_cnt)
2174                 vnic->flags |= BNXT_VNIC_INFO_MCAST;
2175         else
2176                 vnic->flags &= ~BNXT_VNIC_INFO_MCAST;
2177
2178 allmulti:
2179         return bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
2180 }
2181
2182 static int
2183 bnxt_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size)
2184 {
2185         struct bnxt *bp = dev->data->dev_private;
2186         uint8_t fw_major = (bp->fw_ver >> 24) & 0xff;
2187         uint8_t fw_minor = (bp->fw_ver >> 16) & 0xff;
2188         uint8_t fw_updt = (bp->fw_ver >> 8) & 0xff;
2189         int ret;
2190
2191         ret = snprintf(fw_version, fw_size, "%d.%d.%d",
2192                         fw_major, fw_minor, fw_updt);
2193
2194         ret += 1; /* add the size of '\0' */
2195         if (fw_size < (uint32_t)ret)
2196                 return ret;
2197         else
2198                 return 0;
2199 }
2200
2201 static void
2202 bnxt_rxq_info_get_op(struct rte_eth_dev *dev, uint16_t queue_id,
2203         struct rte_eth_rxq_info *qinfo)
2204 {
2205         struct bnxt *bp = dev->data->dev_private;
2206         struct bnxt_rx_queue *rxq;
2207
2208         if (is_bnxt_in_error(bp))
2209                 return;
2210
2211         rxq = dev->data->rx_queues[queue_id];
2212
2213         qinfo->mp = rxq->mb_pool;
2214         qinfo->scattered_rx = dev->data->scattered_rx;
2215         qinfo->nb_desc = rxq->nb_rx_desc;
2216
2217         qinfo->conf.rx_free_thresh = rxq->rx_free_thresh;
2218         qinfo->conf.rx_drop_en = 0;
2219         qinfo->conf.rx_deferred_start = rxq->rx_deferred_start;
2220 }
2221
2222 static void
2223 bnxt_txq_info_get_op(struct rte_eth_dev *dev, uint16_t queue_id,
2224         struct rte_eth_txq_info *qinfo)
2225 {
2226         struct bnxt *bp = dev->data->dev_private;
2227         struct bnxt_tx_queue *txq;
2228
2229         if (is_bnxt_in_error(bp))
2230                 return;
2231
2232         txq = dev->data->tx_queues[queue_id];
2233
2234         qinfo->nb_desc = txq->nb_tx_desc;
2235
2236         qinfo->conf.tx_thresh.pthresh = txq->pthresh;
2237         qinfo->conf.tx_thresh.hthresh = txq->hthresh;
2238         qinfo->conf.tx_thresh.wthresh = txq->wthresh;
2239
2240         qinfo->conf.tx_free_thresh = txq->tx_free_thresh;
2241         qinfo->conf.tx_rs_thresh = 0;
2242         qinfo->conf.tx_deferred_start = txq->tx_deferred_start;
2243 }
2244
2245 int bnxt_mtu_set_op(struct rte_eth_dev *eth_dev, uint16_t new_mtu)
2246 {
2247         struct bnxt *bp = eth_dev->data->dev_private;
2248         uint32_t new_pkt_size;
2249         uint32_t rc = 0;
2250         uint32_t i;
2251
2252         rc = is_bnxt_in_error(bp);
2253         if (rc)
2254                 return rc;
2255
2256         /* Exit if receive queues are not configured yet */
2257         if (!eth_dev->data->nb_rx_queues)
2258                 return rc;
2259
2260         new_pkt_size = new_mtu + RTE_ETHER_HDR_LEN + RTE_ETHER_CRC_LEN +
2261                        VLAN_TAG_SIZE * BNXT_NUM_VLANS;
2262
2263 #ifdef RTE_ARCH_X86
2264         /*
2265          * If vector-mode tx/rx is active, disallow any MTU change that would
2266          * require scattered receive support.
2267          */
2268         if (eth_dev->data->dev_started &&
2269             (eth_dev->rx_pkt_burst == bnxt_recv_pkts_vec ||
2270              eth_dev->tx_pkt_burst == bnxt_xmit_pkts_vec) &&
2271             (new_pkt_size >
2272              eth_dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM)) {
2273                 PMD_DRV_LOG(ERR,
2274                             "MTU change would require scattered rx support. ");
2275                 PMD_DRV_LOG(ERR, "Stop port before changing MTU.\n");
2276                 return -EINVAL;
2277         }
2278 #endif
2279
2280         if (new_mtu > RTE_ETHER_MTU) {
2281                 bp->flags |= BNXT_FLAG_JUMBO;
2282                 bp->eth_dev->data->dev_conf.rxmode.offloads |=
2283                         DEV_RX_OFFLOAD_JUMBO_FRAME;
2284         } else {
2285                 bp->eth_dev->data->dev_conf.rxmode.offloads &=
2286                         ~DEV_RX_OFFLOAD_JUMBO_FRAME;
2287                 bp->flags &= ~BNXT_FLAG_JUMBO;
2288         }
2289
2290         /* Is there a change in mtu setting? */
2291         if (eth_dev->data->dev_conf.rxmode.max_rx_pkt_len == new_pkt_size)
2292                 return rc;
2293
2294         for (i = 0; i < bp->nr_vnics; i++) {
2295                 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
2296                 uint16_t size = 0;
2297
2298                 vnic->mru = BNXT_VNIC_MRU(new_mtu);
2299                 rc = bnxt_hwrm_vnic_cfg(bp, vnic);
2300                 if (rc)
2301                         break;
2302
2303                 size = rte_pktmbuf_data_room_size(bp->rx_queues[0]->mb_pool);
2304                 size -= RTE_PKTMBUF_HEADROOM;
2305
2306                 if (size < new_mtu) {
2307                         rc = bnxt_hwrm_vnic_plcmode_cfg(bp, vnic);
2308                         if (rc)
2309                                 return rc;
2310                 }
2311         }
2312
2313         if (!rc)
2314                 eth_dev->data->dev_conf.rxmode.max_rx_pkt_len = new_pkt_size;
2315
2316         PMD_DRV_LOG(INFO, "New MTU is %d\n", new_mtu);
2317
2318         return rc;
2319 }
2320
2321 static int
2322 bnxt_vlan_pvid_set_op(struct rte_eth_dev *dev, uint16_t pvid, int on)
2323 {
2324         struct bnxt *bp = dev->data->dev_private;
2325         uint16_t vlan = bp->vlan;
2326         int rc;
2327
2328         rc = is_bnxt_in_error(bp);
2329         if (rc)
2330                 return rc;
2331
2332         if (!BNXT_SINGLE_PF(bp) || BNXT_VF(bp)) {
2333                 PMD_DRV_LOG(ERR,
2334                         "PVID cannot be modified for this function\n");
2335                 return -ENOTSUP;
2336         }
2337         bp->vlan = on ? pvid : 0;
2338
2339         rc = bnxt_hwrm_set_default_vlan(bp, 0, 0);
2340         if (rc)
2341                 bp->vlan = vlan;
2342         return rc;
2343 }
2344
2345 static int
2346 bnxt_dev_led_on_op(struct rte_eth_dev *dev)
2347 {
2348         struct bnxt *bp = dev->data->dev_private;
2349         int rc;
2350
2351         rc = is_bnxt_in_error(bp);
2352         if (rc)
2353                 return rc;
2354
2355         return bnxt_hwrm_port_led_cfg(bp, true);
2356 }
2357
2358 static int
2359 bnxt_dev_led_off_op(struct rte_eth_dev *dev)
2360 {
2361         struct bnxt *bp = dev->data->dev_private;
2362         int rc;
2363
2364         rc = is_bnxt_in_error(bp);
2365         if (rc)
2366                 return rc;
2367
2368         return bnxt_hwrm_port_led_cfg(bp, false);
2369 }
2370
2371 static uint32_t
2372 bnxt_rx_queue_count_op(struct rte_eth_dev *dev, uint16_t rx_queue_id)
2373 {
2374         struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
2375         uint32_t desc = 0, raw_cons = 0, cons;
2376         struct bnxt_cp_ring_info *cpr;
2377         struct bnxt_rx_queue *rxq;
2378         struct rx_pkt_cmpl *rxcmp;
2379         int rc;
2380
2381         rc = is_bnxt_in_error(bp);
2382         if (rc)
2383                 return rc;
2384
2385         rxq = dev->data->rx_queues[rx_queue_id];
2386         cpr = rxq->cp_ring;
2387         raw_cons = cpr->cp_raw_cons;
2388
2389         while (1) {
2390                 cons = RING_CMP(cpr->cp_ring_struct, raw_cons);
2391                 rte_prefetch0(&cpr->cp_desc_ring[cons]);
2392                 rxcmp = (struct rx_pkt_cmpl *)&cpr->cp_desc_ring[cons];
2393
2394                 if (!CMP_VALID(rxcmp, raw_cons, cpr->cp_ring_struct)) {
2395                         break;
2396                 } else {
2397                         raw_cons++;
2398                         desc++;
2399                 }
2400         }
2401
2402         return desc;
2403 }
2404
2405 static int
2406 bnxt_rx_descriptor_status_op(void *rx_queue, uint16_t offset)
2407 {
2408         struct bnxt_rx_queue *rxq = (struct bnxt_rx_queue *)rx_queue;
2409         struct bnxt_rx_ring_info *rxr;
2410         struct bnxt_cp_ring_info *cpr;
2411         struct bnxt_sw_rx_bd *rx_buf;
2412         struct rx_pkt_cmpl *rxcmp;
2413         uint32_t cons, cp_cons;
2414         int rc;
2415
2416         if (!rxq)
2417                 return -EINVAL;
2418
2419         rc = is_bnxt_in_error(rxq->bp);
2420         if (rc)
2421                 return rc;
2422
2423         cpr = rxq->cp_ring;
2424         rxr = rxq->rx_ring;
2425
2426         if (offset >= rxq->nb_rx_desc)
2427                 return -EINVAL;
2428
2429         cons = RING_CMP(cpr->cp_ring_struct, offset);
2430         cp_cons = cpr->cp_raw_cons;
2431         rxcmp = (struct rx_pkt_cmpl *)&cpr->cp_desc_ring[cons];
2432
2433         if (cons > cp_cons) {
2434                 if (CMPL_VALID(rxcmp, cpr->valid))
2435                         return RTE_ETH_RX_DESC_DONE;
2436         } else {
2437                 if (CMPL_VALID(rxcmp, !cpr->valid))
2438                         return RTE_ETH_RX_DESC_DONE;
2439         }
2440         rx_buf = &rxr->rx_buf_ring[cons];
2441         if (rx_buf->mbuf == NULL)
2442                 return RTE_ETH_RX_DESC_UNAVAIL;
2443
2444
2445         return RTE_ETH_RX_DESC_AVAIL;
2446 }
2447
2448 static int
2449 bnxt_tx_descriptor_status_op(void *tx_queue, uint16_t offset)
2450 {
2451         struct bnxt_tx_queue *txq = (struct bnxt_tx_queue *)tx_queue;
2452         struct bnxt_tx_ring_info *txr;
2453         struct bnxt_cp_ring_info *cpr;
2454         struct bnxt_sw_tx_bd *tx_buf;
2455         struct tx_pkt_cmpl *txcmp;
2456         uint32_t cons, cp_cons;
2457         int rc;
2458
2459         if (!txq)
2460                 return -EINVAL;
2461
2462         rc = is_bnxt_in_error(txq->bp);
2463         if (rc)
2464                 return rc;
2465
2466         cpr = txq->cp_ring;
2467         txr = txq->tx_ring;
2468
2469         if (offset >= txq->nb_tx_desc)
2470                 return -EINVAL;
2471
2472         cons = RING_CMP(cpr->cp_ring_struct, offset);
2473         txcmp = (struct tx_pkt_cmpl *)&cpr->cp_desc_ring[cons];
2474         cp_cons = cpr->cp_raw_cons;
2475
2476         if (cons > cp_cons) {
2477                 if (CMPL_VALID(txcmp, cpr->valid))
2478                         return RTE_ETH_TX_DESC_UNAVAIL;
2479         } else {
2480                 if (CMPL_VALID(txcmp, !cpr->valid))
2481                         return RTE_ETH_TX_DESC_UNAVAIL;
2482         }
2483         tx_buf = &txr->tx_buf_ring[cons];
2484         if (tx_buf->mbuf == NULL)
2485                 return RTE_ETH_TX_DESC_DONE;
2486
2487         return RTE_ETH_TX_DESC_FULL;
2488 }
2489
2490 static struct bnxt_filter_info *
2491 bnxt_match_and_validate_ether_filter(struct bnxt *bp,
2492                                 struct rte_eth_ethertype_filter *efilter,
2493                                 struct bnxt_vnic_info *vnic0,
2494                                 struct bnxt_vnic_info *vnic,
2495                                 int *ret)
2496 {
2497         struct bnxt_filter_info *mfilter = NULL;
2498         int match = 0;
2499         *ret = 0;
2500
2501         if (efilter->ether_type == RTE_ETHER_TYPE_IPV4 ||
2502                 efilter->ether_type == RTE_ETHER_TYPE_IPV6) {
2503                 PMD_DRV_LOG(ERR, "invalid ether_type(0x%04x) in"
2504                         " ethertype filter.", efilter->ether_type);
2505                 *ret = -EINVAL;
2506                 goto exit;
2507         }
2508         if (efilter->queue >= bp->rx_nr_rings) {
2509                 PMD_DRV_LOG(ERR, "Invalid queue %d\n", efilter->queue);
2510                 *ret = -EINVAL;
2511                 goto exit;
2512         }
2513
2514         vnic0 = BNXT_GET_DEFAULT_VNIC(bp);
2515         vnic = &bp->vnic_info[efilter->queue];
2516         if (vnic == NULL) {
2517                 PMD_DRV_LOG(ERR, "Invalid queue %d\n", efilter->queue);
2518                 *ret = -EINVAL;
2519                 goto exit;
2520         }
2521
2522         if (efilter->flags & RTE_ETHTYPE_FLAGS_DROP) {
2523                 STAILQ_FOREACH(mfilter, &vnic0->filter, next) {
2524                         if ((!memcmp(efilter->mac_addr.addr_bytes,
2525                                      mfilter->l2_addr, RTE_ETHER_ADDR_LEN) &&
2526                              mfilter->flags ==
2527                              HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_DROP &&
2528                              mfilter->ethertype == efilter->ether_type)) {
2529                                 match = 1;
2530                                 break;
2531                         }
2532                 }
2533         } else {
2534                 STAILQ_FOREACH(mfilter, &vnic->filter, next)
2535                         if ((!memcmp(efilter->mac_addr.addr_bytes,
2536                                      mfilter->l2_addr, RTE_ETHER_ADDR_LEN) &&
2537                              mfilter->ethertype == efilter->ether_type &&
2538                              mfilter->flags ==
2539                              HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_PATH_RX)) {
2540                                 match = 1;
2541                                 break;
2542                         }
2543         }
2544
2545         if (match)
2546                 *ret = -EEXIST;
2547
2548 exit:
2549         return mfilter;
2550 }
2551
2552 static int
2553 bnxt_ethertype_filter(struct rte_eth_dev *dev,
2554                         enum rte_filter_op filter_op,
2555                         void *arg)
2556 {
2557         struct bnxt *bp = dev->data->dev_private;
2558         struct rte_eth_ethertype_filter *efilter =
2559                         (struct rte_eth_ethertype_filter *)arg;
2560         struct bnxt_filter_info *bfilter, *filter1;
2561         struct bnxt_vnic_info *vnic, *vnic0;
2562         int ret;
2563
2564         if (filter_op == RTE_ETH_FILTER_NOP)
2565                 return 0;
2566
2567         if (arg == NULL) {
2568                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
2569                             filter_op);
2570                 return -EINVAL;
2571         }
2572
2573         vnic0 = BNXT_GET_DEFAULT_VNIC(bp);
2574         vnic = &bp->vnic_info[efilter->queue];
2575
2576         switch (filter_op) {
2577         case RTE_ETH_FILTER_ADD:
2578                 bnxt_match_and_validate_ether_filter(bp, efilter,
2579                                                         vnic0, vnic, &ret);
2580                 if (ret < 0)
2581                         return ret;
2582
2583                 bfilter = bnxt_get_unused_filter(bp);
2584                 if (bfilter == NULL) {
2585                         PMD_DRV_LOG(ERR,
2586                                 "Not enough resources for a new filter.\n");
2587                         return -ENOMEM;
2588                 }
2589                 bfilter->filter_type = HWRM_CFA_NTUPLE_FILTER;
2590                 memcpy(bfilter->l2_addr, efilter->mac_addr.addr_bytes,
2591                        RTE_ETHER_ADDR_LEN);
2592                 memcpy(bfilter->dst_macaddr, efilter->mac_addr.addr_bytes,
2593                        RTE_ETHER_ADDR_LEN);
2594                 bfilter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_MACADDR;
2595                 bfilter->ethertype = efilter->ether_type;
2596                 bfilter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2597
2598                 filter1 = bnxt_get_l2_filter(bp, bfilter, vnic0);
2599                 if (filter1 == NULL) {
2600                         ret = -EINVAL;
2601                         goto cleanup;
2602                 }
2603                 bfilter->enables |=
2604                         HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID;
2605                 bfilter->fw_l2_filter_id = filter1->fw_l2_filter_id;
2606
2607                 bfilter->dst_id = vnic->fw_vnic_id;
2608
2609                 if (efilter->flags & RTE_ETHTYPE_FLAGS_DROP) {
2610                         bfilter->flags =
2611                                 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_DROP;
2612                 }
2613
2614                 ret = bnxt_hwrm_set_ntuple_filter(bp, bfilter->dst_id, bfilter);
2615                 if (ret)
2616                         goto cleanup;
2617                 STAILQ_INSERT_TAIL(&vnic->filter, bfilter, next);
2618                 break;
2619         case RTE_ETH_FILTER_DELETE:
2620                 filter1 = bnxt_match_and_validate_ether_filter(bp, efilter,
2621                                                         vnic0, vnic, &ret);
2622                 if (ret == -EEXIST) {
2623                         ret = bnxt_hwrm_clear_ntuple_filter(bp, filter1);
2624
2625                         STAILQ_REMOVE(&vnic->filter, filter1, bnxt_filter_info,
2626                                       next);
2627                         bnxt_free_filter(bp, filter1);
2628                 } else if (ret == 0) {
2629                         PMD_DRV_LOG(ERR, "No matching filter found\n");
2630                 }
2631                 break;
2632         default:
2633                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
2634                 ret = -EINVAL;
2635                 goto error;
2636         }
2637         return ret;
2638 cleanup:
2639         bnxt_free_filter(bp, bfilter);
2640 error:
2641         return ret;
2642 }
2643
2644 static inline int
2645 parse_ntuple_filter(struct bnxt *bp,
2646                     struct rte_eth_ntuple_filter *nfilter,
2647                     struct bnxt_filter_info *bfilter)
2648 {
2649         uint32_t en = 0;
2650
2651         if (nfilter->queue >= bp->rx_nr_rings) {
2652                 PMD_DRV_LOG(ERR, "Invalid queue %d\n", nfilter->queue);
2653                 return -EINVAL;
2654         }
2655
2656         switch (nfilter->dst_port_mask) {
2657         case UINT16_MAX:
2658                 bfilter->dst_port_mask = -1;
2659                 bfilter->dst_port = nfilter->dst_port;
2660                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT |
2661                         NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
2662                 break;
2663         default:
2664                 PMD_DRV_LOG(ERR, "invalid dst_port mask.");
2665                 return -EINVAL;
2666         }
2667
2668         bfilter->ip_addr_type = NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4;
2669         en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2670
2671         switch (nfilter->proto_mask) {
2672         case UINT8_MAX:
2673                 if (nfilter->proto == 17) /* IPPROTO_UDP */
2674                         bfilter->ip_protocol = 17;
2675                 else if (nfilter->proto == 6) /* IPPROTO_TCP */
2676                         bfilter->ip_protocol = 6;
2677                 else
2678                         return -EINVAL;
2679                 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2680                 break;
2681         default:
2682                 PMD_DRV_LOG(ERR, "invalid protocol mask.");
2683                 return -EINVAL;
2684         }
2685
2686         switch (nfilter->dst_ip_mask) {
2687         case UINT32_MAX:
2688                 bfilter->dst_ipaddr_mask[0] = -1;
2689                 bfilter->dst_ipaddr[0] = nfilter->dst_ip;
2690                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR |
2691                         NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2692                 break;
2693         default:
2694                 PMD_DRV_LOG(ERR, "invalid dst_ip mask.");
2695                 return -EINVAL;
2696         }
2697
2698         switch (nfilter->src_ip_mask) {
2699         case UINT32_MAX:
2700                 bfilter->src_ipaddr_mask[0] = -1;
2701                 bfilter->src_ipaddr[0] = nfilter->src_ip;
2702                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR |
2703                         NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2704                 break;
2705         default:
2706                 PMD_DRV_LOG(ERR, "invalid src_ip mask.");
2707                 return -EINVAL;
2708         }
2709
2710         switch (nfilter->src_port_mask) {
2711         case UINT16_MAX:
2712                 bfilter->src_port_mask = -1;
2713                 bfilter->src_port = nfilter->src_port;
2714                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT |
2715                         NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
2716                 break;
2717         default:
2718                 PMD_DRV_LOG(ERR, "invalid src_port mask.");
2719                 return -EINVAL;
2720         }
2721
2722         bfilter->enables = en;
2723         return 0;
2724 }
2725
2726 static struct bnxt_filter_info*
2727 bnxt_match_ntuple_filter(struct bnxt *bp,
2728                          struct bnxt_filter_info *bfilter,
2729                          struct bnxt_vnic_info **mvnic)
2730 {
2731         struct bnxt_filter_info *mfilter = NULL;
2732         int i;
2733
2734         for (i = bp->nr_vnics - 1; i >= 0; i--) {
2735                 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
2736                 STAILQ_FOREACH(mfilter, &vnic->filter, next) {
2737                         if (bfilter->src_ipaddr[0] == mfilter->src_ipaddr[0] &&
2738                             bfilter->src_ipaddr_mask[0] ==
2739                             mfilter->src_ipaddr_mask[0] &&
2740                             bfilter->src_port == mfilter->src_port &&
2741                             bfilter->src_port_mask == mfilter->src_port_mask &&
2742                             bfilter->dst_ipaddr[0] == mfilter->dst_ipaddr[0] &&
2743                             bfilter->dst_ipaddr_mask[0] ==
2744                             mfilter->dst_ipaddr_mask[0] &&
2745                             bfilter->dst_port == mfilter->dst_port &&
2746                             bfilter->dst_port_mask == mfilter->dst_port_mask &&
2747                             bfilter->flags == mfilter->flags &&
2748                             bfilter->enables == mfilter->enables) {
2749                                 if (mvnic)
2750                                         *mvnic = vnic;
2751                                 return mfilter;
2752                         }
2753                 }
2754         }
2755         return NULL;
2756 }
2757
2758 static int
2759 bnxt_cfg_ntuple_filter(struct bnxt *bp,
2760                        struct rte_eth_ntuple_filter *nfilter,
2761                        enum rte_filter_op filter_op)
2762 {
2763         struct bnxt_filter_info *bfilter, *mfilter, *filter1;
2764         struct bnxt_vnic_info *vnic, *vnic0, *mvnic;
2765         int ret;
2766
2767         if (nfilter->flags != RTE_5TUPLE_FLAGS) {
2768                 PMD_DRV_LOG(ERR, "only 5tuple is supported.");
2769                 return -EINVAL;
2770         }
2771
2772         if (nfilter->flags & RTE_NTUPLE_FLAGS_TCP_FLAG) {
2773                 PMD_DRV_LOG(ERR, "Ntuple filter: TCP flags not supported\n");
2774                 return -EINVAL;
2775         }
2776
2777         bfilter = bnxt_get_unused_filter(bp);
2778         if (bfilter == NULL) {
2779                 PMD_DRV_LOG(ERR,
2780                         "Not enough resources for a new filter.\n");
2781                 return -ENOMEM;
2782         }
2783         ret = parse_ntuple_filter(bp, nfilter, bfilter);
2784         if (ret < 0)
2785                 goto free_filter;
2786
2787         vnic = &bp->vnic_info[nfilter->queue];
2788         vnic0 = BNXT_GET_DEFAULT_VNIC(bp);
2789         filter1 = STAILQ_FIRST(&vnic0->filter);
2790         if (filter1 == NULL) {
2791                 ret = -EINVAL;
2792                 goto free_filter;
2793         }
2794
2795         bfilter->dst_id = vnic->fw_vnic_id;
2796         bfilter->fw_l2_filter_id = filter1->fw_l2_filter_id;
2797         bfilter->enables |=
2798                 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID;
2799         bfilter->ethertype = 0x800;
2800         bfilter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2801
2802         mfilter = bnxt_match_ntuple_filter(bp, bfilter, &mvnic);
2803
2804         if (mfilter != NULL && filter_op == RTE_ETH_FILTER_ADD &&
2805             bfilter->dst_id == mfilter->dst_id) {
2806                 PMD_DRV_LOG(ERR, "filter exists.\n");
2807                 ret = -EEXIST;
2808                 goto free_filter;
2809         } else if (mfilter != NULL && filter_op == RTE_ETH_FILTER_ADD &&
2810                    bfilter->dst_id != mfilter->dst_id) {
2811                 mfilter->dst_id = vnic->fw_vnic_id;
2812                 ret = bnxt_hwrm_set_ntuple_filter(bp, mfilter->dst_id, mfilter);
2813                 STAILQ_REMOVE(&mvnic->filter, mfilter, bnxt_filter_info, next);
2814                 STAILQ_INSERT_TAIL(&vnic->filter, mfilter, next);
2815                 PMD_DRV_LOG(ERR, "filter with matching pattern exists.\n");
2816                 PMD_DRV_LOG(ERR, " Updated it to the new destination queue\n");
2817                 goto free_filter;
2818         }
2819         if (mfilter == NULL && filter_op == RTE_ETH_FILTER_DELETE) {
2820                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
2821                 ret = -ENOENT;
2822                 goto free_filter;
2823         }
2824
2825         if (filter_op == RTE_ETH_FILTER_ADD) {
2826                 bfilter->filter_type = HWRM_CFA_NTUPLE_FILTER;
2827                 ret = bnxt_hwrm_set_ntuple_filter(bp, bfilter->dst_id, bfilter);
2828                 if (ret)
2829                         goto free_filter;
2830                 STAILQ_INSERT_TAIL(&vnic->filter, bfilter, next);
2831         } else {
2832                 if (mfilter == NULL) {
2833                         /* This should not happen. But for Coverity! */
2834                         ret = -ENOENT;
2835                         goto free_filter;
2836                 }
2837                 ret = bnxt_hwrm_clear_ntuple_filter(bp, mfilter);
2838
2839                 STAILQ_REMOVE(&vnic->filter, mfilter, bnxt_filter_info, next);
2840                 bnxt_free_filter(bp, mfilter);
2841                 bnxt_free_filter(bp, bfilter);
2842         }
2843
2844         return 0;
2845 free_filter:
2846         bnxt_free_filter(bp, bfilter);
2847         return ret;
2848 }
2849
2850 static int
2851 bnxt_ntuple_filter(struct rte_eth_dev *dev,
2852                         enum rte_filter_op filter_op,
2853                         void *arg)
2854 {
2855         struct bnxt *bp = dev->data->dev_private;
2856         int ret;
2857
2858         if (filter_op == RTE_ETH_FILTER_NOP)
2859                 return 0;
2860
2861         if (arg == NULL) {
2862                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
2863                             filter_op);
2864                 return -EINVAL;
2865         }
2866
2867         switch (filter_op) {
2868         case RTE_ETH_FILTER_ADD:
2869                 ret = bnxt_cfg_ntuple_filter(bp,
2870                         (struct rte_eth_ntuple_filter *)arg,
2871                         filter_op);
2872                 break;
2873         case RTE_ETH_FILTER_DELETE:
2874                 ret = bnxt_cfg_ntuple_filter(bp,
2875                         (struct rte_eth_ntuple_filter *)arg,
2876                         filter_op);
2877                 break;
2878         default:
2879                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
2880                 ret = -EINVAL;
2881                 break;
2882         }
2883         return ret;
2884 }
2885
2886 static int
2887 bnxt_parse_fdir_filter(struct bnxt *bp,
2888                        struct rte_eth_fdir_filter *fdir,
2889                        struct bnxt_filter_info *filter)
2890 {
2891         enum rte_fdir_mode fdir_mode =
2892                 bp->eth_dev->data->dev_conf.fdir_conf.mode;
2893         struct bnxt_vnic_info *vnic0, *vnic;
2894         struct bnxt_filter_info *filter1;
2895         uint32_t en = 0;
2896         int i;
2897
2898         if (fdir_mode == RTE_FDIR_MODE_PERFECT_TUNNEL)
2899                 return -EINVAL;
2900
2901         filter->l2_ovlan = fdir->input.flow_ext.vlan_tci;
2902         en |= EM_FLOW_ALLOC_INPUT_EN_OVLAN_VID;
2903
2904         switch (fdir->input.flow_type) {
2905         case RTE_ETH_FLOW_IPV4:
2906         case RTE_ETH_FLOW_NONFRAG_IPV4_OTHER:
2907                 /* FALLTHROUGH */
2908                 filter->src_ipaddr[0] = fdir->input.flow.ip4_flow.src_ip;
2909                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
2910                 filter->dst_ipaddr[0] = fdir->input.flow.ip4_flow.dst_ip;
2911                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
2912                 filter->ip_protocol = fdir->input.flow.ip4_flow.proto;
2913                 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2914                 filter->ip_addr_type =
2915                         NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4;
2916                 filter->src_ipaddr_mask[0] = 0xffffffff;
2917                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2918                 filter->dst_ipaddr_mask[0] = 0xffffffff;
2919                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2920                 filter->ethertype = 0x800;
2921                 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2922                 break;
2923         case RTE_ETH_FLOW_NONFRAG_IPV4_TCP:
2924                 filter->src_port = fdir->input.flow.tcp4_flow.src_port;
2925                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT;
2926                 filter->dst_port = fdir->input.flow.tcp4_flow.dst_port;
2927                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT;
2928                 filter->dst_port_mask = 0xffff;
2929                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
2930                 filter->src_port_mask = 0xffff;
2931                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
2932                 filter->src_ipaddr[0] = fdir->input.flow.tcp4_flow.ip.src_ip;
2933                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
2934                 filter->dst_ipaddr[0] = fdir->input.flow.tcp4_flow.ip.dst_ip;
2935                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
2936                 filter->ip_protocol = 6;
2937                 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2938                 filter->ip_addr_type =
2939                         NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4;
2940                 filter->src_ipaddr_mask[0] = 0xffffffff;
2941                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2942                 filter->dst_ipaddr_mask[0] = 0xffffffff;
2943                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2944                 filter->ethertype = 0x800;
2945                 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2946                 break;
2947         case RTE_ETH_FLOW_NONFRAG_IPV4_UDP:
2948                 filter->src_port = fdir->input.flow.udp4_flow.src_port;
2949                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT;
2950                 filter->dst_port = fdir->input.flow.udp4_flow.dst_port;
2951                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT;
2952                 filter->dst_port_mask = 0xffff;
2953                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
2954                 filter->src_port_mask = 0xffff;
2955                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
2956                 filter->src_ipaddr[0] = fdir->input.flow.udp4_flow.ip.src_ip;
2957                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
2958                 filter->dst_ipaddr[0] = fdir->input.flow.udp4_flow.ip.dst_ip;
2959                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
2960                 filter->ip_protocol = 17;
2961                 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2962                 filter->ip_addr_type =
2963                         NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4;
2964                 filter->src_ipaddr_mask[0] = 0xffffffff;
2965                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2966                 filter->dst_ipaddr_mask[0] = 0xffffffff;
2967                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2968                 filter->ethertype = 0x800;
2969                 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2970                 break;
2971         case RTE_ETH_FLOW_IPV6:
2972         case RTE_ETH_FLOW_NONFRAG_IPV6_OTHER:
2973                 /* FALLTHROUGH */
2974                 filter->ip_addr_type =
2975                         NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV6;
2976                 filter->ip_protocol = fdir->input.flow.ipv6_flow.proto;
2977                 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2978                 rte_memcpy(filter->src_ipaddr,
2979                            fdir->input.flow.ipv6_flow.src_ip, 16);
2980                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
2981                 rte_memcpy(filter->dst_ipaddr,
2982                            fdir->input.flow.ipv6_flow.dst_ip, 16);
2983                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
2984                 memset(filter->dst_ipaddr_mask, 0xff, 16);
2985                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2986                 memset(filter->src_ipaddr_mask, 0xff, 16);
2987                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2988                 filter->ethertype = 0x86dd;
2989                 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2990                 break;
2991         case RTE_ETH_FLOW_NONFRAG_IPV6_TCP:
2992                 filter->src_port = fdir->input.flow.tcp6_flow.src_port;
2993                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT;
2994                 filter->dst_port = fdir->input.flow.tcp6_flow.dst_port;
2995                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT;
2996                 filter->dst_port_mask = 0xffff;
2997                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
2998                 filter->src_port_mask = 0xffff;
2999                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
3000                 filter->ip_addr_type =
3001                         NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV6;
3002                 filter->ip_protocol = fdir->input.flow.tcp6_flow.ip.proto;
3003                 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
3004                 rte_memcpy(filter->src_ipaddr,
3005                            fdir->input.flow.tcp6_flow.ip.src_ip, 16);
3006                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
3007                 rte_memcpy(filter->dst_ipaddr,
3008                            fdir->input.flow.tcp6_flow.ip.dst_ip, 16);
3009                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
3010                 memset(filter->dst_ipaddr_mask, 0xff, 16);
3011                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
3012                 memset(filter->src_ipaddr_mask, 0xff, 16);
3013                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
3014                 filter->ethertype = 0x86dd;
3015                 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
3016                 break;
3017         case RTE_ETH_FLOW_NONFRAG_IPV6_UDP:
3018                 filter->src_port = fdir->input.flow.udp6_flow.src_port;
3019                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT;
3020                 filter->dst_port = fdir->input.flow.udp6_flow.dst_port;
3021                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT;
3022                 filter->dst_port_mask = 0xffff;
3023                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
3024                 filter->src_port_mask = 0xffff;
3025                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
3026                 filter->ip_addr_type =
3027                         NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV6;
3028                 filter->ip_protocol = fdir->input.flow.udp6_flow.ip.proto;
3029                 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
3030                 rte_memcpy(filter->src_ipaddr,
3031                            fdir->input.flow.udp6_flow.ip.src_ip, 16);
3032                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
3033                 rte_memcpy(filter->dst_ipaddr,
3034                            fdir->input.flow.udp6_flow.ip.dst_ip, 16);
3035                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
3036                 memset(filter->dst_ipaddr_mask, 0xff, 16);
3037                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
3038                 memset(filter->src_ipaddr_mask, 0xff, 16);
3039                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
3040                 filter->ethertype = 0x86dd;
3041                 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
3042                 break;
3043         case RTE_ETH_FLOW_L2_PAYLOAD:
3044                 filter->ethertype = fdir->input.flow.l2_flow.ether_type;
3045                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
3046                 break;
3047         case RTE_ETH_FLOW_VXLAN:
3048                 if (fdir->action.behavior == RTE_ETH_FDIR_REJECT)
3049                         return -EINVAL;
3050                 filter->vni = fdir->input.flow.tunnel_flow.tunnel_id;
3051                 filter->tunnel_type =
3052                         CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN;
3053                 en |= HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_TUNNEL_TYPE;
3054                 break;
3055         case RTE_ETH_FLOW_NVGRE:
3056                 if (fdir->action.behavior == RTE_ETH_FDIR_REJECT)
3057                         return -EINVAL;
3058                 filter->vni = fdir->input.flow.tunnel_flow.tunnel_id;
3059                 filter->tunnel_type =
3060                         CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_NVGRE;
3061                 en |= HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_TUNNEL_TYPE;
3062                 break;
3063         case RTE_ETH_FLOW_UNKNOWN:
3064         case RTE_ETH_FLOW_RAW:
3065         case RTE_ETH_FLOW_FRAG_IPV4:
3066         case RTE_ETH_FLOW_NONFRAG_IPV4_SCTP:
3067         case RTE_ETH_FLOW_FRAG_IPV6:
3068         case RTE_ETH_FLOW_NONFRAG_IPV6_SCTP:
3069         case RTE_ETH_FLOW_IPV6_EX:
3070         case RTE_ETH_FLOW_IPV6_TCP_EX:
3071         case RTE_ETH_FLOW_IPV6_UDP_EX:
3072         case RTE_ETH_FLOW_GENEVE:
3073                 /* FALLTHROUGH */
3074         default:
3075                 return -EINVAL;
3076         }
3077
3078         vnic0 = BNXT_GET_DEFAULT_VNIC(bp);
3079         vnic = &bp->vnic_info[fdir->action.rx_queue];
3080         if (vnic == NULL) {
3081                 PMD_DRV_LOG(ERR, "Invalid queue %d\n", fdir->action.rx_queue);
3082                 return -EINVAL;
3083         }
3084
3085         if (fdir_mode == RTE_FDIR_MODE_PERFECT_MAC_VLAN) {
3086                 rte_memcpy(filter->dst_macaddr,
3087                         fdir->input.flow.mac_vlan_flow.mac_addr.addr_bytes, 6);
3088                         en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_MACADDR;
3089         }
3090
3091         if (fdir->action.behavior == RTE_ETH_FDIR_REJECT) {
3092                 filter->flags = HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_DROP;
3093                 filter1 = STAILQ_FIRST(&vnic0->filter);
3094                 //filter1 = bnxt_get_l2_filter(bp, filter, vnic0);
3095         } else {
3096                 filter->dst_id = vnic->fw_vnic_id;
3097                 for (i = 0; i < RTE_ETHER_ADDR_LEN; i++)
3098                         if (filter->dst_macaddr[i] == 0x00)
3099                                 filter1 = STAILQ_FIRST(&vnic0->filter);
3100                         else
3101                                 filter1 = bnxt_get_l2_filter(bp, filter, vnic);
3102         }
3103
3104         if (filter1 == NULL)
3105                 return -EINVAL;
3106
3107         en |= HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID;
3108         filter->fw_l2_filter_id = filter1->fw_l2_filter_id;
3109
3110         filter->enables = en;
3111
3112         return 0;
3113 }
3114
3115 static struct bnxt_filter_info *
3116 bnxt_match_fdir(struct bnxt *bp, struct bnxt_filter_info *nf,
3117                 struct bnxt_vnic_info **mvnic)
3118 {
3119         struct bnxt_filter_info *mf = NULL;
3120         int i;
3121
3122         for (i = bp->nr_vnics - 1; i >= 0; i--) {
3123                 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
3124
3125                 STAILQ_FOREACH(mf, &vnic->filter, next) {
3126                         if (mf->filter_type == nf->filter_type &&
3127                             mf->flags == nf->flags &&
3128                             mf->src_port == nf->src_port &&
3129                             mf->src_port_mask == nf->src_port_mask &&
3130                             mf->dst_port == nf->dst_port &&
3131                             mf->dst_port_mask == nf->dst_port_mask &&
3132                             mf->ip_protocol == nf->ip_protocol &&
3133                             mf->ip_addr_type == nf->ip_addr_type &&
3134                             mf->ethertype == nf->ethertype &&
3135                             mf->vni == nf->vni &&
3136                             mf->tunnel_type == nf->tunnel_type &&
3137                             mf->l2_ovlan == nf->l2_ovlan &&
3138                             mf->l2_ovlan_mask == nf->l2_ovlan_mask &&
3139                             mf->l2_ivlan == nf->l2_ivlan &&
3140                             mf->l2_ivlan_mask == nf->l2_ivlan_mask &&
3141                             !memcmp(mf->l2_addr, nf->l2_addr,
3142                                     RTE_ETHER_ADDR_LEN) &&
3143                             !memcmp(mf->l2_addr_mask, nf->l2_addr_mask,
3144                                     RTE_ETHER_ADDR_LEN) &&
3145                             !memcmp(mf->src_macaddr, nf->src_macaddr,
3146                                     RTE_ETHER_ADDR_LEN) &&
3147                             !memcmp(mf->dst_macaddr, nf->dst_macaddr,
3148                                     RTE_ETHER_ADDR_LEN) &&
3149                             !memcmp(mf->src_ipaddr, nf->src_ipaddr,
3150                                     sizeof(nf->src_ipaddr)) &&
3151                             !memcmp(mf->src_ipaddr_mask, nf->src_ipaddr_mask,
3152                                     sizeof(nf->src_ipaddr_mask)) &&
3153                             !memcmp(mf->dst_ipaddr, nf->dst_ipaddr,
3154                                     sizeof(nf->dst_ipaddr)) &&
3155                             !memcmp(mf->dst_ipaddr_mask, nf->dst_ipaddr_mask,
3156                                     sizeof(nf->dst_ipaddr_mask))) {
3157                                 if (mvnic)
3158                                         *mvnic = vnic;
3159                                 return mf;
3160                         }
3161                 }
3162         }
3163         return NULL;
3164 }
3165
3166 static int
3167 bnxt_fdir_filter(struct rte_eth_dev *dev,
3168                  enum rte_filter_op filter_op,
3169                  void *arg)
3170 {
3171         struct bnxt *bp = dev->data->dev_private;
3172         struct rte_eth_fdir_filter *fdir  = (struct rte_eth_fdir_filter *)arg;
3173         struct bnxt_filter_info *filter, *match;
3174         struct bnxt_vnic_info *vnic, *mvnic;
3175         int ret = 0, i;
3176
3177         if (filter_op == RTE_ETH_FILTER_NOP)
3178                 return 0;
3179
3180         if (arg == NULL && filter_op != RTE_ETH_FILTER_FLUSH)
3181                 return -EINVAL;
3182
3183         switch (filter_op) {
3184         case RTE_ETH_FILTER_ADD:
3185         case RTE_ETH_FILTER_DELETE:
3186                 /* FALLTHROUGH */
3187                 filter = bnxt_get_unused_filter(bp);
3188                 if (filter == NULL) {
3189                         PMD_DRV_LOG(ERR,
3190                                 "Not enough resources for a new flow.\n");
3191                         return -ENOMEM;
3192                 }
3193
3194                 ret = bnxt_parse_fdir_filter(bp, fdir, filter);
3195                 if (ret != 0)
3196                         goto free_filter;
3197                 filter->filter_type = HWRM_CFA_NTUPLE_FILTER;
3198
3199                 if (fdir->action.behavior == RTE_ETH_FDIR_REJECT)
3200                         vnic = &bp->vnic_info[0];
3201                 else
3202                         vnic = &bp->vnic_info[fdir->action.rx_queue];
3203
3204                 match = bnxt_match_fdir(bp, filter, &mvnic);
3205                 if (match != NULL && filter_op == RTE_ETH_FILTER_ADD) {
3206                         if (match->dst_id == vnic->fw_vnic_id) {
3207                                 PMD_DRV_LOG(ERR, "Flow already exists.\n");
3208                                 ret = -EEXIST;
3209                                 goto free_filter;
3210                         } else {
3211                                 match->dst_id = vnic->fw_vnic_id;
3212                                 ret = bnxt_hwrm_set_ntuple_filter(bp,
3213                                                                   match->dst_id,
3214                                                                   match);
3215                                 STAILQ_REMOVE(&mvnic->filter, match,
3216                                               bnxt_filter_info, next);
3217                                 STAILQ_INSERT_TAIL(&vnic->filter, match, next);
3218                                 PMD_DRV_LOG(ERR,
3219                                         "Filter with matching pattern exist\n");
3220                                 PMD_DRV_LOG(ERR,
3221                                         "Updated it to new destination q\n");
3222                                 goto free_filter;
3223                         }
3224                 }
3225                 if (match == NULL && filter_op == RTE_ETH_FILTER_DELETE) {
3226                         PMD_DRV_LOG(ERR, "Flow does not exist.\n");
3227                         ret = -ENOENT;
3228                         goto free_filter;
3229                 }
3230
3231                 if (filter_op == RTE_ETH_FILTER_ADD) {
3232                         ret = bnxt_hwrm_set_ntuple_filter(bp,
3233                                                           filter->dst_id,
3234                                                           filter);
3235                         if (ret)
3236                                 goto free_filter;
3237                         STAILQ_INSERT_TAIL(&vnic->filter, filter, next);
3238                 } else {
3239                         ret = bnxt_hwrm_clear_ntuple_filter(bp, match);
3240                         STAILQ_REMOVE(&vnic->filter, match,
3241                                       bnxt_filter_info, next);
3242                         bnxt_free_filter(bp, match);
3243                         bnxt_free_filter(bp, filter);
3244                 }
3245                 break;
3246         case RTE_ETH_FILTER_FLUSH:
3247                 for (i = bp->nr_vnics - 1; i >= 0; i--) {
3248                         struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
3249
3250                         STAILQ_FOREACH(filter, &vnic->filter, next) {
3251                                 if (filter->filter_type ==
3252                                     HWRM_CFA_NTUPLE_FILTER) {
3253                                         ret =
3254                                         bnxt_hwrm_clear_ntuple_filter(bp,
3255                                                                       filter);
3256                                         STAILQ_REMOVE(&vnic->filter, filter,
3257                                                       bnxt_filter_info, next);
3258                                 }
3259                         }
3260                 }
3261                 return ret;
3262         case RTE_ETH_FILTER_UPDATE:
3263         case RTE_ETH_FILTER_STATS:
3264         case RTE_ETH_FILTER_INFO:
3265                 PMD_DRV_LOG(ERR, "operation %u not implemented", filter_op);
3266                 break;
3267         default:
3268                 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
3269                 ret = -EINVAL;
3270                 break;
3271         }
3272         return ret;
3273
3274 free_filter:
3275         bnxt_free_filter(bp, filter);
3276         return ret;
3277 }
3278
3279 static int
3280 bnxt_filter_ctrl_op(struct rte_eth_dev *dev,
3281                     enum rte_filter_type filter_type,
3282                     enum rte_filter_op filter_op, void *arg)
3283 {
3284         int ret = 0;
3285
3286         ret = is_bnxt_in_error(dev->data->dev_private);
3287         if (ret)
3288                 return ret;
3289
3290         switch (filter_type) {
3291         case RTE_ETH_FILTER_TUNNEL:
3292                 PMD_DRV_LOG(ERR,
3293                         "filter type: %d: To be implemented\n", filter_type);
3294                 break;
3295         case RTE_ETH_FILTER_FDIR:
3296                 ret = bnxt_fdir_filter(dev, filter_op, arg);
3297                 break;
3298         case RTE_ETH_FILTER_NTUPLE:
3299                 ret = bnxt_ntuple_filter(dev, filter_op, arg);
3300                 break;
3301         case RTE_ETH_FILTER_ETHERTYPE:
3302                 ret = bnxt_ethertype_filter(dev, filter_op, arg);
3303                 break;
3304         case RTE_ETH_FILTER_GENERIC:
3305                 if (filter_op != RTE_ETH_FILTER_GET)
3306                         return -EINVAL;
3307                 *(const void **)arg = &bnxt_flow_ops;
3308                 break;
3309         default:
3310                 PMD_DRV_LOG(ERR,
3311                         "Filter type (%d) not supported", filter_type);
3312                 ret = -EINVAL;
3313                 break;
3314         }
3315         return ret;
3316 }
3317
3318 static const uint32_t *
3319 bnxt_dev_supported_ptypes_get_op(struct rte_eth_dev *dev)
3320 {
3321         static const uint32_t ptypes[] = {
3322                 RTE_PTYPE_L2_ETHER_VLAN,
3323                 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN,
3324                 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN,
3325                 RTE_PTYPE_L4_ICMP,
3326                 RTE_PTYPE_L4_TCP,
3327                 RTE_PTYPE_L4_UDP,
3328                 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN,
3329                 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN,
3330                 RTE_PTYPE_INNER_L4_ICMP,
3331                 RTE_PTYPE_INNER_L4_TCP,
3332                 RTE_PTYPE_INNER_L4_UDP,
3333                 RTE_PTYPE_UNKNOWN
3334         };
3335
3336         if (!dev->rx_pkt_burst)
3337                 return NULL;
3338
3339         return ptypes;
3340 }
3341
3342 static int bnxt_map_regs(struct bnxt *bp, uint32_t *reg_arr, int count,
3343                          int reg_win)
3344 {
3345         uint32_t reg_base = *reg_arr & 0xfffff000;
3346         uint32_t win_off;
3347         int i;
3348
3349         for (i = 0; i < count; i++) {
3350                 if ((reg_arr[i] & 0xfffff000) != reg_base)
3351                         return -ERANGE;
3352         }
3353         win_off = BNXT_GRCPF_REG_WINDOW_BASE_OUT + (reg_win - 1) * 4;
3354         rte_write32(reg_base, (uint8_t *)bp->bar0 + win_off);
3355         return 0;
3356 }
3357
3358 static int bnxt_map_ptp_regs(struct bnxt *bp)
3359 {
3360         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3361         uint32_t *reg_arr;
3362         int rc, i;
3363
3364         reg_arr = ptp->rx_regs;
3365         rc = bnxt_map_regs(bp, reg_arr, BNXT_PTP_RX_REGS, 5);
3366         if (rc)
3367                 return rc;
3368
3369         reg_arr = ptp->tx_regs;
3370         rc = bnxt_map_regs(bp, reg_arr, BNXT_PTP_TX_REGS, 6);
3371         if (rc)
3372                 return rc;
3373
3374         for (i = 0; i < BNXT_PTP_RX_REGS; i++)
3375                 ptp->rx_mapped_regs[i] = 0x5000 + (ptp->rx_regs[i] & 0xfff);
3376
3377         for (i = 0; i < BNXT_PTP_TX_REGS; i++)
3378                 ptp->tx_mapped_regs[i] = 0x6000 + (ptp->tx_regs[i] & 0xfff);
3379
3380         return 0;
3381 }
3382
3383 static void bnxt_unmap_ptp_regs(struct bnxt *bp)
3384 {
3385         rte_write32(0, (uint8_t *)bp->bar0 +
3386                          BNXT_GRCPF_REG_WINDOW_BASE_OUT + 16);
3387         rte_write32(0, (uint8_t *)bp->bar0 +
3388                          BNXT_GRCPF_REG_WINDOW_BASE_OUT + 20);
3389 }
3390
3391 static uint64_t bnxt_cc_read(struct bnxt *bp)
3392 {
3393         uint64_t ns;
3394
3395         ns = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3396                               BNXT_GRCPF_REG_SYNC_TIME));
3397         ns |= (uint64_t)(rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3398                                           BNXT_GRCPF_REG_SYNC_TIME + 4))) << 32;
3399         return ns;
3400 }
3401
3402 static int bnxt_get_tx_ts(struct bnxt *bp, uint64_t *ts)
3403 {
3404         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3405         uint32_t fifo;
3406
3407         fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3408                                 ptp->tx_mapped_regs[BNXT_PTP_TX_FIFO]));
3409         if (fifo & BNXT_PTP_TX_FIFO_EMPTY)
3410                 return -EAGAIN;
3411
3412         fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3413                                 ptp->tx_mapped_regs[BNXT_PTP_TX_FIFO]));
3414         *ts = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3415                                 ptp->tx_mapped_regs[BNXT_PTP_TX_TS_L]));
3416         *ts |= (uint64_t)rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3417                                 ptp->tx_mapped_regs[BNXT_PTP_TX_TS_H])) << 32;
3418
3419         return 0;
3420 }
3421
3422 static int bnxt_get_rx_ts(struct bnxt *bp, uint64_t *ts)
3423 {
3424         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3425         struct bnxt_pf_info *pf = &bp->pf;
3426         uint16_t port_id;
3427         uint32_t fifo;
3428
3429         if (!ptp)
3430                 return -ENODEV;
3431
3432         fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3433                                 ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO]));
3434         if (!(fifo & BNXT_PTP_RX_FIFO_PENDING))
3435                 return -EAGAIN;
3436
3437         port_id = pf->port_id;
3438         rte_write32(1 << port_id, (uint8_t *)bp->bar0 +
3439                ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO_ADV]);
3440
3441         fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3442                                    ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO]));
3443         if (fifo & BNXT_PTP_RX_FIFO_PENDING) {
3444 /*              bnxt_clr_rx_ts(bp);       TBD  */
3445                 return -EBUSY;
3446         }
3447
3448         *ts = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3449                                 ptp->rx_mapped_regs[BNXT_PTP_RX_TS_L]));
3450         *ts |= (uint64_t)rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3451                                 ptp->rx_mapped_regs[BNXT_PTP_RX_TS_H])) << 32;
3452
3453         return 0;
3454 }
3455
3456 static int
3457 bnxt_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
3458 {
3459         uint64_t ns;
3460         struct bnxt *bp = dev->data->dev_private;
3461         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3462
3463         if (!ptp)
3464                 return 0;
3465
3466         ns = rte_timespec_to_ns(ts);
3467         /* Set the timecounters to a new value. */
3468         ptp->tc.nsec = ns;
3469
3470         return 0;
3471 }
3472
3473 static int
3474 bnxt_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
3475 {
3476         struct bnxt *bp = dev->data->dev_private;
3477         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3478         uint64_t ns, systime_cycles = 0;
3479         int rc = 0;
3480
3481         if (!ptp)
3482                 return 0;
3483
3484         if (BNXT_CHIP_THOR(bp))
3485                 rc = bnxt_hwrm_port_ts_query(bp, BNXT_PTP_FLAGS_CURRENT_TIME,
3486                                              &systime_cycles);
3487         else
3488                 systime_cycles = bnxt_cc_read(bp);
3489
3490         ns = rte_timecounter_update(&ptp->tc, systime_cycles);
3491         *ts = rte_ns_to_timespec(ns);
3492
3493         return rc;
3494 }
3495 static int
3496 bnxt_timesync_enable(struct rte_eth_dev *dev)
3497 {
3498         struct bnxt *bp = dev->data->dev_private;
3499         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3500         uint32_t shift = 0;
3501         int rc;
3502
3503         if (!ptp)
3504                 return 0;
3505
3506         ptp->rx_filter = 1;
3507         ptp->tx_tstamp_en = 1;
3508         ptp->rxctl = BNXT_PTP_MSG_EVENTS;
3509
3510         rc = bnxt_hwrm_ptp_cfg(bp);
3511         if (rc)
3512                 return rc;
3513
3514         memset(&ptp->tc, 0, sizeof(struct rte_timecounter));
3515         memset(&ptp->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
3516         memset(&ptp->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
3517
3518         ptp->tc.cc_mask = BNXT_CYCLECOUNTER_MASK;
3519         ptp->tc.cc_shift = shift;
3520         ptp->tc.nsec_mask = (1ULL << shift) - 1;
3521
3522         ptp->rx_tstamp_tc.cc_mask = BNXT_CYCLECOUNTER_MASK;
3523         ptp->rx_tstamp_tc.cc_shift = shift;
3524         ptp->rx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
3525
3526         ptp->tx_tstamp_tc.cc_mask = BNXT_CYCLECOUNTER_MASK;
3527         ptp->tx_tstamp_tc.cc_shift = shift;
3528         ptp->tx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
3529
3530         if (!BNXT_CHIP_THOR(bp))
3531                 bnxt_map_ptp_regs(bp);
3532
3533         return 0;
3534 }
3535
3536 static int
3537 bnxt_timesync_disable(struct rte_eth_dev *dev)
3538 {
3539         struct bnxt *bp = dev->data->dev_private;
3540         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3541
3542         if (!ptp)
3543                 return 0;
3544
3545         ptp->rx_filter = 0;
3546         ptp->tx_tstamp_en = 0;
3547         ptp->rxctl = 0;
3548
3549         bnxt_hwrm_ptp_cfg(bp);
3550
3551         if (!BNXT_CHIP_THOR(bp))
3552                 bnxt_unmap_ptp_regs(bp);
3553
3554         return 0;
3555 }
3556
3557 static int
3558 bnxt_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
3559                                  struct timespec *timestamp,
3560                                  uint32_t flags __rte_unused)
3561 {
3562         struct bnxt *bp = dev->data->dev_private;
3563         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3564         uint64_t rx_tstamp_cycles = 0;
3565         uint64_t ns;
3566
3567         if (!ptp)
3568                 return 0;
3569
3570         if (BNXT_CHIP_THOR(bp))
3571                 rx_tstamp_cycles = ptp->rx_timestamp;
3572         else
3573                 bnxt_get_rx_ts(bp, &rx_tstamp_cycles);
3574
3575         ns = rte_timecounter_update(&ptp->rx_tstamp_tc, rx_tstamp_cycles);
3576         *timestamp = rte_ns_to_timespec(ns);
3577         return  0;
3578 }
3579
3580 static int
3581 bnxt_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
3582                                  struct timespec *timestamp)
3583 {
3584         struct bnxt *bp = dev->data->dev_private;
3585         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3586         uint64_t tx_tstamp_cycles = 0;
3587         uint64_t ns;
3588         int rc = 0;
3589
3590         if (!ptp)
3591                 return 0;
3592
3593         if (BNXT_CHIP_THOR(bp))
3594                 rc = bnxt_hwrm_port_ts_query(bp, BNXT_PTP_FLAGS_PATH_TX,
3595                                              &tx_tstamp_cycles);
3596         else
3597                 rc = bnxt_get_tx_ts(bp, &tx_tstamp_cycles);
3598
3599         ns = rte_timecounter_update(&ptp->tx_tstamp_tc, tx_tstamp_cycles);
3600         *timestamp = rte_ns_to_timespec(ns);
3601
3602         return rc;
3603 }
3604
3605 static int
3606 bnxt_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
3607 {
3608         struct bnxt *bp = dev->data->dev_private;
3609         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3610
3611         if (!ptp)
3612                 return 0;
3613
3614         ptp->tc.nsec += delta;
3615
3616         return 0;
3617 }
3618
3619 static int
3620 bnxt_get_eeprom_length_op(struct rte_eth_dev *dev)
3621 {
3622         struct bnxt *bp = dev->data->dev_private;
3623         int rc;
3624         uint32_t dir_entries;
3625         uint32_t entry_length;
3626
3627         rc = is_bnxt_in_error(bp);
3628         if (rc)
3629                 return rc;
3630
3631         PMD_DRV_LOG(INFO, PCI_PRI_FMT "\n",
3632                     bp->pdev->addr.domain, bp->pdev->addr.bus,
3633                     bp->pdev->addr.devid, bp->pdev->addr.function);
3634
3635         rc = bnxt_hwrm_nvm_get_dir_info(bp, &dir_entries, &entry_length);
3636         if (rc != 0)
3637                 return rc;
3638
3639         return dir_entries * entry_length;
3640 }
3641
3642 static int
3643 bnxt_get_eeprom_op(struct rte_eth_dev *dev,
3644                 struct rte_dev_eeprom_info *in_eeprom)
3645 {
3646         struct bnxt *bp = dev->data->dev_private;
3647         uint32_t index;
3648         uint32_t offset;
3649         int rc;
3650
3651         rc = is_bnxt_in_error(bp);
3652         if (rc)
3653                 return rc;
3654
3655         PMD_DRV_LOG(INFO, PCI_PRI_FMT " in_eeprom->offset = %d len = %d\n",
3656                     bp->pdev->addr.domain, bp->pdev->addr.bus,
3657                     bp->pdev->addr.devid, bp->pdev->addr.function,
3658                     in_eeprom->offset, in_eeprom->length);
3659
3660         if (in_eeprom->offset == 0) /* special offset value to get directory */
3661                 return bnxt_get_nvram_directory(bp, in_eeprom->length,
3662                                                 in_eeprom->data);
3663
3664         index = in_eeprom->offset >> 24;
3665         offset = in_eeprom->offset & 0xffffff;
3666
3667         if (index != 0)
3668                 return bnxt_hwrm_get_nvram_item(bp, index - 1, offset,
3669                                            in_eeprom->length, in_eeprom->data);
3670
3671         return 0;
3672 }
3673
3674 static bool bnxt_dir_type_is_ape_bin_format(uint16_t dir_type)
3675 {
3676         switch (dir_type) {
3677         case BNX_DIR_TYPE_CHIMP_PATCH:
3678         case BNX_DIR_TYPE_BOOTCODE:
3679         case BNX_DIR_TYPE_BOOTCODE_2:
3680         case BNX_DIR_TYPE_APE_FW:
3681         case BNX_DIR_TYPE_APE_PATCH:
3682         case BNX_DIR_TYPE_KONG_FW:
3683         case BNX_DIR_TYPE_KONG_PATCH:
3684         case BNX_DIR_TYPE_BONO_FW:
3685         case BNX_DIR_TYPE_BONO_PATCH:
3686                 /* FALLTHROUGH */
3687                 return true;
3688         }
3689
3690         return false;
3691 }
3692
3693 static bool bnxt_dir_type_is_other_exec_format(uint16_t dir_type)
3694 {
3695         switch (dir_type) {
3696         case BNX_DIR_TYPE_AVS:
3697         case BNX_DIR_TYPE_EXP_ROM_MBA:
3698         case BNX_DIR_TYPE_PCIE:
3699         case BNX_DIR_TYPE_TSCF_UCODE:
3700         case BNX_DIR_TYPE_EXT_PHY:
3701         case BNX_DIR_TYPE_CCM:
3702         case BNX_DIR_TYPE_ISCSI_BOOT:
3703         case BNX_DIR_TYPE_ISCSI_BOOT_IPV6:
3704         case BNX_DIR_TYPE_ISCSI_BOOT_IPV4N6:
3705                 /* FALLTHROUGH */
3706                 return true;
3707         }
3708
3709         return false;
3710 }
3711
3712 static bool bnxt_dir_type_is_executable(uint16_t dir_type)
3713 {
3714         return bnxt_dir_type_is_ape_bin_format(dir_type) ||
3715                 bnxt_dir_type_is_other_exec_format(dir_type);
3716 }
3717
3718 static int
3719 bnxt_set_eeprom_op(struct rte_eth_dev *dev,
3720                 struct rte_dev_eeprom_info *in_eeprom)
3721 {
3722         struct bnxt *bp = dev->data->dev_private;
3723         uint8_t index, dir_op;
3724         uint16_t type, ext, ordinal, attr;
3725         int rc;
3726
3727         rc = is_bnxt_in_error(bp);
3728         if (rc)
3729                 return rc;
3730
3731         PMD_DRV_LOG(INFO, PCI_PRI_FMT " in_eeprom->offset = %d len = %d\n",
3732                     bp->pdev->addr.domain, bp->pdev->addr.bus,
3733                     bp->pdev->addr.devid, bp->pdev->addr.function,
3734                     in_eeprom->offset, in_eeprom->length);
3735
3736         if (!BNXT_PF(bp)) {
3737                 PMD_DRV_LOG(ERR, "NVM write not supported from a VF\n");
3738                 return -EINVAL;
3739         }
3740
3741         type = in_eeprom->magic >> 16;
3742
3743         if (type == 0xffff) { /* special value for directory operations */
3744                 index = in_eeprom->magic & 0xff;
3745                 dir_op = in_eeprom->magic >> 8;
3746                 if (index == 0)
3747                         return -EINVAL;
3748                 switch (dir_op) {
3749                 case 0x0e: /* erase */
3750                         if (in_eeprom->offset != ~in_eeprom->magic)
3751                                 return -EINVAL;
3752                         return bnxt_hwrm_erase_nvram_directory(bp, index - 1);
3753                 default:
3754                         return -EINVAL;
3755                 }
3756         }
3757
3758         /* Create or re-write an NVM item: */
3759         if (bnxt_dir_type_is_executable(type) == true)
3760                 return -EOPNOTSUPP;
3761         ext = in_eeprom->magic & 0xffff;
3762         ordinal = in_eeprom->offset >> 16;
3763         attr = in_eeprom->offset & 0xffff;
3764
3765         return bnxt_hwrm_flash_nvram(bp, type, ordinal, ext, attr,
3766                                      in_eeprom->data, in_eeprom->length);
3767 }
3768
3769 /*
3770  * Initialization
3771  */
3772
3773 static const struct eth_dev_ops bnxt_dev_ops = {
3774         .dev_infos_get = bnxt_dev_info_get_op,
3775         .dev_close = bnxt_dev_close_op,
3776         .dev_configure = bnxt_dev_configure_op,
3777         .dev_start = bnxt_dev_start_op,
3778         .dev_stop = bnxt_dev_stop_op,
3779         .dev_set_link_up = bnxt_dev_set_link_up_op,
3780         .dev_set_link_down = bnxt_dev_set_link_down_op,
3781         .stats_get = bnxt_stats_get_op,
3782         .stats_reset = bnxt_stats_reset_op,
3783         .rx_queue_setup = bnxt_rx_queue_setup_op,
3784         .rx_queue_release = bnxt_rx_queue_release_op,
3785         .tx_queue_setup = bnxt_tx_queue_setup_op,
3786         .tx_queue_release = bnxt_tx_queue_release_op,
3787         .rx_queue_intr_enable = bnxt_rx_queue_intr_enable_op,
3788         .rx_queue_intr_disable = bnxt_rx_queue_intr_disable_op,
3789         .reta_update = bnxt_reta_update_op,
3790         .reta_query = bnxt_reta_query_op,
3791         .rss_hash_update = bnxt_rss_hash_update_op,
3792         .rss_hash_conf_get = bnxt_rss_hash_conf_get_op,
3793         .link_update = bnxt_link_update_op,
3794         .promiscuous_enable = bnxt_promiscuous_enable_op,
3795         .promiscuous_disable = bnxt_promiscuous_disable_op,
3796         .allmulticast_enable = bnxt_allmulticast_enable_op,
3797         .allmulticast_disable = bnxt_allmulticast_disable_op,
3798         .mac_addr_add = bnxt_mac_addr_add_op,
3799         .mac_addr_remove = bnxt_mac_addr_remove_op,
3800         .flow_ctrl_get = bnxt_flow_ctrl_get_op,
3801         .flow_ctrl_set = bnxt_flow_ctrl_set_op,
3802         .udp_tunnel_port_add  = bnxt_udp_tunnel_port_add_op,
3803         .udp_tunnel_port_del  = bnxt_udp_tunnel_port_del_op,
3804         .vlan_filter_set = bnxt_vlan_filter_set_op,
3805         .vlan_offload_set = bnxt_vlan_offload_set_op,
3806         .vlan_tpid_set = bnxt_vlan_tpid_set_op,
3807         .vlan_pvid_set = bnxt_vlan_pvid_set_op,
3808         .mtu_set = bnxt_mtu_set_op,
3809         .mac_addr_set = bnxt_set_default_mac_addr_op,
3810         .xstats_get = bnxt_dev_xstats_get_op,
3811         .xstats_get_names = bnxt_dev_xstats_get_names_op,
3812         .xstats_reset = bnxt_dev_xstats_reset_op,
3813         .fw_version_get = bnxt_fw_version_get,
3814         .set_mc_addr_list = bnxt_dev_set_mc_addr_list_op,
3815         .rxq_info_get = bnxt_rxq_info_get_op,
3816         .txq_info_get = bnxt_txq_info_get_op,
3817         .dev_led_on = bnxt_dev_led_on_op,
3818         .dev_led_off = bnxt_dev_led_off_op,
3819         .xstats_get_by_id = bnxt_dev_xstats_get_by_id_op,
3820         .xstats_get_names_by_id = bnxt_dev_xstats_get_names_by_id_op,
3821         .rx_queue_count = bnxt_rx_queue_count_op,
3822         .rx_descriptor_status = bnxt_rx_descriptor_status_op,
3823         .tx_descriptor_status = bnxt_tx_descriptor_status_op,
3824         .rx_queue_start = bnxt_rx_queue_start,
3825         .rx_queue_stop = bnxt_rx_queue_stop,
3826         .tx_queue_start = bnxt_tx_queue_start,
3827         .tx_queue_stop = bnxt_tx_queue_stop,
3828         .filter_ctrl = bnxt_filter_ctrl_op,
3829         .dev_supported_ptypes_get = bnxt_dev_supported_ptypes_get_op,
3830         .get_eeprom_length    = bnxt_get_eeprom_length_op,
3831         .get_eeprom           = bnxt_get_eeprom_op,
3832         .set_eeprom           = bnxt_set_eeprom_op,
3833         .timesync_enable      = bnxt_timesync_enable,
3834         .timesync_disable     = bnxt_timesync_disable,
3835         .timesync_read_time   = bnxt_timesync_read_time,
3836         .timesync_write_time   = bnxt_timesync_write_time,
3837         .timesync_adjust_time = bnxt_timesync_adjust_time,
3838         .timesync_read_rx_timestamp = bnxt_timesync_read_rx_timestamp,
3839         .timesync_read_tx_timestamp = bnxt_timesync_read_tx_timestamp,
3840 };
3841
3842 static uint32_t bnxt_map_reset_regs(struct bnxt *bp, uint32_t reg)
3843 {
3844         uint32_t offset;
3845
3846         /* Only pre-map the reset GRC registers using window 3 */
3847         rte_write32(reg & 0xfffff000, (uint8_t *)bp->bar0 +
3848                     BNXT_GRCPF_REG_WINDOW_BASE_OUT + 8);
3849
3850         offset = BNXT_GRCP_WINDOW_3_BASE + (reg & 0xffc);
3851
3852         return offset;
3853 }
3854
3855 int bnxt_map_fw_health_status_regs(struct bnxt *bp)
3856 {
3857         struct bnxt_error_recovery_info *info = bp->recovery_info;
3858         uint32_t reg_base = 0xffffffff;
3859         int i;
3860
3861         /* Only pre-map the monitoring GRC registers using window 2 */
3862         for (i = 0; i < BNXT_FW_STATUS_REG_CNT; i++) {
3863                 uint32_t reg = info->status_regs[i];
3864
3865                 if (BNXT_FW_STATUS_REG_TYPE(reg) != BNXT_FW_STATUS_REG_TYPE_GRC)
3866                         continue;
3867
3868                 if (reg_base == 0xffffffff)
3869                         reg_base = reg & 0xfffff000;
3870                 if ((reg & 0xfffff000) != reg_base)
3871                         return -ERANGE;
3872
3873                 /* Use mask 0xffc as the Lower 2 bits indicates
3874                  * address space location
3875                  */
3876                 info->mapped_status_regs[i] = BNXT_GRCP_WINDOW_2_BASE +
3877                                                 (reg & 0xffc);
3878         }
3879
3880         if (reg_base == 0xffffffff)
3881                 return 0;
3882
3883         rte_write32(reg_base, (uint8_t *)bp->bar0 +
3884                     BNXT_GRCPF_REG_WINDOW_BASE_OUT + 4);
3885
3886         return 0;
3887 }
3888
3889 static void bnxt_write_fw_reset_reg(struct bnxt *bp, uint32_t index)
3890 {
3891         struct bnxt_error_recovery_info *info = bp->recovery_info;
3892         uint32_t delay = info->delay_after_reset[index];
3893         uint32_t val = info->reset_reg_val[index];
3894         uint32_t reg = info->reset_reg[index];
3895         uint32_t type, offset;
3896
3897         type = BNXT_FW_STATUS_REG_TYPE(reg);
3898         offset = BNXT_FW_STATUS_REG_OFF(reg);
3899
3900         switch (type) {
3901         case BNXT_FW_STATUS_REG_TYPE_CFG:
3902                 rte_pci_write_config(bp->pdev, &val, sizeof(val), offset);
3903                 break;
3904         case BNXT_FW_STATUS_REG_TYPE_GRC:
3905                 offset = bnxt_map_reset_regs(bp, offset);
3906                 rte_write32(val, (uint8_t *)bp->bar0 + offset);
3907                 break;
3908         case BNXT_FW_STATUS_REG_TYPE_BAR0:
3909                 rte_write32(val, (uint8_t *)bp->bar0 + offset);
3910                 break;
3911         }
3912         /* wait on a specific interval of time until core reset is complete */
3913         if (delay)
3914                 rte_delay_ms(delay);
3915 }
3916
3917 static void bnxt_dev_cleanup(struct bnxt *bp)
3918 {
3919         bnxt_set_hwrm_link_config(bp, false);
3920         bp->link_info.link_up = 0;
3921         if (bp->eth_dev->data->dev_started)
3922                 bnxt_dev_stop_op(bp->eth_dev);
3923
3924         bnxt_uninit_resources(bp, true);
3925 }
3926
3927 static int bnxt_restore_vlan_filters(struct bnxt *bp)
3928 {
3929         struct rte_eth_dev *dev = bp->eth_dev;
3930         struct rte_vlan_filter_conf *vfc;
3931         int vidx, vbit, rc;
3932         uint16_t vlan_id;
3933
3934         for (vlan_id = 1; vlan_id <= RTE_ETHER_MAX_VLAN_ID; vlan_id++) {
3935                 vfc = &dev->data->vlan_filter_conf;
3936                 vidx = vlan_id / 64;
3937                 vbit = vlan_id % 64;
3938
3939                 /* Each bit corresponds to a VLAN id */
3940                 if (vfc->ids[vidx] & (UINT64_C(1) << vbit)) {
3941                         rc = bnxt_add_vlan_filter(bp, vlan_id);
3942                         if (rc)
3943                                 return rc;
3944                 }
3945         }
3946
3947         return 0;
3948 }
3949
3950 static int bnxt_restore_mac_filters(struct bnxt *bp)
3951 {
3952         struct rte_eth_dev *dev = bp->eth_dev;
3953         struct rte_eth_dev_info dev_info;
3954         struct rte_ether_addr *addr;
3955         uint64_t pool_mask;
3956         uint32_t pool = 0;
3957         uint16_t i;
3958         int rc;
3959
3960         if (BNXT_VF(bp) & !BNXT_VF_IS_TRUSTED(bp))
3961                 return 0;
3962
3963         rc = bnxt_dev_info_get_op(dev, &dev_info);
3964         if (rc)
3965                 return rc;
3966
3967         /* replay MAC address configuration */
3968         for (i = 1; i < dev_info.max_mac_addrs; i++) {
3969                 addr = &dev->data->mac_addrs[i];
3970
3971                 /* skip zero address */
3972                 if (rte_is_zero_ether_addr(addr))
3973                         continue;
3974
3975                 pool = 0;
3976                 pool_mask = dev->data->mac_pool_sel[i];
3977
3978                 do {
3979                         if (pool_mask & 1ULL) {
3980                                 rc = bnxt_mac_addr_add_op(dev, addr, i, pool);
3981                                 if (rc)
3982                                         return rc;
3983                         }
3984                         pool_mask >>= 1;
3985                         pool++;
3986                 } while (pool_mask);
3987         }
3988
3989         return 0;
3990 }
3991
3992 static int bnxt_restore_filters(struct bnxt *bp)
3993 {
3994         struct rte_eth_dev *dev = bp->eth_dev;
3995         int ret = 0;
3996
3997         if (dev->data->all_multicast) {
3998                 ret = bnxt_allmulticast_enable_op(dev);
3999                 if (ret)
4000                         return ret;
4001         }
4002         if (dev->data->promiscuous) {
4003                 ret = bnxt_promiscuous_enable_op(dev);
4004                 if (ret)
4005                         return ret;
4006         }
4007
4008         ret = bnxt_restore_mac_filters(bp);
4009         if (ret)
4010                 return ret;
4011
4012         ret = bnxt_restore_vlan_filters(bp);
4013         /* TODO restore other filters as well */
4014         return ret;
4015 }
4016
4017 static void bnxt_dev_recover(void *arg)
4018 {
4019         struct bnxt *bp = arg;
4020         int timeout = bp->fw_reset_max_msecs;
4021         int rc = 0;
4022
4023         /* Clear Error flag so that device re-init should happen */
4024         bp->flags &= ~BNXT_FLAG_FATAL_ERROR;
4025
4026         do {
4027                 rc = bnxt_hwrm_ver_get(bp, SHORT_HWRM_CMD_TIMEOUT);
4028                 if (rc == 0)
4029                         break;
4030                 rte_delay_ms(BNXT_FW_READY_WAIT_INTERVAL);
4031                 timeout -= BNXT_FW_READY_WAIT_INTERVAL;
4032         } while (rc && timeout);
4033
4034         if (rc) {
4035                 PMD_DRV_LOG(ERR, "FW is not Ready after reset\n");
4036                 goto err;
4037         }
4038
4039         rc = bnxt_init_resources(bp, true);
4040         if (rc) {
4041                 PMD_DRV_LOG(ERR,
4042                             "Failed to initialize resources after reset\n");
4043                 goto err;
4044         }
4045         /* clear reset flag as the device is initialized now */
4046         bp->flags &= ~BNXT_FLAG_FW_RESET;
4047
4048         rc = bnxt_dev_start_op(bp->eth_dev);
4049         if (rc) {
4050                 PMD_DRV_LOG(ERR, "Failed to start port after reset\n");
4051                 goto err_start;
4052         }
4053
4054         rc = bnxt_restore_filters(bp);
4055         if (rc)
4056                 goto err_start;
4057
4058         PMD_DRV_LOG(INFO, "Recovered from FW reset\n");
4059         return;
4060 err_start:
4061         bnxt_dev_stop_op(bp->eth_dev);
4062 err:
4063         bp->flags |= BNXT_FLAG_FATAL_ERROR;
4064         bnxt_uninit_resources(bp, false);
4065         PMD_DRV_LOG(ERR, "Failed to recover from FW reset\n");
4066 }
4067
4068 void bnxt_dev_reset_and_resume(void *arg)
4069 {
4070         struct bnxt *bp = arg;
4071         int rc;
4072
4073         bnxt_dev_cleanup(bp);
4074
4075         bnxt_wait_for_device_shutdown(bp);
4076
4077         rc = rte_eal_alarm_set(US_PER_MS * bp->fw_reset_min_msecs,
4078                                bnxt_dev_recover, (void *)bp);
4079         if (rc)
4080                 PMD_DRV_LOG(ERR, "Error setting recovery alarm");
4081 }
4082
4083 uint32_t bnxt_read_fw_status_reg(struct bnxt *bp, uint32_t index)
4084 {
4085         struct bnxt_error_recovery_info *info = bp->recovery_info;
4086         uint32_t reg = info->status_regs[index];
4087         uint32_t type, offset, val = 0;
4088
4089         type = BNXT_FW_STATUS_REG_TYPE(reg);
4090         offset = BNXT_FW_STATUS_REG_OFF(reg);
4091
4092         switch (type) {
4093         case BNXT_FW_STATUS_REG_TYPE_CFG:
4094                 rte_pci_read_config(bp->pdev, &val, sizeof(val), offset);
4095                 break;
4096         case BNXT_FW_STATUS_REG_TYPE_GRC:
4097                 offset = info->mapped_status_regs[index];
4098                 /* FALLTHROUGH */
4099         case BNXT_FW_STATUS_REG_TYPE_BAR0:
4100                 val = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
4101                                        offset));
4102                 break;
4103         }
4104
4105         return val;
4106 }
4107
4108 static int bnxt_fw_reset_all(struct bnxt *bp)
4109 {
4110         struct bnxt_error_recovery_info *info = bp->recovery_info;
4111         uint32_t i;
4112         int rc = 0;
4113
4114         if (info->flags & BNXT_FLAG_ERROR_RECOVERY_HOST) {
4115                 /* Reset through master function driver */
4116                 for (i = 0; i < info->reg_array_cnt; i++)
4117                         bnxt_write_fw_reset_reg(bp, i);
4118                 /* Wait for time specified by FW after triggering reset */
4119                 rte_delay_ms(info->master_func_wait_period_after_reset);
4120         } else if (info->flags & BNXT_FLAG_ERROR_RECOVERY_CO_CPU) {
4121                 /* Reset with the help of Kong processor */
4122                 rc = bnxt_hwrm_fw_reset(bp);
4123                 if (rc)
4124                         PMD_DRV_LOG(ERR, "Failed to reset FW\n");
4125         }
4126
4127         return rc;
4128 }
4129
4130 static void bnxt_fw_reset_cb(void *arg)
4131 {
4132         struct bnxt *bp = arg;
4133         struct bnxt_error_recovery_info *info = bp->recovery_info;
4134         int rc = 0;
4135
4136         /* Only Master function can do FW reset */
4137         if (bnxt_is_master_func(bp) &&
4138             bnxt_is_recovery_enabled(bp)) {
4139                 rc = bnxt_fw_reset_all(bp);
4140                 if (rc) {
4141                         PMD_DRV_LOG(ERR, "Adapter recovery failed\n");
4142                         return;
4143                 }
4144         }
4145
4146         /* if recovery method is ERROR_RECOVERY_CO_CPU, KONG will send
4147          * EXCEPTION_FATAL_ASYNC event to all the functions
4148          * (including MASTER FUNC). After receiving this Async, all the active
4149          * drivers should treat this case as FW initiated recovery
4150          */
4151         if (info->flags & BNXT_FLAG_ERROR_RECOVERY_HOST) {
4152                 bp->fw_reset_min_msecs = BNXT_MIN_FW_READY_TIMEOUT;
4153                 bp->fw_reset_max_msecs = BNXT_MAX_FW_RESET_TIMEOUT;
4154
4155                 /* To recover from error */
4156                 rte_eal_alarm_set(US_PER_MS, bnxt_dev_reset_and_resume,
4157                                   (void *)bp);
4158         }
4159 }
4160
4161 /* Driver should poll FW heartbeat, reset_counter with the frequency
4162  * advertised by FW in HWRM_ERROR_RECOVERY_QCFG.
4163  * When the driver detects heartbeat stop or change in reset_counter,
4164  * it has to trigger a reset to recover from the error condition.
4165  * A “master PF” is the function who will have the privilege to
4166  * initiate the chimp reset. The master PF will be elected by the
4167  * firmware and will be notified through async message.
4168  */
4169 static void bnxt_check_fw_health(void *arg)
4170 {
4171         struct bnxt *bp = arg;
4172         struct bnxt_error_recovery_info *info = bp->recovery_info;
4173         uint32_t val = 0, wait_msec;
4174
4175         if (!info || !bnxt_is_recovery_enabled(bp) ||
4176             is_bnxt_in_error(bp))
4177                 return;
4178
4179         val = bnxt_read_fw_status_reg(bp, BNXT_FW_HEARTBEAT_CNT_REG);
4180         if (val == info->last_heart_beat)
4181                 goto reset;
4182
4183         info->last_heart_beat = val;
4184
4185         val = bnxt_read_fw_status_reg(bp, BNXT_FW_RECOVERY_CNT_REG);
4186         if (val != info->last_reset_counter)
4187                 goto reset;
4188
4189         info->last_reset_counter = val;
4190
4191         rte_eal_alarm_set(US_PER_MS * info->driver_polling_freq,
4192                           bnxt_check_fw_health, (void *)bp);
4193
4194         return;
4195 reset:
4196         /* Stop DMA to/from device */
4197         bp->flags |= BNXT_FLAG_FATAL_ERROR;
4198         bp->flags |= BNXT_FLAG_FW_RESET;
4199
4200         PMD_DRV_LOG(ERR, "Detected FW dead condition\n");
4201
4202         if (bnxt_is_master_func(bp))
4203                 wait_msec = info->master_func_wait_period;
4204         else
4205                 wait_msec = info->normal_func_wait_period;
4206
4207         rte_eal_alarm_set(US_PER_MS * wait_msec,
4208                           bnxt_fw_reset_cb, (void *)bp);
4209 }
4210
4211 void bnxt_schedule_fw_health_check(struct bnxt *bp)
4212 {
4213         uint32_t polling_freq;
4214
4215         if (!bnxt_is_recovery_enabled(bp))
4216                 return;
4217
4218         if (bp->flags & BNXT_FLAG_FW_HEALTH_CHECK_SCHEDULED)
4219                 return;
4220
4221         polling_freq = bp->recovery_info->driver_polling_freq;
4222
4223         rte_eal_alarm_set(US_PER_MS * polling_freq,
4224                           bnxt_check_fw_health, (void *)bp);
4225         bp->flags |= BNXT_FLAG_FW_HEALTH_CHECK_SCHEDULED;
4226 }
4227
4228 static void bnxt_cancel_fw_health_check(struct bnxt *bp)
4229 {
4230         if (!bnxt_is_recovery_enabled(bp))
4231                 return;
4232
4233         rte_eal_alarm_cancel(bnxt_check_fw_health, (void *)bp);
4234         bp->flags &= ~BNXT_FLAG_FW_HEALTH_CHECK_SCHEDULED;
4235 }
4236
4237 static bool bnxt_vf_pciid(uint16_t device_id)
4238 {
4239         switch (device_id) {
4240         case BROADCOM_DEV_ID_57304_VF:
4241         case BROADCOM_DEV_ID_57406_VF:
4242         case BROADCOM_DEV_ID_5731X_VF:
4243         case BROADCOM_DEV_ID_5741X_VF:
4244         case BROADCOM_DEV_ID_57414_VF:
4245         case BROADCOM_DEV_ID_STRATUS_NIC_VF1:
4246         case BROADCOM_DEV_ID_STRATUS_NIC_VF2:
4247         case BROADCOM_DEV_ID_58802_VF:
4248         case BROADCOM_DEV_ID_57500_VF1:
4249         case BROADCOM_DEV_ID_57500_VF2:
4250                 /* FALLTHROUGH */
4251                 return true;
4252         default:
4253                 return false;
4254         }
4255 }
4256
4257 static bool bnxt_thor_device(uint16_t device_id)
4258 {
4259         switch (device_id) {
4260         case BROADCOM_DEV_ID_57508:
4261         case BROADCOM_DEV_ID_57504:
4262         case BROADCOM_DEV_ID_57502:
4263         case BROADCOM_DEV_ID_57508_MF1:
4264         case BROADCOM_DEV_ID_57504_MF1:
4265         case BROADCOM_DEV_ID_57502_MF1:
4266         case BROADCOM_DEV_ID_57508_MF2:
4267         case BROADCOM_DEV_ID_57504_MF2:
4268         case BROADCOM_DEV_ID_57502_MF2:
4269         case BROADCOM_DEV_ID_57500_VF1:
4270         case BROADCOM_DEV_ID_57500_VF2:
4271                 /* FALLTHROUGH */
4272                 return true;
4273         default:
4274                 return false;
4275         }
4276 }
4277
4278 bool bnxt_stratus_device(struct bnxt *bp)
4279 {
4280         uint16_t device_id = bp->pdev->id.device_id;
4281
4282         switch (device_id) {
4283         case BROADCOM_DEV_ID_STRATUS_NIC:
4284         case BROADCOM_DEV_ID_STRATUS_NIC_VF1:
4285         case BROADCOM_DEV_ID_STRATUS_NIC_VF2:
4286                 /* FALLTHROUGH */
4287                 return true;
4288         default:
4289                 return false;
4290         }
4291 }
4292
4293 static int bnxt_init_board(struct rte_eth_dev *eth_dev)
4294 {
4295         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
4296         struct bnxt *bp = eth_dev->data->dev_private;
4297
4298         /* enable device (incl. PCI PM wakeup), and bus-mastering */
4299         bp->bar0 = (void *)pci_dev->mem_resource[0].addr;
4300         bp->doorbell_base = (void *)pci_dev->mem_resource[2].addr;
4301         if (!bp->bar0 || !bp->doorbell_base) {
4302                 PMD_DRV_LOG(ERR, "Unable to access Hardware\n");
4303                 return -ENODEV;
4304         }
4305
4306         bp->eth_dev = eth_dev;
4307         bp->pdev = pci_dev;
4308
4309         return 0;
4310 }
4311
4312 static int bnxt_alloc_ctx_mem_blk(struct bnxt *bp,
4313                                   struct bnxt_ctx_pg_info *ctx_pg,
4314                                   uint32_t mem_size,
4315                                   const char *suffix,
4316                                   uint16_t idx)
4317 {
4318         struct bnxt_ring_mem_info *rmem = &ctx_pg->ring_mem;
4319         const struct rte_memzone *mz = NULL;
4320         char mz_name[RTE_MEMZONE_NAMESIZE];
4321         rte_iova_t mz_phys_addr;
4322         uint64_t valid_bits = 0;
4323         uint32_t sz;
4324         int i;
4325
4326         if (!mem_size)
4327                 return 0;
4328
4329         rmem->nr_pages = RTE_ALIGN_MUL_CEIL(mem_size, BNXT_PAGE_SIZE) /
4330                          BNXT_PAGE_SIZE;
4331         rmem->page_size = BNXT_PAGE_SIZE;
4332         rmem->pg_arr = ctx_pg->ctx_pg_arr;
4333         rmem->dma_arr = ctx_pg->ctx_dma_arr;
4334         rmem->flags = BNXT_RMEM_VALID_PTE_FLAG;
4335
4336         valid_bits = PTU_PTE_VALID;
4337
4338         if (rmem->nr_pages > 1) {
4339                 snprintf(mz_name, RTE_MEMZONE_NAMESIZE,
4340                          "bnxt_ctx_pg_tbl%s_%x_%d",
4341                          suffix, idx, bp->eth_dev->data->port_id);
4342                 mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0;
4343                 mz = rte_memzone_lookup(mz_name);
4344                 if (!mz) {
4345                         mz = rte_memzone_reserve_aligned(mz_name,
4346                                                 rmem->nr_pages * 8,
4347                                                 SOCKET_ID_ANY,
4348                                                 RTE_MEMZONE_2MB |
4349                                                 RTE_MEMZONE_SIZE_HINT_ONLY |
4350                                                 RTE_MEMZONE_IOVA_CONTIG,
4351                                                 BNXT_PAGE_SIZE);
4352                         if (mz == NULL)
4353                                 return -ENOMEM;
4354                 }
4355
4356                 memset(mz->addr, 0, mz->len);
4357                 mz_phys_addr = mz->iova;
4358
4359                 rmem->pg_tbl = mz->addr;
4360                 rmem->pg_tbl_map = mz_phys_addr;
4361                 rmem->pg_tbl_mz = mz;
4362         }
4363
4364         snprintf(mz_name, RTE_MEMZONE_NAMESIZE, "bnxt_ctx_%s_%x_%d",
4365                  suffix, idx, bp->eth_dev->data->port_id);
4366         mz = rte_memzone_lookup(mz_name);
4367         if (!mz) {
4368                 mz = rte_memzone_reserve_aligned(mz_name,
4369                                                  mem_size,
4370                                                  SOCKET_ID_ANY,
4371                                                  RTE_MEMZONE_1GB |
4372                                                  RTE_MEMZONE_SIZE_HINT_ONLY |
4373                                                  RTE_MEMZONE_IOVA_CONTIG,
4374                                                  BNXT_PAGE_SIZE);
4375                 if (mz == NULL)
4376                         return -ENOMEM;
4377         }
4378
4379         memset(mz->addr, 0, mz->len);
4380         mz_phys_addr = mz->iova;
4381
4382         for (sz = 0, i = 0; sz < mem_size; sz += BNXT_PAGE_SIZE, i++) {
4383                 rmem->pg_arr[i] = ((char *)mz->addr) + sz;
4384                 rmem->dma_arr[i] = mz_phys_addr + sz;
4385
4386                 if (rmem->nr_pages > 1) {
4387                         if (i == rmem->nr_pages - 2 &&
4388                             (rmem->flags & BNXT_RMEM_RING_PTE_FLAG))
4389                                 valid_bits |= PTU_PTE_NEXT_TO_LAST;
4390                         else if (i == rmem->nr_pages - 1 &&
4391                                  (rmem->flags & BNXT_RMEM_RING_PTE_FLAG))
4392                                 valid_bits |= PTU_PTE_LAST;
4393
4394                         rmem->pg_tbl[i] = rte_cpu_to_le_64(rmem->dma_arr[i] |
4395                                                            valid_bits);
4396                 }
4397         }
4398
4399         rmem->mz = mz;
4400         if (rmem->vmem_size)
4401                 rmem->vmem = (void **)mz->addr;
4402         rmem->dma_arr[0] = mz_phys_addr;
4403         return 0;
4404 }
4405
4406 static void bnxt_free_ctx_mem(struct bnxt *bp)
4407 {
4408         int i;
4409
4410         if (!bp->ctx || !(bp->ctx->flags & BNXT_CTX_FLAG_INITED))
4411                 return;
4412
4413         bp->ctx->flags &= ~BNXT_CTX_FLAG_INITED;
4414         rte_memzone_free(bp->ctx->qp_mem.ring_mem.mz);
4415         rte_memzone_free(bp->ctx->srq_mem.ring_mem.mz);
4416         rte_memzone_free(bp->ctx->cq_mem.ring_mem.mz);
4417         rte_memzone_free(bp->ctx->vnic_mem.ring_mem.mz);
4418         rte_memzone_free(bp->ctx->stat_mem.ring_mem.mz);
4419         rte_memzone_free(bp->ctx->qp_mem.ring_mem.pg_tbl_mz);
4420         rte_memzone_free(bp->ctx->srq_mem.ring_mem.pg_tbl_mz);
4421         rte_memzone_free(bp->ctx->cq_mem.ring_mem.pg_tbl_mz);
4422         rte_memzone_free(bp->ctx->vnic_mem.ring_mem.pg_tbl_mz);
4423         rte_memzone_free(bp->ctx->stat_mem.ring_mem.pg_tbl_mz);
4424
4425         for (i = 0; i < BNXT_MAX_Q; i++) {
4426                 if (bp->ctx->tqm_mem[i])
4427                         rte_memzone_free(bp->ctx->tqm_mem[i]->ring_mem.mz);
4428         }
4429
4430         rte_free(bp->ctx);
4431         bp->ctx = NULL;
4432 }
4433
4434 #define bnxt_roundup(x, y)   ((((x) + ((y) - 1)) / (y)) * (y))
4435
4436 #define min_t(type, x, y) ({                    \
4437         type __min1 = (x);                      \
4438         type __min2 = (y);                      \
4439         __min1 < __min2 ? __min1 : __min2; })
4440
4441 #define max_t(type, x, y) ({                    \
4442         type __max1 = (x);                      \
4443         type __max2 = (y);                      \
4444         __max1 > __max2 ? __max1 : __max2; })
4445
4446 #define clamp_t(type, _x, min, max)     min_t(type, max_t(type, _x, min), max)
4447
4448 int bnxt_alloc_ctx_mem(struct bnxt *bp)
4449 {
4450         struct bnxt_ctx_pg_info *ctx_pg;
4451         struct bnxt_ctx_mem_info *ctx;
4452         uint32_t mem_size, ena, entries;
4453         int i, rc;
4454
4455         rc = bnxt_hwrm_func_backing_store_qcaps(bp);
4456         if (rc) {
4457                 PMD_DRV_LOG(ERR, "Query context mem capability failed\n");
4458                 return rc;
4459         }
4460         ctx = bp->ctx;
4461         if (!ctx || (ctx->flags & BNXT_CTX_FLAG_INITED))
4462                 return 0;
4463
4464         ctx_pg = &ctx->qp_mem;
4465         ctx_pg->entries = ctx->qp_min_qp1_entries + ctx->qp_max_l2_entries;
4466         mem_size = ctx->qp_entry_size * ctx_pg->entries;
4467         rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "qp_mem", 0);
4468         if (rc)
4469                 return rc;
4470
4471         ctx_pg = &ctx->srq_mem;
4472         ctx_pg->entries = ctx->srq_max_l2_entries;
4473         mem_size = ctx->srq_entry_size * ctx_pg->entries;
4474         rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "srq_mem", 0);
4475         if (rc)
4476                 return rc;
4477
4478         ctx_pg = &ctx->cq_mem;
4479         ctx_pg->entries = ctx->cq_max_l2_entries;
4480         mem_size = ctx->cq_entry_size * ctx_pg->entries;
4481         rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "cq_mem", 0);
4482         if (rc)
4483                 return rc;
4484
4485         ctx_pg = &ctx->vnic_mem;
4486         ctx_pg->entries = ctx->vnic_max_vnic_entries +
4487                 ctx->vnic_max_ring_table_entries;
4488         mem_size = ctx->vnic_entry_size * ctx_pg->entries;
4489         rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "vnic_mem", 0);
4490         if (rc)
4491                 return rc;
4492
4493         ctx_pg = &ctx->stat_mem;
4494         ctx_pg->entries = ctx->stat_max_entries;
4495         mem_size = ctx->stat_entry_size * ctx_pg->entries;
4496         rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "stat_mem", 0);
4497         if (rc)
4498                 return rc;
4499
4500         entries = ctx->qp_max_l2_entries +
4501                   ctx->vnic_max_vnic_entries +
4502                   ctx->tqm_min_entries_per_ring;
4503         entries = bnxt_roundup(entries, ctx->tqm_entries_multiple);
4504         entries = clamp_t(uint32_t, entries, ctx->tqm_min_entries_per_ring,
4505                           ctx->tqm_max_entries_per_ring);
4506         for (i = 0, ena = 0; i < BNXT_MAX_Q; i++) {
4507                 ctx_pg = ctx->tqm_mem[i];
4508                 /* use min tqm entries for now. */
4509                 ctx_pg->entries = entries;
4510                 mem_size = ctx->tqm_entry_size * ctx_pg->entries;
4511                 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "tqm_mem", i);
4512                 if (rc)
4513                         return rc;
4514                 ena |= HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_SP << i;
4515         }
4516
4517         ena |= FUNC_BACKING_STORE_CFG_INPUT_DFLT_ENABLES;
4518         rc = bnxt_hwrm_func_backing_store_cfg(bp, ena);
4519         if (rc)
4520                 PMD_DRV_LOG(ERR,
4521                             "Failed to configure context mem: rc = %d\n", rc);
4522         else
4523                 ctx->flags |= BNXT_CTX_FLAG_INITED;
4524
4525         return rc;
4526 }
4527
4528 static int bnxt_alloc_stats_mem(struct bnxt *bp)
4529 {
4530         struct rte_pci_device *pci_dev = bp->pdev;
4531         char mz_name[RTE_MEMZONE_NAMESIZE];
4532         const struct rte_memzone *mz = NULL;
4533         uint32_t total_alloc_len;
4534         rte_iova_t mz_phys_addr;
4535
4536         if (pci_dev->id.device_id == BROADCOM_DEV_ID_NS2)
4537                 return 0;
4538
4539         snprintf(mz_name, RTE_MEMZONE_NAMESIZE,
4540                  "bnxt_" PCI_PRI_FMT "-%s", pci_dev->addr.domain,
4541                  pci_dev->addr.bus, pci_dev->addr.devid,
4542                  pci_dev->addr.function, "rx_port_stats");
4543         mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0;
4544         mz = rte_memzone_lookup(mz_name);
4545         total_alloc_len =
4546                 RTE_CACHE_LINE_ROUNDUP(sizeof(struct rx_port_stats) +
4547                                        sizeof(struct rx_port_stats_ext) + 512);
4548         if (!mz) {
4549                 mz = rte_memzone_reserve(mz_name, total_alloc_len,
4550                                          SOCKET_ID_ANY,
4551                                          RTE_MEMZONE_2MB |
4552                                          RTE_MEMZONE_SIZE_HINT_ONLY |
4553                                          RTE_MEMZONE_IOVA_CONTIG);
4554                 if (mz == NULL)
4555                         return -ENOMEM;
4556         }
4557         memset(mz->addr, 0, mz->len);
4558         mz_phys_addr = mz->iova;
4559
4560         bp->rx_mem_zone = (const void *)mz;
4561         bp->hw_rx_port_stats = mz->addr;
4562         bp->hw_rx_port_stats_map = mz_phys_addr;
4563
4564         snprintf(mz_name, RTE_MEMZONE_NAMESIZE,
4565                  "bnxt_" PCI_PRI_FMT "-%s", pci_dev->addr.domain,
4566                  pci_dev->addr.bus, pci_dev->addr.devid,
4567                  pci_dev->addr.function, "tx_port_stats");
4568         mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0;
4569         mz = rte_memzone_lookup(mz_name);
4570         total_alloc_len =
4571                 RTE_CACHE_LINE_ROUNDUP(sizeof(struct tx_port_stats) +
4572                                        sizeof(struct tx_port_stats_ext) + 512);
4573         if (!mz) {
4574                 mz = rte_memzone_reserve(mz_name,
4575                                          total_alloc_len,
4576                                          SOCKET_ID_ANY,
4577                                          RTE_MEMZONE_2MB |
4578                                          RTE_MEMZONE_SIZE_HINT_ONLY |
4579                                          RTE_MEMZONE_IOVA_CONTIG);
4580                 if (mz == NULL)
4581                         return -ENOMEM;
4582         }
4583         memset(mz->addr, 0, mz->len);
4584         mz_phys_addr = mz->iova;
4585
4586         bp->tx_mem_zone = (const void *)mz;
4587         bp->hw_tx_port_stats = mz->addr;
4588         bp->hw_tx_port_stats_map = mz_phys_addr;
4589         bp->flags |= BNXT_FLAG_PORT_STATS;
4590
4591         /* Display extended statistics if FW supports it */
4592         if (bp->hwrm_spec_code < HWRM_SPEC_CODE_1_8_4 ||
4593             bp->hwrm_spec_code == HWRM_SPEC_CODE_1_9_0 ||
4594             !(bp->flags & BNXT_FLAG_EXT_STATS_SUPPORTED))
4595                 return 0;
4596
4597         bp->hw_rx_port_stats_ext = (void *)
4598                 ((uint8_t *)bp->hw_rx_port_stats +
4599                  sizeof(struct rx_port_stats));
4600         bp->hw_rx_port_stats_ext_map = bp->hw_rx_port_stats_map +
4601                 sizeof(struct rx_port_stats);
4602         bp->flags |= BNXT_FLAG_EXT_RX_PORT_STATS;
4603
4604         if (bp->hwrm_spec_code < HWRM_SPEC_CODE_1_9_2 ||
4605             bp->flags & BNXT_FLAG_EXT_STATS_SUPPORTED) {
4606                 bp->hw_tx_port_stats_ext = (void *)
4607                         ((uint8_t *)bp->hw_tx_port_stats +
4608                          sizeof(struct tx_port_stats));
4609                 bp->hw_tx_port_stats_ext_map =
4610                         bp->hw_tx_port_stats_map +
4611                         sizeof(struct tx_port_stats);
4612                 bp->flags |= BNXT_FLAG_EXT_TX_PORT_STATS;
4613         }
4614
4615         return 0;
4616 }
4617
4618 static int bnxt_setup_mac_addr(struct rte_eth_dev *eth_dev)
4619 {
4620         struct bnxt *bp = eth_dev->data->dev_private;
4621         int rc = 0;
4622
4623         eth_dev->data->mac_addrs = rte_zmalloc("bnxt_mac_addr_tbl",
4624                                                RTE_ETHER_ADDR_LEN *
4625                                                bp->max_l2_ctx,
4626                                                0);
4627         if (eth_dev->data->mac_addrs == NULL) {
4628                 PMD_DRV_LOG(ERR, "Failed to alloc MAC addr tbl\n");
4629                 return -ENOMEM;
4630         }
4631
4632         if (bnxt_check_zero_bytes(bp->dflt_mac_addr, RTE_ETHER_ADDR_LEN)) {
4633                 if (BNXT_PF(bp))
4634                         return -EINVAL;
4635
4636                 /* Generate a random MAC address, if none was assigned by PF */
4637                 PMD_DRV_LOG(INFO, "VF MAC address not assigned by Host PF\n");
4638                 bnxt_eth_hw_addr_random(bp->mac_addr);
4639                 PMD_DRV_LOG(INFO,
4640                             "Assign random MAC:%02X:%02X:%02X:%02X:%02X:%02X\n",
4641                             bp->mac_addr[0], bp->mac_addr[1], bp->mac_addr[2],
4642                             bp->mac_addr[3], bp->mac_addr[4], bp->mac_addr[5]);
4643
4644                 rc = bnxt_hwrm_set_mac(bp);
4645                 if (!rc)
4646                         memcpy(&bp->eth_dev->data->mac_addrs[0], bp->mac_addr,
4647                                RTE_ETHER_ADDR_LEN);
4648                 return rc;
4649         }
4650
4651         /* Copy the permanent MAC from the FUNC_QCAPS response */
4652         memcpy(bp->mac_addr, bp->dflt_mac_addr, RTE_ETHER_ADDR_LEN);
4653         memcpy(&eth_dev->data->mac_addrs[0], bp->mac_addr, RTE_ETHER_ADDR_LEN);
4654
4655         return rc;
4656 }
4657
4658 static int bnxt_restore_dflt_mac(struct bnxt *bp)
4659 {
4660         int rc = 0;
4661
4662         /* MAC is already configured in FW */
4663         if (!bnxt_check_zero_bytes(bp->dflt_mac_addr, RTE_ETHER_ADDR_LEN))
4664                 return 0;
4665
4666         /* Restore the old MAC configured */
4667         rc = bnxt_hwrm_set_mac(bp);
4668         if (rc)
4669                 PMD_DRV_LOG(ERR, "Failed to restore MAC address\n");
4670
4671         return rc;
4672 }
4673
4674 static void bnxt_config_vf_req_fwd(struct bnxt *bp)
4675 {
4676         if (!BNXT_PF(bp))
4677                 return;
4678
4679 #define ALLOW_FUNC(x)   \
4680         { \
4681                 uint32_t arg = (x); \
4682                 bp->pf.vf_req_fwd[((arg) >> 5)] &= \
4683                 ~rte_cpu_to_le_32(1 << ((arg) & 0x1f)); \
4684         }
4685
4686         /* Forward all requests if firmware is new enough */
4687         if (((bp->fw_ver >= ((20 << 24) | (6 << 16) | (100 << 8))) &&
4688              (bp->fw_ver < ((20 << 24) | (7 << 16)))) ||
4689             ((bp->fw_ver >= ((20 << 24) | (8 << 16))))) {
4690                 memset(bp->pf.vf_req_fwd, 0xff, sizeof(bp->pf.vf_req_fwd));
4691         } else {
4692                 PMD_DRV_LOG(WARNING,
4693                             "Firmware too old for VF mailbox functionality\n");
4694                 memset(bp->pf.vf_req_fwd, 0, sizeof(bp->pf.vf_req_fwd));
4695         }
4696
4697         /*
4698          * The following are used for driver cleanup. If we disallow these,
4699          * VF drivers can't clean up cleanly.
4700          */
4701         ALLOW_FUNC(HWRM_FUNC_DRV_UNRGTR);
4702         ALLOW_FUNC(HWRM_VNIC_FREE);
4703         ALLOW_FUNC(HWRM_RING_FREE);
4704         ALLOW_FUNC(HWRM_RING_GRP_FREE);
4705         ALLOW_FUNC(HWRM_VNIC_RSS_COS_LB_CTX_FREE);
4706         ALLOW_FUNC(HWRM_CFA_L2_FILTER_FREE);
4707         ALLOW_FUNC(HWRM_STAT_CTX_FREE);
4708         ALLOW_FUNC(HWRM_PORT_PHY_QCFG);
4709         ALLOW_FUNC(HWRM_VNIC_TPA_CFG);
4710 }
4711
4712 uint16_t
4713 bnxt_get_svif(uint16_t port_id, bool func_svif)
4714 {
4715         struct rte_eth_dev *eth_dev;
4716         struct bnxt *bp;
4717
4718         eth_dev = &rte_eth_devices[port_id];
4719         bp = eth_dev->data->dev_private;
4720
4721         return func_svif ? bp->func_svif : bp->port_svif;
4722 }
4723
4724 uint16_t
4725 bnxt_get_vnic_id(uint16_t port)
4726 {
4727         struct rte_eth_dev *eth_dev;
4728         struct bnxt_vnic_info *vnic;
4729         struct bnxt *bp;
4730
4731         eth_dev = &rte_eth_devices[port];
4732         bp = eth_dev->data->dev_private;
4733
4734         vnic = BNXT_GET_DEFAULT_VNIC(bp);
4735
4736         return vnic->fw_vnic_id;
4737 }
4738
4739 static int bnxt_init_fw(struct bnxt *bp)
4740 {
4741         uint16_t mtu;
4742         int rc = 0;
4743
4744         bp->fw_cap = 0;
4745
4746         rc = bnxt_hwrm_ver_get(bp, DFLT_HWRM_CMD_TIMEOUT);
4747         if (rc)
4748                 return rc;
4749
4750         rc = bnxt_hwrm_func_reset(bp);
4751         if (rc)
4752                 return -EIO;
4753
4754         rc = bnxt_hwrm_vnic_qcaps(bp);
4755         if (rc)
4756                 return rc;
4757
4758         rc = bnxt_hwrm_queue_qportcfg(bp);
4759         if (rc)
4760                 return rc;
4761
4762         /* Get the MAX capabilities for this function.
4763          * This function also allocates context memory for TQM rings and
4764          * informs the firmware about this allocated backing store memory.
4765          */
4766         rc = bnxt_hwrm_func_qcaps(bp);
4767         if (rc)
4768                 return rc;
4769
4770         rc = bnxt_hwrm_func_qcfg(bp, &mtu);
4771         if (rc)
4772                 return rc;
4773
4774         bnxt_hwrm_port_mac_qcfg(bp);
4775
4776         rc = bnxt_hwrm_cfa_adv_flow_mgmt_qcaps(bp);
4777         if (rc)
4778                 return rc;
4779
4780         /* Get the adapter error recovery support info */
4781         rc = bnxt_hwrm_error_recovery_qcfg(bp);
4782         if (rc)
4783                 bp->fw_cap &= ~BNXT_FW_CAP_ERROR_RECOVERY;
4784
4785         bnxt_hwrm_port_led_qcaps(bp);
4786
4787         return 0;
4788 }
4789
4790 static int
4791 bnxt_init_locks(struct bnxt *bp)
4792 {
4793         int err;
4794
4795         err = pthread_mutex_init(&bp->flow_lock, NULL);
4796         if (err) {
4797                 PMD_DRV_LOG(ERR, "Unable to initialize flow_lock\n");
4798                 return err;
4799         }
4800
4801         err = pthread_mutex_init(&bp->def_cp_lock, NULL);
4802         if (err)
4803                 PMD_DRV_LOG(ERR, "Unable to initialize def_cp_lock\n");
4804         return err;
4805 }
4806
4807 static int bnxt_init_resources(struct bnxt *bp, bool reconfig_dev)
4808 {
4809         int rc;
4810
4811         rc = bnxt_init_fw(bp);
4812         if (rc)
4813                 return rc;
4814
4815         if (!reconfig_dev) {
4816                 rc = bnxt_setup_mac_addr(bp->eth_dev);
4817                 if (rc)
4818                         return rc;
4819         } else {
4820                 rc = bnxt_restore_dflt_mac(bp);
4821                 if (rc)
4822                         return rc;
4823         }
4824
4825         bnxt_config_vf_req_fwd(bp);
4826
4827         rc = bnxt_hwrm_func_driver_register(bp);
4828         if (rc) {
4829                 PMD_DRV_LOG(ERR, "Failed to register driver");
4830                 return -EBUSY;
4831         }
4832
4833         if (BNXT_PF(bp)) {
4834                 if (bp->pdev->max_vfs) {
4835                         rc = bnxt_hwrm_allocate_vfs(bp, bp->pdev->max_vfs);
4836                         if (rc) {
4837                                 PMD_DRV_LOG(ERR, "Failed to allocate VFs\n");
4838                                 return rc;
4839                         }
4840                 } else {
4841                         rc = bnxt_hwrm_allocate_pf_only(bp);
4842                         if (rc) {
4843                                 PMD_DRV_LOG(ERR,
4844                                             "Failed to allocate PF resources");
4845                                 return rc;
4846                         }
4847                 }
4848         }
4849
4850         rc = bnxt_alloc_mem(bp, reconfig_dev);
4851         if (rc)
4852                 return rc;
4853
4854         rc = bnxt_setup_int(bp);
4855         if (rc)
4856                 return rc;
4857
4858         rc = bnxt_request_int(bp);
4859         if (rc)
4860                 return rc;
4861
4862         rc = bnxt_init_locks(bp);
4863         if (rc)
4864                 return rc;
4865
4866         return 0;
4867 }
4868
4869 static int
4870 bnxt_parse_devarg_truflow(__rte_unused const char *key,
4871                           const char *value, void *opaque_arg)
4872 {
4873         struct bnxt *bp = opaque_arg;
4874         unsigned long truflow;
4875         char *end = NULL;
4876
4877         if (!value || !opaque_arg) {
4878                 PMD_DRV_LOG(ERR,
4879                             "Invalid parameter passed to truflow devargs.\n");
4880                 return -EINVAL;
4881         }
4882
4883         truflow = strtoul(value, &end, 10);
4884         if (end == NULL || *end != '\0' ||
4885             (truflow == ULONG_MAX && errno == ERANGE)) {
4886                 PMD_DRV_LOG(ERR,
4887                             "Invalid parameter passed to truflow devargs.\n");
4888                 return -EINVAL;
4889         }
4890
4891         if (BNXT_DEVARG_TRUFLOW_INVALID(truflow)) {
4892                 PMD_DRV_LOG(ERR,
4893                             "Invalid value passed to truflow devargs.\n");
4894                 return -EINVAL;
4895         }
4896
4897         bp->truflow = truflow;
4898         if (bp->truflow)
4899                 PMD_DRV_LOG(INFO, "Host-based truflow feature enabled.\n");
4900
4901         return 0;
4902 }
4903
4904 static void
4905 bnxt_parse_dev_args(struct bnxt *bp, struct rte_devargs *devargs)
4906 {
4907         struct rte_kvargs *kvlist;
4908
4909         if (devargs == NULL)
4910                 return;
4911
4912         kvlist = rte_kvargs_parse(devargs->args, bnxt_dev_args);
4913         if (kvlist == NULL)
4914                 return;
4915
4916         /*
4917          * Handler for "truflow" devarg.
4918          * Invoked as for ex: "-w 0000:00:0d.0,host-based-truflow=1”
4919          */
4920         rte_kvargs_process(kvlist, BNXT_DEVARG_TRUFLOW,
4921                            bnxt_parse_devarg_truflow, bp);
4922
4923         rte_kvargs_free(kvlist);
4924 }
4925
4926 static int
4927 bnxt_dev_init(struct rte_eth_dev *eth_dev)
4928 {
4929         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
4930         static int version_printed;
4931         struct bnxt *bp;
4932         int rc;
4933
4934         if (version_printed++ == 0)
4935                 PMD_DRV_LOG(INFO, "%s\n", bnxt_version);
4936
4937         eth_dev->dev_ops = &bnxt_dev_ops;
4938         eth_dev->rx_pkt_burst = &bnxt_recv_pkts;
4939         eth_dev->tx_pkt_burst = &bnxt_xmit_pkts;
4940
4941         /*
4942          * For secondary processes, we don't initialise any further
4943          * as primary has already done this work.
4944          */
4945         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
4946                 return 0;
4947
4948         rte_eth_copy_pci_info(eth_dev, pci_dev);
4949
4950         bp = eth_dev->data->dev_private;
4951
4952         /* Parse dev arguments passed on when starting the DPDK application. */
4953         bnxt_parse_dev_args(bp, pci_dev->device.devargs);
4954
4955         bp->flags &= ~BNXT_FLAG_RX_VECTOR_PKT_MODE;
4956
4957         if (bnxt_vf_pciid(pci_dev->id.device_id))
4958                 bp->flags |= BNXT_FLAG_VF;
4959
4960         if (bnxt_thor_device(pci_dev->id.device_id))
4961                 bp->flags |= BNXT_FLAG_THOR_CHIP;
4962
4963         if (pci_dev->id.device_id == BROADCOM_DEV_ID_58802 ||
4964             pci_dev->id.device_id == BROADCOM_DEV_ID_58804 ||
4965             pci_dev->id.device_id == BROADCOM_DEV_ID_58808 ||
4966             pci_dev->id.device_id == BROADCOM_DEV_ID_58802_VF)
4967                 bp->flags |= BNXT_FLAG_STINGRAY;
4968
4969         rc = bnxt_init_board(eth_dev);
4970         if (rc) {
4971                 PMD_DRV_LOG(ERR,
4972                             "Failed to initialize board rc: %x\n", rc);
4973                 return rc;
4974         }
4975
4976         rc = bnxt_alloc_hwrm_resources(bp);
4977         if (rc) {
4978                 PMD_DRV_LOG(ERR,
4979                             "Failed to allocate hwrm resource rc: %x\n", rc);
4980                 goto error_free;
4981         }
4982         rc = bnxt_init_resources(bp, false);
4983         if (rc)
4984                 goto error_free;
4985
4986         rc = bnxt_alloc_stats_mem(bp);
4987         if (rc)
4988                 goto error_free;
4989
4990         /* Pass the information to the rte_eth_dev_close() that it should also
4991          * release the private port resources.
4992          */
4993         eth_dev->data->dev_flags |= RTE_ETH_DEV_CLOSE_REMOVE;
4994
4995         PMD_DRV_LOG(INFO,
4996                     DRV_MODULE_NAME "found at mem %" PRIX64 ", node addr %pM\n",
4997                     pci_dev->mem_resource[0].phys_addr,
4998                     pci_dev->mem_resource[0].addr);
4999
5000         return 0;
5001
5002 error_free:
5003         bnxt_dev_uninit(eth_dev);
5004         return rc;
5005 }
5006
5007 static void
5008 bnxt_uninit_locks(struct bnxt *bp)
5009 {
5010         pthread_mutex_destroy(&bp->flow_lock);
5011         pthread_mutex_destroy(&bp->def_cp_lock);
5012 }
5013
5014 static int
5015 bnxt_uninit_resources(struct bnxt *bp, bool reconfig_dev)
5016 {
5017         int rc;
5018
5019         bnxt_free_int(bp);
5020         bnxt_free_mem(bp, reconfig_dev);
5021         bnxt_hwrm_func_buf_unrgtr(bp);
5022         rc = bnxt_hwrm_func_driver_unregister(bp, 0);
5023         bp->flags &= ~BNXT_FLAG_REGISTERED;
5024         bnxt_free_ctx_mem(bp);
5025         if (!reconfig_dev) {
5026                 bnxt_free_hwrm_resources(bp);
5027
5028                 if (bp->recovery_info != NULL) {
5029                         rte_free(bp->recovery_info);
5030                         bp->recovery_info = NULL;
5031                 }
5032         }
5033
5034         bnxt_uninit_locks(bp);
5035         rte_free(bp->ptp_cfg);
5036         bp->ptp_cfg = NULL;
5037         return rc;
5038 }
5039
5040 static int
5041 bnxt_dev_uninit(struct rte_eth_dev *eth_dev)
5042 {
5043         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
5044                 return -EPERM;
5045
5046         PMD_DRV_LOG(DEBUG, "Calling Device uninit\n");
5047
5048         if (eth_dev->state != RTE_ETH_DEV_UNUSED)
5049                 bnxt_dev_close_op(eth_dev);
5050
5051         return 0;
5052 }
5053
5054 static int bnxt_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
5055         struct rte_pci_device *pci_dev)
5056 {
5057         return rte_eth_dev_pci_generic_probe(pci_dev, sizeof(struct bnxt),
5058                 bnxt_dev_init);
5059 }
5060
5061 static int bnxt_pci_remove(struct rte_pci_device *pci_dev)
5062 {
5063         if (rte_eal_process_type() == RTE_PROC_PRIMARY)
5064                 return rte_eth_dev_pci_generic_remove(pci_dev,
5065                                 bnxt_dev_uninit);
5066         else
5067                 return rte_eth_dev_pci_generic_remove(pci_dev, NULL);
5068 }
5069
5070 static struct rte_pci_driver bnxt_rte_pmd = {
5071         .id_table = bnxt_pci_id_map,
5072         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
5073         .probe = bnxt_pci_probe,
5074         .remove = bnxt_pci_remove,
5075 };
5076
5077 static bool
5078 is_device_supported(struct rte_eth_dev *dev, struct rte_pci_driver *drv)
5079 {
5080         if (strcmp(dev->device->driver->name, drv->driver.name))
5081                 return false;
5082
5083         return true;
5084 }
5085
5086 bool is_bnxt_supported(struct rte_eth_dev *dev)
5087 {
5088         return is_device_supported(dev, &bnxt_rte_pmd);
5089 }
5090
5091 RTE_INIT(bnxt_init_log)
5092 {
5093         bnxt_logtype_driver = rte_log_register("pmd.net.bnxt.driver");
5094         if (bnxt_logtype_driver >= 0)
5095                 rte_log_set_level(bnxt_logtype_driver, RTE_LOG_NOTICE);
5096 }
5097
5098 RTE_PMD_REGISTER_PCI(net_bnxt, bnxt_rte_pmd);
5099 RTE_PMD_REGISTER_PCI_TABLE(net_bnxt, bnxt_pci_id_map);
5100 RTE_PMD_REGISTER_KMOD_DEP(net_bnxt, "* igb_uio | uio_pci_generic | vfio-pci");