drivers/net/bnxt/bnxt_ethdev.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2014-2021 Broadcom
   3  * All rights reserved.
   4  */
   5
   6 #include <inttypes.h>
   7 #include <stdbool.h>
   8
   9 #include <rte_dev.h>
  10 #include <ethdev_driver.h>
  11 #include <ethdev_pci.h>
  12 #include <rte_malloc.h>
  13 #include <rte_cycles.h>
  14 #include <rte_alarm.h>
  15 #include <rte_kvargs.h>
  16 #include <rte_vect.h>
  17
  18 #include "bnxt.h"
  19 #include "bnxt_filter.h"
  20 #include "bnxt_hwrm.h"
  21 #include "bnxt_irq.h"
  22 #include "bnxt_reps.h"
  23 #include "bnxt_ring.h"
  24 #include "bnxt_rxq.h"
  25 #include "bnxt_rxr.h"
  26 #include "bnxt_stats.h"
  27 #include "bnxt_txq.h"
  28 #include "bnxt_txr.h"
  29 #include "bnxt_vnic.h"
  30 #include "hsi_struct_def_dpdk.h"
  31 #include "bnxt_nvm_defs.h"
  32 #include "bnxt_tf_common.h"
  33 #include "ulp_flow_db.h"
  34 #include "rte_pmd_bnxt.h"
  35
  36 #define DRV_MODULE_NAME         "bnxt"
  37 static const char bnxt_version[] =
  38         "Broadcom NetXtreme driver " DRV_MODULE_NAME;
  39
  40 /*
  41  * The set of PCI devices this driver supports
  42  */
  43 static const struct rte_pci_id bnxt_pci_id_map[] = {
  44         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM,
  45                          BROADCOM_DEV_ID_STRATUS_NIC_VF1) },
  46         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM,
  47                          BROADCOM_DEV_ID_STRATUS_NIC_VF2) },
  48         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_STRATUS_NIC) },
  49         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414_VF) },
  50         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57304_VF) },
  51         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_NS2) },
  52         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57406_VF) },
  53         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57407_MF) },
  54         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_5741X_VF) },
  55         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_5731X_VF) },
  56         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_MF) },
  57         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57412) },
  58         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414) },
  59         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_RJ45) },
  60         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_RJ45) },
  61         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57412_MF) },
  62         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57317_RJ45) },
  63         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_SFP) },
  64         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_SFP) },
  65         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57317_SFP) },
  66         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414_MF) },
  67         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_MF) },
  68         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58802) },
  69         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58804) },
  70         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58808) },
  71         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58802_VF) },
  72         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57508) },
  73         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57504) },
  74         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57502) },
  75         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57500_VF1) },
  76         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57500_VF2) },
  77         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57508_MF1) },
  78         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57504_MF1) },
  79         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57502_MF1) },
  80         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57508_MF2) },
  81         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57504_MF2) },
  82         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57502_MF2) },
  83         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58812) },
  84         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58814) },
  85         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58818) },
  86         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58818_VF) },
  87         { .vendor_id = 0, /* sentinel */ },
  88 };
  89
  90 #define BNXT_DEVARG_TRUFLOW     "host-based-truflow"
  91 #define BNXT_DEVARG_FLOW_XSTAT  "flow-xstat"
  92 #define BNXT_DEVARG_MAX_NUM_KFLOWS  "max-num-kflows"
  93 #define BNXT_DEVARG_REPRESENTOR "representor"
  94 #define BNXT_DEVARG_REP_BASED_PF  "rep-based-pf"
  95 #define BNXT_DEVARG_REP_IS_PF  "rep-is-pf"
  96 #define BNXT_DEVARG_REP_Q_R2F  "rep-q-r2f"
  97 #define BNXT_DEVARG_REP_Q_F2R  "rep-q-f2r"
  98 #define BNXT_DEVARG_REP_FC_R2F  "rep-fc-r2f"
  99 #define BNXT_DEVARG_REP_FC_F2R  "rep-fc-f2r"
 100
 101 static const char *const bnxt_dev_args[] = {
 102         BNXT_DEVARG_REPRESENTOR,
 103         BNXT_DEVARG_TRUFLOW,
 104         BNXT_DEVARG_FLOW_XSTAT,
 105         BNXT_DEVARG_MAX_NUM_KFLOWS,
 106         BNXT_DEVARG_REP_BASED_PF,
 107         BNXT_DEVARG_REP_IS_PF,
 108         BNXT_DEVARG_REP_Q_R2F,
 109         BNXT_DEVARG_REP_Q_F2R,
 110         BNXT_DEVARG_REP_FC_R2F,
 111         BNXT_DEVARG_REP_FC_F2R,
 112         NULL
 113 };
 114
 115 /*
 116  * truflow == false to disable the feature
 117  * truflow == true to enable the feature
 118  */
 119 #define BNXT_DEVARG_TRUFLOW_INVALID(truflow)    ((truflow) > 1)
 120
 121 /*
 122  * flow_xstat == false to disable the feature
 123  * flow_xstat == true to enable the feature
 124  */
 125 #define BNXT_DEVARG_FLOW_XSTAT_INVALID(flow_xstat)      ((flow_xstat) > 1)
 126
 127 /*
 128  * rep_is_pf == false to indicate VF representor
 129  * rep_is_pf == true to indicate PF representor
 130  */
 131 #define BNXT_DEVARG_REP_IS_PF_INVALID(rep_is_pf)        ((rep_is_pf) > 1)
 132
 133 /*
 134  * rep_based_pf == Physical index of the PF
 135  */
 136 #define BNXT_DEVARG_REP_BASED_PF_INVALID(rep_based_pf)  ((rep_based_pf) > 15)
 137 /*
 138  * rep_q_r2f == Logical COS Queue index for the rep to endpoint direction
 139  */
 140 #define BNXT_DEVARG_REP_Q_R2F_INVALID(rep_q_r2f)        ((rep_q_r2f) > 3)
 141
 142 /*
 143  * rep_q_f2r == Logical COS Queue index for the endpoint to rep direction
 144  */
 145 #define BNXT_DEVARG_REP_Q_F2R_INVALID(rep_q_f2r)        ((rep_q_f2r) > 3)
 146
 147 /*
 148  * rep_fc_r2f == Flow control for the representor to endpoint direction
 149  */
 150 #define BNXT_DEVARG_REP_FC_R2F_INVALID(rep_fc_r2f)      ((rep_fc_r2f) > 1)
 151
 152 /*
 153  * rep_fc_f2r == Flow control for the endpoint to representor direction
 154  */
 155 #define BNXT_DEVARG_REP_FC_F2R_INVALID(rep_fc_f2r)      ((rep_fc_f2r) > 1)
 156
 157 int bnxt_cfa_code_dynfield_offset = -1;
 158
 159 /*
 160  * max_num_kflows must be >= 32
 161  * and must be a power-of-2 supported value
 162  * return: 1 -> invalid
 163  *         0 -> valid
 164  */
 165 static int bnxt_devarg_max_num_kflow_invalid(uint16_t max_num_kflows)
 166 {
 167         if (max_num_kflows < 32 || !rte_is_power_of_2(max_num_kflows))
 168                 return 1;
 169         return 0;
 170 }
 171
 172 static int bnxt_vlan_offload_set_op(struct rte_eth_dev *dev, int mask);
 173 static int bnxt_dev_uninit(struct rte_eth_dev *eth_dev);
 174 static int bnxt_init_resources(struct bnxt *bp, bool reconfig_dev);
 175 static int bnxt_uninit_resources(struct bnxt *bp, bool reconfig_dev);
 176 static void bnxt_cancel_fw_health_check(struct bnxt *bp);
 177 static int bnxt_restore_vlan_filters(struct bnxt *bp);
 178 static void bnxt_dev_recover(void *arg);
 179 static void bnxt_free_error_recovery_info(struct bnxt *bp);
 180 static void bnxt_free_rep_info(struct bnxt *bp);
 181
 182 int is_bnxt_in_error(struct bnxt *bp)
 183 {
 184         if (bp->flags & BNXT_FLAG_FATAL_ERROR)
 185                 return -EIO;
 186         if (bp->flags & BNXT_FLAG_FW_RESET)
 187                 return -EBUSY;
 188
 189         return 0;
 190 }
 191
 192 /***********************/
 193
 194 /*
 195  * High level utility functions
 196  */
 197
 198 static uint16_t bnxt_rss_ctxts(const struct bnxt *bp)
 199 {
 200         unsigned int num_rss_rings = RTE_MIN(bp->rx_nr_rings,
 201                                              BNXT_RSS_TBL_SIZE_P5);
 202
 203         if (!BNXT_CHIP_P5(bp))
 204                 return 1;
 205
 206         return RTE_ALIGN_MUL_CEIL(num_rss_rings,
 207                                   BNXT_RSS_ENTRIES_PER_CTX_P5) /
 208                                   BNXT_RSS_ENTRIES_PER_CTX_P5;
 209 }
 210
 211 uint16_t bnxt_rss_hash_tbl_size(const struct bnxt *bp)
 212 {
 213         if (!BNXT_CHIP_P5(bp))
 214                 return HW_HASH_INDEX_SIZE;
 215
 216         return bnxt_rss_ctxts(bp) * BNXT_RSS_ENTRIES_PER_CTX_P5;
 217 }
 218
 219 static void bnxt_free_parent_info(struct bnxt *bp)
 220 {
 221         rte_free(bp->parent);
 222         bp->parent = NULL;
 223 }
 224
 225 static void bnxt_free_pf_info(struct bnxt *bp)
 226 {
 227         rte_free(bp->pf);
 228         bp->pf = NULL;
 229 }
 230
 231 static void bnxt_free_link_info(struct bnxt *bp)
 232 {
 233         rte_free(bp->link_info);
 234         bp->link_info = NULL;
 235 }
 236
 237 static void bnxt_free_leds_info(struct bnxt *bp)
 238 {
 239         if (BNXT_VF(bp))
 240                 return;
 241
 242         rte_free(bp->leds);
 243         bp->leds = NULL;
 244 }
 245
 246 static void bnxt_free_flow_stats_info(struct bnxt *bp)
 247 {
 248         rte_free(bp->flow_stat);
 249         bp->flow_stat = NULL;
 250 }
 251
 252 static void bnxt_free_cos_queues(struct bnxt *bp)
 253 {
 254         rte_free(bp->rx_cos_queue);
 255         bp->rx_cos_queue = NULL;
 256         rte_free(bp->tx_cos_queue);
 257         bp->tx_cos_queue = NULL;
 258 }
 259
 260 static void bnxt_free_mem(struct bnxt *bp, bool reconfig)
 261 {
 262         bnxt_free_filter_mem(bp);
 263         bnxt_free_vnic_attributes(bp);
 264         bnxt_free_vnic_mem(bp);
 265
 266         /* tx/rx rings are configured as part of *_queue_setup callbacks.
 267          * If the number of rings change across fw update,
 268          * we don't have much choice except to warn the user.
 269          */
 270         if (!reconfig) {
 271                 bnxt_free_stats(bp);
 272                 bnxt_free_tx_rings(bp);
 273                 bnxt_free_rx_rings(bp);
 274         }
 275         bnxt_free_async_cp_ring(bp);
 276         bnxt_free_rxtx_nq_ring(bp);
 277
 278         rte_free(bp->grp_info);
 279         bp->grp_info = NULL;
 280 }
 281
 282 static int bnxt_alloc_parent_info(struct bnxt *bp)
 283 {
 284         bp->parent = rte_zmalloc("bnxt_parent_info",
 285                                  sizeof(struct bnxt_parent_info), 0);
 286         if (bp->parent == NULL)
 287                 return -ENOMEM;
 288
 289         return 0;
 290 }
 291
 292 static int bnxt_alloc_pf_info(struct bnxt *bp)
 293 {
 294         bp->pf = rte_zmalloc("bnxt_pf_info", sizeof(struct bnxt_pf_info), 0);
 295         if (bp->pf == NULL)
 296                 return -ENOMEM;
 297
 298         return 0;
 299 }
 300
 301 static int bnxt_alloc_link_info(struct bnxt *bp)
 302 {
 303         bp->link_info =
 304                 rte_zmalloc("bnxt_link_info", sizeof(struct bnxt_link_info), 0);
 305         if (bp->link_info == NULL)
 306                 return -ENOMEM;
 307
 308         return 0;
 309 }
 310
 311 static int bnxt_alloc_leds_info(struct bnxt *bp)
 312 {
 313         if (BNXT_VF(bp))
 314                 return 0;
 315
 316         bp->leds = rte_zmalloc("bnxt_leds",
 317                                BNXT_MAX_LED * sizeof(struct bnxt_led_info),
 318                                0);
 319         if (bp->leds == NULL)
 320                 return -ENOMEM;
 321
 322         return 0;
 323 }
 324
 325 static int bnxt_alloc_cos_queues(struct bnxt *bp)
 326 {
 327         bp->rx_cos_queue =
 328                 rte_zmalloc("bnxt_rx_cosq",
 329                             BNXT_COS_QUEUE_COUNT *
 330                             sizeof(struct bnxt_cos_queue_info),
 331                             0);
 332         if (bp->rx_cos_queue == NULL)
 333                 return -ENOMEM;
 334
 335         bp->tx_cos_queue =
 336                 rte_zmalloc("bnxt_tx_cosq",
 337                             BNXT_COS_QUEUE_COUNT *
 338                             sizeof(struct bnxt_cos_queue_info),
 339                             0);
 340         if (bp->tx_cos_queue == NULL)
 341                 return -ENOMEM;
 342
 343         return 0;
 344 }
 345
 346 static int bnxt_alloc_flow_stats_info(struct bnxt *bp)
 347 {
 348         bp->flow_stat = rte_zmalloc("bnxt_flow_xstat",
 349                                     sizeof(struct bnxt_flow_stat_info), 0);
 350         if (bp->flow_stat == NULL)
 351                 return -ENOMEM;
 352
 353         return 0;
 354 }
 355
 356 static int bnxt_alloc_mem(struct bnxt *bp, bool reconfig)
 357 {
 358         int rc;
 359
 360         rc = bnxt_alloc_ring_grps(bp);
 361         if (rc)
 362                 goto alloc_mem_err;
 363
 364         rc = bnxt_alloc_async_ring_struct(bp);
 365         if (rc)
 366                 goto alloc_mem_err;
 367
 368         rc = bnxt_alloc_vnic_mem(bp);
 369         if (rc)
 370                 goto alloc_mem_err;
 371
 372         rc = bnxt_alloc_vnic_attributes(bp);
 373         if (rc)
 374                 goto alloc_mem_err;
 375
 376         rc = bnxt_alloc_filter_mem(bp);
 377         if (rc)
 378                 goto alloc_mem_err;
 379
 380         rc = bnxt_alloc_async_cp_ring(bp);
 381         if (rc)
 382                 goto alloc_mem_err;
 383
 384         rc = bnxt_alloc_rxtx_nq_ring(bp);
 385         if (rc)
 386                 goto alloc_mem_err;
 387
 388         if (BNXT_FLOW_XSTATS_EN(bp)) {
 389                 rc = bnxt_alloc_flow_stats_info(bp);
 390                 if (rc)
 391                         goto alloc_mem_err;
 392         }
 393
 394         return 0;
 395
 396 alloc_mem_err:
 397         bnxt_free_mem(bp, reconfig);
 398         return rc;
 399 }
 400
 401 static int bnxt_setup_one_vnic(struct bnxt *bp, uint16_t vnic_id)
 402 {
 403         struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
 404         struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id];
 405         uint64_t rx_offloads = dev_conf->rxmode.offloads;
 406         struct bnxt_rx_queue *rxq;
 407         unsigned int j;
 408         int rc;
 409
 410         rc = bnxt_vnic_grp_alloc(bp, vnic);
 411         if (rc)
 412                 goto err_out;
 413
 414         PMD_DRV_LOG(DEBUG, "vnic[%d] = %p vnic->fw_grp_ids = %p\n",
 415                     vnic_id, vnic, vnic->fw_grp_ids);
 416
 417         rc = bnxt_hwrm_vnic_alloc(bp, vnic);
 418         if (rc)
 419                 goto err_out;
 420
 421         /* Alloc RSS context only if RSS mode is enabled */
 422         if (dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS) {
 423                 int j, nr_ctxs = bnxt_rss_ctxts(bp);
 424
 425                 /* RSS table size in Thor is 512.
 426                  * Cap max Rx rings to same value
 427                  */
 428                 if (bp->rx_nr_rings > BNXT_RSS_TBL_SIZE_P5) {
 429                         PMD_DRV_LOG(ERR, "RxQ cnt %d > reta_size %d\n",
 430                                     bp->rx_nr_rings, BNXT_RSS_TBL_SIZE_P5);
 431                         goto err_out;
 432                 }
 433
 434                 rc = 0;
 435                 for (j = 0; j < nr_ctxs; j++) {
 436                         rc = bnxt_hwrm_vnic_ctx_alloc(bp, vnic, j);
 437                         if (rc)
 438                                 break;
 439                 }
 440                 if (rc) {
 441                         PMD_DRV_LOG(ERR,
 442                                     "HWRM vnic %d ctx %d alloc failure rc: %x\n",
 443                                     vnic_id, j, rc);
 444                         goto err_out;
 445                 }
 446                 vnic->num_lb_ctxts = nr_ctxs;
 447         }
 448
 449         /*
 450          * Firmware sets pf pair in default vnic cfg. If the VLAN strip
 451          * setting is not available at this time, it will not be
 452          * configured correctly in the CFA.
 453          */
 454         if (rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
 455                 vnic->vlan_strip = true;
 456         else
 457                 vnic->vlan_strip = false;
 458
 459         rc = bnxt_hwrm_vnic_cfg(bp, vnic);
 460         if (rc)
 461                 goto err_out;
 462
 463         rc = bnxt_set_hwrm_vnic_filters(bp, vnic);
 464         if (rc)
 465                 goto err_out;
 466
 467         for (j = 0; j < bp->rx_num_qs_per_vnic; j++) {
 468                 rxq = bp->eth_dev->data->rx_queues[j];
 469
 470                 PMD_DRV_LOG(DEBUG,
 471                             "rxq[%d]->vnic=%p vnic->fw_grp_ids=%p\n",
 472                             j, rxq->vnic, rxq->vnic->fw_grp_ids);
 473
 474                 if (BNXT_HAS_RING_GRPS(bp) && rxq->rx_deferred_start)
 475                         rxq->vnic->fw_grp_ids[j] = INVALID_HW_RING_ID;
 476                 else
 477                         vnic->rx_queue_cnt++;
 478         }
 479
 480         PMD_DRV_LOG(DEBUG, "vnic->rx_queue_cnt = %d\n", vnic->rx_queue_cnt);
 481
 482         rc = bnxt_vnic_rss_configure(bp, vnic);
 483         if (rc)
 484                 goto err_out;
 485
 486         bnxt_hwrm_vnic_plcmode_cfg(bp, vnic);
 487
 488         rc = bnxt_hwrm_vnic_tpa_cfg(bp, vnic,
 489                                     (rx_offloads & DEV_RX_OFFLOAD_TCP_LRO) ?
 490                                     true : false);
 491         if (rc)
 492                 goto err_out;
 493
 494         return 0;
 495 err_out:
 496         PMD_DRV_LOG(ERR, "HWRM vnic %d cfg failure rc: %x\n",
 497                     vnic_id, rc);
 498         return rc;
 499 }
 500
 501 static int bnxt_register_fc_ctx_mem(struct bnxt *bp)
 502 {
 503         int rc = 0;
 504
 505         rc = bnxt_hwrm_ctx_rgtr(bp, bp->flow_stat->rx_fc_in_tbl.dma,
 506                                 &bp->flow_stat->rx_fc_in_tbl.ctx_id);
 507         if (rc)
 508                 return rc;
 509
 510         PMD_DRV_LOG(DEBUG,
 511                     "rx_fc_in_tbl.va = %p rx_fc_in_tbl.dma = %p"
 512                     " rx_fc_in_tbl.ctx_id = %d\n",
 513                     bp->flow_stat->rx_fc_in_tbl.va,
 514                     (void *)((uintptr_t)bp->flow_stat->rx_fc_in_tbl.dma),
 515                     bp->flow_stat->rx_fc_in_tbl.ctx_id);
 516
 517         rc = bnxt_hwrm_ctx_rgtr(bp, bp->flow_stat->rx_fc_out_tbl.dma,
 518                                 &bp->flow_stat->rx_fc_out_tbl.ctx_id);
 519         if (rc)
 520                 return rc;
 521
 522         PMD_DRV_LOG(DEBUG,
 523                     "rx_fc_out_tbl.va = %p rx_fc_out_tbl.dma = %p"
 524                     " rx_fc_out_tbl.ctx_id = %d\n",
 525                     bp->flow_stat->rx_fc_out_tbl.va,
 526                     (void *)((uintptr_t)bp->flow_stat->rx_fc_out_tbl.dma),
 527                     bp->flow_stat->rx_fc_out_tbl.ctx_id);
 528
 529         rc = bnxt_hwrm_ctx_rgtr(bp, bp->flow_stat->tx_fc_in_tbl.dma,
 530                                 &bp->flow_stat->tx_fc_in_tbl.ctx_id);
 531         if (rc)
 532                 return rc;
 533
 534         PMD_DRV_LOG(DEBUG,
 535                     "tx_fc_in_tbl.va = %p tx_fc_in_tbl.dma = %p"
 536                     " tx_fc_in_tbl.ctx_id = %d\n",
 537                     bp->flow_stat->tx_fc_in_tbl.va,
 538                     (void *)((uintptr_t)bp->flow_stat->tx_fc_in_tbl.dma),
 539                     bp->flow_stat->tx_fc_in_tbl.ctx_id);
 540
 541         rc = bnxt_hwrm_ctx_rgtr(bp, bp->flow_stat->tx_fc_out_tbl.dma,
 542                                 &bp->flow_stat->tx_fc_out_tbl.ctx_id);
 543         if (rc)
 544                 return rc;
 545
 546         PMD_DRV_LOG(DEBUG,
 547                     "tx_fc_out_tbl.va = %p tx_fc_out_tbl.dma = %p"
 548                     " tx_fc_out_tbl.ctx_id = %d\n",
 549                     bp->flow_stat->tx_fc_out_tbl.va,
 550                     (void *)((uintptr_t)bp->flow_stat->tx_fc_out_tbl.dma),
 551                     bp->flow_stat->tx_fc_out_tbl.ctx_id);
 552
 553         memset(bp->flow_stat->rx_fc_out_tbl.va,
 554                0,
 555                bp->flow_stat->rx_fc_out_tbl.size);
 556         rc = bnxt_hwrm_cfa_counter_cfg(bp, BNXT_DIR_RX,
 557                                        CFA_COUNTER_CFG_IN_COUNTER_TYPE_FC,
 558                                        bp->flow_stat->rx_fc_out_tbl.ctx_id,
 559                                        bp->flow_stat->max_fc,
 560                                        true);
 561         if (rc)
 562                 return rc;
 563
 564         memset(bp->flow_stat->tx_fc_out_tbl.va,
 565                0,
 566                bp->flow_stat->tx_fc_out_tbl.size);
 567         rc = bnxt_hwrm_cfa_counter_cfg(bp, BNXT_DIR_TX,
 568                                        CFA_COUNTER_CFG_IN_COUNTER_TYPE_FC,
 569                                        bp->flow_stat->tx_fc_out_tbl.ctx_id,
 570                                        bp->flow_stat->max_fc,
 571                                        true);
 572
 573         return rc;
 574 }
 575
 576 static int bnxt_alloc_ctx_mem_buf(char *type, size_t size,
 577                                   struct bnxt_ctx_mem_buf_info *ctx)
 578 {
 579         if (!ctx)
 580                 return -EINVAL;
 581
 582         ctx->va = rte_zmalloc(type, size, 0);
 583         if (ctx->va == NULL)
 584                 return -ENOMEM;
 585         rte_mem_lock_page(ctx->va);
 586         ctx->size = size;
 587         ctx->dma = rte_mem_virt2iova(ctx->va);
 588         if (ctx->dma == RTE_BAD_IOVA)
 589                 return -ENOMEM;
 590
 591         return 0;
 592 }
 593
 594 static int bnxt_init_fc_ctx_mem(struct bnxt *bp)
 595 {
 596         struct rte_pci_device *pdev = bp->pdev;
 597         char type[RTE_MEMZONE_NAMESIZE];
 598         uint16_t max_fc;
 599         int rc = 0;
 600
 601         max_fc = bp->flow_stat->max_fc;
 602
 603         sprintf(type, "bnxt_rx_fc_in_" PCI_PRI_FMT, pdev->addr.domain,
 604                 pdev->addr.bus, pdev->addr.devid, pdev->addr.function);
 605         /* 4 bytes for each counter-id */
 606         rc = bnxt_alloc_ctx_mem_buf(type,
 607                                     max_fc * 4,
 608                                     &bp->flow_stat->rx_fc_in_tbl);
 609         if (rc)
 610                 return rc;
 611
 612         sprintf(type, "bnxt_rx_fc_out_" PCI_PRI_FMT, pdev->addr.domain,
 613                 pdev->addr.bus, pdev->addr.devid, pdev->addr.function);
 614         /* 16 bytes for each counter - 8 bytes pkt_count, 8 bytes byte_count */
 615         rc = bnxt_alloc_ctx_mem_buf(type,
 616                                     max_fc * 16,
 617                                     &bp->flow_stat->rx_fc_out_tbl);
 618         if (rc)
 619                 return rc;
 620
 621         sprintf(type, "bnxt_tx_fc_in_" PCI_PRI_FMT, pdev->addr.domain,
 622                 pdev->addr.bus, pdev->addr.devid, pdev->addr.function);
 623         /* 4 bytes for each counter-id */
 624         rc = bnxt_alloc_ctx_mem_buf(type,
 625                                     max_fc * 4,
 626                                     &bp->flow_stat->tx_fc_in_tbl);
 627         if (rc)
 628                 return rc;
 629
 630         sprintf(type, "bnxt_tx_fc_out_" PCI_PRI_FMT, pdev->addr.domain,
 631                 pdev->addr.bus, pdev->addr.devid, pdev->addr.function);
 632         /* 16 bytes for each counter - 8 bytes pkt_count, 8 bytes byte_count */
 633         rc = bnxt_alloc_ctx_mem_buf(type,
 634                                     max_fc * 16,
 635                                     &bp->flow_stat->tx_fc_out_tbl);
 636         if (rc)
 637                 return rc;
 638
 639         rc = bnxt_register_fc_ctx_mem(bp);
 640
 641         return rc;
 642 }
 643
 644 static int bnxt_init_ctx_mem(struct bnxt *bp)
 645 {
 646         int rc = 0;
 647
 648         if (!(bp->fw_cap & BNXT_FW_CAP_ADV_FLOW_COUNTERS) ||
 649             !(BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp)) ||
 650             !BNXT_FLOW_XSTATS_EN(bp))
 651                 return 0;
 652
 653         rc = bnxt_hwrm_cfa_counter_qcaps(bp, &bp->flow_stat->max_fc);
 654         if (rc)
 655                 return rc;
 656
 657         rc = bnxt_init_fc_ctx_mem(bp);
 658
 659         return rc;
 660 }
 661
 662 static int bnxt_update_phy_setting(struct bnxt *bp)
 663 {
 664         struct rte_eth_link new;
 665         int rc;
 666
 667         rc = bnxt_get_hwrm_link_config(bp, &new);
 668         if (rc) {
 669                 PMD_DRV_LOG(ERR, "Failed to get link settings\n");
 670                 return rc;
 671         }
 672
 673         /*
 674          * On BCM957508-N2100 adapters, FW will not allow any user other
 675          * than BMC to shutdown the port. bnxt_get_hwrm_link_config() call
 676          * always returns link up. Force phy update always in that case.
 677          */
 678         if (!new.link_status || IS_BNXT_DEV_957508_N2100(bp)) {
 679                 rc = bnxt_set_hwrm_link_config(bp, true);
 680                 if (rc) {
 681                         PMD_DRV_LOG(ERR, "Failed to update PHY settings\n");
 682                         return rc;
 683                 }
 684         }
 685
 686         return rc;
 687 }
 688
 689 static void bnxt_free_prev_ring_stats(struct bnxt *bp)
 690 {
 691         rte_free(bp->prev_rx_ring_stats);
 692         rte_free(bp->prev_tx_ring_stats);
 693
 694         bp->prev_rx_ring_stats = NULL;
 695         bp->prev_tx_ring_stats = NULL;
 696 }
 697
 698 static int bnxt_alloc_prev_ring_stats(struct bnxt *bp)
 699 {
 700         bp->prev_rx_ring_stats =  rte_zmalloc("bnxt_prev_rx_ring_stats",
 701                                               sizeof(struct bnxt_ring_stats) *
 702                                               bp->rx_cp_nr_rings,
 703                                               0);
 704         if (bp->prev_rx_ring_stats == NULL)
 705                 return -ENOMEM;
 706
 707         bp->prev_tx_ring_stats = rte_zmalloc("bnxt_prev_tx_ring_stats",
 708                                              sizeof(struct bnxt_ring_stats) *
 709                                              bp->tx_cp_nr_rings,
 710                                              0);
 711         if (bp->prev_tx_ring_stats == NULL)
 712                 goto error;
 713
 714         return 0;
 715
 716 error:
 717         bnxt_free_prev_ring_stats(bp);
 718         return -ENOMEM;
 719 }
 720
 721 static int bnxt_start_nic(struct bnxt *bp)
 722 {
 723         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(bp->eth_dev);
 724         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
 725         uint32_t intr_vector = 0;
 726         uint32_t queue_id, base = BNXT_MISC_VEC_ID;
 727         uint32_t vec = BNXT_MISC_VEC_ID;
 728         unsigned int i, j;
 729         int rc;
 730
 731         if (bp->eth_dev->data->mtu > RTE_ETHER_MTU) {
 732                 bp->eth_dev->data->dev_conf.rxmode.offloads |=
 733                         DEV_RX_OFFLOAD_JUMBO_FRAME;
 734                 bp->flags |= BNXT_FLAG_JUMBO;
 735         } else {
 736                 bp->eth_dev->data->dev_conf.rxmode.offloads &=
 737                         ~DEV_RX_OFFLOAD_JUMBO_FRAME;
 738                 bp->flags &= ~BNXT_FLAG_JUMBO;
 739         }
 740
 741         /* THOR does not support ring groups.
 742          * But we will use the array to save RSS context IDs.
 743          */
 744         if (BNXT_CHIP_P5(bp))
 745                 bp->max_ring_grps = BNXT_MAX_RSS_CTXTS_P5;
 746
 747         rc = bnxt_alloc_all_hwrm_stat_ctxs(bp);
 748         if (rc) {
 749                 PMD_DRV_LOG(ERR, "HWRM stat ctx alloc failure rc: %x\n", rc);
 750                 goto err_out;
 751         }
 752
 753         rc = bnxt_alloc_hwrm_rings(bp);
 754         if (rc) {
 755                 PMD_DRV_LOG(ERR, "HWRM ring alloc failure rc: %x\n", rc);
 756                 goto err_out;
 757         }
 758
 759         rc = bnxt_alloc_all_hwrm_ring_grps(bp);
 760         if (rc) {
 761                 PMD_DRV_LOG(ERR, "HWRM ring grp alloc failure: %x\n", rc);
 762                 goto err_out;
 763         }
 764
 765         if (!(bp->vnic_cap_flags & BNXT_VNIC_CAP_COS_CLASSIFY))
 766                 goto skip_cosq_cfg;
 767
 768         for (j = 0, i = 0; i < BNXT_COS_QUEUE_COUNT; i++) {
 769                 if (bp->rx_cos_queue[i].id != 0xff) {
 770                         struct bnxt_vnic_info *vnic = &bp->vnic_info[j++];
 771
 772                         if (!vnic) {
 773                                 PMD_DRV_LOG(ERR,
 774                                             "Num pools more than FW profile\n");
 775                                 rc = -EINVAL;
 776                                 goto err_out;
 777                         }
 778                         vnic->cos_queue_id = bp->rx_cos_queue[i].id;
 779                         bp->rx_cosq_cnt++;
 780                 }
 781         }
 782
 783 skip_cosq_cfg:
 784         rc = bnxt_mq_rx_configure(bp);
 785         if (rc) {
 786                 PMD_DRV_LOG(ERR, "MQ mode configure failure rc: %x\n", rc);
 787                 goto err_out;
 788         }
 789
 790         /* default vnic 0 */
 791         rc = bnxt_setup_one_vnic(bp, 0);
 792         if (rc)
 793                 goto err_out;
 794         /* VNIC configuration */
 795         if (BNXT_RFS_NEEDS_VNIC(bp)) {
 796                 for (i = 1; i < bp->nr_vnics; i++) {
 797                         rc = bnxt_setup_one_vnic(bp, i);
 798                         if (rc)
 799                                 goto err_out;
 800                 }
 801         }
 802
 803         rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, &bp->vnic_info[0], 0, NULL);
 804         if (rc) {
 805                 PMD_DRV_LOG(ERR,
 806                         "HWRM cfa l2 rx mask failure rc: %x\n", rc);
 807                 goto err_out;
 808         }
 809
 810         /* check and configure queue intr-vector mapping */
 811         if ((rte_intr_cap_multiple(intr_handle) ||
 812              !RTE_ETH_DEV_SRIOV(bp->eth_dev).active) &&
 813             bp->eth_dev->data->dev_conf.intr_conf.rxq != 0) {
 814                 intr_vector = bp->eth_dev->data->nb_rx_queues;
 815                 PMD_DRV_LOG(DEBUG, "intr_vector = %d\n", intr_vector);
 816                 if (intr_vector > bp->rx_cp_nr_rings) {
 817                         PMD_DRV_LOG(ERR, "At most %d intr queues supported",
 818                                         bp->rx_cp_nr_rings);
 819                         return -ENOTSUP;
 820                 }
 821                 rc = rte_intr_efd_enable(intr_handle, intr_vector);
 822                 if (rc)
 823                         return rc;
 824         }
 825
 826         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
 827                 intr_handle->intr_vec =
 828                         rte_zmalloc("intr_vec",
 829                                     bp->eth_dev->data->nb_rx_queues *
 830                                     sizeof(int), 0);
 831                 if (intr_handle->intr_vec == NULL) {
 832                         PMD_DRV_LOG(ERR, "Failed to allocate %d rx_queues"
 833                                 " intr_vec", bp->eth_dev->data->nb_rx_queues);
 834                         rc = -ENOMEM;
 835                         goto err_out;
 836                 }
 837                 PMD_DRV_LOG(DEBUG, "intr_handle->intr_vec = %p "
 838                         "intr_handle->nb_efd = %d intr_handle->max_intr = %d\n",
 839                          intr_handle->intr_vec, intr_handle->nb_efd,
 840                         intr_handle->max_intr);
 841                 for (queue_id = 0; queue_id < bp->eth_dev->data->nb_rx_queues;
 842                      queue_id++) {
 843                         intr_handle->intr_vec[queue_id] =
 844                                                         vec + BNXT_RX_VEC_START;
 845                         if (vec < base + intr_handle->nb_efd - 1)
 846                                 vec++;
 847                 }
 848         }
 849
 850         /* enable uio/vfio intr/eventfd mapping */
 851         rc = rte_intr_enable(intr_handle);
 852 #ifndef RTE_EXEC_ENV_FREEBSD
 853         /* In FreeBSD OS, nic_uio driver does not support interrupts */
 854         if (rc)
 855                 goto err_out;
 856 #endif
 857
 858         rc = bnxt_update_phy_setting(bp);
 859         if (rc)
 860                 goto err_out;
 861
 862         bp->mark_table = rte_zmalloc("bnxt_mark_table", BNXT_MARK_TABLE_SZ, 0);
 863         if (!bp->mark_table)
 864                 PMD_DRV_LOG(ERR, "Allocation of mark table failed\n");
 865
 866         return 0;
 867
 868 err_out:
 869         /* Some of the error status returned by FW may not be from errno.h */
 870         if (rc > 0)
 871                 rc = -EIO;
 872
 873         return rc;
 874 }
 875
 876 static int bnxt_shutdown_nic(struct bnxt *bp)
 877 {
 878         bnxt_free_all_hwrm_resources(bp);
 879         bnxt_free_all_filters(bp);
 880         bnxt_free_all_vnics(bp);
 881         return 0;
 882 }
 883
 884 /*
 885  * Device configuration and status function
 886  */
 887
 888 uint32_t bnxt_get_speed_capabilities(struct bnxt *bp)
 889 {
 890         uint32_t link_speed = 0;
 891         uint32_t speed_capa = 0;
 892
 893         if (bp->link_info == NULL)
 894                 return 0;
 895
 896         link_speed = bp->link_info->support_speeds;
 897
 898         /* If PAM4 is configured, use PAM4 supported speed */
 899         if (link_speed == 0 && bp->link_info->support_pam4_speeds > 0)
 900                 link_speed = bp->link_info->support_pam4_speeds;
 901
 902         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_100MB)
 903                 speed_capa |= ETH_LINK_SPEED_100M;
 904         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_100MBHD)
 905                 speed_capa |= ETH_LINK_SPEED_100M_HD;
 906         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_1GB)
 907                 speed_capa |= ETH_LINK_SPEED_1G;
 908         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_2_5GB)
 909                 speed_capa |= ETH_LINK_SPEED_2_5G;
 910         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_10GB)
 911                 speed_capa |= ETH_LINK_SPEED_10G;
 912         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_20GB)
 913                 speed_capa |= ETH_LINK_SPEED_20G;
 914         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_25GB)
 915                 speed_capa |= ETH_LINK_SPEED_25G;
 916         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_40GB)
 917                 speed_capa |= ETH_LINK_SPEED_40G;
 918         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_50GB)
 919                 speed_capa |= ETH_LINK_SPEED_50G;
 920         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_100GB)
 921                 speed_capa |= ETH_LINK_SPEED_100G;
 922         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_PAM4_SPEEDS_50G)
 923                 speed_capa |= ETH_LINK_SPEED_50G;
 924         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_PAM4_SPEEDS_100G)
 925                 speed_capa |= ETH_LINK_SPEED_100G;
 926         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_PAM4_SPEEDS_200G)
 927                 speed_capa |= ETH_LINK_SPEED_200G;
 928
 929         if (bp->link_info->auto_mode ==
 930             HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_MODE_NONE)
 931                 speed_capa |= ETH_LINK_SPEED_FIXED;
 932
 933         return speed_capa;
 934 }
 935
 936 static int bnxt_dev_info_get_op(struct rte_eth_dev *eth_dev,
 937                                 struct rte_eth_dev_info *dev_info)
 938 {
 939         struct rte_pci_device *pdev = RTE_DEV_TO_PCI(eth_dev->device);
 940         struct bnxt *bp = eth_dev->data->dev_private;
 941         uint16_t max_vnics, i, j, vpool, vrxq;
 942         unsigned int max_rx_rings;
 943         int rc;
 944
 945         rc = is_bnxt_in_error(bp);
 946         if (rc)
 947                 return rc;
 948
 949         /* MAC Specifics */
 950         dev_info->max_mac_addrs = bp->max_l2_ctx;
 951         dev_info->max_hash_mac_addrs = 0;
 952
 953         /* PF/VF specifics */
 954         if (BNXT_PF(bp))
 955                 dev_info->max_vfs = pdev->max_vfs;
 956
 957         max_rx_rings = bnxt_max_rings(bp);
 958         /* For the sake of symmetry, max_rx_queues = max_tx_queues */
 959         dev_info->max_rx_queues = max_rx_rings;
 960         dev_info->max_tx_queues = max_rx_rings;
 961         dev_info->reta_size = bnxt_rss_hash_tbl_size(bp);
 962         dev_info->hash_key_size = 40;
 963         max_vnics = bp->max_vnics;
 964
 965         /* MTU specifics */
 966         dev_info->min_mtu = RTE_ETHER_MIN_MTU;
 967         dev_info->max_mtu = BNXT_MAX_MTU;
 968
 969         /* Fast path specifics */
 970         dev_info->min_rx_bufsize = 1;
 971         dev_info->max_rx_pktlen = BNXT_MAX_PKT_LEN;
 972
 973         dev_info->rx_offload_capa = BNXT_DEV_RX_OFFLOAD_SUPPORT;
 974         if (bp->flags & BNXT_FLAG_PTP_SUPPORTED)
 975                 dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_TIMESTAMP;
 976         dev_info->tx_queue_offload_capa = DEV_TX_OFFLOAD_MBUF_FAST_FREE;
 977         dev_info->tx_offload_capa = BNXT_DEV_TX_OFFLOAD_SUPPORT |
 978                                     dev_info->tx_queue_offload_capa;
 979         dev_info->flow_type_rss_offloads = BNXT_ETH_RSS_SUPPORT;
 980
 981         dev_info->speed_capa = bnxt_get_speed_capabilities(bp);
 982
 983         /* *INDENT-OFF* */
 984         dev_info->default_rxconf = (struct rte_eth_rxconf) {
 985                 .rx_thresh = {
 986                         .pthresh = 8,
 987                         .hthresh = 8,
 988                         .wthresh = 0,
 989                 },
 990                 .rx_free_thresh = 32,
 991                 .rx_drop_en = BNXT_DEFAULT_RX_DROP_EN,
 992         };
 993
 994         dev_info->default_txconf = (struct rte_eth_txconf) {
 995                 .tx_thresh = {
 996                         .pthresh = 32,
 997                         .hthresh = 0,
 998                         .wthresh = 0,
 999                 },
1000                 .tx_free_thresh = 32,
1001                 .tx_rs_thresh = 32,
1002         };
1003         eth_dev->data->dev_conf.intr_conf.lsc = 1;
1004
1005         eth_dev->data->dev_conf.intr_conf.rxq = 1;
1006         dev_info->rx_desc_lim.nb_min = BNXT_MIN_RING_DESC;
1007         dev_info->rx_desc_lim.nb_max = BNXT_MAX_RX_RING_DESC;
1008         dev_info->tx_desc_lim.nb_min = BNXT_MIN_RING_DESC;
1009         dev_info->tx_desc_lim.nb_max = BNXT_MAX_TX_RING_DESC;
1010
1011         if (BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp)) {
1012                 dev_info->switch_info.name = eth_dev->device->name;
1013                 dev_info->switch_info.domain_id = bp->switch_domain_id;
1014                 dev_info->switch_info.port_id =
1015                                 BNXT_PF(bp) ? BNXT_SWITCH_PORT_ID_PF :
1016                                     BNXT_SWITCH_PORT_ID_TRUSTED_VF;
1017         }
1018
1019         /* *INDENT-ON* */
1020
1021         /*
1022          * TODO: default_rxconf, default_txconf, rx_desc_lim, and tx_desc_lim
1023          *       need further investigation.
1024          */
1025
1026         /* VMDq resources */
1027         vpool = 64; /* ETH_64_POOLS */
1028         vrxq = 128; /* ETH_VMDQ_DCB_NUM_QUEUES */
1029         for (i = 0; i < 4; vpool >>= 1, i++) {
1030                 if (max_vnics > vpool) {
1031                         for (j = 0; j < 5; vrxq >>= 1, j++) {
1032                                 if (dev_info->max_rx_queues > vrxq) {
1033                                         if (vpool > vrxq)
1034                                                 vpool = vrxq;
1035                                         goto found;
1036                                 }
1037                         }
1038                         /* Not enough resources to support VMDq */
1039                         break;
1040                 }
1041         }
1042         /* Not enough resources to support VMDq */
1043         vpool = 0;
1044         vrxq = 0;
1045 found:
1046         dev_info->max_vmdq_pools = vpool;
1047         dev_info->vmdq_queue_num = vrxq;
1048
1049         dev_info->vmdq_pool_base = 0;
1050         dev_info->vmdq_queue_base = 0;
1051
1052         return 0;
1053 }
1054
1055 /* Configure the device based on the configuration provided */
1056 static int bnxt_dev_configure_op(struct rte_eth_dev *eth_dev)
1057 {
1058         struct bnxt *bp = eth_dev->data->dev_private;
1059         uint64_t rx_offloads = eth_dev->data->dev_conf.rxmode.offloads;
1060         int rc;
1061
1062         bp->rx_queues = (void *)eth_dev->data->rx_queues;
1063         bp->tx_queues = (void *)eth_dev->data->tx_queues;
1064         bp->tx_nr_rings = eth_dev->data->nb_tx_queues;
1065         bp->rx_nr_rings = eth_dev->data->nb_rx_queues;
1066
1067         rc = is_bnxt_in_error(bp);
1068         if (rc)
1069                 return rc;
1070
1071         if (BNXT_VF(bp) && (bp->flags & BNXT_FLAG_NEW_RM)) {
1072                 rc = bnxt_hwrm_check_vf_rings(bp);
1073                 if (rc) {
1074                         PMD_DRV_LOG(ERR, "HWRM insufficient resources\n");
1075                         return -ENOSPC;
1076                 }
1077
1078                 /* If a resource has already been allocated - in this case
1079                  * it is the async completion ring, free it. Reallocate it after
1080                  * resource reservation. This will ensure the resource counts
1081                  * are calculated correctly.
1082                  */
1083
1084                 pthread_mutex_lock(&bp->def_cp_lock);
1085
1086                 if (!BNXT_HAS_NQ(bp) && bp->async_cp_ring) {
1087                         bnxt_disable_int(bp);
1088                         bnxt_free_cp_ring(bp, bp->async_cp_ring);
1089                 }
1090
1091                 rc = bnxt_hwrm_func_reserve_vf_resc(bp, false);
1092                 if (rc) {
1093                         PMD_DRV_LOG(ERR, "HWRM resource alloc fail:%x\n", rc);
1094                         pthread_mutex_unlock(&bp->def_cp_lock);
1095                         return -ENOSPC;
1096                 }
1097
1098                 if (!BNXT_HAS_NQ(bp) && bp->async_cp_ring) {
1099                         rc = bnxt_alloc_async_cp_ring(bp);
1100                         if (rc) {
1101                                 pthread_mutex_unlock(&bp->def_cp_lock);
1102                                 return rc;
1103                         }
1104                         bnxt_enable_int(bp);
1105                 }
1106
1107                 pthread_mutex_unlock(&bp->def_cp_lock);
1108         }
1109
1110         /* Inherit new configurations */
1111         if (eth_dev->data->nb_rx_queues > bp->max_rx_rings ||
1112             eth_dev->data->nb_tx_queues > bp->max_tx_rings ||
1113             eth_dev->data->nb_rx_queues + eth_dev->data->nb_tx_queues
1114                 + BNXT_NUM_ASYNC_CPR(bp) > bp->max_cp_rings ||
1115             eth_dev->data->nb_rx_queues + eth_dev->data->nb_tx_queues >
1116             bp->max_stat_ctx)
1117                 goto resource_error;
1118
1119         if (BNXT_HAS_RING_GRPS(bp) &&
1120             (uint32_t)(eth_dev->data->nb_rx_queues) > bp->max_ring_grps)
1121                 goto resource_error;
1122
1123         if (!(eth_dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_RSS) &&
1124             bp->max_vnics < eth_dev->data->nb_rx_queues)
1125                 goto resource_error;
1126
1127         bp->rx_cp_nr_rings = bp->rx_nr_rings;
1128         bp->tx_cp_nr_rings = bp->tx_nr_rings;
1129
1130         if (eth_dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG)
1131                 rx_offloads |= DEV_RX_OFFLOAD_RSS_HASH;
1132         eth_dev->data->dev_conf.rxmode.offloads = rx_offloads;
1133
1134         if (rx_offloads & DEV_RX_OFFLOAD_JUMBO_FRAME) {
1135                 eth_dev->data->mtu =
1136                         eth_dev->data->dev_conf.rxmode.max_rx_pkt_len -
1137                         RTE_ETHER_HDR_LEN - RTE_ETHER_CRC_LEN - VLAN_TAG_SIZE *
1138                         BNXT_NUM_VLANS;
1139                 bnxt_mtu_set_op(eth_dev, eth_dev->data->mtu);
1140         }
1141         return 0;
1142
1143 resource_error:
1144         PMD_DRV_LOG(ERR,
1145                     "Insufficient resources to support requested config\n");
1146         PMD_DRV_LOG(ERR,
1147                     "Num Queues Requested: Tx %d, Rx %d\n",
1148                     eth_dev->data->nb_tx_queues,
1149                     eth_dev->data->nb_rx_queues);
1150         PMD_DRV_LOG(ERR,
1151                     "MAX: TxQ %d, RxQ %d, CQ %d Stat %d, Grp %d, Vnic %d\n",
1152                     bp->max_tx_rings, bp->max_rx_rings, bp->max_cp_rings,
1153                     bp->max_stat_ctx, bp->max_ring_grps, bp->max_vnics);
1154         return -ENOSPC;
1155 }
1156
1157 void bnxt_print_link_info(struct rte_eth_dev *eth_dev)
1158 {
1159         struct rte_eth_link *link = &eth_dev->data->dev_link;
1160
1161         if (link->link_status)
1162                 PMD_DRV_LOG(INFO, "Port %d Link Up - speed %u Mbps - %s\n",
1163                         eth_dev->data->port_id,
1164                         (uint32_t)link->link_speed,
1165                         (link->link_duplex == ETH_LINK_FULL_DUPLEX) ?
1166                         ("full-duplex") : ("half-duplex\n"));
1167         else
1168                 PMD_DRV_LOG(INFO, "Port %d Link Down\n",
1169                         eth_dev->data->port_id);
1170 }
1171
1172 /*
1173  * Determine whether the current configuration requires support for scattered
1174  * receive; return 1 if scattered receive is required and 0 if not.
1175  */
1176 static int bnxt_scattered_rx(struct rte_eth_dev *eth_dev)
1177 {
1178         uint16_t buf_size;
1179         int i;
1180
1181         if (eth_dev->data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_SCATTER)
1182                 return 1;
1183
1184         if (eth_dev->data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_TCP_LRO)
1185                 return 1;
1186
1187         for (i = 0; i < eth_dev->data->nb_rx_queues; i++) {
1188                 struct bnxt_rx_queue *rxq = eth_dev->data->rx_queues[i];
1189
1190                 buf_size = (uint16_t)(rte_pktmbuf_data_room_size(rxq->mb_pool) -
1191                                       RTE_PKTMBUF_HEADROOM);
1192                 if (eth_dev->data->dev_conf.rxmode.max_rx_pkt_len > buf_size)
1193                         return 1;
1194         }
1195         return 0;
1196 }
1197
1198 static eth_rx_burst_t
1199 bnxt_receive_function(struct rte_eth_dev *eth_dev)
1200 {
1201         struct bnxt *bp = eth_dev->data->dev_private;
1202
1203         /* Disable vector mode RX for Stingray2 for now */
1204         if (BNXT_CHIP_SR2(bp)) {
1205                 bp->flags &= ~BNXT_FLAG_RX_VECTOR_PKT_MODE;
1206                 return bnxt_recv_pkts;
1207         }
1208
1209 #if (defined(RTE_ARCH_X86) || defined(RTE_ARCH_ARM64)) && \
1210         !defined(RTE_LIBRTE_IEEE1588)
1211
1212         /* Vector mode receive cannot be enabled if scattered rx is in use. */
1213         if (eth_dev->data->scattered_rx)
1214                 goto use_scalar_rx;
1215
1216         /*
1217          * Vector mode receive cannot be enabled if Truflow is enabled or if
1218          * asynchronous completions and receive completions can be placed in
1219          * the same completion ring.
1220          */
1221         if (BNXT_TRUFLOW_EN(bp) || !BNXT_NUM_ASYNC_CPR(bp))
1222                 goto use_scalar_rx;
1223
1224         /*
1225          * Vector mode receive cannot be enabled if any receive offloads outside
1226          * a limited subset have been enabled.
1227          */
1228         if (eth_dev->data->dev_conf.rxmode.offloads &
1229                 ~(DEV_RX_OFFLOAD_VLAN_STRIP |
1230                   DEV_RX_OFFLOAD_KEEP_CRC |
1231                   DEV_RX_OFFLOAD_JUMBO_FRAME |
1232                   DEV_RX_OFFLOAD_IPV4_CKSUM |
1233                   DEV_RX_OFFLOAD_UDP_CKSUM |
1234                   DEV_RX_OFFLOAD_TCP_CKSUM |
1235                   DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM |
1236                   DEV_RX_OFFLOAD_OUTER_UDP_CKSUM |
1237                   DEV_RX_OFFLOAD_RSS_HASH |
1238                   DEV_RX_OFFLOAD_VLAN_FILTER))
1239                 goto use_scalar_rx;
1240
1241 #if defined(RTE_ARCH_X86) && defined(CC_AVX2_SUPPORT)
1242         if (rte_vect_get_max_simd_bitwidth() >= RTE_VECT_SIMD_256 &&
1243             rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX2) == 1) {
1244                 PMD_DRV_LOG(INFO,
1245                             "Using AVX2 vector mode receive for port %d\n",
1246                             eth_dev->data->port_id);
1247                 bp->flags |= BNXT_FLAG_RX_VECTOR_PKT_MODE;
1248                 return bnxt_recv_pkts_vec_avx2;
1249         }
1250  #endif
1251         if (rte_vect_get_max_simd_bitwidth() >= RTE_VECT_SIMD_128) {
1252                 PMD_DRV_LOG(INFO,
1253                             "Using SSE vector mode receive for port %d\n",
1254                             eth_dev->data->port_id);
1255                 bp->flags |= BNXT_FLAG_RX_VECTOR_PKT_MODE;
1256                 return bnxt_recv_pkts_vec;
1257         }
1258
1259 use_scalar_rx:
1260         PMD_DRV_LOG(INFO, "Vector mode receive disabled for port %d\n",
1261                     eth_dev->data->port_id);
1262         PMD_DRV_LOG(INFO,
1263                     "Port %d scatter: %d rx offload: %" PRIX64 "\n",
1264                     eth_dev->data->port_id,
1265                     eth_dev->data->scattered_rx,
1266                     eth_dev->data->dev_conf.rxmode.offloads);
1267 #endif
1268         bp->flags &= ~BNXT_FLAG_RX_VECTOR_PKT_MODE;
1269         return bnxt_recv_pkts;
1270 }
1271
1272 static eth_tx_burst_t
1273 bnxt_transmit_function(struct rte_eth_dev *eth_dev)
1274 {
1275         struct bnxt *bp = eth_dev->data->dev_private;
1276
1277         /* Disable vector mode TX for Stingray2 for now */
1278         if (BNXT_CHIP_SR2(bp))
1279                 return bnxt_xmit_pkts;
1280
1281 #if defined(RTE_ARCH_X86) || defined(RTE_ARCH_ARM64) && \
1282         !defined(RTE_LIBRTE_IEEE1588)
1283         uint64_t offloads = eth_dev->data->dev_conf.txmode.offloads;
1284
1285         /*
1286          * Vector mode transmit can be enabled only if not using scatter rx
1287          * or tx offloads.
1288          */
1289         if (eth_dev->data->scattered_rx ||
1290             (offloads & ~DEV_TX_OFFLOAD_MBUF_FAST_FREE) ||
1291             BNXT_TRUFLOW_EN(bp))
1292                 goto use_scalar_tx;
1293
1294 #if defined(RTE_ARCH_X86) && defined(CC_AVX2_SUPPORT)
1295         if (rte_vect_get_max_simd_bitwidth() >= RTE_VECT_SIMD_256 &&
1296             rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX2) == 1) {
1297                 PMD_DRV_LOG(INFO,
1298                             "Using AVX2 vector mode transmit for port %d\n",
1299                             eth_dev->data->port_id);
1300                 return bnxt_xmit_pkts_vec_avx2;
1301         }
1302 #endif
1303         if (rte_vect_get_max_simd_bitwidth() >= RTE_VECT_SIMD_128) {
1304                 PMD_DRV_LOG(INFO,
1305                             "Using SSE vector mode transmit for port %d\n",
1306                             eth_dev->data->port_id);
1307                 return bnxt_xmit_pkts_vec;
1308         }
1309
1310 use_scalar_tx:
1311         PMD_DRV_LOG(INFO, "Vector mode transmit disabled for port %d\n",
1312                     eth_dev->data->port_id);
1313         PMD_DRV_LOG(INFO,
1314                     "Port %d scatter: %d tx offload: %" PRIX64 "\n",
1315                     eth_dev->data->port_id,
1316                     eth_dev->data->scattered_rx,
1317                     offloads);
1318 #endif
1319         return bnxt_xmit_pkts;
1320 }
1321
1322 static int bnxt_handle_if_change_status(struct bnxt *bp)
1323 {
1324         int rc;
1325
1326         /* Since fw has undergone a reset and lost all contexts,
1327          * set fatal flag to not issue hwrm during cleanup
1328          */
1329         bp->flags |= BNXT_FLAG_FATAL_ERROR;
1330         bnxt_uninit_resources(bp, true);
1331
1332         /* clear fatal flag so that re-init happens */
1333         bp->flags &= ~BNXT_FLAG_FATAL_ERROR;
1334         rc = bnxt_init_resources(bp, true);
1335
1336         bp->flags &= ~BNXT_FLAG_IF_CHANGE_HOT_FW_RESET_DONE;
1337
1338         return rc;
1339 }
1340
1341 static int bnxt_dev_set_link_up_op(struct rte_eth_dev *eth_dev)
1342 {
1343         struct bnxt *bp = eth_dev->data->dev_private;
1344         int rc = 0;
1345
1346         if (!BNXT_SINGLE_PF(bp))
1347                 return -ENOTSUP;
1348
1349         if (!bp->link_info->link_up)
1350                 rc = bnxt_set_hwrm_link_config(bp, true);
1351         if (!rc)
1352                 eth_dev->data->dev_link.link_status = 1;
1353
1354         bnxt_print_link_info(eth_dev);
1355         return rc;
1356 }
1357
1358 static int bnxt_dev_set_link_down_op(struct rte_eth_dev *eth_dev)
1359 {
1360         struct bnxt *bp = eth_dev->data->dev_private;
1361
1362         if (!BNXT_SINGLE_PF(bp))
1363                 return -ENOTSUP;
1364
1365         eth_dev->data->dev_link.link_status = 0;
1366         bnxt_set_hwrm_link_config(bp, false);
1367         bp->link_info->link_up = 0;
1368
1369         return 0;
1370 }
1371
1372 static void bnxt_free_switch_domain(struct bnxt *bp)
1373 {
1374         int rc = 0;
1375
1376         if (!(BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp)))
1377                 return;
1378
1379         rc = rte_eth_switch_domain_free(bp->switch_domain_id);
1380         if (rc)
1381                 PMD_DRV_LOG(ERR, "free switch domain:%d fail: %d\n",
1382                             bp->switch_domain_id, rc);
1383 }
1384
1385 static void bnxt_ptp_get_current_time(void *arg)
1386 {
1387         struct bnxt *bp = arg;
1388         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
1389         int rc;
1390
1391         rc = is_bnxt_in_error(bp);
1392         if (rc)
1393                 return;
1394
1395         if (!ptp)
1396                 return;
1397
1398         bnxt_hwrm_port_ts_query(bp, BNXT_PTP_FLAGS_CURRENT_TIME,
1399                                 &ptp->current_time);
1400
1401         rc = rte_eal_alarm_set(US_PER_S, bnxt_ptp_get_current_time, (void *)bp);
1402         if (rc != 0) {
1403                 PMD_DRV_LOG(ERR, "Failed to re-schedule PTP alarm\n");
1404                 bp->flags2 &= ~BNXT_FLAGS2_PTP_ALARM_SCHEDULED;
1405         }
1406 }
1407
1408 static int bnxt_schedule_ptp_alarm(struct bnxt *bp)
1409 {
1410         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
1411         int rc;
1412
1413         if (bp->flags2 & BNXT_FLAGS2_PTP_ALARM_SCHEDULED)
1414                 return 0;
1415
1416         bnxt_hwrm_port_ts_query(bp, BNXT_PTP_FLAGS_CURRENT_TIME,
1417                                 &ptp->current_time);
1418
1419         rc = rte_eal_alarm_set(US_PER_S, bnxt_ptp_get_current_time, (void *)bp);
1420         return rc;
1421 }
1422
1423 static void bnxt_cancel_ptp_alarm(struct bnxt *bp)
1424 {
1425         if (bp->flags2 & BNXT_FLAGS2_PTP_ALARM_SCHEDULED) {
1426                 rte_eal_alarm_cancel(bnxt_ptp_get_current_time, (void *)bp);
1427                 bp->flags2 &= ~BNXT_FLAGS2_PTP_ALARM_SCHEDULED;
1428         }
1429 }
1430
1431 static void bnxt_ptp_stop(struct bnxt *bp)
1432 {
1433         bnxt_cancel_ptp_alarm(bp);
1434         bp->flags2 &= ~BNXT_FLAGS2_PTP_TIMESYNC_ENABLED;
1435 }
1436
1437 static int bnxt_ptp_start(struct bnxt *bp)
1438 {
1439         int rc;
1440
1441         rc = bnxt_schedule_ptp_alarm(bp);
1442         if (rc != 0) {
1443                 PMD_DRV_LOG(ERR, "Failed to schedule PTP alarm\n");
1444         } else {
1445                 bp->flags2 |= BNXT_FLAGS2_PTP_TIMESYNC_ENABLED;
1446                 bp->flags2 |= BNXT_FLAGS2_PTP_ALARM_SCHEDULED;
1447         }
1448
1449         return rc;
1450 }
1451
1452 static int bnxt_dev_stop(struct rte_eth_dev *eth_dev)
1453 {
1454         struct bnxt *bp = eth_dev->data->dev_private;
1455         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1456         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1457         struct rte_eth_link link;
1458         int ret;
1459
1460         eth_dev->data->dev_started = 0;
1461         eth_dev->data->scattered_rx = 0;
1462
1463         /* Prevent crashes when queues are still in use */
1464         eth_dev->rx_pkt_burst = &bnxt_dummy_recv_pkts;
1465         eth_dev->tx_pkt_burst = &bnxt_dummy_xmit_pkts;
1466
1467         bnxt_disable_int(bp);
1468
1469         /* disable uio/vfio intr/eventfd mapping */
1470         rte_intr_disable(intr_handle);
1471
1472         /* Stop the child representors for this device */
1473         ret = bnxt_rep_stop_all(bp);
1474         if (ret != 0)
1475                 return ret;
1476
1477         /* delete the bnxt ULP port details */
1478         bnxt_ulp_port_deinit(bp);
1479
1480         bnxt_cancel_fw_health_check(bp);
1481
1482         if (BNXT_P5_PTP_TIMESYNC_ENABLED(bp))
1483                 bnxt_cancel_ptp_alarm(bp);
1484
1485         /* Do not bring link down during reset recovery */
1486         if (!is_bnxt_in_error(bp)) {
1487                 bnxt_dev_set_link_down_op(eth_dev);
1488                 /* Wait for link to be reset */
1489                 if (BNXT_SINGLE_PF(bp))
1490                         rte_delay_ms(500);
1491                 /* clear the recorded link status */
1492                 memset(&link, 0, sizeof(link));
1493                 rte_eth_linkstatus_set(eth_dev, &link);
1494         }
1495
1496         /* Clean queue intr-vector mapping */
1497         rte_intr_efd_disable(intr_handle);
1498         if (intr_handle->intr_vec != NULL) {
1499                 rte_free(intr_handle->intr_vec);
1500                 intr_handle->intr_vec = NULL;
1501         }
1502
1503         bnxt_hwrm_port_clr_stats(bp);
1504         bnxt_free_tx_mbufs(bp);
1505         bnxt_free_rx_mbufs(bp);
1506         /* Process any remaining notifications in default completion queue */
1507         bnxt_int_handler(eth_dev);
1508         bnxt_shutdown_nic(bp);
1509         bnxt_hwrm_if_change(bp, false);
1510
1511         bnxt_free_prev_ring_stats(bp);
1512         rte_free(bp->mark_table);
1513         bp->mark_table = NULL;
1514
1515         bp->flags &= ~BNXT_FLAG_RX_VECTOR_PKT_MODE;
1516         bp->rx_cosq_cnt = 0;
1517         /* All filters are deleted on a port stop. */
1518         if (BNXT_FLOW_XSTATS_EN(bp))
1519                 bp->flow_stat->flow_count = 0;
1520
1521         return 0;
1522 }
1523
1524 /* Unload the driver, release resources */
1525 static int bnxt_dev_stop_op(struct rte_eth_dev *eth_dev)
1526 {
1527         struct bnxt *bp = eth_dev->data->dev_private;
1528
1529         pthread_mutex_lock(&bp->err_recovery_lock);
1530         if (bp->flags & BNXT_FLAG_FW_RESET) {
1531                 PMD_DRV_LOG(ERR,
1532                             "Adapter recovering from error..Please retry\n");
1533                 pthread_mutex_unlock(&bp->err_recovery_lock);
1534                 return -EAGAIN;
1535         }
1536         pthread_mutex_unlock(&bp->err_recovery_lock);
1537
1538         return bnxt_dev_stop(eth_dev);
1539 }
1540
1541 static int bnxt_dev_start_op(struct rte_eth_dev *eth_dev)
1542 {
1543         struct bnxt *bp = eth_dev->data->dev_private;
1544         uint64_t rx_offloads = eth_dev->data->dev_conf.rxmode.offloads;
1545         int vlan_mask = 0;
1546         int rc, retry_cnt = BNXT_IF_CHANGE_RETRY_COUNT;
1547
1548         if (!eth_dev->data->nb_tx_queues || !eth_dev->data->nb_rx_queues) {
1549                 PMD_DRV_LOG(ERR, "Queues are not configured yet!\n");
1550                 return -EINVAL;
1551         }
1552
1553         if (bp->rx_cp_nr_rings > RTE_ETHDEV_QUEUE_STAT_CNTRS)
1554                 PMD_DRV_LOG(ERR,
1555                             "RxQ cnt %d > RTE_ETHDEV_QUEUE_STAT_CNTRS %d\n",
1556                             bp->rx_cp_nr_rings, RTE_ETHDEV_QUEUE_STAT_CNTRS);
1557
1558         do {
1559                 rc = bnxt_hwrm_if_change(bp, true);
1560                 if (rc == 0 || rc != -EAGAIN)
1561                         break;
1562
1563                 rte_delay_ms(BNXT_IF_CHANGE_RETRY_INTERVAL);
1564         } while (retry_cnt--);
1565
1566         if (rc)
1567                 return rc;
1568
1569         if (bp->flags & BNXT_FLAG_IF_CHANGE_HOT_FW_RESET_DONE) {
1570                 rc = bnxt_handle_if_change_status(bp);
1571                 if (rc)
1572                         return rc;
1573         }
1574
1575         bnxt_enable_int(bp);
1576
1577         eth_dev->data->scattered_rx = bnxt_scattered_rx(eth_dev);
1578
1579         rc = bnxt_start_nic(bp);
1580         if (rc)
1581                 goto error;
1582
1583         rc = bnxt_alloc_prev_ring_stats(bp);
1584         if (rc)
1585                 goto error;
1586
1587         eth_dev->data->dev_started = 1;
1588
1589         bnxt_link_update_op(eth_dev, 1);
1590
1591         if (rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER)
1592                 vlan_mask |= ETH_VLAN_FILTER_MASK;
1593         if (rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
1594                 vlan_mask |= ETH_VLAN_STRIP_MASK;
1595         rc = bnxt_vlan_offload_set_op(eth_dev, vlan_mask);
1596         if (rc)
1597                 goto error;
1598
1599         /* Initialize bnxt ULP port details */
1600         rc = bnxt_ulp_port_init(bp);
1601         if (rc)
1602                 goto error;
1603
1604         eth_dev->rx_pkt_burst = bnxt_receive_function(eth_dev);
1605         eth_dev->tx_pkt_burst = bnxt_transmit_function(eth_dev);
1606
1607         bnxt_schedule_fw_health_check(bp);
1608
1609         if (BNXT_P5_PTP_TIMESYNC_ENABLED(bp))
1610                 bnxt_schedule_ptp_alarm(bp);
1611
1612         return 0;
1613
1614 error:
1615         bnxt_dev_stop(eth_dev);
1616         return rc;
1617 }
1618
1619 static void
1620 bnxt_uninit_locks(struct bnxt *bp)
1621 {
1622         pthread_mutex_destroy(&bp->flow_lock);
1623         pthread_mutex_destroy(&bp->def_cp_lock);
1624         pthread_mutex_destroy(&bp->health_check_lock);
1625         pthread_mutex_destroy(&bp->err_recovery_lock);
1626         if (bp->rep_info) {
1627                 pthread_mutex_destroy(&bp->rep_info->vfr_lock);
1628                 pthread_mutex_destroy(&bp->rep_info->vfr_start_lock);
1629         }
1630 }
1631
1632 static void bnxt_drv_uninit(struct bnxt *bp)
1633 {
1634         bnxt_free_leds_info(bp);
1635         bnxt_free_cos_queues(bp);
1636         bnxt_free_link_info(bp);
1637         bnxt_free_parent_info(bp);
1638         bnxt_uninit_locks(bp);
1639
1640         rte_memzone_free((const struct rte_memzone *)bp->tx_mem_zone);
1641         bp->tx_mem_zone = NULL;
1642         rte_memzone_free((const struct rte_memzone *)bp->rx_mem_zone);
1643         bp->rx_mem_zone = NULL;
1644
1645         bnxt_free_vf_info(bp);
1646         bnxt_free_pf_info(bp);
1647
1648         rte_free(bp->grp_info);
1649         bp->grp_info = NULL;
1650 }
1651
1652 static int bnxt_dev_close_op(struct rte_eth_dev *eth_dev)
1653 {
1654         struct bnxt *bp = eth_dev->data->dev_private;
1655         int ret = 0;
1656
1657         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1658                 return 0;
1659
1660         pthread_mutex_lock(&bp->err_recovery_lock);
1661         if (bp->flags & BNXT_FLAG_FW_RESET) {
1662                 PMD_DRV_LOG(ERR,
1663                             "Adapter recovering from error...Please retry\n");
1664                 pthread_mutex_unlock(&bp->err_recovery_lock);
1665                 return -EAGAIN;
1666         }
1667         pthread_mutex_unlock(&bp->err_recovery_lock);
1668
1669         /* cancel the recovery handler before remove dev */
1670         rte_eal_alarm_cancel(bnxt_dev_reset_and_resume, (void *)bp);
1671         rte_eal_alarm_cancel(bnxt_dev_recover, (void *)bp);
1672         bnxt_cancel_fc_thread(bp);
1673
1674         if (eth_dev->data->dev_started)
1675                 ret = bnxt_dev_stop(eth_dev);
1676
1677         bnxt_uninit_resources(bp, false);
1678
1679         bnxt_drv_uninit(bp);
1680
1681         return ret;
1682 }
1683
1684 static void bnxt_mac_addr_remove_op(struct rte_eth_dev *eth_dev,
1685                                     uint32_t index)
1686 {
1687         struct bnxt *bp = eth_dev->data->dev_private;
1688         uint64_t pool_mask = eth_dev->data->mac_pool_sel[index];
1689         struct bnxt_vnic_info *vnic;
1690         struct bnxt_filter_info *filter, *temp_filter;
1691         uint32_t i;
1692
1693         if (is_bnxt_in_error(bp))
1694                 return;
1695
1696         /*
1697          * Loop through all VNICs from the specified filter flow pools to
1698          * remove the corresponding MAC addr filter
1699          */
1700         for (i = 0; i < bp->nr_vnics; i++) {
1701                 if (!(pool_mask & (1ULL << i)))
1702                         continue;
1703
1704                 vnic = &bp->vnic_info[i];
1705                 filter = STAILQ_FIRST(&vnic->filter);
1706                 while (filter) {
1707                         temp_filter = STAILQ_NEXT(filter, next);
1708                         if (filter->mac_index == index) {
1709                                 STAILQ_REMOVE(&vnic->filter, filter,
1710                                                 bnxt_filter_info, next);
1711                                 bnxt_hwrm_clear_l2_filter(bp, filter);
1712                                 bnxt_free_filter(bp, filter);
1713                         }
1714                         filter = temp_filter;
1715                 }
1716         }
1717 }
1718
1719 static int bnxt_add_mac_filter(struct bnxt *bp, struct bnxt_vnic_info *vnic,
1720                                struct rte_ether_addr *mac_addr, uint32_t index,
1721                                uint32_t pool)
1722 {
1723         struct bnxt_filter_info *filter;
1724         int rc = 0;
1725
1726         /* Attach requested MAC address to the new l2_filter */
1727         STAILQ_FOREACH(filter, &vnic->filter, next) {
1728                 if (filter->mac_index == index) {
1729                         PMD_DRV_LOG(DEBUG,
1730                                     "MAC addr already existed for pool %d\n",
1731                                     pool);
1732                         return 0;
1733                 }
1734         }
1735
1736         filter = bnxt_alloc_filter(bp);
1737         if (!filter) {
1738                 PMD_DRV_LOG(ERR, "L2 filter alloc failed\n");
1739                 return -ENODEV;
1740         }
1741
1742         /* bnxt_alloc_filter copies default MAC to filter->l2_addr. So,
1743          * if the MAC that's been programmed now is a different one, then,
1744          * copy that addr to filter->l2_addr
1745          */
1746         if (mac_addr)
1747                 memcpy(filter->l2_addr, mac_addr, RTE_ETHER_ADDR_LEN);
1748         filter->flags |= HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_OUTERMOST;
1749
1750         rc = bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id, filter);
1751         if (!rc) {
1752                 filter->mac_index = index;
1753                 if (filter->mac_index == 0)
1754                         STAILQ_INSERT_HEAD(&vnic->filter, filter, next);
1755                 else
1756                         STAILQ_INSERT_TAIL(&vnic->filter, filter, next);
1757         } else {
1758                 bnxt_free_filter(bp, filter);
1759         }
1760
1761         return rc;
1762 }
1763
1764 static int bnxt_mac_addr_add_op(struct rte_eth_dev *eth_dev,
1765                                 struct rte_ether_addr *mac_addr,
1766                                 uint32_t index, uint32_t pool)
1767 {
1768         struct bnxt *bp = eth_dev->data->dev_private;
1769         struct bnxt_vnic_info *vnic = &bp->vnic_info[pool];
1770         int rc = 0;
1771
1772         rc = is_bnxt_in_error(bp);
1773         if (rc)
1774                 return rc;
1775
1776         if (BNXT_VF(bp) && !BNXT_VF_IS_TRUSTED(bp)) {
1777                 PMD_DRV_LOG(ERR, "Cannot add MAC address to a VF interface\n");
1778                 return -ENOTSUP;
1779         }
1780
1781         if (!vnic) {
1782                 PMD_DRV_LOG(ERR, "VNIC not found for pool %d!\n", pool);
1783                 return -EINVAL;
1784         }
1785
1786         /* Filter settings will get applied when port is started */
1787         if (!eth_dev->data->dev_started)
1788                 return 0;
1789
1790         rc = bnxt_add_mac_filter(bp, vnic, mac_addr, index, pool);
1791
1792         return rc;
1793 }
1794
1795 int bnxt_link_update_op(struct rte_eth_dev *eth_dev, int wait_to_complete)
1796 {
1797         int rc = 0;
1798         struct bnxt *bp = eth_dev->data->dev_private;
1799         struct rte_eth_link new;
1800         int cnt = wait_to_complete ? BNXT_MAX_LINK_WAIT_CNT :
1801                         BNXT_MIN_LINK_WAIT_CNT;
1802
1803         rc = is_bnxt_in_error(bp);
1804         if (rc)
1805                 return rc;
1806
1807         memset(&new, 0, sizeof(new));
1808
1809         if (bp->link_info == NULL)
1810                 goto out;
1811
1812         do {
1813                 /* Retrieve link info from hardware */
1814                 rc = bnxt_get_hwrm_link_config(bp, &new);
1815                 if (rc) {
1816                         new.link_speed = ETH_LINK_SPEED_100M;
1817                         new.link_duplex = ETH_LINK_FULL_DUPLEX;
1818                         PMD_DRV_LOG(ERR,
1819                                 "Failed to retrieve link rc = 0x%x!\n", rc);
1820                         goto out;
1821                 }
1822
1823                 if (!wait_to_complete || new.link_status)
1824                         break;
1825
1826                 rte_delay_ms(BNXT_LINK_WAIT_INTERVAL);
1827         } while (cnt--);
1828
1829         /* Only single function PF can bring phy down.
1830          * When port is stopped, report link down for VF/MH/NPAR functions.
1831          */
1832         if (!BNXT_SINGLE_PF(bp) && !eth_dev->data->dev_started)
1833                 memset(&new, 0, sizeof(new));
1834
1835 out:
1836         /* Timed out or success */
1837         if (new.link_status != eth_dev->data->dev_link.link_status ||
1838             new.link_speed != eth_dev->data->dev_link.link_speed) {
1839                 rte_eth_linkstatus_set(eth_dev, &new);
1840
1841                 rte_eth_dev_callback_process(eth_dev,
1842                                              RTE_ETH_EVENT_INTR_LSC,
1843                                              NULL);
1844
1845                 bnxt_print_link_info(eth_dev);
1846         }
1847
1848         return rc;
1849 }
1850
1851 static int bnxt_promiscuous_enable_op(struct rte_eth_dev *eth_dev)
1852 {
1853         struct bnxt *bp = eth_dev->data->dev_private;
1854         struct bnxt_vnic_info *vnic;
1855         uint32_t old_flags;
1856         int rc;
1857
1858         rc = is_bnxt_in_error(bp);
1859         if (rc)
1860                 return rc;
1861
1862         /* Filter settings will get applied when port is started */
1863         if (!eth_dev->data->dev_started)
1864                 return 0;
1865
1866         if (bp->vnic_info == NULL)
1867                 return 0;
1868
1869         vnic = BNXT_GET_DEFAULT_VNIC(bp);
1870
1871         old_flags = vnic->flags;
1872         vnic->flags |= BNXT_VNIC_INFO_PROMISC;
1873         rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1874         if (rc != 0)
1875                 vnic->flags = old_flags;
1876
1877         return rc;
1878 }
1879
1880 static int bnxt_promiscuous_disable_op(struct rte_eth_dev *eth_dev)
1881 {
1882         struct bnxt *bp = eth_dev->data->dev_private;
1883         struct bnxt_vnic_info *vnic;
1884         uint32_t old_flags;
1885         int rc;
1886
1887         rc = is_bnxt_in_error(bp);
1888         if (rc)
1889                 return rc;
1890
1891         /* Filter settings will get applied when port is started */
1892         if (!eth_dev->data->dev_started)
1893                 return 0;
1894
1895         if (bp->vnic_info == NULL)
1896                 return 0;
1897
1898         vnic = BNXT_GET_DEFAULT_VNIC(bp);
1899
1900         old_flags = vnic->flags;
1901         vnic->flags &= ~BNXT_VNIC_INFO_PROMISC;
1902         rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1903         if (rc != 0)
1904                 vnic->flags = old_flags;
1905
1906         return rc;
1907 }
1908
1909 static int bnxt_allmulticast_enable_op(struct rte_eth_dev *eth_dev)
1910 {
1911         struct bnxt *bp = eth_dev->data->dev_private;
1912         struct bnxt_vnic_info *vnic;
1913         uint32_t old_flags;
1914         int rc;
1915
1916         rc = is_bnxt_in_error(bp);
1917         if (rc)
1918                 return rc;
1919
1920         /* Filter settings will get applied when port is started */
1921         if (!eth_dev->data->dev_started)
1922                 return 0;
1923
1924         if (bp->vnic_info == NULL)
1925                 return 0;
1926
1927         vnic = BNXT_GET_DEFAULT_VNIC(bp);
1928
1929         old_flags = vnic->flags;
1930         vnic->flags |= BNXT_VNIC_INFO_ALLMULTI;
1931         rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1932         if (rc != 0)
1933                 vnic->flags = old_flags;
1934
1935         return rc;
1936 }
1937
1938 static int bnxt_allmulticast_disable_op(struct rte_eth_dev *eth_dev)
1939 {
1940         struct bnxt *bp = eth_dev->data->dev_private;
1941         struct bnxt_vnic_info *vnic;
1942         uint32_t old_flags;
1943         int rc;
1944
1945         rc = is_bnxt_in_error(bp);
1946         if (rc)
1947                 return rc;
1948
1949         /* Filter settings will get applied when port is started */
1950         if (!eth_dev->data->dev_started)
1951                 return 0;
1952
1953         if (bp->vnic_info == NULL)
1954                 return 0;
1955
1956         vnic = BNXT_GET_DEFAULT_VNIC(bp);
1957
1958         old_flags = vnic->flags;
1959         vnic->flags &= ~BNXT_VNIC_INFO_ALLMULTI;
1960         rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1961         if (rc != 0)
1962                 vnic->flags = old_flags;
1963
1964         return rc;
1965 }
1966
1967 /* Return bnxt_rx_queue pointer corresponding to a given rxq. */
1968 static struct bnxt_rx_queue *bnxt_qid_to_rxq(struct bnxt *bp, uint16_t qid)
1969 {
1970         if (qid >= bp->rx_nr_rings)
1971                 return NULL;
1972
1973         return bp->eth_dev->data->rx_queues[qid];
1974 }
1975
1976 /* Return rxq corresponding to a given rss table ring/group ID. */
1977 static uint16_t bnxt_rss_to_qid(struct bnxt *bp, uint16_t fwr)
1978 {
1979         struct bnxt_rx_queue *rxq;
1980         unsigned int i;
1981
1982         if (!BNXT_HAS_RING_GRPS(bp)) {
1983                 for (i = 0; i < bp->rx_nr_rings; i++) {
1984                         rxq = bp->eth_dev->data->rx_queues[i];
1985                         if (rxq->rx_ring->rx_ring_struct->fw_ring_id == fwr)
1986                                 return rxq->index;
1987                 }
1988         } else {
1989                 for (i = 0; i < bp->rx_nr_rings; i++) {
1990                         if (bp->grp_info[i].fw_grp_id == fwr)
1991                                 return i;
1992                 }
1993         }
1994
1995         return INVALID_HW_RING_ID;
1996 }
1997
1998 static int bnxt_reta_update_op(struct rte_eth_dev *eth_dev,
1999                             struct rte_eth_rss_reta_entry64 *reta_conf,
2000                             uint16_t reta_size)
2001 {
2002         struct bnxt *bp = eth_dev->data->dev_private;
2003         struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
2004         struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp);
2005         uint16_t tbl_size = bnxt_rss_hash_tbl_size(bp);
2006         uint16_t idx, sft;
2007         int i, rc;
2008
2009         rc = is_bnxt_in_error(bp);
2010         if (rc)
2011                 return rc;
2012
2013         if (!vnic->rss_table)
2014                 return -EINVAL;
2015
2016         if (!(dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG))
2017                 return -EINVAL;
2018
2019         if (reta_size != tbl_size) {
2020                 PMD_DRV_LOG(ERR, "The configured hash table lookup size "
2021                         "(%d) must equal the size supported by the hardware "
2022                         "(%d)\n", reta_size, tbl_size);
2023                 return -EINVAL;
2024         }
2025
2026         for (i = 0; i < reta_size; i++) {
2027                 struct bnxt_rx_queue *rxq;
2028
2029                 idx = i / RTE_RETA_GROUP_SIZE;
2030                 sft = i % RTE_RETA_GROUP_SIZE;
2031
2032                 if (!(reta_conf[idx].mask & (1ULL << sft)))
2033                         continue;
2034
2035                 rxq = bnxt_qid_to_rxq(bp, reta_conf[idx].reta[sft]);
2036                 if (!rxq) {
2037                         PMD_DRV_LOG(ERR, "Invalid ring in reta_conf.\n");
2038                         return -EINVAL;
2039                 }
2040
2041                 if (BNXT_CHIP_P5(bp)) {
2042                         vnic->rss_table[i * 2] =
2043                                 rxq->rx_ring->rx_ring_struct->fw_ring_id;
2044                         vnic->rss_table[i * 2 + 1] =
2045                                 rxq->cp_ring->cp_ring_struct->fw_ring_id;
2046                 } else {
2047                         vnic->rss_table[i] =
2048                             vnic->fw_grp_ids[reta_conf[idx].reta[sft]];
2049                 }
2050         }
2051
2052         rc = bnxt_hwrm_vnic_rss_cfg(bp, vnic);
2053         return rc;
2054 }
2055
2056 static int bnxt_reta_query_op(struct rte_eth_dev *eth_dev,
2057                               struct rte_eth_rss_reta_entry64 *reta_conf,
2058                               uint16_t reta_size)
2059 {
2060         struct bnxt *bp = eth_dev->data->dev_private;
2061         struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp);
2062         uint16_t tbl_size = bnxt_rss_hash_tbl_size(bp);
2063         uint16_t idx, sft, i;
2064         int rc;
2065
2066         rc = is_bnxt_in_error(bp);
2067         if (rc)
2068                 return rc;
2069
2070         /* Retrieve from the default VNIC */
2071         if (!vnic)
2072                 return -EINVAL;
2073         if (!vnic->rss_table)
2074                 return -EINVAL;
2075
2076         if (reta_size != tbl_size) {
2077                 PMD_DRV_LOG(ERR, "The configured hash table lookup size "
2078                         "(%d) must equal the size supported by the hardware "
2079                         "(%d)\n", reta_size, tbl_size);
2080                 return -EINVAL;
2081         }
2082
2083         for (idx = 0, i = 0; i < reta_size; i++) {
2084                 idx = i / RTE_RETA_GROUP_SIZE;
2085                 sft = i % RTE_RETA_GROUP_SIZE;
2086
2087                 if (reta_conf[idx].mask & (1ULL << sft)) {
2088                         uint16_t qid;
2089
2090                         if (BNXT_CHIP_P5(bp))
2091                                 qid = bnxt_rss_to_qid(bp,
2092                                                       vnic->rss_table[i * 2]);
2093                         else
2094                                 qid = bnxt_rss_to_qid(bp, vnic->rss_table[i]);
2095
2096                         if (qid == INVALID_HW_RING_ID) {
2097                                 PMD_DRV_LOG(ERR, "Inv. entry in rss table.\n");
2098                                 return -EINVAL;
2099                         }
2100                         reta_conf[idx].reta[sft] = qid;
2101                 }
2102         }
2103
2104         return 0;
2105 }
2106
2107 static int bnxt_rss_hash_update_op(struct rte_eth_dev *eth_dev,
2108                                    struct rte_eth_rss_conf *rss_conf)
2109 {
2110         struct bnxt *bp = eth_dev->data->dev_private;
2111         struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
2112         struct bnxt_vnic_info *vnic;
2113         int rc;
2114
2115         rc = is_bnxt_in_error(bp);
2116         if (rc)
2117                 return rc;
2118
2119         /*
2120          * If RSS enablement were different than dev_configure,
2121          * then return -EINVAL
2122          */
2123         if (dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG) {
2124                 if (!rss_conf->rss_hf)
2125                         PMD_DRV_LOG(ERR, "Hash type NONE\n");
2126         } else {
2127                 if (rss_conf->rss_hf & BNXT_ETH_RSS_SUPPORT)
2128                         return -EINVAL;
2129         }
2130
2131         bp->flags |= BNXT_FLAG_UPDATE_HASH;
2132         memcpy(&eth_dev->data->dev_conf.rx_adv_conf.rss_conf,
2133                rss_conf,
2134                sizeof(*rss_conf));
2135
2136         /* Update the default RSS VNIC(s) */
2137         vnic = BNXT_GET_DEFAULT_VNIC(bp);
2138         vnic->hash_type = bnxt_rte_to_hwrm_hash_types(rss_conf->rss_hf);
2139         vnic->hash_mode =
2140                 bnxt_rte_to_hwrm_hash_level(bp, rss_conf->rss_hf,
2141                                             ETH_RSS_LEVEL(rss_conf->rss_hf));
2142
2143         /*
2144          * If hashkey is not specified, use the previously configured
2145          * hashkey
2146          */
2147         if (!rss_conf->rss_key)
2148                 goto rss_config;
2149
2150         if (rss_conf->rss_key_len != HW_HASH_KEY_SIZE) {
2151                 PMD_DRV_LOG(ERR,
2152                             "Invalid hashkey length, should be 16 bytes\n");
2153                 return -EINVAL;
2154         }
2155         memcpy(vnic->rss_hash_key, rss_conf->rss_key, rss_conf->rss_key_len);
2156
2157 rss_config:
2158         rc = bnxt_hwrm_vnic_rss_cfg(bp, vnic);
2159         return rc;
2160 }
2161
2162 static int bnxt_rss_hash_conf_get_op(struct rte_eth_dev *eth_dev,
2163                                      struct rte_eth_rss_conf *rss_conf)
2164 {
2165         struct bnxt *bp = eth_dev->data->dev_private;
2166         struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp);
2167         int len, rc;
2168         uint32_t hash_types;
2169
2170         rc = is_bnxt_in_error(bp);
2171         if (rc)
2172                 return rc;
2173
2174         /* RSS configuration is the same for all VNICs */
2175         if (vnic && vnic->rss_hash_key) {
2176                 if (rss_conf->rss_key) {
2177                         len = rss_conf->rss_key_len <= HW_HASH_KEY_SIZE ?
2178                               rss_conf->rss_key_len : HW_HASH_KEY_SIZE;
2179                         memcpy(rss_conf->rss_key, vnic->rss_hash_key, len);
2180                 }
2181
2182                 hash_types = vnic->hash_type;
2183                 rss_conf->rss_hf = 0;
2184                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV4) {
2185                         rss_conf->rss_hf |= ETH_RSS_IPV4;
2186                         hash_types &= ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV4;
2187                 }
2188                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV4) {
2189                         rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP;
2190                         hash_types &=
2191                                 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV4;
2192                 }
2193                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV4) {
2194                         rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
2195                         hash_types &=
2196                                 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV4;
2197                 }
2198                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6) {
2199                         rss_conf->rss_hf |= ETH_RSS_IPV6;
2200                         hash_types &= ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6;
2201                 }
2202                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV6) {
2203                         rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV6_TCP;
2204                         hash_types &=
2205                                 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV6;
2206                 }
2207                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV6) {
2208                         rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;
2209                         hash_types &=
2210                                 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV6;
2211                 }
2212
2213                 rss_conf->rss_hf |=
2214                         bnxt_hwrm_to_rte_rss_level(bp, vnic->hash_mode);
2215
2216                 if (hash_types) {
2217                         PMD_DRV_LOG(ERR,
2218                                 "Unknown RSS config from firmware (%08x), RSS disabled",
2219                                 vnic->hash_type);
2220                         return -ENOTSUP;
2221                 }
2222         } else {
2223                 rss_conf->rss_hf = 0;
2224         }
2225         return 0;
2226 }
2227
2228 static int bnxt_flow_ctrl_get_op(struct rte_eth_dev *dev,
2229                                struct rte_eth_fc_conf *fc_conf)
2230 {
2231         struct bnxt *bp = dev->data->dev_private;
2232         struct rte_eth_link link_info;
2233         int rc;
2234
2235         rc = is_bnxt_in_error(bp);
2236         if (rc)
2237                 return rc;
2238
2239         rc = bnxt_get_hwrm_link_config(bp, &link_info);
2240         if (rc)
2241                 return rc;
2242
2243         memset(fc_conf, 0, sizeof(*fc_conf));
2244         if (bp->link_info->auto_pause)
2245                 fc_conf->autoneg = 1;
2246         switch (bp->link_info->pause) {
2247         case 0:
2248                 fc_conf->mode = RTE_FC_NONE;
2249                 break;
2250         case HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_TX:
2251                 fc_conf->mode = RTE_FC_TX_PAUSE;
2252                 break;
2253         case HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_RX:
2254                 fc_conf->mode = RTE_FC_RX_PAUSE;
2255                 break;
2256         case (HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_TX |
2257                         HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_RX):
2258                 fc_conf->mode = RTE_FC_FULL;
2259                 break;
2260         }
2261         return 0;
2262 }
2263
2264 static int bnxt_flow_ctrl_set_op(struct rte_eth_dev *dev,
2265                                struct rte_eth_fc_conf *fc_conf)
2266 {
2267         struct bnxt *bp = dev->data->dev_private;
2268         int rc;
2269
2270         rc = is_bnxt_in_error(bp);
2271         if (rc)
2272                 return rc;
2273
2274         if (!BNXT_SINGLE_PF(bp)) {
2275                 PMD_DRV_LOG(ERR,
2276                             "Flow Control Settings cannot be modified on VF or on shared PF\n");
2277                 return -ENOTSUP;
2278         }
2279
2280         switch (fc_conf->mode) {
2281         case RTE_FC_NONE:
2282                 bp->link_info->auto_pause = 0;
2283                 bp->link_info->force_pause = 0;
2284                 break;
2285         case RTE_FC_RX_PAUSE:
2286                 if (fc_conf->autoneg) {
2287                         bp->link_info->auto_pause =
2288                                         HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_RX;
2289                         bp->link_info->force_pause = 0;
2290                 } else {
2291                         bp->link_info->auto_pause = 0;
2292                         bp->link_info->force_pause =
2293                                         HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_RX;
2294                 }
2295                 break;
2296         case RTE_FC_TX_PAUSE:
2297                 if (fc_conf->autoneg) {
2298                         bp->link_info->auto_pause =
2299                                         HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_TX;
2300                         bp->link_info->force_pause = 0;
2301                 } else {
2302                         bp->link_info->auto_pause = 0;
2303                         bp->link_info->force_pause =
2304                                         HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_TX;
2305                 }
2306                 break;
2307         case RTE_FC_FULL:
2308                 if (fc_conf->autoneg) {
2309                         bp->link_info->auto_pause =
2310                                         HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_TX |
2311                                         HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_RX;
2312                         bp->link_info->force_pause = 0;
2313                 } else {
2314                         bp->link_info->auto_pause = 0;
2315                         bp->link_info->force_pause =
2316                                         HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_TX |
2317                                         HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_RX;
2318                 }
2319                 break;
2320         }
2321         return bnxt_set_hwrm_link_config(bp, true);
2322 }
2323
2324 /* Add UDP tunneling port */
2325 static int
2326 bnxt_udp_tunnel_port_add_op(struct rte_eth_dev *eth_dev,
2327                          struct rte_eth_udp_tunnel *udp_tunnel)
2328 {
2329         struct bnxt *bp = eth_dev->data->dev_private;
2330         uint16_t tunnel_type = 0;
2331         int rc = 0;
2332
2333         rc = is_bnxt_in_error(bp);
2334         if (rc)
2335                 return rc;
2336
2337         switch (udp_tunnel->prot_type) {
2338         case RTE_TUNNEL_TYPE_VXLAN:
2339                 if (bp->vxlan_port_cnt) {
2340                         PMD_DRV_LOG(ERR, "Tunnel Port %d already programmed\n",
2341                                 udp_tunnel->udp_port);
2342                         if (bp->vxlan_port != udp_tunnel->udp_port) {
2343                                 PMD_DRV_LOG(ERR, "Only one port allowed\n");
2344                                 return -ENOSPC;
2345                         }
2346                         bp->vxlan_port_cnt++;
2347                         return 0;
2348                 }
2349                 tunnel_type =
2350                         HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_VXLAN;
2351                 bp->vxlan_port_cnt++;
2352                 break;
2353         case RTE_TUNNEL_TYPE_GENEVE:
2354                 if (bp->geneve_port_cnt) {
2355                         PMD_DRV_LOG(ERR, "Tunnel Port %d already programmed\n",
2356                                 udp_tunnel->udp_port);
2357                         if (bp->geneve_port != udp_tunnel->udp_port) {
2358                                 PMD_DRV_LOG(ERR, "Only one port allowed\n");
2359                                 return -ENOSPC;
2360                         }
2361                         bp->geneve_port_cnt++;
2362                         return 0;
2363                 }
2364                 tunnel_type =
2365                         HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_GENEVE;
2366                 bp->geneve_port_cnt++;
2367                 break;
2368         default:
2369                 PMD_DRV_LOG(ERR, "Tunnel type is not supported\n");
2370                 return -ENOTSUP;
2371         }
2372         rc = bnxt_hwrm_tunnel_dst_port_alloc(bp, udp_tunnel->udp_port,
2373                                              tunnel_type);
2374         return rc;
2375 }
2376
2377 static int
2378 bnxt_udp_tunnel_port_del_op(struct rte_eth_dev *eth_dev,
2379                          struct rte_eth_udp_tunnel *udp_tunnel)
2380 {
2381         struct bnxt *bp = eth_dev->data->dev_private;
2382         uint16_t tunnel_type = 0;
2383         uint16_t port = 0;
2384         int rc = 0;
2385
2386         rc = is_bnxt_in_error(bp);
2387         if (rc)
2388                 return rc;
2389
2390         switch (udp_tunnel->prot_type) {
2391         case RTE_TUNNEL_TYPE_VXLAN:
2392                 if (!bp->vxlan_port_cnt) {
2393                         PMD_DRV_LOG(ERR, "No Tunnel port configured yet\n");
2394                         return -EINVAL;
2395                 }
2396                 if (bp->vxlan_port != udp_tunnel->udp_port) {
2397                         PMD_DRV_LOG(ERR, "Req Port: %d. Configured port: %d\n",
2398                                 udp_tunnel->udp_port, bp->vxlan_port);
2399                         return -EINVAL;
2400                 }
2401                 if (--bp->vxlan_port_cnt)
2402                         return 0;
2403
2404                 tunnel_type =
2405                         HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN;
2406                 port = bp->vxlan_fw_dst_port_id;
2407                 break;
2408         case RTE_TUNNEL_TYPE_GENEVE:
2409                 if (!bp->geneve_port_cnt) {
2410                         PMD_DRV_LOG(ERR, "No Tunnel port configured yet\n");
2411                         return -EINVAL;
2412                 }
2413                 if (bp->geneve_port != udp_tunnel->udp_port) {
2414                         PMD_DRV_LOG(ERR, "Req Port: %d. Configured port: %d\n",
2415                                 udp_tunnel->udp_port, bp->geneve_port);
2416                         return -EINVAL;
2417                 }
2418                 if (--bp->geneve_port_cnt)
2419                         return 0;
2420
2421                 tunnel_type =
2422                         HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_GENEVE;
2423                 port = bp->geneve_fw_dst_port_id;
2424                 break;
2425         default:
2426                 PMD_DRV_LOG(ERR, "Tunnel type is not supported\n");
2427                 return -ENOTSUP;
2428         }
2429
2430         rc = bnxt_hwrm_tunnel_dst_port_free(bp, port, tunnel_type);
2431         return rc;
2432 }
2433
2434 static int bnxt_del_vlan_filter(struct bnxt *bp, uint16_t vlan_id)
2435 {
2436         struct bnxt_filter_info *filter;
2437         struct bnxt_vnic_info *vnic;
2438         int rc = 0;
2439         uint32_t chk = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN;
2440
2441         vnic = BNXT_GET_DEFAULT_VNIC(bp);
2442         filter = STAILQ_FIRST(&vnic->filter);
2443         while (filter) {
2444                 /* Search for this matching MAC+VLAN filter */
2445                 if (bnxt_vlan_filter_exists(bp, filter, chk, vlan_id)) {
2446                         /* Delete the filter */
2447                         rc = bnxt_hwrm_clear_l2_filter(bp, filter);
2448                         if (rc)
2449                                 return rc;
2450                         STAILQ_REMOVE(&vnic->filter, filter,
2451                                       bnxt_filter_info, next);
2452                         bnxt_free_filter(bp, filter);
2453                         PMD_DRV_LOG(INFO,
2454                                     "Deleted vlan filter for %d\n",
2455                                     vlan_id);
2456                         return 0;
2457                 }
2458                 filter = STAILQ_NEXT(filter, next);
2459         }
2460         return -ENOENT;
2461 }
2462
2463 static int bnxt_add_vlan_filter(struct bnxt *bp, uint16_t vlan_id)
2464 {
2465         struct bnxt_filter_info *filter;
2466         struct bnxt_vnic_info *vnic;
2467         int rc = 0;
2468         uint32_t en = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN |
2469                 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN_MASK;
2470         uint32_t chk = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN;
2471
2472         /* Implementation notes on the use of VNIC in this command:
2473          *
2474          * By default, these filters belong to default vnic for the function.
2475          * Once these filters are set up, only destination VNIC can be modified.
2476          * If the destination VNIC is not specified in this command,
2477          * then the HWRM shall only create an l2 context id.
2478          */
2479
2480         vnic = BNXT_GET_DEFAULT_VNIC(bp);
2481         filter = STAILQ_FIRST(&vnic->filter);
2482         /* Check if the VLAN has already been added */
2483         while (filter) {
2484                 if (bnxt_vlan_filter_exists(bp, filter, chk, vlan_id))
2485                         return -EEXIST;
2486
2487                 filter = STAILQ_NEXT(filter, next);
2488         }
2489
2490         /* No match found. Alloc a fresh filter and issue the L2_FILTER_ALLOC
2491          * command to create MAC+VLAN filter with the right flags, enables set.
2492          */
2493         filter = bnxt_alloc_filter(bp);
2494         if (!filter) {
2495                 PMD_DRV_LOG(ERR,
2496                             "MAC/VLAN filter alloc failed\n");
2497                 return -ENOMEM;
2498         }
2499         /* MAC + VLAN ID filter */
2500         /* If l2_ivlan == 0 and l2_ivlan_mask != 0, only
2501          * untagged packets are received
2502          *
2503          * If l2_ivlan != 0 and l2_ivlan_mask != 0, untagged
2504          * packets and only the programmed vlan's packets are received
2505          */
2506         filter->l2_ivlan = vlan_id;
2507         filter->l2_ivlan_mask = 0x0FFF;
2508         filter->enables |= en;
2509         filter->flags |= HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_OUTERMOST;
2510
2511         rc = bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id, filter);
2512         if (rc) {
2513                 /* Free the newly allocated filter as we were
2514                  * not able to create the filter in hardware.
2515                  */
2516                 bnxt_free_filter(bp, filter);
2517                 return rc;
2518         }
2519
2520         filter->mac_index = 0;
2521         /* Add this new filter to the list */
2522         if (vlan_id == 0)
2523                 STAILQ_INSERT_HEAD(&vnic->filter, filter, next);
2524         else
2525                 STAILQ_INSERT_TAIL(&vnic->filter, filter, next);
2526
2527         PMD_DRV_LOG(INFO,
2528                     "Added Vlan filter for %d\n", vlan_id);
2529         return rc;
2530 }
2531
2532 static int bnxt_vlan_filter_set_op(struct rte_eth_dev *eth_dev,
2533                 uint16_t vlan_id, int on)
2534 {
2535         struct bnxt *bp = eth_dev->data->dev_private;
2536         int rc;
2537
2538         rc = is_bnxt_in_error(bp);
2539         if (rc)
2540                 return rc;
2541
2542         if (!eth_dev->data->dev_started) {
2543                 PMD_DRV_LOG(ERR, "port must be started before setting vlan\n");
2544                 return -EINVAL;
2545         }
2546
2547         /* These operations apply to ALL existing MAC/VLAN filters */
2548         if (on)
2549                 return bnxt_add_vlan_filter(bp, vlan_id);
2550         else
2551                 return bnxt_del_vlan_filter(bp, vlan_id);
2552 }
2553
2554 static int bnxt_del_dflt_mac_filter(struct bnxt *bp,
2555                                     struct bnxt_vnic_info *vnic)
2556 {
2557         struct bnxt_filter_info *filter;
2558         int rc;
2559
2560         filter = STAILQ_FIRST(&vnic->filter);
2561         while (filter) {
2562                 if (filter->mac_index == 0 &&
2563                     !memcmp(filter->l2_addr, bp->mac_addr,
2564                             RTE_ETHER_ADDR_LEN)) {
2565                         rc = bnxt_hwrm_clear_l2_filter(bp, filter);
2566                         if (!rc) {
2567                                 STAILQ_REMOVE(&vnic->filter, filter,
2568                                               bnxt_filter_info, next);
2569                                 bnxt_free_filter(bp, filter);
2570                         }
2571                         return rc;
2572                 }
2573                 filter = STAILQ_NEXT(filter, next);
2574         }
2575         return 0;
2576 }
2577
2578 static int
2579 bnxt_config_vlan_hw_filter(struct bnxt *bp, uint64_t rx_offloads)
2580 {
2581         struct bnxt_vnic_info *vnic;
2582         unsigned int i;
2583         int rc;
2584
2585         vnic = BNXT_GET_DEFAULT_VNIC(bp);
2586         if (!(rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER)) {
2587                 /* Remove any VLAN filters programmed */
2588                 for (i = 0; i < RTE_ETHER_MAX_VLAN_ID; i++)
2589                         bnxt_del_vlan_filter(bp, i);
2590
2591                 rc = bnxt_add_mac_filter(bp, vnic, NULL, 0, 0);
2592                 if (rc)
2593                         return rc;
2594         } else {
2595                 /* Default filter will allow packets that match the
2596                  * dest mac. So, it has to be deleted, otherwise, we
2597                  * will endup receiving vlan packets for which the
2598                  * filter is not programmed, when hw-vlan-filter
2599                  * configuration is ON
2600                  */
2601                 bnxt_del_dflt_mac_filter(bp, vnic);
2602                 /* This filter will allow only untagged packets */
2603                 bnxt_add_vlan_filter(bp, 0);
2604         }
2605         PMD_DRV_LOG(DEBUG, "VLAN Filtering: %d\n",
2606                     !!(rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER));
2607
2608         return 0;
2609 }
2610
2611 static int bnxt_free_one_vnic(struct bnxt *bp, uint16_t vnic_id)
2612 {
2613         struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id];
2614         unsigned int i;
2615         int rc;
2616
2617         /* Destroy vnic filters and vnic */
2618         if (bp->eth_dev->data->dev_conf.rxmode.offloads &
2619             DEV_RX_OFFLOAD_VLAN_FILTER) {
2620                 for (i = 0; i < RTE_ETHER_MAX_VLAN_ID; i++)
2621                         bnxt_del_vlan_filter(bp, i);
2622         }
2623         bnxt_del_dflt_mac_filter(bp, vnic);
2624
2625         rc = bnxt_hwrm_vnic_ctx_free(bp, vnic);
2626         if (rc)
2627                 return rc;
2628
2629         rc = bnxt_hwrm_vnic_free(bp, vnic);
2630         if (rc)
2631                 return rc;
2632
2633         rte_free(vnic->fw_grp_ids);
2634         vnic->fw_grp_ids = NULL;
2635
2636         vnic->rx_queue_cnt = 0;
2637
2638         return 0;
2639 }
2640
2641 static int
2642 bnxt_config_vlan_hw_stripping(struct bnxt *bp, uint64_t rx_offloads)
2643 {
2644         struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp);
2645         int rc;
2646
2647         /* Destroy, recreate and reconfigure the default vnic */
2648         rc = bnxt_free_one_vnic(bp, 0);
2649         if (rc)
2650                 return rc;
2651
2652         /* default vnic 0 */
2653         rc = bnxt_setup_one_vnic(bp, 0);
2654         if (rc)
2655                 return rc;
2656
2657         if (bp->eth_dev->data->dev_conf.rxmode.offloads &
2658             DEV_RX_OFFLOAD_VLAN_FILTER) {
2659                 rc = bnxt_add_vlan_filter(bp, 0);
2660                 if (rc)
2661                         return rc;
2662                 rc = bnxt_restore_vlan_filters(bp);
2663                 if (rc)
2664                         return rc;
2665         } else {
2666                 rc = bnxt_add_mac_filter(bp, vnic, NULL, 0, 0);
2667                 if (rc)
2668                         return rc;
2669         }
2670
2671         rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
2672         if (rc)
2673                 return rc;
2674
2675         PMD_DRV_LOG(DEBUG, "VLAN Strip Offload: %d\n",
2676                     !!(rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP));
2677
2678         return rc;
2679 }
2680
2681 static int
2682 bnxt_vlan_offload_set_op(struct rte_eth_dev *dev, int mask)
2683 {
2684         uint64_t rx_offloads = dev->data->dev_conf.rxmode.offloads;
2685         struct bnxt *bp = dev->data->dev_private;
2686         int rc;
2687
2688         rc = is_bnxt_in_error(bp);
2689         if (rc)
2690                 return rc;
2691
2692         /* Filter settings will get applied when port is started */
2693         if (!dev->data->dev_started)
2694                 return 0;
2695
2696         if (mask & ETH_VLAN_FILTER_MASK) {
2697                 /* Enable or disable VLAN filtering */
2698                 rc = bnxt_config_vlan_hw_filter(bp, rx_offloads);
2699                 if (rc)
2700                         return rc;
2701         }
2702
2703         if (mask & ETH_VLAN_STRIP_MASK) {
2704                 /* Enable or disable VLAN stripping */
2705                 rc = bnxt_config_vlan_hw_stripping(bp, rx_offloads);
2706                 if (rc)
2707                         return rc;
2708         }
2709
2710         if (mask & ETH_VLAN_EXTEND_MASK) {
2711                 if (rx_offloads & DEV_RX_OFFLOAD_VLAN_EXTEND)
2712                         PMD_DRV_LOG(DEBUG, "Extend VLAN supported\n");
2713                 else
2714                         PMD_DRV_LOG(INFO, "Extend VLAN unsupported\n");
2715         }
2716
2717         return 0;
2718 }
2719
2720 static int
2721 bnxt_vlan_tpid_set_op(struct rte_eth_dev *dev, enum rte_vlan_type vlan_type,
2722                       uint16_t tpid)
2723 {
2724         struct bnxt *bp = dev->data->dev_private;
2725         int qinq = dev->data->dev_conf.rxmode.offloads &
2726                    DEV_RX_OFFLOAD_VLAN_EXTEND;
2727
2728         if (vlan_type != ETH_VLAN_TYPE_INNER &&
2729             vlan_type != ETH_VLAN_TYPE_OUTER) {
2730                 PMD_DRV_LOG(ERR,
2731                             "Unsupported vlan type.");
2732                 return -EINVAL;
2733         }
2734         if (!qinq) {
2735                 PMD_DRV_LOG(ERR,
2736                             "QinQ not enabled. Needs to be ON as we can "
2737                             "accelerate only outer vlan\n");
2738                 return -EINVAL;
2739         }
2740
2741         if (vlan_type == ETH_VLAN_TYPE_OUTER) {
2742                 switch (tpid) {
2743                 case RTE_ETHER_TYPE_QINQ:
2744                         bp->outer_tpid_bd =
2745                                 TX_BD_LONG_CFA_META_VLAN_TPID_TPID88A8;
2746                                 break;
2747                 case RTE_ETHER_TYPE_VLAN:
2748                         bp->outer_tpid_bd =
2749                                 TX_BD_LONG_CFA_META_VLAN_TPID_TPID8100;
2750                                 break;
2751                 case RTE_ETHER_TYPE_QINQ1:
2752                         bp->outer_tpid_bd =
2753                                 TX_BD_LONG_CFA_META_VLAN_TPID_TPID9100;
2754                                 break;
2755                 case RTE_ETHER_TYPE_QINQ2:
2756                         bp->outer_tpid_bd =
2757                                 TX_BD_LONG_CFA_META_VLAN_TPID_TPID9200;
2758                                 break;
2759                 case RTE_ETHER_TYPE_QINQ3:
2760                         bp->outer_tpid_bd =
2761                                  TX_BD_LONG_CFA_META_VLAN_TPID_TPID9300;
2762                                 break;
2763                 default:
2764                         PMD_DRV_LOG(ERR, "Invalid TPID: %x\n", tpid);
2765                         return -EINVAL;
2766                 }
2767                 bp->outer_tpid_bd |= tpid;
2768                 PMD_DRV_LOG(INFO, "outer_tpid_bd = %x\n", bp->outer_tpid_bd);
2769         } else if (vlan_type == ETH_VLAN_TYPE_INNER) {
2770                 PMD_DRV_LOG(ERR,
2771                             "Can accelerate only outer vlan in QinQ\n");
2772                 return -EINVAL;
2773         }
2774
2775         return 0;
2776 }
2777
2778 static int
2779 bnxt_set_default_mac_addr_op(struct rte_eth_dev *dev,
2780                              struct rte_ether_addr *addr)
2781 {
2782         struct bnxt *bp = dev->data->dev_private;
2783         /* Default Filter is tied to VNIC 0 */
2784         struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp);
2785         int rc;
2786
2787         rc = is_bnxt_in_error(bp);
2788         if (rc)
2789                 return rc;
2790
2791         if (BNXT_VF(bp) && !BNXT_VF_IS_TRUSTED(bp))
2792                 return -EPERM;
2793
2794         if (rte_is_zero_ether_addr(addr))
2795                 return -EINVAL;
2796
2797         /* Filter settings will get applied when port is started */
2798         if (!dev->data->dev_started)
2799                 return 0;
2800
2801         /* Check if the requested MAC is already added */
2802         if (memcmp(addr, bp->mac_addr, RTE_ETHER_ADDR_LEN) == 0)
2803                 return 0;
2804
2805         /* Destroy filter and re-create it */
2806         bnxt_del_dflt_mac_filter(bp, vnic);
2807
2808         memcpy(bp->mac_addr, addr, RTE_ETHER_ADDR_LEN);
2809         if (dev->data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_VLAN_FILTER) {
2810                 /* This filter will allow only untagged packets */
2811                 rc = bnxt_add_vlan_filter(bp, 0);
2812         } else {
2813                 rc = bnxt_add_mac_filter(bp, vnic, addr, 0, 0);
2814         }
2815
2816         PMD_DRV_LOG(DEBUG, "Set MAC addr\n");
2817         return rc;
2818 }
2819
2820 static int
2821 bnxt_dev_set_mc_addr_list_op(struct rte_eth_dev *eth_dev,
2822                           struct rte_ether_addr *mc_addr_set,
2823                           uint32_t nb_mc_addr)
2824 {
2825         struct bnxt *bp = eth_dev->data->dev_private;
2826         char *mc_addr_list = (char *)mc_addr_set;
2827         struct bnxt_vnic_info *vnic;
2828         uint32_t off = 0, i = 0;
2829         int rc;
2830
2831         rc = is_bnxt_in_error(bp);
2832         if (rc)
2833                 return rc;
2834
2835         vnic = BNXT_GET_DEFAULT_VNIC(bp);
2836
2837         if (nb_mc_addr > BNXT_MAX_MC_ADDRS) {
2838                 vnic->flags |= BNXT_VNIC_INFO_ALLMULTI;
2839                 goto allmulti;
2840         }
2841
2842         /* TODO Check for Duplicate mcast addresses */
2843         vnic->flags &= ~BNXT_VNIC_INFO_ALLMULTI;
2844         for (i = 0; i < nb_mc_addr; i++) {
2845                 memcpy(vnic->mc_list + off, &mc_addr_list[i],
2846                         RTE_ETHER_ADDR_LEN);
2847                 off += RTE_ETHER_ADDR_LEN;
2848         }
2849
2850         vnic->mc_addr_cnt = i;
2851         if (vnic->mc_addr_cnt)
2852                 vnic->flags |= BNXT_VNIC_INFO_MCAST;
2853         else
2854                 vnic->flags &= ~BNXT_VNIC_INFO_MCAST;
2855
2856 allmulti:
2857         return bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
2858 }
2859
2860 static int
2861 bnxt_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size)
2862 {
2863         struct bnxt *bp = dev->data->dev_private;
2864         uint8_t fw_major = (bp->fw_ver >> 24) & 0xff;
2865         uint8_t fw_minor = (bp->fw_ver >> 16) & 0xff;
2866         uint8_t fw_updt = (bp->fw_ver >> 8) & 0xff;
2867         uint8_t fw_rsvd = bp->fw_ver & 0xff;
2868         int ret;
2869
2870         ret = snprintf(fw_version, fw_size, "%d.%d.%d.%d",
2871                         fw_major, fw_minor, fw_updt, fw_rsvd);
2872         if (ret < 0)
2873                 return -EINVAL;
2874
2875         ret += 1; /* add the size of '\0' */
2876         if (fw_size < (size_t)ret)
2877                 return ret;
2878         else
2879                 return 0;
2880 }
2881
2882 static void
2883 bnxt_rxq_info_get_op(struct rte_eth_dev *dev, uint16_t queue_id,
2884         struct rte_eth_rxq_info *qinfo)
2885 {
2886         struct bnxt *bp = dev->data->dev_private;
2887         struct bnxt_rx_queue *rxq;
2888
2889         if (is_bnxt_in_error(bp))
2890                 return;
2891
2892         rxq = dev->data->rx_queues[queue_id];
2893
2894         qinfo->mp = rxq->mb_pool;
2895         qinfo->scattered_rx = dev->data->scattered_rx;
2896         qinfo->nb_desc = rxq->nb_rx_desc;
2897
2898         qinfo->conf.rx_free_thresh = rxq->rx_free_thresh;
2899         qinfo->conf.rx_drop_en = rxq->drop_en;
2900         qinfo->conf.rx_deferred_start = rxq->rx_deferred_start;
2901         qinfo->conf.offloads = dev->data->dev_conf.rxmode.offloads;
2902 }
2903
2904 static void
2905 bnxt_txq_info_get_op(struct rte_eth_dev *dev, uint16_t queue_id,
2906         struct rte_eth_txq_info *qinfo)
2907 {
2908         struct bnxt *bp = dev->data->dev_private;
2909         struct bnxt_tx_queue *txq;
2910
2911         if (is_bnxt_in_error(bp))
2912                 return;
2913
2914         txq = dev->data->tx_queues[queue_id];
2915
2916         qinfo->nb_desc = txq->nb_tx_desc;
2917
2918         qinfo->conf.tx_thresh.pthresh = txq->pthresh;
2919         qinfo->conf.tx_thresh.hthresh = txq->hthresh;
2920         qinfo->conf.tx_thresh.wthresh = txq->wthresh;
2921
2922         qinfo->conf.tx_free_thresh = txq->tx_free_thresh;
2923         qinfo->conf.tx_rs_thresh = 0;
2924         qinfo->conf.tx_deferred_start = txq->tx_deferred_start;
2925         qinfo->conf.offloads = txq->offloads;
2926 }
2927
2928 static const struct {
2929         eth_rx_burst_t pkt_burst;
2930         const char *info;
2931 } bnxt_rx_burst_info[] = {
2932         {bnxt_recv_pkts,                "Scalar"},
2933 #if defined(RTE_ARCH_X86)
2934         {bnxt_recv_pkts_vec,            "Vector SSE"},
2935 #endif
2936 #if defined(RTE_ARCH_X86) && defined(CC_AVX2_SUPPORT)
2937         {bnxt_recv_pkts_vec_avx2,       "Vector AVX2"},
2938 #endif
2939 #if defined(RTE_ARCH_ARM64)
2940         {bnxt_recv_pkts_vec,            "Vector Neon"},
2941 #endif
2942 };
2943
2944 static int
2945 bnxt_rx_burst_mode_get(struct rte_eth_dev *dev, __rte_unused uint16_t queue_id,
2946                        struct rte_eth_burst_mode *mode)
2947 {
2948         eth_rx_burst_t pkt_burst = dev->rx_pkt_burst;
2949         size_t i;
2950
2951         for (i = 0; i < RTE_DIM(bnxt_rx_burst_info); i++) {
2952                 if (pkt_burst == bnxt_rx_burst_info[i].pkt_burst) {
2953                         snprintf(mode->info, sizeof(mode->info), "%s",
2954                                  bnxt_rx_burst_info[i].info);
2955                         return 0;
2956                 }
2957         }
2958
2959         return -EINVAL;
2960 }
2961
2962 static const struct {
2963         eth_tx_burst_t pkt_burst;
2964         const char *info;
2965 } bnxt_tx_burst_info[] = {
2966         {bnxt_xmit_pkts,                "Scalar"},
2967 #if defined(RTE_ARCH_X86)
2968         {bnxt_xmit_pkts_vec,            "Vector SSE"},
2969 #endif
2970 #if defined(RTE_ARCH_X86) && defined(CC_AVX2_SUPPORT)
2971         {bnxt_xmit_pkts_vec_avx2,       "Vector AVX2"},
2972 #endif
2973 #if defined(RTE_ARCH_ARM64)
2974         {bnxt_xmit_pkts_vec,            "Vector Neon"},
2975 #endif
2976 };
2977
2978 static int
2979 bnxt_tx_burst_mode_get(struct rte_eth_dev *dev, __rte_unused uint16_t queue_id,
2980                        struct rte_eth_burst_mode *mode)
2981 {
2982         eth_tx_burst_t pkt_burst = dev->tx_pkt_burst;
2983         size_t i;
2984
2985         for (i = 0; i < RTE_DIM(bnxt_tx_burst_info); i++) {
2986                 if (pkt_burst == bnxt_tx_burst_info[i].pkt_burst) {
2987                         snprintf(mode->info, sizeof(mode->info), "%s",
2988                                  bnxt_tx_burst_info[i].info);
2989                         return 0;
2990                 }
2991         }
2992
2993         return -EINVAL;
2994 }
2995
2996 int bnxt_mtu_set_op(struct rte_eth_dev *eth_dev, uint16_t new_mtu)
2997 {
2998         struct bnxt *bp = eth_dev->data->dev_private;
2999         uint32_t new_pkt_size;
3000         uint32_t rc = 0;
3001         uint32_t i;
3002
3003         rc = is_bnxt_in_error(bp);
3004         if (rc)
3005                 return rc;
3006
3007         /* Exit if receive queues are not configured yet */
3008         if (!eth_dev->data->nb_rx_queues)
3009                 return rc;
3010
3011         new_pkt_size = new_mtu + RTE_ETHER_HDR_LEN + RTE_ETHER_CRC_LEN +
3012                        VLAN_TAG_SIZE * BNXT_NUM_VLANS;
3013
3014         /*
3015          * Disallow any MTU change that would require scattered receive support
3016          * if it is not already enabled.
3017          */
3018         if (eth_dev->data->dev_started &&
3019             !eth_dev->data->scattered_rx &&
3020             (new_pkt_size >
3021              eth_dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM)) {
3022                 PMD_DRV_LOG(ERR,
3023                             "MTU change would require scattered rx support. ");
3024                 PMD_DRV_LOG(ERR, "Stop port before changing MTU.\n");
3025                 return -EINVAL;
3026         }
3027
3028         if (new_mtu > RTE_ETHER_MTU) {
3029                 bp->flags |= BNXT_FLAG_JUMBO;
3030                 bp->eth_dev->data->dev_conf.rxmode.offloads |=
3031                         DEV_RX_OFFLOAD_JUMBO_FRAME;
3032         } else {
3033                 bp->eth_dev->data->dev_conf.rxmode.offloads &=
3034                         ~DEV_RX_OFFLOAD_JUMBO_FRAME;
3035                 bp->flags &= ~BNXT_FLAG_JUMBO;
3036         }
3037
3038         /* Is there a change in mtu setting? */
3039         if (eth_dev->data->dev_conf.rxmode.max_rx_pkt_len == new_pkt_size)
3040                 return rc;
3041
3042         for (i = 0; i < bp->nr_vnics; i++) {
3043                 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
3044                 uint16_t size = 0;
3045
3046                 vnic->mru = BNXT_VNIC_MRU(new_mtu);
3047                 rc = bnxt_hwrm_vnic_cfg(bp, vnic);
3048                 if (rc)
3049                         break;
3050
3051                 size = rte_pktmbuf_data_room_size(bp->rx_queues[0]->mb_pool);
3052                 size -= RTE_PKTMBUF_HEADROOM;
3053
3054                 if (size < new_mtu) {
3055                         rc = bnxt_hwrm_vnic_plcmode_cfg(bp, vnic);
3056                         if (rc)
3057                                 return rc;
3058                 }
3059         }
3060
3061         if (!rc)
3062                 eth_dev->data->dev_conf.rxmode.max_rx_pkt_len = new_pkt_size;
3063
3064         PMD_DRV_LOG(INFO, "New MTU is %d\n", new_mtu);
3065
3066         return rc;
3067 }
3068
3069 static int
3070 bnxt_vlan_pvid_set_op(struct rte_eth_dev *dev, uint16_t pvid, int on)
3071 {
3072         struct bnxt *bp = dev->data->dev_private;
3073         uint16_t vlan = bp->vlan;
3074         int rc;
3075
3076         rc = is_bnxt_in_error(bp);
3077         if (rc)
3078                 return rc;
3079
3080         if (!BNXT_SINGLE_PF(bp)) {
3081                 PMD_DRV_LOG(ERR, "PVID cannot be modified on VF or on shared PF\n");
3082                 return -ENOTSUP;
3083         }
3084         bp->vlan = on ? pvid : 0;
3085
3086         rc = bnxt_hwrm_set_default_vlan(bp, 0, 0);
3087         if (rc)
3088                 bp->vlan = vlan;
3089         return rc;
3090 }
3091
3092 static int
3093 bnxt_dev_led_on_op(struct rte_eth_dev *dev)
3094 {
3095         struct bnxt *bp = dev->data->dev_private;
3096         int rc;
3097
3098         rc = is_bnxt_in_error(bp);
3099         if (rc)
3100                 return rc;
3101
3102         return bnxt_hwrm_port_led_cfg(bp, true);
3103 }
3104
3105 static int
3106 bnxt_dev_led_off_op(struct rte_eth_dev *dev)
3107 {
3108         struct bnxt *bp = dev->data->dev_private;
3109         int rc;
3110
3111         rc = is_bnxt_in_error(bp);
3112         if (rc)
3113                 return rc;
3114
3115         return bnxt_hwrm_port_led_cfg(bp, false);
3116 }
3117
3118 static uint32_t
3119 bnxt_rx_queue_count_op(struct rte_eth_dev *dev, uint16_t rx_queue_id)
3120 {
3121         struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
3122         struct bnxt_cp_ring_info *cpr;
3123         uint32_t desc = 0, raw_cons;
3124         struct bnxt_rx_queue *rxq;
3125         struct rx_pkt_cmpl *rxcmp;
3126         int rc;
3127
3128         rc = is_bnxt_in_error(bp);
3129         if (rc)
3130                 return rc;
3131
3132         rxq = dev->data->rx_queues[rx_queue_id];
3133         cpr = rxq->cp_ring;
3134         raw_cons = cpr->cp_raw_cons;
3135
3136         while (1) {
3137                 uint32_t agg_cnt, cons, cmpl_type;
3138
3139                 cons = RING_CMP(cpr->cp_ring_struct, raw_cons);
3140                 rxcmp = (struct rx_pkt_cmpl *)&cpr->cp_desc_ring[cons];
3141
3142                 if (!CMP_VALID(rxcmp, raw_cons, cpr->cp_ring_struct))
3143                         break;
3144
3145                 cmpl_type = CMP_TYPE(rxcmp);
3146
3147                 switch (cmpl_type) {
3148                 case CMPL_BASE_TYPE_RX_L2:
3149                 case CMPL_BASE_TYPE_RX_L2_V2:
3150                         agg_cnt = BNXT_RX_L2_AGG_BUFS(rxcmp);
3151                         raw_cons = raw_cons + CMP_LEN(cmpl_type) + agg_cnt;
3152                         desc++;
3153                         break;
3154
3155                 case CMPL_BASE_TYPE_RX_TPA_END:
3156                         if (BNXT_CHIP_P5(rxq->bp)) {
3157                                 struct rx_tpa_v2_end_cmpl_hi *p5_tpa_end;
3158
3159                                 p5_tpa_end = (void *)rxcmp;
3160                                 agg_cnt = BNXT_TPA_END_AGG_BUFS_TH(p5_tpa_end);
3161                         } else {
3162                                 struct rx_tpa_end_cmpl *tpa_end;
3163
3164                                 tpa_end = (void *)rxcmp;
3165                                 agg_cnt = BNXT_TPA_END_AGG_BUFS(tpa_end);
3166                         }
3167
3168                         raw_cons = raw_cons + CMP_LEN(cmpl_type) + agg_cnt;
3169                         desc++;
3170                         break;
3171
3172                 default:
3173                         raw_cons += CMP_LEN(cmpl_type);
3174                 }
3175         }
3176
3177         return desc;
3178 }
3179
3180 static int
3181 bnxt_rx_descriptor_status_op(void *rx_queue, uint16_t offset)
3182 {
3183         struct bnxt_rx_queue *rxq = rx_queue;
3184         struct bnxt_cp_ring_info *cpr;
3185         struct bnxt_rx_ring_info *rxr;
3186         uint32_t desc, raw_cons;
3187         struct bnxt *bp = rxq->bp;
3188         struct rx_pkt_cmpl *rxcmp;
3189         int rc;
3190
3191         rc = is_bnxt_in_error(bp);
3192         if (rc)
3193                 return rc;
3194
3195         if (offset >= rxq->nb_rx_desc)
3196                 return -EINVAL;
3197
3198         rxr = rxq->rx_ring;
3199         cpr = rxq->cp_ring;
3200
3201         /*
3202          * For the vector receive case, the completion at the requested
3203          * offset can be indexed directly.
3204          */
3205 #if defined(RTE_ARCH_X86) || defined(RTE_ARCH_ARM64)
3206         if (bp->flags & BNXT_FLAG_RX_VECTOR_PKT_MODE) {
3207                 struct rx_pkt_cmpl *rxcmp;
3208                 uint32_t cons;
3209
3210                 /* Check status of completion descriptor. */
3211                 raw_cons = cpr->cp_raw_cons +
3212                            offset * CMP_LEN(CMPL_BASE_TYPE_RX_L2);
3213                 cons = RING_CMP(cpr->cp_ring_struct, raw_cons);
3214                 rxcmp = (struct rx_pkt_cmpl *)&cpr->cp_desc_ring[cons];
3215
3216                 if (CMP_VALID(rxcmp, raw_cons, cpr->cp_ring_struct))
3217                         return RTE_ETH_RX_DESC_DONE;
3218
3219                 /* Check whether rx desc has an mbuf attached. */
3220                 cons = RING_CMP(rxr->rx_ring_struct, raw_cons / 2);
3221                 if (cons >= rxq->rxrearm_start &&
3222                     cons < rxq->rxrearm_start + rxq->rxrearm_nb) {
3223                         return RTE_ETH_RX_DESC_UNAVAIL;
3224                 }
3225
3226                 return RTE_ETH_RX_DESC_AVAIL;
3227         }
3228 #endif
3229
3230         /*
3231          * For the non-vector receive case, scan the completion ring to
3232          * locate the completion descriptor for the requested offset.
3233          */
3234         raw_cons = cpr->cp_raw_cons;
3235         desc = 0;
3236         while (1) {
3237                 uint32_t agg_cnt, cons, cmpl_type;
3238
3239                 cons = RING_CMP(cpr->cp_ring_struct, raw_cons);
3240                 rxcmp = (struct rx_pkt_cmpl *)&cpr->cp_desc_ring[cons];
3241
3242                 if (!CMP_VALID(rxcmp, raw_cons, cpr->cp_ring_struct))
3243                         break;
3244
3245                 cmpl_type = CMP_TYPE(rxcmp);
3246
3247                 switch (cmpl_type) {
3248                 case CMPL_BASE_TYPE_RX_L2:
3249                 case CMPL_BASE_TYPE_RX_L2_V2:
3250                         if (desc == offset) {
3251                                 cons = rxcmp->opaque;
3252                                 if (rxr->rx_buf_ring[cons])
3253                                         return RTE_ETH_RX_DESC_DONE;
3254                                 else
3255                                         return RTE_ETH_RX_DESC_UNAVAIL;
3256                         }
3257                         agg_cnt = BNXT_RX_L2_AGG_BUFS(rxcmp);
3258                         raw_cons = raw_cons + CMP_LEN(cmpl_type) + agg_cnt;
3259                         desc++;
3260                         break;
3261
3262                 case CMPL_BASE_TYPE_RX_TPA_END:
3263                         if (desc == offset)
3264                                 return RTE_ETH_RX_DESC_DONE;
3265
3266                         if (BNXT_CHIP_P5(rxq->bp)) {
3267                                 struct rx_tpa_v2_end_cmpl_hi *p5_tpa_end;
3268
3269                                 p5_tpa_end = (void *)rxcmp;
3270                                 agg_cnt = BNXT_TPA_END_AGG_BUFS_TH(p5_tpa_end);
3271                         } else {
3272                                 struct rx_tpa_end_cmpl *tpa_end;
3273
3274                                 tpa_end = (void *)rxcmp;
3275                                 agg_cnt = BNXT_TPA_END_AGG_BUFS(tpa_end);
3276                         }
3277
3278                         raw_cons = raw_cons + CMP_LEN(cmpl_type) + agg_cnt;
3279                         desc++;
3280                         break;
3281
3282                 default:
3283                         raw_cons += CMP_LEN(cmpl_type);
3284                 }
3285         }
3286
3287         return RTE_ETH_RX_DESC_AVAIL;
3288 }
3289
3290 static int
3291 bnxt_tx_descriptor_status_op(void *tx_queue, uint16_t offset)
3292 {
3293         struct bnxt_tx_queue *txq = (struct bnxt_tx_queue *)tx_queue;
3294         struct bnxt_tx_ring_info *txr;
3295         struct bnxt_cp_ring_info *cpr;
3296         struct rte_mbuf **tx_buf;
3297         struct tx_pkt_cmpl *txcmp;
3298         uint32_t cons, cp_cons;
3299         int rc;
3300
3301         if (!txq)
3302                 return -EINVAL;
3303
3304         rc = is_bnxt_in_error(txq->bp);
3305         if (rc)
3306                 return rc;
3307
3308         cpr = txq->cp_ring;
3309         txr = txq->tx_ring;
3310
3311         if (offset >= txq->nb_tx_desc)
3312                 return -EINVAL;
3313
3314         cons = RING_CMP(cpr->cp_ring_struct, offset);
3315         txcmp = (struct tx_pkt_cmpl *)&cpr->cp_desc_ring[cons];
3316         cp_cons = cpr->cp_raw_cons;
3317
3318         if (cons > cp_cons) {
3319                 if (CMPL_VALID(txcmp, cpr->valid))
3320                         return RTE_ETH_TX_DESC_UNAVAIL;
3321         } else {
3322                 if (CMPL_VALID(txcmp, !cpr->valid))
3323                         return RTE_ETH_TX_DESC_UNAVAIL;
3324         }
3325         tx_buf = &txr->tx_buf_ring[cons];
3326         if (*tx_buf == NULL)
3327                 return RTE_ETH_TX_DESC_DONE;
3328
3329         return RTE_ETH_TX_DESC_FULL;
3330 }
3331
3332 int
3333 bnxt_flow_ops_get_op(struct rte_eth_dev *dev,
3334                      const struct rte_flow_ops **ops)
3335 {
3336         struct bnxt *bp = dev->data->dev_private;
3337         int ret = 0;
3338
3339         if (!bp)
3340                 return -EIO;
3341
3342         if (BNXT_ETH_DEV_IS_REPRESENTOR(dev)) {
3343                 struct bnxt_representor *vfr = dev->data->dev_private;
3344                 bp = vfr->parent_dev->data->dev_private;
3345                 /* parent is deleted while children are still valid */
3346                 if (!bp) {
3347                         PMD_DRV_LOG(DEBUG, "BNXT Port:%d VFR Error\n",
3348                                     dev->data->port_id);
3349                         return -EIO;
3350                 }
3351         }
3352
3353         ret = is_bnxt_in_error(bp);
3354         if (ret)
3355                 return ret;
3356
3357         /* PMD supports thread-safe flow operations.  rte_flow API
3358          * functions can avoid mutex for multi-thread safety.
3359          */
3360         dev->data->dev_flags |= RTE_ETH_DEV_FLOW_OPS_THREAD_SAFE;
3361
3362         if (BNXT_TRUFLOW_EN(bp))
3363                 *ops = &bnxt_ulp_rte_flow_ops;
3364         else
3365                 *ops = &bnxt_flow_ops;
3366
3367         return ret;
3368 }
3369
3370 static const uint32_t *
3371 bnxt_dev_supported_ptypes_get_op(struct rte_eth_dev *dev)
3372 {
3373         static const uint32_t ptypes[] = {
3374                 RTE_PTYPE_L2_ETHER_VLAN,
3375                 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN,
3376                 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN,
3377                 RTE_PTYPE_L4_ICMP,
3378                 RTE_PTYPE_L4_TCP,
3379                 RTE_PTYPE_L4_UDP,
3380                 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN,
3381                 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN,
3382                 RTE_PTYPE_INNER_L4_ICMP,
3383                 RTE_PTYPE_INNER_L4_TCP,
3384                 RTE_PTYPE_INNER_L4_UDP,
3385                 RTE_PTYPE_UNKNOWN
3386         };
3387
3388         if (!dev->rx_pkt_burst)
3389                 return NULL;
3390
3391         return ptypes;
3392 }
3393
3394 static int bnxt_map_regs(struct bnxt *bp, uint32_t *reg_arr, int count,
3395                          int reg_win)
3396 {
3397         uint32_t reg_base = *reg_arr & 0xfffff000;
3398         uint32_t win_off;
3399         int i;
3400
3401         for (i = 0; i < count; i++) {
3402                 if ((reg_arr[i] & 0xfffff000) != reg_base)
3403                         return -ERANGE;
3404         }
3405         win_off = BNXT_GRCPF_REG_WINDOW_BASE_OUT + (reg_win - 1) * 4;
3406         rte_write32(reg_base, (uint8_t *)bp->bar0 + win_off);
3407         return 0;
3408 }
3409
3410 static int bnxt_map_ptp_regs(struct bnxt *bp)
3411 {
3412         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3413         uint32_t *reg_arr;
3414         int rc, i;
3415
3416         reg_arr = ptp->rx_regs;
3417         rc = bnxt_map_regs(bp, reg_arr, BNXT_PTP_RX_REGS, 5);
3418         if (rc)
3419                 return rc;
3420
3421         reg_arr = ptp->tx_regs;
3422         rc = bnxt_map_regs(bp, reg_arr, BNXT_PTP_TX_REGS, 6);
3423         if (rc)
3424                 return rc;
3425
3426         for (i = 0; i < BNXT_PTP_RX_REGS; i++)
3427                 ptp->rx_mapped_regs[i] = 0x5000 + (ptp->rx_regs[i] & 0xfff);
3428
3429         for (i = 0; i < BNXT_PTP_TX_REGS; i++)
3430                 ptp->tx_mapped_regs[i] = 0x6000 + (ptp->tx_regs[i] & 0xfff);
3431
3432         return 0;
3433 }
3434
3435 static void bnxt_unmap_ptp_regs(struct bnxt *bp)
3436 {
3437         rte_write32(0, (uint8_t *)bp->bar0 +
3438                          BNXT_GRCPF_REG_WINDOW_BASE_OUT + 16);
3439         rte_write32(0, (uint8_t *)bp->bar0 +
3440                          BNXT_GRCPF_REG_WINDOW_BASE_OUT + 20);
3441 }
3442
3443 static uint64_t bnxt_cc_read(struct bnxt *bp)
3444 {
3445         uint64_t ns;
3446
3447         ns = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3448                               BNXT_GRCPF_REG_SYNC_TIME));
3449         ns |= (uint64_t)(rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3450                                           BNXT_GRCPF_REG_SYNC_TIME + 4))) << 32;
3451         return ns;
3452 }
3453
3454 static int bnxt_get_tx_ts(struct bnxt *bp, uint64_t *ts)
3455 {
3456         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3457         uint32_t fifo;
3458
3459         fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3460                                 ptp->tx_mapped_regs[BNXT_PTP_TX_FIFO]));
3461         if (fifo & BNXT_PTP_TX_FIFO_EMPTY)
3462                 return -EAGAIN;
3463
3464         fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3465                                 ptp->tx_mapped_regs[BNXT_PTP_TX_FIFO]));
3466         *ts = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3467                                 ptp->tx_mapped_regs[BNXT_PTP_TX_TS_L]));
3468         *ts |= (uint64_t)rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3469                                 ptp->tx_mapped_regs[BNXT_PTP_TX_TS_H])) << 32;
3470         rte_read32((uint8_t *)bp->bar0 + ptp->tx_mapped_regs[BNXT_PTP_TX_SEQ]);
3471
3472         return 0;
3473 }
3474
3475 static int bnxt_clr_rx_ts(struct bnxt *bp, uint64_t *last_ts)
3476 {
3477         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3478         struct bnxt_pf_info *pf = bp->pf;
3479         uint16_t port_id;
3480         int i = 0;
3481         uint32_t fifo;
3482
3483         if (!ptp || (bp->flags & BNXT_FLAG_CHIP_P5))
3484                 return -EINVAL;
3485
3486         port_id = pf->port_id;
3487         fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3488                                 ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO]));
3489         while ((fifo & BNXT_PTP_RX_FIFO_PENDING) && (i < BNXT_PTP_RX_PND_CNT)) {
3490                 rte_write32(1 << port_id, (uint8_t *)bp->bar0 +
3491                             ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO_ADV]);
3492                 fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3493                                         ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO]));
3494                 *last_ts = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3495                                         ptp->rx_mapped_regs[BNXT_PTP_RX_TS_L]));
3496                 *last_ts |= (uint64_t)rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3497                                         ptp->rx_mapped_regs[BNXT_PTP_RX_TS_H])) << 32;
3498                 i++;
3499         }
3500
3501         if (i >= BNXT_PTP_RX_PND_CNT)
3502                 return -EBUSY;
3503
3504         return 0;
3505 }
3506
3507 static int bnxt_get_rx_ts(struct bnxt *bp, uint64_t *ts)
3508 {
3509         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3510         struct bnxt_pf_info *pf = bp->pf;
3511         uint16_t port_id;
3512         uint32_t fifo;
3513
3514         fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3515                                 ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO]));
3516         if (!(fifo & BNXT_PTP_RX_FIFO_PENDING))
3517                 return -EAGAIN;
3518
3519         port_id = pf->port_id;
3520         rte_write32(1 << port_id, (uint8_t *)bp->bar0 +
3521                ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO_ADV]);
3522
3523         fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3524                                    ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO]));
3525         if (fifo & BNXT_PTP_RX_FIFO_PENDING)
3526                 return bnxt_clr_rx_ts(bp, ts);
3527
3528         *ts = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3529                                 ptp->rx_mapped_regs[BNXT_PTP_RX_TS_L]));
3530         *ts |= (uint64_t)rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3531                                 ptp->rx_mapped_regs[BNXT_PTP_RX_TS_H])) << 32;
3532
3533         return 0;
3534 }
3535
3536 static int
3537 bnxt_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
3538 {
3539         uint64_t ns;
3540         struct bnxt *bp = dev->data->dev_private;
3541         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3542
3543         if (!ptp)
3544                 return -ENOTSUP;
3545
3546         ns = rte_timespec_to_ns(ts);
3547         /* Set the timecounters to a new value. */
3548         ptp->tc.nsec = ns;
3549         ptp->tx_tstamp_tc.nsec = ns;
3550         ptp->rx_tstamp_tc.nsec = ns;
3551
3552         return 0;
3553 }
3554
3555 static int
3556 bnxt_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
3557 {
3558         struct bnxt *bp = dev->data->dev_private;
3559         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3560         uint64_t ns, systime_cycles = 0;
3561         int rc = 0;
3562
3563         if (!ptp)
3564                 return -ENOTSUP;
3565
3566         if (BNXT_CHIP_P5(bp))
3567                 rc = bnxt_hwrm_port_ts_query(bp, BNXT_PTP_FLAGS_CURRENT_TIME,
3568                                              &systime_cycles);
3569         else
3570                 systime_cycles = bnxt_cc_read(bp);
3571
3572         ns = rte_timecounter_update(&ptp->tc, systime_cycles);
3573         *ts = rte_ns_to_timespec(ns);
3574
3575         return rc;
3576 }
3577 static int
3578 bnxt_timesync_enable(struct rte_eth_dev *dev)
3579 {
3580         struct bnxt *bp = dev->data->dev_private;
3581         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3582         uint32_t shift = 0;
3583         int rc;
3584
3585         if (!ptp)
3586                 return -ENOTSUP;
3587
3588         ptp->rx_filter = 1;
3589         ptp->tx_tstamp_en = 1;
3590         ptp->rxctl = BNXT_PTP_MSG_EVENTS;
3591
3592         rc = bnxt_hwrm_ptp_cfg(bp);
3593         if (rc)
3594                 return rc;
3595
3596         memset(&ptp->tc, 0, sizeof(struct rte_timecounter));
3597         memset(&ptp->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
3598         memset(&ptp->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
3599
3600         ptp->tc.cc_mask = BNXT_CYCLECOUNTER_MASK;
3601         ptp->tc.cc_shift = shift;
3602         ptp->tc.nsec_mask = (1ULL << shift) - 1;
3603
3604         ptp->rx_tstamp_tc.cc_mask = BNXT_CYCLECOUNTER_MASK;
3605         ptp->rx_tstamp_tc.cc_shift = shift;
3606         ptp->rx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
3607
3608         ptp->tx_tstamp_tc.cc_mask = BNXT_CYCLECOUNTER_MASK;
3609         ptp->tx_tstamp_tc.cc_shift = shift;
3610         ptp->tx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
3611
3612         if (!BNXT_CHIP_P5(bp))
3613                 bnxt_map_ptp_regs(bp);
3614         else
3615                 rc = bnxt_ptp_start(bp);
3616
3617         return rc;
3618 }
3619
3620 static int
3621 bnxt_timesync_disable(struct rte_eth_dev *dev)
3622 {
3623         struct bnxt *bp = dev->data->dev_private;
3624         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3625
3626         if (!ptp)
3627                 return -ENOTSUP;
3628
3629         ptp->rx_filter = 0;
3630         ptp->tx_tstamp_en = 0;
3631         ptp->rxctl = 0;
3632
3633         bnxt_hwrm_ptp_cfg(bp);
3634
3635         if (!BNXT_CHIP_P5(bp))
3636                 bnxt_unmap_ptp_regs(bp);
3637         else
3638                 bnxt_ptp_stop(bp);
3639
3640         return 0;
3641 }
3642
3643 static int
3644 bnxt_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
3645                                  struct timespec *timestamp,
3646                                  uint32_t flags __rte_unused)
3647 {
3648         struct bnxt *bp = dev->data->dev_private;
3649         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3650         uint64_t rx_tstamp_cycles = 0;
3651         uint64_t ns;
3652
3653         if (!ptp)
3654                 return -ENOTSUP;
3655
3656         if (BNXT_CHIP_P5(bp))
3657                 rx_tstamp_cycles = ptp->rx_timestamp;
3658         else
3659                 bnxt_get_rx_ts(bp, &rx_tstamp_cycles);
3660
3661         ns = rte_timecounter_update(&ptp->rx_tstamp_tc, rx_tstamp_cycles);
3662         *timestamp = rte_ns_to_timespec(ns);
3663         return  0;
3664 }
3665
3666 static int
3667 bnxt_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
3668                                  struct timespec *timestamp)
3669 {
3670         struct bnxt *bp = dev->data->dev_private;
3671         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3672         uint64_t tx_tstamp_cycles = 0;
3673         uint64_t ns;
3674         int rc = 0;
3675
3676         if (!ptp)
3677                 return -ENOTSUP;
3678
3679         if (BNXT_CHIP_P5(bp))
3680                 rc = bnxt_hwrm_port_ts_query(bp, BNXT_PTP_FLAGS_PATH_TX,
3681                                              &tx_tstamp_cycles);
3682         else
3683                 rc = bnxt_get_tx_ts(bp, &tx_tstamp_cycles);
3684
3685         ns = rte_timecounter_update(&ptp->tx_tstamp_tc, tx_tstamp_cycles);
3686         *timestamp = rte_ns_to_timespec(ns);
3687
3688         return rc;
3689 }
3690
3691 static int
3692 bnxt_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
3693 {
3694         struct bnxt *bp = dev->data->dev_private;
3695         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3696
3697         if (!ptp)
3698                 return -ENOTSUP;
3699
3700         ptp->tc.nsec += delta;
3701         ptp->tx_tstamp_tc.nsec += delta;
3702         ptp->rx_tstamp_tc.nsec += delta;
3703
3704         return 0;
3705 }
3706
3707 static int
3708 bnxt_get_eeprom_length_op(struct rte_eth_dev *dev)
3709 {
3710         struct bnxt *bp = dev->data->dev_private;
3711         int rc;
3712         uint32_t dir_entries;
3713         uint32_t entry_length;
3714
3715         rc = is_bnxt_in_error(bp);
3716         if (rc)
3717                 return rc;
3718
3719         PMD_DRV_LOG(INFO, PCI_PRI_FMT "\n",
3720                     bp->pdev->addr.domain, bp->pdev->addr.bus,
3721                     bp->pdev->addr.devid, bp->pdev->addr.function);
3722
3723         rc = bnxt_hwrm_nvm_get_dir_info(bp, &dir_entries, &entry_length);
3724         if (rc != 0)
3725                 return rc;
3726
3727         return dir_entries * entry_length;
3728 }
3729
3730 static int
3731 bnxt_get_eeprom_op(struct rte_eth_dev *dev,
3732                 struct rte_dev_eeprom_info *in_eeprom)
3733 {
3734         struct bnxt *bp = dev->data->dev_private;
3735         uint32_t index;
3736         uint32_t offset;
3737         int rc;
3738
3739         rc = is_bnxt_in_error(bp);
3740         if (rc)
3741                 return rc;
3742
3743         PMD_DRV_LOG(INFO, PCI_PRI_FMT " in_eeprom->offset = %d len = %d\n",
3744                     bp->pdev->addr.domain, bp->pdev->addr.bus,
3745                     bp->pdev->addr.devid, bp->pdev->addr.function,
3746                     in_eeprom->offset, in_eeprom->length);
3747
3748         if (in_eeprom->offset == 0) /* special offset value to get directory */
3749                 return bnxt_get_nvram_directory(bp, in_eeprom->length,
3750                                                 in_eeprom->data);
3751
3752         index = in_eeprom->offset >> 24;
3753         offset = in_eeprom->offset & 0xffffff;
3754
3755         if (index != 0)
3756                 return bnxt_hwrm_get_nvram_item(bp, index - 1, offset,
3757                                            in_eeprom->length, in_eeprom->data);
3758
3759         return 0;
3760 }
3761
3762 static bool bnxt_dir_type_is_ape_bin_format(uint16_t dir_type)
3763 {
3764         switch (dir_type) {
3765         case BNX_DIR_TYPE_CHIMP_PATCH:
3766         case BNX_DIR_TYPE_BOOTCODE:
3767         case BNX_DIR_TYPE_BOOTCODE_2:
3768         case BNX_DIR_TYPE_APE_FW:
3769         case BNX_DIR_TYPE_APE_PATCH:
3770         case BNX_DIR_TYPE_KONG_FW:
3771         case BNX_DIR_TYPE_KONG_PATCH:
3772         case BNX_DIR_TYPE_BONO_FW:
3773         case BNX_DIR_TYPE_BONO_PATCH:
3774                 /* FALLTHROUGH */
3775                 return true;
3776         }
3777
3778         return false;
3779 }
3780
3781 static bool bnxt_dir_type_is_other_exec_format(uint16_t dir_type)
3782 {
3783         switch (dir_type) {
3784         case BNX_DIR_TYPE_AVS:
3785         case BNX_DIR_TYPE_EXP_ROM_MBA:
3786         case BNX_DIR_TYPE_PCIE:
3787         case BNX_DIR_TYPE_TSCF_UCODE:
3788         case BNX_DIR_TYPE_EXT_PHY:
3789         case BNX_DIR_TYPE_CCM:
3790         case BNX_DIR_TYPE_ISCSI_BOOT:
3791         case BNX_DIR_TYPE_ISCSI_BOOT_IPV6:
3792         case BNX_DIR_TYPE_ISCSI_BOOT_IPV4N6:
3793                 /* FALLTHROUGH */
3794                 return true;
3795         }
3796
3797         return false;
3798 }
3799
3800 static bool bnxt_dir_type_is_executable(uint16_t dir_type)
3801 {
3802         return bnxt_dir_type_is_ape_bin_format(dir_type) ||
3803                 bnxt_dir_type_is_other_exec_format(dir_type);
3804 }
3805
3806 static int
3807 bnxt_set_eeprom_op(struct rte_eth_dev *dev,
3808                 struct rte_dev_eeprom_info *in_eeprom)
3809 {
3810         struct bnxt *bp = dev->data->dev_private;
3811         uint8_t index, dir_op;
3812         uint16_t type, ext, ordinal, attr;
3813         int rc;
3814
3815         rc = is_bnxt_in_error(bp);
3816         if (rc)
3817                 return rc;
3818
3819         PMD_DRV_LOG(INFO, PCI_PRI_FMT " in_eeprom->offset = %d len = %d\n",
3820                     bp->pdev->addr.domain, bp->pdev->addr.bus,
3821                     bp->pdev->addr.devid, bp->pdev->addr.function,
3822                     in_eeprom->offset, in_eeprom->length);
3823
3824         if (!BNXT_PF(bp)) {
3825                 PMD_DRV_LOG(ERR, "NVM write not supported from a VF\n");
3826                 return -EINVAL;
3827         }
3828
3829         type = in_eeprom->magic >> 16;
3830
3831         if (type == 0xffff) { /* special value for directory operations */
3832                 index = in_eeprom->magic & 0xff;
3833                 dir_op = in_eeprom->magic >> 8;
3834                 if (index == 0)
3835                         return -EINVAL;
3836                 switch (dir_op) {
3837                 case 0x0e: /* erase */
3838                         if (in_eeprom->offset != ~in_eeprom->magic)
3839                                 return -EINVAL;
3840                         return bnxt_hwrm_erase_nvram_directory(bp, index - 1);
3841                 default:
3842                         return -EINVAL;
3843                 }
3844         }
3845
3846         /* Create or re-write an NVM item: */
3847         if (bnxt_dir_type_is_executable(type) == true)
3848                 return -EOPNOTSUPP;
3849         ext = in_eeprom->magic & 0xffff;
3850         ordinal = in_eeprom->offset >> 16;
3851         attr = in_eeprom->offset & 0xffff;
3852
3853         return bnxt_hwrm_flash_nvram(bp, type, ordinal, ext, attr,
3854                                      in_eeprom->data, in_eeprom->length);
3855 }
3856
3857 /*
3858  * Initialization
3859  */
3860
3861 static const struct eth_dev_ops bnxt_dev_ops = {
3862         .dev_infos_get = bnxt_dev_info_get_op,
3863         .dev_close = bnxt_dev_close_op,
3864         .dev_configure = bnxt_dev_configure_op,
3865         .dev_start = bnxt_dev_start_op,
3866         .dev_stop = bnxt_dev_stop_op,
3867         .dev_set_link_up = bnxt_dev_set_link_up_op,
3868         .dev_set_link_down = bnxt_dev_set_link_down_op,
3869         .stats_get = bnxt_stats_get_op,
3870         .stats_reset = bnxt_stats_reset_op,
3871         .rx_queue_setup = bnxt_rx_queue_setup_op,
3872         .rx_queue_release = bnxt_rx_queue_release_op,
3873         .tx_queue_setup = bnxt_tx_queue_setup_op,
3874         .tx_queue_release = bnxt_tx_queue_release_op,
3875         .rx_queue_intr_enable = bnxt_rx_queue_intr_enable_op,
3876         .rx_queue_intr_disable = bnxt_rx_queue_intr_disable_op,
3877         .reta_update = bnxt_reta_update_op,
3878         .reta_query = bnxt_reta_query_op,
3879         .rss_hash_update = bnxt_rss_hash_update_op,
3880         .rss_hash_conf_get = bnxt_rss_hash_conf_get_op,
3881         .link_update = bnxt_link_update_op,
3882         .promiscuous_enable = bnxt_promiscuous_enable_op,
3883         .promiscuous_disable = bnxt_promiscuous_disable_op,
3884         .allmulticast_enable = bnxt_allmulticast_enable_op,
3885         .allmulticast_disable = bnxt_allmulticast_disable_op,
3886         .mac_addr_add = bnxt_mac_addr_add_op,
3887         .mac_addr_remove = bnxt_mac_addr_remove_op,
3888         .flow_ctrl_get = bnxt_flow_ctrl_get_op,
3889         .flow_ctrl_set = bnxt_flow_ctrl_set_op,
3890         .udp_tunnel_port_add  = bnxt_udp_tunnel_port_add_op,
3891         .udp_tunnel_port_del  = bnxt_udp_tunnel_port_del_op,
3892         .vlan_filter_set = bnxt_vlan_filter_set_op,
3893         .vlan_offload_set = bnxt_vlan_offload_set_op,
3894         .vlan_tpid_set = bnxt_vlan_tpid_set_op,
3895         .vlan_pvid_set = bnxt_vlan_pvid_set_op,
3896         .mtu_set = bnxt_mtu_set_op,
3897         .mac_addr_set = bnxt_set_default_mac_addr_op,
3898         .xstats_get = bnxt_dev_xstats_get_op,
3899         .xstats_get_names = bnxt_dev_xstats_get_names_op,
3900         .xstats_reset = bnxt_dev_xstats_reset_op,
3901         .fw_version_get = bnxt_fw_version_get,
3902         .set_mc_addr_list = bnxt_dev_set_mc_addr_list_op,
3903         .rxq_info_get = bnxt_rxq_info_get_op,
3904         .txq_info_get = bnxt_txq_info_get_op,
3905         .rx_burst_mode_get = bnxt_rx_burst_mode_get,
3906         .tx_burst_mode_get = bnxt_tx_burst_mode_get,
3907         .dev_led_on = bnxt_dev_led_on_op,
3908         .dev_led_off = bnxt_dev_led_off_op,
3909         .rx_queue_start = bnxt_rx_queue_start,
3910         .rx_queue_stop = bnxt_rx_queue_stop,
3911         .tx_queue_start = bnxt_tx_queue_start,
3912         .tx_queue_stop = bnxt_tx_queue_stop,
3913         .flow_ops_get = bnxt_flow_ops_get_op,
3914         .dev_supported_ptypes_get = bnxt_dev_supported_ptypes_get_op,
3915         .get_eeprom_length    = bnxt_get_eeprom_length_op,
3916         .get_eeprom           = bnxt_get_eeprom_op,
3917         .set_eeprom           = bnxt_set_eeprom_op,
3918         .timesync_enable      = bnxt_timesync_enable,
3919         .timesync_disable     = bnxt_timesync_disable,
3920         .timesync_read_time   = bnxt_timesync_read_time,
3921         .timesync_write_time   = bnxt_timesync_write_time,
3922         .timesync_adjust_time = bnxt_timesync_adjust_time,
3923         .timesync_read_rx_timestamp = bnxt_timesync_read_rx_timestamp,
3924         .timesync_read_tx_timestamp = bnxt_timesync_read_tx_timestamp,
3925 };
3926
3927 static uint32_t bnxt_map_reset_regs(struct bnxt *bp, uint32_t reg)
3928 {
3929         uint32_t offset;
3930
3931         /* Only pre-map the reset GRC registers using window 3 */
3932         rte_write32(reg & 0xfffff000, (uint8_t *)bp->bar0 +
3933                     BNXT_GRCPF_REG_WINDOW_BASE_OUT + 8);
3934
3935         offset = BNXT_GRCP_WINDOW_3_BASE + (reg & 0xffc);
3936
3937         return offset;
3938 }
3939
3940 int bnxt_map_fw_health_status_regs(struct bnxt *bp)
3941 {
3942         struct bnxt_error_recovery_info *info = bp->recovery_info;
3943         uint32_t reg_base = 0xffffffff;
3944         int i;
3945
3946         /* Only pre-map the monitoring GRC registers using window 2 */
3947         for (i = 0; i < BNXT_FW_STATUS_REG_CNT; i++) {
3948                 uint32_t reg = info->status_regs[i];
3949
3950                 if (BNXT_FW_STATUS_REG_TYPE(reg) != BNXT_FW_STATUS_REG_TYPE_GRC)
3951                         continue;
3952
3953                 if (reg_base == 0xffffffff)
3954                         reg_base = reg & 0xfffff000;
3955                 if ((reg & 0xfffff000) != reg_base)
3956                         return -ERANGE;
3957
3958                 /* Use mask 0xffc as the Lower 2 bits indicates
3959                  * address space location
3960                  */
3961                 info->mapped_status_regs[i] = BNXT_GRCP_WINDOW_2_BASE +
3962                                                 (reg & 0xffc);
3963         }
3964
3965         if (reg_base == 0xffffffff)
3966                 return 0;
3967
3968         rte_write32(reg_base, (uint8_t *)bp->bar0 +
3969                     BNXT_GRCPF_REG_WINDOW_BASE_OUT + 4);
3970
3971         return 0;
3972 }
3973
3974 static void bnxt_write_fw_reset_reg(struct bnxt *bp, uint32_t index)
3975 {
3976         struct bnxt_error_recovery_info *info = bp->recovery_info;
3977         uint32_t delay = info->delay_after_reset[index];
3978         uint32_t val = info->reset_reg_val[index];
3979         uint32_t reg = info->reset_reg[index];
3980         uint32_t type, offset;
3981         int ret;
3982
3983         type = BNXT_FW_STATUS_REG_TYPE(reg);
3984         offset = BNXT_FW_STATUS_REG_OFF(reg);
3985
3986         switch (type) {
3987         case BNXT_FW_STATUS_REG_TYPE_CFG:
3988                 ret = rte_pci_write_config(bp->pdev, &val, sizeof(val), offset);
3989                 if (ret < 0) {
3990                         PMD_DRV_LOG(ERR, "Failed to write %#x at PCI offset %#x",
3991                                     val, offset);
3992                         return;
3993                 }
3994                 break;
3995         case BNXT_FW_STATUS_REG_TYPE_GRC:
3996                 offset = bnxt_map_reset_regs(bp, offset);
3997                 rte_write32(val, (uint8_t *)bp->bar0 + offset);
3998                 break;
3999         case BNXT_FW_STATUS_REG_TYPE_BAR0:
4000                 rte_write32(val, (uint8_t *)bp->bar0 + offset);
4001                 break;
4002         }
4003         /* wait on a specific interval of time until core reset is complete */
4004         if (delay)
4005                 rte_delay_ms(delay);
4006 }
4007
4008 static void bnxt_dev_cleanup(struct bnxt *bp)
4009 {
4010         bp->eth_dev->data->dev_link.link_status = 0;
4011         bp->link_info->link_up = 0;
4012         if (bp->eth_dev->data->dev_started)
4013                 bnxt_dev_stop(bp->eth_dev);
4014
4015         bnxt_uninit_resources(bp, true);
4016 }
4017
4018 static int
4019 bnxt_check_fw_reset_done(struct bnxt *bp)
4020 {
4021         int timeout = bp->fw_reset_max_msecs;
4022         uint16_t val = 0;
4023         int rc;
4024
4025         do {
4026                 rc = rte_pci_read_config(bp->pdev, &val, sizeof(val), PCI_SUBSYSTEM_ID_OFFSET);
4027                 if (rc < 0) {
4028                         PMD_DRV_LOG(ERR, "Failed to read PCI offset 0x%x", PCI_SUBSYSTEM_ID_OFFSET);
4029                         return rc;
4030                 }
4031                 if (val != 0xffff)
4032                         break;
4033                 rte_delay_ms(1);
4034         } while (timeout--);
4035
4036         if (val == 0xffff) {
4037                 PMD_DRV_LOG(ERR, "Firmware reset aborted, PCI config space invalid\n");
4038                 return -1;
4039         }
4040
4041         return 0;
4042 }
4043
4044 static int bnxt_restore_vlan_filters(struct bnxt *bp)
4045 {
4046         struct rte_eth_dev *dev = bp->eth_dev;
4047         struct rte_vlan_filter_conf *vfc;
4048         int vidx, vbit, rc;
4049         uint16_t vlan_id;
4050
4051         for (vlan_id = 1; vlan_id <= RTE_ETHER_MAX_VLAN_ID; vlan_id++) {
4052                 vfc = &dev->data->vlan_filter_conf;
4053                 vidx = vlan_id / 64;
4054                 vbit = vlan_id % 64;
4055
4056                 /* Each bit corresponds to a VLAN id */
4057                 if (vfc->ids[vidx] & (UINT64_C(1) << vbit)) {
4058                         rc = bnxt_add_vlan_filter(bp, vlan_id);
4059                         if (rc)
4060                                 return rc;
4061                 }
4062         }
4063
4064         return 0;
4065 }
4066
4067 static int bnxt_restore_mac_filters(struct bnxt *bp)
4068 {
4069         struct rte_eth_dev *dev = bp->eth_dev;
4070         struct rte_eth_dev_info dev_info;
4071         struct rte_ether_addr *addr;
4072         uint64_t pool_mask;
4073         uint32_t pool = 0;
4074         uint32_t i;
4075         int rc;
4076
4077         if (BNXT_VF(bp) && !BNXT_VF_IS_TRUSTED(bp))
4078                 return 0;
4079
4080         rc = bnxt_dev_info_get_op(dev, &dev_info);
4081         if (rc)
4082                 return rc;
4083
4084         /* replay MAC address configuration */
4085         for (i = 1; i < dev_info.max_mac_addrs; i++) {
4086                 addr = &dev->data->mac_addrs[i];
4087
4088                 /* skip zero address */
4089                 if (rte_is_zero_ether_addr(addr))
4090                         continue;
4091
4092                 pool = 0;
4093                 pool_mask = dev->data->mac_pool_sel[i];
4094
4095                 do {
4096                         if (pool_mask & 1ULL) {
4097                                 rc = bnxt_mac_addr_add_op(dev, addr, i, pool);
4098                                 if (rc)
4099                                         return rc;
4100                         }
4101                         pool_mask >>= 1;
4102                         pool++;
4103                 } while (pool_mask);
4104         }
4105
4106         return 0;
4107 }
4108
4109 static int bnxt_restore_filters(struct bnxt *bp)
4110 {
4111         struct rte_eth_dev *dev = bp->eth_dev;
4112         int ret = 0;
4113
4114         if (dev->data->all_multicast) {
4115                 ret = bnxt_allmulticast_enable_op(dev);
4116                 if (ret)
4117                         return ret;
4118         }
4119         if (dev->data->promiscuous) {
4120                 ret = bnxt_promiscuous_enable_op(dev);
4121                 if (ret)
4122                         return ret;
4123         }
4124
4125         ret = bnxt_restore_mac_filters(bp);
4126         if (ret)
4127                 return ret;
4128
4129         ret = bnxt_restore_vlan_filters(bp);
4130         /* TODO restore other filters as well */
4131         return ret;
4132 }
4133
4134 static int bnxt_check_fw_ready(struct bnxt *bp)
4135 {
4136         int timeout = bp->fw_reset_max_msecs;
4137         int rc = 0;
4138
4139         do {
4140                 rc = bnxt_hwrm_poll_ver_get(bp);
4141                 if (rc == 0)
4142                         break;
4143                 rte_delay_ms(BNXT_FW_READY_WAIT_INTERVAL);
4144                 timeout -= BNXT_FW_READY_WAIT_INTERVAL;
4145         } while (rc && timeout > 0);
4146
4147         if (rc)
4148                 PMD_DRV_LOG(ERR, "FW is not Ready after reset\n");
4149
4150         return rc;
4151 }
4152
4153 static void bnxt_dev_recover(void *arg)
4154 {
4155         struct bnxt *bp = arg;
4156         int rc = 0;
4157
4158         pthread_mutex_lock(&bp->err_recovery_lock);
4159
4160         if (!bp->fw_reset_min_msecs) {
4161                 rc = bnxt_check_fw_reset_done(bp);
4162                 if (rc)
4163                         goto err;
4164         }
4165
4166         /* Clear Error flag so that device re-init should happen */
4167         bp->flags &= ~BNXT_FLAG_FATAL_ERROR;
4168
4169         rc = bnxt_check_fw_ready(bp);
4170         if (rc)
4171                 goto err;
4172
4173         rc = bnxt_init_resources(bp, true);
4174         if (rc) {
4175                 PMD_DRV_LOG(ERR,
4176                             "Failed to initialize resources after reset\n");
4177                 goto err;
4178         }
4179         /* clear reset flag as the device is initialized now */
4180         bp->flags &= ~BNXT_FLAG_FW_RESET;
4181
4182         rc = bnxt_dev_start_op(bp->eth_dev);
4183         if (rc) {
4184                 PMD_DRV_LOG(ERR, "Failed to start port after reset\n");
4185                 goto err_start;
4186         }
4187
4188         rc = bnxt_restore_filters(bp);
4189         if (rc)
4190                 goto err_start;
4191
4192         PMD_DRV_LOG(INFO, "Recovered from FW reset\n");
4193         pthread_mutex_unlock(&bp->err_recovery_lock);
4194
4195         return;
4196 err_start:
4197         bnxt_dev_stop(bp->eth_dev);
4198 err:
4199         bp->flags |= BNXT_FLAG_FATAL_ERROR;
4200         bnxt_uninit_resources(bp, false);
4201         pthread_mutex_unlock(&bp->err_recovery_lock);
4202         PMD_DRV_LOG(ERR, "Failed to recover from FW reset\n");
4203 }
4204
4205 void bnxt_dev_reset_and_resume(void *arg)
4206 {
4207         struct bnxt *bp = arg;
4208         uint32_t us = US_PER_MS * bp->fw_reset_min_msecs;
4209         uint16_t val = 0;
4210         int rc;
4211
4212         bnxt_dev_cleanup(bp);
4213
4214         bnxt_wait_for_device_shutdown(bp);
4215
4216         /* During some fatal firmware error conditions, the PCI config space
4217          * register 0x2e which normally contains the subsystem ID will become
4218          * 0xffff. This register will revert back to the normal value after
4219          * the chip has completed core reset. If we detect this condition,
4220          * we can poll this config register immediately for the value to revert.
4221          */
4222         if (bp->flags & BNXT_FLAG_FATAL_ERROR) {
4223                 rc = rte_pci_read_config(bp->pdev, &val, sizeof(val), PCI_SUBSYSTEM_ID_OFFSET);
4224                 if (rc < 0) {
4225                         PMD_DRV_LOG(ERR, "Failed to read PCI offset 0x%x", PCI_SUBSYSTEM_ID_OFFSET);
4226                         return;
4227                 }
4228                 if (val == 0xffff) {
4229                         bp->fw_reset_min_msecs = 0;
4230                         us = 1;
4231                 }
4232         }
4233
4234         rc = rte_eal_alarm_set(us, bnxt_dev_recover, (void *)bp);
4235         if (rc)
4236                 PMD_DRV_LOG(ERR, "Error setting recovery alarm");
4237 }
4238
4239 uint32_t bnxt_read_fw_status_reg(struct bnxt *bp, uint32_t index)
4240 {
4241         struct bnxt_error_recovery_info *info = bp->recovery_info;
4242         uint32_t reg = info->status_regs[index];
4243         uint32_t type, offset, val = 0;
4244         int ret = 0;
4245
4246         type = BNXT_FW_STATUS_REG_TYPE(reg);
4247         offset = BNXT_FW_STATUS_REG_OFF(reg);
4248
4249         switch (type) {
4250         case BNXT_FW_STATUS_REG_TYPE_CFG:
4251                 ret = rte_pci_read_config(bp->pdev, &val, sizeof(val), offset);
4252                 if (ret < 0)
4253                         PMD_DRV_LOG(ERR, "Failed to read PCI offset %#x",
4254                                     offset);
4255                 break;
4256         case BNXT_FW_STATUS_REG_TYPE_GRC:
4257                 offset = info->mapped_status_regs[index];
4258                 /* FALLTHROUGH */
4259         case BNXT_FW_STATUS_REG_TYPE_BAR0:
4260                 val = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
4261                                        offset));
4262                 break;
4263         }
4264
4265         return val;
4266 }
4267
4268 static int bnxt_fw_reset_all(struct bnxt *bp)
4269 {
4270         struct bnxt_error_recovery_info *info = bp->recovery_info;
4271         uint32_t i;
4272         int rc = 0;
4273
4274         if (info->flags & BNXT_FLAG_ERROR_RECOVERY_HOST) {
4275                 /* Reset through master function driver */
4276                 for (i = 0; i < info->reg_array_cnt; i++)
4277                         bnxt_write_fw_reset_reg(bp, i);
4278                 /* Wait for time specified by FW after triggering reset */
4279                 rte_delay_ms(info->master_func_wait_period_after_reset);
4280         } else if (info->flags & BNXT_FLAG_ERROR_RECOVERY_CO_CPU) {
4281                 /* Reset with the help of Kong processor */
4282                 rc = bnxt_hwrm_fw_reset(bp);
4283                 if (rc)
4284                         PMD_DRV_LOG(ERR, "Failed to reset FW\n");
4285         }
4286
4287         return rc;
4288 }
4289
4290 static void bnxt_fw_reset_cb(void *arg)
4291 {
4292         struct bnxt *bp = arg;
4293         struct bnxt_error_recovery_info *info = bp->recovery_info;
4294         int rc = 0;
4295
4296         /* Only Master function can do FW reset */
4297         if (bnxt_is_master_func(bp) &&
4298             bnxt_is_recovery_enabled(bp)) {
4299                 rc = bnxt_fw_reset_all(bp);
4300                 if (rc) {
4301                         PMD_DRV_LOG(ERR, "Adapter recovery failed\n");
4302                         return;
4303                 }
4304         }
4305
4306         /* if recovery method is ERROR_RECOVERY_CO_CPU, KONG will send
4307          * EXCEPTION_FATAL_ASYNC event to all the functions
4308          * (including MASTER FUNC). After receiving this Async, all the active
4309          * drivers should treat this case as FW initiated recovery
4310          */
4311         if (info->flags & BNXT_FLAG_ERROR_RECOVERY_HOST) {
4312                 bp->fw_reset_min_msecs = BNXT_MIN_FW_READY_TIMEOUT;
4313                 bp->fw_reset_max_msecs = BNXT_MAX_FW_RESET_TIMEOUT;
4314
4315                 /* To recover from error */
4316                 rte_eal_alarm_set(US_PER_MS, bnxt_dev_reset_and_resume,
4317                                   (void *)bp);
4318         }
4319 }
4320
4321 /* Driver should poll FW heartbeat, reset_counter with the frequency
4322  * advertised by FW in HWRM_ERROR_RECOVERY_QCFG.
4323  * When the driver detects heartbeat stop or change in reset_counter,
4324  * it has to trigger a reset to recover from the error condition.
4325  * A “master PF” is the function who will have the privilege to
4326  * initiate the chimp reset. The master PF will be elected by the
4327  * firmware and will be notified through async message.
4328  */
4329 static void bnxt_check_fw_health(void *arg)
4330 {
4331         struct bnxt *bp = arg;
4332         struct bnxt_error_recovery_info *info = bp->recovery_info;
4333         uint32_t val = 0, wait_msec;
4334
4335         if (!info || !bnxt_is_recovery_enabled(bp) ||
4336             is_bnxt_in_error(bp))
4337                 return;
4338
4339         val = bnxt_read_fw_status_reg(bp, BNXT_FW_HEARTBEAT_CNT_REG);
4340         if (val == info->last_heart_beat)
4341                 goto reset;
4342
4343         info->last_heart_beat = val;
4344
4345         val = bnxt_read_fw_status_reg(bp, BNXT_FW_RECOVERY_CNT_REG);
4346         if (val != info->last_reset_counter)
4347                 goto reset;
4348
4349         info->last_reset_counter = val;
4350
4351         rte_eal_alarm_set(US_PER_MS * info->driver_polling_freq,
4352                           bnxt_check_fw_health, (void *)bp);
4353
4354         return;
4355 reset:
4356         /* Stop DMA to/from device */
4357         bp->flags |= BNXT_FLAG_FATAL_ERROR;
4358         bp->flags |= BNXT_FLAG_FW_RESET;
4359
4360         bnxt_stop_rxtx(bp);
4361
4362         PMD_DRV_LOG(ERR, "Detected FW dead condition\n");
4363
4364         if (bnxt_is_master_func(bp))
4365                 wait_msec = info->master_func_wait_period;
4366         else
4367                 wait_msec = info->normal_func_wait_period;
4368
4369         rte_eal_alarm_set(US_PER_MS * wait_msec,
4370                           bnxt_fw_reset_cb, (void *)bp);
4371 }
4372
4373 void bnxt_schedule_fw_health_check(struct bnxt *bp)
4374 {
4375         uint32_t polling_freq;
4376
4377         pthread_mutex_lock(&bp->health_check_lock);
4378
4379         if (!bnxt_is_recovery_enabled(bp))
4380                 goto done;
4381
4382         if (bp->flags & BNXT_FLAG_FW_HEALTH_CHECK_SCHEDULED)
4383                 goto done;
4384
4385         polling_freq = bp->recovery_info->driver_polling_freq;
4386
4387         rte_eal_alarm_set(US_PER_MS * polling_freq,
4388                           bnxt_check_fw_health, (void *)bp);
4389         bp->flags |= BNXT_FLAG_FW_HEALTH_CHECK_SCHEDULED;
4390
4391 done:
4392         pthread_mutex_unlock(&bp->health_check_lock);
4393 }
4394
4395 static void bnxt_cancel_fw_health_check(struct bnxt *bp)
4396 {
4397         rte_eal_alarm_cancel(bnxt_check_fw_health, (void *)bp);
4398         bp->flags &= ~BNXT_FLAG_FW_HEALTH_CHECK_SCHEDULED;
4399 }
4400
4401 static bool bnxt_vf_pciid(uint16_t device_id)
4402 {
4403         switch (device_id) {
4404         case BROADCOM_DEV_ID_57304_VF:
4405         case BROADCOM_DEV_ID_57406_VF:
4406         case BROADCOM_DEV_ID_5731X_VF:
4407         case BROADCOM_DEV_ID_5741X_VF:
4408         case BROADCOM_DEV_ID_57414_VF:
4409         case BROADCOM_DEV_ID_STRATUS_NIC_VF1:
4410         case BROADCOM_DEV_ID_STRATUS_NIC_VF2:
4411         case BROADCOM_DEV_ID_58802_VF:
4412         case BROADCOM_DEV_ID_57500_VF1:
4413         case BROADCOM_DEV_ID_57500_VF2:
4414         case BROADCOM_DEV_ID_58818_VF:
4415                 /* FALLTHROUGH */
4416                 return true;
4417         default:
4418                 return false;
4419         }
4420 }
4421
4422 /* Phase 5 device */
4423 static bool bnxt_p5_device(uint16_t device_id)
4424 {
4425         switch (device_id) {
4426         case BROADCOM_DEV_ID_57508:
4427         case BROADCOM_DEV_ID_57504:
4428         case BROADCOM_DEV_ID_57502:
4429         case BROADCOM_DEV_ID_57508_MF1:
4430         case BROADCOM_DEV_ID_57504_MF1:
4431         case BROADCOM_DEV_ID_57502_MF1:
4432         case BROADCOM_DEV_ID_57508_MF2:
4433         case BROADCOM_DEV_ID_57504_MF2:
4434         case BROADCOM_DEV_ID_57502_MF2:
4435         case BROADCOM_DEV_ID_57500_VF1:
4436         case BROADCOM_DEV_ID_57500_VF2:
4437         case BROADCOM_DEV_ID_58812:
4438         case BROADCOM_DEV_ID_58814:
4439         case BROADCOM_DEV_ID_58818:
4440         case BROADCOM_DEV_ID_58818_VF:
4441                 /* FALLTHROUGH */
4442                 return true;
4443         default:
4444                 return false;
4445         }
4446 }
4447
4448 bool bnxt_stratus_device(struct bnxt *bp)
4449 {
4450         uint16_t device_id = bp->pdev->id.device_id;
4451
4452         switch (device_id) {
4453         case BROADCOM_DEV_ID_STRATUS_NIC:
4454         case BROADCOM_DEV_ID_STRATUS_NIC_VF1:
4455         case BROADCOM_DEV_ID_STRATUS_NIC_VF2:
4456                 /* FALLTHROUGH */
4457                 return true;
4458         default:
4459                 return false;
4460         }
4461 }
4462
4463 static int bnxt_map_pci_bars(struct rte_eth_dev *eth_dev)
4464 {
4465         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
4466         struct bnxt *bp = eth_dev->data->dev_private;
4467
4468         /* enable device (incl. PCI PM wakeup), and bus-mastering */
4469         bp->bar0 = (void *)pci_dev->mem_resource[0].addr;
4470         bp->doorbell_base = (void *)pci_dev->mem_resource[2].addr;
4471         if (!bp->bar0 || !bp->doorbell_base) {
4472                 PMD_DRV_LOG(ERR, "Unable to access Hardware\n");
4473                 return -ENODEV;
4474         }
4475
4476         bp->eth_dev = eth_dev;
4477         bp->pdev = pci_dev;
4478
4479         return 0;
4480 }
4481
4482 static int bnxt_alloc_ctx_mem_blk(struct bnxt *bp,
4483                                   struct bnxt_ctx_pg_info *ctx_pg,
4484                                   uint32_t mem_size,
4485                                   const char *suffix,
4486                                   uint16_t idx)
4487 {
4488         struct bnxt_ring_mem_info *rmem = &ctx_pg->ring_mem;
4489         const struct rte_memzone *mz = NULL;
4490         char mz_name[RTE_MEMZONE_NAMESIZE];
4491         rte_iova_t mz_phys_addr;
4492         uint64_t valid_bits = 0;
4493         uint32_t sz;
4494         int i;
4495
4496         if (!mem_size)
4497                 return 0;
4498
4499         rmem->nr_pages = RTE_ALIGN_MUL_CEIL(mem_size, BNXT_PAGE_SIZE) /
4500                          BNXT_PAGE_SIZE;
4501         rmem->page_size = BNXT_PAGE_SIZE;
4502         rmem->pg_arr = ctx_pg->ctx_pg_arr;
4503         rmem->dma_arr = ctx_pg->ctx_dma_arr;
4504         rmem->flags = BNXT_RMEM_VALID_PTE_FLAG;
4505
4506         valid_bits = PTU_PTE_VALID;
4507
4508         if (rmem->nr_pages > 1) {
4509                 snprintf(mz_name, RTE_MEMZONE_NAMESIZE,
4510                          "bnxt_ctx_pg_tbl%s_%x_%d",
4511                          suffix, idx, bp->eth_dev->data->port_id);
4512                 mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0;
4513                 mz = rte_memzone_lookup(mz_name);
4514                 if (!mz) {
4515                         mz = rte_memzone_reserve_aligned(mz_name,
4516                                                 rmem->nr_pages * 8,
4517                                                 SOCKET_ID_ANY,
4518                                                 RTE_MEMZONE_2MB |
4519                                                 RTE_MEMZONE_SIZE_HINT_ONLY |
4520                                                 RTE_MEMZONE_IOVA_CONTIG,
4521                                                 BNXT_PAGE_SIZE);
4522                         if (mz == NULL)
4523                                 return -ENOMEM;
4524                 }
4525
4526                 memset(mz->addr, 0, mz->len);
4527                 mz_phys_addr = mz->iova;
4528
4529                 rmem->pg_tbl = mz->addr;
4530                 rmem->pg_tbl_map = mz_phys_addr;
4531                 rmem->pg_tbl_mz = mz;
4532         }
4533
4534         snprintf(mz_name, RTE_MEMZONE_NAMESIZE, "bnxt_ctx_%s_%x_%d",
4535                  suffix, idx, bp->eth_dev->data->port_id);
4536         mz = rte_memzone_lookup(mz_name);
4537         if (!mz) {
4538                 mz = rte_memzone_reserve_aligned(mz_name,
4539                                                  mem_size,
4540                                                  SOCKET_ID_ANY,
4541                                                  RTE_MEMZONE_1GB |
4542                                                  RTE_MEMZONE_SIZE_HINT_ONLY |
4543                                                  RTE_MEMZONE_IOVA_CONTIG,
4544                                                  BNXT_PAGE_SIZE);
4545                 if (mz == NULL)
4546                         return -ENOMEM;
4547         }
4548
4549         memset(mz->addr, 0, mz->len);
4550         mz_phys_addr = mz->iova;
4551
4552         for (sz = 0, i = 0; sz < mem_size; sz += BNXT_PAGE_SIZE, i++) {
4553                 rmem->pg_arr[i] = ((char *)mz->addr) + sz;
4554                 rmem->dma_arr[i] = mz_phys_addr + sz;
4555
4556                 if (rmem->nr_pages > 1) {
4557                         if (i == rmem->nr_pages - 2 &&
4558                             (rmem->flags & BNXT_RMEM_RING_PTE_FLAG))
4559                                 valid_bits |= PTU_PTE_NEXT_TO_LAST;
4560                         else if (i == rmem->nr_pages - 1 &&
4561                                  (rmem->flags & BNXT_RMEM_RING_PTE_FLAG))
4562                                 valid_bits |= PTU_PTE_LAST;
4563
4564                         rmem->pg_tbl[i] = rte_cpu_to_le_64(rmem->dma_arr[i] |
4565                                                            valid_bits);
4566                 }
4567         }
4568
4569         rmem->mz = mz;
4570         if (rmem->vmem_size)
4571                 rmem->vmem = (void **)mz->addr;
4572         rmem->dma_arr[0] = mz_phys_addr;
4573         return 0;
4574 }
4575
4576 static void bnxt_free_ctx_mem(struct bnxt *bp)
4577 {
4578         int i;
4579
4580         if (!bp->ctx || !(bp->ctx->flags & BNXT_CTX_FLAG_INITED))
4581                 return;
4582
4583         bp->ctx->flags &= ~BNXT_CTX_FLAG_INITED;
4584         rte_memzone_free(bp->ctx->qp_mem.ring_mem.mz);
4585         rte_memzone_free(bp->ctx->srq_mem.ring_mem.mz);
4586         rte_memzone_free(bp->ctx->cq_mem.ring_mem.mz);
4587         rte_memzone_free(bp->ctx->vnic_mem.ring_mem.mz);
4588         rte_memzone_free(bp->ctx->stat_mem.ring_mem.mz);
4589         rte_memzone_free(bp->ctx->qp_mem.ring_mem.pg_tbl_mz);
4590         rte_memzone_free(bp->ctx->srq_mem.ring_mem.pg_tbl_mz);
4591         rte_memzone_free(bp->ctx->cq_mem.ring_mem.pg_tbl_mz);
4592         rte_memzone_free(bp->ctx->vnic_mem.ring_mem.pg_tbl_mz);
4593         rte_memzone_free(bp->ctx->stat_mem.ring_mem.pg_tbl_mz);
4594
4595         for (i = 0; i < bp->ctx->tqm_fp_rings_count + 1; i++) {
4596                 if (bp->ctx->tqm_mem[i])
4597                         rte_memzone_free(bp->ctx->tqm_mem[i]->ring_mem.mz);
4598         }
4599
4600         rte_free(bp->ctx);
4601         bp->ctx = NULL;
4602 }
4603
4604 #define bnxt_roundup(x, y)   ((((x) + ((y) - 1)) / (y)) * (y))
4605
4606 #define min_t(type, x, y) ({                    \
4607         type __min1 = (x);                      \
4608         type __min2 = (y);                      \
4609         __min1 < __min2 ? __min1 : __min2; })
4610
4611 #define max_t(type, x, y) ({                    \
4612         type __max1 = (x);                      \
4613         type __max2 = (y);                      \
4614         __max1 > __max2 ? __max1 : __max2; })
4615
4616 #define clamp_t(type, _x, min, max)     min_t(type, max_t(type, _x, min), max)
4617
4618 int bnxt_alloc_ctx_mem(struct bnxt *bp)
4619 {
4620         struct bnxt_ctx_pg_info *ctx_pg;
4621         struct bnxt_ctx_mem_info *ctx;
4622         uint32_t mem_size, ena, entries;
4623         uint32_t entries_sp, min;
4624         int i, rc;
4625
4626         rc = bnxt_hwrm_func_backing_store_qcaps(bp);
4627         if (rc) {
4628                 PMD_DRV_LOG(ERR, "Query context mem capability failed\n");
4629                 return rc;
4630         }
4631         ctx = bp->ctx;
4632         if (!ctx || (ctx->flags & BNXT_CTX_FLAG_INITED))
4633                 return 0;
4634
4635         ctx_pg = &ctx->qp_mem;
4636         ctx_pg->entries = ctx->qp_min_qp1_entries + ctx->qp_max_l2_entries;
4637         if (ctx->qp_entry_size) {
4638                 mem_size = ctx->qp_entry_size * ctx_pg->entries;
4639                 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "qp_mem", 0);
4640                 if (rc)
4641                         return rc;
4642         }
4643
4644         ctx_pg = &ctx->srq_mem;
4645         ctx_pg->entries = ctx->srq_max_l2_entries;
4646         if (ctx->srq_entry_size) {
4647                 mem_size = ctx->srq_entry_size * ctx_pg->entries;
4648                 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "srq_mem", 0);
4649                 if (rc)
4650                         return rc;
4651         }
4652
4653         ctx_pg = &ctx->cq_mem;
4654         ctx_pg->entries = ctx->cq_max_l2_entries;
4655         if (ctx->cq_entry_size) {
4656                 mem_size = ctx->cq_entry_size * ctx_pg->entries;
4657                 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "cq_mem", 0);
4658                 if (rc)
4659                         return rc;
4660         }
4661
4662         ctx_pg = &ctx->vnic_mem;
4663         ctx_pg->entries = ctx->vnic_max_vnic_entries +
4664                 ctx->vnic_max_ring_table_entries;
4665         if (ctx->vnic_entry_size) {
4666                 mem_size = ctx->vnic_entry_size * ctx_pg->entries;
4667                 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "vnic_mem", 0);
4668                 if (rc)
4669                         return rc;
4670         }
4671
4672         ctx_pg = &ctx->stat_mem;
4673         ctx_pg->entries = ctx->stat_max_entries;
4674         if (ctx->stat_entry_size) {
4675                 mem_size = ctx->stat_entry_size * ctx_pg->entries;
4676                 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "stat_mem", 0);
4677                 if (rc)
4678                         return rc;
4679         }
4680
4681         min = ctx->tqm_min_entries_per_ring;
4682
4683         entries_sp = ctx->qp_max_l2_entries +
4684                      ctx->vnic_max_vnic_entries +
4685                      2 * ctx->qp_min_qp1_entries + min;
4686         entries_sp = bnxt_roundup(entries_sp, ctx->tqm_entries_multiple);
4687
4688         entries = ctx->qp_max_l2_entries + ctx->qp_min_qp1_entries;
4689         entries = bnxt_roundup(entries, ctx->tqm_entries_multiple);
4690         entries = clamp_t(uint32_t, entries, min,
4691                           ctx->tqm_max_entries_per_ring);
4692         for (i = 0, ena = 0; i < ctx->tqm_fp_rings_count + 1; i++) {
4693                 /* i=0 is for TQM_SP. i=1 to i=8 applies to RING0 to RING7.
4694                  * i > 8 is other ext rings.
4695                  */
4696                 ctx_pg = ctx->tqm_mem[i];
4697                 ctx_pg->entries = i ? entries : entries_sp;
4698                 if (ctx->tqm_entry_size) {
4699                         mem_size = ctx->tqm_entry_size * ctx_pg->entries;
4700                         rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size,
4701                                                     "tqm_mem", i);
4702                         if (rc)
4703                                 return rc;
4704                 }
4705                 if (i < BNXT_MAX_TQM_LEGACY_RINGS)
4706                         ena |= HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_SP << i;
4707                 else
4708                         ena |= HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_RING8;
4709         }
4710
4711         ena |= FUNC_BACKING_STORE_CFG_INPUT_DFLT_ENABLES;
4712         rc = bnxt_hwrm_func_backing_store_cfg(bp, ena);
4713         if (rc)
4714                 PMD_DRV_LOG(ERR,
4715                             "Failed to configure context mem: rc = %d\n", rc);
4716         else
4717                 ctx->flags |= BNXT_CTX_FLAG_INITED;
4718
4719         return rc;
4720 }
4721
4722 static int bnxt_alloc_stats_mem(struct bnxt *bp)
4723 {
4724         struct rte_pci_device *pci_dev = bp->pdev;
4725         char mz_name[RTE_MEMZONE_NAMESIZE];
4726         const struct rte_memzone *mz = NULL;
4727         uint32_t total_alloc_len;
4728         rte_iova_t mz_phys_addr;
4729
4730         if (pci_dev->id.device_id == BROADCOM_DEV_ID_NS2)
4731                 return 0;
4732
4733         snprintf(mz_name, RTE_MEMZONE_NAMESIZE,
4734                  "bnxt_" PCI_PRI_FMT "-%s", pci_dev->addr.domain,
4735                  pci_dev->addr.bus, pci_dev->addr.devid,
4736                  pci_dev->addr.function, "rx_port_stats");
4737         mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0;
4738         mz = rte_memzone_lookup(mz_name);
4739         total_alloc_len =
4740                 RTE_CACHE_LINE_ROUNDUP(sizeof(struct rx_port_stats) +
4741                                        sizeof(struct rx_port_stats_ext) + 512);
4742         if (!mz) {
4743                 mz = rte_memzone_reserve(mz_name, total_alloc_len,
4744                                          SOCKET_ID_ANY,
4745                                          RTE_MEMZONE_2MB |
4746                                          RTE_MEMZONE_SIZE_HINT_ONLY |
4747                                          RTE_MEMZONE_IOVA_CONTIG);
4748                 if (mz == NULL)
4749                         return -ENOMEM;
4750         }
4751         memset(mz->addr, 0, mz->len);
4752         mz_phys_addr = mz->iova;
4753
4754         bp->rx_mem_zone = (const void *)mz;
4755         bp->hw_rx_port_stats = mz->addr;
4756         bp->hw_rx_port_stats_map = mz_phys_addr;
4757
4758         snprintf(mz_name, RTE_MEMZONE_NAMESIZE,
4759                  "bnxt_" PCI_PRI_FMT "-%s", pci_dev->addr.domain,
4760                  pci_dev->addr.bus, pci_dev->addr.devid,
4761                  pci_dev->addr.function, "tx_port_stats");
4762         mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0;
4763         mz = rte_memzone_lookup(mz_name);
4764         total_alloc_len =
4765                 RTE_CACHE_LINE_ROUNDUP(sizeof(struct tx_port_stats) +
4766                                        sizeof(struct tx_port_stats_ext) + 512);
4767         if (!mz) {
4768                 mz = rte_memzone_reserve(mz_name,
4769                                          total_alloc_len,
4770                                          SOCKET_ID_ANY,
4771                                          RTE_MEMZONE_2MB |
4772                                          RTE_MEMZONE_SIZE_HINT_ONLY |
4773                                          RTE_MEMZONE_IOVA_CONTIG);
4774                 if (mz == NULL)
4775                         return -ENOMEM;
4776         }
4777         memset(mz->addr, 0, mz->len);
4778         mz_phys_addr = mz->iova;
4779
4780         bp->tx_mem_zone = (const void *)mz;
4781         bp->hw_tx_port_stats = mz->addr;
4782         bp->hw_tx_port_stats_map = mz_phys_addr;
4783         bp->flags |= BNXT_FLAG_PORT_STATS;
4784
4785         /* Display extended statistics if FW supports it */
4786         if (bp->hwrm_spec_code < HWRM_SPEC_CODE_1_8_4 ||
4787             bp->hwrm_spec_code == HWRM_SPEC_CODE_1_9_0 ||
4788             !(bp->flags & BNXT_FLAG_EXT_STATS_SUPPORTED))
4789                 return 0;
4790
4791         bp->hw_rx_port_stats_ext = (void *)
4792                 ((uint8_t *)bp->hw_rx_port_stats +
4793                  sizeof(struct rx_port_stats));
4794         bp->hw_rx_port_stats_ext_map = bp->hw_rx_port_stats_map +
4795                 sizeof(struct rx_port_stats);
4796         bp->flags |= BNXT_FLAG_EXT_RX_PORT_STATS;
4797
4798         if (bp->hwrm_spec_code < HWRM_SPEC_CODE_1_9_2 ||
4799             bp->flags & BNXT_FLAG_EXT_STATS_SUPPORTED) {
4800                 bp->hw_tx_port_stats_ext = (void *)
4801                         ((uint8_t *)bp->hw_tx_port_stats +
4802                          sizeof(struct tx_port_stats));
4803                 bp->hw_tx_port_stats_ext_map =
4804                         bp->hw_tx_port_stats_map +
4805                         sizeof(struct tx_port_stats);
4806                 bp->flags |= BNXT_FLAG_EXT_TX_PORT_STATS;
4807         }
4808
4809         return 0;
4810 }
4811
4812 static int bnxt_setup_mac_addr(struct rte_eth_dev *eth_dev)
4813 {
4814         struct bnxt *bp = eth_dev->data->dev_private;
4815         int rc = 0;
4816
4817         eth_dev->data->mac_addrs = rte_zmalloc("bnxt_mac_addr_tbl",
4818                                                RTE_ETHER_ADDR_LEN *
4819                                                bp->max_l2_ctx,
4820                                                0);
4821         if (eth_dev->data->mac_addrs == NULL) {
4822                 PMD_DRV_LOG(ERR, "Failed to alloc MAC addr tbl\n");
4823                 return -ENOMEM;
4824         }
4825
4826         if (!BNXT_HAS_DFLT_MAC_SET(bp)) {
4827                 if (BNXT_PF(bp))
4828                         return -EINVAL;
4829
4830                 /* Generate a random MAC address, if none was assigned by PF */
4831                 PMD_DRV_LOG(INFO, "VF MAC address not assigned by Host PF\n");
4832                 bnxt_eth_hw_addr_random(bp->mac_addr);
4833                 PMD_DRV_LOG(INFO,
4834                             "Assign random MAC:%02X:%02X:%02X:%02X:%02X:%02X\n",
4835                             bp->mac_addr[0], bp->mac_addr[1], bp->mac_addr[2],
4836                             bp->mac_addr[3], bp->mac_addr[4], bp->mac_addr[5]);
4837
4838                 rc = bnxt_hwrm_set_mac(bp);
4839                 if (rc)
4840                         return rc;
4841         }
4842
4843         /* Copy the permanent MAC from the FUNC_QCAPS response */
4844         memcpy(&eth_dev->data->mac_addrs[0], bp->mac_addr, RTE_ETHER_ADDR_LEN);
4845
4846         return rc;
4847 }
4848
4849 static int bnxt_restore_dflt_mac(struct bnxt *bp)
4850 {
4851         int rc = 0;
4852
4853         /* MAC is already configured in FW */
4854         if (BNXT_HAS_DFLT_MAC_SET(bp))
4855                 return 0;
4856
4857         /* Restore the old MAC configured */
4858         rc = bnxt_hwrm_set_mac(bp);
4859         if (rc)
4860                 PMD_DRV_LOG(ERR, "Failed to restore MAC address\n");
4861
4862         return rc;
4863 }
4864
4865 static void bnxt_config_vf_req_fwd(struct bnxt *bp)
4866 {
4867         if (!BNXT_PF(bp))
4868                 return;
4869
4870         memset(bp->pf->vf_req_fwd, 0, sizeof(bp->pf->vf_req_fwd));
4871
4872         if (!(bp->fw_cap & BNXT_FW_CAP_LINK_ADMIN))
4873                 BNXT_HWRM_CMD_TO_FORWARD(HWRM_PORT_PHY_QCFG);
4874         BNXT_HWRM_CMD_TO_FORWARD(HWRM_FUNC_CFG);
4875         BNXT_HWRM_CMD_TO_FORWARD(HWRM_FUNC_VF_CFG);
4876         BNXT_HWRM_CMD_TO_FORWARD(HWRM_CFA_L2_FILTER_ALLOC);
4877         BNXT_HWRM_CMD_TO_FORWARD(HWRM_OEM_CMD);
4878 }
4879
4880 uint16_t
4881 bnxt_get_svif(uint16_t port_id, bool func_svif,
4882               enum bnxt_ulp_intf_type type)
4883 {
4884         struct rte_eth_dev *eth_dev;
4885         struct bnxt *bp;
4886
4887         eth_dev = &rte_eth_devices[port_id];
4888         if (BNXT_ETH_DEV_IS_REPRESENTOR(eth_dev)) {
4889                 struct bnxt_representor *vfr = eth_dev->data->dev_private;
4890                 if (!vfr)
4891                         return 0;
4892
4893                 if (type == BNXT_ULP_INTF_TYPE_VF_REP)
4894                         return vfr->svif;
4895
4896                 eth_dev = vfr->parent_dev;
4897         }
4898
4899         bp = eth_dev->data->dev_private;
4900
4901         return func_svif ? bp->func_svif : bp->port_svif;
4902 }
4903
4904 uint16_t
4905 bnxt_get_vnic_id(uint16_t port, enum bnxt_ulp_intf_type type)
4906 {
4907         struct rte_eth_dev *eth_dev;
4908         struct bnxt_vnic_info *vnic;
4909         struct bnxt *bp;
4910
4911         eth_dev = &rte_eth_devices[port];
4912         if (BNXT_ETH_DEV_IS_REPRESENTOR(eth_dev)) {
4913                 struct bnxt_representor *vfr = eth_dev->data->dev_private;
4914                 if (!vfr)
4915                         return 0;
4916
4917                 if (type == BNXT_ULP_INTF_TYPE_VF_REP)
4918                         return vfr->dflt_vnic_id;
4919
4920                 eth_dev = vfr->parent_dev;
4921         }
4922
4923         bp = eth_dev->data->dev_private;
4924
4925         vnic = BNXT_GET_DEFAULT_VNIC(bp);
4926
4927         return vnic->fw_vnic_id;
4928 }
4929
4930 uint16_t
4931 bnxt_get_fw_func_id(uint16_t port, enum bnxt_ulp_intf_type type)
4932 {
4933         struct rte_eth_dev *eth_dev;
4934         struct bnxt *bp;
4935
4936         eth_dev = &rte_eth_devices[port];
4937         if (BNXT_ETH_DEV_IS_REPRESENTOR(eth_dev)) {
4938                 struct bnxt_representor *vfr = eth_dev->data->dev_private;
4939                 if (!vfr)
4940                         return 0;
4941
4942                 if (type == BNXT_ULP_INTF_TYPE_VF_REP)
4943                         return vfr->fw_fid;
4944
4945                 eth_dev = vfr->parent_dev;
4946         }
4947
4948         bp = eth_dev->data->dev_private;
4949
4950         return bp->fw_fid;
4951 }
4952
4953 enum bnxt_ulp_intf_type
4954 bnxt_get_interface_type(uint16_t port)
4955 {
4956         struct rte_eth_dev *eth_dev;
4957         struct bnxt *bp;
4958
4959         eth_dev = &rte_eth_devices[port];
4960         if (BNXT_ETH_DEV_IS_REPRESENTOR(eth_dev))
4961                 return BNXT_ULP_INTF_TYPE_VF_REP;
4962
4963         bp = eth_dev->data->dev_private;
4964         if (BNXT_PF(bp))
4965                 return BNXT_ULP_INTF_TYPE_PF;
4966         else if (BNXT_VF_IS_TRUSTED(bp))
4967                 return BNXT_ULP_INTF_TYPE_TRUSTED_VF;
4968         else if (BNXT_VF(bp))
4969                 return BNXT_ULP_INTF_TYPE_VF;
4970
4971         return BNXT_ULP_INTF_TYPE_INVALID;
4972 }
4973
4974 uint16_t
4975 bnxt_get_phy_port_id(uint16_t port_id)
4976 {
4977         struct bnxt_representor *vfr;
4978         struct rte_eth_dev *eth_dev;
4979         struct bnxt *bp;
4980
4981         eth_dev = &rte_eth_devices[port_id];
4982         if (BNXT_ETH_DEV_IS_REPRESENTOR(eth_dev)) {
4983                 vfr = eth_dev->data->dev_private;
4984                 if (!vfr)
4985                         return 0;
4986
4987                 eth_dev = vfr->parent_dev;
4988         }
4989
4990         bp = eth_dev->data->dev_private;
4991
4992         return BNXT_PF(bp) ? bp->pf->port_id : bp->parent->port_id;
4993 }
4994
4995 uint16_t
4996 bnxt_get_parif(uint16_t port_id, enum bnxt_ulp_intf_type type)
4997 {
4998         struct rte_eth_dev *eth_dev;
4999         struct bnxt *bp;
5000
5001         eth_dev = &rte_eth_devices[port_id];
5002         if (BNXT_ETH_DEV_IS_REPRESENTOR(eth_dev)) {
5003                 struct bnxt_representor *vfr = eth_dev->data->dev_private;
5004                 if (!vfr)
5005                         return 0;
5006
5007                 if (type == BNXT_ULP_INTF_TYPE_VF_REP)
5008                         return vfr->fw_fid - 1;
5009
5010                 eth_dev = vfr->parent_dev;
5011         }
5012
5013         bp = eth_dev->data->dev_private;
5014
5015         return BNXT_PF(bp) ? bp->fw_fid - 1 : bp->parent->fid - 1;
5016 }
5017
5018 uint16_t
5019 bnxt_get_vport(uint16_t port_id)
5020 {
5021         return (1 << bnxt_get_phy_port_id(port_id));
5022 }
5023
5024 static void bnxt_alloc_error_recovery_info(struct bnxt *bp)
5025 {
5026         struct bnxt_error_recovery_info *info = bp->recovery_info;
5027
5028         if (info) {
5029                 if (!(bp->fw_cap & BNXT_FW_CAP_HCOMM_FW_STATUS))
5030                         memset(info, 0, sizeof(*info));
5031                 return;
5032         }
5033
5034         if (!(bp->fw_cap & BNXT_FW_CAP_ERROR_RECOVERY))
5035                 return;
5036
5037         info = rte_zmalloc("bnxt_hwrm_error_recovery_qcfg",
5038                            sizeof(*info), 0);
5039         if (!info)
5040                 bp->fw_cap &= ~BNXT_FW_CAP_ERROR_RECOVERY;
5041
5042         bp->recovery_info = info;
5043 }
5044
5045 static void bnxt_check_fw_status(struct bnxt *bp)
5046 {
5047         uint32_t fw_status;
5048
5049         if (!(bp->recovery_info &&
5050               (bp->fw_cap & BNXT_FW_CAP_HCOMM_FW_STATUS)))
5051                 return;
5052
5053         fw_status = bnxt_read_fw_status_reg(bp, BNXT_FW_STATUS_REG);
5054         if (fw_status != BNXT_FW_STATUS_HEALTHY)
5055                 PMD_DRV_LOG(ERR, "Firmware not responding, status: %#x\n",
5056                             fw_status);
5057 }
5058
5059 static int bnxt_map_hcomm_fw_status_reg(struct bnxt *bp)
5060 {
5061         struct bnxt_error_recovery_info *info = bp->recovery_info;
5062         uint32_t status_loc;
5063         uint32_t sig_ver;
5064
5065         rte_write32(HCOMM_STATUS_STRUCT_LOC, (uint8_t *)bp->bar0 +
5066                     BNXT_GRCPF_REG_WINDOW_BASE_OUT + 4);
5067         sig_ver = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
5068                                    BNXT_GRCP_WINDOW_2_BASE +
5069                                    offsetof(struct hcomm_status,
5070                                             sig_ver)));
5071         /* If the signature is absent, then FW does not support this feature */
5072         if ((sig_ver & HCOMM_STATUS_SIGNATURE_MASK) !=
5073             HCOMM_STATUS_SIGNATURE_VAL)
5074                 return 0;
5075
5076         if (!info) {
5077                 info = rte_zmalloc("bnxt_hwrm_error_recovery_qcfg",
5078                                    sizeof(*info), 0);
5079                 if (!info)
5080                         return -ENOMEM;
5081                 bp->recovery_info = info;
5082         } else {
5083                 memset(info, 0, sizeof(*info));
5084         }
5085
5086         status_loc = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
5087                                       BNXT_GRCP_WINDOW_2_BASE +
5088                                       offsetof(struct hcomm_status,
5089                                                fw_status_loc)));
5090
5091         /* Only pre-map the FW health status GRC register */
5092         if (BNXT_FW_STATUS_REG_TYPE(status_loc) != BNXT_FW_STATUS_REG_TYPE_GRC)
5093                 return 0;
5094
5095         info->status_regs[BNXT_FW_STATUS_REG] = status_loc;
5096         info->mapped_status_regs[BNXT_FW_STATUS_REG] =
5097                 BNXT_GRCP_WINDOW_2_BASE + (status_loc & BNXT_GRCP_OFFSET_MASK);
5098
5099         rte_write32((status_loc & BNXT_GRCP_BASE_MASK), (uint8_t *)bp->bar0 +
5100                     BNXT_GRCPF_REG_WINDOW_BASE_OUT + 4);
5101
5102         bp->fw_cap |= BNXT_FW_CAP_HCOMM_FW_STATUS;
5103
5104         return 0;
5105 }
5106
5107 /* This function gets the FW version along with the
5108  * capabilities(MAX and current) of the function, vnic,
5109  * error recovery, phy and other chip related info
5110  */
5111 static int bnxt_get_config(struct bnxt *bp)
5112 {
5113         uint16_t mtu;
5114         int rc = 0;
5115
5116         bp->fw_cap = 0;
5117
5118         rc = bnxt_map_hcomm_fw_status_reg(bp);
5119         if (rc)
5120                 return rc;
5121
5122         rc = bnxt_hwrm_ver_get(bp, DFLT_HWRM_CMD_TIMEOUT);
5123         if (rc) {
5124                 bnxt_check_fw_status(bp);
5125                 return rc;
5126         }
5127
5128         rc = bnxt_hwrm_func_reset(bp);
5129         if (rc)
5130                 return -EIO;
5131
5132         rc = bnxt_hwrm_vnic_qcaps(bp);
5133         if (rc)
5134                 return rc;
5135
5136         rc = bnxt_hwrm_queue_qportcfg(bp);
5137         if (rc)
5138                 return rc;
5139
5140         /* Get the MAX capabilities for this function.
5141          * This function also allocates context memory for TQM rings and
5142          * informs the firmware about this allocated backing store memory.
5143          */
5144         rc = bnxt_hwrm_func_qcaps(bp);
5145         if (rc)
5146                 return rc;
5147
5148         rc = bnxt_hwrm_func_qcfg(bp, &mtu);
5149         if (rc)
5150                 return rc;
5151
5152         rc = bnxt_hwrm_cfa_adv_flow_mgmt_qcaps(bp);
5153         if (rc)
5154                 return rc;
5155
5156         bnxt_hwrm_port_mac_qcfg(bp);
5157
5158         bnxt_hwrm_parent_pf_qcfg(bp);
5159
5160         bnxt_hwrm_port_phy_qcaps(bp);
5161
5162         bnxt_alloc_error_recovery_info(bp);
5163         /* Get the adapter error recovery support info */
5164         rc = bnxt_hwrm_error_recovery_qcfg(bp);
5165         if (rc)
5166                 bp->fw_cap &= ~BNXT_FW_CAP_ERROR_RECOVERY;
5167
5168         bnxt_hwrm_port_led_qcaps(bp);
5169
5170         return 0;
5171 }
5172
5173 static int
5174 bnxt_init_locks(struct bnxt *bp)
5175 {
5176         int err;
5177
5178         err = pthread_mutex_init(&bp->flow_lock, NULL);
5179         if (err) {
5180                 PMD_DRV_LOG(ERR, "Unable to initialize flow_lock\n");
5181                 return err;
5182         }
5183
5184         err = pthread_mutex_init(&bp->def_cp_lock, NULL);
5185         if (err) {
5186                 PMD_DRV_LOG(ERR, "Unable to initialize def_cp_lock\n");
5187                 return err;
5188         }
5189
5190         err = pthread_mutex_init(&bp->health_check_lock, NULL);
5191         if (err) {
5192                 PMD_DRV_LOG(ERR, "Unable to initialize health_check_lock\n");
5193                 return err;
5194         }
5195
5196         err = pthread_mutex_init(&bp->err_recovery_lock, NULL);
5197         if (err)
5198                 PMD_DRV_LOG(ERR, "Unable to initialize err_recovery_lock\n");
5199
5200         return err;
5201 }
5202
5203 static int bnxt_init_resources(struct bnxt *bp, bool reconfig_dev)
5204 {
5205         int rc = 0;
5206
5207         rc = bnxt_get_config(bp);
5208         if (rc)
5209                 return rc;
5210
5211         if (!reconfig_dev) {
5212                 rc = bnxt_setup_mac_addr(bp->eth_dev);
5213                 if (rc)
5214                         return rc;
5215         } else {
5216                 rc = bnxt_restore_dflt_mac(bp);
5217                 if (rc)
5218                         return rc;
5219         }
5220
5221         bnxt_config_vf_req_fwd(bp);
5222
5223         rc = bnxt_hwrm_func_driver_register(bp);
5224         if (rc) {
5225                 PMD_DRV_LOG(ERR, "Failed to register driver");
5226                 return -EBUSY;
5227         }
5228
5229         if (BNXT_PF(bp)) {
5230                 if (bp->pdev->max_vfs) {
5231                         rc = bnxt_hwrm_allocate_vfs(bp, bp->pdev->max_vfs);
5232                         if (rc) {
5233                                 PMD_DRV_LOG(ERR, "Failed to allocate VFs\n");
5234                                 return rc;
5235                         }
5236                 } else {
5237                         rc = bnxt_hwrm_allocate_pf_only(bp);
5238                         if (rc) {
5239                                 PMD_DRV_LOG(ERR,
5240                                             "Failed to allocate PF resources");
5241                                 return rc;
5242                         }
5243                 }
5244         }
5245
5246         rc = bnxt_alloc_mem(bp, reconfig_dev);
5247         if (rc)
5248                 return rc;
5249
5250         rc = bnxt_setup_int(bp);
5251         if (rc)
5252                 return rc;
5253
5254         rc = bnxt_request_int(bp);
5255         if (rc)
5256                 return rc;
5257
5258         rc = bnxt_init_ctx_mem(bp);
5259         if (rc) {
5260                 PMD_DRV_LOG(ERR, "Failed to init adv_flow_counters\n");
5261                 return rc;
5262         }
5263
5264         return 0;
5265 }
5266
5267 static int
5268 bnxt_parse_devarg_truflow(__rte_unused const char *key,
5269                           const char *value, void *opaque_arg)
5270 {
5271         struct bnxt *bp = opaque_arg;
5272         unsigned long truflow;
5273         char *end = NULL;
5274
5275         if (!value || !opaque_arg) {
5276                 PMD_DRV_LOG(ERR,
5277                             "Invalid parameter passed to truflow devargs.\n");
5278                 return -EINVAL;
5279         }
5280
5281         truflow = strtoul(value, &end, 10);
5282         if (end == NULL || *end != '\0' ||
5283             (truflow == ULONG_MAX && errno == ERANGE)) {
5284                 PMD_DRV_LOG(ERR,
5285                             "Invalid parameter passed to truflow devargs.\n");
5286                 return -EINVAL;
5287         }
5288
5289         if (BNXT_DEVARG_TRUFLOW_INVALID(truflow)) {
5290                 PMD_DRV_LOG(ERR,
5291                             "Invalid value passed to truflow devargs.\n");
5292                 return -EINVAL;
5293         }
5294
5295         if (truflow) {
5296                 bp->flags |= BNXT_FLAG_TRUFLOW_EN;
5297                 PMD_DRV_LOG(INFO, "Host-based truflow feature enabled.\n");
5298         } else {
5299                 bp->flags &= ~BNXT_FLAG_TRUFLOW_EN;
5300                 PMD_DRV_LOG(INFO, "Host-based truflow feature disabled.\n");
5301         }
5302
5303         return 0;
5304 }
5305
5306 static int
5307 bnxt_parse_devarg_flow_xstat(__rte_unused const char *key,
5308                              const char *value, void *opaque_arg)
5309 {
5310         struct bnxt *bp = opaque_arg;
5311         unsigned long flow_xstat;
5312         char *end = NULL;
5313
5314         if (!value || !opaque_arg) {
5315                 PMD_DRV_LOG(ERR,
5316                             "Invalid parameter passed to flow_xstat devarg.\n");
5317                 return -EINVAL;
5318         }
5319
5320         flow_xstat = strtoul(value, &end, 10);
5321         if (end == NULL || *end != '\0' ||
5322             (flow_xstat == ULONG_MAX && errno == ERANGE)) {
5323                 PMD_DRV_LOG(ERR,
5324                             "Invalid parameter passed to flow_xstat devarg.\n");
5325                 return -EINVAL;
5326         }
5327
5328         if (BNXT_DEVARG_FLOW_XSTAT_INVALID(flow_xstat)) {
5329                 PMD_DRV_LOG(ERR,
5330                             "Invalid value passed to flow_xstat devarg.\n");
5331                 return -EINVAL;
5332         }
5333
5334         bp->flags |= BNXT_FLAG_FLOW_XSTATS_EN;
5335         if (BNXT_FLOW_XSTATS_EN(bp))
5336                 PMD_DRV_LOG(INFO, "flow_xstat feature enabled.\n");
5337
5338         return 0;
5339 }
5340
5341 static int
5342 bnxt_parse_devarg_max_num_kflows(__rte_unused const char *key,
5343                                         const char *value, void *opaque_arg)
5344 {
5345         struct bnxt *bp = opaque_arg;
5346         unsigned long max_num_kflows;
5347         char *end = NULL;
5348
5349         if (!value || !opaque_arg) {
5350                 PMD_DRV_LOG(ERR,
5351                         "Invalid parameter passed to max_num_kflows devarg.\n");
5352                 return -EINVAL;
5353         }
5354
5355         max_num_kflows = strtoul(value, &end, 10);
5356         if (end == NULL || *end != '\0' ||
5357                 (max_num_kflows == ULONG_MAX && errno == ERANGE)) {
5358                 PMD_DRV_LOG(ERR,
5359                         "Invalid parameter passed to max_num_kflows devarg.\n");
5360                 return -EINVAL;
5361         }
5362
5363         if (bnxt_devarg_max_num_kflow_invalid(max_num_kflows)) {
5364                 PMD_DRV_LOG(ERR,
5365                         "Invalid value passed to max_num_kflows devarg.\n");
5366                 return -EINVAL;
5367         }
5368
5369         bp->max_num_kflows = max_num_kflows;
5370         if (bp->max_num_kflows)
5371                 PMD_DRV_LOG(INFO, "max_num_kflows set as %ldK.\n",
5372                                 max_num_kflows);
5373
5374         return 0;
5375 }
5376
5377 static int
5378 bnxt_parse_devarg_rep_is_pf(__rte_unused const char *key,
5379                             const char *value, void *opaque_arg)
5380 {
5381         struct bnxt_representor *vfr_bp = opaque_arg;
5382         unsigned long rep_is_pf;
5383         char *end = NULL;
5384
5385         if (!value || !opaque_arg) {
5386                 PMD_DRV_LOG(ERR,
5387                             "Invalid parameter passed to rep_is_pf devargs.\n");
5388                 return -EINVAL;
5389         }
5390
5391         rep_is_pf = strtoul(value, &end, 10);
5392         if (end == NULL || *end != '\0' ||
5393             (rep_is_pf == ULONG_MAX && errno == ERANGE)) {
5394                 PMD_DRV_LOG(ERR,
5395                             "Invalid parameter passed to rep_is_pf devargs.\n");
5396                 return -EINVAL;
5397         }
5398
5399         if (BNXT_DEVARG_REP_IS_PF_INVALID(rep_is_pf)) {
5400                 PMD_DRV_LOG(ERR,
5401                             "Invalid value passed to rep_is_pf devargs.\n");
5402                 return -EINVAL;
5403         }
5404
5405         vfr_bp->flags |= rep_is_pf;
5406         if (BNXT_REP_PF(vfr_bp))
5407                 PMD_DRV_LOG(INFO, "PF representor\n");
5408         else
5409                 PMD_DRV_LOG(INFO, "VF representor\n");
5410
5411         return 0;
5412 }
5413
5414 static int
5415 bnxt_parse_devarg_rep_based_pf(__rte_unused const char *key,
5416                                const char *value, void *opaque_arg)
5417 {
5418         struct bnxt_representor *vfr_bp = opaque_arg;
5419         unsigned long rep_based_pf;
5420         char *end = NULL;
5421
5422         if (!value || !opaque_arg) {
5423                 PMD_DRV_LOG(ERR,
5424                             "Invalid parameter passed to rep_based_pf "
5425                             "devargs.\n");
5426                 return -EINVAL;
5427         }
5428
5429         rep_based_pf = strtoul(value, &end, 10);
5430         if (end == NULL || *end != '\0' ||
5431             (rep_based_pf == ULONG_MAX && errno == ERANGE)) {
5432                 PMD_DRV_LOG(ERR,
5433                             "Invalid parameter passed to rep_based_pf "
5434                             "devargs.\n");
5435                 return -EINVAL;
5436         }
5437
5438         if (BNXT_DEVARG_REP_BASED_PF_INVALID(rep_based_pf)) {
5439                 PMD_DRV_LOG(ERR,
5440                             "Invalid value passed to rep_based_pf devargs.\n");
5441                 return -EINVAL;
5442         }
5443
5444         vfr_bp->rep_based_pf = rep_based_pf;
5445         vfr_bp->flags |= BNXT_REP_BASED_PF_VALID;
5446
5447         PMD_DRV_LOG(INFO, "rep-based-pf = %d\n", vfr_bp->rep_based_pf);
5448
5449         return 0;
5450 }
5451
5452 static int
5453 bnxt_parse_devarg_rep_q_r2f(__rte_unused const char *key,
5454                             const char *value, void *opaque_arg)
5455 {
5456         struct bnxt_representor *vfr_bp = opaque_arg;
5457         unsigned long rep_q_r2f;
5458         char *end = NULL;
5459
5460         if (!value || !opaque_arg) {
5461                 PMD_DRV_LOG(ERR,
5462                             "Invalid parameter passed to rep_q_r2f "
5463                             "devargs.\n");
5464                 return -EINVAL;
5465         }
5466
5467         rep_q_r2f = strtoul(value, &end, 10);
5468         if (end == NULL || *end != '\0' ||
5469             (rep_q_r2f == ULONG_MAX && errno == ERANGE)) {
5470                 PMD_DRV_LOG(ERR,
5471                             "Invalid parameter passed to rep_q_r2f "
5472                             "devargs.\n");
5473                 return -EINVAL;
5474         }
5475
5476         if (BNXT_DEVARG_REP_Q_R2F_INVALID(rep_q_r2f)) {
5477                 PMD_DRV_LOG(ERR,
5478                             "Invalid value passed to rep_q_r2f devargs.\n");
5479                 return -EINVAL;
5480         }
5481
5482         vfr_bp->rep_q_r2f = rep_q_r2f;
5483         vfr_bp->flags |= BNXT_REP_Q_R2F_VALID;
5484         PMD_DRV_LOG(INFO, "rep-q-r2f = %d\n", vfr_bp->rep_q_r2f);
5485
5486         return 0;
5487 }
5488
5489 static int
5490 bnxt_parse_devarg_rep_q_f2r(__rte_unused const char *key,
5491                             const char *value, void *opaque_arg)
5492 {
5493         struct bnxt_representor *vfr_bp = opaque_arg;
5494         unsigned long rep_q_f2r;
5495         char *end = NULL;
5496
5497         if (!value || !opaque_arg) {
5498                 PMD_DRV_LOG(ERR,
5499                             "Invalid parameter passed to rep_q_f2r "
5500                             "devargs.\n");
5501                 return -EINVAL;
5502         }
5503
5504         rep_q_f2r = strtoul(value, &end, 10);
5505         if (end == NULL || *end != '\0' ||
5506             (rep_q_f2r == ULONG_MAX && errno == ERANGE)) {
5507                 PMD_DRV_LOG(ERR,
5508                             "Invalid parameter passed to rep_q_f2r "
5509                             "devargs.\n");
5510                 return -EINVAL;
5511         }
5512
5513         if (BNXT_DEVARG_REP_Q_F2R_INVALID(rep_q_f2r)) {
5514                 PMD_DRV_LOG(ERR,
5515                             "Invalid value passed to rep_q_f2r devargs.\n");
5516                 return -EINVAL;
5517         }
5518
5519         vfr_bp->rep_q_f2r = rep_q_f2r;
5520         vfr_bp->flags |= BNXT_REP_Q_F2R_VALID;
5521         PMD_DRV_LOG(INFO, "rep-q-f2r = %d\n", vfr_bp->rep_q_f2r);
5522
5523         return 0;
5524 }
5525
5526 static int
5527 bnxt_parse_devarg_rep_fc_r2f(__rte_unused const char *key,
5528                              const char *value, void *opaque_arg)
5529 {
5530         struct bnxt_representor *vfr_bp = opaque_arg;
5531         unsigned long rep_fc_r2f;
5532         char *end = NULL;
5533
5534         if (!value || !opaque_arg) {
5535                 PMD_DRV_LOG(ERR,
5536                             "Invalid parameter passed to rep_fc_r2f "
5537                             "devargs.\n");
5538                 return -EINVAL;
5539         }
5540
5541         rep_fc_r2f = strtoul(value, &end, 10);
5542         if (end == NULL || *end != '\0' ||
5543             (rep_fc_r2f == ULONG_MAX && errno == ERANGE)) {
5544                 PMD_DRV_LOG(ERR,
5545                             "Invalid parameter passed to rep_fc_r2f "
5546                             "devargs.\n");
5547                 return -EINVAL;
5548         }
5549
5550         if (BNXT_DEVARG_REP_FC_R2F_INVALID(rep_fc_r2f)) {
5551                 PMD_DRV_LOG(ERR,
5552                             "Invalid value passed to rep_fc_r2f devargs.\n");
5553                 return -EINVAL;
5554         }
5555
5556         vfr_bp->flags |= BNXT_REP_FC_R2F_VALID;
5557         vfr_bp->rep_fc_r2f = rep_fc_r2f;
5558         PMD_DRV_LOG(INFO, "rep-fc-r2f = %lu\n", rep_fc_r2f);
5559
5560         return 0;
5561 }
5562
5563 static int
5564 bnxt_parse_devarg_rep_fc_f2r(__rte_unused const char *key,
5565                              const char *value, void *opaque_arg)
5566 {
5567         struct bnxt_representor *vfr_bp = opaque_arg;
5568         unsigned long rep_fc_f2r;
5569         char *end = NULL;
5570
5571         if (!value || !opaque_arg) {
5572                 PMD_DRV_LOG(ERR,
5573                             "Invalid parameter passed to rep_fc_f2r "
5574                             "devargs.\n");
5575                 return -EINVAL;
5576         }
5577
5578         rep_fc_f2r = strtoul(value, &end, 10);
5579         if (end == NULL || *end != '\0' ||
5580             (rep_fc_f2r == ULONG_MAX && errno == ERANGE)) {
5581                 PMD_DRV_LOG(ERR,
5582                             "Invalid parameter passed to rep_fc_f2r "
5583                             "devargs.\n");
5584                 return -EINVAL;
5585         }
5586
5587         if (BNXT_DEVARG_REP_FC_F2R_INVALID(rep_fc_f2r)) {
5588                 PMD_DRV_LOG(ERR,
5589                             "Invalid value passed to rep_fc_f2r devargs.\n");
5590                 return -EINVAL;
5591         }
5592
5593         vfr_bp->flags |= BNXT_REP_FC_F2R_VALID;
5594         vfr_bp->rep_fc_f2r = rep_fc_f2r;
5595         PMD_DRV_LOG(INFO, "rep-fc-f2r = %lu\n", rep_fc_f2r);
5596
5597         return 0;
5598 }
5599
5600 static int
5601 bnxt_parse_dev_args(struct bnxt *bp, struct rte_devargs *devargs)
5602 {
5603         struct rte_kvargs *kvlist;
5604         int ret;
5605
5606         if (devargs == NULL)
5607                 return 0;
5608
5609         kvlist = rte_kvargs_parse(devargs->args, bnxt_dev_args);
5610         if (kvlist == NULL)
5611                 return -EINVAL;
5612
5613         /*
5614          * Handler for "truflow" devarg.
5615          * Invoked as for ex: "-a 0000:00:0d.0,host-based-truflow=1"
5616          */
5617         ret = rte_kvargs_process(kvlist, BNXT_DEVARG_TRUFLOW,
5618                                  bnxt_parse_devarg_truflow, bp);
5619         if (ret)
5620                 goto err;
5621
5622         /*
5623          * Handler for "flow_xstat" devarg.
5624          * Invoked as for ex: "-a 0000:00:0d.0,flow_xstat=1"
5625          */
5626         ret = rte_kvargs_process(kvlist, BNXT_DEVARG_FLOW_XSTAT,
5627                                  bnxt_parse_devarg_flow_xstat, bp);
5628         if (ret)
5629                 goto err;
5630
5631         /*
5632          * Handler for "max_num_kflows" devarg.
5633          * Invoked as for ex: "-a 000:00:0d.0,max_num_kflows=32"
5634          */
5635         ret = rte_kvargs_process(kvlist, BNXT_DEVARG_MAX_NUM_KFLOWS,
5636                                  bnxt_parse_devarg_max_num_kflows, bp);
5637         if (ret)
5638                 goto err;
5639
5640 err:
5641         rte_kvargs_free(kvlist);
5642         return ret;
5643 }
5644
5645 static int bnxt_alloc_switch_domain(struct bnxt *bp)
5646 {
5647         int rc = 0;
5648
5649         if (BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp)) {
5650                 rc = rte_eth_switch_domain_alloc(&bp->switch_domain_id);
5651                 if (rc)
5652                         PMD_DRV_LOG(ERR,
5653                                     "Failed to alloc switch domain: %d\n", rc);
5654                 else
5655                         PMD_DRV_LOG(INFO,
5656                                     "Switch domain allocated %d\n",
5657                                     bp->switch_domain_id);
5658         }
5659
5660         return rc;
5661 }
5662
5663 /* Allocate and initialize various fields in bnxt struct that
5664  * need to be allocated/destroyed only once in the lifetime of the driver
5665  */
5666 static int bnxt_drv_init(struct rte_eth_dev *eth_dev)
5667 {
5668         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
5669         struct bnxt *bp = eth_dev->data->dev_private;
5670         int rc = 0;
5671
5672         bp->flags &= ~BNXT_FLAG_RX_VECTOR_PKT_MODE;
5673
5674         if (bnxt_vf_pciid(pci_dev->id.device_id))
5675                 bp->flags |= BNXT_FLAG_VF;
5676
5677         if (bnxt_p5_device(pci_dev->id.device_id))
5678                 bp->flags |= BNXT_FLAG_CHIP_P5;
5679
5680         if (pci_dev->id.device_id == BROADCOM_DEV_ID_58802 ||
5681             pci_dev->id.device_id == BROADCOM_DEV_ID_58804 ||
5682             pci_dev->id.device_id == BROADCOM_DEV_ID_58808 ||
5683             pci_dev->id.device_id == BROADCOM_DEV_ID_58802_VF)
5684                 bp->flags |= BNXT_FLAG_STINGRAY;
5685
5686         if (BNXT_TRUFLOW_EN(bp)) {
5687                 /* extra mbuf field is required to store CFA code from mark */
5688                 static const struct rte_mbuf_dynfield bnxt_cfa_code_dynfield_desc = {
5689                         .name = RTE_PMD_BNXT_CFA_CODE_DYNFIELD_NAME,
5690                         .size = sizeof(bnxt_cfa_code_dynfield_t),
5691                         .align = __alignof__(bnxt_cfa_code_dynfield_t),
5692                 };
5693                 bnxt_cfa_code_dynfield_offset =
5694                         rte_mbuf_dynfield_register(&bnxt_cfa_code_dynfield_desc);
5695                 if (bnxt_cfa_code_dynfield_offset < 0) {
5696                         PMD_DRV_LOG(ERR,
5697                             "Failed to register mbuf field for TruFlow mark\n");
5698                         return -rte_errno;
5699                 }
5700         }
5701
5702         rc = bnxt_map_pci_bars(eth_dev);
5703         if (rc) {
5704                 PMD_DRV_LOG(ERR,
5705                             "Failed to initialize board rc: %x\n", rc);
5706                 return rc;
5707         }
5708
5709         rc = bnxt_alloc_pf_info(bp);
5710         if (rc)
5711                 return rc;
5712
5713         rc = bnxt_alloc_link_info(bp);
5714         if (rc)
5715                 return rc;
5716
5717         rc = bnxt_alloc_parent_info(bp);
5718         if (rc)
5719                 return rc;
5720
5721         rc = bnxt_alloc_hwrm_resources(bp);
5722         if (rc) {
5723                 PMD_DRV_LOG(ERR,
5724                             "Failed to allocate response buffer rc: %x\n", rc);
5725                 return rc;
5726         }
5727         rc = bnxt_alloc_leds_info(bp);
5728         if (rc)
5729                 return rc;
5730
5731         rc = bnxt_alloc_cos_queues(bp);
5732         if (rc)
5733                 return rc;
5734
5735         rc = bnxt_init_locks(bp);
5736         if (rc)
5737                 return rc;
5738
5739         rc = bnxt_alloc_switch_domain(bp);
5740         if (rc)
5741                 return rc;
5742
5743         return rc;
5744 }
5745
5746 static int
5747 bnxt_dev_init(struct rte_eth_dev *eth_dev, void *params __rte_unused)
5748 {
5749         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
5750         static int version_printed;
5751         struct bnxt *bp;
5752         int rc;
5753
5754         if (version_printed++ == 0)
5755                 PMD_DRV_LOG(INFO, "%s\n", bnxt_version);
5756
5757         eth_dev->dev_ops = &bnxt_dev_ops;
5758         eth_dev->rx_queue_count = bnxt_rx_queue_count_op;
5759         eth_dev->rx_descriptor_status = bnxt_rx_descriptor_status_op;
5760         eth_dev->tx_descriptor_status = bnxt_tx_descriptor_status_op;
5761         eth_dev->rx_pkt_burst = &bnxt_recv_pkts;
5762         eth_dev->tx_pkt_burst = &bnxt_xmit_pkts;
5763
5764         /*
5765          * For secondary processes, we don't initialise any further
5766          * as primary has already done this work.
5767          */
5768         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
5769                 return 0;
5770
5771         rte_eth_copy_pci_info(eth_dev, pci_dev);
5772         eth_dev->data->dev_flags |= RTE_ETH_DEV_AUTOFILL_QUEUE_XSTATS;
5773
5774         bp = eth_dev->data->dev_private;
5775
5776         /* Parse dev arguments passed on when starting the DPDK application. */
5777         rc = bnxt_parse_dev_args(bp, pci_dev->device.devargs);
5778         if (rc)
5779                 goto error_free;
5780
5781         rc = bnxt_drv_init(eth_dev);
5782         if (rc)
5783                 goto error_free;
5784
5785         rc = bnxt_init_resources(bp, false);
5786         if (rc)
5787                 goto error_free;
5788
5789         rc = bnxt_alloc_stats_mem(bp);
5790         if (rc)
5791                 goto error_free;
5792
5793         PMD_DRV_LOG(INFO,
5794                     DRV_MODULE_NAME "found at mem %" PRIX64 ", node addr %pM\n",
5795                     pci_dev->mem_resource[0].phys_addr,
5796                     pci_dev->mem_resource[0].addr);
5797
5798         return 0;
5799
5800 error_free:
5801         bnxt_dev_uninit(eth_dev);
5802         return rc;
5803 }
5804
5805
5806 static void bnxt_free_ctx_mem_buf(struct bnxt_ctx_mem_buf_info *ctx)
5807 {
5808         if (!ctx)
5809                 return;
5810
5811         if (ctx->va)
5812                 rte_free(ctx->va);
5813
5814         ctx->va = NULL;
5815         ctx->dma = RTE_BAD_IOVA;
5816         ctx->ctx_id = BNXT_CTX_VAL_INVAL;
5817 }
5818
5819 static void bnxt_unregister_fc_ctx_mem(struct bnxt *bp)
5820 {
5821         bnxt_hwrm_cfa_counter_cfg(bp, BNXT_DIR_RX,
5822                                   CFA_COUNTER_CFG_IN_COUNTER_TYPE_FC,
5823                                   bp->flow_stat->rx_fc_out_tbl.ctx_id,
5824                                   bp->flow_stat->max_fc,
5825                                   false);
5826
5827         bnxt_hwrm_cfa_counter_cfg(bp, BNXT_DIR_TX,
5828                                   CFA_COUNTER_CFG_IN_COUNTER_TYPE_FC,
5829                                   bp->flow_stat->tx_fc_out_tbl.ctx_id,
5830                                   bp->flow_stat->max_fc,
5831                                   false);
5832
5833         if (bp->flow_stat->rx_fc_in_tbl.ctx_id != BNXT_CTX_VAL_INVAL)
5834                 bnxt_hwrm_ctx_unrgtr(bp, bp->flow_stat->rx_fc_in_tbl.ctx_id);
5835         bp->flow_stat->rx_fc_in_tbl.ctx_id = BNXT_CTX_VAL_INVAL;
5836
5837         if (bp->flow_stat->rx_fc_out_tbl.ctx_id != BNXT_CTX_VAL_INVAL)
5838                 bnxt_hwrm_ctx_unrgtr(bp, bp->flow_stat->rx_fc_out_tbl.ctx_id);
5839         bp->flow_stat->rx_fc_out_tbl.ctx_id = BNXT_CTX_VAL_INVAL;
5840
5841         if (bp->flow_stat->tx_fc_in_tbl.ctx_id != BNXT_CTX_VAL_INVAL)
5842                 bnxt_hwrm_ctx_unrgtr(bp, bp->flow_stat->tx_fc_in_tbl.ctx_id);
5843         bp->flow_stat->tx_fc_in_tbl.ctx_id = BNXT_CTX_VAL_INVAL;
5844
5845         if (bp->flow_stat->tx_fc_out_tbl.ctx_id != BNXT_CTX_VAL_INVAL)
5846                 bnxt_hwrm_ctx_unrgtr(bp, bp->flow_stat->tx_fc_out_tbl.ctx_id);
5847         bp->flow_stat->tx_fc_out_tbl.ctx_id = BNXT_CTX_VAL_INVAL;
5848 }
5849
5850 static void bnxt_uninit_fc_ctx_mem(struct bnxt *bp)
5851 {
5852         bnxt_unregister_fc_ctx_mem(bp);
5853
5854         bnxt_free_ctx_mem_buf(&bp->flow_stat->rx_fc_in_tbl);
5855         bnxt_free_ctx_mem_buf(&bp->flow_stat->rx_fc_out_tbl);
5856         bnxt_free_ctx_mem_buf(&bp->flow_stat->tx_fc_in_tbl);
5857         bnxt_free_ctx_mem_buf(&bp->flow_stat->tx_fc_out_tbl);
5858 }
5859
5860 static void bnxt_uninit_ctx_mem(struct bnxt *bp)
5861 {
5862         if (BNXT_FLOW_XSTATS_EN(bp))
5863                 bnxt_uninit_fc_ctx_mem(bp);
5864 }
5865
5866 static void
5867 bnxt_free_error_recovery_info(struct bnxt *bp)
5868 {
5869         rte_free(bp->recovery_info);
5870         bp->recovery_info = NULL;
5871         bp->fw_cap &= ~BNXT_FW_CAP_ERROR_RECOVERY;
5872 }
5873
5874 static int
5875 bnxt_uninit_resources(struct bnxt *bp, bool reconfig_dev)
5876 {
5877         int rc;
5878
5879         bnxt_free_int(bp);
5880         bnxt_free_mem(bp, reconfig_dev);
5881
5882         bnxt_hwrm_func_buf_unrgtr(bp);
5883         if (bp->pf != NULL) {
5884                 rte_free(bp->pf->vf_req_buf);
5885                 bp->pf->vf_req_buf = NULL;
5886         }
5887
5888         rc = bnxt_hwrm_func_driver_unregister(bp, 0);
5889         bp->flags &= ~BNXT_FLAG_REGISTERED;
5890         bnxt_free_ctx_mem(bp);
5891         if (!reconfig_dev) {
5892                 bnxt_free_hwrm_resources(bp);
5893                 bnxt_free_error_recovery_info(bp);
5894         }
5895
5896         bnxt_uninit_ctx_mem(bp);
5897
5898         bnxt_free_flow_stats_info(bp);
5899         if (bp->rep_info != NULL)
5900                 bnxt_free_switch_domain(bp);
5901         bnxt_free_rep_info(bp);
5902         rte_free(bp->ptp_cfg);
5903         bp->ptp_cfg = NULL;
5904         return rc;
5905 }
5906
5907 static int
5908 bnxt_dev_uninit(struct rte_eth_dev *eth_dev)
5909 {
5910         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
5911                 return -EPERM;
5912
5913         PMD_DRV_LOG(DEBUG, "Calling Device uninit\n");
5914
5915         if (eth_dev->state != RTE_ETH_DEV_UNUSED)
5916                 bnxt_dev_close_op(eth_dev);
5917
5918         return 0;
5919 }
5920
5921 static int bnxt_pci_remove_dev_with_reps(struct rte_eth_dev *eth_dev)
5922 {
5923         struct bnxt *bp = eth_dev->data->dev_private;
5924         struct rte_eth_dev *vf_rep_eth_dev;
5925         int ret = 0, i;
5926
5927         if (!bp)
5928                 return -EINVAL;
5929
5930         for (i = 0; i < bp->num_reps; i++) {
5931                 vf_rep_eth_dev = bp->rep_info[i].vfr_eth_dev;
5932                 if (!vf_rep_eth_dev)
5933                         continue;
5934                 PMD_DRV_LOG(DEBUG, "BNXT Port:%d VFR pci remove\n",
5935                             vf_rep_eth_dev->data->port_id);
5936                 rte_eth_dev_destroy(vf_rep_eth_dev, bnxt_representor_uninit);
5937         }
5938         PMD_DRV_LOG(DEBUG, "BNXT Port:%d pci remove\n",
5939                     eth_dev->data->port_id);
5940         ret = rte_eth_dev_destroy(eth_dev, bnxt_dev_uninit);
5941
5942         return ret;
5943 }
5944
5945 static void bnxt_free_rep_info(struct bnxt *bp)
5946 {
5947         rte_free(bp->rep_info);
5948         bp->rep_info = NULL;
5949         rte_free(bp->cfa_code_map);
5950         bp->cfa_code_map = NULL;
5951 }
5952
5953 static int bnxt_init_rep_info(struct bnxt *bp)
5954 {
5955         int i = 0, rc;
5956
5957         if (bp->rep_info)
5958                 return 0;
5959
5960         bp->rep_info = rte_zmalloc("bnxt_rep_info",
5961                                    sizeof(bp->rep_info[0]) * BNXT_MAX_VF_REPS,
5962                                    0);
5963         if (!bp->rep_info) {
5964                 PMD_DRV_LOG(ERR, "Failed to alloc memory for rep info\n");
5965                 return -ENOMEM;
5966         }
5967         bp->cfa_code_map = rte_zmalloc("bnxt_cfa_code_map",
5968                                        sizeof(*bp->cfa_code_map) *
5969                                        BNXT_MAX_CFA_CODE, 0);
5970         if (!bp->cfa_code_map) {
5971                 PMD_DRV_LOG(ERR, "Failed to alloc memory for cfa_code_map\n");
5972                 bnxt_free_rep_info(bp);
5973                 return -ENOMEM;
5974         }
5975
5976         for (i = 0; i < BNXT_MAX_CFA_CODE; i++)
5977                 bp->cfa_code_map[i] = BNXT_VF_IDX_INVALID;
5978
5979         rc = pthread_mutex_init(&bp->rep_info->vfr_lock, NULL);
5980         if (rc) {
5981                 PMD_DRV_LOG(ERR, "Unable to initialize vfr_lock\n");
5982                 bnxt_free_rep_info(bp);
5983                 return rc;
5984         }
5985
5986         rc = pthread_mutex_init(&bp->rep_info->vfr_start_lock, NULL);
5987         if (rc) {
5988                 PMD_DRV_LOG(ERR, "Unable to initialize vfr_start_lock\n");
5989                 bnxt_free_rep_info(bp);
5990                 return rc;
5991         }
5992
5993         return rc;
5994 }
5995
5996 static int bnxt_rep_port_probe(struct rte_pci_device *pci_dev,
5997                                struct rte_eth_devargs *eth_da,
5998                                struct rte_eth_dev *backing_eth_dev,
5999                                const char *dev_args)
6000 {
6001         struct rte_eth_dev *vf_rep_eth_dev;
6002         char name[RTE_ETH_NAME_MAX_LEN];
6003         struct bnxt *backing_bp;
6004         uint16_t num_rep;
6005         int i, ret = 0;
6006         struct rte_kvargs *kvlist = NULL;
6007
6008         if (eth_da->type == RTE_ETH_REPRESENTOR_NONE)
6009                 return 0;
6010         if (eth_da->type != RTE_ETH_REPRESENTOR_VF) {
6011                 PMD_DRV_LOG(ERR, "unsupported representor type %d\n",
6012                             eth_da->type);
6013                 return -ENOTSUP;
6014         }
6015         num_rep = eth_da->nb_representor_ports;
6016         if (num_rep > BNXT_MAX_VF_REPS) {
6017                 PMD_DRV_LOG(ERR, "nb_representor_ports = %d > %d MAX VF REPS\n",
6018                             num_rep, BNXT_MAX_VF_REPS);
6019                 return -EINVAL;
6020         }
6021
6022         if (num_rep >= RTE_MAX_ETHPORTS) {
6023                 PMD_DRV_LOG(ERR,
6024                             "nb_representor_ports = %d > %d MAX ETHPORTS\n",
6025                             num_rep, RTE_MAX_ETHPORTS);
6026                 return -EINVAL;
6027         }
6028
6029         backing_bp = backing_eth_dev->data->dev_private;
6030
6031         if (!(BNXT_PF(backing_bp) || BNXT_VF_IS_TRUSTED(backing_bp))) {
6032                 PMD_DRV_LOG(ERR,
6033                             "Not a PF or trusted VF. No Representor support\n");
6034                 /* Returning an error is not an option.
6035                  * Applications are not handling this correctly
6036                  */
6037                 return 0;
6038         }
6039
6040         if (bnxt_init_rep_info(backing_bp))
6041                 return 0;
6042
6043         for (i = 0; i < num_rep; i++) {
6044                 struct bnxt_representor representor = {
6045                         .vf_id = eth_da->representor_ports[i],
6046                         .switch_domain_id = backing_bp->switch_domain_id,
6047                         .parent_dev = backing_eth_dev
6048                 };
6049
6050                 if (representor.vf_id >= BNXT_MAX_VF_REPS) {
6051                         PMD_DRV_LOG(ERR, "VF-Rep id %d >= %d MAX VF ID\n",
6052                                     representor.vf_id, BNXT_MAX_VF_REPS);
6053                         continue;
6054                 }
6055
6056                 /* representor port net_bdf_port */
6057                 snprintf(name, sizeof(name), "net_%s_representor_%d",
6058                          pci_dev->device.name, eth_da->representor_ports[i]);
6059
6060                 kvlist = rte_kvargs_parse(dev_args, bnxt_dev_args);
6061                 if (kvlist) {
6062                         /*
6063                          * Handler for "rep_is_pf" devarg.
6064                          * Invoked as for ex: "-a 000:00:0d.0,
6065                          * rep-based-pf=<pf index> rep-is-pf=<VF=0 or PF=1>"
6066                          */
6067                         ret = rte_kvargs_process(kvlist, BNXT_DEVARG_REP_IS_PF,
6068                                                  bnxt_parse_devarg_rep_is_pf,
6069                                                  (void *)&representor);
6070                         if (ret) {
6071                                 ret = -EINVAL;
6072                                 goto err;
6073                         }
6074                         /*
6075                          * Handler for "rep_based_pf" devarg.
6076                          * Invoked as for ex: "-a 000:00:0d.0,
6077                          * rep-based-pf=<pf index> rep-is-pf=<VF=0 or PF=1>"
6078                          */
6079                         ret = rte_kvargs_process(kvlist,
6080                                                  BNXT_DEVARG_REP_BASED_PF,
6081                                                  bnxt_parse_devarg_rep_based_pf,
6082                                                  (void *)&representor);
6083                         if (ret) {
6084                                 ret = -EINVAL;
6085                                 goto err;
6086                         }
6087                         /*
6088                          * Handler for "rep_based_pf" devarg.
6089                          * Invoked as for ex: "-a 000:00:0d.0,
6090                          * rep-based-pf=<pf index> rep-is-pf=<VF=0 or PF=1>"
6091                          */
6092                         ret = rte_kvargs_process(kvlist, BNXT_DEVARG_REP_Q_R2F,
6093                                                  bnxt_parse_devarg_rep_q_r2f,
6094                                                  (void *)&representor);
6095                         if (ret) {
6096                                 ret = -EINVAL;
6097                                 goto err;
6098                         }
6099                         /*
6100                          * Handler for "rep_based_pf" devarg.
6101                          * Invoked as for ex: "-a 000:00:0d.0,
6102                          * rep-based-pf=<pf index> rep-is-pf=<VF=0 or PF=1>"
6103                          */
6104                         ret = rte_kvargs_process(kvlist, BNXT_DEVARG_REP_Q_F2R,
6105                                                  bnxt_parse_devarg_rep_q_f2r,
6106                                                  (void *)&representor);
6107                         if (ret) {
6108                                 ret = -EINVAL;
6109                                 goto err;
6110                         }
6111                         /*
6112                          * Handler for "rep_based_pf" devarg.
6113                          * Invoked as for ex: "-a 000:00:0d.0,
6114                          * rep-based-pf=<pf index> rep-is-pf=<VF=0 or PF=1>"
6115                          */
6116                         ret = rte_kvargs_process(kvlist, BNXT_DEVARG_REP_FC_R2F,
6117                                                  bnxt_parse_devarg_rep_fc_r2f,
6118                                                  (void *)&representor);
6119                         if (ret) {
6120                                 ret = -EINVAL;
6121                                 goto err;
6122                         }
6123                         /*
6124                          * Handler for "rep_based_pf" devarg.
6125                          * Invoked as for ex: "-a 000:00:0d.0,
6126                          * rep-based-pf=<pf index> rep-is-pf=<VF=0 or PF=1>"
6127                          */
6128                         ret = rte_kvargs_process(kvlist, BNXT_DEVARG_REP_FC_F2R,
6129                                                  bnxt_parse_devarg_rep_fc_f2r,
6130                                                  (void *)&representor);
6131                         if (ret) {
6132                                 ret = -EINVAL;
6133                                 goto err;
6134                         }
6135                 }
6136
6137                 ret = rte_eth_dev_create(&pci_dev->device, name,
6138                                          sizeof(struct bnxt_representor),
6139                                          NULL, NULL,
6140                                          bnxt_representor_init,
6141                                          &representor);
6142                 if (ret) {
6143                         PMD_DRV_LOG(ERR, "failed to create bnxt vf "
6144                                     "representor %s.", name);
6145                         goto err;
6146                 }
6147
6148                 vf_rep_eth_dev = rte_eth_dev_allocated(name);
6149                 if (!vf_rep_eth_dev) {
6150                         PMD_DRV_LOG(ERR, "Failed to find the eth_dev"
6151                                     " for VF-Rep: %s.", name);
6152                         ret = -ENODEV;
6153                         goto err;
6154                 }
6155
6156                 PMD_DRV_LOG(DEBUG, "BNXT Port:%d VFR pci probe\n",
6157                             backing_eth_dev->data->port_id);
6158                 backing_bp->rep_info[representor.vf_id].vfr_eth_dev =
6159                                                          vf_rep_eth_dev;
6160                 backing_bp->num_reps++;
6161
6162         }
6163
6164         rte_kvargs_free(kvlist);
6165         return 0;
6166
6167 err:
6168         /* If num_rep > 1, then rollback already created
6169          * ports, since we'll be failing the probe anyway
6170          */
6171         if (num_rep > 1)
6172                 bnxt_pci_remove_dev_with_reps(backing_eth_dev);
6173         rte_errno = -ret;
6174         rte_kvargs_free(kvlist);
6175
6176         return ret;
6177 }
6178
6179 static int bnxt_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
6180                           struct rte_pci_device *pci_dev)
6181 {
6182         struct rte_eth_devargs eth_da = { .nb_representor_ports = 0 };
6183         struct rte_eth_dev *backing_eth_dev;
6184         uint16_t num_rep;
6185         int ret = 0;
6186
6187         if (pci_dev->device.devargs) {
6188                 ret = rte_eth_devargs_parse(pci_dev->device.devargs->args,
6189                                             &eth_da);
6190                 if (ret)
6191                         return ret;
6192         }
6193
6194         num_rep = eth_da.nb_representor_ports;
6195         PMD_DRV_LOG(DEBUG, "nb_representor_ports = %d\n",
6196                     num_rep);
6197
6198         /* We could come here after first level of probe is already invoked
6199          * as part of an application bringup(OVS-DPDK vswitchd), so first check
6200          * for already allocated eth_dev for the backing device (PF/Trusted VF)
6201          */
6202         backing_eth_dev = rte_eth_dev_allocated(pci_dev->device.name);
6203         if (backing_eth_dev == NULL) {
6204                 ret = rte_eth_dev_create(&pci_dev->device, pci_dev->device.name,
6205                                          sizeof(struct bnxt),
6206                                          eth_dev_pci_specific_init, pci_dev,
6207                                          bnxt_dev_init, NULL);
6208
6209                 if (ret || !num_rep)
6210                         return ret;
6211
6212                 backing_eth_dev = rte_eth_dev_allocated(pci_dev->device.name);
6213         }
6214         PMD_DRV_LOG(DEBUG, "BNXT Port:%d pci probe\n",
6215                     backing_eth_dev->data->port_id);
6216
6217         if (!num_rep)
6218                 return ret;
6219
6220         /* probe representor ports now */
6221         ret = bnxt_rep_port_probe(pci_dev, &eth_da, backing_eth_dev,
6222                                   pci_dev->device.devargs->args);
6223
6224         return ret;
6225 }
6226
6227 static int bnxt_pci_remove(struct rte_pci_device *pci_dev)
6228 {
6229         struct rte_eth_dev *eth_dev;
6230
6231         eth_dev = rte_eth_dev_allocated(pci_dev->device.name);
6232         if (!eth_dev)
6233                 return 0; /* Invoked typically only by OVS-DPDK, by the
6234                            * time it comes here the eth_dev is already
6235                            * deleted by rte_eth_dev_close(), so returning
6236                            * +ve value will at least help in proper cleanup
6237                            */
6238
6239         PMD_DRV_LOG(DEBUG, "BNXT Port:%d pci remove\n", eth_dev->data->port_id);
6240         if (rte_eal_process_type() == RTE_PROC_PRIMARY) {
6241                 if (eth_dev->data->dev_flags & RTE_ETH_DEV_REPRESENTOR)
6242                         return rte_eth_dev_destroy(eth_dev,
6243                                                    bnxt_representor_uninit);
6244                 else
6245                         return rte_eth_dev_destroy(eth_dev,
6246                                                    bnxt_dev_uninit);
6247         } else {
6248                 return rte_eth_dev_pci_generic_remove(pci_dev, NULL);
6249         }
6250 }
6251
6252 static struct rte_pci_driver bnxt_rte_pmd = {
6253         .id_table = bnxt_pci_id_map,
6254         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC |
6255                         RTE_PCI_DRV_PROBE_AGAIN, /* Needed in case of VF-REPs
6256                                                   * and OVS-DPDK
6257                                                   */
6258         .probe = bnxt_pci_probe,
6259         .remove = bnxt_pci_remove,
6260 };
6261
6262 static bool
6263 is_device_supported(struct rte_eth_dev *dev, struct rte_pci_driver *drv)
6264 {
6265         if (strcmp(dev->device->driver->name, drv->driver.name))
6266                 return false;
6267
6268         return true;
6269 }
6270
6271 bool is_bnxt_supported(struct rte_eth_dev *dev)
6272 {
6273         return is_device_supported(dev, &bnxt_rte_pmd);
6274 }
6275
6276 RTE_LOG_REGISTER_SUFFIX(bnxt_logtype_driver, driver, NOTICE);
6277 RTE_PMD_REGISTER_PCI(net_bnxt, bnxt_rte_pmd);
6278 RTE_PMD_REGISTER_PCI_TABLE(net_bnxt, bnxt_pci_id_map);
6279 RTE_PMD_REGISTER_KMOD_DEP(net_bnxt, "* igb_uio | uio_pci_generic | vfio-pci");