drivers/net/bnxt/bnxt_ethdev.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2014-2018 Broadcom
   3  * All rights reserved.
   4  */
   5
   6 #include <inttypes.h>
   7 #include <stdbool.h>
   8
   9 #include <rte_dev.h>
  10 #include <rte_ethdev_driver.h>
  11 #include <rte_ethdev_pci.h>
  12 #include <rte_malloc.h>
  13 #include <rte_cycles.h>
  14 #include <rte_alarm.h>
  15
  16 #include "bnxt.h"
  17 #include "bnxt_cpr.h"
  18 #include "bnxt_filter.h"
  19 #include "bnxt_hwrm.h"
  20 #include "bnxt_irq.h"
  21 #include "bnxt_ring.h"
  22 #include "bnxt_rxq.h"
  23 #include "bnxt_rxr.h"
  24 #include "bnxt_stats.h"
  25 #include "bnxt_txq.h"
  26 #include "bnxt_txr.h"
  27 #include "bnxt_vnic.h"
  28 #include "hsi_struct_def_dpdk.h"
  29 #include "bnxt_nvm_defs.h"
  30 #include "bnxt_util.h"
  31
  32 #define DRV_MODULE_NAME         "bnxt"
  33 static const char bnxt_version[] =
  34         "Broadcom NetXtreme driver " DRV_MODULE_NAME;
  35 int bnxt_logtype_driver;
  36
  37 #define PCI_VENDOR_ID_BROADCOM 0x14E4
  38
  39 #define BROADCOM_DEV_ID_STRATUS_NIC_VF1 0x1606
  40 #define BROADCOM_DEV_ID_STRATUS_NIC_VF2 0x1609
  41 #define BROADCOM_DEV_ID_STRATUS_NIC 0x1614
  42 #define BROADCOM_DEV_ID_57414_VF 0x16c1
  43 #define BROADCOM_DEV_ID_57301 0x16c8
  44 #define BROADCOM_DEV_ID_57302 0x16c9
  45 #define BROADCOM_DEV_ID_57304_PF 0x16ca
  46 #define BROADCOM_DEV_ID_57304_VF 0x16cb
  47 #define BROADCOM_DEV_ID_57417_MF 0x16cc
  48 #define BROADCOM_DEV_ID_NS2 0x16cd
  49 #define BROADCOM_DEV_ID_57311 0x16ce
  50 #define BROADCOM_DEV_ID_57312 0x16cf
  51 #define BROADCOM_DEV_ID_57402 0x16d0
  52 #define BROADCOM_DEV_ID_57404 0x16d1
  53 #define BROADCOM_DEV_ID_57406_PF 0x16d2
  54 #define BROADCOM_DEV_ID_57406_VF 0x16d3
  55 #define BROADCOM_DEV_ID_57402_MF 0x16d4
  56 #define BROADCOM_DEV_ID_57407_RJ45 0x16d5
  57 #define BROADCOM_DEV_ID_57412 0x16d6
  58 #define BROADCOM_DEV_ID_57414 0x16d7
  59 #define BROADCOM_DEV_ID_57416_RJ45 0x16d8
  60 #define BROADCOM_DEV_ID_57417_RJ45 0x16d9
  61 #define BROADCOM_DEV_ID_5741X_VF 0x16dc
  62 #define BROADCOM_DEV_ID_57412_MF 0x16de
  63 #define BROADCOM_DEV_ID_57314 0x16df
  64 #define BROADCOM_DEV_ID_57317_RJ45 0x16e0
  65 #define BROADCOM_DEV_ID_5731X_VF 0x16e1
  66 #define BROADCOM_DEV_ID_57417_SFP 0x16e2
  67 #define BROADCOM_DEV_ID_57416_SFP 0x16e3
  68 #define BROADCOM_DEV_ID_57317_SFP 0x16e4
  69 #define BROADCOM_DEV_ID_57404_MF 0x16e7
  70 #define BROADCOM_DEV_ID_57406_MF 0x16e8
  71 #define BROADCOM_DEV_ID_57407_SFP 0x16e9
  72 #define BROADCOM_DEV_ID_57407_MF 0x16ea
  73 #define BROADCOM_DEV_ID_57414_MF 0x16ec
  74 #define BROADCOM_DEV_ID_57416_MF 0x16ee
  75 #define BROADCOM_DEV_ID_57508 0x1750
  76 #define BROADCOM_DEV_ID_57504 0x1751
  77 #define BROADCOM_DEV_ID_57502 0x1752
  78 #define BROADCOM_DEV_ID_57500_VF1 0x1806
  79 #define BROADCOM_DEV_ID_57500_VF2 0x1807
  80 #define BROADCOM_DEV_ID_58802 0xd802
  81 #define BROADCOM_DEV_ID_58804 0xd804
  82 #define BROADCOM_DEV_ID_58808 0x16f0
  83 #define BROADCOM_DEV_ID_58802_VF 0xd800
  84
  85 static const struct rte_pci_id bnxt_pci_id_map[] = {
  86         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM,
  87                          BROADCOM_DEV_ID_STRATUS_NIC_VF1) },
  88         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM,
  89                          BROADCOM_DEV_ID_STRATUS_NIC_VF2) },
  90         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_STRATUS_NIC) },
  91         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414_VF) },
  92         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57301) },
  93         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57302) },
  94         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57304_PF) },
  95         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57304_VF) },
  96         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_NS2) },
  97         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57402) },
  98         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57404) },
  99         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57406_PF) },
 100         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57406_VF) },
 101         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57402_MF) },
 102         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57407_RJ45) },
 103         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57404_MF) },
 104         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57406_MF) },
 105         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57407_SFP) },
 106         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57407_MF) },
 107         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_5741X_VF) },
 108         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_5731X_VF) },
 109         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57314) },
 110         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_MF) },
 111         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57311) },
 112         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57312) },
 113         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57412) },
 114         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414) },
 115         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_RJ45) },
 116         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_RJ45) },
 117         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57412_MF) },
 118         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57317_RJ45) },
 119         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_SFP) },
 120         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_SFP) },
 121         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57317_SFP) },
 122         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414_MF) },
 123         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_MF) },
 124         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58802) },
 125         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58804) },
 126         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58808) },
 127         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58802_VF) },
 128         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57508) },
 129         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57504) },
 130         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57502) },
 131         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57500_VF1) },
 132         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57500_VF2) },
 133         { .vendor_id = 0, /* sentinel */ },
 134 };
 135
 136 #define BNXT_ETH_RSS_SUPPORT (  \
 137         ETH_RSS_IPV4 |          \
 138         ETH_RSS_NONFRAG_IPV4_TCP |      \
 139         ETH_RSS_NONFRAG_IPV4_UDP |      \
 140         ETH_RSS_IPV6 |          \
 141         ETH_RSS_NONFRAG_IPV6_TCP |      \
 142         ETH_RSS_NONFRAG_IPV6_UDP)
 143
 144 #define BNXT_DEV_TX_OFFLOAD_SUPPORT (DEV_TX_OFFLOAD_VLAN_INSERT | \
 145                                      DEV_TX_OFFLOAD_IPV4_CKSUM | \
 146                                      DEV_TX_OFFLOAD_TCP_CKSUM | \
 147                                      DEV_TX_OFFLOAD_UDP_CKSUM | \
 148                                      DEV_TX_OFFLOAD_TCP_TSO | \
 149                                      DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM | \
 150                                      DEV_TX_OFFLOAD_VXLAN_TNL_TSO | \
 151                                      DEV_TX_OFFLOAD_GRE_TNL_TSO | \
 152                                      DEV_TX_OFFLOAD_IPIP_TNL_TSO | \
 153                                      DEV_TX_OFFLOAD_GENEVE_TNL_TSO | \
 154                                      DEV_TX_OFFLOAD_QINQ_INSERT | \
 155                                      DEV_TX_OFFLOAD_MULTI_SEGS)
 156
 157 #define BNXT_DEV_RX_OFFLOAD_SUPPORT (DEV_RX_OFFLOAD_VLAN_FILTER | \
 158                                      DEV_RX_OFFLOAD_VLAN_STRIP | \
 159                                      DEV_RX_OFFLOAD_IPV4_CKSUM | \
 160                                      DEV_RX_OFFLOAD_UDP_CKSUM | \
 161                                      DEV_RX_OFFLOAD_TCP_CKSUM | \
 162                                      DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM | \
 163                                      DEV_RX_OFFLOAD_JUMBO_FRAME | \
 164                                      DEV_RX_OFFLOAD_KEEP_CRC | \
 165                                      DEV_RX_OFFLOAD_VLAN_EXTEND | \
 166                                      DEV_RX_OFFLOAD_TCP_LRO)
 167
 168 static int bnxt_vlan_offload_set_op(struct rte_eth_dev *dev, int mask);
 169 static void bnxt_print_link_info(struct rte_eth_dev *eth_dev);
 170 static int bnxt_mtu_set_op(struct rte_eth_dev *eth_dev, uint16_t new_mtu);
 171 static int bnxt_dev_uninit(struct rte_eth_dev *eth_dev);
 172 static int bnxt_init_resources(struct bnxt *bp, bool reconfig_dev);
 173 static int bnxt_uninit_resources(struct bnxt *bp, bool reconfig_dev);
 174 static void bnxt_cancel_fw_health_check(struct bnxt *bp);
 175
 176 int is_bnxt_in_error(struct bnxt *bp)
 177 {
 178         if (bp->flags & BNXT_FLAG_FATAL_ERROR)
 179                 return -EIO;
 180         if (bp->flags & BNXT_FLAG_FW_RESET)
 181                 return -EBUSY;
 182
 183         return 0;
 184 }
 185
 186 /***********************/
 187
 188 /*
 189  * High level utility functions
 190  */
 191
 192 uint16_t bnxt_rss_ctxts(const struct bnxt *bp)
 193 {
 194         if (!BNXT_CHIP_THOR(bp))
 195                 return 1;
 196
 197         return RTE_ALIGN_MUL_CEIL(bp->rx_nr_rings,
 198                                   BNXT_RSS_ENTRIES_PER_CTX_THOR) /
 199                                     BNXT_RSS_ENTRIES_PER_CTX_THOR;
 200 }
 201
 202 static uint16_t  bnxt_rss_hash_tbl_size(const struct bnxt *bp)
 203 {
 204         if (!BNXT_CHIP_THOR(bp))
 205                 return HW_HASH_INDEX_SIZE;
 206
 207         return bnxt_rss_ctxts(bp) * BNXT_RSS_ENTRIES_PER_CTX_THOR;
 208 }
 209
 210 static void bnxt_free_mem(struct bnxt *bp, bool reconfig)
 211 {
 212         bnxt_free_filter_mem(bp);
 213         bnxt_free_vnic_attributes(bp);
 214         bnxt_free_vnic_mem(bp);
 215
 216         /* tx/rx rings are configured as part of *_queue_setup callbacks.
 217          * If the number of rings change across fw update,
 218          * we don't have much choice except to warn the user.
 219          */
 220         if (!reconfig) {
 221                 bnxt_free_stats(bp);
 222                 bnxt_free_tx_rings(bp);
 223                 bnxt_free_rx_rings(bp);
 224         }
 225         bnxt_free_async_cp_ring(bp);
 226 }
 227
 228 static int bnxt_alloc_mem(struct bnxt *bp, bool reconfig)
 229 {
 230         int rc;
 231
 232         rc = bnxt_alloc_ring_grps(bp);
 233         if (rc)
 234                 goto alloc_mem_err;
 235
 236         rc = bnxt_alloc_async_ring_struct(bp);
 237         if (rc)
 238                 goto alloc_mem_err;
 239
 240         rc = bnxt_alloc_vnic_mem(bp);
 241         if (rc)
 242                 goto alloc_mem_err;
 243
 244         rc = bnxt_alloc_vnic_attributes(bp);
 245         if (rc)
 246                 goto alloc_mem_err;
 247
 248         rc = bnxt_alloc_filter_mem(bp);
 249         if (rc)
 250                 goto alloc_mem_err;
 251
 252         rc = bnxt_alloc_async_cp_ring(bp);
 253         if (rc)
 254                 goto alloc_mem_err;
 255
 256         return 0;
 257
 258 alloc_mem_err:
 259         bnxt_free_mem(bp, reconfig);
 260         return rc;
 261 }
 262
 263 static int bnxt_init_chip(struct bnxt *bp)
 264 {
 265         struct bnxt_rx_queue *rxq;
 266         struct rte_eth_link new;
 267         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(bp->eth_dev);
 268         struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
 269         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
 270         uint64_t rx_offloads = dev_conf->rxmode.offloads;
 271         uint32_t intr_vector = 0;
 272         uint32_t queue_id, base = BNXT_MISC_VEC_ID;
 273         uint32_t vec = BNXT_MISC_VEC_ID;
 274         unsigned int i, j;
 275         int rc;
 276
 277         if (bp->eth_dev->data->mtu > RTE_ETHER_MTU) {
 278                 bp->eth_dev->data->dev_conf.rxmode.offloads |=
 279                         DEV_RX_OFFLOAD_JUMBO_FRAME;
 280                 bp->flags |= BNXT_FLAG_JUMBO;
 281         } else {
 282                 bp->eth_dev->data->dev_conf.rxmode.offloads &=
 283                         ~DEV_RX_OFFLOAD_JUMBO_FRAME;
 284                 bp->flags &= ~BNXT_FLAG_JUMBO;
 285         }
 286
 287         /* THOR does not support ring groups.
 288          * But we will use the array to save RSS context IDs.
 289          */
 290         if (BNXT_CHIP_THOR(bp))
 291                 bp->max_ring_grps = BNXT_MAX_RSS_CTXTS_THOR;
 292
 293         rc = bnxt_alloc_all_hwrm_stat_ctxs(bp);
 294         if (rc) {
 295                 PMD_DRV_LOG(ERR, "HWRM stat ctx alloc failure rc: %x\n", rc);
 296                 goto err_out;
 297         }
 298
 299         rc = bnxt_alloc_hwrm_rings(bp);
 300         if (rc) {
 301                 PMD_DRV_LOG(ERR, "HWRM ring alloc failure rc: %x\n", rc);
 302                 goto err_out;
 303         }
 304
 305         rc = bnxt_alloc_all_hwrm_ring_grps(bp);
 306         if (rc) {
 307                 PMD_DRV_LOG(ERR, "HWRM ring grp alloc failure: %x\n", rc);
 308                 goto err_out;
 309         }
 310
 311         rc = bnxt_mq_rx_configure(bp);
 312         if (rc) {
 313                 PMD_DRV_LOG(ERR, "MQ mode configure failure rc: %x\n", rc);
 314                 goto err_out;
 315         }
 316
 317         /* VNIC configuration */
 318         for (i = 0; i < bp->nr_vnics; i++) {
 319                 struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
 320                 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
 321
 322                 rc = bnxt_vnic_grp_alloc(bp, vnic);
 323                 if (rc)
 324                         goto err_out;
 325
 326                 PMD_DRV_LOG(DEBUG, "vnic[%d] = %p vnic->fw_grp_ids = %p\n",
 327                             i, vnic, vnic->fw_grp_ids);
 328
 329                 rc = bnxt_hwrm_vnic_alloc(bp, vnic);
 330                 if (rc) {
 331                         PMD_DRV_LOG(ERR, "HWRM vnic %d alloc failure rc: %x\n",
 332                                 i, rc);
 333                         goto err_out;
 334                 }
 335
 336                 /* Alloc RSS context only if RSS mode is enabled */
 337                 if (dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS) {
 338                         int j, nr_ctxs = bnxt_rss_ctxts(bp);
 339
 340                         rc = 0;
 341                         for (j = 0; j < nr_ctxs; j++) {
 342                                 rc = bnxt_hwrm_vnic_ctx_alloc(bp, vnic, j);
 343                                 if (rc)
 344                                         break;
 345                         }
 346                         if (rc) {
 347                                 PMD_DRV_LOG(ERR,
 348                                   "HWRM vnic %d ctx %d alloc failure rc: %x\n",
 349                                   i, j, rc);
 350                                 goto err_out;
 351                         }
 352                         vnic->num_lb_ctxts = nr_ctxs;
 353                 }
 354
 355                 /*
 356                  * Firmware sets pf pair in default vnic cfg. If the VLAN strip
 357                  * setting is not available at this time, it will not be
 358                  * configured correctly in the CFA.
 359                  */
 360                 if (rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
 361                         vnic->vlan_strip = true;
 362                 else
 363                         vnic->vlan_strip = false;
 364
 365                 rc = bnxt_hwrm_vnic_cfg(bp, vnic);
 366                 if (rc) {
 367                         PMD_DRV_LOG(ERR, "HWRM vnic %d cfg failure rc: %x\n",
 368                                 i, rc);
 369                         goto err_out;
 370                 }
 371
 372                 rc = bnxt_set_hwrm_vnic_filters(bp, vnic);
 373                 if (rc) {
 374                         PMD_DRV_LOG(ERR,
 375                                 "HWRM vnic %d filter failure rc: %x\n",
 376                                 i, rc);
 377                         goto err_out;
 378                 }
 379
 380                 for (j = 0; j < bp->rx_num_qs_per_vnic; j++) {
 381                         rxq = bp->eth_dev->data->rx_queues[j];
 382
 383                         PMD_DRV_LOG(DEBUG,
 384                                     "rxq[%d]->vnic=%p vnic->fw_grp_ids=%p\n",
 385                                     j, rxq->vnic, rxq->vnic->fw_grp_ids);
 386
 387                         if (BNXT_HAS_RING_GRPS(bp) && rxq->rx_deferred_start)
 388                                 rxq->vnic->fw_grp_ids[j] = INVALID_HW_RING_ID;
 389                 }
 390
 391                 rc = bnxt_vnic_rss_configure(bp, vnic);
 392                 if (rc) {
 393                         PMD_DRV_LOG(ERR,
 394                                     "HWRM vnic set RSS failure rc: %x\n", rc);
 395                         goto err_out;
 396                 }
 397
 398                 bnxt_hwrm_vnic_plcmode_cfg(bp, vnic);
 399
 400                 if (bp->eth_dev->data->dev_conf.rxmode.offloads &
 401                     DEV_RX_OFFLOAD_TCP_LRO)
 402                         bnxt_hwrm_vnic_tpa_cfg(bp, vnic, 1);
 403                 else
 404                         bnxt_hwrm_vnic_tpa_cfg(bp, vnic, 0);
 405         }
 406         rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, &bp->vnic_info[0], 0, NULL);
 407         if (rc) {
 408                 PMD_DRV_LOG(ERR,
 409                         "HWRM cfa l2 rx mask failure rc: %x\n", rc);
 410                 goto err_out;
 411         }
 412
 413         /* check and configure queue intr-vector mapping */
 414         if ((rte_intr_cap_multiple(intr_handle) ||
 415              !RTE_ETH_DEV_SRIOV(bp->eth_dev).active) &&
 416             bp->eth_dev->data->dev_conf.intr_conf.rxq != 0) {
 417                 intr_vector = bp->eth_dev->data->nb_rx_queues;
 418                 PMD_DRV_LOG(DEBUG, "intr_vector = %d\n", intr_vector);
 419                 if (intr_vector > bp->rx_cp_nr_rings) {
 420                         PMD_DRV_LOG(ERR, "At most %d intr queues supported",
 421                                         bp->rx_cp_nr_rings);
 422                         return -ENOTSUP;
 423                 }
 424                 rc = rte_intr_efd_enable(intr_handle, intr_vector);
 425                 if (rc)
 426                         return rc;
 427         }
 428
 429         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
 430                 intr_handle->intr_vec =
 431                         rte_zmalloc("intr_vec",
 432                                     bp->eth_dev->data->nb_rx_queues *
 433                                     sizeof(int), 0);
 434                 if (intr_handle->intr_vec == NULL) {
 435                         PMD_DRV_LOG(ERR, "Failed to allocate %d rx_queues"
 436                                 " intr_vec", bp->eth_dev->data->nb_rx_queues);
 437                         rc = -ENOMEM;
 438                         goto err_disable;
 439                 }
 440                 PMD_DRV_LOG(DEBUG, "intr_handle->intr_vec = %p "
 441                         "intr_handle->nb_efd = %d intr_handle->max_intr = %d\n",
 442                          intr_handle->intr_vec, intr_handle->nb_efd,
 443                         intr_handle->max_intr);
 444                 for (queue_id = 0; queue_id < bp->eth_dev->data->nb_rx_queues;
 445                      queue_id++) {
 446                         intr_handle->intr_vec[queue_id] =
 447                                                         vec + BNXT_RX_VEC_START;
 448                         if (vec < base + intr_handle->nb_efd - 1)
 449                                 vec++;
 450                 }
 451         }
 452
 453         /* enable uio/vfio intr/eventfd mapping */
 454         rc = rte_intr_enable(intr_handle);
 455         if (rc)
 456                 goto err_free;
 457
 458         rc = bnxt_get_hwrm_link_config(bp, &new);
 459         if (rc) {
 460                 PMD_DRV_LOG(ERR, "HWRM Get link config failure rc: %x\n", rc);
 461                 goto err_free;
 462         }
 463
 464         if (!bp->link_info.link_up) {
 465                 rc = bnxt_set_hwrm_link_config(bp, true);
 466                 if (rc) {
 467                         PMD_DRV_LOG(ERR,
 468                                 "HWRM link config failure rc: %x\n", rc);
 469                         goto err_free;
 470                 }
 471         }
 472         bnxt_print_link_info(bp->eth_dev);
 473
 474         return 0;
 475
 476 err_free:
 477         rte_free(intr_handle->intr_vec);
 478 err_disable:
 479         rte_intr_efd_disable(intr_handle);
 480 err_out:
 481         /* Some of the error status returned by FW may not be from errno.h */
 482         if (rc > 0)
 483                 rc = -EIO;
 484
 485         return rc;
 486 }
 487
 488 static int bnxt_shutdown_nic(struct bnxt *bp)
 489 {
 490         bnxt_free_all_hwrm_resources(bp);
 491         bnxt_free_all_filters(bp);
 492         bnxt_free_all_vnics(bp);
 493         return 0;
 494 }
 495
 496 static int bnxt_init_nic(struct bnxt *bp)
 497 {
 498         int rc;
 499
 500         if (BNXT_HAS_RING_GRPS(bp)) {
 501                 rc = bnxt_init_ring_grps(bp);
 502                 if (rc)
 503                         return rc;
 504         }
 505
 506         bnxt_init_vnics(bp);
 507         bnxt_init_filters(bp);
 508
 509         return 0;
 510 }
 511
 512 /*
 513  * Device configuration and status function
 514  */
 515
 516 static int bnxt_dev_info_get_op(struct rte_eth_dev *eth_dev,
 517                                 struct rte_eth_dev_info *dev_info)
 518 {
 519         struct rte_pci_device *pdev = RTE_DEV_TO_PCI(eth_dev->device);
 520         struct bnxt *bp = eth_dev->data->dev_private;
 521         uint16_t max_vnics, i, j, vpool, vrxq;
 522         unsigned int max_rx_rings;
 523         int rc;
 524
 525         rc = is_bnxt_in_error(bp);
 526         if (rc)
 527                 return rc;
 528
 529         /* MAC Specifics */
 530         dev_info->max_mac_addrs = bp->max_l2_ctx;
 531         dev_info->max_hash_mac_addrs = 0;
 532
 533         /* PF/VF specifics */
 534         if (BNXT_PF(bp))
 535                 dev_info->max_vfs = pdev->max_vfs;
 536
 537         max_rx_rings = RTE_MIN(bp->max_rx_rings, bp->max_stat_ctx);
 538         /* For the sake of symmetry, max_rx_queues = max_tx_queues */
 539         dev_info->max_rx_queues = max_rx_rings;
 540         dev_info->max_tx_queues = max_rx_rings;
 541         dev_info->reta_size = bnxt_rss_hash_tbl_size(bp);
 542         dev_info->hash_key_size = 40;
 543         max_vnics = bp->max_vnics;
 544
 545         /* MTU specifics */
 546         dev_info->min_mtu = RTE_ETHER_MIN_MTU;
 547         dev_info->max_mtu = BNXT_MAX_MTU;
 548
 549         /* Fast path specifics */
 550         dev_info->min_rx_bufsize = 1;
 551         dev_info->max_rx_pktlen = BNXT_MAX_PKT_LEN;
 552
 553         dev_info->rx_offload_capa = BNXT_DEV_RX_OFFLOAD_SUPPORT;
 554         if (bp->flags & BNXT_FLAG_PTP_SUPPORTED)
 555                 dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_TIMESTAMP;
 556         dev_info->tx_offload_capa = BNXT_DEV_TX_OFFLOAD_SUPPORT;
 557         dev_info->flow_type_rss_offloads = BNXT_ETH_RSS_SUPPORT;
 558
 559         /* *INDENT-OFF* */
 560         dev_info->default_rxconf = (struct rte_eth_rxconf) {
 561                 .rx_thresh = {
 562                         .pthresh = 8,
 563                         .hthresh = 8,
 564                         .wthresh = 0,
 565                 },
 566                 .rx_free_thresh = 32,
 567                 /* If no descriptors available, pkts are dropped by default */
 568                 .rx_drop_en = 1,
 569         };
 570
 571         dev_info->default_txconf = (struct rte_eth_txconf) {
 572                 .tx_thresh = {
 573                         .pthresh = 32,
 574                         .hthresh = 0,
 575                         .wthresh = 0,
 576                 },
 577                 .tx_free_thresh = 32,
 578                 .tx_rs_thresh = 32,
 579         };
 580         eth_dev->data->dev_conf.intr_conf.lsc = 1;
 581
 582         eth_dev->data->dev_conf.intr_conf.rxq = 1;
 583         dev_info->rx_desc_lim.nb_min = BNXT_MIN_RING_DESC;
 584         dev_info->rx_desc_lim.nb_max = BNXT_MAX_RX_RING_DESC;
 585         dev_info->tx_desc_lim.nb_min = BNXT_MIN_RING_DESC;
 586         dev_info->tx_desc_lim.nb_max = BNXT_MAX_TX_RING_DESC;
 587
 588         /* *INDENT-ON* */
 589
 590         /*
 591          * TODO: default_rxconf, default_txconf, rx_desc_lim, and tx_desc_lim
 592          *       need further investigation.
 593          */
 594
 595         /* VMDq resources */
 596         vpool = 64; /* ETH_64_POOLS */
 597         vrxq = 128; /* ETH_VMDQ_DCB_NUM_QUEUES */
 598         for (i = 0; i < 4; vpool >>= 1, i++) {
 599                 if (max_vnics > vpool) {
 600                         for (j = 0; j < 5; vrxq >>= 1, j++) {
 601                                 if (dev_info->max_rx_queues > vrxq) {
 602                                         if (vpool > vrxq)
 603                                                 vpool = vrxq;
 604                                         goto found;
 605                                 }
 606                         }
 607                         /* Not enough resources to support VMDq */
 608                         break;
 609                 }
 610         }
 611         /* Not enough resources to support VMDq */
 612         vpool = 0;
 613         vrxq = 0;
 614 found:
 615         dev_info->max_vmdq_pools = vpool;
 616         dev_info->vmdq_queue_num = vrxq;
 617
 618         dev_info->vmdq_pool_base = 0;
 619         dev_info->vmdq_queue_base = 0;
 620
 621         return 0;
 622 }
 623
 624 /* Configure the device based on the configuration provided */
 625 static int bnxt_dev_configure_op(struct rte_eth_dev *eth_dev)
 626 {
 627         struct bnxt *bp = eth_dev->data->dev_private;
 628         uint64_t rx_offloads = eth_dev->data->dev_conf.rxmode.offloads;
 629         int rc;
 630
 631         bp->rx_queues = (void *)eth_dev->data->rx_queues;
 632         bp->tx_queues = (void *)eth_dev->data->tx_queues;
 633         bp->tx_nr_rings = eth_dev->data->nb_tx_queues;
 634         bp->rx_nr_rings = eth_dev->data->nb_rx_queues;
 635
 636         rc = is_bnxt_in_error(bp);
 637         if (rc)
 638                 return rc;
 639
 640         if (BNXT_VF(bp) && (bp->flags & BNXT_FLAG_NEW_RM)) {
 641                 rc = bnxt_hwrm_check_vf_rings(bp);
 642                 if (rc) {
 643                         PMD_DRV_LOG(ERR, "HWRM insufficient resources\n");
 644                         return -ENOSPC;
 645                 }
 646
 647                 rc = bnxt_hwrm_func_reserve_vf_resc(bp, false);
 648                 if (rc) {
 649                         PMD_DRV_LOG(ERR, "HWRM resource alloc fail:%x\n", rc);
 650                         return -ENOSPC;
 651                 }
 652         } else {
 653                 /* legacy driver needs to get updated values */
 654                 rc = bnxt_hwrm_func_qcaps(bp);
 655                 if (rc) {
 656                         PMD_DRV_LOG(ERR, "hwrm func qcaps fail:%d\n", rc);
 657                         return rc;
 658                 }
 659         }
 660
 661         /* Inherit new configurations */
 662         if (eth_dev->data->nb_rx_queues > bp->max_rx_rings ||
 663             eth_dev->data->nb_tx_queues > bp->max_tx_rings ||
 664             eth_dev->data->nb_rx_queues + eth_dev->data->nb_tx_queues
 665                 + BNXT_NUM_ASYNC_CPR(bp) > bp->max_cp_rings ||
 666             eth_dev->data->nb_rx_queues + eth_dev->data->nb_tx_queues >
 667             bp->max_stat_ctx)
 668                 goto resource_error;
 669
 670         if (BNXT_HAS_RING_GRPS(bp) &&
 671             (uint32_t)(eth_dev->data->nb_rx_queues) > bp->max_ring_grps)
 672                 goto resource_error;
 673
 674         if (!(eth_dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_RSS) &&
 675             bp->max_vnics < eth_dev->data->nb_rx_queues)
 676                 goto resource_error;
 677
 678         bp->rx_cp_nr_rings = bp->rx_nr_rings;
 679         bp->tx_cp_nr_rings = bp->tx_nr_rings;
 680
 681         if (rx_offloads & DEV_RX_OFFLOAD_JUMBO_FRAME) {
 682                 eth_dev->data->mtu =
 683                         eth_dev->data->dev_conf.rxmode.max_rx_pkt_len -
 684                         RTE_ETHER_HDR_LEN - RTE_ETHER_CRC_LEN - VLAN_TAG_SIZE *
 685                         BNXT_NUM_VLANS;
 686                 bnxt_mtu_set_op(eth_dev, eth_dev->data->mtu);
 687         }
 688         return 0;
 689
 690 resource_error:
 691         PMD_DRV_LOG(ERR,
 692                     "Insufficient resources to support requested config\n");
 693         PMD_DRV_LOG(ERR,
 694                     "Num Queues Requested: Tx %d, Rx %d\n",
 695                     eth_dev->data->nb_tx_queues,
 696                     eth_dev->data->nb_rx_queues);
 697         PMD_DRV_LOG(ERR,
 698                     "MAX: TxQ %d, RxQ %d, CQ %d Stat %d, Grp %d, Vnic %d\n",
 699                     bp->max_tx_rings, bp->max_rx_rings, bp->max_cp_rings,
 700                     bp->max_stat_ctx, bp->max_ring_grps, bp->max_vnics);
 701         return -ENOSPC;
 702 }
 703
 704 static void bnxt_print_link_info(struct rte_eth_dev *eth_dev)
 705 {
 706         struct rte_eth_link *link = &eth_dev->data->dev_link;
 707
 708         if (link->link_status)
 709                 PMD_DRV_LOG(INFO, "Port %d Link Up - speed %u Mbps - %s\n",
 710                         eth_dev->data->port_id,
 711                         (uint32_t)link->link_speed,
 712                         (link->link_duplex == ETH_LINK_FULL_DUPLEX) ?
 713                         ("full-duplex") : ("half-duplex\n"));
 714         else
 715                 PMD_DRV_LOG(INFO, "Port %d Link Down\n",
 716                         eth_dev->data->port_id);
 717 }
 718
 719 /*
 720  * Determine whether the current configuration requires support for scattered
 721  * receive; return 1 if scattered receive is required and 0 if not.
 722  */
 723 static int bnxt_scattered_rx(struct rte_eth_dev *eth_dev)
 724 {
 725         uint16_t buf_size;
 726         int i;
 727
 728         for (i = 0; i < eth_dev->data->nb_rx_queues; i++) {
 729                 struct bnxt_rx_queue *rxq = eth_dev->data->rx_queues[i];
 730
 731                 buf_size = (uint16_t)(rte_pktmbuf_data_room_size(rxq->mb_pool) -
 732                                       RTE_PKTMBUF_HEADROOM);
 733                 if (eth_dev->data->dev_conf.rxmode.max_rx_pkt_len > buf_size)
 734                         return 1;
 735         }
 736         return 0;
 737 }
 738
 739 static eth_rx_burst_t
 740 bnxt_receive_function(__rte_unused struct rte_eth_dev *eth_dev)
 741 {
 742 #ifdef RTE_ARCH_X86
 743 #ifndef RTE_LIBRTE_IEEE1588
 744         /*
 745          * Vector mode receive can be enabled only if scatter rx is not
 746          * in use and rx offloads are limited to VLAN stripping and
 747          * CRC stripping.
 748          */
 749         if (!eth_dev->data->scattered_rx &&
 750             !(eth_dev->data->dev_conf.rxmode.offloads &
 751               ~(DEV_RX_OFFLOAD_VLAN_STRIP |
 752                 DEV_RX_OFFLOAD_KEEP_CRC |
 753                 DEV_RX_OFFLOAD_JUMBO_FRAME |
 754                 DEV_RX_OFFLOAD_IPV4_CKSUM |
 755                 DEV_RX_OFFLOAD_UDP_CKSUM |
 756                 DEV_RX_OFFLOAD_TCP_CKSUM |
 757                 DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM |
 758                 DEV_RX_OFFLOAD_VLAN_FILTER))) {
 759                 PMD_DRV_LOG(INFO, "Using vector mode receive for port %d\n",
 760                             eth_dev->data->port_id);
 761                 return bnxt_recv_pkts_vec;
 762         }
 763         PMD_DRV_LOG(INFO, "Vector mode receive disabled for port %d\n",
 764                     eth_dev->data->port_id);
 765         PMD_DRV_LOG(INFO,
 766                     "Port %d scatter: %d rx offload: %" PRIX64 "\n",
 767                     eth_dev->data->port_id,
 768                     eth_dev->data->scattered_rx,
 769                     eth_dev->data->dev_conf.rxmode.offloads);
 770 #endif
 771 #endif
 772         return bnxt_recv_pkts;
 773 }
 774
 775 static eth_tx_burst_t
 776 bnxt_transmit_function(__rte_unused struct rte_eth_dev *eth_dev)
 777 {
 778 #ifdef RTE_ARCH_X86
 779 #ifndef RTE_LIBRTE_IEEE1588
 780         /*
 781          * Vector mode transmit can be enabled only if not using scatter rx
 782          * or tx offloads.
 783          */
 784         if (!eth_dev->data->scattered_rx &&
 785             !eth_dev->data->dev_conf.txmode.offloads) {
 786                 PMD_DRV_LOG(INFO, "Using vector mode transmit for port %d\n",
 787                             eth_dev->data->port_id);
 788                 return bnxt_xmit_pkts_vec;
 789         }
 790         PMD_DRV_LOG(INFO, "Vector mode transmit disabled for port %d\n",
 791                     eth_dev->data->port_id);
 792         PMD_DRV_LOG(INFO,
 793                     "Port %d scatter: %d tx offload: %" PRIX64 "\n",
 794                     eth_dev->data->port_id,
 795                     eth_dev->data->scattered_rx,
 796                     eth_dev->data->dev_conf.txmode.offloads);
 797 #endif
 798 #endif
 799         return bnxt_xmit_pkts;
 800 }
 801
 802 static int bnxt_handle_if_change_status(struct bnxt *bp)
 803 {
 804         int rc;
 805
 806         /* Since fw has undergone a reset and lost all contexts,
 807          * set fatal flag to not issue hwrm during cleanup
 808          */
 809         bp->flags |= BNXT_FLAG_FATAL_ERROR;
 810         bnxt_uninit_resources(bp, true);
 811
 812         /* clear fatal flag so that re-init happens */
 813         bp->flags &= ~BNXT_FLAG_FATAL_ERROR;
 814         rc = bnxt_init_resources(bp, true);
 815
 816         bp->flags &= ~BNXT_FLAG_IF_CHANGE_HOT_FW_RESET_DONE;
 817
 818         return rc;
 819 }
 820
 821 static int bnxt_dev_start_op(struct rte_eth_dev *eth_dev)
 822 {
 823         struct bnxt *bp = eth_dev->data->dev_private;
 824         uint64_t rx_offloads = eth_dev->data->dev_conf.rxmode.offloads;
 825         int vlan_mask = 0;
 826         int rc;
 827
 828         if (bp->rx_cp_nr_rings > RTE_ETHDEV_QUEUE_STAT_CNTRS) {
 829                 PMD_DRV_LOG(ERR,
 830                         "RxQ cnt %d > CONFIG_RTE_ETHDEV_QUEUE_STAT_CNTRS %d\n",
 831                         bp->rx_cp_nr_rings, RTE_ETHDEV_QUEUE_STAT_CNTRS);
 832         }
 833
 834         bnxt_enable_int(bp);
 835         rc = bnxt_hwrm_if_change(bp, 1);
 836         if (!rc) {
 837                 if (bp->flags & BNXT_FLAG_IF_CHANGE_HOT_FW_RESET_DONE) {
 838                         rc = bnxt_handle_if_change_status(bp);
 839                         if (rc)
 840                                 return rc;
 841                 }
 842         }
 843
 844         rc = bnxt_init_chip(bp);
 845         if (rc)
 846                 goto error;
 847
 848         eth_dev->data->scattered_rx = bnxt_scattered_rx(eth_dev);
 849
 850         bnxt_link_update_op(eth_dev, 1);
 851
 852         if (rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER)
 853                 vlan_mask |= ETH_VLAN_FILTER_MASK;
 854         if (rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
 855                 vlan_mask |= ETH_VLAN_STRIP_MASK;
 856         rc = bnxt_vlan_offload_set_op(eth_dev, vlan_mask);
 857         if (rc)
 858                 goto error;
 859
 860         eth_dev->rx_pkt_burst = bnxt_receive_function(eth_dev);
 861         eth_dev->tx_pkt_burst = bnxt_transmit_function(eth_dev);
 862
 863         bp->flags |= BNXT_FLAG_INIT_DONE;
 864         eth_dev->data->dev_started = 1;
 865         bp->dev_stopped = 0;
 866         bnxt_schedule_fw_health_check(bp);
 867         return 0;
 868
 869 error:
 870         bnxt_hwrm_if_change(bp, 0);
 871         bnxt_shutdown_nic(bp);
 872         bnxt_free_tx_mbufs(bp);
 873         bnxt_free_rx_mbufs(bp);
 874         return rc;
 875 }
 876
 877 static int bnxt_dev_set_link_up_op(struct rte_eth_dev *eth_dev)
 878 {
 879         struct bnxt *bp = eth_dev->data->dev_private;
 880         int rc = 0;
 881
 882         if (!bp->link_info.link_up)
 883                 rc = bnxt_set_hwrm_link_config(bp, true);
 884         if (!rc)
 885                 eth_dev->data->dev_link.link_status = 1;
 886
 887         bnxt_print_link_info(eth_dev);
 888         return 0;
 889 }
 890
 891 static int bnxt_dev_set_link_down_op(struct rte_eth_dev *eth_dev)
 892 {
 893         struct bnxt *bp = eth_dev->data->dev_private;
 894
 895         eth_dev->data->dev_link.link_status = 0;
 896         bnxt_set_hwrm_link_config(bp, false);
 897         bp->link_info.link_up = 0;
 898
 899         return 0;
 900 }
 901
 902 /* Unload the driver, release resources */
 903 static void bnxt_dev_stop_op(struct rte_eth_dev *eth_dev)
 904 {
 905         struct bnxt *bp = eth_dev->data->dev_private;
 906         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
 907         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
 908
 909         eth_dev->data->dev_started = 0;
 910         /* Prevent crashes when queues are still in use */
 911         eth_dev->rx_pkt_burst = &bnxt_dummy_recv_pkts;
 912         eth_dev->tx_pkt_burst = &bnxt_dummy_xmit_pkts;
 913
 914         bnxt_disable_int(bp);
 915
 916         /* disable uio/vfio intr/eventfd mapping */
 917         rte_intr_disable(intr_handle);
 918
 919         bnxt_cancel_fw_health_check(bp);
 920
 921         bp->flags &= ~BNXT_FLAG_INIT_DONE;
 922         if (bp->eth_dev->data->dev_started) {
 923                 /* TBD: STOP HW queues DMA */
 924                 eth_dev->data->dev_link.link_status = 0;
 925         }
 926         bnxt_dev_set_link_down_op(eth_dev);
 927         /* Wait for link to be reset and the async notification to process. */
 928         rte_delay_ms(BNXT_LINK_WAIT_INTERVAL * 2);
 929
 930         /* Clean queue intr-vector mapping */
 931         rte_intr_efd_disable(intr_handle);
 932         if (intr_handle->intr_vec != NULL) {
 933                 rte_free(intr_handle->intr_vec);
 934                 intr_handle->intr_vec = NULL;
 935         }
 936
 937         bnxt_hwrm_port_clr_stats(bp);
 938         bnxt_free_tx_mbufs(bp);
 939         bnxt_free_rx_mbufs(bp);
 940         /* Process any remaining notifications in default completion queue */
 941         bnxt_int_handler(eth_dev);
 942         bnxt_shutdown_nic(bp);
 943         bnxt_hwrm_if_change(bp, 0);
 944         bp->dev_stopped = 1;
 945 }
 946
 947 static void bnxt_dev_close_op(struct rte_eth_dev *eth_dev)
 948 {
 949         struct bnxt *bp = eth_dev->data->dev_private;
 950
 951         if (bp->dev_stopped == 0)
 952                 bnxt_dev_stop_op(eth_dev);
 953
 954         if (eth_dev->data->mac_addrs != NULL) {
 955                 rte_free(eth_dev->data->mac_addrs);
 956                 eth_dev->data->mac_addrs = NULL;
 957         }
 958         if (bp->grp_info != NULL) {
 959                 rte_free(bp->grp_info);
 960                 bp->grp_info = NULL;
 961         }
 962
 963         bnxt_dev_uninit(eth_dev);
 964 }
 965
 966 static void bnxt_mac_addr_remove_op(struct rte_eth_dev *eth_dev,
 967                                     uint32_t index)
 968 {
 969         struct bnxt *bp = eth_dev->data->dev_private;
 970         uint64_t pool_mask = eth_dev->data->mac_pool_sel[index];
 971         struct bnxt_vnic_info *vnic;
 972         struct bnxt_filter_info *filter, *temp_filter;
 973         uint32_t i;
 974
 975         if (is_bnxt_in_error(bp))
 976                 return;
 977
 978         /*
 979          * Loop through all VNICs from the specified filter flow pools to
 980          * remove the corresponding MAC addr filter
 981          */
 982         for (i = 0; i < bp->nr_vnics; i++) {
 983                 if (!(pool_mask & (1ULL << i)))
 984                         continue;
 985
 986                 vnic = &bp->vnic_info[i];
 987                 filter = STAILQ_FIRST(&vnic->filter);
 988                 while (filter) {
 989                         temp_filter = STAILQ_NEXT(filter, next);
 990                         if (filter->mac_index == index) {
 991                                 STAILQ_REMOVE(&vnic->filter, filter,
 992                                                 bnxt_filter_info, next);
 993                                 bnxt_hwrm_clear_l2_filter(bp, filter);
 994                                 filter->mac_index = INVALID_MAC_INDEX;
 995                                 memset(&filter->l2_addr, 0, RTE_ETHER_ADDR_LEN);
 996                                 STAILQ_INSERT_TAIL(&bp->free_filter_list,
 997                                                    filter, next);
 998                         }
 999                         filter = temp_filter;
1000                 }
1001         }
1002 }
1003
1004 static int bnxt_add_mac_filter(struct bnxt *bp, struct bnxt_vnic_info *vnic,
1005                                struct rte_ether_addr *mac_addr, uint32_t index)
1006 {
1007         struct bnxt_filter_info *filter;
1008         int rc = 0;
1009
1010         filter = STAILQ_FIRST(&vnic->filter);
1011         /* During bnxt_mac_addr_add_op, default MAC is
1012          * already programmed, so skip it. But, when
1013          * hw-vlan-filter is turned OFF from ON, default
1014          * MAC filter should be restored
1015          */
1016         if (filter->dflt)
1017                 return 0;
1018
1019         filter = bnxt_alloc_filter(bp);
1020         if (!filter) {
1021                 PMD_DRV_LOG(ERR, "L2 filter alloc failed\n");
1022                 return -ENODEV;
1023         }
1024
1025         filter->mac_index = index;
1026         /* bnxt_alloc_filter copies default MAC to filter->l2_addr. So,
1027          * if the MAC that's been programmed now is a different one, then,
1028          * copy that addr to filter->l2_addr
1029          */
1030         if (mac_addr)
1031                 memcpy(filter->l2_addr, mac_addr, RTE_ETHER_ADDR_LEN);
1032         filter->flags |= HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_OUTERMOST;
1033
1034         rc = bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id, filter);
1035         if (!rc) {
1036                 if (filter->mac_index == 0) {
1037                         filter->dflt = true;
1038                         STAILQ_INSERT_HEAD(&vnic->filter, filter, next);
1039                 } else {
1040                         STAILQ_INSERT_TAIL(&vnic->filter, filter, next);
1041                 }
1042         } else {
1043                 filter->mac_index = INVALID_MAC_INDEX;
1044                 memset(&filter->l2_addr, 0, RTE_ETHER_ADDR_LEN);
1045                 bnxt_free_filter(bp, filter);
1046         }
1047
1048         return rc;
1049 }
1050
1051 static int bnxt_mac_addr_add_op(struct rte_eth_dev *eth_dev,
1052                                 struct rte_ether_addr *mac_addr,
1053                                 uint32_t index, uint32_t pool)
1054 {
1055         struct bnxt *bp = eth_dev->data->dev_private;
1056         struct bnxt_vnic_info *vnic = &bp->vnic_info[pool];
1057         struct bnxt_filter_info *filter;
1058         int rc = 0;
1059
1060         rc = is_bnxt_in_error(bp);
1061         if (rc)
1062                 return rc;
1063
1064         if (BNXT_VF(bp) & !BNXT_VF_IS_TRUSTED(bp)) {
1065                 PMD_DRV_LOG(ERR, "Cannot add MAC address to a VF interface\n");
1066                 return -ENOTSUP;
1067         }
1068
1069         if (!vnic) {
1070                 PMD_DRV_LOG(ERR, "VNIC not found for pool %d!\n", pool);
1071                 return -EINVAL;
1072         }
1073         /* Attach requested MAC address to the new l2_filter */
1074         STAILQ_FOREACH(filter, &vnic->filter, next) {
1075                 if (filter->mac_index == index) {
1076                         PMD_DRV_LOG(ERR,
1077                                 "MAC addr already existed for pool %d\n", pool);
1078                         return 0;
1079                 }
1080         }
1081
1082         rc = bnxt_add_mac_filter(bp, vnic, mac_addr, index);
1083
1084         return rc;
1085 }
1086
1087 int bnxt_link_update_op(struct rte_eth_dev *eth_dev, int wait_to_complete)
1088 {
1089         int rc = 0;
1090         struct bnxt *bp = eth_dev->data->dev_private;
1091         struct rte_eth_link new;
1092         unsigned int cnt = BNXT_LINK_WAIT_CNT;
1093
1094         rc = is_bnxt_in_error(bp);
1095         if (rc)
1096                 return rc;
1097
1098         memset(&new, 0, sizeof(new));
1099         do {
1100                 /* Retrieve link info from hardware */
1101                 rc = bnxt_get_hwrm_link_config(bp, &new);
1102                 if (rc) {
1103                         new.link_speed = ETH_LINK_SPEED_100M;
1104                         new.link_duplex = ETH_LINK_FULL_DUPLEX;
1105                         PMD_DRV_LOG(ERR,
1106                                 "Failed to retrieve link rc = 0x%x!\n", rc);
1107                         goto out;
1108                 }
1109
1110                 if (!wait_to_complete || new.link_status)
1111                         break;
1112
1113                 rte_delay_ms(BNXT_LINK_WAIT_INTERVAL);
1114         } while (cnt--);
1115
1116 out:
1117         /* Timed out or success */
1118         if (new.link_status != eth_dev->data->dev_link.link_status ||
1119         new.link_speed != eth_dev->data->dev_link.link_speed) {
1120                 rte_eth_linkstatus_set(eth_dev, &new);
1121
1122                 _rte_eth_dev_callback_process(eth_dev,
1123                                               RTE_ETH_EVENT_INTR_LSC,
1124                                               NULL);
1125
1126                 bnxt_print_link_info(eth_dev);
1127         }
1128
1129         return rc;
1130 }
1131
1132 static int bnxt_promiscuous_enable_op(struct rte_eth_dev *eth_dev)
1133 {
1134         struct bnxt *bp = eth_dev->data->dev_private;
1135         struct bnxt_vnic_info *vnic;
1136         uint32_t old_flags;
1137         int rc;
1138
1139         rc = is_bnxt_in_error(bp);
1140         if (rc)
1141                 return rc;
1142
1143         if (bp->vnic_info == NULL)
1144                 return 0;
1145
1146         vnic = BNXT_GET_DEFAULT_VNIC(bp);
1147
1148         old_flags = vnic->flags;
1149         vnic->flags |= BNXT_VNIC_INFO_PROMISC;
1150         rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1151         if (rc != 0)
1152                 vnic->flags = old_flags;
1153
1154         return rc;
1155 }
1156
1157 static int bnxt_promiscuous_disable_op(struct rte_eth_dev *eth_dev)
1158 {
1159         struct bnxt *bp = eth_dev->data->dev_private;
1160         struct bnxt_vnic_info *vnic;
1161         uint32_t old_flags;
1162         int rc;
1163
1164         rc = is_bnxt_in_error(bp);
1165         if (rc)
1166                 return rc;
1167
1168         if (bp->vnic_info == NULL)
1169                 return 0;
1170
1171         vnic = BNXT_GET_DEFAULT_VNIC(bp);
1172
1173         old_flags = vnic->flags;
1174         vnic->flags &= ~BNXT_VNIC_INFO_PROMISC;
1175         rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1176         if (rc != 0)
1177                 vnic->flags = old_flags;
1178
1179         return rc;
1180 }
1181
1182 static int bnxt_allmulticast_enable_op(struct rte_eth_dev *eth_dev)
1183 {
1184         struct bnxt *bp = eth_dev->data->dev_private;
1185         struct bnxt_vnic_info *vnic;
1186         uint32_t old_flags;
1187         int rc;
1188
1189         rc = is_bnxt_in_error(bp);
1190         if (rc)
1191                 return rc;
1192
1193         if (bp->vnic_info == NULL)
1194                 return 0;
1195
1196         vnic = BNXT_GET_DEFAULT_VNIC(bp);
1197
1198         old_flags = vnic->flags;
1199         vnic->flags |= BNXT_VNIC_INFO_ALLMULTI;
1200         rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1201         if (rc != 0)
1202                 vnic->flags = old_flags;
1203
1204         return rc;
1205 }
1206
1207 static int bnxt_allmulticast_disable_op(struct rte_eth_dev *eth_dev)
1208 {
1209         struct bnxt *bp = eth_dev->data->dev_private;
1210         struct bnxt_vnic_info *vnic;
1211         uint32_t old_flags;
1212         int rc;
1213
1214         rc = is_bnxt_in_error(bp);
1215         if (rc)
1216                 return rc;
1217
1218         if (bp->vnic_info == NULL)
1219                 return 0;
1220
1221         vnic = BNXT_GET_DEFAULT_VNIC(bp);
1222
1223         old_flags = vnic->flags;
1224         vnic->flags &= ~BNXT_VNIC_INFO_ALLMULTI;
1225         rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1226         if (rc != 0)
1227                 vnic->flags = old_flags;
1228
1229         return rc;
1230 }
1231
1232 /* Return bnxt_rx_queue pointer corresponding to a given rxq. */
1233 static struct bnxt_rx_queue *bnxt_qid_to_rxq(struct bnxt *bp, uint16_t qid)
1234 {
1235         if (qid >= bp->rx_nr_rings)
1236                 return NULL;
1237
1238         return bp->eth_dev->data->rx_queues[qid];
1239 }
1240
1241 /* Return rxq corresponding to a given rss table ring/group ID. */
1242 static uint16_t bnxt_rss_to_qid(struct bnxt *bp, uint16_t fwr)
1243 {
1244         struct bnxt_rx_queue *rxq;
1245         unsigned int i;
1246
1247         if (!BNXT_HAS_RING_GRPS(bp)) {
1248                 for (i = 0; i < bp->rx_nr_rings; i++) {
1249                         rxq = bp->eth_dev->data->rx_queues[i];
1250                         if (rxq->rx_ring->rx_ring_struct->fw_ring_id == fwr)
1251                                 return rxq->index;
1252                 }
1253         } else {
1254                 for (i = 0; i < bp->rx_nr_rings; i++) {
1255                         if (bp->grp_info[i].fw_grp_id == fwr)
1256                                 return i;
1257                 }
1258         }
1259
1260         return INVALID_HW_RING_ID;
1261 }
1262
1263 static int bnxt_reta_update_op(struct rte_eth_dev *eth_dev,
1264                             struct rte_eth_rss_reta_entry64 *reta_conf,
1265                             uint16_t reta_size)
1266 {
1267         struct bnxt *bp = eth_dev->data->dev_private;
1268         struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
1269         struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
1270         uint16_t tbl_size = bnxt_rss_hash_tbl_size(bp);
1271         uint16_t idx, sft;
1272         int i, rc;
1273
1274         rc = is_bnxt_in_error(bp);
1275         if (rc)
1276                 return rc;
1277
1278         if (!vnic->rss_table)
1279                 return -EINVAL;
1280
1281         if (!(dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG))
1282                 return -EINVAL;
1283
1284         if (reta_size != tbl_size) {
1285                 PMD_DRV_LOG(ERR, "The configured hash table lookup size "
1286                         "(%d) must equal the size supported by the hardware "
1287                         "(%d)\n", reta_size, tbl_size);
1288                 return -EINVAL;
1289         }
1290
1291         for (i = 0; i < reta_size; i++) {
1292                 struct bnxt_rx_queue *rxq;
1293
1294                 idx = i / RTE_RETA_GROUP_SIZE;
1295                 sft = i % RTE_RETA_GROUP_SIZE;
1296
1297                 if (!(reta_conf[idx].mask & (1ULL << sft)))
1298                         continue;
1299
1300                 rxq = bnxt_qid_to_rxq(bp, reta_conf[idx].reta[sft]);
1301                 if (!rxq) {
1302                         PMD_DRV_LOG(ERR, "Invalid ring in reta_conf.\n");
1303                         return -EINVAL;
1304                 }
1305
1306                 if (BNXT_CHIP_THOR(bp)) {
1307                         vnic->rss_table[i * 2] =
1308                                 rxq->rx_ring->rx_ring_struct->fw_ring_id;
1309                         vnic->rss_table[i * 2 + 1] =
1310                                 rxq->cp_ring->cp_ring_struct->fw_ring_id;
1311                 } else {
1312                         vnic->rss_table[i] =
1313                             vnic->fw_grp_ids[reta_conf[idx].reta[sft]];
1314                 }
1315
1316                 vnic->rss_table[i] =
1317                     vnic->fw_grp_ids[reta_conf[idx].reta[sft]];
1318         }
1319
1320         bnxt_hwrm_vnic_rss_cfg(bp, vnic);
1321         return 0;
1322 }
1323
1324 static int bnxt_reta_query_op(struct rte_eth_dev *eth_dev,
1325                               struct rte_eth_rss_reta_entry64 *reta_conf,
1326                               uint16_t reta_size)
1327 {
1328         struct bnxt *bp = eth_dev->data->dev_private;
1329         struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
1330         uint16_t tbl_size = bnxt_rss_hash_tbl_size(bp);
1331         uint16_t idx, sft, i;
1332         int rc;
1333
1334         rc = is_bnxt_in_error(bp);
1335         if (rc)
1336                 return rc;
1337
1338         /* Retrieve from the default VNIC */
1339         if (!vnic)
1340                 return -EINVAL;
1341         if (!vnic->rss_table)
1342                 return -EINVAL;
1343
1344         if (reta_size != tbl_size) {
1345                 PMD_DRV_LOG(ERR, "The configured hash table lookup size "
1346                         "(%d) must equal the size supported by the hardware "
1347                         "(%d)\n", reta_size, tbl_size);
1348                 return -EINVAL;
1349         }
1350
1351         for (idx = 0, i = 0; i < reta_size; i++) {
1352                 idx = i / RTE_RETA_GROUP_SIZE;
1353                 sft = i % RTE_RETA_GROUP_SIZE;
1354
1355                 if (reta_conf[idx].mask & (1ULL << sft)) {
1356                         uint16_t qid;
1357
1358                         if (BNXT_CHIP_THOR(bp))
1359                                 qid = bnxt_rss_to_qid(bp,
1360                                                       vnic->rss_table[i * 2]);
1361                         else
1362                                 qid = bnxt_rss_to_qid(bp, vnic->rss_table[i]);
1363
1364                         if (qid == INVALID_HW_RING_ID) {
1365                                 PMD_DRV_LOG(ERR, "Inv. entry in rss table.\n");
1366                                 return -EINVAL;
1367                         }
1368                         reta_conf[idx].reta[sft] = qid;
1369                 }
1370         }
1371
1372         return 0;
1373 }
1374
1375 static int bnxt_rss_hash_update_op(struct rte_eth_dev *eth_dev,
1376                                    struct rte_eth_rss_conf *rss_conf)
1377 {
1378         struct bnxt *bp = eth_dev->data->dev_private;
1379         struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
1380         struct bnxt_vnic_info *vnic;
1381         int rc;
1382
1383         rc = is_bnxt_in_error(bp);
1384         if (rc)
1385                 return rc;
1386
1387         /*
1388          * If RSS enablement were different than dev_configure,
1389          * then return -EINVAL
1390          */
1391         if (dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG) {
1392                 if (!rss_conf->rss_hf)
1393                         PMD_DRV_LOG(ERR, "Hash type NONE\n");
1394         } else {
1395                 if (rss_conf->rss_hf & BNXT_ETH_RSS_SUPPORT)
1396                         return -EINVAL;
1397         }
1398
1399         bp->flags |= BNXT_FLAG_UPDATE_HASH;
1400         memcpy(&bp->rss_conf, rss_conf, sizeof(*rss_conf));
1401
1402         /* Update the default RSS VNIC(s) */
1403         vnic = &bp->vnic_info[0];
1404         vnic->hash_type = bnxt_rte_to_hwrm_hash_types(rss_conf->rss_hf);
1405
1406         /*
1407          * If hashkey is not specified, use the previously configured
1408          * hashkey
1409          */
1410         if (!rss_conf->rss_key)
1411                 goto rss_config;
1412
1413         if (rss_conf->rss_key_len != HW_HASH_KEY_SIZE) {
1414                 PMD_DRV_LOG(ERR,
1415                             "Invalid hashkey length, should be 16 bytes\n");
1416                 return -EINVAL;
1417         }
1418         memcpy(vnic->rss_hash_key, rss_conf->rss_key, rss_conf->rss_key_len);
1419
1420 rss_config:
1421         bnxt_hwrm_vnic_rss_cfg(bp, vnic);
1422         return 0;
1423 }
1424
1425 static int bnxt_rss_hash_conf_get_op(struct rte_eth_dev *eth_dev,
1426                                      struct rte_eth_rss_conf *rss_conf)
1427 {
1428         struct bnxt *bp = eth_dev->data->dev_private;
1429         struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
1430         int len, rc;
1431         uint32_t hash_types;
1432
1433         rc = is_bnxt_in_error(bp);
1434         if (rc)
1435                 return rc;
1436
1437         /* RSS configuration is the same for all VNICs */
1438         if (vnic && vnic->rss_hash_key) {
1439                 if (rss_conf->rss_key) {
1440                         len = rss_conf->rss_key_len <= HW_HASH_KEY_SIZE ?
1441                               rss_conf->rss_key_len : HW_HASH_KEY_SIZE;
1442                         memcpy(rss_conf->rss_key, vnic->rss_hash_key, len);
1443                 }
1444
1445                 hash_types = vnic->hash_type;
1446                 rss_conf->rss_hf = 0;
1447                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV4) {
1448                         rss_conf->rss_hf |= ETH_RSS_IPV4;
1449                         hash_types &= ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV4;
1450                 }
1451                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV4) {
1452                         rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP;
1453                         hash_types &=
1454                                 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV4;
1455                 }
1456                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV4) {
1457                         rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
1458                         hash_types &=
1459                                 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV4;
1460                 }
1461                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6) {
1462                         rss_conf->rss_hf |= ETH_RSS_IPV6;
1463                         hash_types &= ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6;
1464                 }
1465                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV6) {
1466                         rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV6_TCP;
1467                         hash_types &=
1468                                 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV6;
1469                 }
1470                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV6) {
1471                         rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;
1472                         hash_types &=
1473                                 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV6;
1474                 }
1475                 if (hash_types) {
1476                         PMD_DRV_LOG(ERR,
1477                                 "Unknwon RSS config from firmware (%08x), RSS disabled",
1478                                 vnic->hash_type);
1479                         return -ENOTSUP;
1480                 }
1481         } else {
1482                 rss_conf->rss_hf = 0;
1483         }
1484         return 0;
1485 }
1486
1487 static int bnxt_flow_ctrl_get_op(struct rte_eth_dev *dev,
1488                                struct rte_eth_fc_conf *fc_conf)
1489 {
1490         struct bnxt *bp = dev->data->dev_private;
1491         struct rte_eth_link link_info;
1492         int rc;
1493
1494         rc = is_bnxt_in_error(bp);
1495         if (rc)
1496                 return rc;
1497
1498         rc = bnxt_get_hwrm_link_config(bp, &link_info);
1499         if (rc)
1500                 return rc;
1501
1502         memset(fc_conf, 0, sizeof(*fc_conf));
1503         if (bp->link_info.auto_pause)
1504                 fc_conf->autoneg = 1;
1505         switch (bp->link_info.pause) {
1506         case 0:
1507                 fc_conf->mode = RTE_FC_NONE;
1508                 break;
1509         case HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_TX:
1510                 fc_conf->mode = RTE_FC_TX_PAUSE;
1511                 break;
1512         case HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_RX:
1513                 fc_conf->mode = RTE_FC_RX_PAUSE;
1514                 break;
1515         case (HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_TX |
1516                         HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_RX):
1517                 fc_conf->mode = RTE_FC_FULL;
1518                 break;
1519         }
1520         return 0;
1521 }
1522
1523 static int bnxt_flow_ctrl_set_op(struct rte_eth_dev *dev,
1524                                struct rte_eth_fc_conf *fc_conf)
1525 {
1526         struct bnxt *bp = dev->data->dev_private;
1527         int rc;
1528
1529         rc = is_bnxt_in_error(bp);
1530         if (rc)
1531                 return rc;
1532
1533         if (!BNXT_SINGLE_PF(bp) || BNXT_VF(bp)) {
1534                 PMD_DRV_LOG(ERR, "Flow Control Settings cannot be modified\n");
1535                 return -ENOTSUP;
1536         }
1537
1538         switch (fc_conf->mode) {
1539         case RTE_FC_NONE:
1540                 bp->link_info.auto_pause = 0;
1541                 bp->link_info.force_pause = 0;
1542                 break;
1543         case RTE_FC_RX_PAUSE:
1544                 if (fc_conf->autoneg) {
1545                         bp->link_info.auto_pause =
1546                                         HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_RX;
1547                         bp->link_info.force_pause = 0;
1548                 } else {
1549                         bp->link_info.auto_pause = 0;
1550                         bp->link_info.force_pause =
1551                                         HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_RX;
1552                 }
1553                 break;
1554         case RTE_FC_TX_PAUSE:
1555                 if (fc_conf->autoneg) {
1556                         bp->link_info.auto_pause =
1557                                         HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_TX;
1558                         bp->link_info.force_pause = 0;
1559                 } else {
1560                         bp->link_info.auto_pause = 0;
1561                         bp->link_info.force_pause =
1562                                         HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_TX;
1563                 }
1564                 break;
1565         case RTE_FC_FULL:
1566                 if (fc_conf->autoneg) {
1567                         bp->link_info.auto_pause =
1568                                         HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_TX |
1569                                         HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_RX;
1570                         bp->link_info.force_pause = 0;
1571                 } else {
1572                         bp->link_info.auto_pause = 0;
1573                         bp->link_info.force_pause =
1574                                         HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_TX |
1575                                         HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_RX;
1576                 }
1577                 break;
1578         }
1579         return bnxt_set_hwrm_link_config(bp, true);
1580 }
1581
1582 /* Add UDP tunneling port */
1583 static int
1584 bnxt_udp_tunnel_port_add_op(struct rte_eth_dev *eth_dev,
1585                          struct rte_eth_udp_tunnel *udp_tunnel)
1586 {
1587         struct bnxt *bp = eth_dev->data->dev_private;
1588         uint16_t tunnel_type = 0;
1589         int rc = 0;
1590
1591         rc = is_bnxt_in_error(bp);
1592         if (rc)
1593                 return rc;
1594
1595         switch (udp_tunnel->prot_type) {
1596         case RTE_TUNNEL_TYPE_VXLAN:
1597                 if (bp->vxlan_port_cnt) {
1598                         PMD_DRV_LOG(ERR, "Tunnel Port %d already programmed\n",
1599                                 udp_tunnel->udp_port);
1600                         if (bp->vxlan_port != udp_tunnel->udp_port) {
1601                                 PMD_DRV_LOG(ERR, "Only one port allowed\n");
1602                                 return -ENOSPC;
1603                         }
1604                         bp->vxlan_port_cnt++;
1605                         return 0;
1606                 }
1607                 tunnel_type =
1608                         HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_VXLAN;
1609                 bp->vxlan_port_cnt++;
1610                 break;
1611         case RTE_TUNNEL_TYPE_GENEVE:
1612                 if (bp->geneve_port_cnt) {
1613                         PMD_DRV_LOG(ERR, "Tunnel Port %d already programmed\n",
1614                                 udp_tunnel->udp_port);
1615                         if (bp->geneve_port != udp_tunnel->udp_port) {
1616                                 PMD_DRV_LOG(ERR, "Only one port allowed\n");
1617                                 return -ENOSPC;
1618                         }
1619                         bp->geneve_port_cnt++;
1620                         return 0;
1621                 }
1622                 tunnel_type =
1623                         HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_GENEVE;
1624                 bp->geneve_port_cnt++;
1625                 break;
1626         default:
1627                 PMD_DRV_LOG(ERR, "Tunnel type is not supported\n");
1628                 return -ENOTSUP;
1629         }
1630         rc = bnxt_hwrm_tunnel_dst_port_alloc(bp, udp_tunnel->udp_port,
1631                                              tunnel_type);
1632         return rc;
1633 }
1634
1635 static int
1636 bnxt_udp_tunnel_port_del_op(struct rte_eth_dev *eth_dev,
1637                          struct rte_eth_udp_tunnel *udp_tunnel)
1638 {
1639         struct bnxt *bp = eth_dev->data->dev_private;
1640         uint16_t tunnel_type = 0;
1641         uint16_t port = 0;
1642         int rc = 0;
1643
1644         rc = is_bnxt_in_error(bp);
1645         if (rc)
1646                 return rc;
1647
1648         switch (udp_tunnel->prot_type) {
1649         case RTE_TUNNEL_TYPE_VXLAN:
1650                 if (!bp->vxlan_port_cnt) {
1651                         PMD_DRV_LOG(ERR, "No Tunnel port configured yet\n");
1652                         return -EINVAL;
1653                 }
1654                 if (bp->vxlan_port != udp_tunnel->udp_port) {
1655                         PMD_DRV_LOG(ERR, "Req Port: %d. Configured port: %d\n",
1656                                 udp_tunnel->udp_port, bp->vxlan_port);
1657                         return -EINVAL;
1658                 }
1659                 if (--bp->vxlan_port_cnt)
1660                         return 0;
1661
1662                 tunnel_type =
1663                         HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN;
1664                 port = bp->vxlan_fw_dst_port_id;
1665                 break;
1666         case RTE_TUNNEL_TYPE_GENEVE:
1667                 if (!bp->geneve_port_cnt) {
1668                         PMD_DRV_LOG(ERR, "No Tunnel port configured yet\n");
1669                         return -EINVAL;
1670                 }
1671                 if (bp->geneve_port != udp_tunnel->udp_port) {
1672                         PMD_DRV_LOG(ERR, "Req Port: %d. Configured port: %d\n",
1673                                 udp_tunnel->udp_port, bp->geneve_port);
1674                         return -EINVAL;
1675                 }
1676                 if (--bp->geneve_port_cnt)
1677                         return 0;
1678
1679                 tunnel_type =
1680                         HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_GENEVE;
1681                 port = bp->geneve_fw_dst_port_id;
1682                 break;
1683         default:
1684                 PMD_DRV_LOG(ERR, "Tunnel type is not supported\n");
1685                 return -ENOTSUP;
1686         }
1687
1688         rc = bnxt_hwrm_tunnel_dst_port_free(bp, port, tunnel_type);
1689         if (!rc) {
1690                 if (tunnel_type ==
1691                     HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN)
1692                         bp->vxlan_port = 0;
1693                 if (tunnel_type ==
1694                     HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_GENEVE)
1695                         bp->geneve_port = 0;
1696         }
1697         return rc;
1698 }
1699
1700 static int bnxt_del_vlan_filter(struct bnxt *bp, uint16_t vlan_id)
1701 {
1702         struct bnxt_filter_info *filter;
1703         struct bnxt_vnic_info *vnic;
1704         int rc = 0;
1705         uint32_t chk = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN;
1706
1707         /* if VLAN exists && VLAN matches vlan_id
1708          *      remove the MAC+VLAN filter
1709          *      add a new MAC only filter
1710          * else
1711          *      VLAN filter doesn't exist, just skip and continue
1712          */
1713         vnic = BNXT_GET_DEFAULT_VNIC(bp);
1714         filter = STAILQ_FIRST(&vnic->filter);
1715         while (filter) {
1716                 /* Search for this matching MAC+VLAN filter */
1717                 if ((filter->enables & chk) &&
1718                     (filter->l2_ivlan == vlan_id &&
1719                      filter->l2_ivlan_mask != 0) &&
1720                     !memcmp(filter->l2_addr, bp->mac_addr,
1721                             RTE_ETHER_ADDR_LEN)) {
1722                         /* Delete the filter */
1723                         rc = bnxt_hwrm_clear_l2_filter(bp, filter);
1724                         if (rc)
1725                                 return rc;
1726                         STAILQ_REMOVE(&vnic->filter, filter,
1727                                       bnxt_filter_info, next);
1728                         STAILQ_INSERT_TAIL(&bp->free_filter_list, filter, next);
1729
1730                         PMD_DRV_LOG(INFO,
1731                                     "Del Vlan filter for %d\n",
1732                                     vlan_id);
1733                         return rc;
1734                 }
1735                 filter = STAILQ_NEXT(filter, next);
1736         }
1737         return -ENOENT;
1738 }
1739
1740 static int bnxt_add_vlan_filter(struct bnxt *bp, uint16_t vlan_id)
1741 {
1742         struct bnxt_filter_info *filter;
1743         struct bnxt_vnic_info *vnic;
1744         int rc = 0;
1745         uint32_t en = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN |
1746                 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN_MASK;
1747         uint32_t chk = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN;
1748
1749         /* Implementation notes on the use of VNIC in this command:
1750          *
1751          * By default, these filters belong to default vnic for the function.
1752          * Once these filters are set up, only destination VNIC can be modified.
1753          * If the destination VNIC is not specified in this command,
1754          * then the HWRM shall only create an l2 context id.
1755          */
1756
1757         vnic = BNXT_GET_DEFAULT_VNIC(bp);
1758         filter = STAILQ_FIRST(&vnic->filter);
1759         /* Check if the VLAN has already been added */
1760         while (filter) {
1761                 if ((filter->enables & chk) &&
1762                     (filter->l2_ivlan == vlan_id &&
1763                      filter->l2_ivlan_mask == 0x0FFF) &&
1764                      !memcmp(filter->l2_addr, bp->mac_addr,
1765                              RTE_ETHER_ADDR_LEN))
1766                         return -EEXIST;
1767
1768                 filter = STAILQ_NEXT(filter, next);
1769         }
1770
1771         /* No match found. Alloc a fresh filter and issue the L2_FILTER_ALLOC
1772          * command to create MAC+VLAN filter with the right flags, enables set.
1773          */
1774         filter = bnxt_alloc_filter(bp);
1775         if (!filter) {
1776                 PMD_DRV_LOG(ERR,
1777                             "MAC/VLAN filter alloc failed\n");
1778                 return -ENOMEM;
1779         }
1780         /* MAC + VLAN ID filter */
1781         /* If l2_ivlan == 0 and l2_ivlan_mask != 0, only
1782          * untagged packets are received
1783          *
1784          * If l2_ivlan != 0 and l2_ivlan_mask != 0, untagged
1785          * packets and only the programmed vlan's packets are received
1786          */
1787         filter->l2_ivlan = vlan_id;
1788         filter->l2_ivlan_mask = 0x0FFF;
1789         filter->enables |= en;
1790         filter->flags |= HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_OUTERMOST;
1791
1792         rc = bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id, filter);
1793         if (rc) {
1794                 /* Free the newly allocated filter as we were
1795                  * not able to create the filter in hardware.
1796                  */
1797                 filter->fw_l2_filter_id = UINT64_MAX;
1798                 STAILQ_INSERT_TAIL(&bp->free_filter_list, filter, next);
1799                 return rc;
1800         } else {
1801                 /* Add this new filter to the list */
1802                 if (vlan_id == 0) {
1803                         filter->dflt = true;
1804                         STAILQ_INSERT_HEAD(&vnic->filter, filter, next);
1805                 } else {
1806                         STAILQ_INSERT_TAIL(&vnic->filter, filter, next);
1807                 }
1808         }
1809
1810         PMD_DRV_LOG(INFO,
1811                     "Added Vlan filter for %d\n", vlan_id);
1812         return rc;
1813 }
1814
1815 static int bnxt_vlan_filter_set_op(struct rte_eth_dev *eth_dev,
1816                 uint16_t vlan_id, int on)
1817 {
1818         struct bnxt *bp = eth_dev->data->dev_private;
1819         int rc;
1820
1821         rc = is_bnxt_in_error(bp);
1822         if (rc)
1823                 return rc;
1824
1825         /* These operations apply to ALL existing MAC/VLAN filters */
1826         if (on)
1827                 return bnxt_add_vlan_filter(bp, vlan_id);
1828         else
1829                 return bnxt_del_vlan_filter(bp, vlan_id);
1830 }
1831
1832 static int bnxt_del_dflt_mac_filter(struct bnxt *bp,
1833                                     struct bnxt_vnic_info *vnic)
1834 {
1835         struct bnxt_filter_info *filter;
1836         int rc;
1837
1838         filter = STAILQ_FIRST(&vnic->filter);
1839         while (filter) {
1840                 if (filter->dflt &&
1841                     !memcmp(filter->l2_addr, bp->mac_addr,
1842                             RTE_ETHER_ADDR_LEN)) {
1843                         rc = bnxt_hwrm_clear_l2_filter(bp, filter);
1844                         if (rc)
1845                                 return rc;
1846                         filter->dflt = false;
1847                         STAILQ_REMOVE(&vnic->filter, filter,
1848                                       bnxt_filter_info, next);
1849                         STAILQ_INSERT_TAIL(&bp->free_filter_list,
1850                                            filter, next);
1851                         filter->fw_l2_filter_id = -1;
1852                         break;
1853                 }
1854                 filter = STAILQ_NEXT(filter, next);
1855         }
1856         return 0;
1857 }
1858
1859 static int
1860 bnxt_vlan_offload_set_op(struct rte_eth_dev *dev, int mask)
1861 {
1862         struct bnxt *bp = dev->data->dev_private;
1863         uint64_t rx_offloads = dev->data->dev_conf.rxmode.offloads;
1864         struct bnxt_vnic_info *vnic;
1865         unsigned int i;
1866         int rc;
1867
1868         rc = is_bnxt_in_error(bp);
1869         if (rc)
1870                 return rc;
1871
1872         vnic = BNXT_GET_DEFAULT_VNIC(bp);
1873         if (!(rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER)) {
1874                 /* Remove any VLAN filters programmed */
1875                 for (i = 0; i < 4095; i++)
1876                         bnxt_del_vlan_filter(bp, i);
1877
1878                 rc = bnxt_add_mac_filter(bp, vnic, NULL, 0);
1879                 if (rc)
1880                         return rc;
1881         } else {
1882                 /* Default filter will allow packets that match the
1883                  * dest mac. So, it has to be deleted, otherwise, we
1884                  * will endup receiving vlan packets for which the
1885                  * filter is not programmed, when hw-vlan-filter
1886                  * configuration is ON
1887                  */
1888                 bnxt_del_dflt_mac_filter(bp, vnic);
1889                 /* This filter will allow only untagged packets */
1890                 bnxt_add_vlan_filter(bp, 0);
1891         }
1892         PMD_DRV_LOG(DEBUG, "VLAN Filtering: %d\n",
1893                     !!(rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER));
1894
1895         if (mask & ETH_VLAN_STRIP_MASK) {
1896                 /* Enable or disable VLAN stripping */
1897                 for (i = 0; i < bp->nr_vnics; i++) {
1898                         struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
1899                         if (rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
1900                                 vnic->vlan_strip = true;
1901                         else
1902                                 vnic->vlan_strip = false;
1903                         bnxt_hwrm_vnic_cfg(bp, vnic);
1904                 }
1905                 PMD_DRV_LOG(DEBUG, "VLAN Strip Offload: %d\n",
1906                         !!(rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP));
1907         }
1908
1909         if (mask & ETH_VLAN_EXTEND_MASK) {
1910                 if (rx_offloads & DEV_RX_OFFLOAD_VLAN_EXTEND)
1911                         PMD_DRV_LOG(DEBUG, "Extend VLAN supported\n");
1912                 else
1913                         PMD_DRV_LOG(INFO, "Extend VLAN unsupported\n");
1914         }
1915
1916         return 0;
1917 }
1918
1919 static int
1920 bnxt_vlan_tpid_set_op(struct rte_eth_dev *dev, enum rte_vlan_type vlan_type,
1921                       uint16_t tpid)
1922 {
1923         struct bnxt *bp = dev->data->dev_private;
1924         int qinq = dev->data->dev_conf.rxmode.offloads &
1925                    DEV_RX_OFFLOAD_VLAN_EXTEND;
1926
1927         if (vlan_type != ETH_VLAN_TYPE_INNER &&
1928             vlan_type != ETH_VLAN_TYPE_OUTER) {
1929                 PMD_DRV_LOG(ERR,
1930                             "Unsupported vlan type.");
1931                 return -EINVAL;
1932         }
1933         if (!qinq) {
1934                 PMD_DRV_LOG(ERR,
1935                             "QinQ not enabled. Needs to be ON as we can "
1936                             "accelerate only outer vlan\n");
1937                 return -EINVAL;
1938         }
1939
1940         if (vlan_type == ETH_VLAN_TYPE_OUTER) {
1941                 switch (tpid) {
1942                 case RTE_ETHER_TYPE_QINQ:
1943                         bp->outer_tpid_bd =
1944                                 TX_BD_LONG_CFA_META_VLAN_TPID_TPID88A8;
1945                                 break;
1946                 case RTE_ETHER_TYPE_VLAN:
1947                         bp->outer_tpid_bd =
1948                                 TX_BD_LONG_CFA_META_VLAN_TPID_TPID8100;
1949                                 break;
1950                 case 0x9100:
1951                         bp->outer_tpid_bd =
1952                                 TX_BD_LONG_CFA_META_VLAN_TPID_TPID9100;
1953                                 break;
1954                 case 0x9200:
1955                         bp->outer_tpid_bd =
1956                                 TX_BD_LONG_CFA_META_VLAN_TPID_TPID9200;
1957                                 break;
1958                 case 0x9300:
1959                         bp->outer_tpid_bd =
1960                                  TX_BD_LONG_CFA_META_VLAN_TPID_TPID9300;
1961                                 break;
1962                 default:
1963                         PMD_DRV_LOG(ERR, "Invalid TPID: %x\n", tpid);
1964                         return -EINVAL;
1965                 }
1966                 bp->outer_tpid_bd |= tpid;
1967                 PMD_DRV_LOG(INFO, "outer_tpid_bd = %x\n", bp->outer_tpid_bd);
1968         } else if (vlan_type == ETH_VLAN_TYPE_INNER) {
1969                 PMD_DRV_LOG(ERR,
1970                             "Can accelerate only outer vlan in QinQ\n");
1971                 return -EINVAL;
1972         }
1973
1974         return 0;
1975 }
1976
1977 static int
1978 bnxt_set_default_mac_addr_op(struct rte_eth_dev *dev,
1979                              struct rte_ether_addr *addr)
1980 {
1981         struct bnxt *bp = dev->data->dev_private;
1982         /* Default Filter is tied to VNIC 0 */
1983         struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
1984         struct bnxt_filter_info *filter;
1985         int rc;
1986
1987         rc = is_bnxt_in_error(bp);
1988         if (rc)
1989                 return rc;
1990
1991         if (BNXT_VF(bp) && !BNXT_VF_IS_TRUSTED(bp))
1992                 return -EPERM;
1993
1994         if (rte_is_zero_ether_addr(addr))
1995                 return -EINVAL;
1996
1997         STAILQ_FOREACH(filter, &vnic->filter, next) {
1998                 /* Default Filter is at Index 0 */
1999                 if (filter->mac_index != 0)
2000                         continue;
2001
2002                 memcpy(filter->l2_addr, addr, RTE_ETHER_ADDR_LEN);
2003                 memset(filter->l2_addr_mask, 0xff, RTE_ETHER_ADDR_LEN);
2004                 filter->flags |= HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_PATH_RX |
2005                         HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_OUTERMOST;
2006                 filter->enables |=
2007                         HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR |
2008                         HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR_MASK;
2009
2010                 rc = bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id, filter);
2011                 if (rc) {
2012                         memcpy(filter->l2_addr, bp->mac_addr,
2013                                RTE_ETHER_ADDR_LEN);
2014                         return rc;
2015                 }
2016
2017                 memcpy(bp->mac_addr, addr, RTE_ETHER_ADDR_LEN);
2018                 PMD_DRV_LOG(DEBUG, "Set MAC addr\n");
2019                 return 0;
2020         }
2021
2022         return 0;
2023 }
2024
2025 static int
2026 bnxt_dev_set_mc_addr_list_op(struct rte_eth_dev *eth_dev,
2027                           struct rte_ether_addr *mc_addr_set,
2028                           uint32_t nb_mc_addr)
2029 {
2030         struct bnxt *bp = eth_dev->data->dev_private;
2031         char *mc_addr_list = (char *)mc_addr_set;
2032         struct bnxt_vnic_info *vnic;
2033         uint32_t off = 0, i = 0;
2034         int rc;
2035
2036         rc = is_bnxt_in_error(bp);
2037         if (rc)
2038                 return rc;
2039
2040         vnic = BNXT_GET_DEFAULT_VNIC(bp);
2041
2042         if (nb_mc_addr > BNXT_MAX_MC_ADDRS) {
2043                 vnic->flags |= BNXT_VNIC_INFO_ALLMULTI;
2044                 goto allmulti;
2045         }
2046
2047         /* TODO Check for Duplicate mcast addresses */
2048         vnic->flags &= ~BNXT_VNIC_INFO_ALLMULTI;
2049         for (i = 0; i < nb_mc_addr; i++) {
2050                 memcpy(vnic->mc_list + off, &mc_addr_list[i],
2051                         RTE_ETHER_ADDR_LEN);
2052                 off += RTE_ETHER_ADDR_LEN;
2053         }
2054
2055         vnic->mc_addr_cnt = i;
2056
2057 allmulti:
2058         return bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
2059 }
2060
2061 static int
2062 bnxt_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size)
2063 {
2064         struct bnxt *bp = dev->data->dev_private;
2065         uint8_t fw_major = (bp->fw_ver >> 24) & 0xff;
2066         uint8_t fw_minor = (bp->fw_ver >> 16) & 0xff;
2067         uint8_t fw_updt = (bp->fw_ver >> 8) & 0xff;
2068         int ret;
2069
2070         ret = snprintf(fw_version, fw_size, "%d.%d.%d",
2071                         fw_major, fw_minor, fw_updt);
2072
2073         ret += 1; /* add the size of '\0' */
2074         if (fw_size < (uint32_t)ret)
2075                 return ret;
2076         else
2077                 return 0;
2078 }
2079
2080 static void
2081 bnxt_rxq_info_get_op(struct rte_eth_dev *dev, uint16_t queue_id,
2082         struct rte_eth_rxq_info *qinfo)
2083 {
2084         struct bnxt_rx_queue *rxq;
2085
2086         rxq = dev->data->rx_queues[queue_id];
2087
2088         qinfo->mp = rxq->mb_pool;
2089         qinfo->scattered_rx = dev->data->scattered_rx;
2090         qinfo->nb_desc = rxq->nb_rx_desc;
2091
2092         qinfo->conf.rx_free_thresh = rxq->rx_free_thresh;
2093         qinfo->conf.rx_drop_en = 0;
2094         qinfo->conf.rx_deferred_start = rxq->rx_deferred_start;
2095 }
2096
2097 static void
2098 bnxt_txq_info_get_op(struct rte_eth_dev *dev, uint16_t queue_id,
2099         struct rte_eth_txq_info *qinfo)
2100 {
2101         struct bnxt_tx_queue *txq;
2102
2103         txq = dev->data->tx_queues[queue_id];
2104
2105         qinfo->nb_desc = txq->nb_tx_desc;
2106
2107         qinfo->conf.tx_thresh.pthresh = txq->pthresh;
2108         qinfo->conf.tx_thresh.hthresh = txq->hthresh;
2109         qinfo->conf.tx_thresh.wthresh = txq->wthresh;
2110
2111         qinfo->conf.tx_free_thresh = txq->tx_free_thresh;
2112         qinfo->conf.tx_rs_thresh = 0;
2113         qinfo->conf.tx_deferred_start = txq->tx_deferred_start;
2114 }
2115
2116 static int bnxt_mtu_set_op(struct rte_eth_dev *eth_dev, uint16_t new_mtu)
2117 {
2118         struct bnxt *bp = eth_dev->data->dev_private;
2119         uint32_t new_pkt_size;
2120         uint32_t rc = 0;
2121         uint32_t i;
2122
2123         rc = is_bnxt_in_error(bp);
2124         if (rc)
2125                 return rc;
2126
2127         new_pkt_size = new_mtu + RTE_ETHER_HDR_LEN + RTE_ETHER_CRC_LEN +
2128                        VLAN_TAG_SIZE * BNXT_NUM_VLANS;
2129
2130 #ifdef RTE_ARCH_X86
2131         /*
2132          * If vector-mode tx/rx is active, disallow any MTU change that would
2133          * require scattered receive support.
2134          */
2135         if (eth_dev->data->dev_started &&
2136             (eth_dev->rx_pkt_burst == bnxt_recv_pkts_vec ||
2137              eth_dev->tx_pkt_burst == bnxt_xmit_pkts_vec) &&
2138             (new_pkt_size >
2139              eth_dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM)) {
2140                 PMD_DRV_LOG(ERR,
2141                             "MTU change would require scattered rx support. ");
2142                 PMD_DRV_LOG(ERR, "Stop port before changing MTU.\n");
2143                 return -EINVAL;
2144         }
2145 #endif
2146
2147         if (new_mtu > RTE_ETHER_MTU) {
2148                 bp->flags |= BNXT_FLAG_JUMBO;
2149                 bp->eth_dev->data->dev_conf.rxmode.offloads |=
2150                         DEV_RX_OFFLOAD_JUMBO_FRAME;
2151         } else {
2152                 bp->eth_dev->data->dev_conf.rxmode.offloads &=
2153                         ~DEV_RX_OFFLOAD_JUMBO_FRAME;
2154                 bp->flags &= ~BNXT_FLAG_JUMBO;
2155         }
2156
2157         eth_dev->data->dev_conf.rxmode.max_rx_pkt_len = new_pkt_size;
2158
2159         for (i = 0; i < bp->nr_vnics; i++) {
2160                 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
2161                 uint16_t size = 0;
2162
2163                 vnic->mru = new_mtu + RTE_ETHER_HDR_LEN +
2164                                 RTE_ETHER_CRC_LEN + VLAN_TAG_SIZE * 2;
2165                 rc = bnxt_hwrm_vnic_cfg(bp, vnic);
2166                 if (rc)
2167                         break;
2168
2169                 size = rte_pktmbuf_data_room_size(bp->rx_queues[0]->mb_pool);
2170                 size -= RTE_PKTMBUF_HEADROOM;
2171
2172                 if (size < new_mtu) {
2173                         rc = bnxt_hwrm_vnic_plcmode_cfg(bp, vnic);
2174                         if (rc)
2175                                 return rc;
2176                 }
2177         }
2178
2179         PMD_DRV_LOG(INFO, "New MTU is %d\n", new_mtu);
2180
2181         return rc;
2182 }
2183
2184 static int
2185 bnxt_vlan_pvid_set_op(struct rte_eth_dev *dev, uint16_t pvid, int on)
2186 {
2187         struct bnxt *bp = dev->data->dev_private;
2188         uint16_t vlan = bp->vlan;
2189         int rc;
2190
2191         rc = is_bnxt_in_error(bp);
2192         if (rc)
2193                 return rc;
2194
2195         if (!BNXT_SINGLE_PF(bp) || BNXT_VF(bp)) {
2196                 PMD_DRV_LOG(ERR,
2197                         "PVID cannot be modified for this function\n");
2198                 return -ENOTSUP;
2199         }
2200         bp->vlan = on ? pvid : 0;
2201
2202         rc = bnxt_hwrm_set_default_vlan(bp, 0, 0);
2203         if (rc)
2204                 bp->vlan = vlan;
2205         return rc;
2206 }
2207
2208 static int
2209 bnxt_dev_led_on_op(struct rte_eth_dev *dev)
2210 {
2211         struct bnxt *bp = dev->data->dev_private;
2212         int rc;
2213
2214         rc = is_bnxt_in_error(bp);
2215         if (rc)
2216                 return rc;
2217
2218         return bnxt_hwrm_port_led_cfg(bp, true);
2219 }
2220
2221 static int
2222 bnxt_dev_led_off_op(struct rte_eth_dev *dev)
2223 {
2224         struct bnxt *bp = dev->data->dev_private;
2225         int rc;
2226
2227         rc = is_bnxt_in_error(bp);
2228         if (rc)
2229                 return rc;
2230
2231         return bnxt_hwrm_port_led_cfg(bp, false);
2232 }
2233
2234 static uint32_t
2235 bnxt_rx_queue_count_op(struct rte_eth_dev *dev, uint16_t rx_queue_id)
2236 {
2237         struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
2238         uint32_t desc = 0, raw_cons = 0, cons;
2239         struct bnxt_cp_ring_info *cpr;
2240         struct bnxt_rx_queue *rxq;
2241         struct rx_pkt_cmpl *rxcmp;
2242         int rc;
2243
2244         rc = is_bnxt_in_error(bp);
2245         if (rc)
2246                 return rc;
2247
2248         rxq = dev->data->rx_queues[rx_queue_id];
2249         cpr = rxq->cp_ring;
2250         raw_cons = cpr->cp_raw_cons;
2251
2252         while (1) {
2253                 cons = RING_CMP(cpr->cp_ring_struct, raw_cons);
2254                 rte_prefetch0(&cpr->cp_desc_ring[cons]);
2255                 rxcmp = (struct rx_pkt_cmpl *)&cpr->cp_desc_ring[cons];
2256
2257                 if (!CMP_VALID(rxcmp, raw_cons, cpr->cp_ring_struct)) {
2258                         break;
2259                 } else {
2260                         raw_cons++;
2261                         desc++;
2262                 }
2263         }
2264
2265         return desc;
2266 }
2267
2268 static int
2269 bnxt_rx_descriptor_status_op(void *rx_queue, uint16_t offset)
2270 {
2271         struct bnxt_rx_queue *rxq = (struct bnxt_rx_queue *)rx_queue;
2272         struct bnxt_rx_ring_info *rxr;
2273         struct bnxt_cp_ring_info *cpr;
2274         struct bnxt_sw_rx_bd *rx_buf;
2275         struct rx_pkt_cmpl *rxcmp;
2276         uint32_t cons, cp_cons;
2277         int rc;
2278
2279         if (!rxq)
2280                 return -EINVAL;
2281
2282         rc = is_bnxt_in_error(rxq->bp);
2283         if (rc)
2284                 return rc;
2285
2286         cpr = rxq->cp_ring;
2287         rxr = rxq->rx_ring;
2288
2289         if (offset >= rxq->nb_rx_desc)
2290                 return -EINVAL;
2291
2292         cons = RING_CMP(cpr->cp_ring_struct, offset);
2293         cp_cons = cpr->cp_raw_cons;
2294         rxcmp = (struct rx_pkt_cmpl *)&cpr->cp_desc_ring[cons];
2295
2296         if (cons > cp_cons) {
2297                 if (CMPL_VALID(rxcmp, cpr->valid))
2298                         return RTE_ETH_RX_DESC_DONE;
2299         } else {
2300                 if (CMPL_VALID(rxcmp, !cpr->valid))
2301                         return RTE_ETH_RX_DESC_DONE;
2302         }
2303         rx_buf = &rxr->rx_buf_ring[cons];
2304         if (rx_buf->mbuf == NULL)
2305                 return RTE_ETH_RX_DESC_UNAVAIL;
2306
2307
2308         return RTE_ETH_RX_DESC_AVAIL;
2309 }
2310
2311 static int
2312 bnxt_tx_descriptor_status_op(void *tx_queue, uint16_t offset)
2313 {
2314         struct bnxt_tx_queue *txq = (struct bnxt_tx_queue *)tx_queue;
2315         struct bnxt_tx_ring_info *txr;
2316         struct bnxt_cp_ring_info *cpr;
2317         struct bnxt_sw_tx_bd *tx_buf;
2318         struct tx_pkt_cmpl *txcmp;
2319         uint32_t cons, cp_cons;
2320         int rc;
2321
2322         if (!txq)
2323                 return -EINVAL;
2324
2325         rc = is_bnxt_in_error(txq->bp);
2326         if (rc)
2327                 return rc;
2328
2329         cpr = txq->cp_ring;
2330         txr = txq->tx_ring;
2331
2332         if (offset >= txq->nb_tx_desc)
2333                 return -EINVAL;
2334
2335         cons = RING_CMP(cpr->cp_ring_struct, offset);
2336         txcmp = (struct tx_pkt_cmpl *)&cpr->cp_desc_ring[cons];
2337         cp_cons = cpr->cp_raw_cons;
2338
2339         if (cons > cp_cons) {
2340                 if (CMPL_VALID(txcmp, cpr->valid))
2341                         return RTE_ETH_TX_DESC_UNAVAIL;
2342         } else {
2343                 if (CMPL_VALID(txcmp, !cpr->valid))
2344                         return RTE_ETH_TX_DESC_UNAVAIL;
2345         }
2346         tx_buf = &txr->tx_buf_ring[cons];
2347         if (tx_buf->mbuf == NULL)
2348                 return RTE_ETH_TX_DESC_DONE;
2349
2350         return RTE_ETH_TX_DESC_FULL;
2351 }
2352
2353 static struct bnxt_filter_info *
2354 bnxt_match_and_validate_ether_filter(struct bnxt *bp,
2355                                 struct rte_eth_ethertype_filter *efilter,
2356                                 struct bnxt_vnic_info *vnic0,
2357                                 struct bnxt_vnic_info *vnic,
2358                                 int *ret)
2359 {
2360         struct bnxt_filter_info *mfilter = NULL;
2361         int match = 0;
2362         *ret = 0;
2363
2364         if (efilter->ether_type == RTE_ETHER_TYPE_IPV4 ||
2365                 efilter->ether_type == RTE_ETHER_TYPE_IPV6) {
2366                 PMD_DRV_LOG(ERR, "invalid ether_type(0x%04x) in"
2367                         " ethertype filter.", efilter->ether_type);
2368                 *ret = -EINVAL;
2369                 goto exit;
2370         }
2371         if (efilter->queue >= bp->rx_nr_rings) {
2372                 PMD_DRV_LOG(ERR, "Invalid queue %d\n", efilter->queue);
2373                 *ret = -EINVAL;
2374                 goto exit;
2375         }
2376
2377         vnic0 = &bp->vnic_info[0];
2378         vnic = &bp->vnic_info[efilter->queue];
2379         if (vnic == NULL) {
2380                 PMD_DRV_LOG(ERR, "Invalid queue %d\n", efilter->queue);
2381                 *ret = -EINVAL;
2382                 goto exit;
2383         }
2384
2385         if (efilter->flags & RTE_ETHTYPE_FLAGS_DROP) {
2386                 STAILQ_FOREACH(mfilter, &vnic0->filter, next) {
2387                         if ((!memcmp(efilter->mac_addr.addr_bytes,
2388                                      mfilter->l2_addr, RTE_ETHER_ADDR_LEN) &&
2389                              mfilter->flags ==
2390                              HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_DROP &&
2391                              mfilter->ethertype == efilter->ether_type)) {
2392                                 match = 1;
2393                                 break;
2394                         }
2395                 }
2396         } else {
2397                 STAILQ_FOREACH(mfilter, &vnic->filter, next)
2398                         if ((!memcmp(efilter->mac_addr.addr_bytes,
2399                                      mfilter->l2_addr, RTE_ETHER_ADDR_LEN) &&
2400                              mfilter->ethertype == efilter->ether_type &&
2401                              mfilter->flags ==
2402                              HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_PATH_RX)) {
2403                                 match = 1;
2404                                 break;
2405                         }
2406         }
2407
2408         if (match)
2409                 *ret = -EEXIST;
2410
2411 exit:
2412         return mfilter;
2413 }
2414
2415 static int
2416 bnxt_ethertype_filter(struct rte_eth_dev *dev,
2417                         enum rte_filter_op filter_op,
2418                         void *arg)
2419 {
2420         struct bnxt *bp = dev->data->dev_private;
2421         struct rte_eth_ethertype_filter *efilter =
2422                         (struct rte_eth_ethertype_filter *)arg;
2423         struct bnxt_filter_info *bfilter, *filter1;
2424         struct bnxt_vnic_info *vnic, *vnic0;
2425         int ret;
2426
2427         if (filter_op == RTE_ETH_FILTER_NOP)
2428                 return 0;
2429
2430         if (arg == NULL) {
2431                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
2432                             filter_op);
2433                 return -EINVAL;
2434         }
2435
2436         vnic0 = &bp->vnic_info[0];
2437         vnic = &bp->vnic_info[efilter->queue];
2438
2439         switch (filter_op) {
2440         case RTE_ETH_FILTER_ADD:
2441                 bnxt_match_and_validate_ether_filter(bp, efilter,
2442                                                         vnic0, vnic, &ret);
2443                 if (ret < 0)
2444                         return ret;
2445
2446                 bfilter = bnxt_get_unused_filter(bp);
2447                 if (bfilter == NULL) {
2448                         PMD_DRV_LOG(ERR,
2449                                 "Not enough resources for a new filter.\n");
2450                         return -ENOMEM;
2451                 }
2452                 bfilter->filter_type = HWRM_CFA_NTUPLE_FILTER;
2453                 memcpy(bfilter->l2_addr, efilter->mac_addr.addr_bytes,
2454                        RTE_ETHER_ADDR_LEN);
2455                 memcpy(bfilter->dst_macaddr, efilter->mac_addr.addr_bytes,
2456                        RTE_ETHER_ADDR_LEN);
2457                 bfilter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_MACADDR;
2458                 bfilter->ethertype = efilter->ether_type;
2459                 bfilter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2460
2461                 filter1 = bnxt_get_l2_filter(bp, bfilter, vnic0);
2462                 if (filter1 == NULL) {
2463                         ret = -EINVAL;
2464                         goto cleanup;
2465                 }
2466                 bfilter->enables |=
2467                         HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID;
2468                 bfilter->fw_l2_filter_id = filter1->fw_l2_filter_id;
2469
2470                 bfilter->dst_id = vnic->fw_vnic_id;
2471
2472                 if (efilter->flags & RTE_ETHTYPE_FLAGS_DROP) {
2473                         bfilter->flags =
2474                                 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_DROP;
2475                 }
2476
2477                 ret = bnxt_hwrm_set_ntuple_filter(bp, bfilter->dst_id, bfilter);
2478                 if (ret)
2479                         goto cleanup;
2480                 STAILQ_INSERT_TAIL(&vnic->filter, bfilter, next);
2481                 break;
2482         case RTE_ETH_FILTER_DELETE:
2483                 filter1 = bnxt_match_and_validate_ether_filter(bp, efilter,
2484                                                         vnic0, vnic, &ret);
2485                 if (ret == -EEXIST) {
2486                         ret = bnxt_hwrm_clear_ntuple_filter(bp, filter1);
2487
2488                         STAILQ_REMOVE(&vnic->filter, filter1, bnxt_filter_info,
2489                                       next);
2490                         bnxt_free_filter(bp, filter1);
2491                 } else if (ret == 0) {
2492                         PMD_DRV_LOG(ERR, "No matching filter found\n");
2493                 }
2494                 break;
2495         default:
2496                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
2497                 ret = -EINVAL;
2498                 goto error;
2499         }
2500         return ret;
2501 cleanup:
2502         bnxt_free_filter(bp, bfilter);
2503 error:
2504         return ret;
2505 }
2506
2507 static inline int
2508 parse_ntuple_filter(struct bnxt *bp,
2509                     struct rte_eth_ntuple_filter *nfilter,
2510                     struct bnxt_filter_info *bfilter)
2511 {
2512         uint32_t en = 0;
2513
2514         if (nfilter->queue >= bp->rx_nr_rings) {
2515                 PMD_DRV_LOG(ERR, "Invalid queue %d\n", nfilter->queue);
2516                 return -EINVAL;
2517         }
2518
2519         switch (nfilter->dst_port_mask) {
2520         case UINT16_MAX:
2521                 bfilter->dst_port_mask = -1;
2522                 bfilter->dst_port = nfilter->dst_port;
2523                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT |
2524                         NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
2525                 break;
2526         default:
2527                 PMD_DRV_LOG(ERR, "invalid dst_port mask.");
2528                 return -EINVAL;
2529         }
2530
2531         bfilter->ip_addr_type = NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4;
2532         en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2533
2534         switch (nfilter->proto_mask) {
2535         case UINT8_MAX:
2536                 if (nfilter->proto == 17) /* IPPROTO_UDP */
2537                         bfilter->ip_protocol = 17;
2538                 else if (nfilter->proto == 6) /* IPPROTO_TCP */
2539                         bfilter->ip_protocol = 6;
2540                 else
2541                         return -EINVAL;
2542                 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2543                 break;
2544         default:
2545                 PMD_DRV_LOG(ERR, "invalid protocol mask.");
2546                 return -EINVAL;
2547         }
2548
2549         switch (nfilter->dst_ip_mask) {
2550         case UINT32_MAX:
2551                 bfilter->dst_ipaddr_mask[0] = -1;
2552                 bfilter->dst_ipaddr[0] = nfilter->dst_ip;
2553                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR |
2554                         NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2555                 break;
2556         default:
2557                 PMD_DRV_LOG(ERR, "invalid dst_ip mask.");
2558                 return -EINVAL;
2559         }
2560
2561         switch (nfilter->src_ip_mask) {
2562         case UINT32_MAX:
2563                 bfilter->src_ipaddr_mask[0] = -1;
2564                 bfilter->src_ipaddr[0] = nfilter->src_ip;
2565                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR |
2566                         NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2567                 break;
2568         default:
2569                 PMD_DRV_LOG(ERR, "invalid src_ip mask.");
2570                 return -EINVAL;
2571         }
2572
2573         switch (nfilter->src_port_mask) {
2574         case UINT16_MAX:
2575                 bfilter->src_port_mask = -1;
2576                 bfilter->src_port = nfilter->src_port;
2577                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT |
2578                         NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
2579                 break;
2580         default:
2581                 PMD_DRV_LOG(ERR, "invalid src_port mask.");
2582                 return -EINVAL;
2583         }
2584
2585         //TODO Priority
2586         //nfilter->priority = (uint8_t)filter->priority;
2587
2588         bfilter->enables = en;
2589         return 0;
2590 }
2591
2592 static struct bnxt_filter_info*
2593 bnxt_match_ntuple_filter(struct bnxt *bp,
2594                          struct bnxt_filter_info *bfilter,
2595                          struct bnxt_vnic_info **mvnic)
2596 {
2597         struct bnxt_filter_info *mfilter = NULL;
2598         int i;
2599
2600         for (i = bp->nr_vnics - 1; i >= 0; i--) {
2601                 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
2602                 STAILQ_FOREACH(mfilter, &vnic->filter, next) {
2603                         if (bfilter->src_ipaddr[0] == mfilter->src_ipaddr[0] &&
2604                             bfilter->src_ipaddr_mask[0] ==
2605                             mfilter->src_ipaddr_mask[0] &&
2606                             bfilter->src_port == mfilter->src_port &&
2607                             bfilter->src_port_mask == mfilter->src_port_mask &&
2608                             bfilter->dst_ipaddr[0] == mfilter->dst_ipaddr[0] &&
2609                             bfilter->dst_ipaddr_mask[0] ==
2610                             mfilter->dst_ipaddr_mask[0] &&
2611                             bfilter->dst_port == mfilter->dst_port &&
2612                             bfilter->dst_port_mask == mfilter->dst_port_mask &&
2613                             bfilter->flags == mfilter->flags &&
2614                             bfilter->enables == mfilter->enables) {
2615                                 if (mvnic)
2616                                         *mvnic = vnic;
2617                                 return mfilter;
2618                         }
2619                 }
2620         }
2621         return NULL;
2622 }
2623
2624 static int
2625 bnxt_cfg_ntuple_filter(struct bnxt *bp,
2626                        struct rte_eth_ntuple_filter *nfilter,
2627                        enum rte_filter_op filter_op)
2628 {
2629         struct bnxt_filter_info *bfilter, *mfilter, *filter1;
2630         struct bnxt_vnic_info *vnic, *vnic0, *mvnic;
2631         int ret;
2632
2633         if (nfilter->flags != RTE_5TUPLE_FLAGS) {
2634                 PMD_DRV_LOG(ERR, "only 5tuple is supported.");
2635                 return -EINVAL;
2636         }
2637
2638         if (nfilter->flags & RTE_NTUPLE_FLAGS_TCP_FLAG) {
2639                 PMD_DRV_LOG(ERR, "Ntuple filter: TCP flags not supported\n");
2640                 return -EINVAL;
2641         }
2642
2643         bfilter = bnxt_get_unused_filter(bp);
2644         if (bfilter == NULL) {
2645                 PMD_DRV_LOG(ERR,
2646                         "Not enough resources for a new filter.\n");
2647                 return -ENOMEM;
2648         }
2649         ret = parse_ntuple_filter(bp, nfilter, bfilter);
2650         if (ret < 0)
2651                 goto free_filter;
2652
2653         vnic = &bp->vnic_info[nfilter->queue];
2654         vnic0 = &bp->vnic_info[0];
2655         filter1 = STAILQ_FIRST(&vnic0->filter);
2656         if (filter1 == NULL) {
2657                 ret = -EINVAL;
2658                 goto free_filter;
2659         }
2660
2661         bfilter->dst_id = vnic->fw_vnic_id;
2662         bfilter->fw_l2_filter_id = filter1->fw_l2_filter_id;
2663         bfilter->enables |=
2664                 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID;
2665         bfilter->ethertype = 0x800;
2666         bfilter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2667
2668         mfilter = bnxt_match_ntuple_filter(bp, bfilter, &mvnic);
2669
2670         if (mfilter != NULL && filter_op == RTE_ETH_FILTER_ADD &&
2671             bfilter->dst_id == mfilter->dst_id) {
2672                 PMD_DRV_LOG(ERR, "filter exists.\n");
2673                 ret = -EEXIST;
2674                 goto free_filter;
2675         } else if (mfilter != NULL && filter_op == RTE_ETH_FILTER_ADD &&
2676                    bfilter->dst_id != mfilter->dst_id) {
2677                 mfilter->dst_id = vnic->fw_vnic_id;
2678                 ret = bnxt_hwrm_set_ntuple_filter(bp, mfilter->dst_id, mfilter);
2679                 STAILQ_REMOVE(&mvnic->filter, mfilter, bnxt_filter_info, next);
2680                 STAILQ_INSERT_TAIL(&vnic->filter, mfilter, next);
2681                 PMD_DRV_LOG(ERR, "filter with matching pattern exists.\n");
2682                 PMD_DRV_LOG(ERR, " Updated it to the new destination queue\n");
2683                 goto free_filter;
2684         }
2685         if (mfilter == NULL && filter_op == RTE_ETH_FILTER_DELETE) {
2686                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
2687                 ret = -ENOENT;
2688                 goto free_filter;
2689         }
2690
2691         if (filter_op == RTE_ETH_FILTER_ADD) {
2692                 bfilter->filter_type = HWRM_CFA_NTUPLE_FILTER;
2693                 ret = bnxt_hwrm_set_ntuple_filter(bp, bfilter->dst_id, bfilter);
2694                 if (ret)
2695                         goto free_filter;
2696                 STAILQ_INSERT_TAIL(&vnic->filter, bfilter, next);
2697         } else {
2698                 if (mfilter == NULL) {
2699                         /* This should not happen. But for Coverity! */
2700                         ret = -ENOENT;
2701                         goto free_filter;
2702                 }
2703                 ret = bnxt_hwrm_clear_ntuple_filter(bp, mfilter);
2704
2705                 STAILQ_REMOVE(&vnic->filter, mfilter, bnxt_filter_info, next);
2706                 bnxt_free_filter(bp, mfilter);
2707                 mfilter->fw_l2_filter_id = -1;
2708                 bnxt_free_filter(bp, bfilter);
2709                 bfilter->fw_l2_filter_id = -1;
2710         }
2711
2712         return 0;
2713 free_filter:
2714         bfilter->fw_l2_filter_id = -1;
2715         bnxt_free_filter(bp, bfilter);
2716         return ret;
2717 }
2718
2719 static int
2720 bnxt_ntuple_filter(struct rte_eth_dev *dev,
2721                         enum rte_filter_op filter_op,
2722                         void *arg)
2723 {
2724         struct bnxt *bp = dev->data->dev_private;
2725         int ret;
2726
2727         if (filter_op == RTE_ETH_FILTER_NOP)
2728                 return 0;
2729
2730         if (arg == NULL) {
2731                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
2732                             filter_op);
2733                 return -EINVAL;
2734         }
2735
2736         switch (filter_op) {
2737         case RTE_ETH_FILTER_ADD:
2738                 ret = bnxt_cfg_ntuple_filter(bp,
2739                         (struct rte_eth_ntuple_filter *)arg,
2740                         filter_op);
2741                 break;
2742         case RTE_ETH_FILTER_DELETE:
2743                 ret = bnxt_cfg_ntuple_filter(bp,
2744                         (struct rte_eth_ntuple_filter *)arg,
2745                         filter_op);
2746                 break;
2747         default:
2748                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
2749                 ret = -EINVAL;
2750                 break;
2751         }
2752         return ret;
2753 }
2754
2755 static int
2756 bnxt_parse_fdir_filter(struct bnxt *bp,
2757                        struct rte_eth_fdir_filter *fdir,
2758                        struct bnxt_filter_info *filter)
2759 {
2760         enum rte_fdir_mode fdir_mode =
2761                 bp->eth_dev->data->dev_conf.fdir_conf.mode;
2762         struct bnxt_vnic_info *vnic0, *vnic;
2763         struct bnxt_filter_info *filter1;
2764         uint32_t en = 0;
2765         int i;
2766
2767         if (fdir_mode == RTE_FDIR_MODE_PERFECT_TUNNEL)
2768                 return -EINVAL;
2769
2770         filter->l2_ovlan = fdir->input.flow_ext.vlan_tci;
2771         en |= EM_FLOW_ALLOC_INPUT_EN_OVLAN_VID;
2772
2773         switch (fdir->input.flow_type) {
2774         case RTE_ETH_FLOW_IPV4:
2775         case RTE_ETH_FLOW_NONFRAG_IPV4_OTHER:
2776                 /* FALLTHROUGH */
2777                 filter->src_ipaddr[0] = fdir->input.flow.ip4_flow.src_ip;
2778                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
2779                 filter->dst_ipaddr[0] = fdir->input.flow.ip4_flow.dst_ip;
2780                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
2781                 filter->ip_protocol = fdir->input.flow.ip4_flow.proto;
2782                 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2783                 filter->ip_addr_type =
2784                         NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4;
2785                 filter->src_ipaddr_mask[0] = 0xffffffff;
2786                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2787                 filter->dst_ipaddr_mask[0] = 0xffffffff;
2788                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2789                 filter->ethertype = 0x800;
2790                 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2791                 break;
2792         case RTE_ETH_FLOW_NONFRAG_IPV4_TCP:
2793                 filter->src_port = fdir->input.flow.tcp4_flow.src_port;
2794                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT;
2795                 filter->dst_port = fdir->input.flow.tcp4_flow.dst_port;
2796                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT;
2797                 filter->dst_port_mask = 0xffff;
2798                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
2799                 filter->src_port_mask = 0xffff;
2800                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
2801                 filter->src_ipaddr[0] = fdir->input.flow.tcp4_flow.ip.src_ip;
2802                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
2803                 filter->dst_ipaddr[0] = fdir->input.flow.tcp4_flow.ip.dst_ip;
2804                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
2805                 filter->ip_protocol = 6;
2806                 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2807                 filter->ip_addr_type =
2808                         NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4;
2809                 filter->src_ipaddr_mask[0] = 0xffffffff;
2810                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2811                 filter->dst_ipaddr_mask[0] = 0xffffffff;
2812                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2813                 filter->ethertype = 0x800;
2814                 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2815                 break;
2816         case RTE_ETH_FLOW_NONFRAG_IPV4_UDP:
2817                 filter->src_port = fdir->input.flow.udp4_flow.src_port;
2818                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT;
2819                 filter->dst_port = fdir->input.flow.udp4_flow.dst_port;
2820                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT;
2821                 filter->dst_port_mask = 0xffff;
2822                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
2823                 filter->src_port_mask = 0xffff;
2824                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
2825                 filter->src_ipaddr[0] = fdir->input.flow.udp4_flow.ip.src_ip;
2826                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
2827                 filter->dst_ipaddr[0] = fdir->input.flow.udp4_flow.ip.dst_ip;
2828                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
2829                 filter->ip_protocol = 17;
2830                 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2831                 filter->ip_addr_type =
2832                         NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4;
2833                 filter->src_ipaddr_mask[0] = 0xffffffff;
2834                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2835                 filter->dst_ipaddr_mask[0] = 0xffffffff;
2836                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2837                 filter->ethertype = 0x800;
2838                 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2839                 break;
2840         case RTE_ETH_FLOW_IPV6:
2841         case RTE_ETH_FLOW_NONFRAG_IPV6_OTHER:
2842                 /* FALLTHROUGH */
2843                 filter->ip_addr_type =
2844                         NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV6;
2845                 filter->ip_protocol = fdir->input.flow.ipv6_flow.proto;
2846                 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2847                 rte_memcpy(filter->src_ipaddr,
2848                            fdir->input.flow.ipv6_flow.src_ip, 16);
2849                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
2850                 rte_memcpy(filter->dst_ipaddr,
2851                            fdir->input.flow.ipv6_flow.dst_ip, 16);
2852                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
2853                 memset(filter->dst_ipaddr_mask, 0xff, 16);
2854                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2855                 memset(filter->src_ipaddr_mask, 0xff, 16);
2856                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2857                 filter->ethertype = 0x86dd;
2858                 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2859                 break;
2860         case RTE_ETH_FLOW_NONFRAG_IPV6_TCP:
2861                 filter->src_port = fdir->input.flow.tcp6_flow.src_port;
2862                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT;
2863                 filter->dst_port = fdir->input.flow.tcp6_flow.dst_port;
2864                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT;
2865                 filter->dst_port_mask = 0xffff;
2866                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
2867                 filter->src_port_mask = 0xffff;
2868                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
2869                 filter->ip_addr_type =
2870                         NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV6;
2871                 filter->ip_protocol = fdir->input.flow.tcp6_flow.ip.proto;
2872                 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2873                 rte_memcpy(filter->src_ipaddr,
2874                            fdir->input.flow.tcp6_flow.ip.src_ip, 16);
2875                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
2876                 rte_memcpy(filter->dst_ipaddr,
2877                            fdir->input.flow.tcp6_flow.ip.dst_ip, 16);
2878                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
2879                 memset(filter->dst_ipaddr_mask, 0xff, 16);
2880                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2881                 memset(filter->src_ipaddr_mask, 0xff, 16);
2882                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2883                 filter->ethertype = 0x86dd;
2884                 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2885                 break;
2886         case RTE_ETH_FLOW_NONFRAG_IPV6_UDP:
2887                 filter->src_port = fdir->input.flow.udp6_flow.src_port;
2888                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT;
2889                 filter->dst_port = fdir->input.flow.udp6_flow.dst_port;
2890                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT;
2891                 filter->dst_port_mask = 0xffff;
2892                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
2893                 filter->src_port_mask = 0xffff;
2894                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
2895                 filter->ip_addr_type =
2896                         NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV6;
2897                 filter->ip_protocol = fdir->input.flow.udp6_flow.ip.proto;
2898                 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2899                 rte_memcpy(filter->src_ipaddr,
2900                            fdir->input.flow.udp6_flow.ip.src_ip, 16);
2901                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
2902                 rte_memcpy(filter->dst_ipaddr,
2903                            fdir->input.flow.udp6_flow.ip.dst_ip, 16);
2904                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
2905                 memset(filter->dst_ipaddr_mask, 0xff, 16);
2906                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2907                 memset(filter->src_ipaddr_mask, 0xff, 16);
2908                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2909                 filter->ethertype = 0x86dd;
2910                 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2911                 break;
2912         case RTE_ETH_FLOW_L2_PAYLOAD:
2913                 filter->ethertype = fdir->input.flow.l2_flow.ether_type;
2914                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2915                 break;
2916         case RTE_ETH_FLOW_VXLAN:
2917                 if (fdir->action.behavior == RTE_ETH_FDIR_REJECT)
2918                         return -EINVAL;
2919                 filter->vni = fdir->input.flow.tunnel_flow.tunnel_id;
2920                 filter->tunnel_type =
2921                         CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN;
2922                 en |= HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_TUNNEL_TYPE;
2923                 break;
2924         case RTE_ETH_FLOW_NVGRE:
2925                 if (fdir->action.behavior == RTE_ETH_FDIR_REJECT)
2926                         return -EINVAL;
2927                 filter->vni = fdir->input.flow.tunnel_flow.tunnel_id;
2928                 filter->tunnel_type =
2929                         CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_NVGRE;
2930                 en |= HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_TUNNEL_TYPE;
2931                 break;
2932         case RTE_ETH_FLOW_UNKNOWN:
2933         case RTE_ETH_FLOW_RAW:
2934         case RTE_ETH_FLOW_FRAG_IPV4:
2935         case RTE_ETH_FLOW_NONFRAG_IPV4_SCTP:
2936         case RTE_ETH_FLOW_FRAG_IPV6:
2937         case RTE_ETH_FLOW_NONFRAG_IPV6_SCTP:
2938         case RTE_ETH_FLOW_IPV6_EX:
2939         case RTE_ETH_FLOW_IPV6_TCP_EX:
2940         case RTE_ETH_FLOW_IPV6_UDP_EX:
2941         case RTE_ETH_FLOW_GENEVE:
2942                 /* FALLTHROUGH */
2943         default:
2944                 return -EINVAL;
2945         }
2946
2947         vnic0 = &bp->vnic_info[0];
2948         vnic = &bp->vnic_info[fdir->action.rx_queue];
2949         if (vnic == NULL) {
2950                 PMD_DRV_LOG(ERR, "Invalid queue %d\n", fdir->action.rx_queue);
2951                 return -EINVAL;
2952         }
2953
2954
2955         if (fdir_mode == RTE_FDIR_MODE_PERFECT_MAC_VLAN) {
2956                 rte_memcpy(filter->dst_macaddr,
2957                         fdir->input.flow.mac_vlan_flow.mac_addr.addr_bytes, 6);
2958                         en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_MACADDR;
2959         }
2960
2961         if (fdir->action.behavior == RTE_ETH_FDIR_REJECT) {
2962                 filter->flags = HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_DROP;
2963                 filter1 = STAILQ_FIRST(&vnic0->filter);
2964                 //filter1 = bnxt_get_l2_filter(bp, filter, vnic0);
2965         } else {
2966                 filter->dst_id = vnic->fw_vnic_id;
2967                 for (i = 0; i < RTE_ETHER_ADDR_LEN; i++)
2968                         if (filter->dst_macaddr[i] == 0x00)
2969                                 filter1 = STAILQ_FIRST(&vnic0->filter);
2970                         else
2971                                 filter1 = bnxt_get_l2_filter(bp, filter, vnic);
2972         }
2973
2974         if (filter1 == NULL)
2975                 return -EINVAL;
2976
2977         en |= HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID;
2978         filter->fw_l2_filter_id = filter1->fw_l2_filter_id;
2979
2980         filter->enables = en;
2981
2982         return 0;
2983 }
2984
2985 static struct bnxt_filter_info *
2986 bnxt_match_fdir(struct bnxt *bp, struct bnxt_filter_info *nf,
2987                 struct bnxt_vnic_info **mvnic)
2988 {
2989         struct bnxt_filter_info *mf = NULL;
2990         int i;
2991
2992         for (i = bp->nr_vnics - 1; i >= 0; i--) {
2993                 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
2994
2995                 STAILQ_FOREACH(mf, &vnic->filter, next) {
2996                         if (mf->filter_type == nf->filter_type &&
2997                             mf->flags == nf->flags &&
2998                             mf->src_port == nf->src_port &&
2999                             mf->src_port_mask == nf->src_port_mask &&
3000                             mf->dst_port == nf->dst_port &&
3001                             mf->dst_port_mask == nf->dst_port_mask &&
3002                             mf->ip_protocol == nf->ip_protocol &&
3003                             mf->ip_addr_type == nf->ip_addr_type &&
3004                             mf->ethertype == nf->ethertype &&
3005                             mf->vni == nf->vni &&
3006                             mf->tunnel_type == nf->tunnel_type &&
3007                             mf->l2_ovlan == nf->l2_ovlan &&
3008                             mf->l2_ovlan_mask == nf->l2_ovlan_mask &&
3009                             mf->l2_ivlan == nf->l2_ivlan &&
3010                             mf->l2_ivlan_mask == nf->l2_ivlan_mask &&
3011                             !memcmp(mf->l2_addr, nf->l2_addr,
3012                                     RTE_ETHER_ADDR_LEN) &&
3013                             !memcmp(mf->l2_addr_mask, nf->l2_addr_mask,
3014                                     RTE_ETHER_ADDR_LEN) &&
3015                             !memcmp(mf->src_macaddr, nf->src_macaddr,
3016                                     RTE_ETHER_ADDR_LEN) &&
3017                             !memcmp(mf->dst_macaddr, nf->dst_macaddr,
3018                                     RTE_ETHER_ADDR_LEN) &&
3019                             !memcmp(mf->src_ipaddr, nf->src_ipaddr,
3020                                     sizeof(nf->src_ipaddr)) &&
3021                             !memcmp(mf->src_ipaddr_mask, nf->src_ipaddr_mask,
3022                                     sizeof(nf->src_ipaddr_mask)) &&
3023                             !memcmp(mf->dst_ipaddr, nf->dst_ipaddr,
3024                                     sizeof(nf->dst_ipaddr)) &&
3025                             !memcmp(mf->dst_ipaddr_mask, nf->dst_ipaddr_mask,
3026                                     sizeof(nf->dst_ipaddr_mask))) {
3027                                 if (mvnic)
3028                                         *mvnic = vnic;
3029                                 return mf;
3030                         }
3031                 }
3032         }
3033         return NULL;
3034 }
3035
3036 static int
3037 bnxt_fdir_filter(struct rte_eth_dev *dev,
3038                  enum rte_filter_op filter_op,
3039                  void *arg)
3040 {
3041         struct bnxt *bp = dev->data->dev_private;
3042         struct rte_eth_fdir_filter *fdir  = (struct rte_eth_fdir_filter *)arg;
3043         struct bnxt_filter_info *filter, *match;
3044         struct bnxt_vnic_info *vnic, *mvnic;
3045         int ret = 0, i;
3046
3047         if (filter_op == RTE_ETH_FILTER_NOP)
3048                 return 0;
3049
3050         if (arg == NULL && filter_op != RTE_ETH_FILTER_FLUSH)
3051                 return -EINVAL;
3052
3053         switch (filter_op) {
3054         case RTE_ETH_FILTER_ADD:
3055         case RTE_ETH_FILTER_DELETE:
3056                 /* FALLTHROUGH */
3057                 filter = bnxt_get_unused_filter(bp);
3058                 if (filter == NULL) {
3059                         PMD_DRV_LOG(ERR,
3060                                 "Not enough resources for a new flow.\n");
3061                         return -ENOMEM;
3062                 }
3063
3064                 ret = bnxt_parse_fdir_filter(bp, fdir, filter);
3065                 if (ret != 0)
3066                         goto free_filter;
3067                 filter->filter_type = HWRM_CFA_NTUPLE_FILTER;
3068
3069                 if (fdir->action.behavior == RTE_ETH_FDIR_REJECT)
3070                         vnic = &bp->vnic_info[0];
3071                 else
3072                         vnic = &bp->vnic_info[fdir->action.rx_queue];
3073
3074                 match = bnxt_match_fdir(bp, filter, &mvnic);
3075                 if (match != NULL && filter_op == RTE_ETH_FILTER_ADD) {
3076                         if (match->dst_id == vnic->fw_vnic_id) {
3077                                 PMD_DRV_LOG(ERR, "Flow already exists.\n");
3078                                 ret = -EEXIST;
3079                                 goto free_filter;
3080                         } else {
3081                                 match->dst_id = vnic->fw_vnic_id;
3082                                 ret = bnxt_hwrm_set_ntuple_filter(bp,
3083                                                                   match->dst_id,
3084                                                                   match);
3085                                 STAILQ_REMOVE(&mvnic->filter, match,
3086                                               bnxt_filter_info, next);
3087                                 STAILQ_INSERT_TAIL(&vnic->filter, match, next);
3088                                 PMD_DRV_LOG(ERR,
3089                                         "Filter with matching pattern exist\n");
3090                                 PMD_DRV_LOG(ERR,
3091                                         "Updated it to new destination q\n");
3092                                 goto free_filter;
3093                         }
3094                 }
3095                 if (match == NULL && filter_op == RTE_ETH_FILTER_DELETE) {
3096                         PMD_DRV_LOG(ERR, "Flow does not exist.\n");
3097                         ret = -ENOENT;
3098                         goto free_filter;
3099                 }
3100
3101                 if (filter_op == RTE_ETH_FILTER_ADD) {
3102                         ret = bnxt_hwrm_set_ntuple_filter(bp,
3103                                                           filter->dst_id,
3104                                                           filter);
3105                         if (ret)
3106                                 goto free_filter;
3107                         STAILQ_INSERT_TAIL(&vnic->filter, filter, next);
3108                 } else {
3109                         ret = bnxt_hwrm_clear_ntuple_filter(bp, match);
3110                         STAILQ_REMOVE(&vnic->filter, match,
3111                                       bnxt_filter_info, next);
3112                         bnxt_free_filter(bp, match);
3113                         filter->fw_l2_filter_id = -1;
3114                         bnxt_free_filter(bp, filter);
3115                 }
3116                 break;
3117         case RTE_ETH_FILTER_FLUSH:
3118                 for (i = bp->nr_vnics - 1; i >= 0; i--) {
3119                         struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
3120
3121                         STAILQ_FOREACH(filter, &vnic->filter, next) {
3122                                 if (filter->filter_type ==
3123                                     HWRM_CFA_NTUPLE_FILTER) {
3124                                         ret =
3125                                         bnxt_hwrm_clear_ntuple_filter(bp,
3126                                                                       filter);
3127                                         STAILQ_REMOVE(&vnic->filter, filter,
3128                                                       bnxt_filter_info, next);
3129                                 }
3130                         }
3131                 }
3132                 return ret;
3133         case RTE_ETH_FILTER_UPDATE:
3134         case RTE_ETH_FILTER_STATS:
3135         case RTE_ETH_FILTER_INFO:
3136                 PMD_DRV_LOG(ERR, "operation %u not implemented", filter_op);
3137                 break;
3138         default:
3139                 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
3140                 ret = -EINVAL;
3141                 break;
3142         }
3143         return ret;
3144
3145 free_filter:
3146         filter->fw_l2_filter_id = -1;
3147         bnxt_free_filter(bp, filter);
3148         return ret;
3149 }
3150
3151 static int
3152 bnxt_filter_ctrl_op(struct rte_eth_dev *dev __rte_unused,
3153                     enum rte_filter_type filter_type,
3154                     enum rte_filter_op filter_op, void *arg)
3155 {
3156         int ret = 0;
3157
3158         ret = is_bnxt_in_error(dev->data->dev_private);
3159         if (ret)
3160                 return ret;
3161
3162         switch (filter_type) {
3163         case RTE_ETH_FILTER_TUNNEL:
3164                 PMD_DRV_LOG(ERR,
3165                         "filter type: %d: To be implemented\n", filter_type);
3166                 break;
3167         case RTE_ETH_FILTER_FDIR:
3168                 ret = bnxt_fdir_filter(dev, filter_op, arg);
3169                 break;
3170         case RTE_ETH_FILTER_NTUPLE:
3171                 ret = bnxt_ntuple_filter(dev, filter_op, arg);
3172                 break;
3173         case RTE_ETH_FILTER_ETHERTYPE:
3174                 ret = bnxt_ethertype_filter(dev, filter_op, arg);
3175                 break;
3176         case RTE_ETH_FILTER_GENERIC:
3177                 if (filter_op != RTE_ETH_FILTER_GET)
3178                         return -EINVAL;
3179                 *(const void **)arg = &bnxt_flow_ops;
3180                 break;
3181         default:
3182                 PMD_DRV_LOG(ERR,
3183                         "Filter type (%d) not supported", filter_type);
3184                 ret = -EINVAL;
3185                 break;
3186         }
3187         return ret;
3188 }
3189
3190 static const uint32_t *
3191 bnxt_dev_supported_ptypes_get_op(struct rte_eth_dev *dev)
3192 {
3193         static const uint32_t ptypes[] = {
3194                 RTE_PTYPE_L2_ETHER_VLAN,
3195                 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN,
3196                 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN,
3197                 RTE_PTYPE_L4_ICMP,
3198                 RTE_PTYPE_L4_TCP,
3199                 RTE_PTYPE_L4_UDP,
3200                 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN,
3201                 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN,
3202                 RTE_PTYPE_INNER_L4_ICMP,
3203                 RTE_PTYPE_INNER_L4_TCP,
3204                 RTE_PTYPE_INNER_L4_UDP,
3205                 RTE_PTYPE_UNKNOWN
3206         };
3207
3208         if (!dev->rx_pkt_burst)
3209                 return NULL;
3210
3211         return ptypes;
3212 }
3213
3214 static int bnxt_map_regs(struct bnxt *bp, uint32_t *reg_arr, int count,
3215                          int reg_win)
3216 {
3217         uint32_t reg_base = *reg_arr & 0xfffff000;
3218         uint32_t win_off;
3219         int i;
3220
3221         for (i = 0; i < count; i++) {
3222                 if ((reg_arr[i] & 0xfffff000) != reg_base)
3223                         return -ERANGE;
3224         }
3225         win_off = BNXT_GRCPF_REG_WINDOW_BASE_OUT + (reg_win - 1) * 4;
3226         rte_write32(reg_base, (uint8_t *)bp->bar0 + win_off);
3227         return 0;
3228 }
3229
3230 static int bnxt_map_ptp_regs(struct bnxt *bp)
3231 {
3232         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3233         uint32_t *reg_arr;
3234         int rc, i;
3235
3236         reg_arr = ptp->rx_regs;
3237         rc = bnxt_map_regs(bp, reg_arr, BNXT_PTP_RX_REGS, 5);
3238         if (rc)
3239                 return rc;
3240
3241         reg_arr = ptp->tx_regs;
3242         rc = bnxt_map_regs(bp, reg_arr, BNXT_PTP_TX_REGS, 6);
3243         if (rc)
3244                 return rc;
3245
3246         for (i = 0; i < BNXT_PTP_RX_REGS; i++)
3247                 ptp->rx_mapped_regs[i] = 0x5000 + (ptp->rx_regs[i] & 0xfff);
3248
3249         for (i = 0; i < BNXT_PTP_TX_REGS; i++)
3250                 ptp->tx_mapped_regs[i] = 0x6000 + (ptp->tx_regs[i] & 0xfff);
3251
3252         return 0;
3253 }
3254
3255 static void bnxt_unmap_ptp_regs(struct bnxt *bp)
3256 {
3257         rte_write32(0, (uint8_t *)bp->bar0 +
3258                          BNXT_GRCPF_REG_WINDOW_BASE_OUT + 16);
3259         rte_write32(0, (uint8_t *)bp->bar0 +
3260                          BNXT_GRCPF_REG_WINDOW_BASE_OUT + 20);
3261 }
3262
3263 static uint64_t bnxt_cc_read(struct bnxt *bp)
3264 {
3265         uint64_t ns;
3266
3267         ns = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3268                               BNXT_GRCPF_REG_SYNC_TIME));
3269         ns |= (uint64_t)(rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3270                                           BNXT_GRCPF_REG_SYNC_TIME + 4))) << 32;
3271         return ns;
3272 }
3273
3274 static int bnxt_get_tx_ts(struct bnxt *bp, uint64_t *ts)
3275 {
3276         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3277         uint32_t fifo;
3278
3279         fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3280                                 ptp->tx_mapped_regs[BNXT_PTP_TX_FIFO]));
3281         if (fifo & BNXT_PTP_TX_FIFO_EMPTY)
3282                 return -EAGAIN;
3283
3284         fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3285                                 ptp->tx_mapped_regs[BNXT_PTP_TX_FIFO]));
3286         *ts = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3287                                 ptp->tx_mapped_regs[BNXT_PTP_TX_TS_L]));
3288         *ts |= (uint64_t)rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3289                                 ptp->tx_mapped_regs[BNXT_PTP_TX_TS_H])) << 32;
3290
3291         return 0;
3292 }
3293
3294 static int bnxt_get_rx_ts(struct bnxt *bp, uint64_t *ts)
3295 {
3296         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3297         struct bnxt_pf_info *pf = &bp->pf;
3298         uint16_t port_id;
3299         uint32_t fifo;
3300
3301         if (!ptp)
3302                 return -ENODEV;
3303
3304         fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3305                                 ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO]));
3306         if (!(fifo & BNXT_PTP_RX_FIFO_PENDING))
3307                 return -EAGAIN;
3308
3309         port_id = pf->port_id;
3310         rte_write32(1 << port_id, (uint8_t *)bp->bar0 +
3311                ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO_ADV]);
3312
3313         fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3314                                    ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO]));
3315         if (fifo & BNXT_PTP_RX_FIFO_PENDING) {
3316 /*              bnxt_clr_rx_ts(bp);       TBD  */
3317                 return -EBUSY;
3318         }
3319
3320         *ts = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3321                                 ptp->rx_mapped_regs[BNXT_PTP_RX_TS_L]));
3322         *ts |= (uint64_t)rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3323                                 ptp->rx_mapped_regs[BNXT_PTP_RX_TS_H])) << 32;
3324
3325         return 0;
3326 }
3327
3328 static int
3329 bnxt_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
3330 {
3331         uint64_t ns;
3332         struct bnxt *bp = dev->data->dev_private;
3333         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3334
3335         if (!ptp)
3336                 return 0;
3337
3338         ns = rte_timespec_to_ns(ts);
3339         /* Set the timecounters to a new value. */
3340         ptp->tc.nsec = ns;
3341
3342         return 0;
3343 }
3344
3345 static int
3346 bnxt_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
3347 {
3348         struct bnxt *bp = dev->data->dev_private;
3349         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3350         uint64_t ns, systime_cycles = 0;
3351         int rc = 0;
3352
3353         if (!ptp)
3354                 return 0;
3355
3356         if (BNXT_CHIP_THOR(bp))
3357                 rc = bnxt_hwrm_port_ts_query(bp, BNXT_PTP_FLAGS_CURRENT_TIME,
3358                                              &systime_cycles);
3359         else
3360                 systime_cycles = bnxt_cc_read(bp);
3361
3362         ns = rte_timecounter_update(&ptp->tc, systime_cycles);
3363         *ts = rte_ns_to_timespec(ns);
3364
3365         return rc;
3366 }
3367 static int
3368 bnxt_timesync_enable(struct rte_eth_dev *dev)
3369 {
3370         struct bnxt *bp = dev->data->dev_private;
3371         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3372         uint32_t shift = 0;
3373         int rc;
3374
3375         if (!ptp)
3376                 return 0;
3377
3378         ptp->rx_filter = 1;
3379         ptp->tx_tstamp_en = 1;
3380         ptp->rxctl = BNXT_PTP_MSG_EVENTS;
3381
3382         rc = bnxt_hwrm_ptp_cfg(bp);
3383         if (rc)
3384                 return rc;
3385
3386         memset(&ptp->tc, 0, sizeof(struct rte_timecounter));
3387         memset(&ptp->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
3388         memset(&ptp->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
3389
3390         ptp->tc.cc_mask = BNXT_CYCLECOUNTER_MASK;
3391         ptp->tc.cc_shift = shift;
3392         ptp->tc.nsec_mask = (1ULL << shift) - 1;
3393
3394         ptp->rx_tstamp_tc.cc_mask = BNXT_CYCLECOUNTER_MASK;
3395         ptp->rx_tstamp_tc.cc_shift = shift;
3396         ptp->rx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
3397
3398         ptp->tx_tstamp_tc.cc_mask = BNXT_CYCLECOUNTER_MASK;
3399         ptp->tx_tstamp_tc.cc_shift = shift;
3400         ptp->tx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
3401
3402         if (!BNXT_CHIP_THOR(bp))
3403                 bnxt_map_ptp_regs(bp);
3404
3405         return 0;
3406 }
3407
3408 static int
3409 bnxt_timesync_disable(struct rte_eth_dev *dev)
3410 {
3411         struct bnxt *bp = dev->data->dev_private;
3412         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3413
3414         if (!ptp)
3415                 return 0;
3416
3417         ptp->rx_filter = 0;
3418         ptp->tx_tstamp_en = 0;
3419         ptp->rxctl = 0;
3420
3421         bnxt_hwrm_ptp_cfg(bp);
3422
3423         if (!BNXT_CHIP_THOR(bp))
3424                 bnxt_unmap_ptp_regs(bp);
3425
3426         return 0;
3427 }
3428
3429 static int
3430 bnxt_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
3431                                  struct timespec *timestamp,
3432                                  uint32_t flags __rte_unused)
3433 {
3434         struct bnxt *bp = dev->data->dev_private;
3435         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3436         uint64_t rx_tstamp_cycles = 0;
3437         uint64_t ns;
3438
3439         if (!ptp)
3440                 return 0;
3441
3442         if (BNXT_CHIP_THOR(bp))
3443                 rx_tstamp_cycles = ptp->rx_timestamp;
3444         else
3445                 bnxt_get_rx_ts(bp, &rx_tstamp_cycles);
3446
3447         ns = rte_timecounter_update(&ptp->rx_tstamp_tc, rx_tstamp_cycles);
3448         *timestamp = rte_ns_to_timespec(ns);
3449         return  0;
3450 }
3451
3452 static int
3453 bnxt_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
3454                                  struct timespec *timestamp)
3455 {
3456         struct bnxt *bp = dev->data->dev_private;
3457         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3458         uint64_t tx_tstamp_cycles = 0;
3459         uint64_t ns;
3460         int rc = 0;
3461
3462         if (!ptp)
3463                 return 0;
3464
3465         if (BNXT_CHIP_THOR(bp))
3466                 rc = bnxt_hwrm_port_ts_query(bp, BNXT_PTP_FLAGS_PATH_TX,
3467                                              &tx_tstamp_cycles);
3468         else
3469                 rc = bnxt_get_tx_ts(bp, &tx_tstamp_cycles);
3470
3471         ns = rte_timecounter_update(&ptp->tx_tstamp_tc, tx_tstamp_cycles);
3472         *timestamp = rte_ns_to_timespec(ns);
3473
3474         return rc;
3475 }
3476
3477 static int
3478 bnxt_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
3479 {
3480         struct bnxt *bp = dev->data->dev_private;
3481         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3482
3483         if (!ptp)
3484                 return 0;
3485
3486         ptp->tc.nsec += delta;
3487
3488         return 0;
3489 }
3490
3491 static int
3492 bnxt_get_eeprom_length_op(struct rte_eth_dev *dev)
3493 {
3494         struct bnxt *bp = dev->data->dev_private;
3495         int rc;
3496         uint32_t dir_entries;
3497         uint32_t entry_length;
3498
3499         rc = is_bnxt_in_error(bp);
3500         if (rc)
3501                 return rc;
3502
3503         PMD_DRV_LOG(INFO, "%04x:%02x:%02x:%02x\n",
3504                 bp->pdev->addr.domain, bp->pdev->addr.bus,
3505                 bp->pdev->addr.devid, bp->pdev->addr.function);
3506
3507         rc = bnxt_hwrm_nvm_get_dir_info(bp, &dir_entries, &entry_length);
3508         if (rc != 0)
3509                 return rc;
3510
3511         return dir_entries * entry_length;
3512 }
3513
3514 static int
3515 bnxt_get_eeprom_op(struct rte_eth_dev *dev,
3516                 struct rte_dev_eeprom_info *in_eeprom)
3517 {
3518         struct bnxt *bp = dev->data->dev_private;
3519         uint32_t index;
3520         uint32_t offset;
3521         int rc;
3522
3523         rc = is_bnxt_in_error(bp);
3524         if (rc)
3525                 return rc;
3526
3527         PMD_DRV_LOG(INFO, "%04x:%02x:%02x:%02x in_eeprom->offset = %d "
3528                 "len = %d\n", bp->pdev->addr.domain,
3529                 bp->pdev->addr.bus, bp->pdev->addr.devid,
3530                 bp->pdev->addr.function, in_eeprom->offset, in_eeprom->length);
3531
3532         if (in_eeprom->offset == 0) /* special offset value to get directory */
3533                 return bnxt_get_nvram_directory(bp, in_eeprom->length,
3534                                                 in_eeprom->data);
3535
3536         index = in_eeprom->offset >> 24;
3537         offset = in_eeprom->offset & 0xffffff;
3538
3539         if (index != 0)
3540                 return bnxt_hwrm_get_nvram_item(bp, index - 1, offset,
3541                                            in_eeprom->length, in_eeprom->data);
3542
3543         return 0;
3544 }
3545
3546 static bool bnxt_dir_type_is_ape_bin_format(uint16_t dir_type)
3547 {
3548         switch (dir_type) {
3549         case BNX_DIR_TYPE_CHIMP_PATCH:
3550         case BNX_DIR_TYPE_BOOTCODE:
3551         case BNX_DIR_TYPE_BOOTCODE_2:
3552         case BNX_DIR_TYPE_APE_FW:
3553         case BNX_DIR_TYPE_APE_PATCH:
3554         case BNX_DIR_TYPE_KONG_FW:
3555         case BNX_DIR_TYPE_KONG_PATCH:
3556         case BNX_DIR_TYPE_BONO_FW:
3557         case BNX_DIR_TYPE_BONO_PATCH:
3558                 /* FALLTHROUGH */
3559                 return true;
3560         }
3561
3562         return false;
3563 }
3564
3565 static bool bnxt_dir_type_is_other_exec_format(uint16_t dir_type)
3566 {
3567         switch (dir_type) {
3568         case BNX_DIR_TYPE_AVS:
3569         case BNX_DIR_TYPE_EXP_ROM_MBA:
3570         case BNX_DIR_TYPE_PCIE:
3571         case BNX_DIR_TYPE_TSCF_UCODE:
3572         case BNX_DIR_TYPE_EXT_PHY:
3573         case BNX_DIR_TYPE_CCM:
3574         case BNX_DIR_TYPE_ISCSI_BOOT:
3575         case BNX_DIR_TYPE_ISCSI_BOOT_IPV6:
3576         case BNX_DIR_TYPE_ISCSI_BOOT_IPV4N6:
3577                 /* FALLTHROUGH */
3578                 return true;
3579         }
3580
3581         return false;
3582 }
3583
3584 static bool bnxt_dir_type_is_executable(uint16_t dir_type)
3585 {
3586         return bnxt_dir_type_is_ape_bin_format(dir_type) ||
3587                 bnxt_dir_type_is_other_exec_format(dir_type);
3588 }
3589
3590 static int
3591 bnxt_set_eeprom_op(struct rte_eth_dev *dev,
3592                 struct rte_dev_eeprom_info *in_eeprom)
3593 {
3594         struct bnxt *bp = dev->data->dev_private;
3595         uint8_t index, dir_op;
3596         uint16_t type, ext, ordinal, attr;
3597         int rc;
3598
3599         rc = is_bnxt_in_error(bp);
3600         if (rc)
3601                 return rc;
3602
3603         PMD_DRV_LOG(INFO, "%04x:%02x:%02x:%02x in_eeprom->offset = %d "
3604                 "len = %d\n", bp->pdev->addr.domain,
3605                 bp->pdev->addr.bus, bp->pdev->addr.devid,
3606                 bp->pdev->addr.function, in_eeprom->offset, in_eeprom->length);
3607
3608         if (!BNXT_PF(bp)) {
3609                 PMD_DRV_LOG(ERR, "NVM write not supported from a VF\n");
3610                 return -EINVAL;
3611         }
3612
3613         type = in_eeprom->magic >> 16;
3614
3615         if (type == 0xffff) { /* special value for directory operations */
3616                 index = in_eeprom->magic & 0xff;
3617                 dir_op = in_eeprom->magic >> 8;
3618                 if (index == 0)
3619                         return -EINVAL;
3620                 switch (dir_op) {
3621                 case 0x0e: /* erase */
3622                         if (in_eeprom->offset != ~in_eeprom->magic)
3623                                 return -EINVAL;
3624                         return bnxt_hwrm_erase_nvram_directory(bp, index - 1);
3625                 default:
3626                         return -EINVAL;
3627                 }
3628         }
3629
3630         /* Create or re-write an NVM item: */
3631         if (bnxt_dir_type_is_executable(type) == true)
3632                 return -EOPNOTSUPP;
3633         ext = in_eeprom->magic & 0xffff;
3634         ordinal = in_eeprom->offset >> 16;
3635         attr = in_eeprom->offset & 0xffff;
3636
3637         return bnxt_hwrm_flash_nvram(bp, type, ordinal, ext, attr,
3638                                      in_eeprom->data, in_eeprom->length);
3639 }
3640
3641 /*
3642  * Initialization
3643  */
3644
3645 static const struct eth_dev_ops bnxt_dev_ops = {
3646         .dev_infos_get = bnxt_dev_info_get_op,
3647         .dev_close = bnxt_dev_close_op,
3648         .dev_configure = bnxt_dev_configure_op,
3649         .dev_start = bnxt_dev_start_op,
3650         .dev_stop = bnxt_dev_stop_op,
3651         .dev_set_link_up = bnxt_dev_set_link_up_op,
3652         .dev_set_link_down = bnxt_dev_set_link_down_op,
3653         .stats_get = bnxt_stats_get_op,
3654         .stats_reset = bnxt_stats_reset_op,
3655         .rx_queue_setup = bnxt_rx_queue_setup_op,
3656         .rx_queue_release = bnxt_rx_queue_release_op,
3657         .tx_queue_setup = bnxt_tx_queue_setup_op,
3658         .tx_queue_release = bnxt_tx_queue_release_op,
3659         .rx_queue_intr_enable = bnxt_rx_queue_intr_enable_op,
3660         .rx_queue_intr_disable = bnxt_rx_queue_intr_disable_op,
3661         .reta_update = bnxt_reta_update_op,
3662         .reta_query = bnxt_reta_query_op,
3663         .rss_hash_update = bnxt_rss_hash_update_op,
3664         .rss_hash_conf_get = bnxt_rss_hash_conf_get_op,
3665         .link_update = bnxt_link_update_op,
3666         .promiscuous_enable = bnxt_promiscuous_enable_op,
3667         .promiscuous_disable = bnxt_promiscuous_disable_op,
3668         .allmulticast_enable = bnxt_allmulticast_enable_op,
3669         .allmulticast_disable = bnxt_allmulticast_disable_op,
3670         .mac_addr_add = bnxt_mac_addr_add_op,
3671         .mac_addr_remove = bnxt_mac_addr_remove_op,
3672         .flow_ctrl_get = bnxt_flow_ctrl_get_op,
3673         .flow_ctrl_set = bnxt_flow_ctrl_set_op,
3674         .udp_tunnel_port_add  = bnxt_udp_tunnel_port_add_op,
3675         .udp_tunnel_port_del  = bnxt_udp_tunnel_port_del_op,
3676         .vlan_filter_set = bnxt_vlan_filter_set_op,
3677         .vlan_offload_set = bnxt_vlan_offload_set_op,
3678         .vlan_tpid_set = bnxt_vlan_tpid_set_op,
3679         .vlan_pvid_set = bnxt_vlan_pvid_set_op,
3680         .mtu_set = bnxt_mtu_set_op,
3681         .mac_addr_set = bnxt_set_default_mac_addr_op,
3682         .xstats_get = bnxt_dev_xstats_get_op,
3683         .xstats_get_names = bnxt_dev_xstats_get_names_op,
3684         .xstats_reset = bnxt_dev_xstats_reset_op,
3685         .fw_version_get = bnxt_fw_version_get,
3686         .set_mc_addr_list = bnxt_dev_set_mc_addr_list_op,
3687         .rxq_info_get = bnxt_rxq_info_get_op,
3688         .txq_info_get = bnxt_txq_info_get_op,
3689         .dev_led_on = bnxt_dev_led_on_op,
3690         .dev_led_off = bnxt_dev_led_off_op,
3691         .xstats_get_by_id = bnxt_dev_xstats_get_by_id_op,
3692         .xstats_get_names_by_id = bnxt_dev_xstats_get_names_by_id_op,
3693         .rx_queue_count = bnxt_rx_queue_count_op,
3694         .rx_descriptor_status = bnxt_rx_descriptor_status_op,
3695         .tx_descriptor_status = bnxt_tx_descriptor_status_op,
3696         .rx_queue_start = bnxt_rx_queue_start,
3697         .rx_queue_stop = bnxt_rx_queue_stop,
3698         .tx_queue_start = bnxt_tx_queue_start,
3699         .tx_queue_stop = bnxt_tx_queue_stop,
3700         .filter_ctrl = bnxt_filter_ctrl_op,
3701         .dev_supported_ptypes_get = bnxt_dev_supported_ptypes_get_op,
3702         .get_eeprom_length    = bnxt_get_eeprom_length_op,
3703         .get_eeprom           = bnxt_get_eeprom_op,
3704         .set_eeprom           = bnxt_set_eeprom_op,
3705         .timesync_enable      = bnxt_timesync_enable,
3706         .timesync_disable     = bnxt_timesync_disable,
3707         .timesync_read_time   = bnxt_timesync_read_time,
3708         .timesync_write_time   = bnxt_timesync_write_time,
3709         .timesync_adjust_time = bnxt_timesync_adjust_time,
3710         .timesync_read_rx_timestamp = bnxt_timesync_read_rx_timestamp,
3711         .timesync_read_tx_timestamp = bnxt_timesync_read_tx_timestamp,
3712 };
3713
3714 static uint32_t bnxt_map_reset_regs(struct bnxt *bp, uint32_t reg)
3715 {
3716         uint32_t offset;
3717
3718         /* Only pre-map the reset GRC registers using window 3 */
3719         rte_write32(reg & 0xfffff000, (uint8_t *)bp->bar0 +
3720                     BNXT_GRCPF_REG_WINDOW_BASE_OUT + 8);
3721
3722         offset = BNXT_GRCP_WINDOW_3_BASE + (reg & 0xffc);
3723
3724         return offset;
3725 }
3726
3727 int bnxt_map_fw_health_status_regs(struct bnxt *bp)
3728 {
3729         struct bnxt_error_recovery_info *info = bp->recovery_info;
3730         uint32_t reg_base = 0xffffffff;
3731         int i;
3732
3733         /* Only pre-map the monitoring GRC registers using window 2 */
3734         for (i = 0; i < BNXT_FW_STATUS_REG_CNT; i++) {
3735                 uint32_t reg = info->status_regs[i];
3736
3737                 if (BNXT_FW_STATUS_REG_TYPE(reg) != BNXT_FW_STATUS_REG_TYPE_GRC)
3738                         continue;
3739
3740                 if (reg_base == 0xffffffff)
3741                         reg_base = reg & 0xfffff000;
3742                 if ((reg & 0xfffff000) != reg_base)
3743                         return -ERANGE;
3744
3745                 /* Use mask 0xffc as the Lower 2 bits indicates
3746                  * address space location
3747                  */
3748                 info->mapped_status_regs[i] = BNXT_GRCP_WINDOW_2_BASE +
3749                                                 (reg & 0xffc);
3750         }
3751
3752         if (reg_base == 0xffffffff)
3753                 return 0;
3754
3755         rte_write32(reg_base, (uint8_t *)bp->bar0 +
3756                     BNXT_GRCPF_REG_WINDOW_BASE_OUT + 4);
3757
3758         return 0;
3759 }
3760
3761 static void bnxt_write_fw_reset_reg(struct bnxt *bp, uint32_t index)
3762 {
3763         struct bnxt_error_recovery_info *info = bp->recovery_info;
3764         uint32_t delay = info->delay_after_reset[index];
3765         uint32_t val = info->reset_reg_val[index];
3766         uint32_t reg = info->reset_reg[index];
3767         uint32_t type, offset;
3768
3769         type = BNXT_FW_STATUS_REG_TYPE(reg);
3770         offset = BNXT_FW_STATUS_REG_OFF(reg);
3771
3772         switch (type) {
3773         case BNXT_FW_STATUS_REG_TYPE_CFG:
3774                 rte_pci_write_config(bp->pdev, &val, sizeof(val), offset);
3775                 break;
3776         case BNXT_FW_STATUS_REG_TYPE_GRC:
3777                 offset = bnxt_map_reset_regs(bp, offset);
3778                 rte_write32(val, (uint8_t *)bp->bar0 + offset);
3779                 break;
3780         case BNXT_FW_STATUS_REG_TYPE_BAR0:
3781                 rte_write32(val, (uint8_t *)bp->bar0 + offset);
3782                 break;
3783         }
3784         /* wait on a specific interval of time until core reset is complete */
3785         if (delay)
3786                 rte_delay_ms(delay);
3787 }
3788
3789 static void bnxt_dev_cleanup(struct bnxt *bp)
3790 {
3791         bnxt_set_hwrm_link_config(bp, false);
3792         bp->link_info.link_up = 0;
3793         if (bp->dev_stopped == 0)
3794                 bnxt_dev_stop_op(bp->eth_dev);
3795
3796         bnxt_uninit_resources(bp, true);
3797 }
3798
3799 static int bnxt_restore_filters(struct bnxt *bp)
3800 {
3801         struct rte_eth_dev *dev = bp->eth_dev;
3802         int ret = 0;
3803
3804         if (dev->data->all_multicast)
3805                 ret = bnxt_allmulticast_enable_op(dev);
3806         if (dev->data->promiscuous)
3807                 ret = bnxt_promiscuous_enable_op(dev);
3808
3809         /* TODO restore other filters as well */
3810         return ret;
3811 }
3812
3813 static void bnxt_dev_recover(void *arg)
3814 {
3815         struct bnxt *bp = arg;
3816         int timeout = bp->fw_reset_max_msecs;
3817         int rc = 0;
3818
3819         /* Clear Error flag so that device re-init should happen */
3820         bp->flags &= ~BNXT_FLAG_FATAL_ERROR;
3821
3822         do {
3823                 rc = bnxt_hwrm_ver_get(bp);
3824                 if (rc == 0)
3825                         break;
3826                 rte_delay_ms(BNXT_FW_READY_WAIT_INTERVAL);
3827                 timeout -= BNXT_FW_READY_WAIT_INTERVAL;
3828         } while (rc && timeout);
3829
3830         if (rc) {
3831                 PMD_DRV_LOG(ERR, "FW is not Ready after reset\n");
3832                 goto err;
3833         }
3834
3835         rc = bnxt_init_resources(bp, true);
3836         if (rc) {
3837                 PMD_DRV_LOG(ERR,
3838                             "Failed to initialize resources after reset\n");
3839                 goto err;
3840         }
3841         /* clear reset flag as the device is initialized now */
3842         bp->flags &= ~BNXT_FLAG_FW_RESET;
3843
3844         rc = bnxt_dev_start_op(bp->eth_dev);
3845         if (rc) {
3846                 PMD_DRV_LOG(ERR, "Failed to start port after reset\n");
3847                 goto err;
3848         }
3849
3850         rc = bnxt_restore_filters(bp);
3851         if (rc)
3852                 goto err;
3853
3854         PMD_DRV_LOG(INFO, "Recovered from FW reset\n");
3855         return;
3856 err:
3857         bp->flags |= BNXT_FLAG_FATAL_ERROR;
3858         bnxt_uninit_resources(bp, false);
3859         PMD_DRV_LOG(ERR, "Failed to recover from FW reset\n");
3860 }
3861
3862 void bnxt_dev_reset_and_resume(void *arg)
3863 {
3864         struct bnxt *bp = arg;
3865         int rc;
3866
3867         bnxt_dev_cleanup(bp);
3868
3869         bnxt_wait_for_device_shutdown(bp);
3870
3871         rc = rte_eal_alarm_set(US_PER_MS * bp->fw_reset_min_msecs,
3872                                bnxt_dev_recover, (void *)bp);
3873         if (rc)
3874                 PMD_DRV_LOG(ERR, "Error setting recovery alarm");
3875 }
3876
3877 uint32_t bnxt_read_fw_status_reg(struct bnxt *bp, uint32_t index)
3878 {
3879         struct bnxt_error_recovery_info *info = bp->recovery_info;
3880         uint32_t reg = info->status_regs[index];
3881         uint32_t type, offset, val = 0;
3882
3883         type = BNXT_FW_STATUS_REG_TYPE(reg);
3884         offset = BNXT_FW_STATUS_REG_OFF(reg);
3885
3886         switch (type) {
3887         case BNXT_FW_STATUS_REG_TYPE_CFG:
3888                 rte_pci_read_config(bp->pdev, &val, sizeof(val), offset);
3889                 break;
3890         case BNXT_FW_STATUS_REG_TYPE_GRC:
3891                 offset = info->mapped_status_regs[index];
3892                 /* FALLTHROUGH */
3893         case BNXT_FW_STATUS_REG_TYPE_BAR0:
3894                 val = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3895                                        offset));
3896                 break;
3897         }
3898
3899         return val;
3900 }
3901
3902 static int bnxt_fw_reset_all(struct bnxt *bp)
3903 {
3904         struct bnxt_error_recovery_info *info = bp->recovery_info;
3905         uint32_t i;
3906         int rc = 0;
3907
3908         if (info->flags & BNXT_FLAG_ERROR_RECOVERY_HOST) {
3909                 /* Reset through master function driver */
3910                 for (i = 0; i < info->reg_array_cnt; i++)
3911                         bnxt_write_fw_reset_reg(bp, i);
3912                 /* Wait for time specified by FW after triggering reset */
3913                 rte_delay_ms(info->master_func_wait_period_after_reset);
3914         } else if (info->flags & BNXT_FLAG_ERROR_RECOVERY_CO_CPU) {
3915                 /* Reset with the help of Kong processor */
3916                 rc = bnxt_hwrm_fw_reset(bp);
3917                 if (rc)
3918                         PMD_DRV_LOG(ERR, "Failed to reset FW\n");
3919         }
3920
3921         return rc;
3922 }
3923
3924 static void bnxt_fw_reset_cb(void *arg)
3925 {
3926         struct bnxt *bp = arg;
3927         struct bnxt_error_recovery_info *info = bp->recovery_info;
3928         int rc = 0;
3929
3930         /* Only Master function can do FW reset */
3931         if (bnxt_is_master_func(bp) &&
3932             bnxt_is_recovery_enabled(bp)) {
3933                 rc = bnxt_fw_reset_all(bp);
3934                 if (rc) {
3935                         PMD_DRV_LOG(ERR, "Adapter recovery failed\n");
3936                         return;
3937                 }
3938         }
3939
3940         /* if recovery method is ERROR_RECOVERY_CO_CPU, KONG will send
3941          * EXCEPTION_FATAL_ASYNC event to all the functions
3942          * (including MASTER FUNC). After receiving this Async, all the active
3943          * drivers should treat this case as FW initiated recovery
3944          */
3945         if (info->flags & BNXT_FLAG_ERROR_RECOVERY_HOST) {
3946                 bp->fw_reset_min_msecs = BNXT_MIN_FW_READY_TIMEOUT;
3947                 bp->fw_reset_max_msecs = BNXT_MAX_FW_RESET_TIMEOUT;
3948
3949                 /* To recover from error */
3950                 rte_eal_alarm_set(US_PER_MS, bnxt_dev_reset_and_resume,
3951                                   (void *)bp);
3952         }
3953 }
3954
3955 /* Driver should poll FW heartbeat, reset_counter with the frequency
3956  * advertised by FW in HWRM_ERROR_RECOVERY_QCFG.
3957  * When the driver detects heartbeat stop or change in reset_counter,
3958  * it has to trigger a reset to recover from the error condition.
3959  * A “master PF” is the function who will have the privilege to
3960  * initiate the chimp reset. The master PF will be elected by the
3961  * firmware and will be notified through async message.
3962  */
3963 static void bnxt_check_fw_health(void *arg)
3964 {
3965         struct bnxt *bp = arg;
3966         struct bnxt_error_recovery_info *info = bp->recovery_info;
3967         uint32_t val = 0, wait_msec;
3968
3969         if (!info || !bnxt_is_recovery_enabled(bp) ||
3970             is_bnxt_in_error(bp))
3971                 return;
3972
3973         val = bnxt_read_fw_status_reg(bp, BNXT_FW_HEARTBEAT_CNT_REG);
3974         if (val == info->last_heart_beat)
3975                 goto reset;
3976
3977         info->last_heart_beat = val;
3978
3979         val = bnxt_read_fw_status_reg(bp, BNXT_FW_RECOVERY_CNT_REG);
3980         if (val != info->last_reset_counter)
3981                 goto reset;
3982
3983         info->last_reset_counter = val;
3984
3985         rte_eal_alarm_set(US_PER_MS * info->driver_polling_freq,
3986                           bnxt_check_fw_health, (void *)bp);
3987
3988         return;
3989 reset:
3990         /* Stop DMA to/from device */
3991         bp->flags |= BNXT_FLAG_FATAL_ERROR;
3992         bp->flags |= BNXT_FLAG_FW_RESET;
3993
3994         PMD_DRV_LOG(ERR, "Detected FW dead condition\n");
3995
3996         if (bnxt_is_master_func(bp))
3997                 wait_msec = info->master_func_wait_period;
3998         else
3999                 wait_msec = info->normal_func_wait_period;
4000
4001         rte_eal_alarm_set(US_PER_MS * wait_msec,
4002                           bnxt_fw_reset_cb, (void *)bp);
4003 }
4004
4005 void bnxt_schedule_fw_health_check(struct bnxt *bp)
4006 {
4007         uint32_t polling_freq;
4008
4009         if (!bnxt_is_recovery_enabled(bp))
4010                 return;
4011
4012         if (bp->flags & BNXT_FLAG_FW_HEALTH_CHECK_SCHEDULED)
4013                 return;
4014
4015         polling_freq = bp->recovery_info->driver_polling_freq;
4016
4017         rte_eal_alarm_set(US_PER_MS * polling_freq,
4018                           bnxt_check_fw_health, (void *)bp);
4019         bp->flags |= BNXT_FLAG_FW_HEALTH_CHECK_SCHEDULED;
4020 }
4021
4022 static void bnxt_cancel_fw_health_check(struct bnxt *bp)
4023 {
4024         if (!bnxt_is_recovery_enabled(bp))
4025                 return;
4026
4027         rte_eal_alarm_cancel(bnxt_check_fw_health, (void *)bp);
4028         bp->flags &= ~BNXT_FLAG_FW_HEALTH_CHECK_SCHEDULED;
4029 }
4030
4031 static bool bnxt_vf_pciid(uint16_t id)
4032 {
4033         if (id == BROADCOM_DEV_ID_57304_VF ||
4034             id == BROADCOM_DEV_ID_57406_VF ||
4035             id == BROADCOM_DEV_ID_5731X_VF ||
4036             id == BROADCOM_DEV_ID_5741X_VF ||
4037             id == BROADCOM_DEV_ID_57414_VF ||
4038             id == BROADCOM_DEV_ID_STRATUS_NIC_VF1 ||
4039             id == BROADCOM_DEV_ID_STRATUS_NIC_VF2 ||
4040             id == BROADCOM_DEV_ID_58802_VF ||
4041             id == BROADCOM_DEV_ID_57500_VF1 ||
4042             id == BROADCOM_DEV_ID_57500_VF2)
4043                 return true;
4044         return false;
4045 }
4046
4047 bool bnxt_stratus_device(struct bnxt *bp)
4048 {
4049         uint16_t id = bp->pdev->id.device_id;
4050
4051         if (id == BROADCOM_DEV_ID_STRATUS_NIC ||
4052             id == BROADCOM_DEV_ID_STRATUS_NIC_VF1 ||
4053             id == BROADCOM_DEV_ID_STRATUS_NIC_VF2)
4054                 return true;
4055         return false;
4056 }
4057
4058 static int bnxt_init_board(struct rte_eth_dev *eth_dev)
4059 {
4060         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
4061         struct bnxt *bp = eth_dev->data->dev_private;
4062
4063         /* enable device (incl. PCI PM wakeup), and bus-mastering */
4064         bp->bar0 = (void *)pci_dev->mem_resource[0].addr;
4065         bp->doorbell_base = (void *)pci_dev->mem_resource[2].addr;
4066         if (!bp->bar0 || !bp->doorbell_base) {
4067                 PMD_DRV_LOG(ERR, "Unable to access Hardware\n");
4068                 return -ENODEV;
4069         }
4070
4071         bp->eth_dev = eth_dev;
4072         bp->pdev = pci_dev;
4073
4074         return 0;
4075 }
4076
4077 static int bnxt_alloc_ctx_mem_blk(__rte_unused struct bnxt *bp,
4078                                   struct bnxt_ctx_pg_info *ctx_pg,
4079                                   uint32_t mem_size,
4080                                   const char *suffix,
4081                                   uint16_t idx)
4082 {
4083         struct bnxt_ring_mem_info *rmem = &ctx_pg->ring_mem;
4084         const struct rte_memzone *mz = NULL;
4085         char mz_name[RTE_MEMZONE_NAMESIZE];
4086         rte_iova_t mz_phys_addr;
4087         uint64_t valid_bits = 0;
4088         uint32_t sz;
4089         int i;
4090
4091         if (!mem_size)
4092                 return 0;
4093
4094         rmem->nr_pages = RTE_ALIGN_MUL_CEIL(mem_size, BNXT_PAGE_SIZE) /
4095                          BNXT_PAGE_SIZE;
4096         rmem->page_size = BNXT_PAGE_SIZE;
4097         rmem->pg_arr = ctx_pg->ctx_pg_arr;
4098         rmem->dma_arr = ctx_pg->ctx_dma_arr;
4099         rmem->flags = BNXT_RMEM_VALID_PTE_FLAG;
4100
4101         valid_bits = PTU_PTE_VALID;
4102
4103         if (rmem->nr_pages > 1) {
4104                 snprintf(mz_name, RTE_MEMZONE_NAMESIZE,
4105                          "bnxt_ctx_pg_tbl%s_%x_%d",
4106                          suffix, idx, bp->eth_dev->data->port_id);
4107                 mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0;
4108                 mz = rte_memzone_lookup(mz_name);
4109                 if (!mz) {
4110                         mz = rte_memzone_reserve_aligned(mz_name,
4111                                                 rmem->nr_pages * 8,
4112                                                 SOCKET_ID_ANY,
4113                                                 RTE_MEMZONE_2MB |
4114                                                 RTE_MEMZONE_SIZE_HINT_ONLY |
4115                                                 RTE_MEMZONE_IOVA_CONTIG,
4116                                                 BNXT_PAGE_SIZE);
4117                         if (mz == NULL)
4118                                 return -ENOMEM;
4119                 }
4120
4121                 memset(mz->addr, 0, mz->len);
4122                 mz_phys_addr = mz->iova;
4123                 if ((unsigned long)mz->addr == mz_phys_addr) {
4124                         PMD_DRV_LOG(DEBUG,
4125                                     "physical address same as virtual\n");
4126                         PMD_DRV_LOG(DEBUG, "Using rte_mem_virt2iova()\n");
4127                         mz_phys_addr = rte_mem_virt2iova(mz->addr);
4128                         if (mz_phys_addr == RTE_BAD_IOVA) {
4129                                 PMD_DRV_LOG(ERR,
4130                                         "unable to map addr to phys memory\n");
4131                                 return -ENOMEM;
4132                         }
4133                 }
4134                 rte_mem_lock_page(((char *)mz->addr));
4135
4136                 rmem->pg_tbl = mz->addr;
4137                 rmem->pg_tbl_map = mz_phys_addr;
4138                 rmem->pg_tbl_mz = mz;
4139         }
4140
4141         snprintf(mz_name, RTE_MEMZONE_NAMESIZE, "bnxt_ctx_%s_%x_%d",
4142                  suffix, idx, bp->eth_dev->data->port_id);
4143         mz = rte_memzone_lookup(mz_name);
4144         if (!mz) {
4145                 mz = rte_memzone_reserve_aligned(mz_name,
4146                                                  mem_size,
4147                                                  SOCKET_ID_ANY,
4148                                                  RTE_MEMZONE_1GB |
4149                                                  RTE_MEMZONE_SIZE_HINT_ONLY |
4150                                                  RTE_MEMZONE_IOVA_CONTIG,
4151                                                  BNXT_PAGE_SIZE);
4152                 if (mz == NULL)
4153                         return -ENOMEM;
4154         }
4155
4156         memset(mz->addr, 0, mz->len);
4157         mz_phys_addr = mz->iova;
4158         if ((unsigned long)mz->addr == mz_phys_addr) {
4159                 PMD_DRV_LOG(DEBUG,
4160                             "Memzone physical address same as virtual.\n");
4161                 PMD_DRV_LOG(DEBUG, "Using rte_mem_virt2iova()\n");
4162                 for (sz = 0; sz < mem_size; sz += BNXT_PAGE_SIZE)
4163                         rte_mem_lock_page(((char *)mz->addr) + sz);
4164                 mz_phys_addr = rte_mem_virt2iova(mz->addr);
4165                 if (mz_phys_addr == RTE_BAD_IOVA) {
4166                         PMD_DRV_LOG(ERR,
4167                                     "unable to map addr to phys memory\n");
4168                         return -ENOMEM;
4169                 }
4170         }
4171
4172         for (sz = 0, i = 0; sz < mem_size; sz += BNXT_PAGE_SIZE, i++) {
4173                 rte_mem_lock_page(((char *)mz->addr) + sz);
4174                 rmem->pg_arr[i] = ((char *)mz->addr) + sz;
4175                 rmem->dma_arr[i] = mz_phys_addr + sz;
4176
4177                 if (rmem->nr_pages > 1) {
4178                         if (i == rmem->nr_pages - 2 &&
4179                             (rmem->flags & BNXT_RMEM_RING_PTE_FLAG))
4180                                 valid_bits |= PTU_PTE_NEXT_TO_LAST;
4181                         else if (i == rmem->nr_pages - 1 &&
4182                                  (rmem->flags & BNXT_RMEM_RING_PTE_FLAG))
4183                                 valid_bits |= PTU_PTE_LAST;
4184
4185                         rmem->pg_tbl[i] = rte_cpu_to_le_64(rmem->dma_arr[i] |
4186                                                            valid_bits);
4187                 }
4188         }
4189
4190         rmem->mz = mz;
4191         if (rmem->vmem_size)
4192                 rmem->vmem = (void **)mz->addr;
4193         rmem->dma_arr[0] = mz_phys_addr;
4194         return 0;
4195 }
4196
4197 static void bnxt_free_ctx_mem(struct bnxt *bp)
4198 {
4199         int i;
4200
4201         if (!bp->ctx || !(bp->ctx->flags & BNXT_CTX_FLAG_INITED))
4202                 return;
4203
4204         bp->ctx->flags &= ~BNXT_CTX_FLAG_INITED;
4205         rte_memzone_free(bp->ctx->qp_mem.ring_mem.mz);
4206         rte_memzone_free(bp->ctx->srq_mem.ring_mem.mz);
4207         rte_memzone_free(bp->ctx->cq_mem.ring_mem.mz);
4208         rte_memzone_free(bp->ctx->vnic_mem.ring_mem.mz);
4209         rte_memzone_free(bp->ctx->stat_mem.ring_mem.mz);
4210         rte_memzone_free(bp->ctx->qp_mem.ring_mem.pg_tbl_mz);
4211         rte_memzone_free(bp->ctx->srq_mem.ring_mem.pg_tbl_mz);
4212         rte_memzone_free(bp->ctx->cq_mem.ring_mem.pg_tbl_mz);
4213         rte_memzone_free(bp->ctx->vnic_mem.ring_mem.pg_tbl_mz);
4214         rte_memzone_free(bp->ctx->stat_mem.ring_mem.pg_tbl_mz);
4215
4216         for (i = 0; i < BNXT_MAX_Q; i++) {
4217                 if (bp->ctx->tqm_mem[i])
4218                         rte_memzone_free(bp->ctx->tqm_mem[i]->ring_mem.mz);
4219         }
4220
4221         rte_free(bp->ctx);
4222         bp->ctx = NULL;
4223 }
4224
4225 #define bnxt_roundup(x, y)   ((((x) + ((y) - 1)) / (y)) * (y))
4226
4227 #define min_t(type, x, y) ({                    \
4228         type __min1 = (x);                      \
4229         type __min2 = (y);                      \
4230         __min1 < __min2 ? __min1 : __min2; })
4231
4232 #define max_t(type, x, y) ({                    \
4233         type __max1 = (x);                      \
4234         type __max2 = (y);                      \
4235         __max1 > __max2 ? __max1 : __max2; })
4236
4237 #define clamp_t(type, _x, min, max)     min_t(type, max_t(type, _x, min), max)
4238
4239 int bnxt_alloc_ctx_mem(struct bnxt *bp)
4240 {
4241         struct bnxt_ctx_pg_info *ctx_pg;
4242         struct bnxt_ctx_mem_info *ctx;
4243         uint32_t mem_size, ena, entries;
4244         int i, rc;
4245
4246         rc = bnxt_hwrm_func_backing_store_qcaps(bp);
4247         if (rc) {
4248                 PMD_DRV_LOG(ERR, "Query context mem capability failed\n");
4249                 return rc;
4250         }
4251         ctx = bp->ctx;
4252         if (!ctx || (ctx->flags & BNXT_CTX_FLAG_INITED))
4253                 return 0;
4254
4255         ctx_pg = &ctx->qp_mem;
4256         ctx_pg->entries = ctx->qp_min_qp1_entries + ctx->qp_max_l2_entries;
4257         mem_size = ctx->qp_entry_size * ctx_pg->entries;
4258         rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "qp_mem", 0);
4259         if (rc)
4260                 return rc;
4261
4262         ctx_pg = &ctx->srq_mem;
4263         ctx_pg->entries = ctx->srq_max_l2_entries;
4264         mem_size = ctx->srq_entry_size * ctx_pg->entries;
4265         rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "srq_mem", 0);
4266         if (rc)
4267                 return rc;
4268
4269         ctx_pg = &ctx->cq_mem;
4270         ctx_pg->entries = ctx->cq_max_l2_entries;
4271         mem_size = ctx->cq_entry_size * ctx_pg->entries;
4272         rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "cq_mem", 0);
4273         if (rc)
4274                 return rc;
4275
4276         ctx_pg = &ctx->vnic_mem;
4277         ctx_pg->entries = ctx->vnic_max_vnic_entries +
4278                 ctx->vnic_max_ring_table_entries;
4279         mem_size = ctx->vnic_entry_size * ctx_pg->entries;
4280         rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "vnic_mem", 0);
4281         if (rc)
4282                 return rc;
4283
4284         ctx_pg = &ctx->stat_mem;
4285         ctx_pg->entries = ctx->stat_max_entries;
4286         mem_size = ctx->stat_entry_size * ctx_pg->entries;
4287         rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "stat_mem", 0);
4288         if (rc)
4289                 return rc;
4290
4291         entries = ctx->qp_max_l2_entries;
4292         entries = bnxt_roundup(entries, ctx->tqm_entries_multiple);
4293         entries = clamp_t(uint32_t, entries, ctx->tqm_min_entries_per_ring,
4294                           ctx->tqm_max_entries_per_ring);
4295         for (i = 0, ena = 0; i < BNXT_MAX_Q; i++) {
4296                 ctx_pg = ctx->tqm_mem[i];
4297                 /* use min tqm entries for now. */
4298                 ctx_pg->entries = entries;
4299                 mem_size = ctx->tqm_entry_size * ctx_pg->entries;
4300                 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "tqm_mem", i);
4301                 if (rc)
4302                         return rc;
4303                 ena |= HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_SP << i;
4304         }
4305
4306         ena |= FUNC_BACKING_STORE_CFG_INPUT_DFLT_ENABLES;
4307         rc = bnxt_hwrm_func_backing_store_cfg(bp, ena);
4308         if (rc)
4309                 PMD_DRV_LOG(ERR,
4310                             "Failed to configure context mem: rc = %d\n", rc);
4311         else
4312                 ctx->flags |= BNXT_CTX_FLAG_INITED;
4313
4314         return rc;
4315 }
4316
4317 static int bnxt_alloc_stats_mem(struct bnxt *bp)
4318 {
4319         struct rte_pci_device *pci_dev = bp->pdev;
4320         char mz_name[RTE_MEMZONE_NAMESIZE];
4321         const struct rte_memzone *mz = NULL;
4322         uint32_t total_alloc_len;
4323         rte_iova_t mz_phys_addr;
4324
4325         if (pci_dev->id.device_id == BROADCOM_DEV_ID_NS2)
4326                 return 0;
4327
4328         snprintf(mz_name, RTE_MEMZONE_NAMESIZE,
4329                  "bnxt_" PCI_PRI_FMT "-%s", pci_dev->addr.domain,
4330                  pci_dev->addr.bus, pci_dev->addr.devid,
4331                  pci_dev->addr.function, "rx_port_stats");
4332         mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0;
4333         mz = rte_memzone_lookup(mz_name);
4334         total_alloc_len =
4335                 RTE_CACHE_LINE_ROUNDUP(sizeof(struct rx_port_stats) +
4336                                        sizeof(struct rx_port_stats_ext) + 512);
4337         if (!mz) {
4338                 mz = rte_memzone_reserve(mz_name, total_alloc_len,
4339                                          SOCKET_ID_ANY,
4340                                          RTE_MEMZONE_2MB |
4341                                          RTE_MEMZONE_SIZE_HINT_ONLY |
4342                                          RTE_MEMZONE_IOVA_CONTIG);
4343                 if (mz == NULL)
4344                         return -ENOMEM;
4345         }
4346         memset(mz->addr, 0, mz->len);
4347         mz_phys_addr = mz->iova;
4348         if ((unsigned long)mz->addr == mz_phys_addr) {
4349                 PMD_DRV_LOG(DEBUG,
4350                             "Memzone physical address same as virtual.\n");
4351                 PMD_DRV_LOG(DEBUG,
4352                             "Using rte_mem_virt2iova()\n");
4353                 mz_phys_addr = rte_mem_virt2iova(mz->addr);
4354                 if (mz_phys_addr == RTE_BAD_IOVA) {
4355                         PMD_DRV_LOG(ERR,
4356                                     "Can't map address to physical memory\n");
4357                         return -ENOMEM;
4358                 }
4359         }
4360
4361         bp->rx_mem_zone = (const void *)mz;
4362         bp->hw_rx_port_stats = mz->addr;
4363         bp->hw_rx_port_stats_map = mz_phys_addr;
4364
4365         snprintf(mz_name, RTE_MEMZONE_NAMESIZE,
4366                  "bnxt_" PCI_PRI_FMT "-%s", pci_dev->addr.domain,
4367                  pci_dev->addr.bus, pci_dev->addr.devid,
4368                  pci_dev->addr.function, "tx_port_stats");
4369         mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0;
4370         mz = rte_memzone_lookup(mz_name);
4371         total_alloc_len =
4372                 RTE_CACHE_LINE_ROUNDUP(sizeof(struct tx_port_stats) +
4373                                        sizeof(struct tx_port_stats_ext) + 512);
4374         if (!mz) {
4375                 mz = rte_memzone_reserve(mz_name,
4376                                          total_alloc_len,
4377                                          SOCKET_ID_ANY,
4378                                          RTE_MEMZONE_2MB |
4379                                          RTE_MEMZONE_SIZE_HINT_ONLY |
4380                                          RTE_MEMZONE_IOVA_CONTIG);
4381                 if (mz == NULL)
4382                         return -ENOMEM;
4383         }
4384         memset(mz->addr, 0, mz->len);
4385         mz_phys_addr = mz->iova;
4386         if ((unsigned long)mz->addr == mz_phys_addr) {
4387                 PMD_DRV_LOG(DEBUG,
4388                             "Memzone physical address same as virtual\n");
4389                 PMD_DRV_LOG(DEBUG, "Using rte_mem_virt2iova()\n");
4390                 mz_phys_addr = rte_mem_virt2iova(mz->addr);
4391                 if (mz_phys_addr == RTE_BAD_IOVA) {
4392                         PMD_DRV_LOG(ERR,
4393                                     "Can't map address to physical memory\n");
4394                         return -ENOMEM;
4395                 }
4396         }
4397
4398         bp->tx_mem_zone = (const void *)mz;
4399         bp->hw_tx_port_stats = mz->addr;
4400         bp->hw_tx_port_stats_map = mz_phys_addr;
4401         bp->flags |= BNXT_FLAG_PORT_STATS;
4402
4403         /* Display extended statistics if FW supports it */
4404         if (bp->hwrm_spec_code < HWRM_SPEC_CODE_1_8_4 ||
4405             bp->hwrm_spec_code == HWRM_SPEC_CODE_1_9_0 ||
4406             !(bp->flags & BNXT_FLAG_EXT_STATS_SUPPORTED))
4407                 return 0;
4408
4409         bp->hw_rx_port_stats_ext = (void *)
4410                 ((uint8_t *)bp->hw_rx_port_stats +
4411                  sizeof(struct rx_port_stats));
4412         bp->hw_rx_port_stats_ext_map = bp->hw_rx_port_stats_map +
4413                 sizeof(struct rx_port_stats);
4414         bp->flags |= BNXT_FLAG_EXT_RX_PORT_STATS;
4415
4416         if (bp->hwrm_spec_code < HWRM_SPEC_CODE_1_9_2 ||
4417             bp->flags & BNXT_FLAG_EXT_STATS_SUPPORTED) {
4418                 bp->hw_tx_port_stats_ext = (void *)
4419                         ((uint8_t *)bp->hw_tx_port_stats +
4420                          sizeof(struct tx_port_stats));
4421                 bp->hw_tx_port_stats_ext_map =
4422                         bp->hw_tx_port_stats_map +
4423                         sizeof(struct tx_port_stats);
4424                 bp->flags |= BNXT_FLAG_EXT_TX_PORT_STATS;
4425         }
4426
4427         return 0;
4428 }
4429
4430 static int bnxt_setup_mac_addr(struct rte_eth_dev *eth_dev)
4431 {
4432         struct bnxt *bp = eth_dev->data->dev_private;
4433         int rc = 0;
4434
4435         eth_dev->data->mac_addrs = rte_zmalloc("bnxt_mac_addr_tbl",
4436                                                RTE_ETHER_ADDR_LEN *
4437                                                bp->max_l2_ctx,
4438                                                0);
4439         if (eth_dev->data->mac_addrs == NULL) {
4440                 PMD_DRV_LOG(ERR, "Failed to alloc MAC addr tbl\n");
4441                 return -ENOMEM;
4442         }
4443
4444         if (bnxt_check_zero_bytes(bp->dflt_mac_addr, RTE_ETHER_ADDR_LEN)) {
4445                 if (BNXT_PF(bp))
4446                         return -EINVAL;
4447
4448                 /* Generate a random MAC address, if none was assigned by PF */
4449                 PMD_DRV_LOG(INFO, "VF MAC address not assigned by Host PF\n");
4450                 bnxt_eth_hw_addr_random(bp->mac_addr);
4451                 PMD_DRV_LOG(INFO,
4452                             "Assign random MAC:%02X:%02X:%02X:%02X:%02X:%02X\n",
4453                             bp->mac_addr[0], bp->mac_addr[1], bp->mac_addr[2],
4454                             bp->mac_addr[3], bp->mac_addr[4], bp->mac_addr[5]);
4455
4456                 rc = bnxt_hwrm_set_mac(bp);
4457                 if (!rc)
4458                         memcpy(&bp->eth_dev->data->mac_addrs[0], bp->mac_addr,
4459                                RTE_ETHER_ADDR_LEN);
4460                 return rc;
4461         }
4462
4463         /* Copy the permanent MAC from the FUNC_QCAPS response */
4464         memcpy(bp->mac_addr, bp->dflt_mac_addr, RTE_ETHER_ADDR_LEN);
4465         memcpy(&eth_dev->data->mac_addrs[0], bp->mac_addr, RTE_ETHER_ADDR_LEN);
4466
4467         return rc;
4468 }
4469
4470 static int bnxt_restore_dflt_mac(struct bnxt *bp)
4471 {
4472         int rc = 0;
4473
4474         /* MAC is already configured in FW */
4475         if (!bnxt_check_zero_bytes(bp->dflt_mac_addr, RTE_ETHER_ADDR_LEN))
4476                 return 0;
4477
4478         /* Restore the old MAC configured */
4479         rc = bnxt_hwrm_set_mac(bp);
4480         if (rc)
4481                 PMD_DRV_LOG(ERR, "Failed to restore MAC address\n");
4482
4483         return rc;
4484 }
4485
4486 static void bnxt_config_vf_req_fwd(struct bnxt *bp)
4487 {
4488         if (!BNXT_PF(bp))
4489                 return;
4490
4491 #define ALLOW_FUNC(x)   \
4492         { \
4493                 uint32_t arg = (x); \
4494                 bp->pf.vf_req_fwd[((arg) >> 5)] &= \
4495                 ~rte_cpu_to_le_32(1 << ((arg) & 0x1f)); \
4496         }
4497
4498         /* Forward all requests if firmware is new enough */
4499         if (((bp->fw_ver >= ((20 << 24) | (6 << 16) | (100 << 8))) &&
4500              (bp->fw_ver < ((20 << 24) | (7 << 16)))) ||
4501             ((bp->fw_ver >= ((20 << 24) | (8 << 16))))) {
4502                 memset(bp->pf.vf_req_fwd, 0xff, sizeof(bp->pf.vf_req_fwd));
4503         } else {
4504                 PMD_DRV_LOG(WARNING,
4505                             "Firmware too old for VF mailbox functionality\n");
4506                 memset(bp->pf.vf_req_fwd, 0, sizeof(bp->pf.vf_req_fwd));
4507         }
4508
4509         /*
4510          * The following are used for driver cleanup. If we disallow these,
4511          * VF drivers can't clean up cleanly.
4512          */
4513         ALLOW_FUNC(HWRM_FUNC_DRV_UNRGTR);
4514         ALLOW_FUNC(HWRM_VNIC_FREE);
4515         ALLOW_FUNC(HWRM_RING_FREE);
4516         ALLOW_FUNC(HWRM_RING_GRP_FREE);
4517         ALLOW_FUNC(HWRM_VNIC_RSS_COS_LB_CTX_FREE);
4518         ALLOW_FUNC(HWRM_CFA_L2_FILTER_FREE);
4519         ALLOW_FUNC(HWRM_STAT_CTX_FREE);
4520         ALLOW_FUNC(HWRM_PORT_PHY_QCFG);
4521         ALLOW_FUNC(HWRM_VNIC_TPA_CFG);
4522 }
4523
4524 static int bnxt_init_fw(struct bnxt *bp)
4525 {
4526         uint16_t mtu;
4527         int rc = 0;
4528
4529         rc = bnxt_hwrm_ver_get(bp);
4530         if (rc)
4531                 return rc;
4532
4533         rc = bnxt_hwrm_func_reset(bp);
4534         if (rc)
4535                 return -EIO;
4536
4537         rc = bnxt_hwrm_cfa_adv_flow_mgmt_qcaps(bp);
4538         if (rc)
4539                 return rc;
4540
4541         rc = bnxt_hwrm_queue_qportcfg(bp);
4542         if (rc)
4543                 return rc;
4544
4545         /* Get the MAX capabilities for this function */
4546         rc = bnxt_hwrm_func_qcaps(bp);
4547         if (rc)
4548                 return rc;
4549
4550         rc = bnxt_hwrm_func_qcfg(bp, &mtu);
4551         if (rc)
4552                 return rc;
4553
4554         /* Get the adapter error recovery support info */
4555         rc = bnxt_hwrm_error_recovery_qcfg(bp);
4556         if (rc)
4557                 bp->flags &= ~BNXT_FLAG_FW_CAP_ERROR_RECOVERY;
4558
4559         if (mtu >= RTE_ETHER_MIN_MTU && mtu <= BNXT_MAX_MTU &&
4560             mtu != bp->eth_dev->data->mtu)
4561                 bp->eth_dev->data->mtu = mtu;
4562
4563         bnxt_hwrm_port_led_qcaps(bp);
4564
4565         return 0;
4566 }
4567
4568 static int
4569 bnxt_init_locks(struct bnxt *bp)
4570 {
4571         int err;
4572
4573         err = pthread_mutex_init(&bp->flow_lock, NULL);
4574         if (err)
4575                 PMD_DRV_LOG(ERR, "Unable to initialize flow_lock\n");
4576         return err;
4577 }
4578
4579 static int bnxt_init_resources(struct bnxt *bp, bool reconfig_dev)
4580 {
4581         int rc;
4582
4583         rc = bnxt_init_fw(bp);
4584         if (rc)
4585                 return rc;
4586
4587         if (!reconfig_dev) {
4588                 rc = bnxt_setup_mac_addr(bp->eth_dev);
4589                 if (rc)
4590                         return rc;
4591         } else {
4592                 rc = bnxt_restore_dflt_mac(bp);
4593                 if (rc)
4594                         return rc;
4595         }
4596
4597         bnxt_config_vf_req_fwd(bp);
4598
4599         rc = bnxt_hwrm_func_driver_register(bp);
4600         if (rc) {
4601                 PMD_DRV_LOG(ERR, "Failed to register driver");
4602                 return -EBUSY;
4603         }
4604
4605         if (BNXT_PF(bp)) {
4606                 if (bp->pdev->max_vfs) {
4607                         rc = bnxt_hwrm_allocate_vfs(bp, bp->pdev->max_vfs);
4608                         if (rc) {
4609                                 PMD_DRV_LOG(ERR, "Failed to allocate VFs\n");
4610                                 return rc;
4611                         }
4612                 } else {
4613                         rc = bnxt_hwrm_allocate_pf_only(bp);
4614                         if (rc) {
4615                                 PMD_DRV_LOG(ERR,
4616                                             "Failed to allocate PF resources");
4617                                 return rc;
4618                         }
4619                 }
4620         }
4621
4622         rc = bnxt_alloc_mem(bp, reconfig_dev);
4623         if (rc)
4624                 return rc;
4625
4626         rc = bnxt_setup_int(bp);
4627         if (rc)
4628                 return rc;
4629
4630         bnxt_init_nic(bp);
4631
4632         rc = bnxt_request_int(bp);
4633         if (rc)
4634                 return rc;
4635
4636         rc = bnxt_init_locks(bp);
4637         if (rc)
4638                 return rc;
4639
4640         return 0;
4641 }
4642
4643 static int
4644 bnxt_dev_init(struct rte_eth_dev *eth_dev)
4645 {
4646         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
4647         static int version_printed;
4648         struct bnxt *bp;
4649         int rc;
4650
4651         if (version_printed++ == 0)
4652                 PMD_DRV_LOG(INFO, "%s\n", bnxt_version);
4653
4654         eth_dev->dev_ops = &bnxt_dev_ops;
4655         eth_dev->rx_pkt_burst = &bnxt_recv_pkts;
4656         eth_dev->tx_pkt_burst = &bnxt_xmit_pkts;
4657
4658         /*
4659          * For secondary processes, we don't initialise any further
4660          * as primary has already done this work.
4661          */
4662         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
4663                 return 0;
4664
4665         rte_eth_copy_pci_info(eth_dev, pci_dev);
4666
4667         bp = eth_dev->data->dev_private;
4668
4669         bp->dev_stopped = 1;
4670
4671         if (bnxt_vf_pciid(pci_dev->id.device_id))
4672                 bp->flags |= BNXT_FLAG_VF;
4673
4674         if (pci_dev->id.device_id == BROADCOM_DEV_ID_57508 ||
4675             pci_dev->id.device_id == BROADCOM_DEV_ID_57504 ||
4676             pci_dev->id.device_id == BROADCOM_DEV_ID_57502 ||
4677             pci_dev->id.device_id == BROADCOM_DEV_ID_57500_VF1 ||
4678             pci_dev->id.device_id == BROADCOM_DEV_ID_57500_VF2)
4679                 bp->flags |= BNXT_FLAG_THOR_CHIP;
4680
4681         if (pci_dev->id.device_id == BROADCOM_DEV_ID_58802 ||
4682             pci_dev->id.device_id == BROADCOM_DEV_ID_58804 ||
4683             pci_dev->id.device_id == BROADCOM_DEV_ID_58808 ||
4684             pci_dev->id.device_id == BROADCOM_DEV_ID_58802_VF)
4685                 bp->flags |= BNXT_FLAG_STINGRAY;
4686
4687         rc = bnxt_init_board(eth_dev);
4688         if (rc) {
4689                 PMD_DRV_LOG(ERR,
4690                             "Failed to initialize board rc: %x\n", rc);
4691                 return rc;
4692         }
4693
4694         rc = bnxt_alloc_hwrm_resources(bp);
4695         if (rc) {
4696                 PMD_DRV_LOG(ERR,
4697                             "Failed to allocate hwrm resource rc: %x\n", rc);
4698                 goto error_free;
4699         }
4700         rc = bnxt_init_resources(bp, false);
4701         if (rc)
4702                 goto error_free;
4703
4704         rc = bnxt_alloc_stats_mem(bp);
4705         if (rc)
4706                 goto error_free;
4707
4708         PMD_DRV_LOG(INFO,
4709                     DRV_MODULE_NAME "found at mem %" PRIX64 ", node addr %pM\n",
4710                     pci_dev->mem_resource[0].phys_addr,
4711                     pci_dev->mem_resource[0].addr);
4712
4713         return 0;
4714
4715 error_free:
4716         bnxt_dev_uninit(eth_dev);
4717         return rc;
4718 }
4719
4720 static void
4721 bnxt_uninit_locks(struct bnxt *bp)
4722 {
4723         pthread_mutex_destroy(&bp->flow_lock);
4724 }
4725
4726 static int
4727 bnxt_uninit_resources(struct bnxt *bp, bool reconfig_dev)
4728 {
4729         int rc;
4730
4731         bnxt_free_int(bp);
4732         bnxt_free_mem(bp, reconfig_dev);
4733         bnxt_hwrm_func_buf_unrgtr(bp);
4734         rc = bnxt_hwrm_func_driver_unregister(bp, 0);
4735         bp->flags &= ~BNXT_FLAG_REGISTERED;
4736         bnxt_free_ctx_mem(bp);
4737         if (!reconfig_dev) {
4738                 bnxt_free_hwrm_resources(bp);
4739
4740                 if (bp->recovery_info != NULL) {
4741                         rte_free(bp->recovery_info);
4742                         bp->recovery_info = NULL;
4743                 }
4744         }
4745
4746         rte_free(bp->ptp_cfg);
4747         bp->ptp_cfg = NULL;
4748         return rc;
4749 }
4750
4751 static int
4752 bnxt_dev_uninit(struct rte_eth_dev *eth_dev)
4753 {
4754         struct bnxt *bp = eth_dev->data->dev_private;
4755         int rc;
4756
4757         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
4758                 return -EPERM;
4759
4760         PMD_DRV_LOG(DEBUG, "Calling Device uninit\n");
4761
4762         rc = bnxt_uninit_resources(bp, false);
4763
4764         if (bp->grp_info != NULL) {
4765                 rte_free(bp->grp_info);
4766                 bp->grp_info = NULL;
4767         }
4768
4769         if (bp->tx_mem_zone) {
4770                 rte_memzone_free((const struct rte_memzone *)bp->tx_mem_zone);
4771                 bp->tx_mem_zone = NULL;
4772         }
4773
4774         if (bp->rx_mem_zone) {
4775                 rte_memzone_free((const struct rte_memzone *)bp->rx_mem_zone);
4776                 bp->rx_mem_zone = NULL;
4777         }
4778
4779         if (bp->dev_stopped == 0)
4780                 bnxt_dev_close_op(eth_dev);
4781         if (bp->pf.vf_info)
4782                 rte_free(bp->pf.vf_info);
4783         eth_dev->dev_ops = NULL;
4784         eth_dev->rx_pkt_burst = NULL;
4785         eth_dev->tx_pkt_burst = NULL;
4786
4787         bnxt_uninit_locks(bp);
4788
4789         return rc;
4790 }
4791
4792 static int bnxt_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
4793         struct rte_pci_device *pci_dev)
4794 {
4795         return rte_eth_dev_pci_generic_probe(pci_dev, sizeof(struct bnxt),
4796                 bnxt_dev_init);
4797 }
4798
4799 static int bnxt_pci_remove(struct rte_pci_device *pci_dev)
4800 {
4801         if (rte_eal_process_type() == RTE_PROC_PRIMARY)
4802                 return rte_eth_dev_pci_generic_remove(pci_dev,
4803                                 bnxt_dev_uninit);
4804         else
4805                 return rte_eth_dev_pci_generic_remove(pci_dev, NULL);
4806 }
4807
4808 static struct rte_pci_driver bnxt_rte_pmd = {
4809         .id_table = bnxt_pci_id_map,
4810         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
4811         .probe = bnxt_pci_probe,
4812         .remove = bnxt_pci_remove,
4813 };
4814
4815 static bool
4816 is_device_supported(struct rte_eth_dev *dev, struct rte_pci_driver *drv)
4817 {
4818         if (strcmp(dev->device->driver->name, drv->driver.name))
4819                 return false;
4820
4821         return true;
4822 }
4823
4824 bool is_bnxt_supported(struct rte_eth_dev *dev)
4825 {
4826         return is_device_supported(dev, &bnxt_rte_pmd);
4827 }
4828
4829 RTE_INIT(bnxt_init_log)
4830 {
4831         bnxt_logtype_driver = rte_log_register("pmd.net.bnxt.driver");
4832         if (bnxt_logtype_driver >= 0)
4833                 rte_log_set_level(bnxt_logtype_driver, RTE_LOG_NOTICE);
4834 }
4835
4836 RTE_PMD_REGISTER_PCI(net_bnxt, bnxt_rte_pmd);
4837 RTE_PMD_REGISTER_PCI_TABLE(net_bnxt, bnxt_pci_id_map);
4838 RTE_PMD_REGISTER_KMOD_DEP(net_bnxt, "* igb_uio | uio_pci_generic | vfio-pci");