1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2014-2018 Broadcom
10 #include <rte_ethdev_driver.h>
11 #include <rte_ethdev_pci.h>
12 #include <rte_malloc.h>
13 #include <rte_cycles.h>
17 #include "bnxt_filter.h"
18 #include "bnxt_hwrm.h"
20 #include "bnxt_ring.h"
23 #include "bnxt_stats.h"
26 #include "bnxt_vnic.h"
27 #include "hsi_struct_def_dpdk.h"
28 #include "bnxt_nvm_defs.h"
30 #define DRV_MODULE_NAME "bnxt"
31 static const char bnxt_version[] =
32 "Broadcom NetXtreme driver " DRV_MODULE_NAME "\n";
33 int bnxt_logtype_driver;
35 #define PCI_VENDOR_ID_BROADCOM 0x14E4
37 #define BROADCOM_DEV_ID_STRATUS_NIC_VF1 0x1606
38 #define BROADCOM_DEV_ID_STRATUS_NIC_VF2 0x1609
39 #define BROADCOM_DEV_ID_STRATUS_NIC 0x1614
40 #define BROADCOM_DEV_ID_57414_VF 0x16c1
41 #define BROADCOM_DEV_ID_57301 0x16c8
42 #define BROADCOM_DEV_ID_57302 0x16c9
43 #define BROADCOM_DEV_ID_57304_PF 0x16ca
44 #define BROADCOM_DEV_ID_57304_VF 0x16cb
45 #define BROADCOM_DEV_ID_57417_MF 0x16cc
46 #define BROADCOM_DEV_ID_NS2 0x16cd
47 #define BROADCOM_DEV_ID_57311 0x16ce
48 #define BROADCOM_DEV_ID_57312 0x16cf
49 #define BROADCOM_DEV_ID_57402 0x16d0
50 #define BROADCOM_DEV_ID_57404 0x16d1
51 #define BROADCOM_DEV_ID_57406_PF 0x16d2
52 #define BROADCOM_DEV_ID_57406_VF 0x16d3
53 #define BROADCOM_DEV_ID_57402_MF 0x16d4
54 #define BROADCOM_DEV_ID_57407_RJ45 0x16d5
55 #define BROADCOM_DEV_ID_57412 0x16d6
56 #define BROADCOM_DEV_ID_57414 0x16d7
57 #define BROADCOM_DEV_ID_57416_RJ45 0x16d8
58 #define BROADCOM_DEV_ID_57417_RJ45 0x16d9
59 #define BROADCOM_DEV_ID_5741X_VF 0x16dc
60 #define BROADCOM_DEV_ID_57412_MF 0x16de
61 #define BROADCOM_DEV_ID_57314 0x16df
62 #define BROADCOM_DEV_ID_57317_RJ45 0x16e0
63 #define BROADCOM_DEV_ID_5731X_VF 0x16e1
64 #define BROADCOM_DEV_ID_57417_SFP 0x16e2
65 #define BROADCOM_DEV_ID_57416_SFP 0x16e3
66 #define BROADCOM_DEV_ID_57317_SFP 0x16e4
67 #define BROADCOM_DEV_ID_57404_MF 0x16e7
68 #define BROADCOM_DEV_ID_57406_MF 0x16e8
69 #define BROADCOM_DEV_ID_57407_SFP 0x16e9
70 #define BROADCOM_DEV_ID_57407_MF 0x16ea
71 #define BROADCOM_DEV_ID_57414_MF 0x16ec
72 #define BROADCOM_DEV_ID_57416_MF 0x16ee
73 #define BROADCOM_DEV_ID_58802 0xd802
74 #define BROADCOM_DEV_ID_58804 0xd804
75 #define BROADCOM_DEV_ID_58808 0x16f0
77 static const struct rte_pci_id bnxt_pci_id_map[] = {
78 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM,
79 BROADCOM_DEV_ID_STRATUS_NIC_VF1) },
80 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM,
81 BROADCOM_DEV_ID_STRATUS_NIC_VF2) },
82 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_STRATUS_NIC) },
83 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414_VF) },
84 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57301) },
85 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57302) },
86 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57304_PF) },
87 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57304_VF) },
88 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_NS2) },
89 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57402) },
90 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57404) },
91 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57406_PF) },
92 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57406_VF) },
93 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57402_MF) },
94 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57407_RJ45) },
95 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57404_MF) },
96 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57406_MF) },
97 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57407_SFP) },
98 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57407_MF) },
99 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_5741X_VF) },
100 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_5731X_VF) },
101 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57314) },
102 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_MF) },
103 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57311) },
104 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57312) },
105 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57412) },
106 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414) },
107 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_RJ45) },
108 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_RJ45) },
109 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57412_MF) },
110 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57317_RJ45) },
111 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_SFP) },
112 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_SFP) },
113 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57317_SFP) },
114 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414_MF) },
115 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_MF) },
116 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58802) },
117 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58804) },
118 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58808) },
119 { .vendor_id = 0, /* sentinel */ },
122 #define BNXT_ETH_RSS_SUPPORT ( \
124 ETH_RSS_NONFRAG_IPV4_TCP | \
125 ETH_RSS_NONFRAG_IPV4_UDP | \
127 ETH_RSS_NONFRAG_IPV6_TCP | \
128 ETH_RSS_NONFRAG_IPV6_UDP)
130 #define BNXT_DEV_TX_OFFLOAD_SUPPORT (DEV_TX_OFFLOAD_VLAN_INSERT | \
131 DEV_TX_OFFLOAD_IPV4_CKSUM | \
132 DEV_TX_OFFLOAD_TCP_CKSUM | \
133 DEV_TX_OFFLOAD_UDP_CKSUM | \
134 DEV_TX_OFFLOAD_TCP_TSO | \
135 DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM | \
136 DEV_TX_OFFLOAD_VXLAN_TNL_TSO | \
137 DEV_TX_OFFLOAD_GRE_TNL_TSO | \
138 DEV_TX_OFFLOAD_IPIP_TNL_TSO | \
139 DEV_TX_OFFLOAD_GENEVE_TNL_TSO | \
140 DEV_TX_OFFLOAD_MULTI_SEGS)
142 #define BNXT_DEV_RX_OFFLOAD_SUPPORT (DEV_RX_OFFLOAD_VLAN_FILTER | \
143 DEV_RX_OFFLOAD_VLAN_STRIP | \
144 DEV_RX_OFFLOAD_IPV4_CKSUM | \
145 DEV_RX_OFFLOAD_UDP_CKSUM | \
146 DEV_RX_OFFLOAD_TCP_CKSUM | \
147 DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM | \
148 DEV_RX_OFFLOAD_JUMBO_FRAME | \
149 DEV_RX_OFFLOAD_CRC_STRIP | \
150 DEV_RX_OFFLOAD_KEEP_CRC | \
151 DEV_RX_OFFLOAD_TCP_LRO)
153 static int bnxt_vlan_offload_set_op(struct rte_eth_dev *dev, int mask);
154 static void bnxt_print_link_info(struct rte_eth_dev *eth_dev);
155 static int bnxt_mtu_set_op(struct rte_eth_dev *eth_dev, uint16_t new_mtu);
157 /***********************/
160 * High level utility functions
163 static void bnxt_free_mem(struct bnxt *bp)
165 bnxt_free_filter_mem(bp);
166 bnxt_free_vnic_attributes(bp);
167 bnxt_free_vnic_mem(bp);
170 bnxt_free_tx_rings(bp);
171 bnxt_free_rx_rings(bp);
174 static int bnxt_alloc_mem(struct bnxt *bp)
178 rc = bnxt_alloc_vnic_mem(bp);
182 rc = bnxt_alloc_vnic_attributes(bp);
186 rc = bnxt_alloc_filter_mem(bp);
197 static int bnxt_init_chip(struct bnxt *bp)
200 struct rte_eth_link new;
201 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(bp->eth_dev);
202 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
203 uint32_t intr_vector = 0;
204 uint32_t queue_id, base = BNXT_MISC_VEC_ID;
205 uint32_t vec = BNXT_MISC_VEC_ID;
208 /* disable uio/vfio intr/eventfd mapping */
209 rte_intr_disable(intr_handle);
211 if (bp->eth_dev->data->mtu > ETHER_MTU) {
212 bp->eth_dev->data->dev_conf.rxmode.offloads |=
213 DEV_RX_OFFLOAD_JUMBO_FRAME;
214 bp->flags |= BNXT_FLAG_JUMBO;
216 bp->eth_dev->data->dev_conf.rxmode.offloads &=
217 ~DEV_RX_OFFLOAD_JUMBO_FRAME;
218 bp->flags &= ~BNXT_FLAG_JUMBO;
221 rc = bnxt_alloc_all_hwrm_stat_ctxs(bp);
223 PMD_DRV_LOG(ERR, "HWRM stat ctx alloc failure rc: %x\n", rc);
227 rc = bnxt_alloc_hwrm_rings(bp);
229 PMD_DRV_LOG(ERR, "HWRM ring alloc failure rc: %x\n", rc);
233 rc = bnxt_alloc_all_hwrm_ring_grps(bp);
235 PMD_DRV_LOG(ERR, "HWRM ring grp alloc failure: %x\n", rc);
239 rc = bnxt_mq_rx_configure(bp);
241 PMD_DRV_LOG(ERR, "MQ mode configure failure rc: %x\n", rc);
245 /* VNIC configuration */
246 for (i = 0; i < bp->nr_vnics; i++) {
247 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
249 rc = bnxt_hwrm_vnic_alloc(bp, vnic);
251 PMD_DRV_LOG(ERR, "HWRM vnic %d alloc failure rc: %x\n",
256 rc = bnxt_hwrm_vnic_ctx_alloc(bp, vnic);
259 "HWRM vnic %d ctx alloc failure rc: %x\n",
264 rc = bnxt_hwrm_vnic_cfg(bp, vnic);
266 PMD_DRV_LOG(ERR, "HWRM vnic %d cfg failure rc: %x\n",
271 rc = bnxt_set_hwrm_vnic_filters(bp, vnic);
274 "HWRM vnic %d filter failure rc: %x\n",
279 rc = bnxt_vnic_rss_configure(bp, vnic);
282 "HWRM vnic set RSS failure rc: %x\n", rc);
286 bnxt_hwrm_vnic_plcmode_cfg(bp, vnic);
288 if (bp->eth_dev->data->dev_conf.rxmode.offloads &
289 DEV_RX_OFFLOAD_TCP_LRO)
290 bnxt_hwrm_vnic_tpa_cfg(bp, vnic, 1);
292 bnxt_hwrm_vnic_tpa_cfg(bp, vnic, 0);
294 rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, &bp->vnic_info[0], 0, NULL);
297 "HWRM cfa l2 rx mask failure rc: %x\n", rc);
301 /* check and configure queue intr-vector mapping */
302 if ((rte_intr_cap_multiple(intr_handle) ||
303 !RTE_ETH_DEV_SRIOV(bp->eth_dev).active) &&
304 bp->eth_dev->data->dev_conf.intr_conf.rxq != 0) {
305 intr_vector = bp->eth_dev->data->nb_rx_queues;
306 PMD_DRV_LOG(DEBUG, "intr_vector = %d\n", intr_vector);
307 if (intr_vector > bp->rx_cp_nr_rings) {
308 PMD_DRV_LOG(ERR, "At most %d intr queues supported",
312 if (rte_intr_efd_enable(intr_handle, intr_vector))
316 if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
317 intr_handle->intr_vec =
318 rte_zmalloc("intr_vec",
319 bp->eth_dev->data->nb_rx_queues *
321 if (intr_handle->intr_vec == NULL) {
322 PMD_DRV_LOG(ERR, "Failed to allocate %d rx_queues"
323 " intr_vec", bp->eth_dev->data->nb_rx_queues);
326 PMD_DRV_LOG(DEBUG, "intr_handle->intr_vec = %p "
327 "intr_handle->nb_efd = %d intr_handle->max_intr = %d\n",
328 intr_handle->intr_vec, intr_handle->nb_efd,
329 intr_handle->max_intr);
332 for (queue_id = 0; queue_id < bp->eth_dev->data->nb_rx_queues;
334 intr_handle->intr_vec[queue_id] = vec;
335 if (vec < base + intr_handle->nb_efd - 1)
339 /* enable uio/vfio intr/eventfd mapping */
340 rte_intr_enable(intr_handle);
342 rc = bnxt_get_hwrm_link_config(bp, &new);
344 PMD_DRV_LOG(ERR, "HWRM Get link config failure rc: %x\n", rc);
348 if (!bp->link_info.link_up) {
349 rc = bnxt_set_hwrm_link_config(bp, true);
352 "HWRM link config failure rc: %x\n", rc);
356 bnxt_print_link_info(bp->eth_dev);
361 bnxt_free_all_hwrm_resources(bp);
363 /* Some of the error status returned by FW may not be from errno.h */
370 static int bnxt_shutdown_nic(struct bnxt *bp)
372 bnxt_free_all_hwrm_resources(bp);
373 bnxt_free_all_filters(bp);
374 bnxt_free_all_vnics(bp);
378 static int bnxt_init_nic(struct bnxt *bp)
382 rc = bnxt_init_ring_grps(bp);
387 bnxt_init_filters(bp);
393 * Device configuration and status function
396 static void bnxt_dev_info_get_op(struct rte_eth_dev *eth_dev,
397 struct rte_eth_dev_info *dev_info)
399 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
400 uint16_t max_vnics, i, j, vpool, vrxq;
401 unsigned int max_rx_rings;
404 dev_info->max_mac_addrs = bp->max_l2_ctx;
405 dev_info->max_hash_mac_addrs = 0;
407 /* PF/VF specifics */
409 dev_info->max_vfs = bp->pdev->max_vfs;
410 max_rx_rings = RTE_MIN(bp->max_vnics, bp->max_stat_ctx);
411 /* For the sake of symmetry, max_rx_queues = max_tx_queues */
412 dev_info->max_rx_queues = max_rx_rings;
413 dev_info->max_tx_queues = max_rx_rings;
414 dev_info->reta_size = bp->max_rsscos_ctx;
415 dev_info->hash_key_size = 40;
416 max_vnics = bp->max_vnics;
418 /* Fast path specifics */
419 dev_info->min_rx_bufsize = 1;
420 dev_info->max_rx_pktlen = BNXT_MAX_MTU + ETHER_HDR_LEN + ETHER_CRC_LEN
423 dev_info->rx_offload_capa = BNXT_DEV_RX_OFFLOAD_SUPPORT;
424 if (bp->flags & BNXT_FLAG_PTP_SUPPORTED)
425 dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_TIMESTAMP;
426 dev_info->tx_offload_capa = BNXT_DEV_TX_OFFLOAD_SUPPORT;
427 dev_info->flow_type_rss_offloads = BNXT_ETH_RSS_SUPPORT;
430 dev_info->default_rxconf = (struct rte_eth_rxconf) {
436 .rx_free_thresh = 32,
437 /* If no descriptors available, pkts are dropped by default */
441 dev_info->default_txconf = (struct rte_eth_txconf) {
447 .tx_free_thresh = 32,
450 eth_dev->data->dev_conf.intr_conf.lsc = 1;
452 eth_dev->data->dev_conf.intr_conf.rxq = 1;
457 * TODO: default_rxconf, default_txconf, rx_desc_lim, and tx_desc_lim
458 * need further investigation.
462 vpool = 64; /* ETH_64_POOLS */
463 vrxq = 128; /* ETH_VMDQ_DCB_NUM_QUEUES */
464 for (i = 0; i < 4; vpool >>= 1, i++) {
465 if (max_vnics > vpool) {
466 for (j = 0; j < 5; vrxq >>= 1, j++) {
467 if (dev_info->max_rx_queues > vrxq) {
473 /* Not enough resources to support VMDq */
477 /* Not enough resources to support VMDq */
481 dev_info->max_vmdq_pools = vpool;
482 dev_info->vmdq_queue_num = vrxq;
484 dev_info->vmdq_pool_base = 0;
485 dev_info->vmdq_queue_base = 0;
488 /* Configure the device based on the configuration provided */
489 static int bnxt_dev_configure_op(struct rte_eth_dev *eth_dev)
491 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
492 uint64_t rx_offloads = eth_dev->data->dev_conf.rxmode.offloads;
494 bp->rx_queues = (void *)eth_dev->data->rx_queues;
495 bp->tx_queues = (void *)eth_dev->data->tx_queues;
496 bp->tx_nr_rings = eth_dev->data->nb_tx_queues;
497 bp->rx_nr_rings = eth_dev->data->nb_rx_queues;
499 if (BNXT_VF(bp) && (bp->flags & BNXT_FLAG_NEW_RM)) {
502 rc = bnxt_hwrm_func_reserve_vf_resc(bp);
504 PMD_DRV_LOG(ERR, "HWRM resource alloc fail:%x\n", rc);
508 /* legacy driver needs to get updated values */
509 rc = bnxt_hwrm_func_qcaps(bp);
511 PMD_DRV_LOG(ERR, "hwrm func qcaps fail:%d\n", rc);
516 /* Inherit new configurations */
517 if (eth_dev->data->nb_rx_queues > bp->max_rx_rings ||
518 eth_dev->data->nb_tx_queues > bp->max_tx_rings ||
519 eth_dev->data->nb_rx_queues + eth_dev->data->nb_tx_queues >
521 eth_dev->data->nb_rx_queues + eth_dev->data->nb_tx_queues >
523 (uint32_t)(eth_dev->data->nb_rx_queues) > bp->max_ring_grps) {
525 "Insufficient resources to support requested config\n");
527 "Num Queues Requested: Tx %d, Rx %d\n",
528 eth_dev->data->nb_tx_queues,
529 eth_dev->data->nb_rx_queues);
531 "Res available: TxQ %d, RxQ %d, CQ %d Stat %d, Grp %d\n",
532 bp->max_tx_rings, bp->max_rx_rings, bp->max_cp_rings,
533 bp->max_stat_ctx, bp->max_ring_grps);
537 bp->rx_cp_nr_rings = bp->rx_nr_rings;
538 bp->tx_cp_nr_rings = bp->tx_nr_rings;
540 if (rx_offloads & DEV_RX_OFFLOAD_JUMBO_FRAME) {
542 eth_dev->data->dev_conf.rxmode.max_rx_pkt_len -
543 ETHER_HDR_LEN - ETHER_CRC_LEN - VLAN_TAG_SIZE *
545 bnxt_mtu_set_op(eth_dev, eth_dev->data->mtu);
550 static void bnxt_print_link_info(struct rte_eth_dev *eth_dev)
552 struct rte_eth_link *link = ð_dev->data->dev_link;
554 if (link->link_status)
555 PMD_DRV_LOG(INFO, "Port %d Link Up - speed %u Mbps - %s\n",
556 eth_dev->data->port_id,
557 (uint32_t)link->link_speed,
558 (link->link_duplex == ETH_LINK_FULL_DUPLEX) ?
559 ("full-duplex") : ("half-duplex\n"));
561 PMD_DRV_LOG(INFO, "Port %d Link Down\n",
562 eth_dev->data->port_id);
565 static int bnxt_dev_lsc_intr_setup(struct rte_eth_dev *eth_dev)
567 bnxt_print_link_info(eth_dev);
571 static int bnxt_dev_start_op(struct rte_eth_dev *eth_dev)
573 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
574 uint64_t rx_offloads = eth_dev->data->dev_conf.rxmode.offloads;
578 if (bp->rx_cp_nr_rings > RTE_ETHDEV_QUEUE_STAT_CNTRS) {
580 "RxQ cnt %d > CONFIG_RTE_ETHDEV_QUEUE_STAT_CNTRS %d\n",
581 bp->rx_cp_nr_rings, RTE_ETHDEV_QUEUE_STAT_CNTRS);
585 rc = bnxt_init_chip(bp);
589 bnxt_link_update_op(eth_dev, 1);
591 if (rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER)
592 vlan_mask |= ETH_VLAN_FILTER_MASK;
593 if (rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
594 vlan_mask |= ETH_VLAN_STRIP_MASK;
595 rc = bnxt_vlan_offload_set_op(eth_dev, vlan_mask);
599 bp->flags |= BNXT_FLAG_INIT_DONE;
603 bnxt_shutdown_nic(bp);
604 bnxt_free_tx_mbufs(bp);
605 bnxt_free_rx_mbufs(bp);
609 static int bnxt_dev_set_link_up_op(struct rte_eth_dev *eth_dev)
611 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
614 if (!bp->link_info.link_up)
615 rc = bnxt_set_hwrm_link_config(bp, true);
617 eth_dev->data->dev_link.link_status = 1;
619 bnxt_print_link_info(eth_dev);
623 static int bnxt_dev_set_link_down_op(struct rte_eth_dev *eth_dev)
625 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
627 eth_dev->data->dev_link.link_status = 0;
628 bnxt_set_hwrm_link_config(bp, false);
629 bp->link_info.link_up = 0;
634 /* Unload the driver, release resources */
635 static void bnxt_dev_stop_op(struct rte_eth_dev *eth_dev)
637 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
639 bp->flags &= ~BNXT_FLAG_INIT_DONE;
640 if (bp->eth_dev->data->dev_started) {
641 /* TBD: STOP HW queues DMA */
642 eth_dev->data->dev_link.link_status = 0;
644 bnxt_set_hwrm_link_config(bp, false);
645 bnxt_hwrm_port_clr_stats(bp);
646 bnxt_free_tx_mbufs(bp);
647 bnxt_free_rx_mbufs(bp);
648 bnxt_shutdown_nic(bp);
652 static void bnxt_dev_close_op(struct rte_eth_dev *eth_dev)
654 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
656 if (bp->dev_stopped == 0)
657 bnxt_dev_stop_op(eth_dev);
660 if (eth_dev->data->mac_addrs != NULL) {
661 rte_free(eth_dev->data->mac_addrs);
662 eth_dev->data->mac_addrs = NULL;
664 if (bp->grp_info != NULL) {
665 rte_free(bp->grp_info);
670 static void bnxt_mac_addr_remove_op(struct rte_eth_dev *eth_dev,
673 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
674 uint64_t pool_mask = eth_dev->data->mac_pool_sel[index];
675 struct bnxt_vnic_info *vnic;
676 struct bnxt_filter_info *filter, *temp_filter;
677 uint32_t pool = RTE_MIN(MAX_FF_POOLS, ETH_64_POOLS);
681 * Loop through all VNICs from the specified filter flow pools to
682 * remove the corresponding MAC addr filter
684 for (i = 0; i < pool; i++) {
685 if (!(pool_mask & (1ULL << i)))
688 STAILQ_FOREACH(vnic, &bp->ff_pool[i], next) {
689 filter = STAILQ_FIRST(&vnic->filter);
691 temp_filter = STAILQ_NEXT(filter, next);
692 if (filter->mac_index == index) {
693 STAILQ_REMOVE(&vnic->filter, filter,
694 bnxt_filter_info, next);
695 bnxt_hwrm_clear_l2_filter(bp, filter);
696 filter->mac_index = INVALID_MAC_INDEX;
697 memset(&filter->l2_addr, 0,
700 &bp->free_filter_list,
703 filter = temp_filter;
709 static int bnxt_mac_addr_add_op(struct rte_eth_dev *eth_dev,
710 struct ether_addr *mac_addr,
711 uint32_t index, uint32_t pool)
713 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
714 struct bnxt_vnic_info *vnic = STAILQ_FIRST(&bp->ff_pool[pool]);
715 struct bnxt_filter_info *filter;
718 PMD_DRV_LOG(ERR, "Cannot add MAC address to a VF interface\n");
723 PMD_DRV_LOG(ERR, "VNIC not found for pool %d!\n", pool);
726 /* Attach requested MAC address to the new l2_filter */
727 STAILQ_FOREACH(filter, &vnic->filter, next) {
728 if (filter->mac_index == index) {
730 "MAC addr already existed for pool %d\n", pool);
734 filter = bnxt_alloc_filter(bp);
736 PMD_DRV_LOG(ERR, "L2 filter alloc failed\n");
739 STAILQ_INSERT_TAIL(&vnic->filter, filter, next);
740 filter->mac_index = index;
741 memcpy(filter->l2_addr, mac_addr, ETHER_ADDR_LEN);
742 return bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id, filter);
745 int bnxt_link_update_op(struct rte_eth_dev *eth_dev, int wait_to_complete)
748 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
749 struct rte_eth_link new;
750 unsigned int cnt = BNXT_LINK_WAIT_CNT;
752 memset(&new, 0, sizeof(new));
754 /* Retrieve link info from hardware */
755 rc = bnxt_get_hwrm_link_config(bp, &new);
757 new.link_speed = ETH_LINK_SPEED_100M;
758 new.link_duplex = ETH_LINK_FULL_DUPLEX;
760 "Failed to retrieve link rc = 0x%x!\n", rc);
763 rte_delay_ms(BNXT_LINK_WAIT_INTERVAL);
765 if (!wait_to_complete)
767 } while (!new.link_status && cnt--);
770 /* Timed out or success */
771 if (new.link_status != eth_dev->data->dev_link.link_status ||
772 new.link_speed != eth_dev->data->dev_link.link_speed) {
773 memcpy(ð_dev->data->dev_link, &new,
774 sizeof(struct rte_eth_link));
776 _rte_eth_dev_callback_process(eth_dev,
777 RTE_ETH_EVENT_INTR_LSC,
780 bnxt_print_link_info(eth_dev);
786 static void bnxt_promiscuous_enable_op(struct rte_eth_dev *eth_dev)
788 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
789 struct bnxt_vnic_info *vnic;
791 if (bp->vnic_info == NULL)
794 vnic = &bp->vnic_info[0];
796 vnic->flags |= BNXT_VNIC_INFO_PROMISC;
797 bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
800 static void bnxt_promiscuous_disable_op(struct rte_eth_dev *eth_dev)
802 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
803 struct bnxt_vnic_info *vnic;
805 if (bp->vnic_info == NULL)
808 vnic = &bp->vnic_info[0];
810 vnic->flags &= ~BNXT_VNIC_INFO_PROMISC;
811 bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
814 static void bnxt_allmulticast_enable_op(struct rte_eth_dev *eth_dev)
816 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
817 struct bnxt_vnic_info *vnic;
819 if (bp->vnic_info == NULL)
822 vnic = &bp->vnic_info[0];
824 vnic->flags |= BNXT_VNIC_INFO_ALLMULTI;
825 bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
828 static void bnxt_allmulticast_disable_op(struct rte_eth_dev *eth_dev)
830 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
831 struct bnxt_vnic_info *vnic;
833 if (bp->vnic_info == NULL)
836 vnic = &bp->vnic_info[0];
838 vnic->flags &= ~BNXT_VNIC_INFO_ALLMULTI;
839 bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
842 static int bnxt_reta_update_op(struct rte_eth_dev *eth_dev,
843 struct rte_eth_rss_reta_entry64 *reta_conf,
846 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
847 struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
848 struct bnxt_vnic_info *vnic;
851 if (!(dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG))
854 if (reta_size != HW_HASH_INDEX_SIZE) {
855 PMD_DRV_LOG(ERR, "The configured hash table lookup size "
856 "(%d) must equal the size supported by the hardware "
857 "(%d)\n", reta_size, HW_HASH_INDEX_SIZE);
860 /* Update the RSS VNIC(s) */
861 for (i = 0; i < MAX_FF_POOLS; i++) {
862 STAILQ_FOREACH(vnic, &bp->ff_pool[i], next) {
863 memcpy(vnic->rss_table, reta_conf, reta_size);
865 bnxt_hwrm_vnic_rss_cfg(bp, vnic);
871 static int bnxt_reta_query_op(struct rte_eth_dev *eth_dev,
872 struct rte_eth_rss_reta_entry64 *reta_conf,
875 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
876 struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
877 struct rte_intr_handle *intr_handle
878 = &bp->pdev->intr_handle;
880 /* Retrieve from the default VNIC */
883 if (!vnic->rss_table)
886 if (reta_size != HW_HASH_INDEX_SIZE) {
887 PMD_DRV_LOG(ERR, "The configured hash table lookup size "
888 "(%d) must equal the size supported by the hardware "
889 "(%d)\n", reta_size, HW_HASH_INDEX_SIZE);
892 /* EW - need to revisit here copying from uint64_t to uint16_t */
893 memcpy(reta_conf, vnic->rss_table, reta_size);
895 if (rte_intr_allow_others(intr_handle)) {
896 if (eth_dev->data->dev_conf.intr_conf.lsc != 0)
897 bnxt_dev_lsc_intr_setup(eth_dev);
903 static int bnxt_rss_hash_update_op(struct rte_eth_dev *eth_dev,
904 struct rte_eth_rss_conf *rss_conf)
906 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
907 struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
908 struct bnxt_vnic_info *vnic;
909 uint16_t hash_type = 0;
913 * If RSS enablement were different than dev_configure,
914 * then return -EINVAL
916 if (dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG) {
917 if (!rss_conf->rss_hf)
918 PMD_DRV_LOG(ERR, "Hash type NONE\n");
920 if (rss_conf->rss_hf & BNXT_ETH_RSS_SUPPORT)
924 bp->flags |= BNXT_FLAG_UPDATE_HASH;
925 memcpy(&bp->rss_conf, rss_conf, sizeof(*rss_conf));
927 if (rss_conf->rss_hf & ETH_RSS_IPV4)
928 hash_type |= HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV4;
929 if (rss_conf->rss_hf & ETH_RSS_NONFRAG_IPV4_TCP)
930 hash_type |= HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV4;
931 if (rss_conf->rss_hf & ETH_RSS_NONFRAG_IPV4_UDP)
932 hash_type |= HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV4;
933 if (rss_conf->rss_hf & ETH_RSS_IPV6)
934 hash_type |= HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6;
935 if (rss_conf->rss_hf & ETH_RSS_NONFRAG_IPV6_TCP)
936 hash_type |= HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV6;
937 if (rss_conf->rss_hf & ETH_RSS_NONFRAG_IPV6_UDP)
938 hash_type |= HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV6;
940 /* Update the RSS VNIC(s) */
941 for (i = 0; i < MAX_FF_POOLS; i++) {
942 STAILQ_FOREACH(vnic, &bp->ff_pool[i], next) {
943 vnic->hash_type = hash_type;
946 * Use the supplied key if the key length is
947 * acceptable and the rss_key is not NULL
949 if (rss_conf->rss_key &&
950 rss_conf->rss_key_len <= HW_HASH_KEY_SIZE)
951 memcpy(vnic->rss_hash_key, rss_conf->rss_key,
952 rss_conf->rss_key_len);
954 bnxt_hwrm_vnic_rss_cfg(bp, vnic);
960 static int bnxt_rss_hash_conf_get_op(struct rte_eth_dev *eth_dev,
961 struct rte_eth_rss_conf *rss_conf)
963 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
964 struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
968 /* RSS configuration is the same for all VNICs */
969 if (vnic && vnic->rss_hash_key) {
970 if (rss_conf->rss_key) {
971 len = rss_conf->rss_key_len <= HW_HASH_KEY_SIZE ?
972 rss_conf->rss_key_len : HW_HASH_KEY_SIZE;
973 memcpy(rss_conf->rss_key, vnic->rss_hash_key, len);
976 hash_types = vnic->hash_type;
977 rss_conf->rss_hf = 0;
978 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV4) {
979 rss_conf->rss_hf |= ETH_RSS_IPV4;
980 hash_types &= ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV4;
982 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV4) {
983 rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP;
985 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV4;
987 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV4) {
988 rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
990 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV4;
992 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6) {
993 rss_conf->rss_hf |= ETH_RSS_IPV6;
994 hash_types &= ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6;
996 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV6) {
997 rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV6_TCP;
999 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV6;
1001 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV6) {
1002 rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;
1004 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV6;
1008 "Unknwon RSS config from firmware (%08x), RSS disabled",
1013 rss_conf->rss_hf = 0;
1018 static int bnxt_flow_ctrl_get_op(struct rte_eth_dev *dev,
1019 struct rte_eth_fc_conf *fc_conf)
1021 struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
1022 struct rte_eth_link link_info;
1025 rc = bnxt_get_hwrm_link_config(bp, &link_info);
1029 memset(fc_conf, 0, sizeof(*fc_conf));
1030 if (bp->link_info.auto_pause)
1031 fc_conf->autoneg = 1;
1032 switch (bp->link_info.pause) {
1034 fc_conf->mode = RTE_FC_NONE;
1036 case HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_TX:
1037 fc_conf->mode = RTE_FC_TX_PAUSE;
1039 case HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_RX:
1040 fc_conf->mode = RTE_FC_RX_PAUSE;
1042 case (HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_TX |
1043 HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_RX):
1044 fc_conf->mode = RTE_FC_FULL;
1050 static int bnxt_flow_ctrl_set_op(struct rte_eth_dev *dev,
1051 struct rte_eth_fc_conf *fc_conf)
1053 struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
1055 if (!BNXT_SINGLE_PF(bp) || BNXT_VF(bp)) {
1056 PMD_DRV_LOG(ERR, "Flow Control Settings cannot be modified\n");
1060 switch (fc_conf->mode) {
1062 bp->link_info.auto_pause = 0;
1063 bp->link_info.force_pause = 0;
1065 case RTE_FC_RX_PAUSE:
1066 if (fc_conf->autoneg) {
1067 bp->link_info.auto_pause =
1068 HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_RX;
1069 bp->link_info.force_pause = 0;
1071 bp->link_info.auto_pause = 0;
1072 bp->link_info.force_pause =
1073 HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_RX;
1076 case RTE_FC_TX_PAUSE:
1077 if (fc_conf->autoneg) {
1078 bp->link_info.auto_pause =
1079 HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_TX;
1080 bp->link_info.force_pause = 0;
1082 bp->link_info.auto_pause = 0;
1083 bp->link_info.force_pause =
1084 HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_TX;
1088 if (fc_conf->autoneg) {
1089 bp->link_info.auto_pause =
1090 HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_TX |
1091 HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_RX;
1092 bp->link_info.force_pause = 0;
1094 bp->link_info.auto_pause = 0;
1095 bp->link_info.force_pause =
1096 HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_TX |
1097 HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_RX;
1101 return bnxt_set_hwrm_link_config(bp, true);
1104 /* Add UDP tunneling port */
1106 bnxt_udp_tunnel_port_add_op(struct rte_eth_dev *eth_dev,
1107 struct rte_eth_udp_tunnel *udp_tunnel)
1109 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
1110 uint16_t tunnel_type = 0;
1113 switch (udp_tunnel->prot_type) {
1114 case RTE_TUNNEL_TYPE_VXLAN:
1115 if (bp->vxlan_port_cnt) {
1116 PMD_DRV_LOG(ERR, "Tunnel Port %d already programmed\n",
1117 udp_tunnel->udp_port);
1118 if (bp->vxlan_port != udp_tunnel->udp_port) {
1119 PMD_DRV_LOG(ERR, "Only one port allowed\n");
1122 bp->vxlan_port_cnt++;
1126 HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_VXLAN;
1127 bp->vxlan_port_cnt++;
1129 case RTE_TUNNEL_TYPE_GENEVE:
1130 if (bp->geneve_port_cnt) {
1131 PMD_DRV_LOG(ERR, "Tunnel Port %d already programmed\n",
1132 udp_tunnel->udp_port);
1133 if (bp->geneve_port != udp_tunnel->udp_port) {
1134 PMD_DRV_LOG(ERR, "Only one port allowed\n");
1137 bp->geneve_port_cnt++;
1141 HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_GENEVE;
1142 bp->geneve_port_cnt++;
1145 PMD_DRV_LOG(ERR, "Tunnel type is not supported\n");
1148 rc = bnxt_hwrm_tunnel_dst_port_alloc(bp, udp_tunnel->udp_port,
1154 bnxt_udp_tunnel_port_del_op(struct rte_eth_dev *eth_dev,
1155 struct rte_eth_udp_tunnel *udp_tunnel)
1157 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
1158 uint16_t tunnel_type = 0;
1162 switch (udp_tunnel->prot_type) {
1163 case RTE_TUNNEL_TYPE_VXLAN:
1164 if (!bp->vxlan_port_cnt) {
1165 PMD_DRV_LOG(ERR, "No Tunnel port configured yet\n");
1168 if (bp->vxlan_port != udp_tunnel->udp_port) {
1169 PMD_DRV_LOG(ERR, "Req Port: %d. Configured port: %d\n",
1170 udp_tunnel->udp_port, bp->vxlan_port);
1173 if (--bp->vxlan_port_cnt)
1177 HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN;
1178 port = bp->vxlan_fw_dst_port_id;
1180 case RTE_TUNNEL_TYPE_GENEVE:
1181 if (!bp->geneve_port_cnt) {
1182 PMD_DRV_LOG(ERR, "No Tunnel port configured yet\n");
1185 if (bp->geneve_port != udp_tunnel->udp_port) {
1186 PMD_DRV_LOG(ERR, "Req Port: %d. Configured port: %d\n",
1187 udp_tunnel->udp_port, bp->geneve_port);
1190 if (--bp->geneve_port_cnt)
1194 HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_GENEVE;
1195 port = bp->geneve_fw_dst_port_id;
1198 PMD_DRV_LOG(ERR, "Tunnel type is not supported\n");
1202 rc = bnxt_hwrm_tunnel_dst_port_free(bp, port, tunnel_type);
1205 HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN)
1208 HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_GENEVE)
1209 bp->geneve_port = 0;
1214 static int bnxt_del_vlan_filter(struct bnxt *bp, uint16_t vlan_id)
1216 struct bnxt_filter_info *filter, *temp_filter, *new_filter;
1217 struct bnxt_vnic_info *vnic;
1220 uint32_t chk = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_OVLAN;
1222 /* Cycle through all VNICs */
1223 for (i = 0; i < bp->nr_vnics; i++) {
1225 * For each VNIC and each associated filter(s)
1226 * if VLAN exists && VLAN matches vlan_id
1227 * remove the MAC+VLAN filter
1228 * add a new MAC only filter
1230 * VLAN filter doesn't exist, just skip and continue
1232 STAILQ_FOREACH(vnic, &bp->ff_pool[i], next) {
1233 filter = STAILQ_FIRST(&vnic->filter);
1235 temp_filter = STAILQ_NEXT(filter, next);
1237 if (filter->enables & chk &&
1238 filter->l2_ovlan == vlan_id) {
1239 /* Must delete the filter */
1240 STAILQ_REMOVE(&vnic->filter, filter,
1241 bnxt_filter_info, next);
1242 bnxt_hwrm_clear_l2_filter(bp, filter);
1244 &bp->free_filter_list,
1248 * Need to examine to see if the MAC
1249 * filter already existed or not before
1250 * allocating a new one
1253 new_filter = bnxt_alloc_filter(bp);
1256 "MAC/VLAN filter alloc failed\n");
1260 STAILQ_INSERT_TAIL(&vnic->filter,
1262 /* Inherit MAC from previous filter */
1263 new_filter->mac_index =
1265 memcpy(new_filter->l2_addr,
1266 filter->l2_addr, ETHER_ADDR_LEN);
1267 /* MAC only filter */
1268 rc = bnxt_hwrm_set_l2_filter(bp,
1274 "Del Vlan filter for %d\n",
1277 filter = temp_filter;
1285 static int bnxt_add_vlan_filter(struct bnxt *bp, uint16_t vlan_id)
1287 struct bnxt_filter_info *filter, *temp_filter, *new_filter;
1288 struct bnxt_vnic_info *vnic;
1291 uint32_t en = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_OVLAN |
1292 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_OVLAN_MASK;
1293 uint32_t chk = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_OVLAN;
1295 /* Cycle through all VNICs */
1296 for (i = 0; i < bp->nr_vnics; i++) {
1298 * For each VNIC and each associated filter(s)
1300 * if VLAN matches vlan_id
1301 * VLAN filter already exists, just skip and continue
1303 * add a new MAC+VLAN filter
1305 * Remove the old MAC only filter
1306 * Add a new MAC+VLAN filter
1308 STAILQ_FOREACH(vnic, &bp->ff_pool[i], next) {
1309 filter = STAILQ_FIRST(&vnic->filter);
1311 temp_filter = STAILQ_NEXT(filter, next);
1313 if (filter->enables & chk) {
1314 if (filter->l2_ovlan == vlan_id)
1317 /* Must delete the MAC filter */
1318 STAILQ_REMOVE(&vnic->filter, filter,
1319 bnxt_filter_info, next);
1320 bnxt_hwrm_clear_l2_filter(bp, filter);
1321 filter->l2_ovlan = 0;
1323 &bp->free_filter_list,
1326 new_filter = bnxt_alloc_filter(bp);
1329 "MAC/VLAN filter alloc failed\n");
1333 STAILQ_INSERT_TAIL(&vnic->filter, new_filter,
1335 /* Inherit MAC from the previous filter */
1336 new_filter->mac_index = filter->mac_index;
1337 memcpy(new_filter->l2_addr, filter->l2_addr,
1339 /* MAC + VLAN ID filter */
1340 new_filter->l2_ovlan = vlan_id;
1341 new_filter->l2_ovlan_mask = 0xF000;
1342 new_filter->enables |= en;
1343 rc = bnxt_hwrm_set_l2_filter(bp,
1349 "Added Vlan filter for %d\n", vlan_id);
1351 filter = temp_filter;
1359 static int bnxt_vlan_filter_set_op(struct rte_eth_dev *eth_dev,
1360 uint16_t vlan_id, int on)
1362 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
1364 /* These operations apply to ALL existing MAC/VLAN filters */
1366 return bnxt_add_vlan_filter(bp, vlan_id);
1368 return bnxt_del_vlan_filter(bp, vlan_id);
1372 bnxt_vlan_offload_set_op(struct rte_eth_dev *dev, int mask)
1374 struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
1375 uint64_t rx_offloads = dev->data->dev_conf.rxmode.offloads;
1378 if (mask & ETH_VLAN_FILTER_MASK) {
1379 if (!(rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER)) {
1380 /* Remove any VLAN filters programmed */
1381 for (i = 0; i < 4095; i++)
1382 bnxt_del_vlan_filter(bp, i);
1384 PMD_DRV_LOG(DEBUG, "VLAN Filtering: %d\n",
1385 !!(rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER));
1388 if (mask & ETH_VLAN_STRIP_MASK) {
1389 /* Enable or disable VLAN stripping */
1390 for (i = 0; i < bp->nr_vnics; i++) {
1391 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
1392 if (rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
1393 vnic->vlan_strip = true;
1395 vnic->vlan_strip = false;
1396 bnxt_hwrm_vnic_cfg(bp, vnic);
1398 PMD_DRV_LOG(DEBUG, "VLAN Strip Offload: %d\n",
1399 !!(rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP));
1402 if (mask & ETH_VLAN_EXTEND_MASK)
1403 PMD_DRV_LOG(ERR, "Extend VLAN Not supported\n");
1409 bnxt_set_default_mac_addr_op(struct rte_eth_dev *dev, struct ether_addr *addr)
1411 struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
1412 /* Default Filter is tied to VNIC 0 */
1413 struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
1414 struct bnxt_filter_info *filter;
1420 memcpy(bp->mac_addr, addr, sizeof(bp->mac_addr));
1422 STAILQ_FOREACH(filter, &vnic->filter, next) {
1423 /* Default Filter is at Index 0 */
1424 if (filter->mac_index != 0)
1426 rc = bnxt_hwrm_clear_l2_filter(bp, filter);
1429 memcpy(filter->l2_addr, bp->mac_addr, ETHER_ADDR_LEN);
1430 memset(filter->l2_addr_mask, 0xff, ETHER_ADDR_LEN);
1431 filter->flags |= HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_PATH_RX;
1433 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR |
1434 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR_MASK;
1435 rc = bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id, filter);
1438 filter->mac_index = 0;
1439 PMD_DRV_LOG(DEBUG, "Set MAC addr\n");
1446 bnxt_dev_set_mc_addr_list_op(struct rte_eth_dev *eth_dev,
1447 struct ether_addr *mc_addr_set,
1448 uint32_t nb_mc_addr)
1450 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
1451 char *mc_addr_list = (char *)mc_addr_set;
1452 struct bnxt_vnic_info *vnic;
1453 uint32_t off = 0, i = 0;
1455 vnic = &bp->vnic_info[0];
1457 if (nb_mc_addr > BNXT_MAX_MC_ADDRS) {
1458 vnic->flags |= BNXT_VNIC_INFO_ALLMULTI;
1462 /* TODO Check for Duplicate mcast addresses */
1463 vnic->flags &= ~BNXT_VNIC_INFO_ALLMULTI;
1464 for (i = 0; i < nb_mc_addr; i++) {
1465 memcpy(vnic->mc_list + off, &mc_addr_list[i], ETHER_ADDR_LEN);
1466 off += ETHER_ADDR_LEN;
1469 vnic->mc_addr_cnt = i;
1472 return bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1476 bnxt_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size)
1478 struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
1479 uint8_t fw_major = (bp->fw_ver >> 24) & 0xff;
1480 uint8_t fw_minor = (bp->fw_ver >> 16) & 0xff;
1481 uint8_t fw_updt = (bp->fw_ver >> 8) & 0xff;
1484 ret = snprintf(fw_version, fw_size, "%d.%d.%d",
1485 fw_major, fw_minor, fw_updt);
1487 ret += 1; /* add the size of '\0' */
1488 if (fw_size < (uint32_t)ret)
1495 bnxt_rxq_info_get_op(struct rte_eth_dev *dev, uint16_t queue_id,
1496 struct rte_eth_rxq_info *qinfo)
1498 struct bnxt_rx_queue *rxq;
1500 rxq = dev->data->rx_queues[queue_id];
1502 qinfo->mp = rxq->mb_pool;
1503 qinfo->scattered_rx = dev->data->scattered_rx;
1504 qinfo->nb_desc = rxq->nb_rx_desc;
1506 qinfo->conf.rx_free_thresh = rxq->rx_free_thresh;
1507 qinfo->conf.rx_drop_en = 0;
1508 qinfo->conf.rx_deferred_start = 0;
1512 bnxt_txq_info_get_op(struct rte_eth_dev *dev, uint16_t queue_id,
1513 struct rte_eth_txq_info *qinfo)
1515 struct bnxt_tx_queue *txq;
1517 txq = dev->data->tx_queues[queue_id];
1519 qinfo->nb_desc = txq->nb_tx_desc;
1521 qinfo->conf.tx_thresh.pthresh = txq->pthresh;
1522 qinfo->conf.tx_thresh.hthresh = txq->hthresh;
1523 qinfo->conf.tx_thresh.wthresh = txq->wthresh;
1525 qinfo->conf.tx_free_thresh = txq->tx_free_thresh;
1526 qinfo->conf.tx_rs_thresh = 0;
1527 qinfo->conf.tx_deferred_start = txq->tx_deferred_start;
1530 static int bnxt_mtu_set_op(struct rte_eth_dev *eth_dev, uint16_t new_mtu)
1532 struct bnxt *bp = eth_dev->data->dev_private;
1533 struct rte_eth_dev_info dev_info;
1534 uint32_t max_dev_mtu;
1538 bnxt_dev_info_get_op(eth_dev, &dev_info);
1539 max_dev_mtu = dev_info.max_rx_pktlen -
1540 ETHER_HDR_LEN - ETHER_CRC_LEN - VLAN_TAG_SIZE * 2;
1542 if (new_mtu < ETHER_MIN_MTU || new_mtu > max_dev_mtu) {
1543 PMD_DRV_LOG(ERR, "MTU requested must be within (%d, %d)\n",
1544 ETHER_MIN_MTU, max_dev_mtu);
1549 if (new_mtu > ETHER_MTU) {
1550 bp->flags |= BNXT_FLAG_JUMBO;
1551 bp->eth_dev->data->dev_conf.rxmode.offloads |=
1552 DEV_RX_OFFLOAD_JUMBO_FRAME;
1554 bp->eth_dev->data->dev_conf.rxmode.offloads &=
1555 ~DEV_RX_OFFLOAD_JUMBO_FRAME;
1556 bp->flags &= ~BNXT_FLAG_JUMBO;
1559 eth_dev->data->dev_conf.rxmode.max_rx_pkt_len =
1560 new_mtu + ETHER_HDR_LEN + ETHER_CRC_LEN + VLAN_TAG_SIZE * 2;
1562 eth_dev->data->mtu = new_mtu;
1563 PMD_DRV_LOG(INFO, "New MTU is %d\n", eth_dev->data->mtu);
1565 for (i = 0; i < bp->nr_vnics; i++) {
1566 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
1568 vnic->mru = bp->eth_dev->data->mtu + ETHER_HDR_LEN +
1569 ETHER_CRC_LEN + VLAN_TAG_SIZE * 2;
1570 rc = bnxt_hwrm_vnic_cfg(bp, vnic);
1574 rc = bnxt_hwrm_vnic_plcmode_cfg(bp, vnic);
1583 bnxt_vlan_pvid_set_op(struct rte_eth_dev *dev, uint16_t pvid, int on)
1585 struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
1586 uint16_t vlan = bp->vlan;
1589 if (!BNXT_SINGLE_PF(bp) || BNXT_VF(bp)) {
1591 "PVID cannot be modified for this function\n");
1594 bp->vlan = on ? pvid : 0;
1596 rc = bnxt_hwrm_set_default_vlan(bp, 0, 0);
1603 bnxt_dev_led_on_op(struct rte_eth_dev *dev)
1605 struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
1607 return bnxt_hwrm_port_led_cfg(bp, true);
1611 bnxt_dev_led_off_op(struct rte_eth_dev *dev)
1613 struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
1615 return bnxt_hwrm_port_led_cfg(bp, false);
1619 bnxt_rx_queue_count_op(struct rte_eth_dev *dev, uint16_t rx_queue_id)
1621 uint32_t desc = 0, raw_cons = 0, cons;
1622 struct bnxt_cp_ring_info *cpr;
1623 struct bnxt_rx_queue *rxq;
1624 struct rx_pkt_cmpl *rxcmp;
1629 rxq = dev->data->rx_queues[rx_queue_id];
1633 while (raw_cons < rxq->nb_rx_desc) {
1634 cons = RING_CMP(cpr->cp_ring_struct, raw_cons);
1635 rxcmp = (struct rx_pkt_cmpl *)&cpr->cp_desc_ring[cons];
1637 if (!CMPL_VALID(rxcmp, valid))
1639 valid = FLIP_VALID(cons, cpr->cp_ring_struct->ring_mask, valid);
1640 cmp_type = CMP_TYPE(rxcmp);
1641 if (cmp_type == RX_TPA_END_CMPL_TYPE_RX_TPA_END) {
1642 cmp = (rte_le_to_cpu_32(
1643 ((struct rx_tpa_end_cmpl *)
1644 (rxcmp))->agg_bufs_v1) &
1645 RX_TPA_END_CMPL_AGG_BUFS_MASK) >>
1646 RX_TPA_END_CMPL_AGG_BUFS_SFT;
1648 } else if (cmp_type == 0x11) {
1650 cmp = (rxcmp->agg_bufs_v1 &
1651 RX_PKT_CMPL_AGG_BUFS_MASK) >>
1652 RX_PKT_CMPL_AGG_BUFS_SFT;
1657 raw_cons += cmp ? cmp : 2;
1664 bnxt_rx_descriptor_status_op(void *rx_queue, uint16_t offset)
1666 struct bnxt_rx_queue *rxq = (struct bnxt_rx_queue *)rx_queue;
1667 struct bnxt_rx_ring_info *rxr;
1668 struct bnxt_cp_ring_info *cpr;
1669 struct bnxt_sw_rx_bd *rx_buf;
1670 struct rx_pkt_cmpl *rxcmp;
1671 uint32_t cons, cp_cons;
1679 if (offset >= rxq->nb_rx_desc)
1682 cons = RING_CMP(cpr->cp_ring_struct, offset);
1683 cp_cons = cpr->cp_raw_cons;
1684 rxcmp = (struct rx_pkt_cmpl *)&cpr->cp_desc_ring[cons];
1686 if (cons > cp_cons) {
1687 if (CMPL_VALID(rxcmp, cpr->valid))
1688 return RTE_ETH_RX_DESC_DONE;
1690 if (CMPL_VALID(rxcmp, !cpr->valid))
1691 return RTE_ETH_RX_DESC_DONE;
1693 rx_buf = &rxr->rx_buf_ring[cons];
1694 if (rx_buf->mbuf == NULL)
1695 return RTE_ETH_RX_DESC_UNAVAIL;
1698 return RTE_ETH_RX_DESC_AVAIL;
1702 bnxt_tx_descriptor_status_op(void *tx_queue, uint16_t offset)
1704 struct bnxt_tx_queue *txq = (struct bnxt_tx_queue *)tx_queue;
1705 struct bnxt_tx_ring_info *txr;
1706 struct bnxt_cp_ring_info *cpr;
1707 struct bnxt_sw_tx_bd *tx_buf;
1708 struct tx_pkt_cmpl *txcmp;
1709 uint32_t cons, cp_cons;
1717 if (offset >= txq->nb_tx_desc)
1720 cons = RING_CMP(cpr->cp_ring_struct, offset);
1721 txcmp = (struct tx_pkt_cmpl *)&cpr->cp_desc_ring[cons];
1722 cp_cons = cpr->cp_raw_cons;
1724 if (cons > cp_cons) {
1725 if (CMPL_VALID(txcmp, cpr->valid))
1726 return RTE_ETH_TX_DESC_UNAVAIL;
1728 if (CMPL_VALID(txcmp, !cpr->valid))
1729 return RTE_ETH_TX_DESC_UNAVAIL;
1731 tx_buf = &txr->tx_buf_ring[cons];
1732 if (tx_buf->mbuf == NULL)
1733 return RTE_ETH_TX_DESC_DONE;
1735 return RTE_ETH_TX_DESC_FULL;
1738 static struct bnxt_filter_info *
1739 bnxt_match_and_validate_ether_filter(struct bnxt *bp,
1740 struct rte_eth_ethertype_filter *efilter,
1741 struct bnxt_vnic_info *vnic0,
1742 struct bnxt_vnic_info *vnic,
1745 struct bnxt_filter_info *mfilter = NULL;
1749 if (efilter->ether_type == ETHER_TYPE_IPv4 ||
1750 efilter->ether_type == ETHER_TYPE_IPv6) {
1751 PMD_DRV_LOG(ERR, "invalid ether_type(0x%04x) in"
1752 " ethertype filter.", efilter->ether_type);
1756 if (efilter->queue >= bp->rx_nr_rings) {
1757 PMD_DRV_LOG(ERR, "Invalid queue %d\n", efilter->queue);
1762 vnic0 = STAILQ_FIRST(&bp->ff_pool[0]);
1763 vnic = STAILQ_FIRST(&bp->ff_pool[efilter->queue]);
1765 PMD_DRV_LOG(ERR, "Invalid queue %d\n", efilter->queue);
1770 if (efilter->flags & RTE_ETHTYPE_FLAGS_DROP) {
1771 STAILQ_FOREACH(mfilter, &vnic0->filter, next) {
1772 if ((!memcmp(efilter->mac_addr.addr_bytes,
1773 mfilter->l2_addr, ETHER_ADDR_LEN) &&
1775 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_DROP &&
1776 mfilter->ethertype == efilter->ether_type)) {
1782 STAILQ_FOREACH(mfilter, &vnic->filter, next)
1783 if ((!memcmp(efilter->mac_addr.addr_bytes,
1784 mfilter->l2_addr, ETHER_ADDR_LEN) &&
1785 mfilter->ethertype == efilter->ether_type &&
1787 HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_PATH_RX)) {
1801 bnxt_ethertype_filter(struct rte_eth_dev *dev,
1802 enum rte_filter_op filter_op,
1805 struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
1806 struct rte_eth_ethertype_filter *efilter =
1807 (struct rte_eth_ethertype_filter *)arg;
1808 struct bnxt_filter_info *bfilter, *filter1;
1809 struct bnxt_vnic_info *vnic, *vnic0;
1812 if (filter_op == RTE_ETH_FILTER_NOP)
1816 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
1821 vnic0 = STAILQ_FIRST(&bp->ff_pool[0]);
1822 vnic = STAILQ_FIRST(&bp->ff_pool[efilter->queue]);
1824 switch (filter_op) {
1825 case RTE_ETH_FILTER_ADD:
1826 bnxt_match_and_validate_ether_filter(bp, efilter,
1831 bfilter = bnxt_get_unused_filter(bp);
1832 if (bfilter == NULL) {
1834 "Not enough resources for a new filter.\n");
1837 bfilter->filter_type = HWRM_CFA_NTUPLE_FILTER;
1838 memcpy(bfilter->l2_addr, efilter->mac_addr.addr_bytes,
1840 memcpy(bfilter->dst_macaddr, efilter->mac_addr.addr_bytes,
1842 bfilter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_MACADDR;
1843 bfilter->ethertype = efilter->ether_type;
1844 bfilter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
1846 filter1 = bnxt_get_l2_filter(bp, bfilter, vnic0);
1847 if (filter1 == NULL) {
1852 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID;
1853 bfilter->fw_l2_filter_id = filter1->fw_l2_filter_id;
1855 bfilter->dst_id = vnic->fw_vnic_id;
1857 if (efilter->flags & RTE_ETHTYPE_FLAGS_DROP) {
1859 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_DROP;
1862 ret = bnxt_hwrm_set_ntuple_filter(bp, bfilter->dst_id, bfilter);
1865 STAILQ_INSERT_TAIL(&vnic->filter, bfilter, next);
1867 case RTE_ETH_FILTER_DELETE:
1868 filter1 = bnxt_match_and_validate_ether_filter(bp, efilter,
1870 if (ret == -EEXIST) {
1871 ret = bnxt_hwrm_clear_ntuple_filter(bp, filter1);
1873 STAILQ_REMOVE(&vnic->filter, filter1, bnxt_filter_info,
1875 bnxt_free_filter(bp, filter1);
1876 } else if (ret == 0) {
1877 PMD_DRV_LOG(ERR, "No matching filter found\n");
1881 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
1887 bnxt_free_filter(bp, bfilter);
1893 parse_ntuple_filter(struct bnxt *bp,
1894 struct rte_eth_ntuple_filter *nfilter,
1895 struct bnxt_filter_info *bfilter)
1899 if (nfilter->queue >= bp->rx_nr_rings) {
1900 PMD_DRV_LOG(ERR, "Invalid queue %d\n", nfilter->queue);
1904 switch (nfilter->dst_port_mask) {
1906 bfilter->dst_port_mask = -1;
1907 bfilter->dst_port = nfilter->dst_port;
1908 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT |
1909 NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
1912 PMD_DRV_LOG(ERR, "invalid dst_port mask.");
1916 bfilter->ip_addr_type = NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4;
1917 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
1919 switch (nfilter->proto_mask) {
1921 if (nfilter->proto == 17) /* IPPROTO_UDP */
1922 bfilter->ip_protocol = 17;
1923 else if (nfilter->proto == 6) /* IPPROTO_TCP */
1924 bfilter->ip_protocol = 6;
1927 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
1930 PMD_DRV_LOG(ERR, "invalid protocol mask.");
1934 switch (nfilter->dst_ip_mask) {
1936 bfilter->dst_ipaddr_mask[0] = -1;
1937 bfilter->dst_ipaddr[0] = nfilter->dst_ip;
1938 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR |
1939 NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
1942 PMD_DRV_LOG(ERR, "invalid dst_ip mask.");
1946 switch (nfilter->src_ip_mask) {
1948 bfilter->src_ipaddr_mask[0] = -1;
1949 bfilter->src_ipaddr[0] = nfilter->src_ip;
1950 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR |
1951 NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
1954 PMD_DRV_LOG(ERR, "invalid src_ip mask.");
1958 switch (nfilter->src_port_mask) {
1960 bfilter->src_port_mask = -1;
1961 bfilter->src_port = nfilter->src_port;
1962 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT |
1963 NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
1966 PMD_DRV_LOG(ERR, "invalid src_port mask.");
1971 //nfilter->priority = (uint8_t)filter->priority;
1973 bfilter->enables = en;
1977 static struct bnxt_filter_info*
1978 bnxt_match_ntuple_filter(struct bnxt *bp,
1979 struct bnxt_filter_info *bfilter,
1980 struct bnxt_vnic_info **mvnic)
1982 struct bnxt_filter_info *mfilter = NULL;
1985 for (i = bp->nr_vnics - 1; i >= 0; i--) {
1986 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
1987 STAILQ_FOREACH(mfilter, &vnic->filter, next) {
1988 if (bfilter->src_ipaddr[0] == mfilter->src_ipaddr[0] &&
1989 bfilter->src_ipaddr_mask[0] ==
1990 mfilter->src_ipaddr_mask[0] &&
1991 bfilter->src_port == mfilter->src_port &&
1992 bfilter->src_port_mask == mfilter->src_port_mask &&
1993 bfilter->dst_ipaddr[0] == mfilter->dst_ipaddr[0] &&
1994 bfilter->dst_ipaddr_mask[0] ==
1995 mfilter->dst_ipaddr_mask[0] &&
1996 bfilter->dst_port == mfilter->dst_port &&
1997 bfilter->dst_port_mask == mfilter->dst_port_mask &&
1998 bfilter->flags == mfilter->flags &&
1999 bfilter->enables == mfilter->enables) {
2010 bnxt_cfg_ntuple_filter(struct bnxt *bp,
2011 struct rte_eth_ntuple_filter *nfilter,
2012 enum rte_filter_op filter_op)
2014 struct bnxt_filter_info *bfilter, *mfilter, *filter1;
2015 struct bnxt_vnic_info *vnic, *vnic0, *mvnic;
2018 if (nfilter->flags != RTE_5TUPLE_FLAGS) {
2019 PMD_DRV_LOG(ERR, "only 5tuple is supported.");
2023 if (nfilter->flags & RTE_NTUPLE_FLAGS_TCP_FLAG) {
2024 PMD_DRV_LOG(ERR, "Ntuple filter: TCP flags not supported\n");
2028 bfilter = bnxt_get_unused_filter(bp);
2029 if (bfilter == NULL) {
2031 "Not enough resources for a new filter.\n");
2034 ret = parse_ntuple_filter(bp, nfilter, bfilter);
2038 vnic = STAILQ_FIRST(&bp->ff_pool[nfilter->queue]);
2039 vnic0 = STAILQ_FIRST(&bp->ff_pool[0]);
2040 filter1 = STAILQ_FIRST(&vnic0->filter);
2041 if (filter1 == NULL) {
2046 bfilter->dst_id = vnic->fw_vnic_id;
2047 bfilter->fw_l2_filter_id = filter1->fw_l2_filter_id;
2049 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID;
2050 bfilter->ethertype = 0x800;
2051 bfilter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2053 mfilter = bnxt_match_ntuple_filter(bp, bfilter, &mvnic);
2055 if (mfilter != NULL && filter_op == RTE_ETH_FILTER_ADD &&
2056 bfilter->dst_id == mfilter->dst_id) {
2057 PMD_DRV_LOG(ERR, "filter exists.\n");
2060 } else if (mfilter != NULL && filter_op == RTE_ETH_FILTER_ADD &&
2061 bfilter->dst_id != mfilter->dst_id) {
2062 mfilter->dst_id = vnic->fw_vnic_id;
2063 ret = bnxt_hwrm_set_ntuple_filter(bp, mfilter->dst_id, mfilter);
2064 STAILQ_REMOVE(&mvnic->filter, mfilter, bnxt_filter_info, next);
2065 STAILQ_INSERT_TAIL(&vnic->filter, mfilter, next);
2066 PMD_DRV_LOG(ERR, "filter with matching pattern exists.\n");
2067 PMD_DRV_LOG(ERR, " Updated it to the new destination queue\n");
2070 if (mfilter == NULL && filter_op == RTE_ETH_FILTER_DELETE) {
2071 PMD_DRV_LOG(ERR, "filter doesn't exist.");
2076 if (filter_op == RTE_ETH_FILTER_ADD) {
2077 bfilter->filter_type = HWRM_CFA_NTUPLE_FILTER;
2078 ret = bnxt_hwrm_set_ntuple_filter(bp, bfilter->dst_id, bfilter);
2081 STAILQ_INSERT_TAIL(&vnic->filter, bfilter, next);
2083 if (mfilter == NULL) {
2084 /* This should not happen. But for Coverity! */
2088 ret = bnxt_hwrm_clear_ntuple_filter(bp, mfilter);
2090 STAILQ_REMOVE(&vnic->filter, mfilter, bnxt_filter_info, next);
2091 bnxt_free_filter(bp, mfilter);
2092 mfilter->fw_l2_filter_id = -1;
2093 bnxt_free_filter(bp, bfilter);
2094 bfilter->fw_l2_filter_id = -1;
2099 bfilter->fw_l2_filter_id = -1;
2100 bnxt_free_filter(bp, bfilter);
2105 bnxt_ntuple_filter(struct rte_eth_dev *dev,
2106 enum rte_filter_op filter_op,
2109 struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
2112 if (filter_op == RTE_ETH_FILTER_NOP)
2116 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
2121 switch (filter_op) {
2122 case RTE_ETH_FILTER_ADD:
2123 ret = bnxt_cfg_ntuple_filter(bp,
2124 (struct rte_eth_ntuple_filter *)arg,
2127 case RTE_ETH_FILTER_DELETE:
2128 ret = bnxt_cfg_ntuple_filter(bp,
2129 (struct rte_eth_ntuple_filter *)arg,
2133 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
2141 bnxt_parse_fdir_filter(struct bnxt *bp,
2142 struct rte_eth_fdir_filter *fdir,
2143 struct bnxt_filter_info *filter)
2145 enum rte_fdir_mode fdir_mode =
2146 bp->eth_dev->data->dev_conf.fdir_conf.mode;
2147 struct bnxt_vnic_info *vnic0, *vnic;
2148 struct bnxt_filter_info *filter1;
2152 if (fdir_mode == RTE_FDIR_MODE_PERFECT_TUNNEL)
2155 filter->l2_ovlan = fdir->input.flow_ext.vlan_tci;
2156 en |= EM_FLOW_ALLOC_INPUT_EN_OVLAN_VID;
2158 switch (fdir->input.flow_type) {
2159 case RTE_ETH_FLOW_IPV4:
2160 case RTE_ETH_FLOW_NONFRAG_IPV4_OTHER:
2162 filter->src_ipaddr[0] = fdir->input.flow.ip4_flow.src_ip;
2163 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
2164 filter->dst_ipaddr[0] = fdir->input.flow.ip4_flow.dst_ip;
2165 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
2166 filter->ip_protocol = fdir->input.flow.ip4_flow.proto;
2167 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2168 filter->ip_addr_type =
2169 NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4;
2170 filter->src_ipaddr_mask[0] = 0xffffffff;
2171 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2172 filter->dst_ipaddr_mask[0] = 0xffffffff;
2173 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2174 filter->ethertype = 0x800;
2175 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2177 case RTE_ETH_FLOW_NONFRAG_IPV4_TCP:
2178 filter->src_port = fdir->input.flow.tcp4_flow.src_port;
2179 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT;
2180 filter->dst_port = fdir->input.flow.tcp4_flow.dst_port;
2181 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT;
2182 filter->dst_port_mask = 0xffff;
2183 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
2184 filter->src_port_mask = 0xffff;
2185 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
2186 filter->src_ipaddr[0] = fdir->input.flow.tcp4_flow.ip.src_ip;
2187 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
2188 filter->dst_ipaddr[0] = fdir->input.flow.tcp4_flow.ip.dst_ip;
2189 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
2190 filter->ip_protocol = 6;
2191 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2192 filter->ip_addr_type =
2193 NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4;
2194 filter->src_ipaddr_mask[0] = 0xffffffff;
2195 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2196 filter->dst_ipaddr_mask[0] = 0xffffffff;
2197 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2198 filter->ethertype = 0x800;
2199 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2201 case RTE_ETH_FLOW_NONFRAG_IPV4_UDP:
2202 filter->src_port = fdir->input.flow.udp4_flow.src_port;
2203 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT;
2204 filter->dst_port = fdir->input.flow.udp4_flow.dst_port;
2205 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT;
2206 filter->dst_port_mask = 0xffff;
2207 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
2208 filter->src_port_mask = 0xffff;
2209 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
2210 filter->src_ipaddr[0] = fdir->input.flow.udp4_flow.ip.src_ip;
2211 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
2212 filter->dst_ipaddr[0] = fdir->input.flow.udp4_flow.ip.dst_ip;
2213 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
2214 filter->ip_protocol = 17;
2215 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2216 filter->ip_addr_type =
2217 NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4;
2218 filter->src_ipaddr_mask[0] = 0xffffffff;
2219 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2220 filter->dst_ipaddr_mask[0] = 0xffffffff;
2221 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2222 filter->ethertype = 0x800;
2223 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2225 case RTE_ETH_FLOW_IPV6:
2226 case RTE_ETH_FLOW_NONFRAG_IPV6_OTHER:
2228 filter->ip_addr_type =
2229 NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV6;
2230 filter->ip_protocol = fdir->input.flow.ipv6_flow.proto;
2231 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2232 rte_memcpy(filter->src_ipaddr,
2233 fdir->input.flow.ipv6_flow.src_ip, 16);
2234 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
2235 rte_memcpy(filter->dst_ipaddr,
2236 fdir->input.flow.ipv6_flow.dst_ip, 16);
2237 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
2238 memset(filter->dst_ipaddr_mask, 0xff, 16);
2239 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2240 memset(filter->src_ipaddr_mask, 0xff, 16);
2241 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2242 filter->ethertype = 0x86dd;
2243 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2245 case RTE_ETH_FLOW_NONFRAG_IPV6_TCP:
2246 filter->src_port = fdir->input.flow.tcp6_flow.src_port;
2247 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT;
2248 filter->dst_port = fdir->input.flow.tcp6_flow.dst_port;
2249 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT;
2250 filter->dst_port_mask = 0xffff;
2251 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
2252 filter->src_port_mask = 0xffff;
2253 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
2254 filter->ip_addr_type =
2255 NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV6;
2256 filter->ip_protocol = fdir->input.flow.tcp6_flow.ip.proto;
2257 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2258 rte_memcpy(filter->src_ipaddr,
2259 fdir->input.flow.tcp6_flow.ip.src_ip, 16);
2260 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
2261 rte_memcpy(filter->dst_ipaddr,
2262 fdir->input.flow.tcp6_flow.ip.dst_ip, 16);
2263 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
2264 memset(filter->dst_ipaddr_mask, 0xff, 16);
2265 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2266 memset(filter->src_ipaddr_mask, 0xff, 16);
2267 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2268 filter->ethertype = 0x86dd;
2269 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2271 case RTE_ETH_FLOW_NONFRAG_IPV6_UDP:
2272 filter->src_port = fdir->input.flow.udp6_flow.src_port;
2273 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT;
2274 filter->dst_port = fdir->input.flow.udp6_flow.dst_port;
2275 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT;
2276 filter->dst_port_mask = 0xffff;
2277 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
2278 filter->src_port_mask = 0xffff;
2279 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
2280 filter->ip_addr_type =
2281 NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV6;
2282 filter->ip_protocol = fdir->input.flow.udp6_flow.ip.proto;
2283 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2284 rte_memcpy(filter->src_ipaddr,
2285 fdir->input.flow.udp6_flow.ip.src_ip, 16);
2286 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
2287 rte_memcpy(filter->dst_ipaddr,
2288 fdir->input.flow.udp6_flow.ip.dst_ip, 16);
2289 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
2290 memset(filter->dst_ipaddr_mask, 0xff, 16);
2291 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2292 memset(filter->src_ipaddr_mask, 0xff, 16);
2293 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2294 filter->ethertype = 0x86dd;
2295 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2297 case RTE_ETH_FLOW_L2_PAYLOAD:
2298 filter->ethertype = fdir->input.flow.l2_flow.ether_type;
2299 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2301 case RTE_ETH_FLOW_VXLAN:
2302 if (fdir->action.behavior == RTE_ETH_FDIR_REJECT)
2304 filter->vni = fdir->input.flow.tunnel_flow.tunnel_id;
2305 filter->tunnel_type =
2306 CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN;
2307 en |= HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_TUNNEL_TYPE;
2309 case RTE_ETH_FLOW_NVGRE:
2310 if (fdir->action.behavior == RTE_ETH_FDIR_REJECT)
2312 filter->vni = fdir->input.flow.tunnel_flow.tunnel_id;
2313 filter->tunnel_type =
2314 CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_NVGRE;
2315 en |= HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_TUNNEL_TYPE;
2317 case RTE_ETH_FLOW_UNKNOWN:
2318 case RTE_ETH_FLOW_RAW:
2319 case RTE_ETH_FLOW_FRAG_IPV4:
2320 case RTE_ETH_FLOW_NONFRAG_IPV4_SCTP:
2321 case RTE_ETH_FLOW_FRAG_IPV6:
2322 case RTE_ETH_FLOW_NONFRAG_IPV6_SCTP:
2323 case RTE_ETH_FLOW_IPV6_EX:
2324 case RTE_ETH_FLOW_IPV6_TCP_EX:
2325 case RTE_ETH_FLOW_IPV6_UDP_EX:
2326 case RTE_ETH_FLOW_GENEVE:
2332 vnic0 = STAILQ_FIRST(&bp->ff_pool[0]);
2333 vnic = STAILQ_FIRST(&bp->ff_pool[fdir->action.rx_queue]);
2335 PMD_DRV_LOG(ERR, "Invalid queue %d\n", fdir->action.rx_queue);
2340 if (fdir_mode == RTE_FDIR_MODE_PERFECT_MAC_VLAN) {
2341 rte_memcpy(filter->dst_macaddr,
2342 fdir->input.flow.mac_vlan_flow.mac_addr.addr_bytes, 6);
2343 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_MACADDR;
2346 if (fdir->action.behavior == RTE_ETH_FDIR_REJECT) {
2347 filter->flags = HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_DROP;
2348 filter1 = STAILQ_FIRST(&vnic0->filter);
2349 //filter1 = bnxt_get_l2_filter(bp, filter, vnic0);
2351 filter->dst_id = vnic->fw_vnic_id;
2352 for (i = 0; i < ETHER_ADDR_LEN; i++)
2353 if (filter->dst_macaddr[i] == 0x00)
2354 filter1 = STAILQ_FIRST(&vnic0->filter);
2356 filter1 = bnxt_get_l2_filter(bp, filter, vnic);
2359 if (filter1 == NULL)
2362 en |= HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID;
2363 filter->fw_l2_filter_id = filter1->fw_l2_filter_id;
2365 filter->enables = en;
2370 static struct bnxt_filter_info *
2371 bnxt_match_fdir(struct bnxt *bp, struct bnxt_filter_info *nf,
2372 struct bnxt_vnic_info **mvnic)
2374 struct bnxt_filter_info *mf = NULL;
2377 for (i = bp->nr_vnics - 1; i >= 0; i--) {
2378 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
2380 STAILQ_FOREACH(mf, &vnic->filter, next) {
2381 if (mf->filter_type == nf->filter_type &&
2382 mf->flags == nf->flags &&
2383 mf->src_port == nf->src_port &&
2384 mf->src_port_mask == nf->src_port_mask &&
2385 mf->dst_port == nf->dst_port &&
2386 mf->dst_port_mask == nf->dst_port_mask &&
2387 mf->ip_protocol == nf->ip_protocol &&
2388 mf->ip_addr_type == nf->ip_addr_type &&
2389 mf->ethertype == nf->ethertype &&
2390 mf->vni == nf->vni &&
2391 mf->tunnel_type == nf->tunnel_type &&
2392 mf->l2_ovlan == nf->l2_ovlan &&
2393 mf->l2_ovlan_mask == nf->l2_ovlan_mask &&
2394 mf->l2_ivlan == nf->l2_ivlan &&
2395 mf->l2_ivlan_mask == nf->l2_ivlan_mask &&
2396 !memcmp(mf->l2_addr, nf->l2_addr, ETHER_ADDR_LEN) &&
2397 !memcmp(mf->l2_addr_mask, nf->l2_addr_mask,
2399 !memcmp(mf->src_macaddr, nf->src_macaddr,
2401 !memcmp(mf->dst_macaddr, nf->dst_macaddr,
2403 !memcmp(mf->src_ipaddr, nf->src_ipaddr,
2404 sizeof(nf->src_ipaddr)) &&
2405 !memcmp(mf->src_ipaddr_mask, nf->src_ipaddr_mask,
2406 sizeof(nf->src_ipaddr_mask)) &&
2407 !memcmp(mf->dst_ipaddr, nf->dst_ipaddr,
2408 sizeof(nf->dst_ipaddr)) &&
2409 !memcmp(mf->dst_ipaddr_mask, nf->dst_ipaddr_mask,
2410 sizeof(nf->dst_ipaddr_mask))) {
2421 bnxt_fdir_filter(struct rte_eth_dev *dev,
2422 enum rte_filter_op filter_op,
2425 struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
2426 struct rte_eth_fdir_filter *fdir = (struct rte_eth_fdir_filter *)arg;
2427 struct bnxt_filter_info *filter, *match;
2428 struct bnxt_vnic_info *vnic, *mvnic;
2431 if (filter_op == RTE_ETH_FILTER_NOP)
2434 if (arg == NULL && filter_op != RTE_ETH_FILTER_FLUSH)
2437 switch (filter_op) {
2438 case RTE_ETH_FILTER_ADD:
2439 case RTE_ETH_FILTER_DELETE:
2441 filter = bnxt_get_unused_filter(bp);
2442 if (filter == NULL) {
2444 "Not enough resources for a new flow.\n");
2448 ret = bnxt_parse_fdir_filter(bp, fdir, filter);
2451 filter->filter_type = HWRM_CFA_NTUPLE_FILTER;
2453 if (fdir->action.behavior == RTE_ETH_FDIR_REJECT)
2454 vnic = STAILQ_FIRST(&bp->ff_pool[0]);
2456 vnic = STAILQ_FIRST(&bp->ff_pool[fdir->action.rx_queue]);
2458 match = bnxt_match_fdir(bp, filter, &mvnic);
2459 if (match != NULL && filter_op == RTE_ETH_FILTER_ADD) {
2460 if (match->dst_id == vnic->fw_vnic_id) {
2461 PMD_DRV_LOG(ERR, "Flow already exists.\n");
2465 match->dst_id = vnic->fw_vnic_id;
2466 ret = bnxt_hwrm_set_ntuple_filter(bp,
2469 STAILQ_REMOVE(&mvnic->filter, match,
2470 bnxt_filter_info, next);
2471 STAILQ_INSERT_TAIL(&vnic->filter, match, next);
2473 "Filter with matching pattern exist\n");
2475 "Updated it to new destination q\n");
2479 if (match == NULL && filter_op == RTE_ETH_FILTER_DELETE) {
2480 PMD_DRV_LOG(ERR, "Flow does not exist.\n");
2485 if (filter_op == RTE_ETH_FILTER_ADD) {
2486 ret = bnxt_hwrm_set_ntuple_filter(bp,
2491 STAILQ_INSERT_TAIL(&vnic->filter, filter, next);
2493 ret = bnxt_hwrm_clear_ntuple_filter(bp, match);
2494 STAILQ_REMOVE(&vnic->filter, match,
2495 bnxt_filter_info, next);
2496 bnxt_free_filter(bp, match);
2497 filter->fw_l2_filter_id = -1;
2498 bnxt_free_filter(bp, filter);
2501 case RTE_ETH_FILTER_FLUSH:
2502 for (i = bp->nr_vnics - 1; i >= 0; i--) {
2503 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
2505 STAILQ_FOREACH(filter, &vnic->filter, next) {
2506 if (filter->filter_type ==
2507 HWRM_CFA_NTUPLE_FILTER) {
2509 bnxt_hwrm_clear_ntuple_filter(bp,
2511 STAILQ_REMOVE(&vnic->filter, filter,
2512 bnxt_filter_info, next);
2517 case RTE_ETH_FILTER_UPDATE:
2518 case RTE_ETH_FILTER_STATS:
2519 case RTE_ETH_FILTER_INFO:
2520 PMD_DRV_LOG(ERR, "operation %u not implemented", filter_op);
2523 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
2530 filter->fw_l2_filter_id = -1;
2531 bnxt_free_filter(bp, filter);
2536 bnxt_filter_ctrl_op(struct rte_eth_dev *dev __rte_unused,
2537 enum rte_filter_type filter_type,
2538 enum rte_filter_op filter_op, void *arg)
2542 switch (filter_type) {
2543 case RTE_ETH_FILTER_TUNNEL:
2545 "filter type: %d: To be implemented\n", filter_type);
2547 case RTE_ETH_FILTER_FDIR:
2548 ret = bnxt_fdir_filter(dev, filter_op, arg);
2550 case RTE_ETH_FILTER_NTUPLE:
2551 ret = bnxt_ntuple_filter(dev, filter_op, arg);
2553 case RTE_ETH_FILTER_ETHERTYPE:
2554 ret = bnxt_ethertype_filter(dev, filter_op, arg);
2556 case RTE_ETH_FILTER_GENERIC:
2557 if (filter_op != RTE_ETH_FILTER_GET)
2559 *(const void **)arg = &bnxt_flow_ops;
2563 "Filter type (%d) not supported", filter_type);
2570 static const uint32_t *
2571 bnxt_dev_supported_ptypes_get_op(struct rte_eth_dev *dev)
2573 static const uint32_t ptypes[] = {
2574 RTE_PTYPE_L2_ETHER_VLAN,
2575 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN,
2576 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN,
2580 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN,
2581 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN,
2582 RTE_PTYPE_INNER_L4_ICMP,
2583 RTE_PTYPE_INNER_L4_TCP,
2584 RTE_PTYPE_INNER_L4_UDP,
2588 if (dev->rx_pkt_burst == bnxt_recv_pkts)
2593 static int bnxt_map_regs(struct bnxt *bp, uint32_t *reg_arr, int count,
2596 uint32_t reg_base = *reg_arr & 0xfffff000;
2600 for (i = 0; i < count; i++) {
2601 if ((reg_arr[i] & 0xfffff000) != reg_base)
2604 win_off = BNXT_GRCPF_REG_WINDOW_BASE_OUT + (reg_win - 1) * 4;
2605 rte_cpu_to_le_32(rte_write32(reg_base, (uint8_t *)bp->bar0 + win_off));
2609 static int bnxt_map_ptp_regs(struct bnxt *bp)
2611 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
2615 reg_arr = ptp->rx_regs;
2616 rc = bnxt_map_regs(bp, reg_arr, BNXT_PTP_RX_REGS, 5);
2620 reg_arr = ptp->tx_regs;
2621 rc = bnxt_map_regs(bp, reg_arr, BNXT_PTP_TX_REGS, 6);
2625 for (i = 0; i < BNXT_PTP_RX_REGS; i++)
2626 ptp->rx_mapped_regs[i] = 0x5000 + (ptp->rx_regs[i] & 0xfff);
2628 for (i = 0; i < BNXT_PTP_TX_REGS; i++)
2629 ptp->tx_mapped_regs[i] = 0x6000 + (ptp->tx_regs[i] & 0xfff);
2634 static void bnxt_unmap_ptp_regs(struct bnxt *bp)
2636 rte_cpu_to_le_32(rte_write32(0, (uint8_t *)bp->bar0 +
2637 BNXT_GRCPF_REG_WINDOW_BASE_OUT + 16));
2638 rte_cpu_to_le_32(rte_write32(0, (uint8_t *)bp->bar0 +
2639 BNXT_GRCPF_REG_WINDOW_BASE_OUT + 20));
2642 static uint64_t bnxt_cc_read(struct bnxt *bp)
2646 ns = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
2647 BNXT_GRCPF_REG_SYNC_TIME));
2648 ns |= (uint64_t)(rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
2649 BNXT_GRCPF_REG_SYNC_TIME + 4))) << 32;
2653 static int bnxt_get_tx_ts(struct bnxt *bp, uint64_t *ts)
2655 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
2658 fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
2659 ptp->tx_mapped_regs[BNXT_PTP_TX_FIFO]));
2660 if (fifo & BNXT_PTP_TX_FIFO_EMPTY)
2663 fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
2664 ptp->tx_mapped_regs[BNXT_PTP_TX_FIFO]));
2665 *ts = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
2666 ptp->tx_mapped_regs[BNXT_PTP_TX_TS_L]));
2667 *ts |= (uint64_t)rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
2668 ptp->tx_mapped_regs[BNXT_PTP_TX_TS_H])) << 32;
2673 static int bnxt_get_rx_ts(struct bnxt *bp, uint64_t *ts)
2675 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
2676 struct bnxt_pf_info *pf = &bp->pf;
2683 fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
2684 ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO]));
2685 if (!(fifo & BNXT_PTP_RX_FIFO_PENDING))
2688 port_id = pf->port_id;
2689 rte_cpu_to_le_32(rte_write32(1 << port_id, (uint8_t *)bp->bar0 +
2690 ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO_ADV]));
2692 fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
2693 ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO]));
2694 if (fifo & BNXT_PTP_RX_FIFO_PENDING) {
2695 /* bnxt_clr_rx_ts(bp); TBD */
2699 *ts = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
2700 ptp->rx_mapped_regs[BNXT_PTP_RX_TS_L]));
2701 *ts |= (uint64_t)rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
2702 ptp->rx_mapped_regs[BNXT_PTP_RX_TS_H])) << 32;
2708 bnxt_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
2711 struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
2712 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
2717 ns = rte_timespec_to_ns(ts);
2718 /* Set the timecounters to a new value. */
2725 bnxt_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
2727 uint64_t ns, systime_cycles;
2728 struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
2729 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
2734 systime_cycles = bnxt_cc_read(bp);
2735 ns = rte_timecounter_update(&ptp->tc, systime_cycles);
2736 *ts = rte_ns_to_timespec(ns);
2741 bnxt_timesync_enable(struct rte_eth_dev *dev)
2743 struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
2744 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
2751 ptp->tx_tstamp_en = 1;
2752 ptp->rxctl = BNXT_PTP_MSG_EVENTS;
2754 if (!bnxt_hwrm_ptp_cfg(bp))
2755 bnxt_map_ptp_regs(bp);
2757 memset(&ptp->tc, 0, sizeof(struct rte_timecounter));
2758 memset(&ptp->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
2759 memset(&ptp->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
2761 ptp->tc.cc_mask = BNXT_CYCLECOUNTER_MASK;
2762 ptp->tc.cc_shift = shift;
2763 ptp->tc.nsec_mask = (1ULL << shift) - 1;
2765 ptp->rx_tstamp_tc.cc_mask = BNXT_CYCLECOUNTER_MASK;
2766 ptp->rx_tstamp_tc.cc_shift = shift;
2767 ptp->rx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
2769 ptp->tx_tstamp_tc.cc_mask = BNXT_CYCLECOUNTER_MASK;
2770 ptp->tx_tstamp_tc.cc_shift = shift;
2771 ptp->tx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
2777 bnxt_timesync_disable(struct rte_eth_dev *dev)
2779 struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
2780 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
2786 ptp->tx_tstamp_en = 0;
2789 bnxt_hwrm_ptp_cfg(bp);
2791 bnxt_unmap_ptp_regs(bp);
2797 bnxt_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
2798 struct timespec *timestamp,
2799 uint32_t flags __rte_unused)
2801 struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
2802 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
2803 uint64_t rx_tstamp_cycles = 0;
2809 bnxt_get_rx_ts(bp, &rx_tstamp_cycles);
2810 ns = rte_timecounter_update(&ptp->rx_tstamp_tc, rx_tstamp_cycles);
2811 *timestamp = rte_ns_to_timespec(ns);
2816 bnxt_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
2817 struct timespec *timestamp)
2819 struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
2820 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
2821 uint64_t tx_tstamp_cycles = 0;
2827 bnxt_get_tx_ts(bp, &tx_tstamp_cycles);
2828 ns = rte_timecounter_update(&ptp->tx_tstamp_tc, tx_tstamp_cycles);
2829 *timestamp = rte_ns_to_timespec(ns);
2835 bnxt_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
2837 struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
2838 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
2843 ptp->tc.nsec += delta;
2849 bnxt_get_eeprom_length_op(struct rte_eth_dev *dev)
2851 struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
2853 uint32_t dir_entries;
2854 uint32_t entry_length;
2856 PMD_DRV_LOG(INFO, "%04x:%02x:%02x:%02x\n",
2857 bp->pdev->addr.domain, bp->pdev->addr.bus,
2858 bp->pdev->addr.devid, bp->pdev->addr.function);
2860 rc = bnxt_hwrm_nvm_get_dir_info(bp, &dir_entries, &entry_length);
2864 return dir_entries * entry_length;
2868 bnxt_get_eeprom_op(struct rte_eth_dev *dev,
2869 struct rte_dev_eeprom_info *in_eeprom)
2871 struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
2875 PMD_DRV_LOG(INFO, "%04x:%02x:%02x:%02x in_eeprom->offset = %d "
2876 "len = %d\n", bp->pdev->addr.domain,
2877 bp->pdev->addr.bus, bp->pdev->addr.devid,
2878 bp->pdev->addr.function, in_eeprom->offset, in_eeprom->length);
2880 if (in_eeprom->offset == 0) /* special offset value to get directory */
2881 return bnxt_get_nvram_directory(bp, in_eeprom->length,
2884 index = in_eeprom->offset >> 24;
2885 offset = in_eeprom->offset & 0xffffff;
2888 return bnxt_hwrm_get_nvram_item(bp, index - 1, offset,
2889 in_eeprom->length, in_eeprom->data);
2894 static bool bnxt_dir_type_is_ape_bin_format(uint16_t dir_type)
2897 case BNX_DIR_TYPE_CHIMP_PATCH:
2898 case BNX_DIR_TYPE_BOOTCODE:
2899 case BNX_DIR_TYPE_BOOTCODE_2:
2900 case BNX_DIR_TYPE_APE_FW:
2901 case BNX_DIR_TYPE_APE_PATCH:
2902 case BNX_DIR_TYPE_KONG_FW:
2903 case BNX_DIR_TYPE_KONG_PATCH:
2904 case BNX_DIR_TYPE_BONO_FW:
2905 case BNX_DIR_TYPE_BONO_PATCH:
2913 static bool bnxt_dir_type_is_other_exec_format(uint16_t dir_type)
2916 case BNX_DIR_TYPE_AVS:
2917 case BNX_DIR_TYPE_EXP_ROM_MBA:
2918 case BNX_DIR_TYPE_PCIE:
2919 case BNX_DIR_TYPE_TSCF_UCODE:
2920 case BNX_DIR_TYPE_EXT_PHY:
2921 case BNX_DIR_TYPE_CCM:
2922 case BNX_DIR_TYPE_ISCSI_BOOT:
2923 case BNX_DIR_TYPE_ISCSI_BOOT_IPV6:
2924 case BNX_DIR_TYPE_ISCSI_BOOT_IPV4N6:
2932 static bool bnxt_dir_type_is_executable(uint16_t dir_type)
2934 return bnxt_dir_type_is_ape_bin_format(dir_type) ||
2935 bnxt_dir_type_is_other_exec_format(dir_type);
2939 bnxt_set_eeprom_op(struct rte_eth_dev *dev,
2940 struct rte_dev_eeprom_info *in_eeprom)
2942 struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
2943 uint8_t index, dir_op;
2944 uint16_t type, ext, ordinal, attr;
2946 PMD_DRV_LOG(INFO, "%04x:%02x:%02x:%02x in_eeprom->offset = %d "
2947 "len = %d\n", bp->pdev->addr.domain,
2948 bp->pdev->addr.bus, bp->pdev->addr.devid,
2949 bp->pdev->addr.function, in_eeprom->offset, in_eeprom->length);
2952 PMD_DRV_LOG(ERR, "NVM write not supported from a VF\n");
2956 type = in_eeprom->magic >> 16;
2958 if (type == 0xffff) { /* special value for directory operations */
2959 index = in_eeprom->magic & 0xff;
2960 dir_op = in_eeprom->magic >> 8;
2964 case 0x0e: /* erase */
2965 if (in_eeprom->offset != ~in_eeprom->magic)
2967 return bnxt_hwrm_erase_nvram_directory(bp, index - 1);
2973 /* Create or re-write an NVM item: */
2974 if (bnxt_dir_type_is_executable(type) == true)
2976 ext = in_eeprom->magic & 0xffff;
2977 ordinal = in_eeprom->offset >> 16;
2978 attr = in_eeprom->offset & 0xffff;
2980 return bnxt_hwrm_flash_nvram(bp, type, ordinal, ext, attr,
2981 in_eeprom->data, in_eeprom->length);
2989 static const struct eth_dev_ops bnxt_dev_ops = {
2990 .dev_infos_get = bnxt_dev_info_get_op,
2991 .dev_close = bnxt_dev_close_op,
2992 .dev_configure = bnxt_dev_configure_op,
2993 .dev_start = bnxt_dev_start_op,
2994 .dev_stop = bnxt_dev_stop_op,
2995 .dev_set_link_up = bnxt_dev_set_link_up_op,
2996 .dev_set_link_down = bnxt_dev_set_link_down_op,
2997 .stats_get = bnxt_stats_get_op,
2998 .stats_reset = bnxt_stats_reset_op,
2999 .rx_queue_setup = bnxt_rx_queue_setup_op,
3000 .rx_queue_release = bnxt_rx_queue_release_op,
3001 .tx_queue_setup = bnxt_tx_queue_setup_op,
3002 .tx_queue_release = bnxt_tx_queue_release_op,
3003 .rx_queue_intr_enable = bnxt_rx_queue_intr_enable_op,
3004 .rx_queue_intr_disable = bnxt_rx_queue_intr_disable_op,
3005 .reta_update = bnxt_reta_update_op,
3006 .reta_query = bnxt_reta_query_op,
3007 .rss_hash_update = bnxt_rss_hash_update_op,
3008 .rss_hash_conf_get = bnxt_rss_hash_conf_get_op,
3009 .link_update = bnxt_link_update_op,
3010 .promiscuous_enable = bnxt_promiscuous_enable_op,
3011 .promiscuous_disable = bnxt_promiscuous_disable_op,
3012 .allmulticast_enable = bnxt_allmulticast_enable_op,
3013 .allmulticast_disable = bnxt_allmulticast_disable_op,
3014 .mac_addr_add = bnxt_mac_addr_add_op,
3015 .mac_addr_remove = bnxt_mac_addr_remove_op,
3016 .flow_ctrl_get = bnxt_flow_ctrl_get_op,
3017 .flow_ctrl_set = bnxt_flow_ctrl_set_op,
3018 .udp_tunnel_port_add = bnxt_udp_tunnel_port_add_op,
3019 .udp_tunnel_port_del = bnxt_udp_tunnel_port_del_op,
3020 .vlan_filter_set = bnxt_vlan_filter_set_op,
3021 .vlan_offload_set = bnxt_vlan_offload_set_op,
3022 .vlan_pvid_set = bnxt_vlan_pvid_set_op,
3023 .mtu_set = bnxt_mtu_set_op,
3024 .mac_addr_set = bnxt_set_default_mac_addr_op,
3025 .xstats_get = bnxt_dev_xstats_get_op,
3026 .xstats_get_names = bnxt_dev_xstats_get_names_op,
3027 .xstats_reset = bnxt_dev_xstats_reset_op,
3028 .fw_version_get = bnxt_fw_version_get,
3029 .set_mc_addr_list = bnxt_dev_set_mc_addr_list_op,
3030 .rxq_info_get = bnxt_rxq_info_get_op,
3031 .txq_info_get = bnxt_txq_info_get_op,
3032 .dev_led_on = bnxt_dev_led_on_op,
3033 .dev_led_off = bnxt_dev_led_off_op,
3034 .xstats_get_by_id = bnxt_dev_xstats_get_by_id_op,
3035 .xstats_get_names_by_id = bnxt_dev_xstats_get_names_by_id_op,
3036 .rx_queue_count = bnxt_rx_queue_count_op,
3037 .rx_descriptor_status = bnxt_rx_descriptor_status_op,
3038 .tx_descriptor_status = bnxt_tx_descriptor_status_op,
3039 .rx_queue_start = bnxt_rx_queue_start,
3040 .rx_queue_stop = bnxt_rx_queue_stop,
3041 .tx_queue_start = bnxt_tx_queue_start,
3042 .tx_queue_stop = bnxt_tx_queue_stop,
3043 .filter_ctrl = bnxt_filter_ctrl_op,
3044 .dev_supported_ptypes_get = bnxt_dev_supported_ptypes_get_op,
3045 .get_eeprom_length = bnxt_get_eeprom_length_op,
3046 .get_eeprom = bnxt_get_eeprom_op,
3047 .set_eeprom = bnxt_set_eeprom_op,
3048 .timesync_enable = bnxt_timesync_enable,
3049 .timesync_disable = bnxt_timesync_disable,
3050 .timesync_read_time = bnxt_timesync_read_time,
3051 .timesync_write_time = bnxt_timesync_write_time,
3052 .timesync_adjust_time = bnxt_timesync_adjust_time,
3053 .timesync_read_rx_timestamp = bnxt_timesync_read_rx_timestamp,
3054 .timesync_read_tx_timestamp = bnxt_timesync_read_tx_timestamp,
3057 static bool bnxt_vf_pciid(uint16_t id)
3059 if (id == BROADCOM_DEV_ID_57304_VF ||
3060 id == BROADCOM_DEV_ID_57406_VF ||
3061 id == BROADCOM_DEV_ID_5731X_VF ||
3062 id == BROADCOM_DEV_ID_5741X_VF ||
3063 id == BROADCOM_DEV_ID_57414_VF ||
3064 id == BROADCOM_DEV_ID_STRATUS_NIC_VF1 ||
3065 id == BROADCOM_DEV_ID_STRATUS_NIC_VF2)
3070 static int bnxt_init_board(struct rte_eth_dev *eth_dev)
3072 struct bnxt *bp = eth_dev->data->dev_private;
3073 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
3076 /* enable device (incl. PCI PM wakeup), and bus-mastering */
3077 if (!pci_dev->mem_resource[0].addr) {
3079 "Cannot find PCI device base address, aborting\n");
3081 goto init_err_disable;
3084 bp->eth_dev = eth_dev;
3087 bp->bar0 = (void *)pci_dev->mem_resource[0].addr;
3089 PMD_DRV_LOG(ERR, "Cannot map device registers, aborting\n");
3091 goto init_err_release;
3094 if (!pci_dev->mem_resource[2].addr) {
3096 "Cannot find PCI device BAR 2 address, aborting\n");
3098 goto init_err_release;
3100 bp->doorbell_base = (void *)pci_dev->mem_resource[2].addr;
3108 if (bp->doorbell_base)
3109 bp->doorbell_base = NULL;
3116 static int bnxt_dev_uninit(struct rte_eth_dev *eth_dev);
3118 #define ALLOW_FUNC(x) \
3120 typeof(x) arg = (x); \
3121 bp->pf.vf_req_fwd[((arg) >> 5)] &= \
3122 ~rte_cpu_to_le_32(1 << ((arg) & 0x1f)); \
3125 bnxt_dev_init(struct rte_eth_dev *eth_dev)
3127 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
3128 char mz_name[RTE_MEMZONE_NAMESIZE];
3129 const struct rte_memzone *mz = NULL;
3130 static int version_printed;
3131 uint32_t total_alloc_len;
3132 rte_iova_t mz_phys_addr;
3136 if (version_printed++ == 0)
3137 PMD_DRV_LOG(INFO, "%s\n", bnxt_version);
3139 rte_eth_copy_pci_info(eth_dev, pci_dev);
3141 bp = eth_dev->data->dev_private;
3143 bp->dev_stopped = 1;
3145 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
3148 if (bnxt_vf_pciid(pci_dev->id.device_id))
3149 bp->flags |= BNXT_FLAG_VF;
3151 rc = bnxt_init_board(eth_dev);
3154 "Board initialization failed rc: %x\n", rc);
3158 eth_dev->dev_ops = &bnxt_dev_ops;
3159 eth_dev->rx_pkt_burst = &bnxt_recv_pkts;
3160 eth_dev->tx_pkt_burst = &bnxt_xmit_pkts;
3161 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
3164 if (pci_dev->id.device_id != BROADCOM_DEV_ID_NS2) {
3165 snprintf(mz_name, RTE_MEMZONE_NAMESIZE,
3166 "bnxt_%04x:%02x:%02x:%02x-%s", pci_dev->addr.domain,
3167 pci_dev->addr.bus, pci_dev->addr.devid,
3168 pci_dev->addr.function, "rx_port_stats");
3169 mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0;
3170 mz = rte_memzone_lookup(mz_name);
3171 total_alloc_len = RTE_CACHE_LINE_ROUNDUP(
3172 sizeof(struct rx_port_stats) + 512);
3174 mz = rte_memzone_reserve(mz_name, total_alloc_len,
3177 RTE_MEMZONE_SIZE_HINT_ONLY |
3178 RTE_MEMZONE_IOVA_CONTIG);
3182 memset(mz->addr, 0, mz->len);
3183 mz_phys_addr = mz->iova;
3184 if ((unsigned long)mz->addr == mz_phys_addr) {
3185 PMD_DRV_LOG(WARNING,
3186 "Memzone physical address same as virtual.\n");
3187 PMD_DRV_LOG(WARNING,
3188 "Using rte_mem_virt2iova()\n");
3189 mz_phys_addr = rte_mem_virt2iova(mz->addr);
3190 if (mz_phys_addr == 0) {
3192 "unable to map address to physical memory\n");
3197 bp->rx_mem_zone = (const void *)mz;
3198 bp->hw_rx_port_stats = mz->addr;
3199 bp->hw_rx_port_stats_map = mz_phys_addr;
3201 snprintf(mz_name, RTE_MEMZONE_NAMESIZE,
3202 "bnxt_%04x:%02x:%02x:%02x-%s", pci_dev->addr.domain,
3203 pci_dev->addr.bus, pci_dev->addr.devid,
3204 pci_dev->addr.function, "tx_port_stats");
3205 mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0;
3206 mz = rte_memzone_lookup(mz_name);
3207 total_alloc_len = RTE_CACHE_LINE_ROUNDUP(
3208 sizeof(struct tx_port_stats) + 512);
3210 mz = rte_memzone_reserve(mz_name,
3214 RTE_MEMZONE_SIZE_HINT_ONLY |
3215 RTE_MEMZONE_IOVA_CONTIG);
3219 memset(mz->addr, 0, mz->len);
3220 mz_phys_addr = mz->iova;
3221 if ((unsigned long)mz->addr == mz_phys_addr) {
3222 PMD_DRV_LOG(WARNING,
3223 "Memzone physical address same as virtual.\n");
3224 PMD_DRV_LOG(WARNING,
3225 "Using rte_mem_virt2iova()\n");
3226 mz_phys_addr = rte_mem_virt2iova(mz->addr);
3227 if (mz_phys_addr == 0) {
3229 "unable to map address to physical memory\n");
3234 bp->tx_mem_zone = (const void *)mz;
3235 bp->hw_tx_port_stats = mz->addr;
3236 bp->hw_tx_port_stats_map = mz_phys_addr;
3238 bp->flags |= BNXT_FLAG_PORT_STATS;
3241 rc = bnxt_alloc_hwrm_resources(bp);
3244 "hwrm resource allocation failure rc: %x\n", rc);
3247 rc = bnxt_hwrm_ver_get(bp);
3250 rc = bnxt_hwrm_queue_qportcfg(bp);
3252 PMD_DRV_LOG(ERR, "hwrm queue qportcfg failed\n");
3256 rc = bnxt_hwrm_func_qcfg(bp);
3258 PMD_DRV_LOG(ERR, "hwrm func qcfg failed\n");
3262 /* Get the MAX capabilities for this function */
3263 rc = bnxt_hwrm_func_qcaps(bp);
3265 PMD_DRV_LOG(ERR, "hwrm query capability failure rc: %x\n", rc);
3268 if (bp->max_tx_rings == 0) {
3269 PMD_DRV_LOG(ERR, "No TX rings available!\n");
3273 eth_dev->data->mac_addrs = rte_zmalloc("bnxt_mac_addr_tbl",
3274 ETHER_ADDR_LEN * bp->max_l2_ctx, 0);
3275 if (eth_dev->data->mac_addrs == NULL) {
3277 "Failed to alloc %u bytes needed to store MAC addr tbl",
3278 ETHER_ADDR_LEN * bp->max_l2_ctx);
3283 if (bnxt_check_zero_bytes(bp->dflt_mac_addr, ETHER_ADDR_LEN)) {
3285 "Invalid MAC addr %02X:%02X:%02X:%02X:%02X:%02X\n",
3286 bp->dflt_mac_addr[0], bp->dflt_mac_addr[1],
3287 bp->dflt_mac_addr[2], bp->dflt_mac_addr[3],
3288 bp->dflt_mac_addr[4], bp->dflt_mac_addr[5]);
3292 /* Copy the permanent MAC from the qcap response address now. */
3293 memcpy(bp->mac_addr, bp->dflt_mac_addr, sizeof(bp->mac_addr));
3294 memcpy(ð_dev->data->mac_addrs[0], bp->mac_addr, ETHER_ADDR_LEN);
3296 if (bp->max_ring_grps < bp->rx_cp_nr_rings) {
3297 /* 1 ring is for default completion ring */
3298 PMD_DRV_LOG(ERR, "Insufficient resource: Ring Group\n");
3303 bp->grp_info = rte_zmalloc("bnxt_grp_info",
3304 sizeof(*bp->grp_info) * bp->max_ring_grps, 0);
3305 if (!bp->grp_info) {
3307 "Failed to alloc %zu bytes to store group info table\n",
3308 sizeof(*bp->grp_info) * bp->max_ring_grps);
3313 /* Forward all requests if firmware is new enough */
3314 if (((bp->fw_ver >= ((20 << 24) | (6 << 16) | (100 << 8))) &&
3315 (bp->fw_ver < ((20 << 24) | (7 << 16)))) ||
3316 ((bp->fw_ver >= ((20 << 24) | (8 << 16))))) {
3317 memset(bp->pf.vf_req_fwd, 0xff, sizeof(bp->pf.vf_req_fwd));
3319 PMD_DRV_LOG(WARNING,
3320 "Firmware too old for VF mailbox functionality\n");
3321 memset(bp->pf.vf_req_fwd, 0, sizeof(bp->pf.vf_req_fwd));
3325 * The following are used for driver cleanup. If we disallow these,
3326 * VF drivers can't clean up cleanly.
3328 ALLOW_FUNC(HWRM_FUNC_DRV_UNRGTR);
3329 ALLOW_FUNC(HWRM_VNIC_FREE);
3330 ALLOW_FUNC(HWRM_RING_FREE);
3331 ALLOW_FUNC(HWRM_RING_GRP_FREE);
3332 ALLOW_FUNC(HWRM_VNIC_RSS_COS_LB_CTX_FREE);
3333 ALLOW_FUNC(HWRM_CFA_L2_FILTER_FREE);
3334 ALLOW_FUNC(HWRM_STAT_CTX_FREE);
3335 ALLOW_FUNC(HWRM_PORT_PHY_QCFG);
3336 ALLOW_FUNC(HWRM_VNIC_TPA_CFG);
3337 rc = bnxt_hwrm_func_driver_register(bp);
3340 "Failed to register driver");
3346 DRV_MODULE_NAME " found at mem %" PRIx64 ", node addr %pM\n",
3347 pci_dev->mem_resource[0].phys_addr,
3348 pci_dev->mem_resource[0].addr);
3350 rc = bnxt_hwrm_func_reset(bp);
3352 PMD_DRV_LOG(ERR, "hwrm chip reset failure rc: %x\n", rc);
3358 //if (bp->pf.active_vfs) {
3359 // TODO: Deallocate VF resources?
3361 if (bp->pdev->max_vfs) {
3362 rc = bnxt_hwrm_allocate_vfs(bp, bp->pdev->max_vfs);
3364 PMD_DRV_LOG(ERR, "Failed to allocate VFs\n");
3368 rc = bnxt_hwrm_allocate_pf_only(bp);
3371 "Failed to allocate PF resources\n");
3377 bnxt_hwrm_port_led_qcaps(bp);
3379 rc = bnxt_setup_int(bp);
3383 rc = bnxt_alloc_mem(bp);
3385 goto error_free_int;
3387 rc = bnxt_request_int(bp);
3389 goto error_free_int;
3391 bnxt_enable_int(bp);
3397 bnxt_disable_int(bp);
3398 bnxt_hwrm_func_buf_unrgtr(bp);
3402 bnxt_dev_uninit(eth_dev);
3408 bnxt_dev_uninit(struct rte_eth_dev *eth_dev) {
3409 struct bnxt *bp = eth_dev->data->dev_private;
3412 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
3415 bnxt_disable_int(bp);
3418 if (eth_dev->data->mac_addrs != NULL) {
3419 rte_free(eth_dev->data->mac_addrs);
3420 eth_dev->data->mac_addrs = NULL;
3422 if (bp->grp_info != NULL) {
3423 rte_free(bp->grp_info);
3424 bp->grp_info = NULL;
3426 rc = bnxt_hwrm_func_driver_unregister(bp, 0);
3427 bnxt_free_hwrm_resources(bp);
3428 rte_memzone_free((const struct rte_memzone *)bp->tx_mem_zone);
3429 rte_memzone_free((const struct rte_memzone *)bp->rx_mem_zone);
3430 if (bp->dev_stopped == 0)
3431 bnxt_dev_close_op(eth_dev);
3433 rte_free(bp->pf.vf_info);
3434 eth_dev->dev_ops = NULL;
3435 eth_dev->rx_pkt_burst = NULL;
3436 eth_dev->tx_pkt_burst = NULL;
3441 static int bnxt_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
3442 struct rte_pci_device *pci_dev)
3444 return rte_eth_dev_pci_generic_probe(pci_dev, sizeof(struct bnxt),
3448 static int bnxt_pci_remove(struct rte_pci_device *pci_dev)
3450 return rte_eth_dev_pci_generic_remove(pci_dev, bnxt_dev_uninit);
3453 static struct rte_pci_driver bnxt_rte_pmd = {
3454 .id_table = bnxt_pci_id_map,
3455 .drv_flags = RTE_PCI_DRV_NEED_MAPPING |
3456 RTE_PCI_DRV_INTR_LSC,
3457 .probe = bnxt_pci_probe,
3458 .remove = bnxt_pci_remove,
3462 is_device_supported(struct rte_eth_dev *dev, struct rte_pci_driver *drv)
3464 if (strcmp(dev->device->driver->name, drv->driver.name))
3470 bool is_bnxt_supported(struct rte_eth_dev *dev)
3472 return is_device_supported(dev, &bnxt_rte_pmd);
3475 RTE_INIT(bnxt_init_log);
3479 bnxt_logtype_driver = rte_log_register("pmd.bnxt.driver");
3480 if (bnxt_logtype_driver >= 0)
3481 rte_log_set_level(bnxt_logtype_driver, RTE_LOG_INFO);
3484 RTE_PMD_REGISTER_PCI(net_bnxt, bnxt_rte_pmd);
3485 RTE_PMD_REGISTER_PCI_TABLE(net_bnxt, bnxt_pci_id_map);
3486 RTE_PMD_REGISTER_KMOD_DEP(net_bnxt, "* igb_uio | uio_pci_generic | vfio-pci");