drivers/net/bnxt/bnxt_ethdev.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2014-2021 Broadcom
   3  * All rights reserved.
   4  */
   5
   6 #include <inttypes.h>
   7 #include <stdbool.h>
   8
   9 #include <rte_dev.h>
  10 #include <ethdev_driver.h>
  11 #include <ethdev_pci.h>
  12 #include <rte_malloc.h>
  13 #include <rte_cycles.h>
  14 #include <rte_alarm.h>
  15 #include <rte_kvargs.h>
  16 #include <rte_vect.h>
  17
  18 #include "bnxt.h"
  19 #include "bnxt_filter.h"
  20 #include "bnxt_hwrm.h"
  21 #include "bnxt_irq.h"
  22 #include "bnxt_reps.h"
  23 #include "bnxt_ring.h"
  24 #include "bnxt_rxq.h"
  25 #include "bnxt_rxr.h"
  26 #include "bnxt_stats.h"
  27 #include "bnxt_txq.h"
  28 #include "bnxt_txr.h"
  29 #include "bnxt_vnic.h"
  30 #include "hsi_struct_def_dpdk.h"
  31 #include "bnxt_nvm_defs.h"
  32 #include "bnxt_tf_common.h"
  33 #include "ulp_flow_db.h"
  34 #include "rte_pmd_bnxt.h"
  35
  36 #define DRV_MODULE_NAME         "bnxt"
  37 static const char bnxt_version[] =
  38         "Broadcom NetXtreme driver " DRV_MODULE_NAME;
  39
  40 /*
  41  * The set of PCI devices this driver supports
  42  */
  43 static const struct rte_pci_id bnxt_pci_id_map[] = {
  44         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM,
  45                          BROADCOM_DEV_ID_STRATUS_NIC_VF1) },
  46         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM,
  47                          BROADCOM_DEV_ID_STRATUS_NIC_VF2) },
  48         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_STRATUS_NIC) },
  49         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414_VF) },
  50         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57304_VF) },
  51         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_NS2) },
  52         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57406_VF) },
  53         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57407_MF) },
  54         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_5741X_VF) },
  55         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_5731X_VF) },
  56         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_MF) },
  57         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57412) },
  58         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414) },
  59         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_RJ45) },
  60         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_RJ45) },
  61         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57412_MF) },
  62         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57317_RJ45) },
  63         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_SFP) },
  64         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_SFP) },
  65         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57317_SFP) },
  66         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414_MF) },
  67         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_MF) },
  68         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58802) },
  69         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58804) },
  70         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58808) },
  71         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58802_VF) },
  72         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57508) },
  73         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57504) },
  74         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57502) },
  75         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57500_VF1) },
  76         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57500_VF2) },
  77         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57508_MF1) },
  78         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57504_MF1) },
  79         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57502_MF1) },
  80         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57508_MF2) },
  81         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57504_MF2) },
  82         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57502_MF2) },
  83         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58812) },
  84         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58814) },
  85         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58818) },
  86         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58818_VF) },
  87         { .vendor_id = 0, /* sentinel */ },
  88 };
  89
  90 #define BNXT_DEVARG_TRUFLOW     "host-based-truflow"
  91 #define BNXT_DEVARG_FLOW_XSTAT  "flow-xstat"
  92 #define BNXT_DEVARG_MAX_NUM_KFLOWS  "max-num-kflows"
  93 #define BNXT_DEVARG_REPRESENTOR "representor"
  94 #define BNXT_DEVARG_REP_BASED_PF  "rep-based-pf"
  95 #define BNXT_DEVARG_REP_IS_PF  "rep-is-pf"
  96 #define BNXT_DEVARG_REP_Q_R2F  "rep-q-r2f"
  97 #define BNXT_DEVARG_REP_Q_F2R  "rep-q-f2r"
  98 #define BNXT_DEVARG_REP_FC_R2F  "rep-fc-r2f"
  99 #define BNXT_DEVARG_REP_FC_F2R  "rep-fc-f2r"
 100
 101 static const char *const bnxt_dev_args[] = {
 102         BNXT_DEVARG_REPRESENTOR,
 103         BNXT_DEVARG_TRUFLOW,
 104         BNXT_DEVARG_FLOW_XSTAT,
 105         BNXT_DEVARG_MAX_NUM_KFLOWS,
 106         BNXT_DEVARG_REP_BASED_PF,
 107         BNXT_DEVARG_REP_IS_PF,
 108         BNXT_DEVARG_REP_Q_R2F,
 109         BNXT_DEVARG_REP_Q_F2R,
 110         BNXT_DEVARG_REP_FC_R2F,
 111         BNXT_DEVARG_REP_FC_F2R,
 112         NULL
 113 };
 114
 115 /*
 116  * truflow == false to disable the feature
 117  * truflow == true to enable the feature
 118  */
 119 #define BNXT_DEVARG_TRUFLOW_INVALID(truflow)    ((truflow) > 1)
 120
 121 /*
 122  * flow_xstat == false to disable the feature
 123  * flow_xstat == true to enable the feature
 124  */
 125 #define BNXT_DEVARG_FLOW_XSTAT_INVALID(flow_xstat)      ((flow_xstat) > 1)
 126
 127 /*
 128  * rep_is_pf == false to indicate VF representor
 129  * rep_is_pf == true to indicate PF representor
 130  */
 131 #define BNXT_DEVARG_REP_IS_PF_INVALID(rep_is_pf)        ((rep_is_pf) > 1)
 132
 133 /*
 134  * rep_based_pf == Physical index of the PF
 135  */
 136 #define BNXT_DEVARG_REP_BASED_PF_INVALID(rep_based_pf)  ((rep_based_pf) > 15)
 137 /*
 138  * rep_q_r2f == Logical COS Queue index for the rep to endpoint direction
 139  */
 140 #define BNXT_DEVARG_REP_Q_R2F_INVALID(rep_q_r2f)        ((rep_q_r2f) > 3)
 141
 142 /*
 143  * rep_q_f2r == Logical COS Queue index for the endpoint to rep direction
 144  */
 145 #define BNXT_DEVARG_REP_Q_F2R_INVALID(rep_q_f2r)        ((rep_q_f2r) > 3)
 146
 147 /*
 148  * rep_fc_r2f == Flow control for the representor to endpoint direction
 149  */
 150 #define BNXT_DEVARG_REP_FC_R2F_INVALID(rep_fc_r2f)      ((rep_fc_r2f) > 1)
 151
 152 /*
 153  * rep_fc_f2r == Flow control for the endpoint to representor direction
 154  */
 155 #define BNXT_DEVARG_REP_FC_F2R_INVALID(rep_fc_f2r)      ((rep_fc_f2r) > 1)
 156
 157 int bnxt_cfa_code_dynfield_offset = -1;
 158
 159 /*
 160  * max_num_kflows must be >= 32
 161  * and must be a power-of-2 supported value
 162  * return: 1 -> invalid
 163  *         0 -> valid
 164  */
 165 static int bnxt_devarg_max_num_kflow_invalid(uint16_t max_num_kflows)
 166 {
 167         if (max_num_kflows < 32 || !rte_is_power_of_2(max_num_kflows))
 168                 return 1;
 169         return 0;
 170 }
 171
 172 static int bnxt_vlan_offload_set_op(struct rte_eth_dev *dev, int mask);
 173 static int bnxt_dev_uninit(struct rte_eth_dev *eth_dev);
 174 static int bnxt_init_resources(struct bnxt *bp, bool reconfig_dev);
 175 static int bnxt_uninit_resources(struct bnxt *bp, bool reconfig_dev);
 176 static void bnxt_cancel_fw_health_check(struct bnxt *bp);
 177 static int bnxt_restore_vlan_filters(struct bnxt *bp);
 178 static void bnxt_dev_recover(void *arg);
 179 static void bnxt_free_error_recovery_info(struct bnxt *bp);
 180 static void bnxt_free_rep_info(struct bnxt *bp);
 181
 182 int is_bnxt_in_error(struct bnxt *bp)
 183 {
 184         if (bp->flags & BNXT_FLAG_FATAL_ERROR)
 185                 return -EIO;
 186         if (bp->flags & BNXT_FLAG_FW_RESET)
 187                 return -EBUSY;
 188
 189         return 0;
 190 }
 191
 192 /***********************/
 193
 194 /*
 195  * High level utility functions
 196  */
 197
 198 static uint16_t bnxt_rss_ctxts(const struct bnxt *bp)
 199 {
 200         unsigned int num_rss_rings = RTE_MIN(bp->rx_nr_rings,
 201                                              BNXT_RSS_TBL_SIZE_P5);
 202
 203         if (!BNXT_CHIP_P5(bp))
 204                 return 1;
 205
 206         return RTE_ALIGN_MUL_CEIL(num_rss_rings,
 207                                   BNXT_RSS_ENTRIES_PER_CTX_P5) /
 208                                   BNXT_RSS_ENTRIES_PER_CTX_P5;
 209 }
 210
 211 uint16_t bnxt_rss_hash_tbl_size(const struct bnxt *bp)
 212 {
 213         if (!BNXT_CHIP_P5(bp))
 214                 return HW_HASH_INDEX_SIZE;
 215
 216         return bnxt_rss_ctxts(bp) * BNXT_RSS_ENTRIES_PER_CTX_P5;
 217 }
 218
 219 static void bnxt_free_parent_info(struct bnxt *bp)
 220 {
 221         rte_free(bp->parent);
 222 }
 223
 224 static void bnxt_free_pf_info(struct bnxt *bp)
 225 {
 226         rte_free(bp->pf);
 227 }
 228
 229 static void bnxt_free_link_info(struct bnxt *bp)
 230 {
 231         rte_free(bp->link_info);
 232 }
 233
 234 static void bnxt_free_leds_info(struct bnxt *bp)
 235 {
 236         if (BNXT_VF(bp))
 237                 return;
 238
 239         rte_free(bp->leds);
 240         bp->leds = NULL;
 241 }
 242
 243 static void bnxt_free_flow_stats_info(struct bnxt *bp)
 244 {
 245         rte_free(bp->flow_stat);
 246         bp->flow_stat = NULL;
 247 }
 248
 249 static void bnxt_free_cos_queues(struct bnxt *bp)
 250 {
 251         rte_free(bp->rx_cos_queue);
 252         rte_free(bp->tx_cos_queue);
 253 }
 254
 255 static void bnxt_free_mem(struct bnxt *bp, bool reconfig)
 256 {
 257         bnxt_free_filter_mem(bp);
 258         bnxt_free_vnic_attributes(bp);
 259         bnxt_free_vnic_mem(bp);
 260
 261         /* tx/rx rings are configured as part of *_queue_setup callbacks.
 262          * If the number of rings change across fw update,
 263          * we don't have much choice except to warn the user.
 264          */
 265         if (!reconfig) {
 266                 bnxt_free_stats(bp);
 267                 bnxt_free_tx_rings(bp);
 268                 bnxt_free_rx_rings(bp);
 269         }
 270         bnxt_free_async_cp_ring(bp);
 271         bnxt_free_rxtx_nq_ring(bp);
 272
 273         rte_free(bp->grp_info);
 274         bp->grp_info = NULL;
 275 }
 276
 277 static int bnxt_alloc_parent_info(struct bnxt *bp)
 278 {
 279         bp->parent = rte_zmalloc("bnxt_parent_info",
 280                                  sizeof(struct bnxt_parent_info), 0);
 281         if (bp->parent == NULL)
 282                 return -ENOMEM;
 283
 284         return 0;
 285 }
 286
 287 static int bnxt_alloc_pf_info(struct bnxt *bp)
 288 {
 289         bp->pf = rte_zmalloc("bnxt_pf_info", sizeof(struct bnxt_pf_info), 0);
 290         if (bp->pf == NULL)
 291                 return -ENOMEM;
 292
 293         return 0;
 294 }
 295
 296 static int bnxt_alloc_link_info(struct bnxt *bp)
 297 {
 298         bp->link_info =
 299                 rte_zmalloc("bnxt_link_info", sizeof(struct bnxt_link_info), 0);
 300         if (bp->link_info == NULL)
 301                 return -ENOMEM;
 302
 303         return 0;
 304 }
 305
 306 static int bnxt_alloc_leds_info(struct bnxt *bp)
 307 {
 308         if (BNXT_VF(bp))
 309                 return 0;
 310
 311         bp->leds = rte_zmalloc("bnxt_leds",
 312                                BNXT_MAX_LED * sizeof(struct bnxt_led_info),
 313                                0);
 314         if (bp->leds == NULL)
 315                 return -ENOMEM;
 316
 317         return 0;
 318 }
 319
 320 static int bnxt_alloc_cos_queues(struct bnxt *bp)
 321 {
 322         bp->rx_cos_queue =
 323                 rte_zmalloc("bnxt_rx_cosq",
 324                             BNXT_COS_QUEUE_COUNT *
 325                             sizeof(struct bnxt_cos_queue_info),
 326                             0);
 327         if (bp->rx_cos_queue == NULL)
 328                 return -ENOMEM;
 329
 330         bp->tx_cos_queue =
 331                 rte_zmalloc("bnxt_tx_cosq",
 332                             BNXT_COS_QUEUE_COUNT *
 333                             sizeof(struct bnxt_cos_queue_info),
 334                             0);
 335         if (bp->tx_cos_queue == NULL)
 336                 return -ENOMEM;
 337
 338         return 0;
 339 }
 340
 341 static int bnxt_alloc_flow_stats_info(struct bnxt *bp)
 342 {
 343         bp->flow_stat = rte_zmalloc("bnxt_flow_xstat",
 344                                     sizeof(struct bnxt_flow_stat_info), 0);
 345         if (bp->flow_stat == NULL)
 346                 return -ENOMEM;
 347
 348         return 0;
 349 }
 350
 351 static int bnxt_alloc_mem(struct bnxt *bp, bool reconfig)
 352 {
 353         int rc;
 354
 355         rc = bnxt_alloc_ring_grps(bp);
 356         if (rc)
 357                 goto alloc_mem_err;
 358
 359         rc = bnxt_alloc_async_ring_struct(bp);
 360         if (rc)
 361                 goto alloc_mem_err;
 362
 363         rc = bnxt_alloc_vnic_mem(bp);
 364         if (rc)
 365                 goto alloc_mem_err;
 366
 367         rc = bnxt_alloc_vnic_attributes(bp);
 368         if (rc)
 369                 goto alloc_mem_err;
 370
 371         rc = bnxt_alloc_filter_mem(bp);
 372         if (rc)
 373                 goto alloc_mem_err;
 374
 375         rc = bnxt_alloc_async_cp_ring(bp);
 376         if (rc)
 377                 goto alloc_mem_err;
 378
 379         rc = bnxt_alloc_rxtx_nq_ring(bp);
 380         if (rc)
 381                 goto alloc_mem_err;
 382
 383         if (BNXT_FLOW_XSTATS_EN(bp)) {
 384                 rc = bnxt_alloc_flow_stats_info(bp);
 385                 if (rc)
 386                         goto alloc_mem_err;
 387         }
 388
 389         return 0;
 390
 391 alloc_mem_err:
 392         bnxt_free_mem(bp, reconfig);
 393         return rc;
 394 }
 395
 396 static int bnxt_setup_one_vnic(struct bnxt *bp, uint16_t vnic_id)
 397 {
 398         struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
 399         struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id];
 400         uint64_t rx_offloads = dev_conf->rxmode.offloads;
 401         struct bnxt_rx_queue *rxq;
 402         unsigned int j;
 403         int rc;
 404
 405         rc = bnxt_vnic_grp_alloc(bp, vnic);
 406         if (rc)
 407                 goto err_out;
 408
 409         PMD_DRV_LOG(DEBUG, "vnic[%d] = %p vnic->fw_grp_ids = %p\n",
 410                     vnic_id, vnic, vnic->fw_grp_ids);
 411
 412         rc = bnxt_hwrm_vnic_alloc(bp, vnic);
 413         if (rc)
 414                 goto err_out;
 415
 416         /* Alloc RSS context only if RSS mode is enabled */
 417         if (dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS) {
 418                 int j, nr_ctxs = bnxt_rss_ctxts(bp);
 419
 420                 if (bp->rx_nr_rings > BNXT_RSS_TBL_SIZE_P5) {
 421                         PMD_DRV_LOG(ERR, "RxQ cnt %d > reta_size %d\n",
 422                                     bp->rx_nr_rings, BNXT_RSS_TBL_SIZE_P5);
 423                         PMD_DRV_LOG(ERR,
 424                                     "Only queues 0-%d will be in RSS table\n",
 425                                     BNXT_RSS_TBL_SIZE_P5 - 1);
 426                 }
 427
 428                 rc = 0;
 429                 for (j = 0; j < nr_ctxs; j++) {
 430                         rc = bnxt_hwrm_vnic_ctx_alloc(bp, vnic, j);
 431                         if (rc)
 432                                 break;
 433                 }
 434                 if (rc) {
 435                         PMD_DRV_LOG(ERR,
 436                                     "HWRM vnic %d ctx %d alloc failure rc: %x\n",
 437                                     vnic_id, j, rc);
 438                         goto err_out;
 439                 }
 440                 vnic->num_lb_ctxts = nr_ctxs;
 441         }
 442
 443         /*
 444          * Firmware sets pf pair in default vnic cfg. If the VLAN strip
 445          * setting is not available at this time, it will not be
 446          * configured correctly in the CFA.
 447          */
 448         if (rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
 449                 vnic->vlan_strip = true;
 450         else
 451                 vnic->vlan_strip = false;
 452
 453         rc = bnxt_hwrm_vnic_cfg(bp, vnic);
 454         if (rc)
 455                 goto err_out;
 456
 457         rc = bnxt_set_hwrm_vnic_filters(bp, vnic);
 458         if (rc)
 459                 goto err_out;
 460
 461         for (j = 0; j < bp->rx_num_qs_per_vnic; j++) {
 462                 rxq = bp->eth_dev->data->rx_queues[j];
 463
 464                 PMD_DRV_LOG(DEBUG,
 465                             "rxq[%d]->vnic=%p vnic->fw_grp_ids=%p\n",
 466                             j, rxq->vnic, rxq->vnic->fw_grp_ids);
 467
 468                 if (BNXT_HAS_RING_GRPS(bp) && rxq->rx_deferred_start)
 469                         rxq->vnic->fw_grp_ids[j] = INVALID_HW_RING_ID;
 470                 else
 471                         vnic->rx_queue_cnt++;
 472         }
 473
 474         PMD_DRV_LOG(DEBUG, "vnic->rx_queue_cnt = %d\n", vnic->rx_queue_cnt);
 475
 476         rc = bnxt_vnic_rss_configure(bp, vnic);
 477         if (rc)
 478                 goto err_out;
 479
 480         bnxt_hwrm_vnic_plcmode_cfg(bp, vnic);
 481
 482         if (rx_offloads & DEV_RX_OFFLOAD_TCP_LRO)
 483                 bnxt_hwrm_vnic_tpa_cfg(bp, vnic, 1);
 484         else
 485                 bnxt_hwrm_vnic_tpa_cfg(bp, vnic, 0);
 486
 487         return 0;
 488 err_out:
 489         PMD_DRV_LOG(ERR, "HWRM vnic %d cfg failure rc: %x\n",
 490                     vnic_id, rc);
 491         return rc;
 492 }
 493
 494 static int bnxt_register_fc_ctx_mem(struct bnxt *bp)
 495 {
 496         int rc = 0;
 497
 498         rc = bnxt_hwrm_ctx_rgtr(bp, bp->flow_stat->rx_fc_in_tbl.dma,
 499                                 &bp->flow_stat->rx_fc_in_tbl.ctx_id);
 500         if (rc)
 501                 return rc;
 502
 503         PMD_DRV_LOG(DEBUG,
 504                     "rx_fc_in_tbl.va = %p rx_fc_in_tbl.dma = %p"
 505                     " rx_fc_in_tbl.ctx_id = %d\n",
 506                     bp->flow_stat->rx_fc_in_tbl.va,
 507                     (void *)((uintptr_t)bp->flow_stat->rx_fc_in_tbl.dma),
 508                     bp->flow_stat->rx_fc_in_tbl.ctx_id);
 509
 510         rc = bnxt_hwrm_ctx_rgtr(bp, bp->flow_stat->rx_fc_out_tbl.dma,
 511                                 &bp->flow_stat->rx_fc_out_tbl.ctx_id);
 512         if (rc)
 513                 return rc;
 514
 515         PMD_DRV_LOG(DEBUG,
 516                     "rx_fc_out_tbl.va = %p rx_fc_out_tbl.dma = %p"
 517                     " rx_fc_out_tbl.ctx_id = %d\n",
 518                     bp->flow_stat->rx_fc_out_tbl.va,
 519                     (void *)((uintptr_t)bp->flow_stat->rx_fc_out_tbl.dma),
 520                     bp->flow_stat->rx_fc_out_tbl.ctx_id);
 521
 522         rc = bnxt_hwrm_ctx_rgtr(bp, bp->flow_stat->tx_fc_in_tbl.dma,
 523                                 &bp->flow_stat->tx_fc_in_tbl.ctx_id);
 524         if (rc)
 525                 return rc;
 526
 527         PMD_DRV_LOG(DEBUG,
 528                     "tx_fc_in_tbl.va = %p tx_fc_in_tbl.dma = %p"
 529                     " tx_fc_in_tbl.ctx_id = %d\n",
 530                     bp->flow_stat->tx_fc_in_tbl.va,
 531                     (void *)((uintptr_t)bp->flow_stat->tx_fc_in_tbl.dma),
 532                     bp->flow_stat->tx_fc_in_tbl.ctx_id);
 533
 534         rc = bnxt_hwrm_ctx_rgtr(bp, bp->flow_stat->tx_fc_out_tbl.dma,
 535                                 &bp->flow_stat->tx_fc_out_tbl.ctx_id);
 536         if (rc)
 537                 return rc;
 538
 539         PMD_DRV_LOG(DEBUG,
 540                     "tx_fc_out_tbl.va = %p tx_fc_out_tbl.dma = %p"
 541                     " tx_fc_out_tbl.ctx_id = %d\n",
 542                     bp->flow_stat->tx_fc_out_tbl.va,
 543                     (void *)((uintptr_t)bp->flow_stat->tx_fc_out_tbl.dma),
 544                     bp->flow_stat->tx_fc_out_tbl.ctx_id);
 545
 546         memset(bp->flow_stat->rx_fc_out_tbl.va,
 547                0,
 548                bp->flow_stat->rx_fc_out_tbl.size);
 549         rc = bnxt_hwrm_cfa_counter_cfg(bp, BNXT_DIR_RX,
 550                                        CFA_COUNTER_CFG_IN_COUNTER_TYPE_FC,
 551                                        bp->flow_stat->rx_fc_out_tbl.ctx_id,
 552                                        bp->flow_stat->max_fc,
 553                                        true);
 554         if (rc)
 555                 return rc;
 556
 557         memset(bp->flow_stat->tx_fc_out_tbl.va,
 558                0,
 559                bp->flow_stat->tx_fc_out_tbl.size);
 560         rc = bnxt_hwrm_cfa_counter_cfg(bp, BNXT_DIR_TX,
 561                                        CFA_COUNTER_CFG_IN_COUNTER_TYPE_FC,
 562                                        bp->flow_stat->tx_fc_out_tbl.ctx_id,
 563                                        bp->flow_stat->max_fc,
 564                                        true);
 565
 566         return rc;
 567 }
 568
 569 static int bnxt_alloc_ctx_mem_buf(char *type, size_t size,
 570                                   struct bnxt_ctx_mem_buf_info *ctx)
 571 {
 572         if (!ctx)
 573                 return -EINVAL;
 574
 575         ctx->va = rte_zmalloc(type, size, 0);
 576         if (ctx->va == NULL)
 577                 return -ENOMEM;
 578         rte_mem_lock_page(ctx->va);
 579         ctx->size = size;
 580         ctx->dma = rte_mem_virt2iova(ctx->va);
 581         if (ctx->dma == RTE_BAD_IOVA)
 582                 return -ENOMEM;
 583
 584         return 0;
 585 }
 586
 587 static int bnxt_init_fc_ctx_mem(struct bnxt *bp)
 588 {
 589         struct rte_pci_device *pdev = bp->pdev;
 590         char type[RTE_MEMZONE_NAMESIZE];
 591         uint16_t max_fc;
 592         int rc = 0;
 593
 594         max_fc = bp->flow_stat->max_fc;
 595
 596         sprintf(type, "bnxt_rx_fc_in_" PCI_PRI_FMT, pdev->addr.domain,
 597                 pdev->addr.bus, pdev->addr.devid, pdev->addr.function);
 598         /* 4 bytes for each counter-id */
 599         rc = bnxt_alloc_ctx_mem_buf(type,
 600                                     max_fc * 4,
 601                                     &bp->flow_stat->rx_fc_in_tbl);
 602         if (rc)
 603                 return rc;
 604
 605         sprintf(type, "bnxt_rx_fc_out_" PCI_PRI_FMT, pdev->addr.domain,
 606                 pdev->addr.bus, pdev->addr.devid, pdev->addr.function);
 607         /* 16 bytes for each counter - 8 bytes pkt_count, 8 bytes byte_count */
 608         rc = bnxt_alloc_ctx_mem_buf(type,
 609                                     max_fc * 16,
 610                                     &bp->flow_stat->rx_fc_out_tbl);
 611         if (rc)
 612                 return rc;
 613
 614         sprintf(type, "bnxt_tx_fc_in_" PCI_PRI_FMT, pdev->addr.domain,
 615                 pdev->addr.bus, pdev->addr.devid, pdev->addr.function);
 616         /* 4 bytes for each counter-id */
 617         rc = bnxt_alloc_ctx_mem_buf(type,
 618                                     max_fc * 4,
 619                                     &bp->flow_stat->tx_fc_in_tbl);
 620         if (rc)
 621                 return rc;
 622
 623         sprintf(type, "bnxt_tx_fc_out_" PCI_PRI_FMT, pdev->addr.domain,
 624                 pdev->addr.bus, pdev->addr.devid, pdev->addr.function);
 625         /* 16 bytes for each counter - 8 bytes pkt_count, 8 bytes byte_count */
 626         rc = bnxt_alloc_ctx_mem_buf(type,
 627                                     max_fc * 16,
 628                                     &bp->flow_stat->tx_fc_out_tbl);
 629         if (rc)
 630                 return rc;
 631
 632         rc = bnxt_register_fc_ctx_mem(bp);
 633
 634         return rc;
 635 }
 636
 637 static int bnxt_init_ctx_mem(struct bnxt *bp)
 638 {
 639         int rc = 0;
 640
 641         if (!(bp->fw_cap & BNXT_FW_CAP_ADV_FLOW_COUNTERS) ||
 642             !(BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp)) ||
 643             !BNXT_FLOW_XSTATS_EN(bp))
 644                 return 0;
 645
 646         rc = bnxt_hwrm_cfa_counter_qcaps(bp, &bp->flow_stat->max_fc);
 647         if (rc)
 648                 return rc;
 649
 650         rc = bnxt_init_fc_ctx_mem(bp);
 651
 652         return rc;
 653 }
 654
 655 static int bnxt_update_phy_setting(struct bnxt *bp)
 656 {
 657         struct rte_eth_link new;
 658         int rc;
 659
 660         rc = bnxt_get_hwrm_link_config(bp, &new);
 661         if (rc) {
 662                 PMD_DRV_LOG(ERR, "Failed to get link settings\n");
 663                 return rc;
 664         }
 665
 666         /*
 667          * On BCM957508-N2100 adapters, FW will not allow any user other
 668          * than BMC to shutdown the port. bnxt_get_hwrm_link_config() call
 669          * always returns link up. Force phy update always in that case.
 670          */
 671         if (!new.link_status || IS_BNXT_DEV_957508_N2100(bp)) {
 672                 rc = bnxt_set_hwrm_link_config(bp, true);
 673                 if (rc) {
 674                         PMD_DRV_LOG(ERR, "Failed to update PHY settings\n");
 675                         return rc;
 676                 }
 677         }
 678
 679         return rc;
 680 }
 681
 682 static int bnxt_start_nic(struct bnxt *bp)
 683 {
 684         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(bp->eth_dev);
 685         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
 686         uint32_t intr_vector = 0;
 687         uint32_t queue_id, base = BNXT_MISC_VEC_ID;
 688         uint32_t vec = BNXT_MISC_VEC_ID;
 689         unsigned int i, j;
 690         int rc;
 691
 692         if (bp->eth_dev->data->mtu > RTE_ETHER_MTU) {
 693                 bp->eth_dev->data->dev_conf.rxmode.offloads |=
 694                         DEV_RX_OFFLOAD_JUMBO_FRAME;
 695                 bp->flags |= BNXT_FLAG_JUMBO;
 696         } else {
 697                 bp->eth_dev->data->dev_conf.rxmode.offloads &=
 698                         ~DEV_RX_OFFLOAD_JUMBO_FRAME;
 699                 bp->flags &= ~BNXT_FLAG_JUMBO;
 700         }
 701
 702         /* THOR does not support ring groups.
 703          * But we will use the array to save RSS context IDs.
 704          */
 705         if (BNXT_CHIP_P5(bp))
 706                 bp->max_ring_grps = BNXT_MAX_RSS_CTXTS_P5;
 707
 708         rc = bnxt_alloc_all_hwrm_stat_ctxs(bp);
 709         if (rc) {
 710                 PMD_DRV_LOG(ERR, "HWRM stat ctx alloc failure rc: %x\n", rc);
 711                 goto err_out;
 712         }
 713
 714         rc = bnxt_alloc_hwrm_rings(bp);
 715         if (rc) {
 716                 PMD_DRV_LOG(ERR, "HWRM ring alloc failure rc: %x\n", rc);
 717                 goto err_out;
 718         }
 719
 720         rc = bnxt_alloc_all_hwrm_ring_grps(bp);
 721         if (rc) {
 722                 PMD_DRV_LOG(ERR, "HWRM ring grp alloc failure: %x\n", rc);
 723                 goto err_out;
 724         }
 725
 726         if (!(bp->vnic_cap_flags & BNXT_VNIC_CAP_COS_CLASSIFY))
 727                 goto skip_cosq_cfg;
 728
 729         for (j = 0, i = 0; i < BNXT_COS_QUEUE_COUNT; i++) {
 730                 if (bp->rx_cos_queue[i].id != 0xff) {
 731                         struct bnxt_vnic_info *vnic = &bp->vnic_info[j++];
 732
 733                         if (!vnic) {
 734                                 PMD_DRV_LOG(ERR,
 735                                             "Num pools more than FW profile\n");
 736                                 rc = -EINVAL;
 737                                 goto err_out;
 738                         }
 739                         vnic->cos_queue_id = bp->rx_cos_queue[i].id;
 740                         bp->rx_cosq_cnt++;
 741                 }
 742         }
 743
 744 skip_cosq_cfg:
 745         rc = bnxt_mq_rx_configure(bp);
 746         if (rc) {
 747                 PMD_DRV_LOG(ERR, "MQ mode configure failure rc: %x\n", rc);
 748                 goto err_out;
 749         }
 750
 751         /* default vnic 0 */
 752         rc = bnxt_setup_one_vnic(bp, 0);
 753         if (rc)
 754                 goto err_out;
 755         /* VNIC configuration */
 756         if (BNXT_RFS_NEEDS_VNIC(bp)) {
 757                 for (i = 1; i < bp->nr_vnics; i++) {
 758                         rc = bnxt_setup_one_vnic(bp, i);
 759                         if (rc)
 760                                 goto err_out;
 761                 }
 762         }
 763
 764         rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, &bp->vnic_info[0], 0, NULL);
 765         if (rc) {
 766                 PMD_DRV_LOG(ERR,
 767                         "HWRM cfa l2 rx mask failure rc: %x\n", rc);
 768                 goto err_out;
 769         }
 770
 771         /* check and configure queue intr-vector mapping */
 772         if ((rte_intr_cap_multiple(intr_handle) ||
 773              !RTE_ETH_DEV_SRIOV(bp->eth_dev).active) &&
 774             bp->eth_dev->data->dev_conf.intr_conf.rxq != 0) {
 775                 intr_vector = bp->eth_dev->data->nb_rx_queues;
 776                 PMD_DRV_LOG(DEBUG, "intr_vector = %d\n", intr_vector);
 777                 if (intr_vector > bp->rx_cp_nr_rings) {
 778                         PMD_DRV_LOG(ERR, "At most %d intr queues supported",
 779                                         bp->rx_cp_nr_rings);
 780                         return -ENOTSUP;
 781                 }
 782                 rc = rte_intr_efd_enable(intr_handle, intr_vector);
 783                 if (rc)
 784                         return rc;
 785         }
 786
 787         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
 788                 intr_handle->intr_vec =
 789                         rte_zmalloc("intr_vec",
 790                                     bp->eth_dev->data->nb_rx_queues *
 791                                     sizeof(int), 0);
 792                 if (intr_handle->intr_vec == NULL) {
 793                         PMD_DRV_LOG(ERR, "Failed to allocate %d rx_queues"
 794                                 " intr_vec", bp->eth_dev->data->nb_rx_queues);
 795                         rc = -ENOMEM;
 796                         goto err_disable;
 797                 }
 798                 PMD_DRV_LOG(DEBUG, "intr_handle->intr_vec = %p "
 799                         "intr_handle->nb_efd = %d intr_handle->max_intr = %d\n",
 800                          intr_handle->intr_vec, intr_handle->nb_efd,
 801                         intr_handle->max_intr);
 802                 for (queue_id = 0; queue_id < bp->eth_dev->data->nb_rx_queues;
 803                      queue_id++) {
 804                         intr_handle->intr_vec[queue_id] =
 805                                                         vec + BNXT_RX_VEC_START;
 806                         if (vec < base + intr_handle->nb_efd - 1)
 807                                 vec++;
 808                 }
 809         }
 810
 811         /* enable uio/vfio intr/eventfd mapping */
 812         rc = rte_intr_enable(intr_handle);
 813 #ifndef RTE_EXEC_ENV_FREEBSD
 814         /* In FreeBSD OS, nic_uio driver does not support interrupts */
 815         if (rc)
 816                 goto err_free;
 817 #endif
 818
 819         rc = bnxt_update_phy_setting(bp);
 820         if (rc)
 821                 goto err_free;
 822
 823         bp->mark_table = rte_zmalloc("bnxt_mark_table", BNXT_MARK_TABLE_SZ, 0);
 824         if (!bp->mark_table)
 825                 PMD_DRV_LOG(ERR, "Allocation of mark table failed\n");
 826
 827         return 0;
 828
 829 err_free:
 830         rte_free(intr_handle->intr_vec);
 831 err_disable:
 832         rte_intr_efd_disable(intr_handle);
 833 err_out:
 834         /* Some of the error status returned by FW may not be from errno.h */
 835         if (rc > 0)
 836                 rc = -EIO;
 837
 838         return rc;
 839 }
 840
 841 static int bnxt_shutdown_nic(struct bnxt *bp)
 842 {
 843         bnxt_free_all_hwrm_resources(bp);
 844         bnxt_free_all_filters(bp);
 845         bnxt_free_all_vnics(bp);
 846         return 0;
 847 }
 848
 849 /*
 850  * Device configuration and status function
 851  */
 852
 853 uint32_t bnxt_get_speed_capabilities(struct bnxt *bp)
 854 {
 855         uint32_t link_speed = bp->link_info->support_speeds;
 856         uint32_t speed_capa = 0;
 857
 858         /* If PAM4 is configured, use PAM4 supported speed */
 859         if (link_speed == 0 && bp->link_info->support_pam4_speeds > 0)
 860                 link_speed = bp->link_info->support_pam4_speeds;
 861
 862         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_100MB)
 863                 speed_capa |= ETH_LINK_SPEED_100M;
 864         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_100MBHD)
 865                 speed_capa |= ETH_LINK_SPEED_100M_HD;
 866         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_1GB)
 867                 speed_capa |= ETH_LINK_SPEED_1G;
 868         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_2_5GB)
 869                 speed_capa |= ETH_LINK_SPEED_2_5G;
 870         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_10GB)
 871                 speed_capa |= ETH_LINK_SPEED_10G;
 872         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_20GB)
 873                 speed_capa |= ETH_LINK_SPEED_20G;
 874         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_25GB)
 875                 speed_capa |= ETH_LINK_SPEED_25G;
 876         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_40GB)
 877                 speed_capa |= ETH_LINK_SPEED_40G;
 878         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_50GB)
 879                 speed_capa |= ETH_LINK_SPEED_50G;
 880         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_100GB)
 881                 speed_capa |= ETH_LINK_SPEED_100G;
 882         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_PAM4_SPEEDS_50G)
 883                 speed_capa |= ETH_LINK_SPEED_50G;
 884         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_PAM4_SPEEDS_100G)
 885                 speed_capa |= ETH_LINK_SPEED_100G;
 886         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_PAM4_SPEEDS_200G)
 887                 speed_capa |= ETH_LINK_SPEED_200G;
 888
 889         if (bp->link_info->auto_mode ==
 890             HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_MODE_NONE)
 891                 speed_capa |= ETH_LINK_SPEED_FIXED;
 892
 893         return speed_capa;
 894 }
 895
 896 static int bnxt_dev_info_get_op(struct rte_eth_dev *eth_dev,
 897                                 struct rte_eth_dev_info *dev_info)
 898 {
 899         struct rte_pci_device *pdev = RTE_DEV_TO_PCI(eth_dev->device);
 900         struct bnxt *bp = eth_dev->data->dev_private;
 901         uint16_t max_vnics, i, j, vpool, vrxq;
 902         unsigned int max_rx_rings;
 903         int rc;
 904
 905         rc = is_bnxt_in_error(bp);
 906         if (rc)
 907                 return rc;
 908
 909         /* MAC Specifics */
 910         dev_info->max_mac_addrs = bp->max_l2_ctx;
 911         dev_info->max_hash_mac_addrs = 0;
 912
 913         /* PF/VF specifics */
 914         if (BNXT_PF(bp))
 915                 dev_info->max_vfs = pdev->max_vfs;
 916
 917         max_rx_rings = bnxt_max_rings(bp);
 918         /* For the sake of symmetry, max_rx_queues = max_tx_queues */
 919         dev_info->max_rx_queues = max_rx_rings;
 920         dev_info->max_tx_queues = max_rx_rings;
 921         dev_info->reta_size = bnxt_rss_hash_tbl_size(bp);
 922         dev_info->hash_key_size = 40;
 923         max_vnics = bp->max_vnics;
 924
 925         /* MTU specifics */
 926         dev_info->min_mtu = RTE_ETHER_MIN_MTU;
 927         dev_info->max_mtu = BNXT_MAX_MTU;
 928
 929         /* Fast path specifics */
 930         dev_info->min_rx_bufsize = 1;
 931         dev_info->max_rx_pktlen = BNXT_MAX_PKT_LEN;
 932
 933         dev_info->rx_offload_capa = BNXT_DEV_RX_OFFLOAD_SUPPORT;
 934         if (bp->flags & BNXT_FLAG_PTP_SUPPORTED)
 935                 dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_TIMESTAMP;
 936         dev_info->tx_queue_offload_capa = DEV_TX_OFFLOAD_MBUF_FAST_FREE;
 937         dev_info->tx_offload_capa = BNXT_DEV_TX_OFFLOAD_SUPPORT |
 938                                     dev_info->tx_queue_offload_capa;
 939         dev_info->flow_type_rss_offloads = BNXT_ETH_RSS_SUPPORT;
 940
 941         dev_info->speed_capa = bnxt_get_speed_capabilities(bp);
 942
 943         /* *INDENT-OFF* */
 944         dev_info->default_rxconf = (struct rte_eth_rxconf) {
 945                 .rx_thresh = {
 946                         .pthresh = 8,
 947                         .hthresh = 8,
 948                         .wthresh = 0,
 949                 },
 950                 .rx_free_thresh = 32,
 951                 .rx_drop_en = BNXT_DEFAULT_RX_DROP_EN,
 952         };
 953
 954         dev_info->default_txconf = (struct rte_eth_txconf) {
 955                 .tx_thresh = {
 956                         .pthresh = 32,
 957                         .hthresh = 0,
 958                         .wthresh = 0,
 959                 },
 960                 .tx_free_thresh = 32,
 961                 .tx_rs_thresh = 32,
 962         };
 963         eth_dev->data->dev_conf.intr_conf.lsc = 1;
 964
 965         eth_dev->data->dev_conf.intr_conf.rxq = 1;
 966         dev_info->rx_desc_lim.nb_min = BNXT_MIN_RING_DESC;
 967         dev_info->rx_desc_lim.nb_max = BNXT_MAX_RX_RING_DESC;
 968         dev_info->tx_desc_lim.nb_min = BNXT_MIN_RING_DESC;
 969         dev_info->tx_desc_lim.nb_max = BNXT_MAX_TX_RING_DESC;
 970
 971         if (BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp)) {
 972                 dev_info->switch_info.name = eth_dev->device->name;
 973                 dev_info->switch_info.domain_id = bp->switch_domain_id;
 974                 dev_info->switch_info.port_id =
 975                                 BNXT_PF(bp) ? BNXT_SWITCH_PORT_ID_PF :
 976                                     BNXT_SWITCH_PORT_ID_TRUSTED_VF;
 977         }
 978
 979         /* *INDENT-ON* */
 980
 981         /*
 982          * TODO: default_rxconf, default_txconf, rx_desc_lim, and tx_desc_lim
 983          *       need further investigation.
 984          */
 985
 986         /* VMDq resources */
 987         vpool = 64; /* ETH_64_POOLS */
 988         vrxq = 128; /* ETH_VMDQ_DCB_NUM_QUEUES */
 989         for (i = 0; i < 4; vpool >>= 1, i++) {
 990                 if (max_vnics > vpool) {
 991                         for (j = 0; j < 5; vrxq >>= 1, j++) {
 992                                 if (dev_info->max_rx_queues > vrxq) {
 993                                         if (vpool > vrxq)
 994                                                 vpool = vrxq;
 995                                         goto found;
 996                                 }
 997                         }
 998                         /* Not enough resources to support VMDq */
 999                         break;
1000                 }
1001         }
1002         /* Not enough resources to support VMDq */
1003         vpool = 0;
1004         vrxq = 0;
1005 found:
1006         dev_info->max_vmdq_pools = vpool;
1007         dev_info->vmdq_queue_num = vrxq;
1008
1009         dev_info->vmdq_pool_base = 0;
1010         dev_info->vmdq_queue_base = 0;
1011
1012         return 0;
1013 }
1014
1015 /* Configure the device based on the configuration provided */
1016 static int bnxt_dev_configure_op(struct rte_eth_dev *eth_dev)
1017 {
1018         struct bnxt *bp = eth_dev->data->dev_private;
1019         uint64_t rx_offloads = eth_dev->data->dev_conf.rxmode.offloads;
1020         int rc;
1021
1022         bp->rx_queues = (void *)eth_dev->data->rx_queues;
1023         bp->tx_queues = (void *)eth_dev->data->tx_queues;
1024         bp->tx_nr_rings = eth_dev->data->nb_tx_queues;
1025         bp->rx_nr_rings = eth_dev->data->nb_rx_queues;
1026
1027         rc = is_bnxt_in_error(bp);
1028         if (rc)
1029                 return rc;
1030
1031         if (BNXT_VF(bp) && (bp->flags & BNXT_FLAG_NEW_RM)) {
1032                 rc = bnxt_hwrm_check_vf_rings(bp);
1033                 if (rc) {
1034                         PMD_DRV_LOG(ERR, "HWRM insufficient resources\n");
1035                         return -ENOSPC;
1036                 }
1037
1038                 /* If a resource has already been allocated - in this case
1039                  * it is the async completion ring, free it. Reallocate it after
1040                  * resource reservation. This will ensure the resource counts
1041                  * are calculated correctly.
1042                  */
1043
1044                 pthread_mutex_lock(&bp->def_cp_lock);
1045
1046                 if (!BNXT_HAS_NQ(bp) && bp->async_cp_ring) {
1047                         bnxt_disable_int(bp);
1048                         bnxt_free_cp_ring(bp, bp->async_cp_ring);
1049                 }
1050
1051                 rc = bnxt_hwrm_func_reserve_vf_resc(bp, false);
1052                 if (rc) {
1053                         PMD_DRV_LOG(ERR, "HWRM resource alloc fail:%x\n", rc);
1054                         pthread_mutex_unlock(&bp->def_cp_lock);
1055                         return -ENOSPC;
1056                 }
1057
1058                 if (!BNXT_HAS_NQ(bp) && bp->async_cp_ring) {
1059                         rc = bnxt_alloc_async_cp_ring(bp);
1060                         if (rc) {
1061                                 pthread_mutex_unlock(&bp->def_cp_lock);
1062                                 return rc;
1063                         }
1064                         bnxt_enable_int(bp);
1065                 }
1066
1067                 pthread_mutex_unlock(&bp->def_cp_lock);
1068         }
1069
1070         /* Inherit new configurations */
1071         if (eth_dev->data->nb_rx_queues > bp->max_rx_rings ||
1072             eth_dev->data->nb_tx_queues > bp->max_tx_rings ||
1073             eth_dev->data->nb_rx_queues + eth_dev->data->nb_tx_queues
1074                 + BNXT_NUM_ASYNC_CPR(bp) > bp->max_cp_rings ||
1075             eth_dev->data->nb_rx_queues + eth_dev->data->nb_tx_queues >
1076             bp->max_stat_ctx)
1077                 goto resource_error;
1078
1079         if (BNXT_HAS_RING_GRPS(bp) &&
1080             (uint32_t)(eth_dev->data->nb_rx_queues) > bp->max_ring_grps)
1081                 goto resource_error;
1082
1083         if (!(eth_dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_RSS) &&
1084             bp->max_vnics < eth_dev->data->nb_rx_queues)
1085                 goto resource_error;
1086
1087         bp->rx_cp_nr_rings = bp->rx_nr_rings;
1088         bp->tx_cp_nr_rings = bp->tx_nr_rings;
1089
1090         if (eth_dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG)
1091                 rx_offloads |= DEV_RX_OFFLOAD_RSS_HASH;
1092         eth_dev->data->dev_conf.rxmode.offloads = rx_offloads;
1093
1094         if (rx_offloads & DEV_RX_OFFLOAD_JUMBO_FRAME) {
1095                 eth_dev->data->mtu =
1096                         eth_dev->data->dev_conf.rxmode.max_rx_pkt_len -
1097                         RTE_ETHER_HDR_LEN - RTE_ETHER_CRC_LEN - VLAN_TAG_SIZE *
1098                         BNXT_NUM_VLANS;
1099                 bnxt_mtu_set_op(eth_dev, eth_dev->data->mtu);
1100         }
1101         return 0;
1102
1103 resource_error:
1104         PMD_DRV_LOG(ERR,
1105                     "Insufficient resources to support requested config\n");
1106         PMD_DRV_LOG(ERR,
1107                     "Num Queues Requested: Tx %d, Rx %d\n",
1108                     eth_dev->data->nb_tx_queues,
1109                     eth_dev->data->nb_rx_queues);
1110         PMD_DRV_LOG(ERR,
1111                     "MAX: TxQ %d, RxQ %d, CQ %d Stat %d, Grp %d, Vnic %d\n",
1112                     bp->max_tx_rings, bp->max_rx_rings, bp->max_cp_rings,
1113                     bp->max_stat_ctx, bp->max_ring_grps, bp->max_vnics);
1114         return -ENOSPC;
1115 }
1116
1117 void bnxt_print_link_info(struct rte_eth_dev *eth_dev)
1118 {
1119         struct rte_eth_link *link = &eth_dev->data->dev_link;
1120
1121         if (link->link_status)
1122                 PMD_DRV_LOG(INFO, "Port %d Link Up - speed %u Mbps - %s\n",
1123                         eth_dev->data->port_id,
1124                         (uint32_t)link->link_speed,
1125                         (link->link_duplex == ETH_LINK_FULL_DUPLEX) ?
1126                         ("full-duplex") : ("half-duplex\n"));
1127         else
1128                 PMD_DRV_LOG(INFO, "Port %d Link Down\n",
1129                         eth_dev->data->port_id);
1130 }
1131
1132 /*
1133  * Determine whether the current configuration requires support for scattered
1134  * receive; return 1 if scattered receive is required and 0 if not.
1135  */
1136 static int bnxt_scattered_rx(struct rte_eth_dev *eth_dev)
1137 {
1138         uint16_t buf_size;
1139         int i;
1140
1141         if (eth_dev->data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_SCATTER)
1142                 return 1;
1143
1144         if (eth_dev->data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_TCP_LRO)
1145                 return 1;
1146
1147         for (i = 0; i < eth_dev->data->nb_rx_queues; i++) {
1148                 struct bnxt_rx_queue *rxq = eth_dev->data->rx_queues[i];
1149
1150                 buf_size = (uint16_t)(rte_pktmbuf_data_room_size(rxq->mb_pool) -
1151                                       RTE_PKTMBUF_HEADROOM);
1152                 if (eth_dev->data->dev_conf.rxmode.max_rx_pkt_len > buf_size)
1153                         return 1;
1154         }
1155         return 0;
1156 }
1157
1158 static eth_rx_burst_t
1159 bnxt_receive_function(struct rte_eth_dev *eth_dev)
1160 {
1161         struct bnxt *bp = eth_dev->data->dev_private;
1162
1163         /* Disable vector mode RX for Stingray2 for now */
1164         if (BNXT_CHIP_SR2(bp)) {
1165                 bp->flags &= ~BNXT_FLAG_RX_VECTOR_PKT_MODE;
1166                 return bnxt_recv_pkts;
1167         }
1168
1169 #if defined(RTE_ARCH_X86) || defined(RTE_ARCH_ARM64)
1170 #ifndef RTE_LIBRTE_IEEE1588
1171         /*
1172          * Vector mode receive can be enabled only if scatter rx is not
1173          * in use and rx offloads are limited to VLAN stripping and
1174          * CRC stripping.
1175          */
1176         if (!eth_dev->data->scattered_rx &&
1177             !(eth_dev->data->dev_conf.rxmode.offloads &
1178               ~(DEV_RX_OFFLOAD_VLAN_STRIP |
1179                 DEV_RX_OFFLOAD_KEEP_CRC |
1180                 DEV_RX_OFFLOAD_JUMBO_FRAME |
1181                 DEV_RX_OFFLOAD_IPV4_CKSUM |
1182                 DEV_RX_OFFLOAD_UDP_CKSUM |
1183                 DEV_RX_OFFLOAD_TCP_CKSUM |
1184                 DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM |
1185                 DEV_RX_OFFLOAD_OUTER_UDP_CKSUM |
1186                 DEV_RX_OFFLOAD_RSS_HASH |
1187                 DEV_RX_OFFLOAD_VLAN_FILTER)) &&
1188             !BNXT_TRUFLOW_EN(bp) && BNXT_NUM_ASYNC_CPR(bp) &&
1189             rte_vect_get_max_simd_bitwidth() >= RTE_VECT_SIMD_128) {
1190                 PMD_DRV_LOG(INFO, "Using vector mode receive for port %d\n",
1191                             eth_dev->data->port_id);
1192                 bp->flags |= BNXT_FLAG_RX_VECTOR_PKT_MODE;
1193                 return bnxt_recv_pkts_vec;
1194         }
1195         PMD_DRV_LOG(INFO, "Vector mode receive disabled for port %d\n",
1196                     eth_dev->data->port_id);
1197         PMD_DRV_LOG(INFO,
1198                     "Port %d scatter: %d rx offload: %" PRIX64 "\n",
1199                     eth_dev->data->port_id,
1200                     eth_dev->data->scattered_rx,
1201                     eth_dev->data->dev_conf.rxmode.offloads);
1202 #endif
1203 #endif
1204         bp->flags &= ~BNXT_FLAG_RX_VECTOR_PKT_MODE;
1205         return bnxt_recv_pkts;
1206 }
1207
1208 static eth_tx_burst_t
1209 bnxt_transmit_function(struct rte_eth_dev *eth_dev)
1210 {
1211         struct bnxt *bp = eth_dev->data->dev_private;
1212
1213         /* Disable vector mode TX for Stingray2 for now */
1214         if (BNXT_CHIP_SR2(bp))
1215                 return bnxt_xmit_pkts;
1216
1217 #if defined(RTE_ARCH_X86) || defined(RTE_ARCH_ARM64)
1218 #ifndef RTE_LIBRTE_IEEE1588
1219         uint64_t offloads = eth_dev->data->dev_conf.txmode.offloads;
1220
1221         /*
1222          * Vector mode transmit can be enabled only if not using scatter rx
1223          * or tx offloads.
1224          */
1225         if (!eth_dev->data->scattered_rx &&
1226             !(offloads & ~DEV_TX_OFFLOAD_MBUF_FAST_FREE) &&
1227             !BNXT_TRUFLOW_EN(bp) &&
1228             rte_vect_get_max_simd_bitwidth() >= RTE_VECT_SIMD_128) {
1229                 PMD_DRV_LOG(INFO, "Using vector mode transmit for port %d\n",
1230                             eth_dev->data->port_id);
1231                 return bnxt_xmit_pkts_vec;
1232         }
1233         PMD_DRV_LOG(INFO, "Vector mode transmit disabled for port %d\n",
1234                     eth_dev->data->port_id);
1235         PMD_DRV_LOG(INFO,
1236                     "Port %d scatter: %d tx offload: %" PRIX64 "\n",
1237                     eth_dev->data->port_id,
1238                     eth_dev->data->scattered_rx,
1239                     offloads);
1240 #endif
1241 #endif
1242         return bnxt_xmit_pkts;
1243 }
1244
1245 static int bnxt_handle_if_change_status(struct bnxt *bp)
1246 {
1247         int rc;
1248
1249         /* Since fw has undergone a reset and lost all contexts,
1250          * set fatal flag to not issue hwrm during cleanup
1251          */
1252         bp->flags |= BNXT_FLAG_FATAL_ERROR;
1253         bnxt_uninit_resources(bp, true);
1254
1255         /* clear fatal flag so that re-init happens */
1256         bp->flags &= ~BNXT_FLAG_FATAL_ERROR;
1257         rc = bnxt_init_resources(bp, true);
1258
1259         bp->flags &= ~BNXT_FLAG_IF_CHANGE_HOT_FW_RESET_DONE;
1260
1261         return rc;
1262 }
1263
1264 static int bnxt_dev_set_link_up_op(struct rte_eth_dev *eth_dev)
1265 {
1266         struct bnxt *bp = eth_dev->data->dev_private;
1267         int rc = 0;
1268
1269         if (!BNXT_SINGLE_PF(bp))
1270                 return -ENOTSUP;
1271
1272         if (!bp->link_info->link_up)
1273                 rc = bnxt_set_hwrm_link_config(bp, true);
1274         if (!rc)
1275                 eth_dev->data->dev_link.link_status = 1;
1276
1277         bnxt_print_link_info(eth_dev);
1278         return rc;
1279 }
1280
1281 static int bnxt_dev_set_link_down_op(struct rte_eth_dev *eth_dev)
1282 {
1283         struct bnxt *bp = eth_dev->data->dev_private;
1284
1285         if (!BNXT_SINGLE_PF(bp))
1286                 return -ENOTSUP;
1287
1288         eth_dev->data->dev_link.link_status = 0;
1289         bnxt_set_hwrm_link_config(bp, false);
1290         bp->link_info->link_up = 0;
1291
1292         return 0;
1293 }
1294
1295 static void bnxt_free_switch_domain(struct bnxt *bp)
1296 {
1297         int rc = 0;
1298
1299         if (bp->switch_domain_id) {
1300                 rc = rte_eth_switch_domain_free(bp->switch_domain_id);
1301                 if (rc)
1302                         PMD_DRV_LOG(ERR, "free switch domain:%d fail: %d\n",
1303                                     bp->switch_domain_id, rc);
1304         }
1305 }
1306
1307 static void bnxt_ptp_get_current_time(void *arg)
1308 {
1309         struct bnxt *bp = arg;
1310         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
1311         int rc;
1312
1313         rc = is_bnxt_in_error(bp);
1314         if (rc)
1315                 return;
1316
1317         if (!ptp)
1318                 return;
1319
1320         bnxt_hwrm_port_ts_query(bp, BNXT_PTP_FLAGS_CURRENT_TIME,
1321                                 &ptp->current_time);
1322
1323         rc = rte_eal_alarm_set(US_PER_S, bnxt_ptp_get_current_time, (void *)bp);
1324         if (rc != 0) {
1325                 PMD_DRV_LOG(ERR, "Failed to re-schedule PTP alarm\n");
1326                 bp->flags2 &= ~BNXT_FLAGS2_PTP_ALARM_SCHEDULED;
1327         }
1328 }
1329
1330 static int bnxt_schedule_ptp_alarm(struct bnxt *bp)
1331 {
1332         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
1333         int rc;
1334
1335         if (bp->flags2 & BNXT_FLAGS2_PTP_ALARM_SCHEDULED)
1336                 return 0;
1337
1338         bnxt_hwrm_port_ts_query(bp, BNXT_PTP_FLAGS_CURRENT_TIME,
1339                                 &ptp->current_time);
1340
1341         rc = rte_eal_alarm_set(US_PER_S, bnxt_ptp_get_current_time, (void *)bp);
1342         return rc;
1343 }
1344
1345 static void bnxt_cancel_ptp_alarm(struct bnxt *bp)
1346 {
1347         if (bp->flags2 & BNXT_FLAGS2_PTP_ALARM_SCHEDULED) {
1348                 rte_eal_alarm_cancel(bnxt_ptp_get_current_time, (void *)bp);
1349                 bp->flags2 &= ~BNXT_FLAGS2_PTP_ALARM_SCHEDULED;
1350         }
1351 }
1352
1353 static void bnxt_ptp_stop(struct bnxt *bp)
1354 {
1355         bnxt_cancel_ptp_alarm(bp);
1356         bp->flags2 &= ~BNXT_FLAGS2_PTP_TIMESYNC_ENABLED;
1357 }
1358
1359 static int bnxt_ptp_start(struct bnxt *bp)
1360 {
1361         int rc;
1362
1363         rc = bnxt_schedule_ptp_alarm(bp);
1364         if (rc != 0) {
1365                 PMD_DRV_LOG(ERR, "Failed to schedule PTP alarm\n");
1366         } else {
1367                 bp->flags2 |= BNXT_FLAGS2_PTP_TIMESYNC_ENABLED;
1368                 bp->flags2 |= BNXT_FLAGS2_PTP_ALARM_SCHEDULED;
1369         }
1370
1371         return rc;
1372 }
1373
1374 static int bnxt_dev_stop(struct rte_eth_dev *eth_dev)
1375 {
1376         struct bnxt *bp = eth_dev->data->dev_private;
1377         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1378         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1379         struct rte_eth_link link;
1380         int ret;
1381
1382         eth_dev->data->dev_started = 0;
1383         eth_dev->data->scattered_rx = 0;
1384
1385         /* Prevent crashes when queues are still in use */
1386         eth_dev->rx_pkt_burst = &bnxt_dummy_recv_pkts;
1387         eth_dev->tx_pkt_burst = &bnxt_dummy_xmit_pkts;
1388
1389         bnxt_disable_int(bp);
1390
1391         /* disable uio/vfio intr/eventfd mapping */
1392         rte_intr_disable(intr_handle);
1393
1394         /* Stop the child representors for this device */
1395         ret = bnxt_rep_stop_all(bp);
1396         if (ret != 0)
1397                 return ret;
1398
1399         /* delete the bnxt ULP port details */
1400         bnxt_ulp_port_deinit(bp);
1401
1402         bnxt_cancel_fw_health_check(bp);
1403
1404         if (BNXT_P5_PTP_TIMESYNC_ENABLED(bp))
1405                 bnxt_cancel_ptp_alarm(bp);
1406
1407         /* Do not bring link down during reset recovery */
1408         if (!is_bnxt_in_error(bp)) {
1409                 bnxt_dev_set_link_down_op(eth_dev);
1410                 /* Wait for link to be reset */
1411                 if (BNXT_SINGLE_PF(bp))
1412                         rte_delay_ms(500);
1413                 /* clear the recorded link status */
1414                 memset(&link, 0, sizeof(link));
1415                 rte_eth_linkstatus_set(eth_dev, &link);
1416         }
1417
1418         /* Clean queue intr-vector mapping */
1419         rte_intr_efd_disable(intr_handle);
1420         if (intr_handle->intr_vec != NULL) {
1421                 rte_free(intr_handle->intr_vec);
1422                 intr_handle->intr_vec = NULL;
1423         }
1424
1425         bnxt_hwrm_port_clr_stats(bp);
1426         bnxt_free_tx_mbufs(bp);
1427         bnxt_free_rx_mbufs(bp);
1428         /* Process any remaining notifications in default completion queue */
1429         bnxt_int_handler(eth_dev);
1430         bnxt_shutdown_nic(bp);
1431         bnxt_hwrm_if_change(bp, false);
1432
1433         rte_free(bp->mark_table);
1434         bp->mark_table = NULL;
1435
1436         bp->flags &= ~BNXT_FLAG_RX_VECTOR_PKT_MODE;
1437         bp->rx_cosq_cnt = 0;
1438         /* All filters are deleted on a port stop. */
1439         if (BNXT_FLOW_XSTATS_EN(bp))
1440                 bp->flow_stat->flow_count = 0;
1441
1442         return 0;
1443 }
1444
1445 /* Unload the driver, release resources */
1446 static int bnxt_dev_stop_op(struct rte_eth_dev *eth_dev)
1447 {
1448         struct bnxt *bp = eth_dev->data->dev_private;
1449
1450         pthread_mutex_lock(&bp->err_recovery_lock);
1451         if (bp->flags & BNXT_FLAG_FW_RESET) {
1452                 PMD_DRV_LOG(ERR,
1453                             "Adapter recovering from error..Please retry\n");
1454                 pthread_mutex_unlock(&bp->err_recovery_lock);
1455                 return -EAGAIN;
1456         }
1457         pthread_mutex_unlock(&bp->err_recovery_lock);
1458
1459         return bnxt_dev_stop(eth_dev);
1460 }
1461
1462 static int bnxt_dev_start_op(struct rte_eth_dev *eth_dev)
1463 {
1464         struct bnxt *bp = eth_dev->data->dev_private;
1465         uint64_t rx_offloads = eth_dev->data->dev_conf.rxmode.offloads;
1466         int vlan_mask = 0;
1467         int rc, retry_cnt = BNXT_IF_CHANGE_RETRY_COUNT;
1468
1469         if (!eth_dev->data->nb_tx_queues || !eth_dev->data->nb_rx_queues) {
1470                 PMD_DRV_LOG(ERR, "Queues are not configured yet!\n");
1471                 return -EINVAL;
1472         }
1473
1474         if (bp->rx_cp_nr_rings > RTE_ETHDEV_QUEUE_STAT_CNTRS)
1475                 PMD_DRV_LOG(ERR,
1476                             "RxQ cnt %d > RTE_ETHDEV_QUEUE_STAT_CNTRS %d\n",
1477                             bp->rx_cp_nr_rings, RTE_ETHDEV_QUEUE_STAT_CNTRS);
1478
1479         do {
1480                 rc = bnxt_hwrm_if_change(bp, true);
1481                 if (rc == 0 || rc != -EAGAIN)
1482                         break;
1483
1484                 rte_delay_ms(BNXT_IF_CHANGE_RETRY_INTERVAL);
1485         } while (retry_cnt--);
1486
1487         if (rc)
1488                 return rc;
1489
1490         if (bp->flags & BNXT_FLAG_IF_CHANGE_HOT_FW_RESET_DONE) {
1491                 rc = bnxt_handle_if_change_status(bp);
1492                 if (rc)
1493                         return rc;
1494         }
1495
1496         bnxt_enable_int(bp);
1497
1498         eth_dev->data->scattered_rx = bnxt_scattered_rx(eth_dev);
1499
1500         rc = bnxt_start_nic(bp);
1501         if (rc)
1502                 goto error;
1503
1504         eth_dev->data->dev_started = 1;
1505
1506         bnxt_link_update_op(eth_dev, 1);
1507
1508         if (rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER)
1509                 vlan_mask |= ETH_VLAN_FILTER_MASK;
1510         if (rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
1511                 vlan_mask |= ETH_VLAN_STRIP_MASK;
1512         rc = bnxt_vlan_offload_set_op(eth_dev, vlan_mask);
1513         if (rc)
1514                 goto error;
1515
1516         /* Initialize bnxt ULP port details */
1517         rc = bnxt_ulp_port_init(bp);
1518         if (rc)
1519                 goto error;
1520
1521         eth_dev->rx_pkt_burst = bnxt_receive_function(eth_dev);
1522         eth_dev->tx_pkt_burst = bnxt_transmit_function(eth_dev);
1523
1524         bnxt_schedule_fw_health_check(bp);
1525
1526         if (BNXT_P5_PTP_TIMESYNC_ENABLED(bp))
1527                 bnxt_schedule_ptp_alarm(bp);
1528
1529         return 0;
1530
1531 error:
1532         bnxt_dev_stop(eth_dev);
1533         return rc;
1534 }
1535
1536 static void
1537 bnxt_uninit_locks(struct bnxt *bp)
1538 {
1539         pthread_mutex_destroy(&bp->flow_lock);
1540         pthread_mutex_destroy(&bp->def_cp_lock);
1541         pthread_mutex_destroy(&bp->health_check_lock);
1542         pthread_mutex_destroy(&bp->err_recovery_lock);
1543         if (bp->rep_info) {
1544                 pthread_mutex_destroy(&bp->rep_info->vfr_lock);
1545                 pthread_mutex_destroy(&bp->rep_info->vfr_start_lock);
1546         }
1547 }
1548
1549 static void bnxt_drv_uninit(struct bnxt *bp)
1550 {
1551         bnxt_free_switch_domain(bp);
1552         bnxt_free_leds_info(bp);
1553         bnxt_free_cos_queues(bp);
1554         bnxt_free_link_info(bp);
1555         bnxt_free_pf_info(bp);
1556         bnxt_free_parent_info(bp);
1557         bnxt_uninit_locks(bp);
1558
1559         rte_memzone_free((const struct rte_memzone *)bp->tx_mem_zone);
1560         bp->tx_mem_zone = NULL;
1561         rte_memzone_free((const struct rte_memzone *)bp->rx_mem_zone);
1562         bp->rx_mem_zone = NULL;
1563
1564         bnxt_free_vf_info(bp);
1565
1566         rte_free(bp->grp_info);
1567         bp->grp_info = NULL;
1568 }
1569
1570 static int bnxt_dev_close_op(struct rte_eth_dev *eth_dev)
1571 {
1572         struct bnxt *bp = eth_dev->data->dev_private;
1573         int ret = 0;
1574
1575         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1576                 return 0;
1577
1578         pthread_mutex_lock(&bp->err_recovery_lock);
1579         if (bp->flags & BNXT_FLAG_FW_RESET) {
1580                 PMD_DRV_LOG(ERR,
1581                             "Adapter recovering from error...Please retry\n");
1582                 pthread_mutex_unlock(&bp->err_recovery_lock);
1583                 return -EAGAIN;
1584         }
1585         pthread_mutex_unlock(&bp->err_recovery_lock);
1586
1587         /* cancel the recovery handler before remove dev */
1588         rte_eal_alarm_cancel(bnxt_dev_reset_and_resume, (void *)bp);
1589         rte_eal_alarm_cancel(bnxt_dev_recover, (void *)bp);
1590         bnxt_cancel_fc_thread(bp);
1591
1592         if (eth_dev->data->dev_started)
1593                 ret = bnxt_dev_stop(eth_dev);
1594
1595         bnxt_uninit_resources(bp, false);
1596
1597         bnxt_drv_uninit(bp);
1598
1599         return ret;
1600 }
1601
1602 static void bnxt_mac_addr_remove_op(struct rte_eth_dev *eth_dev,
1603                                     uint32_t index)
1604 {
1605         struct bnxt *bp = eth_dev->data->dev_private;
1606         uint64_t pool_mask = eth_dev->data->mac_pool_sel[index];
1607         struct bnxt_vnic_info *vnic;
1608         struct bnxt_filter_info *filter, *temp_filter;
1609         uint32_t i;
1610
1611         if (is_bnxt_in_error(bp))
1612                 return;
1613
1614         /*
1615          * Loop through all VNICs from the specified filter flow pools to
1616          * remove the corresponding MAC addr filter
1617          */
1618         for (i = 0; i < bp->nr_vnics; i++) {
1619                 if (!(pool_mask & (1ULL << i)))
1620                         continue;
1621
1622                 vnic = &bp->vnic_info[i];
1623                 filter = STAILQ_FIRST(&vnic->filter);
1624                 while (filter) {
1625                         temp_filter = STAILQ_NEXT(filter, next);
1626                         if (filter->mac_index == index) {
1627                                 STAILQ_REMOVE(&vnic->filter, filter,
1628                                                 bnxt_filter_info, next);
1629                                 bnxt_hwrm_clear_l2_filter(bp, filter);
1630                                 bnxt_free_filter(bp, filter);
1631                         }
1632                         filter = temp_filter;
1633                 }
1634         }
1635 }
1636
1637 static int bnxt_add_mac_filter(struct bnxt *bp, struct bnxt_vnic_info *vnic,
1638                                struct rte_ether_addr *mac_addr, uint32_t index,
1639                                uint32_t pool)
1640 {
1641         struct bnxt_filter_info *filter;
1642         int rc = 0;
1643
1644         /* Attach requested MAC address to the new l2_filter */
1645         STAILQ_FOREACH(filter, &vnic->filter, next) {
1646                 if (filter->mac_index == index) {
1647                         PMD_DRV_LOG(DEBUG,
1648                                     "MAC addr already existed for pool %d\n",
1649                                     pool);
1650                         return 0;
1651                 }
1652         }
1653
1654         filter = bnxt_alloc_filter(bp);
1655         if (!filter) {
1656                 PMD_DRV_LOG(ERR, "L2 filter alloc failed\n");
1657                 return -ENODEV;
1658         }
1659
1660         /* bnxt_alloc_filter copies default MAC to filter->l2_addr. So,
1661          * if the MAC that's been programmed now is a different one, then,
1662          * copy that addr to filter->l2_addr
1663          */
1664         if (mac_addr)
1665                 memcpy(filter->l2_addr, mac_addr, RTE_ETHER_ADDR_LEN);
1666         filter->flags |= HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_OUTERMOST;
1667
1668         rc = bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id, filter);
1669         if (!rc) {
1670                 filter->mac_index = index;
1671                 if (filter->mac_index == 0)
1672                         STAILQ_INSERT_HEAD(&vnic->filter, filter, next);
1673                 else
1674                         STAILQ_INSERT_TAIL(&vnic->filter, filter, next);
1675         } else {
1676                 bnxt_free_filter(bp, filter);
1677         }
1678
1679         return rc;
1680 }
1681
1682 static int bnxt_mac_addr_add_op(struct rte_eth_dev *eth_dev,
1683                                 struct rte_ether_addr *mac_addr,
1684                                 uint32_t index, uint32_t pool)
1685 {
1686         struct bnxt *bp = eth_dev->data->dev_private;
1687         struct bnxt_vnic_info *vnic = &bp->vnic_info[pool];
1688         int rc = 0;
1689
1690         rc = is_bnxt_in_error(bp);
1691         if (rc)
1692                 return rc;
1693
1694         if (BNXT_VF(bp) && !BNXT_VF_IS_TRUSTED(bp)) {
1695                 PMD_DRV_LOG(ERR, "Cannot add MAC address to a VF interface\n");
1696                 return -ENOTSUP;
1697         }
1698
1699         if (!vnic) {
1700                 PMD_DRV_LOG(ERR, "VNIC not found for pool %d!\n", pool);
1701                 return -EINVAL;
1702         }
1703
1704         /* Filter settings will get applied when port is started */
1705         if (!eth_dev->data->dev_started)
1706                 return 0;
1707
1708         rc = bnxt_add_mac_filter(bp, vnic, mac_addr, index, pool);
1709
1710         return rc;
1711 }
1712
1713 int bnxt_link_update_op(struct rte_eth_dev *eth_dev, int wait_to_complete)
1714 {
1715         int rc = 0;
1716         struct bnxt *bp = eth_dev->data->dev_private;
1717         struct rte_eth_link new;
1718         int cnt = wait_to_complete ? BNXT_MAX_LINK_WAIT_CNT :
1719                         BNXT_MIN_LINK_WAIT_CNT;
1720
1721         rc = is_bnxt_in_error(bp);
1722         if (rc)
1723                 return rc;
1724
1725         memset(&new, 0, sizeof(new));
1726         do {
1727                 /* Retrieve link info from hardware */
1728                 rc = bnxt_get_hwrm_link_config(bp, &new);
1729                 if (rc) {
1730                         new.link_speed = ETH_LINK_SPEED_100M;
1731                         new.link_duplex = ETH_LINK_FULL_DUPLEX;
1732                         PMD_DRV_LOG(ERR,
1733                                 "Failed to retrieve link rc = 0x%x!\n", rc);
1734                         goto out;
1735                 }
1736
1737                 if (!wait_to_complete || new.link_status)
1738                         break;
1739
1740                 rte_delay_ms(BNXT_LINK_WAIT_INTERVAL);
1741         } while (cnt--);
1742
1743         /* Only single function PF can bring phy down.
1744          * When port is stopped, report link down for VF/MH/NPAR functions.
1745          */
1746         if (!BNXT_SINGLE_PF(bp) && !eth_dev->data->dev_started)
1747                 memset(&new, 0, sizeof(new));
1748
1749 out:
1750         /* Timed out or success */
1751         if (new.link_status != eth_dev->data->dev_link.link_status ||
1752             new.link_speed != eth_dev->data->dev_link.link_speed) {
1753                 rte_eth_linkstatus_set(eth_dev, &new);
1754
1755                 rte_eth_dev_callback_process(eth_dev,
1756                                              RTE_ETH_EVENT_INTR_LSC,
1757                                              NULL);
1758
1759                 bnxt_print_link_info(eth_dev);
1760         }
1761
1762         return rc;
1763 }
1764
1765 static int bnxt_promiscuous_enable_op(struct rte_eth_dev *eth_dev)
1766 {
1767         struct bnxt *bp = eth_dev->data->dev_private;
1768         struct bnxt_vnic_info *vnic;
1769         uint32_t old_flags;
1770         int rc;
1771
1772         rc = is_bnxt_in_error(bp);
1773         if (rc)
1774                 return rc;
1775
1776         /* Filter settings will get applied when port is started */
1777         if (!eth_dev->data->dev_started)
1778                 return 0;
1779
1780         if (bp->vnic_info == NULL)
1781                 return 0;
1782
1783         vnic = BNXT_GET_DEFAULT_VNIC(bp);
1784
1785         old_flags = vnic->flags;
1786         vnic->flags |= BNXT_VNIC_INFO_PROMISC;
1787         rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1788         if (rc != 0)
1789                 vnic->flags = old_flags;
1790
1791         return rc;
1792 }
1793
1794 static int bnxt_promiscuous_disable_op(struct rte_eth_dev *eth_dev)
1795 {
1796         struct bnxt *bp = eth_dev->data->dev_private;
1797         struct bnxt_vnic_info *vnic;
1798         uint32_t old_flags;
1799         int rc;
1800
1801         rc = is_bnxt_in_error(bp);
1802         if (rc)
1803                 return rc;
1804
1805         /* Filter settings will get applied when port is started */
1806         if (!eth_dev->data->dev_started)
1807                 return 0;
1808
1809         if (bp->vnic_info == NULL)
1810                 return 0;
1811
1812         vnic = BNXT_GET_DEFAULT_VNIC(bp);
1813
1814         old_flags = vnic->flags;
1815         vnic->flags &= ~BNXT_VNIC_INFO_PROMISC;
1816         rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1817         if (rc != 0)
1818                 vnic->flags = old_flags;
1819
1820         return rc;
1821 }
1822
1823 static int bnxt_allmulticast_enable_op(struct rte_eth_dev *eth_dev)
1824 {
1825         struct bnxt *bp = eth_dev->data->dev_private;
1826         struct bnxt_vnic_info *vnic;
1827         uint32_t old_flags;
1828         int rc;
1829
1830         rc = is_bnxt_in_error(bp);
1831         if (rc)
1832                 return rc;
1833
1834         /* Filter settings will get applied when port is started */
1835         if (!eth_dev->data->dev_started)
1836                 return 0;
1837
1838         if (bp->vnic_info == NULL)
1839                 return 0;
1840
1841         vnic = BNXT_GET_DEFAULT_VNIC(bp);
1842
1843         old_flags = vnic->flags;
1844         vnic->flags |= BNXT_VNIC_INFO_ALLMULTI;
1845         rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1846         if (rc != 0)
1847                 vnic->flags = old_flags;
1848
1849         return rc;
1850 }
1851
1852 static int bnxt_allmulticast_disable_op(struct rte_eth_dev *eth_dev)
1853 {
1854         struct bnxt *bp = eth_dev->data->dev_private;
1855         struct bnxt_vnic_info *vnic;
1856         uint32_t old_flags;
1857         int rc;
1858
1859         rc = is_bnxt_in_error(bp);
1860         if (rc)
1861                 return rc;
1862
1863         /* Filter settings will get applied when port is started */
1864         if (!eth_dev->data->dev_started)
1865                 return 0;
1866
1867         if (bp->vnic_info == NULL)
1868                 return 0;
1869
1870         vnic = BNXT_GET_DEFAULT_VNIC(bp);
1871
1872         old_flags = vnic->flags;
1873         vnic->flags &= ~BNXT_VNIC_INFO_ALLMULTI;
1874         rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1875         if (rc != 0)
1876                 vnic->flags = old_flags;
1877
1878         return rc;
1879 }
1880
1881 /* Return bnxt_rx_queue pointer corresponding to a given rxq. */
1882 static struct bnxt_rx_queue *bnxt_qid_to_rxq(struct bnxt *bp, uint16_t qid)
1883 {
1884         if (qid >= bp->rx_nr_rings)
1885                 return NULL;
1886
1887         return bp->eth_dev->data->rx_queues[qid];
1888 }
1889
1890 /* Return rxq corresponding to a given rss table ring/group ID. */
1891 static uint16_t bnxt_rss_to_qid(struct bnxt *bp, uint16_t fwr)
1892 {
1893         struct bnxt_rx_queue *rxq;
1894         unsigned int i;
1895
1896         if (!BNXT_HAS_RING_GRPS(bp)) {
1897                 for (i = 0; i < bp->rx_nr_rings; i++) {
1898                         rxq = bp->eth_dev->data->rx_queues[i];
1899                         if (rxq->rx_ring->rx_ring_struct->fw_ring_id == fwr)
1900                                 return rxq->index;
1901                 }
1902         } else {
1903                 for (i = 0; i < bp->rx_nr_rings; i++) {
1904                         if (bp->grp_info[i].fw_grp_id == fwr)
1905                                 return i;
1906                 }
1907         }
1908
1909         return INVALID_HW_RING_ID;
1910 }
1911
1912 static int bnxt_reta_update_op(struct rte_eth_dev *eth_dev,
1913                             struct rte_eth_rss_reta_entry64 *reta_conf,
1914                             uint16_t reta_size)
1915 {
1916         struct bnxt *bp = eth_dev->data->dev_private;
1917         struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
1918         struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp);
1919         uint16_t tbl_size = bnxt_rss_hash_tbl_size(bp);
1920         uint16_t idx, sft;
1921         int i, rc;
1922
1923         rc = is_bnxt_in_error(bp);
1924         if (rc)
1925                 return rc;
1926
1927         if (!vnic->rss_table)
1928                 return -EINVAL;
1929
1930         if (!(dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG))
1931                 return -EINVAL;
1932
1933         if (reta_size != tbl_size) {
1934                 PMD_DRV_LOG(ERR, "The configured hash table lookup size "
1935                         "(%d) must equal the size supported by the hardware "
1936                         "(%d)\n", reta_size, tbl_size);
1937                 return -EINVAL;
1938         }
1939
1940         for (i = 0; i < reta_size; i++) {
1941                 struct bnxt_rx_queue *rxq;
1942
1943                 idx = i / RTE_RETA_GROUP_SIZE;
1944                 sft = i % RTE_RETA_GROUP_SIZE;
1945
1946                 if (!(reta_conf[idx].mask & (1ULL << sft)))
1947                         continue;
1948
1949                 rxq = bnxt_qid_to_rxq(bp, reta_conf[idx].reta[sft]);
1950                 if (!rxq) {
1951                         PMD_DRV_LOG(ERR, "Invalid ring in reta_conf.\n");
1952                         return -EINVAL;
1953                 }
1954
1955                 if (BNXT_CHIP_P5(bp)) {
1956                         vnic->rss_table[i * 2] =
1957                                 rxq->rx_ring->rx_ring_struct->fw_ring_id;
1958                         vnic->rss_table[i * 2 + 1] =
1959                                 rxq->cp_ring->cp_ring_struct->fw_ring_id;
1960                 } else {
1961                         vnic->rss_table[i] =
1962                             vnic->fw_grp_ids[reta_conf[idx].reta[sft]];
1963                 }
1964         }
1965
1966         rc = bnxt_hwrm_vnic_rss_cfg(bp, vnic);
1967         return rc;
1968 }
1969
1970 static int bnxt_reta_query_op(struct rte_eth_dev *eth_dev,
1971                               struct rte_eth_rss_reta_entry64 *reta_conf,
1972                               uint16_t reta_size)
1973 {
1974         struct bnxt *bp = eth_dev->data->dev_private;
1975         struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp);
1976         uint16_t tbl_size = bnxt_rss_hash_tbl_size(bp);
1977         uint16_t idx, sft, i;
1978         int rc;
1979
1980         rc = is_bnxt_in_error(bp);
1981         if (rc)
1982                 return rc;
1983
1984         /* Retrieve from the default VNIC */
1985         if (!vnic)
1986                 return -EINVAL;
1987         if (!vnic->rss_table)
1988                 return -EINVAL;
1989
1990         if (reta_size != tbl_size) {
1991                 PMD_DRV_LOG(ERR, "The configured hash table lookup size "
1992                         "(%d) must equal the size supported by the hardware "
1993                         "(%d)\n", reta_size, tbl_size);
1994                 return -EINVAL;
1995         }
1996
1997         for (idx = 0, i = 0; i < reta_size; i++) {
1998                 idx = i / RTE_RETA_GROUP_SIZE;
1999                 sft = i % RTE_RETA_GROUP_SIZE;
2000
2001                 if (reta_conf[idx].mask & (1ULL << sft)) {
2002                         uint16_t qid;
2003
2004                         if (BNXT_CHIP_P5(bp))
2005                                 qid = bnxt_rss_to_qid(bp,
2006                                                       vnic->rss_table[i * 2]);
2007                         else
2008                                 qid = bnxt_rss_to_qid(bp, vnic->rss_table[i]);
2009
2010                         if (qid == INVALID_HW_RING_ID) {
2011                                 PMD_DRV_LOG(ERR, "Inv. entry in rss table.\n");
2012                                 return -EINVAL;
2013                         }
2014                         reta_conf[idx].reta[sft] = qid;
2015                 }
2016         }
2017
2018         return 0;
2019 }
2020
2021 static int bnxt_rss_hash_update_op(struct rte_eth_dev *eth_dev,
2022                                    struct rte_eth_rss_conf *rss_conf)
2023 {
2024         struct bnxt *bp = eth_dev->data->dev_private;
2025         struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
2026         struct bnxt_vnic_info *vnic;
2027         int rc;
2028
2029         rc = is_bnxt_in_error(bp);
2030         if (rc)
2031                 return rc;
2032
2033         /*
2034          * If RSS enablement were different than dev_configure,
2035          * then return -EINVAL
2036          */
2037         if (dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG) {
2038                 if (!rss_conf->rss_hf)
2039                         PMD_DRV_LOG(ERR, "Hash type NONE\n");
2040         } else {
2041                 if (rss_conf->rss_hf & BNXT_ETH_RSS_SUPPORT)
2042                         return -EINVAL;
2043         }
2044
2045         bp->flags |= BNXT_FLAG_UPDATE_HASH;
2046         memcpy(&eth_dev->data->dev_conf.rx_adv_conf.rss_conf,
2047                rss_conf,
2048                sizeof(*rss_conf));
2049
2050         /* Update the default RSS VNIC(s) */
2051         vnic = BNXT_GET_DEFAULT_VNIC(bp);
2052         vnic->hash_type = bnxt_rte_to_hwrm_hash_types(rss_conf->rss_hf);
2053         vnic->hash_mode =
2054                 bnxt_rte_to_hwrm_hash_level(bp, rss_conf->rss_hf,
2055                                             ETH_RSS_LEVEL(rss_conf->rss_hf));
2056
2057         /*
2058          * If hashkey is not specified, use the previously configured
2059          * hashkey
2060          */
2061         if (!rss_conf->rss_key)
2062                 goto rss_config;
2063
2064         if (rss_conf->rss_key_len != HW_HASH_KEY_SIZE) {
2065                 PMD_DRV_LOG(ERR,
2066                             "Invalid hashkey length, should be 16 bytes\n");
2067                 return -EINVAL;
2068         }
2069         memcpy(vnic->rss_hash_key, rss_conf->rss_key, rss_conf->rss_key_len);
2070
2071 rss_config:
2072         rc = bnxt_hwrm_vnic_rss_cfg(bp, vnic);
2073         return rc;
2074 }
2075
2076 static int bnxt_rss_hash_conf_get_op(struct rte_eth_dev *eth_dev,
2077                                      struct rte_eth_rss_conf *rss_conf)
2078 {
2079         struct bnxt *bp = eth_dev->data->dev_private;
2080         struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp);
2081         int len, rc;
2082         uint32_t hash_types;
2083
2084         rc = is_bnxt_in_error(bp);
2085         if (rc)
2086                 return rc;
2087
2088         /* RSS configuration is the same for all VNICs */
2089         if (vnic && vnic->rss_hash_key) {
2090                 if (rss_conf->rss_key) {
2091                         len = rss_conf->rss_key_len <= HW_HASH_KEY_SIZE ?
2092                               rss_conf->rss_key_len : HW_HASH_KEY_SIZE;
2093                         memcpy(rss_conf->rss_key, vnic->rss_hash_key, len);
2094                 }
2095
2096                 hash_types = vnic->hash_type;
2097                 rss_conf->rss_hf = 0;
2098                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV4) {
2099                         rss_conf->rss_hf |= ETH_RSS_IPV4;
2100                         hash_types &= ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV4;
2101                 }
2102                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV4) {
2103                         rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP;
2104                         hash_types &=
2105                                 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV4;
2106                 }
2107                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV4) {
2108                         rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
2109                         hash_types &=
2110                                 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV4;
2111                 }
2112                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6) {
2113                         rss_conf->rss_hf |= ETH_RSS_IPV6;
2114                         hash_types &= ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6;
2115                 }
2116                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV6) {
2117                         rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV6_TCP;
2118                         hash_types &=
2119                                 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV6;
2120                 }
2121                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV6) {
2122                         rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;
2123                         hash_types &=
2124                                 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV6;
2125                 }
2126
2127                 rss_conf->rss_hf |=
2128                         bnxt_hwrm_to_rte_rss_level(bp, vnic->hash_mode);
2129
2130                 if (hash_types) {
2131                         PMD_DRV_LOG(ERR,
2132                                 "Unknown RSS config from firmware (%08x), RSS disabled",
2133                                 vnic->hash_type);
2134                         return -ENOTSUP;
2135                 }
2136         } else {
2137                 rss_conf->rss_hf = 0;
2138         }
2139         return 0;
2140 }
2141
2142 static int bnxt_flow_ctrl_get_op(struct rte_eth_dev *dev,
2143                                struct rte_eth_fc_conf *fc_conf)
2144 {
2145         struct bnxt *bp = dev->data->dev_private;
2146         struct rte_eth_link link_info;
2147         int rc;
2148
2149         rc = is_bnxt_in_error(bp);
2150         if (rc)
2151                 return rc;
2152
2153         rc = bnxt_get_hwrm_link_config(bp, &link_info);
2154         if (rc)
2155                 return rc;
2156
2157         memset(fc_conf, 0, sizeof(*fc_conf));
2158         if (bp->link_info->auto_pause)
2159                 fc_conf->autoneg = 1;
2160         switch (bp->link_info->pause) {
2161         case 0:
2162                 fc_conf->mode = RTE_FC_NONE;
2163                 break;
2164         case HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_TX:
2165                 fc_conf->mode = RTE_FC_TX_PAUSE;
2166                 break;
2167         case HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_RX:
2168                 fc_conf->mode = RTE_FC_RX_PAUSE;
2169                 break;
2170         case (HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_TX |
2171                         HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_RX):
2172                 fc_conf->mode = RTE_FC_FULL;
2173                 break;
2174         }
2175         return 0;
2176 }
2177
2178 static int bnxt_flow_ctrl_set_op(struct rte_eth_dev *dev,
2179                                struct rte_eth_fc_conf *fc_conf)
2180 {
2181         struct bnxt *bp = dev->data->dev_private;
2182         int rc;
2183
2184         rc = is_bnxt_in_error(bp);
2185         if (rc)
2186                 return rc;
2187
2188         if (!BNXT_SINGLE_PF(bp) || BNXT_VF(bp)) {
2189                 PMD_DRV_LOG(ERR, "Flow Control Settings cannot be modified\n");
2190                 return -ENOTSUP;
2191         }
2192
2193         switch (fc_conf->mode) {
2194         case RTE_FC_NONE:
2195                 bp->link_info->auto_pause = 0;
2196                 bp->link_info->force_pause = 0;
2197                 break;
2198         case RTE_FC_RX_PAUSE:
2199                 if (fc_conf->autoneg) {
2200                         bp->link_info->auto_pause =
2201                                         HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_RX;
2202                         bp->link_info->force_pause = 0;
2203                 } else {
2204                         bp->link_info->auto_pause = 0;
2205                         bp->link_info->force_pause =
2206                                         HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_RX;
2207                 }
2208                 break;
2209         case RTE_FC_TX_PAUSE:
2210                 if (fc_conf->autoneg) {
2211                         bp->link_info->auto_pause =
2212                                         HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_TX;
2213                         bp->link_info->force_pause = 0;
2214                 } else {
2215                         bp->link_info->auto_pause = 0;
2216                         bp->link_info->force_pause =
2217                                         HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_TX;
2218                 }
2219                 break;
2220         case RTE_FC_FULL:
2221                 if (fc_conf->autoneg) {
2222                         bp->link_info->auto_pause =
2223                                         HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_TX |
2224                                         HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_RX;
2225                         bp->link_info->force_pause = 0;
2226                 } else {
2227                         bp->link_info->auto_pause = 0;
2228                         bp->link_info->force_pause =
2229                                         HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_TX |
2230                                         HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_RX;
2231                 }
2232                 break;
2233         }
2234         return bnxt_set_hwrm_link_config(bp, true);
2235 }
2236
2237 /* Add UDP tunneling port */
2238 static int
2239 bnxt_udp_tunnel_port_add_op(struct rte_eth_dev *eth_dev,
2240                          struct rte_eth_udp_tunnel *udp_tunnel)
2241 {
2242         struct bnxt *bp = eth_dev->data->dev_private;
2243         uint16_t tunnel_type = 0;
2244         int rc = 0;
2245
2246         rc = is_bnxt_in_error(bp);
2247         if (rc)
2248                 return rc;
2249
2250         switch (udp_tunnel->prot_type) {
2251         case RTE_TUNNEL_TYPE_VXLAN:
2252                 if (bp->vxlan_port_cnt) {
2253                         PMD_DRV_LOG(ERR, "Tunnel Port %d already programmed\n",
2254                                 udp_tunnel->udp_port);
2255                         if (bp->vxlan_port != udp_tunnel->udp_port) {
2256                                 PMD_DRV_LOG(ERR, "Only one port allowed\n");
2257                                 return -ENOSPC;
2258                         }
2259                         bp->vxlan_port_cnt++;
2260                         return 0;
2261                 }
2262                 tunnel_type =
2263                         HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_VXLAN;
2264                 bp->vxlan_port_cnt++;
2265                 break;
2266         case RTE_TUNNEL_TYPE_GENEVE:
2267                 if (bp->geneve_port_cnt) {
2268                         PMD_DRV_LOG(ERR, "Tunnel Port %d already programmed\n",
2269                                 udp_tunnel->udp_port);
2270                         if (bp->geneve_port != udp_tunnel->udp_port) {
2271                                 PMD_DRV_LOG(ERR, "Only one port allowed\n");
2272                                 return -ENOSPC;
2273                         }
2274                         bp->geneve_port_cnt++;
2275                         return 0;
2276                 }
2277                 tunnel_type =
2278                         HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_GENEVE;
2279                 bp->geneve_port_cnt++;
2280                 break;
2281         default:
2282                 PMD_DRV_LOG(ERR, "Tunnel type is not supported\n");
2283                 return -ENOTSUP;
2284         }
2285         rc = bnxt_hwrm_tunnel_dst_port_alloc(bp, udp_tunnel->udp_port,
2286                                              tunnel_type);
2287         return rc;
2288 }
2289
2290 static int
2291 bnxt_udp_tunnel_port_del_op(struct rte_eth_dev *eth_dev,
2292                          struct rte_eth_udp_tunnel *udp_tunnel)
2293 {
2294         struct bnxt *bp = eth_dev->data->dev_private;
2295         uint16_t tunnel_type = 0;
2296         uint16_t port = 0;
2297         int rc = 0;
2298
2299         rc = is_bnxt_in_error(bp);
2300         if (rc)
2301                 return rc;
2302
2303         switch (udp_tunnel->prot_type) {
2304         case RTE_TUNNEL_TYPE_VXLAN:
2305                 if (!bp->vxlan_port_cnt) {
2306                         PMD_DRV_LOG(ERR, "No Tunnel port configured yet\n");
2307                         return -EINVAL;
2308                 }
2309                 if (bp->vxlan_port != udp_tunnel->udp_port) {
2310                         PMD_DRV_LOG(ERR, "Req Port: %d. Configured port: %d\n",
2311                                 udp_tunnel->udp_port, bp->vxlan_port);
2312                         return -EINVAL;
2313                 }
2314                 if (--bp->vxlan_port_cnt)
2315                         return 0;
2316
2317                 tunnel_type =
2318                         HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN;
2319                 port = bp->vxlan_fw_dst_port_id;
2320                 break;
2321         case RTE_TUNNEL_TYPE_GENEVE:
2322                 if (!bp->geneve_port_cnt) {
2323                         PMD_DRV_LOG(ERR, "No Tunnel port configured yet\n");
2324                         return -EINVAL;
2325                 }
2326                 if (bp->geneve_port != udp_tunnel->udp_port) {
2327                         PMD_DRV_LOG(ERR, "Req Port: %d. Configured port: %d\n",
2328                                 udp_tunnel->udp_port, bp->geneve_port);
2329                         return -EINVAL;
2330                 }
2331                 if (--bp->geneve_port_cnt)
2332                         return 0;
2333
2334                 tunnel_type =
2335                         HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_GENEVE;
2336                 port = bp->geneve_fw_dst_port_id;
2337                 break;
2338         default:
2339                 PMD_DRV_LOG(ERR, "Tunnel type is not supported\n");
2340                 return -ENOTSUP;
2341         }
2342
2343         rc = bnxt_hwrm_tunnel_dst_port_free(bp, port, tunnel_type);
2344         return rc;
2345 }
2346
2347 static int bnxt_del_vlan_filter(struct bnxt *bp, uint16_t vlan_id)
2348 {
2349         struct bnxt_filter_info *filter;
2350         struct bnxt_vnic_info *vnic;
2351         int rc = 0;
2352         uint32_t chk = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN;
2353
2354         vnic = BNXT_GET_DEFAULT_VNIC(bp);
2355         filter = STAILQ_FIRST(&vnic->filter);
2356         while (filter) {
2357                 /* Search for this matching MAC+VLAN filter */
2358                 if (bnxt_vlan_filter_exists(bp, filter, chk, vlan_id)) {
2359                         /* Delete the filter */
2360                         rc = bnxt_hwrm_clear_l2_filter(bp, filter);
2361                         if (rc)
2362                                 return rc;
2363                         STAILQ_REMOVE(&vnic->filter, filter,
2364                                       bnxt_filter_info, next);
2365                         bnxt_free_filter(bp, filter);
2366                         PMD_DRV_LOG(INFO,
2367                                     "Deleted vlan filter for %d\n",
2368                                     vlan_id);
2369                         return 0;
2370                 }
2371                 filter = STAILQ_NEXT(filter, next);
2372         }
2373         return -ENOENT;
2374 }
2375
2376 static int bnxt_add_vlan_filter(struct bnxt *bp, uint16_t vlan_id)
2377 {
2378         struct bnxt_filter_info *filter;
2379         struct bnxt_vnic_info *vnic;
2380         int rc = 0;
2381         uint32_t en = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN |
2382                 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN_MASK;
2383         uint32_t chk = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN;
2384
2385         /* Implementation notes on the use of VNIC in this command:
2386          *
2387          * By default, these filters belong to default vnic for the function.
2388          * Once these filters are set up, only destination VNIC can be modified.
2389          * If the destination VNIC is not specified in this command,
2390          * then the HWRM shall only create an l2 context id.
2391          */
2392
2393         vnic = BNXT_GET_DEFAULT_VNIC(bp);
2394         filter = STAILQ_FIRST(&vnic->filter);
2395         /* Check if the VLAN has already been added */
2396         while (filter) {
2397                 if (bnxt_vlan_filter_exists(bp, filter, chk, vlan_id))
2398                         return -EEXIST;
2399
2400                 filter = STAILQ_NEXT(filter, next);
2401         }
2402
2403         /* No match found. Alloc a fresh filter and issue the L2_FILTER_ALLOC
2404          * command to create MAC+VLAN filter with the right flags, enables set.
2405          */
2406         filter = bnxt_alloc_filter(bp);
2407         if (!filter) {
2408                 PMD_DRV_LOG(ERR,
2409                             "MAC/VLAN filter alloc failed\n");
2410                 return -ENOMEM;
2411         }
2412         /* MAC + VLAN ID filter */
2413         /* If l2_ivlan == 0 and l2_ivlan_mask != 0, only
2414          * untagged packets are received
2415          *
2416          * If l2_ivlan != 0 and l2_ivlan_mask != 0, untagged
2417          * packets and only the programmed vlan's packets are received
2418          */
2419         filter->l2_ivlan = vlan_id;
2420         filter->l2_ivlan_mask = 0x0FFF;
2421         filter->enables |= en;
2422         filter->flags |= HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_OUTERMOST;
2423
2424         rc = bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id, filter);
2425         if (rc) {
2426                 /* Free the newly allocated filter as we were
2427                  * not able to create the filter in hardware.
2428                  */
2429                 bnxt_free_filter(bp, filter);
2430                 return rc;
2431         }
2432
2433         filter->mac_index = 0;
2434         /* Add this new filter to the list */
2435         if (vlan_id == 0)
2436                 STAILQ_INSERT_HEAD(&vnic->filter, filter, next);
2437         else
2438                 STAILQ_INSERT_TAIL(&vnic->filter, filter, next);
2439
2440         PMD_DRV_LOG(INFO,
2441                     "Added Vlan filter for %d\n", vlan_id);
2442         return rc;
2443 }
2444
2445 static int bnxt_vlan_filter_set_op(struct rte_eth_dev *eth_dev,
2446                 uint16_t vlan_id, int on)
2447 {
2448         struct bnxt *bp = eth_dev->data->dev_private;
2449         int rc;
2450
2451         rc = is_bnxt_in_error(bp);
2452         if (rc)
2453                 return rc;
2454
2455         if (!eth_dev->data->dev_started) {
2456                 PMD_DRV_LOG(ERR, "port must be started before setting vlan\n");
2457                 return -EINVAL;
2458         }
2459
2460         /* These operations apply to ALL existing MAC/VLAN filters */
2461         if (on)
2462                 return bnxt_add_vlan_filter(bp, vlan_id);
2463         else
2464                 return bnxt_del_vlan_filter(bp, vlan_id);
2465 }
2466
2467 static int bnxt_del_dflt_mac_filter(struct bnxt *bp,
2468                                     struct bnxt_vnic_info *vnic)
2469 {
2470         struct bnxt_filter_info *filter;
2471         int rc;
2472
2473         filter = STAILQ_FIRST(&vnic->filter);
2474         while (filter) {
2475                 if (filter->mac_index == 0 &&
2476                     !memcmp(filter->l2_addr, bp->mac_addr,
2477                             RTE_ETHER_ADDR_LEN)) {
2478                         rc = bnxt_hwrm_clear_l2_filter(bp, filter);
2479                         if (!rc) {
2480                                 STAILQ_REMOVE(&vnic->filter, filter,
2481                                               bnxt_filter_info, next);
2482                                 bnxt_free_filter(bp, filter);
2483                         }
2484                         return rc;
2485                 }
2486                 filter = STAILQ_NEXT(filter, next);
2487         }
2488         return 0;
2489 }
2490
2491 static int
2492 bnxt_config_vlan_hw_filter(struct bnxt *bp, uint64_t rx_offloads)
2493 {
2494         struct bnxt_vnic_info *vnic;
2495         unsigned int i;
2496         int rc;
2497
2498         vnic = BNXT_GET_DEFAULT_VNIC(bp);
2499         if (!(rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER)) {
2500                 /* Remove any VLAN filters programmed */
2501                 for (i = 0; i < RTE_ETHER_MAX_VLAN_ID; i++)
2502                         bnxt_del_vlan_filter(bp, i);
2503
2504                 rc = bnxt_add_mac_filter(bp, vnic, NULL, 0, 0);
2505                 if (rc)
2506                         return rc;
2507         } else {
2508                 /* Default filter will allow packets that match the
2509                  * dest mac. So, it has to be deleted, otherwise, we
2510                  * will endup receiving vlan packets for which the
2511                  * filter is not programmed, when hw-vlan-filter
2512                  * configuration is ON
2513                  */
2514                 bnxt_del_dflt_mac_filter(bp, vnic);
2515                 /* This filter will allow only untagged packets */
2516                 bnxt_add_vlan_filter(bp, 0);
2517         }
2518         PMD_DRV_LOG(DEBUG, "VLAN Filtering: %d\n",
2519                     !!(rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER));
2520
2521         return 0;
2522 }
2523
2524 static int bnxt_free_one_vnic(struct bnxt *bp, uint16_t vnic_id)
2525 {
2526         struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id];
2527         unsigned int i;
2528         int rc;
2529
2530         /* Destroy vnic filters and vnic */
2531         if (bp->eth_dev->data->dev_conf.rxmode.offloads &
2532             DEV_RX_OFFLOAD_VLAN_FILTER) {
2533                 for (i = 0; i < RTE_ETHER_MAX_VLAN_ID; i++)
2534                         bnxt_del_vlan_filter(bp, i);
2535         }
2536         bnxt_del_dflt_mac_filter(bp, vnic);
2537
2538         rc = bnxt_hwrm_vnic_ctx_free(bp, vnic);
2539         if (rc)
2540                 return rc;
2541
2542         rc = bnxt_hwrm_vnic_free(bp, vnic);
2543         if (rc)
2544                 return rc;
2545
2546         rte_free(vnic->fw_grp_ids);
2547         vnic->fw_grp_ids = NULL;
2548
2549         vnic->rx_queue_cnt = 0;
2550
2551         return 0;
2552 }
2553
2554 static int
2555 bnxt_config_vlan_hw_stripping(struct bnxt *bp, uint64_t rx_offloads)
2556 {
2557         struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp);
2558         int rc;
2559
2560         /* Destroy, recreate and reconfigure the default vnic */
2561         rc = bnxt_free_one_vnic(bp, 0);
2562         if (rc)
2563                 return rc;
2564
2565         /* default vnic 0 */
2566         rc = bnxt_setup_one_vnic(bp, 0);
2567         if (rc)
2568                 return rc;
2569
2570         if (bp->eth_dev->data->dev_conf.rxmode.offloads &
2571             DEV_RX_OFFLOAD_VLAN_FILTER) {
2572                 rc = bnxt_add_vlan_filter(bp, 0);
2573                 if (rc)
2574                         return rc;
2575                 rc = bnxt_restore_vlan_filters(bp);
2576                 if (rc)
2577                         return rc;
2578         } else {
2579                 rc = bnxt_add_mac_filter(bp, vnic, NULL, 0, 0);
2580                 if (rc)
2581                         return rc;
2582         }
2583
2584         rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
2585         if (rc)
2586                 return rc;
2587
2588         PMD_DRV_LOG(DEBUG, "VLAN Strip Offload: %d\n",
2589                     !!(rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP));
2590
2591         return rc;
2592 }
2593
2594 static int
2595 bnxt_vlan_offload_set_op(struct rte_eth_dev *dev, int mask)
2596 {
2597         uint64_t rx_offloads = dev->data->dev_conf.rxmode.offloads;
2598         struct bnxt *bp = dev->data->dev_private;
2599         int rc;
2600
2601         rc = is_bnxt_in_error(bp);
2602         if (rc)
2603                 return rc;
2604
2605         /* Filter settings will get applied when port is started */
2606         if (!dev->data->dev_started)
2607                 return 0;
2608
2609         if (mask & ETH_VLAN_FILTER_MASK) {
2610                 /* Enable or disable VLAN filtering */
2611                 rc = bnxt_config_vlan_hw_filter(bp, rx_offloads);
2612                 if (rc)
2613                         return rc;
2614         }
2615
2616         if (mask & ETH_VLAN_STRIP_MASK) {
2617                 /* Enable or disable VLAN stripping */
2618                 rc = bnxt_config_vlan_hw_stripping(bp, rx_offloads);
2619                 if (rc)
2620                         return rc;
2621         }
2622
2623         if (mask & ETH_VLAN_EXTEND_MASK) {
2624                 if (rx_offloads & DEV_RX_OFFLOAD_VLAN_EXTEND)
2625                         PMD_DRV_LOG(DEBUG, "Extend VLAN supported\n");
2626                 else
2627                         PMD_DRV_LOG(INFO, "Extend VLAN unsupported\n");
2628         }
2629
2630         return 0;
2631 }
2632
2633 static int
2634 bnxt_vlan_tpid_set_op(struct rte_eth_dev *dev, enum rte_vlan_type vlan_type,
2635                       uint16_t tpid)
2636 {
2637         struct bnxt *bp = dev->data->dev_private;
2638         int qinq = dev->data->dev_conf.rxmode.offloads &
2639                    DEV_RX_OFFLOAD_VLAN_EXTEND;
2640
2641         if (vlan_type != ETH_VLAN_TYPE_INNER &&
2642             vlan_type != ETH_VLAN_TYPE_OUTER) {
2643                 PMD_DRV_LOG(ERR,
2644                             "Unsupported vlan type.");
2645                 return -EINVAL;
2646         }
2647         if (!qinq) {
2648                 PMD_DRV_LOG(ERR,
2649                             "QinQ not enabled. Needs to be ON as we can "
2650                             "accelerate only outer vlan\n");
2651                 return -EINVAL;
2652         }
2653
2654         if (vlan_type == ETH_VLAN_TYPE_OUTER) {
2655                 switch (tpid) {
2656                 case RTE_ETHER_TYPE_QINQ:
2657                         bp->outer_tpid_bd =
2658                                 TX_BD_LONG_CFA_META_VLAN_TPID_TPID88A8;
2659                                 break;
2660                 case RTE_ETHER_TYPE_VLAN:
2661                         bp->outer_tpid_bd =
2662                                 TX_BD_LONG_CFA_META_VLAN_TPID_TPID8100;
2663                                 break;
2664                 case RTE_ETHER_TYPE_QINQ1:
2665                         bp->outer_tpid_bd =
2666                                 TX_BD_LONG_CFA_META_VLAN_TPID_TPID9100;
2667                                 break;
2668                 case RTE_ETHER_TYPE_QINQ2:
2669                         bp->outer_tpid_bd =
2670                                 TX_BD_LONG_CFA_META_VLAN_TPID_TPID9200;
2671                                 break;
2672                 case RTE_ETHER_TYPE_QINQ3:
2673                         bp->outer_tpid_bd =
2674                                  TX_BD_LONG_CFA_META_VLAN_TPID_TPID9300;
2675                                 break;
2676                 default:
2677                         PMD_DRV_LOG(ERR, "Invalid TPID: %x\n", tpid);
2678                         return -EINVAL;
2679                 }
2680                 bp->outer_tpid_bd |= tpid;
2681                 PMD_DRV_LOG(INFO, "outer_tpid_bd = %x\n", bp->outer_tpid_bd);
2682         } else if (vlan_type == ETH_VLAN_TYPE_INNER) {
2683                 PMD_DRV_LOG(ERR,
2684                             "Can accelerate only outer vlan in QinQ\n");
2685                 return -EINVAL;
2686         }
2687
2688         return 0;
2689 }
2690
2691 static int
2692 bnxt_set_default_mac_addr_op(struct rte_eth_dev *dev,
2693                              struct rte_ether_addr *addr)
2694 {
2695         struct bnxt *bp = dev->data->dev_private;
2696         /* Default Filter is tied to VNIC 0 */
2697         struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp);
2698         int rc;
2699
2700         rc = is_bnxt_in_error(bp);
2701         if (rc)
2702                 return rc;
2703
2704         if (BNXT_VF(bp) && !BNXT_VF_IS_TRUSTED(bp))
2705                 return -EPERM;
2706
2707         if (rte_is_zero_ether_addr(addr))
2708                 return -EINVAL;
2709
2710         /* Filter settings will get applied when port is started */
2711         if (!dev->data->dev_started)
2712                 return 0;
2713
2714         /* Check if the requested MAC is already added */
2715         if (memcmp(addr, bp->mac_addr, RTE_ETHER_ADDR_LEN) == 0)
2716                 return 0;
2717
2718         /* Destroy filter and re-create it */
2719         bnxt_del_dflt_mac_filter(bp, vnic);
2720
2721         memcpy(bp->mac_addr, addr, RTE_ETHER_ADDR_LEN);
2722         if (dev->data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_VLAN_FILTER) {
2723                 /* This filter will allow only untagged packets */
2724                 rc = bnxt_add_vlan_filter(bp, 0);
2725         } else {
2726                 rc = bnxt_add_mac_filter(bp, vnic, addr, 0, 0);
2727         }
2728
2729         PMD_DRV_LOG(DEBUG, "Set MAC addr\n");
2730         return rc;
2731 }
2732
2733 static int
2734 bnxt_dev_set_mc_addr_list_op(struct rte_eth_dev *eth_dev,
2735                           struct rte_ether_addr *mc_addr_set,
2736                           uint32_t nb_mc_addr)
2737 {
2738         struct bnxt *bp = eth_dev->data->dev_private;
2739         char *mc_addr_list = (char *)mc_addr_set;
2740         struct bnxt_vnic_info *vnic;
2741         uint32_t off = 0, i = 0;
2742         int rc;
2743
2744         rc = is_bnxt_in_error(bp);
2745         if (rc)
2746                 return rc;
2747
2748         vnic = BNXT_GET_DEFAULT_VNIC(bp);
2749
2750         if (nb_mc_addr > BNXT_MAX_MC_ADDRS) {
2751                 vnic->flags |= BNXT_VNIC_INFO_ALLMULTI;
2752                 goto allmulti;
2753         }
2754
2755         /* TODO Check for Duplicate mcast addresses */
2756         vnic->flags &= ~BNXT_VNIC_INFO_ALLMULTI;
2757         for (i = 0; i < nb_mc_addr; i++) {
2758                 memcpy(vnic->mc_list + off, &mc_addr_list[i],
2759                         RTE_ETHER_ADDR_LEN);
2760                 off += RTE_ETHER_ADDR_LEN;
2761         }
2762
2763         vnic->mc_addr_cnt = i;
2764         if (vnic->mc_addr_cnt)
2765                 vnic->flags |= BNXT_VNIC_INFO_MCAST;
2766         else
2767                 vnic->flags &= ~BNXT_VNIC_INFO_MCAST;
2768
2769 allmulti:
2770         return bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
2771 }
2772
2773 static int
2774 bnxt_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size)
2775 {
2776         struct bnxt *bp = dev->data->dev_private;
2777         uint8_t fw_major = (bp->fw_ver >> 24) & 0xff;
2778         uint8_t fw_minor = (bp->fw_ver >> 16) & 0xff;
2779         uint8_t fw_updt = (bp->fw_ver >> 8) & 0xff;
2780         uint8_t fw_rsvd = bp->fw_ver & 0xff;
2781         int ret;
2782
2783         ret = snprintf(fw_version, fw_size, "%d.%d.%d.%d",
2784                         fw_major, fw_minor, fw_updt, fw_rsvd);
2785
2786         ret += 1; /* add the size of '\0' */
2787         if (fw_size < (uint32_t)ret)
2788                 return ret;
2789         else
2790                 return 0;
2791 }
2792
2793 static void
2794 bnxt_rxq_info_get_op(struct rte_eth_dev *dev, uint16_t queue_id,
2795         struct rte_eth_rxq_info *qinfo)
2796 {
2797         struct bnxt *bp = dev->data->dev_private;
2798         struct bnxt_rx_queue *rxq;
2799
2800         if (is_bnxt_in_error(bp))
2801                 return;
2802
2803         rxq = dev->data->rx_queues[queue_id];
2804
2805         qinfo->mp = rxq->mb_pool;
2806         qinfo->scattered_rx = dev->data->scattered_rx;
2807         qinfo->nb_desc = rxq->nb_rx_desc;
2808
2809         qinfo->conf.rx_free_thresh = rxq->rx_free_thresh;
2810         qinfo->conf.rx_drop_en = rxq->drop_en;
2811         qinfo->conf.rx_deferred_start = rxq->rx_deferred_start;
2812         qinfo->conf.offloads = dev->data->dev_conf.rxmode.offloads;
2813 }
2814
2815 static void
2816 bnxt_txq_info_get_op(struct rte_eth_dev *dev, uint16_t queue_id,
2817         struct rte_eth_txq_info *qinfo)
2818 {
2819         struct bnxt *bp = dev->data->dev_private;
2820         struct bnxt_tx_queue *txq;
2821
2822         if (is_bnxt_in_error(bp))
2823                 return;
2824
2825         txq = dev->data->tx_queues[queue_id];
2826
2827         qinfo->nb_desc = txq->nb_tx_desc;
2828
2829         qinfo->conf.tx_thresh.pthresh = txq->pthresh;
2830         qinfo->conf.tx_thresh.hthresh = txq->hthresh;
2831         qinfo->conf.tx_thresh.wthresh = txq->wthresh;
2832
2833         qinfo->conf.tx_free_thresh = txq->tx_free_thresh;
2834         qinfo->conf.tx_rs_thresh = 0;
2835         qinfo->conf.tx_deferred_start = txq->tx_deferred_start;
2836         qinfo->conf.offloads = txq->offloads;
2837 }
2838
2839 static const struct {
2840         eth_rx_burst_t pkt_burst;
2841         const char *info;
2842 } bnxt_rx_burst_info[] = {
2843         {bnxt_recv_pkts,        "Scalar"},
2844 #if defined(RTE_ARCH_X86)
2845         {bnxt_recv_pkts_vec,    "Vector SSE"},
2846 #elif defined(RTE_ARCH_ARM64)
2847         {bnxt_recv_pkts_vec,    "Vector Neon"},
2848 #endif
2849 };
2850
2851 static int
2852 bnxt_rx_burst_mode_get(struct rte_eth_dev *dev, __rte_unused uint16_t queue_id,
2853                        struct rte_eth_burst_mode *mode)
2854 {
2855         eth_rx_burst_t pkt_burst = dev->rx_pkt_burst;
2856         size_t i;
2857
2858         for (i = 0; i < RTE_DIM(bnxt_rx_burst_info); i++) {
2859                 if (pkt_burst == bnxt_rx_burst_info[i].pkt_burst) {
2860                         snprintf(mode->info, sizeof(mode->info), "%s",
2861                                  bnxt_rx_burst_info[i].info);
2862                         return 0;
2863                 }
2864         }
2865
2866         return -EINVAL;
2867 }
2868
2869 static const struct {
2870         eth_tx_burst_t pkt_burst;
2871         const char *info;
2872 } bnxt_tx_burst_info[] = {
2873         {bnxt_xmit_pkts,        "Scalar"},
2874 #if defined(RTE_ARCH_X86)
2875         {bnxt_xmit_pkts_vec,    "Vector SSE"},
2876 #elif defined(RTE_ARCH_ARM64)
2877         {bnxt_xmit_pkts_vec,    "Vector Neon"},
2878 #endif
2879 };
2880
2881 static int
2882 bnxt_tx_burst_mode_get(struct rte_eth_dev *dev, __rte_unused uint16_t queue_id,
2883                        struct rte_eth_burst_mode *mode)
2884 {
2885         eth_tx_burst_t pkt_burst = dev->tx_pkt_burst;
2886         size_t i;
2887
2888         for (i = 0; i < RTE_DIM(bnxt_tx_burst_info); i++) {
2889                 if (pkt_burst == bnxt_tx_burst_info[i].pkt_burst) {
2890                         snprintf(mode->info, sizeof(mode->info), "%s",
2891                                  bnxt_tx_burst_info[i].info);
2892                         return 0;
2893                 }
2894         }
2895
2896         return -EINVAL;
2897 }
2898
2899 int bnxt_mtu_set_op(struct rte_eth_dev *eth_dev, uint16_t new_mtu)
2900 {
2901         struct bnxt *bp = eth_dev->data->dev_private;
2902         uint32_t new_pkt_size;
2903         uint32_t rc = 0;
2904         uint32_t i;
2905
2906         rc = is_bnxt_in_error(bp);
2907         if (rc)
2908                 return rc;
2909
2910         /* Exit if receive queues are not configured yet */
2911         if (!eth_dev->data->nb_rx_queues)
2912                 return rc;
2913
2914         new_pkt_size = new_mtu + RTE_ETHER_HDR_LEN + RTE_ETHER_CRC_LEN +
2915                        VLAN_TAG_SIZE * BNXT_NUM_VLANS;
2916
2917         /*
2918          * Disallow any MTU change that would require scattered receive support
2919          * if it is not already enabled.
2920          */
2921         if (eth_dev->data->dev_started &&
2922             !eth_dev->data->scattered_rx &&
2923             (new_pkt_size >
2924              eth_dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM)) {
2925                 PMD_DRV_LOG(ERR,
2926                             "MTU change would require scattered rx support. ");
2927                 PMD_DRV_LOG(ERR, "Stop port before changing MTU.\n");
2928                 return -EINVAL;
2929         }
2930
2931         if (new_mtu > RTE_ETHER_MTU) {
2932                 bp->flags |= BNXT_FLAG_JUMBO;
2933                 bp->eth_dev->data->dev_conf.rxmode.offloads |=
2934                         DEV_RX_OFFLOAD_JUMBO_FRAME;
2935         } else {
2936                 bp->eth_dev->data->dev_conf.rxmode.offloads &=
2937                         ~DEV_RX_OFFLOAD_JUMBO_FRAME;
2938                 bp->flags &= ~BNXT_FLAG_JUMBO;
2939         }
2940
2941         /* Is there a change in mtu setting? */
2942         if (eth_dev->data->dev_conf.rxmode.max_rx_pkt_len == new_pkt_size)
2943                 return rc;
2944
2945         for (i = 0; i < bp->nr_vnics; i++) {
2946                 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
2947                 uint16_t size = 0;
2948
2949                 vnic->mru = BNXT_VNIC_MRU(new_mtu);
2950                 rc = bnxt_hwrm_vnic_cfg(bp, vnic);
2951                 if (rc)
2952                         break;
2953
2954                 size = rte_pktmbuf_data_room_size(bp->rx_queues[0]->mb_pool);
2955                 size -= RTE_PKTMBUF_HEADROOM;
2956
2957                 if (size < new_mtu) {
2958                         rc = bnxt_hwrm_vnic_plcmode_cfg(bp, vnic);
2959                         if (rc)
2960                                 return rc;
2961                 }
2962         }
2963
2964         if (!rc)
2965                 eth_dev->data->dev_conf.rxmode.max_rx_pkt_len = new_pkt_size;
2966
2967         PMD_DRV_LOG(INFO, "New MTU is %d\n", new_mtu);
2968
2969         return rc;
2970 }
2971
2972 static int
2973 bnxt_vlan_pvid_set_op(struct rte_eth_dev *dev, uint16_t pvid, int on)
2974 {
2975         struct bnxt *bp = dev->data->dev_private;
2976         uint16_t vlan = bp->vlan;
2977         int rc;
2978
2979         rc = is_bnxt_in_error(bp);
2980         if (rc)
2981                 return rc;
2982
2983         if (!BNXT_SINGLE_PF(bp) || BNXT_VF(bp)) {
2984                 PMD_DRV_LOG(ERR,
2985                         "PVID cannot be modified for this function\n");
2986                 return -ENOTSUP;
2987         }
2988         bp->vlan = on ? pvid : 0;
2989
2990         rc = bnxt_hwrm_set_default_vlan(bp, 0, 0);
2991         if (rc)
2992                 bp->vlan = vlan;
2993         return rc;
2994 }
2995
2996 static int
2997 bnxt_dev_led_on_op(struct rte_eth_dev *dev)
2998 {
2999         struct bnxt *bp = dev->data->dev_private;
3000         int rc;
3001
3002         rc = is_bnxt_in_error(bp);
3003         if (rc)
3004                 return rc;
3005
3006         return bnxt_hwrm_port_led_cfg(bp, true);
3007 }
3008
3009 static int
3010 bnxt_dev_led_off_op(struct rte_eth_dev *dev)
3011 {
3012         struct bnxt *bp = dev->data->dev_private;
3013         int rc;
3014
3015         rc = is_bnxt_in_error(bp);
3016         if (rc)
3017                 return rc;
3018
3019         return bnxt_hwrm_port_led_cfg(bp, false);
3020 }
3021
3022 static uint32_t
3023 bnxt_rx_queue_count_op(struct rte_eth_dev *dev, uint16_t rx_queue_id)
3024 {
3025         struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
3026         struct bnxt_cp_ring_info *cpr;
3027         uint32_t desc = 0, raw_cons;
3028         struct bnxt_rx_queue *rxq;
3029         struct rx_pkt_cmpl *rxcmp;
3030         int rc;
3031
3032         rc = is_bnxt_in_error(bp);
3033         if (rc)
3034                 return rc;
3035
3036         rxq = dev->data->rx_queues[rx_queue_id];
3037         cpr = rxq->cp_ring;
3038         raw_cons = cpr->cp_raw_cons;
3039
3040         while (1) {
3041                 uint32_t agg_cnt, cons, cmpl_type;
3042
3043                 cons = RING_CMP(cpr->cp_ring_struct, raw_cons);
3044                 rxcmp = (struct rx_pkt_cmpl *)&cpr->cp_desc_ring[cons];
3045
3046                 if (!CMP_VALID(rxcmp, raw_cons, cpr->cp_ring_struct))
3047                         break;
3048
3049                 cmpl_type = CMP_TYPE(rxcmp);
3050
3051                 switch (cmpl_type) {
3052                 case CMPL_BASE_TYPE_RX_L2:
3053                 case CMPL_BASE_TYPE_RX_L2_V2:
3054                         agg_cnt = BNXT_RX_L2_AGG_BUFS(rxcmp);
3055                         raw_cons = raw_cons + CMP_LEN(cmpl_type) + agg_cnt;
3056                         desc++;
3057                         break;
3058
3059                 case CMPL_BASE_TYPE_RX_TPA_END:
3060                         if (BNXT_CHIP_P5(rxq->bp)) {
3061                                 struct rx_tpa_v2_end_cmpl_hi *p5_tpa_end;
3062
3063                                 p5_tpa_end = (void *)rxcmp;
3064                                 agg_cnt = BNXT_TPA_END_AGG_BUFS_TH(p5_tpa_end);
3065                         } else {
3066                                 struct rx_tpa_end_cmpl *tpa_end;
3067
3068                                 tpa_end = (void *)rxcmp;
3069                                 agg_cnt = BNXT_TPA_END_AGG_BUFS(tpa_end);
3070                         }
3071
3072                         raw_cons = raw_cons + CMP_LEN(cmpl_type) + agg_cnt;
3073                         desc++;
3074                         break;
3075
3076                 default:
3077                         raw_cons += CMP_LEN(cmpl_type);
3078                 }
3079         }
3080
3081         return desc;
3082 }
3083
3084 static int
3085 bnxt_rx_descriptor_status_op(void *rx_queue, uint16_t offset)
3086 {
3087         struct bnxt_rx_queue *rxq = rx_queue;
3088         struct bnxt_cp_ring_info *cpr;
3089         struct bnxt_rx_ring_info *rxr;
3090         uint32_t desc, raw_cons;
3091         struct bnxt *bp = rxq->bp;
3092         struct rx_pkt_cmpl *rxcmp;
3093         int rc;
3094
3095         rc = is_bnxt_in_error(bp);
3096         if (rc)
3097                 return rc;
3098
3099         if (offset >= rxq->nb_rx_desc)
3100                 return -EINVAL;
3101
3102         rxr = rxq->rx_ring;
3103         cpr = rxq->cp_ring;
3104
3105         /*
3106          * For the vector receive case, the completion at the requested
3107          * offset can be indexed directly.
3108          */
3109 #if defined(RTE_ARCH_X86) || defined(RTE_ARCH_ARM64)
3110         if (bp->flags & BNXT_FLAG_RX_VECTOR_PKT_MODE) {
3111                 struct rx_pkt_cmpl *rxcmp;
3112                 uint32_t cons;
3113
3114                 /* Check status of completion descriptor. */
3115                 raw_cons = cpr->cp_raw_cons +
3116                            offset * CMP_LEN(CMPL_BASE_TYPE_RX_L2);
3117                 cons = RING_CMP(cpr->cp_ring_struct, raw_cons);
3118                 rxcmp = (struct rx_pkt_cmpl *)&cpr->cp_desc_ring[cons];
3119
3120                 if (CMP_VALID(rxcmp, raw_cons, cpr->cp_ring_struct))
3121                         return RTE_ETH_RX_DESC_DONE;
3122
3123                 /* Check whether rx desc has an mbuf attached. */
3124                 cons = RING_CMP(rxr->rx_ring_struct, raw_cons / 2);
3125                 if (cons >= rxq->rxrearm_start &&
3126                     cons < rxq->rxrearm_start + rxq->rxrearm_nb) {
3127                         return RTE_ETH_RX_DESC_UNAVAIL;
3128                 }
3129
3130                 return RTE_ETH_RX_DESC_AVAIL;
3131         }
3132 #endif
3133
3134         /*
3135          * For the non-vector receive case, scan the completion ring to
3136          * locate the completion descriptor for the requested offset.
3137          */
3138         raw_cons = cpr->cp_raw_cons;
3139         desc = 0;
3140         while (1) {
3141                 uint32_t agg_cnt, cons, cmpl_type;
3142
3143                 cons = RING_CMP(cpr->cp_ring_struct, raw_cons);
3144                 rxcmp = (struct rx_pkt_cmpl *)&cpr->cp_desc_ring[cons];
3145
3146                 if (!CMP_VALID(rxcmp, raw_cons, cpr->cp_ring_struct))
3147                         break;
3148
3149                 cmpl_type = CMP_TYPE(rxcmp);
3150
3151                 switch (cmpl_type) {
3152                 case CMPL_BASE_TYPE_RX_L2:
3153                 case CMPL_BASE_TYPE_RX_L2_V2:
3154                         if (desc == offset) {
3155                                 cons = rxcmp->opaque;
3156                                 if (rxr->rx_buf_ring[cons])
3157                                         return RTE_ETH_RX_DESC_DONE;
3158                                 else
3159                                         return RTE_ETH_RX_DESC_UNAVAIL;
3160                         }
3161                         agg_cnt = BNXT_RX_L2_AGG_BUFS(rxcmp);
3162                         raw_cons = raw_cons + CMP_LEN(cmpl_type) + agg_cnt;
3163                         desc++;
3164                         break;
3165
3166                 case CMPL_BASE_TYPE_RX_TPA_END:
3167                         if (desc == offset)
3168                                 return RTE_ETH_RX_DESC_DONE;
3169
3170                         if (BNXT_CHIP_P5(rxq->bp)) {
3171                                 struct rx_tpa_v2_end_cmpl_hi *p5_tpa_end;
3172
3173                                 p5_tpa_end = (void *)rxcmp;
3174                                 agg_cnt = BNXT_TPA_END_AGG_BUFS_TH(p5_tpa_end);
3175                         } else {
3176                                 struct rx_tpa_end_cmpl *tpa_end;
3177
3178                                 tpa_end = (void *)rxcmp;
3179                                 agg_cnt = BNXT_TPA_END_AGG_BUFS(tpa_end);
3180                         }
3181
3182                         raw_cons = raw_cons + CMP_LEN(cmpl_type) + agg_cnt;
3183                         desc++;
3184                         break;
3185
3186                 default:
3187                         raw_cons += CMP_LEN(cmpl_type);
3188                 }
3189         }
3190
3191         return RTE_ETH_RX_DESC_AVAIL;
3192 }
3193
3194 static int
3195 bnxt_tx_descriptor_status_op(void *tx_queue, uint16_t offset)
3196 {
3197         struct bnxt_tx_queue *txq = (struct bnxt_tx_queue *)tx_queue;
3198         struct bnxt_tx_ring_info *txr;
3199         struct bnxt_cp_ring_info *cpr;
3200         struct rte_mbuf **tx_buf;
3201         struct tx_pkt_cmpl *txcmp;
3202         uint32_t cons, cp_cons;
3203         int rc;
3204
3205         if (!txq)
3206                 return -EINVAL;
3207
3208         rc = is_bnxt_in_error(txq->bp);
3209         if (rc)
3210                 return rc;
3211
3212         cpr = txq->cp_ring;
3213         txr = txq->tx_ring;
3214
3215         if (offset >= txq->nb_tx_desc)
3216                 return -EINVAL;
3217
3218         cons = RING_CMP(cpr->cp_ring_struct, offset);
3219         txcmp = (struct tx_pkt_cmpl *)&cpr->cp_desc_ring[cons];
3220         cp_cons = cpr->cp_raw_cons;
3221
3222         if (cons > cp_cons) {
3223                 if (CMPL_VALID(txcmp, cpr->valid))
3224                         return RTE_ETH_TX_DESC_UNAVAIL;
3225         } else {
3226                 if (CMPL_VALID(txcmp, !cpr->valid))
3227                         return RTE_ETH_TX_DESC_UNAVAIL;
3228         }
3229         tx_buf = &txr->tx_buf_ring[cons];
3230         if (*tx_buf == NULL)
3231                 return RTE_ETH_TX_DESC_DONE;
3232
3233         return RTE_ETH_TX_DESC_FULL;
3234 }
3235
3236 int
3237 bnxt_flow_ops_get_op(struct rte_eth_dev *dev,
3238                      const struct rte_flow_ops **ops)
3239 {
3240         struct bnxt *bp = dev->data->dev_private;
3241         int ret = 0;
3242
3243         if (!bp)
3244                 return -EIO;
3245
3246         if (BNXT_ETH_DEV_IS_REPRESENTOR(dev)) {
3247                 struct bnxt_representor *vfr = dev->data->dev_private;
3248                 bp = vfr->parent_dev->data->dev_private;
3249                 /* parent is deleted while children are still valid */
3250                 if (!bp) {
3251                         PMD_DRV_LOG(DEBUG, "BNXT Port:%d VFR Error\n",
3252                                     dev->data->port_id);
3253                         return -EIO;
3254                 }
3255         }
3256
3257         ret = is_bnxt_in_error(bp);
3258         if (ret)
3259                 return ret;
3260
3261         /* PMD supports thread-safe flow operations.  rte_flow API
3262          * functions can avoid mutex for multi-thread safety.
3263          */
3264         dev->data->dev_flags |= RTE_ETH_DEV_FLOW_OPS_THREAD_SAFE;
3265
3266         if (BNXT_TRUFLOW_EN(bp))
3267                 *ops = &bnxt_ulp_rte_flow_ops;
3268         else
3269                 *ops = &bnxt_flow_ops;
3270
3271         return ret;
3272 }
3273
3274 static const uint32_t *
3275 bnxt_dev_supported_ptypes_get_op(struct rte_eth_dev *dev)
3276 {
3277         static const uint32_t ptypes[] = {
3278                 RTE_PTYPE_L2_ETHER_VLAN,
3279                 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN,
3280                 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN,
3281                 RTE_PTYPE_L4_ICMP,
3282                 RTE_PTYPE_L4_TCP,
3283                 RTE_PTYPE_L4_UDP,
3284                 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN,
3285                 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN,
3286                 RTE_PTYPE_INNER_L4_ICMP,
3287                 RTE_PTYPE_INNER_L4_TCP,
3288                 RTE_PTYPE_INNER_L4_UDP,
3289                 RTE_PTYPE_UNKNOWN
3290         };
3291
3292         if (!dev->rx_pkt_burst)
3293                 return NULL;
3294
3295         return ptypes;
3296 }
3297
3298 static int bnxt_map_regs(struct bnxt *bp, uint32_t *reg_arr, int count,
3299                          int reg_win)
3300 {
3301         uint32_t reg_base = *reg_arr & 0xfffff000;
3302         uint32_t win_off;
3303         int i;
3304
3305         for (i = 0; i < count; i++) {
3306                 if ((reg_arr[i] & 0xfffff000) != reg_base)
3307                         return -ERANGE;
3308         }
3309         win_off = BNXT_GRCPF_REG_WINDOW_BASE_OUT + (reg_win - 1) * 4;
3310         rte_write32(reg_base, (uint8_t *)bp->bar0 + win_off);
3311         return 0;
3312 }
3313
3314 static int bnxt_map_ptp_regs(struct bnxt *bp)
3315 {
3316         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3317         uint32_t *reg_arr;
3318         int rc, i;
3319
3320         reg_arr = ptp->rx_regs;
3321         rc = bnxt_map_regs(bp, reg_arr, BNXT_PTP_RX_REGS, 5);
3322         if (rc)
3323                 return rc;
3324
3325         reg_arr = ptp->tx_regs;
3326         rc = bnxt_map_regs(bp, reg_arr, BNXT_PTP_TX_REGS, 6);
3327         if (rc)
3328                 return rc;
3329
3330         for (i = 0; i < BNXT_PTP_RX_REGS; i++)
3331                 ptp->rx_mapped_regs[i] = 0x5000 + (ptp->rx_regs[i] & 0xfff);
3332
3333         for (i = 0; i < BNXT_PTP_TX_REGS; i++)
3334                 ptp->tx_mapped_regs[i] = 0x6000 + (ptp->tx_regs[i] & 0xfff);
3335
3336         return 0;
3337 }
3338
3339 static void bnxt_unmap_ptp_regs(struct bnxt *bp)
3340 {
3341         rte_write32(0, (uint8_t *)bp->bar0 +
3342                          BNXT_GRCPF_REG_WINDOW_BASE_OUT + 16);
3343         rte_write32(0, (uint8_t *)bp->bar0 +
3344                          BNXT_GRCPF_REG_WINDOW_BASE_OUT + 20);
3345 }
3346
3347 static uint64_t bnxt_cc_read(struct bnxt *bp)
3348 {
3349         uint64_t ns;
3350
3351         ns = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3352                               BNXT_GRCPF_REG_SYNC_TIME));
3353         ns |= (uint64_t)(rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3354                                           BNXT_GRCPF_REG_SYNC_TIME + 4))) << 32;
3355         return ns;
3356 }
3357
3358 static int bnxt_get_tx_ts(struct bnxt *bp, uint64_t *ts)
3359 {
3360         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3361         uint32_t fifo;
3362
3363         fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3364                                 ptp->tx_mapped_regs[BNXT_PTP_TX_FIFO]));
3365         if (fifo & BNXT_PTP_TX_FIFO_EMPTY)
3366                 return -EAGAIN;
3367
3368         fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3369                                 ptp->tx_mapped_regs[BNXT_PTP_TX_FIFO]));
3370         *ts = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3371                                 ptp->tx_mapped_regs[BNXT_PTP_TX_TS_L]));
3372         *ts |= (uint64_t)rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3373                                 ptp->tx_mapped_regs[BNXT_PTP_TX_TS_H])) << 32;
3374         rte_read32((uint8_t *)bp->bar0 + ptp->tx_mapped_regs[BNXT_PTP_TX_SEQ]);
3375
3376         return 0;
3377 }
3378
3379 static int bnxt_get_rx_ts(struct bnxt *bp, uint64_t *ts)
3380 {
3381         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3382         struct bnxt_pf_info *pf = bp->pf;
3383         uint16_t port_id;
3384         uint32_t fifo;
3385
3386         fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3387                                 ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO]));
3388         if (!(fifo & BNXT_PTP_RX_FIFO_PENDING))
3389                 return -EAGAIN;
3390
3391         port_id = pf->port_id;
3392         rte_write32(1 << port_id, (uint8_t *)bp->bar0 +
3393                ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO_ADV]);
3394
3395         fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3396                                    ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO]));
3397         if (fifo & BNXT_PTP_RX_FIFO_PENDING) {
3398 /*              bnxt_clr_rx_ts(bp);       TBD  */
3399                 return -EBUSY;
3400         }
3401
3402         *ts = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3403                                 ptp->rx_mapped_regs[BNXT_PTP_RX_TS_L]));
3404         *ts |= (uint64_t)rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3405                                 ptp->rx_mapped_regs[BNXT_PTP_RX_TS_H])) << 32;
3406
3407         return 0;
3408 }
3409
3410 static int
3411 bnxt_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
3412 {
3413         uint64_t ns;
3414         struct bnxt *bp = dev->data->dev_private;
3415         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3416
3417         if (!ptp)
3418                 return -ENOTSUP;
3419
3420         ns = rte_timespec_to_ns(ts);
3421         /* Set the timecounters to a new value. */
3422         ptp->tc.nsec = ns;
3423         ptp->tx_tstamp_tc.nsec = ns;
3424         ptp->rx_tstamp_tc.nsec = ns;
3425
3426         return 0;
3427 }
3428
3429 static int
3430 bnxt_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
3431 {
3432         struct bnxt *bp = dev->data->dev_private;
3433         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3434         uint64_t ns, systime_cycles = 0;
3435         int rc = 0;
3436
3437         if (!ptp)
3438                 return -ENOTSUP;
3439
3440         if (BNXT_CHIP_P5(bp))
3441                 rc = bnxt_hwrm_port_ts_query(bp, BNXT_PTP_FLAGS_CURRENT_TIME,
3442                                              &systime_cycles);
3443         else
3444                 systime_cycles = bnxt_cc_read(bp);
3445
3446         ns = rte_timecounter_update(&ptp->tc, systime_cycles);
3447         *ts = rte_ns_to_timespec(ns);
3448
3449         return rc;
3450 }
3451 static int
3452 bnxt_timesync_enable(struct rte_eth_dev *dev)
3453 {
3454         struct bnxt *bp = dev->data->dev_private;
3455         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3456         uint32_t shift = 0;
3457         int rc;
3458
3459         if (!ptp)
3460                 return -ENOTSUP;
3461
3462         ptp->rx_filter = 1;
3463         ptp->tx_tstamp_en = 1;
3464         ptp->rxctl = BNXT_PTP_MSG_EVENTS;
3465
3466         rc = bnxt_hwrm_ptp_cfg(bp);
3467         if (rc)
3468                 return rc;
3469
3470         memset(&ptp->tc, 0, sizeof(struct rte_timecounter));
3471         memset(&ptp->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
3472         memset(&ptp->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
3473
3474         ptp->tc.cc_mask = BNXT_CYCLECOUNTER_MASK;
3475         ptp->tc.cc_shift = shift;
3476         ptp->tc.nsec_mask = (1ULL << shift) - 1;
3477
3478         ptp->rx_tstamp_tc.cc_mask = BNXT_CYCLECOUNTER_MASK;
3479         ptp->rx_tstamp_tc.cc_shift = shift;
3480         ptp->rx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
3481
3482         ptp->tx_tstamp_tc.cc_mask = BNXT_CYCLECOUNTER_MASK;
3483         ptp->tx_tstamp_tc.cc_shift = shift;
3484         ptp->tx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
3485
3486         if (!BNXT_CHIP_P5(bp))
3487                 bnxt_map_ptp_regs(bp);
3488         else
3489                 rc = bnxt_ptp_start(bp);
3490
3491         return rc;
3492 }
3493
3494 static int
3495 bnxt_timesync_disable(struct rte_eth_dev *dev)
3496 {
3497         struct bnxt *bp = dev->data->dev_private;
3498         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3499
3500         if (!ptp)
3501                 return -ENOTSUP;
3502
3503         ptp->rx_filter = 0;
3504         ptp->tx_tstamp_en = 0;
3505         ptp->rxctl = 0;
3506
3507         bnxt_hwrm_ptp_cfg(bp);
3508
3509         if (!BNXT_CHIP_P5(bp))
3510                 bnxt_unmap_ptp_regs(bp);
3511         else
3512                 bnxt_ptp_stop(bp);
3513
3514         return 0;
3515 }
3516
3517 static int
3518 bnxt_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
3519                                  struct timespec *timestamp,
3520                                  uint32_t flags __rte_unused)
3521 {
3522         struct bnxt *bp = dev->data->dev_private;
3523         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3524         uint64_t rx_tstamp_cycles = 0;
3525         uint64_t ns;
3526
3527         if (!ptp)
3528                 return -ENOTSUP;
3529
3530         if (BNXT_CHIP_P5(bp))
3531                 rx_tstamp_cycles = ptp->rx_timestamp;
3532         else
3533                 bnxt_get_rx_ts(bp, &rx_tstamp_cycles);
3534
3535         ns = rte_timecounter_update(&ptp->rx_tstamp_tc, rx_tstamp_cycles);
3536         *timestamp = rte_ns_to_timespec(ns);
3537         return  0;
3538 }
3539
3540 static int
3541 bnxt_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
3542                                  struct timespec *timestamp)
3543 {
3544         struct bnxt *bp = dev->data->dev_private;
3545         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3546         uint64_t tx_tstamp_cycles = 0;
3547         uint64_t ns;
3548         int rc = 0;
3549
3550         if (!ptp)
3551                 return -ENOTSUP;
3552
3553         if (BNXT_CHIP_P5(bp))
3554                 rc = bnxt_hwrm_port_ts_query(bp, BNXT_PTP_FLAGS_PATH_TX,
3555                                              &tx_tstamp_cycles);
3556         else
3557                 rc = bnxt_get_tx_ts(bp, &tx_tstamp_cycles);
3558
3559         ns = rte_timecounter_update(&ptp->tx_tstamp_tc, tx_tstamp_cycles);
3560         *timestamp = rte_ns_to_timespec(ns);
3561
3562         return rc;
3563 }
3564
3565 static int
3566 bnxt_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
3567 {
3568         struct bnxt *bp = dev->data->dev_private;
3569         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3570
3571         if (!ptp)
3572                 return -ENOTSUP;
3573
3574         ptp->tc.nsec += delta;
3575         ptp->tx_tstamp_tc.nsec += delta;
3576         ptp->rx_tstamp_tc.nsec += delta;
3577
3578         return 0;
3579 }
3580
3581 static int
3582 bnxt_get_eeprom_length_op(struct rte_eth_dev *dev)
3583 {
3584         struct bnxt *bp = dev->data->dev_private;
3585         int rc;
3586         uint32_t dir_entries;
3587         uint32_t entry_length;
3588
3589         rc = is_bnxt_in_error(bp);
3590         if (rc)
3591                 return rc;
3592
3593         PMD_DRV_LOG(INFO, PCI_PRI_FMT "\n",
3594                     bp->pdev->addr.domain, bp->pdev->addr.bus,
3595                     bp->pdev->addr.devid, bp->pdev->addr.function);
3596
3597         rc = bnxt_hwrm_nvm_get_dir_info(bp, &dir_entries, &entry_length);
3598         if (rc != 0)
3599                 return rc;
3600
3601         return dir_entries * entry_length;
3602 }
3603
3604 static int
3605 bnxt_get_eeprom_op(struct rte_eth_dev *dev,
3606                 struct rte_dev_eeprom_info *in_eeprom)
3607 {
3608         struct bnxt *bp = dev->data->dev_private;
3609         uint32_t index;
3610         uint32_t offset;
3611         int rc;
3612
3613         rc = is_bnxt_in_error(bp);
3614         if (rc)
3615                 return rc;
3616
3617         PMD_DRV_LOG(INFO, PCI_PRI_FMT " in_eeprom->offset = %d len = %d\n",
3618                     bp->pdev->addr.domain, bp->pdev->addr.bus,
3619                     bp->pdev->addr.devid, bp->pdev->addr.function,
3620                     in_eeprom->offset, in_eeprom->length);
3621
3622         if (in_eeprom->offset == 0) /* special offset value to get directory */
3623                 return bnxt_get_nvram_directory(bp, in_eeprom->length,
3624                                                 in_eeprom->data);
3625
3626         index = in_eeprom->offset >> 24;
3627         offset = in_eeprom->offset & 0xffffff;
3628
3629         if (index != 0)
3630                 return bnxt_hwrm_get_nvram_item(bp, index - 1, offset,
3631                                            in_eeprom->length, in_eeprom->data);
3632
3633         return 0;
3634 }
3635
3636 static bool bnxt_dir_type_is_ape_bin_format(uint16_t dir_type)
3637 {
3638         switch (dir_type) {
3639         case BNX_DIR_TYPE_CHIMP_PATCH:
3640         case BNX_DIR_TYPE_BOOTCODE:
3641         case BNX_DIR_TYPE_BOOTCODE_2:
3642         case BNX_DIR_TYPE_APE_FW:
3643         case BNX_DIR_TYPE_APE_PATCH:
3644         case BNX_DIR_TYPE_KONG_FW:
3645         case BNX_DIR_TYPE_KONG_PATCH:
3646         case BNX_DIR_TYPE_BONO_FW:
3647         case BNX_DIR_TYPE_BONO_PATCH:
3648                 /* FALLTHROUGH */
3649                 return true;
3650         }
3651
3652         return false;
3653 }
3654
3655 static bool bnxt_dir_type_is_other_exec_format(uint16_t dir_type)
3656 {
3657         switch (dir_type) {
3658         case BNX_DIR_TYPE_AVS:
3659         case BNX_DIR_TYPE_EXP_ROM_MBA:
3660         case BNX_DIR_TYPE_PCIE:
3661         case BNX_DIR_TYPE_TSCF_UCODE:
3662         case BNX_DIR_TYPE_EXT_PHY:
3663         case BNX_DIR_TYPE_CCM:
3664         case BNX_DIR_TYPE_ISCSI_BOOT:
3665         case BNX_DIR_TYPE_ISCSI_BOOT_IPV6:
3666         case BNX_DIR_TYPE_ISCSI_BOOT_IPV4N6:
3667                 /* FALLTHROUGH */
3668                 return true;
3669         }
3670
3671         return false;
3672 }
3673
3674 static bool bnxt_dir_type_is_executable(uint16_t dir_type)
3675 {
3676         return bnxt_dir_type_is_ape_bin_format(dir_type) ||
3677                 bnxt_dir_type_is_other_exec_format(dir_type);
3678 }
3679
3680 static int
3681 bnxt_set_eeprom_op(struct rte_eth_dev *dev,
3682                 struct rte_dev_eeprom_info *in_eeprom)
3683 {
3684         struct bnxt *bp = dev->data->dev_private;
3685         uint8_t index, dir_op;
3686         uint16_t type, ext, ordinal, attr;
3687         int rc;
3688
3689         rc = is_bnxt_in_error(bp);
3690         if (rc)
3691                 return rc;
3692
3693         PMD_DRV_LOG(INFO, PCI_PRI_FMT " in_eeprom->offset = %d len = %d\n",
3694                     bp->pdev->addr.domain, bp->pdev->addr.bus,
3695                     bp->pdev->addr.devid, bp->pdev->addr.function,
3696                     in_eeprom->offset, in_eeprom->length);
3697
3698         if (!BNXT_PF(bp)) {
3699                 PMD_DRV_LOG(ERR, "NVM write not supported from a VF\n");
3700                 return -EINVAL;
3701         }
3702
3703         type = in_eeprom->magic >> 16;
3704
3705         if (type == 0xffff) { /* special value for directory operations */
3706                 index = in_eeprom->magic & 0xff;
3707                 dir_op = in_eeprom->magic >> 8;
3708                 if (index == 0)
3709                         return -EINVAL;
3710                 switch (dir_op) {
3711                 case 0x0e: /* erase */
3712                         if (in_eeprom->offset != ~in_eeprom->magic)
3713                                 return -EINVAL;
3714                         return bnxt_hwrm_erase_nvram_directory(bp, index - 1);
3715                 default:
3716                         return -EINVAL;
3717                 }
3718         }
3719
3720         /* Create or re-write an NVM item: */
3721         if (bnxt_dir_type_is_executable(type) == true)
3722                 return -EOPNOTSUPP;
3723         ext = in_eeprom->magic & 0xffff;
3724         ordinal = in_eeprom->offset >> 16;
3725         attr = in_eeprom->offset & 0xffff;
3726
3727         return bnxt_hwrm_flash_nvram(bp, type, ordinal, ext, attr,
3728                                      in_eeprom->data, in_eeprom->length);
3729 }
3730
3731 /*
3732  * Initialization
3733  */
3734
3735 static const struct eth_dev_ops bnxt_dev_ops = {
3736         .dev_infos_get = bnxt_dev_info_get_op,
3737         .dev_close = bnxt_dev_close_op,
3738         .dev_configure = bnxt_dev_configure_op,
3739         .dev_start = bnxt_dev_start_op,
3740         .dev_stop = bnxt_dev_stop_op,
3741         .dev_set_link_up = bnxt_dev_set_link_up_op,
3742         .dev_set_link_down = bnxt_dev_set_link_down_op,
3743         .stats_get = bnxt_stats_get_op,
3744         .stats_reset = bnxt_stats_reset_op,
3745         .rx_queue_setup = bnxt_rx_queue_setup_op,
3746         .rx_queue_release = bnxt_rx_queue_release_op,
3747         .tx_queue_setup = bnxt_tx_queue_setup_op,
3748         .tx_queue_release = bnxt_tx_queue_release_op,
3749         .rx_queue_intr_enable = bnxt_rx_queue_intr_enable_op,
3750         .rx_queue_intr_disable = bnxt_rx_queue_intr_disable_op,
3751         .reta_update = bnxt_reta_update_op,
3752         .reta_query = bnxt_reta_query_op,
3753         .rss_hash_update = bnxt_rss_hash_update_op,
3754         .rss_hash_conf_get = bnxt_rss_hash_conf_get_op,
3755         .link_update = bnxt_link_update_op,
3756         .promiscuous_enable = bnxt_promiscuous_enable_op,
3757         .promiscuous_disable = bnxt_promiscuous_disable_op,
3758         .allmulticast_enable = bnxt_allmulticast_enable_op,
3759         .allmulticast_disable = bnxt_allmulticast_disable_op,
3760         .mac_addr_add = bnxt_mac_addr_add_op,
3761         .mac_addr_remove = bnxt_mac_addr_remove_op,
3762         .flow_ctrl_get = bnxt_flow_ctrl_get_op,
3763         .flow_ctrl_set = bnxt_flow_ctrl_set_op,
3764         .udp_tunnel_port_add  = bnxt_udp_tunnel_port_add_op,
3765         .udp_tunnel_port_del  = bnxt_udp_tunnel_port_del_op,
3766         .vlan_filter_set = bnxt_vlan_filter_set_op,
3767         .vlan_offload_set = bnxt_vlan_offload_set_op,
3768         .vlan_tpid_set = bnxt_vlan_tpid_set_op,
3769         .vlan_pvid_set = bnxt_vlan_pvid_set_op,
3770         .mtu_set = bnxt_mtu_set_op,
3771         .mac_addr_set = bnxt_set_default_mac_addr_op,
3772         .xstats_get = bnxt_dev_xstats_get_op,
3773         .xstats_get_names = bnxt_dev_xstats_get_names_op,
3774         .xstats_reset = bnxt_dev_xstats_reset_op,
3775         .fw_version_get = bnxt_fw_version_get,
3776         .set_mc_addr_list = bnxt_dev_set_mc_addr_list_op,
3777         .rxq_info_get = bnxt_rxq_info_get_op,
3778         .txq_info_get = bnxt_txq_info_get_op,
3779         .rx_burst_mode_get = bnxt_rx_burst_mode_get,
3780         .tx_burst_mode_get = bnxt_tx_burst_mode_get,
3781         .dev_led_on = bnxt_dev_led_on_op,
3782         .dev_led_off = bnxt_dev_led_off_op,
3783         .rx_queue_start = bnxt_rx_queue_start,
3784         .rx_queue_stop = bnxt_rx_queue_stop,
3785         .tx_queue_start = bnxt_tx_queue_start,
3786         .tx_queue_stop = bnxt_tx_queue_stop,
3787         .flow_ops_get = bnxt_flow_ops_get_op,
3788         .dev_supported_ptypes_get = bnxt_dev_supported_ptypes_get_op,
3789         .get_eeprom_length    = bnxt_get_eeprom_length_op,
3790         .get_eeprom           = bnxt_get_eeprom_op,
3791         .set_eeprom           = bnxt_set_eeprom_op,
3792         .timesync_enable      = bnxt_timesync_enable,
3793         .timesync_disable     = bnxt_timesync_disable,
3794         .timesync_read_time   = bnxt_timesync_read_time,
3795         .timesync_write_time   = bnxt_timesync_write_time,
3796         .timesync_adjust_time = bnxt_timesync_adjust_time,
3797         .timesync_read_rx_timestamp = bnxt_timesync_read_rx_timestamp,
3798         .timesync_read_tx_timestamp = bnxt_timesync_read_tx_timestamp,
3799 };
3800
3801 static uint32_t bnxt_map_reset_regs(struct bnxt *bp, uint32_t reg)
3802 {
3803         uint32_t offset;
3804
3805         /* Only pre-map the reset GRC registers using window 3 */
3806         rte_write32(reg & 0xfffff000, (uint8_t *)bp->bar0 +
3807                     BNXT_GRCPF_REG_WINDOW_BASE_OUT + 8);
3808
3809         offset = BNXT_GRCP_WINDOW_3_BASE + (reg & 0xffc);
3810
3811         return offset;
3812 }
3813
3814 int bnxt_map_fw_health_status_regs(struct bnxt *bp)
3815 {
3816         struct bnxt_error_recovery_info *info = bp->recovery_info;
3817         uint32_t reg_base = 0xffffffff;
3818         int i;
3819
3820         /* Only pre-map the monitoring GRC registers using window 2 */
3821         for (i = 0; i < BNXT_FW_STATUS_REG_CNT; i++) {
3822                 uint32_t reg = info->status_regs[i];
3823
3824                 if (BNXT_FW_STATUS_REG_TYPE(reg) != BNXT_FW_STATUS_REG_TYPE_GRC)
3825                         continue;
3826
3827                 if (reg_base == 0xffffffff)
3828                         reg_base = reg & 0xfffff000;
3829                 if ((reg & 0xfffff000) != reg_base)
3830                         return -ERANGE;
3831
3832                 /* Use mask 0xffc as the Lower 2 bits indicates
3833                  * address space location
3834                  */
3835                 info->mapped_status_regs[i] = BNXT_GRCP_WINDOW_2_BASE +
3836                                                 (reg & 0xffc);
3837         }
3838
3839         if (reg_base == 0xffffffff)
3840                 return 0;
3841
3842         rte_write32(reg_base, (uint8_t *)bp->bar0 +
3843                     BNXT_GRCPF_REG_WINDOW_BASE_OUT + 4);
3844
3845         return 0;
3846 }
3847
3848 static void bnxt_write_fw_reset_reg(struct bnxt *bp, uint32_t index)
3849 {
3850         struct bnxt_error_recovery_info *info = bp->recovery_info;
3851         uint32_t delay = info->delay_after_reset[index];
3852         uint32_t val = info->reset_reg_val[index];
3853         uint32_t reg = info->reset_reg[index];
3854         uint32_t type, offset;
3855         int ret;
3856
3857         type = BNXT_FW_STATUS_REG_TYPE(reg);
3858         offset = BNXT_FW_STATUS_REG_OFF(reg);
3859
3860         switch (type) {
3861         case BNXT_FW_STATUS_REG_TYPE_CFG:
3862                 ret = rte_pci_write_config(bp->pdev, &val, sizeof(val), offset);
3863                 if (ret < 0) {
3864                         PMD_DRV_LOG(ERR, "Failed to write %#x at PCI offset %#x",
3865                                     val, offset);
3866                         return;
3867                 }
3868                 break;
3869         case BNXT_FW_STATUS_REG_TYPE_GRC:
3870                 offset = bnxt_map_reset_regs(bp, offset);
3871                 rte_write32(val, (uint8_t *)bp->bar0 + offset);
3872                 break;
3873         case BNXT_FW_STATUS_REG_TYPE_BAR0:
3874                 rte_write32(val, (uint8_t *)bp->bar0 + offset);
3875                 break;
3876         }
3877         /* wait on a specific interval of time until core reset is complete */
3878         if (delay)
3879                 rte_delay_ms(delay);
3880 }
3881
3882 static void bnxt_dev_cleanup(struct bnxt *bp)
3883 {
3884         bp->eth_dev->data->dev_link.link_status = 0;
3885         bp->link_info->link_up = 0;
3886         if (bp->eth_dev->data->dev_started)
3887                 bnxt_dev_stop(bp->eth_dev);
3888
3889         bnxt_uninit_resources(bp, true);
3890 }
3891
3892 static int
3893 bnxt_check_fw_reset_done(struct bnxt *bp)
3894 {
3895         int timeout = bp->fw_reset_max_msecs;
3896         uint16_t val = 0;
3897         int rc;
3898
3899         do {
3900                 rc = rte_pci_read_config(bp->pdev, &val, sizeof(val), PCI_SUBSYSTEM_ID_OFFSET);
3901                 if (rc < 0) {
3902                         PMD_DRV_LOG(ERR, "Failed to read PCI offset 0x%x", PCI_SUBSYSTEM_ID_OFFSET);
3903                         return rc;
3904                 }
3905                 if (val != 0xffff)
3906                         break;
3907                 rte_delay_ms(1);
3908         } while (timeout--);
3909
3910         if (val == 0xffff) {
3911                 PMD_DRV_LOG(ERR, "Firmware reset aborted, PCI config space invalid\n");
3912                 return -1;
3913         }
3914
3915         return 0;
3916 }
3917
3918 static int bnxt_restore_vlan_filters(struct bnxt *bp)
3919 {
3920         struct rte_eth_dev *dev = bp->eth_dev;
3921         struct rte_vlan_filter_conf *vfc;
3922         int vidx, vbit, rc;
3923         uint16_t vlan_id;
3924
3925         for (vlan_id = 1; vlan_id <= RTE_ETHER_MAX_VLAN_ID; vlan_id++) {
3926                 vfc = &dev->data->vlan_filter_conf;
3927                 vidx = vlan_id / 64;
3928                 vbit = vlan_id % 64;
3929
3930                 /* Each bit corresponds to a VLAN id */
3931                 if (vfc->ids[vidx] & (UINT64_C(1) << vbit)) {
3932                         rc = bnxt_add_vlan_filter(bp, vlan_id);
3933                         if (rc)
3934                                 return rc;
3935                 }
3936         }
3937
3938         return 0;
3939 }
3940
3941 static int bnxt_restore_mac_filters(struct bnxt *bp)
3942 {
3943         struct rte_eth_dev *dev = bp->eth_dev;
3944         struct rte_eth_dev_info dev_info;
3945         struct rte_ether_addr *addr;
3946         uint64_t pool_mask;
3947         uint32_t pool = 0;
3948         uint16_t i;
3949         int rc;
3950
3951         if (BNXT_VF(bp) && !BNXT_VF_IS_TRUSTED(bp))
3952                 return 0;
3953
3954         rc = bnxt_dev_info_get_op(dev, &dev_info);
3955         if (rc)
3956                 return rc;
3957
3958         /* replay MAC address configuration */
3959         for (i = 1; i < dev_info.max_mac_addrs; i++) {
3960                 addr = &dev->data->mac_addrs[i];
3961
3962                 /* skip zero address */
3963                 if (rte_is_zero_ether_addr(addr))
3964                         continue;
3965
3966                 pool = 0;
3967                 pool_mask = dev->data->mac_pool_sel[i];
3968
3969                 do {
3970                         if (pool_mask & 1ULL) {
3971                                 rc = bnxt_mac_addr_add_op(dev, addr, i, pool);
3972                                 if (rc)
3973                                         return rc;
3974                         }
3975                         pool_mask >>= 1;
3976                         pool++;
3977                 } while (pool_mask);
3978         }
3979
3980         return 0;
3981 }
3982
3983 static int bnxt_restore_filters(struct bnxt *bp)
3984 {
3985         struct rte_eth_dev *dev = bp->eth_dev;
3986         int ret = 0;
3987
3988         if (dev->data->all_multicast) {
3989                 ret = bnxt_allmulticast_enable_op(dev);
3990                 if (ret)
3991                         return ret;
3992         }
3993         if (dev->data->promiscuous) {
3994                 ret = bnxt_promiscuous_enable_op(dev);
3995                 if (ret)
3996                         return ret;
3997         }
3998
3999         ret = bnxt_restore_mac_filters(bp);
4000         if (ret)
4001                 return ret;
4002
4003         ret = bnxt_restore_vlan_filters(bp);
4004         /* TODO restore other filters as well */
4005         return ret;
4006 }
4007
4008 static int bnxt_check_fw_ready(struct bnxt *bp)
4009 {
4010         int timeout = bp->fw_reset_max_msecs;
4011         int rc = 0;
4012
4013         do {
4014                 rc = bnxt_hwrm_poll_ver_get(bp);
4015                 if (rc == 0)
4016                         break;
4017                 rte_delay_ms(BNXT_FW_READY_WAIT_INTERVAL);
4018                 timeout -= BNXT_FW_READY_WAIT_INTERVAL;
4019         } while (rc && timeout > 0);
4020
4021         if (rc)
4022                 PMD_DRV_LOG(ERR, "FW is not Ready after reset\n");
4023
4024         return rc;
4025 }
4026
4027 static void bnxt_dev_recover(void *arg)
4028 {
4029         struct bnxt *bp = arg;
4030         int rc = 0;
4031
4032         pthread_mutex_lock(&bp->err_recovery_lock);
4033
4034         if (!bp->fw_reset_min_msecs) {
4035                 rc = bnxt_check_fw_reset_done(bp);
4036                 if (rc)
4037                         goto err;
4038         }
4039
4040         /* Clear Error flag so that device re-init should happen */
4041         bp->flags &= ~BNXT_FLAG_FATAL_ERROR;
4042
4043         rc = bnxt_check_fw_ready(bp);
4044         if (rc)
4045                 goto err;
4046
4047         rc = bnxt_init_resources(bp, true);
4048         if (rc) {
4049                 PMD_DRV_LOG(ERR,
4050                             "Failed to initialize resources after reset\n");
4051                 goto err;
4052         }
4053         /* clear reset flag as the device is initialized now */
4054         bp->flags &= ~BNXT_FLAG_FW_RESET;
4055
4056         rc = bnxt_dev_start_op(bp->eth_dev);
4057         if (rc) {
4058                 PMD_DRV_LOG(ERR, "Failed to start port after reset\n");
4059                 goto err_start;
4060         }
4061
4062         rc = bnxt_restore_filters(bp);
4063         if (rc)
4064                 goto err_start;
4065
4066         PMD_DRV_LOG(INFO, "Recovered from FW reset\n");
4067         pthread_mutex_unlock(&bp->err_recovery_lock);
4068
4069         return;
4070 err_start:
4071         bnxt_dev_stop(bp->eth_dev);
4072 err:
4073         bp->flags |= BNXT_FLAG_FATAL_ERROR;
4074         bnxt_uninit_resources(bp, false);
4075         pthread_mutex_unlock(&bp->err_recovery_lock);
4076         PMD_DRV_LOG(ERR, "Failed to recover from FW reset\n");
4077 }
4078
4079 void bnxt_dev_reset_and_resume(void *arg)
4080 {
4081         struct bnxt *bp = arg;
4082         uint32_t us = US_PER_MS * bp->fw_reset_min_msecs;
4083         uint16_t val = 0;
4084         int rc;
4085
4086         bnxt_dev_cleanup(bp);
4087
4088         bnxt_wait_for_device_shutdown(bp);
4089
4090         /* During some fatal firmware error conditions, the PCI config space
4091          * register 0x2e which normally contains the subsystem ID will become
4092          * 0xffff. This register will revert back to the normal value after
4093          * the chip has completed core reset. If we detect this condition,
4094          * we can poll this config register immediately for the value to revert.
4095          */
4096         if (bp->flags & BNXT_FLAG_FATAL_ERROR) {
4097                 rc = rte_pci_read_config(bp->pdev, &val, sizeof(val), PCI_SUBSYSTEM_ID_OFFSET);
4098                 if (rc < 0) {
4099                         PMD_DRV_LOG(ERR, "Failed to read PCI offset 0x%x", PCI_SUBSYSTEM_ID_OFFSET);
4100                         return;
4101                 }
4102                 if (val == 0xffff) {
4103                         bp->fw_reset_min_msecs = 0;
4104                         us = 1;
4105                 }
4106         }
4107
4108         rc = rte_eal_alarm_set(us, bnxt_dev_recover, (void *)bp);
4109         if (rc)
4110                 PMD_DRV_LOG(ERR, "Error setting recovery alarm");
4111 }
4112
4113 uint32_t bnxt_read_fw_status_reg(struct bnxt *bp, uint32_t index)
4114 {
4115         struct bnxt_error_recovery_info *info = bp->recovery_info;
4116         uint32_t reg = info->status_regs[index];
4117         uint32_t type, offset, val = 0;
4118
4119         type = BNXT_FW_STATUS_REG_TYPE(reg);
4120         offset = BNXT_FW_STATUS_REG_OFF(reg);
4121
4122         switch (type) {
4123         case BNXT_FW_STATUS_REG_TYPE_CFG:
4124                 rte_pci_read_config(bp->pdev, &val, sizeof(val), offset);
4125                 break;
4126         case BNXT_FW_STATUS_REG_TYPE_GRC:
4127                 offset = info->mapped_status_regs[index];
4128                 /* FALLTHROUGH */
4129         case BNXT_FW_STATUS_REG_TYPE_BAR0:
4130                 val = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
4131                                        offset));
4132                 break;
4133         }
4134
4135         return val;
4136 }
4137
4138 static int bnxt_fw_reset_all(struct bnxt *bp)
4139 {
4140         struct bnxt_error_recovery_info *info = bp->recovery_info;
4141         uint32_t i;
4142         int rc = 0;
4143
4144         if (info->flags & BNXT_FLAG_ERROR_RECOVERY_HOST) {
4145                 /* Reset through master function driver */
4146                 for (i = 0; i < info->reg_array_cnt; i++)
4147                         bnxt_write_fw_reset_reg(bp, i);
4148                 /* Wait for time specified by FW after triggering reset */
4149                 rte_delay_ms(info->master_func_wait_period_after_reset);
4150         } else if (info->flags & BNXT_FLAG_ERROR_RECOVERY_CO_CPU) {
4151                 /* Reset with the help of Kong processor */
4152                 rc = bnxt_hwrm_fw_reset(bp);
4153                 if (rc)
4154                         PMD_DRV_LOG(ERR, "Failed to reset FW\n");
4155         }
4156
4157         return rc;
4158 }
4159
4160 static void bnxt_fw_reset_cb(void *arg)
4161 {
4162         struct bnxt *bp = arg;
4163         struct bnxt_error_recovery_info *info = bp->recovery_info;
4164         int rc = 0;
4165
4166         /* Only Master function can do FW reset */
4167         if (bnxt_is_master_func(bp) &&
4168             bnxt_is_recovery_enabled(bp)) {
4169                 rc = bnxt_fw_reset_all(bp);
4170                 if (rc) {
4171                         PMD_DRV_LOG(ERR, "Adapter recovery failed\n");
4172                         return;
4173                 }
4174         }
4175
4176         /* if recovery method is ERROR_RECOVERY_CO_CPU, KONG will send
4177          * EXCEPTION_FATAL_ASYNC event to all the functions
4178          * (including MASTER FUNC). After receiving this Async, all the active
4179          * drivers should treat this case as FW initiated recovery
4180          */
4181         if (info->flags & BNXT_FLAG_ERROR_RECOVERY_HOST) {
4182                 bp->fw_reset_min_msecs = BNXT_MIN_FW_READY_TIMEOUT;
4183                 bp->fw_reset_max_msecs = BNXT_MAX_FW_RESET_TIMEOUT;
4184
4185                 /* To recover from error */
4186                 rte_eal_alarm_set(US_PER_MS, bnxt_dev_reset_and_resume,
4187                                   (void *)bp);
4188         }
4189 }
4190
4191 /* Driver should poll FW heartbeat, reset_counter with the frequency
4192  * advertised by FW in HWRM_ERROR_RECOVERY_QCFG.
4193  * When the driver detects heartbeat stop or change in reset_counter,
4194  * it has to trigger a reset to recover from the error condition.
4195  * A “master PF” is the function who will have the privilege to
4196  * initiate the chimp reset. The master PF will be elected by the
4197  * firmware and will be notified through async message.
4198  */
4199 static void bnxt_check_fw_health(void *arg)
4200 {
4201         struct bnxt *bp = arg;
4202         struct bnxt_error_recovery_info *info = bp->recovery_info;
4203         uint32_t val = 0, wait_msec;
4204
4205         if (!info || !bnxt_is_recovery_enabled(bp) ||
4206             is_bnxt_in_error(bp))
4207                 return;
4208
4209         val = bnxt_read_fw_status_reg(bp, BNXT_FW_HEARTBEAT_CNT_REG);
4210         if (val == info->last_heart_beat)
4211                 goto reset;
4212
4213         info->last_heart_beat = val;
4214
4215         val = bnxt_read_fw_status_reg(bp, BNXT_FW_RECOVERY_CNT_REG);
4216         if (val != info->last_reset_counter)
4217                 goto reset;
4218
4219         info->last_reset_counter = val;
4220
4221         rte_eal_alarm_set(US_PER_MS * info->driver_polling_freq,
4222                           bnxt_check_fw_health, (void *)bp);
4223
4224         return;
4225 reset:
4226         /* Stop DMA to/from device */
4227         bp->flags |= BNXT_FLAG_FATAL_ERROR;
4228         bp->flags |= BNXT_FLAG_FW_RESET;
4229
4230         PMD_DRV_LOG(ERR, "Detected FW dead condition\n");
4231
4232         if (bnxt_is_master_func(bp))
4233                 wait_msec = info->master_func_wait_period;
4234         else
4235                 wait_msec = info->normal_func_wait_period;
4236
4237         rte_eal_alarm_set(US_PER_MS * wait_msec,
4238                           bnxt_fw_reset_cb, (void *)bp);
4239 }
4240
4241 void bnxt_schedule_fw_health_check(struct bnxt *bp)
4242 {
4243         uint32_t polling_freq;
4244
4245         pthread_mutex_lock(&bp->health_check_lock);
4246
4247         if (!bnxt_is_recovery_enabled(bp))
4248                 goto done;
4249
4250         if (bp->flags & BNXT_FLAG_FW_HEALTH_CHECK_SCHEDULED)
4251                 goto done;
4252
4253         polling_freq = bp->recovery_info->driver_polling_freq;
4254
4255         rte_eal_alarm_set(US_PER_MS * polling_freq,
4256                           bnxt_check_fw_health, (void *)bp);
4257         bp->flags |= BNXT_FLAG_FW_HEALTH_CHECK_SCHEDULED;
4258
4259 done:
4260         pthread_mutex_unlock(&bp->health_check_lock);
4261 }
4262
4263 static void bnxt_cancel_fw_health_check(struct bnxt *bp)
4264 {
4265         if (!bnxt_is_recovery_enabled(bp))
4266                 return;
4267
4268         rte_eal_alarm_cancel(bnxt_check_fw_health, (void *)bp);
4269         bp->flags &= ~BNXT_FLAG_FW_HEALTH_CHECK_SCHEDULED;
4270 }
4271
4272 static bool bnxt_vf_pciid(uint16_t device_id)
4273 {
4274         switch (device_id) {
4275         case BROADCOM_DEV_ID_57304_VF:
4276         case BROADCOM_DEV_ID_57406_VF:
4277         case BROADCOM_DEV_ID_5731X_VF:
4278         case BROADCOM_DEV_ID_5741X_VF:
4279         case BROADCOM_DEV_ID_57414_VF:
4280         case BROADCOM_DEV_ID_STRATUS_NIC_VF1:
4281         case BROADCOM_DEV_ID_STRATUS_NIC_VF2:
4282         case BROADCOM_DEV_ID_58802_VF:
4283         case BROADCOM_DEV_ID_57500_VF1:
4284         case BROADCOM_DEV_ID_57500_VF2:
4285         case BROADCOM_DEV_ID_58818_VF:
4286                 /* FALLTHROUGH */
4287                 return true;
4288         default:
4289                 return false;
4290         }
4291 }
4292
4293 /* Phase 5 device */
4294 static bool bnxt_p5_device(uint16_t device_id)
4295 {
4296         switch (device_id) {
4297         case BROADCOM_DEV_ID_57508:
4298         case BROADCOM_DEV_ID_57504:
4299         case BROADCOM_DEV_ID_57502:
4300         case BROADCOM_DEV_ID_57508_MF1:
4301         case BROADCOM_DEV_ID_57504_MF1:
4302         case BROADCOM_DEV_ID_57502_MF1:
4303         case BROADCOM_DEV_ID_57508_MF2:
4304         case BROADCOM_DEV_ID_57504_MF2:
4305         case BROADCOM_DEV_ID_57502_MF2:
4306         case BROADCOM_DEV_ID_57500_VF1:
4307         case BROADCOM_DEV_ID_57500_VF2:
4308         case BROADCOM_DEV_ID_58812:
4309         case BROADCOM_DEV_ID_58814:
4310         case BROADCOM_DEV_ID_58818:
4311         case BROADCOM_DEV_ID_58818_VF:
4312                 /* FALLTHROUGH */
4313                 return true;
4314         default:
4315                 return false;
4316         }
4317 }
4318
4319 bool bnxt_stratus_device(struct bnxt *bp)
4320 {
4321         uint16_t device_id = bp->pdev->id.device_id;
4322
4323         switch (device_id) {
4324         case BROADCOM_DEV_ID_STRATUS_NIC:
4325         case BROADCOM_DEV_ID_STRATUS_NIC_VF1:
4326         case BROADCOM_DEV_ID_STRATUS_NIC_VF2:
4327                 /* FALLTHROUGH */
4328                 return true;
4329         default:
4330                 return false;
4331         }
4332 }
4333
4334 static int bnxt_map_pci_bars(struct rte_eth_dev *eth_dev)
4335 {
4336         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
4337         struct bnxt *bp = eth_dev->data->dev_private;
4338
4339         /* enable device (incl. PCI PM wakeup), and bus-mastering */
4340         bp->bar0 = (void *)pci_dev->mem_resource[0].addr;
4341         bp->doorbell_base = (void *)pci_dev->mem_resource[2].addr;
4342         if (!bp->bar0 || !bp->doorbell_base) {
4343                 PMD_DRV_LOG(ERR, "Unable to access Hardware\n");
4344                 return -ENODEV;
4345         }
4346
4347         bp->eth_dev = eth_dev;
4348         bp->pdev = pci_dev;
4349
4350         return 0;
4351 }
4352
4353 static int bnxt_alloc_ctx_mem_blk(struct bnxt *bp,
4354                                   struct bnxt_ctx_pg_info *ctx_pg,
4355                                   uint32_t mem_size,
4356                                   const char *suffix,
4357                                   uint16_t idx)
4358 {
4359         struct bnxt_ring_mem_info *rmem = &ctx_pg->ring_mem;
4360         const struct rte_memzone *mz = NULL;
4361         char mz_name[RTE_MEMZONE_NAMESIZE];
4362         rte_iova_t mz_phys_addr;
4363         uint64_t valid_bits = 0;
4364         uint32_t sz;
4365         int i;
4366
4367         if (!mem_size)
4368                 return 0;
4369
4370         rmem->nr_pages = RTE_ALIGN_MUL_CEIL(mem_size, BNXT_PAGE_SIZE) /
4371                          BNXT_PAGE_SIZE;
4372         rmem->page_size = BNXT_PAGE_SIZE;
4373         rmem->pg_arr = ctx_pg->ctx_pg_arr;
4374         rmem->dma_arr = ctx_pg->ctx_dma_arr;
4375         rmem->flags = BNXT_RMEM_VALID_PTE_FLAG;
4376
4377         valid_bits = PTU_PTE_VALID;
4378
4379         if (rmem->nr_pages > 1) {
4380                 snprintf(mz_name, RTE_MEMZONE_NAMESIZE,
4381                          "bnxt_ctx_pg_tbl%s_%x_%d",
4382                          suffix, idx, bp->eth_dev->data->port_id);
4383                 mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0;
4384                 mz = rte_memzone_lookup(mz_name);
4385                 if (!mz) {
4386                         mz = rte_memzone_reserve_aligned(mz_name,
4387                                                 rmem->nr_pages * 8,
4388                                                 SOCKET_ID_ANY,
4389                                                 RTE_MEMZONE_2MB |
4390                                                 RTE_MEMZONE_SIZE_HINT_ONLY |
4391                                                 RTE_MEMZONE_IOVA_CONTIG,
4392                                                 BNXT_PAGE_SIZE);
4393                         if (mz == NULL)
4394                                 return -ENOMEM;
4395                 }
4396
4397                 memset(mz->addr, 0, mz->len);
4398                 mz_phys_addr = mz->iova;
4399
4400                 rmem->pg_tbl = mz->addr;
4401                 rmem->pg_tbl_map = mz_phys_addr;
4402                 rmem->pg_tbl_mz = mz;
4403         }
4404
4405         snprintf(mz_name, RTE_MEMZONE_NAMESIZE, "bnxt_ctx_%s_%x_%d",
4406                  suffix, idx, bp->eth_dev->data->port_id);
4407         mz = rte_memzone_lookup(mz_name);
4408         if (!mz) {
4409                 mz = rte_memzone_reserve_aligned(mz_name,
4410                                                  mem_size,
4411                                                  SOCKET_ID_ANY,
4412                                                  RTE_MEMZONE_1GB |
4413                                                  RTE_MEMZONE_SIZE_HINT_ONLY |
4414                                                  RTE_MEMZONE_IOVA_CONTIG,
4415                                                  BNXT_PAGE_SIZE);
4416                 if (mz == NULL)
4417                         return -ENOMEM;
4418         }
4419
4420         memset(mz->addr, 0, mz->len);
4421         mz_phys_addr = mz->iova;
4422
4423         for (sz = 0, i = 0; sz < mem_size; sz += BNXT_PAGE_SIZE, i++) {
4424                 rmem->pg_arr[i] = ((char *)mz->addr) + sz;
4425                 rmem->dma_arr[i] = mz_phys_addr + sz;
4426
4427                 if (rmem->nr_pages > 1) {
4428                         if (i == rmem->nr_pages - 2 &&
4429                             (rmem->flags & BNXT_RMEM_RING_PTE_FLAG))
4430                                 valid_bits |= PTU_PTE_NEXT_TO_LAST;
4431                         else if (i == rmem->nr_pages - 1 &&
4432                                  (rmem->flags & BNXT_RMEM_RING_PTE_FLAG))
4433                                 valid_bits |= PTU_PTE_LAST;
4434
4435                         rmem->pg_tbl[i] = rte_cpu_to_le_64(rmem->dma_arr[i] |
4436                                                            valid_bits);
4437                 }
4438         }
4439
4440         rmem->mz = mz;
4441         if (rmem->vmem_size)
4442                 rmem->vmem = (void **)mz->addr;
4443         rmem->dma_arr[0] = mz_phys_addr;
4444         return 0;
4445 }
4446
4447 static void bnxt_free_ctx_mem(struct bnxt *bp)
4448 {
4449         int i;
4450
4451         if (!bp->ctx || !(bp->ctx->flags & BNXT_CTX_FLAG_INITED))
4452                 return;
4453
4454         bp->ctx->flags &= ~BNXT_CTX_FLAG_INITED;
4455         rte_memzone_free(bp->ctx->qp_mem.ring_mem.mz);
4456         rte_memzone_free(bp->ctx->srq_mem.ring_mem.mz);
4457         rte_memzone_free(bp->ctx->cq_mem.ring_mem.mz);
4458         rte_memzone_free(bp->ctx->vnic_mem.ring_mem.mz);
4459         rte_memzone_free(bp->ctx->stat_mem.ring_mem.mz);
4460         rte_memzone_free(bp->ctx->qp_mem.ring_mem.pg_tbl_mz);
4461         rte_memzone_free(bp->ctx->srq_mem.ring_mem.pg_tbl_mz);
4462         rte_memzone_free(bp->ctx->cq_mem.ring_mem.pg_tbl_mz);
4463         rte_memzone_free(bp->ctx->vnic_mem.ring_mem.pg_tbl_mz);
4464         rte_memzone_free(bp->ctx->stat_mem.ring_mem.pg_tbl_mz);
4465
4466         for (i = 0; i < bp->ctx->tqm_fp_rings_count + 1; i++) {
4467                 if (bp->ctx->tqm_mem[i])
4468                         rte_memzone_free(bp->ctx->tqm_mem[i]->ring_mem.mz);
4469         }
4470
4471         rte_free(bp->ctx);
4472         bp->ctx = NULL;
4473 }
4474
4475 #define bnxt_roundup(x, y)   ((((x) + ((y) - 1)) / (y)) * (y))
4476
4477 #define min_t(type, x, y) ({                    \
4478         type __min1 = (x);                      \
4479         type __min2 = (y);                      \
4480         __min1 < __min2 ? __min1 : __min2; })
4481
4482 #define max_t(type, x, y) ({                    \
4483         type __max1 = (x);                      \
4484         type __max2 = (y);                      \
4485         __max1 > __max2 ? __max1 : __max2; })
4486
4487 #define clamp_t(type, _x, min, max)     min_t(type, max_t(type, _x, min), max)
4488
4489 int bnxt_alloc_ctx_mem(struct bnxt *bp)
4490 {
4491         struct bnxt_ctx_pg_info *ctx_pg;
4492         struct bnxt_ctx_mem_info *ctx;
4493         uint32_t mem_size, ena, entries;
4494         uint32_t entries_sp, min;
4495         int i, rc;
4496
4497         rc = bnxt_hwrm_func_backing_store_qcaps(bp);
4498         if (rc) {
4499                 PMD_DRV_LOG(ERR, "Query context mem capability failed\n");
4500                 return rc;
4501         }
4502         ctx = bp->ctx;
4503         if (!ctx || (ctx->flags & BNXT_CTX_FLAG_INITED))
4504                 return 0;
4505
4506         ctx_pg = &ctx->qp_mem;
4507         ctx_pg->entries = ctx->qp_min_qp1_entries + ctx->qp_max_l2_entries;
4508         if (ctx->qp_entry_size) {
4509                 mem_size = ctx->qp_entry_size * ctx_pg->entries;
4510                 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "qp_mem", 0);
4511                 if (rc)
4512                         return rc;
4513         }
4514
4515         ctx_pg = &ctx->srq_mem;
4516         ctx_pg->entries = ctx->srq_max_l2_entries;
4517         if (ctx->srq_entry_size) {
4518                 mem_size = ctx->srq_entry_size * ctx_pg->entries;
4519                 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "srq_mem", 0);
4520                 if (rc)
4521                         return rc;
4522         }
4523
4524         ctx_pg = &ctx->cq_mem;
4525         ctx_pg->entries = ctx->cq_max_l2_entries;
4526         if (ctx->cq_entry_size) {
4527                 mem_size = ctx->cq_entry_size * ctx_pg->entries;
4528                 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "cq_mem", 0);
4529                 if (rc)
4530                         return rc;
4531         }
4532
4533         ctx_pg = &ctx->vnic_mem;
4534         ctx_pg->entries = ctx->vnic_max_vnic_entries +
4535                 ctx->vnic_max_ring_table_entries;
4536         if (ctx->vnic_entry_size) {
4537                 mem_size = ctx->vnic_entry_size * ctx_pg->entries;
4538                 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "vnic_mem", 0);
4539                 if (rc)
4540                         return rc;
4541         }
4542
4543         ctx_pg = &ctx->stat_mem;
4544         ctx_pg->entries = ctx->stat_max_entries;
4545         if (ctx->stat_entry_size) {
4546                 mem_size = ctx->stat_entry_size * ctx_pg->entries;
4547                 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "stat_mem", 0);
4548                 if (rc)
4549                         return rc;
4550         }
4551
4552         min = ctx->tqm_min_entries_per_ring;
4553
4554         entries_sp = ctx->qp_max_l2_entries +
4555                      ctx->vnic_max_vnic_entries +
4556                      2 * ctx->qp_min_qp1_entries + min;
4557         entries_sp = bnxt_roundup(entries_sp, ctx->tqm_entries_multiple);
4558
4559         entries = ctx->qp_max_l2_entries + ctx->qp_min_qp1_entries;
4560         entries = bnxt_roundup(entries, ctx->tqm_entries_multiple);
4561         entries = clamp_t(uint32_t, entries, min,
4562                           ctx->tqm_max_entries_per_ring);
4563         for (i = 0, ena = 0; i < ctx->tqm_fp_rings_count + 1; i++) {
4564                 /* i=0 is for TQM_SP. i=1 to i=8 applies to RING0 to RING7.
4565                  * i > 8 is other ext rings.
4566                  */
4567                 ctx_pg = ctx->tqm_mem[i];
4568                 ctx_pg->entries = i ? entries : entries_sp;
4569                 if (ctx->tqm_entry_size) {
4570                         mem_size = ctx->tqm_entry_size * ctx_pg->entries;
4571                         rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size,
4572                                                     "tqm_mem", i);
4573                         if (rc)
4574                                 return rc;
4575                 }
4576                 if (i < BNXT_MAX_TQM_LEGACY_RINGS)
4577                         ena |= HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_SP << i;
4578                 else
4579                         ena |= HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_RING8;
4580         }
4581
4582         ena |= FUNC_BACKING_STORE_CFG_INPUT_DFLT_ENABLES;
4583         rc = bnxt_hwrm_func_backing_store_cfg(bp, ena);
4584         if (rc)
4585                 PMD_DRV_LOG(ERR,
4586                             "Failed to configure context mem: rc = %d\n", rc);
4587         else
4588                 ctx->flags |= BNXT_CTX_FLAG_INITED;
4589
4590         return rc;
4591 }
4592
4593 static int bnxt_alloc_stats_mem(struct bnxt *bp)
4594 {
4595         struct rte_pci_device *pci_dev = bp->pdev;
4596         char mz_name[RTE_MEMZONE_NAMESIZE];
4597         const struct rte_memzone *mz = NULL;
4598         uint32_t total_alloc_len;
4599         rte_iova_t mz_phys_addr;
4600
4601         if (pci_dev->id.device_id == BROADCOM_DEV_ID_NS2)
4602                 return 0;
4603
4604         snprintf(mz_name, RTE_MEMZONE_NAMESIZE,
4605                  "bnxt_" PCI_PRI_FMT "-%s", pci_dev->addr.domain,
4606                  pci_dev->addr.bus, pci_dev->addr.devid,
4607                  pci_dev->addr.function, "rx_port_stats");
4608         mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0;
4609         mz = rte_memzone_lookup(mz_name);
4610         total_alloc_len =
4611                 RTE_CACHE_LINE_ROUNDUP(sizeof(struct rx_port_stats) +
4612                                        sizeof(struct rx_port_stats_ext) + 512);
4613         if (!mz) {
4614                 mz = rte_memzone_reserve(mz_name, total_alloc_len,
4615                                          SOCKET_ID_ANY,
4616                                          RTE_MEMZONE_2MB |
4617                                          RTE_MEMZONE_SIZE_HINT_ONLY |
4618                                          RTE_MEMZONE_IOVA_CONTIG);
4619                 if (mz == NULL)
4620                         return -ENOMEM;
4621         }
4622         memset(mz->addr, 0, mz->len);
4623         mz_phys_addr = mz->iova;
4624
4625         bp->rx_mem_zone = (const void *)mz;
4626         bp->hw_rx_port_stats = mz->addr;
4627         bp->hw_rx_port_stats_map = mz_phys_addr;
4628
4629         snprintf(mz_name, RTE_MEMZONE_NAMESIZE,
4630                  "bnxt_" PCI_PRI_FMT "-%s", pci_dev->addr.domain,
4631                  pci_dev->addr.bus, pci_dev->addr.devid,
4632                  pci_dev->addr.function, "tx_port_stats");
4633         mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0;
4634         mz = rte_memzone_lookup(mz_name);
4635         total_alloc_len =
4636                 RTE_CACHE_LINE_ROUNDUP(sizeof(struct tx_port_stats) +
4637                                        sizeof(struct tx_port_stats_ext) + 512);
4638         if (!mz) {
4639                 mz = rte_memzone_reserve(mz_name,
4640                                          total_alloc_len,
4641                                          SOCKET_ID_ANY,
4642                                          RTE_MEMZONE_2MB |
4643                                          RTE_MEMZONE_SIZE_HINT_ONLY |
4644                                          RTE_MEMZONE_IOVA_CONTIG);
4645                 if (mz == NULL)
4646                         return -ENOMEM;
4647         }
4648         memset(mz->addr, 0, mz->len);
4649         mz_phys_addr = mz->iova;
4650
4651         bp->tx_mem_zone = (const void *)mz;
4652         bp->hw_tx_port_stats = mz->addr;
4653         bp->hw_tx_port_stats_map = mz_phys_addr;
4654         bp->flags |= BNXT_FLAG_PORT_STATS;
4655
4656         /* Display extended statistics if FW supports it */
4657         if (bp->hwrm_spec_code < HWRM_SPEC_CODE_1_8_4 ||
4658             bp->hwrm_spec_code == HWRM_SPEC_CODE_1_9_0 ||
4659             !(bp->flags & BNXT_FLAG_EXT_STATS_SUPPORTED))
4660                 return 0;
4661
4662         bp->hw_rx_port_stats_ext = (void *)
4663                 ((uint8_t *)bp->hw_rx_port_stats +
4664                  sizeof(struct rx_port_stats));
4665         bp->hw_rx_port_stats_ext_map = bp->hw_rx_port_stats_map +
4666                 sizeof(struct rx_port_stats);
4667         bp->flags |= BNXT_FLAG_EXT_RX_PORT_STATS;
4668
4669         if (bp->hwrm_spec_code < HWRM_SPEC_CODE_1_9_2 ||
4670             bp->flags & BNXT_FLAG_EXT_STATS_SUPPORTED) {
4671                 bp->hw_tx_port_stats_ext = (void *)
4672                         ((uint8_t *)bp->hw_tx_port_stats +
4673                          sizeof(struct tx_port_stats));
4674                 bp->hw_tx_port_stats_ext_map =
4675                         bp->hw_tx_port_stats_map +
4676                         sizeof(struct tx_port_stats);
4677                 bp->flags |= BNXT_FLAG_EXT_TX_PORT_STATS;
4678         }
4679
4680         return 0;
4681 }
4682
4683 static int bnxt_setup_mac_addr(struct rte_eth_dev *eth_dev)
4684 {
4685         struct bnxt *bp = eth_dev->data->dev_private;
4686         int rc = 0;
4687
4688         eth_dev->data->mac_addrs = rte_zmalloc("bnxt_mac_addr_tbl",
4689                                                RTE_ETHER_ADDR_LEN *
4690                                                bp->max_l2_ctx,
4691                                                0);
4692         if (eth_dev->data->mac_addrs == NULL) {
4693                 PMD_DRV_LOG(ERR, "Failed to alloc MAC addr tbl\n");
4694                 return -ENOMEM;
4695         }
4696
4697         if (!BNXT_HAS_DFLT_MAC_SET(bp)) {
4698                 if (BNXT_PF(bp))
4699                         return -EINVAL;
4700
4701                 /* Generate a random MAC address, if none was assigned by PF */
4702                 PMD_DRV_LOG(INFO, "VF MAC address not assigned by Host PF\n");
4703                 bnxt_eth_hw_addr_random(bp->mac_addr);
4704                 PMD_DRV_LOG(INFO,
4705                             "Assign random MAC:%02X:%02X:%02X:%02X:%02X:%02X\n",
4706                             bp->mac_addr[0], bp->mac_addr[1], bp->mac_addr[2],
4707                             bp->mac_addr[3], bp->mac_addr[4], bp->mac_addr[5]);
4708
4709                 rc = bnxt_hwrm_set_mac(bp);
4710                 if (rc)
4711                         return rc;
4712         }
4713
4714         /* Copy the permanent MAC from the FUNC_QCAPS response */
4715         memcpy(&eth_dev->data->mac_addrs[0], bp->mac_addr, RTE_ETHER_ADDR_LEN);
4716
4717         return rc;
4718 }
4719
4720 static int bnxt_restore_dflt_mac(struct bnxt *bp)
4721 {
4722         int rc = 0;
4723
4724         /* MAC is already configured in FW */
4725         if (BNXT_HAS_DFLT_MAC_SET(bp))
4726                 return 0;
4727
4728         /* Restore the old MAC configured */
4729         rc = bnxt_hwrm_set_mac(bp);
4730         if (rc)
4731                 PMD_DRV_LOG(ERR, "Failed to restore MAC address\n");
4732
4733         return rc;
4734 }
4735
4736 static void bnxt_config_vf_req_fwd(struct bnxt *bp)
4737 {
4738         if (!BNXT_PF(bp))
4739                 return;
4740
4741         memset(bp->pf->vf_req_fwd, 0, sizeof(bp->pf->vf_req_fwd));
4742
4743         if (!(bp->fw_cap & BNXT_FW_CAP_LINK_ADMIN))
4744                 BNXT_HWRM_CMD_TO_FORWARD(HWRM_PORT_PHY_QCFG);
4745         BNXT_HWRM_CMD_TO_FORWARD(HWRM_FUNC_CFG);
4746         BNXT_HWRM_CMD_TO_FORWARD(HWRM_FUNC_VF_CFG);
4747         BNXT_HWRM_CMD_TO_FORWARD(HWRM_CFA_L2_FILTER_ALLOC);
4748         BNXT_HWRM_CMD_TO_FORWARD(HWRM_OEM_CMD);
4749 }
4750
4751 uint16_t
4752 bnxt_get_svif(uint16_t port_id, bool func_svif,
4753               enum bnxt_ulp_intf_type type)
4754 {
4755         struct rte_eth_dev *eth_dev;
4756         struct bnxt *bp;
4757
4758         eth_dev = &rte_eth_devices[port_id];
4759         if (BNXT_ETH_DEV_IS_REPRESENTOR(eth_dev)) {
4760                 struct bnxt_representor *vfr = eth_dev->data->dev_private;
4761                 if (!vfr)
4762                         return 0;
4763
4764                 if (type == BNXT_ULP_INTF_TYPE_VF_REP)
4765                         return vfr->svif;
4766
4767                 eth_dev = vfr->parent_dev;
4768         }
4769
4770         bp = eth_dev->data->dev_private;
4771
4772         return func_svif ? bp->func_svif : bp->port_svif;
4773 }
4774
4775 uint16_t
4776 bnxt_get_vnic_id(uint16_t port, enum bnxt_ulp_intf_type type)
4777 {
4778         struct rte_eth_dev *eth_dev;
4779         struct bnxt_vnic_info *vnic;
4780         struct bnxt *bp;
4781
4782         eth_dev = &rte_eth_devices[port];
4783         if (BNXT_ETH_DEV_IS_REPRESENTOR(eth_dev)) {
4784                 struct bnxt_representor *vfr = eth_dev->data->dev_private;
4785                 if (!vfr)
4786                         return 0;
4787
4788                 if (type == BNXT_ULP_INTF_TYPE_VF_REP)
4789                         return vfr->dflt_vnic_id;
4790
4791                 eth_dev = vfr->parent_dev;
4792         }
4793
4794         bp = eth_dev->data->dev_private;
4795
4796         vnic = BNXT_GET_DEFAULT_VNIC(bp);
4797
4798         return vnic->fw_vnic_id;
4799 }
4800
4801 uint16_t
4802 bnxt_get_fw_func_id(uint16_t port, enum bnxt_ulp_intf_type type)
4803 {
4804         struct rte_eth_dev *eth_dev;
4805         struct bnxt *bp;
4806
4807         eth_dev = &rte_eth_devices[port];
4808         if (BNXT_ETH_DEV_IS_REPRESENTOR(eth_dev)) {
4809                 struct bnxt_representor *vfr = eth_dev->data->dev_private;
4810                 if (!vfr)
4811                         return 0;
4812
4813                 if (type == BNXT_ULP_INTF_TYPE_VF_REP)
4814                         return vfr->fw_fid;
4815
4816                 eth_dev = vfr->parent_dev;
4817         }
4818
4819         bp = eth_dev->data->dev_private;
4820
4821         return bp->fw_fid;
4822 }
4823
4824 enum bnxt_ulp_intf_type
4825 bnxt_get_interface_type(uint16_t port)
4826 {
4827         struct rte_eth_dev *eth_dev;
4828         struct bnxt *bp;
4829
4830         eth_dev = &rte_eth_devices[port];
4831         if (BNXT_ETH_DEV_IS_REPRESENTOR(eth_dev))
4832                 return BNXT_ULP_INTF_TYPE_VF_REP;
4833
4834         bp = eth_dev->data->dev_private;
4835         if (BNXT_PF(bp))
4836                 return BNXT_ULP_INTF_TYPE_PF;
4837         else if (BNXT_VF_IS_TRUSTED(bp))
4838                 return BNXT_ULP_INTF_TYPE_TRUSTED_VF;
4839         else if (BNXT_VF(bp))
4840                 return BNXT_ULP_INTF_TYPE_VF;
4841
4842         return BNXT_ULP_INTF_TYPE_INVALID;
4843 }
4844
4845 uint16_t
4846 bnxt_get_phy_port_id(uint16_t port_id)
4847 {
4848         struct bnxt_representor *vfr;
4849         struct rte_eth_dev *eth_dev;
4850         struct bnxt *bp;
4851
4852         eth_dev = &rte_eth_devices[port_id];
4853         if (BNXT_ETH_DEV_IS_REPRESENTOR(eth_dev)) {
4854                 vfr = eth_dev->data->dev_private;
4855                 if (!vfr)
4856                         return 0;
4857
4858                 eth_dev = vfr->parent_dev;
4859         }
4860
4861         bp = eth_dev->data->dev_private;
4862
4863         return BNXT_PF(bp) ? bp->pf->port_id : bp->parent->port_id;
4864 }
4865
4866 uint16_t
4867 bnxt_get_parif(uint16_t port_id, enum bnxt_ulp_intf_type type)
4868 {
4869         struct rte_eth_dev *eth_dev;
4870         struct bnxt *bp;
4871
4872         eth_dev = &rte_eth_devices[port_id];
4873         if (BNXT_ETH_DEV_IS_REPRESENTOR(eth_dev)) {
4874                 struct bnxt_representor *vfr = eth_dev->data->dev_private;
4875                 if (!vfr)
4876                         return 0;
4877
4878                 if (type == BNXT_ULP_INTF_TYPE_VF_REP)
4879                         return vfr->fw_fid - 1;
4880
4881                 eth_dev = vfr->parent_dev;
4882         }
4883
4884         bp = eth_dev->data->dev_private;
4885
4886         return BNXT_PF(bp) ? bp->fw_fid - 1 : bp->parent->fid - 1;
4887 }
4888
4889 uint16_t
4890 bnxt_get_vport(uint16_t port_id)
4891 {
4892         return (1 << bnxt_get_phy_port_id(port_id));
4893 }
4894
4895 static void bnxt_alloc_error_recovery_info(struct bnxt *bp)
4896 {
4897         struct bnxt_error_recovery_info *info = bp->recovery_info;
4898
4899         if (info) {
4900                 if (!(bp->fw_cap & BNXT_FW_CAP_HCOMM_FW_STATUS))
4901                         memset(info, 0, sizeof(*info));
4902                 return;
4903         }
4904
4905         if (!(bp->fw_cap & BNXT_FW_CAP_ERROR_RECOVERY))
4906                 return;
4907
4908         info = rte_zmalloc("bnxt_hwrm_error_recovery_qcfg",
4909                            sizeof(*info), 0);
4910         if (!info)
4911                 bp->fw_cap &= ~BNXT_FW_CAP_ERROR_RECOVERY;
4912
4913         bp->recovery_info = info;
4914 }
4915
4916 static void bnxt_check_fw_status(struct bnxt *bp)
4917 {
4918         uint32_t fw_status;
4919
4920         if (!(bp->recovery_info &&
4921               (bp->fw_cap & BNXT_FW_CAP_HCOMM_FW_STATUS)))
4922                 return;
4923
4924         fw_status = bnxt_read_fw_status_reg(bp, BNXT_FW_STATUS_REG);
4925         if (fw_status != BNXT_FW_STATUS_HEALTHY)
4926                 PMD_DRV_LOG(ERR, "Firmware not responding, status: %#x\n",
4927                             fw_status);
4928 }
4929
4930 static int bnxt_map_hcomm_fw_status_reg(struct bnxt *bp)
4931 {
4932         struct bnxt_error_recovery_info *info = bp->recovery_info;
4933         uint32_t status_loc;
4934         uint32_t sig_ver;
4935
4936         rte_write32(HCOMM_STATUS_STRUCT_LOC, (uint8_t *)bp->bar0 +
4937                     BNXT_GRCPF_REG_WINDOW_BASE_OUT + 4);
4938         sig_ver = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
4939                                    BNXT_GRCP_WINDOW_2_BASE +
4940                                    offsetof(struct hcomm_status,
4941                                             sig_ver)));
4942         /* If the signature is absent, then FW does not support this feature */
4943         if ((sig_ver & HCOMM_STATUS_SIGNATURE_MASK) !=
4944             HCOMM_STATUS_SIGNATURE_VAL)
4945                 return 0;
4946
4947         if (!info) {
4948                 info = rte_zmalloc("bnxt_hwrm_error_recovery_qcfg",
4949                                    sizeof(*info), 0);
4950                 if (!info)
4951                         return -ENOMEM;
4952                 bp->recovery_info = info;
4953         } else {
4954                 memset(info, 0, sizeof(*info));
4955         }
4956
4957         status_loc = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
4958                                       BNXT_GRCP_WINDOW_2_BASE +
4959                                       offsetof(struct hcomm_status,
4960                                                fw_status_loc)));
4961
4962         /* Only pre-map the FW health status GRC register */
4963         if (BNXT_FW_STATUS_REG_TYPE(status_loc) != BNXT_FW_STATUS_REG_TYPE_GRC)
4964                 return 0;
4965
4966         info->status_regs[BNXT_FW_STATUS_REG] = status_loc;
4967         info->mapped_status_regs[BNXT_FW_STATUS_REG] =
4968                 BNXT_GRCP_WINDOW_2_BASE + (status_loc & BNXT_GRCP_OFFSET_MASK);
4969
4970         rte_write32((status_loc & BNXT_GRCP_BASE_MASK), (uint8_t *)bp->bar0 +
4971                     BNXT_GRCPF_REG_WINDOW_BASE_OUT + 4);
4972
4973         bp->fw_cap |= BNXT_FW_CAP_HCOMM_FW_STATUS;
4974
4975         return 0;
4976 }
4977
4978 /* This function gets the FW version along with the
4979  * capabilities(MAX and current) of the function, vnic,
4980  * error recovery, phy and other chip related info
4981  */
4982 static int bnxt_get_config(struct bnxt *bp)
4983 {
4984         uint16_t mtu;
4985         int rc = 0;
4986
4987         bp->fw_cap = 0;
4988
4989         rc = bnxt_map_hcomm_fw_status_reg(bp);
4990         if (rc)
4991                 return rc;
4992
4993         rc = bnxt_hwrm_ver_get(bp, DFLT_HWRM_CMD_TIMEOUT);
4994         if (rc) {
4995                 bnxt_check_fw_status(bp);
4996                 return rc;
4997         }
4998
4999         rc = bnxt_hwrm_func_reset(bp);
5000         if (rc)
5001                 return -EIO;
5002
5003         rc = bnxt_hwrm_vnic_qcaps(bp);
5004         if (rc)
5005                 return rc;
5006
5007         rc = bnxt_hwrm_queue_qportcfg(bp);
5008         if (rc)
5009                 return rc;
5010
5011         /* Get the MAX capabilities for this function.
5012          * This function also allocates context memory for TQM rings and
5013          * informs the firmware about this allocated backing store memory.
5014          */
5015         rc = bnxt_hwrm_func_qcaps(bp);
5016         if (rc)
5017                 return rc;
5018
5019         rc = bnxt_hwrm_func_qcfg(bp, &mtu);
5020         if (rc)
5021                 return rc;
5022
5023         rc = bnxt_hwrm_cfa_adv_flow_mgmt_qcaps(bp);
5024         if (rc)
5025                 return rc;
5026
5027         bnxt_hwrm_port_mac_qcfg(bp);
5028
5029         bnxt_hwrm_parent_pf_qcfg(bp);
5030
5031         bnxt_hwrm_port_phy_qcaps(bp);
5032
5033         bnxt_alloc_error_recovery_info(bp);
5034         /* Get the adapter error recovery support info */
5035         rc = bnxt_hwrm_error_recovery_qcfg(bp);
5036         if (rc)
5037                 bp->fw_cap &= ~BNXT_FW_CAP_ERROR_RECOVERY;
5038
5039         bnxt_hwrm_port_led_qcaps(bp);
5040
5041         return 0;
5042 }
5043
5044 static int
5045 bnxt_init_locks(struct bnxt *bp)
5046 {
5047         int err;
5048
5049         err = pthread_mutex_init(&bp->flow_lock, NULL);
5050         if (err) {
5051                 PMD_DRV_LOG(ERR, "Unable to initialize flow_lock\n");
5052                 return err;
5053         }
5054
5055         err = pthread_mutex_init(&bp->def_cp_lock, NULL);
5056         if (err) {
5057                 PMD_DRV_LOG(ERR, "Unable to initialize def_cp_lock\n");
5058                 return err;
5059         }
5060
5061         err = pthread_mutex_init(&bp->health_check_lock, NULL);
5062         if (err) {
5063                 PMD_DRV_LOG(ERR, "Unable to initialize health_check_lock\n");
5064                 return err;
5065         }
5066
5067         err = pthread_mutex_init(&bp->err_recovery_lock, NULL);
5068         if (err)
5069                 PMD_DRV_LOG(ERR, "Unable to initialize err_recovery_lock\n");
5070
5071         return err;
5072 }
5073
5074 static int bnxt_init_resources(struct bnxt *bp, bool reconfig_dev)
5075 {
5076         int rc = 0;
5077
5078         rc = bnxt_get_config(bp);
5079         if (rc)
5080                 return rc;
5081
5082         if (!reconfig_dev) {
5083                 rc = bnxt_setup_mac_addr(bp->eth_dev);
5084                 if (rc)
5085                         return rc;
5086         } else {
5087                 rc = bnxt_restore_dflt_mac(bp);
5088                 if (rc)
5089                         return rc;
5090         }
5091
5092         bnxt_config_vf_req_fwd(bp);
5093
5094         rc = bnxt_hwrm_func_driver_register(bp);
5095         if (rc) {
5096                 PMD_DRV_LOG(ERR, "Failed to register driver");
5097                 return -EBUSY;
5098         }
5099
5100         if (BNXT_PF(bp)) {
5101                 if (bp->pdev->max_vfs) {
5102                         rc = bnxt_hwrm_allocate_vfs(bp, bp->pdev->max_vfs);
5103                         if (rc) {
5104                                 PMD_DRV_LOG(ERR, "Failed to allocate VFs\n");
5105                                 return rc;
5106                         }
5107                 } else {
5108                         rc = bnxt_hwrm_allocate_pf_only(bp);
5109                         if (rc) {
5110                                 PMD_DRV_LOG(ERR,
5111                                             "Failed to allocate PF resources");
5112                                 return rc;
5113                         }
5114                 }
5115         }
5116
5117         rc = bnxt_alloc_mem(bp, reconfig_dev);
5118         if (rc)
5119                 return rc;
5120
5121         rc = bnxt_setup_int(bp);
5122         if (rc)
5123                 return rc;
5124
5125         rc = bnxt_request_int(bp);
5126         if (rc)
5127                 return rc;
5128
5129         rc = bnxt_init_ctx_mem(bp);
5130         if (rc) {
5131                 PMD_DRV_LOG(ERR, "Failed to init adv_flow_counters\n");
5132                 return rc;
5133         }
5134
5135         return 0;
5136 }
5137
5138 static int
5139 bnxt_parse_devarg_truflow(__rte_unused const char *key,
5140                           const char *value, void *opaque_arg)
5141 {
5142         struct bnxt *bp = opaque_arg;
5143         unsigned long truflow;
5144         char *end = NULL;
5145
5146         if (!value || !opaque_arg) {
5147                 PMD_DRV_LOG(ERR,
5148                             "Invalid parameter passed to truflow devargs.\n");
5149                 return -EINVAL;
5150         }
5151
5152         truflow = strtoul(value, &end, 10);
5153         if (end == NULL || *end != '\0' ||
5154             (truflow == ULONG_MAX && errno == ERANGE)) {
5155                 PMD_DRV_LOG(ERR,
5156                             "Invalid parameter passed to truflow devargs.\n");
5157                 return -EINVAL;
5158         }
5159
5160         if (BNXT_DEVARG_TRUFLOW_INVALID(truflow)) {
5161                 PMD_DRV_LOG(ERR,
5162                             "Invalid value passed to truflow devargs.\n");
5163                 return -EINVAL;
5164         }
5165
5166         if (truflow) {
5167                 bp->flags |= BNXT_FLAG_TRUFLOW_EN;
5168                 PMD_DRV_LOG(INFO, "Host-based truflow feature enabled.\n");
5169         } else {
5170                 bp->flags &= ~BNXT_FLAG_TRUFLOW_EN;
5171                 PMD_DRV_LOG(INFO, "Host-based truflow feature disabled.\n");
5172         }
5173
5174         return 0;
5175 }
5176
5177 static int
5178 bnxt_parse_devarg_flow_xstat(__rte_unused const char *key,
5179                              const char *value, void *opaque_arg)
5180 {
5181         struct bnxt *bp = opaque_arg;
5182         unsigned long flow_xstat;
5183         char *end = NULL;
5184
5185         if (!value || !opaque_arg) {
5186                 PMD_DRV_LOG(ERR,
5187                             "Invalid parameter passed to flow_xstat devarg.\n");
5188                 return -EINVAL;
5189         }
5190
5191         flow_xstat = strtoul(value, &end, 10);
5192         if (end == NULL || *end != '\0' ||
5193             (flow_xstat == ULONG_MAX && errno == ERANGE)) {
5194                 PMD_DRV_LOG(ERR,
5195                             "Invalid parameter passed to flow_xstat devarg.\n");
5196                 return -EINVAL;
5197         }
5198
5199         if (BNXT_DEVARG_FLOW_XSTAT_INVALID(flow_xstat)) {
5200                 PMD_DRV_LOG(ERR,
5201                             "Invalid value passed to flow_xstat devarg.\n");
5202                 return -EINVAL;
5203         }
5204
5205         bp->flags |= BNXT_FLAG_FLOW_XSTATS_EN;
5206         if (BNXT_FLOW_XSTATS_EN(bp))
5207                 PMD_DRV_LOG(INFO, "flow_xstat feature enabled.\n");
5208
5209         return 0;
5210 }
5211
5212 static int
5213 bnxt_parse_devarg_max_num_kflows(__rte_unused const char *key,
5214                                         const char *value, void *opaque_arg)
5215 {
5216         struct bnxt *bp = opaque_arg;
5217         unsigned long max_num_kflows;
5218         char *end = NULL;
5219
5220         if (!value || !opaque_arg) {
5221                 PMD_DRV_LOG(ERR,
5222                         "Invalid parameter passed to max_num_kflows devarg.\n");
5223                 return -EINVAL;
5224         }
5225
5226         max_num_kflows = strtoul(value, &end, 10);
5227         if (end == NULL || *end != '\0' ||
5228                 (max_num_kflows == ULONG_MAX && errno == ERANGE)) {
5229                 PMD_DRV_LOG(ERR,
5230                         "Invalid parameter passed to max_num_kflows devarg.\n");
5231                 return -EINVAL;
5232         }
5233
5234         if (bnxt_devarg_max_num_kflow_invalid(max_num_kflows)) {
5235                 PMD_DRV_LOG(ERR,
5236                         "Invalid value passed to max_num_kflows devarg.\n");
5237                 return -EINVAL;
5238         }
5239
5240         bp->max_num_kflows = max_num_kflows;
5241         if (bp->max_num_kflows)
5242                 PMD_DRV_LOG(INFO, "max_num_kflows set as %ldK.\n",
5243                                 max_num_kflows);
5244
5245         return 0;
5246 }
5247
5248 static int
5249 bnxt_parse_devarg_rep_is_pf(__rte_unused const char *key,
5250                             const char *value, void *opaque_arg)
5251 {
5252         struct bnxt_representor *vfr_bp = opaque_arg;
5253         unsigned long rep_is_pf;
5254         char *end = NULL;
5255
5256         if (!value || !opaque_arg) {
5257                 PMD_DRV_LOG(ERR,
5258                             "Invalid parameter passed to rep_is_pf devargs.\n");
5259                 return -EINVAL;
5260         }
5261
5262         rep_is_pf = strtoul(value, &end, 10);
5263         if (end == NULL || *end != '\0' ||
5264             (rep_is_pf == ULONG_MAX && errno == ERANGE)) {
5265                 PMD_DRV_LOG(ERR,
5266                             "Invalid parameter passed to rep_is_pf devargs.\n");
5267                 return -EINVAL;
5268         }
5269
5270         if (BNXT_DEVARG_REP_IS_PF_INVALID(rep_is_pf)) {
5271                 PMD_DRV_LOG(ERR,
5272                             "Invalid value passed to rep_is_pf devargs.\n");
5273                 return -EINVAL;
5274         }
5275
5276         vfr_bp->flags |= rep_is_pf;
5277         if (BNXT_REP_PF(vfr_bp))
5278                 PMD_DRV_LOG(INFO, "PF representor\n");
5279         else
5280                 PMD_DRV_LOG(INFO, "VF representor\n");
5281
5282         return 0;
5283 }
5284
5285 static int
5286 bnxt_parse_devarg_rep_based_pf(__rte_unused const char *key,
5287                                const char *value, void *opaque_arg)
5288 {
5289         struct bnxt_representor *vfr_bp = opaque_arg;
5290         unsigned long rep_based_pf;
5291         char *end = NULL;
5292
5293         if (!value || !opaque_arg) {
5294                 PMD_DRV_LOG(ERR,
5295                             "Invalid parameter passed to rep_based_pf "
5296                             "devargs.\n");
5297                 return -EINVAL;
5298         }
5299
5300         rep_based_pf = strtoul(value, &end, 10);
5301         if (end == NULL || *end != '\0' ||
5302             (rep_based_pf == ULONG_MAX && errno == ERANGE)) {
5303                 PMD_DRV_LOG(ERR,
5304                             "Invalid parameter passed to rep_based_pf "
5305                             "devargs.\n");
5306                 return -EINVAL;
5307         }
5308
5309         if (BNXT_DEVARG_REP_BASED_PF_INVALID(rep_based_pf)) {
5310                 PMD_DRV_LOG(ERR,
5311                             "Invalid value passed to rep_based_pf devargs.\n");
5312                 return -EINVAL;
5313         }
5314
5315         vfr_bp->rep_based_pf = rep_based_pf;
5316         vfr_bp->flags |= BNXT_REP_BASED_PF_VALID;
5317
5318         PMD_DRV_LOG(INFO, "rep-based-pf = %d\n", vfr_bp->rep_based_pf);
5319
5320         return 0;
5321 }
5322
5323 static int
5324 bnxt_parse_devarg_rep_q_r2f(__rte_unused const char *key,
5325                             const char *value, void *opaque_arg)
5326 {
5327         struct bnxt_representor *vfr_bp = opaque_arg;
5328         unsigned long rep_q_r2f;
5329         char *end = NULL;
5330
5331         if (!value || !opaque_arg) {
5332                 PMD_DRV_LOG(ERR,
5333                             "Invalid parameter passed to rep_q_r2f "
5334                             "devargs.\n");
5335                 return -EINVAL;
5336         }
5337
5338         rep_q_r2f = strtoul(value, &end, 10);
5339         if (end == NULL || *end != '\0' ||
5340             (rep_q_r2f == ULONG_MAX && errno == ERANGE)) {
5341                 PMD_DRV_LOG(ERR,
5342                             "Invalid parameter passed to rep_q_r2f "
5343                             "devargs.\n");
5344                 return -EINVAL;
5345         }
5346
5347         if (BNXT_DEVARG_REP_Q_R2F_INVALID(rep_q_r2f)) {
5348                 PMD_DRV_LOG(ERR,
5349                             "Invalid value passed to rep_q_r2f devargs.\n");
5350                 return -EINVAL;
5351         }
5352
5353         vfr_bp->rep_q_r2f = rep_q_r2f;
5354         vfr_bp->flags |= BNXT_REP_Q_R2F_VALID;
5355         PMD_DRV_LOG(INFO, "rep-q-r2f = %d\n", vfr_bp->rep_q_r2f);
5356
5357         return 0;
5358 }
5359
5360 static int
5361 bnxt_parse_devarg_rep_q_f2r(__rte_unused const char *key,
5362                             const char *value, void *opaque_arg)
5363 {
5364         struct bnxt_representor *vfr_bp = opaque_arg;
5365         unsigned long rep_q_f2r;
5366         char *end = NULL;
5367
5368         if (!value || !opaque_arg) {
5369                 PMD_DRV_LOG(ERR,
5370                             "Invalid parameter passed to rep_q_f2r "
5371                             "devargs.\n");
5372                 return -EINVAL;
5373         }
5374
5375         rep_q_f2r = strtoul(value, &end, 10);
5376         if (end == NULL || *end != '\0' ||
5377             (rep_q_f2r == ULONG_MAX && errno == ERANGE)) {
5378                 PMD_DRV_LOG(ERR,
5379                             "Invalid parameter passed to rep_q_f2r "
5380                             "devargs.\n");
5381                 return -EINVAL;
5382         }
5383
5384         if (BNXT_DEVARG_REP_Q_F2R_INVALID(rep_q_f2r)) {
5385                 PMD_DRV_LOG(ERR,
5386                             "Invalid value passed to rep_q_f2r devargs.\n");
5387                 return -EINVAL;
5388         }
5389
5390         vfr_bp->rep_q_f2r = rep_q_f2r;
5391         vfr_bp->flags |= BNXT_REP_Q_F2R_VALID;
5392         PMD_DRV_LOG(INFO, "rep-q-f2r = %d\n", vfr_bp->rep_q_f2r);
5393
5394         return 0;
5395 }
5396
5397 static int
5398 bnxt_parse_devarg_rep_fc_r2f(__rte_unused const char *key,
5399                              const char *value, void *opaque_arg)
5400 {
5401         struct bnxt_representor *vfr_bp = opaque_arg;
5402         unsigned long rep_fc_r2f;
5403         char *end = NULL;
5404
5405         if (!value || !opaque_arg) {
5406                 PMD_DRV_LOG(ERR,
5407                             "Invalid parameter passed to rep_fc_r2f "
5408                             "devargs.\n");
5409                 return -EINVAL;
5410         }
5411
5412         rep_fc_r2f = strtoul(value, &end, 10);
5413         if (end == NULL || *end != '\0' ||
5414             (rep_fc_r2f == ULONG_MAX && errno == ERANGE)) {
5415                 PMD_DRV_LOG(ERR,
5416                             "Invalid parameter passed to rep_fc_r2f "
5417                             "devargs.\n");
5418                 return -EINVAL;
5419         }
5420
5421         if (BNXT_DEVARG_REP_FC_R2F_INVALID(rep_fc_r2f)) {
5422                 PMD_DRV_LOG(ERR,
5423                             "Invalid value passed to rep_fc_r2f devargs.\n");
5424                 return -EINVAL;
5425         }
5426
5427         vfr_bp->flags |= BNXT_REP_FC_R2F_VALID;
5428         vfr_bp->rep_fc_r2f = rep_fc_r2f;
5429         PMD_DRV_LOG(INFO, "rep-fc-r2f = %lu\n", rep_fc_r2f);
5430
5431         return 0;
5432 }
5433
5434 static int
5435 bnxt_parse_devarg_rep_fc_f2r(__rte_unused const char *key,
5436                              const char *value, void *opaque_arg)
5437 {
5438         struct bnxt_representor *vfr_bp = opaque_arg;
5439         unsigned long rep_fc_f2r;
5440         char *end = NULL;
5441
5442         if (!value || !opaque_arg) {
5443                 PMD_DRV_LOG(ERR,
5444                             "Invalid parameter passed to rep_fc_f2r "
5445                             "devargs.\n");
5446                 return -EINVAL;
5447         }
5448
5449         rep_fc_f2r = strtoul(value, &end, 10);
5450         if (end == NULL || *end != '\0' ||
5451             (rep_fc_f2r == ULONG_MAX && errno == ERANGE)) {
5452                 PMD_DRV_LOG(ERR,
5453                             "Invalid parameter passed to rep_fc_f2r "
5454                             "devargs.\n");
5455                 return -EINVAL;
5456         }
5457
5458         if (BNXT_DEVARG_REP_FC_F2R_INVALID(rep_fc_f2r)) {
5459                 PMD_DRV_LOG(ERR,
5460                             "Invalid value passed to rep_fc_f2r devargs.\n");
5461                 return -EINVAL;
5462         }
5463
5464         vfr_bp->flags |= BNXT_REP_FC_F2R_VALID;
5465         vfr_bp->rep_fc_f2r = rep_fc_f2r;
5466         PMD_DRV_LOG(INFO, "rep-fc-f2r = %lu\n", rep_fc_f2r);
5467
5468         return 0;
5469 }
5470
5471 static int
5472 bnxt_parse_dev_args(struct bnxt *bp, struct rte_devargs *devargs)
5473 {
5474         struct rte_kvargs *kvlist;
5475         int ret;
5476
5477         if (devargs == NULL)
5478                 return 0;
5479
5480         kvlist = rte_kvargs_parse(devargs->args, bnxt_dev_args);
5481         if (kvlist == NULL)
5482                 return -EINVAL;
5483
5484         /*
5485          * Handler for "truflow" devarg.
5486          * Invoked as for ex: "-a 0000:00:0d.0,host-based-truflow=1"
5487          */
5488         ret = rte_kvargs_process(kvlist, BNXT_DEVARG_TRUFLOW,
5489                                  bnxt_parse_devarg_truflow, bp);
5490         if (ret)
5491                 goto err;
5492
5493         /*
5494          * Handler for "flow_xstat" devarg.
5495          * Invoked as for ex: "-a 0000:00:0d.0,flow_xstat=1"
5496          */
5497         ret = rte_kvargs_process(kvlist, BNXT_DEVARG_FLOW_XSTAT,
5498                                  bnxt_parse_devarg_flow_xstat, bp);
5499         if (ret)
5500                 goto err;
5501
5502         /*
5503          * Handler for "max_num_kflows" devarg.
5504          * Invoked as for ex: "-a 000:00:0d.0,max_num_kflows=32"
5505          */
5506         ret = rte_kvargs_process(kvlist, BNXT_DEVARG_MAX_NUM_KFLOWS,
5507                                  bnxt_parse_devarg_max_num_kflows, bp);
5508         if (ret)
5509                 goto err;
5510
5511 err:
5512         rte_kvargs_free(kvlist);
5513         return ret;
5514 }
5515
5516 static int bnxt_alloc_switch_domain(struct bnxt *bp)
5517 {
5518         int rc = 0;
5519
5520         if (BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp)) {
5521                 rc = rte_eth_switch_domain_alloc(&bp->switch_domain_id);
5522                 if (rc)
5523                         PMD_DRV_LOG(ERR,
5524                                     "Failed to alloc switch domain: %d\n", rc);
5525                 else
5526                         PMD_DRV_LOG(INFO,
5527                                     "Switch domain allocated %d\n",
5528                                     bp->switch_domain_id);
5529         }
5530
5531         return rc;
5532 }
5533
5534 /* Allocate and initialize various fields in bnxt struct that
5535  * need to be allocated/destroyed only once in the lifetime of the driver
5536  */
5537 static int bnxt_drv_init(struct rte_eth_dev *eth_dev)
5538 {
5539         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
5540         struct bnxt *bp = eth_dev->data->dev_private;
5541         int rc = 0;
5542
5543         bp->flags &= ~BNXT_FLAG_RX_VECTOR_PKT_MODE;
5544
5545         if (bnxt_vf_pciid(pci_dev->id.device_id))
5546                 bp->flags |= BNXT_FLAG_VF;
5547
5548         if (bnxt_p5_device(pci_dev->id.device_id))
5549                 bp->flags |= BNXT_FLAG_CHIP_P5;
5550
5551         if (pci_dev->id.device_id == BROADCOM_DEV_ID_58802 ||
5552             pci_dev->id.device_id == BROADCOM_DEV_ID_58804 ||
5553             pci_dev->id.device_id == BROADCOM_DEV_ID_58808 ||
5554             pci_dev->id.device_id == BROADCOM_DEV_ID_58802_VF)
5555                 bp->flags |= BNXT_FLAG_STINGRAY;
5556
5557         if (BNXT_TRUFLOW_EN(bp)) {
5558                 /* extra mbuf field is required to store CFA code from mark */
5559                 static const struct rte_mbuf_dynfield bnxt_cfa_code_dynfield_desc = {
5560                         .name = RTE_PMD_BNXT_CFA_CODE_DYNFIELD_NAME,
5561                         .size = sizeof(bnxt_cfa_code_dynfield_t),
5562                         .align = __alignof__(bnxt_cfa_code_dynfield_t),
5563                 };
5564                 bnxt_cfa_code_dynfield_offset =
5565                         rte_mbuf_dynfield_register(&bnxt_cfa_code_dynfield_desc);
5566                 if (bnxt_cfa_code_dynfield_offset < 0) {
5567                         PMD_DRV_LOG(ERR,
5568                             "Failed to register mbuf field for TruFlow mark\n");
5569                         return -rte_errno;
5570                 }
5571         }
5572
5573         rc = bnxt_map_pci_bars(eth_dev);
5574         if (rc) {
5575                 PMD_DRV_LOG(ERR,
5576                             "Failed to initialize board rc: %x\n", rc);
5577                 return rc;
5578         }
5579
5580         rc = bnxt_alloc_pf_info(bp);
5581         if (rc)
5582                 return rc;
5583
5584         rc = bnxt_alloc_link_info(bp);
5585         if (rc)
5586                 return rc;
5587
5588         rc = bnxt_alloc_parent_info(bp);
5589         if (rc)
5590                 return rc;
5591
5592         rc = bnxt_alloc_hwrm_resources(bp);
5593         if (rc) {
5594                 PMD_DRV_LOG(ERR,
5595                             "Failed to allocate response buffer rc: %x\n", rc);
5596                 return rc;
5597         }
5598         rc = bnxt_alloc_leds_info(bp);
5599         if (rc)
5600                 return rc;
5601
5602         rc = bnxt_alloc_cos_queues(bp);
5603         if (rc)
5604                 return rc;
5605
5606         rc = bnxt_init_locks(bp);
5607         if (rc)
5608                 return rc;
5609
5610         rc = bnxt_alloc_switch_domain(bp);
5611         if (rc)
5612                 return rc;
5613
5614         return rc;
5615 }
5616
5617 static int
5618 bnxt_dev_init(struct rte_eth_dev *eth_dev, void *params __rte_unused)
5619 {
5620         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
5621         static int version_printed;
5622         struct bnxt *bp;
5623         int rc;
5624
5625         if (version_printed++ == 0)
5626                 PMD_DRV_LOG(INFO, "%s\n", bnxt_version);
5627
5628         eth_dev->dev_ops = &bnxt_dev_ops;
5629         eth_dev->rx_queue_count = bnxt_rx_queue_count_op;
5630         eth_dev->rx_descriptor_status = bnxt_rx_descriptor_status_op;
5631         eth_dev->tx_descriptor_status = bnxt_tx_descriptor_status_op;
5632         eth_dev->rx_pkt_burst = &bnxt_recv_pkts;
5633         eth_dev->tx_pkt_burst = &bnxt_xmit_pkts;
5634
5635         /*
5636          * For secondary processes, we don't initialise any further
5637          * as primary has already done this work.
5638          */
5639         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
5640                 return 0;
5641
5642         rte_eth_copy_pci_info(eth_dev, pci_dev);
5643         eth_dev->data->dev_flags |= RTE_ETH_DEV_AUTOFILL_QUEUE_XSTATS;
5644
5645         bp = eth_dev->data->dev_private;
5646
5647         /* Parse dev arguments passed on when starting the DPDK application. */
5648         rc = bnxt_parse_dev_args(bp, pci_dev->device.devargs);
5649         if (rc)
5650                 goto error_free;
5651
5652         rc = bnxt_drv_init(eth_dev);
5653         if (rc)
5654                 goto error_free;
5655
5656         rc = bnxt_init_resources(bp, false);
5657         if (rc)
5658                 goto error_free;
5659
5660         rc = bnxt_alloc_stats_mem(bp);
5661         if (rc)
5662                 goto error_free;
5663
5664         PMD_DRV_LOG(INFO,
5665                     DRV_MODULE_NAME "found at mem %" PRIX64 ", node addr %pM\n",
5666                     pci_dev->mem_resource[0].phys_addr,
5667                     pci_dev->mem_resource[0].addr);
5668
5669         return 0;
5670
5671 error_free:
5672         bnxt_dev_uninit(eth_dev);
5673         return rc;
5674 }
5675
5676
5677 static void bnxt_free_ctx_mem_buf(struct bnxt_ctx_mem_buf_info *ctx)
5678 {
5679         if (!ctx)
5680                 return;
5681
5682         if (ctx->va)
5683                 rte_free(ctx->va);
5684
5685         ctx->va = NULL;
5686         ctx->dma = RTE_BAD_IOVA;
5687         ctx->ctx_id = BNXT_CTX_VAL_INVAL;
5688 }
5689
5690 static void bnxt_unregister_fc_ctx_mem(struct bnxt *bp)
5691 {
5692         bnxt_hwrm_cfa_counter_cfg(bp, BNXT_DIR_RX,
5693                                   CFA_COUNTER_CFG_IN_COUNTER_TYPE_FC,
5694                                   bp->flow_stat->rx_fc_out_tbl.ctx_id,
5695                                   bp->flow_stat->max_fc,
5696                                   false);
5697
5698         bnxt_hwrm_cfa_counter_cfg(bp, BNXT_DIR_TX,
5699                                   CFA_COUNTER_CFG_IN_COUNTER_TYPE_FC,
5700                                   bp->flow_stat->tx_fc_out_tbl.ctx_id,
5701                                   bp->flow_stat->max_fc,
5702                                   false);
5703
5704         if (bp->flow_stat->rx_fc_in_tbl.ctx_id != BNXT_CTX_VAL_INVAL)
5705                 bnxt_hwrm_ctx_unrgtr(bp, bp->flow_stat->rx_fc_in_tbl.ctx_id);
5706         bp->flow_stat->rx_fc_in_tbl.ctx_id = BNXT_CTX_VAL_INVAL;
5707
5708         if (bp->flow_stat->rx_fc_out_tbl.ctx_id != BNXT_CTX_VAL_INVAL)
5709                 bnxt_hwrm_ctx_unrgtr(bp, bp->flow_stat->rx_fc_out_tbl.ctx_id);
5710         bp->flow_stat->rx_fc_out_tbl.ctx_id = BNXT_CTX_VAL_INVAL;
5711
5712         if (bp->flow_stat->tx_fc_in_tbl.ctx_id != BNXT_CTX_VAL_INVAL)
5713                 bnxt_hwrm_ctx_unrgtr(bp, bp->flow_stat->tx_fc_in_tbl.ctx_id);
5714         bp->flow_stat->tx_fc_in_tbl.ctx_id = BNXT_CTX_VAL_INVAL;
5715
5716         if (bp->flow_stat->tx_fc_out_tbl.ctx_id != BNXT_CTX_VAL_INVAL)
5717                 bnxt_hwrm_ctx_unrgtr(bp, bp->flow_stat->tx_fc_out_tbl.ctx_id);
5718         bp->flow_stat->tx_fc_out_tbl.ctx_id = BNXT_CTX_VAL_INVAL;
5719 }
5720
5721 static void bnxt_uninit_fc_ctx_mem(struct bnxt *bp)
5722 {
5723         bnxt_unregister_fc_ctx_mem(bp);
5724
5725         bnxt_free_ctx_mem_buf(&bp->flow_stat->rx_fc_in_tbl);
5726         bnxt_free_ctx_mem_buf(&bp->flow_stat->rx_fc_out_tbl);
5727         bnxt_free_ctx_mem_buf(&bp->flow_stat->tx_fc_in_tbl);
5728         bnxt_free_ctx_mem_buf(&bp->flow_stat->tx_fc_out_tbl);
5729 }
5730
5731 static void bnxt_uninit_ctx_mem(struct bnxt *bp)
5732 {
5733         if (BNXT_FLOW_XSTATS_EN(bp))
5734                 bnxt_uninit_fc_ctx_mem(bp);
5735 }
5736
5737 static void
5738 bnxt_free_error_recovery_info(struct bnxt *bp)
5739 {
5740         rte_free(bp->recovery_info);
5741         bp->recovery_info = NULL;
5742         bp->fw_cap &= ~BNXT_FW_CAP_ERROR_RECOVERY;
5743 }
5744
5745 static int
5746 bnxt_uninit_resources(struct bnxt *bp, bool reconfig_dev)
5747 {
5748         int rc;
5749
5750         bnxt_free_int(bp);
5751         bnxt_free_mem(bp, reconfig_dev);
5752
5753         bnxt_hwrm_func_buf_unrgtr(bp);
5754         rte_free(bp->pf->vf_req_buf);
5755
5756         rc = bnxt_hwrm_func_driver_unregister(bp, 0);
5757         bp->flags &= ~BNXT_FLAG_REGISTERED;
5758         bnxt_free_ctx_mem(bp);
5759         if (!reconfig_dev) {
5760                 bnxt_free_hwrm_resources(bp);
5761                 bnxt_free_error_recovery_info(bp);
5762         }
5763
5764         bnxt_uninit_ctx_mem(bp);
5765
5766         bnxt_free_flow_stats_info(bp);
5767         bnxt_free_rep_info(bp);
5768         rte_free(bp->ptp_cfg);
5769         bp->ptp_cfg = NULL;
5770         return rc;
5771 }
5772
5773 static int
5774 bnxt_dev_uninit(struct rte_eth_dev *eth_dev)
5775 {
5776         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
5777                 return -EPERM;
5778
5779         PMD_DRV_LOG(DEBUG, "Calling Device uninit\n");
5780
5781         if (eth_dev->state != RTE_ETH_DEV_UNUSED)
5782                 bnxt_dev_close_op(eth_dev);
5783
5784         return 0;
5785 }
5786
5787 static int bnxt_pci_remove_dev_with_reps(struct rte_eth_dev *eth_dev)
5788 {
5789         struct bnxt *bp = eth_dev->data->dev_private;
5790         struct rte_eth_dev *vf_rep_eth_dev;
5791         int ret = 0, i;
5792
5793         if (!bp)
5794                 return -EINVAL;
5795
5796         for (i = 0; i < bp->num_reps; i++) {
5797                 vf_rep_eth_dev = bp->rep_info[i].vfr_eth_dev;
5798                 if (!vf_rep_eth_dev)
5799                         continue;
5800                 PMD_DRV_LOG(DEBUG, "BNXT Port:%d VFR pci remove\n",
5801                             vf_rep_eth_dev->data->port_id);
5802                 rte_eth_dev_destroy(vf_rep_eth_dev, bnxt_representor_uninit);
5803         }
5804         PMD_DRV_LOG(DEBUG, "BNXT Port:%d pci remove\n",
5805                     eth_dev->data->port_id);
5806         ret = rte_eth_dev_destroy(eth_dev, bnxt_dev_uninit);
5807
5808         return ret;
5809 }
5810
5811 static void bnxt_free_rep_info(struct bnxt *bp)
5812 {
5813         rte_free(bp->rep_info);
5814         bp->rep_info = NULL;
5815         rte_free(bp->cfa_code_map);
5816         bp->cfa_code_map = NULL;
5817 }
5818
5819 static int bnxt_init_rep_info(struct bnxt *bp)
5820 {
5821         int i = 0, rc;
5822
5823         if (bp->rep_info)
5824                 return 0;
5825
5826         bp->rep_info = rte_zmalloc("bnxt_rep_info",
5827                                    sizeof(bp->rep_info[0]) * BNXT_MAX_VF_REPS,
5828                                    0);
5829         if (!bp->rep_info) {
5830                 PMD_DRV_LOG(ERR, "Failed to alloc memory for rep info\n");
5831                 return -ENOMEM;
5832         }
5833         bp->cfa_code_map = rte_zmalloc("bnxt_cfa_code_map",
5834                                        sizeof(*bp->cfa_code_map) *
5835                                        BNXT_MAX_CFA_CODE, 0);
5836         if (!bp->cfa_code_map) {
5837                 PMD_DRV_LOG(ERR, "Failed to alloc memory for cfa_code_map\n");
5838                 bnxt_free_rep_info(bp);
5839                 return -ENOMEM;
5840         }
5841
5842         for (i = 0; i < BNXT_MAX_CFA_CODE; i++)
5843                 bp->cfa_code_map[i] = BNXT_VF_IDX_INVALID;
5844
5845         rc = pthread_mutex_init(&bp->rep_info->vfr_lock, NULL);
5846         if (rc) {
5847                 PMD_DRV_LOG(ERR, "Unable to initialize vfr_lock\n");
5848                 bnxt_free_rep_info(bp);
5849                 return rc;
5850         }
5851
5852         rc = pthread_mutex_init(&bp->rep_info->vfr_start_lock, NULL);
5853         if (rc) {
5854                 PMD_DRV_LOG(ERR, "Unable to initialize vfr_start_lock\n");
5855                 bnxt_free_rep_info(bp);
5856                 return rc;
5857         }
5858
5859         return rc;
5860 }
5861
5862 static int bnxt_rep_port_probe(struct rte_pci_device *pci_dev,
5863                                struct rte_eth_devargs *eth_da,
5864                                struct rte_eth_dev *backing_eth_dev,
5865                                const char *dev_args)
5866 {
5867         struct rte_eth_dev *vf_rep_eth_dev;
5868         char name[RTE_ETH_NAME_MAX_LEN];
5869         struct bnxt *backing_bp;
5870         uint16_t num_rep;
5871         int i, ret = 0;
5872         struct rte_kvargs *kvlist = NULL;
5873
5874         if (eth_da->type == RTE_ETH_REPRESENTOR_NONE)
5875                 return 0;
5876         if (eth_da->type != RTE_ETH_REPRESENTOR_VF) {
5877                 PMD_DRV_LOG(ERR, "unsupported representor type %d\n",
5878                             eth_da->type);
5879                 return -ENOTSUP;
5880         }
5881         num_rep = eth_da->nb_representor_ports;
5882         if (num_rep > BNXT_MAX_VF_REPS) {
5883                 PMD_DRV_LOG(ERR, "nb_representor_ports = %d > %d MAX VF REPS\n",
5884                             num_rep, BNXT_MAX_VF_REPS);
5885                 return -EINVAL;
5886         }
5887
5888         if (num_rep >= RTE_MAX_ETHPORTS) {
5889                 PMD_DRV_LOG(ERR,
5890                             "nb_representor_ports = %d > %d MAX ETHPORTS\n",
5891                             num_rep, RTE_MAX_ETHPORTS);
5892                 return -EINVAL;
5893         }
5894
5895         backing_bp = backing_eth_dev->data->dev_private;
5896
5897         if (!(BNXT_PF(backing_bp) || BNXT_VF_IS_TRUSTED(backing_bp))) {
5898                 PMD_DRV_LOG(ERR,
5899                             "Not a PF or trusted VF. No Representor support\n");
5900                 /* Returning an error is not an option.
5901                  * Applications are not handling this correctly
5902                  */
5903                 return 0;
5904         }
5905
5906         if (bnxt_init_rep_info(backing_bp))
5907                 return 0;
5908
5909         for (i = 0; i < num_rep; i++) {
5910                 struct bnxt_representor representor = {
5911                         .vf_id = eth_da->representor_ports[i],
5912                         .switch_domain_id = backing_bp->switch_domain_id,
5913                         .parent_dev = backing_eth_dev
5914                 };
5915
5916                 if (representor.vf_id >= BNXT_MAX_VF_REPS) {
5917                         PMD_DRV_LOG(ERR, "VF-Rep id %d >= %d MAX VF ID\n",
5918                                     representor.vf_id, BNXT_MAX_VF_REPS);
5919                         continue;
5920                 }
5921
5922                 /* representor port net_bdf_port */
5923                 snprintf(name, sizeof(name), "net_%s_representor_%d",
5924                          pci_dev->device.name, eth_da->representor_ports[i]);
5925
5926                 kvlist = rte_kvargs_parse(dev_args, bnxt_dev_args);
5927                 if (kvlist) {
5928                         /*
5929                          * Handler for "rep_is_pf" devarg.
5930                          * Invoked as for ex: "-a 000:00:0d.0,
5931                          * rep-based-pf=<pf index> rep-is-pf=<VF=0 or PF=1>"
5932                          */
5933                         ret = rte_kvargs_process(kvlist, BNXT_DEVARG_REP_IS_PF,
5934                                                  bnxt_parse_devarg_rep_is_pf,
5935                                                  (void *)&representor);
5936                         if (ret) {
5937                                 ret = -EINVAL;
5938                                 goto err;
5939                         }
5940                         /*
5941                          * Handler for "rep_based_pf" devarg.
5942                          * Invoked as for ex: "-a 000:00:0d.0,
5943                          * rep-based-pf=<pf index> rep-is-pf=<VF=0 or PF=1>"
5944                          */
5945                         ret = rte_kvargs_process(kvlist,
5946                                                  BNXT_DEVARG_REP_BASED_PF,
5947                                                  bnxt_parse_devarg_rep_based_pf,
5948                                                  (void *)&representor);
5949                         if (ret) {
5950                                 ret = -EINVAL;
5951                                 goto err;
5952                         }
5953                         /*
5954                          * Handler for "rep_based_pf" devarg.
5955                          * Invoked as for ex: "-a 000:00:0d.0,
5956                          * rep-based-pf=<pf index> rep-is-pf=<VF=0 or PF=1>"
5957                          */
5958                         ret = rte_kvargs_process(kvlist, BNXT_DEVARG_REP_Q_R2F,
5959                                                  bnxt_parse_devarg_rep_q_r2f,
5960                                                  (void *)&representor);
5961                         if (ret) {
5962                                 ret = -EINVAL;
5963                                 goto err;
5964                         }
5965                         /*
5966                          * Handler for "rep_based_pf" devarg.
5967                          * Invoked as for ex: "-a 000:00:0d.0,
5968                          * rep-based-pf=<pf index> rep-is-pf=<VF=0 or PF=1>"
5969                          */
5970                         ret = rte_kvargs_process(kvlist, BNXT_DEVARG_REP_Q_F2R,
5971                                                  bnxt_parse_devarg_rep_q_f2r,
5972                                                  (void *)&representor);
5973                         if (ret) {
5974                                 ret = -EINVAL;
5975                                 goto err;
5976                         }
5977                         /*
5978                          * Handler for "rep_based_pf" devarg.
5979                          * Invoked as for ex: "-a 000:00:0d.0,
5980                          * rep-based-pf=<pf index> rep-is-pf=<VF=0 or PF=1>"
5981                          */
5982                         ret = rte_kvargs_process(kvlist, BNXT_DEVARG_REP_FC_R2F,
5983                                                  bnxt_parse_devarg_rep_fc_r2f,
5984                                                  (void *)&representor);
5985                         if (ret) {
5986                                 ret = -EINVAL;
5987                                 goto err;
5988                         }
5989                         /*
5990                          * Handler for "rep_based_pf" devarg.
5991                          * Invoked as for ex: "-a 000:00:0d.0,
5992                          * rep-based-pf=<pf index> rep-is-pf=<VF=0 or PF=1>"
5993                          */
5994                         ret = rte_kvargs_process(kvlist, BNXT_DEVARG_REP_FC_F2R,
5995                                                  bnxt_parse_devarg_rep_fc_f2r,
5996                                                  (void *)&representor);
5997                         if (ret) {
5998                                 ret = -EINVAL;
5999                                 goto err;
6000                         }
6001                 }
6002
6003                 ret = rte_eth_dev_create(&pci_dev->device, name,
6004                                          sizeof(struct bnxt_representor),
6005                                          NULL, NULL,
6006                                          bnxt_representor_init,
6007                                          &representor);
6008                 if (ret) {
6009                         PMD_DRV_LOG(ERR, "failed to create bnxt vf "
6010                                     "representor %s.", name);
6011                         goto err;
6012                 }
6013
6014                 vf_rep_eth_dev = rte_eth_dev_allocated(name);
6015                 if (!vf_rep_eth_dev) {
6016                         PMD_DRV_LOG(ERR, "Failed to find the eth_dev"
6017                                     " for VF-Rep: %s.", name);
6018                         ret = -ENODEV;
6019                         goto err;
6020                 }
6021
6022                 PMD_DRV_LOG(DEBUG, "BNXT Port:%d VFR pci probe\n",
6023                             backing_eth_dev->data->port_id);
6024                 backing_bp->rep_info[representor.vf_id].vfr_eth_dev =
6025                                                          vf_rep_eth_dev;
6026                 backing_bp->num_reps++;
6027
6028         }
6029
6030         rte_kvargs_free(kvlist);
6031         return 0;
6032
6033 err:
6034         /* If num_rep > 1, then rollback already created
6035          * ports, since we'll be failing the probe anyway
6036          */
6037         if (num_rep > 1)
6038                 bnxt_pci_remove_dev_with_reps(backing_eth_dev);
6039         rte_errno = -ret;
6040         rte_kvargs_free(kvlist);
6041
6042         return ret;
6043 }
6044
6045 static int bnxt_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
6046                           struct rte_pci_device *pci_dev)
6047 {
6048         struct rte_eth_devargs eth_da = { .nb_representor_ports = 0 };
6049         struct rte_eth_dev *backing_eth_dev;
6050         uint16_t num_rep;
6051         int ret = 0;
6052
6053         if (pci_dev->device.devargs) {
6054                 ret = rte_eth_devargs_parse(pci_dev->device.devargs->args,
6055                                             &eth_da);
6056                 if (ret)
6057                         return ret;
6058         }
6059
6060         num_rep = eth_da.nb_representor_ports;
6061         PMD_DRV_LOG(DEBUG, "nb_representor_ports = %d\n",
6062                     num_rep);
6063
6064         /* We could come here after first level of probe is already invoked
6065          * as part of an application bringup(OVS-DPDK vswitchd), so first check
6066          * for already allocated eth_dev for the backing device (PF/Trusted VF)
6067          */
6068         backing_eth_dev = rte_eth_dev_allocated(pci_dev->device.name);
6069         if (backing_eth_dev == NULL) {
6070                 ret = rte_eth_dev_create(&pci_dev->device, pci_dev->device.name,
6071                                          sizeof(struct bnxt),
6072                                          eth_dev_pci_specific_init, pci_dev,
6073                                          bnxt_dev_init, NULL);
6074
6075                 if (ret || !num_rep)
6076                         return ret;
6077
6078                 backing_eth_dev = rte_eth_dev_allocated(pci_dev->device.name);
6079         }
6080         PMD_DRV_LOG(DEBUG, "BNXT Port:%d pci probe\n",
6081                     backing_eth_dev->data->port_id);
6082
6083         if (!num_rep)
6084                 return ret;
6085
6086         /* probe representor ports now */
6087         ret = bnxt_rep_port_probe(pci_dev, &eth_da, backing_eth_dev,
6088                                   pci_dev->device.devargs->args);
6089
6090         return ret;
6091 }
6092
6093 static int bnxt_pci_remove(struct rte_pci_device *pci_dev)
6094 {
6095         struct rte_eth_dev *eth_dev;
6096
6097         eth_dev = rte_eth_dev_allocated(pci_dev->device.name);
6098         if (!eth_dev)
6099                 return 0; /* Invoked typically only by OVS-DPDK, by the
6100                            * time it comes here the eth_dev is already
6101                            * deleted by rte_eth_dev_close(), so returning
6102                            * +ve value will at least help in proper cleanup
6103                            */
6104
6105         PMD_DRV_LOG(DEBUG, "BNXT Port:%d pci remove\n", eth_dev->data->port_id);
6106         if (rte_eal_process_type() == RTE_PROC_PRIMARY) {
6107                 if (eth_dev->data->dev_flags & RTE_ETH_DEV_REPRESENTOR)
6108                         return rte_eth_dev_destroy(eth_dev,
6109                                                    bnxt_representor_uninit);
6110                 else
6111                         return rte_eth_dev_destroy(eth_dev,
6112                                                    bnxt_dev_uninit);
6113         } else {
6114                 return rte_eth_dev_pci_generic_remove(pci_dev, NULL);
6115         }
6116 }
6117
6118 static struct rte_pci_driver bnxt_rte_pmd = {
6119         .id_table = bnxt_pci_id_map,
6120         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC |
6121                         RTE_PCI_DRV_PROBE_AGAIN, /* Needed in case of VF-REPs
6122                                                   * and OVS-DPDK
6123                                                   */
6124         .probe = bnxt_pci_probe,
6125         .remove = bnxt_pci_remove,
6126 };
6127
6128 static bool
6129 is_device_supported(struct rte_eth_dev *dev, struct rte_pci_driver *drv)
6130 {
6131         if (strcmp(dev->device->driver->name, drv->driver.name))
6132                 return false;
6133
6134         return true;
6135 }
6136
6137 bool is_bnxt_supported(struct rte_eth_dev *dev)
6138 {
6139         return is_device_supported(dev, &bnxt_rte_pmd);
6140 }
6141
6142 RTE_LOG_REGISTER(bnxt_logtype_driver, pmd.net.bnxt.driver, NOTICE);
6143 RTE_PMD_REGISTER_PCI(net_bnxt, bnxt_rte_pmd);
6144 RTE_PMD_REGISTER_PCI_TABLE(net_bnxt, bnxt_pci_id_map);
6145 RTE_PMD_REGISTER_KMOD_DEP(net_bnxt, "* igb_uio | uio_pci_generic | vfio-pci");