drivers/net/bnxt/bnxt_ethdev.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2014-2018 Broadcom
   3  * All rights reserved.
   4  */
   5
   6 #include <inttypes.h>
   7 #include <stdbool.h>
   8
   9 #include <rte_dev.h>
  10 #include <rte_ethdev_driver.h>
  11 #include <rte_ethdev_pci.h>
  12 #include <rte_malloc.h>
  13 #include <rte_cycles.h>
  14 #include <rte_alarm.h>
  15 #include <rte_kvargs.h>
  16 #include <rte_vect.h>
  17
  18 #include "bnxt.h"
  19 #include "bnxt_filter.h"
  20 #include "bnxt_hwrm.h"
  21 #include "bnxt_irq.h"
  22 #include "bnxt_reps.h"
  23 #include "bnxt_ring.h"
  24 #include "bnxt_rxq.h"
  25 #include "bnxt_rxr.h"
  26 #include "bnxt_stats.h"
  27 #include "bnxt_txq.h"
  28 #include "bnxt_txr.h"
  29 #include "bnxt_vnic.h"
  30 #include "hsi_struct_def_dpdk.h"
  31 #include "bnxt_nvm_defs.h"
  32 #include "bnxt_tf_common.h"
  33 #include "ulp_flow_db.h"
  34
  35 #define DRV_MODULE_NAME         "bnxt"
  36 static const char bnxt_version[] =
  37         "Broadcom NetXtreme driver " DRV_MODULE_NAME;
  38
  39 /*
  40  * The set of PCI devices this driver supports
  41  */
  42 static const struct rte_pci_id bnxt_pci_id_map[] = {
  43         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM,
  44                          BROADCOM_DEV_ID_STRATUS_NIC_VF1) },
  45         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM,
  46                          BROADCOM_DEV_ID_STRATUS_NIC_VF2) },
  47         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_STRATUS_NIC) },
  48         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414_VF) },
  49         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57301) },
  50         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57302) },
  51         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57304_PF) },
  52         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57304_VF) },
  53         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_NS2) },
  54         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57402) },
  55         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57404) },
  56         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57406_PF) },
  57         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57406_VF) },
  58         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57402_MF) },
  59         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57407_RJ45) },
  60         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57404_MF) },
  61         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57406_MF) },
  62         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57407_SFP) },
  63         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57407_MF) },
  64         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_5741X_VF) },
  65         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_5731X_VF) },
  66         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57314) },
  67         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_MF) },
  68         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57311) },
  69         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57312) },
  70         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57412) },
  71         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414) },
  72         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_RJ45) },
  73         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_RJ45) },
  74         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57412_MF) },
  75         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57317_RJ45) },
  76         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_SFP) },
  77         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_SFP) },
  78         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57317_SFP) },
  79         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414_MF) },
  80         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_MF) },
  81         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58802) },
  82         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58804) },
  83         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58808) },
  84         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58802_VF) },
  85         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57508) },
  86         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57504) },
  87         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57502) },
  88         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57500_VF1) },
  89         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57500_VF2) },
  90         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57508_MF1) },
  91         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57504_MF1) },
  92         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57502_MF1) },
  93         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57508_MF2) },
  94         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57504_MF2) },
  95         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57502_MF2) },
  96         { .vendor_id = 0, /* sentinel */ },
  97 };
  98
  99 #define BNXT_DEVARG_TRUFLOW     "host-based-truflow"
 100 #define BNXT_DEVARG_FLOW_XSTAT  "flow-xstat"
 101 #define BNXT_DEVARG_MAX_NUM_KFLOWS  "max-num-kflows"
 102 #define BNXT_DEVARG_REPRESENTOR "representor"
 103 #define BNXT_DEVARG_REP_BASED_PF  "rep-based-pf"
 104 #define BNXT_DEVARG_REP_IS_PF  "rep-is-pf"
 105 #define BNXT_DEVARG_REP_Q_R2F  "rep-q-r2f"
 106 #define BNXT_DEVARG_REP_Q_F2R  "rep-q-f2r"
 107 #define BNXT_DEVARG_REP_FC_R2F  "rep-fc-r2f"
 108 #define BNXT_DEVARG_REP_FC_F2R  "rep-fc-f2r"
 109
 110 static const char *const bnxt_dev_args[] = {
 111         BNXT_DEVARG_REPRESENTOR,
 112         BNXT_DEVARG_TRUFLOW,
 113         BNXT_DEVARG_FLOW_XSTAT,
 114         BNXT_DEVARG_MAX_NUM_KFLOWS,
 115         BNXT_DEVARG_REP_BASED_PF,
 116         BNXT_DEVARG_REP_IS_PF,
 117         BNXT_DEVARG_REP_Q_R2F,
 118         BNXT_DEVARG_REP_Q_F2R,
 119         BNXT_DEVARG_REP_FC_R2F,
 120         BNXT_DEVARG_REP_FC_F2R,
 121         NULL
 122 };
 123
 124 /*
 125  * truflow == false to disable the feature
 126  * truflow == true to enable the feature
 127  */
 128 #define BNXT_DEVARG_TRUFLOW_INVALID(truflow)    ((truflow) > 1)
 129
 130 /*
 131  * flow_xstat == false to disable the feature
 132  * flow_xstat == true to enable the feature
 133  */
 134 #define BNXT_DEVARG_FLOW_XSTAT_INVALID(flow_xstat)      ((flow_xstat) > 1)
 135
 136 /*
 137  * rep_is_pf == false to indicate VF representor
 138  * rep_is_pf == true to indicate PF representor
 139  */
 140 #define BNXT_DEVARG_REP_IS_PF_INVALID(rep_is_pf)        ((rep_is_pf) > 1)
 141
 142 /*
 143  * rep_based_pf == Physical index of the PF
 144  */
 145 #define BNXT_DEVARG_REP_BASED_PF_INVALID(rep_based_pf)  ((rep_based_pf) > 15)
 146 /*
 147  * rep_q_r2f == Logical COS Queue index for the rep to endpoint direction
 148  */
 149 #define BNXT_DEVARG_REP_Q_R2F_INVALID(rep_q_r2f)        ((rep_q_r2f) > 3)
 150
 151 /*
 152  * rep_q_f2r == Logical COS Queue index for the endpoint to rep direction
 153  */
 154 #define BNXT_DEVARG_REP_Q_F2R_INVALID(rep_q_f2r)        ((rep_q_f2r) > 3)
 155
 156 /*
 157  * rep_fc_r2f == Flow control for the representor to endpoint direction
 158  */
 159 #define BNXT_DEVARG_REP_FC_R2F_INVALID(rep_fc_r2f)      ((rep_fc_r2f) > 1)
 160
 161 /*
 162  * rep_fc_f2r == Flow control for the endpoint to representor direction
 163  */
 164 #define BNXT_DEVARG_REP_FC_F2R_INVALID(rep_fc_f2r)      ((rep_fc_f2r) > 1)
 165
 166 /*
 167  * max_num_kflows must be >= 32
 168  * and must be a power-of-2 supported value
 169  * return: 1 -> invalid
 170  *         0 -> valid
 171  */
 172 static int bnxt_devarg_max_num_kflow_invalid(uint16_t max_num_kflows)
 173 {
 174         if (max_num_kflows < 32 || !rte_is_power_of_2(max_num_kflows))
 175                 return 1;
 176         return 0;
 177 }
 178
 179 static int bnxt_vlan_offload_set_op(struct rte_eth_dev *dev, int mask);
 180 static int bnxt_dev_uninit(struct rte_eth_dev *eth_dev);
 181 static int bnxt_init_resources(struct bnxt *bp, bool reconfig_dev);
 182 static int bnxt_uninit_resources(struct bnxt *bp, bool reconfig_dev);
 183 static void bnxt_cancel_fw_health_check(struct bnxt *bp);
 184 static int bnxt_restore_vlan_filters(struct bnxt *bp);
 185 static void bnxt_dev_recover(void *arg);
 186 static void bnxt_free_error_recovery_info(struct bnxt *bp);
 187 static void bnxt_free_rep_info(struct bnxt *bp);
 188
 189 int is_bnxt_in_error(struct bnxt *bp)
 190 {
 191         if (bp->flags & BNXT_FLAG_FATAL_ERROR)
 192                 return -EIO;
 193         if (bp->flags & BNXT_FLAG_FW_RESET)
 194                 return -EBUSY;
 195
 196         return 0;
 197 }
 198
 199 /***********************/
 200
 201 /*
 202  * High level utility functions
 203  */
 204
 205 static uint16_t bnxt_rss_ctxts(const struct bnxt *bp)
 206 {
 207         if (!BNXT_CHIP_THOR(bp))
 208                 return 1;
 209
 210         return RTE_ALIGN_MUL_CEIL(bp->rx_nr_rings,
 211                                   BNXT_RSS_ENTRIES_PER_CTX_THOR) /
 212                                     BNXT_RSS_ENTRIES_PER_CTX_THOR;
 213 }
 214
 215 uint16_t bnxt_rss_hash_tbl_size(const struct bnxt *bp)
 216 {
 217         if (!BNXT_CHIP_THOR(bp))
 218                 return HW_HASH_INDEX_SIZE;
 219
 220         return bnxt_rss_ctxts(bp) * BNXT_RSS_ENTRIES_PER_CTX_THOR;
 221 }
 222
 223 static void bnxt_free_parent_info(struct bnxt *bp)
 224 {
 225         rte_free(bp->parent);
 226 }
 227
 228 static void bnxt_free_pf_info(struct bnxt *bp)
 229 {
 230         rte_free(bp->pf);
 231 }
 232
 233 static void bnxt_free_link_info(struct bnxt *bp)
 234 {
 235         rte_free(bp->link_info);
 236 }
 237
 238 static void bnxt_free_leds_info(struct bnxt *bp)
 239 {
 240         if (BNXT_VF(bp))
 241                 return;
 242
 243         rte_free(bp->leds);
 244         bp->leds = NULL;
 245 }
 246
 247 static void bnxt_free_flow_stats_info(struct bnxt *bp)
 248 {
 249         rte_free(bp->flow_stat);
 250         bp->flow_stat = NULL;
 251 }
 252
 253 static void bnxt_free_cos_queues(struct bnxt *bp)
 254 {
 255         rte_free(bp->rx_cos_queue);
 256         rte_free(bp->tx_cos_queue);
 257 }
 258
 259 static void bnxt_free_mem(struct bnxt *bp, bool reconfig)
 260 {
 261         bnxt_free_filter_mem(bp);
 262         bnxt_free_vnic_attributes(bp);
 263         bnxt_free_vnic_mem(bp);
 264
 265         /* tx/rx rings are configured as part of *_queue_setup callbacks.
 266          * If the number of rings change across fw update,
 267          * we don't have much choice except to warn the user.
 268          */
 269         if (!reconfig) {
 270                 bnxt_free_stats(bp);
 271                 bnxt_free_tx_rings(bp);
 272                 bnxt_free_rx_rings(bp);
 273         }
 274         bnxt_free_async_cp_ring(bp);
 275         bnxt_free_rxtx_nq_ring(bp);
 276
 277         rte_free(bp->grp_info);
 278         bp->grp_info = NULL;
 279 }
 280
 281 static int bnxt_alloc_parent_info(struct bnxt *bp)
 282 {
 283         bp->parent = rte_zmalloc("bnxt_parent_info",
 284                                  sizeof(struct bnxt_parent_info), 0);
 285         if (bp->parent == NULL)
 286                 return -ENOMEM;
 287
 288         return 0;
 289 }
 290
 291 static int bnxt_alloc_pf_info(struct bnxt *bp)
 292 {
 293         bp->pf = rte_zmalloc("bnxt_pf_info", sizeof(struct bnxt_pf_info), 0);
 294         if (bp->pf == NULL)
 295                 return -ENOMEM;
 296
 297         return 0;
 298 }
 299
 300 static int bnxt_alloc_link_info(struct bnxt *bp)
 301 {
 302         bp->link_info =
 303                 rte_zmalloc("bnxt_link_info", sizeof(struct bnxt_link_info), 0);
 304         if (bp->link_info == NULL)
 305                 return -ENOMEM;
 306
 307         return 0;
 308 }
 309
 310 static int bnxt_alloc_leds_info(struct bnxt *bp)
 311 {
 312         if (BNXT_VF(bp))
 313                 return 0;
 314
 315         bp->leds = rte_zmalloc("bnxt_leds",
 316                                BNXT_MAX_LED * sizeof(struct bnxt_led_info),
 317                                0);
 318         if (bp->leds == NULL)
 319                 return -ENOMEM;
 320
 321         return 0;
 322 }
 323
 324 static int bnxt_alloc_cos_queues(struct bnxt *bp)
 325 {
 326         bp->rx_cos_queue =
 327                 rte_zmalloc("bnxt_rx_cosq",
 328                             BNXT_COS_QUEUE_COUNT *
 329                             sizeof(struct bnxt_cos_queue_info),
 330                             0);
 331         if (bp->rx_cos_queue == NULL)
 332                 return -ENOMEM;
 333
 334         bp->tx_cos_queue =
 335                 rte_zmalloc("bnxt_tx_cosq",
 336                             BNXT_COS_QUEUE_COUNT *
 337                             sizeof(struct bnxt_cos_queue_info),
 338                             0);
 339         if (bp->tx_cos_queue == NULL)
 340                 return -ENOMEM;
 341
 342         return 0;
 343 }
 344
 345 static int bnxt_alloc_flow_stats_info(struct bnxt *bp)
 346 {
 347         bp->flow_stat = rte_zmalloc("bnxt_flow_xstat",
 348                                     sizeof(struct bnxt_flow_stat_info), 0);
 349         if (bp->flow_stat == NULL)
 350                 return -ENOMEM;
 351
 352         return 0;
 353 }
 354
 355 static int bnxt_alloc_mem(struct bnxt *bp, bool reconfig)
 356 {
 357         int rc;
 358
 359         rc = bnxt_alloc_ring_grps(bp);
 360         if (rc)
 361                 goto alloc_mem_err;
 362
 363         rc = bnxt_alloc_async_ring_struct(bp);
 364         if (rc)
 365                 goto alloc_mem_err;
 366
 367         rc = bnxt_alloc_vnic_mem(bp);
 368         if (rc)
 369                 goto alloc_mem_err;
 370
 371         rc = bnxt_alloc_vnic_attributes(bp);
 372         if (rc)
 373                 goto alloc_mem_err;
 374
 375         rc = bnxt_alloc_filter_mem(bp);
 376         if (rc)
 377                 goto alloc_mem_err;
 378
 379         rc = bnxt_alloc_async_cp_ring(bp);
 380         if (rc)
 381                 goto alloc_mem_err;
 382
 383         rc = bnxt_alloc_rxtx_nq_ring(bp);
 384         if (rc)
 385                 goto alloc_mem_err;
 386
 387         if (BNXT_FLOW_XSTATS_EN(bp)) {
 388                 rc = bnxt_alloc_flow_stats_info(bp);
 389                 if (rc)
 390                         goto alloc_mem_err;
 391         }
 392
 393         return 0;
 394
 395 alloc_mem_err:
 396         bnxt_free_mem(bp, reconfig);
 397         return rc;
 398 }
 399
 400 static int bnxt_setup_one_vnic(struct bnxt *bp, uint16_t vnic_id)
 401 {
 402         struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
 403         struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id];
 404         uint64_t rx_offloads = dev_conf->rxmode.offloads;
 405         struct bnxt_rx_queue *rxq;
 406         unsigned int j;
 407         int rc;
 408
 409         rc = bnxt_vnic_grp_alloc(bp, vnic);
 410         if (rc)
 411                 goto err_out;
 412
 413         PMD_DRV_LOG(DEBUG, "vnic[%d] = %p vnic->fw_grp_ids = %p\n",
 414                     vnic_id, vnic, vnic->fw_grp_ids);
 415
 416         rc = bnxt_hwrm_vnic_alloc(bp, vnic);
 417         if (rc)
 418                 goto err_out;
 419
 420         /* Alloc RSS context only if RSS mode is enabled */
 421         if (dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS) {
 422                 int j, nr_ctxs = bnxt_rss_ctxts(bp);
 423
 424                 rc = 0;
 425                 for (j = 0; j < nr_ctxs; j++) {
 426                         rc = bnxt_hwrm_vnic_ctx_alloc(bp, vnic, j);
 427                         if (rc)
 428                                 break;
 429                 }
 430                 if (rc) {
 431                         PMD_DRV_LOG(ERR,
 432                                     "HWRM vnic %d ctx %d alloc failure rc: %x\n",
 433                                     vnic_id, j, rc);
 434                         goto err_out;
 435                 }
 436                 vnic->num_lb_ctxts = nr_ctxs;
 437         }
 438
 439         /*
 440          * Firmware sets pf pair in default vnic cfg. If the VLAN strip
 441          * setting is not available at this time, it will not be
 442          * configured correctly in the CFA.
 443          */
 444         if (rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
 445                 vnic->vlan_strip = true;
 446         else
 447                 vnic->vlan_strip = false;
 448
 449         rc = bnxt_hwrm_vnic_cfg(bp, vnic);
 450         if (rc)
 451                 goto err_out;
 452
 453         rc = bnxt_set_hwrm_vnic_filters(bp, vnic);
 454         if (rc)
 455                 goto err_out;
 456
 457         for (j = 0; j < bp->rx_num_qs_per_vnic; j++) {
 458                 rxq = bp->eth_dev->data->rx_queues[j];
 459
 460                 PMD_DRV_LOG(DEBUG,
 461                             "rxq[%d]->vnic=%p vnic->fw_grp_ids=%p\n",
 462                             j, rxq->vnic, rxq->vnic->fw_grp_ids);
 463
 464                 if (BNXT_HAS_RING_GRPS(bp) && rxq->rx_deferred_start)
 465                         rxq->vnic->fw_grp_ids[j] = INVALID_HW_RING_ID;
 466                 else
 467                         vnic->rx_queue_cnt++;
 468         }
 469
 470         PMD_DRV_LOG(DEBUG, "vnic->rx_queue_cnt = %d\n", vnic->rx_queue_cnt);
 471
 472         rc = bnxt_vnic_rss_configure(bp, vnic);
 473         if (rc)
 474                 goto err_out;
 475
 476         bnxt_hwrm_vnic_plcmode_cfg(bp, vnic);
 477
 478         if (rx_offloads & DEV_RX_OFFLOAD_TCP_LRO)
 479                 bnxt_hwrm_vnic_tpa_cfg(bp, vnic, 1);
 480         else
 481                 bnxt_hwrm_vnic_tpa_cfg(bp, vnic, 0);
 482
 483         return 0;
 484 err_out:
 485         PMD_DRV_LOG(ERR, "HWRM vnic %d cfg failure rc: %x\n",
 486                     vnic_id, rc);
 487         return rc;
 488 }
 489
 490 static int bnxt_register_fc_ctx_mem(struct bnxt *bp)
 491 {
 492         int rc = 0;
 493
 494         rc = bnxt_hwrm_ctx_rgtr(bp, bp->flow_stat->rx_fc_in_tbl.dma,
 495                                 &bp->flow_stat->rx_fc_in_tbl.ctx_id);
 496         if (rc)
 497                 return rc;
 498
 499         PMD_DRV_LOG(DEBUG,
 500                     "rx_fc_in_tbl.va = %p rx_fc_in_tbl.dma = %p"
 501                     " rx_fc_in_tbl.ctx_id = %d\n",
 502                     bp->flow_stat->rx_fc_in_tbl.va,
 503                     (void *)((uintptr_t)bp->flow_stat->rx_fc_in_tbl.dma),
 504                     bp->flow_stat->rx_fc_in_tbl.ctx_id);
 505
 506         rc = bnxt_hwrm_ctx_rgtr(bp, bp->flow_stat->rx_fc_out_tbl.dma,
 507                                 &bp->flow_stat->rx_fc_out_tbl.ctx_id);
 508         if (rc)
 509                 return rc;
 510
 511         PMD_DRV_LOG(DEBUG,
 512                     "rx_fc_out_tbl.va = %p rx_fc_out_tbl.dma = %p"
 513                     " rx_fc_out_tbl.ctx_id = %d\n",
 514                     bp->flow_stat->rx_fc_out_tbl.va,
 515                     (void *)((uintptr_t)bp->flow_stat->rx_fc_out_tbl.dma),
 516                     bp->flow_stat->rx_fc_out_tbl.ctx_id);
 517
 518         rc = bnxt_hwrm_ctx_rgtr(bp, bp->flow_stat->tx_fc_in_tbl.dma,
 519                                 &bp->flow_stat->tx_fc_in_tbl.ctx_id);
 520         if (rc)
 521                 return rc;
 522
 523         PMD_DRV_LOG(DEBUG,
 524                     "tx_fc_in_tbl.va = %p tx_fc_in_tbl.dma = %p"
 525                     " tx_fc_in_tbl.ctx_id = %d\n",
 526                     bp->flow_stat->tx_fc_in_tbl.va,
 527                     (void *)((uintptr_t)bp->flow_stat->tx_fc_in_tbl.dma),
 528                     bp->flow_stat->tx_fc_in_tbl.ctx_id);
 529
 530         rc = bnxt_hwrm_ctx_rgtr(bp, bp->flow_stat->tx_fc_out_tbl.dma,
 531                                 &bp->flow_stat->tx_fc_out_tbl.ctx_id);
 532         if (rc)
 533                 return rc;
 534
 535         PMD_DRV_LOG(DEBUG,
 536                     "tx_fc_out_tbl.va = %p tx_fc_out_tbl.dma = %p"
 537                     " tx_fc_out_tbl.ctx_id = %d\n",
 538                     bp->flow_stat->tx_fc_out_tbl.va,
 539                     (void *)((uintptr_t)bp->flow_stat->tx_fc_out_tbl.dma),
 540                     bp->flow_stat->tx_fc_out_tbl.ctx_id);
 541
 542         memset(bp->flow_stat->rx_fc_out_tbl.va,
 543                0,
 544                bp->flow_stat->rx_fc_out_tbl.size);
 545         rc = bnxt_hwrm_cfa_counter_cfg(bp, BNXT_DIR_RX,
 546                                        CFA_COUNTER_CFG_IN_COUNTER_TYPE_FC,
 547                                        bp->flow_stat->rx_fc_out_tbl.ctx_id,
 548                                        bp->flow_stat->max_fc,
 549                                        true);
 550         if (rc)
 551                 return rc;
 552
 553         memset(bp->flow_stat->tx_fc_out_tbl.va,
 554                0,
 555                bp->flow_stat->tx_fc_out_tbl.size);
 556         rc = bnxt_hwrm_cfa_counter_cfg(bp, BNXT_DIR_TX,
 557                                        CFA_COUNTER_CFG_IN_COUNTER_TYPE_FC,
 558                                        bp->flow_stat->tx_fc_out_tbl.ctx_id,
 559                                        bp->flow_stat->max_fc,
 560                                        true);
 561
 562         return rc;
 563 }
 564
 565 static int bnxt_alloc_ctx_mem_buf(char *type, size_t size,
 566                                   struct bnxt_ctx_mem_buf_info *ctx)
 567 {
 568         if (!ctx)
 569                 return -EINVAL;
 570
 571         ctx->va = rte_zmalloc(type, size, 0);
 572         if (ctx->va == NULL)
 573                 return -ENOMEM;
 574         rte_mem_lock_page(ctx->va);
 575         ctx->size = size;
 576         ctx->dma = rte_mem_virt2iova(ctx->va);
 577         if (ctx->dma == RTE_BAD_IOVA)
 578                 return -ENOMEM;
 579
 580         return 0;
 581 }
 582
 583 static int bnxt_init_fc_ctx_mem(struct bnxt *bp)
 584 {
 585         struct rte_pci_device *pdev = bp->pdev;
 586         char type[RTE_MEMZONE_NAMESIZE];
 587         uint16_t max_fc;
 588         int rc = 0;
 589
 590         max_fc = bp->flow_stat->max_fc;
 591
 592         sprintf(type, "bnxt_rx_fc_in_" PCI_PRI_FMT, pdev->addr.domain,
 593                 pdev->addr.bus, pdev->addr.devid, pdev->addr.function);
 594         /* 4 bytes for each counter-id */
 595         rc = bnxt_alloc_ctx_mem_buf(type,
 596                                     max_fc * 4,
 597                                     &bp->flow_stat->rx_fc_in_tbl);
 598         if (rc)
 599                 return rc;
 600
 601         sprintf(type, "bnxt_rx_fc_out_" PCI_PRI_FMT, pdev->addr.domain,
 602                 pdev->addr.bus, pdev->addr.devid, pdev->addr.function);
 603         /* 16 bytes for each counter - 8 bytes pkt_count, 8 bytes byte_count */
 604         rc = bnxt_alloc_ctx_mem_buf(type,
 605                                     max_fc * 16,
 606                                     &bp->flow_stat->rx_fc_out_tbl);
 607         if (rc)
 608                 return rc;
 609
 610         sprintf(type, "bnxt_tx_fc_in_" PCI_PRI_FMT, pdev->addr.domain,
 611                 pdev->addr.bus, pdev->addr.devid, pdev->addr.function);
 612         /* 4 bytes for each counter-id */
 613         rc = bnxt_alloc_ctx_mem_buf(type,
 614                                     max_fc * 4,
 615                                     &bp->flow_stat->tx_fc_in_tbl);
 616         if (rc)
 617                 return rc;
 618
 619         sprintf(type, "bnxt_tx_fc_out_" PCI_PRI_FMT, pdev->addr.domain,
 620                 pdev->addr.bus, pdev->addr.devid, pdev->addr.function);
 621         /* 16 bytes for each counter - 8 bytes pkt_count, 8 bytes byte_count */
 622         rc = bnxt_alloc_ctx_mem_buf(type,
 623                                     max_fc * 16,
 624                                     &bp->flow_stat->tx_fc_out_tbl);
 625         if (rc)
 626                 return rc;
 627
 628         rc = bnxt_register_fc_ctx_mem(bp);
 629
 630         return rc;
 631 }
 632
 633 static int bnxt_init_ctx_mem(struct bnxt *bp)
 634 {
 635         int rc = 0;
 636
 637         if (!(bp->fw_cap & BNXT_FW_CAP_ADV_FLOW_COUNTERS) ||
 638             !(BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp)) ||
 639             !BNXT_FLOW_XSTATS_EN(bp))
 640                 return 0;
 641
 642         rc = bnxt_hwrm_cfa_counter_qcaps(bp, &bp->flow_stat->max_fc);
 643         if (rc)
 644                 return rc;
 645
 646         rc = bnxt_init_fc_ctx_mem(bp);
 647
 648         return rc;
 649 }
 650
 651 static int bnxt_update_phy_setting(struct bnxt *bp)
 652 {
 653         struct rte_eth_link new;
 654         int rc;
 655
 656         rc = bnxt_get_hwrm_link_config(bp, &new);
 657         if (rc) {
 658                 PMD_DRV_LOG(ERR, "Failed to get link settings\n");
 659                 return rc;
 660         }
 661
 662         /*
 663          * On BCM957508-N2100 adapters, FW will not allow any user other
 664          * than BMC to shutdown the port. bnxt_get_hwrm_link_config() call
 665          * always returns link up. Force phy update always in that case.
 666          */
 667         if (!new.link_status || IS_BNXT_DEV_957508_N2100(bp)) {
 668                 rc = bnxt_set_hwrm_link_config(bp, true);
 669                 if (rc) {
 670                         PMD_DRV_LOG(ERR, "Failed to update PHY settings\n");
 671                         return rc;
 672                 }
 673         }
 674
 675         return rc;
 676 }
 677
 678 static int bnxt_init_chip(struct bnxt *bp)
 679 {
 680         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(bp->eth_dev);
 681         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
 682         uint32_t intr_vector = 0;
 683         uint32_t queue_id, base = BNXT_MISC_VEC_ID;
 684         uint32_t vec = BNXT_MISC_VEC_ID;
 685         unsigned int i, j;
 686         int rc;
 687
 688         if (bp->eth_dev->data->mtu > RTE_ETHER_MTU) {
 689                 bp->eth_dev->data->dev_conf.rxmode.offloads |=
 690                         DEV_RX_OFFLOAD_JUMBO_FRAME;
 691                 bp->flags |= BNXT_FLAG_JUMBO;
 692         } else {
 693                 bp->eth_dev->data->dev_conf.rxmode.offloads &=
 694                         ~DEV_RX_OFFLOAD_JUMBO_FRAME;
 695                 bp->flags &= ~BNXT_FLAG_JUMBO;
 696         }
 697
 698         /* THOR does not support ring groups.
 699          * But we will use the array to save RSS context IDs.
 700          */
 701         if (BNXT_CHIP_THOR(bp))
 702                 bp->max_ring_grps = BNXT_MAX_RSS_CTXTS_THOR;
 703
 704         rc = bnxt_alloc_all_hwrm_stat_ctxs(bp);
 705         if (rc) {
 706                 PMD_DRV_LOG(ERR, "HWRM stat ctx alloc failure rc: %x\n", rc);
 707                 goto err_out;
 708         }
 709
 710         rc = bnxt_alloc_hwrm_rings(bp);
 711         if (rc) {
 712                 PMD_DRV_LOG(ERR, "HWRM ring alloc failure rc: %x\n", rc);
 713                 goto err_out;
 714         }
 715
 716         rc = bnxt_alloc_all_hwrm_ring_grps(bp);
 717         if (rc) {
 718                 PMD_DRV_LOG(ERR, "HWRM ring grp alloc failure: %x\n", rc);
 719                 goto err_out;
 720         }
 721
 722         if (!(bp->vnic_cap_flags & BNXT_VNIC_CAP_COS_CLASSIFY))
 723                 goto skip_cosq_cfg;
 724
 725         for (j = 0, i = 0; i < BNXT_COS_QUEUE_COUNT; i++) {
 726                 if (bp->rx_cos_queue[i].id != 0xff) {
 727                         struct bnxt_vnic_info *vnic = &bp->vnic_info[j++];
 728
 729                         if (!vnic) {
 730                                 PMD_DRV_LOG(ERR,
 731                                             "Num pools more than FW profile\n");
 732                                 rc = -EINVAL;
 733                                 goto err_out;
 734                         }
 735                         vnic->cos_queue_id = bp->rx_cos_queue[i].id;
 736                         bp->rx_cosq_cnt++;
 737                 }
 738         }
 739
 740 skip_cosq_cfg:
 741         rc = bnxt_mq_rx_configure(bp);
 742         if (rc) {
 743                 PMD_DRV_LOG(ERR, "MQ mode configure failure rc: %x\n", rc);
 744                 goto err_out;
 745         }
 746
 747         /* VNIC configuration */
 748         for (i = 0; i < bp->nr_vnics; i++) {
 749                 rc = bnxt_setup_one_vnic(bp, i);
 750                 if (rc)
 751                         goto err_out;
 752         }
 753
 754         rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, &bp->vnic_info[0], 0, NULL);
 755         if (rc) {
 756                 PMD_DRV_LOG(ERR,
 757                         "HWRM cfa l2 rx mask failure rc: %x\n", rc);
 758                 goto err_out;
 759         }
 760
 761         /* check and configure queue intr-vector mapping */
 762         if ((rte_intr_cap_multiple(intr_handle) ||
 763              !RTE_ETH_DEV_SRIOV(bp->eth_dev).active) &&
 764             bp->eth_dev->data->dev_conf.intr_conf.rxq != 0) {
 765                 intr_vector = bp->eth_dev->data->nb_rx_queues;
 766                 PMD_DRV_LOG(DEBUG, "intr_vector = %d\n", intr_vector);
 767                 if (intr_vector > bp->rx_cp_nr_rings) {
 768                         PMD_DRV_LOG(ERR, "At most %d intr queues supported",
 769                                         bp->rx_cp_nr_rings);
 770                         return -ENOTSUP;
 771                 }
 772                 rc = rte_intr_efd_enable(intr_handle, intr_vector);
 773                 if (rc)
 774                         return rc;
 775         }
 776
 777         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
 778                 intr_handle->intr_vec =
 779                         rte_zmalloc("intr_vec",
 780                                     bp->eth_dev->data->nb_rx_queues *
 781                                     sizeof(int), 0);
 782                 if (intr_handle->intr_vec == NULL) {
 783                         PMD_DRV_LOG(ERR, "Failed to allocate %d rx_queues"
 784                                 " intr_vec", bp->eth_dev->data->nb_rx_queues);
 785                         rc = -ENOMEM;
 786                         goto err_disable;
 787                 }
 788                 PMD_DRV_LOG(DEBUG, "intr_handle->intr_vec = %p "
 789                         "intr_handle->nb_efd = %d intr_handle->max_intr = %d\n",
 790                          intr_handle->intr_vec, intr_handle->nb_efd,
 791                         intr_handle->max_intr);
 792                 for (queue_id = 0; queue_id < bp->eth_dev->data->nb_rx_queues;
 793                      queue_id++) {
 794                         intr_handle->intr_vec[queue_id] =
 795                                                         vec + BNXT_RX_VEC_START;
 796                         if (vec < base + intr_handle->nb_efd - 1)
 797                                 vec++;
 798                 }
 799         }
 800
 801         /* enable uio/vfio intr/eventfd mapping */
 802         rc = rte_intr_enable(intr_handle);
 803 #ifndef RTE_EXEC_ENV_FREEBSD
 804         /* In FreeBSD OS, nic_uio driver does not support interrupts */
 805         if (rc)
 806                 goto err_free;
 807 #endif
 808
 809         rc = bnxt_update_phy_setting(bp);
 810         if (rc)
 811                 goto err_free;
 812
 813         bp->mark_table = rte_zmalloc("bnxt_mark_table", BNXT_MARK_TABLE_SZ, 0);
 814         if (!bp->mark_table)
 815                 PMD_DRV_LOG(ERR, "Allocation of mark table failed\n");
 816
 817         return 0;
 818
 819 err_free:
 820         rte_free(intr_handle->intr_vec);
 821 err_disable:
 822         rte_intr_efd_disable(intr_handle);
 823 err_out:
 824         /* Some of the error status returned by FW may not be from errno.h */
 825         if (rc > 0)
 826                 rc = -EIO;
 827
 828         return rc;
 829 }
 830
 831 static int bnxt_shutdown_nic(struct bnxt *bp)
 832 {
 833         bnxt_free_all_hwrm_resources(bp);
 834         bnxt_free_all_filters(bp);
 835         bnxt_free_all_vnics(bp);
 836         return 0;
 837 }
 838
 839 /*
 840  * Device configuration and status function
 841  */
 842
 843 uint32_t bnxt_get_speed_capabilities(struct bnxt *bp)
 844 {
 845         uint32_t link_speed = bp->link_info->support_speeds;
 846         uint32_t speed_capa = 0;
 847
 848         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_100MB)
 849                 speed_capa |= ETH_LINK_SPEED_100M;
 850         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_100MBHD)
 851                 speed_capa |= ETH_LINK_SPEED_100M_HD;
 852         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_1GB)
 853                 speed_capa |= ETH_LINK_SPEED_1G;
 854         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_2_5GB)
 855                 speed_capa |= ETH_LINK_SPEED_2_5G;
 856         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_10GB)
 857                 speed_capa |= ETH_LINK_SPEED_10G;
 858         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_20GB)
 859                 speed_capa |= ETH_LINK_SPEED_20G;
 860         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_25GB)
 861                 speed_capa |= ETH_LINK_SPEED_25G;
 862         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_40GB)
 863                 speed_capa |= ETH_LINK_SPEED_40G;
 864         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_50GB)
 865                 speed_capa |= ETH_LINK_SPEED_50G;
 866         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_100GB)
 867                 speed_capa |= ETH_LINK_SPEED_100G;
 868         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_PAM4_SPEEDS_50G)
 869                 speed_capa |= ETH_LINK_SPEED_50G;
 870         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_PAM4_SPEEDS_100G)
 871                 speed_capa |= ETH_LINK_SPEED_100G;
 872         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_PAM4_SPEEDS_200G)
 873                 speed_capa |= ETH_LINK_SPEED_200G;
 874
 875         if (bp->link_info->auto_mode ==
 876             HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_MODE_NONE)
 877                 speed_capa |= ETH_LINK_SPEED_FIXED;
 878         else
 879                 speed_capa |= ETH_LINK_SPEED_AUTONEG;
 880
 881         return speed_capa;
 882 }
 883
 884 static int bnxt_dev_info_get_op(struct rte_eth_dev *eth_dev,
 885                                 struct rte_eth_dev_info *dev_info)
 886 {
 887         struct rte_pci_device *pdev = RTE_DEV_TO_PCI(eth_dev->device);
 888         struct bnxt *bp = eth_dev->data->dev_private;
 889         uint16_t max_vnics, i, j, vpool, vrxq;
 890         unsigned int max_rx_rings;
 891         int rc;
 892
 893         rc = is_bnxt_in_error(bp);
 894         if (rc)
 895                 return rc;
 896
 897         /* MAC Specifics */
 898         dev_info->max_mac_addrs = bp->max_l2_ctx;
 899         dev_info->max_hash_mac_addrs = 0;
 900
 901         /* PF/VF specifics */
 902         if (BNXT_PF(bp))
 903                 dev_info->max_vfs = pdev->max_vfs;
 904
 905         max_rx_rings = BNXT_MAX_RINGS(bp);
 906         /* For the sake of symmetry, max_rx_queues = max_tx_queues */
 907         dev_info->max_rx_queues = max_rx_rings;
 908         dev_info->max_tx_queues = max_rx_rings;
 909         dev_info->reta_size = bnxt_rss_hash_tbl_size(bp);
 910         dev_info->hash_key_size = 40;
 911         max_vnics = bp->max_vnics;
 912
 913         /* MTU specifics */
 914         dev_info->min_mtu = RTE_ETHER_MIN_MTU;
 915         dev_info->max_mtu = BNXT_MAX_MTU;
 916
 917         /* Fast path specifics */
 918         dev_info->min_rx_bufsize = 1;
 919         dev_info->max_rx_pktlen = BNXT_MAX_PKT_LEN;
 920
 921         dev_info->rx_offload_capa = BNXT_DEV_RX_OFFLOAD_SUPPORT;
 922         if (bp->flags & BNXT_FLAG_PTP_SUPPORTED)
 923                 dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_TIMESTAMP;
 924         dev_info->tx_queue_offload_capa = DEV_TX_OFFLOAD_MBUF_FAST_FREE;
 925         dev_info->tx_offload_capa = BNXT_DEV_TX_OFFLOAD_SUPPORT |
 926                                     dev_info->tx_queue_offload_capa;
 927         dev_info->flow_type_rss_offloads = BNXT_ETH_RSS_SUPPORT;
 928
 929         dev_info->speed_capa = bnxt_get_speed_capabilities(bp);
 930
 931         /* *INDENT-OFF* */
 932         dev_info->default_rxconf = (struct rte_eth_rxconf) {
 933                 .rx_thresh = {
 934                         .pthresh = 8,
 935                         .hthresh = 8,
 936                         .wthresh = 0,
 937                 },
 938                 .rx_free_thresh = 32,
 939                 .rx_drop_en = BNXT_DEFAULT_RX_DROP_EN,
 940         };
 941
 942         dev_info->default_txconf = (struct rte_eth_txconf) {
 943                 .tx_thresh = {
 944                         .pthresh = 32,
 945                         .hthresh = 0,
 946                         .wthresh = 0,
 947                 },
 948                 .tx_free_thresh = 32,
 949                 .tx_rs_thresh = 32,
 950         };
 951         eth_dev->data->dev_conf.intr_conf.lsc = 1;
 952
 953         eth_dev->data->dev_conf.intr_conf.rxq = 1;
 954         dev_info->rx_desc_lim.nb_min = BNXT_MIN_RING_DESC;
 955         dev_info->rx_desc_lim.nb_max = BNXT_MAX_RX_RING_DESC;
 956         dev_info->tx_desc_lim.nb_min = BNXT_MIN_RING_DESC;
 957         dev_info->tx_desc_lim.nb_max = BNXT_MAX_TX_RING_DESC;
 958
 959         if (BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp)) {
 960                 dev_info->switch_info.name = eth_dev->device->name;
 961                 dev_info->switch_info.domain_id = bp->switch_domain_id;
 962                 dev_info->switch_info.port_id =
 963                                 BNXT_PF(bp) ? BNXT_SWITCH_PORT_ID_PF :
 964                                     BNXT_SWITCH_PORT_ID_TRUSTED_VF;
 965         }
 966
 967         /* *INDENT-ON* */
 968
 969         /*
 970          * TODO: default_rxconf, default_txconf, rx_desc_lim, and tx_desc_lim
 971          *       need further investigation.
 972          */
 973
 974         /* VMDq resources */
 975         vpool = 64; /* ETH_64_POOLS */
 976         vrxq = 128; /* ETH_VMDQ_DCB_NUM_QUEUES */
 977         for (i = 0; i < 4; vpool >>= 1, i++) {
 978                 if (max_vnics > vpool) {
 979                         for (j = 0; j < 5; vrxq >>= 1, j++) {
 980                                 if (dev_info->max_rx_queues > vrxq) {
 981                                         if (vpool > vrxq)
 982                                                 vpool = vrxq;
 983                                         goto found;
 984                                 }
 985                         }
 986                         /* Not enough resources to support VMDq */
 987                         break;
 988                 }
 989         }
 990         /* Not enough resources to support VMDq */
 991         vpool = 0;
 992         vrxq = 0;
 993 found:
 994         dev_info->max_vmdq_pools = vpool;
 995         dev_info->vmdq_queue_num = vrxq;
 996
 997         dev_info->vmdq_pool_base = 0;
 998         dev_info->vmdq_queue_base = 0;
 999
1000         return 0;
1001 }
1002
1003 /* Configure the device based on the configuration provided */
1004 static int bnxt_dev_configure_op(struct rte_eth_dev *eth_dev)
1005 {
1006         struct bnxt *bp = eth_dev->data->dev_private;
1007         uint64_t rx_offloads = eth_dev->data->dev_conf.rxmode.offloads;
1008         int rc;
1009
1010         bp->rx_queues = (void *)eth_dev->data->rx_queues;
1011         bp->tx_queues = (void *)eth_dev->data->tx_queues;
1012         bp->tx_nr_rings = eth_dev->data->nb_tx_queues;
1013         bp->rx_nr_rings = eth_dev->data->nb_rx_queues;
1014
1015         rc = is_bnxt_in_error(bp);
1016         if (rc)
1017                 return rc;
1018
1019         if (BNXT_VF(bp) && (bp->flags & BNXT_FLAG_NEW_RM)) {
1020                 rc = bnxt_hwrm_check_vf_rings(bp);
1021                 if (rc) {
1022                         PMD_DRV_LOG(ERR, "HWRM insufficient resources\n");
1023                         return -ENOSPC;
1024                 }
1025
1026                 /* If a resource has already been allocated - in this case
1027                  * it is the async completion ring, free it. Reallocate it after
1028                  * resource reservation. This will ensure the resource counts
1029                  * are calculated correctly.
1030                  */
1031
1032                 pthread_mutex_lock(&bp->def_cp_lock);
1033
1034                 if (!BNXT_HAS_NQ(bp) && bp->async_cp_ring) {
1035                         bnxt_disable_int(bp);
1036                         bnxt_free_cp_ring(bp, bp->async_cp_ring);
1037                 }
1038
1039                 rc = bnxt_hwrm_func_reserve_vf_resc(bp, false);
1040                 if (rc) {
1041                         PMD_DRV_LOG(ERR, "HWRM resource alloc fail:%x\n", rc);
1042                         pthread_mutex_unlock(&bp->def_cp_lock);
1043                         return -ENOSPC;
1044                 }
1045
1046                 if (!BNXT_HAS_NQ(bp) && bp->async_cp_ring) {
1047                         rc = bnxt_alloc_async_cp_ring(bp);
1048                         if (rc) {
1049                                 pthread_mutex_unlock(&bp->def_cp_lock);
1050                                 return rc;
1051                         }
1052                         bnxt_enable_int(bp);
1053                 }
1054
1055                 pthread_mutex_unlock(&bp->def_cp_lock);
1056         } else {
1057                 /* legacy driver needs to get updated values */
1058                 rc = bnxt_hwrm_func_qcaps(bp);
1059                 if (rc) {
1060                         PMD_DRV_LOG(ERR, "hwrm func qcaps fail:%d\n", rc);
1061                         return rc;
1062                 }
1063         }
1064
1065         /* Inherit new configurations */
1066         if (eth_dev->data->nb_rx_queues > bp->max_rx_rings ||
1067             eth_dev->data->nb_tx_queues > bp->max_tx_rings ||
1068             eth_dev->data->nb_rx_queues + eth_dev->data->nb_tx_queues
1069                 + BNXT_NUM_ASYNC_CPR(bp) > bp->max_cp_rings ||
1070             eth_dev->data->nb_rx_queues + eth_dev->data->nb_tx_queues >
1071             bp->max_stat_ctx)
1072                 goto resource_error;
1073
1074         if (BNXT_HAS_RING_GRPS(bp) &&
1075             (uint32_t)(eth_dev->data->nb_rx_queues) > bp->max_ring_grps)
1076                 goto resource_error;
1077
1078         if (!(eth_dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_RSS) &&
1079             bp->max_vnics < eth_dev->data->nb_rx_queues)
1080                 goto resource_error;
1081
1082         bp->rx_cp_nr_rings = bp->rx_nr_rings;
1083         bp->tx_cp_nr_rings = bp->tx_nr_rings;
1084
1085         if (eth_dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG)
1086                 rx_offloads |= DEV_RX_OFFLOAD_RSS_HASH;
1087         eth_dev->data->dev_conf.rxmode.offloads = rx_offloads;
1088
1089         if (rx_offloads & DEV_RX_OFFLOAD_JUMBO_FRAME) {
1090                 eth_dev->data->mtu =
1091                         eth_dev->data->dev_conf.rxmode.max_rx_pkt_len -
1092                         RTE_ETHER_HDR_LEN - RTE_ETHER_CRC_LEN - VLAN_TAG_SIZE *
1093                         BNXT_NUM_VLANS;
1094                 bnxt_mtu_set_op(eth_dev, eth_dev->data->mtu);
1095         }
1096         return 0;
1097
1098 resource_error:
1099         PMD_DRV_LOG(ERR,
1100                     "Insufficient resources to support requested config\n");
1101         PMD_DRV_LOG(ERR,
1102                     "Num Queues Requested: Tx %d, Rx %d\n",
1103                     eth_dev->data->nb_tx_queues,
1104                     eth_dev->data->nb_rx_queues);
1105         PMD_DRV_LOG(ERR,
1106                     "MAX: TxQ %d, RxQ %d, CQ %d Stat %d, Grp %d, Vnic %d\n",
1107                     bp->max_tx_rings, bp->max_rx_rings, bp->max_cp_rings,
1108                     bp->max_stat_ctx, bp->max_ring_grps, bp->max_vnics);
1109         return -ENOSPC;
1110 }
1111
1112 void bnxt_print_link_info(struct rte_eth_dev *eth_dev)
1113 {
1114         struct rte_eth_link *link = &eth_dev->data->dev_link;
1115
1116         if (link->link_status)
1117                 PMD_DRV_LOG(INFO, "Port %d Link Up - speed %u Mbps - %s\n",
1118                         eth_dev->data->port_id,
1119                         (uint32_t)link->link_speed,
1120                         (link->link_duplex == ETH_LINK_FULL_DUPLEX) ?
1121                         ("full-duplex") : ("half-duplex\n"));
1122         else
1123                 PMD_DRV_LOG(INFO, "Port %d Link Down\n",
1124                         eth_dev->data->port_id);
1125 }
1126
1127 /*
1128  * Determine whether the current configuration requires support for scattered
1129  * receive; return 1 if scattered receive is required and 0 if not.
1130  */
1131 static int bnxt_scattered_rx(struct rte_eth_dev *eth_dev)
1132 {
1133         uint16_t buf_size;
1134         int i;
1135
1136         if (eth_dev->data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_SCATTER)
1137                 return 1;
1138
1139         for (i = 0; i < eth_dev->data->nb_rx_queues; i++) {
1140                 struct bnxt_rx_queue *rxq = eth_dev->data->rx_queues[i];
1141
1142                 buf_size = (uint16_t)(rte_pktmbuf_data_room_size(rxq->mb_pool) -
1143                                       RTE_PKTMBUF_HEADROOM);
1144                 if (eth_dev->data->dev_conf.rxmode.max_rx_pkt_len > buf_size)
1145                         return 1;
1146         }
1147         return 0;
1148 }
1149
1150 static eth_rx_burst_t
1151 bnxt_receive_function(struct rte_eth_dev *eth_dev)
1152 {
1153         struct bnxt *bp = eth_dev->data->dev_private;
1154
1155 #if defined(RTE_ARCH_X86) || defined(RTE_ARCH_ARM64)
1156 #ifndef RTE_LIBRTE_IEEE1588
1157         /*
1158          * Vector mode receive can be enabled only if scatter rx is not
1159          * in use and rx offloads are limited to VLAN stripping and
1160          * CRC stripping.
1161          */
1162         if (!eth_dev->data->scattered_rx &&
1163             !(eth_dev->data->dev_conf.rxmode.offloads &
1164               ~(DEV_RX_OFFLOAD_VLAN_STRIP |
1165                 DEV_RX_OFFLOAD_KEEP_CRC |
1166                 DEV_RX_OFFLOAD_JUMBO_FRAME |
1167                 DEV_RX_OFFLOAD_IPV4_CKSUM |
1168                 DEV_RX_OFFLOAD_UDP_CKSUM |
1169                 DEV_RX_OFFLOAD_TCP_CKSUM |
1170                 DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM |
1171                 DEV_RX_OFFLOAD_RSS_HASH |
1172                 DEV_RX_OFFLOAD_VLAN_FILTER)) &&
1173             !BNXT_TRUFLOW_EN(bp) && BNXT_NUM_ASYNC_CPR(bp) &&
1174             rte_vect_get_max_simd_bitwidth() >= RTE_VECT_SIMD_128) {
1175                 PMD_DRV_LOG(INFO, "Using vector mode receive for port %d\n",
1176                             eth_dev->data->port_id);
1177                 bp->flags |= BNXT_FLAG_RX_VECTOR_PKT_MODE;
1178                 return bnxt_recv_pkts_vec;
1179         }
1180         PMD_DRV_LOG(INFO, "Vector mode receive disabled for port %d\n",
1181                     eth_dev->data->port_id);
1182         PMD_DRV_LOG(INFO,
1183                     "Port %d scatter: %d rx offload: %" PRIX64 "\n",
1184                     eth_dev->data->port_id,
1185                     eth_dev->data->scattered_rx,
1186                     eth_dev->data->dev_conf.rxmode.offloads);
1187 #endif
1188 #endif
1189         bp->flags &= ~BNXT_FLAG_RX_VECTOR_PKT_MODE;
1190         return bnxt_recv_pkts;
1191 }
1192
1193 static eth_tx_burst_t
1194 bnxt_transmit_function(__rte_unused struct rte_eth_dev *eth_dev)
1195 {
1196 #if defined(RTE_ARCH_X86) || defined(RTE_ARCH_ARM64)
1197 #ifndef RTE_LIBRTE_IEEE1588
1198         uint64_t offloads = eth_dev->data->dev_conf.txmode.offloads;
1199         struct bnxt *bp = eth_dev->data->dev_private;
1200
1201         /*
1202          * Vector mode transmit can be enabled only if not using scatter rx
1203          * or tx offloads.
1204          */
1205         if (!eth_dev->data->scattered_rx &&
1206             !(offloads & ~DEV_TX_OFFLOAD_MBUF_FAST_FREE) &&
1207             !BNXT_TRUFLOW_EN(bp) &&
1208             rte_vect_get_max_simd_bitwidth() >= RTE_VECT_SIMD_128) {
1209                 PMD_DRV_LOG(INFO, "Using vector mode transmit for port %d\n",
1210                             eth_dev->data->port_id);
1211                 return bnxt_xmit_pkts_vec;
1212         }
1213         PMD_DRV_LOG(INFO, "Vector mode transmit disabled for port %d\n",
1214                     eth_dev->data->port_id);
1215         PMD_DRV_LOG(INFO,
1216                     "Port %d scatter: %d tx offload: %" PRIX64 "\n",
1217                     eth_dev->data->port_id,
1218                     eth_dev->data->scattered_rx,
1219                     offloads);
1220 #endif
1221 #endif
1222         return bnxt_xmit_pkts;
1223 }
1224
1225 static int bnxt_handle_if_change_status(struct bnxt *bp)
1226 {
1227         int rc;
1228
1229         /* Since fw has undergone a reset and lost all contexts,
1230          * set fatal flag to not issue hwrm during cleanup
1231          */
1232         bp->flags |= BNXT_FLAG_FATAL_ERROR;
1233         bnxt_uninit_resources(bp, true);
1234
1235         /* clear fatal flag so that re-init happens */
1236         bp->flags &= ~BNXT_FLAG_FATAL_ERROR;
1237         rc = bnxt_init_resources(bp, true);
1238
1239         bp->flags &= ~BNXT_FLAG_IF_CHANGE_HOT_FW_RESET_DONE;
1240
1241         return rc;
1242 }
1243
1244 static int bnxt_dev_start_op(struct rte_eth_dev *eth_dev)
1245 {
1246         struct bnxt *bp = eth_dev->data->dev_private;
1247         uint64_t rx_offloads = eth_dev->data->dev_conf.rxmode.offloads;
1248         int vlan_mask = 0;
1249         int rc, retry_cnt = BNXT_IF_CHANGE_RETRY_COUNT;
1250
1251         if (!eth_dev->data->nb_tx_queues || !eth_dev->data->nb_rx_queues) {
1252                 PMD_DRV_LOG(ERR, "Queues are not configured yet!\n");
1253                 return -EINVAL;
1254         }
1255
1256         if (bp->rx_cp_nr_rings > RTE_ETHDEV_QUEUE_STAT_CNTRS) {
1257                 PMD_DRV_LOG(ERR,
1258                         "RxQ cnt %d > CONFIG_RTE_ETHDEV_QUEUE_STAT_CNTRS %d\n",
1259                         bp->rx_cp_nr_rings, RTE_ETHDEV_QUEUE_STAT_CNTRS);
1260         }
1261
1262         do {
1263                 rc = bnxt_hwrm_if_change(bp, true);
1264                 if (rc == 0 || rc != -EAGAIN)
1265                         break;
1266
1267                 rte_delay_ms(BNXT_IF_CHANGE_RETRY_INTERVAL);
1268         } while (retry_cnt--);
1269
1270         if (rc)
1271                 return rc;
1272
1273         if (bp->flags & BNXT_FLAG_IF_CHANGE_HOT_FW_RESET_DONE) {
1274                 rc = bnxt_handle_if_change_status(bp);
1275                 if (rc)
1276                         return rc;
1277         }
1278
1279         bnxt_enable_int(bp);
1280
1281         rc = bnxt_init_chip(bp);
1282         if (rc)
1283                 goto error;
1284
1285         eth_dev->data->scattered_rx = bnxt_scattered_rx(eth_dev);
1286         eth_dev->data->dev_started = 1;
1287
1288         bnxt_link_update_op(eth_dev, 1);
1289
1290         if (rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER)
1291                 vlan_mask |= ETH_VLAN_FILTER_MASK;
1292         if (rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
1293                 vlan_mask |= ETH_VLAN_STRIP_MASK;
1294         rc = bnxt_vlan_offload_set_op(eth_dev, vlan_mask);
1295         if (rc)
1296                 goto error;
1297
1298         /* Initialize bnxt ULP port details */
1299         rc = bnxt_ulp_port_init(bp);
1300         if (rc)
1301                 goto error;
1302
1303         eth_dev->rx_pkt_burst = bnxt_receive_function(eth_dev);
1304         eth_dev->tx_pkt_burst = bnxt_transmit_function(eth_dev);
1305
1306         bnxt_schedule_fw_health_check(bp);
1307
1308         return 0;
1309
1310 error:
1311         bnxt_shutdown_nic(bp);
1312         bnxt_free_tx_mbufs(bp);
1313         bnxt_free_rx_mbufs(bp);
1314         bnxt_hwrm_if_change(bp, false);
1315         eth_dev->data->dev_started = 0;
1316         return rc;
1317 }
1318
1319 static int bnxt_dev_set_link_up_op(struct rte_eth_dev *eth_dev)
1320 {
1321         struct bnxt *bp = eth_dev->data->dev_private;
1322         int rc = 0;
1323
1324         if (!bp->link_info->link_up)
1325                 rc = bnxt_set_hwrm_link_config(bp, true);
1326         if (!rc)
1327                 eth_dev->data->dev_link.link_status = 1;
1328
1329         bnxt_print_link_info(eth_dev);
1330         return rc;
1331 }
1332
1333 static int bnxt_dev_set_link_down_op(struct rte_eth_dev *eth_dev)
1334 {
1335         struct bnxt *bp = eth_dev->data->dev_private;
1336
1337         eth_dev->data->dev_link.link_status = 0;
1338         bnxt_set_hwrm_link_config(bp, false);
1339         bp->link_info->link_up = 0;
1340
1341         return 0;
1342 }
1343
1344 static void bnxt_free_switch_domain(struct bnxt *bp)
1345 {
1346         if (bp->switch_domain_id)
1347                 rte_eth_switch_domain_free(bp->switch_domain_id);
1348 }
1349
1350 /* Unload the driver, release resources */
1351 static int bnxt_dev_stop_op(struct rte_eth_dev *eth_dev)
1352 {
1353         struct bnxt *bp = eth_dev->data->dev_private;
1354         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1355         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1356         struct rte_eth_link link;
1357         int ret;
1358
1359         eth_dev->data->dev_started = 0;
1360         eth_dev->data->scattered_rx = 0;
1361
1362         /* Prevent crashes when queues are still in use */
1363         eth_dev->rx_pkt_burst = &bnxt_dummy_recv_pkts;
1364         eth_dev->tx_pkt_burst = &bnxt_dummy_xmit_pkts;
1365
1366         bnxt_disable_int(bp);
1367
1368         /* disable uio/vfio intr/eventfd mapping */
1369         rte_intr_disable(intr_handle);
1370
1371         /* Stop the child representors for this device */
1372         ret = bnxt_rep_stop_all(bp);
1373         if (ret != 0)
1374                 return ret;
1375
1376         /* delete the bnxt ULP port details */
1377         bnxt_ulp_port_deinit(bp);
1378
1379         bnxt_cancel_fw_health_check(bp);
1380
1381         /* Do not bring link down during reset recovery */
1382         if (!is_bnxt_in_error(bp)) {
1383                 bnxt_dev_set_link_down_op(eth_dev);
1384                 /* Wait for link to be reset */
1385                 if (BNXT_SINGLE_PF(bp))
1386                         rte_delay_ms(500);
1387                 /* clear the recorded link status */
1388                 memset(&link, 0, sizeof(link));
1389                 rte_eth_linkstatus_set(eth_dev, &link);
1390         }
1391
1392         /* Clean queue intr-vector mapping */
1393         rte_intr_efd_disable(intr_handle);
1394         if (intr_handle->intr_vec != NULL) {
1395                 rte_free(intr_handle->intr_vec);
1396                 intr_handle->intr_vec = NULL;
1397         }
1398
1399         bnxt_hwrm_port_clr_stats(bp);
1400         bnxt_free_tx_mbufs(bp);
1401         bnxt_free_rx_mbufs(bp);
1402         /* Process any remaining notifications in default completion queue */
1403         bnxt_int_handler(eth_dev);
1404         bnxt_shutdown_nic(bp);
1405         bnxt_hwrm_if_change(bp, false);
1406
1407         rte_free(bp->mark_table);
1408         bp->mark_table = NULL;
1409
1410         bp->flags &= ~BNXT_FLAG_RX_VECTOR_PKT_MODE;
1411         bp->rx_cosq_cnt = 0;
1412         /* All filters are deleted on a port stop. */
1413         if (BNXT_FLOW_XSTATS_EN(bp))
1414                 bp->flow_stat->flow_count = 0;
1415
1416         return 0;
1417 }
1418
1419 static int bnxt_dev_close_op(struct rte_eth_dev *eth_dev)
1420 {
1421         struct bnxt *bp = eth_dev->data->dev_private;
1422         int ret = 0;
1423
1424         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1425                 return 0;
1426
1427         /* cancel the recovery handler before remove dev */
1428         rte_eal_alarm_cancel(bnxt_dev_reset_and_resume, (void *)bp);
1429         rte_eal_alarm_cancel(bnxt_dev_recover, (void *)bp);
1430         bnxt_cancel_fc_thread(bp);
1431
1432         if (eth_dev->data->dev_started)
1433                 ret = bnxt_dev_stop_op(eth_dev);
1434
1435         bnxt_free_switch_domain(bp);
1436
1437         bnxt_uninit_resources(bp, false);
1438
1439         bnxt_free_leds_info(bp);
1440         bnxt_free_cos_queues(bp);
1441         bnxt_free_link_info(bp);
1442         bnxt_free_pf_info(bp);
1443         bnxt_free_parent_info(bp);
1444
1445         rte_memzone_free((const struct rte_memzone *)bp->tx_mem_zone);
1446         bp->tx_mem_zone = NULL;
1447         rte_memzone_free((const struct rte_memzone *)bp->rx_mem_zone);
1448         bp->rx_mem_zone = NULL;
1449
1450         bnxt_hwrm_free_vf_info(bp);
1451
1452         rte_free(bp->grp_info);
1453         bp->grp_info = NULL;
1454
1455         return ret;
1456 }
1457
1458 static void bnxt_mac_addr_remove_op(struct rte_eth_dev *eth_dev,
1459                                     uint32_t index)
1460 {
1461         struct bnxt *bp = eth_dev->data->dev_private;
1462         uint64_t pool_mask = eth_dev->data->mac_pool_sel[index];
1463         struct bnxt_vnic_info *vnic;
1464         struct bnxt_filter_info *filter, *temp_filter;
1465         uint32_t i;
1466
1467         if (is_bnxt_in_error(bp))
1468                 return;
1469
1470         /*
1471          * Loop through all VNICs from the specified filter flow pools to
1472          * remove the corresponding MAC addr filter
1473          */
1474         for (i = 0; i < bp->nr_vnics; i++) {
1475                 if (!(pool_mask & (1ULL << i)))
1476                         continue;
1477
1478                 vnic = &bp->vnic_info[i];
1479                 filter = STAILQ_FIRST(&vnic->filter);
1480                 while (filter) {
1481                         temp_filter = STAILQ_NEXT(filter, next);
1482                         if (filter->mac_index == index) {
1483                                 STAILQ_REMOVE(&vnic->filter, filter,
1484                                                 bnxt_filter_info, next);
1485                                 bnxt_hwrm_clear_l2_filter(bp, filter);
1486                                 bnxt_free_filter(bp, filter);
1487                         }
1488                         filter = temp_filter;
1489                 }
1490         }
1491 }
1492
1493 static int bnxt_add_mac_filter(struct bnxt *bp, struct bnxt_vnic_info *vnic,
1494                                struct rte_ether_addr *mac_addr, uint32_t index,
1495                                uint32_t pool)
1496 {
1497         struct bnxt_filter_info *filter;
1498         int rc = 0;
1499
1500         /* Attach requested MAC address to the new l2_filter */
1501         STAILQ_FOREACH(filter, &vnic->filter, next) {
1502                 if (filter->mac_index == index) {
1503                         PMD_DRV_LOG(DEBUG,
1504                                     "MAC addr already existed for pool %d\n",
1505                                     pool);
1506                         return 0;
1507                 }
1508         }
1509
1510         filter = bnxt_alloc_filter(bp);
1511         if (!filter) {
1512                 PMD_DRV_LOG(ERR, "L2 filter alloc failed\n");
1513                 return -ENODEV;
1514         }
1515
1516         /* bnxt_alloc_filter copies default MAC to filter->l2_addr. So,
1517          * if the MAC that's been programmed now is a different one, then,
1518          * copy that addr to filter->l2_addr
1519          */
1520         if (mac_addr)
1521                 memcpy(filter->l2_addr, mac_addr, RTE_ETHER_ADDR_LEN);
1522         filter->flags |= HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_OUTERMOST;
1523
1524         rc = bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id, filter);
1525         if (!rc) {
1526                 filter->mac_index = index;
1527                 if (filter->mac_index == 0)
1528                         STAILQ_INSERT_HEAD(&vnic->filter, filter, next);
1529                 else
1530                         STAILQ_INSERT_TAIL(&vnic->filter, filter, next);
1531         } else {
1532                 bnxt_free_filter(bp, filter);
1533         }
1534
1535         return rc;
1536 }
1537
1538 static int bnxt_mac_addr_add_op(struct rte_eth_dev *eth_dev,
1539                                 struct rte_ether_addr *mac_addr,
1540                                 uint32_t index, uint32_t pool)
1541 {
1542         struct bnxt *bp = eth_dev->data->dev_private;
1543         struct bnxt_vnic_info *vnic = &bp->vnic_info[pool];
1544         int rc = 0;
1545
1546         rc = is_bnxt_in_error(bp);
1547         if (rc)
1548                 return rc;
1549
1550         if (BNXT_VF(bp) & !BNXT_VF_IS_TRUSTED(bp)) {
1551                 PMD_DRV_LOG(ERR, "Cannot add MAC address to a VF interface\n");
1552                 return -ENOTSUP;
1553         }
1554
1555         if (!vnic) {
1556                 PMD_DRV_LOG(ERR, "VNIC not found for pool %d!\n", pool);
1557                 return -EINVAL;
1558         }
1559
1560         /* Filter settings will get applied when port is started */
1561         if (!eth_dev->data->dev_started)
1562                 return 0;
1563
1564         rc = bnxt_add_mac_filter(bp, vnic, mac_addr, index, pool);
1565
1566         return rc;
1567 }
1568
1569 int bnxt_link_update_op(struct rte_eth_dev *eth_dev, int wait_to_complete)
1570 {
1571         int rc = 0;
1572         struct bnxt *bp = eth_dev->data->dev_private;
1573         struct rte_eth_link new;
1574         int cnt = wait_to_complete ? BNXT_MAX_LINK_WAIT_CNT :
1575                         BNXT_MIN_LINK_WAIT_CNT;
1576
1577         rc = is_bnxt_in_error(bp);
1578         if (rc)
1579                 return rc;
1580
1581         memset(&new, 0, sizeof(new));
1582         do {
1583                 /* Retrieve link info from hardware */
1584                 rc = bnxt_get_hwrm_link_config(bp, &new);
1585                 if (rc) {
1586                         new.link_speed = ETH_LINK_SPEED_100M;
1587                         new.link_duplex = ETH_LINK_FULL_DUPLEX;
1588                         PMD_DRV_LOG(ERR,
1589                                 "Failed to retrieve link rc = 0x%x!\n", rc);
1590                         goto out;
1591                 }
1592
1593                 if (!wait_to_complete || new.link_status)
1594                         break;
1595
1596                 rte_delay_ms(BNXT_LINK_WAIT_INTERVAL);
1597         } while (cnt--);
1598
1599         /* Only single function PF can bring phy down.
1600          * When port is stopped, report link down for VF/MH/NPAR functions.
1601          */
1602         if (!BNXT_SINGLE_PF(bp) && !eth_dev->data->dev_started)
1603                 memset(&new, 0, sizeof(new));
1604
1605 out:
1606         /* Timed out or success */
1607         if (new.link_status != eth_dev->data->dev_link.link_status ||
1608         new.link_speed != eth_dev->data->dev_link.link_speed) {
1609                 rte_eth_linkstatus_set(eth_dev, &new);
1610
1611                 rte_eth_dev_callback_process(eth_dev,
1612                                              RTE_ETH_EVENT_INTR_LSC,
1613                                              NULL);
1614
1615                 bnxt_print_link_info(eth_dev);
1616         }
1617
1618         return rc;
1619 }
1620
1621 static int bnxt_promiscuous_enable_op(struct rte_eth_dev *eth_dev)
1622 {
1623         struct bnxt *bp = eth_dev->data->dev_private;
1624         struct bnxt_vnic_info *vnic;
1625         uint32_t old_flags;
1626         int rc;
1627
1628         rc = is_bnxt_in_error(bp);
1629         if (rc)
1630                 return rc;
1631
1632         /* Filter settings will get applied when port is started */
1633         if (!eth_dev->data->dev_started)
1634                 return 0;
1635
1636         if (bp->vnic_info == NULL)
1637                 return 0;
1638
1639         vnic = BNXT_GET_DEFAULT_VNIC(bp);
1640
1641         old_flags = vnic->flags;
1642         vnic->flags |= BNXT_VNIC_INFO_PROMISC;
1643         rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1644         if (rc != 0)
1645                 vnic->flags = old_flags;
1646
1647         return rc;
1648 }
1649
1650 static int bnxt_promiscuous_disable_op(struct rte_eth_dev *eth_dev)
1651 {
1652         struct bnxt *bp = eth_dev->data->dev_private;
1653         struct bnxt_vnic_info *vnic;
1654         uint32_t old_flags;
1655         int rc;
1656
1657         rc = is_bnxt_in_error(bp);
1658         if (rc)
1659                 return rc;
1660
1661         /* Filter settings will get applied when port is started */
1662         if (!eth_dev->data->dev_started)
1663                 return 0;
1664
1665         if (bp->vnic_info == NULL)
1666                 return 0;
1667
1668         vnic = BNXT_GET_DEFAULT_VNIC(bp);
1669
1670         old_flags = vnic->flags;
1671         vnic->flags &= ~BNXT_VNIC_INFO_PROMISC;
1672         rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1673         if (rc != 0)
1674                 vnic->flags = old_flags;
1675
1676         return rc;
1677 }
1678
1679 static int bnxt_allmulticast_enable_op(struct rte_eth_dev *eth_dev)
1680 {
1681         struct bnxt *bp = eth_dev->data->dev_private;
1682         struct bnxt_vnic_info *vnic;
1683         uint32_t old_flags;
1684         int rc;
1685
1686         rc = is_bnxt_in_error(bp);
1687         if (rc)
1688                 return rc;
1689
1690         /* Filter settings will get applied when port is started */
1691         if (!eth_dev->data->dev_started)
1692                 return 0;
1693
1694         if (bp->vnic_info == NULL)
1695                 return 0;
1696
1697         vnic = BNXT_GET_DEFAULT_VNIC(bp);
1698
1699         old_flags = vnic->flags;
1700         vnic->flags |= BNXT_VNIC_INFO_ALLMULTI;
1701         rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1702         if (rc != 0)
1703                 vnic->flags = old_flags;
1704
1705         return rc;
1706 }
1707
1708 static int bnxt_allmulticast_disable_op(struct rte_eth_dev *eth_dev)
1709 {
1710         struct bnxt *bp = eth_dev->data->dev_private;
1711         struct bnxt_vnic_info *vnic;
1712         uint32_t old_flags;
1713         int rc;
1714
1715         rc = is_bnxt_in_error(bp);
1716         if (rc)
1717                 return rc;
1718
1719         /* Filter settings will get applied when port is started */
1720         if (!eth_dev->data->dev_started)
1721                 return 0;
1722
1723         if (bp->vnic_info == NULL)
1724                 return 0;
1725
1726         vnic = BNXT_GET_DEFAULT_VNIC(bp);
1727
1728         old_flags = vnic->flags;
1729         vnic->flags &= ~BNXT_VNIC_INFO_ALLMULTI;
1730         rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1731         if (rc != 0)
1732                 vnic->flags = old_flags;
1733
1734         return rc;
1735 }
1736
1737 /* Return bnxt_rx_queue pointer corresponding to a given rxq. */
1738 static struct bnxt_rx_queue *bnxt_qid_to_rxq(struct bnxt *bp, uint16_t qid)
1739 {
1740         if (qid >= bp->rx_nr_rings)
1741                 return NULL;
1742
1743         return bp->eth_dev->data->rx_queues[qid];
1744 }
1745
1746 /* Return rxq corresponding to a given rss table ring/group ID. */
1747 static uint16_t bnxt_rss_to_qid(struct bnxt *bp, uint16_t fwr)
1748 {
1749         struct bnxt_rx_queue *rxq;
1750         unsigned int i;
1751
1752         if (!BNXT_HAS_RING_GRPS(bp)) {
1753                 for (i = 0; i < bp->rx_nr_rings; i++) {
1754                         rxq = bp->eth_dev->data->rx_queues[i];
1755                         if (rxq->rx_ring->rx_ring_struct->fw_ring_id == fwr)
1756                                 return rxq->index;
1757                 }
1758         } else {
1759                 for (i = 0; i < bp->rx_nr_rings; i++) {
1760                         if (bp->grp_info[i].fw_grp_id == fwr)
1761                                 return i;
1762                 }
1763         }
1764
1765         return INVALID_HW_RING_ID;
1766 }
1767
1768 static int bnxt_reta_update_op(struct rte_eth_dev *eth_dev,
1769                             struct rte_eth_rss_reta_entry64 *reta_conf,
1770                             uint16_t reta_size)
1771 {
1772         struct bnxt *bp = eth_dev->data->dev_private;
1773         struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
1774         struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp);
1775         uint16_t tbl_size = bnxt_rss_hash_tbl_size(bp);
1776         uint16_t idx, sft;
1777         int i, rc;
1778
1779         rc = is_bnxt_in_error(bp);
1780         if (rc)
1781                 return rc;
1782
1783         if (!vnic->rss_table)
1784                 return -EINVAL;
1785
1786         if (!(dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG))
1787                 return -EINVAL;
1788
1789         if (reta_size != tbl_size) {
1790                 PMD_DRV_LOG(ERR, "The configured hash table lookup size "
1791                         "(%d) must equal the size supported by the hardware "
1792                         "(%d)\n", reta_size, tbl_size);
1793                 return -EINVAL;
1794         }
1795
1796         for (i = 0; i < reta_size; i++) {
1797                 struct bnxt_rx_queue *rxq;
1798
1799                 idx = i / RTE_RETA_GROUP_SIZE;
1800                 sft = i % RTE_RETA_GROUP_SIZE;
1801
1802                 if (!(reta_conf[idx].mask & (1ULL << sft)))
1803                         continue;
1804
1805                 rxq = bnxt_qid_to_rxq(bp, reta_conf[idx].reta[sft]);
1806                 if (!rxq) {
1807                         PMD_DRV_LOG(ERR, "Invalid ring in reta_conf.\n");
1808                         return -EINVAL;
1809                 }
1810
1811                 if (BNXT_CHIP_THOR(bp)) {
1812                         vnic->rss_table[i * 2] =
1813                                 rxq->rx_ring->rx_ring_struct->fw_ring_id;
1814                         vnic->rss_table[i * 2 + 1] =
1815                                 rxq->cp_ring->cp_ring_struct->fw_ring_id;
1816                 } else {
1817                         vnic->rss_table[i] =
1818                             vnic->fw_grp_ids[reta_conf[idx].reta[sft]];
1819                 }
1820         }
1821
1822         bnxt_hwrm_vnic_rss_cfg(bp, vnic);
1823         return 0;
1824 }
1825
1826 static int bnxt_reta_query_op(struct rte_eth_dev *eth_dev,
1827                               struct rte_eth_rss_reta_entry64 *reta_conf,
1828                               uint16_t reta_size)
1829 {
1830         struct bnxt *bp = eth_dev->data->dev_private;
1831         struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp);
1832         uint16_t tbl_size = bnxt_rss_hash_tbl_size(bp);
1833         uint16_t idx, sft, i;
1834         int rc;
1835
1836         rc = is_bnxt_in_error(bp);
1837         if (rc)
1838                 return rc;
1839
1840         /* Retrieve from the default VNIC */
1841         if (!vnic)
1842                 return -EINVAL;
1843         if (!vnic->rss_table)
1844                 return -EINVAL;
1845
1846         if (reta_size != tbl_size) {
1847                 PMD_DRV_LOG(ERR, "The configured hash table lookup size "
1848                         "(%d) must equal the size supported by the hardware "
1849                         "(%d)\n", reta_size, tbl_size);
1850                 return -EINVAL;
1851         }
1852
1853         for (idx = 0, i = 0; i < reta_size; i++) {
1854                 idx = i / RTE_RETA_GROUP_SIZE;
1855                 sft = i % RTE_RETA_GROUP_SIZE;
1856
1857                 if (reta_conf[idx].mask & (1ULL << sft)) {
1858                         uint16_t qid;
1859
1860                         if (BNXT_CHIP_THOR(bp))
1861                                 qid = bnxt_rss_to_qid(bp,
1862                                                       vnic->rss_table[i * 2]);
1863                         else
1864                                 qid = bnxt_rss_to_qid(bp, vnic->rss_table[i]);
1865
1866                         if (qid == INVALID_HW_RING_ID) {
1867                                 PMD_DRV_LOG(ERR, "Inv. entry in rss table.\n");
1868                                 return -EINVAL;
1869                         }
1870                         reta_conf[idx].reta[sft] = qid;
1871                 }
1872         }
1873
1874         return 0;
1875 }
1876
1877 static int bnxt_rss_hash_update_op(struct rte_eth_dev *eth_dev,
1878                                    struct rte_eth_rss_conf *rss_conf)
1879 {
1880         struct bnxt *bp = eth_dev->data->dev_private;
1881         struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
1882         struct bnxt_vnic_info *vnic;
1883         int rc;
1884
1885         rc = is_bnxt_in_error(bp);
1886         if (rc)
1887                 return rc;
1888
1889         /*
1890          * If RSS enablement were different than dev_configure,
1891          * then return -EINVAL
1892          */
1893         if (dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG) {
1894                 if (!rss_conf->rss_hf)
1895                         PMD_DRV_LOG(ERR, "Hash type NONE\n");
1896         } else {
1897                 if (rss_conf->rss_hf & BNXT_ETH_RSS_SUPPORT)
1898                         return -EINVAL;
1899         }
1900
1901         bp->flags |= BNXT_FLAG_UPDATE_HASH;
1902         memcpy(&eth_dev->data->dev_conf.rx_adv_conf.rss_conf,
1903                rss_conf,
1904                sizeof(*rss_conf));
1905
1906         /* Update the default RSS VNIC(s) */
1907         vnic = BNXT_GET_DEFAULT_VNIC(bp);
1908         vnic->hash_type = bnxt_rte_to_hwrm_hash_types(rss_conf->rss_hf);
1909         vnic->hash_mode =
1910                 bnxt_rte_to_hwrm_hash_level(bp, rss_conf->rss_hf,
1911                                             ETH_RSS_LEVEL(rss_conf->rss_hf));
1912
1913         /*
1914          * If hashkey is not specified, use the previously configured
1915          * hashkey
1916          */
1917         if (!rss_conf->rss_key)
1918                 goto rss_config;
1919
1920         if (rss_conf->rss_key_len != HW_HASH_KEY_SIZE) {
1921                 PMD_DRV_LOG(ERR,
1922                             "Invalid hashkey length, should be 16 bytes\n");
1923                 return -EINVAL;
1924         }
1925         memcpy(vnic->rss_hash_key, rss_conf->rss_key, rss_conf->rss_key_len);
1926
1927 rss_config:
1928         bnxt_hwrm_vnic_rss_cfg(bp, vnic);
1929         return 0;
1930 }
1931
1932 static int bnxt_rss_hash_conf_get_op(struct rte_eth_dev *eth_dev,
1933                                      struct rte_eth_rss_conf *rss_conf)
1934 {
1935         struct bnxt *bp = eth_dev->data->dev_private;
1936         struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp);
1937         int len, rc;
1938         uint32_t hash_types;
1939
1940         rc = is_bnxt_in_error(bp);
1941         if (rc)
1942                 return rc;
1943
1944         /* RSS configuration is the same for all VNICs */
1945         if (vnic && vnic->rss_hash_key) {
1946                 if (rss_conf->rss_key) {
1947                         len = rss_conf->rss_key_len <= HW_HASH_KEY_SIZE ?
1948                               rss_conf->rss_key_len : HW_HASH_KEY_SIZE;
1949                         memcpy(rss_conf->rss_key, vnic->rss_hash_key, len);
1950                 }
1951
1952                 hash_types = vnic->hash_type;
1953                 rss_conf->rss_hf = 0;
1954                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV4) {
1955                         rss_conf->rss_hf |= ETH_RSS_IPV4;
1956                         hash_types &= ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV4;
1957                 }
1958                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV4) {
1959                         rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP;
1960                         hash_types &=
1961                                 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV4;
1962                 }
1963                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV4) {
1964                         rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
1965                         hash_types &=
1966                                 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV4;
1967                 }
1968                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6) {
1969                         rss_conf->rss_hf |= ETH_RSS_IPV6;
1970                         hash_types &= ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6;
1971                 }
1972                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV6) {
1973                         rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV6_TCP;
1974                         hash_types &=
1975                                 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV6;
1976                 }
1977                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV6) {
1978                         rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;
1979                         hash_types &=
1980                                 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV6;
1981                 }
1982
1983                 rss_conf->rss_hf |=
1984                         bnxt_hwrm_to_rte_rss_level(bp, vnic->hash_mode);
1985
1986                 if (hash_types) {
1987                         PMD_DRV_LOG(ERR,
1988                                 "Unknown RSS config from firmware (%08x), RSS disabled",
1989                                 vnic->hash_type);
1990                         return -ENOTSUP;
1991                 }
1992         } else {
1993                 rss_conf->rss_hf = 0;
1994         }
1995         return 0;
1996 }
1997
1998 static int bnxt_flow_ctrl_get_op(struct rte_eth_dev *dev,
1999                                struct rte_eth_fc_conf *fc_conf)
2000 {
2001         struct bnxt *bp = dev->data->dev_private;
2002         struct rte_eth_link link_info;
2003         int rc;
2004
2005         rc = is_bnxt_in_error(bp);
2006         if (rc)
2007                 return rc;
2008
2009         rc = bnxt_get_hwrm_link_config(bp, &link_info);
2010         if (rc)
2011                 return rc;
2012
2013         memset(fc_conf, 0, sizeof(*fc_conf));
2014         if (bp->link_info->auto_pause)
2015                 fc_conf->autoneg = 1;
2016         switch (bp->link_info->pause) {
2017         case 0:
2018                 fc_conf->mode = RTE_FC_NONE;
2019                 break;
2020         case HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_TX:
2021                 fc_conf->mode = RTE_FC_TX_PAUSE;
2022                 break;
2023         case HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_RX:
2024                 fc_conf->mode = RTE_FC_RX_PAUSE;
2025                 break;
2026         case (HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_TX |
2027                         HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_RX):
2028                 fc_conf->mode = RTE_FC_FULL;
2029                 break;
2030         }
2031         return 0;
2032 }
2033
2034 static int bnxt_flow_ctrl_set_op(struct rte_eth_dev *dev,
2035                                struct rte_eth_fc_conf *fc_conf)
2036 {
2037         struct bnxt *bp = dev->data->dev_private;
2038         int rc;
2039
2040         rc = is_bnxt_in_error(bp);
2041         if (rc)
2042                 return rc;
2043
2044         if (!BNXT_SINGLE_PF(bp) || BNXT_VF(bp)) {
2045                 PMD_DRV_LOG(ERR, "Flow Control Settings cannot be modified\n");
2046                 return -ENOTSUP;
2047         }
2048
2049         switch (fc_conf->mode) {
2050         case RTE_FC_NONE:
2051                 bp->link_info->auto_pause = 0;
2052                 bp->link_info->force_pause = 0;
2053                 break;
2054         case RTE_FC_RX_PAUSE:
2055                 if (fc_conf->autoneg) {
2056                         bp->link_info->auto_pause =
2057                                         HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_RX;
2058                         bp->link_info->force_pause = 0;
2059                 } else {
2060                         bp->link_info->auto_pause = 0;
2061                         bp->link_info->force_pause =
2062                                         HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_RX;
2063                 }
2064                 break;
2065         case RTE_FC_TX_PAUSE:
2066                 if (fc_conf->autoneg) {
2067                         bp->link_info->auto_pause =
2068                                         HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_TX;
2069                         bp->link_info->force_pause = 0;
2070                 } else {
2071                         bp->link_info->auto_pause = 0;
2072                         bp->link_info->force_pause =
2073                                         HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_TX;
2074                 }
2075                 break;
2076         case RTE_FC_FULL:
2077                 if (fc_conf->autoneg) {
2078                         bp->link_info->auto_pause =
2079                                         HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_TX |
2080                                         HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_RX;
2081                         bp->link_info->force_pause = 0;
2082                 } else {
2083                         bp->link_info->auto_pause = 0;
2084                         bp->link_info->force_pause =
2085                                         HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_TX |
2086                                         HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_RX;
2087                 }
2088                 break;
2089         }
2090         return bnxt_set_hwrm_link_config(bp, true);
2091 }
2092
2093 /* Add UDP tunneling port */
2094 static int
2095 bnxt_udp_tunnel_port_add_op(struct rte_eth_dev *eth_dev,
2096                          struct rte_eth_udp_tunnel *udp_tunnel)
2097 {
2098         struct bnxt *bp = eth_dev->data->dev_private;
2099         uint16_t tunnel_type = 0;
2100         int rc = 0;
2101
2102         rc = is_bnxt_in_error(bp);
2103         if (rc)
2104                 return rc;
2105
2106         switch (udp_tunnel->prot_type) {
2107         case RTE_TUNNEL_TYPE_VXLAN:
2108                 if (bp->vxlan_port_cnt) {
2109                         PMD_DRV_LOG(ERR, "Tunnel Port %d already programmed\n",
2110                                 udp_tunnel->udp_port);
2111                         if (bp->vxlan_port != udp_tunnel->udp_port) {
2112                                 PMD_DRV_LOG(ERR, "Only one port allowed\n");
2113                                 return -ENOSPC;
2114                         }
2115                         bp->vxlan_port_cnt++;
2116                         return 0;
2117                 }
2118                 tunnel_type =
2119                         HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_VXLAN;
2120                 bp->vxlan_port_cnt++;
2121                 break;
2122         case RTE_TUNNEL_TYPE_GENEVE:
2123                 if (bp->geneve_port_cnt) {
2124                         PMD_DRV_LOG(ERR, "Tunnel Port %d already programmed\n",
2125                                 udp_tunnel->udp_port);
2126                         if (bp->geneve_port != udp_tunnel->udp_port) {
2127                                 PMD_DRV_LOG(ERR, "Only one port allowed\n");
2128                                 return -ENOSPC;
2129                         }
2130                         bp->geneve_port_cnt++;
2131                         return 0;
2132                 }
2133                 tunnel_type =
2134                         HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_GENEVE;
2135                 bp->geneve_port_cnt++;
2136                 break;
2137         default:
2138                 PMD_DRV_LOG(ERR, "Tunnel type is not supported\n");
2139                 return -ENOTSUP;
2140         }
2141         rc = bnxt_hwrm_tunnel_dst_port_alloc(bp, udp_tunnel->udp_port,
2142                                              tunnel_type);
2143         return rc;
2144 }
2145
2146 static int
2147 bnxt_udp_tunnel_port_del_op(struct rte_eth_dev *eth_dev,
2148                          struct rte_eth_udp_tunnel *udp_tunnel)
2149 {
2150         struct bnxt *bp = eth_dev->data->dev_private;
2151         uint16_t tunnel_type = 0;
2152         uint16_t port = 0;
2153         int rc = 0;
2154
2155         rc = is_bnxt_in_error(bp);
2156         if (rc)
2157                 return rc;
2158
2159         switch (udp_tunnel->prot_type) {
2160         case RTE_TUNNEL_TYPE_VXLAN:
2161                 if (!bp->vxlan_port_cnt) {
2162                         PMD_DRV_LOG(ERR, "No Tunnel port configured yet\n");
2163                         return -EINVAL;
2164                 }
2165                 if (bp->vxlan_port != udp_tunnel->udp_port) {
2166                         PMD_DRV_LOG(ERR, "Req Port: %d. Configured port: %d\n",
2167                                 udp_tunnel->udp_port, bp->vxlan_port);
2168                         return -EINVAL;
2169                 }
2170                 if (--bp->vxlan_port_cnt)
2171                         return 0;
2172
2173                 tunnel_type =
2174                         HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN;
2175                 port = bp->vxlan_fw_dst_port_id;
2176                 break;
2177         case RTE_TUNNEL_TYPE_GENEVE:
2178                 if (!bp->geneve_port_cnt) {
2179                         PMD_DRV_LOG(ERR, "No Tunnel port configured yet\n");
2180                         return -EINVAL;
2181                 }
2182                 if (bp->geneve_port != udp_tunnel->udp_port) {
2183                         PMD_DRV_LOG(ERR, "Req Port: %d. Configured port: %d\n",
2184                                 udp_tunnel->udp_port, bp->geneve_port);
2185                         return -EINVAL;
2186                 }
2187                 if (--bp->geneve_port_cnt)
2188                         return 0;
2189
2190                 tunnel_type =
2191                         HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_GENEVE;
2192                 port = bp->geneve_fw_dst_port_id;
2193                 break;
2194         default:
2195                 PMD_DRV_LOG(ERR, "Tunnel type is not supported\n");
2196                 return -ENOTSUP;
2197         }
2198
2199         rc = bnxt_hwrm_tunnel_dst_port_free(bp, port, tunnel_type);
2200         return rc;
2201 }
2202
2203 static int bnxt_del_vlan_filter(struct bnxt *bp, uint16_t vlan_id)
2204 {
2205         struct bnxt_filter_info *filter;
2206         struct bnxt_vnic_info *vnic;
2207         int rc = 0;
2208         uint32_t chk = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN;
2209
2210         vnic = BNXT_GET_DEFAULT_VNIC(bp);
2211         filter = STAILQ_FIRST(&vnic->filter);
2212         while (filter) {
2213                 /* Search for this matching MAC+VLAN filter */
2214                 if (bnxt_vlan_filter_exists(bp, filter, chk, vlan_id)) {
2215                         /* Delete the filter */
2216                         rc = bnxt_hwrm_clear_l2_filter(bp, filter);
2217                         if (rc)
2218                                 return rc;
2219                         STAILQ_REMOVE(&vnic->filter, filter,
2220                                       bnxt_filter_info, next);
2221                         bnxt_free_filter(bp, filter);
2222                         PMD_DRV_LOG(INFO,
2223                                     "Deleted vlan filter for %d\n",
2224                                     vlan_id);
2225                         return 0;
2226                 }
2227                 filter = STAILQ_NEXT(filter, next);
2228         }
2229         return -ENOENT;
2230 }
2231
2232 static int bnxt_add_vlan_filter(struct bnxt *bp, uint16_t vlan_id)
2233 {
2234         struct bnxt_filter_info *filter;
2235         struct bnxt_vnic_info *vnic;
2236         int rc = 0;
2237         uint32_t en = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN |
2238                 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN_MASK;
2239         uint32_t chk = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN;
2240
2241         /* Implementation notes on the use of VNIC in this command:
2242          *
2243          * By default, these filters belong to default vnic for the function.
2244          * Once these filters are set up, only destination VNIC can be modified.
2245          * If the destination VNIC is not specified in this command,
2246          * then the HWRM shall only create an l2 context id.
2247          */
2248
2249         vnic = BNXT_GET_DEFAULT_VNIC(bp);
2250         filter = STAILQ_FIRST(&vnic->filter);
2251         /* Check if the VLAN has already been added */
2252         while (filter) {
2253                 if (bnxt_vlan_filter_exists(bp, filter, chk, vlan_id))
2254                         return -EEXIST;
2255
2256                 filter = STAILQ_NEXT(filter, next);
2257         }
2258
2259         /* No match found. Alloc a fresh filter and issue the L2_FILTER_ALLOC
2260          * command to create MAC+VLAN filter with the right flags, enables set.
2261          */
2262         filter = bnxt_alloc_filter(bp);
2263         if (!filter) {
2264                 PMD_DRV_LOG(ERR,
2265                             "MAC/VLAN filter alloc failed\n");
2266                 return -ENOMEM;
2267         }
2268         /* MAC + VLAN ID filter */
2269         /* If l2_ivlan == 0 and l2_ivlan_mask != 0, only
2270          * untagged packets are received
2271          *
2272          * If l2_ivlan != 0 and l2_ivlan_mask != 0, untagged
2273          * packets and only the programmed vlan's packets are received
2274          */
2275         filter->l2_ivlan = vlan_id;
2276         filter->l2_ivlan_mask = 0x0FFF;
2277         filter->enables |= en;
2278         filter->flags |= HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_OUTERMOST;
2279
2280         rc = bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id, filter);
2281         if (rc) {
2282                 /* Free the newly allocated filter as we were
2283                  * not able to create the filter in hardware.
2284                  */
2285                 bnxt_free_filter(bp, filter);
2286                 return rc;
2287         }
2288
2289         filter->mac_index = 0;
2290         /* Add this new filter to the list */
2291         if (vlan_id == 0)
2292                 STAILQ_INSERT_HEAD(&vnic->filter, filter, next);
2293         else
2294                 STAILQ_INSERT_TAIL(&vnic->filter, filter, next);
2295
2296         PMD_DRV_LOG(INFO,
2297                     "Added Vlan filter for %d\n", vlan_id);
2298         return rc;
2299 }
2300
2301 static int bnxt_vlan_filter_set_op(struct rte_eth_dev *eth_dev,
2302                 uint16_t vlan_id, int on)
2303 {
2304         struct bnxt *bp = eth_dev->data->dev_private;
2305         int rc;
2306
2307         rc = is_bnxt_in_error(bp);
2308         if (rc)
2309                 return rc;
2310
2311         if (!eth_dev->data->dev_started) {
2312                 PMD_DRV_LOG(ERR, "port must be started before setting vlan\n");
2313                 return -EINVAL;
2314         }
2315
2316         /* These operations apply to ALL existing MAC/VLAN filters */
2317         if (on)
2318                 return bnxt_add_vlan_filter(bp, vlan_id);
2319         else
2320                 return bnxt_del_vlan_filter(bp, vlan_id);
2321 }
2322
2323 static int bnxt_del_dflt_mac_filter(struct bnxt *bp,
2324                                     struct bnxt_vnic_info *vnic)
2325 {
2326         struct bnxt_filter_info *filter;
2327         int rc;
2328
2329         filter = STAILQ_FIRST(&vnic->filter);
2330         while (filter) {
2331                 if (filter->mac_index == 0 &&
2332                     !memcmp(filter->l2_addr, bp->mac_addr,
2333                             RTE_ETHER_ADDR_LEN)) {
2334                         rc = bnxt_hwrm_clear_l2_filter(bp, filter);
2335                         if (!rc) {
2336                                 STAILQ_REMOVE(&vnic->filter, filter,
2337                                               bnxt_filter_info, next);
2338                                 bnxt_free_filter(bp, filter);
2339                         }
2340                         return rc;
2341                 }
2342                 filter = STAILQ_NEXT(filter, next);
2343         }
2344         return 0;
2345 }
2346
2347 static int
2348 bnxt_config_vlan_hw_filter(struct bnxt *bp, uint64_t rx_offloads)
2349 {
2350         struct bnxt_vnic_info *vnic;
2351         unsigned int i;
2352         int rc;
2353
2354         vnic = BNXT_GET_DEFAULT_VNIC(bp);
2355         if (!(rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER)) {
2356                 /* Remove any VLAN filters programmed */
2357                 for (i = 0; i < RTE_ETHER_MAX_VLAN_ID; i++)
2358                         bnxt_del_vlan_filter(bp, i);
2359
2360                 rc = bnxt_add_mac_filter(bp, vnic, NULL, 0, 0);
2361                 if (rc)
2362                         return rc;
2363         } else {
2364                 /* Default filter will allow packets that match the
2365                  * dest mac. So, it has to be deleted, otherwise, we
2366                  * will endup receiving vlan packets for which the
2367                  * filter is not programmed, when hw-vlan-filter
2368                  * configuration is ON
2369                  */
2370                 bnxt_del_dflt_mac_filter(bp, vnic);
2371                 /* This filter will allow only untagged packets */
2372                 bnxt_add_vlan_filter(bp, 0);
2373         }
2374         PMD_DRV_LOG(DEBUG, "VLAN Filtering: %d\n",
2375                     !!(rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER));
2376
2377         return 0;
2378 }
2379
2380 static int bnxt_free_one_vnic(struct bnxt *bp, uint16_t vnic_id)
2381 {
2382         struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id];
2383         unsigned int i;
2384         int rc;
2385
2386         /* Destroy vnic filters and vnic */
2387         if (bp->eth_dev->data->dev_conf.rxmode.offloads &
2388             DEV_RX_OFFLOAD_VLAN_FILTER) {
2389                 for (i = 0; i < RTE_ETHER_MAX_VLAN_ID; i++)
2390                         bnxt_del_vlan_filter(bp, i);
2391         }
2392         bnxt_del_dflt_mac_filter(bp, vnic);
2393
2394         rc = bnxt_hwrm_vnic_free(bp, vnic);
2395         if (rc)
2396                 return rc;
2397
2398         rte_free(vnic->fw_grp_ids);
2399         vnic->fw_grp_ids = NULL;
2400
2401         vnic->rx_queue_cnt = 0;
2402
2403         return 0;
2404 }
2405
2406 static int
2407 bnxt_config_vlan_hw_stripping(struct bnxt *bp, uint64_t rx_offloads)
2408 {
2409         struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp);
2410         int rc;
2411
2412         /* Destroy, recreate and reconfigure the default vnic */
2413         rc = bnxt_free_one_vnic(bp, 0);
2414         if (rc)
2415                 return rc;
2416
2417         /* default vnic 0 */
2418         rc = bnxt_setup_one_vnic(bp, 0);
2419         if (rc)
2420                 return rc;
2421
2422         if (bp->eth_dev->data->dev_conf.rxmode.offloads &
2423             DEV_RX_OFFLOAD_VLAN_FILTER) {
2424                 rc = bnxt_add_vlan_filter(bp, 0);
2425                 if (rc)
2426                         return rc;
2427                 rc = bnxt_restore_vlan_filters(bp);
2428                 if (rc)
2429                         return rc;
2430         } else {
2431                 rc = bnxt_add_mac_filter(bp, vnic, NULL, 0, 0);
2432                 if (rc)
2433                         return rc;
2434         }
2435
2436         rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
2437         if (rc)
2438                 return rc;
2439
2440         PMD_DRV_LOG(DEBUG, "VLAN Strip Offload: %d\n",
2441                     !!(rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP));
2442
2443         return rc;
2444 }
2445
2446 static int
2447 bnxt_vlan_offload_set_op(struct rte_eth_dev *dev, int mask)
2448 {
2449         uint64_t rx_offloads = dev->data->dev_conf.rxmode.offloads;
2450         struct bnxt *bp = dev->data->dev_private;
2451         int rc;
2452
2453         rc = is_bnxt_in_error(bp);
2454         if (rc)
2455                 return rc;
2456
2457         /* Filter settings will get applied when port is started */
2458         if (!dev->data->dev_started)
2459                 return 0;
2460
2461         if (mask & ETH_VLAN_FILTER_MASK) {
2462                 /* Enable or disable VLAN filtering */
2463                 rc = bnxt_config_vlan_hw_filter(bp, rx_offloads);
2464                 if (rc)
2465                         return rc;
2466         }
2467
2468         if (mask & ETH_VLAN_STRIP_MASK) {
2469                 /* Enable or disable VLAN stripping */
2470                 rc = bnxt_config_vlan_hw_stripping(bp, rx_offloads);
2471                 if (rc)
2472                         return rc;
2473         }
2474
2475         if (mask & ETH_VLAN_EXTEND_MASK) {
2476                 if (rx_offloads & DEV_RX_OFFLOAD_VLAN_EXTEND)
2477                         PMD_DRV_LOG(DEBUG, "Extend VLAN supported\n");
2478                 else
2479                         PMD_DRV_LOG(INFO, "Extend VLAN unsupported\n");
2480         }
2481
2482         return 0;
2483 }
2484
2485 static int
2486 bnxt_vlan_tpid_set_op(struct rte_eth_dev *dev, enum rte_vlan_type vlan_type,
2487                       uint16_t tpid)
2488 {
2489         struct bnxt *bp = dev->data->dev_private;
2490         int qinq = dev->data->dev_conf.rxmode.offloads &
2491                    DEV_RX_OFFLOAD_VLAN_EXTEND;
2492
2493         if (vlan_type != ETH_VLAN_TYPE_INNER &&
2494             vlan_type != ETH_VLAN_TYPE_OUTER) {
2495                 PMD_DRV_LOG(ERR,
2496                             "Unsupported vlan type.");
2497                 return -EINVAL;
2498         }
2499         if (!qinq) {
2500                 PMD_DRV_LOG(ERR,
2501                             "QinQ not enabled. Needs to be ON as we can "
2502                             "accelerate only outer vlan\n");
2503                 return -EINVAL;
2504         }
2505
2506         if (vlan_type == ETH_VLAN_TYPE_OUTER) {
2507                 switch (tpid) {
2508                 case RTE_ETHER_TYPE_QINQ:
2509                         bp->outer_tpid_bd =
2510                                 TX_BD_LONG_CFA_META_VLAN_TPID_TPID88A8;
2511                                 break;
2512                 case RTE_ETHER_TYPE_VLAN:
2513                         bp->outer_tpid_bd =
2514                                 TX_BD_LONG_CFA_META_VLAN_TPID_TPID8100;
2515                                 break;
2516                 case RTE_ETHER_TYPE_QINQ1:
2517                         bp->outer_tpid_bd =
2518                                 TX_BD_LONG_CFA_META_VLAN_TPID_TPID9100;
2519                                 break;
2520                 case RTE_ETHER_TYPE_QINQ2:
2521                         bp->outer_tpid_bd =
2522                                 TX_BD_LONG_CFA_META_VLAN_TPID_TPID9200;
2523                                 break;
2524                 case RTE_ETHER_TYPE_QINQ3:
2525                         bp->outer_tpid_bd =
2526                                  TX_BD_LONG_CFA_META_VLAN_TPID_TPID9300;
2527                                 break;
2528                 default:
2529                         PMD_DRV_LOG(ERR, "Invalid TPID: %x\n", tpid);
2530                         return -EINVAL;
2531                 }
2532                 bp->outer_tpid_bd |= tpid;
2533                 PMD_DRV_LOG(INFO, "outer_tpid_bd = %x\n", bp->outer_tpid_bd);
2534         } else if (vlan_type == ETH_VLAN_TYPE_INNER) {
2535                 PMD_DRV_LOG(ERR,
2536                             "Can accelerate only outer vlan in QinQ\n");
2537                 return -EINVAL;
2538         }
2539
2540         return 0;
2541 }
2542
2543 static int
2544 bnxt_set_default_mac_addr_op(struct rte_eth_dev *dev,
2545                              struct rte_ether_addr *addr)
2546 {
2547         struct bnxt *bp = dev->data->dev_private;
2548         /* Default Filter is tied to VNIC 0 */
2549         struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp);
2550         int rc;
2551
2552         rc = is_bnxt_in_error(bp);
2553         if (rc)
2554                 return rc;
2555
2556         if (BNXT_VF(bp) && !BNXT_VF_IS_TRUSTED(bp))
2557                 return -EPERM;
2558
2559         if (rte_is_zero_ether_addr(addr))
2560                 return -EINVAL;
2561
2562         /* Filter settings will get applied when port is started */
2563         if (!dev->data->dev_started)
2564                 return 0;
2565
2566         /* Check if the requested MAC is already added */
2567         if (memcmp(addr, bp->mac_addr, RTE_ETHER_ADDR_LEN) == 0)
2568                 return 0;
2569
2570         /* Destroy filter and re-create it */
2571         bnxt_del_dflt_mac_filter(bp, vnic);
2572
2573         memcpy(bp->mac_addr, addr, RTE_ETHER_ADDR_LEN);
2574         if (dev->data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_VLAN_FILTER) {
2575                 /* This filter will allow only untagged packets */
2576                 rc = bnxt_add_vlan_filter(bp, 0);
2577         } else {
2578                 rc = bnxt_add_mac_filter(bp, vnic, addr, 0, 0);
2579         }
2580
2581         PMD_DRV_LOG(DEBUG, "Set MAC addr\n");
2582         return rc;
2583 }
2584
2585 static int
2586 bnxt_dev_set_mc_addr_list_op(struct rte_eth_dev *eth_dev,
2587                           struct rte_ether_addr *mc_addr_set,
2588                           uint32_t nb_mc_addr)
2589 {
2590         struct bnxt *bp = eth_dev->data->dev_private;
2591         char *mc_addr_list = (char *)mc_addr_set;
2592         struct bnxt_vnic_info *vnic;
2593         uint32_t off = 0, i = 0;
2594         int rc;
2595
2596         rc = is_bnxt_in_error(bp);
2597         if (rc)
2598                 return rc;
2599
2600         vnic = BNXT_GET_DEFAULT_VNIC(bp);
2601
2602         if (nb_mc_addr > BNXT_MAX_MC_ADDRS) {
2603                 vnic->flags |= BNXT_VNIC_INFO_ALLMULTI;
2604                 goto allmulti;
2605         }
2606
2607         /* TODO Check for Duplicate mcast addresses */
2608         vnic->flags &= ~BNXT_VNIC_INFO_ALLMULTI;
2609         for (i = 0; i < nb_mc_addr; i++) {
2610                 memcpy(vnic->mc_list + off, &mc_addr_list[i],
2611                         RTE_ETHER_ADDR_LEN);
2612                 off += RTE_ETHER_ADDR_LEN;
2613         }
2614
2615         vnic->mc_addr_cnt = i;
2616         if (vnic->mc_addr_cnt)
2617                 vnic->flags |= BNXT_VNIC_INFO_MCAST;
2618         else
2619                 vnic->flags &= ~BNXT_VNIC_INFO_MCAST;
2620
2621 allmulti:
2622         return bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
2623 }
2624
2625 static int
2626 bnxt_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size)
2627 {
2628         struct bnxt *bp = dev->data->dev_private;
2629         uint8_t fw_major = (bp->fw_ver >> 24) & 0xff;
2630         uint8_t fw_minor = (bp->fw_ver >> 16) & 0xff;
2631         uint8_t fw_updt = (bp->fw_ver >> 8) & 0xff;
2632         uint8_t fw_rsvd = bp->fw_ver & 0xff;
2633         int ret;
2634
2635         ret = snprintf(fw_version, fw_size, "%d.%d.%d.%d",
2636                         fw_major, fw_minor, fw_updt, fw_rsvd);
2637
2638         ret += 1; /* add the size of '\0' */
2639         if (fw_size < (uint32_t)ret)
2640                 return ret;
2641         else
2642                 return 0;
2643 }
2644
2645 static void
2646 bnxt_rxq_info_get_op(struct rte_eth_dev *dev, uint16_t queue_id,
2647         struct rte_eth_rxq_info *qinfo)
2648 {
2649         struct bnxt *bp = dev->data->dev_private;
2650         struct bnxt_rx_queue *rxq;
2651
2652         if (is_bnxt_in_error(bp))
2653                 return;
2654
2655         rxq = dev->data->rx_queues[queue_id];
2656
2657         qinfo->mp = rxq->mb_pool;
2658         qinfo->scattered_rx = dev->data->scattered_rx;
2659         qinfo->nb_desc = rxq->nb_rx_desc;
2660
2661         qinfo->conf.rx_free_thresh = rxq->rx_free_thresh;
2662         qinfo->conf.rx_drop_en = rxq->drop_en;
2663         qinfo->conf.rx_deferred_start = rxq->rx_deferred_start;
2664         qinfo->conf.offloads = dev->data->dev_conf.rxmode.offloads;
2665 }
2666
2667 static void
2668 bnxt_txq_info_get_op(struct rte_eth_dev *dev, uint16_t queue_id,
2669         struct rte_eth_txq_info *qinfo)
2670 {
2671         struct bnxt *bp = dev->data->dev_private;
2672         struct bnxt_tx_queue *txq;
2673
2674         if (is_bnxt_in_error(bp))
2675                 return;
2676
2677         txq = dev->data->tx_queues[queue_id];
2678
2679         qinfo->nb_desc = txq->nb_tx_desc;
2680
2681         qinfo->conf.tx_thresh.pthresh = txq->pthresh;
2682         qinfo->conf.tx_thresh.hthresh = txq->hthresh;
2683         qinfo->conf.tx_thresh.wthresh = txq->wthresh;
2684
2685         qinfo->conf.tx_free_thresh = txq->tx_free_thresh;
2686         qinfo->conf.tx_rs_thresh = 0;
2687         qinfo->conf.tx_deferred_start = txq->tx_deferred_start;
2688         qinfo->conf.offloads = txq->offloads;
2689 }
2690
2691 static const struct {
2692         eth_rx_burst_t pkt_burst;
2693         const char *info;
2694 } bnxt_rx_burst_info[] = {
2695         {bnxt_recv_pkts,        "Scalar"},
2696 #if defined(RTE_ARCH_X86)
2697         {bnxt_recv_pkts_vec,    "Vector SSE"},
2698 #elif defined(RTE_ARCH_ARM64)
2699         {bnxt_recv_pkts_vec,    "Vector Neon"},
2700 #endif
2701 };
2702
2703 static int
2704 bnxt_rx_burst_mode_get(struct rte_eth_dev *dev, __rte_unused uint16_t queue_id,
2705                        struct rte_eth_burst_mode *mode)
2706 {
2707         eth_rx_burst_t pkt_burst = dev->rx_pkt_burst;
2708         size_t i;
2709
2710         for (i = 0; i < RTE_DIM(bnxt_rx_burst_info); i++) {
2711                 if (pkt_burst == bnxt_rx_burst_info[i].pkt_burst) {
2712                         snprintf(mode->info, sizeof(mode->info), "%s",
2713                                  bnxt_rx_burst_info[i].info);
2714                         return 0;
2715                 }
2716         }
2717
2718         return -EINVAL;
2719 }
2720
2721 static const struct {
2722         eth_tx_burst_t pkt_burst;
2723         const char *info;
2724 } bnxt_tx_burst_info[] = {
2725         {bnxt_xmit_pkts,        "Scalar"},
2726 #if defined(RTE_ARCH_X86)
2727         {bnxt_xmit_pkts_vec,    "Vector SSE"},
2728 #elif defined(RTE_ARCH_ARM64)
2729         {bnxt_xmit_pkts_vec,    "Vector Neon"},
2730 #endif
2731 };
2732
2733 static int
2734 bnxt_tx_burst_mode_get(struct rte_eth_dev *dev, __rte_unused uint16_t queue_id,
2735                        struct rte_eth_burst_mode *mode)
2736 {
2737         eth_tx_burst_t pkt_burst = dev->tx_pkt_burst;
2738         size_t i;
2739
2740         for (i = 0; i < RTE_DIM(bnxt_tx_burst_info); i++) {
2741                 if (pkt_burst == bnxt_tx_burst_info[i].pkt_burst) {
2742                         snprintf(mode->info, sizeof(mode->info), "%s",
2743                                  bnxt_tx_burst_info[i].info);
2744                         return 0;
2745                 }
2746         }
2747
2748         return -EINVAL;
2749 }
2750
2751 int bnxt_mtu_set_op(struct rte_eth_dev *eth_dev, uint16_t new_mtu)
2752 {
2753         struct bnxt *bp = eth_dev->data->dev_private;
2754         uint32_t new_pkt_size;
2755         uint32_t rc = 0;
2756         uint32_t i;
2757
2758         rc = is_bnxt_in_error(bp);
2759         if (rc)
2760                 return rc;
2761
2762         /* Exit if receive queues are not configured yet */
2763         if (!eth_dev->data->nb_rx_queues)
2764                 return rc;
2765
2766         new_pkt_size = new_mtu + RTE_ETHER_HDR_LEN + RTE_ETHER_CRC_LEN +
2767                        VLAN_TAG_SIZE * BNXT_NUM_VLANS;
2768
2769         /*
2770          * Disallow any MTU change that would require scattered receive support
2771          * if it is not already enabled.
2772          */
2773         if (eth_dev->data->dev_started &&
2774             !eth_dev->data->scattered_rx &&
2775             (new_pkt_size >
2776              eth_dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM)) {
2777                 PMD_DRV_LOG(ERR,
2778                             "MTU change would require scattered rx support. ");
2779                 PMD_DRV_LOG(ERR, "Stop port before changing MTU.\n");
2780                 return -EINVAL;
2781         }
2782
2783         if (new_mtu > RTE_ETHER_MTU) {
2784                 bp->flags |= BNXT_FLAG_JUMBO;
2785                 bp->eth_dev->data->dev_conf.rxmode.offloads |=
2786                         DEV_RX_OFFLOAD_JUMBO_FRAME;
2787         } else {
2788                 bp->eth_dev->data->dev_conf.rxmode.offloads &=
2789                         ~DEV_RX_OFFLOAD_JUMBO_FRAME;
2790                 bp->flags &= ~BNXT_FLAG_JUMBO;
2791         }
2792
2793         /* Is there a change in mtu setting? */
2794         if (eth_dev->data->dev_conf.rxmode.max_rx_pkt_len == new_pkt_size)
2795                 return rc;
2796
2797         for (i = 0; i < bp->nr_vnics; i++) {
2798                 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
2799                 uint16_t size = 0;
2800
2801                 vnic->mru = BNXT_VNIC_MRU(new_mtu);
2802                 rc = bnxt_hwrm_vnic_cfg(bp, vnic);
2803                 if (rc)
2804                         break;
2805
2806                 size = rte_pktmbuf_data_room_size(bp->rx_queues[0]->mb_pool);
2807                 size -= RTE_PKTMBUF_HEADROOM;
2808
2809                 if (size < new_mtu) {
2810                         rc = bnxt_hwrm_vnic_plcmode_cfg(bp, vnic);
2811                         if (rc)
2812                                 return rc;
2813                 }
2814         }
2815
2816         if (!rc)
2817                 eth_dev->data->dev_conf.rxmode.max_rx_pkt_len = new_pkt_size;
2818
2819         PMD_DRV_LOG(INFO, "New MTU is %d\n", new_mtu);
2820
2821         return rc;
2822 }
2823
2824 static int
2825 bnxt_vlan_pvid_set_op(struct rte_eth_dev *dev, uint16_t pvid, int on)
2826 {
2827         struct bnxt *bp = dev->data->dev_private;
2828         uint16_t vlan = bp->vlan;
2829         int rc;
2830
2831         rc = is_bnxt_in_error(bp);
2832         if (rc)
2833                 return rc;
2834
2835         if (!BNXT_SINGLE_PF(bp) || BNXT_VF(bp)) {
2836                 PMD_DRV_LOG(ERR,
2837                         "PVID cannot be modified for this function\n");
2838                 return -ENOTSUP;
2839         }
2840         bp->vlan = on ? pvid : 0;
2841
2842         rc = bnxt_hwrm_set_default_vlan(bp, 0, 0);
2843         if (rc)
2844                 bp->vlan = vlan;
2845         return rc;
2846 }
2847
2848 static int
2849 bnxt_dev_led_on_op(struct rte_eth_dev *dev)
2850 {
2851         struct bnxt *bp = dev->data->dev_private;
2852         int rc;
2853
2854         rc = is_bnxt_in_error(bp);
2855         if (rc)
2856                 return rc;
2857
2858         return bnxt_hwrm_port_led_cfg(bp, true);
2859 }
2860
2861 static int
2862 bnxt_dev_led_off_op(struct rte_eth_dev *dev)
2863 {
2864         struct bnxt *bp = dev->data->dev_private;
2865         int rc;
2866
2867         rc = is_bnxt_in_error(bp);
2868         if (rc)
2869                 return rc;
2870
2871         return bnxt_hwrm_port_led_cfg(bp, false);
2872 }
2873
2874 static uint32_t
2875 bnxt_rx_queue_count_op(struct rte_eth_dev *dev, uint16_t rx_queue_id)
2876 {
2877         struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
2878         uint32_t desc = 0, raw_cons = 0, cons;
2879         struct bnxt_cp_ring_info *cpr;
2880         struct bnxt_rx_queue *rxq;
2881         struct rx_pkt_cmpl *rxcmp;
2882         int rc;
2883
2884         rc = is_bnxt_in_error(bp);
2885         if (rc)
2886                 return rc;
2887
2888         rxq = dev->data->rx_queues[rx_queue_id];
2889         cpr = rxq->cp_ring;
2890         raw_cons = cpr->cp_raw_cons;
2891
2892         while (1) {
2893                 cons = RING_CMP(cpr->cp_ring_struct, raw_cons);
2894                 rte_prefetch0(&cpr->cp_desc_ring[cons]);
2895                 rxcmp = (struct rx_pkt_cmpl *)&cpr->cp_desc_ring[cons];
2896
2897                 if (!CMP_VALID(rxcmp, raw_cons, cpr->cp_ring_struct)) {
2898                         break;
2899                 } else {
2900                         raw_cons++;
2901                         desc++;
2902                 }
2903         }
2904
2905         return desc;
2906 }
2907
2908 static int
2909 bnxt_rx_descriptor_status_op(void *rx_queue, uint16_t offset)
2910 {
2911         struct bnxt_rx_queue *rxq = (struct bnxt_rx_queue *)rx_queue;
2912         struct bnxt_rx_ring_info *rxr;
2913         struct bnxt_cp_ring_info *cpr;
2914         struct rte_mbuf *rx_buf;
2915         struct rx_pkt_cmpl *rxcmp;
2916         uint32_t cons, cp_cons;
2917         int rc;
2918
2919         if (!rxq)
2920                 return -EINVAL;
2921
2922         rc = is_bnxt_in_error(rxq->bp);
2923         if (rc)
2924                 return rc;
2925
2926         cpr = rxq->cp_ring;
2927         rxr = rxq->rx_ring;
2928
2929         if (offset >= rxq->nb_rx_desc)
2930                 return -EINVAL;
2931
2932         cons = RING_CMP(cpr->cp_ring_struct, offset);
2933         cp_cons = cpr->cp_raw_cons;
2934         rxcmp = (struct rx_pkt_cmpl *)&cpr->cp_desc_ring[cons];
2935
2936         if (cons > cp_cons) {
2937                 if (CMPL_VALID(rxcmp, cpr->valid))
2938                         return RTE_ETH_RX_DESC_DONE;
2939         } else {
2940                 if (CMPL_VALID(rxcmp, !cpr->valid))
2941                         return RTE_ETH_RX_DESC_DONE;
2942         }
2943         rx_buf = rxr->rx_buf_ring[cons];
2944         if (rx_buf == NULL || rx_buf == &rxq->fake_mbuf)
2945                 return RTE_ETH_RX_DESC_UNAVAIL;
2946
2947
2948         return RTE_ETH_RX_DESC_AVAIL;
2949 }
2950
2951 static int
2952 bnxt_tx_descriptor_status_op(void *tx_queue, uint16_t offset)
2953 {
2954         struct bnxt_tx_queue *txq = (struct bnxt_tx_queue *)tx_queue;
2955         struct bnxt_tx_ring_info *txr;
2956         struct bnxt_cp_ring_info *cpr;
2957         struct bnxt_sw_tx_bd *tx_buf;
2958         struct tx_pkt_cmpl *txcmp;
2959         uint32_t cons, cp_cons;
2960         int rc;
2961
2962         if (!txq)
2963                 return -EINVAL;
2964
2965         rc = is_bnxt_in_error(txq->bp);
2966         if (rc)
2967                 return rc;
2968
2969         cpr = txq->cp_ring;
2970         txr = txq->tx_ring;
2971
2972         if (offset >= txq->nb_tx_desc)
2973                 return -EINVAL;
2974
2975         cons = RING_CMP(cpr->cp_ring_struct, offset);
2976         txcmp = (struct tx_pkt_cmpl *)&cpr->cp_desc_ring[cons];
2977         cp_cons = cpr->cp_raw_cons;
2978
2979         if (cons > cp_cons) {
2980                 if (CMPL_VALID(txcmp, cpr->valid))
2981                         return RTE_ETH_TX_DESC_UNAVAIL;
2982         } else {
2983                 if (CMPL_VALID(txcmp, !cpr->valid))
2984                         return RTE_ETH_TX_DESC_UNAVAIL;
2985         }
2986         tx_buf = &txr->tx_buf_ring[cons];
2987         if (tx_buf->mbuf == NULL)
2988                 return RTE_ETH_TX_DESC_DONE;
2989
2990         return RTE_ETH_TX_DESC_FULL;
2991 }
2992
2993 static struct bnxt_filter_info *
2994 bnxt_match_and_validate_ether_filter(struct bnxt *bp,
2995                                 struct rte_eth_ethertype_filter *efilter,
2996                                 struct bnxt_vnic_info *vnic0,
2997                                 struct bnxt_vnic_info *vnic,
2998                                 int *ret)
2999 {
3000         struct bnxt_filter_info *mfilter = NULL;
3001         int match = 0;
3002         *ret = 0;
3003
3004         if (efilter->ether_type == RTE_ETHER_TYPE_IPV4 ||
3005                 efilter->ether_type == RTE_ETHER_TYPE_IPV6) {
3006                 PMD_DRV_LOG(ERR, "invalid ether_type(0x%04x) in"
3007                         " ethertype filter.", efilter->ether_type);
3008                 *ret = -EINVAL;
3009                 goto exit;
3010         }
3011         if (efilter->queue >= bp->rx_nr_rings) {
3012                 PMD_DRV_LOG(ERR, "Invalid queue %d\n", efilter->queue);
3013                 *ret = -EINVAL;
3014                 goto exit;
3015         }
3016
3017         vnic0 = BNXT_GET_DEFAULT_VNIC(bp);
3018         vnic = &bp->vnic_info[efilter->queue];
3019         if (vnic == NULL) {
3020                 PMD_DRV_LOG(ERR, "Invalid queue %d\n", efilter->queue);
3021                 *ret = -EINVAL;
3022                 goto exit;
3023         }
3024
3025         if (efilter->flags & RTE_ETHTYPE_FLAGS_DROP) {
3026                 STAILQ_FOREACH(mfilter, &vnic0->filter, next) {
3027                         if ((!memcmp(efilter->mac_addr.addr_bytes,
3028                                      mfilter->l2_addr, RTE_ETHER_ADDR_LEN) &&
3029                              mfilter->flags ==
3030                              HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_DROP &&
3031                              mfilter->ethertype == efilter->ether_type)) {
3032                                 match = 1;
3033                                 break;
3034                         }
3035                 }
3036         } else {
3037                 STAILQ_FOREACH(mfilter, &vnic->filter, next)
3038                         if ((!memcmp(efilter->mac_addr.addr_bytes,
3039                                      mfilter->l2_addr, RTE_ETHER_ADDR_LEN) &&
3040                              mfilter->ethertype == efilter->ether_type &&
3041                              mfilter->flags ==
3042                              HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_PATH_RX)) {
3043                                 match = 1;
3044                                 break;
3045                         }
3046         }
3047
3048         if (match)
3049                 *ret = -EEXIST;
3050
3051 exit:
3052         return mfilter;
3053 }
3054
3055 static int
3056 bnxt_ethertype_filter(struct rte_eth_dev *dev,
3057                         enum rte_filter_op filter_op,
3058                         void *arg)
3059 {
3060         struct bnxt *bp = dev->data->dev_private;
3061         struct rte_eth_ethertype_filter *efilter =
3062                         (struct rte_eth_ethertype_filter *)arg;
3063         struct bnxt_filter_info *bfilter, *filter1;
3064         struct bnxt_vnic_info *vnic, *vnic0;
3065         int ret;
3066
3067         if (filter_op == RTE_ETH_FILTER_NOP)
3068                 return 0;
3069
3070         if (arg == NULL) {
3071                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
3072                             filter_op);
3073                 return -EINVAL;
3074         }
3075
3076         vnic0 = BNXT_GET_DEFAULT_VNIC(bp);
3077         vnic = &bp->vnic_info[efilter->queue];
3078
3079         switch (filter_op) {
3080         case RTE_ETH_FILTER_ADD:
3081                 bnxt_match_and_validate_ether_filter(bp, efilter,
3082                                                         vnic0, vnic, &ret);
3083                 if (ret < 0)
3084                         return ret;
3085
3086                 bfilter = bnxt_get_unused_filter(bp);
3087                 if (bfilter == NULL) {
3088                         PMD_DRV_LOG(ERR,
3089                                 "Not enough resources for a new filter.\n");
3090                         return -ENOMEM;
3091                 }
3092                 bfilter->filter_type = HWRM_CFA_NTUPLE_FILTER;
3093                 memcpy(bfilter->l2_addr, efilter->mac_addr.addr_bytes,
3094                        RTE_ETHER_ADDR_LEN);
3095                 memcpy(bfilter->dst_macaddr, efilter->mac_addr.addr_bytes,
3096                        RTE_ETHER_ADDR_LEN);
3097                 bfilter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_MACADDR;
3098                 bfilter->ethertype = efilter->ether_type;
3099                 bfilter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
3100
3101                 filter1 = bnxt_get_l2_filter(bp, bfilter, vnic0);
3102                 if (filter1 == NULL) {
3103                         ret = -EINVAL;
3104                         goto cleanup;
3105                 }
3106                 bfilter->enables |=
3107                         HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID;
3108                 bfilter->fw_l2_filter_id = filter1->fw_l2_filter_id;
3109
3110                 bfilter->dst_id = vnic->fw_vnic_id;
3111
3112                 if (efilter->flags & RTE_ETHTYPE_FLAGS_DROP) {
3113                         bfilter->flags =
3114                                 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_DROP;
3115                 }
3116
3117                 ret = bnxt_hwrm_set_ntuple_filter(bp, bfilter->dst_id, bfilter);
3118                 if (ret)
3119                         goto cleanup;
3120                 STAILQ_INSERT_TAIL(&vnic->filter, bfilter, next);
3121                 break;
3122         case RTE_ETH_FILTER_DELETE:
3123                 filter1 = bnxt_match_and_validate_ether_filter(bp, efilter,
3124                                                         vnic0, vnic, &ret);
3125                 if (ret == -EEXIST) {
3126                         ret = bnxt_hwrm_clear_ntuple_filter(bp, filter1);
3127
3128                         STAILQ_REMOVE(&vnic->filter, filter1, bnxt_filter_info,
3129                                       next);
3130                         bnxt_free_filter(bp, filter1);
3131                 } else if (ret == 0) {
3132                         PMD_DRV_LOG(ERR, "No matching filter found\n");
3133                 }
3134                 break;
3135         default:
3136                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
3137                 ret = -EINVAL;
3138                 goto error;
3139         }
3140         return ret;
3141 cleanup:
3142         bnxt_free_filter(bp, bfilter);
3143 error:
3144         return ret;
3145 }
3146
3147 static inline int
3148 parse_ntuple_filter(struct bnxt *bp,
3149                     struct rte_eth_ntuple_filter *nfilter,
3150                     struct bnxt_filter_info *bfilter)
3151 {
3152         uint32_t en = 0;
3153
3154         if (nfilter->queue >= bp->rx_nr_rings) {
3155                 PMD_DRV_LOG(ERR, "Invalid queue %d\n", nfilter->queue);
3156                 return -EINVAL;
3157         }
3158
3159         switch (nfilter->dst_port_mask) {
3160         case UINT16_MAX:
3161                 bfilter->dst_port_mask = -1;
3162                 bfilter->dst_port = nfilter->dst_port;
3163                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT |
3164                         NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
3165                 break;
3166         default:
3167                 PMD_DRV_LOG(ERR, "invalid dst_port mask.");
3168                 return -EINVAL;
3169         }
3170
3171         bfilter->ip_addr_type = NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4;
3172         en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
3173
3174         switch (nfilter->proto_mask) {
3175         case UINT8_MAX:
3176                 if (nfilter->proto == 17) /* IPPROTO_UDP */
3177                         bfilter->ip_protocol = 17;
3178                 else if (nfilter->proto == 6) /* IPPROTO_TCP */
3179                         bfilter->ip_protocol = 6;
3180                 else
3181                         return -EINVAL;
3182                 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
3183                 break;
3184         default:
3185                 PMD_DRV_LOG(ERR, "invalid protocol mask.");
3186                 return -EINVAL;
3187         }
3188
3189         switch (nfilter->dst_ip_mask) {
3190         case UINT32_MAX:
3191                 bfilter->dst_ipaddr_mask[0] = -1;
3192                 bfilter->dst_ipaddr[0] = nfilter->dst_ip;
3193                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR |
3194                         NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
3195                 break;
3196         default:
3197                 PMD_DRV_LOG(ERR, "invalid dst_ip mask.");
3198                 return -EINVAL;
3199         }
3200
3201         switch (nfilter->src_ip_mask) {
3202         case UINT32_MAX:
3203                 bfilter->src_ipaddr_mask[0] = -1;
3204                 bfilter->src_ipaddr[0] = nfilter->src_ip;
3205                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR |
3206                         NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
3207                 break;
3208         default:
3209                 PMD_DRV_LOG(ERR, "invalid src_ip mask.");
3210                 return -EINVAL;
3211         }
3212
3213         switch (nfilter->src_port_mask) {
3214         case UINT16_MAX:
3215                 bfilter->src_port_mask = -1;
3216                 bfilter->src_port = nfilter->src_port;
3217                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT |
3218                         NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
3219                 break;
3220         default:
3221                 PMD_DRV_LOG(ERR, "invalid src_port mask.");
3222                 return -EINVAL;
3223         }
3224
3225         bfilter->enables = en;
3226         return 0;
3227 }
3228
3229 static struct bnxt_filter_info*
3230 bnxt_match_ntuple_filter(struct bnxt *bp,
3231                          struct bnxt_filter_info *bfilter,
3232                          struct bnxt_vnic_info **mvnic)
3233 {
3234         struct bnxt_filter_info *mfilter = NULL;
3235         int i;
3236
3237         for (i = bp->nr_vnics - 1; i >= 0; i--) {
3238                 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
3239                 STAILQ_FOREACH(mfilter, &vnic->filter, next) {
3240                         if (bfilter->src_ipaddr[0] == mfilter->src_ipaddr[0] &&
3241                             bfilter->src_ipaddr_mask[0] ==
3242                             mfilter->src_ipaddr_mask[0] &&
3243                             bfilter->src_port == mfilter->src_port &&
3244                             bfilter->src_port_mask == mfilter->src_port_mask &&
3245                             bfilter->dst_ipaddr[0] == mfilter->dst_ipaddr[0] &&
3246                             bfilter->dst_ipaddr_mask[0] ==
3247                             mfilter->dst_ipaddr_mask[0] &&
3248                             bfilter->dst_port == mfilter->dst_port &&
3249                             bfilter->dst_port_mask == mfilter->dst_port_mask &&
3250                             bfilter->flags == mfilter->flags &&
3251                             bfilter->enables == mfilter->enables) {
3252                                 if (mvnic)
3253                                         *mvnic = vnic;
3254                                 return mfilter;
3255                         }
3256                 }
3257         }
3258         return NULL;
3259 }
3260
3261 static int
3262 bnxt_cfg_ntuple_filter(struct bnxt *bp,
3263                        struct rte_eth_ntuple_filter *nfilter,
3264                        enum rte_filter_op filter_op)
3265 {
3266         struct bnxt_filter_info *bfilter, *mfilter, *filter1;
3267         struct bnxt_vnic_info *vnic, *vnic0, *mvnic;
3268         int ret;
3269
3270         if (nfilter->flags != RTE_5TUPLE_FLAGS) {
3271                 PMD_DRV_LOG(ERR, "only 5tuple is supported.");
3272                 return -EINVAL;
3273         }
3274
3275         if (nfilter->flags & RTE_NTUPLE_FLAGS_TCP_FLAG) {
3276                 PMD_DRV_LOG(ERR, "Ntuple filter: TCP flags not supported\n");
3277                 return -EINVAL;
3278         }
3279
3280         bfilter = bnxt_get_unused_filter(bp);
3281         if (bfilter == NULL) {
3282                 PMD_DRV_LOG(ERR,
3283                         "Not enough resources for a new filter.\n");
3284                 return -ENOMEM;
3285         }
3286         ret = parse_ntuple_filter(bp, nfilter, bfilter);
3287         if (ret < 0)
3288                 goto free_filter;
3289
3290         vnic = &bp->vnic_info[nfilter->queue];
3291         vnic0 = BNXT_GET_DEFAULT_VNIC(bp);
3292         filter1 = STAILQ_FIRST(&vnic0->filter);
3293         if (filter1 == NULL) {
3294                 ret = -EINVAL;
3295                 goto free_filter;
3296         }
3297
3298         bfilter->dst_id = vnic->fw_vnic_id;
3299         bfilter->fw_l2_filter_id = filter1->fw_l2_filter_id;
3300         bfilter->enables |=
3301                 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID;
3302         bfilter->ethertype = 0x800;
3303         bfilter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
3304
3305         mfilter = bnxt_match_ntuple_filter(bp, bfilter, &mvnic);
3306
3307         if (mfilter != NULL && filter_op == RTE_ETH_FILTER_ADD &&
3308             bfilter->dst_id == mfilter->dst_id) {
3309                 PMD_DRV_LOG(ERR, "filter exists.\n");
3310                 ret = -EEXIST;
3311                 goto free_filter;
3312         } else if (mfilter != NULL && filter_op == RTE_ETH_FILTER_ADD &&
3313                    bfilter->dst_id != mfilter->dst_id) {
3314                 mfilter->dst_id = vnic->fw_vnic_id;
3315                 ret = bnxt_hwrm_set_ntuple_filter(bp, mfilter->dst_id, mfilter);
3316                 STAILQ_REMOVE(&mvnic->filter, mfilter, bnxt_filter_info, next);
3317                 STAILQ_INSERT_TAIL(&vnic->filter, mfilter, next);
3318                 PMD_DRV_LOG(ERR, "filter with matching pattern exists.\n");
3319                 PMD_DRV_LOG(ERR, " Updated it to the new destination queue\n");
3320                 goto free_filter;
3321         }
3322         if (mfilter == NULL && filter_op == RTE_ETH_FILTER_DELETE) {
3323                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
3324                 ret = -ENOENT;
3325                 goto free_filter;
3326         }
3327
3328         if (filter_op == RTE_ETH_FILTER_ADD) {
3329                 bfilter->filter_type = HWRM_CFA_NTUPLE_FILTER;
3330                 ret = bnxt_hwrm_set_ntuple_filter(bp, bfilter->dst_id, bfilter);
3331                 if (ret)
3332                         goto free_filter;
3333                 STAILQ_INSERT_TAIL(&vnic->filter, bfilter, next);
3334         } else {
3335                 if (mfilter == NULL) {
3336                         /* This should not happen. But for Coverity! */
3337                         ret = -ENOENT;
3338                         goto free_filter;
3339                 }
3340                 ret = bnxt_hwrm_clear_ntuple_filter(bp, mfilter);
3341
3342                 STAILQ_REMOVE(&vnic->filter, mfilter, bnxt_filter_info, next);
3343                 bnxt_free_filter(bp, mfilter);
3344                 bnxt_free_filter(bp, bfilter);
3345         }
3346
3347         return 0;
3348 free_filter:
3349         bnxt_free_filter(bp, bfilter);
3350         return ret;
3351 }
3352
3353 static int
3354 bnxt_ntuple_filter(struct rte_eth_dev *dev,
3355                         enum rte_filter_op filter_op,
3356                         void *arg)
3357 {
3358         struct bnxt *bp = dev->data->dev_private;
3359         int ret;
3360
3361         if (filter_op == RTE_ETH_FILTER_NOP)
3362                 return 0;
3363
3364         if (arg == NULL) {
3365                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
3366                             filter_op);
3367                 return -EINVAL;
3368         }
3369
3370         switch (filter_op) {
3371         case RTE_ETH_FILTER_ADD:
3372                 ret = bnxt_cfg_ntuple_filter(bp,
3373                         (struct rte_eth_ntuple_filter *)arg,
3374                         filter_op);
3375                 break;
3376         case RTE_ETH_FILTER_DELETE:
3377                 ret = bnxt_cfg_ntuple_filter(bp,
3378                         (struct rte_eth_ntuple_filter *)arg,
3379                         filter_op);
3380                 break;
3381         default:
3382                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
3383                 ret = -EINVAL;
3384                 break;
3385         }
3386         return ret;
3387 }
3388
3389 static int
3390 bnxt_parse_fdir_filter(struct bnxt *bp,
3391                        struct rte_eth_fdir_filter *fdir,
3392                        struct bnxt_filter_info *filter)
3393 {
3394         enum rte_fdir_mode fdir_mode =
3395                 bp->eth_dev->data->dev_conf.fdir_conf.mode;
3396         struct bnxt_vnic_info *vnic0, *vnic;
3397         struct bnxt_filter_info *filter1;
3398         uint32_t en = 0;
3399         int i;
3400
3401         if (fdir_mode == RTE_FDIR_MODE_PERFECT_TUNNEL)
3402                 return -EINVAL;
3403
3404         filter->l2_ovlan = fdir->input.flow_ext.vlan_tci;
3405         en |= EM_FLOW_ALLOC_INPUT_EN_OVLAN_VID;
3406
3407         switch (fdir->input.flow_type) {
3408         case RTE_ETH_FLOW_IPV4:
3409         case RTE_ETH_FLOW_NONFRAG_IPV4_OTHER:
3410                 /* FALLTHROUGH */
3411                 filter->src_ipaddr[0] = fdir->input.flow.ip4_flow.src_ip;
3412                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
3413                 filter->dst_ipaddr[0] = fdir->input.flow.ip4_flow.dst_ip;
3414                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
3415                 filter->ip_protocol = fdir->input.flow.ip4_flow.proto;
3416                 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
3417                 filter->ip_addr_type =
3418                         NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4;
3419                 filter->src_ipaddr_mask[0] = 0xffffffff;
3420                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
3421                 filter->dst_ipaddr_mask[0] = 0xffffffff;
3422                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
3423                 filter->ethertype = 0x800;
3424                 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
3425                 break;
3426         case RTE_ETH_FLOW_NONFRAG_IPV4_TCP:
3427                 filter->src_port = fdir->input.flow.tcp4_flow.src_port;
3428                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT;
3429                 filter->dst_port = fdir->input.flow.tcp4_flow.dst_port;
3430                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT;
3431                 filter->dst_port_mask = 0xffff;
3432                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
3433                 filter->src_port_mask = 0xffff;
3434                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
3435                 filter->src_ipaddr[0] = fdir->input.flow.tcp4_flow.ip.src_ip;
3436                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
3437                 filter->dst_ipaddr[0] = fdir->input.flow.tcp4_flow.ip.dst_ip;
3438                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
3439                 filter->ip_protocol = 6;
3440                 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
3441                 filter->ip_addr_type =
3442                         NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4;
3443                 filter->src_ipaddr_mask[0] = 0xffffffff;
3444                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
3445                 filter->dst_ipaddr_mask[0] = 0xffffffff;
3446                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
3447                 filter->ethertype = 0x800;
3448                 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
3449                 break;
3450         case RTE_ETH_FLOW_NONFRAG_IPV4_UDP:
3451                 filter->src_port = fdir->input.flow.udp4_flow.src_port;
3452                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT;
3453                 filter->dst_port = fdir->input.flow.udp4_flow.dst_port;
3454                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT;
3455                 filter->dst_port_mask = 0xffff;
3456                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
3457                 filter->src_port_mask = 0xffff;
3458                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
3459                 filter->src_ipaddr[0] = fdir->input.flow.udp4_flow.ip.src_ip;
3460                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
3461                 filter->dst_ipaddr[0] = fdir->input.flow.udp4_flow.ip.dst_ip;
3462                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
3463                 filter->ip_protocol = 17;
3464                 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
3465                 filter->ip_addr_type =
3466                         NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4;
3467                 filter->src_ipaddr_mask[0] = 0xffffffff;
3468                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
3469                 filter->dst_ipaddr_mask[0] = 0xffffffff;
3470                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
3471                 filter->ethertype = 0x800;
3472                 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
3473                 break;
3474         case RTE_ETH_FLOW_IPV6:
3475         case RTE_ETH_FLOW_NONFRAG_IPV6_OTHER:
3476                 /* FALLTHROUGH */
3477                 filter->ip_addr_type =
3478                         NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV6;
3479                 filter->ip_protocol = fdir->input.flow.ipv6_flow.proto;
3480                 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
3481                 rte_memcpy(filter->src_ipaddr,
3482                            fdir->input.flow.ipv6_flow.src_ip, 16);
3483                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
3484                 rte_memcpy(filter->dst_ipaddr,
3485                            fdir->input.flow.ipv6_flow.dst_ip, 16);
3486                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
3487                 memset(filter->dst_ipaddr_mask, 0xff, 16);
3488                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
3489                 memset(filter->src_ipaddr_mask, 0xff, 16);
3490                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
3491                 filter->ethertype = 0x86dd;
3492                 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
3493                 break;
3494         case RTE_ETH_FLOW_NONFRAG_IPV6_TCP:
3495                 filter->src_port = fdir->input.flow.tcp6_flow.src_port;
3496                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT;
3497                 filter->dst_port = fdir->input.flow.tcp6_flow.dst_port;
3498                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT;
3499                 filter->dst_port_mask = 0xffff;
3500                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
3501                 filter->src_port_mask = 0xffff;
3502                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
3503                 filter->ip_addr_type =
3504                         NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV6;
3505                 filter->ip_protocol = fdir->input.flow.tcp6_flow.ip.proto;
3506                 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
3507                 rte_memcpy(filter->src_ipaddr,
3508                            fdir->input.flow.tcp6_flow.ip.src_ip, 16);
3509                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
3510                 rte_memcpy(filter->dst_ipaddr,
3511                            fdir->input.flow.tcp6_flow.ip.dst_ip, 16);
3512                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
3513                 memset(filter->dst_ipaddr_mask, 0xff, 16);
3514                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
3515                 memset(filter->src_ipaddr_mask, 0xff, 16);
3516                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
3517                 filter->ethertype = 0x86dd;
3518                 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
3519                 break;
3520         case RTE_ETH_FLOW_NONFRAG_IPV6_UDP:
3521                 filter->src_port = fdir->input.flow.udp6_flow.src_port;
3522                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT;
3523                 filter->dst_port = fdir->input.flow.udp6_flow.dst_port;
3524                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT;
3525                 filter->dst_port_mask = 0xffff;
3526                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
3527                 filter->src_port_mask = 0xffff;
3528                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
3529                 filter->ip_addr_type =
3530                         NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV6;
3531                 filter->ip_protocol = fdir->input.flow.udp6_flow.ip.proto;
3532                 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
3533                 rte_memcpy(filter->src_ipaddr,
3534                            fdir->input.flow.udp6_flow.ip.src_ip, 16);
3535                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
3536                 rte_memcpy(filter->dst_ipaddr,
3537                            fdir->input.flow.udp6_flow.ip.dst_ip, 16);
3538                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
3539                 memset(filter->dst_ipaddr_mask, 0xff, 16);
3540                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
3541                 memset(filter->src_ipaddr_mask, 0xff, 16);
3542                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
3543                 filter->ethertype = 0x86dd;
3544                 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
3545                 break;
3546         case RTE_ETH_FLOW_L2_PAYLOAD:
3547                 filter->ethertype = fdir->input.flow.l2_flow.ether_type;
3548                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
3549                 break;
3550         case RTE_ETH_FLOW_VXLAN:
3551                 if (fdir->action.behavior == RTE_ETH_FDIR_REJECT)
3552                         return -EINVAL;
3553                 filter->vni = fdir->input.flow.tunnel_flow.tunnel_id;
3554                 filter->tunnel_type =
3555                         CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN;
3556                 en |= HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_TUNNEL_TYPE;
3557                 break;
3558         case RTE_ETH_FLOW_NVGRE:
3559                 if (fdir->action.behavior == RTE_ETH_FDIR_REJECT)
3560                         return -EINVAL;
3561                 filter->vni = fdir->input.flow.tunnel_flow.tunnel_id;
3562                 filter->tunnel_type =
3563                         CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_NVGRE;
3564                 en |= HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_TUNNEL_TYPE;
3565                 break;
3566         case RTE_ETH_FLOW_UNKNOWN:
3567         case RTE_ETH_FLOW_RAW:
3568         case RTE_ETH_FLOW_FRAG_IPV4:
3569         case RTE_ETH_FLOW_NONFRAG_IPV4_SCTP:
3570         case RTE_ETH_FLOW_FRAG_IPV6:
3571         case RTE_ETH_FLOW_NONFRAG_IPV6_SCTP:
3572         case RTE_ETH_FLOW_IPV6_EX:
3573         case RTE_ETH_FLOW_IPV6_TCP_EX:
3574         case RTE_ETH_FLOW_IPV6_UDP_EX:
3575         case RTE_ETH_FLOW_GENEVE:
3576                 /* FALLTHROUGH */
3577         default:
3578                 return -EINVAL;
3579         }
3580
3581         vnic0 = BNXT_GET_DEFAULT_VNIC(bp);
3582         vnic = &bp->vnic_info[fdir->action.rx_queue];
3583         if (vnic == NULL) {
3584                 PMD_DRV_LOG(ERR, "Invalid queue %d\n", fdir->action.rx_queue);
3585                 return -EINVAL;
3586         }
3587
3588         if (fdir_mode == RTE_FDIR_MODE_PERFECT_MAC_VLAN) {
3589                 rte_memcpy(filter->dst_macaddr,
3590                         fdir->input.flow.mac_vlan_flow.mac_addr.addr_bytes, 6);
3591                         en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_MACADDR;
3592         }
3593
3594         if (fdir->action.behavior == RTE_ETH_FDIR_REJECT) {
3595                 filter->flags = HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_DROP;
3596                 filter1 = STAILQ_FIRST(&vnic0->filter);
3597                 //filter1 = bnxt_get_l2_filter(bp, filter, vnic0);
3598         } else {
3599                 filter->dst_id = vnic->fw_vnic_id;
3600                 for (i = 0; i < RTE_ETHER_ADDR_LEN; i++)
3601                         if (filter->dst_macaddr[i] == 0x00)
3602                                 filter1 = STAILQ_FIRST(&vnic0->filter);
3603                         else
3604                                 filter1 = bnxt_get_l2_filter(bp, filter, vnic);
3605         }
3606
3607         if (filter1 == NULL)
3608                 return -EINVAL;
3609
3610         en |= HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID;
3611         filter->fw_l2_filter_id = filter1->fw_l2_filter_id;
3612
3613         filter->enables = en;
3614
3615         return 0;
3616 }
3617
3618 static struct bnxt_filter_info *
3619 bnxt_match_fdir(struct bnxt *bp, struct bnxt_filter_info *nf,
3620                 struct bnxt_vnic_info **mvnic)
3621 {
3622         struct bnxt_filter_info *mf = NULL;
3623         int i;
3624
3625         for (i = bp->nr_vnics - 1; i >= 0; i--) {
3626                 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
3627
3628                 STAILQ_FOREACH(mf, &vnic->filter, next) {
3629                         if (mf->filter_type == nf->filter_type &&
3630                             mf->flags == nf->flags &&
3631                             mf->src_port == nf->src_port &&
3632                             mf->src_port_mask == nf->src_port_mask &&
3633                             mf->dst_port == nf->dst_port &&
3634                             mf->dst_port_mask == nf->dst_port_mask &&
3635                             mf->ip_protocol == nf->ip_protocol &&
3636                             mf->ip_addr_type == nf->ip_addr_type &&
3637                             mf->ethertype == nf->ethertype &&
3638                             mf->vni == nf->vni &&
3639                             mf->tunnel_type == nf->tunnel_type &&
3640                             mf->l2_ovlan == nf->l2_ovlan &&
3641                             mf->l2_ovlan_mask == nf->l2_ovlan_mask &&
3642                             mf->l2_ivlan == nf->l2_ivlan &&
3643                             mf->l2_ivlan_mask == nf->l2_ivlan_mask &&
3644                             !memcmp(mf->l2_addr, nf->l2_addr,
3645                                     RTE_ETHER_ADDR_LEN) &&
3646                             !memcmp(mf->l2_addr_mask, nf->l2_addr_mask,
3647                                     RTE_ETHER_ADDR_LEN) &&
3648                             !memcmp(mf->src_macaddr, nf->src_macaddr,
3649                                     RTE_ETHER_ADDR_LEN) &&
3650                             !memcmp(mf->dst_macaddr, nf->dst_macaddr,
3651                                     RTE_ETHER_ADDR_LEN) &&
3652                             !memcmp(mf->src_ipaddr, nf->src_ipaddr,
3653                                     sizeof(nf->src_ipaddr)) &&
3654                             !memcmp(mf->src_ipaddr_mask, nf->src_ipaddr_mask,
3655                                     sizeof(nf->src_ipaddr_mask)) &&
3656                             !memcmp(mf->dst_ipaddr, nf->dst_ipaddr,
3657                                     sizeof(nf->dst_ipaddr)) &&
3658                             !memcmp(mf->dst_ipaddr_mask, nf->dst_ipaddr_mask,
3659                                     sizeof(nf->dst_ipaddr_mask))) {
3660                                 if (mvnic)
3661                                         *mvnic = vnic;
3662                                 return mf;
3663                         }
3664                 }
3665         }
3666         return NULL;
3667 }
3668
3669 static int
3670 bnxt_fdir_filter(struct rte_eth_dev *dev,
3671                  enum rte_filter_op filter_op,
3672                  void *arg)
3673 {
3674         struct bnxt *bp = dev->data->dev_private;
3675         struct rte_eth_fdir_filter *fdir  = (struct rte_eth_fdir_filter *)arg;
3676         struct bnxt_filter_info *filter, *match;
3677         struct bnxt_vnic_info *vnic, *mvnic;
3678         int ret = 0, i;
3679
3680         if (filter_op == RTE_ETH_FILTER_NOP)
3681                 return 0;
3682
3683         if (arg == NULL && filter_op != RTE_ETH_FILTER_FLUSH)
3684                 return -EINVAL;
3685
3686         switch (filter_op) {
3687         case RTE_ETH_FILTER_ADD:
3688         case RTE_ETH_FILTER_DELETE:
3689                 /* FALLTHROUGH */
3690                 filter = bnxt_get_unused_filter(bp);
3691                 if (filter == NULL) {
3692                         PMD_DRV_LOG(ERR,
3693                                 "Not enough resources for a new flow.\n");
3694                         return -ENOMEM;
3695                 }
3696
3697                 ret = bnxt_parse_fdir_filter(bp, fdir, filter);
3698                 if (ret != 0)
3699                         goto free_filter;
3700                 filter->filter_type = HWRM_CFA_NTUPLE_FILTER;
3701
3702                 if (fdir->action.behavior == RTE_ETH_FDIR_REJECT)
3703                         vnic = &bp->vnic_info[0];
3704                 else
3705                         vnic = &bp->vnic_info[fdir->action.rx_queue];
3706
3707                 match = bnxt_match_fdir(bp, filter, &mvnic);
3708                 if (match != NULL && filter_op == RTE_ETH_FILTER_ADD) {
3709                         if (match->dst_id == vnic->fw_vnic_id) {
3710                                 PMD_DRV_LOG(ERR, "Flow already exists.\n");
3711                                 ret = -EEXIST;
3712                                 goto free_filter;
3713                         } else {
3714                                 match->dst_id = vnic->fw_vnic_id;
3715                                 ret = bnxt_hwrm_set_ntuple_filter(bp,
3716                                                                   match->dst_id,
3717                                                                   match);
3718                                 STAILQ_REMOVE(&mvnic->filter, match,
3719                                               bnxt_filter_info, next);
3720                                 STAILQ_INSERT_TAIL(&vnic->filter, match, next);
3721                                 PMD_DRV_LOG(ERR,
3722                                         "Filter with matching pattern exist\n");
3723                                 PMD_DRV_LOG(ERR,
3724                                         "Updated it to new destination q\n");
3725                                 goto free_filter;
3726                         }
3727                 }
3728                 if (match == NULL && filter_op == RTE_ETH_FILTER_DELETE) {
3729                         PMD_DRV_LOG(ERR, "Flow does not exist.\n");
3730                         ret = -ENOENT;
3731                         goto free_filter;
3732                 }
3733
3734                 if (filter_op == RTE_ETH_FILTER_ADD) {
3735                         ret = bnxt_hwrm_set_ntuple_filter(bp,
3736                                                           filter->dst_id,
3737                                                           filter);
3738                         if (ret)
3739                                 goto free_filter;
3740                         STAILQ_INSERT_TAIL(&vnic->filter, filter, next);
3741                 } else {
3742                         ret = bnxt_hwrm_clear_ntuple_filter(bp, match);
3743                         STAILQ_REMOVE(&vnic->filter, match,
3744                                       bnxt_filter_info, next);
3745                         bnxt_free_filter(bp, match);
3746                         bnxt_free_filter(bp, filter);
3747                 }
3748                 break;
3749         case RTE_ETH_FILTER_FLUSH:
3750                 for (i = bp->nr_vnics - 1; i >= 0; i--) {
3751                         struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
3752
3753                         STAILQ_FOREACH(filter, &vnic->filter, next) {
3754                                 if (filter->filter_type ==
3755                                     HWRM_CFA_NTUPLE_FILTER) {
3756                                         ret =
3757                                         bnxt_hwrm_clear_ntuple_filter(bp,
3758                                                                       filter);
3759                                         STAILQ_REMOVE(&vnic->filter, filter,
3760                                                       bnxt_filter_info, next);
3761                                 }
3762                         }
3763                 }
3764                 return ret;
3765         case RTE_ETH_FILTER_UPDATE:
3766         case RTE_ETH_FILTER_STATS:
3767         case RTE_ETH_FILTER_INFO:
3768                 PMD_DRV_LOG(ERR, "operation %u not implemented", filter_op);
3769                 break;
3770         default:
3771                 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
3772                 ret = -EINVAL;
3773                 break;
3774         }
3775         return ret;
3776
3777 free_filter:
3778         bnxt_free_filter(bp, filter);
3779         return ret;
3780 }
3781
3782 int
3783 bnxt_filter_ctrl_op(struct rte_eth_dev *dev,
3784                     enum rte_filter_type filter_type,
3785                     enum rte_filter_op filter_op, void *arg)
3786 {
3787         struct bnxt *bp = dev->data->dev_private;
3788         int ret = 0;
3789
3790         if (!bp)
3791                 return -EIO;
3792
3793         if (BNXT_ETH_DEV_IS_REPRESENTOR(dev)) {
3794                 struct bnxt_representor *vfr = dev->data->dev_private;
3795                 bp = vfr->parent_dev->data->dev_private;
3796                 /* parent is deleted while children are still valid */
3797                 if (!bp) {
3798                         PMD_DRV_LOG(DEBUG, "BNXT Port:%d VFR Error %d:%d\n",
3799                                     dev->data->port_id,
3800                                     filter_type,
3801                                     filter_op);
3802                         return -EIO;
3803                 }
3804         }
3805
3806         ret = is_bnxt_in_error(bp);
3807         if (ret)
3808                 return ret;
3809
3810         switch (filter_type) {
3811         case RTE_ETH_FILTER_TUNNEL:
3812                 PMD_DRV_LOG(ERR,
3813                         "filter type: %d: To be implemented\n", filter_type);
3814                 break;
3815         case RTE_ETH_FILTER_FDIR:
3816                 ret = bnxt_fdir_filter(dev, filter_op, arg);
3817                 break;
3818         case RTE_ETH_FILTER_NTUPLE:
3819                 ret = bnxt_ntuple_filter(dev, filter_op, arg);
3820                 break;
3821         case RTE_ETH_FILTER_ETHERTYPE:
3822                 ret = bnxt_ethertype_filter(dev, filter_op, arg);
3823                 break;
3824         case RTE_ETH_FILTER_GENERIC:
3825                 if (filter_op != RTE_ETH_FILTER_GET)
3826                         return -EINVAL;
3827                 if (BNXT_TRUFLOW_EN(bp))
3828                         *(const void **)arg = &bnxt_ulp_rte_flow_ops;
3829                 else
3830                         *(const void **)arg = &bnxt_flow_ops;
3831                 break;
3832         default:
3833                 PMD_DRV_LOG(ERR,
3834                         "Filter type (%d) not supported", filter_type);
3835                 ret = -EINVAL;
3836                 break;
3837         }
3838         return ret;
3839 }
3840
3841 static const uint32_t *
3842 bnxt_dev_supported_ptypes_get_op(struct rte_eth_dev *dev)
3843 {
3844         static const uint32_t ptypes[] = {
3845                 RTE_PTYPE_L2_ETHER_VLAN,
3846                 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN,
3847                 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN,
3848                 RTE_PTYPE_L4_ICMP,
3849                 RTE_PTYPE_L4_TCP,
3850                 RTE_PTYPE_L4_UDP,
3851                 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN,
3852                 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN,
3853                 RTE_PTYPE_INNER_L4_ICMP,
3854                 RTE_PTYPE_INNER_L4_TCP,
3855                 RTE_PTYPE_INNER_L4_UDP,
3856                 RTE_PTYPE_UNKNOWN
3857         };
3858
3859         if (!dev->rx_pkt_burst)
3860                 return NULL;
3861
3862         return ptypes;
3863 }
3864
3865 static int bnxt_map_regs(struct bnxt *bp, uint32_t *reg_arr, int count,
3866                          int reg_win)
3867 {
3868         uint32_t reg_base = *reg_arr & 0xfffff000;
3869         uint32_t win_off;
3870         int i;
3871
3872         for (i = 0; i < count; i++) {
3873                 if ((reg_arr[i] & 0xfffff000) != reg_base)
3874                         return -ERANGE;
3875         }
3876         win_off = BNXT_GRCPF_REG_WINDOW_BASE_OUT + (reg_win - 1) * 4;
3877         rte_write32(reg_base, (uint8_t *)bp->bar0 + win_off);
3878         return 0;
3879 }
3880
3881 static int bnxt_map_ptp_regs(struct bnxt *bp)
3882 {
3883         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3884         uint32_t *reg_arr;
3885         int rc, i;
3886
3887         reg_arr = ptp->rx_regs;
3888         rc = bnxt_map_regs(bp, reg_arr, BNXT_PTP_RX_REGS, 5);
3889         if (rc)
3890                 return rc;
3891
3892         reg_arr = ptp->tx_regs;
3893         rc = bnxt_map_regs(bp, reg_arr, BNXT_PTP_TX_REGS, 6);
3894         if (rc)
3895                 return rc;
3896
3897         for (i = 0; i < BNXT_PTP_RX_REGS; i++)
3898                 ptp->rx_mapped_regs[i] = 0x5000 + (ptp->rx_regs[i] & 0xfff);
3899
3900         for (i = 0; i < BNXT_PTP_TX_REGS; i++)
3901                 ptp->tx_mapped_regs[i] = 0x6000 + (ptp->tx_regs[i] & 0xfff);
3902
3903         return 0;
3904 }
3905
3906 static void bnxt_unmap_ptp_regs(struct bnxt *bp)
3907 {
3908         rte_write32(0, (uint8_t *)bp->bar0 +
3909                          BNXT_GRCPF_REG_WINDOW_BASE_OUT + 16);
3910         rte_write32(0, (uint8_t *)bp->bar0 +
3911                          BNXT_GRCPF_REG_WINDOW_BASE_OUT + 20);
3912 }
3913
3914 static uint64_t bnxt_cc_read(struct bnxt *bp)
3915 {
3916         uint64_t ns;
3917
3918         ns = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3919                               BNXT_GRCPF_REG_SYNC_TIME));
3920         ns |= (uint64_t)(rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3921                                           BNXT_GRCPF_REG_SYNC_TIME + 4))) << 32;
3922         return ns;
3923 }
3924
3925 static int bnxt_get_tx_ts(struct bnxt *bp, uint64_t *ts)
3926 {
3927         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3928         uint32_t fifo;
3929
3930         fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3931                                 ptp->tx_mapped_regs[BNXT_PTP_TX_FIFO]));
3932         if (fifo & BNXT_PTP_TX_FIFO_EMPTY)
3933                 return -EAGAIN;
3934
3935         fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3936                                 ptp->tx_mapped_regs[BNXT_PTP_TX_FIFO]));
3937         *ts = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3938                                 ptp->tx_mapped_regs[BNXT_PTP_TX_TS_L]));
3939         *ts |= (uint64_t)rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3940                                 ptp->tx_mapped_regs[BNXT_PTP_TX_TS_H])) << 32;
3941
3942         return 0;
3943 }
3944
3945 static int bnxt_get_rx_ts(struct bnxt *bp, uint64_t *ts)
3946 {
3947         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3948         struct bnxt_pf_info *pf = bp->pf;
3949         uint16_t port_id;
3950         uint32_t fifo;
3951
3952         if (!ptp)
3953                 return -ENODEV;
3954
3955         fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3956                                 ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO]));
3957         if (!(fifo & BNXT_PTP_RX_FIFO_PENDING))
3958                 return -EAGAIN;
3959
3960         port_id = pf->port_id;
3961         rte_write32(1 << port_id, (uint8_t *)bp->bar0 +
3962                ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO_ADV]);
3963
3964         fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3965                                    ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO]));
3966         if (fifo & BNXT_PTP_RX_FIFO_PENDING) {
3967 /*              bnxt_clr_rx_ts(bp);       TBD  */
3968                 return -EBUSY;
3969         }
3970
3971         *ts = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3972                                 ptp->rx_mapped_regs[BNXT_PTP_RX_TS_L]));
3973         *ts |= (uint64_t)rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3974                                 ptp->rx_mapped_regs[BNXT_PTP_RX_TS_H])) << 32;
3975
3976         return 0;
3977 }
3978
3979 static int
3980 bnxt_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
3981 {
3982         uint64_t ns;
3983         struct bnxt *bp = dev->data->dev_private;
3984         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3985
3986         if (!ptp)
3987                 return 0;
3988
3989         ns = rte_timespec_to_ns(ts);
3990         /* Set the timecounters to a new value. */
3991         ptp->tc.nsec = ns;
3992
3993         return 0;
3994 }
3995
3996 static int
3997 bnxt_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
3998 {
3999         struct bnxt *bp = dev->data->dev_private;
4000         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
4001         uint64_t ns, systime_cycles = 0;
4002         int rc = 0;
4003
4004         if (!ptp)
4005                 return 0;
4006
4007         if (BNXT_CHIP_THOR(bp))
4008                 rc = bnxt_hwrm_port_ts_query(bp, BNXT_PTP_FLAGS_CURRENT_TIME,
4009                                              &systime_cycles);
4010         else
4011                 systime_cycles = bnxt_cc_read(bp);
4012
4013         ns = rte_timecounter_update(&ptp->tc, systime_cycles);
4014         *ts = rte_ns_to_timespec(ns);
4015
4016         return rc;
4017 }
4018 static int
4019 bnxt_timesync_enable(struct rte_eth_dev *dev)
4020 {
4021         struct bnxt *bp = dev->data->dev_private;
4022         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
4023         uint32_t shift = 0;
4024         int rc;
4025
4026         if (!ptp)
4027                 return 0;
4028
4029         ptp->rx_filter = 1;
4030         ptp->tx_tstamp_en = 1;
4031         ptp->rxctl = BNXT_PTP_MSG_EVENTS;
4032
4033         rc = bnxt_hwrm_ptp_cfg(bp);
4034         if (rc)
4035                 return rc;
4036
4037         memset(&ptp->tc, 0, sizeof(struct rte_timecounter));
4038         memset(&ptp->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
4039         memset(&ptp->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
4040
4041         ptp->tc.cc_mask = BNXT_CYCLECOUNTER_MASK;
4042         ptp->tc.cc_shift = shift;
4043         ptp->tc.nsec_mask = (1ULL << shift) - 1;
4044
4045         ptp->rx_tstamp_tc.cc_mask = BNXT_CYCLECOUNTER_MASK;
4046         ptp->rx_tstamp_tc.cc_shift = shift;
4047         ptp->rx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
4048
4049         ptp->tx_tstamp_tc.cc_mask = BNXT_CYCLECOUNTER_MASK;
4050         ptp->tx_tstamp_tc.cc_shift = shift;
4051         ptp->tx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
4052
4053         if (!BNXT_CHIP_THOR(bp))
4054                 bnxt_map_ptp_regs(bp);
4055
4056         return 0;
4057 }
4058
4059 static int
4060 bnxt_timesync_disable(struct rte_eth_dev *dev)
4061 {
4062         struct bnxt *bp = dev->data->dev_private;
4063         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
4064
4065         if (!ptp)
4066                 return 0;
4067
4068         ptp->rx_filter = 0;
4069         ptp->tx_tstamp_en = 0;
4070         ptp->rxctl = 0;
4071
4072         bnxt_hwrm_ptp_cfg(bp);
4073
4074         if (!BNXT_CHIP_THOR(bp))
4075                 bnxt_unmap_ptp_regs(bp);
4076
4077         return 0;
4078 }
4079
4080 static int
4081 bnxt_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
4082                                  struct timespec *timestamp,
4083                                  uint32_t flags __rte_unused)
4084 {
4085         struct bnxt *bp = dev->data->dev_private;
4086         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
4087         uint64_t rx_tstamp_cycles = 0;
4088         uint64_t ns;
4089
4090         if (!ptp)
4091                 return 0;
4092
4093         if (BNXT_CHIP_THOR(bp))
4094                 rx_tstamp_cycles = ptp->rx_timestamp;
4095         else
4096                 bnxt_get_rx_ts(bp, &rx_tstamp_cycles);
4097
4098         ns = rte_timecounter_update(&ptp->rx_tstamp_tc, rx_tstamp_cycles);
4099         *timestamp = rte_ns_to_timespec(ns);
4100         return  0;
4101 }
4102
4103 static int
4104 bnxt_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
4105                                  struct timespec *timestamp)
4106 {
4107         struct bnxt *bp = dev->data->dev_private;
4108         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
4109         uint64_t tx_tstamp_cycles = 0;
4110         uint64_t ns;
4111         int rc = 0;
4112
4113         if (!ptp)
4114                 return 0;
4115
4116         if (BNXT_CHIP_THOR(bp))
4117                 rc = bnxt_hwrm_port_ts_query(bp, BNXT_PTP_FLAGS_PATH_TX,
4118                                              &tx_tstamp_cycles);
4119         else
4120                 rc = bnxt_get_tx_ts(bp, &tx_tstamp_cycles);
4121
4122         ns = rte_timecounter_update(&ptp->tx_tstamp_tc, tx_tstamp_cycles);
4123         *timestamp = rte_ns_to_timespec(ns);
4124
4125         return rc;
4126 }
4127
4128 static int
4129 bnxt_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
4130 {
4131         struct bnxt *bp = dev->data->dev_private;
4132         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
4133
4134         if (!ptp)
4135                 return 0;
4136
4137         ptp->tc.nsec += delta;
4138
4139         return 0;
4140 }
4141
4142 static int
4143 bnxt_get_eeprom_length_op(struct rte_eth_dev *dev)
4144 {
4145         struct bnxt *bp = dev->data->dev_private;
4146         int rc;
4147         uint32_t dir_entries;
4148         uint32_t entry_length;
4149
4150         rc = is_bnxt_in_error(bp);
4151         if (rc)
4152                 return rc;
4153
4154         PMD_DRV_LOG(INFO, PCI_PRI_FMT "\n",
4155                     bp->pdev->addr.domain, bp->pdev->addr.bus,
4156                     bp->pdev->addr.devid, bp->pdev->addr.function);
4157
4158         rc = bnxt_hwrm_nvm_get_dir_info(bp, &dir_entries, &entry_length);
4159         if (rc != 0)
4160                 return rc;
4161
4162         return dir_entries * entry_length;
4163 }
4164
4165 static int
4166 bnxt_get_eeprom_op(struct rte_eth_dev *dev,
4167                 struct rte_dev_eeprom_info *in_eeprom)
4168 {
4169         struct bnxt *bp = dev->data->dev_private;
4170         uint32_t index;
4171         uint32_t offset;
4172         int rc;
4173
4174         rc = is_bnxt_in_error(bp);
4175         if (rc)
4176                 return rc;
4177
4178         PMD_DRV_LOG(INFO, PCI_PRI_FMT " in_eeprom->offset = %d len = %d\n",
4179                     bp->pdev->addr.domain, bp->pdev->addr.bus,
4180                     bp->pdev->addr.devid, bp->pdev->addr.function,
4181                     in_eeprom->offset, in_eeprom->length);
4182
4183         if (in_eeprom->offset == 0) /* special offset value to get directory */
4184                 return bnxt_get_nvram_directory(bp, in_eeprom->length,
4185                                                 in_eeprom->data);
4186
4187         index = in_eeprom->offset >> 24;
4188         offset = in_eeprom->offset & 0xffffff;
4189
4190         if (index != 0)
4191                 return bnxt_hwrm_get_nvram_item(bp, index - 1, offset,
4192                                            in_eeprom->length, in_eeprom->data);
4193
4194         return 0;
4195 }
4196
4197 static bool bnxt_dir_type_is_ape_bin_format(uint16_t dir_type)
4198 {
4199         switch (dir_type) {
4200         case BNX_DIR_TYPE_CHIMP_PATCH:
4201         case BNX_DIR_TYPE_BOOTCODE:
4202         case BNX_DIR_TYPE_BOOTCODE_2:
4203         case BNX_DIR_TYPE_APE_FW:
4204         case BNX_DIR_TYPE_APE_PATCH:
4205         case BNX_DIR_TYPE_KONG_FW:
4206         case BNX_DIR_TYPE_KONG_PATCH:
4207         case BNX_DIR_TYPE_BONO_FW:
4208         case BNX_DIR_TYPE_BONO_PATCH:
4209                 /* FALLTHROUGH */
4210                 return true;
4211         }
4212
4213         return false;
4214 }
4215
4216 static bool bnxt_dir_type_is_other_exec_format(uint16_t dir_type)
4217 {
4218         switch (dir_type) {
4219         case BNX_DIR_TYPE_AVS:
4220         case BNX_DIR_TYPE_EXP_ROM_MBA:
4221         case BNX_DIR_TYPE_PCIE:
4222         case BNX_DIR_TYPE_TSCF_UCODE:
4223         case BNX_DIR_TYPE_EXT_PHY:
4224         case BNX_DIR_TYPE_CCM:
4225         case BNX_DIR_TYPE_ISCSI_BOOT:
4226         case BNX_DIR_TYPE_ISCSI_BOOT_IPV6:
4227         case BNX_DIR_TYPE_ISCSI_BOOT_IPV4N6:
4228                 /* FALLTHROUGH */
4229                 return true;
4230         }
4231
4232         return false;
4233 }
4234
4235 static bool bnxt_dir_type_is_executable(uint16_t dir_type)
4236 {
4237         return bnxt_dir_type_is_ape_bin_format(dir_type) ||
4238                 bnxt_dir_type_is_other_exec_format(dir_type);
4239 }
4240
4241 static int
4242 bnxt_set_eeprom_op(struct rte_eth_dev *dev,
4243                 struct rte_dev_eeprom_info *in_eeprom)
4244 {
4245         struct bnxt *bp = dev->data->dev_private;
4246         uint8_t index, dir_op;
4247         uint16_t type, ext, ordinal, attr;
4248         int rc;
4249
4250         rc = is_bnxt_in_error(bp);
4251         if (rc)
4252                 return rc;
4253
4254         PMD_DRV_LOG(INFO, PCI_PRI_FMT " in_eeprom->offset = %d len = %d\n",
4255                     bp->pdev->addr.domain, bp->pdev->addr.bus,
4256                     bp->pdev->addr.devid, bp->pdev->addr.function,
4257                     in_eeprom->offset, in_eeprom->length);
4258
4259         if (!BNXT_PF(bp)) {
4260                 PMD_DRV_LOG(ERR, "NVM write not supported from a VF\n");
4261                 return -EINVAL;
4262         }
4263
4264         type = in_eeprom->magic >> 16;
4265
4266         if (type == 0xffff) { /* special value for directory operations */
4267                 index = in_eeprom->magic & 0xff;
4268                 dir_op = in_eeprom->magic >> 8;
4269                 if (index == 0)
4270                         return -EINVAL;
4271                 switch (dir_op) {
4272                 case 0x0e: /* erase */
4273                         if (in_eeprom->offset != ~in_eeprom->magic)
4274                                 return -EINVAL;
4275                         return bnxt_hwrm_erase_nvram_directory(bp, index - 1);
4276                 default:
4277                         return -EINVAL;
4278                 }
4279         }
4280
4281         /* Create or re-write an NVM item: */
4282         if (bnxt_dir_type_is_executable(type) == true)
4283                 return -EOPNOTSUPP;
4284         ext = in_eeprom->magic & 0xffff;
4285         ordinal = in_eeprom->offset >> 16;
4286         attr = in_eeprom->offset & 0xffff;
4287
4288         return bnxt_hwrm_flash_nvram(bp, type, ordinal, ext, attr,
4289                                      in_eeprom->data, in_eeprom->length);
4290 }
4291
4292 /*
4293  * Initialization
4294  */
4295
4296 static const struct eth_dev_ops bnxt_dev_ops = {
4297         .dev_infos_get = bnxt_dev_info_get_op,
4298         .dev_close = bnxt_dev_close_op,
4299         .dev_configure = bnxt_dev_configure_op,
4300         .dev_start = bnxt_dev_start_op,
4301         .dev_stop = bnxt_dev_stop_op,
4302         .dev_set_link_up = bnxt_dev_set_link_up_op,
4303         .dev_set_link_down = bnxt_dev_set_link_down_op,
4304         .stats_get = bnxt_stats_get_op,
4305         .stats_reset = bnxt_stats_reset_op,
4306         .rx_queue_setup = bnxt_rx_queue_setup_op,
4307         .rx_queue_release = bnxt_rx_queue_release_op,
4308         .tx_queue_setup = bnxt_tx_queue_setup_op,
4309         .tx_queue_release = bnxt_tx_queue_release_op,
4310         .rx_queue_intr_enable = bnxt_rx_queue_intr_enable_op,
4311         .rx_queue_intr_disable = bnxt_rx_queue_intr_disable_op,
4312         .reta_update = bnxt_reta_update_op,
4313         .reta_query = bnxt_reta_query_op,
4314         .rss_hash_update = bnxt_rss_hash_update_op,
4315         .rss_hash_conf_get = bnxt_rss_hash_conf_get_op,
4316         .link_update = bnxt_link_update_op,
4317         .promiscuous_enable = bnxt_promiscuous_enable_op,
4318         .promiscuous_disable = bnxt_promiscuous_disable_op,
4319         .allmulticast_enable = bnxt_allmulticast_enable_op,
4320         .allmulticast_disable = bnxt_allmulticast_disable_op,
4321         .mac_addr_add = bnxt_mac_addr_add_op,
4322         .mac_addr_remove = bnxt_mac_addr_remove_op,
4323         .flow_ctrl_get = bnxt_flow_ctrl_get_op,
4324         .flow_ctrl_set = bnxt_flow_ctrl_set_op,
4325         .udp_tunnel_port_add  = bnxt_udp_tunnel_port_add_op,
4326         .udp_tunnel_port_del  = bnxt_udp_tunnel_port_del_op,
4327         .vlan_filter_set = bnxt_vlan_filter_set_op,
4328         .vlan_offload_set = bnxt_vlan_offload_set_op,
4329         .vlan_tpid_set = bnxt_vlan_tpid_set_op,
4330         .vlan_pvid_set = bnxt_vlan_pvid_set_op,
4331         .mtu_set = bnxt_mtu_set_op,
4332         .mac_addr_set = bnxt_set_default_mac_addr_op,
4333         .xstats_get = bnxt_dev_xstats_get_op,
4334         .xstats_get_names = bnxt_dev_xstats_get_names_op,
4335         .xstats_reset = bnxt_dev_xstats_reset_op,
4336         .fw_version_get = bnxt_fw_version_get,
4337         .set_mc_addr_list = bnxt_dev_set_mc_addr_list_op,
4338         .rxq_info_get = bnxt_rxq_info_get_op,
4339         .txq_info_get = bnxt_txq_info_get_op,
4340         .rx_burst_mode_get = bnxt_rx_burst_mode_get,
4341         .tx_burst_mode_get = bnxt_tx_burst_mode_get,
4342         .dev_led_on = bnxt_dev_led_on_op,
4343         .dev_led_off = bnxt_dev_led_off_op,
4344         .xstats_get_by_id = bnxt_dev_xstats_get_by_id_op,
4345         .xstats_get_names_by_id = bnxt_dev_xstats_get_names_by_id_op,
4346         .rx_queue_start = bnxt_rx_queue_start,
4347         .rx_queue_stop = bnxt_rx_queue_stop,
4348         .tx_queue_start = bnxt_tx_queue_start,
4349         .tx_queue_stop = bnxt_tx_queue_stop,
4350         .filter_ctrl = bnxt_filter_ctrl_op,
4351         .dev_supported_ptypes_get = bnxt_dev_supported_ptypes_get_op,
4352         .get_eeprom_length    = bnxt_get_eeprom_length_op,
4353         .get_eeprom           = bnxt_get_eeprom_op,
4354         .set_eeprom           = bnxt_set_eeprom_op,
4355         .timesync_enable      = bnxt_timesync_enable,
4356         .timesync_disable     = bnxt_timesync_disable,
4357         .timesync_read_time   = bnxt_timesync_read_time,
4358         .timesync_write_time   = bnxt_timesync_write_time,
4359         .timesync_adjust_time = bnxt_timesync_adjust_time,
4360         .timesync_read_rx_timestamp = bnxt_timesync_read_rx_timestamp,
4361         .timesync_read_tx_timestamp = bnxt_timesync_read_tx_timestamp,
4362 };
4363
4364 static uint32_t bnxt_map_reset_regs(struct bnxt *bp, uint32_t reg)
4365 {
4366         uint32_t offset;
4367
4368         /* Only pre-map the reset GRC registers using window 3 */
4369         rte_write32(reg & 0xfffff000, (uint8_t *)bp->bar0 +
4370                     BNXT_GRCPF_REG_WINDOW_BASE_OUT + 8);
4371
4372         offset = BNXT_GRCP_WINDOW_3_BASE + (reg & 0xffc);
4373
4374         return offset;
4375 }
4376
4377 int bnxt_map_fw_health_status_regs(struct bnxt *bp)
4378 {
4379         struct bnxt_error_recovery_info *info = bp->recovery_info;
4380         uint32_t reg_base = 0xffffffff;
4381         int i;
4382
4383         /* Only pre-map the monitoring GRC registers using window 2 */
4384         for (i = 0; i < BNXT_FW_STATUS_REG_CNT; i++) {
4385                 uint32_t reg = info->status_regs[i];
4386
4387                 if (BNXT_FW_STATUS_REG_TYPE(reg) != BNXT_FW_STATUS_REG_TYPE_GRC)
4388                         continue;
4389
4390                 if (reg_base == 0xffffffff)
4391                         reg_base = reg & 0xfffff000;
4392                 if ((reg & 0xfffff000) != reg_base)
4393                         return -ERANGE;
4394
4395                 /* Use mask 0xffc as the Lower 2 bits indicates
4396                  * address space location
4397                  */
4398                 info->mapped_status_regs[i] = BNXT_GRCP_WINDOW_2_BASE +
4399                                                 (reg & 0xffc);
4400         }
4401
4402         if (reg_base == 0xffffffff)
4403                 return 0;
4404
4405         rte_write32(reg_base, (uint8_t *)bp->bar0 +
4406                     BNXT_GRCPF_REG_WINDOW_BASE_OUT + 4);
4407
4408         return 0;
4409 }
4410
4411 static void bnxt_write_fw_reset_reg(struct bnxt *bp, uint32_t index)
4412 {
4413         struct bnxt_error_recovery_info *info = bp->recovery_info;
4414         uint32_t delay = info->delay_after_reset[index];
4415         uint32_t val = info->reset_reg_val[index];
4416         uint32_t reg = info->reset_reg[index];
4417         uint32_t type, offset;
4418
4419         type = BNXT_FW_STATUS_REG_TYPE(reg);
4420         offset = BNXT_FW_STATUS_REG_OFF(reg);
4421
4422         switch (type) {
4423         case BNXT_FW_STATUS_REG_TYPE_CFG:
4424                 rte_pci_write_config(bp->pdev, &val, sizeof(val), offset);
4425                 break;
4426         case BNXT_FW_STATUS_REG_TYPE_GRC:
4427                 offset = bnxt_map_reset_regs(bp, offset);
4428                 rte_write32(val, (uint8_t *)bp->bar0 + offset);
4429                 break;
4430         case BNXT_FW_STATUS_REG_TYPE_BAR0:
4431                 rte_write32(val, (uint8_t *)bp->bar0 + offset);
4432                 break;
4433         }
4434         /* wait on a specific interval of time until core reset is complete */
4435         if (delay)
4436                 rte_delay_ms(delay);
4437 }
4438
4439 static void bnxt_dev_cleanup(struct bnxt *bp)
4440 {
4441         bp->eth_dev->data->dev_link.link_status = 0;
4442         bp->link_info->link_up = 0;
4443         if (bp->eth_dev->data->dev_started)
4444                 bnxt_dev_stop_op(bp->eth_dev);
4445
4446         bnxt_uninit_resources(bp, true);
4447 }
4448
4449 static int bnxt_restore_vlan_filters(struct bnxt *bp)
4450 {
4451         struct rte_eth_dev *dev = bp->eth_dev;
4452         struct rte_vlan_filter_conf *vfc;
4453         int vidx, vbit, rc;
4454         uint16_t vlan_id;
4455
4456         for (vlan_id = 1; vlan_id <= RTE_ETHER_MAX_VLAN_ID; vlan_id++) {
4457                 vfc = &dev->data->vlan_filter_conf;
4458                 vidx = vlan_id / 64;
4459                 vbit = vlan_id % 64;
4460
4461                 /* Each bit corresponds to a VLAN id */
4462                 if (vfc->ids[vidx] & (UINT64_C(1) << vbit)) {
4463                         rc = bnxt_add_vlan_filter(bp, vlan_id);
4464                         if (rc)
4465                                 return rc;
4466                 }
4467         }
4468
4469         return 0;
4470 }
4471
4472 static int bnxt_restore_mac_filters(struct bnxt *bp)
4473 {
4474         struct rte_eth_dev *dev = bp->eth_dev;
4475         struct rte_eth_dev_info dev_info;
4476         struct rte_ether_addr *addr;
4477         uint64_t pool_mask;
4478         uint32_t pool = 0;
4479         uint16_t i;
4480         int rc;
4481
4482         if (BNXT_VF(bp) && !BNXT_VF_IS_TRUSTED(bp))
4483                 return 0;
4484
4485         rc = bnxt_dev_info_get_op(dev, &dev_info);
4486         if (rc)
4487                 return rc;
4488
4489         /* replay MAC address configuration */
4490         for (i = 1; i < dev_info.max_mac_addrs; i++) {
4491                 addr = &dev->data->mac_addrs[i];
4492
4493                 /* skip zero address */
4494                 if (rte_is_zero_ether_addr(addr))
4495                         continue;
4496
4497                 pool = 0;
4498                 pool_mask = dev->data->mac_pool_sel[i];
4499
4500                 do {
4501                         if (pool_mask & 1ULL) {
4502                                 rc = bnxt_mac_addr_add_op(dev, addr, i, pool);
4503                                 if (rc)
4504                                         return rc;
4505                         }
4506                         pool_mask >>= 1;
4507                         pool++;
4508                 } while (pool_mask);
4509         }
4510
4511         return 0;
4512 }
4513
4514 static int bnxt_restore_filters(struct bnxt *bp)
4515 {
4516         struct rte_eth_dev *dev = bp->eth_dev;
4517         int ret = 0;
4518
4519         if (dev->data->all_multicast) {
4520                 ret = bnxt_allmulticast_enable_op(dev);
4521                 if (ret)
4522                         return ret;
4523         }
4524         if (dev->data->promiscuous) {
4525                 ret = bnxt_promiscuous_enable_op(dev);
4526                 if (ret)
4527                         return ret;
4528         }
4529
4530         ret = bnxt_restore_mac_filters(bp);
4531         if (ret)
4532                 return ret;
4533
4534         ret = bnxt_restore_vlan_filters(bp);
4535         /* TODO restore other filters as well */
4536         return ret;
4537 }
4538
4539 static void bnxt_dev_recover(void *arg)
4540 {
4541         struct bnxt *bp = arg;
4542         int timeout = bp->fw_reset_max_msecs;
4543         int rc = 0;
4544
4545         /* Clear Error flag so that device re-init should happen */
4546         bp->flags &= ~BNXT_FLAG_FATAL_ERROR;
4547
4548         do {
4549                 rc = bnxt_hwrm_ver_get(bp, SHORT_HWRM_CMD_TIMEOUT);
4550                 if (rc == 0)
4551                         break;
4552                 rte_delay_ms(BNXT_FW_READY_WAIT_INTERVAL);
4553                 timeout -= BNXT_FW_READY_WAIT_INTERVAL;
4554         } while (rc && timeout);
4555
4556         if (rc) {
4557                 PMD_DRV_LOG(ERR, "FW is not Ready after reset\n");
4558                 goto err;
4559         }
4560
4561         rc = bnxt_init_resources(bp, true);
4562         if (rc) {
4563                 PMD_DRV_LOG(ERR,
4564                             "Failed to initialize resources after reset\n");
4565                 goto err;
4566         }
4567         /* clear reset flag as the device is initialized now */
4568         bp->flags &= ~BNXT_FLAG_FW_RESET;
4569
4570         rc = bnxt_dev_start_op(bp->eth_dev);
4571         if (rc) {
4572                 PMD_DRV_LOG(ERR, "Failed to start port after reset\n");
4573                 goto err_start;
4574         }
4575
4576         rc = bnxt_restore_filters(bp);
4577         if (rc)
4578                 goto err_start;
4579
4580         PMD_DRV_LOG(INFO, "Recovered from FW reset\n");
4581         return;
4582 err_start:
4583         bnxt_dev_stop_op(bp->eth_dev);
4584 err:
4585         bp->flags |= BNXT_FLAG_FATAL_ERROR;
4586         bnxt_uninit_resources(bp, false);
4587         PMD_DRV_LOG(ERR, "Failed to recover from FW reset\n");
4588 }
4589
4590 void bnxt_dev_reset_and_resume(void *arg)
4591 {
4592         struct bnxt *bp = arg;
4593         int rc;
4594
4595         bnxt_dev_cleanup(bp);
4596
4597         bnxt_wait_for_device_shutdown(bp);
4598
4599         rc = rte_eal_alarm_set(US_PER_MS * bp->fw_reset_min_msecs,
4600                                bnxt_dev_recover, (void *)bp);
4601         if (rc)
4602                 PMD_DRV_LOG(ERR, "Error setting recovery alarm");
4603 }
4604
4605 uint32_t bnxt_read_fw_status_reg(struct bnxt *bp, uint32_t index)
4606 {
4607         struct bnxt_error_recovery_info *info = bp->recovery_info;
4608         uint32_t reg = info->status_regs[index];
4609         uint32_t type, offset, val = 0;
4610
4611         type = BNXT_FW_STATUS_REG_TYPE(reg);
4612         offset = BNXT_FW_STATUS_REG_OFF(reg);
4613
4614         switch (type) {
4615         case BNXT_FW_STATUS_REG_TYPE_CFG:
4616                 rte_pci_read_config(bp->pdev, &val, sizeof(val), offset);
4617                 break;
4618         case BNXT_FW_STATUS_REG_TYPE_GRC:
4619                 offset = info->mapped_status_regs[index];
4620                 /* FALLTHROUGH */
4621         case BNXT_FW_STATUS_REG_TYPE_BAR0:
4622                 val = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
4623                                        offset));
4624                 break;
4625         }
4626
4627         return val;
4628 }
4629
4630 static int bnxt_fw_reset_all(struct bnxt *bp)
4631 {
4632         struct bnxt_error_recovery_info *info = bp->recovery_info;
4633         uint32_t i;
4634         int rc = 0;
4635
4636         if (info->flags & BNXT_FLAG_ERROR_RECOVERY_HOST) {
4637                 /* Reset through master function driver */
4638                 for (i = 0; i < info->reg_array_cnt; i++)
4639                         bnxt_write_fw_reset_reg(bp, i);
4640                 /* Wait for time specified by FW after triggering reset */
4641                 rte_delay_ms(info->master_func_wait_period_after_reset);
4642         } else if (info->flags & BNXT_FLAG_ERROR_RECOVERY_CO_CPU) {
4643                 /* Reset with the help of Kong processor */
4644                 rc = bnxt_hwrm_fw_reset(bp);
4645                 if (rc)
4646                         PMD_DRV_LOG(ERR, "Failed to reset FW\n");
4647         }
4648
4649         return rc;
4650 }
4651
4652 static void bnxt_fw_reset_cb(void *arg)
4653 {
4654         struct bnxt *bp = arg;
4655         struct bnxt_error_recovery_info *info = bp->recovery_info;
4656         int rc = 0;
4657
4658         /* Only Master function can do FW reset */
4659         if (bnxt_is_master_func(bp) &&
4660             bnxt_is_recovery_enabled(bp)) {
4661                 rc = bnxt_fw_reset_all(bp);
4662                 if (rc) {
4663                         PMD_DRV_LOG(ERR, "Adapter recovery failed\n");
4664                         return;
4665                 }
4666         }
4667
4668         /* if recovery method is ERROR_RECOVERY_CO_CPU, KONG will send
4669          * EXCEPTION_FATAL_ASYNC event to all the functions
4670          * (including MASTER FUNC). After receiving this Async, all the active
4671          * drivers should treat this case as FW initiated recovery
4672          */
4673         if (info->flags & BNXT_FLAG_ERROR_RECOVERY_HOST) {
4674                 bp->fw_reset_min_msecs = BNXT_MIN_FW_READY_TIMEOUT;
4675                 bp->fw_reset_max_msecs = BNXT_MAX_FW_RESET_TIMEOUT;
4676
4677                 /* To recover from error */
4678                 rte_eal_alarm_set(US_PER_MS, bnxt_dev_reset_and_resume,
4679                                   (void *)bp);
4680         }
4681 }
4682
4683 /* Driver should poll FW heartbeat, reset_counter with the frequency
4684  * advertised by FW in HWRM_ERROR_RECOVERY_QCFG.
4685  * When the driver detects heartbeat stop or change in reset_counter,
4686  * it has to trigger a reset to recover from the error condition.
4687  * A “master PF” is the function who will have the privilege to
4688  * initiate the chimp reset. The master PF will be elected by the
4689  * firmware and will be notified through async message.
4690  */
4691 static void bnxt_check_fw_health(void *arg)
4692 {
4693         struct bnxt *bp = arg;
4694         struct bnxt_error_recovery_info *info = bp->recovery_info;
4695         uint32_t val = 0, wait_msec;
4696
4697         if (!info || !bnxt_is_recovery_enabled(bp) ||
4698             is_bnxt_in_error(bp))
4699                 return;
4700
4701         val = bnxt_read_fw_status_reg(bp, BNXT_FW_HEARTBEAT_CNT_REG);
4702         if (val == info->last_heart_beat)
4703                 goto reset;
4704
4705         info->last_heart_beat = val;
4706
4707         val = bnxt_read_fw_status_reg(bp, BNXT_FW_RECOVERY_CNT_REG);
4708         if (val != info->last_reset_counter)
4709                 goto reset;
4710
4711         info->last_reset_counter = val;
4712
4713         rte_eal_alarm_set(US_PER_MS * info->driver_polling_freq,
4714                           bnxt_check_fw_health, (void *)bp);
4715
4716         return;
4717 reset:
4718         /* Stop DMA to/from device */
4719         bp->flags |= BNXT_FLAG_FATAL_ERROR;
4720         bp->flags |= BNXT_FLAG_FW_RESET;
4721
4722         PMD_DRV_LOG(ERR, "Detected FW dead condition\n");
4723
4724         if (bnxt_is_master_func(bp))
4725                 wait_msec = info->master_func_wait_period;
4726         else
4727                 wait_msec = info->normal_func_wait_period;
4728
4729         rte_eal_alarm_set(US_PER_MS * wait_msec,
4730                           bnxt_fw_reset_cb, (void *)bp);
4731 }
4732
4733 void bnxt_schedule_fw_health_check(struct bnxt *bp)
4734 {
4735         uint32_t polling_freq;
4736
4737         pthread_mutex_lock(&bp->health_check_lock);
4738
4739         if (!bnxt_is_recovery_enabled(bp))
4740                 goto done;
4741
4742         if (bp->flags & BNXT_FLAG_FW_HEALTH_CHECK_SCHEDULED)
4743                 goto done;
4744
4745         polling_freq = bp->recovery_info->driver_polling_freq;
4746
4747         rte_eal_alarm_set(US_PER_MS * polling_freq,
4748                           bnxt_check_fw_health, (void *)bp);
4749         bp->flags |= BNXT_FLAG_FW_HEALTH_CHECK_SCHEDULED;
4750
4751 done:
4752         pthread_mutex_unlock(&bp->health_check_lock);
4753 }
4754
4755 static void bnxt_cancel_fw_health_check(struct bnxt *bp)
4756 {
4757         if (!bnxt_is_recovery_enabled(bp))
4758                 return;
4759
4760         rte_eal_alarm_cancel(bnxt_check_fw_health, (void *)bp);
4761         bp->flags &= ~BNXT_FLAG_FW_HEALTH_CHECK_SCHEDULED;
4762 }
4763
4764 static bool bnxt_vf_pciid(uint16_t device_id)
4765 {
4766         switch (device_id) {
4767         case BROADCOM_DEV_ID_57304_VF:
4768         case BROADCOM_DEV_ID_57406_VF:
4769         case BROADCOM_DEV_ID_5731X_VF:
4770         case BROADCOM_DEV_ID_5741X_VF:
4771         case BROADCOM_DEV_ID_57414_VF:
4772         case BROADCOM_DEV_ID_STRATUS_NIC_VF1:
4773         case BROADCOM_DEV_ID_STRATUS_NIC_VF2:
4774         case BROADCOM_DEV_ID_58802_VF:
4775         case BROADCOM_DEV_ID_57500_VF1:
4776         case BROADCOM_DEV_ID_57500_VF2:
4777                 /* FALLTHROUGH */
4778                 return true;
4779         default:
4780                 return false;
4781         }
4782 }
4783
4784 static bool bnxt_thor_device(uint16_t device_id)
4785 {
4786         switch (device_id) {
4787         case BROADCOM_DEV_ID_57508:
4788         case BROADCOM_DEV_ID_57504:
4789         case BROADCOM_DEV_ID_57502:
4790         case BROADCOM_DEV_ID_57508_MF1:
4791         case BROADCOM_DEV_ID_57504_MF1:
4792         case BROADCOM_DEV_ID_57502_MF1:
4793         case BROADCOM_DEV_ID_57508_MF2:
4794         case BROADCOM_DEV_ID_57504_MF2:
4795         case BROADCOM_DEV_ID_57502_MF2:
4796         case BROADCOM_DEV_ID_57500_VF1:
4797         case BROADCOM_DEV_ID_57500_VF2:
4798                 /* FALLTHROUGH */
4799                 return true;
4800         default:
4801                 return false;
4802         }
4803 }
4804
4805 bool bnxt_stratus_device(struct bnxt *bp)
4806 {
4807         uint16_t device_id = bp->pdev->id.device_id;
4808
4809         switch (device_id) {
4810         case BROADCOM_DEV_ID_STRATUS_NIC:
4811         case BROADCOM_DEV_ID_STRATUS_NIC_VF1:
4812         case BROADCOM_DEV_ID_STRATUS_NIC_VF2:
4813                 /* FALLTHROUGH */
4814                 return true;
4815         default:
4816                 return false;
4817         }
4818 }
4819
4820 static int bnxt_init_board(struct rte_eth_dev *eth_dev)
4821 {
4822         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
4823         struct bnxt *bp = eth_dev->data->dev_private;
4824
4825         /* enable device (incl. PCI PM wakeup), and bus-mastering */
4826         bp->bar0 = (void *)pci_dev->mem_resource[0].addr;
4827         bp->doorbell_base = (void *)pci_dev->mem_resource[2].addr;
4828         if (!bp->bar0 || !bp->doorbell_base) {
4829                 PMD_DRV_LOG(ERR, "Unable to access Hardware\n");
4830                 return -ENODEV;
4831         }
4832
4833         bp->eth_dev = eth_dev;
4834         bp->pdev = pci_dev;
4835
4836         return 0;
4837 }
4838
4839 static int bnxt_alloc_ctx_mem_blk(struct bnxt *bp,
4840                                   struct bnxt_ctx_pg_info *ctx_pg,
4841                                   uint32_t mem_size,
4842                                   const char *suffix,
4843                                   uint16_t idx)
4844 {
4845         struct bnxt_ring_mem_info *rmem = &ctx_pg->ring_mem;
4846         const struct rte_memzone *mz = NULL;
4847         char mz_name[RTE_MEMZONE_NAMESIZE];
4848         rte_iova_t mz_phys_addr;
4849         uint64_t valid_bits = 0;
4850         uint32_t sz;
4851         int i;
4852
4853         if (!mem_size)
4854                 return 0;
4855
4856         rmem->nr_pages = RTE_ALIGN_MUL_CEIL(mem_size, BNXT_PAGE_SIZE) /
4857                          BNXT_PAGE_SIZE;
4858         rmem->page_size = BNXT_PAGE_SIZE;
4859         rmem->pg_arr = ctx_pg->ctx_pg_arr;
4860         rmem->dma_arr = ctx_pg->ctx_dma_arr;
4861         rmem->flags = BNXT_RMEM_VALID_PTE_FLAG;
4862
4863         valid_bits = PTU_PTE_VALID;
4864
4865         if (rmem->nr_pages > 1) {
4866                 snprintf(mz_name, RTE_MEMZONE_NAMESIZE,
4867                          "bnxt_ctx_pg_tbl%s_%x_%d",
4868                          suffix, idx, bp->eth_dev->data->port_id);
4869                 mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0;
4870                 mz = rte_memzone_lookup(mz_name);
4871                 if (!mz) {
4872                         mz = rte_memzone_reserve_aligned(mz_name,
4873                                                 rmem->nr_pages * 8,
4874                                                 SOCKET_ID_ANY,
4875                                                 RTE_MEMZONE_2MB |
4876                                                 RTE_MEMZONE_SIZE_HINT_ONLY |
4877                                                 RTE_MEMZONE_IOVA_CONTIG,
4878                                                 BNXT_PAGE_SIZE);
4879                         if (mz == NULL)
4880                                 return -ENOMEM;
4881                 }
4882
4883                 memset(mz->addr, 0, mz->len);
4884                 mz_phys_addr = mz->iova;
4885
4886                 rmem->pg_tbl = mz->addr;
4887                 rmem->pg_tbl_map = mz_phys_addr;
4888                 rmem->pg_tbl_mz = mz;
4889         }
4890
4891         snprintf(mz_name, RTE_MEMZONE_NAMESIZE, "bnxt_ctx_%s_%x_%d",
4892                  suffix, idx, bp->eth_dev->data->port_id);
4893         mz = rte_memzone_lookup(mz_name);
4894         if (!mz) {
4895                 mz = rte_memzone_reserve_aligned(mz_name,
4896                                                  mem_size,
4897                                                  SOCKET_ID_ANY,
4898                                                  RTE_MEMZONE_1GB |
4899                                                  RTE_MEMZONE_SIZE_HINT_ONLY |
4900                                                  RTE_MEMZONE_IOVA_CONTIG,
4901                                                  BNXT_PAGE_SIZE);
4902                 if (mz == NULL)
4903                         return -ENOMEM;
4904         }
4905
4906         memset(mz->addr, 0, mz->len);
4907         mz_phys_addr = mz->iova;
4908
4909         for (sz = 0, i = 0; sz < mem_size; sz += BNXT_PAGE_SIZE, i++) {
4910                 rmem->pg_arr[i] = ((char *)mz->addr) + sz;
4911                 rmem->dma_arr[i] = mz_phys_addr + sz;
4912
4913                 if (rmem->nr_pages > 1) {
4914                         if (i == rmem->nr_pages - 2 &&
4915                             (rmem->flags & BNXT_RMEM_RING_PTE_FLAG))
4916                                 valid_bits |= PTU_PTE_NEXT_TO_LAST;
4917                         else if (i == rmem->nr_pages - 1 &&
4918                                  (rmem->flags & BNXT_RMEM_RING_PTE_FLAG))
4919                                 valid_bits |= PTU_PTE_LAST;
4920
4921                         rmem->pg_tbl[i] = rte_cpu_to_le_64(rmem->dma_arr[i] |
4922                                                            valid_bits);
4923                 }
4924         }
4925
4926         rmem->mz = mz;
4927         if (rmem->vmem_size)
4928                 rmem->vmem = (void **)mz->addr;
4929         rmem->dma_arr[0] = mz_phys_addr;
4930         return 0;
4931 }
4932
4933 static void bnxt_free_ctx_mem(struct bnxt *bp)
4934 {
4935         int i;
4936
4937         if (!bp->ctx || !(bp->ctx->flags & BNXT_CTX_FLAG_INITED))
4938                 return;
4939
4940         bp->ctx->flags &= ~BNXT_CTX_FLAG_INITED;
4941         rte_memzone_free(bp->ctx->qp_mem.ring_mem.mz);
4942         rte_memzone_free(bp->ctx->srq_mem.ring_mem.mz);
4943         rte_memzone_free(bp->ctx->cq_mem.ring_mem.mz);
4944         rte_memzone_free(bp->ctx->vnic_mem.ring_mem.mz);
4945         rte_memzone_free(bp->ctx->stat_mem.ring_mem.mz);
4946         rte_memzone_free(bp->ctx->qp_mem.ring_mem.pg_tbl_mz);
4947         rte_memzone_free(bp->ctx->srq_mem.ring_mem.pg_tbl_mz);
4948         rte_memzone_free(bp->ctx->cq_mem.ring_mem.pg_tbl_mz);
4949         rte_memzone_free(bp->ctx->vnic_mem.ring_mem.pg_tbl_mz);
4950         rte_memzone_free(bp->ctx->stat_mem.ring_mem.pg_tbl_mz);
4951
4952         for (i = 0; i < bp->ctx->tqm_fp_rings_count + 1; i++) {
4953                 if (bp->ctx->tqm_mem[i])
4954                         rte_memzone_free(bp->ctx->tqm_mem[i]->ring_mem.mz);
4955         }
4956
4957         rte_free(bp->ctx);
4958         bp->ctx = NULL;
4959 }
4960
4961 #define bnxt_roundup(x, y)   ((((x) + ((y) - 1)) / (y)) * (y))
4962
4963 #define min_t(type, x, y) ({                    \
4964         type __min1 = (x);                      \
4965         type __min2 = (y);                      \
4966         __min1 < __min2 ? __min1 : __min2; })
4967
4968 #define max_t(type, x, y) ({                    \
4969         type __max1 = (x);                      \
4970         type __max2 = (y);                      \
4971         __max1 > __max2 ? __max1 : __max2; })
4972
4973 #define clamp_t(type, _x, min, max)     min_t(type, max_t(type, _x, min), max)
4974
4975 int bnxt_alloc_ctx_mem(struct bnxt *bp)
4976 {
4977         struct bnxt_ctx_pg_info *ctx_pg;
4978         struct bnxt_ctx_mem_info *ctx;
4979         uint32_t mem_size, ena, entries;
4980         uint32_t entries_sp, min;
4981         int i, rc;
4982
4983         rc = bnxt_hwrm_func_backing_store_qcaps(bp);
4984         if (rc) {
4985                 PMD_DRV_LOG(ERR, "Query context mem capability failed\n");
4986                 return rc;
4987         }
4988         ctx = bp->ctx;
4989         if (!ctx || (ctx->flags & BNXT_CTX_FLAG_INITED))
4990                 return 0;
4991
4992         ctx_pg = &ctx->qp_mem;
4993         ctx_pg->entries = ctx->qp_min_qp1_entries + ctx->qp_max_l2_entries;
4994         mem_size = ctx->qp_entry_size * ctx_pg->entries;
4995         rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "qp_mem", 0);
4996         if (rc)
4997                 return rc;
4998
4999         ctx_pg = &ctx->srq_mem;
5000         ctx_pg->entries = ctx->srq_max_l2_entries;
5001         mem_size = ctx->srq_entry_size * ctx_pg->entries;
5002         rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "srq_mem", 0);
5003         if (rc)
5004                 return rc;
5005
5006         ctx_pg = &ctx->cq_mem;
5007         ctx_pg->entries = ctx->cq_max_l2_entries;
5008         mem_size = ctx->cq_entry_size * ctx_pg->entries;
5009         rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "cq_mem", 0);
5010         if (rc)
5011                 return rc;
5012
5013         ctx_pg = &ctx->vnic_mem;
5014         ctx_pg->entries = ctx->vnic_max_vnic_entries +
5015                 ctx->vnic_max_ring_table_entries;
5016         mem_size = ctx->vnic_entry_size * ctx_pg->entries;
5017         rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "vnic_mem", 0);
5018         if (rc)
5019                 return rc;
5020
5021         ctx_pg = &ctx->stat_mem;
5022         ctx_pg->entries = ctx->stat_max_entries;
5023         mem_size = ctx->stat_entry_size * ctx_pg->entries;
5024         rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "stat_mem", 0);
5025         if (rc)
5026                 return rc;
5027
5028         min = ctx->tqm_min_entries_per_ring;
5029
5030         entries_sp = ctx->qp_max_l2_entries +
5031                      ctx->vnic_max_vnic_entries +
5032                      2 * ctx->qp_min_qp1_entries + min;
5033         entries_sp = bnxt_roundup(entries_sp, ctx->tqm_entries_multiple);
5034
5035         entries = ctx->qp_max_l2_entries + ctx->qp_min_qp1_entries;
5036         entries = bnxt_roundup(entries, ctx->tqm_entries_multiple);
5037         entries = clamp_t(uint32_t, entries, min,
5038                           ctx->tqm_max_entries_per_ring);
5039         for (i = 0, ena = 0; i < ctx->tqm_fp_rings_count + 1; i++) {
5040                 ctx_pg = ctx->tqm_mem[i];
5041                 ctx_pg->entries = i ? entries : entries_sp;
5042                 mem_size = ctx->tqm_entry_size * ctx_pg->entries;
5043                 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "tqm_mem", i);
5044                 if (rc)
5045                         return rc;
5046                 ena |= HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_SP << i;
5047         }
5048
5049         ena |= FUNC_BACKING_STORE_CFG_INPUT_DFLT_ENABLES;
5050         rc = bnxt_hwrm_func_backing_store_cfg(bp, ena);
5051         if (rc)
5052                 PMD_DRV_LOG(ERR,
5053                             "Failed to configure context mem: rc = %d\n", rc);
5054         else
5055                 ctx->flags |= BNXT_CTX_FLAG_INITED;
5056
5057         return rc;
5058 }
5059
5060 static int bnxt_alloc_stats_mem(struct bnxt *bp)
5061 {
5062         struct rte_pci_device *pci_dev = bp->pdev;
5063         char mz_name[RTE_MEMZONE_NAMESIZE];
5064         const struct rte_memzone *mz = NULL;
5065         uint32_t total_alloc_len;
5066         rte_iova_t mz_phys_addr;
5067
5068         if (pci_dev->id.device_id == BROADCOM_DEV_ID_NS2)
5069                 return 0;
5070
5071         snprintf(mz_name, RTE_MEMZONE_NAMESIZE,
5072                  "bnxt_" PCI_PRI_FMT "-%s", pci_dev->addr.domain,
5073                  pci_dev->addr.bus, pci_dev->addr.devid,
5074                  pci_dev->addr.function, "rx_port_stats");
5075         mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0;
5076         mz = rte_memzone_lookup(mz_name);
5077         total_alloc_len =
5078                 RTE_CACHE_LINE_ROUNDUP(sizeof(struct rx_port_stats) +
5079                                        sizeof(struct rx_port_stats_ext) + 512);
5080         if (!mz) {
5081                 mz = rte_memzone_reserve(mz_name, total_alloc_len,
5082                                          SOCKET_ID_ANY,
5083                                          RTE_MEMZONE_2MB |
5084                                          RTE_MEMZONE_SIZE_HINT_ONLY |
5085                                          RTE_MEMZONE_IOVA_CONTIG);
5086                 if (mz == NULL)
5087                         return -ENOMEM;
5088         }
5089         memset(mz->addr, 0, mz->len);
5090         mz_phys_addr = mz->iova;
5091
5092         bp->rx_mem_zone = (const void *)mz;
5093         bp->hw_rx_port_stats = mz->addr;
5094         bp->hw_rx_port_stats_map = mz_phys_addr;
5095
5096         snprintf(mz_name, RTE_MEMZONE_NAMESIZE,
5097                  "bnxt_" PCI_PRI_FMT "-%s", pci_dev->addr.domain,
5098                  pci_dev->addr.bus, pci_dev->addr.devid,
5099                  pci_dev->addr.function, "tx_port_stats");
5100         mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0;
5101         mz = rte_memzone_lookup(mz_name);
5102         total_alloc_len =
5103                 RTE_CACHE_LINE_ROUNDUP(sizeof(struct tx_port_stats) +
5104                                        sizeof(struct tx_port_stats_ext) + 512);
5105         if (!mz) {
5106                 mz = rte_memzone_reserve(mz_name,
5107                                          total_alloc_len,
5108                                          SOCKET_ID_ANY,
5109                                          RTE_MEMZONE_2MB |
5110                                          RTE_MEMZONE_SIZE_HINT_ONLY |
5111                                          RTE_MEMZONE_IOVA_CONTIG);
5112                 if (mz == NULL)
5113                         return -ENOMEM;
5114         }
5115         memset(mz->addr, 0, mz->len);
5116         mz_phys_addr = mz->iova;
5117
5118         bp->tx_mem_zone = (const void *)mz;
5119         bp->hw_tx_port_stats = mz->addr;
5120         bp->hw_tx_port_stats_map = mz_phys_addr;
5121         bp->flags |= BNXT_FLAG_PORT_STATS;
5122
5123         /* Display extended statistics if FW supports it */
5124         if (bp->hwrm_spec_code < HWRM_SPEC_CODE_1_8_4 ||
5125             bp->hwrm_spec_code == HWRM_SPEC_CODE_1_9_0 ||
5126             !(bp->flags & BNXT_FLAG_EXT_STATS_SUPPORTED))
5127                 return 0;
5128
5129         bp->hw_rx_port_stats_ext = (void *)
5130                 ((uint8_t *)bp->hw_rx_port_stats +
5131                  sizeof(struct rx_port_stats));
5132         bp->hw_rx_port_stats_ext_map = bp->hw_rx_port_stats_map +
5133                 sizeof(struct rx_port_stats);
5134         bp->flags |= BNXT_FLAG_EXT_RX_PORT_STATS;
5135
5136         if (bp->hwrm_spec_code < HWRM_SPEC_CODE_1_9_2 ||
5137             bp->flags & BNXT_FLAG_EXT_STATS_SUPPORTED) {
5138                 bp->hw_tx_port_stats_ext = (void *)
5139                         ((uint8_t *)bp->hw_tx_port_stats +
5140                          sizeof(struct tx_port_stats));
5141                 bp->hw_tx_port_stats_ext_map =
5142                         bp->hw_tx_port_stats_map +
5143                         sizeof(struct tx_port_stats);
5144                 bp->flags |= BNXT_FLAG_EXT_TX_PORT_STATS;
5145         }
5146
5147         return 0;
5148 }
5149
5150 static int bnxt_setup_mac_addr(struct rte_eth_dev *eth_dev)
5151 {
5152         struct bnxt *bp = eth_dev->data->dev_private;
5153         int rc = 0;
5154
5155         eth_dev->data->mac_addrs = rte_zmalloc("bnxt_mac_addr_tbl",
5156                                                RTE_ETHER_ADDR_LEN *
5157                                                bp->max_l2_ctx,
5158                                                0);
5159         if (eth_dev->data->mac_addrs == NULL) {
5160                 PMD_DRV_LOG(ERR, "Failed to alloc MAC addr tbl\n");
5161                 return -ENOMEM;
5162         }
5163
5164         if (!BNXT_HAS_DFLT_MAC_SET(bp)) {
5165                 if (BNXT_PF(bp))
5166                         return -EINVAL;
5167
5168                 /* Generate a random MAC address, if none was assigned by PF */
5169                 PMD_DRV_LOG(INFO, "VF MAC address not assigned by Host PF\n");
5170                 bnxt_eth_hw_addr_random(bp->mac_addr);
5171                 PMD_DRV_LOG(INFO,
5172                             "Assign random MAC:%02X:%02X:%02X:%02X:%02X:%02X\n",
5173                             bp->mac_addr[0], bp->mac_addr[1], bp->mac_addr[2],
5174                             bp->mac_addr[3], bp->mac_addr[4], bp->mac_addr[5]);
5175
5176                 rc = bnxt_hwrm_set_mac(bp);
5177                 if (rc)
5178                         return rc;
5179         }
5180
5181         /* Copy the permanent MAC from the FUNC_QCAPS response */
5182         memcpy(&eth_dev->data->mac_addrs[0], bp->mac_addr, RTE_ETHER_ADDR_LEN);
5183
5184         return rc;
5185 }
5186
5187 static int bnxt_restore_dflt_mac(struct bnxt *bp)
5188 {
5189         int rc = 0;
5190
5191         /* MAC is already configured in FW */
5192         if (BNXT_HAS_DFLT_MAC_SET(bp))
5193                 return 0;
5194
5195         /* Restore the old MAC configured */
5196         rc = bnxt_hwrm_set_mac(bp);
5197         if (rc)
5198                 PMD_DRV_LOG(ERR, "Failed to restore MAC address\n");
5199
5200         return rc;
5201 }
5202
5203 static void bnxt_config_vf_req_fwd(struct bnxt *bp)
5204 {
5205         if (!BNXT_PF(bp))
5206                 return;
5207
5208         memset(bp->pf->vf_req_fwd, 0, sizeof(bp->pf->vf_req_fwd));
5209
5210         if (!(bp->fw_cap & BNXT_FW_CAP_LINK_ADMIN))
5211                 BNXT_HWRM_CMD_TO_FORWARD(HWRM_PORT_PHY_QCFG);
5212         BNXT_HWRM_CMD_TO_FORWARD(HWRM_FUNC_CFG);
5213         BNXT_HWRM_CMD_TO_FORWARD(HWRM_FUNC_VF_CFG);
5214         BNXT_HWRM_CMD_TO_FORWARD(HWRM_CFA_L2_FILTER_ALLOC);
5215         BNXT_HWRM_CMD_TO_FORWARD(HWRM_OEM_CMD);
5216 }
5217
5218 uint16_t
5219 bnxt_get_svif(uint16_t port_id, bool func_svif,
5220               enum bnxt_ulp_intf_type type)
5221 {
5222         struct rte_eth_dev *eth_dev;
5223         struct bnxt *bp;
5224
5225         eth_dev = &rte_eth_devices[port_id];
5226         if (BNXT_ETH_DEV_IS_REPRESENTOR(eth_dev)) {
5227                 struct bnxt_representor *vfr = eth_dev->data->dev_private;
5228                 if (!vfr)
5229                         return 0;
5230
5231                 if (type == BNXT_ULP_INTF_TYPE_VF_REP)
5232                         return vfr->svif;
5233
5234                 eth_dev = vfr->parent_dev;
5235         }
5236
5237         bp = eth_dev->data->dev_private;
5238
5239         return func_svif ? bp->func_svif : bp->port_svif;
5240 }
5241
5242 uint16_t
5243 bnxt_get_vnic_id(uint16_t port, enum bnxt_ulp_intf_type type)
5244 {
5245         struct rte_eth_dev *eth_dev;
5246         struct bnxt_vnic_info *vnic;
5247         struct bnxt *bp;
5248
5249         eth_dev = &rte_eth_devices[port];
5250         if (BNXT_ETH_DEV_IS_REPRESENTOR(eth_dev)) {
5251                 struct bnxt_representor *vfr = eth_dev->data->dev_private;
5252                 if (!vfr)
5253                         return 0;
5254
5255                 if (type == BNXT_ULP_INTF_TYPE_VF_REP)
5256                         return vfr->dflt_vnic_id;
5257
5258                 eth_dev = vfr->parent_dev;
5259         }
5260
5261         bp = eth_dev->data->dev_private;
5262
5263         vnic = BNXT_GET_DEFAULT_VNIC(bp);
5264
5265         return vnic->fw_vnic_id;
5266 }
5267
5268 uint16_t
5269 bnxt_get_fw_func_id(uint16_t port, enum bnxt_ulp_intf_type type)
5270 {
5271         struct rte_eth_dev *eth_dev;
5272         struct bnxt *bp;
5273
5274         eth_dev = &rte_eth_devices[port];
5275         if (BNXT_ETH_DEV_IS_REPRESENTOR(eth_dev)) {
5276                 struct bnxt_representor *vfr = eth_dev->data->dev_private;
5277                 if (!vfr)
5278                         return 0;
5279
5280                 if (type == BNXT_ULP_INTF_TYPE_VF_REP)
5281                         return vfr->fw_fid;
5282
5283                 eth_dev = vfr->parent_dev;
5284         }
5285
5286         bp = eth_dev->data->dev_private;
5287
5288         return bp->fw_fid;
5289 }
5290
5291 enum bnxt_ulp_intf_type
5292 bnxt_get_interface_type(uint16_t port)
5293 {
5294         struct rte_eth_dev *eth_dev;
5295         struct bnxt *bp;
5296
5297         eth_dev = &rte_eth_devices[port];
5298         if (BNXT_ETH_DEV_IS_REPRESENTOR(eth_dev))
5299                 return BNXT_ULP_INTF_TYPE_VF_REP;
5300
5301         bp = eth_dev->data->dev_private;
5302         if (BNXT_PF(bp))
5303                 return BNXT_ULP_INTF_TYPE_PF;
5304         else if (BNXT_VF_IS_TRUSTED(bp))
5305                 return BNXT_ULP_INTF_TYPE_TRUSTED_VF;
5306         else if (BNXT_VF(bp))
5307                 return BNXT_ULP_INTF_TYPE_VF;
5308
5309         return BNXT_ULP_INTF_TYPE_INVALID;
5310 }
5311
5312 uint16_t
5313 bnxt_get_phy_port_id(uint16_t port_id)
5314 {
5315         struct bnxt_representor *vfr;
5316         struct rte_eth_dev *eth_dev;
5317         struct bnxt *bp;
5318
5319         eth_dev = &rte_eth_devices[port_id];
5320         if (BNXT_ETH_DEV_IS_REPRESENTOR(eth_dev)) {
5321                 vfr = eth_dev->data->dev_private;
5322                 if (!vfr)
5323                         return 0;
5324
5325                 eth_dev = vfr->parent_dev;
5326         }
5327
5328         bp = eth_dev->data->dev_private;
5329
5330         return BNXT_PF(bp) ? bp->pf->port_id : bp->parent->port_id;
5331 }
5332
5333 uint16_t
5334 bnxt_get_parif(uint16_t port_id, enum bnxt_ulp_intf_type type)
5335 {
5336         struct rte_eth_dev *eth_dev;
5337         struct bnxt *bp;
5338
5339         eth_dev = &rte_eth_devices[port_id];
5340         if (BNXT_ETH_DEV_IS_REPRESENTOR(eth_dev)) {
5341                 struct bnxt_representor *vfr = eth_dev->data->dev_private;
5342                 if (!vfr)
5343                         return 0;
5344
5345                 if (type == BNXT_ULP_INTF_TYPE_VF_REP)
5346                         return vfr->fw_fid - 1;
5347
5348                 eth_dev = vfr->parent_dev;
5349         }
5350
5351         bp = eth_dev->data->dev_private;
5352
5353         return BNXT_PF(bp) ? bp->fw_fid - 1 : bp->parent->fid - 1;
5354 }
5355
5356 uint16_t
5357 bnxt_get_vport(uint16_t port_id)
5358 {
5359         return (1 << bnxt_get_phy_port_id(port_id));
5360 }
5361
5362 static void bnxt_alloc_error_recovery_info(struct bnxt *bp)
5363 {
5364         struct bnxt_error_recovery_info *info = bp->recovery_info;
5365
5366         if (info) {
5367                 if (!(bp->fw_cap & BNXT_FW_CAP_HCOMM_FW_STATUS))
5368                         memset(info, 0, sizeof(*info));
5369                 return;
5370         }
5371
5372         if (!(bp->fw_cap & BNXT_FW_CAP_ERROR_RECOVERY))
5373                 return;
5374
5375         info = rte_zmalloc("bnxt_hwrm_error_recovery_qcfg",
5376                            sizeof(*info), 0);
5377         if (!info)
5378                 bp->fw_cap &= ~BNXT_FW_CAP_ERROR_RECOVERY;
5379
5380         bp->recovery_info = info;
5381 }
5382
5383 static void bnxt_check_fw_status(struct bnxt *bp)
5384 {
5385         uint32_t fw_status;
5386
5387         if (!(bp->recovery_info &&
5388               (bp->fw_cap & BNXT_FW_CAP_HCOMM_FW_STATUS)))
5389                 return;
5390
5391         fw_status = bnxt_read_fw_status_reg(bp, BNXT_FW_STATUS_REG);
5392         if (fw_status != BNXT_FW_STATUS_HEALTHY)
5393                 PMD_DRV_LOG(ERR, "Firmware not responding, status: %#x\n",
5394                             fw_status);
5395 }
5396
5397 static int bnxt_map_hcomm_fw_status_reg(struct bnxt *bp)
5398 {
5399         struct bnxt_error_recovery_info *info = bp->recovery_info;
5400         uint32_t status_loc;
5401         uint32_t sig_ver;
5402
5403         rte_write32(HCOMM_STATUS_STRUCT_LOC, (uint8_t *)bp->bar0 +
5404                     BNXT_GRCPF_REG_WINDOW_BASE_OUT + 4);
5405         sig_ver = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
5406                                    BNXT_GRCP_WINDOW_2_BASE +
5407                                    offsetof(struct hcomm_status,
5408                                             sig_ver)));
5409         /* If the signature is absent, then FW does not support this feature */
5410         if ((sig_ver & HCOMM_STATUS_SIGNATURE_MASK) !=
5411             HCOMM_STATUS_SIGNATURE_VAL)
5412                 return 0;
5413
5414         if (!info) {
5415                 info = rte_zmalloc("bnxt_hwrm_error_recovery_qcfg",
5416                                    sizeof(*info), 0);
5417                 if (!info)
5418                         return -ENOMEM;
5419                 bp->recovery_info = info;
5420         } else {
5421                 memset(info, 0, sizeof(*info));
5422         }
5423
5424         status_loc = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
5425                                       BNXT_GRCP_WINDOW_2_BASE +
5426                                       offsetof(struct hcomm_status,
5427                                                fw_status_loc)));
5428
5429         /* Only pre-map the FW health status GRC register */
5430         if (BNXT_FW_STATUS_REG_TYPE(status_loc) != BNXT_FW_STATUS_REG_TYPE_GRC)
5431                 return 0;
5432
5433         info->status_regs[BNXT_FW_STATUS_REG] = status_loc;
5434         info->mapped_status_regs[BNXT_FW_STATUS_REG] =
5435                 BNXT_GRCP_WINDOW_2_BASE + (status_loc & BNXT_GRCP_OFFSET_MASK);
5436
5437         rte_write32((status_loc & BNXT_GRCP_BASE_MASK), (uint8_t *)bp->bar0 +
5438                     BNXT_GRCPF_REG_WINDOW_BASE_OUT + 4);
5439
5440         bp->fw_cap |= BNXT_FW_CAP_HCOMM_FW_STATUS;
5441
5442         return 0;
5443 }
5444
5445 static int bnxt_init_fw(struct bnxt *bp)
5446 {
5447         uint16_t mtu;
5448         int rc = 0;
5449
5450         bp->fw_cap = 0;
5451
5452         rc = bnxt_map_hcomm_fw_status_reg(bp);
5453         if (rc)
5454                 return rc;
5455
5456         rc = bnxt_hwrm_ver_get(bp, DFLT_HWRM_CMD_TIMEOUT);
5457         if (rc) {
5458                 bnxt_check_fw_status(bp);
5459                 return rc;
5460         }
5461
5462         rc = bnxt_hwrm_func_reset(bp);
5463         if (rc)
5464                 return -EIO;
5465
5466         rc = bnxt_hwrm_vnic_qcaps(bp);
5467         if (rc)
5468                 return rc;
5469
5470         rc = bnxt_hwrm_queue_qportcfg(bp);
5471         if (rc)
5472                 return rc;
5473
5474         /* Get the MAX capabilities for this function.
5475          * This function also allocates context memory for TQM rings and
5476          * informs the firmware about this allocated backing store memory.
5477          */
5478         rc = bnxt_hwrm_func_qcaps(bp);
5479         if (rc)
5480                 return rc;
5481
5482         rc = bnxt_hwrm_func_qcfg(bp, &mtu);
5483         if (rc)
5484                 return rc;
5485
5486         bnxt_hwrm_port_mac_qcfg(bp);
5487
5488         bnxt_hwrm_parent_pf_qcfg(bp);
5489
5490         bnxt_hwrm_port_phy_qcaps(bp);
5491
5492         bnxt_alloc_error_recovery_info(bp);
5493         /* Get the adapter error recovery support info */
5494         rc = bnxt_hwrm_error_recovery_qcfg(bp);
5495         if (rc)
5496                 bp->fw_cap &= ~BNXT_FW_CAP_ERROR_RECOVERY;
5497
5498         bnxt_hwrm_port_led_qcaps(bp);
5499
5500         return 0;
5501 }
5502
5503 static int
5504 bnxt_init_locks(struct bnxt *bp)
5505 {
5506         int err;
5507
5508         err = pthread_mutex_init(&bp->flow_lock, NULL);
5509         if (err) {
5510                 PMD_DRV_LOG(ERR, "Unable to initialize flow_lock\n");
5511                 return err;
5512         }
5513
5514         err = pthread_mutex_init(&bp->def_cp_lock, NULL);
5515         if (err)
5516                 PMD_DRV_LOG(ERR, "Unable to initialize def_cp_lock\n");
5517
5518         err = pthread_mutex_init(&bp->health_check_lock, NULL);
5519         if (err)
5520                 PMD_DRV_LOG(ERR, "Unable to initialize health_check_lock\n");
5521         return err;
5522 }
5523
5524 static int bnxt_init_resources(struct bnxt *bp, bool reconfig_dev)
5525 {
5526         int rc = 0;
5527
5528         rc = bnxt_init_fw(bp);
5529         if (rc)
5530                 return rc;
5531
5532         if (!reconfig_dev) {
5533                 rc = bnxt_setup_mac_addr(bp->eth_dev);
5534                 if (rc)
5535                         return rc;
5536         } else {
5537                 rc = bnxt_restore_dflt_mac(bp);
5538                 if (rc)
5539                         return rc;
5540         }
5541
5542         bnxt_config_vf_req_fwd(bp);
5543
5544         rc = bnxt_hwrm_func_driver_register(bp);
5545         if (rc) {
5546                 PMD_DRV_LOG(ERR, "Failed to register driver");
5547                 return -EBUSY;
5548         }
5549
5550         if (BNXT_PF(bp)) {
5551                 if (bp->pdev->max_vfs) {
5552                         rc = bnxt_hwrm_allocate_vfs(bp, bp->pdev->max_vfs);
5553                         if (rc) {
5554                                 PMD_DRV_LOG(ERR, "Failed to allocate VFs\n");
5555                                 return rc;
5556                         }
5557                 } else {
5558                         rc = bnxt_hwrm_allocate_pf_only(bp);
5559                         if (rc) {
5560                                 PMD_DRV_LOG(ERR,
5561                                             "Failed to allocate PF resources");
5562                                 return rc;
5563                         }
5564                 }
5565         }
5566
5567         rc = bnxt_alloc_mem(bp, reconfig_dev);
5568         if (rc)
5569                 return rc;
5570
5571         rc = bnxt_setup_int(bp);
5572         if (rc)
5573                 return rc;
5574
5575         rc = bnxt_request_int(bp);
5576         if (rc)
5577                 return rc;
5578
5579         rc = bnxt_init_ctx_mem(bp);
5580         if (rc) {
5581                 PMD_DRV_LOG(ERR, "Failed to init adv_flow_counters\n");
5582                 return rc;
5583         }
5584
5585         rc = bnxt_init_locks(bp);
5586         if (rc)
5587                 return rc;
5588
5589         return 0;
5590 }
5591
5592 static int
5593 bnxt_parse_devarg_truflow(__rte_unused const char *key,
5594                           const char *value, void *opaque_arg)
5595 {
5596         struct bnxt *bp = opaque_arg;
5597         unsigned long truflow;
5598         char *end = NULL;
5599
5600         if (!value || !opaque_arg) {
5601                 PMD_DRV_LOG(ERR,
5602                             "Invalid parameter passed to truflow devargs.\n");
5603                 return -EINVAL;
5604         }
5605
5606         truflow = strtoul(value, &end, 10);
5607         if (end == NULL || *end != '\0' ||
5608             (truflow == ULONG_MAX && errno == ERANGE)) {
5609                 PMD_DRV_LOG(ERR,
5610                             "Invalid parameter passed to truflow devargs.\n");
5611                 return -EINVAL;
5612         }
5613
5614         if (BNXT_DEVARG_TRUFLOW_INVALID(truflow)) {
5615                 PMD_DRV_LOG(ERR,
5616                             "Invalid value passed to truflow devargs.\n");
5617                 return -EINVAL;
5618         }
5619
5620         if (truflow) {
5621                 bp->flags |= BNXT_FLAG_TRUFLOW_EN;
5622                 PMD_DRV_LOG(INFO, "Host-based truflow feature enabled.\n");
5623         } else {
5624                 bp->flags &= ~BNXT_FLAG_TRUFLOW_EN;
5625                 PMD_DRV_LOG(INFO, "Host-based truflow feature disabled.\n");
5626         }
5627
5628         return 0;
5629 }
5630
5631 static int
5632 bnxt_parse_devarg_flow_xstat(__rte_unused const char *key,
5633                              const char *value, void *opaque_arg)
5634 {
5635         struct bnxt *bp = opaque_arg;
5636         unsigned long flow_xstat;
5637         char *end = NULL;
5638
5639         if (!value || !opaque_arg) {
5640                 PMD_DRV_LOG(ERR,
5641                             "Invalid parameter passed to flow_xstat devarg.\n");
5642                 return -EINVAL;
5643         }
5644
5645         flow_xstat = strtoul(value, &end, 10);
5646         if (end == NULL || *end != '\0' ||
5647             (flow_xstat == ULONG_MAX && errno == ERANGE)) {
5648                 PMD_DRV_LOG(ERR,
5649                             "Invalid parameter passed to flow_xstat devarg.\n");
5650                 return -EINVAL;
5651         }
5652
5653         if (BNXT_DEVARG_FLOW_XSTAT_INVALID(flow_xstat)) {
5654                 PMD_DRV_LOG(ERR,
5655                             "Invalid value passed to flow_xstat devarg.\n");
5656                 return -EINVAL;
5657         }
5658
5659         bp->flags |= BNXT_FLAG_FLOW_XSTATS_EN;
5660         if (BNXT_FLOW_XSTATS_EN(bp))
5661                 PMD_DRV_LOG(INFO, "flow_xstat feature enabled.\n");
5662
5663         return 0;
5664 }
5665
5666 static int
5667 bnxt_parse_devarg_max_num_kflows(__rte_unused const char *key,
5668                                         const char *value, void *opaque_arg)
5669 {
5670         struct bnxt *bp = opaque_arg;
5671         unsigned long max_num_kflows;
5672         char *end = NULL;
5673
5674         if (!value || !opaque_arg) {
5675                 PMD_DRV_LOG(ERR,
5676                         "Invalid parameter passed to max_num_kflows devarg.\n");
5677                 return -EINVAL;
5678         }
5679
5680         max_num_kflows = strtoul(value, &end, 10);
5681         if (end == NULL || *end != '\0' ||
5682                 (max_num_kflows == ULONG_MAX && errno == ERANGE)) {
5683                 PMD_DRV_LOG(ERR,
5684                         "Invalid parameter passed to max_num_kflows devarg.\n");
5685                 return -EINVAL;
5686         }
5687
5688         if (bnxt_devarg_max_num_kflow_invalid(max_num_kflows)) {
5689                 PMD_DRV_LOG(ERR,
5690                         "Invalid value passed to max_num_kflows devarg.\n");
5691                 return -EINVAL;
5692         }
5693
5694         bp->max_num_kflows = max_num_kflows;
5695         if (bp->max_num_kflows)
5696                 PMD_DRV_LOG(INFO, "max_num_kflows set as %ldK.\n",
5697                                 max_num_kflows);
5698
5699         return 0;
5700 }
5701
5702 static int
5703 bnxt_parse_devarg_rep_is_pf(__rte_unused const char *key,
5704                             const char *value, void *opaque_arg)
5705 {
5706         struct bnxt_representor *vfr_bp = opaque_arg;
5707         unsigned long rep_is_pf;
5708         char *end = NULL;
5709
5710         if (!value || !opaque_arg) {
5711                 PMD_DRV_LOG(ERR,
5712                             "Invalid parameter passed to rep_is_pf devargs.\n");
5713                 return -EINVAL;
5714         }
5715
5716         rep_is_pf = strtoul(value, &end, 10);
5717         if (end == NULL || *end != '\0' ||
5718             (rep_is_pf == ULONG_MAX && errno == ERANGE)) {
5719                 PMD_DRV_LOG(ERR,
5720                             "Invalid parameter passed to rep_is_pf devargs.\n");
5721                 return -EINVAL;
5722         }
5723
5724         if (BNXT_DEVARG_REP_IS_PF_INVALID(rep_is_pf)) {
5725                 PMD_DRV_LOG(ERR,
5726                             "Invalid value passed to rep_is_pf devargs.\n");
5727                 return -EINVAL;
5728         }
5729
5730         vfr_bp->flags |= rep_is_pf;
5731         if (BNXT_REP_PF(vfr_bp))
5732                 PMD_DRV_LOG(INFO, "PF representor\n");
5733         else
5734                 PMD_DRV_LOG(INFO, "VF representor\n");
5735
5736         return 0;
5737 }
5738
5739 static int
5740 bnxt_parse_devarg_rep_based_pf(__rte_unused const char *key,
5741                                const char *value, void *opaque_arg)
5742 {
5743         struct bnxt_representor *vfr_bp = opaque_arg;
5744         unsigned long rep_based_pf;
5745         char *end = NULL;
5746
5747         if (!value || !opaque_arg) {
5748                 PMD_DRV_LOG(ERR,
5749                             "Invalid parameter passed to rep_based_pf "
5750                             "devargs.\n");
5751                 return -EINVAL;
5752         }
5753
5754         rep_based_pf = strtoul(value, &end, 10);
5755         if (end == NULL || *end != '\0' ||
5756             (rep_based_pf == ULONG_MAX && errno == ERANGE)) {
5757                 PMD_DRV_LOG(ERR,
5758                             "Invalid parameter passed to rep_based_pf "
5759                             "devargs.\n");
5760                 return -EINVAL;
5761         }
5762
5763         if (BNXT_DEVARG_REP_BASED_PF_INVALID(rep_based_pf)) {
5764                 PMD_DRV_LOG(ERR,
5765                             "Invalid value passed to rep_based_pf devargs.\n");
5766                 return -EINVAL;
5767         }
5768
5769         vfr_bp->rep_based_pf = rep_based_pf;
5770         PMD_DRV_LOG(INFO, "rep-based-pf = %d\n", vfr_bp->rep_based_pf);
5771
5772         return 0;
5773 }
5774
5775 static int
5776 bnxt_parse_devarg_rep_q_r2f(__rte_unused const char *key,
5777                             const char *value, void *opaque_arg)
5778 {
5779         struct bnxt_representor *vfr_bp = opaque_arg;
5780         unsigned long rep_q_r2f;
5781         char *end = NULL;
5782
5783         if (!value || !opaque_arg) {
5784                 PMD_DRV_LOG(ERR,
5785                             "Invalid parameter passed to rep_q_r2f "
5786                             "devargs.\n");
5787                 return -EINVAL;
5788         }
5789
5790         rep_q_r2f = strtoul(value, &end, 10);
5791         if (end == NULL || *end != '\0' ||
5792             (rep_q_r2f == ULONG_MAX && errno == ERANGE)) {
5793                 PMD_DRV_LOG(ERR,
5794                             "Invalid parameter passed to rep_q_r2f "
5795                             "devargs.\n");
5796                 return -EINVAL;
5797         }
5798
5799         if (BNXT_DEVARG_REP_Q_R2F_INVALID(rep_q_r2f)) {
5800                 PMD_DRV_LOG(ERR,
5801                             "Invalid value passed to rep_q_r2f devargs.\n");
5802                 return -EINVAL;
5803         }
5804
5805         vfr_bp->rep_q_r2f = rep_q_r2f;
5806         vfr_bp->flags |= BNXT_REP_Q_R2F_VALID;
5807         PMD_DRV_LOG(INFO, "rep-q-r2f = %d\n", vfr_bp->rep_q_r2f);
5808
5809         return 0;
5810 }
5811
5812 static int
5813 bnxt_parse_devarg_rep_q_f2r(__rte_unused const char *key,
5814                             const char *value, void *opaque_arg)
5815 {
5816         struct bnxt_representor *vfr_bp = opaque_arg;
5817         unsigned long rep_q_f2r;
5818         char *end = NULL;
5819
5820         if (!value || !opaque_arg) {
5821                 PMD_DRV_LOG(ERR,
5822                             "Invalid parameter passed to rep_q_f2r "
5823                             "devargs.\n");
5824                 return -EINVAL;
5825         }
5826
5827         rep_q_f2r = strtoul(value, &end, 10);
5828         if (end == NULL || *end != '\0' ||
5829             (rep_q_f2r == ULONG_MAX && errno == ERANGE)) {
5830                 PMD_DRV_LOG(ERR,
5831                             "Invalid parameter passed to rep_q_f2r "
5832                             "devargs.\n");
5833                 return -EINVAL;
5834         }
5835
5836         if (BNXT_DEVARG_REP_Q_F2R_INVALID(rep_q_f2r)) {
5837                 PMD_DRV_LOG(ERR,
5838                             "Invalid value passed to rep_q_f2r devargs.\n");
5839                 return -EINVAL;
5840         }
5841
5842         vfr_bp->rep_q_f2r = rep_q_f2r;
5843         vfr_bp->flags |= BNXT_REP_Q_F2R_VALID;
5844         PMD_DRV_LOG(INFO, "rep-q-f2r = %d\n", vfr_bp->rep_q_f2r);
5845
5846         return 0;
5847 }
5848
5849 static int
5850 bnxt_parse_devarg_rep_fc_r2f(__rte_unused const char *key,
5851                              const char *value, void *opaque_arg)
5852 {
5853         struct bnxt_representor *vfr_bp = opaque_arg;
5854         unsigned long rep_fc_r2f;
5855         char *end = NULL;
5856
5857         if (!value || !opaque_arg) {
5858                 PMD_DRV_LOG(ERR,
5859                             "Invalid parameter passed to rep_fc_r2f "
5860                             "devargs.\n");
5861                 return -EINVAL;
5862         }
5863
5864         rep_fc_r2f = strtoul(value, &end, 10);
5865         if (end == NULL || *end != '\0' ||
5866             (rep_fc_r2f == ULONG_MAX && errno == ERANGE)) {
5867                 PMD_DRV_LOG(ERR,
5868                             "Invalid parameter passed to rep_fc_r2f "
5869                             "devargs.\n");
5870                 return -EINVAL;
5871         }
5872
5873         if (BNXT_DEVARG_REP_FC_R2F_INVALID(rep_fc_r2f)) {
5874                 PMD_DRV_LOG(ERR,
5875                             "Invalid value passed to rep_fc_r2f devargs.\n");
5876                 return -EINVAL;
5877         }
5878
5879         vfr_bp->flags |= BNXT_REP_FC_R2F_VALID;
5880         vfr_bp->rep_fc_r2f = rep_fc_r2f;
5881         PMD_DRV_LOG(INFO, "rep-fc-r2f = %lu\n", rep_fc_r2f);
5882
5883         return 0;
5884 }
5885
5886 static int
5887 bnxt_parse_devarg_rep_fc_f2r(__rte_unused const char *key,
5888                              const char *value, void *opaque_arg)
5889 {
5890         struct bnxt_representor *vfr_bp = opaque_arg;
5891         unsigned long rep_fc_f2r;
5892         char *end = NULL;
5893
5894         if (!value || !opaque_arg) {
5895                 PMD_DRV_LOG(ERR,
5896                             "Invalid parameter passed to rep_fc_f2r "
5897                             "devargs.\n");
5898                 return -EINVAL;
5899         }
5900
5901         rep_fc_f2r = strtoul(value, &end, 10);
5902         if (end == NULL || *end != '\0' ||
5903             (rep_fc_f2r == ULONG_MAX && errno == ERANGE)) {
5904                 PMD_DRV_LOG(ERR,
5905                             "Invalid parameter passed to rep_fc_f2r "
5906                             "devargs.\n");
5907                 return -EINVAL;
5908         }
5909
5910         if (BNXT_DEVARG_REP_FC_F2R_INVALID(rep_fc_f2r)) {
5911                 PMD_DRV_LOG(ERR,
5912                             "Invalid value passed to rep_fc_f2r devargs.\n");
5913                 return -EINVAL;
5914         }
5915
5916         vfr_bp->flags |= BNXT_REP_FC_F2R_VALID;
5917         vfr_bp->rep_fc_f2r = rep_fc_f2r;
5918         PMD_DRV_LOG(INFO, "rep-fc-f2r = %lu\n", rep_fc_f2r);
5919
5920         return 0;
5921 }
5922
5923 static void
5924 bnxt_parse_dev_args(struct bnxt *bp, struct rte_devargs *devargs)
5925 {
5926         struct rte_kvargs *kvlist;
5927
5928         if (devargs == NULL)
5929                 return;
5930
5931         kvlist = rte_kvargs_parse(devargs->args, bnxt_dev_args);
5932         if (kvlist == NULL)
5933                 return;
5934
5935         /*
5936          * Handler for "truflow" devarg.
5937          * Invoked as for ex: "-w 0000:00:0d.0,host-based-truflow=1"
5938          */
5939         rte_kvargs_process(kvlist, BNXT_DEVARG_TRUFLOW,
5940                            bnxt_parse_devarg_truflow, bp);
5941
5942         /*
5943          * Handler for "flow_xstat" devarg.
5944          * Invoked as for ex: "-w 0000:00:0d.0,flow_xstat=1"
5945          */
5946         rte_kvargs_process(kvlist, BNXT_DEVARG_FLOW_XSTAT,
5947                            bnxt_parse_devarg_flow_xstat, bp);
5948
5949         /*
5950          * Handler for "max_num_kflows" devarg.
5951          * Invoked as for ex: "-w 000:00:0d.0,max_num_kflows=32"
5952          */
5953         rte_kvargs_process(kvlist, BNXT_DEVARG_MAX_NUM_KFLOWS,
5954                            bnxt_parse_devarg_max_num_kflows, bp);
5955
5956         rte_kvargs_free(kvlist);
5957 }
5958
5959 static int bnxt_alloc_switch_domain(struct bnxt *bp)
5960 {
5961         int rc = 0;
5962
5963         if (BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp)) {
5964                 rc = rte_eth_switch_domain_alloc(&bp->switch_domain_id);
5965                 if (rc)
5966                         PMD_DRV_LOG(ERR,
5967                                     "Failed to alloc switch domain: %d\n", rc);
5968                 else
5969                         PMD_DRV_LOG(INFO,
5970                                     "Switch domain allocated %d\n",
5971                                     bp->switch_domain_id);
5972         }
5973
5974         return rc;
5975 }
5976
5977 static int
5978 bnxt_dev_init(struct rte_eth_dev *eth_dev, void *params __rte_unused)
5979 {
5980         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
5981         static int version_printed;
5982         struct bnxt *bp;
5983         int rc;
5984
5985         if (version_printed++ == 0)
5986                 PMD_DRV_LOG(INFO, "%s\n", bnxt_version);
5987
5988         eth_dev->dev_ops = &bnxt_dev_ops;
5989         eth_dev->rx_queue_count = bnxt_rx_queue_count_op;
5990         eth_dev->rx_descriptor_status = bnxt_rx_descriptor_status_op;
5991         eth_dev->tx_descriptor_status = bnxt_tx_descriptor_status_op;
5992         eth_dev->rx_pkt_burst = &bnxt_recv_pkts;
5993         eth_dev->tx_pkt_burst = &bnxt_xmit_pkts;
5994
5995         /*
5996          * For secondary processes, we don't initialise any further
5997          * as primary has already done this work.
5998          */
5999         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
6000                 return 0;
6001
6002         rte_eth_copy_pci_info(eth_dev, pci_dev);
6003         eth_dev->data->dev_flags |= RTE_ETH_DEV_AUTOFILL_QUEUE_XSTATS;
6004
6005         bp = eth_dev->data->dev_private;
6006
6007         /* Parse dev arguments passed on when starting the DPDK application. */
6008         bnxt_parse_dev_args(bp, pci_dev->device.devargs);
6009
6010         bp->flags &= ~BNXT_FLAG_RX_VECTOR_PKT_MODE;
6011
6012         if (bnxt_vf_pciid(pci_dev->id.device_id))
6013                 bp->flags |= BNXT_FLAG_VF;
6014
6015         if (bnxt_thor_device(pci_dev->id.device_id))
6016                 bp->flags |= BNXT_FLAG_THOR_CHIP;
6017
6018         if (pci_dev->id.device_id == BROADCOM_DEV_ID_58802 ||
6019             pci_dev->id.device_id == BROADCOM_DEV_ID_58804 ||
6020             pci_dev->id.device_id == BROADCOM_DEV_ID_58808 ||
6021             pci_dev->id.device_id == BROADCOM_DEV_ID_58802_VF)
6022                 bp->flags |= BNXT_FLAG_STINGRAY;
6023
6024         rc = bnxt_init_board(eth_dev);
6025         if (rc) {
6026                 PMD_DRV_LOG(ERR,
6027                             "Failed to initialize board rc: %x\n", rc);
6028                 return rc;
6029         }
6030
6031         rc = bnxt_alloc_pf_info(bp);
6032         if (rc)
6033                 goto error_free;
6034
6035         rc = bnxt_alloc_link_info(bp);
6036         if (rc)
6037                 goto error_free;
6038
6039         rc = bnxt_alloc_parent_info(bp);
6040         if (rc)
6041                 goto error_free;
6042
6043         rc = bnxt_alloc_hwrm_resources(bp);
6044         if (rc) {
6045                 PMD_DRV_LOG(ERR,
6046                             "Failed to allocate hwrm resource rc: %x\n", rc);
6047                 goto error_free;
6048         }
6049         rc = bnxt_alloc_leds_info(bp);
6050         if (rc)
6051                 goto error_free;
6052
6053         rc = bnxt_alloc_cos_queues(bp);
6054         if (rc)
6055                 goto error_free;
6056
6057         rc = bnxt_init_resources(bp, false);
6058         if (rc)
6059                 goto error_free;
6060
6061         rc = bnxt_alloc_stats_mem(bp);
6062         if (rc)
6063                 goto error_free;
6064
6065         bnxt_alloc_switch_domain(bp);
6066
6067         PMD_DRV_LOG(INFO,
6068                     DRV_MODULE_NAME "found at mem %" PRIX64 ", node addr %pM\n",
6069                     pci_dev->mem_resource[0].phys_addr,
6070                     pci_dev->mem_resource[0].addr);
6071
6072         return 0;
6073
6074 error_free:
6075         bnxt_dev_uninit(eth_dev);
6076         return rc;
6077 }
6078
6079
6080 static void bnxt_free_ctx_mem_buf(struct bnxt_ctx_mem_buf_info *ctx)
6081 {
6082         if (!ctx)
6083                 return;
6084
6085         if (ctx->va)
6086                 rte_free(ctx->va);
6087
6088         ctx->va = NULL;
6089         ctx->dma = RTE_BAD_IOVA;
6090         ctx->ctx_id = BNXT_CTX_VAL_INVAL;
6091 }
6092
6093 static void bnxt_unregister_fc_ctx_mem(struct bnxt *bp)
6094 {
6095         bnxt_hwrm_cfa_counter_cfg(bp, BNXT_DIR_RX,
6096                                   CFA_COUNTER_CFG_IN_COUNTER_TYPE_FC,
6097                                   bp->flow_stat->rx_fc_out_tbl.ctx_id,
6098                                   bp->flow_stat->max_fc,
6099                                   false);
6100
6101         bnxt_hwrm_cfa_counter_cfg(bp, BNXT_DIR_TX,
6102                                   CFA_COUNTER_CFG_IN_COUNTER_TYPE_FC,
6103                                   bp->flow_stat->tx_fc_out_tbl.ctx_id,
6104                                   bp->flow_stat->max_fc,
6105                                   false);
6106
6107         if (bp->flow_stat->rx_fc_in_tbl.ctx_id != BNXT_CTX_VAL_INVAL)
6108                 bnxt_hwrm_ctx_unrgtr(bp, bp->flow_stat->rx_fc_in_tbl.ctx_id);
6109         bp->flow_stat->rx_fc_in_tbl.ctx_id = BNXT_CTX_VAL_INVAL;
6110
6111         if (bp->flow_stat->rx_fc_out_tbl.ctx_id != BNXT_CTX_VAL_INVAL)
6112                 bnxt_hwrm_ctx_unrgtr(bp, bp->flow_stat->rx_fc_out_tbl.ctx_id);
6113         bp->flow_stat->rx_fc_out_tbl.ctx_id = BNXT_CTX_VAL_INVAL;
6114
6115         if (bp->flow_stat->tx_fc_in_tbl.ctx_id != BNXT_CTX_VAL_INVAL)
6116                 bnxt_hwrm_ctx_unrgtr(bp, bp->flow_stat->tx_fc_in_tbl.ctx_id);
6117         bp->flow_stat->tx_fc_in_tbl.ctx_id = BNXT_CTX_VAL_INVAL;
6118
6119         if (bp->flow_stat->tx_fc_out_tbl.ctx_id != BNXT_CTX_VAL_INVAL)
6120                 bnxt_hwrm_ctx_unrgtr(bp, bp->flow_stat->tx_fc_out_tbl.ctx_id);
6121         bp->flow_stat->tx_fc_out_tbl.ctx_id = BNXT_CTX_VAL_INVAL;
6122 }
6123
6124 static void bnxt_uninit_fc_ctx_mem(struct bnxt *bp)
6125 {
6126         bnxt_unregister_fc_ctx_mem(bp);
6127
6128         bnxt_free_ctx_mem_buf(&bp->flow_stat->rx_fc_in_tbl);
6129         bnxt_free_ctx_mem_buf(&bp->flow_stat->rx_fc_out_tbl);
6130         bnxt_free_ctx_mem_buf(&bp->flow_stat->tx_fc_in_tbl);
6131         bnxt_free_ctx_mem_buf(&bp->flow_stat->tx_fc_out_tbl);
6132 }
6133
6134 static void bnxt_uninit_ctx_mem(struct bnxt *bp)
6135 {
6136         if (BNXT_FLOW_XSTATS_EN(bp))
6137                 bnxt_uninit_fc_ctx_mem(bp);
6138 }
6139
6140 static void
6141 bnxt_free_error_recovery_info(struct bnxt *bp)
6142 {
6143         rte_free(bp->recovery_info);
6144         bp->recovery_info = NULL;
6145         bp->fw_cap &= ~BNXT_FW_CAP_ERROR_RECOVERY;
6146 }
6147
6148 static void
6149 bnxt_uninit_locks(struct bnxt *bp)
6150 {
6151         pthread_mutex_destroy(&bp->flow_lock);
6152         pthread_mutex_destroy(&bp->def_cp_lock);
6153         pthread_mutex_destroy(&bp->health_check_lock);
6154         if (bp->rep_info) {
6155                 pthread_mutex_destroy(&bp->rep_info->vfr_lock);
6156                 pthread_mutex_destroy(&bp->rep_info->vfr_start_lock);
6157         }
6158 }
6159
6160 static int
6161 bnxt_uninit_resources(struct bnxt *bp, bool reconfig_dev)
6162 {
6163         int rc;
6164
6165         bnxt_free_int(bp);
6166         bnxt_free_mem(bp, reconfig_dev);
6167
6168         bnxt_hwrm_func_buf_unrgtr(bp);
6169         rte_free(bp->pf->vf_req_buf);
6170
6171         rc = bnxt_hwrm_func_driver_unregister(bp, 0);
6172         bp->flags &= ~BNXT_FLAG_REGISTERED;
6173         bnxt_free_ctx_mem(bp);
6174         if (!reconfig_dev) {
6175                 bnxt_free_hwrm_resources(bp);
6176                 bnxt_free_error_recovery_info(bp);
6177         }
6178
6179         bnxt_uninit_ctx_mem(bp);
6180
6181         bnxt_uninit_locks(bp);
6182         bnxt_free_flow_stats_info(bp);
6183         bnxt_free_rep_info(bp);
6184         rte_free(bp->ptp_cfg);
6185         bp->ptp_cfg = NULL;
6186         return rc;
6187 }
6188
6189 static int
6190 bnxt_dev_uninit(struct rte_eth_dev *eth_dev)
6191 {
6192         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
6193                 return -EPERM;
6194
6195         PMD_DRV_LOG(DEBUG, "Calling Device uninit\n");
6196
6197         if (eth_dev->state != RTE_ETH_DEV_UNUSED)
6198                 bnxt_dev_close_op(eth_dev);
6199
6200         return 0;
6201 }
6202
6203 static int bnxt_pci_remove_dev_with_reps(struct rte_eth_dev *eth_dev)
6204 {
6205         struct bnxt *bp = eth_dev->data->dev_private;
6206         struct rte_eth_dev *vf_rep_eth_dev;
6207         int ret = 0, i;
6208
6209         if (!bp)
6210                 return -EINVAL;
6211
6212         for (i = 0; i < bp->num_reps; i++) {
6213                 vf_rep_eth_dev = bp->rep_info[i].vfr_eth_dev;
6214                 if (!vf_rep_eth_dev)
6215                         continue;
6216                 PMD_DRV_LOG(DEBUG, "BNXT Port:%d VFR pci remove\n",
6217                             vf_rep_eth_dev->data->port_id);
6218                 rte_eth_dev_destroy(vf_rep_eth_dev, bnxt_representor_uninit);
6219         }
6220         PMD_DRV_LOG(DEBUG, "BNXT Port:%d pci remove\n",
6221                     eth_dev->data->port_id);
6222         ret = rte_eth_dev_destroy(eth_dev, bnxt_dev_uninit);
6223
6224         return ret;
6225 }
6226
6227 static void bnxt_free_rep_info(struct bnxt *bp)
6228 {
6229         rte_free(bp->rep_info);
6230         bp->rep_info = NULL;
6231         rte_free(bp->cfa_code_map);
6232         bp->cfa_code_map = NULL;
6233 }
6234
6235 static int bnxt_init_rep_info(struct bnxt *bp)
6236 {
6237         int i = 0, rc;
6238
6239         if (bp->rep_info)
6240                 return 0;
6241
6242         bp->rep_info = rte_zmalloc("bnxt_rep_info",
6243                                    sizeof(bp->rep_info[0]) * BNXT_MAX_VF_REPS,
6244                                    0);
6245         if (!bp->rep_info) {
6246                 PMD_DRV_LOG(ERR, "Failed to alloc memory for rep info\n");
6247                 return -ENOMEM;
6248         }
6249         bp->cfa_code_map = rte_zmalloc("bnxt_cfa_code_map",
6250                                        sizeof(*bp->cfa_code_map) *
6251                                        BNXT_MAX_CFA_CODE, 0);
6252         if (!bp->cfa_code_map) {
6253                 PMD_DRV_LOG(ERR, "Failed to alloc memory for cfa_code_map\n");
6254                 bnxt_free_rep_info(bp);
6255                 return -ENOMEM;
6256         }
6257
6258         for (i = 0; i < BNXT_MAX_CFA_CODE; i++)
6259                 bp->cfa_code_map[i] = BNXT_VF_IDX_INVALID;
6260
6261         rc = pthread_mutex_init(&bp->rep_info->vfr_lock, NULL);
6262         if (rc) {
6263                 PMD_DRV_LOG(ERR, "Unable to initialize vfr_lock\n");
6264                 bnxt_free_rep_info(bp);
6265                 return rc;
6266         }
6267
6268         rc = pthread_mutex_init(&bp->rep_info->vfr_start_lock, NULL);
6269         if (rc) {
6270                 PMD_DRV_LOG(ERR, "Unable to initialize vfr_start_lock\n");
6271                 bnxt_free_rep_info(bp);
6272                 return rc;
6273         }
6274
6275         return rc;
6276 }
6277
6278 static int bnxt_rep_port_probe(struct rte_pci_device *pci_dev,
6279                                struct rte_eth_devargs eth_da,
6280                                struct rte_eth_dev *backing_eth_dev,
6281                                const char *dev_args)
6282 {
6283         struct rte_eth_dev *vf_rep_eth_dev;
6284         char name[RTE_ETH_NAME_MAX_LEN];
6285         struct bnxt *backing_bp;
6286         uint16_t num_rep;
6287         int i, ret = 0;
6288         struct rte_kvargs *kvlist;
6289
6290         num_rep = eth_da.nb_representor_ports;
6291         if (num_rep > BNXT_MAX_VF_REPS) {
6292                 PMD_DRV_LOG(ERR, "nb_representor_ports = %d > %d MAX VF REPS\n",
6293                             num_rep, BNXT_MAX_VF_REPS);
6294                 return -EINVAL;
6295         }
6296
6297         if (num_rep >= RTE_MAX_ETHPORTS) {
6298                 PMD_DRV_LOG(ERR,
6299                             "nb_representor_ports = %d > %d MAX ETHPORTS\n",
6300                             num_rep, RTE_MAX_ETHPORTS);
6301                 return -EINVAL;
6302         }
6303
6304         backing_bp = backing_eth_dev->data->dev_private;
6305
6306         if (!(BNXT_PF(backing_bp) || BNXT_VF_IS_TRUSTED(backing_bp))) {
6307                 PMD_DRV_LOG(ERR,
6308                             "Not a PF or trusted VF. No Representor support\n");
6309                 /* Returning an error is not an option.
6310                  * Applications are not handling this correctly
6311                  */
6312                 return 0;
6313         }
6314
6315         if (bnxt_init_rep_info(backing_bp))
6316                 return 0;
6317
6318         for (i = 0; i < num_rep; i++) {
6319                 struct bnxt_representor representor = {
6320                         .vf_id = eth_da.representor_ports[i],
6321                         .switch_domain_id = backing_bp->switch_domain_id,
6322                         .parent_dev = backing_eth_dev
6323                 };
6324
6325                 if (representor.vf_id >= BNXT_MAX_VF_REPS) {
6326                         PMD_DRV_LOG(ERR, "VF-Rep id %d >= %d MAX VF ID\n",
6327                                     representor.vf_id, BNXT_MAX_VF_REPS);
6328                         continue;
6329                 }
6330
6331                 /* representor port net_bdf_port */
6332                 snprintf(name, sizeof(name), "net_%s_representor_%d",
6333                          pci_dev->device.name, eth_da.representor_ports[i]);
6334
6335                 kvlist = rte_kvargs_parse(dev_args, bnxt_dev_args);
6336                 if (kvlist) {
6337                         /*
6338                          * Handler for "rep_is_pf" devarg.
6339                          * Invoked as for ex: "-w 000:00:0d.0,
6340                          * rep-based-pf=<pf index> rep-is-pf=<VF=0 or PF=1>"
6341                          */
6342                         rte_kvargs_process(kvlist, BNXT_DEVARG_REP_IS_PF,
6343                                            bnxt_parse_devarg_rep_is_pf,
6344                                            (void *)&representor);
6345                         /*
6346                          * Handler for "rep_based_pf" devarg.
6347                          * Invoked as for ex: "-w 000:00:0d.0,
6348                          * rep-based-pf=<pf index> rep-is-pf=<VF=0 or PF=1>"
6349                          */
6350                         rte_kvargs_process(kvlist, BNXT_DEVARG_REP_BASED_PF,
6351                                            bnxt_parse_devarg_rep_based_pf,
6352                                            (void *)&representor);
6353                         /*
6354                          * Handler for "rep_based_pf" devarg.
6355                          * Invoked as for ex: "-w 000:00:0d.0,
6356                          * rep-based-pf=<pf index> rep-is-pf=<VF=0 or PF=1>"
6357                          */
6358                         rte_kvargs_process(kvlist, BNXT_DEVARG_REP_Q_R2F,
6359                                            bnxt_parse_devarg_rep_q_r2f,
6360                                            (void *)&representor);
6361                         /*
6362                          * Handler for "rep_based_pf" devarg.
6363                          * Invoked as for ex: "-w 000:00:0d.0,
6364                          * rep-based-pf=<pf index> rep-is-pf=<VF=0 or PF=1>"
6365                          */
6366                         rte_kvargs_process(kvlist, BNXT_DEVARG_REP_Q_F2R,
6367                                            bnxt_parse_devarg_rep_q_f2r,
6368                                            (void *)&representor);
6369                         /*
6370                          * Handler for "rep_based_pf" devarg.
6371                          * Invoked as for ex: "-w 000:00:0d.0,
6372                          * rep-based-pf=<pf index> rep-is-pf=<VF=0 or PF=1>"
6373                          */
6374                         rte_kvargs_process(kvlist, BNXT_DEVARG_REP_FC_R2F,
6375                                            bnxt_parse_devarg_rep_fc_r2f,
6376                                            (void *)&representor);
6377                         /*
6378                          * Handler for "rep_based_pf" devarg.
6379                          * Invoked as for ex: "-w 000:00:0d.0,
6380                          * rep-based-pf=<pf index> rep-is-pf=<VF=0 or PF=1>"
6381                          */
6382                         rte_kvargs_process(kvlist, BNXT_DEVARG_REP_FC_F2R,
6383                                            bnxt_parse_devarg_rep_fc_f2r,
6384                                            (void *)&representor);
6385                 }
6386
6387                 ret = rte_eth_dev_create(&pci_dev->device, name,
6388                                          sizeof(struct bnxt_representor),
6389                                          NULL, NULL,
6390                                          bnxt_representor_init,
6391                                          &representor);
6392                 if (ret) {
6393                         PMD_DRV_LOG(ERR, "failed to create bnxt vf "
6394                                     "representor %s.", name);
6395                         goto err;
6396                 }
6397
6398                 vf_rep_eth_dev = rte_eth_dev_allocated(name);
6399                 if (!vf_rep_eth_dev) {
6400                         PMD_DRV_LOG(ERR, "Failed to find the eth_dev"
6401                                     " for VF-Rep: %s.", name);
6402                         ret = -ENODEV;
6403                         goto err;
6404                 }
6405
6406                 PMD_DRV_LOG(DEBUG, "BNXT Port:%d VFR pci probe\n",
6407                             backing_eth_dev->data->port_id);
6408                 backing_bp->rep_info[representor.vf_id].vfr_eth_dev =
6409                                                          vf_rep_eth_dev;
6410                 backing_bp->num_reps++;
6411
6412         }
6413
6414         return 0;
6415
6416 err:
6417         /* If num_rep > 1, then rollback already created
6418          * ports, since we'll be failing the probe anyway
6419          */
6420         if (num_rep > 1)
6421                 bnxt_pci_remove_dev_with_reps(backing_eth_dev);
6422
6423         return ret;
6424 }
6425
6426 static int bnxt_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
6427                           struct rte_pci_device *pci_dev)
6428 {
6429         struct rte_eth_devargs eth_da = { .nb_representor_ports = 0 };
6430         struct rte_eth_dev *backing_eth_dev;
6431         uint16_t num_rep;
6432         int ret = 0;
6433
6434         if (pci_dev->device.devargs) {
6435                 ret = rte_eth_devargs_parse(pci_dev->device.devargs->args,
6436                                             &eth_da);
6437                 if (ret)
6438                         return ret;
6439         }
6440
6441         num_rep = eth_da.nb_representor_ports;
6442         PMD_DRV_LOG(DEBUG, "nb_representor_ports = %d\n",
6443                     num_rep);
6444
6445         /* We could come here after first level of probe is already invoked
6446          * as part of an application bringup(OVS-DPDK vswitchd), so first check
6447          * for already allocated eth_dev for the backing device (PF/Trusted VF)
6448          */
6449         backing_eth_dev = rte_eth_dev_allocated(pci_dev->device.name);
6450         if (backing_eth_dev == NULL) {
6451                 ret = rte_eth_dev_create(&pci_dev->device, pci_dev->device.name,
6452                                          sizeof(struct bnxt),
6453                                          eth_dev_pci_specific_init, pci_dev,
6454                                          bnxt_dev_init, NULL);
6455
6456                 if (ret || !num_rep)
6457                         return ret;
6458
6459                 backing_eth_dev = rte_eth_dev_allocated(pci_dev->device.name);
6460         }
6461         PMD_DRV_LOG(DEBUG, "BNXT Port:%d pci probe\n",
6462                     backing_eth_dev->data->port_id);
6463
6464         if (!num_rep)
6465                 return ret;
6466
6467         /* probe representor ports now */
6468         ret = bnxt_rep_port_probe(pci_dev, eth_da, backing_eth_dev,
6469                                   pci_dev->device.devargs->args);
6470
6471         return ret;
6472 }
6473
6474 static int bnxt_pci_remove(struct rte_pci_device *pci_dev)
6475 {
6476         struct rte_eth_dev *eth_dev;
6477
6478         eth_dev = rte_eth_dev_allocated(pci_dev->device.name);
6479         if (!eth_dev)
6480                 return 0; /* Invoked typically only by OVS-DPDK, by the
6481                            * time it comes here the eth_dev is already
6482                            * deleted by rte_eth_dev_close(), so returning
6483                            * +ve value will at least help in proper cleanup
6484                            */
6485
6486         PMD_DRV_LOG(DEBUG, "BNXT Port:%d pci remove\n", eth_dev->data->port_id);
6487         if (rte_eal_process_type() == RTE_PROC_PRIMARY) {
6488                 if (eth_dev->data->dev_flags & RTE_ETH_DEV_REPRESENTOR)
6489                         return rte_eth_dev_destroy(eth_dev,
6490                                                    bnxt_representor_uninit);
6491                 else
6492                         return rte_eth_dev_destroy(eth_dev,
6493                                                    bnxt_dev_uninit);
6494         } else {
6495                 return rte_eth_dev_pci_generic_remove(pci_dev, NULL);
6496         }
6497 }
6498
6499 static struct rte_pci_driver bnxt_rte_pmd = {
6500         .id_table = bnxt_pci_id_map,
6501         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC |
6502                         RTE_PCI_DRV_PROBE_AGAIN, /* Needed in case of VF-REPs
6503                                                   * and OVS-DPDK
6504                                                   */
6505         .probe = bnxt_pci_probe,
6506         .remove = bnxt_pci_remove,
6507 };
6508
6509 static bool
6510 is_device_supported(struct rte_eth_dev *dev, struct rte_pci_driver *drv)
6511 {
6512         if (strcmp(dev->device->driver->name, drv->driver.name))
6513                 return false;
6514
6515         return true;
6516 }
6517
6518 bool is_bnxt_supported(struct rte_eth_dev *dev)
6519 {
6520         return is_device_supported(dev, &bnxt_rte_pmd);
6521 }
6522
6523 RTE_LOG_REGISTER(bnxt_logtype_driver, pmd.net.bnxt.driver, NOTICE);
6524 RTE_PMD_REGISTER_PCI(net_bnxt, bnxt_rte_pmd);
6525 RTE_PMD_REGISTER_PCI_TABLE(net_bnxt, bnxt_pci_id_map);
6526 RTE_PMD_REGISTER_KMOD_DEP(net_bnxt, "* igb_uio | uio_pci_generic | vfio-pci");