4 * Copyright(c) Broadcom Limited.
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8 * modification, are permitted provided that the following conditions
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12 * notice, this list of conditions and the following disclaimer.
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14 * notice, this list of conditions and the following disclaimer in
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31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
38 #include <rte_ethdev.h>
39 #include <rte_malloc.h>
40 #include <rte_cycles.h>
44 #include "bnxt_filter.h"
45 #include "bnxt_hwrm.h"
47 #include "bnxt_ring.h"
50 #include "bnxt_stats.h"
53 #include "bnxt_vnic.h"
54 #include "hsi_struct_def_dpdk.h"
56 #define DRV_MODULE_NAME "bnxt"
57 static const char bnxt_version[] =
58 "Broadcom Cumulus driver " DRV_MODULE_NAME "\n";
60 #define PCI_VENDOR_ID_BROADCOM 0x14E4
62 #define BROADCOM_DEV_ID_57301 0x16c8
63 #define BROADCOM_DEV_ID_57302 0x16c9
64 #define BROADCOM_DEV_ID_57304_PF 0x16ca
65 #define BROADCOM_DEV_ID_57304_VF 0x16cb
66 #define BROADCOM_DEV_ID_NS2 0x16cd
67 #define BROADCOM_DEV_ID_57402 0x16d0
68 #define BROADCOM_DEV_ID_57404 0x16d1
69 #define BROADCOM_DEV_ID_57406_PF 0x16d2
70 #define BROADCOM_DEV_ID_57406_VF 0x16d3
71 #define BROADCOM_DEV_ID_57402_MF 0x16d4
72 #define BROADCOM_DEV_ID_57407_RJ45 0x16d5
73 #define BROADCOM_DEV_ID_5741X_VF 0x16dc
74 #define BROADCOM_DEV_ID_5731X_VF 0x16e1
75 #define BROADCOM_DEV_ID_57404_MF 0x16e7
76 #define BROADCOM_DEV_ID_57406_MF 0x16e8
77 #define BROADCOM_DEV_ID_57407_SFP 0x16e9
78 #define BROADCOM_DEV_ID_57407_MF 0x16ea
80 static struct rte_pci_id bnxt_pci_id_map[] = {
81 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57301) },
82 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57302) },
83 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57304_PF) },
84 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57304_VF) },
85 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_NS2) },
86 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57402) },
87 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57404) },
88 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57406_PF) },
89 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57406_VF) },
90 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57402_MF) },
91 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57407_RJ45) },
92 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57404_MF) },
93 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57406_MF) },
94 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57407_SFP) },
95 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57407_MF) },
96 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_5741X_VF) },
97 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_5731X_VF) },
98 { .vendor_id = 0, /* sentinel */ },
101 #define BNXT_ETH_RSS_SUPPORT ( \
103 ETH_RSS_NONFRAG_IPV4_TCP | \
104 ETH_RSS_NONFRAG_IPV4_UDP | \
106 ETH_RSS_NONFRAG_IPV6_TCP | \
107 ETH_RSS_NONFRAG_IPV6_UDP)
109 /***********************/
112 * High level utility functions
115 static void bnxt_free_mem(struct bnxt *bp)
117 bnxt_free_filter_mem(bp);
118 bnxt_free_vnic_attributes(bp);
119 bnxt_free_vnic_mem(bp);
122 bnxt_free_tx_rings(bp);
123 bnxt_free_rx_rings(bp);
124 bnxt_free_def_cp_ring(bp);
127 static int bnxt_alloc_mem(struct bnxt *bp)
131 /* Default completion ring */
132 rc = bnxt_init_def_ring_struct(bp, SOCKET_ID_ANY);
136 rc = bnxt_alloc_rings(bp, 0, NULL, NULL,
137 bp->def_cp_ring, "def_cp");
141 rc = bnxt_alloc_vnic_mem(bp);
145 rc = bnxt_alloc_vnic_attributes(bp);
149 rc = bnxt_alloc_filter_mem(bp);
160 static int bnxt_init_chip(struct bnxt *bp)
162 unsigned int i, rss_idx, fw_idx;
163 struct rte_eth_link new;
166 rc = bnxt_alloc_all_hwrm_stat_ctxs(bp);
168 RTE_LOG(ERR, PMD, "HWRM stat ctx alloc failure rc: %x\n", rc);
172 rc = bnxt_alloc_hwrm_rings(bp);
174 RTE_LOG(ERR, PMD, "HWRM ring alloc failure rc: %x\n", rc);
178 rc = bnxt_alloc_all_hwrm_ring_grps(bp);
180 RTE_LOG(ERR, PMD, "HWRM ring grp alloc failure: %x\n", rc);
184 rc = bnxt_mq_rx_configure(bp);
186 RTE_LOG(ERR, PMD, "MQ mode configure failure rc: %x\n", rc);
190 /* VNIC configuration */
191 for (i = 0; i < bp->nr_vnics; i++) {
192 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
194 rc = bnxt_hwrm_vnic_alloc(bp, vnic);
196 RTE_LOG(ERR, PMD, "HWRM vnic alloc failure rc: %x\n",
201 rc = bnxt_hwrm_vnic_ctx_alloc(bp, vnic);
204 "HWRM vnic ctx alloc failure rc: %x\n", rc);
208 rc = bnxt_hwrm_vnic_cfg(bp, vnic);
210 RTE_LOG(ERR, PMD, "HWRM vnic cfg failure rc: %x\n", rc);
214 rc = bnxt_set_hwrm_vnic_filters(bp, vnic);
216 RTE_LOG(ERR, PMD, "HWRM vnic filter failure rc: %x\n",
220 if (vnic->rss_table && vnic->hash_type) {
222 * Fill the RSS hash & redirection table with
223 * ring group ids for all VNICs
225 for (rss_idx = 0, fw_idx = 0;
226 rss_idx < HW_HASH_INDEX_SIZE;
227 rss_idx++, fw_idx++) {
228 if (vnic->fw_grp_ids[fw_idx] ==
231 vnic->rss_table[rss_idx] =
232 vnic->fw_grp_ids[fw_idx];
234 rc = bnxt_hwrm_vnic_rss_cfg(bp, vnic);
237 "HWRM vnic set RSS failure rc: %x\n",
243 rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, &bp->vnic_info[0]);
246 "HWRM cfa l2 rx mask failure rc: %x\n", rc);
250 rc = bnxt_get_hwrm_link_config(bp, &new);
252 RTE_LOG(ERR, PMD, "HWRM Get link config failure rc: %x\n", rc);
256 if (!bp->link_info.link_up) {
257 rc = bnxt_set_hwrm_link_config(bp, true);
260 "HWRM link config failure rc: %x\n", rc);
268 bnxt_free_all_hwrm_resources(bp);
273 static int bnxt_shutdown_nic(struct bnxt *bp)
275 bnxt_free_all_hwrm_resources(bp);
276 bnxt_free_all_filters(bp);
277 bnxt_free_all_vnics(bp);
281 static int bnxt_init_nic(struct bnxt *bp)
285 bnxt_init_ring_grps(bp);
287 bnxt_init_filters(bp);
289 rc = bnxt_init_chip(bp);
297 * Device configuration and status function
300 static void bnxt_dev_info_get_op(struct rte_eth_dev *eth_dev,
301 struct rte_eth_dev_info *dev_info)
303 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
304 uint16_t max_vnics, i, j, vpool, vrxq;
307 dev_info->max_mac_addrs = MAX_NUM_MAC_ADDR;
308 dev_info->max_hash_mac_addrs = 0;
310 /* PF/VF specifics */
312 dev_info->max_rx_queues = bp->pf.max_rx_rings;
313 dev_info->max_tx_queues = bp->pf.max_tx_rings;
314 dev_info->max_vfs = bp->pf.active_vfs;
315 dev_info->reta_size = bp->pf.max_rsscos_ctx;
316 max_vnics = bp->pf.max_vnics;
318 dev_info->max_rx_queues = bp->vf.max_rx_rings;
319 dev_info->max_tx_queues = bp->vf.max_tx_rings;
320 dev_info->reta_size = bp->vf.max_rsscos_ctx;
321 max_vnics = bp->vf.max_vnics;
324 /* Fast path specifics */
325 dev_info->min_rx_bufsize = 1;
326 dev_info->max_rx_pktlen = BNXT_MAX_MTU + ETHER_HDR_LEN + ETHER_CRC_LEN
328 dev_info->rx_offload_capa = 0;
329 dev_info->tx_offload_capa = DEV_TX_OFFLOAD_IPV4_CKSUM |
330 DEV_TX_OFFLOAD_TCP_CKSUM |
331 DEV_TX_OFFLOAD_UDP_CKSUM |
332 DEV_TX_OFFLOAD_TCP_TSO;
335 dev_info->default_rxconf = (struct rte_eth_rxconf) {
341 .rx_free_thresh = 32,
345 dev_info->default_txconf = (struct rte_eth_txconf) {
351 .tx_free_thresh = 32,
353 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
354 ETH_TXQ_FLAGS_NOOFFLOADS,
356 eth_dev->data->dev_conf.intr_conf.lsc = 1;
361 * TODO: default_rxconf, default_txconf, rx_desc_lim, and tx_desc_lim
362 * need further investigation.
366 vpool = 64; /* ETH_64_POOLS */
367 vrxq = 128; /* ETH_VMDQ_DCB_NUM_QUEUES */
368 for (i = 0; i < 4; vpool >>= 1, i++) {
369 if (max_vnics > vpool) {
370 for (j = 0; j < 5; vrxq >>= 1, j++) {
371 if (dev_info->max_rx_queues > vrxq) {
377 /* Not enough resources to support VMDq */
381 /* Not enough resources to support VMDq */
385 dev_info->max_vmdq_pools = vpool;
386 dev_info->vmdq_queue_num = vrxq;
388 dev_info->vmdq_pool_base = 0;
389 dev_info->vmdq_queue_base = 0;
392 /* Configure the device based on the configuration provided */
393 static int bnxt_dev_configure_op(struct rte_eth_dev *eth_dev)
395 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
397 bp->rx_queues = (void *)eth_dev->data->rx_queues;
398 bp->tx_queues = (void *)eth_dev->data->tx_queues;
400 /* Inherit new configurations */
401 bp->rx_nr_rings = eth_dev->data->nb_rx_queues;
402 bp->tx_nr_rings = eth_dev->data->nb_tx_queues;
403 bp->rx_cp_nr_rings = bp->rx_nr_rings;
404 bp->tx_cp_nr_rings = bp->tx_nr_rings;
406 if (eth_dev->data->dev_conf.rxmode.jumbo_frame)
408 eth_dev->data->dev_conf.rxmode.max_rx_pkt_len -
409 ETHER_HDR_LEN - ETHER_CRC_LEN - VLAN_TAG_SIZE;
414 rte_bnxt_atomic_write_link_status(struct rte_eth_dev *eth_dev,
415 struct rte_eth_link *link)
417 struct rte_eth_link *dst = ð_dev->data->dev_link;
418 struct rte_eth_link *src = link;
420 if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
421 *(uint64_t *)src) == 0)
427 static void bnxt_print_link_info(struct rte_eth_dev *eth_dev)
429 struct rte_eth_link *link = ð_dev->data->dev_link;
431 if (link->link_status)
432 RTE_LOG(INFO, PMD, "Port %d Link Up - speed %u Mbps - %s\n",
433 (uint8_t)(eth_dev->data->port_id),
434 (uint32_t)link->link_speed,
435 (link->link_duplex == ETH_LINK_FULL_DUPLEX) ?
436 ("full-duplex") : ("half-duplex\n"));
438 RTE_LOG(INFO, PMD, "Port %d Link Down\n",
439 (uint8_t)(eth_dev->data->port_id));
442 static int bnxt_dev_lsc_intr_setup(struct rte_eth_dev *eth_dev)
444 bnxt_print_link_info(eth_dev);
448 static int bnxt_dev_start_op(struct rte_eth_dev *eth_dev)
450 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
454 rc = bnxt_hwrm_func_reset(bp);
456 RTE_LOG(ERR, PMD, "hwrm chip reset failure rc: %x\n", rc);
461 rc = bnxt_setup_int(bp);
465 rc = bnxt_alloc_mem(bp);
469 rc = bnxt_request_int(bp);
473 rc = bnxt_init_nic(bp);
479 bnxt_link_update_op(eth_dev, 0);
483 bnxt_shutdown_nic(bp);
484 bnxt_disable_int(bp);
486 bnxt_free_tx_mbufs(bp);
487 bnxt_free_rx_mbufs(bp);
492 static int bnxt_dev_set_link_up_op(struct rte_eth_dev *eth_dev)
494 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
496 eth_dev->data->dev_link.link_status = 1;
497 bnxt_set_hwrm_link_config(bp, true);
501 static int bnxt_dev_set_link_down_op(struct rte_eth_dev *eth_dev)
503 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
505 eth_dev->data->dev_link.link_status = 0;
506 bnxt_set_hwrm_link_config(bp, false);
510 /* Unload the driver, release resources */
511 static void bnxt_dev_stop_op(struct rte_eth_dev *eth_dev)
513 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
515 if (bp->eth_dev->data->dev_started) {
516 /* TBD: STOP HW queues DMA */
517 eth_dev->data->dev_link.link_status = 0;
519 bnxt_set_hwrm_link_config(bp, false);
520 bnxt_disable_int(bp);
522 bnxt_shutdown_nic(bp);
526 static void bnxt_dev_close_op(struct rte_eth_dev *eth_dev)
528 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
530 if (bp->dev_stopped == 0)
531 bnxt_dev_stop_op(eth_dev);
533 bnxt_free_tx_mbufs(bp);
534 bnxt_free_rx_mbufs(bp);
536 if (eth_dev->data->mac_addrs != NULL) {
537 rte_free(eth_dev->data->mac_addrs);
538 eth_dev->data->mac_addrs = NULL;
540 if (bp->grp_info != NULL) {
541 rte_free(bp->grp_info);
546 static void bnxt_mac_addr_remove_op(struct rte_eth_dev *eth_dev,
549 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
550 uint64_t pool_mask = eth_dev->data->mac_pool_sel[index];
551 struct bnxt_vnic_info *vnic;
552 struct bnxt_filter_info *filter, *temp_filter;
556 * Loop through all VNICs from the specified filter flow pools to
557 * remove the corresponding MAC addr filter
559 for (i = 0; i < MAX_FF_POOLS; i++) {
560 if (!(pool_mask & (1ULL << i)))
563 STAILQ_FOREACH(vnic, &bp->ff_pool[i], next) {
564 filter = STAILQ_FIRST(&vnic->filter);
566 temp_filter = STAILQ_NEXT(filter, next);
567 if (filter->mac_index == index) {
568 STAILQ_REMOVE(&vnic->filter, filter,
569 bnxt_filter_info, next);
570 bnxt_hwrm_clear_filter(bp, filter);
571 filter->mac_index = INVALID_MAC_INDEX;
572 memset(&filter->l2_addr, 0,
575 &bp->free_filter_list,
578 filter = temp_filter;
584 static void bnxt_mac_addr_add_op(struct rte_eth_dev *eth_dev,
585 struct ether_addr *mac_addr,
586 uint32_t index, uint32_t pool)
588 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
589 struct bnxt_vnic_info *vnic = STAILQ_FIRST(&bp->ff_pool[pool]);
590 struct bnxt_filter_info *filter;
593 RTE_LOG(ERR, PMD, "Cannot add MAC address to a VF interface\n");
598 RTE_LOG(ERR, PMD, "VNIC not found for pool %d!\n", pool);
601 /* Attach requested MAC address to the new l2_filter */
602 STAILQ_FOREACH(filter, &vnic->filter, next) {
603 if (filter->mac_index == index) {
605 "MAC addr already existed for pool %d\n", pool);
609 filter = bnxt_alloc_filter(bp);
611 RTE_LOG(ERR, PMD, "L2 filter alloc failed\n");
614 STAILQ_INSERT_TAIL(&vnic->filter, filter, next);
615 filter->mac_index = index;
616 memcpy(filter->l2_addr, mac_addr, ETHER_ADDR_LEN);
617 bnxt_hwrm_set_filter(bp, vnic, filter);
620 int bnxt_link_update_op(struct rte_eth_dev *eth_dev, int wait_to_complete)
623 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
624 struct rte_eth_link new;
625 unsigned int cnt = BNXT_LINK_WAIT_CNT;
627 memset(&new, 0, sizeof(new));
629 /* Retrieve link info from hardware */
630 rc = bnxt_get_hwrm_link_config(bp, &new);
632 new.link_speed = ETH_LINK_SPEED_100M;
633 new.link_duplex = ETH_LINK_FULL_DUPLEX;
635 "Failed to retrieve link rc = 0x%x!", rc);
638 rte_delay_ms(BNXT_LINK_WAIT_INTERVAL);
640 if (!wait_to_complete)
642 } while (!new.link_status && cnt--);
645 /* Timed out or success */
646 if (new.link_status != eth_dev->data->dev_link.link_status ||
647 new.link_speed != eth_dev->data->dev_link.link_speed) {
648 rte_bnxt_atomic_write_link_status(eth_dev, &new);
649 bnxt_print_link_info(eth_dev);
655 static void bnxt_promiscuous_enable_op(struct rte_eth_dev *eth_dev)
657 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
658 struct bnxt_vnic_info *vnic;
660 if (bp->vnic_info == NULL)
663 vnic = &bp->vnic_info[0];
665 vnic->flags |= BNXT_VNIC_INFO_PROMISC;
666 bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic);
669 static void bnxt_promiscuous_disable_op(struct rte_eth_dev *eth_dev)
671 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
672 struct bnxt_vnic_info *vnic;
674 if (bp->vnic_info == NULL)
677 vnic = &bp->vnic_info[0];
679 vnic->flags &= ~BNXT_VNIC_INFO_PROMISC;
680 bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic);
683 static void bnxt_allmulticast_enable_op(struct rte_eth_dev *eth_dev)
685 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
686 struct bnxt_vnic_info *vnic;
688 if (bp->vnic_info == NULL)
691 vnic = &bp->vnic_info[0];
693 vnic->flags |= BNXT_VNIC_INFO_ALLMULTI;
694 bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic);
697 static void bnxt_allmulticast_disable_op(struct rte_eth_dev *eth_dev)
699 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
700 struct bnxt_vnic_info *vnic;
702 if (bp->vnic_info == NULL)
705 vnic = &bp->vnic_info[0];
707 vnic->flags &= ~BNXT_VNIC_INFO_ALLMULTI;
708 bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic);
711 static int bnxt_reta_update_op(struct rte_eth_dev *eth_dev,
712 struct rte_eth_rss_reta_entry64 *reta_conf,
715 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
716 struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
717 struct bnxt_vnic_info *vnic;
720 if (!(dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG))
723 if (reta_size != HW_HASH_INDEX_SIZE) {
724 RTE_LOG(ERR, PMD, "The configured hash table lookup size "
725 "(%d) must equal the size supported by the hardware "
726 "(%d)\n", reta_size, HW_HASH_INDEX_SIZE);
729 /* Update the RSS VNIC(s) */
730 for (i = 0; i < MAX_FF_POOLS; i++) {
731 STAILQ_FOREACH(vnic, &bp->ff_pool[i], next) {
732 memcpy(vnic->rss_table, reta_conf, reta_size);
734 bnxt_hwrm_vnic_rss_cfg(bp, vnic);
740 static int bnxt_reta_query_op(struct rte_eth_dev *eth_dev,
741 struct rte_eth_rss_reta_entry64 *reta_conf,
744 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
745 struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
747 /* Retrieve from the default VNIC */
750 if (!vnic->rss_table)
753 if (reta_size != HW_HASH_INDEX_SIZE) {
754 RTE_LOG(ERR, PMD, "The configured hash table lookup size "
755 "(%d) must equal the size supported by the hardware "
756 "(%d)\n", reta_size, HW_HASH_INDEX_SIZE);
759 /* EW - need to revisit here copying from u64 to u16 */
760 memcpy(reta_conf, vnic->rss_table, reta_size);
762 if (rte_intr_allow_others(ð_dev->pci_dev->intr_handle)) {
763 if (eth_dev->data->dev_conf.intr_conf.lsc != 0)
764 bnxt_dev_lsc_intr_setup(eth_dev);
770 static int bnxt_rss_hash_update_op(struct rte_eth_dev *eth_dev,
771 struct rte_eth_rss_conf *rss_conf)
773 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
774 struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
775 struct bnxt_vnic_info *vnic;
776 uint16_t hash_type = 0;
780 * If RSS enablement were different than dev_configure,
781 * then return -EINVAL
783 if (dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG) {
784 if (!rss_conf->rss_hf)
787 if (rss_conf->rss_hf & BNXT_ETH_RSS_SUPPORT)
790 if (rss_conf->rss_hf & ETH_RSS_IPV4)
791 hash_type |= HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV4;
792 if (rss_conf->rss_hf & ETH_RSS_NONFRAG_IPV4_TCP)
793 hash_type |= HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV4;
794 if (rss_conf->rss_hf & ETH_RSS_NONFRAG_IPV4_UDP)
795 hash_type |= HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV4;
796 if (rss_conf->rss_hf & ETH_RSS_IPV6)
797 hash_type |= HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6;
798 if (rss_conf->rss_hf & ETH_RSS_NONFRAG_IPV6_TCP)
799 hash_type |= HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV6;
800 if (rss_conf->rss_hf & ETH_RSS_NONFRAG_IPV6_UDP)
801 hash_type |= HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV6;
803 /* Update the RSS VNIC(s) */
804 for (i = 0; i < MAX_FF_POOLS; i++) {
805 STAILQ_FOREACH(vnic, &bp->ff_pool[i], next) {
806 vnic->hash_type = hash_type;
809 * Use the supplied key if the key length is
810 * acceptable and the rss_key is not NULL
812 if (rss_conf->rss_key &&
813 rss_conf->rss_key_len <= HW_HASH_KEY_SIZE)
814 memcpy(vnic->rss_hash_key, rss_conf->rss_key,
815 rss_conf->rss_key_len);
817 bnxt_hwrm_vnic_rss_cfg(bp, vnic);
823 static int bnxt_rss_hash_conf_get_op(struct rte_eth_dev *eth_dev,
824 struct rte_eth_rss_conf *rss_conf)
826 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
827 struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
831 /* RSS configuration is the same for all VNICs */
832 if (vnic && vnic->rss_hash_key) {
833 if (rss_conf->rss_key) {
834 len = rss_conf->rss_key_len <= HW_HASH_KEY_SIZE ?
835 rss_conf->rss_key_len : HW_HASH_KEY_SIZE;
836 memcpy(rss_conf->rss_key, vnic->rss_hash_key, len);
839 hash_types = vnic->hash_type;
840 rss_conf->rss_hf = 0;
841 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV4) {
842 rss_conf->rss_hf |= ETH_RSS_IPV4;
843 hash_types &= ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV4;
845 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV4) {
846 rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP;
848 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV4;
850 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV4) {
851 rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
853 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV4;
855 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6) {
856 rss_conf->rss_hf |= ETH_RSS_IPV6;
857 hash_types &= ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6;
859 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV6) {
860 rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV6_TCP;
862 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV6;
864 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV6) {
865 rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;
867 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV6;
871 "Unknwon RSS config from firmware (%08x), RSS disabled",
876 rss_conf->rss_hf = 0;
881 static int bnxt_flow_ctrl_get_op(struct rte_eth_dev *dev,
882 struct rte_eth_fc_conf *fc_conf __rte_unused)
884 struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
885 struct rte_eth_link link_info;
888 rc = bnxt_get_hwrm_link_config(bp, &link_info);
892 memset(fc_conf, 0, sizeof(*fc_conf));
893 if (bp->link_info.auto_pause)
894 fc_conf->autoneg = 1;
895 switch (bp->link_info.pause) {
897 fc_conf->mode = RTE_FC_NONE;
899 case HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_TX:
900 fc_conf->mode = RTE_FC_TX_PAUSE;
902 case HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_RX:
903 fc_conf->mode = RTE_FC_RX_PAUSE;
905 case (HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_TX |
906 HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_RX):
907 fc_conf->mode = RTE_FC_FULL;
913 static int bnxt_flow_ctrl_set_op(struct rte_eth_dev *dev,
914 struct rte_eth_fc_conf *fc_conf)
916 struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
918 if (BNXT_NPAR_PF(bp) || BNXT_VF(bp)) {
919 RTE_LOG(ERR, PMD, "Flow Control Settings cannot be modified\n");
923 switch (fc_conf->mode) {
925 bp->link_info.auto_pause = 0;
926 bp->link_info.force_pause = 0;
928 case RTE_FC_RX_PAUSE:
929 if (fc_conf->autoneg) {
930 bp->link_info.auto_pause =
931 HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_RX;
932 bp->link_info.force_pause = 0;
934 bp->link_info.auto_pause = 0;
935 bp->link_info.force_pause =
936 HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_RX;
939 case RTE_FC_TX_PAUSE:
940 if (fc_conf->autoneg) {
941 bp->link_info.auto_pause =
942 HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_TX;
943 bp->link_info.force_pause = 0;
945 bp->link_info.auto_pause = 0;
946 bp->link_info.force_pause =
947 HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_TX;
951 if (fc_conf->autoneg) {
952 bp->link_info.auto_pause =
953 HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_TX |
954 HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_RX;
955 bp->link_info.force_pause = 0;
957 bp->link_info.auto_pause = 0;
958 bp->link_info.force_pause =
959 HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_TX |
960 HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_RX;
964 return bnxt_set_hwrm_link_config(bp, true);
971 static struct eth_dev_ops bnxt_dev_ops = {
972 .dev_infos_get = bnxt_dev_info_get_op,
973 .dev_close = bnxt_dev_close_op,
974 .dev_configure = bnxt_dev_configure_op,
975 .dev_start = bnxt_dev_start_op,
976 .dev_stop = bnxt_dev_stop_op,
977 .dev_set_link_up = bnxt_dev_set_link_up_op,
978 .dev_set_link_down = bnxt_dev_set_link_down_op,
979 .stats_get = bnxt_stats_get_op,
980 .stats_reset = bnxt_stats_reset_op,
981 .rx_queue_setup = bnxt_rx_queue_setup_op,
982 .rx_queue_release = bnxt_rx_queue_release_op,
983 .tx_queue_setup = bnxt_tx_queue_setup_op,
984 .tx_queue_release = bnxt_tx_queue_release_op,
985 .reta_update = bnxt_reta_update_op,
986 .reta_query = bnxt_reta_query_op,
987 .rss_hash_update = bnxt_rss_hash_update_op,
988 .rss_hash_conf_get = bnxt_rss_hash_conf_get_op,
989 .link_update = bnxt_link_update_op,
990 .promiscuous_enable = bnxt_promiscuous_enable_op,
991 .promiscuous_disable = bnxt_promiscuous_disable_op,
992 .allmulticast_enable = bnxt_allmulticast_enable_op,
993 .allmulticast_disable = bnxt_allmulticast_disable_op,
994 .mac_addr_add = bnxt_mac_addr_add_op,
995 .mac_addr_remove = bnxt_mac_addr_remove_op,
996 .flow_ctrl_get = bnxt_flow_ctrl_get_op,
997 .flow_ctrl_set = bnxt_flow_ctrl_set_op,
1000 static bool bnxt_vf_pciid(uint16_t id)
1002 if (id == BROADCOM_DEV_ID_57304_VF ||
1003 id == BROADCOM_DEV_ID_57406_VF ||
1004 id == BROADCOM_DEV_ID_5731X_VF ||
1005 id == BROADCOM_DEV_ID_5741X_VF)
1010 static int bnxt_init_board(struct rte_eth_dev *eth_dev)
1013 struct bnxt *bp = eth_dev->data->dev_private;
1015 /* enable device (incl. PCI PM wakeup), and bus-mastering */
1016 if (!eth_dev->pci_dev->mem_resource[0].addr) {
1018 "Cannot find PCI device base address, aborting\n");
1020 goto init_err_disable;
1023 bp->eth_dev = eth_dev;
1024 bp->pdev = eth_dev->pci_dev;
1026 bp->bar0 = (void *)eth_dev->pci_dev->mem_resource[0].addr;
1028 RTE_LOG(ERR, PMD, "Cannot map device registers, aborting\n");
1030 goto init_err_release;
1044 bnxt_dev_init(struct rte_eth_dev *eth_dev)
1046 static int version_printed;
1050 if (version_printed++ == 0)
1051 RTE_LOG(INFO, PMD, "%s", bnxt_version);
1053 rte_eth_copy_pci_info(eth_dev, eth_dev->pci_dev);
1054 bp = eth_dev->data->dev_private;
1056 if (bnxt_vf_pciid(eth_dev->pci_dev->id.device_id))
1057 bp->flags |= BNXT_FLAG_VF;
1059 rc = bnxt_init_board(eth_dev);
1062 "Board initialization failed rc: %x\n", rc);
1065 eth_dev->dev_ops = &bnxt_dev_ops;
1066 eth_dev->rx_pkt_burst = &bnxt_recv_pkts;
1067 eth_dev->tx_pkt_burst = &bnxt_xmit_pkts;
1069 rc = bnxt_alloc_hwrm_resources(bp);
1072 "hwrm resource allocation failure rc: %x\n", rc);
1075 rc = bnxt_hwrm_ver_get(bp);
1078 bnxt_hwrm_queue_qportcfg(bp);
1080 bnxt_hwrm_func_qcfg(bp);
1082 /* Get the MAX capabilities for this function */
1083 rc = bnxt_hwrm_func_qcaps(bp);
1085 RTE_LOG(ERR, PMD, "hwrm query capability failure rc: %x\n", rc);
1088 eth_dev->data->mac_addrs = rte_zmalloc("bnxt_mac_addr_tbl",
1089 ETHER_ADDR_LEN * MAX_NUM_MAC_ADDR, 0);
1090 if (eth_dev->data->mac_addrs == NULL) {
1092 "Failed to alloc %u bytes needed to store MAC addr tbl",
1093 ETHER_ADDR_LEN * MAX_NUM_MAC_ADDR);
1097 /* Copy the permanent MAC from the qcap response address now. */
1099 memcpy(bp->mac_addr, bp->pf.mac_addr, sizeof(bp->mac_addr));
1101 memcpy(bp->mac_addr, bp->vf.mac_addr, sizeof(bp->mac_addr));
1102 memcpy(ð_dev->data->mac_addrs[0], bp->mac_addr, ETHER_ADDR_LEN);
1103 bp->grp_info = rte_zmalloc("bnxt_grp_info",
1104 sizeof(*bp->grp_info) * bp->max_ring_grps, 0);
1105 if (!bp->grp_info) {
1107 "Failed to alloc %zu bytes needed to store group info table\n",
1108 sizeof(*bp->grp_info) * bp->max_ring_grps);
1113 rc = bnxt_hwrm_func_driver_register(bp, 0,
1117 "Failed to register driver");
1123 DRV_MODULE_NAME " found at mem %" PRIx64 ", node addr %pM\n",
1124 eth_dev->pci_dev->mem_resource[0].phys_addr,
1125 eth_dev->pci_dev->mem_resource[0].addr);
1127 bp->dev_stopped = 0;
1132 eth_dev->driver->eth_dev_uninit(eth_dev);
1138 bnxt_dev_uninit(struct rte_eth_dev *eth_dev) {
1139 struct bnxt *bp = eth_dev->data->dev_private;
1142 if (eth_dev->data->mac_addrs != NULL) {
1143 rte_free(eth_dev->data->mac_addrs);
1144 eth_dev->data->mac_addrs = NULL;
1146 if (bp->grp_info != NULL) {
1147 rte_free(bp->grp_info);
1148 bp->grp_info = NULL;
1150 rc = bnxt_hwrm_func_driver_unregister(bp, 0);
1151 bnxt_free_hwrm_resources(bp);
1152 if (bp->dev_stopped == 0)
1153 bnxt_dev_close_op(eth_dev);
1154 eth_dev->dev_ops = NULL;
1155 eth_dev->rx_pkt_burst = NULL;
1156 eth_dev->tx_pkt_burst = NULL;
1161 static struct eth_driver bnxt_rte_pmd = {
1163 .id_table = bnxt_pci_id_map,
1164 .drv_flags = RTE_PCI_DRV_NEED_MAPPING |
1165 RTE_PCI_DRV_DETACHABLE | RTE_PCI_DRV_INTR_LSC,
1166 .probe = rte_eth_dev_pci_probe,
1167 .remove = rte_eth_dev_pci_remove
1169 .eth_dev_init = bnxt_dev_init,
1170 .eth_dev_uninit = bnxt_dev_uninit,
1171 .dev_private_size = sizeof(struct bnxt),
1174 RTE_PMD_REGISTER_PCI(net_bnxt, bnxt_rte_pmd.pci_drv);
1175 RTE_PMD_REGISTER_PCI_TABLE(net_bnxt, bnxt_pci_id_map);
1176 RTE_PMD_REGISTER_KMOD_DEP(net_bnxt, "* igb_uio | uio_pci_generic | vfio");