drivers/net/bnxt/bnxt_ethdev.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2014-2018 Broadcom
   3  * All rights reserved.
   4  */
   5
   6 #include <inttypes.h>
   7 #include <stdbool.h>
   8
   9 #include <rte_dev.h>
  10 #include <ethdev_driver.h>
  11 #include <ethdev_pci.h>
  12 #include <rte_malloc.h>
  13 #include <rte_cycles.h>
  14 #include <rte_alarm.h>
  15 #include <rte_kvargs.h>
  16 #include <rte_vect.h>
  17
  18 #include "bnxt.h"
  19 #include "bnxt_filter.h"
  20 #include "bnxt_hwrm.h"
  21 #include "bnxt_irq.h"
  22 #include "bnxt_reps.h"
  23 #include "bnxt_ring.h"
  24 #include "bnxt_rxq.h"
  25 #include "bnxt_rxr.h"
  26 #include "bnxt_stats.h"
  27 #include "bnxt_txq.h"
  28 #include "bnxt_txr.h"
  29 #include "bnxt_vnic.h"
  30 #include "hsi_struct_def_dpdk.h"
  31 #include "bnxt_nvm_defs.h"
  32 #include "bnxt_tf_common.h"
  33 #include "ulp_flow_db.h"
  34 #include "rte_pmd_bnxt.h"
  35
  36 #define DRV_MODULE_NAME         "bnxt"
  37 static const char bnxt_version[] =
  38         "Broadcom NetXtreme driver " DRV_MODULE_NAME;
  39
  40 /*
  41  * The set of PCI devices this driver supports
  42  */
  43 static const struct rte_pci_id bnxt_pci_id_map[] = {
  44         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM,
  45                          BROADCOM_DEV_ID_STRATUS_NIC_VF1) },
  46         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM,
  47                          BROADCOM_DEV_ID_STRATUS_NIC_VF2) },
  48         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_STRATUS_NIC) },
  49         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414_VF) },
  50         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57304_VF) },
  51         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_NS2) },
  52         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57406_VF) },
  53         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57407_MF) },
  54         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_5741X_VF) },
  55         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_5731X_VF) },
  56         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_MF) },
  57         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57412) },
  58         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414) },
  59         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_RJ45) },
  60         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_RJ45) },
  61         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57412_MF) },
  62         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57317_RJ45) },
  63         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_SFP) },
  64         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_SFP) },
  65         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57317_SFP) },
  66         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414_MF) },
  67         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_MF) },
  68         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58802) },
  69         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58804) },
  70         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58808) },
  71         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58802_VF) },
  72         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57508) },
  73         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57504) },
  74         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57502) },
  75         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57500_VF1) },
  76         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57500_VF2) },
  77         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57508_MF1) },
  78         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57504_MF1) },
  79         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57502_MF1) },
  80         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57508_MF2) },
  81         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57504_MF2) },
  82         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57502_MF2) },
  83         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58812) },
  84         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58814) },
  85         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58818) },
  86         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58818_VF) },
  87         { .vendor_id = 0, /* sentinel */ },
  88 };
  89
  90 #define BNXT_DEVARG_TRUFLOW     "host-based-truflow"
  91 #define BNXT_DEVARG_FLOW_XSTAT  "flow-xstat"
  92 #define BNXT_DEVARG_MAX_NUM_KFLOWS  "max-num-kflows"
  93 #define BNXT_DEVARG_REPRESENTOR "representor"
  94 #define BNXT_DEVARG_REP_BASED_PF  "rep-based-pf"
  95 #define BNXT_DEVARG_REP_IS_PF  "rep-is-pf"
  96 #define BNXT_DEVARG_REP_Q_R2F  "rep-q-r2f"
  97 #define BNXT_DEVARG_REP_Q_F2R  "rep-q-f2r"
  98 #define BNXT_DEVARG_REP_FC_R2F  "rep-fc-r2f"
  99 #define BNXT_DEVARG_REP_FC_F2R  "rep-fc-f2r"
 100
 101 static const char *const bnxt_dev_args[] = {
 102         BNXT_DEVARG_REPRESENTOR,
 103         BNXT_DEVARG_TRUFLOW,
 104         BNXT_DEVARG_FLOW_XSTAT,
 105         BNXT_DEVARG_MAX_NUM_KFLOWS,
 106         BNXT_DEVARG_REP_BASED_PF,
 107         BNXT_DEVARG_REP_IS_PF,
 108         BNXT_DEVARG_REP_Q_R2F,
 109         BNXT_DEVARG_REP_Q_F2R,
 110         BNXT_DEVARG_REP_FC_R2F,
 111         BNXT_DEVARG_REP_FC_F2R,
 112         NULL
 113 };
 114
 115 /*
 116  * truflow == false to disable the feature
 117  * truflow == true to enable the feature
 118  */
 119 #define BNXT_DEVARG_TRUFLOW_INVALID(truflow)    ((truflow) > 1)
 120
 121 /*
 122  * flow_xstat == false to disable the feature
 123  * flow_xstat == true to enable the feature
 124  */
 125 #define BNXT_DEVARG_FLOW_XSTAT_INVALID(flow_xstat)      ((flow_xstat) > 1)
 126
 127 /*
 128  * rep_is_pf == false to indicate VF representor
 129  * rep_is_pf == true to indicate PF representor
 130  */
 131 #define BNXT_DEVARG_REP_IS_PF_INVALID(rep_is_pf)        ((rep_is_pf) > 1)
 132
 133 /*
 134  * rep_based_pf == Physical index of the PF
 135  */
 136 #define BNXT_DEVARG_REP_BASED_PF_INVALID(rep_based_pf)  ((rep_based_pf) > 15)
 137 /*
 138  * rep_q_r2f == Logical COS Queue index for the rep to endpoint direction
 139  */
 140 #define BNXT_DEVARG_REP_Q_R2F_INVALID(rep_q_r2f)        ((rep_q_r2f) > 3)
 141
 142 /*
 143  * rep_q_f2r == Logical COS Queue index for the endpoint to rep direction
 144  */
 145 #define BNXT_DEVARG_REP_Q_F2R_INVALID(rep_q_f2r)        ((rep_q_f2r) > 3)
 146
 147 /*
 148  * rep_fc_r2f == Flow control for the representor to endpoint direction
 149  */
 150 #define BNXT_DEVARG_REP_FC_R2F_INVALID(rep_fc_r2f)      ((rep_fc_r2f) > 1)
 151
 152 /*
 153  * rep_fc_f2r == Flow control for the endpoint to representor direction
 154  */
 155 #define BNXT_DEVARG_REP_FC_F2R_INVALID(rep_fc_f2r)      ((rep_fc_f2r) > 1)
 156
 157 int bnxt_cfa_code_dynfield_offset = -1;
 158
 159 /*
 160  * max_num_kflows must be >= 32
 161  * and must be a power-of-2 supported value
 162  * return: 1 -> invalid
 163  *         0 -> valid
 164  */
 165 static int bnxt_devarg_max_num_kflow_invalid(uint16_t max_num_kflows)
 166 {
 167         if (max_num_kflows < 32 || !rte_is_power_of_2(max_num_kflows))
 168                 return 1;
 169         return 0;
 170 }
 171
 172 static int bnxt_vlan_offload_set_op(struct rte_eth_dev *dev, int mask);
 173 static int bnxt_dev_uninit(struct rte_eth_dev *eth_dev);
 174 static int bnxt_init_resources(struct bnxt *bp, bool reconfig_dev);
 175 static int bnxt_uninit_resources(struct bnxt *bp, bool reconfig_dev);
 176 static void bnxt_cancel_fw_health_check(struct bnxt *bp);
 177 static int bnxt_restore_vlan_filters(struct bnxt *bp);
 178 static void bnxt_dev_recover(void *arg);
 179 static void bnxt_free_error_recovery_info(struct bnxt *bp);
 180 static void bnxt_free_rep_info(struct bnxt *bp);
 181
 182 int is_bnxt_in_error(struct bnxt *bp)
 183 {
 184         if (bp->flags & BNXT_FLAG_FATAL_ERROR)
 185                 return -EIO;
 186         if (bp->flags & BNXT_FLAG_FW_RESET)
 187                 return -EBUSY;
 188
 189         return 0;
 190 }
 191
 192 /***********************/
 193
 194 /*
 195  * High level utility functions
 196  */
 197
 198 static uint16_t bnxt_rss_ctxts(const struct bnxt *bp)
 199 {
 200         unsigned int num_rss_rings = RTE_MIN(bp->rx_nr_rings,
 201                                              BNXT_RSS_TBL_SIZE_P5);
 202
 203         if (!BNXT_CHIP_P5(bp))
 204                 return 1;
 205
 206         return RTE_ALIGN_MUL_CEIL(num_rss_rings,
 207                                   BNXT_RSS_ENTRIES_PER_CTX_P5) /
 208                                   BNXT_RSS_ENTRIES_PER_CTX_P5;
 209 }
 210
 211 uint16_t bnxt_rss_hash_tbl_size(const struct bnxt *bp)
 212 {
 213         if (!BNXT_CHIP_P5(bp))
 214                 return HW_HASH_INDEX_SIZE;
 215
 216         return bnxt_rss_ctxts(bp) * BNXT_RSS_ENTRIES_PER_CTX_P5;
 217 }
 218
 219 static void bnxt_free_parent_info(struct bnxt *bp)
 220 {
 221         rte_free(bp->parent);
 222 }
 223
 224 static void bnxt_free_pf_info(struct bnxt *bp)
 225 {
 226         rte_free(bp->pf);
 227 }
 228
 229 static void bnxt_free_link_info(struct bnxt *bp)
 230 {
 231         rte_free(bp->link_info);
 232 }
 233
 234 static void bnxt_free_leds_info(struct bnxt *bp)
 235 {
 236         if (BNXT_VF(bp))
 237                 return;
 238
 239         rte_free(bp->leds);
 240         bp->leds = NULL;
 241 }
 242
 243 static void bnxt_free_flow_stats_info(struct bnxt *bp)
 244 {
 245         rte_free(bp->flow_stat);
 246         bp->flow_stat = NULL;
 247 }
 248
 249 static void bnxt_free_cos_queues(struct bnxt *bp)
 250 {
 251         rte_free(bp->rx_cos_queue);
 252         rte_free(bp->tx_cos_queue);
 253 }
 254
 255 static void bnxt_free_mem(struct bnxt *bp, bool reconfig)
 256 {
 257         bnxt_free_filter_mem(bp);
 258         bnxt_free_vnic_attributes(bp);
 259         bnxt_free_vnic_mem(bp);
 260
 261         /* tx/rx rings are configured as part of *_queue_setup callbacks.
 262          * If the number of rings change across fw update,
 263          * we don't have much choice except to warn the user.
 264          */
 265         if (!reconfig) {
 266                 bnxt_free_stats(bp);
 267                 bnxt_free_tx_rings(bp);
 268                 bnxt_free_rx_rings(bp);
 269         }
 270         bnxt_free_async_cp_ring(bp);
 271         bnxt_free_rxtx_nq_ring(bp);
 272
 273         rte_free(bp->grp_info);
 274         bp->grp_info = NULL;
 275 }
 276
 277 static int bnxt_alloc_parent_info(struct bnxt *bp)
 278 {
 279         bp->parent = rte_zmalloc("bnxt_parent_info",
 280                                  sizeof(struct bnxt_parent_info), 0);
 281         if (bp->parent == NULL)
 282                 return -ENOMEM;
 283
 284         return 0;
 285 }
 286
 287 static int bnxt_alloc_pf_info(struct bnxt *bp)
 288 {
 289         bp->pf = rte_zmalloc("bnxt_pf_info", sizeof(struct bnxt_pf_info), 0);
 290         if (bp->pf == NULL)
 291                 return -ENOMEM;
 292
 293         return 0;
 294 }
 295
 296 static int bnxt_alloc_link_info(struct bnxt *bp)
 297 {
 298         bp->link_info =
 299                 rte_zmalloc("bnxt_link_info", sizeof(struct bnxt_link_info), 0);
 300         if (bp->link_info == NULL)
 301                 return -ENOMEM;
 302
 303         return 0;
 304 }
 305
 306 static int bnxt_alloc_leds_info(struct bnxt *bp)
 307 {
 308         if (BNXT_VF(bp))
 309                 return 0;
 310
 311         bp->leds = rte_zmalloc("bnxt_leds",
 312                                BNXT_MAX_LED * sizeof(struct bnxt_led_info),
 313                                0);
 314         if (bp->leds == NULL)
 315                 return -ENOMEM;
 316
 317         return 0;
 318 }
 319
 320 static int bnxt_alloc_cos_queues(struct bnxt *bp)
 321 {
 322         bp->rx_cos_queue =
 323                 rte_zmalloc("bnxt_rx_cosq",
 324                             BNXT_COS_QUEUE_COUNT *
 325                             sizeof(struct bnxt_cos_queue_info),
 326                             0);
 327         if (bp->rx_cos_queue == NULL)
 328                 return -ENOMEM;
 329
 330         bp->tx_cos_queue =
 331                 rte_zmalloc("bnxt_tx_cosq",
 332                             BNXT_COS_QUEUE_COUNT *
 333                             sizeof(struct bnxt_cos_queue_info),
 334                             0);
 335         if (bp->tx_cos_queue == NULL)
 336                 return -ENOMEM;
 337
 338         return 0;
 339 }
 340
 341 static int bnxt_alloc_flow_stats_info(struct bnxt *bp)
 342 {
 343         bp->flow_stat = rte_zmalloc("bnxt_flow_xstat",
 344                                     sizeof(struct bnxt_flow_stat_info), 0);
 345         if (bp->flow_stat == NULL)
 346                 return -ENOMEM;
 347
 348         return 0;
 349 }
 350
 351 static int bnxt_alloc_mem(struct bnxt *bp, bool reconfig)
 352 {
 353         int rc;
 354
 355         rc = bnxt_alloc_ring_grps(bp);
 356         if (rc)
 357                 goto alloc_mem_err;
 358
 359         rc = bnxt_alloc_async_ring_struct(bp);
 360         if (rc)
 361                 goto alloc_mem_err;
 362
 363         rc = bnxt_alloc_vnic_mem(bp);
 364         if (rc)
 365                 goto alloc_mem_err;
 366
 367         rc = bnxt_alloc_vnic_attributes(bp);
 368         if (rc)
 369                 goto alloc_mem_err;
 370
 371         rc = bnxt_alloc_filter_mem(bp);
 372         if (rc)
 373                 goto alloc_mem_err;
 374
 375         rc = bnxt_alloc_async_cp_ring(bp);
 376         if (rc)
 377                 goto alloc_mem_err;
 378
 379         rc = bnxt_alloc_rxtx_nq_ring(bp);
 380         if (rc)
 381                 goto alloc_mem_err;
 382
 383         if (BNXT_FLOW_XSTATS_EN(bp)) {
 384                 rc = bnxt_alloc_flow_stats_info(bp);
 385                 if (rc)
 386                         goto alloc_mem_err;
 387         }
 388
 389         return 0;
 390
 391 alloc_mem_err:
 392         bnxt_free_mem(bp, reconfig);
 393         return rc;
 394 }
 395
 396 static int bnxt_setup_one_vnic(struct bnxt *bp, uint16_t vnic_id)
 397 {
 398         struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
 399         struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id];
 400         uint64_t rx_offloads = dev_conf->rxmode.offloads;
 401         struct bnxt_rx_queue *rxq;
 402         unsigned int j;
 403         int rc;
 404
 405         rc = bnxt_vnic_grp_alloc(bp, vnic);
 406         if (rc)
 407                 goto err_out;
 408
 409         PMD_DRV_LOG(DEBUG, "vnic[%d] = %p vnic->fw_grp_ids = %p\n",
 410                     vnic_id, vnic, vnic->fw_grp_ids);
 411
 412         rc = bnxt_hwrm_vnic_alloc(bp, vnic);
 413         if (rc)
 414                 goto err_out;
 415
 416         /* Alloc RSS context only if RSS mode is enabled */
 417         if (dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS) {
 418                 int j, nr_ctxs = bnxt_rss_ctxts(bp);
 419
 420                 if (bp->rx_nr_rings > BNXT_RSS_TBL_SIZE_P5) {
 421                         PMD_DRV_LOG(ERR, "RxQ cnt %d > reta_size %d\n",
 422                                     bp->rx_nr_rings, BNXT_RSS_TBL_SIZE_P5);
 423                         PMD_DRV_LOG(ERR,
 424                                     "Only queues 0-%d will be in RSS table\n",
 425                                     BNXT_RSS_TBL_SIZE_P5 - 1);
 426                 }
 427
 428                 rc = 0;
 429                 for (j = 0; j < nr_ctxs; j++) {
 430                         rc = bnxt_hwrm_vnic_ctx_alloc(bp, vnic, j);
 431                         if (rc)
 432                                 break;
 433                 }
 434                 if (rc) {
 435                         PMD_DRV_LOG(ERR,
 436                                     "HWRM vnic %d ctx %d alloc failure rc: %x\n",
 437                                     vnic_id, j, rc);
 438                         goto err_out;
 439                 }
 440                 vnic->num_lb_ctxts = nr_ctxs;
 441         }
 442
 443         /*
 444          * Firmware sets pf pair in default vnic cfg. If the VLAN strip
 445          * setting is not available at this time, it will not be
 446          * configured correctly in the CFA.
 447          */
 448         if (rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
 449                 vnic->vlan_strip = true;
 450         else
 451                 vnic->vlan_strip = false;
 452
 453         rc = bnxt_hwrm_vnic_cfg(bp, vnic);
 454         if (rc)
 455                 goto err_out;
 456
 457         rc = bnxt_set_hwrm_vnic_filters(bp, vnic);
 458         if (rc)
 459                 goto err_out;
 460
 461         for (j = 0; j < bp->rx_num_qs_per_vnic; j++) {
 462                 rxq = bp->eth_dev->data->rx_queues[j];
 463
 464                 PMD_DRV_LOG(DEBUG,
 465                             "rxq[%d]->vnic=%p vnic->fw_grp_ids=%p\n",
 466                             j, rxq->vnic, rxq->vnic->fw_grp_ids);
 467
 468                 if (BNXT_HAS_RING_GRPS(bp) && rxq->rx_deferred_start)
 469                         rxq->vnic->fw_grp_ids[j] = INVALID_HW_RING_ID;
 470                 else
 471                         vnic->rx_queue_cnt++;
 472         }
 473
 474         PMD_DRV_LOG(DEBUG, "vnic->rx_queue_cnt = %d\n", vnic->rx_queue_cnt);
 475
 476         rc = bnxt_vnic_rss_configure(bp, vnic);
 477         if (rc)
 478                 goto err_out;
 479
 480         bnxt_hwrm_vnic_plcmode_cfg(bp, vnic);
 481
 482         if (rx_offloads & DEV_RX_OFFLOAD_TCP_LRO)
 483                 bnxt_hwrm_vnic_tpa_cfg(bp, vnic, 1);
 484         else
 485                 bnxt_hwrm_vnic_tpa_cfg(bp, vnic, 0);
 486
 487         return 0;
 488 err_out:
 489         PMD_DRV_LOG(ERR, "HWRM vnic %d cfg failure rc: %x\n",
 490                     vnic_id, rc);
 491         return rc;
 492 }
 493
 494 static int bnxt_register_fc_ctx_mem(struct bnxt *bp)
 495 {
 496         int rc = 0;
 497
 498         rc = bnxt_hwrm_ctx_rgtr(bp, bp->flow_stat->rx_fc_in_tbl.dma,
 499                                 &bp->flow_stat->rx_fc_in_tbl.ctx_id);
 500         if (rc)
 501                 return rc;
 502
 503         PMD_DRV_LOG(DEBUG,
 504                     "rx_fc_in_tbl.va = %p rx_fc_in_tbl.dma = %p"
 505                     " rx_fc_in_tbl.ctx_id = %d\n",
 506                     bp->flow_stat->rx_fc_in_tbl.va,
 507                     (void *)((uintptr_t)bp->flow_stat->rx_fc_in_tbl.dma),
 508                     bp->flow_stat->rx_fc_in_tbl.ctx_id);
 509
 510         rc = bnxt_hwrm_ctx_rgtr(bp, bp->flow_stat->rx_fc_out_tbl.dma,
 511                                 &bp->flow_stat->rx_fc_out_tbl.ctx_id);
 512         if (rc)
 513                 return rc;
 514
 515         PMD_DRV_LOG(DEBUG,
 516                     "rx_fc_out_tbl.va = %p rx_fc_out_tbl.dma = %p"
 517                     " rx_fc_out_tbl.ctx_id = %d\n",
 518                     bp->flow_stat->rx_fc_out_tbl.va,
 519                     (void *)((uintptr_t)bp->flow_stat->rx_fc_out_tbl.dma),
 520                     bp->flow_stat->rx_fc_out_tbl.ctx_id);
 521
 522         rc = bnxt_hwrm_ctx_rgtr(bp, bp->flow_stat->tx_fc_in_tbl.dma,
 523                                 &bp->flow_stat->tx_fc_in_tbl.ctx_id);
 524         if (rc)
 525                 return rc;
 526
 527         PMD_DRV_LOG(DEBUG,
 528                     "tx_fc_in_tbl.va = %p tx_fc_in_tbl.dma = %p"
 529                     " tx_fc_in_tbl.ctx_id = %d\n",
 530                     bp->flow_stat->tx_fc_in_tbl.va,
 531                     (void *)((uintptr_t)bp->flow_stat->tx_fc_in_tbl.dma),
 532                     bp->flow_stat->tx_fc_in_tbl.ctx_id);
 533
 534         rc = bnxt_hwrm_ctx_rgtr(bp, bp->flow_stat->tx_fc_out_tbl.dma,
 535                                 &bp->flow_stat->tx_fc_out_tbl.ctx_id);
 536         if (rc)
 537                 return rc;
 538
 539         PMD_DRV_LOG(DEBUG,
 540                     "tx_fc_out_tbl.va = %p tx_fc_out_tbl.dma = %p"
 541                     " tx_fc_out_tbl.ctx_id = %d\n",
 542                     bp->flow_stat->tx_fc_out_tbl.va,
 543                     (void *)((uintptr_t)bp->flow_stat->tx_fc_out_tbl.dma),
 544                     bp->flow_stat->tx_fc_out_tbl.ctx_id);
 545
 546         memset(bp->flow_stat->rx_fc_out_tbl.va,
 547                0,
 548                bp->flow_stat->rx_fc_out_tbl.size);
 549         rc = bnxt_hwrm_cfa_counter_cfg(bp, BNXT_DIR_RX,
 550                                        CFA_COUNTER_CFG_IN_COUNTER_TYPE_FC,
 551                                        bp->flow_stat->rx_fc_out_tbl.ctx_id,
 552                                        bp->flow_stat->max_fc,
 553                                        true);
 554         if (rc)
 555                 return rc;
 556
 557         memset(bp->flow_stat->tx_fc_out_tbl.va,
 558                0,
 559                bp->flow_stat->tx_fc_out_tbl.size);
 560         rc = bnxt_hwrm_cfa_counter_cfg(bp, BNXT_DIR_TX,
 561                                        CFA_COUNTER_CFG_IN_COUNTER_TYPE_FC,
 562                                        bp->flow_stat->tx_fc_out_tbl.ctx_id,
 563                                        bp->flow_stat->max_fc,
 564                                        true);
 565
 566         return rc;
 567 }
 568
 569 static int bnxt_alloc_ctx_mem_buf(char *type, size_t size,
 570                                   struct bnxt_ctx_mem_buf_info *ctx)
 571 {
 572         if (!ctx)
 573                 return -EINVAL;
 574
 575         ctx->va = rte_zmalloc(type, size, 0);
 576         if (ctx->va == NULL)
 577                 return -ENOMEM;
 578         rte_mem_lock_page(ctx->va);
 579         ctx->size = size;
 580         ctx->dma = rte_mem_virt2iova(ctx->va);
 581         if (ctx->dma == RTE_BAD_IOVA)
 582                 return -ENOMEM;
 583
 584         return 0;
 585 }
 586
 587 static int bnxt_init_fc_ctx_mem(struct bnxt *bp)
 588 {
 589         struct rte_pci_device *pdev = bp->pdev;
 590         char type[RTE_MEMZONE_NAMESIZE];
 591         uint16_t max_fc;
 592         int rc = 0;
 593
 594         max_fc = bp->flow_stat->max_fc;
 595
 596         sprintf(type, "bnxt_rx_fc_in_" PCI_PRI_FMT, pdev->addr.domain,
 597                 pdev->addr.bus, pdev->addr.devid, pdev->addr.function);
 598         /* 4 bytes for each counter-id */
 599         rc = bnxt_alloc_ctx_mem_buf(type,
 600                                     max_fc * 4,
 601                                     &bp->flow_stat->rx_fc_in_tbl);
 602         if (rc)
 603                 return rc;
 604
 605         sprintf(type, "bnxt_rx_fc_out_" PCI_PRI_FMT, pdev->addr.domain,
 606                 pdev->addr.bus, pdev->addr.devid, pdev->addr.function);
 607         /* 16 bytes for each counter - 8 bytes pkt_count, 8 bytes byte_count */
 608         rc = bnxt_alloc_ctx_mem_buf(type,
 609                                     max_fc * 16,
 610                                     &bp->flow_stat->rx_fc_out_tbl);
 611         if (rc)
 612                 return rc;
 613
 614         sprintf(type, "bnxt_tx_fc_in_" PCI_PRI_FMT, pdev->addr.domain,
 615                 pdev->addr.bus, pdev->addr.devid, pdev->addr.function);
 616         /* 4 bytes for each counter-id */
 617         rc = bnxt_alloc_ctx_mem_buf(type,
 618                                     max_fc * 4,
 619                                     &bp->flow_stat->tx_fc_in_tbl);
 620         if (rc)
 621                 return rc;
 622
 623         sprintf(type, "bnxt_tx_fc_out_" PCI_PRI_FMT, pdev->addr.domain,
 624                 pdev->addr.bus, pdev->addr.devid, pdev->addr.function);
 625         /* 16 bytes for each counter - 8 bytes pkt_count, 8 bytes byte_count */
 626         rc = bnxt_alloc_ctx_mem_buf(type,
 627                                     max_fc * 16,
 628                                     &bp->flow_stat->tx_fc_out_tbl);
 629         if (rc)
 630                 return rc;
 631
 632         rc = bnxt_register_fc_ctx_mem(bp);
 633
 634         return rc;
 635 }
 636
 637 static int bnxt_init_ctx_mem(struct bnxt *bp)
 638 {
 639         int rc = 0;
 640
 641         if (!(bp->fw_cap & BNXT_FW_CAP_ADV_FLOW_COUNTERS) ||
 642             !(BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp)) ||
 643             !BNXT_FLOW_XSTATS_EN(bp))
 644                 return 0;
 645
 646         rc = bnxt_hwrm_cfa_counter_qcaps(bp, &bp->flow_stat->max_fc);
 647         if (rc)
 648                 return rc;
 649
 650         rc = bnxt_init_fc_ctx_mem(bp);
 651
 652         return rc;
 653 }
 654
 655 static int bnxt_update_phy_setting(struct bnxt *bp)
 656 {
 657         struct rte_eth_link new;
 658         int rc;
 659
 660         rc = bnxt_get_hwrm_link_config(bp, &new);
 661         if (rc) {
 662                 PMD_DRV_LOG(ERR, "Failed to get link settings\n");
 663                 return rc;
 664         }
 665
 666         /*
 667          * On BCM957508-N2100 adapters, FW will not allow any user other
 668          * than BMC to shutdown the port. bnxt_get_hwrm_link_config() call
 669          * always returns link up. Force phy update always in that case.
 670          */
 671         if (!new.link_status || IS_BNXT_DEV_957508_N2100(bp)) {
 672                 rc = bnxt_set_hwrm_link_config(bp, true);
 673                 if (rc) {
 674                         PMD_DRV_LOG(ERR, "Failed to update PHY settings\n");
 675                         return rc;
 676                 }
 677         }
 678
 679         return rc;
 680 }
 681
 682 static int bnxt_start_nic(struct bnxt *bp)
 683 {
 684         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(bp->eth_dev);
 685         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
 686         uint32_t intr_vector = 0;
 687         uint32_t queue_id, base = BNXT_MISC_VEC_ID;
 688         uint32_t vec = BNXT_MISC_VEC_ID;
 689         unsigned int i, j;
 690         int rc;
 691
 692         if (bp->eth_dev->data->mtu > RTE_ETHER_MTU) {
 693                 bp->eth_dev->data->dev_conf.rxmode.offloads |=
 694                         DEV_RX_OFFLOAD_JUMBO_FRAME;
 695                 bp->flags |= BNXT_FLAG_JUMBO;
 696         } else {
 697                 bp->eth_dev->data->dev_conf.rxmode.offloads &=
 698                         ~DEV_RX_OFFLOAD_JUMBO_FRAME;
 699                 bp->flags &= ~BNXT_FLAG_JUMBO;
 700         }
 701
 702         /* THOR does not support ring groups.
 703          * But we will use the array to save RSS context IDs.
 704          */
 705         if (BNXT_CHIP_P5(bp))
 706                 bp->max_ring_grps = BNXT_MAX_RSS_CTXTS_P5;
 707
 708         rc = bnxt_alloc_all_hwrm_stat_ctxs(bp);
 709         if (rc) {
 710                 PMD_DRV_LOG(ERR, "HWRM stat ctx alloc failure rc: %x\n", rc);
 711                 goto err_out;
 712         }
 713
 714         rc = bnxt_alloc_hwrm_rings(bp);
 715         if (rc) {
 716                 PMD_DRV_LOG(ERR, "HWRM ring alloc failure rc: %x\n", rc);
 717                 goto err_out;
 718         }
 719
 720         rc = bnxt_alloc_all_hwrm_ring_grps(bp);
 721         if (rc) {
 722                 PMD_DRV_LOG(ERR, "HWRM ring grp alloc failure: %x\n", rc);
 723                 goto err_out;
 724         }
 725
 726         if (!(bp->vnic_cap_flags & BNXT_VNIC_CAP_COS_CLASSIFY))
 727                 goto skip_cosq_cfg;
 728
 729         for (j = 0, i = 0; i < BNXT_COS_QUEUE_COUNT; i++) {
 730                 if (bp->rx_cos_queue[i].id != 0xff) {
 731                         struct bnxt_vnic_info *vnic = &bp->vnic_info[j++];
 732
 733                         if (!vnic) {
 734                                 PMD_DRV_LOG(ERR,
 735                                             "Num pools more than FW profile\n");
 736                                 rc = -EINVAL;
 737                                 goto err_out;
 738                         }
 739                         vnic->cos_queue_id = bp->rx_cos_queue[i].id;
 740                         bp->rx_cosq_cnt++;
 741                 }
 742         }
 743
 744 skip_cosq_cfg:
 745         rc = bnxt_mq_rx_configure(bp);
 746         if (rc) {
 747                 PMD_DRV_LOG(ERR, "MQ mode configure failure rc: %x\n", rc);
 748                 goto err_out;
 749         }
 750
 751         /* default vnic 0 */
 752         rc = bnxt_setup_one_vnic(bp, 0);
 753         if (rc)
 754                 goto err_out;
 755         /* VNIC configuration */
 756         if (BNXT_RFS_NEEDS_VNIC(bp)) {
 757                 for (i = 1; i < bp->nr_vnics; i++) {
 758                         rc = bnxt_setup_one_vnic(bp, i);
 759                         if (rc)
 760                                 goto err_out;
 761                 }
 762         }
 763
 764         rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, &bp->vnic_info[0], 0, NULL);
 765         if (rc) {
 766                 PMD_DRV_LOG(ERR,
 767                         "HWRM cfa l2 rx mask failure rc: %x\n", rc);
 768                 goto err_out;
 769         }
 770
 771         /* check and configure queue intr-vector mapping */
 772         if ((rte_intr_cap_multiple(intr_handle) ||
 773              !RTE_ETH_DEV_SRIOV(bp->eth_dev).active) &&
 774             bp->eth_dev->data->dev_conf.intr_conf.rxq != 0) {
 775                 intr_vector = bp->eth_dev->data->nb_rx_queues;
 776                 PMD_DRV_LOG(DEBUG, "intr_vector = %d\n", intr_vector);
 777                 if (intr_vector > bp->rx_cp_nr_rings) {
 778                         PMD_DRV_LOG(ERR, "At most %d intr queues supported",
 779                                         bp->rx_cp_nr_rings);
 780                         return -ENOTSUP;
 781                 }
 782                 rc = rte_intr_efd_enable(intr_handle, intr_vector);
 783                 if (rc)
 784                         return rc;
 785         }
 786
 787         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
 788                 intr_handle->intr_vec =
 789                         rte_zmalloc("intr_vec",
 790                                     bp->eth_dev->data->nb_rx_queues *
 791                                     sizeof(int), 0);
 792                 if (intr_handle->intr_vec == NULL) {
 793                         PMD_DRV_LOG(ERR, "Failed to allocate %d rx_queues"
 794                                 " intr_vec", bp->eth_dev->data->nb_rx_queues);
 795                         rc = -ENOMEM;
 796                         goto err_disable;
 797                 }
 798                 PMD_DRV_LOG(DEBUG, "intr_handle->intr_vec = %p "
 799                         "intr_handle->nb_efd = %d intr_handle->max_intr = %d\n",
 800                          intr_handle->intr_vec, intr_handle->nb_efd,
 801                         intr_handle->max_intr);
 802                 for (queue_id = 0; queue_id < bp->eth_dev->data->nb_rx_queues;
 803                      queue_id++) {
 804                         intr_handle->intr_vec[queue_id] =
 805                                                         vec + BNXT_RX_VEC_START;
 806                         if (vec < base + intr_handle->nb_efd - 1)
 807                                 vec++;
 808                 }
 809         }
 810
 811         /* enable uio/vfio intr/eventfd mapping */
 812         rc = rte_intr_enable(intr_handle);
 813 #ifndef RTE_EXEC_ENV_FREEBSD
 814         /* In FreeBSD OS, nic_uio driver does not support interrupts */
 815         if (rc)
 816                 goto err_free;
 817 #endif
 818
 819         rc = bnxt_update_phy_setting(bp);
 820         if (rc)
 821                 goto err_free;
 822
 823         bp->mark_table = rte_zmalloc("bnxt_mark_table", BNXT_MARK_TABLE_SZ, 0);
 824         if (!bp->mark_table)
 825                 PMD_DRV_LOG(ERR, "Allocation of mark table failed\n");
 826
 827         return 0;
 828
 829 err_free:
 830         rte_free(intr_handle->intr_vec);
 831 err_disable:
 832         rte_intr_efd_disable(intr_handle);
 833 err_out:
 834         /* Some of the error status returned by FW may not be from errno.h */
 835         if (rc > 0)
 836                 rc = -EIO;
 837
 838         return rc;
 839 }
 840
 841 static int bnxt_shutdown_nic(struct bnxt *bp)
 842 {
 843         bnxt_free_all_hwrm_resources(bp);
 844         bnxt_free_all_filters(bp);
 845         bnxt_free_all_vnics(bp);
 846         return 0;
 847 }
 848
 849 /*
 850  * Device configuration and status function
 851  */
 852
 853 uint32_t bnxt_get_speed_capabilities(struct bnxt *bp)
 854 {
 855         uint32_t link_speed = bp->link_info->support_speeds;
 856         uint32_t speed_capa = 0;
 857
 858         /* If PAM4 is configured, use PAM4 supported speed */
 859         if (link_speed == 0 && bp->link_info->support_pam4_speeds > 0)
 860                 link_speed = bp->link_info->support_pam4_speeds;
 861
 862         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_100MB)
 863                 speed_capa |= ETH_LINK_SPEED_100M;
 864         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_100MBHD)
 865                 speed_capa |= ETH_LINK_SPEED_100M_HD;
 866         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_1GB)
 867                 speed_capa |= ETH_LINK_SPEED_1G;
 868         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_2_5GB)
 869                 speed_capa |= ETH_LINK_SPEED_2_5G;
 870         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_10GB)
 871                 speed_capa |= ETH_LINK_SPEED_10G;
 872         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_20GB)
 873                 speed_capa |= ETH_LINK_SPEED_20G;
 874         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_25GB)
 875                 speed_capa |= ETH_LINK_SPEED_25G;
 876         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_40GB)
 877                 speed_capa |= ETH_LINK_SPEED_40G;
 878         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_50GB)
 879                 speed_capa |= ETH_LINK_SPEED_50G;
 880         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_100GB)
 881                 speed_capa |= ETH_LINK_SPEED_100G;
 882         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_PAM4_SPEEDS_50G)
 883                 speed_capa |= ETH_LINK_SPEED_50G;
 884         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_PAM4_SPEEDS_100G)
 885                 speed_capa |= ETH_LINK_SPEED_100G;
 886         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_PAM4_SPEEDS_200G)
 887                 speed_capa |= ETH_LINK_SPEED_200G;
 888
 889         if (bp->link_info->auto_mode ==
 890             HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_MODE_NONE)
 891                 speed_capa |= ETH_LINK_SPEED_FIXED;
 892         else
 893                 speed_capa |= ETH_LINK_SPEED_AUTONEG;
 894
 895         return speed_capa;
 896 }
 897
 898 static int bnxt_dev_info_get_op(struct rte_eth_dev *eth_dev,
 899                                 struct rte_eth_dev_info *dev_info)
 900 {
 901         struct rte_pci_device *pdev = RTE_DEV_TO_PCI(eth_dev->device);
 902         struct bnxt *bp = eth_dev->data->dev_private;
 903         uint16_t max_vnics, i, j, vpool, vrxq;
 904         unsigned int max_rx_rings;
 905         int rc;
 906
 907         rc = is_bnxt_in_error(bp);
 908         if (rc)
 909                 return rc;
 910
 911         /* MAC Specifics */
 912         dev_info->max_mac_addrs = bp->max_l2_ctx;
 913         dev_info->max_hash_mac_addrs = 0;
 914
 915         /* PF/VF specifics */
 916         if (BNXT_PF(bp))
 917                 dev_info->max_vfs = pdev->max_vfs;
 918
 919         max_rx_rings = bnxt_max_rings(bp);
 920         /* For the sake of symmetry, max_rx_queues = max_tx_queues */
 921         dev_info->max_rx_queues = max_rx_rings;
 922         dev_info->max_tx_queues = max_rx_rings;
 923         dev_info->reta_size = bnxt_rss_hash_tbl_size(bp);
 924         dev_info->hash_key_size = 40;
 925         max_vnics = bp->max_vnics;
 926
 927         /* MTU specifics */
 928         dev_info->min_mtu = RTE_ETHER_MIN_MTU;
 929         dev_info->max_mtu = BNXT_MAX_MTU;
 930
 931         /* Fast path specifics */
 932         dev_info->min_rx_bufsize = 1;
 933         dev_info->max_rx_pktlen = BNXT_MAX_PKT_LEN;
 934
 935         dev_info->rx_offload_capa = BNXT_DEV_RX_OFFLOAD_SUPPORT;
 936         if (bp->flags & BNXT_FLAG_PTP_SUPPORTED)
 937                 dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_TIMESTAMP;
 938         dev_info->tx_queue_offload_capa = DEV_TX_OFFLOAD_MBUF_FAST_FREE;
 939         dev_info->tx_offload_capa = BNXT_DEV_TX_OFFLOAD_SUPPORT |
 940                                     dev_info->tx_queue_offload_capa;
 941         dev_info->flow_type_rss_offloads = BNXT_ETH_RSS_SUPPORT;
 942
 943         dev_info->speed_capa = bnxt_get_speed_capabilities(bp);
 944
 945         /* *INDENT-OFF* */
 946         dev_info->default_rxconf = (struct rte_eth_rxconf) {
 947                 .rx_thresh = {
 948                         .pthresh = 8,
 949                         .hthresh = 8,
 950                         .wthresh = 0,
 951                 },
 952                 .rx_free_thresh = 32,
 953                 .rx_drop_en = BNXT_DEFAULT_RX_DROP_EN,
 954         };
 955
 956         dev_info->default_txconf = (struct rte_eth_txconf) {
 957                 .tx_thresh = {
 958                         .pthresh = 32,
 959                         .hthresh = 0,
 960                         .wthresh = 0,
 961                 },
 962                 .tx_free_thresh = 32,
 963                 .tx_rs_thresh = 32,
 964         };
 965         eth_dev->data->dev_conf.intr_conf.lsc = 1;
 966
 967         eth_dev->data->dev_conf.intr_conf.rxq = 1;
 968         dev_info->rx_desc_lim.nb_min = BNXT_MIN_RING_DESC;
 969         dev_info->rx_desc_lim.nb_max = BNXT_MAX_RX_RING_DESC;
 970         dev_info->tx_desc_lim.nb_min = BNXT_MIN_RING_DESC;
 971         dev_info->tx_desc_lim.nb_max = BNXT_MAX_TX_RING_DESC;
 972
 973         if (BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp)) {
 974                 dev_info->switch_info.name = eth_dev->device->name;
 975                 dev_info->switch_info.domain_id = bp->switch_domain_id;
 976                 dev_info->switch_info.port_id =
 977                                 BNXT_PF(bp) ? BNXT_SWITCH_PORT_ID_PF :
 978                                     BNXT_SWITCH_PORT_ID_TRUSTED_VF;
 979         }
 980
 981         /* *INDENT-ON* */
 982
 983         /*
 984          * TODO: default_rxconf, default_txconf, rx_desc_lim, and tx_desc_lim
 985          *       need further investigation.
 986          */
 987
 988         /* VMDq resources */
 989         vpool = 64; /* ETH_64_POOLS */
 990         vrxq = 128; /* ETH_VMDQ_DCB_NUM_QUEUES */
 991         for (i = 0; i < 4; vpool >>= 1, i++) {
 992                 if (max_vnics > vpool) {
 993                         for (j = 0; j < 5; vrxq >>= 1, j++) {
 994                                 if (dev_info->max_rx_queues > vrxq) {
 995                                         if (vpool > vrxq)
 996                                                 vpool = vrxq;
 997                                         goto found;
 998                                 }
 999                         }
1000                         /* Not enough resources to support VMDq */
1001                         break;
1002                 }
1003         }
1004         /* Not enough resources to support VMDq */
1005         vpool = 0;
1006         vrxq = 0;
1007 found:
1008         dev_info->max_vmdq_pools = vpool;
1009         dev_info->vmdq_queue_num = vrxq;
1010
1011         dev_info->vmdq_pool_base = 0;
1012         dev_info->vmdq_queue_base = 0;
1013
1014         return 0;
1015 }
1016
1017 /* Configure the device based on the configuration provided */
1018 static int bnxt_dev_configure_op(struct rte_eth_dev *eth_dev)
1019 {
1020         struct bnxt *bp = eth_dev->data->dev_private;
1021         uint64_t rx_offloads = eth_dev->data->dev_conf.rxmode.offloads;
1022         int rc;
1023
1024         bp->rx_queues = (void *)eth_dev->data->rx_queues;
1025         bp->tx_queues = (void *)eth_dev->data->tx_queues;
1026         bp->tx_nr_rings = eth_dev->data->nb_tx_queues;
1027         bp->rx_nr_rings = eth_dev->data->nb_rx_queues;
1028
1029         rc = is_bnxt_in_error(bp);
1030         if (rc)
1031                 return rc;
1032
1033         if (BNXT_VF(bp) && (bp->flags & BNXT_FLAG_NEW_RM)) {
1034                 rc = bnxt_hwrm_check_vf_rings(bp);
1035                 if (rc) {
1036                         PMD_DRV_LOG(ERR, "HWRM insufficient resources\n");
1037                         return -ENOSPC;
1038                 }
1039
1040                 /* If a resource has already been allocated - in this case
1041                  * it is the async completion ring, free it. Reallocate it after
1042                  * resource reservation. This will ensure the resource counts
1043                  * are calculated correctly.
1044                  */
1045
1046                 pthread_mutex_lock(&bp->def_cp_lock);
1047
1048                 if (!BNXT_HAS_NQ(bp) && bp->async_cp_ring) {
1049                         bnxt_disable_int(bp);
1050                         bnxt_free_cp_ring(bp, bp->async_cp_ring);
1051                 }
1052
1053                 rc = bnxt_hwrm_func_reserve_vf_resc(bp, false);
1054                 if (rc) {
1055                         PMD_DRV_LOG(ERR, "HWRM resource alloc fail:%x\n", rc);
1056                         pthread_mutex_unlock(&bp->def_cp_lock);
1057                         return -ENOSPC;
1058                 }
1059
1060                 if (!BNXT_HAS_NQ(bp) && bp->async_cp_ring) {
1061                         rc = bnxt_alloc_async_cp_ring(bp);
1062                         if (rc) {
1063                                 pthread_mutex_unlock(&bp->def_cp_lock);
1064                                 return rc;
1065                         }
1066                         bnxt_enable_int(bp);
1067                 }
1068
1069                 pthread_mutex_unlock(&bp->def_cp_lock);
1070         }
1071
1072         /* Inherit new configurations */
1073         if (eth_dev->data->nb_rx_queues > bp->max_rx_rings ||
1074             eth_dev->data->nb_tx_queues > bp->max_tx_rings ||
1075             eth_dev->data->nb_rx_queues + eth_dev->data->nb_tx_queues
1076                 + BNXT_NUM_ASYNC_CPR(bp) > bp->max_cp_rings ||
1077             eth_dev->data->nb_rx_queues + eth_dev->data->nb_tx_queues >
1078             bp->max_stat_ctx)
1079                 goto resource_error;
1080
1081         if (BNXT_HAS_RING_GRPS(bp) &&
1082             (uint32_t)(eth_dev->data->nb_rx_queues) > bp->max_ring_grps)
1083                 goto resource_error;
1084
1085         if (!(eth_dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_RSS) &&
1086             bp->max_vnics < eth_dev->data->nb_rx_queues)
1087                 goto resource_error;
1088
1089         bp->rx_cp_nr_rings = bp->rx_nr_rings;
1090         bp->tx_cp_nr_rings = bp->tx_nr_rings;
1091
1092         if (eth_dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG)
1093                 rx_offloads |= DEV_RX_OFFLOAD_RSS_HASH;
1094         eth_dev->data->dev_conf.rxmode.offloads = rx_offloads;
1095
1096         if (rx_offloads & DEV_RX_OFFLOAD_JUMBO_FRAME) {
1097                 eth_dev->data->mtu =
1098                         eth_dev->data->dev_conf.rxmode.max_rx_pkt_len -
1099                         RTE_ETHER_HDR_LEN - RTE_ETHER_CRC_LEN - VLAN_TAG_SIZE *
1100                         BNXT_NUM_VLANS;
1101                 bnxt_mtu_set_op(eth_dev, eth_dev->data->mtu);
1102         }
1103         return 0;
1104
1105 resource_error:
1106         PMD_DRV_LOG(ERR,
1107                     "Insufficient resources to support requested config\n");
1108         PMD_DRV_LOG(ERR,
1109                     "Num Queues Requested: Tx %d, Rx %d\n",
1110                     eth_dev->data->nb_tx_queues,
1111                     eth_dev->data->nb_rx_queues);
1112         PMD_DRV_LOG(ERR,
1113                     "MAX: TxQ %d, RxQ %d, CQ %d Stat %d, Grp %d, Vnic %d\n",
1114                     bp->max_tx_rings, bp->max_rx_rings, bp->max_cp_rings,
1115                     bp->max_stat_ctx, bp->max_ring_grps, bp->max_vnics);
1116         return -ENOSPC;
1117 }
1118
1119 void bnxt_print_link_info(struct rte_eth_dev *eth_dev)
1120 {
1121         struct rte_eth_link *link = &eth_dev->data->dev_link;
1122
1123         if (link->link_status)
1124                 PMD_DRV_LOG(INFO, "Port %d Link Up - speed %u Mbps - %s\n",
1125                         eth_dev->data->port_id,
1126                         (uint32_t)link->link_speed,
1127                         (link->link_duplex == ETH_LINK_FULL_DUPLEX) ?
1128                         ("full-duplex") : ("half-duplex\n"));
1129         else
1130                 PMD_DRV_LOG(INFO, "Port %d Link Down\n",
1131                         eth_dev->data->port_id);
1132 }
1133
1134 /*
1135  * Determine whether the current configuration requires support for scattered
1136  * receive; return 1 if scattered receive is required and 0 if not.
1137  */
1138 static int bnxt_scattered_rx(struct rte_eth_dev *eth_dev)
1139 {
1140         uint16_t buf_size;
1141         int i;
1142
1143         if (eth_dev->data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_SCATTER)
1144                 return 1;
1145
1146         for (i = 0; i < eth_dev->data->nb_rx_queues; i++) {
1147                 struct bnxt_rx_queue *rxq = eth_dev->data->rx_queues[i];
1148
1149                 buf_size = (uint16_t)(rte_pktmbuf_data_room_size(rxq->mb_pool) -
1150                                       RTE_PKTMBUF_HEADROOM);
1151                 if (eth_dev->data->dev_conf.rxmode.max_rx_pkt_len > buf_size)
1152                         return 1;
1153         }
1154         return 0;
1155 }
1156
1157 static eth_rx_burst_t
1158 bnxt_receive_function(struct rte_eth_dev *eth_dev)
1159 {
1160         struct bnxt *bp = eth_dev->data->dev_private;
1161
1162         /* Disable vector mode RX for Stingray2 for now */
1163         if (BNXT_CHIP_SR2(bp)) {
1164                 bp->flags &= ~BNXT_FLAG_RX_VECTOR_PKT_MODE;
1165                 return bnxt_recv_pkts;
1166         }
1167
1168 #if defined(RTE_ARCH_X86) || defined(RTE_ARCH_ARM64)
1169 #ifndef RTE_LIBRTE_IEEE1588
1170         /*
1171          * Vector mode receive can be enabled only if scatter rx is not
1172          * in use and rx offloads are limited to VLAN stripping and
1173          * CRC stripping.
1174          */
1175         if (!eth_dev->data->scattered_rx &&
1176             !(eth_dev->data->dev_conf.rxmode.offloads &
1177               ~(DEV_RX_OFFLOAD_VLAN_STRIP |
1178                 DEV_RX_OFFLOAD_KEEP_CRC |
1179                 DEV_RX_OFFLOAD_JUMBO_FRAME |
1180                 DEV_RX_OFFLOAD_IPV4_CKSUM |
1181                 DEV_RX_OFFLOAD_UDP_CKSUM |
1182                 DEV_RX_OFFLOAD_TCP_CKSUM |
1183                 DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM |
1184                 DEV_RX_OFFLOAD_OUTER_UDP_CKSUM |
1185                 DEV_RX_OFFLOAD_RSS_HASH |
1186                 DEV_RX_OFFLOAD_VLAN_FILTER)) &&
1187             !BNXT_TRUFLOW_EN(bp) && BNXT_NUM_ASYNC_CPR(bp) &&
1188             rte_vect_get_max_simd_bitwidth() >= RTE_VECT_SIMD_128) {
1189                 PMD_DRV_LOG(INFO, "Using vector mode receive for port %d\n",
1190                             eth_dev->data->port_id);
1191                 bp->flags |= BNXT_FLAG_RX_VECTOR_PKT_MODE;
1192                 return bnxt_recv_pkts_vec;
1193         }
1194         PMD_DRV_LOG(INFO, "Vector mode receive disabled for port %d\n",
1195                     eth_dev->data->port_id);
1196         PMD_DRV_LOG(INFO,
1197                     "Port %d scatter: %d rx offload: %" PRIX64 "\n",
1198                     eth_dev->data->port_id,
1199                     eth_dev->data->scattered_rx,
1200                     eth_dev->data->dev_conf.rxmode.offloads);
1201 #endif
1202 #endif
1203         bp->flags &= ~BNXT_FLAG_RX_VECTOR_PKT_MODE;
1204         return bnxt_recv_pkts;
1205 }
1206
1207 static eth_tx_burst_t
1208 bnxt_transmit_function(struct rte_eth_dev *eth_dev)
1209 {
1210         struct bnxt *bp = eth_dev->data->dev_private;
1211
1212         /* Disable vector mode TX for Stingray2 for now */
1213         if (BNXT_CHIP_SR2(bp))
1214                 return bnxt_xmit_pkts;
1215
1216 #if defined(RTE_ARCH_X86) || defined(RTE_ARCH_ARM64)
1217 #ifndef RTE_LIBRTE_IEEE1588
1218         uint64_t offloads = eth_dev->data->dev_conf.txmode.offloads;
1219
1220         /*
1221          * Vector mode transmit can be enabled only if not using scatter rx
1222          * or tx offloads.
1223          */
1224         if (!eth_dev->data->scattered_rx &&
1225             !(offloads & ~DEV_TX_OFFLOAD_MBUF_FAST_FREE) &&
1226             !BNXT_TRUFLOW_EN(bp) &&
1227             rte_vect_get_max_simd_bitwidth() >= RTE_VECT_SIMD_128) {
1228                 PMD_DRV_LOG(INFO, "Using vector mode transmit for port %d\n",
1229                             eth_dev->data->port_id);
1230                 return bnxt_xmit_pkts_vec;
1231         }
1232         PMD_DRV_LOG(INFO, "Vector mode transmit disabled for port %d\n",
1233                     eth_dev->data->port_id);
1234         PMD_DRV_LOG(INFO,
1235                     "Port %d scatter: %d tx offload: %" PRIX64 "\n",
1236                     eth_dev->data->port_id,
1237                     eth_dev->data->scattered_rx,
1238                     offloads);
1239 #endif
1240 #endif
1241         return bnxt_xmit_pkts;
1242 }
1243
1244 static int bnxt_handle_if_change_status(struct bnxt *bp)
1245 {
1246         int rc;
1247
1248         /* Since fw has undergone a reset and lost all contexts,
1249          * set fatal flag to not issue hwrm during cleanup
1250          */
1251         bp->flags |= BNXT_FLAG_FATAL_ERROR;
1252         bnxt_uninit_resources(bp, true);
1253
1254         /* clear fatal flag so that re-init happens */
1255         bp->flags &= ~BNXT_FLAG_FATAL_ERROR;
1256         rc = bnxt_init_resources(bp, true);
1257
1258         bp->flags &= ~BNXT_FLAG_IF_CHANGE_HOT_FW_RESET_DONE;
1259
1260         return rc;
1261 }
1262
1263 static int bnxt_dev_set_link_up_op(struct rte_eth_dev *eth_dev)
1264 {
1265         struct bnxt *bp = eth_dev->data->dev_private;
1266         int rc = 0;
1267
1268         if (!bp->link_info->link_up)
1269                 rc = bnxt_set_hwrm_link_config(bp, true);
1270         if (!rc)
1271                 eth_dev->data->dev_link.link_status = 1;
1272
1273         bnxt_print_link_info(eth_dev);
1274         return rc;
1275 }
1276
1277 static int bnxt_dev_set_link_down_op(struct rte_eth_dev *eth_dev)
1278 {
1279         struct bnxt *bp = eth_dev->data->dev_private;
1280
1281         eth_dev->data->dev_link.link_status = 0;
1282         bnxt_set_hwrm_link_config(bp, false);
1283         bp->link_info->link_up = 0;
1284
1285         return 0;
1286 }
1287
1288 static void bnxt_free_switch_domain(struct bnxt *bp)
1289 {
1290         int rc = 0;
1291
1292         if (bp->switch_domain_id) {
1293                 rc = rte_eth_switch_domain_free(bp->switch_domain_id);
1294                 if (rc)
1295                         PMD_DRV_LOG(ERR, "free switch domain:%d fail: %d\n",
1296                                     bp->switch_domain_id, rc);
1297         }
1298 }
1299
1300 static int bnxt_dev_stop(struct rte_eth_dev *eth_dev)
1301 {
1302         struct bnxt *bp = eth_dev->data->dev_private;
1303         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1304         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1305         struct rte_eth_link link;
1306         int ret;
1307
1308         eth_dev->data->dev_started = 0;
1309         eth_dev->data->scattered_rx = 0;
1310
1311         /* Prevent crashes when queues are still in use */
1312         eth_dev->rx_pkt_burst = &bnxt_dummy_recv_pkts;
1313         eth_dev->tx_pkt_burst = &bnxt_dummy_xmit_pkts;
1314
1315         bnxt_disable_int(bp);
1316
1317         /* disable uio/vfio intr/eventfd mapping */
1318         rte_intr_disable(intr_handle);
1319
1320         /* Stop the child representors for this device */
1321         ret = bnxt_rep_stop_all(bp);
1322         if (ret != 0)
1323                 return ret;
1324
1325         /* delete the bnxt ULP port details */
1326         bnxt_ulp_port_deinit(bp);
1327
1328         bnxt_cancel_fw_health_check(bp);
1329
1330         /* Do not bring link down during reset recovery */
1331         if (!is_bnxt_in_error(bp)) {
1332                 bnxt_dev_set_link_down_op(eth_dev);
1333                 /* Wait for link to be reset */
1334                 if (BNXT_SINGLE_PF(bp))
1335                         rte_delay_ms(500);
1336                 /* clear the recorded link status */
1337                 memset(&link, 0, sizeof(link));
1338                 rte_eth_linkstatus_set(eth_dev, &link);
1339         }
1340
1341         /* Clean queue intr-vector mapping */
1342         rte_intr_efd_disable(intr_handle);
1343         if (intr_handle->intr_vec != NULL) {
1344                 rte_free(intr_handle->intr_vec);
1345                 intr_handle->intr_vec = NULL;
1346         }
1347
1348         bnxt_hwrm_port_clr_stats(bp);
1349         bnxt_free_tx_mbufs(bp);
1350         bnxt_free_rx_mbufs(bp);
1351         /* Process any remaining notifications in default completion queue */
1352         bnxt_int_handler(eth_dev);
1353         bnxt_shutdown_nic(bp);
1354         bnxt_hwrm_if_change(bp, false);
1355
1356         rte_free(bp->mark_table);
1357         bp->mark_table = NULL;
1358
1359         bp->flags &= ~BNXT_FLAG_RX_VECTOR_PKT_MODE;
1360         bp->rx_cosq_cnt = 0;
1361         /* All filters are deleted on a port stop. */
1362         if (BNXT_FLOW_XSTATS_EN(bp))
1363                 bp->flow_stat->flow_count = 0;
1364
1365         return 0;
1366 }
1367
1368 /* Unload the driver, release resources */
1369 static int bnxt_dev_stop_op(struct rte_eth_dev *eth_dev)
1370 {
1371         struct bnxt *bp = eth_dev->data->dev_private;
1372
1373         pthread_mutex_lock(&bp->err_recovery_lock);
1374         if (bp->flags & BNXT_FLAG_FW_RESET) {
1375                 PMD_DRV_LOG(ERR,
1376                             "Adapter recovering from error..Please retry\n");
1377                 return -EAGAIN;
1378         }
1379         pthread_mutex_unlock(&bp->err_recovery_lock);
1380
1381         return bnxt_dev_stop(eth_dev);
1382 }
1383
1384 static int bnxt_dev_start_op(struct rte_eth_dev *eth_dev)
1385 {
1386         struct bnxt *bp = eth_dev->data->dev_private;
1387         uint64_t rx_offloads = eth_dev->data->dev_conf.rxmode.offloads;
1388         int vlan_mask = 0;
1389         int rc, retry_cnt = BNXT_IF_CHANGE_RETRY_COUNT;
1390
1391         if (!eth_dev->data->nb_tx_queues || !eth_dev->data->nb_rx_queues) {
1392                 PMD_DRV_LOG(ERR, "Queues are not configured yet!\n");
1393                 return -EINVAL;
1394         }
1395
1396         if (bp->rx_cp_nr_rings > RTE_ETHDEV_QUEUE_STAT_CNTRS)
1397                 PMD_DRV_LOG(ERR,
1398                             "RxQ cnt %d > RTE_ETHDEV_QUEUE_STAT_CNTRS %d\n",
1399                             bp->rx_cp_nr_rings, RTE_ETHDEV_QUEUE_STAT_CNTRS);
1400
1401         do {
1402                 rc = bnxt_hwrm_if_change(bp, true);
1403                 if (rc == 0 || rc != -EAGAIN)
1404                         break;
1405
1406                 rte_delay_ms(BNXT_IF_CHANGE_RETRY_INTERVAL);
1407         } while (retry_cnt--);
1408
1409         if (rc)
1410                 return rc;
1411
1412         if (bp->flags & BNXT_FLAG_IF_CHANGE_HOT_FW_RESET_DONE) {
1413                 rc = bnxt_handle_if_change_status(bp);
1414                 if (rc)
1415                         return rc;
1416         }
1417
1418         bnxt_enable_int(bp);
1419
1420         rc = bnxt_start_nic(bp);
1421         if (rc)
1422                 goto error;
1423
1424         eth_dev->data->scattered_rx = bnxt_scattered_rx(eth_dev);
1425         eth_dev->data->dev_started = 1;
1426
1427         bnxt_link_update_op(eth_dev, 1);
1428
1429         if (rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER)
1430                 vlan_mask |= ETH_VLAN_FILTER_MASK;
1431         if (rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
1432                 vlan_mask |= ETH_VLAN_STRIP_MASK;
1433         rc = bnxt_vlan_offload_set_op(eth_dev, vlan_mask);
1434         if (rc)
1435                 goto error;
1436
1437         /* Initialize bnxt ULP port details */
1438         rc = bnxt_ulp_port_init(bp);
1439         if (rc)
1440                 goto error;
1441
1442         eth_dev->rx_pkt_burst = bnxt_receive_function(eth_dev);
1443         eth_dev->tx_pkt_burst = bnxt_transmit_function(eth_dev);
1444
1445         bnxt_schedule_fw_health_check(bp);
1446
1447         return 0;
1448
1449 error:
1450         bnxt_dev_stop(eth_dev);
1451         return rc;
1452 }
1453
1454 static void
1455 bnxt_uninit_locks(struct bnxt *bp)
1456 {
1457         pthread_mutex_destroy(&bp->flow_lock);
1458         pthread_mutex_destroy(&bp->def_cp_lock);
1459         pthread_mutex_destroy(&bp->health_check_lock);
1460         pthread_mutex_destroy(&bp->err_recovery_lock);
1461         if (bp->rep_info) {
1462                 pthread_mutex_destroy(&bp->rep_info->vfr_lock);
1463                 pthread_mutex_destroy(&bp->rep_info->vfr_start_lock);
1464         }
1465 }
1466
1467 static void bnxt_drv_uninit(struct bnxt *bp)
1468 {
1469         bnxt_free_switch_domain(bp);
1470         bnxt_free_leds_info(bp);
1471         bnxt_free_cos_queues(bp);
1472         bnxt_free_link_info(bp);
1473         bnxt_free_pf_info(bp);
1474         bnxt_free_parent_info(bp);
1475         bnxt_uninit_locks(bp);
1476
1477         rte_memzone_free((const struct rte_memzone *)bp->tx_mem_zone);
1478         bp->tx_mem_zone = NULL;
1479         rte_memzone_free((const struct rte_memzone *)bp->rx_mem_zone);
1480         bp->rx_mem_zone = NULL;
1481
1482         bnxt_hwrm_free_vf_info(bp);
1483
1484         rte_free(bp->grp_info);
1485         bp->grp_info = NULL;
1486 }
1487
1488 static int bnxt_dev_close_op(struct rte_eth_dev *eth_dev)
1489 {
1490         struct bnxt *bp = eth_dev->data->dev_private;
1491         int ret = 0;
1492
1493         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1494                 return 0;
1495
1496         pthread_mutex_lock(&bp->err_recovery_lock);
1497         if (bp->flags & BNXT_FLAG_FW_RESET) {
1498                 PMD_DRV_LOG(ERR,
1499                             "Adapter recovering from error...Please retry\n");
1500                 return -EAGAIN;
1501         }
1502         pthread_mutex_unlock(&bp->err_recovery_lock);
1503
1504         /* cancel the recovery handler before remove dev */
1505         rte_eal_alarm_cancel(bnxt_dev_reset_and_resume, (void *)bp);
1506         rte_eal_alarm_cancel(bnxt_dev_recover, (void *)bp);
1507         bnxt_cancel_fc_thread(bp);
1508
1509         if (eth_dev->data->dev_started)
1510                 ret = bnxt_dev_stop(eth_dev);
1511
1512         bnxt_uninit_resources(bp, false);
1513
1514         bnxt_drv_uninit(bp);
1515
1516         return ret;
1517 }
1518
1519 static void bnxt_mac_addr_remove_op(struct rte_eth_dev *eth_dev,
1520                                     uint32_t index)
1521 {
1522         struct bnxt *bp = eth_dev->data->dev_private;
1523         uint64_t pool_mask = eth_dev->data->mac_pool_sel[index];
1524         struct bnxt_vnic_info *vnic;
1525         struct bnxt_filter_info *filter, *temp_filter;
1526         uint32_t i;
1527
1528         if (is_bnxt_in_error(bp))
1529                 return;
1530
1531         /*
1532          * Loop through all VNICs from the specified filter flow pools to
1533          * remove the corresponding MAC addr filter
1534          */
1535         for (i = 0; i < bp->nr_vnics; i++) {
1536                 if (!(pool_mask & (1ULL << i)))
1537                         continue;
1538
1539                 vnic = &bp->vnic_info[i];
1540                 filter = STAILQ_FIRST(&vnic->filter);
1541                 while (filter) {
1542                         temp_filter = STAILQ_NEXT(filter, next);
1543                         if (filter->mac_index == index) {
1544                                 STAILQ_REMOVE(&vnic->filter, filter,
1545                                                 bnxt_filter_info, next);
1546                                 bnxt_hwrm_clear_l2_filter(bp, filter);
1547                                 bnxt_free_filter(bp, filter);
1548                         }
1549                         filter = temp_filter;
1550                 }
1551         }
1552 }
1553
1554 static int bnxt_add_mac_filter(struct bnxt *bp, struct bnxt_vnic_info *vnic,
1555                                struct rte_ether_addr *mac_addr, uint32_t index,
1556                                uint32_t pool)
1557 {
1558         struct bnxt_filter_info *filter;
1559         int rc = 0;
1560
1561         /* Attach requested MAC address to the new l2_filter */
1562         STAILQ_FOREACH(filter, &vnic->filter, next) {
1563                 if (filter->mac_index == index) {
1564                         PMD_DRV_LOG(DEBUG,
1565                                     "MAC addr already existed for pool %d\n",
1566                                     pool);
1567                         return 0;
1568                 }
1569         }
1570
1571         filter = bnxt_alloc_filter(bp);
1572         if (!filter) {
1573                 PMD_DRV_LOG(ERR, "L2 filter alloc failed\n");
1574                 return -ENODEV;
1575         }
1576
1577         /* bnxt_alloc_filter copies default MAC to filter->l2_addr. So,
1578          * if the MAC that's been programmed now is a different one, then,
1579          * copy that addr to filter->l2_addr
1580          */
1581         if (mac_addr)
1582                 memcpy(filter->l2_addr, mac_addr, RTE_ETHER_ADDR_LEN);
1583         filter->flags |= HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_OUTERMOST;
1584
1585         rc = bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id, filter);
1586         if (!rc) {
1587                 filter->mac_index = index;
1588                 if (filter->mac_index == 0)
1589                         STAILQ_INSERT_HEAD(&vnic->filter, filter, next);
1590                 else
1591                         STAILQ_INSERT_TAIL(&vnic->filter, filter, next);
1592         } else {
1593                 bnxt_free_filter(bp, filter);
1594         }
1595
1596         return rc;
1597 }
1598
1599 static int bnxt_mac_addr_add_op(struct rte_eth_dev *eth_dev,
1600                                 struct rte_ether_addr *mac_addr,
1601                                 uint32_t index, uint32_t pool)
1602 {
1603         struct bnxt *bp = eth_dev->data->dev_private;
1604         struct bnxt_vnic_info *vnic = &bp->vnic_info[pool];
1605         int rc = 0;
1606
1607         rc = is_bnxt_in_error(bp);
1608         if (rc)
1609                 return rc;
1610
1611         if (BNXT_VF(bp) && !BNXT_VF_IS_TRUSTED(bp)) {
1612                 PMD_DRV_LOG(ERR, "Cannot add MAC address to a VF interface\n");
1613                 return -ENOTSUP;
1614         }
1615
1616         if (!vnic) {
1617                 PMD_DRV_LOG(ERR, "VNIC not found for pool %d!\n", pool);
1618                 return -EINVAL;
1619         }
1620
1621         /* Filter settings will get applied when port is started */
1622         if (!eth_dev->data->dev_started)
1623                 return 0;
1624
1625         rc = bnxt_add_mac_filter(bp, vnic, mac_addr, index, pool);
1626
1627         return rc;
1628 }
1629
1630 int bnxt_link_update_op(struct rte_eth_dev *eth_dev, int wait_to_complete)
1631 {
1632         int rc = 0;
1633         struct bnxt *bp = eth_dev->data->dev_private;
1634         struct rte_eth_link new;
1635         int cnt = wait_to_complete ? BNXT_MAX_LINK_WAIT_CNT :
1636                         BNXT_MIN_LINK_WAIT_CNT;
1637
1638         rc = is_bnxt_in_error(bp);
1639         if (rc)
1640                 return rc;
1641
1642         memset(&new, 0, sizeof(new));
1643         do {
1644                 /* Retrieve link info from hardware */
1645                 rc = bnxt_get_hwrm_link_config(bp, &new);
1646                 if (rc) {
1647                         new.link_speed = ETH_LINK_SPEED_100M;
1648                         new.link_duplex = ETH_LINK_FULL_DUPLEX;
1649                         PMD_DRV_LOG(ERR,
1650                                 "Failed to retrieve link rc = 0x%x!\n", rc);
1651                         goto out;
1652                 }
1653
1654                 if (!wait_to_complete || new.link_status)
1655                         break;
1656
1657                 rte_delay_ms(BNXT_LINK_WAIT_INTERVAL);
1658         } while (cnt--);
1659
1660         /* Only single function PF can bring phy down.
1661          * When port is stopped, report link down for VF/MH/NPAR functions.
1662          */
1663         if (!BNXT_SINGLE_PF(bp) && !eth_dev->data->dev_started)
1664                 memset(&new, 0, sizeof(new));
1665
1666 out:
1667         /* Timed out or success */
1668         if (new.link_status != eth_dev->data->dev_link.link_status ||
1669             new.link_speed != eth_dev->data->dev_link.link_speed) {
1670                 rte_eth_linkstatus_set(eth_dev, &new);
1671
1672                 rte_eth_dev_callback_process(eth_dev,
1673                                              RTE_ETH_EVENT_INTR_LSC,
1674                                              NULL);
1675
1676                 bnxt_print_link_info(eth_dev);
1677         }
1678
1679         return rc;
1680 }
1681
1682 static int bnxt_promiscuous_enable_op(struct rte_eth_dev *eth_dev)
1683 {
1684         struct bnxt *bp = eth_dev->data->dev_private;
1685         struct bnxt_vnic_info *vnic;
1686         uint32_t old_flags;
1687         int rc;
1688
1689         rc = is_bnxt_in_error(bp);
1690         if (rc)
1691                 return rc;
1692
1693         /* Filter settings will get applied when port is started */
1694         if (!eth_dev->data->dev_started)
1695                 return 0;
1696
1697         if (bp->vnic_info == NULL)
1698                 return 0;
1699
1700         vnic = BNXT_GET_DEFAULT_VNIC(bp);
1701
1702         old_flags = vnic->flags;
1703         vnic->flags |= BNXT_VNIC_INFO_PROMISC;
1704         rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1705         if (rc != 0)
1706                 vnic->flags = old_flags;
1707
1708         return rc;
1709 }
1710
1711 static int bnxt_promiscuous_disable_op(struct rte_eth_dev *eth_dev)
1712 {
1713         struct bnxt *bp = eth_dev->data->dev_private;
1714         struct bnxt_vnic_info *vnic;
1715         uint32_t old_flags;
1716         int rc;
1717
1718         rc = is_bnxt_in_error(bp);
1719         if (rc)
1720                 return rc;
1721
1722         /* Filter settings will get applied when port is started */
1723         if (!eth_dev->data->dev_started)
1724                 return 0;
1725
1726         if (bp->vnic_info == NULL)
1727                 return 0;
1728
1729         vnic = BNXT_GET_DEFAULT_VNIC(bp);
1730
1731         old_flags = vnic->flags;
1732         vnic->flags &= ~BNXT_VNIC_INFO_PROMISC;
1733         rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1734         if (rc != 0)
1735                 vnic->flags = old_flags;
1736
1737         return rc;
1738 }
1739
1740 static int bnxt_allmulticast_enable_op(struct rte_eth_dev *eth_dev)
1741 {
1742         struct bnxt *bp = eth_dev->data->dev_private;
1743         struct bnxt_vnic_info *vnic;
1744         uint32_t old_flags;
1745         int rc;
1746
1747         rc = is_bnxt_in_error(bp);
1748         if (rc)
1749                 return rc;
1750
1751         /* Filter settings will get applied when port is started */
1752         if (!eth_dev->data->dev_started)
1753                 return 0;
1754
1755         if (bp->vnic_info == NULL)
1756                 return 0;
1757
1758         vnic = BNXT_GET_DEFAULT_VNIC(bp);
1759
1760         old_flags = vnic->flags;
1761         vnic->flags |= BNXT_VNIC_INFO_ALLMULTI;
1762         rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1763         if (rc != 0)
1764                 vnic->flags = old_flags;
1765
1766         return rc;
1767 }
1768
1769 static int bnxt_allmulticast_disable_op(struct rte_eth_dev *eth_dev)
1770 {
1771         struct bnxt *bp = eth_dev->data->dev_private;
1772         struct bnxt_vnic_info *vnic;
1773         uint32_t old_flags;
1774         int rc;
1775
1776         rc = is_bnxt_in_error(bp);
1777         if (rc)
1778                 return rc;
1779
1780         /* Filter settings will get applied when port is started */
1781         if (!eth_dev->data->dev_started)
1782                 return 0;
1783
1784         if (bp->vnic_info == NULL)
1785                 return 0;
1786
1787         vnic = BNXT_GET_DEFAULT_VNIC(bp);
1788
1789         old_flags = vnic->flags;
1790         vnic->flags &= ~BNXT_VNIC_INFO_ALLMULTI;
1791         rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1792         if (rc != 0)
1793                 vnic->flags = old_flags;
1794
1795         return rc;
1796 }
1797
1798 /* Return bnxt_rx_queue pointer corresponding to a given rxq. */
1799 static struct bnxt_rx_queue *bnxt_qid_to_rxq(struct bnxt *bp, uint16_t qid)
1800 {
1801         if (qid >= bp->rx_nr_rings)
1802                 return NULL;
1803
1804         return bp->eth_dev->data->rx_queues[qid];
1805 }
1806
1807 /* Return rxq corresponding to a given rss table ring/group ID. */
1808 static uint16_t bnxt_rss_to_qid(struct bnxt *bp, uint16_t fwr)
1809 {
1810         struct bnxt_rx_queue *rxq;
1811         unsigned int i;
1812
1813         if (!BNXT_HAS_RING_GRPS(bp)) {
1814                 for (i = 0; i < bp->rx_nr_rings; i++) {
1815                         rxq = bp->eth_dev->data->rx_queues[i];
1816                         if (rxq->rx_ring->rx_ring_struct->fw_ring_id == fwr)
1817                                 return rxq->index;
1818                 }
1819         } else {
1820                 for (i = 0; i < bp->rx_nr_rings; i++) {
1821                         if (bp->grp_info[i].fw_grp_id == fwr)
1822                                 return i;
1823                 }
1824         }
1825
1826         return INVALID_HW_RING_ID;
1827 }
1828
1829 static int bnxt_reta_update_op(struct rte_eth_dev *eth_dev,
1830                             struct rte_eth_rss_reta_entry64 *reta_conf,
1831                             uint16_t reta_size)
1832 {
1833         struct bnxt *bp = eth_dev->data->dev_private;
1834         struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
1835         struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp);
1836         uint16_t tbl_size = bnxt_rss_hash_tbl_size(bp);
1837         uint16_t idx, sft;
1838         int i, rc;
1839
1840         rc = is_bnxt_in_error(bp);
1841         if (rc)
1842                 return rc;
1843
1844         if (!vnic->rss_table)
1845                 return -EINVAL;
1846
1847         if (!(dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG))
1848                 return -EINVAL;
1849
1850         if (reta_size != tbl_size) {
1851                 PMD_DRV_LOG(ERR, "The configured hash table lookup size "
1852                         "(%d) must equal the size supported by the hardware "
1853                         "(%d)\n", reta_size, tbl_size);
1854                 return -EINVAL;
1855         }
1856
1857         for (i = 0; i < reta_size; i++) {
1858                 struct bnxt_rx_queue *rxq;
1859
1860                 idx = i / RTE_RETA_GROUP_SIZE;
1861                 sft = i % RTE_RETA_GROUP_SIZE;
1862
1863                 if (!(reta_conf[idx].mask & (1ULL << sft)))
1864                         continue;
1865
1866                 rxq = bnxt_qid_to_rxq(bp, reta_conf[idx].reta[sft]);
1867                 if (!rxq) {
1868                         PMD_DRV_LOG(ERR, "Invalid ring in reta_conf.\n");
1869                         return -EINVAL;
1870                 }
1871
1872                 if (BNXT_CHIP_P5(bp)) {
1873                         vnic->rss_table[i * 2] =
1874                                 rxq->rx_ring->rx_ring_struct->fw_ring_id;
1875                         vnic->rss_table[i * 2 + 1] =
1876                                 rxq->cp_ring->cp_ring_struct->fw_ring_id;
1877                 } else {
1878                         vnic->rss_table[i] =
1879                             vnic->fw_grp_ids[reta_conf[idx].reta[sft]];
1880                 }
1881         }
1882
1883         rc = bnxt_hwrm_vnic_rss_cfg(bp, vnic);
1884         return rc;
1885 }
1886
1887 static int bnxt_reta_query_op(struct rte_eth_dev *eth_dev,
1888                               struct rte_eth_rss_reta_entry64 *reta_conf,
1889                               uint16_t reta_size)
1890 {
1891         struct bnxt *bp = eth_dev->data->dev_private;
1892         struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp);
1893         uint16_t tbl_size = bnxt_rss_hash_tbl_size(bp);
1894         uint16_t idx, sft, i;
1895         int rc;
1896
1897         rc = is_bnxt_in_error(bp);
1898         if (rc)
1899                 return rc;
1900
1901         /* Retrieve from the default VNIC */
1902         if (!vnic)
1903                 return -EINVAL;
1904         if (!vnic->rss_table)
1905                 return -EINVAL;
1906
1907         if (reta_size != tbl_size) {
1908                 PMD_DRV_LOG(ERR, "The configured hash table lookup size "
1909                         "(%d) must equal the size supported by the hardware "
1910                         "(%d)\n", reta_size, tbl_size);
1911                 return -EINVAL;
1912         }
1913
1914         for (idx = 0, i = 0; i < reta_size; i++) {
1915                 idx = i / RTE_RETA_GROUP_SIZE;
1916                 sft = i % RTE_RETA_GROUP_SIZE;
1917
1918                 if (reta_conf[idx].mask & (1ULL << sft)) {
1919                         uint16_t qid;
1920
1921                         if (BNXT_CHIP_P5(bp))
1922                                 qid = bnxt_rss_to_qid(bp,
1923                                                       vnic->rss_table[i * 2]);
1924                         else
1925                                 qid = bnxt_rss_to_qid(bp, vnic->rss_table[i]);
1926
1927                         if (qid == INVALID_HW_RING_ID) {
1928                                 PMD_DRV_LOG(ERR, "Inv. entry in rss table.\n");
1929                                 return -EINVAL;
1930                         }
1931                         reta_conf[idx].reta[sft] = qid;
1932                 }
1933         }
1934
1935         return 0;
1936 }
1937
1938 static int bnxt_rss_hash_update_op(struct rte_eth_dev *eth_dev,
1939                                    struct rte_eth_rss_conf *rss_conf)
1940 {
1941         struct bnxt *bp = eth_dev->data->dev_private;
1942         struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
1943         struct bnxt_vnic_info *vnic;
1944         int rc;
1945
1946         rc = is_bnxt_in_error(bp);
1947         if (rc)
1948                 return rc;
1949
1950         /*
1951          * If RSS enablement were different than dev_configure,
1952          * then return -EINVAL
1953          */
1954         if (dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG) {
1955                 if (!rss_conf->rss_hf)
1956                         PMD_DRV_LOG(ERR, "Hash type NONE\n");
1957         } else {
1958                 if (rss_conf->rss_hf & BNXT_ETH_RSS_SUPPORT)
1959                         return -EINVAL;
1960         }
1961
1962         bp->flags |= BNXT_FLAG_UPDATE_HASH;
1963         memcpy(&eth_dev->data->dev_conf.rx_adv_conf.rss_conf,
1964                rss_conf,
1965                sizeof(*rss_conf));
1966
1967         /* Update the default RSS VNIC(s) */
1968         vnic = BNXT_GET_DEFAULT_VNIC(bp);
1969         vnic->hash_type = bnxt_rte_to_hwrm_hash_types(rss_conf->rss_hf);
1970         vnic->hash_mode =
1971                 bnxt_rte_to_hwrm_hash_level(bp, rss_conf->rss_hf,
1972                                             ETH_RSS_LEVEL(rss_conf->rss_hf));
1973
1974         /*
1975          * If hashkey is not specified, use the previously configured
1976          * hashkey
1977          */
1978         if (!rss_conf->rss_key)
1979                 goto rss_config;
1980
1981         if (rss_conf->rss_key_len != HW_HASH_KEY_SIZE) {
1982                 PMD_DRV_LOG(ERR,
1983                             "Invalid hashkey length, should be 16 bytes\n");
1984                 return -EINVAL;
1985         }
1986         memcpy(vnic->rss_hash_key, rss_conf->rss_key, rss_conf->rss_key_len);
1987
1988 rss_config:
1989         rc = bnxt_hwrm_vnic_rss_cfg(bp, vnic);
1990         return rc;
1991 }
1992
1993 static int bnxt_rss_hash_conf_get_op(struct rte_eth_dev *eth_dev,
1994                                      struct rte_eth_rss_conf *rss_conf)
1995 {
1996         struct bnxt *bp = eth_dev->data->dev_private;
1997         struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp);
1998         int len, rc;
1999         uint32_t hash_types;
2000
2001         rc = is_bnxt_in_error(bp);
2002         if (rc)
2003                 return rc;
2004
2005         /* RSS configuration is the same for all VNICs */
2006         if (vnic && vnic->rss_hash_key) {
2007                 if (rss_conf->rss_key) {
2008                         len = rss_conf->rss_key_len <= HW_HASH_KEY_SIZE ?
2009                               rss_conf->rss_key_len : HW_HASH_KEY_SIZE;
2010                         memcpy(rss_conf->rss_key, vnic->rss_hash_key, len);
2011                 }
2012
2013                 hash_types = vnic->hash_type;
2014                 rss_conf->rss_hf = 0;
2015                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV4) {
2016                         rss_conf->rss_hf |= ETH_RSS_IPV4;
2017                         hash_types &= ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV4;
2018                 }
2019                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV4) {
2020                         rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP;
2021                         hash_types &=
2022                                 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV4;
2023                 }
2024                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV4) {
2025                         rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
2026                         hash_types &=
2027                                 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV4;
2028                 }
2029                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6) {
2030                         rss_conf->rss_hf |= ETH_RSS_IPV6;
2031                         hash_types &= ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6;
2032                 }
2033                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV6) {
2034                         rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV6_TCP;
2035                         hash_types &=
2036                                 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV6;
2037                 }
2038                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV6) {
2039                         rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;
2040                         hash_types &=
2041                                 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV6;
2042                 }
2043
2044                 rss_conf->rss_hf |=
2045                         bnxt_hwrm_to_rte_rss_level(bp, vnic->hash_mode);
2046
2047                 if (hash_types) {
2048                         PMD_DRV_LOG(ERR,
2049                                 "Unknown RSS config from firmware (%08x), RSS disabled",
2050                                 vnic->hash_type);
2051                         return -ENOTSUP;
2052                 }
2053         } else {
2054                 rss_conf->rss_hf = 0;
2055         }
2056         return 0;
2057 }
2058
2059 static int bnxt_flow_ctrl_get_op(struct rte_eth_dev *dev,
2060                                struct rte_eth_fc_conf *fc_conf)
2061 {
2062         struct bnxt *bp = dev->data->dev_private;
2063         struct rte_eth_link link_info;
2064         int rc;
2065
2066         rc = is_bnxt_in_error(bp);
2067         if (rc)
2068                 return rc;
2069
2070         rc = bnxt_get_hwrm_link_config(bp, &link_info);
2071         if (rc)
2072                 return rc;
2073
2074         memset(fc_conf, 0, sizeof(*fc_conf));
2075         if (bp->link_info->auto_pause)
2076                 fc_conf->autoneg = 1;
2077         switch (bp->link_info->pause) {
2078         case 0:
2079                 fc_conf->mode = RTE_FC_NONE;
2080                 break;
2081         case HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_TX:
2082                 fc_conf->mode = RTE_FC_TX_PAUSE;
2083                 break;
2084         case HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_RX:
2085                 fc_conf->mode = RTE_FC_RX_PAUSE;
2086                 break;
2087         case (HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_TX |
2088                         HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_RX):
2089                 fc_conf->mode = RTE_FC_FULL;
2090                 break;
2091         }
2092         return 0;
2093 }
2094
2095 static int bnxt_flow_ctrl_set_op(struct rte_eth_dev *dev,
2096                                struct rte_eth_fc_conf *fc_conf)
2097 {
2098         struct bnxt *bp = dev->data->dev_private;
2099         int rc;
2100
2101         rc = is_bnxt_in_error(bp);
2102         if (rc)
2103                 return rc;
2104
2105         if (!BNXT_SINGLE_PF(bp) || BNXT_VF(bp)) {
2106                 PMD_DRV_LOG(ERR, "Flow Control Settings cannot be modified\n");
2107                 return -ENOTSUP;
2108         }
2109
2110         switch (fc_conf->mode) {
2111         case RTE_FC_NONE:
2112                 bp->link_info->auto_pause = 0;
2113                 bp->link_info->force_pause = 0;
2114                 break;
2115         case RTE_FC_RX_PAUSE:
2116                 if (fc_conf->autoneg) {
2117                         bp->link_info->auto_pause =
2118                                         HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_RX;
2119                         bp->link_info->force_pause = 0;
2120                 } else {
2121                         bp->link_info->auto_pause = 0;
2122                         bp->link_info->force_pause =
2123                                         HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_RX;
2124                 }
2125                 break;
2126         case RTE_FC_TX_PAUSE:
2127                 if (fc_conf->autoneg) {
2128                         bp->link_info->auto_pause =
2129                                         HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_TX;
2130                         bp->link_info->force_pause = 0;
2131                 } else {
2132                         bp->link_info->auto_pause = 0;
2133                         bp->link_info->force_pause =
2134                                         HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_TX;
2135                 }
2136                 break;
2137         case RTE_FC_FULL:
2138                 if (fc_conf->autoneg) {
2139                         bp->link_info->auto_pause =
2140                                         HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_TX |
2141                                         HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_RX;
2142                         bp->link_info->force_pause = 0;
2143                 } else {
2144                         bp->link_info->auto_pause = 0;
2145                         bp->link_info->force_pause =
2146                                         HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_TX |
2147                                         HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_RX;
2148                 }
2149                 break;
2150         }
2151         return bnxt_set_hwrm_link_config(bp, true);
2152 }
2153
2154 /* Add UDP tunneling port */
2155 static int
2156 bnxt_udp_tunnel_port_add_op(struct rte_eth_dev *eth_dev,
2157                          struct rte_eth_udp_tunnel *udp_tunnel)
2158 {
2159         struct bnxt *bp = eth_dev->data->dev_private;
2160         uint16_t tunnel_type = 0;
2161         int rc = 0;
2162
2163         rc = is_bnxt_in_error(bp);
2164         if (rc)
2165                 return rc;
2166
2167         switch (udp_tunnel->prot_type) {
2168         case RTE_TUNNEL_TYPE_VXLAN:
2169                 if (bp->vxlan_port_cnt) {
2170                         PMD_DRV_LOG(ERR, "Tunnel Port %d already programmed\n",
2171                                 udp_tunnel->udp_port);
2172                         if (bp->vxlan_port != udp_tunnel->udp_port) {
2173                                 PMD_DRV_LOG(ERR, "Only one port allowed\n");
2174                                 return -ENOSPC;
2175                         }
2176                         bp->vxlan_port_cnt++;
2177                         return 0;
2178                 }
2179                 tunnel_type =
2180                         HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_VXLAN;
2181                 bp->vxlan_port_cnt++;
2182                 break;
2183         case RTE_TUNNEL_TYPE_GENEVE:
2184                 if (bp->geneve_port_cnt) {
2185                         PMD_DRV_LOG(ERR, "Tunnel Port %d already programmed\n",
2186                                 udp_tunnel->udp_port);
2187                         if (bp->geneve_port != udp_tunnel->udp_port) {
2188                                 PMD_DRV_LOG(ERR, "Only one port allowed\n");
2189                                 return -ENOSPC;
2190                         }
2191                         bp->geneve_port_cnt++;
2192                         return 0;
2193                 }
2194                 tunnel_type =
2195                         HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_GENEVE;
2196                 bp->geneve_port_cnt++;
2197                 break;
2198         default:
2199                 PMD_DRV_LOG(ERR, "Tunnel type is not supported\n");
2200                 return -ENOTSUP;
2201         }
2202         rc = bnxt_hwrm_tunnel_dst_port_alloc(bp, udp_tunnel->udp_port,
2203                                              tunnel_type);
2204         return rc;
2205 }
2206
2207 static int
2208 bnxt_udp_tunnel_port_del_op(struct rte_eth_dev *eth_dev,
2209                          struct rte_eth_udp_tunnel *udp_tunnel)
2210 {
2211         struct bnxt *bp = eth_dev->data->dev_private;
2212         uint16_t tunnel_type = 0;
2213         uint16_t port = 0;
2214         int rc = 0;
2215
2216         rc = is_bnxt_in_error(bp);
2217         if (rc)
2218                 return rc;
2219
2220         switch (udp_tunnel->prot_type) {
2221         case RTE_TUNNEL_TYPE_VXLAN:
2222                 if (!bp->vxlan_port_cnt) {
2223                         PMD_DRV_LOG(ERR, "No Tunnel port configured yet\n");
2224                         return -EINVAL;
2225                 }
2226                 if (bp->vxlan_port != udp_tunnel->udp_port) {
2227                         PMD_DRV_LOG(ERR, "Req Port: %d. Configured port: %d\n",
2228                                 udp_tunnel->udp_port, bp->vxlan_port);
2229                         return -EINVAL;
2230                 }
2231                 if (--bp->vxlan_port_cnt)
2232                         return 0;
2233
2234                 tunnel_type =
2235                         HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN;
2236                 port = bp->vxlan_fw_dst_port_id;
2237                 break;
2238         case RTE_TUNNEL_TYPE_GENEVE:
2239                 if (!bp->geneve_port_cnt) {
2240                         PMD_DRV_LOG(ERR, "No Tunnel port configured yet\n");
2241                         return -EINVAL;
2242                 }
2243                 if (bp->geneve_port != udp_tunnel->udp_port) {
2244                         PMD_DRV_LOG(ERR, "Req Port: %d. Configured port: %d\n",
2245                                 udp_tunnel->udp_port, bp->geneve_port);
2246                         return -EINVAL;
2247                 }
2248                 if (--bp->geneve_port_cnt)
2249                         return 0;
2250
2251                 tunnel_type =
2252                         HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_GENEVE;
2253                 port = bp->geneve_fw_dst_port_id;
2254                 break;
2255         default:
2256                 PMD_DRV_LOG(ERR, "Tunnel type is not supported\n");
2257                 return -ENOTSUP;
2258         }
2259
2260         rc = bnxt_hwrm_tunnel_dst_port_free(bp, port, tunnel_type);
2261         return rc;
2262 }
2263
2264 static int bnxt_del_vlan_filter(struct bnxt *bp, uint16_t vlan_id)
2265 {
2266         struct bnxt_filter_info *filter;
2267         struct bnxt_vnic_info *vnic;
2268         int rc = 0;
2269         uint32_t chk = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN;
2270
2271         vnic = BNXT_GET_DEFAULT_VNIC(bp);
2272         filter = STAILQ_FIRST(&vnic->filter);
2273         while (filter) {
2274                 /* Search for this matching MAC+VLAN filter */
2275                 if (bnxt_vlan_filter_exists(bp, filter, chk, vlan_id)) {
2276                         /* Delete the filter */
2277                         rc = bnxt_hwrm_clear_l2_filter(bp, filter);
2278                         if (rc)
2279                                 return rc;
2280                         STAILQ_REMOVE(&vnic->filter, filter,
2281                                       bnxt_filter_info, next);
2282                         bnxt_free_filter(bp, filter);
2283                         PMD_DRV_LOG(INFO,
2284                                     "Deleted vlan filter for %d\n",
2285                                     vlan_id);
2286                         return 0;
2287                 }
2288                 filter = STAILQ_NEXT(filter, next);
2289         }
2290         return -ENOENT;
2291 }
2292
2293 static int bnxt_add_vlan_filter(struct bnxt *bp, uint16_t vlan_id)
2294 {
2295         struct bnxt_filter_info *filter;
2296         struct bnxt_vnic_info *vnic;
2297         int rc = 0;
2298         uint32_t en = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN |
2299                 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN_MASK;
2300         uint32_t chk = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN;
2301
2302         /* Implementation notes on the use of VNIC in this command:
2303          *
2304          * By default, these filters belong to default vnic for the function.
2305          * Once these filters are set up, only destination VNIC can be modified.
2306          * If the destination VNIC is not specified in this command,
2307          * then the HWRM shall only create an l2 context id.
2308          */
2309
2310         vnic = BNXT_GET_DEFAULT_VNIC(bp);
2311         filter = STAILQ_FIRST(&vnic->filter);
2312         /* Check if the VLAN has already been added */
2313         while (filter) {
2314                 if (bnxt_vlan_filter_exists(bp, filter, chk, vlan_id))
2315                         return -EEXIST;
2316
2317                 filter = STAILQ_NEXT(filter, next);
2318         }
2319
2320         /* No match found. Alloc a fresh filter and issue the L2_FILTER_ALLOC
2321          * command to create MAC+VLAN filter with the right flags, enables set.
2322          */
2323         filter = bnxt_alloc_filter(bp);
2324         if (!filter) {
2325                 PMD_DRV_LOG(ERR,
2326                             "MAC/VLAN filter alloc failed\n");
2327                 return -ENOMEM;
2328         }
2329         /* MAC + VLAN ID filter */
2330         /* If l2_ivlan == 0 and l2_ivlan_mask != 0, only
2331          * untagged packets are received
2332          *
2333          * If l2_ivlan != 0 and l2_ivlan_mask != 0, untagged
2334          * packets and only the programmed vlan's packets are received
2335          */
2336         filter->l2_ivlan = vlan_id;
2337         filter->l2_ivlan_mask = 0x0FFF;
2338         filter->enables |= en;
2339         filter->flags |= HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_OUTERMOST;
2340
2341         rc = bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id, filter);
2342         if (rc) {
2343                 /* Free the newly allocated filter as we were
2344                  * not able to create the filter in hardware.
2345                  */
2346                 bnxt_free_filter(bp, filter);
2347                 return rc;
2348         }
2349
2350         filter->mac_index = 0;
2351         /* Add this new filter to the list */
2352         if (vlan_id == 0)
2353                 STAILQ_INSERT_HEAD(&vnic->filter, filter, next);
2354         else
2355                 STAILQ_INSERT_TAIL(&vnic->filter, filter, next);
2356
2357         PMD_DRV_LOG(INFO,
2358                     "Added Vlan filter for %d\n", vlan_id);
2359         return rc;
2360 }
2361
2362 static int bnxt_vlan_filter_set_op(struct rte_eth_dev *eth_dev,
2363                 uint16_t vlan_id, int on)
2364 {
2365         struct bnxt *bp = eth_dev->data->dev_private;
2366         int rc;
2367
2368         rc = is_bnxt_in_error(bp);
2369         if (rc)
2370                 return rc;
2371
2372         if (!eth_dev->data->dev_started) {
2373                 PMD_DRV_LOG(ERR, "port must be started before setting vlan\n");
2374                 return -EINVAL;
2375         }
2376
2377         /* These operations apply to ALL existing MAC/VLAN filters */
2378         if (on)
2379                 return bnxt_add_vlan_filter(bp, vlan_id);
2380         else
2381                 return bnxt_del_vlan_filter(bp, vlan_id);
2382 }
2383
2384 static int bnxt_del_dflt_mac_filter(struct bnxt *bp,
2385                                     struct bnxt_vnic_info *vnic)
2386 {
2387         struct bnxt_filter_info *filter;
2388         int rc;
2389
2390         filter = STAILQ_FIRST(&vnic->filter);
2391         while (filter) {
2392                 if (filter->mac_index == 0 &&
2393                     !memcmp(filter->l2_addr, bp->mac_addr,
2394                             RTE_ETHER_ADDR_LEN)) {
2395                         rc = bnxt_hwrm_clear_l2_filter(bp, filter);
2396                         if (!rc) {
2397                                 STAILQ_REMOVE(&vnic->filter, filter,
2398                                               bnxt_filter_info, next);
2399                                 bnxt_free_filter(bp, filter);
2400                         }
2401                         return rc;
2402                 }
2403                 filter = STAILQ_NEXT(filter, next);
2404         }
2405         return 0;
2406 }
2407
2408 static int
2409 bnxt_config_vlan_hw_filter(struct bnxt *bp, uint64_t rx_offloads)
2410 {
2411         struct bnxt_vnic_info *vnic;
2412         unsigned int i;
2413         int rc;
2414
2415         vnic = BNXT_GET_DEFAULT_VNIC(bp);
2416         if (!(rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER)) {
2417                 /* Remove any VLAN filters programmed */
2418                 for (i = 0; i < RTE_ETHER_MAX_VLAN_ID; i++)
2419                         bnxt_del_vlan_filter(bp, i);
2420
2421                 rc = bnxt_add_mac_filter(bp, vnic, NULL, 0, 0);
2422                 if (rc)
2423                         return rc;
2424         } else {
2425                 /* Default filter will allow packets that match the
2426                  * dest mac. So, it has to be deleted, otherwise, we
2427                  * will endup receiving vlan packets for which the
2428                  * filter is not programmed, when hw-vlan-filter
2429                  * configuration is ON
2430                  */
2431                 bnxt_del_dflt_mac_filter(bp, vnic);
2432                 /* This filter will allow only untagged packets */
2433                 bnxt_add_vlan_filter(bp, 0);
2434         }
2435         PMD_DRV_LOG(DEBUG, "VLAN Filtering: %d\n",
2436                     !!(rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER));
2437
2438         return 0;
2439 }
2440
2441 static int bnxt_free_one_vnic(struct bnxt *bp, uint16_t vnic_id)
2442 {
2443         struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id];
2444         unsigned int i;
2445         int rc;
2446
2447         /* Destroy vnic filters and vnic */
2448         if (bp->eth_dev->data->dev_conf.rxmode.offloads &
2449             DEV_RX_OFFLOAD_VLAN_FILTER) {
2450                 for (i = 0; i < RTE_ETHER_MAX_VLAN_ID; i++)
2451                         bnxt_del_vlan_filter(bp, i);
2452         }
2453         bnxt_del_dflt_mac_filter(bp, vnic);
2454
2455         rc = bnxt_hwrm_vnic_free(bp, vnic);
2456         if (rc)
2457                 return rc;
2458
2459         rte_free(vnic->fw_grp_ids);
2460         vnic->fw_grp_ids = NULL;
2461
2462         vnic->rx_queue_cnt = 0;
2463
2464         return 0;
2465 }
2466
2467 static int
2468 bnxt_config_vlan_hw_stripping(struct bnxt *bp, uint64_t rx_offloads)
2469 {
2470         struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp);
2471         int rc;
2472
2473         /* Destroy, recreate and reconfigure the default vnic */
2474         rc = bnxt_free_one_vnic(bp, 0);
2475         if (rc)
2476                 return rc;
2477
2478         /* default vnic 0 */
2479         rc = bnxt_setup_one_vnic(bp, 0);
2480         if (rc)
2481                 return rc;
2482
2483         if (bp->eth_dev->data->dev_conf.rxmode.offloads &
2484             DEV_RX_OFFLOAD_VLAN_FILTER) {
2485                 rc = bnxt_add_vlan_filter(bp, 0);
2486                 if (rc)
2487                         return rc;
2488                 rc = bnxt_restore_vlan_filters(bp);
2489                 if (rc)
2490                         return rc;
2491         } else {
2492                 rc = bnxt_add_mac_filter(bp, vnic, NULL, 0, 0);
2493                 if (rc)
2494                         return rc;
2495         }
2496
2497         rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
2498         if (rc)
2499                 return rc;
2500
2501         PMD_DRV_LOG(DEBUG, "VLAN Strip Offload: %d\n",
2502                     !!(rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP));
2503
2504         return rc;
2505 }
2506
2507 static int
2508 bnxt_vlan_offload_set_op(struct rte_eth_dev *dev, int mask)
2509 {
2510         uint64_t rx_offloads = dev->data->dev_conf.rxmode.offloads;
2511         struct bnxt *bp = dev->data->dev_private;
2512         int rc;
2513
2514         rc = is_bnxt_in_error(bp);
2515         if (rc)
2516                 return rc;
2517
2518         /* Filter settings will get applied when port is started */
2519         if (!dev->data->dev_started)
2520                 return 0;
2521
2522         if (mask & ETH_VLAN_FILTER_MASK) {
2523                 /* Enable or disable VLAN filtering */
2524                 rc = bnxt_config_vlan_hw_filter(bp, rx_offloads);
2525                 if (rc)
2526                         return rc;
2527         }
2528
2529         if (mask & ETH_VLAN_STRIP_MASK) {
2530                 /* Enable or disable VLAN stripping */
2531                 rc = bnxt_config_vlan_hw_stripping(bp, rx_offloads);
2532                 if (rc)
2533                         return rc;
2534         }
2535
2536         if (mask & ETH_VLAN_EXTEND_MASK) {
2537                 if (rx_offloads & DEV_RX_OFFLOAD_VLAN_EXTEND)
2538                         PMD_DRV_LOG(DEBUG, "Extend VLAN supported\n");
2539                 else
2540                         PMD_DRV_LOG(INFO, "Extend VLAN unsupported\n");
2541         }
2542
2543         return 0;
2544 }
2545
2546 static int
2547 bnxt_vlan_tpid_set_op(struct rte_eth_dev *dev, enum rte_vlan_type vlan_type,
2548                       uint16_t tpid)
2549 {
2550         struct bnxt *bp = dev->data->dev_private;
2551         int qinq = dev->data->dev_conf.rxmode.offloads &
2552                    DEV_RX_OFFLOAD_VLAN_EXTEND;
2553
2554         if (vlan_type != ETH_VLAN_TYPE_INNER &&
2555             vlan_type != ETH_VLAN_TYPE_OUTER) {
2556                 PMD_DRV_LOG(ERR,
2557                             "Unsupported vlan type.");
2558                 return -EINVAL;
2559         }
2560         if (!qinq) {
2561                 PMD_DRV_LOG(ERR,
2562                             "QinQ not enabled. Needs to be ON as we can "
2563                             "accelerate only outer vlan\n");
2564                 return -EINVAL;
2565         }
2566
2567         if (vlan_type == ETH_VLAN_TYPE_OUTER) {
2568                 switch (tpid) {
2569                 case RTE_ETHER_TYPE_QINQ:
2570                         bp->outer_tpid_bd =
2571                                 TX_BD_LONG_CFA_META_VLAN_TPID_TPID88A8;
2572                                 break;
2573                 case RTE_ETHER_TYPE_VLAN:
2574                         bp->outer_tpid_bd =
2575                                 TX_BD_LONG_CFA_META_VLAN_TPID_TPID8100;
2576                                 break;
2577                 case RTE_ETHER_TYPE_QINQ1:
2578                         bp->outer_tpid_bd =
2579                                 TX_BD_LONG_CFA_META_VLAN_TPID_TPID9100;
2580                                 break;
2581                 case RTE_ETHER_TYPE_QINQ2:
2582                         bp->outer_tpid_bd =
2583                                 TX_BD_LONG_CFA_META_VLAN_TPID_TPID9200;
2584                                 break;
2585                 case RTE_ETHER_TYPE_QINQ3:
2586                         bp->outer_tpid_bd =
2587                                  TX_BD_LONG_CFA_META_VLAN_TPID_TPID9300;
2588                                 break;
2589                 default:
2590                         PMD_DRV_LOG(ERR, "Invalid TPID: %x\n", tpid);
2591                         return -EINVAL;
2592                 }
2593                 bp->outer_tpid_bd |= tpid;
2594                 PMD_DRV_LOG(INFO, "outer_tpid_bd = %x\n", bp->outer_tpid_bd);
2595         } else if (vlan_type == ETH_VLAN_TYPE_INNER) {
2596                 PMD_DRV_LOG(ERR,
2597                             "Can accelerate only outer vlan in QinQ\n");
2598                 return -EINVAL;
2599         }
2600
2601         return 0;
2602 }
2603
2604 static int
2605 bnxt_set_default_mac_addr_op(struct rte_eth_dev *dev,
2606                              struct rte_ether_addr *addr)
2607 {
2608         struct bnxt *bp = dev->data->dev_private;
2609         /* Default Filter is tied to VNIC 0 */
2610         struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp);
2611         int rc;
2612
2613         rc = is_bnxt_in_error(bp);
2614         if (rc)
2615                 return rc;
2616
2617         if (BNXT_VF(bp) && !BNXT_VF_IS_TRUSTED(bp))
2618                 return -EPERM;
2619
2620         if (rte_is_zero_ether_addr(addr))
2621                 return -EINVAL;
2622
2623         /* Filter settings will get applied when port is started */
2624         if (!dev->data->dev_started)
2625                 return 0;
2626
2627         /* Check if the requested MAC is already added */
2628         if (memcmp(addr, bp->mac_addr, RTE_ETHER_ADDR_LEN) == 0)
2629                 return 0;
2630
2631         /* Destroy filter and re-create it */
2632         bnxt_del_dflt_mac_filter(bp, vnic);
2633
2634         memcpy(bp->mac_addr, addr, RTE_ETHER_ADDR_LEN);
2635         if (dev->data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_VLAN_FILTER) {
2636                 /* This filter will allow only untagged packets */
2637                 rc = bnxt_add_vlan_filter(bp, 0);
2638         } else {
2639                 rc = bnxt_add_mac_filter(bp, vnic, addr, 0, 0);
2640         }
2641
2642         PMD_DRV_LOG(DEBUG, "Set MAC addr\n");
2643         return rc;
2644 }
2645
2646 static int
2647 bnxt_dev_set_mc_addr_list_op(struct rte_eth_dev *eth_dev,
2648                           struct rte_ether_addr *mc_addr_set,
2649                           uint32_t nb_mc_addr)
2650 {
2651         struct bnxt *bp = eth_dev->data->dev_private;
2652         char *mc_addr_list = (char *)mc_addr_set;
2653         struct bnxt_vnic_info *vnic;
2654         uint32_t off = 0, i = 0;
2655         int rc;
2656
2657         rc = is_bnxt_in_error(bp);
2658         if (rc)
2659                 return rc;
2660
2661         vnic = BNXT_GET_DEFAULT_VNIC(bp);
2662
2663         if (nb_mc_addr > BNXT_MAX_MC_ADDRS) {
2664                 vnic->flags |= BNXT_VNIC_INFO_ALLMULTI;
2665                 goto allmulti;
2666         }
2667
2668         /* TODO Check for Duplicate mcast addresses */
2669         vnic->flags &= ~BNXT_VNIC_INFO_ALLMULTI;
2670         for (i = 0; i < nb_mc_addr; i++) {
2671                 memcpy(vnic->mc_list + off, &mc_addr_list[i],
2672                         RTE_ETHER_ADDR_LEN);
2673                 off += RTE_ETHER_ADDR_LEN;
2674         }
2675
2676         vnic->mc_addr_cnt = i;
2677         if (vnic->mc_addr_cnt)
2678                 vnic->flags |= BNXT_VNIC_INFO_MCAST;
2679         else
2680                 vnic->flags &= ~BNXT_VNIC_INFO_MCAST;
2681
2682 allmulti:
2683         return bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
2684 }
2685
2686 static int
2687 bnxt_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size)
2688 {
2689         struct bnxt *bp = dev->data->dev_private;
2690         uint8_t fw_major = (bp->fw_ver >> 24) & 0xff;
2691         uint8_t fw_minor = (bp->fw_ver >> 16) & 0xff;
2692         uint8_t fw_updt = (bp->fw_ver >> 8) & 0xff;
2693         uint8_t fw_rsvd = bp->fw_ver & 0xff;
2694         int ret;
2695
2696         ret = snprintf(fw_version, fw_size, "%d.%d.%d.%d",
2697                         fw_major, fw_minor, fw_updt, fw_rsvd);
2698
2699         ret += 1; /* add the size of '\0' */
2700         if (fw_size < (uint32_t)ret)
2701                 return ret;
2702         else
2703                 return 0;
2704 }
2705
2706 static void
2707 bnxt_rxq_info_get_op(struct rte_eth_dev *dev, uint16_t queue_id,
2708         struct rte_eth_rxq_info *qinfo)
2709 {
2710         struct bnxt *bp = dev->data->dev_private;
2711         struct bnxt_rx_queue *rxq;
2712
2713         if (is_bnxt_in_error(bp))
2714                 return;
2715
2716         rxq = dev->data->rx_queues[queue_id];
2717
2718         qinfo->mp = rxq->mb_pool;
2719         qinfo->scattered_rx = dev->data->scattered_rx;
2720         qinfo->nb_desc = rxq->nb_rx_desc;
2721
2722         qinfo->conf.rx_free_thresh = rxq->rx_free_thresh;
2723         qinfo->conf.rx_drop_en = rxq->drop_en;
2724         qinfo->conf.rx_deferred_start = rxq->rx_deferred_start;
2725         qinfo->conf.offloads = dev->data->dev_conf.rxmode.offloads;
2726 }
2727
2728 static void
2729 bnxt_txq_info_get_op(struct rte_eth_dev *dev, uint16_t queue_id,
2730         struct rte_eth_txq_info *qinfo)
2731 {
2732         struct bnxt *bp = dev->data->dev_private;
2733         struct bnxt_tx_queue *txq;
2734
2735         if (is_bnxt_in_error(bp))
2736                 return;
2737
2738         txq = dev->data->tx_queues[queue_id];
2739
2740         qinfo->nb_desc = txq->nb_tx_desc;
2741
2742         qinfo->conf.tx_thresh.pthresh = txq->pthresh;
2743         qinfo->conf.tx_thresh.hthresh = txq->hthresh;
2744         qinfo->conf.tx_thresh.wthresh = txq->wthresh;
2745
2746         qinfo->conf.tx_free_thresh = txq->tx_free_thresh;
2747         qinfo->conf.tx_rs_thresh = 0;
2748         qinfo->conf.tx_deferred_start = txq->tx_deferred_start;
2749         qinfo->conf.offloads = txq->offloads;
2750 }
2751
2752 static const struct {
2753         eth_rx_burst_t pkt_burst;
2754         const char *info;
2755 } bnxt_rx_burst_info[] = {
2756         {bnxt_recv_pkts,        "Scalar"},
2757 #if defined(RTE_ARCH_X86)
2758         {bnxt_recv_pkts_vec,    "Vector SSE"},
2759 #elif defined(RTE_ARCH_ARM64)
2760         {bnxt_recv_pkts_vec,    "Vector Neon"},
2761 #endif
2762 };
2763
2764 static int
2765 bnxt_rx_burst_mode_get(struct rte_eth_dev *dev, __rte_unused uint16_t queue_id,
2766                        struct rte_eth_burst_mode *mode)
2767 {
2768         eth_rx_burst_t pkt_burst = dev->rx_pkt_burst;
2769         size_t i;
2770
2771         for (i = 0; i < RTE_DIM(bnxt_rx_burst_info); i++) {
2772                 if (pkt_burst == bnxt_rx_burst_info[i].pkt_burst) {
2773                         snprintf(mode->info, sizeof(mode->info), "%s",
2774                                  bnxt_rx_burst_info[i].info);
2775                         return 0;
2776                 }
2777         }
2778
2779         return -EINVAL;
2780 }
2781
2782 static const struct {
2783         eth_tx_burst_t pkt_burst;
2784         const char *info;
2785 } bnxt_tx_burst_info[] = {
2786         {bnxt_xmit_pkts,        "Scalar"},
2787 #if defined(RTE_ARCH_X86)
2788         {bnxt_xmit_pkts_vec,    "Vector SSE"},
2789 #elif defined(RTE_ARCH_ARM64)
2790         {bnxt_xmit_pkts_vec,    "Vector Neon"},
2791 #endif
2792 };
2793
2794 static int
2795 bnxt_tx_burst_mode_get(struct rte_eth_dev *dev, __rte_unused uint16_t queue_id,
2796                        struct rte_eth_burst_mode *mode)
2797 {
2798         eth_tx_burst_t pkt_burst = dev->tx_pkt_burst;
2799         size_t i;
2800
2801         for (i = 0; i < RTE_DIM(bnxt_tx_burst_info); i++) {
2802                 if (pkt_burst == bnxt_tx_burst_info[i].pkt_burst) {
2803                         snprintf(mode->info, sizeof(mode->info), "%s",
2804                                  bnxt_tx_burst_info[i].info);
2805                         return 0;
2806                 }
2807         }
2808
2809         return -EINVAL;
2810 }
2811
2812 int bnxt_mtu_set_op(struct rte_eth_dev *eth_dev, uint16_t new_mtu)
2813 {
2814         struct bnxt *bp = eth_dev->data->dev_private;
2815         uint32_t new_pkt_size;
2816         uint32_t rc = 0;
2817         uint32_t i;
2818
2819         rc = is_bnxt_in_error(bp);
2820         if (rc)
2821                 return rc;
2822
2823         /* Exit if receive queues are not configured yet */
2824         if (!eth_dev->data->nb_rx_queues)
2825                 return rc;
2826
2827         new_pkt_size = new_mtu + RTE_ETHER_HDR_LEN + RTE_ETHER_CRC_LEN +
2828                        VLAN_TAG_SIZE * BNXT_NUM_VLANS;
2829
2830         /*
2831          * Disallow any MTU change that would require scattered receive support
2832          * if it is not already enabled.
2833          */
2834         if (eth_dev->data->dev_started &&
2835             !eth_dev->data->scattered_rx &&
2836             (new_pkt_size >
2837              eth_dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM)) {
2838                 PMD_DRV_LOG(ERR,
2839                             "MTU change would require scattered rx support. ");
2840                 PMD_DRV_LOG(ERR, "Stop port before changing MTU.\n");
2841                 return -EINVAL;
2842         }
2843
2844         if (new_mtu > RTE_ETHER_MTU) {
2845                 bp->flags |= BNXT_FLAG_JUMBO;
2846                 bp->eth_dev->data->dev_conf.rxmode.offloads |=
2847                         DEV_RX_OFFLOAD_JUMBO_FRAME;
2848         } else {
2849                 bp->eth_dev->data->dev_conf.rxmode.offloads &=
2850                         ~DEV_RX_OFFLOAD_JUMBO_FRAME;
2851                 bp->flags &= ~BNXT_FLAG_JUMBO;
2852         }
2853
2854         /* Is there a change in mtu setting? */
2855         if (eth_dev->data->dev_conf.rxmode.max_rx_pkt_len == new_pkt_size)
2856                 return rc;
2857
2858         for (i = 0; i < bp->nr_vnics; i++) {
2859                 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
2860                 uint16_t size = 0;
2861
2862                 vnic->mru = BNXT_VNIC_MRU(new_mtu);
2863                 rc = bnxt_hwrm_vnic_cfg(bp, vnic);
2864                 if (rc)
2865                         break;
2866
2867                 size = rte_pktmbuf_data_room_size(bp->rx_queues[0]->mb_pool);
2868                 size -= RTE_PKTMBUF_HEADROOM;
2869
2870                 if (size < new_mtu) {
2871                         rc = bnxt_hwrm_vnic_plcmode_cfg(bp, vnic);
2872                         if (rc)
2873                                 return rc;
2874                 }
2875         }
2876
2877         if (!rc)
2878                 eth_dev->data->dev_conf.rxmode.max_rx_pkt_len = new_pkt_size;
2879
2880         PMD_DRV_LOG(INFO, "New MTU is %d\n", new_mtu);
2881
2882         return rc;
2883 }
2884
2885 static int
2886 bnxt_vlan_pvid_set_op(struct rte_eth_dev *dev, uint16_t pvid, int on)
2887 {
2888         struct bnxt *bp = dev->data->dev_private;
2889         uint16_t vlan = bp->vlan;
2890         int rc;
2891
2892         rc = is_bnxt_in_error(bp);
2893         if (rc)
2894                 return rc;
2895
2896         if (!BNXT_SINGLE_PF(bp) || BNXT_VF(bp)) {
2897                 PMD_DRV_LOG(ERR,
2898                         "PVID cannot be modified for this function\n");
2899                 return -ENOTSUP;
2900         }
2901         bp->vlan = on ? pvid : 0;
2902
2903         rc = bnxt_hwrm_set_default_vlan(bp, 0, 0);
2904         if (rc)
2905                 bp->vlan = vlan;
2906         return rc;
2907 }
2908
2909 static int
2910 bnxt_dev_led_on_op(struct rte_eth_dev *dev)
2911 {
2912         struct bnxt *bp = dev->data->dev_private;
2913         int rc;
2914
2915         rc = is_bnxt_in_error(bp);
2916         if (rc)
2917                 return rc;
2918
2919         return bnxt_hwrm_port_led_cfg(bp, true);
2920 }
2921
2922 static int
2923 bnxt_dev_led_off_op(struct rte_eth_dev *dev)
2924 {
2925         struct bnxt *bp = dev->data->dev_private;
2926         int rc;
2927
2928         rc = is_bnxt_in_error(bp);
2929         if (rc)
2930                 return rc;
2931
2932         return bnxt_hwrm_port_led_cfg(bp, false);
2933 }
2934
2935 static uint32_t
2936 bnxt_rx_queue_count_op(struct rte_eth_dev *dev, uint16_t rx_queue_id)
2937 {
2938         struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
2939         uint32_t desc = 0, raw_cons = 0, cons;
2940         struct bnxt_cp_ring_info *cpr;
2941         struct bnxt_rx_queue *rxq;
2942         struct rx_pkt_cmpl *rxcmp;
2943         int rc;
2944
2945         rc = is_bnxt_in_error(bp);
2946         if (rc)
2947                 return rc;
2948
2949         rxq = dev->data->rx_queues[rx_queue_id];
2950         cpr = rxq->cp_ring;
2951         raw_cons = cpr->cp_raw_cons;
2952
2953         while (1) {
2954                 cons = RING_CMP(cpr->cp_ring_struct, raw_cons);
2955                 rte_prefetch0(&cpr->cp_desc_ring[cons]);
2956                 rxcmp = (struct rx_pkt_cmpl *)&cpr->cp_desc_ring[cons];
2957
2958                 if (!CMP_VALID(rxcmp, raw_cons, cpr->cp_ring_struct)) {
2959                         break;
2960                 } else {
2961                         raw_cons++;
2962                         desc++;
2963                 }
2964         }
2965
2966         return desc;
2967 }
2968
2969 static int
2970 bnxt_rx_descriptor_status_op(void *rx_queue, uint16_t offset)
2971 {
2972         struct bnxt_rx_queue *rxq = (struct bnxt_rx_queue *)rx_queue;
2973         struct bnxt_rx_ring_info *rxr;
2974         struct bnxt_cp_ring_info *cpr;
2975         struct rte_mbuf *rx_buf;
2976         struct rx_pkt_cmpl *rxcmp;
2977         uint32_t cons, cp_cons;
2978         int rc;
2979
2980         if (!rxq)
2981                 return -EINVAL;
2982
2983         rc = is_bnxt_in_error(rxq->bp);
2984         if (rc)
2985                 return rc;
2986
2987         cpr = rxq->cp_ring;
2988         rxr = rxq->rx_ring;
2989
2990         if (offset >= rxq->nb_rx_desc)
2991                 return -EINVAL;
2992
2993         cons = RING_CMP(cpr->cp_ring_struct, offset);
2994         cp_cons = cpr->cp_raw_cons;
2995         rxcmp = (struct rx_pkt_cmpl *)&cpr->cp_desc_ring[cons];
2996
2997         if (cons > cp_cons) {
2998                 if (CMPL_VALID(rxcmp, cpr->valid))
2999                         return RTE_ETH_RX_DESC_DONE;
3000         } else {
3001                 if (CMPL_VALID(rxcmp, !cpr->valid))
3002                         return RTE_ETH_RX_DESC_DONE;
3003         }
3004         rx_buf = rxr->rx_buf_ring[cons];
3005         if (rx_buf == NULL || rx_buf == &rxq->fake_mbuf)
3006                 return RTE_ETH_RX_DESC_UNAVAIL;
3007
3008
3009         return RTE_ETH_RX_DESC_AVAIL;
3010 }
3011
3012 static int
3013 bnxt_tx_descriptor_status_op(void *tx_queue, uint16_t offset)
3014 {
3015         struct bnxt_tx_queue *txq = (struct bnxt_tx_queue *)tx_queue;
3016         struct bnxt_tx_ring_info *txr;
3017         struct bnxt_cp_ring_info *cpr;
3018         struct bnxt_sw_tx_bd *tx_buf;
3019         struct tx_pkt_cmpl *txcmp;
3020         uint32_t cons, cp_cons;
3021         int rc;
3022
3023         if (!txq)
3024                 return -EINVAL;
3025
3026         rc = is_bnxt_in_error(txq->bp);
3027         if (rc)
3028                 return rc;
3029
3030         cpr = txq->cp_ring;
3031         txr = txq->tx_ring;
3032
3033         if (offset >= txq->nb_tx_desc)
3034                 return -EINVAL;
3035
3036         cons = RING_CMP(cpr->cp_ring_struct, offset);
3037         txcmp = (struct tx_pkt_cmpl *)&cpr->cp_desc_ring[cons];
3038         cp_cons = cpr->cp_raw_cons;
3039
3040         if (cons > cp_cons) {
3041                 if (CMPL_VALID(txcmp, cpr->valid))
3042                         return RTE_ETH_TX_DESC_UNAVAIL;
3043         } else {
3044                 if (CMPL_VALID(txcmp, !cpr->valid))
3045                         return RTE_ETH_TX_DESC_UNAVAIL;
3046         }
3047         tx_buf = &txr->tx_buf_ring[cons];
3048         if (tx_buf->mbuf == NULL)
3049                 return RTE_ETH_TX_DESC_DONE;
3050
3051         return RTE_ETH_TX_DESC_FULL;
3052 }
3053
3054 int
3055 bnxt_filter_ctrl_op(struct rte_eth_dev *dev,
3056                     enum rte_filter_type filter_type,
3057                     enum rte_filter_op filter_op, void *arg)
3058 {
3059         struct bnxt *bp = dev->data->dev_private;
3060         int ret = 0;
3061
3062         if (!bp)
3063                 return -EIO;
3064
3065         if (BNXT_ETH_DEV_IS_REPRESENTOR(dev)) {
3066                 struct bnxt_representor *vfr = dev->data->dev_private;
3067                 bp = vfr->parent_dev->data->dev_private;
3068                 /* parent is deleted while children are still valid */
3069                 if (!bp) {
3070                         PMD_DRV_LOG(DEBUG, "BNXT Port:%d VFR Error %d:%d\n",
3071                                     dev->data->port_id,
3072                                     filter_type,
3073                                     filter_op);
3074                         return -EIO;
3075                 }
3076         }
3077
3078         ret = is_bnxt_in_error(bp);
3079         if (ret)
3080                 return ret;
3081
3082         switch (filter_type) {
3083         case RTE_ETH_FILTER_GENERIC:
3084                 if (filter_op != RTE_ETH_FILTER_GET)
3085                         return -EINVAL;
3086
3087                 /* PMD supports thread-safe flow operations.  rte_flow API
3088                  * functions can avoid mutex for multi-thread safety.
3089                  */
3090                 dev->data->dev_flags |= RTE_ETH_DEV_FLOW_OPS_THREAD_SAFE;
3091
3092                 if (BNXT_TRUFLOW_EN(bp))
3093                         *(const void **)arg = &bnxt_ulp_rte_flow_ops;
3094                 else
3095                         *(const void **)arg = &bnxt_flow_ops;
3096                 break;
3097         default:
3098                 PMD_DRV_LOG(ERR,
3099                         "Filter type (%d) not supported", filter_type);
3100                 ret = -EINVAL;
3101                 break;
3102         }
3103         return ret;
3104 }
3105
3106 static const uint32_t *
3107 bnxt_dev_supported_ptypes_get_op(struct rte_eth_dev *dev)
3108 {
3109         static const uint32_t ptypes[] = {
3110                 RTE_PTYPE_L2_ETHER_VLAN,
3111                 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN,
3112                 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN,
3113                 RTE_PTYPE_L4_ICMP,
3114                 RTE_PTYPE_L4_TCP,
3115                 RTE_PTYPE_L4_UDP,
3116                 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN,
3117                 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN,
3118                 RTE_PTYPE_INNER_L4_ICMP,
3119                 RTE_PTYPE_INNER_L4_TCP,
3120                 RTE_PTYPE_INNER_L4_UDP,
3121                 RTE_PTYPE_UNKNOWN
3122         };
3123
3124         if (!dev->rx_pkt_burst)
3125                 return NULL;
3126
3127         return ptypes;
3128 }
3129
3130 static int bnxt_map_regs(struct bnxt *bp, uint32_t *reg_arr, int count,
3131                          int reg_win)
3132 {
3133         uint32_t reg_base = *reg_arr & 0xfffff000;
3134         uint32_t win_off;
3135         int i;
3136
3137         for (i = 0; i < count; i++) {
3138                 if ((reg_arr[i] & 0xfffff000) != reg_base)
3139                         return -ERANGE;
3140         }
3141         win_off = BNXT_GRCPF_REG_WINDOW_BASE_OUT + (reg_win - 1) * 4;
3142         rte_write32(reg_base, (uint8_t *)bp->bar0 + win_off);
3143         return 0;
3144 }
3145
3146 static int bnxt_map_ptp_regs(struct bnxt *bp)
3147 {
3148         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3149         uint32_t *reg_arr;
3150         int rc, i;
3151
3152         reg_arr = ptp->rx_regs;
3153         rc = bnxt_map_regs(bp, reg_arr, BNXT_PTP_RX_REGS, 5);
3154         if (rc)
3155                 return rc;
3156
3157         reg_arr = ptp->tx_regs;
3158         rc = bnxt_map_regs(bp, reg_arr, BNXT_PTP_TX_REGS, 6);
3159         if (rc)
3160                 return rc;
3161
3162         for (i = 0; i < BNXT_PTP_RX_REGS; i++)
3163                 ptp->rx_mapped_regs[i] = 0x5000 + (ptp->rx_regs[i] & 0xfff);
3164
3165         for (i = 0; i < BNXT_PTP_TX_REGS; i++)
3166                 ptp->tx_mapped_regs[i] = 0x6000 + (ptp->tx_regs[i] & 0xfff);
3167
3168         return 0;
3169 }
3170
3171 static void bnxt_unmap_ptp_regs(struct bnxt *bp)
3172 {
3173         rte_write32(0, (uint8_t *)bp->bar0 +
3174                          BNXT_GRCPF_REG_WINDOW_BASE_OUT + 16);
3175         rte_write32(0, (uint8_t *)bp->bar0 +
3176                          BNXT_GRCPF_REG_WINDOW_BASE_OUT + 20);
3177 }
3178
3179 static uint64_t bnxt_cc_read(struct bnxt *bp)
3180 {
3181         uint64_t ns;
3182
3183         ns = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3184                               BNXT_GRCPF_REG_SYNC_TIME));
3185         ns |= (uint64_t)(rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3186                                           BNXT_GRCPF_REG_SYNC_TIME + 4))) << 32;
3187         return ns;
3188 }
3189
3190 static int bnxt_get_tx_ts(struct bnxt *bp, uint64_t *ts)
3191 {
3192         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3193         uint32_t fifo;
3194
3195         fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3196                                 ptp->tx_mapped_regs[BNXT_PTP_TX_FIFO]));
3197         if (fifo & BNXT_PTP_TX_FIFO_EMPTY)
3198                 return -EAGAIN;
3199
3200         fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3201                                 ptp->tx_mapped_regs[BNXT_PTP_TX_FIFO]));
3202         *ts = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3203                                 ptp->tx_mapped_regs[BNXT_PTP_TX_TS_L]));
3204         *ts |= (uint64_t)rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3205                                 ptp->tx_mapped_regs[BNXT_PTP_TX_TS_H])) << 32;
3206
3207         return 0;
3208 }
3209
3210 static int bnxt_get_rx_ts(struct bnxt *bp, uint64_t *ts)
3211 {
3212         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3213         struct bnxt_pf_info *pf = bp->pf;
3214         uint16_t port_id;
3215         uint32_t fifo;
3216
3217         if (!ptp)
3218                 return -ENODEV;
3219
3220         fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3221                                 ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO]));
3222         if (!(fifo & BNXT_PTP_RX_FIFO_PENDING))
3223                 return -EAGAIN;
3224
3225         port_id = pf->port_id;
3226         rte_write32(1 << port_id, (uint8_t *)bp->bar0 +
3227                ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO_ADV]);
3228
3229         fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3230                                    ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO]));
3231         if (fifo & BNXT_PTP_RX_FIFO_PENDING) {
3232 /*              bnxt_clr_rx_ts(bp);       TBD  */
3233                 return -EBUSY;
3234         }
3235
3236         *ts = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3237                                 ptp->rx_mapped_regs[BNXT_PTP_RX_TS_L]));
3238         *ts |= (uint64_t)rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3239                                 ptp->rx_mapped_regs[BNXT_PTP_RX_TS_H])) << 32;
3240
3241         return 0;
3242 }
3243
3244 static int
3245 bnxt_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
3246 {
3247         uint64_t ns;
3248         struct bnxt *bp = dev->data->dev_private;
3249         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3250
3251         if (!ptp)
3252                 return 0;
3253
3254         ns = rte_timespec_to_ns(ts);
3255         /* Set the timecounters to a new value. */
3256         ptp->tc.nsec = ns;
3257
3258         return 0;
3259 }
3260
3261 static int
3262 bnxt_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
3263 {
3264         struct bnxt *bp = dev->data->dev_private;
3265         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3266         uint64_t ns, systime_cycles = 0;
3267         int rc = 0;
3268
3269         if (!ptp)
3270                 return 0;
3271
3272         if (BNXT_CHIP_P5(bp))
3273                 rc = bnxt_hwrm_port_ts_query(bp, BNXT_PTP_FLAGS_CURRENT_TIME,
3274                                              &systime_cycles);
3275         else
3276                 systime_cycles = bnxt_cc_read(bp);
3277
3278         ns = rte_timecounter_update(&ptp->tc, systime_cycles);
3279         *ts = rte_ns_to_timespec(ns);
3280
3281         return rc;
3282 }
3283 static int
3284 bnxt_timesync_enable(struct rte_eth_dev *dev)
3285 {
3286         struct bnxt *bp = dev->data->dev_private;
3287         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3288         uint32_t shift = 0;
3289         int rc;
3290
3291         if (!ptp)
3292                 return 0;
3293
3294         ptp->rx_filter = 1;
3295         ptp->tx_tstamp_en = 1;
3296         ptp->rxctl = BNXT_PTP_MSG_EVENTS;
3297
3298         rc = bnxt_hwrm_ptp_cfg(bp);
3299         if (rc)
3300                 return rc;
3301
3302         memset(&ptp->tc, 0, sizeof(struct rte_timecounter));
3303         memset(&ptp->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
3304         memset(&ptp->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
3305
3306         ptp->tc.cc_mask = BNXT_CYCLECOUNTER_MASK;
3307         ptp->tc.cc_shift = shift;
3308         ptp->tc.nsec_mask = (1ULL << shift) - 1;
3309
3310         ptp->rx_tstamp_tc.cc_mask = BNXT_CYCLECOUNTER_MASK;
3311         ptp->rx_tstamp_tc.cc_shift = shift;
3312         ptp->rx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
3313
3314         ptp->tx_tstamp_tc.cc_mask = BNXT_CYCLECOUNTER_MASK;
3315         ptp->tx_tstamp_tc.cc_shift = shift;
3316         ptp->tx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
3317
3318         if (!BNXT_CHIP_P5(bp))
3319                 bnxt_map_ptp_regs(bp);
3320
3321         return 0;
3322 }
3323
3324 static int
3325 bnxt_timesync_disable(struct rte_eth_dev *dev)
3326 {
3327         struct bnxt *bp = dev->data->dev_private;
3328         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3329
3330         if (!ptp)
3331                 return 0;
3332
3333         ptp->rx_filter = 0;
3334         ptp->tx_tstamp_en = 0;
3335         ptp->rxctl = 0;
3336
3337         bnxt_hwrm_ptp_cfg(bp);
3338
3339         if (!BNXT_CHIP_P5(bp))
3340                 bnxt_unmap_ptp_regs(bp);
3341
3342         return 0;
3343 }
3344
3345 static int
3346 bnxt_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
3347                                  struct timespec *timestamp,
3348                                  uint32_t flags __rte_unused)
3349 {
3350         struct bnxt *bp = dev->data->dev_private;
3351         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3352         uint64_t rx_tstamp_cycles = 0;
3353         uint64_t ns;
3354
3355         if (!ptp)
3356                 return 0;
3357
3358         if (BNXT_CHIP_P5(bp))
3359                 rx_tstamp_cycles = ptp->rx_timestamp;
3360         else
3361                 bnxt_get_rx_ts(bp, &rx_tstamp_cycles);
3362
3363         ns = rte_timecounter_update(&ptp->rx_tstamp_tc, rx_tstamp_cycles);
3364         *timestamp = rte_ns_to_timespec(ns);
3365         return  0;
3366 }
3367
3368 static int
3369 bnxt_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
3370                                  struct timespec *timestamp)
3371 {
3372         struct bnxt *bp = dev->data->dev_private;
3373         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3374         uint64_t tx_tstamp_cycles = 0;
3375         uint64_t ns;
3376         int rc = 0;
3377
3378         if (!ptp)
3379                 return 0;
3380
3381         if (BNXT_CHIP_P5(bp))
3382                 rc = bnxt_hwrm_port_ts_query(bp, BNXT_PTP_FLAGS_PATH_TX,
3383                                              &tx_tstamp_cycles);
3384         else
3385                 rc = bnxt_get_tx_ts(bp, &tx_tstamp_cycles);
3386
3387         ns = rte_timecounter_update(&ptp->tx_tstamp_tc, tx_tstamp_cycles);
3388         *timestamp = rte_ns_to_timespec(ns);
3389
3390         return rc;
3391 }
3392
3393 static int
3394 bnxt_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
3395 {
3396         struct bnxt *bp = dev->data->dev_private;
3397         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3398
3399         if (!ptp)
3400                 return 0;
3401
3402         ptp->tc.nsec += delta;
3403
3404         return 0;
3405 }
3406
3407 static int
3408 bnxt_get_eeprom_length_op(struct rte_eth_dev *dev)
3409 {
3410         struct bnxt *bp = dev->data->dev_private;
3411         int rc;
3412         uint32_t dir_entries;
3413         uint32_t entry_length;
3414
3415         rc = is_bnxt_in_error(bp);
3416         if (rc)
3417                 return rc;
3418
3419         PMD_DRV_LOG(INFO, PCI_PRI_FMT "\n",
3420                     bp->pdev->addr.domain, bp->pdev->addr.bus,
3421                     bp->pdev->addr.devid, bp->pdev->addr.function);
3422
3423         rc = bnxt_hwrm_nvm_get_dir_info(bp, &dir_entries, &entry_length);
3424         if (rc != 0)
3425                 return rc;
3426
3427         return dir_entries * entry_length;
3428 }
3429
3430 static int
3431 bnxt_get_eeprom_op(struct rte_eth_dev *dev,
3432                 struct rte_dev_eeprom_info *in_eeprom)
3433 {
3434         struct bnxt *bp = dev->data->dev_private;
3435         uint32_t index;
3436         uint32_t offset;
3437         int rc;
3438
3439         rc = is_bnxt_in_error(bp);
3440         if (rc)
3441                 return rc;
3442
3443         PMD_DRV_LOG(INFO, PCI_PRI_FMT " in_eeprom->offset = %d len = %d\n",
3444                     bp->pdev->addr.domain, bp->pdev->addr.bus,
3445                     bp->pdev->addr.devid, bp->pdev->addr.function,
3446                     in_eeprom->offset, in_eeprom->length);
3447
3448         if (in_eeprom->offset == 0) /* special offset value to get directory */
3449                 return bnxt_get_nvram_directory(bp, in_eeprom->length,
3450                                                 in_eeprom->data);
3451
3452         index = in_eeprom->offset >> 24;
3453         offset = in_eeprom->offset & 0xffffff;
3454
3455         if (index != 0)
3456                 return bnxt_hwrm_get_nvram_item(bp, index - 1, offset,
3457                                            in_eeprom->length, in_eeprom->data);
3458
3459         return 0;
3460 }
3461
3462 static bool bnxt_dir_type_is_ape_bin_format(uint16_t dir_type)
3463 {
3464         switch (dir_type) {
3465         case BNX_DIR_TYPE_CHIMP_PATCH:
3466         case BNX_DIR_TYPE_BOOTCODE:
3467         case BNX_DIR_TYPE_BOOTCODE_2:
3468         case BNX_DIR_TYPE_APE_FW:
3469         case BNX_DIR_TYPE_APE_PATCH:
3470         case BNX_DIR_TYPE_KONG_FW:
3471         case BNX_DIR_TYPE_KONG_PATCH:
3472         case BNX_DIR_TYPE_BONO_FW:
3473         case BNX_DIR_TYPE_BONO_PATCH:
3474                 /* FALLTHROUGH */
3475                 return true;
3476         }
3477
3478         return false;
3479 }
3480
3481 static bool bnxt_dir_type_is_other_exec_format(uint16_t dir_type)
3482 {
3483         switch (dir_type) {
3484         case BNX_DIR_TYPE_AVS:
3485         case BNX_DIR_TYPE_EXP_ROM_MBA:
3486         case BNX_DIR_TYPE_PCIE:
3487         case BNX_DIR_TYPE_TSCF_UCODE:
3488         case BNX_DIR_TYPE_EXT_PHY:
3489         case BNX_DIR_TYPE_CCM:
3490         case BNX_DIR_TYPE_ISCSI_BOOT:
3491         case BNX_DIR_TYPE_ISCSI_BOOT_IPV6:
3492         case BNX_DIR_TYPE_ISCSI_BOOT_IPV4N6:
3493                 /* FALLTHROUGH */
3494                 return true;
3495         }
3496
3497         return false;
3498 }
3499
3500 static bool bnxt_dir_type_is_executable(uint16_t dir_type)
3501 {
3502         return bnxt_dir_type_is_ape_bin_format(dir_type) ||
3503                 bnxt_dir_type_is_other_exec_format(dir_type);
3504 }
3505
3506 static int
3507 bnxt_set_eeprom_op(struct rte_eth_dev *dev,
3508                 struct rte_dev_eeprom_info *in_eeprom)
3509 {
3510         struct bnxt *bp = dev->data->dev_private;
3511         uint8_t index, dir_op;
3512         uint16_t type, ext, ordinal, attr;
3513         int rc;
3514
3515         rc = is_bnxt_in_error(bp);
3516         if (rc)
3517                 return rc;
3518
3519         PMD_DRV_LOG(INFO, PCI_PRI_FMT " in_eeprom->offset = %d len = %d\n",
3520                     bp->pdev->addr.domain, bp->pdev->addr.bus,
3521                     bp->pdev->addr.devid, bp->pdev->addr.function,
3522                     in_eeprom->offset, in_eeprom->length);
3523
3524         if (!BNXT_PF(bp)) {
3525                 PMD_DRV_LOG(ERR, "NVM write not supported from a VF\n");
3526                 return -EINVAL;
3527         }
3528
3529         type = in_eeprom->magic >> 16;
3530
3531         if (type == 0xffff) { /* special value for directory operations */
3532                 index = in_eeprom->magic & 0xff;
3533                 dir_op = in_eeprom->magic >> 8;
3534                 if (index == 0)
3535                         return -EINVAL;
3536                 switch (dir_op) {
3537                 case 0x0e: /* erase */
3538                         if (in_eeprom->offset != ~in_eeprom->magic)
3539                                 return -EINVAL;
3540                         return bnxt_hwrm_erase_nvram_directory(bp, index - 1);
3541                 default:
3542                         return -EINVAL;
3543                 }
3544         }
3545
3546         /* Create or re-write an NVM item: */
3547         if (bnxt_dir_type_is_executable(type) == true)
3548                 return -EOPNOTSUPP;
3549         ext = in_eeprom->magic & 0xffff;
3550         ordinal = in_eeprom->offset >> 16;
3551         attr = in_eeprom->offset & 0xffff;
3552
3553         return bnxt_hwrm_flash_nvram(bp, type, ordinal, ext, attr,
3554                                      in_eeprom->data, in_eeprom->length);
3555 }
3556
3557 /*
3558  * Initialization
3559  */
3560
3561 static const struct eth_dev_ops bnxt_dev_ops = {
3562         .dev_infos_get = bnxt_dev_info_get_op,
3563         .dev_close = bnxt_dev_close_op,
3564         .dev_configure = bnxt_dev_configure_op,
3565         .dev_start = bnxt_dev_start_op,
3566         .dev_stop = bnxt_dev_stop_op,
3567         .dev_set_link_up = bnxt_dev_set_link_up_op,
3568         .dev_set_link_down = bnxt_dev_set_link_down_op,
3569         .stats_get = bnxt_stats_get_op,
3570         .stats_reset = bnxt_stats_reset_op,
3571         .rx_queue_setup = bnxt_rx_queue_setup_op,
3572         .rx_queue_release = bnxt_rx_queue_release_op,
3573         .tx_queue_setup = bnxt_tx_queue_setup_op,
3574         .tx_queue_release = bnxt_tx_queue_release_op,
3575         .rx_queue_intr_enable = bnxt_rx_queue_intr_enable_op,
3576         .rx_queue_intr_disable = bnxt_rx_queue_intr_disable_op,
3577         .reta_update = bnxt_reta_update_op,
3578         .reta_query = bnxt_reta_query_op,
3579         .rss_hash_update = bnxt_rss_hash_update_op,
3580         .rss_hash_conf_get = bnxt_rss_hash_conf_get_op,
3581         .link_update = bnxt_link_update_op,
3582         .promiscuous_enable = bnxt_promiscuous_enable_op,
3583         .promiscuous_disable = bnxt_promiscuous_disable_op,
3584         .allmulticast_enable = bnxt_allmulticast_enable_op,
3585         .allmulticast_disable = bnxt_allmulticast_disable_op,
3586         .mac_addr_add = bnxt_mac_addr_add_op,
3587         .mac_addr_remove = bnxt_mac_addr_remove_op,
3588         .flow_ctrl_get = bnxt_flow_ctrl_get_op,
3589         .flow_ctrl_set = bnxt_flow_ctrl_set_op,
3590         .udp_tunnel_port_add  = bnxt_udp_tunnel_port_add_op,
3591         .udp_tunnel_port_del  = bnxt_udp_tunnel_port_del_op,
3592         .vlan_filter_set = bnxt_vlan_filter_set_op,
3593         .vlan_offload_set = bnxt_vlan_offload_set_op,
3594         .vlan_tpid_set = bnxt_vlan_tpid_set_op,
3595         .vlan_pvid_set = bnxt_vlan_pvid_set_op,
3596         .mtu_set = bnxt_mtu_set_op,
3597         .mac_addr_set = bnxt_set_default_mac_addr_op,
3598         .xstats_get = bnxt_dev_xstats_get_op,
3599         .xstats_get_names = bnxt_dev_xstats_get_names_op,
3600         .xstats_reset = bnxt_dev_xstats_reset_op,
3601         .fw_version_get = bnxt_fw_version_get,
3602         .set_mc_addr_list = bnxt_dev_set_mc_addr_list_op,
3603         .rxq_info_get = bnxt_rxq_info_get_op,
3604         .txq_info_get = bnxt_txq_info_get_op,
3605         .rx_burst_mode_get = bnxt_rx_burst_mode_get,
3606         .tx_burst_mode_get = bnxt_tx_burst_mode_get,
3607         .dev_led_on = bnxt_dev_led_on_op,
3608         .dev_led_off = bnxt_dev_led_off_op,
3609         .rx_queue_start = bnxt_rx_queue_start,
3610         .rx_queue_stop = bnxt_rx_queue_stop,
3611         .tx_queue_start = bnxt_tx_queue_start,
3612         .tx_queue_stop = bnxt_tx_queue_stop,
3613         .filter_ctrl = bnxt_filter_ctrl_op,
3614         .dev_supported_ptypes_get = bnxt_dev_supported_ptypes_get_op,
3615         .get_eeprom_length    = bnxt_get_eeprom_length_op,
3616         .get_eeprom           = bnxt_get_eeprom_op,
3617         .set_eeprom           = bnxt_set_eeprom_op,
3618         .timesync_enable      = bnxt_timesync_enable,
3619         .timesync_disable     = bnxt_timesync_disable,
3620         .timesync_read_time   = bnxt_timesync_read_time,
3621         .timesync_write_time   = bnxt_timesync_write_time,
3622         .timesync_adjust_time = bnxt_timesync_adjust_time,
3623         .timesync_read_rx_timestamp = bnxt_timesync_read_rx_timestamp,
3624         .timesync_read_tx_timestamp = bnxt_timesync_read_tx_timestamp,
3625 };
3626
3627 static uint32_t bnxt_map_reset_regs(struct bnxt *bp, uint32_t reg)
3628 {
3629         uint32_t offset;
3630
3631         /* Only pre-map the reset GRC registers using window 3 */
3632         rte_write32(reg & 0xfffff000, (uint8_t *)bp->bar0 +
3633                     BNXT_GRCPF_REG_WINDOW_BASE_OUT + 8);
3634
3635         offset = BNXT_GRCP_WINDOW_3_BASE + (reg & 0xffc);
3636
3637         return offset;
3638 }
3639
3640 int bnxt_map_fw_health_status_regs(struct bnxt *bp)
3641 {
3642         struct bnxt_error_recovery_info *info = bp->recovery_info;
3643         uint32_t reg_base = 0xffffffff;
3644         int i;
3645
3646         /* Only pre-map the monitoring GRC registers using window 2 */
3647         for (i = 0; i < BNXT_FW_STATUS_REG_CNT; i++) {
3648                 uint32_t reg = info->status_regs[i];
3649
3650                 if (BNXT_FW_STATUS_REG_TYPE(reg) != BNXT_FW_STATUS_REG_TYPE_GRC)
3651                         continue;
3652
3653                 if (reg_base == 0xffffffff)
3654                         reg_base = reg & 0xfffff000;
3655                 if ((reg & 0xfffff000) != reg_base)
3656                         return -ERANGE;
3657
3658                 /* Use mask 0xffc as the Lower 2 bits indicates
3659                  * address space location
3660                  */
3661                 info->mapped_status_regs[i] = BNXT_GRCP_WINDOW_2_BASE +
3662                                                 (reg & 0xffc);
3663         }
3664
3665         if (reg_base == 0xffffffff)
3666                 return 0;
3667
3668         rte_write32(reg_base, (uint8_t *)bp->bar0 +
3669                     BNXT_GRCPF_REG_WINDOW_BASE_OUT + 4);
3670
3671         return 0;
3672 }
3673
3674 static void bnxt_write_fw_reset_reg(struct bnxt *bp, uint32_t index)
3675 {
3676         struct bnxt_error_recovery_info *info = bp->recovery_info;
3677         uint32_t delay = info->delay_after_reset[index];
3678         uint32_t val = info->reset_reg_val[index];
3679         uint32_t reg = info->reset_reg[index];
3680         uint32_t type, offset;
3681
3682         type = BNXT_FW_STATUS_REG_TYPE(reg);
3683         offset = BNXT_FW_STATUS_REG_OFF(reg);
3684
3685         switch (type) {
3686         case BNXT_FW_STATUS_REG_TYPE_CFG:
3687                 rte_pci_write_config(bp->pdev, &val, sizeof(val), offset);
3688                 break;
3689         case BNXT_FW_STATUS_REG_TYPE_GRC:
3690                 offset = bnxt_map_reset_regs(bp, offset);
3691                 rte_write32(val, (uint8_t *)bp->bar0 + offset);
3692                 break;
3693         case BNXT_FW_STATUS_REG_TYPE_BAR0:
3694                 rte_write32(val, (uint8_t *)bp->bar0 + offset);
3695                 break;
3696         }
3697         /* wait on a specific interval of time until core reset is complete */
3698         if (delay)
3699                 rte_delay_ms(delay);
3700 }
3701
3702 static void bnxt_dev_cleanup(struct bnxt *bp)
3703 {
3704         bp->eth_dev->data->dev_link.link_status = 0;
3705         bp->link_info->link_up = 0;
3706         if (bp->eth_dev->data->dev_started)
3707                 bnxt_dev_stop(bp->eth_dev);
3708
3709         bnxt_uninit_resources(bp, true);
3710 }
3711
3712 static int bnxt_restore_vlan_filters(struct bnxt *bp)
3713 {
3714         struct rte_eth_dev *dev = bp->eth_dev;
3715         struct rte_vlan_filter_conf *vfc;
3716         int vidx, vbit, rc;
3717         uint16_t vlan_id;
3718
3719         for (vlan_id = 1; vlan_id <= RTE_ETHER_MAX_VLAN_ID; vlan_id++) {
3720                 vfc = &dev->data->vlan_filter_conf;
3721                 vidx = vlan_id / 64;
3722                 vbit = vlan_id % 64;
3723
3724                 /* Each bit corresponds to a VLAN id */
3725                 if (vfc->ids[vidx] & (UINT64_C(1) << vbit)) {
3726                         rc = bnxt_add_vlan_filter(bp, vlan_id);
3727                         if (rc)
3728                                 return rc;
3729                 }
3730         }
3731
3732         return 0;
3733 }
3734
3735 static int bnxt_restore_mac_filters(struct bnxt *bp)
3736 {
3737         struct rte_eth_dev *dev = bp->eth_dev;
3738         struct rte_eth_dev_info dev_info;
3739         struct rte_ether_addr *addr;
3740         uint64_t pool_mask;
3741         uint32_t pool = 0;
3742         uint16_t i;
3743         int rc;
3744
3745         if (BNXT_VF(bp) && !BNXT_VF_IS_TRUSTED(bp))
3746                 return 0;
3747
3748         rc = bnxt_dev_info_get_op(dev, &dev_info);
3749         if (rc)
3750                 return rc;
3751
3752         /* replay MAC address configuration */
3753         for (i = 1; i < dev_info.max_mac_addrs; i++) {
3754                 addr = &dev->data->mac_addrs[i];
3755
3756                 /* skip zero address */
3757                 if (rte_is_zero_ether_addr(addr))
3758                         continue;
3759
3760                 pool = 0;
3761                 pool_mask = dev->data->mac_pool_sel[i];
3762
3763                 do {
3764                         if (pool_mask & 1ULL) {
3765                                 rc = bnxt_mac_addr_add_op(dev, addr, i, pool);
3766                                 if (rc)
3767                                         return rc;
3768                         }
3769                         pool_mask >>= 1;
3770                         pool++;
3771                 } while (pool_mask);
3772         }
3773
3774         return 0;
3775 }
3776
3777 static int bnxt_restore_filters(struct bnxt *bp)
3778 {
3779         struct rte_eth_dev *dev = bp->eth_dev;
3780         int ret = 0;
3781
3782         if (dev->data->all_multicast) {
3783                 ret = bnxt_allmulticast_enable_op(dev);
3784                 if (ret)
3785                         return ret;
3786         }
3787         if (dev->data->promiscuous) {
3788                 ret = bnxt_promiscuous_enable_op(dev);
3789                 if (ret)
3790                         return ret;
3791         }
3792
3793         ret = bnxt_restore_mac_filters(bp);
3794         if (ret)
3795                 return ret;
3796
3797         ret = bnxt_restore_vlan_filters(bp);
3798         /* TODO restore other filters as well */
3799         return ret;
3800 }
3801
3802 static void bnxt_dev_recover(void *arg)
3803 {
3804         struct bnxt *bp = arg;
3805         int timeout = bp->fw_reset_max_msecs;
3806         int rc = 0;
3807
3808         pthread_mutex_lock(&bp->err_recovery_lock);
3809         /* Clear Error flag so that device re-init should happen */
3810         bp->flags &= ~BNXT_FLAG_FATAL_ERROR;
3811
3812         do {
3813                 rc = bnxt_hwrm_ver_get(bp, SHORT_HWRM_CMD_TIMEOUT);
3814                 if (rc == 0)
3815                         break;
3816                 rte_delay_ms(BNXT_FW_READY_WAIT_INTERVAL);
3817                 timeout -= BNXT_FW_READY_WAIT_INTERVAL;
3818         } while (rc && timeout);
3819
3820         if (rc) {
3821                 PMD_DRV_LOG(ERR, "FW is not Ready after reset\n");
3822                 goto err;
3823         }
3824
3825         rc = bnxt_init_resources(bp, true);
3826         if (rc) {
3827                 PMD_DRV_LOG(ERR,
3828                             "Failed to initialize resources after reset\n");
3829                 goto err;
3830         }
3831         /* clear reset flag as the device is initialized now */
3832         bp->flags &= ~BNXT_FLAG_FW_RESET;
3833
3834         rc = bnxt_dev_start_op(bp->eth_dev);
3835         if (rc) {
3836                 PMD_DRV_LOG(ERR, "Failed to start port after reset\n");
3837                 goto err_start;
3838         }
3839
3840         rc = bnxt_restore_filters(bp);
3841         if (rc)
3842                 goto err_start;
3843
3844         PMD_DRV_LOG(INFO, "Recovered from FW reset\n");
3845         pthread_mutex_unlock(&bp->err_recovery_lock);
3846
3847         return;
3848 err_start:
3849         bnxt_dev_stop(bp->eth_dev);
3850 err:
3851         bp->flags |= BNXT_FLAG_FATAL_ERROR;
3852         bnxt_uninit_resources(bp, false);
3853         pthread_mutex_unlock(&bp->err_recovery_lock);
3854         PMD_DRV_LOG(ERR, "Failed to recover from FW reset\n");
3855 }
3856
3857 void bnxt_dev_reset_and_resume(void *arg)
3858 {
3859         struct bnxt *bp = arg;
3860         int rc;
3861
3862         bnxt_dev_cleanup(bp);
3863
3864         bnxt_wait_for_device_shutdown(bp);
3865
3866         rc = rte_eal_alarm_set(US_PER_MS * bp->fw_reset_min_msecs,
3867                                bnxt_dev_recover, (void *)bp);
3868         if (rc)
3869                 PMD_DRV_LOG(ERR, "Error setting recovery alarm");
3870 }
3871
3872 uint32_t bnxt_read_fw_status_reg(struct bnxt *bp, uint32_t index)
3873 {
3874         struct bnxt_error_recovery_info *info = bp->recovery_info;
3875         uint32_t reg = info->status_regs[index];
3876         uint32_t type, offset, val = 0;
3877
3878         type = BNXT_FW_STATUS_REG_TYPE(reg);
3879         offset = BNXT_FW_STATUS_REG_OFF(reg);
3880
3881         switch (type) {
3882         case BNXT_FW_STATUS_REG_TYPE_CFG:
3883                 rte_pci_read_config(bp->pdev, &val, sizeof(val), offset);
3884                 break;
3885         case BNXT_FW_STATUS_REG_TYPE_GRC:
3886                 offset = info->mapped_status_regs[index];
3887                 /* FALLTHROUGH */
3888         case BNXT_FW_STATUS_REG_TYPE_BAR0:
3889                 val = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3890                                        offset));
3891                 break;
3892         }
3893
3894         return val;
3895 }
3896
3897 static int bnxt_fw_reset_all(struct bnxt *bp)
3898 {
3899         struct bnxt_error_recovery_info *info = bp->recovery_info;
3900         uint32_t i;
3901         int rc = 0;
3902
3903         if (info->flags & BNXT_FLAG_ERROR_RECOVERY_HOST) {
3904                 /* Reset through master function driver */
3905                 for (i = 0; i < info->reg_array_cnt; i++)
3906                         bnxt_write_fw_reset_reg(bp, i);
3907                 /* Wait for time specified by FW after triggering reset */
3908                 rte_delay_ms(info->master_func_wait_period_after_reset);
3909         } else if (info->flags & BNXT_FLAG_ERROR_RECOVERY_CO_CPU) {
3910                 /* Reset with the help of Kong processor */
3911                 rc = bnxt_hwrm_fw_reset(bp);
3912                 if (rc)
3913                         PMD_DRV_LOG(ERR, "Failed to reset FW\n");
3914         }
3915
3916         return rc;
3917 }
3918
3919 static void bnxt_fw_reset_cb(void *arg)
3920 {
3921         struct bnxt *bp = arg;
3922         struct bnxt_error_recovery_info *info = bp->recovery_info;
3923         int rc = 0;
3924
3925         /* Only Master function can do FW reset */
3926         if (bnxt_is_master_func(bp) &&
3927             bnxt_is_recovery_enabled(bp)) {
3928                 rc = bnxt_fw_reset_all(bp);
3929                 if (rc) {
3930                         PMD_DRV_LOG(ERR, "Adapter recovery failed\n");
3931                         return;
3932                 }
3933         }
3934
3935         /* if recovery method is ERROR_RECOVERY_CO_CPU, KONG will send
3936          * EXCEPTION_FATAL_ASYNC event to all the functions
3937          * (including MASTER FUNC). After receiving this Async, all the active
3938          * drivers should treat this case as FW initiated recovery
3939          */
3940         if (info->flags & BNXT_FLAG_ERROR_RECOVERY_HOST) {
3941                 bp->fw_reset_min_msecs = BNXT_MIN_FW_READY_TIMEOUT;
3942                 bp->fw_reset_max_msecs = BNXT_MAX_FW_RESET_TIMEOUT;
3943
3944                 /* To recover from error */
3945                 rte_eal_alarm_set(US_PER_MS, bnxt_dev_reset_and_resume,
3946                                   (void *)bp);
3947         }
3948 }
3949
3950 /* Driver should poll FW heartbeat, reset_counter with the frequency
3951  * advertised by FW in HWRM_ERROR_RECOVERY_QCFG.
3952  * When the driver detects heartbeat stop or change in reset_counter,
3953  * it has to trigger a reset to recover from the error condition.
3954  * A “master PF” is the function who will have the privilege to
3955  * initiate the chimp reset. The master PF will be elected by the
3956  * firmware and will be notified through async message.
3957  */
3958 static void bnxt_check_fw_health(void *arg)
3959 {
3960         struct bnxt *bp = arg;
3961         struct bnxt_error_recovery_info *info = bp->recovery_info;
3962         uint32_t val = 0, wait_msec;
3963
3964         if (!info || !bnxt_is_recovery_enabled(bp) ||
3965             is_bnxt_in_error(bp))
3966                 return;
3967
3968         val = bnxt_read_fw_status_reg(bp, BNXT_FW_HEARTBEAT_CNT_REG);
3969         if (val == info->last_heart_beat)
3970                 goto reset;
3971
3972         info->last_heart_beat = val;
3973
3974         val = bnxt_read_fw_status_reg(bp, BNXT_FW_RECOVERY_CNT_REG);
3975         if (val != info->last_reset_counter)
3976                 goto reset;
3977
3978         info->last_reset_counter = val;
3979
3980         rte_eal_alarm_set(US_PER_MS * info->driver_polling_freq,
3981                           bnxt_check_fw_health, (void *)bp);
3982
3983         return;
3984 reset:
3985         /* Stop DMA to/from device */
3986         bp->flags |= BNXT_FLAG_FATAL_ERROR;
3987         bp->flags |= BNXT_FLAG_FW_RESET;
3988
3989         PMD_DRV_LOG(ERR, "Detected FW dead condition\n");
3990
3991         if (bnxt_is_master_func(bp))
3992                 wait_msec = info->master_func_wait_period;
3993         else
3994                 wait_msec = info->normal_func_wait_period;
3995
3996         rte_eal_alarm_set(US_PER_MS * wait_msec,
3997                           bnxt_fw_reset_cb, (void *)bp);
3998 }
3999
4000 void bnxt_schedule_fw_health_check(struct bnxt *bp)
4001 {
4002         uint32_t polling_freq;
4003
4004         pthread_mutex_lock(&bp->health_check_lock);
4005
4006         if (!bnxt_is_recovery_enabled(bp))
4007                 goto done;
4008
4009         if (bp->flags & BNXT_FLAG_FW_HEALTH_CHECK_SCHEDULED)
4010                 goto done;
4011
4012         polling_freq = bp->recovery_info->driver_polling_freq;
4013
4014         rte_eal_alarm_set(US_PER_MS * polling_freq,
4015                           bnxt_check_fw_health, (void *)bp);
4016         bp->flags |= BNXT_FLAG_FW_HEALTH_CHECK_SCHEDULED;
4017
4018 done:
4019         pthread_mutex_unlock(&bp->health_check_lock);
4020 }
4021
4022 static void bnxt_cancel_fw_health_check(struct bnxt *bp)
4023 {
4024         if (!bnxt_is_recovery_enabled(bp))
4025                 return;
4026
4027         rte_eal_alarm_cancel(bnxt_check_fw_health, (void *)bp);
4028         bp->flags &= ~BNXT_FLAG_FW_HEALTH_CHECK_SCHEDULED;
4029 }
4030
4031 static bool bnxt_vf_pciid(uint16_t device_id)
4032 {
4033         switch (device_id) {
4034         case BROADCOM_DEV_ID_57304_VF:
4035         case BROADCOM_DEV_ID_57406_VF:
4036         case BROADCOM_DEV_ID_5731X_VF:
4037         case BROADCOM_DEV_ID_5741X_VF:
4038         case BROADCOM_DEV_ID_57414_VF:
4039         case BROADCOM_DEV_ID_STRATUS_NIC_VF1:
4040         case BROADCOM_DEV_ID_STRATUS_NIC_VF2:
4041         case BROADCOM_DEV_ID_58802_VF:
4042         case BROADCOM_DEV_ID_57500_VF1:
4043         case BROADCOM_DEV_ID_57500_VF2:
4044         case BROADCOM_DEV_ID_58818_VF:
4045                 /* FALLTHROUGH */
4046                 return true;
4047         default:
4048                 return false;
4049         }
4050 }
4051
4052 /* Phase 5 device */
4053 static bool bnxt_p5_device(uint16_t device_id)
4054 {
4055         switch (device_id) {
4056         case BROADCOM_DEV_ID_57508:
4057         case BROADCOM_DEV_ID_57504:
4058         case BROADCOM_DEV_ID_57502:
4059         case BROADCOM_DEV_ID_57508_MF1:
4060         case BROADCOM_DEV_ID_57504_MF1:
4061         case BROADCOM_DEV_ID_57502_MF1:
4062         case BROADCOM_DEV_ID_57508_MF2:
4063         case BROADCOM_DEV_ID_57504_MF2:
4064         case BROADCOM_DEV_ID_57502_MF2:
4065         case BROADCOM_DEV_ID_57500_VF1:
4066         case BROADCOM_DEV_ID_57500_VF2:
4067         case BROADCOM_DEV_ID_58812:
4068         case BROADCOM_DEV_ID_58814:
4069         case BROADCOM_DEV_ID_58818:
4070         case BROADCOM_DEV_ID_58818_VF:
4071                 /* FALLTHROUGH */
4072                 return true;
4073         default:
4074                 return false;
4075         }
4076 }
4077
4078 bool bnxt_stratus_device(struct bnxt *bp)
4079 {
4080         uint16_t device_id = bp->pdev->id.device_id;
4081
4082         switch (device_id) {
4083         case BROADCOM_DEV_ID_STRATUS_NIC:
4084         case BROADCOM_DEV_ID_STRATUS_NIC_VF1:
4085         case BROADCOM_DEV_ID_STRATUS_NIC_VF2:
4086                 /* FALLTHROUGH */
4087                 return true;
4088         default:
4089                 return false;
4090         }
4091 }
4092
4093 static int bnxt_map_pci_bars(struct rte_eth_dev *eth_dev)
4094 {
4095         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
4096         struct bnxt *bp = eth_dev->data->dev_private;
4097
4098         /* enable device (incl. PCI PM wakeup), and bus-mastering */
4099         bp->bar0 = (void *)pci_dev->mem_resource[0].addr;
4100         bp->doorbell_base = (void *)pci_dev->mem_resource[2].addr;
4101         if (!bp->bar0 || !bp->doorbell_base) {
4102                 PMD_DRV_LOG(ERR, "Unable to access Hardware\n");
4103                 return -ENODEV;
4104         }
4105
4106         bp->eth_dev = eth_dev;
4107         bp->pdev = pci_dev;
4108
4109         return 0;
4110 }
4111
4112 static int bnxt_alloc_ctx_mem_blk(struct bnxt *bp,
4113                                   struct bnxt_ctx_pg_info *ctx_pg,
4114                                   uint32_t mem_size,
4115                                   const char *suffix,
4116                                   uint16_t idx)
4117 {
4118         struct bnxt_ring_mem_info *rmem = &ctx_pg->ring_mem;
4119         const struct rte_memzone *mz = NULL;
4120         char mz_name[RTE_MEMZONE_NAMESIZE];
4121         rte_iova_t mz_phys_addr;
4122         uint64_t valid_bits = 0;
4123         uint32_t sz;
4124         int i;
4125
4126         if (!mem_size)
4127                 return 0;
4128
4129         rmem->nr_pages = RTE_ALIGN_MUL_CEIL(mem_size, BNXT_PAGE_SIZE) /
4130                          BNXT_PAGE_SIZE;
4131         rmem->page_size = BNXT_PAGE_SIZE;
4132         rmem->pg_arr = ctx_pg->ctx_pg_arr;
4133         rmem->dma_arr = ctx_pg->ctx_dma_arr;
4134         rmem->flags = BNXT_RMEM_VALID_PTE_FLAG;
4135
4136         valid_bits = PTU_PTE_VALID;
4137
4138         if (rmem->nr_pages > 1) {
4139                 snprintf(mz_name, RTE_MEMZONE_NAMESIZE,
4140                          "bnxt_ctx_pg_tbl%s_%x_%d",
4141                          suffix, idx, bp->eth_dev->data->port_id);
4142                 mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0;
4143                 mz = rte_memzone_lookup(mz_name);
4144                 if (!mz) {
4145                         mz = rte_memzone_reserve_aligned(mz_name,
4146                                                 rmem->nr_pages * 8,
4147                                                 SOCKET_ID_ANY,
4148                                                 RTE_MEMZONE_2MB |
4149                                                 RTE_MEMZONE_SIZE_HINT_ONLY |
4150                                                 RTE_MEMZONE_IOVA_CONTIG,
4151                                                 BNXT_PAGE_SIZE);
4152                         if (mz == NULL)
4153                                 return -ENOMEM;
4154                 }
4155
4156                 memset(mz->addr, 0, mz->len);
4157                 mz_phys_addr = mz->iova;
4158
4159                 rmem->pg_tbl = mz->addr;
4160                 rmem->pg_tbl_map = mz_phys_addr;
4161                 rmem->pg_tbl_mz = mz;
4162         }
4163
4164         snprintf(mz_name, RTE_MEMZONE_NAMESIZE, "bnxt_ctx_%s_%x_%d",
4165                  suffix, idx, bp->eth_dev->data->port_id);
4166         mz = rte_memzone_lookup(mz_name);
4167         if (!mz) {
4168                 mz = rte_memzone_reserve_aligned(mz_name,
4169                                                  mem_size,
4170                                                  SOCKET_ID_ANY,
4171                                                  RTE_MEMZONE_1GB |
4172                                                  RTE_MEMZONE_SIZE_HINT_ONLY |
4173                                                  RTE_MEMZONE_IOVA_CONTIG,
4174                                                  BNXT_PAGE_SIZE);
4175                 if (mz == NULL)
4176                         return -ENOMEM;
4177         }
4178
4179         memset(mz->addr, 0, mz->len);
4180         mz_phys_addr = mz->iova;
4181
4182         for (sz = 0, i = 0; sz < mem_size; sz += BNXT_PAGE_SIZE, i++) {
4183                 rmem->pg_arr[i] = ((char *)mz->addr) + sz;
4184                 rmem->dma_arr[i] = mz_phys_addr + sz;
4185
4186                 if (rmem->nr_pages > 1) {
4187                         if (i == rmem->nr_pages - 2 &&
4188                             (rmem->flags & BNXT_RMEM_RING_PTE_FLAG))
4189                                 valid_bits |= PTU_PTE_NEXT_TO_LAST;
4190                         else if (i == rmem->nr_pages - 1 &&
4191                                  (rmem->flags & BNXT_RMEM_RING_PTE_FLAG))
4192                                 valid_bits |= PTU_PTE_LAST;
4193
4194                         rmem->pg_tbl[i] = rte_cpu_to_le_64(rmem->dma_arr[i] |
4195                                                            valid_bits);
4196                 }
4197         }
4198
4199         rmem->mz = mz;
4200         if (rmem->vmem_size)
4201                 rmem->vmem = (void **)mz->addr;
4202         rmem->dma_arr[0] = mz_phys_addr;
4203         return 0;
4204 }
4205
4206 static void bnxt_free_ctx_mem(struct bnxt *bp)
4207 {
4208         int i;
4209
4210         if (!bp->ctx || !(bp->ctx->flags & BNXT_CTX_FLAG_INITED))
4211                 return;
4212
4213         bp->ctx->flags &= ~BNXT_CTX_FLAG_INITED;
4214         rte_memzone_free(bp->ctx->qp_mem.ring_mem.mz);
4215         rte_memzone_free(bp->ctx->srq_mem.ring_mem.mz);
4216         rte_memzone_free(bp->ctx->cq_mem.ring_mem.mz);
4217         rte_memzone_free(bp->ctx->vnic_mem.ring_mem.mz);
4218         rte_memzone_free(bp->ctx->stat_mem.ring_mem.mz);
4219         rte_memzone_free(bp->ctx->qp_mem.ring_mem.pg_tbl_mz);
4220         rte_memzone_free(bp->ctx->srq_mem.ring_mem.pg_tbl_mz);
4221         rte_memzone_free(bp->ctx->cq_mem.ring_mem.pg_tbl_mz);
4222         rte_memzone_free(bp->ctx->vnic_mem.ring_mem.pg_tbl_mz);
4223         rte_memzone_free(bp->ctx->stat_mem.ring_mem.pg_tbl_mz);
4224
4225         for (i = 0; i < bp->ctx->tqm_fp_rings_count + 1; i++) {
4226                 if (bp->ctx->tqm_mem[i])
4227                         rte_memzone_free(bp->ctx->tqm_mem[i]->ring_mem.mz);
4228         }
4229
4230         rte_free(bp->ctx);
4231         bp->ctx = NULL;
4232 }
4233
4234 #define bnxt_roundup(x, y)   ((((x) + ((y) - 1)) / (y)) * (y))
4235
4236 #define min_t(type, x, y) ({                    \
4237         type __min1 = (x);                      \
4238         type __min2 = (y);                      \
4239         __min1 < __min2 ? __min1 : __min2; })
4240
4241 #define max_t(type, x, y) ({                    \
4242         type __max1 = (x);                      \
4243         type __max2 = (y);                      \
4244         __max1 > __max2 ? __max1 : __max2; })
4245
4246 #define clamp_t(type, _x, min, max)     min_t(type, max_t(type, _x, min), max)
4247
4248 int bnxt_alloc_ctx_mem(struct bnxt *bp)
4249 {
4250         struct bnxt_ctx_pg_info *ctx_pg;
4251         struct bnxt_ctx_mem_info *ctx;
4252         uint32_t mem_size, ena, entries;
4253         uint32_t entries_sp, min;
4254         int i, rc;
4255
4256         rc = bnxt_hwrm_func_backing_store_qcaps(bp);
4257         if (rc) {
4258                 PMD_DRV_LOG(ERR, "Query context mem capability failed\n");
4259                 return rc;
4260         }
4261         ctx = bp->ctx;
4262         if (!ctx || (ctx->flags & BNXT_CTX_FLAG_INITED))
4263                 return 0;
4264
4265         ctx_pg = &ctx->qp_mem;
4266         ctx_pg->entries = ctx->qp_min_qp1_entries + ctx->qp_max_l2_entries;
4267         if (ctx->qp_entry_size) {
4268                 mem_size = ctx->qp_entry_size * ctx_pg->entries;
4269                 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "qp_mem", 0);
4270                 if (rc)
4271                         return rc;
4272         }
4273
4274         ctx_pg = &ctx->srq_mem;
4275         ctx_pg->entries = ctx->srq_max_l2_entries;
4276         if (ctx->srq_entry_size) {
4277                 mem_size = ctx->srq_entry_size * ctx_pg->entries;
4278                 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "srq_mem", 0);
4279                 if (rc)
4280                         return rc;
4281         }
4282
4283         ctx_pg = &ctx->cq_mem;
4284         ctx_pg->entries = ctx->cq_max_l2_entries;
4285         if (ctx->cq_entry_size) {
4286                 mem_size = ctx->cq_entry_size * ctx_pg->entries;
4287                 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "cq_mem", 0);
4288                 if (rc)
4289                         return rc;
4290         }
4291
4292         ctx_pg = &ctx->vnic_mem;
4293         ctx_pg->entries = ctx->vnic_max_vnic_entries +
4294                 ctx->vnic_max_ring_table_entries;
4295         if (ctx->vnic_entry_size) {
4296                 mem_size = ctx->vnic_entry_size * ctx_pg->entries;
4297                 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "vnic_mem", 0);
4298                 if (rc)
4299                         return rc;
4300         }
4301
4302         ctx_pg = &ctx->stat_mem;
4303         ctx_pg->entries = ctx->stat_max_entries;
4304         if (ctx->stat_entry_size) {
4305                 mem_size = ctx->stat_entry_size * ctx_pg->entries;
4306                 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "stat_mem", 0);
4307                 if (rc)
4308                         return rc;
4309         }
4310
4311         min = ctx->tqm_min_entries_per_ring;
4312
4313         entries_sp = ctx->qp_max_l2_entries +
4314                      ctx->vnic_max_vnic_entries +
4315                      2 * ctx->qp_min_qp1_entries + min;
4316         entries_sp = bnxt_roundup(entries_sp, ctx->tqm_entries_multiple);
4317
4318         entries = ctx->qp_max_l2_entries + ctx->qp_min_qp1_entries;
4319         entries = bnxt_roundup(entries, ctx->tqm_entries_multiple);
4320         entries = clamp_t(uint32_t, entries, min,
4321                           ctx->tqm_max_entries_per_ring);
4322         for (i = 0, ena = 0; i < ctx->tqm_fp_rings_count + 1; i++) {
4323                 ctx_pg = ctx->tqm_mem[i];
4324                 ctx_pg->entries = i ? entries : entries_sp;
4325                 if (ctx->tqm_entry_size) {
4326                         mem_size = ctx->tqm_entry_size * ctx_pg->entries;
4327                         rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "tqm_mem", i);
4328                         if (rc)
4329                                 return rc;
4330                 }
4331                 ena |= HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_SP << i;
4332         }
4333
4334         ena |= FUNC_BACKING_STORE_CFG_INPUT_DFLT_ENABLES;
4335         rc = bnxt_hwrm_func_backing_store_cfg(bp, ena);
4336         if (rc)
4337                 PMD_DRV_LOG(ERR,
4338                             "Failed to configure context mem: rc = %d\n", rc);
4339         else
4340                 ctx->flags |= BNXT_CTX_FLAG_INITED;
4341
4342         return rc;
4343 }
4344
4345 static int bnxt_alloc_stats_mem(struct bnxt *bp)
4346 {
4347         struct rte_pci_device *pci_dev = bp->pdev;
4348         char mz_name[RTE_MEMZONE_NAMESIZE];
4349         const struct rte_memzone *mz = NULL;
4350         uint32_t total_alloc_len;
4351         rte_iova_t mz_phys_addr;
4352
4353         if (pci_dev->id.device_id == BROADCOM_DEV_ID_NS2)
4354                 return 0;
4355
4356         snprintf(mz_name, RTE_MEMZONE_NAMESIZE,
4357                  "bnxt_" PCI_PRI_FMT "-%s", pci_dev->addr.domain,
4358                  pci_dev->addr.bus, pci_dev->addr.devid,
4359                  pci_dev->addr.function, "rx_port_stats");
4360         mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0;
4361         mz = rte_memzone_lookup(mz_name);
4362         total_alloc_len =
4363                 RTE_CACHE_LINE_ROUNDUP(sizeof(struct rx_port_stats) +
4364                                        sizeof(struct rx_port_stats_ext) + 512);
4365         if (!mz) {
4366                 mz = rte_memzone_reserve(mz_name, total_alloc_len,
4367                                          SOCKET_ID_ANY,
4368                                          RTE_MEMZONE_2MB |
4369                                          RTE_MEMZONE_SIZE_HINT_ONLY |
4370                                          RTE_MEMZONE_IOVA_CONTIG);
4371                 if (mz == NULL)
4372                         return -ENOMEM;
4373         }
4374         memset(mz->addr, 0, mz->len);
4375         mz_phys_addr = mz->iova;
4376
4377         bp->rx_mem_zone = (const void *)mz;
4378         bp->hw_rx_port_stats = mz->addr;
4379         bp->hw_rx_port_stats_map = mz_phys_addr;
4380
4381         snprintf(mz_name, RTE_MEMZONE_NAMESIZE,
4382                  "bnxt_" PCI_PRI_FMT "-%s", pci_dev->addr.domain,
4383                  pci_dev->addr.bus, pci_dev->addr.devid,
4384                  pci_dev->addr.function, "tx_port_stats");
4385         mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0;
4386         mz = rte_memzone_lookup(mz_name);
4387         total_alloc_len =
4388                 RTE_CACHE_LINE_ROUNDUP(sizeof(struct tx_port_stats) +
4389                                        sizeof(struct tx_port_stats_ext) + 512);
4390         if (!mz) {
4391                 mz = rte_memzone_reserve(mz_name,
4392                                          total_alloc_len,
4393                                          SOCKET_ID_ANY,
4394                                          RTE_MEMZONE_2MB |
4395                                          RTE_MEMZONE_SIZE_HINT_ONLY |
4396                                          RTE_MEMZONE_IOVA_CONTIG);
4397                 if (mz == NULL)
4398                         return -ENOMEM;
4399         }
4400         memset(mz->addr, 0, mz->len);
4401         mz_phys_addr = mz->iova;
4402
4403         bp->tx_mem_zone = (const void *)mz;
4404         bp->hw_tx_port_stats = mz->addr;
4405         bp->hw_tx_port_stats_map = mz_phys_addr;
4406         bp->flags |= BNXT_FLAG_PORT_STATS;
4407
4408         /* Display extended statistics if FW supports it */
4409         if (bp->hwrm_spec_code < HWRM_SPEC_CODE_1_8_4 ||
4410             bp->hwrm_spec_code == HWRM_SPEC_CODE_1_9_0 ||
4411             !(bp->flags & BNXT_FLAG_EXT_STATS_SUPPORTED))
4412                 return 0;
4413
4414         bp->hw_rx_port_stats_ext = (void *)
4415                 ((uint8_t *)bp->hw_rx_port_stats +
4416                  sizeof(struct rx_port_stats));
4417         bp->hw_rx_port_stats_ext_map = bp->hw_rx_port_stats_map +
4418                 sizeof(struct rx_port_stats);
4419         bp->flags |= BNXT_FLAG_EXT_RX_PORT_STATS;
4420
4421         if (bp->hwrm_spec_code < HWRM_SPEC_CODE_1_9_2 ||
4422             bp->flags & BNXT_FLAG_EXT_STATS_SUPPORTED) {
4423                 bp->hw_tx_port_stats_ext = (void *)
4424                         ((uint8_t *)bp->hw_tx_port_stats +
4425                          sizeof(struct tx_port_stats));
4426                 bp->hw_tx_port_stats_ext_map =
4427                         bp->hw_tx_port_stats_map +
4428                         sizeof(struct tx_port_stats);
4429                 bp->flags |= BNXT_FLAG_EXT_TX_PORT_STATS;
4430         }
4431
4432         return 0;
4433 }
4434
4435 static int bnxt_setup_mac_addr(struct rte_eth_dev *eth_dev)
4436 {
4437         struct bnxt *bp = eth_dev->data->dev_private;
4438         int rc = 0;
4439
4440         eth_dev->data->mac_addrs = rte_zmalloc("bnxt_mac_addr_tbl",
4441                                                RTE_ETHER_ADDR_LEN *
4442                                                bp->max_l2_ctx,
4443                                                0);
4444         if (eth_dev->data->mac_addrs == NULL) {
4445                 PMD_DRV_LOG(ERR, "Failed to alloc MAC addr tbl\n");
4446                 return -ENOMEM;
4447         }
4448
4449         if (!BNXT_HAS_DFLT_MAC_SET(bp)) {
4450                 if (BNXT_PF(bp))
4451                         return -EINVAL;
4452
4453                 /* Generate a random MAC address, if none was assigned by PF */
4454                 PMD_DRV_LOG(INFO, "VF MAC address not assigned by Host PF\n");
4455                 bnxt_eth_hw_addr_random(bp->mac_addr);
4456                 PMD_DRV_LOG(INFO,
4457                             "Assign random MAC:%02X:%02X:%02X:%02X:%02X:%02X\n",
4458                             bp->mac_addr[0], bp->mac_addr[1], bp->mac_addr[2],
4459                             bp->mac_addr[3], bp->mac_addr[4], bp->mac_addr[5]);
4460
4461                 rc = bnxt_hwrm_set_mac(bp);
4462                 if (rc)
4463                         return rc;
4464         }
4465
4466         /* Copy the permanent MAC from the FUNC_QCAPS response */
4467         memcpy(&eth_dev->data->mac_addrs[0], bp->mac_addr, RTE_ETHER_ADDR_LEN);
4468
4469         return rc;
4470 }
4471
4472 static int bnxt_restore_dflt_mac(struct bnxt *bp)
4473 {
4474         int rc = 0;
4475
4476         /* MAC is already configured in FW */
4477         if (BNXT_HAS_DFLT_MAC_SET(bp))
4478                 return 0;
4479
4480         /* Restore the old MAC configured */
4481         rc = bnxt_hwrm_set_mac(bp);
4482         if (rc)
4483                 PMD_DRV_LOG(ERR, "Failed to restore MAC address\n");
4484
4485         return rc;
4486 }
4487
4488 static void bnxt_config_vf_req_fwd(struct bnxt *bp)
4489 {
4490         if (!BNXT_PF(bp))
4491                 return;
4492
4493         memset(bp->pf->vf_req_fwd, 0, sizeof(bp->pf->vf_req_fwd));
4494
4495         if (!(bp->fw_cap & BNXT_FW_CAP_LINK_ADMIN))
4496                 BNXT_HWRM_CMD_TO_FORWARD(HWRM_PORT_PHY_QCFG);
4497         BNXT_HWRM_CMD_TO_FORWARD(HWRM_FUNC_CFG);
4498         BNXT_HWRM_CMD_TO_FORWARD(HWRM_FUNC_VF_CFG);
4499         BNXT_HWRM_CMD_TO_FORWARD(HWRM_CFA_L2_FILTER_ALLOC);
4500         BNXT_HWRM_CMD_TO_FORWARD(HWRM_OEM_CMD);
4501 }
4502
4503 uint16_t
4504 bnxt_get_svif(uint16_t port_id, bool func_svif,
4505               enum bnxt_ulp_intf_type type)
4506 {
4507         struct rte_eth_dev *eth_dev;
4508         struct bnxt *bp;
4509
4510         eth_dev = &rte_eth_devices[port_id];
4511         if (BNXT_ETH_DEV_IS_REPRESENTOR(eth_dev)) {
4512                 struct bnxt_representor *vfr = eth_dev->data->dev_private;
4513                 if (!vfr)
4514                         return 0;
4515
4516                 if (type == BNXT_ULP_INTF_TYPE_VF_REP)
4517                         return vfr->svif;
4518
4519                 eth_dev = vfr->parent_dev;
4520         }
4521
4522         bp = eth_dev->data->dev_private;
4523
4524         return func_svif ? bp->func_svif : bp->port_svif;
4525 }
4526
4527 uint16_t
4528 bnxt_get_vnic_id(uint16_t port, enum bnxt_ulp_intf_type type)
4529 {
4530         struct rte_eth_dev *eth_dev;
4531         struct bnxt_vnic_info *vnic;
4532         struct bnxt *bp;
4533
4534         eth_dev = &rte_eth_devices[port];
4535         if (BNXT_ETH_DEV_IS_REPRESENTOR(eth_dev)) {
4536                 struct bnxt_representor *vfr = eth_dev->data->dev_private;
4537                 if (!vfr)
4538                         return 0;
4539
4540                 if (type == BNXT_ULP_INTF_TYPE_VF_REP)
4541                         return vfr->dflt_vnic_id;
4542
4543                 eth_dev = vfr->parent_dev;
4544         }
4545
4546         bp = eth_dev->data->dev_private;
4547
4548         vnic = BNXT_GET_DEFAULT_VNIC(bp);
4549
4550         return vnic->fw_vnic_id;
4551 }
4552
4553 uint16_t
4554 bnxt_get_fw_func_id(uint16_t port, enum bnxt_ulp_intf_type type)
4555 {
4556         struct rte_eth_dev *eth_dev;
4557         struct bnxt *bp;
4558
4559         eth_dev = &rte_eth_devices[port];
4560         if (BNXT_ETH_DEV_IS_REPRESENTOR(eth_dev)) {
4561                 struct bnxt_representor *vfr = eth_dev->data->dev_private;
4562                 if (!vfr)
4563                         return 0;
4564
4565                 if (type == BNXT_ULP_INTF_TYPE_VF_REP)
4566                         return vfr->fw_fid;
4567
4568                 eth_dev = vfr->parent_dev;
4569         }
4570
4571         bp = eth_dev->data->dev_private;
4572
4573         return bp->fw_fid;
4574 }
4575
4576 enum bnxt_ulp_intf_type
4577 bnxt_get_interface_type(uint16_t port)
4578 {
4579         struct rte_eth_dev *eth_dev;
4580         struct bnxt *bp;
4581
4582         eth_dev = &rte_eth_devices[port];
4583         if (BNXT_ETH_DEV_IS_REPRESENTOR(eth_dev))
4584                 return BNXT_ULP_INTF_TYPE_VF_REP;
4585
4586         bp = eth_dev->data->dev_private;
4587         if (BNXT_PF(bp))
4588                 return BNXT_ULP_INTF_TYPE_PF;
4589         else if (BNXT_VF_IS_TRUSTED(bp))
4590                 return BNXT_ULP_INTF_TYPE_TRUSTED_VF;
4591         else if (BNXT_VF(bp))
4592                 return BNXT_ULP_INTF_TYPE_VF;
4593
4594         return BNXT_ULP_INTF_TYPE_INVALID;
4595 }
4596
4597 uint16_t
4598 bnxt_get_phy_port_id(uint16_t port_id)
4599 {
4600         struct bnxt_representor *vfr;
4601         struct rte_eth_dev *eth_dev;
4602         struct bnxt *bp;
4603
4604         eth_dev = &rte_eth_devices[port_id];
4605         if (BNXT_ETH_DEV_IS_REPRESENTOR(eth_dev)) {
4606                 vfr = eth_dev->data->dev_private;
4607                 if (!vfr)
4608                         return 0;
4609
4610                 eth_dev = vfr->parent_dev;
4611         }
4612
4613         bp = eth_dev->data->dev_private;
4614
4615         return BNXT_PF(bp) ? bp->pf->port_id : bp->parent->port_id;
4616 }
4617
4618 uint16_t
4619 bnxt_get_parif(uint16_t port_id, enum bnxt_ulp_intf_type type)
4620 {
4621         struct rte_eth_dev *eth_dev;
4622         struct bnxt *bp;
4623
4624         eth_dev = &rte_eth_devices[port_id];
4625         if (BNXT_ETH_DEV_IS_REPRESENTOR(eth_dev)) {
4626                 struct bnxt_representor *vfr = eth_dev->data->dev_private;
4627                 if (!vfr)
4628                         return 0;
4629
4630                 if (type == BNXT_ULP_INTF_TYPE_VF_REP)
4631                         return vfr->fw_fid - 1;
4632
4633                 eth_dev = vfr->parent_dev;
4634         }
4635
4636         bp = eth_dev->data->dev_private;
4637
4638         return BNXT_PF(bp) ? bp->fw_fid - 1 : bp->parent->fid - 1;
4639 }
4640
4641 uint16_t
4642 bnxt_get_vport(uint16_t port_id)
4643 {
4644         return (1 << bnxt_get_phy_port_id(port_id));
4645 }
4646
4647 static void bnxt_alloc_error_recovery_info(struct bnxt *bp)
4648 {
4649         struct bnxt_error_recovery_info *info = bp->recovery_info;
4650
4651         if (info) {
4652                 if (!(bp->fw_cap & BNXT_FW_CAP_HCOMM_FW_STATUS))
4653                         memset(info, 0, sizeof(*info));
4654                 return;
4655         }
4656
4657         if (!(bp->fw_cap & BNXT_FW_CAP_ERROR_RECOVERY))
4658                 return;
4659
4660         info = rte_zmalloc("bnxt_hwrm_error_recovery_qcfg",
4661                            sizeof(*info), 0);
4662         if (!info)
4663                 bp->fw_cap &= ~BNXT_FW_CAP_ERROR_RECOVERY;
4664
4665         bp->recovery_info = info;
4666 }
4667
4668 static void bnxt_check_fw_status(struct bnxt *bp)
4669 {
4670         uint32_t fw_status;
4671
4672         if (!(bp->recovery_info &&
4673               (bp->fw_cap & BNXT_FW_CAP_HCOMM_FW_STATUS)))
4674                 return;
4675
4676         fw_status = bnxt_read_fw_status_reg(bp, BNXT_FW_STATUS_REG);
4677         if (fw_status != BNXT_FW_STATUS_HEALTHY)
4678                 PMD_DRV_LOG(ERR, "Firmware not responding, status: %#x\n",
4679                             fw_status);
4680 }
4681
4682 static int bnxt_map_hcomm_fw_status_reg(struct bnxt *bp)
4683 {
4684         struct bnxt_error_recovery_info *info = bp->recovery_info;
4685         uint32_t status_loc;
4686         uint32_t sig_ver;
4687
4688         rte_write32(HCOMM_STATUS_STRUCT_LOC, (uint8_t *)bp->bar0 +
4689                     BNXT_GRCPF_REG_WINDOW_BASE_OUT + 4);
4690         sig_ver = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
4691                                    BNXT_GRCP_WINDOW_2_BASE +
4692                                    offsetof(struct hcomm_status,
4693                                             sig_ver)));
4694         /* If the signature is absent, then FW does not support this feature */
4695         if ((sig_ver & HCOMM_STATUS_SIGNATURE_MASK) !=
4696             HCOMM_STATUS_SIGNATURE_VAL)
4697                 return 0;
4698
4699         if (!info) {
4700                 info = rte_zmalloc("bnxt_hwrm_error_recovery_qcfg",
4701                                    sizeof(*info), 0);
4702                 if (!info)
4703                         return -ENOMEM;
4704                 bp->recovery_info = info;
4705         } else {
4706                 memset(info, 0, sizeof(*info));
4707         }
4708
4709         status_loc = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
4710                                       BNXT_GRCP_WINDOW_2_BASE +
4711                                       offsetof(struct hcomm_status,
4712                                                fw_status_loc)));
4713
4714         /* Only pre-map the FW health status GRC register */
4715         if (BNXT_FW_STATUS_REG_TYPE(status_loc) != BNXT_FW_STATUS_REG_TYPE_GRC)
4716                 return 0;
4717
4718         info->status_regs[BNXT_FW_STATUS_REG] = status_loc;
4719         info->mapped_status_regs[BNXT_FW_STATUS_REG] =
4720                 BNXT_GRCP_WINDOW_2_BASE + (status_loc & BNXT_GRCP_OFFSET_MASK);
4721
4722         rte_write32((status_loc & BNXT_GRCP_BASE_MASK), (uint8_t *)bp->bar0 +
4723                     BNXT_GRCPF_REG_WINDOW_BASE_OUT + 4);
4724
4725         bp->fw_cap |= BNXT_FW_CAP_HCOMM_FW_STATUS;
4726
4727         return 0;
4728 }
4729
4730 /* This function gets the FW version along with the
4731  * capabilities(MAX and current) of the function, vnic,
4732  * error recovery, phy and other chip related info
4733  */
4734 static int bnxt_get_config(struct bnxt *bp)
4735 {
4736         uint16_t mtu;
4737         int rc = 0;
4738
4739         bp->fw_cap = 0;
4740
4741         rc = bnxt_map_hcomm_fw_status_reg(bp);
4742         if (rc)
4743                 return rc;
4744
4745         rc = bnxt_hwrm_ver_get(bp, DFLT_HWRM_CMD_TIMEOUT);
4746         if (rc) {
4747                 bnxt_check_fw_status(bp);
4748                 return rc;
4749         }
4750
4751         rc = bnxt_hwrm_func_reset(bp);
4752         if (rc)
4753                 return -EIO;
4754
4755         rc = bnxt_hwrm_vnic_qcaps(bp);
4756         if (rc)
4757                 return rc;
4758
4759         rc = bnxt_hwrm_queue_qportcfg(bp);
4760         if (rc)
4761                 return rc;
4762
4763         /* Get the MAX capabilities for this function.
4764          * This function also allocates context memory for TQM rings and
4765          * informs the firmware about this allocated backing store memory.
4766          */
4767         rc = bnxt_hwrm_func_qcaps(bp);
4768         if (rc)
4769                 return rc;
4770
4771         rc = bnxt_hwrm_func_qcfg(bp, &mtu);
4772         if (rc)
4773                 return rc;
4774
4775         rc = bnxt_hwrm_cfa_adv_flow_mgmt_qcaps(bp);
4776         if (rc)
4777                 return rc;
4778
4779         bnxt_hwrm_port_mac_qcfg(bp);
4780
4781         bnxt_hwrm_parent_pf_qcfg(bp);
4782
4783         bnxt_hwrm_port_phy_qcaps(bp);
4784
4785         bnxt_alloc_error_recovery_info(bp);
4786         /* Get the adapter error recovery support info */
4787         rc = bnxt_hwrm_error_recovery_qcfg(bp);
4788         if (rc)
4789                 bp->fw_cap &= ~BNXT_FW_CAP_ERROR_RECOVERY;
4790
4791         bnxt_hwrm_port_led_qcaps(bp);
4792
4793         return 0;
4794 }
4795
4796 static int
4797 bnxt_init_locks(struct bnxt *bp)
4798 {
4799         int err;
4800
4801         err = pthread_mutex_init(&bp->flow_lock, NULL);
4802         if (err) {
4803                 PMD_DRV_LOG(ERR, "Unable to initialize flow_lock\n");
4804                 return err;
4805         }
4806
4807         err = pthread_mutex_init(&bp->def_cp_lock, NULL);
4808         if (err) {
4809                 PMD_DRV_LOG(ERR, "Unable to initialize def_cp_lock\n");
4810                 return err;
4811         }
4812
4813         err = pthread_mutex_init(&bp->health_check_lock, NULL);
4814         if (err) {
4815                 PMD_DRV_LOG(ERR, "Unable to initialize health_check_lock\n");
4816                 return err;
4817         }
4818
4819         err = pthread_mutex_init(&bp->err_recovery_lock, NULL);
4820         if (err)
4821                 PMD_DRV_LOG(ERR, "Unable to initialize err_recovery_lock\n");
4822
4823         return err;
4824 }
4825
4826 static int bnxt_init_resources(struct bnxt *bp, bool reconfig_dev)
4827 {
4828         int rc = 0;
4829
4830         rc = bnxt_get_config(bp);
4831         if (rc)
4832                 return rc;
4833
4834         if (!reconfig_dev) {
4835                 rc = bnxt_setup_mac_addr(bp->eth_dev);
4836                 if (rc)
4837                         return rc;
4838         } else {
4839                 rc = bnxt_restore_dflt_mac(bp);
4840                 if (rc)
4841                         return rc;
4842         }
4843
4844         bnxt_config_vf_req_fwd(bp);
4845
4846         rc = bnxt_hwrm_func_driver_register(bp);
4847         if (rc) {
4848                 PMD_DRV_LOG(ERR, "Failed to register driver");
4849                 return -EBUSY;
4850         }
4851
4852         if (BNXT_PF(bp)) {
4853                 if (bp->pdev->max_vfs) {
4854                         rc = bnxt_hwrm_allocate_vfs(bp, bp->pdev->max_vfs);
4855                         if (rc) {
4856                                 PMD_DRV_LOG(ERR, "Failed to allocate VFs\n");
4857                                 return rc;
4858                         }
4859                 } else {
4860                         rc = bnxt_hwrm_allocate_pf_only(bp);
4861                         if (rc) {
4862                                 PMD_DRV_LOG(ERR,
4863                                             "Failed to allocate PF resources");
4864                                 return rc;
4865                         }
4866                 }
4867         }
4868
4869         rc = bnxt_alloc_mem(bp, reconfig_dev);
4870         if (rc)
4871                 return rc;
4872
4873         rc = bnxt_setup_int(bp);
4874         if (rc)
4875                 return rc;
4876
4877         rc = bnxt_request_int(bp);
4878         if (rc)
4879                 return rc;
4880
4881         rc = bnxt_init_ctx_mem(bp);
4882         if (rc) {
4883                 PMD_DRV_LOG(ERR, "Failed to init adv_flow_counters\n");
4884                 return rc;
4885         }
4886
4887         return 0;
4888 }
4889
4890 static int
4891 bnxt_parse_devarg_truflow(__rte_unused const char *key,
4892                           const char *value, void *opaque_arg)
4893 {
4894         struct bnxt *bp = opaque_arg;
4895         unsigned long truflow;
4896         char *end = NULL;
4897
4898         if (!value || !opaque_arg) {
4899                 PMD_DRV_LOG(ERR,
4900                             "Invalid parameter passed to truflow devargs.\n");
4901                 return -EINVAL;
4902         }
4903
4904         truflow = strtoul(value, &end, 10);
4905         if (end == NULL || *end != '\0' ||
4906             (truflow == ULONG_MAX && errno == ERANGE)) {
4907                 PMD_DRV_LOG(ERR,
4908                             "Invalid parameter passed to truflow devargs.\n");
4909                 return -EINVAL;
4910         }
4911
4912         if (BNXT_DEVARG_TRUFLOW_INVALID(truflow)) {
4913                 PMD_DRV_LOG(ERR,
4914                             "Invalid value passed to truflow devargs.\n");
4915                 return -EINVAL;
4916         }
4917
4918         if (truflow) {
4919                 bp->flags |= BNXT_FLAG_TRUFLOW_EN;
4920                 PMD_DRV_LOG(INFO, "Host-based truflow feature enabled.\n");
4921         } else {
4922                 bp->flags &= ~BNXT_FLAG_TRUFLOW_EN;
4923                 PMD_DRV_LOG(INFO, "Host-based truflow feature disabled.\n");
4924         }
4925
4926         return 0;
4927 }
4928
4929 static int
4930 bnxt_parse_devarg_flow_xstat(__rte_unused const char *key,
4931                              const char *value, void *opaque_arg)
4932 {
4933         struct bnxt *bp = opaque_arg;
4934         unsigned long flow_xstat;
4935         char *end = NULL;
4936
4937         if (!value || !opaque_arg) {
4938                 PMD_DRV_LOG(ERR,
4939                             "Invalid parameter passed to flow_xstat devarg.\n");
4940                 return -EINVAL;
4941         }
4942
4943         flow_xstat = strtoul(value, &end, 10);
4944         if (end == NULL || *end != '\0' ||
4945             (flow_xstat == ULONG_MAX && errno == ERANGE)) {
4946                 PMD_DRV_LOG(ERR,
4947                             "Invalid parameter passed to flow_xstat devarg.\n");
4948                 return -EINVAL;
4949         }
4950
4951         if (BNXT_DEVARG_FLOW_XSTAT_INVALID(flow_xstat)) {
4952                 PMD_DRV_LOG(ERR,
4953                             "Invalid value passed to flow_xstat devarg.\n");
4954                 return -EINVAL;
4955         }
4956
4957         bp->flags |= BNXT_FLAG_FLOW_XSTATS_EN;
4958         if (BNXT_FLOW_XSTATS_EN(bp))
4959                 PMD_DRV_LOG(INFO, "flow_xstat feature enabled.\n");
4960
4961         return 0;
4962 }
4963
4964 static int
4965 bnxt_parse_devarg_max_num_kflows(__rte_unused const char *key,
4966                                         const char *value, void *opaque_arg)
4967 {
4968         struct bnxt *bp = opaque_arg;
4969         unsigned long max_num_kflows;
4970         char *end = NULL;
4971
4972         if (!value || !opaque_arg) {
4973                 PMD_DRV_LOG(ERR,
4974                         "Invalid parameter passed to max_num_kflows devarg.\n");
4975                 return -EINVAL;
4976         }
4977
4978         max_num_kflows = strtoul(value, &end, 10);
4979         if (end == NULL || *end != '\0' ||
4980                 (max_num_kflows == ULONG_MAX && errno == ERANGE)) {
4981                 PMD_DRV_LOG(ERR,
4982                         "Invalid parameter passed to max_num_kflows devarg.\n");
4983                 return -EINVAL;
4984         }
4985
4986         if (bnxt_devarg_max_num_kflow_invalid(max_num_kflows)) {
4987                 PMD_DRV_LOG(ERR,
4988                         "Invalid value passed to max_num_kflows devarg.\n");
4989                 return -EINVAL;
4990         }
4991
4992         bp->max_num_kflows = max_num_kflows;
4993         if (bp->max_num_kflows)
4994                 PMD_DRV_LOG(INFO, "max_num_kflows set as %ldK.\n",
4995                                 max_num_kflows);
4996
4997         return 0;
4998 }
4999
5000 static int
5001 bnxt_parse_devarg_rep_is_pf(__rte_unused const char *key,
5002                             const char *value, void *opaque_arg)
5003 {
5004         struct bnxt_representor *vfr_bp = opaque_arg;
5005         unsigned long rep_is_pf;
5006         char *end = NULL;
5007
5008         if (!value || !opaque_arg) {
5009                 PMD_DRV_LOG(ERR,
5010                             "Invalid parameter passed to rep_is_pf devargs.\n");
5011                 return -EINVAL;
5012         }
5013
5014         rep_is_pf = strtoul(value, &end, 10);
5015         if (end == NULL || *end != '\0' ||
5016             (rep_is_pf == ULONG_MAX && errno == ERANGE)) {
5017                 PMD_DRV_LOG(ERR,
5018                             "Invalid parameter passed to rep_is_pf devargs.\n");
5019                 return -EINVAL;
5020         }
5021
5022         if (BNXT_DEVARG_REP_IS_PF_INVALID(rep_is_pf)) {
5023                 PMD_DRV_LOG(ERR,
5024                             "Invalid value passed to rep_is_pf devargs.\n");
5025                 return -EINVAL;
5026         }
5027
5028         vfr_bp->flags |= rep_is_pf;
5029         if (BNXT_REP_PF(vfr_bp))
5030                 PMD_DRV_LOG(INFO, "PF representor\n");
5031         else
5032                 PMD_DRV_LOG(INFO, "VF representor\n");
5033
5034         return 0;
5035 }
5036
5037 static int
5038 bnxt_parse_devarg_rep_based_pf(__rte_unused const char *key,
5039                                const char *value, void *opaque_arg)
5040 {
5041         struct bnxt_representor *vfr_bp = opaque_arg;
5042         unsigned long rep_based_pf;
5043         char *end = NULL;
5044
5045         if (!value || !opaque_arg) {
5046                 PMD_DRV_LOG(ERR,
5047                             "Invalid parameter passed to rep_based_pf "
5048                             "devargs.\n");
5049                 return -EINVAL;
5050         }
5051
5052         rep_based_pf = strtoul(value, &end, 10);
5053         if (end == NULL || *end != '\0' ||
5054             (rep_based_pf == ULONG_MAX && errno == ERANGE)) {
5055                 PMD_DRV_LOG(ERR,
5056                             "Invalid parameter passed to rep_based_pf "
5057                             "devargs.\n");
5058                 return -EINVAL;
5059         }
5060
5061         if (BNXT_DEVARG_REP_BASED_PF_INVALID(rep_based_pf)) {
5062                 PMD_DRV_LOG(ERR,
5063                             "Invalid value passed to rep_based_pf devargs.\n");
5064                 return -EINVAL;
5065         }
5066
5067         vfr_bp->rep_based_pf = rep_based_pf;
5068         vfr_bp->flags |= BNXT_REP_BASED_PF_VALID;
5069
5070         PMD_DRV_LOG(INFO, "rep-based-pf = %d\n", vfr_bp->rep_based_pf);
5071
5072         return 0;
5073 }
5074
5075 static int
5076 bnxt_parse_devarg_rep_q_r2f(__rte_unused const char *key,
5077                             const char *value, void *opaque_arg)
5078 {
5079         struct bnxt_representor *vfr_bp = opaque_arg;
5080         unsigned long rep_q_r2f;
5081         char *end = NULL;
5082
5083         if (!value || !opaque_arg) {
5084                 PMD_DRV_LOG(ERR,
5085                             "Invalid parameter passed to rep_q_r2f "
5086                             "devargs.\n");
5087                 return -EINVAL;
5088         }
5089
5090         rep_q_r2f = strtoul(value, &end, 10);
5091         if (end == NULL || *end != '\0' ||
5092             (rep_q_r2f == ULONG_MAX && errno == ERANGE)) {
5093                 PMD_DRV_LOG(ERR,
5094                             "Invalid parameter passed to rep_q_r2f "
5095                             "devargs.\n");
5096                 return -EINVAL;
5097         }
5098
5099         if (BNXT_DEVARG_REP_Q_R2F_INVALID(rep_q_r2f)) {
5100                 PMD_DRV_LOG(ERR,
5101                             "Invalid value passed to rep_q_r2f devargs.\n");
5102                 return -EINVAL;
5103         }
5104
5105         vfr_bp->rep_q_r2f = rep_q_r2f;
5106         vfr_bp->flags |= BNXT_REP_Q_R2F_VALID;
5107         PMD_DRV_LOG(INFO, "rep-q-r2f = %d\n", vfr_bp->rep_q_r2f);
5108
5109         return 0;
5110 }
5111
5112 static int
5113 bnxt_parse_devarg_rep_q_f2r(__rte_unused const char *key,
5114                             const char *value, void *opaque_arg)
5115 {
5116         struct bnxt_representor *vfr_bp = opaque_arg;
5117         unsigned long rep_q_f2r;
5118         char *end = NULL;
5119
5120         if (!value || !opaque_arg) {
5121                 PMD_DRV_LOG(ERR,
5122                             "Invalid parameter passed to rep_q_f2r "
5123                             "devargs.\n");
5124                 return -EINVAL;
5125         }
5126
5127         rep_q_f2r = strtoul(value, &end, 10);
5128         if (end == NULL || *end != '\0' ||
5129             (rep_q_f2r == ULONG_MAX && errno == ERANGE)) {
5130                 PMD_DRV_LOG(ERR,
5131                             "Invalid parameter passed to rep_q_f2r "
5132                             "devargs.\n");
5133                 return -EINVAL;
5134         }
5135
5136         if (BNXT_DEVARG_REP_Q_F2R_INVALID(rep_q_f2r)) {
5137                 PMD_DRV_LOG(ERR,
5138                             "Invalid value passed to rep_q_f2r devargs.\n");
5139                 return -EINVAL;
5140         }
5141
5142         vfr_bp->rep_q_f2r = rep_q_f2r;
5143         vfr_bp->flags |= BNXT_REP_Q_F2R_VALID;
5144         PMD_DRV_LOG(INFO, "rep-q-f2r = %d\n", vfr_bp->rep_q_f2r);
5145
5146         return 0;
5147 }
5148
5149 static int
5150 bnxt_parse_devarg_rep_fc_r2f(__rte_unused const char *key,
5151                              const char *value, void *opaque_arg)
5152 {
5153         struct bnxt_representor *vfr_bp = opaque_arg;
5154         unsigned long rep_fc_r2f;
5155         char *end = NULL;
5156
5157         if (!value || !opaque_arg) {
5158                 PMD_DRV_LOG(ERR,
5159                             "Invalid parameter passed to rep_fc_r2f "
5160                             "devargs.\n");
5161                 return -EINVAL;
5162         }
5163
5164         rep_fc_r2f = strtoul(value, &end, 10);
5165         if (end == NULL || *end != '\0' ||
5166             (rep_fc_r2f == ULONG_MAX && errno == ERANGE)) {
5167                 PMD_DRV_LOG(ERR,
5168                             "Invalid parameter passed to rep_fc_r2f "
5169                             "devargs.\n");
5170                 return -EINVAL;
5171         }
5172
5173         if (BNXT_DEVARG_REP_FC_R2F_INVALID(rep_fc_r2f)) {
5174                 PMD_DRV_LOG(ERR,
5175                             "Invalid value passed to rep_fc_r2f devargs.\n");
5176                 return -EINVAL;
5177         }
5178
5179         vfr_bp->flags |= BNXT_REP_FC_R2F_VALID;
5180         vfr_bp->rep_fc_r2f = rep_fc_r2f;
5181         PMD_DRV_LOG(INFO, "rep-fc-r2f = %lu\n", rep_fc_r2f);
5182
5183         return 0;
5184 }
5185
5186 static int
5187 bnxt_parse_devarg_rep_fc_f2r(__rte_unused const char *key,
5188                              const char *value, void *opaque_arg)
5189 {
5190         struct bnxt_representor *vfr_bp = opaque_arg;
5191         unsigned long rep_fc_f2r;
5192         char *end = NULL;
5193
5194         if (!value || !opaque_arg) {
5195                 PMD_DRV_LOG(ERR,
5196                             "Invalid parameter passed to rep_fc_f2r "
5197                             "devargs.\n");
5198                 return -EINVAL;
5199         }
5200
5201         rep_fc_f2r = strtoul(value, &end, 10);
5202         if (end == NULL || *end != '\0' ||
5203             (rep_fc_f2r == ULONG_MAX && errno == ERANGE)) {
5204                 PMD_DRV_LOG(ERR,
5205                             "Invalid parameter passed to rep_fc_f2r "
5206                             "devargs.\n");
5207                 return -EINVAL;
5208         }
5209
5210         if (BNXT_DEVARG_REP_FC_F2R_INVALID(rep_fc_f2r)) {
5211                 PMD_DRV_LOG(ERR,
5212                             "Invalid value passed to rep_fc_f2r devargs.\n");
5213                 return -EINVAL;
5214         }
5215
5216         vfr_bp->flags |= BNXT_REP_FC_F2R_VALID;
5217         vfr_bp->rep_fc_f2r = rep_fc_f2r;
5218         PMD_DRV_LOG(INFO, "rep-fc-f2r = %lu\n", rep_fc_f2r);
5219
5220         return 0;
5221 }
5222
5223 static void
5224 bnxt_parse_dev_args(struct bnxt *bp, struct rte_devargs *devargs)
5225 {
5226         struct rte_kvargs *kvlist;
5227
5228         if (devargs == NULL)
5229                 return;
5230
5231         kvlist = rte_kvargs_parse(devargs->args, bnxt_dev_args);
5232         if (kvlist == NULL)
5233                 return;
5234
5235         /*
5236          * Handler for "truflow" devarg.
5237          * Invoked as for ex: "-a 0000:00:0d.0,host-based-truflow=1"
5238          */
5239         rte_kvargs_process(kvlist, BNXT_DEVARG_TRUFLOW,
5240                            bnxt_parse_devarg_truflow, bp);
5241
5242         /*
5243          * Handler for "flow_xstat" devarg.
5244          * Invoked as for ex: "-a 0000:00:0d.0,flow_xstat=1"
5245          */
5246         rte_kvargs_process(kvlist, BNXT_DEVARG_FLOW_XSTAT,
5247                            bnxt_parse_devarg_flow_xstat, bp);
5248
5249         /*
5250          * Handler for "max_num_kflows" devarg.
5251          * Invoked as for ex: "-a 000:00:0d.0,max_num_kflows=32"
5252          */
5253         rte_kvargs_process(kvlist, BNXT_DEVARG_MAX_NUM_KFLOWS,
5254                            bnxt_parse_devarg_max_num_kflows, bp);
5255
5256         rte_kvargs_free(kvlist);
5257 }
5258
5259 static int bnxt_alloc_switch_domain(struct bnxt *bp)
5260 {
5261         int rc = 0;
5262
5263         if (BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp)) {
5264                 rc = rte_eth_switch_domain_alloc(&bp->switch_domain_id);
5265                 if (rc)
5266                         PMD_DRV_LOG(ERR,
5267                                     "Failed to alloc switch domain: %d\n", rc);
5268                 else
5269                         PMD_DRV_LOG(INFO,
5270                                     "Switch domain allocated %d\n",
5271                                     bp->switch_domain_id);
5272         }
5273
5274         return rc;
5275 }
5276
5277 /* Allocate and initialize various fields in bnxt struct that
5278  * need to be allocated/destroyed only once in the lifetime of the driver
5279  */
5280 static int bnxt_drv_init(struct rte_eth_dev *eth_dev)
5281 {
5282         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
5283         struct bnxt *bp = eth_dev->data->dev_private;
5284         int rc = 0;
5285
5286         bp->flags &= ~BNXT_FLAG_RX_VECTOR_PKT_MODE;
5287
5288         if (bnxt_vf_pciid(pci_dev->id.device_id))
5289                 bp->flags |= BNXT_FLAG_VF;
5290
5291         if (bnxt_p5_device(pci_dev->id.device_id))
5292                 bp->flags |= BNXT_FLAG_CHIP_P5;
5293
5294         if (pci_dev->id.device_id == BROADCOM_DEV_ID_58802 ||
5295             pci_dev->id.device_id == BROADCOM_DEV_ID_58804 ||
5296             pci_dev->id.device_id == BROADCOM_DEV_ID_58808 ||
5297             pci_dev->id.device_id == BROADCOM_DEV_ID_58802_VF)
5298                 bp->flags |= BNXT_FLAG_STINGRAY;
5299
5300         if (BNXT_TRUFLOW_EN(bp)) {
5301                 /* extra mbuf field is required to store CFA code from mark */
5302                 static const struct rte_mbuf_dynfield bnxt_cfa_code_dynfield_desc = {
5303                         .name = RTE_PMD_BNXT_CFA_CODE_DYNFIELD_NAME,
5304                         .size = sizeof(bnxt_cfa_code_dynfield_t),
5305                         .align = __alignof__(bnxt_cfa_code_dynfield_t),
5306                 };
5307                 bnxt_cfa_code_dynfield_offset =
5308                         rte_mbuf_dynfield_register(&bnxt_cfa_code_dynfield_desc);
5309                 if (bnxt_cfa_code_dynfield_offset < 0) {
5310                         PMD_DRV_LOG(ERR,
5311                             "Failed to register mbuf field for TruFlow mark\n");
5312                         return -rte_errno;
5313                 }
5314         }
5315
5316         rc = bnxt_map_pci_bars(eth_dev);
5317         if (rc) {
5318                 PMD_DRV_LOG(ERR,
5319                             "Failed to initialize board rc: %x\n", rc);
5320                 return rc;
5321         }
5322
5323         rc = bnxt_alloc_pf_info(bp);
5324         if (rc)
5325                 return rc;
5326
5327         rc = bnxt_alloc_link_info(bp);
5328         if (rc)
5329                 return rc;
5330
5331         rc = bnxt_alloc_parent_info(bp);
5332         if (rc)
5333                 return rc;
5334
5335         rc = bnxt_alloc_hwrm_resources(bp);
5336         if (rc) {
5337                 PMD_DRV_LOG(ERR,
5338                             "Failed to allocate hwrm resource rc: %x\n", rc);
5339                 return rc;
5340         }
5341         rc = bnxt_alloc_leds_info(bp);
5342         if (rc)
5343                 return rc;
5344
5345         rc = bnxt_alloc_cos_queues(bp);
5346         if (rc)
5347                 return rc;
5348
5349         rc = bnxt_init_locks(bp);
5350         if (rc)
5351                 return rc;
5352
5353         rc = bnxt_alloc_switch_domain(bp);
5354         if (rc)
5355                 return rc;
5356
5357         return rc;
5358 }
5359
5360 static int
5361 bnxt_dev_init(struct rte_eth_dev *eth_dev, void *params __rte_unused)
5362 {
5363         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
5364         static int version_printed;
5365         struct bnxt *bp;
5366         int rc;
5367
5368         if (version_printed++ == 0)
5369                 PMD_DRV_LOG(INFO, "%s\n", bnxt_version);
5370
5371         eth_dev->dev_ops = &bnxt_dev_ops;
5372         eth_dev->rx_queue_count = bnxt_rx_queue_count_op;
5373         eth_dev->rx_descriptor_status = bnxt_rx_descriptor_status_op;
5374         eth_dev->tx_descriptor_status = bnxt_tx_descriptor_status_op;
5375         eth_dev->rx_pkt_burst = &bnxt_recv_pkts;
5376         eth_dev->tx_pkt_burst = &bnxt_xmit_pkts;
5377
5378         /*
5379          * For secondary processes, we don't initialise any further
5380          * as primary has already done this work.
5381          */
5382         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
5383                 return 0;
5384
5385         rte_eth_copy_pci_info(eth_dev, pci_dev);
5386         eth_dev->data->dev_flags |= RTE_ETH_DEV_AUTOFILL_QUEUE_XSTATS;
5387
5388         bp = eth_dev->data->dev_private;
5389
5390         /* Parse dev arguments passed on when starting the DPDK application. */
5391         bnxt_parse_dev_args(bp, pci_dev->device.devargs);
5392
5393         rc = bnxt_drv_init(eth_dev);
5394         if (rc)
5395                 goto error_free;
5396
5397         rc = bnxt_init_resources(bp, false);
5398         if (rc)
5399                 goto error_free;
5400
5401         rc = bnxt_alloc_stats_mem(bp);
5402         if (rc)
5403                 goto error_free;
5404
5405         PMD_DRV_LOG(INFO,
5406                     DRV_MODULE_NAME "found at mem %" PRIX64 ", node addr %pM\n",
5407                     pci_dev->mem_resource[0].phys_addr,
5408                     pci_dev->mem_resource[0].addr);
5409
5410         return 0;
5411
5412 error_free:
5413         bnxt_dev_uninit(eth_dev);
5414         return rc;
5415 }
5416
5417
5418 static void bnxt_free_ctx_mem_buf(struct bnxt_ctx_mem_buf_info *ctx)
5419 {
5420         if (!ctx)
5421                 return;
5422
5423         if (ctx->va)
5424                 rte_free(ctx->va);
5425
5426         ctx->va = NULL;
5427         ctx->dma = RTE_BAD_IOVA;
5428         ctx->ctx_id = BNXT_CTX_VAL_INVAL;
5429 }
5430
5431 static void bnxt_unregister_fc_ctx_mem(struct bnxt *bp)
5432 {
5433         bnxt_hwrm_cfa_counter_cfg(bp, BNXT_DIR_RX,
5434                                   CFA_COUNTER_CFG_IN_COUNTER_TYPE_FC,
5435                                   bp->flow_stat->rx_fc_out_tbl.ctx_id,
5436                                   bp->flow_stat->max_fc,
5437                                   false);
5438
5439         bnxt_hwrm_cfa_counter_cfg(bp, BNXT_DIR_TX,
5440                                   CFA_COUNTER_CFG_IN_COUNTER_TYPE_FC,
5441                                   bp->flow_stat->tx_fc_out_tbl.ctx_id,
5442                                   bp->flow_stat->max_fc,
5443                                   false);
5444
5445         if (bp->flow_stat->rx_fc_in_tbl.ctx_id != BNXT_CTX_VAL_INVAL)
5446                 bnxt_hwrm_ctx_unrgtr(bp, bp->flow_stat->rx_fc_in_tbl.ctx_id);
5447         bp->flow_stat->rx_fc_in_tbl.ctx_id = BNXT_CTX_VAL_INVAL;
5448
5449         if (bp->flow_stat->rx_fc_out_tbl.ctx_id != BNXT_CTX_VAL_INVAL)
5450                 bnxt_hwrm_ctx_unrgtr(bp, bp->flow_stat->rx_fc_out_tbl.ctx_id);
5451         bp->flow_stat->rx_fc_out_tbl.ctx_id = BNXT_CTX_VAL_INVAL;
5452
5453         if (bp->flow_stat->tx_fc_in_tbl.ctx_id != BNXT_CTX_VAL_INVAL)
5454                 bnxt_hwrm_ctx_unrgtr(bp, bp->flow_stat->tx_fc_in_tbl.ctx_id);
5455         bp->flow_stat->tx_fc_in_tbl.ctx_id = BNXT_CTX_VAL_INVAL;
5456
5457         if (bp->flow_stat->tx_fc_out_tbl.ctx_id != BNXT_CTX_VAL_INVAL)
5458                 bnxt_hwrm_ctx_unrgtr(bp, bp->flow_stat->tx_fc_out_tbl.ctx_id);
5459         bp->flow_stat->tx_fc_out_tbl.ctx_id = BNXT_CTX_VAL_INVAL;
5460 }
5461
5462 static void bnxt_uninit_fc_ctx_mem(struct bnxt *bp)
5463 {
5464         bnxt_unregister_fc_ctx_mem(bp);
5465
5466         bnxt_free_ctx_mem_buf(&bp->flow_stat->rx_fc_in_tbl);
5467         bnxt_free_ctx_mem_buf(&bp->flow_stat->rx_fc_out_tbl);
5468         bnxt_free_ctx_mem_buf(&bp->flow_stat->tx_fc_in_tbl);
5469         bnxt_free_ctx_mem_buf(&bp->flow_stat->tx_fc_out_tbl);
5470 }
5471
5472 static void bnxt_uninit_ctx_mem(struct bnxt *bp)
5473 {
5474         if (BNXT_FLOW_XSTATS_EN(bp))
5475                 bnxt_uninit_fc_ctx_mem(bp);
5476 }
5477
5478 static void
5479 bnxt_free_error_recovery_info(struct bnxt *bp)
5480 {
5481         rte_free(bp->recovery_info);
5482         bp->recovery_info = NULL;
5483         bp->fw_cap &= ~BNXT_FW_CAP_ERROR_RECOVERY;
5484 }
5485
5486 static int
5487 bnxt_uninit_resources(struct bnxt *bp, bool reconfig_dev)
5488 {
5489         int rc;
5490
5491         bnxt_free_int(bp);
5492         bnxt_free_mem(bp, reconfig_dev);
5493
5494         bnxt_hwrm_func_buf_unrgtr(bp);
5495         rte_free(bp->pf->vf_req_buf);
5496
5497         rc = bnxt_hwrm_func_driver_unregister(bp, 0);
5498         bp->flags &= ~BNXT_FLAG_REGISTERED;
5499         bnxt_free_ctx_mem(bp);
5500         if (!reconfig_dev) {
5501                 bnxt_free_hwrm_resources(bp);
5502                 bnxt_free_error_recovery_info(bp);
5503         }
5504
5505         bnxt_uninit_ctx_mem(bp);
5506
5507         bnxt_free_flow_stats_info(bp);
5508         bnxt_free_rep_info(bp);
5509         rte_free(bp->ptp_cfg);
5510         bp->ptp_cfg = NULL;
5511         return rc;
5512 }
5513
5514 static int
5515 bnxt_dev_uninit(struct rte_eth_dev *eth_dev)
5516 {
5517         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
5518                 return -EPERM;
5519
5520         PMD_DRV_LOG(DEBUG, "Calling Device uninit\n");
5521
5522         if (eth_dev->state != RTE_ETH_DEV_UNUSED)
5523                 bnxt_dev_close_op(eth_dev);
5524
5525         return 0;
5526 }
5527
5528 static int bnxt_pci_remove_dev_with_reps(struct rte_eth_dev *eth_dev)
5529 {
5530         struct bnxt *bp = eth_dev->data->dev_private;
5531         struct rte_eth_dev *vf_rep_eth_dev;
5532         int ret = 0, i;
5533
5534         if (!bp)
5535                 return -EINVAL;
5536
5537         for (i = 0; i < bp->num_reps; i++) {
5538                 vf_rep_eth_dev = bp->rep_info[i].vfr_eth_dev;
5539                 if (!vf_rep_eth_dev)
5540                         continue;
5541                 PMD_DRV_LOG(DEBUG, "BNXT Port:%d VFR pci remove\n",
5542                             vf_rep_eth_dev->data->port_id);
5543                 rte_eth_dev_destroy(vf_rep_eth_dev, bnxt_representor_uninit);
5544         }
5545         PMD_DRV_LOG(DEBUG, "BNXT Port:%d pci remove\n",
5546                     eth_dev->data->port_id);
5547         ret = rte_eth_dev_destroy(eth_dev, bnxt_dev_uninit);
5548
5549         return ret;
5550 }
5551
5552 static void bnxt_free_rep_info(struct bnxt *bp)
5553 {
5554         rte_free(bp->rep_info);
5555         bp->rep_info = NULL;
5556         rte_free(bp->cfa_code_map);
5557         bp->cfa_code_map = NULL;
5558 }
5559
5560 static int bnxt_init_rep_info(struct bnxt *bp)
5561 {
5562         int i = 0, rc;
5563
5564         if (bp->rep_info)
5565                 return 0;
5566
5567         bp->rep_info = rte_zmalloc("bnxt_rep_info",
5568                                    sizeof(bp->rep_info[0]) * BNXT_MAX_VF_REPS,
5569                                    0);
5570         if (!bp->rep_info) {
5571                 PMD_DRV_LOG(ERR, "Failed to alloc memory for rep info\n");
5572                 return -ENOMEM;
5573         }
5574         bp->cfa_code_map = rte_zmalloc("bnxt_cfa_code_map",
5575                                        sizeof(*bp->cfa_code_map) *
5576                                        BNXT_MAX_CFA_CODE, 0);
5577         if (!bp->cfa_code_map) {
5578                 PMD_DRV_LOG(ERR, "Failed to alloc memory for cfa_code_map\n");
5579                 bnxt_free_rep_info(bp);
5580                 return -ENOMEM;
5581         }
5582
5583         for (i = 0; i < BNXT_MAX_CFA_CODE; i++)
5584                 bp->cfa_code_map[i] = BNXT_VF_IDX_INVALID;
5585
5586         rc = pthread_mutex_init(&bp->rep_info->vfr_lock, NULL);
5587         if (rc) {
5588                 PMD_DRV_LOG(ERR, "Unable to initialize vfr_lock\n");
5589                 bnxt_free_rep_info(bp);
5590                 return rc;
5591         }
5592
5593         rc = pthread_mutex_init(&bp->rep_info->vfr_start_lock, NULL);
5594         if (rc) {
5595                 PMD_DRV_LOG(ERR, "Unable to initialize vfr_start_lock\n");
5596                 bnxt_free_rep_info(bp);
5597                 return rc;
5598         }
5599
5600         return rc;
5601 }
5602
5603 static int bnxt_rep_port_probe(struct rte_pci_device *pci_dev,
5604                                struct rte_eth_devargs *eth_da,
5605                                struct rte_eth_dev *backing_eth_dev,
5606                                const char *dev_args)
5607 {
5608         struct rte_eth_dev *vf_rep_eth_dev;
5609         char name[RTE_ETH_NAME_MAX_LEN];
5610         struct bnxt *backing_bp;
5611         uint16_t num_rep;
5612         int i, ret = 0;
5613         struct rte_kvargs *kvlist = NULL;
5614
5615         num_rep = eth_da->nb_representor_ports;
5616         if (num_rep > BNXT_MAX_VF_REPS) {
5617                 PMD_DRV_LOG(ERR, "nb_representor_ports = %d > %d MAX VF REPS\n",
5618                             num_rep, BNXT_MAX_VF_REPS);
5619                 return -EINVAL;
5620         }
5621
5622         if (num_rep >= RTE_MAX_ETHPORTS) {
5623                 PMD_DRV_LOG(ERR,
5624                             "nb_representor_ports = %d > %d MAX ETHPORTS\n",
5625                             num_rep, RTE_MAX_ETHPORTS);
5626                 return -EINVAL;
5627         }
5628
5629         backing_bp = backing_eth_dev->data->dev_private;
5630
5631         if (!(BNXT_PF(backing_bp) || BNXT_VF_IS_TRUSTED(backing_bp))) {
5632                 PMD_DRV_LOG(ERR,
5633                             "Not a PF or trusted VF. No Representor support\n");
5634                 /* Returning an error is not an option.
5635                  * Applications are not handling this correctly
5636                  */
5637                 return 0;
5638         }
5639
5640         if (bnxt_init_rep_info(backing_bp))
5641                 return 0;
5642
5643         for (i = 0; i < num_rep; i++) {
5644                 struct bnxt_representor representor = {
5645                         .vf_id = eth_da->representor_ports[i],
5646                         .switch_domain_id = backing_bp->switch_domain_id,
5647                         .parent_dev = backing_eth_dev
5648                 };
5649
5650                 if (representor.vf_id >= BNXT_MAX_VF_REPS) {
5651                         PMD_DRV_LOG(ERR, "VF-Rep id %d >= %d MAX VF ID\n",
5652                                     representor.vf_id, BNXT_MAX_VF_REPS);
5653                         continue;
5654                 }
5655
5656                 /* representor port net_bdf_port */
5657                 snprintf(name, sizeof(name), "net_%s_representor_%d",
5658                          pci_dev->device.name, eth_da->representor_ports[i]);
5659
5660                 kvlist = rte_kvargs_parse(dev_args, bnxt_dev_args);
5661                 if (kvlist) {
5662                         /*
5663                          * Handler for "rep_is_pf" devarg.
5664                          * Invoked as for ex: "-a 000:00:0d.0,
5665                          * rep-based-pf=<pf index> rep-is-pf=<VF=0 or PF=1>"
5666                          */
5667                         ret = rte_kvargs_process(kvlist, BNXT_DEVARG_REP_IS_PF,
5668                                                  bnxt_parse_devarg_rep_is_pf,
5669                                                  (void *)&representor);
5670                         if (ret) {
5671                                 ret = -EINVAL;
5672                                 goto err;
5673                         }
5674                         /*
5675                          * Handler for "rep_based_pf" devarg.
5676                          * Invoked as for ex: "-a 000:00:0d.0,
5677                          * rep-based-pf=<pf index> rep-is-pf=<VF=0 or PF=1>"
5678                          */
5679                         ret = rte_kvargs_process(kvlist,
5680                                                  BNXT_DEVARG_REP_BASED_PF,
5681                                                  bnxt_parse_devarg_rep_based_pf,
5682                                                  (void *)&representor);
5683                         if (ret) {
5684                                 ret = -EINVAL;
5685                                 goto err;
5686                         }
5687                         /*
5688                          * Handler for "rep_based_pf" devarg.
5689                          * Invoked as for ex: "-a 000:00:0d.0,
5690                          * rep-based-pf=<pf index> rep-is-pf=<VF=0 or PF=1>"
5691                          */
5692                         ret = rte_kvargs_process(kvlist, BNXT_DEVARG_REP_Q_R2F,
5693                                                  bnxt_parse_devarg_rep_q_r2f,
5694                                                  (void *)&representor);
5695                         if (ret) {
5696                                 ret = -EINVAL;
5697                                 goto err;
5698                         }
5699                         /*
5700                          * Handler for "rep_based_pf" devarg.
5701                          * Invoked as for ex: "-a 000:00:0d.0,
5702                          * rep-based-pf=<pf index> rep-is-pf=<VF=0 or PF=1>"
5703                          */
5704                         ret = rte_kvargs_process(kvlist, BNXT_DEVARG_REP_Q_F2R,
5705                                                  bnxt_parse_devarg_rep_q_f2r,
5706                                                  (void *)&representor);
5707                         if (ret) {
5708                                 ret = -EINVAL;
5709                                 goto err;
5710                         }
5711                         /*
5712                          * Handler for "rep_based_pf" devarg.
5713                          * Invoked as for ex: "-a 000:00:0d.0,
5714                          * rep-based-pf=<pf index> rep-is-pf=<VF=0 or PF=1>"
5715                          */
5716                         ret = rte_kvargs_process(kvlist, BNXT_DEVARG_REP_FC_R2F,
5717                                                  bnxt_parse_devarg_rep_fc_r2f,
5718                                                  (void *)&representor);
5719                         if (ret) {
5720                                 ret = -EINVAL;
5721                                 goto err;
5722                         }
5723                         /*
5724                          * Handler for "rep_based_pf" devarg.
5725                          * Invoked as for ex: "-a 000:00:0d.0,
5726                          * rep-based-pf=<pf index> rep-is-pf=<VF=0 or PF=1>"
5727                          */
5728                         ret = rte_kvargs_process(kvlist, BNXT_DEVARG_REP_FC_F2R,
5729                                                  bnxt_parse_devarg_rep_fc_f2r,
5730                                                  (void *)&representor);
5731                         if (ret) {
5732                                 ret = -EINVAL;
5733                                 goto err;
5734                         }
5735                 }
5736
5737                 ret = rte_eth_dev_create(&pci_dev->device, name,
5738                                          sizeof(struct bnxt_representor),
5739                                          NULL, NULL,
5740                                          bnxt_representor_init,
5741                                          &representor);
5742                 if (ret) {
5743                         PMD_DRV_LOG(ERR, "failed to create bnxt vf "
5744                                     "representor %s.", name);
5745                         goto err;
5746                 }
5747
5748                 vf_rep_eth_dev = rte_eth_dev_allocated(name);
5749                 if (!vf_rep_eth_dev) {
5750                         PMD_DRV_LOG(ERR, "Failed to find the eth_dev"
5751                                     " for VF-Rep: %s.", name);
5752                         ret = -ENODEV;
5753                         goto err;
5754                 }
5755
5756                 PMD_DRV_LOG(DEBUG, "BNXT Port:%d VFR pci probe\n",
5757                             backing_eth_dev->data->port_id);
5758                 backing_bp->rep_info[representor.vf_id].vfr_eth_dev =
5759                                                          vf_rep_eth_dev;
5760                 backing_bp->num_reps++;
5761
5762         }
5763
5764         rte_kvargs_free(kvlist);
5765         return 0;
5766
5767 err:
5768         /* If num_rep > 1, then rollback already created
5769          * ports, since we'll be failing the probe anyway
5770          */
5771         if (num_rep > 1)
5772                 bnxt_pci_remove_dev_with_reps(backing_eth_dev);
5773         rte_errno = -ret;
5774         rte_kvargs_free(kvlist);
5775
5776         return ret;
5777 }
5778
5779 static int bnxt_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
5780                           struct rte_pci_device *pci_dev)
5781 {
5782         struct rte_eth_devargs eth_da = { .nb_representor_ports = 0 };
5783         struct rte_eth_dev *backing_eth_dev;
5784         uint16_t num_rep;
5785         int ret = 0;
5786
5787         if (pci_dev->device.devargs) {
5788                 ret = rte_eth_devargs_parse(pci_dev->device.devargs->args,
5789                                             &eth_da);
5790                 if (ret)
5791                         return ret;
5792         }
5793
5794         num_rep = eth_da.nb_representor_ports;
5795         PMD_DRV_LOG(DEBUG, "nb_representor_ports = %d\n",
5796                     num_rep);
5797
5798         /* We could come here after first level of probe is already invoked
5799          * as part of an application bringup(OVS-DPDK vswitchd), so first check
5800          * for already allocated eth_dev for the backing device (PF/Trusted VF)
5801          */
5802         backing_eth_dev = rte_eth_dev_allocated(pci_dev->device.name);
5803         if (backing_eth_dev == NULL) {
5804                 ret = rte_eth_dev_create(&pci_dev->device, pci_dev->device.name,
5805                                          sizeof(struct bnxt),
5806                                          eth_dev_pci_specific_init, pci_dev,
5807                                          bnxt_dev_init, NULL);
5808
5809                 if (ret || !num_rep)
5810                         return ret;
5811
5812                 backing_eth_dev = rte_eth_dev_allocated(pci_dev->device.name);
5813         }
5814         PMD_DRV_LOG(DEBUG, "BNXT Port:%d pci probe\n",
5815                     backing_eth_dev->data->port_id);
5816
5817         if (!num_rep)
5818                 return ret;
5819
5820         /* probe representor ports now */
5821         ret = bnxt_rep_port_probe(pci_dev, &eth_da, backing_eth_dev,
5822                                   pci_dev->device.devargs->args);
5823
5824         return ret;
5825 }
5826
5827 static int bnxt_pci_remove(struct rte_pci_device *pci_dev)
5828 {
5829         struct rte_eth_dev *eth_dev;
5830
5831         eth_dev = rte_eth_dev_allocated(pci_dev->device.name);
5832         if (!eth_dev)
5833                 return 0; /* Invoked typically only by OVS-DPDK, by the
5834                            * time it comes here the eth_dev is already
5835                            * deleted by rte_eth_dev_close(), so returning
5836                            * +ve value will at least help in proper cleanup
5837                            */
5838
5839         PMD_DRV_LOG(DEBUG, "BNXT Port:%d pci remove\n", eth_dev->data->port_id);
5840         if (rte_eal_process_type() == RTE_PROC_PRIMARY) {
5841                 if (eth_dev->data->dev_flags & RTE_ETH_DEV_REPRESENTOR)
5842                         return rte_eth_dev_destroy(eth_dev,
5843                                                    bnxt_representor_uninit);
5844                 else
5845                         return rte_eth_dev_destroy(eth_dev,
5846                                                    bnxt_dev_uninit);
5847         } else {
5848                 return rte_eth_dev_pci_generic_remove(pci_dev, NULL);
5849         }
5850 }
5851
5852 static struct rte_pci_driver bnxt_rte_pmd = {
5853         .id_table = bnxt_pci_id_map,
5854         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC |
5855                         RTE_PCI_DRV_PROBE_AGAIN, /* Needed in case of VF-REPs
5856                                                   * and OVS-DPDK
5857                                                   */
5858         .probe = bnxt_pci_probe,
5859         .remove = bnxt_pci_remove,
5860 };
5861
5862 static bool
5863 is_device_supported(struct rte_eth_dev *dev, struct rte_pci_driver *drv)
5864 {
5865         if (strcmp(dev->device->driver->name, drv->driver.name))
5866                 return false;
5867
5868         return true;
5869 }
5870
5871 bool is_bnxt_supported(struct rte_eth_dev *dev)
5872 {
5873         return is_device_supported(dev, &bnxt_rte_pmd);
5874 }
5875
5876 RTE_LOG_REGISTER(bnxt_logtype_driver, pmd.net.bnxt.driver, NOTICE);
5877 RTE_PMD_REGISTER_PCI(net_bnxt, bnxt_rte_pmd);
5878 RTE_PMD_REGISTER_PCI_TABLE(net_bnxt, bnxt_pci_id_map);
5879 RTE_PMD_REGISTER_KMOD_DEP(net_bnxt, "* igb_uio | uio_pci_generic | vfio-pci");