drivers/net/bnxt/bnxt_ethdev.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2014-2018 Broadcom
   3  * All rights reserved.
   4  */
   5
   6 #include <inttypes.h>
   7 #include <stdbool.h>
   8
   9 #include <rte_dev.h>
  10 #include <rte_ethdev_driver.h>
  11 #include <rte_ethdev_pci.h>
  12 #include <rte_malloc.h>
  13 #include <rte_cycles.h>
  14 #include <rte_alarm.h>
  15 #include <rte_kvargs.h>
  16
  17 #include "bnxt.h"
  18 #include "bnxt_filter.h"
  19 #include "bnxt_hwrm.h"
  20 #include "bnxt_irq.h"
  21 #include "bnxt_reps.h"
  22 #include "bnxt_ring.h"
  23 #include "bnxt_rxq.h"
  24 #include "bnxt_rxr.h"
  25 #include "bnxt_stats.h"
  26 #include "bnxt_txq.h"
  27 #include "bnxt_txr.h"
  28 #include "bnxt_vnic.h"
  29 #include "hsi_struct_def_dpdk.h"
  30 #include "bnxt_nvm_defs.h"
  31 #include "bnxt_tf_common.h"
  32 #include "ulp_flow_db.h"
  33
  34 #define DRV_MODULE_NAME         "bnxt"
  35 static const char bnxt_version[] =
  36         "Broadcom NetXtreme driver " DRV_MODULE_NAME;
  37
  38 /*
  39  * The set of PCI devices this driver supports
  40  */
  41 static const struct rte_pci_id bnxt_pci_id_map[] = {
  42         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM,
  43                          BROADCOM_DEV_ID_STRATUS_NIC_VF1) },
  44         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM,
  45                          BROADCOM_DEV_ID_STRATUS_NIC_VF2) },
  46         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_STRATUS_NIC) },
  47         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414_VF) },
  48         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57301) },
  49         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57302) },
  50         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57304_PF) },
  51         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57304_VF) },
  52         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_NS2) },
  53         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57402) },
  54         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57404) },
  55         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57406_PF) },
  56         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57406_VF) },
  57         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57402_MF) },
  58         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57407_RJ45) },
  59         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57404_MF) },
  60         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57406_MF) },
  61         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57407_SFP) },
  62         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57407_MF) },
  63         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_5741X_VF) },
  64         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_5731X_VF) },
  65         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57314) },
  66         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_MF) },
  67         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57311) },
  68         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57312) },
  69         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57412) },
  70         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414) },
  71         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_RJ45) },
  72         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_RJ45) },
  73         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57412_MF) },
  74         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57317_RJ45) },
  75         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_SFP) },
  76         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_SFP) },
  77         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57317_SFP) },
  78         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414_MF) },
  79         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_MF) },
  80         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58802) },
  81         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58804) },
  82         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58808) },
  83         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58802_VF) },
  84         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57508) },
  85         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57504) },
  86         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57502) },
  87         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57500_VF1) },
  88         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57500_VF2) },
  89         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57508_MF1) },
  90         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57504_MF1) },
  91         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57502_MF1) },
  92         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57508_MF2) },
  93         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57504_MF2) },
  94         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57502_MF2) },
  95         { .vendor_id = 0, /* sentinel */ },
  96 };
  97
  98 #define BNXT_DEVARG_TRUFLOW     "host-based-truflow"
  99 #define BNXT_DEVARG_FLOW_XSTAT  "flow-xstat"
 100 #define BNXT_DEVARG_MAX_NUM_KFLOWS  "max-num-kflows"
 101 #define BNXT_DEVARG_REPRESENTOR "representor"
 102 #define BNXT_DEVARG_REP_BASED_PF  "rep-based-pf"
 103 #define BNXT_DEVARG_REP_IS_PF  "rep-is-pf"
 104 #define BNXT_DEVARG_REP_Q_R2F  "rep-q-r2f"
 105 #define BNXT_DEVARG_REP_Q_F2R  "rep-q-f2r"
 106 #define BNXT_DEVARG_REP_FC_R2F  "rep-fc-r2f"
 107 #define BNXT_DEVARG_REP_FC_F2R  "rep-fc-f2r"
 108
 109 static const char *const bnxt_dev_args[] = {
 110         BNXT_DEVARG_REPRESENTOR,
 111         BNXT_DEVARG_TRUFLOW,
 112         BNXT_DEVARG_FLOW_XSTAT,
 113         BNXT_DEVARG_MAX_NUM_KFLOWS,
 114         BNXT_DEVARG_REP_BASED_PF,
 115         BNXT_DEVARG_REP_IS_PF,
 116         BNXT_DEVARG_REP_Q_R2F,
 117         BNXT_DEVARG_REP_Q_F2R,
 118         BNXT_DEVARG_REP_FC_R2F,
 119         BNXT_DEVARG_REP_FC_F2R,
 120         NULL
 121 };
 122
 123 /*
 124  * truflow == false to disable the feature
 125  * truflow == true to enable the feature
 126  */
 127 #define BNXT_DEVARG_TRUFLOW_INVALID(truflow)    ((truflow) > 1)
 128
 129 /*
 130  * flow_xstat == false to disable the feature
 131  * flow_xstat == true to enable the feature
 132  */
 133 #define BNXT_DEVARG_FLOW_XSTAT_INVALID(flow_xstat)      ((flow_xstat) > 1)
 134
 135 /*
 136  * rep_is_pf == false to indicate VF representor
 137  * rep_is_pf == true to indicate PF representor
 138  */
 139 #define BNXT_DEVARG_REP_IS_PF_INVALID(rep_is_pf)        ((rep_is_pf) > 1)
 140
 141 /*
 142  * rep_based_pf == Physical index of the PF
 143  */
 144 #define BNXT_DEVARG_REP_BASED_PF_INVALID(rep_based_pf)  ((rep_based_pf) > 15)
 145 /*
 146  * rep_q_r2f == Logical COS Queue index for the rep to endpoint direction
 147  */
 148 #define BNXT_DEVARG_REP_Q_R2F_INVALID(rep_q_r2f)        ((rep_q_r2f) > 3)
 149
 150 /*
 151  * rep_q_f2r == Logical COS Queue index for the endpoint to rep direction
 152  */
 153 #define BNXT_DEVARG_REP_Q_F2R_INVALID(rep_q_f2r)        ((rep_q_f2r) > 3)
 154
 155 /*
 156  * rep_fc_r2f == Flow control for the representor to endpoint direction
 157  */
 158 #define BNXT_DEVARG_REP_FC_R2F_INVALID(rep_fc_r2f)      ((rep_fc_r2f) > 1)
 159
 160 /*
 161  * rep_fc_f2r == Flow control for the endpoint to representor direction
 162  */
 163 #define BNXT_DEVARG_REP_FC_F2R_INVALID(rep_fc_f2r)      ((rep_fc_f2r) > 1)
 164
 165 /*
 166  * max_num_kflows must be >= 32
 167  * and must be a power-of-2 supported value
 168  * return: 1 -> invalid
 169  *         0 -> valid
 170  */
 171 static int bnxt_devarg_max_num_kflow_invalid(uint16_t max_num_kflows)
 172 {
 173         if (max_num_kflows < 32 || !rte_is_power_of_2(max_num_kflows))
 174                 return 1;
 175         return 0;
 176 }
 177
 178 static int bnxt_vlan_offload_set_op(struct rte_eth_dev *dev, int mask);
 179 static int bnxt_dev_uninit(struct rte_eth_dev *eth_dev);
 180 static int bnxt_init_resources(struct bnxt *bp, bool reconfig_dev);
 181 static int bnxt_uninit_resources(struct bnxt *bp, bool reconfig_dev);
 182 static void bnxt_cancel_fw_health_check(struct bnxt *bp);
 183 static int bnxt_restore_vlan_filters(struct bnxt *bp);
 184 static void bnxt_dev_recover(void *arg);
 185 static void bnxt_free_error_recovery_info(struct bnxt *bp);
 186 static void bnxt_free_rep_info(struct bnxt *bp);
 187
 188 int is_bnxt_in_error(struct bnxt *bp)
 189 {
 190         if (bp->flags & BNXT_FLAG_FATAL_ERROR)
 191                 return -EIO;
 192         if (bp->flags & BNXT_FLAG_FW_RESET)
 193                 return -EBUSY;
 194
 195         return 0;
 196 }
 197
 198 /***********************/
 199
 200 /*
 201  * High level utility functions
 202  */
 203
 204 static uint16_t bnxt_rss_ctxts(const struct bnxt *bp)
 205 {
 206         if (!BNXT_CHIP_THOR(bp))
 207                 return 1;
 208
 209         return RTE_ALIGN_MUL_CEIL(bp->rx_nr_rings,
 210                                   BNXT_RSS_ENTRIES_PER_CTX_THOR) /
 211                                     BNXT_RSS_ENTRIES_PER_CTX_THOR;
 212 }
 213
 214 uint16_t bnxt_rss_hash_tbl_size(const struct bnxt *bp)
 215 {
 216         if (!BNXT_CHIP_THOR(bp))
 217                 return HW_HASH_INDEX_SIZE;
 218
 219         return bnxt_rss_ctxts(bp) * BNXT_RSS_ENTRIES_PER_CTX_THOR;
 220 }
 221
 222 static void bnxt_free_parent_info(struct bnxt *bp)
 223 {
 224         rte_free(bp->parent);
 225 }
 226
 227 static void bnxt_free_pf_info(struct bnxt *bp)
 228 {
 229         rte_free(bp->pf);
 230 }
 231
 232 static void bnxt_free_link_info(struct bnxt *bp)
 233 {
 234         rte_free(bp->link_info);
 235 }
 236
 237 static void bnxt_free_leds_info(struct bnxt *bp)
 238 {
 239         if (BNXT_VF(bp))
 240                 return;
 241
 242         rte_free(bp->leds);
 243         bp->leds = NULL;
 244 }
 245
 246 static void bnxt_free_flow_stats_info(struct bnxt *bp)
 247 {
 248         rte_free(bp->flow_stat);
 249         bp->flow_stat = NULL;
 250 }
 251
 252 static void bnxt_free_cos_queues(struct bnxt *bp)
 253 {
 254         rte_free(bp->rx_cos_queue);
 255         rte_free(bp->tx_cos_queue);
 256 }
 257
 258 static void bnxt_free_mem(struct bnxt *bp, bool reconfig)
 259 {
 260         bnxt_free_filter_mem(bp);
 261         bnxt_free_vnic_attributes(bp);
 262         bnxt_free_vnic_mem(bp);
 263
 264         /* tx/rx rings are configured as part of *_queue_setup callbacks.
 265          * If the number of rings change across fw update,
 266          * we don't have much choice except to warn the user.
 267          */
 268         if (!reconfig) {
 269                 bnxt_free_stats(bp);
 270                 bnxt_free_tx_rings(bp);
 271                 bnxt_free_rx_rings(bp);
 272         }
 273         bnxt_free_async_cp_ring(bp);
 274         bnxt_free_rxtx_nq_ring(bp);
 275
 276         rte_free(bp->grp_info);
 277         bp->grp_info = NULL;
 278 }
 279
 280 static int bnxt_alloc_parent_info(struct bnxt *bp)
 281 {
 282         bp->parent = rte_zmalloc("bnxt_parent_info",
 283                                  sizeof(struct bnxt_parent_info), 0);
 284         if (bp->parent == NULL)
 285                 return -ENOMEM;
 286
 287         return 0;
 288 }
 289
 290 static int bnxt_alloc_pf_info(struct bnxt *bp)
 291 {
 292         bp->pf = rte_zmalloc("bnxt_pf_info", sizeof(struct bnxt_pf_info), 0);
 293         if (bp->pf == NULL)
 294                 return -ENOMEM;
 295
 296         return 0;
 297 }
 298
 299 static int bnxt_alloc_link_info(struct bnxt *bp)
 300 {
 301         bp->link_info =
 302                 rte_zmalloc("bnxt_link_info", sizeof(struct bnxt_link_info), 0);
 303         if (bp->link_info == NULL)
 304                 return -ENOMEM;
 305
 306         return 0;
 307 }
 308
 309 static int bnxt_alloc_leds_info(struct bnxt *bp)
 310 {
 311         if (BNXT_VF(bp))
 312                 return 0;
 313
 314         bp->leds = rte_zmalloc("bnxt_leds",
 315                                BNXT_MAX_LED * sizeof(struct bnxt_led_info),
 316                                0);
 317         if (bp->leds == NULL)
 318                 return -ENOMEM;
 319
 320         return 0;
 321 }
 322
 323 static int bnxt_alloc_cos_queues(struct bnxt *bp)
 324 {
 325         bp->rx_cos_queue =
 326                 rte_zmalloc("bnxt_rx_cosq",
 327                             BNXT_COS_QUEUE_COUNT *
 328                             sizeof(struct bnxt_cos_queue_info),
 329                             0);
 330         if (bp->rx_cos_queue == NULL)
 331                 return -ENOMEM;
 332
 333         bp->tx_cos_queue =
 334                 rte_zmalloc("bnxt_tx_cosq",
 335                             BNXT_COS_QUEUE_COUNT *
 336                             sizeof(struct bnxt_cos_queue_info),
 337                             0);
 338         if (bp->tx_cos_queue == NULL)
 339                 return -ENOMEM;
 340
 341         return 0;
 342 }
 343
 344 static int bnxt_alloc_flow_stats_info(struct bnxt *bp)
 345 {
 346         bp->flow_stat = rte_zmalloc("bnxt_flow_xstat",
 347                                     sizeof(struct bnxt_flow_stat_info), 0);
 348         if (bp->flow_stat == NULL)
 349                 return -ENOMEM;
 350
 351         return 0;
 352 }
 353
 354 static int bnxt_alloc_mem(struct bnxt *bp, bool reconfig)
 355 {
 356         int rc;
 357
 358         rc = bnxt_alloc_ring_grps(bp);
 359         if (rc)
 360                 goto alloc_mem_err;
 361
 362         rc = bnxt_alloc_async_ring_struct(bp);
 363         if (rc)
 364                 goto alloc_mem_err;
 365
 366         rc = bnxt_alloc_vnic_mem(bp);
 367         if (rc)
 368                 goto alloc_mem_err;
 369
 370         rc = bnxt_alloc_vnic_attributes(bp);
 371         if (rc)
 372                 goto alloc_mem_err;
 373
 374         rc = bnxt_alloc_filter_mem(bp);
 375         if (rc)
 376                 goto alloc_mem_err;
 377
 378         rc = bnxt_alloc_async_cp_ring(bp);
 379         if (rc)
 380                 goto alloc_mem_err;
 381
 382         rc = bnxt_alloc_rxtx_nq_ring(bp);
 383         if (rc)
 384                 goto alloc_mem_err;
 385
 386         if (BNXT_FLOW_XSTATS_EN(bp)) {
 387                 rc = bnxt_alloc_flow_stats_info(bp);
 388                 if (rc)
 389                         goto alloc_mem_err;
 390         }
 391
 392         return 0;
 393
 394 alloc_mem_err:
 395         bnxt_free_mem(bp, reconfig);
 396         return rc;
 397 }
 398
 399 static int bnxt_setup_one_vnic(struct bnxt *bp, uint16_t vnic_id)
 400 {
 401         struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
 402         struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id];
 403         uint64_t rx_offloads = dev_conf->rxmode.offloads;
 404         struct bnxt_rx_queue *rxq;
 405         unsigned int j;
 406         int rc;
 407
 408         rc = bnxt_vnic_grp_alloc(bp, vnic);
 409         if (rc)
 410                 goto err_out;
 411
 412         PMD_DRV_LOG(DEBUG, "vnic[%d] = %p vnic->fw_grp_ids = %p\n",
 413                     vnic_id, vnic, vnic->fw_grp_ids);
 414
 415         rc = bnxt_hwrm_vnic_alloc(bp, vnic);
 416         if (rc)
 417                 goto err_out;
 418
 419         /* Alloc RSS context only if RSS mode is enabled */
 420         if (dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS) {
 421                 int j, nr_ctxs = bnxt_rss_ctxts(bp);
 422
 423                 rc = 0;
 424                 for (j = 0; j < nr_ctxs; j++) {
 425                         rc = bnxt_hwrm_vnic_ctx_alloc(bp, vnic, j);
 426                         if (rc)
 427                                 break;
 428                 }
 429                 if (rc) {
 430                         PMD_DRV_LOG(ERR,
 431                                     "HWRM vnic %d ctx %d alloc failure rc: %x\n",
 432                                     vnic_id, j, rc);
 433                         goto err_out;
 434                 }
 435                 vnic->num_lb_ctxts = nr_ctxs;
 436         }
 437
 438         /*
 439          * Firmware sets pf pair in default vnic cfg. If the VLAN strip
 440          * setting is not available at this time, it will not be
 441          * configured correctly in the CFA.
 442          */
 443         if (rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
 444                 vnic->vlan_strip = true;
 445         else
 446                 vnic->vlan_strip = false;
 447
 448         rc = bnxt_hwrm_vnic_cfg(bp, vnic);
 449         if (rc)
 450                 goto err_out;
 451
 452         rc = bnxt_set_hwrm_vnic_filters(bp, vnic);
 453         if (rc)
 454                 goto err_out;
 455
 456         for (j = 0; j < bp->rx_num_qs_per_vnic; j++) {
 457                 rxq = bp->eth_dev->data->rx_queues[j];
 458
 459                 PMD_DRV_LOG(DEBUG,
 460                             "rxq[%d]->vnic=%p vnic->fw_grp_ids=%p\n",
 461                             j, rxq->vnic, rxq->vnic->fw_grp_ids);
 462
 463                 if (BNXT_HAS_RING_GRPS(bp) && rxq->rx_deferred_start)
 464                         rxq->vnic->fw_grp_ids[j] = INVALID_HW_RING_ID;
 465                 else
 466                         vnic->rx_queue_cnt++;
 467         }
 468
 469         PMD_DRV_LOG(DEBUG, "vnic->rx_queue_cnt = %d\n", vnic->rx_queue_cnt);
 470
 471         rc = bnxt_vnic_rss_configure(bp, vnic);
 472         if (rc)
 473                 goto err_out;
 474
 475         bnxt_hwrm_vnic_plcmode_cfg(bp, vnic);
 476
 477         if (rx_offloads & DEV_RX_OFFLOAD_TCP_LRO)
 478                 bnxt_hwrm_vnic_tpa_cfg(bp, vnic, 1);
 479         else
 480                 bnxt_hwrm_vnic_tpa_cfg(bp, vnic, 0);
 481
 482         return 0;
 483 err_out:
 484         PMD_DRV_LOG(ERR, "HWRM vnic %d cfg failure rc: %x\n",
 485                     vnic_id, rc);
 486         return rc;
 487 }
 488
 489 static int bnxt_register_fc_ctx_mem(struct bnxt *bp)
 490 {
 491         int rc = 0;
 492
 493         rc = bnxt_hwrm_ctx_rgtr(bp, bp->flow_stat->rx_fc_in_tbl.dma,
 494                                 &bp->flow_stat->rx_fc_in_tbl.ctx_id);
 495         if (rc)
 496                 return rc;
 497
 498         PMD_DRV_LOG(DEBUG,
 499                     "rx_fc_in_tbl.va = %p rx_fc_in_tbl.dma = %p"
 500                     " rx_fc_in_tbl.ctx_id = %d\n",
 501                     bp->flow_stat->rx_fc_in_tbl.va,
 502                     (void *)((uintptr_t)bp->flow_stat->rx_fc_in_tbl.dma),
 503                     bp->flow_stat->rx_fc_in_tbl.ctx_id);
 504
 505         rc = bnxt_hwrm_ctx_rgtr(bp, bp->flow_stat->rx_fc_out_tbl.dma,
 506                                 &bp->flow_stat->rx_fc_out_tbl.ctx_id);
 507         if (rc)
 508                 return rc;
 509
 510         PMD_DRV_LOG(DEBUG,
 511                     "rx_fc_out_tbl.va = %p rx_fc_out_tbl.dma = %p"
 512                     " rx_fc_out_tbl.ctx_id = %d\n",
 513                     bp->flow_stat->rx_fc_out_tbl.va,
 514                     (void *)((uintptr_t)bp->flow_stat->rx_fc_out_tbl.dma),
 515                     bp->flow_stat->rx_fc_out_tbl.ctx_id);
 516
 517         rc = bnxt_hwrm_ctx_rgtr(bp, bp->flow_stat->tx_fc_in_tbl.dma,
 518                                 &bp->flow_stat->tx_fc_in_tbl.ctx_id);
 519         if (rc)
 520                 return rc;
 521
 522         PMD_DRV_LOG(DEBUG,
 523                     "tx_fc_in_tbl.va = %p tx_fc_in_tbl.dma = %p"
 524                     " tx_fc_in_tbl.ctx_id = %d\n",
 525                     bp->flow_stat->tx_fc_in_tbl.va,
 526                     (void *)((uintptr_t)bp->flow_stat->tx_fc_in_tbl.dma),
 527                     bp->flow_stat->tx_fc_in_tbl.ctx_id);
 528
 529         rc = bnxt_hwrm_ctx_rgtr(bp, bp->flow_stat->tx_fc_out_tbl.dma,
 530                                 &bp->flow_stat->tx_fc_out_tbl.ctx_id);
 531         if (rc)
 532                 return rc;
 533
 534         PMD_DRV_LOG(DEBUG,
 535                     "tx_fc_out_tbl.va = %p tx_fc_out_tbl.dma = %p"
 536                     " tx_fc_out_tbl.ctx_id = %d\n",
 537                     bp->flow_stat->tx_fc_out_tbl.va,
 538                     (void *)((uintptr_t)bp->flow_stat->tx_fc_out_tbl.dma),
 539                     bp->flow_stat->tx_fc_out_tbl.ctx_id);
 540
 541         memset(bp->flow_stat->rx_fc_out_tbl.va,
 542                0,
 543                bp->flow_stat->rx_fc_out_tbl.size);
 544         rc = bnxt_hwrm_cfa_counter_cfg(bp, BNXT_DIR_RX,
 545                                        CFA_COUNTER_CFG_IN_COUNTER_TYPE_FC,
 546                                        bp->flow_stat->rx_fc_out_tbl.ctx_id,
 547                                        bp->flow_stat->max_fc,
 548                                        true);
 549         if (rc)
 550                 return rc;
 551
 552         memset(bp->flow_stat->tx_fc_out_tbl.va,
 553                0,
 554                bp->flow_stat->tx_fc_out_tbl.size);
 555         rc = bnxt_hwrm_cfa_counter_cfg(bp, BNXT_DIR_TX,
 556                                        CFA_COUNTER_CFG_IN_COUNTER_TYPE_FC,
 557                                        bp->flow_stat->tx_fc_out_tbl.ctx_id,
 558                                        bp->flow_stat->max_fc,
 559                                        true);
 560
 561         return rc;
 562 }
 563
 564 static int bnxt_alloc_ctx_mem_buf(char *type, size_t size,
 565                                   struct bnxt_ctx_mem_buf_info *ctx)
 566 {
 567         if (!ctx)
 568                 return -EINVAL;
 569
 570         ctx->va = rte_zmalloc(type, size, 0);
 571         if (ctx->va == NULL)
 572                 return -ENOMEM;
 573         rte_mem_lock_page(ctx->va);
 574         ctx->size = size;
 575         ctx->dma = rte_mem_virt2iova(ctx->va);
 576         if (ctx->dma == RTE_BAD_IOVA)
 577                 return -ENOMEM;
 578
 579         return 0;
 580 }
 581
 582 static int bnxt_init_fc_ctx_mem(struct bnxt *bp)
 583 {
 584         struct rte_pci_device *pdev = bp->pdev;
 585         char type[RTE_MEMZONE_NAMESIZE];
 586         uint16_t max_fc;
 587         int rc = 0;
 588
 589         max_fc = bp->flow_stat->max_fc;
 590
 591         sprintf(type, "bnxt_rx_fc_in_" PCI_PRI_FMT, pdev->addr.domain,
 592                 pdev->addr.bus, pdev->addr.devid, pdev->addr.function);
 593         /* 4 bytes for each counter-id */
 594         rc = bnxt_alloc_ctx_mem_buf(type,
 595                                     max_fc * 4,
 596                                     &bp->flow_stat->rx_fc_in_tbl);
 597         if (rc)
 598                 return rc;
 599
 600         sprintf(type, "bnxt_rx_fc_out_" PCI_PRI_FMT, pdev->addr.domain,
 601                 pdev->addr.bus, pdev->addr.devid, pdev->addr.function);
 602         /* 16 bytes for each counter - 8 bytes pkt_count, 8 bytes byte_count */
 603         rc = bnxt_alloc_ctx_mem_buf(type,
 604                                     max_fc * 16,
 605                                     &bp->flow_stat->rx_fc_out_tbl);
 606         if (rc)
 607                 return rc;
 608
 609         sprintf(type, "bnxt_tx_fc_in_" PCI_PRI_FMT, pdev->addr.domain,
 610                 pdev->addr.bus, pdev->addr.devid, pdev->addr.function);
 611         /* 4 bytes for each counter-id */
 612         rc = bnxt_alloc_ctx_mem_buf(type,
 613                                     max_fc * 4,
 614                                     &bp->flow_stat->tx_fc_in_tbl);
 615         if (rc)
 616                 return rc;
 617
 618         sprintf(type, "bnxt_tx_fc_out_" PCI_PRI_FMT, pdev->addr.domain,
 619                 pdev->addr.bus, pdev->addr.devid, pdev->addr.function);
 620         /* 16 bytes for each counter - 8 bytes pkt_count, 8 bytes byte_count */
 621         rc = bnxt_alloc_ctx_mem_buf(type,
 622                                     max_fc * 16,
 623                                     &bp->flow_stat->tx_fc_out_tbl);
 624         if (rc)
 625                 return rc;
 626
 627         rc = bnxt_register_fc_ctx_mem(bp);
 628
 629         return rc;
 630 }
 631
 632 static int bnxt_init_ctx_mem(struct bnxt *bp)
 633 {
 634         int rc = 0;
 635
 636         if (!(bp->fw_cap & BNXT_FW_CAP_ADV_FLOW_COUNTERS) ||
 637             !(BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp)) ||
 638             !BNXT_FLOW_XSTATS_EN(bp))
 639                 return 0;
 640
 641         rc = bnxt_hwrm_cfa_counter_qcaps(bp, &bp->flow_stat->max_fc);
 642         if (rc)
 643                 return rc;
 644
 645         rc = bnxt_init_fc_ctx_mem(bp);
 646
 647         return rc;
 648 }
 649
 650 static int bnxt_update_phy_setting(struct bnxt *bp)
 651 {
 652         struct rte_eth_link new;
 653         int rc;
 654
 655         rc = bnxt_get_hwrm_link_config(bp, &new);
 656         if (rc) {
 657                 PMD_DRV_LOG(ERR, "Failed to get link settings\n");
 658                 return rc;
 659         }
 660
 661         /*
 662          * On BCM957508-N2100 adapters, FW will not allow any user other
 663          * than BMC to shutdown the port. bnxt_get_hwrm_link_config() call
 664          * always returns link up. Force phy update always in that case.
 665          */
 666         if (!new.link_status || IS_BNXT_DEV_957508_N2100(bp)) {
 667                 rc = bnxt_set_hwrm_link_config(bp, true);
 668                 if (rc) {
 669                         PMD_DRV_LOG(ERR, "Failed to update PHY settings\n");
 670                         return rc;
 671                 }
 672         }
 673
 674         return rc;
 675 }
 676
 677 static int bnxt_init_chip(struct bnxt *bp)
 678 {
 679         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(bp->eth_dev);
 680         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
 681         uint32_t intr_vector = 0;
 682         uint32_t queue_id, base = BNXT_MISC_VEC_ID;
 683         uint32_t vec = BNXT_MISC_VEC_ID;
 684         unsigned int i, j;
 685         int rc;
 686
 687         if (bp->eth_dev->data->mtu > RTE_ETHER_MTU) {
 688                 bp->eth_dev->data->dev_conf.rxmode.offloads |=
 689                         DEV_RX_OFFLOAD_JUMBO_FRAME;
 690                 bp->flags |= BNXT_FLAG_JUMBO;
 691         } else {
 692                 bp->eth_dev->data->dev_conf.rxmode.offloads &=
 693                         ~DEV_RX_OFFLOAD_JUMBO_FRAME;
 694                 bp->flags &= ~BNXT_FLAG_JUMBO;
 695         }
 696
 697         /* THOR does not support ring groups.
 698          * But we will use the array to save RSS context IDs.
 699          */
 700         if (BNXT_CHIP_THOR(bp))
 701                 bp->max_ring_grps = BNXT_MAX_RSS_CTXTS_THOR;
 702
 703         rc = bnxt_alloc_all_hwrm_stat_ctxs(bp);
 704         if (rc) {
 705                 PMD_DRV_LOG(ERR, "HWRM stat ctx alloc failure rc: %x\n", rc);
 706                 goto err_out;
 707         }
 708
 709         rc = bnxt_alloc_hwrm_rings(bp);
 710         if (rc) {
 711                 PMD_DRV_LOG(ERR, "HWRM ring alloc failure rc: %x\n", rc);
 712                 goto err_out;
 713         }
 714
 715         rc = bnxt_alloc_all_hwrm_ring_grps(bp);
 716         if (rc) {
 717                 PMD_DRV_LOG(ERR, "HWRM ring grp alloc failure: %x\n", rc);
 718                 goto err_out;
 719         }
 720
 721         if (!(bp->vnic_cap_flags & BNXT_VNIC_CAP_COS_CLASSIFY))
 722                 goto skip_cosq_cfg;
 723
 724         for (j = 0, i = 0; i < BNXT_COS_QUEUE_COUNT; i++) {
 725                 if (bp->rx_cos_queue[i].id != 0xff) {
 726                         struct bnxt_vnic_info *vnic = &bp->vnic_info[j++];
 727
 728                         if (!vnic) {
 729                                 PMD_DRV_LOG(ERR,
 730                                             "Num pools more than FW profile\n");
 731                                 rc = -EINVAL;
 732                                 goto err_out;
 733                         }
 734                         vnic->cos_queue_id = bp->rx_cos_queue[i].id;
 735                         bp->rx_cosq_cnt++;
 736                 }
 737         }
 738
 739 skip_cosq_cfg:
 740         rc = bnxt_mq_rx_configure(bp);
 741         if (rc) {
 742                 PMD_DRV_LOG(ERR, "MQ mode configure failure rc: %x\n", rc);
 743                 goto err_out;
 744         }
 745
 746         /* VNIC configuration */
 747         for (i = 0; i < bp->nr_vnics; i++) {
 748                 rc = bnxt_setup_one_vnic(bp, i);
 749                 if (rc)
 750                         goto err_out;
 751         }
 752
 753         rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, &bp->vnic_info[0], 0, NULL);
 754         if (rc) {
 755                 PMD_DRV_LOG(ERR,
 756                         "HWRM cfa l2 rx mask failure rc: %x\n", rc);
 757                 goto err_out;
 758         }
 759
 760         /* check and configure queue intr-vector mapping */
 761         if ((rte_intr_cap_multiple(intr_handle) ||
 762              !RTE_ETH_DEV_SRIOV(bp->eth_dev).active) &&
 763             bp->eth_dev->data->dev_conf.intr_conf.rxq != 0) {
 764                 intr_vector = bp->eth_dev->data->nb_rx_queues;
 765                 PMD_DRV_LOG(DEBUG, "intr_vector = %d\n", intr_vector);
 766                 if (intr_vector > bp->rx_cp_nr_rings) {
 767                         PMD_DRV_LOG(ERR, "At most %d intr queues supported",
 768                                         bp->rx_cp_nr_rings);
 769                         return -ENOTSUP;
 770                 }
 771                 rc = rte_intr_efd_enable(intr_handle, intr_vector);
 772                 if (rc)
 773                         return rc;
 774         }
 775
 776         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
 777                 intr_handle->intr_vec =
 778                         rte_zmalloc("intr_vec",
 779                                     bp->eth_dev->data->nb_rx_queues *
 780                                     sizeof(int), 0);
 781                 if (intr_handle->intr_vec == NULL) {
 782                         PMD_DRV_LOG(ERR, "Failed to allocate %d rx_queues"
 783                                 " intr_vec", bp->eth_dev->data->nb_rx_queues);
 784                         rc = -ENOMEM;
 785                         goto err_disable;
 786                 }
 787                 PMD_DRV_LOG(DEBUG, "intr_handle->intr_vec = %p "
 788                         "intr_handle->nb_efd = %d intr_handle->max_intr = %d\n",
 789                          intr_handle->intr_vec, intr_handle->nb_efd,
 790                         intr_handle->max_intr);
 791                 for (queue_id = 0; queue_id < bp->eth_dev->data->nb_rx_queues;
 792                      queue_id++) {
 793                         intr_handle->intr_vec[queue_id] =
 794                                                         vec + BNXT_RX_VEC_START;
 795                         if (vec < base + intr_handle->nb_efd - 1)
 796                                 vec++;
 797                 }
 798         }
 799
 800         /* enable uio/vfio intr/eventfd mapping */
 801         rc = rte_intr_enable(intr_handle);
 802 #ifndef RTE_EXEC_ENV_FREEBSD
 803         /* In FreeBSD OS, nic_uio driver does not support interrupts */
 804         if (rc)
 805                 goto err_free;
 806 #endif
 807
 808         rc = bnxt_update_phy_setting(bp);
 809         if (rc)
 810                 goto err_free;
 811
 812         bp->mark_table = rte_zmalloc("bnxt_mark_table", BNXT_MARK_TABLE_SZ, 0);
 813         if (!bp->mark_table)
 814                 PMD_DRV_LOG(ERR, "Allocation of mark table failed\n");
 815
 816         return 0;
 817
 818 err_free:
 819         rte_free(intr_handle->intr_vec);
 820 err_disable:
 821         rte_intr_efd_disable(intr_handle);
 822 err_out:
 823         /* Some of the error status returned by FW may not be from errno.h */
 824         if (rc > 0)
 825                 rc = -EIO;
 826
 827         return rc;
 828 }
 829
 830 static int bnxt_shutdown_nic(struct bnxt *bp)
 831 {
 832         bnxt_free_all_hwrm_resources(bp);
 833         bnxt_free_all_filters(bp);
 834         bnxt_free_all_vnics(bp);
 835         return 0;
 836 }
 837
 838 /*
 839  * Device configuration and status function
 840  */
 841
 842 uint32_t bnxt_get_speed_capabilities(struct bnxt *bp)
 843 {
 844         uint32_t link_speed = bp->link_info->support_speeds;
 845         uint32_t speed_capa = 0;
 846
 847         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_100MB)
 848                 speed_capa |= ETH_LINK_SPEED_100M;
 849         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_100MBHD)
 850                 speed_capa |= ETH_LINK_SPEED_100M_HD;
 851         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_1GB)
 852                 speed_capa |= ETH_LINK_SPEED_1G;
 853         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_2_5GB)
 854                 speed_capa |= ETH_LINK_SPEED_2_5G;
 855         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_10GB)
 856                 speed_capa |= ETH_LINK_SPEED_10G;
 857         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_20GB)
 858                 speed_capa |= ETH_LINK_SPEED_20G;
 859         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_25GB)
 860                 speed_capa |= ETH_LINK_SPEED_25G;
 861         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_40GB)
 862                 speed_capa |= ETH_LINK_SPEED_40G;
 863         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_50GB)
 864                 speed_capa |= ETH_LINK_SPEED_50G;
 865         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_100GB)
 866                 speed_capa |= ETH_LINK_SPEED_100G;
 867         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_PAM4_SPEEDS_50G)
 868                 speed_capa |= ETH_LINK_SPEED_50G;
 869         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_PAM4_SPEEDS_100G)
 870                 speed_capa |= ETH_LINK_SPEED_100G;
 871         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_PAM4_SPEEDS_200G)
 872                 speed_capa |= ETH_LINK_SPEED_200G;
 873
 874         if (bp->link_info->auto_mode ==
 875             HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_MODE_NONE)
 876                 speed_capa |= ETH_LINK_SPEED_FIXED;
 877         else
 878                 speed_capa |= ETH_LINK_SPEED_AUTONEG;
 879
 880         return speed_capa;
 881 }
 882
 883 static int bnxt_dev_info_get_op(struct rte_eth_dev *eth_dev,
 884                                 struct rte_eth_dev_info *dev_info)
 885 {
 886         struct rte_pci_device *pdev = RTE_DEV_TO_PCI(eth_dev->device);
 887         struct bnxt *bp = eth_dev->data->dev_private;
 888         uint16_t max_vnics, i, j, vpool, vrxq;
 889         unsigned int max_rx_rings;
 890         int rc;
 891
 892         rc = is_bnxt_in_error(bp);
 893         if (rc)
 894                 return rc;
 895
 896         /* MAC Specifics */
 897         dev_info->max_mac_addrs = bp->max_l2_ctx;
 898         dev_info->max_hash_mac_addrs = 0;
 899
 900         /* PF/VF specifics */
 901         if (BNXT_PF(bp))
 902                 dev_info->max_vfs = pdev->max_vfs;
 903
 904         max_rx_rings = BNXT_MAX_RINGS(bp);
 905         /* For the sake of symmetry, max_rx_queues = max_tx_queues */
 906         dev_info->max_rx_queues = max_rx_rings;
 907         dev_info->max_tx_queues = max_rx_rings;
 908         dev_info->reta_size = bnxt_rss_hash_tbl_size(bp);
 909         dev_info->hash_key_size = 40;
 910         max_vnics = bp->max_vnics;
 911
 912         /* MTU specifics */
 913         dev_info->min_mtu = RTE_ETHER_MIN_MTU;
 914         dev_info->max_mtu = BNXT_MAX_MTU;
 915
 916         /* Fast path specifics */
 917         dev_info->min_rx_bufsize = 1;
 918         dev_info->max_rx_pktlen = BNXT_MAX_PKT_LEN;
 919
 920         dev_info->rx_offload_capa = BNXT_DEV_RX_OFFLOAD_SUPPORT;
 921         if (bp->flags & BNXT_FLAG_PTP_SUPPORTED)
 922                 dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_TIMESTAMP;
 923         dev_info->tx_queue_offload_capa = DEV_TX_OFFLOAD_MBUF_FAST_FREE;
 924         dev_info->tx_offload_capa = BNXT_DEV_TX_OFFLOAD_SUPPORT |
 925                                     dev_info->tx_queue_offload_capa;
 926         dev_info->flow_type_rss_offloads = BNXT_ETH_RSS_SUPPORT;
 927
 928         dev_info->speed_capa = bnxt_get_speed_capabilities(bp);
 929
 930         /* *INDENT-OFF* */
 931         dev_info->default_rxconf = (struct rte_eth_rxconf) {
 932                 .rx_thresh = {
 933                         .pthresh = 8,
 934                         .hthresh = 8,
 935                         .wthresh = 0,
 936                 },
 937                 .rx_free_thresh = 32,
 938                 .rx_drop_en = BNXT_DEFAULT_RX_DROP_EN,
 939         };
 940
 941         dev_info->default_txconf = (struct rte_eth_txconf) {
 942                 .tx_thresh = {
 943                         .pthresh = 32,
 944                         .hthresh = 0,
 945                         .wthresh = 0,
 946                 },
 947                 .tx_free_thresh = 32,
 948                 .tx_rs_thresh = 32,
 949         };
 950         eth_dev->data->dev_conf.intr_conf.lsc = 1;
 951
 952         eth_dev->data->dev_conf.intr_conf.rxq = 1;
 953         dev_info->rx_desc_lim.nb_min = BNXT_MIN_RING_DESC;
 954         dev_info->rx_desc_lim.nb_max = BNXT_MAX_RX_RING_DESC;
 955         dev_info->tx_desc_lim.nb_min = BNXT_MIN_RING_DESC;
 956         dev_info->tx_desc_lim.nb_max = BNXT_MAX_TX_RING_DESC;
 957
 958         if (BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp)) {
 959                 dev_info->switch_info.name = eth_dev->device->name;
 960                 dev_info->switch_info.domain_id = bp->switch_domain_id;
 961                 dev_info->switch_info.port_id =
 962                                 BNXT_PF(bp) ? BNXT_SWITCH_PORT_ID_PF :
 963                                     BNXT_SWITCH_PORT_ID_TRUSTED_VF;
 964         }
 965
 966         /* *INDENT-ON* */
 967
 968         /*
 969          * TODO: default_rxconf, default_txconf, rx_desc_lim, and tx_desc_lim
 970          *       need further investigation.
 971          */
 972
 973         /* VMDq resources */
 974         vpool = 64; /* ETH_64_POOLS */
 975         vrxq = 128; /* ETH_VMDQ_DCB_NUM_QUEUES */
 976         for (i = 0; i < 4; vpool >>= 1, i++) {
 977                 if (max_vnics > vpool) {
 978                         for (j = 0; j < 5; vrxq >>= 1, j++) {
 979                                 if (dev_info->max_rx_queues > vrxq) {
 980                                         if (vpool > vrxq)
 981                                                 vpool = vrxq;
 982                                         goto found;
 983                                 }
 984                         }
 985                         /* Not enough resources to support VMDq */
 986                         break;
 987                 }
 988         }
 989         /* Not enough resources to support VMDq */
 990         vpool = 0;
 991         vrxq = 0;
 992 found:
 993         dev_info->max_vmdq_pools = vpool;
 994         dev_info->vmdq_queue_num = vrxq;
 995
 996         dev_info->vmdq_pool_base = 0;
 997         dev_info->vmdq_queue_base = 0;
 998
 999         return 0;
1000 }
1001
1002 /* Configure the device based on the configuration provided */
1003 static int bnxt_dev_configure_op(struct rte_eth_dev *eth_dev)
1004 {
1005         struct bnxt *bp = eth_dev->data->dev_private;
1006         uint64_t rx_offloads = eth_dev->data->dev_conf.rxmode.offloads;
1007         int rc;
1008
1009         bp->rx_queues = (void *)eth_dev->data->rx_queues;
1010         bp->tx_queues = (void *)eth_dev->data->tx_queues;
1011         bp->tx_nr_rings = eth_dev->data->nb_tx_queues;
1012         bp->rx_nr_rings = eth_dev->data->nb_rx_queues;
1013
1014         rc = is_bnxt_in_error(bp);
1015         if (rc)
1016                 return rc;
1017
1018         if (BNXT_VF(bp) && (bp->flags & BNXT_FLAG_NEW_RM)) {
1019                 rc = bnxt_hwrm_check_vf_rings(bp);
1020                 if (rc) {
1021                         PMD_DRV_LOG(ERR, "HWRM insufficient resources\n");
1022                         return -ENOSPC;
1023                 }
1024
1025                 /* If a resource has already been allocated - in this case
1026                  * it is the async completion ring, free it. Reallocate it after
1027                  * resource reservation. This will ensure the resource counts
1028                  * are calculated correctly.
1029                  */
1030
1031                 pthread_mutex_lock(&bp->def_cp_lock);
1032
1033                 if (!BNXT_HAS_NQ(bp) && bp->async_cp_ring) {
1034                         bnxt_disable_int(bp);
1035                         bnxt_free_cp_ring(bp, bp->async_cp_ring);
1036                 }
1037
1038                 rc = bnxt_hwrm_func_reserve_vf_resc(bp, false);
1039                 if (rc) {
1040                         PMD_DRV_LOG(ERR, "HWRM resource alloc fail:%x\n", rc);
1041                         pthread_mutex_unlock(&bp->def_cp_lock);
1042                         return -ENOSPC;
1043                 }
1044
1045                 if (!BNXT_HAS_NQ(bp) && bp->async_cp_ring) {
1046                         rc = bnxt_alloc_async_cp_ring(bp);
1047                         if (rc) {
1048                                 pthread_mutex_unlock(&bp->def_cp_lock);
1049                                 return rc;
1050                         }
1051                         bnxt_enable_int(bp);
1052                 }
1053
1054                 pthread_mutex_unlock(&bp->def_cp_lock);
1055         } else {
1056                 /* legacy driver needs to get updated values */
1057                 rc = bnxt_hwrm_func_qcaps(bp);
1058                 if (rc) {
1059                         PMD_DRV_LOG(ERR, "hwrm func qcaps fail:%d\n", rc);
1060                         return rc;
1061                 }
1062         }
1063
1064         /* Inherit new configurations */
1065         if (eth_dev->data->nb_rx_queues > bp->max_rx_rings ||
1066             eth_dev->data->nb_tx_queues > bp->max_tx_rings ||
1067             eth_dev->data->nb_rx_queues + eth_dev->data->nb_tx_queues
1068                 + BNXT_NUM_ASYNC_CPR(bp) > bp->max_cp_rings ||
1069             eth_dev->data->nb_rx_queues + eth_dev->data->nb_tx_queues >
1070             bp->max_stat_ctx)
1071                 goto resource_error;
1072
1073         if (BNXT_HAS_RING_GRPS(bp) &&
1074             (uint32_t)(eth_dev->data->nb_rx_queues) > bp->max_ring_grps)
1075                 goto resource_error;
1076
1077         if (!(eth_dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_RSS) &&
1078             bp->max_vnics < eth_dev->data->nb_rx_queues)
1079                 goto resource_error;
1080
1081         bp->rx_cp_nr_rings = bp->rx_nr_rings;
1082         bp->tx_cp_nr_rings = bp->tx_nr_rings;
1083
1084         if (eth_dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG)
1085                 rx_offloads |= DEV_RX_OFFLOAD_RSS_HASH;
1086         eth_dev->data->dev_conf.rxmode.offloads = rx_offloads;
1087
1088         if (rx_offloads & DEV_RX_OFFLOAD_JUMBO_FRAME) {
1089                 eth_dev->data->mtu =
1090                         eth_dev->data->dev_conf.rxmode.max_rx_pkt_len -
1091                         RTE_ETHER_HDR_LEN - RTE_ETHER_CRC_LEN - VLAN_TAG_SIZE *
1092                         BNXT_NUM_VLANS;
1093                 bnxt_mtu_set_op(eth_dev, eth_dev->data->mtu);
1094         }
1095         return 0;
1096
1097 resource_error:
1098         PMD_DRV_LOG(ERR,
1099                     "Insufficient resources to support requested config\n");
1100         PMD_DRV_LOG(ERR,
1101                     "Num Queues Requested: Tx %d, Rx %d\n",
1102                     eth_dev->data->nb_tx_queues,
1103                     eth_dev->data->nb_rx_queues);
1104         PMD_DRV_LOG(ERR,
1105                     "MAX: TxQ %d, RxQ %d, CQ %d Stat %d, Grp %d, Vnic %d\n",
1106                     bp->max_tx_rings, bp->max_rx_rings, bp->max_cp_rings,
1107                     bp->max_stat_ctx, bp->max_ring_grps, bp->max_vnics);
1108         return -ENOSPC;
1109 }
1110
1111 void bnxt_print_link_info(struct rte_eth_dev *eth_dev)
1112 {
1113         struct rte_eth_link *link = &eth_dev->data->dev_link;
1114
1115         if (link->link_status)
1116                 PMD_DRV_LOG(INFO, "Port %d Link Up - speed %u Mbps - %s\n",
1117                         eth_dev->data->port_id,
1118                         (uint32_t)link->link_speed,
1119                         (link->link_duplex == ETH_LINK_FULL_DUPLEX) ?
1120                         ("full-duplex") : ("half-duplex\n"));
1121         else
1122                 PMD_DRV_LOG(INFO, "Port %d Link Down\n",
1123                         eth_dev->data->port_id);
1124 }
1125
1126 /*
1127  * Determine whether the current configuration requires support for scattered
1128  * receive; return 1 if scattered receive is required and 0 if not.
1129  */
1130 static int bnxt_scattered_rx(struct rte_eth_dev *eth_dev)
1131 {
1132         uint16_t buf_size;
1133         int i;
1134
1135         if (eth_dev->data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_SCATTER)
1136                 return 1;
1137
1138         for (i = 0; i < eth_dev->data->nb_rx_queues; i++) {
1139                 struct bnxt_rx_queue *rxq = eth_dev->data->rx_queues[i];
1140
1141                 buf_size = (uint16_t)(rte_pktmbuf_data_room_size(rxq->mb_pool) -
1142                                       RTE_PKTMBUF_HEADROOM);
1143                 if (eth_dev->data->dev_conf.rxmode.max_rx_pkt_len > buf_size)
1144                         return 1;
1145         }
1146         return 0;
1147 }
1148
1149 static eth_rx_burst_t
1150 bnxt_receive_function(struct rte_eth_dev *eth_dev)
1151 {
1152         struct bnxt *bp = eth_dev->data->dev_private;
1153
1154 #if defined(RTE_ARCH_X86) || defined(RTE_ARCH_ARM64)
1155 #ifndef RTE_LIBRTE_IEEE1588
1156         /*
1157          * Vector mode receive can be enabled only if scatter rx is not
1158          * in use and rx offloads are limited to VLAN stripping and
1159          * CRC stripping.
1160          */
1161         if (!eth_dev->data->scattered_rx &&
1162             !(eth_dev->data->dev_conf.rxmode.offloads &
1163               ~(DEV_RX_OFFLOAD_VLAN_STRIP |
1164                 DEV_RX_OFFLOAD_KEEP_CRC |
1165                 DEV_RX_OFFLOAD_JUMBO_FRAME |
1166                 DEV_RX_OFFLOAD_IPV4_CKSUM |
1167                 DEV_RX_OFFLOAD_UDP_CKSUM |
1168                 DEV_RX_OFFLOAD_TCP_CKSUM |
1169                 DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM |
1170                 DEV_RX_OFFLOAD_RSS_HASH |
1171                 DEV_RX_OFFLOAD_VLAN_FILTER)) &&
1172             !BNXT_TRUFLOW_EN(bp) && BNXT_NUM_ASYNC_CPR(bp)) {
1173                 PMD_DRV_LOG(INFO, "Using vector mode receive for port %d\n",
1174                             eth_dev->data->port_id);
1175                 bp->flags |= BNXT_FLAG_RX_VECTOR_PKT_MODE;
1176                 return bnxt_recv_pkts_vec;
1177         }
1178         PMD_DRV_LOG(INFO, "Vector mode receive disabled for port %d\n",
1179                     eth_dev->data->port_id);
1180         PMD_DRV_LOG(INFO,
1181                     "Port %d scatter: %d rx offload: %" PRIX64 "\n",
1182                     eth_dev->data->port_id,
1183                     eth_dev->data->scattered_rx,
1184                     eth_dev->data->dev_conf.rxmode.offloads);
1185 #endif
1186 #endif
1187         bp->flags &= ~BNXT_FLAG_RX_VECTOR_PKT_MODE;
1188         return bnxt_recv_pkts;
1189 }
1190
1191 static eth_tx_burst_t
1192 bnxt_transmit_function(__rte_unused struct rte_eth_dev *eth_dev)
1193 {
1194 #if defined(RTE_ARCH_X86) || defined(RTE_ARCH_ARM64)
1195 #ifndef RTE_LIBRTE_IEEE1588
1196         uint64_t offloads = eth_dev->data->dev_conf.txmode.offloads;
1197         struct bnxt *bp = eth_dev->data->dev_private;
1198
1199         /*
1200          * Vector mode transmit can be enabled only if not using scatter rx
1201          * or tx offloads.
1202          */
1203         if (!eth_dev->data->scattered_rx &&
1204             !(offloads & ~DEV_TX_OFFLOAD_MBUF_FAST_FREE) &&
1205             !BNXT_TRUFLOW_EN(bp)) {
1206                 PMD_DRV_LOG(INFO, "Using vector mode transmit for port %d\n",
1207                             eth_dev->data->port_id);
1208                 return bnxt_xmit_pkts_vec;
1209         }
1210         PMD_DRV_LOG(INFO, "Vector mode transmit disabled for port %d\n",
1211                     eth_dev->data->port_id);
1212         PMD_DRV_LOG(INFO,
1213                     "Port %d scatter: %d tx offload: %" PRIX64 "\n",
1214                     eth_dev->data->port_id,
1215                     eth_dev->data->scattered_rx,
1216                     offloads);
1217 #endif
1218 #endif
1219         return bnxt_xmit_pkts;
1220 }
1221
1222 static int bnxt_handle_if_change_status(struct bnxt *bp)
1223 {
1224         int rc;
1225
1226         /* Since fw has undergone a reset and lost all contexts,
1227          * set fatal flag to not issue hwrm during cleanup
1228          */
1229         bp->flags |= BNXT_FLAG_FATAL_ERROR;
1230         bnxt_uninit_resources(bp, true);
1231
1232         /* clear fatal flag so that re-init happens */
1233         bp->flags &= ~BNXT_FLAG_FATAL_ERROR;
1234         rc = bnxt_init_resources(bp, true);
1235
1236         bp->flags &= ~BNXT_FLAG_IF_CHANGE_HOT_FW_RESET_DONE;
1237
1238         return rc;
1239 }
1240
1241 static int bnxt_dev_start_op(struct rte_eth_dev *eth_dev)
1242 {
1243         struct bnxt *bp = eth_dev->data->dev_private;
1244         uint64_t rx_offloads = eth_dev->data->dev_conf.rxmode.offloads;
1245         int vlan_mask = 0;
1246         int rc, retry_cnt = BNXT_IF_CHANGE_RETRY_COUNT;
1247
1248         if (!eth_dev->data->nb_tx_queues || !eth_dev->data->nb_rx_queues) {
1249                 PMD_DRV_LOG(ERR, "Queues are not configured yet!\n");
1250                 return -EINVAL;
1251         }
1252
1253         if (bp->rx_cp_nr_rings > RTE_ETHDEV_QUEUE_STAT_CNTRS) {
1254                 PMD_DRV_LOG(ERR,
1255                         "RxQ cnt %d > CONFIG_RTE_ETHDEV_QUEUE_STAT_CNTRS %d\n",
1256                         bp->rx_cp_nr_rings, RTE_ETHDEV_QUEUE_STAT_CNTRS);
1257         }
1258
1259         do {
1260                 rc = bnxt_hwrm_if_change(bp, true);
1261                 if (rc == 0 || rc != -EAGAIN)
1262                         break;
1263
1264                 rte_delay_ms(BNXT_IF_CHANGE_RETRY_INTERVAL);
1265         } while (retry_cnt--);
1266
1267         if (rc)
1268                 return rc;
1269
1270         if (bp->flags & BNXT_FLAG_IF_CHANGE_HOT_FW_RESET_DONE) {
1271                 rc = bnxt_handle_if_change_status(bp);
1272                 if (rc)
1273                         return rc;
1274         }
1275
1276         bnxt_enable_int(bp);
1277
1278         rc = bnxt_init_chip(bp);
1279         if (rc)
1280                 goto error;
1281
1282         eth_dev->data->scattered_rx = bnxt_scattered_rx(eth_dev);
1283         eth_dev->data->dev_started = 1;
1284
1285         bnxt_link_update_op(eth_dev, 1);
1286
1287         if (rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER)
1288                 vlan_mask |= ETH_VLAN_FILTER_MASK;
1289         if (rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
1290                 vlan_mask |= ETH_VLAN_STRIP_MASK;
1291         rc = bnxt_vlan_offload_set_op(eth_dev, vlan_mask);
1292         if (rc)
1293                 goto error;
1294
1295         /* Initialize bnxt ULP port details */
1296         rc = bnxt_ulp_port_init(bp);
1297         if (rc)
1298                 goto error;
1299
1300         eth_dev->rx_pkt_burst = bnxt_receive_function(eth_dev);
1301         eth_dev->tx_pkt_burst = bnxt_transmit_function(eth_dev);
1302
1303         bnxt_schedule_fw_health_check(bp);
1304
1305         return 0;
1306
1307 error:
1308         bnxt_shutdown_nic(bp);
1309         bnxt_free_tx_mbufs(bp);
1310         bnxt_free_rx_mbufs(bp);
1311         bnxt_hwrm_if_change(bp, false);
1312         eth_dev->data->dev_started = 0;
1313         return rc;
1314 }
1315
1316 static int bnxt_dev_set_link_up_op(struct rte_eth_dev *eth_dev)
1317 {
1318         struct bnxt *bp = eth_dev->data->dev_private;
1319         int rc = 0;
1320
1321         if (!bp->link_info->link_up)
1322                 rc = bnxt_set_hwrm_link_config(bp, true);
1323         if (!rc)
1324                 eth_dev->data->dev_link.link_status = 1;
1325
1326         bnxt_print_link_info(eth_dev);
1327         return rc;
1328 }
1329
1330 static int bnxt_dev_set_link_down_op(struct rte_eth_dev *eth_dev)
1331 {
1332         struct bnxt *bp = eth_dev->data->dev_private;
1333
1334         eth_dev->data->dev_link.link_status = 0;
1335         bnxt_set_hwrm_link_config(bp, false);
1336         bp->link_info->link_up = 0;
1337
1338         return 0;
1339 }
1340
1341 static void bnxt_free_switch_domain(struct bnxt *bp)
1342 {
1343         if (bp->switch_domain_id)
1344                 rte_eth_switch_domain_free(bp->switch_domain_id);
1345 }
1346
1347 /* Unload the driver, release resources */
1348 static void bnxt_dev_stop_op(struct rte_eth_dev *eth_dev)
1349 {
1350         struct bnxt *bp = eth_dev->data->dev_private;
1351         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1352         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1353         struct rte_eth_link link;
1354
1355         eth_dev->data->dev_started = 0;
1356         eth_dev->data->scattered_rx = 0;
1357
1358         /* Prevent crashes when queues are still in use */
1359         eth_dev->rx_pkt_burst = &bnxt_dummy_recv_pkts;
1360         eth_dev->tx_pkt_burst = &bnxt_dummy_xmit_pkts;
1361
1362         bnxt_disable_int(bp);
1363
1364         /* disable uio/vfio intr/eventfd mapping */
1365         rte_intr_disable(intr_handle);
1366
1367         /* Stop the child representors for this device */
1368         bnxt_rep_stop_all(bp);
1369
1370         /* delete the bnxt ULP port details */
1371         bnxt_ulp_port_deinit(bp);
1372
1373         bnxt_cancel_fw_health_check(bp);
1374
1375         /* Do not bring link down during reset recovery */
1376         if (!is_bnxt_in_error(bp)) {
1377                 bnxt_dev_set_link_down_op(eth_dev);
1378                 /* Wait for link to be reset */
1379                 if (BNXT_SINGLE_PF(bp))
1380                         rte_delay_ms(500);
1381                 /* clear the recorded link status */
1382                 memset(&link, 0, sizeof(link));
1383                 rte_eth_linkstatus_set(eth_dev, &link);
1384         }
1385
1386         /* Clean queue intr-vector mapping */
1387         rte_intr_efd_disable(intr_handle);
1388         if (intr_handle->intr_vec != NULL) {
1389                 rte_free(intr_handle->intr_vec);
1390                 intr_handle->intr_vec = NULL;
1391         }
1392
1393         bnxt_hwrm_port_clr_stats(bp);
1394         bnxt_free_tx_mbufs(bp);
1395         bnxt_free_rx_mbufs(bp);
1396         /* Process any remaining notifications in default completion queue */
1397         bnxt_int_handler(eth_dev);
1398         bnxt_shutdown_nic(bp);
1399         bnxt_hwrm_if_change(bp, false);
1400
1401         rte_free(bp->mark_table);
1402         bp->mark_table = NULL;
1403
1404         bp->flags &= ~BNXT_FLAG_RX_VECTOR_PKT_MODE;
1405         bp->rx_cosq_cnt = 0;
1406         /* All filters are deleted on a port stop. */
1407         if (BNXT_FLOW_XSTATS_EN(bp))
1408                 bp->flow_stat->flow_count = 0;
1409 }
1410
1411 static int bnxt_dev_close_op(struct rte_eth_dev *eth_dev)
1412 {
1413         struct bnxt *bp = eth_dev->data->dev_private;
1414
1415         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1416                 return 0;
1417
1418         /* cancel the recovery handler before remove dev */
1419         rte_eal_alarm_cancel(bnxt_dev_reset_and_resume, (void *)bp);
1420         rte_eal_alarm_cancel(bnxt_dev_recover, (void *)bp);
1421         bnxt_cancel_fc_thread(bp);
1422
1423         if (eth_dev->data->dev_started)
1424                 bnxt_dev_stop_op(eth_dev);
1425
1426         bnxt_free_switch_domain(bp);
1427
1428         bnxt_uninit_resources(bp, false);
1429
1430         bnxt_free_leds_info(bp);
1431         bnxt_free_cos_queues(bp);
1432         bnxt_free_link_info(bp);
1433         bnxt_free_pf_info(bp);
1434         bnxt_free_parent_info(bp);
1435
1436         eth_dev->dev_ops = NULL;
1437         eth_dev->rx_pkt_burst = NULL;
1438         eth_dev->tx_pkt_burst = NULL;
1439
1440         rte_memzone_free((const struct rte_memzone *)bp->tx_mem_zone);
1441         bp->tx_mem_zone = NULL;
1442         rte_memzone_free((const struct rte_memzone *)bp->rx_mem_zone);
1443         bp->rx_mem_zone = NULL;
1444
1445         bnxt_hwrm_free_vf_info(bp);
1446
1447         rte_free(bp->grp_info);
1448         bp->grp_info = NULL;
1449
1450         return 0;
1451 }
1452
1453 static void bnxt_mac_addr_remove_op(struct rte_eth_dev *eth_dev,
1454                                     uint32_t index)
1455 {
1456         struct bnxt *bp = eth_dev->data->dev_private;
1457         uint64_t pool_mask = eth_dev->data->mac_pool_sel[index];
1458         struct bnxt_vnic_info *vnic;
1459         struct bnxt_filter_info *filter, *temp_filter;
1460         uint32_t i;
1461
1462         if (is_bnxt_in_error(bp))
1463                 return;
1464
1465         /*
1466          * Loop through all VNICs from the specified filter flow pools to
1467          * remove the corresponding MAC addr filter
1468          */
1469         for (i = 0; i < bp->nr_vnics; i++) {
1470                 if (!(pool_mask & (1ULL << i)))
1471                         continue;
1472
1473                 vnic = &bp->vnic_info[i];
1474                 filter = STAILQ_FIRST(&vnic->filter);
1475                 while (filter) {
1476                         temp_filter = STAILQ_NEXT(filter, next);
1477                         if (filter->mac_index == index) {
1478                                 STAILQ_REMOVE(&vnic->filter, filter,
1479                                                 bnxt_filter_info, next);
1480                                 bnxt_hwrm_clear_l2_filter(bp, filter);
1481                                 bnxt_free_filter(bp, filter);
1482                         }
1483                         filter = temp_filter;
1484                 }
1485         }
1486 }
1487
1488 static int bnxt_add_mac_filter(struct bnxt *bp, struct bnxt_vnic_info *vnic,
1489                                struct rte_ether_addr *mac_addr, uint32_t index,
1490                                uint32_t pool)
1491 {
1492         struct bnxt_filter_info *filter;
1493         int rc = 0;
1494
1495         /* Attach requested MAC address to the new l2_filter */
1496         STAILQ_FOREACH(filter, &vnic->filter, next) {
1497                 if (filter->mac_index == index) {
1498                         PMD_DRV_LOG(DEBUG,
1499                                     "MAC addr already existed for pool %d\n",
1500                                     pool);
1501                         return 0;
1502                 }
1503         }
1504
1505         filter = bnxt_alloc_filter(bp);
1506         if (!filter) {
1507                 PMD_DRV_LOG(ERR, "L2 filter alloc failed\n");
1508                 return -ENODEV;
1509         }
1510
1511         /* bnxt_alloc_filter copies default MAC to filter->l2_addr. So,
1512          * if the MAC that's been programmed now is a different one, then,
1513          * copy that addr to filter->l2_addr
1514          */
1515         if (mac_addr)
1516                 memcpy(filter->l2_addr, mac_addr, RTE_ETHER_ADDR_LEN);
1517         filter->flags |= HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_OUTERMOST;
1518
1519         rc = bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id, filter);
1520         if (!rc) {
1521                 filter->mac_index = index;
1522                 if (filter->mac_index == 0)
1523                         STAILQ_INSERT_HEAD(&vnic->filter, filter, next);
1524                 else
1525                         STAILQ_INSERT_TAIL(&vnic->filter, filter, next);
1526         } else {
1527                 bnxt_free_filter(bp, filter);
1528         }
1529
1530         return rc;
1531 }
1532
1533 static int bnxt_mac_addr_add_op(struct rte_eth_dev *eth_dev,
1534                                 struct rte_ether_addr *mac_addr,
1535                                 uint32_t index, uint32_t pool)
1536 {
1537         struct bnxt *bp = eth_dev->data->dev_private;
1538         struct bnxt_vnic_info *vnic = &bp->vnic_info[pool];
1539         int rc = 0;
1540
1541         rc = is_bnxt_in_error(bp);
1542         if (rc)
1543                 return rc;
1544
1545         if (BNXT_VF(bp) & !BNXT_VF_IS_TRUSTED(bp)) {
1546                 PMD_DRV_LOG(ERR, "Cannot add MAC address to a VF interface\n");
1547                 return -ENOTSUP;
1548         }
1549
1550         if (!vnic) {
1551                 PMD_DRV_LOG(ERR, "VNIC not found for pool %d!\n", pool);
1552                 return -EINVAL;
1553         }
1554
1555         /* Filter settings will get applied when port is started */
1556         if (!eth_dev->data->dev_started)
1557                 return 0;
1558
1559         rc = bnxt_add_mac_filter(bp, vnic, mac_addr, index, pool);
1560
1561         return rc;
1562 }
1563
1564 int bnxt_link_update_op(struct rte_eth_dev *eth_dev, int wait_to_complete)
1565 {
1566         int rc = 0;
1567         struct bnxt *bp = eth_dev->data->dev_private;
1568         struct rte_eth_link new;
1569         int cnt = wait_to_complete ? BNXT_MAX_LINK_WAIT_CNT :
1570                         BNXT_MIN_LINK_WAIT_CNT;
1571
1572         rc = is_bnxt_in_error(bp);
1573         if (rc)
1574                 return rc;
1575
1576         memset(&new, 0, sizeof(new));
1577         do {
1578                 /* Retrieve link info from hardware */
1579                 rc = bnxt_get_hwrm_link_config(bp, &new);
1580                 if (rc) {
1581                         new.link_speed = ETH_LINK_SPEED_100M;
1582                         new.link_duplex = ETH_LINK_FULL_DUPLEX;
1583                         PMD_DRV_LOG(ERR,
1584                                 "Failed to retrieve link rc = 0x%x!\n", rc);
1585                         goto out;
1586                 }
1587
1588                 if (!wait_to_complete || new.link_status)
1589                         break;
1590
1591                 rte_delay_ms(BNXT_LINK_WAIT_INTERVAL);
1592         } while (cnt--);
1593
1594         /* Only single function PF can bring phy down.
1595          * When port is stopped, report link down for VF/MH/NPAR functions.
1596          */
1597         if (!BNXT_SINGLE_PF(bp) && !eth_dev->data->dev_started)
1598                 memset(&new, 0, sizeof(new));
1599
1600 out:
1601         /* Timed out or success */
1602         if (new.link_status != eth_dev->data->dev_link.link_status ||
1603         new.link_speed != eth_dev->data->dev_link.link_speed) {
1604                 rte_eth_linkstatus_set(eth_dev, &new);
1605
1606                 rte_eth_dev_callback_process(eth_dev,
1607                                              RTE_ETH_EVENT_INTR_LSC,
1608                                              NULL);
1609
1610                 bnxt_print_link_info(eth_dev);
1611         }
1612
1613         return rc;
1614 }
1615
1616 static int bnxt_promiscuous_enable_op(struct rte_eth_dev *eth_dev)
1617 {
1618         struct bnxt *bp = eth_dev->data->dev_private;
1619         struct bnxt_vnic_info *vnic;
1620         uint32_t old_flags;
1621         int rc;
1622
1623         rc = is_bnxt_in_error(bp);
1624         if (rc)
1625                 return rc;
1626
1627         /* Filter settings will get applied when port is started */
1628         if (!eth_dev->data->dev_started)
1629                 return 0;
1630
1631         if (bp->vnic_info == NULL)
1632                 return 0;
1633
1634         vnic = BNXT_GET_DEFAULT_VNIC(bp);
1635
1636         old_flags = vnic->flags;
1637         vnic->flags |= BNXT_VNIC_INFO_PROMISC;
1638         rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1639         if (rc != 0)
1640                 vnic->flags = old_flags;
1641
1642         return rc;
1643 }
1644
1645 static int bnxt_promiscuous_disable_op(struct rte_eth_dev *eth_dev)
1646 {
1647         struct bnxt *bp = eth_dev->data->dev_private;
1648         struct bnxt_vnic_info *vnic;
1649         uint32_t old_flags;
1650         int rc;
1651
1652         rc = is_bnxt_in_error(bp);
1653         if (rc)
1654                 return rc;
1655
1656         /* Filter settings will get applied when port is started */
1657         if (!eth_dev->data->dev_started)
1658                 return 0;
1659
1660         if (bp->vnic_info == NULL)
1661                 return 0;
1662
1663         vnic = BNXT_GET_DEFAULT_VNIC(bp);
1664
1665         old_flags = vnic->flags;
1666         vnic->flags &= ~BNXT_VNIC_INFO_PROMISC;
1667         rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1668         if (rc != 0)
1669                 vnic->flags = old_flags;
1670
1671         return rc;
1672 }
1673
1674 static int bnxt_allmulticast_enable_op(struct rte_eth_dev *eth_dev)
1675 {
1676         struct bnxt *bp = eth_dev->data->dev_private;
1677         struct bnxt_vnic_info *vnic;
1678         uint32_t old_flags;
1679         int rc;
1680
1681         rc = is_bnxt_in_error(bp);
1682         if (rc)
1683                 return rc;
1684
1685         /* Filter settings will get applied when port is started */
1686         if (!eth_dev->data->dev_started)
1687                 return 0;
1688
1689         if (bp->vnic_info == NULL)
1690                 return 0;
1691
1692         vnic = BNXT_GET_DEFAULT_VNIC(bp);
1693
1694         old_flags = vnic->flags;
1695         vnic->flags |= BNXT_VNIC_INFO_ALLMULTI;
1696         rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1697         if (rc != 0)
1698                 vnic->flags = old_flags;
1699
1700         return rc;
1701 }
1702
1703 static int bnxt_allmulticast_disable_op(struct rte_eth_dev *eth_dev)
1704 {
1705         struct bnxt *bp = eth_dev->data->dev_private;
1706         struct bnxt_vnic_info *vnic;
1707         uint32_t old_flags;
1708         int rc;
1709
1710         rc = is_bnxt_in_error(bp);
1711         if (rc)
1712                 return rc;
1713
1714         /* Filter settings will get applied when port is started */
1715         if (!eth_dev->data->dev_started)
1716                 return 0;
1717
1718         if (bp->vnic_info == NULL)
1719                 return 0;
1720
1721         vnic = BNXT_GET_DEFAULT_VNIC(bp);
1722
1723         old_flags = vnic->flags;
1724         vnic->flags &= ~BNXT_VNIC_INFO_ALLMULTI;
1725         rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1726         if (rc != 0)
1727                 vnic->flags = old_flags;
1728
1729         return rc;
1730 }
1731
1732 /* Return bnxt_rx_queue pointer corresponding to a given rxq. */
1733 static struct bnxt_rx_queue *bnxt_qid_to_rxq(struct bnxt *bp, uint16_t qid)
1734 {
1735         if (qid >= bp->rx_nr_rings)
1736                 return NULL;
1737
1738         return bp->eth_dev->data->rx_queues[qid];
1739 }
1740
1741 /* Return rxq corresponding to a given rss table ring/group ID. */
1742 static uint16_t bnxt_rss_to_qid(struct bnxt *bp, uint16_t fwr)
1743 {
1744         struct bnxt_rx_queue *rxq;
1745         unsigned int i;
1746
1747         if (!BNXT_HAS_RING_GRPS(bp)) {
1748                 for (i = 0; i < bp->rx_nr_rings; i++) {
1749                         rxq = bp->eth_dev->data->rx_queues[i];
1750                         if (rxq->rx_ring->rx_ring_struct->fw_ring_id == fwr)
1751                                 return rxq->index;
1752                 }
1753         } else {
1754                 for (i = 0; i < bp->rx_nr_rings; i++) {
1755                         if (bp->grp_info[i].fw_grp_id == fwr)
1756                                 return i;
1757                 }
1758         }
1759
1760         return INVALID_HW_RING_ID;
1761 }
1762
1763 static int bnxt_reta_update_op(struct rte_eth_dev *eth_dev,
1764                             struct rte_eth_rss_reta_entry64 *reta_conf,
1765                             uint16_t reta_size)
1766 {
1767         struct bnxt *bp = eth_dev->data->dev_private;
1768         struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
1769         struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp);
1770         uint16_t tbl_size = bnxt_rss_hash_tbl_size(bp);
1771         uint16_t idx, sft;
1772         int i, rc;
1773
1774         rc = is_bnxt_in_error(bp);
1775         if (rc)
1776                 return rc;
1777
1778         if (!vnic->rss_table)
1779                 return -EINVAL;
1780
1781         if (!(dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG))
1782                 return -EINVAL;
1783
1784         if (reta_size != tbl_size) {
1785                 PMD_DRV_LOG(ERR, "The configured hash table lookup size "
1786                         "(%d) must equal the size supported by the hardware "
1787                         "(%d)\n", reta_size, tbl_size);
1788                 return -EINVAL;
1789         }
1790
1791         for (i = 0; i < reta_size; i++) {
1792                 struct bnxt_rx_queue *rxq;
1793
1794                 idx = i / RTE_RETA_GROUP_SIZE;
1795                 sft = i % RTE_RETA_GROUP_SIZE;
1796
1797                 if (!(reta_conf[idx].mask & (1ULL << sft)))
1798                         continue;
1799
1800                 rxq = bnxt_qid_to_rxq(bp, reta_conf[idx].reta[sft]);
1801                 if (!rxq) {
1802                         PMD_DRV_LOG(ERR, "Invalid ring in reta_conf.\n");
1803                         return -EINVAL;
1804                 }
1805
1806                 if (BNXT_CHIP_THOR(bp)) {
1807                         vnic->rss_table[i * 2] =
1808                                 rxq->rx_ring->rx_ring_struct->fw_ring_id;
1809                         vnic->rss_table[i * 2 + 1] =
1810                                 rxq->cp_ring->cp_ring_struct->fw_ring_id;
1811                 } else {
1812                         vnic->rss_table[i] =
1813                             vnic->fw_grp_ids[reta_conf[idx].reta[sft]];
1814                 }
1815         }
1816
1817         bnxt_hwrm_vnic_rss_cfg(bp, vnic);
1818         return 0;
1819 }
1820
1821 static int bnxt_reta_query_op(struct rte_eth_dev *eth_dev,
1822                               struct rte_eth_rss_reta_entry64 *reta_conf,
1823                               uint16_t reta_size)
1824 {
1825         struct bnxt *bp = eth_dev->data->dev_private;
1826         struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp);
1827         uint16_t tbl_size = bnxt_rss_hash_tbl_size(bp);
1828         uint16_t idx, sft, i;
1829         int rc;
1830
1831         rc = is_bnxt_in_error(bp);
1832         if (rc)
1833                 return rc;
1834
1835         /* Retrieve from the default VNIC */
1836         if (!vnic)
1837                 return -EINVAL;
1838         if (!vnic->rss_table)
1839                 return -EINVAL;
1840
1841         if (reta_size != tbl_size) {
1842                 PMD_DRV_LOG(ERR, "The configured hash table lookup size "
1843                         "(%d) must equal the size supported by the hardware "
1844                         "(%d)\n", reta_size, tbl_size);
1845                 return -EINVAL;
1846         }
1847
1848         for (idx = 0, i = 0; i < reta_size; i++) {
1849                 idx = i / RTE_RETA_GROUP_SIZE;
1850                 sft = i % RTE_RETA_GROUP_SIZE;
1851
1852                 if (reta_conf[idx].mask & (1ULL << sft)) {
1853                         uint16_t qid;
1854
1855                         if (BNXT_CHIP_THOR(bp))
1856                                 qid = bnxt_rss_to_qid(bp,
1857                                                       vnic->rss_table[i * 2]);
1858                         else
1859                                 qid = bnxt_rss_to_qid(bp, vnic->rss_table[i]);
1860
1861                         if (qid == INVALID_HW_RING_ID) {
1862                                 PMD_DRV_LOG(ERR, "Inv. entry in rss table.\n");
1863                                 return -EINVAL;
1864                         }
1865                         reta_conf[idx].reta[sft] = qid;
1866                 }
1867         }
1868
1869         return 0;
1870 }
1871
1872 static int bnxt_rss_hash_update_op(struct rte_eth_dev *eth_dev,
1873                                    struct rte_eth_rss_conf *rss_conf)
1874 {
1875         struct bnxt *bp = eth_dev->data->dev_private;
1876         struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
1877         struct bnxt_vnic_info *vnic;
1878         int rc;
1879
1880         rc = is_bnxt_in_error(bp);
1881         if (rc)
1882                 return rc;
1883
1884         /*
1885          * If RSS enablement were different than dev_configure,
1886          * then return -EINVAL
1887          */
1888         if (dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG) {
1889                 if (!rss_conf->rss_hf)
1890                         PMD_DRV_LOG(ERR, "Hash type NONE\n");
1891         } else {
1892                 if (rss_conf->rss_hf & BNXT_ETH_RSS_SUPPORT)
1893                         return -EINVAL;
1894         }
1895
1896         bp->flags |= BNXT_FLAG_UPDATE_HASH;
1897         memcpy(&eth_dev->data->dev_conf.rx_adv_conf.rss_conf,
1898                rss_conf,
1899                sizeof(*rss_conf));
1900
1901         /* Update the default RSS VNIC(s) */
1902         vnic = BNXT_GET_DEFAULT_VNIC(bp);
1903         vnic->hash_type = bnxt_rte_to_hwrm_hash_types(rss_conf->rss_hf);
1904         vnic->hash_mode =
1905                 bnxt_rte_to_hwrm_hash_level(bp, rss_conf->rss_hf,
1906                                             ETH_RSS_LEVEL(rss_conf->rss_hf));
1907
1908         /*
1909          * If hashkey is not specified, use the previously configured
1910          * hashkey
1911          */
1912         if (!rss_conf->rss_key)
1913                 goto rss_config;
1914
1915         if (rss_conf->rss_key_len != HW_HASH_KEY_SIZE) {
1916                 PMD_DRV_LOG(ERR,
1917                             "Invalid hashkey length, should be 16 bytes\n");
1918                 return -EINVAL;
1919         }
1920         memcpy(vnic->rss_hash_key, rss_conf->rss_key, rss_conf->rss_key_len);
1921
1922 rss_config:
1923         bnxt_hwrm_vnic_rss_cfg(bp, vnic);
1924         return 0;
1925 }
1926
1927 static int bnxt_rss_hash_conf_get_op(struct rte_eth_dev *eth_dev,
1928                                      struct rte_eth_rss_conf *rss_conf)
1929 {
1930         struct bnxt *bp = eth_dev->data->dev_private;
1931         struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp);
1932         int len, rc;
1933         uint32_t hash_types;
1934
1935         rc = is_bnxt_in_error(bp);
1936         if (rc)
1937                 return rc;
1938
1939         /* RSS configuration is the same for all VNICs */
1940         if (vnic && vnic->rss_hash_key) {
1941                 if (rss_conf->rss_key) {
1942                         len = rss_conf->rss_key_len <= HW_HASH_KEY_SIZE ?
1943                               rss_conf->rss_key_len : HW_HASH_KEY_SIZE;
1944                         memcpy(rss_conf->rss_key, vnic->rss_hash_key, len);
1945                 }
1946
1947                 hash_types = vnic->hash_type;
1948                 rss_conf->rss_hf = 0;
1949                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV4) {
1950                         rss_conf->rss_hf |= ETH_RSS_IPV4;
1951                         hash_types &= ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV4;
1952                 }
1953                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV4) {
1954                         rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP;
1955                         hash_types &=
1956                                 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV4;
1957                 }
1958                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV4) {
1959                         rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
1960                         hash_types &=
1961                                 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV4;
1962                 }
1963                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6) {
1964                         rss_conf->rss_hf |= ETH_RSS_IPV6;
1965                         hash_types &= ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6;
1966                 }
1967                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV6) {
1968                         rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV6_TCP;
1969                         hash_types &=
1970                                 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV6;
1971                 }
1972                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV6) {
1973                         rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;
1974                         hash_types &=
1975                                 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV6;
1976                 }
1977
1978                 rss_conf->rss_hf |=
1979                         bnxt_hwrm_to_rte_rss_level(bp, vnic->hash_mode);
1980
1981                 if (hash_types) {
1982                         PMD_DRV_LOG(ERR,
1983                                 "Unknown RSS config from firmware (%08x), RSS disabled",
1984                                 vnic->hash_type);
1985                         return -ENOTSUP;
1986                 }
1987         } else {
1988                 rss_conf->rss_hf = 0;
1989         }
1990         return 0;
1991 }
1992
1993 static int bnxt_flow_ctrl_get_op(struct rte_eth_dev *dev,
1994                                struct rte_eth_fc_conf *fc_conf)
1995 {
1996         struct bnxt *bp = dev->data->dev_private;
1997         struct rte_eth_link link_info;
1998         int rc;
1999
2000         rc = is_bnxt_in_error(bp);
2001         if (rc)
2002                 return rc;
2003
2004         rc = bnxt_get_hwrm_link_config(bp, &link_info);
2005         if (rc)
2006                 return rc;
2007
2008         memset(fc_conf, 0, sizeof(*fc_conf));
2009         if (bp->link_info->auto_pause)
2010                 fc_conf->autoneg = 1;
2011         switch (bp->link_info->pause) {
2012         case 0:
2013                 fc_conf->mode = RTE_FC_NONE;
2014                 break;
2015         case HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_TX:
2016                 fc_conf->mode = RTE_FC_TX_PAUSE;
2017                 break;
2018         case HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_RX:
2019                 fc_conf->mode = RTE_FC_RX_PAUSE;
2020                 break;
2021         case (HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_TX |
2022                         HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_RX):
2023                 fc_conf->mode = RTE_FC_FULL;
2024                 break;
2025         }
2026         return 0;
2027 }
2028
2029 static int bnxt_flow_ctrl_set_op(struct rte_eth_dev *dev,
2030                                struct rte_eth_fc_conf *fc_conf)
2031 {
2032         struct bnxt *bp = dev->data->dev_private;
2033         int rc;
2034
2035         rc = is_bnxt_in_error(bp);
2036         if (rc)
2037                 return rc;
2038
2039         if (!BNXT_SINGLE_PF(bp) || BNXT_VF(bp)) {
2040                 PMD_DRV_LOG(ERR, "Flow Control Settings cannot be modified\n");
2041                 return -ENOTSUP;
2042         }
2043
2044         switch (fc_conf->mode) {
2045         case RTE_FC_NONE:
2046                 bp->link_info->auto_pause = 0;
2047                 bp->link_info->force_pause = 0;
2048                 break;
2049         case RTE_FC_RX_PAUSE:
2050                 if (fc_conf->autoneg) {
2051                         bp->link_info->auto_pause =
2052                                         HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_RX;
2053                         bp->link_info->force_pause = 0;
2054                 } else {
2055                         bp->link_info->auto_pause = 0;
2056                         bp->link_info->force_pause =
2057                                         HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_RX;
2058                 }
2059                 break;
2060         case RTE_FC_TX_PAUSE:
2061                 if (fc_conf->autoneg) {
2062                         bp->link_info->auto_pause =
2063                                         HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_TX;
2064                         bp->link_info->force_pause = 0;
2065                 } else {
2066                         bp->link_info->auto_pause = 0;
2067                         bp->link_info->force_pause =
2068                                         HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_TX;
2069                 }
2070                 break;
2071         case RTE_FC_FULL:
2072                 if (fc_conf->autoneg) {
2073                         bp->link_info->auto_pause =
2074                                         HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_TX |
2075                                         HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_RX;
2076                         bp->link_info->force_pause = 0;
2077                 } else {
2078                         bp->link_info->auto_pause = 0;
2079                         bp->link_info->force_pause =
2080                                         HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_TX |
2081                                         HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_RX;
2082                 }
2083                 break;
2084         }
2085         return bnxt_set_hwrm_link_config(bp, true);
2086 }
2087
2088 /* Add UDP tunneling port */
2089 static int
2090 bnxt_udp_tunnel_port_add_op(struct rte_eth_dev *eth_dev,
2091                          struct rte_eth_udp_tunnel *udp_tunnel)
2092 {
2093         struct bnxt *bp = eth_dev->data->dev_private;
2094         uint16_t tunnel_type = 0;
2095         int rc = 0;
2096
2097         rc = is_bnxt_in_error(bp);
2098         if (rc)
2099                 return rc;
2100
2101         switch (udp_tunnel->prot_type) {
2102         case RTE_TUNNEL_TYPE_VXLAN:
2103                 if (bp->vxlan_port_cnt) {
2104                         PMD_DRV_LOG(ERR, "Tunnel Port %d already programmed\n",
2105                                 udp_tunnel->udp_port);
2106                         if (bp->vxlan_port != udp_tunnel->udp_port) {
2107                                 PMD_DRV_LOG(ERR, "Only one port allowed\n");
2108                                 return -ENOSPC;
2109                         }
2110                         bp->vxlan_port_cnt++;
2111                         return 0;
2112                 }
2113                 tunnel_type =
2114                         HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_VXLAN;
2115                 bp->vxlan_port_cnt++;
2116                 break;
2117         case RTE_TUNNEL_TYPE_GENEVE:
2118                 if (bp->geneve_port_cnt) {
2119                         PMD_DRV_LOG(ERR, "Tunnel Port %d already programmed\n",
2120                                 udp_tunnel->udp_port);
2121                         if (bp->geneve_port != udp_tunnel->udp_port) {
2122                                 PMD_DRV_LOG(ERR, "Only one port allowed\n");
2123                                 return -ENOSPC;
2124                         }
2125                         bp->geneve_port_cnt++;
2126                         return 0;
2127                 }
2128                 tunnel_type =
2129                         HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_GENEVE;
2130                 bp->geneve_port_cnt++;
2131                 break;
2132         default:
2133                 PMD_DRV_LOG(ERR, "Tunnel type is not supported\n");
2134                 return -ENOTSUP;
2135         }
2136         rc = bnxt_hwrm_tunnel_dst_port_alloc(bp, udp_tunnel->udp_port,
2137                                              tunnel_type);
2138         return rc;
2139 }
2140
2141 static int
2142 bnxt_udp_tunnel_port_del_op(struct rte_eth_dev *eth_dev,
2143                          struct rte_eth_udp_tunnel *udp_tunnel)
2144 {
2145         struct bnxt *bp = eth_dev->data->dev_private;
2146         uint16_t tunnel_type = 0;
2147         uint16_t port = 0;
2148         int rc = 0;
2149
2150         rc = is_bnxt_in_error(bp);
2151         if (rc)
2152                 return rc;
2153
2154         switch (udp_tunnel->prot_type) {
2155         case RTE_TUNNEL_TYPE_VXLAN:
2156                 if (!bp->vxlan_port_cnt) {
2157                         PMD_DRV_LOG(ERR, "No Tunnel port configured yet\n");
2158                         return -EINVAL;
2159                 }
2160                 if (bp->vxlan_port != udp_tunnel->udp_port) {
2161                         PMD_DRV_LOG(ERR, "Req Port: %d. Configured port: %d\n",
2162                                 udp_tunnel->udp_port, bp->vxlan_port);
2163                         return -EINVAL;
2164                 }
2165                 if (--bp->vxlan_port_cnt)
2166                         return 0;
2167
2168                 tunnel_type =
2169                         HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN;
2170                 port = bp->vxlan_fw_dst_port_id;
2171                 break;
2172         case RTE_TUNNEL_TYPE_GENEVE:
2173                 if (!bp->geneve_port_cnt) {
2174                         PMD_DRV_LOG(ERR, "No Tunnel port configured yet\n");
2175                         return -EINVAL;
2176                 }
2177                 if (bp->geneve_port != udp_tunnel->udp_port) {
2178                         PMD_DRV_LOG(ERR, "Req Port: %d. Configured port: %d\n",
2179                                 udp_tunnel->udp_port, bp->geneve_port);
2180                         return -EINVAL;
2181                 }
2182                 if (--bp->geneve_port_cnt)
2183                         return 0;
2184
2185                 tunnel_type =
2186                         HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_GENEVE;
2187                 port = bp->geneve_fw_dst_port_id;
2188                 break;
2189         default:
2190                 PMD_DRV_LOG(ERR, "Tunnel type is not supported\n");
2191                 return -ENOTSUP;
2192         }
2193
2194         rc = bnxt_hwrm_tunnel_dst_port_free(bp, port, tunnel_type);
2195         if (!rc) {
2196                 if (tunnel_type ==
2197                     HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN)
2198                         bp->vxlan_port = 0;
2199                 if (tunnel_type ==
2200                     HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_GENEVE)
2201                         bp->geneve_port = 0;
2202         }
2203         return rc;
2204 }
2205
2206 static int bnxt_del_vlan_filter(struct bnxt *bp, uint16_t vlan_id)
2207 {
2208         struct bnxt_filter_info *filter;
2209         struct bnxt_vnic_info *vnic;
2210         int rc = 0;
2211         uint32_t chk = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN;
2212
2213         vnic = BNXT_GET_DEFAULT_VNIC(bp);
2214         filter = STAILQ_FIRST(&vnic->filter);
2215         while (filter) {
2216                 /* Search for this matching MAC+VLAN filter */
2217                 if (bnxt_vlan_filter_exists(bp, filter, chk, vlan_id)) {
2218                         /* Delete the filter */
2219                         rc = bnxt_hwrm_clear_l2_filter(bp, filter);
2220                         if (rc)
2221                                 return rc;
2222                         STAILQ_REMOVE(&vnic->filter, filter,
2223                                       bnxt_filter_info, next);
2224                         bnxt_free_filter(bp, filter);
2225                         PMD_DRV_LOG(INFO,
2226                                     "Deleted vlan filter for %d\n",
2227                                     vlan_id);
2228                         return 0;
2229                 }
2230                 filter = STAILQ_NEXT(filter, next);
2231         }
2232         return -ENOENT;
2233 }
2234
2235 static int bnxt_add_vlan_filter(struct bnxt *bp, uint16_t vlan_id)
2236 {
2237         struct bnxt_filter_info *filter;
2238         struct bnxt_vnic_info *vnic;
2239         int rc = 0;
2240         uint32_t en = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN |
2241                 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN_MASK;
2242         uint32_t chk = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN;
2243
2244         /* Implementation notes on the use of VNIC in this command:
2245          *
2246          * By default, these filters belong to default vnic for the function.
2247          * Once these filters are set up, only destination VNIC can be modified.
2248          * If the destination VNIC is not specified in this command,
2249          * then the HWRM shall only create an l2 context id.
2250          */
2251
2252         vnic = BNXT_GET_DEFAULT_VNIC(bp);
2253         filter = STAILQ_FIRST(&vnic->filter);
2254         /* Check if the VLAN has already been added */
2255         while (filter) {
2256                 if (bnxt_vlan_filter_exists(bp, filter, chk, vlan_id))
2257                         return -EEXIST;
2258
2259                 filter = STAILQ_NEXT(filter, next);
2260         }
2261
2262         /* No match found. Alloc a fresh filter and issue the L2_FILTER_ALLOC
2263          * command to create MAC+VLAN filter with the right flags, enables set.
2264          */
2265         filter = bnxt_alloc_filter(bp);
2266         if (!filter) {
2267                 PMD_DRV_LOG(ERR,
2268                             "MAC/VLAN filter alloc failed\n");
2269                 return -ENOMEM;
2270         }
2271         /* MAC + VLAN ID filter */
2272         /* If l2_ivlan == 0 and l2_ivlan_mask != 0, only
2273          * untagged packets are received
2274          *
2275          * If l2_ivlan != 0 and l2_ivlan_mask != 0, untagged
2276          * packets and only the programmed vlan's packets are received
2277          */
2278         filter->l2_ivlan = vlan_id;
2279         filter->l2_ivlan_mask = 0x0FFF;
2280         filter->enables |= en;
2281         filter->flags |= HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_OUTERMOST;
2282
2283         rc = bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id, filter);
2284         if (rc) {
2285                 /* Free the newly allocated filter as we were
2286                  * not able to create the filter in hardware.
2287                  */
2288                 bnxt_free_filter(bp, filter);
2289                 return rc;
2290         }
2291
2292         filter->mac_index = 0;
2293         /* Add this new filter to the list */
2294         if (vlan_id == 0)
2295                 STAILQ_INSERT_HEAD(&vnic->filter, filter, next);
2296         else
2297                 STAILQ_INSERT_TAIL(&vnic->filter, filter, next);
2298
2299         PMD_DRV_LOG(INFO,
2300                     "Added Vlan filter for %d\n", vlan_id);
2301         return rc;
2302 }
2303
2304 static int bnxt_vlan_filter_set_op(struct rte_eth_dev *eth_dev,
2305                 uint16_t vlan_id, int on)
2306 {
2307         struct bnxt *bp = eth_dev->data->dev_private;
2308         int rc;
2309
2310         rc = is_bnxt_in_error(bp);
2311         if (rc)
2312                 return rc;
2313
2314         if (!eth_dev->data->dev_started) {
2315                 PMD_DRV_LOG(ERR, "port must be started before setting vlan\n");
2316                 return -EINVAL;
2317         }
2318
2319         /* These operations apply to ALL existing MAC/VLAN filters */
2320         if (on)
2321                 return bnxt_add_vlan_filter(bp, vlan_id);
2322         else
2323                 return bnxt_del_vlan_filter(bp, vlan_id);
2324 }
2325
2326 static int bnxt_del_dflt_mac_filter(struct bnxt *bp,
2327                                     struct bnxt_vnic_info *vnic)
2328 {
2329         struct bnxt_filter_info *filter;
2330         int rc;
2331
2332         filter = STAILQ_FIRST(&vnic->filter);
2333         while (filter) {
2334                 if (filter->mac_index == 0 &&
2335                     !memcmp(filter->l2_addr, bp->mac_addr,
2336                             RTE_ETHER_ADDR_LEN)) {
2337                         rc = bnxt_hwrm_clear_l2_filter(bp, filter);
2338                         if (!rc) {
2339                                 STAILQ_REMOVE(&vnic->filter, filter,
2340                                               bnxt_filter_info, next);
2341                                 bnxt_free_filter(bp, filter);
2342                         }
2343                         return rc;
2344                 }
2345                 filter = STAILQ_NEXT(filter, next);
2346         }
2347         return 0;
2348 }
2349
2350 static int
2351 bnxt_config_vlan_hw_filter(struct bnxt *bp, uint64_t rx_offloads)
2352 {
2353         struct bnxt_vnic_info *vnic;
2354         unsigned int i;
2355         int rc;
2356
2357         vnic = BNXT_GET_DEFAULT_VNIC(bp);
2358         if (!(rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER)) {
2359                 /* Remove any VLAN filters programmed */
2360                 for (i = 0; i < RTE_ETHER_MAX_VLAN_ID; i++)
2361                         bnxt_del_vlan_filter(bp, i);
2362
2363                 rc = bnxt_add_mac_filter(bp, vnic, NULL, 0, 0);
2364                 if (rc)
2365                         return rc;
2366         } else {
2367                 /* Default filter will allow packets that match the
2368                  * dest mac. So, it has to be deleted, otherwise, we
2369                  * will endup receiving vlan packets for which the
2370                  * filter is not programmed, when hw-vlan-filter
2371                  * configuration is ON
2372                  */
2373                 bnxt_del_dflt_mac_filter(bp, vnic);
2374                 /* This filter will allow only untagged packets */
2375                 bnxt_add_vlan_filter(bp, 0);
2376         }
2377         PMD_DRV_LOG(DEBUG, "VLAN Filtering: %d\n",
2378                     !!(rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER));
2379
2380         return 0;
2381 }
2382
2383 static int bnxt_free_one_vnic(struct bnxt *bp, uint16_t vnic_id)
2384 {
2385         struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id];
2386         unsigned int i;
2387         int rc;
2388
2389         /* Destroy vnic filters and vnic */
2390         if (bp->eth_dev->data->dev_conf.rxmode.offloads &
2391             DEV_RX_OFFLOAD_VLAN_FILTER) {
2392                 for (i = 0; i < RTE_ETHER_MAX_VLAN_ID; i++)
2393                         bnxt_del_vlan_filter(bp, i);
2394         }
2395         bnxt_del_dflt_mac_filter(bp, vnic);
2396
2397         rc = bnxt_hwrm_vnic_free(bp, vnic);
2398         if (rc)
2399                 return rc;
2400
2401         rte_free(vnic->fw_grp_ids);
2402         vnic->fw_grp_ids = NULL;
2403
2404         vnic->rx_queue_cnt = 0;
2405
2406         return 0;
2407 }
2408
2409 static int
2410 bnxt_config_vlan_hw_stripping(struct bnxt *bp, uint64_t rx_offloads)
2411 {
2412         struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp);
2413         int rc;
2414
2415         /* Destroy, recreate and reconfigure the default vnic */
2416         rc = bnxt_free_one_vnic(bp, 0);
2417         if (rc)
2418                 return rc;
2419
2420         /* default vnic 0 */
2421         rc = bnxt_setup_one_vnic(bp, 0);
2422         if (rc)
2423                 return rc;
2424
2425         if (bp->eth_dev->data->dev_conf.rxmode.offloads &
2426             DEV_RX_OFFLOAD_VLAN_FILTER) {
2427                 rc = bnxt_add_vlan_filter(bp, 0);
2428                 if (rc)
2429                         return rc;
2430                 rc = bnxt_restore_vlan_filters(bp);
2431                 if (rc)
2432                         return rc;
2433         } else {
2434                 rc = bnxt_add_mac_filter(bp, vnic, NULL, 0, 0);
2435                 if (rc)
2436                         return rc;
2437         }
2438
2439         rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
2440         if (rc)
2441                 return rc;
2442
2443         PMD_DRV_LOG(DEBUG, "VLAN Strip Offload: %d\n",
2444                     !!(rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP));
2445
2446         return rc;
2447 }
2448
2449 static int
2450 bnxt_vlan_offload_set_op(struct rte_eth_dev *dev, int mask)
2451 {
2452         uint64_t rx_offloads = dev->data->dev_conf.rxmode.offloads;
2453         struct bnxt *bp = dev->data->dev_private;
2454         int rc;
2455
2456         rc = is_bnxt_in_error(bp);
2457         if (rc)
2458                 return rc;
2459
2460         /* Filter settings will get applied when port is started */
2461         if (!dev->data->dev_started)
2462                 return 0;
2463
2464         if (mask & ETH_VLAN_FILTER_MASK) {
2465                 /* Enable or disable VLAN filtering */
2466                 rc = bnxt_config_vlan_hw_filter(bp, rx_offloads);
2467                 if (rc)
2468                         return rc;
2469         }
2470
2471         if (mask & ETH_VLAN_STRIP_MASK) {
2472                 /* Enable or disable VLAN stripping */
2473                 rc = bnxt_config_vlan_hw_stripping(bp, rx_offloads);
2474                 if (rc)
2475                         return rc;
2476         }
2477
2478         if (mask & ETH_VLAN_EXTEND_MASK) {
2479                 if (rx_offloads & DEV_RX_OFFLOAD_VLAN_EXTEND)
2480                         PMD_DRV_LOG(DEBUG, "Extend VLAN supported\n");
2481                 else
2482                         PMD_DRV_LOG(INFO, "Extend VLAN unsupported\n");
2483         }
2484
2485         return 0;
2486 }
2487
2488 static int
2489 bnxt_vlan_tpid_set_op(struct rte_eth_dev *dev, enum rte_vlan_type vlan_type,
2490                       uint16_t tpid)
2491 {
2492         struct bnxt *bp = dev->data->dev_private;
2493         int qinq = dev->data->dev_conf.rxmode.offloads &
2494                    DEV_RX_OFFLOAD_VLAN_EXTEND;
2495
2496         if (vlan_type != ETH_VLAN_TYPE_INNER &&
2497             vlan_type != ETH_VLAN_TYPE_OUTER) {
2498                 PMD_DRV_LOG(ERR,
2499                             "Unsupported vlan type.");
2500                 return -EINVAL;
2501         }
2502         if (!qinq) {
2503                 PMD_DRV_LOG(ERR,
2504                             "QinQ not enabled. Needs to be ON as we can "
2505                             "accelerate only outer vlan\n");
2506                 return -EINVAL;
2507         }
2508
2509         if (vlan_type == ETH_VLAN_TYPE_OUTER) {
2510                 switch (tpid) {
2511                 case RTE_ETHER_TYPE_QINQ:
2512                         bp->outer_tpid_bd =
2513                                 TX_BD_LONG_CFA_META_VLAN_TPID_TPID88A8;
2514                                 break;
2515                 case RTE_ETHER_TYPE_VLAN:
2516                         bp->outer_tpid_bd =
2517                                 TX_BD_LONG_CFA_META_VLAN_TPID_TPID8100;
2518                                 break;
2519                 case RTE_ETHER_TYPE_QINQ1:
2520                         bp->outer_tpid_bd =
2521                                 TX_BD_LONG_CFA_META_VLAN_TPID_TPID9100;
2522                                 break;
2523                 case RTE_ETHER_TYPE_QINQ2:
2524                         bp->outer_tpid_bd =
2525                                 TX_BD_LONG_CFA_META_VLAN_TPID_TPID9200;
2526                                 break;
2527                 case RTE_ETHER_TYPE_QINQ3:
2528                         bp->outer_tpid_bd =
2529                                  TX_BD_LONG_CFA_META_VLAN_TPID_TPID9300;
2530                                 break;
2531                 default:
2532                         PMD_DRV_LOG(ERR, "Invalid TPID: %x\n", tpid);
2533                         return -EINVAL;
2534                 }
2535                 bp->outer_tpid_bd |= tpid;
2536                 PMD_DRV_LOG(INFO, "outer_tpid_bd = %x\n", bp->outer_tpid_bd);
2537         } else if (vlan_type == ETH_VLAN_TYPE_INNER) {
2538                 PMD_DRV_LOG(ERR,
2539                             "Can accelerate only outer vlan in QinQ\n");
2540                 return -EINVAL;
2541         }
2542
2543         return 0;
2544 }
2545
2546 static int
2547 bnxt_set_default_mac_addr_op(struct rte_eth_dev *dev,
2548                              struct rte_ether_addr *addr)
2549 {
2550         struct bnxt *bp = dev->data->dev_private;
2551         /* Default Filter is tied to VNIC 0 */
2552         struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp);
2553         int rc;
2554
2555         rc = is_bnxt_in_error(bp);
2556         if (rc)
2557                 return rc;
2558
2559         if (BNXT_VF(bp) && !BNXT_VF_IS_TRUSTED(bp))
2560                 return -EPERM;
2561
2562         if (rte_is_zero_ether_addr(addr))
2563                 return -EINVAL;
2564
2565         /* Filter settings will get applied when port is started */
2566         if (!dev->data->dev_started)
2567                 return 0;
2568
2569         /* Check if the requested MAC is already added */
2570         if (memcmp(addr, bp->mac_addr, RTE_ETHER_ADDR_LEN) == 0)
2571                 return 0;
2572
2573         /* Destroy filter and re-create it */
2574         bnxt_del_dflt_mac_filter(bp, vnic);
2575
2576         memcpy(bp->mac_addr, addr, RTE_ETHER_ADDR_LEN);
2577         if (dev->data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_VLAN_FILTER) {
2578                 /* This filter will allow only untagged packets */
2579                 rc = bnxt_add_vlan_filter(bp, 0);
2580         } else {
2581                 rc = bnxt_add_mac_filter(bp, vnic, addr, 0, 0);
2582         }
2583
2584         PMD_DRV_LOG(DEBUG, "Set MAC addr\n");
2585         return rc;
2586 }
2587
2588 static int
2589 bnxt_dev_set_mc_addr_list_op(struct rte_eth_dev *eth_dev,
2590                           struct rte_ether_addr *mc_addr_set,
2591                           uint32_t nb_mc_addr)
2592 {
2593         struct bnxt *bp = eth_dev->data->dev_private;
2594         char *mc_addr_list = (char *)mc_addr_set;
2595         struct bnxt_vnic_info *vnic;
2596         uint32_t off = 0, i = 0;
2597         int rc;
2598
2599         rc = is_bnxt_in_error(bp);
2600         if (rc)
2601                 return rc;
2602
2603         vnic = BNXT_GET_DEFAULT_VNIC(bp);
2604
2605         if (nb_mc_addr > BNXT_MAX_MC_ADDRS) {
2606                 vnic->flags |= BNXT_VNIC_INFO_ALLMULTI;
2607                 goto allmulti;
2608         }
2609
2610         /* TODO Check for Duplicate mcast addresses */
2611         vnic->flags &= ~BNXT_VNIC_INFO_ALLMULTI;
2612         for (i = 0; i < nb_mc_addr; i++) {
2613                 memcpy(vnic->mc_list + off, &mc_addr_list[i],
2614                         RTE_ETHER_ADDR_LEN);
2615                 off += RTE_ETHER_ADDR_LEN;
2616         }
2617
2618         vnic->mc_addr_cnt = i;
2619         if (vnic->mc_addr_cnt)
2620                 vnic->flags |= BNXT_VNIC_INFO_MCAST;
2621         else
2622                 vnic->flags &= ~BNXT_VNIC_INFO_MCAST;
2623
2624 allmulti:
2625         return bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
2626 }
2627
2628 static int
2629 bnxt_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size)
2630 {
2631         struct bnxt *bp = dev->data->dev_private;
2632         uint8_t fw_major = (bp->fw_ver >> 24) & 0xff;
2633         uint8_t fw_minor = (bp->fw_ver >> 16) & 0xff;
2634         uint8_t fw_updt = (bp->fw_ver >> 8) & 0xff;
2635         uint8_t fw_rsvd = bp->fw_ver & 0xff;
2636         int ret;
2637
2638         ret = snprintf(fw_version, fw_size, "%d.%d.%d.%d",
2639                         fw_major, fw_minor, fw_updt, fw_rsvd);
2640
2641         ret += 1; /* add the size of '\0' */
2642         if (fw_size < (uint32_t)ret)
2643                 return ret;
2644         else
2645                 return 0;
2646 }
2647
2648 static void
2649 bnxt_rxq_info_get_op(struct rte_eth_dev *dev, uint16_t queue_id,
2650         struct rte_eth_rxq_info *qinfo)
2651 {
2652         struct bnxt *bp = dev->data->dev_private;
2653         struct bnxt_rx_queue *rxq;
2654
2655         if (is_bnxt_in_error(bp))
2656                 return;
2657
2658         rxq = dev->data->rx_queues[queue_id];
2659
2660         qinfo->mp = rxq->mb_pool;
2661         qinfo->scattered_rx = dev->data->scattered_rx;
2662         qinfo->nb_desc = rxq->nb_rx_desc;
2663
2664         qinfo->conf.rx_free_thresh = rxq->rx_free_thresh;
2665         qinfo->conf.rx_drop_en = rxq->drop_en;
2666         qinfo->conf.rx_deferred_start = rxq->rx_deferred_start;
2667         qinfo->conf.offloads = dev->data->dev_conf.rxmode.offloads;
2668 }
2669
2670 static void
2671 bnxt_txq_info_get_op(struct rte_eth_dev *dev, uint16_t queue_id,
2672         struct rte_eth_txq_info *qinfo)
2673 {
2674         struct bnxt *bp = dev->data->dev_private;
2675         struct bnxt_tx_queue *txq;
2676
2677         if (is_bnxt_in_error(bp))
2678                 return;
2679
2680         txq = dev->data->tx_queues[queue_id];
2681
2682         qinfo->nb_desc = txq->nb_tx_desc;
2683
2684         qinfo->conf.tx_thresh.pthresh = txq->pthresh;
2685         qinfo->conf.tx_thresh.hthresh = txq->hthresh;
2686         qinfo->conf.tx_thresh.wthresh = txq->wthresh;
2687
2688         qinfo->conf.tx_free_thresh = txq->tx_free_thresh;
2689         qinfo->conf.tx_rs_thresh = 0;
2690         qinfo->conf.tx_deferred_start = txq->tx_deferred_start;
2691         qinfo->conf.offloads = txq->offloads;
2692 }
2693
2694 static const struct {
2695         eth_rx_burst_t pkt_burst;
2696         const char *info;
2697 } bnxt_rx_burst_info[] = {
2698         {bnxt_recv_pkts,        "Scalar"},
2699 #if defined(RTE_ARCH_X86)
2700         {bnxt_recv_pkts_vec,    "Vector SSE"},
2701 #elif defined(RTE_ARCH_ARM64)
2702         {bnxt_recv_pkts_vec,    "Vector Neon"},
2703 #endif
2704 };
2705
2706 static int
2707 bnxt_rx_burst_mode_get(struct rte_eth_dev *dev, __rte_unused uint16_t queue_id,
2708                        struct rte_eth_burst_mode *mode)
2709 {
2710         eth_rx_burst_t pkt_burst = dev->rx_pkt_burst;
2711         size_t i;
2712
2713         for (i = 0; i < RTE_DIM(bnxt_rx_burst_info); i++) {
2714                 if (pkt_burst == bnxt_rx_burst_info[i].pkt_burst) {
2715                         snprintf(mode->info, sizeof(mode->info), "%s",
2716                                  bnxt_rx_burst_info[i].info);
2717                         return 0;
2718                 }
2719         }
2720
2721         return -EINVAL;
2722 }
2723
2724 static const struct {
2725         eth_tx_burst_t pkt_burst;
2726         const char *info;
2727 } bnxt_tx_burst_info[] = {
2728         {bnxt_xmit_pkts,        "Scalar"},
2729 #if defined(RTE_ARCH_X86)
2730         {bnxt_xmit_pkts_vec,    "Vector SSE"},
2731 #elif defined(RTE_ARCH_ARM64)
2732         {bnxt_xmit_pkts_vec,    "Vector Neon"},
2733 #endif
2734 };
2735
2736 static int
2737 bnxt_tx_burst_mode_get(struct rte_eth_dev *dev, __rte_unused uint16_t queue_id,
2738                        struct rte_eth_burst_mode *mode)
2739 {
2740         eth_tx_burst_t pkt_burst = dev->tx_pkt_burst;
2741         size_t i;
2742
2743         for (i = 0; i < RTE_DIM(bnxt_tx_burst_info); i++) {
2744                 if (pkt_burst == bnxt_tx_burst_info[i].pkt_burst) {
2745                         snprintf(mode->info, sizeof(mode->info), "%s",
2746                                  bnxt_tx_burst_info[i].info);
2747                         return 0;
2748                 }
2749         }
2750
2751         return -EINVAL;
2752 }
2753
2754 int bnxt_mtu_set_op(struct rte_eth_dev *eth_dev, uint16_t new_mtu)
2755 {
2756         struct bnxt *bp = eth_dev->data->dev_private;
2757         uint32_t new_pkt_size;
2758         uint32_t rc = 0;
2759         uint32_t i;
2760
2761         rc = is_bnxt_in_error(bp);
2762         if (rc)
2763                 return rc;
2764
2765         /* Exit if receive queues are not configured yet */
2766         if (!eth_dev->data->nb_rx_queues)
2767                 return rc;
2768
2769         new_pkt_size = new_mtu + RTE_ETHER_HDR_LEN + RTE_ETHER_CRC_LEN +
2770                        VLAN_TAG_SIZE * BNXT_NUM_VLANS;
2771
2772         /*
2773          * Disallow any MTU change that would require scattered receive support
2774          * if it is not already enabled.
2775          */
2776         if (eth_dev->data->dev_started &&
2777             !eth_dev->data->scattered_rx &&
2778             (new_pkt_size >
2779              eth_dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM)) {
2780                 PMD_DRV_LOG(ERR,
2781                             "MTU change would require scattered rx support. ");
2782                 PMD_DRV_LOG(ERR, "Stop port before changing MTU.\n");
2783                 return -EINVAL;
2784         }
2785
2786         if (new_mtu > RTE_ETHER_MTU) {
2787                 bp->flags |= BNXT_FLAG_JUMBO;
2788                 bp->eth_dev->data->dev_conf.rxmode.offloads |=
2789                         DEV_RX_OFFLOAD_JUMBO_FRAME;
2790         } else {
2791                 bp->eth_dev->data->dev_conf.rxmode.offloads &=
2792                         ~DEV_RX_OFFLOAD_JUMBO_FRAME;
2793                 bp->flags &= ~BNXT_FLAG_JUMBO;
2794         }
2795
2796         /* Is there a change in mtu setting? */
2797         if (eth_dev->data->dev_conf.rxmode.max_rx_pkt_len == new_pkt_size)
2798                 return rc;
2799
2800         for (i = 0; i < bp->nr_vnics; i++) {
2801                 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
2802                 uint16_t size = 0;
2803
2804                 vnic->mru = BNXT_VNIC_MRU(new_mtu);
2805                 rc = bnxt_hwrm_vnic_cfg(bp, vnic);
2806                 if (rc)
2807                         break;
2808
2809                 size = rte_pktmbuf_data_room_size(bp->rx_queues[0]->mb_pool);
2810                 size -= RTE_PKTMBUF_HEADROOM;
2811
2812                 if (size < new_mtu) {
2813                         rc = bnxt_hwrm_vnic_plcmode_cfg(bp, vnic);
2814                         if (rc)
2815                                 return rc;
2816                 }
2817         }
2818
2819         if (!rc)
2820                 eth_dev->data->dev_conf.rxmode.max_rx_pkt_len = new_pkt_size;
2821
2822         PMD_DRV_LOG(INFO, "New MTU is %d\n", new_mtu);
2823
2824         return rc;
2825 }
2826
2827 static int
2828 bnxt_vlan_pvid_set_op(struct rte_eth_dev *dev, uint16_t pvid, int on)
2829 {
2830         struct bnxt *bp = dev->data->dev_private;
2831         uint16_t vlan = bp->vlan;
2832         int rc;
2833
2834         rc = is_bnxt_in_error(bp);
2835         if (rc)
2836                 return rc;
2837
2838         if (!BNXT_SINGLE_PF(bp) || BNXT_VF(bp)) {
2839                 PMD_DRV_LOG(ERR,
2840                         "PVID cannot be modified for this function\n");
2841                 return -ENOTSUP;
2842         }
2843         bp->vlan = on ? pvid : 0;
2844
2845         rc = bnxt_hwrm_set_default_vlan(bp, 0, 0);
2846         if (rc)
2847                 bp->vlan = vlan;
2848         return rc;
2849 }
2850
2851 static int
2852 bnxt_dev_led_on_op(struct rte_eth_dev *dev)
2853 {
2854         struct bnxt *bp = dev->data->dev_private;
2855         int rc;
2856
2857         rc = is_bnxt_in_error(bp);
2858         if (rc)
2859                 return rc;
2860
2861         return bnxt_hwrm_port_led_cfg(bp, true);
2862 }
2863
2864 static int
2865 bnxt_dev_led_off_op(struct rte_eth_dev *dev)
2866 {
2867         struct bnxt *bp = dev->data->dev_private;
2868         int rc;
2869
2870         rc = is_bnxt_in_error(bp);
2871         if (rc)
2872                 return rc;
2873
2874         return bnxt_hwrm_port_led_cfg(bp, false);
2875 }
2876
2877 static uint32_t
2878 bnxt_rx_queue_count_op(struct rte_eth_dev *dev, uint16_t rx_queue_id)
2879 {
2880         struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
2881         uint32_t desc = 0, raw_cons = 0, cons;
2882         struct bnxt_cp_ring_info *cpr;
2883         struct bnxt_rx_queue *rxq;
2884         struct rx_pkt_cmpl *rxcmp;
2885         int rc;
2886
2887         rc = is_bnxt_in_error(bp);
2888         if (rc)
2889                 return rc;
2890
2891         rxq = dev->data->rx_queues[rx_queue_id];
2892         cpr = rxq->cp_ring;
2893         raw_cons = cpr->cp_raw_cons;
2894
2895         while (1) {
2896                 cons = RING_CMP(cpr->cp_ring_struct, raw_cons);
2897                 rte_prefetch0(&cpr->cp_desc_ring[cons]);
2898                 rxcmp = (struct rx_pkt_cmpl *)&cpr->cp_desc_ring[cons];
2899
2900                 if (!CMP_VALID(rxcmp, raw_cons, cpr->cp_ring_struct)) {
2901                         break;
2902                 } else {
2903                         raw_cons++;
2904                         desc++;
2905                 }
2906         }
2907
2908         return desc;
2909 }
2910
2911 static int
2912 bnxt_rx_descriptor_status_op(void *rx_queue, uint16_t offset)
2913 {
2914         struct bnxt_rx_queue *rxq = (struct bnxt_rx_queue *)rx_queue;
2915         struct bnxt_rx_ring_info *rxr;
2916         struct bnxt_cp_ring_info *cpr;
2917         struct rte_mbuf *rx_buf;
2918         struct rx_pkt_cmpl *rxcmp;
2919         uint32_t cons, cp_cons;
2920         int rc;
2921
2922         if (!rxq)
2923                 return -EINVAL;
2924
2925         rc = is_bnxt_in_error(rxq->bp);
2926         if (rc)
2927                 return rc;
2928
2929         cpr = rxq->cp_ring;
2930         rxr = rxq->rx_ring;
2931
2932         if (offset >= rxq->nb_rx_desc)
2933                 return -EINVAL;
2934
2935         cons = RING_CMP(cpr->cp_ring_struct, offset);
2936         cp_cons = cpr->cp_raw_cons;
2937         rxcmp = (struct rx_pkt_cmpl *)&cpr->cp_desc_ring[cons];
2938
2939         if (cons > cp_cons) {
2940                 if (CMPL_VALID(rxcmp, cpr->valid))
2941                         return RTE_ETH_RX_DESC_DONE;
2942         } else {
2943                 if (CMPL_VALID(rxcmp, !cpr->valid))
2944                         return RTE_ETH_RX_DESC_DONE;
2945         }
2946         rx_buf = rxr->rx_buf_ring[cons];
2947         if (rx_buf == NULL || rx_buf == &rxq->fake_mbuf)
2948                 return RTE_ETH_RX_DESC_UNAVAIL;
2949
2950
2951         return RTE_ETH_RX_DESC_AVAIL;
2952 }
2953
2954 static int
2955 bnxt_tx_descriptor_status_op(void *tx_queue, uint16_t offset)
2956 {
2957         struct bnxt_tx_queue *txq = (struct bnxt_tx_queue *)tx_queue;
2958         struct bnxt_tx_ring_info *txr;
2959         struct bnxt_cp_ring_info *cpr;
2960         struct bnxt_sw_tx_bd *tx_buf;
2961         struct tx_pkt_cmpl *txcmp;
2962         uint32_t cons, cp_cons;
2963         int rc;
2964
2965         if (!txq)
2966                 return -EINVAL;
2967
2968         rc = is_bnxt_in_error(txq->bp);
2969         if (rc)
2970                 return rc;
2971
2972         cpr = txq->cp_ring;
2973         txr = txq->tx_ring;
2974
2975         if (offset >= txq->nb_tx_desc)
2976                 return -EINVAL;
2977
2978         cons = RING_CMP(cpr->cp_ring_struct, offset);
2979         txcmp = (struct tx_pkt_cmpl *)&cpr->cp_desc_ring[cons];
2980         cp_cons = cpr->cp_raw_cons;
2981
2982         if (cons > cp_cons) {
2983                 if (CMPL_VALID(txcmp, cpr->valid))
2984                         return RTE_ETH_TX_DESC_UNAVAIL;
2985         } else {
2986                 if (CMPL_VALID(txcmp, !cpr->valid))
2987                         return RTE_ETH_TX_DESC_UNAVAIL;
2988         }
2989         tx_buf = &txr->tx_buf_ring[cons];
2990         if (tx_buf->mbuf == NULL)
2991                 return RTE_ETH_TX_DESC_DONE;
2992
2993         return RTE_ETH_TX_DESC_FULL;
2994 }
2995
2996 static struct bnxt_filter_info *
2997 bnxt_match_and_validate_ether_filter(struct bnxt *bp,
2998                                 struct rte_eth_ethertype_filter *efilter,
2999                                 struct bnxt_vnic_info *vnic0,
3000                                 struct bnxt_vnic_info *vnic,
3001                                 int *ret)
3002 {
3003         struct bnxt_filter_info *mfilter = NULL;
3004         int match = 0;
3005         *ret = 0;
3006
3007         if (efilter->ether_type == RTE_ETHER_TYPE_IPV4 ||
3008                 efilter->ether_type == RTE_ETHER_TYPE_IPV6) {
3009                 PMD_DRV_LOG(ERR, "invalid ether_type(0x%04x) in"
3010                         " ethertype filter.", efilter->ether_type);
3011                 *ret = -EINVAL;
3012                 goto exit;
3013         }
3014         if (efilter->queue >= bp->rx_nr_rings) {
3015                 PMD_DRV_LOG(ERR, "Invalid queue %d\n", efilter->queue);
3016                 *ret = -EINVAL;
3017                 goto exit;
3018         }
3019
3020         vnic0 = BNXT_GET_DEFAULT_VNIC(bp);
3021         vnic = &bp->vnic_info[efilter->queue];
3022         if (vnic == NULL) {
3023                 PMD_DRV_LOG(ERR, "Invalid queue %d\n", efilter->queue);
3024                 *ret = -EINVAL;
3025                 goto exit;
3026         }
3027
3028         if (efilter->flags & RTE_ETHTYPE_FLAGS_DROP) {
3029                 STAILQ_FOREACH(mfilter, &vnic0->filter, next) {
3030                         if ((!memcmp(efilter->mac_addr.addr_bytes,
3031                                      mfilter->l2_addr, RTE_ETHER_ADDR_LEN) &&
3032                              mfilter->flags ==
3033                              HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_DROP &&
3034                              mfilter->ethertype == efilter->ether_type)) {
3035                                 match = 1;
3036                                 break;
3037                         }
3038                 }
3039         } else {
3040                 STAILQ_FOREACH(mfilter, &vnic->filter, next)
3041                         if ((!memcmp(efilter->mac_addr.addr_bytes,
3042                                      mfilter->l2_addr, RTE_ETHER_ADDR_LEN) &&
3043                              mfilter->ethertype == efilter->ether_type &&
3044                              mfilter->flags ==
3045                              HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_PATH_RX)) {
3046                                 match = 1;
3047                                 break;
3048                         }
3049         }
3050
3051         if (match)
3052                 *ret = -EEXIST;
3053
3054 exit:
3055         return mfilter;
3056 }
3057
3058 static int
3059 bnxt_ethertype_filter(struct rte_eth_dev *dev,
3060                         enum rte_filter_op filter_op,
3061                         void *arg)
3062 {
3063         struct bnxt *bp = dev->data->dev_private;
3064         struct rte_eth_ethertype_filter *efilter =
3065                         (struct rte_eth_ethertype_filter *)arg;
3066         struct bnxt_filter_info *bfilter, *filter1;
3067         struct bnxt_vnic_info *vnic, *vnic0;
3068         int ret;
3069
3070         if (filter_op == RTE_ETH_FILTER_NOP)
3071                 return 0;
3072
3073         if (arg == NULL) {
3074                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
3075                             filter_op);
3076                 return -EINVAL;
3077         }
3078
3079         vnic0 = BNXT_GET_DEFAULT_VNIC(bp);
3080         vnic = &bp->vnic_info[efilter->queue];
3081
3082         switch (filter_op) {
3083         case RTE_ETH_FILTER_ADD:
3084                 bnxt_match_and_validate_ether_filter(bp, efilter,
3085                                                         vnic0, vnic, &ret);
3086                 if (ret < 0)
3087                         return ret;
3088
3089                 bfilter = bnxt_get_unused_filter(bp);
3090                 if (bfilter == NULL) {
3091                         PMD_DRV_LOG(ERR,
3092                                 "Not enough resources for a new filter.\n");
3093                         return -ENOMEM;
3094                 }
3095                 bfilter->filter_type = HWRM_CFA_NTUPLE_FILTER;
3096                 memcpy(bfilter->l2_addr, efilter->mac_addr.addr_bytes,
3097                        RTE_ETHER_ADDR_LEN);
3098                 memcpy(bfilter->dst_macaddr, efilter->mac_addr.addr_bytes,
3099                        RTE_ETHER_ADDR_LEN);
3100                 bfilter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_MACADDR;
3101                 bfilter->ethertype = efilter->ether_type;
3102                 bfilter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
3103
3104                 filter1 = bnxt_get_l2_filter(bp, bfilter, vnic0);
3105                 if (filter1 == NULL) {
3106                         ret = -EINVAL;
3107                         goto cleanup;
3108                 }
3109                 bfilter->enables |=
3110                         HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID;
3111                 bfilter->fw_l2_filter_id = filter1->fw_l2_filter_id;
3112
3113                 bfilter->dst_id = vnic->fw_vnic_id;
3114
3115                 if (efilter->flags & RTE_ETHTYPE_FLAGS_DROP) {
3116                         bfilter->flags =
3117                                 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_DROP;
3118                 }
3119
3120                 ret = bnxt_hwrm_set_ntuple_filter(bp, bfilter->dst_id, bfilter);
3121                 if (ret)
3122                         goto cleanup;
3123                 STAILQ_INSERT_TAIL(&vnic->filter, bfilter, next);
3124                 break;
3125         case RTE_ETH_FILTER_DELETE:
3126                 filter1 = bnxt_match_and_validate_ether_filter(bp, efilter,
3127                                                         vnic0, vnic, &ret);
3128                 if (ret == -EEXIST) {
3129                         ret = bnxt_hwrm_clear_ntuple_filter(bp, filter1);
3130
3131                         STAILQ_REMOVE(&vnic->filter, filter1, bnxt_filter_info,
3132                                       next);
3133                         bnxt_free_filter(bp, filter1);
3134                 } else if (ret == 0) {
3135                         PMD_DRV_LOG(ERR, "No matching filter found\n");
3136                 }
3137                 break;
3138         default:
3139                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
3140                 ret = -EINVAL;
3141                 goto error;
3142         }
3143         return ret;
3144 cleanup:
3145         bnxt_free_filter(bp, bfilter);
3146 error:
3147         return ret;
3148 }
3149
3150 static inline int
3151 parse_ntuple_filter(struct bnxt *bp,
3152                     struct rte_eth_ntuple_filter *nfilter,
3153                     struct bnxt_filter_info *bfilter)
3154 {
3155         uint32_t en = 0;
3156
3157         if (nfilter->queue >= bp->rx_nr_rings) {
3158                 PMD_DRV_LOG(ERR, "Invalid queue %d\n", nfilter->queue);
3159                 return -EINVAL;
3160         }
3161
3162         switch (nfilter->dst_port_mask) {
3163         case UINT16_MAX:
3164                 bfilter->dst_port_mask = -1;
3165                 bfilter->dst_port = nfilter->dst_port;
3166                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT |
3167                         NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
3168                 break;
3169         default:
3170                 PMD_DRV_LOG(ERR, "invalid dst_port mask.");
3171                 return -EINVAL;
3172         }
3173
3174         bfilter->ip_addr_type = NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4;
3175         en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
3176
3177         switch (nfilter->proto_mask) {
3178         case UINT8_MAX:
3179                 if (nfilter->proto == 17) /* IPPROTO_UDP */
3180                         bfilter->ip_protocol = 17;
3181                 else if (nfilter->proto == 6) /* IPPROTO_TCP */
3182                         bfilter->ip_protocol = 6;
3183                 else
3184                         return -EINVAL;
3185                 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
3186                 break;
3187         default:
3188                 PMD_DRV_LOG(ERR, "invalid protocol mask.");
3189                 return -EINVAL;
3190         }
3191
3192         switch (nfilter->dst_ip_mask) {
3193         case UINT32_MAX:
3194                 bfilter->dst_ipaddr_mask[0] = -1;
3195                 bfilter->dst_ipaddr[0] = nfilter->dst_ip;
3196                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR |
3197                         NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
3198                 break;
3199         default:
3200                 PMD_DRV_LOG(ERR, "invalid dst_ip mask.");
3201                 return -EINVAL;
3202         }
3203
3204         switch (nfilter->src_ip_mask) {
3205         case UINT32_MAX:
3206                 bfilter->src_ipaddr_mask[0] = -1;
3207                 bfilter->src_ipaddr[0] = nfilter->src_ip;
3208                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR |
3209                         NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
3210                 break;
3211         default:
3212                 PMD_DRV_LOG(ERR, "invalid src_ip mask.");
3213                 return -EINVAL;
3214         }
3215
3216         switch (nfilter->src_port_mask) {
3217         case UINT16_MAX:
3218                 bfilter->src_port_mask = -1;
3219                 bfilter->src_port = nfilter->src_port;
3220                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT |
3221                         NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
3222                 break;
3223         default:
3224                 PMD_DRV_LOG(ERR, "invalid src_port mask.");
3225                 return -EINVAL;
3226         }
3227
3228         bfilter->enables = en;
3229         return 0;
3230 }
3231
3232 static struct bnxt_filter_info*
3233 bnxt_match_ntuple_filter(struct bnxt *bp,
3234                          struct bnxt_filter_info *bfilter,
3235                          struct bnxt_vnic_info **mvnic)
3236 {
3237         struct bnxt_filter_info *mfilter = NULL;
3238         int i;
3239
3240         for (i = bp->nr_vnics - 1; i >= 0; i--) {
3241                 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
3242                 STAILQ_FOREACH(mfilter, &vnic->filter, next) {
3243                         if (bfilter->src_ipaddr[0] == mfilter->src_ipaddr[0] &&
3244                             bfilter->src_ipaddr_mask[0] ==
3245                             mfilter->src_ipaddr_mask[0] &&
3246                             bfilter->src_port == mfilter->src_port &&
3247                             bfilter->src_port_mask == mfilter->src_port_mask &&
3248                             bfilter->dst_ipaddr[0] == mfilter->dst_ipaddr[0] &&
3249                             bfilter->dst_ipaddr_mask[0] ==
3250                             mfilter->dst_ipaddr_mask[0] &&
3251                             bfilter->dst_port == mfilter->dst_port &&
3252                             bfilter->dst_port_mask == mfilter->dst_port_mask &&
3253                             bfilter->flags == mfilter->flags &&
3254                             bfilter->enables == mfilter->enables) {
3255                                 if (mvnic)
3256                                         *mvnic = vnic;
3257                                 return mfilter;
3258                         }
3259                 }
3260         }
3261         return NULL;
3262 }
3263
3264 static int
3265 bnxt_cfg_ntuple_filter(struct bnxt *bp,
3266                        struct rte_eth_ntuple_filter *nfilter,
3267                        enum rte_filter_op filter_op)
3268 {
3269         struct bnxt_filter_info *bfilter, *mfilter, *filter1;
3270         struct bnxt_vnic_info *vnic, *vnic0, *mvnic;
3271         int ret;
3272
3273         if (nfilter->flags != RTE_5TUPLE_FLAGS) {
3274                 PMD_DRV_LOG(ERR, "only 5tuple is supported.");
3275                 return -EINVAL;
3276         }
3277
3278         if (nfilter->flags & RTE_NTUPLE_FLAGS_TCP_FLAG) {
3279                 PMD_DRV_LOG(ERR, "Ntuple filter: TCP flags not supported\n");
3280                 return -EINVAL;
3281         }
3282
3283         bfilter = bnxt_get_unused_filter(bp);
3284         if (bfilter == NULL) {
3285                 PMD_DRV_LOG(ERR,
3286                         "Not enough resources for a new filter.\n");
3287                 return -ENOMEM;
3288         }
3289         ret = parse_ntuple_filter(bp, nfilter, bfilter);
3290         if (ret < 0)
3291                 goto free_filter;
3292
3293         vnic = &bp->vnic_info[nfilter->queue];
3294         vnic0 = BNXT_GET_DEFAULT_VNIC(bp);
3295         filter1 = STAILQ_FIRST(&vnic0->filter);
3296         if (filter1 == NULL) {
3297                 ret = -EINVAL;
3298                 goto free_filter;
3299         }
3300
3301         bfilter->dst_id = vnic->fw_vnic_id;
3302         bfilter->fw_l2_filter_id = filter1->fw_l2_filter_id;
3303         bfilter->enables |=
3304                 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID;
3305         bfilter->ethertype = 0x800;
3306         bfilter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
3307
3308         mfilter = bnxt_match_ntuple_filter(bp, bfilter, &mvnic);
3309
3310         if (mfilter != NULL && filter_op == RTE_ETH_FILTER_ADD &&
3311             bfilter->dst_id == mfilter->dst_id) {
3312                 PMD_DRV_LOG(ERR, "filter exists.\n");
3313                 ret = -EEXIST;
3314                 goto free_filter;
3315         } else if (mfilter != NULL && filter_op == RTE_ETH_FILTER_ADD &&
3316                    bfilter->dst_id != mfilter->dst_id) {
3317                 mfilter->dst_id = vnic->fw_vnic_id;
3318                 ret = bnxt_hwrm_set_ntuple_filter(bp, mfilter->dst_id, mfilter);
3319                 STAILQ_REMOVE(&mvnic->filter, mfilter, bnxt_filter_info, next);
3320                 STAILQ_INSERT_TAIL(&vnic->filter, mfilter, next);
3321                 PMD_DRV_LOG(ERR, "filter with matching pattern exists.\n");
3322                 PMD_DRV_LOG(ERR, " Updated it to the new destination queue\n");
3323                 goto free_filter;
3324         }
3325         if (mfilter == NULL && filter_op == RTE_ETH_FILTER_DELETE) {
3326                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
3327                 ret = -ENOENT;
3328                 goto free_filter;
3329         }
3330
3331         if (filter_op == RTE_ETH_FILTER_ADD) {
3332                 bfilter->filter_type = HWRM_CFA_NTUPLE_FILTER;
3333                 ret = bnxt_hwrm_set_ntuple_filter(bp, bfilter->dst_id, bfilter);
3334                 if (ret)
3335                         goto free_filter;
3336                 STAILQ_INSERT_TAIL(&vnic->filter, bfilter, next);
3337         } else {
3338                 if (mfilter == NULL) {
3339                         /* This should not happen. But for Coverity! */
3340                         ret = -ENOENT;
3341                         goto free_filter;
3342                 }
3343                 ret = bnxt_hwrm_clear_ntuple_filter(bp, mfilter);
3344
3345                 STAILQ_REMOVE(&vnic->filter, mfilter, bnxt_filter_info, next);
3346                 bnxt_free_filter(bp, mfilter);
3347                 bnxt_free_filter(bp, bfilter);
3348         }
3349
3350         return 0;
3351 free_filter:
3352         bnxt_free_filter(bp, bfilter);
3353         return ret;
3354 }
3355
3356 static int
3357 bnxt_ntuple_filter(struct rte_eth_dev *dev,
3358                         enum rte_filter_op filter_op,
3359                         void *arg)
3360 {
3361         struct bnxt *bp = dev->data->dev_private;
3362         int ret;
3363
3364         if (filter_op == RTE_ETH_FILTER_NOP)
3365                 return 0;
3366
3367         if (arg == NULL) {
3368                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
3369                             filter_op);
3370                 return -EINVAL;
3371         }
3372
3373         switch (filter_op) {
3374         case RTE_ETH_FILTER_ADD:
3375                 ret = bnxt_cfg_ntuple_filter(bp,
3376                         (struct rte_eth_ntuple_filter *)arg,
3377                         filter_op);
3378                 break;
3379         case RTE_ETH_FILTER_DELETE:
3380                 ret = bnxt_cfg_ntuple_filter(bp,
3381                         (struct rte_eth_ntuple_filter *)arg,
3382                         filter_op);
3383                 break;
3384         default:
3385                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
3386                 ret = -EINVAL;
3387                 break;
3388         }
3389         return ret;
3390 }
3391
3392 static int
3393 bnxt_parse_fdir_filter(struct bnxt *bp,
3394                        struct rte_eth_fdir_filter *fdir,
3395                        struct bnxt_filter_info *filter)
3396 {
3397         enum rte_fdir_mode fdir_mode =
3398                 bp->eth_dev->data->dev_conf.fdir_conf.mode;
3399         struct bnxt_vnic_info *vnic0, *vnic;
3400         struct bnxt_filter_info *filter1;
3401         uint32_t en = 0;
3402         int i;
3403
3404         if (fdir_mode == RTE_FDIR_MODE_PERFECT_TUNNEL)
3405                 return -EINVAL;
3406
3407         filter->l2_ovlan = fdir->input.flow_ext.vlan_tci;
3408         en |= EM_FLOW_ALLOC_INPUT_EN_OVLAN_VID;
3409
3410         switch (fdir->input.flow_type) {
3411         case RTE_ETH_FLOW_IPV4:
3412         case RTE_ETH_FLOW_NONFRAG_IPV4_OTHER:
3413                 /* FALLTHROUGH */
3414                 filter->src_ipaddr[0] = fdir->input.flow.ip4_flow.src_ip;
3415                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
3416                 filter->dst_ipaddr[0] = fdir->input.flow.ip4_flow.dst_ip;
3417                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
3418                 filter->ip_protocol = fdir->input.flow.ip4_flow.proto;
3419                 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
3420                 filter->ip_addr_type =
3421                         NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4;
3422                 filter->src_ipaddr_mask[0] = 0xffffffff;
3423                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
3424                 filter->dst_ipaddr_mask[0] = 0xffffffff;
3425                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
3426                 filter->ethertype = 0x800;
3427                 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
3428                 break;
3429         case RTE_ETH_FLOW_NONFRAG_IPV4_TCP:
3430                 filter->src_port = fdir->input.flow.tcp4_flow.src_port;
3431                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT;
3432                 filter->dst_port = fdir->input.flow.tcp4_flow.dst_port;
3433                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT;
3434                 filter->dst_port_mask = 0xffff;
3435                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
3436                 filter->src_port_mask = 0xffff;
3437                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
3438                 filter->src_ipaddr[0] = fdir->input.flow.tcp4_flow.ip.src_ip;
3439                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
3440                 filter->dst_ipaddr[0] = fdir->input.flow.tcp4_flow.ip.dst_ip;
3441                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
3442                 filter->ip_protocol = 6;
3443                 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
3444                 filter->ip_addr_type =
3445                         NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4;
3446                 filter->src_ipaddr_mask[0] = 0xffffffff;
3447                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
3448                 filter->dst_ipaddr_mask[0] = 0xffffffff;
3449                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
3450                 filter->ethertype = 0x800;
3451                 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
3452                 break;
3453         case RTE_ETH_FLOW_NONFRAG_IPV4_UDP:
3454                 filter->src_port = fdir->input.flow.udp4_flow.src_port;
3455                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT;
3456                 filter->dst_port = fdir->input.flow.udp4_flow.dst_port;
3457                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT;
3458                 filter->dst_port_mask = 0xffff;
3459                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
3460                 filter->src_port_mask = 0xffff;
3461                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
3462                 filter->src_ipaddr[0] = fdir->input.flow.udp4_flow.ip.src_ip;
3463                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
3464                 filter->dst_ipaddr[0] = fdir->input.flow.udp4_flow.ip.dst_ip;
3465                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
3466                 filter->ip_protocol = 17;
3467                 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
3468                 filter->ip_addr_type =
3469                         NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4;
3470                 filter->src_ipaddr_mask[0] = 0xffffffff;
3471                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
3472                 filter->dst_ipaddr_mask[0] = 0xffffffff;
3473                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
3474                 filter->ethertype = 0x800;
3475                 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
3476                 break;
3477         case RTE_ETH_FLOW_IPV6:
3478         case RTE_ETH_FLOW_NONFRAG_IPV6_OTHER:
3479                 /* FALLTHROUGH */
3480                 filter->ip_addr_type =
3481                         NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV6;
3482                 filter->ip_protocol = fdir->input.flow.ipv6_flow.proto;
3483                 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
3484                 rte_memcpy(filter->src_ipaddr,
3485                            fdir->input.flow.ipv6_flow.src_ip, 16);
3486                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
3487                 rte_memcpy(filter->dst_ipaddr,
3488                            fdir->input.flow.ipv6_flow.dst_ip, 16);
3489                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
3490                 memset(filter->dst_ipaddr_mask, 0xff, 16);
3491                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
3492                 memset(filter->src_ipaddr_mask, 0xff, 16);
3493                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
3494                 filter->ethertype = 0x86dd;
3495                 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
3496                 break;
3497         case RTE_ETH_FLOW_NONFRAG_IPV6_TCP:
3498                 filter->src_port = fdir->input.flow.tcp6_flow.src_port;
3499                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT;
3500                 filter->dst_port = fdir->input.flow.tcp6_flow.dst_port;
3501                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT;
3502                 filter->dst_port_mask = 0xffff;
3503                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
3504                 filter->src_port_mask = 0xffff;
3505                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
3506                 filter->ip_addr_type =
3507                         NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV6;
3508                 filter->ip_protocol = fdir->input.flow.tcp6_flow.ip.proto;
3509                 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
3510                 rte_memcpy(filter->src_ipaddr,
3511                            fdir->input.flow.tcp6_flow.ip.src_ip, 16);
3512                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
3513                 rte_memcpy(filter->dst_ipaddr,
3514                            fdir->input.flow.tcp6_flow.ip.dst_ip, 16);
3515                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
3516                 memset(filter->dst_ipaddr_mask, 0xff, 16);
3517                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
3518                 memset(filter->src_ipaddr_mask, 0xff, 16);
3519                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
3520                 filter->ethertype = 0x86dd;
3521                 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
3522                 break;
3523         case RTE_ETH_FLOW_NONFRAG_IPV6_UDP:
3524                 filter->src_port = fdir->input.flow.udp6_flow.src_port;
3525                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT;
3526                 filter->dst_port = fdir->input.flow.udp6_flow.dst_port;
3527                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT;
3528                 filter->dst_port_mask = 0xffff;
3529                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
3530                 filter->src_port_mask = 0xffff;
3531                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
3532                 filter->ip_addr_type =
3533                         NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV6;
3534                 filter->ip_protocol = fdir->input.flow.udp6_flow.ip.proto;
3535                 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
3536                 rte_memcpy(filter->src_ipaddr,
3537                            fdir->input.flow.udp6_flow.ip.src_ip, 16);
3538                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
3539                 rte_memcpy(filter->dst_ipaddr,
3540                            fdir->input.flow.udp6_flow.ip.dst_ip, 16);
3541                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
3542                 memset(filter->dst_ipaddr_mask, 0xff, 16);
3543                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
3544                 memset(filter->src_ipaddr_mask, 0xff, 16);
3545                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
3546                 filter->ethertype = 0x86dd;
3547                 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
3548                 break;
3549         case RTE_ETH_FLOW_L2_PAYLOAD:
3550                 filter->ethertype = fdir->input.flow.l2_flow.ether_type;
3551                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
3552                 break;
3553         case RTE_ETH_FLOW_VXLAN:
3554                 if (fdir->action.behavior == RTE_ETH_FDIR_REJECT)
3555                         return -EINVAL;
3556                 filter->vni = fdir->input.flow.tunnel_flow.tunnel_id;
3557                 filter->tunnel_type =
3558                         CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN;
3559                 en |= HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_TUNNEL_TYPE;
3560                 break;
3561         case RTE_ETH_FLOW_NVGRE:
3562                 if (fdir->action.behavior == RTE_ETH_FDIR_REJECT)
3563                         return -EINVAL;
3564                 filter->vni = fdir->input.flow.tunnel_flow.tunnel_id;
3565                 filter->tunnel_type =
3566                         CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_NVGRE;
3567                 en |= HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_TUNNEL_TYPE;
3568                 break;
3569         case RTE_ETH_FLOW_UNKNOWN:
3570         case RTE_ETH_FLOW_RAW:
3571         case RTE_ETH_FLOW_FRAG_IPV4:
3572         case RTE_ETH_FLOW_NONFRAG_IPV4_SCTP:
3573         case RTE_ETH_FLOW_FRAG_IPV6:
3574         case RTE_ETH_FLOW_NONFRAG_IPV6_SCTP:
3575         case RTE_ETH_FLOW_IPV6_EX:
3576         case RTE_ETH_FLOW_IPV6_TCP_EX:
3577         case RTE_ETH_FLOW_IPV6_UDP_EX:
3578         case RTE_ETH_FLOW_GENEVE:
3579                 /* FALLTHROUGH */
3580         default:
3581                 return -EINVAL;
3582         }
3583
3584         vnic0 = BNXT_GET_DEFAULT_VNIC(bp);
3585         vnic = &bp->vnic_info[fdir->action.rx_queue];
3586         if (vnic == NULL) {
3587                 PMD_DRV_LOG(ERR, "Invalid queue %d\n", fdir->action.rx_queue);
3588                 return -EINVAL;
3589         }
3590
3591         if (fdir_mode == RTE_FDIR_MODE_PERFECT_MAC_VLAN) {
3592                 rte_memcpy(filter->dst_macaddr,
3593                         fdir->input.flow.mac_vlan_flow.mac_addr.addr_bytes, 6);
3594                         en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_MACADDR;
3595         }
3596
3597         if (fdir->action.behavior == RTE_ETH_FDIR_REJECT) {
3598                 filter->flags = HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_DROP;
3599                 filter1 = STAILQ_FIRST(&vnic0->filter);
3600                 //filter1 = bnxt_get_l2_filter(bp, filter, vnic0);
3601         } else {
3602                 filter->dst_id = vnic->fw_vnic_id;
3603                 for (i = 0; i < RTE_ETHER_ADDR_LEN; i++)
3604                         if (filter->dst_macaddr[i] == 0x00)
3605                                 filter1 = STAILQ_FIRST(&vnic0->filter);
3606                         else
3607                                 filter1 = bnxt_get_l2_filter(bp, filter, vnic);
3608         }
3609
3610         if (filter1 == NULL)
3611                 return -EINVAL;
3612
3613         en |= HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID;
3614         filter->fw_l2_filter_id = filter1->fw_l2_filter_id;
3615
3616         filter->enables = en;
3617
3618         return 0;
3619 }
3620
3621 static struct bnxt_filter_info *
3622 bnxt_match_fdir(struct bnxt *bp, struct bnxt_filter_info *nf,
3623                 struct bnxt_vnic_info **mvnic)
3624 {
3625         struct bnxt_filter_info *mf = NULL;
3626         int i;
3627
3628         for (i = bp->nr_vnics - 1; i >= 0; i--) {
3629                 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
3630
3631                 STAILQ_FOREACH(mf, &vnic->filter, next) {
3632                         if (mf->filter_type == nf->filter_type &&
3633                             mf->flags == nf->flags &&
3634                             mf->src_port == nf->src_port &&
3635                             mf->src_port_mask == nf->src_port_mask &&
3636                             mf->dst_port == nf->dst_port &&
3637                             mf->dst_port_mask == nf->dst_port_mask &&
3638                             mf->ip_protocol == nf->ip_protocol &&
3639                             mf->ip_addr_type == nf->ip_addr_type &&
3640                             mf->ethertype == nf->ethertype &&
3641                             mf->vni == nf->vni &&
3642                             mf->tunnel_type == nf->tunnel_type &&
3643                             mf->l2_ovlan == nf->l2_ovlan &&
3644                             mf->l2_ovlan_mask == nf->l2_ovlan_mask &&
3645                             mf->l2_ivlan == nf->l2_ivlan &&
3646                             mf->l2_ivlan_mask == nf->l2_ivlan_mask &&
3647                             !memcmp(mf->l2_addr, nf->l2_addr,
3648                                     RTE_ETHER_ADDR_LEN) &&
3649                             !memcmp(mf->l2_addr_mask, nf->l2_addr_mask,
3650                                     RTE_ETHER_ADDR_LEN) &&
3651                             !memcmp(mf->src_macaddr, nf->src_macaddr,
3652                                     RTE_ETHER_ADDR_LEN) &&
3653                             !memcmp(mf->dst_macaddr, nf->dst_macaddr,
3654                                     RTE_ETHER_ADDR_LEN) &&
3655                             !memcmp(mf->src_ipaddr, nf->src_ipaddr,
3656                                     sizeof(nf->src_ipaddr)) &&
3657                             !memcmp(mf->src_ipaddr_mask, nf->src_ipaddr_mask,
3658                                     sizeof(nf->src_ipaddr_mask)) &&
3659                             !memcmp(mf->dst_ipaddr, nf->dst_ipaddr,
3660                                     sizeof(nf->dst_ipaddr)) &&
3661                             !memcmp(mf->dst_ipaddr_mask, nf->dst_ipaddr_mask,
3662                                     sizeof(nf->dst_ipaddr_mask))) {
3663                                 if (mvnic)
3664                                         *mvnic = vnic;
3665                                 return mf;
3666                         }
3667                 }
3668         }
3669         return NULL;
3670 }
3671
3672 static int
3673 bnxt_fdir_filter(struct rte_eth_dev *dev,
3674                  enum rte_filter_op filter_op,
3675                  void *arg)
3676 {
3677         struct bnxt *bp = dev->data->dev_private;
3678         struct rte_eth_fdir_filter *fdir  = (struct rte_eth_fdir_filter *)arg;
3679         struct bnxt_filter_info *filter, *match;
3680         struct bnxt_vnic_info *vnic, *mvnic;
3681         int ret = 0, i;
3682
3683         if (filter_op == RTE_ETH_FILTER_NOP)
3684                 return 0;
3685
3686         if (arg == NULL && filter_op != RTE_ETH_FILTER_FLUSH)
3687                 return -EINVAL;
3688
3689         switch (filter_op) {
3690         case RTE_ETH_FILTER_ADD:
3691         case RTE_ETH_FILTER_DELETE:
3692                 /* FALLTHROUGH */
3693                 filter = bnxt_get_unused_filter(bp);
3694                 if (filter == NULL) {
3695                         PMD_DRV_LOG(ERR,
3696                                 "Not enough resources for a new flow.\n");
3697                         return -ENOMEM;
3698                 }
3699
3700                 ret = bnxt_parse_fdir_filter(bp, fdir, filter);
3701                 if (ret != 0)
3702                         goto free_filter;
3703                 filter->filter_type = HWRM_CFA_NTUPLE_FILTER;
3704
3705                 if (fdir->action.behavior == RTE_ETH_FDIR_REJECT)
3706                         vnic = &bp->vnic_info[0];
3707                 else
3708                         vnic = &bp->vnic_info[fdir->action.rx_queue];
3709
3710                 match = bnxt_match_fdir(bp, filter, &mvnic);
3711                 if (match != NULL && filter_op == RTE_ETH_FILTER_ADD) {
3712                         if (match->dst_id == vnic->fw_vnic_id) {
3713                                 PMD_DRV_LOG(ERR, "Flow already exists.\n");
3714                                 ret = -EEXIST;
3715                                 goto free_filter;
3716                         } else {
3717                                 match->dst_id = vnic->fw_vnic_id;
3718                                 ret = bnxt_hwrm_set_ntuple_filter(bp,
3719                                                                   match->dst_id,
3720                                                                   match);
3721                                 STAILQ_REMOVE(&mvnic->filter, match,
3722                                               bnxt_filter_info, next);
3723                                 STAILQ_INSERT_TAIL(&vnic->filter, match, next);
3724                                 PMD_DRV_LOG(ERR,
3725                                         "Filter with matching pattern exist\n");
3726                                 PMD_DRV_LOG(ERR,
3727                                         "Updated it to new destination q\n");
3728                                 goto free_filter;
3729                         }
3730                 }
3731                 if (match == NULL && filter_op == RTE_ETH_FILTER_DELETE) {
3732                         PMD_DRV_LOG(ERR, "Flow does not exist.\n");
3733                         ret = -ENOENT;
3734                         goto free_filter;
3735                 }
3736
3737                 if (filter_op == RTE_ETH_FILTER_ADD) {
3738                         ret = bnxt_hwrm_set_ntuple_filter(bp,
3739                                                           filter->dst_id,
3740                                                           filter);
3741                         if (ret)
3742                                 goto free_filter;
3743                         STAILQ_INSERT_TAIL(&vnic->filter, filter, next);
3744                 } else {
3745                         ret = bnxt_hwrm_clear_ntuple_filter(bp, match);
3746                         STAILQ_REMOVE(&vnic->filter, match,
3747                                       bnxt_filter_info, next);
3748                         bnxt_free_filter(bp, match);
3749                         bnxt_free_filter(bp, filter);
3750                 }
3751                 break;
3752         case RTE_ETH_FILTER_FLUSH:
3753                 for (i = bp->nr_vnics - 1; i >= 0; i--) {
3754                         struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
3755
3756                         STAILQ_FOREACH(filter, &vnic->filter, next) {
3757                                 if (filter->filter_type ==
3758                                     HWRM_CFA_NTUPLE_FILTER) {
3759                                         ret =
3760                                         bnxt_hwrm_clear_ntuple_filter(bp,
3761                                                                       filter);
3762                                         STAILQ_REMOVE(&vnic->filter, filter,
3763                                                       bnxt_filter_info, next);
3764                                 }
3765                         }
3766                 }
3767                 return ret;
3768         case RTE_ETH_FILTER_UPDATE:
3769         case RTE_ETH_FILTER_STATS:
3770         case RTE_ETH_FILTER_INFO:
3771                 PMD_DRV_LOG(ERR, "operation %u not implemented", filter_op);
3772                 break;
3773         default:
3774                 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
3775                 ret = -EINVAL;
3776                 break;
3777         }
3778         return ret;
3779
3780 free_filter:
3781         bnxt_free_filter(bp, filter);
3782         return ret;
3783 }
3784
3785 int
3786 bnxt_filter_ctrl_op(struct rte_eth_dev *dev,
3787                     enum rte_filter_type filter_type,
3788                     enum rte_filter_op filter_op, void *arg)
3789 {
3790         struct bnxt *bp = dev->data->dev_private;
3791         int ret = 0;
3792
3793         if (!bp)
3794                 return -EIO;
3795
3796         if (BNXT_ETH_DEV_IS_REPRESENTOR(dev)) {
3797                 struct bnxt_representor *vfr = dev->data->dev_private;
3798                 bp = vfr->parent_dev->data->dev_private;
3799                 /* parent is deleted while children are still valid */
3800                 if (!bp) {
3801                         PMD_DRV_LOG(DEBUG, "BNXT Port:%d VFR Error %d:%d\n",
3802                                     dev->data->port_id,
3803                                     filter_type,
3804                                     filter_op);
3805                         return -EIO;
3806                 }
3807         }
3808
3809         ret = is_bnxt_in_error(bp);
3810         if (ret)
3811                 return ret;
3812
3813         switch (filter_type) {
3814         case RTE_ETH_FILTER_TUNNEL:
3815                 PMD_DRV_LOG(ERR,
3816                         "filter type: %d: To be implemented\n", filter_type);
3817                 break;
3818         case RTE_ETH_FILTER_FDIR:
3819                 ret = bnxt_fdir_filter(dev, filter_op, arg);
3820                 break;
3821         case RTE_ETH_FILTER_NTUPLE:
3822                 ret = bnxt_ntuple_filter(dev, filter_op, arg);
3823                 break;
3824         case RTE_ETH_FILTER_ETHERTYPE:
3825                 ret = bnxt_ethertype_filter(dev, filter_op, arg);
3826                 break;
3827         case RTE_ETH_FILTER_GENERIC:
3828                 if (filter_op != RTE_ETH_FILTER_GET)
3829                         return -EINVAL;
3830                 if (BNXT_TRUFLOW_EN(bp))
3831                         *(const void **)arg = &bnxt_ulp_rte_flow_ops;
3832                 else
3833                         *(const void **)arg = &bnxt_flow_ops;
3834                 break;
3835         default:
3836                 PMD_DRV_LOG(ERR,
3837                         "Filter type (%d) not supported", filter_type);
3838                 ret = -EINVAL;
3839                 break;
3840         }
3841         return ret;
3842 }
3843
3844 static const uint32_t *
3845 bnxt_dev_supported_ptypes_get_op(struct rte_eth_dev *dev)
3846 {
3847         static const uint32_t ptypes[] = {
3848                 RTE_PTYPE_L2_ETHER_VLAN,
3849                 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN,
3850                 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN,
3851                 RTE_PTYPE_L4_ICMP,
3852                 RTE_PTYPE_L4_TCP,
3853                 RTE_PTYPE_L4_UDP,
3854                 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN,
3855                 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN,
3856                 RTE_PTYPE_INNER_L4_ICMP,
3857                 RTE_PTYPE_INNER_L4_TCP,
3858                 RTE_PTYPE_INNER_L4_UDP,
3859                 RTE_PTYPE_UNKNOWN
3860         };
3861
3862         if (!dev->rx_pkt_burst)
3863                 return NULL;
3864
3865         return ptypes;
3866 }
3867
3868 static int bnxt_map_regs(struct bnxt *bp, uint32_t *reg_arr, int count,
3869                          int reg_win)
3870 {
3871         uint32_t reg_base = *reg_arr & 0xfffff000;
3872         uint32_t win_off;
3873         int i;
3874
3875         for (i = 0; i < count; i++) {
3876                 if ((reg_arr[i] & 0xfffff000) != reg_base)
3877                         return -ERANGE;
3878         }
3879         win_off = BNXT_GRCPF_REG_WINDOW_BASE_OUT + (reg_win - 1) * 4;
3880         rte_write32(reg_base, (uint8_t *)bp->bar0 + win_off);
3881         return 0;
3882 }
3883
3884 static int bnxt_map_ptp_regs(struct bnxt *bp)
3885 {
3886         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3887         uint32_t *reg_arr;
3888         int rc, i;
3889
3890         reg_arr = ptp->rx_regs;
3891         rc = bnxt_map_regs(bp, reg_arr, BNXT_PTP_RX_REGS, 5);
3892         if (rc)
3893                 return rc;
3894
3895         reg_arr = ptp->tx_regs;
3896         rc = bnxt_map_regs(bp, reg_arr, BNXT_PTP_TX_REGS, 6);
3897         if (rc)
3898                 return rc;
3899
3900         for (i = 0; i < BNXT_PTP_RX_REGS; i++)
3901                 ptp->rx_mapped_regs[i] = 0x5000 + (ptp->rx_regs[i] & 0xfff);
3902
3903         for (i = 0; i < BNXT_PTP_TX_REGS; i++)
3904                 ptp->tx_mapped_regs[i] = 0x6000 + (ptp->tx_regs[i] & 0xfff);
3905
3906         return 0;
3907 }
3908
3909 static void bnxt_unmap_ptp_regs(struct bnxt *bp)
3910 {
3911         rte_write32(0, (uint8_t *)bp->bar0 +
3912                          BNXT_GRCPF_REG_WINDOW_BASE_OUT + 16);
3913         rte_write32(0, (uint8_t *)bp->bar0 +
3914                          BNXT_GRCPF_REG_WINDOW_BASE_OUT + 20);
3915 }
3916
3917 static uint64_t bnxt_cc_read(struct bnxt *bp)
3918 {
3919         uint64_t ns;
3920
3921         ns = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3922                               BNXT_GRCPF_REG_SYNC_TIME));
3923         ns |= (uint64_t)(rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3924                                           BNXT_GRCPF_REG_SYNC_TIME + 4))) << 32;
3925         return ns;
3926 }
3927
3928 static int bnxt_get_tx_ts(struct bnxt *bp, uint64_t *ts)
3929 {
3930         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3931         uint32_t fifo;
3932
3933         fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3934                                 ptp->tx_mapped_regs[BNXT_PTP_TX_FIFO]));
3935         if (fifo & BNXT_PTP_TX_FIFO_EMPTY)
3936                 return -EAGAIN;
3937
3938         fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3939                                 ptp->tx_mapped_regs[BNXT_PTP_TX_FIFO]));
3940         *ts = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3941                                 ptp->tx_mapped_regs[BNXT_PTP_TX_TS_L]));
3942         *ts |= (uint64_t)rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3943                                 ptp->tx_mapped_regs[BNXT_PTP_TX_TS_H])) << 32;
3944
3945         return 0;
3946 }
3947
3948 static int bnxt_get_rx_ts(struct bnxt *bp, uint64_t *ts)
3949 {
3950         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3951         struct bnxt_pf_info *pf = bp->pf;
3952         uint16_t port_id;
3953         uint32_t fifo;
3954
3955         if (!ptp)
3956                 return -ENODEV;
3957
3958         fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3959                                 ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO]));
3960         if (!(fifo & BNXT_PTP_RX_FIFO_PENDING))
3961                 return -EAGAIN;
3962
3963         port_id = pf->port_id;
3964         rte_write32(1 << port_id, (uint8_t *)bp->bar0 +
3965                ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO_ADV]);
3966
3967         fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3968                                    ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO]));
3969         if (fifo & BNXT_PTP_RX_FIFO_PENDING) {
3970 /*              bnxt_clr_rx_ts(bp);       TBD  */
3971                 return -EBUSY;
3972         }
3973
3974         *ts = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3975                                 ptp->rx_mapped_regs[BNXT_PTP_RX_TS_L]));
3976         *ts |= (uint64_t)rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3977                                 ptp->rx_mapped_regs[BNXT_PTP_RX_TS_H])) << 32;
3978
3979         return 0;
3980 }
3981
3982 static int
3983 bnxt_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
3984 {
3985         uint64_t ns;
3986         struct bnxt *bp = dev->data->dev_private;
3987         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3988
3989         if (!ptp)
3990                 return 0;
3991
3992         ns = rte_timespec_to_ns(ts);
3993         /* Set the timecounters to a new value. */
3994         ptp->tc.nsec = ns;
3995
3996         return 0;
3997 }
3998
3999 static int
4000 bnxt_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
4001 {
4002         struct bnxt *bp = dev->data->dev_private;
4003         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
4004         uint64_t ns, systime_cycles = 0;
4005         int rc = 0;
4006
4007         if (!ptp)
4008                 return 0;
4009
4010         if (BNXT_CHIP_THOR(bp))
4011                 rc = bnxt_hwrm_port_ts_query(bp, BNXT_PTP_FLAGS_CURRENT_TIME,
4012                                              &systime_cycles);
4013         else
4014                 systime_cycles = bnxt_cc_read(bp);
4015
4016         ns = rte_timecounter_update(&ptp->tc, systime_cycles);
4017         *ts = rte_ns_to_timespec(ns);
4018
4019         return rc;
4020 }
4021 static int
4022 bnxt_timesync_enable(struct rte_eth_dev *dev)
4023 {
4024         struct bnxt *bp = dev->data->dev_private;
4025         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
4026         uint32_t shift = 0;
4027         int rc;
4028
4029         if (!ptp)
4030                 return 0;
4031
4032         ptp->rx_filter = 1;
4033         ptp->tx_tstamp_en = 1;
4034         ptp->rxctl = BNXT_PTP_MSG_EVENTS;
4035
4036         rc = bnxt_hwrm_ptp_cfg(bp);
4037         if (rc)
4038                 return rc;
4039
4040         memset(&ptp->tc, 0, sizeof(struct rte_timecounter));
4041         memset(&ptp->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
4042         memset(&ptp->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
4043
4044         ptp->tc.cc_mask = BNXT_CYCLECOUNTER_MASK;
4045         ptp->tc.cc_shift = shift;
4046         ptp->tc.nsec_mask = (1ULL << shift) - 1;
4047
4048         ptp->rx_tstamp_tc.cc_mask = BNXT_CYCLECOUNTER_MASK;
4049         ptp->rx_tstamp_tc.cc_shift = shift;
4050         ptp->rx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
4051
4052         ptp->tx_tstamp_tc.cc_mask = BNXT_CYCLECOUNTER_MASK;
4053         ptp->tx_tstamp_tc.cc_shift = shift;
4054         ptp->tx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
4055
4056         if (!BNXT_CHIP_THOR(bp))
4057                 bnxt_map_ptp_regs(bp);
4058
4059         return 0;
4060 }
4061
4062 static int
4063 bnxt_timesync_disable(struct rte_eth_dev *dev)
4064 {
4065         struct bnxt *bp = dev->data->dev_private;
4066         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
4067
4068         if (!ptp)
4069                 return 0;
4070
4071         ptp->rx_filter = 0;
4072         ptp->tx_tstamp_en = 0;
4073         ptp->rxctl = 0;
4074
4075         bnxt_hwrm_ptp_cfg(bp);
4076
4077         if (!BNXT_CHIP_THOR(bp))
4078                 bnxt_unmap_ptp_regs(bp);
4079
4080         return 0;
4081 }
4082
4083 static int
4084 bnxt_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
4085                                  struct timespec *timestamp,
4086                                  uint32_t flags __rte_unused)
4087 {
4088         struct bnxt *bp = dev->data->dev_private;
4089         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
4090         uint64_t rx_tstamp_cycles = 0;
4091         uint64_t ns;
4092
4093         if (!ptp)
4094                 return 0;
4095
4096         if (BNXT_CHIP_THOR(bp))
4097                 rx_tstamp_cycles = ptp->rx_timestamp;
4098         else
4099                 bnxt_get_rx_ts(bp, &rx_tstamp_cycles);
4100
4101         ns = rte_timecounter_update(&ptp->rx_tstamp_tc, rx_tstamp_cycles);
4102         *timestamp = rte_ns_to_timespec(ns);
4103         return  0;
4104 }
4105
4106 static int
4107 bnxt_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
4108                                  struct timespec *timestamp)
4109 {
4110         struct bnxt *bp = dev->data->dev_private;
4111         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
4112         uint64_t tx_tstamp_cycles = 0;
4113         uint64_t ns;
4114         int rc = 0;
4115
4116         if (!ptp)
4117                 return 0;
4118
4119         if (BNXT_CHIP_THOR(bp))
4120                 rc = bnxt_hwrm_port_ts_query(bp, BNXT_PTP_FLAGS_PATH_TX,
4121                                              &tx_tstamp_cycles);
4122         else
4123                 rc = bnxt_get_tx_ts(bp, &tx_tstamp_cycles);
4124
4125         ns = rte_timecounter_update(&ptp->tx_tstamp_tc, tx_tstamp_cycles);
4126         *timestamp = rte_ns_to_timespec(ns);
4127
4128         return rc;
4129 }
4130
4131 static int
4132 bnxt_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
4133 {
4134         struct bnxt *bp = dev->data->dev_private;
4135         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
4136
4137         if (!ptp)
4138                 return 0;
4139
4140         ptp->tc.nsec += delta;
4141
4142         return 0;
4143 }
4144
4145 static int
4146 bnxt_get_eeprom_length_op(struct rte_eth_dev *dev)
4147 {
4148         struct bnxt *bp = dev->data->dev_private;
4149         int rc;
4150         uint32_t dir_entries;
4151         uint32_t entry_length;
4152
4153         rc = is_bnxt_in_error(bp);
4154         if (rc)
4155                 return rc;
4156
4157         PMD_DRV_LOG(INFO, PCI_PRI_FMT "\n",
4158                     bp->pdev->addr.domain, bp->pdev->addr.bus,
4159                     bp->pdev->addr.devid, bp->pdev->addr.function);
4160
4161         rc = bnxt_hwrm_nvm_get_dir_info(bp, &dir_entries, &entry_length);
4162         if (rc != 0)
4163                 return rc;
4164
4165         return dir_entries * entry_length;
4166 }
4167
4168 static int
4169 bnxt_get_eeprom_op(struct rte_eth_dev *dev,
4170                 struct rte_dev_eeprom_info *in_eeprom)
4171 {
4172         struct bnxt *bp = dev->data->dev_private;
4173         uint32_t index;
4174         uint32_t offset;
4175         int rc;
4176
4177         rc = is_bnxt_in_error(bp);
4178         if (rc)
4179                 return rc;
4180
4181         PMD_DRV_LOG(INFO, PCI_PRI_FMT " in_eeprom->offset = %d len = %d\n",
4182                     bp->pdev->addr.domain, bp->pdev->addr.bus,
4183                     bp->pdev->addr.devid, bp->pdev->addr.function,
4184                     in_eeprom->offset, in_eeprom->length);
4185
4186         if (in_eeprom->offset == 0) /* special offset value to get directory */
4187                 return bnxt_get_nvram_directory(bp, in_eeprom->length,
4188                                                 in_eeprom->data);
4189
4190         index = in_eeprom->offset >> 24;
4191         offset = in_eeprom->offset & 0xffffff;
4192
4193         if (index != 0)
4194                 return bnxt_hwrm_get_nvram_item(bp, index - 1, offset,
4195                                            in_eeprom->length, in_eeprom->data);
4196
4197         return 0;
4198 }
4199
4200 static bool bnxt_dir_type_is_ape_bin_format(uint16_t dir_type)
4201 {
4202         switch (dir_type) {
4203         case BNX_DIR_TYPE_CHIMP_PATCH:
4204         case BNX_DIR_TYPE_BOOTCODE:
4205         case BNX_DIR_TYPE_BOOTCODE_2:
4206         case BNX_DIR_TYPE_APE_FW:
4207         case BNX_DIR_TYPE_APE_PATCH:
4208         case BNX_DIR_TYPE_KONG_FW:
4209         case BNX_DIR_TYPE_KONG_PATCH:
4210         case BNX_DIR_TYPE_BONO_FW:
4211         case BNX_DIR_TYPE_BONO_PATCH:
4212                 /* FALLTHROUGH */
4213                 return true;
4214         }
4215
4216         return false;
4217 }
4218
4219 static bool bnxt_dir_type_is_other_exec_format(uint16_t dir_type)
4220 {
4221         switch (dir_type) {
4222         case BNX_DIR_TYPE_AVS:
4223         case BNX_DIR_TYPE_EXP_ROM_MBA:
4224         case BNX_DIR_TYPE_PCIE:
4225         case BNX_DIR_TYPE_TSCF_UCODE:
4226         case BNX_DIR_TYPE_EXT_PHY:
4227         case BNX_DIR_TYPE_CCM:
4228         case BNX_DIR_TYPE_ISCSI_BOOT:
4229         case BNX_DIR_TYPE_ISCSI_BOOT_IPV6:
4230         case BNX_DIR_TYPE_ISCSI_BOOT_IPV4N6:
4231                 /* FALLTHROUGH */
4232                 return true;
4233         }
4234
4235         return false;
4236 }
4237
4238 static bool bnxt_dir_type_is_executable(uint16_t dir_type)
4239 {
4240         return bnxt_dir_type_is_ape_bin_format(dir_type) ||
4241                 bnxt_dir_type_is_other_exec_format(dir_type);
4242 }
4243
4244 static int
4245 bnxt_set_eeprom_op(struct rte_eth_dev *dev,
4246                 struct rte_dev_eeprom_info *in_eeprom)
4247 {
4248         struct bnxt *bp = dev->data->dev_private;
4249         uint8_t index, dir_op;
4250         uint16_t type, ext, ordinal, attr;
4251         int rc;
4252
4253         rc = is_bnxt_in_error(bp);
4254         if (rc)
4255                 return rc;
4256
4257         PMD_DRV_LOG(INFO, PCI_PRI_FMT " in_eeprom->offset = %d len = %d\n",
4258                     bp->pdev->addr.domain, bp->pdev->addr.bus,
4259                     bp->pdev->addr.devid, bp->pdev->addr.function,
4260                     in_eeprom->offset, in_eeprom->length);
4261
4262         if (!BNXT_PF(bp)) {
4263                 PMD_DRV_LOG(ERR, "NVM write not supported from a VF\n");
4264                 return -EINVAL;
4265         }
4266
4267         type = in_eeprom->magic >> 16;
4268
4269         if (type == 0xffff) { /* special value for directory operations */
4270                 index = in_eeprom->magic & 0xff;
4271                 dir_op = in_eeprom->magic >> 8;
4272                 if (index == 0)
4273                         return -EINVAL;
4274                 switch (dir_op) {
4275                 case 0x0e: /* erase */
4276                         if (in_eeprom->offset != ~in_eeprom->magic)
4277                                 return -EINVAL;
4278                         return bnxt_hwrm_erase_nvram_directory(bp, index - 1);
4279                 default:
4280                         return -EINVAL;
4281                 }
4282         }
4283
4284         /* Create or re-write an NVM item: */
4285         if (bnxt_dir_type_is_executable(type) == true)
4286                 return -EOPNOTSUPP;
4287         ext = in_eeprom->magic & 0xffff;
4288         ordinal = in_eeprom->offset >> 16;
4289         attr = in_eeprom->offset & 0xffff;
4290
4291         return bnxt_hwrm_flash_nvram(bp, type, ordinal, ext, attr,
4292                                      in_eeprom->data, in_eeprom->length);
4293 }
4294
4295 /*
4296  * Initialization
4297  */
4298
4299 static const struct eth_dev_ops bnxt_dev_ops = {
4300         .dev_infos_get = bnxt_dev_info_get_op,
4301         .dev_close = bnxt_dev_close_op,
4302         .dev_configure = bnxt_dev_configure_op,
4303         .dev_start = bnxt_dev_start_op,
4304         .dev_stop = bnxt_dev_stop_op,
4305         .dev_set_link_up = bnxt_dev_set_link_up_op,
4306         .dev_set_link_down = bnxt_dev_set_link_down_op,
4307         .stats_get = bnxt_stats_get_op,
4308         .stats_reset = bnxt_stats_reset_op,
4309         .rx_queue_setup = bnxt_rx_queue_setup_op,
4310         .rx_queue_release = bnxt_rx_queue_release_op,
4311         .tx_queue_setup = bnxt_tx_queue_setup_op,
4312         .tx_queue_release = bnxt_tx_queue_release_op,
4313         .rx_queue_intr_enable = bnxt_rx_queue_intr_enable_op,
4314         .rx_queue_intr_disable = bnxt_rx_queue_intr_disable_op,
4315         .reta_update = bnxt_reta_update_op,
4316         .reta_query = bnxt_reta_query_op,
4317         .rss_hash_update = bnxt_rss_hash_update_op,
4318         .rss_hash_conf_get = bnxt_rss_hash_conf_get_op,
4319         .link_update = bnxt_link_update_op,
4320         .promiscuous_enable = bnxt_promiscuous_enable_op,
4321         .promiscuous_disable = bnxt_promiscuous_disable_op,
4322         .allmulticast_enable = bnxt_allmulticast_enable_op,
4323         .allmulticast_disable = bnxt_allmulticast_disable_op,
4324         .mac_addr_add = bnxt_mac_addr_add_op,
4325         .mac_addr_remove = bnxt_mac_addr_remove_op,
4326         .flow_ctrl_get = bnxt_flow_ctrl_get_op,
4327         .flow_ctrl_set = bnxt_flow_ctrl_set_op,
4328         .udp_tunnel_port_add  = bnxt_udp_tunnel_port_add_op,
4329         .udp_tunnel_port_del  = bnxt_udp_tunnel_port_del_op,
4330         .vlan_filter_set = bnxt_vlan_filter_set_op,
4331         .vlan_offload_set = bnxt_vlan_offload_set_op,
4332         .vlan_tpid_set = bnxt_vlan_tpid_set_op,
4333         .vlan_pvid_set = bnxt_vlan_pvid_set_op,
4334         .mtu_set = bnxt_mtu_set_op,
4335         .mac_addr_set = bnxt_set_default_mac_addr_op,
4336         .xstats_get = bnxt_dev_xstats_get_op,
4337         .xstats_get_names = bnxt_dev_xstats_get_names_op,
4338         .xstats_reset = bnxt_dev_xstats_reset_op,
4339         .fw_version_get = bnxt_fw_version_get,
4340         .set_mc_addr_list = bnxt_dev_set_mc_addr_list_op,
4341         .rxq_info_get = bnxt_rxq_info_get_op,
4342         .txq_info_get = bnxt_txq_info_get_op,
4343         .rx_burst_mode_get = bnxt_rx_burst_mode_get,
4344         .tx_burst_mode_get = bnxt_tx_burst_mode_get,
4345         .dev_led_on = bnxt_dev_led_on_op,
4346         .dev_led_off = bnxt_dev_led_off_op,
4347         .xstats_get_by_id = bnxt_dev_xstats_get_by_id_op,
4348         .xstats_get_names_by_id = bnxt_dev_xstats_get_names_by_id_op,
4349         .rx_queue_start = bnxt_rx_queue_start,
4350         .rx_queue_stop = bnxt_rx_queue_stop,
4351         .tx_queue_start = bnxt_tx_queue_start,
4352         .tx_queue_stop = bnxt_tx_queue_stop,
4353         .filter_ctrl = bnxt_filter_ctrl_op,
4354         .dev_supported_ptypes_get = bnxt_dev_supported_ptypes_get_op,
4355         .get_eeprom_length    = bnxt_get_eeprom_length_op,
4356         .get_eeprom           = bnxt_get_eeprom_op,
4357         .set_eeprom           = bnxt_set_eeprom_op,
4358         .timesync_enable      = bnxt_timesync_enable,
4359         .timesync_disable     = bnxt_timesync_disable,
4360         .timesync_read_time   = bnxt_timesync_read_time,
4361         .timesync_write_time   = bnxt_timesync_write_time,
4362         .timesync_adjust_time = bnxt_timesync_adjust_time,
4363         .timesync_read_rx_timestamp = bnxt_timesync_read_rx_timestamp,
4364         .timesync_read_tx_timestamp = bnxt_timesync_read_tx_timestamp,
4365 };
4366
4367 static uint32_t bnxt_map_reset_regs(struct bnxt *bp, uint32_t reg)
4368 {
4369         uint32_t offset;
4370
4371         /* Only pre-map the reset GRC registers using window 3 */
4372         rte_write32(reg & 0xfffff000, (uint8_t *)bp->bar0 +
4373                     BNXT_GRCPF_REG_WINDOW_BASE_OUT + 8);
4374
4375         offset = BNXT_GRCP_WINDOW_3_BASE + (reg & 0xffc);
4376
4377         return offset;
4378 }
4379
4380 int bnxt_map_fw_health_status_regs(struct bnxt *bp)
4381 {
4382         struct bnxt_error_recovery_info *info = bp->recovery_info;
4383         uint32_t reg_base = 0xffffffff;
4384         int i;
4385
4386         /* Only pre-map the monitoring GRC registers using window 2 */
4387         for (i = 0; i < BNXT_FW_STATUS_REG_CNT; i++) {
4388                 uint32_t reg = info->status_regs[i];
4389
4390                 if (BNXT_FW_STATUS_REG_TYPE(reg) != BNXT_FW_STATUS_REG_TYPE_GRC)
4391                         continue;
4392
4393                 if (reg_base == 0xffffffff)
4394                         reg_base = reg & 0xfffff000;
4395                 if ((reg & 0xfffff000) != reg_base)
4396                         return -ERANGE;
4397
4398                 /* Use mask 0xffc as the Lower 2 bits indicates
4399                  * address space location
4400                  */
4401                 info->mapped_status_regs[i] = BNXT_GRCP_WINDOW_2_BASE +
4402                                                 (reg & 0xffc);
4403         }
4404
4405         if (reg_base == 0xffffffff)
4406                 return 0;
4407
4408         rte_write32(reg_base, (uint8_t *)bp->bar0 +
4409                     BNXT_GRCPF_REG_WINDOW_BASE_OUT + 4);
4410
4411         return 0;
4412 }
4413
4414 static void bnxt_write_fw_reset_reg(struct bnxt *bp, uint32_t index)
4415 {
4416         struct bnxt_error_recovery_info *info = bp->recovery_info;
4417         uint32_t delay = info->delay_after_reset[index];
4418         uint32_t val = info->reset_reg_val[index];
4419         uint32_t reg = info->reset_reg[index];
4420         uint32_t type, offset;
4421
4422         type = BNXT_FW_STATUS_REG_TYPE(reg);
4423         offset = BNXT_FW_STATUS_REG_OFF(reg);
4424
4425         switch (type) {
4426         case BNXT_FW_STATUS_REG_TYPE_CFG:
4427                 rte_pci_write_config(bp->pdev, &val, sizeof(val), offset);
4428                 break;
4429         case BNXT_FW_STATUS_REG_TYPE_GRC:
4430                 offset = bnxt_map_reset_regs(bp, offset);
4431                 rte_write32(val, (uint8_t *)bp->bar0 + offset);
4432                 break;
4433         case BNXT_FW_STATUS_REG_TYPE_BAR0:
4434                 rte_write32(val, (uint8_t *)bp->bar0 + offset);
4435                 break;
4436         }
4437         /* wait on a specific interval of time until core reset is complete */
4438         if (delay)
4439                 rte_delay_ms(delay);
4440 }
4441
4442 static void bnxt_dev_cleanup(struct bnxt *bp)
4443 {
4444         bp->eth_dev->data->dev_link.link_status = 0;
4445         bp->link_info->link_up = 0;
4446         if (bp->eth_dev->data->dev_started)
4447                 bnxt_dev_stop_op(bp->eth_dev);
4448
4449         bnxt_uninit_resources(bp, true);
4450 }
4451
4452 static int bnxt_restore_vlan_filters(struct bnxt *bp)
4453 {
4454         struct rte_eth_dev *dev = bp->eth_dev;
4455         struct rte_vlan_filter_conf *vfc;
4456         int vidx, vbit, rc;
4457         uint16_t vlan_id;
4458
4459         for (vlan_id = 1; vlan_id <= RTE_ETHER_MAX_VLAN_ID; vlan_id++) {
4460                 vfc = &dev->data->vlan_filter_conf;
4461                 vidx = vlan_id / 64;
4462                 vbit = vlan_id % 64;
4463
4464                 /* Each bit corresponds to a VLAN id */
4465                 if (vfc->ids[vidx] & (UINT64_C(1) << vbit)) {
4466                         rc = bnxt_add_vlan_filter(bp, vlan_id);
4467                         if (rc)
4468                                 return rc;
4469                 }
4470         }
4471
4472         return 0;
4473 }
4474
4475 static int bnxt_restore_mac_filters(struct bnxt *bp)
4476 {
4477         struct rte_eth_dev *dev = bp->eth_dev;
4478         struct rte_eth_dev_info dev_info;
4479         struct rte_ether_addr *addr;
4480         uint64_t pool_mask;
4481         uint32_t pool = 0;
4482         uint16_t i;
4483         int rc;
4484
4485         if (BNXT_VF(bp) && !BNXT_VF_IS_TRUSTED(bp))
4486                 return 0;
4487
4488         rc = bnxt_dev_info_get_op(dev, &dev_info);
4489         if (rc)
4490                 return rc;
4491
4492         /* replay MAC address configuration */
4493         for (i = 1; i < dev_info.max_mac_addrs; i++) {
4494                 addr = &dev->data->mac_addrs[i];
4495
4496                 /* skip zero address */
4497                 if (rte_is_zero_ether_addr(addr))
4498                         continue;
4499
4500                 pool = 0;
4501                 pool_mask = dev->data->mac_pool_sel[i];
4502
4503                 do {
4504                         if (pool_mask & 1ULL) {
4505                                 rc = bnxt_mac_addr_add_op(dev, addr, i, pool);
4506                                 if (rc)
4507                                         return rc;
4508                         }
4509                         pool_mask >>= 1;
4510                         pool++;
4511                 } while (pool_mask);
4512         }
4513
4514         return 0;
4515 }
4516
4517 static int bnxt_restore_filters(struct bnxt *bp)
4518 {
4519         struct rte_eth_dev *dev = bp->eth_dev;
4520         int ret = 0;
4521
4522         if (dev->data->all_multicast) {
4523                 ret = bnxt_allmulticast_enable_op(dev);
4524                 if (ret)
4525                         return ret;
4526         }
4527         if (dev->data->promiscuous) {
4528                 ret = bnxt_promiscuous_enable_op(dev);
4529                 if (ret)
4530                         return ret;
4531         }
4532
4533         ret = bnxt_restore_mac_filters(bp);
4534         if (ret)
4535                 return ret;
4536
4537         ret = bnxt_restore_vlan_filters(bp);
4538         /* TODO restore other filters as well */
4539         return ret;
4540 }
4541
4542 static void bnxt_dev_recover(void *arg)
4543 {
4544         struct bnxt *bp = arg;
4545         int timeout = bp->fw_reset_max_msecs;
4546         int rc = 0;
4547
4548         /* Clear Error flag so that device re-init should happen */
4549         bp->flags &= ~BNXT_FLAG_FATAL_ERROR;
4550
4551         do {
4552                 rc = bnxt_hwrm_ver_get(bp, SHORT_HWRM_CMD_TIMEOUT);
4553                 if (rc == 0)
4554                         break;
4555                 rte_delay_ms(BNXT_FW_READY_WAIT_INTERVAL);
4556                 timeout -= BNXT_FW_READY_WAIT_INTERVAL;
4557         } while (rc && timeout);
4558
4559         if (rc) {
4560                 PMD_DRV_LOG(ERR, "FW is not Ready after reset\n");
4561                 goto err;
4562         }
4563
4564         rc = bnxt_init_resources(bp, true);
4565         if (rc) {
4566                 PMD_DRV_LOG(ERR,
4567                             "Failed to initialize resources after reset\n");
4568                 goto err;
4569         }
4570         /* clear reset flag as the device is initialized now */
4571         bp->flags &= ~BNXT_FLAG_FW_RESET;
4572
4573         rc = bnxt_dev_start_op(bp->eth_dev);
4574         if (rc) {
4575                 PMD_DRV_LOG(ERR, "Failed to start port after reset\n");
4576                 goto err_start;
4577         }
4578
4579         rc = bnxt_restore_filters(bp);
4580         if (rc)
4581                 goto err_start;
4582
4583         PMD_DRV_LOG(INFO, "Recovered from FW reset\n");
4584         return;
4585 err_start:
4586         bnxt_dev_stop_op(bp->eth_dev);
4587 err:
4588         bp->flags |= BNXT_FLAG_FATAL_ERROR;
4589         bnxt_uninit_resources(bp, false);
4590         PMD_DRV_LOG(ERR, "Failed to recover from FW reset\n");
4591 }
4592
4593 void bnxt_dev_reset_and_resume(void *arg)
4594 {
4595         struct bnxt *bp = arg;
4596         int rc;
4597
4598         bnxt_dev_cleanup(bp);
4599
4600         bnxt_wait_for_device_shutdown(bp);
4601
4602         rc = rte_eal_alarm_set(US_PER_MS * bp->fw_reset_min_msecs,
4603                                bnxt_dev_recover, (void *)bp);
4604         if (rc)
4605                 PMD_DRV_LOG(ERR, "Error setting recovery alarm");
4606 }
4607
4608 uint32_t bnxt_read_fw_status_reg(struct bnxt *bp, uint32_t index)
4609 {
4610         struct bnxt_error_recovery_info *info = bp->recovery_info;
4611         uint32_t reg = info->status_regs[index];
4612         uint32_t type, offset, val = 0;
4613
4614         type = BNXT_FW_STATUS_REG_TYPE(reg);
4615         offset = BNXT_FW_STATUS_REG_OFF(reg);
4616
4617         switch (type) {
4618         case BNXT_FW_STATUS_REG_TYPE_CFG:
4619                 rte_pci_read_config(bp->pdev, &val, sizeof(val), offset);
4620                 break;
4621         case BNXT_FW_STATUS_REG_TYPE_GRC:
4622                 offset = info->mapped_status_regs[index];
4623                 /* FALLTHROUGH */
4624         case BNXT_FW_STATUS_REG_TYPE_BAR0:
4625                 val = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
4626                                        offset));
4627                 break;
4628         }
4629
4630         return val;
4631 }
4632
4633 static int bnxt_fw_reset_all(struct bnxt *bp)
4634 {
4635         struct bnxt_error_recovery_info *info = bp->recovery_info;
4636         uint32_t i;
4637         int rc = 0;
4638
4639         if (info->flags & BNXT_FLAG_ERROR_RECOVERY_HOST) {
4640                 /* Reset through master function driver */
4641                 for (i = 0; i < info->reg_array_cnt; i++)
4642                         bnxt_write_fw_reset_reg(bp, i);
4643                 /* Wait for time specified by FW after triggering reset */
4644                 rte_delay_ms(info->master_func_wait_period_after_reset);
4645         } else if (info->flags & BNXT_FLAG_ERROR_RECOVERY_CO_CPU) {
4646                 /* Reset with the help of Kong processor */
4647                 rc = bnxt_hwrm_fw_reset(bp);
4648                 if (rc)
4649                         PMD_DRV_LOG(ERR, "Failed to reset FW\n");
4650         }
4651
4652         return rc;
4653 }
4654
4655 static void bnxt_fw_reset_cb(void *arg)
4656 {
4657         struct bnxt *bp = arg;
4658         struct bnxt_error_recovery_info *info = bp->recovery_info;
4659         int rc = 0;
4660
4661         /* Only Master function can do FW reset */
4662         if (bnxt_is_master_func(bp) &&
4663             bnxt_is_recovery_enabled(bp)) {
4664                 rc = bnxt_fw_reset_all(bp);
4665                 if (rc) {
4666                         PMD_DRV_LOG(ERR, "Adapter recovery failed\n");
4667                         return;
4668                 }
4669         }
4670
4671         /* if recovery method is ERROR_RECOVERY_CO_CPU, KONG will send
4672          * EXCEPTION_FATAL_ASYNC event to all the functions
4673          * (including MASTER FUNC). After receiving this Async, all the active
4674          * drivers should treat this case as FW initiated recovery
4675          */
4676         if (info->flags & BNXT_FLAG_ERROR_RECOVERY_HOST) {
4677                 bp->fw_reset_min_msecs = BNXT_MIN_FW_READY_TIMEOUT;
4678                 bp->fw_reset_max_msecs = BNXT_MAX_FW_RESET_TIMEOUT;
4679
4680                 /* To recover from error */
4681                 rte_eal_alarm_set(US_PER_MS, bnxt_dev_reset_and_resume,
4682                                   (void *)bp);
4683         }
4684 }
4685
4686 /* Driver should poll FW heartbeat, reset_counter with the frequency
4687  * advertised by FW in HWRM_ERROR_RECOVERY_QCFG.
4688  * When the driver detects heartbeat stop or change in reset_counter,
4689  * it has to trigger a reset to recover from the error condition.
4690  * A “master PF” is the function who will have the privilege to
4691  * initiate the chimp reset. The master PF will be elected by the
4692  * firmware and will be notified through async message.
4693  */
4694 static void bnxt_check_fw_health(void *arg)
4695 {
4696         struct bnxt *bp = arg;
4697         struct bnxt_error_recovery_info *info = bp->recovery_info;
4698         uint32_t val = 0, wait_msec;
4699
4700         if (!info || !bnxt_is_recovery_enabled(bp) ||
4701             is_bnxt_in_error(bp))
4702                 return;
4703
4704         val = bnxt_read_fw_status_reg(bp, BNXT_FW_HEARTBEAT_CNT_REG);
4705         if (val == info->last_heart_beat)
4706                 goto reset;
4707
4708         info->last_heart_beat = val;
4709
4710         val = bnxt_read_fw_status_reg(bp, BNXT_FW_RECOVERY_CNT_REG);
4711         if (val != info->last_reset_counter)
4712                 goto reset;
4713
4714         info->last_reset_counter = val;
4715
4716         rte_eal_alarm_set(US_PER_MS * info->driver_polling_freq,
4717                           bnxt_check_fw_health, (void *)bp);
4718
4719         return;
4720 reset:
4721         /* Stop DMA to/from device */
4722         bp->flags |= BNXT_FLAG_FATAL_ERROR;
4723         bp->flags |= BNXT_FLAG_FW_RESET;
4724
4725         PMD_DRV_LOG(ERR, "Detected FW dead condition\n");
4726
4727         if (bnxt_is_master_func(bp))
4728                 wait_msec = info->master_func_wait_period;
4729         else
4730                 wait_msec = info->normal_func_wait_period;
4731
4732         rte_eal_alarm_set(US_PER_MS * wait_msec,
4733                           bnxt_fw_reset_cb, (void *)bp);
4734 }
4735
4736 void bnxt_schedule_fw_health_check(struct bnxt *bp)
4737 {
4738         uint32_t polling_freq;
4739
4740         pthread_mutex_lock(&bp->health_check_lock);
4741
4742         if (!bnxt_is_recovery_enabled(bp))
4743                 goto done;
4744
4745         if (bp->flags & BNXT_FLAG_FW_HEALTH_CHECK_SCHEDULED)
4746                 goto done;
4747
4748         polling_freq = bp->recovery_info->driver_polling_freq;
4749
4750         rte_eal_alarm_set(US_PER_MS * polling_freq,
4751                           bnxt_check_fw_health, (void *)bp);
4752         bp->flags |= BNXT_FLAG_FW_HEALTH_CHECK_SCHEDULED;
4753
4754 done:
4755         pthread_mutex_unlock(&bp->health_check_lock);
4756 }
4757
4758 static void bnxt_cancel_fw_health_check(struct bnxt *bp)
4759 {
4760         if (!bnxt_is_recovery_enabled(bp))
4761                 return;
4762
4763         rte_eal_alarm_cancel(bnxt_check_fw_health, (void *)bp);
4764         bp->flags &= ~BNXT_FLAG_FW_HEALTH_CHECK_SCHEDULED;
4765 }
4766
4767 static bool bnxt_vf_pciid(uint16_t device_id)
4768 {
4769         switch (device_id) {
4770         case BROADCOM_DEV_ID_57304_VF:
4771         case BROADCOM_DEV_ID_57406_VF:
4772         case BROADCOM_DEV_ID_5731X_VF:
4773         case BROADCOM_DEV_ID_5741X_VF:
4774         case BROADCOM_DEV_ID_57414_VF:
4775         case BROADCOM_DEV_ID_STRATUS_NIC_VF1:
4776         case BROADCOM_DEV_ID_STRATUS_NIC_VF2:
4777         case BROADCOM_DEV_ID_58802_VF:
4778         case BROADCOM_DEV_ID_57500_VF1:
4779         case BROADCOM_DEV_ID_57500_VF2:
4780                 /* FALLTHROUGH */
4781                 return true;
4782         default:
4783                 return false;
4784         }
4785 }
4786
4787 static bool bnxt_thor_device(uint16_t device_id)
4788 {
4789         switch (device_id) {
4790         case BROADCOM_DEV_ID_57508:
4791         case BROADCOM_DEV_ID_57504:
4792         case BROADCOM_DEV_ID_57502:
4793         case BROADCOM_DEV_ID_57508_MF1:
4794         case BROADCOM_DEV_ID_57504_MF1:
4795         case BROADCOM_DEV_ID_57502_MF1:
4796         case BROADCOM_DEV_ID_57508_MF2:
4797         case BROADCOM_DEV_ID_57504_MF2:
4798         case BROADCOM_DEV_ID_57502_MF2:
4799         case BROADCOM_DEV_ID_57500_VF1:
4800         case BROADCOM_DEV_ID_57500_VF2:
4801                 /* FALLTHROUGH */
4802                 return true;
4803         default:
4804                 return false;
4805         }
4806 }
4807
4808 bool bnxt_stratus_device(struct bnxt *bp)
4809 {
4810         uint16_t device_id = bp->pdev->id.device_id;
4811
4812         switch (device_id) {
4813         case BROADCOM_DEV_ID_STRATUS_NIC:
4814         case BROADCOM_DEV_ID_STRATUS_NIC_VF1:
4815         case BROADCOM_DEV_ID_STRATUS_NIC_VF2:
4816                 /* FALLTHROUGH */
4817                 return true;
4818         default:
4819                 return false;
4820         }
4821 }
4822
4823 static int bnxt_init_board(struct rte_eth_dev *eth_dev)
4824 {
4825         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
4826         struct bnxt *bp = eth_dev->data->dev_private;
4827
4828         /* enable device (incl. PCI PM wakeup), and bus-mastering */
4829         bp->bar0 = (void *)pci_dev->mem_resource[0].addr;
4830         bp->doorbell_base = (void *)pci_dev->mem_resource[2].addr;
4831         if (!bp->bar0 || !bp->doorbell_base) {
4832                 PMD_DRV_LOG(ERR, "Unable to access Hardware\n");
4833                 return -ENODEV;
4834         }
4835
4836         bp->eth_dev = eth_dev;
4837         bp->pdev = pci_dev;
4838
4839         return 0;
4840 }
4841
4842 static int bnxt_alloc_ctx_mem_blk(struct bnxt *bp,
4843                                   struct bnxt_ctx_pg_info *ctx_pg,
4844                                   uint32_t mem_size,
4845                                   const char *suffix,
4846                                   uint16_t idx)
4847 {
4848         struct bnxt_ring_mem_info *rmem = &ctx_pg->ring_mem;
4849         const struct rte_memzone *mz = NULL;
4850         char mz_name[RTE_MEMZONE_NAMESIZE];
4851         rte_iova_t mz_phys_addr;
4852         uint64_t valid_bits = 0;
4853         uint32_t sz;
4854         int i;
4855
4856         if (!mem_size)
4857                 return 0;
4858
4859         rmem->nr_pages = RTE_ALIGN_MUL_CEIL(mem_size, BNXT_PAGE_SIZE) /
4860                          BNXT_PAGE_SIZE;
4861         rmem->page_size = BNXT_PAGE_SIZE;
4862         rmem->pg_arr = ctx_pg->ctx_pg_arr;
4863         rmem->dma_arr = ctx_pg->ctx_dma_arr;
4864         rmem->flags = BNXT_RMEM_VALID_PTE_FLAG;
4865
4866         valid_bits = PTU_PTE_VALID;
4867
4868         if (rmem->nr_pages > 1) {
4869                 snprintf(mz_name, RTE_MEMZONE_NAMESIZE,
4870                          "bnxt_ctx_pg_tbl%s_%x_%d",
4871                          suffix, idx, bp->eth_dev->data->port_id);
4872                 mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0;
4873                 mz = rte_memzone_lookup(mz_name);
4874                 if (!mz) {
4875                         mz = rte_memzone_reserve_aligned(mz_name,
4876                                                 rmem->nr_pages * 8,
4877                                                 SOCKET_ID_ANY,
4878                                                 RTE_MEMZONE_2MB |
4879                                                 RTE_MEMZONE_SIZE_HINT_ONLY |
4880                                                 RTE_MEMZONE_IOVA_CONTIG,
4881                                                 BNXT_PAGE_SIZE);
4882                         if (mz == NULL)
4883                                 return -ENOMEM;
4884                 }
4885
4886                 memset(mz->addr, 0, mz->len);
4887                 mz_phys_addr = mz->iova;
4888
4889                 rmem->pg_tbl = mz->addr;
4890                 rmem->pg_tbl_map = mz_phys_addr;
4891                 rmem->pg_tbl_mz = mz;
4892         }
4893
4894         snprintf(mz_name, RTE_MEMZONE_NAMESIZE, "bnxt_ctx_%s_%x_%d",
4895                  suffix, idx, bp->eth_dev->data->port_id);
4896         mz = rte_memzone_lookup(mz_name);
4897         if (!mz) {
4898                 mz = rte_memzone_reserve_aligned(mz_name,
4899                                                  mem_size,
4900                                                  SOCKET_ID_ANY,
4901                                                  RTE_MEMZONE_1GB |
4902                                                  RTE_MEMZONE_SIZE_HINT_ONLY |
4903                                                  RTE_MEMZONE_IOVA_CONTIG,
4904                                                  BNXT_PAGE_SIZE);
4905                 if (mz == NULL)
4906                         return -ENOMEM;
4907         }
4908
4909         memset(mz->addr, 0, mz->len);
4910         mz_phys_addr = mz->iova;
4911
4912         for (sz = 0, i = 0; sz < mem_size; sz += BNXT_PAGE_SIZE, i++) {
4913                 rmem->pg_arr[i] = ((char *)mz->addr) + sz;
4914                 rmem->dma_arr[i] = mz_phys_addr + sz;
4915
4916                 if (rmem->nr_pages > 1) {
4917                         if (i == rmem->nr_pages - 2 &&
4918                             (rmem->flags & BNXT_RMEM_RING_PTE_FLAG))
4919                                 valid_bits |= PTU_PTE_NEXT_TO_LAST;
4920                         else if (i == rmem->nr_pages - 1 &&
4921                                  (rmem->flags & BNXT_RMEM_RING_PTE_FLAG))
4922                                 valid_bits |= PTU_PTE_LAST;
4923
4924                         rmem->pg_tbl[i] = rte_cpu_to_le_64(rmem->dma_arr[i] |
4925                                                            valid_bits);
4926                 }
4927         }
4928
4929         rmem->mz = mz;
4930         if (rmem->vmem_size)
4931                 rmem->vmem = (void **)mz->addr;
4932         rmem->dma_arr[0] = mz_phys_addr;
4933         return 0;
4934 }
4935
4936 static void bnxt_free_ctx_mem(struct bnxt *bp)
4937 {
4938         int i;
4939
4940         if (!bp->ctx || !(bp->ctx->flags & BNXT_CTX_FLAG_INITED))
4941                 return;
4942
4943         bp->ctx->flags &= ~BNXT_CTX_FLAG_INITED;
4944         rte_memzone_free(bp->ctx->qp_mem.ring_mem.mz);
4945         rte_memzone_free(bp->ctx->srq_mem.ring_mem.mz);
4946         rte_memzone_free(bp->ctx->cq_mem.ring_mem.mz);
4947         rte_memzone_free(bp->ctx->vnic_mem.ring_mem.mz);
4948         rte_memzone_free(bp->ctx->stat_mem.ring_mem.mz);
4949         rte_memzone_free(bp->ctx->qp_mem.ring_mem.pg_tbl_mz);
4950         rte_memzone_free(bp->ctx->srq_mem.ring_mem.pg_tbl_mz);
4951         rte_memzone_free(bp->ctx->cq_mem.ring_mem.pg_tbl_mz);
4952         rte_memzone_free(bp->ctx->vnic_mem.ring_mem.pg_tbl_mz);
4953         rte_memzone_free(bp->ctx->stat_mem.ring_mem.pg_tbl_mz);
4954
4955         for (i = 0; i < bp->ctx->tqm_fp_rings_count + 1; i++) {
4956                 if (bp->ctx->tqm_mem[i])
4957                         rte_memzone_free(bp->ctx->tqm_mem[i]->ring_mem.mz);
4958         }
4959
4960         rte_free(bp->ctx);
4961         bp->ctx = NULL;
4962 }
4963
4964 #define bnxt_roundup(x, y)   ((((x) + ((y) - 1)) / (y)) * (y))
4965
4966 #define min_t(type, x, y) ({                    \
4967         type __min1 = (x);                      \
4968         type __min2 = (y);                      \
4969         __min1 < __min2 ? __min1 : __min2; })
4970
4971 #define max_t(type, x, y) ({                    \
4972         type __max1 = (x);                      \
4973         type __max2 = (y);                      \
4974         __max1 > __max2 ? __max1 : __max2; })
4975
4976 #define clamp_t(type, _x, min, max)     min_t(type, max_t(type, _x, min), max)
4977
4978 int bnxt_alloc_ctx_mem(struct bnxt *bp)
4979 {
4980         struct bnxt_ctx_pg_info *ctx_pg;
4981         struct bnxt_ctx_mem_info *ctx;
4982         uint32_t mem_size, ena, entries;
4983         uint32_t entries_sp, min;
4984         int i, rc;
4985
4986         rc = bnxt_hwrm_func_backing_store_qcaps(bp);
4987         if (rc) {
4988                 PMD_DRV_LOG(ERR, "Query context mem capability failed\n");
4989                 return rc;
4990         }
4991         ctx = bp->ctx;
4992         if (!ctx || (ctx->flags & BNXT_CTX_FLAG_INITED))
4993                 return 0;
4994
4995         ctx_pg = &ctx->qp_mem;
4996         ctx_pg->entries = ctx->qp_min_qp1_entries + ctx->qp_max_l2_entries;
4997         mem_size = ctx->qp_entry_size * ctx_pg->entries;
4998         rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "qp_mem", 0);
4999         if (rc)
5000                 return rc;
5001
5002         ctx_pg = &ctx->srq_mem;
5003         ctx_pg->entries = ctx->srq_max_l2_entries;
5004         mem_size = ctx->srq_entry_size * ctx_pg->entries;
5005         rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "srq_mem", 0);
5006         if (rc)
5007                 return rc;
5008
5009         ctx_pg = &ctx->cq_mem;
5010         ctx_pg->entries = ctx->cq_max_l2_entries;
5011         mem_size = ctx->cq_entry_size * ctx_pg->entries;
5012         rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "cq_mem", 0);
5013         if (rc)
5014                 return rc;
5015
5016         ctx_pg = &ctx->vnic_mem;
5017         ctx_pg->entries = ctx->vnic_max_vnic_entries +
5018                 ctx->vnic_max_ring_table_entries;
5019         mem_size = ctx->vnic_entry_size * ctx_pg->entries;
5020         rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "vnic_mem", 0);
5021         if (rc)
5022                 return rc;
5023
5024         ctx_pg = &ctx->stat_mem;
5025         ctx_pg->entries = ctx->stat_max_entries;
5026         mem_size = ctx->stat_entry_size * ctx_pg->entries;
5027         rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "stat_mem", 0);
5028         if (rc)
5029                 return rc;
5030
5031         min = ctx->tqm_min_entries_per_ring;
5032
5033         entries_sp = ctx->qp_max_l2_entries +
5034                      ctx->vnic_max_vnic_entries +
5035                      2 * ctx->qp_min_qp1_entries + min;
5036         entries_sp = bnxt_roundup(entries_sp, ctx->tqm_entries_multiple);
5037
5038         entries = ctx->qp_max_l2_entries + ctx->qp_min_qp1_entries;
5039         entries = bnxt_roundup(entries, ctx->tqm_entries_multiple);
5040         entries = clamp_t(uint32_t, entries, min,
5041                           ctx->tqm_max_entries_per_ring);
5042         for (i = 0, ena = 0; i < ctx->tqm_fp_rings_count + 1; i++) {
5043                 ctx_pg = ctx->tqm_mem[i];
5044                 ctx_pg->entries = i ? entries : entries_sp;
5045                 mem_size = ctx->tqm_entry_size * ctx_pg->entries;
5046                 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "tqm_mem", i);
5047                 if (rc)
5048                         return rc;
5049                 ena |= HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_SP << i;
5050         }
5051
5052         ena |= FUNC_BACKING_STORE_CFG_INPUT_DFLT_ENABLES;
5053         rc = bnxt_hwrm_func_backing_store_cfg(bp, ena);
5054         if (rc)
5055                 PMD_DRV_LOG(ERR,
5056                             "Failed to configure context mem: rc = %d\n", rc);
5057         else
5058                 ctx->flags |= BNXT_CTX_FLAG_INITED;
5059
5060         return rc;
5061 }
5062
5063 static int bnxt_alloc_stats_mem(struct bnxt *bp)
5064 {
5065         struct rte_pci_device *pci_dev = bp->pdev;
5066         char mz_name[RTE_MEMZONE_NAMESIZE];
5067         const struct rte_memzone *mz = NULL;
5068         uint32_t total_alloc_len;
5069         rte_iova_t mz_phys_addr;
5070
5071         if (pci_dev->id.device_id == BROADCOM_DEV_ID_NS2)
5072                 return 0;
5073
5074         snprintf(mz_name, RTE_MEMZONE_NAMESIZE,
5075                  "bnxt_" PCI_PRI_FMT "-%s", pci_dev->addr.domain,
5076                  pci_dev->addr.bus, pci_dev->addr.devid,
5077                  pci_dev->addr.function, "rx_port_stats");
5078         mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0;
5079         mz = rte_memzone_lookup(mz_name);
5080         total_alloc_len =
5081                 RTE_CACHE_LINE_ROUNDUP(sizeof(struct rx_port_stats) +
5082                                        sizeof(struct rx_port_stats_ext) + 512);
5083         if (!mz) {
5084                 mz = rte_memzone_reserve(mz_name, total_alloc_len,
5085                                          SOCKET_ID_ANY,
5086                                          RTE_MEMZONE_2MB |
5087                                          RTE_MEMZONE_SIZE_HINT_ONLY |
5088                                          RTE_MEMZONE_IOVA_CONTIG);
5089                 if (mz == NULL)
5090                         return -ENOMEM;
5091         }
5092         memset(mz->addr, 0, mz->len);
5093         mz_phys_addr = mz->iova;
5094
5095         bp->rx_mem_zone = (const void *)mz;
5096         bp->hw_rx_port_stats = mz->addr;
5097         bp->hw_rx_port_stats_map = mz_phys_addr;
5098
5099         snprintf(mz_name, RTE_MEMZONE_NAMESIZE,
5100                  "bnxt_" PCI_PRI_FMT "-%s", pci_dev->addr.domain,
5101                  pci_dev->addr.bus, pci_dev->addr.devid,
5102                  pci_dev->addr.function, "tx_port_stats");
5103         mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0;
5104         mz = rte_memzone_lookup(mz_name);
5105         total_alloc_len =
5106                 RTE_CACHE_LINE_ROUNDUP(sizeof(struct tx_port_stats) +
5107                                        sizeof(struct tx_port_stats_ext) + 512);
5108         if (!mz) {
5109                 mz = rte_memzone_reserve(mz_name,
5110                                          total_alloc_len,
5111                                          SOCKET_ID_ANY,
5112                                          RTE_MEMZONE_2MB |
5113                                          RTE_MEMZONE_SIZE_HINT_ONLY |
5114                                          RTE_MEMZONE_IOVA_CONTIG);
5115                 if (mz == NULL)
5116                         return -ENOMEM;
5117         }
5118         memset(mz->addr, 0, mz->len);
5119         mz_phys_addr = mz->iova;
5120
5121         bp->tx_mem_zone = (const void *)mz;
5122         bp->hw_tx_port_stats = mz->addr;
5123         bp->hw_tx_port_stats_map = mz_phys_addr;
5124         bp->flags |= BNXT_FLAG_PORT_STATS;
5125
5126         /* Display extended statistics if FW supports it */
5127         if (bp->hwrm_spec_code < HWRM_SPEC_CODE_1_8_4 ||
5128             bp->hwrm_spec_code == HWRM_SPEC_CODE_1_9_0 ||
5129             !(bp->flags & BNXT_FLAG_EXT_STATS_SUPPORTED))
5130                 return 0;
5131
5132         bp->hw_rx_port_stats_ext = (void *)
5133                 ((uint8_t *)bp->hw_rx_port_stats +
5134                  sizeof(struct rx_port_stats));
5135         bp->hw_rx_port_stats_ext_map = bp->hw_rx_port_stats_map +
5136                 sizeof(struct rx_port_stats);
5137         bp->flags |= BNXT_FLAG_EXT_RX_PORT_STATS;
5138
5139         if (bp->hwrm_spec_code < HWRM_SPEC_CODE_1_9_2 ||
5140             bp->flags & BNXT_FLAG_EXT_STATS_SUPPORTED) {
5141                 bp->hw_tx_port_stats_ext = (void *)
5142                         ((uint8_t *)bp->hw_tx_port_stats +
5143                          sizeof(struct tx_port_stats));
5144                 bp->hw_tx_port_stats_ext_map =
5145                         bp->hw_tx_port_stats_map +
5146                         sizeof(struct tx_port_stats);
5147                 bp->flags |= BNXT_FLAG_EXT_TX_PORT_STATS;
5148         }
5149
5150         return 0;
5151 }
5152
5153 static int bnxt_setup_mac_addr(struct rte_eth_dev *eth_dev)
5154 {
5155         struct bnxt *bp = eth_dev->data->dev_private;
5156         int rc = 0;
5157
5158         eth_dev->data->mac_addrs = rte_zmalloc("bnxt_mac_addr_tbl",
5159                                                RTE_ETHER_ADDR_LEN *
5160                                                bp->max_l2_ctx,
5161                                                0);
5162         if (eth_dev->data->mac_addrs == NULL) {
5163                 PMD_DRV_LOG(ERR, "Failed to alloc MAC addr tbl\n");
5164                 return -ENOMEM;
5165         }
5166
5167         if (!BNXT_HAS_DFLT_MAC_SET(bp)) {
5168                 if (BNXT_PF(bp))
5169                         return -EINVAL;
5170
5171                 /* Generate a random MAC address, if none was assigned by PF */
5172                 PMD_DRV_LOG(INFO, "VF MAC address not assigned by Host PF\n");
5173                 bnxt_eth_hw_addr_random(bp->mac_addr);
5174                 PMD_DRV_LOG(INFO,
5175                             "Assign random MAC:%02X:%02X:%02X:%02X:%02X:%02X\n",
5176                             bp->mac_addr[0], bp->mac_addr[1], bp->mac_addr[2],
5177                             bp->mac_addr[3], bp->mac_addr[4], bp->mac_addr[5]);
5178
5179                 rc = bnxt_hwrm_set_mac(bp);
5180                 if (rc)
5181                         return rc;
5182         }
5183
5184         /* Copy the permanent MAC from the FUNC_QCAPS response */
5185         memcpy(&eth_dev->data->mac_addrs[0], bp->mac_addr, RTE_ETHER_ADDR_LEN);
5186
5187         return rc;
5188 }
5189
5190 static int bnxt_restore_dflt_mac(struct bnxt *bp)
5191 {
5192         int rc = 0;
5193
5194         /* MAC is already configured in FW */
5195         if (BNXT_HAS_DFLT_MAC_SET(bp))
5196                 return 0;
5197
5198         /* Restore the old MAC configured */
5199         rc = bnxt_hwrm_set_mac(bp);
5200         if (rc)
5201                 PMD_DRV_LOG(ERR, "Failed to restore MAC address\n");
5202
5203         return rc;
5204 }
5205
5206 static void bnxt_config_vf_req_fwd(struct bnxt *bp)
5207 {
5208         if (!BNXT_PF(bp))
5209                 return;
5210
5211 #define ALLOW_FUNC(x)   \
5212         { \
5213                 uint32_t arg = (x); \
5214                 bp->pf->vf_req_fwd[((arg) >> 5)] &= \
5215                 ~rte_cpu_to_le_32(1 << ((arg) & 0x1f)); \
5216         }
5217
5218         /* Forward all requests if firmware is new enough */
5219         if (((bp->fw_ver >= ((20 << 24) | (6 << 16) | (100 << 8))) &&
5220              (bp->fw_ver < ((20 << 24) | (7 << 16)))) ||
5221             ((bp->fw_ver >= ((20 << 24) | (8 << 16))))) {
5222                 memset(bp->pf->vf_req_fwd, 0xff, sizeof(bp->pf->vf_req_fwd));
5223         } else {
5224                 PMD_DRV_LOG(WARNING,
5225                             "Firmware too old for VF mailbox functionality\n");
5226                 memset(bp->pf->vf_req_fwd, 0, sizeof(bp->pf->vf_req_fwd));
5227         }
5228
5229         /*
5230          * The following are used for driver cleanup. If we disallow these,
5231          * VF drivers can't clean up cleanly.
5232          */
5233         ALLOW_FUNC(HWRM_FUNC_DRV_UNRGTR);
5234         ALLOW_FUNC(HWRM_VNIC_FREE);
5235         ALLOW_FUNC(HWRM_RING_FREE);
5236         ALLOW_FUNC(HWRM_RING_GRP_FREE);
5237         ALLOW_FUNC(HWRM_VNIC_RSS_COS_LB_CTX_FREE);
5238         ALLOW_FUNC(HWRM_CFA_L2_FILTER_FREE);
5239         ALLOW_FUNC(HWRM_STAT_CTX_FREE);
5240         ALLOW_FUNC(HWRM_PORT_PHY_QCFG);
5241         ALLOW_FUNC(HWRM_VNIC_TPA_CFG);
5242 }
5243
5244 uint16_t
5245 bnxt_get_svif(uint16_t port_id, bool func_svif,
5246               enum bnxt_ulp_intf_type type)
5247 {
5248         struct rte_eth_dev *eth_dev;
5249         struct bnxt *bp;
5250
5251         eth_dev = &rte_eth_devices[port_id];
5252         if (BNXT_ETH_DEV_IS_REPRESENTOR(eth_dev)) {
5253                 struct bnxt_representor *vfr = eth_dev->data->dev_private;
5254                 if (!vfr)
5255                         return 0;
5256
5257                 if (type == BNXT_ULP_INTF_TYPE_VF_REP)
5258                         return vfr->svif;
5259
5260                 eth_dev = vfr->parent_dev;
5261         }
5262
5263         bp = eth_dev->data->dev_private;
5264
5265         return func_svif ? bp->func_svif : bp->port_svif;
5266 }
5267
5268 uint16_t
5269 bnxt_get_vnic_id(uint16_t port, enum bnxt_ulp_intf_type type)
5270 {
5271         struct rte_eth_dev *eth_dev;
5272         struct bnxt_vnic_info *vnic;
5273         struct bnxt *bp;
5274
5275         eth_dev = &rte_eth_devices[port];
5276         if (BNXT_ETH_DEV_IS_REPRESENTOR(eth_dev)) {
5277                 struct bnxt_representor *vfr = eth_dev->data->dev_private;
5278                 if (!vfr)
5279                         return 0;
5280
5281                 if (type == BNXT_ULP_INTF_TYPE_VF_REP)
5282                         return vfr->dflt_vnic_id;
5283
5284                 eth_dev = vfr->parent_dev;
5285         }
5286
5287         bp = eth_dev->data->dev_private;
5288
5289         vnic = BNXT_GET_DEFAULT_VNIC(bp);
5290
5291         return vnic->fw_vnic_id;
5292 }
5293
5294 uint16_t
5295 bnxt_get_fw_func_id(uint16_t port, enum bnxt_ulp_intf_type type)
5296 {
5297         struct rte_eth_dev *eth_dev;
5298         struct bnxt *bp;
5299
5300         eth_dev = &rte_eth_devices[port];
5301         if (BNXT_ETH_DEV_IS_REPRESENTOR(eth_dev)) {
5302                 struct bnxt_representor *vfr = eth_dev->data->dev_private;
5303                 if (!vfr)
5304                         return 0;
5305
5306                 if (type == BNXT_ULP_INTF_TYPE_VF_REP)
5307                         return vfr->fw_fid;
5308
5309                 eth_dev = vfr->parent_dev;
5310         }
5311
5312         bp = eth_dev->data->dev_private;
5313
5314         return bp->fw_fid;
5315 }
5316
5317 enum bnxt_ulp_intf_type
5318 bnxt_get_interface_type(uint16_t port)
5319 {
5320         struct rte_eth_dev *eth_dev;
5321         struct bnxt *bp;
5322
5323         eth_dev = &rte_eth_devices[port];
5324         if (BNXT_ETH_DEV_IS_REPRESENTOR(eth_dev))
5325                 return BNXT_ULP_INTF_TYPE_VF_REP;
5326
5327         bp = eth_dev->data->dev_private;
5328         if (BNXT_PF(bp))
5329                 return BNXT_ULP_INTF_TYPE_PF;
5330         else if (BNXT_VF_IS_TRUSTED(bp))
5331                 return BNXT_ULP_INTF_TYPE_TRUSTED_VF;
5332         else if (BNXT_VF(bp))
5333                 return BNXT_ULP_INTF_TYPE_VF;
5334
5335         return BNXT_ULP_INTF_TYPE_INVALID;
5336 }
5337
5338 uint16_t
5339 bnxt_get_phy_port_id(uint16_t port_id)
5340 {
5341         struct bnxt_representor *vfr;
5342         struct rte_eth_dev *eth_dev;
5343         struct bnxt *bp;
5344
5345         eth_dev = &rte_eth_devices[port_id];
5346         if (BNXT_ETH_DEV_IS_REPRESENTOR(eth_dev)) {
5347                 vfr = eth_dev->data->dev_private;
5348                 if (!vfr)
5349                         return 0;
5350
5351                 eth_dev = vfr->parent_dev;
5352         }
5353
5354         bp = eth_dev->data->dev_private;
5355
5356         return BNXT_PF(bp) ? bp->pf->port_id : bp->parent->port_id;
5357 }
5358
5359 uint16_t
5360 bnxt_get_parif(uint16_t port_id, enum bnxt_ulp_intf_type type)
5361 {
5362         struct rte_eth_dev *eth_dev;
5363         struct bnxt *bp;
5364
5365         eth_dev = &rte_eth_devices[port_id];
5366         if (BNXT_ETH_DEV_IS_REPRESENTOR(eth_dev)) {
5367                 struct bnxt_representor *vfr = eth_dev->data->dev_private;
5368                 if (!vfr)
5369                         return 0;
5370
5371                 if (type == BNXT_ULP_INTF_TYPE_VF_REP)
5372                         return vfr->fw_fid - 1;
5373
5374                 eth_dev = vfr->parent_dev;
5375         }
5376
5377         bp = eth_dev->data->dev_private;
5378
5379         return BNXT_PF(bp) ? bp->fw_fid - 1 : bp->parent->fid - 1;
5380 }
5381
5382 uint16_t
5383 bnxt_get_vport(uint16_t port_id)
5384 {
5385         return (1 << bnxt_get_phy_port_id(port_id));
5386 }
5387
5388 static void bnxt_alloc_error_recovery_info(struct bnxt *bp)
5389 {
5390         struct bnxt_error_recovery_info *info = bp->recovery_info;
5391
5392         if (info) {
5393                 if (!(bp->fw_cap & BNXT_FW_CAP_HCOMM_FW_STATUS))
5394                         memset(info, 0, sizeof(*info));
5395                 return;
5396         }
5397
5398         if (!(bp->fw_cap & BNXT_FW_CAP_ERROR_RECOVERY))
5399                 return;
5400
5401         info = rte_zmalloc("bnxt_hwrm_error_recovery_qcfg",
5402                            sizeof(*info), 0);
5403         if (!info)
5404                 bp->fw_cap &= ~BNXT_FW_CAP_ERROR_RECOVERY;
5405
5406         bp->recovery_info = info;
5407 }
5408
5409 static void bnxt_check_fw_status(struct bnxt *bp)
5410 {
5411         uint32_t fw_status;
5412
5413         if (!(bp->recovery_info &&
5414               (bp->fw_cap & BNXT_FW_CAP_HCOMM_FW_STATUS)))
5415                 return;
5416
5417         fw_status = bnxt_read_fw_status_reg(bp, BNXT_FW_STATUS_REG);
5418         if (fw_status != BNXT_FW_STATUS_HEALTHY)
5419                 PMD_DRV_LOG(ERR, "Firmware not responding, status: %#x\n",
5420                             fw_status);
5421 }
5422
5423 static int bnxt_map_hcomm_fw_status_reg(struct bnxt *bp)
5424 {
5425         struct bnxt_error_recovery_info *info = bp->recovery_info;
5426         uint32_t status_loc;
5427         uint32_t sig_ver;
5428
5429         rte_write32(HCOMM_STATUS_STRUCT_LOC, (uint8_t *)bp->bar0 +
5430                     BNXT_GRCPF_REG_WINDOW_BASE_OUT + 4);
5431         sig_ver = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
5432                                    BNXT_GRCP_WINDOW_2_BASE +
5433                                    offsetof(struct hcomm_status,
5434                                             sig_ver)));
5435         /* If the signature is absent, then FW does not support this feature */
5436         if ((sig_ver & HCOMM_STATUS_SIGNATURE_MASK) !=
5437             HCOMM_STATUS_SIGNATURE_VAL)
5438                 return 0;
5439
5440         if (!info) {
5441                 info = rte_zmalloc("bnxt_hwrm_error_recovery_qcfg",
5442                                    sizeof(*info), 0);
5443                 if (!info)
5444                         return -ENOMEM;
5445                 bp->recovery_info = info;
5446         } else {
5447                 memset(info, 0, sizeof(*info));
5448         }
5449
5450         status_loc = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
5451                                       BNXT_GRCP_WINDOW_2_BASE +
5452                                       offsetof(struct hcomm_status,
5453                                                fw_status_loc)));
5454
5455         /* Only pre-map the FW health status GRC register */
5456         if (BNXT_FW_STATUS_REG_TYPE(status_loc) != BNXT_FW_STATUS_REG_TYPE_GRC)
5457                 return 0;
5458
5459         info->status_regs[BNXT_FW_STATUS_REG] = status_loc;
5460         info->mapped_status_regs[BNXT_FW_STATUS_REG] =
5461                 BNXT_GRCP_WINDOW_2_BASE + (status_loc & BNXT_GRCP_OFFSET_MASK);
5462
5463         rte_write32((status_loc & BNXT_GRCP_BASE_MASK), (uint8_t *)bp->bar0 +
5464                     BNXT_GRCPF_REG_WINDOW_BASE_OUT + 4);
5465
5466         bp->fw_cap |= BNXT_FW_CAP_HCOMM_FW_STATUS;
5467
5468         return 0;
5469 }
5470
5471 static int bnxt_init_fw(struct bnxt *bp)
5472 {
5473         uint16_t mtu;
5474         int rc = 0;
5475
5476         bp->fw_cap = 0;
5477
5478         rc = bnxt_map_hcomm_fw_status_reg(bp);
5479         if (rc)
5480                 return rc;
5481
5482         rc = bnxt_hwrm_ver_get(bp, DFLT_HWRM_CMD_TIMEOUT);
5483         if (rc) {
5484                 bnxt_check_fw_status(bp);
5485                 return rc;
5486         }
5487
5488         rc = bnxt_hwrm_func_reset(bp);
5489         if (rc)
5490                 return -EIO;
5491
5492         rc = bnxt_hwrm_vnic_qcaps(bp);
5493         if (rc)
5494                 return rc;
5495
5496         rc = bnxt_hwrm_queue_qportcfg(bp);
5497         if (rc)
5498                 return rc;
5499
5500         /* Get the MAX capabilities for this function.
5501          * This function also allocates context memory for TQM rings and
5502          * informs the firmware about this allocated backing store memory.
5503          */
5504         rc = bnxt_hwrm_func_qcaps(bp);
5505         if (rc)
5506                 return rc;
5507
5508         rc = bnxt_hwrm_func_qcfg(bp, &mtu);
5509         if (rc)
5510                 return rc;
5511
5512         bnxt_hwrm_port_mac_qcfg(bp);
5513
5514         bnxt_hwrm_parent_pf_qcfg(bp);
5515
5516         bnxt_hwrm_port_phy_qcaps(bp);
5517
5518         bnxt_alloc_error_recovery_info(bp);
5519         /* Get the adapter error recovery support info */
5520         rc = bnxt_hwrm_error_recovery_qcfg(bp);
5521         if (rc)
5522                 bp->fw_cap &= ~BNXT_FW_CAP_ERROR_RECOVERY;
5523
5524         bnxt_hwrm_port_led_qcaps(bp);
5525
5526         return 0;
5527 }
5528
5529 static int
5530 bnxt_init_locks(struct bnxt *bp)
5531 {
5532         int err;
5533
5534         err = pthread_mutex_init(&bp->flow_lock, NULL);
5535         if (err) {
5536                 PMD_DRV_LOG(ERR, "Unable to initialize flow_lock\n");
5537                 return err;
5538         }
5539
5540         err = pthread_mutex_init(&bp->def_cp_lock, NULL);
5541         if (err)
5542                 PMD_DRV_LOG(ERR, "Unable to initialize def_cp_lock\n");
5543
5544         err = pthread_mutex_init(&bp->health_check_lock, NULL);
5545         if (err)
5546                 PMD_DRV_LOG(ERR, "Unable to initialize health_check_lock\n");
5547         return err;
5548 }
5549
5550 static int bnxt_init_resources(struct bnxt *bp, bool reconfig_dev)
5551 {
5552         int rc = 0;
5553
5554         rc = bnxt_init_fw(bp);
5555         if (rc)
5556                 return rc;
5557
5558         if (!reconfig_dev) {
5559                 rc = bnxt_setup_mac_addr(bp->eth_dev);
5560                 if (rc)
5561                         return rc;
5562         } else {
5563                 rc = bnxt_restore_dflt_mac(bp);
5564                 if (rc)
5565                         return rc;
5566         }
5567
5568         bnxt_config_vf_req_fwd(bp);
5569
5570         rc = bnxt_hwrm_func_driver_register(bp);
5571         if (rc) {
5572                 PMD_DRV_LOG(ERR, "Failed to register driver");
5573                 return -EBUSY;
5574         }
5575
5576         if (BNXT_PF(bp)) {
5577                 if (bp->pdev->max_vfs) {
5578                         rc = bnxt_hwrm_allocate_vfs(bp, bp->pdev->max_vfs);
5579                         if (rc) {
5580                                 PMD_DRV_LOG(ERR, "Failed to allocate VFs\n");
5581                                 return rc;
5582                         }
5583                 } else {
5584                         rc = bnxt_hwrm_allocate_pf_only(bp);
5585                         if (rc) {
5586                                 PMD_DRV_LOG(ERR,
5587                                             "Failed to allocate PF resources");
5588                                 return rc;
5589                         }
5590                 }
5591         }
5592
5593         rc = bnxt_alloc_mem(bp, reconfig_dev);
5594         if (rc)
5595                 return rc;
5596
5597         rc = bnxt_setup_int(bp);
5598         if (rc)
5599                 return rc;
5600
5601         rc = bnxt_request_int(bp);
5602         if (rc)
5603                 return rc;
5604
5605         rc = bnxt_init_ctx_mem(bp);
5606         if (rc) {
5607                 PMD_DRV_LOG(ERR, "Failed to init adv_flow_counters\n");
5608                 return rc;
5609         }
5610
5611         rc = bnxt_init_locks(bp);
5612         if (rc)
5613                 return rc;
5614
5615         return 0;
5616 }
5617
5618 static int
5619 bnxt_parse_devarg_truflow(__rte_unused const char *key,
5620                           const char *value, void *opaque_arg)
5621 {
5622         struct bnxt *bp = opaque_arg;
5623         unsigned long truflow;
5624         char *end = NULL;
5625
5626         if (!value || !opaque_arg) {
5627                 PMD_DRV_LOG(ERR,
5628                             "Invalid parameter passed to truflow devargs.\n");
5629                 return -EINVAL;
5630         }
5631
5632         truflow = strtoul(value, &end, 10);
5633         if (end == NULL || *end != '\0' ||
5634             (truflow == ULONG_MAX && errno == ERANGE)) {
5635                 PMD_DRV_LOG(ERR,
5636                             "Invalid parameter passed to truflow devargs.\n");
5637                 return -EINVAL;
5638         }
5639
5640         if (BNXT_DEVARG_TRUFLOW_INVALID(truflow)) {
5641                 PMD_DRV_LOG(ERR,
5642                             "Invalid value passed to truflow devargs.\n");
5643                 return -EINVAL;
5644         }
5645
5646         if (truflow) {
5647                 bp->flags |= BNXT_FLAG_TRUFLOW_EN;
5648                 PMD_DRV_LOG(INFO, "Host-based truflow feature enabled.\n");
5649         } else {
5650                 bp->flags &= ~BNXT_FLAG_TRUFLOW_EN;
5651                 PMD_DRV_LOG(INFO, "Host-based truflow feature disabled.\n");
5652         }
5653
5654         return 0;
5655 }
5656
5657 static int
5658 bnxt_parse_devarg_flow_xstat(__rte_unused const char *key,
5659                              const char *value, void *opaque_arg)
5660 {
5661         struct bnxt *bp = opaque_arg;
5662         unsigned long flow_xstat;
5663         char *end = NULL;
5664
5665         if (!value || !opaque_arg) {
5666                 PMD_DRV_LOG(ERR,
5667                             "Invalid parameter passed to flow_xstat devarg.\n");
5668                 return -EINVAL;
5669         }
5670
5671         flow_xstat = strtoul(value, &end, 10);
5672         if (end == NULL || *end != '\0' ||
5673             (flow_xstat == ULONG_MAX && errno == ERANGE)) {
5674                 PMD_DRV_LOG(ERR,
5675                             "Invalid parameter passed to flow_xstat devarg.\n");
5676                 return -EINVAL;
5677         }
5678
5679         if (BNXT_DEVARG_FLOW_XSTAT_INVALID(flow_xstat)) {
5680                 PMD_DRV_LOG(ERR,
5681                             "Invalid value passed to flow_xstat devarg.\n");
5682                 return -EINVAL;
5683         }
5684
5685         bp->flags |= BNXT_FLAG_FLOW_XSTATS_EN;
5686         if (BNXT_FLOW_XSTATS_EN(bp))
5687                 PMD_DRV_LOG(INFO, "flow_xstat feature enabled.\n");
5688
5689         return 0;
5690 }
5691
5692 static int
5693 bnxt_parse_devarg_max_num_kflows(__rte_unused const char *key,
5694                                         const char *value, void *opaque_arg)
5695 {
5696         struct bnxt *bp = opaque_arg;
5697         unsigned long max_num_kflows;
5698         char *end = NULL;
5699
5700         if (!value || !opaque_arg) {
5701                 PMD_DRV_LOG(ERR,
5702                         "Invalid parameter passed to max_num_kflows devarg.\n");
5703                 return -EINVAL;
5704         }
5705
5706         max_num_kflows = strtoul(value, &end, 10);
5707         if (end == NULL || *end != '\0' ||
5708                 (max_num_kflows == ULONG_MAX && errno == ERANGE)) {
5709                 PMD_DRV_LOG(ERR,
5710                         "Invalid parameter passed to max_num_kflows devarg.\n");
5711                 return -EINVAL;
5712         }
5713
5714         if (bnxt_devarg_max_num_kflow_invalid(max_num_kflows)) {
5715                 PMD_DRV_LOG(ERR,
5716                         "Invalid value passed to max_num_kflows devarg.\n");
5717                 return -EINVAL;
5718         }
5719
5720         bp->max_num_kflows = max_num_kflows;
5721         if (bp->max_num_kflows)
5722                 PMD_DRV_LOG(INFO, "max_num_kflows set as %ldK.\n",
5723                                 max_num_kflows);
5724
5725         return 0;
5726 }
5727
5728 static int
5729 bnxt_parse_devarg_rep_is_pf(__rte_unused const char *key,
5730                             const char *value, void *opaque_arg)
5731 {
5732         struct bnxt_representor *vfr_bp = opaque_arg;
5733         unsigned long rep_is_pf;
5734         char *end = NULL;
5735
5736         if (!value || !opaque_arg) {
5737                 PMD_DRV_LOG(ERR,
5738                             "Invalid parameter passed to rep_is_pf devargs.\n");
5739                 return -EINVAL;
5740         }
5741
5742         rep_is_pf = strtoul(value, &end, 10);
5743         if (end == NULL || *end != '\0' ||
5744             (rep_is_pf == ULONG_MAX && errno == ERANGE)) {
5745                 PMD_DRV_LOG(ERR,
5746                             "Invalid parameter passed to rep_is_pf devargs.\n");
5747                 return -EINVAL;
5748         }
5749
5750         if (BNXT_DEVARG_REP_IS_PF_INVALID(rep_is_pf)) {
5751                 PMD_DRV_LOG(ERR,
5752                             "Invalid value passed to rep_is_pf devargs.\n");
5753                 return -EINVAL;
5754         }
5755
5756         vfr_bp->flags |= rep_is_pf;
5757         if (BNXT_REP_PF(vfr_bp))
5758                 PMD_DRV_LOG(INFO, "PF representor\n");
5759         else
5760                 PMD_DRV_LOG(INFO, "VF representor\n");
5761
5762         return 0;
5763 }
5764
5765 static int
5766 bnxt_parse_devarg_rep_based_pf(__rte_unused const char *key,
5767                                const char *value, void *opaque_arg)
5768 {
5769         struct bnxt_representor *vfr_bp = opaque_arg;
5770         unsigned long rep_based_pf;
5771         char *end = NULL;
5772
5773         if (!value || !opaque_arg) {
5774                 PMD_DRV_LOG(ERR,
5775                             "Invalid parameter passed to rep_based_pf "
5776                             "devargs.\n");
5777                 return -EINVAL;
5778         }
5779
5780         rep_based_pf = strtoul(value, &end, 10);
5781         if (end == NULL || *end != '\0' ||
5782             (rep_based_pf == ULONG_MAX && errno == ERANGE)) {
5783                 PMD_DRV_LOG(ERR,
5784                             "Invalid parameter passed to rep_based_pf "
5785                             "devargs.\n");
5786                 return -EINVAL;
5787         }
5788
5789         if (BNXT_DEVARG_REP_BASED_PF_INVALID(rep_based_pf)) {
5790                 PMD_DRV_LOG(ERR,
5791                             "Invalid value passed to rep_based_pf devargs.\n");
5792                 return -EINVAL;
5793         }
5794
5795         vfr_bp->rep_based_pf = rep_based_pf;
5796         PMD_DRV_LOG(INFO, "rep-based-pf = %d\n", vfr_bp->rep_based_pf);
5797
5798         return 0;
5799 }
5800
5801 static int
5802 bnxt_parse_devarg_rep_q_r2f(__rte_unused const char *key,
5803                             const char *value, void *opaque_arg)
5804 {
5805         struct bnxt_representor *vfr_bp = opaque_arg;
5806         unsigned long rep_q_r2f;
5807         char *end = NULL;
5808
5809         if (!value || !opaque_arg) {
5810                 PMD_DRV_LOG(ERR,
5811                             "Invalid parameter passed to rep_q_r2f "
5812                             "devargs.\n");
5813                 return -EINVAL;
5814         }
5815
5816         rep_q_r2f = strtoul(value, &end, 10);
5817         if (end == NULL || *end != '\0' ||
5818             (rep_q_r2f == ULONG_MAX && errno == ERANGE)) {
5819                 PMD_DRV_LOG(ERR,
5820                             "Invalid parameter passed to rep_q_r2f "
5821                             "devargs.\n");
5822                 return -EINVAL;
5823         }
5824
5825         if (BNXT_DEVARG_REP_Q_R2F_INVALID(rep_q_r2f)) {
5826                 PMD_DRV_LOG(ERR,
5827                             "Invalid value passed to rep_q_r2f devargs.\n");
5828                 return -EINVAL;
5829         }
5830
5831         vfr_bp->rep_q_r2f = rep_q_r2f;
5832         vfr_bp->flags |= BNXT_REP_Q_R2F_VALID;
5833         PMD_DRV_LOG(INFO, "rep-q-r2f = %d\n", vfr_bp->rep_q_r2f);
5834
5835         return 0;
5836 }
5837
5838 static int
5839 bnxt_parse_devarg_rep_q_f2r(__rte_unused const char *key,
5840                             const char *value, void *opaque_arg)
5841 {
5842         struct bnxt_representor *vfr_bp = opaque_arg;
5843         unsigned long rep_q_f2r;
5844         char *end = NULL;
5845
5846         if (!value || !opaque_arg) {
5847                 PMD_DRV_LOG(ERR,
5848                             "Invalid parameter passed to rep_q_f2r "
5849                             "devargs.\n");
5850                 return -EINVAL;
5851         }
5852
5853         rep_q_f2r = strtoul(value, &end, 10);
5854         if (end == NULL || *end != '\0' ||
5855             (rep_q_f2r == ULONG_MAX && errno == ERANGE)) {
5856                 PMD_DRV_LOG(ERR,
5857                             "Invalid parameter passed to rep_q_f2r "
5858                             "devargs.\n");
5859                 return -EINVAL;
5860         }
5861
5862         if (BNXT_DEVARG_REP_Q_F2R_INVALID(rep_q_f2r)) {
5863                 PMD_DRV_LOG(ERR,
5864                             "Invalid value passed to rep_q_f2r devargs.\n");
5865                 return -EINVAL;
5866         }
5867
5868         vfr_bp->rep_q_f2r = rep_q_f2r;
5869         vfr_bp->flags |= BNXT_REP_Q_F2R_VALID;
5870         PMD_DRV_LOG(INFO, "rep-q-f2r = %d\n", vfr_bp->rep_q_f2r);
5871
5872         return 0;
5873 }
5874
5875 static int
5876 bnxt_parse_devarg_rep_fc_r2f(__rte_unused const char *key,
5877                              const char *value, void *opaque_arg)
5878 {
5879         struct bnxt_representor *vfr_bp = opaque_arg;
5880         unsigned long rep_fc_r2f;
5881         char *end = NULL;
5882
5883         if (!value || !opaque_arg) {
5884                 PMD_DRV_LOG(ERR,
5885                             "Invalid parameter passed to rep_fc_r2f "
5886                             "devargs.\n");
5887                 return -EINVAL;
5888         }
5889
5890         rep_fc_r2f = strtoul(value, &end, 10);
5891         if (end == NULL || *end != '\0' ||
5892             (rep_fc_r2f == ULONG_MAX && errno == ERANGE)) {
5893                 PMD_DRV_LOG(ERR,
5894                             "Invalid parameter passed to rep_fc_r2f "
5895                             "devargs.\n");
5896                 return -EINVAL;
5897         }
5898
5899         if (BNXT_DEVARG_REP_FC_R2F_INVALID(rep_fc_r2f)) {
5900                 PMD_DRV_LOG(ERR,
5901                             "Invalid value passed to rep_fc_r2f devargs.\n");
5902                 return -EINVAL;
5903         }
5904
5905         vfr_bp->flags |= BNXT_REP_FC_R2F_VALID;
5906         vfr_bp->rep_fc_r2f = rep_fc_r2f;
5907         PMD_DRV_LOG(INFO, "rep-fc-r2f = %lu\n", rep_fc_r2f);
5908
5909         return 0;
5910 }
5911
5912 static int
5913 bnxt_parse_devarg_rep_fc_f2r(__rte_unused const char *key,
5914                              const char *value, void *opaque_arg)
5915 {
5916         struct bnxt_representor *vfr_bp = opaque_arg;
5917         unsigned long rep_fc_f2r;
5918         char *end = NULL;
5919
5920         if (!value || !opaque_arg) {
5921                 PMD_DRV_LOG(ERR,
5922                             "Invalid parameter passed to rep_fc_f2r "
5923                             "devargs.\n");
5924                 return -EINVAL;
5925         }
5926
5927         rep_fc_f2r = strtoul(value, &end, 10);
5928         if (end == NULL || *end != '\0' ||
5929             (rep_fc_f2r == ULONG_MAX && errno == ERANGE)) {
5930                 PMD_DRV_LOG(ERR,
5931                             "Invalid parameter passed to rep_fc_f2r "
5932                             "devargs.\n");
5933                 return -EINVAL;
5934         }
5935
5936         if (BNXT_DEVARG_REP_FC_F2R_INVALID(rep_fc_f2r)) {
5937                 PMD_DRV_LOG(ERR,
5938                             "Invalid value passed to rep_fc_f2r devargs.\n");
5939                 return -EINVAL;
5940         }
5941
5942         vfr_bp->flags |= BNXT_REP_FC_F2R_VALID;
5943         vfr_bp->rep_fc_f2r = rep_fc_f2r;
5944         PMD_DRV_LOG(INFO, "rep-fc-f2r = %lu\n", rep_fc_f2r);
5945
5946         return 0;
5947 }
5948
5949 static void
5950 bnxt_parse_dev_args(struct bnxt *bp, struct rte_devargs *devargs)
5951 {
5952         struct rte_kvargs *kvlist;
5953
5954         if (devargs == NULL)
5955                 return;
5956
5957         kvlist = rte_kvargs_parse(devargs->args, bnxt_dev_args);
5958         if (kvlist == NULL)
5959                 return;
5960
5961         /*
5962          * Handler for "truflow" devarg.
5963          * Invoked as for ex: "-w 0000:00:0d.0,host-based-truflow=1"
5964          */
5965         rte_kvargs_process(kvlist, BNXT_DEVARG_TRUFLOW,
5966                            bnxt_parse_devarg_truflow, bp);
5967
5968         /*
5969          * Handler for "flow_xstat" devarg.
5970          * Invoked as for ex: "-w 0000:00:0d.0,flow_xstat=1"
5971          */
5972         rte_kvargs_process(kvlist, BNXT_DEVARG_FLOW_XSTAT,
5973                            bnxt_parse_devarg_flow_xstat, bp);
5974
5975         /*
5976          * Handler for "max_num_kflows" devarg.
5977          * Invoked as for ex: "-w 000:00:0d.0,max_num_kflows=32"
5978          */
5979         rte_kvargs_process(kvlist, BNXT_DEVARG_MAX_NUM_KFLOWS,
5980                            bnxt_parse_devarg_max_num_kflows, bp);
5981
5982         rte_kvargs_free(kvlist);
5983 }
5984
5985 static int bnxt_alloc_switch_domain(struct bnxt *bp)
5986 {
5987         int rc = 0;
5988
5989         if (BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp)) {
5990                 rc = rte_eth_switch_domain_alloc(&bp->switch_domain_id);
5991                 if (rc)
5992                         PMD_DRV_LOG(ERR,
5993                                     "Failed to alloc switch domain: %d\n", rc);
5994                 else
5995                         PMD_DRV_LOG(INFO,
5996                                     "Switch domain allocated %d\n",
5997                                     bp->switch_domain_id);
5998         }
5999
6000         return rc;
6001 }
6002
6003 static int
6004 bnxt_dev_init(struct rte_eth_dev *eth_dev, void *params __rte_unused)
6005 {
6006         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
6007         static int version_printed;
6008         struct bnxt *bp;
6009         int rc;
6010
6011         if (version_printed++ == 0)
6012                 PMD_DRV_LOG(INFO, "%s\n", bnxt_version);
6013
6014         eth_dev->dev_ops = &bnxt_dev_ops;
6015         eth_dev->rx_queue_count = bnxt_rx_queue_count_op;
6016         eth_dev->rx_descriptor_status = bnxt_rx_descriptor_status_op;
6017         eth_dev->tx_descriptor_status = bnxt_tx_descriptor_status_op;
6018         eth_dev->rx_pkt_burst = &bnxt_recv_pkts;
6019         eth_dev->tx_pkt_burst = &bnxt_xmit_pkts;
6020
6021         /*
6022          * For secondary processes, we don't initialise any further
6023          * as primary has already done this work.
6024          */
6025         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
6026                 return 0;
6027
6028         rte_eth_copy_pci_info(eth_dev, pci_dev);
6029
6030         bp = eth_dev->data->dev_private;
6031
6032         /* Parse dev arguments passed on when starting the DPDK application. */
6033         bnxt_parse_dev_args(bp, pci_dev->device.devargs);
6034
6035         bp->flags &= ~BNXT_FLAG_RX_VECTOR_PKT_MODE;
6036
6037         if (bnxt_vf_pciid(pci_dev->id.device_id))
6038                 bp->flags |= BNXT_FLAG_VF;
6039
6040         if (bnxt_thor_device(pci_dev->id.device_id))
6041                 bp->flags |= BNXT_FLAG_THOR_CHIP;
6042
6043         if (pci_dev->id.device_id == BROADCOM_DEV_ID_58802 ||
6044             pci_dev->id.device_id == BROADCOM_DEV_ID_58804 ||
6045             pci_dev->id.device_id == BROADCOM_DEV_ID_58808 ||
6046             pci_dev->id.device_id == BROADCOM_DEV_ID_58802_VF)
6047                 bp->flags |= BNXT_FLAG_STINGRAY;
6048
6049         rc = bnxt_init_board(eth_dev);
6050         if (rc) {
6051                 PMD_DRV_LOG(ERR,
6052                             "Failed to initialize board rc: %x\n", rc);
6053                 return rc;
6054         }
6055
6056         rc = bnxt_alloc_pf_info(bp);
6057         if (rc)
6058                 goto error_free;
6059
6060         rc = bnxt_alloc_link_info(bp);
6061         if (rc)
6062                 goto error_free;
6063
6064         rc = bnxt_alloc_parent_info(bp);
6065         if (rc)
6066                 goto error_free;
6067
6068         rc = bnxt_alloc_hwrm_resources(bp);
6069         if (rc) {
6070                 PMD_DRV_LOG(ERR,
6071                             "Failed to allocate hwrm resource rc: %x\n", rc);
6072                 goto error_free;
6073         }
6074         rc = bnxt_alloc_leds_info(bp);
6075         if (rc)
6076                 goto error_free;
6077
6078         rc = bnxt_alloc_cos_queues(bp);
6079         if (rc)
6080                 goto error_free;
6081
6082         rc = bnxt_init_resources(bp, false);
6083         if (rc)
6084                 goto error_free;
6085
6086         rc = bnxt_alloc_stats_mem(bp);
6087         if (rc)
6088                 goto error_free;
6089
6090         bnxt_alloc_switch_domain(bp);
6091
6092         PMD_DRV_LOG(INFO,
6093                     DRV_MODULE_NAME "found at mem %" PRIX64 ", node addr %pM\n",
6094                     pci_dev->mem_resource[0].phys_addr,
6095                     pci_dev->mem_resource[0].addr);
6096
6097         return 0;
6098
6099 error_free:
6100         bnxt_dev_uninit(eth_dev);
6101         return rc;
6102 }
6103
6104
6105 static void bnxt_free_ctx_mem_buf(struct bnxt_ctx_mem_buf_info *ctx)
6106 {
6107         if (!ctx)
6108                 return;
6109
6110         if (ctx->va)
6111                 rte_free(ctx->va);
6112
6113         ctx->va = NULL;
6114         ctx->dma = RTE_BAD_IOVA;
6115         ctx->ctx_id = BNXT_CTX_VAL_INVAL;
6116 }
6117
6118 static void bnxt_unregister_fc_ctx_mem(struct bnxt *bp)
6119 {
6120         bnxt_hwrm_cfa_counter_cfg(bp, BNXT_DIR_RX,
6121                                   CFA_COUNTER_CFG_IN_COUNTER_TYPE_FC,
6122                                   bp->flow_stat->rx_fc_out_tbl.ctx_id,
6123                                   bp->flow_stat->max_fc,
6124                                   false);
6125
6126         bnxt_hwrm_cfa_counter_cfg(bp, BNXT_DIR_TX,
6127                                   CFA_COUNTER_CFG_IN_COUNTER_TYPE_FC,
6128                                   bp->flow_stat->tx_fc_out_tbl.ctx_id,
6129                                   bp->flow_stat->max_fc,
6130                                   false);
6131
6132         if (bp->flow_stat->rx_fc_in_tbl.ctx_id != BNXT_CTX_VAL_INVAL)
6133                 bnxt_hwrm_ctx_unrgtr(bp, bp->flow_stat->rx_fc_in_tbl.ctx_id);
6134         bp->flow_stat->rx_fc_in_tbl.ctx_id = BNXT_CTX_VAL_INVAL;
6135
6136         if (bp->flow_stat->rx_fc_out_tbl.ctx_id != BNXT_CTX_VAL_INVAL)
6137                 bnxt_hwrm_ctx_unrgtr(bp, bp->flow_stat->rx_fc_out_tbl.ctx_id);
6138         bp->flow_stat->rx_fc_out_tbl.ctx_id = BNXT_CTX_VAL_INVAL;
6139
6140         if (bp->flow_stat->tx_fc_in_tbl.ctx_id != BNXT_CTX_VAL_INVAL)
6141                 bnxt_hwrm_ctx_unrgtr(bp, bp->flow_stat->tx_fc_in_tbl.ctx_id);
6142         bp->flow_stat->tx_fc_in_tbl.ctx_id = BNXT_CTX_VAL_INVAL;
6143
6144         if (bp->flow_stat->tx_fc_out_tbl.ctx_id != BNXT_CTX_VAL_INVAL)
6145                 bnxt_hwrm_ctx_unrgtr(bp, bp->flow_stat->tx_fc_out_tbl.ctx_id);
6146         bp->flow_stat->tx_fc_out_tbl.ctx_id = BNXT_CTX_VAL_INVAL;
6147 }
6148
6149 static void bnxt_uninit_fc_ctx_mem(struct bnxt *bp)
6150 {
6151         bnxt_unregister_fc_ctx_mem(bp);
6152
6153         bnxt_free_ctx_mem_buf(&bp->flow_stat->rx_fc_in_tbl);
6154         bnxt_free_ctx_mem_buf(&bp->flow_stat->rx_fc_out_tbl);
6155         bnxt_free_ctx_mem_buf(&bp->flow_stat->tx_fc_in_tbl);
6156         bnxt_free_ctx_mem_buf(&bp->flow_stat->tx_fc_out_tbl);
6157 }
6158
6159 static void bnxt_uninit_ctx_mem(struct bnxt *bp)
6160 {
6161         if (BNXT_FLOW_XSTATS_EN(bp))
6162                 bnxt_uninit_fc_ctx_mem(bp);
6163 }
6164
6165 static void
6166 bnxt_free_error_recovery_info(struct bnxt *bp)
6167 {
6168         rte_free(bp->recovery_info);
6169         bp->recovery_info = NULL;
6170         bp->fw_cap &= ~BNXT_FW_CAP_ERROR_RECOVERY;
6171 }
6172
6173 static void
6174 bnxt_uninit_locks(struct bnxt *bp)
6175 {
6176         pthread_mutex_destroy(&bp->flow_lock);
6177         pthread_mutex_destroy(&bp->def_cp_lock);
6178         pthread_mutex_destroy(&bp->health_check_lock);
6179         if (bp->rep_info) {
6180                 pthread_mutex_destroy(&bp->rep_info->vfr_lock);
6181                 pthread_mutex_destroy(&bp->rep_info->vfr_start_lock);
6182         }
6183 }
6184
6185 static int
6186 bnxt_uninit_resources(struct bnxt *bp, bool reconfig_dev)
6187 {
6188         int rc;
6189
6190         bnxt_free_int(bp);
6191         bnxt_free_mem(bp, reconfig_dev);
6192         bnxt_hwrm_func_buf_unrgtr(bp);
6193         rc = bnxt_hwrm_func_driver_unregister(bp, 0);
6194         bp->flags &= ~BNXT_FLAG_REGISTERED;
6195         bnxt_free_ctx_mem(bp);
6196         if (!reconfig_dev) {
6197                 bnxt_free_hwrm_resources(bp);
6198                 bnxt_free_error_recovery_info(bp);
6199         }
6200
6201         bnxt_uninit_ctx_mem(bp);
6202
6203         bnxt_uninit_locks(bp);
6204         bnxt_free_flow_stats_info(bp);
6205         bnxt_free_rep_info(bp);
6206         rte_free(bp->ptp_cfg);
6207         bp->ptp_cfg = NULL;
6208         return rc;
6209 }
6210
6211 static int
6212 bnxt_dev_uninit(struct rte_eth_dev *eth_dev)
6213 {
6214         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
6215                 return -EPERM;
6216
6217         PMD_DRV_LOG(DEBUG, "Calling Device uninit\n");
6218
6219         if (eth_dev->state != RTE_ETH_DEV_UNUSED)
6220                 bnxt_dev_close_op(eth_dev);
6221
6222         return 0;
6223 }
6224
6225 static int bnxt_pci_remove_dev_with_reps(struct rte_eth_dev *eth_dev)
6226 {
6227         struct bnxt *bp = eth_dev->data->dev_private;
6228         struct rte_eth_dev *vf_rep_eth_dev;
6229         int ret = 0, i;
6230
6231         if (!bp)
6232                 return -EINVAL;
6233
6234         for (i = 0; i < bp->num_reps; i++) {
6235                 vf_rep_eth_dev = bp->rep_info[i].vfr_eth_dev;
6236                 if (!vf_rep_eth_dev)
6237                         continue;
6238                 PMD_DRV_LOG(DEBUG, "BNXT Port:%d VFR pci remove\n",
6239                             vf_rep_eth_dev->data->port_id);
6240                 rte_eth_dev_destroy(vf_rep_eth_dev, bnxt_representor_uninit);
6241         }
6242         PMD_DRV_LOG(DEBUG, "BNXT Port:%d pci remove\n",
6243                     eth_dev->data->port_id);
6244         ret = rte_eth_dev_destroy(eth_dev, bnxt_dev_uninit);
6245
6246         return ret;
6247 }
6248
6249 static void bnxt_free_rep_info(struct bnxt *bp)
6250 {
6251         rte_free(bp->rep_info);
6252         bp->rep_info = NULL;
6253         rte_free(bp->cfa_code_map);
6254         bp->cfa_code_map = NULL;
6255 }
6256
6257 static int bnxt_init_rep_info(struct bnxt *bp)
6258 {
6259         int i = 0, rc;
6260
6261         if (bp->rep_info)
6262                 return 0;
6263
6264         bp->rep_info = rte_zmalloc("bnxt_rep_info",
6265                                    sizeof(bp->rep_info[0]) * BNXT_MAX_VF_REPS,
6266                                    0);
6267         if (!bp->rep_info) {
6268                 PMD_DRV_LOG(ERR, "Failed to alloc memory for rep info\n");
6269                 return -ENOMEM;
6270         }
6271         bp->cfa_code_map = rte_zmalloc("bnxt_cfa_code_map",
6272                                        sizeof(*bp->cfa_code_map) *
6273                                        BNXT_MAX_CFA_CODE, 0);
6274         if (!bp->cfa_code_map) {
6275                 PMD_DRV_LOG(ERR, "Failed to alloc memory for cfa_code_map\n");
6276                 bnxt_free_rep_info(bp);
6277                 return -ENOMEM;
6278         }
6279
6280         for (i = 0; i < BNXT_MAX_CFA_CODE; i++)
6281                 bp->cfa_code_map[i] = BNXT_VF_IDX_INVALID;
6282
6283         rc = pthread_mutex_init(&bp->rep_info->vfr_lock, NULL);
6284         if (rc) {
6285                 PMD_DRV_LOG(ERR, "Unable to initialize vfr_lock\n");
6286                 bnxt_free_rep_info(bp);
6287                 return rc;
6288         }
6289
6290         rc = pthread_mutex_init(&bp->rep_info->vfr_start_lock, NULL);
6291         if (rc) {
6292                 PMD_DRV_LOG(ERR, "Unable to initialize vfr_start_lock\n");
6293                 bnxt_free_rep_info(bp);
6294                 return rc;
6295         }
6296
6297         return rc;
6298 }
6299
6300 static int bnxt_rep_port_probe(struct rte_pci_device *pci_dev,
6301                                struct rte_eth_devargs eth_da,
6302                                struct rte_eth_dev *backing_eth_dev,
6303                                const char *dev_args)
6304 {
6305         struct rte_eth_dev *vf_rep_eth_dev;
6306         char name[RTE_ETH_NAME_MAX_LEN];
6307         struct bnxt *backing_bp;
6308         uint16_t num_rep;
6309         int i, ret = 0;
6310         struct rte_kvargs *kvlist;
6311
6312         num_rep = eth_da.nb_representor_ports;
6313         if (num_rep > BNXT_MAX_VF_REPS) {
6314                 PMD_DRV_LOG(ERR, "nb_representor_ports = %d > %d MAX VF REPS\n",
6315                             num_rep, BNXT_MAX_VF_REPS);
6316                 return -EINVAL;
6317         }
6318
6319         if (num_rep >= RTE_MAX_ETHPORTS) {
6320                 PMD_DRV_LOG(ERR,
6321                             "nb_representor_ports = %d > %d MAX ETHPORTS\n",
6322                             num_rep, RTE_MAX_ETHPORTS);
6323                 return -EINVAL;
6324         }
6325
6326         backing_bp = backing_eth_dev->data->dev_private;
6327
6328         if (!(BNXT_PF(backing_bp) || BNXT_VF_IS_TRUSTED(backing_bp))) {
6329                 PMD_DRV_LOG(ERR,
6330                             "Not a PF or trusted VF. No Representor support\n");
6331                 /* Returning an error is not an option.
6332                  * Applications are not handling this correctly
6333                  */
6334                 return 0;
6335         }
6336
6337         if (bnxt_init_rep_info(backing_bp))
6338                 return 0;
6339
6340         for (i = 0; i < num_rep; i++) {
6341                 struct bnxt_representor representor = {
6342                         .vf_id = eth_da.representor_ports[i],
6343                         .switch_domain_id = backing_bp->switch_domain_id,
6344                         .parent_dev = backing_eth_dev
6345                 };
6346
6347                 if (representor.vf_id >= BNXT_MAX_VF_REPS) {
6348                         PMD_DRV_LOG(ERR, "VF-Rep id %d >= %d MAX VF ID\n",
6349                                     representor.vf_id, BNXT_MAX_VF_REPS);
6350                         continue;
6351                 }
6352
6353                 /* representor port net_bdf_port */
6354                 snprintf(name, sizeof(name), "net_%s_representor_%d",
6355                          pci_dev->device.name, eth_da.representor_ports[i]);
6356
6357                 kvlist = rte_kvargs_parse(dev_args, bnxt_dev_args);
6358                 if (kvlist) {
6359                         /*
6360                          * Handler for "rep_is_pf" devarg.
6361                          * Invoked as for ex: "-w 000:00:0d.0,
6362                          * rep-based-pf=<pf index> rep-is-pf=<VF=0 or PF=1>"
6363                          */
6364                         rte_kvargs_process(kvlist, BNXT_DEVARG_REP_IS_PF,
6365                                            bnxt_parse_devarg_rep_is_pf,
6366                                            (void *)&representor);
6367                         /*
6368                          * Handler for "rep_based_pf" devarg.
6369                          * Invoked as for ex: "-w 000:00:0d.0,
6370                          * rep-based-pf=<pf index> rep-is-pf=<VF=0 or PF=1>"
6371                          */
6372                         rte_kvargs_process(kvlist, BNXT_DEVARG_REP_BASED_PF,
6373                                            bnxt_parse_devarg_rep_based_pf,
6374                                            (void *)&representor);
6375                         /*
6376                          * Handler for "rep_based_pf" devarg.
6377                          * Invoked as for ex: "-w 000:00:0d.0,
6378                          * rep-based-pf=<pf index> rep-is-pf=<VF=0 or PF=1>"
6379                          */
6380                         rte_kvargs_process(kvlist, BNXT_DEVARG_REP_Q_R2F,
6381                                            bnxt_parse_devarg_rep_q_r2f,
6382                                            (void *)&representor);
6383                         /*
6384                          * Handler for "rep_based_pf" devarg.
6385                          * Invoked as for ex: "-w 000:00:0d.0,
6386                          * rep-based-pf=<pf index> rep-is-pf=<VF=0 or PF=1>"
6387                          */
6388                         rte_kvargs_process(kvlist, BNXT_DEVARG_REP_Q_F2R,
6389                                            bnxt_parse_devarg_rep_q_f2r,
6390                                            (void *)&representor);
6391                         /*
6392                          * Handler for "rep_based_pf" devarg.
6393                          * Invoked as for ex: "-w 000:00:0d.0,
6394                          * rep-based-pf=<pf index> rep-is-pf=<VF=0 or PF=1>"
6395                          */
6396                         rte_kvargs_process(kvlist, BNXT_DEVARG_REP_FC_R2F,
6397                                            bnxt_parse_devarg_rep_fc_r2f,
6398                                            (void *)&representor);
6399                         /*
6400                          * Handler for "rep_based_pf" devarg.
6401                          * Invoked as for ex: "-w 000:00:0d.0,
6402                          * rep-based-pf=<pf index> rep-is-pf=<VF=0 or PF=1>"
6403                          */
6404                         rte_kvargs_process(kvlist, BNXT_DEVARG_REP_FC_F2R,
6405                                            bnxt_parse_devarg_rep_fc_f2r,
6406                                            (void *)&representor);
6407                 }
6408
6409                 ret = rte_eth_dev_create(&pci_dev->device, name,
6410                                          sizeof(struct bnxt_representor),
6411                                          NULL, NULL,
6412                                          bnxt_representor_init,
6413                                          &representor);
6414                 if (ret) {
6415                         PMD_DRV_LOG(ERR, "failed to create bnxt vf "
6416                                     "representor %s.", name);
6417                         goto err;
6418                 }
6419
6420                 vf_rep_eth_dev = rte_eth_dev_allocated(name);
6421                 if (!vf_rep_eth_dev) {
6422                         PMD_DRV_LOG(ERR, "Failed to find the eth_dev"
6423                                     " for VF-Rep: %s.", name);
6424                         ret = -ENODEV;
6425                         goto err;
6426                 }
6427
6428                 PMD_DRV_LOG(DEBUG, "BNXT Port:%d VFR pci probe\n",
6429                             backing_eth_dev->data->port_id);
6430                 backing_bp->rep_info[representor.vf_id].vfr_eth_dev =
6431                                                          vf_rep_eth_dev;
6432                 backing_bp->num_reps++;
6433
6434         }
6435
6436         return 0;
6437
6438 err:
6439         /* If num_rep > 1, then rollback already created
6440          * ports, since we'll be failing the probe anyway
6441          */
6442         if (num_rep > 1)
6443                 bnxt_pci_remove_dev_with_reps(backing_eth_dev);
6444
6445         return ret;
6446 }
6447
6448 static int bnxt_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
6449                           struct rte_pci_device *pci_dev)
6450 {
6451         struct rte_eth_devargs eth_da = { .nb_representor_ports = 0 };
6452         struct rte_eth_dev *backing_eth_dev;
6453         uint16_t num_rep;
6454         int ret = 0;
6455
6456         if (pci_dev->device.devargs) {
6457                 ret = rte_eth_devargs_parse(pci_dev->device.devargs->args,
6458                                             &eth_da);
6459                 if (ret)
6460                         return ret;
6461         }
6462
6463         num_rep = eth_da.nb_representor_ports;
6464         PMD_DRV_LOG(DEBUG, "nb_representor_ports = %d\n",
6465                     num_rep);
6466
6467         /* We could come here after first level of probe is already invoked
6468          * as part of an application bringup(OVS-DPDK vswitchd), so first check
6469          * for already allocated eth_dev for the backing device (PF/Trusted VF)
6470          */
6471         backing_eth_dev = rte_eth_dev_allocated(pci_dev->device.name);
6472         if (backing_eth_dev == NULL) {
6473                 ret = rte_eth_dev_create(&pci_dev->device, pci_dev->device.name,
6474                                          sizeof(struct bnxt),
6475                                          eth_dev_pci_specific_init, pci_dev,
6476                                          bnxt_dev_init, NULL);
6477
6478                 if (ret || !num_rep)
6479                         return ret;
6480
6481                 backing_eth_dev = rte_eth_dev_allocated(pci_dev->device.name);
6482         }
6483         PMD_DRV_LOG(DEBUG, "BNXT Port:%d pci probe\n",
6484                     backing_eth_dev->data->port_id);
6485
6486         if (!num_rep)
6487                 return ret;
6488
6489         /* probe representor ports now */
6490         ret = bnxt_rep_port_probe(pci_dev, eth_da, backing_eth_dev,
6491                                   pci_dev->device.devargs->args);
6492
6493         return ret;
6494 }
6495
6496 static int bnxt_pci_remove(struct rte_pci_device *pci_dev)
6497 {
6498         struct rte_eth_dev *eth_dev;
6499
6500         eth_dev = rte_eth_dev_allocated(pci_dev->device.name);
6501         if (!eth_dev)
6502                 return 0; /* Invoked typically only by OVS-DPDK, by the
6503                            * time it comes here the eth_dev is already
6504                            * deleted by rte_eth_dev_close(), so returning
6505                            * +ve value will at least help in proper cleanup
6506                            */
6507
6508         PMD_DRV_LOG(DEBUG, "BNXT Port:%d pci remove\n", eth_dev->data->port_id);
6509         if (rte_eal_process_type() == RTE_PROC_PRIMARY) {
6510                 if (eth_dev->data->dev_flags & RTE_ETH_DEV_REPRESENTOR)
6511                         return rte_eth_dev_destroy(eth_dev,
6512                                                    bnxt_representor_uninit);
6513                 else
6514                         return rte_eth_dev_destroy(eth_dev,
6515                                                    bnxt_dev_uninit);
6516         } else {
6517                 return rte_eth_dev_pci_generic_remove(pci_dev, NULL);
6518         }
6519 }
6520
6521 static struct rte_pci_driver bnxt_rte_pmd = {
6522         .id_table = bnxt_pci_id_map,
6523         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC |
6524                         RTE_PCI_DRV_PROBE_AGAIN, /* Needed in case of VF-REPs
6525                                                   * and OVS-DPDK
6526                                                   */
6527         .probe = bnxt_pci_probe,
6528         .remove = bnxt_pci_remove,
6529 };
6530
6531 static bool
6532 is_device_supported(struct rte_eth_dev *dev, struct rte_pci_driver *drv)
6533 {
6534         if (strcmp(dev->device->driver->name, drv->driver.name))
6535                 return false;
6536
6537         return true;
6538 }
6539
6540 bool is_bnxt_supported(struct rte_eth_dev *dev)
6541 {
6542         return is_device_supported(dev, &bnxt_rte_pmd);
6543 }
6544
6545 RTE_LOG_REGISTER(bnxt_logtype_driver, pmd.net.bnxt.driver, NOTICE);
6546 RTE_PMD_REGISTER_PCI(net_bnxt, bnxt_rte_pmd);
6547 RTE_PMD_REGISTER_PCI_TABLE(net_bnxt, bnxt_pci_id_map);
6548 RTE_PMD_REGISTER_KMOD_DEP(net_bnxt, "* igb_uio | uio_pci_generic | vfio-pci");