drivers/net/bnxt/bnxt_ethdev.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2014-2018 Broadcom
   3  * All rights reserved.
   4  */
   5
   6 #include <inttypes.h>
   7 #include <stdbool.h>
   8
   9 #include <rte_dev.h>
  10 #include <rte_ethdev_driver.h>
  11 #include <rte_ethdev_pci.h>
  12 #include <rte_malloc.h>
  13 #include <rte_cycles.h>
  14 #include <rte_alarm.h>
  15
  16 #include "bnxt.h"
  17 #include "bnxt_filter.h"
  18 #include "bnxt_hwrm.h"
  19 #include "bnxt_irq.h"
  20 #include "bnxt_ring.h"
  21 #include "bnxt_rxq.h"
  22 #include "bnxt_rxr.h"
  23 #include "bnxt_stats.h"
  24 #include "bnxt_txq.h"
  25 #include "bnxt_txr.h"
  26 #include "bnxt_vnic.h"
  27 #include "hsi_struct_def_dpdk.h"
  28 #include "bnxt_nvm_defs.h"
  29
  30 #define DRV_MODULE_NAME         "bnxt"
  31 static const char bnxt_version[] =
  32         "Broadcom NetXtreme driver " DRV_MODULE_NAME;
  33 int bnxt_logtype_driver;
  34
  35 /*
  36  * The set of PCI devices this driver supports
  37  */
  38 static const struct rte_pci_id bnxt_pci_id_map[] = {
  39         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM,
  40                          BROADCOM_DEV_ID_STRATUS_NIC_VF1) },
  41         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM,
  42                          BROADCOM_DEV_ID_STRATUS_NIC_VF2) },
  43         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_STRATUS_NIC) },
  44         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414_VF) },
  45         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57301) },
  46         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57302) },
  47         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57304_PF) },
  48         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57304_VF) },
  49         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_NS2) },
  50         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57402) },
  51         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57404) },
  52         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57406_PF) },
  53         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57406_VF) },
  54         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57402_MF) },
  55         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57407_RJ45) },
  56         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57404_MF) },
  57         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57406_MF) },
  58         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57407_SFP) },
  59         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57407_MF) },
  60         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_5741X_VF) },
  61         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_5731X_VF) },
  62         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57314) },
  63         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_MF) },
  64         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57311) },
  65         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57312) },
  66         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57412) },
  67         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414) },
  68         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_RJ45) },
  69         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_RJ45) },
  70         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57412_MF) },
  71         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57317_RJ45) },
  72         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_SFP) },
  73         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_SFP) },
  74         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57317_SFP) },
  75         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414_MF) },
  76         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_MF) },
  77         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58802) },
  78         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58804) },
  79         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58808) },
  80         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58802_VF) },
  81         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57508) },
  82         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57504) },
  83         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57502) },
  84         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57500_VF1) },
  85         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57500_VF2) },
  86         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57508_MF1) },
  87         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57504_MF1) },
  88         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57502_MF1) },
  89         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57508_MF2) },
  90         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57504_MF2) },
  91         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57502_MF2) },
  92         { .vendor_id = 0, /* sentinel */ },
  93 };
  94
  95 #define BNXT_ETH_RSS_SUPPORT (  \
  96         ETH_RSS_IPV4 |          \
  97         ETH_RSS_NONFRAG_IPV4_TCP |      \
  98         ETH_RSS_NONFRAG_IPV4_UDP |      \
  99         ETH_RSS_IPV6 |          \
 100         ETH_RSS_NONFRAG_IPV6_TCP |      \
 101         ETH_RSS_NONFRAG_IPV6_UDP)
 102
 103 #define BNXT_DEV_TX_OFFLOAD_SUPPORT (DEV_TX_OFFLOAD_VLAN_INSERT | \
 104                                      DEV_TX_OFFLOAD_IPV4_CKSUM | \
 105                                      DEV_TX_OFFLOAD_TCP_CKSUM | \
 106                                      DEV_TX_OFFLOAD_UDP_CKSUM | \
 107                                      DEV_TX_OFFLOAD_TCP_TSO | \
 108                                      DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM | \
 109                                      DEV_TX_OFFLOAD_VXLAN_TNL_TSO | \
 110                                      DEV_TX_OFFLOAD_GRE_TNL_TSO | \
 111                                      DEV_TX_OFFLOAD_IPIP_TNL_TSO | \
 112                                      DEV_TX_OFFLOAD_GENEVE_TNL_TSO | \
 113                                      DEV_TX_OFFLOAD_QINQ_INSERT | \
 114                                      DEV_TX_OFFLOAD_MULTI_SEGS)
 115
 116 #define BNXT_DEV_RX_OFFLOAD_SUPPORT (DEV_RX_OFFLOAD_VLAN_FILTER | \
 117                                      DEV_RX_OFFLOAD_VLAN_STRIP | \
 118                                      DEV_RX_OFFLOAD_IPV4_CKSUM | \
 119                                      DEV_RX_OFFLOAD_UDP_CKSUM | \
 120                                      DEV_RX_OFFLOAD_TCP_CKSUM | \
 121                                      DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM | \
 122                                      DEV_RX_OFFLOAD_JUMBO_FRAME | \
 123                                      DEV_RX_OFFLOAD_KEEP_CRC | \
 124                                      DEV_RX_OFFLOAD_VLAN_EXTEND | \
 125                                      DEV_RX_OFFLOAD_TCP_LRO | \
 126                                      DEV_RX_OFFLOAD_SCATTER)
 127
 128 static int bnxt_vlan_offload_set_op(struct rte_eth_dev *dev, int mask);
 129 static void bnxt_print_link_info(struct rte_eth_dev *eth_dev);
 130 static int bnxt_dev_uninit(struct rte_eth_dev *eth_dev);
 131 static int bnxt_init_resources(struct bnxt *bp, bool reconfig_dev);
 132 static int bnxt_uninit_resources(struct bnxt *bp, bool reconfig_dev);
 133 static void bnxt_cancel_fw_health_check(struct bnxt *bp);
 134
 135 int is_bnxt_in_error(struct bnxt *bp)
 136 {
 137         if (bp->flags & BNXT_FLAG_FATAL_ERROR)
 138                 return -EIO;
 139         if (bp->flags & BNXT_FLAG_FW_RESET)
 140                 return -EBUSY;
 141
 142         return 0;
 143 }
 144
 145 /***********************/
 146
 147 /*
 148  * High level utility functions
 149  */
 150
 151 uint16_t bnxt_rss_ctxts(const struct bnxt *bp)
 152 {
 153         if (!BNXT_CHIP_THOR(bp))
 154                 return 1;
 155
 156         return RTE_ALIGN_MUL_CEIL(bp->rx_nr_rings,
 157                                   BNXT_RSS_ENTRIES_PER_CTX_THOR) /
 158                                     BNXT_RSS_ENTRIES_PER_CTX_THOR;
 159 }
 160
 161 static uint16_t  bnxt_rss_hash_tbl_size(const struct bnxt *bp)
 162 {
 163         if (!BNXT_CHIP_THOR(bp))
 164                 return HW_HASH_INDEX_SIZE;
 165
 166         return bnxt_rss_ctxts(bp) * BNXT_RSS_ENTRIES_PER_CTX_THOR;
 167 }
 168
 169 static void bnxt_free_mem(struct bnxt *bp, bool reconfig)
 170 {
 171         bnxt_free_filter_mem(bp);
 172         bnxt_free_vnic_attributes(bp);
 173         bnxt_free_vnic_mem(bp);
 174
 175         /* tx/rx rings are configured as part of *_queue_setup callbacks.
 176          * If the number of rings change across fw update,
 177          * we don't have much choice except to warn the user.
 178          */
 179         if (!reconfig) {
 180                 bnxt_free_stats(bp);
 181                 bnxt_free_tx_rings(bp);
 182                 bnxt_free_rx_rings(bp);
 183         }
 184         bnxt_free_async_cp_ring(bp);
 185         bnxt_free_rxtx_nq_ring(bp);
 186 }
 187
 188 static int bnxt_alloc_mem(struct bnxt *bp, bool reconfig)
 189 {
 190         int rc;
 191
 192         rc = bnxt_alloc_ring_grps(bp);
 193         if (rc)
 194                 goto alloc_mem_err;
 195
 196         rc = bnxt_alloc_async_ring_struct(bp);
 197         if (rc)
 198                 goto alloc_mem_err;
 199
 200         rc = bnxt_alloc_vnic_mem(bp);
 201         if (rc)
 202                 goto alloc_mem_err;
 203
 204         rc = bnxt_alloc_vnic_attributes(bp);
 205         if (rc)
 206                 goto alloc_mem_err;
 207
 208         rc = bnxt_alloc_filter_mem(bp);
 209         if (rc)
 210                 goto alloc_mem_err;
 211
 212         rc = bnxt_alloc_async_cp_ring(bp);
 213         if (rc)
 214                 goto alloc_mem_err;
 215
 216         rc = bnxt_alloc_rxtx_nq_ring(bp);
 217         if (rc)
 218                 goto alloc_mem_err;
 219
 220         return 0;
 221
 222 alloc_mem_err:
 223         bnxt_free_mem(bp, reconfig);
 224         return rc;
 225 }
 226
 227 static int bnxt_init_chip(struct bnxt *bp)
 228 {
 229         struct bnxt_rx_queue *rxq;
 230         struct rte_eth_link new;
 231         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(bp->eth_dev);
 232         struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
 233         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
 234         uint64_t rx_offloads = dev_conf->rxmode.offloads;
 235         uint32_t intr_vector = 0;
 236         uint32_t queue_id, base = BNXT_MISC_VEC_ID;
 237         uint32_t vec = BNXT_MISC_VEC_ID;
 238         unsigned int i, j;
 239         int rc;
 240
 241         if (bp->eth_dev->data->mtu > RTE_ETHER_MTU) {
 242                 bp->eth_dev->data->dev_conf.rxmode.offloads |=
 243                         DEV_RX_OFFLOAD_JUMBO_FRAME;
 244                 bp->flags |= BNXT_FLAG_JUMBO;
 245         } else {
 246                 bp->eth_dev->data->dev_conf.rxmode.offloads &=
 247                         ~DEV_RX_OFFLOAD_JUMBO_FRAME;
 248                 bp->flags &= ~BNXT_FLAG_JUMBO;
 249         }
 250
 251         /* THOR does not support ring groups.
 252          * But we will use the array to save RSS context IDs.
 253          */
 254         if (BNXT_CHIP_THOR(bp))
 255                 bp->max_ring_grps = BNXT_MAX_RSS_CTXTS_THOR;
 256
 257         rc = bnxt_alloc_all_hwrm_stat_ctxs(bp);
 258         if (rc) {
 259                 PMD_DRV_LOG(ERR, "HWRM stat ctx alloc failure rc: %x\n", rc);
 260                 goto err_out;
 261         }
 262
 263         rc = bnxt_alloc_hwrm_rings(bp);
 264         if (rc) {
 265                 PMD_DRV_LOG(ERR, "HWRM ring alloc failure rc: %x\n", rc);
 266                 goto err_out;
 267         }
 268
 269         rc = bnxt_alloc_all_hwrm_ring_grps(bp);
 270         if (rc) {
 271                 PMD_DRV_LOG(ERR, "HWRM ring grp alloc failure: %x\n", rc);
 272                 goto err_out;
 273         }
 274
 275         if (!(bp->vnic_cap_flags & BNXT_VNIC_CAP_COS_CLASSIFY))
 276                 goto skip_cosq_cfg;
 277
 278         for (j = 0, i = 0; i < BNXT_COS_QUEUE_COUNT; i++) {
 279                 if (bp->rx_cos_queue[i].id != 0xff) {
 280                         struct bnxt_vnic_info *vnic = &bp->vnic_info[j++];
 281
 282                         if (!vnic) {
 283                                 PMD_DRV_LOG(ERR,
 284                                             "Num pools more than FW profile\n");
 285                                 rc = -EINVAL;
 286                                 goto err_out;
 287                         }
 288                         vnic->cos_queue_id = bp->rx_cos_queue[i].id;
 289                         bp->rx_cosq_cnt++;
 290                 }
 291         }
 292
 293 skip_cosq_cfg:
 294         rc = bnxt_mq_rx_configure(bp);
 295         if (rc) {
 296                 PMD_DRV_LOG(ERR, "MQ mode configure failure rc: %x\n", rc);
 297                 goto err_out;
 298         }
 299
 300         /* VNIC configuration */
 301         for (i = 0; i < bp->nr_vnics; i++) {
 302                 struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
 303                 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
 304
 305                 rc = bnxt_vnic_grp_alloc(bp, vnic);
 306                 if (rc)
 307                         goto err_out;
 308
 309                 PMD_DRV_LOG(DEBUG, "vnic[%d] = %p vnic->fw_grp_ids = %p\n",
 310                             i, vnic, vnic->fw_grp_ids);
 311
 312                 rc = bnxt_hwrm_vnic_alloc(bp, vnic);
 313                 if (rc) {
 314                         PMD_DRV_LOG(ERR, "HWRM vnic %d alloc failure rc: %x\n",
 315                                 i, rc);
 316                         goto err_out;
 317                 }
 318
 319                 /* Alloc RSS context only if RSS mode is enabled */
 320                 if (dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS) {
 321                         int j, nr_ctxs = bnxt_rss_ctxts(bp);
 322
 323                         rc = 0;
 324                         for (j = 0; j < nr_ctxs; j++) {
 325                                 rc = bnxt_hwrm_vnic_ctx_alloc(bp, vnic, j);
 326                                 if (rc)
 327                                         break;
 328                         }
 329                         if (rc) {
 330                                 PMD_DRV_LOG(ERR,
 331                                   "HWRM vnic %d ctx %d alloc failure rc: %x\n",
 332                                   i, j, rc);
 333                                 goto err_out;
 334                         }
 335                         vnic->num_lb_ctxts = nr_ctxs;
 336                 }
 337
 338                 /*
 339                  * Firmware sets pf pair in default vnic cfg. If the VLAN strip
 340                  * setting is not available at this time, it will not be
 341                  * configured correctly in the CFA.
 342                  */
 343                 if (rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
 344                         vnic->vlan_strip = true;
 345                 else
 346                         vnic->vlan_strip = false;
 347
 348                 rc = bnxt_hwrm_vnic_cfg(bp, vnic);
 349                 if (rc) {
 350                         PMD_DRV_LOG(ERR, "HWRM vnic %d cfg failure rc: %x\n",
 351                                 i, rc);
 352                         goto err_out;
 353                 }
 354
 355                 rc = bnxt_set_hwrm_vnic_filters(bp, vnic);
 356                 if (rc) {
 357                         PMD_DRV_LOG(ERR,
 358                                 "HWRM vnic %d filter failure rc: %x\n",
 359                                 i, rc);
 360                         goto err_out;
 361                 }
 362
 363                 for (j = 0; j < bp->rx_num_qs_per_vnic; j++) {
 364                         rxq = bp->eth_dev->data->rx_queues[j];
 365
 366                         PMD_DRV_LOG(DEBUG,
 367                                     "rxq[%d]->vnic=%p vnic->fw_grp_ids=%p\n",
 368                                     j, rxq->vnic, rxq->vnic->fw_grp_ids);
 369
 370                         if (BNXT_HAS_RING_GRPS(bp) && rxq->rx_deferred_start)
 371                                 rxq->vnic->fw_grp_ids[j] = INVALID_HW_RING_ID;
 372                 }
 373
 374                 rc = bnxt_vnic_rss_configure(bp, vnic);
 375                 if (rc) {
 376                         PMD_DRV_LOG(ERR,
 377                                     "HWRM vnic set RSS failure rc: %x\n", rc);
 378                         goto err_out;
 379                 }
 380
 381                 bnxt_hwrm_vnic_plcmode_cfg(bp, vnic);
 382
 383                 if (bp->eth_dev->data->dev_conf.rxmode.offloads &
 384                     DEV_RX_OFFLOAD_TCP_LRO)
 385                         bnxt_hwrm_vnic_tpa_cfg(bp, vnic, 1);
 386                 else
 387                         bnxt_hwrm_vnic_tpa_cfg(bp, vnic, 0);
 388         }
 389         rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, &bp->vnic_info[0], 0, NULL);
 390         if (rc) {
 391                 PMD_DRV_LOG(ERR,
 392                         "HWRM cfa l2 rx mask failure rc: %x\n", rc);
 393                 goto err_out;
 394         }
 395
 396         /* check and configure queue intr-vector mapping */
 397         if ((rte_intr_cap_multiple(intr_handle) ||
 398              !RTE_ETH_DEV_SRIOV(bp->eth_dev).active) &&
 399             bp->eth_dev->data->dev_conf.intr_conf.rxq != 0) {
 400                 intr_vector = bp->eth_dev->data->nb_rx_queues;
 401                 PMD_DRV_LOG(DEBUG, "intr_vector = %d\n", intr_vector);
 402                 if (intr_vector > bp->rx_cp_nr_rings) {
 403                         PMD_DRV_LOG(ERR, "At most %d intr queues supported",
 404                                         bp->rx_cp_nr_rings);
 405                         return -ENOTSUP;
 406                 }
 407                 rc = rte_intr_efd_enable(intr_handle, intr_vector);
 408                 if (rc)
 409                         return rc;
 410         }
 411
 412         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
 413                 intr_handle->intr_vec =
 414                         rte_zmalloc("intr_vec",
 415                                     bp->eth_dev->data->nb_rx_queues *
 416                                     sizeof(int), 0);
 417                 if (intr_handle->intr_vec == NULL) {
 418                         PMD_DRV_LOG(ERR, "Failed to allocate %d rx_queues"
 419                                 " intr_vec", bp->eth_dev->data->nb_rx_queues);
 420                         rc = -ENOMEM;
 421                         goto err_disable;
 422                 }
 423                 PMD_DRV_LOG(DEBUG, "intr_handle->intr_vec = %p "
 424                         "intr_handle->nb_efd = %d intr_handle->max_intr = %d\n",
 425                          intr_handle->intr_vec, intr_handle->nb_efd,
 426                         intr_handle->max_intr);
 427                 for (queue_id = 0; queue_id < bp->eth_dev->data->nb_rx_queues;
 428                      queue_id++) {
 429                         intr_handle->intr_vec[queue_id] =
 430                                                         vec + BNXT_RX_VEC_START;
 431                         if (vec < base + intr_handle->nb_efd - 1)
 432                                 vec++;
 433                 }
 434         }
 435
 436         /* enable uio/vfio intr/eventfd mapping */
 437         rc = rte_intr_enable(intr_handle);
 438         if (rc)
 439                 goto err_free;
 440
 441         rc = bnxt_get_hwrm_link_config(bp, &new);
 442         if (rc) {
 443                 PMD_DRV_LOG(ERR, "HWRM Get link config failure rc: %x\n", rc);
 444                 goto err_free;
 445         }
 446
 447         if (!bp->link_info.link_up) {
 448                 rc = bnxt_set_hwrm_link_config(bp, true);
 449                 if (rc) {
 450                         PMD_DRV_LOG(ERR,
 451                                 "HWRM link config failure rc: %x\n", rc);
 452                         goto err_free;
 453                 }
 454         }
 455         bnxt_print_link_info(bp->eth_dev);
 456
 457         return 0;
 458
 459 err_free:
 460         rte_free(intr_handle->intr_vec);
 461 err_disable:
 462         rte_intr_efd_disable(intr_handle);
 463 err_out:
 464         /* Some of the error status returned by FW may not be from errno.h */
 465         if (rc > 0)
 466                 rc = -EIO;
 467
 468         return rc;
 469 }
 470
 471 static int bnxt_shutdown_nic(struct bnxt *bp)
 472 {
 473         bnxt_free_all_hwrm_resources(bp);
 474         bnxt_free_all_filters(bp);
 475         bnxt_free_all_vnics(bp);
 476         return 0;
 477 }
 478
 479 static int bnxt_init_nic(struct bnxt *bp)
 480 {
 481         int rc;
 482
 483         if (BNXT_HAS_RING_GRPS(bp)) {
 484                 rc = bnxt_init_ring_grps(bp);
 485                 if (rc)
 486                         return rc;
 487         }
 488
 489         bnxt_init_vnics(bp);
 490         bnxt_init_filters(bp);
 491
 492         return 0;
 493 }
 494
 495 /*
 496  * Device configuration and status function
 497  */
 498
 499 static int bnxt_dev_info_get_op(struct rte_eth_dev *eth_dev,
 500                                 struct rte_eth_dev_info *dev_info)
 501 {
 502         struct rte_pci_device *pdev = RTE_DEV_TO_PCI(eth_dev->device);
 503         struct bnxt *bp = eth_dev->data->dev_private;
 504         uint16_t max_vnics, i, j, vpool, vrxq;
 505         unsigned int max_rx_rings;
 506         int rc;
 507
 508         rc = is_bnxt_in_error(bp);
 509         if (rc)
 510                 return rc;
 511
 512         /* MAC Specifics */
 513         dev_info->max_mac_addrs = bp->max_l2_ctx;
 514         dev_info->max_hash_mac_addrs = 0;
 515
 516         /* PF/VF specifics */
 517         if (BNXT_PF(bp))
 518                 dev_info->max_vfs = pdev->max_vfs;
 519
 520         max_rx_rings = RTE_MIN(bp->max_rx_rings, bp->max_stat_ctx);
 521         /* For the sake of symmetry, max_rx_queues = max_tx_queues */
 522         dev_info->max_rx_queues = max_rx_rings;
 523         dev_info->max_tx_queues = max_rx_rings;
 524         dev_info->reta_size = bnxt_rss_hash_tbl_size(bp);
 525         dev_info->hash_key_size = 40;
 526         max_vnics = bp->max_vnics;
 527
 528         /* MTU specifics */
 529         dev_info->min_mtu = RTE_ETHER_MIN_MTU;
 530         dev_info->max_mtu = BNXT_MAX_MTU;
 531
 532         /* Fast path specifics */
 533         dev_info->min_rx_bufsize = 1;
 534         dev_info->max_rx_pktlen = BNXT_MAX_PKT_LEN;
 535
 536         dev_info->rx_offload_capa = BNXT_DEV_RX_OFFLOAD_SUPPORT;
 537         if (bp->flags & BNXT_FLAG_PTP_SUPPORTED)
 538                 dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_TIMESTAMP;
 539         dev_info->tx_offload_capa = BNXT_DEV_TX_OFFLOAD_SUPPORT;
 540         dev_info->flow_type_rss_offloads = BNXT_ETH_RSS_SUPPORT;
 541
 542         /* *INDENT-OFF* */
 543         dev_info->default_rxconf = (struct rte_eth_rxconf) {
 544                 .rx_thresh = {
 545                         .pthresh = 8,
 546                         .hthresh = 8,
 547                         .wthresh = 0,
 548                 },
 549                 .rx_free_thresh = 32,
 550                 /* If no descriptors available, pkts are dropped by default */
 551                 .rx_drop_en = 1,
 552         };
 553
 554         dev_info->default_txconf = (struct rte_eth_txconf) {
 555                 .tx_thresh = {
 556                         .pthresh = 32,
 557                         .hthresh = 0,
 558                         .wthresh = 0,
 559                 },
 560                 .tx_free_thresh = 32,
 561                 .tx_rs_thresh = 32,
 562         };
 563         eth_dev->data->dev_conf.intr_conf.lsc = 1;
 564
 565         eth_dev->data->dev_conf.intr_conf.rxq = 1;
 566         dev_info->rx_desc_lim.nb_min = BNXT_MIN_RING_DESC;
 567         dev_info->rx_desc_lim.nb_max = BNXT_MAX_RX_RING_DESC;
 568         dev_info->tx_desc_lim.nb_min = BNXT_MIN_RING_DESC;
 569         dev_info->tx_desc_lim.nb_max = BNXT_MAX_TX_RING_DESC;
 570
 571         /* *INDENT-ON* */
 572
 573         /*
 574          * TODO: default_rxconf, default_txconf, rx_desc_lim, and tx_desc_lim
 575          *       need further investigation.
 576          */
 577
 578         /* VMDq resources */
 579         vpool = 64; /* ETH_64_POOLS */
 580         vrxq = 128; /* ETH_VMDQ_DCB_NUM_QUEUES */
 581         for (i = 0; i < 4; vpool >>= 1, i++) {
 582                 if (max_vnics > vpool) {
 583                         for (j = 0; j < 5; vrxq >>= 1, j++) {
 584                                 if (dev_info->max_rx_queues > vrxq) {
 585                                         if (vpool > vrxq)
 586                                                 vpool = vrxq;
 587                                         goto found;
 588                                 }
 589                         }
 590                         /* Not enough resources to support VMDq */
 591                         break;
 592                 }
 593         }
 594         /* Not enough resources to support VMDq */
 595         vpool = 0;
 596         vrxq = 0;
 597 found:
 598         dev_info->max_vmdq_pools = vpool;
 599         dev_info->vmdq_queue_num = vrxq;
 600
 601         dev_info->vmdq_pool_base = 0;
 602         dev_info->vmdq_queue_base = 0;
 603
 604         return 0;
 605 }
 606
 607 /* Configure the device based on the configuration provided */
 608 static int bnxt_dev_configure_op(struct rte_eth_dev *eth_dev)
 609 {
 610         struct bnxt *bp = eth_dev->data->dev_private;
 611         uint64_t rx_offloads = eth_dev->data->dev_conf.rxmode.offloads;
 612         int rc;
 613
 614         bp->rx_queues = (void *)eth_dev->data->rx_queues;
 615         bp->tx_queues = (void *)eth_dev->data->tx_queues;
 616         bp->tx_nr_rings = eth_dev->data->nb_tx_queues;
 617         bp->rx_nr_rings = eth_dev->data->nb_rx_queues;
 618
 619         rc = is_bnxt_in_error(bp);
 620         if (rc)
 621                 return rc;
 622
 623         if (BNXT_VF(bp) && (bp->flags & BNXT_FLAG_NEW_RM)) {
 624                 rc = bnxt_hwrm_check_vf_rings(bp);
 625                 if (rc) {
 626                         PMD_DRV_LOG(ERR, "HWRM insufficient resources\n");
 627                         return -ENOSPC;
 628                 }
 629
 630                 /* If a resource has already been allocated - in this case
 631                  * it is the async completion ring, free it. Reallocate it after
 632                  * resource reservation. This will ensure the resource counts
 633                  * are calculated correctly.
 634                  */
 635
 636                 pthread_mutex_lock(&bp->def_cp_lock);
 637
 638                 if (!BNXT_HAS_NQ(bp) && bp->async_cp_ring) {
 639                         bnxt_disable_int(bp);
 640                         bnxt_free_cp_ring(bp, bp->async_cp_ring);
 641                 }
 642
 643                 rc = bnxt_hwrm_func_reserve_vf_resc(bp, false);
 644                 if (rc) {
 645                         PMD_DRV_LOG(ERR, "HWRM resource alloc fail:%x\n", rc);
 646                         pthread_mutex_unlock(&bp->def_cp_lock);
 647                         return -ENOSPC;
 648                 }
 649
 650                 if (!BNXT_HAS_NQ(bp) && bp->async_cp_ring) {
 651                         rc = bnxt_alloc_async_cp_ring(bp);
 652                         if (rc) {
 653                                 pthread_mutex_unlock(&bp->def_cp_lock);
 654                                 return rc;
 655                         }
 656                         bnxt_enable_int(bp);
 657                 }
 658
 659                 pthread_mutex_unlock(&bp->def_cp_lock);
 660         } else {
 661                 /* legacy driver needs to get updated values */
 662                 rc = bnxt_hwrm_func_qcaps(bp);
 663                 if (rc) {
 664                         PMD_DRV_LOG(ERR, "hwrm func qcaps fail:%d\n", rc);
 665                         return rc;
 666                 }
 667         }
 668
 669         /* Inherit new configurations */
 670         if (eth_dev->data->nb_rx_queues > bp->max_rx_rings ||
 671             eth_dev->data->nb_tx_queues > bp->max_tx_rings ||
 672             eth_dev->data->nb_rx_queues + eth_dev->data->nb_tx_queues
 673                 + BNXT_NUM_ASYNC_CPR(bp) > bp->max_cp_rings ||
 674             eth_dev->data->nb_rx_queues + eth_dev->data->nb_tx_queues >
 675             bp->max_stat_ctx)
 676                 goto resource_error;
 677
 678         if (BNXT_HAS_RING_GRPS(bp) &&
 679             (uint32_t)(eth_dev->data->nb_rx_queues) > bp->max_ring_grps)
 680                 goto resource_error;
 681
 682         if (!(eth_dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_RSS) &&
 683             bp->max_vnics < eth_dev->data->nb_rx_queues)
 684                 goto resource_error;
 685
 686         bp->rx_cp_nr_rings = bp->rx_nr_rings;
 687         bp->tx_cp_nr_rings = bp->tx_nr_rings;
 688
 689         if (rx_offloads & DEV_RX_OFFLOAD_JUMBO_FRAME) {
 690                 eth_dev->data->mtu =
 691                         eth_dev->data->dev_conf.rxmode.max_rx_pkt_len -
 692                         RTE_ETHER_HDR_LEN - RTE_ETHER_CRC_LEN - VLAN_TAG_SIZE *
 693                         BNXT_NUM_VLANS;
 694                 bnxt_mtu_set_op(eth_dev, eth_dev->data->mtu);
 695         }
 696         return 0;
 697
 698 resource_error:
 699         PMD_DRV_LOG(ERR,
 700                     "Insufficient resources to support requested config\n");
 701         PMD_DRV_LOG(ERR,
 702                     "Num Queues Requested: Tx %d, Rx %d\n",
 703                     eth_dev->data->nb_tx_queues,
 704                     eth_dev->data->nb_rx_queues);
 705         PMD_DRV_LOG(ERR,
 706                     "MAX: TxQ %d, RxQ %d, CQ %d Stat %d, Grp %d, Vnic %d\n",
 707                     bp->max_tx_rings, bp->max_rx_rings, bp->max_cp_rings,
 708                     bp->max_stat_ctx, bp->max_ring_grps, bp->max_vnics);
 709         return -ENOSPC;
 710 }
 711
 712 static void bnxt_print_link_info(struct rte_eth_dev *eth_dev)
 713 {
 714         struct rte_eth_link *link = &eth_dev->data->dev_link;
 715
 716         if (link->link_status)
 717                 PMD_DRV_LOG(INFO, "Port %d Link Up - speed %u Mbps - %s\n",
 718                         eth_dev->data->port_id,
 719                         (uint32_t)link->link_speed,
 720                         (link->link_duplex == ETH_LINK_FULL_DUPLEX) ?
 721                         ("full-duplex") : ("half-duplex\n"));
 722         else
 723                 PMD_DRV_LOG(INFO, "Port %d Link Down\n",
 724                         eth_dev->data->port_id);
 725 }
 726
 727 /*
 728  * Determine whether the current configuration requires support for scattered
 729  * receive; return 1 if scattered receive is required and 0 if not.
 730  */
 731 static int bnxt_scattered_rx(struct rte_eth_dev *eth_dev)
 732 {
 733         uint16_t buf_size;
 734         int i;
 735
 736         if (eth_dev->data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_SCATTER)
 737                 return 1;
 738
 739         for (i = 0; i < eth_dev->data->nb_rx_queues; i++) {
 740                 struct bnxt_rx_queue *rxq = eth_dev->data->rx_queues[i];
 741
 742                 buf_size = (uint16_t)(rte_pktmbuf_data_room_size(rxq->mb_pool) -
 743                                       RTE_PKTMBUF_HEADROOM);
 744                 if (eth_dev->data->dev_conf.rxmode.max_rx_pkt_len > buf_size)
 745                         return 1;
 746         }
 747         return 0;
 748 }
 749
 750 static eth_rx_burst_t
 751 bnxt_receive_function(__rte_unused struct rte_eth_dev *eth_dev)
 752 {
 753 #ifdef RTE_ARCH_X86
 754 #ifndef RTE_LIBRTE_IEEE1588
 755         /*
 756          * Vector mode receive can be enabled only if scatter rx is not
 757          * in use and rx offloads are limited to VLAN stripping and
 758          * CRC stripping.
 759          */
 760         if (!eth_dev->data->scattered_rx &&
 761             !(eth_dev->data->dev_conf.rxmode.offloads &
 762               ~(DEV_RX_OFFLOAD_VLAN_STRIP |
 763                 DEV_RX_OFFLOAD_KEEP_CRC |
 764                 DEV_RX_OFFLOAD_JUMBO_FRAME |
 765                 DEV_RX_OFFLOAD_IPV4_CKSUM |
 766                 DEV_RX_OFFLOAD_UDP_CKSUM |
 767                 DEV_RX_OFFLOAD_TCP_CKSUM |
 768                 DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM |
 769                 DEV_RX_OFFLOAD_VLAN_FILTER))) {
 770                 PMD_DRV_LOG(INFO, "Using vector mode receive for port %d\n",
 771                             eth_dev->data->port_id);
 772                 return bnxt_recv_pkts_vec;
 773         }
 774         PMD_DRV_LOG(INFO, "Vector mode receive disabled for port %d\n",
 775                     eth_dev->data->port_id);
 776         PMD_DRV_LOG(INFO,
 777                     "Port %d scatter: %d rx offload: %" PRIX64 "\n",
 778                     eth_dev->data->port_id,
 779                     eth_dev->data->scattered_rx,
 780                     eth_dev->data->dev_conf.rxmode.offloads);
 781 #endif
 782 #endif
 783         return bnxt_recv_pkts;
 784 }
 785
 786 static eth_tx_burst_t
 787 bnxt_transmit_function(__rte_unused struct rte_eth_dev *eth_dev)
 788 {
 789 #ifdef RTE_ARCH_X86
 790 #ifndef RTE_LIBRTE_IEEE1588
 791         /*
 792          * Vector mode transmit can be enabled only if not using scatter rx
 793          * or tx offloads.
 794          */
 795         if (!eth_dev->data->scattered_rx &&
 796             !eth_dev->data->dev_conf.txmode.offloads) {
 797                 PMD_DRV_LOG(INFO, "Using vector mode transmit for port %d\n",
 798                             eth_dev->data->port_id);
 799                 return bnxt_xmit_pkts_vec;
 800         }
 801         PMD_DRV_LOG(INFO, "Vector mode transmit disabled for port %d\n",
 802                     eth_dev->data->port_id);
 803         PMD_DRV_LOG(INFO,
 804                     "Port %d scatter: %d tx offload: %" PRIX64 "\n",
 805                     eth_dev->data->port_id,
 806                     eth_dev->data->scattered_rx,
 807                     eth_dev->data->dev_conf.txmode.offloads);
 808 #endif
 809 #endif
 810         return bnxt_xmit_pkts;
 811 }
 812
 813 static int bnxt_handle_if_change_status(struct bnxt *bp)
 814 {
 815         int rc;
 816
 817         /* Since fw has undergone a reset and lost all contexts,
 818          * set fatal flag to not issue hwrm during cleanup
 819          */
 820         bp->flags |= BNXT_FLAG_FATAL_ERROR;
 821         bnxt_uninit_resources(bp, true);
 822
 823         /* clear fatal flag so that re-init happens */
 824         bp->flags &= ~BNXT_FLAG_FATAL_ERROR;
 825         rc = bnxt_init_resources(bp, true);
 826
 827         bp->flags &= ~BNXT_FLAG_IF_CHANGE_HOT_FW_RESET_DONE;
 828
 829         return rc;
 830 }
 831
 832 static int bnxt_dev_start_op(struct rte_eth_dev *eth_dev)
 833 {
 834         struct bnxt *bp = eth_dev->data->dev_private;
 835         uint64_t rx_offloads = eth_dev->data->dev_conf.rxmode.offloads;
 836         int vlan_mask = 0;
 837         int rc;
 838
 839         if (!eth_dev->data->nb_tx_queues || !eth_dev->data->nb_rx_queues) {
 840                 PMD_DRV_LOG(ERR, "Queues are not configured yet!\n");
 841                 return -EINVAL;
 842         }
 843
 844         if (bp->rx_cp_nr_rings > RTE_ETHDEV_QUEUE_STAT_CNTRS) {
 845                 PMD_DRV_LOG(ERR,
 846                         "RxQ cnt %d > CONFIG_RTE_ETHDEV_QUEUE_STAT_CNTRS %d\n",
 847                         bp->rx_cp_nr_rings, RTE_ETHDEV_QUEUE_STAT_CNTRS);
 848         }
 849
 850         rc = bnxt_hwrm_if_change(bp, 1);
 851         if (!rc) {
 852                 if (bp->flags & BNXT_FLAG_IF_CHANGE_HOT_FW_RESET_DONE) {
 853                         rc = bnxt_handle_if_change_status(bp);
 854                         if (rc)
 855                                 return rc;
 856                 }
 857         }
 858         bnxt_enable_int(bp);
 859
 860         rc = bnxt_init_chip(bp);
 861         if (rc)
 862                 goto error;
 863
 864         eth_dev->data->scattered_rx = bnxt_scattered_rx(eth_dev);
 865
 866         bnxt_link_update_op(eth_dev, 1);
 867
 868         if (rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER)
 869                 vlan_mask |= ETH_VLAN_FILTER_MASK;
 870         if (rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
 871                 vlan_mask |= ETH_VLAN_STRIP_MASK;
 872         rc = bnxt_vlan_offload_set_op(eth_dev, vlan_mask);
 873         if (rc)
 874                 goto error;
 875
 876         eth_dev->rx_pkt_burst = bnxt_receive_function(eth_dev);
 877         eth_dev->tx_pkt_burst = bnxt_transmit_function(eth_dev);
 878
 879         bp->flags |= BNXT_FLAG_INIT_DONE;
 880         eth_dev->data->dev_started = 1;
 881         bp->dev_stopped = 0;
 882         pthread_mutex_lock(&bp->def_cp_lock);
 883         bnxt_schedule_fw_health_check(bp);
 884         pthread_mutex_unlock(&bp->def_cp_lock);
 885         return 0;
 886
 887 error:
 888         bnxt_hwrm_if_change(bp, 0);
 889         bnxt_shutdown_nic(bp);
 890         bnxt_free_tx_mbufs(bp);
 891         bnxt_free_rx_mbufs(bp);
 892         return rc;
 893 }
 894
 895 static int bnxt_dev_set_link_up_op(struct rte_eth_dev *eth_dev)
 896 {
 897         struct bnxt *bp = eth_dev->data->dev_private;
 898         int rc = 0;
 899
 900         if (!bp->link_info.link_up)
 901                 rc = bnxt_set_hwrm_link_config(bp, true);
 902         if (!rc)
 903                 eth_dev->data->dev_link.link_status = 1;
 904
 905         bnxt_print_link_info(eth_dev);
 906         return rc;
 907 }
 908
 909 static int bnxt_dev_set_link_down_op(struct rte_eth_dev *eth_dev)
 910 {
 911         struct bnxt *bp = eth_dev->data->dev_private;
 912
 913         eth_dev->data->dev_link.link_status = 0;
 914         bnxt_set_hwrm_link_config(bp, false);
 915         bp->link_info.link_up = 0;
 916
 917         return 0;
 918 }
 919
 920 /* Unload the driver, release resources */
 921 static void bnxt_dev_stop_op(struct rte_eth_dev *eth_dev)
 922 {
 923         struct bnxt *bp = eth_dev->data->dev_private;
 924         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
 925         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
 926
 927         eth_dev->data->dev_started = 0;
 928         /* Prevent crashes when queues are still in use */
 929         eth_dev->rx_pkt_burst = &bnxt_dummy_recv_pkts;
 930         eth_dev->tx_pkt_burst = &bnxt_dummy_xmit_pkts;
 931
 932         bnxt_disable_int(bp);
 933
 934         /* disable uio/vfio intr/eventfd mapping */
 935         rte_intr_disable(intr_handle);
 936
 937         bnxt_cancel_fw_health_check(bp);
 938
 939         bp->flags &= ~BNXT_FLAG_INIT_DONE;
 940         if (bp->eth_dev->data->dev_started) {
 941                 /* TBD: STOP HW queues DMA */
 942                 eth_dev->data->dev_link.link_status = 0;
 943         }
 944         bnxt_dev_set_link_down_op(eth_dev);
 945
 946         /* Wait for link to be reset and the async notification to process.
 947          * During reset recovery, there is no need to wait
 948          */
 949         if (!is_bnxt_in_error(bp))
 950                 rte_delay_ms(BNXT_LINK_WAIT_INTERVAL * 2);
 951
 952         /* Clean queue intr-vector mapping */
 953         rte_intr_efd_disable(intr_handle);
 954         if (intr_handle->intr_vec != NULL) {
 955                 rte_free(intr_handle->intr_vec);
 956                 intr_handle->intr_vec = NULL;
 957         }
 958
 959         bnxt_hwrm_port_clr_stats(bp);
 960         bnxt_free_tx_mbufs(bp);
 961         bnxt_free_rx_mbufs(bp);
 962         /* Process any remaining notifications in default completion queue */
 963         bnxt_int_handler(eth_dev);
 964         bnxt_shutdown_nic(bp);
 965         bnxt_hwrm_if_change(bp, 0);
 966         bp->dev_stopped = 1;
 967 }
 968
 969 static void bnxt_dev_close_op(struct rte_eth_dev *eth_dev)
 970 {
 971         struct bnxt *bp = eth_dev->data->dev_private;
 972
 973         if (bp->dev_stopped == 0)
 974                 bnxt_dev_stop_op(eth_dev);
 975
 976         if (eth_dev->data->mac_addrs != NULL) {
 977                 rte_free(eth_dev->data->mac_addrs);
 978                 eth_dev->data->mac_addrs = NULL;
 979         }
 980         if (bp->grp_info != NULL) {
 981                 rte_free(bp->grp_info);
 982                 bp->grp_info = NULL;
 983         }
 984
 985         bnxt_dev_uninit(eth_dev);
 986 }
 987
 988 static void bnxt_mac_addr_remove_op(struct rte_eth_dev *eth_dev,
 989                                     uint32_t index)
 990 {
 991         struct bnxt *bp = eth_dev->data->dev_private;
 992         uint64_t pool_mask = eth_dev->data->mac_pool_sel[index];
 993         struct bnxt_vnic_info *vnic;
 994         struct bnxt_filter_info *filter, *temp_filter;
 995         uint32_t i;
 996
 997         if (is_bnxt_in_error(bp))
 998                 return;
 999
1000         /*
1001          * Loop through all VNICs from the specified filter flow pools to
1002          * remove the corresponding MAC addr filter
1003          */
1004         for (i = 0; i < bp->nr_vnics; i++) {
1005                 if (!(pool_mask & (1ULL << i)))
1006                         continue;
1007
1008                 vnic = &bp->vnic_info[i];
1009                 filter = STAILQ_FIRST(&vnic->filter);
1010                 while (filter) {
1011                         temp_filter = STAILQ_NEXT(filter, next);
1012                         if (filter->mac_index == index) {
1013                                 STAILQ_REMOVE(&vnic->filter, filter,
1014                                                 bnxt_filter_info, next);
1015                                 bnxt_hwrm_clear_l2_filter(bp, filter);
1016                                 filter->mac_index = INVALID_MAC_INDEX;
1017                                 memset(&filter->l2_addr, 0, RTE_ETHER_ADDR_LEN);
1018                                 STAILQ_INSERT_TAIL(&bp->free_filter_list,
1019                                                    filter, next);
1020                         }
1021                         filter = temp_filter;
1022                 }
1023         }
1024 }
1025
1026 static int bnxt_add_mac_filter(struct bnxt *bp, struct bnxt_vnic_info *vnic,
1027                                struct rte_ether_addr *mac_addr, uint32_t index)
1028 {
1029         struct bnxt_filter_info *filter;
1030         int rc = 0;
1031
1032         filter = STAILQ_FIRST(&vnic->filter);
1033         /* During bnxt_mac_addr_add_op, default MAC is
1034          * already programmed, so skip it. But, when
1035          * hw-vlan-filter is turned OFF from ON, default
1036          * MAC filter should be restored
1037          */
1038         if (index == 0 && filter->dflt)
1039                 return 0;
1040
1041         filter = bnxt_alloc_filter(bp);
1042         if (!filter) {
1043                 PMD_DRV_LOG(ERR, "L2 filter alloc failed\n");
1044                 return -ENODEV;
1045         }
1046
1047         filter->mac_index = index;
1048         /* bnxt_alloc_filter copies default MAC to filter->l2_addr. So,
1049          * if the MAC that's been programmed now is a different one, then,
1050          * copy that addr to filter->l2_addr
1051          */
1052         if (mac_addr)
1053                 memcpy(filter->l2_addr, mac_addr, RTE_ETHER_ADDR_LEN);
1054         filter->flags |= HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_OUTERMOST;
1055
1056         rc = bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id, filter);
1057         if (!rc) {
1058                 if (filter->mac_index == 0) {
1059                         filter->dflt = true;
1060                         STAILQ_INSERT_HEAD(&vnic->filter, filter, next);
1061                 } else {
1062                         STAILQ_INSERT_TAIL(&vnic->filter, filter, next);
1063                 }
1064         } else {
1065                 filter->mac_index = INVALID_MAC_INDEX;
1066                 memset(&filter->l2_addr, 0, RTE_ETHER_ADDR_LEN);
1067                 bnxt_free_filter(bp, filter);
1068         }
1069
1070         return rc;
1071 }
1072
1073 static int bnxt_mac_addr_add_op(struct rte_eth_dev *eth_dev,
1074                                 struct rte_ether_addr *mac_addr,
1075                                 uint32_t index, uint32_t pool)
1076 {
1077         struct bnxt *bp = eth_dev->data->dev_private;
1078         struct bnxt_vnic_info *vnic = &bp->vnic_info[pool];
1079         struct bnxt_filter_info *filter;
1080         int rc = 0;
1081
1082         rc = is_bnxt_in_error(bp);
1083         if (rc)
1084                 return rc;
1085
1086         if (BNXT_VF(bp) & !BNXT_VF_IS_TRUSTED(bp)) {
1087                 PMD_DRV_LOG(ERR, "Cannot add MAC address to a VF interface\n");
1088                 return -ENOTSUP;
1089         }
1090
1091         if (!vnic) {
1092                 PMD_DRV_LOG(ERR, "VNIC not found for pool %d!\n", pool);
1093                 return -EINVAL;
1094         }
1095         /* Attach requested MAC address to the new l2_filter */
1096         STAILQ_FOREACH(filter, &vnic->filter, next) {
1097                 if (filter->mac_index == index) {
1098                         PMD_DRV_LOG(ERR,
1099                                 "MAC addr already existed for pool %d\n", pool);
1100                         return 0;
1101                 }
1102         }
1103
1104         rc = bnxt_add_mac_filter(bp, vnic, mac_addr, index);
1105
1106         return rc;
1107 }
1108
1109 int bnxt_link_update_op(struct rte_eth_dev *eth_dev, int wait_to_complete)
1110 {
1111         int rc = 0;
1112         struct bnxt *bp = eth_dev->data->dev_private;
1113         struct rte_eth_link new;
1114         unsigned int cnt = BNXT_LINK_WAIT_CNT;
1115
1116         rc = is_bnxt_in_error(bp);
1117         if (rc)
1118                 return rc;
1119
1120         memset(&new, 0, sizeof(new));
1121         do {
1122                 /* Retrieve link info from hardware */
1123                 rc = bnxt_get_hwrm_link_config(bp, &new);
1124                 if (rc) {
1125                         new.link_speed = ETH_LINK_SPEED_100M;
1126                         new.link_duplex = ETH_LINK_FULL_DUPLEX;
1127                         PMD_DRV_LOG(ERR,
1128                                 "Failed to retrieve link rc = 0x%x!\n", rc);
1129                         goto out;
1130                 }
1131
1132                 if (!wait_to_complete || new.link_status)
1133                         break;
1134
1135                 rte_delay_ms(BNXT_LINK_WAIT_INTERVAL);
1136         } while (cnt--);
1137
1138 out:
1139         /* Timed out or success */
1140         if (new.link_status != eth_dev->data->dev_link.link_status ||
1141         new.link_speed != eth_dev->data->dev_link.link_speed) {
1142                 rte_eth_linkstatus_set(eth_dev, &new);
1143
1144                 _rte_eth_dev_callback_process(eth_dev,
1145                                               RTE_ETH_EVENT_INTR_LSC,
1146                                               NULL);
1147
1148                 bnxt_print_link_info(eth_dev);
1149         }
1150
1151         return rc;
1152 }
1153
1154 static int bnxt_promiscuous_enable_op(struct rte_eth_dev *eth_dev)
1155 {
1156         struct bnxt *bp = eth_dev->data->dev_private;
1157         struct bnxt_vnic_info *vnic;
1158         uint32_t old_flags;
1159         int rc;
1160
1161         rc = is_bnxt_in_error(bp);
1162         if (rc)
1163                 return rc;
1164
1165         if (bp->vnic_info == NULL)
1166                 return 0;
1167
1168         vnic = BNXT_GET_DEFAULT_VNIC(bp);
1169
1170         old_flags = vnic->flags;
1171         vnic->flags |= BNXT_VNIC_INFO_PROMISC;
1172         rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1173         if (rc != 0)
1174                 vnic->flags = old_flags;
1175
1176         return rc;
1177 }
1178
1179 static int bnxt_promiscuous_disable_op(struct rte_eth_dev *eth_dev)
1180 {
1181         struct bnxt *bp = eth_dev->data->dev_private;
1182         struct bnxt_vnic_info *vnic;
1183         uint32_t old_flags;
1184         int rc;
1185
1186         rc = is_bnxt_in_error(bp);
1187         if (rc)
1188                 return rc;
1189
1190         if (bp->vnic_info == NULL)
1191                 return 0;
1192
1193         vnic = BNXT_GET_DEFAULT_VNIC(bp);
1194
1195         old_flags = vnic->flags;
1196         vnic->flags &= ~BNXT_VNIC_INFO_PROMISC;
1197         rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1198         if (rc != 0)
1199                 vnic->flags = old_flags;
1200
1201         return rc;
1202 }
1203
1204 static int bnxt_allmulticast_enable_op(struct rte_eth_dev *eth_dev)
1205 {
1206         struct bnxt *bp = eth_dev->data->dev_private;
1207         struct bnxt_vnic_info *vnic;
1208         uint32_t old_flags;
1209         int rc;
1210
1211         rc = is_bnxt_in_error(bp);
1212         if (rc)
1213                 return rc;
1214
1215         if (bp->vnic_info == NULL)
1216                 return 0;
1217
1218         vnic = BNXT_GET_DEFAULT_VNIC(bp);
1219
1220         old_flags = vnic->flags;
1221         vnic->flags |= BNXT_VNIC_INFO_ALLMULTI;
1222         rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1223         if (rc != 0)
1224                 vnic->flags = old_flags;
1225
1226         return rc;
1227 }
1228
1229 static int bnxt_allmulticast_disable_op(struct rte_eth_dev *eth_dev)
1230 {
1231         struct bnxt *bp = eth_dev->data->dev_private;
1232         struct bnxt_vnic_info *vnic;
1233         uint32_t old_flags;
1234         int rc;
1235
1236         rc = is_bnxt_in_error(bp);
1237         if (rc)
1238                 return rc;
1239
1240         if (bp->vnic_info == NULL)
1241                 return 0;
1242
1243         vnic = BNXT_GET_DEFAULT_VNIC(bp);
1244
1245         old_flags = vnic->flags;
1246         vnic->flags &= ~BNXT_VNIC_INFO_ALLMULTI;
1247         rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1248         if (rc != 0)
1249                 vnic->flags = old_flags;
1250
1251         return rc;
1252 }
1253
1254 /* Return bnxt_rx_queue pointer corresponding to a given rxq. */
1255 static struct bnxt_rx_queue *bnxt_qid_to_rxq(struct bnxt *bp, uint16_t qid)
1256 {
1257         if (qid >= bp->rx_nr_rings)
1258                 return NULL;
1259
1260         return bp->eth_dev->data->rx_queues[qid];
1261 }
1262
1263 /* Return rxq corresponding to a given rss table ring/group ID. */
1264 static uint16_t bnxt_rss_to_qid(struct bnxt *bp, uint16_t fwr)
1265 {
1266         struct bnxt_rx_queue *rxq;
1267         unsigned int i;
1268
1269         if (!BNXT_HAS_RING_GRPS(bp)) {
1270                 for (i = 0; i < bp->rx_nr_rings; i++) {
1271                         rxq = bp->eth_dev->data->rx_queues[i];
1272                         if (rxq->rx_ring->rx_ring_struct->fw_ring_id == fwr)
1273                                 return rxq->index;
1274                 }
1275         } else {
1276                 for (i = 0; i < bp->rx_nr_rings; i++) {
1277                         if (bp->grp_info[i].fw_grp_id == fwr)
1278                                 return i;
1279                 }
1280         }
1281
1282         return INVALID_HW_RING_ID;
1283 }
1284
1285 static int bnxt_reta_update_op(struct rte_eth_dev *eth_dev,
1286                             struct rte_eth_rss_reta_entry64 *reta_conf,
1287                             uint16_t reta_size)
1288 {
1289         struct bnxt *bp = eth_dev->data->dev_private;
1290         struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
1291         struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
1292         uint16_t tbl_size = bnxt_rss_hash_tbl_size(bp);
1293         uint16_t idx, sft;
1294         int i, rc;
1295
1296         rc = is_bnxt_in_error(bp);
1297         if (rc)
1298                 return rc;
1299
1300         if (!vnic->rss_table)
1301                 return -EINVAL;
1302
1303         if (!(dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG))
1304                 return -EINVAL;
1305
1306         if (reta_size != tbl_size) {
1307                 PMD_DRV_LOG(ERR, "The configured hash table lookup size "
1308                         "(%d) must equal the size supported by the hardware "
1309                         "(%d)\n", reta_size, tbl_size);
1310                 return -EINVAL;
1311         }
1312
1313         for (i = 0; i < reta_size; i++) {
1314                 struct bnxt_rx_queue *rxq;
1315
1316                 idx = i / RTE_RETA_GROUP_SIZE;
1317                 sft = i % RTE_RETA_GROUP_SIZE;
1318
1319                 if (!(reta_conf[idx].mask & (1ULL << sft)))
1320                         continue;
1321
1322                 rxq = bnxt_qid_to_rxq(bp, reta_conf[idx].reta[sft]);
1323                 if (!rxq) {
1324                         PMD_DRV_LOG(ERR, "Invalid ring in reta_conf.\n");
1325                         return -EINVAL;
1326                 }
1327
1328                 if (BNXT_CHIP_THOR(bp)) {
1329                         vnic->rss_table[i * 2] =
1330                                 rxq->rx_ring->rx_ring_struct->fw_ring_id;
1331                         vnic->rss_table[i * 2 + 1] =
1332                                 rxq->cp_ring->cp_ring_struct->fw_ring_id;
1333                 } else {
1334                         vnic->rss_table[i] =
1335                             vnic->fw_grp_ids[reta_conf[idx].reta[sft]];
1336                 }
1337         }
1338
1339         bnxt_hwrm_vnic_rss_cfg(bp, vnic);
1340         return 0;
1341 }
1342
1343 static int bnxt_reta_query_op(struct rte_eth_dev *eth_dev,
1344                               struct rte_eth_rss_reta_entry64 *reta_conf,
1345                               uint16_t reta_size)
1346 {
1347         struct bnxt *bp = eth_dev->data->dev_private;
1348         struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
1349         uint16_t tbl_size = bnxt_rss_hash_tbl_size(bp);
1350         uint16_t idx, sft, i;
1351         int rc;
1352
1353         rc = is_bnxt_in_error(bp);
1354         if (rc)
1355                 return rc;
1356
1357         /* Retrieve from the default VNIC */
1358         if (!vnic)
1359                 return -EINVAL;
1360         if (!vnic->rss_table)
1361                 return -EINVAL;
1362
1363         if (reta_size != tbl_size) {
1364                 PMD_DRV_LOG(ERR, "The configured hash table lookup size "
1365                         "(%d) must equal the size supported by the hardware "
1366                         "(%d)\n", reta_size, tbl_size);
1367                 return -EINVAL;
1368         }
1369
1370         for (idx = 0, i = 0; i < reta_size; i++) {
1371                 idx = i / RTE_RETA_GROUP_SIZE;
1372                 sft = i % RTE_RETA_GROUP_SIZE;
1373
1374                 if (reta_conf[idx].mask & (1ULL << sft)) {
1375                         uint16_t qid;
1376
1377                         if (BNXT_CHIP_THOR(bp))
1378                                 qid = bnxt_rss_to_qid(bp,
1379                                                       vnic->rss_table[i * 2]);
1380                         else
1381                                 qid = bnxt_rss_to_qid(bp, vnic->rss_table[i]);
1382
1383                         if (qid == INVALID_HW_RING_ID) {
1384                                 PMD_DRV_LOG(ERR, "Inv. entry in rss table.\n");
1385                                 return -EINVAL;
1386                         }
1387                         reta_conf[idx].reta[sft] = qid;
1388                 }
1389         }
1390
1391         return 0;
1392 }
1393
1394 static int bnxt_rss_hash_update_op(struct rte_eth_dev *eth_dev,
1395                                    struct rte_eth_rss_conf *rss_conf)
1396 {
1397         struct bnxt *bp = eth_dev->data->dev_private;
1398         struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
1399         struct bnxt_vnic_info *vnic;
1400         int rc;
1401
1402         rc = is_bnxt_in_error(bp);
1403         if (rc)
1404                 return rc;
1405
1406         /*
1407          * If RSS enablement were different than dev_configure,
1408          * then return -EINVAL
1409          */
1410         if (dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG) {
1411                 if (!rss_conf->rss_hf)
1412                         PMD_DRV_LOG(ERR, "Hash type NONE\n");
1413         } else {
1414                 if (rss_conf->rss_hf & BNXT_ETH_RSS_SUPPORT)
1415                         return -EINVAL;
1416         }
1417
1418         bp->flags |= BNXT_FLAG_UPDATE_HASH;
1419         memcpy(&bp->rss_conf, rss_conf, sizeof(*rss_conf));
1420
1421         /* Update the default RSS VNIC(s) */
1422         vnic = &bp->vnic_info[0];
1423         vnic->hash_type = bnxt_rte_to_hwrm_hash_types(rss_conf->rss_hf);
1424
1425         /*
1426          * If hashkey is not specified, use the previously configured
1427          * hashkey
1428          */
1429         if (!rss_conf->rss_key)
1430                 goto rss_config;
1431
1432         if (rss_conf->rss_key_len != HW_HASH_KEY_SIZE) {
1433                 PMD_DRV_LOG(ERR,
1434                             "Invalid hashkey length, should be 16 bytes\n");
1435                 return -EINVAL;
1436         }
1437         memcpy(vnic->rss_hash_key, rss_conf->rss_key, rss_conf->rss_key_len);
1438
1439 rss_config:
1440         bnxt_hwrm_vnic_rss_cfg(bp, vnic);
1441         return 0;
1442 }
1443
1444 static int bnxt_rss_hash_conf_get_op(struct rte_eth_dev *eth_dev,
1445                                      struct rte_eth_rss_conf *rss_conf)
1446 {
1447         struct bnxt *bp = eth_dev->data->dev_private;
1448         struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
1449         int len, rc;
1450         uint32_t hash_types;
1451
1452         rc = is_bnxt_in_error(bp);
1453         if (rc)
1454                 return rc;
1455
1456         /* RSS configuration is the same for all VNICs */
1457         if (vnic && vnic->rss_hash_key) {
1458                 if (rss_conf->rss_key) {
1459                         len = rss_conf->rss_key_len <= HW_HASH_KEY_SIZE ?
1460                               rss_conf->rss_key_len : HW_HASH_KEY_SIZE;
1461                         memcpy(rss_conf->rss_key, vnic->rss_hash_key, len);
1462                 }
1463
1464                 hash_types = vnic->hash_type;
1465                 rss_conf->rss_hf = 0;
1466                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV4) {
1467                         rss_conf->rss_hf |= ETH_RSS_IPV4;
1468                         hash_types &= ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV4;
1469                 }
1470                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV4) {
1471                         rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP;
1472                         hash_types &=
1473                                 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV4;
1474                 }
1475                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV4) {
1476                         rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
1477                         hash_types &=
1478                                 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV4;
1479                 }
1480                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6) {
1481                         rss_conf->rss_hf |= ETH_RSS_IPV6;
1482                         hash_types &= ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6;
1483                 }
1484                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV6) {
1485                         rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV6_TCP;
1486                         hash_types &=
1487                                 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV6;
1488                 }
1489                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV6) {
1490                         rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;
1491                         hash_types &=
1492                                 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV6;
1493                 }
1494                 if (hash_types) {
1495                         PMD_DRV_LOG(ERR,
1496                                 "Unknwon RSS config from firmware (%08x), RSS disabled",
1497                                 vnic->hash_type);
1498                         return -ENOTSUP;
1499                 }
1500         } else {
1501                 rss_conf->rss_hf = 0;
1502         }
1503         return 0;
1504 }
1505
1506 static int bnxt_flow_ctrl_get_op(struct rte_eth_dev *dev,
1507                                struct rte_eth_fc_conf *fc_conf)
1508 {
1509         struct bnxt *bp = dev->data->dev_private;
1510         struct rte_eth_link link_info;
1511         int rc;
1512
1513         rc = is_bnxt_in_error(bp);
1514         if (rc)
1515                 return rc;
1516
1517         rc = bnxt_get_hwrm_link_config(bp, &link_info);
1518         if (rc)
1519                 return rc;
1520
1521         memset(fc_conf, 0, sizeof(*fc_conf));
1522         if (bp->link_info.auto_pause)
1523                 fc_conf->autoneg = 1;
1524         switch (bp->link_info.pause) {
1525         case 0:
1526                 fc_conf->mode = RTE_FC_NONE;
1527                 break;
1528         case HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_TX:
1529                 fc_conf->mode = RTE_FC_TX_PAUSE;
1530                 break;
1531         case HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_RX:
1532                 fc_conf->mode = RTE_FC_RX_PAUSE;
1533                 break;
1534         case (HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_TX |
1535                         HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_RX):
1536                 fc_conf->mode = RTE_FC_FULL;
1537                 break;
1538         }
1539         return 0;
1540 }
1541
1542 static int bnxt_flow_ctrl_set_op(struct rte_eth_dev *dev,
1543                                struct rte_eth_fc_conf *fc_conf)
1544 {
1545         struct bnxt *bp = dev->data->dev_private;
1546         int rc;
1547
1548         rc = is_bnxt_in_error(bp);
1549         if (rc)
1550                 return rc;
1551
1552         if (!BNXT_SINGLE_PF(bp) || BNXT_VF(bp)) {
1553                 PMD_DRV_LOG(ERR, "Flow Control Settings cannot be modified\n");
1554                 return -ENOTSUP;
1555         }
1556
1557         switch (fc_conf->mode) {
1558         case RTE_FC_NONE:
1559                 bp->link_info.auto_pause = 0;
1560                 bp->link_info.force_pause = 0;
1561                 break;
1562         case RTE_FC_RX_PAUSE:
1563                 if (fc_conf->autoneg) {
1564                         bp->link_info.auto_pause =
1565                                         HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_RX;
1566                         bp->link_info.force_pause = 0;
1567                 } else {
1568                         bp->link_info.auto_pause = 0;
1569                         bp->link_info.force_pause =
1570                                         HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_RX;
1571                 }
1572                 break;
1573         case RTE_FC_TX_PAUSE:
1574                 if (fc_conf->autoneg) {
1575                         bp->link_info.auto_pause =
1576                                         HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_TX;
1577                         bp->link_info.force_pause = 0;
1578                 } else {
1579                         bp->link_info.auto_pause = 0;
1580                         bp->link_info.force_pause =
1581                                         HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_TX;
1582                 }
1583                 break;
1584         case RTE_FC_FULL:
1585                 if (fc_conf->autoneg) {
1586                         bp->link_info.auto_pause =
1587                                         HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_TX |
1588                                         HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_RX;
1589                         bp->link_info.force_pause = 0;
1590                 } else {
1591                         bp->link_info.auto_pause = 0;
1592                         bp->link_info.force_pause =
1593                                         HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_TX |
1594                                         HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_RX;
1595                 }
1596                 break;
1597         }
1598         return bnxt_set_hwrm_link_config(bp, true);
1599 }
1600
1601 /* Add UDP tunneling port */
1602 static int
1603 bnxt_udp_tunnel_port_add_op(struct rte_eth_dev *eth_dev,
1604                          struct rte_eth_udp_tunnel *udp_tunnel)
1605 {
1606         struct bnxt *bp = eth_dev->data->dev_private;
1607         uint16_t tunnel_type = 0;
1608         int rc = 0;
1609
1610         rc = is_bnxt_in_error(bp);
1611         if (rc)
1612                 return rc;
1613
1614         switch (udp_tunnel->prot_type) {
1615         case RTE_TUNNEL_TYPE_VXLAN:
1616                 if (bp->vxlan_port_cnt) {
1617                         PMD_DRV_LOG(ERR, "Tunnel Port %d already programmed\n",
1618                                 udp_tunnel->udp_port);
1619                         if (bp->vxlan_port != udp_tunnel->udp_port) {
1620                                 PMD_DRV_LOG(ERR, "Only one port allowed\n");
1621                                 return -ENOSPC;
1622                         }
1623                         bp->vxlan_port_cnt++;
1624                         return 0;
1625                 }
1626                 tunnel_type =
1627                         HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_VXLAN;
1628                 bp->vxlan_port_cnt++;
1629                 break;
1630         case RTE_TUNNEL_TYPE_GENEVE:
1631                 if (bp->geneve_port_cnt) {
1632                         PMD_DRV_LOG(ERR, "Tunnel Port %d already programmed\n",
1633                                 udp_tunnel->udp_port);
1634                         if (bp->geneve_port != udp_tunnel->udp_port) {
1635                                 PMD_DRV_LOG(ERR, "Only one port allowed\n");
1636                                 return -ENOSPC;
1637                         }
1638                         bp->geneve_port_cnt++;
1639                         return 0;
1640                 }
1641                 tunnel_type =
1642                         HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_GENEVE;
1643                 bp->geneve_port_cnt++;
1644                 break;
1645         default:
1646                 PMD_DRV_LOG(ERR, "Tunnel type is not supported\n");
1647                 return -ENOTSUP;
1648         }
1649         rc = bnxt_hwrm_tunnel_dst_port_alloc(bp, udp_tunnel->udp_port,
1650                                              tunnel_type);
1651         return rc;
1652 }
1653
1654 static int
1655 bnxt_udp_tunnel_port_del_op(struct rte_eth_dev *eth_dev,
1656                          struct rte_eth_udp_tunnel *udp_tunnel)
1657 {
1658         struct bnxt *bp = eth_dev->data->dev_private;
1659         uint16_t tunnel_type = 0;
1660         uint16_t port = 0;
1661         int rc = 0;
1662
1663         rc = is_bnxt_in_error(bp);
1664         if (rc)
1665                 return rc;
1666
1667         switch (udp_tunnel->prot_type) {
1668         case RTE_TUNNEL_TYPE_VXLAN:
1669                 if (!bp->vxlan_port_cnt) {
1670                         PMD_DRV_LOG(ERR, "No Tunnel port configured yet\n");
1671                         return -EINVAL;
1672                 }
1673                 if (bp->vxlan_port != udp_tunnel->udp_port) {
1674                         PMD_DRV_LOG(ERR, "Req Port: %d. Configured port: %d\n",
1675                                 udp_tunnel->udp_port, bp->vxlan_port);
1676                         return -EINVAL;
1677                 }
1678                 if (--bp->vxlan_port_cnt)
1679                         return 0;
1680
1681                 tunnel_type =
1682                         HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN;
1683                 port = bp->vxlan_fw_dst_port_id;
1684                 break;
1685         case RTE_TUNNEL_TYPE_GENEVE:
1686                 if (!bp->geneve_port_cnt) {
1687                         PMD_DRV_LOG(ERR, "No Tunnel port configured yet\n");
1688                         return -EINVAL;
1689                 }
1690                 if (bp->geneve_port != udp_tunnel->udp_port) {
1691                         PMD_DRV_LOG(ERR, "Req Port: %d. Configured port: %d\n",
1692                                 udp_tunnel->udp_port, bp->geneve_port);
1693                         return -EINVAL;
1694                 }
1695                 if (--bp->geneve_port_cnt)
1696                         return 0;
1697
1698                 tunnel_type =
1699                         HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_GENEVE;
1700                 port = bp->geneve_fw_dst_port_id;
1701                 break;
1702         default:
1703                 PMD_DRV_LOG(ERR, "Tunnel type is not supported\n");
1704                 return -ENOTSUP;
1705         }
1706
1707         rc = bnxt_hwrm_tunnel_dst_port_free(bp, port, tunnel_type);
1708         if (!rc) {
1709                 if (tunnel_type ==
1710                     HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN)
1711                         bp->vxlan_port = 0;
1712                 if (tunnel_type ==
1713                     HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_GENEVE)
1714                         bp->geneve_port = 0;
1715         }
1716         return rc;
1717 }
1718
1719 static int bnxt_del_vlan_filter(struct bnxt *bp, uint16_t vlan_id)
1720 {
1721         struct bnxt_filter_info *filter;
1722         struct bnxt_vnic_info *vnic;
1723         int rc = 0;
1724         uint32_t chk = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN;
1725
1726         /* if VLAN exists && VLAN matches vlan_id
1727          *      remove the MAC+VLAN filter
1728          *      add a new MAC only filter
1729          * else
1730          *      VLAN filter doesn't exist, just skip and continue
1731          */
1732         vnic = BNXT_GET_DEFAULT_VNIC(bp);
1733         filter = STAILQ_FIRST(&vnic->filter);
1734         while (filter) {
1735                 /* Search for this matching MAC+VLAN filter */
1736                 if ((filter->enables & chk) &&
1737                     (filter->l2_ivlan == vlan_id &&
1738                      filter->l2_ivlan_mask != 0) &&
1739                     !memcmp(filter->l2_addr, bp->mac_addr,
1740                             RTE_ETHER_ADDR_LEN)) {
1741                         /* Delete the filter */
1742                         rc = bnxt_hwrm_clear_l2_filter(bp, filter);
1743                         if (rc)
1744                                 return rc;
1745                         STAILQ_REMOVE(&vnic->filter, filter,
1746                                       bnxt_filter_info, next);
1747                         STAILQ_INSERT_TAIL(&bp->free_filter_list, filter, next);
1748
1749                         PMD_DRV_LOG(INFO,
1750                                     "Del Vlan filter for %d\n",
1751                                     vlan_id);
1752                         return rc;
1753                 }
1754                 filter = STAILQ_NEXT(filter, next);
1755         }
1756         return -ENOENT;
1757 }
1758
1759 static int bnxt_add_vlan_filter(struct bnxt *bp, uint16_t vlan_id)
1760 {
1761         struct bnxt_filter_info *filter;
1762         struct bnxt_vnic_info *vnic;
1763         int rc = 0;
1764         uint32_t en = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN |
1765                 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN_MASK;
1766         uint32_t chk = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN;
1767
1768         /* Implementation notes on the use of VNIC in this command:
1769          *
1770          * By default, these filters belong to default vnic for the function.
1771          * Once these filters are set up, only destination VNIC can be modified.
1772          * If the destination VNIC is not specified in this command,
1773          * then the HWRM shall only create an l2 context id.
1774          */
1775
1776         vnic = BNXT_GET_DEFAULT_VNIC(bp);
1777         filter = STAILQ_FIRST(&vnic->filter);
1778         /* Check if the VLAN has already been added */
1779         while (filter) {
1780                 if ((filter->enables & chk) &&
1781                     (filter->l2_ivlan == vlan_id &&
1782                      filter->l2_ivlan_mask == 0x0FFF) &&
1783                      !memcmp(filter->l2_addr, bp->mac_addr,
1784                              RTE_ETHER_ADDR_LEN))
1785                         return -EEXIST;
1786
1787                 filter = STAILQ_NEXT(filter, next);
1788         }
1789
1790         /* No match found. Alloc a fresh filter and issue the L2_FILTER_ALLOC
1791          * command to create MAC+VLAN filter with the right flags, enables set.
1792          */
1793         filter = bnxt_alloc_filter(bp);
1794         if (!filter) {
1795                 PMD_DRV_LOG(ERR,
1796                             "MAC/VLAN filter alloc failed\n");
1797                 return -ENOMEM;
1798         }
1799         /* MAC + VLAN ID filter */
1800         /* If l2_ivlan == 0 and l2_ivlan_mask != 0, only
1801          * untagged packets are received
1802          *
1803          * If l2_ivlan != 0 and l2_ivlan_mask != 0, untagged
1804          * packets and only the programmed vlan's packets are received
1805          */
1806         filter->l2_ivlan = vlan_id;
1807         filter->l2_ivlan_mask = 0x0FFF;
1808         filter->enables |= en;
1809         filter->flags |= HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_OUTERMOST;
1810
1811         rc = bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id, filter);
1812         if (rc) {
1813                 /* Free the newly allocated filter as we were
1814                  * not able to create the filter in hardware.
1815                  */
1816                 filter->fw_l2_filter_id = UINT64_MAX;
1817                 STAILQ_INSERT_TAIL(&bp->free_filter_list, filter, next);
1818                 return rc;
1819         } else {
1820                 /* Add this new filter to the list */
1821                 if (vlan_id == 0) {
1822                         filter->dflt = true;
1823                         STAILQ_INSERT_HEAD(&vnic->filter, filter, next);
1824                 } else {
1825                         STAILQ_INSERT_TAIL(&vnic->filter, filter, next);
1826                 }
1827         }
1828
1829         PMD_DRV_LOG(INFO,
1830                     "Added Vlan filter for %d\n", vlan_id);
1831         return rc;
1832 }
1833
1834 static int bnxt_vlan_filter_set_op(struct rte_eth_dev *eth_dev,
1835                 uint16_t vlan_id, int on)
1836 {
1837         struct bnxt *bp = eth_dev->data->dev_private;
1838         int rc;
1839
1840         rc = is_bnxt_in_error(bp);
1841         if (rc)
1842                 return rc;
1843
1844         /* These operations apply to ALL existing MAC/VLAN filters */
1845         if (on)
1846                 return bnxt_add_vlan_filter(bp, vlan_id);
1847         else
1848                 return bnxt_del_vlan_filter(bp, vlan_id);
1849 }
1850
1851 static int bnxt_del_dflt_mac_filter(struct bnxt *bp,
1852                                     struct bnxt_vnic_info *vnic)
1853 {
1854         struct bnxt_filter_info *filter;
1855         int rc;
1856
1857         filter = STAILQ_FIRST(&vnic->filter);
1858         while (filter) {
1859                 if (filter->dflt &&
1860                     !memcmp(filter->l2_addr, bp->mac_addr,
1861                             RTE_ETHER_ADDR_LEN)) {
1862                         rc = bnxt_hwrm_clear_l2_filter(bp, filter);
1863                         if (rc)
1864                                 return rc;
1865                         filter->dflt = false;
1866                         STAILQ_REMOVE(&vnic->filter, filter,
1867                                       bnxt_filter_info, next);
1868                         STAILQ_INSERT_TAIL(&bp->free_filter_list,
1869                                            filter, next);
1870                         filter->fw_l2_filter_id = -1;
1871                         break;
1872                 }
1873                 filter = STAILQ_NEXT(filter, next);
1874         }
1875         return 0;
1876 }
1877
1878 static int
1879 bnxt_vlan_offload_set_op(struct rte_eth_dev *dev, int mask)
1880 {
1881         struct bnxt *bp = dev->data->dev_private;
1882         uint64_t rx_offloads = dev->data->dev_conf.rxmode.offloads;
1883         struct bnxt_vnic_info *vnic;
1884         unsigned int i;
1885         int rc;
1886
1887         rc = is_bnxt_in_error(bp);
1888         if (rc)
1889                 return rc;
1890
1891         vnic = BNXT_GET_DEFAULT_VNIC(bp);
1892         if (!(rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER)) {
1893                 /* Remove any VLAN filters programmed */
1894                 for (i = 0; i < 4095; i++)
1895                         bnxt_del_vlan_filter(bp, i);
1896
1897                 rc = bnxt_add_mac_filter(bp, vnic, NULL, 0);
1898                 if (rc)
1899                         return rc;
1900         } else {
1901                 /* Default filter will allow packets that match the
1902                  * dest mac. So, it has to be deleted, otherwise, we
1903                  * will endup receiving vlan packets for which the
1904                  * filter is not programmed, when hw-vlan-filter
1905                  * configuration is ON
1906                  */
1907                 bnxt_del_dflt_mac_filter(bp, vnic);
1908                 /* This filter will allow only untagged packets */
1909                 bnxt_add_vlan_filter(bp, 0);
1910         }
1911         PMD_DRV_LOG(DEBUG, "VLAN Filtering: %d\n",
1912                     !!(rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER));
1913
1914         if (mask & ETH_VLAN_STRIP_MASK) {
1915                 /* Enable or disable VLAN stripping */
1916                 for (i = 0; i < bp->nr_vnics; i++) {
1917                         struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
1918                         if (rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
1919                                 vnic->vlan_strip = true;
1920                         else
1921                                 vnic->vlan_strip = false;
1922                         bnxt_hwrm_vnic_cfg(bp, vnic);
1923                 }
1924                 PMD_DRV_LOG(DEBUG, "VLAN Strip Offload: %d\n",
1925                         !!(rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP));
1926         }
1927
1928         if (mask & ETH_VLAN_EXTEND_MASK) {
1929                 if (rx_offloads & DEV_RX_OFFLOAD_VLAN_EXTEND)
1930                         PMD_DRV_LOG(DEBUG, "Extend VLAN supported\n");
1931                 else
1932                         PMD_DRV_LOG(INFO, "Extend VLAN unsupported\n");
1933         }
1934
1935         return 0;
1936 }
1937
1938 static int
1939 bnxt_vlan_tpid_set_op(struct rte_eth_dev *dev, enum rte_vlan_type vlan_type,
1940                       uint16_t tpid)
1941 {
1942         struct bnxt *bp = dev->data->dev_private;
1943         int qinq = dev->data->dev_conf.rxmode.offloads &
1944                    DEV_RX_OFFLOAD_VLAN_EXTEND;
1945
1946         if (vlan_type != ETH_VLAN_TYPE_INNER &&
1947             vlan_type != ETH_VLAN_TYPE_OUTER) {
1948                 PMD_DRV_LOG(ERR,
1949                             "Unsupported vlan type.");
1950                 return -EINVAL;
1951         }
1952         if (!qinq) {
1953                 PMD_DRV_LOG(ERR,
1954                             "QinQ not enabled. Needs to be ON as we can "
1955                             "accelerate only outer vlan\n");
1956                 return -EINVAL;
1957         }
1958
1959         if (vlan_type == ETH_VLAN_TYPE_OUTER) {
1960                 switch (tpid) {
1961                 case RTE_ETHER_TYPE_QINQ:
1962                         bp->outer_tpid_bd =
1963                                 TX_BD_LONG_CFA_META_VLAN_TPID_TPID88A8;
1964                                 break;
1965                 case RTE_ETHER_TYPE_VLAN:
1966                         bp->outer_tpid_bd =
1967                                 TX_BD_LONG_CFA_META_VLAN_TPID_TPID8100;
1968                                 break;
1969                 case 0x9100:
1970                         bp->outer_tpid_bd =
1971                                 TX_BD_LONG_CFA_META_VLAN_TPID_TPID9100;
1972                                 break;
1973                 case 0x9200:
1974                         bp->outer_tpid_bd =
1975                                 TX_BD_LONG_CFA_META_VLAN_TPID_TPID9200;
1976                                 break;
1977                 case 0x9300:
1978                         bp->outer_tpid_bd =
1979                                  TX_BD_LONG_CFA_META_VLAN_TPID_TPID9300;
1980                                 break;
1981                 default:
1982                         PMD_DRV_LOG(ERR, "Invalid TPID: %x\n", tpid);
1983                         return -EINVAL;
1984                 }
1985                 bp->outer_tpid_bd |= tpid;
1986                 PMD_DRV_LOG(INFO, "outer_tpid_bd = %x\n", bp->outer_tpid_bd);
1987         } else if (vlan_type == ETH_VLAN_TYPE_INNER) {
1988                 PMD_DRV_LOG(ERR,
1989                             "Can accelerate only outer vlan in QinQ\n");
1990                 return -EINVAL;
1991         }
1992
1993         return 0;
1994 }
1995
1996 static int
1997 bnxt_set_default_mac_addr_op(struct rte_eth_dev *dev,
1998                              struct rte_ether_addr *addr)
1999 {
2000         struct bnxt *bp = dev->data->dev_private;
2001         /* Default Filter is tied to VNIC 0 */
2002         struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
2003         struct bnxt_filter_info *filter;
2004         int rc;
2005
2006         rc = is_bnxt_in_error(bp);
2007         if (rc)
2008                 return rc;
2009
2010         if (BNXT_VF(bp) && !BNXT_VF_IS_TRUSTED(bp))
2011                 return -EPERM;
2012
2013         if (rte_is_zero_ether_addr(addr))
2014                 return -EINVAL;
2015
2016         STAILQ_FOREACH(filter, &vnic->filter, next) {
2017                 /* Default Filter is at Index 0 */
2018                 if (filter->mac_index != 0)
2019                         continue;
2020
2021                 memcpy(filter->l2_addr, addr, RTE_ETHER_ADDR_LEN);
2022                 memset(filter->l2_addr_mask, 0xff, RTE_ETHER_ADDR_LEN);
2023                 filter->flags |= HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_PATH_RX |
2024                         HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_OUTERMOST;
2025                 filter->enables |=
2026                         HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR |
2027                         HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR_MASK;
2028
2029                 rc = bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id, filter);
2030                 if (rc) {
2031                         memcpy(filter->l2_addr, bp->mac_addr,
2032                                RTE_ETHER_ADDR_LEN);
2033                         return rc;
2034                 }
2035
2036                 memcpy(bp->mac_addr, addr, RTE_ETHER_ADDR_LEN);
2037                 PMD_DRV_LOG(DEBUG, "Set MAC addr\n");
2038                 return 0;
2039         }
2040
2041         return 0;
2042 }
2043
2044 static int
2045 bnxt_dev_set_mc_addr_list_op(struct rte_eth_dev *eth_dev,
2046                           struct rte_ether_addr *mc_addr_set,
2047                           uint32_t nb_mc_addr)
2048 {
2049         struct bnxt *bp = eth_dev->data->dev_private;
2050         char *mc_addr_list = (char *)mc_addr_set;
2051         struct bnxt_vnic_info *vnic;
2052         uint32_t off = 0, i = 0;
2053         int rc;
2054
2055         rc = is_bnxt_in_error(bp);
2056         if (rc)
2057                 return rc;
2058
2059         vnic = BNXT_GET_DEFAULT_VNIC(bp);
2060
2061         if (nb_mc_addr > BNXT_MAX_MC_ADDRS) {
2062                 vnic->flags |= BNXT_VNIC_INFO_ALLMULTI;
2063                 goto allmulti;
2064         }
2065
2066         /* TODO Check for Duplicate mcast addresses */
2067         vnic->flags &= ~BNXT_VNIC_INFO_ALLMULTI;
2068         for (i = 0; i < nb_mc_addr; i++) {
2069                 memcpy(vnic->mc_list + off, &mc_addr_list[i],
2070                         RTE_ETHER_ADDR_LEN);
2071                 off += RTE_ETHER_ADDR_LEN;
2072         }
2073
2074         vnic->mc_addr_cnt = i;
2075         if (vnic->mc_addr_cnt)
2076                 vnic->flags |= BNXT_VNIC_INFO_MCAST;
2077         else
2078                 vnic->flags &= ~BNXT_VNIC_INFO_MCAST;
2079
2080 allmulti:
2081         return bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
2082 }
2083
2084 static int
2085 bnxt_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size)
2086 {
2087         struct bnxt *bp = dev->data->dev_private;
2088         uint8_t fw_major = (bp->fw_ver >> 24) & 0xff;
2089         uint8_t fw_minor = (bp->fw_ver >> 16) & 0xff;
2090         uint8_t fw_updt = (bp->fw_ver >> 8) & 0xff;
2091         int ret;
2092
2093         ret = snprintf(fw_version, fw_size, "%d.%d.%d",
2094                         fw_major, fw_minor, fw_updt);
2095
2096         ret += 1; /* add the size of '\0' */
2097         if (fw_size < (uint32_t)ret)
2098                 return ret;
2099         else
2100                 return 0;
2101 }
2102
2103 static void
2104 bnxt_rxq_info_get_op(struct rte_eth_dev *dev, uint16_t queue_id,
2105         struct rte_eth_rxq_info *qinfo)
2106 {
2107         struct bnxt_rx_queue *rxq;
2108
2109         rxq = dev->data->rx_queues[queue_id];
2110
2111         qinfo->mp = rxq->mb_pool;
2112         qinfo->scattered_rx = dev->data->scattered_rx;
2113         qinfo->nb_desc = rxq->nb_rx_desc;
2114
2115         qinfo->conf.rx_free_thresh = rxq->rx_free_thresh;
2116         qinfo->conf.rx_drop_en = 0;
2117         qinfo->conf.rx_deferred_start = rxq->rx_deferred_start;
2118 }
2119
2120 static void
2121 bnxt_txq_info_get_op(struct rte_eth_dev *dev, uint16_t queue_id,
2122         struct rte_eth_txq_info *qinfo)
2123 {
2124         struct bnxt_tx_queue *txq;
2125
2126         txq = dev->data->tx_queues[queue_id];
2127
2128         qinfo->nb_desc = txq->nb_tx_desc;
2129
2130         qinfo->conf.tx_thresh.pthresh = txq->pthresh;
2131         qinfo->conf.tx_thresh.hthresh = txq->hthresh;
2132         qinfo->conf.tx_thresh.wthresh = txq->wthresh;
2133
2134         qinfo->conf.tx_free_thresh = txq->tx_free_thresh;
2135         qinfo->conf.tx_rs_thresh = 0;
2136         qinfo->conf.tx_deferred_start = txq->tx_deferred_start;
2137 }
2138
2139 int bnxt_mtu_set_op(struct rte_eth_dev *eth_dev, uint16_t new_mtu)
2140 {
2141         struct bnxt *bp = eth_dev->data->dev_private;
2142         uint32_t new_pkt_size;
2143         uint32_t rc = 0;
2144         uint32_t i;
2145
2146         rc = is_bnxt_in_error(bp);
2147         if (rc)
2148                 return rc;
2149
2150         /* Exit if receive queues are not configured yet */
2151         if (!eth_dev->data->nb_rx_queues)
2152                 return rc;
2153
2154         new_pkt_size = new_mtu + RTE_ETHER_HDR_LEN + RTE_ETHER_CRC_LEN +
2155                        VLAN_TAG_SIZE * BNXT_NUM_VLANS;
2156
2157 #ifdef RTE_ARCH_X86
2158         /*
2159          * If vector-mode tx/rx is active, disallow any MTU change that would
2160          * require scattered receive support.
2161          */
2162         if (eth_dev->data->dev_started &&
2163             (eth_dev->rx_pkt_burst == bnxt_recv_pkts_vec ||
2164              eth_dev->tx_pkt_burst == bnxt_xmit_pkts_vec) &&
2165             (new_pkt_size >
2166              eth_dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM)) {
2167                 PMD_DRV_LOG(ERR,
2168                             "MTU change would require scattered rx support. ");
2169                 PMD_DRV_LOG(ERR, "Stop port before changing MTU.\n");
2170                 return -EINVAL;
2171         }
2172 #endif
2173
2174         if (new_mtu > RTE_ETHER_MTU) {
2175                 bp->flags |= BNXT_FLAG_JUMBO;
2176                 bp->eth_dev->data->dev_conf.rxmode.offloads |=
2177                         DEV_RX_OFFLOAD_JUMBO_FRAME;
2178         } else {
2179                 bp->eth_dev->data->dev_conf.rxmode.offloads &=
2180                         ~DEV_RX_OFFLOAD_JUMBO_FRAME;
2181                 bp->flags &= ~BNXT_FLAG_JUMBO;
2182         }
2183
2184         /* Is there a change in mtu setting? */
2185         if (eth_dev->data->dev_conf.rxmode.max_rx_pkt_len == new_pkt_size)
2186                 return rc;
2187
2188         for (i = 0; i < bp->nr_vnics; i++) {
2189                 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
2190                 uint16_t size = 0;
2191
2192                 vnic->mru = BNXT_VNIC_MRU(new_mtu);
2193                 rc = bnxt_hwrm_vnic_cfg(bp, vnic);
2194                 if (rc)
2195                         break;
2196
2197                 size = rte_pktmbuf_data_room_size(bp->rx_queues[0]->mb_pool);
2198                 size -= RTE_PKTMBUF_HEADROOM;
2199
2200                 if (size < new_mtu) {
2201                         rc = bnxt_hwrm_vnic_plcmode_cfg(bp, vnic);
2202                         if (rc)
2203                                 return rc;
2204                 }
2205         }
2206
2207         if (!rc)
2208                 eth_dev->data->dev_conf.rxmode.max_rx_pkt_len = new_pkt_size;
2209
2210         PMD_DRV_LOG(INFO, "New MTU is %d\n", new_mtu);
2211
2212         return rc;
2213 }
2214
2215 static int
2216 bnxt_vlan_pvid_set_op(struct rte_eth_dev *dev, uint16_t pvid, int on)
2217 {
2218         struct bnxt *bp = dev->data->dev_private;
2219         uint16_t vlan = bp->vlan;
2220         int rc;
2221
2222         rc = is_bnxt_in_error(bp);
2223         if (rc)
2224                 return rc;
2225
2226         if (!BNXT_SINGLE_PF(bp) || BNXT_VF(bp)) {
2227                 PMD_DRV_LOG(ERR,
2228                         "PVID cannot be modified for this function\n");
2229                 return -ENOTSUP;
2230         }
2231         bp->vlan = on ? pvid : 0;
2232
2233         rc = bnxt_hwrm_set_default_vlan(bp, 0, 0);
2234         if (rc)
2235                 bp->vlan = vlan;
2236         return rc;
2237 }
2238
2239 static int
2240 bnxt_dev_led_on_op(struct rte_eth_dev *dev)
2241 {
2242         struct bnxt *bp = dev->data->dev_private;
2243         int rc;
2244
2245         rc = is_bnxt_in_error(bp);
2246         if (rc)
2247                 return rc;
2248
2249         return bnxt_hwrm_port_led_cfg(bp, true);
2250 }
2251
2252 static int
2253 bnxt_dev_led_off_op(struct rte_eth_dev *dev)
2254 {
2255         struct bnxt *bp = dev->data->dev_private;
2256         int rc;
2257
2258         rc = is_bnxt_in_error(bp);
2259         if (rc)
2260                 return rc;
2261
2262         return bnxt_hwrm_port_led_cfg(bp, false);
2263 }
2264
2265 static uint32_t
2266 bnxt_rx_queue_count_op(struct rte_eth_dev *dev, uint16_t rx_queue_id)
2267 {
2268         struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
2269         uint32_t desc = 0, raw_cons = 0, cons;
2270         struct bnxt_cp_ring_info *cpr;
2271         struct bnxt_rx_queue *rxq;
2272         struct rx_pkt_cmpl *rxcmp;
2273         int rc;
2274
2275         rc = is_bnxt_in_error(bp);
2276         if (rc)
2277                 return rc;
2278
2279         rxq = dev->data->rx_queues[rx_queue_id];
2280         cpr = rxq->cp_ring;
2281         raw_cons = cpr->cp_raw_cons;
2282
2283         while (1) {
2284                 cons = RING_CMP(cpr->cp_ring_struct, raw_cons);
2285                 rte_prefetch0(&cpr->cp_desc_ring[cons]);
2286                 rxcmp = (struct rx_pkt_cmpl *)&cpr->cp_desc_ring[cons];
2287
2288                 if (!CMP_VALID(rxcmp, raw_cons, cpr->cp_ring_struct)) {
2289                         break;
2290                 } else {
2291                         raw_cons++;
2292                         desc++;
2293                 }
2294         }
2295
2296         return desc;
2297 }
2298
2299 static int
2300 bnxt_rx_descriptor_status_op(void *rx_queue, uint16_t offset)
2301 {
2302         struct bnxt_rx_queue *rxq = (struct bnxt_rx_queue *)rx_queue;
2303         struct bnxt_rx_ring_info *rxr;
2304         struct bnxt_cp_ring_info *cpr;
2305         struct bnxt_sw_rx_bd *rx_buf;
2306         struct rx_pkt_cmpl *rxcmp;
2307         uint32_t cons, cp_cons;
2308         int rc;
2309
2310         if (!rxq)
2311                 return -EINVAL;
2312
2313         rc = is_bnxt_in_error(rxq->bp);
2314         if (rc)
2315                 return rc;
2316
2317         cpr = rxq->cp_ring;
2318         rxr = rxq->rx_ring;
2319
2320         if (offset >= rxq->nb_rx_desc)
2321                 return -EINVAL;
2322
2323         cons = RING_CMP(cpr->cp_ring_struct, offset);
2324         cp_cons = cpr->cp_raw_cons;
2325         rxcmp = (struct rx_pkt_cmpl *)&cpr->cp_desc_ring[cons];
2326
2327         if (cons > cp_cons) {
2328                 if (CMPL_VALID(rxcmp, cpr->valid))
2329                         return RTE_ETH_RX_DESC_DONE;
2330         } else {
2331                 if (CMPL_VALID(rxcmp, !cpr->valid))
2332                         return RTE_ETH_RX_DESC_DONE;
2333         }
2334         rx_buf = &rxr->rx_buf_ring[cons];
2335         if (rx_buf->mbuf == NULL)
2336                 return RTE_ETH_RX_DESC_UNAVAIL;
2337
2338
2339         return RTE_ETH_RX_DESC_AVAIL;
2340 }
2341
2342 static int
2343 bnxt_tx_descriptor_status_op(void *tx_queue, uint16_t offset)
2344 {
2345         struct bnxt_tx_queue *txq = (struct bnxt_tx_queue *)tx_queue;
2346         struct bnxt_tx_ring_info *txr;
2347         struct bnxt_cp_ring_info *cpr;
2348         struct bnxt_sw_tx_bd *tx_buf;
2349         struct tx_pkt_cmpl *txcmp;
2350         uint32_t cons, cp_cons;
2351         int rc;
2352
2353         if (!txq)
2354                 return -EINVAL;
2355
2356         rc = is_bnxt_in_error(txq->bp);
2357         if (rc)
2358                 return rc;
2359
2360         cpr = txq->cp_ring;
2361         txr = txq->tx_ring;
2362
2363         if (offset >= txq->nb_tx_desc)
2364                 return -EINVAL;
2365
2366         cons = RING_CMP(cpr->cp_ring_struct, offset);
2367         txcmp = (struct tx_pkt_cmpl *)&cpr->cp_desc_ring[cons];
2368         cp_cons = cpr->cp_raw_cons;
2369
2370         if (cons > cp_cons) {
2371                 if (CMPL_VALID(txcmp, cpr->valid))
2372                         return RTE_ETH_TX_DESC_UNAVAIL;
2373         } else {
2374                 if (CMPL_VALID(txcmp, !cpr->valid))
2375                         return RTE_ETH_TX_DESC_UNAVAIL;
2376         }
2377         tx_buf = &txr->tx_buf_ring[cons];
2378         if (tx_buf->mbuf == NULL)
2379                 return RTE_ETH_TX_DESC_DONE;
2380
2381         return RTE_ETH_TX_DESC_FULL;
2382 }
2383
2384 static struct bnxt_filter_info *
2385 bnxt_match_and_validate_ether_filter(struct bnxt *bp,
2386                                 struct rte_eth_ethertype_filter *efilter,
2387                                 struct bnxt_vnic_info *vnic0,
2388                                 struct bnxt_vnic_info *vnic,
2389                                 int *ret)
2390 {
2391         struct bnxt_filter_info *mfilter = NULL;
2392         int match = 0;
2393         *ret = 0;
2394
2395         if (efilter->ether_type == RTE_ETHER_TYPE_IPV4 ||
2396                 efilter->ether_type == RTE_ETHER_TYPE_IPV6) {
2397                 PMD_DRV_LOG(ERR, "invalid ether_type(0x%04x) in"
2398                         " ethertype filter.", efilter->ether_type);
2399                 *ret = -EINVAL;
2400                 goto exit;
2401         }
2402         if (efilter->queue >= bp->rx_nr_rings) {
2403                 PMD_DRV_LOG(ERR, "Invalid queue %d\n", efilter->queue);
2404                 *ret = -EINVAL;
2405                 goto exit;
2406         }
2407
2408         vnic0 = &bp->vnic_info[0];
2409         vnic = &bp->vnic_info[efilter->queue];
2410         if (vnic == NULL) {
2411                 PMD_DRV_LOG(ERR, "Invalid queue %d\n", efilter->queue);
2412                 *ret = -EINVAL;
2413                 goto exit;
2414         }
2415
2416         if (efilter->flags & RTE_ETHTYPE_FLAGS_DROP) {
2417                 STAILQ_FOREACH(mfilter, &vnic0->filter, next) {
2418                         if ((!memcmp(efilter->mac_addr.addr_bytes,
2419                                      mfilter->l2_addr, RTE_ETHER_ADDR_LEN) &&
2420                              mfilter->flags ==
2421                              HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_DROP &&
2422                              mfilter->ethertype == efilter->ether_type)) {
2423                                 match = 1;
2424                                 break;
2425                         }
2426                 }
2427         } else {
2428                 STAILQ_FOREACH(mfilter, &vnic->filter, next)
2429                         if ((!memcmp(efilter->mac_addr.addr_bytes,
2430                                      mfilter->l2_addr, RTE_ETHER_ADDR_LEN) &&
2431                              mfilter->ethertype == efilter->ether_type &&
2432                              mfilter->flags ==
2433                              HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_PATH_RX)) {
2434                                 match = 1;
2435                                 break;
2436                         }
2437         }
2438
2439         if (match)
2440                 *ret = -EEXIST;
2441
2442 exit:
2443         return mfilter;
2444 }
2445
2446 static int
2447 bnxt_ethertype_filter(struct rte_eth_dev *dev,
2448                         enum rte_filter_op filter_op,
2449                         void *arg)
2450 {
2451         struct bnxt *bp = dev->data->dev_private;
2452         struct rte_eth_ethertype_filter *efilter =
2453                         (struct rte_eth_ethertype_filter *)arg;
2454         struct bnxt_filter_info *bfilter, *filter1;
2455         struct bnxt_vnic_info *vnic, *vnic0;
2456         int ret;
2457
2458         if (filter_op == RTE_ETH_FILTER_NOP)
2459                 return 0;
2460
2461         if (arg == NULL) {
2462                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
2463                             filter_op);
2464                 return -EINVAL;
2465         }
2466
2467         vnic0 = &bp->vnic_info[0];
2468         vnic = &bp->vnic_info[efilter->queue];
2469
2470         switch (filter_op) {
2471         case RTE_ETH_FILTER_ADD:
2472                 bnxt_match_and_validate_ether_filter(bp, efilter,
2473                                                         vnic0, vnic, &ret);
2474                 if (ret < 0)
2475                         return ret;
2476
2477                 bfilter = bnxt_get_unused_filter(bp);
2478                 if (bfilter == NULL) {
2479                         PMD_DRV_LOG(ERR,
2480                                 "Not enough resources for a new filter.\n");
2481                         return -ENOMEM;
2482                 }
2483                 bfilter->filter_type = HWRM_CFA_NTUPLE_FILTER;
2484                 memcpy(bfilter->l2_addr, efilter->mac_addr.addr_bytes,
2485                        RTE_ETHER_ADDR_LEN);
2486                 memcpy(bfilter->dst_macaddr, efilter->mac_addr.addr_bytes,
2487                        RTE_ETHER_ADDR_LEN);
2488                 bfilter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_MACADDR;
2489                 bfilter->ethertype = efilter->ether_type;
2490                 bfilter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2491
2492                 filter1 = bnxt_get_l2_filter(bp, bfilter, vnic0);
2493                 if (filter1 == NULL) {
2494                         ret = -EINVAL;
2495                         goto cleanup;
2496                 }
2497                 bfilter->enables |=
2498                         HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID;
2499                 bfilter->fw_l2_filter_id = filter1->fw_l2_filter_id;
2500
2501                 bfilter->dst_id = vnic->fw_vnic_id;
2502
2503                 if (efilter->flags & RTE_ETHTYPE_FLAGS_DROP) {
2504                         bfilter->flags =
2505                                 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_DROP;
2506                 }
2507
2508                 ret = bnxt_hwrm_set_ntuple_filter(bp, bfilter->dst_id, bfilter);
2509                 if (ret)
2510                         goto cleanup;
2511                 STAILQ_INSERT_TAIL(&vnic->filter, bfilter, next);
2512                 break;
2513         case RTE_ETH_FILTER_DELETE:
2514                 filter1 = bnxt_match_and_validate_ether_filter(bp, efilter,
2515                                                         vnic0, vnic, &ret);
2516                 if (ret == -EEXIST) {
2517                         ret = bnxt_hwrm_clear_ntuple_filter(bp, filter1);
2518
2519                         STAILQ_REMOVE(&vnic->filter, filter1, bnxt_filter_info,
2520                                       next);
2521                         bnxt_free_filter(bp, filter1);
2522                 } else if (ret == 0) {
2523                         PMD_DRV_LOG(ERR, "No matching filter found\n");
2524                 }
2525                 break;
2526         default:
2527                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
2528                 ret = -EINVAL;
2529                 goto error;
2530         }
2531         return ret;
2532 cleanup:
2533         bnxt_free_filter(bp, bfilter);
2534 error:
2535         return ret;
2536 }
2537
2538 static inline int
2539 parse_ntuple_filter(struct bnxt *bp,
2540                     struct rte_eth_ntuple_filter *nfilter,
2541                     struct bnxt_filter_info *bfilter)
2542 {
2543         uint32_t en = 0;
2544
2545         if (nfilter->queue >= bp->rx_nr_rings) {
2546                 PMD_DRV_LOG(ERR, "Invalid queue %d\n", nfilter->queue);
2547                 return -EINVAL;
2548         }
2549
2550         switch (nfilter->dst_port_mask) {
2551         case UINT16_MAX:
2552                 bfilter->dst_port_mask = -1;
2553                 bfilter->dst_port = nfilter->dst_port;
2554                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT |
2555                         NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
2556                 break;
2557         default:
2558                 PMD_DRV_LOG(ERR, "invalid dst_port mask.");
2559                 return -EINVAL;
2560         }
2561
2562         bfilter->ip_addr_type = NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4;
2563         en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2564
2565         switch (nfilter->proto_mask) {
2566         case UINT8_MAX:
2567                 if (nfilter->proto == 17) /* IPPROTO_UDP */
2568                         bfilter->ip_protocol = 17;
2569                 else if (nfilter->proto == 6) /* IPPROTO_TCP */
2570                         bfilter->ip_protocol = 6;
2571                 else
2572                         return -EINVAL;
2573                 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2574                 break;
2575         default:
2576                 PMD_DRV_LOG(ERR, "invalid protocol mask.");
2577                 return -EINVAL;
2578         }
2579
2580         switch (nfilter->dst_ip_mask) {
2581         case UINT32_MAX:
2582                 bfilter->dst_ipaddr_mask[0] = -1;
2583                 bfilter->dst_ipaddr[0] = nfilter->dst_ip;
2584                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR |
2585                         NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2586                 break;
2587         default:
2588                 PMD_DRV_LOG(ERR, "invalid dst_ip mask.");
2589                 return -EINVAL;
2590         }
2591
2592         switch (nfilter->src_ip_mask) {
2593         case UINT32_MAX:
2594                 bfilter->src_ipaddr_mask[0] = -1;
2595                 bfilter->src_ipaddr[0] = nfilter->src_ip;
2596                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR |
2597                         NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2598                 break;
2599         default:
2600                 PMD_DRV_LOG(ERR, "invalid src_ip mask.");
2601                 return -EINVAL;
2602         }
2603
2604         switch (nfilter->src_port_mask) {
2605         case UINT16_MAX:
2606                 bfilter->src_port_mask = -1;
2607                 bfilter->src_port = nfilter->src_port;
2608                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT |
2609                         NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
2610                 break;
2611         default:
2612                 PMD_DRV_LOG(ERR, "invalid src_port mask.");
2613                 return -EINVAL;
2614         }
2615
2616         //TODO Priority
2617         //nfilter->priority = (uint8_t)filter->priority;
2618
2619         bfilter->enables = en;
2620         return 0;
2621 }
2622
2623 static struct bnxt_filter_info*
2624 bnxt_match_ntuple_filter(struct bnxt *bp,
2625                          struct bnxt_filter_info *bfilter,
2626                          struct bnxt_vnic_info **mvnic)
2627 {
2628         struct bnxt_filter_info *mfilter = NULL;
2629         int i;
2630
2631         for (i = bp->nr_vnics - 1; i >= 0; i--) {
2632                 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
2633                 STAILQ_FOREACH(mfilter, &vnic->filter, next) {
2634                         if (bfilter->src_ipaddr[0] == mfilter->src_ipaddr[0] &&
2635                             bfilter->src_ipaddr_mask[0] ==
2636                             mfilter->src_ipaddr_mask[0] &&
2637                             bfilter->src_port == mfilter->src_port &&
2638                             bfilter->src_port_mask == mfilter->src_port_mask &&
2639                             bfilter->dst_ipaddr[0] == mfilter->dst_ipaddr[0] &&
2640                             bfilter->dst_ipaddr_mask[0] ==
2641                             mfilter->dst_ipaddr_mask[0] &&
2642                             bfilter->dst_port == mfilter->dst_port &&
2643                             bfilter->dst_port_mask == mfilter->dst_port_mask &&
2644                             bfilter->flags == mfilter->flags &&
2645                             bfilter->enables == mfilter->enables) {
2646                                 if (mvnic)
2647                                         *mvnic = vnic;
2648                                 return mfilter;
2649                         }
2650                 }
2651         }
2652         return NULL;
2653 }
2654
2655 static int
2656 bnxt_cfg_ntuple_filter(struct bnxt *bp,
2657                        struct rte_eth_ntuple_filter *nfilter,
2658                        enum rte_filter_op filter_op)
2659 {
2660         struct bnxt_filter_info *bfilter, *mfilter, *filter1;
2661         struct bnxt_vnic_info *vnic, *vnic0, *mvnic;
2662         int ret;
2663
2664         if (nfilter->flags != RTE_5TUPLE_FLAGS) {
2665                 PMD_DRV_LOG(ERR, "only 5tuple is supported.");
2666                 return -EINVAL;
2667         }
2668
2669         if (nfilter->flags & RTE_NTUPLE_FLAGS_TCP_FLAG) {
2670                 PMD_DRV_LOG(ERR, "Ntuple filter: TCP flags not supported\n");
2671                 return -EINVAL;
2672         }
2673
2674         bfilter = bnxt_get_unused_filter(bp);
2675         if (bfilter == NULL) {
2676                 PMD_DRV_LOG(ERR,
2677                         "Not enough resources for a new filter.\n");
2678                 return -ENOMEM;
2679         }
2680         ret = parse_ntuple_filter(bp, nfilter, bfilter);
2681         if (ret < 0)
2682                 goto free_filter;
2683
2684         vnic = &bp->vnic_info[nfilter->queue];
2685         vnic0 = &bp->vnic_info[0];
2686         filter1 = STAILQ_FIRST(&vnic0->filter);
2687         if (filter1 == NULL) {
2688                 ret = -EINVAL;
2689                 goto free_filter;
2690         }
2691
2692         bfilter->dst_id = vnic->fw_vnic_id;
2693         bfilter->fw_l2_filter_id = filter1->fw_l2_filter_id;
2694         bfilter->enables |=
2695                 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID;
2696         bfilter->ethertype = 0x800;
2697         bfilter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2698
2699         mfilter = bnxt_match_ntuple_filter(bp, bfilter, &mvnic);
2700
2701         if (mfilter != NULL && filter_op == RTE_ETH_FILTER_ADD &&
2702             bfilter->dst_id == mfilter->dst_id) {
2703                 PMD_DRV_LOG(ERR, "filter exists.\n");
2704                 ret = -EEXIST;
2705                 goto free_filter;
2706         } else if (mfilter != NULL && filter_op == RTE_ETH_FILTER_ADD &&
2707                    bfilter->dst_id != mfilter->dst_id) {
2708                 mfilter->dst_id = vnic->fw_vnic_id;
2709                 ret = bnxt_hwrm_set_ntuple_filter(bp, mfilter->dst_id, mfilter);
2710                 STAILQ_REMOVE(&mvnic->filter, mfilter, bnxt_filter_info, next);
2711                 STAILQ_INSERT_TAIL(&vnic->filter, mfilter, next);
2712                 PMD_DRV_LOG(ERR, "filter with matching pattern exists.\n");
2713                 PMD_DRV_LOG(ERR, " Updated it to the new destination queue\n");
2714                 goto free_filter;
2715         }
2716         if (mfilter == NULL && filter_op == RTE_ETH_FILTER_DELETE) {
2717                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
2718                 ret = -ENOENT;
2719                 goto free_filter;
2720         }
2721
2722         if (filter_op == RTE_ETH_FILTER_ADD) {
2723                 bfilter->filter_type = HWRM_CFA_NTUPLE_FILTER;
2724                 ret = bnxt_hwrm_set_ntuple_filter(bp, bfilter->dst_id, bfilter);
2725                 if (ret)
2726                         goto free_filter;
2727                 STAILQ_INSERT_TAIL(&vnic->filter, bfilter, next);
2728         } else {
2729                 if (mfilter == NULL) {
2730                         /* This should not happen. But for Coverity! */
2731                         ret = -ENOENT;
2732                         goto free_filter;
2733                 }
2734                 ret = bnxt_hwrm_clear_ntuple_filter(bp, mfilter);
2735
2736                 STAILQ_REMOVE(&vnic->filter, mfilter, bnxt_filter_info, next);
2737                 bnxt_free_filter(bp, mfilter);
2738                 mfilter->fw_l2_filter_id = -1;
2739                 bnxt_free_filter(bp, bfilter);
2740                 bfilter->fw_l2_filter_id = -1;
2741         }
2742
2743         return 0;
2744 free_filter:
2745         bfilter->fw_l2_filter_id = -1;
2746         bnxt_free_filter(bp, bfilter);
2747         return ret;
2748 }
2749
2750 static int
2751 bnxt_ntuple_filter(struct rte_eth_dev *dev,
2752                         enum rte_filter_op filter_op,
2753                         void *arg)
2754 {
2755         struct bnxt *bp = dev->data->dev_private;
2756         int ret;
2757
2758         if (filter_op == RTE_ETH_FILTER_NOP)
2759                 return 0;
2760
2761         if (arg == NULL) {
2762                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
2763                             filter_op);
2764                 return -EINVAL;
2765         }
2766
2767         switch (filter_op) {
2768         case RTE_ETH_FILTER_ADD:
2769                 ret = bnxt_cfg_ntuple_filter(bp,
2770                         (struct rte_eth_ntuple_filter *)arg,
2771                         filter_op);
2772                 break;
2773         case RTE_ETH_FILTER_DELETE:
2774                 ret = bnxt_cfg_ntuple_filter(bp,
2775                         (struct rte_eth_ntuple_filter *)arg,
2776                         filter_op);
2777                 break;
2778         default:
2779                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
2780                 ret = -EINVAL;
2781                 break;
2782         }
2783         return ret;
2784 }
2785
2786 static int
2787 bnxt_parse_fdir_filter(struct bnxt *bp,
2788                        struct rte_eth_fdir_filter *fdir,
2789                        struct bnxt_filter_info *filter)
2790 {
2791         enum rte_fdir_mode fdir_mode =
2792                 bp->eth_dev->data->dev_conf.fdir_conf.mode;
2793         struct bnxt_vnic_info *vnic0, *vnic;
2794         struct bnxt_filter_info *filter1;
2795         uint32_t en = 0;
2796         int i;
2797
2798         if (fdir_mode == RTE_FDIR_MODE_PERFECT_TUNNEL)
2799                 return -EINVAL;
2800
2801         filter->l2_ovlan = fdir->input.flow_ext.vlan_tci;
2802         en |= EM_FLOW_ALLOC_INPUT_EN_OVLAN_VID;
2803
2804         switch (fdir->input.flow_type) {
2805         case RTE_ETH_FLOW_IPV4:
2806         case RTE_ETH_FLOW_NONFRAG_IPV4_OTHER:
2807                 /* FALLTHROUGH */
2808                 filter->src_ipaddr[0] = fdir->input.flow.ip4_flow.src_ip;
2809                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
2810                 filter->dst_ipaddr[0] = fdir->input.flow.ip4_flow.dst_ip;
2811                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
2812                 filter->ip_protocol = fdir->input.flow.ip4_flow.proto;
2813                 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2814                 filter->ip_addr_type =
2815                         NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4;
2816                 filter->src_ipaddr_mask[0] = 0xffffffff;
2817                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2818                 filter->dst_ipaddr_mask[0] = 0xffffffff;
2819                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2820                 filter->ethertype = 0x800;
2821                 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2822                 break;
2823         case RTE_ETH_FLOW_NONFRAG_IPV4_TCP:
2824                 filter->src_port = fdir->input.flow.tcp4_flow.src_port;
2825                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT;
2826                 filter->dst_port = fdir->input.flow.tcp4_flow.dst_port;
2827                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT;
2828                 filter->dst_port_mask = 0xffff;
2829                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
2830                 filter->src_port_mask = 0xffff;
2831                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
2832                 filter->src_ipaddr[0] = fdir->input.flow.tcp4_flow.ip.src_ip;
2833                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
2834                 filter->dst_ipaddr[0] = fdir->input.flow.tcp4_flow.ip.dst_ip;
2835                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
2836                 filter->ip_protocol = 6;
2837                 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2838                 filter->ip_addr_type =
2839                         NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4;
2840                 filter->src_ipaddr_mask[0] = 0xffffffff;
2841                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2842                 filter->dst_ipaddr_mask[0] = 0xffffffff;
2843                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2844                 filter->ethertype = 0x800;
2845                 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2846                 break;
2847         case RTE_ETH_FLOW_NONFRAG_IPV4_UDP:
2848                 filter->src_port = fdir->input.flow.udp4_flow.src_port;
2849                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT;
2850                 filter->dst_port = fdir->input.flow.udp4_flow.dst_port;
2851                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT;
2852                 filter->dst_port_mask = 0xffff;
2853                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
2854                 filter->src_port_mask = 0xffff;
2855                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
2856                 filter->src_ipaddr[0] = fdir->input.flow.udp4_flow.ip.src_ip;
2857                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
2858                 filter->dst_ipaddr[0] = fdir->input.flow.udp4_flow.ip.dst_ip;
2859                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
2860                 filter->ip_protocol = 17;
2861                 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2862                 filter->ip_addr_type =
2863                         NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4;
2864                 filter->src_ipaddr_mask[0] = 0xffffffff;
2865                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2866                 filter->dst_ipaddr_mask[0] = 0xffffffff;
2867                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2868                 filter->ethertype = 0x800;
2869                 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2870                 break;
2871         case RTE_ETH_FLOW_IPV6:
2872         case RTE_ETH_FLOW_NONFRAG_IPV6_OTHER:
2873                 /* FALLTHROUGH */
2874                 filter->ip_addr_type =
2875                         NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV6;
2876                 filter->ip_protocol = fdir->input.flow.ipv6_flow.proto;
2877                 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2878                 rte_memcpy(filter->src_ipaddr,
2879                            fdir->input.flow.ipv6_flow.src_ip, 16);
2880                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
2881                 rte_memcpy(filter->dst_ipaddr,
2882                            fdir->input.flow.ipv6_flow.dst_ip, 16);
2883                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
2884                 memset(filter->dst_ipaddr_mask, 0xff, 16);
2885                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2886                 memset(filter->src_ipaddr_mask, 0xff, 16);
2887                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2888                 filter->ethertype = 0x86dd;
2889                 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2890                 break;
2891         case RTE_ETH_FLOW_NONFRAG_IPV6_TCP:
2892                 filter->src_port = fdir->input.flow.tcp6_flow.src_port;
2893                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT;
2894                 filter->dst_port = fdir->input.flow.tcp6_flow.dst_port;
2895                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT;
2896                 filter->dst_port_mask = 0xffff;
2897                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
2898                 filter->src_port_mask = 0xffff;
2899                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
2900                 filter->ip_addr_type =
2901                         NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV6;
2902                 filter->ip_protocol = fdir->input.flow.tcp6_flow.ip.proto;
2903                 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2904                 rte_memcpy(filter->src_ipaddr,
2905                            fdir->input.flow.tcp6_flow.ip.src_ip, 16);
2906                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
2907                 rte_memcpy(filter->dst_ipaddr,
2908                            fdir->input.flow.tcp6_flow.ip.dst_ip, 16);
2909                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
2910                 memset(filter->dst_ipaddr_mask, 0xff, 16);
2911                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2912                 memset(filter->src_ipaddr_mask, 0xff, 16);
2913                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2914                 filter->ethertype = 0x86dd;
2915                 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2916                 break;
2917         case RTE_ETH_FLOW_NONFRAG_IPV6_UDP:
2918                 filter->src_port = fdir->input.flow.udp6_flow.src_port;
2919                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT;
2920                 filter->dst_port = fdir->input.flow.udp6_flow.dst_port;
2921                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT;
2922                 filter->dst_port_mask = 0xffff;
2923                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
2924                 filter->src_port_mask = 0xffff;
2925                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
2926                 filter->ip_addr_type =
2927                         NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV6;
2928                 filter->ip_protocol = fdir->input.flow.udp6_flow.ip.proto;
2929                 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2930                 rte_memcpy(filter->src_ipaddr,
2931                            fdir->input.flow.udp6_flow.ip.src_ip, 16);
2932                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
2933                 rte_memcpy(filter->dst_ipaddr,
2934                            fdir->input.flow.udp6_flow.ip.dst_ip, 16);
2935                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
2936                 memset(filter->dst_ipaddr_mask, 0xff, 16);
2937                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2938                 memset(filter->src_ipaddr_mask, 0xff, 16);
2939                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2940                 filter->ethertype = 0x86dd;
2941                 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2942                 break;
2943         case RTE_ETH_FLOW_L2_PAYLOAD:
2944                 filter->ethertype = fdir->input.flow.l2_flow.ether_type;
2945                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2946                 break;
2947         case RTE_ETH_FLOW_VXLAN:
2948                 if (fdir->action.behavior == RTE_ETH_FDIR_REJECT)
2949                         return -EINVAL;
2950                 filter->vni = fdir->input.flow.tunnel_flow.tunnel_id;
2951                 filter->tunnel_type =
2952                         CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN;
2953                 en |= HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_TUNNEL_TYPE;
2954                 break;
2955         case RTE_ETH_FLOW_NVGRE:
2956                 if (fdir->action.behavior == RTE_ETH_FDIR_REJECT)
2957                         return -EINVAL;
2958                 filter->vni = fdir->input.flow.tunnel_flow.tunnel_id;
2959                 filter->tunnel_type =
2960                         CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_NVGRE;
2961                 en |= HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_TUNNEL_TYPE;
2962                 break;
2963         case RTE_ETH_FLOW_UNKNOWN:
2964         case RTE_ETH_FLOW_RAW:
2965         case RTE_ETH_FLOW_FRAG_IPV4:
2966         case RTE_ETH_FLOW_NONFRAG_IPV4_SCTP:
2967         case RTE_ETH_FLOW_FRAG_IPV6:
2968         case RTE_ETH_FLOW_NONFRAG_IPV6_SCTP:
2969         case RTE_ETH_FLOW_IPV6_EX:
2970         case RTE_ETH_FLOW_IPV6_TCP_EX:
2971         case RTE_ETH_FLOW_IPV6_UDP_EX:
2972         case RTE_ETH_FLOW_GENEVE:
2973                 /* FALLTHROUGH */
2974         default:
2975                 return -EINVAL;
2976         }
2977
2978         vnic0 = &bp->vnic_info[0];
2979         vnic = &bp->vnic_info[fdir->action.rx_queue];
2980         if (vnic == NULL) {
2981                 PMD_DRV_LOG(ERR, "Invalid queue %d\n", fdir->action.rx_queue);
2982                 return -EINVAL;
2983         }
2984
2985         if (fdir_mode == RTE_FDIR_MODE_PERFECT_MAC_VLAN) {
2986                 rte_memcpy(filter->dst_macaddr,
2987                         fdir->input.flow.mac_vlan_flow.mac_addr.addr_bytes, 6);
2988                         en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_MACADDR;
2989         }
2990
2991         if (fdir->action.behavior == RTE_ETH_FDIR_REJECT) {
2992                 filter->flags = HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_DROP;
2993                 filter1 = STAILQ_FIRST(&vnic0->filter);
2994                 //filter1 = bnxt_get_l2_filter(bp, filter, vnic0);
2995         } else {
2996                 filter->dst_id = vnic->fw_vnic_id;
2997                 for (i = 0; i < RTE_ETHER_ADDR_LEN; i++)
2998                         if (filter->dst_macaddr[i] == 0x00)
2999                                 filter1 = STAILQ_FIRST(&vnic0->filter);
3000                         else
3001                                 filter1 = bnxt_get_l2_filter(bp, filter, vnic);
3002         }
3003
3004         if (filter1 == NULL)
3005                 return -EINVAL;
3006
3007         en |= HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID;
3008         filter->fw_l2_filter_id = filter1->fw_l2_filter_id;
3009
3010         filter->enables = en;
3011
3012         return 0;
3013 }
3014
3015 static struct bnxt_filter_info *
3016 bnxt_match_fdir(struct bnxt *bp, struct bnxt_filter_info *nf,
3017                 struct bnxt_vnic_info **mvnic)
3018 {
3019         struct bnxt_filter_info *mf = NULL;
3020         int i;
3021
3022         for (i = bp->nr_vnics - 1; i >= 0; i--) {
3023                 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
3024
3025                 STAILQ_FOREACH(mf, &vnic->filter, next) {
3026                         if (mf->filter_type == nf->filter_type &&
3027                             mf->flags == nf->flags &&
3028                             mf->src_port == nf->src_port &&
3029                             mf->src_port_mask == nf->src_port_mask &&
3030                             mf->dst_port == nf->dst_port &&
3031                             mf->dst_port_mask == nf->dst_port_mask &&
3032                             mf->ip_protocol == nf->ip_protocol &&
3033                             mf->ip_addr_type == nf->ip_addr_type &&
3034                             mf->ethertype == nf->ethertype &&
3035                             mf->vni == nf->vni &&
3036                             mf->tunnel_type == nf->tunnel_type &&
3037                             mf->l2_ovlan == nf->l2_ovlan &&
3038                             mf->l2_ovlan_mask == nf->l2_ovlan_mask &&
3039                             mf->l2_ivlan == nf->l2_ivlan &&
3040                             mf->l2_ivlan_mask == nf->l2_ivlan_mask &&
3041                             !memcmp(mf->l2_addr, nf->l2_addr,
3042                                     RTE_ETHER_ADDR_LEN) &&
3043                             !memcmp(mf->l2_addr_mask, nf->l2_addr_mask,
3044                                     RTE_ETHER_ADDR_LEN) &&
3045                             !memcmp(mf->src_macaddr, nf->src_macaddr,
3046                                     RTE_ETHER_ADDR_LEN) &&
3047                             !memcmp(mf->dst_macaddr, nf->dst_macaddr,
3048                                     RTE_ETHER_ADDR_LEN) &&
3049                             !memcmp(mf->src_ipaddr, nf->src_ipaddr,
3050                                     sizeof(nf->src_ipaddr)) &&
3051                             !memcmp(mf->src_ipaddr_mask, nf->src_ipaddr_mask,
3052                                     sizeof(nf->src_ipaddr_mask)) &&
3053                             !memcmp(mf->dst_ipaddr, nf->dst_ipaddr,
3054                                     sizeof(nf->dst_ipaddr)) &&
3055                             !memcmp(mf->dst_ipaddr_mask, nf->dst_ipaddr_mask,
3056                                     sizeof(nf->dst_ipaddr_mask))) {
3057                                 if (mvnic)
3058                                         *mvnic = vnic;
3059                                 return mf;
3060                         }
3061                 }
3062         }
3063         return NULL;
3064 }
3065
3066 static int
3067 bnxt_fdir_filter(struct rte_eth_dev *dev,
3068                  enum rte_filter_op filter_op,
3069                  void *arg)
3070 {
3071         struct bnxt *bp = dev->data->dev_private;
3072         struct rte_eth_fdir_filter *fdir  = (struct rte_eth_fdir_filter *)arg;
3073         struct bnxt_filter_info *filter, *match;
3074         struct bnxt_vnic_info *vnic, *mvnic;
3075         int ret = 0, i;
3076
3077         if (filter_op == RTE_ETH_FILTER_NOP)
3078                 return 0;
3079
3080         if (arg == NULL && filter_op != RTE_ETH_FILTER_FLUSH)
3081                 return -EINVAL;
3082
3083         switch (filter_op) {
3084         case RTE_ETH_FILTER_ADD:
3085         case RTE_ETH_FILTER_DELETE:
3086                 /* FALLTHROUGH */
3087                 filter = bnxt_get_unused_filter(bp);
3088                 if (filter == NULL) {
3089                         PMD_DRV_LOG(ERR,
3090                                 "Not enough resources for a new flow.\n");
3091                         return -ENOMEM;
3092                 }
3093
3094                 ret = bnxt_parse_fdir_filter(bp, fdir, filter);
3095                 if (ret != 0)
3096                         goto free_filter;
3097                 filter->filter_type = HWRM_CFA_NTUPLE_FILTER;
3098
3099                 if (fdir->action.behavior == RTE_ETH_FDIR_REJECT)
3100                         vnic = &bp->vnic_info[0];
3101                 else
3102                         vnic = &bp->vnic_info[fdir->action.rx_queue];
3103
3104                 match = bnxt_match_fdir(bp, filter, &mvnic);
3105                 if (match != NULL && filter_op == RTE_ETH_FILTER_ADD) {
3106                         if (match->dst_id == vnic->fw_vnic_id) {
3107                                 PMD_DRV_LOG(ERR, "Flow already exists.\n");
3108                                 ret = -EEXIST;
3109                                 goto free_filter;
3110                         } else {
3111                                 match->dst_id = vnic->fw_vnic_id;
3112                                 ret = bnxt_hwrm_set_ntuple_filter(bp,
3113                                                                   match->dst_id,
3114                                                                   match);
3115                                 STAILQ_REMOVE(&mvnic->filter, match,
3116                                               bnxt_filter_info, next);
3117                                 STAILQ_INSERT_TAIL(&vnic->filter, match, next);
3118                                 PMD_DRV_LOG(ERR,
3119                                         "Filter with matching pattern exist\n");
3120                                 PMD_DRV_LOG(ERR,
3121                                         "Updated it to new destination q\n");
3122                                 goto free_filter;
3123                         }
3124                 }
3125                 if (match == NULL && filter_op == RTE_ETH_FILTER_DELETE) {
3126                         PMD_DRV_LOG(ERR, "Flow does not exist.\n");
3127                         ret = -ENOENT;
3128                         goto free_filter;
3129                 }
3130
3131                 if (filter_op == RTE_ETH_FILTER_ADD) {
3132                         ret = bnxt_hwrm_set_ntuple_filter(bp,
3133                                                           filter->dst_id,
3134                                                           filter);
3135                         if (ret)
3136                                 goto free_filter;
3137                         STAILQ_INSERT_TAIL(&vnic->filter, filter, next);
3138                 } else {
3139                         ret = bnxt_hwrm_clear_ntuple_filter(bp, match);
3140                         STAILQ_REMOVE(&vnic->filter, match,
3141                                       bnxt_filter_info, next);
3142                         bnxt_free_filter(bp, match);
3143                         filter->fw_l2_filter_id = -1;
3144                         bnxt_free_filter(bp, filter);
3145                 }
3146                 break;
3147         case RTE_ETH_FILTER_FLUSH:
3148                 for (i = bp->nr_vnics - 1; i >= 0; i--) {
3149                         struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
3150
3151                         STAILQ_FOREACH(filter, &vnic->filter, next) {
3152                                 if (filter->filter_type ==
3153                                     HWRM_CFA_NTUPLE_FILTER) {
3154                                         ret =
3155                                         bnxt_hwrm_clear_ntuple_filter(bp,
3156                                                                       filter);
3157                                         STAILQ_REMOVE(&vnic->filter, filter,
3158                                                       bnxt_filter_info, next);
3159                                 }
3160                         }
3161                 }
3162                 return ret;
3163         case RTE_ETH_FILTER_UPDATE:
3164         case RTE_ETH_FILTER_STATS:
3165         case RTE_ETH_FILTER_INFO:
3166                 PMD_DRV_LOG(ERR, "operation %u not implemented", filter_op);
3167                 break;
3168         default:
3169                 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
3170                 ret = -EINVAL;
3171                 break;
3172         }
3173         return ret;
3174
3175 free_filter:
3176         filter->fw_l2_filter_id = -1;
3177         bnxt_free_filter(bp, filter);
3178         return ret;
3179 }
3180
3181 static int
3182 bnxt_filter_ctrl_op(struct rte_eth_dev *dev __rte_unused,
3183                     enum rte_filter_type filter_type,
3184                     enum rte_filter_op filter_op, void *arg)
3185 {
3186         int ret = 0;
3187
3188         ret = is_bnxt_in_error(dev->data->dev_private);
3189         if (ret)
3190                 return ret;
3191
3192         switch (filter_type) {
3193         case RTE_ETH_FILTER_TUNNEL:
3194                 PMD_DRV_LOG(ERR,
3195                         "filter type: %d: To be implemented\n", filter_type);
3196                 break;
3197         case RTE_ETH_FILTER_FDIR:
3198                 ret = bnxt_fdir_filter(dev, filter_op, arg);
3199                 break;
3200         case RTE_ETH_FILTER_NTUPLE:
3201                 ret = bnxt_ntuple_filter(dev, filter_op, arg);
3202                 break;
3203         case RTE_ETH_FILTER_ETHERTYPE:
3204                 ret = bnxt_ethertype_filter(dev, filter_op, arg);
3205                 break;
3206         case RTE_ETH_FILTER_GENERIC:
3207                 if (filter_op != RTE_ETH_FILTER_GET)
3208                         return -EINVAL;
3209                 *(const void **)arg = &bnxt_flow_ops;
3210                 break;
3211         default:
3212                 PMD_DRV_LOG(ERR,
3213                         "Filter type (%d) not supported", filter_type);
3214                 ret = -EINVAL;
3215                 break;
3216         }
3217         return ret;
3218 }
3219
3220 static const uint32_t *
3221 bnxt_dev_supported_ptypes_get_op(struct rte_eth_dev *dev)
3222 {
3223         static const uint32_t ptypes[] = {
3224                 RTE_PTYPE_L2_ETHER_VLAN,
3225                 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN,
3226                 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN,
3227                 RTE_PTYPE_L4_ICMP,
3228                 RTE_PTYPE_L4_TCP,
3229                 RTE_PTYPE_L4_UDP,
3230                 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN,
3231                 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN,
3232                 RTE_PTYPE_INNER_L4_ICMP,
3233                 RTE_PTYPE_INNER_L4_TCP,
3234                 RTE_PTYPE_INNER_L4_UDP,
3235                 RTE_PTYPE_UNKNOWN
3236         };
3237
3238         if (!dev->rx_pkt_burst)
3239                 return NULL;
3240
3241         return ptypes;
3242 }
3243
3244 static int bnxt_map_regs(struct bnxt *bp, uint32_t *reg_arr, int count,
3245                          int reg_win)
3246 {
3247         uint32_t reg_base = *reg_arr & 0xfffff000;
3248         uint32_t win_off;
3249         int i;
3250
3251         for (i = 0; i < count; i++) {
3252                 if ((reg_arr[i] & 0xfffff000) != reg_base)
3253                         return -ERANGE;
3254         }
3255         win_off = BNXT_GRCPF_REG_WINDOW_BASE_OUT + (reg_win - 1) * 4;
3256         rte_write32(reg_base, (uint8_t *)bp->bar0 + win_off);
3257         return 0;
3258 }
3259
3260 static int bnxt_map_ptp_regs(struct bnxt *bp)
3261 {
3262         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3263         uint32_t *reg_arr;
3264         int rc, i;
3265
3266         reg_arr = ptp->rx_regs;
3267         rc = bnxt_map_regs(bp, reg_arr, BNXT_PTP_RX_REGS, 5);
3268         if (rc)
3269                 return rc;
3270
3271         reg_arr = ptp->tx_regs;
3272         rc = bnxt_map_regs(bp, reg_arr, BNXT_PTP_TX_REGS, 6);
3273         if (rc)
3274                 return rc;
3275
3276         for (i = 0; i < BNXT_PTP_RX_REGS; i++)
3277                 ptp->rx_mapped_regs[i] = 0x5000 + (ptp->rx_regs[i] & 0xfff);
3278
3279         for (i = 0; i < BNXT_PTP_TX_REGS; i++)
3280                 ptp->tx_mapped_regs[i] = 0x6000 + (ptp->tx_regs[i] & 0xfff);
3281
3282         return 0;
3283 }
3284
3285 static void bnxt_unmap_ptp_regs(struct bnxt *bp)
3286 {
3287         rte_write32(0, (uint8_t *)bp->bar0 +
3288                          BNXT_GRCPF_REG_WINDOW_BASE_OUT + 16);
3289         rte_write32(0, (uint8_t *)bp->bar0 +
3290                          BNXT_GRCPF_REG_WINDOW_BASE_OUT + 20);
3291 }
3292
3293 static uint64_t bnxt_cc_read(struct bnxt *bp)
3294 {
3295         uint64_t ns;
3296
3297         ns = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3298                               BNXT_GRCPF_REG_SYNC_TIME));
3299         ns |= (uint64_t)(rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3300                                           BNXT_GRCPF_REG_SYNC_TIME + 4))) << 32;
3301         return ns;
3302 }
3303
3304 static int bnxt_get_tx_ts(struct bnxt *bp, uint64_t *ts)
3305 {
3306         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3307         uint32_t fifo;
3308
3309         fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3310                                 ptp->tx_mapped_regs[BNXT_PTP_TX_FIFO]));
3311         if (fifo & BNXT_PTP_TX_FIFO_EMPTY)
3312                 return -EAGAIN;
3313
3314         fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3315                                 ptp->tx_mapped_regs[BNXT_PTP_TX_FIFO]));
3316         *ts = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3317                                 ptp->tx_mapped_regs[BNXT_PTP_TX_TS_L]));
3318         *ts |= (uint64_t)rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3319                                 ptp->tx_mapped_regs[BNXT_PTP_TX_TS_H])) << 32;
3320
3321         return 0;
3322 }
3323
3324 static int bnxt_get_rx_ts(struct bnxt *bp, uint64_t *ts)
3325 {
3326         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3327         struct bnxt_pf_info *pf = &bp->pf;
3328         uint16_t port_id;
3329         uint32_t fifo;
3330
3331         if (!ptp)
3332                 return -ENODEV;
3333
3334         fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3335                                 ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO]));
3336         if (!(fifo & BNXT_PTP_RX_FIFO_PENDING))
3337                 return -EAGAIN;
3338
3339         port_id = pf->port_id;
3340         rte_write32(1 << port_id, (uint8_t *)bp->bar0 +
3341                ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO_ADV]);
3342
3343         fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3344                                    ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO]));
3345         if (fifo & BNXT_PTP_RX_FIFO_PENDING) {
3346 /*              bnxt_clr_rx_ts(bp);       TBD  */
3347                 return -EBUSY;
3348         }
3349
3350         *ts = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3351                                 ptp->rx_mapped_regs[BNXT_PTP_RX_TS_L]));
3352         *ts |= (uint64_t)rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3353                                 ptp->rx_mapped_regs[BNXT_PTP_RX_TS_H])) << 32;
3354
3355         return 0;
3356 }
3357
3358 static int
3359 bnxt_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
3360 {
3361         uint64_t ns;
3362         struct bnxt *bp = dev->data->dev_private;
3363         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3364
3365         if (!ptp)
3366                 return 0;
3367
3368         ns = rte_timespec_to_ns(ts);
3369         /* Set the timecounters to a new value. */
3370         ptp->tc.nsec = ns;
3371
3372         return 0;
3373 }
3374
3375 static int
3376 bnxt_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
3377 {
3378         struct bnxt *bp = dev->data->dev_private;
3379         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3380         uint64_t ns, systime_cycles = 0;
3381         int rc = 0;
3382
3383         if (!ptp)
3384                 return 0;
3385
3386         if (BNXT_CHIP_THOR(bp))
3387                 rc = bnxt_hwrm_port_ts_query(bp, BNXT_PTP_FLAGS_CURRENT_TIME,
3388                                              &systime_cycles);
3389         else
3390                 systime_cycles = bnxt_cc_read(bp);
3391
3392         ns = rte_timecounter_update(&ptp->tc, systime_cycles);
3393         *ts = rte_ns_to_timespec(ns);
3394
3395         return rc;
3396 }
3397 static int
3398 bnxt_timesync_enable(struct rte_eth_dev *dev)
3399 {
3400         struct bnxt *bp = dev->data->dev_private;
3401         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3402         uint32_t shift = 0;
3403         int rc;
3404
3405         if (!ptp)
3406                 return 0;
3407
3408         ptp->rx_filter = 1;
3409         ptp->tx_tstamp_en = 1;
3410         ptp->rxctl = BNXT_PTP_MSG_EVENTS;
3411
3412         rc = bnxt_hwrm_ptp_cfg(bp);
3413         if (rc)
3414                 return rc;
3415
3416         memset(&ptp->tc, 0, sizeof(struct rte_timecounter));
3417         memset(&ptp->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
3418         memset(&ptp->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
3419
3420         ptp->tc.cc_mask = BNXT_CYCLECOUNTER_MASK;
3421         ptp->tc.cc_shift = shift;
3422         ptp->tc.nsec_mask = (1ULL << shift) - 1;
3423
3424         ptp->rx_tstamp_tc.cc_mask = BNXT_CYCLECOUNTER_MASK;
3425         ptp->rx_tstamp_tc.cc_shift = shift;
3426         ptp->rx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
3427
3428         ptp->tx_tstamp_tc.cc_mask = BNXT_CYCLECOUNTER_MASK;
3429         ptp->tx_tstamp_tc.cc_shift = shift;
3430         ptp->tx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
3431
3432         if (!BNXT_CHIP_THOR(bp))
3433                 bnxt_map_ptp_regs(bp);
3434
3435         return 0;
3436 }
3437
3438 static int
3439 bnxt_timesync_disable(struct rte_eth_dev *dev)
3440 {
3441         struct bnxt *bp = dev->data->dev_private;
3442         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3443
3444         if (!ptp)
3445                 return 0;
3446
3447         ptp->rx_filter = 0;
3448         ptp->tx_tstamp_en = 0;
3449         ptp->rxctl = 0;
3450
3451         bnxt_hwrm_ptp_cfg(bp);
3452
3453         if (!BNXT_CHIP_THOR(bp))
3454                 bnxt_unmap_ptp_regs(bp);
3455
3456         return 0;
3457 }
3458
3459 static int
3460 bnxt_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
3461                                  struct timespec *timestamp,
3462                                  uint32_t flags __rte_unused)
3463 {
3464         struct bnxt *bp = dev->data->dev_private;
3465         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3466         uint64_t rx_tstamp_cycles = 0;
3467         uint64_t ns;
3468
3469         if (!ptp)
3470                 return 0;
3471
3472         if (BNXT_CHIP_THOR(bp))
3473                 rx_tstamp_cycles = ptp->rx_timestamp;
3474         else
3475                 bnxt_get_rx_ts(bp, &rx_tstamp_cycles);
3476
3477         ns = rte_timecounter_update(&ptp->rx_tstamp_tc, rx_tstamp_cycles);
3478         *timestamp = rte_ns_to_timespec(ns);
3479         return  0;
3480 }
3481
3482 static int
3483 bnxt_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
3484                                  struct timespec *timestamp)
3485 {
3486         struct bnxt *bp = dev->data->dev_private;
3487         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3488         uint64_t tx_tstamp_cycles = 0;
3489         uint64_t ns;
3490         int rc = 0;
3491
3492         if (!ptp)
3493                 return 0;
3494
3495         if (BNXT_CHIP_THOR(bp))
3496                 rc = bnxt_hwrm_port_ts_query(bp, BNXT_PTP_FLAGS_PATH_TX,
3497                                              &tx_tstamp_cycles);
3498         else
3499                 rc = bnxt_get_tx_ts(bp, &tx_tstamp_cycles);
3500
3501         ns = rte_timecounter_update(&ptp->tx_tstamp_tc, tx_tstamp_cycles);
3502         *timestamp = rte_ns_to_timespec(ns);
3503
3504         return rc;
3505 }
3506
3507 static int
3508 bnxt_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
3509 {
3510         struct bnxt *bp = dev->data->dev_private;
3511         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3512
3513         if (!ptp)
3514                 return 0;
3515
3516         ptp->tc.nsec += delta;
3517
3518         return 0;
3519 }
3520
3521 static int
3522 bnxt_get_eeprom_length_op(struct rte_eth_dev *dev)
3523 {
3524         struct bnxt *bp = dev->data->dev_private;
3525         int rc;
3526         uint32_t dir_entries;
3527         uint32_t entry_length;
3528
3529         rc = is_bnxt_in_error(bp);
3530         if (rc)
3531                 return rc;
3532
3533         PMD_DRV_LOG(INFO, "%04x:%02x:%02x:%02x\n",
3534                 bp->pdev->addr.domain, bp->pdev->addr.bus,
3535                 bp->pdev->addr.devid, bp->pdev->addr.function);
3536
3537         rc = bnxt_hwrm_nvm_get_dir_info(bp, &dir_entries, &entry_length);
3538         if (rc != 0)
3539                 return rc;
3540
3541         return dir_entries * entry_length;
3542 }
3543
3544 static int
3545 bnxt_get_eeprom_op(struct rte_eth_dev *dev,
3546                 struct rte_dev_eeprom_info *in_eeprom)
3547 {
3548         struct bnxt *bp = dev->data->dev_private;
3549         uint32_t index;
3550         uint32_t offset;
3551         int rc;
3552
3553         rc = is_bnxt_in_error(bp);
3554         if (rc)
3555                 return rc;
3556
3557         PMD_DRV_LOG(INFO, "%04x:%02x:%02x:%02x in_eeprom->offset = %d "
3558                 "len = %d\n", bp->pdev->addr.domain,
3559                 bp->pdev->addr.bus, bp->pdev->addr.devid,
3560                 bp->pdev->addr.function, in_eeprom->offset, in_eeprom->length);
3561
3562         if (in_eeprom->offset == 0) /* special offset value to get directory */
3563                 return bnxt_get_nvram_directory(bp, in_eeprom->length,
3564                                                 in_eeprom->data);
3565
3566         index = in_eeprom->offset >> 24;
3567         offset = in_eeprom->offset & 0xffffff;
3568
3569         if (index != 0)
3570                 return bnxt_hwrm_get_nvram_item(bp, index - 1, offset,
3571                                            in_eeprom->length, in_eeprom->data);
3572
3573         return 0;
3574 }
3575
3576 static bool bnxt_dir_type_is_ape_bin_format(uint16_t dir_type)
3577 {
3578         switch (dir_type) {
3579         case BNX_DIR_TYPE_CHIMP_PATCH:
3580         case BNX_DIR_TYPE_BOOTCODE:
3581         case BNX_DIR_TYPE_BOOTCODE_2:
3582         case BNX_DIR_TYPE_APE_FW:
3583         case BNX_DIR_TYPE_APE_PATCH:
3584         case BNX_DIR_TYPE_KONG_FW:
3585         case BNX_DIR_TYPE_KONG_PATCH:
3586         case BNX_DIR_TYPE_BONO_FW:
3587         case BNX_DIR_TYPE_BONO_PATCH:
3588                 /* FALLTHROUGH */
3589                 return true;
3590         }
3591
3592         return false;
3593 }
3594
3595 static bool bnxt_dir_type_is_other_exec_format(uint16_t dir_type)
3596 {
3597         switch (dir_type) {
3598         case BNX_DIR_TYPE_AVS:
3599         case BNX_DIR_TYPE_EXP_ROM_MBA:
3600         case BNX_DIR_TYPE_PCIE:
3601         case BNX_DIR_TYPE_TSCF_UCODE:
3602         case BNX_DIR_TYPE_EXT_PHY:
3603         case BNX_DIR_TYPE_CCM:
3604         case BNX_DIR_TYPE_ISCSI_BOOT:
3605         case BNX_DIR_TYPE_ISCSI_BOOT_IPV6:
3606         case BNX_DIR_TYPE_ISCSI_BOOT_IPV4N6:
3607                 /* FALLTHROUGH */
3608                 return true;
3609         }
3610
3611         return false;
3612 }
3613
3614 static bool bnxt_dir_type_is_executable(uint16_t dir_type)
3615 {
3616         return bnxt_dir_type_is_ape_bin_format(dir_type) ||
3617                 bnxt_dir_type_is_other_exec_format(dir_type);
3618 }
3619
3620 static int
3621 bnxt_set_eeprom_op(struct rte_eth_dev *dev,
3622                 struct rte_dev_eeprom_info *in_eeprom)
3623 {
3624         struct bnxt *bp = dev->data->dev_private;
3625         uint8_t index, dir_op;
3626         uint16_t type, ext, ordinal, attr;
3627         int rc;
3628
3629         rc = is_bnxt_in_error(bp);
3630         if (rc)
3631                 return rc;
3632
3633         PMD_DRV_LOG(INFO, "%04x:%02x:%02x:%02x in_eeprom->offset = %d "
3634                 "len = %d\n", bp->pdev->addr.domain,
3635                 bp->pdev->addr.bus, bp->pdev->addr.devid,
3636                 bp->pdev->addr.function, in_eeprom->offset, in_eeprom->length);
3637
3638         if (!BNXT_PF(bp)) {
3639                 PMD_DRV_LOG(ERR, "NVM write not supported from a VF\n");
3640                 return -EINVAL;
3641         }
3642
3643         type = in_eeprom->magic >> 16;
3644
3645         if (type == 0xffff) { /* special value for directory operations */
3646                 index = in_eeprom->magic & 0xff;
3647                 dir_op = in_eeprom->magic >> 8;
3648                 if (index == 0)
3649                         return -EINVAL;
3650                 switch (dir_op) {
3651                 case 0x0e: /* erase */
3652                         if (in_eeprom->offset != ~in_eeprom->magic)
3653                                 return -EINVAL;
3654                         return bnxt_hwrm_erase_nvram_directory(bp, index - 1);
3655                 default:
3656                         return -EINVAL;
3657                 }
3658         }
3659
3660         /* Create or re-write an NVM item: */
3661         if (bnxt_dir_type_is_executable(type) == true)
3662                 return -EOPNOTSUPP;
3663         ext = in_eeprom->magic & 0xffff;
3664         ordinal = in_eeprom->offset >> 16;
3665         attr = in_eeprom->offset & 0xffff;
3666
3667         return bnxt_hwrm_flash_nvram(bp, type, ordinal, ext, attr,
3668                                      in_eeprom->data, in_eeprom->length);
3669 }
3670
3671 /*
3672  * Initialization
3673  */
3674
3675 static const struct eth_dev_ops bnxt_dev_ops = {
3676         .dev_infos_get = bnxt_dev_info_get_op,
3677         .dev_close = bnxt_dev_close_op,
3678         .dev_configure = bnxt_dev_configure_op,
3679         .dev_start = bnxt_dev_start_op,
3680         .dev_stop = bnxt_dev_stop_op,
3681         .dev_set_link_up = bnxt_dev_set_link_up_op,
3682         .dev_set_link_down = bnxt_dev_set_link_down_op,
3683         .stats_get = bnxt_stats_get_op,
3684         .stats_reset = bnxt_stats_reset_op,
3685         .rx_queue_setup = bnxt_rx_queue_setup_op,
3686         .rx_queue_release = bnxt_rx_queue_release_op,
3687         .tx_queue_setup = bnxt_tx_queue_setup_op,
3688         .tx_queue_release = bnxt_tx_queue_release_op,
3689         .rx_queue_intr_enable = bnxt_rx_queue_intr_enable_op,
3690         .rx_queue_intr_disable = bnxt_rx_queue_intr_disable_op,
3691         .reta_update = bnxt_reta_update_op,
3692         .reta_query = bnxt_reta_query_op,
3693         .rss_hash_update = bnxt_rss_hash_update_op,
3694         .rss_hash_conf_get = bnxt_rss_hash_conf_get_op,
3695         .link_update = bnxt_link_update_op,
3696         .promiscuous_enable = bnxt_promiscuous_enable_op,
3697         .promiscuous_disable = bnxt_promiscuous_disable_op,
3698         .allmulticast_enable = bnxt_allmulticast_enable_op,
3699         .allmulticast_disable = bnxt_allmulticast_disable_op,
3700         .mac_addr_add = bnxt_mac_addr_add_op,
3701         .mac_addr_remove = bnxt_mac_addr_remove_op,
3702         .flow_ctrl_get = bnxt_flow_ctrl_get_op,
3703         .flow_ctrl_set = bnxt_flow_ctrl_set_op,
3704         .udp_tunnel_port_add  = bnxt_udp_tunnel_port_add_op,
3705         .udp_tunnel_port_del  = bnxt_udp_tunnel_port_del_op,
3706         .vlan_filter_set = bnxt_vlan_filter_set_op,
3707         .vlan_offload_set = bnxt_vlan_offload_set_op,
3708         .vlan_tpid_set = bnxt_vlan_tpid_set_op,
3709         .vlan_pvid_set = bnxt_vlan_pvid_set_op,
3710         .mtu_set = bnxt_mtu_set_op,
3711         .mac_addr_set = bnxt_set_default_mac_addr_op,
3712         .xstats_get = bnxt_dev_xstats_get_op,
3713         .xstats_get_names = bnxt_dev_xstats_get_names_op,
3714         .xstats_reset = bnxt_dev_xstats_reset_op,
3715         .fw_version_get = bnxt_fw_version_get,
3716         .set_mc_addr_list = bnxt_dev_set_mc_addr_list_op,
3717         .rxq_info_get = bnxt_rxq_info_get_op,
3718         .txq_info_get = bnxt_txq_info_get_op,
3719         .dev_led_on = bnxt_dev_led_on_op,
3720         .dev_led_off = bnxt_dev_led_off_op,
3721         .xstats_get_by_id = bnxt_dev_xstats_get_by_id_op,
3722         .xstats_get_names_by_id = bnxt_dev_xstats_get_names_by_id_op,
3723         .rx_queue_count = bnxt_rx_queue_count_op,
3724         .rx_descriptor_status = bnxt_rx_descriptor_status_op,
3725         .tx_descriptor_status = bnxt_tx_descriptor_status_op,
3726         .rx_queue_start = bnxt_rx_queue_start,
3727         .rx_queue_stop = bnxt_rx_queue_stop,
3728         .tx_queue_start = bnxt_tx_queue_start,
3729         .tx_queue_stop = bnxt_tx_queue_stop,
3730         .filter_ctrl = bnxt_filter_ctrl_op,
3731         .dev_supported_ptypes_get = bnxt_dev_supported_ptypes_get_op,
3732         .get_eeprom_length    = bnxt_get_eeprom_length_op,
3733         .get_eeprom           = bnxt_get_eeprom_op,
3734         .set_eeprom           = bnxt_set_eeprom_op,
3735         .timesync_enable      = bnxt_timesync_enable,
3736         .timesync_disable     = bnxt_timesync_disable,
3737         .timesync_read_time   = bnxt_timesync_read_time,
3738         .timesync_write_time   = bnxt_timesync_write_time,
3739         .timesync_adjust_time = bnxt_timesync_adjust_time,
3740         .timesync_read_rx_timestamp = bnxt_timesync_read_rx_timestamp,
3741         .timesync_read_tx_timestamp = bnxt_timesync_read_tx_timestamp,
3742 };
3743
3744 static uint32_t bnxt_map_reset_regs(struct bnxt *bp, uint32_t reg)
3745 {
3746         uint32_t offset;
3747
3748         /* Only pre-map the reset GRC registers using window 3 */
3749         rte_write32(reg & 0xfffff000, (uint8_t *)bp->bar0 +
3750                     BNXT_GRCPF_REG_WINDOW_BASE_OUT + 8);
3751
3752         offset = BNXT_GRCP_WINDOW_3_BASE + (reg & 0xffc);
3753
3754         return offset;
3755 }
3756
3757 int bnxt_map_fw_health_status_regs(struct bnxt *bp)
3758 {
3759         struct bnxt_error_recovery_info *info = bp->recovery_info;
3760         uint32_t reg_base = 0xffffffff;
3761         int i;
3762
3763         /* Only pre-map the monitoring GRC registers using window 2 */
3764         for (i = 0; i < BNXT_FW_STATUS_REG_CNT; i++) {
3765                 uint32_t reg = info->status_regs[i];
3766
3767                 if (BNXT_FW_STATUS_REG_TYPE(reg) != BNXT_FW_STATUS_REG_TYPE_GRC)
3768                         continue;
3769
3770                 if (reg_base == 0xffffffff)
3771                         reg_base = reg & 0xfffff000;
3772                 if ((reg & 0xfffff000) != reg_base)
3773                         return -ERANGE;
3774
3775                 /* Use mask 0xffc as the Lower 2 bits indicates
3776                  * address space location
3777                  */
3778                 info->mapped_status_regs[i] = BNXT_GRCP_WINDOW_2_BASE +
3779                                                 (reg & 0xffc);
3780         }
3781
3782         if (reg_base == 0xffffffff)
3783                 return 0;
3784
3785         rte_write32(reg_base, (uint8_t *)bp->bar0 +
3786                     BNXT_GRCPF_REG_WINDOW_BASE_OUT + 4);
3787
3788         return 0;
3789 }
3790
3791 static void bnxt_write_fw_reset_reg(struct bnxt *bp, uint32_t index)
3792 {
3793         struct bnxt_error_recovery_info *info = bp->recovery_info;
3794         uint32_t delay = info->delay_after_reset[index];
3795         uint32_t val = info->reset_reg_val[index];
3796         uint32_t reg = info->reset_reg[index];
3797         uint32_t type, offset;
3798
3799         type = BNXT_FW_STATUS_REG_TYPE(reg);
3800         offset = BNXT_FW_STATUS_REG_OFF(reg);
3801
3802         switch (type) {
3803         case BNXT_FW_STATUS_REG_TYPE_CFG:
3804                 rte_pci_write_config(bp->pdev, &val, sizeof(val), offset);
3805                 break;
3806         case BNXT_FW_STATUS_REG_TYPE_GRC:
3807                 offset = bnxt_map_reset_regs(bp, offset);
3808                 rte_write32(val, (uint8_t *)bp->bar0 + offset);
3809                 break;
3810         case BNXT_FW_STATUS_REG_TYPE_BAR0:
3811                 rte_write32(val, (uint8_t *)bp->bar0 + offset);
3812                 break;
3813         }
3814         /* wait on a specific interval of time until core reset is complete */
3815         if (delay)
3816                 rte_delay_ms(delay);
3817 }
3818
3819 static void bnxt_dev_cleanup(struct bnxt *bp)
3820 {
3821         bnxt_set_hwrm_link_config(bp, false);
3822         bp->link_info.link_up = 0;
3823         if (bp->dev_stopped == 0)
3824                 bnxt_dev_stop_op(bp->eth_dev);
3825
3826         bnxt_uninit_resources(bp, true);
3827 }
3828
3829 static int bnxt_restore_filters(struct bnxt *bp)
3830 {
3831         struct rte_eth_dev *dev = bp->eth_dev;
3832         int ret = 0;
3833
3834         if (dev->data->all_multicast)
3835                 ret = bnxt_allmulticast_enable_op(dev);
3836         if (dev->data->promiscuous)
3837                 ret = bnxt_promiscuous_enable_op(dev);
3838
3839         /* TODO restore other filters as well */
3840         return ret;
3841 }
3842
3843 static void bnxt_dev_recover(void *arg)
3844 {
3845         struct bnxt *bp = arg;
3846         int timeout = bp->fw_reset_max_msecs;
3847         int rc = 0;
3848
3849         /* Clear Error flag so that device re-init should happen */
3850         bp->flags &= ~BNXT_FLAG_FATAL_ERROR;
3851
3852         do {
3853                 rc = bnxt_hwrm_ver_get(bp);
3854                 if (rc == 0)
3855                         break;
3856                 rte_delay_ms(BNXT_FW_READY_WAIT_INTERVAL);
3857                 timeout -= BNXT_FW_READY_WAIT_INTERVAL;
3858         } while (rc && timeout);
3859
3860         if (rc) {
3861                 PMD_DRV_LOG(ERR, "FW is not Ready after reset\n");
3862                 goto err;
3863         }
3864
3865         rc = bnxt_init_resources(bp, true);
3866         if (rc) {
3867                 PMD_DRV_LOG(ERR,
3868                             "Failed to initialize resources after reset\n");
3869                 goto err;
3870         }
3871         /* clear reset flag as the device is initialized now */
3872         bp->flags &= ~BNXT_FLAG_FW_RESET;
3873
3874         rc = bnxt_dev_start_op(bp->eth_dev);
3875         if (rc) {
3876                 PMD_DRV_LOG(ERR, "Failed to start port after reset\n");
3877                 goto err;
3878         }
3879
3880         rc = bnxt_restore_filters(bp);
3881         if (rc)
3882                 goto err;
3883
3884         PMD_DRV_LOG(INFO, "Recovered from FW reset\n");
3885         return;
3886 err:
3887         bp->flags |= BNXT_FLAG_FATAL_ERROR;
3888         bnxt_uninit_resources(bp, false);
3889         PMD_DRV_LOG(ERR, "Failed to recover from FW reset\n");
3890 }
3891
3892 void bnxt_dev_reset_and_resume(void *arg)
3893 {
3894         struct bnxt *bp = arg;
3895         int rc;
3896
3897         bnxt_dev_cleanup(bp);
3898
3899         bnxt_wait_for_device_shutdown(bp);
3900
3901         rc = rte_eal_alarm_set(US_PER_MS * bp->fw_reset_min_msecs,
3902                                bnxt_dev_recover, (void *)bp);
3903         if (rc)
3904                 PMD_DRV_LOG(ERR, "Error setting recovery alarm");
3905 }
3906
3907 uint32_t bnxt_read_fw_status_reg(struct bnxt *bp, uint32_t index)
3908 {
3909         struct bnxt_error_recovery_info *info = bp->recovery_info;
3910         uint32_t reg = info->status_regs[index];
3911         uint32_t type, offset, val = 0;
3912
3913         type = BNXT_FW_STATUS_REG_TYPE(reg);
3914         offset = BNXT_FW_STATUS_REG_OFF(reg);
3915
3916         switch (type) {
3917         case BNXT_FW_STATUS_REG_TYPE_CFG:
3918                 rte_pci_read_config(bp->pdev, &val, sizeof(val), offset);
3919                 break;
3920         case BNXT_FW_STATUS_REG_TYPE_GRC:
3921                 offset = info->mapped_status_regs[index];
3922                 /* FALLTHROUGH */
3923         case BNXT_FW_STATUS_REG_TYPE_BAR0:
3924                 val = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3925                                        offset));
3926                 break;
3927         }
3928
3929         return val;
3930 }
3931
3932 static int bnxt_fw_reset_all(struct bnxt *bp)
3933 {
3934         struct bnxt_error_recovery_info *info = bp->recovery_info;
3935         uint32_t i;
3936         int rc = 0;
3937
3938         if (info->flags & BNXT_FLAG_ERROR_RECOVERY_HOST) {
3939                 /* Reset through master function driver */
3940                 for (i = 0; i < info->reg_array_cnt; i++)
3941                         bnxt_write_fw_reset_reg(bp, i);
3942                 /* Wait for time specified by FW after triggering reset */
3943                 rte_delay_ms(info->master_func_wait_period_after_reset);
3944         } else if (info->flags & BNXT_FLAG_ERROR_RECOVERY_CO_CPU) {
3945                 /* Reset with the help of Kong processor */
3946                 rc = bnxt_hwrm_fw_reset(bp);
3947                 if (rc)
3948                         PMD_DRV_LOG(ERR, "Failed to reset FW\n");
3949         }
3950
3951         return rc;
3952 }
3953
3954 static void bnxt_fw_reset_cb(void *arg)
3955 {
3956         struct bnxt *bp = arg;
3957         struct bnxt_error_recovery_info *info = bp->recovery_info;
3958         int rc = 0;
3959
3960         /* Only Master function can do FW reset */
3961         if (bnxt_is_master_func(bp) &&
3962             bnxt_is_recovery_enabled(bp)) {
3963                 rc = bnxt_fw_reset_all(bp);
3964                 if (rc) {
3965                         PMD_DRV_LOG(ERR, "Adapter recovery failed\n");
3966                         return;
3967                 }
3968         }
3969
3970         /* if recovery method is ERROR_RECOVERY_CO_CPU, KONG will send
3971          * EXCEPTION_FATAL_ASYNC event to all the functions
3972          * (including MASTER FUNC). After receiving this Async, all the active
3973          * drivers should treat this case as FW initiated recovery
3974          */
3975         if (info->flags & BNXT_FLAG_ERROR_RECOVERY_HOST) {
3976                 bp->fw_reset_min_msecs = BNXT_MIN_FW_READY_TIMEOUT;
3977                 bp->fw_reset_max_msecs = BNXT_MAX_FW_RESET_TIMEOUT;
3978
3979                 /* To recover from error */
3980                 rte_eal_alarm_set(US_PER_MS, bnxt_dev_reset_and_resume,
3981                                   (void *)bp);
3982         }
3983 }
3984
3985 /* Driver should poll FW heartbeat, reset_counter with the frequency
3986  * advertised by FW in HWRM_ERROR_RECOVERY_QCFG.
3987  * When the driver detects heartbeat stop or change in reset_counter,
3988  * it has to trigger a reset to recover from the error condition.
3989  * A “master PF” is the function who will have the privilege to
3990  * initiate the chimp reset. The master PF will be elected by the
3991  * firmware and will be notified through async message.
3992  */
3993 static void bnxt_check_fw_health(void *arg)
3994 {
3995         struct bnxt *bp = arg;
3996         struct bnxt_error_recovery_info *info = bp->recovery_info;
3997         uint32_t val = 0, wait_msec;
3998
3999         if (!info || !bnxt_is_recovery_enabled(bp) ||
4000             is_bnxt_in_error(bp))
4001                 return;
4002
4003         val = bnxt_read_fw_status_reg(bp, BNXT_FW_HEARTBEAT_CNT_REG);
4004         if (val == info->last_heart_beat)
4005                 goto reset;
4006
4007         info->last_heart_beat = val;
4008
4009         val = bnxt_read_fw_status_reg(bp, BNXT_FW_RECOVERY_CNT_REG);
4010         if (val != info->last_reset_counter)
4011                 goto reset;
4012
4013         info->last_reset_counter = val;
4014
4015         rte_eal_alarm_set(US_PER_MS * info->driver_polling_freq,
4016                           bnxt_check_fw_health, (void *)bp);
4017
4018         return;
4019 reset:
4020         /* Stop DMA to/from device */
4021         bp->flags |= BNXT_FLAG_FATAL_ERROR;
4022         bp->flags |= BNXT_FLAG_FW_RESET;
4023
4024         PMD_DRV_LOG(ERR, "Detected FW dead condition\n");
4025
4026         if (bnxt_is_master_func(bp))
4027                 wait_msec = info->master_func_wait_period;
4028         else
4029                 wait_msec = info->normal_func_wait_period;
4030
4031         rte_eal_alarm_set(US_PER_MS * wait_msec,
4032                           bnxt_fw_reset_cb, (void *)bp);
4033 }
4034
4035 void bnxt_schedule_fw_health_check(struct bnxt *bp)
4036 {
4037         uint32_t polling_freq;
4038
4039         if (!bnxt_is_recovery_enabled(bp))
4040                 return;
4041
4042         if (bp->flags & BNXT_FLAG_FW_HEALTH_CHECK_SCHEDULED)
4043                 return;
4044
4045         polling_freq = bp->recovery_info->driver_polling_freq;
4046
4047         rte_eal_alarm_set(US_PER_MS * polling_freq,
4048                           bnxt_check_fw_health, (void *)bp);
4049         bp->flags |= BNXT_FLAG_FW_HEALTH_CHECK_SCHEDULED;
4050 }
4051
4052 static void bnxt_cancel_fw_health_check(struct bnxt *bp)
4053 {
4054         if (!bnxt_is_recovery_enabled(bp))
4055                 return;
4056
4057         rte_eal_alarm_cancel(bnxt_check_fw_health, (void *)bp);
4058         bp->flags &= ~BNXT_FLAG_FW_HEALTH_CHECK_SCHEDULED;
4059 }
4060
4061 static bool bnxt_vf_pciid(uint16_t id)
4062 {
4063         if (id == BROADCOM_DEV_ID_57304_VF ||
4064             id == BROADCOM_DEV_ID_57406_VF ||
4065             id == BROADCOM_DEV_ID_5731X_VF ||
4066             id == BROADCOM_DEV_ID_5741X_VF ||
4067             id == BROADCOM_DEV_ID_57414_VF ||
4068             id == BROADCOM_DEV_ID_STRATUS_NIC_VF1 ||
4069             id == BROADCOM_DEV_ID_STRATUS_NIC_VF2 ||
4070             id == BROADCOM_DEV_ID_58802_VF ||
4071             id == BROADCOM_DEV_ID_57500_VF1 ||
4072             id == BROADCOM_DEV_ID_57500_VF2)
4073                 return true;
4074         return false;
4075 }
4076
4077 bool bnxt_stratus_device(struct bnxt *bp)
4078 {
4079         uint16_t id = bp->pdev->id.device_id;
4080
4081         if (id == BROADCOM_DEV_ID_STRATUS_NIC ||
4082             id == BROADCOM_DEV_ID_STRATUS_NIC_VF1 ||
4083             id == BROADCOM_DEV_ID_STRATUS_NIC_VF2)
4084                 return true;
4085         return false;
4086 }
4087
4088 static int bnxt_init_board(struct rte_eth_dev *eth_dev)
4089 {
4090         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
4091         struct bnxt *bp = eth_dev->data->dev_private;
4092
4093         /* enable device (incl. PCI PM wakeup), and bus-mastering */
4094         bp->bar0 = (void *)pci_dev->mem_resource[0].addr;
4095         bp->doorbell_base = (void *)pci_dev->mem_resource[2].addr;
4096         if (!bp->bar0 || !bp->doorbell_base) {
4097                 PMD_DRV_LOG(ERR, "Unable to access Hardware\n");
4098                 return -ENODEV;
4099         }
4100
4101         bp->eth_dev = eth_dev;
4102         bp->pdev = pci_dev;
4103
4104         return 0;
4105 }
4106
4107 static int bnxt_alloc_ctx_mem_blk(__rte_unused struct bnxt *bp,
4108                                   struct bnxt_ctx_pg_info *ctx_pg,
4109                                   uint32_t mem_size,
4110                                   const char *suffix,
4111                                   uint16_t idx)
4112 {
4113         struct bnxt_ring_mem_info *rmem = &ctx_pg->ring_mem;
4114         const struct rte_memzone *mz = NULL;
4115         char mz_name[RTE_MEMZONE_NAMESIZE];
4116         rte_iova_t mz_phys_addr;
4117         uint64_t valid_bits = 0;
4118         uint32_t sz;
4119         int i;
4120
4121         if (!mem_size)
4122                 return 0;
4123
4124         rmem->nr_pages = RTE_ALIGN_MUL_CEIL(mem_size, BNXT_PAGE_SIZE) /
4125                          BNXT_PAGE_SIZE;
4126         rmem->page_size = BNXT_PAGE_SIZE;
4127         rmem->pg_arr = ctx_pg->ctx_pg_arr;
4128         rmem->dma_arr = ctx_pg->ctx_dma_arr;
4129         rmem->flags = BNXT_RMEM_VALID_PTE_FLAG;
4130
4131         valid_bits = PTU_PTE_VALID;
4132
4133         if (rmem->nr_pages > 1) {
4134                 snprintf(mz_name, RTE_MEMZONE_NAMESIZE,
4135                          "bnxt_ctx_pg_tbl%s_%x_%d",
4136                          suffix, idx, bp->eth_dev->data->port_id);
4137                 mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0;
4138                 mz = rte_memzone_lookup(mz_name);
4139                 if (!mz) {
4140                         mz = rte_memzone_reserve_aligned(mz_name,
4141                                                 rmem->nr_pages * 8,
4142                                                 SOCKET_ID_ANY,
4143                                                 RTE_MEMZONE_2MB |
4144                                                 RTE_MEMZONE_SIZE_HINT_ONLY |
4145                                                 RTE_MEMZONE_IOVA_CONTIG,
4146                                                 BNXT_PAGE_SIZE);
4147                         if (mz == NULL)
4148                                 return -ENOMEM;
4149                 }
4150
4151                 memset(mz->addr, 0, mz->len);
4152                 mz_phys_addr = mz->iova;
4153                 if ((unsigned long)mz->addr == mz_phys_addr) {
4154                         PMD_DRV_LOG(DEBUG,
4155                                     "physical address same as virtual\n");
4156                         PMD_DRV_LOG(DEBUG, "Using rte_mem_virt2iova()\n");
4157                         mz_phys_addr = rte_mem_virt2iova(mz->addr);
4158                         if (mz_phys_addr == RTE_BAD_IOVA) {
4159                                 PMD_DRV_LOG(ERR,
4160                                         "unable to map addr to phys memory\n");
4161                                 return -ENOMEM;
4162                         }
4163                 }
4164                 rte_mem_lock_page(((char *)mz->addr));
4165
4166                 rmem->pg_tbl = mz->addr;
4167                 rmem->pg_tbl_map = mz_phys_addr;
4168                 rmem->pg_tbl_mz = mz;
4169         }
4170
4171         snprintf(mz_name, RTE_MEMZONE_NAMESIZE, "bnxt_ctx_%s_%x_%d",
4172                  suffix, idx, bp->eth_dev->data->port_id);
4173         mz = rte_memzone_lookup(mz_name);
4174         if (!mz) {
4175                 mz = rte_memzone_reserve_aligned(mz_name,
4176                                                  mem_size,
4177                                                  SOCKET_ID_ANY,
4178                                                  RTE_MEMZONE_1GB |
4179                                                  RTE_MEMZONE_SIZE_HINT_ONLY |
4180                                                  RTE_MEMZONE_IOVA_CONTIG,
4181                                                  BNXT_PAGE_SIZE);
4182                 if (mz == NULL)
4183                         return -ENOMEM;
4184         }
4185
4186         memset(mz->addr, 0, mz->len);
4187         mz_phys_addr = mz->iova;
4188         if ((unsigned long)mz->addr == mz_phys_addr) {
4189                 PMD_DRV_LOG(DEBUG,
4190                             "Memzone physical address same as virtual.\n");
4191                 PMD_DRV_LOG(DEBUG, "Using rte_mem_virt2iova()\n");
4192                 for (sz = 0; sz < mem_size; sz += BNXT_PAGE_SIZE)
4193                         rte_mem_lock_page(((char *)mz->addr) + sz);
4194                 mz_phys_addr = rte_mem_virt2iova(mz->addr);
4195                 if (mz_phys_addr == RTE_BAD_IOVA) {
4196                         PMD_DRV_LOG(ERR,
4197                                     "unable to map addr to phys memory\n");
4198                         return -ENOMEM;
4199                 }
4200         }
4201
4202         for (sz = 0, i = 0; sz < mem_size; sz += BNXT_PAGE_SIZE, i++) {
4203                 rte_mem_lock_page(((char *)mz->addr) + sz);
4204                 rmem->pg_arr[i] = ((char *)mz->addr) + sz;
4205                 rmem->dma_arr[i] = mz_phys_addr + sz;
4206
4207                 if (rmem->nr_pages > 1) {
4208                         if (i == rmem->nr_pages - 2 &&
4209                             (rmem->flags & BNXT_RMEM_RING_PTE_FLAG))
4210                                 valid_bits |= PTU_PTE_NEXT_TO_LAST;
4211                         else if (i == rmem->nr_pages - 1 &&
4212                                  (rmem->flags & BNXT_RMEM_RING_PTE_FLAG))
4213                                 valid_bits |= PTU_PTE_LAST;
4214
4215                         rmem->pg_tbl[i] = rte_cpu_to_le_64(rmem->dma_arr[i] |
4216                                                            valid_bits);
4217                 }
4218         }
4219
4220         rmem->mz = mz;
4221         if (rmem->vmem_size)
4222                 rmem->vmem = (void **)mz->addr;
4223         rmem->dma_arr[0] = mz_phys_addr;
4224         return 0;
4225 }
4226
4227 static void bnxt_free_ctx_mem(struct bnxt *bp)
4228 {
4229         int i;
4230
4231         if (!bp->ctx || !(bp->ctx->flags & BNXT_CTX_FLAG_INITED))
4232                 return;
4233
4234         bp->ctx->flags &= ~BNXT_CTX_FLAG_INITED;
4235         rte_memzone_free(bp->ctx->qp_mem.ring_mem.mz);
4236         rte_memzone_free(bp->ctx->srq_mem.ring_mem.mz);
4237         rte_memzone_free(bp->ctx->cq_mem.ring_mem.mz);
4238         rte_memzone_free(bp->ctx->vnic_mem.ring_mem.mz);
4239         rte_memzone_free(bp->ctx->stat_mem.ring_mem.mz);
4240         rte_memzone_free(bp->ctx->qp_mem.ring_mem.pg_tbl_mz);
4241         rte_memzone_free(bp->ctx->srq_mem.ring_mem.pg_tbl_mz);
4242         rte_memzone_free(bp->ctx->cq_mem.ring_mem.pg_tbl_mz);
4243         rte_memzone_free(bp->ctx->vnic_mem.ring_mem.pg_tbl_mz);
4244         rte_memzone_free(bp->ctx->stat_mem.ring_mem.pg_tbl_mz);
4245
4246         for (i = 0; i < BNXT_MAX_Q; i++) {
4247                 if (bp->ctx->tqm_mem[i])
4248                         rte_memzone_free(bp->ctx->tqm_mem[i]->ring_mem.mz);
4249         }
4250
4251         rte_free(bp->ctx);
4252         bp->ctx = NULL;
4253 }
4254
4255 #define bnxt_roundup(x, y)   ((((x) + ((y) - 1)) / (y)) * (y))
4256
4257 #define min_t(type, x, y) ({                    \
4258         type __min1 = (x);                      \
4259         type __min2 = (y);                      \
4260         __min1 < __min2 ? __min1 : __min2; })
4261
4262 #define max_t(type, x, y) ({                    \
4263         type __max1 = (x);                      \
4264         type __max2 = (y);                      \
4265         __max1 > __max2 ? __max1 : __max2; })
4266
4267 #define clamp_t(type, _x, min, max)     min_t(type, max_t(type, _x, min), max)
4268
4269 int bnxt_alloc_ctx_mem(struct bnxt *bp)
4270 {
4271         struct bnxt_ctx_pg_info *ctx_pg;
4272         struct bnxt_ctx_mem_info *ctx;
4273         uint32_t mem_size, ena, entries;
4274         int i, rc;
4275
4276         rc = bnxt_hwrm_func_backing_store_qcaps(bp);
4277         if (rc) {
4278                 PMD_DRV_LOG(ERR, "Query context mem capability failed\n");
4279                 return rc;
4280         }
4281         ctx = bp->ctx;
4282         if (!ctx || (ctx->flags & BNXT_CTX_FLAG_INITED))
4283                 return 0;
4284
4285         ctx_pg = &ctx->qp_mem;
4286         ctx_pg->entries = ctx->qp_min_qp1_entries + ctx->qp_max_l2_entries;
4287         mem_size = ctx->qp_entry_size * ctx_pg->entries;
4288         rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "qp_mem", 0);
4289         if (rc)
4290                 return rc;
4291
4292         ctx_pg = &ctx->srq_mem;
4293         ctx_pg->entries = ctx->srq_max_l2_entries;
4294         mem_size = ctx->srq_entry_size * ctx_pg->entries;
4295         rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "srq_mem", 0);
4296         if (rc)
4297                 return rc;
4298
4299         ctx_pg = &ctx->cq_mem;
4300         ctx_pg->entries = ctx->cq_max_l2_entries;
4301         mem_size = ctx->cq_entry_size * ctx_pg->entries;
4302         rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "cq_mem", 0);
4303         if (rc)
4304                 return rc;
4305
4306         ctx_pg = &ctx->vnic_mem;
4307         ctx_pg->entries = ctx->vnic_max_vnic_entries +
4308                 ctx->vnic_max_ring_table_entries;
4309         mem_size = ctx->vnic_entry_size * ctx_pg->entries;
4310         rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "vnic_mem", 0);
4311         if (rc)
4312                 return rc;
4313
4314         ctx_pg = &ctx->stat_mem;
4315         ctx_pg->entries = ctx->stat_max_entries;
4316         mem_size = ctx->stat_entry_size * ctx_pg->entries;
4317         rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "stat_mem", 0);
4318         if (rc)
4319                 return rc;
4320
4321         entries = ctx->qp_max_l2_entries +
4322                   ctx->vnic_max_vnic_entries +
4323                   ctx->tqm_min_entries_per_ring;
4324         entries = bnxt_roundup(entries, ctx->tqm_entries_multiple);
4325         entries = clamp_t(uint32_t, entries, ctx->tqm_min_entries_per_ring,
4326                           ctx->tqm_max_entries_per_ring);
4327         for (i = 0, ena = 0; i < BNXT_MAX_Q; i++) {
4328                 ctx_pg = ctx->tqm_mem[i];
4329                 /* use min tqm entries for now. */
4330                 ctx_pg->entries = entries;
4331                 mem_size = ctx->tqm_entry_size * ctx_pg->entries;
4332                 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "tqm_mem", i);
4333                 if (rc)
4334                         return rc;
4335                 ena |= HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_SP << i;
4336         }
4337
4338         ena |= FUNC_BACKING_STORE_CFG_INPUT_DFLT_ENABLES;
4339         rc = bnxt_hwrm_func_backing_store_cfg(bp, ena);
4340         if (rc)
4341                 PMD_DRV_LOG(ERR,
4342                             "Failed to configure context mem: rc = %d\n", rc);
4343         else
4344                 ctx->flags |= BNXT_CTX_FLAG_INITED;
4345
4346         return rc;
4347 }
4348
4349 static int bnxt_alloc_stats_mem(struct bnxt *bp)
4350 {
4351         struct rte_pci_device *pci_dev = bp->pdev;
4352         char mz_name[RTE_MEMZONE_NAMESIZE];
4353         const struct rte_memzone *mz = NULL;
4354         uint32_t total_alloc_len;
4355         rte_iova_t mz_phys_addr;
4356
4357         if (pci_dev->id.device_id == BROADCOM_DEV_ID_NS2)
4358                 return 0;
4359
4360         snprintf(mz_name, RTE_MEMZONE_NAMESIZE,
4361                  "bnxt_" PCI_PRI_FMT "-%s", pci_dev->addr.domain,
4362                  pci_dev->addr.bus, pci_dev->addr.devid,
4363                  pci_dev->addr.function, "rx_port_stats");
4364         mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0;
4365         mz = rte_memzone_lookup(mz_name);
4366         total_alloc_len =
4367                 RTE_CACHE_LINE_ROUNDUP(sizeof(struct rx_port_stats) +
4368                                        sizeof(struct rx_port_stats_ext) + 512);
4369         if (!mz) {
4370                 mz = rte_memzone_reserve(mz_name, total_alloc_len,
4371                                          SOCKET_ID_ANY,
4372                                          RTE_MEMZONE_2MB |
4373                                          RTE_MEMZONE_SIZE_HINT_ONLY |
4374                                          RTE_MEMZONE_IOVA_CONTIG);
4375                 if (mz == NULL)
4376                         return -ENOMEM;
4377         }
4378         memset(mz->addr, 0, mz->len);
4379         mz_phys_addr = mz->iova;
4380         if ((unsigned long)mz->addr == mz_phys_addr) {
4381                 PMD_DRV_LOG(DEBUG,
4382                             "Memzone physical address same as virtual.\n");
4383                 PMD_DRV_LOG(DEBUG,
4384                             "Using rte_mem_virt2iova()\n");
4385                 mz_phys_addr = rte_mem_virt2iova(mz->addr);
4386                 if (mz_phys_addr == RTE_BAD_IOVA) {
4387                         PMD_DRV_LOG(ERR,
4388                                     "Can't map address to physical memory\n");
4389                         return -ENOMEM;
4390                 }
4391         }
4392
4393         bp->rx_mem_zone = (const void *)mz;
4394         bp->hw_rx_port_stats = mz->addr;
4395         bp->hw_rx_port_stats_map = mz_phys_addr;
4396
4397         snprintf(mz_name, RTE_MEMZONE_NAMESIZE,
4398                  "bnxt_" PCI_PRI_FMT "-%s", pci_dev->addr.domain,
4399                  pci_dev->addr.bus, pci_dev->addr.devid,
4400                  pci_dev->addr.function, "tx_port_stats");
4401         mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0;
4402         mz = rte_memzone_lookup(mz_name);
4403         total_alloc_len =
4404                 RTE_CACHE_LINE_ROUNDUP(sizeof(struct tx_port_stats) +
4405                                        sizeof(struct tx_port_stats_ext) + 512);
4406         if (!mz) {
4407                 mz = rte_memzone_reserve(mz_name,
4408                                          total_alloc_len,
4409                                          SOCKET_ID_ANY,
4410                                          RTE_MEMZONE_2MB |
4411                                          RTE_MEMZONE_SIZE_HINT_ONLY |
4412                                          RTE_MEMZONE_IOVA_CONTIG);
4413                 if (mz == NULL)
4414                         return -ENOMEM;
4415         }
4416         memset(mz->addr, 0, mz->len);
4417         mz_phys_addr = mz->iova;
4418         if ((unsigned long)mz->addr == mz_phys_addr) {
4419                 PMD_DRV_LOG(DEBUG,
4420                             "Memzone physical address same as virtual\n");
4421                 PMD_DRV_LOG(DEBUG, "Using rte_mem_virt2iova()\n");
4422                 mz_phys_addr = rte_mem_virt2iova(mz->addr);
4423                 if (mz_phys_addr == RTE_BAD_IOVA) {
4424                         PMD_DRV_LOG(ERR,
4425                                     "Can't map address to physical memory\n");
4426                         return -ENOMEM;
4427                 }
4428         }
4429
4430         bp->tx_mem_zone = (const void *)mz;
4431         bp->hw_tx_port_stats = mz->addr;
4432         bp->hw_tx_port_stats_map = mz_phys_addr;
4433         bp->flags |= BNXT_FLAG_PORT_STATS;
4434
4435         /* Display extended statistics if FW supports it */
4436         if (bp->hwrm_spec_code < HWRM_SPEC_CODE_1_8_4 ||
4437             bp->hwrm_spec_code == HWRM_SPEC_CODE_1_9_0 ||
4438             !(bp->flags & BNXT_FLAG_EXT_STATS_SUPPORTED))
4439                 return 0;
4440
4441         bp->hw_rx_port_stats_ext = (void *)
4442                 ((uint8_t *)bp->hw_rx_port_stats +
4443                  sizeof(struct rx_port_stats));
4444         bp->hw_rx_port_stats_ext_map = bp->hw_rx_port_stats_map +
4445                 sizeof(struct rx_port_stats);
4446         bp->flags |= BNXT_FLAG_EXT_RX_PORT_STATS;
4447
4448         if (bp->hwrm_spec_code < HWRM_SPEC_CODE_1_9_2 ||
4449             bp->flags & BNXT_FLAG_EXT_STATS_SUPPORTED) {
4450                 bp->hw_tx_port_stats_ext = (void *)
4451                         ((uint8_t *)bp->hw_tx_port_stats +
4452                          sizeof(struct tx_port_stats));
4453                 bp->hw_tx_port_stats_ext_map =
4454                         bp->hw_tx_port_stats_map +
4455                         sizeof(struct tx_port_stats);
4456                 bp->flags |= BNXT_FLAG_EXT_TX_PORT_STATS;
4457         }
4458
4459         return 0;
4460 }
4461
4462 static int bnxt_setup_mac_addr(struct rte_eth_dev *eth_dev)
4463 {
4464         struct bnxt *bp = eth_dev->data->dev_private;
4465         int rc = 0;
4466
4467         eth_dev->data->mac_addrs = rte_zmalloc("bnxt_mac_addr_tbl",
4468                                                RTE_ETHER_ADDR_LEN *
4469                                                bp->max_l2_ctx,
4470                                                0);
4471         if (eth_dev->data->mac_addrs == NULL) {
4472                 PMD_DRV_LOG(ERR, "Failed to alloc MAC addr tbl\n");
4473                 return -ENOMEM;
4474         }
4475
4476         if (bnxt_check_zero_bytes(bp->dflt_mac_addr, RTE_ETHER_ADDR_LEN)) {
4477                 if (BNXT_PF(bp))
4478                         return -EINVAL;
4479
4480                 /* Generate a random MAC address, if none was assigned by PF */
4481                 PMD_DRV_LOG(INFO, "VF MAC address not assigned by Host PF\n");
4482                 bnxt_eth_hw_addr_random(bp->mac_addr);
4483                 PMD_DRV_LOG(INFO,
4484                             "Assign random MAC:%02X:%02X:%02X:%02X:%02X:%02X\n",
4485                             bp->mac_addr[0], bp->mac_addr[1], bp->mac_addr[2],
4486                             bp->mac_addr[3], bp->mac_addr[4], bp->mac_addr[5]);
4487
4488                 rc = bnxt_hwrm_set_mac(bp);
4489                 if (!rc)
4490                         memcpy(&bp->eth_dev->data->mac_addrs[0], bp->mac_addr,
4491                                RTE_ETHER_ADDR_LEN);
4492                 return rc;
4493         }
4494
4495         /* Copy the permanent MAC from the FUNC_QCAPS response */
4496         memcpy(bp->mac_addr, bp->dflt_mac_addr, RTE_ETHER_ADDR_LEN);
4497         memcpy(&eth_dev->data->mac_addrs[0], bp->mac_addr, RTE_ETHER_ADDR_LEN);
4498
4499         return rc;
4500 }
4501
4502 static int bnxt_restore_dflt_mac(struct bnxt *bp)
4503 {
4504         int rc = 0;
4505
4506         /* MAC is already configured in FW */
4507         if (!bnxt_check_zero_bytes(bp->dflt_mac_addr, RTE_ETHER_ADDR_LEN))
4508                 return 0;
4509
4510         /* Restore the old MAC configured */
4511         rc = bnxt_hwrm_set_mac(bp);
4512         if (rc)
4513                 PMD_DRV_LOG(ERR, "Failed to restore MAC address\n");
4514
4515         return rc;
4516 }
4517
4518 static void bnxt_config_vf_req_fwd(struct bnxt *bp)
4519 {
4520         if (!BNXT_PF(bp))
4521                 return;
4522
4523 #define ALLOW_FUNC(x)   \
4524         { \
4525                 uint32_t arg = (x); \
4526                 bp->pf.vf_req_fwd[((arg) >> 5)] &= \
4527                 ~rte_cpu_to_le_32(1 << ((arg) & 0x1f)); \
4528         }
4529
4530         /* Forward all requests if firmware is new enough */
4531         if (((bp->fw_ver >= ((20 << 24) | (6 << 16) | (100 << 8))) &&
4532              (bp->fw_ver < ((20 << 24) | (7 << 16)))) ||
4533             ((bp->fw_ver >= ((20 << 24) | (8 << 16))))) {
4534                 memset(bp->pf.vf_req_fwd, 0xff, sizeof(bp->pf.vf_req_fwd));
4535         } else {
4536                 PMD_DRV_LOG(WARNING,
4537                             "Firmware too old for VF mailbox functionality\n");
4538                 memset(bp->pf.vf_req_fwd, 0, sizeof(bp->pf.vf_req_fwd));
4539         }
4540
4541         /*
4542          * The following are used for driver cleanup. If we disallow these,
4543          * VF drivers can't clean up cleanly.
4544          */
4545         ALLOW_FUNC(HWRM_FUNC_DRV_UNRGTR);
4546         ALLOW_FUNC(HWRM_VNIC_FREE);
4547         ALLOW_FUNC(HWRM_RING_FREE);
4548         ALLOW_FUNC(HWRM_RING_GRP_FREE);
4549         ALLOW_FUNC(HWRM_VNIC_RSS_COS_LB_CTX_FREE);
4550         ALLOW_FUNC(HWRM_CFA_L2_FILTER_FREE);
4551         ALLOW_FUNC(HWRM_STAT_CTX_FREE);
4552         ALLOW_FUNC(HWRM_PORT_PHY_QCFG);
4553         ALLOW_FUNC(HWRM_VNIC_TPA_CFG);
4554 }
4555
4556 static int bnxt_init_fw(struct bnxt *bp)
4557 {
4558         uint16_t mtu;
4559         int rc = 0;
4560
4561         rc = bnxt_hwrm_ver_get(bp);
4562         if (rc)
4563                 return rc;
4564
4565         rc = bnxt_hwrm_func_reset(bp);
4566         if (rc)
4567                 return -EIO;
4568
4569         rc = bnxt_hwrm_vnic_qcaps(bp);
4570         if (rc)
4571                 return rc;
4572
4573         rc = bnxt_hwrm_queue_qportcfg(bp);
4574         if (rc)
4575                 return rc;
4576
4577         /* Get the MAX capabilities for this function.
4578          * This function also allocates context memory for TQM rings and
4579          * informs the firmware about this allocated backing store memory.
4580          */
4581         rc = bnxt_hwrm_func_qcaps(bp);
4582         if (rc)
4583                 return rc;
4584
4585         rc = bnxt_hwrm_func_qcfg(bp, &mtu);
4586         if (rc)
4587                 return rc;
4588
4589         rc = bnxt_hwrm_cfa_adv_flow_mgmt_qcaps(bp);
4590         if (rc)
4591                 return rc;
4592
4593         /* Get the adapter error recovery support info */
4594         rc = bnxt_hwrm_error_recovery_qcfg(bp);
4595         if (rc)
4596                 bp->flags &= ~BNXT_FLAG_FW_CAP_ERROR_RECOVERY;
4597
4598         if (mtu >= RTE_ETHER_MIN_MTU && mtu <= BNXT_MAX_MTU &&
4599             mtu != bp->eth_dev->data->mtu)
4600                 bp->eth_dev->data->mtu = mtu;
4601
4602         bnxt_hwrm_port_led_qcaps(bp);
4603
4604         return 0;
4605 }
4606
4607 static int
4608 bnxt_init_locks(struct bnxt *bp)
4609 {
4610         int err;
4611
4612         err = pthread_mutex_init(&bp->flow_lock, NULL);
4613         if (err) {
4614                 PMD_DRV_LOG(ERR, "Unable to initialize flow_lock\n");
4615                 return err;
4616         }
4617
4618         err = pthread_mutex_init(&bp->def_cp_lock, NULL);
4619         if (err)
4620                 PMD_DRV_LOG(ERR, "Unable to initialize def_cp_lock\n");
4621         return err;
4622 }
4623
4624 static int bnxt_init_resources(struct bnxt *bp, bool reconfig_dev)
4625 {
4626         int rc;
4627
4628         rc = bnxt_init_fw(bp);
4629         if (rc)
4630                 return rc;
4631
4632         if (!reconfig_dev) {
4633                 rc = bnxt_setup_mac_addr(bp->eth_dev);
4634                 if (rc)
4635                         return rc;
4636         } else {
4637                 rc = bnxt_restore_dflt_mac(bp);
4638                 if (rc)
4639                         return rc;
4640         }
4641
4642         bnxt_config_vf_req_fwd(bp);
4643
4644         rc = bnxt_hwrm_func_driver_register(bp);
4645         if (rc) {
4646                 PMD_DRV_LOG(ERR, "Failed to register driver");
4647                 return -EBUSY;
4648         }
4649
4650         if (BNXT_PF(bp)) {
4651                 if (bp->pdev->max_vfs) {
4652                         rc = bnxt_hwrm_allocate_vfs(bp, bp->pdev->max_vfs);
4653                         if (rc) {
4654                                 PMD_DRV_LOG(ERR, "Failed to allocate VFs\n");
4655                                 return rc;
4656                         }
4657                 } else {
4658                         rc = bnxt_hwrm_allocate_pf_only(bp);
4659                         if (rc) {
4660                                 PMD_DRV_LOG(ERR,
4661                                             "Failed to allocate PF resources");
4662                                 return rc;
4663                         }
4664                 }
4665         }
4666
4667         rc = bnxt_alloc_mem(bp, reconfig_dev);
4668         if (rc)
4669                 return rc;
4670
4671         rc = bnxt_setup_int(bp);
4672         if (rc)
4673                 return rc;
4674
4675         bnxt_init_nic(bp);
4676
4677         rc = bnxt_request_int(bp);
4678         if (rc)
4679                 return rc;
4680
4681         rc = bnxt_init_locks(bp);
4682         if (rc)
4683                 return rc;
4684
4685         return 0;
4686 }
4687
4688 static int
4689 bnxt_dev_init(struct rte_eth_dev *eth_dev)
4690 {
4691         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
4692         static int version_printed;
4693         struct bnxt *bp;
4694         int rc;
4695
4696         if (version_printed++ == 0)
4697                 PMD_DRV_LOG(INFO, "%s\n", bnxt_version);
4698
4699         eth_dev->dev_ops = &bnxt_dev_ops;
4700         eth_dev->rx_pkt_burst = &bnxt_recv_pkts;
4701         eth_dev->tx_pkt_burst = &bnxt_xmit_pkts;
4702
4703         /*
4704          * For secondary processes, we don't initialise any further
4705          * as primary has already done this work.
4706          */
4707         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
4708                 return 0;
4709
4710         rte_eth_copy_pci_info(eth_dev, pci_dev);
4711
4712         bp = eth_dev->data->dev_private;
4713
4714         bp->dev_stopped = 1;
4715
4716         if (bnxt_vf_pciid(pci_dev->id.device_id))
4717                 bp->flags |= BNXT_FLAG_VF;
4718
4719         if (pci_dev->id.device_id == BROADCOM_DEV_ID_57508 ||
4720             pci_dev->id.device_id == BROADCOM_DEV_ID_57504 ||
4721             pci_dev->id.device_id == BROADCOM_DEV_ID_57502 ||
4722             pci_dev->id.device_id == BROADCOM_DEV_ID_57500_VF1 ||
4723             pci_dev->id.device_id == BROADCOM_DEV_ID_57500_VF2)
4724                 bp->flags |= BNXT_FLAG_THOR_CHIP;
4725
4726         if (pci_dev->id.device_id == BROADCOM_DEV_ID_58802 ||
4727             pci_dev->id.device_id == BROADCOM_DEV_ID_58804 ||
4728             pci_dev->id.device_id == BROADCOM_DEV_ID_58808 ||
4729             pci_dev->id.device_id == BROADCOM_DEV_ID_58802_VF)
4730                 bp->flags |= BNXT_FLAG_STINGRAY;
4731
4732         rc = bnxt_init_board(eth_dev);
4733         if (rc) {
4734                 PMD_DRV_LOG(ERR,
4735                             "Failed to initialize board rc: %x\n", rc);
4736                 return rc;
4737         }
4738
4739         rc = bnxt_alloc_hwrm_resources(bp);
4740         if (rc) {
4741                 PMD_DRV_LOG(ERR,
4742                             "Failed to allocate hwrm resource rc: %x\n", rc);
4743                 goto error_free;
4744         }
4745         rc = bnxt_init_resources(bp, false);
4746         if (rc)
4747                 goto error_free;
4748
4749         rc = bnxt_alloc_stats_mem(bp);
4750         if (rc)
4751                 goto error_free;
4752
4753         PMD_DRV_LOG(INFO,
4754                     DRV_MODULE_NAME "found at mem %" PRIX64 ", node addr %pM\n",
4755                     pci_dev->mem_resource[0].phys_addr,
4756                     pci_dev->mem_resource[0].addr);
4757
4758         return 0;
4759
4760 error_free:
4761         bnxt_dev_uninit(eth_dev);
4762         return rc;
4763 }
4764
4765 static void
4766 bnxt_uninit_locks(struct bnxt *bp)
4767 {
4768         pthread_mutex_destroy(&bp->flow_lock);
4769         pthread_mutex_destroy(&bp->def_cp_lock);
4770 }
4771
4772 static int
4773 bnxt_uninit_resources(struct bnxt *bp, bool reconfig_dev)
4774 {
4775         int rc;
4776
4777         bnxt_free_int(bp);
4778         bnxt_free_mem(bp, reconfig_dev);
4779         bnxt_hwrm_func_buf_unrgtr(bp);
4780         rc = bnxt_hwrm_func_driver_unregister(bp, 0);
4781         bp->flags &= ~BNXT_FLAG_REGISTERED;
4782         bnxt_free_ctx_mem(bp);
4783         if (!reconfig_dev) {
4784                 bnxt_free_hwrm_resources(bp);
4785
4786                 if (bp->recovery_info != NULL) {
4787                         rte_free(bp->recovery_info);
4788                         bp->recovery_info = NULL;
4789                 }
4790         }
4791
4792         rte_free(bp->ptp_cfg);
4793         bp->ptp_cfg = NULL;
4794         return rc;
4795 }
4796
4797 static int
4798 bnxt_dev_uninit(struct rte_eth_dev *eth_dev)
4799 {
4800         struct bnxt *bp = eth_dev->data->dev_private;
4801         int rc;
4802
4803         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
4804                 return -EPERM;
4805
4806         PMD_DRV_LOG(DEBUG, "Calling Device uninit\n");
4807
4808         rc = bnxt_uninit_resources(bp, false);
4809
4810         if (bp->grp_info != NULL) {
4811                 rte_free(bp->grp_info);
4812                 bp->grp_info = NULL;
4813         }
4814
4815         if (bp->tx_mem_zone) {
4816                 rte_memzone_free((const struct rte_memzone *)bp->tx_mem_zone);
4817                 bp->tx_mem_zone = NULL;
4818         }
4819
4820         if (bp->rx_mem_zone) {
4821                 rte_memzone_free((const struct rte_memzone *)bp->rx_mem_zone);
4822                 bp->rx_mem_zone = NULL;
4823         }
4824
4825         if (bp->dev_stopped == 0)
4826                 bnxt_dev_close_op(eth_dev);
4827         if (bp->pf.vf_info)
4828                 rte_free(bp->pf.vf_info);
4829         eth_dev->dev_ops = NULL;
4830         eth_dev->rx_pkt_burst = NULL;
4831         eth_dev->tx_pkt_burst = NULL;
4832
4833         bnxt_uninit_locks(bp);
4834
4835         return rc;
4836 }
4837
4838 static int bnxt_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
4839         struct rte_pci_device *pci_dev)
4840 {
4841         return rte_eth_dev_pci_generic_probe(pci_dev, sizeof(struct bnxt),
4842                 bnxt_dev_init);
4843 }
4844
4845 static int bnxt_pci_remove(struct rte_pci_device *pci_dev)
4846 {
4847         if (rte_eal_process_type() == RTE_PROC_PRIMARY)
4848                 return rte_eth_dev_pci_generic_remove(pci_dev,
4849                                 bnxt_dev_uninit);
4850         else
4851                 return rte_eth_dev_pci_generic_remove(pci_dev, NULL);
4852 }
4853
4854 static struct rte_pci_driver bnxt_rte_pmd = {
4855         .id_table = bnxt_pci_id_map,
4856         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
4857         .probe = bnxt_pci_probe,
4858         .remove = bnxt_pci_remove,
4859 };
4860
4861 static bool
4862 is_device_supported(struct rte_eth_dev *dev, struct rte_pci_driver *drv)
4863 {
4864         if (strcmp(dev->device->driver->name, drv->driver.name))
4865                 return false;
4866
4867         return true;
4868 }
4869
4870 bool is_bnxt_supported(struct rte_eth_dev *dev)
4871 {
4872         return is_device_supported(dev, &bnxt_rte_pmd);
4873 }
4874
4875 RTE_INIT(bnxt_init_log)
4876 {
4877         bnxt_logtype_driver = rte_log_register("pmd.net.bnxt.driver");
4878         if (bnxt_logtype_driver >= 0)
4879                 rte_log_set_level(bnxt_logtype_driver, RTE_LOG_NOTICE);
4880 }
4881
4882 RTE_PMD_REGISTER_PCI(net_bnxt, bnxt_rte_pmd);
4883 RTE_PMD_REGISTER_PCI_TABLE(net_bnxt, bnxt_pci_id_map);
4884 RTE_PMD_REGISTER_KMOD_DEP(net_bnxt, "* igb_uio | uio_pci_generic | vfio-pci");