drivers/net/bnxt/bnxt_ethdev.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2014-2021 Broadcom
   3  * All rights reserved.
   4  */
   5
   6 #include <inttypes.h>
   7 #include <stdbool.h>
   8
   9 #include <rte_dev.h>
  10 #include <ethdev_driver.h>
  11 #include <ethdev_pci.h>
  12 #include <rte_malloc.h>
  13 #include <rte_cycles.h>
  14 #include <rte_alarm.h>
  15 #include <rte_kvargs.h>
  16 #include <rte_vect.h>
  17
  18 #include "bnxt.h"
  19 #include "bnxt_filter.h"
  20 #include "bnxt_hwrm.h"
  21 #include "bnxt_irq.h"
  22 #include "bnxt_reps.h"
  23 #include "bnxt_ring.h"
  24 #include "bnxt_rxq.h"
  25 #include "bnxt_rxr.h"
  26 #include "bnxt_stats.h"
  27 #include "bnxt_txq.h"
  28 #include "bnxt_txr.h"
  29 #include "bnxt_vnic.h"
  30 #include "hsi_struct_def_dpdk.h"
  31 #include "bnxt_nvm_defs.h"
  32 #include "bnxt_tf_common.h"
  33 #include "ulp_flow_db.h"
  34 #include "rte_pmd_bnxt.h"
  35
  36 #define DRV_MODULE_NAME         "bnxt"
  37 static const char bnxt_version[] =
  38         "Broadcom NetXtreme driver " DRV_MODULE_NAME;
  39
  40 /*
  41  * The set of PCI devices this driver supports
  42  */
  43 static const struct rte_pci_id bnxt_pci_id_map[] = {
  44         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM,
  45                          BROADCOM_DEV_ID_STRATUS_NIC_VF1) },
  46         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM,
  47                          BROADCOM_DEV_ID_STRATUS_NIC_VF2) },
  48         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_STRATUS_NIC) },
  49         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414_VF) },
  50         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57304_VF) },
  51         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_NS2) },
  52         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57406_VF) },
  53         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57407_MF) },
  54         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_5741X_VF) },
  55         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_5731X_VF) },
  56         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_MF) },
  57         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57412) },
  58         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414) },
  59         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_RJ45) },
  60         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_RJ45) },
  61         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57412_MF) },
  62         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57317_RJ45) },
  63         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_SFP) },
  64         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_SFP) },
  65         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57317_SFP) },
  66         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414_MF) },
  67         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_MF) },
  68         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58802) },
  69         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58804) },
  70         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58808) },
  71         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58802_VF) },
  72         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57508) },
  73         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57504) },
  74         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57502) },
  75         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57500_VF1) },
  76         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57500_VF2) },
  77         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57508_MF1) },
  78         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57504_MF1) },
  79         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57502_MF1) },
  80         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57508_MF2) },
  81         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57504_MF2) },
  82         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57502_MF2) },
  83         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58812) },
  84         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58814) },
  85         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58818) },
  86         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58818_VF) },
  87         { .vendor_id = 0, /* sentinel */ },
  88 };
  89
  90 #define BNXT_DEVARG_TRUFLOW     "host-based-truflow"
  91 #define BNXT_DEVARG_FLOW_XSTAT  "flow-xstat"
  92 #define BNXT_DEVARG_MAX_NUM_KFLOWS  "max-num-kflows"
  93 #define BNXT_DEVARG_REPRESENTOR "representor"
  94 #define BNXT_DEVARG_REP_BASED_PF  "rep-based-pf"
  95 #define BNXT_DEVARG_REP_IS_PF  "rep-is-pf"
  96 #define BNXT_DEVARG_REP_Q_R2F  "rep-q-r2f"
  97 #define BNXT_DEVARG_REP_Q_F2R  "rep-q-f2r"
  98 #define BNXT_DEVARG_REP_FC_R2F  "rep-fc-r2f"
  99 #define BNXT_DEVARG_REP_FC_F2R  "rep-fc-f2r"
 100
 101 static const char *const bnxt_dev_args[] = {
 102         BNXT_DEVARG_REPRESENTOR,
 103         BNXT_DEVARG_TRUFLOW,
 104         BNXT_DEVARG_FLOW_XSTAT,
 105         BNXT_DEVARG_MAX_NUM_KFLOWS,
 106         BNXT_DEVARG_REP_BASED_PF,
 107         BNXT_DEVARG_REP_IS_PF,
 108         BNXT_DEVARG_REP_Q_R2F,
 109         BNXT_DEVARG_REP_Q_F2R,
 110         BNXT_DEVARG_REP_FC_R2F,
 111         BNXT_DEVARG_REP_FC_F2R,
 112         NULL
 113 };
 114
 115 /*
 116  * truflow == false to disable the feature
 117  * truflow == true to enable the feature
 118  */
 119 #define BNXT_DEVARG_TRUFLOW_INVALID(truflow)    ((truflow) > 1)
 120
 121 /*
 122  * flow_xstat == false to disable the feature
 123  * flow_xstat == true to enable the feature
 124  */
 125 #define BNXT_DEVARG_FLOW_XSTAT_INVALID(flow_xstat)      ((flow_xstat) > 1)
 126
 127 /*
 128  * rep_is_pf == false to indicate VF representor
 129  * rep_is_pf == true to indicate PF representor
 130  */
 131 #define BNXT_DEVARG_REP_IS_PF_INVALID(rep_is_pf)        ((rep_is_pf) > 1)
 132
 133 /*
 134  * rep_based_pf == Physical index of the PF
 135  */
 136 #define BNXT_DEVARG_REP_BASED_PF_INVALID(rep_based_pf)  ((rep_based_pf) > 15)
 137 /*
 138  * rep_q_r2f == Logical COS Queue index for the rep to endpoint direction
 139  */
 140 #define BNXT_DEVARG_REP_Q_R2F_INVALID(rep_q_r2f)        ((rep_q_r2f) > 3)
 141
 142 /*
 143  * rep_q_f2r == Logical COS Queue index for the endpoint to rep direction
 144  */
 145 #define BNXT_DEVARG_REP_Q_F2R_INVALID(rep_q_f2r)        ((rep_q_f2r) > 3)
 146
 147 /*
 148  * rep_fc_r2f == Flow control for the representor to endpoint direction
 149  */
 150 #define BNXT_DEVARG_REP_FC_R2F_INVALID(rep_fc_r2f)      ((rep_fc_r2f) > 1)
 151
 152 /*
 153  * rep_fc_f2r == Flow control for the endpoint to representor direction
 154  */
 155 #define BNXT_DEVARG_REP_FC_F2R_INVALID(rep_fc_f2r)      ((rep_fc_f2r) > 1)
 156
 157 int bnxt_cfa_code_dynfield_offset = -1;
 158
 159 /*
 160  * max_num_kflows must be >= 32
 161  * and must be a power-of-2 supported value
 162  * return: 1 -> invalid
 163  *         0 -> valid
 164  */
 165 static int bnxt_devarg_max_num_kflow_invalid(uint16_t max_num_kflows)
 166 {
 167         if (max_num_kflows < 32 || !rte_is_power_of_2(max_num_kflows))
 168                 return 1;
 169         return 0;
 170 }
 171
 172 static int bnxt_vlan_offload_set_op(struct rte_eth_dev *dev, int mask);
 173 static int bnxt_dev_uninit(struct rte_eth_dev *eth_dev);
 174 static int bnxt_init_resources(struct bnxt *bp, bool reconfig_dev);
 175 static int bnxt_uninit_resources(struct bnxt *bp, bool reconfig_dev);
 176 static void bnxt_cancel_fw_health_check(struct bnxt *bp);
 177 static int bnxt_restore_vlan_filters(struct bnxt *bp);
 178 static void bnxt_dev_recover(void *arg);
 179 static void bnxt_free_error_recovery_info(struct bnxt *bp);
 180 static void bnxt_free_rep_info(struct bnxt *bp);
 181
 182 int is_bnxt_in_error(struct bnxt *bp)
 183 {
 184         if (bp->flags & BNXT_FLAG_FATAL_ERROR)
 185                 return -EIO;
 186         if (bp->flags & BNXT_FLAG_FW_RESET)
 187                 return -EBUSY;
 188
 189         return 0;
 190 }
 191
 192 /***********************/
 193
 194 /*
 195  * High level utility functions
 196  */
 197
 198 static uint16_t bnxt_rss_ctxts(const struct bnxt *bp)
 199 {
 200         unsigned int num_rss_rings = RTE_MIN(bp->rx_nr_rings,
 201                                              BNXT_RSS_TBL_SIZE_P5);
 202
 203         if (!BNXT_CHIP_P5(bp))
 204                 return 1;
 205
 206         return RTE_ALIGN_MUL_CEIL(num_rss_rings,
 207                                   BNXT_RSS_ENTRIES_PER_CTX_P5) /
 208                                   BNXT_RSS_ENTRIES_PER_CTX_P5;
 209 }
 210
 211 uint16_t bnxt_rss_hash_tbl_size(const struct bnxt *bp)
 212 {
 213         if (!BNXT_CHIP_P5(bp))
 214                 return HW_HASH_INDEX_SIZE;
 215
 216         return bnxt_rss_ctxts(bp) * BNXT_RSS_ENTRIES_PER_CTX_P5;
 217 }
 218
 219 static void bnxt_free_parent_info(struct bnxt *bp)
 220 {
 221         rte_free(bp->parent);
 222 }
 223
 224 static void bnxt_free_pf_info(struct bnxt *bp)
 225 {
 226         rte_free(bp->pf);
 227 }
 228
 229 static void bnxt_free_link_info(struct bnxt *bp)
 230 {
 231         rte_free(bp->link_info);
 232 }
 233
 234 static void bnxt_free_leds_info(struct bnxt *bp)
 235 {
 236         if (BNXT_VF(bp))
 237                 return;
 238
 239         rte_free(bp->leds);
 240         bp->leds = NULL;
 241 }
 242
 243 static void bnxt_free_flow_stats_info(struct bnxt *bp)
 244 {
 245         rte_free(bp->flow_stat);
 246         bp->flow_stat = NULL;
 247 }
 248
 249 static void bnxt_free_cos_queues(struct bnxt *bp)
 250 {
 251         rte_free(bp->rx_cos_queue);
 252         rte_free(bp->tx_cos_queue);
 253 }
 254
 255 static void bnxt_free_mem(struct bnxt *bp, bool reconfig)
 256 {
 257         bnxt_free_filter_mem(bp);
 258         bnxt_free_vnic_attributes(bp);
 259         bnxt_free_vnic_mem(bp);
 260
 261         /* tx/rx rings are configured as part of *_queue_setup callbacks.
 262          * If the number of rings change across fw update,
 263          * we don't have much choice except to warn the user.
 264          */
 265         if (!reconfig) {
 266                 bnxt_free_stats(bp);
 267                 bnxt_free_tx_rings(bp);
 268                 bnxt_free_rx_rings(bp);
 269         }
 270         bnxt_free_async_cp_ring(bp);
 271         bnxt_free_rxtx_nq_ring(bp);
 272
 273         rte_free(bp->grp_info);
 274         bp->grp_info = NULL;
 275 }
 276
 277 static int bnxt_alloc_parent_info(struct bnxt *bp)
 278 {
 279         bp->parent = rte_zmalloc("bnxt_parent_info",
 280                                  sizeof(struct bnxt_parent_info), 0);
 281         if (bp->parent == NULL)
 282                 return -ENOMEM;
 283
 284         return 0;
 285 }
 286
 287 static int bnxt_alloc_pf_info(struct bnxt *bp)
 288 {
 289         bp->pf = rte_zmalloc("bnxt_pf_info", sizeof(struct bnxt_pf_info), 0);
 290         if (bp->pf == NULL)
 291                 return -ENOMEM;
 292
 293         return 0;
 294 }
 295
 296 static int bnxt_alloc_link_info(struct bnxt *bp)
 297 {
 298         bp->link_info =
 299                 rte_zmalloc("bnxt_link_info", sizeof(struct bnxt_link_info), 0);
 300         if (bp->link_info == NULL)
 301                 return -ENOMEM;
 302
 303         return 0;
 304 }
 305
 306 static int bnxt_alloc_leds_info(struct bnxt *bp)
 307 {
 308         if (BNXT_VF(bp))
 309                 return 0;
 310
 311         bp->leds = rte_zmalloc("bnxt_leds",
 312                                BNXT_MAX_LED * sizeof(struct bnxt_led_info),
 313                                0);
 314         if (bp->leds == NULL)
 315                 return -ENOMEM;
 316
 317         return 0;
 318 }
 319
 320 static int bnxt_alloc_cos_queues(struct bnxt *bp)
 321 {
 322         bp->rx_cos_queue =
 323                 rte_zmalloc("bnxt_rx_cosq",
 324                             BNXT_COS_QUEUE_COUNT *
 325                             sizeof(struct bnxt_cos_queue_info),
 326                             0);
 327         if (bp->rx_cos_queue == NULL)
 328                 return -ENOMEM;
 329
 330         bp->tx_cos_queue =
 331                 rte_zmalloc("bnxt_tx_cosq",
 332                             BNXT_COS_QUEUE_COUNT *
 333                             sizeof(struct bnxt_cos_queue_info),
 334                             0);
 335         if (bp->tx_cos_queue == NULL)
 336                 return -ENOMEM;
 337
 338         return 0;
 339 }
 340
 341 static int bnxt_alloc_flow_stats_info(struct bnxt *bp)
 342 {
 343         bp->flow_stat = rte_zmalloc("bnxt_flow_xstat",
 344                                     sizeof(struct bnxt_flow_stat_info), 0);
 345         if (bp->flow_stat == NULL)
 346                 return -ENOMEM;
 347
 348         return 0;
 349 }
 350
 351 static int bnxt_alloc_mem(struct bnxt *bp, bool reconfig)
 352 {
 353         int rc;
 354
 355         rc = bnxt_alloc_ring_grps(bp);
 356         if (rc)
 357                 goto alloc_mem_err;
 358
 359         rc = bnxt_alloc_async_ring_struct(bp);
 360         if (rc)
 361                 goto alloc_mem_err;
 362
 363         rc = bnxt_alloc_vnic_mem(bp);
 364         if (rc)
 365                 goto alloc_mem_err;
 366
 367         rc = bnxt_alloc_vnic_attributes(bp);
 368         if (rc)
 369                 goto alloc_mem_err;
 370
 371         rc = bnxt_alloc_filter_mem(bp);
 372         if (rc)
 373                 goto alloc_mem_err;
 374
 375         rc = bnxt_alloc_async_cp_ring(bp);
 376         if (rc)
 377                 goto alloc_mem_err;
 378
 379         rc = bnxt_alloc_rxtx_nq_ring(bp);
 380         if (rc)
 381                 goto alloc_mem_err;
 382
 383         if (BNXT_FLOW_XSTATS_EN(bp)) {
 384                 rc = bnxt_alloc_flow_stats_info(bp);
 385                 if (rc)
 386                         goto alloc_mem_err;
 387         }
 388
 389         return 0;
 390
 391 alloc_mem_err:
 392         bnxt_free_mem(bp, reconfig);
 393         return rc;
 394 }
 395
 396 static int bnxt_setup_one_vnic(struct bnxt *bp, uint16_t vnic_id)
 397 {
 398         struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
 399         struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id];
 400         uint64_t rx_offloads = dev_conf->rxmode.offloads;
 401         struct bnxt_rx_queue *rxq;
 402         unsigned int j;
 403         int rc;
 404
 405         rc = bnxt_vnic_grp_alloc(bp, vnic);
 406         if (rc)
 407                 goto err_out;
 408
 409         PMD_DRV_LOG(DEBUG, "vnic[%d] = %p vnic->fw_grp_ids = %p\n",
 410                     vnic_id, vnic, vnic->fw_grp_ids);
 411
 412         rc = bnxt_hwrm_vnic_alloc(bp, vnic);
 413         if (rc)
 414                 goto err_out;
 415
 416         /* Alloc RSS context only if RSS mode is enabled */
 417         if (dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS) {
 418                 int j, nr_ctxs = bnxt_rss_ctxts(bp);
 419
 420                 if (bp->rx_nr_rings > BNXT_RSS_TBL_SIZE_P5) {
 421                         PMD_DRV_LOG(ERR, "RxQ cnt %d > reta_size %d\n",
 422                                     bp->rx_nr_rings, BNXT_RSS_TBL_SIZE_P5);
 423                         PMD_DRV_LOG(ERR,
 424                                     "Only queues 0-%d will be in RSS table\n",
 425                                     BNXT_RSS_TBL_SIZE_P5 - 1);
 426                 }
 427
 428                 rc = 0;
 429                 for (j = 0; j < nr_ctxs; j++) {
 430                         rc = bnxt_hwrm_vnic_ctx_alloc(bp, vnic, j);
 431                         if (rc)
 432                                 break;
 433                 }
 434                 if (rc) {
 435                         PMD_DRV_LOG(ERR,
 436                                     "HWRM vnic %d ctx %d alloc failure rc: %x\n",
 437                                     vnic_id, j, rc);
 438                         goto err_out;
 439                 }
 440                 vnic->num_lb_ctxts = nr_ctxs;
 441         }
 442
 443         /*
 444          * Firmware sets pf pair in default vnic cfg. If the VLAN strip
 445          * setting is not available at this time, it will not be
 446          * configured correctly in the CFA.
 447          */
 448         if (rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
 449                 vnic->vlan_strip = true;
 450         else
 451                 vnic->vlan_strip = false;
 452
 453         rc = bnxt_hwrm_vnic_cfg(bp, vnic);
 454         if (rc)
 455                 goto err_out;
 456
 457         rc = bnxt_set_hwrm_vnic_filters(bp, vnic);
 458         if (rc)
 459                 goto err_out;
 460
 461         for (j = 0; j < bp->rx_num_qs_per_vnic; j++) {
 462                 rxq = bp->eth_dev->data->rx_queues[j];
 463
 464                 PMD_DRV_LOG(DEBUG,
 465                             "rxq[%d]->vnic=%p vnic->fw_grp_ids=%p\n",
 466                             j, rxq->vnic, rxq->vnic->fw_grp_ids);
 467
 468                 if (BNXT_HAS_RING_GRPS(bp) && rxq->rx_deferred_start)
 469                         rxq->vnic->fw_grp_ids[j] = INVALID_HW_RING_ID;
 470                 else
 471                         vnic->rx_queue_cnt++;
 472         }
 473
 474         PMD_DRV_LOG(DEBUG, "vnic->rx_queue_cnt = %d\n", vnic->rx_queue_cnt);
 475
 476         rc = bnxt_vnic_rss_configure(bp, vnic);
 477         if (rc)
 478                 goto err_out;
 479
 480         bnxt_hwrm_vnic_plcmode_cfg(bp, vnic);
 481
 482         if (rx_offloads & DEV_RX_OFFLOAD_TCP_LRO)
 483                 bnxt_hwrm_vnic_tpa_cfg(bp, vnic, 1);
 484         else
 485                 bnxt_hwrm_vnic_tpa_cfg(bp, vnic, 0);
 486
 487         return 0;
 488 err_out:
 489         PMD_DRV_LOG(ERR, "HWRM vnic %d cfg failure rc: %x\n",
 490                     vnic_id, rc);
 491         return rc;
 492 }
 493
 494 static int bnxt_register_fc_ctx_mem(struct bnxt *bp)
 495 {
 496         int rc = 0;
 497
 498         rc = bnxt_hwrm_ctx_rgtr(bp, bp->flow_stat->rx_fc_in_tbl.dma,
 499                                 &bp->flow_stat->rx_fc_in_tbl.ctx_id);
 500         if (rc)
 501                 return rc;
 502
 503         PMD_DRV_LOG(DEBUG,
 504                     "rx_fc_in_tbl.va = %p rx_fc_in_tbl.dma = %p"
 505                     " rx_fc_in_tbl.ctx_id = %d\n",
 506                     bp->flow_stat->rx_fc_in_tbl.va,
 507                     (void *)((uintptr_t)bp->flow_stat->rx_fc_in_tbl.dma),
 508                     bp->flow_stat->rx_fc_in_tbl.ctx_id);
 509
 510         rc = bnxt_hwrm_ctx_rgtr(bp, bp->flow_stat->rx_fc_out_tbl.dma,
 511                                 &bp->flow_stat->rx_fc_out_tbl.ctx_id);
 512         if (rc)
 513                 return rc;
 514
 515         PMD_DRV_LOG(DEBUG,
 516                     "rx_fc_out_tbl.va = %p rx_fc_out_tbl.dma = %p"
 517                     " rx_fc_out_tbl.ctx_id = %d\n",
 518                     bp->flow_stat->rx_fc_out_tbl.va,
 519                     (void *)((uintptr_t)bp->flow_stat->rx_fc_out_tbl.dma),
 520                     bp->flow_stat->rx_fc_out_tbl.ctx_id);
 521
 522         rc = bnxt_hwrm_ctx_rgtr(bp, bp->flow_stat->tx_fc_in_tbl.dma,
 523                                 &bp->flow_stat->tx_fc_in_tbl.ctx_id);
 524         if (rc)
 525                 return rc;
 526
 527         PMD_DRV_LOG(DEBUG,
 528                     "tx_fc_in_tbl.va = %p tx_fc_in_tbl.dma = %p"
 529                     " tx_fc_in_tbl.ctx_id = %d\n",
 530                     bp->flow_stat->tx_fc_in_tbl.va,
 531                     (void *)((uintptr_t)bp->flow_stat->tx_fc_in_tbl.dma),
 532                     bp->flow_stat->tx_fc_in_tbl.ctx_id);
 533
 534         rc = bnxt_hwrm_ctx_rgtr(bp, bp->flow_stat->tx_fc_out_tbl.dma,
 535                                 &bp->flow_stat->tx_fc_out_tbl.ctx_id);
 536         if (rc)
 537                 return rc;
 538
 539         PMD_DRV_LOG(DEBUG,
 540                     "tx_fc_out_tbl.va = %p tx_fc_out_tbl.dma = %p"
 541                     " tx_fc_out_tbl.ctx_id = %d\n",
 542                     bp->flow_stat->tx_fc_out_tbl.va,
 543                     (void *)((uintptr_t)bp->flow_stat->tx_fc_out_tbl.dma),
 544                     bp->flow_stat->tx_fc_out_tbl.ctx_id);
 545
 546         memset(bp->flow_stat->rx_fc_out_tbl.va,
 547                0,
 548                bp->flow_stat->rx_fc_out_tbl.size);
 549         rc = bnxt_hwrm_cfa_counter_cfg(bp, BNXT_DIR_RX,
 550                                        CFA_COUNTER_CFG_IN_COUNTER_TYPE_FC,
 551                                        bp->flow_stat->rx_fc_out_tbl.ctx_id,
 552                                        bp->flow_stat->max_fc,
 553                                        true);
 554         if (rc)
 555                 return rc;
 556
 557         memset(bp->flow_stat->tx_fc_out_tbl.va,
 558                0,
 559                bp->flow_stat->tx_fc_out_tbl.size);
 560         rc = bnxt_hwrm_cfa_counter_cfg(bp, BNXT_DIR_TX,
 561                                        CFA_COUNTER_CFG_IN_COUNTER_TYPE_FC,
 562                                        bp->flow_stat->tx_fc_out_tbl.ctx_id,
 563                                        bp->flow_stat->max_fc,
 564                                        true);
 565
 566         return rc;
 567 }
 568
 569 static int bnxt_alloc_ctx_mem_buf(char *type, size_t size,
 570                                   struct bnxt_ctx_mem_buf_info *ctx)
 571 {
 572         if (!ctx)
 573                 return -EINVAL;
 574
 575         ctx->va = rte_zmalloc(type, size, 0);
 576         if (ctx->va == NULL)
 577                 return -ENOMEM;
 578         rte_mem_lock_page(ctx->va);
 579         ctx->size = size;
 580         ctx->dma = rte_mem_virt2iova(ctx->va);
 581         if (ctx->dma == RTE_BAD_IOVA)
 582                 return -ENOMEM;
 583
 584         return 0;
 585 }
 586
 587 static int bnxt_init_fc_ctx_mem(struct bnxt *bp)
 588 {
 589         struct rte_pci_device *pdev = bp->pdev;
 590         char type[RTE_MEMZONE_NAMESIZE];
 591         uint16_t max_fc;
 592         int rc = 0;
 593
 594         max_fc = bp->flow_stat->max_fc;
 595
 596         sprintf(type, "bnxt_rx_fc_in_" PCI_PRI_FMT, pdev->addr.domain,
 597                 pdev->addr.bus, pdev->addr.devid, pdev->addr.function);
 598         /* 4 bytes for each counter-id */
 599         rc = bnxt_alloc_ctx_mem_buf(type,
 600                                     max_fc * 4,
 601                                     &bp->flow_stat->rx_fc_in_tbl);
 602         if (rc)
 603                 return rc;
 604
 605         sprintf(type, "bnxt_rx_fc_out_" PCI_PRI_FMT, pdev->addr.domain,
 606                 pdev->addr.bus, pdev->addr.devid, pdev->addr.function);
 607         /* 16 bytes for each counter - 8 bytes pkt_count, 8 bytes byte_count */
 608         rc = bnxt_alloc_ctx_mem_buf(type,
 609                                     max_fc * 16,
 610                                     &bp->flow_stat->rx_fc_out_tbl);
 611         if (rc)
 612                 return rc;
 613
 614         sprintf(type, "bnxt_tx_fc_in_" PCI_PRI_FMT, pdev->addr.domain,
 615                 pdev->addr.bus, pdev->addr.devid, pdev->addr.function);
 616         /* 4 bytes for each counter-id */
 617         rc = bnxt_alloc_ctx_mem_buf(type,
 618                                     max_fc * 4,
 619                                     &bp->flow_stat->tx_fc_in_tbl);
 620         if (rc)
 621                 return rc;
 622
 623         sprintf(type, "bnxt_tx_fc_out_" PCI_PRI_FMT, pdev->addr.domain,
 624                 pdev->addr.bus, pdev->addr.devid, pdev->addr.function);
 625         /* 16 bytes for each counter - 8 bytes pkt_count, 8 bytes byte_count */
 626         rc = bnxt_alloc_ctx_mem_buf(type,
 627                                     max_fc * 16,
 628                                     &bp->flow_stat->tx_fc_out_tbl);
 629         if (rc)
 630                 return rc;
 631
 632         rc = bnxt_register_fc_ctx_mem(bp);
 633
 634         return rc;
 635 }
 636
 637 static int bnxt_init_ctx_mem(struct bnxt *bp)
 638 {
 639         int rc = 0;
 640
 641         if (!(bp->fw_cap & BNXT_FW_CAP_ADV_FLOW_COUNTERS) ||
 642             !(BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp)) ||
 643             !BNXT_FLOW_XSTATS_EN(bp))
 644                 return 0;
 645
 646         rc = bnxt_hwrm_cfa_counter_qcaps(bp, &bp->flow_stat->max_fc);
 647         if (rc)
 648                 return rc;
 649
 650         rc = bnxt_init_fc_ctx_mem(bp);
 651
 652         return rc;
 653 }
 654
 655 static int bnxt_update_phy_setting(struct bnxt *bp)
 656 {
 657         struct rte_eth_link new;
 658         int rc;
 659
 660         rc = bnxt_get_hwrm_link_config(bp, &new);
 661         if (rc) {
 662                 PMD_DRV_LOG(ERR, "Failed to get link settings\n");
 663                 return rc;
 664         }
 665
 666         /*
 667          * On BCM957508-N2100 adapters, FW will not allow any user other
 668          * than BMC to shutdown the port. bnxt_get_hwrm_link_config() call
 669          * always returns link up. Force phy update always in that case.
 670          */
 671         if (!new.link_status || IS_BNXT_DEV_957508_N2100(bp)) {
 672                 rc = bnxt_set_hwrm_link_config(bp, true);
 673                 if (rc) {
 674                         PMD_DRV_LOG(ERR, "Failed to update PHY settings\n");
 675                         return rc;
 676                 }
 677         }
 678
 679         return rc;
 680 }
 681
 682 static int bnxt_start_nic(struct bnxt *bp)
 683 {
 684         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(bp->eth_dev);
 685         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
 686         uint32_t intr_vector = 0;
 687         uint32_t queue_id, base = BNXT_MISC_VEC_ID;
 688         uint32_t vec = BNXT_MISC_VEC_ID;
 689         unsigned int i, j;
 690         int rc;
 691
 692         if (bp->eth_dev->data->mtu > RTE_ETHER_MTU) {
 693                 bp->eth_dev->data->dev_conf.rxmode.offloads |=
 694                         DEV_RX_OFFLOAD_JUMBO_FRAME;
 695                 bp->flags |= BNXT_FLAG_JUMBO;
 696         } else {
 697                 bp->eth_dev->data->dev_conf.rxmode.offloads &=
 698                         ~DEV_RX_OFFLOAD_JUMBO_FRAME;
 699                 bp->flags &= ~BNXT_FLAG_JUMBO;
 700         }
 701
 702         /* THOR does not support ring groups.
 703          * But we will use the array to save RSS context IDs.
 704          */
 705         if (BNXT_CHIP_P5(bp))
 706                 bp->max_ring_grps = BNXT_MAX_RSS_CTXTS_P5;
 707
 708         rc = bnxt_alloc_all_hwrm_stat_ctxs(bp);
 709         if (rc) {
 710                 PMD_DRV_LOG(ERR, "HWRM stat ctx alloc failure rc: %x\n", rc);
 711                 goto err_out;
 712         }
 713
 714         rc = bnxt_alloc_hwrm_rings(bp);
 715         if (rc) {
 716                 PMD_DRV_LOG(ERR, "HWRM ring alloc failure rc: %x\n", rc);
 717                 goto err_out;
 718         }
 719
 720         rc = bnxt_alloc_all_hwrm_ring_grps(bp);
 721         if (rc) {
 722                 PMD_DRV_LOG(ERR, "HWRM ring grp alloc failure: %x\n", rc);
 723                 goto err_out;
 724         }
 725
 726         if (!(bp->vnic_cap_flags & BNXT_VNIC_CAP_COS_CLASSIFY))
 727                 goto skip_cosq_cfg;
 728
 729         for (j = 0, i = 0; i < BNXT_COS_QUEUE_COUNT; i++) {
 730                 if (bp->rx_cos_queue[i].id != 0xff) {
 731                         struct bnxt_vnic_info *vnic = &bp->vnic_info[j++];
 732
 733                         if (!vnic) {
 734                                 PMD_DRV_LOG(ERR,
 735                                             "Num pools more than FW profile\n");
 736                                 rc = -EINVAL;
 737                                 goto err_out;
 738                         }
 739                         vnic->cos_queue_id = bp->rx_cos_queue[i].id;
 740                         bp->rx_cosq_cnt++;
 741                 }
 742         }
 743
 744 skip_cosq_cfg:
 745         rc = bnxt_mq_rx_configure(bp);
 746         if (rc) {
 747                 PMD_DRV_LOG(ERR, "MQ mode configure failure rc: %x\n", rc);
 748                 goto err_out;
 749         }
 750
 751         /* default vnic 0 */
 752         rc = bnxt_setup_one_vnic(bp, 0);
 753         if (rc)
 754                 goto err_out;
 755         /* VNIC configuration */
 756         if (BNXT_RFS_NEEDS_VNIC(bp)) {
 757                 for (i = 1; i < bp->nr_vnics; i++) {
 758                         rc = bnxt_setup_one_vnic(bp, i);
 759                         if (rc)
 760                                 goto err_out;
 761                 }
 762         }
 763
 764         rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, &bp->vnic_info[0], 0, NULL);
 765         if (rc) {
 766                 PMD_DRV_LOG(ERR,
 767                         "HWRM cfa l2 rx mask failure rc: %x\n", rc);
 768                 goto err_out;
 769         }
 770
 771         /* check and configure queue intr-vector mapping */
 772         if ((rte_intr_cap_multiple(intr_handle) ||
 773              !RTE_ETH_DEV_SRIOV(bp->eth_dev).active) &&
 774             bp->eth_dev->data->dev_conf.intr_conf.rxq != 0) {
 775                 intr_vector = bp->eth_dev->data->nb_rx_queues;
 776                 PMD_DRV_LOG(DEBUG, "intr_vector = %d\n", intr_vector);
 777                 if (intr_vector > bp->rx_cp_nr_rings) {
 778                         PMD_DRV_LOG(ERR, "At most %d intr queues supported",
 779                                         bp->rx_cp_nr_rings);
 780                         return -ENOTSUP;
 781                 }
 782                 rc = rte_intr_efd_enable(intr_handle, intr_vector);
 783                 if (rc)
 784                         return rc;
 785         }
 786
 787         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
 788                 intr_handle->intr_vec =
 789                         rte_zmalloc("intr_vec",
 790                                     bp->eth_dev->data->nb_rx_queues *
 791                                     sizeof(int), 0);
 792                 if (intr_handle->intr_vec == NULL) {
 793                         PMD_DRV_LOG(ERR, "Failed to allocate %d rx_queues"
 794                                 " intr_vec", bp->eth_dev->data->nb_rx_queues);
 795                         rc = -ENOMEM;
 796                         goto err_disable;
 797                 }
 798                 PMD_DRV_LOG(DEBUG, "intr_handle->intr_vec = %p "
 799                         "intr_handle->nb_efd = %d intr_handle->max_intr = %d\n",
 800                          intr_handle->intr_vec, intr_handle->nb_efd,
 801                         intr_handle->max_intr);
 802                 for (queue_id = 0; queue_id < bp->eth_dev->data->nb_rx_queues;
 803                      queue_id++) {
 804                         intr_handle->intr_vec[queue_id] =
 805                                                         vec + BNXT_RX_VEC_START;
 806                         if (vec < base + intr_handle->nb_efd - 1)
 807                                 vec++;
 808                 }
 809         }
 810
 811         /* enable uio/vfio intr/eventfd mapping */
 812         rc = rte_intr_enable(intr_handle);
 813 #ifndef RTE_EXEC_ENV_FREEBSD
 814         /* In FreeBSD OS, nic_uio driver does not support interrupts */
 815         if (rc)
 816                 goto err_free;
 817 #endif
 818
 819         rc = bnxt_update_phy_setting(bp);
 820         if (rc)
 821                 goto err_free;
 822
 823         bp->mark_table = rte_zmalloc("bnxt_mark_table", BNXT_MARK_TABLE_SZ, 0);
 824         if (!bp->mark_table)
 825                 PMD_DRV_LOG(ERR, "Allocation of mark table failed\n");
 826
 827         return 0;
 828
 829 err_free:
 830         rte_free(intr_handle->intr_vec);
 831 err_disable:
 832         rte_intr_efd_disable(intr_handle);
 833 err_out:
 834         /* Some of the error status returned by FW may not be from errno.h */
 835         if (rc > 0)
 836                 rc = -EIO;
 837
 838         return rc;
 839 }
 840
 841 static int bnxt_shutdown_nic(struct bnxt *bp)
 842 {
 843         bnxt_free_all_hwrm_resources(bp);
 844         bnxt_free_all_filters(bp);
 845         bnxt_free_all_vnics(bp);
 846         return 0;
 847 }
 848
 849 /*
 850  * Device configuration and status function
 851  */
 852
 853 uint32_t bnxt_get_speed_capabilities(struct bnxt *bp)
 854 {
 855         uint32_t link_speed = bp->link_info->support_speeds;
 856         uint32_t speed_capa = 0;
 857
 858         /* If PAM4 is configured, use PAM4 supported speed */
 859         if (link_speed == 0 && bp->link_info->support_pam4_speeds > 0)
 860                 link_speed = bp->link_info->support_pam4_speeds;
 861
 862         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_100MB)
 863                 speed_capa |= ETH_LINK_SPEED_100M;
 864         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_100MBHD)
 865                 speed_capa |= ETH_LINK_SPEED_100M_HD;
 866         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_1GB)
 867                 speed_capa |= ETH_LINK_SPEED_1G;
 868         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_2_5GB)
 869                 speed_capa |= ETH_LINK_SPEED_2_5G;
 870         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_10GB)
 871                 speed_capa |= ETH_LINK_SPEED_10G;
 872         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_20GB)
 873                 speed_capa |= ETH_LINK_SPEED_20G;
 874         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_25GB)
 875                 speed_capa |= ETH_LINK_SPEED_25G;
 876         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_40GB)
 877                 speed_capa |= ETH_LINK_SPEED_40G;
 878         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_50GB)
 879                 speed_capa |= ETH_LINK_SPEED_50G;
 880         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_100GB)
 881                 speed_capa |= ETH_LINK_SPEED_100G;
 882         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_PAM4_SPEEDS_50G)
 883                 speed_capa |= ETH_LINK_SPEED_50G;
 884         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_PAM4_SPEEDS_100G)
 885                 speed_capa |= ETH_LINK_SPEED_100G;
 886         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_PAM4_SPEEDS_200G)
 887                 speed_capa |= ETH_LINK_SPEED_200G;
 888
 889         if (bp->link_info->auto_mode ==
 890             HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_MODE_NONE)
 891                 speed_capa |= ETH_LINK_SPEED_FIXED;
 892         else
 893                 speed_capa |= ETH_LINK_SPEED_AUTONEG;
 894
 895         return speed_capa;
 896 }
 897
 898 static int bnxt_dev_info_get_op(struct rte_eth_dev *eth_dev,
 899                                 struct rte_eth_dev_info *dev_info)
 900 {
 901         struct rte_pci_device *pdev = RTE_DEV_TO_PCI(eth_dev->device);
 902         struct bnxt *bp = eth_dev->data->dev_private;
 903         uint16_t max_vnics, i, j, vpool, vrxq;
 904         unsigned int max_rx_rings;
 905         int rc;
 906
 907         rc = is_bnxt_in_error(bp);
 908         if (rc)
 909                 return rc;
 910
 911         /* MAC Specifics */
 912         dev_info->max_mac_addrs = bp->max_l2_ctx;
 913         dev_info->max_hash_mac_addrs = 0;
 914
 915         /* PF/VF specifics */
 916         if (BNXT_PF(bp))
 917                 dev_info->max_vfs = pdev->max_vfs;
 918
 919         max_rx_rings = bnxt_max_rings(bp);
 920         /* For the sake of symmetry, max_rx_queues = max_tx_queues */
 921         dev_info->max_rx_queues = max_rx_rings;
 922         dev_info->max_tx_queues = max_rx_rings;
 923         dev_info->reta_size = bnxt_rss_hash_tbl_size(bp);
 924         dev_info->hash_key_size = 40;
 925         max_vnics = bp->max_vnics;
 926
 927         /* MTU specifics */
 928         dev_info->min_mtu = RTE_ETHER_MIN_MTU;
 929         dev_info->max_mtu = BNXT_MAX_MTU;
 930
 931         /* Fast path specifics */
 932         dev_info->min_rx_bufsize = 1;
 933         dev_info->max_rx_pktlen = BNXT_MAX_PKT_LEN;
 934
 935         dev_info->rx_offload_capa = BNXT_DEV_RX_OFFLOAD_SUPPORT;
 936         if (bp->flags & BNXT_FLAG_PTP_SUPPORTED)
 937                 dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_TIMESTAMP;
 938         dev_info->tx_queue_offload_capa = DEV_TX_OFFLOAD_MBUF_FAST_FREE;
 939         dev_info->tx_offload_capa = BNXT_DEV_TX_OFFLOAD_SUPPORT |
 940                                     dev_info->tx_queue_offload_capa;
 941         dev_info->flow_type_rss_offloads = BNXT_ETH_RSS_SUPPORT;
 942
 943         dev_info->speed_capa = bnxt_get_speed_capabilities(bp);
 944
 945         /* *INDENT-OFF* */
 946         dev_info->default_rxconf = (struct rte_eth_rxconf) {
 947                 .rx_thresh = {
 948                         .pthresh = 8,
 949                         .hthresh = 8,
 950                         .wthresh = 0,
 951                 },
 952                 .rx_free_thresh = 32,
 953                 .rx_drop_en = BNXT_DEFAULT_RX_DROP_EN,
 954         };
 955
 956         dev_info->default_txconf = (struct rte_eth_txconf) {
 957                 .tx_thresh = {
 958                         .pthresh = 32,
 959                         .hthresh = 0,
 960                         .wthresh = 0,
 961                 },
 962                 .tx_free_thresh = 32,
 963                 .tx_rs_thresh = 32,
 964         };
 965         eth_dev->data->dev_conf.intr_conf.lsc = 1;
 966
 967         eth_dev->data->dev_conf.intr_conf.rxq = 1;
 968         dev_info->rx_desc_lim.nb_min = BNXT_MIN_RING_DESC;
 969         dev_info->rx_desc_lim.nb_max = BNXT_MAX_RX_RING_DESC;
 970         dev_info->tx_desc_lim.nb_min = BNXT_MIN_RING_DESC;
 971         dev_info->tx_desc_lim.nb_max = BNXT_MAX_TX_RING_DESC;
 972
 973         if (BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp)) {
 974                 dev_info->switch_info.name = eth_dev->device->name;
 975                 dev_info->switch_info.domain_id = bp->switch_domain_id;
 976                 dev_info->switch_info.port_id =
 977                                 BNXT_PF(bp) ? BNXT_SWITCH_PORT_ID_PF :
 978                                     BNXT_SWITCH_PORT_ID_TRUSTED_VF;
 979         }
 980
 981         /* *INDENT-ON* */
 982
 983         /*
 984          * TODO: default_rxconf, default_txconf, rx_desc_lim, and tx_desc_lim
 985          *       need further investigation.
 986          */
 987
 988         /* VMDq resources */
 989         vpool = 64; /* ETH_64_POOLS */
 990         vrxq = 128; /* ETH_VMDQ_DCB_NUM_QUEUES */
 991         for (i = 0; i < 4; vpool >>= 1, i++) {
 992                 if (max_vnics > vpool) {
 993                         for (j = 0; j < 5; vrxq >>= 1, j++) {
 994                                 if (dev_info->max_rx_queues > vrxq) {
 995                                         if (vpool > vrxq)
 996                                                 vpool = vrxq;
 997                                         goto found;
 998                                 }
 999                         }
1000                         /* Not enough resources to support VMDq */
1001                         break;
1002                 }
1003         }
1004         /* Not enough resources to support VMDq */
1005         vpool = 0;
1006         vrxq = 0;
1007 found:
1008         dev_info->max_vmdq_pools = vpool;
1009         dev_info->vmdq_queue_num = vrxq;
1010
1011         dev_info->vmdq_pool_base = 0;
1012         dev_info->vmdq_queue_base = 0;
1013
1014         return 0;
1015 }
1016
1017 /* Configure the device based on the configuration provided */
1018 static int bnxt_dev_configure_op(struct rte_eth_dev *eth_dev)
1019 {
1020         struct bnxt *bp = eth_dev->data->dev_private;
1021         uint64_t rx_offloads = eth_dev->data->dev_conf.rxmode.offloads;
1022         int rc;
1023
1024         bp->rx_queues = (void *)eth_dev->data->rx_queues;
1025         bp->tx_queues = (void *)eth_dev->data->tx_queues;
1026         bp->tx_nr_rings = eth_dev->data->nb_tx_queues;
1027         bp->rx_nr_rings = eth_dev->data->nb_rx_queues;
1028
1029         rc = is_bnxt_in_error(bp);
1030         if (rc)
1031                 return rc;
1032
1033         if (BNXT_VF(bp) && (bp->flags & BNXT_FLAG_NEW_RM)) {
1034                 rc = bnxt_hwrm_check_vf_rings(bp);
1035                 if (rc) {
1036                         PMD_DRV_LOG(ERR, "HWRM insufficient resources\n");
1037                         return -ENOSPC;
1038                 }
1039
1040                 /* If a resource has already been allocated - in this case
1041                  * it is the async completion ring, free it. Reallocate it after
1042                  * resource reservation. This will ensure the resource counts
1043                  * are calculated correctly.
1044                  */
1045
1046                 pthread_mutex_lock(&bp->def_cp_lock);
1047
1048                 if (!BNXT_HAS_NQ(bp) && bp->async_cp_ring) {
1049                         bnxt_disable_int(bp);
1050                         bnxt_free_cp_ring(bp, bp->async_cp_ring);
1051                 }
1052
1053                 rc = bnxt_hwrm_func_reserve_vf_resc(bp, false);
1054                 if (rc) {
1055                         PMD_DRV_LOG(ERR, "HWRM resource alloc fail:%x\n", rc);
1056                         pthread_mutex_unlock(&bp->def_cp_lock);
1057                         return -ENOSPC;
1058                 }
1059
1060                 if (!BNXT_HAS_NQ(bp) && bp->async_cp_ring) {
1061                         rc = bnxt_alloc_async_cp_ring(bp);
1062                         if (rc) {
1063                                 pthread_mutex_unlock(&bp->def_cp_lock);
1064                                 return rc;
1065                         }
1066                         bnxt_enable_int(bp);
1067                 }
1068
1069                 pthread_mutex_unlock(&bp->def_cp_lock);
1070         }
1071
1072         /* Inherit new configurations */
1073         if (eth_dev->data->nb_rx_queues > bp->max_rx_rings ||
1074             eth_dev->data->nb_tx_queues > bp->max_tx_rings ||
1075             eth_dev->data->nb_rx_queues + eth_dev->data->nb_tx_queues
1076                 + BNXT_NUM_ASYNC_CPR(bp) > bp->max_cp_rings ||
1077             eth_dev->data->nb_rx_queues + eth_dev->data->nb_tx_queues >
1078             bp->max_stat_ctx)
1079                 goto resource_error;
1080
1081         if (BNXT_HAS_RING_GRPS(bp) &&
1082             (uint32_t)(eth_dev->data->nb_rx_queues) > bp->max_ring_grps)
1083                 goto resource_error;
1084
1085         if (!(eth_dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_RSS) &&
1086             bp->max_vnics < eth_dev->data->nb_rx_queues)
1087                 goto resource_error;
1088
1089         bp->rx_cp_nr_rings = bp->rx_nr_rings;
1090         bp->tx_cp_nr_rings = bp->tx_nr_rings;
1091
1092         if (eth_dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG)
1093                 rx_offloads |= DEV_RX_OFFLOAD_RSS_HASH;
1094         eth_dev->data->dev_conf.rxmode.offloads = rx_offloads;
1095
1096         if (rx_offloads & DEV_RX_OFFLOAD_JUMBO_FRAME) {
1097                 eth_dev->data->mtu =
1098                         eth_dev->data->dev_conf.rxmode.max_rx_pkt_len -
1099                         RTE_ETHER_HDR_LEN - RTE_ETHER_CRC_LEN - VLAN_TAG_SIZE *
1100                         BNXT_NUM_VLANS;
1101                 bnxt_mtu_set_op(eth_dev, eth_dev->data->mtu);
1102         }
1103         return 0;
1104
1105 resource_error:
1106         PMD_DRV_LOG(ERR,
1107                     "Insufficient resources to support requested config\n");
1108         PMD_DRV_LOG(ERR,
1109                     "Num Queues Requested: Tx %d, Rx %d\n",
1110                     eth_dev->data->nb_tx_queues,
1111                     eth_dev->data->nb_rx_queues);
1112         PMD_DRV_LOG(ERR,
1113                     "MAX: TxQ %d, RxQ %d, CQ %d Stat %d, Grp %d, Vnic %d\n",
1114                     bp->max_tx_rings, bp->max_rx_rings, bp->max_cp_rings,
1115                     bp->max_stat_ctx, bp->max_ring_grps, bp->max_vnics);
1116         return -ENOSPC;
1117 }
1118
1119 void bnxt_print_link_info(struct rte_eth_dev *eth_dev)
1120 {
1121         struct rte_eth_link *link = &eth_dev->data->dev_link;
1122
1123         if (link->link_status)
1124                 PMD_DRV_LOG(INFO, "Port %d Link Up - speed %u Mbps - %s\n",
1125                         eth_dev->data->port_id,
1126                         (uint32_t)link->link_speed,
1127                         (link->link_duplex == ETH_LINK_FULL_DUPLEX) ?
1128                         ("full-duplex") : ("half-duplex\n"));
1129         else
1130                 PMD_DRV_LOG(INFO, "Port %d Link Down\n",
1131                         eth_dev->data->port_id);
1132 }
1133
1134 /*
1135  * Determine whether the current configuration requires support for scattered
1136  * receive; return 1 if scattered receive is required and 0 if not.
1137  */
1138 static int bnxt_scattered_rx(struct rte_eth_dev *eth_dev)
1139 {
1140         uint16_t buf_size;
1141         int i;
1142
1143         if (eth_dev->data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_SCATTER)
1144                 return 1;
1145
1146         if (eth_dev->data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_TCP_LRO)
1147                 return 1;
1148
1149         for (i = 0; i < eth_dev->data->nb_rx_queues; i++) {
1150                 struct bnxt_rx_queue *rxq = eth_dev->data->rx_queues[i];
1151
1152                 buf_size = (uint16_t)(rte_pktmbuf_data_room_size(rxq->mb_pool) -
1153                                       RTE_PKTMBUF_HEADROOM);
1154                 if (eth_dev->data->dev_conf.rxmode.max_rx_pkt_len > buf_size)
1155                         return 1;
1156         }
1157         return 0;
1158 }
1159
1160 static eth_rx_burst_t
1161 bnxt_receive_function(struct rte_eth_dev *eth_dev)
1162 {
1163         struct bnxt *bp = eth_dev->data->dev_private;
1164
1165         /* Disable vector mode RX for Stingray2 for now */
1166         if (BNXT_CHIP_SR2(bp)) {
1167                 bp->flags &= ~BNXT_FLAG_RX_VECTOR_PKT_MODE;
1168                 return bnxt_recv_pkts;
1169         }
1170
1171 #if defined(RTE_ARCH_X86) || defined(RTE_ARCH_ARM64)
1172 #ifndef RTE_LIBRTE_IEEE1588
1173         /*
1174          * Vector mode receive can be enabled only if scatter rx is not
1175          * in use and rx offloads are limited to VLAN stripping and
1176          * CRC stripping.
1177          */
1178         if (!eth_dev->data->scattered_rx &&
1179             !(eth_dev->data->dev_conf.rxmode.offloads &
1180               ~(DEV_RX_OFFLOAD_VLAN_STRIP |
1181                 DEV_RX_OFFLOAD_KEEP_CRC |
1182                 DEV_RX_OFFLOAD_JUMBO_FRAME |
1183                 DEV_RX_OFFLOAD_IPV4_CKSUM |
1184                 DEV_RX_OFFLOAD_UDP_CKSUM |
1185                 DEV_RX_OFFLOAD_TCP_CKSUM |
1186                 DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM |
1187                 DEV_RX_OFFLOAD_OUTER_UDP_CKSUM |
1188                 DEV_RX_OFFLOAD_RSS_HASH |
1189                 DEV_RX_OFFLOAD_VLAN_FILTER)) &&
1190             !BNXT_TRUFLOW_EN(bp) && BNXT_NUM_ASYNC_CPR(bp) &&
1191             rte_vect_get_max_simd_bitwidth() >= RTE_VECT_SIMD_128) {
1192                 PMD_DRV_LOG(INFO, "Using vector mode receive for port %d\n",
1193                             eth_dev->data->port_id);
1194                 bp->flags |= BNXT_FLAG_RX_VECTOR_PKT_MODE;
1195                 return bnxt_recv_pkts_vec;
1196         }
1197         PMD_DRV_LOG(INFO, "Vector mode receive disabled for port %d\n",
1198                     eth_dev->data->port_id);
1199         PMD_DRV_LOG(INFO,
1200                     "Port %d scatter: %d rx offload: %" PRIX64 "\n",
1201                     eth_dev->data->port_id,
1202                     eth_dev->data->scattered_rx,
1203                     eth_dev->data->dev_conf.rxmode.offloads);
1204 #endif
1205 #endif
1206         bp->flags &= ~BNXT_FLAG_RX_VECTOR_PKT_MODE;
1207         return bnxt_recv_pkts;
1208 }
1209
1210 static eth_tx_burst_t
1211 bnxt_transmit_function(struct rte_eth_dev *eth_dev)
1212 {
1213         struct bnxt *bp = eth_dev->data->dev_private;
1214
1215         /* Disable vector mode TX for Stingray2 for now */
1216         if (BNXT_CHIP_SR2(bp))
1217                 return bnxt_xmit_pkts;
1218
1219 #if defined(RTE_ARCH_X86) || defined(RTE_ARCH_ARM64)
1220 #ifndef RTE_LIBRTE_IEEE1588
1221         uint64_t offloads = eth_dev->data->dev_conf.txmode.offloads;
1222
1223         /*
1224          * Vector mode transmit can be enabled only if not using scatter rx
1225          * or tx offloads.
1226          */
1227         if (!eth_dev->data->scattered_rx &&
1228             !(offloads & ~DEV_TX_OFFLOAD_MBUF_FAST_FREE) &&
1229             !BNXT_TRUFLOW_EN(bp) &&
1230             rte_vect_get_max_simd_bitwidth() >= RTE_VECT_SIMD_128) {
1231                 PMD_DRV_LOG(INFO, "Using vector mode transmit for port %d\n",
1232                             eth_dev->data->port_id);
1233                 return bnxt_xmit_pkts_vec;
1234         }
1235         PMD_DRV_LOG(INFO, "Vector mode transmit disabled for port %d\n",
1236                     eth_dev->data->port_id);
1237         PMD_DRV_LOG(INFO,
1238                     "Port %d scatter: %d tx offload: %" PRIX64 "\n",
1239                     eth_dev->data->port_id,
1240                     eth_dev->data->scattered_rx,
1241                     offloads);
1242 #endif
1243 #endif
1244         return bnxt_xmit_pkts;
1245 }
1246
1247 static int bnxt_handle_if_change_status(struct bnxt *bp)
1248 {
1249         int rc;
1250
1251         /* Since fw has undergone a reset and lost all contexts,
1252          * set fatal flag to not issue hwrm during cleanup
1253          */
1254         bp->flags |= BNXT_FLAG_FATAL_ERROR;
1255         bnxt_uninit_resources(bp, true);
1256
1257         /* clear fatal flag so that re-init happens */
1258         bp->flags &= ~BNXT_FLAG_FATAL_ERROR;
1259         rc = bnxt_init_resources(bp, true);
1260
1261         bp->flags &= ~BNXT_FLAG_IF_CHANGE_HOT_FW_RESET_DONE;
1262
1263         return rc;
1264 }
1265
1266 static int bnxt_dev_set_link_up_op(struct rte_eth_dev *eth_dev)
1267 {
1268         struct bnxt *bp = eth_dev->data->dev_private;
1269         int rc = 0;
1270
1271         if (!bp->link_info->link_up)
1272                 rc = bnxt_set_hwrm_link_config(bp, true);
1273         if (!rc)
1274                 eth_dev->data->dev_link.link_status = 1;
1275
1276         bnxt_print_link_info(eth_dev);
1277         return rc;
1278 }
1279
1280 static int bnxt_dev_set_link_down_op(struct rte_eth_dev *eth_dev)
1281 {
1282         struct bnxt *bp = eth_dev->data->dev_private;
1283
1284         eth_dev->data->dev_link.link_status = 0;
1285         bnxt_set_hwrm_link_config(bp, false);
1286         bp->link_info->link_up = 0;
1287
1288         return 0;
1289 }
1290
1291 static void bnxt_free_switch_domain(struct bnxt *bp)
1292 {
1293         int rc = 0;
1294
1295         if (bp->switch_domain_id) {
1296                 rc = rte_eth_switch_domain_free(bp->switch_domain_id);
1297                 if (rc)
1298                         PMD_DRV_LOG(ERR, "free switch domain:%d fail: %d\n",
1299                                     bp->switch_domain_id, rc);
1300         }
1301 }
1302
1303 static void bnxt_ptp_get_current_time(void *arg)
1304 {
1305         struct bnxt *bp = arg;
1306         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
1307         int rc;
1308
1309         rc = is_bnxt_in_error(bp);
1310         if (rc)
1311                 return;
1312
1313         if (!ptp)
1314                 return;
1315
1316         bnxt_hwrm_port_ts_query(bp, BNXT_PTP_FLAGS_CURRENT_TIME,
1317                                 &ptp->current_time);
1318
1319         rc = rte_eal_alarm_set(US_PER_S, bnxt_ptp_get_current_time, (void *)bp);
1320         if (rc != 0) {
1321                 PMD_DRV_LOG(ERR, "Failed to re-schedule PTP alarm\n");
1322                 bp->flags2 &= ~BNXT_FLAGS2_PTP_ALARM_SCHEDULED;
1323         }
1324 }
1325
1326 static int bnxt_schedule_ptp_alarm(struct bnxt *bp)
1327 {
1328         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
1329         int rc;
1330
1331         if (bp->flags2 & BNXT_FLAGS2_PTP_ALARM_SCHEDULED)
1332                 return 0;
1333
1334         bnxt_hwrm_port_ts_query(bp, BNXT_PTP_FLAGS_CURRENT_TIME,
1335                                 &ptp->current_time);
1336
1337         rc = rte_eal_alarm_set(US_PER_S, bnxt_ptp_get_current_time, (void *)bp);
1338         return rc;
1339 }
1340
1341 static void bnxt_cancel_ptp_alarm(struct bnxt *bp)
1342 {
1343         if (bp->flags2 & BNXT_FLAGS2_PTP_ALARM_SCHEDULED) {
1344                 rte_eal_alarm_cancel(bnxt_ptp_get_current_time, (void *)bp);
1345                 bp->flags2 &= ~BNXT_FLAGS2_PTP_ALARM_SCHEDULED;
1346         }
1347 }
1348
1349 static void bnxt_ptp_stop(struct bnxt *bp)
1350 {
1351         bnxt_cancel_ptp_alarm(bp);
1352         bp->flags2 &= ~BNXT_FLAGS2_PTP_TIMESYNC_ENABLED;
1353 }
1354
1355 static int bnxt_ptp_start(struct bnxt *bp)
1356 {
1357         int rc;
1358
1359         rc = bnxt_schedule_ptp_alarm(bp);
1360         if (rc != 0) {
1361                 PMD_DRV_LOG(ERR, "Failed to schedule PTP alarm\n");
1362         } else {
1363                 bp->flags2 |= BNXT_FLAGS2_PTP_TIMESYNC_ENABLED;
1364                 bp->flags2 |= BNXT_FLAGS2_PTP_ALARM_SCHEDULED;
1365         }
1366
1367         return rc;
1368 }
1369
1370 static int bnxt_dev_stop(struct rte_eth_dev *eth_dev)
1371 {
1372         struct bnxt *bp = eth_dev->data->dev_private;
1373         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1374         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1375         struct rte_eth_link link;
1376         int ret;
1377
1378         eth_dev->data->dev_started = 0;
1379         eth_dev->data->scattered_rx = 0;
1380
1381         /* Prevent crashes when queues are still in use */
1382         eth_dev->rx_pkt_burst = &bnxt_dummy_recv_pkts;
1383         eth_dev->tx_pkt_burst = &bnxt_dummy_xmit_pkts;
1384
1385         bnxt_disable_int(bp);
1386
1387         /* disable uio/vfio intr/eventfd mapping */
1388         rte_intr_disable(intr_handle);
1389
1390         /* Stop the child representors for this device */
1391         ret = bnxt_rep_stop_all(bp);
1392         if (ret != 0)
1393                 return ret;
1394
1395         /* delete the bnxt ULP port details */
1396         bnxt_ulp_port_deinit(bp);
1397
1398         bnxt_cancel_fw_health_check(bp);
1399
1400         if (BNXT_P5_PTP_TIMESYNC_ENABLED(bp))
1401                 bnxt_cancel_ptp_alarm(bp);
1402
1403         /* Do not bring link down during reset recovery */
1404         if (!is_bnxt_in_error(bp)) {
1405                 bnxt_dev_set_link_down_op(eth_dev);
1406                 /* Wait for link to be reset */
1407                 if (BNXT_SINGLE_PF(bp))
1408                         rte_delay_ms(500);
1409                 /* clear the recorded link status */
1410                 memset(&link, 0, sizeof(link));
1411                 rte_eth_linkstatus_set(eth_dev, &link);
1412         }
1413
1414         /* Clean queue intr-vector mapping */
1415         rte_intr_efd_disable(intr_handle);
1416         if (intr_handle->intr_vec != NULL) {
1417                 rte_free(intr_handle->intr_vec);
1418                 intr_handle->intr_vec = NULL;
1419         }
1420
1421         bnxt_hwrm_port_clr_stats(bp);
1422         bnxt_free_tx_mbufs(bp);
1423         bnxt_free_rx_mbufs(bp);
1424         /* Process any remaining notifications in default completion queue */
1425         bnxt_int_handler(eth_dev);
1426         bnxt_shutdown_nic(bp);
1427         bnxt_hwrm_if_change(bp, false);
1428
1429         rte_free(bp->mark_table);
1430         bp->mark_table = NULL;
1431
1432         bp->flags &= ~BNXT_FLAG_RX_VECTOR_PKT_MODE;
1433         bp->rx_cosq_cnt = 0;
1434         /* All filters are deleted on a port stop. */
1435         if (BNXT_FLOW_XSTATS_EN(bp))
1436                 bp->flow_stat->flow_count = 0;
1437
1438         return 0;
1439 }
1440
1441 /* Unload the driver, release resources */
1442 static int bnxt_dev_stop_op(struct rte_eth_dev *eth_dev)
1443 {
1444         struct bnxt *bp = eth_dev->data->dev_private;
1445
1446         pthread_mutex_lock(&bp->err_recovery_lock);
1447         if (bp->flags & BNXT_FLAG_FW_RESET) {
1448                 PMD_DRV_LOG(ERR,
1449                             "Adapter recovering from error..Please retry\n");
1450                 pthread_mutex_unlock(&bp->err_recovery_lock);
1451                 return -EAGAIN;
1452         }
1453         pthread_mutex_unlock(&bp->err_recovery_lock);
1454
1455         return bnxt_dev_stop(eth_dev);
1456 }
1457
1458 static int bnxt_dev_start_op(struct rte_eth_dev *eth_dev)
1459 {
1460         struct bnxt *bp = eth_dev->data->dev_private;
1461         uint64_t rx_offloads = eth_dev->data->dev_conf.rxmode.offloads;
1462         int vlan_mask = 0;
1463         int rc, retry_cnt = BNXT_IF_CHANGE_RETRY_COUNT;
1464
1465         if (!eth_dev->data->nb_tx_queues || !eth_dev->data->nb_rx_queues) {
1466                 PMD_DRV_LOG(ERR, "Queues are not configured yet!\n");
1467                 return -EINVAL;
1468         }
1469
1470         if (bp->rx_cp_nr_rings > RTE_ETHDEV_QUEUE_STAT_CNTRS)
1471                 PMD_DRV_LOG(ERR,
1472                             "RxQ cnt %d > RTE_ETHDEV_QUEUE_STAT_CNTRS %d\n",
1473                             bp->rx_cp_nr_rings, RTE_ETHDEV_QUEUE_STAT_CNTRS);
1474
1475         do {
1476                 rc = bnxt_hwrm_if_change(bp, true);
1477                 if (rc == 0 || rc != -EAGAIN)
1478                         break;
1479
1480                 rte_delay_ms(BNXT_IF_CHANGE_RETRY_INTERVAL);
1481         } while (retry_cnt--);
1482
1483         if (rc)
1484                 return rc;
1485
1486         if (bp->flags & BNXT_FLAG_IF_CHANGE_HOT_FW_RESET_DONE) {
1487                 rc = bnxt_handle_if_change_status(bp);
1488                 if (rc)
1489                         return rc;
1490         }
1491
1492         bnxt_enable_int(bp);
1493
1494         eth_dev->data->scattered_rx = bnxt_scattered_rx(eth_dev);
1495
1496         rc = bnxt_start_nic(bp);
1497         if (rc)
1498                 goto error;
1499
1500         eth_dev->data->dev_started = 1;
1501
1502         bnxt_link_update_op(eth_dev, 1);
1503
1504         if (rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER)
1505                 vlan_mask |= ETH_VLAN_FILTER_MASK;
1506         if (rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
1507                 vlan_mask |= ETH_VLAN_STRIP_MASK;
1508         rc = bnxt_vlan_offload_set_op(eth_dev, vlan_mask);
1509         if (rc)
1510                 goto error;
1511
1512         /* Initialize bnxt ULP port details */
1513         rc = bnxt_ulp_port_init(bp);
1514         if (rc)
1515                 goto error;
1516
1517         eth_dev->rx_pkt_burst = bnxt_receive_function(eth_dev);
1518         eth_dev->tx_pkt_burst = bnxt_transmit_function(eth_dev);
1519
1520         bnxt_schedule_fw_health_check(bp);
1521
1522         if (BNXT_P5_PTP_TIMESYNC_ENABLED(bp))
1523                 bnxt_schedule_ptp_alarm(bp);
1524
1525         return 0;
1526
1527 error:
1528         bnxt_dev_stop(eth_dev);
1529         return rc;
1530 }
1531
1532 static void
1533 bnxt_uninit_locks(struct bnxt *bp)
1534 {
1535         pthread_mutex_destroy(&bp->flow_lock);
1536         pthread_mutex_destroy(&bp->def_cp_lock);
1537         pthread_mutex_destroy(&bp->health_check_lock);
1538         pthread_mutex_destroy(&bp->err_recovery_lock);
1539         if (bp->rep_info) {
1540                 pthread_mutex_destroy(&bp->rep_info->vfr_lock);
1541                 pthread_mutex_destroy(&bp->rep_info->vfr_start_lock);
1542         }
1543 }
1544
1545 static void bnxt_drv_uninit(struct bnxt *bp)
1546 {
1547         bnxt_free_switch_domain(bp);
1548         bnxt_free_leds_info(bp);
1549         bnxt_free_cos_queues(bp);
1550         bnxt_free_link_info(bp);
1551         bnxt_free_pf_info(bp);
1552         bnxt_free_parent_info(bp);
1553         bnxt_uninit_locks(bp);
1554
1555         rte_memzone_free((const struct rte_memzone *)bp->tx_mem_zone);
1556         bp->tx_mem_zone = NULL;
1557         rte_memzone_free((const struct rte_memzone *)bp->rx_mem_zone);
1558         bp->rx_mem_zone = NULL;
1559
1560         bnxt_free_vf_info(bp);
1561
1562         rte_free(bp->grp_info);
1563         bp->grp_info = NULL;
1564 }
1565
1566 static int bnxt_dev_close_op(struct rte_eth_dev *eth_dev)
1567 {
1568         struct bnxt *bp = eth_dev->data->dev_private;
1569         int ret = 0;
1570
1571         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1572                 return 0;
1573
1574         pthread_mutex_lock(&bp->err_recovery_lock);
1575         if (bp->flags & BNXT_FLAG_FW_RESET) {
1576                 PMD_DRV_LOG(ERR,
1577                             "Adapter recovering from error...Please retry\n");
1578                 pthread_mutex_unlock(&bp->err_recovery_lock);
1579                 return -EAGAIN;
1580         }
1581         pthread_mutex_unlock(&bp->err_recovery_lock);
1582
1583         /* cancel the recovery handler before remove dev */
1584         rte_eal_alarm_cancel(bnxt_dev_reset_and_resume, (void *)bp);
1585         rte_eal_alarm_cancel(bnxt_dev_recover, (void *)bp);
1586         bnxt_cancel_fc_thread(bp);
1587
1588         if (eth_dev->data->dev_started)
1589                 ret = bnxt_dev_stop(eth_dev);
1590
1591         bnxt_uninit_resources(bp, false);
1592
1593         bnxt_drv_uninit(bp);
1594
1595         return ret;
1596 }
1597
1598 static void bnxt_mac_addr_remove_op(struct rte_eth_dev *eth_dev,
1599                                     uint32_t index)
1600 {
1601         struct bnxt *bp = eth_dev->data->dev_private;
1602         uint64_t pool_mask = eth_dev->data->mac_pool_sel[index];
1603         struct bnxt_vnic_info *vnic;
1604         struct bnxt_filter_info *filter, *temp_filter;
1605         uint32_t i;
1606
1607         if (is_bnxt_in_error(bp))
1608                 return;
1609
1610         /*
1611          * Loop through all VNICs from the specified filter flow pools to
1612          * remove the corresponding MAC addr filter
1613          */
1614         for (i = 0; i < bp->nr_vnics; i++) {
1615                 if (!(pool_mask & (1ULL << i)))
1616                         continue;
1617
1618                 vnic = &bp->vnic_info[i];
1619                 filter = STAILQ_FIRST(&vnic->filter);
1620                 while (filter) {
1621                         temp_filter = STAILQ_NEXT(filter, next);
1622                         if (filter->mac_index == index) {
1623                                 STAILQ_REMOVE(&vnic->filter, filter,
1624                                                 bnxt_filter_info, next);
1625                                 bnxt_hwrm_clear_l2_filter(bp, filter);
1626                                 bnxt_free_filter(bp, filter);
1627                         }
1628                         filter = temp_filter;
1629                 }
1630         }
1631 }
1632
1633 static int bnxt_add_mac_filter(struct bnxt *bp, struct bnxt_vnic_info *vnic,
1634                                struct rte_ether_addr *mac_addr, uint32_t index,
1635                                uint32_t pool)
1636 {
1637         struct bnxt_filter_info *filter;
1638         int rc = 0;
1639
1640         /* Attach requested MAC address to the new l2_filter */
1641         STAILQ_FOREACH(filter, &vnic->filter, next) {
1642                 if (filter->mac_index == index) {
1643                         PMD_DRV_LOG(DEBUG,
1644                                     "MAC addr already existed for pool %d\n",
1645                                     pool);
1646                         return 0;
1647                 }
1648         }
1649
1650         filter = bnxt_alloc_filter(bp);
1651         if (!filter) {
1652                 PMD_DRV_LOG(ERR, "L2 filter alloc failed\n");
1653                 return -ENODEV;
1654         }
1655
1656         /* bnxt_alloc_filter copies default MAC to filter->l2_addr. So,
1657          * if the MAC that's been programmed now is a different one, then,
1658          * copy that addr to filter->l2_addr
1659          */
1660         if (mac_addr)
1661                 memcpy(filter->l2_addr, mac_addr, RTE_ETHER_ADDR_LEN);
1662         filter->flags |= HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_OUTERMOST;
1663
1664         rc = bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id, filter);
1665         if (!rc) {
1666                 filter->mac_index = index;
1667                 if (filter->mac_index == 0)
1668                         STAILQ_INSERT_HEAD(&vnic->filter, filter, next);
1669                 else
1670                         STAILQ_INSERT_TAIL(&vnic->filter, filter, next);
1671         } else {
1672                 bnxt_free_filter(bp, filter);
1673         }
1674
1675         return rc;
1676 }
1677
1678 static int bnxt_mac_addr_add_op(struct rte_eth_dev *eth_dev,
1679                                 struct rte_ether_addr *mac_addr,
1680                                 uint32_t index, uint32_t pool)
1681 {
1682         struct bnxt *bp = eth_dev->data->dev_private;
1683         struct bnxt_vnic_info *vnic = &bp->vnic_info[pool];
1684         int rc = 0;
1685
1686         rc = is_bnxt_in_error(bp);
1687         if (rc)
1688                 return rc;
1689
1690         if (BNXT_VF(bp) && !BNXT_VF_IS_TRUSTED(bp)) {
1691                 PMD_DRV_LOG(ERR, "Cannot add MAC address to a VF interface\n");
1692                 return -ENOTSUP;
1693         }
1694
1695         if (!vnic) {
1696                 PMD_DRV_LOG(ERR, "VNIC not found for pool %d!\n", pool);
1697                 return -EINVAL;
1698         }
1699
1700         /* Filter settings will get applied when port is started */
1701         if (!eth_dev->data->dev_started)
1702                 return 0;
1703
1704         rc = bnxt_add_mac_filter(bp, vnic, mac_addr, index, pool);
1705
1706         return rc;
1707 }
1708
1709 int bnxt_link_update_op(struct rte_eth_dev *eth_dev, int wait_to_complete)
1710 {
1711         int rc = 0;
1712         struct bnxt *bp = eth_dev->data->dev_private;
1713         struct rte_eth_link new;
1714         int cnt = wait_to_complete ? BNXT_MAX_LINK_WAIT_CNT :
1715                         BNXT_MIN_LINK_WAIT_CNT;
1716
1717         rc = is_bnxt_in_error(bp);
1718         if (rc)
1719                 return rc;
1720
1721         memset(&new, 0, sizeof(new));
1722         do {
1723                 /* Retrieve link info from hardware */
1724                 rc = bnxt_get_hwrm_link_config(bp, &new);
1725                 if (rc) {
1726                         new.link_speed = ETH_LINK_SPEED_100M;
1727                         new.link_duplex = ETH_LINK_FULL_DUPLEX;
1728                         PMD_DRV_LOG(ERR,
1729                                 "Failed to retrieve link rc = 0x%x!\n", rc);
1730                         goto out;
1731                 }
1732
1733                 if (!wait_to_complete || new.link_status)
1734                         break;
1735
1736                 rte_delay_ms(BNXT_LINK_WAIT_INTERVAL);
1737         } while (cnt--);
1738
1739         /* Only single function PF can bring phy down.
1740          * When port is stopped, report link down for VF/MH/NPAR functions.
1741          */
1742         if (!BNXT_SINGLE_PF(bp) && !eth_dev->data->dev_started)
1743                 memset(&new, 0, sizeof(new));
1744
1745 out:
1746         /* Timed out or success */
1747         if (new.link_status != eth_dev->data->dev_link.link_status ||
1748             new.link_speed != eth_dev->data->dev_link.link_speed) {
1749                 rte_eth_linkstatus_set(eth_dev, &new);
1750
1751                 rte_eth_dev_callback_process(eth_dev,
1752                                              RTE_ETH_EVENT_INTR_LSC,
1753                                              NULL);
1754
1755                 bnxt_print_link_info(eth_dev);
1756         }
1757
1758         return rc;
1759 }
1760
1761 static int bnxt_promiscuous_enable_op(struct rte_eth_dev *eth_dev)
1762 {
1763         struct bnxt *bp = eth_dev->data->dev_private;
1764         struct bnxt_vnic_info *vnic;
1765         uint32_t old_flags;
1766         int rc;
1767
1768         rc = is_bnxt_in_error(bp);
1769         if (rc)
1770                 return rc;
1771
1772         /* Filter settings will get applied when port is started */
1773         if (!eth_dev->data->dev_started)
1774                 return 0;
1775
1776         if (bp->vnic_info == NULL)
1777                 return 0;
1778
1779         vnic = BNXT_GET_DEFAULT_VNIC(bp);
1780
1781         old_flags = vnic->flags;
1782         vnic->flags |= BNXT_VNIC_INFO_PROMISC;
1783         rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1784         if (rc != 0)
1785                 vnic->flags = old_flags;
1786
1787         return rc;
1788 }
1789
1790 static int bnxt_promiscuous_disable_op(struct rte_eth_dev *eth_dev)
1791 {
1792         struct bnxt *bp = eth_dev->data->dev_private;
1793         struct bnxt_vnic_info *vnic;
1794         uint32_t old_flags;
1795         int rc;
1796
1797         rc = is_bnxt_in_error(bp);
1798         if (rc)
1799                 return rc;
1800
1801         /* Filter settings will get applied when port is started */
1802         if (!eth_dev->data->dev_started)
1803                 return 0;
1804
1805         if (bp->vnic_info == NULL)
1806                 return 0;
1807
1808         vnic = BNXT_GET_DEFAULT_VNIC(bp);
1809
1810         old_flags = vnic->flags;
1811         vnic->flags &= ~BNXT_VNIC_INFO_PROMISC;
1812         rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1813         if (rc != 0)
1814                 vnic->flags = old_flags;
1815
1816         return rc;
1817 }
1818
1819 static int bnxt_allmulticast_enable_op(struct rte_eth_dev *eth_dev)
1820 {
1821         struct bnxt *bp = eth_dev->data->dev_private;
1822         struct bnxt_vnic_info *vnic;
1823         uint32_t old_flags;
1824         int rc;
1825
1826         rc = is_bnxt_in_error(bp);
1827         if (rc)
1828                 return rc;
1829
1830         /* Filter settings will get applied when port is started */
1831         if (!eth_dev->data->dev_started)
1832                 return 0;
1833
1834         if (bp->vnic_info == NULL)
1835                 return 0;
1836
1837         vnic = BNXT_GET_DEFAULT_VNIC(bp);
1838
1839         old_flags = vnic->flags;
1840         vnic->flags |= BNXT_VNIC_INFO_ALLMULTI;
1841         rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1842         if (rc != 0)
1843                 vnic->flags = old_flags;
1844
1845         return rc;
1846 }
1847
1848 static int bnxt_allmulticast_disable_op(struct rte_eth_dev *eth_dev)
1849 {
1850         struct bnxt *bp = eth_dev->data->dev_private;
1851         struct bnxt_vnic_info *vnic;
1852         uint32_t old_flags;
1853         int rc;
1854
1855         rc = is_bnxt_in_error(bp);
1856         if (rc)
1857                 return rc;
1858
1859         /* Filter settings will get applied when port is started */
1860         if (!eth_dev->data->dev_started)
1861                 return 0;
1862
1863         if (bp->vnic_info == NULL)
1864                 return 0;
1865
1866         vnic = BNXT_GET_DEFAULT_VNIC(bp);
1867
1868         old_flags = vnic->flags;
1869         vnic->flags &= ~BNXT_VNIC_INFO_ALLMULTI;
1870         rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1871         if (rc != 0)
1872                 vnic->flags = old_flags;
1873
1874         return rc;
1875 }
1876
1877 /* Return bnxt_rx_queue pointer corresponding to a given rxq. */
1878 static struct bnxt_rx_queue *bnxt_qid_to_rxq(struct bnxt *bp, uint16_t qid)
1879 {
1880         if (qid >= bp->rx_nr_rings)
1881                 return NULL;
1882
1883         return bp->eth_dev->data->rx_queues[qid];
1884 }
1885
1886 /* Return rxq corresponding to a given rss table ring/group ID. */
1887 static uint16_t bnxt_rss_to_qid(struct bnxt *bp, uint16_t fwr)
1888 {
1889         struct bnxt_rx_queue *rxq;
1890         unsigned int i;
1891
1892         if (!BNXT_HAS_RING_GRPS(bp)) {
1893                 for (i = 0; i < bp->rx_nr_rings; i++) {
1894                         rxq = bp->eth_dev->data->rx_queues[i];
1895                         if (rxq->rx_ring->rx_ring_struct->fw_ring_id == fwr)
1896                                 return rxq->index;
1897                 }
1898         } else {
1899                 for (i = 0; i < bp->rx_nr_rings; i++) {
1900                         if (bp->grp_info[i].fw_grp_id == fwr)
1901                                 return i;
1902                 }
1903         }
1904
1905         return INVALID_HW_RING_ID;
1906 }
1907
1908 static int bnxt_reta_update_op(struct rte_eth_dev *eth_dev,
1909                             struct rte_eth_rss_reta_entry64 *reta_conf,
1910                             uint16_t reta_size)
1911 {
1912         struct bnxt *bp = eth_dev->data->dev_private;
1913         struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
1914         struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp);
1915         uint16_t tbl_size = bnxt_rss_hash_tbl_size(bp);
1916         uint16_t idx, sft;
1917         int i, rc;
1918
1919         rc = is_bnxt_in_error(bp);
1920         if (rc)
1921                 return rc;
1922
1923         if (!vnic->rss_table)
1924                 return -EINVAL;
1925
1926         if (!(dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG))
1927                 return -EINVAL;
1928
1929         if (reta_size != tbl_size) {
1930                 PMD_DRV_LOG(ERR, "The configured hash table lookup size "
1931                         "(%d) must equal the size supported by the hardware "
1932                         "(%d)\n", reta_size, tbl_size);
1933                 return -EINVAL;
1934         }
1935
1936         for (i = 0; i < reta_size; i++) {
1937                 struct bnxt_rx_queue *rxq;
1938
1939                 idx = i / RTE_RETA_GROUP_SIZE;
1940                 sft = i % RTE_RETA_GROUP_SIZE;
1941
1942                 if (!(reta_conf[idx].mask & (1ULL << sft)))
1943                         continue;
1944
1945                 rxq = bnxt_qid_to_rxq(bp, reta_conf[idx].reta[sft]);
1946                 if (!rxq) {
1947                         PMD_DRV_LOG(ERR, "Invalid ring in reta_conf.\n");
1948                         return -EINVAL;
1949                 }
1950
1951                 if (BNXT_CHIP_P5(bp)) {
1952                         vnic->rss_table[i * 2] =
1953                                 rxq->rx_ring->rx_ring_struct->fw_ring_id;
1954                         vnic->rss_table[i * 2 + 1] =
1955                                 rxq->cp_ring->cp_ring_struct->fw_ring_id;
1956                 } else {
1957                         vnic->rss_table[i] =
1958                             vnic->fw_grp_ids[reta_conf[idx].reta[sft]];
1959                 }
1960         }
1961
1962         rc = bnxt_hwrm_vnic_rss_cfg(bp, vnic);
1963         return rc;
1964 }
1965
1966 static int bnxt_reta_query_op(struct rte_eth_dev *eth_dev,
1967                               struct rte_eth_rss_reta_entry64 *reta_conf,
1968                               uint16_t reta_size)
1969 {
1970         struct bnxt *bp = eth_dev->data->dev_private;
1971         struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp);
1972         uint16_t tbl_size = bnxt_rss_hash_tbl_size(bp);
1973         uint16_t idx, sft, i;
1974         int rc;
1975
1976         rc = is_bnxt_in_error(bp);
1977         if (rc)
1978                 return rc;
1979
1980         /* Retrieve from the default VNIC */
1981         if (!vnic)
1982                 return -EINVAL;
1983         if (!vnic->rss_table)
1984                 return -EINVAL;
1985
1986         if (reta_size != tbl_size) {
1987                 PMD_DRV_LOG(ERR, "The configured hash table lookup size "
1988                         "(%d) must equal the size supported by the hardware "
1989                         "(%d)\n", reta_size, tbl_size);
1990                 return -EINVAL;
1991         }
1992
1993         for (idx = 0, i = 0; i < reta_size; i++) {
1994                 idx = i / RTE_RETA_GROUP_SIZE;
1995                 sft = i % RTE_RETA_GROUP_SIZE;
1996
1997                 if (reta_conf[idx].mask & (1ULL << sft)) {
1998                         uint16_t qid;
1999
2000                         if (BNXT_CHIP_P5(bp))
2001                                 qid = bnxt_rss_to_qid(bp,
2002                                                       vnic->rss_table[i * 2]);
2003                         else
2004                                 qid = bnxt_rss_to_qid(bp, vnic->rss_table[i]);
2005
2006                         if (qid == INVALID_HW_RING_ID) {
2007                                 PMD_DRV_LOG(ERR, "Inv. entry in rss table.\n");
2008                                 return -EINVAL;
2009                         }
2010                         reta_conf[idx].reta[sft] = qid;
2011                 }
2012         }
2013
2014         return 0;
2015 }
2016
2017 static int bnxt_rss_hash_update_op(struct rte_eth_dev *eth_dev,
2018                                    struct rte_eth_rss_conf *rss_conf)
2019 {
2020         struct bnxt *bp = eth_dev->data->dev_private;
2021         struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
2022         struct bnxt_vnic_info *vnic;
2023         int rc;
2024
2025         rc = is_bnxt_in_error(bp);
2026         if (rc)
2027                 return rc;
2028
2029         /*
2030          * If RSS enablement were different than dev_configure,
2031          * then return -EINVAL
2032          */
2033         if (dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG) {
2034                 if (!rss_conf->rss_hf)
2035                         PMD_DRV_LOG(ERR, "Hash type NONE\n");
2036         } else {
2037                 if (rss_conf->rss_hf & BNXT_ETH_RSS_SUPPORT)
2038                         return -EINVAL;
2039         }
2040
2041         bp->flags |= BNXT_FLAG_UPDATE_HASH;
2042         memcpy(&eth_dev->data->dev_conf.rx_adv_conf.rss_conf,
2043                rss_conf,
2044                sizeof(*rss_conf));
2045
2046         /* Update the default RSS VNIC(s) */
2047         vnic = BNXT_GET_DEFAULT_VNIC(bp);
2048         vnic->hash_type = bnxt_rte_to_hwrm_hash_types(rss_conf->rss_hf);
2049         vnic->hash_mode =
2050                 bnxt_rte_to_hwrm_hash_level(bp, rss_conf->rss_hf,
2051                                             ETH_RSS_LEVEL(rss_conf->rss_hf));
2052
2053         /*
2054          * If hashkey is not specified, use the previously configured
2055          * hashkey
2056          */
2057         if (!rss_conf->rss_key)
2058                 goto rss_config;
2059
2060         if (rss_conf->rss_key_len != HW_HASH_KEY_SIZE) {
2061                 PMD_DRV_LOG(ERR,
2062                             "Invalid hashkey length, should be 16 bytes\n");
2063                 return -EINVAL;
2064         }
2065         memcpy(vnic->rss_hash_key, rss_conf->rss_key, rss_conf->rss_key_len);
2066
2067 rss_config:
2068         rc = bnxt_hwrm_vnic_rss_cfg(bp, vnic);
2069         return rc;
2070 }
2071
2072 static int bnxt_rss_hash_conf_get_op(struct rte_eth_dev *eth_dev,
2073                                      struct rte_eth_rss_conf *rss_conf)
2074 {
2075         struct bnxt *bp = eth_dev->data->dev_private;
2076         struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp);
2077         int len, rc;
2078         uint32_t hash_types;
2079
2080         rc = is_bnxt_in_error(bp);
2081         if (rc)
2082                 return rc;
2083
2084         /* RSS configuration is the same for all VNICs */
2085         if (vnic && vnic->rss_hash_key) {
2086                 if (rss_conf->rss_key) {
2087                         len = rss_conf->rss_key_len <= HW_HASH_KEY_SIZE ?
2088                               rss_conf->rss_key_len : HW_HASH_KEY_SIZE;
2089                         memcpy(rss_conf->rss_key, vnic->rss_hash_key, len);
2090                 }
2091
2092                 hash_types = vnic->hash_type;
2093                 rss_conf->rss_hf = 0;
2094                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV4) {
2095                         rss_conf->rss_hf |= ETH_RSS_IPV4;
2096                         hash_types &= ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV4;
2097                 }
2098                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV4) {
2099                         rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP;
2100                         hash_types &=
2101                                 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV4;
2102                 }
2103                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV4) {
2104                         rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
2105                         hash_types &=
2106                                 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV4;
2107                 }
2108                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6) {
2109                         rss_conf->rss_hf |= ETH_RSS_IPV6;
2110                         hash_types &= ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6;
2111                 }
2112                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV6) {
2113                         rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV6_TCP;
2114                         hash_types &=
2115                                 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV6;
2116                 }
2117                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV6) {
2118                         rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;
2119                         hash_types &=
2120                                 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV6;
2121                 }
2122
2123                 rss_conf->rss_hf |=
2124                         bnxt_hwrm_to_rte_rss_level(bp, vnic->hash_mode);
2125
2126                 if (hash_types) {
2127                         PMD_DRV_LOG(ERR,
2128                                 "Unknown RSS config from firmware (%08x), RSS disabled",
2129                                 vnic->hash_type);
2130                         return -ENOTSUP;
2131                 }
2132         } else {
2133                 rss_conf->rss_hf = 0;
2134         }
2135         return 0;
2136 }
2137
2138 static int bnxt_flow_ctrl_get_op(struct rte_eth_dev *dev,
2139                                struct rte_eth_fc_conf *fc_conf)
2140 {
2141         struct bnxt *bp = dev->data->dev_private;
2142         struct rte_eth_link link_info;
2143         int rc;
2144
2145         rc = is_bnxt_in_error(bp);
2146         if (rc)
2147                 return rc;
2148
2149         rc = bnxt_get_hwrm_link_config(bp, &link_info);
2150         if (rc)
2151                 return rc;
2152
2153         memset(fc_conf, 0, sizeof(*fc_conf));
2154         if (bp->link_info->auto_pause)
2155                 fc_conf->autoneg = 1;
2156         switch (bp->link_info->pause) {
2157         case 0:
2158                 fc_conf->mode = RTE_FC_NONE;
2159                 break;
2160         case HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_TX:
2161                 fc_conf->mode = RTE_FC_TX_PAUSE;
2162                 break;
2163         case HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_RX:
2164                 fc_conf->mode = RTE_FC_RX_PAUSE;
2165                 break;
2166         case (HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_TX |
2167                         HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_RX):
2168                 fc_conf->mode = RTE_FC_FULL;
2169                 break;
2170         }
2171         return 0;
2172 }
2173
2174 static int bnxt_flow_ctrl_set_op(struct rte_eth_dev *dev,
2175                                struct rte_eth_fc_conf *fc_conf)
2176 {
2177         struct bnxt *bp = dev->data->dev_private;
2178         int rc;
2179
2180         rc = is_bnxt_in_error(bp);
2181         if (rc)
2182                 return rc;
2183
2184         if (!BNXT_SINGLE_PF(bp) || BNXT_VF(bp)) {
2185                 PMD_DRV_LOG(ERR, "Flow Control Settings cannot be modified\n");
2186                 return -ENOTSUP;
2187         }
2188
2189         switch (fc_conf->mode) {
2190         case RTE_FC_NONE:
2191                 bp->link_info->auto_pause = 0;
2192                 bp->link_info->force_pause = 0;
2193                 break;
2194         case RTE_FC_RX_PAUSE:
2195                 if (fc_conf->autoneg) {
2196                         bp->link_info->auto_pause =
2197                                         HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_RX;
2198                         bp->link_info->force_pause = 0;
2199                 } else {
2200                         bp->link_info->auto_pause = 0;
2201                         bp->link_info->force_pause =
2202                                         HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_RX;
2203                 }
2204                 break;
2205         case RTE_FC_TX_PAUSE:
2206                 if (fc_conf->autoneg) {
2207                         bp->link_info->auto_pause =
2208                                         HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_TX;
2209                         bp->link_info->force_pause = 0;
2210                 } else {
2211                         bp->link_info->auto_pause = 0;
2212                         bp->link_info->force_pause =
2213                                         HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_TX;
2214                 }
2215                 break;
2216         case RTE_FC_FULL:
2217                 if (fc_conf->autoneg) {
2218                         bp->link_info->auto_pause =
2219                                         HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_TX |
2220                                         HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_RX;
2221                         bp->link_info->force_pause = 0;
2222                 } else {
2223                         bp->link_info->auto_pause = 0;
2224                         bp->link_info->force_pause =
2225                                         HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_TX |
2226                                         HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_RX;
2227                 }
2228                 break;
2229         }
2230         return bnxt_set_hwrm_link_config(bp, true);
2231 }
2232
2233 /* Add UDP tunneling port */
2234 static int
2235 bnxt_udp_tunnel_port_add_op(struct rte_eth_dev *eth_dev,
2236                          struct rte_eth_udp_tunnel *udp_tunnel)
2237 {
2238         struct bnxt *bp = eth_dev->data->dev_private;
2239         uint16_t tunnel_type = 0;
2240         int rc = 0;
2241
2242         rc = is_bnxt_in_error(bp);
2243         if (rc)
2244                 return rc;
2245
2246         switch (udp_tunnel->prot_type) {
2247         case RTE_TUNNEL_TYPE_VXLAN:
2248                 if (bp->vxlan_port_cnt) {
2249                         PMD_DRV_LOG(ERR, "Tunnel Port %d already programmed\n",
2250                                 udp_tunnel->udp_port);
2251                         if (bp->vxlan_port != udp_tunnel->udp_port) {
2252                                 PMD_DRV_LOG(ERR, "Only one port allowed\n");
2253                                 return -ENOSPC;
2254                         }
2255                         bp->vxlan_port_cnt++;
2256                         return 0;
2257                 }
2258                 tunnel_type =
2259                         HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_VXLAN;
2260                 bp->vxlan_port_cnt++;
2261                 break;
2262         case RTE_TUNNEL_TYPE_GENEVE:
2263                 if (bp->geneve_port_cnt) {
2264                         PMD_DRV_LOG(ERR, "Tunnel Port %d already programmed\n",
2265                                 udp_tunnel->udp_port);
2266                         if (bp->geneve_port != udp_tunnel->udp_port) {
2267                                 PMD_DRV_LOG(ERR, "Only one port allowed\n");
2268                                 return -ENOSPC;
2269                         }
2270                         bp->geneve_port_cnt++;
2271                         return 0;
2272                 }
2273                 tunnel_type =
2274                         HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_GENEVE;
2275                 bp->geneve_port_cnt++;
2276                 break;
2277         default:
2278                 PMD_DRV_LOG(ERR, "Tunnel type is not supported\n");
2279                 return -ENOTSUP;
2280         }
2281         rc = bnxt_hwrm_tunnel_dst_port_alloc(bp, udp_tunnel->udp_port,
2282                                              tunnel_type);
2283         return rc;
2284 }
2285
2286 static int
2287 bnxt_udp_tunnel_port_del_op(struct rte_eth_dev *eth_dev,
2288                          struct rte_eth_udp_tunnel *udp_tunnel)
2289 {
2290         struct bnxt *bp = eth_dev->data->dev_private;
2291         uint16_t tunnel_type = 0;
2292         uint16_t port = 0;
2293         int rc = 0;
2294
2295         rc = is_bnxt_in_error(bp);
2296         if (rc)
2297                 return rc;
2298
2299         switch (udp_tunnel->prot_type) {
2300         case RTE_TUNNEL_TYPE_VXLAN:
2301                 if (!bp->vxlan_port_cnt) {
2302                         PMD_DRV_LOG(ERR, "No Tunnel port configured yet\n");
2303                         return -EINVAL;
2304                 }
2305                 if (bp->vxlan_port != udp_tunnel->udp_port) {
2306                         PMD_DRV_LOG(ERR, "Req Port: %d. Configured port: %d\n",
2307                                 udp_tunnel->udp_port, bp->vxlan_port);
2308                         return -EINVAL;
2309                 }
2310                 if (--bp->vxlan_port_cnt)
2311                         return 0;
2312
2313                 tunnel_type =
2314                         HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN;
2315                 port = bp->vxlan_fw_dst_port_id;
2316                 break;
2317         case RTE_TUNNEL_TYPE_GENEVE:
2318                 if (!bp->geneve_port_cnt) {
2319                         PMD_DRV_LOG(ERR, "No Tunnel port configured yet\n");
2320                         return -EINVAL;
2321                 }
2322                 if (bp->geneve_port != udp_tunnel->udp_port) {
2323                         PMD_DRV_LOG(ERR, "Req Port: %d. Configured port: %d\n",
2324                                 udp_tunnel->udp_port, bp->geneve_port);
2325                         return -EINVAL;
2326                 }
2327                 if (--bp->geneve_port_cnt)
2328                         return 0;
2329
2330                 tunnel_type =
2331                         HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_GENEVE;
2332                 port = bp->geneve_fw_dst_port_id;
2333                 break;
2334         default:
2335                 PMD_DRV_LOG(ERR, "Tunnel type is not supported\n");
2336                 return -ENOTSUP;
2337         }
2338
2339         rc = bnxt_hwrm_tunnel_dst_port_free(bp, port, tunnel_type);
2340         return rc;
2341 }
2342
2343 static int bnxt_del_vlan_filter(struct bnxt *bp, uint16_t vlan_id)
2344 {
2345         struct bnxt_filter_info *filter;
2346         struct bnxt_vnic_info *vnic;
2347         int rc = 0;
2348         uint32_t chk = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN;
2349
2350         vnic = BNXT_GET_DEFAULT_VNIC(bp);
2351         filter = STAILQ_FIRST(&vnic->filter);
2352         while (filter) {
2353                 /* Search for this matching MAC+VLAN filter */
2354                 if (bnxt_vlan_filter_exists(bp, filter, chk, vlan_id)) {
2355                         /* Delete the filter */
2356                         rc = bnxt_hwrm_clear_l2_filter(bp, filter);
2357                         if (rc)
2358                                 return rc;
2359                         STAILQ_REMOVE(&vnic->filter, filter,
2360                                       bnxt_filter_info, next);
2361                         bnxt_free_filter(bp, filter);
2362                         PMD_DRV_LOG(INFO,
2363                                     "Deleted vlan filter for %d\n",
2364                                     vlan_id);
2365                         return 0;
2366                 }
2367                 filter = STAILQ_NEXT(filter, next);
2368         }
2369         return -ENOENT;
2370 }
2371
2372 static int bnxt_add_vlan_filter(struct bnxt *bp, uint16_t vlan_id)
2373 {
2374         struct bnxt_filter_info *filter;
2375         struct bnxt_vnic_info *vnic;
2376         int rc = 0;
2377         uint32_t en = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN |
2378                 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN_MASK;
2379         uint32_t chk = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN;
2380
2381         /* Implementation notes on the use of VNIC in this command:
2382          *
2383          * By default, these filters belong to default vnic for the function.
2384          * Once these filters are set up, only destination VNIC can be modified.
2385          * If the destination VNIC is not specified in this command,
2386          * then the HWRM shall only create an l2 context id.
2387          */
2388
2389         vnic = BNXT_GET_DEFAULT_VNIC(bp);
2390         filter = STAILQ_FIRST(&vnic->filter);
2391         /* Check if the VLAN has already been added */
2392         while (filter) {
2393                 if (bnxt_vlan_filter_exists(bp, filter, chk, vlan_id))
2394                         return -EEXIST;
2395
2396                 filter = STAILQ_NEXT(filter, next);
2397         }
2398
2399         /* No match found. Alloc a fresh filter and issue the L2_FILTER_ALLOC
2400          * command to create MAC+VLAN filter with the right flags, enables set.
2401          */
2402         filter = bnxt_alloc_filter(bp);
2403         if (!filter) {
2404                 PMD_DRV_LOG(ERR,
2405                             "MAC/VLAN filter alloc failed\n");
2406                 return -ENOMEM;
2407         }
2408         /* MAC + VLAN ID filter */
2409         /* If l2_ivlan == 0 and l2_ivlan_mask != 0, only
2410          * untagged packets are received
2411          *
2412          * If l2_ivlan != 0 and l2_ivlan_mask != 0, untagged
2413          * packets and only the programmed vlan's packets are received
2414          */
2415         filter->l2_ivlan = vlan_id;
2416         filter->l2_ivlan_mask = 0x0FFF;
2417         filter->enables |= en;
2418         filter->flags |= HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_OUTERMOST;
2419
2420         rc = bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id, filter);
2421         if (rc) {
2422                 /* Free the newly allocated filter as we were
2423                  * not able to create the filter in hardware.
2424                  */
2425                 bnxt_free_filter(bp, filter);
2426                 return rc;
2427         }
2428
2429         filter->mac_index = 0;
2430         /* Add this new filter to the list */
2431         if (vlan_id == 0)
2432                 STAILQ_INSERT_HEAD(&vnic->filter, filter, next);
2433         else
2434                 STAILQ_INSERT_TAIL(&vnic->filter, filter, next);
2435
2436         PMD_DRV_LOG(INFO,
2437                     "Added Vlan filter for %d\n", vlan_id);
2438         return rc;
2439 }
2440
2441 static int bnxt_vlan_filter_set_op(struct rte_eth_dev *eth_dev,
2442                 uint16_t vlan_id, int on)
2443 {
2444         struct bnxt *bp = eth_dev->data->dev_private;
2445         int rc;
2446
2447         rc = is_bnxt_in_error(bp);
2448         if (rc)
2449                 return rc;
2450
2451         if (!eth_dev->data->dev_started) {
2452                 PMD_DRV_LOG(ERR, "port must be started before setting vlan\n");
2453                 return -EINVAL;
2454         }
2455
2456         /* These operations apply to ALL existing MAC/VLAN filters */
2457         if (on)
2458                 return bnxt_add_vlan_filter(bp, vlan_id);
2459         else
2460                 return bnxt_del_vlan_filter(bp, vlan_id);
2461 }
2462
2463 static int bnxt_del_dflt_mac_filter(struct bnxt *bp,
2464                                     struct bnxt_vnic_info *vnic)
2465 {
2466         struct bnxt_filter_info *filter;
2467         int rc;
2468
2469         filter = STAILQ_FIRST(&vnic->filter);
2470         while (filter) {
2471                 if (filter->mac_index == 0 &&
2472                     !memcmp(filter->l2_addr, bp->mac_addr,
2473                             RTE_ETHER_ADDR_LEN)) {
2474                         rc = bnxt_hwrm_clear_l2_filter(bp, filter);
2475                         if (!rc) {
2476                                 STAILQ_REMOVE(&vnic->filter, filter,
2477                                               bnxt_filter_info, next);
2478                                 bnxt_free_filter(bp, filter);
2479                         }
2480                         return rc;
2481                 }
2482                 filter = STAILQ_NEXT(filter, next);
2483         }
2484         return 0;
2485 }
2486
2487 static int
2488 bnxt_config_vlan_hw_filter(struct bnxt *bp, uint64_t rx_offloads)
2489 {
2490         struct bnxt_vnic_info *vnic;
2491         unsigned int i;
2492         int rc;
2493
2494         vnic = BNXT_GET_DEFAULT_VNIC(bp);
2495         if (!(rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER)) {
2496                 /* Remove any VLAN filters programmed */
2497                 for (i = 0; i < RTE_ETHER_MAX_VLAN_ID; i++)
2498                         bnxt_del_vlan_filter(bp, i);
2499
2500                 rc = bnxt_add_mac_filter(bp, vnic, NULL, 0, 0);
2501                 if (rc)
2502                         return rc;
2503         } else {
2504                 /* Default filter will allow packets that match the
2505                  * dest mac. So, it has to be deleted, otherwise, we
2506                  * will endup receiving vlan packets for which the
2507                  * filter is not programmed, when hw-vlan-filter
2508                  * configuration is ON
2509                  */
2510                 bnxt_del_dflt_mac_filter(bp, vnic);
2511                 /* This filter will allow only untagged packets */
2512                 bnxt_add_vlan_filter(bp, 0);
2513         }
2514         PMD_DRV_LOG(DEBUG, "VLAN Filtering: %d\n",
2515                     !!(rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER));
2516
2517         return 0;
2518 }
2519
2520 static int bnxt_free_one_vnic(struct bnxt *bp, uint16_t vnic_id)
2521 {
2522         struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id];
2523         unsigned int i;
2524         int rc;
2525
2526         /* Destroy vnic filters and vnic */
2527         if (bp->eth_dev->data->dev_conf.rxmode.offloads &
2528             DEV_RX_OFFLOAD_VLAN_FILTER) {
2529                 for (i = 0; i < RTE_ETHER_MAX_VLAN_ID; i++)
2530                         bnxt_del_vlan_filter(bp, i);
2531         }
2532         bnxt_del_dflt_mac_filter(bp, vnic);
2533
2534         rc = bnxt_hwrm_vnic_free(bp, vnic);
2535         if (rc)
2536                 return rc;
2537
2538         rte_free(vnic->fw_grp_ids);
2539         vnic->fw_grp_ids = NULL;
2540
2541         vnic->rx_queue_cnt = 0;
2542
2543         return 0;
2544 }
2545
2546 static int
2547 bnxt_config_vlan_hw_stripping(struct bnxt *bp, uint64_t rx_offloads)
2548 {
2549         struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp);
2550         int rc;
2551
2552         /* Destroy, recreate and reconfigure the default vnic */
2553         rc = bnxt_free_one_vnic(bp, 0);
2554         if (rc)
2555                 return rc;
2556
2557         /* default vnic 0 */
2558         rc = bnxt_setup_one_vnic(bp, 0);
2559         if (rc)
2560                 return rc;
2561
2562         if (bp->eth_dev->data->dev_conf.rxmode.offloads &
2563             DEV_RX_OFFLOAD_VLAN_FILTER) {
2564                 rc = bnxt_add_vlan_filter(bp, 0);
2565                 if (rc)
2566                         return rc;
2567                 rc = bnxt_restore_vlan_filters(bp);
2568                 if (rc)
2569                         return rc;
2570         } else {
2571                 rc = bnxt_add_mac_filter(bp, vnic, NULL, 0, 0);
2572                 if (rc)
2573                         return rc;
2574         }
2575
2576         rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
2577         if (rc)
2578                 return rc;
2579
2580         PMD_DRV_LOG(DEBUG, "VLAN Strip Offload: %d\n",
2581                     !!(rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP));
2582
2583         return rc;
2584 }
2585
2586 static int
2587 bnxt_vlan_offload_set_op(struct rte_eth_dev *dev, int mask)
2588 {
2589         uint64_t rx_offloads = dev->data->dev_conf.rxmode.offloads;
2590         struct bnxt *bp = dev->data->dev_private;
2591         int rc;
2592
2593         rc = is_bnxt_in_error(bp);
2594         if (rc)
2595                 return rc;
2596
2597         /* Filter settings will get applied when port is started */
2598         if (!dev->data->dev_started)
2599                 return 0;
2600
2601         if (mask & ETH_VLAN_FILTER_MASK) {
2602                 /* Enable or disable VLAN filtering */
2603                 rc = bnxt_config_vlan_hw_filter(bp, rx_offloads);
2604                 if (rc)
2605                         return rc;
2606         }
2607
2608         if (mask & ETH_VLAN_STRIP_MASK) {
2609                 /* Enable or disable VLAN stripping */
2610                 rc = bnxt_config_vlan_hw_stripping(bp, rx_offloads);
2611                 if (rc)
2612                         return rc;
2613         }
2614
2615         if (mask & ETH_VLAN_EXTEND_MASK) {
2616                 if (rx_offloads & DEV_RX_OFFLOAD_VLAN_EXTEND)
2617                         PMD_DRV_LOG(DEBUG, "Extend VLAN supported\n");
2618                 else
2619                         PMD_DRV_LOG(INFO, "Extend VLAN unsupported\n");
2620         }
2621
2622         return 0;
2623 }
2624
2625 static int
2626 bnxt_vlan_tpid_set_op(struct rte_eth_dev *dev, enum rte_vlan_type vlan_type,
2627                       uint16_t tpid)
2628 {
2629         struct bnxt *bp = dev->data->dev_private;
2630         int qinq = dev->data->dev_conf.rxmode.offloads &
2631                    DEV_RX_OFFLOAD_VLAN_EXTEND;
2632
2633         if (vlan_type != ETH_VLAN_TYPE_INNER &&
2634             vlan_type != ETH_VLAN_TYPE_OUTER) {
2635                 PMD_DRV_LOG(ERR,
2636                             "Unsupported vlan type.");
2637                 return -EINVAL;
2638         }
2639         if (!qinq) {
2640                 PMD_DRV_LOG(ERR,
2641                             "QinQ not enabled. Needs to be ON as we can "
2642                             "accelerate only outer vlan\n");
2643                 return -EINVAL;
2644         }
2645
2646         if (vlan_type == ETH_VLAN_TYPE_OUTER) {
2647                 switch (tpid) {
2648                 case RTE_ETHER_TYPE_QINQ:
2649                         bp->outer_tpid_bd =
2650                                 TX_BD_LONG_CFA_META_VLAN_TPID_TPID88A8;
2651                                 break;
2652                 case RTE_ETHER_TYPE_VLAN:
2653                         bp->outer_tpid_bd =
2654                                 TX_BD_LONG_CFA_META_VLAN_TPID_TPID8100;
2655                                 break;
2656                 case RTE_ETHER_TYPE_QINQ1:
2657                         bp->outer_tpid_bd =
2658                                 TX_BD_LONG_CFA_META_VLAN_TPID_TPID9100;
2659                                 break;
2660                 case RTE_ETHER_TYPE_QINQ2:
2661                         bp->outer_tpid_bd =
2662                                 TX_BD_LONG_CFA_META_VLAN_TPID_TPID9200;
2663                                 break;
2664                 case RTE_ETHER_TYPE_QINQ3:
2665                         bp->outer_tpid_bd =
2666                                  TX_BD_LONG_CFA_META_VLAN_TPID_TPID9300;
2667                                 break;
2668                 default:
2669                         PMD_DRV_LOG(ERR, "Invalid TPID: %x\n", tpid);
2670                         return -EINVAL;
2671                 }
2672                 bp->outer_tpid_bd |= tpid;
2673                 PMD_DRV_LOG(INFO, "outer_tpid_bd = %x\n", bp->outer_tpid_bd);
2674         } else if (vlan_type == ETH_VLAN_TYPE_INNER) {
2675                 PMD_DRV_LOG(ERR,
2676                             "Can accelerate only outer vlan in QinQ\n");
2677                 return -EINVAL;
2678         }
2679
2680         return 0;
2681 }
2682
2683 static int
2684 bnxt_set_default_mac_addr_op(struct rte_eth_dev *dev,
2685                              struct rte_ether_addr *addr)
2686 {
2687         struct bnxt *bp = dev->data->dev_private;
2688         /* Default Filter is tied to VNIC 0 */
2689         struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp);
2690         int rc;
2691
2692         rc = is_bnxt_in_error(bp);
2693         if (rc)
2694                 return rc;
2695
2696         if (BNXT_VF(bp) && !BNXT_VF_IS_TRUSTED(bp))
2697                 return -EPERM;
2698
2699         if (rte_is_zero_ether_addr(addr))
2700                 return -EINVAL;
2701
2702         /* Filter settings will get applied when port is started */
2703         if (!dev->data->dev_started)
2704                 return 0;
2705
2706         /* Check if the requested MAC is already added */
2707         if (memcmp(addr, bp->mac_addr, RTE_ETHER_ADDR_LEN) == 0)
2708                 return 0;
2709
2710         /* Destroy filter and re-create it */
2711         bnxt_del_dflt_mac_filter(bp, vnic);
2712
2713         memcpy(bp->mac_addr, addr, RTE_ETHER_ADDR_LEN);
2714         if (dev->data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_VLAN_FILTER) {
2715                 /* This filter will allow only untagged packets */
2716                 rc = bnxt_add_vlan_filter(bp, 0);
2717         } else {
2718                 rc = bnxt_add_mac_filter(bp, vnic, addr, 0, 0);
2719         }
2720
2721         PMD_DRV_LOG(DEBUG, "Set MAC addr\n");
2722         return rc;
2723 }
2724
2725 static int
2726 bnxt_dev_set_mc_addr_list_op(struct rte_eth_dev *eth_dev,
2727                           struct rte_ether_addr *mc_addr_set,
2728                           uint32_t nb_mc_addr)
2729 {
2730         struct bnxt *bp = eth_dev->data->dev_private;
2731         char *mc_addr_list = (char *)mc_addr_set;
2732         struct bnxt_vnic_info *vnic;
2733         uint32_t off = 0, i = 0;
2734         int rc;
2735
2736         rc = is_bnxt_in_error(bp);
2737         if (rc)
2738                 return rc;
2739
2740         vnic = BNXT_GET_DEFAULT_VNIC(bp);
2741
2742         if (nb_mc_addr > BNXT_MAX_MC_ADDRS) {
2743                 vnic->flags |= BNXT_VNIC_INFO_ALLMULTI;
2744                 goto allmulti;
2745         }
2746
2747         /* TODO Check for Duplicate mcast addresses */
2748         vnic->flags &= ~BNXT_VNIC_INFO_ALLMULTI;
2749         for (i = 0; i < nb_mc_addr; i++) {
2750                 memcpy(vnic->mc_list + off, &mc_addr_list[i],
2751                         RTE_ETHER_ADDR_LEN);
2752                 off += RTE_ETHER_ADDR_LEN;
2753         }
2754
2755         vnic->mc_addr_cnt = i;
2756         if (vnic->mc_addr_cnt)
2757                 vnic->flags |= BNXT_VNIC_INFO_MCAST;
2758         else
2759                 vnic->flags &= ~BNXT_VNIC_INFO_MCAST;
2760
2761 allmulti:
2762         return bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
2763 }
2764
2765 static int
2766 bnxt_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size)
2767 {
2768         struct bnxt *bp = dev->data->dev_private;
2769         uint8_t fw_major = (bp->fw_ver >> 24) & 0xff;
2770         uint8_t fw_minor = (bp->fw_ver >> 16) & 0xff;
2771         uint8_t fw_updt = (bp->fw_ver >> 8) & 0xff;
2772         uint8_t fw_rsvd = bp->fw_ver & 0xff;
2773         int ret;
2774
2775         ret = snprintf(fw_version, fw_size, "%d.%d.%d.%d",
2776                         fw_major, fw_minor, fw_updt, fw_rsvd);
2777
2778         ret += 1; /* add the size of '\0' */
2779         if (fw_size < (uint32_t)ret)
2780                 return ret;
2781         else
2782                 return 0;
2783 }
2784
2785 static void
2786 bnxt_rxq_info_get_op(struct rte_eth_dev *dev, uint16_t queue_id,
2787         struct rte_eth_rxq_info *qinfo)
2788 {
2789         struct bnxt *bp = dev->data->dev_private;
2790         struct bnxt_rx_queue *rxq;
2791
2792         if (is_bnxt_in_error(bp))
2793                 return;
2794
2795         rxq = dev->data->rx_queues[queue_id];
2796
2797         qinfo->mp = rxq->mb_pool;
2798         qinfo->scattered_rx = dev->data->scattered_rx;
2799         qinfo->nb_desc = rxq->nb_rx_desc;
2800
2801         qinfo->conf.rx_free_thresh = rxq->rx_free_thresh;
2802         qinfo->conf.rx_drop_en = rxq->drop_en;
2803         qinfo->conf.rx_deferred_start = rxq->rx_deferred_start;
2804         qinfo->conf.offloads = dev->data->dev_conf.rxmode.offloads;
2805 }
2806
2807 static void
2808 bnxt_txq_info_get_op(struct rte_eth_dev *dev, uint16_t queue_id,
2809         struct rte_eth_txq_info *qinfo)
2810 {
2811         struct bnxt *bp = dev->data->dev_private;
2812         struct bnxt_tx_queue *txq;
2813
2814         if (is_bnxt_in_error(bp))
2815                 return;
2816
2817         txq = dev->data->tx_queues[queue_id];
2818
2819         qinfo->nb_desc = txq->nb_tx_desc;
2820
2821         qinfo->conf.tx_thresh.pthresh = txq->pthresh;
2822         qinfo->conf.tx_thresh.hthresh = txq->hthresh;
2823         qinfo->conf.tx_thresh.wthresh = txq->wthresh;
2824
2825         qinfo->conf.tx_free_thresh = txq->tx_free_thresh;
2826         qinfo->conf.tx_rs_thresh = 0;
2827         qinfo->conf.tx_deferred_start = txq->tx_deferred_start;
2828         qinfo->conf.offloads = txq->offloads;
2829 }
2830
2831 static const struct {
2832         eth_rx_burst_t pkt_burst;
2833         const char *info;
2834 } bnxt_rx_burst_info[] = {
2835         {bnxt_recv_pkts,        "Scalar"},
2836 #if defined(RTE_ARCH_X86)
2837         {bnxt_recv_pkts_vec,    "Vector SSE"},
2838 #elif defined(RTE_ARCH_ARM64)
2839         {bnxt_recv_pkts_vec,    "Vector Neon"},
2840 #endif
2841 };
2842
2843 static int
2844 bnxt_rx_burst_mode_get(struct rte_eth_dev *dev, __rte_unused uint16_t queue_id,
2845                        struct rte_eth_burst_mode *mode)
2846 {
2847         eth_rx_burst_t pkt_burst = dev->rx_pkt_burst;
2848         size_t i;
2849
2850         for (i = 0; i < RTE_DIM(bnxt_rx_burst_info); i++) {
2851                 if (pkt_burst == bnxt_rx_burst_info[i].pkt_burst) {
2852                         snprintf(mode->info, sizeof(mode->info), "%s",
2853                                  bnxt_rx_burst_info[i].info);
2854                         return 0;
2855                 }
2856         }
2857
2858         return -EINVAL;
2859 }
2860
2861 static const struct {
2862         eth_tx_burst_t pkt_burst;
2863         const char *info;
2864 } bnxt_tx_burst_info[] = {
2865         {bnxt_xmit_pkts,        "Scalar"},
2866 #if defined(RTE_ARCH_X86)
2867         {bnxt_xmit_pkts_vec,    "Vector SSE"},
2868 #elif defined(RTE_ARCH_ARM64)
2869         {bnxt_xmit_pkts_vec,    "Vector Neon"},
2870 #endif
2871 };
2872
2873 static int
2874 bnxt_tx_burst_mode_get(struct rte_eth_dev *dev, __rte_unused uint16_t queue_id,
2875                        struct rte_eth_burst_mode *mode)
2876 {
2877         eth_tx_burst_t pkt_burst = dev->tx_pkt_burst;
2878         size_t i;
2879
2880         for (i = 0; i < RTE_DIM(bnxt_tx_burst_info); i++) {
2881                 if (pkt_burst == bnxt_tx_burst_info[i].pkt_burst) {
2882                         snprintf(mode->info, sizeof(mode->info), "%s",
2883                                  bnxt_tx_burst_info[i].info);
2884                         return 0;
2885                 }
2886         }
2887
2888         return -EINVAL;
2889 }
2890
2891 int bnxt_mtu_set_op(struct rte_eth_dev *eth_dev, uint16_t new_mtu)
2892 {
2893         struct bnxt *bp = eth_dev->data->dev_private;
2894         uint32_t new_pkt_size;
2895         uint32_t rc = 0;
2896         uint32_t i;
2897
2898         rc = is_bnxt_in_error(bp);
2899         if (rc)
2900                 return rc;
2901
2902         /* Exit if receive queues are not configured yet */
2903         if (!eth_dev->data->nb_rx_queues)
2904                 return rc;
2905
2906         new_pkt_size = new_mtu + RTE_ETHER_HDR_LEN + RTE_ETHER_CRC_LEN +
2907                        VLAN_TAG_SIZE * BNXT_NUM_VLANS;
2908
2909         /*
2910          * Disallow any MTU change that would require scattered receive support
2911          * if it is not already enabled.
2912          */
2913         if (eth_dev->data->dev_started &&
2914             !eth_dev->data->scattered_rx &&
2915             (new_pkt_size >
2916              eth_dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM)) {
2917                 PMD_DRV_LOG(ERR,
2918                             "MTU change would require scattered rx support. ");
2919                 PMD_DRV_LOG(ERR, "Stop port before changing MTU.\n");
2920                 return -EINVAL;
2921         }
2922
2923         if (new_mtu > RTE_ETHER_MTU) {
2924                 bp->flags |= BNXT_FLAG_JUMBO;
2925                 bp->eth_dev->data->dev_conf.rxmode.offloads |=
2926                         DEV_RX_OFFLOAD_JUMBO_FRAME;
2927         } else {
2928                 bp->eth_dev->data->dev_conf.rxmode.offloads &=
2929                         ~DEV_RX_OFFLOAD_JUMBO_FRAME;
2930                 bp->flags &= ~BNXT_FLAG_JUMBO;
2931         }
2932
2933         /* Is there a change in mtu setting? */
2934         if (eth_dev->data->dev_conf.rxmode.max_rx_pkt_len == new_pkt_size)
2935                 return rc;
2936
2937         for (i = 0; i < bp->nr_vnics; i++) {
2938                 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
2939                 uint16_t size = 0;
2940
2941                 vnic->mru = BNXT_VNIC_MRU(new_mtu);
2942                 rc = bnxt_hwrm_vnic_cfg(bp, vnic);
2943                 if (rc)
2944                         break;
2945
2946                 size = rte_pktmbuf_data_room_size(bp->rx_queues[0]->mb_pool);
2947                 size -= RTE_PKTMBUF_HEADROOM;
2948
2949                 if (size < new_mtu) {
2950                         rc = bnxt_hwrm_vnic_plcmode_cfg(bp, vnic);
2951                         if (rc)
2952                                 return rc;
2953                 }
2954         }
2955
2956         if (!rc)
2957                 eth_dev->data->dev_conf.rxmode.max_rx_pkt_len = new_pkt_size;
2958
2959         PMD_DRV_LOG(INFO, "New MTU is %d\n", new_mtu);
2960
2961         return rc;
2962 }
2963
2964 static int
2965 bnxt_vlan_pvid_set_op(struct rte_eth_dev *dev, uint16_t pvid, int on)
2966 {
2967         struct bnxt *bp = dev->data->dev_private;
2968         uint16_t vlan = bp->vlan;
2969         int rc;
2970
2971         rc = is_bnxt_in_error(bp);
2972         if (rc)
2973                 return rc;
2974
2975         if (!BNXT_SINGLE_PF(bp) || BNXT_VF(bp)) {
2976                 PMD_DRV_LOG(ERR,
2977                         "PVID cannot be modified for this function\n");
2978                 return -ENOTSUP;
2979         }
2980         bp->vlan = on ? pvid : 0;
2981
2982         rc = bnxt_hwrm_set_default_vlan(bp, 0, 0);
2983         if (rc)
2984                 bp->vlan = vlan;
2985         return rc;
2986 }
2987
2988 static int
2989 bnxt_dev_led_on_op(struct rte_eth_dev *dev)
2990 {
2991         struct bnxt *bp = dev->data->dev_private;
2992         int rc;
2993
2994         rc = is_bnxt_in_error(bp);
2995         if (rc)
2996                 return rc;
2997
2998         return bnxt_hwrm_port_led_cfg(bp, true);
2999 }
3000
3001 static int
3002 bnxt_dev_led_off_op(struct rte_eth_dev *dev)
3003 {
3004         struct bnxt *bp = dev->data->dev_private;
3005         int rc;
3006
3007         rc = is_bnxt_in_error(bp);
3008         if (rc)
3009                 return rc;
3010
3011         return bnxt_hwrm_port_led_cfg(bp, false);
3012 }
3013
3014 static uint32_t
3015 bnxt_rx_queue_count_op(struct rte_eth_dev *dev, uint16_t rx_queue_id)
3016 {
3017         struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
3018         struct bnxt_cp_ring_info *cpr;
3019         uint32_t desc = 0, raw_cons;
3020         struct bnxt_rx_queue *rxq;
3021         struct rx_pkt_cmpl *rxcmp;
3022         int rc;
3023
3024         rc = is_bnxt_in_error(bp);
3025         if (rc)
3026                 return rc;
3027
3028         rxq = dev->data->rx_queues[rx_queue_id];
3029         cpr = rxq->cp_ring;
3030         raw_cons = cpr->cp_raw_cons;
3031
3032         while (1) {
3033                 uint32_t agg_cnt, cons, cmpl_type;
3034
3035                 cons = RING_CMP(cpr->cp_ring_struct, raw_cons);
3036                 rxcmp = (struct rx_pkt_cmpl *)&cpr->cp_desc_ring[cons];
3037
3038                 if (!CMP_VALID(rxcmp, raw_cons, cpr->cp_ring_struct))
3039                         break;
3040
3041                 cmpl_type = CMP_TYPE(rxcmp);
3042
3043                 switch (cmpl_type) {
3044                 case CMPL_BASE_TYPE_RX_L2:
3045                 case CMPL_BASE_TYPE_RX_L2_V2:
3046                         agg_cnt = BNXT_RX_L2_AGG_BUFS(rxcmp);
3047                         raw_cons = raw_cons + CMP_LEN(cmpl_type) + agg_cnt;
3048                         desc++;
3049                         break;
3050
3051                 case CMPL_BASE_TYPE_RX_TPA_END:
3052                         if (BNXT_CHIP_P5(rxq->bp)) {
3053                                 struct rx_tpa_v2_end_cmpl_hi *p5_tpa_end;
3054
3055                                 p5_tpa_end = (void *)rxcmp;
3056                                 agg_cnt = BNXT_TPA_END_AGG_BUFS_TH(p5_tpa_end);
3057                         } else {
3058                                 struct rx_tpa_end_cmpl *tpa_end;
3059
3060                                 tpa_end = (void *)rxcmp;
3061                                 agg_cnt = BNXT_TPA_END_AGG_BUFS(tpa_end);
3062                         }
3063
3064                         raw_cons = raw_cons + CMP_LEN(cmpl_type) + agg_cnt;
3065                         desc++;
3066                         break;
3067
3068                 default:
3069                         raw_cons += CMP_LEN(cmpl_type);
3070                 }
3071         }
3072
3073         return desc;
3074 }
3075
3076 static int
3077 bnxt_rx_descriptor_status_op(void *rx_queue, uint16_t offset)
3078 {
3079         struct bnxt_rx_queue *rxq = rx_queue;
3080         struct bnxt_cp_ring_info *cpr;
3081         struct bnxt_rx_ring_info *rxr;
3082         uint32_t desc, raw_cons;
3083         struct bnxt *bp = rxq->bp;
3084         struct rx_pkt_cmpl *rxcmp;
3085         int rc;
3086
3087         rc = is_bnxt_in_error(bp);
3088         if (rc)
3089                 return rc;
3090
3091         if (offset >= rxq->nb_rx_desc)
3092                 return -EINVAL;
3093
3094         rxr = rxq->rx_ring;
3095         cpr = rxq->cp_ring;
3096
3097         /*
3098          * For the vector receive case, the completion at the requested
3099          * offset can be indexed directly.
3100          */
3101 #if defined(RTE_ARCH_X86) || defined(RTE_ARCH_ARM64)
3102         if (bp->flags & BNXT_FLAG_RX_VECTOR_PKT_MODE) {
3103                 struct rx_pkt_cmpl *rxcmp;
3104                 uint32_t cons;
3105
3106                 /* Check status of completion descriptor. */
3107                 raw_cons = cpr->cp_raw_cons +
3108                            offset * CMP_LEN(CMPL_BASE_TYPE_RX_L2);
3109                 cons = RING_CMP(cpr->cp_ring_struct, raw_cons);
3110                 rxcmp = (struct rx_pkt_cmpl *)&cpr->cp_desc_ring[cons];
3111
3112                 if (CMP_VALID(rxcmp, raw_cons, cpr->cp_ring_struct))
3113                         return RTE_ETH_RX_DESC_DONE;
3114
3115                 /* Check whether rx desc has an mbuf attached. */
3116                 cons = RING_CMP(rxr->rx_ring_struct, raw_cons / 2);
3117                 if (cons >= rxq->rxrearm_start &&
3118                     cons < rxq->rxrearm_start + rxq->rxrearm_nb) {
3119                         return RTE_ETH_RX_DESC_UNAVAIL;
3120                 }
3121
3122                 return RTE_ETH_RX_DESC_AVAIL;
3123         }
3124 #endif
3125
3126         /*
3127          * For the non-vector receive case, scan the completion ring to
3128          * locate the completion descriptor for the requested offset.
3129          */
3130         raw_cons = cpr->cp_raw_cons;
3131         desc = 0;
3132         while (1) {
3133                 uint32_t agg_cnt, cons, cmpl_type;
3134
3135                 cons = RING_CMP(cpr->cp_ring_struct, raw_cons);
3136                 rxcmp = (struct rx_pkt_cmpl *)&cpr->cp_desc_ring[cons];
3137
3138                 if (!CMP_VALID(rxcmp, raw_cons, cpr->cp_ring_struct))
3139                         break;
3140
3141                 cmpl_type = CMP_TYPE(rxcmp);
3142
3143                 switch (cmpl_type) {
3144                 case CMPL_BASE_TYPE_RX_L2:
3145                 case CMPL_BASE_TYPE_RX_L2_V2:
3146                         if (desc == offset) {
3147                                 cons = rxcmp->opaque;
3148                                 if (rxr->rx_buf_ring[cons])
3149                                         return RTE_ETH_RX_DESC_DONE;
3150                                 else
3151                                         return RTE_ETH_RX_DESC_UNAVAIL;
3152                         }
3153                         agg_cnt = BNXT_RX_L2_AGG_BUFS(rxcmp);
3154                         raw_cons = raw_cons + CMP_LEN(cmpl_type) + agg_cnt;
3155                         desc++;
3156                         break;
3157
3158                 case CMPL_BASE_TYPE_RX_TPA_END:
3159                         if (desc == offset)
3160                                 return RTE_ETH_RX_DESC_DONE;
3161
3162                         if (BNXT_CHIP_P5(rxq->bp)) {
3163                                 struct rx_tpa_v2_end_cmpl_hi *p5_tpa_end;
3164
3165                                 p5_tpa_end = (void *)rxcmp;
3166                                 agg_cnt = BNXT_TPA_END_AGG_BUFS_TH(p5_tpa_end);
3167                         } else {
3168                                 struct rx_tpa_end_cmpl *tpa_end;
3169
3170                                 tpa_end = (void *)rxcmp;
3171                                 agg_cnt = BNXT_TPA_END_AGG_BUFS(tpa_end);
3172                         }
3173
3174                         raw_cons = raw_cons + CMP_LEN(cmpl_type) + agg_cnt;
3175                         desc++;
3176                         break;
3177
3178                 default:
3179                         raw_cons += CMP_LEN(cmpl_type);
3180                 }
3181         }
3182
3183         return RTE_ETH_RX_DESC_AVAIL;
3184 }
3185
3186 static int
3187 bnxt_tx_descriptor_status_op(void *tx_queue, uint16_t offset)
3188 {
3189         struct bnxt_tx_queue *txq = (struct bnxt_tx_queue *)tx_queue;
3190         struct bnxt_tx_ring_info *txr;
3191         struct bnxt_cp_ring_info *cpr;
3192         struct rte_mbuf **tx_buf;
3193         struct tx_pkt_cmpl *txcmp;
3194         uint32_t cons, cp_cons;
3195         int rc;
3196
3197         if (!txq)
3198                 return -EINVAL;
3199
3200         rc = is_bnxt_in_error(txq->bp);
3201         if (rc)
3202                 return rc;
3203
3204         cpr = txq->cp_ring;
3205         txr = txq->tx_ring;
3206
3207         if (offset >= txq->nb_tx_desc)
3208                 return -EINVAL;
3209
3210         cons = RING_CMP(cpr->cp_ring_struct, offset);
3211         txcmp = (struct tx_pkt_cmpl *)&cpr->cp_desc_ring[cons];
3212         cp_cons = cpr->cp_raw_cons;
3213
3214         if (cons > cp_cons) {
3215                 if (CMPL_VALID(txcmp, cpr->valid))
3216                         return RTE_ETH_TX_DESC_UNAVAIL;
3217         } else {
3218                 if (CMPL_VALID(txcmp, !cpr->valid))
3219                         return RTE_ETH_TX_DESC_UNAVAIL;
3220         }
3221         tx_buf = &txr->tx_buf_ring[cons];
3222         if (*tx_buf == NULL)
3223                 return RTE_ETH_TX_DESC_DONE;
3224
3225         return RTE_ETH_TX_DESC_FULL;
3226 }
3227
3228 int
3229 bnxt_filter_ctrl_op(struct rte_eth_dev *dev,
3230                     enum rte_filter_type filter_type,
3231                     enum rte_filter_op filter_op, void *arg)
3232 {
3233         struct bnxt *bp = dev->data->dev_private;
3234         int ret = 0;
3235
3236         if (!bp)
3237                 return -EIO;
3238
3239         if (BNXT_ETH_DEV_IS_REPRESENTOR(dev)) {
3240                 struct bnxt_representor *vfr = dev->data->dev_private;
3241                 bp = vfr->parent_dev->data->dev_private;
3242                 /* parent is deleted while children are still valid */
3243                 if (!bp) {
3244                         PMD_DRV_LOG(DEBUG, "BNXT Port:%d VFR Error %d:%d\n",
3245                                     dev->data->port_id,
3246                                     filter_type,
3247                                     filter_op);
3248                         return -EIO;
3249                 }
3250         }
3251
3252         ret = is_bnxt_in_error(bp);
3253         if (ret)
3254                 return ret;
3255
3256         switch (filter_type) {
3257         case RTE_ETH_FILTER_GENERIC:
3258                 if (filter_op != RTE_ETH_FILTER_GET)
3259                         return -EINVAL;
3260
3261                 /* PMD supports thread-safe flow operations.  rte_flow API
3262                  * functions can avoid mutex for multi-thread safety.
3263                  */
3264                 dev->data->dev_flags |= RTE_ETH_DEV_FLOW_OPS_THREAD_SAFE;
3265
3266                 if (BNXT_TRUFLOW_EN(bp))
3267                         *(const void **)arg = &bnxt_ulp_rte_flow_ops;
3268                 else
3269                         *(const void **)arg = &bnxt_flow_ops;
3270                 break;
3271         default:
3272                 PMD_DRV_LOG(ERR,
3273                         "Filter type (%d) not supported", filter_type);
3274                 ret = -EINVAL;
3275                 break;
3276         }
3277         return ret;
3278 }
3279
3280 static const uint32_t *
3281 bnxt_dev_supported_ptypes_get_op(struct rte_eth_dev *dev)
3282 {
3283         static const uint32_t ptypes[] = {
3284                 RTE_PTYPE_L2_ETHER_VLAN,
3285                 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN,
3286                 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN,
3287                 RTE_PTYPE_L4_ICMP,
3288                 RTE_PTYPE_L4_TCP,
3289                 RTE_PTYPE_L4_UDP,
3290                 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN,
3291                 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN,
3292                 RTE_PTYPE_INNER_L4_ICMP,
3293                 RTE_PTYPE_INNER_L4_TCP,
3294                 RTE_PTYPE_INNER_L4_UDP,
3295                 RTE_PTYPE_UNKNOWN
3296         };
3297
3298         if (!dev->rx_pkt_burst)
3299                 return NULL;
3300
3301         return ptypes;
3302 }
3303
3304 static int bnxt_map_regs(struct bnxt *bp, uint32_t *reg_arr, int count,
3305                          int reg_win)
3306 {
3307         uint32_t reg_base = *reg_arr & 0xfffff000;
3308         uint32_t win_off;
3309         int i;
3310
3311         for (i = 0; i < count; i++) {
3312                 if ((reg_arr[i] & 0xfffff000) != reg_base)
3313                         return -ERANGE;
3314         }
3315         win_off = BNXT_GRCPF_REG_WINDOW_BASE_OUT + (reg_win - 1) * 4;
3316         rte_write32(reg_base, (uint8_t *)bp->bar0 + win_off);
3317         return 0;
3318 }
3319
3320 static int bnxt_map_ptp_regs(struct bnxt *bp)
3321 {
3322         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3323         uint32_t *reg_arr;
3324         int rc, i;
3325
3326         reg_arr = ptp->rx_regs;
3327         rc = bnxt_map_regs(bp, reg_arr, BNXT_PTP_RX_REGS, 5);
3328         if (rc)
3329                 return rc;
3330
3331         reg_arr = ptp->tx_regs;
3332         rc = bnxt_map_regs(bp, reg_arr, BNXT_PTP_TX_REGS, 6);
3333         if (rc)
3334                 return rc;
3335
3336         for (i = 0; i < BNXT_PTP_RX_REGS; i++)
3337                 ptp->rx_mapped_regs[i] = 0x5000 + (ptp->rx_regs[i] & 0xfff);
3338
3339         for (i = 0; i < BNXT_PTP_TX_REGS; i++)
3340                 ptp->tx_mapped_regs[i] = 0x6000 + (ptp->tx_regs[i] & 0xfff);
3341
3342         return 0;
3343 }
3344
3345 static void bnxt_unmap_ptp_regs(struct bnxt *bp)
3346 {
3347         rte_write32(0, (uint8_t *)bp->bar0 +
3348                          BNXT_GRCPF_REG_WINDOW_BASE_OUT + 16);
3349         rte_write32(0, (uint8_t *)bp->bar0 +
3350                          BNXT_GRCPF_REG_WINDOW_BASE_OUT + 20);
3351 }
3352
3353 static uint64_t bnxt_cc_read(struct bnxt *bp)
3354 {
3355         uint64_t ns;
3356
3357         ns = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3358                               BNXT_GRCPF_REG_SYNC_TIME));
3359         ns |= (uint64_t)(rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3360                                           BNXT_GRCPF_REG_SYNC_TIME + 4))) << 32;
3361         return ns;
3362 }
3363
3364 static int bnxt_get_tx_ts(struct bnxt *bp, uint64_t *ts)
3365 {
3366         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3367         uint32_t fifo;
3368
3369         fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3370                                 ptp->tx_mapped_regs[BNXT_PTP_TX_FIFO]));
3371         if (fifo & BNXT_PTP_TX_FIFO_EMPTY)
3372                 return -EAGAIN;
3373
3374         fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3375                                 ptp->tx_mapped_regs[BNXT_PTP_TX_FIFO]));
3376         *ts = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3377                                 ptp->tx_mapped_regs[BNXT_PTP_TX_TS_L]));
3378         *ts |= (uint64_t)rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3379                                 ptp->tx_mapped_regs[BNXT_PTP_TX_TS_H])) << 32;
3380
3381         return 0;
3382 }
3383
3384 static int bnxt_get_rx_ts(struct bnxt *bp, uint64_t *ts)
3385 {
3386         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3387         struct bnxt_pf_info *pf = bp->pf;
3388         uint16_t port_id;
3389         uint32_t fifo;
3390
3391         if (!ptp)
3392                 return -ENODEV;
3393
3394         fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3395                                 ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO]));
3396         if (!(fifo & BNXT_PTP_RX_FIFO_PENDING))
3397                 return -EAGAIN;
3398
3399         port_id = pf->port_id;
3400         rte_write32(1 << port_id, (uint8_t *)bp->bar0 +
3401                ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO_ADV]);
3402
3403         fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3404                                    ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO]));
3405         if (fifo & BNXT_PTP_RX_FIFO_PENDING) {
3406 /*              bnxt_clr_rx_ts(bp);       TBD  */
3407                 return -EBUSY;
3408         }
3409
3410         *ts = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3411                                 ptp->rx_mapped_regs[BNXT_PTP_RX_TS_L]));
3412         *ts |= (uint64_t)rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3413                                 ptp->rx_mapped_regs[BNXT_PTP_RX_TS_H])) << 32;
3414
3415         return 0;
3416 }
3417
3418 static int
3419 bnxt_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
3420 {
3421         uint64_t ns;
3422         struct bnxt *bp = dev->data->dev_private;
3423         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3424
3425         if (!ptp)
3426                 return 0;
3427
3428         ns = rte_timespec_to_ns(ts);
3429         /* Set the timecounters to a new value. */
3430         ptp->tc.nsec = ns;
3431
3432         return 0;
3433 }
3434
3435 static int
3436 bnxt_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
3437 {
3438         struct bnxt *bp = dev->data->dev_private;
3439         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3440         uint64_t ns, systime_cycles = 0;
3441         int rc = 0;
3442
3443         if (!ptp)
3444                 return 0;
3445
3446         if (BNXT_CHIP_P5(bp))
3447                 rc = bnxt_hwrm_port_ts_query(bp, BNXT_PTP_FLAGS_CURRENT_TIME,
3448                                              &systime_cycles);
3449         else
3450                 systime_cycles = bnxt_cc_read(bp);
3451
3452         ns = rte_timecounter_update(&ptp->tc, systime_cycles);
3453         *ts = rte_ns_to_timespec(ns);
3454
3455         return rc;
3456 }
3457 static int
3458 bnxt_timesync_enable(struct rte_eth_dev *dev)
3459 {
3460         struct bnxt *bp = dev->data->dev_private;
3461         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3462         uint32_t shift = 0;
3463         int rc;
3464
3465         if (!ptp)
3466                 return 0;
3467
3468         ptp->rx_filter = 1;
3469         ptp->tx_tstamp_en = 1;
3470         ptp->rxctl = BNXT_PTP_MSG_EVENTS;
3471
3472         rc = bnxt_hwrm_ptp_cfg(bp);
3473         if (rc)
3474                 return rc;
3475
3476         memset(&ptp->tc, 0, sizeof(struct rte_timecounter));
3477         memset(&ptp->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
3478         memset(&ptp->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
3479
3480         ptp->tc.cc_mask = BNXT_CYCLECOUNTER_MASK;
3481         ptp->tc.cc_shift = shift;
3482         ptp->tc.nsec_mask = (1ULL << shift) - 1;
3483
3484         ptp->rx_tstamp_tc.cc_mask = BNXT_CYCLECOUNTER_MASK;
3485         ptp->rx_tstamp_tc.cc_shift = shift;
3486         ptp->rx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
3487
3488         ptp->tx_tstamp_tc.cc_mask = BNXT_CYCLECOUNTER_MASK;
3489         ptp->tx_tstamp_tc.cc_shift = shift;
3490         ptp->tx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
3491
3492         if (!BNXT_CHIP_P5(bp))
3493                 bnxt_map_ptp_regs(bp);
3494         else
3495                 rc = bnxt_ptp_start(bp);
3496
3497         return rc;
3498 }
3499
3500 static int
3501 bnxt_timesync_disable(struct rte_eth_dev *dev)
3502 {
3503         struct bnxt *bp = dev->data->dev_private;
3504         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3505
3506         if (!ptp)
3507                 return 0;
3508
3509         ptp->rx_filter = 0;
3510         ptp->tx_tstamp_en = 0;
3511         ptp->rxctl = 0;
3512
3513         bnxt_hwrm_ptp_cfg(bp);
3514
3515         if (!BNXT_CHIP_P5(bp))
3516                 bnxt_unmap_ptp_regs(bp);
3517         else
3518                 bnxt_ptp_stop(bp);
3519
3520         return 0;
3521 }
3522
3523 static int
3524 bnxt_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
3525                                  struct timespec *timestamp,
3526                                  uint32_t flags __rte_unused)
3527 {
3528         struct bnxt *bp = dev->data->dev_private;
3529         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3530         uint64_t rx_tstamp_cycles = 0;
3531         uint64_t ns;
3532
3533         if (!ptp)
3534                 return 0;
3535
3536         if (BNXT_CHIP_P5(bp))
3537                 rx_tstamp_cycles = ptp->rx_timestamp;
3538         else
3539                 bnxt_get_rx_ts(bp, &rx_tstamp_cycles);
3540
3541         ns = rte_timecounter_update(&ptp->rx_tstamp_tc, rx_tstamp_cycles);
3542         *timestamp = rte_ns_to_timespec(ns);
3543         return  0;
3544 }
3545
3546 static int
3547 bnxt_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
3548                                  struct timespec *timestamp)
3549 {
3550         struct bnxt *bp = dev->data->dev_private;
3551         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3552         uint64_t tx_tstamp_cycles = 0;
3553         uint64_t ns;
3554         int rc = 0;
3555
3556         if (!ptp)
3557                 return 0;
3558
3559         if (BNXT_CHIP_P5(bp))
3560                 rc = bnxt_hwrm_port_ts_query(bp, BNXT_PTP_FLAGS_PATH_TX,
3561                                              &tx_tstamp_cycles);
3562         else
3563                 rc = bnxt_get_tx_ts(bp, &tx_tstamp_cycles);
3564
3565         ns = rte_timecounter_update(&ptp->tx_tstamp_tc, tx_tstamp_cycles);
3566         *timestamp = rte_ns_to_timespec(ns);
3567
3568         return rc;
3569 }
3570
3571 static int
3572 bnxt_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
3573 {
3574         struct bnxt *bp = dev->data->dev_private;
3575         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3576
3577         if (!ptp)
3578                 return 0;
3579
3580         ptp->tc.nsec += delta;
3581
3582         return 0;
3583 }
3584
3585 static int
3586 bnxt_get_eeprom_length_op(struct rte_eth_dev *dev)
3587 {
3588         struct bnxt *bp = dev->data->dev_private;
3589         int rc;
3590         uint32_t dir_entries;
3591         uint32_t entry_length;
3592
3593         rc = is_bnxt_in_error(bp);
3594         if (rc)
3595                 return rc;
3596
3597         PMD_DRV_LOG(INFO, PCI_PRI_FMT "\n",
3598                     bp->pdev->addr.domain, bp->pdev->addr.bus,
3599                     bp->pdev->addr.devid, bp->pdev->addr.function);
3600
3601         rc = bnxt_hwrm_nvm_get_dir_info(bp, &dir_entries, &entry_length);
3602         if (rc != 0)
3603                 return rc;
3604
3605         return dir_entries * entry_length;
3606 }
3607
3608 static int
3609 bnxt_get_eeprom_op(struct rte_eth_dev *dev,
3610                 struct rte_dev_eeprom_info *in_eeprom)
3611 {
3612         struct bnxt *bp = dev->data->dev_private;
3613         uint32_t index;
3614         uint32_t offset;
3615         int rc;
3616
3617         rc = is_bnxt_in_error(bp);
3618         if (rc)
3619                 return rc;
3620
3621         PMD_DRV_LOG(INFO, PCI_PRI_FMT " in_eeprom->offset = %d len = %d\n",
3622                     bp->pdev->addr.domain, bp->pdev->addr.bus,
3623                     bp->pdev->addr.devid, bp->pdev->addr.function,
3624                     in_eeprom->offset, in_eeprom->length);
3625
3626         if (in_eeprom->offset == 0) /* special offset value to get directory */
3627                 return bnxt_get_nvram_directory(bp, in_eeprom->length,
3628                                                 in_eeprom->data);
3629
3630         index = in_eeprom->offset >> 24;
3631         offset = in_eeprom->offset & 0xffffff;
3632
3633         if (index != 0)
3634                 return bnxt_hwrm_get_nvram_item(bp, index - 1, offset,
3635                                            in_eeprom->length, in_eeprom->data);
3636
3637         return 0;
3638 }
3639
3640 static bool bnxt_dir_type_is_ape_bin_format(uint16_t dir_type)
3641 {
3642         switch (dir_type) {
3643         case BNX_DIR_TYPE_CHIMP_PATCH:
3644         case BNX_DIR_TYPE_BOOTCODE:
3645         case BNX_DIR_TYPE_BOOTCODE_2:
3646         case BNX_DIR_TYPE_APE_FW:
3647         case BNX_DIR_TYPE_APE_PATCH:
3648         case BNX_DIR_TYPE_KONG_FW:
3649         case BNX_DIR_TYPE_KONG_PATCH:
3650         case BNX_DIR_TYPE_BONO_FW:
3651         case BNX_DIR_TYPE_BONO_PATCH:
3652                 /* FALLTHROUGH */
3653                 return true;
3654         }
3655
3656         return false;
3657 }
3658
3659 static bool bnxt_dir_type_is_other_exec_format(uint16_t dir_type)
3660 {
3661         switch (dir_type) {
3662         case BNX_DIR_TYPE_AVS:
3663         case BNX_DIR_TYPE_EXP_ROM_MBA:
3664         case BNX_DIR_TYPE_PCIE:
3665         case BNX_DIR_TYPE_TSCF_UCODE:
3666         case BNX_DIR_TYPE_EXT_PHY:
3667         case BNX_DIR_TYPE_CCM:
3668         case BNX_DIR_TYPE_ISCSI_BOOT:
3669         case BNX_DIR_TYPE_ISCSI_BOOT_IPV6:
3670         case BNX_DIR_TYPE_ISCSI_BOOT_IPV4N6:
3671                 /* FALLTHROUGH */
3672                 return true;
3673         }
3674
3675         return false;
3676 }
3677
3678 static bool bnxt_dir_type_is_executable(uint16_t dir_type)
3679 {
3680         return bnxt_dir_type_is_ape_bin_format(dir_type) ||
3681                 bnxt_dir_type_is_other_exec_format(dir_type);
3682 }
3683
3684 static int
3685 bnxt_set_eeprom_op(struct rte_eth_dev *dev,
3686                 struct rte_dev_eeprom_info *in_eeprom)
3687 {
3688         struct bnxt *bp = dev->data->dev_private;
3689         uint8_t index, dir_op;
3690         uint16_t type, ext, ordinal, attr;
3691         int rc;
3692
3693         rc = is_bnxt_in_error(bp);
3694         if (rc)
3695                 return rc;
3696
3697         PMD_DRV_LOG(INFO, PCI_PRI_FMT " in_eeprom->offset = %d len = %d\n",
3698                     bp->pdev->addr.domain, bp->pdev->addr.bus,
3699                     bp->pdev->addr.devid, bp->pdev->addr.function,
3700                     in_eeprom->offset, in_eeprom->length);
3701
3702         if (!BNXT_PF(bp)) {
3703                 PMD_DRV_LOG(ERR, "NVM write not supported from a VF\n");
3704                 return -EINVAL;
3705         }
3706
3707         type = in_eeprom->magic >> 16;
3708
3709         if (type == 0xffff) { /* special value for directory operations */
3710                 index = in_eeprom->magic & 0xff;
3711                 dir_op = in_eeprom->magic >> 8;
3712                 if (index == 0)
3713                         return -EINVAL;
3714                 switch (dir_op) {
3715                 case 0x0e: /* erase */
3716                         if (in_eeprom->offset != ~in_eeprom->magic)
3717                                 return -EINVAL;
3718                         return bnxt_hwrm_erase_nvram_directory(bp, index - 1);
3719                 default:
3720                         return -EINVAL;
3721                 }
3722         }
3723
3724         /* Create or re-write an NVM item: */
3725         if (bnxt_dir_type_is_executable(type) == true)
3726                 return -EOPNOTSUPP;
3727         ext = in_eeprom->magic & 0xffff;
3728         ordinal = in_eeprom->offset >> 16;
3729         attr = in_eeprom->offset & 0xffff;
3730
3731         return bnxt_hwrm_flash_nvram(bp, type, ordinal, ext, attr,
3732                                      in_eeprom->data, in_eeprom->length);
3733 }
3734
3735 /*
3736  * Initialization
3737  */
3738
3739 static const struct eth_dev_ops bnxt_dev_ops = {
3740         .dev_infos_get = bnxt_dev_info_get_op,
3741         .dev_close = bnxt_dev_close_op,
3742         .dev_configure = bnxt_dev_configure_op,
3743         .dev_start = bnxt_dev_start_op,
3744         .dev_stop = bnxt_dev_stop_op,
3745         .dev_set_link_up = bnxt_dev_set_link_up_op,
3746         .dev_set_link_down = bnxt_dev_set_link_down_op,
3747         .stats_get = bnxt_stats_get_op,
3748         .stats_reset = bnxt_stats_reset_op,
3749         .rx_queue_setup = bnxt_rx_queue_setup_op,
3750         .rx_queue_release = bnxt_rx_queue_release_op,
3751         .tx_queue_setup = bnxt_tx_queue_setup_op,
3752         .tx_queue_release = bnxt_tx_queue_release_op,
3753         .rx_queue_intr_enable = bnxt_rx_queue_intr_enable_op,
3754         .rx_queue_intr_disable = bnxt_rx_queue_intr_disable_op,
3755         .reta_update = bnxt_reta_update_op,
3756         .reta_query = bnxt_reta_query_op,
3757         .rss_hash_update = bnxt_rss_hash_update_op,
3758         .rss_hash_conf_get = bnxt_rss_hash_conf_get_op,
3759         .link_update = bnxt_link_update_op,
3760         .promiscuous_enable = bnxt_promiscuous_enable_op,
3761         .promiscuous_disable = bnxt_promiscuous_disable_op,
3762         .allmulticast_enable = bnxt_allmulticast_enable_op,
3763         .allmulticast_disable = bnxt_allmulticast_disable_op,
3764         .mac_addr_add = bnxt_mac_addr_add_op,
3765         .mac_addr_remove = bnxt_mac_addr_remove_op,
3766         .flow_ctrl_get = bnxt_flow_ctrl_get_op,
3767         .flow_ctrl_set = bnxt_flow_ctrl_set_op,
3768         .udp_tunnel_port_add  = bnxt_udp_tunnel_port_add_op,
3769         .udp_tunnel_port_del  = bnxt_udp_tunnel_port_del_op,
3770         .vlan_filter_set = bnxt_vlan_filter_set_op,
3771         .vlan_offload_set = bnxt_vlan_offload_set_op,
3772         .vlan_tpid_set = bnxt_vlan_tpid_set_op,
3773         .vlan_pvid_set = bnxt_vlan_pvid_set_op,
3774         .mtu_set = bnxt_mtu_set_op,
3775         .mac_addr_set = bnxt_set_default_mac_addr_op,
3776         .xstats_get = bnxt_dev_xstats_get_op,
3777         .xstats_get_names = bnxt_dev_xstats_get_names_op,
3778         .xstats_reset = bnxt_dev_xstats_reset_op,
3779         .fw_version_get = bnxt_fw_version_get,
3780         .set_mc_addr_list = bnxt_dev_set_mc_addr_list_op,
3781         .rxq_info_get = bnxt_rxq_info_get_op,
3782         .txq_info_get = bnxt_txq_info_get_op,
3783         .rx_burst_mode_get = bnxt_rx_burst_mode_get,
3784         .tx_burst_mode_get = bnxt_tx_burst_mode_get,
3785         .dev_led_on = bnxt_dev_led_on_op,
3786         .dev_led_off = bnxt_dev_led_off_op,
3787         .rx_queue_start = bnxt_rx_queue_start,
3788         .rx_queue_stop = bnxt_rx_queue_stop,
3789         .tx_queue_start = bnxt_tx_queue_start,
3790         .tx_queue_stop = bnxt_tx_queue_stop,
3791         .filter_ctrl = bnxt_filter_ctrl_op,
3792         .dev_supported_ptypes_get = bnxt_dev_supported_ptypes_get_op,
3793         .get_eeprom_length    = bnxt_get_eeprom_length_op,
3794         .get_eeprom           = bnxt_get_eeprom_op,
3795         .set_eeprom           = bnxt_set_eeprom_op,
3796         .timesync_enable      = bnxt_timesync_enable,
3797         .timesync_disable     = bnxt_timesync_disable,
3798         .timesync_read_time   = bnxt_timesync_read_time,
3799         .timesync_write_time   = bnxt_timesync_write_time,
3800         .timesync_adjust_time = bnxt_timesync_adjust_time,
3801         .timesync_read_rx_timestamp = bnxt_timesync_read_rx_timestamp,
3802         .timesync_read_tx_timestamp = bnxt_timesync_read_tx_timestamp,
3803 };
3804
3805 static uint32_t bnxt_map_reset_regs(struct bnxt *bp, uint32_t reg)
3806 {
3807         uint32_t offset;
3808
3809         /* Only pre-map the reset GRC registers using window 3 */
3810         rte_write32(reg & 0xfffff000, (uint8_t *)bp->bar0 +
3811                     BNXT_GRCPF_REG_WINDOW_BASE_OUT + 8);
3812
3813         offset = BNXT_GRCP_WINDOW_3_BASE + (reg & 0xffc);
3814
3815         return offset;
3816 }
3817
3818 int bnxt_map_fw_health_status_regs(struct bnxt *bp)
3819 {
3820         struct bnxt_error_recovery_info *info = bp->recovery_info;
3821         uint32_t reg_base = 0xffffffff;
3822         int i;
3823
3824         /* Only pre-map the monitoring GRC registers using window 2 */
3825         for (i = 0; i < BNXT_FW_STATUS_REG_CNT; i++) {
3826                 uint32_t reg = info->status_regs[i];
3827
3828                 if (BNXT_FW_STATUS_REG_TYPE(reg) != BNXT_FW_STATUS_REG_TYPE_GRC)
3829                         continue;
3830
3831                 if (reg_base == 0xffffffff)
3832                         reg_base = reg & 0xfffff000;
3833                 if ((reg & 0xfffff000) != reg_base)
3834                         return -ERANGE;
3835
3836                 /* Use mask 0xffc as the Lower 2 bits indicates
3837                  * address space location
3838                  */
3839                 info->mapped_status_regs[i] = BNXT_GRCP_WINDOW_2_BASE +
3840                                                 (reg & 0xffc);
3841         }
3842
3843         if (reg_base == 0xffffffff)
3844                 return 0;
3845
3846         rte_write32(reg_base, (uint8_t *)bp->bar0 +
3847                     BNXT_GRCPF_REG_WINDOW_BASE_OUT + 4);
3848
3849         return 0;
3850 }
3851
3852 static void bnxt_write_fw_reset_reg(struct bnxt *bp, uint32_t index)
3853 {
3854         struct bnxt_error_recovery_info *info = bp->recovery_info;
3855         uint32_t delay = info->delay_after_reset[index];
3856         uint32_t val = info->reset_reg_val[index];
3857         uint32_t reg = info->reset_reg[index];
3858         uint32_t type, offset;
3859
3860         type = BNXT_FW_STATUS_REG_TYPE(reg);
3861         offset = BNXT_FW_STATUS_REG_OFF(reg);
3862
3863         switch (type) {
3864         case BNXT_FW_STATUS_REG_TYPE_CFG:
3865                 rte_pci_write_config(bp->pdev, &val, sizeof(val), offset);
3866                 break;
3867         case BNXT_FW_STATUS_REG_TYPE_GRC:
3868                 offset = bnxt_map_reset_regs(bp, offset);
3869                 rte_write32(val, (uint8_t *)bp->bar0 + offset);
3870                 break;
3871         case BNXT_FW_STATUS_REG_TYPE_BAR0:
3872                 rte_write32(val, (uint8_t *)bp->bar0 + offset);
3873                 break;
3874         }
3875         /* wait on a specific interval of time until core reset is complete */
3876         if (delay)
3877                 rte_delay_ms(delay);
3878 }
3879
3880 static void bnxt_dev_cleanup(struct bnxt *bp)
3881 {
3882         bp->eth_dev->data->dev_link.link_status = 0;
3883         bp->link_info->link_up = 0;
3884         if (bp->eth_dev->data->dev_started)
3885                 bnxt_dev_stop(bp->eth_dev);
3886
3887         bnxt_uninit_resources(bp, true);
3888 }
3889
3890 static int
3891 bnxt_check_fw_reset_done(struct bnxt *bp)
3892 {
3893         int timeout = bp->fw_reset_max_msecs;
3894         uint16_t val = 0;
3895         int rc;
3896
3897         do {
3898                 rc = rte_pci_read_config(bp->pdev, &val, sizeof(val), PCI_SUBSYSTEM_ID_OFFSET);
3899                 if (rc < 0) {
3900                         PMD_DRV_LOG(ERR, "Failed to read PCI offset 0x%x", PCI_SUBSYSTEM_ID_OFFSET);
3901                         return rc;
3902                 }
3903                 if (val != 0xffff)
3904                         break;
3905                 rte_delay_ms(1);
3906         } while (timeout--);
3907
3908         if (val == 0xffff) {
3909                 PMD_DRV_LOG(ERR, "Firmware reset aborted, PCI config space invalid\n");
3910                 return -1;
3911         }
3912
3913         return 0;
3914 }
3915
3916 static int bnxt_restore_vlan_filters(struct bnxt *bp)
3917 {
3918         struct rte_eth_dev *dev = bp->eth_dev;
3919         struct rte_vlan_filter_conf *vfc;
3920         int vidx, vbit, rc;
3921         uint16_t vlan_id;
3922
3923         for (vlan_id = 1; vlan_id <= RTE_ETHER_MAX_VLAN_ID; vlan_id++) {
3924                 vfc = &dev->data->vlan_filter_conf;
3925                 vidx = vlan_id / 64;
3926                 vbit = vlan_id % 64;
3927
3928                 /* Each bit corresponds to a VLAN id */
3929                 if (vfc->ids[vidx] & (UINT64_C(1) << vbit)) {
3930                         rc = bnxt_add_vlan_filter(bp, vlan_id);
3931                         if (rc)
3932                                 return rc;
3933                 }
3934         }
3935
3936         return 0;
3937 }
3938
3939 static int bnxt_restore_mac_filters(struct bnxt *bp)
3940 {
3941         struct rte_eth_dev *dev = bp->eth_dev;
3942         struct rte_eth_dev_info dev_info;
3943         struct rte_ether_addr *addr;
3944         uint64_t pool_mask;
3945         uint32_t pool = 0;
3946         uint16_t i;
3947         int rc;
3948
3949         if (BNXT_VF(bp) && !BNXT_VF_IS_TRUSTED(bp))
3950                 return 0;
3951
3952         rc = bnxt_dev_info_get_op(dev, &dev_info);
3953         if (rc)
3954                 return rc;
3955
3956         /* replay MAC address configuration */
3957         for (i = 1; i < dev_info.max_mac_addrs; i++) {
3958                 addr = &dev->data->mac_addrs[i];
3959
3960                 /* skip zero address */
3961                 if (rte_is_zero_ether_addr(addr))
3962                         continue;
3963
3964                 pool = 0;
3965                 pool_mask = dev->data->mac_pool_sel[i];
3966
3967                 do {
3968                         if (pool_mask & 1ULL) {
3969                                 rc = bnxt_mac_addr_add_op(dev, addr, i, pool);
3970                                 if (rc)
3971                                         return rc;
3972                         }
3973                         pool_mask >>= 1;
3974                         pool++;
3975                 } while (pool_mask);
3976         }
3977
3978         return 0;
3979 }
3980
3981 static int bnxt_restore_filters(struct bnxt *bp)
3982 {
3983         struct rte_eth_dev *dev = bp->eth_dev;
3984         int ret = 0;
3985
3986         if (dev->data->all_multicast) {
3987                 ret = bnxt_allmulticast_enable_op(dev);
3988                 if (ret)
3989                         return ret;
3990         }
3991         if (dev->data->promiscuous) {
3992                 ret = bnxt_promiscuous_enable_op(dev);
3993                 if (ret)
3994                         return ret;
3995         }
3996
3997         ret = bnxt_restore_mac_filters(bp);
3998         if (ret)
3999                 return ret;
4000
4001         ret = bnxt_restore_vlan_filters(bp);
4002         /* TODO restore other filters as well */
4003         return ret;
4004 }
4005
4006 static int bnxt_check_fw_ready(struct bnxt *bp)
4007 {
4008         int timeout = bp->fw_reset_max_msecs;
4009         int rc = 0;
4010
4011         do {
4012                 rc = bnxt_hwrm_poll_ver_get(bp);
4013                 if (rc == 0)
4014                         break;
4015                 rte_delay_ms(BNXT_FW_READY_WAIT_INTERVAL);
4016                 timeout -= BNXT_FW_READY_WAIT_INTERVAL;
4017         } while (rc && timeout > 0);
4018
4019         if (rc)
4020                 PMD_DRV_LOG(ERR, "FW is not Ready after reset\n");
4021
4022         return rc;
4023 }
4024
4025 static void bnxt_dev_recover(void *arg)
4026 {
4027         struct bnxt *bp = arg;
4028         int rc = 0;
4029
4030         pthread_mutex_lock(&bp->err_recovery_lock);
4031
4032         if (!bp->fw_reset_min_msecs) {
4033                 rc = bnxt_check_fw_reset_done(bp);
4034                 if (rc)
4035                         goto err;
4036         }
4037
4038         /* Clear Error flag so that device re-init should happen */
4039         bp->flags &= ~BNXT_FLAG_FATAL_ERROR;
4040
4041         rc = bnxt_check_fw_ready(bp);
4042         if (rc)
4043                 goto err;
4044
4045         rc = bnxt_init_resources(bp, true);
4046         if (rc) {
4047                 PMD_DRV_LOG(ERR,
4048                             "Failed to initialize resources after reset\n");
4049                 goto err;
4050         }
4051         /* clear reset flag as the device is initialized now */
4052         bp->flags &= ~BNXT_FLAG_FW_RESET;
4053
4054         rc = bnxt_dev_start_op(bp->eth_dev);
4055         if (rc) {
4056                 PMD_DRV_LOG(ERR, "Failed to start port after reset\n");
4057                 goto err_start;
4058         }
4059
4060         rc = bnxt_restore_filters(bp);
4061         if (rc)
4062                 goto err_start;
4063
4064         PMD_DRV_LOG(INFO, "Recovered from FW reset\n");
4065         pthread_mutex_unlock(&bp->err_recovery_lock);
4066
4067         return;
4068 err_start:
4069         bnxt_dev_stop(bp->eth_dev);
4070 err:
4071         bp->flags |= BNXT_FLAG_FATAL_ERROR;
4072         bnxt_uninit_resources(bp, false);
4073         pthread_mutex_unlock(&bp->err_recovery_lock);
4074         PMD_DRV_LOG(ERR, "Failed to recover from FW reset\n");
4075 }
4076
4077 void bnxt_dev_reset_and_resume(void *arg)
4078 {
4079         struct bnxt *bp = arg;
4080         uint32_t us = US_PER_MS * bp->fw_reset_min_msecs;
4081         uint16_t val = 0;
4082         int rc;
4083
4084         bnxt_dev_cleanup(bp);
4085
4086         bnxt_wait_for_device_shutdown(bp);
4087
4088         /* During some fatal firmware error conditions, the PCI config space
4089          * register 0x2e which normally contains the subsystem ID will become
4090          * 0xffff. This register will revert back to the normal value after
4091          * the chip has completed core reset. If we detect this condition,
4092          * we can poll this config register immediately for the value to revert.
4093          */
4094         if (bp->flags & BNXT_FLAG_FATAL_ERROR) {
4095                 rc = rte_pci_read_config(bp->pdev, &val, sizeof(val), PCI_SUBSYSTEM_ID_OFFSET);
4096                 if (rc < 0) {
4097                         PMD_DRV_LOG(ERR, "Failed to read PCI offset 0x%x", PCI_SUBSYSTEM_ID_OFFSET);
4098                         return;
4099                 }
4100                 if (val == 0xffff) {
4101                         bp->fw_reset_min_msecs = 0;
4102                         us = 1;
4103                 }
4104         }
4105
4106         rc = rte_eal_alarm_set(us, bnxt_dev_recover, (void *)bp);
4107         if (rc)
4108                 PMD_DRV_LOG(ERR, "Error setting recovery alarm");
4109 }
4110
4111 uint32_t bnxt_read_fw_status_reg(struct bnxt *bp, uint32_t index)
4112 {
4113         struct bnxt_error_recovery_info *info = bp->recovery_info;
4114         uint32_t reg = info->status_regs[index];
4115         uint32_t type, offset, val = 0;
4116
4117         type = BNXT_FW_STATUS_REG_TYPE(reg);
4118         offset = BNXT_FW_STATUS_REG_OFF(reg);
4119
4120         switch (type) {
4121         case BNXT_FW_STATUS_REG_TYPE_CFG:
4122                 rte_pci_read_config(bp->pdev, &val, sizeof(val), offset);
4123                 break;
4124         case BNXT_FW_STATUS_REG_TYPE_GRC:
4125                 offset = info->mapped_status_regs[index];
4126                 /* FALLTHROUGH */
4127         case BNXT_FW_STATUS_REG_TYPE_BAR0:
4128                 val = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
4129                                        offset));
4130                 break;
4131         }
4132
4133         return val;
4134 }
4135
4136 static int bnxt_fw_reset_all(struct bnxt *bp)
4137 {
4138         struct bnxt_error_recovery_info *info = bp->recovery_info;
4139         uint32_t i;
4140         int rc = 0;
4141
4142         if (info->flags & BNXT_FLAG_ERROR_RECOVERY_HOST) {
4143                 /* Reset through master function driver */
4144                 for (i = 0; i < info->reg_array_cnt; i++)
4145                         bnxt_write_fw_reset_reg(bp, i);
4146                 /* Wait for time specified by FW after triggering reset */
4147                 rte_delay_ms(info->master_func_wait_period_after_reset);
4148         } else if (info->flags & BNXT_FLAG_ERROR_RECOVERY_CO_CPU) {
4149                 /* Reset with the help of Kong processor */
4150                 rc = bnxt_hwrm_fw_reset(bp);
4151                 if (rc)
4152                         PMD_DRV_LOG(ERR, "Failed to reset FW\n");
4153         }
4154
4155         return rc;
4156 }
4157
4158 static void bnxt_fw_reset_cb(void *arg)
4159 {
4160         struct bnxt *bp = arg;
4161         struct bnxt_error_recovery_info *info = bp->recovery_info;
4162         int rc = 0;
4163
4164         /* Only Master function can do FW reset */
4165         if (bnxt_is_master_func(bp) &&
4166             bnxt_is_recovery_enabled(bp)) {
4167                 rc = bnxt_fw_reset_all(bp);
4168                 if (rc) {
4169                         PMD_DRV_LOG(ERR, "Adapter recovery failed\n");
4170                         return;
4171                 }
4172         }
4173
4174         /* if recovery method is ERROR_RECOVERY_CO_CPU, KONG will send
4175          * EXCEPTION_FATAL_ASYNC event to all the functions
4176          * (including MASTER FUNC). After receiving this Async, all the active
4177          * drivers should treat this case as FW initiated recovery
4178          */
4179         if (info->flags & BNXT_FLAG_ERROR_RECOVERY_HOST) {
4180                 bp->fw_reset_min_msecs = BNXT_MIN_FW_READY_TIMEOUT;
4181                 bp->fw_reset_max_msecs = BNXT_MAX_FW_RESET_TIMEOUT;
4182
4183                 /* To recover from error */
4184                 rte_eal_alarm_set(US_PER_MS, bnxt_dev_reset_and_resume,
4185                                   (void *)bp);
4186         }
4187 }
4188
4189 /* Driver should poll FW heartbeat, reset_counter with the frequency
4190  * advertised by FW in HWRM_ERROR_RECOVERY_QCFG.
4191  * When the driver detects heartbeat stop or change in reset_counter,
4192  * it has to trigger a reset to recover from the error condition.
4193  * A “master PF” is the function who will have the privilege to
4194  * initiate the chimp reset. The master PF will be elected by the
4195  * firmware and will be notified through async message.
4196  */
4197 static void bnxt_check_fw_health(void *arg)
4198 {
4199         struct bnxt *bp = arg;
4200         struct bnxt_error_recovery_info *info = bp->recovery_info;
4201         uint32_t val = 0, wait_msec;
4202
4203         if (!info || !bnxt_is_recovery_enabled(bp) ||
4204             is_bnxt_in_error(bp))
4205                 return;
4206
4207         val = bnxt_read_fw_status_reg(bp, BNXT_FW_HEARTBEAT_CNT_REG);
4208         if (val == info->last_heart_beat)
4209                 goto reset;
4210
4211         info->last_heart_beat = val;
4212
4213         val = bnxt_read_fw_status_reg(bp, BNXT_FW_RECOVERY_CNT_REG);
4214         if (val != info->last_reset_counter)
4215                 goto reset;
4216
4217         info->last_reset_counter = val;
4218
4219         rte_eal_alarm_set(US_PER_MS * info->driver_polling_freq,
4220                           bnxt_check_fw_health, (void *)bp);
4221
4222         return;
4223 reset:
4224         /* Stop DMA to/from device */
4225         bp->flags |= BNXT_FLAG_FATAL_ERROR;
4226         bp->flags |= BNXT_FLAG_FW_RESET;
4227
4228         PMD_DRV_LOG(ERR, "Detected FW dead condition\n");
4229
4230         if (bnxt_is_master_func(bp))
4231                 wait_msec = info->master_func_wait_period;
4232         else
4233                 wait_msec = info->normal_func_wait_period;
4234
4235         rte_eal_alarm_set(US_PER_MS * wait_msec,
4236                           bnxt_fw_reset_cb, (void *)bp);
4237 }
4238
4239 void bnxt_schedule_fw_health_check(struct bnxt *bp)
4240 {
4241         uint32_t polling_freq;
4242
4243         pthread_mutex_lock(&bp->health_check_lock);
4244
4245         if (!bnxt_is_recovery_enabled(bp))
4246                 goto done;
4247
4248         if (bp->flags & BNXT_FLAG_FW_HEALTH_CHECK_SCHEDULED)
4249                 goto done;
4250
4251         polling_freq = bp->recovery_info->driver_polling_freq;
4252
4253         rte_eal_alarm_set(US_PER_MS * polling_freq,
4254                           bnxt_check_fw_health, (void *)bp);
4255         bp->flags |= BNXT_FLAG_FW_HEALTH_CHECK_SCHEDULED;
4256
4257 done:
4258         pthread_mutex_unlock(&bp->health_check_lock);
4259 }
4260
4261 static void bnxt_cancel_fw_health_check(struct bnxt *bp)
4262 {
4263         if (!bnxt_is_recovery_enabled(bp))
4264                 return;
4265
4266         rte_eal_alarm_cancel(bnxt_check_fw_health, (void *)bp);
4267         bp->flags &= ~BNXT_FLAG_FW_HEALTH_CHECK_SCHEDULED;
4268 }
4269
4270 static bool bnxt_vf_pciid(uint16_t device_id)
4271 {
4272         switch (device_id) {
4273         case BROADCOM_DEV_ID_57304_VF:
4274         case BROADCOM_DEV_ID_57406_VF:
4275         case BROADCOM_DEV_ID_5731X_VF:
4276         case BROADCOM_DEV_ID_5741X_VF:
4277         case BROADCOM_DEV_ID_57414_VF:
4278         case BROADCOM_DEV_ID_STRATUS_NIC_VF1:
4279         case BROADCOM_DEV_ID_STRATUS_NIC_VF2:
4280         case BROADCOM_DEV_ID_58802_VF:
4281         case BROADCOM_DEV_ID_57500_VF1:
4282         case BROADCOM_DEV_ID_57500_VF2:
4283         case BROADCOM_DEV_ID_58818_VF:
4284                 /* FALLTHROUGH */
4285                 return true;
4286         default:
4287                 return false;
4288         }
4289 }
4290
4291 /* Phase 5 device */
4292 static bool bnxt_p5_device(uint16_t device_id)
4293 {
4294         switch (device_id) {
4295         case BROADCOM_DEV_ID_57508:
4296         case BROADCOM_DEV_ID_57504:
4297         case BROADCOM_DEV_ID_57502:
4298         case BROADCOM_DEV_ID_57508_MF1:
4299         case BROADCOM_DEV_ID_57504_MF1:
4300         case BROADCOM_DEV_ID_57502_MF1:
4301         case BROADCOM_DEV_ID_57508_MF2:
4302         case BROADCOM_DEV_ID_57504_MF2:
4303         case BROADCOM_DEV_ID_57502_MF2:
4304         case BROADCOM_DEV_ID_57500_VF1:
4305         case BROADCOM_DEV_ID_57500_VF2:
4306         case BROADCOM_DEV_ID_58812:
4307         case BROADCOM_DEV_ID_58814:
4308         case BROADCOM_DEV_ID_58818:
4309         case BROADCOM_DEV_ID_58818_VF:
4310                 /* FALLTHROUGH */
4311                 return true;
4312         default:
4313                 return false;
4314         }
4315 }
4316
4317 bool bnxt_stratus_device(struct bnxt *bp)
4318 {
4319         uint16_t device_id = bp->pdev->id.device_id;
4320
4321         switch (device_id) {
4322         case BROADCOM_DEV_ID_STRATUS_NIC:
4323         case BROADCOM_DEV_ID_STRATUS_NIC_VF1:
4324         case BROADCOM_DEV_ID_STRATUS_NIC_VF2:
4325                 /* FALLTHROUGH */
4326                 return true;
4327         default:
4328                 return false;
4329         }
4330 }
4331
4332 static int bnxt_map_pci_bars(struct rte_eth_dev *eth_dev)
4333 {
4334         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
4335         struct bnxt *bp = eth_dev->data->dev_private;
4336
4337         /* enable device (incl. PCI PM wakeup), and bus-mastering */
4338         bp->bar0 = (void *)pci_dev->mem_resource[0].addr;
4339         bp->doorbell_base = (void *)pci_dev->mem_resource[2].addr;
4340         if (!bp->bar0 || !bp->doorbell_base) {
4341                 PMD_DRV_LOG(ERR, "Unable to access Hardware\n");
4342                 return -ENODEV;
4343         }
4344
4345         bp->eth_dev = eth_dev;
4346         bp->pdev = pci_dev;
4347
4348         return 0;
4349 }
4350
4351 static int bnxt_alloc_ctx_mem_blk(struct bnxt *bp,
4352                                   struct bnxt_ctx_pg_info *ctx_pg,
4353                                   uint32_t mem_size,
4354                                   const char *suffix,
4355                                   uint16_t idx)
4356 {
4357         struct bnxt_ring_mem_info *rmem = &ctx_pg->ring_mem;
4358         const struct rte_memzone *mz = NULL;
4359         char mz_name[RTE_MEMZONE_NAMESIZE];
4360         rte_iova_t mz_phys_addr;
4361         uint64_t valid_bits = 0;
4362         uint32_t sz;
4363         int i;
4364
4365         if (!mem_size)
4366                 return 0;
4367
4368         rmem->nr_pages = RTE_ALIGN_MUL_CEIL(mem_size, BNXT_PAGE_SIZE) /
4369                          BNXT_PAGE_SIZE;
4370         rmem->page_size = BNXT_PAGE_SIZE;
4371         rmem->pg_arr = ctx_pg->ctx_pg_arr;
4372         rmem->dma_arr = ctx_pg->ctx_dma_arr;
4373         rmem->flags = BNXT_RMEM_VALID_PTE_FLAG;
4374
4375         valid_bits = PTU_PTE_VALID;
4376
4377         if (rmem->nr_pages > 1) {
4378                 snprintf(mz_name, RTE_MEMZONE_NAMESIZE,
4379                          "bnxt_ctx_pg_tbl%s_%x_%d",
4380                          suffix, idx, bp->eth_dev->data->port_id);
4381                 mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0;
4382                 mz = rte_memzone_lookup(mz_name);
4383                 if (!mz) {
4384                         mz = rte_memzone_reserve_aligned(mz_name,
4385                                                 rmem->nr_pages * 8,
4386                                                 SOCKET_ID_ANY,
4387                                                 RTE_MEMZONE_2MB |
4388                                                 RTE_MEMZONE_SIZE_HINT_ONLY |
4389                                                 RTE_MEMZONE_IOVA_CONTIG,
4390                                                 BNXT_PAGE_SIZE);
4391                         if (mz == NULL)
4392                                 return -ENOMEM;
4393                 }
4394
4395                 memset(mz->addr, 0, mz->len);
4396                 mz_phys_addr = mz->iova;
4397
4398                 rmem->pg_tbl = mz->addr;
4399                 rmem->pg_tbl_map = mz_phys_addr;
4400                 rmem->pg_tbl_mz = mz;
4401         }
4402
4403         snprintf(mz_name, RTE_MEMZONE_NAMESIZE, "bnxt_ctx_%s_%x_%d",
4404                  suffix, idx, bp->eth_dev->data->port_id);
4405         mz = rte_memzone_lookup(mz_name);
4406         if (!mz) {
4407                 mz = rte_memzone_reserve_aligned(mz_name,
4408                                                  mem_size,
4409                                                  SOCKET_ID_ANY,
4410                                                  RTE_MEMZONE_1GB |
4411                                                  RTE_MEMZONE_SIZE_HINT_ONLY |
4412                                                  RTE_MEMZONE_IOVA_CONTIG,
4413                                                  BNXT_PAGE_SIZE);
4414                 if (mz == NULL)
4415                         return -ENOMEM;
4416         }
4417
4418         memset(mz->addr, 0, mz->len);
4419         mz_phys_addr = mz->iova;
4420
4421         for (sz = 0, i = 0; sz < mem_size; sz += BNXT_PAGE_SIZE, i++) {
4422                 rmem->pg_arr[i] = ((char *)mz->addr) + sz;
4423                 rmem->dma_arr[i] = mz_phys_addr + sz;
4424
4425                 if (rmem->nr_pages > 1) {
4426                         if (i == rmem->nr_pages - 2 &&
4427                             (rmem->flags & BNXT_RMEM_RING_PTE_FLAG))
4428                                 valid_bits |= PTU_PTE_NEXT_TO_LAST;
4429                         else if (i == rmem->nr_pages - 1 &&
4430                                  (rmem->flags & BNXT_RMEM_RING_PTE_FLAG))
4431                                 valid_bits |= PTU_PTE_LAST;
4432
4433                         rmem->pg_tbl[i] = rte_cpu_to_le_64(rmem->dma_arr[i] |
4434                                                            valid_bits);
4435                 }
4436         }
4437
4438         rmem->mz = mz;
4439         if (rmem->vmem_size)
4440                 rmem->vmem = (void **)mz->addr;
4441         rmem->dma_arr[0] = mz_phys_addr;
4442         return 0;
4443 }
4444
4445 static void bnxt_free_ctx_mem(struct bnxt *bp)
4446 {
4447         int i;
4448
4449         if (!bp->ctx || !(bp->ctx->flags & BNXT_CTX_FLAG_INITED))
4450                 return;
4451
4452         bp->ctx->flags &= ~BNXT_CTX_FLAG_INITED;
4453         rte_memzone_free(bp->ctx->qp_mem.ring_mem.mz);
4454         rte_memzone_free(bp->ctx->srq_mem.ring_mem.mz);
4455         rte_memzone_free(bp->ctx->cq_mem.ring_mem.mz);
4456         rte_memzone_free(bp->ctx->vnic_mem.ring_mem.mz);
4457         rte_memzone_free(bp->ctx->stat_mem.ring_mem.mz);
4458         rte_memzone_free(bp->ctx->qp_mem.ring_mem.pg_tbl_mz);
4459         rte_memzone_free(bp->ctx->srq_mem.ring_mem.pg_tbl_mz);
4460         rte_memzone_free(bp->ctx->cq_mem.ring_mem.pg_tbl_mz);
4461         rte_memzone_free(bp->ctx->vnic_mem.ring_mem.pg_tbl_mz);
4462         rte_memzone_free(bp->ctx->stat_mem.ring_mem.pg_tbl_mz);
4463
4464         for (i = 0; i < bp->ctx->tqm_fp_rings_count + 1; i++) {
4465                 if (bp->ctx->tqm_mem[i])
4466                         rte_memzone_free(bp->ctx->tqm_mem[i]->ring_mem.mz);
4467         }
4468
4469         rte_free(bp->ctx);
4470         bp->ctx = NULL;
4471 }
4472
4473 #define bnxt_roundup(x, y)   ((((x) + ((y) - 1)) / (y)) * (y))
4474
4475 #define min_t(type, x, y) ({                    \
4476         type __min1 = (x);                      \
4477         type __min2 = (y);                      \
4478         __min1 < __min2 ? __min1 : __min2; })
4479
4480 #define max_t(type, x, y) ({                    \
4481         type __max1 = (x);                      \
4482         type __max2 = (y);                      \
4483         __max1 > __max2 ? __max1 : __max2; })
4484
4485 #define clamp_t(type, _x, min, max)     min_t(type, max_t(type, _x, min), max)
4486
4487 int bnxt_alloc_ctx_mem(struct bnxt *bp)
4488 {
4489         struct bnxt_ctx_pg_info *ctx_pg;
4490         struct bnxt_ctx_mem_info *ctx;
4491         uint32_t mem_size, ena, entries;
4492         uint32_t entries_sp, min;
4493         int i, rc;
4494
4495         rc = bnxt_hwrm_func_backing_store_qcaps(bp);
4496         if (rc) {
4497                 PMD_DRV_LOG(ERR, "Query context mem capability failed\n");
4498                 return rc;
4499         }
4500         ctx = bp->ctx;
4501         if (!ctx || (ctx->flags & BNXT_CTX_FLAG_INITED))
4502                 return 0;
4503
4504         ctx_pg = &ctx->qp_mem;
4505         ctx_pg->entries = ctx->qp_min_qp1_entries + ctx->qp_max_l2_entries;
4506         if (ctx->qp_entry_size) {
4507                 mem_size = ctx->qp_entry_size * ctx_pg->entries;
4508                 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "qp_mem", 0);
4509                 if (rc)
4510                         return rc;
4511         }
4512
4513         ctx_pg = &ctx->srq_mem;
4514         ctx_pg->entries = ctx->srq_max_l2_entries;
4515         if (ctx->srq_entry_size) {
4516                 mem_size = ctx->srq_entry_size * ctx_pg->entries;
4517                 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "srq_mem", 0);
4518                 if (rc)
4519                         return rc;
4520         }
4521
4522         ctx_pg = &ctx->cq_mem;
4523         ctx_pg->entries = ctx->cq_max_l2_entries;
4524         if (ctx->cq_entry_size) {
4525                 mem_size = ctx->cq_entry_size * ctx_pg->entries;
4526                 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "cq_mem", 0);
4527                 if (rc)
4528                         return rc;
4529         }
4530
4531         ctx_pg = &ctx->vnic_mem;
4532         ctx_pg->entries = ctx->vnic_max_vnic_entries +
4533                 ctx->vnic_max_ring_table_entries;
4534         if (ctx->vnic_entry_size) {
4535                 mem_size = ctx->vnic_entry_size * ctx_pg->entries;
4536                 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "vnic_mem", 0);
4537                 if (rc)
4538                         return rc;
4539         }
4540
4541         ctx_pg = &ctx->stat_mem;
4542         ctx_pg->entries = ctx->stat_max_entries;
4543         if (ctx->stat_entry_size) {
4544                 mem_size = ctx->stat_entry_size * ctx_pg->entries;
4545                 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "stat_mem", 0);
4546                 if (rc)
4547                         return rc;
4548         }
4549
4550         min = ctx->tqm_min_entries_per_ring;
4551
4552         entries_sp = ctx->qp_max_l2_entries +
4553                      ctx->vnic_max_vnic_entries +
4554                      2 * ctx->qp_min_qp1_entries + min;
4555         entries_sp = bnxt_roundup(entries_sp, ctx->tqm_entries_multiple);
4556
4557         entries = ctx->qp_max_l2_entries + ctx->qp_min_qp1_entries;
4558         entries = bnxt_roundup(entries, ctx->tqm_entries_multiple);
4559         entries = clamp_t(uint32_t, entries, min,
4560                           ctx->tqm_max_entries_per_ring);
4561         for (i = 0, ena = 0; i < ctx->tqm_fp_rings_count + 1; i++) {
4562                 /* i=0 is for TQM_SP. i=1 to i=8 applies to RING0 to RING7.
4563                  * i > 8 is other ext rings.
4564                  */
4565                 ctx_pg = ctx->tqm_mem[i];
4566                 ctx_pg->entries = i ? entries : entries_sp;
4567                 if (ctx->tqm_entry_size) {
4568                         mem_size = ctx->tqm_entry_size * ctx_pg->entries;
4569                         rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size,
4570                                                     "tqm_mem", i);
4571                         if (rc)
4572                                 return rc;
4573                 }
4574                 if (i < BNXT_MAX_TQM_LEGACY_RINGS)
4575                         ena |= HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_SP << i;
4576                 else
4577                         ena |= HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_RING8;
4578         }
4579
4580         ena |= FUNC_BACKING_STORE_CFG_INPUT_DFLT_ENABLES;
4581         rc = bnxt_hwrm_func_backing_store_cfg(bp, ena);
4582         if (rc)
4583                 PMD_DRV_LOG(ERR,
4584                             "Failed to configure context mem: rc = %d\n", rc);
4585         else
4586                 ctx->flags |= BNXT_CTX_FLAG_INITED;
4587
4588         return rc;
4589 }
4590
4591 static int bnxt_alloc_stats_mem(struct bnxt *bp)
4592 {
4593         struct rte_pci_device *pci_dev = bp->pdev;
4594         char mz_name[RTE_MEMZONE_NAMESIZE];
4595         const struct rte_memzone *mz = NULL;
4596         uint32_t total_alloc_len;
4597         rte_iova_t mz_phys_addr;
4598
4599         if (pci_dev->id.device_id == BROADCOM_DEV_ID_NS2)
4600                 return 0;
4601
4602         snprintf(mz_name, RTE_MEMZONE_NAMESIZE,
4603                  "bnxt_" PCI_PRI_FMT "-%s", pci_dev->addr.domain,
4604                  pci_dev->addr.bus, pci_dev->addr.devid,
4605                  pci_dev->addr.function, "rx_port_stats");
4606         mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0;
4607         mz = rte_memzone_lookup(mz_name);
4608         total_alloc_len =
4609                 RTE_CACHE_LINE_ROUNDUP(sizeof(struct rx_port_stats) +
4610                                        sizeof(struct rx_port_stats_ext) + 512);
4611         if (!mz) {
4612                 mz = rte_memzone_reserve(mz_name, total_alloc_len,
4613                                          SOCKET_ID_ANY,
4614                                          RTE_MEMZONE_2MB |
4615                                          RTE_MEMZONE_SIZE_HINT_ONLY |
4616                                          RTE_MEMZONE_IOVA_CONTIG);
4617                 if (mz == NULL)
4618                         return -ENOMEM;
4619         }
4620         memset(mz->addr, 0, mz->len);
4621         mz_phys_addr = mz->iova;
4622
4623         bp->rx_mem_zone = (const void *)mz;
4624         bp->hw_rx_port_stats = mz->addr;
4625         bp->hw_rx_port_stats_map = mz_phys_addr;
4626
4627         snprintf(mz_name, RTE_MEMZONE_NAMESIZE,
4628                  "bnxt_" PCI_PRI_FMT "-%s", pci_dev->addr.domain,
4629                  pci_dev->addr.bus, pci_dev->addr.devid,
4630                  pci_dev->addr.function, "tx_port_stats");
4631         mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0;
4632         mz = rte_memzone_lookup(mz_name);
4633         total_alloc_len =
4634                 RTE_CACHE_LINE_ROUNDUP(sizeof(struct tx_port_stats) +
4635                                        sizeof(struct tx_port_stats_ext) + 512);
4636         if (!mz) {
4637                 mz = rte_memzone_reserve(mz_name,
4638                                          total_alloc_len,
4639                                          SOCKET_ID_ANY,
4640                                          RTE_MEMZONE_2MB |
4641                                          RTE_MEMZONE_SIZE_HINT_ONLY |
4642                                          RTE_MEMZONE_IOVA_CONTIG);
4643                 if (mz == NULL)
4644                         return -ENOMEM;
4645         }
4646         memset(mz->addr, 0, mz->len);
4647         mz_phys_addr = mz->iova;
4648
4649         bp->tx_mem_zone = (const void *)mz;
4650         bp->hw_tx_port_stats = mz->addr;
4651         bp->hw_tx_port_stats_map = mz_phys_addr;
4652         bp->flags |= BNXT_FLAG_PORT_STATS;
4653
4654         /* Display extended statistics if FW supports it */
4655         if (bp->hwrm_spec_code < HWRM_SPEC_CODE_1_8_4 ||
4656             bp->hwrm_spec_code == HWRM_SPEC_CODE_1_9_0 ||
4657             !(bp->flags & BNXT_FLAG_EXT_STATS_SUPPORTED))
4658                 return 0;
4659
4660         bp->hw_rx_port_stats_ext = (void *)
4661                 ((uint8_t *)bp->hw_rx_port_stats +
4662                  sizeof(struct rx_port_stats));
4663         bp->hw_rx_port_stats_ext_map = bp->hw_rx_port_stats_map +
4664                 sizeof(struct rx_port_stats);
4665         bp->flags |= BNXT_FLAG_EXT_RX_PORT_STATS;
4666
4667         if (bp->hwrm_spec_code < HWRM_SPEC_CODE_1_9_2 ||
4668             bp->flags & BNXT_FLAG_EXT_STATS_SUPPORTED) {
4669                 bp->hw_tx_port_stats_ext = (void *)
4670                         ((uint8_t *)bp->hw_tx_port_stats +
4671                          sizeof(struct tx_port_stats));
4672                 bp->hw_tx_port_stats_ext_map =
4673                         bp->hw_tx_port_stats_map +
4674                         sizeof(struct tx_port_stats);
4675                 bp->flags |= BNXT_FLAG_EXT_TX_PORT_STATS;
4676         }
4677
4678         return 0;
4679 }
4680
4681 static int bnxt_setup_mac_addr(struct rte_eth_dev *eth_dev)
4682 {
4683         struct bnxt *bp = eth_dev->data->dev_private;
4684         int rc = 0;
4685
4686         eth_dev->data->mac_addrs = rte_zmalloc("bnxt_mac_addr_tbl",
4687                                                RTE_ETHER_ADDR_LEN *
4688                                                bp->max_l2_ctx,
4689                                                0);
4690         if (eth_dev->data->mac_addrs == NULL) {
4691                 PMD_DRV_LOG(ERR, "Failed to alloc MAC addr tbl\n");
4692                 return -ENOMEM;
4693         }
4694
4695         if (!BNXT_HAS_DFLT_MAC_SET(bp)) {
4696                 if (BNXT_PF(bp))
4697                         return -EINVAL;
4698
4699                 /* Generate a random MAC address, if none was assigned by PF */
4700                 PMD_DRV_LOG(INFO, "VF MAC address not assigned by Host PF\n");
4701                 bnxt_eth_hw_addr_random(bp->mac_addr);
4702                 PMD_DRV_LOG(INFO,
4703                             "Assign random MAC:%02X:%02X:%02X:%02X:%02X:%02X\n",
4704                             bp->mac_addr[0], bp->mac_addr[1], bp->mac_addr[2],
4705                             bp->mac_addr[3], bp->mac_addr[4], bp->mac_addr[5]);
4706
4707                 rc = bnxt_hwrm_set_mac(bp);
4708                 if (rc)
4709                         return rc;
4710         }
4711
4712         /* Copy the permanent MAC from the FUNC_QCAPS response */
4713         memcpy(&eth_dev->data->mac_addrs[0], bp->mac_addr, RTE_ETHER_ADDR_LEN);
4714
4715         return rc;
4716 }
4717
4718 static int bnxt_restore_dflt_mac(struct bnxt *bp)
4719 {
4720         int rc = 0;
4721
4722         /* MAC is already configured in FW */
4723         if (BNXT_HAS_DFLT_MAC_SET(bp))
4724                 return 0;
4725
4726         /* Restore the old MAC configured */
4727         rc = bnxt_hwrm_set_mac(bp);
4728         if (rc)
4729                 PMD_DRV_LOG(ERR, "Failed to restore MAC address\n");
4730
4731         return rc;
4732 }
4733
4734 static void bnxt_config_vf_req_fwd(struct bnxt *bp)
4735 {
4736         if (!BNXT_PF(bp))
4737                 return;
4738
4739         memset(bp->pf->vf_req_fwd, 0, sizeof(bp->pf->vf_req_fwd));
4740
4741         if (!(bp->fw_cap & BNXT_FW_CAP_LINK_ADMIN))
4742                 BNXT_HWRM_CMD_TO_FORWARD(HWRM_PORT_PHY_QCFG);
4743         BNXT_HWRM_CMD_TO_FORWARD(HWRM_FUNC_CFG);
4744         BNXT_HWRM_CMD_TO_FORWARD(HWRM_FUNC_VF_CFG);
4745         BNXT_HWRM_CMD_TO_FORWARD(HWRM_CFA_L2_FILTER_ALLOC);
4746         BNXT_HWRM_CMD_TO_FORWARD(HWRM_OEM_CMD);
4747 }
4748
4749 uint16_t
4750 bnxt_get_svif(uint16_t port_id, bool func_svif,
4751               enum bnxt_ulp_intf_type type)
4752 {
4753         struct rte_eth_dev *eth_dev;
4754         struct bnxt *bp;
4755
4756         eth_dev = &rte_eth_devices[port_id];
4757         if (BNXT_ETH_DEV_IS_REPRESENTOR(eth_dev)) {
4758                 struct bnxt_representor *vfr = eth_dev->data->dev_private;
4759                 if (!vfr)
4760                         return 0;
4761
4762                 if (type == BNXT_ULP_INTF_TYPE_VF_REP)
4763                         return vfr->svif;
4764
4765                 eth_dev = vfr->parent_dev;
4766         }
4767
4768         bp = eth_dev->data->dev_private;
4769
4770         return func_svif ? bp->func_svif : bp->port_svif;
4771 }
4772
4773 uint16_t
4774 bnxt_get_vnic_id(uint16_t port, enum bnxt_ulp_intf_type type)
4775 {
4776         struct rte_eth_dev *eth_dev;
4777         struct bnxt_vnic_info *vnic;
4778         struct bnxt *bp;
4779
4780         eth_dev = &rte_eth_devices[port];
4781         if (BNXT_ETH_DEV_IS_REPRESENTOR(eth_dev)) {
4782                 struct bnxt_representor *vfr = eth_dev->data->dev_private;
4783                 if (!vfr)
4784                         return 0;
4785
4786                 if (type == BNXT_ULP_INTF_TYPE_VF_REP)
4787                         return vfr->dflt_vnic_id;
4788
4789                 eth_dev = vfr->parent_dev;
4790         }
4791
4792         bp = eth_dev->data->dev_private;
4793
4794         vnic = BNXT_GET_DEFAULT_VNIC(bp);
4795
4796         return vnic->fw_vnic_id;
4797 }
4798
4799 uint16_t
4800 bnxt_get_fw_func_id(uint16_t port, enum bnxt_ulp_intf_type type)
4801 {
4802         struct rte_eth_dev *eth_dev;
4803         struct bnxt *bp;
4804
4805         eth_dev = &rte_eth_devices[port];
4806         if (BNXT_ETH_DEV_IS_REPRESENTOR(eth_dev)) {
4807                 struct bnxt_representor *vfr = eth_dev->data->dev_private;
4808                 if (!vfr)
4809                         return 0;
4810
4811                 if (type == BNXT_ULP_INTF_TYPE_VF_REP)
4812                         return vfr->fw_fid;
4813
4814                 eth_dev = vfr->parent_dev;
4815         }
4816
4817         bp = eth_dev->data->dev_private;
4818
4819         return bp->fw_fid;
4820 }
4821
4822 enum bnxt_ulp_intf_type
4823 bnxt_get_interface_type(uint16_t port)
4824 {
4825         struct rte_eth_dev *eth_dev;
4826         struct bnxt *bp;
4827
4828         eth_dev = &rte_eth_devices[port];
4829         if (BNXT_ETH_DEV_IS_REPRESENTOR(eth_dev))
4830                 return BNXT_ULP_INTF_TYPE_VF_REP;
4831
4832         bp = eth_dev->data->dev_private;
4833         if (BNXT_PF(bp))
4834                 return BNXT_ULP_INTF_TYPE_PF;
4835         else if (BNXT_VF_IS_TRUSTED(bp))
4836                 return BNXT_ULP_INTF_TYPE_TRUSTED_VF;
4837         else if (BNXT_VF(bp))
4838                 return BNXT_ULP_INTF_TYPE_VF;
4839
4840         return BNXT_ULP_INTF_TYPE_INVALID;
4841 }
4842
4843 uint16_t
4844 bnxt_get_phy_port_id(uint16_t port_id)
4845 {
4846         struct bnxt_representor *vfr;
4847         struct rte_eth_dev *eth_dev;
4848         struct bnxt *bp;
4849
4850         eth_dev = &rte_eth_devices[port_id];
4851         if (BNXT_ETH_DEV_IS_REPRESENTOR(eth_dev)) {
4852                 vfr = eth_dev->data->dev_private;
4853                 if (!vfr)
4854                         return 0;
4855
4856                 eth_dev = vfr->parent_dev;
4857         }
4858
4859         bp = eth_dev->data->dev_private;
4860
4861         return BNXT_PF(bp) ? bp->pf->port_id : bp->parent->port_id;
4862 }
4863
4864 uint16_t
4865 bnxt_get_parif(uint16_t port_id, enum bnxt_ulp_intf_type type)
4866 {
4867         struct rte_eth_dev *eth_dev;
4868         struct bnxt *bp;
4869
4870         eth_dev = &rte_eth_devices[port_id];
4871         if (BNXT_ETH_DEV_IS_REPRESENTOR(eth_dev)) {
4872                 struct bnxt_representor *vfr = eth_dev->data->dev_private;
4873                 if (!vfr)
4874                         return 0;
4875
4876                 if (type == BNXT_ULP_INTF_TYPE_VF_REP)
4877                         return vfr->fw_fid - 1;
4878
4879                 eth_dev = vfr->parent_dev;
4880         }
4881
4882         bp = eth_dev->data->dev_private;
4883
4884         return BNXT_PF(bp) ? bp->fw_fid - 1 : bp->parent->fid - 1;
4885 }
4886
4887 uint16_t
4888 bnxt_get_vport(uint16_t port_id)
4889 {
4890         return (1 << bnxt_get_phy_port_id(port_id));
4891 }
4892
4893 static void bnxt_alloc_error_recovery_info(struct bnxt *bp)
4894 {
4895         struct bnxt_error_recovery_info *info = bp->recovery_info;
4896
4897         if (info) {
4898                 if (!(bp->fw_cap & BNXT_FW_CAP_HCOMM_FW_STATUS))
4899                         memset(info, 0, sizeof(*info));
4900                 return;
4901         }
4902
4903         if (!(bp->fw_cap & BNXT_FW_CAP_ERROR_RECOVERY))
4904                 return;
4905
4906         info = rte_zmalloc("bnxt_hwrm_error_recovery_qcfg",
4907                            sizeof(*info), 0);
4908         if (!info)
4909                 bp->fw_cap &= ~BNXT_FW_CAP_ERROR_RECOVERY;
4910
4911         bp->recovery_info = info;
4912 }
4913
4914 static void bnxt_check_fw_status(struct bnxt *bp)
4915 {
4916         uint32_t fw_status;
4917
4918         if (!(bp->recovery_info &&
4919               (bp->fw_cap & BNXT_FW_CAP_HCOMM_FW_STATUS)))
4920                 return;
4921
4922         fw_status = bnxt_read_fw_status_reg(bp, BNXT_FW_STATUS_REG);
4923         if (fw_status != BNXT_FW_STATUS_HEALTHY)
4924                 PMD_DRV_LOG(ERR, "Firmware not responding, status: %#x\n",
4925                             fw_status);
4926 }
4927
4928 static int bnxt_map_hcomm_fw_status_reg(struct bnxt *bp)
4929 {
4930         struct bnxt_error_recovery_info *info = bp->recovery_info;
4931         uint32_t status_loc;
4932         uint32_t sig_ver;
4933
4934         rte_write32(HCOMM_STATUS_STRUCT_LOC, (uint8_t *)bp->bar0 +
4935                     BNXT_GRCPF_REG_WINDOW_BASE_OUT + 4);
4936         sig_ver = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
4937                                    BNXT_GRCP_WINDOW_2_BASE +
4938                                    offsetof(struct hcomm_status,
4939                                             sig_ver)));
4940         /* If the signature is absent, then FW does not support this feature */
4941         if ((sig_ver & HCOMM_STATUS_SIGNATURE_MASK) !=
4942             HCOMM_STATUS_SIGNATURE_VAL)
4943                 return 0;
4944
4945         if (!info) {
4946                 info = rte_zmalloc("bnxt_hwrm_error_recovery_qcfg",
4947                                    sizeof(*info), 0);
4948                 if (!info)
4949                         return -ENOMEM;
4950                 bp->recovery_info = info;
4951         } else {
4952                 memset(info, 0, sizeof(*info));
4953         }
4954
4955         status_loc = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
4956                                       BNXT_GRCP_WINDOW_2_BASE +
4957                                       offsetof(struct hcomm_status,
4958                                                fw_status_loc)));
4959
4960         /* Only pre-map the FW health status GRC register */
4961         if (BNXT_FW_STATUS_REG_TYPE(status_loc) != BNXT_FW_STATUS_REG_TYPE_GRC)
4962                 return 0;
4963
4964         info->status_regs[BNXT_FW_STATUS_REG] = status_loc;
4965         info->mapped_status_regs[BNXT_FW_STATUS_REG] =
4966                 BNXT_GRCP_WINDOW_2_BASE + (status_loc & BNXT_GRCP_OFFSET_MASK);
4967
4968         rte_write32((status_loc & BNXT_GRCP_BASE_MASK), (uint8_t *)bp->bar0 +
4969                     BNXT_GRCPF_REG_WINDOW_BASE_OUT + 4);
4970
4971         bp->fw_cap |= BNXT_FW_CAP_HCOMM_FW_STATUS;
4972
4973         return 0;
4974 }
4975
4976 /* This function gets the FW version along with the
4977  * capabilities(MAX and current) of the function, vnic,
4978  * error recovery, phy and other chip related info
4979  */
4980 static int bnxt_get_config(struct bnxt *bp)
4981 {
4982         uint16_t mtu;
4983         int rc = 0;
4984
4985         bp->fw_cap = 0;
4986
4987         rc = bnxt_map_hcomm_fw_status_reg(bp);
4988         if (rc)
4989                 return rc;
4990
4991         rc = bnxt_hwrm_ver_get(bp, DFLT_HWRM_CMD_TIMEOUT);
4992         if (rc) {
4993                 bnxt_check_fw_status(bp);
4994                 return rc;
4995         }
4996
4997         rc = bnxt_hwrm_func_reset(bp);
4998         if (rc)
4999                 return -EIO;
5000
5001         rc = bnxt_hwrm_vnic_qcaps(bp);
5002         if (rc)
5003                 return rc;
5004
5005         rc = bnxt_hwrm_queue_qportcfg(bp);
5006         if (rc)
5007                 return rc;
5008
5009         /* Get the MAX capabilities for this function.
5010          * This function also allocates context memory for TQM rings and
5011          * informs the firmware about this allocated backing store memory.
5012          */
5013         rc = bnxt_hwrm_func_qcaps(bp);
5014         if (rc)
5015                 return rc;
5016
5017         rc = bnxt_hwrm_func_qcfg(bp, &mtu);
5018         if (rc)
5019                 return rc;
5020
5021         rc = bnxt_hwrm_cfa_adv_flow_mgmt_qcaps(bp);
5022         if (rc)
5023                 return rc;
5024
5025         bnxt_hwrm_port_mac_qcfg(bp);
5026
5027         bnxt_hwrm_parent_pf_qcfg(bp);
5028
5029         bnxt_hwrm_port_phy_qcaps(bp);
5030
5031         bnxt_alloc_error_recovery_info(bp);
5032         /* Get the adapter error recovery support info */
5033         rc = bnxt_hwrm_error_recovery_qcfg(bp);
5034         if (rc)
5035                 bp->fw_cap &= ~BNXT_FW_CAP_ERROR_RECOVERY;
5036
5037         bnxt_hwrm_port_led_qcaps(bp);
5038
5039         return 0;
5040 }
5041
5042 static int
5043 bnxt_init_locks(struct bnxt *bp)
5044 {
5045         int err;
5046
5047         err = pthread_mutex_init(&bp->flow_lock, NULL);
5048         if (err) {
5049                 PMD_DRV_LOG(ERR, "Unable to initialize flow_lock\n");
5050                 return err;
5051         }
5052
5053         err = pthread_mutex_init(&bp->def_cp_lock, NULL);
5054         if (err) {
5055                 PMD_DRV_LOG(ERR, "Unable to initialize def_cp_lock\n");
5056                 return err;
5057         }
5058
5059         err = pthread_mutex_init(&bp->health_check_lock, NULL);
5060         if (err) {
5061                 PMD_DRV_LOG(ERR, "Unable to initialize health_check_lock\n");
5062                 return err;
5063         }
5064
5065         err = pthread_mutex_init(&bp->err_recovery_lock, NULL);
5066         if (err)
5067                 PMD_DRV_LOG(ERR, "Unable to initialize err_recovery_lock\n");
5068
5069         return err;
5070 }
5071
5072 static int bnxt_init_resources(struct bnxt *bp, bool reconfig_dev)
5073 {
5074         int rc = 0;
5075
5076         rc = bnxt_get_config(bp);
5077         if (rc)
5078                 return rc;
5079
5080         if (!reconfig_dev) {
5081                 rc = bnxt_setup_mac_addr(bp->eth_dev);
5082                 if (rc)
5083                         return rc;
5084         } else {
5085                 rc = bnxt_restore_dflt_mac(bp);
5086                 if (rc)
5087                         return rc;
5088         }
5089
5090         bnxt_config_vf_req_fwd(bp);
5091
5092         rc = bnxt_hwrm_func_driver_register(bp);
5093         if (rc) {
5094                 PMD_DRV_LOG(ERR, "Failed to register driver");
5095                 return -EBUSY;
5096         }
5097
5098         if (BNXT_PF(bp)) {
5099                 if (bp->pdev->max_vfs) {
5100                         rc = bnxt_hwrm_allocate_vfs(bp, bp->pdev->max_vfs);
5101                         if (rc) {
5102                                 PMD_DRV_LOG(ERR, "Failed to allocate VFs\n");
5103                                 return rc;
5104                         }
5105                 } else {
5106                         rc = bnxt_hwrm_allocate_pf_only(bp);
5107                         if (rc) {
5108                                 PMD_DRV_LOG(ERR,
5109                                             "Failed to allocate PF resources");
5110                                 return rc;
5111                         }
5112                 }
5113         }
5114
5115         rc = bnxt_alloc_mem(bp, reconfig_dev);
5116         if (rc)
5117                 return rc;
5118
5119         rc = bnxt_setup_int(bp);
5120         if (rc)
5121                 return rc;
5122
5123         rc = bnxt_request_int(bp);
5124         if (rc)
5125                 return rc;
5126
5127         rc = bnxt_init_ctx_mem(bp);
5128         if (rc) {
5129                 PMD_DRV_LOG(ERR, "Failed to init adv_flow_counters\n");
5130                 return rc;
5131         }
5132
5133         return 0;
5134 }
5135
5136 static int
5137 bnxt_parse_devarg_truflow(__rte_unused const char *key,
5138                           const char *value, void *opaque_arg)
5139 {
5140         struct bnxt *bp = opaque_arg;
5141         unsigned long truflow;
5142         char *end = NULL;
5143
5144         if (!value || !opaque_arg) {
5145                 PMD_DRV_LOG(ERR,
5146                             "Invalid parameter passed to truflow devargs.\n");
5147                 return -EINVAL;
5148         }
5149
5150         truflow = strtoul(value, &end, 10);
5151         if (end == NULL || *end != '\0' ||
5152             (truflow == ULONG_MAX && errno == ERANGE)) {
5153                 PMD_DRV_LOG(ERR,
5154                             "Invalid parameter passed to truflow devargs.\n");
5155                 return -EINVAL;
5156         }
5157
5158         if (BNXT_DEVARG_TRUFLOW_INVALID(truflow)) {
5159                 PMD_DRV_LOG(ERR,
5160                             "Invalid value passed to truflow devargs.\n");
5161                 return -EINVAL;
5162         }
5163
5164         if (truflow) {
5165                 bp->flags |= BNXT_FLAG_TRUFLOW_EN;
5166                 PMD_DRV_LOG(INFO, "Host-based truflow feature enabled.\n");
5167         } else {
5168                 bp->flags &= ~BNXT_FLAG_TRUFLOW_EN;
5169                 PMD_DRV_LOG(INFO, "Host-based truflow feature disabled.\n");
5170         }
5171
5172         return 0;
5173 }
5174
5175 static int
5176 bnxt_parse_devarg_flow_xstat(__rte_unused const char *key,
5177                              const char *value, void *opaque_arg)
5178 {
5179         struct bnxt *bp = opaque_arg;
5180         unsigned long flow_xstat;
5181         char *end = NULL;
5182
5183         if (!value || !opaque_arg) {
5184                 PMD_DRV_LOG(ERR,
5185                             "Invalid parameter passed to flow_xstat devarg.\n");
5186                 return -EINVAL;
5187         }
5188
5189         flow_xstat = strtoul(value, &end, 10);
5190         if (end == NULL || *end != '\0' ||
5191             (flow_xstat == ULONG_MAX && errno == ERANGE)) {
5192                 PMD_DRV_LOG(ERR,
5193                             "Invalid parameter passed to flow_xstat devarg.\n");
5194                 return -EINVAL;
5195         }
5196
5197         if (BNXT_DEVARG_FLOW_XSTAT_INVALID(flow_xstat)) {
5198                 PMD_DRV_LOG(ERR,
5199                             "Invalid value passed to flow_xstat devarg.\n");
5200                 return -EINVAL;
5201         }
5202
5203         bp->flags |= BNXT_FLAG_FLOW_XSTATS_EN;
5204         if (BNXT_FLOW_XSTATS_EN(bp))
5205                 PMD_DRV_LOG(INFO, "flow_xstat feature enabled.\n");
5206
5207         return 0;
5208 }
5209
5210 static int
5211 bnxt_parse_devarg_max_num_kflows(__rte_unused const char *key,
5212                                         const char *value, void *opaque_arg)
5213 {
5214         struct bnxt *bp = opaque_arg;
5215         unsigned long max_num_kflows;
5216         char *end = NULL;
5217
5218         if (!value || !opaque_arg) {
5219                 PMD_DRV_LOG(ERR,
5220                         "Invalid parameter passed to max_num_kflows devarg.\n");
5221                 return -EINVAL;
5222         }
5223
5224         max_num_kflows = strtoul(value, &end, 10);
5225         if (end == NULL || *end != '\0' ||
5226                 (max_num_kflows == ULONG_MAX && errno == ERANGE)) {
5227                 PMD_DRV_LOG(ERR,
5228                         "Invalid parameter passed to max_num_kflows devarg.\n");
5229                 return -EINVAL;
5230         }
5231
5232         if (bnxt_devarg_max_num_kflow_invalid(max_num_kflows)) {
5233                 PMD_DRV_LOG(ERR,
5234                         "Invalid value passed to max_num_kflows devarg.\n");
5235                 return -EINVAL;
5236         }
5237
5238         bp->max_num_kflows = max_num_kflows;
5239         if (bp->max_num_kflows)
5240                 PMD_DRV_LOG(INFO, "max_num_kflows set as %ldK.\n",
5241                                 max_num_kflows);
5242
5243         return 0;
5244 }
5245
5246 static int
5247 bnxt_parse_devarg_rep_is_pf(__rte_unused const char *key,
5248                             const char *value, void *opaque_arg)
5249 {
5250         struct bnxt_representor *vfr_bp = opaque_arg;
5251         unsigned long rep_is_pf;
5252         char *end = NULL;
5253
5254         if (!value || !opaque_arg) {
5255                 PMD_DRV_LOG(ERR,
5256                             "Invalid parameter passed to rep_is_pf devargs.\n");
5257                 return -EINVAL;
5258         }
5259
5260         rep_is_pf = strtoul(value, &end, 10);
5261         if (end == NULL || *end != '\0' ||
5262             (rep_is_pf == ULONG_MAX && errno == ERANGE)) {
5263                 PMD_DRV_LOG(ERR,
5264                             "Invalid parameter passed to rep_is_pf devargs.\n");
5265                 return -EINVAL;
5266         }
5267
5268         if (BNXT_DEVARG_REP_IS_PF_INVALID(rep_is_pf)) {
5269                 PMD_DRV_LOG(ERR,
5270                             "Invalid value passed to rep_is_pf devargs.\n");
5271                 return -EINVAL;
5272         }
5273
5274         vfr_bp->flags |= rep_is_pf;
5275         if (BNXT_REP_PF(vfr_bp))
5276                 PMD_DRV_LOG(INFO, "PF representor\n");
5277         else
5278                 PMD_DRV_LOG(INFO, "VF representor\n");
5279
5280         return 0;
5281 }
5282
5283 static int
5284 bnxt_parse_devarg_rep_based_pf(__rte_unused const char *key,
5285                                const char *value, void *opaque_arg)
5286 {
5287         struct bnxt_representor *vfr_bp = opaque_arg;
5288         unsigned long rep_based_pf;
5289         char *end = NULL;
5290
5291         if (!value || !opaque_arg) {
5292                 PMD_DRV_LOG(ERR,
5293                             "Invalid parameter passed to rep_based_pf "
5294                             "devargs.\n");
5295                 return -EINVAL;
5296         }
5297
5298         rep_based_pf = strtoul(value, &end, 10);
5299         if (end == NULL || *end != '\0' ||
5300             (rep_based_pf == ULONG_MAX && errno == ERANGE)) {
5301                 PMD_DRV_LOG(ERR,
5302                             "Invalid parameter passed to rep_based_pf "
5303                             "devargs.\n");
5304                 return -EINVAL;
5305         }
5306
5307         if (BNXT_DEVARG_REP_BASED_PF_INVALID(rep_based_pf)) {
5308                 PMD_DRV_LOG(ERR,
5309                             "Invalid value passed to rep_based_pf devargs.\n");
5310                 return -EINVAL;
5311         }
5312
5313         vfr_bp->rep_based_pf = rep_based_pf;
5314         vfr_bp->flags |= BNXT_REP_BASED_PF_VALID;
5315
5316         PMD_DRV_LOG(INFO, "rep-based-pf = %d\n", vfr_bp->rep_based_pf);
5317
5318         return 0;
5319 }
5320
5321 static int
5322 bnxt_parse_devarg_rep_q_r2f(__rte_unused const char *key,
5323                             const char *value, void *opaque_arg)
5324 {
5325         struct bnxt_representor *vfr_bp = opaque_arg;
5326         unsigned long rep_q_r2f;
5327         char *end = NULL;
5328
5329         if (!value || !opaque_arg) {
5330                 PMD_DRV_LOG(ERR,
5331                             "Invalid parameter passed to rep_q_r2f "
5332                             "devargs.\n");
5333                 return -EINVAL;
5334         }
5335
5336         rep_q_r2f = strtoul(value, &end, 10);
5337         if (end == NULL || *end != '\0' ||
5338             (rep_q_r2f == ULONG_MAX && errno == ERANGE)) {
5339                 PMD_DRV_LOG(ERR,
5340                             "Invalid parameter passed to rep_q_r2f "
5341                             "devargs.\n");
5342                 return -EINVAL;
5343         }
5344
5345         if (BNXT_DEVARG_REP_Q_R2F_INVALID(rep_q_r2f)) {
5346                 PMD_DRV_LOG(ERR,
5347                             "Invalid value passed to rep_q_r2f devargs.\n");
5348                 return -EINVAL;
5349         }
5350
5351         vfr_bp->rep_q_r2f = rep_q_r2f;
5352         vfr_bp->flags |= BNXT_REP_Q_R2F_VALID;
5353         PMD_DRV_LOG(INFO, "rep-q-r2f = %d\n", vfr_bp->rep_q_r2f);
5354
5355         return 0;
5356 }
5357
5358 static int
5359 bnxt_parse_devarg_rep_q_f2r(__rte_unused const char *key,
5360                             const char *value, void *opaque_arg)
5361 {
5362         struct bnxt_representor *vfr_bp = opaque_arg;
5363         unsigned long rep_q_f2r;
5364         char *end = NULL;
5365
5366         if (!value || !opaque_arg) {
5367                 PMD_DRV_LOG(ERR,
5368                             "Invalid parameter passed to rep_q_f2r "
5369                             "devargs.\n");
5370                 return -EINVAL;
5371         }
5372
5373         rep_q_f2r = strtoul(value, &end, 10);
5374         if (end == NULL || *end != '\0' ||
5375             (rep_q_f2r == ULONG_MAX && errno == ERANGE)) {
5376                 PMD_DRV_LOG(ERR,
5377                             "Invalid parameter passed to rep_q_f2r "
5378                             "devargs.\n");
5379                 return -EINVAL;
5380         }
5381
5382         if (BNXT_DEVARG_REP_Q_F2R_INVALID(rep_q_f2r)) {
5383                 PMD_DRV_LOG(ERR,
5384                             "Invalid value passed to rep_q_f2r devargs.\n");
5385                 return -EINVAL;
5386         }
5387
5388         vfr_bp->rep_q_f2r = rep_q_f2r;
5389         vfr_bp->flags |= BNXT_REP_Q_F2R_VALID;
5390         PMD_DRV_LOG(INFO, "rep-q-f2r = %d\n", vfr_bp->rep_q_f2r);
5391
5392         return 0;
5393 }
5394
5395 static int
5396 bnxt_parse_devarg_rep_fc_r2f(__rte_unused const char *key,
5397                              const char *value, void *opaque_arg)
5398 {
5399         struct bnxt_representor *vfr_bp = opaque_arg;
5400         unsigned long rep_fc_r2f;
5401         char *end = NULL;
5402
5403         if (!value || !opaque_arg) {
5404                 PMD_DRV_LOG(ERR,
5405                             "Invalid parameter passed to rep_fc_r2f "
5406                             "devargs.\n");
5407                 return -EINVAL;
5408         }
5409
5410         rep_fc_r2f = strtoul(value, &end, 10);
5411         if (end == NULL || *end != '\0' ||
5412             (rep_fc_r2f == ULONG_MAX && errno == ERANGE)) {
5413                 PMD_DRV_LOG(ERR,
5414                             "Invalid parameter passed to rep_fc_r2f "
5415                             "devargs.\n");
5416                 return -EINVAL;
5417         }
5418
5419         if (BNXT_DEVARG_REP_FC_R2F_INVALID(rep_fc_r2f)) {
5420                 PMD_DRV_LOG(ERR,
5421                             "Invalid value passed to rep_fc_r2f devargs.\n");
5422                 return -EINVAL;
5423         }
5424
5425         vfr_bp->flags |= BNXT_REP_FC_R2F_VALID;
5426         vfr_bp->rep_fc_r2f = rep_fc_r2f;
5427         PMD_DRV_LOG(INFO, "rep-fc-r2f = %lu\n", rep_fc_r2f);
5428
5429         return 0;
5430 }
5431
5432 static int
5433 bnxt_parse_devarg_rep_fc_f2r(__rte_unused const char *key,
5434                              const char *value, void *opaque_arg)
5435 {
5436         struct bnxt_representor *vfr_bp = opaque_arg;
5437         unsigned long rep_fc_f2r;
5438         char *end = NULL;
5439
5440         if (!value || !opaque_arg) {
5441                 PMD_DRV_LOG(ERR,
5442                             "Invalid parameter passed to rep_fc_f2r "
5443                             "devargs.\n");
5444                 return -EINVAL;
5445         }
5446
5447         rep_fc_f2r = strtoul(value, &end, 10);
5448         if (end == NULL || *end != '\0' ||
5449             (rep_fc_f2r == ULONG_MAX && errno == ERANGE)) {
5450                 PMD_DRV_LOG(ERR,
5451                             "Invalid parameter passed to rep_fc_f2r "
5452                             "devargs.\n");
5453                 return -EINVAL;
5454         }
5455
5456         if (BNXT_DEVARG_REP_FC_F2R_INVALID(rep_fc_f2r)) {
5457                 PMD_DRV_LOG(ERR,
5458                             "Invalid value passed to rep_fc_f2r devargs.\n");
5459                 return -EINVAL;
5460         }
5461
5462         vfr_bp->flags |= BNXT_REP_FC_F2R_VALID;
5463         vfr_bp->rep_fc_f2r = rep_fc_f2r;
5464         PMD_DRV_LOG(INFO, "rep-fc-f2r = %lu\n", rep_fc_f2r);
5465
5466         return 0;
5467 }
5468
5469 static void
5470 bnxt_parse_dev_args(struct bnxt *bp, struct rte_devargs *devargs)
5471 {
5472         struct rte_kvargs *kvlist;
5473
5474         if (devargs == NULL)
5475                 return;
5476
5477         kvlist = rte_kvargs_parse(devargs->args, bnxt_dev_args);
5478         if (kvlist == NULL)
5479                 return;
5480
5481         /*
5482          * Handler for "truflow" devarg.
5483          * Invoked as for ex: "-a 0000:00:0d.0,host-based-truflow=1"
5484          */
5485         rte_kvargs_process(kvlist, BNXT_DEVARG_TRUFLOW,
5486                            bnxt_parse_devarg_truflow, bp);
5487
5488         /*
5489          * Handler for "flow_xstat" devarg.
5490          * Invoked as for ex: "-a 0000:00:0d.0,flow_xstat=1"
5491          */
5492         rte_kvargs_process(kvlist, BNXT_DEVARG_FLOW_XSTAT,
5493                            bnxt_parse_devarg_flow_xstat, bp);
5494
5495         /*
5496          * Handler for "max_num_kflows" devarg.
5497          * Invoked as for ex: "-a 000:00:0d.0,max_num_kflows=32"
5498          */
5499         rte_kvargs_process(kvlist, BNXT_DEVARG_MAX_NUM_KFLOWS,
5500                            bnxt_parse_devarg_max_num_kflows, bp);
5501
5502         rte_kvargs_free(kvlist);
5503 }
5504
5505 static int bnxt_alloc_switch_domain(struct bnxt *bp)
5506 {
5507         int rc = 0;
5508
5509         if (BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp)) {
5510                 rc = rte_eth_switch_domain_alloc(&bp->switch_domain_id);
5511                 if (rc)
5512                         PMD_DRV_LOG(ERR,
5513                                     "Failed to alloc switch domain: %d\n", rc);
5514                 else
5515                         PMD_DRV_LOG(INFO,
5516                                     "Switch domain allocated %d\n",
5517                                     bp->switch_domain_id);
5518         }
5519
5520         return rc;
5521 }
5522
5523 /* Allocate and initialize various fields in bnxt struct that
5524  * need to be allocated/destroyed only once in the lifetime of the driver
5525  */
5526 static int bnxt_drv_init(struct rte_eth_dev *eth_dev)
5527 {
5528         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
5529         struct bnxt *bp = eth_dev->data->dev_private;
5530         int rc = 0;
5531
5532         bp->flags &= ~BNXT_FLAG_RX_VECTOR_PKT_MODE;
5533
5534         if (bnxt_vf_pciid(pci_dev->id.device_id))
5535                 bp->flags |= BNXT_FLAG_VF;
5536
5537         if (bnxt_p5_device(pci_dev->id.device_id))
5538                 bp->flags |= BNXT_FLAG_CHIP_P5;
5539
5540         if (pci_dev->id.device_id == BROADCOM_DEV_ID_58802 ||
5541             pci_dev->id.device_id == BROADCOM_DEV_ID_58804 ||
5542             pci_dev->id.device_id == BROADCOM_DEV_ID_58808 ||
5543             pci_dev->id.device_id == BROADCOM_DEV_ID_58802_VF)
5544                 bp->flags |= BNXT_FLAG_STINGRAY;
5545
5546         if (BNXT_TRUFLOW_EN(bp)) {
5547                 /* extra mbuf field is required to store CFA code from mark */
5548                 static const struct rte_mbuf_dynfield bnxt_cfa_code_dynfield_desc = {
5549                         .name = RTE_PMD_BNXT_CFA_CODE_DYNFIELD_NAME,
5550                         .size = sizeof(bnxt_cfa_code_dynfield_t),
5551                         .align = __alignof__(bnxt_cfa_code_dynfield_t),
5552                 };
5553                 bnxt_cfa_code_dynfield_offset =
5554                         rte_mbuf_dynfield_register(&bnxt_cfa_code_dynfield_desc);
5555                 if (bnxt_cfa_code_dynfield_offset < 0) {
5556                         PMD_DRV_LOG(ERR,
5557                             "Failed to register mbuf field for TruFlow mark\n");
5558                         return -rte_errno;
5559                 }
5560         }
5561
5562         rc = bnxt_map_pci_bars(eth_dev);
5563         if (rc) {
5564                 PMD_DRV_LOG(ERR,
5565                             "Failed to initialize board rc: %x\n", rc);
5566                 return rc;
5567         }
5568
5569         rc = bnxt_alloc_pf_info(bp);
5570         if (rc)
5571                 return rc;
5572
5573         rc = bnxt_alloc_link_info(bp);
5574         if (rc)
5575                 return rc;
5576
5577         rc = bnxt_alloc_parent_info(bp);
5578         if (rc)
5579                 return rc;
5580
5581         rc = bnxt_alloc_hwrm_resources(bp);
5582         if (rc) {
5583                 PMD_DRV_LOG(ERR,
5584                             "Failed to allocate hwrm resource rc: %x\n", rc);
5585                 return rc;
5586         }
5587         rc = bnxt_alloc_leds_info(bp);
5588         if (rc)
5589                 return rc;
5590
5591         rc = bnxt_alloc_cos_queues(bp);
5592         if (rc)
5593                 return rc;
5594
5595         rc = bnxt_init_locks(bp);
5596         if (rc)
5597                 return rc;
5598
5599         rc = bnxt_alloc_switch_domain(bp);
5600         if (rc)
5601                 return rc;
5602
5603         return rc;
5604 }
5605
5606 static int
5607 bnxt_dev_init(struct rte_eth_dev *eth_dev, void *params __rte_unused)
5608 {
5609         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
5610         static int version_printed;
5611         struct bnxt *bp;
5612         int rc;
5613
5614         if (version_printed++ == 0)
5615                 PMD_DRV_LOG(INFO, "%s\n", bnxt_version);
5616
5617         eth_dev->dev_ops = &bnxt_dev_ops;
5618         eth_dev->rx_queue_count = bnxt_rx_queue_count_op;
5619         eth_dev->rx_descriptor_status = bnxt_rx_descriptor_status_op;
5620         eth_dev->tx_descriptor_status = bnxt_tx_descriptor_status_op;
5621         eth_dev->rx_pkt_burst = &bnxt_recv_pkts;
5622         eth_dev->tx_pkt_burst = &bnxt_xmit_pkts;
5623
5624         /*
5625          * For secondary processes, we don't initialise any further
5626          * as primary has already done this work.
5627          */
5628         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
5629                 return 0;
5630
5631         rte_eth_copy_pci_info(eth_dev, pci_dev);
5632         eth_dev->data->dev_flags |= RTE_ETH_DEV_AUTOFILL_QUEUE_XSTATS;
5633
5634         bp = eth_dev->data->dev_private;
5635
5636         /* Parse dev arguments passed on when starting the DPDK application. */
5637         bnxt_parse_dev_args(bp, pci_dev->device.devargs);
5638
5639         rc = bnxt_drv_init(eth_dev);
5640         if (rc)
5641                 goto error_free;
5642
5643         rc = bnxt_init_resources(bp, false);
5644         if (rc)
5645                 goto error_free;
5646
5647         rc = bnxt_alloc_stats_mem(bp);
5648         if (rc)
5649                 goto error_free;
5650
5651         PMD_DRV_LOG(INFO,
5652                     DRV_MODULE_NAME "found at mem %" PRIX64 ", node addr %pM\n",
5653                     pci_dev->mem_resource[0].phys_addr,
5654                     pci_dev->mem_resource[0].addr);
5655
5656         return 0;
5657
5658 error_free:
5659         bnxt_dev_uninit(eth_dev);
5660         return rc;
5661 }
5662
5663
5664 static void bnxt_free_ctx_mem_buf(struct bnxt_ctx_mem_buf_info *ctx)
5665 {
5666         if (!ctx)
5667                 return;
5668
5669         if (ctx->va)
5670                 rte_free(ctx->va);
5671
5672         ctx->va = NULL;
5673         ctx->dma = RTE_BAD_IOVA;
5674         ctx->ctx_id = BNXT_CTX_VAL_INVAL;
5675 }
5676
5677 static void bnxt_unregister_fc_ctx_mem(struct bnxt *bp)
5678 {
5679         bnxt_hwrm_cfa_counter_cfg(bp, BNXT_DIR_RX,
5680                                   CFA_COUNTER_CFG_IN_COUNTER_TYPE_FC,
5681                                   bp->flow_stat->rx_fc_out_tbl.ctx_id,
5682                                   bp->flow_stat->max_fc,
5683                                   false);
5684
5685         bnxt_hwrm_cfa_counter_cfg(bp, BNXT_DIR_TX,
5686                                   CFA_COUNTER_CFG_IN_COUNTER_TYPE_FC,
5687                                   bp->flow_stat->tx_fc_out_tbl.ctx_id,
5688                                   bp->flow_stat->max_fc,
5689                                   false);
5690
5691         if (bp->flow_stat->rx_fc_in_tbl.ctx_id != BNXT_CTX_VAL_INVAL)
5692                 bnxt_hwrm_ctx_unrgtr(bp, bp->flow_stat->rx_fc_in_tbl.ctx_id);
5693         bp->flow_stat->rx_fc_in_tbl.ctx_id = BNXT_CTX_VAL_INVAL;
5694
5695         if (bp->flow_stat->rx_fc_out_tbl.ctx_id != BNXT_CTX_VAL_INVAL)
5696                 bnxt_hwrm_ctx_unrgtr(bp, bp->flow_stat->rx_fc_out_tbl.ctx_id);
5697         bp->flow_stat->rx_fc_out_tbl.ctx_id = BNXT_CTX_VAL_INVAL;
5698
5699         if (bp->flow_stat->tx_fc_in_tbl.ctx_id != BNXT_CTX_VAL_INVAL)
5700                 bnxt_hwrm_ctx_unrgtr(bp, bp->flow_stat->tx_fc_in_tbl.ctx_id);
5701         bp->flow_stat->tx_fc_in_tbl.ctx_id = BNXT_CTX_VAL_INVAL;
5702
5703         if (bp->flow_stat->tx_fc_out_tbl.ctx_id != BNXT_CTX_VAL_INVAL)
5704                 bnxt_hwrm_ctx_unrgtr(bp, bp->flow_stat->tx_fc_out_tbl.ctx_id);
5705         bp->flow_stat->tx_fc_out_tbl.ctx_id = BNXT_CTX_VAL_INVAL;
5706 }
5707
5708 static void bnxt_uninit_fc_ctx_mem(struct bnxt *bp)
5709 {
5710         bnxt_unregister_fc_ctx_mem(bp);
5711
5712         bnxt_free_ctx_mem_buf(&bp->flow_stat->rx_fc_in_tbl);
5713         bnxt_free_ctx_mem_buf(&bp->flow_stat->rx_fc_out_tbl);
5714         bnxt_free_ctx_mem_buf(&bp->flow_stat->tx_fc_in_tbl);
5715         bnxt_free_ctx_mem_buf(&bp->flow_stat->tx_fc_out_tbl);
5716 }
5717
5718 static void bnxt_uninit_ctx_mem(struct bnxt *bp)
5719 {
5720         if (BNXT_FLOW_XSTATS_EN(bp))
5721                 bnxt_uninit_fc_ctx_mem(bp);
5722 }
5723
5724 static void
5725 bnxt_free_error_recovery_info(struct bnxt *bp)
5726 {
5727         rte_free(bp->recovery_info);
5728         bp->recovery_info = NULL;
5729         bp->fw_cap &= ~BNXT_FW_CAP_ERROR_RECOVERY;
5730 }
5731
5732 static int
5733 bnxt_uninit_resources(struct bnxt *bp, bool reconfig_dev)
5734 {
5735         int rc;
5736
5737         bnxt_free_int(bp);
5738         bnxt_free_mem(bp, reconfig_dev);
5739
5740         bnxt_hwrm_func_buf_unrgtr(bp);
5741         rte_free(bp->pf->vf_req_buf);
5742
5743         rc = bnxt_hwrm_func_driver_unregister(bp, 0);
5744         bp->flags &= ~BNXT_FLAG_REGISTERED;
5745         bnxt_free_ctx_mem(bp);
5746         if (!reconfig_dev) {
5747                 bnxt_free_hwrm_resources(bp);
5748                 bnxt_free_error_recovery_info(bp);
5749         }
5750
5751         bnxt_uninit_ctx_mem(bp);
5752
5753         bnxt_free_flow_stats_info(bp);
5754         bnxt_free_rep_info(bp);
5755         rte_free(bp->ptp_cfg);
5756         bp->ptp_cfg = NULL;
5757         return rc;
5758 }
5759
5760 static int
5761 bnxt_dev_uninit(struct rte_eth_dev *eth_dev)
5762 {
5763         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
5764                 return -EPERM;
5765
5766         PMD_DRV_LOG(DEBUG, "Calling Device uninit\n");
5767
5768         if (eth_dev->state != RTE_ETH_DEV_UNUSED)
5769                 bnxt_dev_close_op(eth_dev);
5770
5771         return 0;
5772 }
5773
5774 static int bnxt_pci_remove_dev_with_reps(struct rte_eth_dev *eth_dev)
5775 {
5776         struct bnxt *bp = eth_dev->data->dev_private;
5777         struct rte_eth_dev *vf_rep_eth_dev;
5778         int ret = 0, i;
5779
5780         if (!bp)
5781                 return -EINVAL;
5782
5783         for (i = 0; i < bp->num_reps; i++) {
5784                 vf_rep_eth_dev = bp->rep_info[i].vfr_eth_dev;
5785                 if (!vf_rep_eth_dev)
5786                         continue;
5787                 PMD_DRV_LOG(DEBUG, "BNXT Port:%d VFR pci remove\n",
5788                             vf_rep_eth_dev->data->port_id);
5789                 rte_eth_dev_destroy(vf_rep_eth_dev, bnxt_representor_uninit);
5790         }
5791         PMD_DRV_LOG(DEBUG, "BNXT Port:%d pci remove\n",
5792                     eth_dev->data->port_id);
5793         ret = rte_eth_dev_destroy(eth_dev, bnxt_dev_uninit);
5794
5795         return ret;
5796 }
5797
5798 static void bnxt_free_rep_info(struct bnxt *bp)
5799 {
5800         rte_free(bp->rep_info);
5801         bp->rep_info = NULL;
5802         rte_free(bp->cfa_code_map);
5803         bp->cfa_code_map = NULL;
5804 }
5805
5806 static int bnxt_init_rep_info(struct bnxt *bp)
5807 {
5808         int i = 0, rc;
5809
5810         if (bp->rep_info)
5811                 return 0;
5812
5813         bp->rep_info = rte_zmalloc("bnxt_rep_info",
5814                                    sizeof(bp->rep_info[0]) * BNXT_MAX_VF_REPS,
5815                                    0);
5816         if (!bp->rep_info) {
5817                 PMD_DRV_LOG(ERR, "Failed to alloc memory for rep info\n");
5818                 return -ENOMEM;
5819         }
5820         bp->cfa_code_map = rte_zmalloc("bnxt_cfa_code_map",
5821                                        sizeof(*bp->cfa_code_map) *
5822                                        BNXT_MAX_CFA_CODE, 0);
5823         if (!bp->cfa_code_map) {
5824                 PMD_DRV_LOG(ERR, "Failed to alloc memory for cfa_code_map\n");
5825                 bnxt_free_rep_info(bp);
5826                 return -ENOMEM;
5827         }
5828
5829         for (i = 0; i < BNXT_MAX_CFA_CODE; i++)
5830                 bp->cfa_code_map[i] = BNXT_VF_IDX_INVALID;
5831
5832         rc = pthread_mutex_init(&bp->rep_info->vfr_lock, NULL);
5833         if (rc) {
5834                 PMD_DRV_LOG(ERR, "Unable to initialize vfr_lock\n");
5835                 bnxt_free_rep_info(bp);
5836                 return rc;
5837         }
5838
5839         rc = pthread_mutex_init(&bp->rep_info->vfr_start_lock, NULL);
5840         if (rc) {
5841                 PMD_DRV_LOG(ERR, "Unable to initialize vfr_start_lock\n");
5842                 bnxt_free_rep_info(bp);
5843                 return rc;
5844         }
5845
5846         return rc;
5847 }
5848
5849 static int bnxt_rep_port_probe(struct rte_pci_device *pci_dev,
5850                                struct rte_eth_devargs *eth_da,
5851                                struct rte_eth_dev *backing_eth_dev,
5852                                const char *dev_args)
5853 {
5854         struct rte_eth_dev *vf_rep_eth_dev;
5855         char name[RTE_ETH_NAME_MAX_LEN];
5856         struct bnxt *backing_bp;
5857         uint16_t num_rep;
5858         int i, ret = 0;
5859         struct rte_kvargs *kvlist = NULL;
5860
5861         num_rep = eth_da->nb_representor_ports;
5862         if (num_rep > BNXT_MAX_VF_REPS) {
5863                 PMD_DRV_LOG(ERR, "nb_representor_ports = %d > %d MAX VF REPS\n",
5864                             num_rep, BNXT_MAX_VF_REPS);
5865                 return -EINVAL;
5866         }
5867
5868         if (num_rep >= RTE_MAX_ETHPORTS) {
5869                 PMD_DRV_LOG(ERR,
5870                             "nb_representor_ports = %d > %d MAX ETHPORTS\n",
5871                             num_rep, RTE_MAX_ETHPORTS);
5872                 return -EINVAL;
5873         }
5874
5875         backing_bp = backing_eth_dev->data->dev_private;
5876
5877         if (!(BNXT_PF(backing_bp) || BNXT_VF_IS_TRUSTED(backing_bp))) {
5878                 PMD_DRV_LOG(ERR,
5879                             "Not a PF or trusted VF. No Representor support\n");
5880                 /* Returning an error is not an option.
5881                  * Applications are not handling this correctly
5882                  */
5883                 return 0;
5884         }
5885
5886         if (bnxt_init_rep_info(backing_bp))
5887                 return 0;
5888
5889         for (i = 0; i < num_rep; i++) {
5890                 struct bnxt_representor representor = {
5891                         .vf_id = eth_da->representor_ports[i],
5892                         .switch_domain_id = backing_bp->switch_domain_id,
5893                         .parent_dev = backing_eth_dev
5894                 };
5895
5896                 if (representor.vf_id >= BNXT_MAX_VF_REPS) {
5897                         PMD_DRV_LOG(ERR, "VF-Rep id %d >= %d MAX VF ID\n",
5898                                     representor.vf_id, BNXT_MAX_VF_REPS);
5899                         continue;
5900                 }
5901
5902                 /* representor port net_bdf_port */
5903                 snprintf(name, sizeof(name), "net_%s_representor_%d",
5904                          pci_dev->device.name, eth_da->representor_ports[i]);
5905
5906                 kvlist = rte_kvargs_parse(dev_args, bnxt_dev_args);
5907                 if (kvlist) {
5908                         /*
5909                          * Handler for "rep_is_pf" devarg.
5910                          * Invoked as for ex: "-a 000:00:0d.0,
5911                          * rep-based-pf=<pf index> rep-is-pf=<VF=0 or PF=1>"
5912                          */
5913                         ret = rte_kvargs_process(kvlist, BNXT_DEVARG_REP_IS_PF,
5914                                                  bnxt_parse_devarg_rep_is_pf,
5915                                                  (void *)&representor);
5916                         if (ret) {
5917                                 ret = -EINVAL;
5918                                 goto err;
5919                         }
5920                         /*
5921                          * Handler for "rep_based_pf" devarg.
5922                          * Invoked as for ex: "-a 000:00:0d.0,
5923                          * rep-based-pf=<pf index> rep-is-pf=<VF=0 or PF=1>"
5924                          */
5925                         ret = rte_kvargs_process(kvlist,
5926                                                  BNXT_DEVARG_REP_BASED_PF,
5927                                                  bnxt_parse_devarg_rep_based_pf,
5928                                                  (void *)&representor);
5929                         if (ret) {
5930                                 ret = -EINVAL;
5931                                 goto err;
5932                         }
5933                         /*
5934                          * Handler for "rep_based_pf" devarg.
5935                          * Invoked as for ex: "-a 000:00:0d.0,
5936                          * rep-based-pf=<pf index> rep-is-pf=<VF=0 or PF=1>"
5937                          */
5938                         ret = rte_kvargs_process(kvlist, BNXT_DEVARG_REP_Q_R2F,
5939                                                  bnxt_parse_devarg_rep_q_r2f,
5940                                                  (void *)&representor);
5941                         if (ret) {
5942                                 ret = -EINVAL;
5943                                 goto err;
5944                         }
5945                         /*
5946                          * Handler for "rep_based_pf" devarg.
5947                          * Invoked as for ex: "-a 000:00:0d.0,
5948                          * rep-based-pf=<pf index> rep-is-pf=<VF=0 or PF=1>"
5949                          */
5950                         ret = rte_kvargs_process(kvlist, BNXT_DEVARG_REP_Q_F2R,
5951                                                  bnxt_parse_devarg_rep_q_f2r,
5952                                                  (void *)&representor);
5953                         if (ret) {
5954                                 ret = -EINVAL;
5955                                 goto err;
5956                         }
5957                         /*
5958                          * Handler for "rep_based_pf" devarg.
5959                          * Invoked as for ex: "-a 000:00:0d.0,
5960                          * rep-based-pf=<pf index> rep-is-pf=<VF=0 or PF=1>"
5961                          */
5962                         ret = rte_kvargs_process(kvlist, BNXT_DEVARG_REP_FC_R2F,
5963                                                  bnxt_parse_devarg_rep_fc_r2f,
5964                                                  (void *)&representor);
5965                         if (ret) {
5966                                 ret = -EINVAL;
5967                                 goto err;
5968                         }
5969                         /*
5970                          * Handler for "rep_based_pf" devarg.
5971                          * Invoked as for ex: "-a 000:00:0d.0,
5972                          * rep-based-pf=<pf index> rep-is-pf=<VF=0 or PF=1>"
5973                          */
5974                         ret = rte_kvargs_process(kvlist, BNXT_DEVARG_REP_FC_F2R,
5975                                                  bnxt_parse_devarg_rep_fc_f2r,
5976                                                  (void *)&representor);
5977                         if (ret) {
5978                                 ret = -EINVAL;
5979                                 goto err;
5980                         }
5981                 }
5982
5983                 ret = rte_eth_dev_create(&pci_dev->device, name,
5984                                          sizeof(struct bnxt_representor),
5985                                          NULL, NULL,
5986                                          bnxt_representor_init,
5987                                          &representor);
5988                 if (ret) {
5989                         PMD_DRV_LOG(ERR, "failed to create bnxt vf "
5990                                     "representor %s.", name);
5991                         goto err;
5992                 }
5993
5994                 vf_rep_eth_dev = rte_eth_dev_allocated(name);
5995                 if (!vf_rep_eth_dev) {
5996                         PMD_DRV_LOG(ERR, "Failed to find the eth_dev"
5997                                     " for VF-Rep: %s.", name);
5998                         ret = -ENODEV;
5999                         goto err;
6000                 }
6001
6002                 PMD_DRV_LOG(DEBUG, "BNXT Port:%d VFR pci probe\n",
6003                             backing_eth_dev->data->port_id);
6004                 backing_bp->rep_info[representor.vf_id].vfr_eth_dev =
6005                                                          vf_rep_eth_dev;
6006                 backing_bp->num_reps++;
6007
6008         }
6009
6010         rte_kvargs_free(kvlist);
6011         return 0;
6012
6013 err:
6014         /* If num_rep > 1, then rollback already created
6015          * ports, since we'll be failing the probe anyway
6016          */
6017         if (num_rep > 1)
6018                 bnxt_pci_remove_dev_with_reps(backing_eth_dev);
6019         rte_errno = -ret;
6020         rte_kvargs_free(kvlist);
6021
6022         return ret;
6023 }
6024
6025 static int bnxt_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
6026                           struct rte_pci_device *pci_dev)
6027 {
6028         struct rte_eth_devargs eth_da = { .nb_representor_ports = 0 };
6029         struct rte_eth_dev *backing_eth_dev;
6030         uint16_t num_rep;
6031         int ret = 0;
6032
6033         if (pci_dev->device.devargs) {
6034                 ret = rte_eth_devargs_parse(pci_dev->device.devargs->args,
6035                                             &eth_da);
6036                 if (ret)
6037                         return ret;
6038         }
6039
6040         num_rep = eth_da.nb_representor_ports;
6041         PMD_DRV_LOG(DEBUG, "nb_representor_ports = %d\n",
6042                     num_rep);
6043
6044         /* We could come here after first level of probe is already invoked
6045          * as part of an application bringup(OVS-DPDK vswitchd), so first check
6046          * for already allocated eth_dev for the backing device (PF/Trusted VF)
6047          */
6048         backing_eth_dev = rte_eth_dev_allocated(pci_dev->device.name);
6049         if (backing_eth_dev == NULL) {
6050                 ret = rte_eth_dev_create(&pci_dev->device, pci_dev->device.name,
6051                                          sizeof(struct bnxt),
6052                                          eth_dev_pci_specific_init, pci_dev,
6053                                          bnxt_dev_init, NULL);
6054
6055                 if (ret || !num_rep)
6056                         return ret;
6057
6058                 backing_eth_dev = rte_eth_dev_allocated(pci_dev->device.name);
6059         }
6060         PMD_DRV_LOG(DEBUG, "BNXT Port:%d pci probe\n",
6061                     backing_eth_dev->data->port_id);
6062
6063         if (!num_rep)
6064                 return ret;
6065
6066         /* probe representor ports now */
6067         ret = bnxt_rep_port_probe(pci_dev, &eth_da, backing_eth_dev,
6068                                   pci_dev->device.devargs->args);
6069
6070         return ret;
6071 }
6072
6073 static int bnxt_pci_remove(struct rte_pci_device *pci_dev)
6074 {
6075         struct rte_eth_dev *eth_dev;
6076
6077         eth_dev = rte_eth_dev_allocated(pci_dev->device.name);
6078         if (!eth_dev)
6079                 return 0; /* Invoked typically only by OVS-DPDK, by the
6080                            * time it comes here the eth_dev is already
6081                            * deleted by rte_eth_dev_close(), so returning
6082                            * +ve value will at least help in proper cleanup
6083                            */
6084
6085         PMD_DRV_LOG(DEBUG, "BNXT Port:%d pci remove\n", eth_dev->data->port_id);
6086         if (rte_eal_process_type() == RTE_PROC_PRIMARY) {
6087                 if (eth_dev->data->dev_flags & RTE_ETH_DEV_REPRESENTOR)
6088                         return rte_eth_dev_destroy(eth_dev,
6089                                                    bnxt_representor_uninit);
6090                 else
6091                         return rte_eth_dev_destroy(eth_dev,
6092                                                    bnxt_dev_uninit);
6093         } else {
6094                 return rte_eth_dev_pci_generic_remove(pci_dev, NULL);
6095         }
6096 }
6097
6098 static struct rte_pci_driver bnxt_rte_pmd = {
6099         .id_table = bnxt_pci_id_map,
6100         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC |
6101                         RTE_PCI_DRV_PROBE_AGAIN, /* Needed in case of VF-REPs
6102                                                   * and OVS-DPDK
6103                                                   */
6104         .probe = bnxt_pci_probe,
6105         .remove = bnxt_pci_remove,
6106 };
6107
6108 static bool
6109 is_device_supported(struct rte_eth_dev *dev, struct rte_pci_driver *drv)
6110 {
6111         if (strcmp(dev->device->driver->name, drv->driver.name))
6112                 return false;
6113
6114         return true;
6115 }
6116
6117 bool is_bnxt_supported(struct rte_eth_dev *dev)
6118 {
6119         return is_device_supported(dev, &bnxt_rte_pmd);
6120 }
6121
6122 RTE_LOG_REGISTER(bnxt_logtype_driver, pmd.net.bnxt.driver, NOTICE);
6123 RTE_PMD_REGISTER_PCI(net_bnxt, bnxt_rte_pmd);
6124 RTE_PMD_REGISTER_PCI_TABLE(net_bnxt, bnxt_pci_id_map);
6125 RTE_PMD_REGISTER_KMOD_DEP(net_bnxt, "* igb_uio | uio_pci_generic | vfio-pci");