drivers/net/bnxt/bnxt_ethdev.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2014-2018 Broadcom
   3  * All rights reserved.
   4  */
   5
   6 #include <inttypes.h>
   7 #include <stdbool.h>
   8
   9 #include <rte_dev.h>
  10 #include <rte_ethdev_driver.h>
  11 #include <rte_ethdev_pci.h>
  12 #include <rte_malloc.h>
  13 #include <rte_cycles.h>
  14 #include <rte_alarm.h>
  15 #include <rte_kvargs.h>
  16
  17 #include "bnxt.h"
  18 #include "bnxt_filter.h"
  19 #include "bnxt_hwrm.h"
  20 #include "bnxt_irq.h"
  21 #include "bnxt_reps.h"
  22 #include "bnxt_ring.h"
  23 #include "bnxt_rxq.h"
  24 #include "bnxt_rxr.h"
  25 #include "bnxt_stats.h"
  26 #include "bnxt_txq.h"
  27 #include "bnxt_txr.h"
  28 #include "bnxt_vnic.h"
  29 #include "hsi_struct_def_dpdk.h"
  30 #include "bnxt_nvm_defs.h"
  31 #include "bnxt_tf_common.h"
  32 #include "ulp_flow_db.h"
  33
  34 #define DRV_MODULE_NAME         "bnxt"
  35 static const char bnxt_version[] =
  36         "Broadcom NetXtreme driver " DRV_MODULE_NAME;
  37
  38 /*
  39  * The set of PCI devices this driver supports
  40  */
  41 static const struct rte_pci_id bnxt_pci_id_map[] = {
  42         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM,
  43                          BROADCOM_DEV_ID_STRATUS_NIC_VF1) },
  44         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM,
  45                          BROADCOM_DEV_ID_STRATUS_NIC_VF2) },
  46         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_STRATUS_NIC) },
  47         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414_VF) },
  48         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57301) },
  49         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57302) },
  50         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57304_PF) },
  51         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57304_VF) },
  52         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_NS2) },
  53         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57402) },
  54         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57404) },
  55         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57406_PF) },
  56         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57406_VF) },
  57         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57402_MF) },
  58         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57407_RJ45) },
  59         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57404_MF) },
  60         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57406_MF) },
  61         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57407_SFP) },
  62         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57407_MF) },
  63         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_5741X_VF) },
  64         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_5731X_VF) },
  65         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57314) },
  66         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_MF) },
  67         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57311) },
  68         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57312) },
  69         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57412) },
  70         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414) },
  71         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_RJ45) },
  72         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_RJ45) },
  73         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57412_MF) },
  74         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57317_RJ45) },
  75         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_SFP) },
  76         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_SFP) },
  77         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57317_SFP) },
  78         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414_MF) },
  79         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_MF) },
  80         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58802) },
  81         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58804) },
  82         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58808) },
  83         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58802_VF) },
  84         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57508) },
  85         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57504) },
  86         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57502) },
  87         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57500_VF1) },
  88         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57500_VF2) },
  89         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57508_MF1) },
  90         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57504_MF1) },
  91         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57502_MF1) },
  92         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57508_MF2) },
  93         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57504_MF2) },
  94         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57502_MF2) },
  95         { .vendor_id = 0, /* sentinel */ },
  96 };
  97
  98 #define BNXT_DEVARG_TRUFLOW     "host-based-truflow"
  99 #define BNXT_DEVARG_FLOW_XSTAT  "flow-xstat"
 100 #define BNXT_DEVARG_MAX_NUM_KFLOWS  "max-num-kflows"
 101 #define BNXT_DEVARG_REPRESENTOR "representor"
 102
 103 static const char *const bnxt_dev_args[] = {
 104         BNXT_DEVARG_REPRESENTOR,
 105         BNXT_DEVARG_TRUFLOW,
 106         BNXT_DEVARG_FLOW_XSTAT,
 107         BNXT_DEVARG_MAX_NUM_KFLOWS,
 108         NULL
 109 };
 110
 111 /*
 112  * truflow == false to disable the feature
 113  * truflow == true to enable the feature
 114  */
 115 #define BNXT_DEVARG_TRUFLOW_INVALID(truflow)    ((truflow) > 1)
 116
 117 /*
 118  * flow_xstat == false to disable the feature
 119  * flow_xstat == true to enable the feature
 120  */
 121 #define BNXT_DEVARG_FLOW_XSTAT_INVALID(flow_xstat)      ((flow_xstat) > 1)
 122
 123 /*
 124  * max_num_kflows must be >= 32
 125  * and must be a power-of-2 supported value
 126  * return: 1 -> invalid
 127  *         0 -> valid
 128  */
 129 static int bnxt_devarg_max_num_kflow_invalid(uint16_t max_num_kflows)
 130 {
 131         if (max_num_kflows < 32 || !rte_is_power_of_2(max_num_kflows))
 132                 return 1;
 133         return 0;
 134 }
 135
 136 static int bnxt_vlan_offload_set_op(struct rte_eth_dev *dev, int mask);
 137 static int bnxt_dev_uninit(struct rte_eth_dev *eth_dev);
 138 static int bnxt_init_resources(struct bnxt *bp, bool reconfig_dev);
 139 static int bnxt_uninit_resources(struct bnxt *bp, bool reconfig_dev);
 140 static void bnxt_cancel_fw_health_check(struct bnxt *bp);
 141 static int bnxt_restore_vlan_filters(struct bnxt *bp);
 142 static void bnxt_dev_recover(void *arg);
 143 static void bnxt_free_error_recovery_info(struct bnxt *bp);
 144 static void bnxt_free_rep_info(struct bnxt *bp);
 145
 146 int is_bnxt_in_error(struct bnxt *bp)
 147 {
 148         if (bp->flags & BNXT_FLAG_FATAL_ERROR)
 149                 return -EIO;
 150         if (bp->flags & BNXT_FLAG_FW_RESET)
 151                 return -EBUSY;
 152
 153         return 0;
 154 }
 155
 156 /***********************/
 157
 158 /*
 159  * High level utility functions
 160  */
 161
 162 static uint16_t bnxt_rss_ctxts(const struct bnxt *bp)
 163 {
 164         if (!BNXT_CHIP_THOR(bp))
 165                 return 1;
 166
 167         return RTE_ALIGN_MUL_CEIL(bp->rx_nr_rings,
 168                                   BNXT_RSS_ENTRIES_PER_CTX_THOR) /
 169                                     BNXT_RSS_ENTRIES_PER_CTX_THOR;
 170 }
 171
 172 uint16_t bnxt_rss_hash_tbl_size(const struct bnxt *bp)
 173 {
 174         if (!BNXT_CHIP_THOR(bp))
 175                 return HW_HASH_INDEX_SIZE;
 176
 177         return bnxt_rss_ctxts(bp) * BNXT_RSS_ENTRIES_PER_CTX_THOR;
 178 }
 179
 180 static void bnxt_free_parent_info(struct bnxt *bp)
 181 {
 182         rte_free(bp->parent);
 183 }
 184
 185 static void bnxt_free_pf_info(struct bnxt *bp)
 186 {
 187         rte_free(bp->pf);
 188 }
 189
 190 static void bnxt_free_link_info(struct bnxt *bp)
 191 {
 192         rte_free(bp->link_info);
 193 }
 194
 195 static void bnxt_free_leds_info(struct bnxt *bp)
 196 {
 197         if (BNXT_VF(bp))
 198                 return;
 199
 200         rte_free(bp->leds);
 201         bp->leds = NULL;
 202 }
 203
 204 static void bnxt_free_flow_stats_info(struct bnxt *bp)
 205 {
 206         rte_free(bp->flow_stat);
 207         bp->flow_stat = NULL;
 208 }
 209
 210 static void bnxt_free_cos_queues(struct bnxt *bp)
 211 {
 212         rte_free(bp->rx_cos_queue);
 213         rte_free(bp->tx_cos_queue);
 214 }
 215
 216 static void bnxt_free_mem(struct bnxt *bp, bool reconfig)
 217 {
 218         bnxt_free_filter_mem(bp);
 219         bnxt_free_vnic_attributes(bp);
 220         bnxt_free_vnic_mem(bp);
 221
 222         /* tx/rx rings are configured as part of *_queue_setup callbacks.
 223          * If the number of rings change across fw update,
 224          * we don't have much choice except to warn the user.
 225          */
 226         if (!reconfig) {
 227                 bnxt_free_stats(bp);
 228                 bnxt_free_tx_rings(bp);
 229                 bnxt_free_rx_rings(bp);
 230         }
 231         bnxt_free_async_cp_ring(bp);
 232         bnxt_free_rxtx_nq_ring(bp);
 233
 234         rte_free(bp->grp_info);
 235         bp->grp_info = NULL;
 236 }
 237
 238 static int bnxt_alloc_parent_info(struct bnxt *bp)
 239 {
 240         bp->parent = rte_zmalloc("bnxt_parent_info",
 241                                  sizeof(struct bnxt_parent_info), 0);
 242         if (bp->parent == NULL)
 243                 return -ENOMEM;
 244
 245         return 0;
 246 }
 247
 248 static int bnxt_alloc_pf_info(struct bnxt *bp)
 249 {
 250         bp->pf = rte_zmalloc("bnxt_pf_info", sizeof(struct bnxt_pf_info), 0);
 251         if (bp->pf == NULL)
 252                 return -ENOMEM;
 253
 254         return 0;
 255 }
 256
 257 static int bnxt_alloc_link_info(struct bnxt *bp)
 258 {
 259         bp->link_info =
 260                 rte_zmalloc("bnxt_link_info", sizeof(struct bnxt_link_info), 0);
 261         if (bp->link_info == NULL)
 262                 return -ENOMEM;
 263
 264         return 0;
 265 }
 266
 267 static int bnxt_alloc_leds_info(struct bnxt *bp)
 268 {
 269         if (BNXT_VF(bp))
 270                 return 0;
 271
 272         bp->leds = rte_zmalloc("bnxt_leds",
 273                                BNXT_MAX_LED * sizeof(struct bnxt_led_info),
 274                                0);
 275         if (bp->leds == NULL)
 276                 return -ENOMEM;
 277
 278         return 0;
 279 }
 280
 281 static int bnxt_alloc_cos_queues(struct bnxt *bp)
 282 {
 283         bp->rx_cos_queue =
 284                 rte_zmalloc("bnxt_rx_cosq",
 285                             BNXT_COS_QUEUE_COUNT *
 286                             sizeof(struct bnxt_cos_queue_info),
 287                             0);
 288         if (bp->rx_cos_queue == NULL)
 289                 return -ENOMEM;
 290
 291         bp->tx_cos_queue =
 292                 rte_zmalloc("bnxt_tx_cosq",
 293                             BNXT_COS_QUEUE_COUNT *
 294                             sizeof(struct bnxt_cos_queue_info),
 295                             0);
 296         if (bp->tx_cos_queue == NULL)
 297                 return -ENOMEM;
 298
 299         return 0;
 300 }
 301
 302 static int bnxt_alloc_flow_stats_info(struct bnxt *bp)
 303 {
 304         bp->flow_stat = rte_zmalloc("bnxt_flow_xstat",
 305                                     sizeof(struct bnxt_flow_stat_info), 0);
 306         if (bp->flow_stat == NULL)
 307                 return -ENOMEM;
 308
 309         return 0;
 310 }
 311
 312 static int bnxt_alloc_mem(struct bnxt *bp, bool reconfig)
 313 {
 314         int rc;
 315
 316         rc = bnxt_alloc_ring_grps(bp);
 317         if (rc)
 318                 goto alloc_mem_err;
 319
 320         rc = bnxt_alloc_async_ring_struct(bp);
 321         if (rc)
 322                 goto alloc_mem_err;
 323
 324         rc = bnxt_alloc_vnic_mem(bp);
 325         if (rc)
 326                 goto alloc_mem_err;
 327
 328         rc = bnxt_alloc_vnic_attributes(bp);
 329         if (rc)
 330                 goto alloc_mem_err;
 331
 332         rc = bnxt_alloc_filter_mem(bp);
 333         if (rc)
 334                 goto alloc_mem_err;
 335
 336         rc = bnxt_alloc_async_cp_ring(bp);
 337         if (rc)
 338                 goto alloc_mem_err;
 339
 340         rc = bnxt_alloc_rxtx_nq_ring(bp);
 341         if (rc)
 342                 goto alloc_mem_err;
 343
 344         if (BNXT_FLOW_XSTATS_EN(bp)) {
 345                 rc = bnxt_alloc_flow_stats_info(bp);
 346                 if (rc)
 347                         goto alloc_mem_err;
 348         }
 349
 350         return 0;
 351
 352 alloc_mem_err:
 353         bnxt_free_mem(bp, reconfig);
 354         return rc;
 355 }
 356
 357 static int bnxt_setup_one_vnic(struct bnxt *bp, uint16_t vnic_id)
 358 {
 359         struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
 360         struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id];
 361         uint64_t rx_offloads = dev_conf->rxmode.offloads;
 362         struct bnxt_rx_queue *rxq;
 363         unsigned int j;
 364         int rc;
 365
 366         rc = bnxt_vnic_grp_alloc(bp, vnic);
 367         if (rc)
 368                 goto err_out;
 369
 370         PMD_DRV_LOG(DEBUG, "vnic[%d] = %p vnic->fw_grp_ids = %p\n",
 371                     vnic_id, vnic, vnic->fw_grp_ids);
 372
 373         rc = bnxt_hwrm_vnic_alloc(bp, vnic);
 374         if (rc)
 375                 goto err_out;
 376
 377         /* Alloc RSS context only if RSS mode is enabled */
 378         if (dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS) {
 379                 int j, nr_ctxs = bnxt_rss_ctxts(bp);
 380
 381                 rc = 0;
 382                 for (j = 0; j < nr_ctxs; j++) {
 383                         rc = bnxt_hwrm_vnic_ctx_alloc(bp, vnic, j);
 384                         if (rc)
 385                                 break;
 386                 }
 387                 if (rc) {
 388                         PMD_DRV_LOG(ERR,
 389                                     "HWRM vnic %d ctx %d alloc failure rc: %x\n",
 390                                     vnic_id, j, rc);
 391                         goto err_out;
 392                 }
 393                 vnic->num_lb_ctxts = nr_ctxs;
 394         }
 395
 396         /*
 397          * Firmware sets pf pair in default vnic cfg. If the VLAN strip
 398          * setting is not available at this time, it will not be
 399          * configured correctly in the CFA.
 400          */
 401         if (rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
 402                 vnic->vlan_strip = true;
 403         else
 404                 vnic->vlan_strip = false;
 405
 406         rc = bnxt_hwrm_vnic_cfg(bp, vnic);
 407         if (rc)
 408                 goto err_out;
 409
 410         rc = bnxt_set_hwrm_vnic_filters(bp, vnic);
 411         if (rc)
 412                 goto err_out;
 413
 414         for (j = 0; j < bp->rx_num_qs_per_vnic; j++) {
 415                 rxq = bp->eth_dev->data->rx_queues[j];
 416
 417                 PMD_DRV_LOG(DEBUG,
 418                             "rxq[%d]->vnic=%p vnic->fw_grp_ids=%p\n",
 419                             j, rxq->vnic, rxq->vnic->fw_grp_ids);
 420
 421                 if (BNXT_HAS_RING_GRPS(bp) && rxq->rx_deferred_start)
 422                         rxq->vnic->fw_grp_ids[j] = INVALID_HW_RING_ID;
 423                 else
 424                         vnic->rx_queue_cnt++;
 425         }
 426
 427         PMD_DRV_LOG(DEBUG, "vnic->rx_queue_cnt = %d\n", vnic->rx_queue_cnt);
 428
 429         rc = bnxt_vnic_rss_configure(bp, vnic);
 430         if (rc)
 431                 goto err_out;
 432
 433         bnxt_hwrm_vnic_plcmode_cfg(bp, vnic);
 434
 435         if (rx_offloads & DEV_RX_OFFLOAD_TCP_LRO)
 436                 bnxt_hwrm_vnic_tpa_cfg(bp, vnic, 1);
 437         else
 438                 bnxt_hwrm_vnic_tpa_cfg(bp, vnic, 0);
 439
 440         return 0;
 441 err_out:
 442         PMD_DRV_LOG(ERR, "HWRM vnic %d cfg failure rc: %x\n",
 443                     vnic_id, rc);
 444         return rc;
 445 }
 446
 447 static int bnxt_register_fc_ctx_mem(struct bnxt *bp)
 448 {
 449         int rc = 0;
 450
 451         rc = bnxt_hwrm_ctx_rgtr(bp, bp->flow_stat->rx_fc_in_tbl.dma,
 452                                 &bp->flow_stat->rx_fc_in_tbl.ctx_id);
 453         if (rc)
 454                 return rc;
 455
 456         PMD_DRV_LOG(DEBUG,
 457                     "rx_fc_in_tbl.va = %p rx_fc_in_tbl.dma = %p"
 458                     " rx_fc_in_tbl.ctx_id = %d\n",
 459                     bp->flow_stat->rx_fc_in_tbl.va,
 460                     (void *)((uintptr_t)bp->flow_stat->rx_fc_in_tbl.dma),
 461                     bp->flow_stat->rx_fc_in_tbl.ctx_id);
 462
 463         rc = bnxt_hwrm_ctx_rgtr(bp, bp->flow_stat->rx_fc_out_tbl.dma,
 464                                 &bp->flow_stat->rx_fc_out_tbl.ctx_id);
 465         if (rc)
 466                 return rc;
 467
 468         PMD_DRV_LOG(DEBUG,
 469                     "rx_fc_out_tbl.va = %p rx_fc_out_tbl.dma = %p"
 470                     " rx_fc_out_tbl.ctx_id = %d\n",
 471                     bp->flow_stat->rx_fc_out_tbl.va,
 472                     (void *)((uintptr_t)bp->flow_stat->rx_fc_out_tbl.dma),
 473                     bp->flow_stat->rx_fc_out_tbl.ctx_id);
 474
 475         rc = bnxt_hwrm_ctx_rgtr(bp, bp->flow_stat->tx_fc_in_tbl.dma,
 476                                 &bp->flow_stat->tx_fc_in_tbl.ctx_id);
 477         if (rc)
 478                 return rc;
 479
 480         PMD_DRV_LOG(DEBUG,
 481                     "tx_fc_in_tbl.va = %p tx_fc_in_tbl.dma = %p"
 482                     " tx_fc_in_tbl.ctx_id = %d\n",
 483                     bp->flow_stat->tx_fc_in_tbl.va,
 484                     (void *)((uintptr_t)bp->flow_stat->tx_fc_in_tbl.dma),
 485                     bp->flow_stat->tx_fc_in_tbl.ctx_id);
 486
 487         rc = bnxt_hwrm_ctx_rgtr(bp, bp->flow_stat->tx_fc_out_tbl.dma,
 488                                 &bp->flow_stat->tx_fc_out_tbl.ctx_id);
 489         if (rc)
 490                 return rc;
 491
 492         PMD_DRV_LOG(DEBUG,
 493                     "tx_fc_out_tbl.va = %p tx_fc_out_tbl.dma = %p"
 494                     " tx_fc_out_tbl.ctx_id = %d\n",
 495                     bp->flow_stat->tx_fc_out_tbl.va,
 496                     (void *)((uintptr_t)bp->flow_stat->tx_fc_out_tbl.dma),
 497                     bp->flow_stat->tx_fc_out_tbl.ctx_id);
 498
 499         memset(bp->flow_stat->rx_fc_out_tbl.va,
 500                0,
 501                bp->flow_stat->rx_fc_out_tbl.size);
 502         rc = bnxt_hwrm_cfa_counter_cfg(bp, BNXT_DIR_RX,
 503                                        CFA_COUNTER_CFG_IN_COUNTER_TYPE_FC,
 504                                        bp->flow_stat->rx_fc_out_tbl.ctx_id,
 505                                        bp->flow_stat->max_fc,
 506                                        true);
 507         if (rc)
 508                 return rc;
 509
 510         memset(bp->flow_stat->tx_fc_out_tbl.va,
 511                0,
 512                bp->flow_stat->tx_fc_out_tbl.size);
 513         rc = bnxt_hwrm_cfa_counter_cfg(bp, BNXT_DIR_TX,
 514                                        CFA_COUNTER_CFG_IN_COUNTER_TYPE_FC,
 515                                        bp->flow_stat->tx_fc_out_tbl.ctx_id,
 516                                        bp->flow_stat->max_fc,
 517                                        true);
 518
 519         return rc;
 520 }
 521
 522 static int bnxt_alloc_ctx_mem_buf(char *type, size_t size,
 523                                   struct bnxt_ctx_mem_buf_info *ctx)
 524 {
 525         if (!ctx)
 526                 return -EINVAL;
 527
 528         ctx->va = rte_zmalloc(type, size, 0);
 529         if (ctx->va == NULL)
 530                 return -ENOMEM;
 531         rte_mem_lock_page(ctx->va);
 532         ctx->size = size;
 533         ctx->dma = rte_mem_virt2iova(ctx->va);
 534         if (ctx->dma == RTE_BAD_IOVA)
 535                 return -ENOMEM;
 536
 537         return 0;
 538 }
 539
 540 static int bnxt_init_fc_ctx_mem(struct bnxt *bp)
 541 {
 542         struct rte_pci_device *pdev = bp->pdev;
 543         char type[RTE_MEMZONE_NAMESIZE];
 544         uint16_t max_fc;
 545         int rc = 0;
 546
 547         max_fc = bp->flow_stat->max_fc;
 548
 549         sprintf(type, "bnxt_rx_fc_in_" PCI_PRI_FMT, pdev->addr.domain,
 550                 pdev->addr.bus, pdev->addr.devid, pdev->addr.function);
 551         /* 4 bytes for each counter-id */
 552         rc = bnxt_alloc_ctx_mem_buf(type,
 553                                     max_fc * 4,
 554                                     &bp->flow_stat->rx_fc_in_tbl);
 555         if (rc)
 556                 return rc;
 557
 558         sprintf(type, "bnxt_rx_fc_out_" PCI_PRI_FMT, pdev->addr.domain,
 559                 pdev->addr.bus, pdev->addr.devid, pdev->addr.function);
 560         /* 16 bytes for each counter - 8 bytes pkt_count, 8 bytes byte_count */
 561         rc = bnxt_alloc_ctx_mem_buf(type,
 562                                     max_fc * 16,
 563                                     &bp->flow_stat->rx_fc_out_tbl);
 564         if (rc)
 565                 return rc;
 566
 567         sprintf(type, "bnxt_tx_fc_in_" PCI_PRI_FMT, pdev->addr.domain,
 568                 pdev->addr.bus, pdev->addr.devid, pdev->addr.function);
 569         /* 4 bytes for each counter-id */
 570         rc = bnxt_alloc_ctx_mem_buf(type,
 571                                     max_fc * 4,
 572                                     &bp->flow_stat->tx_fc_in_tbl);
 573         if (rc)
 574                 return rc;
 575
 576         sprintf(type, "bnxt_tx_fc_out_" PCI_PRI_FMT, pdev->addr.domain,
 577                 pdev->addr.bus, pdev->addr.devid, pdev->addr.function);
 578         /* 16 bytes for each counter - 8 bytes pkt_count, 8 bytes byte_count */
 579         rc = bnxt_alloc_ctx_mem_buf(type,
 580                                     max_fc * 16,
 581                                     &bp->flow_stat->tx_fc_out_tbl);
 582         if (rc)
 583                 return rc;
 584
 585         rc = bnxt_register_fc_ctx_mem(bp);
 586
 587         return rc;
 588 }
 589
 590 static int bnxt_init_ctx_mem(struct bnxt *bp)
 591 {
 592         int rc = 0;
 593
 594         if (!(bp->fw_cap & BNXT_FW_CAP_ADV_FLOW_COUNTERS) ||
 595             !(BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp)) ||
 596             !BNXT_FLOW_XSTATS_EN(bp))
 597                 return 0;
 598
 599         rc = bnxt_hwrm_cfa_counter_qcaps(bp, &bp->flow_stat->max_fc);
 600         if (rc)
 601                 return rc;
 602
 603         rc = bnxt_init_fc_ctx_mem(bp);
 604
 605         return rc;
 606 }
 607
 608 static int bnxt_update_phy_setting(struct bnxt *bp)
 609 {
 610         struct rte_eth_link new;
 611         int rc;
 612
 613         rc = bnxt_get_hwrm_link_config(bp, &new);
 614         if (rc) {
 615                 PMD_DRV_LOG(ERR, "Failed to get link settings\n");
 616                 return rc;
 617         }
 618
 619         /*
 620          * On BCM957508-N2100 adapters, FW will not allow any user other
 621          * than BMC to shutdown the port. bnxt_get_hwrm_link_config() call
 622          * always returns link up. Force phy update always in that case.
 623          */
 624         if (!new.link_status || IS_BNXT_DEV_957508_N2100(bp)) {
 625                 rc = bnxt_set_hwrm_link_config(bp, true);
 626                 if (rc) {
 627                         PMD_DRV_LOG(ERR, "Failed to update PHY settings\n");
 628                         return rc;
 629                 }
 630         }
 631
 632         return rc;
 633 }
 634
 635 static int bnxt_init_chip(struct bnxt *bp)
 636 {
 637         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(bp->eth_dev);
 638         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
 639         uint32_t intr_vector = 0;
 640         uint32_t queue_id, base = BNXT_MISC_VEC_ID;
 641         uint32_t vec = BNXT_MISC_VEC_ID;
 642         unsigned int i, j;
 643         int rc;
 644
 645         if (bp->eth_dev->data->mtu > RTE_ETHER_MTU) {
 646                 bp->eth_dev->data->dev_conf.rxmode.offloads |=
 647                         DEV_RX_OFFLOAD_JUMBO_FRAME;
 648                 bp->flags |= BNXT_FLAG_JUMBO;
 649         } else {
 650                 bp->eth_dev->data->dev_conf.rxmode.offloads &=
 651                         ~DEV_RX_OFFLOAD_JUMBO_FRAME;
 652                 bp->flags &= ~BNXT_FLAG_JUMBO;
 653         }
 654
 655         /* THOR does not support ring groups.
 656          * But we will use the array to save RSS context IDs.
 657          */
 658         if (BNXT_CHIP_THOR(bp))
 659                 bp->max_ring_grps = BNXT_MAX_RSS_CTXTS_THOR;
 660
 661         rc = bnxt_alloc_all_hwrm_stat_ctxs(bp);
 662         if (rc) {
 663                 PMD_DRV_LOG(ERR, "HWRM stat ctx alloc failure rc: %x\n", rc);
 664                 goto err_out;
 665         }
 666
 667         rc = bnxt_alloc_hwrm_rings(bp);
 668         if (rc) {
 669                 PMD_DRV_LOG(ERR, "HWRM ring alloc failure rc: %x\n", rc);
 670                 goto err_out;
 671         }
 672
 673         rc = bnxt_alloc_all_hwrm_ring_grps(bp);
 674         if (rc) {
 675                 PMD_DRV_LOG(ERR, "HWRM ring grp alloc failure: %x\n", rc);
 676                 goto err_out;
 677         }
 678
 679         if (!(bp->vnic_cap_flags & BNXT_VNIC_CAP_COS_CLASSIFY))
 680                 goto skip_cosq_cfg;
 681
 682         for (j = 0, i = 0; i < BNXT_COS_QUEUE_COUNT; i++) {
 683                 if (bp->rx_cos_queue[i].id != 0xff) {
 684                         struct bnxt_vnic_info *vnic = &bp->vnic_info[j++];
 685
 686                         if (!vnic) {
 687                                 PMD_DRV_LOG(ERR,
 688                                             "Num pools more than FW profile\n");
 689                                 rc = -EINVAL;
 690                                 goto err_out;
 691                         }
 692                         vnic->cos_queue_id = bp->rx_cos_queue[i].id;
 693                         bp->rx_cosq_cnt++;
 694                 }
 695         }
 696
 697 skip_cosq_cfg:
 698         rc = bnxt_mq_rx_configure(bp);
 699         if (rc) {
 700                 PMD_DRV_LOG(ERR, "MQ mode configure failure rc: %x\n", rc);
 701                 goto err_out;
 702         }
 703
 704         /* VNIC configuration */
 705         for (i = 0; i < bp->nr_vnics; i++) {
 706                 rc = bnxt_setup_one_vnic(bp, i);
 707                 if (rc)
 708                         goto err_out;
 709         }
 710
 711         rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, &bp->vnic_info[0], 0, NULL);
 712         if (rc) {
 713                 PMD_DRV_LOG(ERR,
 714                         "HWRM cfa l2 rx mask failure rc: %x\n", rc);
 715                 goto err_out;
 716         }
 717
 718         /* check and configure queue intr-vector mapping */
 719         if ((rte_intr_cap_multiple(intr_handle) ||
 720              !RTE_ETH_DEV_SRIOV(bp->eth_dev).active) &&
 721             bp->eth_dev->data->dev_conf.intr_conf.rxq != 0) {
 722                 intr_vector = bp->eth_dev->data->nb_rx_queues;
 723                 PMD_DRV_LOG(DEBUG, "intr_vector = %d\n", intr_vector);
 724                 if (intr_vector > bp->rx_cp_nr_rings) {
 725                         PMD_DRV_LOG(ERR, "At most %d intr queues supported",
 726                                         bp->rx_cp_nr_rings);
 727                         return -ENOTSUP;
 728                 }
 729                 rc = rte_intr_efd_enable(intr_handle, intr_vector);
 730                 if (rc)
 731                         return rc;
 732         }
 733
 734         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
 735                 intr_handle->intr_vec =
 736                         rte_zmalloc("intr_vec",
 737                                     bp->eth_dev->data->nb_rx_queues *
 738                                     sizeof(int), 0);
 739                 if (intr_handle->intr_vec == NULL) {
 740                         PMD_DRV_LOG(ERR, "Failed to allocate %d rx_queues"
 741                                 " intr_vec", bp->eth_dev->data->nb_rx_queues);
 742                         rc = -ENOMEM;
 743                         goto err_disable;
 744                 }
 745                 PMD_DRV_LOG(DEBUG, "intr_handle->intr_vec = %p "
 746                         "intr_handle->nb_efd = %d intr_handle->max_intr = %d\n",
 747                          intr_handle->intr_vec, intr_handle->nb_efd,
 748                         intr_handle->max_intr);
 749                 for (queue_id = 0; queue_id < bp->eth_dev->data->nb_rx_queues;
 750                      queue_id++) {
 751                         intr_handle->intr_vec[queue_id] =
 752                                                         vec + BNXT_RX_VEC_START;
 753                         if (vec < base + intr_handle->nb_efd - 1)
 754                                 vec++;
 755                 }
 756         }
 757
 758         /* enable uio/vfio intr/eventfd mapping */
 759         rc = rte_intr_enable(intr_handle);
 760 #ifndef RTE_EXEC_ENV_FREEBSD
 761         /* In FreeBSD OS, nic_uio driver does not support interrupts */
 762         if (rc)
 763                 goto err_free;
 764 #endif
 765
 766         rc = bnxt_update_phy_setting(bp);
 767         if (rc)
 768                 goto err_free;
 769
 770         bp->mark_table = rte_zmalloc("bnxt_mark_table", BNXT_MARK_TABLE_SZ, 0);
 771         if (!bp->mark_table)
 772                 PMD_DRV_LOG(ERR, "Allocation of mark table failed\n");
 773
 774         return 0;
 775
 776 err_free:
 777         rte_free(intr_handle->intr_vec);
 778 err_disable:
 779         rte_intr_efd_disable(intr_handle);
 780 err_out:
 781         /* Some of the error status returned by FW may not be from errno.h */
 782         if (rc > 0)
 783                 rc = -EIO;
 784
 785         return rc;
 786 }
 787
 788 static int bnxt_shutdown_nic(struct bnxt *bp)
 789 {
 790         bnxt_free_all_hwrm_resources(bp);
 791         bnxt_free_all_filters(bp);
 792         bnxt_free_all_vnics(bp);
 793         return 0;
 794 }
 795
 796 /*
 797  * Device configuration and status function
 798  */
 799
 800 uint32_t bnxt_get_speed_capabilities(struct bnxt *bp)
 801 {
 802         uint32_t link_speed = bp->link_info->support_speeds;
 803         uint32_t speed_capa = 0;
 804
 805         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_100MB)
 806                 speed_capa |= ETH_LINK_SPEED_100M;
 807         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_100MBHD)
 808                 speed_capa |= ETH_LINK_SPEED_100M_HD;
 809         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_1GB)
 810                 speed_capa |= ETH_LINK_SPEED_1G;
 811         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_2_5GB)
 812                 speed_capa |= ETH_LINK_SPEED_2_5G;
 813         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_10GB)
 814                 speed_capa |= ETH_LINK_SPEED_10G;
 815         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_20GB)
 816                 speed_capa |= ETH_LINK_SPEED_20G;
 817         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_25GB)
 818                 speed_capa |= ETH_LINK_SPEED_25G;
 819         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_40GB)
 820                 speed_capa |= ETH_LINK_SPEED_40G;
 821         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_50GB)
 822                 speed_capa |= ETH_LINK_SPEED_50G;
 823         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_100GB)
 824                 speed_capa |= ETH_LINK_SPEED_100G;
 825         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_200GB)
 826                 speed_capa |= ETH_LINK_SPEED_200G;
 827
 828         if (bp->link_info->auto_mode ==
 829             HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_MODE_NONE)
 830                 speed_capa |= ETH_LINK_SPEED_FIXED;
 831         else
 832                 speed_capa |= ETH_LINK_SPEED_AUTONEG;
 833
 834         return speed_capa;
 835 }
 836
 837 static int bnxt_dev_info_get_op(struct rte_eth_dev *eth_dev,
 838                                 struct rte_eth_dev_info *dev_info)
 839 {
 840         struct rte_pci_device *pdev = RTE_DEV_TO_PCI(eth_dev->device);
 841         struct bnxt *bp = eth_dev->data->dev_private;
 842         uint16_t max_vnics, i, j, vpool, vrxq;
 843         unsigned int max_rx_rings;
 844         int rc;
 845
 846         rc = is_bnxt_in_error(bp);
 847         if (rc)
 848                 return rc;
 849
 850         /* MAC Specifics */
 851         dev_info->max_mac_addrs = bp->max_l2_ctx;
 852         dev_info->max_hash_mac_addrs = 0;
 853
 854         /* PF/VF specifics */
 855         if (BNXT_PF(bp))
 856                 dev_info->max_vfs = pdev->max_vfs;
 857
 858         max_rx_rings = BNXT_MAX_RINGS(bp);
 859         /* For the sake of symmetry, max_rx_queues = max_tx_queues */
 860         dev_info->max_rx_queues = max_rx_rings;
 861         dev_info->max_tx_queues = max_rx_rings;
 862         dev_info->reta_size = bnxt_rss_hash_tbl_size(bp);
 863         dev_info->hash_key_size = 40;
 864         max_vnics = bp->max_vnics;
 865
 866         /* MTU specifics */
 867         dev_info->min_mtu = RTE_ETHER_MIN_MTU;
 868         dev_info->max_mtu = BNXT_MAX_MTU;
 869
 870         /* Fast path specifics */
 871         dev_info->min_rx_bufsize = 1;
 872         dev_info->max_rx_pktlen = BNXT_MAX_PKT_LEN;
 873
 874         dev_info->rx_offload_capa = BNXT_DEV_RX_OFFLOAD_SUPPORT;
 875         if (bp->flags & BNXT_FLAG_PTP_SUPPORTED)
 876                 dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_TIMESTAMP;
 877         dev_info->tx_offload_capa = BNXT_DEV_TX_OFFLOAD_SUPPORT;
 878         dev_info->flow_type_rss_offloads = BNXT_ETH_RSS_SUPPORT;
 879
 880         dev_info->speed_capa = bnxt_get_speed_capabilities(bp);
 881
 882         /* *INDENT-OFF* */
 883         dev_info->default_rxconf = (struct rte_eth_rxconf) {
 884                 .rx_thresh = {
 885                         .pthresh = 8,
 886                         .hthresh = 8,
 887                         .wthresh = 0,
 888                 },
 889                 .rx_free_thresh = 32,
 890                 /* If no descriptors available, pkts are dropped by default */
 891                 .rx_drop_en = 1,
 892         };
 893
 894         dev_info->default_txconf = (struct rte_eth_txconf) {
 895                 .tx_thresh = {
 896                         .pthresh = 32,
 897                         .hthresh = 0,
 898                         .wthresh = 0,
 899                 },
 900                 .tx_free_thresh = 32,
 901                 .tx_rs_thresh = 32,
 902         };
 903         eth_dev->data->dev_conf.intr_conf.lsc = 1;
 904
 905         eth_dev->data->dev_conf.intr_conf.rxq = 1;
 906         dev_info->rx_desc_lim.nb_min = BNXT_MIN_RING_DESC;
 907         dev_info->rx_desc_lim.nb_max = BNXT_MAX_RX_RING_DESC;
 908         dev_info->tx_desc_lim.nb_min = BNXT_MIN_RING_DESC;
 909         dev_info->tx_desc_lim.nb_max = BNXT_MAX_TX_RING_DESC;
 910
 911         /* *INDENT-ON* */
 912
 913         /*
 914          * TODO: default_rxconf, default_txconf, rx_desc_lim, and tx_desc_lim
 915          *       need further investigation.
 916          */
 917
 918         /* VMDq resources */
 919         vpool = 64; /* ETH_64_POOLS */
 920         vrxq = 128; /* ETH_VMDQ_DCB_NUM_QUEUES */
 921         for (i = 0; i < 4; vpool >>= 1, i++) {
 922                 if (max_vnics > vpool) {
 923                         for (j = 0; j < 5; vrxq >>= 1, j++) {
 924                                 if (dev_info->max_rx_queues > vrxq) {
 925                                         if (vpool > vrxq)
 926                                                 vpool = vrxq;
 927                                         goto found;
 928                                 }
 929                         }
 930                         /* Not enough resources to support VMDq */
 931                         break;
 932                 }
 933         }
 934         /* Not enough resources to support VMDq */
 935         vpool = 0;
 936         vrxq = 0;
 937 found:
 938         dev_info->max_vmdq_pools = vpool;
 939         dev_info->vmdq_queue_num = vrxq;
 940
 941         dev_info->vmdq_pool_base = 0;
 942         dev_info->vmdq_queue_base = 0;
 943
 944         return 0;
 945 }
 946
 947 /* Configure the device based on the configuration provided */
 948 static int bnxt_dev_configure_op(struct rte_eth_dev *eth_dev)
 949 {
 950         struct bnxt *bp = eth_dev->data->dev_private;
 951         uint64_t rx_offloads = eth_dev->data->dev_conf.rxmode.offloads;
 952         int rc;
 953
 954         bp->rx_queues = (void *)eth_dev->data->rx_queues;
 955         bp->tx_queues = (void *)eth_dev->data->tx_queues;
 956         bp->tx_nr_rings = eth_dev->data->nb_tx_queues;
 957         bp->rx_nr_rings = eth_dev->data->nb_rx_queues;
 958
 959         rc = is_bnxt_in_error(bp);
 960         if (rc)
 961                 return rc;
 962
 963         if (BNXT_VF(bp) && (bp->flags & BNXT_FLAG_NEW_RM)) {
 964                 rc = bnxt_hwrm_check_vf_rings(bp);
 965                 if (rc) {
 966                         PMD_DRV_LOG(ERR, "HWRM insufficient resources\n");
 967                         return -ENOSPC;
 968                 }
 969
 970                 /* If a resource has already been allocated - in this case
 971                  * it is the async completion ring, free it. Reallocate it after
 972                  * resource reservation. This will ensure the resource counts
 973                  * are calculated correctly.
 974                  */
 975
 976                 pthread_mutex_lock(&bp->def_cp_lock);
 977
 978                 if (!BNXT_HAS_NQ(bp) && bp->async_cp_ring) {
 979                         bnxt_disable_int(bp);
 980                         bnxt_free_cp_ring(bp, bp->async_cp_ring);
 981                 }
 982
 983                 rc = bnxt_hwrm_func_reserve_vf_resc(bp, false);
 984                 if (rc) {
 985                         PMD_DRV_LOG(ERR, "HWRM resource alloc fail:%x\n", rc);
 986                         pthread_mutex_unlock(&bp->def_cp_lock);
 987                         return -ENOSPC;
 988                 }
 989
 990                 if (!BNXT_HAS_NQ(bp) && bp->async_cp_ring) {
 991                         rc = bnxt_alloc_async_cp_ring(bp);
 992                         if (rc) {
 993                                 pthread_mutex_unlock(&bp->def_cp_lock);
 994                                 return rc;
 995                         }
 996                         bnxt_enable_int(bp);
 997                 }
 998
 999                 pthread_mutex_unlock(&bp->def_cp_lock);
1000         } else {
1001                 /* legacy driver needs to get updated values */
1002                 rc = bnxt_hwrm_func_qcaps(bp);
1003                 if (rc) {
1004                         PMD_DRV_LOG(ERR, "hwrm func qcaps fail:%d\n", rc);
1005                         return rc;
1006                 }
1007         }
1008
1009         /* Inherit new configurations */
1010         if (eth_dev->data->nb_rx_queues > bp->max_rx_rings ||
1011             eth_dev->data->nb_tx_queues > bp->max_tx_rings ||
1012             eth_dev->data->nb_rx_queues + eth_dev->data->nb_tx_queues
1013                 + BNXT_NUM_ASYNC_CPR(bp) > bp->max_cp_rings ||
1014             eth_dev->data->nb_rx_queues + eth_dev->data->nb_tx_queues >
1015             bp->max_stat_ctx)
1016                 goto resource_error;
1017
1018         if (BNXT_HAS_RING_GRPS(bp) &&
1019             (uint32_t)(eth_dev->data->nb_rx_queues) > bp->max_ring_grps)
1020                 goto resource_error;
1021
1022         if (!(eth_dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_RSS) &&
1023             bp->max_vnics < eth_dev->data->nb_rx_queues)
1024                 goto resource_error;
1025
1026         bp->rx_cp_nr_rings = bp->rx_nr_rings;
1027         bp->tx_cp_nr_rings = bp->tx_nr_rings;
1028
1029         if (eth_dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG)
1030                 rx_offloads |= DEV_RX_OFFLOAD_RSS_HASH;
1031         eth_dev->data->dev_conf.rxmode.offloads = rx_offloads;
1032
1033         if (rx_offloads & DEV_RX_OFFLOAD_JUMBO_FRAME) {
1034                 eth_dev->data->mtu =
1035                         eth_dev->data->dev_conf.rxmode.max_rx_pkt_len -
1036                         RTE_ETHER_HDR_LEN - RTE_ETHER_CRC_LEN - VLAN_TAG_SIZE *
1037                         BNXT_NUM_VLANS;
1038                 bnxt_mtu_set_op(eth_dev, eth_dev->data->mtu);
1039         }
1040         return 0;
1041
1042 resource_error:
1043         PMD_DRV_LOG(ERR,
1044                     "Insufficient resources to support requested config\n");
1045         PMD_DRV_LOG(ERR,
1046                     "Num Queues Requested: Tx %d, Rx %d\n",
1047                     eth_dev->data->nb_tx_queues,
1048                     eth_dev->data->nb_rx_queues);
1049         PMD_DRV_LOG(ERR,
1050                     "MAX: TxQ %d, RxQ %d, CQ %d Stat %d, Grp %d, Vnic %d\n",
1051                     bp->max_tx_rings, bp->max_rx_rings, bp->max_cp_rings,
1052                     bp->max_stat_ctx, bp->max_ring_grps, bp->max_vnics);
1053         return -ENOSPC;
1054 }
1055
1056 void bnxt_print_link_info(struct rte_eth_dev *eth_dev)
1057 {
1058         struct rte_eth_link *link = &eth_dev->data->dev_link;
1059
1060         if (link->link_status)
1061                 PMD_DRV_LOG(INFO, "Port %d Link Up - speed %u Mbps - %s\n",
1062                         eth_dev->data->port_id,
1063                         (uint32_t)link->link_speed,
1064                         (link->link_duplex == ETH_LINK_FULL_DUPLEX) ?
1065                         ("full-duplex") : ("half-duplex\n"));
1066         else
1067                 PMD_DRV_LOG(INFO, "Port %d Link Down\n",
1068                         eth_dev->data->port_id);
1069 }
1070
1071 /*
1072  * Determine whether the current configuration requires support for scattered
1073  * receive; return 1 if scattered receive is required and 0 if not.
1074  */
1075 static int bnxt_scattered_rx(struct rte_eth_dev *eth_dev)
1076 {
1077         uint16_t buf_size;
1078         int i;
1079
1080         if (eth_dev->data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_SCATTER)
1081                 return 1;
1082
1083         for (i = 0; i < eth_dev->data->nb_rx_queues; i++) {
1084                 struct bnxt_rx_queue *rxq = eth_dev->data->rx_queues[i];
1085
1086                 buf_size = (uint16_t)(rte_pktmbuf_data_room_size(rxq->mb_pool) -
1087                                       RTE_PKTMBUF_HEADROOM);
1088                 if (eth_dev->data->dev_conf.rxmode.max_rx_pkt_len > buf_size)
1089                         return 1;
1090         }
1091         return 0;
1092 }
1093
1094 static eth_rx_burst_t
1095 bnxt_receive_function(struct rte_eth_dev *eth_dev)
1096 {
1097         struct bnxt *bp = eth_dev->data->dev_private;
1098
1099 #if defined(RTE_ARCH_X86) || defined(RTE_ARCH_ARM64)
1100 #ifndef RTE_LIBRTE_IEEE1588
1101         /*
1102          * Vector mode receive can be enabled only if scatter rx is not
1103          * in use and rx offloads are limited to VLAN stripping and
1104          * CRC stripping.
1105          */
1106         if (!eth_dev->data->scattered_rx &&
1107             !(eth_dev->data->dev_conf.rxmode.offloads &
1108               ~(DEV_RX_OFFLOAD_VLAN_STRIP |
1109                 DEV_RX_OFFLOAD_KEEP_CRC |
1110                 DEV_RX_OFFLOAD_JUMBO_FRAME |
1111                 DEV_RX_OFFLOAD_IPV4_CKSUM |
1112                 DEV_RX_OFFLOAD_UDP_CKSUM |
1113                 DEV_RX_OFFLOAD_TCP_CKSUM |
1114                 DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM |
1115                 DEV_RX_OFFLOAD_RSS_HASH |
1116                 DEV_RX_OFFLOAD_VLAN_FILTER)) &&
1117             !BNXT_TRUFLOW_EN(bp)) {
1118                 PMD_DRV_LOG(INFO, "Using vector mode receive for port %d\n",
1119                             eth_dev->data->port_id);
1120                 bp->flags |= BNXT_FLAG_RX_VECTOR_PKT_MODE;
1121                 return bnxt_recv_pkts_vec;
1122         }
1123         PMD_DRV_LOG(INFO, "Vector mode receive disabled for port %d\n",
1124                     eth_dev->data->port_id);
1125         PMD_DRV_LOG(INFO,
1126                     "Port %d scatter: %d rx offload: %" PRIX64 "\n",
1127                     eth_dev->data->port_id,
1128                     eth_dev->data->scattered_rx,
1129                     eth_dev->data->dev_conf.rxmode.offloads);
1130 #endif
1131 #endif
1132         bp->flags &= ~BNXT_FLAG_RX_VECTOR_PKT_MODE;
1133         return bnxt_recv_pkts;
1134 }
1135
1136 static eth_tx_burst_t
1137 bnxt_transmit_function(__rte_unused struct rte_eth_dev *eth_dev)
1138 {
1139 #if defined(RTE_ARCH_X86) || defined(RTE_ARCH_ARM64)
1140 #ifndef RTE_LIBRTE_IEEE1588
1141         struct bnxt *bp = eth_dev->data->dev_private;
1142
1143         /*
1144          * Vector mode transmit can be enabled only if not using scatter rx
1145          * or tx offloads.
1146          */
1147         if (!eth_dev->data->scattered_rx &&
1148             !eth_dev->data->dev_conf.txmode.offloads &&
1149             !BNXT_TRUFLOW_EN(bp)) {
1150                 PMD_DRV_LOG(INFO, "Using vector mode transmit for port %d\n",
1151                             eth_dev->data->port_id);
1152                 return bnxt_xmit_pkts_vec;
1153         }
1154         PMD_DRV_LOG(INFO, "Vector mode transmit disabled for port %d\n",
1155                     eth_dev->data->port_id);
1156         PMD_DRV_LOG(INFO,
1157                     "Port %d scatter: %d tx offload: %" PRIX64 "\n",
1158                     eth_dev->data->port_id,
1159                     eth_dev->data->scattered_rx,
1160                     eth_dev->data->dev_conf.txmode.offloads);
1161 #endif
1162 #endif
1163         return bnxt_xmit_pkts;
1164 }
1165
1166 static int bnxt_handle_if_change_status(struct bnxt *bp)
1167 {
1168         int rc;
1169
1170         /* Since fw has undergone a reset and lost all contexts,
1171          * set fatal flag to not issue hwrm during cleanup
1172          */
1173         bp->flags |= BNXT_FLAG_FATAL_ERROR;
1174         bnxt_uninit_resources(bp, true);
1175
1176         /* clear fatal flag so that re-init happens */
1177         bp->flags &= ~BNXT_FLAG_FATAL_ERROR;
1178         rc = bnxt_init_resources(bp, true);
1179
1180         bp->flags &= ~BNXT_FLAG_IF_CHANGE_HOT_FW_RESET_DONE;
1181
1182         return rc;
1183 }
1184
1185 static int bnxt_dev_start_op(struct rte_eth_dev *eth_dev)
1186 {
1187         struct bnxt *bp = eth_dev->data->dev_private;
1188         uint64_t rx_offloads = eth_dev->data->dev_conf.rxmode.offloads;
1189         int vlan_mask = 0;
1190         int rc, retry_cnt = BNXT_IF_CHANGE_RETRY_COUNT;
1191
1192         if (!eth_dev->data->nb_tx_queues || !eth_dev->data->nb_rx_queues) {
1193                 PMD_DRV_LOG(ERR, "Queues are not configured yet!\n");
1194                 return -EINVAL;
1195         }
1196
1197         if (bp->rx_cp_nr_rings > RTE_ETHDEV_QUEUE_STAT_CNTRS) {
1198                 PMD_DRV_LOG(ERR,
1199                         "RxQ cnt %d > CONFIG_RTE_ETHDEV_QUEUE_STAT_CNTRS %d\n",
1200                         bp->rx_cp_nr_rings, RTE_ETHDEV_QUEUE_STAT_CNTRS);
1201         }
1202
1203         do {
1204                 rc = bnxt_hwrm_if_change(bp, true);
1205                 if (rc == 0 || rc != -EAGAIN)
1206                         break;
1207
1208                 rte_delay_ms(BNXT_IF_CHANGE_RETRY_INTERVAL);
1209         } while (retry_cnt--);
1210
1211         if (rc)
1212                 return rc;
1213
1214         if (bp->flags & BNXT_FLAG_IF_CHANGE_HOT_FW_RESET_DONE) {
1215                 rc = bnxt_handle_if_change_status(bp);
1216                 if (rc)
1217                         return rc;
1218         }
1219
1220         bnxt_enable_int(bp);
1221
1222         rc = bnxt_init_chip(bp);
1223         if (rc)
1224                 goto error;
1225
1226         eth_dev->data->scattered_rx = bnxt_scattered_rx(eth_dev);
1227         eth_dev->data->dev_started = 1;
1228
1229         bnxt_link_update(eth_dev, 1, ETH_LINK_UP);
1230
1231         if (rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER)
1232                 vlan_mask |= ETH_VLAN_FILTER_MASK;
1233         if (rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
1234                 vlan_mask |= ETH_VLAN_STRIP_MASK;
1235         rc = bnxt_vlan_offload_set_op(eth_dev, vlan_mask);
1236         if (rc)
1237                 goto error;
1238
1239         eth_dev->rx_pkt_burst = bnxt_receive_function(eth_dev);
1240         eth_dev->tx_pkt_burst = bnxt_transmit_function(eth_dev);
1241
1242         pthread_mutex_lock(&bp->def_cp_lock);
1243         bnxt_schedule_fw_health_check(bp);
1244         pthread_mutex_unlock(&bp->def_cp_lock);
1245
1246         bnxt_ulp_init(bp);
1247
1248         return 0;
1249
1250 error:
1251         bnxt_shutdown_nic(bp);
1252         bnxt_free_tx_mbufs(bp);
1253         bnxt_free_rx_mbufs(bp);
1254         bnxt_hwrm_if_change(bp, false);
1255         eth_dev->data->dev_started = 0;
1256         return rc;
1257 }
1258
1259 static int bnxt_dev_set_link_up_op(struct rte_eth_dev *eth_dev)
1260 {
1261         struct bnxt *bp = eth_dev->data->dev_private;
1262         int rc = 0;
1263
1264         if (!bp->link_info->link_up)
1265                 rc = bnxt_set_hwrm_link_config(bp, true);
1266         if (!rc)
1267                 eth_dev->data->dev_link.link_status = 1;
1268
1269         bnxt_print_link_info(eth_dev);
1270         return rc;
1271 }
1272
1273 static int bnxt_dev_set_link_down_op(struct rte_eth_dev *eth_dev)
1274 {
1275         struct bnxt *bp = eth_dev->data->dev_private;
1276
1277         eth_dev->data->dev_link.link_status = 0;
1278         bnxt_set_hwrm_link_config(bp, false);
1279         bp->link_info->link_up = 0;
1280
1281         return 0;
1282 }
1283
1284 static void bnxt_free_switch_domain(struct bnxt *bp)
1285 {
1286         if (bp->switch_domain_id)
1287                 rte_eth_switch_domain_free(bp->switch_domain_id);
1288 }
1289
1290 /* Unload the driver, release resources */
1291 static void bnxt_dev_stop_op(struct rte_eth_dev *eth_dev)
1292 {
1293         struct bnxt *bp = eth_dev->data->dev_private;
1294         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1295         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1296
1297         eth_dev->data->dev_started = 0;
1298         /* Prevent crashes when queues are still in use */
1299         eth_dev->rx_pkt_burst = &bnxt_dummy_recv_pkts;
1300         eth_dev->tx_pkt_burst = &bnxt_dummy_xmit_pkts;
1301
1302         bnxt_disable_int(bp);
1303
1304         /* disable uio/vfio intr/eventfd mapping */
1305         rte_intr_disable(intr_handle);
1306
1307         bnxt_ulp_destroy_df_rules(bp, false);
1308         bnxt_ulp_deinit(bp);
1309
1310         bnxt_cancel_fw_health_check(bp);
1311
1312         bnxt_dev_set_link_down_op(eth_dev);
1313
1314         /* Wait for link to be reset and the async notification to process.
1315          * During reset recovery, there is no need to wait and
1316          * VF/NPAR functions do not have privilege to change PHY config.
1317          */
1318         if (!is_bnxt_in_error(bp) && BNXT_SINGLE_PF(bp))
1319                 bnxt_link_update(eth_dev, 1, ETH_LINK_DOWN);
1320
1321         /* Clean queue intr-vector mapping */
1322         rte_intr_efd_disable(intr_handle);
1323         if (intr_handle->intr_vec != NULL) {
1324                 rte_free(intr_handle->intr_vec);
1325                 intr_handle->intr_vec = NULL;
1326         }
1327
1328         bnxt_hwrm_port_clr_stats(bp);
1329         bnxt_free_tx_mbufs(bp);
1330         bnxt_free_rx_mbufs(bp);
1331         /* Process any remaining notifications in default completion queue */
1332         bnxt_int_handler(eth_dev);
1333         bnxt_shutdown_nic(bp);
1334         bnxt_hwrm_if_change(bp, false);
1335
1336         rte_free(bp->mark_table);
1337         bp->mark_table = NULL;
1338
1339         bp->flags &= ~BNXT_FLAG_RX_VECTOR_PKT_MODE;
1340         bp->rx_cosq_cnt = 0;
1341         /* All filters are deleted on a port stop. */
1342         if (BNXT_FLOW_XSTATS_EN(bp))
1343                 bp->flow_stat->flow_count = 0;
1344 }
1345
1346 static void bnxt_dev_close_op(struct rte_eth_dev *eth_dev)
1347 {
1348         struct bnxt *bp = eth_dev->data->dev_private;
1349
1350         /* cancel the recovery handler before remove dev */
1351         rte_eal_alarm_cancel(bnxt_dev_reset_and_resume, (void *)bp);
1352         rte_eal_alarm_cancel(bnxt_dev_recover, (void *)bp);
1353         bnxt_cancel_fc_thread(bp);
1354
1355         if (eth_dev->data->dev_started)
1356                 bnxt_dev_stop_op(eth_dev);
1357
1358         bnxt_free_switch_domain(bp);
1359
1360         bnxt_uninit_resources(bp, false);
1361
1362         bnxt_free_leds_info(bp);
1363         bnxt_free_cos_queues(bp);
1364         bnxt_free_link_info(bp);
1365         bnxt_free_pf_info(bp);
1366         bnxt_free_parent_info(bp);
1367
1368         eth_dev->dev_ops = NULL;
1369         eth_dev->rx_pkt_burst = NULL;
1370         eth_dev->tx_pkt_burst = NULL;
1371
1372         rte_memzone_free((const struct rte_memzone *)bp->tx_mem_zone);
1373         bp->tx_mem_zone = NULL;
1374         rte_memzone_free((const struct rte_memzone *)bp->rx_mem_zone);
1375         bp->rx_mem_zone = NULL;
1376
1377         bnxt_hwrm_free_vf_info(bp);
1378
1379         rte_free(bp->grp_info);
1380         bp->grp_info = NULL;
1381 }
1382
1383 static void bnxt_mac_addr_remove_op(struct rte_eth_dev *eth_dev,
1384                                     uint32_t index)
1385 {
1386         struct bnxt *bp = eth_dev->data->dev_private;
1387         uint64_t pool_mask = eth_dev->data->mac_pool_sel[index];
1388         struct bnxt_vnic_info *vnic;
1389         struct bnxt_filter_info *filter, *temp_filter;
1390         uint32_t i;
1391
1392         if (is_bnxt_in_error(bp))
1393                 return;
1394
1395         /*
1396          * Loop through all VNICs from the specified filter flow pools to
1397          * remove the corresponding MAC addr filter
1398          */
1399         for (i = 0; i < bp->nr_vnics; i++) {
1400                 if (!(pool_mask & (1ULL << i)))
1401                         continue;
1402
1403                 vnic = &bp->vnic_info[i];
1404                 filter = STAILQ_FIRST(&vnic->filter);
1405                 while (filter) {
1406                         temp_filter = STAILQ_NEXT(filter, next);
1407                         if (filter->mac_index == index) {
1408                                 STAILQ_REMOVE(&vnic->filter, filter,
1409                                                 bnxt_filter_info, next);
1410                                 bnxt_hwrm_clear_l2_filter(bp, filter);
1411                                 bnxt_free_filter(bp, filter);
1412                         }
1413                         filter = temp_filter;
1414                 }
1415         }
1416 }
1417
1418 static int bnxt_add_mac_filter(struct bnxt *bp, struct bnxt_vnic_info *vnic,
1419                                struct rte_ether_addr *mac_addr, uint32_t index,
1420                                uint32_t pool)
1421 {
1422         struct bnxt_filter_info *filter;
1423         int rc = 0;
1424
1425         /* Attach requested MAC address to the new l2_filter */
1426         STAILQ_FOREACH(filter, &vnic->filter, next) {
1427                 if (filter->mac_index == index) {
1428                         PMD_DRV_LOG(DEBUG,
1429                                     "MAC addr already existed for pool %d\n",
1430                                     pool);
1431                         return 0;
1432                 }
1433         }
1434
1435         filter = bnxt_alloc_filter(bp);
1436         if (!filter) {
1437                 PMD_DRV_LOG(ERR, "L2 filter alloc failed\n");
1438                 return -ENODEV;
1439         }
1440
1441         /* bnxt_alloc_filter copies default MAC to filter->l2_addr. So,
1442          * if the MAC that's been programmed now is a different one, then,
1443          * copy that addr to filter->l2_addr
1444          */
1445         if (mac_addr)
1446                 memcpy(filter->l2_addr, mac_addr, RTE_ETHER_ADDR_LEN);
1447         filter->flags |= HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_OUTERMOST;
1448
1449         rc = bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id, filter);
1450         if (!rc) {
1451                 filter->mac_index = index;
1452                 if (filter->mac_index == 0)
1453                         STAILQ_INSERT_HEAD(&vnic->filter, filter, next);
1454                 else
1455                         STAILQ_INSERT_TAIL(&vnic->filter, filter, next);
1456         } else {
1457                 bnxt_free_filter(bp, filter);
1458         }
1459
1460         return rc;
1461 }
1462
1463 static int bnxt_mac_addr_add_op(struct rte_eth_dev *eth_dev,
1464                                 struct rte_ether_addr *mac_addr,
1465                                 uint32_t index, uint32_t pool)
1466 {
1467         struct bnxt *bp = eth_dev->data->dev_private;
1468         struct bnxt_vnic_info *vnic = &bp->vnic_info[pool];
1469         int rc = 0;
1470
1471         rc = is_bnxt_in_error(bp);
1472         if (rc)
1473                 return rc;
1474
1475         if (BNXT_VF(bp) & !BNXT_VF_IS_TRUSTED(bp)) {
1476                 PMD_DRV_LOG(ERR, "Cannot add MAC address to a VF interface\n");
1477                 return -ENOTSUP;
1478         }
1479
1480         if (!vnic) {
1481                 PMD_DRV_LOG(ERR, "VNIC not found for pool %d!\n", pool);
1482                 return -EINVAL;
1483         }
1484
1485         /* Filter settings will get applied when port is started */
1486         if (!eth_dev->data->dev_started)
1487                 return 0;
1488
1489         rc = bnxt_add_mac_filter(bp, vnic, mac_addr, index, pool);
1490
1491         return rc;
1492 }
1493
1494 int bnxt_link_update(struct rte_eth_dev *eth_dev, int wait_to_complete,
1495                      bool exp_link_status)
1496 {
1497         int rc = 0;
1498         struct bnxt *bp = eth_dev->data->dev_private;
1499         struct rte_eth_link new;
1500         int cnt = exp_link_status ? BNXT_LINK_UP_WAIT_CNT :
1501                   BNXT_LINK_DOWN_WAIT_CNT;
1502
1503         rc = is_bnxt_in_error(bp);
1504         if (rc)
1505                 return rc;
1506
1507         memset(&new, 0, sizeof(new));
1508         do {
1509                 /* Retrieve link info from hardware */
1510                 rc = bnxt_get_hwrm_link_config(bp, &new);
1511                 if (rc) {
1512                         new.link_speed = ETH_LINK_SPEED_100M;
1513                         new.link_duplex = ETH_LINK_FULL_DUPLEX;
1514                         PMD_DRV_LOG(ERR,
1515                                 "Failed to retrieve link rc = 0x%x!\n", rc);
1516                         goto out;
1517                 }
1518
1519                 if (!wait_to_complete || new.link_status == exp_link_status)
1520                         break;
1521
1522                 rte_delay_ms(BNXT_LINK_WAIT_INTERVAL);
1523         } while (cnt--);
1524
1525 out:
1526         /* Timed out or success */
1527         if (new.link_status != eth_dev->data->dev_link.link_status ||
1528         new.link_speed != eth_dev->data->dev_link.link_speed) {
1529                 rte_eth_linkstatus_set(eth_dev, &new);
1530
1531                 rte_eth_dev_callback_process(eth_dev,
1532                                              RTE_ETH_EVENT_INTR_LSC,
1533                                              NULL);
1534
1535                 bnxt_print_link_info(eth_dev);
1536         }
1537
1538         return rc;
1539 }
1540
1541 int bnxt_link_update_op(struct rte_eth_dev *eth_dev,
1542                         int wait_to_complete)
1543 {
1544         return bnxt_link_update(eth_dev, wait_to_complete, ETH_LINK_UP);
1545 }
1546
1547 static int bnxt_promiscuous_enable_op(struct rte_eth_dev *eth_dev)
1548 {
1549         struct bnxt *bp = eth_dev->data->dev_private;
1550         struct bnxt_vnic_info *vnic;
1551         uint32_t old_flags;
1552         int rc;
1553
1554         rc = is_bnxt_in_error(bp);
1555         if (rc)
1556                 return rc;
1557
1558         /* Filter settings will get applied when port is started */
1559         if (!eth_dev->data->dev_started)
1560                 return 0;
1561
1562         if (bp->vnic_info == NULL)
1563                 return 0;
1564
1565         vnic = BNXT_GET_DEFAULT_VNIC(bp);
1566
1567         old_flags = vnic->flags;
1568         vnic->flags |= BNXT_VNIC_INFO_PROMISC;
1569         rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1570         if (rc != 0)
1571                 vnic->flags = old_flags;
1572
1573         return rc;
1574 }
1575
1576 static int bnxt_promiscuous_disable_op(struct rte_eth_dev *eth_dev)
1577 {
1578         struct bnxt *bp = eth_dev->data->dev_private;
1579         struct bnxt_vnic_info *vnic;
1580         uint32_t old_flags;
1581         int rc;
1582
1583         rc = is_bnxt_in_error(bp);
1584         if (rc)
1585                 return rc;
1586
1587         /* Filter settings will get applied when port is started */
1588         if (!eth_dev->data->dev_started)
1589                 return 0;
1590
1591         if (bp->vnic_info == NULL)
1592                 return 0;
1593
1594         vnic = BNXT_GET_DEFAULT_VNIC(bp);
1595
1596         old_flags = vnic->flags;
1597         vnic->flags &= ~BNXT_VNIC_INFO_PROMISC;
1598         rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1599         if (rc != 0)
1600                 vnic->flags = old_flags;
1601
1602         bnxt_ulp_create_df_rules(bp);
1603
1604         return rc;
1605 }
1606
1607 static int bnxt_allmulticast_enable_op(struct rte_eth_dev *eth_dev)
1608 {
1609         struct bnxt *bp = eth_dev->data->dev_private;
1610         struct bnxt_vnic_info *vnic;
1611         uint32_t old_flags;
1612         int rc;
1613
1614         rc = is_bnxt_in_error(bp);
1615         if (rc)
1616                 return rc;
1617
1618         /* Filter settings will get applied when port is started */
1619         if (!eth_dev->data->dev_started)
1620                 return 0;
1621
1622         if (bp->vnic_info == NULL)
1623                 return 0;
1624
1625         vnic = BNXT_GET_DEFAULT_VNIC(bp);
1626
1627         old_flags = vnic->flags;
1628         vnic->flags |= BNXT_VNIC_INFO_ALLMULTI;
1629         rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1630         if (rc != 0)
1631                 vnic->flags = old_flags;
1632
1633         return rc;
1634 }
1635
1636 static int bnxt_allmulticast_disable_op(struct rte_eth_dev *eth_dev)
1637 {
1638         struct bnxt *bp = eth_dev->data->dev_private;
1639         struct bnxt_vnic_info *vnic;
1640         uint32_t old_flags;
1641         int rc;
1642
1643         rc = is_bnxt_in_error(bp);
1644         if (rc)
1645                 return rc;
1646
1647         /* Filter settings will get applied when port is started */
1648         if (!eth_dev->data->dev_started)
1649                 return 0;
1650
1651         if (bp->vnic_info == NULL)
1652                 return 0;
1653
1654         vnic = BNXT_GET_DEFAULT_VNIC(bp);
1655
1656         old_flags = vnic->flags;
1657         vnic->flags &= ~BNXT_VNIC_INFO_ALLMULTI;
1658         rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1659         if (rc != 0)
1660                 vnic->flags = old_flags;
1661
1662         return rc;
1663 }
1664
1665 /* Return bnxt_rx_queue pointer corresponding to a given rxq. */
1666 static struct bnxt_rx_queue *bnxt_qid_to_rxq(struct bnxt *bp, uint16_t qid)
1667 {
1668         if (qid >= bp->rx_nr_rings)
1669                 return NULL;
1670
1671         return bp->eth_dev->data->rx_queues[qid];
1672 }
1673
1674 /* Return rxq corresponding to a given rss table ring/group ID. */
1675 static uint16_t bnxt_rss_to_qid(struct bnxt *bp, uint16_t fwr)
1676 {
1677         struct bnxt_rx_queue *rxq;
1678         unsigned int i;
1679
1680         if (!BNXT_HAS_RING_GRPS(bp)) {
1681                 for (i = 0; i < bp->rx_nr_rings; i++) {
1682                         rxq = bp->eth_dev->data->rx_queues[i];
1683                         if (rxq->rx_ring->rx_ring_struct->fw_ring_id == fwr)
1684                                 return rxq->index;
1685                 }
1686         } else {
1687                 for (i = 0; i < bp->rx_nr_rings; i++) {
1688                         if (bp->grp_info[i].fw_grp_id == fwr)
1689                                 return i;
1690                 }
1691         }
1692
1693         return INVALID_HW_RING_ID;
1694 }
1695
1696 static int bnxt_reta_update_op(struct rte_eth_dev *eth_dev,
1697                             struct rte_eth_rss_reta_entry64 *reta_conf,
1698                             uint16_t reta_size)
1699 {
1700         struct bnxt *bp = eth_dev->data->dev_private;
1701         struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
1702         struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp);
1703         uint16_t tbl_size = bnxt_rss_hash_tbl_size(bp);
1704         uint16_t idx, sft;
1705         int i, rc;
1706
1707         rc = is_bnxt_in_error(bp);
1708         if (rc)
1709                 return rc;
1710
1711         if (!vnic->rss_table)
1712                 return -EINVAL;
1713
1714         if (!(dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG))
1715                 return -EINVAL;
1716
1717         if (reta_size != tbl_size) {
1718                 PMD_DRV_LOG(ERR, "The configured hash table lookup size "
1719                         "(%d) must equal the size supported by the hardware "
1720                         "(%d)\n", reta_size, tbl_size);
1721                 return -EINVAL;
1722         }
1723
1724         for (i = 0; i < reta_size; i++) {
1725                 struct bnxt_rx_queue *rxq;
1726
1727                 idx = i / RTE_RETA_GROUP_SIZE;
1728                 sft = i % RTE_RETA_GROUP_SIZE;
1729
1730                 if (!(reta_conf[idx].mask & (1ULL << sft)))
1731                         continue;
1732
1733                 rxq = bnxt_qid_to_rxq(bp, reta_conf[idx].reta[sft]);
1734                 if (!rxq) {
1735                         PMD_DRV_LOG(ERR, "Invalid ring in reta_conf.\n");
1736                         return -EINVAL;
1737                 }
1738
1739                 if (BNXT_CHIP_THOR(bp)) {
1740                         vnic->rss_table[i * 2] =
1741                                 rxq->rx_ring->rx_ring_struct->fw_ring_id;
1742                         vnic->rss_table[i * 2 + 1] =
1743                                 rxq->cp_ring->cp_ring_struct->fw_ring_id;
1744                 } else {
1745                         vnic->rss_table[i] =
1746                             vnic->fw_grp_ids[reta_conf[idx].reta[sft]];
1747                 }
1748         }
1749
1750         bnxt_hwrm_vnic_rss_cfg(bp, vnic);
1751         return 0;
1752 }
1753
1754 static int bnxt_reta_query_op(struct rte_eth_dev *eth_dev,
1755                               struct rte_eth_rss_reta_entry64 *reta_conf,
1756                               uint16_t reta_size)
1757 {
1758         struct bnxt *bp = eth_dev->data->dev_private;
1759         struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp);
1760         uint16_t tbl_size = bnxt_rss_hash_tbl_size(bp);
1761         uint16_t idx, sft, i;
1762         int rc;
1763
1764         rc = is_bnxt_in_error(bp);
1765         if (rc)
1766                 return rc;
1767
1768         /* Retrieve from the default VNIC */
1769         if (!vnic)
1770                 return -EINVAL;
1771         if (!vnic->rss_table)
1772                 return -EINVAL;
1773
1774         if (reta_size != tbl_size) {
1775                 PMD_DRV_LOG(ERR, "The configured hash table lookup size "
1776                         "(%d) must equal the size supported by the hardware "
1777                         "(%d)\n", reta_size, tbl_size);
1778                 return -EINVAL;
1779         }
1780
1781         for (idx = 0, i = 0; i < reta_size; i++) {
1782                 idx = i / RTE_RETA_GROUP_SIZE;
1783                 sft = i % RTE_RETA_GROUP_SIZE;
1784
1785                 if (reta_conf[idx].mask & (1ULL << sft)) {
1786                         uint16_t qid;
1787
1788                         if (BNXT_CHIP_THOR(bp))
1789                                 qid = bnxt_rss_to_qid(bp,
1790                                                       vnic->rss_table[i * 2]);
1791                         else
1792                                 qid = bnxt_rss_to_qid(bp, vnic->rss_table[i]);
1793
1794                         if (qid == INVALID_HW_RING_ID) {
1795                                 PMD_DRV_LOG(ERR, "Inv. entry in rss table.\n");
1796                                 return -EINVAL;
1797                         }
1798                         reta_conf[idx].reta[sft] = qid;
1799                 }
1800         }
1801
1802         return 0;
1803 }
1804
1805 static int bnxt_rss_hash_update_op(struct rte_eth_dev *eth_dev,
1806                                    struct rte_eth_rss_conf *rss_conf)
1807 {
1808         struct bnxt *bp = eth_dev->data->dev_private;
1809         struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
1810         struct bnxt_vnic_info *vnic;
1811         int rc;
1812
1813         rc = is_bnxt_in_error(bp);
1814         if (rc)
1815                 return rc;
1816
1817         /*
1818          * If RSS enablement were different than dev_configure,
1819          * then return -EINVAL
1820          */
1821         if (dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG) {
1822                 if (!rss_conf->rss_hf)
1823                         PMD_DRV_LOG(ERR, "Hash type NONE\n");
1824         } else {
1825                 if (rss_conf->rss_hf & BNXT_ETH_RSS_SUPPORT)
1826                         return -EINVAL;
1827         }
1828
1829         bp->flags |= BNXT_FLAG_UPDATE_HASH;
1830         memcpy(&eth_dev->data->dev_conf.rx_adv_conf.rss_conf,
1831                rss_conf,
1832                sizeof(*rss_conf));
1833
1834         /* Update the default RSS VNIC(s) */
1835         vnic = BNXT_GET_DEFAULT_VNIC(bp);
1836         vnic->hash_type = bnxt_rte_to_hwrm_hash_types(rss_conf->rss_hf);
1837
1838         /*
1839          * If hashkey is not specified, use the previously configured
1840          * hashkey
1841          */
1842         if (!rss_conf->rss_key)
1843                 goto rss_config;
1844
1845         if (rss_conf->rss_key_len != HW_HASH_KEY_SIZE) {
1846                 PMD_DRV_LOG(ERR,
1847                             "Invalid hashkey length, should be 16 bytes\n");
1848                 return -EINVAL;
1849         }
1850         memcpy(vnic->rss_hash_key, rss_conf->rss_key, rss_conf->rss_key_len);
1851
1852 rss_config:
1853         bnxt_hwrm_vnic_rss_cfg(bp, vnic);
1854         return 0;
1855 }
1856
1857 static int bnxt_rss_hash_conf_get_op(struct rte_eth_dev *eth_dev,
1858                                      struct rte_eth_rss_conf *rss_conf)
1859 {
1860         struct bnxt *bp = eth_dev->data->dev_private;
1861         struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp);
1862         int len, rc;
1863         uint32_t hash_types;
1864
1865         rc = is_bnxt_in_error(bp);
1866         if (rc)
1867                 return rc;
1868
1869         /* RSS configuration is the same for all VNICs */
1870         if (vnic && vnic->rss_hash_key) {
1871                 if (rss_conf->rss_key) {
1872                         len = rss_conf->rss_key_len <= HW_HASH_KEY_SIZE ?
1873                               rss_conf->rss_key_len : HW_HASH_KEY_SIZE;
1874                         memcpy(rss_conf->rss_key, vnic->rss_hash_key, len);
1875                 }
1876
1877                 hash_types = vnic->hash_type;
1878                 rss_conf->rss_hf = 0;
1879                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV4) {
1880                         rss_conf->rss_hf |= ETH_RSS_IPV4;
1881                         hash_types &= ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV4;
1882                 }
1883                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV4) {
1884                         rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP;
1885                         hash_types &=
1886                                 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV4;
1887                 }
1888                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV4) {
1889                         rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
1890                         hash_types &=
1891                                 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV4;
1892                 }
1893                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6) {
1894                         rss_conf->rss_hf |= ETH_RSS_IPV6;
1895                         hash_types &= ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6;
1896                 }
1897                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV6) {
1898                         rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV6_TCP;
1899                         hash_types &=
1900                                 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV6;
1901                 }
1902                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV6) {
1903                         rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;
1904                         hash_types &=
1905                                 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV6;
1906                 }
1907                 if (hash_types) {
1908                         PMD_DRV_LOG(ERR,
1909                                 "Unknown RSS config from firmware (%08x), RSS disabled",
1910                                 vnic->hash_type);
1911                         return -ENOTSUP;
1912                 }
1913         } else {
1914                 rss_conf->rss_hf = 0;
1915         }
1916         return 0;
1917 }
1918
1919 static int bnxt_flow_ctrl_get_op(struct rte_eth_dev *dev,
1920                                struct rte_eth_fc_conf *fc_conf)
1921 {
1922         struct bnxt *bp = dev->data->dev_private;
1923         struct rte_eth_link link_info;
1924         int rc;
1925
1926         rc = is_bnxt_in_error(bp);
1927         if (rc)
1928                 return rc;
1929
1930         rc = bnxt_get_hwrm_link_config(bp, &link_info);
1931         if (rc)
1932                 return rc;
1933
1934         memset(fc_conf, 0, sizeof(*fc_conf));
1935         if (bp->link_info->auto_pause)
1936                 fc_conf->autoneg = 1;
1937         switch (bp->link_info->pause) {
1938         case 0:
1939                 fc_conf->mode = RTE_FC_NONE;
1940                 break;
1941         case HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_TX:
1942                 fc_conf->mode = RTE_FC_TX_PAUSE;
1943                 break;
1944         case HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_RX:
1945                 fc_conf->mode = RTE_FC_RX_PAUSE;
1946                 break;
1947         case (HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_TX |
1948                         HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_RX):
1949                 fc_conf->mode = RTE_FC_FULL;
1950                 break;
1951         }
1952         return 0;
1953 }
1954
1955 static int bnxt_flow_ctrl_set_op(struct rte_eth_dev *dev,
1956                                struct rte_eth_fc_conf *fc_conf)
1957 {
1958         struct bnxt *bp = dev->data->dev_private;
1959         int rc;
1960
1961         rc = is_bnxt_in_error(bp);
1962         if (rc)
1963                 return rc;
1964
1965         if (!BNXT_SINGLE_PF(bp) || BNXT_VF(bp)) {
1966                 PMD_DRV_LOG(ERR, "Flow Control Settings cannot be modified\n");
1967                 return -ENOTSUP;
1968         }
1969
1970         switch (fc_conf->mode) {
1971         case RTE_FC_NONE:
1972                 bp->link_info->auto_pause = 0;
1973                 bp->link_info->force_pause = 0;
1974                 break;
1975         case RTE_FC_RX_PAUSE:
1976                 if (fc_conf->autoneg) {
1977                         bp->link_info->auto_pause =
1978                                         HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_RX;
1979                         bp->link_info->force_pause = 0;
1980                 } else {
1981                         bp->link_info->auto_pause = 0;
1982                         bp->link_info->force_pause =
1983                                         HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_RX;
1984                 }
1985                 break;
1986         case RTE_FC_TX_PAUSE:
1987                 if (fc_conf->autoneg) {
1988                         bp->link_info->auto_pause =
1989                                         HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_TX;
1990                         bp->link_info->force_pause = 0;
1991                 } else {
1992                         bp->link_info->auto_pause = 0;
1993                         bp->link_info->force_pause =
1994                                         HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_TX;
1995                 }
1996                 break;
1997         case RTE_FC_FULL:
1998                 if (fc_conf->autoneg) {
1999                         bp->link_info->auto_pause =
2000                                         HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_TX |
2001                                         HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_RX;
2002                         bp->link_info->force_pause = 0;
2003                 } else {
2004                         bp->link_info->auto_pause = 0;
2005                         bp->link_info->force_pause =
2006                                         HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_TX |
2007                                         HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_RX;
2008                 }
2009                 break;
2010         }
2011         return bnxt_set_hwrm_link_config(bp, true);
2012 }
2013
2014 /* Add UDP tunneling port */
2015 static int
2016 bnxt_udp_tunnel_port_add_op(struct rte_eth_dev *eth_dev,
2017                          struct rte_eth_udp_tunnel *udp_tunnel)
2018 {
2019         struct bnxt *bp = eth_dev->data->dev_private;
2020         uint16_t tunnel_type = 0;
2021         int rc = 0;
2022
2023         rc = is_bnxt_in_error(bp);
2024         if (rc)
2025                 return rc;
2026
2027         switch (udp_tunnel->prot_type) {
2028         case RTE_TUNNEL_TYPE_VXLAN:
2029                 if (bp->vxlan_port_cnt) {
2030                         PMD_DRV_LOG(ERR, "Tunnel Port %d already programmed\n",
2031                                 udp_tunnel->udp_port);
2032                         if (bp->vxlan_port != udp_tunnel->udp_port) {
2033                                 PMD_DRV_LOG(ERR, "Only one port allowed\n");
2034                                 return -ENOSPC;
2035                         }
2036                         bp->vxlan_port_cnt++;
2037                         return 0;
2038                 }
2039                 tunnel_type =
2040                         HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_VXLAN;
2041                 bp->vxlan_port_cnt++;
2042                 break;
2043         case RTE_TUNNEL_TYPE_GENEVE:
2044                 if (bp->geneve_port_cnt) {
2045                         PMD_DRV_LOG(ERR, "Tunnel Port %d already programmed\n",
2046                                 udp_tunnel->udp_port);
2047                         if (bp->geneve_port != udp_tunnel->udp_port) {
2048                                 PMD_DRV_LOG(ERR, "Only one port allowed\n");
2049                                 return -ENOSPC;
2050                         }
2051                         bp->geneve_port_cnt++;
2052                         return 0;
2053                 }
2054                 tunnel_type =
2055                         HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_GENEVE;
2056                 bp->geneve_port_cnt++;
2057                 break;
2058         default:
2059                 PMD_DRV_LOG(ERR, "Tunnel type is not supported\n");
2060                 return -ENOTSUP;
2061         }
2062         rc = bnxt_hwrm_tunnel_dst_port_alloc(bp, udp_tunnel->udp_port,
2063                                              tunnel_type);
2064         return rc;
2065 }
2066
2067 static int
2068 bnxt_udp_tunnel_port_del_op(struct rte_eth_dev *eth_dev,
2069                          struct rte_eth_udp_tunnel *udp_tunnel)
2070 {
2071         struct bnxt *bp = eth_dev->data->dev_private;
2072         uint16_t tunnel_type = 0;
2073         uint16_t port = 0;
2074         int rc = 0;
2075
2076         rc = is_bnxt_in_error(bp);
2077         if (rc)
2078                 return rc;
2079
2080         switch (udp_tunnel->prot_type) {
2081         case RTE_TUNNEL_TYPE_VXLAN:
2082                 if (!bp->vxlan_port_cnt) {
2083                         PMD_DRV_LOG(ERR, "No Tunnel port configured yet\n");
2084                         return -EINVAL;
2085                 }
2086                 if (bp->vxlan_port != udp_tunnel->udp_port) {
2087                         PMD_DRV_LOG(ERR, "Req Port: %d. Configured port: %d\n",
2088                                 udp_tunnel->udp_port, bp->vxlan_port);
2089                         return -EINVAL;
2090                 }
2091                 if (--bp->vxlan_port_cnt)
2092                         return 0;
2093
2094                 tunnel_type =
2095                         HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN;
2096                 port = bp->vxlan_fw_dst_port_id;
2097                 break;
2098         case RTE_TUNNEL_TYPE_GENEVE:
2099                 if (!bp->geneve_port_cnt) {
2100                         PMD_DRV_LOG(ERR, "No Tunnel port configured yet\n");
2101                         return -EINVAL;
2102                 }
2103                 if (bp->geneve_port != udp_tunnel->udp_port) {
2104                         PMD_DRV_LOG(ERR, "Req Port: %d. Configured port: %d\n",
2105                                 udp_tunnel->udp_port, bp->geneve_port);
2106                         return -EINVAL;
2107                 }
2108                 if (--bp->geneve_port_cnt)
2109                         return 0;
2110
2111                 tunnel_type =
2112                         HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_GENEVE;
2113                 port = bp->geneve_fw_dst_port_id;
2114                 break;
2115         default:
2116                 PMD_DRV_LOG(ERR, "Tunnel type is not supported\n");
2117                 return -ENOTSUP;
2118         }
2119
2120         rc = bnxt_hwrm_tunnel_dst_port_free(bp, port, tunnel_type);
2121         if (!rc) {
2122                 if (tunnel_type ==
2123                     HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN)
2124                         bp->vxlan_port = 0;
2125                 if (tunnel_type ==
2126                     HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_GENEVE)
2127                         bp->geneve_port = 0;
2128         }
2129         return rc;
2130 }
2131
2132 static int bnxt_del_vlan_filter(struct bnxt *bp, uint16_t vlan_id)
2133 {
2134         struct bnxt_filter_info *filter;
2135         struct bnxt_vnic_info *vnic;
2136         int rc = 0;
2137         uint32_t chk = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN;
2138
2139         vnic = BNXT_GET_DEFAULT_VNIC(bp);
2140         filter = STAILQ_FIRST(&vnic->filter);
2141         while (filter) {
2142                 /* Search for this matching MAC+VLAN filter */
2143                 if (bnxt_vlan_filter_exists(bp, filter, chk, vlan_id)) {
2144                         /* Delete the filter */
2145                         rc = bnxt_hwrm_clear_l2_filter(bp, filter);
2146                         if (rc)
2147                                 return rc;
2148                         STAILQ_REMOVE(&vnic->filter, filter,
2149                                       bnxt_filter_info, next);
2150                         bnxt_free_filter(bp, filter);
2151                         PMD_DRV_LOG(INFO,
2152                                     "Deleted vlan filter for %d\n",
2153                                     vlan_id);
2154                         return 0;
2155                 }
2156                 filter = STAILQ_NEXT(filter, next);
2157         }
2158         return -ENOENT;
2159 }
2160
2161 static int bnxt_add_vlan_filter(struct bnxt *bp, uint16_t vlan_id)
2162 {
2163         struct bnxt_filter_info *filter;
2164         struct bnxt_vnic_info *vnic;
2165         int rc = 0;
2166         uint32_t en = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN |
2167                 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN_MASK;
2168         uint32_t chk = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN;
2169
2170         /* Implementation notes on the use of VNIC in this command:
2171          *
2172          * By default, these filters belong to default vnic for the function.
2173          * Once these filters are set up, only destination VNIC can be modified.
2174          * If the destination VNIC is not specified in this command,
2175          * then the HWRM shall only create an l2 context id.
2176          */
2177
2178         vnic = BNXT_GET_DEFAULT_VNIC(bp);
2179         filter = STAILQ_FIRST(&vnic->filter);
2180         /* Check if the VLAN has already been added */
2181         while (filter) {
2182                 if (bnxt_vlan_filter_exists(bp, filter, chk, vlan_id))
2183                         return -EEXIST;
2184
2185                 filter = STAILQ_NEXT(filter, next);
2186         }
2187
2188         /* No match found. Alloc a fresh filter and issue the L2_FILTER_ALLOC
2189          * command to create MAC+VLAN filter with the right flags, enables set.
2190          */
2191         filter = bnxt_alloc_filter(bp);
2192         if (!filter) {
2193                 PMD_DRV_LOG(ERR,
2194                             "MAC/VLAN filter alloc failed\n");
2195                 return -ENOMEM;
2196         }
2197         /* MAC + VLAN ID filter */
2198         /* If l2_ivlan == 0 and l2_ivlan_mask != 0, only
2199          * untagged packets are received
2200          *
2201          * If l2_ivlan != 0 and l2_ivlan_mask != 0, untagged
2202          * packets and only the programmed vlan's packets are received
2203          */
2204         filter->l2_ivlan = vlan_id;
2205         filter->l2_ivlan_mask = 0x0FFF;
2206         filter->enables |= en;
2207         filter->flags |= HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_OUTERMOST;
2208
2209         rc = bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id, filter);
2210         if (rc) {
2211                 /* Free the newly allocated filter as we were
2212                  * not able to create the filter in hardware.
2213                  */
2214                 bnxt_free_filter(bp, filter);
2215                 return rc;
2216         }
2217
2218         filter->mac_index = 0;
2219         /* Add this new filter to the list */
2220         if (vlan_id == 0)
2221                 STAILQ_INSERT_HEAD(&vnic->filter, filter, next);
2222         else
2223                 STAILQ_INSERT_TAIL(&vnic->filter, filter, next);
2224
2225         PMD_DRV_LOG(INFO,
2226                     "Added Vlan filter for %d\n", vlan_id);
2227         return rc;
2228 }
2229
2230 static int bnxt_vlan_filter_set_op(struct rte_eth_dev *eth_dev,
2231                 uint16_t vlan_id, int on)
2232 {
2233         struct bnxt *bp = eth_dev->data->dev_private;
2234         int rc;
2235
2236         rc = is_bnxt_in_error(bp);
2237         if (rc)
2238                 return rc;
2239
2240         if (!eth_dev->data->dev_started) {
2241                 PMD_DRV_LOG(ERR, "port must be started before setting vlan\n");
2242                 return -EINVAL;
2243         }
2244
2245         /* These operations apply to ALL existing MAC/VLAN filters */
2246         if (on)
2247                 return bnxt_add_vlan_filter(bp, vlan_id);
2248         else
2249                 return bnxt_del_vlan_filter(bp, vlan_id);
2250 }
2251
2252 static int bnxt_del_dflt_mac_filter(struct bnxt *bp,
2253                                     struct bnxt_vnic_info *vnic)
2254 {
2255         struct bnxt_filter_info *filter;
2256         int rc;
2257
2258         filter = STAILQ_FIRST(&vnic->filter);
2259         while (filter) {
2260                 if (filter->mac_index == 0 &&
2261                     !memcmp(filter->l2_addr, bp->mac_addr,
2262                             RTE_ETHER_ADDR_LEN)) {
2263                         rc = bnxt_hwrm_clear_l2_filter(bp, filter);
2264                         if (!rc) {
2265                                 STAILQ_REMOVE(&vnic->filter, filter,
2266                                               bnxt_filter_info, next);
2267                                 bnxt_free_filter(bp, filter);
2268                         }
2269                         return rc;
2270                 }
2271                 filter = STAILQ_NEXT(filter, next);
2272         }
2273         return 0;
2274 }
2275
2276 static int
2277 bnxt_config_vlan_hw_filter(struct bnxt *bp, uint64_t rx_offloads)
2278 {
2279         struct bnxt_vnic_info *vnic;
2280         unsigned int i;
2281         int rc;
2282
2283         vnic = BNXT_GET_DEFAULT_VNIC(bp);
2284         if (!(rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER)) {
2285                 /* Remove any VLAN filters programmed */
2286                 for (i = 0; i < RTE_ETHER_MAX_VLAN_ID; i++)
2287                         bnxt_del_vlan_filter(bp, i);
2288
2289                 rc = bnxt_add_mac_filter(bp, vnic, NULL, 0, 0);
2290                 if (rc)
2291                         return rc;
2292         } else {
2293                 /* Default filter will allow packets that match the
2294                  * dest mac. So, it has to be deleted, otherwise, we
2295                  * will endup receiving vlan packets for which the
2296                  * filter is not programmed, when hw-vlan-filter
2297                  * configuration is ON
2298                  */
2299                 bnxt_del_dflt_mac_filter(bp, vnic);
2300                 /* This filter will allow only untagged packets */
2301                 bnxt_add_vlan_filter(bp, 0);
2302         }
2303         PMD_DRV_LOG(DEBUG, "VLAN Filtering: %d\n",
2304                     !!(rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER));
2305
2306         return 0;
2307 }
2308
2309 static int bnxt_free_one_vnic(struct bnxt *bp, uint16_t vnic_id)
2310 {
2311         struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id];
2312         unsigned int i;
2313         int rc;
2314
2315         /* Destroy vnic filters and vnic */
2316         if (bp->eth_dev->data->dev_conf.rxmode.offloads &
2317             DEV_RX_OFFLOAD_VLAN_FILTER) {
2318                 for (i = 0; i < RTE_ETHER_MAX_VLAN_ID; i++)
2319                         bnxt_del_vlan_filter(bp, i);
2320         }
2321         bnxt_del_dflt_mac_filter(bp, vnic);
2322
2323         rc = bnxt_hwrm_vnic_free(bp, vnic);
2324         if (rc)
2325                 return rc;
2326
2327         rte_free(vnic->fw_grp_ids);
2328         vnic->fw_grp_ids = NULL;
2329
2330         vnic->rx_queue_cnt = 0;
2331
2332         return 0;
2333 }
2334
2335 static int
2336 bnxt_config_vlan_hw_stripping(struct bnxt *bp, uint64_t rx_offloads)
2337 {
2338         struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp);
2339         int rc;
2340
2341         /* Destroy, recreate and reconfigure the default vnic */
2342         rc = bnxt_free_one_vnic(bp, 0);
2343         if (rc)
2344                 return rc;
2345
2346         /* default vnic 0 */
2347         rc = bnxt_setup_one_vnic(bp, 0);
2348         if (rc)
2349                 return rc;
2350
2351         if (bp->eth_dev->data->dev_conf.rxmode.offloads &
2352             DEV_RX_OFFLOAD_VLAN_FILTER) {
2353                 rc = bnxt_add_vlan_filter(bp, 0);
2354                 if (rc)
2355                         return rc;
2356                 rc = bnxt_restore_vlan_filters(bp);
2357                 if (rc)
2358                         return rc;
2359         } else {
2360                 rc = bnxt_add_mac_filter(bp, vnic, NULL, 0, 0);
2361                 if (rc)
2362                         return rc;
2363         }
2364
2365         rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
2366         if (rc)
2367                 return rc;
2368
2369         PMD_DRV_LOG(DEBUG, "VLAN Strip Offload: %d\n",
2370                     !!(rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP));
2371
2372         return rc;
2373 }
2374
2375 static int
2376 bnxt_vlan_offload_set_op(struct rte_eth_dev *dev, int mask)
2377 {
2378         uint64_t rx_offloads = dev->data->dev_conf.rxmode.offloads;
2379         struct bnxt *bp = dev->data->dev_private;
2380         int rc;
2381
2382         rc = is_bnxt_in_error(bp);
2383         if (rc)
2384                 return rc;
2385
2386         /* Filter settings will get applied when port is started */
2387         if (!dev->data->dev_started)
2388                 return 0;
2389
2390         if (mask & ETH_VLAN_FILTER_MASK) {
2391                 /* Enable or disable VLAN filtering */
2392                 rc = bnxt_config_vlan_hw_filter(bp, rx_offloads);
2393                 if (rc)
2394                         return rc;
2395         }
2396
2397         if (mask & ETH_VLAN_STRIP_MASK) {
2398                 /* Enable or disable VLAN stripping */
2399                 rc = bnxt_config_vlan_hw_stripping(bp, rx_offloads);
2400                 if (rc)
2401                         return rc;
2402         }
2403
2404         if (mask & ETH_VLAN_EXTEND_MASK) {
2405                 if (rx_offloads & DEV_RX_OFFLOAD_VLAN_EXTEND)
2406                         PMD_DRV_LOG(DEBUG, "Extend VLAN supported\n");
2407                 else
2408                         PMD_DRV_LOG(INFO, "Extend VLAN unsupported\n");
2409         }
2410
2411         return 0;
2412 }
2413
2414 static int
2415 bnxt_vlan_tpid_set_op(struct rte_eth_dev *dev, enum rte_vlan_type vlan_type,
2416                       uint16_t tpid)
2417 {
2418         struct bnxt *bp = dev->data->dev_private;
2419         int qinq = dev->data->dev_conf.rxmode.offloads &
2420                    DEV_RX_OFFLOAD_VLAN_EXTEND;
2421
2422         if (vlan_type != ETH_VLAN_TYPE_INNER &&
2423             vlan_type != ETH_VLAN_TYPE_OUTER) {
2424                 PMD_DRV_LOG(ERR,
2425                             "Unsupported vlan type.");
2426                 return -EINVAL;
2427         }
2428         if (!qinq) {
2429                 PMD_DRV_LOG(ERR,
2430                             "QinQ not enabled. Needs to be ON as we can "
2431                             "accelerate only outer vlan\n");
2432                 return -EINVAL;
2433         }
2434
2435         if (vlan_type == ETH_VLAN_TYPE_OUTER) {
2436                 switch (tpid) {
2437                 case RTE_ETHER_TYPE_QINQ:
2438                         bp->outer_tpid_bd =
2439                                 TX_BD_LONG_CFA_META_VLAN_TPID_TPID88A8;
2440                                 break;
2441                 case RTE_ETHER_TYPE_VLAN:
2442                         bp->outer_tpid_bd =
2443                                 TX_BD_LONG_CFA_META_VLAN_TPID_TPID8100;
2444                                 break;
2445                 case RTE_ETHER_TYPE_QINQ1:
2446                         bp->outer_tpid_bd =
2447                                 TX_BD_LONG_CFA_META_VLAN_TPID_TPID9100;
2448                                 break;
2449                 case RTE_ETHER_TYPE_QINQ2:
2450                         bp->outer_tpid_bd =
2451                                 TX_BD_LONG_CFA_META_VLAN_TPID_TPID9200;
2452                                 break;
2453                 case RTE_ETHER_TYPE_QINQ3:
2454                         bp->outer_tpid_bd =
2455                                  TX_BD_LONG_CFA_META_VLAN_TPID_TPID9300;
2456                                 break;
2457                 default:
2458                         PMD_DRV_LOG(ERR, "Invalid TPID: %x\n", tpid);
2459                         return -EINVAL;
2460                 }
2461                 bp->outer_tpid_bd |= tpid;
2462                 PMD_DRV_LOG(INFO, "outer_tpid_bd = %x\n", bp->outer_tpid_bd);
2463         } else if (vlan_type == ETH_VLAN_TYPE_INNER) {
2464                 PMD_DRV_LOG(ERR,
2465                             "Can accelerate only outer vlan in QinQ\n");
2466                 return -EINVAL;
2467         }
2468
2469         return 0;
2470 }
2471
2472 static int
2473 bnxt_set_default_mac_addr_op(struct rte_eth_dev *dev,
2474                              struct rte_ether_addr *addr)
2475 {
2476         struct bnxt *bp = dev->data->dev_private;
2477         /* Default Filter is tied to VNIC 0 */
2478         struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp);
2479         int rc;
2480
2481         rc = is_bnxt_in_error(bp);
2482         if (rc)
2483                 return rc;
2484
2485         if (BNXT_VF(bp) && !BNXT_VF_IS_TRUSTED(bp))
2486                 return -EPERM;
2487
2488         if (rte_is_zero_ether_addr(addr))
2489                 return -EINVAL;
2490
2491         /* Filter settings will get applied when port is started */
2492         if (!dev->data->dev_started)
2493                 return 0;
2494
2495         /* Check if the requested MAC is already added */
2496         if (memcmp(addr, bp->mac_addr, RTE_ETHER_ADDR_LEN) == 0)
2497                 return 0;
2498
2499         /* Destroy filter and re-create it */
2500         bnxt_del_dflt_mac_filter(bp, vnic);
2501
2502         memcpy(bp->mac_addr, addr, RTE_ETHER_ADDR_LEN);
2503         if (dev->data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_VLAN_FILTER) {
2504                 /* This filter will allow only untagged packets */
2505                 rc = bnxt_add_vlan_filter(bp, 0);
2506         } else {
2507                 rc = bnxt_add_mac_filter(bp, vnic, addr, 0, 0);
2508         }
2509
2510         PMD_DRV_LOG(DEBUG, "Set MAC addr\n");
2511         return rc;
2512 }
2513
2514 static int
2515 bnxt_dev_set_mc_addr_list_op(struct rte_eth_dev *eth_dev,
2516                           struct rte_ether_addr *mc_addr_set,
2517                           uint32_t nb_mc_addr)
2518 {
2519         struct bnxt *bp = eth_dev->data->dev_private;
2520         char *mc_addr_list = (char *)mc_addr_set;
2521         struct bnxt_vnic_info *vnic;
2522         uint32_t off = 0, i = 0;
2523         int rc;
2524
2525         rc = is_bnxt_in_error(bp);
2526         if (rc)
2527                 return rc;
2528
2529         vnic = BNXT_GET_DEFAULT_VNIC(bp);
2530
2531         if (nb_mc_addr > BNXT_MAX_MC_ADDRS) {
2532                 vnic->flags |= BNXT_VNIC_INFO_ALLMULTI;
2533                 goto allmulti;
2534         }
2535
2536         /* TODO Check for Duplicate mcast addresses */
2537         vnic->flags &= ~BNXT_VNIC_INFO_ALLMULTI;
2538         for (i = 0; i < nb_mc_addr; i++) {
2539                 memcpy(vnic->mc_list + off, &mc_addr_list[i],
2540                         RTE_ETHER_ADDR_LEN);
2541                 off += RTE_ETHER_ADDR_LEN;
2542         }
2543
2544         vnic->mc_addr_cnt = i;
2545         if (vnic->mc_addr_cnt)
2546                 vnic->flags |= BNXT_VNIC_INFO_MCAST;
2547         else
2548                 vnic->flags &= ~BNXT_VNIC_INFO_MCAST;
2549
2550 allmulti:
2551         return bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
2552 }
2553
2554 static int
2555 bnxt_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size)
2556 {
2557         struct bnxt *bp = dev->data->dev_private;
2558         uint8_t fw_major = (bp->fw_ver >> 24) & 0xff;
2559         uint8_t fw_minor = (bp->fw_ver >> 16) & 0xff;
2560         uint8_t fw_updt = (bp->fw_ver >> 8) & 0xff;
2561         uint8_t fw_rsvd = bp->fw_ver & 0xff;
2562         int ret;
2563
2564         ret = snprintf(fw_version, fw_size, "%d.%d.%d.%d",
2565                         fw_major, fw_minor, fw_updt, fw_rsvd);
2566
2567         ret += 1; /* add the size of '\0' */
2568         if (fw_size < (uint32_t)ret)
2569                 return ret;
2570         else
2571                 return 0;
2572 }
2573
2574 static void
2575 bnxt_rxq_info_get_op(struct rte_eth_dev *dev, uint16_t queue_id,
2576         struct rte_eth_rxq_info *qinfo)
2577 {
2578         struct bnxt *bp = dev->data->dev_private;
2579         struct bnxt_rx_queue *rxq;
2580
2581         if (is_bnxt_in_error(bp))
2582                 return;
2583
2584         rxq = dev->data->rx_queues[queue_id];
2585
2586         qinfo->mp = rxq->mb_pool;
2587         qinfo->scattered_rx = dev->data->scattered_rx;
2588         qinfo->nb_desc = rxq->nb_rx_desc;
2589
2590         qinfo->conf.rx_free_thresh = rxq->rx_free_thresh;
2591         qinfo->conf.rx_drop_en = 0;
2592         qinfo->conf.rx_deferred_start = rxq->rx_deferred_start;
2593 }
2594
2595 static void
2596 bnxt_txq_info_get_op(struct rte_eth_dev *dev, uint16_t queue_id,
2597         struct rte_eth_txq_info *qinfo)
2598 {
2599         struct bnxt *bp = dev->data->dev_private;
2600         struct bnxt_tx_queue *txq;
2601
2602         if (is_bnxt_in_error(bp))
2603                 return;
2604
2605         txq = dev->data->tx_queues[queue_id];
2606
2607         qinfo->nb_desc = txq->nb_tx_desc;
2608
2609         qinfo->conf.tx_thresh.pthresh = txq->pthresh;
2610         qinfo->conf.tx_thresh.hthresh = txq->hthresh;
2611         qinfo->conf.tx_thresh.wthresh = txq->wthresh;
2612
2613         qinfo->conf.tx_free_thresh = txq->tx_free_thresh;
2614         qinfo->conf.tx_rs_thresh = 0;
2615         qinfo->conf.tx_deferred_start = txq->tx_deferred_start;
2616 }
2617
2618 static int
2619 bnxt_rx_burst_mode_get(struct rte_eth_dev *dev, __rte_unused uint16_t queue_id,
2620                        struct rte_eth_burst_mode *mode)
2621 {
2622         eth_rx_burst_t pkt_burst = dev->rx_pkt_burst;
2623
2624         if (pkt_burst == bnxt_recv_pkts) {
2625                 snprintf(mode->info, sizeof(mode->info), "%s",
2626                          "Scalar");
2627                 return 0;
2628         }
2629 #if defined(RTE_ARCH_X86) || defined(RTE_ARCH_ARM64)
2630         if (pkt_burst == bnxt_recv_pkts_vec) {
2631                 snprintf(mode->info, sizeof(mode->info), "%s",
2632                          "Vector SSE");
2633                 return 0;
2634         }
2635 #endif
2636
2637         return -EINVAL;
2638 }
2639
2640 static int
2641 bnxt_tx_burst_mode_get(struct rte_eth_dev *dev, __rte_unused uint16_t queue_id,
2642                        struct rte_eth_burst_mode *mode)
2643 {
2644         eth_tx_burst_t pkt_burst = dev->tx_pkt_burst;
2645
2646         if (pkt_burst == bnxt_xmit_pkts) {
2647                 snprintf(mode->info, sizeof(mode->info), "%s",
2648                          "Scalar");
2649                 return 0;
2650         }
2651 #if defined(RTE_ARCH_X86) || defined(RTE_ARCH_ARM64)
2652         if (pkt_burst == bnxt_xmit_pkts_vec) {
2653                 snprintf(mode->info, sizeof(mode->info), "%s",
2654                          "Vector SSE");
2655                 return 0;
2656         }
2657 #endif
2658
2659         return -EINVAL;
2660 }
2661
2662 int bnxt_mtu_set_op(struct rte_eth_dev *eth_dev, uint16_t new_mtu)
2663 {
2664         struct bnxt *bp = eth_dev->data->dev_private;
2665         uint32_t new_pkt_size;
2666         uint32_t rc = 0;
2667         uint32_t i;
2668
2669         rc = is_bnxt_in_error(bp);
2670         if (rc)
2671                 return rc;
2672
2673         /* Exit if receive queues are not configured yet */
2674         if (!eth_dev->data->nb_rx_queues)
2675                 return rc;
2676
2677         new_pkt_size = new_mtu + RTE_ETHER_HDR_LEN + RTE_ETHER_CRC_LEN +
2678                        VLAN_TAG_SIZE * BNXT_NUM_VLANS;
2679
2680 #if defined(RTE_ARCH_X86) || defined(RTE_ARCH_ARM64)
2681         /*
2682          * If vector-mode tx/rx is active, disallow any MTU change that would
2683          * require scattered receive support.
2684          */
2685         if (eth_dev->data->dev_started &&
2686             (eth_dev->rx_pkt_burst == bnxt_recv_pkts_vec ||
2687              eth_dev->tx_pkt_burst == bnxt_xmit_pkts_vec) &&
2688             (new_pkt_size >
2689              eth_dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM)) {
2690                 PMD_DRV_LOG(ERR,
2691                             "MTU change would require scattered rx support. ");
2692                 PMD_DRV_LOG(ERR, "Stop port before changing MTU.\n");
2693                 return -EINVAL;
2694         }
2695 #endif
2696
2697         if (new_mtu > RTE_ETHER_MTU) {
2698                 bp->flags |= BNXT_FLAG_JUMBO;
2699                 bp->eth_dev->data->dev_conf.rxmode.offloads |=
2700                         DEV_RX_OFFLOAD_JUMBO_FRAME;
2701         } else {
2702                 bp->eth_dev->data->dev_conf.rxmode.offloads &=
2703                         ~DEV_RX_OFFLOAD_JUMBO_FRAME;
2704                 bp->flags &= ~BNXT_FLAG_JUMBO;
2705         }
2706
2707         /* Is there a change in mtu setting? */
2708         if (eth_dev->data->dev_conf.rxmode.max_rx_pkt_len == new_pkt_size)
2709                 return rc;
2710
2711         for (i = 0; i < bp->nr_vnics; i++) {
2712                 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
2713                 uint16_t size = 0;
2714
2715                 vnic->mru = BNXT_VNIC_MRU(new_mtu);
2716                 rc = bnxt_hwrm_vnic_cfg(bp, vnic);
2717                 if (rc)
2718                         break;
2719
2720                 size = rte_pktmbuf_data_room_size(bp->rx_queues[0]->mb_pool);
2721                 size -= RTE_PKTMBUF_HEADROOM;
2722
2723                 if (size < new_mtu) {
2724                         rc = bnxt_hwrm_vnic_plcmode_cfg(bp, vnic);
2725                         if (rc)
2726                                 return rc;
2727                 }
2728         }
2729
2730         if (!rc)
2731                 eth_dev->data->dev_conf.rxmode.max_rx_pkt_len = new_pkt_size;
2732
2733         PMD_DRV_LOG(INFO, "New MTU is %d\n", new_mtu);
2734
2735         return rc;
2736 }
2737
2738 static int
2739 bnxt_vlan_pvid_set_op(struct rte_eth_dev *dev, uint16_t pvid, int on)
2740 {
2741         struct bnxt *bp = dev->data->dev_private;
2742         uint16_t vlan = bp->vlan;
2743         int rc;
2744
2745         rc = is_bnxt_in_error(bp);
2746         if (rc)
2747                 return rc;
2748
2749         if (!BNXT_SINGLE_PF(bp) || BNXT_VF(bp)) {
2750                 PMD_DRV_LOG(ERR,
2751                         "PVID cannot be modified for this function\n");
2752                 return -ENOTSUP;
2753         }
2754         bp->vlan = on ? pvid : 0;
2755
2756         rc = bnxt_hwrm_set_default_vlan(bp, 0, 0);
2757         if (rc)
2758                 bp->vlan = vlan;
2759         return rc;
2760 }
2761
2762 static int
2763 bnxt_dev_led_on_op(struct rte_eth_dev *dev)
2764 {
2765         struct bnxt *bp = dev->data->dev_private;
2766         int rc;
2767
2768         rc = is_bnxt_in_error(bp);
2769         if (rc)
2770                 return rc;
2771
2772         return bnxt_hwrm_port_led_cfg(bp, true);
2773 }
2774
2775 static int
2776 bnxt_dev_led_off_op(struct rte_eth_dev *dev)
2777 {
2778         struct bnxt *bp = dev->data->dev_private;
2779         int rc;
2780
2781         rc = is_bnxt_in_error(bp);
2782         if (rc)
2783                 return rc;
2784
2785         return bnxt_hwrm_port_led_cfg(bp, false);
2786 }
2787
2788 static uint32_t
2789 bnxt_rx_queue_count_op(struct rte_eth_dev *dev, uint16_t rx_queue_id)
2790 {
2791         struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
2792         uint32_t desc = 0, raw_cons = 0, cons;
2793         struct bnxt_cp_ring_info *cpr;
2794         struct bnxt_rx_queue *rxq;
2795         struct rx_pkt_cmpl *rxcmp;
2796         int rc;
2797
2798         rc = is_bnxt_in_error(bp);
2799         if (rc)
2800                 return rc;
2801
2802         rxq = dev->data->rx_queues[rx_queue_id];
2803         cpr = rxq->cp_ring;
2804         raw_cons = cpr->cp_raw_cons;
2805
2806         while (1) {
2807                 cons = RING_CMP(cpr->cp_ring_struct, raw_cons);
2808                 rte_prefetch0(&cpr->cp_desc_ring[cons]);
2809                 rxcmp = (struct rx_pkt_cmpl *)&cpr->cp_desc_ring[cons];
2810
2811                 if (!CMP_VALID(rxcmp, raw_cons, cpr->cp_ring_struct)) {
2812                         break;
2813                 } else {
2814                         raw_cons++;
2815                         desc++;
2816                 }
2817         }
2818
2819         return desc;
2820 }
2821
2822 static int
2823 bnxt_rx_descriptor_status_op(void *rx_queue, uint16_t offset)
2824 {
2825         struct bnxt_rx_queue *rxq = (struct bnxt_rx_queue *)rx_queue;
2826         struct bnxt_rx_ring_info *rxr;
2827         struct bnxt_cp_ring_info *cpr;
2828         struct bnxt_sw_rx_bd *rx_buf;
2829         struct rx_pkt_cmpl *rxcmp;
2830         uint32_t cons, cp_cons;
2831         int rc;
2832
2833         if (!rxq)
2834                 return -EINVAL;
2835
2836         rc = is_bnxt_in_error(rxq->bp);
2837         if (rc)
2838                 return rc;
2839
2840         cpr = rxq->cp_ring;
2841         rxr = rxq->rx_ring;
2842
2843         if (offset >= rxq->nb_rx_desc)
2844                 return -EINVAL;
2845
2846         cons = RING_CMP(cpr->cp_ring_struct, offset);
2847         cp_cons = cpr->cp_raw_cons;
2848         rxcmp = (struct rx_pkt_cmpl *)&cpr->cp_desc_ring[cons];
2849
2850         if (cons > cp_cons) {
2851                 if (CMPL_VALID(rxcmp, cpr->valid))
2852                         return RTE_ETH_RX_DESC_DONE;
2853         } else {
2854                 if (CMPL_VALID(rxcmp, !cpr->valid))
2855                         return RTE_ETH_RX_DESC_DONE;
2856         }
2857         rx_buf = &rxr->rx_buf_ring[cons];
2858         if (rx_buf->mbuf == NULL)
2859                 return RTE_ETH_RX_DESC_UNAVAIL;
2860
2861
2862         return RTE_ETH_RX_DESC_AVAIL;
2863 }
2864
2865 static int
2866 bnxt_tx_descriptor_status_op(void *tx_queue, uint16_t offset)
2867 {
2868         struct bnxt_tx_queue *txq = (struct bnxt_tx_queue *)tx_queue;
2869         struct bnxt_tx_ring_info *txr;
2870         struct bnxt_cp_ring_info *cpr;
2871         struct bnxt_sw_tx_bd *tx_buf;
2872         struct tx_pkt_cmpl *txcmp;
2873         uint32_t cons, cp_cons;
2874         int rc;
2875
2876         if (!txq)
2877                 return -EINVAL;
2878
2879         rc = is_bnxt_in_error(txq->bp);
2880         if (rc)
2881                 return rc;
2882
2883         cpr = txq->cp_ring;
2884         txr = txq->tx_ring;
2885
2886         if (offset >= txq->nb_tx_desc)
2887                 return -EINVAL;
2888
2889         cons = RING_CMP(cpr->cp_ring_struct, offset);
2890         txcmp = (struct tx_pkt_cmpl *)&cpr->cp_desc_ring[cons];
2891         cp_cons = cpr->cp_raw_cons;
2892
2893         if (cons > cp_cons) {
2894                 if (CMPL_VALID(txcmp, cpr->valid))
2895                         return RTE_ETH_TX_DESC_UNAVAIL;
2896         } else {
2897                 if (CMPL_VALID(txcmp, !cpr->valid))
2898                         return RTE_ETH_TX_DESC_UNAVAIL;
2899         }
2900         tx_buf = &txr->tx_buf_ring[cons];
2901         if (tx_buf->mbuf == NULL)
2902                 return RTE_ETH_TX_DESC_DONE;
2903
2904         return RTE_ETH_TX_DESC_FULL;
2905 }
2906
2907 static struct bnxt_filter_info *
2908 bnxt_match_and_validate_ether_filter(struct bnxt *bp,
2909                                 struct rte_eth_ethertype_filter *efilter,
2910                                 struct bnxt_vnic_info *vnic0,
2911                                 struct bnxt_vnic_info *vnic,
2912                                 int *ret)
2913 {
2914         struct bnxt_filter_info *mfilter = NULL;
2915         int match = 0;
2916         *ret = 0;
2917
2918         if (efilter->ether_type == RTE_ETHER_TYPE_IPV4 ||
2919                 efilter->ether_type == RTE_ETHER_TYPE_IPV6) {
2920                 PMD_DRV_LOG(ERR, "invalid ether_type(0x%04x) in"
2921                         " ethertype filter.", efilter->ether_type);
2922                 *ret = -EINVAL;
2923                 goto exit;
2924         }
2925         if (efilter->queue >= bp->rx_nr_rings) {
2926                 PMD_DRV_LOG(ERR, "Invalid queue %d\n", efilter->queue);
2927                 *ret = -EINVAL;
2928                 goto exit;
2929         }
2930
2931         vnic0 = BNXT_GET_DEFAULT_VNIC(bp);
2932         vnic = &bp->vnic_info[efilter->queue];
2933         if (vnic == NULL) {
2934                 PMD_DRV_LOG(ERR, "Invalid queue %d\n", efilter->queue);
2935                 *ret = -EINVAL;
2936                 goto exit;
2937         }
2938
2939         if (efilter->flags & RTE_ETHTYPE_FLAGS_DROP) {
2940                 STAILQ_FOREACH(mfilter, &vnic0->filter, next) {
2941                         if ((!memcmp(efilter->mac_addr.addr_bytes,
2942                                      mfilter->l2_addr, RTE_ETHER_ADDR_LEN) &&
2943                              mfilter->flags ==
2944                              HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_DROP &&
2945                              mfilter->ethertype == efilter->ether_type)) {
2946                                 match = 1;
2947                                 break;
2948                         }
2949                 }
2950         } else {
2951                 STAILQ_FOREACH(mfilter, &vnic->filter, next)
2952                         if ((!memcmp(efilter->mac_addr.addr_bytes,
2953                                      mfilter->l2_addr, RTE_ETHER_ADDR_LEN) &&
2954                              mfilter->ethertype == efilter->ether_type &&
2955                              mfilter->flags ==
2956                              HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_PATH_RX)) {
2957                                 match = 1;
2958                                 break;
2959                         }
2960         }
2961
2962         if (match)
2963                 *ret = -EEXIST;
2964
2965 exit:
2966         return mfilter;
2967 }
2968
2969 static int
2970 bnxt_ethertype_filter(struct rte_eth_dev *dev,
2971                         enum rte_filter_op filter_op,
2972                         void *arg)
2973 {
2974         struct bnxt *bp = dev->data->dev_private;
2975         struct rte_eth_ethertype_filter *efilter =
2976                         (struct rte_eth_ethertype_filter *)arg;
2977         struct bnxt_filter_info *bfilter, *filter1;
2978         struct bnxt_vnic_info *vnic, *vnic0;
2979         int ret;
2980
2981         if (filter_op == RTE_ETH_FILTER_NOP)
2982                 return 0;
2983
2984         if (arg == NULL) {
2985                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
2986                             filter_op);
2987                 return -EINVAL;
2988         }
2989
2990         vnic0 = BNXT_GET_DEFAULT_VNIC(bp);
2991         vnic = &bp->vnic_info[efilter->queue];
2992
2993         switch (filter_op) {
2994         case RTE_ETH_FILTER_ADD:
2995                 bnxt_match_and_validate_ether_filter(bp, efilter,
2996                                                         vnic0, vnic, &ret);
2997                 if (ret < 0)
2998                         return ret;
2999
3000                 bfilter = bnxt_get_unused_filter(bp);
3001                 if (bfilter == NULL) {
3002                         PMD_DRV_LOG(ERR,
3003                                 "Not enough resources for a new filter.\n");
3004                         return -ENOMEM;
3005                 }
3006                 bfilter->filter_type = HWRM_CFA_NTUPLE_FILTER;
3007                 memcpy(bfilter->l2_addr, efilter->mac_addr.addr_bytes,
3008                        RTE_ETHER_ADDR_LEN);
3009                 memcpy(bfilter->dst_macaddr, efilter->mac_addr.addr_bytes,
3010                        RTE_ETHER_ADDR_LEN);
3011                 bfilter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_MACADDR;
3012                 bfilter->ethertype = efilter->ether_type;
3013                 bfilter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
3014
3015                 filter1 = bnxt_get_l2_filter(bp, bfilter, vnic0);
3016                 if (filter1 == NULL) {
3017                         ret = -EINVAL;
3018                         goto cleanup;
3019                 }
3020                 bfilter->enables |=
3021                         HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID;
3022                 bfilter->fw_l2_filter_id = filter1->fw_l2_filter_id;
3023
3024                 bfilter->dst_id = vnic->fw_vnic_id;
3025
3026                 if (efilter->flags & RTE_ETHTYPE_FLAGS_DROP) {
3027                         bfilter->flags =
3028                                 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_DROP;
3029                 }
3030
3031                 ret = bnxt_hwrm_set_ntuple_filter(bp, bfilter->dst_id, bfilter);
3032                 if (ret)
3033                         goto cleanup;
3034                 STAILQ_INSERT_TAIL(&vnic->filter, bfilter, next);
3035                 break;
3036         case RTE_ETH_FILTER_DELETE:
3037                 filter1 = bnxt_match_and_validate_ether_filter(bp, efilter,
3038                                                         vnic0, vnic, &ret);
3039                 if (ret == -EEXIST) {
3040                         ret = bnxt_hwrm_clear_ntuple_filter(bp, filter1);
3041
3042                         STAILQ_REMOVE(&vnic->filter, filter1, bnxt_filter_info,
3043                                       next);
3044                         bnxt_free_filter(bp, filter1);
3045                 } else if (ret == 0) {
3046                         PMD_DRV_LOG(ERR, "No matching filter found\n");
3047                 }
3048                 break;
3049         default:
3050                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
3051                 ret = -EINVAL;
3052                 goto error;
3053         }
3054         return ret;
3055 cleanup:
3056         bnxt_free_filter(bp, bfilter);
3057 error:
3058         return ret;
3059 }
3060
3061 static inline int
3062 parse_ntuple_filter(struct bnxt *bp,
3063                     struct rte_eth_ntuple_filter *nfilter,
3064                     struct bnxt_filter_info *bfilter)
3065 {
3066         uint32_t en = 0;
3067
3068         if (nfilter->queue >= bp->rx_nr_rings) {
3069                 PMD_DRV_LOG(ERR, "Invalid queue %d\n", nfilter->queue);
3070                 return -EINVAL;
3071         }
3072
3073         switch (nfilter->dst_port_mask) {
3074         case UINT16_MAX:
3075                 bfilter->dst_port_mask = -1;
3076                 bfilter->dst_port = nfilter->dst_port;
3077                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT |
3078                         NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
3079                 break;
3080         default:
3081                 PMD_DRV_LOG(ERR, "invalid dst_port mask.");
3082                 return -EINVAL;
3083         }
3084
3085         bfilter->ip_addr_type = NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4;
3086         en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
3087
3088         switch (nfilter->proto_mask) {
3089         case UINT8_MAX:
3090                 if (nfilter->proto == 17) /* IPPROTO_UDP */
3091                         bfilter->ip_protocol = 17;
3092                 else if (nfilter->proto == 6) /* IPPROTO_TCP */
3093                         bfilter->ip_protocol = 6;
3094                 else
3095                         return -EINVAL;
3096                 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
3097                 break;
3098         default:
3099                 PMD_DRV_LOG(ERR, "invalid protocol mask.");
3100                 return -EINVAL;
3101         }
3102
3103         switch (nfilter->dst_ip_mask) {
3104         case UINT32_MAX:
3105                 bfilter->dst_ipaddr_mask[0] = -1;
3106                 bfilter->dst_ipaddr[0] = nfilter->dst_ip;
3107                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR |
3108                         NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
3109                 break;
3110         default:
3111                 PMD_DRV_LOG(ERR, "invalid dst_ip mask.");
3112                 return -EINVAL;
3113         }
3114
3115         switch (nfilter->src_ip_mask) {
3116         case UINT32_MAX:
3117                 bfilter->src_ipaddr_mask[0] = -1;
3118                 bfilter->src_ipaddr[0] = nfilter->src_ip;
3119                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR |
3120                         NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
3121                 break;
3122         default:
3123                 PMD_DRV_LOG(ERR, "invalid src_ip mask.");
3124                 return -EINVAL;
3125         }
3126
3127         switch (nfilter->src_port_mask) {
3128         case UINT16_MAX:
3129                 bfilter->src_port_mask = -1;
3130                 bfilter->src_port = nfilter->src_port;
3131                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT |
3132                         NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
3133                 break;
3134         default:
3135                 PMD_DRV_LOG(ERR, "invalid src_port mask.");
3136                 return -EINVAL;
3137         }
3138
3139         bfilter->enables = en;
3140         return 0;
3141 }
3142
3143 static struct bnxt_filter_info*
3144 bnxt_match_ntuple_filter(struct bnxt *bp,
3145                          struct bnxt_filter_info *bfilter,
3146                          struct bnxt_vnic_info **mvnic)
3147 {
3148         struct bnxt_filter_info *mfilter = NULL;
3149         int i;
3150
3151         for (i = bp->nr_vnics - 1; i >= 0; i--) {
3152                 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
3153                 STAILQ_FOREACH(mfilter, &vnic->filter, next) {
3154                         if (bfilter->src_ipaddr[0] == mfilter->src_ipaddr[0] &&
3155                             bfilter->src_ipaddr_mask[0] ==
3156                             mfilter->src_ipaddr_mask[0] &&
3157                             bfilter->src_port == mfilter->src_port &&
3158                             bfilter->src_port_mask == mfilter->src_port_mask &&
3159                             bfilter->dst_ipaddr[0] == mfilter->dst_ipaddr[0] &&
3160                             bfilter->dst_ipaddr_mask[0] ==
3161                             mfilter->dst_ipaddr_mask[0] &&
3162                             bfilter->dst_port == mfilter->dst_port &&
3163                             bfilter->dst_port_mask == mfilter->dst_port_mask &&
3164                             bfilter->flags == mfilter->flags &&
3165                             bfilter->enables == mfilter->enables) {
3166                                 if (mvnic)
3167                                         *mvnic = vnic;
3168                                 return mfilter;
3169                         }
3170                 }
3171         }
3172         return NULL;
3173 }
3174
3175 static int
3176 bnxt_cfg_ntuple_filter(struct bnxt *bp,
3177                        struct rte_eth_ntuple_filter *nfilter,
3178                        enum rte_filter_op filter_op)
3179 {
3180         struct bnxt_filter_info *bfilter, *mfilter, *filter1;
3181         struct bnxt_vnic_info *vnic, *vnic0, *mvnic;
3182         int ret;
3183
3184         if (nfilter->flags != RTE_5TUPLE_FLAGS) {
3185                 PMD_DRV_LOG(ERR, "only 5tuple is supported.");
3186                 return -EINVAL;
3187         }
3188
3189         if (nfilter->flags & RTE_NTUPLE_FLAGS_TCP_FLAG) {
3190                 PMD_DRV_LOG(ERR, "Ntuple filter: TCP flags not supported\n");
3191                 return -EINVAL;
3192         }
3193
3194         bfilter = bnxt_get_unused_filter(bp);
3195         if (bfilter == NULL) {
3196                 PMD_DRV_LOG(ERR,
3197                         "Not enough resources for a new filter.\n");
3198                 return -ENOMEM;
3199         }
3200         ret = parse_ntuple_filter(bp, nfilter, bfilter);
3201         if (ret < 0)
3202                 goto free_filter;
3203
3204         vnic = &bp->vnic_info[nfilter->queue];
3205         vnic0 = BNXT_GET_DEFAULT_VNIC(bp);
3206         filter1 = STAILQ_FIRST(&vnic0->filter);
3207         if (filter1 == NULL) {
3208                 ret = -EINVAL;
3209                 goto free_filter;
3210         }
3211
3212         bfilter->dst_id = vnic->fw_vnic_id;
3213         bfilter->fw_l2_filter_id = filter1->fw_l2_filter_id;
3214         bfilter->enables |=
3215                 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID;
3216         bfilter->ethertype = 0x800;
3217         bfilter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
3218
3219         mfilter = bnxt_match_ntuple_filter(bp, bfilter, &mvnic);
3220
3221         if (mfilter != NULL && filter_op == RTE_ETH_FILTER_ADD &&
3222             bfilter->dst_id == mfilter->dst_id) {
3223                 PMD_DRV_LOG(ERR, "filter exists.\n");
3224                 ret = -EEXIST;
3225                 goto free_filter;
3226         } else if (mfilter != NULL && filter_op == RTE_ETH_FILTER_ADD &&
3227                    bfilter->dst_id != mfilter->dst_id) {
3228                 mfilter->dst_id = vnic->fw_vnic_id;
3229                 ret = bnxt_hwrm_set_ntuple_filter(bp, mfilter->dst_id, mfilter);
3230                 STAILQ_REMOVE(&mvnic->filter, mfilter, bnxt_filter_info, next);
3231                 STAILQ_INSERT_TAIL(&vnic->filter, mfilter, next);
3232                 PMD_DRV_LOG(ERR, "filter with matching pattern exists.\n");
3233                 PMD_DRV_LOG(ERR, " Updated it to the new destination queue\n");
3234                 goto free_filter;
3235         }
3236         if (mfilter == NULL && filter_op == RTE_ETH_FILTER_DELETE) {
3237                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
3238                 ret = -ENOENT;
3239                 goto free_filter;
3240         }
3241
3242         if (filter_op == RTE_ETH_FILTER_ADD) {
3243                 bfilter->filter_type = HWRM_CFA_NTUPLE_FILTER;
3244                 ret = bnxt_hwrm_set_ntuple_filter(bp, bfilter->dst_id, bfilter);
3245                 if (ret)
3246                         goto free_filter;
3247                 STAILQ_INSERT_TAIL(&vnic->filter, bfilter, next);
3248         } else {
3249                 if (mfilter == NULL) {
3250                         /* This should not happen. But for Coverity! */
3251                         ret = -ENOENT;
3252                         goto free_filter;
3253                 }
3254                 ret = bnxt_hwrm_clear_ntuple_filter(bp, mfilter);
3255
3256                 STAILQ_REMOVE(&vnic->filter, mfilter, bnxt_filter_info, next);
3257                 bnxt_free_filter(bp, mfilter);
3258                 bnxt_free_filter(bp, bfilter);
3259         }
3260
3261         return 0;
3262 free_filter:
3263         bnxt_free_filter(bp, bfilter);
3264         return ret;
3265 }
3266
3267 static int
3268 bnxt_ntuple_filter(struct rte_eth_dev *dev,
3269                         enum rte_filter_op filter_op,
3270                         void *arg)
3271 {
3272         struct bnxt *bp = dev->data->dev_private;
3273         int ret;
3274
3275         if (filter_op == RTE_ETH_FILTER_NOP)
3276                 return 0;
3277
3278         if (arg == NULL) {
3279                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
3280                             filter_op);
3281                 return -EINVAL;
3282         }
3283
3284         switch (filter_op) {
3285         case RTE_ETH_FILTER_ADD:
3286                 ret = bnxt_cfg_ntuple_filter(bp,
3287                         (struct rte_eth_ntuple_filter *)arg,
3288                         filter_op);
3289                 break;
3290         case RTE_ETH_FILTER_DELETE:
3291                 ret = bnxt_cfg_ntuple_filter(bp,
3292                         (struct rte_eth_ntuple_filter *)arg,
3293                         filter_op);
3294                 break;
3295         default:
3296                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
3297                 ret = -EINVAL;
3298                 break;
3299         }
3300         return ret;
3301 }
3302
3303 static int
3304 bnxt_parse_fdir_filter(struct bnxt *bp,
3305                        struct rte_eth_fdir_filter *fdir,
3306                        struct bnxt_filter_info *filter)
3307 {
3308         enum rte_fdir_mode fdir_mode =
3309                 bp->eth_dev->data->dev_conf.fdir_conf.mode;
3310         struct bnxt_vnic_info *vnic0, *vnic;
3311         struct bnxt_filter_info *filter1;
3312         uint32_t en = 0;
3313         int i;
3314
3315         if (fdir_mode == RTE_FDIR_MODE_PERFECT_TUNNEL)
3316                 return -EINVAL;
3317
3318         filter->l2_ovlan = fdir->input.flow_ext.vlan_tci;
3319         en |= EM_FLOW_ALLOC_INPUT_EN_OVLAN_VID;
3320
3321         switch (fdir->input.flow_type) {
3322         case RTE_ETH_FLOW_IPV4:
3323         case RTE_ETH_FLOW_NONFRAG_IPV4_OTHER:
3324                 /* FALLTHROUGH */
3325                 filter->src_ipaddr[0] = fdir->input.flow.ip4_flow.src_ip;
3326                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
3327                 filter->dst_ipaddr[0] = fdir->input.flow.ip4_flow.dst_ip;
3328                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
3329                 filter->ip_protocol = fdir->input.flow.ip4_flow.proto;
3330                 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
3331                 filter->ip_addr_type =
3332                         NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4;
3333                 filter->src_ipaddr_mask[0] = 0xffffffff;
3334                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
3335                 filter->dst_ipaddr_mask[0] = 0xffffffff;
3336                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
3337                 filter->ethertype = 0x800;
3338                 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
3339                 break;
3340         case RTE_ETH_FLOW_NONFRAG_IPV4_TCP:
3341                 filter->src_port = fdir->input.flow.tcp4_flow.src_port;
3342                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT;
3343                 filter->dst_port = fdir->input.flow.tcp4_flow.dst_port;
3344                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT;
3345                 filter->dst_port_mask = 0xffff;
3346                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
3347                 filter->src_port_mask = 0xffff;
3348                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
3349                 filter->src_ipaddr[0] = fdir->input.flow.tcp4_flow.ip.src_ip;
3350                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
3351                 filter->dst_ipaddr[0] = fdir->input.flow.tcp4_flow.ip.dst_ip;
3352                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
3353                 filter->ip_protocol = 6;
3354                 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
3355                 filter->ip_addr_type =
3356                         NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4;
3357                 filter->src_ipaddr_mask[0] = 0xffffffff;
3358                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
3359                 filter->dst_ipaddr_mask[0] = 0xffffffff;
3360                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
3361                 filter->ethertype = 0x800;
3362                 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
3363                 break;
3364         case RTE_ETH_FLOW_NONFRAG_IPV4_UDP:
3365                 filter->src_port = fdir->input.flow.udp4_flow.src_port;
3366                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT;
3367                 filter->dst_port = fdir->input.flow.udp4_flow.dst_port;
3368                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT;
3369                 filter->dst_port_mask = 0xffff;
3370                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
3371                 filter->src_port_mask = 0xffff;
3372                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
3373                 filter->src_ipaddr[0] = fdir->input.flow.udp4_flow.ip.src_ip;
3374                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
3375                 filter->dst_ipaddr[0] = fdir->input.flow.udp4_flow.ip.dst_ip;
3376                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
3377                 filter->ip_protocol = 17;
3378                 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
3379                 filter->ip_addr_type =
3380                         NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4;
3381                 filter->src_ipaddr_mask[0] = 0xffffffff;
3382                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
3383                 filter->dst_ipaddr_mask[0] = 0xffffffff;
3384                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
3385                 filter->ethertype = 0x800;
3386                 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
3387                 break;
3388         case RTE_ETH_FLOW_IPV6:
3389         case RTE_ETH_FLOW_NONFRAG_IPV6_OTHER:
3390                 /* FALLTHROUGH */
3391                 filter->ip_addr_type =
3392                         NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV6;
3393                 filter->ip_protocol = fdir->input.flow.ipv6_flow.proto;
3394                 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
3395                 rte_memcpy(filter->src_ipaddr,
3396                            fdir->input.flow.ipv6_flow.src_ip, 16);
3397                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
3398                 rte_memcpy(filter->dst_ipaddr,
3399                            fdir->input.flow.ipv6_flow.dst_ip, 16);
3400                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
3401                 memset(filter->dst_ipaddr_mask, 0xff, 16);
3402                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
3403                 memset(filter->src_ipaddr_mask, 0xff, 16);
3404                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
3405                 filter->ethertype = 0x86dd;
3406                 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
3407                 break;
3408         case RTE_ETH_FLOW_NONFRAG_IPV6_TCP:
3409                 filter->src_port = fdir->input.flow.tcp6_flow.src_port;
3410                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT;
3411                 filter->dst_port = fdir->input.flow.tcp6_flow.dst_port;
3412                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT;
3413                 filter->dst_port_mask = 0xffff;
3414                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
3415                 filter->src_port_mask = 0xffff;
3416                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
3417                 filter->ip_addr_type =
3418                         NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV6;
3419                 filter->ip_protocol = fdir->input.flow.tcp6_flow.ip.proto;
3420                 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
3421                 rte_memcpy(filter->src_ipaddr,
3422                            fdir->input.flow.tcp6_flow.ip.src_ip, 16);
3423                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
3424                 rte_memcpy(filter->dst_ipaddr,
3425                            fdir->input.flow.tcp6_flow.ip.dst_ip, 16);
3426                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
3427                 memset(filter->dst_ipaddr_mask, 0xff, 16);
3428                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
3429                 memset(filter->src_ipaddr_mask, 0xff, 16);
3430                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
3431                 filter->ethertype = 0x86dd;
3432                 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
3433                 break;
3434         case RTE_ETH_FLOW_NONFRAG_IPV6_UDP:
3435                 filter->src_port = fdir->input.flow.udp6_flow.src_port;
3436                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT;
3437                 filter->dst_port = fdir->input.flow.udp6_flow.dst_port;
3438                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT;
3439                 filter->dst_port_mask = 0xffff;
3440                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
3441                 filter->src_port_mask = 0xffff;
3442                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
3443                 filter->ip_addr_type =
3444                         NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV6;
3445                 filter->ip_protocol = fdir->input.flow.udp6_flow.ip.proto;
3446                 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
3447                 rte_memcpy(filter->src_ipaddr,
3448                            fdir->input.flow.udp6_flow.ip.src_ip, 16);
3449                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
3450                 rte_memcpy(filter->dst_ipaddr,
3451                            fdir->input.flow.udp6_flow.ip.dst_ip, 16);
3452                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
3453                 memset(filter->dst_ipaddr_mask, 0xff, 16);
3454                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
3455                 memset(filter->src_ipaddr_mask, 0xff, 16);
3456                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
3457                 filter->ethertype = 0x86dd;
3458                 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
3459                 break;
3460         case RTE_ETH_FLOW_L2_PAYLOAD:
3461                 filter->ethertype = fdir->input.flow.l2_flow.ether_type;
3462                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
3463                 break;
3464         case RTE_ETH_FLOW_VXLAN:
3465                 if (fdir->action.behavior == RTE_ETH_FDIR_REJECT)
3466                         return -EINVAL;
3467                 filter->vni = fdir->input.flow.tunnel_flow.tunnel_id;
3468                 filter->tunnel_type =
3469                         CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN;
3470                 en |= HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_TUNNEL_TYPE;
3471                 break;
3472         case RTE_ETH_FLOW_NVGRE:
3473                 if (fdir->action.behavior == RTE_ETH_FDIR_REJECT)
3474                         return -EINVAL;
3475                 filter->vni = fdir->input.flow.tunnel_flow.tunnel_id;
3476                 filter->tunnel_type =
3477                         CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_NVGRE;
3478                 en |= HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_TUNNEL_TYPE;
3479                 break;
3480         case RTE_ETH_FLOW_UNKNOWN:
3481         case RTE_ETH_FLOW_RAW:
3482         case RTE_ETH_FLOW_FRAG_IPV4:
3483         case RTE_ETH_FLOW_NONFRAG_IPV4_SCTP:
3484         case RTE_ETH_FLOW_FRAG_IPV6:
3485         case RTE_ETH_FLOW_NONFRAG_IPV6_SCTP:
3486         case RTE_ETH_FLOW_IPV6_EX:
3487         case RTE_ETH_FLOW_IPV6_TCP_EX:
3488         case RTE_ETH_FLOW_IPV6_UDP_EX:
3489         case RTE_ETH_FLOW_GENEVE:
3490                 /* FALLTHROUGH */
3491         default:
3492                 return -EINVAL;
3493         }
3494
3495         vnic0 = BNXT_GET_DEFAULT_VNIC(bp);
3496         vnic = &bp->vnic_info[fdir->action.rx_queue];
3497         if (vnic == NULL) {
3498                 PMD_DRV_LOG(ERR, "Invalid queue %d\n", fdir->action.rx_queue);
3499                 return -EINVAL;
3500         }
3501
3502         if (fdir_mode == RTE_FDIR_MODE_PERFECT_MAC_VLAN) {
3503                 rte_memcpy(filter->dst_macaddr,
3504                         fdir->input.flow.mac_vlan_flow.mac_addr.addr_bytes, 6);
3505                         en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_MACADDR;
3506         }
3507
3508         if (fdir->action.behavior == RTE_ETH_FDIR_REJECT) {
3509                 filter->flags = HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_DROP;
3510                 filter1 = STAILQ_FIRST(&vnic0->filter);
3511                 //filter1 = bnxt_get_l2_filter(bp, filter, vnic0);
3512         } else {
3513                 filter->dst_id = vnic->fw_vnic_id;
3514                 for (i = 0; i < RTE_ETHER_ADDR_LEN; i++)
3515                         if (filter->dst_macaddr[i] == 0x00)
3516                                 filter1 = STAILQ_FIRST(&vnic0->filter);
3517                         else
3518                                 filter1 = bnxt_get_l2_filter(bp, filter, vnic);
3519         }
3520
3521         if (filter1 == NULL)
3522                 return -EINVAL;
3523
3524         en |= HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID;
3525         filter->fw_l2_filter_id = filter1->fw_l2_filter_id;
3526
3527         filter->enables = en;
3528
3529         return 0;
3530 }
3531
3532 static struct bnxt_filter_info *
3533 bnxt_match_fdir(struct bnxt *bp, struct bnxt_filter_info *nf,
3534                 struct bnxt_vnic_info **mvnic)
3535 {
3536         struct bnxt_filter_info *mf = NULL;
3537         int i;
3538
3539         for (i = bp->nr_vnics - 1; i >= 0; i--) {
3540                 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
3541
3542                 STAILQ_FOREACH(mf, &vnic->filter, next) {
3543                         if (mf->filter_type == nf->filter_type &&
3544                             mf->flags == nf->flags &&
3545                             mf->src_port == nf->src_port &&
3546                             mf->src_port_mask == nf->src_port_mask &&
3547                             mf->dst_port == nf->dst_port &&
3548                             mf->dst_port_mask == nf->dst_port_mask &&
3549                             mf->ip_protocol == nf->ip_protocol &&
3550                             mf->ip_addr_type == nf->ip_addr_type &&
3551                             mf->ethertype == nf->ethertype &&
3552                             mf->vni == nf->vni &&
3553                             mf->tunnel_type == nf->tunnel_type &&
3554                             mf->l2_ovlan == nf->l2_ovlan &&
3555                             mf->l2_ovlan_mask == nf->l2_ovlan_mask &&
3556                             mf->l2_ivlan == nf->l2_ivlan &&
3557                             mf->l2_ivlan_mask == nf->l2_ivlan_mask &&
3558                             !memcmp(mf->l2_addr, nf->l2_addr,
3559                                     RTE_ETHER_ADDR_LEN) &&
3560                             !memcmp(mf->l2_addr_mask, nf->l2_addr_mask,
3561                                     RTE_ETHER_ADDR_LEN) &&
3562                             !memcmp(mf->src_macaddr, nf->src_macaddr,
3563                                     RTE_ETHER_ADDR_LEN) &&
3564                             !memcmp(mf->dst_macaddr, nf->dst_macaddr,
3565                                     RTE_ETHER_ADDR_LEN) &&
3566                             !memcmp(mf->src_ipaddr, nf->src_ipaddr,
3567                                     sizeof(nf->src_ipaddr)) &&
3568                             !memcmp(mf->src_ipaddr_mask, nf->src_ipaddr_mask,
3569                                     sizeof(nf->src_ipaddr_mask)) &&
3570                             !memcmp(mf->dst_ipaddr, nf->dst_ipaddr,
3571                                     sizeof(nf->dst_ipaddr)) &&
3572                             !memcmp(mf->dst_ipaddr_mask, nf->dst_ipaddr_mask,
3573                                     sizeof(nf->dst_ipaddr_mask))) {
3574                                 if (mvnic)
3575                                         *mvnic = vnic;
3576                                 return mf;
3577                         }
3578                 }
3579         }
3580         return NULL;
3581 }
3582
3583 static int
3584 bnxt_fdir_filter(struct rte_eth_dev *dev,
3585                  enum rte_filter_op filter_op,
3586                  void *arg)
3587 {
3588         struct bnxt *bp = dev->data->dev_private;
3589         struct rte_eth_fdir_filter *fdir  = (struct rte_eth_fdir_filter *)arg;
3590         struct bnxt_filter_info *filter, *match;
3591         struct bnxt_vnic_info *vnic, *mvnic;
3592         int ret = 0, i;
3593
3594         if (filter_op == RTE_ETH_FILTER_NOP)
3595                 return 0;
3596
3597         if (arg == NULL && filter_op != RTE_ETH_FILTER_FLUSH)
3598                 return -EINVAL;
3599
3600         switch (filter_op) {
3601         case RTE_ETH_FILTER_ADD:
3602         case RTE_ETH_FILTER_DELETE:
3603                 /* FALLTHROUGH */
3604                 filter = bnxt_get_unused_filter(bp);
3605                 if (filter == NULL) {
3606                         PMD_DRV_LOG(ERR,
3607                                 "Not enough resources for a new flow.\n");
3608                         return -ENOMEM;
3609                 }
3610
3611                 ret = bnxt_parse_fdir_filter(bp, fdir, filter);
3612                 if (ret != 0)
3613                         goto free_filter;
3614                 filter->filter_type = HWRM_CFA_NTUPLE_FILTER;
3615
3616                 if (fdir->action.behavior == RTE_ETH_FDIR_REJECT)
3617                         vnic = &bp->vnic_info[0];
3618                 else
3619                         vnic = &bp->vnic_info[fdir->action.rx_queue];
3620
3621                 match = bnxt_match_fdir(bp, filter, &mvnic);
3622                 if (match != NULL && filter_op == RTE_ETH_FILTER_ADD) {
3623                         if (match->dst_id == vnic->fw_vnic_id) {
3624                                 PMD_DRV_LOG(ERR, "Flow already exists.\n");
3625                                 ret = -EEXIST;
3626                                 goto free_filter;
3627                         } else {
3628                                 match->dst_id = vnic->fw_vnic_id;
3629                                 ret = bnxt_hwrm_set_ntuple_filter(bp,
3630                                                                   match->dst_id,
3631                                                                   match);
3632                                 STAILQ_REMOVE(&mvnic->filter, match,
3633                                               bnxt_filter_info, next);
3634                                 STAILQ_INSERT_TAIL(&vnic->filter, match, next);
3635                                 PMD_DRV_LOG(ERR,
3636                                         "Filter with matching pattern exist\n");
3637                                 PMD_DRV_LOG(ERR,
3638                                         "Updated it to new destination q\n");
3639                                 goto free_filter;
3640                         }
3641                 }
3642                 if (match == NULL && filter_op == RTE_ETH_FILTER_DELETE) {
3643                         PMD_DRV_LOG(ERR, "Flow does not exist.\n");
3644                         ret = -ENOENT;
3645                         goto free_filter;
3646                 }
3647
3648                 if (filter_op == RTE_ETH_FILTER_ADD) {
3649                         ret = bnxt_hwrm_set_ntuple_filter(bp,
3650                                                           filter->dst_id,
3651                                                           filter);
3652                         if (ret)
3653                                 goto free_filter;
3654                         STAILQ_INSERT_TAIL(&vnic->filter, filter, next);
3655                 } else {
3656                         ret = bnxt_hwrm_clear_ntuple_filter(bp, match);
3657                         STAILQ_REMOVE(&vnic->filter, match,
3658                                       bnxt_filter_info, next);
3659                         bnxt_free_filter(bp, match);
3660                         bnxt_free_filter(bp, filter);
3661                 }
3662                 break;
3663         case RTE_ETH_FILTER_FLUSH:
3664                 for (i = bp->nr_vnics - 1; i >= 0; i--) {
3665                         struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
3666
3667                         STAILQ_FOREACH(filter, &vnic->filter, next) {
3668                                 if (filter->filter_type ==
3669                                     HWRM_CFA_NTUPLE_FILTER) {
3670                                         ret =
3671                                         bnxt_hwrm_clear_ntuple_filter(bp,
3672                                                                       filter);
3673                                         STAILQ_REMOVE(&vnic->filter, filter,
3674                                                       bnxt_filter_info, next);
3675                                 }
3676                         }
3677                 }
3678                 return ret;
3679         case RTE_ETH_FILTER_UPDATE:
3680         case RTE_ETH_FILTER_STATS:
3681         case RTE_ETH_FILTER_INFO:
3682                 PMD_DRV_LOG(ERR, "operation %u not implemented", filter_op);
3683                 break;
3684         default:
3685                 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
3686                 ret = -EINVAL;
3687                 break;
3688         }
3689         return ret;
3690
3691 free_filter:
3692         bnxt_free_filter(bp, filter);
3693         return ret;
3694 }
3695
3696 int
3697 bnxt_filter_ctrl_op(struct rte_eth_dev *dev,
3698                     enum rte_filter_type filter_type,
3699                     enum rte_filter_op filter_op, void *arg)
3700 {
3701         struct bnxt *bp = dev->data->dev_private;
3702         int ret = 0;
3703
3704         if (BNXT_ETH_DEV_IS_REPRESENTOR(dev)) {
3705                 struct bnxt_vf_representor *vfr = dev->data->dev_private;
3706                 bp = vfr->parent_dev->data->dev_private;
3707         }
3708
3709         ret = is_bnxt_in_error(bp);
3710         if (ret)
3711                 return ret;
3712
3713         switch (filter_type) {
3714         case RTE_ETH_FILTER_TUNNEL:
3715                 PMD_DRV_LOG(ERR,
3716                         "filter type: %d: To be implemented\n", filter_type);
3717                 break;
3718         case RTE_ETH_FILTER_FDIR:
3719                 ret = bnxt_fdir_filter(dev, filter_op, arg);
3720                 break;
3721         case RTE_ETH_FILTER_NTUPLE:
3722                 ret = bnxt_ntuple_filter(dev, filter_op, arg);
3723                 break;
3724         case RTE_ETH_FILTER_ETHERTYPE:
3725                 ret = bnxt_ethertype_filter(dev, filter_op, arg);
3726                 break;
3727         case RTE_ETH_FILTER_GENERIC:
3728                 if (filter_op != RTE_ETH_FILTER_GET)
3729                         return -EINVAL;
3730                 if (BNXT_TRUFLOW_EN(bp))
3731                         *(const void **)arg = &bnxt_ulp_rte_flow_ops;
3732                 else
3733                         *(const void **)arg = &bnxt_flow_ops;
3734                 break;
3735         default:
3736                 PMD_DRV_LOG(ERR,
3737                         "Filter type (%d) not supported", filter_type);
3738                 ret = -EINVAL;
3739                 break;
3740         }
3741         return ret;
3742 }
3743
3744 static const uint32_t *
3745 bnxt_dev_supported_ptypes_get_op(struct rte_eth_dev *dev)
3746 {
3747         static const uint32_t ptypes[] = {
3748                 RTE_PTYPE_L2_ETHER_VLAN,
3749                 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN,
3750                 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN,
3751                 RTE_PTYPE_L4_ICMP,
3752                 RTE_PTYPE_L4_TCP,
3753                 RTE_PTYPE_L4_UDP,
3754                 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN,
3755                 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN,
3756                 RTE_PTYPE_INNER_L4_ICMP,
3757                 RTE_PTYPE_INNER_L4_TCP,
3758                 RTE_PTYPE_INNER_L4_UDP,
3759                 RTE_PTYPE_UNKNOWN
3760         };
3761
3762         if (!dev->rx_pkt_burst)
3763                 return NULL;
3764
3765         return ptypes;
3766 }
3767
3768 static int bnxt_map_regs(struct bnxt *bp, uint32_t *reg_arr, int count,
3769                          int reg_win)
3770 {
3771         uint32_t reg_base = *reg_arr & 0xfffff000;
3772         uint32_t win_off;
3773         int i;
3774
3775         for (i = 0; i < count; i++) {
3776                 if ((reg_arr[i] & 0xfffff000) != reg_base)
3777                         return -ERANGE;
3778         }
3779         win_off = BNXT_GRCPF_REG_WINDOW_BASE_OUT + (reg_win - 1) * 4;
3780         rte_write32(reg_base, (uint8_t *)bp->bar0 + win_off);
3781         return 0;
3782 }
3783
3784 static int bnxt_map_ptp_regs(struct bnxt *bp)
3785 {
3786         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3787         uint32_t *reg_arr;
3788         int rc, i;
3789
3790         reg_arr = ptp->rx_regs;
3791         rc = bnxt_map_regs(bp, reg_arr, BNXT_PTP_RX_REGS, 5);
3792         if (rc)
3793                 return rc;
3794
3795         reg_arr = ptp->tx_regs;
3796         rc = bnxt_map_regs(bp, reg_arr, BNXT_PTP_TX_REGS, 6);
3797         if (rc)
3798                 return rc;
3799
3800         for (i = 0; i < BNXT_PTP_RX_REGS; i++)
3801                 ptp->rx_mapped_regs[i] = 0x5000 + (ptp->rx_regs[i] & 0xfff);
3802
3803         for (i = 0; i < BNXT_PTP_TX_REGS; i++)
3804                 ptp->tx_mapped_regs[i] = 0x6000 + (ptp->tx_regs[i] & 0xfff);
3805
3806         return 0;
3807 }
3808
3809 static void bnxt_unmap_ptp_regs(struct bnxt *bp)
3810 {
3811         rte_write32(0, (uint8_t *)bp->bar0 +
3812                          BNXT_GRCPF_REG_WINDOW_BASE_OUT + 16);
3813         rte_write32(0, (uint8_t *)bp->bar0 +
3814                          BNXT_GRCPF_REG_WINDOW_BASE_OUT + 20);
3815 }
3816
3817 static uint64_t bnxt_cc_read(struct bnxt *bp)
3818 {
3819         uint64_t ns;
3820
3821         ns = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3822                               BNXT_GRCPF_REG_SYNC_TIME));
3823         ns |= (uint64_t)(rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3824                                           BNXT_GRCPF_REG_SYNC_TIME + 4))) << 32;
3825         return ns;
3826 }
3827
3828 static int bnxt_get_tx_ts(struct bnxt *bp, uint64_t *ts)
3829 {
3830         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3831         uint32_t fifo;
3832
3833         fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3834                                 ptp->tx_mapped_regs[BNXT_PTP_TX_FIFO]));
3835         if (fifo & BNXT_PTP_TX_FIFO_EMPTY)
3836                 return -EAGAIN;
3837
3838         fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3839                                 ptp->tx_mapped_regs[BNXT_PTP_TX_FIFO]));
3840         *ts = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3841                                 ptp->tx_mapped_regs[BNXT_PTP_TX_TS_L]));
3842         *ts |= (uint64_t)rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3843                                 ptp->tx_mapped_regs[BNXT_PTP_TX_TS_H])) << 32;
3844
3845         return 0;
3846 }
3847
3848 static int bnxt_get_rx_ts(struct bnxt *bp, uint64_t *ts)
3849 {
3850         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3851         struct bnxt_pf_info *pf = bp->pf;
3852         uint16_t port_id;
3853         uint32_t fifo;
3854
3855         if (!ptp)
3856                 return -ENODEV;
3857
3858         fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3859                                 ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO]));
3860         if (!(fifo & BNXT_PTP_RX_FIFO_PENDING))
3861                 return -EAGAIN;
3862
3863         port_id = pf->port_id;
3864         rte_write32(1 << port_id, (uint8_t *)bp->bar0 +
3865                ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO_ADV]);
3866
3867         fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3868                                    ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO]));
3869         if (fifo & BNXT_PTP_RX_FIFO_PENDING) {
3870 /*              bnxt_clr_rx_ts(bp);       TBD  */
3871                 return -EBUSY;
3872         }
3873
3874         *ts = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3875                                 ptp->rx_mapped_regs[BNXT_PTP_RX_TS_L]));
3876         *ts |= (uint64_t)rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3877                                 ptp->rx_mapped_regs[BNXT_PTP_RX_TS_H])) << 32;
3878
3879         return 0;
3880 }
3881
3882 static int
3883 bnxt_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
3884 {
3885         uint64_t ns;
3886         struct bnxt *bp = dev->data->dev_private;
3887         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3888
3889         if (!ptp)
3890                 return 0;
3891
3892         ns = rte_timespec_to_ns(ts);
3893         /* Set the timecounters to a new value. */
3894         ptp->tc.nsec = ns;
3895
3896         return 0;
3897 }
3898
3899 static int
3900 bnxt_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
3901 {
3902         struct bnxt *bp = dev->data->dev_private;
3903         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3904         uint64_t ns, systime_cycles = 0;
3905         int rc = 0;
3906
3907         if (!ptp)
3908                 return 0;
3909
3910         if (BNXT_CHIP_THOR(bp))
3911                 rc = bnxt_hwrm_port_ts_query(bp, BNXT_PTP_FLAGS_CURRENT_TIME,
3912                                              &systime_cycles);
3913         else
3914                 systime_cycles = bnxt_cc_read(bp);
3915
3916         ns = rte_timecounter_update(&ptp->tc, systime_cycles);
3917         *ts = rte_ns_to_timespec(ns);
3918
3919         return rc;
3920 }
3921 static int
3922 bnxt_timesync_enable(struct rte_eth_dev *dev)
3923 {
3924         struct bnxt *bp = dev->data->dev_private;
3925         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3926         uint32_t shift = 0;
3927         int rc;
3928
3929         if (!ptp)
3930                 return 0;
3931
3932         ptp->rx_filter = 1;
3933         ptp->tx_tstamp_en = 1;
3934         ptp->rxctl = BNXT_PTP_MSG_EVENTS;
3935
3936         rc = bnxt_hwrm_ptp_cfg(bp);
3937         if (rc)
3938                 return rc;
3939
3940         memset(&ptp->tc, 0, sizeof(struct rte_timecounter));
3941         memset(&ptp->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
3942         memset(&ptp->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
3943
3944         ptp->tc.cc_mask = BNXT_CYCLECOUNTER_MASK;
3945         ptp->tc.cc_shift = shift;
3946         ptp->tc.nsec_mask = (1ULL << shift) - 1;
3947
3948         ptp->rx_tstamp_tc.cc_mask = BNXT_CYCLECOUNTER_MASK;
3949         ptp->rx_tstamp_tc.cc_shift = shift;
3950         ptp->rx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
3951
3952         ptp->tx_tstamp_tc.cc_mask = BNXT_CYCLECOUNTER_MASK;
3953         ptp->tx_tstamp_tc.cc_shift = shift;
3954         ptp->tx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
3955
3956         if (!BNXT_CHIP_THOR(bp))
3957                 bnxt_map_ptp_regs(bp);
3958
3959         return 0;
3960 }
3961
3962 static int
3963 bnxt_timesync_disable(struct rte_eth_dev *dev)
3964 {
3965         struct bnxt *bp = dev->data->dev_private;
3966         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3967
3968         if (!ptp)
3969                 return 0;
3970
3971         ptp->rx_filter = 0;
3972         ptp->tx_tstamp_en = 0;
3973         ptp->rxctl = 0;
3974
3975         bnxt_hwrm_ptp_cfg(bp);
3976
3977         if (!BNXT_CHIP_THOR(bp))
3978                 bnxt_unmap_ptp_regs(bp);
3979
3980         return 0;
3981 }
3982
3983 static int
3984 bnxt_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
3985                                  struct timespec *timestamp,
3986                                  uint32_t flags __rte_unused)
3987 {
3988         struct bnxt *bp = dev->data->dev_private;
3989         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3990         uint64_t rx_tstamp_cycles = 0;
3991         uint64_t ns;
3992
3993         if (!ptp)
3994                 return 0;
3995
3996         if (BNXT_CHIP_THOR(bp))
3997                 rx_tstamp_cycles = ptp->rx_timestamp;
3998         else
3999                 bnxt_get_rx_ts(bp, &rx_tstamp_cycles);
4000
4001         ns = rte_timecounter_update(&ptp->rx_tstamp_tc, rx_tstamp_cycles);
4002         *timestamp = rte_ns_to_timespec(ns);
4003         return  0;
4004 }
4005
4006 static int
4007 bnxt_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
4008                                  struct timespec *timestamp)
4009 {
4010         struct bnxt *bp = dev->data->dev_private;
4011         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
4012         uint64_t tx_tstamp_cycles = 0;
4013         uint64_t ns;
4014         int rc = 0;
4015
4016         if (!ptp)
4017                 return 0;
4018
4019         if (BNXT_CHIP_THOR(bp))
4020                 rc = bnxt_hwrm_port_ts_query(bp, BNXT_PTP_FLAGS_PATH_TX,
4021                                              &tx_tstamp_cycles);
4022         else
4023                 rc = bnxt_get_tx_ts(bp, &tx_tstamp_cycles);
4024
4025         ns = rte_timecounter_update(&ptp->tx_tstamp_tc, tx_tstamp_cycles);
4026         *timestamp = rte_ns_to_timespec(ns);
4027
4028         return rc;
4029 }
4030
4031 static int
4032 bnxt_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
4033 {
4034         struct bnxt *bp = dev->data->dev_private;
4035         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
4036
4037         if (!ptp)
4038                 return 0;
4039
4040         ptp->tc.nsec += delta;
4041
4042         return 0;
4043 }
4044
4045 static int
4046 bnxt_get_eeprom_length_op(struct rte_eth_dev *dev)
4047 {
4048         struct bnxt *bp = dev->data->dev_private;
4049         int rc;
4050         uint32_t dir_entries;
4051         uint32_t entry_length;
4052
4053         rc = is_bnxt_in_error(bp);
4054         if (rc)
4055                 return rc;
4056
4057         PMD_DRV_LOG(INFO, PCI_PRI_FMT "\n",
4058                     bp->pdev->addr.domain, bp->pdev->addr.bus,
4059                     bp->pdev->addr.devid, bp->pdev->addr.function);
4060
4061         rc = bnxt_hwrm_nvm_get_dir_info(bp, &dir_entries, &entry_length);
4062         if (rc != 0)
4063                 return rc;
4064
4065         return dir_entries * entry_length;
4066 }
4067
4068 static int
4069 bnxt_get_eeprom_op(struct rte_eth_dev *dev,
4070                 struct rte_dev_eeprom_info *in_eeprom)
4071 {
4072         struct bnxt *bp = dev->data->dev_private;
4073         uint32_t index;
4074         uint32_t offset;
4075         int rc;
4076
4077         rc = is_bnxt_in_error(bp);
4078         if (rc)
4079                 return rc;
4080
4081         PMD_DRV_LOG(INFO, PCI_PRI_FMT " in_eeprom->offset = %d len = %d\n",
4082                     bp->pdev->addr.domain, bp->pdev->addr.bus,
4083                     bp->pdev->addr.devid, bp->pdev->addr.function,
4084                     in_eeprom->offset, in_eeprom->length);
4085
4086         if (in_eeprom->offset == 0) /* special offset value to get directory */
4087                 return bnxt_get_nvram_directory(bp, in_eeprom->length,
4088                                                 in_eeprom->data);
4089
4090         index = in_eeprom->offset >> 24;
4091         offset = in_eeprom->offset & 0xffffff;
4092
4093         if (index != 0)
4094                 return bnxt_hwrm_get_nvram_item(bp, index - 1, offset,
4095                                            in_eeprom->length, in_eeprom->data);
4096
4097         return 0;
4098 }
4099
4100 static bool bnxt_dir_type_is_ape_bin_format(uint16_t dir_type)
4101 {
4102         switch (dir_type) {
4103         case BNX_DIR_TYPE_CHIMP_PATCH:
4104         case BNX_DIR_TYPE_BOOTCODE:
4105         case BNX_DIR_TYPE_BOOTCODE_2:
4106         case BNX_DIR_TYPE_APE_FW:
4107         case BNX_DIR_TYPE_APE_PATCH:
4108         case BNX_DIR_TYPE_KONG_FW:
4109         case BNX_DIR_TYPE_KONG_PATCH:
4110         case BNX_DIR_TYPE_BONO_FW:
4111         case BNX_DIR_TYPE_BONO_PATCH:
4112                 /* FALLTHROUGH */
4113                 return true;
4114         }
4115
4116         return false;
4117 }
4118
4119 static bool bnxt_dir_type_is_other_exec_format(uint16_t dir_type)
4120 {
4121         switch (dir_type) {
4122         case BNX_DIR_TYPE_AVS:
4123         case BNX_DIR_TYPE_EXP_ROM_MBA:
4124         case BNX_DIR_TYPE_PCIE:
4125         case BNX_DIR_TYPE_TSCF_UCODE:
4126         case BNX_DIR_TYPE_EXT_PHY:
4127         case BNX_DIR_TYPE_CCM:
4128         case BNX_DIR_TYPE_ISCSI_BOOT:
4129         case BNX_DIR_TYPE_ISCSI_BOOT_IPV6:
4130         case BNX_DIR_TYPE_ISCSI_BOOT_IPV4N6:
4131                 /* FALLTHROUGH */
4132                 return true;
4133         }
4134
4135         return false;
4136 }
4137
4138 static bool bnxt_dir_type_is_executable(uint16_t dir_type)
4139 {
4140         return bnxt_dir_type_is_ape_bin_format(dir_type) ||
4141                 bnxt_dir_type_is_other_exec_format(dir_type);
4142 }
4143
4144 static int
4145 bnxt_set_eeprom_op(struct rte_eth_dev *dev,
4146                 struct rte_dev_eeprom_info *in_eeprom)
4147 {
4148         struct bnxt *bp = dev->data->dev_private;
4149         uint8_t index, dir_op;
4150         uint16_t type, ext, ordinal, attr;
4151         int rc;
4152
4153         rc = is_bnxt_in_error(bp);
4154         if (rc)
4155                 return rc;
4156
4157         PMD_DRV_LOG(INFO, PCI_PRI_FMT " in_eeprom->offset = %d len = %d\n",
4158                     bp->pdev->addr.domain, bp->pdev->addr.bus,
4159                     bp->pdev->addr.devid, bp->pdev->addr.function,
4160                     in_eeprom->offset, in_eeprom->length);
4161
4162         if (!BNXT_PF(bp)) {
4163                 PMD_DRV_LOG(ERR, "NVM write not supported from a VF\n");
4164                 return -EINVAL;
4165         }
4166
4167         type = in_eeprom->magic >> 16;
4168
4169         if (type == 0xffff) { /* special value for directory operations */
4170                 index = in_eeprom->magic & 0xff;
4171                 dir_op = in_eeprom->magic >> 8;
4172                 if (index == 0)
4173                         return -EINVAL;
4174                 switch (dir_op) {
4175                 case 0x0e: /* erase */
4176                         if (in_eeprom->offset != ~in_eeprom->magic)
4177                                 return -EINVAL;
4178                         return bnxt_hwrm_erase_nvram_directory(bp, index - 1);
4179                 default:
4180                         return -EINVAL;
4181                 }
4182         }
4183
4184         /* Create or re-write an NVM item: */
4185         if (bnxt_dir_type_is_executable(type) == true)
4186                 return -EOPNOTSUPP;
4187         ext = in_eeprom->magic & 0xffff;
4188         ordinal = in_eeprom->offset >> 16;
4189         attr = in_eeprom->offset & 0xffff;
4190
4191         return bnxt_hwrm_flash_nvram(bp, type, ordinal, ext, attr,
4192                                      in_eeprom->data, in_eeprom->length);
4193 }
4194
4195 /*
4196  * Initialization
4197  */
4198
4199 static const struct eth_dev_ops bnxt_dev_ops = {
4200         .dev_infos_get = bnxt_dev_info_get_op,
4201         .dev_close = bnxt_dev_close_op,
4202         .dev_configure = bnxt_dev_configure_op,
4203         .dev_start = bnxt_dev_start_op,
4204         .dev_stop = bnxt_dev_stop_op,
4205         .dev_set_link_up = bnxt_dev_set_link_up_op,
4206         .dev_set_link_down = bnxt_dev_set_link_down_op,
4207         .stats_get = bnxt_stats_get_op,
4208         .stats_reset = bnxt_stats_reset_op,
4209         .rx_queue_setup = bnxt_rx_queue_setup_op,
4210         .rx_queue_release = bnxt_rx_queue_release_op,
4211         .tx_queue_setup = bnxt_tx_queue_setup_op,
4212         .tx_queue_release = bnxt_tx_queue_release_op,
4213         .rx_queue_intr_enable = bnxt_rx_queue_intr_enable_op,
4214         .rx_queue_intr_disable = bnxt_rx_queue_intr_disable_op,
4215         .reta_update = bnxt_reta_update_op,
4216         .reta_query = bnxt_reta_query_op,
4217         .rss_hash_update = bnxt_rss_hash_update_op,
4218         .rss_hash_conf_get = bnxt_rss_hash_conf_get_op,
4219         .link_update = bnxt_link_update_op,
4220         .promiscuous_enable = bnxt_promiscuous_enable_op,
4221         .promiscuous_disable = bnxt_promiscuous_disable_op,
4222         .allmulticast_enable = bnxt_allmulticast_enable_op,
4223         .allmulticast_disable = bnxt_allmulticast_disable_op,
4224         .mac_addr_add = bnxt_mac_addr_add_op,
4225         .mac_addr_remove = bnxt_mac_addr_remove_op,
4226         .flow_ctrl_get = bnxt_flow_ctrl_get_op,
4227         .flow_ctrl_set = bnxt_flow_ctrl_set_op,
4228         .udp_tunnel_port_add  = bnxt_udp_tunnel_port_add_op,
4229         .udp_tunnel_port_del  = bnxt_udp_tunnel_port_del_op,
4230         .vlan_filter_set = bnxt_vlan_filter_set_op,
4231         .vlan_offload_set = bnxt_vlan_offload_set_op,
4232         .vlan_tpid_set = bnxt_vlan_tpid_set_op,
4233         .vlan_pvid_set = bnxt_vlan_pvid_set_op,
4234         .mtu_set = bnxt_mtu_set_op,
4235         .mac_addr_set = bnxt_set_default_mac_addr_op,
4236         .xstats_get = bnxt_dev_xstats_get_op,
4237         .xstats_get_names = bnxt_dev_xstats_get_names_op,
4238         .xstats_reset = bnxt_dev_xstats_reset_op,
4239         .fw_version_get = bnxt_fw_version_get,
4240         .set_mc_addr_list = bnxt_dev_set_mc_addr_list_op,
4241         .rxq_info_get = bnxt_rxq_info_get_op,
4242         .txq_info_get = bnxt_txq_info_get_op,
4243         .rx_burst_mode_get = bnxt_rx_burst_mode_get,
4244         .tx_burst_mode_get = bnxt_tx_burst_mode_get,
4245         .dev_led_on = bnxt_dev_led_on_op,
4246         .dev_led_off = bnxt_dev_led_off_op,
4247         .xstats_get_by_id = bnxt_dev_xstats_get_by_id_op,
4248         .xstats_get_names_by_id = bnxt_dev_xstats_get_names_by_id_op,
4249         .rx_queue_start = bnxt_rx_queue_start,
4250         .rx_queue_stop = bnxt_rx_queue_stop,
4251         .tx_queue_start = bnxt_tx_queue_start,
4252         .tx_queue_stop = bnxt_tx_queue_stop,
4253         .filter_ctrl = bnxt_filter_ctrl_op,
4254         .dev_supported_ptypes_get = bnxt_dev_supported_ptypes_get_op,
4255         .get_eeprom_length    = bnxt_get_eeprom_length_op,
4256         .get_eeprom           = bnxt_get_eeprom_op,
4257         .set_eeprom           = bnxt_set_eeprom_op,
4258         .timesync_enable      = bnxt_timesync_enable,
4259         .timesync_disable     = bnxt_timesync_disable,
4260         .timesync_read_time   = bnxt_timesync_read_time,
4261         .timesync_write_time   = bnxt_timesync_write_time,
4262         .timesync_adjust_time = bnxt_timesync_adjust_time,
4263         .timesync_read_rx_timestamp = bnxt_timesync_read_rx_timestamp,
4264         .timesync_read_tx_timestamp = bnxt_timesync_read_tx_timestamp,
4265 };
4266
4267 static uint32_t bnxt_map_reset_regs(struct bnxt *bp, uint32_t reg)
4268 {
4269         uint32_t offset;
4270
4271         /* Only pre-map the reset GRC registers using window 3 */
4272         rte_write32(reg & 0xfffff000, (uint8_t *)bp->bar0 +
4273                     BNXT_GRCPF_REG_WINDOW_BASE_OUT + 8);
4274
4275         offset = BNXT_GRCP_WINDOW_3_BASE + (reg & 0xffc);
4276
4277         return offset;
4278 }
4279
4280 int bnxt_map_fw_health_status_regs(struct bnxt *bp)
4281 {
4282         struct bnxt_error_recovery_info *info = bp->recovery_info;
4283         uint32_t reg_base = 0xffffffff;
4284         int i;
4285
4286         /* Only pre-map the monitoring GRC registers using window 2 */
4287         for (i = 0; i < BNXT_FW_STATUS_REG_CNT; i++) {
4288                 uint32_t reg = info->status_regs[i];
4289
4290                 if (BNXT_FW_STATUS_REG_TYPE(reg) != BNXT_FW_STATUS_REG_TYPE_GRC)
4291                         continue;
4292
4293                 if (reg_base == 0xffffffff)
4294                         reg_base = reg & 0xfffff000;
4295                 if ((reg & 0xfffff000) != reg_base)
4296                         return -ERANGE;
4297
4298                 /* Use mask 0xffc as the Lower 2 bits indicates
4299                  * address space location
4300                  */
4301                 info->mapped_status_regs[i] = BNXT_GRCP_WINDOW_2_BASE +
4302                                                 (reg & 0xffc);
4303         }
4304
4305         if (reg_base == 0xffffffff)
4306                 return 0;
4307
4308         rte_write32(reg_base, (uint8_t *)bp->bar0 +
4309                     BNXT_GRCPF_REG_WINDOW_BASE_OUT + 4);
4310
4311         return 0;
4312 }
4313
4314 static void bnxt_write_fw_reset_reg(struct bnxt *bp, uint32_t index)
4315 {
4316         struct bnxt_error_recovery_info *info = bp->recovery_info;
4317         uint32_t delay = info->delay_after_reset[index];
4318         uint32_t val = info->reset_reg_val[index];
4319         uint32_t reg = info->reset_reg[index];
4320         uint32_t type, offset;
4321
4322         type = BNXT_FW_STATUS_REG_TYPE(reg);
4323         offset = BNXT_FW_STATUS_REG_OFF(reg);
4324
4325         switch (type) {
4326         case BNXT_FW_STATUS_REG_TYPE_CFG:
4327                 rte_pci_write_config(bp->pdev, &val, sizeof(val), offset);
4328                 break;
4329         case BNXT_FW_STATUS_REG_TYPE_GRC:
4330                 offset = bnxt_map_reset_regs(bp, offset);
4331                 rte_write32(val, (uint8_t *)bp->bar0 + offset);
4332                 break;
4333         case BNXT_FW_STATUS_REG_TYPE_BAR0:
4334                 rte_write32(val, (uint8_t *)bp->bar0 + offset);
4335                 break;
4336         }
4337         /* wait on a specific interval of time until core reset is complete */
4338         if (delay)
4339                 rte_delay_ms(delay);
4340 }
4341
4342 static void bnxt_dev_cleanup(struct bnxt *bp)
4343 {
4344         bnxt_set_hwrm_link_config(bp, false);
4345         bp->link_info->link_up = 0;
4346         if (bp->eth_dev->data->dev_started)
4347                 bnxt_dev_stop_op(bp->eth_dev);
4348
4349         bnxt_uninit_resources(bp, true);
4350 }
4351
4352 static int bnxt_restore_vlan_filters(struct bnxt *bp)
4353 {
4354         struct rte_eth_dev *dev = bp->eth_dev;
4355         struct rte_vlan_filter_conf *vfc;
4356         int vidx, vbit, rc;
4357         uint16_t vlan_id;
4358
4359         for (vlan_id = 1; vlan_id <= RTE_ETHER_MAX_VLAN_ID; vlan_id++) {
4360                 vfc = &dev->data->vlan_filter_conf;
4361                 vidx = vlan_id / 64;
4362                 vbit = vlan_id % 64;
4363
4364                 /* Each bit corresponds to a VLAN id */
4365                 if (vfc->ids[vidx] & (UINT64_C(1) << vbit)) {
4366                         rc = bnxt_add_vlan_filter(bp, vlan_id);
4367                         if (rc)
4368                                 return rc;
4369                 }
4370         }
4371
4372         return 0;
4373 }
4374
4375 static int bnxt_restore_mac_filters(struct bnxt *bp)
4376 {
4377         struct rte_eth_dev *dev = bp->eth_dev;
4378         struct rte_eth_dev_info dev_info;
4379         struct rte_ether_addr *addr;
4380         uint64_t pool_mask;
4381         uint32_t pool = 0;
4382         uint16_t i;
4383         int rc;
4384
4385         if (BNXT_VF(bp) && !BNXT_VF_IS_TRUSTED(bp))
4386                 return 0;
4387
4388         rc = bnxt_dev_info_get_op(dev, &dev_info);
4389         if (rc)
4390                 return rc;
4391
4392         /* replay MAC address configuration */
4393         for (i = 1; i < dev_info.max_mac_addrs; i++) {
4394                 addr = &dev->data->mac_addrs[i];
4395
4396                 /* skip zero address */
4397                 if (rte_is_zero_ether_addr(addr))
4398                         continue;
4399
4400                 pool = 0;
4401                 pool_mask = dev->data->mac_pool_sel[i];
4402
4403                 do {
4404                         if (pool_mask & 1ULL) {
4405                                 rc = bnxt_mac_addr_add_op(dev, addr, i, pool);
4406                                 if (rc)
4407                                         return rc;
4408                         }
4409                         pool_mask >>= 1;
4410                         pool++;
4411                 } while (pool_mask);
4412         }
4413
4414         return 0;
4415 }
4416
4417 static int bnxt_restore_filters(struct bnxt *bp)
4418 {
4419         struct rte_eth_dev *dev = bp->eth_dev;
4420         int ret = 0;
4421
4422         if (dev->data->all_multicast) {
4423                 ret = bnxt_allmulticast_enable_op(dev);
4424                 if (ret)
4425                         return ret;
4426         }
4427         if (dev->data->promiscuous) {
4428                 ret = bnxt_promiscuous_enable_op(dev);
4429                 if (ret)
4430                         return ret;
4431         }
4432
4433         ret = bnxt_restore_mac_filters(bp);
4434         if (ret)
4435                 return ret;
4436
4437         ret = bnxt_restore_vlan_filters(bp);
4438         /* TODO restore other filters as well */
4439         return ret;
4440 }
4441
4442 static void bnxt_dev_recover(void *arg)
4443 {
4444         struct bnxt *bp = arg;
4445         int timeout = bp->fw_reset_max_msecs;
4446         int rc = 0;
4447
4448         /* Clear Error flag so that device re-init should happen */
4449         bp->flags &= ~BNXT_FLAG_FATAL_ERROR;
4450
4451         do {
4452                 rc = bnxt_hwrm_ver_get(bp, SHORT_HWRM_CMD_TIMEOUT);
4453                 if (rc == 0)
4454                         break;
4455                 rte_delay_ms(BNXT_FW_READY_WAIT_INTERVAL);
4456                 timeout -= BNXT_FW_READY_WAIT_INTERVAL;
4457         } while (rc && timeout);
4458
4459         if (rc) {
4460                 PMD_DRV_LOG(ERR, "FW is not Ready after reset\n");
4461                 goto err;
4462         }
4463
4464         rc = bnxt_init_resources(bp, true);
4465         if (rc) {
4466                 PMD_DRV_LOG(ERR,
4467                             "Failed to initialize resources after reset\n");
4468                 goto err;
4469         }
4470         /* clear reset flag as the device is initialized now */
4471         bp->flags &= ~BNXT_FLAG_FW_RESET;
4472
4473         rc = bnxt_dev_start_op(bp->eth_dev);
4474         if (rc) {
4475                 PMD_DRV_LOG(ERR, "Failed to start port after reset\n");
4476                 goto err_start;
4477         }
4478
4479         rc = bnxt_restore_filters(bp);
4480         if (rc)
4481                 goto err_start;
4482
4483         PMD_DRV_LOG(INFO, "Recovered from FW reset\n");
4484         return;
4485 err_start:
4486         bnxt_dev_stop_op(bp->eth_dev);
4487 err:
4488         bp->flags |= BNXT_FLAG_FATAL_ERROR;
4489         bnxt_uninit_resources(bp, false);
4490         PMD_DRV_LOG(ERR, "Failed to recover from FW reset\n");
4491 }
4492
4493 void bnxt_dev_reset_and_resume(void *arg)
4494 {
4495         struct bnxt *bp = arg;
4496         int rc;
4497
4498         bnxt_dev_cleanup(bp);
4499
4500         bnxt_wait_for_device_shutdown(bp);
4501
4502         rc = rte_eal_alarm_set(US_PER_MS * bp->fw_reset_min_msecs,
4503                                bnxt_dev_recover, (void *)bp);
4504         if (rc)
4505                 PMD_DRV_LOG(ERR, "Error setting recovery alarm");
4506 }
4507
4508 uint32_t bnxt_read_fw_status_reg(struct bnxt *bp, uint32_t index)
4509 {
4510         struct bnxt_error_recovery_info *info = bp->recovery_info;
4511         uint32_t reg = info->status_regs[index];
4512         uint32_t type, offset, val = 0;
4513
4514         type = BNXT_FW_STATUS_REG_TYPE(reg);
4515         offset = BNXT_FW_STATUS_REG_OFF(reg);
4516
4517         switch (type) {
4518         case BNXT_FW_STATUS_REG_TYPE_CFG:
4519                 rte_pci_read_config(bp->pdev, &val, sizeof(val), offset);
4520                 break;
4521         case BNXT_FW_STATUS_REG_TYPE_GRC:
4522                 offset = info->mapped_status_regs[index];
4523                 /* FALLTHROUGH */
4524         case BNXT_FW_STATUS_REG_TYPE_BAR0:
4525                 val = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
4526                                        offset));
4527                 break;
4528         }
4529
4530         return val;
4531 }
4532
4533 static int bnxt_fw_reset_all(struct bnxt *bp)
4534 {
4535         struct bnxt_error_recovery_info *info = bp->recovery_info;
4536         uint32_t i;
4537         int rc = 0;
4538
4539         if (info->flags & BNXT_FLAG_ERROR_RECOVERY_HOST) {
4540                 /* Reset through master function driver */
4541                 for (i = 0; i < info->reg_array_cnt; i++)
4542                         bnxt_write_fw_reset_reg(bp, i);
4543                 /* Wait for time specified by FW after triggering reset */
4544                 rte_delay_ms(info->master_func_wait_period_after_reset);
4545         } else if (info->flags & BNXT_FLAG_ERROR_RECOVERY_CO_CPU) {
4546                 /* Reset with the help of Kong processor */
4547                 rc = bnxt_hwrm_fw_reset(bp);
4548                 if (rc)
4549                         PMD_DRV_LOG(ERR, "Failed to reset FW\n");
4550         }
4551
4552         return rc;
4553 }
4554
4555 static void bnxt_fw_reset_cb(void *arg)
4556 {
4557         struct bnxt *bp = arg;
4558         struct bnxt_error_recovery_info *info = bp->recovery_info;
4559         int rc = 0;
4560
4561         /* Only Master function can do FW reset */
4562         if (bnxt_is_master_func(bp) &&
4563             bnxt_is_recovery_enabled(bp)) {
4564                 rc = bnxt_fw_reset_all(bp);
4565                 if (rc) {
4566                         PMD_DRV_LOG(ERR, "Adapter recovery failed\n");
4567                         return;
4568                 }
4569         }
4570
4571         /* if recovery method is ERROR_RECOVERY_CO_CPU, KONG will send
4572          * EXCEPTION_FATAL_ASYNC event to all the functions
4573          * (including MASTER FUNC). After receiving this Async, all the active
4574          * drivers should treat this case as FW initiated recovery
4575          */
4576         if (info->flags & BNXT_FLAG_ERROR_RECOVERY_HOST) {
4577                 bp->fw_reset_min_msecs = BNXT_MIN_FW_READY_TIMEOUT;
4578                 bp->fw_reset_max_msecs = BNXT_MAX_FW_RESET_TIMEOUT;
4579
4580                 /* To recover from error */
4581                 rte_eal_alarm_set(US_PER_MS, bnxt_dev_reset_and_resume,
4582                                   (void *)bp);
4583         }
4584 }
4585
4586 /* Driver should poll FW heartbeat, reset_counter with the frequency
4587  * advertised by FW in HWRM_ERROR_RECOVERY_QCFG.
4588  * When the driver detects heartbeat stop or change in reset_counter,
4589  * it has to trigger a reset to recover from the error condition.
4590  * A “master PF” is the function who will have the privilege to
4591  * initiate the chimp reset. The master PF will be elected by the
4592  * firmware and will be notified through async message.
4593  */
4594 static void bnxt_check_fw_health(void *arg)
4595 {
4596         struct bnxt *bp = arg;
4597         struct bnxt_error_recovery_info *info = bp->recovery_info;
4598         uint32_t val = 0, wait_msec;
4599
4600         if (!info || !bnxt_is_recovery_enabled(bp) ||
4601             is_bnxt_in_error(bp))
4602                 return;
4603
4604         val = bnxt_read_fw_status_reg(bp, BNXT_FW_HEARTBEAT_CNT_REG);
4605         if (val == info->last_heart_beat)
4606                 goto reset;
4607
4608         info->last_heart_beat = val;
4609
4610         val = bnxt_read_fw_status_reg(bp, BNXT_FW_RECOVERY_CNT_REG);
4611         if (val != info->last_reset_counter)
4612                 goto reset;
4613
4614         info->last_reset_counter = val;
4615
4616         rte_eal_alarm_set(US_PER_MS * info->driver_polling_freq,
4617                           bnxt_check_fw_health, (void *)bp);
4618
4619         return;
4620 reset:
4621         /* Stop DMA to/from device */
4622         bp->flags |= BNXT_FLAG_FATAL_ERROR;
4623         bp->flags |= BNXT_FLAG_FW_RESET;
4624
4625         PMD_DRV_LOG(ERR, "Detected FW dead condition\n");
4626
4627         if (bnxt_is_master_func(bp))
4628                 wait_msec = info->master_func_wait_period;
4629         else
4630                 wait_msec = info->normal_func_wait_period;
4631
4632         rte_eal_alarm_set(US_PER_MS * wait_msec,
4633                           bnxt_fw_reset_cb, (void *)bp);
4634 }
4635
4636 void bnxt_schedule_fw_health_check(struct bnxt *bp)
4637 {
4638         uint32_t polling_freq;
4639
4640         if (!bnxt_is_recovery_enabled(bp))
4641                 return;
4642
4643         if (bp->flags & BNXT_FLAG_FW_HEALTH_CHECK_SCHEDULED)
4644                 return;
4645
4646         polling_freq = bp->recovery_info->driver_polling_freq;
4647
4648         rte_eal_alarm_set(US_PER_MS * polling_freq,
4649                           bnxt_check_fw_health, (void *)bp);
4650         bp->flags |= BNXT_FLAG_FW_HEALTH_CHECK_SCHEDULED;
4651 }
4652
4653 static void bnxt_cancel_fw_health_check(struct bnxt *bp)
4654 {
4655         if (!bnxt_is_recovery_enabled(bp))
4656                 return;
4657
4658         rte_eal_alarm_cancel(bnxt_check_fw_health, (void *)bp);
4659         bp->flags &= ~BNXT_FLAG_FW_HEALTH_CHECK_SCHEDULED;
4660 }
4661
4662 static bool bnxt_vf_pciid(uint16_t device_id)
4663 {
4664         switch (device_id) {
4665         case BROADCOM_DEV_ID_57304_VF:
4666         case BROADCOM_DEV_ID_57406_VF:
4667         case BROADCOM_DEV_ID_5731X_VF:
4668         case BROADCOM_DEV_ID_5741X_VF:
4669         case BROADCOM_DEV_ID_57414_VF:
4670         case BROADCOM_DEV_ID_STRATUS_NIC_VF1:
4671         case BROADCOM_DEV_ID_STRATUS_NIC_VF2:
4672         case BROADCOM_DEV_ID_58802_VF:
4673         case BROADCOM_DEV_ID_57500_VF1:
4674         case BROADCOM_DEV_ID_57500_VF2:
4675                 /* FALLTHROUGH */
4676                 return true;
4677         default:
4678                 return false;
4679         }
4680 }
4681
4682 static bool bnxt_thor_device(uint16_t device_id)
4683 {
4684         switch (device_id) {
4685         case BROADCOM_DEV_ID_57508:
4686         case BROADCOM_DEV_ID_57504:
4687         case BROADCOM_DEV_ID_57502:
4688         case BROADCOM_DEV_ID_57508_MF1:
4689         case BROADCOM_DEV_ID_57504_MF1:
4690         case BROADCOM_DEV_ID_57502_MF1:
4691         case BROADCOM_DEV_ID_57508_MF2:
4692         case BROADCOM_DEV_ID_57504_MF2:
4693         case BROADCOM_DEV_ID_57502_MF2:
4694         case BROADCOM_DEV_ID_57500_VF1:
4695         case BROADCOM_DEV_ID_57500_VF2:
4696                 /* FALLTHROUGH */
4697                 return true;
4698         default:
4699                 return false;
4700         }
4701 }
4702
4703 bool bnxt_stratus_device(struct bnxt *bp)
4704 {
4705         uint16_t device_id = bp->pdev->id.device_id;
4706
4707         switch (device_id) {
4708         case BROADCOM_DEV_ID_STRATUS_NIC:
4709         case BROADCOM_DEV_ID_STRATUS_NIC_VF1:
4710         case BROADCOM_DEV_ID_STRATUS_NIC_VF2:
4711                 /* FALLTHROUGH */
4712                 return true;
4713         default:
4714                 return false;
4715         }
4716 }
4717
4718 static int bnxt_init_board(struct rte_eth_dev *eth_dev)
4719 {
4720         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
4721         struct bnxt *bp = eth_dev->data->dev_private;
4722
4723         /* enable device (incl. PCI PM wakeup), and bus-mastering */
4724         bp->bar0 = (void *)pci_dev->mem_resource[0].addr;
4725         bp->doorbell_base = (void *)pci_dev->mem_resource[2].addr;
4726         if (!bp->bar0 || !bp->doorbell_base) {
4727                 PMD_DRV_LOG(ERR, "Unable to access Hardware\n");
4728                 return -ENODEV;
4729         }
4730
4731         bp->eth_dev = eth_dev;
4732         bp->pdev = pci_dev;
4733
4734         return 0;
4735 }
4736
4737 static int bnxt_alloc_ctx_mem_blk(struct bnxt *bp,
4738                                   struct bnxt_ctx_pg_info *ctx_pg,
4739                                   uint32_t mem_size,
4740                                   const char *suffix,
4741                                   uint16_t idx)
4742 {
4743         struct bnxt_ring_mem_info *rmem = &ctx_pg->ring_mem;
4744         const struct rte_memzone *mz = NULL;
4745         char mz_name[RTE_MEMZONE_NAMESIZE];
4746         rte_iova_t mz_phys_addr;
4747         uint64_t valid_bits = 0;
4748         uint32_t sz;
4749         int i;
4750
4751         if (!mem_size)
4752                 return 0;
4753
4754         rmem->nr_pages = RTE_ALIGN_MUL_CEIL(mem_size, BNXT_PAGE_SIZE) /
4755                          BNXT_PAGE_SIZE;
4756         rmem->page_size = BNXT_PAGE_SIZE;
4757         rmem->pg_arr = ctx_pg->ctx_pg_arr;
4758         rmem->dma_arr = ctx_pg->ctx_dma_arr;
4759         rmem->flags = BNXT_RMEM_VALID_PTE_FLAG;
4760
4761         valid_bits = PTU_PTE_VALID;
4762
4763         if (rmem->nr_pages > 1) {
4764                 snprintf(mz_name, RTE_MEMZONE_NAMESIZE,
4765                          "bnxt_ctx_pg_tbl%s_%x_%d",
4766                          suffix, idx, bp->eth_dev->data->port_id);
4767                 mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0;
4768                 mz = rte_memzone_lookup(mz_name);
4769                 if (!mz) {
4770                         mz = rte_memzone_reserve_aligned(mz_name,
4771                                                 rmem->nr_pages * 8,
4772                                                 SOCKET_ID_ANY,
4773                                                 RTE_MEMZONE_2MB |
4774                                                 RTE_MEMZONE_SIZE_HINT_ONLY |
4775                                                 RTE_MEMZONE_IOVA_CONTIG,
4776                                                 BNXT_PAGE_SIZE);
4777                         if (mz == NULL)
4778                                 return -ENOMEM;
4779                 }
4780
4781                 memset(mz->addr, 0, mz->len);
4782                 mz_phys_addr = mz->iova;
4783
4784                 rmem->pg_tbl = mz->addr;
4785                 rmem->pg_tbl_map = mz_phys_addr;
4786                 rmem->pg_tbl_mz = mz;
4787         }
4788
4789         snprintf(mz_name, RTE_MEMZONE_NAMESIZE, "bnxt_ctx_%s_%x_%d",
4790                  suffix, idx, bp->eth_dev->data->port_id);
4791         mz = rte_memzone_lookup(mz_name);
4792         if (!mz) {
4793                 mz = rte_memzone_reserve_aligned(mz_name,
4794                                                  mem_size,
4795                                                  SOCKET_ID_ANY,
4796                                                  RTE_MEMZONE_1GB |
4797                                                  RTE_MEMZONE_SIZE_HINT_ONLY |
4798                                                  RTE_MEMZONE_IOVA_CONTIG,
4799                                                  BNXT_PAGE_SIZE);
4800                 if (mz == NULL)
4801                         return -ENOMEM;
4802         }
4803
4804         memset(mz->addr, 0, mz->len);
4805         mz_phys_addr = mz->iova;
4806
4807         for (sz = 0, i = 0; sz < mem_size; sz += BNXT_PAGE_SIZE, i++) {
4808                 rmem->pg_arr[i] = ((char *)mz->addr) + sz;
4809                 rmem->dma_arr[i] = mz_phys_addr + sz;
4810
4811                 if (rmem->nr_pages > 1) {
4812                         if (i == rmem->nr_pages - 2 &&
4813                             (rmem->flags & BNXT_RMEM_RING_PTE_FLAG))
4814                                 valid_bits |= PTU_PTE_NEXT_TO_LAST;
4815                         else if (i == rmem->nr_pages - 1 &&
4816                                  (rmem->flags & BNXT_RMEM_RING_PTE_FLAG))
4817                                 valid_bits |= PTU_PTE_LAST;
4818
4819                         rmem->pg_tbl[i] = rte_cpu_to_le_64(rmem->dma_arr[i] |
4820                                                            valid_bits);
4821                 }
4822         }
4823
4824         rmem->mz = mz;
4825         if (rmem->vmem_size)
4826                 rmem->vmem = (void **)mz->addr;
4827         rmem->dma_arr[0] = mz_phys_addr;
4828         return 0;
4829 }
4830
4831 static void bnxt_free_ctx_mem(struct bnxt *bp)
4832 {
4833         int i;
4834
4835         if (!bp->ctx || !(bp->ctx->flags & BNXT_CTX_FLAG_INITED))
4836                 return;
4837
4838         bp->ctx->flags &= ~BNXT_CTX_FLAG_INITED;
4839         rte_memzone_free(bp->ctx->qp_mem.ring_mem.mz);
4840         rte_memzone_free(bp->ctx->srq_mem.ring_mem.mz);
4841         rte_memzone_free(bp->ctx->cq_mem.ring_mem.mz);
4842         rte_memzone_free(bp->ctx->vnic_mem.ring_mem.mz);
4843         rte_memzone_free(bp->ctx->stat_mem.ring_mem.mz);
4844         rte_memzone_free(bp->ctx->qp_mem.ring_mem.pg_tbl_mz);
4845         rte_memzone_free(bp->ctx->srq_mem.ring_mem.pg_tbl_mz);
4846         rte_memzone_free(bp->ctx->cq_mem.ring_mem.pg_tbl_mz);
4847         rte_memzone_free(bp->ctx->vnic_mem.ring_mem.pg_tbl_mz);
4848         rte_memzone_free(bp->ctx->stat_mem.ring_mem.pg_tbl_mz);
4849
4850         for (i = 0; i < bp->ctx->tqm_fp_rings_count + 1; i++) {
4851                 if (bp->ctx->tqm_mem[i])
4852                         rte_memzone_free(bp->ctx->tqm_mem[i]->ring_mem.mz);
4853         }
4854
4855         rte_free(bp->ctx);
4856         bp->ctx = NULL;
4857 }
4858
4859 #define bnxt_roundup(x, y)   ((((x) + ((y) - 1)) / (y)) * (y))
4860
4861 #define min_t(type, x, y) ({                    \
4862         type __min1 = (x);                      \
4863         type __min2 = (y);                      \
4864         __min1 < __min2 ? __min1 : __min2; })
4865
4866 #define max_t(type, x, y) ({                    \
4867         type __max1 = (x);                      \
4868         type __max2 = (y);                      \
4869         __max1 > __max2 ? __max1 : __max2; })
4870
4871 #define clamp_t(type, _x, min, max)     min_t(type, max_t(type, _x, min), max)
4872
4873 int bnxt_alloc_ctx_mem(struct bnxt *bp)
4874 {
4875         struct bnxt_ctx_pg_info *ctx_pg;
4876         struct bnxt_ctx_mem_info *ctx;
4877         uint32_t mem_size, ena, entries;
4878         uint32_t entries_sp, min;
4879         int i, rc;
4880
4881         rc = bnxt_hwrm_func_backing_store_qcaps(bp);
4882         if (rc) {
4883                 PMD_DRV_LOG(ERR, "Query context mem capability failed\n");
4884                 return rc;
4885         }
4886         ctx = bp->ctx;
4887         if (!ctx || (ctx->flags & BNXT_CTX_FLAG_INITED))
4888                 return 0;
4889
4890         ctx_pg = &ctx->qp_mem;
4891         ctx_pg->entries = ctx->qp_min_qp1_entries + ctx->qp_max_l2_entries;
4892         mem_size = ctx->qp_entry_size * ctx_pg->entries;
4893         rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "qp_mem", 0);
4894         if (rc)
4895                 return rc;
4896
4897         ctx_pg = &ctx->srq_mem;
4898         ctx_pg->entries = ctx->srq_max_l2_entries;
4899         mem_size = ctx->srq_entry_size * ctx_pg->entries;
4900         rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "srq_mem", 0);
4901         if (rc)
4902                 return rc;
4903
4904         ctx_pg = &ctx->cq_mem;
4905         ctx_pg->entries = ctx->cq_max_l2_entries;
4906         mem_size = ctx->cq_entry_size * ctx_pg->entries;
4907         rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "cq_mem", 0);
4908         if (rc)
4909                 return rc;
4910
4911         ctx_pg = &ctx->vnic_mem;
4912         ctx_pg->entries = ctx->vnic_max_vnic_entries +
4913                 ctx->vnic_max_ring_table_entries;
4914         mem_size = ctx->vnic_entry_size * ctx_pg->entries;
4915         rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "vnic_mem", 0);
4916         if (rc)
4917                 return rc;
4918
4919         ctx_pg = &ctx->stat_mem;
4920         ctx_pg->entries = ctx->stat_max_entries;
4921         mem_size = ctx->stat_entry_size * ctx_pg->entries;
4922         rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "stat_mem", 0);
4923         if (rc)
4924                 return rc;
4925
4926         min = ctx->tqm_min_entries_per_ring;
4927
4928         entries_sp = ctx->qp_max_l2_entries +
4929                      ctx->vnic_max_vnic_entries +
4930                      2 * ctx->qp_min_qp1_entries + min;
4931         entries_sp = bnxt_roundup(entries_sp, ctx->tqm_entries_multiple);
4932
4933         entries = ctx->qp_max_l2_entries + ctx->qp_min_qp1_entries;
4934         entries = bnxt_roundup(entries, ctx->tqm_entries_multiple);
4935         entries = clamp_t(uint32_t, entries, min,
4936                           ctx->tqm_max_entries_per_ring);
4937         for (i = 0, ena = 0; i < ctx->tqm_fp_rings_count + 1; i++) {
4938                 ctx_pg = ctx->tqm_mem[i];
4939                 ctx_pg->entries = i ? entries : entries_sp;
4940                 mem_size = ctx->tqm_entry_size * ctx_pg->entries;
4941                 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "tqm_mem", i);
4942                 if (rc)
4943                         return rc;
4944                 ena |= HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_SP << i;
4945         }
4946
4947         ena |= FUNC_BACKING_STORE_CFG_INPUT_DFLT_ENABLES;
4948         rc = bnxt_hwrm_func_backing_store_cfg(bp, ena);
4949         if (rc)
4950                 PMD_DRV_LOG(ERR,
4951                             "Failed to configure context mem: rc = %d\n", rc);
4952         else
4953                 ctx->flags |= BNXT_CTX_FLAG_INITED;
4954
4955         return rc;
4956 }
4957
4958 static int bnxt_alloc_stats_mem(struct bnxt *bp)
4959 {
4960         struct rte_pci_device *pci_dev = bp->pdev;
4961         char mz_name[RTE_MEMZONE_NAMESIZE];
4962         const struct rte_memzone *mz = NULL;
4963         uint32_t total_alloc_len;
4964         rte_iova_t mz_phys_addr;
4965
4966         if (pci_dev->id.device_id == BROADCOM_DEV_ID_NS2)
4967                 return 0;
4968
4969         snprintf(mz_name, RTE_MEMZONE_NAMESIZE,
4970                  "bnxt_" PCI_PRI_FMT "-%s", pci_dev->addr.domain,
4971                  pci_dev->addr.bus, pci_dev->addr.devid,
4972                  pci_dev->addr.function, "rx_port_stats");
4973         mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0;
4974         mz = rte_memzone_lookup(mz_name);
4975         total_alloc_len =
4976                 RTE_CACHE_LINE_ROUNDUP(sizeof(struct rx_port_stats) +
4977                                        sizeof(struct rx_port_stats_ext) + 512);
4978         if (!mz) {
4979                 mz = rte_memzone_reserve(mz_name, total_alloc_len,
4980                                          SOCKET_ID_ANY,
4981                                          RTE_MEMZONE_2MB |
4982                                          RTE_MEMZONE_SIZE_HINT_ONLY |
4983                                          RTE_MEMZONE_IOVA_CONTIG);
4984                 if (mz == NULL)
4985                         return -ENOMEM;
4986         }
4987         memset(mz->addr, 0, mz->len);
4988         mz_phys_addr = mz->iova;
4989
4990         bp->rx_mem_zone = (const void *)mz;
4991         bp->hw_rx_port_stats = mz->addr;
4992         bp->hw_rx_port_stats_map = mz_phys_addr;
4993
4994         snprintf(mz_name, RTE_MEMZONE_NAMESIZE,
4995                  "bnxt_" PCI_PRI_FMT "-%s", pci_dev->addr.domain,
4996                  pci_dev->addr.bus, pci_dev->addr.devid,
4997                  pci_dev->addr.function, "tx_port_stats");
4998         mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0;
4999         mz = rte_memzone_lookup(mz_name);
5000         total_alloc_len =
5001                 RTE_CACHE_LINE_ROUNDUP(sizeof(struct tx_port_stats) +
5002                                        sizeof(struct tx_port_stats_ext) + 512);
5003         if (!mz) {
5004                 mz = rte_memzone_reserve(mz_name,
5005                                          total_alloc_len,
5006                                          SOCKET_ID_ANY,
5007                                          RTE_MEMZONE_2MB |
5008                                          RTE_MEMZONE_SIZE_HINT_ONLY |
5009                                          RTE_MEMZONE_IOVA_CONTIG);
5010                 if (mz == NULL)
5011                         return -ENOMEM;
5012         }
5013         memset(mz->addr, 0, mz->len);
5014         mz_phys_addr = mz->iova;
5015
5016         bp->tx_mem_zone = (const void *)mz;
5017         bp->hw_tx_port_stats = mz->addr;
5018         bp->hw_tx_port_stats_map = mz_phys_addr;
5019         bp->flags |= BNXT_FLAG_PORT_STATS;
5020
5021         /* Display extended statistics if FW supports it */
5022         if (bp->hwrm_spec_code < HWRM_SPEC_CODE_1_8_4 ||
5023             bp->hwrm_spec_code == HWRM_SPEC_CODE_1_9_0 ||
5024             !(bp->flags & BNXT_FLAG_EXT_STATS_SUPPORTED))
5025                 return 0;
5026
5027         bp->hw_rx_port_stats_ext = (void *)
5028                 ((uint8_t *)bp->hw_rx_port_stats +
5029                  sizeof(struct rx_port_stats));
5030         bp->hw_rx_port_stats_ext_map = bp->hw_rx_port_stats_map +
5031                 sizeof(struct rx_port_stats);
5032         bp->flags |= BNXT_FLAG_EXT_RX_PORT_STATS;
5033
5034         if (bp->hwrm_spec_code < HWRM_SPEC_CODE_1_9_2 ||
5035             bp->flags & BNXT_FLAG_EXT_STATS_SUPPORTED) {
5036                 bp->hw_tx_port_stats_ext = (void *)
5037                         ((uint8_t *)bp->hw_tx_port_stats +
5038                          sizeof(struct tx_port_stats));
5039                 bp->hw_tx_port_stats_ext_map =
5040                         bp->hw_tx_port_stats_map +
5041                         sizeof(struct tx_port_stats);
5042                 bp->flags |= BNXT_FLAG_EXT_TX_PORT_STATS;
5043         }
5044
5045         return 0;
5046 }
5047
5048 static int bnxt_setup_mac_addr(struct rte_eth_dev *eth_dev)
5049 {
5050         struct bnxt *bp = eth_dev->data->dev_private;
5051         int rc = 0;
5052
5053         eth_dev->data->mac_addrs = rte_zmalloc("bnxt_mac_addr_tbl",
5054                                                RTE_ETHER_ADDR_LEN *
5055                                                bp->max_l2_ctx,
5056                                                0);
5057         if (eth_dev->data->mac_addrs == NULL) {
5058                 PMD_DRV_LOG(ERR, "Failed to alloc MAC addr tbl\n");
5059                 return -ENOMEM;
5060         }
5061
5062         if (!BNXT_HAS_DFLT_MAC_SET(bp)) {
5063                 if (BNXT_PF(bp))
5064                         return -EINVAL;
5065
5066                 /* Generate a random MAC address, if none was assigned by PF */
5067                 PMD_DRV_LOG(INFO, "VF MAC address not assigned by Host PF\n");
5068                 bnxt_eth_hw_addr_random(bp->mac_addr);
5069                 PMD_DRV_LOG(INFO,
5070                             "Assign random MAC:%02X:%02X:%02X:%02X:%02X:%02X\n",
5071                             bp->mac_addr[0], bp->mac_addr[1], bp->mac_addr[2],
5072                             bp->mac_addr[3], bp->mac_addr[4], bp->mac_addr[5]);
5073
5074                 rc = bnxt_hwrm_set_mac(bp);
5075                 if (rc)
5076                         return rc;
5077         }
5078
5079         /* Copy the permanent MAC from the FUNC_QCAPS response */
5080         memcpy(&eth_dev->data->mac_addrs[0], bp->mac_addr, RTE_ETHER_ADDR_LEN);
5081
5082         return rc;
5083 }
5084
5085 static int bnxt_restore_dflt_mac(struct bnxt *bp)
5086 {
5087         int rc = 0;
5088
5089         /* MAC is already configured in FW */
5090         if (BNXT_HAS_DFLT_MAC_SET(bp))
5091                 return 0;
5092
5093         /* Restore the old MAC configured */
5094         rc = bnxt_hwrm_set_mac(bp);
5095         if (rc)
5096                 PMD_DRV_LOG(ERR, "Failed to restore MAC address\n");
5097
5098         return rc;
5099 }
5100
5101 static void bnxt_config_vf_req_fwd(struct bnxt *bp)
5102 {
5103         if (!BNXT_PF(bp))
5104                 return;
5105
5106 #define ALLOW_FUNC(x)   \
5107         { \
5108                 uint32_t arg = (x); \
5109                 bp->pf->vf_req_fwd[((arg) >> 5)] &= \
5110                 ~rte_cpu_to_le_32(1 << ((arg) & 0x1f)); \
5111         }
5112
5113         /* Forward all requests if firmware is new enough */
5114         if (((bp->fw_ver >= ((20 << 24) | (6 << 16) | (100 << 8))) &&
5115              (bp->fw_ver < ((20 << 24) | (7 << 16)))) ||
5116             ((bp->fw_ver >= ((20 << 24) | (8 << 16))))) {
5117                 memset(bp->pf->vf_req_fwd, 0xff, sizeof(bp->pf->vf_req_fwd));
5118         } else {
5119                 PMD_DRV_LOG(WARNING,
5120                             "Firmware too old for VF mailbox functionality\n");
5121                 memset(bp->pf->vf_req_fwd, 0, sizeof(bp->pf->vf_req_fwd));
5122         }
5123
5124         /*
5125          * The following are used for driver cleanup. If we disallow these,
5126          * VF drivers can't clean up cleanly.
5127          */
5128         ALLOW_FUNC(HWRM_FUNC_DRV_UNRGTR);
5129         ALLOW_FUNC(HWRM_VNIC_FREE);
5130         ALLOW_FUNC(HWRM_RING_FREE);
5131         ALLOW_FUNC(HWRM_RING_GRP_FREE);
5132         ALLOW_FUNC(HWRM_VNIC_RSS_COS_LB_CTX_FREE);
5133         ALLOW_FUNC(HWRM_CFA_L2_FILTER_FREE);
5134         ALLOW_FUNC(HWRM_STAT_CTX_FREE);
5135         ALLOW_FUNC(HWRM_PORT_PHY_QCFG);
5136         ALLOW_FUNC(HWRM_VNIC_TPA_CFG);
5137 }
5138
5139 uint16_t
5140 bnxt_get_svif(uint16_t port_id, bool func_svif,
5141               enum bnxt_ulp_intf_type type)
5142 {
5143         struct rte_eth_dev *eth_dev;
5144         struct bnxt *bp;
5145
5146         eth_dev = &rte_eth_devices[port_id];
5147         if (BNXT_ETH_DEV_IS_REPRESENTOR(eth_dev)) {
5148                 struct bnxt_vf_representor *vfr = eth_dev->data->dev_private;
5149                 if (!vfr)
5150                         return 0;
5151
5152                 if (type == BNXT_ULP_INTF_TYPE_VF_REP)
5153                         return vfr->svif;
5154
5155                 eth_dev = vfr->parent_dev;
5156         }
5157
5158         bp = eth_dev->data->dev_private;
5159
5160         return func_svif ? bp->func_svif : bp->port_svif;
5161 }
5162
5163 uint16_t
5164 bnxt_get_vnic_id(uint16_t port, enum bnxt_ulp_intf_type type)
5165 {
5166         struct rte_eth_dev *eth_dev;
5167         struct bnxt_vnic_info *vnic;
5168         struct bnxt *bp;
5169
5170         eth_dev = &rte_eth_devices[port];
5171         if (BNXT_ETH_DEV_IS_REPRESENTOR(eth_dev)) {
5172                 struct bnxt_vf_representor *vfr = eth_dev->data->dev_private;
5173                 if (!vfr)
5174                         return 0;
5175
5176                 if (type == BNXT_ULP_INTF_TYPE_VF_REP)
5177                         return vfr->dflt_vnic_id;
5178
5179                 eth_dev = vfr->parent_dev;
5180         }
5181
5182         bp = eth_dev->data->dev_private;
5183
5184         vnic = BNXT_GET_DEFAULT_VNIC(bp);
5185
5186         return vnic->fw_vnic_id;
5187 }
5188
5189 uint16_t
5190 bnxt_get_fw_func_id(uint16_t port, enum bnxt_ulp_intf_type type)
5191 {
5192         struct rte_eth_dev *eth_dev;
5193         struct bnxt *bp;
5194
5195         eth_dev = &rte_eth_devices[port];
5196         if (BNXT_ETH_DEV_IS_REPRESENTOR(eth_dev)) {
5197                 struct bnxt_vf_representor *vfr = eth_dev->data->dev_private;
5198                 if (!vfr)
5199                         return 0;
5200
5201                 if (type == BNXT_ULP_INTF_TYPE_VF_REP)
5202                         return vfr->fw_fid;
5203
5204                 eth_dev = vfr->parent_dev;
5205         }
5206
5207         bp = eth_dev->data->dev_private;
5208
5209         return bp->fw_fid;
5210 }
5211
5212 enum bnxt_ulp_intf_type
5213 bnxt_get_interface_type(uint16_t port)
5214 {
5215         struct rte_eth_dev *eth_dev;
5216         struct bnxt *bp;
5217
5218         eth_dev = &rte_eth_devices[port];
5219         if (BNXT_ETH_DEV_IS_REPRESENTOR(eth_dev))
5220                 return BNXT_ULP_INTF_TYPE_VF_REP;
5221
5222         bp = eth_dev->data->dev_private;
5223         if (BNXT_PF(bp))
5224                 return BNXT_ULP_INTF_TYPE_PF;
5225         else if (BNXT_VF_IS_TRUSTED(bp))
5226                 return BNXT_ULP_INTF_TYPE_TRUSTED_VF;
5227         else if (BNXT_VF(bp))
5228                 return BNXT_ULP_INTF_TYPE_VF;
5229
5230         return BNXT_ULP_INTF_TYPE_INVALID;
5231 }
5232
5233 uint16_t
5234 bnxt_get_phy_port_id(uint16_t port_id)
5235 {
5236         struct bnxt_vf_representor *vfr;
5237         struct rte_eth_dev *eth_dev;
5238         struct bnxt *bp;
5239
5240         eth_dev = &rte_eth_devices[port_id];
5241         if (BNXT_ETH_DEV_IS_REPRESENTOR(eth_dev)) {
5242                 vfr = eth_dev->data->dev_private;
5243                 if (!vfr)
5244                         return 0;
5245
5246                 eth_dev = vfr->parent_dev;
5247         }
5248
5249         bp = eth_dev->data->dev_private;
5250
5251         return BNXT_PF(bp) ? bp->pf->port_id : bp->parent->port_id;
5252 }
5253
5254 uint16_t
5255 bnxt_get_parif(uint16_t port_id, enum bnxt_ulp_intf_type type)
5256 {
5257         struct rte_eth_dev *eth_dev;
5258         struct bnxt *bp;
5259
5260         eth_dev = &rte_eth_devices[port_id];
5261         if (BNXT_ETH_DEV_IS_REPRESENTOR(eth_dev)) {
5262                 struct bnxt_vf_representor *vfr = eth_dev->data->dev_private;
5263                 if (!vfr)
5264                         return 0;
5265
5266                 if (type == BNXT_ULP_INTF_TYPE_VF_REP)
5267                         return vfr->fw_fid - 1;
5268
5269                 eth_dev = vfr->parent_dev;
5270         }
5271
5272         bp = eth_dev->data->dev_private;
5273
5274         return BNXT_PF(bp) ? bp->fw_fid - 1 : bp->parent->fid - 1;
5275 }
5276
5277 uint16_t
5278 bnxt_get_vport(uint16_t port_id)
5279 {
5280         return (1 << bnxt_get_phy_port_id(port_id));
5281 }
5282
5283 static void bnxt_alloc_error_recovery_info(struct bnxt *bp)
5284 {
5285         struct bnxt_error_recovery_info *info = bp->recovery_info;
5286
5287         if (info) {
5288                 if (!(bp->fw_cap & BNXT_FW_CAP_HCOMM_FW_STATUS))
5289                         memset(info, 0, sizeof(*info));
5290                 return;
5291         }
5292
5293         if (!(bp->fw_cap & BNXT_FW_CAP_ERROR_RECOVERY))
5294                 return;
5295
5296         info = rte_zmalloc("bnxt_hwrm_error_recovery_qcfg",
5297                            sizeof(*info), 0);
5298         if (!info)
5299                 bp->fw_cap &= ~BNXT_FW_CAP_ERROR_RECOVERY;
5300
5301         bp->recovery_info = info;
5302 }
5303
5304 static void bnxt_check_fw_status(struct bnxt *bp)
5305 {
5306         uint32_t fw_status;
5307
5308         if (!(bp->recovery_info &&
5309               (bp->fw_cap & BNXT_FW_CAP_HCOMM_FW_STATUS)))
5310                 return;
5311
5312         fw_status = bnxt_read_fw_status_reg(bp, BNXT_FW_STATUS_REG);
5313         if (fw_status != BNXT_FW_STATUS_HEALTHY)
5314                 PMD_DRV_LOG(ERR, "Firmware not responding, status: %#x\n",
5315                             fw_status);
5316 }
5317
5318 static int bnxt_map_hcomm_fw_status_reg(struct bnxt *bp)
5319 {
5320         struct bnxt_error_recovery_info *info = bp->recovery_info;
5321         uint32_t status_loc;
5322         uint32_t sig_ver;
5323
5324         rte_write32(HCOMM_STATUS_STRUCT_LOC, (uint8_t *)bp->bar0 +
5325                     BNXT_GRCPF_REG_WINDOW_BASE_OUT + 4);
5326         sig_ver = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
5327                                    BNXT_GRCP_WINDOW_2_BASE +
5328                                    offsetof(struct hcomm_status,
5329                                             sig_ver)));
5330         /* If the signature is absent, then FW does not support this feature */
5331         if ((sig_ver & HCOMM_STATUS_SIGNATURE_MASK) !=
5332             HCOMM_STATUS_SIGNATURE_VAL)
5333                 return 0;
5334
5335         if (!info) {
5336                 info = rte_zmalloc("bnxt_hwrm_error_recovery_qcfg",
5337                                    sizeof(*info), 0);
5338                 if (!info)
5339                         return -ENOMEM;
5340                 bp->recovery_info = info;
5341         } else {
5342                 memset(info, 0, sizeof(*info));
5343         }
5344
5345         status_loc = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
5346                                       BNXT_GRCP_WINDOW_2_BASE +
5347                                       offsetof(struct hcomm_status,
5348                                                fw_status_loc)));
5349
5350         /* Only pre-map the FW health status GRC register */
5351         if (BNXT_FW_STATUS_REG_TYPE(status_loc) != BNXT_FW_STATUS_REG_TYPE_GRC)
5352                 return 0;
5353
5354         info->status_regs[BNXT_FW_STATUS_REG] = status_loc;
5355         info->mapped_status_regs[BNXT_FW_STATUS_REG] =
5356                 BNXT_GRCP_WINDOW_2_BASE + (status_loc & BNXT_GRCP_OFFSET_MASK);
5357
5358         rte_write32((status_loc & BNXT_GRCP_BASE_MASK), (uint8_t *)bp->bar0 +
5359                     BNXT_GRCPF_REG_WINDOW_BASE_OUT + 4);
5360
5361         bp->fw_cap |= BNXT_FW_CAP_HCOMM_FW_STATUS;
5362
5363         return 0;
5364 }
5365
5366 static int bnxt_init_fw(struct bnxt *bp)
5367 {
5368         uint16_t mtu;
5369         int rc = 0;
5370
5371         bp->fw_cap = 0;
5372
5373         rc = bnxt_map_hcomm_fw_status_reg(bp);
5374         if (rc)
5375                 return rc;
5376
5377         rc = bnxt_hwrm_ver_get(bp, DFLT_HWRM_CMD_TIMEOUT);
5378         if (rc) {
5379                 bnxt_check_fw_status(bp);
5380                 return rc;
5381         }
5382
5383         rc = bnxt_hwrm_func_reset(bp);
5384         if (rc)
5385                 return -EIO;
5386
5387         rc = bnxt_hwrm_vnic_qcaps(bp);
5388         if (rc)
5389                 return rc;
5390
5391         rc = bnxt_hwrm_queue_qportcfg(bp);
5392         if (rc)
5393                 return rc;
5394
5395         /* Get the MAX capabilities for this function.
5396          * This function also allocates context memory for TQM rings and
5397          * informs the firmware about this allocated backing store memory.
5398          */
5399         rc = bnxt_hwrm_func_qcaps(bp);
5400         if (rc)
5401                 return rc;
5402
5403         rc = bnxt_hwrm_func_qcfg(bp, &mtu);
5404         if (rc)
5405                 return rc;
5406
5407         bnxt_hwrm_port_mac_qcfg(bp);
5408
5409         bnxt_hwrm_parent_pf_qcfg(bp);
5410
5411         bnxt_hwrm_port_phy_qcaps(bp);
5412
5413         bnxt_alloc_error_recovery_info(bp);
5414         /* Get the adapter error recovery support info */
5415         rc = bnxt_hwrm_error_recovery_qcfg(bp);
5416         if (rc)
5417                 bp->fw_cap &= ~BNXT_FW_CAP_ERROR_RECOVERY;
5418
5419         bnxt_hwrm_port_led_qcaps(bp);
5420
5421         return 0;
5422 }
5423
5424 static int
5425 bnxt_init_locks(struct bnxt *bp)
5426 {
5427         int err;
5428
5429         err = pthread_mutex_init(&bp->flow_lock, NULL);
5430         if (err) {
5431                 PMD_DRV_LOG(ERR, "Unable to initialize flow_lock\n");
5432                 return err;
5433         }
5434
5435         err = pthread_mutex_init(&bp->def_cp_lock, NULL);
5436         if (err)
5437                 PMD_DRV_LOG(ERR, "Unable to initialize def_cp_lock\n");
5438         return err;
5439 }
5440
5441 static int bnxt_init_resources(struct bnxt *bp, bool reconfig_dev)
5442 {
5443         int rc = 0;
5444
5445         rc = bnxt_init_fw(bp);
5446         if (rc)
5447                 return rc;
5448
5449         if (!reconfig_dev) {
5450                 rc = bnxt_setup_mac_addr(bp->eth_dev);
5451                 if (rc)
5452                         return rc;
5453         } else {
5454                 rc = bnxt_restore_dflt_mac(bp);
5455                 if (rc)
5456                         return rc;
5457         }
5458
5459         bnxt_config_vf_req_fwd(bp);
5460
5461         rc = bnxt_hwrm_func_driver_register(bp);
5462         if (rc) {
5463                 PMD_DRV_LOG(ERR, "Failed to register driver");
5464                 return -EBUSY;
5465         }
5466
5467         if (BNXT_PF(bp)) {
5468                 if (bp->pdev->max_vfs) {
5469                         rc = bnxt_hwrm_allocate_vfs(bp, bp->pdev->max_vfs);
5470                         if (rc) {
5471                                 PMD_DRV_LOG(ERR, "Failed to allocate VFs\n");
5472                                 return rc;
5473                         }
5474                 } else {
5475                         rc = bnxt_hwrm_allocate_pf_only(bp);
5476                         if (rc) {
5477                                 PMD_DRV_LOG(ERR,
5478                                             "Failed to allocate PF resources");
5479                                 return rc;
5480                         }
5481                 }
5482         }
5483
5484         rc = bnxt_alloc_mem(bp, reconfig_dev);
5485         if (rc)
5486                 return rc;
5487
5488         rc = bnxt_setup_int(bp);
5489         if (rc)
5490                 return rc;
5491
5492         rc = bnxt_request_int(bp);
5493         if (rc)
5494                 return rc;
5495
5496         rc = bnxt_init_ctx_mem(bp);
5497         if (rc) {
5498                 PMD_DRV_LOG(ERR, "Failed to init adv_flow_counters\n");
5499                 return rc;
5500         }
5501
5502         rc = bnxt_init_locks(bp);
5503         if (rc)
5504                 return rc;
5505
5506         return 0;
5507 }
5508
5509 static int
5510 bnxt_parse_devarg_truflow(__rte_unused const char *key,
5511                           const char *value, void *opaque_arg)
5512 {
5513         struct bnxt *bp = opaque_arg;
5514         unsigned long truflow;
5515         char *end = NULL;
5516
5517         if (!value || !opaque_arg) {
5518                 PMD_DRV_LOG(ERR,
5519                             "Invalid parameter passed to truflow devargs.\n");
5520                 return -EINVAL;
5521         }
5522
5523         truflow = strtoul(value, &end, 10);
5524         if (end == NULL || *end != '\0' ||
5525             (truflow == ULONG_MAX && errno == ERANGE)) {
5526                 PMD_DRV_LOG(ERR,
5527                             "Invalid parameter passed to truflow devargs.\n");
5528                 return -EINVAL;
5529         }
5530
5531         if (BNXT_DEVARG_TRUFLOW_INVALID(truflow)) {
5532                 PMD_DRV_LOG(ERR,
5533                             "Invalid value passed to truflow devargs.\n");
5534                 return -EINVAL;
5535         }
5536
5537         bp->flags |= BNXT_FLAG_TRUFLOW_EN;
5538         if (BNXT_TRUFLOW_EN(bp))
5539                 PMD_DRV_LOG(INFO, "Host-based truflow feature enabled.\n");
5540
5541         return 0;
5542 }
5543
5544 static int
5545 bnxt_parse_devarg_flow_xstat(__rte_unused const char *key,
5546                              const char *value, void *opaque_arg)
5547 {
5548         struct bnxt *bp = opaque_arg;
5549         unsigned long flow_xstat;
5550         char *end = NULL;
5551
5552         if (!value || !opaque_arg) {
5553                 PMD_DRV_LOG(ERR,
5554                             "Invalid parameter passed to flow_xstat devarg.\n");
5555                 return -EINVAL;
5556         }
5557
5558         flow_xstat = strtoul(value, &end, 10);
5559         if (end == NULL || *end != '\0' ||
5560             (flow_xstat == ULONG_MAX && errno == ERANGE)) {
5561                 PMD_DRV_LOG(ERR,
5562                             "Invalid parameter passed to flow_xstat devarg.\n");
5563                 return -EINVAL;
5564         }
5565
5566         if (BNXT_DEVARG_FLOW_XSTAT_INVALID(flow_xstat)) {
5567                 PMD_DRV_LOG(ERR,
5568                             "Invalid value passed to flow_xstat devarg.\n");
5569                 return -EINVAL;
5570         }
5571
5572         bp->flags |= BNXT_FLAG_FLOW_XSTATS_EN;
5573         if (BNXT_FLOW_XSTATS_EN(bp))
5574                 PMD_DRV_LOG(INFO, "flow_xstat feature enabled.\n");
5575
5576         return 0;
5577 }
5578
5579 static int
5580 bnxt_parse_devarg_max_num_kflows(__rte_unused const char *key,
5581                                         const char *value, void *opaque_arg)
5582 {
5583         struct bnxt *bp = opaque_arg;
5584         unsigned long max_num_kflows;
5585         char *end = NULL;
5586
5587         if (!value || !opaque_arg) {
5588                 PMD_DRV_LOG(ERR,
5589                         "Invalid parameter passed to max_num_kflows devarg.\n");
5590                 return -EINVAL;
5591         }
5592
5593         max_num_kflows = strtoul(value, &end, 10);
5594         if (end == NULL || *end != '\0' ||
5595                 (max_num_kflows == ULONG_MAX && errno == ERANGE)) {
5596                 PMD_DRV_LOG(ERR,
5597                         "Invalid parameter passed to max_num_kflows devarg.\n");
5598                 return -EINVAL;
5599         }
5600
5601         if (bnxt_devarg_max_num_kflow_invalid(max_num_kflows)) {
5602                 PMD_DRV_LOG(ERR,
5603                         "Invalid value passed to max_num_kflows devarg.\n");
5604                 return -EINVAL;
5605         }
5606
5607         bp->max_num_kflows = max_num_kflows;
5608         if (bp->max_num_kflows)
5609                 PMD_DRV_LOG(INFO, "max_num_kflows set as %ldK.\n",
5610                                 max_num_kflows);
5611
5612         return 0;
5613 }
5614
5615 static void
5616 bnxt_parse_dev_args(struct bnxt *bp, struct rte_devargs *devargs)
5617 {
5618         struct rte_kvargs *kvlist;
5619
5620         if (devargs == NULL)
5621                 return;
5622
5623         kvlist = rte_kvargs_parse(devargs->args, bnxt_dev_args);
5624         if (kvlist == NULL)
5625                 return;
5626
5627         /*
5628          * Handler for "truflow" devarg.
5629          * Invoked as for ex: "-w 0000:00:0d.0,host-based-truflow=1"
5630          */
5631         rte_kvargs_process(kvlist, BNXT_DEVARG_TRUFLOW,
5632                            bnxt_parse_devarg_truflow, bp);
5633
5634         /*
5635          * Handler for "flow_xstat" devarg.
5636          * Invoked as for ex: "-w 0000:00:0d.0,flow_xstat=1"
5637          */
5638         rte_kvargs_process(kvlist, BNXT_DEVARG_FLOW_XSTAT,
5639                            bnxt_parse_devarg_flow_xstat, bp);
5640
5641         /*
5642          * Handler for "max_num_kflows" devarg.
5643          * Invoked as for ex: "-w 000:00:0d.0,max_num_kflows=32"
5644          */
5645         rte_kvargs_process(kvlist, BNXT_DEVARG_MAX_NUM_KFLOWS,
5646                            bnxt_parse_devarg_max_num_kflows, bp);
5647
5648         rte_kvargs_free(kvlist);
5649 }
5650
5651 static int bnxt_alloc_switch_domain(struct bnxt *bp)
5652 {
5653         int rc = 0;
5654
5655         if (BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp)) {
5656                 rc = rte_eth_switch_domain_alloc(&bp->switch_domain_id);
5657                 if (rc)
5658                         PMD_DRV_LOG(ERR,
5659                                     "Failed to alloc switch domain: %d\n", rc);
5660                 else
5661                         PMD_DRV_LOG(INFO,
5662                                     "Switch domain allocated %d\n",
5663                                     bp->switch_domain_id);
5664         }
5665
5666         return rc;
5667 }
5668
5669 static int
5670 bnxt_dev_init(struct rte_eth_dev *eth_dev, void *params __rte_unused)
5671 {
5672         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
5673         static int version_printed;
5674         struct bnxt *bp;
5675         int rc;
5676
5677         if (version_printed++ == 0)
5678                 PMD_DRV_LOG(INFO, "%s\n", bnxt_version);
5679
5680         eth_dev->dev_ops = &bnxt_dev_ops;
5681         eth_dev->rx_queue_count = bnxt_rx_queue_count_op;
5682         eth_dev->rx_descriptor_status = bnxt_rx_descriptor_status_op;
5683         eth_dev->tx_descriptor_status = bnxt_tx_descriptor_status_op;
5684         eth_dev->rx_pkt_burst = &bnxt_recv_pkts;
5685         eth_dev->tx_pkt_burst = &bnxt_xmit_pkts;
5686
5687         /*
5688          * For secondary processes, we don't initialise any further
5689          * as primary has already done this work.
5690          */
5691         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
5692                 return 0;
5693
5694         rte_eth_copy_pci_info(eth_dev, pci_dev);
5695
5696         bp = eth_dev->data->dev_private;
5697
5698         /* Parse dev arguments passed on when starting the DPDK application. */
5699         bnxt_parse_dev_args(bp, pci_dev->device.devargs);
5700
5701         bp->flags &= ~BNXT_FLAG_RX_VECTOR_PKT_MODE;
5702
5703         if (bnxt_vf_pciid(pci_dev->id.device_id))
5704                 bp->flags |= BNXT_FLAG_VF;
5705
5706         if (bnxt_thor_device(pci_dev->id.device_id))
5707                 bp->flags |= BNXT_FLAG_THOR_CHIP;
5708
5709         if (pci_dev->id.device_id == BROADCOM_DEV_ID_58802 ||
5710             pci_dev->id.device_id == BROADCOM_DEV_ID_58804 ||
5711             pci_dev->id.device_id == BROADCOM_DEV_ID_58808 ||
5712             pci_dev->id.device_id == BROADCOM_DEV_ID_58802_VF)
5713                 bp->flags |= BNXT_FLAG_STINGRAY;
5714
5715         rc = bnxt_init_board(eth_dev);
5716         if (rc) {
5717                 PMD_DRV_LOG(ERR,
5718                             "Failed to initialize board rc: %x\n", rc);
5719                 return rc;
5720         }
5721
5722         rc = bnxt_alloc_pf_info(bp);
5723         if (rc)
5724                 goto error_free;
5725
5726         rc = bnxt_alloc_link_info(bp);
5727         if (rc)
5728                 goto error_free;
5729
5730         rc = bnxt_alloc_parent_info(bp);
5731         if (rc)
5732                 goto error_free;
5733
5734         rc = bnxt_alloc_hwrm_resources(bp);
5735         if (rc) {
5736                 PMD_DRV_LOG(ERR,
5737                             "Failed to allocate hwrm resource rc: %x\n", rc);
5738                 goto error_free;
5739         }
5740         rc = bnxt_alloc_leds_info(bp);
5741         if (rc)
5742                 goto error_free;
5743
5744         rc = bnxt_alloc_cos_queues(bp);
5745         if (rc)
5746                 goto error_free;
5747
5748         rc = bnxt_init_resources(bp, false);
5749         if (rc)
5750                 goto error_free;
5751
5752         rc = bnxt_alloc_stats_mem(bp);
5753         if (rc)
5754                 goto error_free;
5755
5756         bnxt_alloc_switch_domain(bp);
5757
5758         /* Pass the information to the rte_eth_dev_close() that it should also
5759          * release the private port resources.
5760          */
5761         eth_dev->data->dev_flags |= RTE_ETH_DEV_CLOSE_REMOVE;
5762
5763         PMD_DRV_LOG(INFO,
5764                     DRV_MODULE_NAME "found at mem %" PRIX64 ", node addr %pM\n",
5765                     pci_dev->mem_resource[0].phys_addr,
5766                     pci_dev->mem_resource[0].addr);
5767
5768         return 0;
5769
5770 error_free:
5771         bnxt_dev_uninit(eth_dev);
5772         return rc;
5773 }
5774
5775
5776 static void bnxt_free_ctx_mem_buf(struct bnxt_ctx_mem_buf_info *ctx)
5777 {
5778         if (!ctx)
5779                 return;
5780
5781         if (ctx->va)
5782                 rte_free(ctx->va);
5783
5784         ctx->va = NULL;
5785         ctx->dma = RTE_BAD_IOVA;
5786         ctx->ctx_id = BNXT_CTX_VAL_INVAL;
5787 }
5788
5789 static void bnxt_unregister_fc_ctx_mem(struct bnxt *bp)
5790 {
5791         bnxt_hwrm_cfa_counter_cfg(bp, BNXT_DIR_RX,
5792                                   CFA_COUNTER_CFG_IN_COUNTER_TYPE_FC,
5793                                   bp->flow_stat->rx_fc_out_tbl.ctx_id,
5794                                   bp->flow_stat->max_fc,
5795                                   false);
5796
5797         bnxt_hwrm_cfa_counter_cfg(bp, BNXT_DIR_TX,
5798                                   CFA_COUNTER_CFG_IN_COUNTER_TYPE_FC,
5799                                   bp->flow_stat->tx_fc_out_tbl.ctx_id,
5800                                   bp->flow_stat->max_fc,
5801                                   false);
5802
5803         if (bp->flow_stat->rx_fc_in_tbl.ctx_id != BNXT_CTX_VAL_INVAL)
5804                 bnxt_hwrm_ctx_unrgtr(bp, bp->flow_stat->rx_fc_in_tbl.ctx_id);
5805         bp->flow_stat->rx_fc_in_tbl.ctx_id = BNXT_CTX_VAL_INVAL;
5806
5807         if (bp->flow_stat->rx_fc_out_tbl.ctx_id != BNXT_CTX_VAL_INVAL)
5808                 bnxt_hwrm_ctx_unrgtr(bp, bp->flow_stat->rx_fc_out_tbl.ctx_id);
5809         bp->flow_stat->rx_fc_out_tbl.ctx_id = BNXT_CTX_VAL_INVAL;
5810
5811         if (bp->flow_stat->tx_fc_in_tbl.ctx_id != BNXT_CTX_VAL_INVAL)
5812                 bnxt_hwrm_ctx_unrgtr(bp, bp->flow_stat->tx_fc_in_tbl.ctx_id);
5813         bp->flow_stat->tx_fc_in_tbl.ctx_id = BNXT_CTX_VAL_INVAL;
5814
5815         if (bp->flow_stat->tx_fc_out_tbl.ctx_id != BNXT_CTX_VAL_INVAL)
5816                 bnxt_hwrm_ctx_unrgtr(bp, bp->flow_stat->tx_fc_out_tbl.ctx_id);
5817         bp->flow_stat->tx_fc_out_tbl.ctx_id = BNXT_CTX_VAL_INVAL;
5818 }
5819
5820 static void bnxt_uninit_fc_ctx_mem(struct bnxt *bp)
5821 {
5822         bnxt_unregister_fc_ctx_mem(bp);
5823
5824         bnxt_free_ctx_mem_buf(&bp->flow_stat->rx_fc_in_tbl);
5825         bnxt_free_ctx_mem_buf(&bp->flow_stat->rx_fc_out_tbl);
5826         bnxt_free_ctx_mem_buf(&bp->flow_stat->tx_fc_in_tbl);
5827         bnxt_free_ctx_mem_buf(&bp->flow_stat->tx_fc_out_tbl);
5828 }
5829
5830 static void bnxt_uninit_ctx_mem(struct bnxt *bp)
5831 {
5832         if (BNXT_FLOW_XSTATS_EN(bp))
5833                 bnxt_uninit_fc_ctx_mem(bp);
5834 }
5835
5836 static void
5837 bnxt_free_error_recovery_info(struct bnxt *bp)
5838 {
5839         rte_free(bp->recovery_info);
5840         bp->recovery_info = NULL;
5841         bp->fw_cap &= ~BNXT_FW_CAP_ERROR_RECOVERY;
5842 }
5843
5844 static void
5845 bnxt_uninit_locks(struct bnxt *bp)
5846 {
5847         pthread_mutex_destroy(&bp->flow_lock);
5848         pthread_mutex_destroy(&bp->def_cp_lock);
5849         if (bp->rep_info) {
5850                 pthread_mutex_destroy(&bp->rep_info->vfr_lock);
5851                 pthread_mutex_destroy(&bp->rep_info->vfr_start_lock);
5852         }
5853 }
5854
5855 static int
5856 bnxt_uninit_resources(struct bnxt *bp, bool reconfig_dev)
5857 {
5858         int rc;
5859
5860         bnxt_free_int(bp);
5861         bnxt_free_mem(bp, reconfig_dev);
5862         bnxt_hwrm_func_buf_unrgtr(bp);
5863         rc = bnxt_hwrm_func_driver_unregister(bp, 0);
5864         bp->flags &= ~BNXT_FLAG_REGISTERED;
5865         bnxt_free_ctx_mem(bp);
5866         if (!reconfig_dev) {
5867                 bnxt_free_hwrm_resources(bp);
5868                 bnxt_free_error_recovery_info(bp);
5869         }
5870
5871         bnxt_uninit_ctx_mem(bp);
5872
5873         bnxt_uninit_locks(bp);
5874         bnxt_free_flow_stats_info(bp);
5875         bnxt_free_rep_info(bp);
5876         rte_free(bp->ptp_cfg);
5877         bp->ptp_cfg = NULL;
5878         return rc;
5879 }
5880
5881 static int
5882 bnxt_dev_uninit(struct rte_eth_dev *eth_dev)
5883 {
5884         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
5885                 return -EPERM;
5886
5887         PMD_DRV_LOG(DEBUG, "Calling Device uninit\n");
5888
5889         if (eth_dev->state != RTE_ETH_DEV_UNUSED)
5890                 bnxt_dev_close_op(eth_dev);
5891
5892         return 0;
5893 }
5894
5895 static int bnxt_pci_remove_dev_with_reps(struct rte_eth_dev *eth_dev)
5896 {
5897         struct bnxt *bp = eth_dev->data->dev_private;
5898         struct rte_eth_dev *vf_rep_eth_dev;
5899         int ret = 0, i;
5900
5901         if (!bp)
5902                 return -EINVAL;
5903
5904         for (i = 0; i < bp->num_reps; i++) {
5905                 vf_rep_eth_dev = bp->rep_info[i].vfr_eth_dev;
5906                 if (!vf_rep_eth_dev)
5907                         continue;
5908                 rte_eth_dev_destroy(vf_rep_eth_dev, bnxt_vf_representor_uninit);
5909         }
5910         ret = rte_eth_dev_destroy(eth_dev, bnxt_dev_uninit);
5911
5912         return ret;
5913 }
5914
5915 static void bnxt_free_rep_info(struct bnxt *bp)
5916 {
5917         rte_free(bp->rep_info);
5918         bp->rep_info = NULL;
5919         rte_free(bp->cfa_code_map);
5920         bp->cfa_code_map = NULL;
5921 }
5922
5923 static int bnxt_init_rep_info(struct bnxt *bp)
5924 {
5925         int i = 0, rc;
5926
5927         if (bp->rep_info)
5928                 return 0;
5929
5930         bp->rep_info = rte_zmalloc("bnxt_rep_info",
5931                                    sizeof(bp->rep_info[0]) * BNXT_MAX_VF_REPS,
5932                                    0);
5933         if (!bp->rep_info) {
5934                 PMD_DRV_LOG(ERR, "Failed to alloc memory for rep info\n");
5935                 return -ENOMEM;
5936         }
5937         bp->cfa_code_map = rte_zmalloc("bnxt_cfa_code_map",
5938                                        sizeof(*bp->cfa_code_map) *
5939                                        BNXT_MAX_CFA_CODE, 0);
5940         if (!bp->cfa_code_map) {
5941                 PMD_DRV_LOG(ERR, "Failed to alloc memory for cfa_code_map\n");
5942                 bnxt_free_rep_info(bp);
5943                 return -ENOMEM;
5944         }
5945
5946         for (i = 0; i < BNXT_MAX_CFA_CODE; i++)
5947                 bp->cfa_code_map[i] = BNXT_VF_IDX_INVALID;
5948
5949         rc = pthread_mutex_init(&bp->rep_info->vfr_lock, NULL);
5950         if (rc) {
5951                 PMD_DRV_LOG(ERR, "Unable to initialize vfr_lock\n");
5952                 bnxt_free_rep_info(bp);
5953                 return rc;
5954         }
5955
5956         rc = pthread_mutex_init(&bp->rep_info->vfr_start_lock, NULL);
5957         if (rc) {
5958                 PMD_DRV_LOG(ERR, "Unable to initialize vfr_start_lock\n");
5959                 bnxt_free_rep_info(bp);
5960                 return rc;
5961         }
5962
5963         return rc;
5964 }
5965
5966 static int bnxt_rep_port_probe(struct rte_pci_device *pci_dev,
5967                                struct rte_eth_devargs eth_da,
5968                                struct rte_eth_dev *backing_eth_dev)
5969 {
5970         struct rte_eth_dev *vf_rep_eth_dev;
5971         char name[RTE_ETH_NAME_MAX_LEN];
5972         struct bnxt *backing_bp;
5973         uint16_t num_rep;
5974         int i, ret = 0;
5975
5976         num_rep = eth_da.nb_representor_ports;
5977         if (num_rep > BNXT_MAX_VF_REPS) {
5978                 PMD_DRV_LOG(ERR, "nb_representor_ports = %d > %d MAX VF REPS\n",
5979                             num_rep, BNXT_MAX_VF_REPS);
5980                 return -EINVAL;
5981         }
5982
5983         if (num_rep > RTE_MAX_ETHPORTS) {
5984                 PMD_DRV_LOG(ERR,
5985                             "nb_representor_ports = %d > %d MAX ETHPORTS\n",
5986                             num_rep, RTE_MAX_ETHPORTS);
5987                 return -EINVAL;
5988         }
5989
5990         backing_bp = backing_eth_dev->data->dev_private;
5991
5992         if (!(BNXT_PF(backing_bp) || BNXT_VF_IS_TRUSTED(backing_bp))) {
5993                 PMD_DRV_LOG(ERR,
5994                             "Not a PF or trusted VF. No Representor support\n");
5995                 /* Returning an error is not an option.
5996                  * Applications are not handling this correctly
5997                  */
5998                 return 0;
5999         }
6000
6001         if (bnxt_init_rep_info(backing_bp))
6002                 return 0;
6003
6004         for (i = 0; i < num_rep; i++) {
6005                 struct bnxt_vf_representor representor = {
6006                         .vf_id = eth_da.representor_ports[i],
6007                         .switch_domain_id = backing_bp->switch_domain_id,
6008                         .parent_dev = backing_eth_dev
6009                 };
6010
6011                 if (representor.vf_id >= BNXT_MAX_VF_REPS) {
6012                         PMD_DRV_LOG(ERR, "VF-Rep id %d >= %d MAX VF ID\n",
6013                                     representor.vf_id, BNXT_MAX_VF_REPS);
6014                         continue;
6015                 }
6016
6017                 /* representor port net_bdf_port */
6018                 snprintf(name, sizeof(name), "net_%s_representor_%d",
6019                          pci_dev->device.name, eth_da.representor_ports[i]);
6020
6021                 ret = rte_eth_dev_create(&pci_dev->device, name,
6022                                          sizeof(struct bnxt_vf_representor),
6023                                          NULL, NULL,
6024                                          bnxt_vf_representor_init,
6025                                          &representor);
6026
6027                 if (!ret) {
6028                         vf_rep_eth_dev = rte_eth_dev_allocated(name);
6029                         if (!vf_rep_eth_dev) {
6030                                 PMD_DRV_LOG(ERR, "Failed to find the eth_dev"
6031                                             " for VF-Rep: %s.", name);
6032                                 bnxt_pci_remove_dev_with_reps(backing_eth_dev);
6033                                 ret = -ENODEV;
6034                                 return ret;
6035                         }
6036                         backing_bp->rep_info[representor.vf_id].vfr_eth_dev =
6037                                 vf_rep_eth_dev;
6038                         backing_bp->num_reps++;
6039                 } else {
6040                         PMD_DRV_LOG(ERR, "failed to create bnxt vf "
6041                                     "representor %s.", name);
6042                         bnxt_pci_remove_dev_with_reps(backing_eth_dev);
6043                 }
6044         }
6045
6046         return ret;
6047 }
6048
6049 static int bnxt_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
6050                           struct rte_pci_device *pci_dev)
6051 {
6052         struct rte_eth_devargs eth_da = { .nb_representor_ports = 0 };
6053         struct rte_eth_dev *backing_eth_dev;
6054         uint16_t num_rep;
6055         int ret = 0;
6056
6057         if (pci_dev->device.devargs) {
6058                 ret = rte_eth_devargs_parse(pci_dev->device.devargs->args,
6059                                             &eth_da);
6060                 if (ret)
6061                         return ret;
6062         }
6063
6064         num_rep = eth_da.nb_representor_ports;
6065         PMD_DRV_LOG(DEBUG, "nb_representor_ports = %d\n",
6066                     num_rep);
6067
6068         /* We could come here after first level of probe is already invoked
6069          * as part of an application bringup(OVS-DPDK vswitchd), so first check
6070          * for already allocated eth_dev for the backing device (PF/Trusted VF)
6071          */
6072         backing_eth_dev = rte_eth_dev_allocated(pci_dev->device.name);
6073         if (backing_eth_dev == NULL) {
6074                 ret = rte_eth_dev_create(&pci_dev->device, pci_dev->device.name,
6075                                          sizeof(struct bnxt),
6076                                          eth_dev_pci_specific_init, pci_dev,
6077                                          bnxt_dev_init, NULL);
6078
6079                 if (ret || !num_rep)
6080                         return ret;
6081
6082                 backing_eth_dev = rte_eth_dev_allocated(pci_dev->device.name);
6083         }
6084
6085         /* probe representor ports now */
6086         ret = bnxt_rep_port_probe(pci_dev, eth_da, backing_eth_dev);
6087
6088         return ret;
6089 }
6090
6091 static int bnxt_pci_remove(struct rte_pci_device *pci_dev)
6092 {
6093         struct rte_eth_dev *eth_dev;
6094
6095         eth_dev = rte_eth_dev_allocated(pci_dev->device.name);
6096         if (!eth_dev)
6097                 return 0; /* Invoked typically only by OVS-DPDK, by the
6098                            * time it comes here the eth_dev is already
6099                            * deleted by rte_eth_dev_close(), so returning
6100                            * +ve value will at least help in proper cleanup
6101                            */
6102
6103         if (rte_eal_process_type() == RTE_PROC_PRIMARY) {
6104                 if (eth_dev->data->dev_flags & RTE_ETH_DEV_REPRESENTOR)
6105                         return rte_eth_dev_destroy(eth_dev,
6106                                                    bnxt_vf_representor_uninit);
6107                 else
6108                         return rte_eth_dev_destroy(eth_dev,
6109                                                    bnxt_dev_uninit);
6110         } else {
6111                 return rte_eth_dev_pci_generic_remove(pci_dev, NULL);
6112         }
6113 }
6114
6115 static struct rte_pci_driver bnxt_rte_pmd = {
6116         .id_table = bnxt_pci_id_map,
6117         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC |
6118                         RTE_PCI_DRV_PROBE_AGAIN, /* Needed in case of VF-REPs
6119                                                   * and OVS-DPDK
6120                                                   */
6121         .probe = bnxt_pci_probe,
6122         .remove = bnxt_pci_remove,
6123 };
6124
6125 static bool
6126 is_device_supported(struct rte_eth_dev *dev, struct rte_pci_driver *drv)
6127 {
6128         if (strcmp(dev->device->driver->name, drv->driver.name))
6129                 return false;
6130
6131         return true;
6132 }
6133
6134 bool is_bnxt_supported(struct rte_eth_dev *dev)
6135 {
6136         return is_device_supported(dev, &bnxt_rte_pmd);
6137 }
6138
6139 RTE_LOG_REGISTER(bnxt_logtype_driver, pmd.net.bnxt.driver, NOTICE);
6140 RTE_PMD_REGISTER_PCI(net_bnxt, bnxt_rte_pmd);
6141 RTE_PMD_REGISTER_PCI_TABLE(net_bnxt, bnxt_pci_id_map);
6142 RTE_PMD_REGISTER_KMOD_DEP(net_bnxt, "* igb_uio | uio_pci_generic | vfio-pci");